1995_National_Data_Acquisition_Databook 1995 National Data Acquisition Databook

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DATA ACQUISITION
DATABOOK
1995 Edition

Data Acquisition Systems
Analog-to-Digital Converters
Digital-to-Analog Converters
Voltage References
Temperature Sensors
Sample and Hold
Active Filters
Analog Switches/Multiplexers
Surface Mount
Appendices/Physical Dimensions

III

••
••
••
••
•

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Definition of Terms

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or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

iii

Table of Contents
Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional Available Linear Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Industry Package Cross Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 1 Data Acquisition Systems
Data Acquisition Systems Definition of Terms ....................................
Data Acquisition Systems Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC0851 / ADC0858 8-Bit Analog Data Acquisition and Monitoring Systems. . . . . . . . . .
LM12434/LM12 {L}438 12-Bit + Sign Data Acquisition System with Serial I/O and
Self-Calibration ............................................................
LM12454/LM12H454/LM12458/LM12H458 12-Bit + Sign Data Acquisition System
with Self-Calibration. .... . . . . . . .. . .. . .. . .... . . .. .. .. .. .. . . . . .. . ... .. . .. . . ...
LM12L454/LM12L458 12-Bit + Sign Data Acquisition System with Self-Calibration .. .
Section 2 Analog-to-Digital Converters
Analog-to-Digital Converters Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converters Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC0800 8-Bit AID Converter .................................................
ADC0801 / ADC0802/ ADC0803/ ADC0804/ ADC0805 8-Bit J-tP Compatible A/D
Converters ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC0808/ ADC0809 8-Bit J-tP Compatible AID Converters with 8-Channel Multiplexer.
ADC0811 8-Bit Serial I/O A/D Converter with 11-Channel Multiplexer .. . . . . . . . . . . . . .
ADC0816/ ADC0817 8-Bit J-tP Compatible A/D Converters with 16-Channel
Multiplexer ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC0819 8-Bit Serial I/O AID Converter with 19-Channel Multiplexer. .. . . . . . . . . . . . .
ADC0820 8-Bit High Speed J-tP Compatible AID Converter with Track/Hold Function. .
ADC0831 / ADC0832/ ADC0834 and ADC0838 8-Bit Serial I/O AID Converters with
Multiplexer Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC0833 8-Bit Serial I/O AID Converter with 4-Channel Multiplexer ................
ADC08031 / ADC08032/ ADC08034/ ADC08038 8-Bit High-Speed Serial I/O AID
Converters with Multiplexer Options, Voltage Reference, and Track/Hold Function. .
ADC08131 / ADC08134/ ADC08138 8-Bit High-Speed Serial I/O A/D Converters with
Multiplexer Options, Voltage Reference, and Track/Hold Function. . .. . . . ... ..... .
ADC08231 / ADC08234/ ADC08238 8-Bit 2 J-ts Serial I/O AID Converters with MUX,
Reference, and Track/Hold. . . . .. . ... . . . .. .. .. .. .... . . . .. . .. . .. . ... ... .. .. . ..
ADC0841 8-Bit J-tP Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC0844/ ADC0848 8-Bit J-tP Compatible AID Converters with Multiplexer Options ...
ADC0852/ ADC0854 Multiplexed Comparator with 8-Bit Reference Divider. . . . . . . . . . .
ADC08061 / ADC08062 500 ns AID Converter with S/H Function and Input
Multiplexer ................................................................
ADC08161 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference.. .
ADC1001 1O-Bit J-tP Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC1005 1O-Bit J-tP Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC1 0154, ADC1 0158 1O-Bit Plus Sign 4 J-tS ADCs with 4- or 8-Channel MUX,
Track/Hold and Reference ..................................................
ADC1 031 / ADC1 034/ ADC1 038 1O-Bit Serial I/O A/D Converters with Analog
Multiplexer and Track/Hold Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC1 0731 / ADC1 0732/ ADC1 0734/ ADC1 0738 1O-Bit Plus Sign Serial I/O AID
Converters with MUX, Sample/Hold and Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC1 0831 / ADC1 0832/ ADC1 0834/ ADC1 0838 10-Bit Plus Sign Serial I/O A/D
Converters with MUX, Sample/Hold and Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC1061 1O-Bit High-Speed J-tP-Compatible AID Converter with Track/Hold
Function ............................................................,. . . . . .

iv

viii
xiii
xxvii
1-3
1-4
1-5
1-37
1-114
1-151
2-4
2-6
2-10
2-19
2-51
2-62
2-73
2-84
2-94
2-110
2-136
2-154
2-174
2-193
2-213
2-225
2-242
2-259
2-273
2-289
2-296
2-307
2-329
2-342
2-367
2-392

Table of Contents (Continued)
Section 2 Analog-to-Digital Converters (Continued)
ADC1 0061/ ADC1 0062/ ADC1 0064 1O-Bit 600 ns AID Converters with Input
Multiplexer and Sample/Hold.... ............ .... ............. ..... ... ... ....
ADC1 0461/ ADC1 0462/ ADC1 0464 1O-Bit 600 ns AID Converter with Input Multiplexer
and Sample/Hold..........................................................
ADC1 0662/ADC1 0664 1O-Bit 360 ns AID Converters with Input Multiplexer and
Sample/Hold ..............................................................
ADC12H030/ ADC12030/ADC12H032/ADC12032/ ADC12H034/ ADC12034/
ADC12H038/ ADC12038 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters
with MUX and Sample/Hold .................................................
ADC12L030/ ADC12L032/ ADC12L034/ ADC12L038 3.3V Self-Calibrating 12-Bit Plus
Sign Serial I/O A/D Converters with MUX and Sample/Hold. ... .. .. . .. . ... ......
ADC12130/ ADC12132/ ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D
Converters with MUX and Sample/Hold... ... . ... ... ...... .... ... .. . ... ... .. ..
ADC1205/ ADC1225 12-Bit Plus Sign /LP Compatible A/D Converters ... . . . . . . . . . . . .
ADC12062 12-Bit, 1 MHz, 75 mW AID Converter with Input Multiplexer and
Sample/Hold..............................................................
ADC12662 12-Bit, 1.5 MHz, 200 mW AID Converter with Input Multiplexer and
Sample/Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC1241 Self-Calibrating 12-Bit Plus Sign /LP-Compatible AID Converter with
Sample/Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC1242 12-Bit Plus Sign Sampling AID Converter.. .. .. .. . .. . .. .. .. . .. . .. . .. . .. .
ADC12441 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with
Sample/Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC1251 Self-Calibrating 12-Bit Plus Sign AID Converter with Sample/Hold. . . . . . . . .
ADC12451 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with
Sample/Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC16071/ADC16471 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converters. . . . .
LM131A1LM131, LM231A1LM231, LM331A1LM331 Precision Voltage-to-Frequency
Converters ................................................................
Section 3 Digital-to-Analog Converters
Digital-to-Analog Converters Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-to-Analog Converters Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC0800/DAC0801/DAC0802 8-Bit D/ A Converters ... . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC0808/DAC0807/DAC0806 8-Bit D/ A Converters .............................
DAC0830/DAC0831/DAC0832 8-Bit /LP Compatible Double-Buffered D/ A
Converters ............................................ ',' . . . . . . . . . . . . . . . . . .
DAC0854 Quad 8-Bit Voltage-Output Serial D/ A Converter with Readback . . . . . . . . . . .
DAC0890 Dual 8-Bit /LP-Compatible D/ A Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC1 006/DAC1 007/DAC1 008 /LP Compatible, Double-Buffered D/ A Converters ....
DAC1 020/DAC1 021/DAC1 022 10-Bit Binary Multiplying D/ A Converters. . . . . . . . . . . .
DAC1220/DAC1222 12-Bit Binary Multiplying D/ A Converters. . . . . . . . . . . . . . . . . . . . . .
DAC1054 Quad 1O-Bit Voltage-Output Serial D/ A Converter with Readback . . . . . . . . . .
DAC1208/DAC1209/DAC121 0/DAC1230/DAC1231/DAC1232 12-Bit /LP Compatible
Double-Buffered D/ A Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC1218/DAC1219 12-Bit Binary Multiplying D/ A Converters. . . . . . . . . . . . . . . . . . . . . .
Section 4 Voltage Reference
Voltage Reference Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LH0070 Series BCD Buffered Reference .....................................•..
LH0071 Series Precision Buffered Reference .................................. :.
LM113/LM313 Reference Diode...............................................
v

2-402
2-415
2-428

2-441
2-478
2-512
2-548
2-565
2-583
2-602
2-615
2-628
2-641
2-656
2-672
2-690
3-3
3-4
3-6
3-15
3-23
3-41
3-53
3-63
3-83
3-83
3-93
3-105
3-121
4-3
4-8
4-8
4-12

Table of Contents (Continued)
Section 4 Voltage Reference (Continued)
LM129/LM329 Precision Reference .................•....•..........•......•...
4-15
4-20
LM134/LM234/LM334 3-Terminal Adjustable Current Sources ..................... '
4-29
LM136-2.5/LM236-2:5/LM336-2.5V Reference Diodes ...........•...............•
LM136-5.0/LM236-5.0/LM336-5.0V Reference Diodes ...•........•............ " .
4-36
4-43
LM169/LM369 Precision Voltage References ............•.................•.....
-4-53
LM185/LM285/LM385 Adjustable Micropower Voltage References ................ .
LM 185-1.2/ LM285-1.2/ LM385-1.2 Micropower Voltage Reference Diodes ....•......
4-60
LM185-2.5/LM285-2.5/LM385-2.5 Micropower Voltage Reference Diodes •.... , ..• ; .
4-67
; 4-73
LM199/LM299/LM399/LM3999 Precision References ........................... .
LM368-2.5 Precision Voltage Reference ........................................ .
4-82
LM368-5.0, LM368-10 Precision Voltage References ......•.......................
4-88
LM4040 Precision Micropower Shunt Voltage Reference ....•..... : .............•.
4-94
LM4041 Precision Micropower Shunt Voltage Reference ......................•...
4-113
LM4431 Micropower Shunt Voltage Reference .............•..................... 4-125
LM9140 Precision Micropower Shunt Voltage Reference ......................... . , 4-131

Section 5 Temperature Sensors
Temperature Sensors Selection Guide .' ........................................ .
LM34/LM34A1LM34C/LM34CAlLM34D Precision Fahrenheit Temperature Sensors ..
LM35/LM35A1LM35C/LM35CAlLM35D Precision Centigrade Temperature Sensors .
LM458/LM45C SOT-23 Precision Centigrade Temperature Sensors ....•.......... :
LM50B/LM50C Single Supply Precision Centigrade Temperature Sensors .......... .
LM134/LM234/LM334 3-Terminal Adjustable Current Sources .................... .
LM135/LM235/LM335/LM135A1LM235A1LM335A Precision Temperature Sensors ..

5-3
5-4
5-12
5-21
5-28
5-29
5-38

Section 6 Sample and Hold
Sample and Hold Definition ofTerms ............................................ Sample and Hold Selection Guide ..•........•.....•........•...................
LF198/LF298/LF398/LF198A1LF398A Monolithic Sample and Hold Circuits ........ .
LF13006/LF13007 Digital Gain Set ............•..............•.................

6-3
6-4
6-5
6-15

Section 7 Active Filters
7-3
Active Filters Definition of Terms ...............................................
Active Filters Selection Guide .........•............•...•.... , .•...•............
7-4
LMF40 High Performance 4th-Order Switched Capacitor Butterworth Low~Pass Filter. .
7~5
LMF60 High Performance 6th-Order Switched Capacitor Butterworth Low-Pass Filter. .
7-19
LMF90 4th-Order Elliptic Notch Filter.... .......... .......•.•.....•.....•........
7-37
LMF100 High Performance Dual Switched Capacitor Filter.... .... .................
7-57
LMF380 Triple One-Third Octave Switched Capacitor Active Filter ......•........... ' 7-79
MF4 4th Order Switched Capacitor Butterworth Lowpass Filter ............. ,'.......
7-89
7-102
MF5 Universal Monolithic Switched Capacitor Filter ................... ~...........
MF6 6th Order Switched Capacitor Butterworth LowpassFilter .........•..........•
7-117
MF8 4th Order Switched Capacitor Bandpass Filter .. ~....... ...............•.....
7-135
7-157
MF10 Universal Monolithic Dual Switched Capacitor Filter. ..• •....•... .... ....•...

Section 8 Analog Switches/Multiplexers
Analog Switches/Multiplexers Definition of Terms ..... ~ . . . . . . . . . . . • . . . . . . . • . .. . . .
Analog SWitches/Multiplexers Selection Guide ...•. . . . . . . . . . . . . • . . . • • . . • • . • • . . • . •
AH0014/AH0014C DPDT, AH0015/AH0015C Quad SPST, AH0019/AH0019C Dual
DPST-TILlDTL Compatible MOS Analog Switches. . . . . . .. .• . . . • . . . . • .. . • . . .• •.
AH501 01 AH5011 / AH5012 Monolithic Analog Current Switches ....... ~ ........ ; . • .
AH5020C Monolithic Analog Current Switch. . . . . • • . . . • . . . • • . . . . . . . • . . . . • • . . • . • . . .
LF11331/LF13331/LF11332/LF13332/LF11333/LF13333,LF11201/LF13201/
LF11202/LF13202 Quad SPST JFET Analog Switches ..•....•...••......... ~ . . .
vi

_8-3
8-4
8-5
8-9
8-20
'8-28

Table of Contents (Continued)
Section 8 Analog Switches/Multiplexers (Continued)
LF13508 8-Channel Analog Multiplexer ......................................... .
LF1350.9 4-Channel Differential Analog Multiplexer .............................. .

8-39
8-39

Section 9 Surface Mount
Packing Considerations (Methods, Materials and Recycling) ....................... .
Board Mount of Surface Mount Components .................................... .
Recommended Soldering Profiles-Surface Mount .............................. .
AN-450 Small Outline (SO) Package Surface Mounting Methods-Parameters and Their
Effect on Product Reliability ................................................. .
Land Pattern Recommendations ............................................. ..

9-3
9-19 .
9-23
9-24
9-35

Section 10 Appendices/Physical Dimensions
Appendix A General Product Marking and Code Explanation ...................... .
Appendix B Device/Application Literature Cross-Reference ....................... .
Appendix D Military Aerospace Programs from National Semiconductor ............. .
Appendix E Understanding Integrated Circuit Package Power Capabilities ........... .
Appendix F How to Get the Right Information from a Datasheet .................... .
Physical Dimensions ......................................................... .
Bookshelf
Distributors

vii

10-3
10-4
10-10
·10-20
10-25
10-29

Alpha-Numeric Index
ADC0800 8-BitA/D Converter .............................................. ,....•...... ,.... 2-10
ADC080i 8-Bit ""p Compatible AiD Converter ................................................ 2-1 S
ADC0802 8-Bit ""p Compatible A/D Converter .....................................•.......... 2-19
ADC0803 8-Bit ""p Compatible A/D Converter ................................................ 2-19
ADC0804 8-Bit ""p Compatible AID Converter ........................................•....... 2-19
ADC0805 8-Bit ""PCompatible AID Converter ................................................ 2-19
ADC0808 8-Bit ""p Compatible AID Converter with 8-Channel Multiplexer ........................ 2-51
ADC0809 8-Bit ""p Compatible AID Converter with 8-Channel Multiplexer ........................ 2-51
ADC0811 8-Bit Serial 110 AID Converter with 11-Channel Multiplexer ........................... 2-62
ADC0816 8-Bit ""p Compatible A/D Converter with 16-Channel Multiplexer ....................... 2-73
ADC0817 8-Bit ""p Compatible AID Converter with 16-Channel Multiplexer ....................... 2-73
ADC0819 8-Bit Serial 110 AID Converter with 19-Channel Multiplexer ........................... 2-84
ADC0820 8-Bit High Speed p.P Compatible A/D Converter with Track/Hold Function .............. 2-94
ADC0831 8-Bit Serial 110 AID Converter with Multiplexer Options ..........................•.. 2-110
ADC0832 8-Bit Serial 110 AID Converter with Multiplexer Options ............................. 2-110
ADC0833 8-Bit Serial 110 AID Converter with 4-Channel Multiplexer ........................... 2-136
ADC0834 8-Bit Serial 110 AID Converter with Multiplexer Options ............................. 2-110
ADC0838 8-Bit Serial 110 AID Converter with Multiplexer Options ............................. 2-110
ADC0841 8-Bit ""p Compatible AID Converter ............................................... 2-213
ADC0844 8-Bit ""p Compatible A/D Converter with Multiplexer Options ......................... 2-225
ADC0848 8-Bit ""p Compatible AID Converter with Multiplexer Options ...............•......... 2-225
ADC0851 8-Bit Analog Data Acquisition and Monitoring System ................................. 1-5
ADC0852 Multiplexed Comparator with 8-Bit Reference Divider ................................ 2-242
ADC0854 Multiplexed Comparator with 8-Bit Reference Divider ..............................•. 2-242
ADC0858 8-Bit Analog Data Acquisition and Monitoring System ................................. 1-5
ADC08031 8-Bit High-Speed Serial 110 AID Converter with Multiplexer Options, Voltage
Reference, and Track/Hold Function .................................................... 2-154
ADC08032 8-Bit High-Speed Serial 110 AID Converter with Multiplexer Options, Voltage
Reference, and Track/Hold Function .................................................... 2-154
ADC08034 8-Bit High-Speed Serial 110 AID Converter with Multiplexer Options, Voltage
Reference, and Track/Hold Function .................................................... 2-154
ADC08038 8-Bit High-Speed Serial 110 AID Converter with Multiplexer Options, Voltage
Reference, and Track/Hold Function .................................................... 2-154
ADC08061 500 ns AID Converter with S/H Function and Input Multiplexer ...................... 2-259
ADC08062 500 ns AID Converter with S/H Function and Input Multiplexer ...................... 2-259
ADC08131 8-Bit High-Speed Serial 110 AID Converter with Multiplexer Options, Voltage
Reference, and Track/Hold Function .................................................... 2-174
ADC08134 8-Bit High-Speed Serial 110 AID Converter with Multiplexer Options, Voltage
Reference, and Track/Hold Function .................................................... 2-174
ADC08138 8-Bit High-Speed Serial 110 AID Converter with Multiplexer Options, Voltage
Reference, and Track/Hold Function .................................................... 2-174
ADC08161 500 ns AID Converter with S/H Function and 2.5V Bandgap Reference .............. 2-273
ADC08231 8-Bit 2 ""s Serial 110 AID Converter with MUX, Reference, and Track/Hold ........... 2-193
ADC08234 8-Bit 2 ""s Serial 110 AID Converter with MUX, Reference, and Track/Hold ........... 2-193
ADC08238 8-Bit 2 ""s Serial 110 AID Converter with MUX, Reference, and Track/Hold ........... 2-193
ADC12H030 Self-Calibrating 12-Bit Plus Sign Serial 110 AID Converter with MUX and
Sample/Hold ......................................................................... 2-441
ADC12H032 Self-Calibrating 12-Bit Plus Sign Serial 110 AID Converter with MUX and
Sample/Hold ......................................................................... 2-441
ADC12H034 Self-Calibrating 12-Bit Plus Sign Serial 110 AID Converter with MUX and
Sample/Hold .........................................................•............... 2-441

viii

Alpha-Numeric

Index(continUed)

ADC12H038 Self-Calibrating 12-Bit Plus Sign Serial I/O AID Converter with MUX and
Sample/Hold ......................................................................... 2-441
ADC12L030 3.3V Self-Calibrating 12-Bit Plus Sign Serial 1/0 AID Converter with MUX and
Sample/Hold ......................................................................... 2-478
ADC12L032 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O AID Converter with MUX and
Sample/Hold ......................................................................... 2-478
ADC12L034 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O AID Converter with MUX and
Sample/Hold ......................................................................... 2-478
ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O AID Converter with MUX and
Sample/Hold ......................................................................... 2-478
ADC1001 1O-Bit JLP Compatible AID Converter ............................................. 2-289
ADC1005 1O-Bit JLP Compatible AID Converter ............................................. 2-296
ADC1031 1O-Bit Serial I/O AID Converter with Analog Multiplexer and Track/Hold Function ...... 2-329
ADC1034 1O-Bit Serial I/O AID Converter with Analog Multiplexer and Track/Hold Function ...... 2-329
ADC1038 1O-Bit Serial I/O AID Converter with Analog Multiplexer and Track/Hold Function ...... 2-329
ADC1061 10-Bit High-Speed JLP-Compatible AID Converter with Track/Hold Function ........... 2-392
ADC1205 12-Bit Plus Sign JLP Compatible AID Converter .........•........................... 2-548
ADC1225 12-Bit Plus Sign JLP Compatible AID Converter ..................................... 2-548
ADC1241 Self-Calibrating 12-Bit Plus Sign JLP-Compatible A/D Converter with Sample/Hold ...... 2-602
ADC1242 12-Bit Plus Sign Sampling AID Converter .......................................... 2-615
ADC1251 Self-Calibrating 12-Bit Plus Sign AID Converter with Sample/Hold .................... 2-641
ADC10061 1O-Bit 600 ns AID Converter with Input Multiplexer and Sample/Hold ................ 2-402
ADC10062 1O-Bit 600 ns AID Converter with Input Multiplexer and Sample/Hold ................ 2-402
ADC10064 1O-Bit 600 ns AID Converter with Input Multiplexer and Sample/Hold ................ 2-402
ADC1 0154 10-Bit Plus Sign 4 JLs ADC with 4- or 8-Channel MUX, Track/Hold and Reference ...... 2-307
ADC1 0158 10-Bit Plus Sign 4 JLs ADC with 4- or 8-Channel MUX, Track/Hold and Reference ...... 2-307
ADC10461 10-Bit 600 ns AID Converter with Input Multiplexer and Sample/Hold ................ 2-415
ADC10462 10-Bit 600 ns AID Converter with Input Multiplexer and Sample/Hold ................ 2-415
ADC10464 1O-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold ................ 2-415
ADC10662 1O-Bit 360 ns AID Converter with Input Multiplexer and Sample/Hold ................ 2-428
ADC10664 1O-Bit 360 ns AID Converter with Input Multiplexer and Sample/Hold ................ 2-428
ADC10731 10-Bit Plus Sign Serial I/O AID Converter with MUX, Sample/Hold and Reference ..... 2-342
ADC10732 10-Bit Plus Sign Serial I/O AID Converter with MUX, Sample/Hold and Reference ..... 2-342
ADC10734 10-Bit Plus Sign Serial I/O AID Converter with MUX, Sample/Hold and Reference ..... 2-342
ADC10738 10-Bit Plus Sign Serial I/O AID Converter with MUX, Sample/Hold and Reference ..... 2-342
ADC10831 1O-Bit Plus Sign Serial I/O AID Converter with MUX, Sample/Hold and Reference ..... 2-367
ADC10832 1O-Bit Plus Sign Serial I/O AID Converter with MUX, Sample/Hold and Reference ..... 2-367
ADC10834 10-Bit Plus Sign Serial 110 AID Converter with MUX, Sample/Hold and Reference ..... 2-367
ADC10838 10-Bit Plus Sign Serial I/O AID Converter with MUX, Sample/Hold and Reference .•... 2-367
ADC12030 Self-Calibrating 12-Bit Plus Sign Serial I/O AID Converter with MUX and
Sample/Hold ......................................................................... 2-441
ADC12032 Self-Calibrating 12-Bit Plus Sign Serial I/O AID Converter with MUX and
Sample/Hold ......................................................................... 2-441
ADC12034 Self-Calibrating 12-Bit Plus Sign Serial 110 AID Converter with MUX and
Sample/Hold ......................................................................... 2-441
ADC12038 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converter with MUX and
Sample/Hold ......................................................................... 2-441
ADC12062 12-Bit, 1 MHz, 75 mW AID Converter with Input Multiplexer and Sample/Hold ......... 2-565
ADC12130 Self-Calibrating 12-Bit Plus Sign Serial I/O AID Converter with MUX and
Sample/Hold ...................................................•......•.............. 2-512

ix

Alpha-Numeric

Index(ContinUed)

ADC12132 Self-Calibrating 12-Bit Plus Sign Serial I/O AID Converter with MUX and
Sample/Hold ................................................................... ~; .... 2-512
ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O AID Converter with MUX and
Sample/Hold ................•.......................•................................ 2-512
ADC12441 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign AID Converter with
Sample/Hold ........•...............•...............•..............................' .• 2-628
ADC12451 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign AID Converter with
, Sample/Hold •......................................................................•. 2-656
ADC12662 12-Bit, 1.5 MHz, 200 mW A/D Converter with Input Multiplexer and Sample/Hold ...... 2-583
ADC16071 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converter ..................•........ 2-672
ADC16471 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converter ........................... 2-672
AH0014 Dual DPDT-TTLlDTL Compatible MOS Analog Switch .................. .' ............... 8-5
AH0015 Quad SPST-TTLlDTL Compatible MOS Analog Switch ...............•.•........ ; ...... 8-5
AH0019 Dual DPST-TTLlDTL Compatible MOS Analog Switch ......... ; .................•...... 8-5
AH5010 Monolithic Analog Current Switch .................................................... 8-9
AH5011 Monolithic Analog Current Switch ....•................•. ; .....................•...... 8-9
AH5012 Monolithic Analog Current Switch .................. ; ............... ; ................. 8-9
AH5020C Monolithic Analog Current Switch .............. ~ ................................... 8-20
AN-450 Small Outline (SO) Package Surface Mounting Methods-Parameters and Their Effect
on Product Reliability ..................................................... ; .............. 9-24
Board Mount of Surface Mount Components ................................................. 9-19
DAC0800 8-Bit D/ A Converter ............................................................... 3-6
DAC0801 8-Bit D/ A Converter ................................................ '......... ; ....... 3-6
DAC0802 8-Bit D/ A Converter ................' ..................................... , ........ 3-6
DAC0806 8-Bit D/ A Converter ..........•........................................... : ....... 3-15
DAC0807 8-Bit D/ A Converter ............................................................. 3-.15
DAC0808 8-Bit D/ A Converter ............................................................. 3-15
DAC0830 8-Bit p.P Compatible Double-Buffered D/ A Converter ................................. 3-23
DAC0831 8-Bit p.P Compatible Double-Buffered D/ A Converter ................................. 3-23
DAC0832 8-Bit p.P Compatible Double-Buffered D/ A Converter ................................. 3-23
DAC0854 Quad 8-Bit Voltage-Output Serial D/ A Converter with Readback ....................... 3-41
DAC0890 Dual 8-Bit p.P-Compatible D/ A Converter ........................................... 3-53
DAC1006 p.P Compatible, Double-Buffered D/ A Converter ..................•.................. 3-63
DAC1007 p.P Compatible, Double-Buffered D/ A Converter ..................•.................. 3"63
DAC1008 p.P Compatible, Double-Buffered D/ A Converter ................................:. .... 3~63
DAC1020 1O-Bit Binary Multiplying D/ A Converter ............................................ 3-83
DAC1021 10-Bit Binary Multiplying D/ A Converter ....................................... ;' .... 3-83
DAC1022 10-Bit Binary Multiplying D/ A Converter ............................................ 3-83
DAC1054 Quad 1O-Bit Voltage-Output Serial D/ A Converter with Readback ................. '..... 3-93
DAC1208 12-Bit p.P Compatible Double-Buffered D/ A Converter ............•......•.......... 3-105
DAC1209 12-Bit p.P Compatible Double-Buffered D/ A Converter .............................. 3-105
DAC1210 12-Bit p.P Compatible Double-Buffered D/ A Converter ................•............. 3-105
DAC121812-Bit Binary Multiplying D/A Converter ..........•.......•.......................• 3-121
DAC1219 12-Bit Binary Multiplying D/ A Converter ........................................... 3-,121
DAC1220 12-Bit Binary Multiplying D/ A Converter ............................................ 3-83
DAC1222 12-Bit Binary Multiplying D/A Converter ............................................ 3-83
DAC1230 12-Bit p.P Compatible Double-Buffered D/A Converter ........................ , ..... 3-.105
DAC1231 .12-Bit p.P Compatible Double-Buffered D/ A Converter .•.............••.•..••....... 3~1 05
DAC1232 12-Bit p.P Compatible Double-Buffered D/ A Converter .................••.•......... 3-105
Land Pattern Recommendations ..................•.......................•......•......... 9-35
LF198 Monolithic Sample and Hold Circuit ...•................................................ 6-5

x

Alpha-Numeric

Index(continUed)

LF298 Monolithic Sample and Hold Circuit .................................................... 6-5
LF398 Monolithic Sample and Hold Circuit .................................................... 6-5
LF11201 Quad SPST JFET Analog Switch ................................................... 8-28
LF11202 Quad SPST JFET Analog Switch ................................................... 8-28
LF11331 Quad SPST JFET Analog Switch ................................................... 8-28
LF11332 Quad SPST JFET Analog Switch ................................................... 8-28
LF11333 Quad SPST JFET Analog Switch ................................................... 8-28
LF13006 Digital Gain Set .................................................................. 6-15
LF13007 Digital Gain Set .................................................................. 6-15
LF13201 Quad SPST JFET Analog Switch ................................................... 8-28
LF13202 Quad SPST JFET Analog Switch ................................................... 8-28
LF13331 Quad SPST JFET Analog Switch ................................................... 8-28
LF13332 Quad SPST JFET Analog Switch ................................................... 8-28
LF13333 Quad SPST JFET Analog Switch ................................................... 8-28
LF13508 8-Channel Analog Multiplexer ...................................................... 8-39
LF13509 4-Channel Differential Analog Multiplexer ........................................... 8-39
LH0070 Series BCD Buffered Reference ...................................................... 4-8
LH0071 Series Precision Buffered Reference ................................................. 4-8
LM12H454 12-Bit + Sign Data Acquisition System with Self-Calibration ........................ 1-114
LM12H458 12-Bit + Sign Data Acquisition System with Self-Calibration ........................ 1-114
LM12L438 12-Bit + Sign Data Acquisition System with Serial 1/0 and Self-Calibration ............. 1-37
LM12L454 12-Bit + Sign Data Acquisition System with Self-Calibration ........................ 1-151
LM12L458 12-Bit + Sign Data Acquisition System with Self-Calibration ........................ 1-151
LM34 Precision Fahrenheit Temperature Sensor ............................................... 5-4
LM35 Precision Centigrade Temperature Sensor ............................................. 5-12
LM45 SOT-23 Precision Centigrade Temperature Sensor ...................................... 5-21
LM50 Single Supply Precision Centigrade Temperature Sensor ................................. 5-28
LM113 Reference Diode .................................................................. 4-12
LM129 Precision Reference ............................................................... 4-15
LM131 Precision Voltage-to-Frequency Converter ........................................... 2-690
LM134 3-Terminal Adjustable Current Source ................................................ 4-20
LM134 3-Terminal Adjustable Current Source ................................................ 5-29
LM135 Precision Temperature Sensor ....................................................... 5-38
LM136-2.5V Reference Diode .............................................................. 4-29
LM136-5.0V Reference Diode .............................................................. 4-36
LM169 Precision Voltage Reference. '" .................................................... 4-43
LM185 Adjustable Micropower Voltage Reference ............................................ 4-53
LM185-1.2 MicropowerVoltage Reference Diode ............................................. 4-60
LM185-2.5 Micropower Voltage Reference Diode ............................................. 4-67
LM199 Precision Reference ............................................................... 4-73
LM231 Precision VOltage-to-Frequency Converter ........................................... 2-690
LM234 3-Terminal Adjustable Current Source ................................................ 5-29
LM234 3-Terminal Adjustable Current Source ................................................ 4-20
LM235 Precision Temperature Sensor ....................................................... 5-38
LM236-2.5V Reference Diode .............................................................. 4-29
LM236-5.0V Reference Diode .............................................................. 4-36
LM285 Adjustable Micropower Voltage Reference ............................................ 4-53
LM285-1.2 MicropowerVoltage Reference Diode ............................................. 4-60
LM285-2.5 Micropower Voltage Reference Diode ............................................. 4-67
LM299 Precision Reference ............................................................... 4-73
LM313 Reference Diode ............•..................................................... 4-12

xi

Alpha-Numeric

Index(ContinUed)

LM329 Precision Reference .......................................................... '.•... 4-15
LM331 Precision Vo!tage-to-Frequency Converter ......................................... , . 2-690
LM334 3-Terminal Adjustable Current Source ................................................ 4-20
LM334 3-Terminal Adjustable Current Source ................................................ 5-29
LM335 Precision Temperature Sensor ....................................................... 5-38
LM336-2.5V Reference Diode ............................................................•. 4-29
LM336-5.0V Reference Diode ............................................................... 4-36
LM368-2.5 Precision Voltage Reference ..................................................... 4-82
LM368-5.0 Precision Voltage Reference ........................................•.......... ; . 4-88
LM368-10 Precision Voltage Reference ..................................................... 4-88
LM369 Precision Voltage Reference .................................................•...... 4-43
LM385 Adjustable Micropower Voltage Reference .............. '.............................. 4-53
LM385-1.2 Micropower Voltage Reference Diode ............................................ ..4-60
LM385-2.5 Micropower Voltage Reference Diode ............................................. 4-67
LM399 Precision Reference ........................................................•...... 4-73
LM3999 Precision Reference .............................................................. 4-73
LM4040 Precision Micropower Shunt Voltage Reference ...............................•...... 4-94
LM4041 Precision Micropower Shunt Voltage Reference ..................................... 4-113
LM4431 Micropower Shunt Voltage Reference ............................................... 4-125
LM9140 Precision Micropower Shunt Voltage Reference ..................................... 4-131
LM12434 12-Bit + Sign Data Acquisition System with Serial 1/0 and Self-Calibration .............. 1-37
LM12454 12-Bit + Sign Data Acquisition System with Self-Calibration .......................... 1-114
LM12458 12-Bit + Sign Data Acquisition System with Self-Calibration .................. ; ....... 1-114
LMF40 High Performance 4th-Order Switched Capacitor Butterworth Low-Pass Filter ............... 7-5
LMF60 High Performance 6th-Order Switched Capacitor Butterworth Low-Pass Filter ............•. 7-19
LMF90 4th-Order Elliptic Notch Filter ........................................................ 7-37
LMF.100 High Performance Dual Switched Capacitor Filter ..... ,.............................. ,'.7-57
LMF380 Triple One-Third Octave Switched Capacitor Active Filter .............................. 7-79
MF4 4th Order Switched Capacitor Butterworth Lowpass Filter ................................. 7-89
MF5 Universal Monolithic Switched Capacitor Filter .................................. ; .•..... 7-102
MF6 6th Order Switched Capacitor Butterworth Lowpass Filter ..........................•..... 7-117
MF8 4th Order Switched Capacitor Bandpass Filter .......................................... 7-135
MF10 Universal, Monolithic Dual Switched Capacitor Filter .................................... 7-157
Packing Considerations (Methods, Materials and Recycling) .................... '................. 9-3
Recommended Soldering Profiles-Surface Mount ........................................... 9-23

xii

Additional Available Linear Devices
54ACT715 Programmable Video Sync Generator ...... Section 2
74ACT715 Programmable Video Sync Generator ...... Section 2
AN-450 Small Outline (SO) Package Surface Mounting
Methods-Parameters and Their Effect on Product
Reliability ...................................... Section 5
AN-450 Small Outline (SO) Package Surface Mounting
Methods-Parameters and Their Effect on Product
Reliability ...................................... Section 5
AN-450 Small Outline (SO) Package Surface Mounting
Methods-Parameters and Their Effect on Product
Reliability ...................................... Section 6
Board Mount of Surface Mount Components .......... Section 6
Board Mount of Surface Mount Components .......... Section 5
Board Mount of Surface Mount Components .......... Section 5
DH0006 Current Driver ............................ Section 5
DH0034 High Speed Dual Level Translator ........... Section 5
DH0035 Pin Diode Driver ........................... Section 5
DP731 0 Octal Latched Peripheral Driver ............. Section 3
DP7311 Octal Latched Peripheral Driver ............. Section 3
DP831 0 Octal Latched Peripheral Driver ............. Section 3
DP8311 Octal Latched Peripheral Driver ............. Section 3
DS0026 5 MHz Two Phase MOS Clock Drivers ........ Section 4
DS1631 CMOS Dual Peripheral Driver ............... Section 3
DS1632 CMOS Dual Peripheral Driver ............... Section 3
DS1633 CMOS Dual Peripheral Driver ............... Section 3
DS1634 CMOS Dual Peripheral Driver ............... Section 3
DS2003 High Current/Voltage Darlington Driver ....... Section 3
DS2004 High Current/Voltage Darlington Driver ....... Section 3
DS3631 CMOS Dual Peripheral Driver ............... Section 3
DS3632 CMOS Dual Peripheral Driver ............... Section 3
DS3633 CMOS Dual Peripheral Driver ............... Section 3
DS3634 CMOS Dual Peripheral Driver ................ Section 3
DS3658 Quad High Current Peripheral Driver .. ; ...... Section 3
DS3668 Quad Fault Protected Peripheral Driver ....... Section 3
DS3680 Quad Negative Voltage Relay Driver ......... Section 3
DS9667 High Current/Voltage Darlington Driver ....... Section 3
DS55451 Series Dual Peripheral Driver .............. Section 3
DS55452 Series Dual Peripheral Driver .............. Section 3
DS55453 Series Dual Peripheral Driver .............. Section 3
DS55454 Series Dual Peripheral Driver .............. Section 3
DS75451 Series Dual Peripheral Driver .............. Section 3
DS75452 Series Dual Peripheral Driver .............. Section 3
DS75453 Series Dual Peripheral Driver .............. Section 3
DS75454 Series Dual Peripheral Driver .............. Section 3
DS75491 MOS-to-LED Quad Segment Driver ......... Section 4
DS75492 MOS-to-LED Hex Digit Driver •............. Section 4
DS75494 Hex Digit Driver ............•......•...... Section 4
Land Pattern Recommendations ......•............. Section 5
Land Pattern Recommendations ........•......••... Section 5
Land Pattern Recommendations .............•...... Section 6
LF111 Voltage Comparator ......................... Section 3

xiii

Application Specific Analog Products
Application Specific Analog Products

Power ICs

Application Specific Analog Products

Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
PowerlCs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
PowerlCs
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers

Additional Available Linear Devices (Continued)
LF147 Wide Bandwidth Quad JFET Input Operational
Amplifier ....................................... Section 1
LF155 Series Monolithic JFET Input Operational
Amplifiers ...................................... Section .1
LF156 Series Monolithic JFET Input Operational
Amplifiers ...................................... Section 1
LF157 Series Monolithic JFET Input Operational
Amplifiers ............................... , ...... Section 1
LF211 Voltage Comparator .......................•. Section 3
LF311 Voltage Comparator ......................... Section 3
LF347 Wide Bandwidth Quad JFET Input Operational
Amplifier ....................................... Section 1
LF351 Wide Bandwidth JFET Input Operational
Amplifier ....................................... Section 1
LF353 Wide Bandwidth Dual JFET Input Operational
Amplifier ....................................... Section 1
LF411 Low Offset, Low Drift JFET Input Operational
Amplifier ....................................... Section 1
LF412 Low Offset, Low Drift Dual JFET Operational
Amplifier ......... ; ............................. Section 1
LF441 Low Power JFET Input Operational Amplifier ... Section 1
LF442 Dual Low Power JFET Input Operational
Amplifier ....................................... Section,1
LF444 Quad Low Power JFET Input Operational
Amplifier ....................................... Section 1
LF451 Wide-Bandwidth JFET Input Operational
Amplifier ....................................... Section 1
LF453 Wide-Bandwidth Dual JFET Input Operational
Amplifier ....................................... Section 1
LH0002 Buffer .................................... Section 2
LH0003 Wide Bandwidth Operational Amplifier ........ Section 1
LH0004 High Voltage Operational Amplifier ........... Section 1
LH0021 1.0 Amp Power Operational Amplifier ......... Section 1
LH0024 High Slew Rate Operational Amplifier ........ Section 1
LH0032 Ultra Fast FET-Input Operational Amplifier .... Section 1
LH0033 Fast and Ultra Fast Buffers ................. Section 2
LH0041 0.2 Amp Power Operational Amplifier ......... Section 1
LH0042 Low Cost FET Operational Amplifier ......... Section 1
LH0063 Fast and Ultra Fast Buffers ................. Section 2
LH0094 Multifunction Converter ..................... Section 5
LH0101 Power Operational Amplifier ................ Section 1
LH 1605 5 Amp, High Efficiency Switching Regulator ... Section 3
LH2111 Dual Voltage Comparator ................... Section 3
LH2311 Dual Voltage Comparator ................... Section 3
LH4001 Wideband Current Buffer ................... Section 2
LH4002 Wideband Video Buffer ..................... Section 2
LM10 Operational Amplifier and Voltage Reference .... Section 1
LM12 80W Operational Amplifier .................... Section 4
LM78LXX Series3-Terminal Positive Regulators ....•. Section 1
LM78MXX Series 3-Terminal Positive Regulator ....... Section 1
LM78S40 Universal Switching Regulator Subsystem ... Section 3

xiv

Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
,Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Power ICs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
PowerlCs
PowerlCs
PowerlCs
, PowerlCs

Additional Available linear Devices (Continued)
LM78XX Series Voltage Regulators ................. Section.1
LM79LXXAC Series 3-Terminal Negative Regulator .... Section 1
LM79MXX Series 3-Terminal Negative Regulators ..... Section 1
LM79XX Series 3-Terminal Negative Regulators ...... Section 1
LM101A Operational Amplifier ...................... Section 1
LM102 Voltage Follower ........................... Section 2
LM105 Voltage Regulator .......................... Section 1
LM106 Voltage Comparator ........................ Section 3
LM107 Operational Amplifier ....................... Section 1
LM108 Operational Amplifier ....................... Section 1
LM109 5-Volt Regulator ............................ Section 1
LM110 Voltage Follower ........................... Section 2
LM 111 Voltage Comparator ........................ Section 3
LM117 3-Terminal Adjustable Regulator ............. Section 1
LM117HV 3-Terminal Adjustable Regulator ........... Section 1
LM118 Operational Amplifier ....................... Section 1
LM119 High Speed Dual Comparator ................ Section 3
LM120 Series 3-Terminal Negative Regulator ......... Section 1
LM122 Precision Timer ............................ Section 4
LM123 3-Amp, 5-Volt Positive Regulator ............. Section 1
LM124 Low Power Quad Operational Amplifier ........ Section 1
LM125 Dual Voltage Regulator ..................... Section 1
LM133 3-Amp Adjustable Negative Regulator ......... Section 1
LM137 3-Terminal Adjustable Negative Regulator ..... Section 1
LM137HV 3-Terminal Adjustable Negative Regulator
(High Voltage) .................................. Section 1
LM138 5-Amp Adjustable Regulator ................. Section 1
LM139 Low Power Low Offset Voltage Quad
Comparator ..................•................. Section 3
LM140 Series 3-Terminal Positive Regulator .......... Section 1
LM140L Series 3-Terminal Positive Regulator ......... Section 1
LM143 High Voltage Operational Amplifier ........... Section 1
LM145 Negative 3-Amp Regulator ................... Section 1
LM146 Programmable Quad Operational Amplifier ..... Section 1
LM148 Quad 741 Operational Amplifier .............. Section 1
LM149 Wide Band Decompensated (Av(MIN) = 5) .... Section 1
LM150 3-Amp Adjustable Regulator ................. Section 1
LM 158 Low Power Dual Operational Amplifier ......... Section 1
LM160 High Speed Differential Comparator ........... Section 3
LM161 High Speed Differential Comparator ........... Section 3
LM193 Low Power Low Offset Voltage Dual
Comparator .................................... Section 3
LM194 Supermatch Pair ........................... Section 5
LM195 Ultra Reliable Power Transistor ............... Section 5
LM201A Operational Amplifier ...................... Section 1
LM205 Voltage Regulator ........................... Section 1
LM207 Operational Amplifier ....................... Section 1
LM208 Operational Amplifier ..........•......•..... Section 1
LM21 0 Voltage Follower ........................... Section 2
LM211 Voltage Comparator ........................ Section 3
LM218 Operational Amplifier ....................... Section 1

xv

Power ICs
Power ICs
Power ICs
Power ICs
Operational Amplifiers
Operational Amplifiers
Power ICs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Power ICs
Operational Amplifiers
Operational Amplifiers
Power ICs
Power ICs
Operational Amplifiers
Operational Amplifiers
Power ICs
Application Specific Analog Products
Power ICs
Operational Amplifiers
Power ICs
Power ICs
Power ICs
Power ICs
Power·ICs
Operational Amplifiers
Power ICs
Power ICs
Operational Amplifiers
Power ICs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Power ICs
Operational Amplifiers
Operational Amplifiers
.Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Power ICs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers

Additional Available Linear Devices (Continued)
LM219 High Speed Dual Comparator ................ Section 3
LM221 Precision Preamplifier ....................... Section 1
LM224 Low Power Quad Operational Amplifier ........ Section 1
LM239 Low Power Low Offset Voltage Quad
Comparator .................................... Section 3
LM246 Programmable Quad Operational Amplifier ..... Section 1
LM248 Quad 741 Operational Amplifier .............. Section 1
LM258 Low Power Dual Operational Amplifier ......... Section 1
LM261 High Speed Differential Comparator ........... Section 3
LM293 Low Power Low Offset Voltage Dual
Comparator ......•....................•........ Section 3
LM301 A Operational Amplifier .•...........•........ Section 1
LM302 Voltage Follower ..................•........ Section 2
LM305 Voltage Regulator ..•.•••..•................ Section 1
LM306 Voltage Comparator •.••••.........•........ Section 3
LM307 Operational Amplifier ............•.•.••••... Section 1
LM308 Operational Amplifier .....................•. Section 1
LM309 5-Volt Regulator •••.•.•••.•..•.....•....•... Section 1
LM310 Voltage Follower .....•.....•..•.•.•.•••••.• Section 2
LM311 Voltage Comparator ....................•... Section 3
LM317 3-Terminal Adjustable Regulator •.•••.•.••..• Section 1
LM317HV 3-Terminal Adjustable Regulator ........... Section 1
LM317L 3-Terminal Adjustable Regulator ...•........ Section 1
LM318 Operational Amplifier ...•.••...•............ Section 1
LM319 High Speed Dual Comparator ...•...•.•...... Section 3
LM320 Series 3-Terminal Negative Regulator ......... Section 1
LM320L Series 3-Terminal Negative Regulator ........ Section 1
LM321 Precision Preamplifier ....................... Section 1
LM322 Precision Timer ............................ Section 4
LM323 3-Amp, 5-Volt Positive Regulator ............. Section 1
LM324 Low Power Quad Operational Amplifier ........ Section 1
LM325 Dual Voltage Regulator ............•........ Section 1
LM330 3-Terminal Positive Regulator ................ Section 2
LM333 3-Amp Adjustable Negative Regulator •...••... Section 1
LM337 3-Terminal Adjustable Negative Regulator ..••. Section 1
LM337HV 3-Terminal Adjustable Negative Regulator
(High Voltage) .......................•.•.•.••... Section 1
LM337L 3-Terminal Adjustable Regulator ...•..•...•• Section 1
LM338 5-Amp Adjustable Regulator ........•......•. Section 1
LM339 Low Power Low Offset Voltage Quad
Comparator .•••.......................•........ Section 3
LM340 Series 3-Terminal Positive Regulator .•........ Section 1
LM340L Series 3-Terminal Positive Regulator •........ Section 1
LM341 Series 3-Terminal Positive Regulator .•........ Section 1
LM343 High Voltage Operational Amplifier ........... Section 1
LM345 Negative 3-Amp Regulator ................... Section 1
LM346 Programmable Quad Operational Amplifier ..... Section 1
LM348 Quad 741 Operational Amplifier ......•..•.... Section 1
LM349 Wide Band Decompensated (Av(MIN) = 5) .... Section 1
LM350 3-AmpAdjustable Regulator ................. Section 1
LM358 Low Power Dual Operational Amplifier ......... Section 1

xvi

Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
PowerlCs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
PowerlCs
Operational Amplifiers
Operational Amplifiers
Power ICs
Power ICs
Power ICs
Operational Amplifiers
Operational Amplifiers
Power ICs
Power ICs
Operational Amplifiers
Application Specific Analog Products
Power ICs
Operational Amplifiers
Power ICs
PowerlCs
PowerlCs
Power ICs
PowerlCs
PowerlCs
Power ICs
Operational Amplifiers
Power ICs
Power ICs
Power ICs
Operational Amplifiers
PowerlCs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Power ICs
Operational Amplifiers

Additional Available Linear Devices (Continued)
LM359 Dual, High Speed, Programmable Current
Mode (Norton) Amplifier ......................... Section 1
LM360 High Speed Differential Comparator ........... Section 3
LM361 High Speed Differential Comparator ........... Section 3
LM376 Voltage Regulator .......................... Section 1
LM380 Audio Power Amplifier ....................... Section 1
LM383 7W Audio Power Amplifier ................... Section 1
LM384 5W Audio Power Amplifier ................... Section 1
LM386 Low Voltage Audio Power Amplifier ........... Section 1
LM387/LM387 A Low Noise Dual Preamplifier ......... Section 1
LM388 1.5W Audio Power Amplifier ................. Section 1
LM389 Low Voltage Audio Power Amplifier with NPN
Transistor Array ................................ Section 1
LM390 1W Battery Operated Audio Power Amplifier ... Section 1
LM391 Audio Power Driver .......................... Section 1
LM392 Low Power Operational AmplifierlVoltage
Comparator ........ ; .......•...•...•.•.•....... Section 1
LM393 Low Power Low Offset Voltage Dual
Comparator .................•.................. Section 3
LM394 Supermatch Pair ........................... Section 5
LM395 Ultra Reliable Power Transistor .........•..... Section 5
LM431 A Adjustable Precision Zener Shunt Regulator .• Section 3
LM555 Timer ................................... '.' Section 4
LM555C Timer .................................... Section 4
LM556 DualTimer ................................ Section 4
LM556C Dual Timer ............................... Section 4
LM565 Phase Locked Loop ........................ Section 4
LM565C Phase Locked Loop ....................... Section 4
LM566C Voltage Controlled Oscillator ............... Section 4
LM567 Tone Decoder ............................. Section 4
LM567C Tone Decoder ............................ Section 4
LM611 Operational Amplifier and Adjustable
Reference ..................................... Section 1
LM612 Dual-Channel Comparator and Reference ..... Section 3
LM613 Dual Operational Amplifier, Dual Comparator,
and Adjustable Reference ........................ Section 3
LM613 Dual Operational Amplifier, Dual Comparator,
and Adjustable Reference •....................... Section 1
LM614 Quad Operational Amplifier and Adjustable
Reference ........................•............ Section 1
LM615 Quad Comparator and Adjustable Reference ... Section 3
LM628 Precision Motion Controller .................. Section 4
LM629 Precision Motion Controller .........•........ Section 4
LM675 Power Operational Amplifier ................. Section 1
LM709 Operational Amplifier ....................... Section 1
LM710 Voltage Comparator ........................ Section 3
LM723 Voltage Regulator .......................... Section 1
LM725 Operational Amplifier ...••.........•.•...... Section 1
LM741 Operational Amplifier •..•..•...•.•••.•...•.. Section 1
LM747 Dual Operational Amplifier.; •.•••.••••••.•... Section 1
LM748 Operational Amplifier •.•••....•.••.......... Section 1

xvii

Application
Application
Application
Application
Application
Application

Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Power ICs
Specific Analog Products
Specific Analog Products
Specific Analog Products
Specific Analog Products
Specific Analog Products
Specific Analog Products

Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers

Application
Application
Application
Application
Application
Application
Application
Application
Application

Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
PowerlCs
Specific Analog Products
Specific Analog Products
Specific Analog Products
Specific Analog Products
Specific Analog Products
Specific Analog Products
Specific Analog Products
Specific Analog Products
Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Power ICs
Power ICs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Power ICs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
. Operational Amplifiers

Additional Availab,e Linear Devices (Continued)
!;'"

.

",'

LM759 Power Operational Ampiifier •. '•••••• ~ •.....•• Section 1
LM760 High Speed Differential C9mparatpr •••.•...••. Section 3
LM831 Low Voiiage Audio Power Amplifier .........•. Section 1
LM833 Dual Audio Operational Amplifier .•.•.•••..••• Section 1 .
LM837 Low Noise Quad Operational Amplifier .....•..• Section 1
LM903 Fluid Level Detector ..• ~ •• ; : ... .' .•.•..•...•. Section 3
LM1036 Dual DC Operated Tone/volume/Balance
Circuit ..•.....•.. '.................; ..••.•. ~' ...••. Section 1
LM 1042 Fluid Level Detector .•..•...•..•..•........ Section 3
LM1131 Dual Dolby B-Type Noise Reduction
Processor ............................. '......•... Section 1
LM1201 Video Amplifier System •...••••••••..••••.• Section 2
LM1202 230 MHz Video Amplifier System .•.•.•.•.... Section 2
LM1203 RGB Video Amplifier System .........•.•.... Section 2
LM1203A 150 MHz RGB Video Amplifier System ...... Section 2
LM1203B 100 MHz RGB Video Amplifier System ...... Section 2
LM1204 150 MHz RGB Video Amplifier System ...•... Section 2
LM1205 130 MHz RGB Video Amplifier Sy~tem with
Blanking ..........•..... : .•. ; ... '... '•......•....•. Section 2
LM1207 85 MHz RGB Video Arnpiifier System wjth
Blanking ................. ::,: ... : ....... : ...... Section 2
LM1208 130 MHz RGB Video Amplifier Syste'!1 with .
Blanking .................. ; : : ....... '........... Section 2
LM1209100 MHz RGB Video Amplifier System wi~h
Blanking .................. :;. : .... , .............. Section 2
LM1212 230 MHz Video Amplifier System w~h OSD
Blanking ............... :,., ..... : .::'.... ~ ~ ~ ...... Section 2
LM1281 85 MHz RGB Video AmplifjerSystem with On
Screen Display (OSD) •.... ::;.; ..•. : .•.•........ Section 2
LM1291 Video PLL System for Contiril!ousSync;: .
Monitors ..................... ;'... : .... :.:........ Section 2
LM 1295 DC Controlled Geometry Correctioi')' System
for Continuous Sync Monitors .'.: . .' .. : .... : ......•. Section 2
LM 1391 Phase-Locked Loop •••.••••.• : • ;' ..•.•.•••. Section 2
LM1458 Dual Operational Amplifier .... :.: ..•.•...•.. Section 1
LM1496 Balanced Modulator-Demo~ulator ...•...•.•• Section 4
LM1558 Dual Operational Amplifier ....•.••..•...•.•• Section 1
LM1575 SIMPLE SWITCHER 1A Step-Down Voltage
Regulator .......... : . : .............. , ........... Section 3
LM1575HV SIMPLE SWITCHER.1 A Step-Down
Voltage Regulator ...........•.• ;: . : .. : • , ......... Section 3
LM1577 SIMPLE SWITCHER Step-Up \(ol~qe
.
Regulator .......•......••..... , . , ..... ; •......•. Section 3
LM1577 SIMPLE SWITCHER Step-Lip Volm,ge
Regulator ................. ,' ... : '..... :'.'......... Section 3
LM1578A Switching Regulator •..•.•.•.•• ~ ......•.•• Section 3
LM1596 Balanced Modulator-Demodulator ••••.••••.. Section 4
LM 1801 Battery Operated Power Comparator .•••••••. Section 3
LM1815 Adaptive Variable Reluctance Sensor
Amplifier ......•.•.••.•...••.••.. ,' •..•.•.••..... Section 3
LM 1819 Air-Core Meter Driver ••.•••••••• : ..•••.•••• Section 3

xviii

Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Application Specific Analog Products
Operational Amplifiers
PowerlCs
PowerlCs
PowerlCs
Application Specific Analog Products
PowerlCs
Application Specific Analog Products
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products

Additional Available Linear Devices (Continued)
LM1823 Video IF Amplifier/PLL Detector System ..... Section 2
LM 1830 Fluid Detector ............................ Section 3
LM1851 Ground Fault Interrupter ................•... Section 4
LM1865 Advanced FM IF System ................... Section 4
LM1868 AM/FM Radio System ..................... Section 4
LM1875 20 Watt Power Audio Amplifier .............. Section 1
LM1875 20WAudio Power Amplifier ................. Section 1
LM1876 Dual20W Audio Power Amplifier with Mute
and Standby Modes ............................. Section 1
LM1877 Dual Audio Power Amplifier ................. Section 1
LM1877 Dual Power Audio Amplifier ................. Section 1
LM1881 Video Sync Separator ...................... Section 2
LM1882 Programmable Video Sync Generator ........ Section 2
LM1893 Carrier-Current Transceiver •................ Section 4
LM1894 Dynamic Noise Reduction System DNR® ..... Section 1
LM1896 Dual Audio Power Amplifier ................. Section 1
LM1896 Dual Power Audio Amplifier ................. Section 1
LM19211 Amp Industrial Switch .................... Section 3
LM 1946 OverI Under Current Limit Diagnostic Circuit .. Section 3
LM1949 Injector Drive Controller .............. " .... Section 3
LM1950 750 mA High Side Switch ................... Section 3
LM1951 Solid State 1 Amp Switch ................... Section 3
LM1971 /A-Pot 62 dB Digitally Controlled Audio
Attenuator with Mute ............................ Section 1
LM1972 /A-Pot 2-Channel 78 dB Audio Attenuator with
Mute ...................................•...... Section 1
LM1973 /A-Pot 3-Channel 76 dB Audio Attenuator with
Mute ..........•...........•................... Section 1
LM2416 Triple 50 MHz CRT Driver .................. Section 2
LM2416C Triple 50 MHz CRT Driver .....•........... Section 2
LM2418 Triple 30 MHz CRT Driver .................. Section 2
LM2419 Triple 65 MHz CRT Driver .................. Section 2
LM2427 Triple 80 MHz CRT Driver ............•..... Section 2
LM2524D Regulating Pulse Width Modulator ......... Section 3
LM2574 SIMPLE SWITCHER 0.5A Step-Down Voltage
Regulator ...................................... Section 3
LM2574HV SIMPLE SWITCHER 0.5A Step-Down
Voltage Regulator ............................... Section 3
LM2575 SIMPLE SWITCHER 1A Step-Down Voltage
Regulator ...................................... Section 3
LM2575HV SIMPLE SWITCHER 1A Step-Down
Voltage Regulator ............................... Section 3
LM2576 SIMPLE SWITCHER 3A Step-Down Voltage
Regulator ...................................... Section 3
LM2576HV SIMPLE SWITCHER 3A Step-Down
Voltage Regulator ............................... Section 3
LM2577 SIMPLE SWITCHER Step-Up Voltage
Regulator ...................................... Section 3
LM2577 SIMPLE SWITCHER Step-Up Voltage
Regulator ...................................... Section 3
LM2578A Switching Regulator ................•..... Section 3

xix

Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
PowerlCs
PowerlCs
PowerlCs
Power ICs
PowerlCs
PowerlCs
Power ICs
Power ICs
Application Specific Analog Products
Power ICs

Additional Available Linear Devices (Continued)
LM2587 SIMPLE SWITCHER 5A Flyback Regulator ... Section 3
LM2876 High-Performance 40WAudio Power Amplifier
with Mute ...................................... Section 1
LM2877 Dual 4 Watt Power Audio Amplifier ........... Section 1
LM2877 Dual4W Audio Power Amplifier ............. Section 1
LM2878 Dual 5 Watt Power Audio Amplifier ........... Section 1
LM2878 Dual 5W Audio Power Amplifier ............. Section 1 .
LM2879 Dual 8 Watt Audio Amplifier .•............... Section 1
LM2879 Dual 8W Audio Power Amplifier ............. Section 1
LM2889 TV Video Modulator ....................... Section 2
LM2893 Carrier-Current Transceiver .....•........... Section 4
LM2896 Dual Audio Power Amplifier ................. Section 1
LM2896 Dual Power Audio Amplifier ......•.......... Section 1
LM2900 Quad Amplifier ............................ Section 1
LM2901 Low Power Low Offset Voltage Quad
Comparator .................................... Section 3
LM2902 Low Power Quad Operational Amplifier ....... Section 1
LM2903 Low Power Low Offset Voltage Dual
Comparator .....•............•................. Section 3·
LM2904 Low Power Dual Operational Amplifier ....... Section 1
LM2907 Frequency to Voltage Converter ............. Section 3
LM2917 Frequency to Voltage Converter ............. Section 3
LM2924 Low Power Operational AmplifierlVoltage
Comparator .................................... Section 1
LM2925 Low Dropout Regulator with Delayed Reset ... Section 3
LM2925 Low Dropout Regulator with Delayed Reset ... Section 2
LM2926 Low Dropout Regulator with Delayed Reset ... Section 2
LM2926 Low Dropout Regulator with Delayed Reset ... Section 3
LM2927 Low Dropout Regulator with Delayed Reset ..• Section 3
LM2927 Low Dropout Regulator with Delayed Reset ... Section 2
LM2930 3-Terminal Positive Regulator ............... Section 2
LM2931 Series Low Dropout Regulators ......•...... Section 2
LM2931 Series Low Dropout Regulators ............. Section 3
LM2935 Low Dropout Dual Regulator ................ Section 3
LM2935 Low Dropout Dual Regulator .........•...... Section 2
LM2936 Ultra-Low Quiescent Current 5V Regulator .... Section 2
LM2936 Ultra-Low Quiescent Current 5V Regulator .... Section 3
LM2937 500 rnA Low Dropout Regulator ............. Section 3
LM2937 500 rnA Low Dropout Regulator ............. Section 2
LM2940/LM2940C 1A Low Dropout Regulators ....... Section 2
LM2940/LM2940C 1A Low Dropout Regulators ....... Section 3
LM2941 I LM2941 C 1A Low Dropout Adjustable
Regulators ..................................... Section 2
LM2984 Microprocessor Power Supply System ....... Section 2
LM2984 Microprocessor Power Supply System ....... Section 3
LM2990 Negative Low Dropout Regulator .....•...... Section 2
LM2991 Negative Low Dropout Adjustable Regulator .. Section 2
LM3001 Primary-Side PWM Driver .............•..... Section 3
LM3045 Transistor Array ........................... Section 1
LM3045 Transistor Array ........................... Section 5
LM3046 Transistor Array •...•....•.......•...••.... Section 5

xx

Power ICs
Application Specific Analog Products
Operational Amplifiers
Application Specific Analog Products
Operational Amplifiers
Application Specific Analog Products
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Application Specific Analog Products
Power ICs
PowerlCs
Application Specific Analog Products
Application Specific Analog Products
Power ICs
Power ICs
Power ICs
Application SpeCific Analog Products
Application Specific Analog Products
PowerlCs
PowerlCs
Application Specific Analog Products
Application Specific Analog Products
Power ICs
PowerlCs
Application Specific Analog Products
Power ICs
PowerlCs
Application Speeific Analog Products
Power ICs
Power ICs
PowerlCs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers

Additional Available Linear Devices (Continued)
LM3046 Transistor Array ........................... Section 1
LM3080 Operational Transconductance Amplifier ..... Section 1
LM3086 Transistor Array ........................... Section 1
LM3086 Transistor Array ........................... Section 5
LM3101 Secondary-Side PWM Controller ............ Section 3
LM3146 High Voltage Transistor Array ............... Section 5
LM3301 Quad Amplifier ............................ Section 1
LM3302 Low Power Low Offset Voltage Quad
Comparator .................................... Section 3
LM3303 Quad Operational Amplifier ................. Section 1
LM3403 Quad Operational Amplifier ................. Section 1
LM3411 Precision Secondary Regulator/Driver ....... Section 3
LM3420-4.2, -8.4, -12.6 Lithium-Ion Battery Charge
Controller ...................................... Section 2
LM3524D Regulating Pulse Width Modulator ......... Section 3
LM3578A Switching Regulator ...................... Section 3
LM3875 High Performance 40 Watt Audio Power
Amplifier ....................................... Section 1
LM3875 High Performance 56W Audio Power
Amplifier ....................................... Section 1
LM3876 High Performance 56W Audio Power Amplifier
with Mute ...................................... Section 1
LM3886 High-Performance 68W Audio Power Amplifier
with Mute ...................................... Section 1
LM3900 Quad Amplifier ............................ Section 1
LM3905 Precision Timer ........................... Section 4
LM3909 LED Flasher/Oscillator ..................... Section 4
LM3914 Dot/Bar Display Driver ..................... Section 4
LM3915 Dot/Bar Display Driver ..................... Section 4
LM3916 Dot/Bar Display Driver ..................... Section 4
LM3940 1A Low Dropout Regulator for 5V to 3.3V
Conversion ..................................... Section 2
LM4250 Programmable Operational Amplifier ......... Section 1
LM4700 Overture™ 30W Audio Power Amplifier with
Mute and Standby Modes ........................ Section 1
LM4860 1W Audio Power Amplifier with Shutdown
Mode .......................................... Section 1
LM4861 %W Audio Power Amplifier with Shutdown
Mode ...................................... ,.... Section 1
LM4862 350 mW Audio Power Amplifier with Shutdown
Mode .......................................... Section 1
LM4880 Dual 200 mW Audio Power Amplifier with
Shutdown Mode ................................ Section 1
LM6104 Quad Gray Scale Current Feedback
Amplifier .•..................................... Section 4
LM6104 Quad Gray Scale Current Feedback
Amplifi~r .•.•...•..•... ~ ........................ Section 1
LM61 04 Quad Gray Scale Current Feedback
Amplifier ..•.•••................................ Section 2
LM6118 Fast Settling Dual Operational Amplifier ...... Section 1
LM6121 High Speed Buffer ......................... Section 2

xxi

Operational
Operational
Operational
Operational

Amplifiers
Amplifiers
Amplifiers
Amplifiers
Power ICs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Power ICs
Power ICs
Power ICs
Power ICs
Operational Amplifiers

Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Power ICs
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers

Additional Available Linear Devices (Continued)
LM6121 High Speed Buffer .........•....•.......... Section 2
LM6125 High Speed Buffer .•....•....•..•... : ••.•.. Section 2
LM6125 High Speed Buffer •.....•.....••..•.••.•..• Section 2
LM6132 Dual High Speed/Low Power 7 MHz
Rail-to-RailIlO Operational Amplifier ....•.•..•.•.. Section 1
LM6134 Quad High Speed/Low Power 7 MHz
Rail-to-RaiIIlO Operational Amplifier ...•.•...•... Section 1
LM6142 Dual High Speed/Low Power 17 MHz
Rail-to-Rail Input-Output Operational Amplifier •..... Section 1
LM6142 Dual High Speed/Low Power 17 MHz
Rail-to-Raillnput-Output Operational Amplifier •..•.. Section 1
LM6144 Quad High Speed/Low Power 17 MHz
Rail-to-Raillnput-Output Operational Amplifier .....• Section 1
LM6144 Quad High Speed/Low Power 17 MHz
Rail-to-Raillnput-Output Operational Amplifier ...... Section 1
LM6152 Dual High Speed/Low Power 45 MHz
Rail-to-Raillnput-Output Operational Amplifier ...... Section 1
LM6152 Dual High Speed/Low Power 45 MHz
Rail-to-RaiIIlO Operational Amplifier •..•.........• Section 2
LM6154 Quad High Speed/Low Power 45 MHz .
Rail-to-Raill/O Operational Amplifier ...•....•..... Section 2
LM6154 Quad High Speed/Low Power 45 MHz
Rail-to-Raillnput-Output Operational Amplifier ...•.. Section 1
LM6161 High Speed Operational Amplifier ....•...... Section 1
LM6161 High Speed Operational Amplifier ........... Section 2
LM6162 High Speed Operational Amplifier .........•. Section 2
LM6162 High Speed Operational Amplifier •..•....••. Section 1
LM6164 High Speed Operational Amplifier ........... Section 1
LM6164 High Speed Operational Amplifier ........... Section 2
LM6165 High Speed Operational Amplifier •..••...•.. Section 2
LM6165 High Speed Operational Amplifier ........... Section 1
LM6171 Voltage Feedback Low Distortion Low Power
Operational Amplifier ...•..•.........•..•..•..... Section 1
LM6171 Voltage Feedback Low Distortion Low Power
Operational Amplifier ...•...•.••....•. ; ..••...•.. Section 2
LM6181 100 rnA, 100 MHz Current Feedback
Amplifier .•....•.•..••.•.•.•.•••.•.•.•.•........ Section 2
LM6181 100 rnA, 100 MHz Current Feedback
Amplifier ........................................ Section 1
LM6182 Dual 100 rnA Output, 100 MHz Dual Current
. Feedback Amplifier ..•.......••.....•.•...•..•.. Section 1
LM6182 Dual 100 rnA Output, 100 MHz Dual Current
Feedback Amplifier ....•..... ; .................. Section 2
LM6218 Fast Settling Dual Operational Amplifier ...... Section 1
LM6221 High Speed Buffer •....•••..•.•.•••••..•••• Section 2
LM6221 High Speed Buffer •..........•....•.•.....• Section 2
LM6225 High Speed Buffer .................•....... Section 2
LM6225 High Speed Buffer •........................ Section 2
LM6261 High Speed Operational Amplifier •..•....•.. Section 1
LM6261 High Speed Operational Amplifier ••••.•.•••• Section 2
LM6262 High Speed Operational Amplifier .....•...•. Section 2

XlCii

Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
. Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
.. Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products

Additional Available Linear Devices (Continued)
LM6262 High Speed Operational Amplifier •.......... Section 1
LM6264 High Speed Operational Amplifier ........... Section 1
LM6264 High Speed Operational Amplifier .........•. Section 2
LM6265 High Speed Operational Amplifier ........... Section 2
LM6265 High Speed Operational Amplifier ........... Section 1
LM6313 High Speed, High Power Operational
Amplifier ....................................... Section 1
LM6321 High Speed Buffer .......................•. Section 2
LM6321 High Speed Buffer ......................... Section 2
LM6325 High Speed Buffer ......................... Section 2
LM6325 High Speed Buffer ......................... Section 2
LM6361 High Speed Operational Amplifier ........... Section 1
LM6361 High Speed Operational Amplifier ........... Section 2
LM6362 High Speed Operational Amplifier ........... Section 2
LM6362 High Speed Operational Amplifier .........•. Section 1
LM6364 High Speed Operational Amplifier ........... Section 1
LM6364 High Speed Operational Amplifier ........... Section 2
LM6365 High Speed Operational Amplifier ........... Section 2
LM6365 High Speed Operational Amplifier .........•. Section 1
LM6511 180 ns 3V Comparator ..................... Section 3
LM7121 Tiny Very High Speed Low Power Voltage
Feedback Amplifier ............................. Section 1
LM7131 Tiny High Speed Single Supply Operational
Amplifier ....................................... Section 1
LM7131 Tiny High Speed Single Supply Operational
Amplifier ....................................... Section 2
LM7171 Very High Speed High Output Current Voltage
Feedback Amplifier ............................. Section 2
LM7171 Very High Speed High Output Current Voltage
Feedback Amplifier ............................. Section 1
LM7800C Series 3-Terminal Positive Regulator ....... Section 1
LM8305 STN LCD Display Bias Voltage Source ....... Section 2
LM8305 STN LCD Display Bias Voltage Source ....... Section 4
LM9044 Lambda Sensor Interface Amplifier .......... Section 3
LM9061 Power MOSFET Driver with Lossless
Protection ...................................... Section 3
LM13600 Dual. Operational Transconductance
Amplifier with Linearizing Diodes and Buffers ....... Section 1
LM13700 Dual Operational Transconductance
Amplifier with Linearizing Diodes and Buffers ....... Section 1
LM18293 Four Channel Push-Pull Driver ............. Section 4
LM77000 Power Operational Amplifier ............... Section 1
LMC555 CMOS Timer ............................. Section 4
LMC567 Low Power Tone Decoder .................. Section 4
LMC568 Low Power Phase-Locked Loop ............. Section 4
LMC660 CMOS Quad Operational Amplifier .......... Section 1
LMC662 CMOS Dual Operational Amplifier ........... Section 1
LMC835 Digital Controlled Graphic Equalizer ......... Section 1
LMC1982 Digitally-Controlled Stereo Tone and Volume
Circuit with Two Selectable Stereo Inputs .•........ Section 1

xxiii

Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
.Application Specific Analog Products
Operational Amplifiers
Power ICs
Application Specific Analog Products
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Power ICs
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products
Application Specific Analog Products
Operational Amplifiers
Operational Amplifiers
Application Specific Analog Products
Application Specific Analog Products

Additional Available Linear Devices (Continued)
LMC1983 Digitally-Controlled Stereo Tone and Volume
Circuit with Three Selectable Stereo Inputs ......... Section 1
LMC1992 Digitally-Controlled Stereo Tone and Volume
Circuit with Four-Channel Input-Selector ........... Section 1
LMC6001 Ultra Ultra-Low Input Current Amplifier ...... Section 1
LMC6008 8 Channel Buffer ......................... Section 4
LMC6008 8 Channel Buffer ......................... Section 2
LMC6022 Low Power CMOS Dual Operational
Amplifier ....................................... Section 1
LMC6024 Low Power CMOS Quad Operational
Amplifier ....................................... Section 1
LMC6032 CMOS Dual Operational Amplifier .......... Section 1
LMC6034 CMOS Quad Operational Amplifier ......... Section 1
LMC6041 CMOS Single Micropower Operational
Amplifier ....................................... Section 1
LMC6042 CMOS Dual Micropower Operational
Amplifier .............•...•......•••...•...•.... Section 1
LMC6044 CMOS Quad Micropower Operational
Amplifier •.•.........................•.......... Section 1
LMC6061 Precision CMOS Single Micropower
Operational Amplifier .................•.......... Section 1
LMC6062 Precision CMOS Dual Micropower
Operational Amplifier ............................ Section 1
LMC6064 Precision CMOS Quad Micropower
Operational Amplifier ............................ Section 1
LMC6081 Precision CMOS Single Operational
Amplifier ....................................... Section 1
LMC6082 Precision CMOS Dual Operational
Amplifier ....................................... Section 1
LMC6084 Precision CMOS Quad Operational
Amplifier ....................................... Section 1
LMC6462 Dual Micropower, Rail-to-Raillnput and
Output CMOS Operational Amplifier ............... Section 1
LMC6464 Quad Micropower, Rail-to-Raillnput and
Output CMOS Operational Amplifier ............... Section 1
LMC6482 CMOS Dual Rail-to-Raillnput and Output
Operational Amplifier ............................ Section 1
LMC6484 CMOS Quad Rail-to-Raillnput and Output
Operational Amplifier .•................•......... Section 1
LMC6492 Dual CMOS Rail-to-Raillnput and Output
Operational Amplifier .....................•...... Section 1
LMC6494 Quad CMOS Rail-to-Raillnput and Output
Operational Amplifier .....................•...... Section 1
LMC6572 Dual Low Voltage (3V) Operational
Amplifier ....................................... Section 1
LMC6574 Quad Low Voltage (2.7V) Operational
Amplifier ....................................... Section 1
LMC6582 Dual Low Voltage, Rail-to-Raillnput and
Output CMOS Operational Amplifier .....•..•...... Section 1
LMC6584 Quad Low Voltage, Rail-to-Raillnput and
Output CMOS Operational Amplifier ............... Section 1

lO

Parallel!
Byte-Wide

12 + Sign
8 + Sign
W

±1 LSB

On-Board
Timer, FIFO,
Sequencer

n
....

Parallel!
Byte-Wide

12 + Sign
8 + Sign
W

±1 LSB

Parallel!
Byte-Wide

12 + Sign
8 + Sign
W

±1 LSB

12 + Sign
8 + Sign
W

±1 LSB

Part

110

No.

Type

ADC0851B

ModelRes'
(Bits)

Accuracy
(Max)

Conversion
Time (Max)

Serial

8
W

±%LSB

ADC0851C

Serial

8
W

ADC0858B

Serial

ADC0858C

LM12H454

LM12H458

.;,..

LM12L458

LM12L454

LM12434

Serial

5.51'-5
2.6 )-'5

Y

5.51'-5
2.61'-5

Y

7.3 )-'5
3.5 )-'5

Y

7.3 )-'5
3.5 )-'5

Y

4

8

8

4

Y

Y

Y

Y

+5V

+5V

+5V

+5V

I

34mW

I,M

34mW

I,M

15mW

V

V,VF,EL

V, VF, EL

Comments

~

C

3V Operation

I,M

15mW

V,VF,EL

3V Operation

5.5 )-'5
2.6 )-'5

Y

4

N

+5V

I

V,M

45mW

On-Board
Timer, FIFO,
Sequencer

12 + Sign
8 + Sign
W

±1 LSB

5.5 )-'5
2.6 )-'5

Y

8

N

+5V

I

45mW

V,M

On-Board
Timer, FIFO,
Sequencer

LM12L438

Serial

12 + Sign
8 + Sign
W

±1 LSB

7.3 )-'5
3.5 )-'5

Y

8

N

+5V

I

20mW

V,M

3V Operation

Watchdog Comparison Mode
(See datasheets for details)

V:l

C

Q)
Q)

Package Codes:

N
M
V
VF
EL

Plastic DIP
Small Outline
PLCC
PQFP
CLCC

Temperatures:

C
I
M

----

O·Cto +70·C
-25·Cto +85·C
or -40·Cto +85·C
-55·Cto + 125·C

-

-------

C\:)

~
.....

n

!!on

0
;:!

_.
-·en

~

CDJl
C

o _.

::J=::!:

5.

(I)

C'D

en
....

~'<

Serial

W

~

Qg

LM12438

Resolution:

~

CD

3

en

~

n

....
0

~

:t:O

o
Q

t;tINational Semiconductor

co

UI
.....

lit
~

a.
:t:-

ADC0851 and ADC0858 8-Bit Analog Data
Acquisition and Monitoring Systems

O

oQ

General Description

Key Specifications

The ADC0851 and ADC0858 are 2 and 8 input analog data
acquisition systems. They can function as conventional multiple input AID converters, automatic scanning AID converters or programmable analog "watchdog" systems. In
"watchdog" mode they monitor analog inputs and determine whether these inputs are inside or outside user programmed window limits. This monitoring process takes
place independent of the host processor. When any input
falls outside of its programmed window limits, an interrupt is
automatically generated which flags the processor; the chip
can then be interrogated as to exactly which channels
crossed which limits.

II Resolution

co
co

UI

8 Bits
± % LSB or ± 1 LSB
50 mW
18 p.s/Channel
2/.1os/Limit

II Total error
II Low power
II Conversion time
II Limit comparison time

Features
II Watchdog operation signals processor when any

channel is outside user programmed window limits
II Frees microprocessor from continually monitoring

analog signals and simplifies applications software
II 2 (ADC0851) or 8 (ADC0858) analog input channels

The advantage of this approach is that its frees the processor from having to frequently monitor analog variables. It
can consequently save having to insert many A/D subroutine calls throughout real time application code. In control
systems where many variables are continually being monitored this can significantly free up the processor, especially
if the variables are DC or slow varying signals.

II Single ended or differential input pairs

II COM input for DC offsetting of input voltage
II 4 (ADC0851) and 16 (ADC0858), 8-bit programmable

limits
II NSC MICROWIRETM interface

III Power fail detection

The Auto AID conversion feature allows the device to scan
through selected input channels, performing an A/D conversion on each channel without the need to select a new
channel after each conversion.

II Auto AID conversion feature
II Single 5V supply
II Window limits are user programmable via serial inter-

face

Applications

•

II Instrumentation monitoring and process control
II Digitizing automotive sensor signals
II Embedded diagnostics

Simplified Block Diagram
RAM
HIGH LIMIT

LOW LIMIT
D7
DO

1-----1!

1-----1:~ 'i""

I---;:!
~::::~:~
.o.:.:r--'-____-'
L-____

15

+- Vee
+- DGND

14

COM-----'

~:::O~il ONLY)

vREr - - - - ,

AGND-----'

~----------~
c~--------------------~
m----------~
osc---+I

CONTROL LOGIC
SHIFT REGISTERS
CONTROL REGISTERS
TIMING GENERATOR
POWER ON RESET

COMPHJ

1---.

DO
EOC

1---.00
TLlH/ll021-22

FIGURE 1

1-5

co
co

In

.---------------------------------------------------------------------------------~

g

Connection Diagrams

cc

ADC0851
2-Channel MUX
Dual-In-Llne Package

"cas

....

ADC0858
S-Channel MUX
Dual-In-Line Package

In

8
c
cc

20

CHO

16

DGND

Vee

OSC

2

15

COt.!PH

OSC

cs

3

14

COt.!PL

cs

CH2

CLK

4

13

CHO

CLK

CH3

DI

5

12

CHI

DI

CH4

DO

6

11

COt.!

DO

CH5

iNi'

7

10

AGND

iNi'

CH6

EOC

8

9

VREF

EOC

CH7

Vee

TUH/11021-1

Top View

.19

2

CHI

DGND

COM

VREF

AGND
TL/H/11021-2

Top View

ADC0851 Pi..CC Package
I~

'-'
VI
0

<.>
<.>

>

c
z
co
C

'"'-'0

CLK
NC

5

01

DO

7

iNT

8

ADC0858 PLCC Package
'-'
VI.
S ~ ;;;
I~ '0

:J::

"-

>

18

COMPL

17

NC

16

CH 0

15

CHI

'-'

'-'

ClK

4

18

CH2

01

5

17

CH3

DO

16

CH4

iNT

15

CH5

14

CH 6

EOC

8

NC

'-'
Z

...'-'
0

~

C

... z

>tIt! ~

<>
:z:
<>

:::IE
0

'"

'-'

~

c

:::IE

...

0
:J::
>'tJ ~" '-'
'-'

TL/H/11021-4
TL/H/11021-3

Top View

Top View

Ordering Information
Industrial
(-40'C:S;: TA:S;: +85'C)

Military .

Package

(-55'C :s;: TA ,;; + 125'C)

Package

ADC0851 BIN,
ADC0851CIN

N16E,16-Pin
Plastic DIP

ADC0851 CMJ/883

J16A,16-Pin
Ceramic DIP

ADC0858BIN,
ADC0858CIN

N20A, 20-Pin
Plastic DIP

ADC0858CMJ/883

J20A, 20-Pin
Ceramic DIP

ADC0851BIV,
ADC0851CIV

V20A, 20-Lead
PLCC

ADC0858BIV,
ADC0858CIV

V20A, 20-Lead
PLCC

1-6

»
c

Absolute Maximum Ratings (Notes 1 &2)

Operating Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage, Vee

4.5Vt05.5V

Temperature Range
ADC0858CMJ/883

TMIN ,,;; TA ,,;; TMAX
-55°C,,;; TA ,,;; + 125°C

ADC0851CMJ/883

-55~C";;

6.5V

Supply Voltage, Vee
Voltage at Logic and Analog
Inputs (Note 3)

\

-0.3V to Vee + 0.3V

Input Current per Pin

±5mA
±20mA

Input Current per Package
Storage Temperature

- 65°C to + 150°C

Package Dissipation
at T A = + 25°C (Board Mount)

500mW
800mW

Lead Temperature (Soldering, 10 Sec.)
Dual-In-Line (Plastic)
Dual-In-Line (Ceramic)

+ 260°C
+ 300°C

ESD Susceptibility (Note 4)

(Notes 1 & 2)

TA";; + 125°C

ADC0858BIN, ADC0858CIN

-40°C";; TA";; +85°C

oo

Q)

U1
.....
D)

:::J
C.

»
C

ADC0851BIN, ADC0851CIN

-40°C,,;; TA";; +85°C

oo

ADC0858BIV, ADC0858CIV

-40°C,,;; TA";; +85°C

U1

ADC0851 BIV, ADC0851CIV

-40°C,,;; TA";; +85°C

Q)
Q)

2000V

DC Electrical Characteristics
The following specifications apply for Vee = + 5 VDe, VREF = + 4.5 VDe, AGND = DGND = OV and lose = 1 MHz (Rex! =
3.16 kO, Cext = 170 pF) unless otherwise specified. Boldface limits apply for T A = TJ = T MIN to T MAX; all other limits apply
at TA = TJ = + 25°C.
Parameter

Typical
(Note 5)

Conditions

Limit
(Note 6)

Units
(Limits)

±Y:,
±1
±1

LSB (Max)
LSB (Max)
LSB (Max)

±2.5
±2.5
±2.5

±10
±20
±20

mV(Max)
mV(Max)
mV(Max)

6

3.5
10

kO(Min)
kO (Max)

GND - 0.05

CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted Error (Note 7)
ADC0851/8/BIN, ADC0851/8/BIV
ADC0851/8/CIN, ADC0851/8/CMJ,
ADC0851/8/CIV
Comparator Offset
ADC0851/8/BIN, ADC0858BIV
ADC0851 18/CIN, ADC0851 18/CMJ,
ADC0858CIV
VREF Input Resistance
Common Mode Input Voltage
(Note 8)

All MUX Inputs
and COM Input

DC Common Mode Error

= -0.05Vto
VREF = 4.75V
Vee = 5V ± 5%
VREF = 4.5V
Vee = 5V ± 10%
On Channel = 5V
Off Channel = OV
On Channel = OV
Off Channel = 5V
On Channel = 5V
Off Channel = OV
On Channel = OV
Off Channel = 5V

Power Supply Sensitivity

IOFF,
Off Channel
Leakage Current
(Note 9)
ION,
On Channel
Leakage Current
(Note 9)

aVeM

1-7

+5.05V

Vee + 0.05

V (Min)
V (Max)

±1/16

±114

LSB (Max)

±1/16

±114

LSB (Max)

±1/16

±112

-0.01

-3

J.'A(Max)

+0.01

+3

J.'A(Max)

+0.01

+3

J.'A(Max)

-0.01

-3

J.'A(Max)

II

CD

II)

CD

o

g
cc

".,...c

DC Electrical Characteristics

(Continued)
The following specifications apply for Vcc = + 5 Voc, VREF = + 4.5 Voc, AGND
3.16 kO, Cext = 170 pF) unless otherwise specified. Boldface limits apply for TA
at TA = TJ = + 25°C.

CIS

Parameter

Typical
(Note 5)

Conditions

II)

~
cc

= DGND = OV and fosc = 1 MHz (Rex! ":'
= TJ = TMIN to TMAX; all other limits apply
Limit
(Note 6)

Units
(Limits)

2.2

V (Min)

0.8

V(Max)

0.005

3

p.A(Max)

-0.005

-3

p.A(Max)

2.4
4.2

V (Min)
V (Min)

0.4

V (Max)

-0.1
0.1

-3
3

p.A(Max)
p.A (Max)

-14

-6.5

mA(Min)

DIGITAL CHARACTERISTICS
logic "1" Input
Voltage, VIH

Vcc

=

5.5V

logic "0" Input
Voltage, VIL

Vee

=

4.5V

logic "1" Input
Current, IIH

VIN

=

Vee

logic "0" Input
Current, IlL

VIN

=

OV

logic "1" Output
Voltage, VOH
(Except INn

Vcc = 4.5V
lOUT = -360 p.A
lOUT = -10 p.A
lOUT = 1.6mA
Vcc = 4.5V

. logic "0" Output
Voltage, VOL
TRI-STATE® Output
Current (DO)

~

ISOURCE
(Except INn

VOUT Short to GND

ISINK

VOUT Short to Vee

16

8

mA(Min)

Supply Current, Icc
ADC0851 or ADC0858

fCLK = 1 MHz
fCLK = 2 MHz
(Note 10)

7
7.2

10

mA(Max)
mA

=

VOUT
VOUT

L.ogic "1" (5V)
O.4V
5V

=
=

AC Electrical Characteristics

The following specifications apply for Vcc = + 5 Voc, VREF = + 4.5 Voc, AGND = DGND = OV, fCLK = 1 MHz, tr = tf =
5 ns unless otherwise specified. Boldface limits apply for TA = T J = 'TMIN to T MAX; all other limits apply at TA =, TJ = 25"C.
Symbol
fCLK

Parameter

Conditions

Data Clock Frequency

Typical
(N~te5)

Limit
(Note 6)

Units
(Limits)

1

2

MHz (Max)

40
60

% (Min)
·%(Max)

30

70

ns(Min)

5

30

ns(Min)

80

200

ns(Max) ,

Clock Duty Cycle
(Note 11)
tSET-UP

~ Falling Edge or
Data Input Valid to
. ClK Rising Edge

tHOLO

Data Input Valid after
ClK Rising Edge

tpOl, tpDO

ClK Rising Edge to
Output Data Valid

CL

=

100pF

1-8

AC Electrical Characteristics (Continued)
=

=

=

=

The following specifications apply for Vee = + 5 VOC, VREF
+4.5 VOC, AGND
DGND = OV, fClK
1 MHz, tr = tf
5 ns unless otherwise specified. Boldface limits apply for T A = T J
T MIN to T MAX; all other limits apply at T A = T J
25°C.

=

Symbol
tlH, tOH

Parameter

Typical

Conditions

= 10'0 pF, R =

Rising Edge of CS to

C

Data Output Hi-Z

(See TRI-STATE

=

(Note 5)

Limit
(Note

6)

Units
(Limits)

2k

90

200

ns (Max)

tEOC

Oscillator Clock Freq.

Rext

(Analog Timing)

Cext

=
=

3.16 kO
170 pF

1

1.4
0.6

CSto End of

....
I»

::s

Q.

»
C
oo

MHz (Max)
MHz (Min)
OSCClock

Conversion Delay

Periods

1
2
tConv

CD
UI

CD
UI
CD

Test Circuits)
fosc

§

Conversion Time

Min
Max
OSCClock
Periods

tcs-INT

CS to Interrupt Delay

CIN

Capacitance of

60

Logic Input
COUT

Capacitance of
Logic Output

17
18

(Max)

120

ns(Max)

(Min)

5

pF

5

pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. but do not guarantee specific performance limits. For guaranteed specifications and test conditions. see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.

Nole 2: All voltages are measured with respect to ground (AGND

= DGND = OV),

Nole 3: All of the analog and digital input pins are internally diode clamped to the supply pins. Should the applied voltage at any pin exceed the power supply
voltage, the additional absolute value of current at that pin (caused by the forward biasing of the internal diodes) should be limited to 5 mA or less.
Note 4: Human body model, 100 pF discharged through a 1.5 kll resistor.
Note 5: Typical specifications are at

+ 25'C and represent the most likely parametric norm.

Nole 6: Tested limits are guaranteed to National's AOQl (Average OutgOing Quality Level).
Note 7: Total unadjusted error includes comparator offset, ADC linearity and multiplexer error, and, is expressed in LSBs.
Note 8: Two on·chip diodes are tied to each analog input. The diodes will forward conduct for analog input voltages one diode drop below ground or one diode drop
above Vee. Care should be exercised when operating the device at low supply voltages (e.g., Vee = 4.5V) because high analog inputs (5V) can cause the input
diodes to conduct, especially at elevated temperatures. This will cause errors for analog inputs near full scale. The specification allows 50 mV forward bias of either
clamp diode. Thus as long as VIN or VREF does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 Voe
to 5 Voe input voltage range will Iherefore require a minimum supply voltage of 4.950 Voe.
Note 9: Leakage current is measured with the oscillator clock disabled.
Nole 10: Measured supply current does not include the DAC ladder current.
Nole 11: A 40% to 60% clock duty cycle range ensures proper operation at all clock frequencies.

1-9

•

:g

co

8c

Typical Performance Characteristics

cc
'tJ
C

ca
an
~

Offset Error vs
Reference Voltage

-U
C

cc

no

HH--+-++-+ Vee = 5V

HH-+-++-+ fosc =1MHz

~

:1:0.6

Total Unadjusted Error
vs Temperature

Vee = 5Y
fose =,IIIHz

Vee = 5V

TA = 250C

fose = 1MHz

~ to.4

~

o

2

3

]'
1;

-...;~po.

r-'"

5. V

V = V
4.

0.8

1\

2.0

.:!.

~

105

145

v

--......

~

t-....

~

>::~

~

TA=25"C_

\\.

1.5

r\

~

1.0

"-

0.5

t-....

.....

-IS

2S

65

IDS

145

R xl=5.lkll

o

TEMPERATURE (OC)

R. xt = 2.5 k.n.

Rut = 3.3 kJl

~

I

o

0.7
-55

65

Vce= 5V _

Cnt = 170pF'

~,

l;l
0

25

TEMPERATURE (OC)

2.5

1.0
0.9

-15

OSC Frequency vs
Rexl and Cext

Rext= 3,16 k4

.:!.

~

-

REFERENCE VOLTAGE (V)

1.2

!!l

-55

4

OSC Frequency
vs Temperature

~

=•.75V

o

o

4

_REFERENCE VOLTAGE (V)

]'

.....

1'-

::l iO.2

O~~-L~~~~-L~

~
~
1.1

VREF

I\,

~

I-HH--+-+-+-++-t--I
~ to.4 I-Hf*l--+-+-+-++-t--I
~ :to.3 I-HH"'cl-+-+-++-t--I
o to.2 I-HH--+t-....-"'Iod-r-...-++-t--I
to.1 I-HI--l--+-+-+=+,,*,-I--I
~ :1:0.5

3

\

~

~~ :1:0.6 I-HH--+--+-+-+++-+

I

\

~'0.8

TA = 250C

o

Linearity Error vs
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Timing Diagrams
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TL/H/11021-10

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Timing Diagrams for ADC0851 and ADC0858
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ADC0851 Programming Chart

cr:

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Receive (01)

Function

Transmit
(DO)

, Mode

Comments

"....cca

Watchdog

1000

C11 ... CO

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Write 1 Limit

1001

A3 ... AO, LO ... L7

g

1 AID Conversion

1010

13 ... 10

DO ... D7, 13 ... 10

Send Data after Conversion

Read 1 Limit

1011

A3 ... AO

LO ... L7

Send Limit from RAM

Test

1100

Write all Limits

1101

4 Bytes, LO First

Auto AID Convert

1110

C11 ... CO

Read all Limits

1111

In

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T3 ... TO, C11 ... CO, P, S3 ... SO

Send Data after INT
Write Limit to RAM

Do Not Use (See Text)
Write All Limits to RAM
DO ... D7, 13 ... 10

Continuous Conversion

4 Bytes, LO First

Send all Limits from RAM

ADC0858 Programming Chart
Receive (01)

Function

Transmit
(DO)

Mode
Watchdog

1000

C11 ... CO

Write 1 Limit

1001

A3 ... AO, LO ... L7

T3 ... TO, C11 ... CO, P, S15 ... SO

Comments
Send Data after TNT
Write Limit to RAM

1 AID Conversion

1010

13 ... 10

DO ... D7, 13 ... 10

Send Data after Conversion

Read 1 Limit

1011

A3 ... AO

LO ... L7

Send Limit from RAM

Test

1100

Write all Limits

1101

16 Bytes, LO First

Auto AID Convert

1110

C11 ... CO

Read all Limits

1111

Do Not Use (See Text)
Write all Limits to RAM
DO ... D7, 13 ... 10

Continuous Conversion

16 Bytes, LO First

Send all Limits from RAM

Serial Communication Bit Order
Bit Order
Information Type

AOC0851
First

Limit Data
AID Conversion Data
Limit Address
Status
Channel Tag
Channel Configuration
Channel Information
Mode
Power Fail

LO
DO
A3
S3
T3
C11
13
M3

I
...

I

...

...
...

...
...
...
...
P(One Bit)

ADC0858
Last

Firat

L7
D7
AO
SO
TO
CO
10
MO

LO
DO
A3
S15
T3
C11
13
M3

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...
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1·16

Last
L7
D7
AO
SO
TO
CO
10
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Pin Descriptions
Vee

OSC

CS

Positive power supply pin. Bypass to analog
ground with a 0.1 ,...F ceramic capacitor in
parallel with a 10 ,...F tantalum capacitor.

DI
DO

TRI-STATE data output pin.

INT

This is the active low interrupt pin that indicates that at least one analog input channel
voltage level has exceeded the programmed window limits. Since this pin has
an open drain output, an external pull up resistor is required. This allows many devices
to be wire-ORed together using a single
pull·up resistor.

EOC

Analog ground reference.

DGND

Digital ground reference for the logic inputs.
Both AGND and DGND should be at same
'potential.
This is the analog reference pin. The voltage applied to this pin sets the full scale
AID conversion range. Recommended voltages applied to this pin range from 1V to
Vee. Bypass to analog ground with a 0.1 ,...F
ceramic capacitor in parallel with a 10,...F
tantalum capacitor.
The COM pin functions as an inverting differential input common to all analog inputs
when each channel is configured as a single-ended channel. If the input channels are
programmed as differential pairs then the
COM input has no effect.
'

Input/Output pin used to generate internal
timing for AID conversion. This pin is connected to an external resistor and capacitor
to set the oscillation frequency for analog
timing (see Figure 12).
This is the chip select input pin. It must be
held low while data is transferred to or from
the ADC0851 /8 (see Timing Diagram).
The serial clock input pin is used to clock
serial data either into the data input pin (DI)
or out of the data output pin (DO). Input data
is loaded on the rising edge of ClK and the
output data is valid at the falling edge of
ClK.
Serial data digital input pin.

ClK

AGND

COM

CHO-CH1
(ADC0851)
CHO-CH7
(ADC0858)
COMPl,
COMPH

End of conversion output pin. The low state
indicates that an AID conversion is in progress. The EOC pin goes high when the conversion is completed.

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CHO-CH7 are analog input channels which
can be configured as single ended inputs or
as differential pairs. The analog input voltage should stay within the power supply
range.
These output pins are available only on the
ADC0851. During "Watchdog" operation, if
either of the inputs exceeds the window limits, not only is an interrupt generated but
also the COMPl and COMPH pins go low to
indicate whether the upper or lower boundary was exceeded (See applications section
for more information.)

III

1-17

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the input channel and the limit (upper or lower) that will be
preset, and the last eight bits set the limit (or comparator
threshold).
The limit data representing the input voltage limit (or comparator threshold) is expressed as per the following equation:

General Overview
The ADC0851/58 is a versatile microprocessor-compatible
data acquisition system with an on-board watchdog capability. The device is capable of synchronous serial interface
with most microprocessors and includes a mUltiplexer, a
RAM and a successive approximation register. The
ADC0851 and the ADC0858 have two and eight input channels respectively.

VLlM = VREF WZ L7
where L7 is the MSB.

+ v.. L6 + ... + 1;256 LO)

Data Input (DI) Word-ADC0851 or ADC0858

1.0 Modes of Operation

C~~L~~O~~IT[

The device can 'be used in anyone of the eight modes of
operation listed below. A mode is selected by taking c:;s low
and providing the IC with an input word whose first four bits
specify the desired mode (see the ':Programming Charts"
for the mode selection codes):

ONE

c==LlWIT OAYA

tmlORY ADDRESS (TABLE ][A FOR ADCOS51,

TABLEIB fOR ADCOS58)

TUH/11021-24

1.1 WATCHDOG MODE
This mode of operation allows the device to operate as a
digitally-programmable window comparator. The analog input voltage at each channel is compared against the upper
and lower boundary limits stored in an internal RAM. When
an input falls outside of its programmed window limits, an
interrupt is generated. The microprocessor can then pull CS
low which causes the device to produce a bit stream that
indicates which channel{s) crossed which limit{s).

1_3 WRITE ALL LIMITS TO RAM
This mode is used to update each pair of lower and upper
limits for all channels. This is accomplished by a stream of
input data whose first four bits select the mode of operation
followed by four bytes of limit data for the ADC0851 and
sixteen bytes of limit data for the ADC0858.
The limit data representing the input voltage limit (or comparator threshold) is expressed as per the following equation:

The watchdog mode is selected by taking c:;s low and shifting in the four bit word (1 0 0 0) followed by a twelve bit
word that configures the analog inputs to operate either as
single-ended or as differential pairs (CHO-CH1, CH2-CH3,
etc.). When a channel is operating single-ended, its input
voltage is compared to the upper and lower limits stored in
RAM for that input. When two inputs are configured as a
differential pair, the limits stored in the RAM for the channel
with the lower number will be compared against the differential input voltage. For example, the differential voltage
CHO-CHI will be compared with the lower and upper limits
for CHO. The limits are programmed using the "write one
limit to RAM" or "write all limits to RAM" mode.

VLlM = VREF (% L7

+ v.. L6 + ... + 1;256 LO)

where L7 is the MSB.
Data Input (DI) Word-ADC0851 or ADC0858
lAfIT 3 (Cfll - UL) ADC0851
LMT 15 (CH7 - UL) - - ADCOB58-----,.

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L_----SELECT WRITE ALL LIIITS WOllE

TUH/11021-25

1.4 READ ONE LIMIT FROM RAM
When the ADC0851/8 is configured in this mode, the user
can read back an 8-bit limit word from the RAM memory
location pointed to by the limit address. An 8-bit input word
selects the mode (1 0 1 1) and the memory location to be
read.
Data Input (DI)-ADC0851 or ADC0858

Data Input (DI) Word-ADC0851 or ADC0858
c==SElECT WATCHDOG MODE

CHANNEL CONFIGURATION

TUH/11021-23

I, 1 I, I, j..I.++ol
0

1.2 WRITE ONE LIMIT TO RAM
This mode allows the user to update a single limit for one of
the input channels. This is accomplished by using a 16-bit
stream of input data (see "Programming Chart"). The first
four bits (1 0 0 1) select the mode, the next four bits select

I

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..EMORY ADDRESS (TABLE ][A fOR ADC0851.

TAlLl :IB FOR ADC0B58)
' - - - - - S a I C T READ ONE llYn' !WDE

TL/H/11021-26

1-18

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1.0 Modes of Operation (Continued)
the OSC pin to ground causes the device's internal oscillator to generate the OSC clock signal for AID conversion
and watchdog timing. With Rext = 3.16 kn and Cext =
170'pF, the OSC clock frequency is approximately 1 MHz.
Note that internally, ADC0851 18 divides the OSC clock frequency by two. An AID conversion is completed in eighteen
OSC clock periods maximum. It should be noted that the
OSC pin of the ADC0851 18 should not be driven by an external clock.

1.5 READ All liMITS FROM RAM
This mode of operation allows the device to serially output
8-bit limit data from each memory location in succession
starting with CHO-Iower limit (see Section 2.4 under interface considerations).
Data Input (01) Word-ADC0851 or ADC0858

11111111 I
I

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SELECT READ ALL

L1~!TS NODE

1.6 INITIATE ONE AID CONVERSION

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3.0 Programming Information

11 I 011 I 0113 112 111 110I

The ADC0851 and ADC0858 communicate data serially
over the 01 (data input) and DO (data output) lines. The data
format for the input and output words for various modes of
operation are shown in the "programming charts."

I
L-----CHANNEL INFORMATION

'------SELECT ONE A/D CONVERSION MODE

TLlH/ll021-2B

There are nine types of data as shown in the "serial communication bit order" table. The order in which data is communicated is MSB first in all but two cases: Limit data and
AID conversion data. The various data types are described
below.

1.7 INITIATE AUTO AID CONVERSION
When configured in this mode, an AID conversion is done
on a channel or channel pair and after the output data is
transmitted, conversion begins on the next subsequent
channel or channel pair. In this mode the device continually
scans through the input channels making AID conversions
unless the device's mode of operation is changed. The first
four bits of the input word select the mode of operation and
the next twelve bits assign the multiplexer configuration.

3.1 lIMITDATA(lO.l1 •••• l7)
Limits on the AOC0851 18 are 8 bits in width and can either
represent an upper or lower boundary limit. Limit data can
either be written (in the "write one limit" or "write all limits"
mode) to or read (in the "read one limit" or "read all limits"
mode) from the limit RAM. Being able to read back the limit
data allows system testability, and it also allows independent software routines to see what window limits were previously written to the Chip. During watchdog operation, a programmed limit must be crossed in order to cause an interrupt.

Data Input (01) Word-ADC0851 or ADC0858

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Note that input data is loaded at the rising edge of ClK
while the output data is valid at the falling edge of ClK. All
digital timing such as data set-up and hold times and delays
are measured with respect to the ClK signal. The OSC
clock and ClK frequencies need not be the same.

Data Input (01) Word-ADC0851 or ADC0858

I

....

I»

An external clock Signal is applied to the ClK pin (pin 4) of
the ADC0851 18. The ClK Signal is used to clock serial data
either into the data input pin (01) or out of the data output
pin (DO).

Tl/H/ll021-27

At any time, the user can initiate an AID conversion on any
input channel. Note that the input channels may be configured as Single ended or differential inputs. The first four bits
of the input word select the mode of operation and the next
four bits assign the multiplexer configuration.

I

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SELECT AUTO A/D CONVERSION MODE

'I--..L.....---'I

11 11 11 I a 10+101091 OB I071 061 csl 041 031 021 011 I
CO

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IL-----CHAHNEL COHRGURATIOH

3.2 AID CONVERSION DATA (DO. 01 •••• 07)

TL/H/ll021-29

There are two AID conversion modes (One A/D conversion
and Auto AID conversion) that produce 8-bit conversion
data. During either type of AID conversion, a single-ended
analog input or a differential analog input pair is digitized to
produce this conversion data.

1.8 TEST MODE
This mode is used to test the ADC0851 /8 at the factory and
is not intended for normal use. If this mode is aCCidentally
selected, the supply voltage must be disconnected and then
reconnected to reset the device.

3.3 liMIT ADDRESS (A3. A2 •••. AO) .

2.0 Conversion Timing vs
Serial Interface Timing

The limit address pOints to the location, within the limit
RAM, to which limit data is sent or from which it is received.
Limit address is used in the "write one limit to RAM", "write
all limits to RAM", "read one limit from RAM" or "read all
limits from RAM" mode. There are two addresses for each
analog input; the even addresses correspond to the lower

Note that the ADC0851 /8 uses two clock signals for proper
operation. Connecting an external resister (Rextl from the
OSC pin (pin 2) to Vee and an external capacitor (Cext) from

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thirty two oscillator clock periods for the AOC0858 respectively (see the Timing Diagram, "Read Power Flag after
Power Up ADC0851/8"). When changing to a new mode of
operation, the device readies itself to read a new input word
clocked in at the data input (01) pin. The input word configures the new mode of operation.

3.0 Programming Information
(Continued)
limits while the odd addresses correspond to the upper limits. The ADC0851 and ADC0858 both use four bits (AS-AO)
to address the limit RAM but the ADC0851 only decodes
the two LSBs while ignoring the two MSBs. The ADC0858
decodes all four bits thus yielding sixteen limit addresses.

Functional Description

3.4 STATUS AND CHANNEL TAG DATA
(S3, S2, ••• ,SO, ADC0851j S15, S14, ••• , SO, ADC0858)
(T3, T2, ••• , TO)
.

The simplified block diagram (Figure 1, front page) shows
the various functional blocks. The ADC0851 and ADC0858
include 2- and 8-channel analog input multiplexers respectively. Using the appropriate serial input word at the Data
Input (01) pin, the analog channels can be configured for
either single-ended operation or differential mode operation.
The COM input pin provides additional flexibility since the
COM pin functions as an inverting differential input common
to all analog inputs when each channel is configured as a
single ended channel. Applying an external DC voltage at
the COM pin allows offsetting the single ended analog input
voltages from ground (pseudo-differential mode). Input
channels that are configured as differential pairs will be un·
affected by the voltage at COM pin.

During watchdog mode, immediately after one analog input
is determined to be outside of its programmed window limit,
its channel number is stored in the channel tag register and
the remaining inputs are checked one more time and the
pass/fail status of each input is stored in the status register.
When the microprocessor receives the interrupt signal, it
can read the status and channel tag data by pLiliing
low
and clocking out the data.

-es

3.5 CHANNEL CONFIGURATION DATA
(C11, C10, ••• CO)
The channel configuration data assigns the configuration of
the multiplexer. The data is comprised of twelve bits with
each group of three bits addressing an analog input channel
pair. Each channel pair can be configured for single-ended
operation, differential operation, one single ended channel
and one disabled channel, or both channels disabled. The
channel configuration data is required when the device is in
.
the watchdog or Auto AID conversion' mode.

The ADC0851/8 includes an 8-bit DAC, a comparator and
an 8-bit successive approximation register. An analog-to·
digital conversion can be initiated at any time on anyone of
the input channels. The 8-bit digital word corresponding to
the analog input voltage is serially clocked out at the Data
Output (DO) pin. In addition to its use as a multiplexed AID
converter, the ADC0851/8 may also be used as a window
comparator in the watchdog mode. An upper and lower
boundary limit corresponding to each analog input voltage
may be stored in an internal RAM. The RAM consists of
sixteen memory locations, each 8 bit wide; however, for the
ADC0851 only four memory locations are used. Limit data
can either be written into or read back from the RAM. The
read/write capability allows independent software routines
to read back previously programmed window limits. Furthermore, currently programmed limits may also be read back to
ensure system testability. An address register holds the addresses of the RAM's memory locations where data may
either be stored or retrieved from.

3.6 CHANNEL INFORMATION DATA
(13,12, ••• 10)
This data is used by the AOC0851 /8 only when the device is
configured in the "One AID conversion" mode. The channel information data assigns the configuration olthe multiplexer.
' .
3.7 MODE ADDRESS (M3, M2, ••• MO)
The input word (DI) configures the ADC0851/8 for various
modes of operation. The first four bits of the input word
constitute the mode address which specifies the mode of
operation.

When the device is operated in the watchdog mode (as described in the "general overview" section), the analog inputs are continually polled and compared against their respective window limits. Once an input signal that has exceeded either boundary limit is detected, a "1" is stored in
the MSB position in a 16-bi~ status register, indicating a limit
crossing. Note that the ADC0851 uses only four locations of
the status register because it has only four limits. In addition, the tag register is updated so that the register holds the
address which indicates the channel and the corresponding
upper or lower limit that was crossed. After the first limit
crossing is detected, the device cycles through the remairiing limits and compares them against their respective input
signals. If any additional limit crossing is or are detected
then a "1" is stored in the appropriate locations of the
status register. After the completion of this operation, the
interrupt pin (TN'i') goes low, providing a flag to a microprocessor. The microprocessor can then cause the serial status
data to be shifted out by bringing the CS line low. Together
with the status and tag bits, the microprocessor can determine which channel exceeded which limit. If desired the mi-

3.8 POWER FAIL BIT (P)
The ADC0851/S is automatically configured to the watchdog mode upon power-up and an interrupt is immediately
generated after
is pulled high. Pulling CS low produces a
17-bit data stream. The seventeenth bit of the output word
DO in the watchdog mode is the power fail bit, P. If the
output data is read after power-up then P will be at logical
"1". Changing the mode of operation resets P to logical
"0". Any subsequent power failure will cause the device to
configure in the watchdog mode upon power-up with P at
logical "1".

-es

4.0 Initialization after Power-Up
The ADC0851/8 is automatically configure!l in the watchdog mode upon power-up. After reading the power fail bit
CS is pulled high. To exit the watchdog mode and to change
should be high less than
to a new mode of operation,
eight oscillator clock periods for the ADC0851 and less than

-es

1-20

Functional Description

of operation, with the first bit of the input word always being
a logic "1". Table I shows the mode addresses for selecting
the different modes of operation.

(Continued)

croprocessor can then initiate an AID c~mversion on any
channel(s). The ADC0851 includes two additional output
pins, COMPl and COMPH. During watchdog operation, if
either of the inputs exceeds its respective window bounds
then not only is an interrupt generated but a logic low at
COMPl or COMPH indicates whether the lower or upper
boundary was crossed.
A mode register within the ADC0851 /8 allows the device to
be used in anyone of the eight modes of operation as described in the "general overview" section.
The features described make the ADC0851 18 ideal for use
in microprocessor-based automotive, instrumentation and
control applications. Such applications often require monitoring of various transducer signals and comparison against
pre-programmed window limits. With its watchdog operation, the ADC0851 /8 frees up the microprocessor from having to continually monitor the analog variables; the microprocessor is interrupted only when the input signal crosses
the preset bounds. Furthermore, the window limits can easily be changed with simple software control.

, TABLE I. Modes of Operation
Mode Address

I. Digital Interface Considerations

I»
::J

a.

Mode

>C

M3

M2

M1

MO

1

0

0

0

Watchdog

1

0

0

1

Write One Limit

1

0

1

0

One AID Conversion

1

0

1

1

Read One Limit

1

1

0

0

Test (for Factory Use Only)

n
CI

1

1

0

1

Write All Limits

1

1

,1

0

Auto AID Conversion

1

1

1

1

Read All Limits

First consider the case of initial power up. After power is
applied, CS should be brought high. Bringing CS high causes the INT pin to go low, which signals the microprocessor
that a failure has occurred. The microprocessor can then
interrogate the device as to the type of failure by bringing
CS low. When CS goes low, it resets the INT pin to high and
the output data 'is read starting at the first rising edge of
clock (ClK) after CS has gone low. Since this is the first
read cycle after power up, the power flag bit, P, is set high
and appears at the rising edge of the seventeenth clock
cycle after CS low is detected (Figure 2). After the power
flag is read by the microprocessor, CS is taken high. Note
that the duration for which CS remains high (after the power
flag is read) must be less than eight oscillator clock periods
for ADC0851 and less than thirty-two oscillator clock periods for ADC0858. This ,is required to interrupt the device
from watchdog mode so that when CS goes low, the device
reads a valid data input (01) word and configures to a new
mode.

The ADC0851 and ADC0858 communicate data serially
over the 01 (Data Input) and DO (Data Output) pins. The
data transfer is synchronous with the external clock (ClK)
signal and is clocked in or out of the device at the rising
edge of clock. Note that although the output data is clocked
out starting at the rising edge of ClK, the data is valid at the
falling edge of ClK.
All internal timing in the device is with respect to the oscillator clock. The oscillator frequency is set by connecting a
resistor from the OSC pin (pin 2 for ADC0851 or ADC0858)
to Vee and a capacitor from the OSC pin to ground. The
period of the oscillator clock will determine the A/D conversion time and chip select (CS) high duration as will be discussed in the following sections.

1.0 Modes of Operation
To initiate the operation of the device in anyone of the eight
modes, the chip select (CS) line must go low. After a CS low
is detected, serial input data at the 01 pin is clocked in starting at the first rising edge of the serial clock. The first four
bits of the input word are reserved for specifying the mode

During normal operation, the power flag bit is reset to zero
after the first "read" cycle and will be updated to a "1" only
if a power interruption occurs.

~
r--lL_____________________1
I;.. . ~:~~l::'~ ~~~ ~~~KBE

TO CHANGE TO A NEW MODE Of

1

2

3

15

16

17

fL.flSl..! .!..f1.llJl &$0/;0%/4

PERIODS fOR ADCOB51 AND
SHORTER THAN 32 OSC CLOCK
PERIODS fOR ADCOB5B.

iNf~
DO - -

co

....U1

m
U1
co

1.1 POWER FAilURE DETECTION!
INITIALIZATION AFTER POWER-UP
Upon power up, the device is automatically configured in the
watchdog mode. The status of the power flag bit, P, provides power failure indication to the microprocessor. The
timing diagram of Figure 2 shows the sequence of events.

Applications Information

cs

c>-

n
CI

TRI-sTAn;---ti0f~4

P=1

f00000W$~

TLlH/ll021-30

FIGURE 2. Read Power Flag after
Power Up ADC085~! ADC0858

1-21

•

m~~------------------------------------------------~

i

~

"CI
C
CIS

....
an

~cc

2.0 Memo..yAccess Modes

Th~ ADC0851 18 has an internal RAM with sixteen, memory
locations (one location for the upper limit and one for the
lower limit for each of the 8 input channels). Each memory
location is 8 bits wide. An 8-bit limit word representing an
upper or lower limit boundary can either be written to or read
from the RAM. The ADC0851 uses only four memory locations for the four boundary limits corresponding to the two
inputs. The eight channel ADC0858, however, makes use of
all sixteen memory locations.
Each memory location is accessed by a specific address as
shown by Table lI(a) and (b). Note that even addresses correspond to the lower limits while the odd addresses correspond to the upper limits. The ADC0851 and ADC0858 both
use 4 bits (A3, ... AO) to address the RAM, however,
ADC0851 decodes only the two LSBs of the address data
while ignoring the two MSBs.

MEMORY ~DDR£SS (TABLE][A FOR ADC0851.

TABLE liB FOR AOCO'5')
TLlHI11 021-31

TABLE lIa. RAM Address and
limit Data for ADC0851
RAM Address
A3

A2

A1

AO

Corresponding
Channel and Umlt'

X

X

0

0

CHO-Lower Limit

X

X

0

1

CHO-Upper Limit

'X

X

1

0

CH1-Lower Limit

X

X

1

1

CH1-Upper Limit

Limit Data (ADC0851)
LO

L1

L2

I L3 I L4 I L5 I L6 I L7 I

TABLE IIb_ RAM Address and
Limit Data for ADC0858
RAM Address

Corresponding
Channel and Limit

A3

A2

A1

AO

0

0

0

0

CHO-Lower Limit

0

0

0

1

CHO-Upper Limit

0

0

1

0

CH1-Lower Limit

0

0

1

1

CH1-Upper Limit

0

1

0

0

, CH2-Lower Limit

0

1

0

1

CH2-Upper Limit

0

1

1

0

CH3-Lower Limit

0

1

1

1

CH3-Upper Limit

1

0

0

0

CH4-Lower Limit

1

0

0

1

CH4-Upper Limit

1

0

1

0

CH5-Lower Limit

1

0

1

1

CH5-Upper Limit

1

1

0

0

CH6- Lower Limit

1

1

0

1

CH6- Upper Limit

1

1

1

0

CH7 - Lower Limit

1

1

1

1

CH7 - Upper Limit

Umlt Data (ADC0858)
LO

L1

I L2 I L3 I L4 I L5 I L6 I L7 I
1-22

»
c

2.0 Memory Access Modes (Continued)

o

Note that the memory address is clocked in with the MSB
(bit A3) first whereas the limit data is clocked in with the lSB
(bit lO) first.

When writing all limits, memory address is not required. The
limit data is sequentially written into the RAM starting at the
location for CHO-lower Limit and ending at; CH1-Upper
Limit for the AOCOB51 (see Table IIa), CH7-Upper Limit for
AOCOB58 .(see Table lib). Note that lO corresponds to the
lSB of the limit data.
Figure 4 shows the timing diagram. After CS is brought low,
the input word (01) is clocked in starting at the first rising
edge of ClK. The first four bits of 01 configure the device in
the "write all limits" mode. Next, the limit data is serially
clocked in. To complete the operation, CS should be
brought high after the data is loaded.

Figure 3 shows the timing diagram for writing one limit. After
CS is brought low, the input word (01) is clocked in starting
at the first rising edge of ClK. Taking CS high after the MSB
(bit l7) of the limit data is loaded completes the write opera·
tion.

2.2 WRITE ALL LIMITS MODE
This mode is used to update all memory locations in the limit
RAM. An 8·bit limit word is written to each memory location.
Note that there are four limit words for the AOC0851 and
sixteen limit words for the AOC085B. To initiate the opera·
tion of the device in the "write all limits" mode, the mode
address has to be 1 1 0 1 (see Table I). The data format for
the input word is as shown below.

UW :5 (CHI - Ul) - - ADC0851
UItlJT 15 (al7 - UL) - - ADC08SS==-,

·

IN" 0 (CHO·

»
c
oo
C)C)

U1

C)C)

Data Input (DI)-ADC0851 or ADC0858

1~lulululul~I~I~I-i~lulululul~I~I~i
~)-"""B51

I'

U1
.....

t:II
:J
Q.

2.3 READ ONE LIMIT MODE
When the mode address is 1 0 1 1, the device is configured
in the "read one limit" mode. One B·bit limit word can be
read from the RAM memory location pointed to by the limit
address. The data format for the input word is as shown
below.

Data Input (DI) Word-ADC0851 or ADC0858

I. I I 10 1I

~

I. 1 I. I. IAlI .. I"H
0

I

I

!

OR """'58

'-----WEWORY ADDRESS
(TABLE n:A FOR AOCOS51, TABLE][B FOR ADC0858)

MOO£

'----NODE

Tl/H/ll021-32

Tl/H/ll021-33

.~~L

__________________________________________

~~

eLK

DI

~

•

. .1-,0_ _0,--,1 • I

A3

I

I

A2

AI

I

AO

I

LO

I u Iu I

13

I

L4

I

L5

I

L6

I

17

W4
TlIH111021-34

FIGURE 3. Timing Diagram for Write One Limit

a~L

____________________

~

__________________________________

~r--

CLK

.w ·I

LO

I

L1

Iu I" I

L4

I

L5

I

L6

I

17

1... 1 LO I u I u I

13

I

L4

I~ I

L6

I

17

liP),)

LrulT 3 (ADC085f). UWIT 15 (A.DC0858)

Ut.llTO

TlIH111021-35

FIGURE 4. Timing Diagram for Write All Limits

1·23

•

2.0 Memory Access Modes (Continued)
Note that no memory address data is required. The limit
data is sequentially transmitted out starting from the memo·
ry location for CHO-Lower Umit and ending at; CH1-Upper
Umit for the ADC0851 (see Table lI(a», CH7,-Upper Limit
for the ADC0858 (see Table lI(b».
'

The address bits access specific memory locations as per
Table lI(a) and (b) for the ADC0851 and ADC0858 respec·
tively. The address data is clocked in with the MSB (bit A3)
first.
The timing diagram in Figure 5 shows that after es goes
low, the first four bits of the input word configure the device

The timing diagram of Figure 6 shows that the input data is
loaded starting at the first rising edge of CLK after,es goes
low. Third clock rising edge after the last bit of the input data
is loaded, the limit data is serially transmitted out. Four limit
words are transmitted for the ADC0851; sixteen for the
ADC0858. Each limit word is output with the LSB (bit LO)
first. Taking CS high after the MSB of the last limit data is
transmitted completes the operation.

to "read one limit" mode. Next. the address bits select the
desired memory location. Third clock rising edge after the
address data's LSB is loaded, the limit data is output with
the LSB (bit LO) first.
2.4 READ ALL LIMITS MODE
With a mode address of 1 1 1 1, the device is configured in
the "read all limits mode". When in this mode, 8·bit limit
data from each memory location is serially transmitted out.
The data format for the input word is as follows:
Data Input (01) Word-AOC0851 or AOC0858

1,1,1,1, I
I

I

IIOOE
B----,~

J

TUH/ll021-36

______________________________________________________

~r___

~~,w,
00

-------------------~m~------------------[IJ~ill:llL1JI~u~l:u~l~w~IJ~~I:iwJI~~~~
TUH111021-36

FIGURE 5. Timing Diagram for Read One Limit ADC08511 AOC0858

Cs---'~

______________________________________________________________ ____
~

~r---

eLK

DI~'
DO

..

IIJL!:.IIJL['II::I"WI::I[]I ••• '

-------TRl~STATE----------_{IJL!:.IIJLI'IIJL!:2IIJL['

L7

""

LO

I

Ll

I

l2

I

II

Iu I

L5

I

L6

I

L7

r--

LlMIT:5 (ADCOI$I). UMlT 15 (ADCOUI)

TLlH111021-39

FIGURE 6. Timing Diagram for Read All Limits AOC0851/ADC0858

1·24

.--------------------------------------------------------------------.~

c

3.0 Watchdog Mode
COM pin will cause the device to measure the difference
between the input signal and the voltage at the COM pin.
The voltage at the COM pin has no effect on an input channel that is configured as a differential pair. When the channel pairs are configured as differential inputs (i.e., CHOCH1, CH2-CH3, etc.) the differential voltage is compared
with the limits for the lower numbered channel. For example, the differential voltage CHO-CH1 will be compared with
the limits for CHO. Note that the channel pairs are programmed in groups of three bits. The channel address is
input to the AID converter with the MSB (bit C11) first.
The timing diagrams for ADC0851 and ADC0858 watchdog
operation are shown in Figure 1. After a CS low is detected,
the input word (DI) is clocked in starting at the first rising
edge of the serial clock (CLK). Once the least significant bit
of the channel address is loaded, CS should go high. Taking
CS high after the proper input word is loaded initiates the
operation of the device in the watchdog mode. To keep the
device in continuous watchdog mode, CS should remain
high for eight or more OSC clock periods for the ADC0851
and thirty-three or more OSC clock periods for the
ADC0858. If the input signals are within the boundary limits,
the interrupt pin (INn remains at logic "1" and the Data
Ouptut (DO) pin is in TRI-STATE. In addition, in the case of
the ADC0851, the COMPL and COMPH pins remain at logic
"1".

This is the primary real time operating mode. During watchdog operation, the upper and lower limits stored in the RAM
are applied sequentially to the DAC's digital inputs. The
DAC's analog output is applied to the comparator input and
compared against the voltage at the enabled analog input
pin. The data format for the input word is as shown below.
Oata Input (01) Word-AOC0851 or AOC0858

I

C

WODE

I

I

I 1 I 0 I 0 I 0 Ic"lc10 1 c91 CB c71 csl csl c41 c31 c 2 1 c+o I

I

I
IL.-----CHANNEL CONFIGURATION
TLIHll 1021 -37

The last twelve bits of the input word assign the multiplexer
channel configuration.
3.1 SELECTING THE CHANNEL CONFIGURATION
When the device is either in the watchdog or automatic AID
conversion mode, each pair of analog input channels must
be programmed to determine which channel(s) will be active, and whether they will be operating single-ended or differentially. Table III(a) and (b) show the channel addresses
for the ADC0851 and the ADC0858 in various channel configurations. When the channels are configured as singleended inputs, the input voltages are measured with respect
to the voltage at the COM pin. Applying a DC voltage at the

oQ

co
en
.....

I»
::l

a..
~

C

n
Q

co
en
co

TABLE ilia. Multiplexer Channel Configuration (AOC0851)
Cll Cl0 C9

CB

C7

C6

cs

C4

C3

C2

Ix'x'xlx'x'xlx1x1xl
CHANNEL
ADDRESS

Cl

co

J~~1

I

CHANNEL
CONFIGURATION

C2

Cl

CO CHO CH1 COM

0

0

0

1

0

0

0

1

0

+

1

1

0

+

X

X

1

+

•

COMMENTS

- I ~:;:;LE-ENDED
-

+
+

CH1 ONLY

-

-

CHO ONLY
DIFFERENTIAL
CHO-CH1

g~'!a~~ CH1
TLIHll 1021 -40

TABLE IIIb. Multiplexer Channel Configuration (AOC0858)
~1~

I

C9

PAIR 6.7

CB

I

~

~

CB

PAIR 4:5

I

~

~

~

PAIR 2:3

~

co

~

PAIR 0'.1

CHANNEL
ADDRESS

SUBSTITUTE
CHANNELS
6 AND 7 INTO
TABLE

C2
SUBsmUTE
CHANNELS
4 AND 5 INTO
TABLE

x =DON'T CARE

SUBSTITUTE
CHANNELS
2 AND 3 INTO
TABLE

C1

CHANNEL
CONFIGURATION

CO CHO CH1

+

0

0

0

1

0

0

0

1

0

+

1

1

0

+

X

X

1

+
+

-

COMMENTS

OM

-

BOTH
SINGLE-ENDED
CHl ONLY
CHO ONLY
OIFFERENTIAL
CHO-CHl
CHO AND CH1
DISABLED
TLIHll 1021 -41

1-25

ADC0851 and ADC0858
Co)

(:)

=e

a
-,
()

:::r
c.

o

cc

Watchdog Operation ADC0851

1+--

B-,

~!~--iL

__________________________ H
~

s::

o

c.



C

3.0 Watchdog Mode (Continued)

(')

oQC)

TABLE IVb. Channel Tag Address
and Status (ADC0858)

The device will read the new-input word and configure to a
different mode if CS is high for less than eight oscillator
clock periods for the ADC0851 and less than thirty-two oscillator clock periods for the ADC0858.

Tag
#

Once a boundary limit is crossed, INT goes low. Moreover,
for ADC0851, COMPL goes low if a lower limit is crossed,
whereas COM PH goes low if an upper limit is crossed. If the
input signals exceed both the upper and lower boundary
limits then both COMPL and COM PH would go low.
To output data after a limit crossing occurs (i.e., after INT
goes low), C5 should be brought low. Note that INT,
COMPL and COMPH would remain low as long as CS
doesn't go low. After C5 goes low INT, COMPL and
OOMPH go high and one clock cycle later output data is
transmitted starting at the first rising edge of CLK, however,
the data is valid at the falling edge of CLK (Figure 7).
3.2 LIMIT CROSSING DETECTION
When the ADC0851 18 is configured in the watchdog mode,
the device operates as a window comparator. First the lower window limit (stored in the RAM) for CHO is compared
against the input voltage at CHO. If the input voltage is
greater than the lower limit, then no interrupt is generated.
Next the upper window limit for CHO is compared against
CHO input voltage. If the input voltage is less than the upper
window limit then no interrupt is generated for CHO and the
device starts a similar comparison cycle for the next channel (CH1). Note that the lower limit can be greater than the
upper limit; in this case the device will flag the microprocessor if the input signal falls inside a window.
TABLE IVa. Channel Tag Address
and Status (ADC0851)

Tag Address

....

CJ'I

Corresponding Limit
and Channel

:::J

(')

T3

T2

T1

TO

0

0

0

0

0

Lower Limit-CHO

1

0

0

0

1

Upper Limit-CHO

2

0

0

1

0

Lower Limit-CH1

3

0

0

1

1

Upper Limit-CH1

4

0

1

0

0

Lower Limit-CH2
Upper Limit-CH2

5

0

1

0

1

B

0

1

1

0

Lower Limit-CH3

7

0

1

1

1

Upper Limit-CH3

8

1

0

0

0

Lower Limit-CH4

9

1

0

0

1

Upper Limit-CH4

10

1

0

1

0

Lower Limit-CH5

11

1

0

1

1

Upper Limit-CH5

12

1

1

0

0

Lower Limit-CHB

13

1

1

0

1

Upper Limit-CHB

14

1

1

1

0

Lower Limit-CH7

15

1

1

1

1

Upper Limit-CH7

STATUS

-

I

5151514 513151215111510159158 571 561 551 541 531 521 51 150

Tag
#

Tag Address

Corresponding Limit
and Channel

T3

T2

T1

TO

0

0

0

0

0

Lower Limit-CHO

REIIAINING 15 BITS REFLECT
RESULTS OF SUCCEEDING TESTS
' - - - FIRST FAILED LIMIT
(ADDRESS OF LIMIT IN CHANNEL TAG REGISTER)

POWER FAil (p)
P

FAil (1)

0

NO

1

0

0

0

1

Upper Limit-CHO

2

0

0

1

0

Lower Limit-CH1

Tl/H/ll021-44

3

0

0

1

1

Upper Limit-CH1

Each comparison takes 21's; thus a total of 4 I£s is required
per channel.

STATU5
51\ SO \

P

---+'

D

NO

1

YES

\53\52

1 YE5

When in watchdog mode, the device will continuously cycle
through the input channels until an input that has crossed its
preset window limit is detected. When this occurs, a logical
"1" is stored in the M5B (bit 53 for ADC0851 and 515 for
ADC0858) position of the status register. In addition the tag
register is updated with the channel's address (see Tables
IV(a) and (b) for ADC0851 and ADC0858 respectively). Note
that the tag address indicates which channel crossed which
limit. Once the tag register is updated after the first limit is
crossed, the device will once more cycle through the remaining channels and compare the input voltages against

POWER FAil (P)

REMAINING 3 BITS REFlECT
RESULTS OF SUCCEEDING TESTS

FAil (1)

' - - - FIRST FAILED LIMIT
(ADDRESS OF LIMIT IN CHANNEL TAG REGISTER)
TL/H/l1021-43

1-27

D)

a.
l>

C

o

QC)

CJ'I

QC)

co
&I)
co
<:)

o
c
c:r:
'C
C

ca
.,...
&I)

co
<:)

o
c
c:r:

r------------------------------------------------------------------------------------------,
3.0 Watchdog Mode (Continued)
their respective window limits. A logical "1" will be placed in
the appropriate location of the status register for each limit
that is crossed as the device cycles through the remaining
channels. Note that the tag register is updated only once
i.e., when the first limit is exceeded. After the last limit comparison is made subsequent to the first limit crossing, the
device will cease any further limit comparisons and will
cause the interrupt pin to go low. Taking CS low causes the
data in the status and tag registers to be transmitted along
with the programmed channel configuration information. In
addition, an extra bit, P, is inserted between the channel
and status information. This bit is updated to a logic "1" in
case of a power interruption.

ter is only updated once when the first limit crossing is detected thus indicating which channel first exceeded its lower
or upper limit.
CHO-LLD
CHI-LLI
CHO-LLO
COMPARE"",
CHO:-ULO ,CH1:-ULI
CHO,-UlD

VIN

CHO

VIN

CHI

The format for the output data is as shown below.
Data Output (DO) Word-ADC0851

r-------f

I T31 T21
I
TAG

T1

I TO ICI
I

*

CHANNEL

EI
f

--I - - - - - - - UPPER
I

:::t:::,.:.
k
::~I
I

I

LIMIT (Ul1)

LOWER LIMIT (LLI)

I

L

SUBSEQUENT LIMIT CROSSING
DETECTED DURING CYCLE THROUGH

L

Assuming that there is no power interruption and that the
ADC0851 was configured for single ended operation, the
output word for our example would be:

CO~FIGURATION

10 1C91 cal···1 Cl I CO I P 1515 1 ...
POWER INTERRUPT -------.J I
STATUS

LOWER Ut.lIT (LLO)

FIGURE 8. Example of Limit Crossing
Detection (ADC0851)

Data Output (DO) Word-ADC0858

I

UPPER lIMlr (ULO)

(

TlIH/11021-45

TL/H/11021-46

I

,

(

(Example: Lower limit of CH1 is crossed first. During cycle through, upper
limit of CHO is crossed)

f

STATUS

,

(

INT

I T31 T21 Tl I TO IC+l+91 CB 1 .. ·1 01 I co I P 153152151 I so I
I
I
POW'R INTERRUPT -------.J I
I
TAG

,

FIRST lIt.lIT CROSSINGj
DETECTED

CHANNEL CONrlGURATION

~~~I~r-'-~-r~

I

:::::?':
: C::t::
:

(Example. of ADC0851 Data Output. Single ended input.
Lower limit of CH1 fails first. During cycle through, upper
limit-CHOfailure is detected).

I

TL/H/ll021-47

The order in which data is transmitted is as follows
(ADC0851 or ADC0858):
• Tags (4 bits)-MSB (T3) first
• Channel configuration (12 bits)-MSB (C11) first

T3 T2 T1 TO C11 C10 C9 C8 C7
x

~

C1 CO P S3 S2 S1 SO

Don't care, whatever bit was initially programmed (ADC0851 only).

The ADC0858 operates similar to the ADC0851 except that
the ADC0858 has a 16-bit status word for the sixteen limits
and sixteen tag addresses (See Table IV(b)). The output
word transmitted to the microprocessor not only contains
information as to how the channels are configured but also
whigh input crossed which limit. If desired, the microproces.
sor can go through a status bit normalization routine to nor·
malize the status information with the tag number as will be
discussed next.

• Power interrupt (1 bit)
• Status (4 bits for ADC0851, 16 bits for ADC0858)-MSB
(S3/S15) first
It is important to note that any channel that is disabled will
not cause an interrupt. Furthermore, when operated in the
differential mode, the arithmetic difference of the two voltages will be compared with the lower and upper limits for
the lower numbered channel. For example, with CHO and
CH1 operating as a differential input pair; the CHO limits will
apply.

3.3 STATUS BIT NORMALIZATION
Figure 9 shows the procedure for normalizing the status information. Let's consider the example cited earlier for the
ADC0851. In our example, the lower limit of CH1 was
crossed first and during cycle·through, upper limit-CHO
crossing was detected, The serial status data is thus 1 0 0 1
and the tag data 0 0 1 0 corresponds to tag #2 (see Table
IVa). Since the most significant bit (S3) of the status data is
transmitted first, the data stored in the microprocessor's
memory is 1 0 0 1. The microprocessor next computes the
tag number from the tag data and rotates the status bits left
"TAG" places as in Figure 9. For our example, the status
bits are rotated by shifting left 2 places. The status informa·
tion in the microprocessor's memory is now normalized i.e.,
UO corresponds to tag 0, U1 corresponds to tag 1 and so
on. From the example in Figure 9 we can see that the status
register in the microprocessor's memory shows that tag 2
and tag 1 failed. The ADC0858 uses a 16·bit status word
and operates similar to the ADC0851. An example shown in
Figure 9 for the ADC0858 demonstrates how status bit nor·
malization is carried out.

Consider an example where the lower limit of CH1 is
crossed first and while the remaining limits are being
checked, the upper limit of CHO is crossed. Figure 8 illustrates the sequence of events for the ADC0851. During
watchdog operation, CHO's lower limit stored in the RAM is
compared against the input voltage at CHO. Since no limit
crossing is detected, the upper limit is compared against
CHO input voltage. Again no limit crossing is detected and
so CH1 's lower limit is next compared against the CH1 input
voltage. This time a limit crossing is detected and a logic
"1" is now stored in the MSB (S3) position of the status
register (see Table IV(a)). Also the Tag register is updated
with the corresponding address (0 0 1 0) from Table IV(a).
The device now cycles through the remaining channels
once more. Since no limit crossing is detected for the upper
limit of CH1, a logic "0" is stored for S2 of the status register. Similarly a logic "0" is stored for S1 of the status register. Finally to complete the cycle, the last limit (upper limit of
CHO) is checked and a limit crossing is detected. Consequently, a logic "1" is stored for SO. Note that the Tag regis1·28

:J>
C

3.0 Watchdog Mode (Continued)

n
o

53
50
O~l~~~~L 111010 11
2

3

0

1

L - TAG
U3

DATA IN

11 10 1011 1

~~g:~OCES50R

1

0

3

....

U15
UO
11 11 10 11 11 1011 11 11 11 11 11 11 11 1011 1
o 15 14 13 12 11 10 9 8 7

n
o

L - TAG

UO

2

PLACES

TAG--1

11+11

~~~~:~:::H

I

t

U3

UO

t

U15

1011 11 10 1

TAG _

3

2

(EXAIIPLE:TAG 2 AND TAG 1 FAILED)

UO

r+ 15 14 13 12 11 10

9

6

8

5

TAG
TLlH/11021-48

FIGURE 9. Status Bit Normalization

4.0 AID Conversion Modes
The ADC0851/8 can be used in two AID conversion
modes. In "One AID conversion" mode, the device operates as a multiplexed AID converter and a conversion may
be initiated on any channel or channel pair configured in the
differential mode. In the "Automatic AID conversion" mode,
an AID conversion is done on a channel or channel pair and
after the output data is transmitted, conversion begins on
the next subsequent channel or channel pair. This process
will continue. unless the device's mode of operation is
changed.

The 4-bit data following the mode address is the channel
information address. These four bits assign the MUX configuration for the single AID conversion. The channel information addresses and the corresonding MUX configurations
are shown in Table Veal and (b) for ADC0851 and ADC0858
respectively. Note that the ADC0851 only decodes the two
lSBs of the channel information data while ignoring the two
MSBs (13 and 12). When a channel pair is configured in the
differential mode, it is important to note that the arithmetic
difference of the channel voltages should not be negative.
Negative difference voltage would result in all zeroes at the
output.

Note that the AID conversion time is determined by the
OSCillator clock period and has no relation with the digital
clock Signal, ClK. The oscillator clock's frequency is set by
connecting a resistor from the OSC pin (pin 2 for ADC0851
or ADC0858) to Vee and a capacitor from the OSC pin to
ground. The conversion time of the AID converter is eighteen OSC clock periods maximum. Assuming that the oscillation clock frequency is set at 1 MHz (with Rext = 3.16 kG
and Cext = 170 pF) then the conversion time would be
18 ,..S maximum.

TABLE Veal. Channel Information for
One AID Conversion (ADC0851)
Channel Information

Channels Enabled

13

12

11

10

X

X

0

0

CHO

X

X

0

1

CHO-CH1

4.1 ONE AID CONVERSION MODE

X

X

1

0

CH1

This mode is used to initiate one AID conversion on a single
channel or channel pair configured in the differential mode.
The necessary mode address as per Table I is 1 0 1 O. The
format for the input word is as follows:

X

X

1

1

Invalid

Data Input (01) word-ADC0851 or ADC0858.

111011101131121111101
I

I

I
[

LCHANHEL INFORllAnOH
MODE

(Table Veal for

ADC0851, Table V(b) for ADC0858)

TL/H/11021-49

1-29

(II

SIt

:::lI

a.

:J>
C

'TAG--1

ROTATE 5TAlUS LEFT
''TAG''

co

515
50
11 10 11 11 11 11 11 11 11 11 10 11 11 10 11 11 1
7
8
9 10 11 12 13 14 15 0

co
co

(II

co
co
o

U)

o
cc(

4.0 AID Conversion Modes (Continued)
TABLE V(b). Channel Information
for One AID Conversion (ADC0858)

"C
C
C'II

Channel Information

.....

13

12

co
o

0
0

U)

o

cc(

The format for the output word is as shown below.
Data Output (DO)-ADC0851 or ADC0858
CHANNEL INFORMATION

Channels Enabled

11

10

0

0

0

CHO

0

O.

1.

CHO-CH1

0

0

1

0

CH1

0

0

1

1

Invalid

0

1

0

0

CH2

0

1

0

1

CH2,..CH3

0

1

1

0

CH3 '

~

I

0

1

1

1

1

0

0

0

1

0

0

1

CH4-CH5

1

0

1

0

CH5

1

0

1

1

Invalid

1

1

0

0

CH6

1

1

0

1

CH6-CH7

1

1

1

0

CH7

1

1

1

1

Invalid

I

.'

I'

tL- - - - - AID DATA
TLlH/ll021-5D

The first eight bits of the output word represent the digital
equivalent of the input voltage. Bits 13 through 10 provide the
chan'nel configuration information as per Table VIa) and (b)
for ADC0851 and ADC0858 respectively. Note that this information is the same as the channel information in the input word. The order in which the output data is transmitted
is as follows:
.. Data-lSB (DO) first

Invalid
. CH4

• Channel information-MSB (13) first
Note that the output will be TRI-STATE if CS remains low
after 10 is transmitted. Taking CS high after the output data
is transmitted causes the device to initiate the start of the
next AID conversion on the same input while ignoring the
data input word (01). If the duration f~r which CS is high is
less than seventeen OSC clock periods, the 'conversion process will be interrupted and the device will look for the mode
address at the falling edge of CS so as to configure to a new
mode of operation. However, if CS is high for eighteen or
more OSC,clock periods then the conversion operation,will
continue from pOint A on the timing diagram (Figure 10). '
To ensure repetitive AiD conversion on the same input; CS
going low should be synchronized with EOC going high.
Thus after EOC goes high, the conversion is completed and
CS
go low to transmiithe output data. Meanwl')ile, if CS
goes low while EOC is low then the conversion process is
interrupted and the device is readied for a new mode of
operation.

The ti,ming diagram for one AID conver!>ion,is ,shown in Figure 10. After CS goes low, ,the input word (01) is clocked in
starting. at the first rising edge of the digital clock signal,
ClK. The first four bits of the input word configure the device for "one AID conversion'; mode while the following
four bits (channel information address) assign the configur~­
tion of the MUX as, per Table VIa) and (b) for the ADC0851
and the ADC0858 respectively. Any.input data following t~e
channel information addreiSs is ignored until the device's
mode of operation is changed.

can

Taking CS high after the last bit of the channel information
address loads the input word. Had CS be,en kept low longer,
the following bits of 'the input word would have been ignored. The device takes one to.tWo OSC dock periods after
CS goes high to initjate the start of AID conversion. The
EOC output goes 10W,'thus signalling the start of the conver'
·sion process. After a maximum of eighteen OSC clock periods, conversion is completed and EOC output goes high,
thus signalling the, end qf conversion. The output data is
now available and will be transmitted only if CS is brought
low. The output data is transmitted starting at the first rising
edge of ClK after CS goes low.

4.2 AUTO AID CONVERSION MODE
When used in this mode, the ADCOa51 /8 offers added flexibility that many multiplexed AID converters don't. In the
auto AID conversiol"! mode, the ADC0851 /8 scans through
the selected input channels, performing AID conversion on
each channel without the need for reloading a new data
input word each time. From Table I, the mode address for
the "Auto AID Conversion" mode is ,1 1 1 O.
The format for the inpulw6rd is as follows:
Data Input (DI) Word-ADC0851 or ADC0858
c=MDDE

I

I

TLlH/ll021-51

1-30

~

C

4.0 AID Conversion Modes (Continued)

(")

The 12-bit channel address following the mode address assigns the MUX configuration as per Table lII(a) and (b) for
ADCOB51 and ADCOB5B respectively. Note that the
ADCOB51 only decodes the three lSBs (CO, C1 and C2) of
the channel address.
The timing diagram for "Auto AID Conversion" mode is
shown in Figure 11. The input word is loaded starting at the
first rising edge of the ClK after CS goes low. The first four
bits configure the device for the "Auto AID Conversion"
mode while the 12-bit channel address assigns the configuration of each channel pair. If CS remains low after CO is
loaded then any subsequent input data is ignored. Taking
CS high after the input word is loaded initiates the start of
AID conversion. AID conversion starts one to two OSC
clock periods after CS goes high. The EOC output goes low
to signal the start of an AID conversion. The conversion
time may range from 17 ".S to 74 ".S depenCiing on how

the channel pairs are configured. The EOC output goes high
at the end of conversion thus signalling that the result of the
AID conversion can now be retrieved. The output data will
be transmitted only if CS goes low and is transmitted starting at the first rising edge of ClK Signal after CS goes low.
The format for the output word is as follows:
CHANNEL INrORMATlON ~

I

lool~I~I~I~I~I~I~I~I~I"I~1
I

I

f

L -----

A/ D DATA
TL/H/11021-52

1-31

.....

I»
:::J

a..

~

(")

Data Output (DO)-ADC0851 or ADC0858

I

o
co

U'I

o
co
U'I
co

ADC0851 and ADC0858
oIlIo

b

:J>
......
C

oo
::::I

<

osc

CD

Cl.K

cs

I.
o..__,
....---J,I

..-----+--!li~I---.....

!

L..._ _ _ _ _ _ _ _ _ _ _ _ _ _--!

~ ..... TO_-TO.

-~ ~~AI:.:cA/D
NEW MODE" DIS TIE SHOULD

COIMJISIONOlIlI£SAME

Il'UTREPrATS FROM

Cl.K

POIIJ-."

ON 1ME 'I1IIIIG w.GWf F DIS
lIME IS EICHIEDC OR KOllE osc

ClOCKPIJIIODS.

DI~

.

:"""-TCOIlV= 17 to II usc

;.....-......:

~

TRHTAlE

00

I

g
a

BmlNNEICI'CONYERSIDN=-=-t:I
..._ _ ___

'1IO'D1'D1'U'IM'DS'DII'm'I3'I2'.'IOI---TRHTATE--

Ii

I

::J

15

TUH/11021 ~53

FIGURE 10. Timing Diagram for One AID Conversion ADC0851J ADC0858
c'.:>

I\)

~f1.Sl.fl.Il..fL ••• ~.•.

!~---,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-.J~~~~.~TO~TO'
!
L......!:::

cs

~

-~.

IIEWMOO[.1HIS'lllESHOULD
:ac.c~17OSC

ClK~ •••

~~

1

I

a

roc

DO

~o

I ••• [J~[J~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~_J

_
TRHTATE

~

CONYDISION

~TCONV"(SEtTOO)
t---IF;I====-;;EJI)iciOlN~.i;
.....

;;;;-----------""ii....

•

,

tT02OSCCLOClCa'CI.LS~

I

~

I

U

i!!:

oIl.
CD

DfDCOIMRSION

~

1m 2 OSCCLOClCcrrus-lJlo!

::::I

(I)

a.oac tm.ES

It---l-~.~====~~;;~~~--------------------_;~;a~~====~

BEGlNCOHYEIISION+==+f

U1
0'

;;;C"";;;;;;t'DtSION;;;;iii"';;;NOO;ooClWlCiWilllLiiiLi'..
:;;;::-----=+1===+\.___....:.

'UO'DI'D2'm'IWID5'DI'rn'o'a'.'D

lRHTAlE-TUH/11021-54

FIGURE 11. Timing Diagram for Auto AID Conversion ADC0851/ADC0858

s.

cause improper operation. The AID converter's conversion
time is a minimum of seventeen OSC clock periods and a
maximum of eighteen. Figure 12 shows a typical connection
for the ADCOS51 and ADCOS5S.

4.0 AID Conversion Modes (Continued)
The first eight bits of the output word represents the digital
equivalent of the analog input voltage. Status bits 13 through
10 provide the channel configuration information as per Table VIa) and (b) for ADCOS51 and ADCOS5S respectively.

2.0 The Reference

Keeping CS low after 10 is transmitted causes the output to
be TRI-STATE. Once the output data is transmitted, CS may
go high to initiate the start of the next AID conversion. The
subsequent AID conversion starts on the next channel pair
that is configured as per the initially loaded input word (Figure 11). Any data on the data input (DI) line is ignored. Note
that if the duration for which CS is high is less than seventeen OSC clock periods then the conversion process would
be interrupted and the device would look for the mode address at the falling edge of CS so that a new mode of operation can be configured.

The magnitude of the reference voltage (VREF) applied to
the AID converter determines the analog input voltage span
(i.e.,. the difference between VIN(max) and VIN(Min)) over
which the 256 possible output codes apply. The reference
voltage source connected to the VREF pin of ADCOS51 IS
must be capable of driving a minimum load of 4 kO.
The ADCOS51/S can be used in either ratiometric applications or in systems requiring absolute accuracy. In a ratiometric system, the analog input voltage is proportional to
the voltage used for the AID's reference. This voltage is
usually the system power supply, so the VREF pin can be
tied to Vee.
For absolute accuracy, where the analog input varies between very specific voltage limits, the reference pin must be
connected to a voltage source that is stable over time and
temperature. The LM3S5 and LM336 micropower references are good low current devices for use with these AID
converters.
The maximum value of the reference voltage is limited by
the AID converter's power supply voltage, Vee. The minimum value, however, can be as low as 1V while maintaining
a typical Integral Linearity of ± 1 LSB (see Typical Performance .Characteristics curve, "Linearity Error vs Reference
voltage"). This allows direct conversion of transducer outputs that provide less than a 5V output span. Due to the
increased sensitivity of the AID converter at low reference
voltages (e.g., 1 LSB = 3.9 mV for a 1V full scale range),
care must be exercised with regard to noise pickup, circuit
layout, and system error voltage sources.

To ensure proper operation in the "Auto AID Conversion"
mode, CS going low should be synchronized with EOC going high. Thus after EOC goes high, the conversion is completed and CS can go low to transmit the output data. After
the output data is transmitted, CS should go high to initiate
automatic AID conversion on the next channel pair and remain high until the conversion is completed and EOC goes
high. Meanwhile, if CS goes low while EOC is low then the
conversion process is interrupted and the device is readied
for a new mode of operation.

5.0 Test Mode
A mode address of 1 1 0 0 configures the device in the test
mode. This mode is used to test the internal operation of the
device at the factory and is not recommended for normal
use. If the device is accidentally configured in the test mode
then the power supply must be disconnected and reconnected again to reset the device.

6.0 Bidirectional 1/0

3.0 The Analog Inputs

If the microprocessor has bidirectional Input/Output capability then ADCOS51/S's input and output pins can be tied
together and a single wire can be used to serially input data
to or output data from ADCOS51 IS. This capability is made
possible because when the input word is clocked in, the
output pin is in TRI-STATE and when the output word is
clocked out, the data at the input pin is ignored.

3.1 REDUCING COMMON MODE ERROR
Rejection of common mode noise can be achieved by configuring the ADCOS51/S's inputs in the differential mode
since the offending common mode signal is common to
both the selected "+" and "-" inputs. The time interval
between sampling the "+" input and the "-" input is one
oscillator clock period. A change in the common-mode voltage during this short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is:

II. Analog Considerations

1.0 AID Conversion Time

Verror(Max) = VPEAK(2'ITfeM) (1/fose)
where feM is the frequency of the common-mode signal,
VPEAK is the signal's peak voltage and fose is the AID
converter's OSC clock frequency.

The AID conversion time is a function of the OSC clock
frequency. The oscillator frequency is set by connecting an
external resistor, Rext from the ADCOS51/S's OSC pin to
Vee and an external capacitor, Cext from the OSC pin to
ground. With Rext = 3.16 kO and Cext = 170 pF, the OSC
frequency is 1 MHz at Vee = 4.5Vand 1.05 MHz at Vee =
5.5V.
The OSC frequency will vary as the ambient temperature
varies, this is shown by the Typical Performance Characteristics curve, "OSC Frequency vs Temperature". For a specified external resistor, the OSC frequency can be changed
by varying the external capacitor as is shown by the Typical
Performance Characteristics curve, "OSC Frequency vs
Rext and Cext". Note that the OSC pin of the ADCOS51/S
should not be driven by an external clock as this might

For a 60 Hz common-mode signal to generate a % LSB
error (:::: 5 mV for a 5V full scale range) with the converter
running at fose = 250 kHz, its peak voltage would have to
be 3.3V.

3.2 SOURCE RESISTANCE
For a source resistance under 2 kO, the ADCOS51 IS's total
unadjusted error is typically ± 0.2 LSB at VREF = 4.75V and
lose ~ 1 MHz (see Typical Performance Characteristics
curves, "Total Unadjusted Error vs Source Impedance").
One source of error is the multiplexer'S leakage current of
3 p,A which contributes a 3 mV drop across a 1 kO source

1-33

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c

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Q

CD

....
en

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a..

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c

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en
CD

co ,---------------------------------------------------------------------------------,
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input of a differential input pair at this V'N(Min) value. This
co
3.0 The Analog Inputs (Continued)
<:)
Co)

c0(
"C
C
CIS

....

It)

CO

<:)

Co)

c0(

utilizes the differential mode operation of the AID converter.

resistance. Another source of error is the sampling nature of
the AID converter. Short spikes of current enter the" +"
input and exit the" -" input at the rising and falling transition of the OSC clock . These currents decay rapidly and
generally do not cause errors since the internal comparator
is strobed at the end of a clock period. If large source resistances are used however, then the transients caused by the
current spikes may not settle completely before conversion
begins. If a capacitor is used at the input of the AID converter for input filtering then the input signal source resistance
should be kept at 1 kO or'less.

The zero scale error of the AID converter relates to the
location of the first riser of the transfer function and can be
measured by grounding the V'N(-) input and applying a
small magnitude positive voltage to the V'N(+) input. Zero
error is the difference between the actual DC input voltage
(the ideal % LSB value, % LSB = 9.8 mV for VREF = 5.000
VDcl and the applied input voltage that causes an output
digital code transition from 0000 0000 to 0000 0001.
4.2 FULL SCALE ADJUSTMENT
The fUll-scale adjustment can be made by applying an input
voltage that is 1.5 LSB less than the desired analog fUIIscale voltage and then adjusting the magnitude of the VREF
input voltage for a digital output code that just changes from
11111110 to 11111111.

3.3 ANALOG INPUT PROTECTION
Often the analog inputs of AID converters are,driven from
voltage sources that can swing higher than Vee or lower
than GND. Analog inputs often come from op amps which
use ± 15V supplies. While during normal operation the input
voltages stay within the OV-5V AID converter supply voltage range, at power up the input voltage may actually rise
above or fall below the AID converter's supply voltages. If
the input voltage to any AID converter input pin does fall
outside the supply voltage by more than 0.3V (worst case)
and the input draws more than 5 mA then there is a good
possibility that the converter may latch up and provide a low
impedance short between Vee and GND.

4.3 ADJUSTING FOR AN ARBITRARY
ANALOG INPUT VOLTAGE RANGE
Analog input voltages that span from a positive non-zero
minimum value can easily be accommodated by the
ADC0851/8. In this case, the AID converter is used in the
differential mode and a reference voltage equal to V'N(Min)
is applied to the V'N(-) input. Normally zero scale adjustment is not required because the zero scale error is very
small. However, if zero scale adjustment is desired then a
voltage equal to V'N(Min) plus % LSB (where 1 LSB = Input
voltage span/256) should be applied to V'N(+) an!:! the reference voltage at V'N( _) should be adjusted such that the
output code just changes from 0000 0000 to 0000 0001.

Figure 13 shows the overvoltage protection circuit for the
analog input.'lf, for instance, the amplifier's output saturates
to its positive supply rail, then the junction of Rl and R2
would be clamped to Vee plus a diode drop. Resistor Rl
limits the op amp's output current and R2 limits the current
flowing into the input of the AID converter. Likewise, the
junction of Rl and 'R2 would be clamped to a diode drop
below ground if the op amp's output saturates to the negative rail.

Once the proper reference voltage is applied to the V'N(-)
input then full scale adjustment can be made. Full scale
adjustment is made by first applying a voltage to the V'N( +)
input that is 1.5 LSB less than V'N(Max) Le.;
V'N( +) FS ADJ = VMax - 1.5 [(VMax - VMin)/256)
where, VMax = the high end of the analog input voltage
range

4.0 Zero Scale and Full Scale
Adjustment

VMin = the low end of the analog input voltage
range

4.1 ZERO SCALE ERROR

The reference voltage, VREF applied to the reference input
pin of the AID converter is adjusted so that the output code
just changes from 1111 1110 to 1111 1111. This completes
the adjustment procedure.

The zero scale error of the AID converter does not require
adjustment. If the minimum analog input voltage value,
V'N(Min), is not at ground potential then a zero offset can be
done. The converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing the V'N( _)

Typical Applications
.-------------1 VIN

r-=====::::::"""

Jo:oo=:-------4p--....- - - , Vee
+

10k
VREF

ADC0851/18

=====~==~~AGND

Rex\

+5V

-~

3.1Skn
OSC~-----------+---.

r-------~DGND

~~-----------.---t------~
Cex\

I'70 PF
TLlH/11021-55

FIGURE 12. Recommended Connection for ADC0851 and ADC0858

1-34

.--------------------------------------------------------------------,
Typical Applications (Continued)

~

c
oQ

CD

....

en

+5V

III

:::s

Q.
~

01
510

Vee
CHO(+)

C

o

R2

1

(:)

CD

02

en

AOC0851

CD

CH1(-)

TLlHlll021-56

FIGURE 13. Over Voltage Protection of the Analog Inputs
ADC0851
Single Ended

o

Differential

Pseudo-Differential

o

CHO(+)

CHO(+)

CH1(+)

CH1(+)

COM(-)

COM(-)

0.1

{

_

CHO(+/-)
CH1(-/+)

TLIHlll021-59
TL1H111021-57
TLIHlll021-58

FIGURE 14. Analog Input Multiplexer Options for ADC0851
ADC0858
Single Ended

Pseudo-Differential

Differential

CHO(+)
CH1(+)
CH2(+)
CH3{+)
CH4(+)
CH5(+)
CH6{+)
CH7(+)

0
2
3
4

5
6

7
COM(-)

O.I{
2.3{
4.5{
6.7{

CHO(+/-)
CH1(-/+)
CH2(+/-)
CH3(-/+)
CH4(+/-)
CH5(-/+)
CH6(+/-)
CH7(-/+)

Mixed Mode
O.I{
2.3{

CHO(+/-)
CH1(-/+)
CH2(+/-)
CH3(-/+)
+
+
+
+

TLlHlll021-62

COM(-)

TLlHlll021-60
TL1H/11021-61

FIGURE 15. Analog Input Multiplexer Options for ADC0858

1-35

TLIH/ll021-63

•

~r-------------------------------------------------------------~

8

Typical Applications (Continued)

C

c(

t 5V

"0

...ani

I

10k

Vcc

co
Q

g
c(

~

I

CHO{+)
CH1{+)
CH2(+)
CH3(+)
CH4(+)
CH5(+)
CH6(+)
CH7(+)

COM(-)

VREF

ADC0858.

-

.

LM335

COMPH 1--+--.

10k

iNi'

CH1{-)

10k
TA MAX
ADJUST

TLlH/11021-65

GND

FIGURE 17. Remote Temperature Sensor
with Over Range Flag

I

..L
TUH/11021-64

FIGURE 16. Adaptive Instrumentation Control
(Ratlometrlc Operation) with Over Range Flag
5V

Rl

0-2.SV +

20k

5k

ADC0851
ADC0851

GND

GND

TL/H/11021-67

TLlH/11021-66

FIGURE 19. Single Channel Ratlometrlc Operation

FIGURE 18. Absolute Input with 2.5V Input Voltage Span

1·36

t;tINational Semiconductor

LM12434/LM12{L}438 12-Bit + Sign Data Acquisition.
System with Serial I/O and Self-Calibration
General Description

Key Specifications

The LM12434 and LM12{L)438 are highly integrated Data
Acquisition Systems. Operating on 3V to 5V, they combine a
fully-differential self-calibrating (correcting linearity and zero
errors) 13-bit (12-bit + sign) analog-to-digital converter
(ADC) and sample-and-hold (S/H) with extensive analog
and digital functionality. Up to 32 consecutive conversions,
using two's complement format, can be stored in an internal
32-word (16-bit wide) FIFO data buffer. An internal 8-word
instruction RAM can store the conversion sequence for up
to eight acquisitions through the LM12{L)438's eight-input
multiplexer. The LM12434 has a four-channel multiplexer, a
differential multiplexer output, and a differential S/H input.
The LM12434 and LM12{L)438 can also operate with 8-bit
+ sign resolution and in a supervisory "watchdog" mode
that compares an input signal against two programmable
limits.
Acquisition times and conversion rates are programmable
through the use of internal clock-driven timers. The differential reference voltage inputs can be externally driven for absolute or ratiometric operation.
All registers, RAM, and FIFO are directly accessible through
the high speed and flexible serial I/O interface bus. The
serial interface bus is user selectable to interface with the
following protocols with zero glue logic: MICROWIRE/
PLUSTM, Motorola's SPI/QSPI, Hitachi's SCI, 8051 Family's
Serial Port (Mode 0), 12C and the TMS320 Family's Serial
Port.
An evaluation kit for demonstrating the LM12434 and
LM12{L)438 is available.

fClK = 8 MHz (L, fClK = 6 MHz)
• Resolution
12-bit + sign or 8-bit + sign
• 13-bit conversion time
.5.5 p.s (7.3 p.s) (max)
• 9-bit conversion time
2.6 p.s (3.5 p.s) (max)
• 13-bit Through-put rate
140k samples/s (105k sample/s) (min)
• Comparison time ("watchdog" mode)
1.4p.s (1.8p.s) (max)
10 MHz (6 MHz) (max)
• Serial Clock
±1 LSB (max)
• Integral Linearity Error
GND to VA+
• VIN range
45 mW (20 mW) (max)
• Power diSSipation
• Stand-by mode
25 p.W (16.5p.W) (typ)
power dissipation
3.3V ±10%
• Supply voltage LM12L438
5V ±10%
LM12434/8

Features

• Three operating modes: 12-bit + Sign, 8-bit + sign,
and "watchdog" comparison mode
• Single-ended or differential inputs
•. Built-in Sample-and-Hold
• Instruction RAM and event sequencer
• 8-channel (LM12{L)438) or 4-channel (LM12434)
multiplexer
• 32-word conversion FIFO
• Programmable acquisition times and conversion rates
• Self-calibration and diagnostic mode
• Power down output for system power management
• Read while convert capability for maximum through-put
rate

Applications
•
•
•
•
•

Data Logging
Portable Instrumentation
Process Control
Energy Management
Robotics

Connection Diagrams
28-Pln PLCC Package

28-Pin Wide Body SO Package
MODESnl

..
IN3

:5

2

2sl-IIOOESEL2
271-Pl
26i-P2

I

eLK

2

iNf

:5

SYNC

..

VD'

6

OONO

7

LM12{L}438

22

INO

8

(LM12434)*

21

Vo'

1282726

25

5

iiif

IN4(NUXOuH'

6

u

elK

IN~ (MUXOUJ+)'

7

23

NOOESELI

IN6 (S/H 1"-)'

8

22

MOO[SEL2

IN7 (S/H IN+)'

9

LM12{L}438
(LM12434)*

21

PI

VREft

10

20

P2

VIU •

11

19

P3

12131415181718

TL/H/11879-1

25

P3

24

'4

23

V,
P5

INI

9

20

DGHD

IH2

10

19

v,,+

1M3

11

18

IN4(WUXOUT-)'

12

17

VREr -

IN5(NUXOUT+)'

13

16

VREH

AGND

IN6 (S/H IN-J'

14

15

IN7 (S/H IN.)·

TL/H/11879-2

Order Number LM12434CIWM, LM12438CIWM, or
LM12L438CIWM
See NS Package Number M28B

'Pln names In () apply to the LM12434

Order Number LM12434CIV, LM12438CIV, or
LM12L438CIV
see NS Package Number V28A
1-37

Table of Contents
1.0 FUNCTIONAL DIAGRAMS ...•................. 1-39

7.0 DIGITAL INTERFACE ......................... 1-77

2.0 ELECTRICAL SPECIFICATIONS ..•...•.......• 1-41

7.1 Standard Interface Mode ..................... 1·77

2.1 Ratings ...................... : .............. 1·41

7.1.1 Examples of Interfacing to the HPC 46XXX's
MICROWIRE/PLUSTM and 68HC11's SPI •. 1·84

2.1.1 Absolute Maximum Ratings •.•.•...•..... 1-41

7.28051 Interface'Mode ......................... 1·91

2.1.2 Operating Ratings ...................... 1-41

7.2.1 Example of Interfacing to the 8051 ..... ~ .. 1·94

2.2 Performance Characteristics ... , ....•.....•..• 1-41

7.3 TMS320 Interface Mode ...................... 1·98

2.2.1 Converter Static Characteristics .......... 1·41

7.3.1 Example of Interfacing tathe
TMS320C3x .......................... 1·101

2.2.2 Converter Dynamic Characteristics ........ 1·42
2.2.3 DC Characteristics ...................... 1-44

7.4 12C Bus Interface ............. ,.............. 1-106

2.2.4 Digital DC Characteristics ............•... 1-45

7.4.1 Example of Interfacing to an' j2C
,
Controller .... : ....................... 1·108

2.3 Digital Switching Characteristics ...........•... 1-46

2~3.1 Standard Interface Mode ................ 1·46

8.0 ANALOG CONSIDERATIONS ............•... :'1-109

2.3.2,8051 Interface Mode ......... , .......•.. 1·47
2.3.3 TMS320 Interface Mode ................. 1·48

8.1 Reference Voltage .......................... 1·109

2.3.4 12C Bus Interface ... , ................... 1-49

'8.2 Input Range .. " ......................... " .. 1·109

2.4 Notes on Specifications ...................... 1·50

8.3 Input Current. .............................. 1·109

3.0 ELECTRICAL CHARACTERISTICS ............. 1-51

8.4 Input Source Resistance ..•..........•...... 1·109
8.5 Input Bypass Capacitance ............•.... ".• 1~1 09

4.0 TYPICAL PERFORMANCE CHARACTERISTICS . 1-55

8.6 Input Noise .......... ,' .... " ..... ,' .......... ,".1.109

5.0 PIN DESCRIPTIONS ..•................•....... 1-59

8.7 Power Supply Consideration .:: ......... ,.: .• 1·109

6.0 OPERATIONAL INFORMATION •............... 1·61

8.8 PC Board Layout and Grounding Consideration .1·110

6.1 Functional Description ................... ; ... 1·61
6.2lntemal User·Accessible Registers ............. 1·65
6.2.1 Instruction RAM ........................ 1·65
6.2.2 Configuration Register. " •..•.......•.... 1·72
6.2.3 Interrupts .............................. 1·72
6.2.4 Interrupt Enable Register ................ 1·73
6.2.5 Interrupt Status Register ..............•.. 1·73
6.2.6 Limit Status Register .................... 1·74
6.2.7 Timer ................................. 1·74
6.2.8 FIFO .................................. 1·74
6.3 Instruction Sequencer ........................ 1~75

1·38

1.0 Functional Diagrams
LM12434
S/H IN+
S/H INMUXOUT+
MUXOUT-

J

INO --f
INI --f

4

MULTIPLEXER

IN2 --f

S/H

---

-

IN3 --f

f

T

AGND
SYNC

. - - VREFt

FULLY-DIFFERENTIAL, SELF -CALIBRATING,
VARIABLE RESOLUTION 12-BIT + SIGN
ANALOG- TO-DIGITAL CONVERTER,

. - - VREF Vt

T

A

~ ~

SEQUENCER

Vt

L..-

0

~

CLK

r
INTERRUPT
ENABLE
REGISTER

.,.

t

I

r

~

INTERFACE

STANDBY OUT

LIMIT AND
INTERRUPT STATUS
REGISTER

INSTRUCTION RAM
8 X 48

16-BIT
TIMER

FIFO
32 X 16

CONFIGURATION
REGISTER

t

t

t

t

t

t

SERIAL INTERFACE

MODIELI MOJSEL2

OGND

~ ~

INT1 ....
INTERRUPT
CONTROL
LOGIC

AGND

! !!!

I
TUH/11879-3

MODESEL1

MODESEL2

P1

P2

P3

P4

P5

Standard

0

1

RtF

CS

DI

DO

SClK

8051

0

0

1"

l'

CS

RXD

TXD

12C

1

0

SADO

SAD1

SAD2

SDA

SCl

TMS320

1

1

FSR

FSX

DX

DR

SClK

'Internal pull-up

Ordering Information (LM12434)
NSC Package Number

Temperature Range

lM12434CIV

28-Pin PlCC

V28A

-40'Cto +85'C

lM12434CIWM

28-Pin Wide Body SO

M28B

-40'C to + 85'C

Part!llumber

Package Type

1-39

III

1.0 Fun.ctlonal Diagrams (Continued)
LM12(L]438
INa -II
IN1~
IN2~
IN3~

MULTIPLEXER
OUT+

IN4~

IN+

IN5~

S/H

IN6~

OUT-

IN7~

+-- VREF+

FULLY-DIFFERENTIAL, SELF-CALIBRATING,
VARIABLE RESOLUTION 12-BIT + SIGN
ANALOG-TO-DIGITAL CONVERTER

+-- VREF-

IN-

T

A!D
SYNC

V + AGND
A

T

CLK

+-

I

! !

-

,

SEQUENCER

v+
0

! !

r

INT1.
INTERRUPT
CONTROL
LOGIC

INTERRUPT
ENABLE
REGISTER

..

LIMIT AND
INTERRUPT STATUS
REGISTER

l

DGND

INSTRUCTION RAM
8 X 48
"

l

STANDBY OUT

16-BIT
TIMER

FIFO
32 X 16

CONFIGURATION
REGISTER

l

l

l

l

t

I

SERIAL INTERFACE

MOD!ELl MOJSEL2

J,

INTERFACE

!!!!
MODESEL1

TUH/11879-4

MODESEL2

P1

P2

P3

P4

PS

Standard

0

1

R/F

CS

01

00

SCLK

8051

0

0

1·

1·

CS

RXO

TXO

12C

1

0

SAOO

SA01

SA02

SOA

SCL

TMS320

1

1.

FSR

FSX

OX

OR

SCLK

'Inlemal pull-up

. ,

Ordering Information (lM 12 { l J438)
Part Number

Package Type

NSC Package Number

. Temperature Range

LM12438CIV
LM12L438CIV

28-PinPLCC

V28A

-4O*Cto+85·C

LM12438CIWM
LM12L438CIWM

28-Pin Wide Body SO

M28B

-40·Cto +85'C

LM12438 Eval

Evaluation Board and Windows" based software

1-40

.

..

2.0 Electrical Specifications
2.1 RATINGS

2.1.2 Operating Ratings (Notes 1 & 2)

2.1.1 Absolute Maximum Ratings (Notes 1 & 2)

Temperature Range
(Tmin:S: TA:S: Tmax)
LM12434CIVILM12( Ll43BCIV
-40'C:s: TA:S: B5'C
LM12434CIWM, LM12(Ll43BCIWM -40'C:s: TA:S: B5'C
Supply Voltage
3.0Vt05.5V
VA+,VO+
:S:100 mV
IVA+ - vo+1

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VA + and Vo+)
6.0V
Voltage at Input and Output Pins
except INO-IN3 (LM12434)
-0.3V to V+ + 0.3V
and INO-IN7 (LM12(Ll43B)
Voltage at Analog Inputs INO-IN3 (LM12434)
and INO-IN7 (LM12(Ll43B)
GND - 5VtoV+ + 5V
IVA+ -vo+1
IAGND - DGNDI
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (TA
V Package
WM Package
Storage Temperature

=

:S:100 mV

IAGDND - DGNDI
Analog Inputs Range

GND:S:VIN+ :S:VA+

VREF+ Input Voltage
VREF- Input Voltage

300mV

1V:S: VREF+ :S: VA+
OV:s: VREF- :S: VREF+ - 1V
1V:S: VREF:S: VA+

VREF+ - VREFVREF Common Mode
Range (Note 16)

300mV
±5mA
±20mA

0.1 VA + :S: VREFCM :S: 0.6 VA +

25'C) (Note 4)

- 65'C to + 150'C
Soldering Information, Lead Temperature (Note 19)
V Package, Vapor Phase (60 seconds)
Infrared (15 seconds)
WM Package, Vapor Phase (60 seconds)
Infrared (15 seconds)
ESD Susceptibility (Note 5)

1.5 kV

2.2 PERFORMANCE CHARACTERISTICS All specifications apply to the LM12434, LM1243B, and LM12L43B unless otherwise
noted. SpeCifications in braces ( l apply only to the LM12L43B.
2.2.1 Converter Static Characteristics The following specifications apply to the LM12434 and LM12(Ll43B for VA+ =
VO+ = 5V (3.3Vl, AGND = DGND = OV, VREF+ = 4.096V (2.5Vl, VREF- = OV, 12-bit + sign conversion mode, fClK =
B.O MHz (6 MHzl, Rs = 250, source impedance for VREF+ and VREF- :S: 250, fully-differential input with fixed 2.04BV
(1.25Vl common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for TA =
T" = TMIN to TMAX; all other limits TA = TJ = 25'C. (Notes 6,7, Band 9)
Symbol

Parameter

Conditions

ILE

Positive and Negative Integral
Linearity Error

After Auto-Cal (Notes 12, 17)

TUE

Total Unadjusted Error

After Auto-Cal (Note 12)

Resolution with No Missing Codes

After Auto-Cal (Note 12)

DNL

ILE

TUE

Typical
(Note 10)

Limits
(Note 11)

±0.35

±1

±1

Units
(Limit)
. LSB(max)
LSB

13

Bits

±1

LSB(max)

Differential Non-Linearity

After Auto-Cal

±0.2

Zero Error

After Auto-Cal (Notes 13, 17)

±0.2

±1

LSB(max)

Positive Full-Scale Error

After Auto-Cal (Notes 12, 17)

±0.2

±2

LSB(max)

Negative Full-Scale Error

After Auto-Cal (Notes 12, 17)

±0.2

±2

LSB (max)

DC Common Mode Error

(Note 14)

±2

±3.5
(±4.0l

LSB(max)

B-Bit + Sign and "Watchdog"
Mode Positive and Negative
Integral Linearity Error

(Note 12)
±0.15

±1/2

LSB (max)

B-Bit + Sign and "Watchdog" Mode
Total Unadjusted Error

After Auto-Zero

±1/2

±1/2

LSB(max)

9

Bits (max)

B-Bit + Sign and "Watchdog" Mode
Resolution with No Missing Codes

1-41

2.0 Electrical Specifications (Continued)
2.2.1 Converter Static' Characteristics The following specifications apply to the LM12434 and LM12(L]438 for VA+ =
Vo+ = 5V (3.3V}, AGND = DGND = OV, VREF+ = 4.096V (2.5V], VREF- = OV, 12-bit + sign conversion mode, fClK =
8.0.MHz (6 MHz}' Rs = 250., source impedance for VREF+ and VREF- ::;;: 250., fully-differential input with fixed 2.048V
( 1.25V I common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for TA =
T" = TMIN to TMAX; all other limits TA = TJ = 25°C. (Notes 6, 7, 8 and 9) (Continued)
Symbol

Parameter

Typical
Limits
(Note 10) (Note 11)

Conditions

8-Bit + Sign and "Watchdog" Mode
Differential Non-Linearity

DNL'

±0.15

±1/2

LSB(max)

±0.05

±1/2

LSB(max)

8-Bit + Sign and "Watchdog" Positive
and Negative Full-Scale Error

±0.1

±1/2

LSB(max)

8-Bit + Sign and "Watchdog" Mode
DC Common Mode Error

±1/8

LSB

Multiplexer Channel-to-Channel
Matching

±0.05

LSB

8-Bit + Sign and "Watchdog" Mode
Zero Error

VIN+
VIN-

Units
(Limit)

After Auto-Zero

Non-Inverting
Input Range

aND

Inverting
Input Range

aND

V (min)
V (max)

VA+
VA+

V (min)
V (max)

-VA+
VA+

V (min)
V (max)

aND

V(min)
V (max)

VIN+ - VIN-

Differential Input Voltage Range

VIN+ - VIN2

Common Mode Input Voltage Range

PSS

Power Supply
Sensitivity
(Note 15)

CREF

VREF+IVREF- Input Capacitance

85

pF

CIN

Selected Multiplexer Channel Input
CapaCitance

75

pF

VA+
Zero Error VA+ = Vo+ = 5V ±10%,
. Full-Scale Error VREF+ = 4.096V, VREF- = GND
Linearity Error

±0.05
±0.25
±0.2

±1.0
±1.5

LSB(max)
LSB(max)
LSB

2.2.2 Converter Dynamic Characteristics The following specifications apply only to the LM12434 and LM12438 for VA + =
Vo+ = 5V, AGND = DGND = OV, VREF+ =4.096V, VREF- = OV, 12-bit + sign conversion mode, fClK = 8.0 MHz,
throughput rate = 133.3 kHz, Rs = 250., source impedance for VREF+ and VREF- ::;;: 250., fully-differential input with fixed
2.048V (1.25V} common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply
for TA = T" = TMIN to TMAX; all other limits TA = TJ = 25~C. (Notes 6,7,8 and 9)
Symbol

Parameter

Typical
(Note 10)

Conditions

tA

Conversion Time

Acquisition Time
(Programmable)

Units
(Limit)

40
60

%
% (min)
% (max)

50

CLK Duty Cycle

te

Limits
(Note 11)

13-Bit Resolution,
Sequencer State S5 (Figure 10)

44 (tclKl

44 (tcLK>

+ 50 ns

(max)

9-Bit Resolution,
Sequencer State 85 (Figure 10)

21 (tClK)

21 (teLK>

+ 50 ns

(max)

Sequencer State 87 (Figure 10)
Minimum for 13-Bits
Maximum for 13-Bits (D = 15)

9 (tClK)
39 (tClK)

9 (teLK> + 50 ns
39 (tcLK> + 50 ns

(max)
(max)

Minimum for 9-Bits (Figure 10)
Maximum for 9-Bits (D = 15)

2 (tclKl
2 (tclKl

2 (teLK> + 50 ns
32 (teLK) + 50 ns

(max)
(max)

1-42

!elK

= CLK Period

2.0 Electrical Specifications (Continued)
2.2.2 Converter Dynamic Characteristics The following specifications apply only to the LM 12434 and LM 12438 for VA + =
Vo+ = 5V, AGND = DGND = OV, VREF+ = 4.096V, VREF- = 'OV, 12-bit + sign conversion mode, fClK = 8.0 MHz,
throughput rate = 133.3 kHz, Rs = 250, source impedance for VREF+ and VREF- 5: 250, fully-differential input with fixed
2.048V common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for T A =
TJ = TMIN to TMAX; all other limits TA = TJ = 25'C. (Notes 6,7,8 and 9) (Continued)
Symbol
tz

Conditions

TY;:lical
(Note 10)

Limits
(Note 11)

Units
(Limit)

Auto-Zero Time

Sequencer State S2 (Figure 10)

76 (tClK)

(max)

4944 (tClK)

+ 50 ns
4944 (tCLK> + 50 ns

142

140

Parameter

76 (tCLK>

(max)

Full Calibration Time

Sequencer State S2 (Figure 10)

Throughput Rate

(Note 18)

two

"Watchdog" Mode Comparison Time

Sequencer States S6, S4,
and S5 (Figure 10)

SNR

Signal-to-Noise Ratio,
Differential Input

VIN = ± 4.096V (Note 20)
fiN = 1 kHz
fiN = 10 kHz
fiN = 62 kHz

79
79
70

dB
dB
dB

Signal-to-Noise Ratio,
Single-Ended Input

VIN =
fiN =
fiN =
fiN =

71
71
67

dB
dB
dB

Signal-to-Noise + Distortion Ratio,
Differential Input

VIN = ± 4.096V (Note 20)
fiN = 1 kHz
fiN = 10 kHz
fiN = 62 kHz

79
78
67

dB
dB
dB

Signal-to-Noise + Distortion Ratio,
Single-Ended Input

VIN = 4.096 Vp. p
fiN = 1 kHz
fiN = 10 kHz
fiN = 62 kHz

71
70
64

dB
dB
dB

Total Harmonic Distortion,
Differential Input

VIN = ±4.096V (Note 20)
fiN = 1 kHz
fiN = 10 kHz
fiN = 62 kHz

-90
-85
-71

dBc
dBc
dBc

Total Harmonic Distortion,
Distortion, Single-Ended Input

VIN = 4.096 Vp. p
fiN = 1 kHz
fiN = 10 kHz
fiN = 62kHz

-88
-82
-67

dBc
dBc
dBc

Effective Number of Bits,
Differential Input

VIN = ±4.096V (Note 20)
fiN = 1 kHz
fiN = 10 kHz
fiN = 62 kHz

12.6
12.2
12.1

Bits
Bits
Bits

Effective Number of Bits,
Single-Ended Input

VIN = 4.096 Vp_p
fiN = 1 kHz
fiN = 10 kHz
fiN = 62 kHz

11.3
11.2
10.8

Bits
Bits
Bits

Spurious Free Dynamic Range,
Differential Input

VIN = ±4.096V (Note 20)
fiN = 1 kHz
fiN = 10 kHz
fiN = 62 kHz

90
86
76

dBc
dBc
dBc

Spurious Free Dynamic Range,
Single-Ended Input

VIN = 4.096V Vp•p
fiN = 1 kHz
fiN = 10 kHz
fiN = 62 kHz

90
85
72

dBc
dBc
dBc

tCAl

SNR

SINAD

SINAD

THD

THD

ENOB

ENOB

SFDR

SFDR

4.096 Vp.p
1 kHz
10 kHz
62 kHz

1-43

11 (tClK)

11 (tCLK>

+ 50 ns

kHz
(min)
(max)

2.0 Electrical Specifications (Continued)
2.2.2 Converter Dynamic Characteristics The following specifications apply only to the LM12434 and LM1243B for VA + =
Vo+ = 5V, AGND = DGND = OV, VREF+ = 4.096V, VREF- = OV, 12-bit + sign conversion mode, fClK = B.O MHz,
throughput rate = 133.3 kHz, Rs = 250, source impedance for VREF+ and VREF- ~ 250, fully-differential input with fixed
2.04BV common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for T A =
T" = TMIN to TMAX; all other limits TA = TJ = 25°C. (Notes 6,7, Band 9) (Continued)
Conditions

Typical
(Note 10)

Two Tone Intermodulation Distortion
Differential Input

VIN = ± 4.096V (Note 20)
f1 = 19.190 kHz
f2 = 19.4B2 kHz

-B2

dBc

TwoTone Intermodulation Distortion
Single Ended Input

VIN = 4.096 Vpp
f1 = 19.190 kHz
f2 = 19.4B2 kHz

-BO

dBc

Multiplexer Channel-to-Channel Crosstalk

VIN = 4.096 Vpp
'IN = 5kHz
'CROSSTALK = 40 kHz
.LM12434 MUXOUT Only
and LM1243B MUX
plus Converter (Note 21)

-90

dBc

Symbol
IMD

IMD

Parameter

tpu

Power-Up Time

twu

Wake-Up Time

(Note 22)

Limits
(Note 11)

Units
(Limit)

10

ms

2

ms

2.2.3 DC Characteristics The following specifications apply to the LM12434 and LM12{L}43B for VA + = Vo+ = 5V {3.3V],
AGND = DGND = OV, VREF+ = 4.096V {2.5Vl. VREF- = OV, fClK = B.O MHz {6 MHz}and minimum acquisition time unless
otherwise specified. Boldface limits apply for TA = T" = TMIN to TMAX; all other limits TA = TJ = 25°C. (Notes 6,7
and 8)
Symbol
10+

Parameter

Conditions
fClK = B MHz (6 MHzl
fSClK = Stopped
fSClK = 10 MHz {B MHz}

Vo + Supply Current

IA+

VA + Supply Current

1ST

Stand-By Supply Current (10 +

fClK

+ IA +)

Multiplexer ON-Channel Leakage Current

Multiplexer OFF-Channel Leakage Current

=

B MHz {6 MHz}

Typical
(Note 10)

Limits
(Note 11)

Units
(Limit)

2.0 {1.4}
4.0 {2.0}

5.0 {2.5}

mA(max)
mA(max)

2.B (2.2)

4.0 {3.5}

mA(max)

Stand-By Mode Selected
fSClK = Stopped
fClK = Stopped
fClK = B MHz {6 MHz}

5{5}
120 {50}

. /LA (max)
/LA (max)

fSClK = 10 MHz {B MHz}
fClK = Stopped
fClK = B MHz {6 MHz}

1.4 {O.B}
1.4 {O.B}

mA(max)
mA(max)

VA+ = 5.5V
ON-Channel = 5.5V
OFF-Channel = OV
ON-Channel = OV
OFF-Channel = 5.5V

0.1

VA+ = 5.5V {3.3V}
ON-Channel = 5.5V {3.3V}
OFF-Channel = OV
ON-Channel = OV
OFF-Channel = 5.5V {3.3V}

0.1

1-44

1.0 (3.0)

/LA (max)

1.0 {3.0}

/LA (max)

1.0 (3.0)

/LA (max)

1.0 {3.0}

/LA (max)

2.0 Electrical Specifications (Continued)
2.2.3 DC Characteristics The following specifications apply to the LM12434 and LM12(L)43B for VA + = Vo+ = SV (3.3V],
AGND = DGND = OV, VREF+ = 4.096V (2.SV), VREF- = OV, feLK = B.O MHz (6 MHz) and minimum acquisition time unless
otherwise specified. Boldface limits appl, for T A = T .. = TlitN to TMAX; all other limits TA = TJ = 2S'C. (Notes 6, 7
and B) (Continued)
Symbol
RON

Typical
(Note 10)

Limits
(Note 11)

Units
(Limit)

LM12434
VIN = SV
VIN = 2.SV
VIN = OV

6S0
700
630

1000
1000
1000

O(max)
O(max)
O(max)

LM12434
VIN = SV
VIN = 2.SV
VIN = OV

±1.0%
±1.0%
±1.0%

±3.0%
±3.0%
±3.0%

(max)
(max)
(max)

Parameter
Multiplexer ON-Resistance

Multiplexer Channel-to-Channel
RON ,matching

Conditions

2.2.4 Digital DC Characteristics The following specifications apply to the LM12434 and LM12(L)43B for VA + = Vo+ = SV
(3.3V), AGND = DGND = OV, unless otherwise specified. Boldface limits appl, for TA = T .. = TMIN to TIIAX; all other
limits TA = TJ = 2S"C. (Notes 6,7 and B)
Symbol

Parameter

VIN(l)

Logical "1" Input Voltage

VIN(ot

Logical "0" Input Voltage

IIN(l)

Logical "1" Input Current

IIN(O)

Logical "0" Input Current

CIN

All Digital Inputs

VOUT(l)

Logical "1" Output Voltage

VOUT(O)

Logical "0" Output Voltage

lOUT

TRI-STATE@ Output Leakage Current

Conditions

= Vo+ = S.SV (3.6V)
= Vo+ = 4.SV (3.0V)
VIN = sv (3.3V)
VIN = OV

Typical
(Note 10)

Limits
(Note 11)

Units
(Limit)

VA +

2.0

V (min)

VA+

0.8

V (max)

O.OOS

1.0

,.,.A(max)

-O.OOS,

-1.0

,.,.A(max)

6

= Vo+ = 4.SV (3.0V)
= - 360 ,.,.A
= -10,.,.A
VA+ = Vo+ = 4.SV (3.0V)
lOUT = 1.6mA
VOUT = OV
VOUT = SV (3.3V)
VA+
lOUT
lOUT

1-45

-O.OS
O.OS

pF
2.4
4.25 (2.9)

V (min)
V (min)

0.4

V (max)

-3.0
3.0

,.,.A (max)
,.,.A(max)

•

2.0 Electrical Specifications (Continued)
2.3 DIGITAL SWITCHING CHARACTERISTICS The following· specifications apply to the LM12434 and LM12 (L}438 for VA +
= Vo+ = 5V (3.3V), AGND = DGND = OV; CL (load capacitance)-on output lines = 80 pF unless otherwise specified.
Boldtace limits apply for TA =TJ = TMIN to TMAXo all other limits for TA "" TJ = 25°C. (Notes 6,7, and 9)
2.3.1 Standard Mode Interface (MICROWIRE/PLUSTM, SCI and SPI/QSPI)
Symbol
(See Figure Below)

Parameter

Conditions

tl

SCLK (Serial Clock) Period

t2

CS Set·Up Time to First
Clock Transition

ta

01 Valid Set·Up Time to Data
Capture Transition of SCLK

I.t

01 Valid Hold Time to Data
Capture Transition of SCLK

ts

DO Hold Time from Data Shift
Transition of SCLK·

Is

CS Hold Time from Last SCLK
Transition in a Read or Write Cycle
(Excluding Burst Read Cycle)

t7

CS Inactive to CS Active Again

Is

SCLK Idle Time between the
End of the Command Byte
Transfer and the Start of the
Data Transfer in Read Cycles

Typical
(Note 10)

Limits
(Note 11)

Units
(Limit)

100 (125)

ns(min)

25 (30)

ns(min)

0

ns(min)

40

ns(min)

70 (120)

ns(max)

25

ns(min)

3

CLKCycle
(min)"

3

GLKCycle
(min)·

'elK is the main clock input to the device, pin number 24 in PlCC package or pin number 2 in SO package.

Cst

-t2 .. 1..

SCLK

-

......

'f.X:IX. ,- _JOv .AM

-

DO

t::f ;

t3 _

1-

01

I~

~

\41+-

I

- '1=-\5

1-46

pxxxxxx

:=x
TL/H/11879-18

2.0 Electrical Specifications (Continued)
2.3 DIGITAL SWITCHING CHARACTERISTICS The following specifications apply to the LM12434 and LM12(L)438 for VA +
= Vo+ = 5V (3.3V), AGND = DGND =OV, CL (load capacitance) on output lines = 80 pF unless otherwise specified.
Boldface'limits apply forTA = TJ = TMIN to,TMAX. all other limits forTA = TJ = 25'C. (NotesS, 7, and 9) (Continued)
2.3.28051 Interface Mode
Symbol
(See Figure Below)

Parameter

Typical
(Note 10)

Conditions

t9

TXD (Serial Clock Period)

tl0

CS Set-Up Time to First
Clock Transition

tll

Data in Valid Set-Up Time to
TXD Clock High

t12

Data in Valid Hold Time
from TXD Clock High

t13

Data Out Hold Time
from TXD Clock High

t14

CS Hold Time from Last TXD
High in a Read or Write Cycle
(Excluding Burst Read Cycle)

t15

CS Inactive to CS Active Again

t16

SCLK Idle Time between the
End of the Command Byte
Transfer and the Start of the
Data Transfer in Read Cycles

Limits
(Note 11)

Units
(Limit)

125(250)

ns(min)

25(40)

ns(min)

40

ns(min)

40(90)

ns(min)

70 (120)

ns(max)

25 (50)

ns(min)

3

CLKCycle
(min)·

3

CLKCycle
(min)·

'CLK is the main clock input to the device. pin number 24 in PLCC package or pin number 2 in SO package.

Cs
\9

C o t10 ."

TXD

,I
\

',I

I~

j"

•

I,

XXXXXXXX'- -~:nxxxxxx
--X~1

RXD
Dcta in

"

\12

RXD
Data out

--

1=\13

:=x

TL/H/11879-21

1-47

2.0 Electrical Specifications (Continued)
2.3 DIGITAL SWITCHING CHARACTERISTICS The following specifications apply to the LM12434 and LM12 [L)438 for VA +
= Vo+ = 5V [3.3V). AGNO == OGNO= OV. CL (load capacitance) on output lines = 80 pF unless otherwise specified.
Boldface limits apply for TA = T .. = TMIN to TMAX. all other IimitsforTA = TJ = 25°C. (Notes 6. 7. and 9) (Continued)
2.3.3 TMS320 Interface Mode
Symbol
(See Figure Below)

Parameter

Conditions

Typical
(Note 10)

Limits
(Note 11)

Units
(Limit)

t22

SCLK (Serial Clock) Period

125 [187)

ns(min)

t23

FSX Set-Up Time to SCLK High

30 (50)

ns(min)

t24

FSX Hold Time from SCLK High

10

ns(min)

t25

Data in (OX) Set-Up
Time to SCLK Low

0

ns(min)

t26

Data in OX Hold Time from
SCLKLow

30 (120)

ns(min)

t27

FSR High from SCLK High

80 [100)

ns(max)

t28

FSR Low from SCLK Low

120

ns(max)

t29

SCLK High to Data
Out (DR) Change

90

ns(max)

,-

,-

. _ 122 _

SCLK

....J

I

rsx

OX

-

F

1 _
23

124

\
125 -

I-

XOOOC :XXXXXX:,_ DOC KXX

-

127

rSR - - - '

1--

126 _

128

\

~

-

I

DR
129 -

'~
TL/H/I1879-23

,

1-48

2.0 Electrical Specifications (Continued)
2.3 DIGITAL SWITCHING CHARACTERISTICS The following specifications apply to the LM12434 and LM12(L)438 for VA +

= VD+ = 5V (3.3V), AGND = DGND = OV, CL (load capacitance) on output lines = 80 pF unless otherwise specified.
Boldface limits apply for TA = T J = TMIN to TMAX. all other limits for TA = TJ = 25'C. (Notes 6,7, and 9) (Continued)
2.3.4 12C Bus Interface
The switching characteristics of the LM12434/8 for 12C bus interface fully meets or exceeds the published specifications of the
12C bus. The following parameters given here are the timing relationships between SCL and SDA signals related to the
LM1243418. They are not the 12C bus specifications.
Symbol
(See Figure Below)

Parameter

Conditions

t17

SCL (Clock) Period

t18

Data in Set·Up Time to SCL High

t19

Typical
(Note 10)

Limits
(Note 11)

Units
(Limit)

2500 (10000)

ns(min)

30

ns(min)

Data Out Stable after SCL Low

900 (1400)

ns(max)

t20

SDA Low Set·Up Time to SCL
Low (Start Condition)

40

ns(min)

t21

SDA High Hold Time after SCL
High (Stop Condition)

40

ns(min)

SCL

-

SDA

~

-

~7

tl

Data in

SDA
Data out

~I~F;'

_t20

-

_t18

_ ....'1

I

\
t1 9 -

·1=1
TLlH/11879-22

1·49

2.0 Electrical Specifications (Contjnued)
2.4 NOTES ON SPECIFICATIONS
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the ~evice may occur. Operating Ratings indicate conditions for which the device Is
functional, but do not guarantee specific performance limHs. For guaranteed specifications and test condHions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device Is not operated under the listed test
conditions.
Note 2: All ,voltages arB measured with respect to GND, unless otherwise specified. GND specifies either AGND and/or DGND and V + specifies either VA + andl

.

~~.

.

Note 3: When the input voHage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > (VA + or Vo +)), the current at that pin should be limited to
SmA. The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current of SmA, to simultaneously exceed the power
supply voltages.
•.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), @JA (package
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TAl/
@JAorthe number given in the Absolute Maximum Ratings, whichever Is lower. For this device, TJmax = .IS0·C, and the typical thermal resistance (@JAl of the V
package, when board mounted, is 7rJ'C/W and In the WM package, when board mounted, is 6rJ'C/W.
Note 5: Human body model, 100 pF discharged through a I.S kO resistor.
Note 6: Two on·chip diodes ara tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to SV above VA + or SV below
GND will not damage the part. However, errors in the AlP conversion can occur if these diodes are forward biased by more than 100 mV. As an example, if VA + is
4.S Voc, the full·scale input voltage must be <:4.6 Voc to ensure accurate conversions.

VA+

r---- -----r

I

~ +

1--+1.Jt/'.'iY--...........

-..4~

TO INTERNAL
CIRCUITRY'

...

L _______ _

GND

TUH/11879-S

Note 7: VA + and Vo+ must be connected together to the same power supply voltage and bypassed with seperate capacitors at each V+ pin to assure
conversion/comparison accuracy. Refer to Section 8.0 for a detailed discussion on giouncling the DAS.
Note 8: Accuracy Is guaranteed when operating the LMI2434/LMI2ILI438 at fClK

= 8 MHz 16 MHz).

Note 9: With the test condition for VREF (VREF+ - VREF-) given as +4.096V, the 12·bH LSB is I mV and the 8-bitl"Watchdog" LSB is 19 mV.
Note 10: Typicals are at TA

= 25"C and represent most likely parametric norm.

Note 11: Limns are guaranteed to National's AOQL (Average Output Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed In LSBs, from the straight line that passes through positive fullscale and zero. For negative integral linearity error the straight line passes through negative full-scale and zero. (See Figures 5b and 5c).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions
between -I to 0 and 0 to + 1 (see Figur9 6).
Note 14: The DC common-mode error is measured with both the Inverted and non-inverted inputs shorted together and driven from OV to 5V 13.3V}. The
measured value is referred to the resulting output value when the inputs are driven with a 2.SV 11.6SVI signal.
Note 15: Power Supply Sensitivity is measured after Auto-Zero and/or Auto-Calibration cycle has been completed wHh VA + and Vo + at the specified extremes.
Note 16: VREFCM (Reference Voltage Common Mode Range) is defined as (VREF+ + VREF-)/2. See FigUres 3 and 4.
Note 17: The device self-calibration technique ensures linearity and offset errors as specified, but noise Inherent In the self-calibratlon process will result In a
repeatability uncertainty of ± 0.1 0 LSB.
Note 18: The Throughput Rate is for a single instruction repeated continuously while reading data during conversions wHh a serial clock frequency ISClK = 10 MHz
18 MHz I. Sequencer states 0 (1 clock CYcle), I (I clock CYcle), 7 (9 clock cycles) and S (44 clock cycles) are used (see Figure 10) for a total of S6 clock cycles per
conversion. The Throughput Rate is fClK (MHz)IN, where N is the number of clock cycles/conversion.
Note 19: See AN-4S0 "Surtace Mounting Methods and their Effect on Product Reliability" for other methods of soldering surface mount devices.
Note 20: Each input referenced to the other input sees a ±4.096V (8.192 Vp-pl sine wave. However the voltage at each input stays within the supply rails. This is
done by applying two sine waves with 180' phese shift and 4.096 Vp-p (between GND and VA+) to the inputs.
Note 21: Multiplexer channel-to-channel crosstalk Is measured by placing a sinewsve with a frequency of fiN = 5 kHz on one channel and another sinewave wHh a
frequency of fCROSSTALK = 40 kHz on the remaining channels. 8192 conversions are performed on the channel with the 5 kHz Signal. A special response is
generated by doing a FFT on these samples. The crosstalk is then calculated by subtracting the amplitude of the frequency component at 40 kHz from the

amplHude of the fundamental frequency at S kHz.
Note 22: Interrupt 7 is set to return an out-of-standby flag 10 ms (typ) after the device is requested to come out of standby mode. However, characterization has
shown the devices will perform to their rated specHicalions in 2 ms.

1-50

3.0 Electrical Characteristics

,,

,,

,

,

,
,,

,
,,

,,

,

,,

,
,,

,
,,

,

. .te,'
,,~~,
,

,,

,
,,

,,

,

,
,,

,

,

,
,,

,,

,

,
,,

,,

"',
,
,,

,,

,

,
,,

,,

,
,,

,

,

,,

,
,,

,
,,

,,

,,

,
,,

,
,,

,,

VREr

,

,
,,

= VREf"+ - VREr-

VIN = VIN + - VIN _
GND S VIN + S VA+
GND S VIN _ S VA+

,,

,'\rotC

,,
,,

,
,,

,,

"'A~t:::>

,

,,

V1N + (V)

TL/H/11879-6

FIGURE 1. Output Digital Code vs the Operating Input Voltage Range (General Case)

,,
,,

,
,,

,

,,

,
,,

,,

,

,
,,

,
,,

,,

,

,

""

VREF + - VREF - = 4.096V
VIN = VIN + - VIN_
GND S VIN + S VAGND S VIN _ S VA'

"

,,

,,

,
,,

,,

,
,,

,,

,

V1N + (V)

FIGURE 2. Outpul Dlgllal Code vs the Operating Input Voltage Range for VREF = 4.096V

1-51

II

TLlH/11879-7

..
....

co
,---------------------------------------------------------------------------------,
C')

...I

3.0 Electrical Characteristics (Continued)

N
,..

V·
A

:i
...I

.....
C')

N
,..

:::i
...I

~

.!.

0.6

vt - O.SV

W

-;!-

0.2

vA"

TUH/11879-8

FIGURE 3. VREF Operating Range (General Case)

VREF = VREF+ - VREFA+ = SV

v

EI
IL

W

-;!-

4

VREF+(V)
TLlH/11879-9

FIGURE 4. VREF Operating Range lor VA + = 5V

1-52

,-----------------------------------------------------------------------------,
3.0 Electrical Characteristics (Continued)

~

a:::
....

t;

O,IIII,IIII,IIII(U095)
0,1111,1111,1110(+4094)
,,"

~E

"""

FULL -SCALE
TRANSITION

.co.
......
~

a:::
....
N
~

.co.

w

////-

co

0,0000,0000,001 O( +2)

t{ + t) _--r-l-.I!!:====.:Z~E~RO~TR~A~NS~IT~IO~N~_ _ _ _ _ _ ___1
f - - - - - - - -0,0000,0000,000
0,0000,0000,0000(0)

VREF = VREF+ - VREF VIN = VIN + - VIN _
GND :S VIN + :S VA +
GND :S VIN _ :S VA+

------------------

~IVE

FULL-SCALE
TRANSITION

1,0000,0000,0001 (-4095)
1,0000,0000,0000 (-4096)
ANALOG INPUT VOLTAGE (YIN)
Tl/H/11879-10

FIGURE Sa. Transfer Characteristic

+12LSB
POSITIVE
FULL-SCALE
ERROR

II

NEGATIVE
FULL-SCALE
ERROR

-12LSB
OUTPUT CODE

(from -4096 to H095)
Tl/H/11879-11

FIGURE 5b. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles

1-53

CD

.---------------------------------------------------------------------------------~

CO)

-

"=I'

...I

3.0 Electrical Characteristics (Continued)

C"I
.-

:::::i

+3 LSB

~
CO)

+2LSB

..J

"=I'

C"I
.-

::E

...I

ZERO

+1 LSB

! ERROR

_J ________________________ _

T

ERROR

'"

POSITIVE
FULL-SCALE
ERROR

--1

f

-4096
NEGATIVE
FULL-SCALE
ERROR

POSITIVE
INTEGRAL
LINEARITY",-

'"

NEGATIVE
INTEGRAL
LINEARITY
ERROR

-1 LSB
-2LSB
-3LSB
OUTPUT CODE

(from -4096 to +4095)
TUH/11879-12

FIGURE 5c. Simplified Error Curve vs Output Code after Auto-Calibration Cycle

+2

+1

...c

8

0

~--------------~~~~~~-------------!;
I-- OFFSET VOLTAGE
o

-J

-1

-2
ANALOG INPUT VOLTAGE (VIN )
TlIH/11879-13

FIGURE 6. Offset or Zero Error Voltage

1-54

4.0 Typical Performance Characteristics

The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. The performance for a-bit
sign and "watchdog" modes is equal to or better than shown. (Note 9)
linearity Error Change
vs ClK Frequency
0.16

I I I

VA+=VO+=5V
YREr + = 4.096V VREr -

"@"

~
~

linearity Error Change
vs Temperature

r-

= ov

~
<.>

/

1'\

~ 0.00

V

"@"

C>
~

~

z

0.1 ~f-+-+-+-+-+-+-lv~H

~ -0.1 ~f-+-+-+-+-+-+++-j

>-

~

~ -0.08
::l

4

8

6

10

=

VREr +

m

0.3

~

0.1

:il
:5
/:

-0.1

..

.......

3V

"@"

VREr - = OV

d

feLK = 8 LlHz

~

0.2

:il
:5

0.0

TA

= 25°C

.......

~

~

-0.3

VA~ ='VD~

-0.2

TA = 25°C

VAt

~_+-_+- felK

=Yot = 5Y
= 8 MHz

I

~

:il
:5

~

~

-1

~

~

:j

2

1.0

4

..
i3

TA

= 25°C

-

m

d

~

-0.1

~

-0.3

...... -1-"

:5

-u

= 8 MHz TA = 25°C
= 3V YREF - = OY

.,

VRH +

0.0 ~-t---+--+--+--j
-0.5
-1.0 ~-.p..,,""+-"7-F--+--j

-10

~

~
!

1\

20

10

TEMP£RATURE (OC)

100

\

= 25°C

-

.~

-0.1

140

'\

0.0

~

VA+=VD+=5V
VREr + = 4.096V VREF - = OV

:il

:::

TA

, -0.3

=

25°C

o

I I I I I

4

10

8

Zero Error Change
vs Supply Voltage

~
C>

\

0.2

\

'-"'

0.3

~

0.2

:il
:5

0.1

~

-0.2

-211

\

0.4

0.4

•

/--

CLK FREQUENCY (MHz)

VA+=VO+=5V
felK = 8 t.lHz

TA

140

0.3

~

0.6

100

0.1

~

~

:il
:5

60

20

Zero Error Change
vs ClK Frequency

Zero Error Change
vs Reference Voltage

0.1

I--f-"

-20

TEMPERATURE (Oc)

0.8

1
VA + = Yo+ = 5Y
VREF + = .... 096V VREr - = OV

0.3

~

-1.5
-60

SUPPLY VOLTAGE (V)

0.5

~

~

:j

10

0.5

Zero Error Change
vs Temperature

d

-0.5

d

REFERENCE VOLTAGE (V)

"@"

0.0

~

2

I I ) I I

-1.5 '-_.L..._.L..._-'-_..L.._..J
3.0
4.0
5.0

-3
2

~

8

1.5 fCLK

d

5

0

-1

= OV _

i

Full-Scale Error
vs Supply Voltage
'@'

4

0.5

CLK FREQUENCY (MHz)

TA = 25°C

li!

1"\"

=tSyl

o

Full-Scale Error Change
vs Reference Voltage

........,

./"

2

Full-Scale Error Change
vs Temperature

~

VREr + = 4.096V VREr -

SUPPLY VOLTAGE (V)

"@"

o

1.5

l\

r\~

5.0

d

\

-0.1

m

\

POSITIVE FULL-S;;ALE

-0.4
4.0

f'...

0.0

d

\'

"j
2

8ldHz

.REFERENCE VOLTAGE (V)

NEGATIVE FULL-SCALE

1/

~

3.0

~

..~

=

'\.

0.1

Full-Scale Error Change
vs ClK Frequency'
0.4

-0.5

::;!

0.2

TEMPERATURE (OC)

linearity Error Change
vs Supply Voltage
0.5

iil::l

:il
:5

-0.5 L..'-l--'......I.-..L...l....L....l......L....J
-60
-20
20
60
100
140

CLK FREQUENCY ("Hz)

~

0.3

::l

0

VA+-=VO+=5V
TA = 25°C 'elK

5
>-

::l -0.3 ~f-t--+-+-+-+-+++-j

-0.16

0.5
0.4

~

i3

"I-V

:5

Linearity Error Change
vs Reference Voltage

d

TA = 25°C

O.OB

+

.......

...........

~

-

I-

"'"

t- fA = 25°C

VREF + = 3V VRH"- = OV
fCLK = 8 MHz

\
\

0.0

r---....

-:--....

-0.1

o

3.0
REFERENCE VOLTAGE (V)

4.0

5.0

SUPPLY VOLTAGE (V)

TL/H111879-14

1-55

4.0 Typical Performance Characteristics (Continued)

.

The following CUNes apply for 12-bit + sign mode after auto-calibration unless otherwise specified. Th.e performance for a-bit
sign and "watchdog" modes is equal to or better than shown. (Note 9)
.
Analog Supply Current
. vs Temperature
4.0

'<'
.5
~

ii3

i9

V/~
/',/

2.0
-60

,.

'<'
.5

"",,'"
/f\. "

3.0

~

L,.;

= 8 MHz

3.5

2.5

I

VAt = Vo+
felK

°Dlgltal Supply Current
vs Clock Frequency

V

'"

"""

1\

~j;l

1/
2.0

V

~
~

VA' = SVvt
VAt

3.0

ii3

= S.5V

VAt

VD+ = VAt = SV
TA = 25 c c

= 4.5V

V

L

V

°Dlgltal Supply Current
vs Temperature
3.6

-

'<'
.5

V

~

20

60

100

140

VAt = Vo+
- I - feLK = 6 MHz

-

3.2

~

ij;l

2.6

I

2.4

TEMPERATURE (Oc)

'-"f-

I I I
-I- -

VD' = sv

-I- _

VD- =.4.SV - I -

2.0
-60

1

L

VD' = S.SV

is

1.0
-20

+

-I I I
I 1 1

-20

ClK FREQUENCY (MHz)

20

60

100

140

TEMPERATURE (DC)

TLlH/11879-15
'Free-running conversion and
read at 200 ns SCLK period.

SPI

mode data

The following CUNes apply to the LM12L43a in 12-bit + sign mode after auto-calibration unless otherwise specified. Rs = 50.0,
TA = 25·C, VA + = Vo + = 3.3V, VREF = 2.5V, fOLK = 6 MHz, fSOlK = a MHz, VIN = 2.5V - 0 dB, Sampling Rate =
100 kHz.

Unipolar Spectral Response with
10 kHz Sine Wave at 0 dB

Unipolar Spectral Response with
20 kHz Sine Wave at 0 dB

-20
'ii1

-20

HH-t-t lIH.~

'ii1

~

-40

3 -40 f--JH-t-fl)"",',

~

-60

~

~

i

-60

H-+-++-.J-H-.+-+-I

-80

ht-++-t-;+.-H-H-H--i

~

;i
-80
-100

-100

10

20

30

40

so

10

20

30

40

so

FREQUENCY (kHz)

FREQUENCY (kHz)

TL/H/I1879-84

The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. Rs = 50.0, TA = 25°C,
VA + = Vo+ = 5V, VREF = 4.096V, fOLK = a MHz, fSOLK = 10 MHz, VIN = 4.096V - 0 dB, Sampling Rate = 100·kHz.
Unipolar Special Response
with 41.2 kHz Sine Wave
at 0 dB Reading Data
during Conversion fSClK = 10 MHz

Unipolar Special Response
with 41.2 kHz Sine Wave
at 0 dB Reading Data
between Conversions

Or-r-~~~~~-'~

-20

!

§
~

6i

-40

-60
-80~~~~~~--I--I~

-100
-120
-140 '--'-'-'--L.:..J'--J'--J--I-'-'--I
10
20
30
40
o

10

20

30

FREQUENCY (kHz)

FREQUENCY (kHz)

1-56

40

TLlH/11879-55

,------------------------------------------------------------------------------,r
s:::
.....
N

4.0 Typical Performance Characteristics (Continued)
The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified.
10 MHz, VIN = 4.096V-0 dB,
Rs = son, TA = 25°C, VA+ = Vo+ = SV, VREF = 4.096V, fCLK = 8 MHz, fSCLK
Sampling Rate = 133.3 kHz.
Unipolar Signal-to-Noise
Unipolar Total
Harmonic Distortion
Unipolar Signal-to-Noise Ratio
+ Distortion
vs Input Frequency
vslnputFrequency
vs Input Frequency
75

75

~

Co)

.....
r
~

s:::
.....

N

-50

r

-60

Co)

~

72.5
70

~

~
~

z
.....
'"

~

"\

-70

~

/

c

';;;

\

;g

'\

~

70

-80

iE

65

67.5

-90

1

10

..... i.--

-100

60

65

co

100

10

fREQUENCY (kHz)

100

10

fREQUENCY (kHz)

Unipolar Spurious Free
Dynamic Range
vs Input Frequency

100

fREQUENCY (kHz)

Unipolar Spectral Response
with 1.025 kHz
Sine Wave at 0 dB

Unipolar Spectral Response
with 10.010 kHz
Sine Wave at 0 dB

95
90

r-.....

-20

"i
~
~

85

I\,

;
~

<

~

'iii'

-40

-:-

-60

~

-80~-t;-r-t-r1-H-l-+H

~

80

\.

~

-100

'"

-120

VI

75

-140
1

10

10

100

20

30

40

SO

60

fREQUENCY (kHz)

fREQUENCY (kHz)

Unipolar Spectral Response
with 40.283 kHz
Sine Wave at 0 dB

fREQUENCY (kHz)

Unipolar Spectral Response
with 40.283 kHz
Sine Wave at -0.5 dB

Unipolar Spectral Response
with 40.283 kHz
Sine Wave at -1.0 dB

-20

-20

en -.40
3 -60 I-t-r-r-r-t-r-t-H-t--t-H
-80 H-I-I+-+-l*+-H-I-rl-H

~
~

~

;

-8oH-hI+-+-l*+-H-I-M-H

-100

~ -100

'"

-120

u; -120

30

40

50

fREQUENCY (kHz)

-100

.. -120

-140 L...L--'--'-.L....L..J.:.-'-.L....L--1......l..-J!...J
o 10 20 30 40 SO 60

fREQUENCY (kHz)

Unipolar Spectral Response
with 62.256 kHz
Sine Wave at 0 dB

i

-80

-120
-160 L...L--'--'-.L....L.:...l..-'-.L....L--1......l..-.L..J
o 10 20 30 40 50 60

60

§ -80H~~Ht+++-l-+~~

~

~ -100

JJ-I-l-+H-l-+H-++tH
20

-40
-60

~

~

10

~

~

~

~

-140

H++-fHl-++-H-++H

-160 L..1--'-..LL.l--'-..L.L....L--'--'-.L..J
o 10 20 30 40 50 60

70

tn

H++-H-++-H-++H

fREQUENCY (kHz)

Unipolar Two Tone Spectral
Response with 11 = 19.190 kHz and
12 = 19.482 kHz Sine Wave

~

-40

f-I-I-HI-I-f-f-f-f--I--I-+-l

~

-60

I-I-I-HI-I-I-I-I-t-t-t-H

~

-100

~ -80f-f-f-Hf-f-f-f-f--I--I-~+-l

iii -120

-140
-110 ...................- i .........................-i...J
o 10 20 50 40 50 10
fREQUENCY (kHz)

I-I-I-HH+I-+-+-+-+-t--l---j
10

TUH111879-17

20

30

40

fREQUENCY (kHz)

1-57

50

60

TlIH/11879-24

II

4.0 Typical Performance Characteristics (Continued)
The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified.,
5V, VREF = 4.096V, fCLK = 8 MHz, fSCLK = 10 MHz,VIN = ±4.096V -+ 0 dB,
Rs = 50n, TA = 25'C, VA +, = Vo+
Sampling Rate = 133.3 kHz.
Bipolar Signal-to-Nolse
Bipolar, Signal-to-Noise Ratio
+ Distortion vs
Bipolar Total Harmonic
'vs Input Frequency
Distortion vs Input Frequency
Input Frequency
80

80

\

75

-50

,....

3

1\

:if

-70

"

-80

3

~
::;;

70

-so

1\\

75

'iD

\

~
~

70
-90

65
10

1

100

Bipolar Spectral Response
with 10.010 kHz
Sine Wave at 0 dB

-20

85

\

80

"iii' -40

\

3

-60

11-;'..,...,...,-':--;--,..,-:..,...,...,........--1

~

-100

1Ht+t:-t-lr+H~-H-+-I

~ -80~-t-+4-++-H-t-~~

1\

~

*

100

FREQUENCY (kHz)

Bipolar Spectral Response
with 1.025 kHz
Sine Wave at 0 dB

r----

3

~

10

FREQUENCY (kHz)

Bipolar Spurious Free
Dynamic Range
vslnputFrequency

:if

1

100

10

FREQUENCY (kHz)

90

-

-100

S5

1

1/

,/

~ -120

75

70
1

10

10

100

20

30

40

50

SO

10

FREQUENCY (kHz)

FREQUENCY (kHz)

Bipolar Spectral Response
with 40.283 kHz
Sine Wave at 0 dB

Bipolar Spectral Response
with 40.283 kHz
Sine Wave at -0.5 dB

-20
-40

'iD

-40

~

-sO~~~-r~r4~~~~

3

-so ~~-r-1-r~H~-H4-~

§ -80~-H+4-++-~-t-~-+~

-80~-H~-+4-~~~~~

~

~

~

-100

12

-1,00

iii -120

en -120

-140 H~-H"+-f'-H'+-H~~
10

20

30

40

50

-140

H++t1-+''+'-H+'H4-.LJ

SO

10

FREQUENCY (kHz)

20

30

40

50

60

FREQUENCY (kHz)

Bipolar Spectral Response
with 62.25 kHz
Sine Wave at 0 dB

Bipolar Two Tone Spectral
Response with f1 = 19.190 kHz and
f2 = 19.482 kHz Sine Waves

-20

-20

"iii' -40

'iD

-40

3 -60 ~-t-~-+4-H~+-H1H

.3

-60

~ -8o~-t-~~4-H~++H1H
~

~

-80

l

~ -100

~ -100

12

iii -120

VI

-120

-140 ~--+'-~-f+-t'-t~-t-'-I-'f-~

-140

-ISO Ll....L.J...J...L...L..L....l...L...L.L.L.J
o 10 20 30 40 50 SO

-ISO

FREQUENCY (kHz)

TL/H111879-25

11,1' 'Ir '1'11'11rr' "11\'IT!'n'll'

r
o

10

20

30

40

FREQUENCY (kHz)

1-58

30

40

50

SO

Bipolar Spectral Response
with 40.283 kHz
Sine Wave at -1.0 dB

-20

!
§

20

FREQUENCY (kHz)

50

60
TL/H/l1B79-26

5.0 Pin Descriptions
TABLE I. LM12[L}438 Pin Description
Pin Number

SO

Pin Name

Description

PLCC
Pkg.

Pkg.

1

7

DGND

Digital ground. This is the device's digital supply ground connection. It should be connected
through a low resistance and low inductance ground return to the system power supply.

2
3
4
5
6
7
8
9

8
9
10
11
12
13
14
15

INO
IN1
IN2
IN3
IN4
IN5
IN6
IN7

These are the eight analog inputs to the multiplexer. For each conversion to be performed, the
active channels are selected according to the instruction RAM programming. Any individual
channel can be selected for a single·ended conversion referenced to AGND, or any pair of
channels, whether adjacent or non adjacent, can be selected as a fully differential input pairs.

10

16

VREF+

Positive reference input. The operating voltage range for this input is 1V S; VREF + S; VA + (See
Figures 3 and 4). In order to achieve 12-bit performance this pin should be by passed to AGND
at least with a parallel combination of a 10 f.tF and a 0.1 f.tF (ceramic) capacitor. The capacitors
should be placed as close to the part as possible.

11

17

VREF-

Negative reference input. The operating voltage range for this input is 0 V S; VREF - S; VREF +
-1 V (See Figures 3 and 4). In order to achieve 12-bit performance, this pin should be bypassed
to AGND at least with a parallel combination of a 10 f.tF and a 0.1 f.tF (ceramic) capacitor. The
capacitors should be placed as close to the part as possible.

12

18

AGND

Analog ground. This is the device's analog supply ground connection. It should be connected
through a low resistance and low inductance ground return to the system power supply.

13

19

VA+

Analog supply. This is the supply connection for the analog circuitry. The device operating supply
voltage range is + 3.0V to + 5.5V. Accuracy is guaranteed only if the VA + and Vo + are
connected to the same potential. In order to achieve 12-bit performance, this pin should be
. bypassed to AGND at least with a parallel combination of a 10 f.tF and a 0.1 f.tF (ceramic)
capacitor. The capacitors should be placed as close to the part as possible.

14

'20

DGND

Digital ground. See above definition.

15
16

21
22

Vo+

Digital supply. This is the supply connection for the analog circuitry. The device operating supply
voltage range is + 3.0V to + 5.5V. The device accuracy is guaranteed only if the VA + and Vo +
are connected to the same potential. In order to achieve 12-bit performance this pin should be
by passed to DGND at least with a parallel combination of a 10 f.tF and a 0.1 f.tF (ceramic)
capacitor. The capacitors should be placed as close to the part as possible.

17

23

P5

P1-P5 are the multi-function serial interface input or output pins that have different assignments
depending on the selected mode.
Serial interface input:
Standard:
SCLK
TXD
8051:
12C:
SCL
TMS320:
DR

18

24

P4

Serial interface input/output: Standard:
8051:
12C:
TMS320:

DO
RXD
SDA
DR

19

25

P3

Serial interface input:

DI
CS
SAD2
DX

Standard:
8051:
12C:
TMS320:

1-59

5.0 Pin Descriptions (Continued)
TABLE I. LM12(L}438 Pin Description (Continued)
Pin Number
Pin Name

SO

Description

PLCC
Pkg.

Pkg.

20

26

P2

Serial interface input:

Standard:
8051:
12C:
TMS320:

'CS
1
SAD1
FSX

21

27

P1

Serial interface input:

Standard:
8051:
12C:
TMS320:

R/F (Clock rise/fall)
1
SADO
FSR

22
23

28
1

MODESEL2
MODESEL1

Serial mode selection inputs. The logic states of these inputs determine the operation of
the serial mode as shown below. The standard mode covers the National's MICROWIRE,
Motorola's SPI and Hitachi's SCI protocols.
MODESEL 1, MODESEL2:
01
Standard mode
00
8051
12C
10
11
TMS320

24

2

CLK

The device main'clock input. The operating range of clock frequency is 0.05 MHz to
10.0 MHz. The device accuracy is guaranteed only for the clock frequencies indicated in
the specification tables.

25

3

INT

Interrupt output. This is an active low output. An interrupt is generated any time a nonmasked interrupt condition takes place. There are seven different conditions that can
generate an interrupt. (Refer to Section 6.2.4). The interrupt is set high (inactive) by reading
the interrupt status register. This output can drive up to 100 pF of capacitive loads. An
external buffer should be used for driving higher capacitive loads.

26

4

SYNC

Synchronization input! output. SYNC is an input if the Configuration Register's SYNC I/O bit
is "0" and output when the bit is "1". When sync is an input, a rising edge on this pin
causes the internal S/H to hold the input signal and a conversion cycle or a comparison
cycle (depending on the programmed instruction) to be started. (The conversion or
comparison actually begins on the rising edge of the CLK immediately following the rising
edge of sync.) When output, it goes high at the start of a conversion or a comparison cycle
and returns low when the cycle is completed. At power up the SYNC pin is set as an input.
When used as an output it can drive up to 100 pF of capacitive loads. An external buffer
should be used for driving higher capacitive loads.

27

5

STANDBYOUT

Stand-by output. This is an active low output. STANDBYOUT will be activated when the
LM12(L}438 is put into stand-by mode through the Configuration Register's stand-by bit. It
is used to force any other devices in the system (signal conditioning circuitry, for example)
to go into power-down mode. This is done by connecting the "shutdown", "powerdown",
"standby", etc. pins of the other ICs to STANDBYOUT. In those cases where the peripheral
ICs do not have the power-down inputs, STANDBYOUT can be used to turn off their power
through an electronic switch. Note that the logiC polarity of the STANDBYOUT is the
oppOSite to that of the stand-by bit in the Configuration Register.

28

6

VD+

Digital supply. See above definition.
LM12434 Pin Description. (Same as LM12 (L}438 with the exceptions of the following pins.)

LM 12434 Pin Description
6
7

12
13

MUXOUTMUXOUT+

8
9

14
15

S/HINS/H IN+

(Same As LM12 (L}438 with the exception ofthe following pins.)

Multiplexer outputs. These are the LM12434's externally available analog MUX output pins.
Analog inputs are directed to these outputs based on the Instruction RAM programming.
Sample-and-hold inputs. These are the inverting and non-inverting inputs of the sampleand-hold. LM12434 allows external analog signal conditioning circuits to be placed
between MUX outputs and S/H inputs.

1-60

6.0 Operational Information
aged, and a correction coefficient is created. After completion of either calibration mode, the offset correction coefficient is stored in an internal offset correction register.
The LM12434 and LM12{Ll438's overall linearity correction
is achieved by correcting the internal DAC's capacitor mismatch. Each capacitor is compared eight times against all
remaining smaller value capacitors and any errors are averaged. A correction coefficient is then created and stored in
one of the thirteen linearity correction registers. A state machine, using patterns stored in 16-bit x 8-bit ROM, executes
each calibration algorithm.
Once the converter has beelJ calibrated, an arithmetic logic
unit (ALU) uses the offset correction coefficient and the 13
linearity correction coefficients to reduce the conversion's
offset error and linearity error, in the background, during the
12-bit + sign conversion. 8-bit + sign conversions and
"watchdog" comparisons use only the offset coefficient. An
8-bit + sign conversion requires less than half the time
needed for a 12-bit + sign conversion.

6.1 FUNCTIONAL DESCRIPTION
The LM12434 and LM12{Ll438 are multi-functional Data
Acquisition Systems that include a fully differential 12-bitplus-sign self-calibrating analog-to-digital converter (ADC)
with a two's-complement output format, an 8-channel
(LM12{Ll438) or a 4-channel (LM12434) analog multiplexer, a first-in-first-out (FIFO) register that can store 32 con·
version results, and an Instruction RAM that can store as
many as eight instructions to be sequentially executed. The
LM12434 also has a differential multiplexer output and a
differential StH input. All of this circuitry operates on only a
single + 5V power supply. For simplicity, the DAS (Data Acquisition System) abbreviation is used as a generic name for
the members of the LM12434 and LM12{Ll438 family
thoughout this discussion.
Figure 7 illustrates the functional block diagram or user programming model of the DAS. Note that this diagram is not
meant to reflect the actual implementation of the internal
building blocks. The model consists of the following blocks:
-

Diagnostic Mode

A flexible analog multiplexer with differential output at
the front end of the device.

A diagnostic mode is available that allows verification of the
LM12{Ll438's operation. The diagnostic mode is disabled
in the LM12434. This mode internally connects the voltages
present at the VREF+ and VREF- pins to the internal VIN+
and VIN- StH inputs. This mode is activated by setting the
Diagnostic bit (Bit 11) in the Configuration register to a "1 ".
More information concerning this mode of operation can be
found in Section 6.2.2.

A fully-differential, self-calibrating 12-bit + sign ADC
converter with sample and hold.
A 32-word FIFO register as the output data buffer.

-

An 8-word instruction RAM that can be programmed to
repeatedly perform a series of conversions and comparisons on selected input channels.

-

A series of registers for overall control and configuration
of DAS operation and indication of internal operational
status.

-

Interrupt generation logic to request service from the
processor under specified conditions.

-

Serial interface logic for input! output operations between the DAS and the processor. All the registers
shown in the diagram can be read and most of them can
also be written to by the user through the input! output
block.

-

A controller unit that manages the interactions of the
different blocks inside the DAS and controls the conversion, comparison and calibration sequences.

Watchdog Mode
In the watchdog mode no conversion is performed, but the
DAS samples an input and compares it with the values ot
the two limits stored in the Instruction RAM. If the input
voltage is above or below the limits (as defined by the user)
an interrupt can be generated to indicate a fault condition.
The LM12434 and LM{Ll438's "watchdog" mode is used
to monitor a single-ended or differential signal's amplitude
and generate an output if the signal's amplitude falls outsidde of a programmable "window". Each watchdog instruction includes two limits. An interrupt can be generated if the
input signal is above or below either of the two limits. This
allows interrupt to be generated when analog voltage inputs
are "outside the window". After a "watchdog" mode interrupt, the processor can then request a conversion on the
input signal and read the Signal's magnitude.

The DAS has 3 different modes of operation:
- 12-bit + sign conversion
-

8-bit + sign conversion

Analog Input Multiplexer

- 8-bit + sign comparison (also called "watchdog" mode)
The fully differential 12-bit-plus-sign ADC uses a charge redistribution topology that includes calibration capabilities.
Charge re-distribution ADCs use a capacitor ladder in place
of a resistor ladder to form an internal DAC. The DAC is
used by a successive approximation register to generate
intermediate voltages between the voltages applied to
VREF- and VREF+. These intermediate voltages are compared against the sampled analog input voltage as each bit
is charged.

The analog input multiplexer can be configured for any combination of single-ended or fully differential operation. Each
input is referenced to AGND when a multiplexer channel
operates in the single-ended mode. Fully differential analog
input channels are formed by pairing any two channels together.
The LM12434's multiplexer outputs and StH inputs
(MUXOUT+, MUXOUT- and StH IN+, StH IN-) provide
the option for additional analog signal processing after the
multiplexer. Fixed-gain amplifiers, programmable-gain amplifiers, filters, and other processing circuits can operate on
the multiplexer output Signals before they are applied to the
ADC's StH inputs. ,If external processing is not used, connect MUXOUT + to StH IN + and MUXOUT - to StH IN -.

Conversion accuracy is ensured by an internal auto-calibration system. Two different calibration mOde's are available;
one compensates for offset voltage, or zero error, while the
other corrects the ADC's linearity and offset errors.
When correcting offset only, the offset error is measured
once and a correction coefficient is created. During the ,full
calibration, the offset error is measured eight times, aver-

1-61

6.0 Operational Information (Continued)
FIFO REG.
PI
P2
P3
INO
INI
IN2
IN3
IN4
INS
IN6
IN7

P4

P5

MODESEL1

29
30

MODESEL2

31
32

CONTROLLER
(Instruction Sequencer, AlU,
Calibration Coefficients Memory, etc.)
CONFIGURATION REG.

INTERRUPT ENABLE REG.
INSTRUCTION RAM
RP= 10
RP=OI
RP=OO
(RP: RAM Po;nl~;) .....;;..-........,....;.;,....;.;....,,.....;;.....;.;..,,,,

INTERRUPT STATUS REG.

LIMIT STATUS REG.

TIMER REG.

(Limits# 2)

(Limits# 1) (Instructions)
TL/H/11879-27

(a) The LM12{L)438

S/H
IN+
S/H INMUXOUT+
MUXOUT-

:======;-,

FIFO REG.
PI

+------.
+-----,

P2
P3

INO
INI
IN2
IN3

INPUT/
OUTPUT
LOGIC
(Serial
Interface)

29
30
31
32

P4
PS

MODESEL1
MODESEL2

CONTROLLER
(Instruction Sequencer, ALU,
Cali~r8tion Co~fficients t.lemory, etc.)
CONFIGURATION REG.

INTERRUPT ENABLE REG.
INSTRUCTION RAM
RP= 10
RP=OI
(RP: RAM Polnler)

RP=OO

I====+====lf===~~

INTERRUPT STATUS REG.

LIMIT STATU.S REG.

TIMER REG.
(Limits# 2)

(Limits#, 1)

(Instructions)
TL/H/11879-28

(b) The LM12434
FIGURE 7. The LM12{L)438 and LM12434 Functional Block Diagram (Programming Model)

1·62

6.0 Operational Information (Continued)
Acquisition Time
The LM12434 and LM12{L)438's internal StH is designed
to operate at its minimum acquisition time (1.125 [1.5) p.s
for a 12-bit + sign conversion) when the source impedance, Rs, is less than or equal to 60 {80) n (fClK ,;; 8 {6)
MHz). When 60 {80) n < Rs ,;; 4.17 {5.56) kn, the internal StH's acquisition time can be increased to a maximum
of 4.88 {6.5) p's (12 + sign bits, fClK = 8 {6) MHz) to
provide sufficient time for the sampling capacitor to charge.
See Section 6.2.1 (Instruction RAM "00") Bits 12-15 for
more information.

Microprocessor overhead is reduced through the use of the
internal conversion FIFO. Thirty-two consecutive conversions can be completed and stored in the FIFO without any
microprocessor intervention. The microprocessor can, at
any time, interrogate the FIFO and retrieve its contents. It
can also wait for the LM12434 and LM12{L)438 to issue an
interrupt when the FIFO is full or after any number (';; 32) of
conversions have been stored.
Configuration Register
The CONFIGURATION Register is the main "control panel"
of the DAS. Writing 1s and Os to the different bits of the
Configuration Register commands .the DAS start or stop the
sequencer, reset the pOinters and flags, go into "standby"
mode for low power consumption, calibrate offset and linearity, and select sections of the RAM.

Instruction Register
The INSTRUCTION RAM is divided into 8 separate words,
each with 48 (3 x 16) bit length. Each word is separated into
three 16-bit sections. Each word has a unique address and
different sections of the instruction word are selected by the
2-bit RAM pointer (RP) in the configuration register. As
shown in Figure 7, the Instruction RAM sections are labeled
Instructions, Limits # 1 arid Limits # 2. The Instruction section holds operational (12-bit + sign, 8-bit + sign or watchdog) information such as the input channels to be selected,
the mode of operation to be performed for each instruction,
and the duration of the acquisition period. The other two
sections are used in the watchdog mode and the userdefined limits are stored in them. Each watchdog instruction
has 2 limits associated with it (usually a low limit and a high
limit, but two low limits or two high limits may be programmed instead). The DAS starts executing from instruction 0 and moves through the next instructions up to any
user-specified instruction and then "loop back" to instruction O. It is not necessary to execute all 8 instructions in the
instruction loop. The cycle may be repeatedly executed until
stopped by the user. The processor should access the Instruction RAM only when the instruction sequencer is
stopped.

Other Registers
The INTERRUPT ENABLE Register lets the user activate up
to 7 sources for interrupt generation (refer to Section 6.2.3).
It also holds two user-programmable values. One is the
number of conversions to be stored in the FIFO register
before the generation of the Data Ready interrupt. The other
value is the instruction number that generates an interrupt
when the sequencer reaches that instruction.
The INTERRUPT STATUS and LIMIT STATUS Registers
are "Read only" registers. They are used as vectors to indicate which conditions have generated the interrupt and
what watchdog limit boundaries have been passed. Note
that the bits are set in the status registers upon occurrence
of their corresponding interrupt conditions, regardless of
whether the condition is enabled for external interrupt generation.
The TIMER Register can be programmed to insert a delay
before execution of each instruction. A bit in the instruction
register enables or disables the insertion of the delay before
the execution of an instruction.

FIFO Register
The FIFO Register stores the conversion results. This register is "Read only" and all the locations are accessed
through a single address. Each time a conversion is performed the result is stored in the FIFO and the FIFO's internal write pointer points to the next location. The pointer rolls
back to location 1 after a Write to location 32. The same
flow occurs when reading from the FIFO. The internal FIFO
Writes and the external FIFO Reads do not affect each other's pointer locations.

Serial 110
A very flexible serial synchronous interface is provided to
facilitate reading from and writing to the LM12434 and
LM12{L)438's registers. The communication between the
LM12434 and LM12{L)438 and microcontrollers, microprocessors and other circuitry is accomplished through this
serial interface. The serial interface is designed to directly
communicate with the synchronous serial interfaces of the
most popular microprocessors with no extra hardware requirement. The interface has been also designed to simplify
software development.

1-63

6.0 Operational Information (Continued)
Instructlon'RAM
RP= ,10
Limits #2

(Read/Write)
RP = 01
Limits #1

RP = 00
Instructions

ADD = 0000

ADD = 0000

ADD = 0000

ADD = 0001

ADD = 0001

ADD = 0001

ADD = 0010

ADD = 0010

ADD = 0010

ADD = 0011

ADD = 001.1

ADD = 0011

ADD = 0100

"

,

.

,ADD = 0100

ADD = 0100

ADD ;"0101

ADD = 0101

ADD = 0101

ADD,=0110

ADD = 011Q

ADD = 0110

ADD = 0111

ADD = 0111

ADD = 0111

RP = RAM Pointer
ADD'" A3, A2, A1, AO

(Read/Write)
CONFIGURATION REGISTER

ADD = 1000

INTERRUPT ENABLE REGISTER

ADD = 1001

(Read/Write)

(Read Only)
INTERRUPT STATUS REGISTER

ADD = 1010

TIMER REGISTER

ADD = 1011

(Read/Write)

(Read Only)
CONVERSION FIFO
(32 Locations, 1 address)

'I'

ADD = 1100

~--------------------~

(Read Only)
LIMIT STATUS REGISTER
FIGURE 8. LM12434 and LM12 (L)438 User Accessible Registers

1-64

ADD = 1101

I

.------------------------------------------------------------------------------.,
3:
....

6.0 Operational Information (Continued)
6.2 INTERNAL USER-ACCESSIBLE REGISTERS
Figure 8 shows the LM12434 and LMI2[L)438 internal user
accessible registers. Figure 9 shows the bit assignment for
each register. All the registers are accessible through the
serial interface bus. Following are the descriptions of the
registers and their bit assignments.

each of the remaining instructions. With the PAUSE bit set
to "I" in instruction 0, no PAUSE Interrupt (INT 5) is' generated the first time the Sequencer executes Instruction o.
When the Sequencer encounters a LOOP bit or completes
all eight instructions, Instruction a is retrieved and decoded.
A set PAUSE bit in Instruction a now halts the Sequencer
before the instruction is executed. If Pause = 0, the instruction loop continues to execute.
Bits 2-4 select which of the eight input channels (INO-IN7)
will be the non-inverting inputs to the LMI2[L)438's ADC.
(See Table 111.) They select which of the four input channels
(for INO-IN3) will be the non-inverting inputs to the
LM12434's ADC. (See Table IV.)

6.2.1 Instruction RAM
The instruction RAM holds up to eight sequentially executable instructions. Each 48-bit long instruction is divided into
three 16-bit sections. READ and WRITE operations can be
issued to each 16-bit section using the instruction's address
and the 2-bit "RAM pOinter" in the Configuration register.
The eight instructions are located at addresses 0000
through 0111. They can be accessed and programmed in
random order.

Bits 5-7 select which of.the seven input channels (INI to
IN7) will be the inverting inputs to the LMI2[L)438 ADC.
(See Table 111.) They select which of the three input channels (IN1-IN4) will be the inverting inputs to the LM12434's
ADC. (See Table IV.) Fully differential operation is created
by selecting two multiplexer channels, one non-inverting
and the other inverting. A code of "000" selects ground as
the inverting input for single ended operation.

Read/Write Operations
Any Instruction RAM READ or WRITE can affect the sequencer's operation.
Therefore, the Sequencer should be stopped by setting the
RESET bit to a "I" or by resetting the START bit in the
Configuration Register and waiting for the current instruction
to finish execution before any Instruction RAM READ or
WRITE is initiated.
A soft RESET should be issued by writing a "I" to the Configuration Register's RESET bit after any READ or WRITE to
the Instruction RAM.
The three sections in the Instruction RAM are selected by
the Configuration Register's 2-bit "RAM Pointer", bits D8
and D9. The first 16-bit Instruction RAM section is selected
with the RAM Pointer equal to "00". This section can be
programmed for multiplexer channel selection, conversion
resolution, watchdog mode operation, timer or external
SYNC use, pause in instruction and loop bit as described
later. The second 16-bit section holds "watchdog" limit # I,
its sign, and a bit that determines whether an interrupt can
be generated when the input is greater than or less than
limit # 1. The third 16-bit section holds "watchdog" limit # 2,
its sign, and the "greater than/less than" selection bit.

Bit 8 is the SYNC bit. Setting Bit 8 to "I" causes the Sequencer to hold operation at the internal S/H's acquisition
cycle and to wait until a rising edge appears at the SYNC
pin. When a rising edge appears, the StH goes into the
"Hold" mode and the ADC begins to perform a conversion
on the next riSing edge of CLK. To make the SYNC pin
serve as an input, the Configuration register's "SYNC I/O"
bit (Bit 7) must be set to a "0". With SYNC configured as an
input, it is possible to synchronize the start of a conversion
to external events. When SYNC pin is defined as an output
(SYNC I/O bit = 1) the SYNC bit in the instruction registers
must not be set to 1.
When the LM12434 and LMI2[L}438 are used in the
"watchdog" mode with external synchronization, two riSing
edges on the SYNC input are required to initiate the two
comparisons that are performed during a watchdog instruction. The first rising edge initiates the comparison of the
selected analog input signal with Limit # 1 (found in Instruction RAM "01") and the second rising edge initiates the
comparison of the same analog input Signal with Limit #2
(found in Instruction RAM "10").

Instruction RAM, Bank 1, RP = 00
Bit 0 is the LOOP bit. After an instruction with Bit a set to a
"I" is executed, the sequencer will loop back to instruction
o. The next instruction to be executed will be instruction O.
Bit 1 is the PAUSE bit. When the PAUSE bit is set ("1"), the
Sequencer will stop after reading the current instruction.
The instruction will not execute at this pOint, and the START
bit in the Configuration register will reset to "0". Setting the
PAUSE also causes an interrupt to be issued. The Sequencer is restarted by placing a "I" in the Configuration register's Bit a (Start bit).

Bit 9 is the TIMER bit. When Bit 9 is set to "1", the Sequencer will halt until the internal 16-bit Timer counts down
to zero. During this time interval, no "watchdog" comparisons or analog-to-digital conversions will be performed.
Bit 10 selects the ADC conversion resolution. Setting Bit 10
to "I" selects 8-bit + sign and resetting to "a" selects 12bit + sign.
Bit 11 is the "watchdog" comparison mode enable bit.
When operating in the "watchdog" comparison mode, the
selected analog input signal is compared with the programmable values stored in Limit # 1 and Limit # 2 (see Instruction RAM "01" and Instruction RAM "10"). Setting Bit 11 to
"I" causes two comparisons of the selected analog input
Signal, one with each of the two stored limits. When Bit 11 is
reset to "0", an 8-bit + sign or 12-bit + sign (depending on
the state of Bit 10 of Instruction RAM "00") conversion of
the input signal can take place.

After the Instruction RAM has been programmed and the
RESET bit is set to "1", the Sequencer retrieves Instruction
0, decodes it, and waits for a "I" to be placed in the Configuration register's START bit. The START bit value of "I"
"overrides" the action of Instruction a's PAUSE bit when
the Sequencer is started. Once started, the Sequencer executes Instruction a and retrieves, decodes, and executes

1-65

I\)
,j::o,
Co)
,j::o,

,......
3:
....
,
I\)

,j::o,
Co)
(II)

6.0 Operational Information
A4 A3 A2 AI
0

0

0
to
1

0

0

1

0

0

0
to
1

0

0

1

0

0

0

1

0
to
1

0
1

0

0

0

1

1

1

Purpose
Instruction RAM
(RAM Pointer ~ 00)

Instruction RAM
(RAM Pointei ~ 01)

Instruction RAM
(RAM Pointer ~ 10)
Configuration
Register

R/W

0

0

1

Interrupt Enable
Register

1

0

1 '0

Interrupt Status
Register

1

0

1

1

1

1

0

0

Conversion
FIFO

1

1

0

1

LimitStalus
'Register

011

010

09

08

07

06

05

04

SIH IN-

Watch8/12 Timer Sync
dog,

03

02

S/HIN+
(MUXIN+)'

(MUXIN'-)·

01

DO

Pause

Loop

Don't Care

>1< Sign

Limit #1

Don't Care

>1< Sign

Limit #2

R/W

R/W

R

Timer
Register

Acquisition
Time

R/W

R/W
1

(Continued)

Type 01510141013 012

Don't Care

R

Test
~O

RAM
Pointer

SYNC AlZEach
1/0
Cycle

Number of Conversion
ResuHs in FIFO to
Generate Interrupt (INT2)

Instruction
Number to
Generate
Inlerrupt (INn)

INT7

X

Number of Unread
Conversion Results
in FIFO

Instruction
Number
being
Executed

INST7

X

R/W

R

DIAGt

TImer Preset Hil!h Byte
Instruction
Number or
Extended
Sign

Sign

Conversion
Data: MSBs '

lIS
INT5

Stand-

by

Full
CAL

AutoZero

Reset

Start

INT4

INT3

INT2

INn

INTO

INST5 I~ST4, INST3 INST2 INSTI INSTO

TImer Preset Low Byte

Conversion Data: LSBs

Limit #2: Status

Umlt #1; Status

'LM12434 (Roler t~ Table IV):
tLMI2(L)438 only. Must be sel to "0" for the CM12434.
X No interrupt Is' associated with this bH. When programming the interrupl Enable Register, blt~ is ,a don't care condition,

FIGURE 9. Bit Assignments for LM12434 and LM12 {L}438 Internal Registers

1·66

6.0 Operational Information (Continued)
CONFIGURATION REGISTER (Read/Write):
015

I

I

014

013

I

012

Don'teare

011

010

Diag.

Test

09

I

07

06

05

04

03

02

01

DO

RAM

08

Sync

/IS

Full
Gal

Auto
Zero

Start

I/O

Standby

Reset

Pointer

AlZEach
Cycle

DO:

Start: 0 stops the instruction execution. 1 starts the instruction execution.

D1:

Reset: When set to 1, resets Start bit; also resets all the bits in status registers and resets the instruction pOinter to
zero. D1 will then automatically reset itself to zero after 2 clock pulses.

D2:
D3:

Auto-Zero: When set to 1 a long (8-cycle) auto-zero calibration cycle is performed.
Full Calibration: When set to 1 a full calibration cycle (linearity and auto-zero) is performed.

D4:

Standby: When set to 1 the chip goes to low-power standby mode. Resetting the bit will return the chip to active
mode after a short delay.

D5:

I/S: Instruction # or extended sign. 0 = Bits 13-15 of the conversion result hold the instruction number to which the
result belongs; 1 = Bits 13-15 of the result hold the extended sign bit.

D6:

AlZ each Cycle: When set to 1 a short auto-zero cycle is performed before each conversion.

D7:
D9-D8:

Sync I/O: 0 = Sync pin is input: 1 = Sync pin is output.
RAM Pointer: Selects the sections of the instruction RAM, 00

D10:

This bit is used for production testing and must be kept zero for normal operation.

= Instruction,01 = Limits #1, 10 = Limits

#2.

Diagnostic: When set to 1, the LM12(L}438 will perform a diagnostic conversion along with a properly selected
instruction. This mode is not available on the LM12434.
D15-D12: Don't Care.

D11:

INSTRUCTION RAM (Read/Write):
Instruction:
015

I

014

I

013

Acquisition Time

I

D12

Dll
Watchdog

I
I

010
8/12

I 09 I
I Timer I

08
Sync

I
I

07

I

D6

05

D4

MUXIN-

03

02

MUXIN+

01

DO

Pause

Loop

DO:

Loop: 0 = Go to next instruction; 1 = Loop back to in instruction #0.

D1:

Pause: 0 = No pause; 1 = Pause; don't do the instruction. The start bit in the Configuration register resets to 0 when
a pause encountered; a 1 written to the Start bit restarts the instruction execution. .

D4-D2:

MUXIN +: For the LM12( L}438, these bits select which input channel is connected to the ADC's non-inverting input.
For the LM12434, they select which input channel is connected to MUXOUT +.

D7-D5:

MUXIN-: For the LM12(L}438, these bits select which input channel is connected to the ADC's inverting input. For
the LM12434, they select which input channel is connected to MUXOUT -.
Sync: 0 = Normal operation, internal timing, SYNC is an output. 1 = SYNC is an input; S/H and conversion
(comparison) timing are controlled by an external signal applied to SYNC pin.

D8:
D9:

Timer: 0 = Timer is not used for this instruction; 1 = Instruction execution does not begin until timer counts down to
zero.

D10:
D11:

8/12: 0 = 12-bit + sign resolution. 1 = 8-bit + sign resolution.
Watchdog: 0 = Conventional conversion (no watchdog comparison); 1 = Instruction performs watchdog comparisons.

D15-D12: Acquisition Time: Determines S/H acquisition time
For 12-bit + sign: (9 + 2D) clock cycles. For 8-bit + sign: (2 + 2D) clock cycles.
Where D = Contents of D15-D12.
For 12-bit + sign: Choose D for D ~ 0.45 x Rs[kn] x fCLK[MHz].
For 8-bit + sign: Choose D for D ~ 0.36 x Rs[kn] x fCLK[MHz].
Where Rs = Input source resistance.
FIGURE g, Bit ASSignments for LM12434 and LM12(L}438 Internal Registers (Continued)

1-67

6.0 Operational Information (Continued)
INSTRUCTION RAM (Read/Write): (Continued)
Limits #1 & 2
D15

I

I

D14

D13

I

D12

I

Dll

Dl0

Don't Care

I
I

D9

>1<

I
I

DB

DB

D7

D5

D4

Sign

D3

D2

Dl

DO

Limit

07-00:

Limit: 8-bit limit value.

08:

Sign: Sign of limit value, 0 = Positive; 1 = Negative.

>/<: High Limit/Low limit. 0 = Inputs lower than limit generate interrupt, 1 = Inputs higher than limit generate
interrupt.
015-010: Oon't Care.

09:

INTERRUPT ENABLE REGISTER (Read/Write):
D15

I

I

D14

D13

I

D12

I

Dll

Dl0

Number of Conversion

I

D9

I

Results In FIFO to
Generate Interrupt (INT2)

D7

DB

D5

D4

D3

D2

Dl

DO

INT7

X

INT5

INT4

INT3

INT2

INTI

INTO

DB

Instruction Number
to Generate
Interrupt (INT1)

Bits # 0 to 7 enable interrupt generation for the following conditions when the bit is set to 1.
00:
INTO: Generates an interrupt when a limit is passed in watchdog mode.
INT1: Generates an interrupt when the sequencer has loaded the instruction number contained in bits 010, 09, and
08 of the Interrupt Enable register.
INT2: Generates an interrupt when the number of conversion results in the FIFO is equal to the programmed value
(015-011).

01:
02:
03:
04:

INT3: Generates an interrupt when an auto-zero cycle is completed.
INT4: Generates an interrupt when a full calibration cycle is completed.

05:

INT5: Generates an interrupt when a pause condition is encountered.

06:
This bit is a don't care condition. No interrupt is associated with this bit.
07:
INT7: Generates an interrupt when the chip is .returned from standby and is ready for operation.
010-08: Programmable instruction number used to generate an interrupt when that instruction has been reached.
015-011: Programmable number of conversion results in the FIFO to gene~ate an interrupt.
TIMER REGISTER (Read/Write):
D15

I

D14

I

D13

I

D12

I

Dll

I

Dl0

I

D9

I=

N

DB

I

D7

I

DB

I

DB

I

D4

I

D3

I

D2

Timer Preset Value

The Timer delays the execution of an instruction if the Timer bit is set in that instruction.
The time delay is:
Oelay = (32

x

N)

+

2 [Clock Cycles)

FIGURE 9. Bit Assignments for LM12434 and LM 12 [L}438 Internal Registers (Continued)

1-68

I

Dl

I

DO

6.0 Operational Information (Continued)
FIFO REGISTER (Read only):
015

I

014

I

013

Instruction Number
or Extended Sign

012

011

010

I

09

I

08

07

Sign

06

05

04

03

02

01

00

Conversion Result

011-00: Conversion Result:
For 12-bit + sign: 12-bit result value
For B-bit

+ sign: 011-04 = result value, 03-00 =

1110

Sign: Conversion result sign bit, 0 = Positive, 1 = Negative
015-013: Instruction number associated with the conversion result or the extended sign bit for 2's complement arithmetic,
selected by bit 05 (Channel Mask) of the Configuration register.
012:

INTERRUPT STATUS REGISTER (Read only):
015

I

014

I

013

012

011

010

Number of Unread Results
in FIFO

J

09

J

07

06

05

04

03

02

01

00

INST7

X

INST5

INST4

INST3

INST2

INSn

INSTO

08

Instruction Number
Being Executed

Bits # 0 to 7 are interrupt flags (vectors) that will be set to 1 when the following conditions occur. The bits are set to 1 whether
the interrupt is enabled or disabled in the Interrupt Enable register. The bits are reset to 0 when the register is read, or by a
device reset through the Configuration register.
00:

INSTO: Is set to 1 when a limit is passed in watchdog mode.

01:

INST1: Is set to 1 when the sequencer has loaded the instruction number contained in bits 010, 09, and OB of the
Interrupt Enable register.

02:

INST2: Is set to 1 when number of conversion results in FIFO is equal to the programmed value (015-011) in the
Interrupt Enable Register.

03:

INST3: 15 set to 1 when an auto-zero cycle is completed.

04:
05:
06:

INST4: Is set to 1 when a full calibraton cycle is completed.
INST5: Is set to 1 when a pause condition is encountered.
Oon't care.

07:

INST7: Is set to 1 when the chip is returned from standby and is ready.

010-08: Holds the instruction number presently being executed or will be executed following a Pause or Timer delay.
015-011: Holds the number of conversion results that have been put in the FIFO but that have not yet been read by the user.
LIMIT STATUS REGISTER (Read only):
015

I

014

I

013

012

011

010

I

09

I

08

07

Umit #2: Status

06

05

04

03

02

01

00

Limit # 1: Status

The bits in this register are limit flags (vectors) that will be set to 1 when a liniit is passed. The bits are associated to individual
instruction limits as indicated below.
00: Limit # 1 of Instruction #0 is passed.
01: Limit # 1 of Instruction # 1 is passed.
02: Limit #1 of Instruction #2 is passed.
03: Limit #1 of Instruction #3 is passed.
04: Limit # 1 of Instruction #4 is passed.
05: Limit # 1 of Instruction # 5 is passed.
06: Limit #1 of Instruction #6 is passed.
07: Limit #1 of Instruction #7 is passed.
08: Limit #2 of Instruction #0 is passed.
09: Limit #2 of Instruction #1 is passed.
010: Limit # 2 of Instruction # 2 is passed.
011: Limit #2 of Instruction #3 is passed.
012: Limit #2 of Instruction #4 is passed.
013: Limit #2 of Instruction #5 is passed.
014: Limit #2 of Instruction #6 is passed.
015: Limit # 2 of Instruction # 7 is passed.
FIGURE 9. Bit Assignments tor LM12434 and LM12( L)438 Internal Registers (Continued)
1-69

•

CD

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r---------------------------------------------------------------------------------~

6.0 Operational Information (Continued)
Bits 12-15 store the user-programmable acquisition time.
The Sequencer keeps the internal StH in the acquisition
mode for a fixed number of clock cycles (nine clock cycles,
for 12-bit + sign conversions and two clock cycles for 8-bit
+ sign conversions or "watchdog" comparisons) plus a
variable number of clock cycles equal to twice the value
stored in Bits 12-15. Thus, the StH's acquisition time is (9
+ 20) clock cycles for 12-bit + sign conversions and (2 +
20) clock cycles for 8-bit + sign conversions or "watchdog" comparisons, where 0 is the value stored in Bits 1215. The minimum acquisition time compensates for the typical internal multiplexer series resistance of 2 kn, and any'
additional delay created by Bits 12-15 compensates for
source resistances greater than 60.11 {80n}. The necessary
acquisition time is determined by the source impedance at
the multiplexer input. If the source resistance Rs < 60.11
and the clock frequency is 8 MHz, the value stored in bits
12-15 (0) can be 0000. If Rs > 60.11, the following equations determine the value that should be stored in
bits 12-15.
o = 0.45 x Rs x fCLK
for 12-bits + sign
0= 0.36 x RSxfCLK
for 8-bits + sign and "watchdog"
Rs is in kn and fCLK is in MHz. Round the result to the next
higher integer value. If the value of 0 obtained from the
expressions above is greater than 15, it is advisable to lower
the source impedance by using an analog buffer between
the signal source and the LM12{L}438's multiplexer inputs.
The value of 0 can also be used to compensate for the
settling or response time of external processing circuits connected between the LM12434's MUXOUT and StH IN pins..

Instruction RAM, Bank 2 RP = 01
The second Instruction RAM section is selected by placing
"Ol'! in Bits 8 and 9 of the Configuration register.
Bits 0-7 hold "watchdog" limit # 1. When Bit 11 of Instruction RAM "00" is set to a "1", the LM12434 and
LM12{L}438 performs a "watchdog" comparison of the
sampled analog input signal with the limit # 1 value first,followed by a comparison of the same sampled analog input
signal with the· value found in limit #2 (Instruction RAM
"10").
Bit 8 holds limit # l's sign.
Bit 9's state determines the limit condition that generates a
"watchdog" interrupt. A "1" causes a voltage greater than
limit # 1 to generate an interrupt, while a "0" causes a voltage less than limit # 1 to generate an interrupt.
Bits 10-15 are' not used.
Instruction RAM, Bank 3, RP = 10
The third Instruction RAM section is seleCted by placing
"10" in Bits 8 and 9 of the Configuration register.
Bits 0-7 hold "watchdog" limit # 2. When Bit 11 of Instruction RAM "00". is set to a "1", the LM12434 and
LM12{L}438 performs a "watchdog" comparison of the
sampled analog input signal with the limit #1 value first (Instruction RAM "01"), followed by a comparison of the same
sampled analog input signal with the value found in limit # 2.
Bit 8 holds limit #2's sign.
Bit 9's state determines the limit condition that generates a
"watchdog" interrupt. A "1" causes a voltage greater than
limit # 2 to generate an interrupt, while a "0" causes a voltage less than limit # 2 to generate an interrupt.
Bits. 10-15 are not used.

TABLE III. LM12{ L} 438 Operating Mode Input Channel Selection through Input Multiplexer
Normal Operating Mode
Non-Inverting Input
Channel Selection Bits
In Instruction Register
04,03,02

Input Channel to Be
Connected to A/O
Non-Inverting Input
(IN+)

Inverting Input
Channel Selection Bits
In Instruction Register
07,06,05

Input Channel to Be
Connected to A/O
Inverting Input
(IN-)

000

INO

000

GNO

001

INl

001

INl

010

IN2

010

IN2

011

IN3

011

IN3

100

IN4

100

IN4

101

IN5

101

IN5

110

IN6

110

IN6

111

IN7

111

IN7

1-70

r

iii:
....

6.0 Operational Information (Continued)

~

TABLE IV. LM12434 Input Channel Selection through Input Multiplexer
Normal Operating Mode
Non-Inverting Input
Channel Selection Bits
in Instruction Register
04,03,02

Input Channel to Be
Connected to MUX
Non-Inverting Output
(MUXOUT+)

Inverting Input
Channel Selection Bits
In Instruction Register
07,06,05

Input Channel to Be
Connected to MUX
Inverting Output
(MUXOUT-)

000

INO

000

GND

001

INl

001

INl

010

IN2

010

IN2

011

IN3

011

IN3

lXX

None

lXX

None

w
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iii:

....
N
r

TABLE V. LM12 (Lj438 Oiagnostic Mode Input Channel Selection through Input Multiplexer
Oiagnostic Mode
Non-Inverting Input
Channel Selection Bits
In Instruction Register
04,03,02

Input Channel to Be
Connected to A/O
Non-Inverting Input
(IN+)

Inverting Input
Channel Selection Bits
in Instruction Register
07,06,05

Input Channel to Be
Connected to AlO
Inverting Input
(IN-)

000

None

000

None

VREF-

001

VREF+

001

010

IN2

010

IN2

011

IN3

011

IN3

100

IN4

100

IN4

101

INS

101

IN5

110

IN6

110

IN6

111

IN7

111

IN7

1-71

•

6.0 Operational Information (Continued)
analpg circuitry power supply current, and preserves all internal RAM contents. After writing a "0" to the Standby bit,
the DAS returns to an operating state identical to that
caused by exercisin'g the RESET bit. A Standby completion
interrupt is issued after a power-up delay to allow the analog
circuitry to settle. The Sequencer shduld be restarted only
after the Standby completion interrupt is issued (see Note
22). The Instruction RAM can still be accessed. through read
and write operations while the LM12434 and LM12(L}438
are in Standby Mode.

6.2.2 Configuration Register
The Configuration register is a 16-bit control register with
read/write capability. It acts as the LM12434's' and
LM12(L}438's "control panel" holding global information
as well as start/stop, reset, self-calibration, and stand-by
'
,
commands.
Bit 0 is the START/STOP bit. Reading Bit,O returns an indication of, the Sequencer's status. A "0" indicates that the
Sequencer is stopped and waiting to execute the next instruction. A "1" shows that the Sequencer is running. Writ- '
ing a "0" halts the Sequencer when the current instruction
has finished execution. The next instruction to be executed
is pointed to by the instruction pOinter found in the status
register. Writing a "1" to Bit 0 restarts the Sequencer .with
the instruction currently pOinted to by the instruction pointer.
(See Bits 8-10 in the Interrupt Status register.)

Bit 5 is the Channel Address MaSk, If Bit 5 is set to a "1",
Bits 13-15 in the conversion FIFO will be equal to the sign
bit (Bit 12) of the conversion data. Resetting Bit 5 to a "0"
causes conversion data Bits 13 through 15 to hold the instruction pOinter value of the instruction to which the conversion data belongs.
Bit 6 selects a "short", auto-zero correction for every conversion. The Sequencer automatically 'inserts an auto-zero
before every conversion or "watchdog" comparison if Bit 6
is set to "1". No automatic correction will be, performed if Bit
'
.
6 is reset to "0".· .

Bit 1 is the DAS' system RESET bit. Writing.a "1" to Bit 1
stops the Sequencer (resetting the Configuration register's
START/STOP bit), resets the Instruction pointer to "000"
(found in the Interrupt Status register), clears the Conversion FIFO, and resets all interrupt flags. The RESET bit will
return to "0" after two clock cycles unless it is forced high
by writing a "1" into the Configuration register's Standby bit.
A reset signal is internally generated when power is first
applied to the part. No operation should be started until the
RESET bit is "0".

The DAS' offset voltage, after calibration, has a typical drift
of 0.1 LSB over a'temperature range 'of -40·C to + 85·C.
This small drift is less than the variability of the change in
offset that can occur when using the auto-zero cOrrection
with each conversion. This variability is the result of using
only one sample of the offset voltage to create a correction
value. This variability decreases when using t\:lefull calibration mode because eight samples of the offset voltage are
taken, averaged, and used to create a correction value.
Therefore, it is recommended that this mode not be used.
Bit 7 programs the SYNC pin (29) to operate as either an
input or an output. The SYNC pin becomes ari output when
Bit 7 is a "1" and an input when Bit 7 is a "0". With SYNC
programmed as' an input, the rising edge of any logiC signal
applied to pin 29 will ,start a conversion or "watchdog" com-. ,
parison. Programmed as an output, the logic level at pin 29
will go high at the start of a conversion or "watchdog" comparison and remain high until either have finished. See Instruction RAM "00", Bit 8.

Bit 2 is the auto-zero bit. Writing a "1" to this bit initiates an
auto-zero offset voltage calibration. Unlike the eight-sample
auto-zero calibration performed during the full calibration
procedure, Bit 2 ,initiates a "short" auto-zero by sampling
the offset once and creating a correction coefficient (full
calibration averages eight samples of the converter offset
voltage when creating a correction coefficient). If the Sequencer is running when Bit 2 is set to "1", an auto-zero
starts immediately after the conclusion of the currently running instruction. Bit 2 is reset automatically to a "0" and an
interrupt flag (Bit 3, in the Interrupt Status register) is set at
the end of the auto-zero (76 clock cycles). After completion
of an auto-zero calibration, the Sequencer fetches the next
instruction as pOinted to by the Instruction RAM's pointer
and resumes execution. If the Sequencer is stopped, an
auto-zero is performed immediately at the time requested.

Bits 8 and 9 form the RAM Pointer that is used to select
each of a 48-bit instruction's three 16-bit sections during
read or write actions. A "00" selects Instruction RAM section one, "01" selects section two, and "10" selects section
three.

Bit 3 is the calibration bit. Writing a "1" to this bit initiates a
complete calibration process that includes a "long" autozero offset voltage correction (this calibration averages
eight samples of the comparator offset voltage when creating a correction coefficient) followed by an ADC linearity
calibration. This complete calibration is started after the currently running instruction is completed if the Sequencer is
running when Bit 3 is set to "1". Bit 3 is reset automatically
to a "0" and an interrupt flag (Bit 4, in the Interrupt Status
register) will be generated at the end of the calibration procedure (4944 clock cycles). After completion of a full autozero and linearity calibration, the Sequencer fetches the
next instruction as pointed to by the Instruction RAM's
pointer and resumes execution. If the Sequencer is stopped,
a full calibration is performed immediately at the time requested.

Bit 10 activates the Test mode that is used only during production testing. Always write "0" in this bit when programming the Instruction Register.
Bit 11 is the Diagnostic bit and is available only in the
LM12(L}438. It can be activated by setting it to a "1". The
Diagnostic mode, along with a properly chosen instruction,
allows verification that the LM12(L}438's ADC is performing correctly. When activated, the inverting and non-inverting inputs are connected as shown in Table V. As an example, an instruction with "001" for both IN+ and IN- while
using the Diagnostic mode typically results in a full-scale
output.
6.2.3 Interrupts
The LM12434 and LM12(L}438 have seven possible interrupts, all with the same priority. Any of these interrupts will
cause a hardware interrupt to appear on the Tiii'f pin (31) if

Bit 4 is the Standby bit. Writing a "1" to Bit 4 immediately
places the DAS In Standby mode. Normal operation returns
when Bit 4 is reset to a "0". The Standby command ("1")
disconnects the external clock from the Internal circuitry,
decreases the LM12434 and LM12(L}438's Internal

1-72

r-

6.0 Operational Information

(Continued)
they are not masked (by the Interrupt Enable register). The
Interrupt Status register is then read to determine which of
the seven interrupts has been issued.

Bit 3 enables an external interrupt when the single-sampled
auto-zero calibration has been completed.
Bit 4 enables an external interrupt when a full auto-zero and
linearity self-calibration has been completed.

The Interrupt Status register must be cleared by reading it
after writing to the Interrupt Enable register. This removes
any spurious interrupts on the INT pin generated during an
Interrupt Enable register access.
Interrupt 0 is generated whenever the analog input voltage
on a selected multiplexer channel crosses a limit while the
LM12434 and LM12[L]438 are operating in the "watchdog" comparison mode. Two sequential comparisons are
made when the LM12434 and LM12[L]438 are executing a
"watchdog" instruction. Depending on the logic state of Bit
9 in the Instruction RAM's second and third sections, an
interrupt will be generated either when the input signal's
magnitude is greater than or less than the programmable
limits. (See the Instruction RAM, Bit 9 description.) The Limit
Status register will indicate which preprogrammed limit (# 1
or #2) was crossed, and which instruction was executing
when the limit was crossed.

Bit 5 enables an external interrupt when an internal Pause
interrupt has been generated.
Bit 6 don't care condition.
Bit 7 enables an external interrupt when the LM12434 and
LM12[L]438 returns from standby to active mode (see
Note 22).
Bits 8-10 form the storage location of the user-programmable value against which the Sequencer's address is compared. When the Sequencer reaches an address that is
equal to the value stored in Bits 8-10, an internal interrupt
is generated and appears in Bit 1 of the Interrupt Status
register. If Bit 1 of the Interrupt Enable register is set to "1 ",
an external interrupt will appear at pin 31 (INT).
The value stored in bits 8-10 ranges from 000 to 111, representing 1 to 8 instructions stored in the Instruction RAM.
After the Instruction RAM has been programmed and the
RESET bit is set to "1 ", the Sequencer is started by placing
a "1" in the Configuration register's START bit. Setting the
INT 1 trigger value to 000 does not generate an INT 1 the
first time the Sequencer retrieves and decodes Instruction
000. The Sequencer generates INT 1 (by placing a "1" in
the Interrupt Status register's Bit 1) the second time and
every subsequent time that the Sequencer encounters Instruction 000. It is important to remember that the Sequencer continues to operate even if an Instruction interrupt (I NT
1) is internally or externally generated. The only mechanisms that stop the Sequencer are an instruction with the
PAUSE bit set to "1" (halts before instruction execution),
placing a "0" in the Configuration register's START bit, or
placing a "1" in the Configuration register's RESET bit.
Bits 11-15 hold the number of conversions that must be
stored in the Conversion FIFO in order to generate an internal interrupt. This internal interrupt appears in Bit 2 of the
Interrupt Status register. If Bit 2 of the Interrupt Enable register is set to "1 ", an external interrupt will appear at pin 31
(INT).

Interrupt 1 is generated when the Sequencer reaches the
instruction counter value specified in the Interrupt Enable
register's bits 8-10. This flag appears before the instruction's execution. Instructions continue to execute as programmed.
Interrupt 2 is activated when the Conversion FIFO holds a
number of conversions equal to the programmable value
stored in the Interrupt Enable register's Bits 11 -15. This
value ranges from 00000 to 11111, with 00001 to 11111
representing 1 to 31 conversions stored in the FIFO, and
00000 generating an interrupt after 32 conversions. See
Section 6.2.8 for more FIFO information.
The completion of the short, single-sampled auto-zero calibration generates Interrupt 3.
The completion of a full auto-zero and linearity self-calibration generates Interrupt 4.
Interrupt 5 is generated when the Sequencer encounters
an instruction that has its Pause bit (Bit 1 in Instruction RAM
"00") set to "1".
Interrupt 7 is issued after a short delay (10 ms typ) while
the DAS returns from Standby mode to active operation using the Configuration register's Bit 4. This short delay allows
the internal analog circuitry to settle sufficiently, ensuring
accurate conversion results (see Note 22).

6.2.5 Interrupt Status Register
This read-only register is located at address 1010. The corresponding flag in the Interrupt Status register goes high
("1 ") any time that an interrupt condition takes place,
whether an interrupt is enabled or disabled in the Interrupt
Enable register. Any of the active ("1 ") Interrupt Status register flags are reset to "0" whenever this register is read or
a device reset is issued (see Bit 1 in the Configuration Register).
Bit 0 is set to "1" when a "watchdog" comparison limit
interrupt has taken place.
Bit 1 is set to "1" when the Sequencer has reached the
address stored in Bits 8-10 of the Interrupt Enable register.

6.2.4 Interrupt Enable Register
The Interrupt Enable register at address location 1001
has READ/WRITE capability. An individual interrupt's ability
to produce an external interrupt at pin 31 (I NT) is accomplished by placing a "1" in the appropriate bit location. Any
of the internal interrupt-producing operations will set their
corresponding bits to "1" in the Interrupt Status register regardless of the state of the associated bit in the Interrupt
Enable register. See Section 2.3 for more information about
each of the eight internal interrupts.

Bit 2 is set to "1" when the Conversion FIFO's limit, stored
in Bits 11-15 of the Interrupt Enable register, has been
reached.
Bit 3 is set to "1" when the single-sampled auto-zero has
been completed.

Bit 0 enables an external interrupt when an internal "watchdog" comparison limit interrupt has taken place.
Bit 1 enables an external interrupt when the Sequencer has
reached the address stored in Bits 8-10 of the Interrupt
Enable register.

Bit 4 is set to "1" when an auto-zero and full linearity selfcalibration has been completed.

Bit 2 enables an external interrupt when the Conversion
FIFO's limit, stored in Bits 11-15 of the Interrupt Enable
register, has been reached.

Bit 5 is set to "1" when a Pause interrupt has been generated.
1-73

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6.0 Operational Information (Continued)
Bit- 6 no interrupt is associated with this bit. Don't care condition .

activated by the Sequencer only if the current instruction's
Bit 9 is set ("1 "). If' the equivalent decimal value "N"
(0 ,;; N ,;; 2 16 - 1) is written inside the 16-bit Timer register
and the Timer is enabled by setting an instruction's bit 9 to a
"1 ", the Sequencer will delay that instruction's execution by
halting at state 3 (S3), as shown in Figure 11. for 32 x N +
2 clock cycles .

Bit 7 is set to "1" when the DAS returns from standby to
active mode (see Note 22) .
Bits 8-10 hold the Sequencer's current instruction number
while it is running.
Bits 11-15 hold the current number of conversion results
stored in FIFO but have not been read by the user. After
each conversion, the result will be stored in the FIFO and
the contents of these bits incremented by one. Each single
read from FIFO decrements the contents of these bits by
one. If more than 32 conversion results being stored in FIFO
the numbers on these bits roll over from "11111" to
"00000" and continue incrementing. If reads are performed
from FIFO more than the number of conversions stored in it,
the contents of these bits roll back from "00000" to
"11111" and continue decrementing.

6.2.8 FIFO
The result of each conversion is stored in an internal readonly FIFO (First-In, First-Out) register. It is located at address 1100. This register has 32 16-bit wide locations. Each
location holds 13 bits of conversion data. Bits 0-3 hold the
four LSBs in the 12 bits + sign mode or "1110" in the 8 bits
+ sign mode. Sits 4-11 hold the eight MSBs and Bit 12
holds the sign bit. Bits 13-15 can hold either the sign bit,
extending the register's two's complement data format to a
full sixteen bits or the instruction address that generated the
conversion and the resulting data. These modes are selected according to the logic state of the Configuration register's Bit 5.
The FIFO status should be read in the Interrupt Status register (Bits 11-15) to determine the number of conversion results that are held in the FIFO before retrieving them. This
will help prevent conversion data corruption that may take
place if the number of reads are greater than the number of
conversion results contained in the FIFO. Trying to read the
FIFO when it is empty may corrupt new data being written
into the FIFO. Writing more than 32 conversion results into
the FIFO by the ADC results in loss of the first conversion
results. Therefore, to prevent data loss, it is recommended
that the LM12434 and LM12{L)438's interrupt capability be
used to inform the system controller that the FIFO is full.

6.2.6 Limit Status Register
This read-only register is located at address 1101. This register is used in tandem with the Limit # 1 and Limit # 2 registers in the Instruction RAM. Whenever a given instruction's
input voltage exceeds the limit set in its corresponding Limit
register (# 1 or # 2) a bit corresponding to the instruction
number is set in the Limit Status register. Any of the active
(" 1") Limit Status flags are reset to "0" whenever this register is read or a device reset is issued (see Bit 1 in the Configuration register). This register holds the status of limits
# 1 and # 2 for each of the eight instructions.
Bits 0-7 show the Limit # 1, status. Each bit will be set high
(",1 ") when the corresponding instruction's input voltage exceeds the threshold stored in the instruction's Limit # 1 register. When, for example, instruction 3 is a "watchdog" operation (Bit 11 is set high) and the input for instruction 3
meets the magnitude and/or polarity data stored in instruction 3's Limit # 1 register, Bit 3 in the Limit Status register
will be set to a "1".
Bits 8-15 show the Limit #2 status. Each bit will be set
high ("1 ") when the corresponding instruction's input voltage exceeds the threshold stored in the instruction's Limit
#2 register. When, for example, the input to instruction 6
meets the value stored in instruction 6's Limit #2 register,
Bit 14 in the Limit Status register will be set to a "1".

Bits 0-12 hold 12-bit + sign conversion data. Bits 0-3 will
be 1110 when using 8-bit plus sign resolution.
Bits 13-15 hold either the instruction responsible for the
associated conversion data or the sign bit. Either mode is
selected with Bit 5 in the Configuration register.
Using the FIFO's full depth is achieved as follows. Set the
value of the Interrupt Enable registers's Bits 11-15 to
00000 and the Interrupt Enable register's Bit 2 to a "1 ". This
generates an external interrupt when the 31 st conversion is
stored in the FIFO. This gives the host processor a chance
to send a "0" to the LM12434 and LM12{L)438's Start bit
(Configuration register) and halt the ADC before it completes the 32nd conversion. The Sequencer halts after the
current (32) conversion is completed. The conversion data
is then transferred to the FIFO and occupies the 32nd location. FIFO overflow is avoided if the Sequencer is halted
before the start of the 32nd conversion by placing a "0" in
the Start bit (Configuration register). It is important to remember that the Sequencer continues to operate even if
a FIFO interrupt (I NT 2) is internally or externally generated. The only mechanisms that stop the Sequencer are an
instruction with the PAUSE bit set to "1" (halts before instruction execution), plaCing a "0" in the Configuration register's START bit, or placing a "1" in the Configuration register'S RESET bit.

6.2_7 Timer
The LM12434 and LM12{L)438 have an on-board 16-bit
timer that includes a 5-bit pre-scaler. It uses the clock signal
applied to pin 23 as its input. It can generate time intervals
of 0 through 221 clock cycles in steps of 25. This time interval can be used to delay the execution of instructions. It can
also be used to slow the conversion rate when converting
slowly changing signals. This can reduce the amount of redundant data stored in the FIFO and retrieved by the controller.
The user-defined timing value used by the Timer is stored in
the 16-bit READ/WRITE Timer register at location 1011 and
is pre-loaded automatically. Bits 0-7 hold the preset value's
low byte and Bits 8-15 hold the high byte. The Timer is

1-74

6.0 Operational Information

(Continued)
State 2: Perform calibration. If bit 2 or bit 6 of the Configuration register is set to a "1", state 2 is 76 clock cycles long.
If the Configuration register's bit 3 is set to a "1", state 2 is
4944 clock cycles long.

6.3 INSTRUCTION SEQUENCER

The Sequencer uses a 3·bit counter (Instruction Pointer, or
IP) to retrieve the programmable conversion instructions
stored in the Instruction RAM. The counter is reset to 000
during chip reset or if the current executed instruction has
its Loop bit (Bit 1 in any Instruction RAM "00") set high
("1 "). It increments at the end of the currently executed
instruction and points to the next instruction. It will continue
to increment up to 111 unless an instruction's Loop bit is
set. If this bit is set, the counter resets to "000" and execu·
tion begins again with the first instruction. If all instructions
have their Loop bit reset to "0", the Sequencer will execute
all eight instructions continuously. Therefore, it is important
to realize that if less than eight instructions are programmed, the Loop bit on the last instruction must be set.
Leaving this bit reset to "0" allows the Sequencer to execute "unprogrammed" instructions, the results of which may
be unpredictable.

State 3: Run the internal 16-bit Timer. The number of
clock cycles for this state varies according to the value
stored in the Timer register. The number of clock cycles is
found by using the expression below
32T

+2

where 0 s;: T s;: 216 -1.
State 7: Sample the input signal and read Limit # 1's value if needed. The number of clock cycles for acquiring the
input signal in the 12-bit + sign mode varies according to
9

+ 2D

where D is the user-programmable 4-bit value stored in bits
12-15 of Instruction RAM "00" and is limited to 0 s;: D s;:
15.

The Sequencer's Instruction Pointer value is readable at
any time and is found in the Status register at Bits 8-10.
Figure 10 illustrates the instruction execution flow as performed by the sequencer. The Sequencer can go through
eight states during instruction execution:

The number of clock cycles for acquiring the input signal in
the 8-bit + sign or "watchdog" mode varies according to
2 + 2D
State 6: Perform first watchdog comparison. This state is
5 clock cycles long.

State 0: The current instruction's first 16 bits are read
from the Instruction RAM "00". This state is one clock cycle
long.

State 4: Read Limit #2. This state is 1 clock cycle long.
State 5: Perform a conversion or second watchdog com·
parison. This state takes 44 clock cycles for a 12-bit + sign
conversions or 21 clock cycles for a 8-bit + sign conversions. The "watchdog" comparison mode takes 5 clock cycles.

State 1: Checks the state of the Calibration and Start bits.
This is the "rest" state whenever the Sequencer is stopped
using the reset, a Pause command, or the Start bit is reset
low ("0"). When the Start bit is set to a "1", this state is one
clock cycle long.

•

1-75

6.0 Operational Information (Continued)
RESET

y

Start Bit= 1

• Store Conversion Results in FlrO
elncrement Contents of Bits 12-15
In Interrupt Status Register

• Set Interrupt Flags if Condition
has occurred

Perform Second Comparison
or Conversion

L-______~====j-~--~~
._---------------------------------_.

FIGURE 10. Sequencer Logic Flow Chart (IP = Instruction Pointer)

1-76

TL/H/11879-19

7.0 Digital Interface
In order to read from or write to the registers of the
lM12434 and lM12{l)438 a very flexible serial synchronous interface is provided. Communication between the
lM12434 and lM12{l)438 and microcontrollers, microprocessors and other circuitry is accomplished through this
serial interface. The serial interface is designed to directly
communicate with synchronous serial interface of the most
popular microprocessors and 12C serial protocol with no additional hardware required. The interface has been also designed to accommodate easy and straightforward software
programmil)g.
The lM12434 and lM12{l)438 supports four selectable
protocols as shown in Table VI. The MODESEl1 and
MODESEl2 inputs select the desired protocol. These pins
are normally hardwired for a selected protocol, but they can
also be controlled by the system in case a protocol change
within the system is required. P1-P5 are multi-function serial interface input or output pins that have different assignments depending on the selected interface mode.
The "Standard" interface mode uses a simple shift register
type of serial data transfer. It supports several micro controllers' serial synchronous protocols, including: National Semiconductor's MICROWIRE/PlUS, Motorola's SPI, aSPl, and
Hitachi's synchronous SCI. Section 7.1.1 shows general
block diagrams. of how the serial DAS, configured in the
Standard Interface Mode, can be connected to the HPC and
68HC11. Also, detailed assembly routines are included for
single writes, single reads and burst read operations.

The "12C" mode supports the Philips' 12C bus specification
for both the standard (100 kHz maximum data rate) and the
fast (400 kHz maximum data rate) modes of operation. The
DAS behaves as a slave device on the 12C bus and receives
and transmits the information under the control of a bus
master. Section 7.4.1 shows a general block diagram of
how the serial DAS, configured in the 12C Interface mode,
can be connected to an 12C bus using an 12C controller
(PCD8584).
All the serial interface modes.allow for three basic types of
data transfer; these are single write, single read and burst
read. In a single write or read, 16 bits (2 bytes) of data is
written to or read from one of the registers inside the DAS.
In a burst read, multiple reads are performed from one register without having to repeatedly send the control and register address information for each read. The burst read can
be performed on any lM12434 and lM12{l)438's register,
however it is primarily provided for multiple reads from the
FIFO register (one address, 32 locations), where a sequence of conversion results is stored.
7.1 STANDARD INTERFACE MODE
The standard interface mode is a simple shift register type
of serial data transfer. The serial clock synchronizes the
transfer of data to and from the lM12434 and lM12{l)438.
The interface uses 4 lines: 2 data lines (DI and DO), a serial
clock line (SClK) and a chip-select (CS) line. More than one
device can share the data and serial clock lines provided
that each device has its own chip-select line.

The "8051" mode supports the synchronous serial interface
of the 8051 family of microcontrollers (8051 serial interface
Mode 0). It is also compatible with the serial interface in the
MCS-96 family' of 16-bit microcontrollers. Section 7.2.1
shows a general block diagram of how the serial DAS, configured in the 8051 Interface Modes can be connected to
the 8051 family of /LCs. Also, detailed assembly routines for
a single write, single read and' burst read operations are
included.
.

The lM12434 and lM12{l)438 standard mode is selected
when the MODESEl1 and MODESEl2 pins. have the logic
state of "01". Figure 12 shows a typical connection diagram
for the lM12434 and lM12{l)438 standard mode serial
interface. The CS, DI, DO, and SClK lines are respectively
assigned to interface pins P2 through P5. The P1 pin is
assigned to, a signal called R/F (Rise/Fall). The logic level
on this pin specifies the polarity of the serial clock:
- If R/F = 1, data is shifted after falling edge and is stable
and captured at the rising edge of the SClK.

The "TMS320" mode is designed to directly interact with
the serial interface of the TMS320C3x and TMS320C5x
families' of digital signal processors. This interface is also
compatible with the similar serial interfaces on the
DSP56000 and the ADSP2100 families of DSP processors.
Section 7.3.1 shows a general block diagram of how the
s'erial DAS, configured in the TMS320 interface mode, can
be connected to the TMS320C3x family of DSP processors.
Also, detailed assembly routines for a single write, single
read and burst read operations are included.

-

If R/F = 0, data is shifted after rising edge and is stable
and captured at the falling edge of the SClK.

TABLE VI. lM12434 and LM12{L)438 Interface Modes and Pin Assignments
Interface
Mode

MODESEL1

MODESEL2

P1

P2

P3

P4

P5

Standard

0

1

R/F

CS

DI

DO

SCLK

8051

0

0

l'

l'

CS

RXD

TXD

TMS320

1

1

FSR

FSX

DX

DR

ClK

12C

1

0

Slave ADO

SiaveAD1

SiaveAD2

SDA

SCl

'Intemally pulled-up

1·77

•

7.0 Digital Interface (Continued)
In both cases the data transfer is insensitive to idle state of
the SClK. SClK can stay at either logic level high or low
when not clocking (see Figure 11)

This data is written to the register addressed in the command byte (A3, A2, A 1, AO). The data is interpreted as MSB
or lSB first based on the logic level of the 7th bit (MSBI
lSB) in the command byte. There is no activity on the DO
line during write cycles and the DAS leaves the DO line in
the high impedance state. "CS will go high after the transfer
of the last bit, thus completing the write cycle.
Read cycle: A read· cycle starts the same way as a write
cycle, except that the command byte's R/W bits equal to
one. Following the command byte, the DAS outputs the
data on the DO line synchronized with the microcontroller's
SClK. The data is read from the register addressed in the
command byte. Data is shifted out MSB or lSB first, depending on the logic level of the MSB/lSB bit. The logic
state of the 01 line is "don't care" after'the command byte.
CS will go high after the transfer of the last data bit, then
completing the read cycle.
Burst read cycle: A burst read cycle starts the same way
as a single read cycle, but the B bit in the command byte is
set to one, indicating a burst read cycle. Following the command byte the data is output on the DO line as long as the
DAS receives SClK from the system. To tell the DAS when
a burst read cycle is completed pull CS high after the 8th
and before the 15th SCLK cycle during the last data byte
transfer (see Figure 11i). After CS high is detected and the
last data bit is transferred, the DAS is ready for a new communication cycle to begin.
The timing diagrams in Figure 11 show the transfer of data
in packets of 8 bits (bytes). This represents the way the
serial ports of most microcontrollers and microprocessors
produce serial clock and data. The DAS does not require a
gap between the first and second byte of the data; 16 continuous clock cycles will transfer the data word. However,
there should be a gap equal to 3 ClK (the DAS main clock
input, not the SClK) cycles between the end of the command byte and the start of the data during a read cycle. This
is not a concern in most systems for two reasons. First, the
processor generally has some inherent gap between byte
transfers. Second, the SClK frequency is usually significantly slower than the ClK frequency. For example, a
68HC11 processor with an 8 MHz crystal generates a maximum SClK frequency of 1 MHz. If the DAS is running with a
6 MHz ClK, there are 6 cycles of ClK within each cycle of
SClK and the requirement is satisfied even if SClK operates continuously during and after the·command byte.

Data transfer in this mode is basically byte-oriented. This is
compatible with the serial interface of the target microcontrollers and microprocessors. As mentioned, the lM12434
and lM12[l}438 have three different communication cycles: write cycle, read cycle and burst read cycle. At the
start of each data transfer cycle, "command byte" is written
to the serial DAS, followed by write or read data. The command byte informs the lM12434 and lM12[l}438 about
the communication cycle.· The command byte carries the
following information:
what type of data transfer (communication cycle) is started
which device register to be accessed

-

The command byte has the following format:
rirst bit

8th bit

~

11

~

IRIWIA3IA2IA1IAOI~!:/1
'-------v---'
CAS Internal Register
Address
{ o = Writ. cycle
1

-

Always 1

= Read cycle

B

1

L{

0
1

=Single read or writ, cycle
=Burst read cycle

{ 0 '" LSB first in data Iranner
1 = !.ISB first in data transfer
TLlH/11879~52

Note that the first bit may be either the MSB or the lSB of
the byte depending on the processor type, but it must be the
first bit transmitted to the lM12434 and lM12[L}438.
Figure 11 shows the timing diagrams for different communication cycles. Figures 11a, b, C, d show write cycles for
various combinations of R/F pin logic level and SClK idle
state. Figures 11e, f, g, h show read cycles for similar sets
of conditions. Figure 11i shows a burst read cycle for the
case of R/F = 0 and low SClK idle state. Note that these
timing diagrams depict general relationships between the
SClK edges, the data bits and CS. These diagrams are not
meant to show guaranteed timing. (See specification tables
for parametriC switching characteristics.)
Write cycle: A write cycle begins with the falling edge of
Then a command byte is written to the DAS on the 01
line synchronized by SClK. The command byte has the
R/W and B bits equal to zero. Following the command byte,
16 bits of data (2 bytes) is shifted in on the same 01 line.

CS.

1-78

r-

3:
.....
N

7.0 Digital Interface (Continued)
10DAS
CS [From
SY'lem] \

\~.

______________________________________________________________________J

,-

16

SCLK [Seri., ClOCk]
I I

II

I I

3:
.....
N
01:00

Co)
Q)

Seri., 0.1. ]
to DAS

Reed/Write Bit
"0" for write

DO

.....
r01:00

r-

to DAS

DI [

01:00

Co)

"1" MSB 1st
"0" LSB l,t

High Impedance, no activity on DO line during writes

[Seri., 0.1. ]
From OAS

TL/H/11879-30

Idle State of SCLK

wDAS
CS [From
SY'lem] \

\~.

=

(a) Write Cycle, RtF Input (P1) = 1
0, Data Stable at Rising Edge and Shifted at Falling Edge of the SCLK

______________________________________________________________________J

r

SCLK [Seri., ClOCk]
10 DAS

I I

DI [

Read/Write Bit

"0" for write

DO

II

II

Seri., D.t. ]
10 DAS

[Seri., D.t. ]

"1" MSB 1st
"0" LSB lsi

High Impedance, no activit)' on 00 line during writes

From CAS
TLlH/llB79-31

(b) Write Cycle, RtF Input (P1) = 1,
Idle State of SCLK = 1, Data Stable at Rising Edge and Shifted at Falling Edge of the SCLK
FIGURE 11. Timing Diagrams for LM12434 and LM12{L1438 Standard Serial Interface

1-79

•

7.0 Digital Interface (Continued)
CS

[From system]
to DAS

~

"""\

__________________________--Jr
16

SCLK

[ Seri~1 ClOCk]

to DAS

II

01

II

II

[ Serial Data]
to DAS

Start Bit

=1

Read/Write Bit
"0" for write

DO [s.rial Data]

"1" "'SB 1st
"0" LSB lst

High Impedance, no activity on DO

lin. during writes

From DAS

TLlH/11879-32

(c) Write Cycle, RtF Input (P1) = 0
Idle State of SCLK = 0, Data Stable at Failing Edge and Shifted at Rising Edge of the SCLK

~----------------------------_I
16

II

Read/Writ. Bit
"0" for write

DO [Serial Data]

"I" ~SB 1st
"0" LSB 1st

High Impedance, no activity on DO line during writes

,From DAS

TLlH/11879-33

(d) Write Cycle, RtF Input (P1) = 0
Idle State of SCLK = 1, Data Stable at Failing Edge and Shifted at Rising Edge of the SCLK
FIGURE 11. Timing Diagrams for LM12434 and LM12{L}438 Standard Serial Interface (Continued)

1-80

r-

3:
.....

7.0 Digital Interface (Continued)
toOAS
CS [From
system] \

\~.

N

______________________________________________________________________

16

1

SCLK

[Se~~alo~~Ck]

-flJlJlJlflJUUlJJlfUl
I I

DI

""

c.:I

CD

I

[Sariel Oeta ]

3:
.....
N

r-

I I

II

[Serial Oeta ]
to OAS

II
I I
I I

I
I I

DO

c.:I

~

I I

I I

,-

~

""
.....
""r-

I

I
I I

High Impedance

From DAS

1st Data Byte

2nd Data Byte

TL/H/11879-34

(e) Read Cycle, RtF Input (P1) = 1
Idle State of SCLK = 0, Data Stable at Rising Edge and Shifted at Falling Edge of the SCLK

(f) Read Cycle, RtF Input (P1) = 1
Idle State of SCLK = 1, Data Stable at Rising Edge and Shifted at Falling Edge of the SCLK
FIGURE 11. Timing Diagrams for LM12434 and LM12(L)438 Standard Serial Interface (Continued)

1·81

7.0 Digital Interface (Continued)

r

CS [from system] -'\

\~.....................................................................................................................................~

toDAS

16

SCLK [Seri., ClOCk]
to DAS

III

II

I II

I I

01

. High Impedance

DO [Seri., D.t. ]
from DAS

1st Data 8yte

2nd Data Byte

TLlH111879-36

Idle State of SCLK

system]
CS [From
to DAS

7'

(g) Read Cycle, R/F Input (P1) = 0
0, Data Stable at Failing Edge and Shifted at Rising Edge of the SCLK

\
9

SCLK

16

r

[ Serial ClOCk]

to DAS
II

II

II

I I

I I

01

II

DO, [ Serial Data]
From DAS

High Impedance

,

O1S

DD

1st Data Byte

2nd Data Byte

TLIH111879-37

(h) Read Cycle, R/F Input (P1) = 0
Idle State of SCLK = 1, Data Stable at Failing Edge and Shifted at Rising Edge of the SCLK
FIGURE 11. Timing Diagrams for LM12434 and LM12 {L}438 Standard Serial Interface (Continued)

1-82

.....

o

-

CS

SCLK

c
m'
;:::;:

[From system] \ ,

~

to DAS

JUlJ ....

[ Serial ClOCk]
to DAS
II

01

~

r+

CD

'"I

I»

(')

[ Serial Data]
to DAS

CD

'0
o
3-

"0" LSB 1st I

I
I I
I I

I I
I I

DO

[Serial Data]

~

II
I I
II

I I
I I

I I
I I
I I

5"
c

I I
I I
I I

III

B

High Impedance

From DAS
1st Data Byte. 1st Word

-

I I

2nd Data Byte. 1st Word

1st Data Byte, 2nd Word

PMflUlfffllijijJIUUlfffll/

CS (Cont.) ••••

I

8 1

16

SCLK (Cont.) ••••
I I

01 (Cont.) ••

2nd Data Byte. 2nd Word

I I

II

II

II

II

II

16

UL
II

··/ffUnJlnnIIIUnJlnnnIIIII/I/JnnnrflfnnnnJIUnUnnUnJlffUUUfII/UIUUUUmJI@flffffUlmJlg//uUlllllllfU1///UI//UU/lj
I I
I I
I I
I I
II
II
I I

I I
I I
I I
I I
I I
I I
II

I I
I I
I I
I I
II
II
I I

II
II
II
I I
I I
I I
I I

II

I I
II
II
I I

II
I I
I I
II
II

I I
II
II
I I
I I
I I
II

II
II
II
II
II
II
I I

DO (Cont.) ••••
1st Data Byte. (N-1)th Word

Idle State of SCLK

2nd Data Byte. (N-1)th Word

1st Data Byte, Nth (last) Word

2nd Data Byte, Nth (Last) Word

TL/H/11879-38

(I) Burst Read Cycle, R/F Input (P1) = 1
= 0, Data Stable at Rising Edge and Shifted at Falling Edge of the SCLK

FIGURE 11, Timing Diagrams for LM12434 and LM12( Ll438 Standard Serial Interface (Continued)

9&~{'1~~W'/~&~~~W'

II

....~

-....

....
....
.........
....
....
:E
N

7.0 Digital Interface (Continued)
7.1.1 Examples of Inter1aclng to the HPC's MICROWIRE/PLUS and 68HC11's SPI

:E

LM 12434/
LM 12{L}438

CO)

N

....

MODESEL 1

V

HPC'"
family of
Microcontrall,rs

+5Vo- MODESEL2
+5V 0- PI (R/r)

------

Gener.1 {
Purpose
Parallel Port

Serial
Pori

ro

SI

~

r--

P2(C5)
P3(OI)
P4(OO)
P5(SCLK)

D.t. -}

D.ta Clock __

To other
Peripher.l.

SK
TL/H/11879-65

Note: Other device pins are not shown.

FIGURE 12a. LM1:il434 and LM12{L}438 Standard Mode Inter1ace to the HPC's MICROWIRE/PLUSTM
LM12434/
LMI2{L}438
MODESEL 1

V

68HCll
family of

+5Vo- MODESEL2

Microcontrallers

-------

+5V or GND 0- PI (R/r)

General {
Purpose
Parallel Port

~

P2(C5)
P3(Dr)
P4(DO)
P5(SCLK)

D.t. -SI
Serial MISO·
Pori rO
SCK

}

Data Clock . .

To other
Peripheral.

TL/H/11879-66

Note: Other device pins are not shown.

FIGURE 12b. LM12434 and LM12{L}438 Standard Mode Inter1aceto the 68HC11'sSPI

1-84

7.0 Digital Interface (Continued)
; * ••••••••• * •• * ••••••• * ••

*. *•• * ••••

HPC Assembly,Code Example
* ••• * •••

* ••••• * *. *_ . . _••• *."' •••••• * ••• l1li • •

*.

, THE HPC MICROCONTROLLER ASSEMBLY SUBROUTINES FOR INTERFACE TO THE UI12434 ,IND LMl2!Ll43B
, SERIAL DATA ACQUISITION SYSTEM (SDAS) CHIP.

; * ••••• ***** •••••• * ••• * ••• l1li l1li • • • * * •••••
j ••••
j

j
j"

_* •••• * ••••••• * •••• * •• *

*.- *. *
* ._.

*._. * •• * * •• * ••• __ *. *. * ••• * * ••.*. '" * ••••• *
* * •• * *.'" * •••• * ••• *. * .... * •••• * ...... ** *

*-

HPC' s CONTROL REGISTER ADDRESSES SYJolBOLIC DEFINITIons. USED IN
INTERFACE ROUTINES

** ••• _..... * ••••••••••••••••• "' •• * ••• ".* *** * ••• *. ** * * .... *

*._ . * *._._ .. ** '" *._ . . *

A
B

.. OxOOCB

K
X

'" OxOOCA
.. OxOOCE
.. OxOOE2

iB REGISTER
;K REGISTER
;X REGISTER
i PORT B DATA REGISTER

... OxODD2

i

'" OxOOD6
.. OxOOCB

;MICROWIRE INPUT/OUTPUT SHIFT REGISTER

- OxOOC9
.. OxOD

; ACCUMULATOR HIGH ORDER BYTE
j SYMBOL FOR BIT- 0 IN IRPO REGISTER TO TEST
i THE END OF MICROWIRE TRANSFER

PORTB
IRPD
SIO
AL
AH
uWDONE

OxOOCC

jACCUMULATOR

INTERRUPT PENDING REGISTER

j ACCUMULATOR LOW ORDER BYTE

; *. * ... * * .. * * ..... * ..... * * * .. * ..... * * * .......... * *. * ....... * ... * '*.* * * ... * * .... * ..... * .... * * •• *. * .... * * * ..
, SERIAL DAS RELATED REGISTERS, CONSTANTS AND MEMORY BLOCK BASE ADDRESSES
SYMBOLIC DEFINITIONS

;*._ .. - •.•.••.•..•.• * ** * ****** *'* .***'****** *....... *.. ** .... ** .... *.. * * *.... * '* *** ** **** •• *
j

RINSTRO • OxC2
WINSTRO
OxB2
RINSTRI .. OxC6

WINSTR1
RINSTR2
WINSTR2
RINSTRl
WINSTRl
RINSTR4
WINSTR4
RINSTRS
WINSTRS
RINSTR6
WINSTR6
RINSTR7

• OxB6
• OxCA

• OxDA
• Ox9A
- OxDE

WINSTR7

Ox9E

•

RINTSTAT= OxEA
-

,READ/WRITE BIT AND THE MSB/LSB BIT
, PREDEFINED.

Ox8A
OxCE
OxBE
OxD2
Ox92
Ox06
Ox96

RCONFIG • OxE2
WCONFIG
OxA2
RINTEN '" OxE6
WINTEN .. OxA6
RTIMER

iSERIAL DAS INSTRUCTION RAM ANO LIMITS 1 & :2
; READ AND WRITE CONTROL BYTES. THESE BYTES
iCONTAIN THE ADDRESS OF THE SOAS REGISTER. THE

OxEE

WTIMER

OxAE

RSFIFO
RBFIFO

.. OxF2
.. OxF3

RLMTSTAT- OxF6

•

,SDAS CONFIGURATION REG. READ CONTROL BYTE.
; 8DAS CONFIGURATION REG. WRITE CONTROL BYT:E:.
; SOAS
; SDAS
;SCAS
;SDAS
iSOAS
;SDAS

INTERRUPT ENABLE REG. READ CONTROL BYTE.
INTERRUPT ENABLE REG. WRITE CONTROL BYTE .
INTERRUPT STATUS REG. READ CONTROL BYTE:
TIMER REG. READ CONTROL BYTE.
TIMER REG. WRITE CONTROL BYTE.
FIFO , SINGLE READ CONTROL BYTE.

; SOAS FIFO , BURST READ CONT~OL BYTE.
; SDAS LIMIT STATUS REG. READ CONTROL BYTE.
;BIT-X OF HPC PORT B USED FOR SOAS CHIP

;SELECT.
; SYMBOLIC STARING ADDRESS OF THE DATA BLOCK
,IN SYSTEM MEMORY, USED TO STORE THE
jCONVERSION RESULTS READ FROM FIFO IN BURST

DATA_BUF- OXXXXX
CNTRL_BUF-OXXXXK

; READ ROUTINE.
'
;SYMBOLIC ADDRESS FOR A 16 BIT DATA BUFFER
iSYMBOLIC ADDRESS FOR AN B BIT BUFFER USED

; IN ROUTINES FOR CONTROL BYTE.
,SYMBOLIC DEFINITION FOR THE NUMBER OF
; RESULTS TO BE READ FROM FIFO IN BURST READ

; .**.'**'***.* .'**'* **'*. '** * **** '* **** **.* *** *'**. ** *'** ** ••• *.* •• * ** *** ***. *'**. * •• '* ...
SERIAL DAS READS AND WRITES ARE PERFORMED BY SUBROUTINES SER_WR & SER_RD,
, THESE ROUTINES USE THE CNTRL_BUF REGISTER AS CONTROL INPUT AND THE DATA_BUF
, REGISTER AS DATA BUFFER. FOR WRITES DATA IS LOADED IN THE DATA_BUF REG. AND
FOR READS DATA RETURNS IN THE DATA_BUF REGISTER.
I ••

*. * '* '* '* ..... * * '** '* * ... * * ............... '* •••• * *". '* ** * ... "* ••••• *.*. * •• ** * *'* '*. '* '*." ..... '* ... * '* *

1·85

TL/H/11879-5a

CD ,---------------------------------------------------------------------------------,

('I)
~

~

..J

7.0 Digital Interface (Continued)
HPC Assembly Code Example (Continued)

N
..-

:E

, - - - AN EXAMPLE OF A WRITE TO CONFIGURATION REGISTER,

..J

;;;:

LD

('I)
~

LD

::&

JSR

CNTRL_BUF. B, #WCONFIG

,CONFIGURATION REG. WRITE COMMAND
; LOADED IN THE CNTRL_aUF.

N
..-

DATA_BUF. W, #ox0002

,DATA LOADED ON THE DATA_ BUF REG. RESET SDAS,
iPAUSE=l, RAM POINTER",OQ .

..J

,CALLING SER_WR FOR DATA TRANSFER.

,--- AN EXAMPLE OF A READ FROM CONFIGURATION REGISTER,
LD

B.B,#RCONFIG

JSR

,CONFIGURATION REG. READ COMMAND
,LOADED IN THE CNTRL_BUF.
;CALLING SER_RD FOR DATA TRANSFER.

; ........... ." .. ** .. '* ................... ** ......................... * ................. ." ** ...... ." .... ** .......... ** .. ** .... *** ................ ,.
DATA WRITE SUBROUTINE II SER_WR " , FOR SERIAL I/O TRANSFER OF DATA BETWEEN THE
HPC AND THE SERIAL DAS WITH uW SERIAL INTERFACE. BEFORE CALLING THE ROUTINE,
THE DATA TRANSFER CONTROL BYTE SHOULD BE LOADED IN THE CNTRL_BUF AND THE
DATA TO BE WRITTEN TO THE SDAS SHOULD BE LOADED IN THE DATA_BUF.

; ******** ..... ******* *** .. **** ... *** ***** ** ** ...... ** .. ***************************** ..
SER_WR:

WAITI:

RBIT

DAS_CS, PORTB.B

iRESET THE PORT B BIT-X TO SELECT

LD

SIO.B,CNTRL_BUF .B

;THE 8DASl.
,LOAD THE CONTROL BYTE TO HPC's SIO
,REGISTER, BYTE TRANSFER IS STARTED.

IFBIT
JP
JP

uWDONE,IRPD.B
WBYTEl

WBYTE1, LD
WAIT2,

WAITl
Sro.B, (DATA_BUF+ll.B

; WAIT AND CHECK THE uWDONE BIT FOR
,COMPLETION OF DATA TRANSFER. WHEN DONE,
; GO AHEAD FOR FIRST DATA BYTE TRANSFER.

,LOAD HIGH ORDER BYTE OF DATA TO SIO
,REGISTER, TRANSFER IS STARTED.

IFBIT

uWDONE, IRPD. B

iWAIT AND CHECK THE uWDONE BIT FOR

JP
JP

WBYTE2
WAIT2

,COMPLETION OF DATA TRANSFER. WHEN DONE,
,GO AHEAD FOR SECOND DATA BYTE TRANSFER.

WBYTE2, LD

SIO.B,DATA_BUF .B

,LOAD LOW ORDER BYTE OF DATA TO SIO

WAIT3,

IFBIT
JP
JP

uWDONE.IRPD.B

jREGISTER, TRANSFER IS STARTED.
j WAIT AND CHECK THE uWDONE BIT FOR

WDONE
WAIT3

,COMPLETION OF DATA TRANSFER. WHEN DONE,
; DESELECT THE SDAS AND RETURN.

SBIT
RET

DAS_CS, PORTB.B

WDONE,

,SET THE BIT TO DESELECT THE SDAS.
; RETURN FROM SUBROUTINE.

; ••• *. '* * '* ••• '* ••••••••••••••••••••••••••••••• '* .... '* '* '* ••• *. '* '* * •• * ......... *. '*. '*. '* * *
DATA READ SUBROUTINE

II

SER_RD " , FOR SERIAL I/O TRANSFER OF DATA BETWEEN THE

HPC AND THE SERIAL DAS WITH uW SERIAL INTERFACE. BEFORE CALLING THE ROUTINE,
THE DATA TRANSFER CONTROL BYTE SHOULD BE LOADED IN THE CNTRL_ BUF AND THE
DATA IS LOADED IN THE DATA_BUF UPON RETURN FROM SUBROUTINE.

; •• *'** •• *.****.* .'******.**. *** *'*'**'*.********* *'***** *'*** * *** * .**. **'***** .'**. *.
SER_RD:
RBIT

DAS_CS, PORTB.B

LD

SIO.D,CNTRL_BUF .B

IFBIT
JP
JP

uWDONE, IRPD. B

jRESET THE PORT B BIT-X TO SELECT
jTHE SOAS!.
;LOAD THE CONTROL BYTE TO HPC's SIO

; REGISTER, BYTE TRANSFER IS STARTED.
WAIT' .

RBYTEl
WAIT4

RBYTE1, LD

SIO.B,#OxOO

WAITS,

uWDONE, IRPD. B

IFBIT
JP
JP

RBYTE2 : LD
LD

RBYTE2
WAITS
(DATA_BUF+ll.B,SIO.B
SIO.B,#OxOO

; WAIT AND CHECK THE uWDONE BIT FOR
;COMPLETION OF DATA TRANSFER. WHEN DONE.
i GO AHEAD FOR FIRST DATA BYTE TRANSFER.
;LOAD THE SIC REGISTER WITH ZERO,
j THIS IS JUST A DUMMY LOAD TO START

,THE DATA TRANSFER
,WAIT AND CHECK THE uWDONE BIT FOR
,COMPLETION OF DATA TRANSFER. WHEN DONE,
,GO AHEAD FOR SECOND DATA BYTE TRANSFER.
,LOAD
,WITH
,LOAD
,THIS

HIGH ORDER BYTE OF THE DATA_BUF REGISTER
DATA JUST READ FROM SDAS.
THE SIO REGISTER WITH ZERO,
IS JUST A DUMMY LOAD TO START

TLlH/11879-57

1·86

7.0 Digital Interface (Continued)
HPC Assembly Code Example (Continued)
i THE DATA TRANSFER

WAIT6,

IFS!T
JP
JP

uWDONE, I RPD. B
ROONE
WAIT6

; WAIT AND CHECK THE uWDONE BIT FOR

; COMPLETION OF DATA TRANSFER. WHEN DONE,

iLOAD THE READ DATA TO AL, DESELECT THE
j

RDONE:

LD

DATA_BUF. R,SIO. B

sarT

DAS_CS, PORTa. B

RET

SOAS AND RETURN.

iLOAC LOW ORDER BYTE OF THE DATA_BUF REGISTER
;WITH THE DATA JUST READ FROM SDAS.
; SET THE BX TO DESELECT THE SDAS.
; RETURN FROM SUBROUTINE.

; ..... * ... ** .. *.* ............... * .................... * .............. *.* ........... * * .... _.. * ... * ....... * .......... *. *. * fr.
FIFO BURST READ SUBROUTINE "RD_FIFO", USED FOR READING THE CONVERSION RESULTS
FROM FIFO IN BURST READ MODE. DATA IS READ FROM FIFO AND STORED IN THE
SYSTEM MEMORY STARTING FROM THE DATA_BLK ADDRESS.

NUMBER OF CONVERSION

RESULTS BEING READ IS RSLT_NUM WHICH IS LOADED IN THE X REGISTER. IT IS ASSUMED
THAT THE HPC IS USING 16 BIT DATA BUS.

; .................................... * •••••••••••••••••••••••• ,..,. ••••• *.* •• *. **.
RD]IFO,
W

BK.W, #DATA_BLK.

# (DATA_BLK+2.RSLT_NUM~1)
;SET B FOR STARTING ADDRESS OF MEMORY
;AND K FOR ENDING ADDRESS MINUS ONE

LPFlFO:

WAIT7:

LD

X. W, #RSLY_NUM

RBIT

DAS_CS, PORTB.B

LD

SIO.B,#RBFIFO

IFBIT
JP
JP

uNDONE,IRPD.B
MSBYTE
WAIT?

MSBYTE: LD

SIO.B.#oxon

WAITe:

uNDONE,IRPD.B
LSBYTE
WAITe

IFBIT
JP

JP
LSBYTE, LD
LD

; LOAD HIGH ORDER BYTE OF THE A REGISTER
; WITH DATA JUST READ FROM THE SOAS.
,LOAD THE SIO WITH 0, THIS IS JUST A
; DUMMY LOAD TO START THE DATA TRANSFER.

DECSZ

X

WAIT9
DAS_CS,PORTB.a

,DECREMENT X AND SET THE SDAS CHIPiSELECT BIT IF LAST READ CYCLE (X==O).
;OTHERWISE CONTINUE.

JP

uWDONE, IRPD. B
CMPLT
WAIT9

,LOAD THE READ DATA TO AI..

IFBIT
JP

CMPLT:

SIO. B, #Oxoo

; LOAD THE SIO WITH O. THIS IS JUST A
; DUMMY LOAD TO START THE DATA TRANSFER
; WAIT AND CHECK THE uWDONE BIT FOR
,COMPLETION OF DATA TRANSFER. WHEN DONE,
; GO AHEAD FOR SECOND DATA BYTE READ.

JP

salT
WAIT9:

AH.B,SIO.B

; A COUNTER TO KEEP TRACK OF # OF FIFO
; READS FOR TERMINATION OF BURST MODE
;BY PULLING THE CHIP SELECT HIGH DURING
; THE LAST READ CYCLE AND BEFORE THE
i 14TH CLOCK EDGE.
;RESET THE PORT B BIT~X TO SELECT
,THE SOAS.
;LOAD THE BURST FIFO READ CONTROL BYTE
,TO SIO REG. BYTE TRANSFER IS STARTED.
,WAIT AND CHECK THE uNDONE BIT FOR
; COMPLETION OF DATA TRANSFER. WHEN DONE,
,GO AHEAD FOR FIRST DATA BYTE READ.

LD

AL.8,SIO.8

XS

A, [B+J.W

JP

MSBYTE

iWAIT AND CRECK THE uWDONE BIT FOR
;COMPLETION OF DATA TRANSFER. WHEN DONE,

; LOAD LOW ORDER BYTE OF THE A REGISTER
; WITH THE DATA JUST READ FROM THE SDAS.
ISTORE A TO THE DATA_BLK WITH B AUTO~
;INCREMENT AND SKIP IF GREATER THAN K.
,GO FOR THE NEXT FIFO DATA

RET

; •••••••••••• *•••••••• * ....... ** ... * * '* •• * •••••••• * * ••• * * *.* '* ... * * ••• * •• * '** •••• * ...
; THIS ROUTINE INITIALIZES THE SDAS SERIAL INTERFACE IN CASE A
; COMMUNICATION CYCLE IS INTERRUPTED IN THE MIDDLE OF A CYCLE FOR ANY REASON.

1··*························*··········*·....
SBIT

DAS_CS, PORTB.B

** •••• * •• **. **** •• * .**.** .. * ..... *

; DESELECT THE SDAS

TL/H/11879-58

1-87

7.0 Digital Interface (Continued)
HPC Assembly Code Example (Continued)
RWAIT1,

R_NXT2'
RWAIT2,

R_NXT3,
RWAIT3,

LD
IFBIT
JP
JP
LD
IFBIT
JP
JP
LD
IFBIT
RET
JP

SIO.S,tOxoo
uWDONE,IRPD.B
R_NXT2
RWAIT1
SIO.B,#OxOO
uWDONE, IRPD. B
R_NXT3
RWAIT2
BIO.B,tOxOO
uWDONE, I RPD . B

;RESET SEQUENCE FOR THE SDAS INTER; FACE TO' BRING IT OUT OF A HANGUP BY
;APPLYING 24 SERIAL CLOCK PULSE WHILE
;CHIP SELECT IS HIGH, THIS IS EQUAL TO
; POWER UP RESET FOR THE INTERFACE
; FACE TO BRING IT OUT OF A HANGUP
; NOTE THAT THIS ROUTINE DOES NOT RESET
; THE SERIAL DAS BUT ONLY THE SERIAL INTERFACE'
;THIS ROUTINE IS USEFUL DURING
; SOFTWARE DEVELOPMENT OR IN CASE THAT
;A COMMUNICATION CYCLE NEEDS TO BE
; INTERRUPTED BY SYSTEM REQUIREMENTS.

RWAIT3

TL/H/11879-59

68HC11 Assembly Code Example
." *.*. ** ••• .., * ** * ••• *** ***.., '" *••• **..,.., ••••••••• '* **.* ** ** •• '" *.*."." ***." **.* • .". *." ••••
• THE 68HC11 MICROCONTROLLERS FAMILY ASSEMBLY SUBROUTINES FOR INTERFACE TO
• THE LM12434 AND LM12{L}438 SERIAL DATA ACQUISITION SYSTEM (SOAS) CHIP •
." ••••••• **." • .., *** • ." •••• * ...... * '" '" **.*. ** ••••••• * •••••• *." ••• ."." *** ... **** ... .".., * •• * **

*.

••••• ** •••••• -.** •• ***** •• * •••• * •••••••••••• * ••••••••••••••••••• ** ••••••••••••
• 68HCll CONTROLLER REGISTER'S ADDRESSES SYMBOLIC DEFINITIONS, USED IN
• INTERFACE ROUTINES

•••••••• ** ••••• * ••••• **.** ••••••••••• **.** ••••••••••••••••••• * •••••••••••••• *

PORTO

EQU

DDRD
SPCR

EQU
EQU

$1009
$1028

SPSR

EQU

$1029

SPDR

EQU

$102A

$1008

Port D data register

-

,
,ss* ,sex ,MOSI,MISO,TxD ,RxO n
PORT D 'SS' BIT IS USED FOR BOAS CHIP SELECT
I Port D data direction
; BPI control register
I "SPIE,SPE ,DWOM,MSTR;CPOL, CPHA, SPR1,SPRO·
I SPI status register
,MODF , ,
"SPIF, WOOL,
1 SPI data register; Read-Buffer; Write-Shifter

-

-.

****.**.***.**.***********************.*** ••••• ******* ••.**.***.**.**.* •••• ***
• SERIAL OAS RELATED REGISTERS, CONSTANTS AND MEMORY BLOCKS BASE ADDRESSES
• SYMBOLIC DEFINITIONS

** *** •• **.* *** ** * ** * *** ** * ***.* ** ****. **** ... ***. * ** •• * .****. ** *. *.*.* * ••••• *.
RINSTRO
WINSTRO
RINSTR1
WINSTR1
RINSTR2
WINSTR2
RINSTR3
WINSTR3
RINSTR4
WINSTR4
RINSTR5
WINSTRS
RINSTR6
WINSTR6
RINSTR7
WINSTR7

EQU
EQU
EOU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EOU
EQU
EOU
EQU
EOU
EQU

RCONFIG
WCONFIG
RINTER
WINTER
RINTSTAT
RTlMER
WTIMER
RSPIFC
RBFIFC
RlIITSTAT

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

$C2
$82
$C6
$86

$CA

I SERIAL DAS INSTRUCTION RAM AND LIMITS 1 I< 2
,READ AND. WRITE CONTROL BYTES. THESE BYTES
,CONTAIN ADDRBSSES OF THB SDAS REGISTER, THE
I READ/WRITE BIT AND THE MBB/LSB BIT.
I PREDEFINED.

$8A
$CE
$88
$D2
$92
$D6
$96
$DA
$9A
$DE
$9E
$E2

$A2
$E6
$A6
$EA
$EB
$AE
$F2
$F3
$F6

.ISDAS
,SOAS
,SOAS
,SOAS
,SOAS
I SOAS
,SOAS
I SOAS
I SOAS
I BOAS

CONFIGURATION REG. READ CONTROL BYTE.
CONFIGURATION REG. WRITE CONTROL BYTE.
INTERRUPT ENABLE REG. READ CONTROL BYTE.
INTERRUPT ENABLE REG. WRITE CONTROL BYTE.
INTERRUPT STATUS REG. READ CONTROL BYTE.
TIMER REG. READ CONTROL BYTE.
TIMER REG. WRITE CONTROL BYTE.
FIFO , SINGLE READ CONTROIl BYTE.
FIFO , BURST READ CONTROL BYTE.
LIMIT STATUS REG. READ CONTROL BYTE.

TL/H/11879-85

1-88

7.0 Digital Interface (Continued)
68HC11 Assembly Code Example (Continued)
DATA_BLK

EQU

$10

DATA_BUF EQU
CNTRL_BUF EQU

$42
$40

RSLT_NUM

$10

EQU

,SYMBOLIC STARTING ADDRESS OF THE DATA BLOCK
,IN SYSTEM MEMORY, USED TO STORE THE
,CONVERSION RESULTS READ FROM FIFO IN BURST
,READ ROUTINE.
,SYMBOLIC ADDRESS FOR A 16 BIT DATA BUFFER
,SYMBOLIC ADDRESS FOR AN 8 BIT BUFFER USED
,IN ROUTINES FOR CONTROL BYTE.
,SYMBOLIC DEFINITION FOR THE NUMBER OF
,RESULTS TO BE READ FROM FIFO IN BURST READ

•• **.**.**.** ••••••••••••••••••••• ** ••••••••••••• ** •••••••••••• ** ••••••••• ***

•
•
•
•

SERIAL DAS READS AND WRITES ARE PERFORMED BY SUBROUTINE SER_IO.
THIS ROUTINE USES THE CNTRL_BUF REGISTER AS CONTROL INPUT AND THE DATA_BUF
REGISTER AS DATA BUFFER, FOR WRITES DATA IS LOADED ON THE DATA_BUF REG. AND
FOR READS DATA RETURNS IN THE DATA_BUF REGISTER .
••••• ** •••••••• * •••••••••••• ** ••••• *** •• * ••••• ** ••• * •• * ••••••••• * ••• * •• *.*.*.
AN EXAMPLE OF A WRITE TO CONFIGURATION REGISTER:
LDAA
STAA
LDD
STD
JSR

#WCONFIG
CNTRL_BUF
#$0010
DATA_BUF
SER_IO

,CONFIGURATION REG. WRITE COMMAND
,LOADED IN THE CNTRL_BUF.
,DATA LOADED ON THE DATA_BUF REG.
,RESET= 1, RAM POINTER=OO.
,CALLING SER_WR FOR DATA TRANSFER.

AN EXAMPLE OF A READ FROM CONFIGURATION REGISTER:
LDAA
STAA
JSR

#RCONFIG
CNTRL_BUF
SER_IO

,CONFIGURATION REG. READ COMMAND
,LOADED IN THE CNTRL_BUF.
,CALLING SER_RD FOR DATA TRANSFER .

•• *.**********.*.****** ••• *********.*****************************.***********

• DATA WRITE/READ SUBROUTINE ·SER_IO", FOR SERIAL I/O TRANSFER OF DATA BETWEEN
• THE 68HC11 AND THE SERIAL DAS WITH SPI SERIAL INTERFACE. BEFORE CALLING THE
• ROUTINE, THE DATA TRANSFER CONTROL BYTE SHOULD BE LOADED IN THE CNTRL_BUF.
• FOR WRITES THE DATA TO BE WRITTEN TO THE SDAS SHOULD BE LOADED IN DATA_BUF.
• FOR READS, DATA IS LOADED INTO THE DATA_BUF UPON RETURN FROM THIS SUBROUTINE .
•• * •• **.***** •••• *****.** •• ** ••••• **.***** ••• * •••••••• *****.*.******** •• **.*.
SER_IO:

SEND1

SEND2

BCLR
LDAA
STAA
LDAA
ANDA
BEQ
LDAA
STAA
LDAA
ANDA

SEND3

BEQ
LDAA
STAA
LDAA
STAA
LDAA
ANDA
BEQ
LDAA
STAA
BSET
RTS

PORTD,Y $20
CNTRL_BUF
SPDR
SPSR
#$80
SEND1
DATA_BUF
SPDR
SPSR
#$80
SEND2
SPDR
DATA_BUF
DATA.J!UF+1
SPDR
SPSR
#$80
SEND3
SPOR
DATA_BUF
PORTD,Y $20

DROP CHIP SELECT
LOAD A WITH CONTROL BYTE
START SPI SEND
GET SPI STATUS TO WAIT FOR SPIF
MASKING THE EIGHTH BIT WITH THE SPIF BIT
IF SPIF=O THEN BRANCH, ELSE SKIP
, GET MSB DATA BYTE AND SEND
START SPI SEND. THIS WILL ALSO CLEAR THE SPIF BIT
GET SPI STATUS TO WAIT FOR SPIF
MASKING THE EIGHTH BIT WITH THE SPIF BIT
, IF SPIF-O THEN BRANCH, ELSE SKIP
LOADS 1 DATA BYTE (MSB/LSB) SENT FROM DAS INTO ACC A
STORE MSB DATA BYTE IN RAM BUFFER
GET LSB DATA BYTE TO SEND
START SPI SEND
GET SPI STATUS TO WAIT FOR SPIF
MASKING THE EIGHTH BIT WITH THE SPIF BIT
IF SPIF-O THEN BRANCH, ELSE SKIP
, LOADS 1 DATA BYTE (MBB/LSB) SENT FROM DAS INTO ACC A
STORE MSB DATA BYTE IN RAM BUFFER
DONE - - RAI SE CS
TUH111878-86

1-89

7.0 Digital Interface (Continued)
68HC11 Assembly Code Example (Continued)

** •• ** ••••••••••••••••••••• ** ••••••••• **** •••• ** •••••••••••• ** ••••••••• *** •••
•
•
•
•
•

FIFO BURST READ SUBROUTINE nRD_FIFon, FOR READING THE CONVERSION RESULTS
FROM FIFO IN BURST READ MODE. DATA IS READ FROM FIFO AND STORED IN THE
SYSTEM MEMORY STARTING FROM THE DATA_BLK ADDRESS. NUMBER OF CONVERSION.
RESULTS BEING READ IS RSLT_NUM WHICH IS LOADED IN THE X REGISTER. IT IS ASSUMED
THAT THE HPC IS USING 16 BIT DATA BUS.
** •••••••••• ** •••••••••••••••• ** •••• **** •• * •••••••••••••••••••••••••••• ** ••••
RD_FIFO:
LOAD X WITH DATA BLOCK BASE ADDRESS
LDX
#DATA_BLK
LOAD B WITH NUMBER OF RESULTS
#RSLT_NUM
LDAB
MAKE INTO BYTE COUNT
LSLB
ONE LESS FOR LAST. BYTE
DECB
DROP CHIP SELECT
PORTD,Y $20
BCLR
LOAD A WITH BURST READ COMMAND
#RBFIFO
LDAA
SPDR
SEND COMMAND
STAA
I GET SPI STATUS TO WAIT FOR SPIF
BURST1 LDAA
SPSR
MASKING THE EIGHTH BIT WITH THE SPIF BIT
ANDA
#$80
IF SPIF-O THEN BRANCH, ELSE SKIP
BEQ
BURST1
BLOOP

BURST2

BURST3

CLRA
STAA
LDAA
ANDA
BEQ
LDAA
STAA
INX
DECB
BNE
BSET
STAA
LDAA
ANDA
BEQ
LDAA
STAA
RTS

SPDR
SPSR
#$80
BURST2
SPDR
O,X

BLOOP
PORTD,Y $20
SPDR
SPSR
#$80
BURST3
SPDR
O,X

I CLEAR DATA BYTE TO SEND
START SPI, RECEIVE A DATA BYTE
GET SPI STATUS TO WAIT FOR SPIF
MASKING THE EIGHTH BIT WITH THE SPIF BIT
I IF SPIF=O THEN BRANCH, ELSE SKIP
I GET THE RECEIVED DATA BYTE
I STORE DATA BYTE
POINT TO NEXT DATA BYTE
COUNTING DOWN # OF BYTES
STILL MORE DATA BYTES TO GET
RAISE CS TO END BURST READ
START SPI, RECEIVE LAST BYTE
GET SPI STATUS TO WAIT FOR SPIF
MASKING THE EIGHTH BIT WITH THE SPIF BIT
IF SPIF-O THEN BRANCH, ELSE SKIP
GET RECEIVED DATA BYTE
STORE DATA BYTE IN RAM BUFFER
TL/H/11879-87

1·90

~----------------------------------------------------------------------'r

i!:
.....

7.0 Digital Interface (Continued)

I\)

.0W
.0-

The command byte has the following format:

:r

7.28051 INTERFACE MODE
The 8051 interface mode is designed to work directly with
the 8051 family of microcontrollers' mode 0 serial interface.
This interface mode is a simple shift register type of serial
data transfer. The serial clock synchronizes the transfer of
data to and from the LM12434 and LM12(LI438. The interface uses 3 lines: a bidirectional data line (RXD), a serial
clock line (TXD) and a chip-select (CS) line. More than one
device can share the data and serial clock lines provided
that ea~h device has its own chip-select line.
The 8051 mode is selected when the MODESEL1 and
MODESEL2 pins have the logic state of "00". Figure 14
shows a typical connection diagram for the 8051 mode serial interface. The ~, RXD and TXD lines are respectively
assigned to interface pins P3 through P5. The P1 and P2
pins are not used in this mode and should be left open or
connected to logic "1". In this interface the idle state of the
serial clock TXD is logic "1". The data is stable at both
edges of the TXD clock and is shifted after its rising edge.
The interface has a bidirectional RXD data line. The
LM12434 and LM12(L1438 leaves the RXD line in a high
impedance state whenever it is not outputting any data.

lr-t:
-----

MODESEL 1
MODESEL2

PI
P2
P3(Cs)

,...--

P4(RXD)

r-

P5(TXD)

Purpose

Parallel Port

}

To other
Peripherals

Data .....

Serial Port { RXD
Mode 0 TXD

Clock --

TL/H/11879-67

FIGURE 14. LM12434 and LM12(L}438In the 8051 Interface Mode
8051 Assembly Code Example
;* ••••• ** •••••••• ****** •••••••• **** •• ***** •• **** •••• ***.*.* •• ***.********** ••

; THE 80Sl. MICROCONTROLLERS FAMILY ASSEMBLY SUBROUTINES FOR INTERFACE TO
; THE LM12434 and LMl.2{L}438, SERIAL INTERFACE DATA ACQUISITION SYSTEM (SOAS) CHIP.
* **** ..... * * ...... * .. * .......... * * * .... *. * ****" .. * * * * .* ... ** .. * * .... *
*. *" * * * *"

*.

I·······

-_._*.

;.** •• ** •••••• ****** •• ****.**** •••••••••••••• ** ••• *** •••••••••••••• _--" •••••••

; 8051 CONTROLLER REGISTER, BITS SYMBOLIC DEFINITIONS, USED IN INTERFACE
; ROUTINES
; ••• **.* * *. *•• *.* .. *.* .. * •••• * .. * •••••• '* •• * ........ *** ** .... **** •• ***. *** * .. *** •• **

*.

BIT
BIT
BIT

R_EN
,SBUF
SOAS_SLCT BIT

,SERIAL PORT CONTROL REGISTER
SCON. 0 ,RECEIVE CYCLE COMPLETE FLAG, BIT #0 OF SCON
SCON.1 . ,SEND CYCLE COMPLETE FLAG, BIT #1 OF SCON
SCON.4 ,RECEIVE CYCLE ENABLE BIT, BIT #4 OF SCON
,SERIAL PORT DATA BUFFER FOR SEND AND RECEIVE
P3 .4
; PIN #4 OF PORT 3 USED FOR THE SDAS CHIP SELECT

, •••••••••• ****** •••• **** •••••• *** ••••• ** •• * •••••• **** ••••••••••• ** •••• * •••• *

; SERIAL DAS RELATED REGISTERS, CONSTANTS AND MEMORY BLOCK BASE ADDRESSES
, SYMBOLIC DEFINITIONS
;* ••••••••••••••••••••••••••••••••••••••• ** •••••••••• ******.*.*.* •• ****.*****

RINSTRO
WINSTRO
RINSTRl.
WINSTRl.
RINSTR2
WINSTR2
RINSTR3
WINSTR3
RINSTR4
WINSTR4
RINSTRS
WINSTRS
RINSTR6
WINSTR6
RINSTR7
WINSTR7

EOO
EQU
EQU
EOO
EQU
EQU
EOO
EQU
EQU
EQU
EQU
EOO
EQU
EQU
EQU
EQU

80H
OOH
81H
01H
82H
02H
83H
03H
84H
04H
8SH
OSH
86H
06H
87H
07H

,SERIAL OAS INSTRUCTION RAM AND LIMITS l. & 2
;READ AND WRITE CONTROL BYTES. THESB BYTES
;CONTAIN ADDRESSES OF THE SDAS REGISTERS, THE
,READ/WRITE BIT AND THE BURST READ BIT
; PREDEFINED.

TL/H/11679-89

1-94

7.0 Digital Interface (Continued)
8051 Assembly Code Example (Continued)
RCONFIG
WCONFIG
RINTEN
WINTEN
RINTSTAT
RTlMER
WTlMER
RSFIFO
RBFIFO
RLMTSTAT

BOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU

BBH
OBH
B9H
D9H
BAH
BBH
DBH
BCH
DCCH
BDH

,SOAS
,SDAS
,SDAS
,SDAS
; SOAS
,SOAS
,SOAS

DATA_BLK

EOU

DXXH

DATA_BUP EOU
CNTRL_BUP EOU

DXXH
DXXH

RSLT_NUM

DXXH

,SYMBOLI C STARTING ADDRESS OF THE DATA BLOCK
, IN SYSTEM MEMORY, USED TO STORE THE
,CONVERSION RESULTS READ FROM FIFO IN BURST
,READ ROUTINE.
,SYMBOLIC ADDRESS FOR A 16 BIT DATA BUFFER
,SYMBOLIC !\DDRESS FOR AN B BIT BUFFER USED
,IN ROUTINES FOR CONTROL BYTE.
,SYMBOLIC DEFINITION FOR THE NUMBER OF
, RESULTS TO BE READ FROM FIFO IN BURST READ

EOU

CONFIGURATION .REG. READ CONTROL BYTE.
CONFIGURATION REG. WRITE CONTROL BYTE.
INTERRUPT ENABLE REG. READ CONTROL BYTE.
INTERRUPT ENABLE REG. WRITE CONTROL BYTE.
INTERRUPT STATUS REG. READ CONTROL BYTE.
TIMER REG. READ CONTROL BYTE.
TIMER REG. WRITE CONTROL BYTE.
18DAS FIFO , SINGLE READ CONTROL BYTE.
,SDAS FIFO, BURST READ CONTROL BYTE.
,SDAS LIMIT STATUS REG. READ CONTROL BYTE.

; ...... ** •• *.* .... * * ...... *.* ..... * •• *** .... * * ••• * .. *** •••••• * •• **** •• *.* •• * * •••• *.* ••
SERIAL DAB READS AND WRITES ARB PERFORMED BY SUBROUTINES SER_WR & SER_RD,
THBSE ROUTINES USE THE "CNTRL_BUFn REGISTER AS CONTROL INPUT AND THE
"DATA_BUP' REGISTER AS DATA BUFFER, FOR WRITES DATA IS LOADED ON THE
1 "DATA_BUFII REGISTER, AND FOR READS DATA RETURNS IN THB "DATA_BOP'n REGISTBR.

; •• *.*.* ........ *.* .. ** *. * *

.*. * ***** •••• *** *** * *** * .. ** **.* ...... * ...... * ••• **.* ••

,--- AN EXAMPLE OF A WRITE TO CONFIGURATION REGISTER:

MOV

CNTRL_BUP, #WCONFIG

, LOAD CNTRL_BUP WITH WRITE CONTROL
iBYTE

, LOAD LOW ORDER BYTE OF DATA TO
;DATA_BUF

,LOAD HIGH ORDER BYTE OF DATA TO
IDATA_BUF

,SER_WR ROUTINE TRANSFERS THE DATA
,--- AN EXAMPLE OF A READ FROM CONFIGURATION REGISTER:

MOV

CNTRL_BUF, #RTIMER

,LOAD CNTRL BUP WITH READ CONTROL
,BYTE
;SER_RD ROUTINE READS THE DATA

TLlH/11B7S-S0

1-95

7.0 Digital Interface (Continued)
8051 Assembly Code Example (Continued)
; *** ******* ** '* .... ** .... ** .... ***** '* ******** ............ ** .... **** ** .*.* .. ** '* '* ** '" *.* ..

--*._.-

DATA WRITE SUBROUTINE "SER_WR", FOR A SERIAL WRITE TO THE DAS. BEFORE CALLING THE
, ROtlTlNE, THE WRITE CONTROL BYTE SHOULD BE LOADED· IN THE "CNTRL_BUF"
I AND TIlE DATA TO BE WRITTEN TO TIlE SDAS SHOULD, BE LOADED IN TIlE ·DATA_BUF".
; ** ***** *** * ** '* **** **** .... *** '* '* ** •• **** •••• '*.* .. '* ..... *.* ••• ",:**" ***. **** .**** •• *
SER_WR,

SENDW.

CLR
CLR
MOV
JNB

SDAS_SLCT
S_DONE
SBOF, CNTRL_BUF
S_DONE, SENDW

,SELECT THE SDAS, CHIP SELECT~a
I CLEAR SEND CYCLE DONE FLAG
, START SENDING THE, WRITE CONTROL BYTE
, WAIT HERE tlNTIL SEND CYCLE COMPLETED

CLR
MOV
JNB

S_DONE
SBOF, DATA_BUF
S_DONE, SENDl

I

SENDl,

MOV
JNB

S_DONE
SBUF, DATA_BOF+l

SEND2.

S_DONE,SEND2

, CLEAR SEND CYCLE, DONE FLAG
,START SENDING HIGH ORDER BYTE OF DATA
; WAIT HERE tlNTIL SEND CYCLE COMPLE'l'En

SETS

SDAS_SLCT

;DESELECT THE s~s, CHIP SBLECT-l

CLR

CLEAR SEND CYCLE DONE FLAG

, START SENDING LOW ORDER BYTE OF DATA
, WAIT HERE tlNTIL SEND CYCLE C,OMPLETED

RET

; *** .... ** '* ***** '* .. *.*.* '* '* .. '* '* *.* .. *** •• ** '* '* '* ....... '* '* ............. '* '* ••• * ....... *. _._.I DATA READ SUBROUTINE ·SBR_RD", FOR A SERl'AL READ, FROM THE DAB. BEFORE CALLING THE
, ROtlTlNE, TIlE READ CONTROL BYTE SHOULD BE LOADED ON THE "CNTRL_BUF"
, AND THE DATA IS LOADED IN THE "DATA BOF' OPON RETtlRN FROM SUBROUTINE.
J

.*. *** '* ••• ** .****. '* .. ** '* *** '* .. ****. *.;... '* *** * * .... *•• * •••••••
*

* ••• *.* ~ * ••'* ••••• *

SBR_RD.

CLR
CLR
MOV
JNB

SDAS_SLCT
S_DONE
SBUF, CIITRL_BUF
S _DONE, SENDR

,SELBCT THE SDAS, CHIP SELECT-a
; CLEAR SEND CYCLE DONE FLA~
, START SENDING THE READ CONTROL BYTE
,WAI~T HERE, tlNTIL SEND CYCLE COMPLE;TED

SETB

R_EN

; ENABLE DATA RECEIVE CYCLES

RCV1.

CLR
JNB
MOV

R_DONE
R_DONE,RCVl
DATA_BUF, SBUF

; START A DATA BYTE RECEIVE CYCLE
,WAIT HERE tlNTIL RECEIVE COMPLETED
,STORE LOW ORDER BYTE, IN DATA_BOF '

CLR
JNB
MOV

R_DONE

RCV2,

DATA_BUF+l,S8UF

,START A DATA BYTE RECEI~ CYCLE
;WAIT HERE tlNTIL RECEIVE COMPLETED
; STORE HIGH ORDBR, BYTE IN DATA_ BOF

SDAS_SLCT
R_EN

,DESELECT ,THE SDAS, CHIP SBLECT=l
; DISABLE 'DATA RECEIVE CYCLES

SENDR.

SETB
CLR
RET

R_DONE,RCV2

Tt/H/I1879-91

1·96

7.0 Digital Interface (Continued)
; 'II • •

* *.* ..... _...... lilt_ * *

*_. __ ._

8051 Assembly Code Example (Continued)
1IIt_1IIt __ • • • • _ • • • • • • • • • • • • • • • • •

* 'II • • • • *"! ••••••••••••• _

, FIFO BURST READ SUBROUTINE uRD_FIFO", FOR READING THE CONVERSION RESULTS
FROM FIFO IN BURST READ MODE. DATA IS READ FROM FIFO AND STORED IN THE
SYSTEM MEMORY STARTING FROM THE lIDATA_BLK" ADDRESS. NUMBER OF CONVERSION
RESULTS BEING READ IS IIRSLT_NUMII. THIS ROUTINE USES THE RO AND R1 REGISTERS.
I IT IS ASSUMED THAT THEY ARE IN THE PRESENT REGISTER BANK.
RO IS THE POINTER TO "DATA_BLK" WHERE THE CONVERSION RESULTS ARE STORED.

Rl IS USED AS A COUNTER TO KEEP TRACK OF THE NUMBER OF RESULTS TO BE READ
FROM FIFO.
i'" "' ........... '" •••

'II."" '" '* '* .. * .......... * .... '* .... * * .. '* '* ...... '* .... '" '* '* .. '* '* '* .... * ... '* ............... '* '* "' .......... '* '* ..

RD]IFO,
MOV
MOV

RO I DATA_BLK
A, #RSLT_NUM

; SETTING DATA BLOCK POINTER
;NUMEER OF RESULTS TO BE READ IN ACC

RL

A

,CALCULATING # OF DATA BYTES TO BE
;READ FROM FIFO, EACH CONVERSION

MOV
DEC

Rl,A
Rl

CLR
CLR
MOV

SDAS_SLCT
S_DONE

.JNB

S _DONE I SENDB

,WAIT HERE UNTIL SEND CYCLE COMPLETED

SETB

R_EN

,ENABLE DATA RECEIVE CYCLES

CLR
JNB
MOV
INC
DJNZ

R_DONE

i START A DATA BYTE RECEIVE CYCLE

R_DONE, RCVB
@RO,SBUF

i WAIT HERE UNTIL RECEIVE COMPLETED
iSTORE DATA BYTES IN DATA_BLK

RO
Rl,RD_LP

,POINTING TO NEXT DATA LOCATION
,READ NEXT BYTE IF NOT THE LAST ONE

; RESULTS IS 2 BYTES

SBUF, #RBFIFO

,NUMBER OF DATA BYTES TO R1 COUNTER
; TOTAL DATA BYTES MINUS 1 IN COUNTER
i SELECT THE SDAS,

CHIP SELECT-O

; CLEAR SEND CYCLE DONE FLAG

,START SENDING TIlE FIFO BURST READ
1 CONTROL BYTE

SENDB,

RD_LP,
RCVB,

SETB

SDAS_SLCT

,DESELECT THE SDAS, BEFOR READING
BURST READ TERMINATION

i THE LAST BYTE,

RCVL:

CLR

R_DONE

; START A DATA BYTE RECEIVE CYCLE

JNB

R_DONE, RCVL
@RO,SBUF

; STORE THE LAST DATA BYTE

R_EN

;DISABLE DATA RECEIVE CYCLES

MOV
CLR
RET

,WAIT HERE UNTIL RECEIVE COMPLETED

; •••••••• * ••• * ••• * ••••• * •••••• * .*** *.* •• ** ***** ••••••• * ••• * •• * •••••••••••••••
,
,
,
,
,
,

THIS ROUTINE INITIALIZES THE SDAS SERIAL INTERFACE IN CASE THAT A
COMMUNICATION CYCLE HAS BEEN INTERRUPTED. TIllS ROUTINE APPLYS 24
SERIAL CLOCK PlJLSES TO THE DAS WHILE ITS ·CHIP SELECT
IS HIGH. THIS ROUTINE CAN BE USED AT THE START OF THE PROGRAM DURING CODE
DEVELOPMENT OR ANYWHERE THAT A READ OR WRITE CYCLE M11ST BE INTERRUPTED
BECAUSE OF THE SYSTEM REQUIREMENT.

1 * •• * •• ** •••••••• * * ***.* *.** .*** * •• *.*.**.*****.*** *. ****** * * •••• *.***.*** •••

SDAS_SER_PORT_RST,
SETB
SDAS_SLCT

TRU,
TRY2,
TRY3,

;DESELECT THE SDAS, CHIP SELECT-l
; ENABLE DATA RECEIVE CYCLES

SETE

R_F;;N

CLR
.JNB
CLR
.JNB
CLR
.JNB

R_DONE

; START A CYCLE, 8 PULSES APPLIED

R_DONE,TRYl

R_DONE
R_DONE, TRY2
R_DONE

;WAIT HERE UNTIL CYCLE COMPLETED
;START'A CYCLE, 8 PULSES APPLIED
,WAIT HERE UNTIL CYCLE COMPLETED
,START A CYCLE, 8 PULSES APPLIED

R_DONE,TRY3

iWAIT HERE UNTIL CYCLE COMPLETED

CLR
RET

R_EN

; DISABLE DATA RECEIVE CYCLES
TL/H/11879-96

1-97

...
---

~~------------------------------------------------I
C")

....I

C'I
....

::IE

....I
....
...

~

C'I
....

::E
....I

7.0 Digital Interface (Continued)
The command packet has the following format:

7.3 TMS320 INTERFACE MODE
The TMS320 interface mode is designed to work directly
with the serial interface port of the TMS320C3x and
TMS320C5x families of digital signal processors. This interface uses five lines: two data lines (DX, DR), two frame.
synchronization signal lines (FSX, FSR), and a serial clock
line (SCLK). Note that the TMS320C3x/5x serial interface
has two separate serial clock lines for transmit and receive
called CLKX and CLKR, but the LM12434 and LM12{L}438
only uses one clock input for both receive and transmit.
Typically, CLKX is specified as an output and drives SCLK .
as well as CLKR (defined as an input). The serial clock for
this interface mode is a free running clock, with the data
stream synchronized by SCLK. The start of each data transfer (the beginning of a data packet) is synchronized by FSX
(Transmit Frame Sync) or FSR (Receive Frame Sync). This'
interface can communicate with one device; no device select signal is used. The following discussion assumes that
the reader has a basic knowledge of the architecture and
operation of the TMS320C3x/5x serial interface port.
The TMS320 interface mode is selected when the
MODESEL1 and MODESEL2 pins have the logic state, of
"11". Figure 16 shows a typical connection diagram for the
LM12434 and LMI2{L}438 in the TMS320 serial interface
mode. The FSR, FSX, DX, DR, and SCLK lines are assigned
. '.
to interface pins PI through P5.

what type of data transfer (communication cycle) is started

-

which device register is to be accessed

Always 0,

OAS Internal Register
Address

{ 0 = Single read or write
1 = Burst read

TLlH/11879-54

The first tiit of the command packet is always the MSB of
the data packet to to be transferred.
Figure '15 shows the timing diagrams for the three communication cycles. Figure 15a shows a write cycle. Figure 15b
shows a read cycle, and Figure 15c shows a burst read
cycle. Note that these timing diagrams depict general relationships between the SCLK edges, the data bits and the
frame synchronization signals (FSX, FSR). These diagrams
are not meant to show guaranteed timing performance.
(See specification tables for parametric switching characteristics.)
.
Write cycle: A write cycle begins with an FSX pulse from
the processor. The first data bit is received by the DAS on
the DX line during the next SCLK falling edge after the failing edge of FSX. A 32-bit data packet 'is written to the DAS.
The TMS320C3x does this with a 32-bit transfer, using its
serial port 32-bit register. With the.TMS320C5x family two
successive 16-bit transfers are initiated without any gap in
between. The first 9 bits (MSBs) of the data are the command packet with the R/W bit and B bit equal to zero. Following the command packet, a 16-bit data stream starts on
the' falling edge of the 10th SCLK cycle and continues
through the 25th cycle. The last 7 bits in the 32-bit data
packet are "don't care" and are ignored by the DAS. The
data is written to the register addressed in, the command
packet (A3, A2, A 1, AO). There is no activity on the FSR and
DR lines during a write cycle. The write cycle is completed
after the last data bit is transferred.

Data transfer in this mode is programmable by the processor for 8-, 16-, 24-, or 32-bit data packets for the
TMS320C3x and 8-, or 16-bit data packets for TMS320C5x.
The LM12434 and LMI2{L}438 uses 16-bit and·32-bit data
packets. For the TMS320C5x the 32-bit packet is composed
of two successive 16-bit packets with no gaps between
them. The data bits in each packet are transferred MSB
first and are shifted in on the rising edge of SCLK and are
stable and captured at the falling edge of the SCLK. As with
the "Standard" and "8051" interface modes, the LM12434
and LM12{L}438 has three different communication cycles:
write cycle, read cycle and burst read cycle. At the start of
each data transfer cycle, a stream of 9 data bits (the "command packet") is written to the LM12434 and LMI2{L}438
and informs it about the communication cycle. The placement of these 9 bits in the data packet is different in the
read and write cycles and is discussed for each case separately. The command packet carries the following information:
-

LSB (9th bit)

MSB (First bit being transferred)

Read cycle: A read cycle also begins with an FSX pulse
from the processor. The read cycle uses 16-bit data transfer. Following the FSX pulse, 16 bits of data are written to
the DAS on the DX line. The first 9 bits (MSBs) of data are
the command packet with the R/W bit equal to one and the
B bit equal to zero. The last 7 bits (LSBs) are "don't care"
and are ignored by the DAS. About3 to 4 CLK (t~ DAS
main clock input, not the SCLI<) cycles after the R/W bit is
received, the DAS generates an FSR pulse to initiate the
data transfer. Following the FSR pulse, the DAS will send
16 bits of data to the processor on the DR line. The first bit
(MSB) of the data appears on the DR line on the next SCLK
cycle following the FSR pulse. The data is read from the
register addressed in the command packet. The read cycle
is completed after the last data bit is transferred.

1-98

r;:

7.0 Digital Interface (Continued)
Burst read cycle: A burst read cycle starts the same way
as a single read cycle, but the B bit in the command packet
is set to one, indicating a burst read cycle. After the first 16
bits of data carrying the command packet is written to the
DAS, the DAS begins to send out the data words from the
addressed register on the DR line repeatedly. Each data
word is preceded by an FSR pulse for synchronization. To
terminate a burst read cycle, the processor does a dummy
read from the configuration register during the last

data word. This dummy read should be started so that its
FSR pulse occurs during the 15th to 17th SCLK cycle of the
last data word as shown in Figure 15c. The dummy read
terminates the burst read cycle and shifts out the contents
of the configuration register on the DR line. This data can be
discarded. After transfer of the last data bit from the config.
uration register, the DAS is ready for a new communication
cycle to begin.

10

SCLK [

....
N
"'W"

"'"

r;:

....
N

r-

32

2S

Seriel ClOCk]
to CAS

I

FSX [rx frame sync]

:n:

-----J

taDAS

I~I----------------~----------------------------~------------~--------__

"0" for write

FSR [RX Frame sync]
From CAS

--------------------------------------------------------------------------------High Impedance

DR [ Serial Data ]
From OAS

TL/H/11879-47

(a) Write Cycle
16

SCLK [

Serial ClOck]

to

CAS

FSX [TX Frame sync]

to~S

:n:

-----J

OX [ Serial Data ]
I. DAS

I

II

,16

I

:::

I~,---------------+---------+-+,-+--------------------------~--------------,,

.JJJ.JJJ.JJJJ.J
<:

0>

SOT-23
2

+

.=-;~

l

Ne

1

r-

3
~lM4040-4.1

1 2 3 4 5 6 7 8

I[
Analog Inputs
TL/H/11879-83

FIGURE 21. General Schematic of the DAS Operating In Standard Interface Mode

1·113

II

CD

~

~
....

r-----------------------------------------------------------------------------,
f}1National Semiconductor

::E
..;.I

m
• LM 12454/LM 12H454/LM 12458/LM 12H458 12-Bit +
.... Sign Data Acquisition System with Self-Calibration
C'\I

:=!l General Description

:;:
an

•C'\I
::c
....

:=!l
~

an
~

....
:=!l

The LMI2454,.LMI2H454, LM12458, and LM12H458 are
highly integrated Data Acquisition Systems. Operating on
just 5V, they combine a fully-differential self-calibrating (correcting linearity and zero errors) 13-bit (12-bil + sign) analog-Io-digital converter (ADC) and sample-and-hold (S/H)
with extensive analog functions and digital functionality. Up
to 32 consecutive conversions, using two's complement format, can be stored in an internal 32-word (16-bit wide) FIFO
data buffer. An internal 8-word RAM can store the conversion sequence for up to eight acquisitions through the
LMI2(H)458's eight-input multiplexer. The LMI2(H)454 has
a four-channel multiplexer, a differential multiplexer output,
and a differential S/H input. The LMI2(H)454 and
LMI2(H)458 can also operate with 8-bit + sign resolution
and in a supervisory "watchdog" mode that compares an
input signal against two programmable limits. ,
Programmable acquisition times and conversion rates are
possible through the use of internal clock-driven timers. The
reference voltage input can be externally generated for absolute or ratiometric operation or can be derived using the
internal 2.5V bandgap reference.
All registers, RAM, and FIFO are directly addressable
through the high speed microprocessor interface to either
an 8-bit or 16-bit databus. The LMI2(H)454 and
LMI2(H)458 include a direct memory access (DMA) interface for high-speed conversion data transfer.
An evaluatlon/lnterface board Is available. Order number LMI2458EVAL.
Additional applications information can be found in applications note AN-906.

Key Specifications (felK =
• Resolution
• 13-bit conversion time

5 MHz; 8 MHz, H)
12-bit + sign or 8-bit + sign
8.8 jLs, 5.5 jLS (H) (max)

• 9-bit conversion time
• 13-bit Through-put rate
• Comparison time
("watchdog" mode)
.ILE
•
•
•
•

VIN range
Power dissipation
Stand-by mode
Single supply

4.2 jLs, 2.6 jLs (H) (max)
88k samples/s (min)
140k samples/s (H) (min)
2.2 jLs (max)
1.4 jLs (H) (max)
±1 LSB (max)
GND to VA+
30 mW, 34 mW (H) (max)
50 jLW (typ)
3V to 5.5V

Features
• Three operating modes: '12-bit + sign, 8-bit + sign,
and "watchdog"
• Single-ended or differential Inputs
• Built-in Sample-and-Hold and 2.5V bandgap reference
• Instruction RAM and event sequencer
• 8-channel (LMI2(H)458), 4-channel (LMI2(H)454)
multiplexer
• 32-word conversion FIFO
• Programmable acquisition times and conversion rates
• Self-calibration and diagnostic mode
• 8- or 16-bit wide databus microprocessor or DSP
Interface

Applications
•
•
•
•
•

Data Logging
Instrumentation
Process Control
Energy Management
Inertial Guidance

Ordering Information
Guaranteed
Clock Freq (min)

Guaranteed
Unearlty Error (max)

Order
Part Number

SeeNS
Package Number

8MHz

±1.0LSB

LM12H454CIV
LM12H458CIV
LM12H458CIVF
LM12H458MELl883
or 5962-9319502MYA
LM12H458MW/883 or
5962-9319502MXA

V44A
V44A
VGZ44A
EL44A

LM12454CIV
LM12458CIV
LM12458CIVF
LM12458MELl8B3
or 5962-9319501 MYA
LM12458MW/883 or
5962-9319501MXA

V44A
V44A
VGZ44A
EL44A

5MHz

±1.0 LSB

1-114

WA44A

WA44A

,-----------------------------------------------------------------------------, !:
~

....

Connection Diagrams

~

en

~
~
!:

"+7
!: !:

i?;

~ S

....

§ + ~ ~
;4>ta>~>!a~~
I

Q

g

I\)

::z:

AU!
A-

.....
~

D5

IN5(MUXOUT+)'

D6

IN4(MUXOUT-)'

!:

D7

IN3

I\)

DB

IN2

en

LM12458
U112H458
(LM12454)
(LM12H454)

D9
VD,
DID
Dll

A-

~
~
!:

INI
INO

....

GND

iiii'

D13

BW

D14

SYNC

Ii I;

I~ ~

d

~ ~ ~ ~

I\)

::z:
A-

DMARQ

D12

~

....

g:

:

TLlH/I1264-2

'Pin names in () apply to the LM12454 and LM12H454.

Order Number LM12454CIV, LM12H454CIV, LM12458CIVor LM12H458CIV
See NS Package Number V44A
Order Number LM12458MEL/883 or 5962·9319501MYA,
LM12H458MEL/883 or 5962·9319502MYA,
LM12458MW/883 or 5962·9319501MXA,
LM12H458MW/883 or 5962·9319502MXA
See NS Package Number EL44A or WA44A

.....

..,

N

..-

0

Q

C

Q

CI

Q

DS

INS

D6

IN4

D7

IN3

DB

IN2

D9

INI

VD'
DID

LM12458
LM12H458

•

INO
GND

Dll

DMARQ

D12

iiii'

D13

BW

D14

SYNC

TLlH/I1264-34

Order Number LM12458CIVF or LM12H458CIVF
See NS Package Number VGZ44A

1·115

Functional Diagrams

LM12(H}454
S/H IN+ - - - - - - - - - - - - ,
S/H IN- - - - - - - - - - . . . ,
MUXOUT+
MUXOUT-

+---------..,
+---------,

FULLY-OIFFERENTIAL, SELF-CALIBRATING
12-BIT + SIGN
ANALOG-TO-OIGITAL CONVERTER

'1

SYNC+---------------~

~

GNO

!! !

CLK---------------'------+-~--~

iNT
OMARQ

SELECT & CONTROL LOGIC

F1II

DO 01 02 03 D4
(LSB)

os

06 07 DB' 09 010011 012013014015
(MSB)

·f f f f f

ffff

Cs ifo WR

AO AI A2 A3 A4

I

ALE

TL/H/11264-1

LM12(H}458
INa
INI
IN2
IN3
IN4
INS
IN6
IN7

12.5V BANDGAP REFERENCE

J----.

VREFOUT

'1

SYNC+----------------~

~

GNO

! ! !

CLK---------------4~-----;-~--_,

INT
OMARQ

I

SELECT & CONTROL LOGIC

F1II

00 01 02 D3 D4
(LSB)

os

06 07 DB D9 010 011 012 013 014 015
(IISB)

fffff

AO AI A2 A3 A4

ffff

Cs ifo WR

ALE

TL/H/11264-21

1-116

Absolute Maximum Ratings (Notes 1 & 2)
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VA + and Vo +)
Voltage at Input and Output Pins
except INO-IN3 (LM12(H)454)
and INO-IN7 (LM12(H)458)

6.0V

Operating Ratings

(Notes 1 &2)
Temperature Range
(Tmin';: TA ,;: Tmaxl
-40·C';: TA';: 85·C
LM12(H)454CIVILM12(H)458CIV
-55·C';: TA ,;: 125·C
LM12(H)458MEL(MW)/883

-0.3VtoV+ + 0.3V

Voltage at Analog Inputs INO-IN3 (LM12(H)454)
and INO-IN7 (LM12(H)458)
GND - 5VtoV+ + 5V

Power Dissipation (TA
V Package (Note 4)

=

Supply Voltage
VA+,VO+

300mV
±5mA
±20mA

IVA+ - vo+1
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
25·C)

875mW
-65·Cto + 150·C

Storage Temperature
Lead Temperature
V Package, Infrared, 15 sec.
EL and W Packages, Solder, 10 sec.
ESD Susceptibility (Note 5)
LM12{H)458MEL{MW)/883

3.0Vto 5.5V
,;:100 mV

IVA+ -vo+1

+300·C
+ 250·C

VIN + Input Range
VIN - Input Range
VREF+ Input Voltage

GND,;: VIN+ ,;: VA+
GND,;: VIN-';: VA+

VREF-lnputVoltage

OV,;: VREF- ,;: VREF+ - 1V
1V ~ VREF';: VA+

1V,;: VREF+ ,;: VA+

VREF+ - VREFVREF Common Mode
Range (Note 16)

1.5kV
2.0kV

0.1 VA + ,;: VREFCM ,;: 0.6 VA +

Converter Characteristics

The following specifications apply to the LM12454, LM12H454, LM12458, and LM12H458 for VA + = Vo+ = 5V, VREF+ =
5V, VREF- = OV, 12-bit + sign conversion mode, fCLK = 8.0 MHz (LM12H454/8) or fCLK = 5.0 MHz (LM12454/8), Rs =
250, source impedance for VREF+ and VREF- ,;: 250, fully-differential input with fixed 2.5V common-mode voltage, and
minimum acquisition time unless otherwise specified. Boldface limits apply for TA = T .. = TMIN to TMAX; all other limits
TA = TJ = 25·C. (Notes 6, 7, 8, 9 and 19)
Symbol

Parameter

Conditions

Typical
. (Note 10)

Limits
(Note 11)

Unit
(Limit)

±1

LSB (max)

ILE

Positive and Negative Integral
Linearity Error

After Auto-Cal (Notes 12, 17)

rUE

Total Unadjusted Error

After Auto-Cal (Note 12)

Resolution with No Missing Codes

After Auto-Cal (Note 12)

13

Bits (max)

Differential Non-Linearity

After Auto-Cal

±%

LSB (max)

Zero Error

After Auto-Cal (Notes 13, 17)
LM12H454
LM12H458

±1/2

±1
±1.5
±1.5

LSB{max)

Positive Full-Scale Error

After Auto-Cal (Notes 12, 17)
LM12{H)458MELlMW

±1/2

±2
±2.5

LSB (max)

Negative Full-Scale Error

After Auto-Cal (Notes 12, 17)
LM12{H)458MELlMW

±1/2

±2
±2.5

LSB (max)

±2

±3.5

LSB{max)

±1/2

LSB{max)

±3/4

LSB (max)

8·Bit + Sign and "Watchdog" Mode
Resolution with No Missing Codes

9

Bits (max)

8-Bit + Sign and "Watchdog" Mode
Differential Non-Linearity

±3/4

LSB (max)

±1/2

LSB{max)

±1/2

LSB{max)

DNL

ILE

TUE

DNL

DC Common Mode Error

(Note 14)

8-Bit + Sign and "Watchdog"
Mode Positive and Negative
Integral Linearity Error

(Note 12)

8-Bit + Sign and "Watchdog" Mode
Total Unadjusted Error

After Auto-Zero

8·Bit + Sign and "Watchdog" Mode
Zero Error

After Auto-Zero

B-Bit + SllIn and "Watchdog" Positive
and Negative Full·Scale Error

1-117

±1/2

±1

±1/2

LSB

•

Converter Characteristics
The following specifications apply to the LM12454, LM12H454, LM12458, and LM12H458 for VA + = Vo+ = 5V,
VREF+ = 5V, VREF- = OV, 12-bit + sign conversion mode, fClK = 8.0 MHz (LM12H454/8) or fClK = 5.0 MHz
(LM12454/8), Rs = 250, source impedance for VREF+ and VREF- S;.250, fully-differential input with fixed 2.5V commonmode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = T.IN to
T.AX; all other limits TA = TJ = 25D C. (Notes 6,7,8,9 and 19) (Continued)
Symbol

Parameter

Typical
(Note 10)

Conditions

Limits
(Note 11)

8-Bit + Sign and "Watchdog" Mode
DC Common Mode Error

±1/8

LSB

Multiplexer Channel-to-Channel
Matching

±0.05

LSB

GND

Non-Inverting Input Range

VIN+

Unit
(Limit)

V (min)
V (max)

VA+

GND
VA+

V (min)
V (max)

-VA+
VA+

V (min)
V (max)

GND

V (min)
V (max)

Inverting Input Range

VINVIN+ - VIN-

Differential Input Voltage Range

VIN+ - VIN2

Common Mode Input Voltage Range

PSS

Power Supply
Sensitivity
(Note 15)

VA+
Zero Error
Full-Scale Error
Linearity Error

VA+ = Vo+ = 5V ±10%
VREF+ = 4.5V, VREF- = GND

±0.2
±0.4
±0.2

±1.75
±2

LSB(max)
LSB(max)
LSB

CREF

VREF + IVREF - Input Capacitance

85

pF

CIN

Selected Multiplexer Channel Input
Capacitance

75

pF

Converter AC Characteristics
The following specifications apply to the LM12454, LM12H454, LM12458, and LM12H458 for VA + = Vo+ = 5V,
VREF+ = 5V, VREF- = OV, 12-bit + sign conversion mode, fClK = 8.0 MHz (LM12H454/8) or fClK = 5.0 MHz
(LM12454/8), Rs = 250, source impedance for VREF+ and VREF- S; 250, fully-differential input with fixed 2.5V common. mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = T.IN to
T.AX; all other limits TA = TJ = 25DC. (Notes 6,7,8,9 and 19)
Symbol

Parameter

Conditions

Clock Duty Cycle

tc

tA

Conversion Time

Acquisition Time

Typical
(Note 10)

Limits
(Note 11)

Unit
(Limit)

40
80

%
% (min)
% (max)

50

13-Bit Resolution,
Sequencer State S5 (Figure 11)

44 (telK)

44 (tcLK)

+ 50 ns

(max)

9-Bit Resolution,
Sequencer State S5 (Figure 11)

21 (tClK)

21 (tcLK)

+ 50 ns

(max)

Sequencer State 87 (Figure 11)
Built-in minimum for 13-Bits

9 (tClK>

9 (tCLK)

+ 50 ns

(max)

Built-in minimum for 9-Bits and
"Watchdog" mode

2 (telK>

2 (tCLK)

+ 50 ns

(max)

76 (telK>

78 (tCLK>

+ 50 ns
+ 50 ns

tz

Auto-Zero Time

Sequencer State S2 (Agure 11)

teAL

Full Calibration Time

Sequencer State S2 (Figure 11) 4944 (telK> 4944 (tCLK)

(max)

88

kHz
(min)

Throughput Rate
(Note 18)
two

LM12H454, LM12H458

"Watchdog" Mode Comparison Time Sequencer States S6, 84,
and S5 (Figure 11)

1-118

89
142
11 (teLK>

140
11 (tcLK>

+ 80 ns

(max)

(max)

Converter AC Characteristics
The following specifications apply to the LM12454, LM12H454, LM1245B, and LM12H45B for VA+ = Vo+ = 5V,
VREF+ = 5V, VREF- = OV, 12-bit + sign conversion mode, fCLK == 5.0 MHz, Rs = 25!l, source impedance for VREF+ and
VREF - ,,; 25!l, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless otherwise
specified. Boldface limits apply for TA = TJ = TMIN to TMAX; ali other limits TA = TJ = 25°C. (Notes 6,7, B, 9 and 19)
(Continued)
Symbol
DSNR

SESNR

DSINAD

SESINAD

DTHD

SETHD

DENOB

SEENOB

DSFDR

Parameter

Conditions

Typical
(Note 10)

Limits
(Note 11)

Unit
(Limii)

VIN = ±5V
fiN = 1 kHz
fiN = 20 kHz
fiN = 40kHz

77.5
75.2
74.7

dB
dB
dB

VIN = 5Vp_p
fiN = 1 kHz
fiN = 20kHz
fiN = 40kHz

69.8
69.2
66.6

dB
dB
dB

VIN = ±5V
fiN = 1 kHz
fiN = 20 kHz
fiN = 40 kHz

76.9
73.9
70.7

dB
dB
dB

VIN = 5Vp_p
fiN = 1 kHz
fiN = 20 kHz
fiN = 40 kHz

69.4
68.3
65.7

dB
dB
dB

Differential Total Harmonic
Distortion

VIN = ±5V
fiN = 1 kHz
fiN = 20 kHz
fiN = 40kHz

-B5.8
-79.9
-72.9

dB
dB
dB

Single-Ended Total Harmonic
Distortion

VIN = 5Vp•p
fiN = 1 kHz
fiN = 20kHz
fiN = 40 kHz

-80.3
-75.6
-72.8

dB
dB
dB

Differential Effective Number of Bits

VIN = ±5V
fiN = 1 kHz
fiN = 20kHz
fiN = 40kHz

12.6
12.2
12.1

Bits
Bits
Bils

VIN = 5Vp•p
fiN = 1 kHz
fiN = 20 kHz
fiN = 40 kHz

11.3
11.2 ,
10.8

Bits
Bils
Bits

Differential Spurious Free Dynamic
Range

VIN = ±5V
fiN = 1 kHz
fiN = 20 kHz
fiN = 40 kHz

87.2
78.9
72.8

dB
dB
dB

Multiplexer Channel-Io-Channel
Crosstalk

VIN = 5Vpp
fiN = 40kHz
LM12(H)454 MUXOUT Only
LM12(H)45B MUX
plus Converter

-76

dB

:-7B

dB

Differential Signal~to-Noise Ratio

Single-Ended Signal-to-Noise Ratio

Differential Signal-to-Noise
Distortion Ratio

+

Single-Ended Signal-to-Noise
Distortion Ratio

+

Single-Ended Effective Number of Bits

tpu

Power-Up Time

10

ms

twu

Wake-Up Time

10

ms

,
1·119

•

DC Characteristics The following specifications apply to the LM12454, LM12H454, LM1245B, and LM12H45B for
VA + = Vo+ = 5V, VREF+ = 5V, VREF- = OV, fClK = B.O MHz (LM12H454/B) or fClK = 5.0 MHz (LM12454/B), and
minimum acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TIlIN to TIIAX; all other limits
TA = TJ = 25°C. (Notes 6, 7, B, and 19)
Symbol
10+

IA+

1ST

Limits
(Note 11)

Unl,.
(Limit)

0.55
'0.55

1.0
1.2

mA(max)

"1"
LM12454/B
LM12H454/B

3.1
3.1

5.0
5.5

mA(max)

Power·Down Mode Selected
Clock Stopped
B MHz Clock

10
40

Conditions

Vo + Supply Current

cs= "1"
LM12454/B
LM12H454/B

Stand·By Supply Current (10 +

I ...

CS =

VA + Supply Current

+ IA +)

Multiplexer ON·Channel Leakage Current

Multiplexer OFF·Channel Leakage Current

RON

Typical
(Note 10)

Parameter

Multiplexer ON·Resistance

VA+ = 5.5V
ON·Channel = 5.5V
OFF·Channel = OV
LM12(H)45BMELlMW
ON·Channel = OV
OFF·Channel = 5.5V
LM12(H)45BMELlMW

0.3
0.1

/LA (max)
0.5
0.3

0.1

/LA (max)
0.5

VA+ = 5.5V'
ON·Channel = 5.5V
OFF·Channel = OV
LM12(H)45BMEL/MW
ON·Channel = OV
OFF·Channel = 5.5V
LM12(H)45BMEL/MW

0.3
0.1

p.A(max)
0.5
0.3

0.1

/LA (max)
0.5'

LM12(H)454
BOO
B50
760

1500
1500
1500

O(max)
O(max)
O(max)

±1.0%
±1.0%
. ±1.0%

±3.0%
±3.0%
±,.O%

(max)
. (max)
(max)

V'N = 5V
V'N = 2.5V
V'N = OV
Multiplexer Channel·to·Channel
RON matching

/LA (max)
/LA (max)

LM12(H)454
V'N = 5V
V'N = 2.5V
V'N = OV

Internal Reference Characteristics The following specifications apply to the LM12454, LM12H454,
LM1245B, and LM12H45B for VA + = Vo+ = 5V unless otherwise specified. Boldface limits apply tor TA = TJ = TIlIN
to TIIAX; all other limits TA = TJ = 25°C. (Notes 6, 7, and 19)
Symbol
VREFOUT

Parameter

typical
(Note 10)

Conditions

Intemal Reference Output Voltage

2.5

LM12(H)45BMELlMW
aVREF/aT

Intemal Reference Temperature
Coefficient

aREF/all

Internal Reference Load Regulation

Sourcing (0 < Il ,;: + 4 mAl
Sinking (-1 ,;: I'l < 0 mAl

aVREF

Line Regulation

4.5V';: VA+ ,;: 5.5V
VREFOUT = OV

Isc

Internal Reference Short Circuit Current

aVREF/at

Long Term Stability

tsu

Internal Reference Start·Up Time

Limits
(Note 11)

Unit
(Limit)

2.5 ±4%
·2.5±6%

v (max)
ppml"C

40

VA+ =Vo+ =OV Cl = 100/LF
1·120

3
13

5V

.;

0.2
1.2

%/mA(max)
%/mA(max)

20

mV(max)

25

. mA(max)

200

ppm/kHr

10

ms

r-

Digital Characteristics The following specifications apply to the LM12454, LM12H454, LM12458, and LM12H458
for VA + = Vo + = 5V, unless otherwise specified. Boldface limits apply for T A
TA = TJ = 25°C. (Notes 6,7,8, and 19)
Symbol

Parameter

Conditions

=
=

=
=

1.0
2.0

p.A(max)

-0.005

-1.0
-2.0

p.A(max)

Logical "1" Input Current

VIN = 5V
LM12(H)458MELlMW

IIN(O)

Logical "0" Input Current

VIN = OV
LM12(H)458MELlMW

VOUT(O)

Logical "0" Output Voltage

lOUT

TRI-STATE® Output Leakage Current

6

=
=
=
VA+ =
lOUT =

VA+
lOUT
lOUT

VOUT
VOUT

Vo+ = 4.5V
-360 p.A
-10 p.A
Vo+ = 4.5V
1.6 mA

= OV
= 5V

-0.01
0.01

~

~
r-

s:::
.....

N

0.005

IIN(l)

Logical "1 " Output Voltage

Unit
(Limit)

V (max)

VA+

VOUT(l)

Limits
(Note 11)

0.8

Logical "0" Input Voltage

s:::
.....

N

U1

4.5V

VIN(O)

00-015 Input Capacitance

Typical
(Note 10)

TMIN to TMAX; all other limits

V (min)

VA+

CIN

=

2.0

Logical "1" Input Voliage

Vo+

TJ

5.5V

VIN(l)

Vo+

=

pF

2.4
4.25

V (min)
V (min)

0.4

V (max)

-3.0
3.0

p.A(max)
",A (max)

::J:
~
(,,"1

~
r-

s:::
.....
N
~

U1

co

"r-s:::
.....
N

::J:
~

U1

co

Digital Timing Characteristics
The following specifications apply to the LM12454, LM12H454, LM12458, and LM12H458 for VA+ = Vo+ = 5V, tr = tf =
3 ns, and CL = 100 pF on data 110, INTand OMARQ lines unless otherwise specified. Boldface limits apply forTA = TJ
= TIlIN to TIIAX; all other limits TA = TJ = 25°C. (Notes 6, 7, 8, and 19)
Symbol
(See Figures
8a, 8b, and 8e)

Limits
(Note 11)

Unit
(Limit)

40

ns (min)

20

ns (min)

ALE Pulse Width

45

ns(min)

Parameter

1,3

CS or Address Valid to ALE Low
Set-UpTime

2,4

CS or Address Valid to ALE Low

Conditions

Typical
(Note 10)

Hold Time
5
6

RO High to Next ALE High

35

ns(min)

7

ALE Low to RO Low

20

ns(min)

8

RD Pulse Width

100

ns(min)

9

RD High to Next RD or WR Low

100

ns(min)

10

ALE Low to WR Low

20

ns(min)

11

WR Pulse Width

60

ns(min)

12

WR High to Next ALE High

75

ns(min)

13

WR High to Next RD or WR Low

140

ns (min)

14

Data Valid to WR High Set-Up Time

40

ns(min)

15

Data Valid to WR High Hold Time

30

ns(min)

16

FfI5 Low to Data Bus Out of TRI-STATE

40

10
70

ns(min)
ns(max)

17

RD High to TRI-STATE

30

10
110

ns(min)
ns(max)

18

AD Low to Data Valid (Access Time)

30

10
80

ns (min)
ns(max)

RL

1-121

=

1 kn

III

co
&I)

....:::E:
....
"I

::Ii

....I
.....
co

r------------------------------------------------------------------------------------------,
Digital Timing Characteristics

The following specifications apply to the LM12454, LM12H454, LM12458, and LM12H458 for VA + = Vc + = 5V, tr = tf =
3 ns, and CL = 100 pF on data 110, Tiiii and DMARQ lines unless otherwise specified. Boldface limit. apply 'or TA = T"
= TMIN to TMAX; all other limits TA = TJ = 25°C. (Notes 6,7,8, and 19) (Continued)

....

Symbol
(See Figures
88, Bb, and Be)

....I

20

Address Valid or CS Low to m5 Low

....
:::E:
....
::E

21

Address Valid or CS Low to WR Low

19

Address Invalid
from RD or WR High

~

"I

::Ii

~
&I)

,

"I

Conditions

Parameter

Typical

Limits

Unit

(Note 10)

(Note 11)

(Umlt)

22

INT High from RD Low

30

23

DMARQ Low from RD Low

30

....I

;;;:

....
....
::E
&I)

"I

....I

20
20,

ns(min)

10

ns(min)

10
80
10
80 '

ns (min)
ns(max)

ns(min)

ns (min)
ns(max)

Nole 1: Absolute Maximum Ratings Indicate limits beyond which damage to the device may occur. Operating Ratings Indicate condition. for which the device Is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Nole 2: All voltages are measured with respect to GND, unless otherwise specified.
Nole 3: When the Input voltage (VIN) at any pin exceeds the power supply rail. (VIN < GND or VIN > (VA+ orVo+», the current at that pin should be IIm"ed 10
5 mAo The 20 mA maximum package input current rating allows the voltage at any four pins, ~h an Input current of 5 mA, to simultaneously exceed the power
supply voltages.
'
Nole 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum juneticn temperature), 0JA (package
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature Is PDm.. = (TJmlX -. TpJ/
€IJA or the number given In the Absolute Maximum Ratings, whichever Is lower. For this device, TJmax = 150'C, and the typical thermal resistance (0JpJ of the
LMI2(H)454 and' LMI2(H)458In the V package, when board mounted, Is 47'C/W, in the W package, when board mounted, is 50'C/W (9Jc '= 5.8"C/W), and In Ihe
EL package, when board mounted, is 70'C/W (9Jc = 3.5"C/W).
Nole 5: Human body model, 100 pF discharged through a 1.5 kn resistor.
Nole 6: Two on·chlp diodes are tied to each analog Input through a series resistor, as shown below. Input voltage magnitude up to 5V abova VA + or 5V below
GND will not damaga tha LMI2(H)454 or the LMI2(H)458. However, arrors in Ihe AID convarsion can occur If thesa diodes are forward biased by more than 100
mY. As an example, If VA + Is 4.5 Voc, lull-scale Input voltage must ba ,,4.6 VOC to ensure accurate conversions.
VA+

r---

I

~ ~ ~?Rb~~~:~AL
~~

1-+-1JVlIv--+
.. ......

:

~----

GND

Nole 7: VA + and Vo+ must be connected together to the same power supply voltage and bypassed
conversion/comparison

TUH/I1264-3
~h

separate capacUors at each V+ pin to assure

~ccuracy.

Nole 8: Accuracy is guaranteed when operating at fClK = 5 MHz lor the LM12454/8 and ICLI( = 8 MHz lor the LMI2H454/8.
Nole 9: With the test condition lor VREF (VREF+ - VREF-) given as +5V, the 12-bit LSB is 1.22 mV and the 8.bitl"Walchdog" LSB is 19.53 mY. ,
Nole 10: Typicals are at TA = 25'C and represent most likely parametric norm.
Nole 11: Limits are guaranteed to National's AOQL (Average Output Quality Level).
Nole 12: Positive integral linearity error Is defined as the deviation 01 the analog value, expressed in LSBs, from the straight line that passes through positive lull·
scale and zero. For negative integral linearitY error the straight line passes through negative lull-scale and zero. (See FIfIU(6S 5b and 5c).
Nole 13: Zero error Is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value 01 the code transitions
between -1 to 0 and 0 to + 1 (see Figure 6).
Nole 14: The DC common·mode error Is measured with both inputs shorted together and driven Irom OV to 5V. The measured value is relerred to the resulting
output value when the inputs are driven with a 2.5V signal.
Nole 15: Power Supply SensHivity is measured aiter Auto·Zero and/or Auto-Calibration cycle has been completed with VA + and Vo + at the spaclfied extremes.
Nole 16: VREFCM (Reference Voltage Common Mode Range) is defined as (VREF+ + VREF-)/2.
Nole 17: The LMI2(H)454/8's seK·calibration technique ensures linearity and offset errors as speCified, but noise inherent In the self-calibration process will result
in a repeatability uncertainty Of ± 0.1 0 LSB.
Nole 18: The Throughput Rate Is for a single Instrueticn repeated continuously. Sequencer states 0 (1 clock CYcle), 1 (1 clock cycle), 7 (9 clock cycles) and 5 (44
, clock cycles) are used (see Figure 11). One additional clock cycle is used to reed the conversion result stored In the FIFO, lor a total 01 56 clock cycles per
conversion. The Throughput Rate Is IClK (MHz)lN, whare N is the number 01 clock cycles/conversion.
Note 18: A mll~ry RETS specification Is available upon request At the time of printing, the LMI2(H)458CMEL/883 RETS specification complied with the boldf_
values In the Limits column.

1-122

.-s:

VIN ~ VIN+ - VIN-

....
"'"
......
.-"'s::"
....

GND ::; VIN+ -s.VA +

::I:

Electrical Characteristics

I\)

UI

Yl~~~~--~~~----------------,,----------------.,

~,'

YREF

,,

...C),~,

,,

~
I

Z

>VREF

,

,
,,

,
,,

,
,,

,

,,

,
,,

,
,,

,, "

""2

,
,,

,,

,

,
,,

,,

,
,,

,,

,
,,

,

,,

,
,,

,~, ,I'

,,

,

,
,,

,

,

,

,
,,

,,

,
,,

,
,,

VREF ~ VREF+ - VREF-

GND ,; VIN- ,;VA +

,,

,,

,
,,

,,

,,

,
,,

,,

,

,
,,

,

Q)

I\)

::I:

"'"

UI
Q)

, ,,'XC),t::l

TLlH/11264-22

FIGURE 1. The General Case of Output Digital Code vs the Operating Input Voltage Range

,,

'", '"
"

"

,,

,

,,

VREF+ - VREF- ~ 4.096V
VIN ~ VIN+ - VINGND ,; VIN+ ,;VA +
GND ,; VIN- ,;VA +

/

"

"

"

"

,,'
,

"

" 'V,'

,X

,I'"

,,

,

, '"
,
,
,,'
',,'

,I;

,
,,

,"

".<.,' Common-mode = 2.048V

"

"

,

,,

'"

,,",

,

,"

,

,
",'

"

"

"

,,'

,~

)<:~'V

"
"

" "
, "1 " ,

V1N + (V)

"

t:Jo,,~

',,,~,,,,,,,,,,,,,,,,,,,,,

TL/H/11264-23

FIGURE 2. Specific Case of Output Digital Code vs the Operating Input Voltage Range for VREF
1-123

01

UI

Y'A

,
,,

"'"
.-s::
....
"'"
......
.-s::
....
I\)

,,

,'~tt>

,
,,

I\)

......
"'"

"

,,

,

=

4.096V

Electrical Characteristics (Continued)
v·
A

~

.L

0.6 V/ - 0.5V

W

>rr.

0.2

v/

VREF+(V)

TLlH/11264-24

FIGURE 3. The General Case of the VREF Operating Range

VREF

= VREF+

- VREF-

VA+ = 5V

~

I

IL

W

~

4

VREF+(V)
FIGURE 4. The Specific Case of the VREF Operating Range for VA + = 5V

1·124

TLlH/11264-25

Electrical Characteristics (Continued)
0,1111,1111,1111( H095)
0,1111,1111,111 0(+4094)

0,0000,0000,001 0(+2)
0,0000,0000,000 1(+ 1)
0,0000,0000,0000(0)

1--------

-l

_~:j...E===:2Z::E~R0:2!TR~A~NS~I~TI~ON~_ _ _ _ _ _ _

VREF

-----------------s-CIVE
FULL-SCALE
TRANSITION

=VREF + - VREF-

= VIN + - VIN _
GHD :s; VIN + :s; VA+
GND:S; VIN _ :s; VA+
VIN

1,0000,0000,0001 (-4095)
1,0000,0000,0000 (-4096)
ANALOG INPUT VOLTAGE (VIN )
TL/H/11264-4

FIGURE 5a, Transfer Characteristic

+12LSB
+8 LSB

POSITIVE
FULL-SCALE
ERROR

+4095
NEGATIVE
FULL-SCALE
ERROR

-4LSB

SIf)

C.
-SLSB
-12LSB

""0

...""""

OUTPUT CODE

(from -4096 to H095)
TUH/11264-5

FIGURE 5b, Simplified Error Curve vs Output Code without Auto-Callbration or Auto-Zero Cycles

1-125

Electrical Characteristics (Continued)
+3 LSB
+2LSB
ZERO
ERROR

+1 LSB

NEGATIVE
FULL-SCALE
ERROR

POSITIVE
INTEGRAL
LlNEARITY,,ERROR

POSITIVE
FULL-SCALE
ERROR

""

+4095

-1 LSB
-2LSB
-3 LSB
OUTPUT CODE

(from -4096 to +4095)
TUH/11264-6

FIGURE 5c. Simplified Error Curve vs Output Code after Auto-Callbration Cycle

+2

+1

...c

8
....
~

!;

0

-T

:-- OFFSET VOLTAGE

,0

-1

-2
ANALOG INPUT VOLTAGE (VIN )
TL/H/11264-7

FIGURE 6. Offset or Zero Error Voltage

1·126

Typical Performance Characteristics

The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. The performance for 8-bit
sign and "watchdog" modes is equal to or better than shown. (Note 9)

Linearity Error Change
vs Clock Frequency
0.16

....

VA +

d
~

~

0
~
e;

~

%

J 1-"-

0.16

~
~

/

~

V

0.04

~

~

",

VA+ = VD+ :; SY
0.12 YREF + = 5Y VREr-

~

-0.04

0.6

I ..!

= OV - r--

felK :; 5 MHz

0.08
0.04

/

t;

1-"' .....

:::l

~

1I

~

~

i

1/ .....

-0.04

o

2

3

4 5

6 7

8

9 10

Linearity Error Change
vs Supply Voltage
0.15

~

0.10

e

0.05

Full-Scale Error Change
vs Clock Frequency
+0.3 O"r::--....".-......"".,-,-..,-,

r- VREF+ =3V
~:::l -005. r- VfCLKREF_==5 OVMHz
%

""""

4

4.5

+3

5

o

5.5

1 2

3

4 5

6 7

~

/'

Full-Scale Error
vs Supply Voltage

~
~

= 5 MHz
VREF + = 3V

-0.6

VREF _ = OV

-0.9

TA,

d

!0
~

felK

= 5 MHz

0.05

e;

-0.05

~

-0.10

IJ

= OV - r-:-

. . .v

",1'

.....

V~

TEMPERATURE (OC)

TA,

~

3.5

4

4.5

V

-0.10
-0.15

5.5

o

123 4 5 6 7 8 9 W
CLOCK FREQUENCY (MHz)

Zero Error Change
vs Supply Voltage

0.6

d
~
~

'"u

I

I"- ~~

i;"'"

-0.05

Zero Error Change
vs Reference Voltage

....

r-r-

= 25°C

0.05

SUPPLY VOLTAGE (V)

~

-0.15
-60 -40 -20 0 20 40 60 80 100 120 140

I--t--t-='l

= 25°C

'--''-~_-'--_-'-_--L.._-'

Zero Error Change
vs Temperature
sv

I

fClIC

NEGATI~E FUll~SCAL[

5V YREF-

VA+ =VD+ = 5V
1 1
0.10 VREF+ = 5V VREF- = OV _

0

~

REFERENCE VOLTAGE (V)

=

0.15

~

3

VA+ :; VD+ =

Zero Error Change
vs Clock Frequency

0.9,--,--.--,--,---,

I I

0.15

-1.01-+-+-+-+-+++++-1

TEMPERATURE (OC)

PO~E 'ULLiSCALE

o

-0.5 I-'F-+-t+-+-++-P.~::+-I

CLOCK FREQUENCY (MHz)

VA+ :; Vo+ :; 5V
fCLK
5MHz _
TA
25 0 C
1

VREH

1.5~~~~~~-,-.-,-,

1.0

-1.5 L...L.....J'--I--'......L......1......L.~~..J
-60 -40 -20 0 20 40 60 80 100 120 140

8 9 10

=
=

0.10

;
~

Full-Scale Error Change
vs Reference Voltage

....

Full-Scale Error Change
vs Temperature

L.....J'--I'--I......L......1......L.~~...L....J

-0.3

SUPPLY VOLTAGE (V)

-3

r--..... ......

o

~

1A. = 25°C

1

"-

0.1

o

I

.....

-0.1
3.5

\.

0.2

i

\

3

\

0.3

REFERENCE VOLTAGE (V)

~~

~

u

0.4

TENPERATURE (OC)

0.20

= 5V

VA+ :; YD+

T. = 25°C feLK = 5 MHz

0.5

:::l

-0.08
-60 -40 -20 0 20 40 60 80 100 120 140

CLOCK FREQUENCY (MHz)

~

~
~

:::l

-0.08

~

Linearity Error Change
vs Reference Voltage

Linearity Error Change
vs Temperature

= Vo+ = 5V I
= OV

0.12 VREF'+ = 5Y VREF'TA = 2.5°C
0.08

+

0.04

= YD+ = 5V
= SMHz = 25°C

VAt

fcLle

0.5

TA,

0.4

....
~

0

0.3

\

0.2
0.1

o

\

,

o

0.02

d

i

~

-0.04

VREF'+ = 3V

v"'_ = DV

I

felK

TA

-0.06

3.5

_

= 5 MHz

=25°C

I

-0.08
3

REFERENCE VOLTAGE (V)

i'-.

I
/

-0.02

-

I
5.5

~.5

SUPPLY VOLTAGE (V)
TlIH/11264-8

1-127

Typical Performance Characteristics

The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. The performance for S-bit
sign and "watchdog" modes is equal to or better than shown. (Note 9) (Continued)
Analog Supply Current
vs Temperature

Digital Supply Current
vs Clock Frequency

4.0

!i

I
~

8:

~ 3.D

!.

~

I-'"
I.~ 1-"' ..... I-"'i'
I-'"
~"
......
1 1

3.5

... ~

'-I~

1.25

§

1.00

i...

0.75

g

0.25

;:!

II

2.5

.5
i3

'"

... ~
-"

.. I--'

Digital Supply Current
vs Temperature
0.70

I.SO

YoU = YD+
- f - feLK III 5t.tHz

!

,;'

TEMPERATURE (OC)

5

6 7

8 9

~

-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (oC)

VREFOUT Une Regulation
40

.1VA+=V
' ..D'+=5V
~

20

. ='D··''''··'' ~#
Sampling Ratl=87.7kHl

50
40

S

.

T,,"25 0 C

60 'cue =S ..Hz

....3

VIN =5Vp_ p

11111111
11111111

60

r-- ,..~INI! ~I!V
• p_p

Rs=SOA

70

r- S.·'"i'I'j'ii ~;i7kH'

62

= SVp_p

80

Rs=50n
TA-250C

-....

VIN

70
68

60

Unipolar Signal-to-Noise
+ Distortion Ratio
vs Input Signal Level

I--

'CLK=5UHl

72

62

Unipolar Signal-to-Noise
+ Distortion Ratio
vs Inpu~ Frequency

I=:

I-- TA"25 0C

74 r-SalllpllngRat,"B7.7kHz -

66

fREQUENCY (kHz)

f-

1..11111 . ~
r- ,,"50Q
VA+=VD+-vRIF -+5V

64

I 1111111

60

68
66

T,,"'2S 0C

70

ill

'eLK-' .. Hz

74

"

Rs "500

75

76 f- v...+=vD+=Vau=+5V

....
3

76

fREQUENCY (kHz)

80
78

78

V1N=:l:SV

10 15 20 25 30 35 40

Unipolar Signal-to-Noise Ratio
vslnputFrequency
80

II

80

§

=

I III
I I JII

~

5

II .1
'~r lIm-'I'1I!

fREQUENCY (kHz)

WJ

85

'CLK=St.lHz

o

Bipolar Spurious Free
Dynamic Range

I

v...+=vD+ =vREr ;; +5V

~

lIP' "lli"' "I'

fREQUENCY (kHz)

Bipolar Spectral Response
with 40 kHz Sine Wave Input
Rs-SOl).

-120

10 15 20 25 30 35 40

fREQUENCY (kHz)

i""j''' ,--

S/H=73,70d8

~

""

T..,=25 0 C
V1N,"iSV
VAt:VD+=VRU =+5V

0::

~ -60 1-+--+-+
~
in

';.".:J+

-20

....~ -40 f-+-+--+-

30

/

20
10

/

o

/

'+~....
",,.a

..... -

/

/

-70 -60 -50 -40 -30 -20 -10

100

0

5

INPUT SIGNAL LEVEL (dB)

fREQUENCY (kHz)

Unipolar Spectral Response
with 10 kHz Sine Wave Input

10 15 20 25 30 35 40
fREQUENCY (kHz)

Unipolar Spectral Response
with 20 kHz Sine Wave Input

Unipolar Spectral Response
with 40 kHz Sine Wave Input

o~,,~,,~-.-.-.,

....

-201-+-++

1-+-+-+§ -60 1-+-+-+~
in

3

-40

-20

....
3

~

-20

-40

....3

-40

-60

§

-60

~

:;!

""z

i'5

ill

-80

in

-100
-120
10 15 20 25 30 35 40
fREQUENCY (kHz)

'-'-'-..JI:...:.J."':"'L-.l....-'-L-J..-'U

o

10 15 20 25 30 35 40
fREQUENCY (kHz)

-120
0

10 15 20 25 30 35 40
fREQUENCY (kHz)

TUHI11264-11

1-129

Test Circuits and Waveforms
V'

V'

Ro

GND

1-+--- ~~~~UT

J

VOH

'1. =100pF

GND

TL/H/11264-12

V'

to

V'

5

90" H

TL/H/11264-13

V'

Ro

... = 1 kR

to

V'

1-+--- ~~~UT
I'1.=100 PF
TL/H/11264-15

TLlH/11264-14

FIGURE 7. TRI-STATE Test Circuits and Waveforms

Timing Diagrams
VA + = Vo+ = +5V, tR = tF = 3 ns, CL = 100 pF for the INT, DMARQ, DO-D15 outputs.

~
~:

~~,'
~,I==~':

,AO-A"~

.===,
j'

Cs

I
ti'

~~_3_i~__-J~~

/

_ _ _ _ _ _ _ _-'

I,

jl

1

I
I
I

\.....

I

"

Ro

c~~~

(

I
I

.: 16.

:,

)>----.....,
:&
I

I:

~

VALID DATA :

DO-DIS - - {..._ _...;._ _ _

I

17

I

~
18

13

\

I
"

I

."
I
I

!
:

.',
I

11

12

I
I

X
:.

)

VALID DATt
14

.:.

15

.:

TLlH/11264-16

FIGURE 8a. Multiplexed Data Bus

1, 3: CS or Address valid to ALE low set-up time.

11: WR pulse width
12: WR high to next ALE high
13: WR high to next WR or RD low

2, 4: CS or Address valid to ALE low hold time.
5: ALE pulse width
6: RD high to next ALE high

14:· Data valid to WR high set-up time
15: Data valid to WR high hold time

7: ALE low to RD low

16: RD low to data bus out of TRI-STATE

8: RD pulse width
9: RD high to next RD or WR low

17: RD high to TRI-STATE
18: RD low to data valid (access time)

10: ALE low to WR low
1-130

Timing Diagrams
VA + = Vo+ = +5V, tR = tF = 3 ns, CL = 100 pF for the iN'i', DMARQ, DO-D15 outputs. (Continued)

)

AO-A4-{

,

csl\

20

.',,

~

II

,,

20

,

I.

\,,
.

iffi

'wl

"

18

CYCLE

~

16

"

00-015

21

"

II

\

ViR

,,,,,I

:.

CYCLE

21

•

,"

17

I.
I

I

II

~

VALID DATA

.'
I

II

.:

I

1,,I

I
I

14

,II

jl

00-015

,

I~--------------------------~~~: _.

'.

,

II

/

X

13

L.-

.:

15
'i

X

VALID DATA

TL/H/I1264-17

FIGURE 8b. Non-Multiplexed Data Bus (ALE = 1)
8: RD pulse width

16: RD low to data bus out of TRI-STATE
17: RD high to TRI-STATE

9: RD high to next RD or WR low
11: WR pulse width
13: WR high to next WR or RD low

18: RD low to data valid (access time)
19: Address invalid from RD or WR high (hold time)

14: Data valid to WR high set-up time
15: Data valid to WR high hold time

20: CS low or address valid to RD low
21: CS low or address valid to WR low

_----Ir!

+ 5V, tR = tF = 3 ns, CL = 100 pF for the INT, DMARQ, DO-D15 outputs.
DMARQ

Ii-!-~\

•

,I~--------------­

I

I

I

~

I
I

i"

22

.:

'

:

~\,,-----r1--.l·TLlH111264-18

FIGURE 8e. Interrupt and OMARQ
22: INT high from RD low
23: DMARQ low from RD low

1-131

•

Pin Description
These are the analog and digital supply voltage
pins. The LM12(H)454/S's supply voltage operating range is + 3.0V to + 5.5V. Accuracy is guaranteed only if VA + and VD + are connected to the
same power supply. Each pin should have a parallel combination of 10 ,.F (electrolytic or tantalum)
and 0.1 ,.F (ceramic) bypass capacitors connected
between it and ground.
00-015 The internal data input/output TRI-STATE buffers
are connected to these pins. These buffers are designed to drive capacitive loads of 100 pF or less.
External buffers are necessary for driving higher
load capacitances. These pins allows the user a
means of instruction input and data output. With a
logic high applied to the BW pin, data lines OS015 are placed in a high impedance state and data
lines 00-07 are used for instruction input and
data output when the LM12(H)454/S is connected
to an S-bit wide data bus. A logic low on the BW
pin allows the LM12(H)454/S to exchange information over a 16-bit wide data bus.

BW

This is the active low interrupt output. This output is. designed to drive capacitive loads of
100 pF or less. External buffers are necessary
for driving higher load capaCitances. An interrupt signal is generated any time a nonmasked interrupt condition takes place. There
are eight different conditions that can cause
an interrupt. Any interrupt is reset by reading
. the Interrupt Status register. (See Section 2.3.)

This is the input for the active low REAO bus control signal. The data input/output TRI-STATE buffers, as selected by the logic signal applied to the
BW pin, are enabled when RO and ~ are both
low. This allows the LM12(H)454/S to transmit information onto the databus.
This is the input for the active low WRITE bus control signal. The data input/output TRI-STATE buffers, as selected by the logic signal applied to the
BW pin, are enabled when WR and ~ are both
low. This allows the LM12(H)454/S to receive information from the databus.
This is the input for the active low Chip Select control signal. A logic low should be applied to this pin
only during a REAO or WRITE access to the
LM12(H)454/S. The internal clocking is halted and
conversion stops while Chip Select is low. Conversion resumes when the Chip Select input signal
returns high.
ALE

This is the Address Latch Enable input. It is used in
systems containing a multiplexed databus. When
ALE is asserted high, the LM12(H)454/S accepts
information on the databus as a valid address. A
high-to-Iow transition will latch the address data on
AO-A4 while the ~ is low. Any changes on AOA4 and CS while ALE is low will not affect the
LM12(H)454/S. See Figure 8a. When a non-multiplexed bus is used, ALE is continuously asserted
high. See Figure 8b.
CLK
This is the external clock input pin. The
LM12(H)454/S operates with an input clock frequency in the range of 0.05 MHz to 10.0 MHz.
AO-A4 These are the LM12(H)454/S's address lines.
They are used to access all internal registers, Conversion FIFO, and Instruction RAM.
SYNC

rising clock edge either starts a conversion or
makes a comparison to a programmable limit
depending on which function is requested by a
programming instruction. This pin will be an
output if "1/0 Select" is set high. The SYNC
output goes high when a conversion or a comparison is started and low when completed.
(See Section 2.2). An internal reset after power is first applied to the LM12(H)454/S automatically sets this pin as an input.
This is the Bus Width input pin. This input allows the LM12(H)454/S to interface directly
with either an S- or 16-bit databus. A logic high
sets the width to S bits and places OS-015 in
a high impedance state. A logic low sets the
width to 16 bits.

OMARQ

This is the active high Oirect Memory Access
Request output. This output is designed to
drive capacitive loads of 100 pF or less. External buffers are necessary for driving higher
load capacitances. It goes high whenever the
number of conversion results in the conversion
FIFO equals a programmable value stored in
the Interrupt Enable register. It returns to a logic low when the FIFO is empty.

GNO

This is the LM12(H)454/S ground connection.
It should be connected to a low resistance and
inductance analog ground return that connects
directly to the system power supply ground.

INO-IN7
(INO-IN3
LM12H454
LM12454)

These are the eight (LM12(H)45S) or four
(LM12(H)454) analog inputs. A given channel
is selected through the instruction RAM. Any
of the channels can be configured as an independent single-ended input. Any pair of channels, whether adjac~nt or non-adjacent, can
operate as a fully differential pair.

S/H IN+
S/H INMUXOUT +
MUXOUT -

These are the LM12(H)454's non-inverting and
inverting inputs to the internal S/H.
These are the LM12(H)454's non-inverting and
inverting outputs from the internal multiplexer.
This is the negative reference input. The
LM12(H)454/S operate with OV ,;: VREF- ,;:
VREF+. This pin should be bypassed to
ground with a parallel combination of 10 ,.F
and 0.1 ,.F (ceramic) capacitors.
This is the positive reference input. The
LM12(H)454/S operate with OV ,;: VREF+ ,;:
VA +. This pin should be bypassed to ground
with a parallel combination of 10 ,.F and
0.1 ,.F (ceramic) capacitors.

This is the synchronization input/output. When
used as an output, it is designed to drive capacitive
loads of 100 pF or less. External buffers are necessary for driving higher load capacitances. SYNC
is an input if the Configuration register's "1/0 Select" bit is low. A rising edge on this pin causes
the internal S/H to hold the input signal. The next

VREFOUT

1-132

This is the internal 2.5V bandgap's output pin.
This pin should be bypassed to ground with 'a
100 ,.F capaCitor.

r-

.....
==

Application Information

N

.co.
.co.

UI

1.0 Functional Description
The LM12(H)454 and LM12(H)458 are multi-functional Data
Acquisition Systems that include a fully differential 12-bitplus-sign self-calibrating analog-to-digital converter (ADC)
with a two's-complement output format, an 8-channel
(LM12(H)458) or a 4-channel (LM12(H)454) analog multiplexer, an internal 2.5V reference, a first-in-first-out (FIFO)
register that can store 32 conversion results, and an Instruction RAM that can store as many as eight instructions to be
sequentially executed. The LM12(H)454 also has a differential multiplexer output and a differential StH input. All of this
circuitry operates on only a single + 5V power supply.

The LM12(H)454t8's "watchdog" mode is used to monitor
a single-ended or differential signal's amplitude. Each sampled signal has two limits. An interrupt can be generated if
the input signal is above or below either of the two limits.
This allows interrupts to be generated when analog voltage
inputs are "inside the window" or, alternatively, "outside the
window". After a "watchdog" mode interrupt, the processor
can then request a conversion on the input signal and read
the signal's magnitude.
The analog input multiplexer can be configur!ld for any combination of single-ended or fully differential operation. Each
input is referenced to ground when a multiplexer channel
operates in the single-ended mode. Fully differential analog
input channels are formed by pairing any two channels together.
The LM12(H)454's multiplexer outputs and StH inputs
(MUXOUT+, MUXOUT- and StH IN+, StH IN-) provide
the option for additional analog signal processing. Fixedgain amplifiers, programmable-gain amplifiers, filters, and
other processing circuits can operate on the signal applied
to the selected multiplexer channel(s). If external processing is not used, connect MUXOUT + to StH IN + and MUXOUT- toStH IN-.

The LM12(H)454t8 have three modes of operation:
12-bit + sign with correction
8-bit + sign without correction
8-bit + sign comparison mode ("watchdog" mode)
The fully differential 12-bit-plus-sign ADC uses a charge redistribution topology that includes calibration capabilities.
Charge re-distribution ADCs use a capacitor ladder in place
of a resistor ladder to form an internal DAC. The DAC is
used by a successive approximation register to generate
intermediate voltages between the voltages applied to
VREF- and VREF+. These intermediate voltages are compared against the sampled analog input voltage as each bit
is generated. The number of intermediate voltages and
comparisons equals the ADC's resolution. The correction of
each bit's accuracy is accomplished by calibrating the capacitor ladder used in the ADC.

The LM12(H)454t8's internal StH is designed to operate at
its minimum acquiSition time (1.13 !'-S, 12 bits) when the
source impedance, Rs, is ,,;: 600. (fCLK ,,;: 8 MHz). When
600. < Rs :;;; 4.17 kn, the internal StH's acquisition time
can be increased to a maximum of 4.88 !,-S (12 bits, fCLK =
8 MHz). See Section 2.1' (Instruction RAM "00") Bits 12-15
for more information.
An internal 2.5V bandgap reference output is, available at
pin 44. This voltage can be used as the ADC reference for
ratiometric conversion or as a virtual ground for front-end
analog conditioning circuits. The VREFOUT pin should be bypassed to ground with a 100 !,-F capacitor.
Microprocessor overhead is reduced through the use of the
internal conversion FIFO. Thirty-two consecutive conversions can be completed and stored in the FIFO without any
microprocessor intervention. The microprocessor can, at
any time, interrogate the FIFO and retrieve its contents. It
can also wait for the LM12(H)454t8 to issue an interrupt
when the FIFO is full or after any number (:;;;32) of conversions have been, stored.

Two different calibration modes are available; one compensates for offset voltage, or zero error, while the other corrects both offset error and the ADC's linearity error.
When correcting offset only, the offset error is measured
once and a correction coefficient is created. During the full
calibration, the offset error is measured eight times, averaged, and a correction coefficient is created. After completion of either calibration mode, the offset correction coefficient is stored in an internal offset correction register.
The LM12(H)454t8's overall linearity correction is achieved
by correcting the internal DAC's capacitor mismatch. Each
capacitor is compared eight times against all remaining
smaller value capacitors and any errors are averaged. A
correction coefficient is then created and stored in one of
the thirteen internal linearity correction registers. An internal
state machine, using patterns stored in an internal 16 x 8-bit
ROM, executes each calibration algorithm.

Conversion sequencing, internal timer interval, multiplexer
configuration, and many other operations are programmed
and set in the Instruction RAM.
A diagnostic mode is available that allows verification of the
LM12(H)458's operation. The diagnostic mode is disabled in
the LM12(H)454. This mode internally connects the voltages present at the VREFOUT, VREF+, VREF-, and GND
pins to the internal VIN+ and VIN- StH inputs. This mode is
activated by setting the Diagnostic bit (Bit 11) in the Configuration register to a "1". More information concerning this
mode of operation can be found in Section 2.2.

Once calibrated, an internal arithmetic logic unit (ALU) uses
the offset correction coefficient and the 13 linearity correction coefficients to reduce the conversion's offset error and
linearity error, in the background, during the 12-bit + sign
conversion. The 8-bit + sign conversion and comparison
modes use only the offset coefficient. The 8-bit + sign
mode performs a conversion in less than half the time used
by the 12-bit + sign conversion mode.

1-133

.....
.....
==

rN

::J:
.co.
UI
.co.

.....
r.....
==
N

.co.

UI

co
.....

r-

.....
==
N

::J:
.co.

UI

co

2.0 Internal User-Programmable Registers
2.1 INSTRUCTION RAM
The instruction RAM holds up to eight sequentially executable instructions. Each 48-bit long instruction is divided into
three 16-bit sections. READ and WRITE operations can be
issued to each 16-bit section using the instruction's address
and the 2-bit "RAM pointer" in the Configuration register.
The eight instructions are located at addresses 0000
through 0111 (M-'A1, BW = 0) when using a 16-bit wide
data bus or at addresses 00000 through 01111 (A4":AO,
BW = 1) when using an 8-bit wide data bus. They can be
accessed and programmed in random order.
Any Instruction RAM READ or WRITE can affect the sequencer's operation:

Bits 2-4 select which of the eight input channels ("000" to
"111" for INO-IN?) will be configured as non-inverting inputs to the LM12(H)458's ADC. (See Page 25, Table I.)
They select which of the four input channels ("000" to
"011" for INO-IN4) will be configured as non-inverting inputs to the LM12(H)454's ADC. (See Page 25, Table II.)
Bits 5-7 select which of the seven input channels ("001" to
"111" for IN1 to IN?) will be configured as inverting inputs to
the LM12(H)458's ADC. (See Page 25, Table I.) They select
which of the three input channels ("001" to "011" for IN1IN4) will be configured as inverting inputs to the
LM12(H)454's ADC. (See Page 25, Table II.) Fully differential operation is created by selecting two multiplexer channels, one operating in the non-inverting mode and the other
operating in the inverting mode. A code of "000" selects
ground as the inverting input for single ended operation.

The Sequencer should be stopped by setting the RESET
bit to a "1" or by resetting the START bit in the Configuration Register and waiting for the current instruction to
finish execution before any Instruction RAM READ or
WRITE is initiated.
A soft RESET should be issued by writing a "1" to the
Configuration Register's RESET bit after any READ or
WRITE to the Instruction RAM.

Bit 8 is the SYNC bit. Setting Bit 8 to "1" causes the Sequencer to suspend operation at the end of the internal
S/H's acquisition cycle and to wait until a rising edge appears at the SYNC pin. When a rising edge appears, the
S/H acquires the input signal magnitude and the ADC performs a conversion on the clock's next rising edge. When
the SYNC pin is used as an input, the Configuration register's "1/0 Select" bit (Bit ?) must be set to a "0". With
SYNC configured as an input, it is possible to synchronize
the start of a conversion to an external event. This is useful
in applications such as digital signal processing (DSP)
where the exact timing of conversions is important.
When the LM12(H)454/8 are used in the "watchdog" mode
with external synchronization, two rising edges on the SYNC
input are required to initiate two comparisons. The first rising
edge initiates the comparison of the selected analog input
signal with Limit # 1 (found in Instruction RAM "01 ") and the
second rising edge initiates the comparison of the same
analog input signal with Limit # 2 (found in Instruction RAM
"10").

The three sections in the Instruction RAM are selected by
the Configuration Register's 2-bit "RAM Pointer", bits D8
and 09. The first 16-bit Instruction RAM section is selected
with the RAM Pointer equal to "00". This section provides
multiplexer channel selection, as well as resolution, acquisition time, etc. The second 16-bit section holds "watchdog"
limit # 1, its sign, and an indicator that shows that an interrupt can be generated if the input signal is greater or less
than the programmed limit. The third 16-bit section holds
"watchdog" limit #2, its sign, and an indicator that shows
that an interrupt can be generated if the input Signal is greater or less than the programmed limit.
Instruction RAM "00"
Bit 0 is the LOOP bit. It indicates the last instruction to be
executed in any instruction sequence when it is set to a "1".
The next instruction to be executed will be instruction O.

Bit 9 is the TIMER bit. When Bit 9 is set to "1", the Sequencer will halt until the internal 16-bit Timer counts down
to zero. During this time interval, no "watchdog" comparisons or analog-to-digital conversions will be performed.

Bit 1 is the PAUSE bit. This controls the Sequencer's operation. When the PAUSE bit is set ("1 "), the Sequencer will
stop after reading the current instruction and before executing it, and the start bit in the Configuration register is automatically reset to a "0". Setting the PAUSE also causes an
interrupt to be issued. The Sequencer is restarted by placing
a "1" in the Configuration register's Bit 0 (Start bit).

Bit 10 selects the ADC conversion resolution. Setting Bit 10
to "1" selects 8-bit + sign and when reset to "0" selects
12-bit + sign.
Bit 11 is the "watchdog" comparison mode enable bit.
When operating in the "watchdog" comparison mode, the
selected analog input signal is compared with the programmable values stored in Limit #1 and Limit #2 (see Instruction RAM "01" and Instruction RAM "10"). Setting Bit 11 to
"1" causes two comparisons of the selected analog input
signal with the two stored limits. When Bit 11 is reset to ."0",
an 8-bit + sign or 12-bit + sign (depending on the state of
Bit 10 of Instruction RAM "00") conversion of the input signal can take place.

After the Instruction RAM has been programmed and the
RESET bit is set to'~1", the Sequencer retrieves Instruction
000, decodes it, and waits for a "1" to be placed in the
Configuration's START bit. The START bit value of "0"
"overrides" the action of Instruction ODD's PAUSE bit when
the Sequencer is started. Once started, the Sequlilncer executes Instruction 000 and retrieves, decodes, and executes
each of the remaining instructions. No PAUSE Interrupt (I NT
5) is generated the first time the Sequencer executes Instruction 000 having a PAUSE bit set to "1 ". When the Sequencer encounters a LOOP bit or completes all eight instructions, Instruction 000 is retrieved and decoded. A set
PAUSE bit in Instruction 000 now halts the Sequencer before the instruction is executed.

1-134

2.0 Internal User-Programmable Registers (Continued)
A4A3A2A1

Purpose

Type 015101410131012

0
0

0 0
R/W
Instruction RAM
to
(RAM Pointer = 00)
1 1 1

010

09

08

Watch8/12 Timer Sync
dog

07

06

05

VIN(MUXOUT-)'

04

03

02

VIN+
(MUXOUT+)'

01

00

Pause Loop

0
0

0 0
R/W
Instruction RAM
to
(RAM Pointer = 01)
1 1 1

Acquisition
Time

011

0

0 0
R/W
Instruction RAM
to
(RAM Pointer = 10)
1 1 1

1

0

0

0

Configuration
Register

1

0

0

1

Interrupt Enable
Register

Don't Care

>/< Sign

Limit #1

Don't Care

>/< Sign

Limit #2

RAM
Pointer

I/O Auto Chan Stand- Full AutoReset Start
Sel Zeroee Mask by
CAL Zero

0

R/W

R/W

R
1

0

1

0

Interrupt Status
Register

Don't Care

DIAGt

Number of Conversions
in Conversion FIFO
to Generate INT2

Test
=0

Sequencer
Address to
Generate INTI
Address
of
Sequencer
Instruction

Actual Number of
Conversion Results
in Conversion FIFO

INT7

INT6

INT5

INT4

INT3 INT2 INn

INTO

INST7 INST6 INST5 INST4 INST3 INST2 INSTI INSTO

bein~

Executed
1

0

1

1

Timer
Register

R/W

1

1

0

0

Conversion
FIFO

R

1

1

0

1

Limit Status
Register

R

Timer Preset High Byte
Address
or Sign

ISign

Conversion
Data: MSBs

timit # 2: Status

Timer Preset Low Byte

Conversion Data: LSBs

Limit #1: Status

'LM12(H)454 (Refer to Table II).
,"
tLM12(H)458 only. Must be set to "0" for the LM12(H)454.

FIGURE 9_ LM12(H)454/8 Memory Map for 16·Blt Wide Databus (BW = "0", Test Bit = "0" and AO

1-135

=

Don't Care)

II

2,0 Internal User-Programmable Registers
A4

A3

A2

A1

0

0
to
1

0

0
to
1

0

0
to
1

0

0
to
1

0

0
to
1

0

0

1

0
to
1

0

0

0

0

1
0
0
1
0
0
1
0
·0
1
0
0
1
0
0
1
1
1

0
0

0
0

AO

Purpose

Type

07

R/W

0
1

Instruction RAM
(RAM Pointer = 00)

(CoritinuE!d)

06
VIN-

VIN+

(MUXOUT-)'

(MUXOUT+)'

R/W

1

02,

.03

04

05

Watchdog

Acquisition Time

1

'

..

01

OJ)

Pause

Loop

Timer

Sync

>1<

Sign

>1<

Sign

Reset

Start

8/12

R/W

Comparison Limit ;1'1

0
1

Instruction RAM
(R~M Pointer = 01)

R/W'

1

Don't Care

1
R/W

Comparison Limit

0
1

Instruction RAM
(RAM Pointer = 10)

;I' 2

R/W

Don't Care

1
1

O.
1

R/W·

0
.1

Configuration
Register

0

1

0

0

1

·1

1

0

1

0

0

1

0

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

0

0

0

1

1

0

0

1

1

1

0

1

0

1

1

0

1

1

R/W

R
Interrupt Status
Register

I Auto I Chan
Zeroee Mask

R/W
R/W

Interrupt Enable
Register

I/O
Sel

R

Standby

Don't Care
INT?I· INTSIINT5.

INT4

Full
Cal

AutoZero

DIAGt

Test
=0

RAM Pointer

INT3

INT2

INn

Number of Conversions in Conversion
FIF.O to Generate INT2
INST7IINSTSIINST5

INST4

INST3

INST2

Actual Number of COlwersions Results
in Conversion FIFO

INST1

INSTO

Address of Sequencer
Instruction
being Executed

R/W

Timer Preset: Low Byte

R/W

Timer Preset: High Byte

Conversion
FIFO

R

Limit Status
Register

INTO

Sequencer Address to
Generate INT1

Timer
Register

R

,

Conversion Data: LSBs
Address or Sign

Conversion Data: MSBs

Sign

R

Limit

;I' 1 Status

R

Limit

;I' 2

Status

'LMI2(H)454 (Refer to Table II).
tLMI2(H)458 only. Must be sello "O"'or Ihe LMI2(H)454.

FIGURE 10. LM12(H)454/8 Memory Map for 8·Blt Wide Oatabus (BW = "1" and Test Bit = "0")

1-13S

2.0 Internal User-Programmable Registers (Continued)
Bits 12-15 are used to store the user-programmable acquisition time. The Sequ/ilncer keeps the internal S/H 'in ,the
acquisition mode for a fixed number of clock cycles (nine
clock cycles, for 12-bit + sign conversions and two clock
cycles for 8-bit + sign conversions or "watchdog" comparisons) plus a variable number of clock cycles equal to twice
the value stored in Bits 12-15. Thus, the S/H's acquisition
time is (9 + 20) clock cycles for 12-bit + sign conversions
and (2 + 20) clock cycles for 8-bit + sign conversions or
"watchdog" comparisons, where 0' is the value stored in
Bits 12-15. The minimum acquisition tim'e compensates for
the typical internal multiplexer series resistance of 2 ,kO,
and any additional delay, created by Bits 12-15 compensates for source resistances greater than 600 (1000): (For
this acquisition time discussion, numbers in ( ) are shown for
the I,.M12(H)454/8 operating at 5 MHz.) The necessary acquisition time is determined by the source impedance at the
multiplexer, input. If the source resistance (Rs) < 600
(1000) and the clock frequency is 8 MHz, the value stored
in bits 12-15 (0) can be 0000. If Rs > 600 (1000), the
following equations determine the value that should be
stored in bits 12-15.
0= 0.45 x Rs xfClK
for 12-bits + sign
0= 0.36xRsxfcLK
for 8-bits + sign and "watchdog"
,

limit # 2 to generate an interrupt, while a "0" causes a voltage less than limit # 2 to generate an interrupt.
Bits'10-15 are not used.
2.2 CONFIGVRATION REGISTER
The Configuration register, 1000 (A4-A1, BW = 0) or
1000x (A4-AO, BW = 1) is a 16-bit control register with
read/write capability. It acts as 'the LM12(H)454's and
LM12(H)458's "control panel" holding global information as
well as start/stop, reset, self-calibration, and stand-by commands.
Bit 0 is the START/STOP bit. Reading Bit 0 returns an indication of the Sequencer's status. A "0" indicates that the
Sequencer is stopped and waiting to execute the next instruction. A "1" shows that the Sequencer is running. Writing a "0" halts the Sequencer when the current instruction
has finished execution. The next instruction to be executed
is pOinted to by the,instruction pointer found in the status
register. A "1" restarts the Sequencer with the instruction
currently pOinted to by the instruction pointer. (See Bits 810 in the Interrupt Status register.)
Bit 1 is the LM12(H)454/8's system RESET bit. Writing a
"1" to Bit 1 stops the Sequencer (resetting the Configuration register's START/STOP bit), resets the Instruction
pOinter to "000" (found in the Interrupt Status register),
clears the Conversion FIFO, and resets all interrupt flags.
The RESET bit will return to "0" after two clock cycles unless it is forced high by writing a "1" into the Configuration
register's Standby bit. A reset signal is internally generated
when power is first applied to the part. No operation should
be started until the RESET bit is "0".
Writing a "1" to Bit 2 initiates an auto-zero offset voltage
calibration. Unlike the' eight-sample auto-zero calibration
performed during the full calibration procedure, Bit 2 initiates 'a "short" auto-zero by sampling the offset once and
creating a correction coefficient (full calibration averages
eight samples of, the converter offset voltage when creating
a correction coefficient). If the Sequencer is running when
Bit 2 is set to "1", an auto-zero starts immediately, after the
conclusion of the currently running instruction. Bit 2 is reset
automatically to a "0'; and an interrupt flag (Bit 3, in the
Interrupt Status register) is set at the end of the auto-zero
(76 clock cycles). After c~mpletion of an auto-zero calibration, the Sequencer fetches the next instruction as pointed
to by the Instruction RAM's pOinter and resumes executi,on.
If the Sequencer is stopped, an auto-zero is performed immediately at the time requested.

Rs is in kO and fClK is in MH~. Rouncl the result to the next
higher integer value. If 0 is greater than 15, it is advisable to
lower the source impedance by using an analog buffer between the signal source and the LM12(H)458's multiplexer
inputs. The value of 0 can also be used to compensate for
the settling or response time of external processing circuits
'connected between the LM12(H)454's MUXOUT and
S/H IN pins.
"
Instruction RAM "01"
The second Instruction RAM section is selected by placing
a "01" 'in Bits 8 and 9 of the Configuration register.
Bits 0-7 hold "watchdog" limit # 1. When Bit 11' of Instruction RAM "00" is set to a "1", the LM12(H)454/8 performs
a "watchdog" comparison of the sampled 'analog input signal with the limit # 1 value first, followed by a comparison of
the same sampled analog input signal with the value found
in ,limit #2 (Instruction'RAM "10").
Bit 8 'holds limit # 1's sign.
Bit 9's'state determines the limit condition that generates a
"watchdog" interrupt. A"'1',' causes voltage greater than
limit #1 to generate an interrupt, while a "O"'causes a volt11ge less than limit # 1 to generate an inter~upt.
'
B!ts 10-15 are not used.
',

a

Writing a "1." to Bit 3 initiates a complete calibration process that includes a "long" auto-zero offset voltage correction (this calibration averages eight samples of the comparator o,ffset voltage when creating a correction coefficient)
followed by an AOC linearitY calibration. This complete calibration is started after the currently run'ning instruction is
completed if the Sequencer is running when Bit 3 is set to
"1". Bit3 is resetauiomaticallyto a "0" and an interruptflag
(Bif4, in' the Interrupt Status register) will be generated at
the end of the calibration procedure (4944 clock cycles).
After completion of a full auto-zero and linearity calibration,
the Sequencer fetches the next instruction as pOinted to by
the Instruction RAM's pointer and resumes execution. If the
Sequencer is stopped, a full calibration is performed imme'
diately at the time requested.'

Instruction RAM "10'"
The third Instruction RAM section is selected by plaCing a
"10" in Bits 8 and 9 of the Configuraiion register.'
"
Bits 0-7 hold "watchdog" limit # 2. Whe~ Bit 11 of Instruction RAM "00" is set to a "1", the LM12(H)454/8 performs
a "watchdog" comparison of the sampl!3d analog input signal with the limit # 1 value first (Instruction RAM "01 "), followed by a comparison of the same sampled analog input
signal with the value found in limit #2.
' '
Bit 8 holds 'Iimii #2's sign.'
Bit 9's state determines the limit condition that generates a
"watchdog" interrupt. A "1" causes a voltage greater than

1-137

II

2.0 Internal User-Programmable Registers (Continued)
Bit 4 is the Standby bit. Writing a "1" to Bit 4 immediately
places the LM12(H)454/S in Standby mode. Normal operation returns when Bit 4 is reset to a "0". The Standby command ("1") disconnects the external clock from the internal
circuitry, decreases the LM12(H)454/S's internal analog circuitry power supply current, and preserves all internal RAM
contents. After writing a "0" to the Standby bit, the
LM12(H)454/S returns to an operating state identical to that
caused by exercising the RESET bit. A Standby completion
interrupt is issued after a power-up completion delay that
allows the analog circuitry to settle. The Sequencer should
be restarted only after the Standby completion is issued.
The Instruction RAM can still be accessed through read and
write operations while the LM12(H)454/8 are in Standby
Mode.
Bit 5 is the Channel Address Mask. If Bit 5 is set to a "1",
Bits 13-15in the conversion FIFO will be. equal to the sign
bit (Bit 12) of the conversion data. Resetting Bit 5 to a "0"
causes conversion data Bits 13 through 15 to hold the instruction pOinter value of the instruction to which the conversion data belongs.
Bit S is used to select a "short" auto-zero correction for
every conversion. The Sequencer automatically inserts an
auto-zero before every conversion or "watchdog" comparison if Bit S is set to "1". No automatic correction will be
performed if Bit S is reset to "0".
The LM12(H)45418's offset voltage, after calibration, has a
typical drift of 0.1 LSB over a temperature range of -40'C
to + 85'C. This small drift is less than the variability of the
change in offset that can occur when using the auto-zero
correction with each conversion. This variability is the result
of using only one sample of the offset voltage to create a
correction value. This variability decreases when using the
full calibration mode because eight samples of the offset
voltage are taken, averaged, and used to create a correction value.
Bit 7 is used to program the SYNC pin (29) to operate as
either an input or an output. The SYNC pin becomes an
output when Bit? is a "1" and an input when Bit? is a "0".
With'SYNC programmed as an input, the rising edge of any
logic signal applied to pin 29 will start a conversion or
"watchdog" comparison. Programmed as an output, the
logiC level at pin 29 will go high at the start of a conversion
or "watchdog" comparison and remain high until either
have finished. See Instruction RAM "00", Bit 8.
Bits 8 and 9 form the RAM Pointer that is used to select
each of a 48-bit instruction's three lS-bit sections during
read or write actions. A "00" selects Instruction RAM section one, "01" selects section two, and "10" selects section
three.
Bit 10 activates the Test mode that is used only during production testing. Leave this bit reset to "0".
Bit 11 is the Diagnostic bit and is available only in the
LM12(H)45S. It can be activated by setting it to a "1" (the
Test bit must be reset to a "0"). The DiagnostiC mode,
along with a correctly chosen instruction, allows verification
that the LM12(H)458's ADC is performing correctly. When
activated, the inverting and non-inverting inputs are connected as shown in Table I. As an example, an instruction
with "001" for both VIN+ and VIN- while using the Diagnostic mode typically results in a full-scale output.
'

2.3 INTERRUPTS
The LM12(H)454 and LM12(H)45S have eight possible interrupts, all with the same priority. Any of these interrupts
will cause a hardware interrupt to appear on the jjiJj pin (31)
if they are not masked (by the Interrupt Enable register).
The Interrupt Status register is then read to determine which
of the eight interrupts has been issued.
TABLE I. LM12(H)458 Input Multiplexer
Channel Configuration Showing Normal
Mode and Diagnostic Mode
Channel
Selection
Data
000
001
010
011
100
101
110
111

Normal
Mode

DiagnostiC
Mode

VIN+

VIN-

VIN+

VIN-

INO
INl
IN2
IN3
IN4
IN5
INS
IN?

GND
INl
IN2
IN3
IN4
IN5
INS
IN?

VREFOUT
VREF+
IN2
IN3
IN4
IN5
INS
IN?

GND
VREFIN2
IN3
IN4
IN5
INS
IN?

TABLE II. LM12(H)454 Input Multiplexer
Channel Configuration
Channel
Selection
Data

MUX+

MUX-

000
001
010
011
lXX

INO
INl
IN2
IN3
OPEN

GND
INl
IN2
IN3
OPEN

The Interrupt Status register, 1010 (A4-A 1, BW = 0) or
1010X (A4-AO, BW = 1) must be cleared by reading it after
writing to the Interrupt Enable register. This removes any
spurious interrupts on the jjiJj pin generated during an Interrupt Enable register access.
Interrupt 0 is generated whenever the analog input voltage
on a selected multiplexer channel crosses a limit while the
LM12(H)454/S are operating in the "watchdog" comparison
mode. Two sequential comparisons are made when the
LM12(H)454/S are executing a "watchdog" instruction. Depending on the logic state of Bit 9 in the Instruction RAM's
second and third sections, an interrupt will be generated
either when the input signal's magnitude is greater than or
less than the programmable limits. (See the Instruction
RAM, Bit 9 description.) The Limit Status register will indicate which preprogrammed limit, ;1'1 or ;I' 2 and which instruction was executing when the limit was crossed.
Interrupt 1 is generated when the Sequencer reaches the
instruction counter value specified in the Interrupt Enable
register's bits S-10. This flag appears before the instruction's execution.
Interrupt 2 is activated when the Conversion FIFO holds a
number of conversions equal to the programmable value

1-138

r------------------------------------------------------------------------------,
2.0 Internal User-Programmable Registers (Continued)
stored in the Interrupt Enable register's Bits 11-15. This
value ranges from 0001 to 1111, representing 1 to 31 conversions stored in the FIFO. A user-programmed value of
0000 has no meaning. See Section 3.0 for more FIFO information.
The completion of the short, single-sampled auto-zero calibration generates Interrupt 3.

RESET bit is set to "1", the Sequencer is started by placing
a "1" in the Configuration register's START bit. Setting the
INT 1 trigger value to 000 does not generate an INT 1 the
first time the Sequencer retrieves and decodes Instruction
000. The Sequencer generates INT 1 (by placing a "1" in
the Interrupt Status register's Bit 1) the second time and
after the Sequencer encounters Instruction 000. It is important to remember that the Sequencer continues to operate
even if an Instruction interrupt (INT 1) is internally or externally generated. The only mechanisms that stop the Sequencer are an instruction with the PAUSE bit set to "1"
(halts before instruction execution), placing a "0" in the
Configuration register's START bit, or placing a "1" in the
Configuration register's RESET bit.

The completion of a full auto-zero and linearity self-calibration generates Interrupt 4.
Interrupt 5 is generated when the Sequencer encounters
an instruction that has its Pause bit (Bit 1 in Instruction RAM
"00") set to "1 ".
The LM12(H)454/8 issues Interrupt 6 whenever it senses
that its power supply voltage is dropping below 4V (typ).
This interrupt indicates the potential corruption of data returned by the LM12(H)454/8.

Bits 11-15 hold the number of conversions that must be
stored in the Conversion FIFO in order to generate an internal interrupt. This internal interrupt appears in Bit 2 of the
Interrupt Status register. If Bit 2 of the Interrupt Enable register is set to "1 ", an external interrupt will appear at pin 31

Interrupt 7 is issued after a short delay (10 ms typ) while
the LM12(H)454/8 returns from Standby mode to active operation using the Configuration register's Bit 4. This short
delay allows the internal analog circuitry to settle sufficiently, ensuring accurate conversion results.

r
:s:::
....

I\)

0l:Io

C7I

:!t
r
:s:::
....
I\)

::I:
0l:Io

"'0l:Io.,
.....
r

:s:::
....
~

U1

co

.....
r

:s:::
....

I\)

::I:
0l:Io

C7I

co

(INn.
2.5 INTERRUPT STATUS REGISTER
This read-only register is located at address 1010 (A4-A1,
BW = 0) or 1010x (A4-AO, BW = 1). The corresponding
flag in the Interrupt Status register goes high ("1 ") any time
that an interrupt condition takes place, whether an interrupt
is enabled or disabled in the Interrupt Enable register. Any
of the active ("1 ") Interrupt Status register flags are reset to
"0" whenever this register is read or a device reset is issued
(see Bit 1 in the Configuration Register).

2.4 INTERRUPT ENABLE REGISTER
The Interrupt Enable register at address location 1001
(A4-A1, BW = 0) or 1001x (A4-AO, BW = 1) has READ/
WRITE capability. An individual interrupt's ability to produce
an external interrupt at pin 31 (fiiI'i') is accomplished by placing a "1" in the appropriate bit location. Any of the internal
interrupt-producing operations will set their corresponding
bits to "1" in the Interrupt Status register regardless of the
state of the associated bit in the Interrupt Enable register.
See Section 2.3 for more information about each of the
eight internal interrupts.

Bit 0 is set to "1" when a "watchdog" comparison limit
interrupt has taken place.
Bit 1 is set to "1" when the Sequencer has reached the
address stored in Bits 8-10 of the Interrupt Enable register.
Bit 2 is set to "1" when the Conversion FIFO's limit, stored
in Bits 11-15 of the Interrupt Enable register, has been
reached.
Bit 3 is set to "1" when the single-sampled auto-zero has
been completed.

Bit 0 enables an external interrupt when an internal "watchdog" comparison limit interrupt has taken place.
Bit 1 enables an external interrupt when the Sequencer has
reached the address stored in Bits 8-10 of the Interrupt
Enable register.
BIt 2 enables an external interrupt when the Conversion
FIFO's limit, stored in Bits 11-15 of the Interrupt Enable
register, has been reached.

Bit 4 is set to "1" when an auto-zero and full linearity selfcalibration has been completed.
Bit 5 is set to "1" when a Pause interrupt has been generated.
Bit 6 is set to "1" when a low-supply voltage condition
(VA + < 4V) has taken place.

Bit 3 enables an external interrupt when the single-sampled
auto-zero calibration has been completed.
Bit 4 enables an external interrupt when a full auto-zero and
linearity self-calibration has been completed.

Bit 7 is set to "1" when the LM12(H)454/8 return from power-down to active mode.

Bit 5 enables an external interrupt when an internal Pause
interrupt has been generated.

Bits 8-10 hold the Sequencer's actual instruction address
while it is running.
Bits 11-15 hold the actual number of conversions stored in
the Conversion FIFO while the Sequencer is running.

Bit 6 enables an external interrupt when a low power supply
condition (VA + < 4V) has generated an internal interrupt.
Bit 7 enables an external interrupt when the LM12(H)454/8
return from power-down to active mode.

2.6 LIMIT STATUS REGISTER

Bits 8-10 form the storage location of the user-programmable value against which the Sequencer's address is compared. When the Sequencer reaches an address that is
equal to the value stored in Bits 8-10, an internal interrupt
is generated and appears in Bit 1 of the Interrupt Status
register. If Bit 1 of the Interrupt Enable register is set to "1",
an external interrupt will appear at pin 31 (fiiI'i').

The read-only register is located at address 1101 (A4-A 1,
BW = 0) or 1101 x (A4-AO, BW = 1). This register is used
in tandem with the Limit '" 1 and Limit '" 2 registers in the
Instruction RAM. Whenever a given instruction's input voltage exceeds the limit set in its corresponding Limit register
('" 1 or '" 2), a bit, corresponding to the instruction number,
is set in the Limit Status register. Any of the active ("1 ")
Limit Status flags are reset to "0" whenever this register is

The value stored in bits 8-10 ranges from 000 to 111, representing 0 to 7 instructions stored in the Instruction RAI,;;.
After the Instruction RAM has been programmed and the

1-139

II

2.0 Internal User-Programmable Registers'(Contlnued)
read or a device reset is issued (see Bit 1 in the Configuration register). This register, holds the status ot.limits # 1 and
#2 for each of the eight instructions. ,
Bits 0-7 show the Limit # 1 status. Each bit will be set high
("1'!) when the corresponding instruction's input voltage exceeds the threshold stored in the instruction's Limit # l' register. When, for example, instruction 3 is a "watchdog" operation (Bit 11 is set high) and the Input 'for instruction 3
meets the magnitude and/or polarity data stored in instruction 3's Limit # 1 register, Bit 3 in the Limit Status register
will be set to a "1".

3.0 ~IFQ
The result of each conversion stored in an. intemalread-only
FIFO (First-In, First-Oui) register. It is locate!i at 1100 (MA1, BW = 0) or 1100x (A4-AO, BW = 1). This register has
32 16-bit wide locations. Each location holds 13-bit data.
Bits 0~3 hold the'four lSB's in the 12 bits +,'sign mode or
"1110" in'the S bits +'slghmode. Bits 4-11 hold'the eight
MSB's and Bit 12 holds the sign bit. Bits 13-15 can hold
either the'''sign bit, extending'the register's tWo's complement data format to a full sixteen 'bits or the Instruction address that generated the' conversion arid the resulting data.
These modes are selected according' to the logic state of
the Configuration register's Bit 5.

Bits '8-15 show the Limit #2 status. Each bit will' be 'set
high ("1") when the corresporid'ing instruction's input voltage exceeds the threshold stored in the instruction's Limit
#2 register. When, for example, the input to instruction 6
meets the value stored in instruction 6'sLimit #2 register,
Bit 14 in the Limit Status register will be set to a "1".
2.7 TIMER

The FIFO status should be read in the Interrupt Status register (Bits 11-15) to determine the number of conversion re'
'suits that are held in the FIFO before retrieving them. 'This
will help prevent conversion data corruption that may take
place if the number of reads,are greater ,than the n!lm~er of
conversion results contained in,the FIFO. ,Trying to read the
FIFO when it is emptY may corrupt new data being written
into the, FIFO. Writing, more t~,an:32 conver~ion data into 'tlie
FIFO by the ADC res'ults in loss' of thE1 fir~t conversion data.
Therefore, to prevent data loss, it is recorrmendeQ that the
lM12(1:l)454/S's intern,lpt capabil,ity be used to inform the
system controller that the FIFO is,,fuli.
"
'

The lM12(H)454/S have an on-board 16-bit timer that includes a S-bit pre-scaler. It uses the clock signal applied to
pin 23 as its input. It can' generate time intervals"bf 0
through 221 clock cycles in steps of 25. This time interval
can be used to delay the execution of instructions. It can
also be used to slow the conversion rate when converting
slowly changing signals. This can reduce the amount of redundant. data stored in the FIFO and retrieved by,the controller.
The user-defined timing value used by the Timer is stored in
the 16-bit READ/WRITE Timer register at location 1011
(A4-A1, BW = 0) or 1011x (A4-AO; BW = 1) and'is preloaded automatically. Bits 0-7 hold the preset value's low
byte and Bits S-15 hold the high byte., The Timer is activated by the Sequencer only if the, current instruction's Bit.9 is
set ("1"). If the equivalent decimal value "N'.'
(0 ~ N ~ 2 16 - 1) is written inside'the 16:bitTimer register
and the Timer is enabled by setting an instruction's bit 9 to Ii
"1", the Sequencer will delay the same instruction's exe~u­
tion by halting at state 3 (S3), as shown' in Figure 11, for
'
32 x N + 2 clock cycles.

The lower p~rtion (AO := 0) of the !iata ~ord (Bits 0-7)
should be read first followed by a read of the upper portion
(AO = 1) when using the S-bit bus width (BW, "", ,1). Reaciillg
the upper portion first causes th~ data to shift down, whiCh
results in loss of. the lower bYte. "
,
Bits 0-12 hold 12-bit + sign conversion data. Bits 0-3 will
be 1110 (lSB) whe'il' using S-bit plus sign resolution.'
'
Bits 13-15 hold either the insiruction' responsible for the
associatEld conversion data or the, sign bit. Either mode is
selected with Bit 5 in the Configuration register.
'

2.8DMA

Using the FIFO's f~1I depth is a~hiev~d as follows: S,et the
value of the Interrupt Enable register's Bits 1,1-15 to ,11111
and the Interrupt Enable register's Bit 2 to a "1". This generates an external interrupt when the 31 st conversion is
stored in the FIFO. This gives the host processor a chance
to send a "0" tei thel:M12(H)454/S's Start bit (Conflgutation register) and,halUhe ADC before it completes the 32nd
conversion. The Sequencer halts after the ,current (32) conversion is completed. ihe, conversion data is then, transferred to the FIFO and occu'pies the 32nd location. FIFO
overflow is avoided iUhe Sequencer is halted .before the
start of the 32nd conversion by placing a "0:' ,in the Start bit
(Configuration register). It is important to remember that the
Sequencer continues to operate even If 'a FIFO internipt
(INT 2) is'internally or externally generated. The dnly
mechanisms that stop the Sequencer ate an instruction with
tM' PAUSE bit set to "1" (halts before instruction execulion); placing a "0'; in the' Configuration register's START
bit, or placing a "1" in the Configuration register's RESET

The OMA works in tandem with Interrupt 2. An active OMA
Request on pin 32 (OMARa), requires that the FIFO interrupt be enabled. The voltage on the OMARa pin goes high
when the'number of conversions iri the FIFO equals the
5-bit value stored in the Interrupt Enable register (bits 1115). The voltage on the TNT 'pin goes low at the same-time
as the voltage on the OMARa pin goes high. The voltage on
the OMARa pin go~s low when the FIFO is emptied. The
Interrupt Status register must be read to clear ,the FIFO interrupt flag in order to enabl~ the next PMA request.
DMA operation is optimized through the use of ,the 16:bit
databus connection (a logiC "0" applied to the, BW pin). Using this bus width allows OMA controllers that have single
address Read/Write capability toeasiiy unload the FIFO.
Using OMA on an S-bit databus is more difficult. Two read
operations (lOW byte, high byte) are needed to retrieve each

..

'

, .' ,

conversion result from the,FIFO. Therefore,;the DMA,controller must' be ,able to repeatedly access tWoc~J:1stant addres~es whE1r:t transferring data from the lM12(H)454/Sto
t~e host, system.

,'.

M"

1-140

,

,

4.0 Sequencer
State 3: Run the internal 16-bit Timer. The number of
clock cycles for this state varies according to the value
stored in the Timer register. The number of clock cycles is
found by using the expression below

The Sequencer uses a 3-bit counter (Instruction Pointer, or
IP, in Figure 7) to retrieve the programmable conversion
instructions stored in the Instruction RAM. The 3-bit counter
is reset to 000 during chip reset or if the current executed
instruction has its Loop bit (Bit 1 in any Instruction RAM
"00") set high ("1 "). It increments at the end of the currently
executed instruction and pOints to the next instruction. It will
continue to increment up to 111 unless an instruction's
Loop bit is set. If this bit is set, the counter resets to "000"
and execution begins again with the first instruction. If all
instructions have their Loop bit reset to "0", the Sequencer
will execute all eight instructions continuously. Therefore, it
is important to realize that if less than eight instructions are
programmed, the Loop bit on the last instruction must be
set. Leaving this bit reset to "0" allows the Sequencer to
execute "unprogrammed" instructions, the results of which
may be unpredictable.
The Sequencer's Instruction Pointer value is readable at
any time and is found in the Status register at Bits 8-10.
The Sequencer can go through eight states during instruction execution:
State 0: The current instruction's first 16 bits are read
from the Instruction RAM "00". This slate is one clock cycle
long.
State 1: Checks the slate of the Calibration and Slart bits.
This is the "rest" slate whenever the Sequencer is stopped
using the reset, a Pause command, or the Slart bit is reset
low ("0"). When the Slart bit is set to a "1 ", this state is one
clock cycle long.

32T

+2

where 0 ,,:; T ,,:; 2 16 -1.
StQto 7: Run the acquisition delay and read Limit # 1's
value if needed. The number of clock cycles for 12-bit +
sign mode varies according to
9 + 2D
where D is the user-programmable 4-bit value stored in bits
12-15 of Instruction RAM "00" and is limited to 0 ,,:; D ,,:;
15.
The number of clock cycles for 8-bit + sign or "watchdog"
mode varies according to
2 + 2D
where D is the user-programmable 4-bit value stored in bits
12-15 of Instruction RAM "00" and is limited to 0 ,,:; D ,,:;
15.
State 6: Perform first comparison. This state is 5 clock
cycles long.
State 4: Read Limit #2. This state is 1 clock cycle long.
State 5: Perform a conversion or second comparison.
This state takes 44 clock cycles when using the 12-bit +
sign mode or 21 clock cycles when using the 8-bit + sign
mode. The "watchdog" mode lakes 5 clock cycles.

State 2: Perform calibration. If bit 2 or bit 6 of the Configuration register is set to a "1", state 2 is 76 clock cycles long.
If the Configuration register's bit 3 is set to a "1", slate 2 is
4944 clock cycles long.

•

1-141

4.0 Sequencer (Continued)
RESET

IP =

a

•I.
I
I

I

Perform ,CalibratIon '52'>

Start Blt=O

Start Blt= 1

I
I
I
I
I
I
I
I

-----_.

~-----,-------IS51

Tl/H/II2M-19

FIGURE 11. Sequencer Logic Flow Chart (IP = Instruction Pointer)

1·142

5.0 Analog Considerations
number. As an example, VREF+ = 2.5V, VREF- = tV,
VIN+ = 1.5V and VIN- = GND. The 12-bit + sign output
code is positive full-scale, or 0,1111,1111,1111. If VREF +
= 5V, VREF- = tV, VIN+ = 3V, and VIN- = GND, the
12-bit + sign output code is 0,1100,0000,0000.

5.1 REFERENCE VOLTAGE
The difference in the voltages applied to the VREF+ and
VREF - defines the analog input voltage span (the difference between the voltages applied between two multiplexer
inputs or the voltage applied to one of the multiplexer inputs
and analog ground), over which 4095 positive and 4096
negative codes exist. The voltage sources driving VREF + or
VREF- must have very low output impedance and noise.
The circuit in Figure 12 is an example of a very stable reference appropriate for use with the LM12(H)454/B.

5.3 INPUT CURRENT
A charging current flows into or out of (depending on the
input voltage polarity) the analog input pins, INO-IN7 at the
start of the analog input acquisition time (tACO)' This current's peak value will depend on the actual input voltage
applied.

The ADC can be used in either ratiometric or absolute reference applications. In ratiometric systems, the analog input
voltage is proportional to the voltage used for the ADC's
reference voltage. When this voltage is the system power
supply, the VREF + pin is connected to VA + and VREF _ is
connected to GND. This technique relaxes the system reference stability requirements because the analog input voltage and the ADC reference voltage move together. This
maintains the same output code for given input conditions.

5.4 INPUT SOURCE RESISTANCE
For low impedance voltage sources ( < 100n for 5 MHz operation and < 60n for S MHz operation), the input charging
current will decay, before the end of the S/H's acquisition
time, to a value that will not introduce any conversion errors.
For higher source impedances, the S/H's acquisition time
can be increased. As an example, operating with a 5 MHz
clock frequency and maximum acquisition time, the
LM12(H)454/S's analog inputs can handle source impedance as high as 6.67 kn. When operating at S MHz and
maximum acquisition time, the LM12H454/S's analog inputs
can handle source impedance as high as 4.17 kn. Refer to
Section 2.1, Instruction RAM "00", Bits 12-15 for further
information.

For absolute accuracy, where the analog input voltage varies between very specific voltage limits, a time and temperature stable voltage source can be connected to the reference inputs. Typically, the reference voltage's magnitude
will require an initial adjustment to null reference voltage
induced full-scale errors.
When using the LM12(H)454/S's internal2.5V bandgap reference, a parallel combination of a 100 /JoF capacitor and a
0.1 /JoF capacitor connected to the VREFOUT pin is recommended for low noise operation. When left unconnected,
the reference remains stable without a bypass capacitor.
However, ensure that stray capacitance at the VREFOUT pin
remains below 50 pF.

5.5 INPUT BYPASS CAPACITANCE
External capacitors (0.01 /JoF-0.1 /JoF) can be connected between the analog input pins, INO-IN7, and analog ground to
filter any noise caused by inductive pickup associated with
long input leads. It will not degrade the conversion accuracy.

5.2 INPUT RANGE

5.6 NOISE

The LM12(H)454/S's fully differential ADC and reference
voltage inputs generate a two's-complement output that is
found by using the equation below.

The leads to each of the analog multiplexer input pins
should be kept as short as possible. This will minimize input
noise and clock frequency coupling that can cause conversion errors. Input filtering can be used to reduce the effects
of the noise sources.

output code =

VIN+ - VIN- (4096) VREF+ - VREF-

'Iz

(12-bit)

5.7 POWER SUPPLIES

(S-bit)
output code = V VIN+ - ~IN- (256) - 'Iz
REF+ - REFRound up to the next integer value between -4096 to 4095
for 12-bit resolution and between - 256 to 255 for S-bit resolution if the result of the above equation is not a whole

Noise spikes on the VA + and Vo + supply lines can cause
conversion errors; the comparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. Low
inductance tantalum capacitors of 10 /JoF or greater paralleled with 0.1 /JoF monolithic ceramic capacitors are recom-

VIN = +13V to +15V
To lMI2(H)454/S VA+=+5V

2.43 kll
0.1%

62 kll
-Tantalum
·-Ceramic
TL/H/I1264-20

FIGURE 12. Low Drift Extremely Stable Reference Circuit
1-143

•

~ r-------------------------------------------------------------------~

Ln
"It

:::c

5.0 Analog Considerations (Continued)

:E

mended for supply bypassing. Separate bypass capacitors
should be used for the VA + and Vo + supplies and placed
as close as possible to these pins.
.

C"I

.....

-I

~
"It
C"I

.....

:E

-I
.....
"It
Ln
"It

:::c

C"I
.....

:E

-I
.....
"It
Ln
"It
C"I

.....

:E

-I

output are applied through a DB-3? connector on the rear
side of the board. Figure 13 shows that there are numerous
analog ground connections available on the DB-3? connector.
The voltage applied to VREF - and VREF + is selected using
two jumpers, JP1 and JP2. JP1 selects between the voltage
applied to the DB-37's pin 24 or GND and applies it to the
LM12(H)454/8's VREF- input. JP2 selects between the
LM12(H)454/8's internal reference output, VREFOUT, and
the voltage applied to the DB-37's pin 22 and applies it to
the LM12(H)454/8's VREF+ input.

5.& GROUNDING
The LM12(H)454/8's nominal high resolution performance
can be maximized through proper grounding techniques.
These include the use of separate analog and digital ground
planes. The digital ground plane is placed under all compo·
nents that handle digital signals, while the analog ground
plane is placed under all analog signal handling circuitry.
The digital and analog ground planes are connected at only
one pOint, the power supply ground. This greatly reduces
the occurrence of ground loops and noise.

TABLE III. LM12(H)454/& Evaluation/Interface
Board SW Dlp·& Switch SeHings
for Available I/O Memory Locations

It is recommended that stray capacitance between the ana·
log inputs or outputs (LM12(H)454: INO-IN3, MUXOUT+,
MUXOUT-, S/H IN+, S/H IN-; LM12(H)458: INO-IN?,
VREF+, and VREF-) be reduced by increasing the clear·
ance (+ 'I16th inch) between the analog signal and refer·
ence pins and the ground plane.

Hexldecimal
I/O Memory
Base Address
100
120
140
160
180
1AO
1CO
300
340
280
2AO

5.9 CLOCK SIGNAL LINE ISOLATION
The LM12(H)454/8's performance is optimized by routing
the analog input!outputand reference signal conductors
(pins 34-44) as far as possible from the conductor that carries the clock Signal to pin 23. Ground traces parallel to the
clock signal trace can be used on printed Circuit boards to
reduce clock Signal interference on the analog input! output
pins.

6.0 Application Circuits
6.1 PC EVALUATION/INTERFACE BOARD
Figure 13 is the schematic of an evaluation/interface board
designed to interface the LM12(H)454 or LM12(H)458 with
an XT or AT style computer. The board can be used to
develop both software and hardware. The board hardwires
the BW (Bus Width) pin to a logic high, selecting an 8-bit
wide databus. Therefore, it is designed for an 8-bit expansion slot on the computer's motherboard.

SWDlp·&
SW1
(SELO)

SW2
(SEL1)

SW3
(SEL2)

SW4
(SEL3)

ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON

ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF

ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
ON

ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF

The board allows the use of one of three Interrupt Request
(IRQ) lines IRQ2, IRQ3, and IRQ5. The individual IRQ line
can be selected using switches 5, 6, and? of SW DIP-8.
When using any of these three IRQs, the user needs to
ensure that there are no conflicts between the evaluation
board and any other boards attached to the computer's
motherboard.
Switches 1-4, along with address lines A5-A9 are used as
inputs to GAL16V8 Programmable Gate Array (U2). This device forms the interface between the computer's control
and address lines and generates the control signals used by
the LM12(H)454/8 for CS, WR, and RD. It also generates
the Signal that controls the data buffers. Several address
ranges within the computer's I/O memory map are available. Refer to Table III for the switch settings that gives the
desired I/O memory address range. Selection of an address
range must be done so that there are no conflicts between
the evaluation board and any other boards attached to the
computer's motherboard. The GAL equations are shown in
Figure 14. The GAL functional block diagram is shown in
Figure 15.

The circuit operates on a single + 5V supply derived from
the computer's + 12V supply using an LM340 regulator.
This greatly attenuates noise that may be present on the
computer's power supply lines. However, your application
may only need an LC filter.
Figure 13 also shows the recommended supply (VA + and
Vo+) and reference input (VREF+ and VREF-) bypassing.
The digital and analog supply pins can be connected together to the same supply voltage. However, they need separate, multiple bypass capacitors. Multiple capacitors on the
supply pins and the reference inputs ensures a low impedance bypass path over a wide frequency range.
All digital interface control signals (lOR, lOW, and AEN),
data lines (DBO-DB?), address lines (AO-A9), and IRQ (interrupt request) lines (IRQ2, IRQ3, and IRQ5) connections
are made through the motherboard slot connector. All analog Signals applied to, or received by, the input multiplexer
(INO-IN? for the LM12(H)458 and INO-IN3, MUXOUT+,
MUXOUT-, S/H IN+ and S/H IN- for the LM12(H)454),
VREF+, VREF-, VREFOUT, and the SYNC signal input!

Figures 16-:-19 show the layout of each layer in the 3-layer
evaluation/interface board plus the silk-screen layout showing parts placement. Figure 17 is the top or component side,
Figure 18 is the middle or ground plane layer, Figure 19 is
the circuit side, and Figure 16 is the parts layout.

1-144

6.0 Application Circuits (Continued)
Rear 0 Connector

Pl
DB37F

~
RN1E
+5VDC
+12VDC
ANALOG GND
eND

SW DIP-B

TLlH/11264-26
Note: The layout utilizes a split ground plane. The analog ground plane is placed under aU analog signals and U5 pins 1,34-44. The remaining signals and pins are
placed over the digital ground. The single pOint ground connection is at U6,' pin 2, and this is connected to the motherboard pin 81.

Parts List:
Y1

HC49U, 8 MHz crystal

C7, C21

D1

1N4002

C8, C12,C20

10 IJ.F, 35V, electrolytic

L1

33IJ.H

C13, C16

0.Q1 IJ.F, 50V, monolithic ceramic
1 IJ.F, 35V, tantalum

100 IJ.F, 25V, electrolytic

P1

DB37F; parallel connector"

C14, C18

R1

10 MO, 5%, 'J..W

C15, C17

100 IJ.F, 50V, ceramic disk

R2

2 kO, 5%, 'J..W

U1

MM74HCT244N

RN1

10 kO, 6 resistor SIP, 5%, 'laW

U2

GAL16V8-20LNC

JP1, JP2

HX3, 3-pin jumper

U3

MM74HCT245N

S1

SW DIP-8; 8 SPST switches

U4

MM74HCU04N

C1-3, C6, C9-11,
C19, C22
0.1 IJ.F, 50V, monolithic ceramic

U5

LM12(H)458CIV or LM12(H)454CIV

U6

LM340AT-5.0

C4

68 pF, 50V, ceramic disk

SK1

44-pin PLCC socket

C5

15 pF, 50V, ceramic disk

A1

LM12(H)458/4 Rev. D PC Board

FIGURE 13. Schematic and Parts List for the LM12(H)454/8 Evaluation/lnterface
Board for XT and AT Style Computers, Order Number LM12458EVAL

1-145

co
In

~

J:

....
('II

:E
....I

......
co
In
~

....
('II

:E
....I

......
~

In
~

J:

....
('II

::i
....I

......
~

In

~
('II

....

:E
....I

6.0 Application Circuits (Continued)
:1"0 Decode Linea
lo_A5
I
lo_A6
2
lo_A7
3
lo_AS
4
lo_A9
5
:Select Linea for Zone Decode
SEL0
6
SELl
7
SEL2
S
SEL3
9
Controls
:Ph~slcal 1.10
15
AEN
! lo_WR
II
Ilo_RO
13
:Ph~sical

ICS
IWR
!RO
!DBEN

Outputs
12

TLlH/11264-33

17
19
IS

: Intenedl ate Ter.s:
OEC0
16
FILT
14
Equations
:Decode of Select Lines:
SL0
ISEL2 & !SELI & ISEL0
ISEL2 & ISELI & SEL0
SLI
SL2
ISEL2 & SELl & ISELB
SL3
!SEL2 & SELl & SELB
SL4
SEL2 & !SELI & ISELB
SL5
SEL2 & !SELI & SELB
SL6
SEL2 & SELl & ISELB
SL7
SEL2 & SELl & SELB
:Decode of Address Lines:
ALB0
SLB & ! lo_A7
AL2B
SLI & Ilo_A7
AL4B
SL2 & Ilo_A7
ALSB
SL3 & lio_A7
ALSB
SL4 & lo_A7
ALA0
SL5 & lo_A7
ALC0
SL6 & lo_A7
AH01
AHB2
AH03

&
&
&
&
&
&
&

Ilo_A6
Ilo_AS
lo_AS
lo_AS
Ilo_AS
Ilo_A6
lo_A6

&
&
&
&
&
&
&

Ilo_A5
lo_A5
! I o_A5
lo_A5
Ilo_A5
lo_A5
Ilo_A5

!SEL3 & Ilo_A9 & lo_AS:
SEL3 & io_A9 & !lo_AS & lo_A? & !lo_A6:
SEL3 & lo_A9 & lo_A8 & !lo_A? & Ilo_A5:

:lnter.edlate Address Groups:
DECB
IAEN & (ALBB + AL2B + AL4B + AL6B + ALSB + ALAB + ALCB);
:DAS Chip Select Decode:
FILT
CS & ( lo_WR + lo_RD);
CS
( lo_WR + lo_RD) & DECB & ( AHBI + AHB2 + AH03);
DBEN
CS & DECB & ( lo_WR + lo_RD):
;Delayed Read" Write Decodes:
WR
lo_WR & FILT:
RD
lo_RD & FILT;
TL/H/11264-32

FIGURE 14. Logic Equations Used to Program the GAL 16V8

1-146

r-

s:
....

6.0 Application Circuits (Continued)

N

.j:Io

U!

.j:Io

......
r-

ADDRESS SELECTOR
Sel
Addre.s
Decode

SEL3

0
1
2
3
4

A9

5
6
7
8
9
A
B
C
D
E
F

A8
A7
A6
AS
AEN

s:
....
N

100
120
140
160
180
lAO
lCO

::::t:
.j:Io

NDBUFEN

U!
.j:Io

......
r-

NCS

s:
....
N

xxx

.j:Io

NRD

U!

300

CO

......

xxx
340

r-

s:
....

NWR

xxx
280
2AO

N

::t:
.j:Io

xxx
xxx

U!

CO

NIOR
NIOW

TUH/11264-27

FIGURE 15. GAL Functional Block Diagram

LM12458/4 EVAL BRO

Rl

REV 0
SER# _

© 1991

51

A31

C2

ulD

u2

D

C6

0

D 5 U4
R2~DC4 o C

D
~
Cl

-c=:J-

D

I2i41 National

~ Semiconductor
JP2

0

JPl

Ar::::::JB Ar::::::J B

C!OC:O

E~

YI

cloD

SW4

~

C13D +C15
C14DD

:~

Q

§

-

us

SW7
SW8

P1

+

DDD

C16C17C18

C3

u3D

a
D
LI

01

U6
C19

C20

DO
+

COMPo SIDE

A31

L...................I

OD

C21 C22

+

AGNO 19
IlGNO

-

A1
TL/H/11264-31

FIGURE 16. Silk-Screen Layout Showing Parts Placement on the LMI2(H)454/8 Evaluation/Interface Board

1·147

II

co

r-------------------~~------------~----------~------------------------------------~

it)

"Of'

::E:

C'I
....

:E
....I

......
co

it)

"Of'
C'I

....

:E
....I

......
"Of'

it)

6.0 Application Circuits (Continued)

•

.~

•

•

••• ••
• • ••

•

"Of'

::E:

....
C'I

:E
....I

~
it)

~
:E

....

....I

•

• •

TLlH111264-28

FIGURE' 17. LM12(H)454/8 Evaluation/Interface Board Component-5lde Layout Positive

1-148

r-----------------------------------------------------------------------------,
6.0 Application Circuits (Continued)

r

3:
.....
I\,)
01:0

U1

01:0
......

r

•
,. ,.
,"
..- •
••
,•,•
..- • •
• '•.-

eee

00'_-:

'.-,.'.

-,,..

'..-,I.

'..-:e

-,'.

e •..

...'
..-'
...
.....
.

,-

'.

1,.,-;'.

w

I\,)

••
•• •••
. •••
••
••
.!
••
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••
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..
-;e
•• '.•- ,• '•. : ••••
,..:.
••

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••
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-'

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••••••
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,'

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.
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.'';
-, .
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••
,- ,- •
• •

.'-.:'
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-

-'

•

•
-'

0

e'::e

-'

•

•

.,-,

•
II

•.. •
• "
II

GI

0
II
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C3

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3:
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01:0

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......
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3:
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::I:
01:0

U1

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CI)

,-

••
••
••
••

,,,-

,...:

.!
,,

~

U1

01:0
......

,-

,,'

.,-,

::I:

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•

QI ..-:

-'

-,'.
.,-,

'.

'.

•

.,-,

.,-~

3:
.....

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•
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• e'-'
•• •• ,•- ,•-e
•• •• ,,••..-- •••
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.. '.-: • ..
-'

III

0
0

.

-'

~

II

•
TL/H/11264-29

FIGURE 18. LM12(H)454/8 Evaluation/Interface Board Ground-Plane Layout Negative

1-149

6.0 Application Circuits (Continued)

•

••

.J..J. /
•

••• ••
• •

..,
Q

iii

•
..

•---_./

•

•••
••

••
•••
•••
•

......

:5
(.)
a::

U

831

TLlH/11264-30

FIGURE 19. LM12(H)454/B Evaluation/Interface Clrcult·Slde Layout Positive

1·150

t!lNational Semiconductor

LM12L454/LM12L458 12-Bit +
Sign Data Acquisition System with Self-Calibration
• Comparison time
("watchdog" mode)
.ILE

General Description
The LM12L454 and LM12L458 are highly integrated 3.3V
Data Acquisition Systems. They combine a fully-differential
self-calibrating (correcting linearity and zero errors) 13-bit
(12-bit + sign) analog-to-digital converter (ADC) and sample-and-hold (StH) with extensive analog functions and digital functionality. Up to 32 consecutive conversions, using
two's complement format, can be stored in an internal
32-word (16-bit wide) FIFO data buffer. An internal 8-word
RAM can store the conversion sequence for up to eight
acquisitions through the LM12L458's eight-input multiplexer. The LM12L454 has a four-channel multiplexer, a differential multiplexer output, and a differential StH input. The
LM12L454 and LM12L458 can also operate with 8-bit +
sign resolution and in a supervisory "watchdog" mode that
compares an input signal against two programmable limits.
Programmable acquisition times and conversion rates are
possible through the use of internal clock-driven timers.

•
•
•
•

Features
.. Three operating modes: 12-bit + sign, 8-bit + sign,
and "watchdog"
• Single-ended or differential inputs
• Built-in Sample-and-Hold
• Instruction RAM and event sequencer
III 8-channel (LM12L458), 4-channel (LM12L454)
multiplexer
.. 32-word conversion FIFO
• Programmable acquisition times and conversion rates
• Self-calibration and diagnostic mode
• 8- or 16-bit wide databus microprocessor or DSP
interface
• CMOS compatible 1/0

All registers, RAM, and FIFO are directly addressable
through the high speed microprocessor interface to either
an 8-bit or 16-bit databus. The LM12L454 and LM12L458
include a direct memory access (DMA) interface for highspeed conversion data transfer.

Key Specifications (fCLK =
•
•
•
•

Resolution
13-bit conversion time
9-bit conversion time
13-bit Through-put rate

12-bit

+

6 MHz)
sign or 8-bit

VIN range
Power dissipation
Stand-by mode
Single supply

Applications
• Data Logging
.. Process Control
• Energy Management
III Medical Instrumentation

+

sign
7.3 ".S
3.5 ".s
106k samplests (min)

Connection Diagram

.,
z

+

.

t:;

z

b~ ~

~~~~~r;~r;r;A~
/

6

5

"

3

2

1 ·44 43 42 41 40

tJ IN5(t.lUXOUT+)'

C7
06 C B

39

D7C 9

37 DIN3

05

38

DBC 10

D9C"
Vo+[ 12
DIOC 13

IN.4(t-lUXOUT-)'

(LM12L454)

35 DINI
34 ~INO

"DONO
32PONARO

C 15

31

DI3L 16

30

C 17

29

D14

P

36 PlN2

LM12L458

Dl1C14
012

1.8".s (max)
±1 LSB (max)
GND to VA+
15 mW (max)
5".W (typ)
3V to 5.5V

DiNT
PBW

b

SYNC

18 19 20 21 22 23 204 2S 26 27 28

TL/H/11711-1

'Pin names in () apply to the LM12L454.

Order Number LM12L454CIVor LM12L458CIV
See NS Package Number V44A

1-151

Functional Diagrams

LM12L454
S/H IN+ - - - - - - - - - - - - ,
S/H IN- - - - - - - - - - - ,
MUXOUT+

MUXOUT-

+----------.
+---------.

vl

SYNC+---------------~

'It,

GNO

! ! !

CLK---------------1~~::::~~LJL---,
iNT
OMARQ

SELECT

f1/I

00

01

02 D5 04

os

D6 07 08 09 010011012013014015

(L58)

II<

fffff

CONTROL LOGIC

ffff

Cs Rii ViR

AO A1 A2 A3 A4

I

ALE

(MSB)
TLlH/11711-2

LM12L458
INO
IN1

IN2
IN3

IN4
INS

IN6
IN7 ---.,i.-'"""lI~""'"

SYNC

vl

+----------------+1

Vil

GNO

! ! !

CLK---~~::::::::::::::::::~------~~--l
iNT
OMARQ

SELECT

f1/I

DO 01 02 03 D4

os

06 07 08 09 010 011 012 013 014 015

(LSB)

fffff

II<

CONTROL LOGIC

ffff

Cs Rii ViR

AO A1 A2 A3 A4

I

ALE

(MSB)
TLlH/11711-3

Ordering Information
Guaranteed
Clock Freq (min)

Guaranteed
Linearity Error (max)

Order
Part Number

SeeNS
Package Number

6MHz

±1.0 LSB

LM12L454CIV
LM12L45BCIV

V44A
V44A

1-152

Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VA + and Vo+)
Voltage at Input and Output Pins
except INO-IN3 (LM12L454)
and INO-IN7 (LM12L45B)

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

6.0V
-0.3V to V+

-i-

Operating Ratings

(Notes 1, 2)
Temperature Range
(Tmin ,;; TA';; Tmax)
-40·C';; TA';; B5·C
LM12L454CIVILM12L45BCIV

0.3V

Voltage at Analog Inputs INO-IN3 (LM12L454)
GND - 5VtoV+ + 5V
and INO-IN7 (LM12L45B)

Package Input Current (Note 3)
Power.Dissipation (TA = 25·C)
V Package (Note 4)
Storage Temperature
Lead Temperature
V Package, Infrared, 15 sec.
ESD Susceptibility (Note 5)

Supply Voltage
3.0Vto 5.5V
';;100 mV

VA+,VO+

300mV
±5mA
±20mA

IVA+ - vo+1
Input Current at Any Pin (Note 3)

IVA+ - vo+1
VIN+ Input Range
VIN- Input Range

B75mW
-65·Cto +150·C

GND,;; VIN+ ,;; VA+
GND,;; VIN- ,;; VA+

VREF + Input Voltage

1V,;; VREF+ ,;; VA+

VREF- Input Voltage

OV';; VREF- ,;; VREF+ - 1V
1V,;; VREF';; VA+

VREF+ - VREFVREF Common Mode
Range (Note 16)

+300·C
1.5 kV

0.1 VA + ,;; VREFCM ,;; 0.6 VA +

Converter Characteristics
The following specifications apply to the LM12L454 and LM12L45B for VA + = Vo + = 3.3V, VREF + = 2.5V, VREF- = OV,
12-bit + sign conversion mode, fClK = 6.0 MHz, Rs = 25n, source impedance for VREF+ and VREF- ,;; 25n, fully-differential
input with .fixed· 1.25V common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25·C. (Notes 6,7, B, and 9)
Symbol

Conditions

Parameter

Typical
(Note 10)

Limits
(Note·11)

Unit
(Limit)

±1/2

±1

LSB(max)

ILE

Positive and Negative Integral
Linearity Error

After Auto-Cal (Notes 12, 17)

TUE

Total Unac:ljusted Error

After Auto-Cal (Note 12)

Resolution with No Missing Codes

After Auto-Cal (Note 12)

13

Bits (max)

Differential Non-Linearity

After Auto-Cal

±1

LSB (max)

DNL

ILE

TUE;

DNL

±1

LSB

Zero Error

After Auto-Cal (Notes 13, 17)

±1/4

±1

LSB(max)

Positive f,ull-Scale Error

After Auto-Cal (Notes 12, 17)

±1/2

±3

LSB (max)

Negative Full-Scale Error

After Auto-Cal (Notes 12, 17)

±1/2

±3

.LSB (max)

DC Common Mode Error

(Note 14)

±2

±4

LSB (max)

±1/2

LSB(max)

±3/4

LSB (max)

B-Bit + Sign and "Watchdog" Mode
Resolution with No Missing Codes '

9

Bits (max)

B-Bit + Sign and "Watchdog" Mode
Differential Non-Linearity

±1

LSB (max)

±1/2

LSB (max)

±1/2

LSB (max)

B-Bit + Sign and "Watchdog"
Mode Positive and Negative
Integral Linearity Error

..

B-Bit + Sign and "Watchdog" Mode
Total Unadjusted Error

B-Bit + Sign and "Watchdog" Mode
Z!lro Error

(Note 12)

After Auto-Zero

After Auto-Zero

B-Bit + Sign and "Watchdog" Positive
and Negative Full-Scale Error

1-153

±1/2

Converter Characteristics
The following specifications apply to the LM12L454 and LM12L458 for VA + = Vo+ = 3.3V, VREF+ = 2.5V, VREF- = OV,
12-bit + sign conversion mode, fCLK = 6.0 MHz, RS = 250, source impedance for VREF+ and VREF- :s; 250, fully-differential
input with fixed 1.25V common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface UIDits
apply for T A = T J = TMIN to TMAX; all other limits TA = TJ = 25°C. (Notes 6, 7, 8, and 9) (Continued)
Symbol

Parameter

Typical

Conditions

(Note 10)

Limits
(Note 11)

8-Bit + Sign and "Watchdog" Mode
DC Common Mode Error

±1/8

LSB

Multiplexer Channel-ta-Channel
Matching

±0.05

LSB

aND

Non-Inverting Input Range

VIN+

Unit
(Limit)

V (min)
V (max)

VA+

aND

Inverting Input Range

VINVIN+ - VIN-

Differential Input Voltage Range

VIN+ - VIN2

Common Mode Input Voltage Range

PSS

Power Supply
Sensitivity
(Note 15)

VA+

V (min)
V (max)

-VA+
VA+

V (min)
V (max)

aND

V (min)
V (max)

VA+
Zero Error
Full-Scale Error
Linearity Error

VA+ =Vo+ = 3.3V ±100/0
VREF+ = 2.5V, VREF- = GND

±0.2
±0.4
±0.2

±1.75
±2

LSB(max)
LSB(max)
LSB

CREF

VREF+/VREF-lnputCapacHance

85

pF

CIN·

Selected Multiplexer Channel Input
CapaCitance

75

pF

Converter AC Characteristics
The following specifications apply to the LM12L454 and LM12L458 for VA + = Vo+ = 3.3V, VREF+ = 2.5V, VREF- = OV,
12-bit + sign conversion mode, fCLK = 6.0 MHz, Rs = 250, source impedance for VREF+ and VREF- :s; 250, fully-differential
. input with fixed 1.25V common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface II......
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. (Notes 6,7,8, and 9)
Symbol

Parameter

Conditions

Clock Duty Cycle

tc

tA

tz
teAL

Conversion Time

Limits
(Note 11)

UnIt
(Limit)

40
60

0/0
0/0 (min)
0/0 (max)

50

13-Bit Resolution,
Sequencer State S5 (Figure 11)

44 (tclK)

44 (tcL.K)

+ SO ne

(max)

9-Bit Resolution,
Sequencer State S5 (F/{/ure 11)

21 (tcuu

21 <'eLK)

+ 50.118

(max)

Sequencer State S7 (F/{/ure 11)
Built-in minimum for 13-Bits

9 (tclK>

9 (tcL.K)

+ SO ne

(max)

Built-in minimum for 9-Bits and
"WatChdog" mode

2 (tclK>

2 ('eLK>

+ SO ne

(max)

Auto-Zero Time

Sequencer State S2 (Figure 11)

76 (tcLK>

Full Calibration Time

Sequencer State S2 (Figure 11) 4944 (tclK>

Acquisition Time

Throughput Rate
(Note 18)
two

Typical
(Note 10)

107

"Watchdog" Mode Comparison Time Sequencer States S6, S4,
and S5 (Figure 11)

11 (tclK)

+ 50 ne
4944 ('eLK) + SO 118
76 ('eLK>

100
11 ('eLK)

+ 50 ne

:

(max)

(max)
kHz
(min)
(max)

tpu

Power-Up Time

10

ms

twu

Wake-Up Time

10

ms

1-154

r-

DC Characteristics The following specifications apply to the LM12L454 and LM12L458 for VA+ = Vo+ = 3.3V,

VREF+ = 2.5V, VREF- = OV, felK = 6.0 MHz and minimum acquisition time unless otherwise specified. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. (Notes 6,7, and 8)

Symbol
10+
IA+

1ST

Parameter

Conditions

Vo + Supply Current

cs= "1"
LM12L454/8

VA + Supply Current
Stand-By Supply Current (10 +

Multiplexer ON-Channel Leakage Current

Multiplexer OFF-Channel Leakage Current

RON

Multiplexer ON-Resistance

0.4

1.0

Unit
(Limit)
mA(max)
mA(max)

3.5

1.5
30

4.5

",A (max)
",A (max)

ON-Channel = 3.6V
OFF-Channel = OV

0.1

0.3

/LA (max)

ON-Channel = OV
OFF-Channel = 3.6V

0.1

0.3

",A (max)

ON-Channel = 3.6V
OFF-Channel = OV

0.1

0.3

/LA (max)

ON-Channel = OV
OFF-Channel = 3.6V

0.1

0.3

",A (max)

850
1300
830

1500
2000
1500

!l(max)
!l(max)
!l(max)

± 1.0%
± 1.0%
± 1.0%

±3.0%
±3.0%
±3.0%

(max)
(max)
(max)

VA+ = 3.6V

VA+ = 3.6V

LM12L454

= 3.3V
= 1.65V
= OV

LM12L454

VIN
VIN
VIN

= 3.3V
= 1.65V
= OV

1-155

U1

olio
.....
r-

3:
.....
N

r~

U1

2.25

Power-Down Mode Selected
Clock Stopped
6 MHz Clock

VIN
VIN
VIN
Multiplexer Channel-to-Channel
RON matching

Limits
(Note 11)

N

!;

co

cs= "1"
LM12L454/8

+ IA +)

Typical
(Note 10)

3:
.....

Digital Characteristics

The following specifications apply to the LM12L454 and LM12L458 for VA + = Vo-l: ;,,;
3;3V, unless otherwise specified. Boldface limits apply for T A = T J = TMIN to TMAX; all other limits TA' = TJ = 25°C.
(Notes 6, 7, and 8)
' '
"
,
Typical
Limits
Unit
Symbol
Parameter
Conditions
(Note 10)
(Note 11)
(Limit)

..

VIN(l)

Logical "1" Input Voltage

VA+ = Vo+ = 3.6V

VIN(O)

Logical "0" Input Voltage

VA+ = Vo+ = 3.0V
ALE, Pin 22

IIN(l)

Logical "1" Input Current

IIN(O)

Logical. "0" Input Currerit

' VIN = 3:3V
VIN = OV
"

CIN

00-015 Input Capacitance

VOUT(l)

Logical "1" Output Voltage

VOUT(O)

Logical "0" Output Voltage

TRI-STATE® Output Leakage Current

lOUT

., 2.0

If (max)"

0:005

1.0
2.0

!LA (max)

-0.005

-1.0
-2.0

/J-A(max)
,:,

6
VA+ = Vo+ ,= 3.0V
lOUT = -360/J-A
lOUT = -10/J-A,

2.4
2.85

VA+ = Vo+ = 3.0V
lOUT = 1.6 mA
lOUT = 10 /J-A
VOUT = OV
VOUT = 3.3V

' V (min)

0.7
0.6,.-

' 0.4
0.1
-0.Q1
0.01

-3.0
3.0

.

pF
V (min)
V (min)
V (max)
/J-A(max)
/J-A(max)

Digital Timing Characteristics

The following specifications apply to the LM12L454 and LM12L458 for VA 'I- = Vo+ = 3.3V, tr = tf = 3 ns, and CL = 100 pI"
on data 110, lNT and DMARQ lines unless otherwise specified. Boldface limits apply for T A = T J = TMIN to TMAX; all
other limits TA = TJ == 25°C. (Notes 6,7, and 8)
,
Symbol
(See Figures
8a, Bb, and 8e}
1,3

Parameter

Conditions

Typical
(Note 10)

CS or Address Valid to ALE Low

• Unit
(Umlt)

4,0

ns(min)

CS or Address Valid to ALE Low
Hold Time

20

ns(min)

Set-UpTime
2,4

Limits " '.
(Note H)

5

ALE Pulse Width

45

ns(min)

6

RD High to Next ALE High

35

ns(min}

7

ALE Low to RD Low

20

ns(min)

8

RD Pulse Width

100

ns(min)

9

RD High to Next RD or WR Low

100

ns(min)

10

ALE Low to WR Low

20

ns(min)

11

WR Pulse Width

60

ns(min)

12

WR' High to Next ALE High

75

ns(min)

13

WR High to Next RD or WR Low

140

ns(min)

14

Data Valid to WR High Set-Up Time

40

ns(min)

15

Data Valid to WR High Hold Time

30

ns(min)

16

RD Low to Data Bus Out of TRI-STATE

30

10
70

ns(min)
ns(max)

17

RD High to TRI-STATE

30

10
110

ns(min)
ns(max)

18

RD Low to Data Valid (Access Time)

10

ns(min)
ns(max)

RL = 1 kO

30

95
1-156

Digital Timing Characteristics
The following specifications apply to the LM12L454 and LM12L458 for VA + = VD + = 3.3V, tr = tf = 3 ns, and CL = 100 pF
on data 110, INT and DMARQ lines unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all
other limits TA = TJ = 25'C. (Notes 6,7, and 8) (Continued)
Symbol
(See Figures
8a,8b, and 8e)

Parameter

20

Limits
(Note 11)

Unit
(Limit)

Address Valid or CS Low to RD Low

20

ns(min)

21

Address Valid or CS Low to WR Low

20

ns(min)

19

Address Invalid
from RD or WR High

10

ns(min)

22

INT High from RD Low

30

10
60

ns(min)
ns(max)

23

DMARQ Low from RD Low

30

10
60

ns(min)
ns (max)

Conditions

Typical
(Note 10)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > 01A+ or Vo +», the current at that pin should be limited to
5 rnA. The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current of 5 rnA, to simultaneously exceed the power
supply voltages.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), 0JA (package
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax ~ (TJmax - TA)I
G>JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJrnax = 1SO"C, and the typical thermal resistance (E>JA) of the
LM12L454 and LM12L458 in the V package, when board mounted, is 47'C/W.
Note 5: Human body model, 100 pF discharged through a 1.5 kfl resistor.
Note 6: Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above VA + or 5V below
GND will not damage the LM12L454 or the LM12L458. However, errors in the A/D conversion can occur if these diodes are forward biased by more than 100 mV.
As an example, if VA + is 3.0 Voc. full-scale input voltage must be ~ 3.1 VOC to ensure accurate conversions.

VA+

r-------,
-l-

1-+'JoJ'Iv--....~I--+

,,
L

-~

TO INTERNAL
CIRCUITRY

"fr.,

________ _

GND

TLlH/11711-4

Note 7: VA+ and Vo+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V+ pin to assure
conversion/comparison accuracy.
Note 8: Accuracy is guaranteed when operating at fCLK

~

6 MHz.

Note 9: With the test condition for VREF ~ VREF+ - VREF- given as +2.5V, the 12·bit LSB is 305 p.V and the 8·bitI"Watchdog" LSB is 4.88 mY.
Note 10: Typicals are at TA

= 25°C and represent most likely parametriC norm.

Note 11: Limits are guaranteed to National's AOQL (Average Output Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive fullscale and zero. For negative integral linearity error the straight line passes through negative full-scale and zero. (See Figures 5b and 50).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between -1 to 0 and 0 to + 1 (see Figure 6).
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from OV to 2.5V. The measured value is referred to the resulting
output value when the inputs are driven with a 1.2SV signal.
Note 15: Power Supply Sensitivity is measured after Auto·Zero and/or Auto-Calibration cycle has been completed with VA + and Vo+ at the specified extremes.
Note 16: VREFCM (Reference Voltage Common Mode Range) is defined as 0IREF+ + VREF-)/2.
Note 17: The LM12L4S4/S's self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in
a repeatability uncertainty of ± 0.1 0 LSB.
Note 18: The Throughput Rate is for a single instruction repeated continuously. Sequencer states 0 (1 clock cycle), 1 (1 clock cycle), 7 (9 clock cycles) and 5 (44
clock cycles) are used (see Figure 11). One additional clock cycle is used to read the conversion result stored in the FIFO, for a total of 56 clock cycles per
conversion. The Throughput Rate is fCLK (MHz)/N, where N is the number of clock cycles/conversion.

1-157

co

~
C'II

....

Electrical Characteristics

::::iE

...I

~
II)

Y'A

~

....C'II

::::iE

...I

,,

>VREF

,

,

",fb,'

YREF

~
I
z

,,

,
,,

,
,,

,,~,
,

,,

,
,,

,,

,,

,
,,

,
,,

,,

,

,,

,
,,

,
,,

,

,,

,

1:>'

2

,
,,

,,

,
,,

,
,,

,,

,
,,

,,

,
,,

,,

,
,,

,,

,,

,
,,

,
,,

,,

,,

,
,,

,

= VREF+ - VREF= VIN+ - VIN-

VREF
VIN

GND

S;

VIN+

S;

VA+

GND

S;

VIN-

S;

VA+

,
,,
,
,

,'~ro

,
,,

,,

,
,,

,
,,

,'x~~
,,

YREF

2
V1N+(V)
TUH/11711-5

FIGURE 1. The General Case of Output Digital Code vs the Operating Input Voltage Range

~
I

z

>-

,
,,

,,

,
,,

,,

,
,,

,

,
,,

.,,

,,

,

,
,,

,
,,

,
,,

,,

,,

,

,

,
,,

,
,,

,,

,,

,

,
,,

,

,

,
,,

,
,,

,,

,,

,

,
,,

,
,,

,
,,

,,

,
,,

,
,,

,,

,

VREF+ - VREFVIN

= VIN+

= 2.5V

- VIN-

GND" VIN+

S;

VA+

GND

S;

VA+

S;

VIN-

,

4

TL/H/11711-6

FIGURE 2. Specific Case of Output Digital Code vs the Operating Input Voltage Range for VREF = 2.5V

1-158

Electrical Characteristics (Continued)

V'
A

~

.L

0.6 VA' - 0.5V

w

>rt:.

TL/H/11711-7

FIGURE 3. The General Case of the VREF Operating Range

VREF
VA'

= VREF'
= 3.3V

- VREF-

~

I

I&.

w

>rt:.
1.48

0.66

TUH/11711-8

FIGURE 4. The Specific Case of the VREF Operating Range for VA + = 3.3V

1-159

Electrical Characteristics (Continued)
0,1111,1111, 1111( +4095)
0,1111,1111,111 O( +4094)
"

~E

rULL -SCALE
TRANSITION

",

///,/'
0,0000,0000,00 10(+2)

1(+ 1) _~:j....E===:2Z::E~RO~TR~A~N~SI~TI~ON~_ _ _ _ _ _ _-l
f - - - - - - - -0,0000,0000,000
0,0000,0000,0000(0)

=

VREr VREr+ - VRErVIN = VIN + - VIN _
GNO ::s; VIN + ::s; VA+
GNO ::s; VIN _ ::s; VA+
1,0000,0000,000 1 (-4095)
1,0000,0000,0000 (-4096)
ANALOG INPUT VOLTAGE (VIN )
TLlH/11711-9

F'IGURE 5a. Transfer Characteristic

"l2LSB
+8 LSB

POSITIVE
rULL-SCALE
ERROR

+4095
NEGATIVE
rULL-SCALE
ERROR

-4LSB

-8 Lse
ERROR

-l2LSe
OUTPUT CODE
(from -4096 to +4095)
TL/H/11711-10

FIGURE 5b. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles

1-160

Electrical Characteristics (Continued)

+3 LSB
+2LSB
ZERO
ERROR

+1 LSB

NEGATIVE
FULL-SCALE
ERROR

POSITIVE
INTEGRAL
LINEARITY,
ERROR

POSITIVE
FULL-SCALE
ERROR

"'"

+4095

-1 LSB
-2LSB
-3 LSB
OUTPUT COOE

(from -4096 to +4095)
TL/H/11711-11

FIGURE 5c. Simplified Error Curve vs Output Code after Auto-Calibration Cycle

+2

+1

....

8'"

0

I-

::>

IL
I-

::>

o

-I

~ OFFSET VOLTAGE

-1

-2
ANALOG INPUT VOLTAGE (VIN )
TL/H/11711-12

FIGURE 6. Offset or Zero Error Voltage

1-161

Typical Performance Characteristics

The following curves apply for 12-bit + sign mode after auto-calibration with VA + = Vo + = a.av, VREF + = 2.5V,
VREF - = OV, TA = 25°C, and felK = 6 MHz unless otherwise specified. The performance for S-bit + sign and "watchdog"
modes is equal to or better than shown. (Note 9)
Linearity Error Change
va Clock Frequency
-

...d

0.14

~

0.12

0.04

~

0.10

~

I
I
'\..

0.04

- 'V

--

0.02
-0.02
-0.04
I

I

-0.04

~

L

o

-0.02

i

I

0.30
0.25
0.20
0.15

~

/

0.10

~

0.05

l!i

0

=
~

-0.05
-0.10
-0.15
~ -0.20
:::; -0.25
-0.30

!

----

/
/

~

i

/

~

/

....-

~

~
~

3.0

3.3

3••

0.15

~

0.4

I

0.6

0.10

0.2 1\

~
~

~
~

~

L

-0.2

n

-0.10
-0.15

I
-0.6 II

I

1
1

1.5

0.9

0.6

I>
f

~

-0.2

2.5

r---...

3.3

/'

~

:'i
13

:-V

-0.05

~

/

""

TEMPERATURE (Oc)

NEGATIVE FULL-SCALE

I

0.14
0.12

i

O.OS

70

S5

I
10

25

40

--

55 70

85

0.06
0.04
0.02

~

-0.02

~
~

-0.06

~

3.3

3.6

'\

"

-0.04

-

\.

-O.OS
-0.10

.....

-0.12
1

3.9

CLOCK FREQUENCY (MHz)

Zero Error Change
VB Supply Voltage

...d

~

0.16

:'i
13

" ."

\

-0.3

-0.'
-0,5
-40 -25 -5

-0.14

5

\

0.04
0.02

0.9

-0.05

~ -0.10

1\
'\..

'\... V
1.5

"'"

/

~

\

0.06

.......

0.05

~

\

0.10

0.10

~

\

o
25 40 55

,)

-0.2

P'

..........

0.15

0.1S

~

.......

-0.1

Zero Error Change
VB Reference Voltage

~

10

r--.

SUPPLY VOLTAGE (V)

/

-0.15
-40 -25 -5

-

~

/

1
3.0

...d

0.20

0.05

0

I
POSITIVE FULL-SCALE

Zero Error Change
VB Clock Frequency

...........
2.7

~

3.3

TEMPERATURE (OC)

NEGATIVE FULL-SCALE

-1.0

.;'

0.10

-0.10

7

"J\.

-o.S

0.15

~

~

/1\

/

Zero Error Change
va Temperature

i

~

~

r-- .\
-0.4

REFERENCE VOLTAGE (v)

~

e;

6

..,- POSITIVE FULL-SCALE

j
-0.•
~

I

2.1

~

:il

~

5

0.2
0.0

I

0.2
0.1

1
1

2

0.3

co
z

"

1

0.5
0.4

13

POSITIVE FULL-SCALE

1/

0.4

e;

I

..

~

\if
Y I\.

1

...

d

Full-SCale Error
va Supply Voltage

~

NEGATIVE FULL-SCALE

-0.4

NEGATIVE

I~ ~

/

-0.05

:il

1

-O.S

~

1

J FULL-SCALE 'I ;;;;;;;;

POSITIVE FULL-SCALE

I

...d

I

2.5

2.0

Full-Scale Error Change
vs Temperature

O.S

POSITIVE FULL-SCALE

""'-

~

1.5

Full-Scale Error Change
vs Clock Frequency

0.05

-0.20

0.9

25 40 55 70 S5

CLOCK FREQUENCY (MHz)

I

I

I"\

-0.2

REFERENCE VOLT AGE (V)

H--,I...

Full-Scale Error Change
vs Reference Voltage

...d

'-V

I r'-....

TEWPERATURE (Oc)

SUPPLY VOLTAGE (V)

O.S

0.0

-0.3
10

0.20

3.9

0.1

:::;

-0.25

2.7

0.2

~
>- -0.1
~

-0.10
-40 -25 -5

...d

'- l -

~

-O.OS

Linearity Error Change
va Supply Voltage

d.

~
!

CLOCK FREQUENCY (WHz)

'iii'

0.3

~

II

-0.06

~
:::;

...d

0.02

~

:: o.os

Linearity Error Change
va Reference Voltage

Linearity Error Change
va Temperature

0.16

2.1

2.5

REFERENCE VOLTAGE (V)

i

-0.15

~

-0.20

'\

'\.
\.

-0.25
3.3

2.7

3.0

3.3

3.6

3.9

SUPPLY VOLTAGE (V)

TL/H/117"-'3

1-162

Typical Performance Characteristics

The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. The performance for 8-bit
sign and "watchdog" modes is equal to or better than shown. (Note 9) (Continued)

'"

3.0

Analog Supply Current
vs Temperature
r-r--.-,.-,---r--r-r--.

2.5

H-t-t-"""'::--t---t--::::Io-I

.5.
...

~

a~
~

. ~., ~~::::r:::
~!-

~~~"'~~.

VA'

= 3.3V

i

1.5

I

1.0
-40 -25 -5

,-,.-,--,----r-,-,.-,

i

0.5

f-+-+-+-+-t-f7'''1

0.4

f-+-+-+-+V~I"'/=-t-l

~

0.31-+--+-+A-I-+---1

~

2.0 r~~ o~

Ol

~

I

Digital Supply Current
vs Clock Frequency

0.6

.5.

~~

0.2

f-t-:..tVL-r-++-t-l

V

~a 0.1 17"+--+-+--+-1-+---1
O~~~~~-~~~

10

25 40 55 70 85

TEWPERATURE (Oc)

1234567
CLOCK FREQUENCY (WHz)

0.50

+

Digital Supply Current
vs Temperature
r-r--.-,.-,---r--r-r--.

~

t:t::j::::.l==t=;;f'-I'-t-1
~u 0.40 t=:t:::t:::;j;;:::t=1'--r--r1
=

.5.

~

i

0.45

0.35

ttj::j::t:t==r11

0.30
0.25 L......l..-..I.......l---'----'--'-----'--'
-40 -25 -5 10 25 40 55 70 85
TEMPERATURE (Oc)

TUH/11711-14

•

1-163

CD ,---------------------------------------------------------------------------------,

!i
C'II
....
:&

Test Circuits and Waveforms
V'

V'

....I

;;:

II)

::s

.Ro
D~T~

Ro

C'II
....
:&

to

V'

Rl = 1 kG
OUTPUT
Ic;.=IDD Pr

TL/H/11711-16
TLlH/11711-15

....I

V'

V'

Ro

"'- = 1 kn

to

V'

DATA
OUTPUT
TLlH/11711-18

TLlH/11711-17

FIGURE 7. TRI-STATE Test Circuits and Waveforms

Timing Diagrams
VA +

=

Vo +

= + 3.3V, tR =

=

tF

~

3 ns, CL

=

100 pF for the INT, DMARQ, DO-D15 outputs.

~,'~

AO-A4~

~!.==::::.,~.==:.~:
I

"

Cs

I"

~~3--_'------J~~----------------J/
I
I

it

!

II

"

I

"

1

Ro

c~~~

;.----)J-------.......,

DO-DI5 - { ' - -____

I,I

TL/H/11711-19

1, 3:

CS or Address valid to ALE

low set·up time.

11: WR pulse width

2, 4: CS or Address valid to ALE low hold time.
5: ALE pulse width

12: WR high to next ALE high
13: WR high to next WR or RD low

6: AD high to next ALE high

14: Data valid to WR high set-up time

7: ALE low to

AD low

15: Data valid to WR high hold time

8: RD pulse width
9: RD high to next RD or WR low

16: RD low to data bus out of TRI·STATE
17: RD high to TRI-STATE
18: RD low to data valid (access time)

10: ALE low to WR low
1-164

r-----------------------------------------------------------------------------~r

s:
....
N

Timing Diagrams
VA +

= VD+ =

+3.3V, tR

= tF = 3 ns, CL = 100 pF for the INT, DMARa, DO-D15 outputs. (Continued)

)
~
/

AO-A4-{

,
,"

Cs

.~[

",

20

TI
,, ,,
,
:

I

,,

I.

,

II,
,"

20

"

\,,

iiii

II

•

00-015

:.

21
II
II

\,,

iii

""[

:.

CYCLE

I

~

UI
CD

17

~

VALID DATA

,

I'

11

.:

21

N

,,

,"

II

I,

16

r

....s:

I,:.~--------~--------~~-.
I,

,

18

:.

CYCLE

!;
UI
0l:Io
......

1,
I'

14

00-015

X

13
15

11.111

jl

"

VALID DATA

X

TLlH/11711-20

FIGURE 8b. Non-Multiplexed Data Bus (ALE = 1)
8: Ai) pulse width

16: RD low to data bus out of TRI·STATE

9: Ai) high to next RD or WR low

17: RD high to TRI·STATE
18: RD low to data valid (access time)
19: Address invalid from RD or WR high (hold time)

11: WR pulse width
13: WR high to next WR or RD low

WR high set·up time
15: Data valid to WR high hold time
14: Data valid to

21: CS low or address valid to WR low

_---.lr;

+3.3V, tR
DIIARQ

20: CS low or address valid to RD low

= tF = 3 ns, CL = 100 pF for the INT, DMARa, DO-D15 outputs.

\

•

,,~--------------,
, ,'
,,~'
,
jl

22

,
.:

I

~\"-----Jr1---J-·
TL/H/11711-21

FIGURE 8e. Interrupt and DMARQ
22: INT high from Ai) low
23: DMARa low from RD low

1·165

•

co

II)

r------------------------------------------------------------------------------------------,

"0'

Pin Description

.....
~

VA +
Vo+

.....
N

~

II)

"0'

.....
N

.....
::IE
.....

These are the analog and digital supply voltage
pins. The LM12L454/8's supply voltage operating
range is +3.0V to +5.5V. Accuracy is guaranteed
only if VA + and Vo + are connected to the same
power supply. Each pin should have a parallel
combination of 10 p.F (electrolytic or tantalum) and
0.1 p.F (ceramic) bypass capacitors connected between it and ground .
DO-D15 The internal data input/output TRI-STATE buffers
are connected to these pins. These buffers are designed to drive capacitive loads of 100 pF or less.
External buffers are necessary for driving higher
load capacitances. These pins allows the user a
means of instruction input and data output. With a
logic high applied to the BW pin, data lines D8D15 are placed in a high impedance state and data
lines DO-D7 are used for instruction input and
data output when the LM12L454/8 is connected to
an 8-bit wide data bus. A logic low on the BW pin
allows the "LM12L454/8 to exchange information
over a 16-bit wide data bus.
AD
This is the input for the active low READ bus control signal. The data input/ output TRI-STATE buffers, as selected by the logic signal applied to the
BW pin, are enabled when RD and CS are both
low. This allows the LM12L454/8 to transmit information onto the databus.
WR

CS

ALE

CLK

BW

This is the input for the active low WRITE bus control signal. The data input/output TRI-STATE buffers, as selected by the logic signal applied to the
BW pin, are enabled when WR and CS are both
low. This allows the LM12L454/8 to receive information from the databus.
This is the input for the active low Chip Select control signal. A logic low should be applied to this pin
only during a READ or WRITE access to the
LM12L454/8. The internal clocking is halted and
conversion stops while Chip Select is low. Conversion resumes when the Chip Select input signal
returns high.
This is the Address Latch Enable input. It is used in
systems containing a multiplexed databus. When
ALE is asserted high, the LM12L454/8 accepts
information on the databus as a valid address. A
high-to-low transition will latch the address data on
AO-A4 and the logic state on the CS input. Any
changes on AO-A4 and CS while ALE is low will
not affect the LM12L454/8. See Figure 8a. When
a non-multiplexed bus is used, ALE is continuously
asserted high. See Figure 8b.
This is the external clock input pin. The
LM12L454/8 operates with an input clock frequency in the range of 0.05 MHz to 8 MHz.

the internal S/H to hold the input signal. The
next rising clock edge either starts a conversion or makes a comparison to a programmable limit depending on which function is requested by a programming instruction. This pin
will be an output if "1/0 Select" is set high.
The SYNC output goes high when a conversion or a comparison is started and low when
completed. (See Section 2.2). An internal reset
after power is first applied to the LM12L454/8
automatically sets this pin as an input.
This is the Bus Width input pin. This input allows the LM12L454/8 to interface directly with
either an 8- or 16-bit databus. A logic high sets
the width to 8 bits and places D8-D15 in a
high impedance state. A logic low sets the
width to 16 bits.
This is the active low interrupt output. niis output is designed to drive capacitive loads of
100 pF or less. External buffers are necessary
for driving higher load capacitances. An interrupt signal is generated any time a nonmasked interrupt condition takes place. There
. are eight different conditions.. that can cause
an interrupt. Any interrupt is reset by reading
the Interrupt Status register. (See Section 2.3.)

DMARQ

This is the active high Direct Memory Access
Request output. This output is designed to
drive capacitive loads of 100 pF or less. External buffers are necessary for driving. higher
load capacitances. It goes high whenever the
number of conversion results in the conversion
FIFO equals a programmable value stored in
the Interrupt Enable register. It returns to a logic low when the FIFO is empty.

GND

This is the LM12L454/8 ground connection. It
should be connected to a low resistance and
inductance analog ground return that connects
directly to the system power supply groUlid.

INO-IN7
(INO-IN3
LM12L454

These are the eight (LMI2L458) or four
(LMI2L454) analog inputs. A given channel is
selected through the .instruction RAM. Any of
the channels can be configured as an independent single-ended input. Any pair of channels,
whether adjacent or non-adjacent, can operate
as a fully differential pair.
These are the LM12L454's non-inverting and
inverting inputs to the internal S/H.

S/H IN+
S/H IN-

MUXOUT+ These are the LM12L454's non-inverting and
MUXOUT - inverting outputs from the internal multiplexer.
This is the negative reference input. The
LM12L454/8 operate with OV ,,; VREF- ,,;
VREF+. This pin should be bypassed to
, ground with a parallel combination of 10 p.F
and 0.1 p.F (ceramic) capacitors.

AO-A4 These are the LM12L454/8's address lines. They
are used to access all internal registers, Conversion FIFO, and Instruction RAM.
SYNC This is the synchronization input/output. When
used as an output, it is deSigned to drive capacitive
loads of 100 pF or less. External buffers are necessary for driving higher load capacitances. SYNC
is an Input if the Configuration register's "I/O Select" bit is low. A rising edge on this pin causes

This is the positive reference input. The
LM12L454/8 operate with OV ,,; VREF+ ,,;
VA +. This pin should be bypassed to ground
with a parallel combination of 10 p.F and
0.1 p.F (ceramic) capacitors.
N.C.

1-166

This is a no connect pin.

Application Information

1.0 Functional Description.
The LM12L454t8's "watchdog" mode is used to monitor a
single-ended or differential Signal's amplitude. Each sampled signal has two limits. An interrupt can be generated if
the input signal is above or below either of the two limits.
This allows interrupts to be generated when analog voltage
inputs are "inside the window" or, alternatively, "outside the
window". After a "watchdog" mode interrupt, the processor
can then request a conversion on the input signal and read
the signal's magnitude.

The LM12L454 and LM12L458 are multi-functional Data Acquisition Systems that include a fully differential 12-bit-plussign self-calibrating analog-~o-digital converter (ADC) with a
two's-complement output format, an 8-channel (LM12L458)
or a 4-channel (LM12L454) analog multiplexer, a first-infirst-out (FIFO) register that can store 32 conversion results,
and an Instruction RAM that can store as many as eight
instructions to be sequentially executed. The LM12L454
also has a differential multiplexer output and a differential
StH input. All of this circuitry operates on only a single
+ 3.3V power supply.
The LM12L454t8 have three modes of operation:
12-bit + sign with correction
8-bit + sign without correction
8-bit + sign comparison mode ("watchdog" mode)

The analog input multiplexer can be configured for any combination of single-ended or fully differential operation. Each
input is referenced to ground when a multiplexer channel
operates in the single-ended mode. Fully differential analog
input channels are formed by pairing any two channels together.
The LM12L454's multiplexer outputs and StH inputs
(MUXOUT +, MUXOUT - and StH IN +, StH IN -) provide
the option for additional analog signal processing. Fixedgain amplifiers, programmable-gain amplifiers, filters, and
other processing circuits can operate on the signal applied
to the selected multiplexer channel(s). If external processing is not used, connect MUXOUT + to StH IN + and MUXOUT- to StH IN-.
The LM12L454t8's internal StH is deSigned to operate at
its minimum acquisition time (1.5 /Ls, 12 bits) when the
source impedance, Rs, is :5: 80n (fClK :5: 6 MHz). When
80n < Rs :5: 5.56 kn, the internal StH's acquisition time
can be increased to a maximum of 6.5 /Ls (12 bits, fClK =
6 MHz). See Section 2.1 (Instruction RAM "00") Bits 12-15
for more information.

The fully differential 12-bit-plus-sign ADC uses a charge redistribution topology that includes calibration capabilities.
Charge re-distribution ADCs use a capacitor ladder in place
ofa resistor ladder to form an internal DAC. The DAC is
used by a successive approximation register to generate
intermediate voltages between the voltages applied to
VREF- and VREF+. These intermediate voltages are compared against the sampled analog input voltage as each bit
is generated. The number of intermediate voltages and
comparisons equals the ADC's resolution. The correction of
each bit's accuracy is accomplished by calibrating the capacitor ladder used in the ADC.
Two different calibration modes are available; one compensates for offset voltage, or zero error, while the other corrects both offset error and the ADC's linearity error.
When correcting offset only, the offset error is measured
once and a correction coefficient is created .. During the full
calibration, the offset error is measured eight times, averaged, and a correction coefficient is created. After completion of either calibration mode, the offset correction coefficient is stored in an internal offset correction register.

Microprocessor overhead is reduced through the use of the
internal conversion FIFO. Thirty-two consecutive conversions can be completed and stored in the FIFO without any
microprocessor intervention. The microprocessor can, at
any time, interrogate the FIFO and retrieve its contents. It
can also wait for the LM 12L454t8 to issue an interrupt
when the FIFO is full or after any number (:5:32) of conversions have been stored.

The LM12L454t8's overall linearity correction is achieved
by correcting the internal DAC's capacitor mismatch. Each
capacitor is compared eight times against all remaining
smaller value capacitors and any errors are averaged. A
correction coefficient is then created and stored in one of
the thirteen internal linearity correction registers. An internal
state machine, using patterns stored in an internal 16 x 8-bit
ROM, executes each calibration algorithm.
Once calibrated, an internal arithmetic logic unit (ALU) uses
the offset correction coefficient and the 13 linearity correction coefficients to reduce the conversion's offset error and
linearity error, in the background, during the 12-bit + sign
conversion. The 8-bit + sign conversion and comparison
modes use only the offset coefficient. The 8-bit + sign
mode performs a conversion in less than half the time used
by the 12-bit + sign conversion mode.

Conversion sequencing, internal timer interval, multiplexer
configuration, and many other operations are programmed
and set in the Instruction RAM.
A diagnostic mode is available that allows verification of the
LM12L458's operation. The diagnostic· mode is disabled in
the LM12L454. This mode internally connects the voltages
present at the VREF+, VREF-, and GND pins to the internal
VIN+ and VIN- StH inputs. This mode is activated by setting the Diagnostic bit (Bit 11) in the Configuration register to
a "1 n. More information concerning this mode of operation
can be found in Section 2.2.

1-167

•

2.0 Internal User-Programmable Registers
2.1 INSTRUCTION RAM

structions, Instruction 000 is retrieved and decoded. A set
PAUSE bit in Instruction 000 now halts the Sequencer before the instruction is executed.

The instruction RAM holds up to eight sequentially executable instructions. Each 48-bit long instruction is divided into
three 16-bit sections. READ and WRITE operations can be
issued to each 16-bit section using the instruction's address
and the 2-bit "RAM pointer" in the Configuration' register.
The eight instructions are located at addresses 0000
through 0111 (A4-A1, BW = O) when using a 16-bit wide
data bus or at addresses 00000 through 01111 (A4-AO,
BW = 1) when using an 8-bit wide data bus. They can be
accessed and programmed in random order. '

Bits 2-4 select which of the eight input channels ("000" to
"111" for i'NO-IN7) will be configured as non-inverting inputs to the LM12L458's ADC. (See Page 22, Table I.) They
select which of the four input channels ("OOO"'to "011" for
INO-IN4) will be configured as non-inverting inpuls to the
LM12L454's ADC. (See Page 22, Table II.)
Bits 5-7 select which of the seven input channels '("001" to
"111" for IN1 to IN7) will be configured as inverting inputs to
the LM12L458's ADC. (See Page 22, Table I.) They select
which of the three input channels ("001" to "011" for IN1IN4) will be configured as inverting inputs to the
LM12L454's ADC. (See Page 22, Table II.) Fully differential
operation is created by selecting two multiplexer channels,
one operating in the non-inverting mode and the other operating in the inverting mode. A code of "000" selects ground
as the inverting input for single ended operation.
Bit 8 is the SYNC bit. Setting Bit 8 to "1" causes the Sequencer to suspend operation at 'the end' of the internal
StH's acquisition cycle and to wait until a riSing edge appears at the SYNC pin. When a rising edge appears, the
StH acquires the input signal magnitude and the ADC performs a conversion on the clock's next rising edge. When
the SYNC pin is used as an input; the Configuration register's "110 Select" bit (Bit 7) must be set t6 a "0". With
SYNC configured as an input, it is possible to synchronize
the start of a conversion to an external event. This is useful
in applications such as digital signal processing (DSP)
where the exact timing of conversions is important.
When the LM12L454t8 are used in the "watchdog" mode
with extemal synchronization, two rising edges on the SYNC
input are required to initiate two comparisons. The first rising
edge initiates the comparison of the selected analog input
signal with Limit # 1 (found in Instruction RAM "01 ") and the
second rising edge initiates the comparison of the same
analog input signal with Limit #2 (found in Instruction RAM
"10").

Any Instruction RAM READ or WRITE clm affect the sequencer's operation:
The Sequencer should be stopped by setting the RESET
bit to a "1" or by resetting the START bit in the Configuration Register and waiting for the current instruction to
finish execution before any Instruction RAM READ or
WRITE is initiated.
A soft RESET should be issued by writing a "1" to the
Configuration Register's RESET bit after any READ or
WRITE to the Instruction RAM.
The three sections in the Instruction RAM are selected by
the Configuration Register's 2-bit "RAM Pointer", bits D8
and D9. The first 16-bit Instruction RAM section is selected
with the RAM Pointer equal to "00". This section provides
multiplexer channel selection, as well as resolution, acquisition time, etc. The second 16-bit section holds "watchdog"
limit # 1, its sign, and an indicator that shows that an interrupt can be generated if the input signal is greater or less
than the programmed limit. The third 16-bit section holds
"watchdog" limit #2, its sign, and an indicator that shows
that an interrupt can be generated if the input signal is greater or less than the programmed limit.
Instruction RAM "00"
Bit 0 is the LOOP bit. It indicates the last instruction to be
executed in any instruction sequence when it is setto a "1".
The next instruction to be executed will be instruction o.
Bit 1 is the PAUSE bit. This controls the Sequencer's operation. When the PAUSE bit is set ("1 "), the Sequencer will
stop after reading the current instruction, but before executing it and the start bit, in the Configuration register, is automatically reset to a "0". Setting the PAUSE also causes an
interrupt to be issued. The Sequencer is restarted by placing
a "1" in the Configuration register's Bit 0 (Start bit).

Bit 9 is the TIMER bit. When Bit 9 is set to "1", the Sequencer will halt until the internal 16-bit Timer counts down
to zero. During this time interval, no "watchdog" comparisons or analog-to-digital conversions will be performed.
Bit 10 selects the ADC conversion resolution; Setting Bit 10
to "1" selects 8-bit + sign and when reset to "0" selects
12-bit + sign.

After the Instruction RAM has been programmed and the
RESET bins set to "1 ", the Sequencer retrieves Instruction
000, decodes it, and waits for a "1" to be placed in the
Configuration's START bit. The START bit value of "0"
"overrides" Ihe action of Instruction OOO's PAUSE bit when
the Sequencer is started. Once started, the Sequencer executes Instruction 000 and retrieves, decodes, and executes
each of the remaining instructions. No PAUSE Interrupt (lNT
5) is generated the first time the Sequencer executes Instruction 000 having a PAUSE bit set to "1". When the Sequencer encounters a LOOP bit or completes all eight in-

Bit 11 is the "watchdog" comparison mode enable bit.
When operating in the "watchdog" comparison mode, the
selected analog input Signal is compared with the programmable values stored in Limit #1 and Limit #2 (see Instruction RAM "01" and Instruction RAM "10"). Setting Bit 11 to
"1" causes two comparisons of the selected analog input
signal with the two stored limits. When Bit 11 is reset to "0",
an 8-bit + sign or 12-bit + sign (depending on the state of
Bit 10 of Instruction RAM "OO") conversion of the input signal can take place.

1-168

2.0 Internal User-Programmable Registers
A4A3A2Al

Purpose

Type 01sI01410131012

R/W
0 0
Instruction RAM
to
(RAM Pointer = 00)
1 1 1

0
0

Acquisition
Time

09

010

08

Watch8/12 Timer Sync
dog

07

06

- 05

04

03

02

VIN-

VIN+

(MUXOUT-j"

(MUXOUT+)'

01

00

Pause Loop

0
0

0 0
R/W
Instruction RAM
to
(RAM Pointer = 01)
1 1 1

011

(Continued)

0

0 0
R/W
Instruction RAM
to
(RAM Pointer = 10)
1 1 1

1

0

0

0

Configuration
Register

1 0

0

1

Interrupt Enable
Register

Don't Care

>1< Sign

Limit #1

Don't Care

>1< Sign

Limit #2

0

R/W

R/W

R
1 0

1

0

Interrupt Status
Register

1 0

1

1

Timer
Register

R/W

1

1

0

0

Conversion
FIFO

R

1

1

0

1

Limit Status
Register

R

Don't Care

DIAGt

Test
=0

RAM
POinter

Number of Conversions
in Conversion FIFO
to Generate INT2

Sequencer
Address to
Generate INTI

Actual Number of
Conversion Results
in Conversion FIFO

Address
of
Sequencer
Instruction
being
Executed

Timer Preset High Byte
Address
or Sign

ISign

Conversion
Data: MSBs

Limit # 2: Status

1/0 Auto Chan Stand- Full
CAL
Sel Zeroec Mask by

INT7 Don't INT5
Care

INST7

"0"

INT4

AutoReset Start
Zero

INT3 INT2 INTI

INSTS INST4 INST3 INST2 INSTI INSTO

Timer Preset Low Byte

Conversion Data: LSBs

Limit # 1: Status

'LM12L454 (Refer to Table II).
tLM12L458 only. Must be set to "0" for the LM12L454.

FIGURE 9. LM12L454/8 Memory Map for lS·Bit Wide Databus (BW = "O",Test Bit = "0" and AO = Don't Care)

1-169

INTO

•

2.0 Internal User-Programmable Registers (Continued)
A4 :A3

A2

A1

0
to
1

0

0
to
1

0

0
to
1

0

0
to
1

O.

0
to
1

0

0

1

0'
to
1

0

0

0

'0
O.
1
0
0
1
0
0
1
0
0
1
0
0
, 1
:

',0

0
1

.AO

Purpose

Type

07

0
1

Instruction RAM
(RAM Pointer = 00)

04 .

05

06

R/W

03

02

01

00

VIN-

VIN+

(MUXOUT-)'

(MUXOUT+)'

,

Pause

Loop

Watchdog

8/12

Timer

Sync

>1<

Sign

>1<

Sign

Reset

Start

R/W

1

Acquisition Time

1

R/W
0

1

Comparison Limit #1
Instruction RAM
(RAM Pointer = 01)

R/W

1

Don't Care

1

R/W
0

1

Comparison Limit"" 2
Instruction RAM
(RAM Pointer = 10)

R/W

1

Don't Care

1

R/W

0

1

0

0

0

.1

1

0

0

1

0

1

0

0

1

1

1

0

1

0

0

1

0

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

0

0

0

1

1

0

0

1

1

1

0

1

0

1

1

0

1

1

Configuration
Register

R/W
R

Interrupt Status
Register

I Auto I Chan
Zeroee Mask

R/W
R/W

Interrupt Enable
Register

1/0
Sel

R

Standby

Don't Care

1~T71

Don't IINT5
Care

'INT4

Full
Cal

AutoZero

DIAGt

Test
=0

RAM Pointer

INT3

INT2

INT1

Number of Conversions in Conversion
FIFO to Generate INT2
INST71

"0"

IINST5

INST4

Sequencer Address to.
Generate INT1

INST3

INST2

Actual Number of Conversions Results
in Conversion FIFO

R/W

Timer Preset: Low Byte

R/W

Timer Preset: High Byte

Conversion
FIFO

R

Conversion Data: LSBs

R

Address or Sign

Sign

Limit "" 1 Status

R

Limit"" 2 Status

'LMI2L454 (Refer 10 Table II).
tLM12L458 only. Must be set to "0" for the LM12L454.

1-170

INSTO

Conversion Data: MSBs

R

FIGURE 10. LM12L454/B Memory Map for 8-Blt Wide Oatabus IBW

INST1

Address of Sequencer
Instruction
being Executed

Timer
Register

Limit Status
Register

INTO

= "1" and Test Bit = "0")

.-----------------------------------------------------------------I~

2.0 Internal User-Programmable Registers (Continued)
Bits 12-15 are used to store the user-programmable acquisition time. The Sequencer keeps the internal S/H in the
acquisition, mode for a fixed number of clock cycles (nine
clock cycles, for 12-bit + sign conversions and two clock
cycles for 8-bit + sign conversions or "watchdog" comparisons) plus a variable number of clock cycles equal to twice
the value stored in Bits 12-15. Thus, the S/H's acquisition
time is (9 + 2D) clock cycles for 12-bit + sign conversions
and (2 + 2D) clock cycles for 8-bit + sign conversions or
"watchdog" comparisons, where D is the value stored in
Bits 12-15. The minimum acquisition time compensates for
the typical internal multiplexer series resistance of 2 kO,
and any additional delay created by Bits 12-15 compensates for source resistances greater than 800. (For this acquisition time discussion, numbers in ( ) are shown for the
LM12L454/8 operating at 6 MHz. The necessary acquisition
time is determined by the source impedance at the multiplexer input. If the source resistance (Rs) < 800 and the
clock frequency is 6 MHz, the value stored in bits 12-15 (D)
can be 0000. If Rs > 800, the following equations determine the value that should be stored in bits 12-15.
D = 0.45 x Rs xfClK
for 12-bits + sign
D = 0.S6xRsxfClK
for 8-bits + sign and "watchdog"

limit # 2 to generate an interrupt, while a "0" causes a voltage less than limit #2 to generate an interrupt.
Bits 10-15 are not used.
2.2 CONFIGURATION REGISTER
The Configuration register, 1000 (A4-Al, BW = 0) or
1000x (A4-AO, BW = 1) is a 16-bit control register with
read/write capability. It acts as the LM12L454's and
LM12L458's "control panel" holding global information as
well as start/stop, reset, self-calibration, and stand-by commands.
Bit 0 is the START/STOP bit. Reading Bit 0 returns an indication of the Sequencer's status. A "0", indicates that the
Sequencer is stopped and waiting to execute the next instruction. A "1" shows that the Sequencer is running. Writing a "0" halts the Sequencer when the current instruction
has finished execution. The next instruction to be executed
is pointed to by the instruction pOinter found in the status
register. A "1" restarts the Sequencer with the instruction
currently pointed to by the instruction pointer. (See Bits 810 in the Interrupt Status register.)
Bit 1 is the LMI2L454/8's system RESET bit. Writing a "1"
to Bit 1 stops the Sequencer (resetting the Configuration
register's START/STOP bit), resets the Instruction pointer
to "000" (found in the Interrupt Status register), clears the
Conversion FIFO, and resets all interrupt flags. The RESET
bit will return to "0" after two clock cycles unless it is forc,ed
high by writing a "1" into the Configuration register's StandbY,bit. A reset signal is intemallygeneratedwhenpower.is
first applied to the part. No operation should be started until
the RESET bit is "0".
Writing a "1" to BII 2 initiates an auto-zero offset voltage
calibration. Unlike the eight-sample auto-zero calibration
performed during, the full calibration procedure, Bit 2 initi;
ates a "short" auto-zero by sampling the, offset once and
creating a correction coefficient (full calibration averages
eight samples of the converter offset voltage when creating
a correction coefficient). If the Sequencer is running when
Bit 2 is set to "1", an auto-zero starts immediately after the
conclusion of the currently running instruction., Bit 2 is, reset
automatically to a "0" and an interrupt flag (Bit S, in the
Interrupt Status register) is set at the end of the auto-zero
(76 clock cycles). After comp)etion of ,an auto-zero calibration, the Sequencer fetches the next instruction as pointed
to by the Instruction RAM's pOinter and resumes execution.
If the Sequencer is stopped, an auto-zero is performed immediately at the time requested.
Writing, a "1" to Blt,3 initiates a complete c::alibratiqn process that includes a "long" auto-zero offset voltage correction (thiS calibration averages eight samples of the comparator offset voltage when creating a correction coefficient)
followed by an ADC linearity calibration. This complete calibration is started after the currently running instruction is
completed if the Sequencer is running when Bit Sis s,etto
"1". BitS is reset automatically to a "0" and an interrupt flag
(Bit 4, in the Interrupt Status register) will be generated at
the end of the calibration procedure (4944 clock cycles).
After completion of a full auto-zero and linearity calibration,
the Sequencer fetches the next instruction as pointed to by
the Instruction RAM's pointer and resumes execution. If the
Sequencer is stopped, a full calibration is performed immediately at the time requested.

Rs is in kO and fClK is in MHz. Round the result to the next
higher integer value. If D is greater than 15, it is advisable to
lower the source impedance by using an analog buffer between the signal source and the LM12L458's multiplexer
inputs. The value of D can also be used to compensate for
the settling or response time of external processing circuits
connected between the LM12L454's MUXOUT and S/H IN
pins.
Instruction RAM "01"
The second Instruction RAM section is selected by placing
a "01" in Bits 8 and 9 of the Configuration register.
Bits 0-7 hold "watchdog" limit # 1. When Bitll of Instruction RAM "00" is set to a "1", the LM12L454/8 performs a
"watchdog" comparison of the sampled analog input signal
with the limit # 1 value first, followed by a comparison of the
same sampled analog input signal with the value found in
limit #2 (Instruction RAM "10").
Bit 8 holds limit # 1's sign.
Bit 9's state determines the limit condition that generates a
"watchdog" interrupt. A "1" causes a voltage greater than
limit # 1 to generate an interrupt, while a "0" causes a voltage less than limit # 1 to generate an interrupt.
Blls 10-15 are not used.
Instruction RAM "10"
The third Instruction RAM section is selected by placing a
"10" in Bits 8 and 9 of the Configuration register.
Bits 0-7 hold "watchdog" IImil #2. When Bitll of Instruction RAM "00" is set to a "1 ", the LM12L454/8 performs a
"watchdog" comparison of the sampled analog input Signal
with the limit # 1 value first (Instruction RAM "01 "), followed
by a comparison of the same sampled analog input Signal
with the value found in limit #2.
Bit 8 holds limit #2's sign.
Bit 9's state determines the limit condition that generates a
"watchdog" interrupt. A "1" causes a voltage greater than

1·171

a:
....
I\)

!;
U1
Ao
......
~

a:
....
I\)

s:
U1

co

•

CD

In

~

....
N

~

~

In

~

....
N

~

r---------------------------------------------------------------------------------~

2.0 Internal User-Programmable Registers (Continued)
2.3 INTERRUPTS
The LM12L454 and LM12L458 have eight possible interrupts, all with the same priority. Any of these interrupts will
cause a hardware interrupt to appear on the INT pin (31) if
they are not masked (by the Interrupt Enable register). The
Interrupt Status register is then read to determine which of
the eight interrupts has been issued.

Bit 4 is the Standby bit. Writing a "1" to Bit 4 immediately
places the LM12L454/8 in Standby mode. Normal operation
returns when Bit 4 is reset to a "0". The Standby command
("1 ") disconnects the external clock from the internal circuitry, decreases the LM12L454/8's internal analog circuitry
power supply current, and preserves all internal RAM contents. After writing a "0" to the Standby bit. the
LM12L454/8 returns to an operating state identical to that
caused by exercising the' RESET bit. A Standby completion
interrupt is issued after a power-up completion delay that
allows the analog circuitry to sellie. The Sequencer should
be restarted only after the Standby completion is issued.
The Instruction RAM can still be accessed through read and
write operations while the LM12L454/8 are in Standby
Mode.
Bit 5 is the Channel Address Mask. If Bit 5 is set to a "1",
Bits 13-15 In the conversion FIFO will be equal to the sign
bit (Bit 12) of the conversion data. Reselling Bit 5 to a "0"
causes conversion data Bits 13 through 15 to hold the instruction pointer value of the instruction to which the conversion data belongs.

TABLE I. LM12L458 Input Multiplexer
. Channel Configuration Showing Normal
Mode and Diagnostic Mode
Channel
Selection
Data

Bit 6 is used to select a "short" auto-zero correction for
every conversion. The Sequencer automatically inserts an
auto-zero before every conversion or "watchdog" comparison if Bit 6 is set to "1". No automatic correction will be
performed if Bit 6 is reset t6 ~·O".

Normal
Mode
VIN+

VIN-

000.

INO

GND

001
010
011
100
101
110
111

IN1
IN2
IN3
'IN4
IN5
IN6
IN7

IN1
IN2
IN3
IN4
IN5
IN6
IN7.

Diagnostic
Mode
VIN+

VIN-

VREF+
IN2
IN3
IN4
IN5
IN6
IN7

VREFIN2
IN3
IN4
IN5
IN6
IN7

TABLE II. LM12L454 Input Multiplexer
Channel Configuration

The LM12L454/8's offset voltage, after calibration; has a
tYpical drift of 0.1 LSB over a temperature range of - 40'C
to .+ 85'C. This small drift is less than the variability of the
change in offset that can occur when using the auto-zero
correction with each conversion. This variability is the result
of using only one sample of the 'offset voltage to create a
correction value. This variability decreases when using the
full calibration mode because eight samples of the offset
voltage are taken, averaged, and used to create a correction value.
Bit 7 is used to program the SYNC pin (29) to operate as
either an' input or an output. The SYNC pin becomes an
output when Bit 7 is a "1" and an input when Bit 7 is a '''0''.
With SYNC programmed as an input,the rising edge of any
logic signal applied to pin 29 will' start a conversion or
"watchdog" comparison. Programmed' as an output, the
logic level at pin 29 will go high at the start of a conversion
or "watchdog" comparison and remain high until either
..
have finished. See Instruction RAM "00", Bit 8.

Channel
Selection
Data

MUX+

MUX-

000
001
010
011
1XX

INO
IN1
IN2
IN3
OPEN

GND
IN1
IN2
IN3
OPEN

The Interrupt Status register, 1010 (A4-A1, BW = 0) or
1010x(A4-AO, BW = 1) musfbe cleared by reading it after
writing to the' Interrupt Enable register. This removes any
spurious interrupts on the TiiIT pin' generated during an Interrupt Enable register access.
Interrupt 0 is generated whenever the analog input voltage
on a selected multiplexer channel crosses a limit while the
LM12L454/8 are operating in the "watchdog" comparison
mode. Two sequential comparisons are made when the
LM12L454/8 are executing a "watchdog" instruction. Depending on the logic state of Bit 9 in the Instruction RAM's
second and third sections, an interrupt will be generated
either when the input signal's magnitude is greater than or
less than the programmable limits. (See the Instruction
RAM, Bit 9 description.) The Limit Status register will indicate which preprogrammed.limit, #1 or #2 and which instruction was executing when the limit was crossed.

Bits 8 and 9 form the RAMOoPointer that is used to' select
each of a 48-bit instruction's three 16-bit sections during
read or write actions. A "00" selects Instruction RAM section one, "01" selects section two, and "10" selects section
three.
Bit 10' activates the Test mode that is used only during production testing. Leave this bit reset to "0".
B.lt 11 is the Diagnostic bit and is available only in' ~he
LM12L458. It can be activated by setting it to a "1" (the
Test bit must be reset to a "0").' The Diagnostic mode,
along with a correctly chosen instruction, allows verification
that the LM12L458's ADC is performing correclly. When activated, the inverting and non-inverting inputs are connected
as shown in Table I. As an example, an instruction with
"001" for both VIN+ and VIN- while using the Diagnostic
mode typically results In a full-sCale output.

Interrupt 1 is generated when the Sequencer reaches the
instruction counter value specified in the Interrupt Enable
register's. bits 8-10. This flag appears before the instruction's execution.
Interrupt 2 is activated when the Conversion FIFO holds a
number of. conversions equal to the programmable value

1-172

2.0 Internal User-Programmable Registers

:he completion of a full auto-zero and linearity self-calibratlon generates Interrupt 4.
Interrupt 5 is generated when the Sequencer encounters
an instruction that has its Pause bit (Bit 1 in Instruction RAM

(Continued)
INT 1 trigger value to 000 does not generate an INT 1 the
first time the Sequencer retrieves and decodes Instruction
000. The Sequencer generates INT 1 (by placing a "1" in
the Interrupt Status register's Bit 1) the second time and
after the Sequencer encounters Instruction 000. It is important to remember that the Sequencer continues to operate
even if an Instruction interrupt (INT .1) is internally or externally generated. The only mechanisms that stop the Sequencer are an instruction with the PAUSE bit set to "1"
(halts before instruction execution), placing a "0" in the
Configuration register's START bit, or placing a "1" in the
Configuration register's RESET bit.

"00") set to "1".
Interrupt 7 is issued after a short delay (10 ms typ) while
the LM12L454/8 returns from Standby mode to active operation using the Configuration register's Bit 4. This short delay allows the internal analog Circuitry to settle sufficiently,
ensuring accurate conversion results.

Bits 11-15 hold the number of conversions that must be
stored in the Conversion FIFO in order to generate an internal interrupt. This internal interrupt appears in Bit 2 of the
Interrupt Status register. If Bit 2 of the Interrupt Enable register is set to "1 ", an external interrupt will appear at pin 31
(INT).

2.4 INTERRUPT ENABLE REGISTER
The Interrupt Enable register at address location 1001
(A4-A1, BW = 0) or 1001x (A4-AO, BW = 1) has READ/
WRITE capability. An individual interrupt's ability to produce
an external interrupt at pin 31 (INn is accomplished by placing a "1" in the appropriate bit location. Any of the internal
interrupt-producing operations will set their corresponding
bits to "1" in the Interrupt Status register regardless of the
state of the associated bit in the Interrupt Enable register.
See Section 2.3 for more information about each of the
eight internal interrupts.
Bit 0 enables an external interrupt when an internal "watchdog" comparison limit interrupt has taken place.
Bit 1 enables an external interrupt when the Sequencer has
reached the address stored in Bits 8-10 of the Interrupt
Enable register.
Bit 2 enables an external interrupt when the Conversion
FIFO's limit, stored in Bits 11-15 of the Interrupt Enable
register, has been reached.
Bit 3 enables an external interrupt when the single-sampled
auto-zero calibration has been completed.
Bit 4 enables an external interrupt when a full auto-zero and
linearity self-calibration has been completed.
Bit 5 enables an external interrupt when an internal Pause
interrupt has been generated.
Bit 6 is a "Don't Care".
Bit 7 enables an external interrupt when the LM12L454/8
return from power-down to active mode.
Bits 8-10 form the storage location of the user-programmable value against which the Sequencer's address is compared. When the Sequencer reaches an address that is
equal to the value stored in Bits 8-10, an internal interrupt
is generated and appears in Bit 1 of the Interrupt Status
register. If Bit 1 of the Interrupt Enable register is set to "1",
an external interrupt will appear at pin 31 (INn.
The value stored in bits 8-10 ranges from 000 to 111, representing 0 to 7 instructions stored in the Instruction RAM.
After the Instruction RAM has been programmed and the
RESET bit is set to "1 ", the Sequencer is started by plaCing
a "1" in the Configuration register's START bit. Setting the

2.5 INTERRUPT STATUS REGISTER
This read-only register is located at address 1010 (A4-A1,
BW = 0) or 1010x (A4-AO, BW = 1). The corresponding
flag in the Interrupt Status register goes high ("1 ") any time
that an interrupt condition takes place, whether an interrupt
is enabled or disabled in the Interrupt Enable register. Any
of the active (" 1") Interrupt Status register flags are reset to
"0" whenever this register is read or a device reset is issued
(see Bit 1 in the Configuration Register).
Bit 0 is set to "1" when a "watchdog" comparison limit
interrupt has taken place.
Bit 1 is set to "1" when the Sequencer has reached the
address stored in Bits 8-10 of the Interrupt Enable register.
Bit 2 is set to "1" when the Conversion FIFO's limit, stored
in Bits 11-15 of the Interrupt Enable register, has been
reached.
Bit 3 is set to "1" when the single-sampled auto-zero has
been completed.
Bit 4 is set to "1" when an auto-zero and full linearity selfcalibration has been completed.
Bit 5 is set to "1" when a Pause interrupt has been generated.
Bit 6 is a "Don't Care".
Bit 7 is set to "1" when the LM12L454/8 return from powerdown to active mode.
Bits 8-10 hold the Sequencer's actual instruction address
while it is running.
Bits 11-15 hold the actual number of conversions stored in
the Conversion FIFO while the Sequencer is running.

stored in the Interrupt Enable register's Bits 11-15. This
value ranges from 0001 to 1111, representing 1 to 31 conversions stored in the FIFO. A user-programmed value of
0000 has no meaning. See Section 3.0 for more FIFO information.
The completion of the short single-sampled auto-zero calibration generates Interrupt '3.

2.6 LIMIT STATUS REGISTER
The read-only register is located at address 1101 (A4-A1,
BW = 0) or 1101 x (A4-AO, BW = 1). This register is used
in tandem with the Limit '" 1 and Limit '" 2 registers in the
Instruction RAM. Whenever a given instruction's input voltage exceeds the limit set in its corresponding Limit register
('" 1 or '" 2), a bit, corresponding to the instruction number,
is set in the Limit Status register. Any of the active ("1 ")
Limit Status flags are reset to "0" whenever this register is

1-173

III

2.0 Internal User-Programmable Registers (Continued)
read or a device reset is issued (see Bit 1 in the Configuration register). This register holds the status of limits # 1 and
#2 for each of the eight instructions.
Bits 0-7 show the Limit # 1 status. Each bit will be set high
("I") when the corresponding instruction's input voltage exceeds the threshold stored in the instruction's Limit # 1 register. When, for example, instruction 3 is a "watchdog" operation (Bit 11 is set high) and the input for instruction 3
meets the magnitude and/or polarity data stored in instruction 3's Limit # 1 register, Bit 3 in the Limit Status register
will be set to a "I".
Bits 8-15 show the Limit #2 status. Each bit will be set
high ("I") when the corresponding instruction's input voltage exceeds the threshold stored in the instruction's Limit
# 2 register. When, for example, the input to instruction 6
meets the value stored in instruction 6's Limit # 2 register,
Bit 14 in the Limit Status register will be set to a "I".

conversion result from the FIFO. Therefore, the DMA controller must be able to repeatedly access two constant addresses when transferring data from the LM12L454/8 to the
host system.

3.0 FIFO
The result of each conversion stored in an internal read-only
FIFO (First-In, First-Out) register. It is located at 1100 (.11.4A I, BW = 0) or 11 OOx (A4-AO, BW = 1). This register has
32 16-bit wide locations. Each location holds 13-bit data.
Bits 0-3 hold the four LSB's in the 12 bits + sign mode or
"1110" in the B bits + sign mode. Bits 4-11 hold the eight
MSB's and Bit 12 holds the sign bit. Bits 13-15 can hold
either the sign bit, extending the register's two's complement data format to a full sixteen bits or the instruction address that generaied the conversion and the resulting data.
These modes are selected according to the logic state of
'
the Configuration register's Bit 5.

2.7 TIMER

The FIFO status should be read in the Interrupt Status register (Bits 11 -15) to determine the number of conversion results that are held in the FIFO before retrieving them. This
will help prevent conversion data corruption that may take
place if the number of reads are greater than the number of
conversion results contained in the FIFO. Trying to read the
FIFO when it is empty may corrupt new data being written
into the FIFO. Writing more than 32 conversion data into the
FIFO by the ADC results in loss of the first conversion data.
Therefore, to preyent data loss, it is recommended that the
LM12L454/8's interrupt capability be used to inform the
system controller that the FIFO is full.
The lower portion (AO = 0) of the data word (Bits 0-7)
should be read first followed by a read of the upper portion
(AO = 1) when using the B-bit bus width (BW = 1). Reading
the upper 'portion first causes the data to shift down, which
results in loss of the lower byte.
Bits 0-12 hold 12-bit + sign conversion data. Bits 0-3 will
be 1110 (LSB) when using 8-bit plus sign resolution.

The LM12L454/B have an on-board 16-bit timer that includes a 5-bit pre-scaler. It uses the clock signal applied to
pin 23 as its input. It can generate time intervals of 0
through 221 clock cycles in steps of 25. This time interval
can be used to delay the execution of instructions. It can
also be used to slow the conversion rate when converting
slowly changing signals. This can reduce the amount ohedundant data stored in the FIFO and retrieved by the controller.
The user-defined timing value used by the Timer is stored in
the 16-bit READ/WRITE Timer register at location 1011
(A4-Al, BW = 0) or 1011x (A4-AO, BW = 1) and is preloaded automatically. Bits 0-7 hold the preset value's low
byte and Bits 8-15 hold the high byte. The Timer is activated by the Sequencer only if the current instruction's Bit 9 is
set ("I"). If the equivalent decimal value "N"
(0 ,;;: N ,;;: 216 - 1) is written inside the 16-bit Timer register
and the Timer is enabled by setting an instruction's bit 9 to a
"1", the Sequencer will delay the same instruction's execution by halting at state 3 (S3), as shown in Figure 11, for
32 x N + 2 clock cycles.
'

Bits 13-15 hold either the, instruction responsible for the
associated conversion data or the sign bit. Either mode is
selected with Bit 5 in the Configuration register.

2.8DMA
The DMA works in tandem with Interrupt 2. An active DMA
Request on pin 32 (DMARQ) requires that the FIFO interrupt be enabled. The voltage on the DMARQ pin goes high
when the number of conversions in the FIFO equals the
5-bit value stored in the Interrupt Enable register (bits 1115). The voltage on the INT pin goes low at the same time
as the voltage on the DMARQ pin goes high. The voltage on
the DMARQ pin goes low when the FIFO is emptied. The
Interrupt Status register must be read to clear the FIFO interrupt flag in order to enable the next DMA request.

Using the FIFO's full depth is achieved as follows. Set ihe
value of the Interrupt Enable registers's Bits 11-15 to 1111
and the Interrupt Enable register's Bit 2 to a "1". This generates an external interrupt when the 31st conversion is
stored in the FIFO. This gives the host processor a chance
to send a "0" to the LM12L454/8's Start bit (Configuration
register) and halt the ADC before it completes the 32nd
conversion. The Sequencer halts after the current (32) conversion is completed. The conversion data is then transferred to the FIFO and occupies the 32nd location. FIFO
overflow is avoided if the Sequencer is halted before the
start of the 32nd conversion by placing ,a "0" in the Start bit
(Configuration register). It is important to remember that the
Sequencer continues to operate even If a FIFO interrupt
(INT 2) Is Internally or externally generated. The only
mechanisms that stop the Sequencer are an instruction with
the PAUSE bit set to "I" (halts before instruction execution), placing a "0" in the Configuration register's START
bit, or placing a "I" in the Configuration register's RESET
bit.
'
,

DMA operation is optimized through the use of the 16-bit
databus connection (8. logic "0" applied to the BW pin). Using this bus width allows DMA controllers that have single
address Read/Write capability to easily unload the FIFO.
Using DMA on an 8-bit databus is more difficult. Two read
operations (low byte, high byte) are needed to retrieve each

1-174

4.0 Sequencer
State 3: Run the internal 16-bit Timer. The number of
clock cycles for this state varies according to the value
stored in the Timer register. The number of clock cycles is
found by using the expression below

The Sequencer uses a 3-bit counter (Instruction Pointer, or
IP, in Figure 7) to retrieve the programmable conversion
instructions stored in the Instruction RAM. The 3-bit counter
is reset to 000 during chip reset or if the current executed
instruction has its Loop bit (Bit 1 in any Instruction RAM
"00") set high ("1 "). It increments at the end of the currently
executed instruction and points to the next instruction. It will
continue to increment up to 111 unless an instruction's
Loop bit is set. If this bit is set, the counter resets to "000"
and execution begins again with the first instruction. If all
instructions have their Loop bit reset to "0", the Sequencer
will execute all eight instructions continuously. Therefore, it
is important to realize that if less than eight instructions are
programmed, the Loop bit on the last instruction must be
set. Leaving this bit reset to "0" allows the Sequencer to
execute "unprogrammed" instructions, the results of which
may be unpredictable.

32T

+2

where 0 ,;; T ,;; 2 16 -1.
State 7: Run the acquisition delay and read Limit # 1's
value if needed. The number of clock cycles for 12-bit +
sign mode varies according to
9 + 2D
where D is the user-programmable 4-bit value stored in bits
12-15 of Instruction RAM "00" and is limited to 0 ,;; D ,;;
15.
The number of clock cycles for 8-bit + sign or "watchdog"
mode varies according to
2 + 2D
where D is the user-programmable 4-bit value stored in bits
12-15 of Instruction RAM "00" and is limited to 0 ,;; D ,;;
15.
State 6: Perform first comparison. This state is 5 clock
cycles long.

The Sequencer's Instruction Pointer value is readable at
any time and is found in the Status register at Bits 8-10.
The Sequencer can go through eight states during instruction execution:
State 0: The current instruction's first 16 bits are read
from the Instruction RAM "00". This state is one clock cycle
long.
State 1: Checks the state of the Calibration and Start bits.
This is the "rest" state whenever the Sequencer is stopped
using the reset, a Pause command, or the Start bit is reset
low ("0"). When the Start bit is set to a "1", this state is one
clock cycle long.
State 2: Perform calibration. If bit 2 or bit 6 of the Configuration register is set to a "1 ", state 2 is 76 clock cycles long.
If the Configuration register's bit 3 is set to a "1 ", state 2 is
4944 clock cycles long.

State 4: Read Limit #2. This state is 1 clock cycle long.
State 5: Perform a conversion or second comparison.
This state takes 44 clock cycles when using the 12-bit +
sign mode or 21 clock cycles when using the 8-bit + sign
mode. The "watchdog" mode takes 5 clock cycles.

1·175

4.0 Sequencer (Continued)
RESET

Perform CalibratIon

52

$tart 81t-O

Start Bit = 1

I
I
I
I
I
I
I
I

. . ._-....,---...1
._------------_.
55 I

FIGURE 11. Sequencer Logic Flow Chart (IP

1·178

=

Instruction Pointer)

TUH/11711-22

r-----------------------------------------------------------------------------,

I\)

5.1 REFERENCE VOLTAGE

5.3 INPUT CURRENT
A charging current flows into or out of (depending on the
input voltage polarity) the analog input pins, INO-IN7 at the
start of the analog input acquisition time (tACO)' This current's peak value will depend on the actual input voltage
applied. ,

The difference in the voltages applied to the VREF+ and
VREF- defines the analog input voltage span (the difference between the voltages applied between two multiplexer
inputs or the voltage applied to one of the multiplexer inputs
and analog ground), over which 4095 positive and 4096
negative codes exist. The voltage sources driving VREF + or
VREF- must have very low output impedance and noise.
The circuit in Figure 12 is an example of a very stable reference appropriate for use with the LM12L454tS.

5.4 INPUT SOURCE RESISTANCE
For low impedance voltage sources «SOO for 6 MHz operation) the input charging current will decay, before the end
of the StH's acquisition time, to a value that will not introduce any conversion errors. For higher source impedances,
the StH's acquisition time can be increased. As an example, operating with a 6 MHz clock frequency and maximum
acquisition time, the LM12L454/S's analog inputs can handle source impedance as high as 5.56 kO. Refer to Section
2.1, Instruction RAM "00", Bits 12-15 for further information.

The ADC can be used in either ratiometric or absolute reference applications. In ratiometric systems, the analog input
voltage is proportional to the voltage used for the ADC's
'reference voltage. When this voltage is the system power
supply, the VREF + pin is connected to VA + and VREF _ is
con[1ected to GND. This technique relaxes the system reference stability requirements because the analog input voltage and the ADC reference voltage move together. This
maintains the same output code for given input conditions. ,

'Iz

(12-bit)

5.7 POWER SUPPLIES
Noise'spikes on the VA+ and Vo+ supply lines can cause
conversion errors; the comparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. Low
inductance tantalum capacitors of 10 ""F or greater paralleled with 0.1 ""F monolithic ceramic capacitors are recom-

V'N+ - V,N- (256) - 'Iz
(S-bit)
VREF+ - VREFRound up to the next integer value between - 4096 to 4095
for 12-bit resolution and between - 256 to 255 for S-bit resolution if the result of the above equation is not a whole
number. As an example, VREF+ = 2.5V, VREF- = 1V,
V'N+ = 1.5V and VII.j_ = GND. The 12-bit + sign output
code is positive full-scale, or 0,1111,1111,1111. If VREF +
= a.av, VREF- = 1V, V,N+ = av, and V,N- = GND, the
12-bit + sign output code is 0,1100,0000,0000.

VIN = +13V to +15V
To LM 12L454/a VA + = +3.3V

OUT

~
.....

I\)

s;:

UI

C»

5.6 NOISE
The leads to each of the analog multiplexer input pins
should be kept as short as possible. This will minimize input
noise and clock frequency coupling that can cause conversion errors. Input filtering can be used to reduce the effects
of the noise sources.

output code =

~.,-""

0100
......

External capacitors (0.01 jl-F-0.1 ""F) can be conne~ted between the analog input pins, INO-IN7, and analog ground to
filter any noise caused by inductive pickup associated with
long input leads. It will not degrade the conversion accuracy.

5.2 INPUT RANGE
The LM12L454/S's fully differential ADC and reference voltage inputs generate a two's-complement output that is
found by using the equation below.
V'N+ - V,N- (4096) VREF+ - VREF-

s;:

UI

5.5 INPUT BYPASS CAPACITANCE

For absolute accuracy, where the analog input voltage varies between very specific voltage limits, a time and temperature stable voltage source can be connected to the reference inputs. Typically, the reference voltage's magnitude
will require an initial adjustment to null reference voltage
induced full-scale errors.

output code =

r

.....
==

5.0 Analog Considerations

50 k!!

1M!!

62k!!

·Tantalum

··Ceramic
'TL/H/11711-23

FIGURE 12. Low Drift Extremely Stable Reference Circuit

1-177

•

output are applied through a OB-37 connector on the rear
side of the board. Figure 13 shows that there are numerous
analog ground connections available on the OB-37 connec·
tor.

5.0 Analog Considerations (Continued)
mended for supply bypassing. Separate bypass capacitors
should be used for the VA + and Vo + supplies and placed
as close ~s possible to these pins.

The voltage applied toVREF- and VREF+ is selected using
two jumpers, JP1 and JP2. JP1 selects between the voltage
applied to the OB-37's pin 24 or GNO and applies it to the
LM12(H)454/S's VREF- input. JP2 selects between the
LM12(H)454/S's internal refE!rence output, VREFOUT, and
the voltage applied to the OB-37's pin 22. and applies it to
the LM12(H)454/S's VREF+ input.

5.8 GROUNDING
The LM12L454/S·s nominal' high resolution performance
can be maximized through proper grounding techniques.
These include the use of separate analog and digital ground
planes. The digital ground plane is placed under all compo·
nents that handle digital signals, while the analog ground
plane is placed under all analog signal handlinQ cirCUitry.
The digital and analog ground planes are connected at only
one pOint, the power supply ground. This greatly reduces
the occurrence of ground loops and noise.

TABLE III. LM12{H)4S4/8 Evaluationllnterface
Board SW Dlp-8 Switch Settings
for Avallable"'O Memory Locations

It is recommended that stray capacitance between the ana·
log inputs or outputs (LM12L454: INO-IN3, MUXOUT +,
MUXOUT-, S/H IN+, S/H IN-; LM12L45S: INO-IN7,
VREF+, and VREF-) be reduced by increasing the clear·
ance (+ v,6th inch) between the analog signal and refer·
ence pins and the ground plane.

Hexldeclmal
I/O Memory
Base Address
100
120
140
160
ISO
1AO
1CO
300
340
2S0
2AO

5.9 CLOCK SIGNAL LINE ISOLATION
.
The LM.12L454/S's performance is optimized by routing the
analog input! output and reference sign~1 conductors (p~ns
34-44) as far as possible from the conductor that cames
the clock Signal to pin 23. Ground traces parallel to the
clock Signal trace can be used on printed circuit boards to
reduce clock signal interference on the analog input/output
pins.

6.0 Application Circuits
6.1 PC EVALUATIONIINTERFACE BOARD

SWDIP-8
SW1
(SELO)

SW2
(SEL 1)

SW3
(SEL2)

SW4
(SEL3)

ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON

ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF

ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
ON

ON
ON
ON
ON
ON
ON'
ON
ON
OFF
OFF
OFF

The board allows the use of one of three Interrupt Request
(IRO) lines IR02, IR03, and IR05. The individual IRO line
can be selected using switches 5, 6, and 7 of SW DIP·S.
When using any of these three IROs, the user needs to
ensure that there are no conflicts betwe.en the evaluation
board and any other boards attached to the computer's
'
motherboard.

Figure 13 is the schematic of an evaluation/interface board
deSigned to interface the LM12(H)454 or LM12(H)45S with
an XT or AT style computer. The LM12(H)454/S is the 5V
version of the Data Acquisition System. It is functionally
equivalent to the LM12L454/S. See the LM12(H)454/S da·
tasheet for further information. The board can be used to
develop both software and hardware for applications using
the LM12L454/S. The board hardwires the BW (Bus Width)
pin to a logic high, selecting an S·bit wide databus. There·
fore, it is deSigned for an S·bit expansion slot on the com·
puter's motherboard.

Switches 1-4, along with address lines A5-A9 are used as
inputs to GAL16VS Programmable Gate Array (U2). This de·
vice forms the interface between the computer's contn:)1
and address lines and generates the control signals used by
the LM12(H)454/S for CS, WR, and RD. It also generates
the signal that controls the data buffers. Several address
ranges within the computer's I/O memory map are avail·
able. Refer to Table III for the switch settings that gives the
desired I/O memory address range. Selection of an address
range must be done so that there are no conflicts between
the evaluation board and any other boards attached to the
computer's motherboard. The GAL equations are shown in
Figure 14. The GAL functional block diagram is shown in

The circuit operates on a single + 5V supply derived from
the computer's + 12V supply using an LM340 regulator.
This greatly attenuates noise that may be present on the
computer's power supply lines. However, your applicetion
may only need an LC filter.

Ftgure 13 also shows the recommended supply (VA + and
Vo+) and reference input (VREF+ and VREF-) bypassing.
The digital and analog supply pins can be connected to·
gether to the same supply voltage. However, they need sep·
arate, multiple bypass capaCitors. Multiple capacitors on the
supply pins and the reference inputs ensures a low imped·
ance bypass path over a wide frequency range.

Figure 15.
'
Figures 16-19 show the layout of each layer in the 3-layer
evaluation/interface board plus the silk·screen layout show·
ing parts placement. Figure 17 is the top or component side,
Figure 18 is the middle or ground plane layer, Figure 19 is
the circuit side, and Figure 16 is the parts layout.

All digital interface control signals (lOR, lOW, and AEN),
data lines (OBO-OB7), address lines (AO-A9), and IRO (in·
terrupt request) lines (IR02, IR03, and IR05) connections
are made through the motherboard slot connector. All ana·
log signals applied to, or received by, the Input multiplexer
(INO-IN7 for the LM12(H)45S and INO-IN3, MUXOUT+,
MUXOUT-, S/H IN+ and S/H IN- for the LM12(H)454),
VREF+, VREF-, VREFOUT, and the SYNC signal input/

1-178

r-----------------------------------------------------------------------------~

r

.....
==
N

6.0 Application Circuits (Continued)

s:

Rear D Connector

UI

~
r

==
.....
N
r

~

UI

co

Pl
DB37F

~
RN1E
TL/H/11711-24

Note: The layout utilizes a split ground plane. The analog ground plane is placed under all analog signals and U5 pins I, 34-44. The remaining signals and pins are
placed over the digital ground. The single point ground connection is at U6, pin 2, and this is connected to the motherboard pin 81.

Parts List:
Y1

HC49U, 8 MHz crystal

01

1N4002

L1

33 p.H

P1

DB37F; parallel connector

R1

10 Mll, 5%, %W

R2

2 kll, 5%, "V4W

10 kll, 6 resistor SIP, 5%,
YaW
JP1, JP2 HX3, 3-pin jumper
RN1

S1

SW DIP-8; 8 SPST switches

C1-3, C6, C9-11,
C19,C22 0.1 p.F, 50V, monolithic
ceramic
C4

68 pF, 50V, ceramic disk

C5

15 pF, 50V, ceramic disk

C7,C21

100 p.F, 25V, electrolytic

C8,C12,
C20
10 p.F, 3SV, electrolytic
C13, C16 0.01 p.F, SOV, monolithic
ceramic

U1

MM74HCT244N

U2

GAL16VB-20LNC

U3

MM74HCT245N

U4

MM74HCU04N

U5
U6

LM12H458CIV
LM12H454CIV
LM340AT-S.O

SK1

44-pin PLCC socket

A1

LM12H458/4 Rev.
Board

C14, C18 1 p.F, 35V, tantalum
C1S, C17 100 p.F, 50V, ceramic disk

FIGURE 13. Schematic and Parts List for the LM12(H)4S4/8 Evaluation/Interface
Board for XT Mel AT Style Compute,., Order Number LM124S8EVAL

1-179

or

o

PC

•

m ,-----------------------------------------------------------------------------,
6.0 Application Circuits (Continued)

Ln

:s
....
C'I

:!

.....
'Oil'

....I

Ln

:s
....

C'I

:::E

....I

ll ... 0 Decode Lines
lo_A5
1
lo_A6
2
lo_A?
3
lo_AB
lo_A9
5

•

lSelect Lines for Zone Decode
SELa
6
SELl
?
SEL2
B
SEL3
9
:Physlcsl 1"'0 Controls
AEN
15
I lo_WR
11
Ilo_RD
13
:Physical Outputs
ICS
'WR

I RD

IDBEN

12

TL/H/11711-25

1?
19
lB

:Intenediate Ter.s:
16
DEC0
FILT
14
Equations
:Decode of Select Lines:
ISEL2 a ISELl a ISELIrl:
SL0
ISEL2 a ISELl a SELIrl:
SLl
ISEL2 a SELl a ISEL0:
SL2
ISEL2 a SELl a SEL0:
SL3
SL4
SEL2 a !SELl a. ISEL0:
SL5
SEL2 a !SELI a SELIrl:
SL6
SEL2a SELl a ISEL0:
SEL2 a SELl 8 SELIrl:
SL?

.-

lDecode of Address Lines:
SLIrl a !io_A?
ALIrlIrl
SLI a liD_A?
AL21rl
SL2 a Ilo_A?
AL40
SL3 a lio_A?
AL61rl
ALB0
SL4 a lo_A?
ALA0
SL5 a lo_A?
ALC0
SL6 a lo_A?
AH01
AH02
AH03

a
a
a
a
a
a
a

Ilo_A6
Ilo_A6
lo_A6
lo_A6
·Ilo_A6
Ilo_A6
lo_A6

a I lo_A5
a lo_A5
a I I o_A5
a lo_A5
a Ilo_A5
a' lo,-A5
a Ilo_A5

ISEL3 a Ilo_A9 a lo_AB:
SEL3 & lo_A9 a lio_AB a lo_A?" a Ilo_A6:
SEL3 a lo_A9 a lo_AB & !lo_A? a Ilo_A5:

:Inter.edlate Address Groups:
DEC0
.
IAEN a (AL00 + AL20 + AL40 + AL60 + ALB0 + ALA0 + ALC0l:
lDAS Chip Select Decode:
FILT
CS a ( lo_WR + lo_RDl:
CS
.
( lo_WR + lo_RDl a DEC0 a'( AH01 + AH02 + AHIrl3l:
DBEN
CS a DEC0 a ( lo_WR + lo_RDl:
:Delayed Read .... Wrlte Decodes:
WR
lo_WR a FILT:
RD
I o_RD a FI LT:
TLlH/11711-26

FIGURE. 14. Logic Equations Used to Program the GAL 16V8

1-180

riii:
.....

6.0 Application Circuits (Continued)

I\)

r.a:o.
en
.a:o.
.....
riii:
.....

ADDRESS SELECTOR
S.I
Addr•••
D.cod.
0
100
1
120
140
2
3
160
4
180
lAO
5
6
lCO
7
xxx
8
300
9
xxx
A
340
B
xxx
280
C
D
2AO
E
xxx
F
xxx

SEL3
SEL2
SEll

I\)

r.a:o.

~DBUFEN

U1

CD
~CS

~RD

~WR

~IOR
~IOW

TUHI11711-27

FIGURE 15. GAL Functional Block Diagram

L.M12458/4

REV D

EVAL BRD
Rl

-c:J-

C6

I2Ml National

~ Semiconductor

~

C14DD

-

SW8
1

+

C2

Cl

ulD

u2D

0

DDD

C16 C17 C18

C3

u3D

L1

Dl

U6

C19

C20

DO
+

D
....,IT"'II'''II'""...

OD

C21 C22

+
COMP. SIDE

A31

O
AGND

DGND
Al

19

TLIHIl1711-2B

FIGURE 16. Silk-Screen Layout Showing Parts Placement on the LM12(H)454/8 Evaluatlon/lnterface Board

1·181

•

:g
~

C'I
....

:i
.....
'01'

an
~

C'I
....

:;

6.0 Application Circuits (Continued)

•

.~

r:

•

•

•••
••

•••

•
•

••• • • ••
•
••

•

·---

• •

TL/H/11711-29

FIGURE 17. LM12(H)454/8 Evaluation/Interface Board Component·Side Layout Positive

1·182

r-----------------------------------------------------------------------------'r
iii:
....
6.0 Application Circuits (Continued)
N

s::

(J1

.0.

......

r
iii:

....

•.,-, •
e,-'
•--- •• • • .,-,
•--- ••
• • •!
'.-:

N

r.0.

WI

• • 0.".:

•••

~

0

'.."",'.

eo~.

•
•••
•• ••
•• ••

0
0
0

• --

0

0

..

•• •••••
•••
••
••
••
•••
,-, ••
'.-,'.
••
•• 0:: ,-,
.- .-. ••
••••••••
•
••••••
,

•

•

••
.-•- •---• •

0

0

•

.-- .-• •

0
.0.-:.

0

.,-,

-

.--

0

.::.

•

••
••

••••
•• •••
•• ••
•• •.-:
'

••
••
•••
•
• •

•
• .,-,

••
•••
••
•• •
•

•

.,-,

•• •.
• •
••• '•.::
•• •.-:
•. • ••
' """

-~

I ..

.

' -,'

'

'. "",.

•••
••
•

••

'..:

•

•
TL1H/11711-30

FIGURE 18. LM12(H)454/8 Evaluation/Interface Board Ground-Plane Layout Negative

1-183

6.0 Application Circuits (Continued)

'.

••

:-l'.J. /

•
.......
----.......
......

••• ••
•
• •

...
Q

iii

•

•

•
..

•".,..---"

••
••
•

••
••
•
•••
•

....

:5

~,

t3

831

TVH/11711-31

FIGURE 19. LM12(H)454/8 Evaluation/Interface Clrcuit-5lde Layout Positive

1·184

Section 2
Analog-to-Digital
Converters

Section 2 Contents
Analog·to·Digital Converters Definition of Terms. . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . .
Analog·to·Digital Converters Selection Guide •..••..•....•.............••..•...•.......
ADC0800 8·Bit AID Converter •..••. . • . . . . . • • . . . . . . . . . . . . . . . . . . . • . . • . . . . . . • . . . • . . . . . .
ADC0801 / ADC0802/ADC0803/ADC0804/ ADC0805 8·Bit ,...p Compatible AID Converters . .
ADC0808/ ADC0809 8·Bit,...P Compatible AID Converters with 8·Channel Multiplexer. . . . . . .
ADC0811 8·Bit Serial I/O AID Converter with 11·Channel Multiplexer.....................
ADC0816/ ADC0817 8·Bit ,...p Compatible AID Converters with 16·Channel Multiplexer. . . . • .
ADC0819 8·Bit Serial I/O A/D Converter with 19·Channel Multiplexer. . • . • . . . • . • . . . • • . . . . .
ADC0820 8·Bit High Speed ,...p Compatible AID Converter with Track/Hold Function. . • . • • . .
ADC0831 / ADC0832/ ADC0834 and ADC0838 8·Bit Serial I/O AID Converters with
Multiplexer Options ••..•.••...•...•.. '. '. . . . . . . . . . . • . . . • . . • . . . . . . . . . . . . . . . . . . . . . . . ..
ADC0833 8·Bit Serial I/O AID Converter with 4·Channel Multiplexer • • • . . • . . . • . • • . . • • . . . ..
,ADC08031 / ADC08032/ ADC08034/ ADC08038 8·Bit High·Speed Serial I/O AID Converters
with Multiplexer Options, Voltage Reference, and Track/Hold Function. . • . • . . . . . . • . • . . . •
ADC08 131/ADC08134/ADC08138 8·Bit High-Speed Serial I/O AID Converters with
Multiplexer Options, Voltage Reference, and Track/Hold Function..... ...•.. ...........
ADC08231/ ADC08234/ ADC08238 8·Bit 2 ,...s Serial I/O A/D Converters with MUX,
Reference, and Track/Hold. • • • . • . • . • • . • • • • . • . . . . • . . . • . . . . . . • . . . . . . • . . • • . . . . . • • . . •.
ADC0841 8.Bit,...P Compatible A/D Converter. . . . • . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . ..
ADC0844/ADC0848 8·Bit ,...p Compatible A/D Converters with Multiplexer Options .........
ADC0852/ADC0854 Multiplexed Comparator with 8·Bit Reference Divider. . . . • . . • . . . . . . . ..
ADC08061 / ADC08062 500 ns AID Converter with S/H Function and Input Multiplexer. . . • ..
ADC08161 500 ns AID Converter with S/H Function and 2.5V Bandgap Reference. . • • . . . • .
ADC1001 10·Bit,...P Compatible AID Converter ............•............••.........•...
ADC1005 1O·Bit ,...p Compatible AID Converter ........................................
ADC10154, ADC10158 10·Bit Plus Sign 4,...s ADCs with 4· or 8·Channel MUX, Track/Hold
and Reference. • . . . . . . . . . . . . . . • . • . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . • . . . . . . . • . . . . • . .•
ADC1 031/ ADC1 034/ADC1 038 1O·Bit Serial I/O AID Converters with Analog Multiplexer and
Track/Hold Function. • . . . . . . . • • . . . • . . . • . . . . . . . . . . • . . . . . • • • . . • • . . • . . . . • . . . . . . . . . . . .
ADC1 0731 / ADC1 0732/ADC1 0734/ ADC1 0738 10·Bit Plus Sign Serial I/O AID Converters
with MUX, Sample/Hold and Reference. . . . • • . . . . • . . . . • . • . . • . . . . . . . . . • . . . • • . . . . . . . ..
ADC1 0831/ ADC1 0832/ ADC1 0834/ ADC1 0838 10·Bit Plus Sign Serial I/O AID Converters
with MUX, Sample/Hold and Reference. . • . • . • . . • . • . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ADC1061 10·Bit High·Speed ,...P·Compatible AID Converter with Track/Hold Function ......
ADC1 0061/ ADC1 0062/ ADC1 0064 10·Bit 600 ns A/D Converters with Input Multiplexer and
Sample/Hold . • . . • . . . . • • . . • • . • . . . . . . . • • . • • . . . • . • • • • . . • . . . • • . . • . . • . . . . . . . . . . . . . • ..
ADC1 0461 / ADC1 0462/ ADC1 0464 1O·Bit 600 ns AID Converter with Input Multiplexer and
Sample/Hold . • • . . • • . . • . . . . . . • • . . . • . . • . . • . • . . . • . . . . . . . . . . . • . . . • . . . • . . . . • . . . . . . . . .
ADC1 0662/ ADC1 0664 1O·Bit 360 ns AID Converters with Input Multiplexer and
Sample/Hold . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . • . . . • . . . . . . . . . . . . . . . . . . . . . . . .
ADC12H030/ ADC12030/ ADC12H032/ ADC12032/ ADC12H034/ ADC120341 ADC12H038/
ADC12038 Self·Calibrating 12·Bit Plus Sign Serial I/O AID Converters with MUX and
Sample/Hold . • . • . . . • . . . . • . • • . • . • . • • • • • • . . • • . . . • . . . . . . . . . . . . . . . . . . . . . . . . • . . . • . . ..
ADC12L030/ADC12L032/ ADC12L034/ADC12L038 3.3V Self·Calibrating 12·Bit Plus Sign
Serial I/O AID Converters with MUX and Sample/Hold. . . . • . . • . . • • • . • . . • • . . . . . . . . . . . ..
ADC12130/ADC12132/ADC12138 Self·Calibrating 12·Bit Plus Sign Serial 110 AID
Converters with MUX and Sample/Hold. • • • • • • • • • • • • • • • • . . . . . . . . . . . . . . . . . . . . . . . . • . . .
ADC1205/ ADC1225 12·Bit Plus Sign ,...p Compatible AID Converters . . . . . . . . • . • . . . . . . . . . .
2·2

2-4
2·6
2·10
2·19
2·51
2·62
2·73
2·84
2·94
2·110
2·136
2·154
2·174
2·193
2·213
2·225
2·242
2·259
2·273
2·289
2·296
2·307
2·329
2·342
2·367
2·392
2·402
2·415
2·428

2·441
2·478
2·512
2·548

Section 2 Contents (Continued)
ADC12062 12-Bit, 1 MHz, 75 mW A/D Converter with Input Multiplexer and Sample/Hold. . . .
ADC12662 12-Bit, 1.5 MHz, 200 mW AID Converter with Input Multiplexer and Sample/Hold.
ADC1241 Self-Calibrating 12-Bit Plus Sign ,...P-Compatible AID Converter with Sample/Hold.
ADC124212-Bit Plus Sign Sampling AID Converter................. ...•......•....... ..
ADC12441 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign AID Converter with
Sample/Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC1251 Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample/Hold. . . . . . . . . . . . . . •
ADC12451 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign AID Converter with
Sample/Hold . . . . . . . . . . . . . . . . . . . • . . . . • • . • . . • • . . . . . . . . • • • . . . • . . . . . . • • . . . . . . . • . . . • .
ADC16071 / ADC16471 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converters ...••.....
LM131A1LM131, LM231 AlLM231, LM331 AlLM331 Precision Voltage-to-Frequency
Converters ........... . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-3

2-565
2-583
2-602
2-615
2-628
2-641
2-656
2-672
2-690

~

~
~
c
o

o
c
.....

1...
E

tflNation~1

Semi'.condu.ctor

Definition Of Terms
AID Converters

~

'0
c

o

:0=

-2

~

LSB (Least-Significant Bit): In a binary coded system this
is the bit that carries the .smallest value or weight. Its value
is the full scale voltage (or current) divided by 2n, where n is
the resolution of the converter.
Missing Codes: When an incremental increase or decrease
in input voltage causes the converter to increment or decrement its numeric output by more than one LSB the converter is said to exhibit "missing codes". If there are missing
codes, there are digital codes which cannot be reached by
any input voltage value.

Conversion Time: The time required for a complete measurement by an analog-to-digital converter. Since the Conversion Time does not include acquisition time, multiplexer
set up time, or other elements of a complete conversion
cycle, the conversion time may be less than the Throughput
Time.
DC Common-Mode Error: This specification applies to
ADCs with differential inputs. It is the change in the output
code that occurs when the analog voltages on the two inputs are changed by an equal amount. It is expressed in
LSBs.
Differential Nonlinearity (DNL): Differential non-linearity is
a measure of the worst case deviation from the ideal 1 LSB
input voltage span that is associated with each output code.
Differential non-linearity may be expressed in fractional bits
or as a percentage of full scale. A differential non-linearity
greater than 1 LSB will lead to missing codes in an ADC.

MSB (Most Significant Bit): In a binary coded system this
is the bit that has the largest value or weight. Its value is one
half of full scale.
Offset Error (Zero Error): This is the difference between
the ideal input voltage (% LSB) and the actual input voltage
that is needed to make the transition from zero to 1 LSB. All
the digital codes in the transfer curve are offset by the same
value. Offset error is usually expressed in LSBs.

Dynamic Specifications: The specifications of an ADC pertaining to an AC input signal. These include SIN ratio, SNR,
SINAD, S/(N+D), ENOB, THD,IMD, FPBW, and SSBW.
Effective Number of Bits (ENOB): The ENOB of an ADC is
determined from a measurement of its SINAD and the following equation: ENOB = (SINAD - 1.76)/6.02. This specification combines the effects of many of the other dynamic
specifications; errors resulting from dynamic differential and
integral nonlinearity, missing codes, THD, and aperture jitter
show up in ENOB.
Full Power Bandwidth (FPBW): The frequency at which
the SIN ratio has dropped by 3 dB (relative to its low frequency level) for an input signal that is at or near full-scale.
This corresponds to a drop in ENOB by 'Iz bit relative to its
low frequency level.
Gain Error (Full Scale Error): The difference (usually expressed in LSBs) between the input voltage that should
ideally produce a full scale output code and the actual input
voltage that produces that code.

Peak Harmonic: The amplitude, relative to the fundamental, of the largest harmonic resulting from the AID conversion of an AC signal.
Power Supply Sensitivity: The sensitivity of a converter to
changes in the dc power supply voltages.
Quantization Error: The error inherent in all AID conversions. Since even an "ideal" converter has finite resolution,
any analog voltage that falls between two adjacent output
codes will result in an output code that is inaccurate by up to
% LSB.
Ratiometrlc Operation: Many A/D applications require a
stable and accurate reference voltage against which the input voltage is compared. This approach results in an absolute conversion. Some applications, however, use transducers or other signal sources whose output voltages are
proportional to some external reference. In these ratlometric applications, the reference for the signal source should
be connected to the reference input of the converter. Thus,
any variations in the source reference voltage will also
change the converter reference voltage and produce an accurate conversion.
Resolution: The smallest analog increment corresponding
to a 1 LSB converter code change. For converters, resolution is normally expressed in bits, where the number of digital codes is equal to 2n. As an example, a 12-bit converter
maps the analog signal into 212 = 40S11 digital codes.

Gain Temperature Coefficient (Full Scale Temperature
Coefficient): Change in gain error divided by change in
temperature. Usually expressed in parts per million per degree Celsius (ppm/oC).
Integral Nonlinearity (Linearity Error): Worst case deviation of an ADC transfer function from the line between the
ADC's measured endpOints (zero and full scale). Can be
expressed as a percentage of full scale or in fractions of an
LSB. This specification is commonly referred to as INL or
ILE.
Intermodulation Distortion (IMD): Two nearby frequency
components in a signal will interact through the nonlinearities in an ADC to produce signal at additional frequencies.
IMD is commonly defined as the ratio of the rms sum of the
distortion product amplitudes to the rms sum of the input
frequency amplitudes.

Signal-ta-Noise Ratio (SIN or SNR): The ratio of the signal amplitude to the background noise level. The background noise is determined by integrating the noise spectral
density over the bandwidth of interest.
SINAD (Slgnal-to-Nolse + Distortion RatiO): Similar to
the SIN ratio, the SINAO includes harmonic distortion components as part of the noise. (See S/(N + 0)

2-4

Total Harmonic Distortion (THD): Due to inherent nonlinearities even in an ideal ADC transfer function, ADC's will
produce harmonics of the input signal frequency. THD is
defined as the ratio of the rms sum of the harmonic distortion product amplitudes to the input signal amplitude.
Throughput Rate: The maximum continuous conversion
rate of the ADC.
Throughput Time: The inverse of the Throughput Rate.

SIN+D (Slgnal-to-Nolse + Distortion Ratio): Similar to
the SIN ratio, the SIN + D includes harmonic distortion
components as part of the noise. (See SINAD)
Small Signal Bandwidth (SSBW): The frequency at which
the SIN ratio has dropped by 3 dB (relative to its low frequency level) for an input signal that is much smaller than
the full-scale input (20 dB or 40 dB below full-scale, for example).
Static Specifications: The specifications of an ADC pertaining to a DC signal input. These include gain error, offset
error, and differential and integral linearity errors.

Total Unadjusted Error (TUE): The maximum deviation of
the voltage corresponding to the center of a digital code's
associated input voltage span from the ideal case. Total
unadjusted error includes offset error, gain error, and differential and integral nonlinearity errors.

2-5

AID Converter Selection Guide
Part
No.

1/0
Type

Res'
(Bits)

ADC0801

Parallel

ADC0802

Parallel

ADC0803

Conversion
Time (Max)

Accuracy
(Max)

# MUX

8

110/Ls

±y. LSB

1

8

110/LS

±%LSB

1

Parallel

8

110/Ls

±%LSB

ADC0804

Parallel

8

110/LS

ADC080S

Parallel

8

110/LS

ADC0808

Parallel

8

ADC0809

Parallel

8

100/Ls

±1 LSB

8

ADC0816

Parallel

8

1(') /Ls

±%LSB

16

ADC0817

Parallel

8

100/Ls

±1 LSB

16

N

N

+SV

ADC0800

Parallel

8

SO /Ls

±2 LSB

1

N

N

+SV, -12V

100/LS

On-Board

Supply
Voltage

N

N

N

N

1

N

±1 LSB

1

±1 LSB

1

±%LSB

Inputs

8

Temp
Range

Power
(mWMax)

+SV

I,M

9mW

J, N

Differential Input

+SV

C,I,M

9mW

J, N,M, V

Differential Input

N

+SV

C,I,M

9mW

J, N,M, V

Differential Input

N

N

+SV

C,I

12.SmW

J, N,M, V

Differential Input

N

N

+SV

I

9mW

N

Ratiometric Operation

N

N

+SV

I,M

1SmW

J, N, V

N

N

+SV

I

1SmW

N,V

N

N

+SV

I

1SmW

J, N

I

1SmW

N

C,M

100mW

J

SIH Reference

Packages

Comments

~
~

~

.....

....
Q

;:

»
.......
C
00(")
°0

ADC0841B

Parallel

8

40/Ls

±%LSB

1

N

N

+SV

C,I

13mW

N,V

ADC0841C

Parallel

8

40/Ls

±1 LSB

1

N

N

+SV

C,I

13mW

N,V

ADC0844B

Parallel

8

40/Ls

±%LSB

4

N

N

+5V

C,I

13mW

J, N

ADC0844C

Parallel

8

40/Ls

±1 LSB

4

N

N

+5V

C,I

13mW

J, N

ADC0848B

Parallel

8

40/Ls

±%LSB

8

N

N

+5V

C,I

13mW

J,N,V

ADC0848C

Parallel

8

40/Ls

±1 LSB

8

N

N

+5V

C,I

13mW

J,N, V

I\)

ADC0811B

Serial

8

32/LS

±%LSB

11

N

N

+5V

I,C

15mW

N,V

~.,

cD

ADC0811C

Serial

8

32/LS

±1 LSB

11

N

N

+5V

I,C

15mW

J,N, V

Sen

ADC0831B

Serial

8

32/LS

±%LSB

1

N

N

+5V

C

15mW

J, N

cHD
:::J-

m(l)

ADC0831C

Serial

8

32/Ls

±1 LSB

1

N

N

+5V

C,I

1SmW

J,N,M

ADC0832B

Serial

8

32/LS

±%LSB

2

N

N

+5V

C,I

32mW

N,M

ADC0832C

Serial

8

32/LS

±1 LSB

2

N

N

+5V

C,I

32mW

N,M

ADC0833B

Serial

8

32/LS

±%LSB

4

N

N

+5V

C

15mW

N

ADC0833C

Serial

8

32 fLs

±1 LSB

4

N

N

+5V

C,I

15mW

J, N

ADC0834B

Serial

8

32 fLs

±%LSB

4

N

N

+5V

C

15mW

N

ADC0834C

Serial

8

32 fLs

±1 LSB

4

N

N

+5V

C,I

15mW

J,N,M

ADC0838B

Serial

8

32 fLs

±%LSB

8

N

N

+5V

C,I

15mW

J,N,V

ADC0838C

Serial

8

32 fLs

±1 LSB

8

N

N

+5V

C,I

15mW

J,N,M, V

ADC0819B

Serial

8

16 fLs

±%LSB

19

N

N

+5V

C

15mW

N,V

ADC0819C

Serial

8

16 fLs

±1 LSB

19

N

N

+5V

C,I

15mW

N,V

ADC08031B

Serial

8

8/Ls

±%LSB

1

Y

Y

+5V

I

20mW

N,M

Cerdip
Package Codes: J
H
Metal Can
N
Plastic Dip
M Small Outline
-

V
MS
VF

PLCC
SSOP
PQFP

Temperatures:

C
I
M

O·Cto +70·C
-25·Cto + 85·C
or -40·Cto +85·C
- 55·C to + 125·C

~~
0..<

~CD
JJ~
(0

CD

:::In
0.._
(J)

O·

-g~

~G)

_.

C

Co

(I)

~

V)

ce

....~
(')

0

;:s
~

:;:!
(')

......
0
""'I

~

1/0

Part
No.

Type

Res' Conversion Accuracy #MUX
On-Board Supply Temp
Power
S/H
(Bits) Time (Max)
(Max)
Inputs
Reference Voltage Range (mWMax)

ADCOB031C

Serial

B

B p.s

±1 LSB

1

ADCOB032B

Serial

B

B p.s

±%LSB

2

ADCOB032C

Serial

B

B p.s

±1 LSB

2

ADCOB034B

Serial

B

"'S

4

ADCOB034C

Serial

B

B
B P.s

±%LSB
±1 LSB

4

ADCOB03BB

Serial

B

B p.s

±%LSB

B

ADCOB03BC

Serial

B

B p's

±1 LSB

B

ADCOB131B

Serial

B

B p.s

±%LSB

1

ADCOB131C

Serial

B

B p.s

±1 LSB

1

ADCOB134B

Serial

B

B p.s

±%LSB

4

ADCOB134C

Serial

B

B p.s

. ±1 LSB

4

ADCOB13BB

Serial

B

B p.s

±%LSB

B

ADCOB13BC

Serial

B

B p's

±1 LSB

B

ADCOB231B

Serial

B

2 p.s

±%LSB

B

ADCOB231C

Serial

B

2 p.s

±1 LSB

B

ADCOB234B

Serial

B

2 p.s

±%LSB

B

ADCOB234C

Serial

B

2 p.s

±1 LSB

B

Packages

Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y

+5V

C,I,M

20mW

J,N,M

+5V

I

20mW

N,M

+5V

I

20mW

N,M

Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y

+5V

I

20mW

N,M

+5V

I

20mW

N,M

+5V

I

20mW

N,M

+5V

I,M

20mW

J,N,M

+5V

I

20mW

N

Guaranteed Reference O/P

+5V

I

20mW

N

Guaranteed Reference O/P

+5V

I

20mW

N,M

Guaranteed Reference O/P

+5V

I

20mW

N,M

Guaranteed Reference O/P

-

+5V

I

20mW

N,M

Guaranteed Reference O/P

G)

+5V

I

20mW

N,M

Guaranteed Reference O/P

+5V

I

20mW

N,M

a:CD

+5V

I

20mW

N,M

y

+5V

I

20mW

N,M

Y
Y
Y

+5V

I

20mW

N,M

N

Serial

B

2 p.s

±1 LSB

B

ADCOB20B

Parallel

B

1.2 p.s

±%LSB

1

ADCOB20C

Parallel

B

1.2 p.s

±1 LSB

1

ADCOB061B

Parallel

B

560 ns

±%LSB

1

ADCOB061C

Parallel.

B

560 ns

±1 LSB

1

ADCOB062B

Parallel

B

560 ns

±%LSB

2

ADCOB062C

Parallel

B

560 ns

±1 LSB

2

ADCOB161B

Parallel

B

560 ns

±%LSB

1

ADCOB161C

Parallel

B

560 ns

±1 LSB

1

Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y

ADC1021C

Parallel

10

200 p.s

±1 LSB

1

N

N

+5V

C,I

25mW

J, V

ADC1001

Byte-Wide

10

50 p.s

±1 LSB

1

N

N

+5V

C,I

25mW

J

ADC1005B

Byte-Wide

10

"'S

±%LSB

1

N

N

+5V

C,I

15mW

J

ADC1005C

Byte-Wide

10

±1 LSB

1

N

N

+5V

C,I

15mW

J, V

ADCOB23BB
ADCOB23BC

Serial

B

2 p's

50
50 p.s

Package Codes: J
Cerdip
H
Metal Can
N
Plastic Dip
M Small Outline

V
MS
VF

±%LSB

B

PLCC
SSOP
PQFP

»
......

Comments

C
0
0

::::s

-...
<

...CD
CD

(IJ

::::s

r:::

:::l

c:

CD

So

20mW

+5V

I,M

20mW

J,N,M

+5V

C,I

75mW

N,M,V

N

+5V

C,I

75mW

J,N,M,V,MS

N

+5V

I

100mW

N.M

High Speed Upgrade forADCOB20

N

+5V

I,M

100mW·

J,N,M

High Speed Upgrade for ADCOB20

N

+5V

I

100mW

N,M

N

+5V

I

100mW

N,M

N

+5V

I

100mW

N,M

ADCOB061 with On-Board Reference

N

+5V

I

100mW

N,M

ADCOB061 with On· Board Reference

M

O·

0

+5V

C
I

CD

a
a

I

Temperatures:

CD

()

N,M

O"Cto +70'C
- 25'C to + B5'C
or -40'Cto +B5'C
- 55'C to + 125'C
----

ep!n~

UO!I09Ies JeIJeAUO~ a/v

AID Converter Selection Guide
Part
No.
ADC1031

I\)

Co

Conversion Accuracy #MUX
Time (Max)
(Max)
Inputs

I/O
Type

Res'
(Bits)

Serial

10

13.7,...s

±1 LSB

1

5tH

On-Board
Reference

Supply
Voltage

Temp Power
Packages
Range (mWMax)

Y

N

+5V

I

15mW

N

ADC1034

Serial-

10

13.7,...s

±1 LSB

4

Y

N

+5V

I,M

15mW

J,N,M

ADC1038

Serial

10

13.7,...s

±1 LSB

8

N

+5V

I,M

15mW

J,N,M

N

+5V

I,M

235mW

J,N,M

Comments

»

......
C
0
0
:::J

ADC1061

Parallel:

10

1.8,...s

±2LSB

1

y
y-

ADC10061

Parallel

10

900 ns

±1 LSB

1

Y

N

+5V

I,M

235mW

J,N,M

1 MSt s Throughput

ADC10062

Parallel

10

900 ns

±1 LSB

2

Y

N

+5V

I,M

235mW

J,N,M

1 MSt s Throughput

ADC10064

Parallel

10

900 ns

±1 LSB

4

Y

N

+5V

I,M

235mW

J,N,M

1 MSt s Throughput

ADC10461

Parallel

10

- 900 ns

±1 LSB

1

Y

N

+5V

I

235mW

N,M

AC Tested Version of ADC10061

ADC10462

Parallel

10

900 ns

±1 LSB

2

Y

N

+5V

I

235mW

N,M

AC Tested Version of ADC10062

ADC10464

Parallel

10

900 ns

±1 LSB

4

Y

N

+5V

I

235mW

N,M

AC Tested Version of ADC10064

ADC10664

Parallel

10

466 ns

±1.5LSB

4

Y

N

+5V-

I

235mW

N,M

AC Tested, 2 MSts Throughput

ADC10662 - Parallel

10

466ns

±1.5LSB

2

Y

N

+5V

I

235mW

N,M

AC Tested, 2 MSts Throughput

10 + Sign

5,...s

±1 LSB

1

Y

Y

+5V

I

37mW

N,M

Software Power-Down to 18,...W

...<
...
CD
CD

en
CD

CD

n

O·

:::J
G)

c

c:CD

ADC10731

Serial

ADC10732

Serial

10 + Sign

5,...s

±1 LSB

2

Y

Y

+5V

I

37mW

N,M

Software Power·Down to 18,...W

ADC10734

Serial

10 + Sign

5,...s

±1 LSB

4

Y

Y

+5V

I-

37mW

N,M

Software Power-Down to lB,...W

ADC10738

Serial

10 + Sign

5,...s

±1 LSB

8

Y

Y

+5V

I

37mW

N,M

Software Power-Down to lB,...W

3-

ADC10B31

Serial

10 + Sign

5,...s

±1 LSB

1

Y

Y

±5V

I-

59mW

N,M

Software Power-Down to 33 ,...W

c::

ADC10832

Serial

10 + Sign

5,...s

±1 LSB

2

Y

Y

±5V

I

59mW

N,M

Software Power-Down to 33 ,...W

ADC10B34

Serial

10 + Sign

5,...s

±1 LSB

4

Y

Y

±5V

I

59mW

N,M

Software Power-Down to 33- ~W

-ADC10838

Serial

10 + Sign

5,...s

±1 LSB

8

Y

Y

±5V

I

59mW

N,M

SoftWare Power-Down to 33,...W

4.4,...s

±1 LSB

4

Y

Y

+5V, ±5V

I

33mW

N,M

ADC10154

Byte-Wide 10 + Sign

ADC1015B

Byte-Wide 10 + Sign

4.4,...s

±1 LSB

B

Y

y

+5V, ±5V

I

33mW

N,M

ADC12062B

Parallel

12

9BOns

±1 LSB

2

Y

N

+5V

I

75mW

V,VF

ADC12062C

Parallel

12

9BOns

Y

N

+5V

I-

75mW

V,VF

Parallel

12

660ns

±1'h LSB
±1'h LSB

2

ADC12662

2

Y

N

+5V

I

200mW

V,VF

ADC1205C

Parallel

12 + Sign

100,...s

±1 LSB

1

N

N

+5V, ±5V

C,I

235mW

J

ADC1225

Parallel

12 + Sign

100,...s

±1 LSB

1

N

N

+5V, ±5V

C,I

235mW

J

ADC1241B

Parallel

12 + Sign

13.8,...s

±'hLSB

1

Y

N

+5V, ±5V

I

70mW

J

Self Calibrating

ADC1241C

Parallel

12 + Sign

13.B,...s

±1 LSB

1

Y

N.

+5V, ±5V

I,M

70mW

J

Self Calibrating

ADC12441

Parallel

12 + Sign

13.8,...s

±1 LSB

1

Y

N

+5V,±5V

I

70mW

J

ACTested

ADC12030

Serial

12 + Sign

8.Bp.S

±1 LSB

2

Y

N

+5V

I

33mW

N,M

Software Power-Down to 100 ,...W

PLCC
SSOP
POFP

Temperatures:

Package Codes: J

Cerdip
MetalCen
N
PlasiicDip
M Small Outline

H

V
MS
VF

C
I
M

O'Cto +70'C
- 25'C to + 85'C
or -40'Cto + 85'C
-55'Cto + 125'C -

'0
0
5CD

.s

Part
No.

1/0
Type

Res'
(Bits)

Conversion
Time (Max)

Accuracy
(Max)

# MUX

ADC12032

Serial

12 + Sign

8.8 p,s

±1 LSB

ADC12034

Serial

12 + Sign

8.8 p,s

ADC12038

Serial

12 + Sign

8.8 p,s

ADC12L030

Serial

12 + Sign

ADC12L032

Serial

12 + Sign

ADC12L034

Serial

ADC12L038

Serial

ADC1251B

I\)

StH

On-Board
Reference

Supply
Voltage

2

Y

N

+5V

I

33mW

N,M

Software Power·Down to 100 p,W

±1 LSB

4

Y

N

+5V

I

33mW

N,M

Software Power·Down to 100 p,W

±1 LSB

8

Y

N

+5V

I

33mW

N,M

Software Power·Down to 100 p,W

8.8 p,s

±1 LSB

2

Y

N

+5V

I

15mW

N,M

3V Guaranteed Operation

8.8 p,s

±1 LSB

2

Y

N

+5V

I

15mW

N,M

3V Guaranteed Operation

12 + Sign

8.8 p,s

±1 LSB

4

Y

N

+5V

I

15mW

N,M

3V Guaranteed Operation

12 + Sign

8.8 p,s

±1 LSB

8

Y

N

+5V

I

15mW

N,M

3V Guaranteed Operation

Inputs

Temp Power
Packages
Range (mWMax)

»

Comments

Byte·Wide 12 + Sign

7.7 p,s

±%LSB

1

Y

N

+5V, ±5V

I

113mW

J

Self Calibrating

ADC1251C Byte·Wide 12 + Sign

7.7 p,s

±1 LSB

1

Y

N

+5V, ±5V

I,M

113mW

J

Self Calibrating

ADC12451

7.7 p,s

±1 LSB

1

Y

N

+5V, ±5V

I

113mW

J

ACTested

12 + Sign

5.5 p,s

±1 LSB

2

Y

N

+5V

I

36mW

N,M

Software Power·Down to 100 p,W

Byte·Wide 12 + Sign

ADC12H032

Serial

12 + Sign

5.5 p,s

±1 LSB

2

Y

N

+5V

I

36mW

N,M

Software Power·Down to 100 p,W

ADC12H034

Serial

12 + Sign

5.5 p,s

±1 LSB

4

Y

N

+5V

I

36mW

N,M

Software Power·Down to 100 p,W

ADC12H038

Serial

12

+ Sign

5.5 p,s

±1 LSB

8

Y

N

+5V

I

36mW

N,M

Software Power·Down to 100 p,W

ADC16071

Serial

16

192 kSts SINAD: 72 dB

1

Y

N

+5V

I

500mW

N,M

Delta Sigma Architecture

ADC16471

Serial

16

192 kS/s SINAD: 72 dB

1

Y

Y

+5V

I

500mW

N,M

Delta Sigma Architecture

Frequency

V·F

1

N/A

N

30mW

N,M,H

V to F Converter, 100 kHz Max

0.01%

+5Vto +40V C,I,M

<
(I)

""I

(I)
""I

en
(I)
CD

0'

Serial

N/A

0
0
:::s

n

ADC12H030

LM131

.......
C

:::s

C)
C

a:
(I)

'0
0
::J

g.
c

 Crf!

C) r-------------------------------------------------------------------------------~
C)

~

t!lNational Semiconductor

ADC0800 8-Bit AID Converter
General Description

Features

The ADC0800 is an 8-bit monolithic AID converter using Pchannel ion-implanted MOS technology. It contains a high
input impedance comparator, 256 series resistors and analog switches, control logic and output latches. Conversion is
performed using a successive approximation technique
where the unknown analog voltage is compared to the resistor tie points using analog switches. When the appropriate tie pOint voltage matches the unknown voltage, conversion is complete and the digital outputs contain an 8-bit
complementary binary word corresponding to the unknown.
The binary output is TRI-STATEIlb to permit bussing on common data lines.

• Low cost
• ± 5V, 10V input ranges
• No missing codes
• Ratiometric conversion
• TRI-STATE outputs
•
•
•
•
•
•
•
•

The ADC0800PD is specified over -55'C to + 125'C and
the ADC0800PCD is specified over O'C to 70'C.

TC=50 p.s,

Fast
Contains output latches
TIL compatible
Supply voltages
Resolution
Linea:rity
Conversion speed
Clock range

5 Voc and -12 Voc
8 bits
±1 LSB
40 clock periods
50 to 800 kHz

Block Diagram
Vss

(PMOS
BODY)

R-NETWORK
TOP
15

r
I

I
:

I

...

-t----------...-"'="='==~~----P-RESISTOR
N.aODY

r- -

450

I
I

r-_ _~~11~ CLOCK

-,

300~_+-1~_
I ~~~~;S

J_

SELECTION,
AND
CONTROL
LOGIC

I

I

10

END OF

300

1-+-0 CONVERSION
(EOC)

150
L . . -.....-o-vGG

I

I
I
L

I-BIT'
LATCH

5--R·NETWORK
BOTTOM

-.J

12

4

3 Z 1

MSB

VIN
ANALOG
INPUT

DIGITA;:=;;ROUND

17 16 14 13

LSB
COMPLEMENTARY
DIGITAL OUTPUT
TUH/5670-1

(00000000 =

+ lull-scale)

2-10

~

C

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Voo)
Vss-22V
Supply Voltage (VGG)
Vss-22V
Voltage at Any Input
Vss+0.3VtoVss-22V
Input Current at Any Pin (Note 2)
5mA
Package Input Current (Note 2)
20mA

(")

Power Dissipation (Note 3)
ESD Susceptibility (Note 4)
Storage Temperature
Lead Temperature (Soldering, 10 sec.)

875mW
500V
150'C
300'C

Operating Ratings (Note 1)
TMIN ~ TA ~ TMAX
-55'C ~ TA ~ +125'C
O'C ~ TA ~ +70'C

Temperature Range
ADC0800PD
ADC0800PCD

Electrical Characteristics
These specifications apply for Vss=5.0 VOC, VGG= -12.0 VOC, Voo=O Voc, a reference voltage of 10.000 Voc across the
on-chip R-network (VR.NETWORK TOP = 5.000 Voc and VR.NETWORK BonOM= -5.000 Voc), and a clock frequency of 800
kHz. For all tests, a 4750 resistor is used from pin 5 to VR.NETWORK BonOM = -5 Voc. Unless otherwise noted, these
specifications apply over an ambient temperature range of - 55'C to + 125'C for the ADC0800PD and O'C to + 70'C for the
ADC0800PCD.
Conditions

Max

Units

±1
±2

LSB
LSB

Differential Non-Linearity

±1f2

LSB

Zero Error

±2

LSB

(Note 9)

0.01

%I'C

±2

LSB

(Note 9)

0.01

%/'C

1

p.A
V

Parameter
Non-Linearity

Zero Error Temperature Coefficient

Min

TA=25'C, (Note 8)
Over Temperature, (Note 8)

Full-Scale Error
Full-Scale Error Temperature Coefficient
Input Leakage

Typ

Logical "I" Input Voltage

All Inputs

Vss-l.0

VSS

Logical "0" Input Voltage

All inputs

VGG

Vss-4.2

V

Logical Input Leakage

TA= 25'C, All Inputs, VIL =
Vss-l0V

1

ItA

Logical "I" Output Voltage

All Outputs, IOH = 100 p.A

Logical "0" Output Voltage

All Outputs, IOL = 1.6 mA

Disabled Output Leakage

TA = 25'C, All Outputs, VOL =
Vss@10V

Ciock Frequency

O'C~TA~+70'C

-55'C~TA~+125'C

Clock Pulse Duty Cycle

2.4

V

2

p.A

50
100

800
500

kHz
kHz

40

60

%

1

p.s

31f2

Clock
Periods

TRI-STATE Enable/Disable Time
Start Conversion Puise

(Note 10)

V
0.4

1

20
mA
Power Supply Current
TA=25'C
Note 1: Absolute Maximum Ratings Indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.

Nole 2: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < Y- or YIN> Y+) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 rnA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAXo BJA. and the ambient temperature. TA. The maximum
allowable power dissipation at any temperature is Po = (TJMAX - TAl/BJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX = 125"C. and the typical junction·to-ambient thermal resistance of the AOCOBOOPD and ADCOBOOPCD when board mounted Is WC/W.
Nole 4: Human body model. 100 pF discharged through a 1.5 kn resistor.
Nole 5: Typlcals are at 25"C end represent most likely parametric norm.
Note 6: Tested limits are guaranteed to National's AOOL (Average Outgoing Quality Level).
Note 7: Oeslgn limits are guaranteed but not 100% tested. These IImHs are not used to calculate outgoing quality levels.
Note 8: Non·llnearity specifications are based on best straight line.
Note 9: Guaranteed by design only.
Note 10: Start conversion pulse duration greater than 3'10 clock periods will cause conversion errors.

2-11

o
CO
o
o

or-------------------------------------------------------------~

o

~
cr:

Timing Diagram
CLOCK
INPUT
+5V-n
START
CONVERSION

L-l-l---------------

ov--1

r--------

+5V,

\-----40XII/f)----./

EOC

\~----~l-----~.

w
+5V
OUTPUT
ENABLE

OV
+5v

DATA

I

J

50%

~501l

90%

/90%
-

-

-

-

-

IrRI.sTATE) -

-

-

-

~

OV
ENABLE
DElAY-

--

'\10%

1-

tOll
DISABLE
DELAY-

'1TUH/5670-2

Data is complementary binary (full scale is all "O's" output).

Application Hints
OPERATION
The. ADCOBOO contains a network with 256-3000 resistors
in series. Analog switch taps are made at the junction of
each resistor and at each end of the network. In operation,
a reference (10.00V) is applied across this network of 256
resistors. An analog input (VIN) is first compared to the center point of the ladder via the appropriate switch. If VIN is
larger than VREF/2, the internal logic changes the switch
pOints and now compares VIN and % VREF. This process,
known as successive approximation, continues until the
best match of VIN and VREFIN is made. N now defines a
specific tap on the resistor network. When the conversion is
complete, the logic loads a binary word corresponding to
this tap into the output latch and an end of conversion
(EOC) logic level appears. The output latches hold this data
. valid until a new conversion is completed and new data is
loaded into the latches. ·The data transfer occurs in about
200 ns so that valid data is present virtually all the time in
the latches. The data outputs are activated when the Output
Enable is high, and in TRI-STATE when Output Enable is
low. The Enable Delay time is approximately 200 ns. Each
conversion requires 40 clock periods. The device may be
operated in the free running mode by connecting the Start
Conversion line to the End of Conversion line. However, to
ensure start-up under all possible conditions, an external
Start Conversion pulse is required during power up conditions.
REF~RENCE

The re.ference applied across the 256 resistor network determines the analog input range. VREF = 1O.OOV with the top
of the R-network connected to 5V and the bottom connected to -5V gives a ±5V range. The reference can be level
shifted between Vss and VGG. However, the voltage, applied to the top of the R-network (pin 15), must not exceed
Vss, to prevent forward biasing the on-chip parasitiC silicon
diodes that exist between the P-diffused resistors (pin 15)
and the N-type body (pin 10, Vss). Use of a standard logic
power supply for Vss can cause problems, both due to initial
voltage tolerance and changes over temperature. A solution
is to power the Vss line (15 mA max drain) from the output
of the op amp that is used to bias the top of the

R-network (pin 15). The analog input voltage and the voltage that is applied to the bottom of the R-network (pin 5)
must be at least 7V above the -VGG supply voltage to
ensure adequate voltage drive to the analog switches.
Other reference voltages may be used (such as 10.24V). If a
5V reference is used, the analog range will be 5" and accuracy will be reduced by a factor of 2. Thus, for maximum
accuracy, it is desirable to operate with at least a 10V reference. For TTL logic levels, this requires 5V and - 5V for the
R-network. CMOS can operate at the 10 VOC Vss level and
a single 10 Voc reference can be used. All digital voltage
levels for both inputs and outputs will be from ground to
Vss·

ANALOG INPUT AND SOURCE RESISTANCE
CONSIDERATIONS
The lead to the analog input (pin 12) should be kept as short
as possible. Both noise and digital clock coupling to this
input can cause conversion errors. To minimize any input
errors, the following source resistance considerations
should be noted:
No analog input bypass capaCitor reFo~ Rs:S:5k
quired, although a 0.1 /LFinput bypass
capaCitor will prevent pickup due to unavoidable series lead inductance.
For 5k 20k
Input buffering is necessary.
If the overall converter system requires lowpass filtering of
the analog input signal, use a 20 kO or less series resistor
for a passive RC section or add an op amp RC active lowpass filter (with its inherent low output reSistance) to ensure
accurate conversions.
CLOCK COUPLING
The clock lead should be kept away from the analog input
.
line to reduce coupling.
LOGIC INPUTS
The logical "1" input voltage swing for the Clock, Start Conversion and Output Enable should be (Vss-l.0V).

:J>

Application Hints

c

o

(Continued)

C)

CMOS will satisfy this requirement but a pull-up resistor
should be used for TTL logic inputs.

CONTINUOUS CONVERSIONS AND LOGIC CONTROL
Simply tying the EOC output to the Start Conversion input
will allow continuous conversions, but an oscillation on this
line will exist during the first 4 clock periods after EOC goes
high. Adding a D flip-flop between EOC (D'input) to Start
Conversion (0 output) will prevent the oscillation and wil!
allow a stopl continuous control via the "clear'? input.

RE-8TART AND DATA VALID AFTER EOC
The EOC line (pin 9) will be in the low state for a maxirilUm
of 40 clock periods to indicate ~'busy". A START pulse that
occurs while the AID is BUSY will reset the SAR and start a
new conversion with the EOC signal remaining in the low
state until the end of this new conversion. When the conversion is complete, the EOC line will go to the high voltage
state. An additional 4 clock periods must be allowed to
elapse after EOC goes high, before a new conversion cycle
is requested. Start Conversion pulses that occur during this
last 4 clock period interval may be ignored (see Figure 1 and
2 for high speed operation). This is a problem only for high
conversion rates and keeping the number of conversions
per second less than fCLOCK/44 automatically guarantees
proper operation. For example, for an 800 kHz clock, approximately 18,000 conversions per second are allowed.
The transfer of the new digital data to the output is initiated
when EOC goes to the high voltage state.

To prevent missing a start pulse that may occur after EOC
goes high and prior to the required 4 clock period time interval, the circuit of Figure 1 can be used. The RS latch can be
set at any time and the 4-stage shift register delays the
application of the start pulse to the AID by 4 clock periods.
The RS latch is reset 1 clock period after the AID EOC
signal goes to the low voltage state. This circuit also provides a Start Conversion pulse to the AID which is 1 clock
period wide.
A second control logic application circuit is shown in Figure

2. This allows an asynchronous start pulse of arbitrary
length less than Tc, to continuously convert for a fixed high
level and provides a single clock period start pulse to the
AID. The binary counter is loaded with a count of 11 when
the start pulse to the AID appears. Counting is inhibited
until the EOC signal from the AID goes high. A carry pulse
is then generated 4 clock periods after EOC goes high and
is used to reset the input RS latch. This carry pulse can be
used to indicate that the conversion is complete, the data
has transferred to the output buffers and the system is
ready for a new conversion cycle.

POWER SUPPLIES
Standard supplies are VSS= +5V, VGG= -12V and
Voo=OV. Device accuracy is dependent on stability of the
reference voltage and has slight sensitivity to VSS-VGG.
Voo has no effect on accuracy. Noise spikes on the Vss
and VGG supplies can cause improper conversion; therefore, filtering each supply with a 4.7 ,.F tantalum capacitor is
recommended.

IL.._ _- - Ir

1IM74cnl

(FRDM~~~------I

START CONVERSION

ITOA/OI

C
CLEAR

JL A~:: .---+--t......- - - - - -......

srART

CONVERSION - - -.........

TL/H/5670-3

FIGURE 1_ Delaying an Asynchronous Start Pulse

JL

STAAT CONVEASION
STMn~-::r::»1r------1i~o-~~i-t:~~ (TOAIDI

CDNVEIIIIDN

MM74C111

....----IeAAAY

CLOCK

CfAOM:~~ -+-----1

ADcalaa
CLOCK

~:......;r__i_T_-i-'

AEADY faR
NEXT CONVEASION

GNO

Vec
I

Vee
I

aND
a

Vec
I

TLlH/5670-10

FIGURE 2. AID Control Logic
2-13

co
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gr-----------------------------------------------------------------~

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Application Hints

(Continued)

Q

ZERO AND FULL-SCALE ADJUSTMENT


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(Continued)

(')

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VREF= 10 VOC With TTL Logic Levels

,.

I&VOC

u.

5Voc

15VOC

OUTPut
ENABLE

..

UtI!;

'See application hints

-12V

TL/H/5670-13

AI and A2=LM358N dual op amp

VREF= 10 VOC With 10V CMOS Logic Levels
2.711
&.9Voc
15YD.o-"II\,."........- - - .

15Y

"
LM32IIDZ

U.
IS

.D.
ENABLE
OUTPUT

- lV oc

'See application hints

Input Level Shifting
15Y

-5V TO 5V .N'UT
TOADCDlDO

...

• Permits TIL compatible outputs with
to IOV Input range (DV to -IDV

ov

input range achieved by reversing
polarity of zener diodes and returning
the 6.8k resistor to V-).

..-1.....

"Yo-....M-~144H

,.

ADJUST FOR -5V

OUT WITH DV INPut

TL/H/5670-5

2-15

TL/H/5670-14

Typical Applications

(Continued)
zero adjust potentiometer should be set to provide a flicker
on the LSB LED readout with all the other display LEOs
OFF. .

TESTING THE AID CONVERTER
There are many degrees of complexity associated with testing an AID converter. One of the simplest tests is to apply a
known analog input voltage to the converter and use LEOs
to display the resulting digital output code as shown in Figure 3. Note that the LED drivers invert the digital output of
the AID converter to provide a binary display. A lab DVM
can be used if a precision voltage source iii not availabie.
After adjusting the zero and full-scale, any number of points
can be checked, as desired.

To adjust the full-scale adjust potentiometer, an analog input that is 1% LSB less than the reference (10.240-0.060
or 10.180 VDcl should be applied to the analog input and
, the full-scale adjusted for a flicker on the LSB LED, but this
time with all the other LEOs ON.
A,complete circuit for a simple AID tester is shown in Figure

4., Note that the clock input voltage swing and the digital
output voltage swings are from OV to 10.24V. The
MM74C901 provides a voltage translation to 5V operation
and also the logic inversion so the readout LEOs are in binary.

For ease of testing, a 10.24 Vee reference is recommended'
for the AID converter. This provides an LSB of 40 mV
(10.240/256). To adjust the zero of the AID, an analog input
voltage of % LSB or 20 mV should be applied and the
START

AID
UNDER TEST

I
I
t

'~
,OUTPUT
ENABLE
BINARY DISPLAY

y+
TLlH/5670-15

FIGURE 3. Basic AID Tester

. Ii
FULL-SCALE
ADJUST
'0.24V-n

r-

OUT EN

ov-I L.J

f· 100kHz

ADCOIDII '
UNDER TEST
ANALOG
INPUT

2 EA MM74C90'
(CMOSTOTTLl

TLlH/5670-7

FIGURE 4. Complete Basic Tester Circuit

2-16

:J>

c

Typical Applications

(Continued)
The digital output LED display can be decoded by dividing
the 8 bits into the 4 most significant bits and 4 least signifi·
cant bits. Table I shows the fractional binary equivalent of
these two 8·bit groups. By adding the decoded voltages
which are obtained from the column: "Input Voltage Value
with a 10.240 VREF" of both the MS and LS groups, the
value of the digital display can be determined. For example,
for an output LED display of "1011 0110" or "B6" (in hex)
the voltage values from the table are 7.04 + 0.24 or

7.280 Voc. These voltage values represent the center val·
ues of a perfect AID converter. The input voltage has to
change by ± % LSB (± 20 mV), the "quantization uncertain·
ty" of an AID, to obtain an output digital code change. The
effects of this quantization error have to be accounted for in
the interpretation of the test results. A plot of this natural
error source is shown in Figure 5 where, for clarity, both the
analog input voltage and the error voltage are normalized to
LSBs.

o
o

CD

o

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TABLE I. DECODING THE DIGITAL OUTPUT LEOs
INPUT VOLTAGE
VALUE WITH
10.24 VREF

FRACTIONAL BINARY VALUE FOR
HEX

BINARY
MSGROUP

F
E
0
C
B
A
9
8
7
6
5
4
3
2
1
0

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

LSGROUP
15/16

MSGROUP

LSGROUP

9.600
8.960
8.320
7.680
7.040
6.400
5.760
5.120
4.480
3.840
3.200
2.560
1.920
1.280
0.640
0

0.600
0.560
0.520
0.480
0.440
0.400
0.360
0.320
0.280
0.240
0.200
0.160
0.120
0.080
0.040
0

15/256

7/8

7/128
13/16

13/256

3/4

3/64
11/16

11/256

5/8

5/128
9/256

9/16
1/2

1/32
7/16

7/256
3/128

3/8

5/256

5/16
1/4

1/64
3/256

3/16
1/8

1/128
1/16

~

i
~~
~

1/256

1

0"

1I2r--

~--~2--~3

EI

~ I--'~--

-1/2 ' - - ..... - - -1

ANALOG INPUT VOLTAGE (IN LSBs)
TL/H/5670-8

FIGURE 5. Error Plot of a Perfect AID Showing Effects of Quantization Error

2·17

!
III(

Typical Applications

(Continued)
For operation with a microprocessor or a computer-based
test system, it is more convenient to present the errors digitally. This can be done with the circuit of Figure .7 where the
output code transitions can be detected as the 1O-bit DAC is
incremented. This provides % LSS steps for the B-bit AID
under test. If the results of this test are automatically plotted
with the analog input on the X axis and the error (in LSS's)
as the Y axis, a useful transfer function of the AID under
test results. For acceptance testing, the plot is not necessary and the testing speed can be increased by establishing
internal limits on the allowed error for each code.

A low speed ramp generator can also be used to sweep the
analog input voltage and the LED outputs will provide a binary counting sequence from zero to full-scale.
The techniques described so far are suitable for an engineering evaluation or Ii quick check on performance. For a
higher speed test system, or to obtain plotted data, a digitalto-analog converter is needed for the test set-up. An accurate 10-bit DAC can serve as the precision voltage source
for the AID. Errors of the AID under test can be provided as
either analog voltages or differences in two digital words.
A basic AID tester which uses a DAC and provides the error
as an analog output voltage is shown in Figure 6. The 2 op
amps can be eliminated if a lab DVM with a numerical subtraction feature is available to directly readout the difference
voltage, "A-C".

AIIALDDIIIPUT
VOLTAGE

-C-

...."
10DXANALDG
ERIIOR VOL fADE

TL/H/5670-16

FIGURE 6. AID Tester with Analog Error Output

DIGITAL
OUTPUT

TLlH/5670-17

FIGURE 7. Basic "Digital" AID Tester

Connection Diagram
Dual-In-Llne Package

..

NET·

1-11

WORK
TOP

Z-7

LSB
z-I

" " " " "

13

YIN
12

CLOCK

Vss

"

11

'--

~

r-

l-

I

,"

,

3

,"

•

,-I

MSB

..In·•

•

1

•

•
EOC

wo••

10nOM

Top View
Order Number ADC0800PD
or ADC0800PCD
See NS Package Number D18A

2-18

TL/H/5670-9

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Nat ion a I Semiconductor

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ADC080 11 ADC08021 ADC08031 ADC08041 ADC0805

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8-Bit J-tP Compatible AID Converters

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General Description
The ADC0801, ADC0802, ADC0803, ADC0804 and
ADC0805 are CMOS 8-bit successive approximation AID
converters that use a differential potentiometric laddersimilar to the 256R products. These converters are designed to allow operation with the NSC800 and INS8080A
derivative control bus with TRI-STATE® output latches direclly driving the data bus. These AIDs appear like memory
locations or 1/0 ports to the microprocessor and no interfacing logic is needed.
Differential analog voltage inputs allow increasing the common-mode rejection and offsetting the analog zero input
voltage value. In addition, the voltage reference input can
be adjusted to allow encoding any smaller analog voltage
span to the full 8 bits of resolution.

• Differential analog voltage inputs
• Logic inputs and outputs meet both MaS and TTL voltage level specifications
• Works with 2.5V (LM336) voltage reference
• On-Chip clock generator
• OV to 5V analog input voltage range with single 5V
supply
• No zero adjust required
• 0.3" standard width 20-pin DIP package
• 20-pin molded chip carrier or small outline package
• Operates ratiometrically or with 5 Voc, 2.5 Voc, or analog span adjusted voltage reference

Features

• Resolution
• Total error
• Conversion time

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Key Specifications

II Compatible with 8080 /LP derivatives--"no interfacing

logic needed - access time - 135 ns
• Easy interface to all microprocessors, or operates
"stand alone"

8 bits
±% LSB, ±% LSB and ±1 LSB
100 /Ls

Typical Applications

, n-

(Yo

•

"

DB'
'2 DBS
13
DB.

~~
$lPRDCESSOR

;

"
15

DB4
DB3

'S DB2
11
11
DBa

0.,

19

elK R

WR
iIIl'ii

y

2.

Vee

2
Rii
3

,ak

eLKIN 4

AID

d.!;1

...-- ~.NSDueE"
".,T RESOLUTION
OVER ANY DES'"ED
ANALOG 'NPUT
VGLTAGE RANGE
SEE SECTION 2.4.1

V,Nt ..., 6
>OIFF INPUTS

V'NI-! '
B

AGNO

'9

SPANADJ

10

ZA.'

VREFI2 ~~EE SECTION
DGNO

r;),

4"='

I

-:i"

'III

TUH/5671-1

8080 Interface

Error Specification (Includes Full-Scale,
Zero Error, and Non-Linearity)

Cf
iiII
Nseaaa,
aoBO,

m,

wn

AID

1048,
ETC.

Part
Number

FullVREF/2=2_500 VDC VREF/2 = No Connection
Scale
(No Adjustments)
(No Adjustments)
Adjusted

ADC0801

±%LSB

ADC0802

iIlTIf

l.i

.,

fI

'-- f-.

ADC0803

±%LSB
±%LSB

DATA

ADC0804
ADC0805
TL/H/5671 -31

2-19

±1 LSB
±1 LSB

In
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Absolute Maximum Ratings

~
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If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

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(Notes 1 & 2)
Package Dissipation at TA = 25·C

875mW

ESD Susceptibility (Note 10)

Supply Voltage {Vccl (Note 3)
6.5V
Voltage
Logic Control Inputs
-0.3Vto +18V.
At Other Input and Outputs
-0.3Vto (Vcc+0.3V)
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
260"C
300·C
Dual-In-Line Package (ceramic)
Surface Mount package
Vapor Phase (60 ·seconds)
Infrared (15 seconds)

-65·Cto +150·C

Storage Temperature Range

800V

Operating Ratings (Notes 1 & 2)
Temperature Range
TMIN,,;TA,,;TMAX
ADC0801 /02LJ, ADC0802LJ/883 -55·C,,;TA"; + 125·C
ADC0801/02/03/04LCJ
-40·C,,;TA"; + 85·C
-40·C,,;TA"; +85·C
ADC0801/02/03/05LCN
O"C,,;TA";+70"C
ADC0804LCN
0·C,,;TA,,;+70·C
ADC0802/03/04LCV
ADC0802/03/04LCWM
O·C,,;TA"; +70·C
RangeofVCC
4.5 VOC to 6.3 voc

215·C
220"C

Electrical Characteristics

C

The following specifications apply for Vcc=5 Voc, TMIN,,;TA,,;TMAX and fCLK=640 kHz unless otherwise specified.

CI

ADC0801: Total Adjusted Error (Note 8)

~
....

B
c
 VIN( +) the digital output code will be 0000 0000. Two on·chip diodes are tied to each analog input (see block diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater, than the Vee supply. Be careful, during testing at low Vee levels (4.5V),
as high level analog inputs (5V) can cause this input diode to conduct-especially at elevated temperatures, and cause errors for analog inputs near full-scale. The
spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output
code will be correct. To achieve an absolute 0 Voe to 5 Voe input voltage range will therefore require a minimum supply voltage of 4.950 Voc over temperature
variations, initial tolerance and loading.

Nol. 5: Accuracy is guaranteed at feLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be
extended so long as the minimum clock high time interval or minimum clock low time Interval is no less than 275 ns.
Note 8: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to 'start the conversion process. The
start request.ls internally latched, see FIgIHB 2 and section 2.0.
Nol. 7: The CS Input Is assumed to bracket the Wft strobe Input and therefore timing is dependent on the Wft pulse width. An arbitrarily wide pulse width will hold
the converier in a reset mode and the start of conversion is inHiated by the low to high transition of the Wft pulse (see timing diagrams).
Note 8: None of these AlOs requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and Figure 5.
Note I: The VREF/2 pin Is the center point of a \Wo-resistor divider connacted from Vee to ground. In all versions of the ADC0801, AOC0802, AOC0803, and
ADC080s, and In the ADC0804LCJ, each rea/Iter 18 typically 1e kO. In all versions of the AOC0804 except the AOCOe04LCJ, each resistor is typically 2.2 kO.

Note 10: Human body model, 100 pF dllCharged through a U kn relilter.
2-21

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DATA OUTPUTS AND INTR
VOUT(O)

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Typical Performance Characteristics

L~C Input Threshold

Delay From Falling Edge of
RD to Output Data Valid
vs. Load Capacitance

Voltage

v • Supply Voltage
1.8

~

.
..'"

400

>

9

~

1.&

"~

1.5

'"

II-

....E
9

>

9
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200

f!l
=

2.3

!

1.9

'"....

~

100

1.3
4.10

4.15

5.00

6.25

2.1

300

~

1.4

!

3.1

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~

1.1

!:;

3.5

500

-55°C~TA S+125°C

~

or

CLK IN Schmitt Trip Levels
vs. Supply Voltage

0

6.60

400

200

Vee -SUPPLY VOLTAGE IVoel

IDO

600

...

A-'
-we,; TA ,; +125'e

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I

i-'

VT_

I
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1.5
4.50

1000

V+

5.00

4.15

LDAD CAPACITANCE CpF)

5.60

5.25

Vec - SUPPLY VOLTAGE (Voel'

..
lUDD

I

;;

'1

a

R- l1li

i.
6
~

a:

3

:;

2

:I
z

=2 I'"

~

lao

10

5

,

1000

4U

g

2.4

or

DATA OUTPUTtBUffERS

-Isriu~e~

,

~OUT-2.4VDC

5

,...

·4
3

-&0 -25

0

2&

60

15

~

I-

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4~

l-

2~

10

12U

1l1li

0"0.01

14U

ifl

1.&
=
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:gg:::;~
D.'!2.
~ND~De/la

1.2

-.VV

~ D.'
=
~

..

TA - AMBIENTTEMPERATURE rei

Vcc~~

l-

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100 12&

~ijt

"'!-t-l.

.! 2.0 .....

f

f-V':u~K-~e

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~ f;
VCC - ••5V

-re -uV

0
-&0 -2&

cr-,I, , I
0

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1.D

101 12&

TA.~ AMBIENTTEMPERATURE rei

1-

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=
=
ffi 0.&
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Linearity Error at Low
VREF/2 Volt.ages

!!l

feLK' 640 kHz

OA

I.U

VREflZ (VDel

Power Supply Current
vs Temperature (Note 9)

Vec' 5 VDe

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Te. CONVERSION TIME "'"

Output Current vs
Temperature
I

t;

:::

vec' 5.DY

&D

12 I10

V1N(+'- VIN(-I = OV.
ASSUMES VOS' 2 mV.
THIS SHOWS THE NEED
fOR A ZERO ADlif
THE SPAN IS REDUCED.

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CLOCK CAPACITOR (.f'

1

=
ffi

/N

I
0

100

!=

Vee· 4•5V

,

H

14 ~

B

4

~

\

.Ii'

16

Te" 13J1eLK

1

=
=
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\

Effect of Unadjusted Offset Error
vs. VREF/2 Voltage

Full-Scale Error vs
Conversion Time

fCLK vs. Clock Capacitor

'1 LSI- 2IVREF/21 211
_

~~~~ ~::~~~I-

tt

I- - ~ I_S~ V~LUE (mV'
1.22
4.11
11.53
(12 BITSn~ I 1.11 II BITSI

--!-l-

~.J..

•

I~ BITS)t~

IY
/I
1.'1 I 1/ I I I
1
2
VREflZ VOLTAGE (VDel

Z.5

TL/H/5871-2

2-22

.--------------------------------------------------------------------,~

c

TRI-STATE Test Circuits and Waveforms

n
o

m
o

....

i>
c

tOH
Vcc

Vcc

n
o

Vcc --r-~="'--­

I!Ii

liII
10k

10k

DATA :::
OUTPUTS

m
o

1ili
GND

~~'H
~

OH

Vcc
DATA
OUTPUTS

GND------=

~

-10%

VOL

,,=20 ns

,,=20 ns

TLlH/5671-3

~
c

n
o

~

;;

g
o
o

m

Timing Diagrams (All timing is measured from the 50% voltage points)

~

START
CONVERSION _ _ _ _.....,

n
o

' ----Ull-- . . . ./

~
en

WIi
'WI
"BUSY"
DATA IS VALID IN
OUTPUTLATCHES

+-__+ ___--";;;NO:.;T..;;B;;;US:.;Y-"-..1

ACT:r~\~~T~:;~~ _ _ _ _ _ _ _ _ _ _
CONVERTER

_INTERNAL

ITO ax 1/IClK

ie

IlAST DATA WAS READl

IIiTII IWT DATA WAS NOT READl
---------~

INT ASSERTED
1/ZTClK

Output Enable and Reset INTR

~

iNTii RESET

~

'RI

-

I!Ii

}
NOTE

DATA
OUTPUTS

-------- -~

-

'Ace

- ----

TRI·STATE"

~----

--

I,H.'OH

.

-

Note: Read strobe must occur 8 clock periods (8l1cud after assertion of interrupt to guarantee reset of fIiI'fR.

2-23

TLlH/5671-4

•

~c

Typical Applications (Continued)
6800 Interface

i

Ratlometrlc with Full-Scale Adjust

."

tavDC)

c

,..----,

~
o

.........

GO

o

o

c

.,',

-.,.......

•• I. ••

IH2.

AID

ETC.

~
N

.

... 1-:--+-_..........'-..

~

.',

"

:

~tI.,

':"'

o

"

GO

8Q

,
I

L-....-_ _ _...I.

~
.,...

.......
......

':"'

o
GO
o

.1.. ___ _
OPTIUAL
FlAD.lUST

:.!.-

. Note: before using caps at VIN or VREF/2,
see section 2.3.2 Input Bypass Capacitors.

o
c

c
Absolute with a 2.S00V Reference

Absolute with a SV Reference

~----,

Vee 1--+--.,

VINI+) .

."

VII(·'

.

I
"

I

.,I

.

I.

T""I
':"

I

AID

'.1

.

I
VIII-!

I
I

I
I

I

I
'1
':"
II.. ____ JI
I

VREFI2I-----+..;;;;;.;:;'

VUIII-)

I

I
I

I

VREFIZ

amONAl

PS"lIun

'For low power, see also LM385·2.5

Zero-Shift and Span Adjust: 2V:S:: VIN:S:: SV

Span Adjust: OV:S:: VIN:S:: 3V

·oo

IIVoC)

.,.

.,,1--+--------.,

r-----------jV
Nf.}

+

VIN

..

~'D~f
AID
B,n.

r-""'"","++2.500 vae

I·BITDAC

VREFIZI--.-+--<

Ik
SIAN

LM338

ADJ

0::; VOAC

< 2.5V

Digitizing a Current Flow
(5V~~~ o-""1.......V'V·I\oo-...._ _ _ _..;~:;;...:ll::;DA:::D~_..:12:;;A.:;'U:.:l::.l.S:::';;:Al::EI:__ _ __ _ _ _ _....,
'00

Vee

V'NI-I

1-----""------,

r

+

Z4Gt

AID

tD

.,

J.n

'00

ZERO ~.I----_tV,N(+1

AOJ

1Z1I.

TL/H/5671-6

2-25

CD

0

19k

mV

0

W
.......

AID

VREF/2~128

»
c

0

Typical Applications (Continued)
Self-Clocking Multiple AIDs

sv

CLKA

External Clocking

'.'VMI.'
:.~tI kffL·-ri~~~-j--U----UVMAXG

.C~ CLltlli

_

,

AJrJ#1

CLkIN

.-

~---------~

,..-

AIIl

fCU

CLK'N

-

leo---

-~"'F

II---

elK IN

AID

elk.

I

tOO kHz:>ICLK:>t460 kHz
AIIl ..

~ CUI:,.

Use a large R value
to reduce loading
at elK R output.

I

+

If MORE THAN I ADDITIONAL
AIfJ.. USE ACMOS.UFFU fiaT TIU

Self-Clocklngln Free-Running Mode

p.P Interface for Free-Running AID

,..
CliCl1

RESET
l.fTAGE

AIIl
AID

elK iii . -....._

.

. .I>CLI

,
~________________,-~I~n'H'

BlC:rc

R

V07-

ClKIN

;/;1&1,'
READY

'='

•Aller power-up. a momentary grounding
01 the 'm! input is needed to guarantee operation.

-I
·VOl

ITO,"

j--fh1ffcLlcl

~'REYENTSRD
t DURINIAID
DATA UPDATE
REStT

T'=-::;-----i

(71. '''elK'

RElET

Operating with "Automotive" Ratlometrlc Transducers
Vee

liVae)

Ratlometric with VREF/2 Forced

Vee
IIVoc)

Vee

Vee 1-__....________•

,..
VOI,l:Itnri:::+-<

...........

~~

,..

..
...
..

ADJ

VO"I:II---+<

,..

·V'N(-)=0.15 Vee
15% 01 Vee:>VXDR:>S5% 01 VCC
TUH/5671-7

2·28

l>
C

Typical Applications (Continued)

(")

g

o
.....
......

,.,.p Compatible Differential-Input Comparator with Pre-Set Vas (with or without Hysteresis)

r----------------------

l>

C

(")

o
CO
o
N
.......

MS'
(01"1

u.

l>
C

(")

o
CO
oCo)
.......

""'.

l>
C

I.-"""/Z""c"'D4"'01",.+--O-l)..+tl +( ~,-IDRVos)

.... ___________________ -J

(")

o
CO
o

":::'

'See Figure 5 to select R value

~

......

087="1" for VIN(+»VIN(-)+(VREF/2)

l>

Omit circuitry within the dotted area If
hysteresis is not needed

(")

C

o

CO

o

Handling ± 10V Analog Inputs
t11V

, ...

Low-Cost, ,.,.p Interlaced, Temperature-to-Dlgltal Converter

r---------t--o~c~acl
'

..

UI

Vee

IIVDe)

•
Till"
....

Vee

VINI+.

Ll3:lS

.

,+'IIoIF

....
Ala
IVDC

TArm!

'Beckman Instruments #694-3·Rl0K resistor array

VrNl-1

'Ok

TAMO

VAEfn

AIIJ

....

EI
,.,.p Interfaced Temperature-to-Dlgltal Converter
. Vee

IIVDe)

..
r-....'IIII~.....- ....-tV..I.1

v"I--..---------.."
•

.

'bF
X
....

"jUV

TaM'1

AIIJ

'Circuit values shown are for O'C,;;TA';; + 121l"C
"Can calibrate each sensor to allow easy replacement. then
AID can be calibrated with a pre-881lnput voltage.

Vlol-I

-+<

VIEfIl .........

111

LM331

'A MAX
AIIJ

u.TUH/5671-8

2-27

Typical Applications (Continued)
Handling ± SV Analog Inputs

Read·Only Interface
~

••us

1=9=---_+019

DATA

,... ..-------,
AID

+
~1a1J.F

n,~
iilI~

r--

DATAIS/~ "STARTS lEW
OUTPUT
COIIVERSION

TL/H/5671-33

TUH/567'-34

'Beckman Instruments #694-3-R10K resistor array

,...p Interfaced Comparator with Hysteresis

Protecting the Input
Vee
(5 V,.)

v,.'+1

1111(01'11---..,
Oil

OUTPUT

AID

Y,.

-15 YDC

VIIII-I

AID

YREFIZ

'="
Diodes are 1N914

+VHfF

CI

eLK

RD

TL/H/5671-9

A Low·Cost, 3·Decade Logarithmic Converter

AFI

TL/H/5671-35

Analog Self·Test for a System
A/O

•

CHOIEL
ANALOG
MUK

AID

e_,

C CHAJIINEl
SELECJ

~~=::-~

,TLlH/56~1-36

'LM389 transistors
A,

2-28

e, C, 0 = LM324A quad op amp

Typical Applications

~

g

(Continued)

m
o

.....
......

3-Decade Logarithmic AID Converter
A. B. C. 0

~

= LM324A

(')

om
o

'ao

N
.....
>
C

n
o

AID

m

oCo)

.....
>
c

,ao

>-1-~P-'WIr---IVINI-t

n
o

'"
1.1

lifT....

Uk

m

o

.a:o.
.....
>
c

43.11:

n

"k
1%

-IV U
FS
AOJ

om
o

U1

Noise Filtering the Analog Input

Multiplexing Differential Inputs

•

CHANNEL

DIFFERENTIAL
MUX
CD4ClSZ

lID

AID

fO=2O Hz

Uses Chebyshev implementation for steeper roll-oll

B CHANNEL
c.._~_..::. SELECT

unity-gain, 2nd order, low-pass filter

Adding a seperate filter for each channel Increases
system response time if an analog multiplexer
is used

Output Buffers with AID Data Enabled

Increasing Bus Drive andlor Reducing Time on Bus

TO".

AiD

DATA IUS

DATA*
AID

II

FROM OUTPUT
'ORTORp'

TRI-STATE<'

Wli_+----oJWli

BUfFERS

g~--------------------------~

TO",.
DATA8US

UAlADUT
AID

TRI.sTATE(2I
IUffERS

n~---------------------------J

TL/H/5671-1D

'Allows output data to set-up at falling edge of rni

'AID output data II updated 1 ClK pttIOd
prior to _rtlon of 1IiITFI

2-29

Typical Applications (Continued)
Sampling an AC Input Signal

...

'IN MAX

.....LE

•••

HOLD

Lf311

fl.
LDW.pW, MULn.pOLE

C.'TRDl

FILTER

-ITcl_I !fl. 1_
.Jl...S"

1"

AI.
Ch

.......,...._ _ _ _ _ _..J

~--

Note 1: Oversample whenever possible [keep fs > 2f( -60)1 to eliminate input frequency folding
(aliasing) and to allow for the skirt response of the filter. '
Note 2: Consider the

ampl~ude

errors which are introduced within the passband of the filter.

70% Power Savings by Clock Gating

~-----=r")o---ct>---""-----~CLKIN

AID'

1/314CM,·

TO AID

(Complete shutdown takes

Z

30 seconds.)

Power Savings by AID and VREF Shutdown
r-------"""1~----1------o~CSDC)

Vee

1--.,.--+

."
"PCONTROl C - - - - L
8US

CMOS
BUFFER

AI.'

TO DATA
8US

VR"" 1----+

TUH/5671-11

'Use ADC0801, 02, '03 or 05 for lowest power consumption.
Note: Logic inputs can be driven to Vee ~h AID supply at zero volts.
Buffer prevents date bus from overdrivlng output of AID when In shutdown mode.

2-30,

~------------------------------------------------~~

C

Functional Description

other words, if we apply an analog input equal to the centervalue ± % LSB, we guarantee that the AID will produce the
correct digital code. The maximum range of the position of
the code transition is indicated by the horizontal arrow and it
is guaranteed to be no more than % LSB.
The error curve of Figure lc shows a worst case error plot
for the ADCOB02. Here we guarantee that if we apply an
analog input equal to the LSB analog voltage center-value
the AID will produce the correct digital code.
Next to each transfer function is shown the corresponding
error plot. Many people may be more familiar with error plots
than transfer functions. The analog input voltage to the AID
is provided by either a linear ramp or by the discrete output
steps of a high resolution DAC. Notice that the error is continuously displayed and includes the quantization uncertainty of the AID. For example the error at pOint 1 of Figure 1a
is + % LSB because the digital code appeared % LSB in
advance of the center-value of the tread. The error plots
always have a constant negative slope and the abrupt upside steps are always 1 LSB in magnitude.

1.0 UNDERSTANDING AID ERROR SPECS
A perfect AID transfer characteristic (staircase waveform) is
shown in Figure la. The horizontal scale is analog input
voltage and the particular pOints labeled are in steps of 1
LSB (19.53 mV with 2.5V tied to the VREF/2 pin). The digital
output codes that correspond to these inputs are shown as
D-l, D, and D+ 1. For the perfect AID, not only will center·
value (A -I, A, A + 1, . . . . ) analog inputs produce the correct output ditigal codes, but also each riser (the transitions
between adjacent output codes) will be located ± % LSB
away from each center-value. As shown, the risers are ideal
and have no width. Correct digital output codes will be provided for a range of analog input voltages that extend ± %
LSB from the ideal center-values. Each tread (the range of
analog input voltage that provides the same digital output
code) is therefore 1 LSB wide.

Figure lb shows a worst case error plot for the ADC0801.
All center-valued inputs are guaranteed to produce the correct output codes and the adjacent risers are guaranteed to
be no closer to tt. .. center-value points than ± % LSB. In

Error Plot

Transfer Function

oo

CD

o......

i;
C

o
o

CD

o

N

......
~

C

oo

CD

o

~

~

C

oo

CD

o

.a:o.
.....
~

C

oo

CD

o

+' LSB 1 - - - - - - - - -

C7I

~

""u

5

.

;

0+1

iTS
1
1

~
s 0-'

i""14

,:
i
1

A-'

1
1

1
1
1

,I
-, lSB ' - - - ' - -........-

A+'

A-1

ANALOG INPUT IVIN)

A

.......- _
A+l

ANALOG INPUT (VIN)

a) Accuracy = ± 0 LSB: A Perfect AID
Transfer Function

Error Plot

.
I

---1

+1/2 LSI

8

i

'"" 0+'

I--f-\-t'lrt-+-t: 4

~

~

~--+,
1 6

-,IZ LSB

c 0-,

-314LSB

---t--2

fII

louANT.

•• OJ-ERROR

--

~--i----

-, LSB

A-'
A
A+l
ANALOG INPUT IYIN)

A-I

A+I

. . ALOG 'NPUT (v,.1

b) Accuracy =

±% LSB

Transfer Function

Error Plot

+' LSB 1-------.---

-, LSB

A-I
AllALOa

A

A.,

L-_--'_-"'---'-_ _
A-1

".,11' (V,lli

.A

A+l

ANALOG 'NPUT (V'NI

c) Accuracy = ±%LSB
FIGURE 1. Clarifying the Error Specs of an AID Converter

2-31

TLlH/5671-12

Functional Description (Continued)

A functional diagram of the AID converter is shown in Figure 2. All of the package pinouts are shown and the major
logic control paths are drawn in heavier weight lines.

2.0 FUNCTIONAL DESCRIPTION
The ADCOB01 series contains a circuit equivalent of the
256R network. Analog switches are sequenced by successive approximation logic to match the analog difference input voltage [VIN( +) - VIN( -)] to a corresponding tap on
the R network. The most significant bit is tested first and
after B comparisons (64 clock cycles) a digital B-bit binary
code (1111 1111 = full-scale) is transferred to an output
latch and then an interrupt is asserted (lNTR makes a highto-low transition). A conversion in process can be interrupted by issu,ing a second start command. The device may be
operated in the free-running mode by connecting INTR to
the WR input with CS= O. To ensure start-up under all'possible conditions, an external WR pulse is required during the
'
first power-up cycle.

The converter is started by having CS and WR simulta'
neously low. This sets the start flip-flop (F/F) and the resulting "1" level resets the B-bit shift register, resets the Interrupt'{INTR) F/F and inputs a "1" to the D flop, F/F1, which
is at the input end of the B-bit shift register. Internal clock
signals then transfer this "1" to the Q output of FIF1. The
AND gate, G1, combines this "1" output with a clock signal
to provide a reset signal to the start F/F. If the set signal is
no longer present (either WR or CS is a "1") the start F/F is
reset and the B-bit shift register then can have the "1"
clocked in, which starts the conversion process. If the set
signal were to still be present, this reset pulse would have
no effect (both outputs of the start F IF would momentarily
be at a "1" level) and the B-bit shift register would continue
to be held in the reset mode. This logic therefore allows for
wide CS and WR signals and the converter will start after at
least one of these signals returns high and the internal
clocks again provide a reset Signal for the start F/F,

On the high-to-Iow transition of the WR input the internal
SAR latches and the shift register stages are reset. As long
as the CS input and WR input remain low, the AID will remain in a reset state. Conversion will start from 1 to 8 clock
periods after at least one of these inputs makes a low-tohigh transition.

"1:"· RESET SHIFT REGISTER
"0"· BUSY AND QUIESCENT STATE

INPUT PROTECTION
FOR ALL LOGIC INPUTS

F
INPUT

CLI

TOINTERNAL
CIRCUITS

BV"'3DV

2B
VCC IVREFI'OO---+----i

VREFl2ci9_-~~---+I

SAR

LADDER

OE~:~ER I+++i-H~---I

LATCH
INOTE 21

INTR F/F
OAC
VIOUTI
AGND

'::'

Vee

1

V,.I-Io-+-+-....
- I I - I " ,nCLII

+-

" DIGITAL OUTPUTS

--u-

fmIV. i!lIMPL.

~'.'/fCLK

"0!::::::-:-:-:-:-:f_-_")-_______"~'"_.;,;OU;.::1P~U~TE;;;N;;;:AB;;;L=4E~--------;;~
TRI.sTATEt!) CONTROL

nINOTE
n

o

-'

RESlT

TLlH/5671-,3

Note t: ClS shown twice for clarity.
Note 2: SAR = Successive Approximation Register.

FIGURE 2. Block DIagram

2·32

l>

Functional Description

(Continued)

After the "1" is clocked through the 8-bit shift register
(which completes the SAR search) it appears as the input to
the D-type latch, LATCH 1. As soon as this "1" is output
from the shift register, the AND gate, G2, causes the new
digital word to transfer to the TRI-STATE output latches.
When LATCH 1 is subsequently enabled, the Q output
makes a high-to-Iow transition which causes the INTR F/F
to set. An inverting buffer then supplies the INTR input signal.

slight time difference between the input voltage samples is
given by:

~

where:
aVe is the error voltage due to sampling delay

o

.....
~

Vp is the peak value of the common-mode voltage
fern is the common-mode frequency
As an example, to keep this error to % LSB ( - 5 mY) when
operating with a 60 Hz common-mode frequency, fern, and
using a 640 kHz AID clock, fCLK, would allow a peak value
of the common-mode voltage, Vp, which is given by:
Vp = [aVe(MAX) (fCLK)]
(27Tfern ) (4.5)

l>

c

o
o

CD

o

.....
Co)

l>

c

o
o

CD

o

or

.....
~

V _ (5 X 1Q-3)(640X 103)
p(6.28) (60) (4.5)

l>
C

g

which gives

When operating in the free-running or continuous conversion mode (lNTR pin tied to WR and CS wired low-see
also section 2.8), the START F/F is SET by the high-to-Iow
transition of the INTR signal. This resets the SHIFT REGISTER which causes the input to the D-type latch, LATCH 1,
to go low. As the latch enable input is still present, the Q
output will go high, which then allows the INTR F/F to be
RESET. This reduces the width of the resulting INTR output
pulse to only a few propagation delays (approximately 300
ns).
When data is to be read, the combination of both CS and
RD being low will cause the INTR F/F to be reset and the
TRI-STATE output latches will be enabled to provide the 8bit digital outputs.

CD

o
....

i>
c

4.5 )
aVe(MAX) = (Vp)(27Tfcrn) ( fCLK '

Note that this SET control of the INTR F/F remains low for
8 of the external clock periods (as the internal clocks run at
Va of the frequency of the external clock). If the data output
is continuously enabled (CS and RD both held low), the
INTR output will still signal the end of conversion (by a highto-low transition), because the SET input can control the Q
output of the INTR F/F even though the RESET input is
constantly at a "1" level in this operating mode. This INTR
output will therefore stay low for the duration of the SET
signal, which is 8 periods of the external clock frequency
(assuming the AID is not started during this interval).

c
oo

Vp"'1.9V.
The allowed range of analog input voltages usually places
more severe restrictions on input common-mode noise levels.
An analog input voltage with a reduced span and a relatively
large zero offset can be handled easily by making use of the
differential input (see section 2.4 Reference Voltage).

CD

o

CIt

2.3 Analog Inputs
2.3.1 Input Current
Normal Mode
Due to the internal switching action, displacement currents
will flow at the analog inputs. This is due to on-chip stray
capacitance to ground as shown in Figure 3.

2.1 Digital Control Inputs
The digital control inputs ((;S, RD, and WR) meet standard
T2L logic voltage levels. These signals have been renamed
when compared to the standard AID Start and Output Enable labels. In addition, these inputs are active low to allow
an easy interface to microprocessor control busses. For
non-microprocessor based applications, the CS input (pin 1)
can be grounded and the standard AID Start function is
obtained by an active low pulse applied at the WR input (pin
3) and the Output Enable function is caused by an active
low pulse at the RD input (pin 2).

r----------------,

I
I
I
I

I
I
I
RS

ICHARGE I
-6

I
YA
PEAK",ON +RS

~t

:i1

~
~

-

TIME

'ON

YIN'+I

2.2 Analog Differential Voltage Inputs and
Common-Mode Rejection

IDiSCHARGE

I
I

SWI
CSTRAY

-7

This AID has additional applications flexibility due to the
analog differential voltage input. The VIN( -) input (pin 7)
can be used to automatically subtract a fixed voltage value
from the input reading (tare correction). This is also useful in
4 mA-20 mA current loop conversion. In addition, commonmode noise can be reduced by use of the differential input.
The time interval between sampling VIN( +) and VIN( -) is 41f2 clock periods. The maximum error voltage due to this

TUZPFI

TLlH/5671-14

rONofSW1 andSW2 '" 5kU
r=roN eSTRAY" 5 kU x 12 pF = 60 ns

FIGURE 3. Analog Input Impedance

2-33

•

~ r---------------------------------------------------------------------------------~
C)

co

C)

o
c

cc
......
0:1'
~

C)

g
~

C')
C)

co
C)

o

c

cc
......
C'I

C)

co

C)

o

c
cc
......

....

C)

co

C)

o
c

cc

Functional Description (Continued)
The voltage on this capacitance is switched and will result in
currents entering the VIN( +) input pin and leaving the
VIN( -) input which will depend on the analog differential
input voltage levels. These current transients occur at the
leading edge of the internal clocks. They rapidly decay and
do not cause errors as the on-chip comparator is strobed at
the end of the clock period.

resistance and the use of an input bypass capacitor. This
error can be eliminated by doing a full·scale adjustment of
the AID (adjust VREF/2 for a proper full-scale reading-see
section 2.5.2 on Full-Scale Adjustment) with the source resistance and input bypass capacitor in place.
2.4 Reference Voltage
2.4.1 Span Adjust
For maximum applications flexibility, these AIDs have been
designed to accommodate a 5 Voe, 2.5 Voe or,an adjusted
voltage reference; This has been achieved in the design of
the IC as shown in Figure 4.

Fault Mode
If the voltage source applied to the VIN(+) or VIN(-) pin
exceeds the allowed operating range of Vee + 50 mV,large
input currents can flow through a parasitic diode to the Vee
pin; If these currents can exceed the 1 mA max allowed
spec, an external diode (1 N914) should be added to bypass
this current to the Vee pin (with the current bypassed with
this diode, the voltage at the VIN( +) pin can exceed the
Vee voltage by the forward voltage of this diode).

20

2.3.2 Input Bypass Capacitors
Bypass capacitors at the inputs will average these charges
and cause a DC current to flow through the output resistances of the analog Signal sources. This charge pumping
action is worse for continuous conversions with the VIN( + )
input Voltage at full-scale. For continuous conversions with
a 640 kHz clock frequency with the VIN( +) input at 5V, this
DC current is at a maximum of approximately 5 pA Therefore, bypass capacitors ,should not be used at the analog
inputs or the VREP2 pin for ~igh resistance sources (> 1
kO). If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to minimize capacitor size, the detrimental effects of the voltage drop
across this input resistance, which is due to the average
value of the input current, can be eliminated with a full-scale
adjustment while the given source resistor and input bypass
capacitor are both in place. This is possible because the
average value of the input current is a precise linear funclion of the differential input voltage.

R
VREFIZ

9

R

~ -1

: DECODE

1

ANALOG
CIRCUITS

DIGITAL
CIRCUITS

_I

I

~}AGND I

~

2.3.3 Input Source Resistance

DGNO 10

117

TL/H/5671-15

Large values of source resistance where an input bypass
capacitor is not used, will not cause errors as the input currents settle out prior to the comparison time. If a low pass
filter is required in the system, use a low valued series resis·
tor (';;; 1 kO) for a passive RC section or add an op amp RC
active low pass filter. For low source resistance applications, (';;; 1 kO), a 0.1 JLF bypass capacitor at the inputs will
prevent noise pickup due to series lead inductance of a long
wire. A 100.0. series resistor can be used to isolate this capacitor-both the Rand C are placed outside the feedback
loop-from the output of an op amp, if used.

FIGURE 4. The VREFERENCE Design on the IC
Notice that the reference voltage for the IC is either '112 of
the voltage applied to the Vee supply pin, or is equal to the
voltage that is externally forced at the VREF/2 pin. This allows for a ratiometric voltage reference using the Vee supply, a 5 Voe reference voltage can be used for the Vee
suppiy or a voltage less than 2.5 Voe can be applied to the
VREF/2 input for increased application flexibility. The internal gain to the VREF/2 input is 2, making the full-scale differential input voltage twice the voltage at pin 9.
An example of the use of an adjusted reference voltage is to
accommodate a reduced span-<>r dynamic voltage range
of the analog input voltage. If the analog input voltage were
to range from 0.5 Voe to 3.5 Voe, instead of OV to 5 Voe,
the span would be 3V as shown in Figure 5. With 0.5 Voe
applied to the VIN(-) pin to absorb the offset, the reference
voltage can be made equal to 112 of the 3V span or 1.5 Voe.
The AID now will encode the VIN( +) Signal from 0.5V to 3.5
V with the 0.5V input corresponding to zero and the 3.5 Voe
input corresponding to full-scale. The full 8 bits of resolution
are therefore applied over this reduced analog input voltage
range.

2.3.4 Noise
The leads to the analog inputs (pin 6 and 7) should be kept
, as short as possible to minimize input noise coupling. Both
noise and undesired digital clock coupling to these inputs
can cause system errors. The source resistance for these
inputs should, in general, be kept below 5 k.o.. Larger values
of source resistance can cause undesired system noise
pickup. Input bypass capacitors, placed from the analog inputs to ground, will eliminate system noise pickup but can
create analog scale errors as these capacitors will average
the transient input switching currents of the AID (see section 2.3.1.). This scale error depends on both a large source

2-34

Functional Description

»
c
oo

(Continued)

Q)

o......

......

»
c
oo

Q)

o

'Add if VREF/2 s: 1 VOC with LM358
to draw 3 rnA to ground.

I\)
......
»
c

oo

Q)

o

-f

1;
>

SV
4

4

VIN!+) MAX
!3.SVJ

Co)
......
»
c

I

oo

3

2
1

vI7tJV~IN

Q)

SPAN =3V

o

I

......
""
c»

O~=====

oo

Q)

TLlH/5671-16

a) Analog Input Signal Example

FIGURE 5. Adapting the

b) Accommodating an Analog Input from
O.5V (Digital Out = = OOHEX) to 3.5V
(Digital Out= FFHEX)

AID Analog Input Voltages to Match an Arbitrary Input Signal Range

2.4.2 Reference Accuracy Requirements
The converter can be operated in a ratiometric mode or an
absolute mode. In ratio metric converter applications, the
magnitude of the reference voltage is a factor in both the
output of the source transducer and the output of the AID
converter and therefore cancels out in the final digital output
code. The ADCOB05 is specified particularly for use in ratio·
metric applications with no adjustments required. In abso·
lute conversion applications, both the initial value and the
temperature stability of the reference voltage are important
factors in the accuracy of the AID converter. For VREF/2
voltages of 2A Voe nominal value, initial errors of ± 10
mVoe will cause conversion errors of ± 1 LSB due to the
gain of 2 of the VREF/2 input. In reduced span applications,
the initial value and the stability of the VREF/2 input voltage
become even more important. For example, if the span is
reduced to 2.5V, the analog input LSB voltage value is cor·
respondingly reduced frorn 20 mV (5V span) to 10 mV and
1 LSB at the VREF/2 input becomes 5 mY. As can be seen,
this reduces the allowed initial tolerance of the reference
voltage and requires correspondingly less absolute change
with temperature variations. Note that spans smaller than
2.5V place even tighter requirements on the initial accuracy
and stability of the reference source.
In general, the magnitude of the reference voltage will reo
quire an initial adjustment. Errors due to an improper value
of reference voltage appear as full·scale errors in the AID
transfer function. IC voltage regulators may be used for ref·
erences if the ambient temperature changes are not exces·
sive. The LM336B 2.5V IC reference diode (from National
Semiconductor) has a temperature stability of 1.B mV typ
(6 mV max) over 0·C,;;TA';;+70·C. Other temperature
range parts are also available.

2.5 Errors and Reference Voltage Adjustments
2.5.1 Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not ground,
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing the AID VIN(-) input at this VIN(MIN) value (see
Applications section). This utilizes the differential mode op·
eration of the AID.
The zero error of the AID converter relates to the location
of the first riser of the transfer function and can be mea·
sured by grounding the VIN (-) input and applying a small
magnitude positive voltage to the VIN (+) input. Zero error
is the difference between the actual DC input voltage that is
necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal % LSB value
(% LSB = 9.B mV for VREF/2=2.500 Vocl.
2.5.2 Full·Scale
The full·scale adjustment can be made by applying a differ·
ential input voltage that is 1% LSB less than the desired
analog full·scale voltage range and then adjusting the mag·
nitude of the VREF/2 input (pin 9 or the Vee supply if pin 9 is
not used) for a digital output code that is just changing from
11111110 to 11111111.

2·35

o

U1

Functional Description

(Continued)
conversion in process is not allowed to be completed, therefore the data of the previous conversion remains in this
latch. The INTR output simply remains at the "1" level.

2.5.3 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal that does not go to ground) this new zero reference
should be properly adjusted first. A VIN( +) voltage that
equals this desired zero reference plus % LSB (where the
LSB is calculated for the desired analog span, 1 LSB = analog span/256) is applied to pin 6 and the zero reference
voltage at pin 7 should then be adjusted to just obtain the
OOHEX to 01 HEX code transition.
The full-scale adjustment should then be made (with the
proper VIN( -) voltage applied) by forcing a voltage to the
VIN( +) input which is given by:

2.8 Continuous Conversions
For operation in the free-running mode an initializing pulse
should be used, following power-up, to ensure circuit operation. In this application, the CS input is grounded and the
WR input is tied to the INTR output. This WR and INTR
node should be momentarily forced to logic low following a
power-up cycle to guarantee operation.
2.9 Driving the Data Bus
This MaS AID, like MaS microprocessors and memories,
will require a bus driver when the total capaCitance of the
data bus gets large. Other circuitry, which is tied to the data
bus, will add to the total capacitive loading, even in TRISTATE (high impedance mode): Backplane bussing also
greatly adds to the stray capacitance of the data bus.
There are some alternatives available to the designer to
handle this problem. Basically, the capacitive loading of the
data bus slows down the response time, even though DC
specifications are still met. For systems operating with a
relatively slow CPU clock frequency, more time is available
in which to establish proper logic levels on the bus and
therefore higher capacitive loads can be driven (see typical
characteristics curves).

(VMAX - VMIN)]
VIN (+) fsadj = VMAX-1.5 [
256
'
where:
VMAX=The high end of the analog input range
and
VMIN=the low end (the offset zero) of the analog range.
(Both are ground referenced.)
The VREF/2 (or Vecl voltage is then adjusted to provide a
code change from FEHEX to FFHEX. This completes the adjustment procedure.
2.6 Clocking Option
The clock for the AID can be derived from the CPU clock or
an external RC 'Can be added to provide self-clocking. The
CLK IN (pin 4) makes use of a Schmitt trigger as shown in
Figure 6.

CLKR

At higher CPU clock frequencies time can be extended for
110 reads (and/or writes) by inserting wait states (8080) or
using clock extending circuits (6800).
Finally, if time is short and capacitive loading is high, external bus drivers must be used. These can be TRI-STATE
buffers (low power Schottky such as the DM74LS240 series
is recommended) or special higher drive current products
which are designed as bus drivers. High current bipolar bus
drivers with PNP inputs are recommended.

v

I'

1
feLKe---I~ ><>-t.... CLK

R""10ko'

AID

TUH/5671-17

2.7 Restart During a Conversion
If the AID is restarted (CS and WR go low and return high)
during a conversion, the converter is reset and a new conversion is started. The output data latch is not updated if the

2-36

)0

c

Functional Description (Continued)
A single pOint analog ground that is separate from the logic
ground points should be used. The power supply bypass
capacitor and the self-clocking capacitor (if used) should
both be returned to digital ground. Any VREF/2 bypass capacitors, analog input filter capacitors, or input signal shielding should be returned to the analog ground point. A test for
proper grounding is to measure the zero error of the AID
converter. Zero errors in excess of % LSB can usually be
traced to improper board layout and wiring (see section
2.5.1 for measuring the zero error).

VREF/2 = 2.560V) can be determined. For example, for an
output LED display of 1011 0110 or B6 (in hex), the voltage
values from the table are 3.520 + 0.120 or 3.640 Voe.
These voltage values represent the center-values of a perfect AID converter. The effects of quantization error have to
be accounted for in the interpretation of the test results.
For a higher speed test system, or to obtain plotted data, a
digital-to·analog converter is needed for the test set-up. An
accurate 10-bit DAC can serve as the precision voltage
source for the AID. Errors of the AID under test can be
expressed as either analog voltages or differences in 2 digital words.
A basic AID tester that uses a DAC and provides the error
as an analog output voltage is shown in Figure 8. The 2 op
amps can be eliminated if a lab DVM with a numerical subtraction feature is available to read the difference voltage,
"A-C", directly. The analog input voltage can be supplied
by a low frequency ramp generator and an X-V plotter can
be used to provide analog error (y axis) versus analog input
(X axis).

3.0 TESTING THE AID CONVERTER
There are many degrees of complexity associated with testing an AID conve~er. One of the simplest tests is to apply a
known analog input voltage to the converter and use LEDs
to display the resulting digital output code as shown in Figure 7.
For ease of testing, the VREF/2 (pin 9) should be supplied
with 2.560 Voe and a Vee supply voltage of 5.12 Voe
should be used. This provides an LSB value of 20 mV.
If a full-scale adjustment is to be made, an analog input
voltage of 5.090 Voe (5.120-1 % LSB) should be applied to
the VIN(+) pin with the VIN(-) pin grounded. The value of
the VREF/2 input voltage should then be adjusted until the
digital output code is just changing from 1111 1110 to 1111
1111. This value of VREF/2 should then be used for all the
tests.
The digital output LED display can be decoded by dividing
the 8 bits into 2 hex characters, the 4 most significant (MS)
and the 4 least significant (LS). Table I shows the fractional
binary equivalent of these two 4-bit groups. By adding the
voltages obtained from the "VMS" and "VLS" columns in
Table I, the nominal value of the digital display (when

For operation with a microprocessor or a computer-based
test system, it is more convenient to present the errors digitally. This can be done with the circuit of Figure 9, where the
output code transitions can be detected as the 10-bit DAC is
incremented. This provides % LSB steps for the 8·bit AID
under test. If the results of this test are automatically plotted
with the analog input on the X axis and the error (in LSB's)
as the Y axis, a useful transfer function of the AID under
test results. For acceptance testing, the plot is not necessary and the testing speed can be increased by establishing
internal limits on the allowed error for each code.
4.0 MICROPROCESSOR INTERFACING
To dicuss the interface with 8080A and 6800 microprocessors, a common sample subroutine structure is used. The
microprocessor starts the AID, reads and stores the results
of 16 successive conversions, then returns to the user's
program. The 16 data bytes are stored in 16 successive
memory locations. All Data and Addresses will be given in
hexadecimal form. Software and hardware details are provided separately for each type of microprocessor.

1Il10

or-c:r-'~_t-05.120VDC

1S0 PF,,};

18

4.1 InterfaCing 8080 Microprocessor Derivatives (8048,
8085)

N.D.
17

STAi

This converter has been designed to directly interface with
derivatives of the 8080 microprocessor. The AID can be
mapped into memory space (using standard memory address decoding for CS and the MEMR and MEMW strobes)
or it can be controlled as an I/O device by using the I/O R
and I/O W strobes and decoding the address bits AO ~
A7 (or address bits A8 ~ A15 as they will contain the
same 8-bit address information) to obtain the CS input. Using the I/O space provides 256 additional addresses and
may allow a simpler 8-bit address decoder but the data can
only be input to the accumulator. To make use of the additional memory reference instructions, the AID should be
mapped into memory space. An example of an AID in I/O
sp!ice is shown in Figure 10.

IS

AID
IS

VINI>I

5Voc

0.1""

14

13

12

2.58GVOC
VREFI2

.a.l"f

l

10
OGNO

"

1.3k
181
TL/H/5671-1 B

FIGURE 7. Basic AID Tester

2-37

n
o

QC)

o
.....
......
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c

n
o

QC)

o

N

;;;
C

n
o

QC)

o

~
)0

c

n
o

QC)

o

~
......

)0

C

o
o

QC)

o

C1I

II)
<:)

co
<:)

o

Functional Description

(Continued)

C


e

Functional Description (Continued)

0
0

0
CD
0

...

~ INT(l4)

T7iIWiI (27)"

......

I7l!lfII (25)"

e

:I>
0

10k

I

0
CD
0

~5V

\...J

cs

Vee
19
elK R
DBo II

."i<: iiDWi\

~

OBI (18)'

VIN(+)

OBI
DB2 16
DB3 15

VIN(-)

DB4 14

DB4(5)"

DB5 13

DB5(11)'

DB6 12
11
DB7

DB812o)'

--feiNT

ANALOG
INPUTS

7

AID

~.r-tAGND

T ':' 0;;-

d?

VREFI2
DGND

T2

W
......

:I>

e

0

0
CD
0

DB7(7)"

.a:o.
......

:I>

e

0

0
CD
0

T

I

OUT

Vec

T5
_T4
DM8\31
8US

-TJ

0
CD
0

DB2(1I)'
DB3(9)'

Y

I

r--

D8o(l3)*

11

ClKIN

i\)
......

:I>
e
0

$10"

COMPARATOR

~TI

~TD

B5

ADI5 (36)

B4

ADI4 (39)
AD\3 (31)

B3
B2
BI

AD12137)
ADII (40)
ADIO (I)

Bo

1

U1

1

d?

TL/H/5671-20

Nole 1: 'Pin numbers (or the DP8228 system controller. others are )NS8080A.
Note 2: Pin 23 of the INS8228 must be tied to +12V through a 1 kG resistor to generate the RST 7
instruction when an interrupt is acknowledged as required by the accompanying sample program.

FIGURE 10. ADC0801-INS8080A CPU Interface

0038

•
•

C3 00 03

SAMPLE PROGRAM FOR FIGURE 10 ADC0801-INS8080A CPU INTERFACE
RST7:
JMP
LDDATA

•
•

•

•

0100

210002

START:

LXI H 0200H

0103
0106
0107
0109
OlOC
OlOE
OlOF
0110
0113

310004
7D
FE OF
CA130l
D3EO
FB
00
C30FOl

RETURN:

LXI SP0400H
MOVA, L
CPIOFH
JZ CONT
OUTEOH
EI
NOP
JMPLOOP

•
•
•
•
•
0300
0302
0303
0304

•
•
•
•
•
•
DBEO
77
23
C3 03 01

LOOP:
CONT:

•
(User program to
process data)

•

•
LDDATA:

; HL pair will point to
; data storage locations
; Initialize stack pointer (Note 1)
; Test # of bytes entered
; I f #= 16. JMP to
; user program
; Start AID
; Enable interrupt
; Loop until end of
; conversion

•
•
•
•
•

•
INEOH
MOVM, A
INXH
JMPRETURN

; Load data into accumulator
; Store data
; Increment storage pointer

Nole 1: The stack pointer must be dimensioned because a RST 7 instruction pushes the PC onto the stack.
Note 2: All address used were arbitrarily chosen.

2-39

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Q

co

B
c

~
-aQ

~

g
ct
....
C')

Q

co
Q

g

i
c

~
....
Q

co
Q

g

Functional Description (Continued)
The standard control bus signals of the 8080 ~, RD and
WR) can be directly wired to the digital control inputs of the
AID and the bus timing requirements are met to allow both
starting the converter and outputting the data onto the data
bus. A bus driver should be used for larger microprocessor
systems where the data bus leaves the PC board and lor
must drive capacitive loads larger than 100 pF.

It is important to note that in systems where the AID con·
verter is 1·of·8 or less 1/0 mapped devices, no address
decoding circuitry is necessary. Each of the 8 address bits
(AO to A7) can be directly used as CS inputs-one for each
1/0 device.
4.1.2 INS8048 Interface
The INS8048' interface technique with the ADC0801 series
(see Figure 11) is simpler than the 8080A CPU interface.
There are 24 1/0 lines and three test input lines in the 8048.
With these extra 1/0 lines available, one of the 1/0 lines (bit
o of port 1) is used as the chip select signal to the AID, thus
eliminating the use of an external address decoder. Bus
control signals RD, WR and iiiI'f of the 8048 are tied directly
to the AID. The 16 converted data words are stored at on·
chip RAM locations from 20 to 2F (Hex). The lID and WFi
signals are generated by reading from and writing into a
dummy address, ~espectively. A sample interface program
is shown below. '

4.1.1 Sample 8080A CPU Interfacing Circuitry and
Program
The following sample program and associated hardware
shown in Figure 10 may be used to input data from the
converter to the INS8080A CPU chip,set (comprised of the
INS8080A microprocessor, the INS8228 system controller
and the INS8224 clock gen,erator). For simplicity, the AID is
controlled as an 1/0 devi,ce, specifically an 8·bit bi·direction·
al port located at an arbitrarily chosen port address, EO. The
TRI-STATE output capability of the AID eliminates the need
for a peripheral interface device, however address decoding
is still required to generate the appropriate CS for the con·
verter.
40

ct

VCC

10
DBa

DB.
DR
DB3
014
OBI
088
INII'" DBJ

lID
WlI

lIlT
PIa

11

•• DIG

.3
.4

17 OBI

,.

II
II
14
13

'1

,.n

IVDC

OBI
DB3
014
081

11 DB1 ADCDI81
1H,F
I

10

3
I

Z7

1

...
RD

•

iNfil
Ci

ANALDG!1 v,.!+1
lN,UT l"""" V,N!-I

Vss

$.M

11 088

11

•
•

Vee

lB .,.

CLKR
eLKIN

AGND
DGND

..l!0

I
~I

~

A

'='

TLlH/567. -2'

FIGURE 11. INS8048 Interface
SAMPLE PROGRAM FOR FIGURE 11INS8048 INTERFACE
0410

JMP
ORG
JMP
ORG
ANL
MOVX

0450
99 FE
81
8901
B820
B9FF
BA10
23FF
99 FE
91
05
9821
EA1B
00
00
81
AO
18
8901
27
93

START:

AGAIN:

LOOP:

INDATA:

ORL
MOV
MOV
MOV
MOV
ANL
MOVX
EN
JNZ
DJNZ
NOP
NOP
ORG
MOVX
MOV
INC
ORL
CLR
RETR

10H
3H
50H

lOB

Pl, #OFEH
A,@Rl
Pl, #1
RO, #20H
Rl, #OFFH
R2, #lOH
A, #OFFH
Pl, #OFEH
@Rl,A
I
LOOP
R2, AGAIN

50H
A,@Rl
@RO,A
RO
Pl, #1
A
2·40

: Program starts at addr 10
; Interrupt jump vector
; Main program
; Chip select
; Read in the 1st data
; to reset the intr
; Set pcrt pin high
; Data address
; Dummy address
; Counter for 18 bytes
; Set ACC for intr locp
;SendCS (bitOofPl)
; SendWRout
; Enable interrupt
; Wai t for interrupt
; If 18 bytes are read
; go to user's program
; Input data, CS still low
; Store in memory
; Increment storage counter
; Reset CS signal
; Clear ACC to get out of
; the,interrupt loop

~--------------------------------------------------------~~

Functional Description

(Continued)

4.2 Interfacing the Z-80
The Z-80 control bus is slightly different from that of the
8080. General RD and WR strobes are provided and separate memory request, MREO, and I/O request, lORa, signals are used which have to be combined with the generalized strobes to provide the equivalent 8080 signals. An advantage of operating the AID in I/O space with the Z-80 is
that the CPU will automatically insert one wait state (the RD
and WR strobes are extended one clock period) to allow
more time for the I/O devices to respond. Logic to map the
AID in I/O space is shown in Figure 13.

:~:I
MM74C3Z

TL/H/5671-23

FIGURE 13. Mapping the AID as an I/O Device
for Use with the Z·80 CPU
Additional I/O advantages exist as software DMA routines
are available and use can be made of the output data transfer which exists on the upper 8 address lines (A8 to A 15)
during I/O input instructions. For example, MUX channel
selection for the AID can be accomplished with this operating mode.

ready decoded 475 line is brought out to the common bus at
pin 21. This can be tied directly to the CS pin of the AID,
provided that no other devices are addressed at HX ADDR:
4XXX or 5XXX.
The following, subroutine performs essentially the same
function as in the case of the 8080A interface and it can be
calied from anYwhere in the user's program.
In Figure 15the .6.DC0801 series is interfaced to the M6800
microprocessor through (the arbitrarily chosen) Port B of the
MC6820 or MC6821 Peripheral Interface Adapter, (PIA).
Here the CS, pin of. the AID is grounded since the PIA is
already memory mapped in the M6800 system and no CS
decoding is necessary. Also notice that the AID output data
lines, are connected to the, microprocessor bus under program control through the PIA and therefore the AID RD pin
can be grounded.
A sam pie interface program equivalent to the previous one
is shown below Rgure 15. The PIA Data and Control Registers of Port Bare iocated at HEX addresses 8006 and 8007,
respective.ly.

(')

5.0 GENERAL APPLICATIONS

~
~

The following, appl,ications, show ~orrie interesting uses for
the AID. The fact that one particular microprocessor is used
is not meant to be restrictive. Each of these application circuits would Have its counterpart using any microprocessor
that is desired.
To transfer analog data from several channels to a single
miproprocessor sys~em, a multiple converter scheme presents severai advantages over the conventional multiplexer
single-converter approach. With the ADC0801 series, the
differential inputs allow individual span adjustment for each
channel. Furthermore, all analog input channels are sensed
simultaneously, which essentially divides the microprocessor's total system servicing time by the number of channels,
since all conversions occur simultaneously. This scheme is
'
shown in Figure 16.

The control bus for the 6800 microprocessor derivatives
does not use the RD and WR strobe signals. Instead it employs a single R/Vii line and additional timing, if needed, can
be derived fom the 2 clock. All I/O devices are memory
mapped in the 6800 system, and a special signal, VMA,
indicates that the current address is valid. Figure 14 shows
an interface schematic where the AID is memory mapped in
the 6800 system. For simplicity, the CS decoding is shown
using % DM8092. Note that in many 6800 systems, an al-

.------------------+1iIif14I"1DI**

.----------o~

0-+--+-"'"7;

~
~

~
0
0

~

);

g
g

0
~

»
g
g
0

~
~

U'I

~.1 Multiple ADC0801 Serle~ to MC6800 CPU Interface

4.3 Interfacing 6800 Microprocessor Derivatives
(6502, etc.)

ANALDG
IN'UTS

0

AID

o-+--+-"";'-i

1-.....- - -....

Hlii 1341 1'1

&---_

DO 1331 (311

E----E----&----.-_
E----E-----

!;----_

I~:il

011321

(Z'(

DZ 1311 (KI
D31301 (HI
D41291 1311
D.IIII (301
06 ~71 (Ll

~---_DIII61

!Ii

J ! - - - - _ A I 2 ~I (301
A13

1231 (NI

j : - - - - _ A I 0 1101 (MI

1-=----_
Note 1: Numbers in parentheses refer to MC6BOO CPU pin out.
Note 2: Number or letters in brackets refer to sta,ndard M6BOO system common bus code.

~'I

(33(

?GNDIIJIWX9 I
m

FIGURE 14. ADC0801·MC6800 CPU Interface
2-41

A1&

VMA I') (F(

414243

TL/H/5671-24

•

1,1)

0
CO
0

0

Functional Description (Continued)

C

C
.....
'Oil'
0
CO
0

0

C

C
.....
C')

0
CO
0

0

C

C
.....
IN
0
CO
0

0

C

C
.....
....
0
CO
0

0

SAMPLE PROGRAM FOR FIGURE 14 ADC0801·MC6800 CPU INTERFACE
DF36
DATAIN
STX
TEMP2
; Save contents of X
CEOO 2C
LDX
; Upon IRQ low CPU
#1I002C
FFFFF8
STX
; jumps ,to 002C
IIFFF8
B75000
STAA
; Start ADC0801
115000
OE
CLI
; Wai t, for interrupt
3E
WAI
CONV~T
LDX
TEMP1'
IlE34
; Is final data stored?
8C 02 OF
CPX
#1I020F
ENDP
BEQ
2714 "
,B75000
STAA
; Restarts ADC0801
115000
08
INX
DF34
TEMPl
STX
20FO
BRA
CONVRT
DE 34
INTRPT
TEMPl
LDX
B65000
LDAA
; Read data
115000
' ; Store i t at X
A700
STAA
X
3B
RTI
0200
TEMPl
FDB
; Starting address for
110200
; data storage
FDB
000.0
TEMPla
110000
; Reinitialize TEMPl
CE0200
ENDP
LDX
#110200
S'TX
DF34
TEMPl
LDX
TEMP2
DE 36
RTS
; Return from subroutine
39
; To user's program

0010
0012
0015
0018
091B
OOlC
OOlD
OOlF
0022
0024 '
0027
0028
0024
002C,
002E
0031
0033
00.34

C

C

0036
0038
003B
003D
003F

Note 1: In order for the micrOprocessor to selVice subroutines and interrupts, the stack pointer must be dimensioned In the user's program.

"

.

18

,.

Cll
CB2

lDk

1

1

2

,h

~
4
5

ANALOG
INPUTS

150 PF

T
,h"=:F

6
7
'6

0;;-

'-J

cr

' VCC ~5V
19
CLKR
DID 18

iIIi
III

081 17
DB2 16

CLKIN

IN'fii

AID

VIN(+I
VINH
AGND
VREFI2
DGND

lD
11

083 15

12
13

014 '4
DIS 13
DBB 12

15
16

017 11

17

..

I.

PIO

PIA

P81
PIZ
PI3
PB4
PIS
PI6
PI7
TLlH/5671-25

FIGURE 15.ADC0801-MC6820 PIA Interface

2·42

~

c

Functional Description (Continued)

n
o

co

SAMPLE PROGRAM FOR FIGURE 15 ADC0801-MC6820 PIA INTERFACE
0010
0013
0016
0019
OOlA
OOlD
0020
0021
0023
0025
0028
002B
002C
002E
0031
0033
0034
0036
0038
003A
003D
003F
0040

CE 00 38
FFFFF8
B6 80 06
4F
B7 80 07
B7 80 06
OE
C634
863D
F78007
B7 80 07
3E
DE 40
8C 02 OF
270F
08
DF40
20 ED
DE 40
B6 80 06
A700
3B
0200

DATAIN

0042
0045
0047

CE0200
DF40
39

ENDP

CONVRT

INTRPT

TEMPl

PIAORB
PIACRB

LDX
STX
LDAA
CLRA
STAA
STAA
CLI
LDAB
LDAA
STAB
STAA
WAI
LDX
CPX
BEQ
INX
STX
BRA
LDX
LDAA
STAA
RTI
FDB

#$0038
$FFF8
PIAORB
PIACRB
PIAORB
#$34
#$3D
PIACRB
PIACRB

; Upon IRQ low CPU
; jumps to 0038
; Clear possible IRQ flags

; Set Port B as input

; Starts ADC0801

TEMPl
CONVRT
TEMPl
PIAORB
X
$0200

LDX
STX
RTS
EQU
EQU

#$0200
TEMPl
$8006
$8007

The following schematic and sample subroutine (DATA IN)
may be used to interface (up to) 8 ADC0801's directly to the
MC6800 CPU. This scheme can easily be extended to allow
the interface of more conve,rters. In this configuration the
converters are (arbitrarily) located at HEX address 5000 in
the MC6800 memory space. To save components, the
clock signal is derived from just one RC pair on the first
converter. This output drives the other AI Os.
All the converters are started simultaneously with a STORE
instruction at HEX address 5000. Note that any other HEX
address of the form 5XXX will be decoded by the circuit,
pulling all the CS inputs low. This can easily be avoided by
using a more definitive address decoding scheme. All the
interrupts are ORed together to insure that all AIDs have
completed their conversion before the microprocessor is interrupted.

; Is final data stored?

o
co

o

;;c
n
o

co
o
~
~

g

co
o
.co.

);
C

co
o
Con

; Read data in
; Store i t at X
; Starting address for
; data storage
; Reini tial1ze TEMPl
; Return from subroutine
; TO,user' s program

5.2 Auto-Zeroed Differential Transducer Amplifier
and AID Converter
The differential inputs of the ADC0801 series eliminate the
need to perform a differential to single ended conversion for
a differential transducer. Thus, one op amp can be eliminated since the differential to single ended conversion is provided by the differential input of the ADC0801 series. In general, a transducer preamp is required to take advantage of
the full AID converter input dynamic range.

2-43

g

oo

CPU, starts all the converters simultaneously and waits for
the interrupt signal. Upon receiving the interrupt, it reads the
converters (from HEX addresses 5000 through 5007) and
stores the data successively at (arbitrarily chosen) HEX addresses 0200 to 0207, before returning to the user's program. All CPU registers then recover the original data they
had before servicing DATA IN.

The subroutine, DATA IN, may be called from anywhere in
the user's program. Once called, this routine initializes the

);

C

; Wai t for interrupt
TEMPl
#$020F
ENDP

o.....

It)

o
~

Functional Description

(Continued)

U
C

~
.....
-=t

5Ik

o
CO
o

1

U
C

cr
~~

~

.....

•

g

,
5

ANALOG

7

INPUTS

~"I

~
C'II

oCO
o

IIII
II I I
IIII

U
C

~
....
o

th*

~

CO

~

ZD

?18

01 (32) [29(
02 fJl) [it)
03 (3D) (ii)

.v

04(21,[321
D5(28) [JO]

DB f271 If]

elKIN

DB1

07 (2B)[J1

1m!

OBZ 18

AID

VIN!.)

VINI-l

AGND

~ VREFI2
DGNO

15

DB3
084'4
13
D65

lli

DBB 12

DB7

11

C ,

·.
··
··· .·
··

···
··

f!.L f-o 5V(81!ABCj
123

"f!-

7 V7

G2A

.,

fL----..~OJDRill

G2Bf-

•

,

-;c
4

.,5

ff

~
~
18

\Wi

DBD

081 11

iNfR
VINf+)

OGND

AID

DBZ 16

M6~OO

;;--0

083 15

OB4 "
DIS 13

,

DBB U
DB7 11

V-

Z

,_r-

GND

lu!in

I

414243

VMA(5)[F]

A12(22)[341

1I2~D~ ~AA14 (241 1M)
13 (2J)[NI

.!....o=n

eLK IN

iIiTR
CI
1m
iii\

DI~

hOBO
DATA~
,

DB'

DZ

D3
01
04
: MM14CJ14

OJ

I--

~~

IIITII
B
1m AlDol
iilI

r

]

)0-

]

10--

GI

YZ

G..

Y1

...

Ie

(')

o
CO
o

DO
OJ

W
.....
):.

C

o
o

D:D

CO

D'

o

IIITII
B
lID AI"
iilI

.....
):.
~

Ie

D'

(')

o
CO
o

OJ

elKIN

DM14LSlJI

Y3

~

eLKIN

y,
y,

e

CO

o

N

OJ

elKIN

"J
y,

B

oo

DO
A/DZ

IIITII
CI
1m AID 3
~iilI

" I-OUT.01
DIS.DI '-0 ••

A

Ie

eLKIN

"

eLK

io
.....
.....
):.

iIiTR
CI
D;J
lID AID 1
D'
iii\

r

YO

r

iIiTR
CI
lID AID'

.

CI'I

.,
D:O

elKIN

iIiTR
B
lID AID'
iii\

DO

;,r-

r- tlKIN

~CLKR
;:J;lDPF

TLlH/5671-29

FIGURE 21. Multiple AIDs with Z-80 Type Microprocessor
INTERRUPT SERVICING SUBROUTINE
SOURCE
OBJCODE
STATEMENT
COMMENT
LOC

0038
0039
003A
003B
003E
0040
0042
0044
0045
0046
0048
004B
004C
004D
004E
0051
0052
0055
0057
0059
005A
005B
005C
005D
0060
0061
0062
0063

E5
C5
F5
2l003E
OEOl
D300
DBOO
47
79
FE 08
CA6000
78
lF
47
DA5500
OC
C34500
ED 78
EEFF
77
2C

TEST

NEXT
LOAD

71

2C
C3 51 00
Fl
Cl
El
C9

DONE

PUSHHL
PUSHBC
PUSHAF
LD (HL) ,X3EOO
LD C, XOl
OUT XOO, A
INA, XOO
LDB,A
LDA,C
CP, X08
JPZ, DONE
LDA,B
RRA
LDB,A
JPC, LOAD
INC C
JP,TEST
INA, (C)
XORFF
LD (HL) ,A
INCL
LD (HL) ,C
INCL
JP,NEXT
POPAF
POPBC
POPHL
RET

; Save contents of all registers affected by ; this subroutine.
; Assumed INT mode 1 earlier set.
; Initialize memory pointer where data will be stored.
; C register will be port ADDR of AID converters.
; Load peripheral status word into 8-bi t latch.
; Load status word into accumulator.
; Save the status word.
; Test to see if the status of all AID's have
; been checked. If so, exit subroutine
; Test a single bi t in status word by looking for
; a "1" to be rotated into the CARRY (an INT
; is loaded as a "1") • If CARRY is set then load
; contents of AID at port ADDR in C register.
; If CARRY is not set, increment C register to point
; to next AID, then test next bit in status word.
; Read data from interrupting AID and invert
; the data.
; Store the data
; Store AID identifier (AID port ADDR) •
; Test next bi t in status word.
; Re-establish all registers as they were
; before the interrupt.
; Return to original program
2-49

fII

Ordering Information
TEMP RANGE

ERROR

O"CTO 70'C

O'CT070"C

O"CTO 70'C

-40"CTO +S5"C
ADC0801LCN

±%Bit
Adjusted
±%Bit
Unadjusted
±%Bit
Adjusted
±1Bit
Unadjusted

PACKAGE OUTLINE

ADC0802LCWM

ADC0802LCV

ADC0802LCN

ADC0803LCWM

ADC0803LCV

ADC0803LCN

ADC0804LCWM

ADC0804LCV

M20B-Small Outline

V20A-Chip Carrier

TEMP RANGE
± % Bit Adjusted
ERROR

± % Bit Unadjusted
± % Bit Adjusted
± 1Bit Unadjusted

PACKAGE OUTLINE

ADC0804LCN

ADC0805LCN

N20A-Molded DIP

-40"CTO +S5'C

-55'CTO + 125"C

ADC0801LCJ
ADC0802LCJ
ADC0803LCJ
ADC0804LCJ

ADC0801LJ
ADC0802LJ,
ADC0802LJ/883

J20A-Cavity DIP

J20A-Cavity DIP

Connection Diagrams·
ADCOSOX
Dual-In-Llne and Small Outline (SO) Packages

CS-l

'-"

ADCOSOX
Molded Chip Carrier (PCC) Package

20 f-Vcc(OR VREF)
~CLKR

RD-2

19

Wii-3

18 ~DBO (LSD)

CLKR- 19

18 17 16 15 14
13 ~DB5

Vcc(ORVREF) - 20

12 ~DB6

ClKIN- 4

17 ~DDI

INTR- 5

16 ~DB2

CS-l

11

VIN(+)- 6

15 f-DD3

RD-2

10 f-DGND

V1N(-)";' 7

14 f-DB4

Wii-3

AGND- 8

13 ~DD5

VREF/2- 9

12 ~DB6

DGND- 10

f-DB7(MSB)
.

9 ~ VREF/2 .
4

5

6

7

8

11 f-DD7 (MSD)
TUH/5671-32

TL/H/5671-30

See Ordering Information

2-50

r----------------------------------------------------------------,~

C

(")

o
CD
o

tt/National Semiconductor

ADC08081ADC0809 8-Bit J-tP Compatible AID Converters
with 8-Channel Multiplexer
General Description

Features
• Easy interlace to all microprocessors
• Operates ratiometrically or with 5 Vee or analog span
adjusted voltage reference
• No zero or full-scale adjust required
• 8-channel multiplexer with address logic
• OV to 5V input range with single 5V power supply
• Outpu1s meet TTL voltage level specifications
• Standard hermetic or molded 28-pin DIP package
• 28-pin molded chip carrier package
• ADC0808 equivalent to MM74C949
• ADC0809 equivalent to MM74C949-1

The device eliminates the need for external zero and fullscale adjustments. Easy interlacing to microprocessors is
provided by the latched and decoded multiplexer address
inputs and latched TTL TRI-STATE® outputs.
The design of the ADC0808, ADC0809 has been optimized
by incorporating the most desirable aspects of several AID
conversion techniques. The ADC0808, ADC0809 offers high
speed, high accuracy, minimal temperature dependence,
excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device
ideally suited to applications from process and machine
control to consumer and automotive applications. For 16channel multiplexer with common output (sample/hold port)
see ADC0816 data sheet. (See AN-247 for more information.)

Block Diagram

Key Specifications
•
•
•
•
•

Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time

START

ra.m AiD -

8 Bits
±% LSB and ±1 LSB
5 Vee
15mW
100,...s

CLOCK

•

- -r----.L..---I-....,

I
I

I
B ANALOG INPUTS

B CHANNELS
I
MU~~:tt~ING t----+'-t
SWITCHES

ADDRESS
LATCH ENABLE

(")

o
CD
o

c::I

The ADC0808, ADC0809 data acquisition component is a
monolithic CMOS device with an 8-bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible control logic. The 8-bit AID converter uses successive
approximation as the conversion technique. The converter
features a high impedance chopper stabilized comparator, a
256R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can
directly access any of 8-single-ended analog signals.

I

~
C

ADDRESS
LATCH
AND
DECODER

See Ordering
Information

11

Vee .Ia

TUH/5672-1

2-51

~
c

i
c

c

Absolute Maximum Ratings (Notes 1 & 2)

Operating Conditions (Notes 1 & 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Temperature Range (Note 1)

Supply Voltage (Vee) (Note 3)

ADCOSOSCCJ, ADCOSOSCCN,

6.5V

Voltage at Any Pin
Except Control Inputs

-40·C~TA~

ADCOS09CCN
ADCOSOSCCV, ADCOS09CCV

- 0.3V to (Vee + 0.3V)

-40·C

Range of Vee (Note 1)

-0.3Vto +15V
Voltage at Control Inputs
(START, OE, CLOCK, ALE, ADD A, ADD B, ADD C)
-65·Cto + 150·C
Storage Temperature Range
Package Dissipation at T A = 25:C
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic).
Molded Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

TMIN~TA~TMAX
-55·C~TA~+125·C

ADCOSOSCJ

~

TA

~

+S5·C
+S5·C

4.5 Vee to 6.0 Vee

S75mW
260·C
300·C
215·C
220·C

ESD Susceptibility (Note 11)

400V

Electrical Characteristics
Converter Specifications: Vee=~ Vee=VREF+, VREF(-)=GND, TMIN~TA~TMAX and feLK=640 kHz unless otherwise
stated.
Symbol

Parameter

Conditions

ADCOSOS
Total Unadjusted Error
(Note 5)

TMINtoTMAX

ADCOS09
Total Unadjusted Error
(Note 5)

TMINto TMAX

Min

Typ

Max

25·C

±%.
±o/4 .'

LSB
LSB

±1
±11f4

LSB
LSB

Vee+ 0.1O

Vee

Vee

Vee + 0.1

V

Vee/2

Vee /2 + O.1

V

2

p.A

O·Cto 70"C
1.0

Units

Input Resistance

From Ref( + ) to Ref( - )

Analog Input Voltage Range

(Note 4) V(+) orV(-)

2.5

VREF(+)

Voltage, Top of Ladder

Measured at Ref( + )

VREF!+1 + VREF!-l
2

Voltage, Center of Ladder

VREF(-)

Voltage, Bottom of Ladder'

Measured at Ref( - )

-0.1

0

liN

Comparator Input Current

fc =640 kHz, (Note 6)

-2

±0.5

kO

GND-0.10

..
Vcc /2-O.1

V

Electrical Characteristics.
Digital Levels and DC Specifications: ADCOSOSCJ 4.5V~Vee~5.5V, -55·C~TA~+125·C unless otherwise noted
ADC0808CCJ, ADC0808CCN, ADC080SCCV;.ADC0809CCN and ADC0809CCV, 4.75~Vee~5.25V, -40·C~TA~ +S5·C unless otherwise noted
Symbol

I

Parameter

I

Conditions

I

Min

I

Typ

I

Max

I

Units

ANALOG MULTIPLEXER
IOFF(+)

OFF Channel Leakage Current

Vee=5V, VIN=5V,
TA=25·C .

10

TMINto TMAX
IOFF(-)

OFF Channel Leakage Current

Vee=5V, VIN=O,
TA=.?5·C
TMIN toTMAX

2-52

-200
-1.0

-10

200
1.0

nA
p.A
nA

,...A

Electrical Characteristics (Continued)
Digital Levels and DC Specifications: ADCOBOBCJ 4.5V~Vcc~5.5V, - 55°C ~ TA ~ + 125°C unless otherwise noted
ADCOB08CCJ, ADC0808CCN, ADC080BCCV, ADC0809CCN and ADC0809CCV, 4.75~Vec~5.25V, -40°C~TA~ + 85°C un·
less otherwise noted
Symbol

I

Parameter

I

Conditions

I

I

Min

Typ

I

Max

I

Units

CONTROL INPUTS
VIN(I)

Logical "1" Input Voltage

VIN(O)

Logical "0" Input Voltage

IIN(I)

Logical "1" Input Current
(The Control Inputs)

VIN=15V

IIN(O)

Logical "0" Input Current
(The Control Inputs)

VIN=O

Icc

Supply Current

fCLK=640 kHz

V

Vee- l •5
1.5

V

1.0

p.A

-1.0

p.A
0.3

3.0

mA

V

DATA OUTPUTS AND EOC (INTERRUPT)
VOUT(I)

Logical "1" Output Voltage

10= -360 p.A

VOUT(O)

Logical "0" Output Voltage

10=1.6mA

0.45
0.45

V

3

p.A
p.A'

VOUT(O)

Logical "0" Output Voltage EOC

10~1.2mA

lOUT

TRI·STATE Output Current

Vo=5V
Vo=O

V

Vee- 0.4

-3

Electrical Characteristics
Timing Specifications Vee=VREF(+)=5V, VREF(-)=GND, tr=tf=20 ns and TA=25°C unless otherwise noted.
Symbol

Typ

Max

Units

Minimum Start Pulse Width

(Figure 5)

100

200

ns

tWALE

Minimum ALE Pulse Width

(Figure 5)

100

200

ns

ts

Minimum Address Set·Up Time

(Figure 5)

25

50

ns

tH

Minimum Address Hold Time

(Figure 5)

25

50

ns

to

Analog MUX Delay Time
From ALE

Rs =

1

2.5

p.S

tHl, tHO

OE Control to Q Logic State

CL =50 pF, RL = 10k (Agure8)

125

250

ns

tlH, toH

OE Control to Hi·Z

CL = 10 pF, RL = 10k (Figure 8)

125

250

ns

1c

Conversion Time

Ie = 640 kHz, (Figure 5) (Note 7)

90

100

116

p.S

Ie

Clock Frequency

10

640

tEoe

EOC Delay Time

(Agure5)

CIN

Input CapaCitance

At Control Inputs

tws

Parameter

Conditions

Min

on (Figure 5)

0
10

1280

kHz

B+2 p.S

Clock
Periods

15

pF

TRI·STATE Output
At TRI·STATE Outputs, (Note 12)
10
15
pF
Capacitance
Note I: Absolute Maximum Ratings Indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless othewise specified.
Note 3: A zener diode exists, internally, from Vee to, GND and has a typical breakdown voltage of 7 Vee.
Note 4: Two on·chip diodes are tied to each analog input which will forward conduct for analog Input voltages one diode drop below ground or one diode drop
greater than the Veen supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage
by more than 100 mV, the output code will be correct To achieve an absolute OVec to 5Vee input voltage range will therefore require a minimum supply voltage of
4.900 Vee over temperature variations, Initial tolerance and loading.
Nota 5: Total unadjusted error Includes offset full·scale, linearity, and multiplexer errors. See Figure 3. None of these AIDs requires a zero or full-scale adjust
However, nan all zero code is desired for an analog Input other than O.OV, or na narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference
voltages can be adjusted to achieve this. See Figure 13.
Note I: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has
UIIIe tIImpetature dependence (Figtn 6). See paragraph 4.0.
Note 71 TIle outpull 01 the datil regllllr IN updated one clock cycle before the riling edge of EOC.
Note I: Human bocIy model, 100 pF dllChIIged through a 1.5 kO rulltor.

CoUT

2·53

II

Functional Description
to give fast, accurate, and repeatable conversions over a
wide range of temperatures. The converter is partitioned
into 3 major sections: the 256R ladder network, the successive approximation register, and the comparator. The converter's digital outputs are positive true.
The 256R ladder network approach (Figure 1) was chosen
over the conventional R/2R ladder because of its inherent
monotonicity, which guarantees no missing digital codes.
Monotonicity is particularly important in closed loop feedback control systems. A non-monotonic relationship can
cause oscillations that will be catastrophic for the system.
Additionally, the 256R network does not cause load variations on the reference voltage.
The bottom resistor and the top resistor of the ladder network in Figure 1 are not the same value as the remainder of
the network. The difference in these resistors ·causes the
output characteristic to be symmetrical with the zero and
full-scale points of the transfer curve. The first output transition occurs when the analog signal has reached + % lSB
and succeeding output transitions occur every 1 lSB later
up to full-scale.
The successive approximation register (SAR) performs 8 iterations to approximate the input voltage. For any SAR type
converter, n-iterations are required for an n-bit converter.
Figure 2 shows a typical example of a 3-bit converter. In the
ADC0808, ADC0809, the approximation technique is extended to 8 bits using the 256R network. '

Multiplexer. The device contains an 8-channel single-ended analog signal multiplexer. A particular inpui channel is
selected by using the address decoder. Table I shows the
input states for the address lines to select any channel. The
address is latched into the decoder on the low-to-high transition of the address latch enable signal.
TABLE I
SELECTED

ADDRESS LINE

ANALOG CHANNEL

C

B

A

INO
IN1
IN2
IN3
IN4
IN5
INS
IN7

L
l
L
l
H
H
H
H

l
l
H
H
l
l
H
H

l
H
l
H
l
H
l
H

CONVERTER CHARACTERISTICS
The Converter
The heart of this single chip data acquisition system is its 8bit analog-to-digital converter. The converter is designed

CONTROLS FROM S.A.R.
I

::J-~
R

.

256R :

•

•

TO
COMPARATOR
INPUT

R

•
R

•

•

::J-..:..

•

TL/H/5672-2

FIGURE 1. Reslltor Ladder and Switch Tree

2-54

>-

C

Functional Description

(Continued)
The AID converter's successive approximation register
(SAR) is reset on the positive edge of the. start conversion
(SC) pulse. The conversion is begun on the falling edge of
the start conversion pulse. A conversion in process will be
interrupted by receipt of a new start conversion pulse. Continuous conversion may be accomplished by tying the endof-conversion (EOC) output to the SC input. If used in this
mode, an external start conversion pulse should be applied
after power up. End-of-conversion will go low between 0
and 8 clock pulses after the rising edge of start conversion.
The most important section of the AID converter is the
comparator. It is this section which is responsible for the
ultimate accuracy of the entire converter. It is also the

comparator drift which has the greatest influence on the
repeatability of the device. A chopper-stabilized comparator
provides the most effective method of satisfying all the converter requirements.
The chopper-stabilized comparator converts the DC input
signal into an AC signal. This signal is then fed throught a
high gain AC amplifier and has the DC level restored. This
technique limits the drift component of the amplifier since
the drift is a DC component which is not passed by the AC
amplifier. This makes the entire AID converter extremely
insensitive to temperature, long term drift and input offset
errors.
Figure 4 shows a typical error curve for the ADC0808 as
measured using the procedures outlined in AN-179.

....
.
e..
u

l-

=>

liD

...
......

101

111

I-

:::>

I!:
:::> 011

~
CD

I

L

100

-ILSB
A8S0lUTE
ACCURACY

l-

~ -1/2LSB
QUANTIZATION

C 010
DOl
LU.IIB-

CI

_J

=> 011

DID

!!!
c>(")

110

co 101

100

co

CI

INFINITE RESOLUTION
PERFECT CONVERTER

111

:--FULL-SCAlE
-" ERROR = I/ZlSB

(")
CI

ERROR

ODO ......- - - - - - - - - - V I N
Q/B lIB 2IB 3IB 41B 5IB 6IB 71B

Z-'8-31B-4-1B-5-1B-6IB-7-'8- VIN

VIN AS FRACTION OF FULL-SCALE

YIN AS FRACTIQN OF FUll·SCAlE

FIGURE 2. 3-Blt AID Transfer Curve

FIGURE 3. 3-Blt AID Absolute Accuracy Curve

.,m. ", ,.

QUAN:~~~: {IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

1111111" II" 11111111111111111111111111111111111111" 111111111

INPUT OY
VOLTAGE

FUll
SCALE
TlIH/5672-3

FIGURE 4. Typical Error Curve

2-55

•

!

Connection Diagrams

....cr:

Molded Chip Carrier Package

Dual·ln·Llne Package .

CD

C

Q

gcr:
CD

IN3

1

28

IN2

IN4

2

27

INI

INS

3

26

INO

4'

25

ADD A

INS
, IN7

5

24

START

18

2-4

INI

17

2-8LSB

IN2

16

VR£F(-)

1N3

15

2- 6

2- I t.tSB
2-2

IN4

14

2-7

INS

13

GND

IN6

12

VREF(+)

ADD B
ALE

OUTPUT ENABLE
CLOCK

19

2-3

Vee

18

2-4

12

17

2-8LSB

13

16

14

15

VREF (-)
2-&

VREF (+)
GND
2- 7

....

INO

ADD C

EOC
2-5

III

~~~~;;..tt

~~st.~~,.H
s
~

TUH/5672-11

Order Number ADCOBOBCCN, ADCOB09CCN,
ADC0808CCJ or ADC0808CJ
See NS Package J28A or N2BA

TUH/5672-12

Order Number ADCOBOBCCV or AoCOB09CCV
See NS',Package V2BA
'

Timing Diagram

r-

1n

---1

CLOCK

START

'11%

/'"\

SDK
I

!--IWSALE

iCI% , ' . : \

~r'WALE-1

- r---

ADDRiSS IiD!I

I

' ,
STAI.. AOORESS

I

....

I

IS
ANALOG

INPUT

tH

"-

STAIU

;

"

K

~L1faCOMPARATOR
IN'UT
(INTERNAL NOOE)

X
f- to-

OUTPUT
EMAILE
EOC

x___

:

I

I

1-

L

Ill!

I-toc
I
1-------t.--------I1

..I}-

aUTfun • _______________ .!.R!;!!~E_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _{\._ _ _ _ _

TUH/5672-4

FIGURES

2·56

:J>
C

Typical Performance Characteristics

n
o

Q)

oQ)

.....

~

c

1.5...---r---,--T"""-"

n
o

Q)

l

o

.....
~

CD

0.5 I---+---+--.r+-H"IC--I

-0.5

I-.a'~.p--+--+---I

-1

1.25

2.5

o '--_-'-_--1._ _" - _.....
o
1.25
2.5
3.75

3.75

VIN (VI

VIN(VI
TlIH/5672-5

FIGURE 6. Comparator liN vs VIN
(VCC=VREF= 5V)

FIGURE 7. Multiplexer RON vs Y,N
(VCC=VREF=5V)

TRI-STATE Test Circuits and Timing Diagrams

Vee
OUTPUT
ENABLE

Vee
GNO --!!!:!!j-l.......- - - - -

OUTPUT
ENABLE
.

VOH~:IH

OUTPUT
GNU

tOH. CL = 10 pF

tOH. tHO
vee

'.
~
---------'=

---Jf'--50%-

tHO. CL = 50 pF

vee
OUTPUT
ENABLE

vee
GNO

OUTPUT
ENABLE
Vee
OUTPUT
':'

VOL

~

--

10%

'fi{
TlIH/5672-6

FIGURE I
2-57

m

CI

~

g

i
o

cc(

r---------------------------------------------------------------------------------~

Applications Information
Ratiometric transducers such as potentiometers, strain
gauges, thermistor bridges, pressure transducers, etc., are
suitable for measuring proportional relationships; however,
many types of measurements must be referred to an abso·
lute standard such as voltage or current. This means a sys·
tem reference must be used which relates the full·scale
voltage to the standard volt. For example, if
VCC=VREF=5.12V, then the full·scale range is divided into
256 standard steps. The smallest standard step is 1 LSB
which is then 20 mY.

OPERATION
1.0 RATIOMETRIC CONVERSION
The ADC0808, ADC0809 is designed as a complete Data
Acquisition System (DAS) for ratiometric conversion systems. In ratiometric systems, the physical variable being
measured is expressed as a percentage of full·scale which
is not necessarily related to an absolute standard. The volt·
age input to the ADC0808 is expressed by the equation
VIN
Ox
Vfs-VZ DMAX-DMIN
VIN = Input voltage into the ADC0808
Vfs=Full-scale voltage

(1)

2.0 RESISTOR LADDER LIMITATIONS
The voltages from the resistor ladder are compared to the
selected into 8 times in a conversion. These voltages are
coupled .to the comparator via an analog switch tree which
is referenced to the supply. The voltages at the top, center
and bottom of the ladder must be controlled to maintain
proper operation.

Vz=Zero voltage
Ox = Data point being measured
DMAX = Maximum data limit
DMIN=Miniml!m data limit

The top of the ladder, Ref( +), should not be more positive
than the supply, and the bottom of the ladder, Ref( -),
should not be more negative than' ground. The center of the
ladder voltage must also be near the center of the supply
because the analog switch tree changes from N-channel
switches to P·channel switches. These limitations are auto·
matically satisfied in ratiometric systems and can be easily
met in ground referenced systems.
Figure 10 shows a ground referenced system with a sepa·
rate supply and reference. In this system, the supply must
be trimmed to match the'reference voltage. For instance, if
a 5.12V is used, the supply should be adjusted to the same
voltage within 0.1 V.

A good example of a ratiometric transducer is a potentiome·
ter used as a position sensor. The position of the wiper is
directly proportional to the output voltage which is a ratio of
the full·scale voltage across it. Since the data is represented as a proportion of full-scale, reference requirements are
greatly reduced, eliminating a large source of error and cost
for many applications. A major advantage of the ADC0808,
ADC0809 is that the input voltage range is equal to the supply range so the transducers can be connected directly
across the supply and their outputs connected directly into
the multiplexer il')puts, (Figure 9).

~1---+----+------1I07

•

~---+--------~:

DIGITAL
OUTPUT
PROPORTIONAL
TO ANALOG
INPUT

DOUT

•

YIN
QOUT= YREF

VIN

=vee

4.75V:sYee=vREF:s5.25V,
• Rallom..rlc transducers
TLlH/5672-7

FIGURE 9. Ratlometrlc Conversion System

2-58

r--------------------------------------------------------------------,~

C

Applications Information (Continued)
The ADC0808 needs less than a milliamp of supply current
so developing the supply from the reference is readily accomplished. In Figure 11 a ground referenced system is
shown which generates the supply from the reference. The
buffer shown can be an op amp of sufficient drive to supply
the milliamp of supply current and the desired bus drive, or if
a capacitive bus is driven by the outputs a large capacitor
will supply the transient supply current as seen in Figure 12.
The LM301 is overcompensated to insure stability when
loaded by the 10 /LF output capacitor.

The top and bottom ladder voltages cannot exceed Vee
and ground, respectively, but they can be symmetrically less
than Vee and greater than ground. The center of the ladder
voltage should always be near the center of the supply. The
sensitivity of the converter can be increased, (i.e., size of
the LSB steps decreased) by using a symmetrical reference
system. In Figure 13, a 2.5V reference is symmetrically centered about Vee/2 since the same current flows in identical
resistors. This system with a 2.5V reference allows the LSB
bit to be half the size of a 5V reference system.

o
o

CO

o

CO

);:
C

o
o

CO

o

CD

t-----------tVcc

t - - - - - I REF(_)

DIGITAL
OUTPUT
REFERENCED
TO
GROUND

QOUT-~

VREF

AD COBOl

4.75V ,;; Vee - VREF ,;; 5.25V

FIGURE 10. Ground Referenced
Conversion System Using Trimmed Supply

Ell

>-"'--IlIcc

DIGITAL OUTPUT
REFERENCED TO
GROUND

QOUT-~

VREF

4.75V ,;; Vee - VREF ,;; 5.2SV.
ADCOBOI
Tl/H/5672-B

FIGURE 11: Ground Referenced Conversion System with
Reference Generating Vee Supply

2-59

en
Q
co
Q

r---------------------------------------------------------------------------------~

Applications Information

(Continued)

(.)

I.

C

~

111-15 VDe

~

o
cc
LM329B

:>41---...

Vee
>~_""-.REF(+)

DIGITAL OUTPUT
PROPORTIONAL TO
ANALOG INPUT
1.25V ~ VIN ~ 3.75V

·Ratiometric transducers
TLlH/5672-9

FIG~RE 13. Symmetrically Centered Reference
3.0 CONVERTER EQUATIONS

4.0 ANALOG COMPARATOR INPUTS

The transition between adjacent codes Nand N + 1 is given
by:

The dynamic comparator input current is caused by the peri·
odic switching of on-chip stray capacitances. These are
connected alternately to the output of the resistor ladderI
switch tree network and to the comparator input as part of
the operation of the chopper stabilized comparator.

VIN=

{(VREF(+l-VREF(-l)[2~6 + 5:2] ±VTUE } +VREF(-l

(2)

The center of an output code N is given by:
VIN{

(VREF(+l-VREF(-l)[2~6] ±VTUE } +VREF(-l

(3)

The output code N for an arbitrary input are the integers
within the range:
.
N

VIN-VREFH x256±AbsoluteAccuracy
VREF(+l-VREF(-l

where: VIN = Voltage at comparator input
VREF(+)=Voltage at Ref(+)
VREF(-) = Voltage at Ref(-)
VTUE=Total unadjusted error voltage (typically
VREF(+)+512)

(4)

The average value of the comparator input current varies
.directly with clock frequency and with VIN as shown in Fig-

ure6.
If no filter capacitors are used at the analog inputs and the
signal source impedances are low, the comparator input
current should not introduce converter errors, as the transient created by the capaCitance discharge will die out bafore the comparator output is strobed.
If input filter capacitors are desired for noise reduction and
signal conditioning they will tend to average out the dynamic
comparator input current. It will then take on the characteristics of a DC bias current whose effect can be predicted
conventionally.

l:ei

Typical Application

n
o

CD

o

CD
....
l:-

mD--.:D

ei

500 kHz- CLK

Aiiiiiim
DRiilIE_

DE

oCD

J ~.mmRm

EOC

5.000V- VREF(+)

n
o

CD

INTERRUPT

O.OOOV- VREF(-)

(A04-A015)'

2-1 ----+087

r

WRITE~
-

START

2-2 ---+086

ALE

2-3 ---+085

MS8

2-4 ---+084
AOO- A
AOI-B

2-5 ---+083
AOCOBOB
AOCOB09

A02- C

2-6 ---+082
2-7 ---+081

]

2-8 ---+080
5VSUPPLVY_

GROUND

VCC

In7

GNO

•
•
•

-:!-

-'.'

LS8

0-5V
ANALOG
INPUT RANGE

InO -VIN!
TL/H/5672-10
• Address latches needed for BOBS and SC/MP interfacing the ADCOBOB to a microprocessor

MICROPROCESSOR INTERFACE TABLE
PROCESSOR
8080
8085
Z-80
SC/MP
6800

READ

WRITE

INTERRUPT (COMMENT)

MEMR
RD
RD
NRDS
VMA0r/>2 o R/W

MEMW
WR
WR
NWDS
VMA°r/>°R/W

INTR (Thru RST Circuit)
INTR (Thru RST Circuit)
INT (Thru RST Circuit, Mode 0)
SA (Thru Sense A)
IRQA or IRQB (Thru PIA)

II

Ordering Information

TEMPERATURE RANGE
E
rror

L ± Yz LSB Unadjusted

I

± 1 LSB Unadjusted

Package Outline

- 40"C to
ADC0808CCN

+ 85°C

ADC0808CCV

AOC0809CCN

ADC0809CCV

N28A Molded DIP

V28A Molded Chip Carrier

2-61

-55°C to

+ 125°C

ADC0808CCJ

ADC0808CJ

J28A Ceramic DIP

J28A Ceramic DIP

~

I
~

r-------------------------------------------------------------------------------------,
ttlNational Semiconductor

ADC0811 8-Bit Serial 1/0 AID Converter
With 11-Channel Multiplexer
General Description
The ADC0811 is an 8-Bit successive approximation AID
converter with simultaneous serial 1/0. The serial input controls an analog multiplexer which selects from 11 input
channels or an internal half scale test voltage.
An input sample-and-hold is implemented by a capacitive
reference ladder and sampled data comparator. This allows
the input signal to vary during the conversion cycle.

.•
•
•
•
•
•

Separate serial 1/0 and conversion clock inputs are provided to facilitate the interlace to various microprocessors.

Features
• Separate asynchronous converter clock and serial data
1/0 clock.
• 11-Channel multiplexer with 4-Bit serial address logic.
• Built-in sample and hold function.

Connection Diagrams

Ratiometric or absolute voltage referencing.
No zero or full-scale adjust required.
Internally addressable test voltage.
OV to 5V input range with single 5V power supply.
TILIMOS input/output compatible.
0.3" standard width 20-pin dip or 20-pin molded chip
carrier

Key Specifications
•
•
•
•
•

Resolution
Total unadjusted error
Single supply
Low Power
Conversion Time

±

Y.LSB and

8-Bits
1 LSB

±

5Voc
15mW
32 "S

Functional Diagram

Dual-In-Llne Package

Vcc

120
20

Vcc

CHI

19

4>2tLK

CH2

18

SCCK

CH3

17

01

CH4

16

DO

CHS

15

cs

01'

CH6

ADDRESS
LATCH AND
DECODER

AGND

eH8

CH1D

GND

10

11

15 ~
1+_-+___......
18 SCU(
1+_-t_....___

CHO
CH1

VREF

CH7

CONTROL
AND
TIMING

ANALOG
INPUT

CH9

MUX

Top View

TlIH/5587 -1

Molded Chip Carrier (PCC) Package
SCCK 01

DO

CS

VREF

4>'CLK

19

AGND

Vcc

20

CHID

CHO

CH9

CHI

GND

CH2

CHS

IITEST

110
GND

113
AGND
Tl/H/5587-3

CH3 CH4 CHS CH6 CH7

Top View

TL/H/5587-2

Order Number ADC0811J,N, V
See NS Packag.. J20A, N20A, V20A
Use Ordering Information
2-62

)00

C

Absolute Maximum Ratings (Notes 1 & 2)

o
C)
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Molded Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Veel
6.5V
Voltage
Inputs and Outputs
-0.3V to Vee +0.3V
Input Current Per Pin (Note 3)
±5mA
Total Package Input Current (Note 3)
±20mA
Storage Temperature
-65'Cto + 150'C
Package Dissipation at TA = 25'C
875mW

00

260'C
300'C
215'C
220'C

ESD Susceptibility (Note 11)

2000V

Operating Ratings (Notes 1 & 2)
Supply Voltage (Vecl
Temperature Range
ADC0811 BCN, ADC0811 CCN
ADC0811BCV
ADC0811CCJ, ADC0811CCV

4.5 Voe to 6.0 Voe
TMIN:S:TA:S:TMAX
O'C:S:TA:S:70'C
-40'C:S:TA:S:85'C
-40'C:S:TA:S:85'C

Electrical Characteristics
The following specifications' apply for Vee = 4.75V to 5.25V, VREF = +4.6V to (Vee + O.1V), 2 elK = 2.097 MHz unless
otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ = 25'C.
ADC0811BCN, ADC0811 BCV
ADC0811 CCN, ADC0811 CCV

ADC0811CCJ
Parameter

Conditions

Typical
(Note 6)

Tested
Limit
(Note 7)

Design
Typical
Limit
(Note 6)
(Note 8)

Tested
Limit
(Note 7)

Design
Limit
(Note 8)

Units

±%
±1

±%
±1

LSB
LSB
LSB

5

kO

11

kO

CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total
VREF=5.00Voe
Unadjusted Error
(Note 4)
ADC0811 BCN, ADC0811 BCV
ADC0811 CCN, ADC0811 CCV
ADC0811CCJ

±1

Minimum Reference
Input Resistance

8

Maximum Reference
Input Resistance

8

Maximum Analog Input Range

(Note 5)

Minimum Analog Input Range
On Channel Leakage Current
ADC0811 BCJ, CCJ. BCN, CCN, On Channel = 5V
BCV,CCV Off Channel = OV
ADC0811CJ. BJ
ADC0811 BCJ, CCJ, BCN, CCN, On Channel = OV
BCV,CCV Off Channel = 5V
(Nole9)
ADC0811 BJ, CJ
Off Channel Leakage Currenl
ADC0811 BCJ, CCJ, BCN. CCN, On Channel = 5V
BCV,CCV Off Channel = OV
ADC0811CJ, BJ
ADC0811 BCJ, CCJ. BCN, CCN, On Channel = OV
BCV,CCV Off Channel = 5V
ADC0811BJ, CJ
(Nole9)

5
11

8
8

11

Vee+ 0 •05

Vee + 0.05 Vee + 0.05

V

GND-0.05

GND-0.05 GND-0.05

V

1000

400

1000

1000
-1000

nA
-400

-1000

-1000
-1000

nA
nA

-400

1000

-1000
1000

nA

nA
nA

400

1000

nA

1000

nA

Minimum VTEST
Internal Test Voltage

VREF = Vee,
CH 11 Selected

125

125

125

(Note 10)
Counts

Maximum VTEST
Internal Test Voltage

VREF=VCC.
CH 11 Selected

130

130

130

(Note 10)
Counts

2-63

.....
.....

Electrical Characteristics
The following specifications apply for VCC = 4.75V to 5.25V, VREF = +4.6V to (Vcc + 0.1V), 2 ClK = 2.097 MHz unless
otherwise specified. Boldface limIts apply from TMIN to TMAXi all other limits TA = TJ = 25'C. (Continued)
ADC0811BCN, ADC0811 BCV
ADC0811CCN, ADC0811CCV

ADC0811CCJ
Parameter

CondItIons

TypIcal
(Note 6)

Tested
LImIt
(Note 7)

DesIgn
LImIt
(Note 8)

TypIcal
(Note 6)

Tested
LImIt
(Note 7)

DesIgn
LImIt
(Note 8)

UnIts

DIGITAL AND DC CHARACTERISTICS
VIN(1), Logical "1" Input
Voltage (Min)

VCC=5.25V

2.0

2.0

2.0

V

VIN(O), Logical "0" Input
Voltage (Max)

VCc=4.75V

0.8

0.8

0.8

V

IIN(1), Logical "1" Input
Current (Max)

VIN=5.0V

IIN(O), Logical "0" Input
Current (Max)

VIN=OV

VOUT(1), Logical "1"
Output Voltage (Min)

Vcc=4.75V
IOUT= -360 p.A
IOUT= -10 p.A

VOUT(Ot Logical "0"
Output oltagEi (Max)

Vcc=5.25V
IOUT=1.6mA

lOUT, TRI·STATE Output
Current (Max)

VOUT=OV
VOUT=5V

-0.01
0.01

-3
3

ISOURCE, Output Source
Current (Min)

VOUT=OV

-12

ISINK, Output Sink Current (Min)

VOUT=VCC

Icc, Supply Current (Max)

CS = 1, VREF Open

IREF(Max)

VREF=5V

0.005

2.5

0.005

2.5

2.5

p.A

-0.005

-2.5

-0.005

2.5

-2.5

p.A

2.4
4.5

2.4
4.5

2.4
4.5

V
V

0.4

0.4

0.4

V

-0.01
0.Q1

-3
3

-3
3

p.A
p.A

-8.5

-14

-6.5

-8.5

mA

18

8.0

16

8.0

8.0

mA

1

2.5

1

2.5

2.5

mA

0.7

1

0.7

1

1

mA

AC CHARACTERISTICS
Parameter
2 ClK, 2 Clock Frequency

SClK, Serial Data Clock
Frequency
T C, Conversion Process Time

tACC, Access Time Delay From CS
Falling Edge to DO Data Valid

CondItions

Tested
TypIcal
LImIt
(Note 6) (Note 7)

MIN

0.70

MAX

3.0

2.0

2.1

MAX

700

525

525

MIN

48

48

64

84

t--

5.0

Not Including MUX
Addressing and
t - - Analog Input
MAX
Sampling Times
MIN

1

MAX

3

t--

tHl:;S,. ~ Hold Time After the Falling
EdgeofSClK

~
MAX

tHOI, Minimum 01 Hold Time from
SClK Rising Edge
tHOO, Minimum DO Hold Time from SClK
Falling Edge

1.0

MIN

t--

!sET-UP, Minimum Set-up Time of CS Falling
Edge to SClK Rising Edge

t~, TotalCSLowTime

Design
Limit
(Note 8)

0
Rl =30k,
Cl =100pF

2-64

Units

MHz

KHz
2 cycles

2 cycles

1
4/2CLK+ 2 ScLK

sec

0

ns

tsat-up + 8/ScLK

sec

tcs(min) + 48/2CLK

sec

0

ns

10

ns

l>

C

Electrical Characteristics

(")

The following specifications apply for Vcc = 4.75V to 5.25V. VREF = +4.6V to (VCC + O.W). 2 ClK = 2.097 MHz unless
otherwise specified. Boldface limits apply from TMIN to TMAXi all other limits TA = TJ = 25°C. (Continued)

co
....
....

Parameter

Tested

Typical

Conditions

(Note 6)

o

Design

Limit

Limit

(Note 7)

(Note 8)

Units

AC CHARACTERISTICS (Continued)
1501. Minimum 01 Set-up Time to SClK
Rising Edge

200

tOOO. Maximum Delay From SClK
Falling Edge to DO Data Valid

Rl =30k.
Cl=100pF

tTRI. Maximum DO Hold Time.
(CS Rising edge to DO

Cl =100pF

400

ns

180

400

400

ns

90

150

150

ns

4/ScLK+1 IJ.s

sec

Rl =3k.

TRI-STATE)
After Address Is Latched

tCA.Analog
Sampling Time

CS=Low

tROO. Maximum DO

RL =30 kn.

"TRI-STATE" to "HIGH" State

Rise Time

CL=100pf

"LOW" to "HIGH" State

tFOO. Maximum DO

RL =30 kn.

"TRI-STATE" to "LOW" State

Fall Time

Cl =100pf

"HIGH" to "LOW" State

CIN. Maximum Input

Analog Inputs. ANO-AN10 and VREF

Capacitance

All Others

75

150

150

150

300

300

75

150

150

150

300

300

11

55

5

15

ns

ns

pF

Nole 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
NOle 2: All voltages are measured with respect to ground.
Nole 3: Under over voltage conditions (VINVee) the maximum input current at anyone pin is ±5 mA.1f the voltage at more than one pin exceeds
Vee + .3V the total package current must be limited to 20 mAo For example the maximum number of pins that can be over driven at the maximum current level of
± 5 rnA is four.
Nole 4: Total unadjusted error includes offset, full·scale, linearity, multiplexer, and hold step errors.
NOle 5: Two on-chip diodes are tied to each analog Input, which will forward-conduct for analog input voltages one diode drop below ground or one diode drop
greater than Vee supply. ee careful during testing at low Vee levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at
elevated temperatures, and cause errors for analog inputs near full·scale. The spec allows 50 mV forward bias of either diode. This means that as long as the
analog VIN does not exceed the supply voltage by more than 50 mY, the output code will be correct. To achieve an absolute 0 Voe to 5 Voc input voltage range will
therefore require a minimum supply voltage of 4.950 Voe over temperature variations, initial tolerance and loading.
Note 6: Typicals are at 25"C and represent most likely parametric norm.

fII

Note 7: Guaranteed and 100% production tested under worst case condition.
Note 8: Guaranteed; but not 100% production tested. These limits are not used to calculate outgoing quality levels.
. Note 9: Channel leakage current is measured after the channel selection.

Nole 10: 1 count

= VREF/256.

Note 11: Human body model, 100 pF discharged through a 1.5 kn resistor.

Test Circuits
DO Except "TRI-5TATE"

Leakage Current
5V

5.0V

~I

0A

Fi~
I

I
I
I

CHMNEL

IILECT

•

TEST POINT
2.2k

MMO 6150
OR EQUIVA.=!NT

CHO (ON)
AOCOS11 DO
CHI (OFF)
Rl

1,·. . ~ ~
T ,.
'

Cl

CH2 (OFF)

~RM~Q~~~LENT

:

I •
I ••
I·

':"

L...!.... CH10(OFF)
TUH/5587-17

2-65

TL/H/5587-6

~ r---~------------------~-----------------------------------------------------------------'
~

!
o

Test Circuits (Continued)
tTRI "TRI-STATE"

C

TEST
POINT

2=2.,MHZ
,Vee =5.5V . Scuc =525 kHz

I'"

E 1.0

I'
I"'"
I"'"
I"'"

~

125'C

~I"""

...

25'C
-~ :.
-55'{-

0.1

VCC=VREF=5V
SCLJ(=525 kHz
TA=25'C

1.3

a

~1~~UT=Or r-

~.l!

-

....
r'"

..."""
Vcc -4.5V

-15
25
65
TEMPERATURE ('C)

10'5

Resistive Ladder Reference
Current vs Temperature
0.8

i

I

VcC=~F=5~_

0.7

2=DV
SCLJ(=OV- .

0.6

i'

~ 0.5

I"'

III

3
2(MHzl

.'_

Vce =5.25V .I I
Vcc-S·DV
::1 .....

Vcr~·75l

0.5
-55

1/>2 ClK (MHz)

11.4

r---. .

ISOURCE Your =2.4V

's

.C 1.5

Power Supply Current vs
2 Clock Frequency

1.2
1.1

10

.~

r----

~

~III:EVoUT'=IDV

,

Power Supply Current
vs Temperature
.

SeLJ( =525 kHz
Vce = VaEF = 5V

-25
25
75
125
TEM'PERATliRE ('C)

ifi
:=

·lS

o

iii

0.1

........

-100 -50·0
50 100' 125
TEMPERATURE ('C)

~

'"
Ii!

Vcc=6Vac

~ ISINK puT'!'5Y

20

Linearity vs 2 Clock·
Frequency
.

Linearity vs Temperature

iii 0.4

i

iii
B

!Ii=
0.5
z
::::I

0.5

25

1...5
I/>z=2.1 MHz
1.25 l-~eLJ( =525 kH~
Vcc=5V
TA=25'C
1.0

!iii 0.75

I

I

Output Current vs· .
Temperature
.

Linearity Error vs VREF
Voltage

0.4
0.3
-55

,
-15
25
65
TEMPERATURE ('CI

.

105
TLIH15587-16

.1

Timing Diagrams
DO "TRI-STATE" Rise & Fall Times

DO Low to High State

IROO
DD

DO. 1.2V-TRI-8TATE-I:-II--...,----

DO High to Low State

....~IRDO
2.4""V---D.4V

___

DD

~

TL/H/5587-14

TLlH/5587-15

1'00
TLlH/5587-13

Timing with a continuous SCLK

SCLK

,..-->E~

DO
TLlH/5587-11

·Strobing ~ High and Low will abort the present conversion and initiate a new serial 1/0 exchange.

Timing with a gated SCLK and CS Continuously Low

SCLK

DD _ _ _D_7_ _

..

~~--~~__~~I~~,,.-

TL/H/5587-9

Using CS To TRI-STATE DO

SCLK

:E)(::!:)--_. .

TRI-8TATE-(!
TL/H/5587-10

Note: Strobing

es Low during this time interval will abort the conversion in process.

2-67

»
c
oo
CO
.....
.....

..-

8
c

,-----------------------------------------------------------------------------------------------,
Timing Diagrams (Continued)

cc

CS High During Conversion
tCA
CHANNEL ----<+-ACQUtStTtDN

I

...."".0----164 "'2 CLDCKS------.!""._------

(MtN)

scU(
9-,~

Dt

______________

_ I ,---', ' - - I

II

~

__________r

............

DO
TLlH/5587 -4

CS Low During Conversion
tCA

- - -...·t·o---A~;~t~~T~~N ------1------'64 "'2 CLOCKS------.ro------- A::~a:~D~~E~~jN - - - - - I
(MtN)

scU(

~l~_____________________ ~------------------~r

DO
Tl/H/5587 -5

Note: DO and 01 lines share the 8-bit 1/0 shift register(see Functional Block Diagram). Since the MUX address bits are shifted in on SClK rising edges while SClK
falling edges shift out conversion data on DO. the eighth falling edge of SClK will shift out Ihe MSB MUX address bil (A7) on DO. Thus. if addressing channels
CH8-CH10. a high DO will occur momenlarily (one 4>2 clock period) untillhe 8-bi11/0 shift regisler is cleared by the Internal EOC signal.

Channel Addressing Table
TABLE I. ADC 0811 Channel Addressing

MUX 'ADDRESS
ANALOG CHANNEL
SELECTED
A7 A6 As A4 A3 A2 A, AO
0 X X X X
CHO
0 0
0
0
0 0
1 X X X X
CH1
0 0
1 0 X X X X
CH2
0
0 1 1 X X X X
CH3
1 0 0 X X X X
CH4
0
0
1 0
1 X X X X
CH5
1 1 0 X X X X
CH6
0
1 1 1 X X X X
0
CH7
1 0 0
0 X X X X
CH8
1 0 0
1 X X X X
CH9
1 0
1 0 X X X X
CH10
1 1 X X X X
1 0
VTEST
1 1 X X X X X X LOGIC TEST MODE·
• Analog channel inputs CHO thru CH3 are logic outputs

2-68

"11
C

~

n

O·
~

e!-

m

1- t ~

_1~2

0'

ICDMP

n

~

CONVERSION
TIMING GENERATORS

C

i'
cc

SAR

SAR

Dl
3

CC

Se.. I!!I

_I

Il>

YYYYYYYj

ffi

01117]

i.

• r-"\

F::::L?1.~

Iii)GNO

rnlVREF

. .J

Il!IAGNO

16100
TUH/5587-8

~~80:>a"

....
....
co

8
c

cc

Functional Description
1.0 DIGITAL INTERFACE
The AOeOB11 uses five input/output pins to implement the
serial interface. Taking chip select (CS) low enables the 1/0
data lines (DO and 01) and the serial clock input (SCLK)' The
result of the last conversion is transmitted by the AID on the
DO line, while simultaneously the 01 line receives the address data that selects the mux channel for the next conversion. The mux address is shifted in on the rising edge of
SCLK and the conversion data is shifted out on the falling
edge. It takes eight SCLK 'cycles to complete the serial 1/0.
A second clock (4)2) controls the SAR during the conversion
process and must be continuously enabled.

this mux addresslsample cycle, data from the last conversion is also clocked out on ~O. Since 07 was clocked out
on the falling edge of es only data bits 06-00 remain to be
received. The following seven falling edges of SCLK shift out
this data on ~O.
The Bth SCLK falling edge initiates the beginning of the AID's
actual conversion process which takes between 4B to 64 4>2
cycles (Te). During this time es can go high to TRI-STATE
DO and disable the SCLK input or it can remain low. If es is
held Iowa new 1/0 exchange will not start until the conversion sequence has been completed, however once the conversion ends serial 1/0 will immediately begin. Since there is
an ambiguity in the conversion time (Tc) synchronizing the
data exchange is impossible. Therefore es should go high
before the 4Bth 4>2 clock has elasped and return low after
the 64th 4>2 to synchronize serial communication.

1.1 CONTINUOUS SCLK
With a continuous SCLK input es must be used to synchronize the serial data exchange (see Figure 1). The AoeOB11
recognizes a valid es one to three 4>2 clock periods after
the actual falling edge of es. This is implemented to'ensure
noise immunity of the es signal. Any spikes on es less than
one 4>2 clock period will be ignored. es must remain low
during the complete 1/0 exchange which takes eight SCLK
cycles. Although es', is not immediately acknowledged for
the purpose of starting a new conversion, the falling edge of
CS immediately enables DO to output the MSB (07) of the
previous conversion.
The first SCLK rising edge will be acknowledged after a set-'
up time (t.et-up) has,elapsed from the falling edge of es.,
This and the following seven SCLK rising edges will shift in
the channel address forthe analog multiplexer. Since there are
12 channels only four address bits are utilized, The first four
SCLK cycles clock in the mux address, during the next four
SCLK cycles the analog input is selected and sampled. During
SERIAL DATA
INPUT
4 MSB OUTPUT

A conversion or 1/0 operation can be aborted at any time by
strobing es. If CS is high or low less than one 4>2 clock it will
be ignored by the AID. If the CS is strobed high or low
between 1 to 3 4>2 clocks the AID mayor may not respond.
Therefore es must be strobed high or low greater than 3 4>2
, clocks to ensure recognition. If a conversion or 110 exchange is aborted while in process the consequent data
output will be erroneous until a complete conversion sequence has been implemented.
1.2 DISCONTINUOUS SCLK
Another way to accomplish synchronous serial communication is to tie CS low continuously and disable SCLK after its
Bth falling edge (see Figure 2). SCLK must remain low for

ANALOG VOLTAGE
ACQUISITION WINDOW
4 LSB DATA OUTPUT

CONVERSION PROCESS

SCLK

TL/H/5587-18

FIGURE 1
CONVERSION PROCESS
SERIAL DATA
INPUT
4 MSB OUTPUT

CS (LOWI

SCU(

ANALOG VOLTAGE
ACQUISITION WINDOW
4 LSB DATA OUTPUT

DATA MAY
BE OUTPUT
BETWEEN

------~------~-------+------~~~~~
-----I

DO
TL/H/5587-19

FIGURE 2
2-70

»

Functional Description

(Continued)

at least 64 <1>2 clocks to insure that the AID has completed
its conversion. If SCLK is enabled sooner, synchronizing to
the data output on DO is not possible since an end of conversion signal from the AID is not available and the actual
conversion time is not known. With CS low during the conversion time (64 <1>2 max) DO will go low after the eighth
falling edge of SCLK and remain low until the conversion is
completed. Once the conversion is through DO will transmit
the MSB. The rest of the data will be shifted out once SCLK
is enabled as discussed previously.

eighth SCLK falling edge. The hold mode is initiated with the
start of the conversion process. An acquisition window of
4tSCLK + 1 ,..,sec is therefore available to allow the ladder
capacitance to settle to the analog input voltage. Any
change in the analog voltage before or after the acquisition
window will not effect the A/D conversion result.
In the most simple case, the ladder's acquisition time is determined by the Ron (3K) of the multiplexer switches and the
total ladder capacitance (90pf). These values yield an acquisition time of about 2 ,..,sec for a full scale reading. Therefore the analog input must be stable for at least 2 ,..,sec
before and 1 ,..,sec after the eighth SCLK falling edge to
ensure a proper conversion. External input source resistance and capacitance will lengthen the acquisition time and
should be accounted for.

If CS goes high during the conversion sequence DO is tristated, and the result is not affected so long as CS remains
high until the end of the conversion.
1.2 MULTIPLEXER ADDRESSING

The four bit mux address is shifted, MSB first, into 01. Input
data corresponds to the channel selected as shown in table
1. Care should be taken not to send an address greater than
or equal to twelve (11 XX) as this puts the A/D in a digital
testing mode. In this mode the analog inputs CHO thru CH3
become digital outputs, for our use in production testing.

Other conventional sample and hold error specifications are
included in the error and timing specs of the AID. The hold
step and gain error sample/hold specs are taken into account in the ADC0811's total unadjusted error, while the
hold settling time is included in the AID's max conversion
time of 64 <1>2 clock periods. The hold droop rate can be
thought of as being zero since an unlimited amount of time
can pass between a conversion and the reading of data.
However, once the data is read it is lost and another converSion is started.

2.0 ANALOG INPUT
2.1 THE INPUT SAMPLE AND HOLD

The ADC0811's sample/hold capacitor is implemented in its
capacitive ladder structure. After the channel address is received, the ladder is switched to sample the proper analog
input. This sampling mode is maintained for 1 ,..,sec after the

Typical Applications
ADC0811-INS8048 INTERFACE

Pl0
INS8048 Pll
P12

t---+t~lK
DI

~~~ ~}

AUC0811

00

r-- rP2

•
:
•

ELEVEN ANALOG
INPUTS

CHID ~

TL/H/5587-21

2-71

c
oo

CCI
.....
.....

~ r-------------------------------------------------------------------------------------~
~

ADC0811 FUNCTIONAL CIRCUIT

B

5V

Q

c(
Uk

5V

14 Vee
01
1

~

19

CHO
CHI

-I/lZCU(

CH2
CH3
CH4

~

SeU(

CH5
CHI
CH7
CHI
CHI

SHIFT/DIlII 1
74CI65

CHID

QA

5

":'

4

14

13

12

11

5V

Uk

_TL/H/5587-20

Ordering Information
Temperature Range
Total Unadjusted
Error

±1f2 LSB
±1 LSB

O"Cto 70·C
ADC0811BCN
ADC0811CCN

N20A

Package Outline

2·72

-40"Cto +85"C

ADC0811BCV
ADC0811CCJ
ADC0811CCV
J20A,V20A

r----------------------------------------------------------------.>
c

o
c

...

tflNational Semiconductor

00

ADC08161 ADC0817 8-Bit JLP Compatible AID Converters
with 16-Channel Multiplexer
General Description

Features

The ADC0816, ADC0817 data acquisition component is a
monolithic CMOS device with an 8-bit analog-to-digital converter, 16-channel multiplexer and microprocessor compatible control logic. The 8-bit AID converter uses successive
approximation as the conversion lechnique. The converter
features a high impedance chopper stabilized comparator, a
256R voltage divider with analog switch tree and a successive approximation register. The 16-channel multiplexer can
directly access anyone of 16-single-ended analog signals,
and provides the logic for additional channel expansion. Signal conditioning of any analog input signal is eased by direct
access to the multiplexer output, and to the input of the 8-bit
AID converter.
The device eliminates the need for external zero and fullscale adjustments. Easy interfacing to microprocessors is
provided by the latched and decoded multiplexer address
inputs and latched TTL TRI-STATE® outputs.

• Easy interface to all microprocessors, or operates
"stand alone"
• Operates ratiometrically or with 5 Voc or analog span
adjusted voltage reference
• 16-channel multiplexer with latched control logic
• Outputs meet TTL voltage level specifications
• OV to 5V analog input voltage range with single 5V supply
• No zero or full-scale adjust required
• Standard hermetic or molded 40-pin DIP package
• Temperature range ~40'C to +85'C or -55'C to
+125'C
• Latched TRI-STATE output
• Direct access to "comparator in" and "multiplexer out"
for Signal conditioning
• ADC0816 equivaient to MM74C948
• ADC0817 equivalent to MM74C948-1

The design of the ADC0816, ADC0817 has been optimized.
by incorporating the most desirable aspects of several AID
conversion techniques. The ADC0816, ADC0817 offers high
speed, high accuracy, minimal temperature dependence,
excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device
ideally suited to applications from process and machine
control to consumer and automotive applications. For similar performance in an 8-channel, 28-pin, 8-bit AID converter, see the ADC0808, ADC0809 data sheet. (See AN-258
for more information.)

Key Specifications
Ii
II

Resolution
Total Unadjusted Error
• Single Supply
• Low Power
• Conversion Time

8 Bits
±% LSB and ±1 LSB
5 Voc
15 mW
100,...s

Block Diagram
COMPARATOR IN

START

CLOCK

MULTIPLEXER

OUT

ri.';;;:Zii -- -..----II-_....L._..

I

~==::::;I-

I
I

__

-oENDDF CONVERSION

IINTERRUPTI

I
I
I

18 ANALOG INPUTS

ADDRESS LATCH ENABLE

ADDRESS
LATCH
AND
DECODER

EXPANSION CONTROL

11

Vee

OUTPUT

ENABLE

GND

TL/H/5277-1

2-73

en
.....
>
c

o
c

........
00

"'.,..."
8c
~.,...
co

co

o

(.)

C

 640 kHz, the minimum start pulse width is 8 clock periods plus 2 ,..s. For synchronous operation
at Ie ,;: 640 kHz take start high within 100 ns of clock going low.
Note 8: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 9: Human body model, 100 pF discharged through a 1.5 k!l resistor.

2-75

•

.........
~
g
~
....
CD

8
c

--0---1 Vcc

III

DIGITAL OUTPUT
REFERENCED TO
GROUND

a OUT-- VREF
~
4.7SV"VCC=VREF"S.2SV
ADcoaI6,17
TL/H/5277-13

FIGURE 11. Ground Referenced Conversion System with
Reference Generating Vee Supply

2-81

.,...

I'-

CD

8c
~
.,...

Applications Information (Continued)
ID-15VOC
Ik

g
CD

HI

1000 pF

c(
lM329B ".......--ot
HZ
lOT

Vcc
>-1~""-.HEF(+1

R3

HEFH
TL/H/5277 -14

FIGURE 12. Typical Reference and Supply Circuit
5V

_'V\rv-...- t VCC
r-__",__",___"_~",,,""__..;3:;:.7::.5V~HEF(+1
~""--II--+-----f Inl5

DOUT

DIGITAL OUTPUT
TO
ANALOG INPUT
I.Z5V,; VIN ~ 3.75V
P~OPOHTIONAl

.....---4 lnO
~_ _" ,_ _",,,,,,,_ _,,,,_~,,,,,""_ _..;I:;:.Z::;5V~HEF(_1

Z.5V
REFERENCE

RA=RB

.....W'\/-...--1GNO

* Rstlometric transducers
TL/H/5277-15

FIGURE 13. Symmetrically Centered Reference
3.0 CONVERTER EQUATIONS
The transition between adjacent codes Nand N + 1 is
given by:
VIN= {

(VAEF(+)-VAEF(-)1[2~6 + 5:2] ±VTUE }

+VAEF(-)

. The output code N for an arbitrary input are the integers
within the range:
VIN-VREF(-l X256±AbsoluteAccuracy
VREF(+)-VREF(-)
where: VIN = Voltage at comparator input
N

(2)

The center of an output code N is given by:
VIN= {

(VAEF(+)-VAEF(-))[2~6] ±VTUE] +VAEF(-)

VREF = Voltage at Ref( +)
VREF = Voltage at Ref( -)
VTUE = Total unadjusted error voltage (typically

(3)

VREF(+) +512)

2-82

(4)

~

c

Applications Information (Continued)
4.0 ANALOG COMPARATOR INPUTS

If no filter capacitors are used at the analog or comparator
inputs and the signal source impedances are low, the comparator input current should not introduce converter errors,
as the transient created by the capacitance discharge will
die out before the comparator output is strobed.

The dynamic comparator input current is caused by the peri·
odic switching of on-chip stray capacitances These are connected alternately to the output of the resistor ladder/switch
tree network and to the comparator input as part of the
operation of the chopper stabilized comparator.

If input filter capacitors are desired for noise reduction and
signal conditioning they will tend to average out the dynamic
comparator input current. It will then take on the characteristics of a DC bias current whose effect can be predicted
conventionally. See AN·258 for further discussion.

The average value of the comparator input current varies
directly with clock frequency and with Y,N as shown in Fig·

ure6.

Typical Application

1--"---.

ADDRESS
DECODE
(AD4-AD151*

INTERRUPT

ADC0816
ADC0811

IN15

COMMON OUT
COMPARATOR
IN

• '"
•
•
INa

"]

O-5V
ANALOG
INPUT RANGE

V,N1
TL/H/5277-t6

• Address latches needed for BOB5 and SC/MP interfacing the ADCOB t6, 17 to a microprocessor

Microprocessor Interface Table
PROCESSOR
8080
8085
Z-80
SC/MP
6800

READ

WRITE

INTERRUPT (COMMENT)

MEMA
AD
AD
NADS
VMAe",2eA/W

MEMW
WR
WA
NWDS
VMAeQ2eR7W

INTA (Thru AST Circuit)
INTR (Thru AST Circuit)
INT (Thru RST Circuit, Mode 0)
SA (Thru Sense A)
IAQA or TRQB (Thru PIA)

Ordering Information
- 40'C to

TEMPERATURE RANGE
Error

I
I

± % Bit Unadjusted

ADC0816CCN

± 1 Bit Unadjusted

ADC0817CCN

Package Outline

N40A Molded DIP

2-83

+ 85'C
ADC0816CCJ

J40A Hermetic DIP

n
o

CD
....
0)

);
c
n
o

....
.....
CD

....

G)

~

tfI Nat ion a I S e.m

i con due tor

ADC0819 8-Bit Serial 1/0 AID Converter
with 19-Channel Multiplexer
General Description
The 'ADC0819 is an 8-Bit successive approximation AID
converter with' simultaneous serial 1/0, The serial input controls an analog multiplexer which selects from 19 input
channels or an internal half scale test voltage,
An input sample-and-hold is implemented by a capacitive
reference ladder and sampled data comparator, This allows
the input signal to vary during the conversion cycle.
Separate serial 1/0 and conversion clock inputs are provided to facilitate the interface to various microprocessors.

Features
• Separate asynchronous converter clock and serial data
1/0 clock.
• 19-Channel multiplexer with 5-Bit serial address logic.
• Built-in sample and hold function.

Connection Diagrams

•
•
•
•
•
•

Ratiometric or absolute voltage referencing.
No zero or full-scale adjust required.
Internally addressable test voltage.
OV to 5V input range with single 5V power supply.
TTL/MOS input/output compatible.
28-pin molded chip carrier or 28-pin molded DIP

Key SpeCifications
•
•
•
•
•

8-Bits

Resolution
Total unadjusted error
Single supply
Low Power
Conversion Time

± 1f2LSB and ± 1LSB
5Voc
15mW
16,...s

Functional Diagram

Molded Chip Carrier (PCC) Package

25 2" 23 22 21 20 19

Sa..

26

18

CHI6

17
16

CH1S

Va:

27
28
I
2
3
4

IS
14
13

.....
ClIO
~I

C112
C113

CHI4
CHI3

01'
ADDRESS

wt1I AND

23

DeCODER

CONTROL
AND
T1MIN&

GNo
CH12

a

1+-_+-......_;;;.28 So..

CNl1

TLlH/92B7-1 .

Top View
Order Number ADC0819BCV, CCV
See NS Package Number V28A
Dual-In-Llne Package
CHD

I

CIII
CH2

2
3
4

CII3

CII4

CN.

•

CH6

28
27
26
25
24

Va:·

vo,,+

01
00

D

CiS·

22

V.,.(+)
V".{")

CN7

8

CH8

9
10

21
20
19

CHI8

18
17
16

Cl-l15

CHI2

11
12
13

GHD

14

I.

CII9
CHID
CHII

. -_ _ _ _--=22

f2CLK
SdK

CHI7
CHI6

1'4

GWO

CHI4
CHI!

TLlH/92B7-2

TL/H/92B7-20

Top View
Order Number ADC0819BCN, CIN
See NS Package Number N28B

2-84

~

c

Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)

6.5V

Voltage
Inputs and Outputs

-0.3VtoVee +0.3V

Input Current Per Pin (Note 3)

±5mA

Total Package Input Current (Note 3)

215'C
220'C

ESD Susceptibility (Note 11)

2000V

260'C

Supply Voltage (Vecl

- 65'C to + 150'C

Package Dissipation at T A = 25'C

Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (Plastic) .
Surface Mount Package
Vapor Phase (60 sec.)
Infrared (15 sec.)

OJ
.....
CD

Operating Ratings (Notes 1 & 2)

±20mA

. Storage Temperature

n
o

4.5 Voe to 6.0 Voe

Temperature Range

B75mW

TMIN S; TA S; TMAX
-40'C S; TA S; +B5'C

ADCOB19BCV, ADCOB 19CCV
ADCOB19BCN
ADCOB19CIN

O'C

S;

TA

S;

+70'C

-40'C

S;

TA

S;

+85'C

Electrical Characteristics
The following specifications apply for Vee = 5V, VREF = 5V, cf>2 elK = 2.097 MHz unless otherwise specified. Boldface limits
apply from T MIN to T MAX; all other limits T A = T J = 25'C.
Parameter

Conditions

Typical
(Note 6)

Tested
Limit
(Note 7)

Design
Limit
(Note 8)

Units

±1f2
±1

±%,
±1

LSB
LSB

5

kO

CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total
Unadjusted Error
ADCOB19BCV, BCN
ADCOB19CCV, CIN

VREF= 5.00 Voe
(Note 4)

Minimum Reference
Input Resistance

B

Maximum Reference
Input Resistance
Maximum Analog Input Range

B
(Note 5)

Minimum Analog Input Range
On Channel Leakage Current

(Note 9)
On Channel = 5V
Off Channel = OV
On Channel=OV
Off Channel = 5V
(Note 9)

Off Channel Leakage Current

(Note 9)
On Channel = 5V
Off Channel = OV
On Channel = OV
Off Channel = 5V
(Note 9)

11

kO

Vcc+ 0.05

Ycc+ 0 •05

V

GND-0.05

GND-0.05

V

400

1000

nA

-400

-1000

nA

-400

-1000

nA

400

1000

nA

11

Minimum VTEST
Internal Test Voltage

VREF=Vee,
CH 19 Selected

125

125

(Note 10)
Counts

Maximum VTEST
Internal Test Voltage

VREF=Vee,
CH 19 Selected

130

130

(Note 10)
Counts

2.0

2.0

V

O.B

0.8

V

2.5

2.5

/J- A

-2.5

-2.5

/J-A

DIGITAL AND DC CHARACTERISTICS'
VIN(l), Logical "1" Input
Voltage (Min)

Vee=5.25V

VIN(O), Logical "0" Input
Voltage (Max)

Vee=4.75V

IIN(l), Logical "1" Input
Current (Max)

VIN=5.0V

IIN(O), Logical "0" Input
Current (Max)

VIN=OV

0.005
-0.005

2-85

fII

Electrical Characteristics

(Continued)
The following specifications apply for Vee = 5V, VREF =. 5V, 2 CLK = 2.097 MHz unless otherwise specified. Boldface limits
apply from T MIN to T MAX; all other limits T A = TJ = 25'C.
Parameter

Typical
(Note 6)

Conditions

Tested
Limit
(Note 7)

Design
Limit
(Note 8)

Units

2.4
4.5

2.4
4.5

V.
V

0.4

0.4

V

-3
3

-3
3

p.A
p.A

-6.5

-8.5

rnA

DIGITAL AND DC CHARACTERISTICS (Continued)
VOUT(lt Logical "1"
Output oltage (Min)

Vee = 4.75V
IOUT= -360 p.A
IOUT=-10 p.A

VOliT(ot Logical "0"
Output oltage (Max)

Vcc=5.25V
IOUT=1.6mA

lOUT, TRI-STATE Output
Current (Max)

VOUT=OV
VOUT=5V

-0.01
0.Q1

ISOURCE, Output Source
Current (Min)

VOUT=OV

-14

ISINK, Output Sink Current (Min)

VOUT=Vee

16

8.0

8.0

rnA

lee, Supply Current (Max)

CS=1, VREFOpen

1

2.5

2.5

rnA

IREF(Max)

VREF=5V

0.7

1

1

rnA

AC CHARACTERISTICS
Parameter

2 eLl~, 2 Clo~k Frequency

SCLK, Serial Data Clock
FrequenCy
Te, Conversion Process TIme

tAce, Access TIme Delay From CS
Falling Edge to DO Data Valid

Conditions

Tested
Typical
Lllllit
(Note 6) (Note 7)

MIN

0.70

MAX

4.0

2.0

2.1.

MAX

1000

525

525

MIN

26

28

32

32

'--MIN

Not Including MUX
Addressing and
c--MAX Analog Input
Sampling Times
MIN

1

MAX

3

i---

~

KHz

2 cycles

2 cycles

1
412CLK + 2 ScLK

sec

0

ns

t ••t_up + 8/ScLK

sec

t5m l n )+ 28/2CLK

MAX

tHOO, Minimum DO Hold Time from SCLK
Falling Edge

MHz

5.0

"-

tHC:S, CS Hold Time After the Falling
EdgeofSCLK

tHOI, Minimum 01 Hold Time from
SCLK Rising Edge

Units

1.0

tsET-UP, Minimum Set-up Time of CS Falling
Edge to SCLK Rising Edge

t~, Total CS L.:ow Time

. Design
Limit
(Note 8)

0

0
RL =30k,
CL =100pF

tSOIo Minimum 01 Set-up Time to SCLK
Rising Edge

200

'

.

sec
ns

10

ns

400

ns

tooo, Maximuni Delay From SCLK
Failing Edge to DO Data Valid

RL =30k,
CL=100pF

180

200

250

ns

tTRI, Maximum Do Hold Time,
(CS Rising edge to DO TRI-STATE)

RL =3k,
CL =100pF

90

150

150

ns

2-86

Electrical Characteristics

The following specifications apply for Vee = 5V, tr= tf= 20 ns, VREF = 5V, unless
otherwise specified. Boldface limits apply from T MIN to T MAX; all other limits T A = T J = 25°C.

Parameter

Typical

Conditions

(Note

6)

Tested

Design

Limit

Limit

(Note 7) .

Units

(Note 8)

AC CHARACTERISTICS (Continued)
After Address Is Latched

IeA,Analog
Sampling Time

a/ScLK+i iJ.s

CS=Low
75

150

150

150

300

300

tROD, Maximum DO

RL =30 kG,

"TRI-STATE" to "HIGH" State

Rise Time

CL =100pf

"LOW" to "HIGH" State

tFDO, Maximum DO

RL=30 kG,

"TRI-STATE" to "LOW" State

75

150

150

Fall Time

CL=100pf

"HIGH" to "LOW" State

150

300

300

CIN, Maximum Input

Analog Inputs, ANO-AN10 and VREF

11

55

Capacitance

All Others

5

15

sec

ns

ns

pF

Nole 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.

Nole 2: All voltages are measured with respect to ground.
Note 3: Under over voltage conditions (VIN  Vee) the maximum input current at anyone pin is ± 5 mAo If the voltage at more than one pin exceeds
Vee + .3V the total package current must be limited to 20 mAo For example the maximum number of pins that can be over driven at the maximum current level of
± 5 mA is four.
Nole 4: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
Nole 5: Two on·chip diodes are tied to each analog input, which will forward-conduct for analog input voltages one diode drop below ground or one diode drop
grealer Ihan Vee supply. Be careful during testing at low Vee levels (4.5V), as high level analog inputs (5V) can cause this input diode 10 conduct, especially at
elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the
analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 Voc to 5 Voc input voltage range will
therefore require a minimum supply vollage of 4.950 Vee over temperature varialions, initial tolerance and loading.
Nole 6: Typicals are at 25·C and represent most likely parametric norm.
Nole 7: Tested limits are guaranteed to National's AOQl (Average OutgOing Quality level).
Note 8: Design Limits are guaranteed, but not 100% production tested. These limits are not used to calculate outgOing quality levels.
Note 9: Channel leakage current is measured after the channel selection.

Note 10: 1 count

= VREF/256.

Nole 11: Human body model; 100 pF discharged through a 1.5 kG resistor.

Test Circuits
DO Except "TRI-STATE"

Leakage Current

5.0Y

5Y

~

.0-

I

bJ
'::'

I
I

I
I
I
I
CHANNEL
SELECT

~.
I
I
I

TEST POINT

MMO 6150
Oft EQUIYA~NT

2.2k

1, ~, ,

CHO (ON)

ADCOB19 00
CHI (OFF)
ftL

TeL

CH2 (OFF)

,

~

,

, MMD7DDO
F- OR EQUIVALENT

:

~

•

L..!....

TL/H/9287 -4

CH1B (Off)
TUH/9287-3

Timing Diagrams

ITRI"TRI·STATE"
TEST
POINT

DO "TRI·STATE" Rise & Fall Times

I-'·1 lJ

5.0Y

~

~tRDO

-+

DD 1.2V-TRI-STATE

-+

~

f'

2.4V
0.4V
fo-tFDD

TL/H/9287-6
TL/H/9287-5

2·87

Timing Diagrams (Continued)
DO High to Low State

DO Low to High State

l

t RDO

DD _ _ _ _
oiiII 2.4~V---•
D 4V

DD
TL/H/9287-8

TLlH/9287 -7

Data Input and Output Timing

SCLI(

DI

DD

.JlI_~

__

----1'1"1,.....TLlH/9287 -9

Timing with a continuous ScLK

TL/H/9287-10

'Strobing i::S High and Low will abort the present conversion and initiate a new serial 110 exchange.

Timing with a gated ScLK and CS Continuously Low
ATAI/O EXCHANGECYCLE--

SCLI(

CSILDW)
DD

~
0

1 6

7

~--I--+-

-----~---+--~--~DT

D7
TLlH/9287-11

-:-1

Using CS To TRI-5TATE DO

TelSEE NOTE)

~---"'--~

TLlH/9287-12

Note: Strobing i::S Low during this Urns Interval will abort the convaralon In process.

2-88

.--------------------------------------------------------------------,~

c

Timing Diagrams (Continued)

o
o

....
Q)

CS High During Conversion

CD

Sc..

r

~-,~--------------~
DI

_ _ _ _ _ _ _ _ _---I

--.J''-.l'---'''----'

DO
TL/H/92B7 -13

CS Low During Conversion

~ ~~~ ---·+-I·~A~~:~~~N-I-I
tCA

ADDRESS

Sm

TC(MAXI

(MINI

012

"l~_____________________ ~------------------__~r

DO
TL/H/92B7-14

Channel Addressing Table
TABLE I. ADC 0819 Channel Addressing
MUXADDRESS
A7
O'
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1

As
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1

As A4 A3 A2 A1
0
0
0
X X
0
0
1
X X
1
0
X X
0
0
1
1
X X
1
0
0
X X
1
0
1
X X
1
0
X X
1
1
1
1
X X
0
0
0
X X
0
0
1 X X
0
1
0
X X
0
1
1
X X
1
0
0
X X
0
1 X X
1
1
1
0
X X
1
1
1 X X
0
0
0
X X
0
0
1
X X
0
X X
0
1
0
1
1 X X
1
0
0
X X
1
0
1
X X
1
1
0
X X
1
1
1
X X
X X X X X

Ao

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

ANALOG
CHANNEL
SELECTED
CHO
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CHB
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH1B

VTEST
No Channel Select
No Channel Select
No Channel Select
No Channel Select
Logic Test Mode·

'Analog channel Inputs CHO thru CH4 are logic outputs

2-B9

fII

ADC0819

"
o·:J2C

:J

!!.

m

0"
n
~

tCOMP

'/"
T.
TR
TS

C

i·

CONVERSION
TIMING GENERATORS

SAR

cc

i-+SAR

DJ

3
CC

Scullsl

:b0

EOC~

SAR

011251

M

~REGISTER

B-BIT 1/0

II

.&t?l II Y

T

!.BITSI!A;' T T
WEIGHTEO

---------- ------

i 14 I I

r:L'i:4J_4+1...,-L.--I-CHj'.8.~~~

mJGNO

I]JVRIF+

miVREF-

241 DO
TL/H/9287 -15

.--------------------------------------------------------------------.>
c
o<:)

Functional Description

CO

1.0 DIGITAL INTERFACE

-"

this mux address/sample cycle, data from the last conversion is also clocked out on DO. Since 07 was clocked out
on the falling edge of
only data bits 06-00 remain to be
received. The following seven falling edges of SCLK shift out
this data on DO.

The ADC0819 uses five input/output pins to implement the
serial interface. Taking chip select (CS) low enables the I/O
data lines (DO and 01) and the serial clock input (Scu2) controls the SAR during the conversion
process and must be continuously enabled.

es

The 8th SCLK falling edge initiates the beginning of the AID's
actual conversion process which takes between 26 and 32
<1>2 cycles (Td. During this time
can go high to TRISTATE DO and disable the SCLK input or it can remain low.
is held Iowa new I/O exchange will not start until the
If
conversion sequence has been completed, however once
the conversion ends serial I/O will immediately begin. Since
there is an ambiguity in the conversion time (Td synchronizshould
ing the data exchange is impossible. Therefore
go high before the 26th <1>2 clock has elasped and return low
after the 32nd <1>2 to synchronize serial communication.

es

es

1.1 CONTINUOUS SCLK
With a continuous SCLK input CS must be used to synchronize the serial data exchange (see Figure 1). The ADC0819
recognizes a valid CS one to three <1>2 clock periods after
the actual falling edge of CS. This is implemented to ensure
noise immunity of the es Signal. Any spikes on es less than
must remain low
one <1>2 clock period will be ignored.
during the complete I/O exchange which takes eight SCLK
cycles. Although es is not immediately acknowledged for
the purpose of starting a new conversion, the falling edge of
es immediately enables DO to output the MSB (07) of the
previous conversion.

es

A conversion or I/O operation can be aborted at any time by
strobing CS. If CS is high or low less than one <1>2 clock it will
be ignored by the A/D. If the CS is strobed high or low
between 1 to 3 <1>2 clocks the AID mayor may not respond.
must be strobed high or low greater than 3 <1>2
Therefore
clocks to ensure recognition. If a conversion or I/O exchange is aborted while in process the consequent data
output will be erroneous until a complete conversion sequence has been implemented..

es

es

The first SCLK riSing edge will be acknowledged after a setup time (!set-up) has elapsed from the falling edge of
This and the following seven SCLK rising edges will shift in
the channel address forthe analog multiplexer. Since there are
19 channels only five address bits are utilized. The first five
SCLK cycles clock in the mux address, during the next three
SCLK cycles the analog input is selected and sampled. During

es.

1.2 DISCONTINUOUS SCLK
Another way to accomplish synchronous serial communication is to tie es low continuously and disable SCLK after its
8th falling edge (see Figure 2). SCLK must remain low for

ANALOG VOLTAGE
ACQUISITION WINDOW
3 LSB DATA OUTPUT

SERIAL DATA
INPUT
5 MSB OUTPUT

CONVERSION PROCESS

Sm

TL1H/9287-16

FIGURE 1

CONVERSION PROCESS

SERIAL DATA

CS (LOW)

SeLK

Tc(MAX) _

INPUT
5 MSB OUTPUT

64TH 4>1

________~--------------+_--------~----------------~--~CL~OC~K~

---"'"

00 _____0_1__.l,'-.,.'-"'~~,,_03~~O_2,,~Dl~~00~

07
TLlH/9287 -17

FIGURE 2
2-91

CD

CD
.,...

r------------------------------------------------------------------------------------------,

§
c(

Functional Description (Continued)
at least 32 2 clocks to ensure that the AID has completed
its conversion. If SCLK is enabled sooner, synchronizing to
the data output on DO is not possible since an end of conversion signal from the A/D is not available and the actual
conversion time is not known. With ~ low during the conversion time (32 2 max) DO will go high or low after the
eighth falling edge of SCLK until the conversion is completed. Once the conversion is through DO will transmit the
MSB. The rest of the data will be shifted out once SCLK is
enabled as discussed previously.

eighth SCLK falling edge. The hold mode is initiated with the
start of the conversion process. An acquisition window of
3tSCLK+ 1. ""sec .is therefore avail.able to allow· the ladder
capacitance to settle to the analog input voltage. Any
change in the analog voltage bef,ore or after the acquisition
window will not effect the AID conversion result.
In the most simple case, the laclder's acquisition til1le is determined by the Ron (3K) of the multiplexer switches and the
total ladder capaCitance (90pf). These values yield an acquisition time of about 2 ""sec for a full scale reading. Therefore the analog input must be stable for at least 2 ""sec
before and 1 ""sec after the eighth SCLK falling edge to
ensure a proper conversion. External input source resistance and capacitance will lengthen the acquisition time and
should be accounted for.

If ~ goes high during the conversion sequence DO is tristated, and the result is not affected so long as CS remains
high until the end of the conversion.

1.2 MULTIPLEXER ADDRESSING
The five bit mux address is shifted, MSB first, into 01. Input
data corresponds to the channel selected as shown in table
1. Care should be taken not to send an address greater than
or equal to twenty four (11XXX) as this puls the AID in a
digital testing mode. In this mode the analog inputs CHO
thru CH4 become digital outputs, for our use in production
testing.

Other conventional sample and hold error speCifications are
included in the error and timing specs of the AID. The hold
step and gain error sample/hold specs ·are taken into account in the ADC0819's total unadjusted error, while the
hold settling time is included in the ·AlD's max conversion
time of 32 2 clock periods. The hold droop rate can be
thought of as being zero since an unlimited amount of time
can pass between a conversion and the reading of data.
However, once the data is read it is lost and another conversion is started.

2.0 ANALOG INPUT
2.1 THE INPUT SAMPLE AND HOLD
The ADC0819's sample/hold capacitor is implemented in its
capacitive ladder structure. After the channel address is received, the ladder is switched to sample the proper analog
input. This sampling mode is maintained for 1 ""sec after the

Typical Applications
ADC0819-INS8048 INTERFACE

-_

P1D
INS8D48 PI·'
Pl2

....

t

~---I~:LK

~:~

01 ADCOS1a
DO

...

~ <1>2

::)
:
NINETEEN ANALOG
:
INPUTS.

CHI8~

\

TL/H/92B7 -18

2-92

.--------------------------------------------------------------------.~

c
oo

ADC0819 FUNCTIONAL CIRCUIT
5V

....

CO

CD

5V

22

CHD
CH1
CH2

CH3
CH4

<1>2 27

CH5
2CLK

CH8
CH7

CH8
SCU(

28

CH9

~

CH1D

CHll

5V

CS

23

CH12
":"

CH13
CH14

SHIFT/LOAD
01 25

74C165

00

CH15

QK

QA

6

CH1S

14

13

12

11

CH17
CH18

5V
21
2.7k

II
CHANNEL SELECT

":"

2Cu(

TLlH192B7-19

Ordering Information
Temperature Range
Total Unadjusted
Error

I

± % LSB

I

±1 LSB

Package Outline

O"Cto +70'C
ADC0819BCN
N2BB

2·93

- 40"C to + 85'C
ADC0819BCV
ADC0819CCV

ADC0819CIN

V28A

N2BB

o

eN

;

r-----------------------~--------------------------------------------_,

I!INational Semiconductor
ADC0820 8-Bit High Speed f-LP Compatible
A/D Converter with Track/Hold Function
General Description

Features

By using a half-flash conversion technique, the 8-bit
ADC0820 CMOS AID offers a 1.5 p.s conversion time and
dissipates only 75 mW of power. The half-flash technique
consists of 32 comparators, a most significant 4-bit ADC
and a least significant 4-bit ADC.

•
•
•
•
•

The input to the ADC0820 is tracked and held by the input
sampling circuitry eliminating the need for an external sample-and-hold for signals moving at less than 100 mV I p.s.
For ease of interface to microprocessors, the ADC0820 has
been designed to appear as a memory location or 110 port
without the need for external interfacing logic.

•
•
•
•

Key Specifications
8 Bits
2.5 p.s Max (RD Mode)
1.5 p.s Max (WR-RD Mode)
• Input signals with slew rate of 100 mV/p.s converted
without external sample-and-hold to 8 bits
75 mW Max
• Low Power
± Yo LSB and ± 1 LSB
• Total Unadjusted Error
• Resolution
• Conversion Time

•
•
•
•
•
•

Built-in track-and-hold function
No miSSing codes
No external clocking
Single supply-5 VDe
Easy interface to all microprocessors, or operates
stand-alone
Latched TRI-STATEI!> output
Logic inputs and outputs meet both MOS and T2L voltage level speCifications
Operates ratiometrically or with any reference value
equal to or less than Vee
OV to 5V analog input voltage range with single 5V
supply
No zero or full-scale adjust required
Overflow output available for cascading
0.3" standard width 20-pin DIP
20-pin molded chip carrier package
20-pin small outline package
20-pin shrink small outline package (SSOP)

Connection and Functional Diagrams
Dual-In-Line, Small Outline and
SSOP Packages

va:

VIN
DBD

NC

DBI

on:

DB2

DB7

DB3

5

WR/RDY

6

MODE

"""+)

FLASH

15

DB5

A"

I.

DB.

Rii
iNi'

13

CS

9

12

GND

10

II

VREF (+)
VREF (-)

1m:

OfL

4·BIT

DB6

DB1

086
DB5
DB.

(eMSI.)
VR£fI-1

OUTPUT

LATCH
AND

4·BIT

TRI-STATE

DAC

BUFFERS

TLlH/5501-1

Top View
DB3

Molded Chip Carrier
Package

DB'

OBI
DBD

cs

NC

va:

20

12

V,N

I

II

DBO
DBI

VREF (+)
VREF (-)

MODE

D/RDY

TL/H/5501 -2

GND

FIGURE 1

iiii

See Ordering Information

TLlH/5501-33

2-94

Absolute Maximum Ratings

(Notes 1 & 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl

Lead Temp. (Soldering, 10 sec.)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 sec.)
Infrared (15 sec.)

10V

Logic Control Inputs

-0.2V to Vee +0.2V

Voltage at Other Inputs and Output

-0.2VtoVee +0.2V

Package Dissipation at TA = 25·C
Input Current at Any Pin (Note 5)'
Package Input Current (Note 5)
ESD Susceptability (Note 9)

215·C
220·C

Operating Raiings (Notes 1 & 2)

-65·Cto +150·C

Storage Temperature Range

260·C
300·C

875mW

Temperature Range
ADC0820CCJ
ADC0820CIWM
ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820CCV
ADC0820BCWM, ADC0820CCWM
ADC0820CCMSA

1 mA
4mA
1200V

TMIN05:TA05:TMAX
-40·C05:TA05: +85·C
-40·C05:TA05: +85·C
O·C 05: TA ,;;?O·C
0·C05:TA05:70·C
O·C05:TA';;?O·C
O·C 05: TA 05: 70·C
4.5Vto 8V

Vee Range

Converter Characteristics The following specifications apply for RD mode (pin 7 = 0), Vee = 5V, VREF( +) = 5V,
and VREF(-)=GND unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA=Tj=25·C.
ADC0820CCJ
Parameter

Conditions
Typ
(Note 6)

Tested
Limit
(Note 7)

Resolution
Total Unadjusted
Error
(Note 3)

Design
Limit
(Note 8)

ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820CCV
ADC0820BCWM, ADC0820CCWM
ADC0820CCMSA, ADC0820CIWM
Typ
(Note 6)

8
ADC0820BCN, BCWM
ADC0820CCJ
ADC0820CCN, CCWM, CIWM,
ADC0820CCMSA

Tested
Limit
(Note 7)

Limit
Units

Design
Limit",
(Note 8)

8

8

Bits

±1f2

±Yz

±1
±1

±1
±1

LSB
LSB
LSB
LSB

±1

Minimum Reference
Resistance

2.3

1.00

2.3

1.2

Maximum Reference
Resistance

2.3

6

2.3

5.3

6

kO

kO

Maximum VREF( + )
Input Voltage

Vee

Vee

Vee

v

Minimum VREF( -)
Input Voltage

GND

GND

GND

V

Minimum VREF( +)
Input Voltage

VREF(-)

VF\EF(-)

VREF(-)

V

Maximum VREF( - )
Input Voltage

VREF(+)

VREF(+)

VREF(+)

V

Maximum VIN Input
Voltage

Vee+ 0-1

Vee+ O•1

Vee + 0_1

V

Minimum VIN Input
Voltage

GND-0.1

GND-0.1

GND-0.1

V

3
-3

0.3
-0.3

3
-3

/LA
/LA

±%

±%

LSB

Maximum Analog
Input Leakage
Current

~=Vcc
VIN=Vee
VIN=GND

Power Supply
Sensitivity

VCC=5V±5%

± 1f1a

±%

2-95

±1f16

•

~
co

B
c

DC Electrical Characteristics The following specifications apply for VCC= 5V. unlesS otherwise specified.
Boldface limits apply from TMIN to TMAX; all other limits TA=TJ=25'C.

tl; (Figure 3b)
CL =15 pF

70

120

ns

CL =100 pF

90

150

ns

RpULLUP = 1k andCL = 15 pF

30

2·9S

ns

AC Electrical Characteristics (Continued) The following specifications apply for Vee = 5V, tr= tl= 20 ns,
VREF( +) = 5V, VREF( -) = OV and T A = 25°C unless otherwise specified.
Parameter

Conditions

Tested
Limit
(Note 7)

Typ
(Note 6)

Design
Limit
(Note 8)

Units

tlo Internal Comparison Time

Pin 7 = Vee; (Figures 3b and 4)
CL =50pF

800

1300

ns

I1H, tOH, TRI-STATE Control
(Delay from Rising Edge of RD to
Hi-ZState)

RL =lk, CL =10 pF

100

200

ns

trliITL, Delay from Rising Edge of
WR 10 Falling Edge of INT

Pin 7 = Vee, CL = 50 pF
tRO>tl; (Figure3b)
tRO  V+) the absolute value of current at that pin should be limited
to 1 rnA or less. The 4 mA package input currentlimils the number of pins that can exceed the power supply boundaries with almA current limit to four.
Note 6: Typicals are at 2S·C and represent most likely parametric norm.
Note 7: Tested limit. are guaranteed to National·. AOQL (Average Outgoing Quality Level).
Note 8: Design limils are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 9: Human body model, 100 pF diocharaged through a 1.5 kO resistor.

TRI-STATE Test Circuits and Waveforms
tlH

Yee
iili

I'H'

Yee
DATA
OUTPUT

CI

":"

":"

1=

iili

GND

lk
DATA VOH

~

OUTPUTS
TL/H/5501-3

10H

tr =20ns

tOH
Yee

Vee

RIi

DATA

T

CL

":r

-=

-=

90%
50%

10%

~
90%

TLlH/5501-4

2-97

90%

~

vec - - - - - - -

OUTPUTS
"~20 novDL

TLlH/5501-5

j"If%
50%

GND

DATA
OUTPUT

CI

',j--

10H' CL=10 pF

vee

M

/111

GND

CL = 10 pF

10%

TLlH/5501-6

•

o

C'II

!

g

Timing Diagrams

tl)

2-98

»

c
oo

Typical Performance Characteristics
Logie Input Threshold
Voltage vs Supply Voltage
~ 1.7

~

~

3,..---.---,.----.-.,..---.

-55'~STAS l'25'C

w

1.6

~

1.5

ffl
~. 1.4

~
0;
...,

1.3

......

C3

9

V

/

V
./

/

~

...,=
~

.
II:

=
I
~

1~~--~--~~--~

4.5

4.75

5.0

5.5

5.25

Accuracy vs tWR
2.0

1.0

z

0.5

i

::I

2.0

!

15 1.0
~
a:

\

::Ii
z

::I

o
400

50D

600
700
lWR (n.)

BOD

Accuracy vs VREF
[VREF=VREF (+ )-VREF (-)1

\

1.5

\

g

15 1.0

i
Z

0.5

VCC'=5V
TA=25'C

~

::I

o

i

;;

~

1.5

a:
co
a:

15 1.0

\

~
!i

lli

0.5

Vec=SV
VREF=SV
TA=2S'C
IWR=600 ns
IRD=600 ns

\

\,
~

o
300 400

500 600 700 BOD 90D
IRD (ns)

2.0 ,..---.r----.---,.----r-...,

500 600 70D
Ip

BOO

90D

(ns)

Output Current vs
Temperature
10

,..---,----.---,.----r-~

w

'"z>=
til

cI

m

-=
VREF (V)

Accuracy vs tp
2.0

til Internal Time Delay vs
Temperature

-

T

o

\

300 400

!1l
~
'"
8

--r--

0.5

~

o

9D0

2.0

•~

1.5

a:
co
a:

Vcc=5V
VREF=SV
TA=2S'C
lp =500 ns
1WR =600 ns

__...I-----L__...L----l

-100 -50
50
100 150
TA-AMBIENT TEMPERATURE ('C)

Accuracy vs tRD

Vee=5V
VREF=5V
TA =25'C
lp=SOO ns
lRD =600 ns

\

a:

S~-I...

-100 -50
0
50
100 150
TA-AMBIENT TEMPERATURE ('C)

vee-SUPPLY VOLTAGE (V).

!1.5

t----1\.,---+---t---+---/

10

....

1.2

!

11 ,..---,----.---r--r-,

1

/

,/

§:
x

Power Supply Current vs
Temperature (not including
reference ladder)

Conversion Time (RD Mode)
vs Temperature

1.5 1--4'----+--+---+--1

1.0 1--4---+--:j,dIIIl"f'--I

0.5
OL..--I...__..l..-----L__...L----l

OL---'--'---'---'----'

-100 -50
0
50
100 150
TA-AMBIENT TEMPERATURE ('C)

-100 -50
50
100
150
TA-AMBIENT TEMPERATURE ('C)
TLIH15501-11

'I LSB= VREF
·256

2-99

CI)

N

o

Description of Pin Functions
Pin Name
1
2
3
4
5
6

VIN
DBO
DBl
DB2
DB3
WR/RDY

7

Mode

8

RD

Function

Pin Name
9

Function

WR-RDMode
INT going low indicates that the conver·
sion is completed and the data result is in
the output latch. INT will go low, - 800 ns
(the preset internal time out, tl) after the
rising edge of WR (see Figure 3b); or INT
will go low after the falling edge of RD, if
RD goes low prior to the 800 ns time out
(see Figure 3a). INT is reset by the rising
edge of RD or CS (see Figures 3a and
3b).
RDMode
INT going low indicates that the conversion is completed and the data result is in
the output latch. INT is reset by the rising
edge of RD or ~ (see Figure 2).
10 GND
Ground
11 VREF(-) The bottom of resistor ladder, voltage
range: GND,,;;VREF(-),,;;VREF(+) (Note
5)
12 VREF(+) The top of resistor ladder, voltage range:
VREF(-),,;;VREF(+),,;;Vce (Note 5)
CS must be low in order for the RD or WR
13 CS
to be recognized by the converter.
TRI·STATE data output-bit 4
14 DB4
TRI·STATE data output-bit 5
15 DB5
16 DB6
TRI·STATE data output-bit 6
TRI·STATE data output-bit 7 (MSB)
17 DB7
Overflow output"'-if the analog input is
18 OFL
higher than the VREF( +), "OF[ will be low
at the end of conversion. It can be used to
cascade 2 or more devices to have more
resolution (9, 1O·bit). This output is always
active and does not go into TRI·STATE
as DBO-DB7 do.
19 NC
No connection
20 Vee
Power supply voltage

Analog input; range =GND,,;;VIN,,;;Vee
TRI·STATE data output-bit 0 (LSB)
TRI·STATE data output-bit 1
TRI·STATE data output-bit 2
TRI·STATE data output-bit 3
WR-RD Mode
WR: With ~ low, the conversion is start·
ed on the falling edge of WR. Approxi·
mately 800 ns (the preset internal time
out, tl) after the WR rising edge, the result
of the conversion will be strobed into the
output latch, provided that RD does not
occur prior to this time out (see Figures
3a and 3b).
RDMode
RDY: This is an open drain output (no in·
ternal pull·up device). RDY will go low af·
ter the falling edge of CS; RDY will go
TRI·STATE when the result of the conver·
sion is strobed into the output latch. It is
used to simplify the interface to a micro·
processor system (see Figure 2).
Mode: Mode selection input-it is inter·
nally tied to GND through a 50 /loA current
source.
RD Mode: When mode is low
WR-RD Mode: When mode is high
WR-RD Mode
With CS low, the TRI·STATE data outputs
(DBO·DB7) will be activated when RD
goes low (see Figure 4). RD can also be
used to increase the speed of the con·
verter by reading data prior to the preset
internal time out (tl, - 800 ns). If this Is
done, the data result transferred to output
latch is latched after the falling edge of
the RD (see Figures 3a and 3b).
RDMode
With CS low, the conversion will start with
RD going low, also RD will enable the
TRI·STATE data outputs at the comple·
tion of the conversion. RDY going TRI·
STATE and INT going low indicates the
completion of the conversion (see Figure

INT

2).

1.0 Functional Description
1.1- GENERAL OPERATION

The internal DAC is actually a subsection of the MS flash
converter. This is accomplished by using the same resistor
ladder for the AID as well as for generating the DAC signal.
The DAC output is actually the tap on the resistor ladder
which most closely approximates the analog input. In addi·
tion, the "sampled·data" comparators used in the ADC0820
provide the ability to compare the magnitudes of several
analog signals simultaneously, without using input summing
amplifiers. This is especially useful in the LS flash ADC,
where the signal to be converted is an analog difference.

The ADC0820 uses two 4·bit flash AID converters to make
an 8·bit measurement (Figure 1). Each flash ADC is made
up of 15 comparators which c1mpare the unknown input to
a reference ladder to get a 4·bit result. To take a full 8·bit
reading, one flash conversion is done to provide the 4 most
significant data bits (via the MS flash ADC). Driven by the 4
MSBs, an internal DAC recreates an analog approximation
of the input voltage. This analog signal is then subtracted
from the input, and the difference voltage is converted by a
second 4·bit flash ADC (the LS ADC), providing the 4 least
significant bits of the output data word.

2·100

»
c

1.0 Functional Description (Continued)
1.2 THE SAMPLED-DATA COMPARATOR

The actual circuitry used in the ADC0820 is a simple but
important expal)sion of the basic comparator described
above. By adding a second capacitor and another set of
switches to the input (Figure 6), the scheme can be expanded to make dual differential comparisons. In this circuit, the
feedback switch and one input switch on each capacitor (2
switches) are closed in the zeroing cycle. A comparison is
then made by connecting the second input on each capacitor and opening all of the other switches (S switches). The
change in voltage at the inverter's input, as a result of the
change in charge on each input capacitor, will now depend
on both input signal differences.

Each comparator in the ADC0820 consists of a CMOS inverter with a capacitively coupled input (Figure 5). Analog
switches connect the two comparator inputs to the input
capacitor (C) and also connect the inverter's input and output. This device in effect now has one differential input pair.
A comparison requires two cycles, one for zeroing the comparator, and another for making the comparison.
In the first cycle, one input switch and the inverter's feedback switch (Figure Sa) are closed. In this interval, C is
charged to the connected input (V1) less the inverter's bias
voltage (VB, approximately 1.2V). In the second cycle (Figure 5b), these two switches are opened and the other (V2)
input's switch is closed. The input capacitor now subtracts
its stored voltage from the second input and the difference
is amplified by the inverter's open loop gain. The inverter's
input (VB') becomes
C
VB-(V1-V2)-C+Cs
and the output will go high or low depending on the sign of
VB'-VB·

Vl--O--C:}C~
A

1.3 ARCHITECTURE
In the ADC0820, one bank of 15 comparators is used in
each 4-bit flash AID converter (Figure 7). The MS (most
significant) flash ADC also has one additional comparator to
detect input overrange. These two sets of comparators operate alternately, with one group in its zeroing cycle while
the other is comparing.

"-/L'~'

.--Y -r

Vo

Va

ICS

V2~

TL/H/5501-13
TLlH/5501-12

oVB'-VB = (V2-Vl)-Cc+cs

o Vo = VB
o V on C =, Vl-VB
• Cs

oVo'

= stray input

= ~ ICV2-CV1]

c+cs
oVo' is dependent on V2-Vl

node capacitor

• VB = inverter input
bias voltage

FIGURE 5b. Compare Phase
FIGURE 5a. Zeroing Phase
FIGURE 5. Sampled-Data Comparator

(Vl)

RLADDER

Z

I_t

./

-a"'"s

-A

VIM~J1
(V2)

Vo = Cl +C2+Cs [Cl(V2-Vl)+C2(V4-V3)]

-A
Vo

Z

ANAGND-/,)
(V3)
C2

s

1/2LSB~
(V4)

TUH/5501-14

FIGURE 6. ADC0820 Comparator (from MS Flash ADC)

2-101

o
o

CD
N

o

Detailed Block Diagram
(BITMS

4MSB

(BlTlS

r -______~F~~'SJH~CO~NY~----~~~Sr_--------F-~-S-HC-O-NY--------~

VIN VAEF(+)

R/32

-'1/2 LSB'VOlTAGE

. VIIEF(-)

A/,32

COMP
OUTPUT

RI16

A/16

I
I

I

A'16

eM
OUTPUTS

CL
OUTPUTS

A SWITCH CONTROL
LINES

010-017

lI2LSIYDLTAGE.L/~

GROUNo~J1p
3

/1

v,.;;..-cr

DAC OUTPUT

A

.!...o/"~

B

v,,!./A.-l'~

MS COMPARATORS
CM1-CM16

A

~

~

LS COMPARATORS
CL1-CL15

112LSBYDLTAGE!./

REF ~DDER.!./A.-l'

REF LADDER.!./J1
FIGURE 7

2-102

TUH/5501-15

r--------------------------------------------------------------------.>
C

1.0 Functional Description (Continued)

oo

When a typical conversion is started, the WR line is brought
low. At this instant the MS comparators go from zeroing to
comparison mode (Figure 8). When WR is returned high after at least 600 ns, the output from the first set of comparators (the first flash) is decoded and latched. At this point the
two 4-bit converters change modes and the LS (least significant) flash ADC enters its compare cycle. No less than 600
ns later, the RD line may be pulled low to latch the lower 4
data bits and finish the 8-bit conversion. When RD goes low,
the ,flash AIDs change state once again in preparation for
the next conversion.
Figure 8 also outlines how the converter's interface timing
relates to its analog input (VIN). In WR-RD mode, VIN is
measured while WR is low. In RD mode, sampling occurs
during the first 800 ns of RD. Because of the input connections to the ADC0820's LS and MS comparators, the converter has the ability to sample VIN at one instant (Section
2.4), despite the fact that two separate 4-bit conversions are
being done. More specifically, when WR is low the MS flash
is in compare mode (connected to VIN), and the LS flash is
in zero mode (also connected to VIN). Therefore both flash
ADCs sample VIN at the same time.

WR then RD Mode
With the MODE pin tied high, the AID will be set up for the
WR-RD mode. Here, a conversion is started with the WR
input; however, there are two options for reading the output
data which relate to interface timing. If an interrupt driven
scheme is desired, the user can wait for INT to go low before reading the conversion result (Figure /3). INT will typically go low 800 ns after WR's riSing edge. However, if a
shorter conversion time is desired, the processor need not
wait for INT and can exercise a read after only 600 ns (Figure A). If this is done, INT will immediately go low and data
will appear at the outputs.

\

1.4 DIGITAL INTERFACE
The ADC0820 has two basic interface modes which are selectE1d by strapping the MODE pin high or low.

OBO-OB7 -

-

-

-

-

-

I

~J

-~ -

-

-TL/H/5501-17

FIGURE A. WR-RD Mode (Pin 7 Is High and tRD < tl)

RDMode
With the'MODE pin grounded, the converter is set to Read
mode. In this configuration, a complete conversion is done
by pulling RD low until output data appears. An INT line is
provided which goes low at the end of the conversion as
well as a RDY output which can be used to signal a processor that the converter is busy or can also serve as a system
Transfer Acknowledge signal.

,'-_----J1

RD Mode (Pin 7 is Low)

~~~----------~I \
Jilj~'-J/
\ '---

~-----

OBO-OB7-----------{

}-

___

TL/H/5501-18

FIGURE B. WR-RD Mode (Pin 7 is High and tRD>tl)

ROY~~_ _..../

Stand-Alone
For stand-alone operation in WR-RD mode, CS and RD can
be tied low and a conversion can be started with WR. Data
will be valid approximately 800 ns following WR's rising
edge.

''-_-II
J)--------

OBO-OB7 - - - - - - - ' - - - - - - - ( " '_ _

WR-RD Mode (Pin 7 is High) Stand-Alone Operation

TL/H/5501-16

~LOW

When in RD mode, the comparator phases are internally
triggered. At the falling edge of RD, the MS flash converter
goes from zero to compare mode and the LS ADC's comparators enter their zero cycle. After 800 ns, data from the
MS flash is latched and the LS flash ADC enters compare
mode. Following another 800 ns, the lower 4 bits are recovered.

- -_ _ _ _ _ _ _ _ _ __

JiljLOW - - - - - - - - - - - - -

.Jr-

--'}----<"'__

OBO-OB7 _ _ _

TLlH/5501-19

2-103

CO
N

o

o ,--------------------------------------------------------------------------,
~
1.0 Functional Description (Continued)

g
cc

" MS COMPARATORS ZERO
TO REFERENCE LADDER.
" LS COMPARATORS FLOAT.
'

• MS COMPARATORS COMPARE
V,N TO THEIR REFERENCE
LADDER TAP, THE COMPARATOR
OUTPUTS DIGITALLY TRACK

l

I
J
1-----800 os-----I
\

VIN-Vu,OOER TAP

• LS COMPARATORS ZERO TO
V'N, THE COMPARATOR'S
INPUT CAPACITORS TRACK V,N.

" MS COMPARATOR OUTPUTS
ARE LATCHED. THE MS
DAC IS SET. THE MS
,
COMPARATOR FLOATS.
" LS COMPARATORS COMPARE
LSB SECTION OF REFERENCE
LADDER.

\ "

~:EC~::E~~~g~:UTS

BE READ.
" MS COMPARATORS RETURN
TO ZERO MODE.

TL/H/5501-20

Note: MS means most signHlcant
LS means least significant

FIGURE 8. Operating Sequence (WR-RD Mode)

OTHER INTERFACE CONSIDERATIONS

2.2 INPUT CURRENT

In order to maintain conversion accuracy, WR has a maximum width spec of 50 p.s. When the MS flash ADC's sampled-data comparators (Section 1.2) are in comparison
mode (WR is low), the input capacitors (C, Figure 6) must
hold their charge. Switch leakage and inverter bias current
can cause errors if the comparator is left in this phase for
too long.
Since the MS flash ADC enters its zeroing phase at the end
of a conversion (Section 1.3), a new conversion cannot be
started until this phase is complete. The minimum spec for
this time (tp, Figures 2, 3a, 3b, and 4) is 500 ns.

Due to the unique conversion techniques employed by the
ADC0820, the analog input behaves somewhat differently
than in conventional devices. The AID's sampled-data comparators take varying amounts of input current depending
on which cycle the conversion is in.
The equivalent input circuit of the ADC0820 is shown in
Figure 10a. When a conversion starts (WR low, WR-RD
mode), all input switches close, connecting VIN to thirty-one
1 pF capacitors. Although the two 4-bit flash circuits are not
both in their compare cycle at the same time, VIN still sees
all input capacitors at once. This is because the MS flash
converter is connected to the input during its compare interval and the LS flash is connected to the input during its
zeroing phase (Section 1.3). In other words, the LS ADC
uses VIN as its zero-phase input.

2.0 Analog Considerations
2.1 REFERENCE AND INPUT
The two VREF inputs of the ADC0820 are fully differential
and define the zero to full-scale input range of the A to D
converter. This allows the designer to easily vary the span
of the analog input since this range will be equivalent to the
voltage difference between VIN( + ) and VIN( - ). By reducing
VREF(VREF=VREF(+)-VREF(-» to less than 5V, the sensitivity of the converter can be increased (i.e., if VREF=2V
then 1 LSB=7.8 mY). The input/reference arrangement
also facilitates ratiometric operation and in many cases the
chip power supply can be used for transducer power as well
as the VREF source.
This reference flexibility lets the input span not only be varied but also offset from zero. The voltage at VREF(-) sets
the input level which produces a digital output of all zeroes.
Though VIN is not itself differential, the reference design
affords nearly differential-input capability for most measurement applications. Figure 9 shows some of the configurations that are possible.

The input capacitors must charge to the input voltage
through the on resistance of the analog switches (about 5
kO to 10 kO). In addition, about 12 pF of input stray capacitance must also be charged. For large source resistances,
the analog input can be modeled as an RC network as
shown in Figure 10b. As Rs increases, it will take longer for
the input capacitance to charge.
In RD mode, the input switches are closed for approximately
800 ns at the start of the conversion. In WR-RD mode, the
time that the switches are closed to allow this charging is
the time that WR is low. Since other factors force this time
to be at least 600 ns, input time constants of 100 ns can be
accommodated without special consideration. Typical total
input capacitance values of 45 pF allow Rs to be 1.5 kO
without lengthening WR to give VIN more time to settle.

2-104

»
c

2.0 Analog Considerations (Continued)
Power Supply as Reference

External Reference 2.5V Full·Scale
V,N 1+)

o
o
Input Not Referred to GND
V,Nlt)

V,N 1+)

IN+

V,N 1-)

o

IN+

GNO

V,N 1-)

1.2k
5V -"""',..,.......-1

Q)

N

1.2k
5V - W l o -.....~ REFI + I

5V

lM3B5·2.5

V,N 1-)

----+-1 REFI-I
c~

• c'

TUH/5501-21

"

TLlH/5501-22

-4:• Current path must

stili exist from VINI-)
to ground

TL/H/5501-23

FIGURE 9. Analog Input Options

~

12PF

l

...JIIRO"'N_-cy~1

VIN_"""RSrv-...

oJ~1
:Ii~

R'~O~~~---o>(,
15 LSB

1

:FT 1 pF

~

COMPARATORS.~

VIN-

o-f1
TOMSB~o--J ipF

-~"r.:I-~~~-rv

12~~T

HoN

32 PF-:;r

RON

R·LAOOER

TL/H/5501-25

.·T
•

1

pF

":"

16 MSB COMPARATORS

TL/H/5501-24

FIGURE 10a

FIGURE 10b

It should be made clear that transients in the analog input
signal, caused by charging current flowing into VIN, will not
degrade the AID's performance in most cases. In effect the
ADC0820 does not "look" at the input when these tran·
sients occur. The comparators' outputs are not latched
while WR is low, so at least 600 ns will be provided to
charge the ADC's input capacitance. It is therefore not necessary to filter out these transients by putting an external
cap on the VIN terminal.

Sampled-data comparators, by nature of their input switching, already accomplish this function to a large degree (Section 1.2). Although the conversion time for the ADC0820 is
1.5 ,..S, the time through which VIN must be 1/2 LSB stable
is much smaller. Since the MS flash ADC uses VIN as its
"compare" input and the LS ADC uses VIN as its "zero"
input, the ADC0820 only "samples" VIN when WR is low
(Sections 1.3 and 2.2). Even though the two flashes are not
done simultaneously, the analog signal is measured at one
instant. The value of VIN approximately 100 ns aiter the
riSing edge of WR (100 ns due to internal logic prop delay)
will be the measured value.

2.3 INPUT FILTERING

2.4 INHERENT SAMPLE·HOLD
Another benefit of the ADC0820's input mechanism is its
ability to measure a variety of high speed signals without the
help of an external sample-and-hold. In a conventional SAR
type converter, regardless of its speed, the input must remain at least % LSB stable throughout the conversion process if full accuracy is to be maintained. Consequently, for
many high speed signals, this signal must be externally
sampled, and held stationary during the conversion.

Input signals with slew rates typically below 100 mV /,..s can
be converted without error. However, because of the input
time constants, and charge injection through the opened
comparator input switches, faster signals may cause errors.
Still, the ADC0820's loss in accuracy for a given increase in
signal slope is far less than what would be witnessed in a
conventional successive approximation device. An SAR
type converter with a conversion time as fast as 1
would
still not be able to measure a 5V 1 kHz sine wave without
the aid of an external sample-and-hold. The ADC0820, with
no such help, can typically measure 5V, 7 kHz waveforms.

,..S

2-105

•

o

C'II

CO

o

o

3.0 Typical Applications
a·Bit Resolution Configuration

C

5V

-+-+--.

"
"

B8

T""

1k

"

TLlH/5501-27

Telecom AID Converter

M,ultiple Input Channels

25'
15'

ISOk

w ......t-;i::;.1:'"

cs

15V ......

13

10k

40k

VIN

Wii
5V

20 kHz '

t-_-1>--,2",0,

SAMPLE RATE

'ee

0.01

'IN

AN

Wii s

iiii 8
ADC082D

jjjjS

10 GND

SV

12

·••

Vn(+!
DBOtg.D87

ADCOB20

iNf9

Vee

12-51

NTOTALINPUT
CHANNELS

• V'N~3 kHz max ± 4Vp
• No track-and-hold needed

• Low power consumption

~13

C"'

12 Vm(+1

OBOto087

11 VREFf-koDE{U-17)

TL/H/5501-2B

'='

2·106

TL/H/5501-29

3.0 Typical Applications (Continued)
8·Blt 2·Quadrant Analog Multiplier

..nr

XIN

elK

YIN

(OV TO 5VI

400 kHz

(-10VTO +10VI

L

2

lSB

7

AGND
DGND

10

XFER 17

VREFI -)
ADC0820

lM340·5.0lAZ

14

16

15

15

16

14

17 MSB 13

YoUT=

=lY

YoUI =Y
X>:Z

22 pF

'ar

TLlH/5501-30

Fast Infinite Sample-and·Hold
1.2"s
VIN

..,

10V TO 5V)

"WIr

10 GND

r-

L..I

2

lS8 12

..':,::3_ _ _...._

15V

T

O•, • F

"

•

10

t"---.......--15V
VREFI- I
ADC0820
15V
LM340·5.0LAZ

t-_5..V.....7'1vcc

15
16

20 MODE

17

12 VREFI +)

18 MS8

5

-15V

1.82k
1%

2·107

TLlH/5501-31

ADC0820

w
b

~
"0

Digital Waveform Recorder
ATOD
COIIVERTERS

MEMORY

....

5V

V,.
MODE

DID

n

liD,

I.

»

110.

10

"0

'S!.

CLRI
CLRZ

(;'

a
0'

UVU

nDB7

::::J

en

C-

liIi, ill,

ell,

ClIII

I.
CLRIU
CLR2

Al

'10

1 1
1IVIIz

II

~

0

!!.

2A

!WI~

~

(;'

• TO 0 CONTROL LOGIC

DMI4LS393

2K x SHAM

ADC082D
ANALOU
INPUT
DV TO 5V

ADDRESS
COUNTERS

CD

1 ""'-1

pO
DM1CLS393

I

I

01

I I r=J[)o ! III !O=WR'

Ii ·
CLOCK

03

DMI4LSI64 04

~ ~- II:Itf§j~
NL

ell,
STORED
DIGm2ED
OUTPUT
OVTD -5V

~

5V

':"
5V

....

-=
5V~

•

• 1.3M samples/sec

·4kmamory

....
TRIGSER

TL/H/5501-32

g>

a

!'"

.--------------------------------------------------------------------.>
c
o
o

Ordering Information
Part Number

Package

O'Cto +70'C

±%LSB

V20A-Molded Chip
Carrier
M20B-Wide Body Small
Outline
N20A-Molded DIP
J20A-Cerdip
MSA20- Shrink Small
Outline
Package
V20A-Molded Chip
Carrier
M20B-Wide Body Small
Outline
M20B-Wide Body Small
Outline
N20A-Molded DIP

-40'Cto +B5'C
D'Cto +70'C

ADCOB20BCV
ADCDB20BCWM
ADCOB20BCN
ADCOB2!)CCJ
ADCOB20CCMSA

ADCDB20CCV
ADCOB20CCWM
ADCOB20CIWM
ADCOB20CCN

Temperature
Range

Total
Unadjusted Error

±1 LSB

CD
N

o

D'Cto +7D'C
D'Cto +70'C

D'Cto +7D'C
D'Cto +70'C
-40'Cto +B5'C
O'Cto +7D'C

fJI

2-109

ttlNational Semiconductor

ADC08311 ADC08321 ADC0834 and ADC0838
8-Bit Serial 110 AID Converters with Multiplexer Options
General Description
The ADC0831 series are 8-bit successive approximation
• Operates ratiometrically or with 5 Voc' voltage
AID converters with a serial 110 and configurable input mul- .
reference
'
tiplexers with up to 8 channels. The serial 110 is configured
• No zero or full-scale adjust required
to comply with the NSC MICROWIRETM serial data ex• 2-, 4- or 8-channel multiplexer options with address
change standard for easy interface to the COPSTM family of
logic
.
processors, and can interface with standard shift registers
• Shunt regulator allows operation with high voltage
or /JoPs.
supplies
.
The 2-, 4- or 8-channel multiplexers are software configured
• OV to 5V input range with single 5V power supply
for single-ended or differential inputs as well as channel as• Remote operation with serial digital data link
signment.
• TIL/MOS input/output compatible
The differential analog voltage input allows increasing the
• 0.3" standard width, 8-,'14- or 20-pin DIP package
common-mode rejection and offsetting the analog zero in• 20 Pin Molded Chip Carrier Package (ADC0838 only)
put voltage value. In addition, the voltage reference input
• Surface-Mount Package
can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.

Key Specifications

Features
• NSC MICROWIRE compatible-direct interface to
COPS family processors
• Easy interface to all microprocessors, or operates
"stand-alone"

•
•
•
•
•

Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time

8 Bits
±% LSB and ±1 LSB
5 Vee
15mW
32/Jos

Typical Application

MICRDWlRE
BIT STREAM

COPS
CPU

5VOC

LM335

TLlH/55B3-1

2-110

Absolute Maximum Ratings

(Notes 1 & 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Current into V + (Note 3)
15mA
Supply Voltage, Vee (Note 3)
Voltage
Logic Inputs
Analog Inputs
Input Current per Pin (Note 4)
Package
Storage Temperature

Lead Temperature (Soldering 10 sec.)
Dual-In-Line Package (Plastic)
Dual-In-Line Package (Ceramic)
Molded Chip Carrier Package
Vapor Phase (60 sec.)
Infrared (15 sec.)

6.5V

215'C
220'C

ESD Susceptibility (Note 5)

-0.3V to Vee + 0.3V
-0.3V to Vee + 0.3V
±5mA
±20mA

2000V

Operating Ratings (Notes 1 & 2)
Supply Voltage, Vee
Temperature Range
ADCOB31/BBCJ,
ADCOB3114/BCCJ.
ADCOB32BIWM.
ADCOB31/2/4/BCIWM
ADCOB31/2114/BBCN.
ADCOB38BCV.
ADC0831/2/4/8CCN.
ADCOB38CCV.
ADC0831/2/4/8CCWM

-65'Cto + 150'C

Package Dissipation
at TA = 25'C (Board Mount)

260'C
300'C

O.BW

4.5 Voe to 6.3 Voe
TMIN:>:TA:>:TMAX

-40'Cto +85'C

O'Cto +70'C

Converter and Multiplexer Electrical Characteristics
The following specifications apply for Vee = V + = VREF = 5V. VREF :>: Vee + 0.1 V. TA = Tj = 25'C. and felK = 250 kHz
unless otherwise specified. Boldface ilmlts apply from TMIN to TMAXBCJ,BIWM,
CIWM and CCJ Devices
Parameter

Conditions
Typ
(Note 12)

Tested
Limit
(Note 13)

BCV, CCV, CCWM, BCN
and CCN Devices

Design
Typ
Limit
(Note 12)
(Note 14)

Tested
Limit
(Note 13)

Design
Limit
(Note 14)

±%
±%

±%
±%

±1
±1
±1

±1
±1
±1

Units

CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted Error
ADC0838BCV
ADC0831/2/4/8BCN
ADC0831/8BCJ
ADC0832BIWM
ADC0838CCV
ADC0831/2/4/8CCN
ADC0831/2/4/8CCWM
ADC0831/4/8CCJ
ADC0831/2/4/8CIWM

VREF=5.00V
(Note 6)

LSB

±%
±%

fII

±1
±1

Minimum Reference
Input Resistance (Note 7)

3.5

1.3

3.5

1.3

1.3

kn

Maximum Reference
Input Resistance (Note 7)

3.5

5.9

3.5

5.4

5.9

kn

Maximum Common-Mode Input
Range (Note 8)

Vee +0.05

Vee +0.05 Vee + 0.05

V

Minimum Common-Mode Input
Range (Note 8)

GND -0.05

GND -0.05 GND-0.05

V

DC Common-Mode Error

±'A.

±%

2-111

±'A.

±%

±%

LSB

Converter and Multiplexer Electrical Characteristics (Continued)
The following specifications apply for Vcc = V+ = 5V, TA = Tj = 25°C, and fCLK = 250 kHz unless otherwise specified.
Boldface limits apply from TMIN to TMAX'
BCJ,BIWM,
CIWM and CCJ Devices
Parameter

Conditions
Typ
(Note 12)

BCV, CCY, CCWM, BCN
and CCN Devices

Tested
Design
Tested
Design ..
Typ
. Limit
Limit
limit
limit
(Note 12)
(Note 13) (Note 14)
(Note 13) (Note 14)

Units

CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)
Change in zero.
error from Vcc=5V
to internal zener
operation (Note 3)
Vz, internal
diode breakdown
(at V + )(Note 3)

15mAintoV+
Vcc=N.C.
VREF=5V
MIN
MAX

15 rnA into V+

1

1

1

LSB

&.3
8.5

6.3
8.5

&.3
8.5

V

Power Supply Sensitivity

Vcc=5V±5%

±%

±%

LSB

IOFF' Off Channel Leakage
Current (Note 9)

On Channel=5V,
Off Channel = OV

-0.2
-1

-0.2

-1

/LA

On Channel=OV,
Off Channel = 5V

+0.2
+1

+0:2

+1

/LA

On Channel = OV,
Off Channel = 5V

-0.2
-1

-0.2

-1

p.A

On Channel = 5V,
Off Channel = OV

+0.2
+1

+0.2

+1

p.A

ION, On Channel Leakage
Current (Note 9)

±Yte

±%

±%

±Yte

DIGITAL AND DC CHARACTERISTICS
VIN(l), Logical "1" Input
Voltage (Min)

Vcc=5.25V

2.0

2.0

. 2.0

V

VIN(O), Logical "0" Input
Voltage (Max)

Vcc=4.75V

0.8

0.8

0.8

V

IIN(l), Logical "1" Input
Current (Max)

VIN=5.0V

IIN(O), Logical "0" Input
Current (Max)

VIN=OV

VOUT(l), Logical "1" Output
Voltage (Min)

Vcc=4.75V
IOUT= -360 /LA
IOUT= -10 /LA

VOUT(O), Logical "0" Output
Voltage (Max)

Vcc=4.75V
IOUT=1.6mA

lOUT. TRI·STATE Output
Current (Max)

VOUT=OV
VOUT=5V

-0.1
0.1

-3
3

ISOURCE, Output Source
Current (Min)

VOUT=OV

-14

ISINK. Output Sink Current (Min)

VOUT=VCC

ICC. Supply Current (Max)
ADC0831, ADC0834.
ADC0838
ADC0832

Includes Ladder
Current

0.005

1

0.005

1

1

p.A

-0.005

-1

-0.005

-1

-1

/LA

2.4
4.5

2.4
4 •.5

2.4
4.5

V
V

0.4

0.4

0.4

,. V

-0.1
0.1

-3
+3

..,.3

/LA

+3

p.A

-&.5

-14

-7.5

-6.5

mA

16

8.0

16

9.0

8.0

mA

0.9

2.5

0.9

2.5

2.5

mA

2.3

&.5

2.3

6.5

6.5

mA

2·112

AC Characteristics
The following specifications apply for Vcc = 5V, tr = tf = 20 ns and 25°C unless otherwise specified.

Parameter

fCLK' Clocl< Frequency

Conditions

Typ
(Note 12)

Tested

Limit

(Note 13)

(Note 14)

10

Min
Max

tc, Conversion Time

Design

Limit

kHz
400

8

Not including MUX Addressing Time

Limit
Units

kHz
l/fcLK

Clock Duty Cycle

Min

40

(Note 10)

Max

60

%
%

250

ns

90

ns

tSET.UP, CS Falling Edge or
Data Input Valid to ClK
Rising Edge
tHOLD, Data Input Valid
after ClK Rising Edge
t p dl, tpdo-ClK Falling

CL=100pF

Edge to Output Data Valid

Data MSB First

650

1500

ns

(Note 11)

Data lSB First

250

600

ns

tl H, toH,-Rising Edge of

CL=10pF,RL=10k

125

250

ns

CS to Data Output and

(see TRI-STATE® Test Circuits)

SARSHi-Z

CL =100 pf, RL =2k

500

CIN, Capacitance of logic

ns

5

pF

5

pF

Input
COUT, Capacitance of logic
Outputs
Nole 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Nole 2: All voltages are measured with respect to the ground plugs.
Nole 3: Internal zener diodes (6.3 to 8.5V) are connected from V + to GND and Vee to GND. The zener at V + can operate as a shunt regulator and is connected
to Vee via a conventional diode. Since the zener voltage equals the AID's breakdown voltage, the diode insures that Vee will be below breakdown when the device
is powered from V +. Functionality is therefore guaranteed for V + operation even though the resultant voltage at Vee may exceed the specified Absolute Max of
6.5V. It Is recommended that a resistor be used to limit the max current into V+. (See Figure Sin Functional Description Section 6.0)
Note 4: When the input voltage (YIN) at any pin exceeds the power supply rails (VIN < V- or VIN > V+) the absolute value of current althat pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 5: Human body model, 100 pF discharged through a 1.5 kG resistor.
Note 6: Total unadjusted error includes offset, full·scale, linearity, and multiplexer errors.
Note 7: Cannot be tested for ADC0832.
Note 8: For VIN( -);;: VIN( +) the digital output code will be 0000 0000. Two on,chip diodes are tied to each analog input (see Block Diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater then the Vee supply. Be careful, during testing at low Vee levels (4.5V),
as high level analog inputs (5V) can cause this input diode to conduct-especially at elevated temperatures, and cause errors for analog Inputs near full·scale. The
spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50 mY, the
output code will be correct. To achieve an absolute 0 Vee to 5 Vee input voltage range will therefore require a minimum supply voltage of 4.950 Vee over

temperature variations, initial tolerance and loading.
Note 9: Leakage current is measured with the clock not switching.
Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case thai an available clock has a duty cycle oulside of
these limits, Ihe minimum, limelhe clock is high or the minimum time the clock is low musl be at least 1 "s. The maximum lime the clock can be high is 60 "s. The
clock can be stopped when low so long as the analog input voltage remains stable.
Note 11: Since data, MSB firsl, is the outpul of the comparator used in Ihe successive approximation loop, an additional delay is built in (see Block Diagram) to

allow for comparator response time.
Note 12: Typicals are al 25"C and represenl mosllikely parametriC norm.
Note 13: Tested limits are guaranteed to Nalional's AOQL (Average OutgOing Quality Level).
Note 14: Guaranleed but not 100% production lested. These limits are not used to calculate outgoing quality levels.

2-113

Typical Performance Characteristics

1.

Ix

Unadjusted Offset Error
vs VREF Voltage

14

.

~I! 12
II

~ :

I,
15

I

§' 1.25

r-

~
l-

lD

;;; 1.0

Ii!
15

I-

~

!z

I-

::::I 0.25

l-

2

I-

D
D.D1

0.75

~

D.l

0.5

I

~ 0.25 I--+-+-+-~='-I

I

'-

VREF= 5.DV

lcuc=250 kHz

o

OL-~--~~--~~

-100 -50

023

I.D

.--=r-"'T'"-"""""""'---'

~

JCC=5J
(250 kHz)
TA=25"C

~

I-

I
4

0.50

1.5

'IIN(+)= VIIII-)=DV
~.:=2.1II¥.

A = 2&"C

Linearity Error vs
Temperature

Linearity Error vs VREF
Voltage

¥lIEF (Yae)

VaEF (V)

0

50

100' 15D

TEMPERATURE ('C)
TL/H/5583-2

Linearity Error vs fCLK

3.0

§'

1.5

Y1IEF=5V
Vcc=5V

2.5

i
125'c

11.0

;;; 2.0

!!

III

1.5

E

I

il.O

-WC

,D.5

iii

I L

I

25'C

D

Power Supply Current vs
Temperature (ADCOS3S,
1'...;.A'D
DC
r"A;;.,
r'-0,-!S...;.3-f
T...;.CO.,..S...;.3T'4)'-T-..,

10 100 2DO 30D 40D 50D
Icuc (kHz)

&OD

D.5

1-+-+-+-+--+--+--+---1

Output Current vs
Temperature

25....--:r----r---r---r----,

i

2D

1

15

B
i

10

~-J::~~~~--.J
IsoURCE Vac = 2.4V

iii 5~E~E:1a

0'--'--..............."'--"'--........

0'----"'"--'----"---'--......

-75-50-25 0

-100 -50

25 50 75 100 125

0

50

1111

125

TEMPERATURE ('C)

mlPEllATURE ('C)
Note: For ADC0832 add IREF.

TLlH/5583-40

Power Supply Current

vsfCLK

1~r-.......,-~--r--~--'

Leakage Current Test Circuit

Ycc1sy .~"C

---

IV
ADCDl3X

1.0 I--r-:::::!::::+;~;;;;;;;j

CH A ION CHANNELl

O~r-~---+---r--~--1

CHANNEL
VDLTAGE
SELECT

TLlH/5583-29

.. .------------1:::}
+_________ _:

DFF
CHANNELS

.. _-------I

TLlH/5583-3

2-114

)l-

e(")

TRI-STATE Test Circuits and Waveforms

o

...);
CD
Co)

Vee

1----.. .

e

(")

Vee

o

CD

-o~~i~UT
DO AND :::
SARS OUTPUTS
GNO

Co)

~~lH
~

N
.....
)le
(")

o

-------=:::.

CD
Co)

.....
"")le
(")

tOH
tOH
Vee

o

Vee

CD
Co)

CD

DATA
OUTPUT

OH

OUANO Vee

~

SARS OUTPUTS

-111%

VOL

TUH/55B3-4

TUH/55B3-23

Timing Diagrams
Data Input Timing

Data Output Timing

elK

DATA
OUT 100)

TL/H/5583-24

TL/H/5583-25

ADC0831 Start Conversion Timing
CLK

DO----"""'\l
BIT 7
(MSB)

2-115

BITS
TUH/55B3-26

Timing Diagrams (Continued)
ADC0831 Timing
10

11

TLlH/5583-27
'LSB first output not available on ADC0831.

ADC0832 Timing
I:I.IICKICUCI

CHIP SELECT iCSl

IlATAIN IDiI

DATA OUT (OOI-~==--I

TLlH/5583-28

ADC0834 Timing

DATAII

DATADUTCIlll)------""'"'i

TL/H/5583-5

2·116

-I

3'

S'

eg

c

ADC0838 Timing

iii'

eg

Dl
3

CLOCK (CLK)

til

oo
::J

5'
c

CHIP SELECT (n)

CD

.eo
OOAIN(OI)

SAIl STATUS (SARS)

~
~

.....

ft="O"
OATAOUT(OO) - - - -__

= __----1

TOEr 00-----------;
lE

OUTPUT

11(+,_ _

7

(MSB)

7
(MSB)

MUX
TLlH/5583-6
, Make sure clock edge # 18 clocks in the LSB before SE is taken low

9C90~a" IPC90~a" IC;C90~a" H C90~a"

II

ADC0831!ADC0832!ADC0834!ADC0838
oz
o~

0 ..

~:-:" en
Gl" 0
zo
3
"
co

~~::

t

t

T

t

0

5·81T SHIFT RECISTER

-

fn ~ ~
Qg ~

START

~~ ~
~~

g

:l ii' re.

oID -g5'

ci 9:

I

SGLlDIF

MUX
ADDRESS

ffi:::r@

VCC

a

DO

Q~ :;::::;:

..... :::1

_. '0

=r

~~ ~
[m ~

CHO"

~
~

Q)

.....

CH 2"

-::.;

CH3"

tA

<;-1.~......:...:~..JL

CH 7'

<;-I.-::-......:...:~..JL

[

COM'..,.._ _ _

0"

'..:"
g

VREF
VCC

~
l"

Q

C

oo

Connection Diagrams

CI)

w
......
......

ADC0838 8-Channel MUX

ADC0834 4-Channel MUX

Small Outline/Dual-ln-Llne Package (J, M and N)

Small Outllne/Dual-ln-Llne Package (J, M, ant1 N)

CHO

20

Vee

l>
C

oo

CI)

v+

w

Vee

CHI

2

19

v+

Cs

CH2

3

18

Cs

CHO

ClK

~
......

01

l>
C

CH3

4

17

01

CHI

SARS

o
o

CH4

5

16

ClK

CH2

DO

w

CH5

6

15

SARS

CH3

VREF

CH6

7

14

DO

OGNO

AGNO

CH7

8

13

Sf

~
C
o
o

COM

9

12

VREr
AGNO

DGNO

10

11

CI)
~

TL/H/55B3-30

COM internally connected to A GND
TLlH/55B3-B

Top View

ADC0832 2-Channel MUX

ADC0832 2-Channel MUX

Dual-In-Une Package (J and N)

Small Outline Package (M)

CS08

Vee (VREF)

CHO

2

7

ClK

CHI

3

6

DO

GN04

ADC0831 Single
Differential Input
Dual-In-Line Package (J and N)

Cs

VIN(~02~ ~~

Vee (VREF)

NC

NC

.CHO

3

12

ClK

NC

4

11

NC

VIN (-)

3

6

DO

DO

GNO

4

5

VREF

501

CHI

5

NC

6

GNO

7

TL/H/55B3-31

Top View

10

NC
8

TLlH/55B3-32

01

Top View

COM internally connected to GND.
VREF internally connected to Vee-

TL/H/55B3-41

Top View

ADC0831 Single Differential Input

ADC0838 8-Channel MUX

Small Outline Package (M)

Molded Chip Carrier (PCC) Package (V)

CS

I~

is

d~

8

14

Vee

NC

2

13

NC

VIN(+)

3

12

ClK

v+

NC

4

11

NC

vee

VIN(-)

5

10

00

CHO

NC

6

9

NC

CHI

DGNO

GNO

7

8

VREF

CH2

COM

Sf
20

12
11

..,

TL/H/5583-42

Top View

is

...
:I:
(,.)

It)

CD

VREF
AGNO

...

is is is
TLlH/5BB3-33

2-119

CI)

w

CI)

Top View

~

8
c
c(

~

CO)

CD

C)

g
~
N
CO)

CD

C)

g

c(

.CO)CD

C)

U

C

c(

Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of these converters utilizes a sample-data comparator structure which provides for a differential analog input to be converted by a successive approximation routine.
The actual voltage converted is always the difference between an assigned" +" input terminal and a .. -" input terminal. The polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive. If the assigned" +" input is less than the
.. -" input the converter responds with an all zeros output
code.
A unique input multiplexing scheme has been utilized to provide multiple analog' channels with software-configurable
single-ended, differential, or a new pseudo-differential option which will convert the difference between the voltage at
any analog input and a common terminal. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.
A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differen-

tial. In the differential case, it also assigns the polarity of the
channels. Differential inputs are' restricted to adjacent channel pairs. For example char:lI:Jel.O and channel 1 may be
selected 'as a different pair but channel 0 or 1 cannot act
differentially with any other channel. In addition to selecting
differential mode the 'sign may also be selected. Channel 0
may be selected as the positive input:and .channel 1 as the
negative input or vice versa. This programmability is best
illustrated by the MUX addressing codes shown in the following tables for the various product options.
The MUX address is shifted into the coiwerter via the 01
line. Because the ADC0831 contains only one differential
input channel with a fixed polarity assignment, it does not
require addressing.
The common input line on the ADC0838 can be used as a
pseudo-differential input. In this mode, the voltage on this
pin is treated as the .. -" input for any ol'the other input
channels. This voltage does not have to be analog ground;
it can be any reference potential which is common to all of
the inputs. This feature is'most useful in single-supply application where the analog circuitry may be biased up to a
potential other than ground and the output signals are all
,referred to this potential.

TABLE I. Multiplexer/Package Options
Part
Number

Number of Analog Channels

Number of

Single-Ended

Differential

Package Pins

ADC0831

1

1

8

ADC0832

2

1

8

ADC0834

4

2

14

ADC0838

8

4

20

2-120

r--------------------------------------------------------------------.~

C

oQ

Functional Description

(Continued)
TABLE II. MUX Addressing: ADC0838
Single-Ended MUX Mode
MUXAddress

~

Analog Single-Ended Channel #

SGLI
DIF

0001

1

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

SELECT

1

SIGN

co

W
.....
.....

1

0

0

2

3

4

5

6

7

-

+

0

~co

COM

+

W

N
.....

~

C

-

+
+
+

oQ

co

W
,;.

~

-

+
+

C

~

-

+

w
co

Differential MUX Mode
MUXAddress
SGLI
DIF

0001

0

Analog Differential Channel-Pair #

SELECT

SIGN

1

0

1

0

0

1

0

0

0

+

-

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

-

2

2

3

+

-

MUXAddress

0001
SIGN

5

+

-

6

7

+

-

-

+

+
-

+
-

TABLE III. MUX Addressing: ADC0834
Single-Ended MUX Mode

SGLI
DIF

3

4

+

TABLE IV. MUX Addressing:
ADC0832

Channel #

Single-Ended MUX Mode

SELECT

1

1

0

0

1

0

1

1

1

0

1

1

1

0

1

2

3

+
+
+

MUXAddress
SGLI
DIF

0001

1

0

1

1

+

SIGN

Channel #
0

1

+
+

COM is internally tied to A GND

COM is internally tied to A GND

Differential MUX Mode
Differential MUX Mode

MUXAddress

MUXAddress

Channel #

SGLI
DIF

0001

0

0

0

0

0

1

0

1

0

0

1

1

SIGN

SGLI
DIF

SELECT

1

0

1

+

-

-

2

3

+

-

-

+

+

2-121

0001
SIGN

Channel #
0

1

0

0

+

-

0

1

-

+

CD

('I)

r-----~--------------------------------------------------------------------------,

CD

o

~

I
c

~
....

B
c
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Functional Description (Continued)
Since the input configuration is under software control, it
can be modified, as required, at each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion. Figure 1 illustrates the input flexibility which can be achieved.
The analog input voltages for each channel can range from
50 mV below ground to 50 mV above Vee (typically 5V)
without degrading conversion accuracy.

To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate diagram is shown of each device.
1. A conversion is initiated by first pulling the ~ (chip select) -line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its
MUX assignment word.
2. A clock is then generated by the processor (if not provided continuously) and output to the AID clock input.
3. On each rising edge of the clock the status of the data in
(01) line is clocked into the MUX address shift register. The
start bit is the first logic "1" that appears on this line (all
leading zeros are ignored). Following the start bit the converter expects the next 2 to 4 bits to be the MUX assignmentword.

2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system improvements; it allows more function to be included in the
converter package with no increase in package size and it
can eliminate the transmission of low level analog signals by
locating the converter right at the analog sensor; transmitting highly noise immune digital data back to the host processor.
8 Single-Ended

8 Pseudo-Differential

+
+

+
VSIAS-=-

J.

Mixed Mode

4 Differential

0.1
2,3
4.5
6.7

-(+1

VSIAS-=-

~

FIGURE 1. Analog Input Multiplexer Options for the ADC0838

2-122

TL/H/55B3-9

»
c

Functional Description

(Continued)
4. When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of 1fz clock
period (where nothing happens) is automatically inserted to
allow the selected MUX channel to settle. The SAR status
line goes high at this time to signal that a conversion is now
in progress and the DI line is disabled (it no longer accepts
data).

The DI and DO lines can be tied together and. controlled
through a bidirectional processor 110 bit with one wire. This
is possible because the DI input is only "looked-at" during
the MUX addressing interval while the DO line is still in a
high impedance .state.
. .
3.0 REFERENCE CONSIDERATIONS
The voltage applied to the reference input to these converters defines the voltage span of the analog input (the difference between VIN(MAX) and VIN(MIN)) over which the 256
possible output codes apply. The devices can be used in
either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a
voltage source capable of driving the reference input resistance of typically 3.5 kfi. This pin is the top of a resistor
divider string used for the successive approximation conversion.
In a ratiometric system, the analog input voltage is proportional to the voltage used for the ·AlD reference. This voltage is typically the system power supply, so the VREF pin
can be tied to Vee (done internally on the ADC0832). This
technique relaxes the stability requirements of the system
reference as the analog input and AID reference move together maintaining the same output code for a given input
condition.
For absolute accuracy, where the analog input varies between very specific voltage limits .. the reference pin can be
biased with a time and temperature stable voltage source.
The LM385 and LM336 reference diodes are good low current devices to use with these converters.

5. The data out (DO) line now comes out of TRI-STATE and
provides a leading zero for this one clock period of MUX
settling time.
6. When the conversion begins, the output of the SAR comparator, which indicates whether the analog input is greater
than (high) or less than (low) each successive voltage from
the internal resistor ladder, appears at the DO line on each
falling edge of the clock. This data is the result of the conversion being shifted out (with the MSB coming first) and
can be read by the processor immediately.
7. After 8 clock periods the conversion is completed. The
SAR status line returns low to indicate this 1fz clock cycle
later.
8. If the programmer prefers, the data can be provided in an
LSB first format [this makes use of the shift enable (SE)
control linel. All 8 bits of the result are stored in an output
shift register. On devices which do not include the SE control line, the data, LSB first, is automatically shifted out the
DO line, after the MSB first data stream. The DO line then
goes low and stays low until CS is returned high. On the
ADC0838 the SE line is brought out and if held high, the
value of the LSB remains valid on the DO line. When SE is
forced low, the data is then clocked out LSB first. The
ADC0831 is an exception in that its data is only output in
MSB first format.

The maximum value of the reference is limited to the Vee
supply voltage: The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals VREFI
256).

9. All internal registers are.cleared when the CS line is high.
If another conversion is desired, ~ must make a high to
low transition followed by address information.

...--------'1.P"----'-......

. . . - - - - -....- - -.... 5V

Vee

5V

vee
20k
TRANSDUCER

~+--

+

ADCD834

VREF

I-_D;.,;V..;-1,.;;.2_5V__-t+

t-

ADCD832

r-

VREFt--- 1.25V

'j ~LM385
GND

GND

1

TL/H/5583-10

a) Ratlometric

b) Absolute with a Reduced Span
FIGURE 2. Reference Examples

2-123

n
o

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....
......
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n
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N

......

c»

n
o

co
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~

......

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o

co
Co)
co

EI

Functional Description

(Continued)

4.0 THE ANALOG INPUTS

5.2 Full-Scale

The most important feature of these converters is that they
can be located right at the analog signal sour~e an~ through
just a few wires can communicate with a controlling processorwith a highly noise immuneserjal bit stream. ThiS in itself
greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise. pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage. .

The full-scale adjustment can be made by applying a differential input voltage which is 1 % LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the VREF input (or Vcc for the ADC0832) for a
digital output code which is just changing from 1111 1110 to
11111111.
.
5.3 AdjustIng for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A VIN (+) voltage which
equals this desired zero reference plus % LSB (where the
LSB is calculated for the desired analog span, using
1 LSB = Ilnalog span/256) is applied to selected" +" input
and the zero reference voltage at the corresponding .. - "
input should then be adjusted to just obtain the OOHEX to
01 HEX code transition .
The full-scale adjustment should be made [with the proper
VIN(:-) voltage applied] by forcing a voltage to the VIN(+)
input which is given by: .

The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected" +" and" -" inputs for a conversion (60
Hz is most typical). The time interval between sampling ·the
.. +" input and then the .. -" input is % of a clock period.
The change in the conimon-modevoltage during this short
time interval can cause conversion errors. For a sinusoidal
common-mode signal this error is:
0.5 )
. Verror(max)= VPEAK(2mCM) ( fClK
where fCM is the frequency of ttie common-mode signal,
VPEAK is its peak voltage v.alue
and fClK, is the AID clock frequency.
For a 60 Hz common-mode signal to generate a % LSB
error (::::: 5 mY) with the convfJiter running at 250 kHz, its
peak value would have to be 6.63V which would be larger
than allowed as it exceeds the maximum analo,! input limits.

.
[ (VMAX-VMIN) ]
VIN(+)fsadJ=VMAX-1.5
256
where:
VMAX = the high end of the an~log input range
and

Due to the sampling nature of the analog inputs short spikes
of current enter the" +" input and exit the" -" input at the
clock edges during the actual conversion. These currents
decay rapidly and do not cause errors as the internal'cpmparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents and cause
an effective DC current to flow through the output resistance of the analog Signal source. Bypass capacitors shouid
not be used if the source resistance is greater than 1 ~O.

. VMIN = the low end (the offset zero) of the analog
range.
(Both are ground referenced.)
The VREF (or Vce> voltage is then adjusted to provide a
code change from FEHEX to FFHEX. This completes the adjustment procedure.
6.0 POWER SUPPLY
A unique feature of the ADC0838 and ADC0834 is the inclusion of a zener diode connected from the V+ terminal to
ground which also connects to the VCC terminal (which is
the actual converter supply) through a silicon diode, as
shown in Figure 3. (See ,Note 3)

This source resistance limitation is important with regard to
the DC leakage currents of input multiplexer as well. The
worst-case leakage curr.ent pf Of: 1 p.A over temperature will
create a 1 mV input error with a 1 kO source resistance. An
op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance
Signal source be required.

Vs

5.0 OPTIONAL ADJUSTMENTS

R V+

..

10...1

5.1 Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not gro~nd
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any VIN (-) input at this VIN(MIN) value. This
utilizes the differential mode operation of the AID.

Vee
ACTUAL
CONVERTER
SUPPlY

~ t7V

GNO

The zero error of the AID coriverter relates· to the .Iocation
of the first riser of the transfer function and can be measured by grounding the VIN( -) input and applying a small
magnitude positive voltage to the VIN( + ) input. Zero error Is
the difference between the actual DC input voltage which is
necessary to just cause an output digila!' code transition
from 0000 0000 to 0000 0001 and the Ideal % LSB value
(% LSB=9.8 mV for VREF=5.000 Voc).

TL/H/5583-11

FIGURE 3. An On-Chip Shunt Regulator Diode

2·124

»
c

Functional Description (Continued)
This zener is intended for use as a shunt voltage regulator
to eliminate the need for any additional regulating components. This is most desirable if the converter is to be remotely located from the system power source. Figures 4
and 5 illustrate two useful applications of this on-board zener when an external transistor can be afforded.
An important use of the interconnecting diode between V +
and Vee is shown in Figures 6 and 7. Here, this diode is
used as a rectifier to allow the Vee supply for the converter

to be derived from the clock. The low current requirements
of the AID and the relatively high clock frequencies used
(typically in the range of 10k-400 kHz) allows using the
small value filter capacitor shown to keep the ripple on the
Vee line to well under % of an LSB. The shunt zener regulator can also be used in this mode. This requires a clock
voltage swing which is in excess of Vz. A current limit for the
zener is needed, either built into the clock generator or a
resistor can be used from the CLK pin to the V + pin.

co

.....
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.......

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.......

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Applications

01:00
.......

12V
lk
SYSTEM -WIr-......---\·
SUPPLY

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12V
. - - -.....-SYSTEM
SUPPLY

ADCD834

:;.---........- -...............-I-Vcc

(")

o

co
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co

V+ 7V

6.4

Vec 6.4

AOCUB3B

T

O1
.

CMOS
OR
NMOS
CIRCUITS

TL/H/5583-12

ANALOG
CIRCUITS

GNO

FIGURE 4. Operating with a Temperature
Compensated Reference

TLlH/5583-34

FIGURE 5. Using the AID as
the System Supply Regulator

.,.

......

f'--oP

Vee
F

TRANSDUCER

ADCD838

100 MHz
CLOCK

5.3~Jl.f ...

oo

Ik
ClK
3.9k

--

GND

~
-

.

Nate: 4.SV ;;

vee;;

6.3V

TLlH/5583-36

TLlH/5583-35

FIGURE 7. Remote SensingClock and Power on 1 Wire

FIGURE 6. Generating Vee from the Converter Clock

2·125

~ r-----------------------------------------------------------------------------~
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Applications (Continued)
Digital Link and Sample Controlling Software for the
Serially Oriented COP420 and the Bit Programmable 110 INS8048

c

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c

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c....

CHO

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•

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C
....
'"

•

SK

•

Q

ADC0838

P12

•

COP420

•

ADC0838

INS8048

•

•

C")
~

P1a

•

•
CH7

CH7

Q

o

C

c

TUH/5583-13

COP CODING EXAMPLE
Mnemonic
LEI
SC
OGI
CLRA
AISC1
XAS
LDD
NOP
XAS

8048 CODING EXAMPLE

Instruction
ENABLES SIO's INPUT AND OUTPUT
C=1
GO=O(CS=O)
CLEARS ACCUMULATOR
LOADS ACCUMULATOR WITH 1
EXCHANGES SIO WITH ACCUMULATOR
AND STARTS SK CLOCK
LOADS MUX ADDRESS FROM RAM
INTO ACCUMULATOR

Mnemonic
P1, #OF7H
ANL
MOV B, #5
MOV A,#ADDR
LOOP 1: RRC A
JC
ONE

'Instruction
;SELECT Alb (cs= 0)
;BIT COUNTER - 5
;A - MUX ADDRESS
;CY - ADDRESS BIT
;TESTBIT
;BIT=O
P1, #OFEH ;01-0
ZERO:
ANL
JMP CONT
;CONTINUE
;BIT=1 '
ONE:
ORL P1, #1
;01-1
;PULSE SK 0 -+ 1 -+ 0
CONT:
CALL PULSE
DJNZ B, LOOP 1 ;CONTINUE UNTIL DONE
;EXTRA CLOCK FOR SYNC
CALL PULSE
MOV B,#8
;BIT COUNTER - 8
LOOP 2: CALL PULSE
;PULSE SK 0 -+ 1 -+ 0
IN
A,P1
;CY-DO
RRC A
RRC A
MOV A,C
;A-RESULT
RLC A
;A(O) - BIT AND SHIFT
;C-RESULT
MOV C,A
DJNZ B, LOOP 2 ;CONTINUE UNTIL DONE
RETR
;PULSE SUBROUTINE
PULSE: ORL P1, #04
;SK-1
NOP
;DELAY
P1, #OFBH ;SK-O
ANL
RET
START:

LOADS MUX ADDRESS FROM
ACCUMULATOR TO SIO REGISTER

t
8 INSTRUCTIONS

J.
XAS
XIS
CLRA
RC
XAS
XIS
OGI
LEI

READS HIGH ORDER NIBBLE (4 BITS)
INTO ACCUMULATOR
PUTS HIGH ORDER NIBBLE INTO RAM
CLEARS ACCUMULATOR
C=O
READS LOW ORDER NIBBLE INTO
ACCUMULATOR AND STOPS SK
PUTS LOW ORDER NIBBLE INTO RAM
GO=1 (CS=1)
DISABLES SIO's INPUT AND OUTPUT

2-126

l>

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Applications (Continued)

oo

CD

A "Stand-Alone" Hook-Up for ADC0838 Evaluation

Co)

.....
......

MUX ADDRESS

-;::==::;:===t===:::;===t--o

l>

Hac

C

oo

_START liT

S1k141

CD

SQuDiF

Co)

N

......

1, 1, 1, 1,

s

1Z

11

13

15

14
PARALLEL INPUTS

l>
C

oo

3

NO

CD

Co)
INPUT SHIFT REGISTER
741:115

NO

~
C

"

o
o

5Voc

CD

Co)

CD

iVac

OUTPUT SHIFT REGISTER

74C164

D.
t2

II

"
NSLSDZ1(.'

S

III leC74

LM-'.--~~--~----·D'-T-'-DI-»~l.~y--~~--~----~u~.O&vac
'Pinouts shown for ADC0838.
For all other products tie to

pin functions as shown.

Low-Cost Remote Temperature Sensor
Vee

(5Vocl

Vee

lM33.

1-.......,.+-..

T'Df.'f
":'

ADcanl

VREF

"k
t-____..:~~~MAX
TLlH/55B3-14

2-127

~

8
c
~
('I)

co

g

Applications

(Continued)

Digitizing a Current Flow
V

0.1

_

ILOAD

(2A FULL·SCALEI

I&VD~~ o-.....'"'"""Mr--t-----;;;...=;.....-....;:;.;.;.:;==:......---------,
1110

~

Vee

1-----""------,

11M
+

('I)

2401

co
o

g

C
0

Applications (Continued)

CI
CD

....
......
(0)

Span Adjust: OV"; VIN"; 3V

l>
C
0

Vee
!5Voel

CI
CD

(0)
i\)

"-

VIN!+I

l>
C
0

vee

+

':J;

VIN

CI
CD

10.F
2lI

(0)

.co.
"l>
C

AoeDl31

0

CI
CD

lk
VINI-!

(0)

VREF

CD

'::'

LM336

'::'

Zero·Shlft and Span Adjust: 2V,,; VIN"; 5V
vee
!5Voel

r--<>--f VIN!+I

Vee

1--1""'--------.. . .

•

1.Zk

----,I

AoeOl31

r--:-=::-+--I

I

I
I

LM336

SETS ZERO

CODE VOLTAGE

Uk

330

I
I
_J

Ii
Z Vue
ZERO AOJ

TL/H/55B3-16

2-129

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I
cc(

......
N
CO)

~
......

-B
cC

. ,'"

Applications (Continued)
Obtaining Higher Resolution

Vcc-4_-'+-----....-------.....,
VIN

+
>2.5V

-

·:.1 ~
+

3R

R

ADC0838

VREF

VREF

ADC0832

CO)

R

~

TL/H/5583-17

Controller performs a routine to determine which input polarity (9-bit example) or which channel pair (10-bH example) provides a non-zero output code.
ThIs information provides the extra bHs.

b)10-Blt AID

a) 9-Blt AID
Protecting the Input
Vee
ISvDel

vee

>...J\N.II""'4~WVINI+1

ADCD132

Diodes ara 1N914
TUH/5583-18

2-130

~

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CD
....

Applications (Continued)

W

High Accuracy Comparators
5V

~

Vee

oQ

C

Vntl
SYSTEM
TEST
POINTS

+

CD
W

}

:}

>----I~

)

~C
g

TO
CDNTROLLER

CD
W

"'"
~

ADCf1838

C

g

COM

CD
W
CD

GND
DO = allIs if +VIN > -VIN
DO = all Os If +VIN < -VIN
TLlH/5583-38

Digital Load Cell
330

TLlH/5583-19

•
•
•
•

Uses one more wire than load cell Itself
Two mini-DIPs could be mounted Inside loed cell for digital output transducer
Electronic offset and galn trims relax mechanical specs for gauge factor and offset
Low level cell output is converted immediately for high noise immunity

2-131

Applications (Continued)
4 mA-20 mA Current Loop Converter
lOOk

10pF
INP
24k

6.2k

200k r----:Vcc:~--.,

+IN

~-+-+--1-1N

Vee

C04024

CLK

ClI---"'-WIr-..,

A0C1I831

6Nl39
0P70 COUPLER
10k

5k~-+--1Vw

47k

Uk

!...............

OOI--.:1H,..-li'"-""""'- Vee

300k'

. . .-----Vo
.....------ONO
""-----V+

-4--------1
• All power supplied by loop
• 1500V isolation at output "

TLlH/5583-20

'

Isolated Data Converter
lN4148

J
6V

lN4148
':'

CLK

470

cs
Vee
lOOk

AOC0838

01

Vee
DO

Uk
':'

• No power required remotely
• 1500V Isolation
TLlH/5583-39

2-132

»

'0

Two Wire Interface for 8 Channels

"2-

~

o·

0.1 pF

~

15'"

10V
lk

~
c:

18k

:::>

Ve

.s

-:!:

18k
":'

Vee
lk

10k> lOOk

10V

r"

LM393
DUAL CDMP.

lN4148

":'

68k

~

LM393
DUAL COMPo

*

c.>
c.>
10k

~100k

=-T
DI

":'

lN4148

00

ClK
Vee

":' T560PF

ADC0838

22D
V' ~Ve

+

tl00PF.

Vee ~-

•I

Vee

r O . 1PF

TO.

-,
33k

hF
":'

• No additional connections

• CS derived from extended high on ClK line> 100 pO n..n.r--uuu• Timing arranged for 40 kHz, could be changed up or down by component change
• 10% ClK frequency change without component change OK

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:!;

!
I

~

OEoooavItEOOoaV IC;EOOOaV I ~ EOOOaV

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Applications (Continued)
Two Wire 1-Channellnterface

~
"II'
C)

g
~

lk

12V

C")

=
CLK
AND

27k

.c

.---H.,)2N2222

'V~2H2'1ff1 ; 18k

C S - 12rV

18k

L-

47k

V-w_t-Wlo-.

N

C")

8
c

10k

1I2LM393

~
....
C")

8
c
c

Vcc"LM393

':' DUAL COMPARATOR

~~5.1V
"=='

• Simpler vorslon of khannol

• Os dorlved from long elK pulse
TLIH/55B3-22

Ordering Information
Part Number

Analog Input
Channels

ADC0831BCJ
ADC0831BCN
ADC0831CCJ.
ADC0831CCN
ADC0831CIWM
ADC0831 CCWM

Package

Temperature
Range

±%

Hermetic (J)
Molded(N)

-40·Cto +85·C
O·Cto +70·C

Hermetic (J)
Molded(N)
80(M)
80(M)

-40"Cto +85·C
O·Ctc +70"C
- 40·C to + 85·C
O·Cto +70·C

:1:'%

80(M)
Molded (N)

- 4O·C to + 85·C
O·Cto +70·C

±1

80(M)
Molded(N)
80(M)

-40·Cto +85·C
O·Cto +70·C
O·Cto +70·C

±1

ADC0832BIWM
ADC0832BCN
ADC0832CIWM
ADC0832CCN
ADC0832CCWM

Total
Unadjusted Error

2

2-134

~

C

Ordering Information (Continued)
Analog Input
Channels

Part Number
ADCOB34BCN
ADCOB34CCJ
ADC0834CCN
ADCOB34CCWM
ADCOB34CIWM

4

ADCOB3BBCJ
ADCOB3BBCV
ADCOB38BCN

o
o
Total
Unadjusted Error

Package

Temperature
Range

±%

Molded (N)

O·Cto +70·C

±1

Hermetic(J)
Molded(N)
SO(M)
SO(M)

-40·Cto + 85·C
O·Cto +70·C
O·Cto +70·C
-40·Cto +B5·C

Hermetic (J)
PCC(V)
Molded(N)

-40·Cto +B5·C
O·Cto +70·C
O·Cto +70·C

Hermetic (J)
PCC(V)
Molded(N)
SO(M)
SO(M)

-40·Cto +B5·C
O·Cto +70·C
O·Cto +70·C
-40·Cto +B5·C
O·Cto +70"C

±%

ADCOB3BCCJ
ADCOB3BCCV
ADCOB38CCN
ADCOB38CIWM
ADCOB3BCCWM

B

±1

co
Co)

....

i>
c
o
o

co
Co)

N
.....

~

C

o
o

co

Co)

.....
""
~

C

oo

co
Co)
co

See NS Package Number J08A, J14A, J20A, M14B, M20B, N08E, N14A, N20A or V20A

•

2-135

~
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8c tflNational Semiconductor
c(

ADC0833 8-Bit Serial I/O A/D Converter
with .4-Channel Multiplexer
General Description

Features

The ADCOa33, series is an a-bit successive approximation
AID converter with a serial 1/0 and configurable input multiplexer with 4 channels. The serial 1/0 is configured to comply with the NSC MICROWIRETM serial 'data exchange standard for easy interface to the COPSTM family of processors,
as well as with standard shift registers or' JiPs.
The 4-channel multiplexer is software configured for singleended or differential inputs when channel,assigned by a 4bit serial word.
The differential analog voltage input allows increasing the
common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input
can be adjusted to allow encoding any smaller analog voltage span to the full a bits of resolution.

• NSC MICROWIRE compatible-direct interface to COPS
family processors
• Easy' interface to all microprocessors, or operates
"stand alone"
• Works with 2.5V (LM336) voltage reference
• No full-scale or zero adjust required
• Differential analog voltage inputs
• 4-channel analog multiplexer
• Shunt regullltor allows operation with high voltage
supplies
• OV to 5V input range with single 5V power supply
• Remote operation with serial digital data link
• TTL/MaS input/output compatible
• 0.3" standard width 14-pin DIP package

Key Specifications
•
•
•
•
•

a Bits

Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time

± Yo LSB and ± 1 LSB
5 Voc
23 mW
32,.s

Connection and Functional Diagrams

DGND

Dual-in-Line Package (J and N)
y+

14

Yee

cs

2

13

01

CHO

3

12

CLK

CHI

4

CH2

5

CH3

6

9

DGND

7

8

ADC0833

11

SARS

10

DO
YRrF/2
AGND

CHD

TLIH15607-14
Order Number ADC0833CCJ,
ADC0833BCN or ADC0833CCN
See NS Package Number
J14A or N14A

~

CLK

DI

CHI
Top View

SARS

I

ADDRESS
LATCH
AND
DECDDER

CH2

DD
4-CHANNEL S.E.
OR
2-CHANNEL
DIFF.
MULTIPUER

CH3

I

V'
(SHUNT
REGI

Vee
(5VI

VREFI2

UND
TLlHI5607-1

2-136

»
c
o

Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Current into V+ (Note 3)

15mA

Supply Voltage, Vee (Note 3)
Voltage
Logic Inputs
Analog Inputs

6.5V
-0.3V to Vee + 0.3V
-0.3V to vee + 0.3V

Input Current per Pin (Note 4)
Storage Temperature

·O.BW

Lead Temperature (Soldering, 10 sec.)
bual-In-Line Package (Plastic)
Dual-In-Line Package (Ceramic)

260'C
300'C

ESD Susceptibility (Note 5)

2000V

CD

(,)
(,)

Operating Conciitions (Notes 1 & 2)

±5mA

Package Input Current (Note 4)

«:)

Package Dissipation at
T A = 25'C (Board Mount)

±20 rnA
-65'Cto + 150'C

Supply Voltage, Vee

4.5 VDe to 6.3 VDe

Temperature Range
ADCOB33CCJ
Abc0833BCN, ADCOB33CCN

TMIN,;;TA,;;TMAX
-40'C';; TA';; 85'C
0'C,;;TA,;;70'C

Electrical Characteristics

The following specifications apply for Vee = v+ = 5V, felK = 250 kHz and
VREF/2 ,;; (Vee + 0.1V) unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits
,
TA = Tj = 25'C.

Parameter

Typ
(Note 6)

Conditions

Te.sted
Limit
(Note 7)

Design
Limit
(Note 8)

±%
±1
±1

±%
±1

Units

CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted Error
ADC0833BCN
ADC0833CCN
ADC0833CCJ

VREF/2 Forced to 2.500 VDe
LSB
LSB
LSB

Minimum Total Ladder
Resistance (Note 9)
ADC0833CCJ
ADC0833BCN/CCN

7.0
7.0

2.6
2.6

2.6

k.o.
k.o.

Maximum Total Ladder
Resistance (Note 9)
ADC0833CCJ
ADC0833BCN/CCN

7.0
7.0

11.8
10.8

11.8

k.o.
k.o.

GND-0.05

GND-0.05

V
V

Vee + 0.05
Vee + 0.05

Vee+ 0 •05

V
V

±%
±%

±%

LSB
LSB

1
1

1

LSB
LSB

Minimum Common-Mode
Input Range (Note 10)
ADC0833CCJ
ADC0833BCN/CCN

All MUX Inputs and COM Input

Maximum Common-Mode
Input Range (Note 10)
ADC0833CCJ
ADCOB33BCN/CCN

All MUX Inputs and COM Input

GND-0.05

DC Common-Mode Error
ADC0833CCJ
ADC0833BCN/CCN
Change In Zero
Error From Vee=5V
To Internal Zener
Operation (Note 3)
ADC0833CCJ
ADCOB33BCN/CCN

±'/16
±'/16
15mAlntoV+
Vee=N.C.
VREF/2 = 2.500V

2-137

•

Electrical Characteristics The following specifications apply for Vee = V+ = 5V, fCLK = 250 kHz and
VREF/2 ~ 01cc + 0.1V) unless otherwise specified. Boldface limits apply from tMIN to tMAXi another limits TA = Tj ,= 25'C.
(Continued)
Parameter

Typ

Conditions

(Note 6)

Tested
Limit
(Note 7)

Design
Limit
(Note 8)

Units

CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued) ,
Vz, Minimum Internal
Diode Breakdown
(At V +) (Note 3)
ADC0833CCJ
ADC0833BCN/CCN

15mAlntoV+

Vz, Maximum Internal
Diode Breakdown
(At V + )(Note 3)
ADC0833CCJ
ADC0833BCN/CCN

15mAlntoV+

Power Supply Sensitivity
ADC0833CCJ
ADC0833BCN/CCN

Vcc=5V±5%

IOFF' Off Channel Leakage
Current (Note 11)
ADC0833CCJ

On Channel = 5V, Off Channel = OV

6.3
6.3

V
V

8.5

8.5

V
V

±%
±%

±%

LSB
LSB

6.3

8.5

±1j,6
±1j,a

-1

/LA
nA

-200,

-1

ADC0833BCN/CCN

!LA

-200

nA

1

/LA
nA

On Channel = OV, Off Channel = 5V
ADC0833CCJ

200
ADC0833BCN/CCN

1
200

/LA
nA

On Channel == 5V, Off Channel = OV

ION, On Channel'Leakage
Current (Note 11)
ADC083CCJ

1

/LA
nA

200
ADC0833BCN/CCN

1
200

/LA
nA

-1,

!LA

On Channel = OV, Off Channel = 5V
ADC083CCJ

-200

nA

-1

ADC0833BCN/CCN
-200

/LA
nA

DIGITAL AND DC CHARACTERISTICS
VIN(1), Logical "1" Input
Voltage
ADC0833CCJ
ADC0833BCN/CCN

I

Vee=5.25V

2.0
2.0

VIN(O), Logical "0" Input
Voltage
ADC0833CCJ
ADC0833BCN/CCN

VCC= 4.75V

IIN(1), Logical "1" Input
Current
ADC0833CCJ
ADC0833BCN/CCN

VIN=VCC

2.0

V
V

0.8

V
V

0.8
0.8

0.005
0.005
2·138

1
1

/LA

1

!LA

Electrical Characteristics The following specifications apply for Vcc =
VREF/2 ~ (Vee
(Continued)

V+ = SV. fCLK = 250 kHz and
Ti = 2SoC.

+ 0.1V) unless otherwise specified. Boldface limits apply from tMIN totMAX; all other limits TA =

Parameter

Typ
(Note 6)

Conditions

Tested
Limit
(Note 7)

Design
Limit
(Note 8)

Units

-1

/J- A
/J- A

DIGITAL AND DC CHARACTERISTICS (Continued)
IIN(O). Logical "0" Input
Current
ADC0833CCJ
ADC0833BCN/CCN

VIN=OV

VOUT(1). Logical "1" Output
Voltage
ADC0833CCJ
ADC0833BCN/CCN
ADC0833CCJ
ADC0833BCN/CCN

Vee = 4.75V

VOUT(O). Logical "0" Output
Voltage
ADC0833CCJ
ADC0833BCN/CCN

IOUT=1.6mA. Vec=4.7SV

lOUT. TRI-STATE Output
Current (DO. SARS)
ADC0833CCJ
ADC0833BCN/CCN
ADC0833CCJ
ADC0833BCN/CCN

-O.OOS
-O.OOS

-1
-1

2.4

IOUT= -360/J-A

2.4

4.5

V
V
V
V

0.4

V
V

2.4

4.5

IOUT= -10/J-A

4.S

0.4
0.4

VOUT=O.4V
VOUT=SV

ISOURCE
ADC0833CCJ
ADC0833BCN/CCN

VOUT Short to GND

ISINK
ADC0833CCJ
ADC0833BCN/CCN

VOUT Short to Vee

Icc. Supply Current (Note 3)
ADC0833CCJ
ADC0833BCN/CCN

VREF/2 Open Circuit

2-139

-0.1
-0.1
0.1
0.1

-3

-14
-14

-8.5

16
16

8.0

0.9
0.9

4.5

-3

3

/J- A
/J-A
/J- A
/J- A

-6.5

mA
mA

8.0

mA
mA

4.5·

mA
mA

-3

3
3

-7.5

9.0

4.S

AC Electrical Characteristics The following specifications apply for VCC '= V+

'=

5V andtr = tf = 20 ns

unless otherwise specified. These limits apply for T A = Tj = 25°C.

Parameter

Conditions

fCLK. Clock Frequency

Tested

Typ

Limit

(Note 6)

(Note

Limit

kHz
400

8

Not including MUX Addressing Time

Units

(Note 8)

10

Min
Max

T C. Conversion Time

7)

Design

kHz
1/fCLK

Min

40

Max

60

%
%

250

nil

90

ns

Clock Duty Cycle (Note 12)

IsET-UP. ~ Falling Edge or,
Data Input Valid to ClK
Rising Edge
tHOLD. Data Input Valid
alter ClK Rising Edge
tpdl. tpdo-ClK Falling

CL = 100pF

Edge to Output Data Valid

Data MSB First

650

1500

ns

(Note 13)

Data lSB First

250

600

ns

tl H. toH-Rising Edge of ~

CL= 10pF.RL= 10k

125

to Data Output and SARS

CL = 100 pF. RL = 2k

Hi-Z

(see TRI-STATE Test Circuits)

250
500

CIN. Capacitance of logic

5

ns
ns

pF

Input
5

COUTo Capacitance of logic
Outputs

pF
"

Not. 1: Absolute Maximum Ratings Indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specHled operating condHions,
Note 2: All voltages are measured with respect to the ground pins.
Not. 3: Internal zener diodes (approx. 7V) are connected from V+ to GND and Vee to GND, The zener at V+ can operate as a shunt regulator and is connected to
Vee via a conventional diode. Since the zener voltage equals the AID's breakdown voltage, the diode insures that Vee will be below breakdown when the device Is
powered from V+, Functionality is therefore guaranteed for V+ operation even though the resultant voltage at Vee may exceed the specHied Absolute Max. of
6.5V. It is recommended that a resistor be used to limit the max. current into V+.

Note,4: When the Input voltage (YIN) at any pin exceeds the power supply reils (YIN < V- or VIN > V+) the absolute value of current at that pin should be IimHed
to 5 mA or less. The 20 mA package input current IimHs the number of pins that can exceed the power supply boundaries wHh Ii 5 mA current limit to four.
Note 5: Human body model, 100 pF discharged through a 1.5 kn resistor.
Note 8: Typicals are at 25"C and represent most likely parametric norm.
Note 7: Tested limits are guaranteed to National's AOOL (Average OutgOing Quality Level).
Note 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 9: See Applications, section 3.0,
Note 10: For VIN( -)"' VIN( + ) the digHal output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward
conduct for analog Input voltages one diode drop below ground or one diode drop greater than the Vee supply. Be careful, during testing at low Vee levels (4.5V),
as high level analog inputs (5V) can cause this input diode to conduct-especially at elevated temperatures, and cause errors for analog inputs near full-scale. The
spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50 mY, the
output code will be correct To achieve an absolute 0 Vee to 5 Vee input voltage range will therefore require a minimum supply voltage of 4.950 Vee over
temperature variations, initial tolerance and loading.
Note 11: Leakage current Is measured wHh the clock not swHching,
Not. 12: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of
these limits, the minimum time the clock is high or the minimum time the clock is low must be at least l,",s. The maximum time the clock can be high is 60 ,",S. The
clocked can be stopped when low so long as the analog input voltage remains stable,

Note 13: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is builtin (see Block Diagram) to
allow for comparator response time.

2-140

.

,

.--------------------------------------------------------------------.~

c

Timing Diagrams

o
o

co
Co)
Co)

Data Output Timing

Data Input Timing

ClK

DATA
OUT (DO)

TRI-STATE Test Circuits and Waveforms

~~'H
~

ODANO :::
SARSOUTPUTS

.
GNO------=

1,=20 ns
tDH

Vcc

Vcc

lOll
DATA
DUTPUT

ODANDVCC~~
, SARSOUTPUTS VOL

~

1,=20 ns

Leakage Current Test Circuit
5V
ADCDB33
CH A (ON CHANNEL)

CHANNEL
VDlTAGE
SELECT

. . ----1::: Ig~:NNELS
L_________

CH D

TL/H/5607-2

2-141

~
~

§c

r---------------------------------------------------------------------------------,
Typical Performance Characteristics
Effect of Unadjusted Offset
Error vs VREF/2 Voltage

Linearity Error vs
VREF Voltage

16rn~~-r~~"Tmrn

H
14H

I
~

VIH(+)=VIN(-)=OV
ASSUMES Vos=2mV.

12~

lHlS SHOWS lHE NEED

10

lHE SPAN IS REOUCEO.

rr-

FOR A ZERO AOJ. IF

8

=
--

6

4
2
0
0.01

0.1

1~r-~--'---r-~--,

1.251--+--+--t--+--J
'Oi'
Vcc=5V
(250Kllz) _
~ 1.0
TA=25CC
0.75

.a
~

~

!!i

1.0

O~

Vcc=5V
125CC

2.D
1~

1.0
M

I

-55CC

/

L.

25CC
0
10 100

r--...-

Vcc=5V
VRU/2=UV
'aJ(i 250 KHt
-100

-so

0

so

100

lSO

25r---:r--r-~-r--'

VRU/2=2~V

~z

0.25

Output Current
vs Temperature

3.0

::I

I1:

. TEMPERATURE (CC)

VREFEi2(V)

Power Supply Current

I

~

O~~--~~--~~

~

1

Linearity Error vs fClK

~

""

'Oi'

!!i

VRU/ 2(VrJi)

~

O~r-~--r-~-r--'

~

"

0.25
0
0

5

Linearity Error
vs Temperature

200 300 400

soo

i :I1T+-+-+--J
i ut~t-r-I
r
faJ(= 250~r-"''''''-.I.--l

1.0

600

CSf"l

vr

-75-50 -25 0

1aJ( (Kllz)

25

so

75 100 125

TEMPERATURE (CC)

TEMPERATURE (CC)

Power Supply
Current vs fClK
~r-~-'--r-~-,

Vcc15v@~cc

2.D1--+--+--t--+--J

l.o~~-~-~~-~

o

100

200

300

400

SOO

Icu«KHz)
TL/H/5607-3

2·142

01 a!?
e§o!

, ,

_J

~

~,

»
c
oQ

C»

t

W
W

."

c

::J

SGUiii!'

n

START CONY AND ENABLE TSL OUTPUT BUFFER

0'

elK _12

::J

MUX
ADDRESS

Dr ' ~
TO

., I .

CH

,!.o I

•

~

I

I

~

ANALOG
MUX
IEnUIVAlENn

~

....

'"

f I. t I..

CH2::5
~~-+-+--J'
CH30 6 '

I.

"=.... I ,

,

%I.

. . o'H
Vee

__
ch

COMP

r-

.1
R

Bl

,

,

•

Di'

ce

b-t:m

DJ

3

II
n

~~

L-

~cs

! llEOC
R

i

C

B5

~TO~~~U~~:~

SAR
lOGIC
AND
lATCH

B4

4

~

TO
INTERNAL

17

CIRCUITS

B-BIT
SHIFT
REGISTER

1

JL

CS .....IR

:~'
n
1,0

00

D

Bl
BD

VCC

13 INPUT
16

B3

!!

I

AGND

~

C

II

':'

':'

n

C R

cs

I

0'

STARTlI

~

•

V
tR

.,"

m

I

TIME

~

~

tlVZENER

DONol

S~y

M::f+Q;11

Vee

CHO~~
t I~ , I~

!!.

EOC

18
INPUT PROTECTION - All lOOIC INPUTS

"*

PARALLEL
XFRTO
SHIFT REG

TLlH/5607 -4

&&80:>0"

II

~ r-------------------------------------------------------------------------~
~

~

c

Timing Diagram
CLOCk
IOLK)
CHIPIELECT

191

.lEn~~':"'::··~'~~~:::::::::J~~~~~~~~!E~::::::::~::~::~~~

DATAl .....

IDI) , ..
DOl7

S8L111lJ!

~RnMUS~~_~~.~UX~C~D.~FI~GU~R~.~~~~~.~W~D~R~~F::t::-----------------------t--------------------~--------~"¢~~~
CAR'

(lARS) TRI-

MUX
SETTLlla-l---I---

STATE

nM'

DATA ~~1---TR»TAT"-----...j

TLlHI5607-5

acquisition systems is significantly simplified with this type
of input flexibility. One converter package can now handle
ground referenced inputs and true differential inputs.
A particular input configuration is assigned during the MUX
addreSSing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differential. In the differential case, it also assigns the polarity of the
channels. Differential inputs are restricted to adjacent channel pairs. For example channel 0 and channel 1 may be
selected as a differential pair. Channel 0 or 1 cannot act
differentially with any other channel. In addition to selecting
differential mode the sign may also be selected. Channel 0
may be select,ed as the positive:input arid channel 1 as the
negative input or vice versa. This programmability is best
illustrated by the MUX addressing codes shown in the following table. The MUX address is shifted into the converter
through the 01 line.

Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of the ADC0833 utilizes a sample-data comparator structure which provides for a differential analog input
to be converted by a successive approximation routine.
The aciual voltage converted is always the difference between an assigned" +" input terminal and a .. -" input terminal. The,polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive. If the assigned" +" input is less than the
.. -" input the converter responds with an all zeros output
code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-configurable
single-ended (ground referred) or differential inputs. The analog signal conditioning required in transducer-based data

,

TABLE I. MUX Addressing
Single-Ended MUX Mode
Address

Channel #

SGLI

0001

DiF

SIGN

1

1
1'

0

0

1

0

1

1

1

1

0

1

1

1

1

1

SELECT

0

3

2

1

0

+
+
+
.

+

2

3

+

-

-

+

'

COM Is Internally ties to a GND

Differential MUX Mode
Channel #

Address
SGLI

0001

OIF

SIGN

1

0

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

SELECT

2-144

0

1

+

-

-

+

Functional Description

(Continued)

Since the input configuration is under software control, it
can be modified, as required, at each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion. Figure 1 illustrates the input flexibility which can be achieved.

ting highly noise immune digital data back to the host processor.
To understand the operation of these converters it is best to
refer to the Timing Diagram and Functional Block Diagram
and to follow a complete conversion sequence. .
1. A conversion is initiated by first pulling the CS (chip select) line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its
MUX assignment word.

The analog input voltages for each channel can range from
50 mV below ground to 50mV above Vcdtypically 5V) without degrading conversion accuracy.

2. A clock is then generated by the processor (if not provided continuously) and output to the AID clock input.

2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very Significant system improvements; it allows more function to be included in the
converter package with no increase in package size and it
can eliminate the transmission of low level analog Signals by
locating the converter right at the analog sensor; transmit-

3. On each rising edge of the clock the status of the data in
(01) line is clocked into the MUX address shift register. The
start bit is the first logic "1" that appears on this line (all
leading zeros are ignored). Following the start bit the converter expects the next 4 bits to be the MUX assignment
word.
.

4 Single-Ended

2 Differential

o

2

3

+

,.

AGND

Mixed Mode

TL/H/5607-6

FIGURE 1. Analog Input Multiplexer Options for the ADC0833

2-145

Functional Description

inputs vary between very specific voltage limits and the reference voltage for the AID converter must remain stable
with time and temperature. For ratiometric applications, an
AOCOa34 is a 'pin-for-pin compatible alternative since it has
a VREF input (note the AOCOa34 needs one less bit of mux
addressing information).

(Continued)

4. When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of Y2 clock
period (where nothing happens) is automaticaily inserted to
allow the selected MUX channel to settle. The SAR status
line goes high at this time to . signal thata conversion is now
in progress and t~e 01 line is disabled (it no longer accepts
data).
.

The voltage applied to the VREF/2 pin defines the voltage
span of the analog input [the difference between VIN( + )
and VIN( -)1 over which the 256 possible output codes ap·
ply. A 'full-scale conversion (an all 1s output code) will result
when the voltage difference between a selected" +" input
and "-" input is approximately twice the voltage at the
VREF/2 pin. This internal gain of 2 from the applied refer·
enc.e to the full-scale' input voltage allows biasing a low voltage reference diode from the 5VDC converter supply. To
accommodate a 5V input span, only a 2.5V reference is
required. The LM3a5 and LM336 reference diodes are good
low current devices to use with these converters. The output code changes in accordance with the following equa-.
tion:

5. The data out (DO) line now comes out of TRI-STATE and
provides a leading zero for this one clock period of MUX
settling time.
6. When the conversion begins, the output of the SAR comparator, 'which indicates whether the anaiog input is greater
than (high) or less ~han (low) each successive voltage from
the. internal resistor ladder, appears at the DO line on each
falling edge of the clock .. This data is the result of the can·
version being shifted out (with the MSB coming first) and
can be read by the processor immediately.

7. After a clock periods the conversion is completed. The
SAR status line returns low to indicate this Y2 clock cycle
later.

VIN(+) - VIN(-»)
Output Code = 256 (
2(VREF/2)
where the output code is the decimal equivalent of the a-bit
binary output (ranging from 0 to 255) and the term VREF/2 is
the voltage from pin 9 to ground.

a. If the programmer prefers, the data can be read in an LSB
first format. All a bits of the result are stored in an output
shift register. The conversion result, LSB first, is automatically shifted out the DO line, after the MSB first data stream.
The DO line then goes low and stays low until CS is returned high.

The VREF/2 pin is the center paint of a two resistor divider
(each resistor is 3.5 kn) connected from Vee to ground.
Total ladder input resistance is the sum of these two equal
resistors. As shown in Figure 2, a reference diode with a
voltage less than Vcc/2 can be connected without requiring
an external biasing resistor if its current requirements meet
the indicated level.

9. All internal registers are cleared when the "CS line is high.
If another conversion is desired, "CS must make a high to
low transition followed by address information.
The 01 and DO lines can be tied together and controlled
through a bidirectional processor 1/0 bit with one wire. This
is possible because the 01 input is only "looked-at" during
the MUX addressing interval while the DO line is still in a
high impedance state.

The minimum value of VREF/2 can be quite small (see Typical Performance Characteristics) to allow direct conversions
of transducer outputs providing less than a 5V output span.
Particular' care must be taken with regard to noise pickup,
circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of
the converter (1 LSB equals VREF/256).

3.0 REFERENCE CONSIDERATIONS
The AOCOa33 is intended primarily for use in circuits requiring absolute accuracy. In this type of system, the analog

Ycc

Vee

5V

CHO1-

,-

CHO

3.5k

CH11CH2! CH3-

Uk

GND

~~LM385-1.2V

3.5k

CH11-

+

ADC0833

5V

!

I

~REF/2

ADC0833
CH2!-

CH31-

...

~ 3.5k

.

,~

~336-2.5V

UND

TlIH/5607-7

VFUll-5CAlE '" 2.4V

VFUll-5CAlE '" 5.0V
vee
Vee/2 - Vz
Note: No external biasing resistor needed if Vz < """2" and Iz min < 1.75 kn

FIGURE 2. Reference Blasing Examples

2-146

Functional Description

(Continued)
is necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and .the ideal % LSB value
(% LSB=9.8 mV for VREF/2=2.500 VDcl.

4.0 THE ANALOG INPUTS
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling processor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the inputs be noisy to begin with or possibly
riding on a large common-mode voltage.

5.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1 % LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the VREF input or Vcc for a digital output code
which is just changing from 1111 1110 to 1111 1111.

5.3 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A VIN( +) voltage which
equals this desired zero reference plus % LSB (where the
LSB is calculated for the desired analog span, using
1 LSB = analog span/256) is applied to selected" +" input
and the zero reference voltage at the corresponding "-"
input should then be adjusted to just obtain the OOHEX' to
01 HEX code transition.
The full-scale adjustment should be made [with the proper
Vln( -) voltage applied] by forcing a voltage to the VIN( + )
input which is given by:

The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected "+" and "-" inputs for a conversion (60
Hz is most typical). The time interval between sampling the
" +" input and then the "-" input is % of a clock period.
The change in the common-mode voltage during this short
time interval can cause conversion errors. For a sinusoidal
common-mode signal this error is:
0.5 )
Verror(max) = VPEAK(21TfCM) ( fCLK
where fCM is the frequency of the common-mode signal,
VPEAK is its peak voltage value
and fCLK is the AID clock frequency.
For a 60 Hz common-mode signal to generate a % LSB
error (::::: 5 mY) with the converter running at 250 kHz, its
peak value would have to be 6.63V which would be larger
than allowed as it exceeds the maximum analog input limits.

V (+) fs adj· = V
- 1.5 [ (VMAX - VMIN) ]
IN
MAX
256
where:
VMAX= the high end of the analog input range

Due to the sampling nature of the analog inputs short spikes
of current enter the" + " input and exit the" -" input at the
clock edges during the actual conversion. These currents
decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents and cause
an effective DC current to flow through the output resistance of the analog signal source. Bypass capacitors should
not be used if the source resistance is greater than 1 kn.
This source resistance limitation is important with regard to
the DC leakage currents of input multiplexer as well. The
worst-case leakage current of ± 1 ",A over temperature will
create a 1 mV inut error with a 1 kn source resistance. An
op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance
signal source be required.

and
VMIN= the low end (the offset zero) of the analog
range.
(Both are ground referenced.)
The VREF/2 voltage is then adjusted to provide a code
change from FEHEX to FFHEX. This completes the adjustment procedure.
6.0 POWER SUPPLV
A unique feature of the ADC0833 is the inclusion of a 7V
zener diode connected from the V+ terminal to ground
which also connects to the VCC terminal (which is the actual
converter supply) through a silicon diode, as shown in FigureS.

5.0 OPTIONAL ADJUSTMENTS
5.1 Zero Error

Vs

R V.

The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not ground
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any VIN (-) input at this VIN(MIN) value. This
utilizes the differential mode operation of the AID.

.......

Vee
ACTUAL
CDNVERTER
SUPPLY

~ (7V

The zero error of the AID converter relates to the location
of the first riser of the transfer function and can be measured by grounding the VIN( -) input and applying a small
magnitude positive voltage to the VIN( +) input. Zero error is
the difference between the actual DC Input voltage which

GND

TL/H/5607-8

FIGURE 3. An On-Chip Shunt Regulator Diode

2-147

fII

~ ~-----------------------------------------------------------------------------------------,
~

I

Functional Description

(Continued)
to be derived from the clock. The low current requirements
of the AID (-3 mA) and the relatively high clock frequencies used (typically in the range of 10k-400 kHz) allows using the small value filter capacitor shown to keep the ripple
on the Vee line to well under y.. of,an lSB. The shunt zener
regulator can also be used in this mode. This requires a
clock voltage swing which is in excess of Vz. A current limit
for the zener is needed, either built into the clock generator
or a resistor can be used from the elK pin to the V+ pin.

This zener is intended for use as a shunt voltage regulator
to eliminate the need ,for any additional regulating components. This is most desirable if the converter is to be remotely located from the system power source. Figures 4
and 5 illustrate two useful applications of this on-board zener when an external transistor can be afforded.
An important use of the interconnecting diode between v+
and Vee is shown in Figures 6 and 7. Here, this diode is
used as a rectifier to allow the Vee supply for the converter

Applications
12Y
, - -....-SYSTEM
SUPPLY
1.6k
Y+ 7Y

ADCD833

Y+

12V
lk
SYSlEM --'W_.....-"""'

4---1H---........+-+-v,'

SUPPlY

Vee 6.4

ADC0833

TO.,

6.4

CMOS
OR
NMOS

ANALOG

CIRCUITS

CIRCUITS
GNO

TLiH/SS07-16

TL/H/5607-1S

FIGURE 4. Operating with a Temperature
Compensated Reference

vt

......

f,o}l
---

FIGURE 5. Using the AID as the
System Supply Regulator

Vee
,

I+"'Nv•

CLK

•

>-

~[+- GO

CHO

[+-

•

SK

AOC0833

>-

CH3

DO

f-+

CLK

•

COP42D
011+- SO

•

~+- Pl3

CHO

>-

Pl2

AOCD833

INSIID4B
Ol+- Pl,

•

SI

+-

CH3

00

--t

Plo

TL/H/S607-10

,
COP CODING EXAMPLE
Mnemonic
LEI
SC
OGI
CLRA
AISC1
XAS
LDD

8048 CODING EXAMPLE
Instruction
;SELECT AID (CS=O)
;BiT COUNTER - 5
;A - MUX ADDRESS
;CY - ADDRESS BIT
;TESTBIT
;BIT=O
P1, #OFEH ;01-0
ZERO:
ANL
;CONTINUE
JMP CONT
;BIT=1
ONE:
ORL P1, #1
;01-1
CO NT: -CALL PULSE
;PULSE SK 0 - 1 - 0
DJNZ B, LOOP 1 ;CONTINUE UNTIL DONE
CALL PULSE
;EXTRA CLOCK FOR SYNC
;BIT COUNTER _ 8
MOV B,#8
LOOP 2: CALL PULSE
;PULSESKO - 1 - 0
A,P1
;CY-DO
IN
RRC A
RRC A
;A- RESULT
MOV A,C
RLC A
;A(O) - BIT AND SHIFT
;C-RESULT
MOV C,A
DJNZ B, LOOP 2 ;CONTINUE UNTIL DONE
RETR
;PULSE SUBROUTINE
PULSE: ORL P1, #04
;SK-1
NOP
;DELAY
ANL P1, #OFBH ;SK-O
RET

Instruction
ENABLES SIO's INPUT AND OUTPUT
C=1
GO=O(CS=O)
CLEARS ACCUMULATOR
LOADS ACCUMULATOR WITH 1
EXCHANGES SIO WiTH ACCUMULATOR
_AND STARTS SK CLOCK
LOADS MUX ADDRESS FROM RAM
INTO ACCUMULATOR

Mnemonic
P1, #OF7H
ANL
MOV B, #5
MOV A,#ADDR.
LOOP 1: RRC A
JC
ONE

START:

-

NOP
XAS

LOADS MUX ADDRESS FROM
ACCUMULATOR TO SIO REGISTER

t
8 INSTRUCTIONS

J.
XAS
XIS
CLRA
RC
XAS
XIS
OGI
LEI

READS HIGH ORDER NIBBLE (4 BITS)
INTO ACCUMULATOR
PUTS HIGH ORDER NIBBLE INTO RAM
CLEARS ACCUMULATOR
C=O
READS LOW ORDER NiBBLE INTO
ACCUMULATOR AND STOPS SK
PUTS LOW ORDER NIBBLE INTO RAM
GO=1 (CS=1)
DISABLES SIO's INPUT AND OUTPUT

2-149

II

Applications (Continued)
A "Stand-Alone" Hook-Up for ADC~833 Evaluation

MUX ADDRESS

~:::::;::::::~::::=1;:::~--o5VDC
-START lIT

51k(4)

SGLfDiF

J J J J

11

12

13

15

14
PARALLEL INPUTS

3

NO

INPUT SHIft REGISTER
74Cl85

DD

Vee

,.

§VDC

SYDC

elR

H~::+-o'VDe
OUTPUT SHIFT REGISTER
74C114

".

"

DA
1D

NSLSDZ'JII)

StJ274C74

!iJI

,v

,v

MSI

'!II

iii

!iJI

iii

iii
LSI

DATA DISPLAY

riVac

Low Cost Remote Temperature Sensor

Vee

lM33.

1--..-.-.
TIDIIF

':'
ADClll33

CHI

1.511

V,NI-!

TUH/5607-11

2-150

r--------------------------------------------------------------------.~

C

Applications (Continued)

oo

CO

w
w

Digitizing a Current Flow

100

ZERO ~'''''----''''''CHI
ADJ

120k

Operating with Automotive Ratlometric Transducers

•

Vcc
(5VDC)

~

20k
XDR

VXDR •

V'N(»

ZE~~ • ~+-

Vcc

f

V'NI-l°

ADJ'

3k

~

+
lOPF

ADCD833

•

-=:-

l.k

1/z~~
VREF/2

+

T

1PF

·VIN(-)=O.15 Vee

1k
FS

.........

0.35 Vcc

"'"

ADJ

!>

:=

Uk

.. 100

TL/H/5607 -12

2-151

Applications (Continued)
Span Adjust: OV ~ VIN ~ 3V

Vee
(IVoel
Vee 1--4--------.

r--<>--I V,.(+I
V,N

2.
AOCOln

TLlH/5607-18

Zero-Shift and Span Adjust: 2V~VIN~5V

Vee

ISVoel
Vee 1--4----------,

r--<>--IV'N(+I

u.

SETS ZERO

CODE VOLTArGE~VIr--"""IM,....--+_+_---=!....I~-....- . J
UII

1k
IVoe
ZEAO ADJ

'='

'='

'='
TL/H/5607 -19

Protecting the Input

High Accuracy Comparators

Vee
(5

IV

vue>

Vee

~[

: la.,
AIICIII33

¥nil

TO
C1IIITRIIUER

:}2,3

-15 Voc
ADC0833
DO
DO

Diodes are lN914

= all Is il + Y,N >
= all Os II + VIN <

TLlH/5607-20

For addlttonal application ideas. refer to the date sheet for the ADC0831 family of sertal date converters.

2-152

-Y,N
-Y'N

TL/H/5607-13

,--------------------------------------------------------------------,

~

c

g

Ordering Information

co

Part Number

Temperature
Range

Total
Unadjusted
Error

ADCOB33BCN

O'Cto +70'C

±1/2LSB

ADCOB33CCJ

-40'Cto +B5'C

ADCOB33CCN

O'Cto +70'C

c.:I
c.:I

±1 LSB

fI

2-153

t!lNational Semiconductor

ADC08031/ ADC08032/ ADC08034/ ADC08038 8-Bit
High-Speed Serial I/O A/D Converters with Multiplexer
Options, Voltage Reference, and Track/Hold Function
General Description

Features

The ADC08031 / ADC08032/ ADC08034/ ADC08038 are
8-bit successive approximation AID converters with serial 1/
and configurable input multiplexers with up to 8 channels.
The serial I/O is configured to comply with the NSC
MICROWIRETM serial data exchange standard for easy interface to the COPSTM family of controllers, and can easily
interface with standard shift registers or microprocessors.

• Serial digital data link requires few I/O pins
• Analog input track/hold function
• 2-, 4-, or 8-channel input multiplexer options with address logic
• OV to 5V analog input range with single 5V power
supply
• No zero or full scale adjustment required
• TTL/CMOS input/output compatible
• On chip 2.6V band-gap reference
• 0.3" standard width 8-, 14-, or 20-pin DIP package
• 14-, 20-pin small-outline packages

o

The ADC08034 and ADC08038 provide a 2.6V band-gap
derived reference. For devices offering guaranteed voltage
reference performance over temperature see ADC08131,
ADC08134 and ADC08138.
A track/hold function allows the analog voltage at the positive input to vary during the actual A/D conversion.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or pseudo-differential modes. In addition, input voltage spans as small as 1V
can be accommodated.

Applications
•
•
•
•
•
•

Digitizing automotive sensors
Process control monitoring
Remote senSing in noisy environments
Instrumentation
Test systems
Embedded diagnostics

Key Specifications
•
•
•
•
•
•

Ordering Information
Industrial (-40"C

S;

TA

S;

+85"C)

Package

ADC08031 BIN, ADC08031 CIN

N08E

ADC08032BIN, ADC08032CIN

N08E

ADC08034BIN, ADC08034CIN

N14A

ADC0803BBIN, ADC0803BCIN

N20A

ADC08031 BIWM, ADC08031 CIWM,
ADC08032BIWM, ADC08032CIWM,
ADCOB034BIWM, ADCOB034CIWM

M14B

ADC08038BIWM, ADC0803BCIWM

M20B

2-154

8 bits
Resolution
8,...s (max)
Conversion time (fe = 1 MHz)
20mW (max)
Power dissipation
5Voc (±5%)
Single supply
±% LSB and ±1LSB
Total unadjusted error
No miSSing codes over temperature

.--------------------------------------------------------------------, c

~

Connection Diagrams

(')
<:)

00

<:)
Co)

CHO

es

es

Vec
01

CHO

CLK

17

DI

CH1

SARS

16

elK

CH2

DO

2

CH2

3

18

"

CH4

5

CH5

15

SARS

CH6

14

DO

CH7

13

SE

COlo!

12

VREf IN
AGND

DGND

10

);;

VREf OUT

Vec
VREf OUT

CH1
CH3

....

ADC08034

ADC08038

11

c

(')
<:)

00

<:)

W

N
.....

~

C

(')

VREr IN

CH3

<:)

00

AGNO

DGND

<:)
Co)

TL/H/l0555-3

.....
"'"
~

C

(')
<:)

00

TLlH/l0555-2

<:)
Co)

00

ADC08031
Dual·ln·Llne Package

ADC08032
Dual·ln·Llne Package

es

8

VCC(REf)

7

ClK

es

CHO

2

CH1

3

6

DO

v.r

GNO

4

5

DI

GNO

VIN·

8

Vee

7

ClK

3

6

DO

"

5

VREfIN

2

TLlH110555-5

TLlH/10555-4

ADC08031
Sma" Outline Package

ADC08032
Small Outline Package

cs

Vee (VREr )

cs

Ne

NC

He

CHO

ClK

Ne

Ne

Ne

CH1

DO

VINe->

DO

NC

Ne

Ne

Ne

01

GND

GNO

14

Vee
Ne

elK

VIN(+)

Ne

7

VREf
TL/H/10555-31

TLlH/10555-30

2·155

I
~
~

a

Input Current at Any Pin (Note 4)
Power Dissipaiion at TA

= 25'C (Note 5)

C")

CI

Storage Temperature

co

ADC08038BIN, ADC08038CIN,
ADC08031 BIWM, ADCO!l032BIWM,

±20mA

"

ADC08034BIWM, ADC08038BIWM

800mW

ESD Susceptibility (Note 6)
Soldering Information
N Package (10 sec.)
SO Package:
Vapor Phase (60 sec.)
Infrared (15 sec.) (Note 7)

ADC08034BIN, ADC08934CINi

-0.3V to Vee + 0.3V
±5mA

Package Input'Current (Note 4)

oQ


260'C

4.5 Vee to 6.3 Vee

215'C
220'C
.'

-65'Cto + 150"C

CI

oQ

 Vee,) the current at that pin should be IimHed to
5 rnA. The 20 rnA maximum package input CUlTent rating limits the number of pins that can safely exceed the power supplies with an input current of 5 rnA to four
pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX' OJA and the ambient temperature, TA. The maximum
allewable pewer dissipation at any temperature is Po = (TJMAX - TAl/ 0 JA or the number given in the Absolute Maximum Ratings, whichever is lower. For devices
with suffixes BIN, CIN, BIJ, CIJ, BIWM, and CIWM TJMAX = 125'C. For devices with suffix CMJ, TJMAX = 150'C. The typical thermal resistances (OJAl of these
parts when board mounted follew: ADC08031 and ADC08032 with BIN and CIN suffixes 120'C/W, ADC08034 with BIN and CIN suffixes 95'C/W, ADC08038 wHh
BIN and CIN suffixes 80'C/W. ADC08031 with BIWM and CIWM suffixes 140'C/W, ADC08032 wHh BIWM and CIWM suffixes 140'C/W, ADC08034 with BIWM and
CIWM suffixes 14O'C/W, ADC08038 with BIWM and CIWM suffixes 91'C/W.
Note 6: Human body model, 100 pF capaCitor discharged through a 1.5 kn resistor.
Note 7: See AN450 "Surface Mounting Methods and Their Effect on Product Reliability" or Linear Data Book section "Surface Mount" for other methods of
soldering surface mount devices.
Note 8: Typicals are at TJ = 25'C and represent the most likely parametric norm.
Note 9: Guaranteed to National's AOQl (Average Outgoing Quality level).
Note 10: Total unadjusted elTor includes offset, full-scale, linearity, multiplexer.
Note 11: Cannot be tested for the ADC08032.
Note 12: ForVIN(_1 :. VIN(+I the digital code will be 0000 0000. Two on·chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct
for analog input voltages one diode drop belew ground or one diode drop greater than Vee supply. During testing at low Vee levels (e.g., 4.5V), high level analog
inputs (e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors for analog inputs near full-scale. The spec allows
50 mV forward bias of either diode; this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be
correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absclute 0 Voc to 5 Voc input voltage
range will therefore require a minimum supply voltage of 4.950 Voc over temperature variations, initial tolerance and loading.
Nole 13: Channel leakage current is measured after a single·ended channel is selected and the clock is turned off. For off channel leakage current the following
two cases are considered: one, with the selected channel tied high (5 Voc) and the remaining seven off channels tied low (0 Voel, total current flow through the off
channels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured. The two
cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.
Note 14: A 40% to 60% duty cycle range Insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these
limits the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or low is 1001's.
Note 15: Since data, MSB first, Is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to
allow for comparator rasponse time.
Note 18: For the ADC08032 VREFIN Is Internally tied to Vee, therefore, for the ADC08032 reference current is included In the supply currenl

2·158

)0

C

oo

Typical Performance Characteristics

CI)

Linearity Error vs
Reference Voltage
0.50

~
§02S

fClJ(

'Oi'

ci

~ 0.75 +--+--+--t-+--+--'--.,11

'Oi'

ci

;;

~

g
ffi 0.25

~

~

1
2
3
4
REFERENCE VOLTAGE (V)

-100

5

5

!2.D

30

1.0

iil
0.5

Ivcc~
fClJ( =1 MHz .......
rt- lCS ="1"1
i'..

-so

0

so

TE~PERATURE

100

/I

lSO

/-55OC

250C
tE~~w~
o

(OC)

250 500 750 1000 1250 1500 1750
CLOCK FREQUENCY (kHz)

i

20

S

15

G

5
0

.............

i'--

10
5
-100

lSO

n
o

CI)

cCo)

N
......

)0

C

n
o

CI)

oCo)

.j:O.

......
)0

=5 Vee
-so

a~
~

ISOORCE (Vee

=ov)

50

100
(OC)

CI)

oCo)

CI)

Va: = 5 Vee

-- -

1.5 t-I---:::l_-t-"F'=+--t-+-~

8::
iil

1D +--+--+--t-+--+--+--t

~

M+-+-+-+-+-+-+-+

It

l-+

0

n
o

!2.D+-+-+_T~A_=~25,OC--t_+-~

........

TE~PERATURE

(OC)

Power Supply Current
vs Clock Frequency

~ I-- ISINK (Vee =5V)

Vee
0.0
-100

0.25

2.5

1
-25

=~.5 veel

100

1/ -1
1-+-1--1-+-+-1\

Output Current vs
Temperature
35

Nee

0.50

i>
c

c

2.5

1.5

so

0

TE~PERATURE

Power Supply Current vs
Temperature (ADC08038,
ADC08034, ADC08031)

is

-so

moc,

~

VREF 5.0V
fell( 1 ~Hz
0.00

0

~

~

=
=1

~

5
0.00

~

~

r-

~

5

~

1.00 ,------,-,-...,.---,----,
VREF = 5 Vee
Vee = 5 Vee f--!-+-t---l

D.5O

=5 Vee
= 1 MHz
T... =250C

vee

oCo)

....

Linearity Error vs
Clock Frequency

Linearity Error vs
Temperature

M~+~~_~+~~

150

0250500 7501000125015001750
CLOCK FREQUENCY (kHz)
TUH/l0555-6

Note: For ADC08032 add IREF

Leakage Current Test Circuit
5V

fII
TL/H/l0555-7

2-159

co

s

8
c

TRI-STATE Test Circuits and Waveforms

..
c(

......

Vee

Cf)

g
8
c

OOANO : : :

c(

......
N

SARS OUTPUTS

---=CJ:~IH
~

GNO------=

Cf)

CI

co

CI

CJ

toH

C

c(

......
,-

Vee

tOH

Vee

Cf)

CI

co

CI

o
cc(

GNO

DATA
OUTPUT

oP-

DO AND Vee
SARS OUTPUTS VOL

TL/H/l0555-8

10%

TlIH/l0555-9

Timing Diagrams
Data Input Timing
CLK _ __

cs

---""I

DATA _ _ _ _ _--'1
IN(DI)
TlIH/l0555-10

'To reset these devices, eLK and ~ must be simulleneously high lor a period 01 tsELECT or greater. Otherwise these devices are compatible with industry
slendards ADCOS31 /2/4/S.

Data Output Timing
elK

DATA
OUTIOOI

TL/H/l0555-11

ADC08031 Start Conversion Timing

eLK

--START
CONVERSION

oo------------~~

____

2-160

~
BIT6

TlIH/l0555-12

»

o
o
c

Timing Diagrams (Continued)

co
c

ADC08031 Timing
10

w
.....
.....
~

11

CLOCK
(CLK)

g

co
c
W

CHIP SELECT

N
.....

(Cs)

»

o
o
c

co
c
w
,a:o.

DATA OUT

(DO)

......
TLlHll0555-13
'LSB firsl oulpul nol available on ADC08031.
LSB informalion is mainlained for remainder of clock periods unlil

co
c
w
co

CS goes high.

ADC08032 Timing
10

11

12

13

14

15

16

17

»
o

o
c

18

19

20

CLOCK
(eLK)
CHIP SELECT

(Cs)
DATA IN

(01)

DATA OUT _ _~~=-.,

(DO)

o

7

(MSB)

7

(lSB)

(MSB)
TLIHll0555-14

ADC08034 Timing
10

Ii

12

13

14

15

16

17 .18

19

20

21

II

CLOCK
(elK)
CHIP SELECT

(Cs)

DATA IN

(01)
SAR STATUS

(SARS)

DATA (~~ _ _ _ _ _ _ _-,
7

o

(Wsa)

(lsa)
Tl1Hll0555-15

2-161

ADC08031!ADC08032! ADC08034! ADC08038
-I

3"

5"
cc

cij"

CC

ADC08038 Timing
0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

""I

I»
16

17

18

19

20

21

22

23

24

25

26

CLOCK

(CLK)

CHIP SElECT

(CS)

3fI)

-0
0

I

["'-I..VV' . . . . . ....,v

:::J
d:

II.....

''cal

.1

I

ADDRESS IIUX

DATA IN
(01)

~I

SAR STATUS
(SARS)

(I)
I\)

5[="0"
MTA OUT (00)

-r

SE TO
CONtROL
LSB
FIRST

OUTPUT

00

....... ....... ....... ....... i.
7
6
(IISB)

5

4

3

2

1

0

(LSB)

.1

....... ....... .......
1

2

3

4

5

6

7

(IISB) _
. TLlH/10555-16

"Make sure clock edge '" 18 clocks in the

Lila before "SI: is taken low

CLK 0

,

16
18

CS

~Q

1>0

D

!---=-o SE·

»
c

oc

C)

DI

•••:. I

...

I START I

I I

......

cCo)

14
DO

C)

."
C

~

n

15

SARS

0'
~
e!.

m

0'

CHO

n

~

CHI

C

CH2· CH3·

o-!
CHS· o!CH6· 02
8
CH4.~

~I

(+)
Odd

It

- ...

i'
Dl
3

CC
~

I(-)~

CH7·

COM

COM·
20
Vcc 0----+
To Internal
Circuitry
DGNOO 0 10

19
VREFOUJO

rh

r-;;

EOP

f-

Input ESO Protection Circuitry
cc

Channel
Inputs,
Pin 1-8

.

To
Internal
Circuits

Protection + c c
On All Other
To
Pins
Internal
Circuits
LSB First

VREFIN·
AGNO

~
11

MSB nrst

TL/H/l0555-'7

·Some of these functions/pins are not available with other options.

Nole 1: Forlhe ADC08034, the "SEL I" Flip-Flop is bypassed, for the ADC08032, both "SEL 0" and "SEL '" Flip-Flops are bypassed.

8£080:>OVIt£080:>OV1~£090:>OV1~£080:>OV

I

~

~c

~

C')

o

8
c
~
g
o

U
C

cc
......
.,...
C')

g

8c

cc

Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of these converters utilizes a comparator structure with built-in sample-and-hold which provides for a differential analog input to be converted by a successiveapproximation routine.
The actual voltage converted is always the difference between an assigned" + .. input terminal and a .. -" input terminal. The polarity of each input terminal of the pair indicates which line the converter expects to be the most positive. If the assigned" + .. input voltage is less than the" -"
input voltage the converter responds with an all zeros out,
put code.

differentially with any other channel. In addition to selecting
differential mode the polarity may also be selected. Channel
o may be selected as the positive input and channel 1 as
the negative input or vice versa. This programmability is
best illustrated by the MUX addressing codes shown in the
following tables for the various product options.
The MUX address is shifted into the converter via the 01
line. Because the ADC08031 contains only one differential
inputcl1annel with a fixed polarity assignment, it does not
require addressing.
The common input line (COM) on the ADC08038 can be
used as a pseudo-differential input. In this mode the voltage
on this pin is treated as the "-" input for any of the other
input channels. This voltage does not have to be analog
ground; it can be any reference potential which is common
to all of the inputs. This feature is most useful in single-supply applications where the analog circuity may be biased up
to a potential other than ground and the output signals are
all referred to this potential.

A unique input multiplexing scheme has been utilized to provide multiple analog channels with soitware-configurable
single-ended, differential, or pseudo-differential (which will
convert the difference between the voltage at any analog
input and a common terminal) operation. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.

T~BLE

A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differential. Differential inputs are restricted to adjacent channel
pairs. For example, channel 0 and channel 1 may be selected as a differential pair but channel 0 or 1 cannot act

Part
Number

I. Multiplexer/Package Options

Number of Analog Channels
Single-Ended

Differential

Number of
Package Plna

ADC08031

1

1

8

ADC08032

2

1

8

ADC08034

4

2

14

ADC08038

8

4

20

TABLE II. MUX Addressing: ADC08038
Single-Ended MUX Mode
MUXAddress
START

SGL/ .
DIF

ODD/
SIGN

Analog Single-Ended Channel #
SELECT
1

0

1

1

0

0

0

1

1

0

0

1

1

1

0

1

0

1

1

0

1

1

1

1

1

0

0

1

1

1

0

1

1

1

1

1

0

1

1

1

1

1

0

1

2

3

4

5

6

7

COM

-

+

-

+

-

+

-

+
+
.+

-

+
+

2-164

-

l>

Functional Description

o
oo

(Continued)

(X)

TABLE II. MUX Addressing: ADC08038 (Continued)

o
w
.....

Differential MUX Mode
MUXAddress
SELECT

SGL!
DIF

ODD!
SIGN

1

0

1

0

0

0

0

1

0

0

0

1

1

0

0

1

0

1

0

0

1

1

1

0

1

0

0

1

0

1

0

1

1

0

1

1

0

1

0

1

1

1

START

0

1

oo

3

2

(X)

0

1

+

-

2

+

SELECT

-

1

1

0

0

1

0

1

1

1

1

0

1

1

1

1

7

-

(X)

-

o

w

~
......

l>

o
-

o
o

+

(X)

+

-

2

o
w

(X)

TABLE IV. MUX Addressing:
ADC08032
Single-Ended MUX Mode
Channel #

MUXAddress

1

W

l>

+

-

0

o

o
oo

-

+

3

1

1

6

+

Channel #

ODD!
SIGN

5

+

MUXAddress
SGl!
DIF

4

3

N
......

TABLE III. MUX Addressing: ADC08034
Single-Ended MUX Mode

START

i>
o

Analog Differential Channel-Pair #

+
+

SGl! ODD!
START
DIF SIGN

1

1

0

1

1

1

+

0

1

+
+

COM is internally tied to AGND

+
COM is internally tied to AGND

Differential MUX Mode

Differential MUX Mode

SGl!
DIF

ODD!
SIGN

SELECT

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

START

MUXAddress

Channel #

MUXAddress
0

1

+

-

2

3

1

-

+

-

-

+

+

2·165

Channel #

SGl! ODD!
START
DIF SIGN

0

1

1

0

0

+

-

1

0

1

-

+

•

~

«:>

8
Q


co
«:>

(.)
Q


co
«:>

(.)
Q

~
....
CO)

«:>
co
«:>

(.)
Q

Functional Description

(Continued)
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate timing diagram is shown foi' each device.
1. A conversion is initiated by pulling the CS (chip select)
line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its
MUX assignment word.
2. On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register.
The start bit is the first logic "1" that appears on this line
(all leading zeros are ignored). Following the start bit the
converter expects the next 2 to 4 bits to be the MUX
assignment word.

Since the input configuration is under software control, it
can be modified as required before each conversion. A
channel can be treated as a single-ended, ground referenced input for one conversion; then it can be reconfigured
as part of a differential channel for another conversion. Figure 1 illustrates the input flexibility which can be achieved.
The analog input voltages for each channel can range from
50mV below ground to 50mV above Vee (typically 5V) without degrading conversion accuracy.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system improvements; it allows many functions to be included in a
small package and it can eliminate the transmission of low
level analog signals by locating the converter right at the
analog sensor; transmitting highly noise immune digital data
back to the host processor.



c

Functional Description

(Continued)
3. When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of % clock
period (where nothing happe:ls) is automatically inserted
to allow the selected MUX channel to settle. The SARS
line goes high at this time to signal that a conversion is
now in progre~s and the DI line is disabled (it no longer
accepts data).

The DI and DO lines can be tied together and controlled
through a bidirectional processor 1/0 bit with ope wire.
This is possible because the DI input is only "Iooked·at"
during the MUX addressing interval while the DO line is
still in a high impedance state.
3.0 REFERENCE CONSIDERATIONS
The voltage applied to the reference input on these convert·
ers, VREFIN, defines the voltage span of the analog input
(the difference between VIN(MAX) and VIN(MIN) over which
the 256 possible output codes apply. The devices can be
used either in ratiometric applications or in systems requir·
ing absolute accuracy. The reference pin must be connect·
ed to a voltage source capable of driving the reference input
resistance which can be as low as 1.3kO. This pin is the top
of a resistor divider string and capacitor array used for the
successive approximation conversion.

4. The data out (DO) line now comes out ofTRI·STATE and
provides a leading zero for this one clock period of MUX
settling time.
5. During the conversion the output of the SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of successive voltages gener·
ated internally from a ratioed capacitor array (first 5 bits)
and a resistor ladder (last 3 bits). After each comparison
the comparator's output is shipped to the DO line on the
falling edge of ClK. This data is the result of the conver·
sion being shifted out (with the MSB first) and can be
read by the processor immediately.

In a ratiometric system the analog input voltage is propor·
tional to the voltage used for the AID reference. This volt·
age is typically the system power supply, so the VREFIN pin
can be tied to VCC (done internally on the ADC08032). This
technique relaxes the stability requirements of the system
reference as the analog input and AID reference move to·
gether maintaining the same output code for a given input
condition.
For absolute accuracy, where the analog input varies be·
tween very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
For the ADC08034 and the ADC08038 a band·gap derived
reference voltage of 2.6V (Note 8) is tied to VREFOUT. This
can be tied back to VREFIN. Bypassing VREFOUT with a
100,..F capacitor is recommended. The lM385 and lM336
reference diodes are good low current devices to use with
these converters.
The maximum value of the reference is limited to the Vcc
supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow di·
rect conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sourc·
es when operating with a reduced span due to the in·
creased sensitivity of the converter (1 LSB equals VREFI
256).

6. After 8 clock periods the conversion is completed. The
SARS line returns low to indicate this '12 clock cycle later.
7. The stored data in the successive approximation register
is loaded into an internal shift register. If the programmer
prefers the data can be provided in an lSB first format
[this makes use of the shift enable (SE) control line). On
the ADC08038 the SE line is brought out and if held high
the value of the lSB remains valid on the DO line. When
SE is forced low the data is clocked out lSB first. On
devices which do not include the SE control line, the
data, lSB first, is automatically shifted out the DO line
after the MSB first data stream. The DO line then goes
low and stays low until CS is returned high. The
ADC08031 is an exception in that its data is only output in
MSB first format.
8. All internal registers are cleared when the CS line is high
and the tsELECT requirement is met. See Data Input Tim·
ing under Timing Diagrams. If another conversion is de·
sired CS must make a high to low transition followed by
address information.

r----------------1r--------t- 5Y

r---------~------~5Y

Vee

Yee

20kn
TRANSDUCER

~+-- +

ADC08D34 VREF IN

r-

t-_D_Y_.1_.2_5Y_-t+

ADC08038 YREFIN _

1.25V

~ ~LM385
AGNO

AGND

1
TLlH/l0555-19

a) Ratiometric

b) Absolute with a Reduced Span
FIGURE 2. Reference Examples

2·167

o
o

CD

o

(0)
.....
......

l>

c(')

o
CD
o

(0)

N
.......
l>

c

o
o

CD

o

(0)

0l:Io
.......
l>

c

o
o

CD

o

(0)

CD

m

C')

g

r--------------------------------------------------------------------------,

B
c

....cc
"'II'

C')
C)

!:
o
cc

c

....
N

C')
C)

m

C)

(.)

C

~
....
C')
C)

B
c
cc

Functional Description

(Continued)

4.0 THE ANALOG INPUTS

The zero error of the A/D converter relates to the location
of the first riser ofthe transfer function and can be measured by grounding the VIN (-) input and applying a small
magnitude positive voltage to the VIN (+) input. Zero error
is the difference between the actual DC input voltage which
is necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal % LSB value
(% LSB = 9.BmV for VREF = 5.000Voc).

The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling proces·
sor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accura·
cy which otherwise is most ,susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common·mode voltage.

5.2 Full Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1% LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the VREFIN input (or Vee for the ADCOB032) for a
digital output code which isjust changing from 1111 1110 to
1111 1111.

The differential input of these converters actually reduces
the effects of common·mode input noise, a Signal common
to both selected U+U and U_" inputs for a conversion
(SO Hz is most typical). The time interval between sampling
the +" input and then the u,--" input is % of a clock peri·
od. The change in the common·mode voltage during this
short time interval can cause conversion errors. For a sinus·
oidal common·mode signal this error is:
U

Verror(max)

5.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A VIN (+) voltage which
equals this desired zero reference plus % LSB (wher~ the
LSB is calculated for the desired analog span, using 1 LSB
= analog span/25S) is applied to selected u+" input and
the zero reference voltage at the corresponding" -" input
should then be adjusted to just obtain the OOHEX to 01HEX
code transition.

0.5 )
= VPEAK(21TfCM) ( -

fClK
where fCM is the frequency of the common·mode Signal,
VPEAK is its peak voltage value
and fClK is the AID clock frequency.
For a SOHz common·mode signal to generate a '14 LSB error (::::: 5mV) with the converter running at 250kHz, its peak
value would have to be S.S3V which would, be larger than
allowed as it exceeds the maximum analog input limits.

The full-scale adjustment should be made [with the proper
VIN (-) voltage applied] by forcing a voltage to the VIN (+)
input which is given by:

Source resistance limitation is important with regard to the
DC leakage currents of the input multiplexer. Bypass capacitors should not be used if the source resistance is greater
than 1kn. The worst-case leakage current of ± 1/LA over
temperature will create a 1mV input error with a 1kn source
resistance. An op amp RC active low pass filter can provide
both impedance buffering and noise filtering should a high
impedance signal source be required.

VIN ( + ) fs adj = VMAX - 1.5 [(VMAX - VMIN)]
,
256
where:
VMAX = the high end of the analog input range
and

5.0 OPTIONAL ADJUSTMENTS

VMIN = the low end (the offset zero) of the analog range.
(Both are ground referenced.)

5.1 Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not ground
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any VIN (-) input at this VIN(MIN) value. This
utilizes the differential mode operation of the AID.

The VREFIN (or Vce> voltage is then adjusted to provide a
code change from FEHEX to FFHEX. This completes the adjustment procedure.

2-1SB

»
c

Applications

o
o

OG

o

A "Stand·Alone" Hook·Up for ADC08038 Evaluation

w
......
.......

MIIX ADDRESS

;:===+===;:===1;:==:;""';0 SWoc

»

c
oo

_STAAT BIT

sn141

(X)

SGL/iiiF

o
w

.....
»
c
~

11

"

oo

NC

OG

INPUT SHIFT REGISTER

o

14C165

+-u-

W

START

.1:10
.....
»
c

DO

Vee
14

10
NC

SVoc

o
o

OG

o
w

OG
HOC

CLR

OUTPUT SHIFT REGISTER

14Cl54

QA

12

10

11

NSl51127(11
J1I274CJ4

L...-.....- -....- _....-

.sa

_-oSVDC

....._ _..._ _...._ .....

Lsa

DATA DISPLAV

'Pinouts shown for ADCOB03B.

For all other products tie to pin functions as shown.

Low·Cost Remote Temperature Sensor
Vee

ISVnc)

Vee

"INI+)

urn.

+
~100lf

ADCOB031

sUoc

,,.1

,,.

TA~b~ ':"

TAMAX

VREFIN

"'NH
GNQ

"OJ
":'

":'

TL/H/10555-21

2-169

CD
CO)

r---------------------------------------------------------------------------------~

~

....

Applications (Continued)
DIgitizing. Current Flow

011(

~
CO)

- _ _ ILDAD

0.1 ..

Vee
IIVDe)

Q

12A FULL·SCALE)

100

8
c

VI.I-)

Vee ~----....

i
g
~
....

I

· •• Ik

I.

------4

ZERO )0....
AD.I

lk
::"'oo...+I-"','F$
ADJ

12Il10

TLlH/10555-22

OperatIng

willi RIdIoinetric Transducers
Vee
(lVoe)

I.
..._C .......d-.....K: FSlk

VIIEf.~,.....
1.1 Vee

ADJ

14k

'VIN(-) = 0.15 Vee
.
15% 01 Vee .: VXDR .: 85% of Vee

2·170

TlIHIIOS55-23

:J>

c
oo

Applications (Continued)

CD

oCo)

Span Adjust; OV :;;; VIN :;;; 3V

.....
.....
:J>

c
oo

CD

.--0---1 VIN(+)

oCo)

veel-~~------.....,

I\)

l>
c
o
o

CD

oCo)
oIiIo
.....

:J>

c
oo

CD

oCo)

LM336

CD

Zero-Shift and Span Ad/ust: 2V :;;; VIN :;;; 5V
Vee
(5VDe)

vccl-~~---------'

.--o---!VIN(+)

•

I.Zk

----,I

ADCDBD31

r---:-=~.....I

I

I
I

LM336
SETS ZERO
CODE VOLTAGE

Z.7k

330

I

I

L _________ JI

Ik
ZVDC
ZERO AOJ

TUH/l0555-24

2-171

Applications (Continued)
Protecting the Input

High Accuracy Comparators
5V

Vee

15Voc)

Vee

+

Vee

SYSTEM
TEST
POINTS

- I6Voe

+

>-_-I~

}

1

TO
CONTROLLER

jAoC08038

ADC08032
VIH 3

DO ~ allIs if +VIN
DO ~ all Os if +VIN

GNo

COM

> -VIN
< -VIN

-=
TL/HI1 0555-26

Diodes are 1N914
TL/H110555-25

Digital Load Cell
330

TUH/l0555-27
• Uses Qne more wire than load cell itself
• Two mini-DIPs could be mounted inside load cell for digital oulputlransducer .

• Electronic offset and gain trims relax mechanical specs for gauge faCtor and offset
• low level cell output is converted immediately for high noise immunity

2-172

Applications (Continued)
4 mA-20 mA Current Loop Converter
lOOk

.50 kHz

lOp!'

INP
24k

6.2k

200k r---:Vc~e:---""
+IN

ClK

~"""'I--+--I-IN

CS t-----.....JVV'Ir--,

AOC08031

10k
DO I-~H.-+:"";W"",,"-Vee

5k >41--1---1 VREfIN

47k

3.9k

Vee
C04024

~----V'

300k

I...-----vo
.....- - - - - - G N D
• All power supplied by loop
• 1500V isolation at output

TL/H/l0555-2B

Isolated Data Converter
lN4148
~-""HIN""'-------_Vee OUT

10k

lN4148

CLJ(-'WI\r--I

fII
6V

'::"

elK

470

CS

Vee

Vee

~~

lOOk

'::"

ADC08038

10k
CS

01

lf1_.

CHANNELS

Vee

7.£-

DO
'::"

6.8k

10k
01
'::"

• No power required remotely
• 15DOV isolation

2·173

TLlH/l0555-29

:g

i

~

tflNational Semiconductor

;

ADC081311 ADC081341 ADC08138 8-Bit High-Speed
Serial 1/0 AID Converters with Multiplexer Options,
~ Voltage Reference, and Track/Hold Function
....

g
....
CD
B
c
CO)

cr:

General Description

Features

The ADC08131/ADC08134/ADC08138 are 8-bit successive approximation AID converters with serial I/O and' configurable input multiplexers with up to 8 channels. The serial
1/0 is configured to comply with the NSC MICROWIRETM
serial data exchange standard for easy interface to the
COPSTM family of controllers, and can easily interface with
standard shift registers or microprocessors.
All three devices provide a 2.5V band-gap derived reference
with guaranteed performance over temperature.
A track/hold function allows the analog voltage at the positive input to vary during the actual AID conversion.

• Serial digital data link requires few 110 pins
• Analog input track/hold function
• 4- or 8-channel input multiplexer options with address
logic
• On-chip 2.5V band-gap reference (±2% over temperature guaranteed)
• No zero or full scale adjustment required
• TIL/CMOS input/output compatible
• OV to 5V analog input range with single 5V power
supply

The analog inputs can be configured to operate in various
combinations of single-ended, differential, or pseudo-differential modes. In addition, input voltage spans as small as 1V
'
can be accommodated.

Applications
•
•
•
•

Digitizing automotive sensors
Process control/monitoring
Remote sensing in noisy environments
Embedded diagnostics

Ordering Information
Industrial

(-4IrC';;; TA ,;;; +85'C)

Key Specifications
8 Bits
Resolution
8,...s (Max)
Conversion time (fc = 1 MHz)
20 mW (Max)
Power dissipation
5 Voc (± 5%)
Single supply
±1f2 LSB and ± 1 LSB
Total unadjusted error
±1f2 LSB
Linearity Error (VREF = 2.5V)
No missing codes (over temperature)
On-board Reference
+ 2.5V ± 1.5% (Max)

•
•
•
•
•
•
•
•

Connection Diagrams
ADC08138

ADC08134

Dual-In-Llne and
Small Outline
Packages

Package

Dual-In-Llne and
Small Outline
Packages

ADC08131BIN, ADC08131CIN

N08E

ADC08134BIN,ADC08134CIN

N14A

CHO- I

ADC08138BIN, ADC08138CIN

N20A

CHI- 2
CH2- 3

19 t-VREF OUT
181-es

ADC08134BIWM, ADC08134CIWM

M14B

CH3- 4

171-DI

ADC08138BIWM, ADC08138CIWM

M20B

CH4- 5

161-ClK

CH5- 6

151-SARS

'--/
20 t-Vee

CH6- 7

141-DO

CH7- 8

13I-Sf

CON- 9

121-VREF IN

DGND- 10

VREF OUT- I
2
CHO- 3
CHI- 4
CH2- 5
CH3- 6
DGND- 7

cs-

'-"

14 t-Vee
131-DI
121-CLK
11 I-SARS
IDI-DO
9 I-VREF IN
81- AGND
TLlH/lD749-3

Iit-AGND
TL/H/l0749-2

ADC08131
Dual-In-Line Package
e s 0 8 vee
VIt(>27CLK
V,N-

3

6

DO

GND

4

5

VREF C

TL/H/I0749-4

2-174

Absolute Maximum Ratings

Operating Ratings

(Notes 1 & 3)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
Voltage at Inputs and Outputs
Input Current at Any Pin (Note 4)
Package Input Current (Note 4)

ADCOB134BIN, ADCOB134CIN,
ADCOB13BBIN, ADC08138CIN,
ADC08134BIWM, ADCOB13BBIWM,
ADCOB134CIWM, ADCOB138CIWM
Supply Voltage (Vee>

4.5 Voe to 6.3 Voe

800mW
1500V

Soldering Information
N Package (10 sec.)
SO Package:
Vapor Phase (60 sec.)
Infrared (15 sec.) (Note 7)
Storage Temperature

TMIN S; TA S; TMAX
-40'C S; TA S; +B5'C

ADCOB131 BiN, ADCOB131CIN,

6.5V
-0.3V to Vee + 0.3V
±5mA
±20mA

Power Dissipation at T A = 25'C (Note 5)
ESD Susceptibility (Note 6)

(Notes 2 & 3)

Temperature Range

260'C
215'C
220'C
-65'Cto + 150'C

Electrical Characteristics
The following specifications apply for Vee = +5 Voe, VREF = +2.5 Voe and feLK = 1 MHz unless otherwise specified.
Boldface limits apply for T A = T J = T MIN to T MAX; all other limits TA = TJ = 25'C.

Symbol

Parameter

Conditions

ADC08131,
ADC08134 and
ADC08138 with BIN,
CIN,BIWMor
CIWM Suffixes
Typical
(Note 8)

Units
(Limits)

Limits
(Note 9)

CONVERTER AND MULTIPLEXER CHARACTERISTICS

RREF

VIN

=

Linearity Error
BIN,BIWM
CIN,CIWM

VREF

Full Scale Error
BIN,BIWM
CIN,CiWM

VREF

Zero Error
BIN,BIWM
CIN,CIWM

VREF

Total Unadjusted Error
BIN,BIWM
CIN,CIWM

VREF = +5 Voe
(Note 10)

Differential Linearity

VREF

Reference Input Resistance

(Note 11)

Analog Input Voltage

+ 2.5 Voe
±~

±1

=

+ 2.5 Voe
±~

=

=

LSB(max)
LSB(max)

±1

LSB(max)
LSB (max)

±1
±1

LSB(max)
LSB (max)

±~

±1

LSB (max)
LSB (max)

8

Bits (min)

1.3
6.0

kO
kO (min)
kO(max)

(Vee + 0.05)
(GND - 0.05)

V (max)
V (min)

+ 2.5 Voe .

+ 2.5 Voe
3.5

(Note 12)

2·175

Electrical Characteristics (Continued) .
The following specifications apply for Vcc = + 5 Voc, VREF = + 2.5 Vee and felK = 1 MHz unless otherwise specified.
..
Bo.ldface Ilmlt.s apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 2~~C.

Symbol

Parsmeter

Conditions

ADC08131,
,
ADC08134 and
ADC08138 with BIN,
CIN,BIWMor
CIWM Suffixes
Typical
(Note 8)

Units
(Limits)

Limits
(Note 9)

CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)
DC Common·Mode Error
Power Supply Sensitivity
On Channel Leakage
Current (Note 13)

Off Channel Leakage
Current (Note 13)

= 2.5 Voc
Vee = +5V ±5%,
VREF = + 2.5 Voc
On Channel = 5V,
Off Channel = OV
On Channel = OV,
Off Channel = 5V
On Channel = 5V,
Off Channel = OV
On Channel = OV,
Off Channel = 5V
VREF

±%

LSB(max)

±%

LSB(max)

0.2
1

p.A(max)

-0.2
-1

.p.A(max)

-0.2
-1

/LA (max)

.0.2
1

p.A (max)

DIGITAL AND DC CHARACTERISTICS

= 5.25V
= 4.75V

VIN(1)

Logical "1" Input Voltage

Vee

VIN(O)

Logical "0" Input Voltage

Vee

IIN(l)

Logical "1" Input Current

VIN = 5.0V

IIN(O)

Logical "0" Input Current

VIN

VOUT(i)

Logical "1" Output Voltage

Vee = 4.75V:
lOUT"; - 360 /LA
lOUT = -10/LA

= OV

VOUT(O)

Logical "0" Output Voltage

Vee = 4.75V
lOUT = (6mA

lOUT

TRI·STATEI!> Output Current

VOUT
VOUT

ISOURCE

Output Source Current

ISINK

Output Sink Current

Icc

Supply Current
ADC08134, ADC08138
ADC08131 (Note 16)

= OV
= 5V
VOUT = OV
VOUT = Vee
CS = HIGH

2·176

2.0

V (min)

0.8

V (max)

1

,

-1

p.A (max)
/LA (max)

2.4
4.5.

V (min)
V (min)

0.4

V (max)

-3.0
3.0

: /LA (max)
/LA (max)

-8.5

mA(min)

8.0

mA(min)

3.0
8.0

mA(max)
mA(max)

Electrical Characteristics (Continued)
The following specifications apply for Vee = + 5 Voe and feLK
TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25'C.

Symbol

Parameter

= 1 MHz unless otherwise specified. Boldface limits apply for

Conditions

ADC08131,
ADC08134 and
ADC08138 with BIN,
CIN,BIWMor
CIWM Suffixes
Typical
(Note 8)

Limits
(Note 9)

ADC08134,
ADC08138

2.5
±2%

2.5 ±1.5%

ADC08131

2.5
±2%

2.5 ±1'.5%

Units
(Limits)

REFERENCE CHARACTERISTICS
VREFOUT

Output Voltage

aVREF/aT

Temperature Coefficient

aVREF/alL

Load Regulation
(Note 17)

Sourcing
(0 s: IL s: +4mA)
ADC08134,
ADC08138

Sinking
(-1 s: IL s:
ADC08134,
ADC08138
Sinking
(-1 s: IL s:
ADC08131
4.75V

Short Circuit Current

VREF = OV
ADC08134,
ADC08138

aVREF/at

Long Term Stability

0.1

0.003

0.1

%/mA
(max)

0.2

0.5

0.2

0.5

0.5

6

8

25'

8

25

a mAl

VREF = OV
ADC08131
Tsu

0.003

a mAl

s: Vee s: 5.25V

Line Regulation

Start-Up Time

ppm/'C

40

Sourcing
(0 s: IL s: +2 mAl
ADC08131

Ise

V

Vee:OV ....... 5V
CL = 100p.F

mA
(max)

20

ms

200

ppm/1 kHr

"

2-177

mV
(max)

fII

CD
C")
.-

CD

g
c(
....
~

C")

Electrical Characteristics (Continued)
The following specifications apply for Vcc =

+

+

2.5 Voc and tr = tf =
5 Voc, VREF =
Boldface limits apply for T A = T J = T MIN to T MAX; all other limits T A = T J = 25°C.

Symbol

Parameter

Conditions

.-

B
c

-B

fCLK

Clock Frequency

tSELECT

10

8
8

1/fCLK (max)

Acquisition Time

%

1/fcLK(max)

fCLK = 1 MHz

ClK High while -es is High
-es Falling Edge or Data Input

50

Data Input Valid after ClK
Rising Edge

tpdlo tpdO

ClK Falling Edge to Output

CL = 100pF:

Data Valid (Note 15)

Data MSB First
Data lSB First

tlH, tOH

kHz (min)

MUX Addressing Time)

Conversion Time (Not Including

Valid to ClK Rising Edge
tHOLO

Units
(Limits)

% (min)
% (max)

(Note 14)

tSET-UP

9)

40
60

Clock Duty Cycle

cc(

Limits
(Note

MHz (max)

.C")
.-

tCA

Typical
(Note 8)

1

c(

Tc

20 ns unless otherwise specified.

TRI-STATE Delay from Rising Edge

CL= 10pF,RL= 10k!}

of

(see TRI-STATE Test Circuits)

-es to Data Output and SARS Hi-Z

ns

25

ns(min)

20

ns(min)

250
200

ns(max)

50

ns(max)
ns

180

CL = 100 pF, RL = 2 k!}

/'oi\l(max)

ns(max)

CIN

Capacitance of logic Inputs

5

pF

COUT

Capacitance of logic Outputs

5

pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed
specifications and test condHions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
Note 3: Aif vollages are measured with respect to AGND = DGND = 0 Vee, unless otherwise specified.
Note 4: When the input voltage (YIN) at any pin exceeds the power supplies (Y,N < (AGND or DGND) or V,N > AVec,) the current at that pin should be limited to
5 mAo The 20 rnA maximum package Input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four

pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX' 8JA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po = (TJMAX - TAl/8JA or the number given in the Absolute Maximum Ratings, whichever is lower. For devices
with suffIXes BIN, CIN, BIJ, CIJ, BIWM, and CIWM TJMAX = 125'C. For devices wllh suffix CMJ, TJMAX = 150'C. The Iypicalthermal resistances (8JAl of these
parts when board mounted follow: ADC08131 wHh BIN and CIN suffixes 12O'C/W, ADC08134 with BIN and CIN suffixes 95'C/W, ADC08138 with BIN and CIN
suffixes 80'C/W. ADC08134 with BIWM and CIWM suffixes 140'C/W, ADC08138 with BIWM and CIWM suffIXes 91'C/W,
Note 6: Human body model, 100 pF capaCitor discharged through a 1.5 kG resistor.
Note 7: See AN450 "Surface Mounting Methods and Their Effect on Product ReliabilHy" or Unear Oala Book section "Surface Mount" for other methods of
soldering surface mount devices.
Note 8: Typicals are at TJ = 25'C and represent the most likely parametric norm.
Note 9: Guaranteed to National's AOOL (Average OutgOing OualHy Level).
Note 10: Total unadjusted error includes zero, full-soale,linearity, and multiplexer error. Total unadjusted error with VREF = .+5V only applies to the ADC08134
and ADC08138. See Note 16.
Note 11: cannot be tested for the ADC08131.
Note 12: For V,Ne _) ;;, V,Ne +) the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct
for analog input voltages one diode drop below ground or one diode drop greater than Vee supply. During testing at low Vee levels (e.g., 4.5V), high level analog
inputs (e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures. This will cause errors for analog inputs near full-scale. The specification
allows 50 mV forward bias of either diode; this means that as long as the analog V,N does not exceed the supply vollage by more than 50 mV, the output code will
be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 Vae to 5 Vae input voltage
range will therefore require a minimum supply voltage of 4.950 Vae over temperature variations, inHial tolerance and loading.
Note 13: Channel leakage current is measured aller a single-ended channel is selected and the clock is turned off. For off channel leakage current the following
two cases are considered: one, whh the selected channel tied high (5 Voel and the remaining seven off channels tied low (0 Vael, total current flow through the off
channels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured. The two
cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.
Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these
limits the minimum time the clock Is high or low must be at least 450 ns. The maximum time the clock can be high or low is 100 ",s.
Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to

allow for comparator response time.
Note 16: For the ADC08131 VREFIN is internally tied to the on chip 2.5V band-gap reference output; therefore, the supply current is larger because it includes the
reference current (700 p.A typical, 2 mA maximum).
Note 17: Load regulaHon test conditions and specifications for the ADC08131 differ from those of the ADC08134 and ADC08138 because the ADC08131 has the
on-board reference as a permanent load.

2-178

.-----------------------------------------------------------------------.~

c
o

ADC08138 Simplified Block Diagram

Q

co
....
....
(0)

»c

ClK

o

....~
~
c

Control and
Timing

01

(0)

I - - - - - - - - f o - - I K . SARS

oQ

CHO

co
....

CH1
CH2
CH3
CH4

(0)

Analog
Input
Multiplexer

co

DO

CH5
CH6
CH7

COM
Vee

DGND

AGND
TL/H/10749-1

fII

2-179

Typical Converter Performance Characteristics
Linearity Error VB
Reference Voltage
vee = 5 VDC
'CU< = 1 MHz
T. = 25CC

0.50

~

Iii'

a.
:!l

i!iD.25

Linearity Error VB
Temperature

Linearity Error VB
Clock Frequency
1.00
VREF = 2.5 VDC
Vee = 5 VDC

0.50

~

. ~ 0.75

~

0.25

~

~

§

VRl:F = 2.5V
'CLK = 1 MHz

3

~. 0.25

0

1

2

3

0.00
-55 -35-15 5 25 45 65 85 105125
TEMPERATURE (CC)

5

4

REfERENCE VOLTAGE (V)

' / -55CC
25CC

I I I

0.00

V
J!

,

15 0.50

r- f-

~

~

125CCI

g

~

I'..

0
250 500 750 1000 1250 1500 1750
ClOCK FREQUEIICY (kHz)

0

,

Power Supply Current VB
Temperature (ADC08138,
ADC08134)

Output Current VB
Temperature

12.0

I
~

II:
iil

1.5

'~ k

Vee

i

II

'we = 'MHz

....

-

~

-~

cs = "I"

f

2.5

30

1

25

III

20

I

',5

is

~
= 4.75V

Vee

1.0 .....

~0.5

= 5.25V

6

10

r--.

12.0

= 5V)

is'NK (VDC

is

.... 'i--hl

I'r--.~

~

1t 1.0

I I I

~0.5

TEIIPERATURE (CC)

-

I--'

r-

iil

Ir .,.-r-

Vee = 5V
5'
-55 -35-15 5 25 45 65 85 105125
TEIIPERATURE (CC)

I I I
0.0
-55 -35 -15 5 25 45 65 85 105 125

15

~

I I I I
IsoURCE (VDC = OV)

JT

Power Supply Current
Clock Frequency
vee = 5 VDC
TA = 25CC

VB

35

2.5

0.0
0

250 500 750 1Il00 1250 1500 1750
a.OCK FREQUENCY (kHz)
(NOTE 16)

Note: For ADC08131 add 'REF (Note 16)

TLlH110749-5

Typical Reference Performance Characteristics
Load Regulation
+5.0
I

+4.D

!

Ii!

+3.0
+2.0

SINKING

I

I
'I

+1.0
0.0

~-o.s

!:

J!

.

SE ="0"

DATA OUT (DO)

~~T

S£ TO
CONIROL
LS8
FIRST

OUTPUT

DO

'--'

7
6
(USB)

5

4

3

2

1

I.

0
(LSB)

·1

1

2

3

4

5

6

7
(USB)
TL/H/I0749-14

'Maka sura clock adga #18 clocks in the LSB before SE is taken low

8& ~ 80:>0"Itt ~ 80:>0"I ~ &~ 80:>0"

II

ADC081311ADC081341ADC08138
CLK

16

CS :

18

,

,

,

"

l

(;>01---------.

Sfo

»

c
oo

...
CD

DI

1

II

!

I~oo

W
CD

."
C
:J

()

L----f-+I-+I-II ~ SARS
Decode

-.

I

OJ

0'
()

I

CHO~

~

CHI~

c

Even

CH2° 0-

iii'

4

il

CH3° 0S
CH4° 06
CHso 07
CH6°
CH7*

ea

iii
3

Odd

OS

COli

CO..o

Vee

~
10

DGNOOO

vREFouro

0'
:J
!!.

EOP

Input [sO Protection Circuitry
To Internal
Circuitry

rJ.,

ee
Channel
To
; : Inputs,
Internal
Pin 1-8
Circuits

Protection
On All other+ e e
. To
Pins
Internal
Circuits

LSB First

v~=;:~~:~t::::jl::::::::::::::::::::___________________ ~1
TLlH/10749-15

'Some of these functions/pins are not available with other options.
Note 1: For the ADC08134. the "SEL I" Aip-Fiop is bypassed. For the ADC08131. VREFOUT and VREFIN are internally tied together.

l>

C

Functional Description

o
<:)

co
.....

1.0 MULTIPLEXER ADDRESSING

The design of these converters utilizes it comparator structure with built-in sample-and-hold which provides for a dif"ferential analog input to be converted by a successiveapproximation routine.

differentially with any other channel. In addition to selecting
differential mode the polarity may also be selected. Channel
o may be" selected as the positive input and channell as
the negative input or vice versa. This programmability is
best illustrated by the MUX addressing codes shown in the
following tables for the various product options.

The actual voltage converted is always the difference between an assigned" +" input terminal and a .. -" input terminal. The polarity of each input terminal of the pair indicates which line the converter expects to be the most positive. If the assigned" +" input voltage is less than the" -"
input voltage the converter responds with an all zeros output code.

The MUX address is shifted into the converter via the DI
line. Because the ADC08131 contains only one differential
input channel with a fixed polarity assignment, it does not
require addressing.
The common input line (COM) on the ADC08138 can be
used as a pseudo-differential input. In this mode the voltage
on this pin is treated as the" -" "input for any of the other
input channels. This voltage does not have to be analog
ground; it can be any reference potential which is common
to all of the inputs. This feature is most useful in single-supply applications where the analog circuity l'J'lay be biased up
to a potential other than ground arid the output signals are
all referred to this potential.

A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-configurable
single-ended, differential, or pseudo-differential (which will
convert the difference between the voltage at any analog
input and a common terminal) operation. The analog signal
conditioning required in t(ansducer-based data acquisition
systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.

TABLE I. Multiplexer/Package Options

A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differen-.
tial. Differential inputs are restricted" to adjacent channel
pairs. For example, channel 0 and channell may be selected as a differential pair but channel 0 or 1 cannot act

T~BLE

Part
Number

Number of Analog Channels
~ingle-Ended

Differential

Number of
Package Pins

ADC08131

1

1

8

ADC08134

4

2

14

ADC08138

8

4

20

II. MUX Addressing: ADC08138

Single-Ended MUX Mode
MUXAddress
SGL/
DIF

ODD/
SIGN

1

1

1

1

1

START

Analog Single-Ended Channel #
SELECT

1

0

0

0

0

0

0

1

1

0

1

0

1

1

0

1

1

1

1

1

0

0

1

1

1

0

1

1

1

1

1

0

1

1

1

1

1

0

1

2

3

4

5

6

7

-

+
+
+

+
+

+
+
+

2-185

COM

-

w
.....

....;

l>
C

g
co
....
w

"'"
);
o

o
<:)

co
.....
w

co

Functional Description (Continued)
TABLE II. MUX Addressing: ADC08138 (Continued)
Differential MUX Mode .
MUXAddress

Analog Differential Channel-Pair IF

0001 .

START

SGLI
OIF

1

0

0

1

1

0

0

0

0

+

-

SIGN

SELECT

1

0

0

0

1

,1

0

0

1

0

1

0

0

1

1

1

0

1

0

0

1

0

1

0

1

1

0

1

1

0

1

0

1

1

1

0

2

1

-

2

3

+

-

4

5

+

-

-

0001

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

-

-

+
,

SELECT

0

1

2

3

1

+
+
+
+
COM is internally tied

to AGND

Differentlai MUX Mode
Channel IF

MUXAddress
SGLI
OIF

0001

1

0

0

0

1

.0

0

1

1

0

1

0

1

0

1

1

SIGN

+

+

Channel IF

MUXAddress
SGLI
DIF

START

7

+

-

SIGN

6

+

TABLE III. MUX Addressing: ADC08134
Single-Ended MUX Mode

START

3

SELECT

0

1

+

-

2

3

+

-

-

+

1

2·186

-

+

r--------------------------------------------------------------------.>
C
Functional Description (Continued)
g
Since the input configuration is under software control, it
can be modified as required before each conversion. A
channel can be treated as a' single-ended, ground referenced input' for one conversion; then it can be reconfigured
as part of a differential channel for another conversion. Figure 1 illustrates the input flexibility which' can be achieved.
The analog input voltages for each channel can range from
50mV below ground to 50mV above Vee (typically 5V) without degrading conversion accuracy.

To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate timing diagram is shown for each device.
1. A conversion is initiated by pulling the CS (chip select)
line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its
MUX assignment word.
2. On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register.
The start bit is the first logic "1" that appears on this line
(all leading zeros are ignored). Following the start bit the
converter expects the next 2 to 4 bits to be the MUX
assignment word.

2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system improvements; it allows many functions to be included in a
small package and it can eliminate the transmission of low
level analog signals by locating the converter right at the
analog sensor; transmitting highly noise immune digital data
back to the host processor.

8 Single-Ended

8 Pseudo-Differential
+

+
CDMI-)

+

COM I-I

VaIAS-=-

J:

4 Differential

Mixed Mode

+

0.1

0.11

+1-)

2.3
2.3
4.5

6.7

+

-1+)
+

COM I-)

VIlAS-="

~

FIGURE 1. Analog Input Multiplexer Options for the ADC08138

2-187

TL/H/l0749-16

co
.....

Co)

.....
......

>
c

g

co
.....
Co)

01:00
......

>
c

g

co
.....
Co)
co

Functional Description (Continued)
3. When the 'start bit has been shifted into the start locatio'n
of the MUX 'register, the input channel has been assigned
and a conversion is about to begin .. An interVal of "h clock
period is automatically inserted to allow for sampling the
, ,analog input. TheSARS line goes high at the end of.this
time to signal that a conversion is,now in progress and
, the 01 line is disabled (it no longer accepts data).
4. The data out (DO) line now comes out of TRI-STATE and
provide~ 'a leading zero.
5. During the conversion'the output olthe SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of 'successive voltages gener" ated internally from a ratioed capaCitor array (fir'st 5 bits)
and a resistor ladder (last 3 bits). After each comparison
the comparator's output is shipped to the DO line on the
falling edge of ClK. This data is the result of the conversion being shifted out (with the MSB first) and can be
read by the processor immediately.
6. After 8 clock periods the conversion is completed. The
SARS line returns low to indicate, ~l1i,s V2 clock cycle later.
7. The stored data in the successive approximation register
is loaded into an internal shift register; If the programmer
prefers the data can be provided in an lSB first format
[this makes use of the shift enable (SE) control line). On
the ADC08138 the ~ line is brought out and if held'high
the value of the lSB remains valid on the DO line. When
SE is forced low the data is clocked out lSB first. On
devices which do not include the ~ control line, the
data, lSB first, is automatically shifted out the DO line
after the MSB first data stream. The DO line then goes
low and stays low until CS is returned high. The
ADC08131 is an exception in that its pata is only output In
MSB first format.
8. All internal registers are cleared 'when the CS line is high
and the tsELECT requirement is met. See Data Input Timing under TIming Diagrams. If another conversion is desired CS must make a high to low transition followed by
address information.
'

y

The 01 and DO lines can be tied together and controlled
through a:bidirectional processor '110 bit with one wire,
"-This is possible because the 01 input is only "looked-at"
during the MUX addressing interval :While the DO line is
, still'in a high impedance state.
.
,
•

I

.,

3.0 REFERENCE CONSIPERATIONS
The ,VREFIN pin on these, converters is the top of a rel3istor
divider string and capacitor array used ,for the su,ccessive
approximation conversion. The voltage applied to this reference input defines the voltage span of the analog input (the
difference between VIN(MAX) and VIN(MIN) over which the
256 possible' output codes apply). The reference source
must be capable, of driving the reference input resistance,
which can be as low as 1.3 kG.
For absolute accuracy, where the analog input varies between specific voltage limits; the reference input must be
biased with a stable voltage source: The ADC08134 and the
ADC08138 provide the output of a 2.5V band:gap reference
at VREFOUT. This voltage does not vary appreciably with
temperature, supply voltage, or load current (see Reference
Characteristics in the Electrical Characteristics tables) and
can be tied directly to VREFIN for an analog input span of OV
to 2.5V. This output can also be used to bias external circuits and: can therefore be used as the reference in ratiometric applications. Bypassing VREFOUT with a 100 p.F capaCitor is recommended.
For the ADC08131, the output af .the on-board reference is
internally:tied to the reference input. Consequently, the analog input span for this device is set at OV to 2.5V. The pin
VREFC is provided for bypassing purposes and biasing external circuits as suggested, above.
The maximum value' of the'reference is limited to the Vee
supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 lSB equals VREFI
256).

~--------------~~-------~

+5V

Vee
TRANSDUCER

I-_O_V-_2_.5_V-I +

+

ADC08134 VREfIN

ADC08138 VREFIN

t-'-

VREFOUT ~

=~

--

I
DGND

AGND,

1

1

-.
"

..l.
TLlH/l0749-18
TL/H/l0749-17

a) Ratlometrlc
FIGURE 2. Reference Examples

b) Absolute

»
c

g

Functional Description (Continued)
The zero error of the AID converter relates to the location
of the first riser of the transfer function and can be measured by grounding the VIN (-) input and applying a small
magnitude positive voltage to the VIN (+) input. Zero error
is the difference between the actual DC input voltage which
is necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal % LSB value
<'12 LSB = 9.8mV for VREF = 5.000Vocl.

4.0 THE ANALOG INPUTS
The most Important feature of these converters is that they"
can be located right at the analog signal source and through
just a few wires can communicate with a controlling processor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected "+" and "-" inputs for a conversion
(SO Hz is most typical). The time interval between sampling
the" +" input and then the" -" input is % of a clock period. The change in the common-mode voltage during this
short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is:

5.2 Full Scale
A full-scale adjustment can be made by applying a differential input voltage which is 1% LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the VREFIN input for a digital output code which is
just changing from 1111 1110 to 1111 1111 (See figure entitled "Span Adjust; OV :s; VIN :s; 3V"). This is possible only
with the ADC08134 and ADC08138. (The reference is internally connected to VREFIN of the ADC08131).

0.5 )
Verror(max) = VPEAK(2'ITfCM) ( fClK
where fCM is the frequency of the common-mode signal,
VPEAK is its peak voltage value
and fClK is the AID clock frequency.
For a SOHz common-mode signal to generate a % LSB er- .
ror (::::: 5mV) with the converter running at 250kHz, its peak
value would have to be S.S3V which would be larger than
allowed as it exceeds the maximum analog input limits.
Source resistance limitation is important with regard to the
DC leakage currents of the input multiplexer. While operating near or at maximum speed bypass capacitors should not
be used if the source resistance is greater than 1k!l. The
worst-case leakage current of ± 1/LA over temperature will
create a 1mV input error with a 1kO source resistance. An
op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance
signal source be required.
5.0 OPTIONAL ADJUSTMENTS
5.1 Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not ground
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biaSing any VIN (-) input at this VIN(MIN) value. This
utilizes the differential mode operation of the AID.

2-189

....cow
....
~

(")

o

co
....
w
~
C

9
co

....

w
co

5.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the AID is .shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A VIN (+) voltage which
equals this desired zero reference plus % LSB (where the
LSB is calculated for the desired analog span, using 1 LSB
= analog span/25S) is applied to selected" +" input and
the zero reference voltage at the corresponding" -" input
should then be adjusted to just obtain the OOHEX to 01 HEX
code transition.
The full-scale adjustment should be made [with the proper
VIN (-) voltage applied] by forcing a voltage to the VIN (+)
input which is given by:
VIN ( + ) fs adj = VMAX - 1.5 [(VMAX - VMIN)]
256
where:
VMAX = the high end of the analog input range
and
VMIN = the low end (the offset zero) of the analog range.
(Both are ground referenced.)
The VREFIN (or Vce! voltage is then adjusted to provide a
code change from FEHEX to FFHEX. This completes the adjustment procedure.

•

Applications
A "Stand-Alone" Hook-Up for ADC08138 Evaluation
MUX ADDRISS

-;:::===i===;:==~==:;-OHDC
_ITARTIIT

Slklt'

.,
IN'UT'SHlfT REGISTER

lctlU

.

••

!Voc

Ht-::--:t-o IV .,
OUTfUT SHIFT REGISTER

r4CIM

Go
IZ

n

10

IISLWI21111

'Pinouts shown for ADC08138.

I'IIMeJ.

For all other products tie to pin functions as shown.

~.=.---4~--~---G~A-TO-.-'P-'·O-y---4~--~----~,=
••-osvac

Low-Cost Remote Temperature Sensor

,!lUI

.....'31

...

.:;!; ".'
TL/HI10749-2'

2-190

.--------------------------------------------------------------------.~

c
oo

Applications (Continued)

.....
.....
......
C»

Protecting the Input

Co)

Vee

I~VDC)

~

c
o
o

15VDC

C»
.....
Co)

~
......

+

'I""'

~

c

o
o

ADC081J8

.....

C»
Co)

C»
eOM
Diodes are lN914

-=

GND

TL/H/l0749-22

Operating with Ratiometric Transducers

20k

vee

VXDR

(+5V)

vee

CHO

.I.+

lk
ZERO
ADJ
3k

-

VREF OUT

-

ADC08134

.I.+

10pF

100pF

VREF IN 1----6--<~

0.7 Vee

GND

'V'N(-) ~ 0.15 VREF
15% of VREF s; VXDR s; 85% of VREF

lk

F5
ADJ

+

I

3.9k

24k
1PF

TL/H/l0749-23

Span Adjust; OV ,;; V,N ,;; 3V
+5V

ADC08134

V,N(_)

TL/H/l0749-24

2-191

co

....

C')

r---------------------------------------------------------------------------------,

!

Applications (Continued)
Zero-Shlft and Span Adjust: 2V :s; VIN :s; 5V
+5V

....
co
8
C')

~....

ADCOBI38

....

C')

8
~

VIN(+)

VIN

COli

Sets Zero
Cod. Voltage

DGND

VREfOUTI-.....- -.....-......I
AGND

100pF

1 k.o.
330.0.
2VDC
Zero ADJ
TLlH/10749-25

2-192

»
c

o
o

tflNational Semiconductor

00
N

....
.....
(,)

ADC08231/ADC08234/ADC08238 8~Bit 2 J-LS Serial I/O
A/D Converters with MUX, Reference, and Track/Hold
Features
• Serial digital data link requires few I/O pins
• Analog input track/hold function
• 4- or 8-channel input multiplexer options with address
logic
II On-chip 2.5V band-gap reference (± 2% over temperature guaranteed)
,
iii No zero or full scale adjustment required
II TTL/CMOS input/output compatible
III OV to 5V analog input range with single 5V power
supply
,
II Pin compatible with Industry-Standards ADC0831/4/8

A track/hold function allows the,analog voltage at the positive input to vary during the actual AID conversion.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or pseudo-differential modes. In addition, input voltage spans as small as 1V
can be accommodated.

Applications
•
•
•
•
•
•
•

High-speed data acquisition
Digitizing automotive sensors
Process control/monitoring
Remote sensing in noisy environments
Disk drives
Portable instrumentation
Test systems

Key Specifications
ID Resolution
8 Bits
tlI Conversion time (fc = 4 MHz)
2 /oIos (Max)
III Power dissipation,
20 mW (Max)
c Single supply
5 Voc (±5%)
[] Total unadjusted error
±% l.SB and ±1 LSB
IJ Linearity Error (VREF = 2.5V)
±%LSB
I:J No misSing codes (over temperature)
I:J On-board Reference
+ 2.5V ± 1.5% (Max)

ADC08238 Simplified Block Diagram
eLK

01

'rCHO

jlJ;-----t----f:===,-I-Ir=:J

SARS

CHI
CH2
DO

CH3
CH4
CH5
CH6
CH7
COM

ci-l..:::r-....

Vee

DONO

AOND
TUH/ll015-4

2-193

n
o

00
N

(,)

General Description
The ADC08231/ ADC08234/ ADC08238 are 8-bit successive approximation AID converters with serial I/O and con- '
figurable input multiplexers with up to 8 channels. The serial
I/O is configured to comply with the NSC MICROWIRETM
serial data exchange standard for easy interface to the
COPSTM family of controllers, and can easily interface with
standard shift registers or, microprocessors.
Designed for high-speed/low-power applications, the devices are capable of a fast 2 /oIos conversion when used with a
4 MHz clock.
All three devices provide a 2.5V band-gap derived reference
with guaranteed performance over temperature.

»
c

~

»
c
n
o

00
N

(,)

00

:g
~

Ordering Information

o

Industrial
(-40'C ~ TA ~ +85"C)

Package

~
""II'

ADC08231 BIN, ADC08231 CIN

N08E, DIP

C'I

:g

ADC08234BIN, ADC08234CIN

N14A, DIP

o

ADC08234CIMF'

'0

~
.('I)

ADC08238BIN, ADC08238CIN

N20A, DIP

ADC08231 BIWM, ADC08231 CIWM

M14B,SO

ADC08234BIWM, ADC08234CIWM

M14B,SO

ADC08238BIWM, ADC08238CIWM

M20B,SO

('I)

~

c(

MTB24, TSSOP

Connection Diagrams
ADC08234
SO and DIP

ADC08238
SO and DIP
CHO

VREF OUT

1

14

cs

Vee

2

13

01

CHO

3

12

elK

CHI

4

11

SARS

CLK

CH2

5

10

DO

SARS

CH3

6

9

VREF IN

DGND

7

8

AGND

20

Vee

2

19

VREF OUT

CH2

3

·18

cs

CH3

4

17

01

CH4

5

16

CH5

6

15

CH6

7

14

DO

13

Sf

CHI

CH7

COW

9

12

VREF IH

DGHD

10

11

AGHD

TLlH/ll015-2

ADC08234
TSSOP

TLlH/ll015-1

ADC08231
DIP

fiO'"
2

VIN'

N/c
N/c

7

CLK

3

6

DO

GHD

4

5

VREF C

NC

2

NC

4

VIN -

5

HC
GND

N/c

23

N/c

Vee

13

HC

12

CLK

11

NC

SARS

4

21

DO

Vee

5

20

VREF. IN

VREF OUT

6

19

cs

TLlH/ll015-3

14

22

DI

ADC08231
SO

VIN'

24

2

CLK

VIN -

cs

I

AGHD
DGNO

CHO

CH3

CHI

CH2

N/c

N/c
N/c
N/c

N/c
N/c

TL/H/ll015-27

DO
HC
VREF C
TLlH/ll015-26

2·194

~

Absolute Maximum Ratings

(Notes 1 & 3)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
Voltage at Inputs and Outputs

±20mA
BOOmW

ESD Susceptibility (Note 6)
Soldering Information
N Package (10 sec.)
TSSOP and SO Package (Note 7):
Vapor Phase (60 sec.)
Infrared (15 sec.)
Storage Temperature

C

(")

ADCOB231 BIWM, ADCOB231 CIWM,

Q

CD

ADCOB234BIWM, ADCOB23BBIWM,

N

W

ADCOB234CIWM, ADCOB23BCIWM,
ADCOB234CIMF

1500V

.....

);:

ADCOB23BBIN, ADCOB23BCIN,

±5mA

Power Dissipation at T A = 25·C (Note 5)

CD
N
W

TMIN S; TA S; TMAX
-40·C S; T A S; + B5·C

ADCOB234BIN, ADCOB234CIN,

-0.3V to Vee + 0.3V

Package Input Current (Note 4)

o
Q

Temperature Range
ADCOB231 BIN, ADCOB231CIN,

6.5V

Input Current at Any Pin (Note 4)

C

Operating Ratings (Notes 2 &3)

Supply Voltage (Vecl

4.5 Voe to 6.3 Voe

~C
o
Q

CD

260·C

N

W
CD

215·C
220·C
-65·C to + 150·C

Electrical Characteristics
The following specifications apply for Vee = + 5 Voe, VREF = + 2.5 Voe and feLK = 4 MHz, RSource = 500 unless otherwise"
specified. Boldface limits apply for T A = TJ = T MIN to T MAX; all other limits T A = TJ = 25·C.

Symbol

Parameter

Conditions

ADC08231,
ADC08234 and
ADC08238 with BIN,
CIN,BIWM,
CIWM, or CIMF Suffixes
Typical
(Note 8)

Units
(Limits)

Limits
(Note 9)

CONVERTER AND MULTIPLEXER CHARACTERISTICS

RREF

Linearity Error
BIN,BIWM
CIN, CIMF, CIWM

VREF = +2.5 Voe

Gain Error
BIN,BIWM
CIN, CIMF, CIWM

VREF = +2.5 Voe

Zero Error
BIN,BIWM
CIN, CIMF, CIWM

VREF = + 2.5 Voe

Total Unadjusted Error
BIN,BIWM
CIN, CIMF, CIWM

VREF = +5 Voe
(Note 10)

Differential Linearity

VREF = + 2.5 Voe

Reference Input Resistance

(Note 11)

±%
±1

LSB (max)
LSB(max)

±1
±1

LSB(max)
LSB (max)

±1
±1

LSB(max)
LSB (max)

±1
±1

LSB(max)
LSB(max)

8

Bits (min)

1.3

kO
kO(min)
kO(max)

3.5

6.0
VIN

Analog Input Voltage

(Note 12)

. (Vee + 0.05)

(GND - 0.05)

2-195

V (max)
V (min)

•

Electrical Characteristics (Continued)
The following specifications apply for Vee = + 5 Voe, VREF = + 2.5 Voc and fCLK = 4 MHz, Rsource = 50n unless otherwise
spepified. B~ldfa~e limits apply for T A = TJ = T MI~ t~ T MAX; all other limits T A' = TJ = 25'C.

Symbol

Parameter

,?onditions

ADC08231,
ADC08234 and
ADC08238 with BIN,
CIN,BIWM,
CIWM, or CIMF Suffixes
Typical
(Note8)

"

Units
, (Limits)

Limits
(Note 9)

CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)
DC Common-Mode Error

VREF = +2.5 Voe

±Yz

LSB (max)

Power Supply Sensitivity

Vee = +5V ±5%,
VREF = +2.5 Voe

±%

LSB (max)

On Channel Leakage
Current (Note 13)

On Channel = 5V,
Off Channel = OV

0.2

On Channel = OV,
Off Channel = 5V

~0.2

On Channel = 5V,
Off Channel = OV

-0.2

On Channel = OV,
Off Channel '=5V

0.2

"

Off Channel Leakage
Current (Note 13)

1
-1
-1

1

/J-A{max)
/J-A{max)
/J-A{max)

IJ.A (max)

DYNAMIC CHARACTERISTICS (see Typical Converter Performance Characteristics)
S
N+D

Signal-to- '
(Noise + Distortion)
Ratio

VREF = +5V
Sample Rate = 286 kHz
VIN ~ +5 Vp_p
fiN = 10 kHz

48.35

dB

. fiN = 50 kHz

48.00

dB

47.40

dB

fiN = 100 kHz
DIGITAL AND DC CHARACTERISTICS

,

VIN(l)

Logical "1" Input Voltage

Vee:: 5.25V

2.0

V (min)

VIN'(O)

Logical "0" Input Voltage

Vee = 4.75V

o.a'

V (max)

IIN(l)

Logical "1 " Input Curr~nt

VIN = 5.0V

1

IJ.A (max)

IINCO)

Logical "0" Input Current

VIN

-1,

/J-A{max)

VOUT(l)

Logical "1" Output Voltage

= OV
Vee = 4.75V:
lOUT = - 360 /J-A
lOUT = -l0/J-A

2.4
4.S

V (min)
V (min)

0.4

V (max)

VOUT(O)

Logical "0" Output Voltage

Vee = 4.75V
lOUT = 1.6 mA

lOUT

TR,I-STf\ TEl!> C,Jtput Current

VOUT = OV
VOUT = 5V

,-;-3.0
3.0

IJ.A (max)

ISOUReE

Output Source Current

VOUT = OV

-6.S

mA{min)

ISINK

Output Sink Current

VOUT = Vee

8.0

mA{min)

Icc

Supply Current
ADC08234, ADC08238
ADC08231 (Note 16)

CS = HIGH

3.0
6.0

mA{max)
mA{max)

2-196

/J-A{max)

Electrical Characteristics (Continued)
The following specifications apply for Vee = + 5 Voc and fCLK
TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25'C.

Symbol

Parameter

= 4 MHz unless otherwise specified. Boldface limits apply for

Condition:;

ADC08231,
ADC08234 and
ADC08238 with BIN,
CIN,BIWM,
CIWM, or CIMF Suffixes
Typical
(Note 8)

Limits
(Note 9)

2.5
±2%

2.5 ±1.5%

2.5
±3.5%

2.5 ±3.0%

Units
(Limits)

REFERENCE CHARACTERISTICS
VREFOUT

Output Voltage

BIN,BIJ,
BIWM
CIN,CIJ,
CIWM,CMJ

AVREF/AT

Temperature Coefficient

AVREF/AIL

Load Regulation
(Note 17)

40
Sourcing
(0 ~ IL ~ +4 rnA)
ADC08234,
ADC08238
Sourcing
(0 ~ IL ~ +2mA)
ADC08231
Sinking
(-1 ~ IL ~ 0 mAl
ADC08234,
ADC08238
Sinking
(-1 ~ IL ~ 0 rnA)
ADC08231

Isc

Line Regulation

4.75V ~ Vee ~ 5.25V

Short Circuit Current

VREF = OV
ADC08234,
ADC08238
VREF = OV
ADC08231

Tsu

Start-Up Time

AVREF/At

Long Term Stability

V

VCc:OV 5V
CL = 100 p.F

2-197

ppml"C

0.003

0.1

0.003

0.1

%/mA
(max)

0.2

0.5

0.2

0.5

0.5

6

8

25

8

25

mV
(max)

mA
(max)

20

ms

200

ppm/1 kHr

•

co
CO)
('II

co

o

(.)

c

«
......

Electrical Characteristics

(Continued)
The following specifications apply 'for Vcc = + 5 VDC, VREF = + 2.5 VDC and tr = tf = 20 ns unless otherwise specified.
Boldface limits apply for TA = TJ = TMIN toTMAX; all other IimitsTA = TJ ='25'C.

"0:1'

Symbol

CO

fCLK

CO)
('II

o

Conditions

Parameter
Clock Frequency

Typical
(Note 8)

c
.....
CO)
('II

Clock Duty Cycle
(Note 14)

c

«

4

kHz (min)
MHz (max)

40
60

% (min)
% (max)

8
2

1/fCLK (max)
/A-~(max)

1%

1/fCLK(max)

Tc

Conversion Time (Not Including
MUX Addressing Time)

tCA

Acquisition Time

tSELECT

ClK High while CS is High

tSET-UP

CS Falling Edge or Data Input
Valid to ClK Rising Edge

25

ns(min)

tHOLD

Data Input Valid after ClK
Rising Edge

20

ns(min)

tpdl, tpdo

ClK Falling Edge to Output
Data Valid (Note 15)

CL = 100 pF:
Data MSB First
Data lSB First

250
200

ns (max)
ns (max)

tlH, tOH

TRI-STATE Delay from Rising Edge
of CS to Data Output and SARS Hi-Z

CL = 10 pF, RL = 10 kO
(see TR I-STATE Test Circuits)

CIN

Capacitance of logic Inputs

5

pF

COUT

Capacitance of logic Outputs

5

pF

CO

o

(.)

Units
(Limits)

10

(.)

«
......

Limits
(Note 9)

fCLK = 4 MHz

ns

50

50

ns

180

CL = 100 pF, RL = 2 kO

ns(max)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed
specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed, Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to AGND = DGND = 0 Voe, unless otherwise specified.

Note 4: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < (AGND or DGND) or VIN > AVec.) the current at that pin should be limited to
5 rnA. The 20 rnA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 rnA to four
pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX' (}JA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po = (TJMAX - TA)/(}JA or the number given in the Absolute Maximum Ratings, whichever is lower. For devices

with suffixes BIN. CIN. BIJ. CIJ, BIWM. and CIWM TJMAX ~ 125°C. For devices with suffix CMJ, TJMAX ~ 150°C. The typical thermal resistances (OJA) of these
parts when board mounted follow; ADC08231 with BIN and CIN suffixes 120°C/W. ADC08234 with BIN and CIN suffixes 95°C/W. ADC08234 with CIMF suffix
167°C/W. ADC08238 with BIN and CIN suffixes 80°C/W. ADC08231 with BIWM and CIWM suffixes 140°C/W. ADC08234 with BIWM and CIWM suffixes 140"'C/W.
ADC08238 with BIWM and CIWM suffixes 91°C/W.
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kf! resistor.
Note 7: See AN450 "Surface Mounting Methods and Their Effect on Product Reliability" or Linear Data Book section "Surface Mount" for other methods of
soldering surface mount devices.
Note 8: Typicals are at TJ = 25°C and represent the most likely parametric norm.

Note 9: Guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 10: Total unadjusted error includes zero, full-scale, linearity, and multiplexer error. Total unadjusted error with VREF = + 5V only applies to the ADC08234
and ADC08238. See Note 16.
Note 11: Cannot be tested for the ADC0823t.
Note 12: For VIN(~) <: VIN(+) the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct
for analog input voltages one diode drop below ground or one diode drop greater than Vee supply. During testing at low Vee levels (e.g., 4.5V), high level analog
inputs (e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures. This will cause errors for analog inputs near full-scale. The specification
allows 50 mV forward bias of either diode; this means that as long as the analog VIN does rQt exceed the supply voltage by more than 50 mV, the output code will
be correct. Exceeding this range on ar, unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 Voe to 5 Voe input voltage
range will therefore require a minimum supply voltage of 4.950 Voe over temperature variations, initial tolerance and loading.
Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following
two cases are considered: one, with the selected channel tied high (5 Vod and the remaining off channels tied low (0 Vod, total current flow through the off
channels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured. The two
cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.
Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these
limits the minimum time the clock is high or low must be at least 120 ns. The maximum time the clock can be high or low is 100 JAs.
Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to
allow for comparator response time.
Note 16: For the ADC08231 VREF'N is internally tied to the on chip 2.5V band-gap reference output; therefore, the supply current is larger because it includes the
reference current (700 JAA typical, 2 rnA maximum).

Note 17: Load regulation test conditions and specifications for the ADC08231 differ from those of the ADC08234 and ADC08238 because the ADC08231 has the
on-board reference as a permanent load.

2-19B

l>

c
oo

Typical Performance Characteristics

Q)

N

....

Co)

Linearity Error vs
Reference Voltage
D.5O

~

~

I1:

025

Linearity Error vs
Temperature

o.so

vee = 5 VDC
fClJ( = 4MHz
TA = 250C

1.00

~

'"51

"-

15

~

0

2

I

3

4

5

3.0

~

~

......

-

Y~=5!25V
r.. r.. lt"'--- :- r-- N....
2.0
Vee-4.75V

15

II!

i3
5

5

1.5

15

]:

0

0

~

"-

I

.... r+4-L

.......... -.(

10

'soURCE (VDC =

~

It

3

4

5

Vee=5V
CS="I"
TA =25OC

-

2.25

~

2.DO

15 1.75

l.so

0

I

TEMPERAtuRE (OC)

~

~

Spectral Response with
50 kHz Sine Wave Input

Rs =50n

VIN = +5V p_ p (Max)
TA = 25°C
VCC =V R£r=+5V
felK = 4.0 101Hz
Sampling Rat.
286kHz
S/(N + 0) = 4B.35 dB

=

,

!
~

~

-100

20
10
0
-10
-20
-3,

20

40

60

80 100

8

7

9

- ,..

2

3

4

5

6

f2Q

-40

VCC=VREr=+5V

0;-

~

,
0

20

FREQUENCY (kHz)

40

o

fClK =4.0 MHz
Sampling Rat.
=286kHz
S/(N + D)= 48.00 dB

-60

140

~~

=

-50
-70
-80
-90

Spectral Response with
100 kHz Sine Wave Input

Rs =50n
VIN +5V p_p (Max)
1,,=25OC

-100

0

6

TL/H/ll015-5

Spectral Response with
10 kHz Sine Wave Input

0;~

~

CLOCK FREQUENCY (MHz)
(NOTE 16)

Note: For ADC08231 add IREF (Note 16)

20
10
0
-10
-20
-30
-40
-50
-6'
-70
-80
-90

Q)

~

T

5
-55 -35-15 5 25 45 65 85 105 125

TEMPERAtuRE (OC)

2

I

~

DV)

J I I I I

Yee = 5V
1.0
-55-35 -15 5 25 45 65 85 105125

]:

I I I I

15

oo

Power Supply Current
vs Clock Frequency

ISINK (VDC = 5V)

20

C

CLOCK FREQUENCY (MHz)

2.50

25

l>

V

N

Output Current vs
Temperature
30

~~

,/

0.00

35

fClJ(=4MHz
CS="I"

2.5

~

TEMPERAtuRE (OC)

Power Supply Current vs
Temperature (ADC08238,
ADC08234)

Co)

.....
"'"

!25OC

D.25

0.00
-55 -35-15 5 25 45 65 85 105 125

REFERENCE VOLTAGE (v)

I

;

III

0.00

250C

I1: o.so

VR... = 2.5V
fClJ( = 4MHz

::J

=
N

I

~

--

0.25

1:

i;
C
oo

~55'::

Vee=5V
VREF = 2.5~DC

lii' 0.75

lii'

;

]:

Linearity Error vs
Clock Frequency

60

80 100 120 140

~

I

-10

Rs= 50n
YIN = +5Yp_p (Wax)
T =25OC

A

~CCLCK~:~~F"=H:

5V
-20
-30 Sampling Rate 286 kH: ' - - I--

=

-40 S/(N + 0) = 47.40 dB
-50
-60

-70
-80
-90
-100
0

20

40

6.

80 100 120 140

FREQUENCY (kHz)

FREQUENCY (kHz)

Signal-to-Noise + Distortion
Ratio vs Input Frequency
60

~

50

rt-r-

40

enl!

I-Nyqulst
Frequenc

I
I
I

30

Vee = VREr = +5.QV :

20 f CLK =4.Hz 11111
0

TA=250 C
VIN = +5V p_p

10

II :
I

I

100

1000

INPUT fREQUENCY (kHz)

TL/H/110t5-6

2-199

Typical Reference Performance Characteristics
Output DrlH

Line Regulation
(3 Typical Parts)

Load Regulation

vs Temperature
(3 Typical Parte)

+~o

!
I:!

..

I

I

+~o

I

+3.0

SINKING

+2.0

,

10 mY

I

+1.0
0.0

>fII. ~.5

~

::..:
II

I

-1.0

-2
-3
-4

SOURCING

-I.S
-~o

-

. r-

f

....

-

~

""""

'"

....t-o...

"

-~

6

5

4

3

2

I

0

~

~

~

-75

2345678

SOURCING
SINKING
OUTPUT CURRENT (mA)
(NOTE 17)

SUPPLY VOLTAGE

20
18

; ::
5

8

J!,

6

iii

75

125

JUNCnON TEMPERATURE

Available
Output Current
vs Supply Voltage

1 ~:

-25 0 25

,

I

V

,V
SUPPLY VOLTAGE

TL/H/11015-7

2-200

~-------------------------------------------------------------------.~

c

TRI-STATE Test Circuits and Waveforms

n
Q
(II)

N

.....
......
Co)

Vee

~

DDAND
SARS OUTPUTS

c

n
Q

i11H

GND,

(II)

VDII---...,j~O%

N

Co)
.j:Io

......

GNO-------'=

~

c

n
Q

#
tOH

vee

CS

N

Co)
(II)

Rlvee

GND

DATA
OUTPUT

tOH

el~

':"

(II)

tOH

,

DO AND Vee

~

--

SARS OUTPUTS

10%
VOL

.

TL/H/ll015-8

TL/H/ll015-9

Timing Diagrams
Data Input Timing
ClK

---.I

DATA _ _ _ _ _ _~I

IN(DI~

TL/H/ll015-10

'To reset these devices, elK and CS must be simultaneously high fo; a period of !sELECT or gre,ater.

Data Output Timing
elK

DATA
OUT 1001

TL/H/ll015-11

ADC08231 Start Conversion Timing
ClK _ __

START

CONVERSION

DO----------------------~~----~

2-201

BIT7
(MSB)

TL/H/ll015-12

eX)
(')
('II
eX)

o

Timing Diagrams (Continued)

o
C

ADC08231 Timing

o

SE'

l>
C

oo

01

I

!

II

1~1lo

CO
N
W
CO
."

c:

::l

n

L..-----i-+I...I--II ~ SARS
Decode

. CHO
'CHI
CH2'
CH3'
CH4'

~I

1
02
0.3
04
0S
0S

0'
!!.
::l

m

P--"-"I

0'

~I

n

~

Even

C

iii'

CC

DJ

., Odd

3

CHS' 07
CHS' 08

CH7'

COM

EOP

COM'
Vcc

~ To Int.rnal
Circuitry

10

OGND* 0

rf,

f=-

Input ESO Protection Circuitry
cc

Channel'
Inputs,'
Pin 1-8

-

,,,'
To
Internal
Circuits

Protection ~cc
'
On All Other
To
Pins
Intemal
Circuits
,
'

VREFOUT*

LSB First

VRE:~:; ~ 1211

1

1

MSB First

TUH/ll015-16

·Some of these functions/pins are not available with other options.
Note 1: For the ADC08234, the "SELl" Flip·Flop is bypassed. For the ADC0823l, VREFOUT and VREFIN are internally lied together.

Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of these converters utilizes a comparator structure with built-in sample-and-hold which provides for a differential analog input to be converted by a successiveapproximation routine.
The actual voltage converted is always the difference between an assigned U+" inputterminal and a U_" input terminal. The polarity of each input terminal of the pair indicates which line the converter expects to be the most positive. If the assigned U+" input voltage is less than the U-"
input voltage the converter responds with an all zeros output code.

' differentially with any other channel. In addition to selecting
differential mode the polarity may also be selected. Channel
o may be selected as the positive input and channel 1 as
the negative input or vice versa. This programmability is
best illustrated by the MUX addressing codes shown in the
following tables for the various product options.
The MUX address is shifted into the converter via the DI
line. Because the ADC08231 contains only one differential
input' channel with a fixed polarity assignment, it does not
require addressing.
The common input line (COM) on the ADC08238 can be
used as a pseudo-differential input. In this mode the voltage
on this pin is treated as the U-" input for- any of the other
input channels. This voltage does not have to be analog
ground; it can be ani reference potential which is common
to all of the inputs. This feature is most useful in single-supply applications where the analog circuitry may be biased up
to a potential other than groLind and the output signals are
all referred to this potential.

A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-configurable
single-ended, differential, or pseudo-differential (which will
convert the difference between the voltage at any analog
input and a common terminal) operation. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.

TABLE I. Multiplexer/Package Options

A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the" analog inputs are to be
enabled and whether this input is single-ended or differential. Differential inputs are restricted to adjacent channel
pairs. For example, channel O,and channel 1 may be selected as a differential pair but channel 0 or 1 cannot act

Part
Number

Number of Analog Channels
Single-Ended

Differential

Number of
Package Pins

1

1

8

ADC08234

:4

2

14

ADC08238

8

4

20

ADC08231

TABLE II. MUX Addressing: ADC08238
Single-Ended MUX Mode
Analog Single-Ended Channel #

MUXAddress
START
1

SGLI
DIF

ODD/
SIGN

1

SELECT
1

0

0

0

0

1

1

0

0

1

1

1

0

1

0

1

1

0

1

1

1

1

1

0

0

1

1

1

0"

1

1

1

1

1

0

1

1

1

1

1

0

1

2

3

4

5

6

7

-

+
+
+
+

-

+
+
+
+

2-205

COM

-

Functional Description (Continued)
TABLE II. MUX Addressing: ADC08238 (Continued)
Differential MUX Mode
Analog Differential Channel-Pair II.

MUXAddress
SGLI
DIF

0001

SELECT

SIGN

1

0

0

1

1

0

0

0

0

+

-

1

0

0

0

1

1

0

0

1

0

1

0

0

1

1

1

0

1

0

0

1

0

1

0

1

1

0

1

1

0

1

0

1

1

1

START

1

0

2

2

4

3

"

+

-

-

-

-

+

+
-

MUXAddress

+

Channel #

SGL/
DIF

0001

SELECT

SIGN

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

0

1

2

3

+
+
+
+
COM is internally tied to AGND

Differential MUX Mode
Channel #

MUXAddress
SGL/
DIF

0001

SELECT

SIGN

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

START

+
+

TABLE III. MUX Addressing: ADC08234
Single-Ended MUX Mode

START

7

6

,

+

-

3

5"

2-206

0

1

+

-

-

,2

3

+,

-

-,

+

+

.--------------------------------------------------------------------.~

Functional Description

c

(Continued)

Since the input configuration is under software control, it
can be modified as required before each conversion. A
channel can be treated as a single·ended, ground refer·
enced input for one conversion; then it can be reconfigured
as part of a differential channel for another conversion. Fig·
ure 1 illustrates the input flexibility which can be achieved.
The analog input voltages for each channel can range from
50mV below ground to 50mV above Vee (typically 5V) with·
out degrading conversion accuracy.

To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate timing diagram is shown for each device.
1. A conversion is initiated by pulling the CS (chip select)
line low. This line must be held low for the entire conver·
sion. The converter is now waiting for a start bit and its
MUX assignment word.
2. On each rising edge of the clock the status of the data in
(01) line is clocked into the MUX address shift register.
The start bit is the first logic "1" that appears on this line
(all leading zeros are ignored). Following the start bit the
converter expects the next 2 to 4 bits to be the MUX
assignment word.

2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the contrOlling processor. Using a serial
communication format offers two very significant system im·
provements; it allows many functions to be included in a
small package and it can eliminate the transmission of low
level analog signals by locating the converter right at the
analog sensor; transmitting highly noise immune digital data
back to the host processor.

8 Single-Ended

8 Pseudo-Differential
+

+

+
+
+

. CDM(-)

VaIAS-=-

J

4 Differential

Mixed Mode

D.ll

0.1

2.3
2.3
4.5
6.7

-(+J
+(-J
-(+J

+

CDM(-J

ValAs-=-

~

, FIGURE 1. Analog Input Multiplexer Options for the ADC08238

2-207

TL/H/ll015-17

n
o

c»

N

........
(0)

~

c

n

o
c»
i\:)
(0)

.....co.
~
no

c»

N

(0)

c»

Functional Description (Continued)
3. When the start bit has been shifted into the start location
'of the MUX register, the input channel has been aSSigned
and a conversion is about to begin .. An interval of 1%
clock periods is automatically inserted to allow for sampling the analog input. The SARS line goes high at the
end of this time to Signal that a conversion is now in progress and the 01 line is disabled (it no longer accepts
data).

This is possible because the 01 input is only "looked-at"
during the MUX addressing interval while the DO line is
still in a high impedance state.
'
3.0 REFERENCE CONStDERATIONS
The VREFIN pin on these converters, is the top ,of a resistor
divider string and capacitor array use~ for the sflccessiv~
approxiniation conversion. The voltage applied to this reference input defines the' voltage span of the analog input (the
difference between VIN(MAX) and VIN(MIN) over which the
256 possible output codes apply). The reference source
must be capable of driving the reference input resi$nce,
which can be as low as 1.3 kfi.

4. The data out (DO) line now comes out of TRI-STATE and
, provides a leading zero.
5. During the conversion the output of the SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of successive voltages generated internally from a ratioed capacitor array (first 5 bits)
and a resistor ladder (last 3 bits). After each comparison
the comparator's output is shipped to the DO line on the
falling edge of ClK. This data is the result of the conversion being shifted out (with the MSB first) and can be
read by the processor immediately.
6. After 8 clock periods the conversion is completed. The
SARS line returns low to indicate this % clock cycle later.
7. The stored data in the successive approximation register
is loaded into an internal shift register. If the programmer
prefers, the data can be provided in an lSB first format
[this makes use of the shift enable (SE) controllinel. On
the ADC08238 the SE line is brought out and if held high
the value of the lSB remains valid on the DO line. When
~ is forced low the data is clocked out lSB first. On
devices which do not include the SE control line, the
data, lSB first, is automatically shifted out the DO line
after the MSB first data stream. The DO line then goes
low and stays low until CS is, returned high. The
ADC08231 is an exception in that its data is only output in
MSB first format.
8. All internal registers are cleared when the CS line is high
and the tsELECT requirement is met. See Data Input Timing under Timing Diagrams. If another conversion is desired CS must make a high to low transition followed by
address information.

For absolute accuracy, where the analog input varies between specific voltage limits, the reference input must be
biased with a stable voltage source. The ADC08234 and the
ADC08238 provide the output of a 2.5V band-gap reference
at VREFDUT. This voltage does not vary appreciably with
temperature, supply voltage, or load current (see Reference
Characteristics in the Electrical Characteristics tables) and
can be tied directly to VREFIN for an analog input span of OV
to 2.5V. This output can also be used to bias external circuits and can therefore be used as the reference in ratiometric applications. Bypassing VREFOUT with a 100 /LF capaCitor is recommended.
For the ADC08231, the output of the on-board reference is
internally tied to the reference input. Consequently, the analog input span for this device is set at OV to 2.5V. The pin
VRE~ is provided for bypassing purposes and biasing external circuits as suggested above.
The maximum value of the 'reference is limited to the Vee
supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 lSB equals VREFI
256).

The 01 and DO lines can be tied together and controlled
through a bidirectional processor 1/0 bit with one wire.

y

~---------------'----------SV

+5V

Vee

vee
TRANSDUCER

+

ADC08234

vREF IN
VREF OUT

- -

t-_O_V-_2_.S_V-.

~

+

ADC08238 VREF IN

- =:;

VREF OUT

I'00PF

DGND

1

AGND

--

J

-.L
TLlH/ll015-19
TL/H/ll015-18

b) Absolute

a) Ratlometric
FIGURE 2. Reference Examples
2-208

Functional Description

(Continued)
The zero error of the AID converter relates to the location
of the first riser of the transfer function and can be measured by grounding the VIN (-) input and applying a small
magnitude positive voltage to the VIN (+) input. Zero error
,is the difference between the actual DC input voltage which
is necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal % LSB value
(% LSB = 9.8mV for VREF = 5.000Vocl.

4.0 THE ANALOG INPUTS
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling proces·
sor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accura·
cy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.

5.2. Full Scale
A full·scale adjustment can be made by applying a differential input voltage which is 1% LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the VREFIN input for a digital output code which is
just changing from 1111 1110 to 1111 1111 (See figure entitled "Span Adjust; OV ,;;; VIN ,;;; 3V"). This is possible only
with the ADC08234 and ADC08238. (The reference is internally connected to VREFIN of the ADC08231).

The differential input of these converters actually reduces
the effects of common· mode input noise, a signal common
to both selected "+" and "-" inputs for a conversion
(60 Hz is most typical). The time interval between sampling
the" + .. input and then the" -" input is % of a clock period. The change in the common-mode voltage during this
short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is:

5.3 Adjusting for an Arbitrary, Analog Input
Voltage Range

0.5 )
Ver,o,(max) = VPEAK(21TfCM) ( fClK

If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A VIN (+) voltage which
equals this desired zero reference plus % LSB (where the
LSB is calculated for the desired analog span, using 1 LSB
= analog span/256) is applied to selected "+" input and
the zero reference voltage at the corresponding" -" input
should then be adjusted to just obtain the OOHEX to 01 HEX
code transition.
The full-scale adjustment should be made [with the proper
VIN (-) voltage applied) by forcing a voltage to the VIN (+)
input which is given by:

where fCM is the frequency of the common-mode signal,
VPEAK is its peak voltage value
and fClK is the AID clock frequency ..
For a 60Hz common-mode signal to generate a % LSB error (:::: 5mV) with the converter running at 250kHz, its peak
value would have to be 6.63V which would be larger than
allowed as it exceeds the maximum analog input limits.
Source resistance limitation is important with regard to the
DC leakage currents of the input multiplexer. While operating near or at maximum speed, bypass capacitors should
not be used if the source resistance is greater than 1kO.
The worst-case leakage current" of ± 1/LA over temperature
will create a 1mV input error with a 1kO source resistance.
An op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance signal source be required.

VIN (+) fsadj = YMAX

~ 1.5 [(VMAX -

256

VMIN)]

where:
VMAX =; the high end of the analog input range
and

5.0 OPTIONAL ADJUSTMENTS
5.1 Zero Error

VMIN = the low end (the offset zero) of the analog range.
(Both are ground referenced.)

The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not ground
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any VIN (-) input at this VIN(MIN) value. This
utilizes the differential mode ~peration of the AID.

The VREFIN (or Vee) voltage is then adjusted to provide a
code change from FEHEX to FFHEX. This completes the adjustment procedure.

2-209

•

Applications
A "Stand·Alone" Hook·Up for ADC08238 Evaluation
MU.I.OORISS

~:::::;::::::~::::=1;:::=t--05VDC
"'f41

,t ,t j, J,
U

.J

11

13

11

:I

II
PARALLEL ,,"'8
I.'UT SHIFT AIGISTER
lIt' ••

...

~~""'-o'v.c
OUtPUT SHIfT REGISTER

J'CIM

Go

1Z

'Pinouts shown for ADC08238.
For all other products tie to pin functions as shown.

11

"

~MA~--~--~~--~.'-T-'-.~~O~y--~~--~----~,-"-osvac

Low-Cost Remote Temperature Sensor
v"

f5VDCI

.

v..

V'NI+I

'IIZI'

TIDIIF

-:

-:
AKII231

IYDe

,·1

TAIUJ

'="

V,II .. ,

.N.
.,..

VREFC

+

I'"''
TL/H/11015-21

2·210

Applications

(Continued)

Protecting the Input
Vee
ISVDe'
1SVOC

>""",,,M~I'\I\I\ICHO

Vee

+

'I'."
AOC118231

COM
GND

Diodes are lN914
TL/H/l1015-22

Operating with Ratlometric Transducers
20k
VXOR

vee

CHO
Ik
ZERO
ADJ

.I.+

CHI'

3k

VREF OUT

ADC08234

.I.+

100pF

3.9k

lk
FS
ADJ

GND

+

I'PF

'V'N(-) = 0.15 VAEF
15% of VAEF ,; VXDR ,; 85% of VREF

Span Adjust; OV

IOpF

24k

TLlH111015-23

~

V,N

~

3V

+5V

TL/H111015-24

2-211

•

Applications (Continued)
Zero-Shift and Span Adjust: 2V ,;; VIN ,;; 5V
+5V

10kl1
FS
'AD~

ADC08238
CHO

COM
Set. Zero
Code Voltage

2.7k1l

VREF OUT

t-.....- - -...---'

DGND . AGND

1 kl1

33011
2VDC

Zero ADJ
TLlH/ll015-25

2-212

r----------------------------------------------------------------,~

C

fi.....

f}1National Semiconductor

ADC0841

01:>0

8-Bit JLP Compatible AID Converter

General Description

Features

The ADC0841 is a CMOS 8-bit successive approximation
AID converter. Differential inputs provide low frequency input common mode rejection and allow offsetting the analog
range of the converter. In addition, the reference input can
be adjusted enabling the conversion of reduced analog
ranges with 8-bit resolution.

• Easy interface to all microprocessors
• Operates ratiometrically or with 5 Voc
voltage reference
• No zero or full-scale adjust required
• Internal clock
• OV to 5V input range with single 5V power supply
• O.S" standard width 20-pin package
• 20 Pin Molded Chip Carrier Package

The AID is designed to operate with the control bus of a
variety of microprocessors. TRI-STATE@ output latches that
directly drive the data bus permit the AI D to be configured
as a memory location or 1/0 device to the microprocessor
with no interface logic necessary.

Key Specifications
•
•
•
•
•

Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time

±Yz LSB and ±

8 Bits
1 LSB
5 Voc
15mW
40 JLs

Block and Connection Diagrams

8-BIT
S.A.R.
AjD

DBO(18)-DB7(11)

TLlH/B557-1

Dual-in-Line Package (N)

cs

1

Ro
WR

2

19

Vee
N.C.

3

18

OBO

N.C.

4

17

OBI

INTR

5

16

DB2

V1N(+)
V1N(-)

6

15

DB3

1

14

OB4

AGNO

8

13

DBS

VREf'

9

12

OB6

OGND

10

11

DBl

20

Molded Chip Carrier Package (V)
DBO

OBI

OB2

OB3

OB4

18

17

16

15

14

N.C.

19

13

OB5

Vee

20

12

DB6

11

DBl

cs
RD

2

10

DGNO

WR

3

9

VREF

TL/H/8557-2

Topvrew

N.C.

(N.C.·No Connection)

INTR V1N(+) V1k) AGNO
TUH/8557-3

Top View

2-213

Absolute Maximum Ratings

(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (Vee)
Voltage
Logic Control Inputs
At Other Inputs and Outputs
Input Current Per Pin (Note 3)
Input Current Per Package (Note 3)
Storage Temperature
Package Dissipation at T A = 25·C

Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (Plastic)
Molded Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
ESD Susceptibility (Note 10)

6.5V
-0.3V to Vee + 0.3V
-0.3V to Vee + 0.3V
±5mA

260·C
215·C
220·C
800V

Operating Conditions (Notes 1 and 2)
Supply Voltage (Vecl
Temperature Range
ADC0841 BCN, ADC0841 CCN
ADC0841 BCV, ADC0841 CCV

±20mA
-65·C to + 150·C
875mW

4.5 Voe to 6.0 Voe
TMIN~TA~TMAX
0·C~TA~70"C
-40·C~TA~85·C

Electrical Characteristics The following specifications apply for Vee = 5 Voe unless otherwise specified.
Boldface limits apply from T MIN to T MAX; all other limits TA = Tj = 25·C.
ADC0841 BCN,.ADC0841CCN
ADC0841 BCV, ADC0841CCV
Parameter

Conditions
Typ
(Note 6)

Units

Tested
Limit
(Note 7)

Design
Limit
(Note 8)

±%
±1

±%
±1

LSB
LSB

CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total
Unadjusted Error
ADC0841 BCN, BCV
ADC0841 CCN, CCV

VREF=5.00VDe
(Note 4)

Minimum Reference
Input Resistance

2.4

1.2

1.1

kG

Maximum Reference
Input Resistance

2.4

5.4

5.9

kG

Maximum Common-Mode
Input Voltage

(Note 5)

Vee + 0.05

Ycc+ O•05

V

Minimum Common-Mode
Input Voltage

(Note 5)

GND-O.05

GND-O.05

V

DC Common-Mode Error

Differential Mode

±'f,6

±%

±~

LSB

Power Supply Sensitivity

Vcc=5V±5%

±'f,6

±Ys

±%

LSB

2-214

l>
C

Electrical Characteristics The following specifications apply for Vcc= 5 Voc unless otherwise specified.

o

.,..om.....

Boldface limits apply from TMIN to TMAXi all other limits TA=Tj=25°C. (Continued)
ADC0841BCN, ADC0841CCN
ADC0841BCV, ADC0841CCV
Symbol

Parameter

Conditions
Typ
(Note 6)

Tested
Limit
(Note 7)

Design
Limit
(Note 3)

Units

DIGITAL AND DC CHARACTERISTICS
VIN(l)

Logical "1 " Input
Voltage (Min)

Vcc=5.25V

2.0

2.0

V

VIN(O)

Logical "a" Input
Voltage (Max)

Vcc= 4.75V

0.8

0.8

V

IIN(l)

Logical "1" Input
Current (Max)

VIN=5.0V

0.005

1

p.A

IIN(O)

Logical "a" Input
Current (Max)

VIN=OV

-0.005

-1

p.A

VOUT(l)

Logical "1"
Output Voltage (Min)

Vcc=4.75V
IOUT= -360 p.A
IOUT=-10p.A

2.8
4.6

2.4
4.5

V
V

VOUT(O)

Logical "0"
Output Voltage (Max)

Vcc=4.75V
IOUT=1.6 mA

0.34

0.4

V

lOUT

TRI-STATE Output
Current (Max)

VOUT=OV
VOUT=5V

-0.01
0.01

-0.3
0.3

-3
3

p.A
p.A

ISOURCE

Output Source
Current (Min)

VOUT=OV

-14

-7.5

-6.5

mA

ISINK

Output Sink
Current (Min)

VOUT= Vcc

16

9.0

8.0

mA

Icc

Supply Current (Max)

CS=1, VREFOpen

1

2.3

2.5

mA

2-215

AC Characteristics The following specifications apply for Vee =

5Voc. tr "': tf = 10 nS'unless otherwise specified.

Boldface limits apply from T MIN to T MAXi all other limits T A = T J = 25'C.
Tested
Symbol

Parameter

Typ

Conditions

Umlt

(Note 7)

(Note 8)

30

40

eo

50

150

ns

145

225

ns

(Note 6)

Ie

Maximum Conversion Time (See Graph)

tW(WA)

Minimiu~WR Pulse Width

(Note 9)

tACC

Maximum Access Time (Delay from Falling Edge of

CL = 100pF

AD to Output Data Valid)

(Note 9) ,

TRI-STATE Control (Maximum Delay from Rising

CL = 10 pF. RL = 10k.

Edge of RD to Hi-Z State)

tr = 20 ns (Note 9)

Maximum Delay from Falling Edge of WR or RD to

(Note 9)

tlH. tOH

tWI. tAl

Design

Umlt

125

200

400'

200

Units

p.s

ns

ns

Reset Of INTR

,

CIN

Capacitance of Logic Inputs

5

pF

COUT

Capacitance of Logic Outputs

5

pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond Its specified operating conditions.
"-

Note 2: All voltages are measurad with respect to the ground pins,
Note 3: During over-voltage conditions (VINVccl the maximum input cumsnt at any one pin is,±5 m".lf the current Is limited to ±5 rnA at all the
pins no more than four pins can be in this condition in order to meet the Input Current Per Package (± 20 rnA) specification.
Nota 4: Total undajusted error includes offset. full-scale, and linearity.

"

wm

Note 5: For VIN (-) ;;, VIN (+) the digital output code will be 0000 0000. Two on-chip diodes are Had to each analog input, which
forward-conduct for analog
input voltages one diode drop below ground or one diode drop greater than Vee supply. Be careful during testing at low Vee levels (4.5VJ, as high level analog
inputs (5VJ cen cause this input diode to conduct, especially at elevated temperatures, and cause errore for analog inputs near full-scale. The spec allows 50 mV
forWard bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the' output code will be correct To
achieve an absolute a Voc to 5 Voc input ,voltage range will therefore require a minimum supply voltage of 4.950 Voc over temperature variations, inHial tolerance
and loading.
Note 6: Typicals are at 25"C and represent most likely parametric norm,
Note 7: Tested IIm~s are guaranteed to National's AOQL (Average OutgOing Quality LeveQ,'
Note 8: DeSign limits are guaranteed but not 100% production tested, These limits are not used to calculate outgoing quality levels.
Nole ~: The temperature coefficient is O.3~/oC.
Note 10: Human body model. 100 pF discharged through 1.5 kO resistor.

Timing Diagram

cs\
Viii

-

\~

/

~~

II'

J

\

"

iiii

INTft

!WI I--

------'

DBO-087 - - - - - -

r

\

L'

te

~

-

l~

IJ

.

~

J

'I

tftl

NOTE 1

tiH. tOH'"

---------------\r-.!!!I:!!~------H
tACe-

OBO-Ol7

t--

+--

TL/H/B557 -9

Note 1: Read strobe must occur at least 600 ns after the assertion of Interrupt to guarantee reset of TNTI'!.

2-216

Typical Performance Characteristics
Logic Input Threshold
Voltage vs Supply Voltage
~

1.1

Power Supply Current vs
Temperature

-55'e S;TA :!>+IZI'C

~

~

Output Current vs
Temperature

Vcc,:,5V

1.7

~1.5

~

9
a
1.'

!

Il!

~

1.5

:,,"'u

1.4

~

1.3

io-'

r-

""'"

'"

ua

4.71

1.110

5.25

0 ...............-'--'-..............-1.........--1
-75-50-250 2550 75100125
TEr.1FERATURE I'C)

5.10

Vce -SUPPLYVULTAGE IVuel

Linearity Error vs VREF
ED

!.

Vcc;SV
Ta=2S'C
IZERD AHD FUU.sCALEAIIIUSTED)

0.5

I

Z
w

-

\.

-75 -50-25 0 25 50 75 100 125
TEMPERATURE I'C)

Conversion Time vs
Temperature

~

40

I

3D

:::

20

VCC~5!

40

....

!I;::

""":-

-==

30

.-.;11"

~ 20

,"

i.' .....

.,

il

B 10

10

o

2
3
VlEF IV)

50

TA=25'C

50

:::

8

o

o

Conversion Time vs VSUPPLY

. 1.0

a

....

~ 0.5
'"

;;

i

:"'"

4.5

4.75
5
5.25
SUFi'LY VOL'DlGE IV)

5.5

a

-75-50 -25 D 25 50 75 100 125
TEMPERATURE I'C) .
TLiH/S557-4

Unadjusted Offset Error vs
VREF Voltage
14

"""TT1Tmr-r-l'TTTnn
\\N(+I~\\~(-I·O

12·

vce

Vos=2mV

!
I :

TA = 25"C

10

.it

TIRI-STATE Test Circuits and Waveforms

PI

Ii;

4 1-++++i1ffA:+++

0 ...............................
0.01
0.1
1.0

VIEF IV)

TLiH/8557-5
TLiH/S557 -22

tOtt. CL = 10 pF

tOH

Vee

Vee
. Vee

DATA :::

OUTPUTS
GND

GND

~~lH

.

~

vee

~OH
---

DATA
OUTPUTS'

--------==

10%

VOL

TLiH/8557-6

TL/H/S557-S

Ir = 20n8

TLiH/8557-7

2·217

1r=20n9

ADC0841

"

c
~
n
0'
~
!!.

-

VREF AGND

90

08

START

LADDER AND DECODER

OJ

flf

0'
n

OAC

~

C

6

VIN(+) 0 ........-

.....-

c!'

....

Q;

3
7
V1N<-) 0

•
8

~

ONE SHOT

CD

TRI-STATE
OUTPUT LATCHES

XfER

14

•

-j

iRi 1<1141----.
ENABLE
DELAY

LSB

t.\SB
" 12 13 14 15 16 17 18
DB7 DB6 DB5 084 DB3 DB2 DBI DBO
DIGITAL OUTPUTS

1-600"S

-U-

"I "=OUTPUT

»
t:J

Functional Description

(")

A conversion is initiated via the CS and WR lines. If the data
from a previous conversion is not read, the INTR line will be
low. The falling edge of WR will reset the INTR line high and
ready the AID for a conversion cycle. The rising edge of WR
starts a conversion. After the conversion cycle (tc s: 60
",sec), which is set by the internal clock frequency, the digital data is transferred to the output latch and the INTR is
asserted low. Taking CS and RD low resets INTR output
high and transfers the conversion result on the output data
lines (DBO-DB7).

For a 60 Hz common-mode signal to generate a % LSB
error (Z 5 mV) with the converter running at 40 ",S, its peak
value would have to be 5.43V. This large a common-mode
signal is much greater than that generally found in a well
designed data acquisition system.

1.0 REFERENCE CONSIDERATIONS
The voltage applied to the reference input of this converter
defines the voltage span of the analog input (the difference
between VIN(MAX) and VIN(MIN) over which the 256 possible output codes apply. The device can be used in either
ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a voltage
source capable of driving the minimum reference input resistance of 1.1 kO. This pin is the top of a resistor divider
string used for the successive approximation conversion.

3.0 OPTIONAL ADJUSTMENTS
3.1 Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not ground,
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing the VIN (-) input at this VIN(MIN) value.
The zero error of the AID converter relates to the location
of the first riser of the transfer function and can be measured by grounding the V- input and applying a small magnitude positive voltage to the V + input. Zero error is the
difference between actual DC input voltage which is necessary to just cause an output digital code transition from 0000
0000 to 0000 0001 and the ideal Yz LSB value (Yz LSB = 9.B
mV for VREF=5.000 Voe>.

In a ratiometric system (Figure 1a), the analog input voltage
is proportional to the voltage used for the AID reference.
This voltage is typically the system power supply, so the
VREF pin can be tied to Vee. This technique relaxes the
stability requirements of the system reference as the analog
input and AID reference move together maintaining the
same output code for a given input condition.
For absolute accuracy (Figure 1b), where the analog input
varies between very specific voltage limits, the reference pin
can be biased with a time and temperature stable voltage
source. The LM3B5 and LM336 reference diodes are good
low current devices to use with this converter.

3.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1 Yz LSB down from the desired
. analog fUll-scale voltage range and then adjusting the magnitude of the VREF input for a digital output code changing
from 11111110 to 11111111.
3.3 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the AI D is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A voltage which equals
this desired zero reference plus Yz LSB (where the LSB is
calculated for the desired analog span, 1 LSB = analog
span/256) is applied to the "+" input (VIN(+) and the zero
reference voltage at the "-" input (VIN(-)should then be
adjusted to just obtain the OOHEX to 01 HEX code transition.

2.0 THE ANALOG INPUTS
2.1 Analog Differential Voltage Inputs and CommonMode Rejection
The differential inputs of this converter actually reduce the
effects of common-mode input noise, a signal common to
both selected" +" and" -" inputs for a conversion (60 Hz
is most typical). The time interval between sampling the
" +" input and then the "-" input is Yz of a clock period.
The change in the common-mode voltage during this short
time interval can cause conversion errors. For a sinusoidal
common-mode signal this error is:
VERROR(MA)<)=Vpeak (2'IT fCM)XO.5x

....

01:>0

2.2 Input Current
Due to the sampling nature of the analog inputs, short duration spikes of current enter the" +" input and exit the" -"
input at the clock edges during the actual conversion. These
currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents
and cause an effective DC current to flow through the output resistance of the analog Signal source. Bypass capacitors should not be used if the source resistance is greater
than 1 kO. An op amp RC active low pass filter can provide
both impedance buffering and noise filtering should a high
impedance signal source be required.

Applications Information

The maximum value of the reference is limited to the Vee
supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals
VREF/256).

oQ)

(~)

where leM is the frequency of the common-mode signal,
Vpeak is its peak voltage value and tc is the conversion
time.

2-219

II

,.. r-----------------------------------------------~----------------------------~--~--,

•

CD '

0'

o
~

Applications Information (Continued)
sv

sv

AGND

AGND

TL/H/8557-11

TL/H/8557-12

a) Ratlometric

b) Absolute with a Reduced Span
FIGURE 1. Referencing Examples

The full-scale adjustment should be made [with the proper
VIN (-) voltage applied] by forcing a voltage to the VIN( +)
input which is given by:
'

VMIN = the low end (the offset zero) of the analog range.
(Both are ground referenced.)
The VREF (or Vee) voltage is then adjusted to provide a
code change from FEHEX to FFHEX. This completes the adjustmentprocedlire. '
,

V (+)fsadJ'=V ' -15 [(VMAX-VMIN)]
IN
MAX·
256
where VMAX=the high end ,of

th~ 'analog input ra~ge

For an example see the Zero-Shift and Span Adjust circuit
below.

and

Zero-ShiH and Span Adjust (2V S;VIN S; 5V)
Vcc
l&Voc)

VINI+)

Vcc

'+
~la'F

VIN

'='SETS
VOLTAGE
SPAN

Uk

....;...--- -,

, AOCOa41'

I
I
VINI-)

VREF

I
I
I
I
_J

LM331-Z.5

SETS ZERO
CODE VOLTAGE
IZV)

331
It

Uk

"::'

ZVoc
ZEROAIIJ

"::'

"::'
TL/H/8557-13

2·220

~----------------------------------------------~~

Applications Information

c

g

(Continued)

Span Adjust OY";YIN,,;3Y

....

~

Vee

(5V oe)

VIN(+)

Vee

+

~'D"F
ADC0841

Ik
VINH

VREF
LM336-2.5

":'

TLlH/8557-14

Protecting the Input

High Accuracy Comparator
Vee
(&Voe)

SV

+

~lOpF
ADCDB41

TLlH/B557 -16

00=a1l1s iIVIN(+»VIN(-)
TLlH/8557-15

OO=all Os iIVIN(+)-++---~ VIN(+)
VIN(-)
8
AGND
9
VREF
10
DGND

OBI
082
DB3
DB4
DBs
DBS

(MSB)DB7

19
18

1.3K
1.3K

17
16

1.3K
1.3K

IS
14

1.3K
1.3K

13
12
II

1.3K
1.3K
L.E.D.
XCIOl7
(8)
TLlH/B557-19

Operating with Automotive Ratiometric Transducers
Vee
CIVgel

AOCD841

TL/H/B557-17

2·222

.--------------------------------------------------------------------.~

c

Applications Information (Continued)

0000

0410

0010

B9FF

0012
0014
0016
0018

B820
89FF
2300
1450

o

g

SAMPLE PROGRAM FOR ADC0841-INS8039 INTERFACE
CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS
ORG
OH
JMP
BEGIN
;START PROGRAM AT ADDR 10
ORG
10H
;MAIN PROGRAM
R1,#OFFH
;LOAD R1 WITH A UNUSED ADDR
BEGIN:
MOV
;LOCATION
MOV
RO,#20H
;AlD DATA ADDRESS
ORL
P1,#OFFH
;SET PORT 1 OUTPUTS HIGH
A,OOH
MOV
;LOAD THE ACC WITH 00
CALL
CONV
;CALL THE CONVERSION SUBROUTINE
;CONTINUE MAIN PROGRAM
;CONVERSION SUBROUTINE
;ENTRY:ACC--A/D MUX DATA
;EXIT: ACC--CONVERTED DATA

0050
0052
0053
0054
0056
0057
0059
005A

99 FE
91
09
3253
81
8901
AO
83

ORG
ANL
MOVX
IN
JB1
MOVX
ORL
MOV
RET

CONV:
LOOP:

50H
P1,#OFEH
@R1"A
A.P1
LOOP
A,@R1
P1,&01H
@RO,A

;CHIP SELECT THE AID
;START CONVERSION
;INPUT INTR STATE
';IF INTR = 1 GOTO LOOP
;IF INTR = 0 INPUT AID DATA
;CLEAR THE AID CHIP SELECT
';STORE THE AID DATA
;RETURN TO MAIN PROGRAM

ADC0841-INS80391nteriace
5V

5V

40
DBO
OBI
DB2
DB3
DB4
INS8039

DB5
DBS
DB7

Viii
iID
Pl0
Pl1

12

18

13

17

14

16

15

15

IS

14

17

13

18

12

19

11

8

3

10

2

6
27

S

DBO
OBI
DB2
DB3
DB4
DBS

V1N(+)

+

ADC0841

DBS
DB7

6

V1N(-)

7

Viii
iID

Cs
INTR

TL/H/8557-20

2-223

.a:o.
....

9- r---------------------------------------------------------------------------------~

Applications Information (Continued)

B

1/0 Interface to NSC800™
5V

5V

11

5V

Vee

:+-

VII£F

vRtl+l

DBO
DBI
DB2
DB3
DB4

ADD

005

AD5

ADI

ADZ
AD!
AD4

DB6

DB7
ADC0841

>-- V"(-l

-

ADa

Am

5V

:::

T1
T2
T3
T4 DM8131
15
T6

AGND

S1B

cs

DGND

Bl
B2
B3
B4

as
B6

8

8
p

AD11
AD12
AD13
AD14
AD15

lolii

our

-----.J

I

WR
RD

WR
RD

...l..
TLlH/8557 -21

SAMPLE PROGRAM FOR ADC0841-NSC800 INTERFACE
0010

NCONV

EaU

16

OOOF
001F
3COO

DEL
CS
ADDTA

EaU
EaU
EaU

15
1FH
003CH

DTA:
START:

DB
LD
LD
LD
LD
OUTI
EX

08H
C,CS
B,NCONV
HL,DTA
DE,ADDTA

LD
DEC
JP
INI

A,DEL
A
NZ,WAIT

EX
JP

DE,HL
NZ,STCONV

0000'
0001'
0003'
0005'
0008'
OOOB'
0000'

00
OE 1F
0616
210000'
11003C
EDA3
EB

OOOE'
0010'
0011'
0014'

3EOF
3D
C20013'
EDA2

0016'
0017'

EB
C2000E'

STCONV:

WAIT:

;TWICE THE NUMBER OF REaUIRED
;CONVERSIONS
;DELAY 60 j.Lsec CONVERSION
;THE BOARD ADDRESS
;START OF RAM FOR AID
;DATA
; DATA

;START A CONVERSION
;HL= RAM ADDRESS FOR THE
;AlDDATA

DE,HL

;WAIT 60 j.Lsec FOR THE
;CONVERSION TO FINISH
;STORE THE AID'S DATA
;THE REaUIRED CONVERSIONS COMPLETED?
;IF NOT GOTO STCONV

END
Note: A conversion is started, then a 60 p.s waH lor the AID 10 complete a conversion and tha data is stored at address ADDTA for the first conversion,
ADDTA + 1 for the second conversion, etc. for a total of 8 conversions.

Ordering Information
Temperature
Range

Total Unadjusted Error

Package
Outline

±% LSB

±1 LSB

O·Cto +70"C

ADC0841BCN

ADC0841CCN

N20A Molded Dip

- 40"C to + 85·C

ADC0841BCV

ADC0841CCV

V20A Molded Chip Carrier

2-224

tJ1National Semiconductor

ADC08441 ADC0848 8-Bit JLP Compatible AID Converters
with Multiplexer Options
General Description

Features

The ADC0844 and ADC0848 are CMOS 8-bit successive
approximation AID converters with versatile analog input
multiplexers. The 4-channel or 8-channel multiplexers can
be software configured for single-ended, differential or
pseudo-differential modes of operation.

• Easy interface to all microprocessors
• Operates ratiometrically or with 5 VDC
voltage reference
• No zero or full-scale adjust required
• 4-channel or 8-channel multiplexer with address logic
• Internal clock
• OV to 5V input range with single 5V power supply
• 0.3" standard width 20-pin or 24-pin DIP
• 28 Pin Molded Chip Carrier Package

The differential mode provides low frequency input common
mode rejection and allows offsetting the analog range of the
converter. In addition, the AID's reference can be adjusted
enabling the conversion of reduced analog ranges with 8-bit
resolution.
The AIDs are designed to operate from the control bus of a
wide variety of microprocessors. TRI-STATE® output latches that directly drive the data bus permit the AIDs to be
configured as memory locations or I/O devices to the microprocessor with no interface logic necessary.

Key Specifications
• Resolution
• Total Unadjusted Error
II Single Supply

±% LSB and ±

• Low Power
• Conversion Time

8 Bits
1 LSB
5 VDC
15mW
40,...s

Block and Connection Diagrams
AGNOIIOI VCCI241 OGNOl121

L

L

L

'CHI121-CHBI91

!II
• ADC0848 shown in

DIP Package
CH5·CH8 not Included
on the ADC0844

TLIH15016-1

Dual-In-Line Package
iiii

cs
CHI
CH2
CH3
CH4

I
2
3
4

_44

20
19
18
17
16
IS
14
13
12
II

Dual-In-Line Package'

Vee

iiii

ViR
iNTR

CHI
CH2
CH3
CH4
CH5
CH6
CH7
CH8
AnNO

080/NAO
081/NA1
082/NA2

DB3/NA3
D94
Dl5
Dl6
TLIH15016-2

VII£F

DGNO

I
2

5
6
7

24 Vee
23
22 ViR
21 iHiR
20 DBO/IIAO
19 DBI/NAI
18 082/NA2
17 083/NA3
16 DB4/NM
15 .085
14 086
13 087
TLIHISOI6-30

Molded Chip Carrier Package

cs

ADC084II

B

9
10
II
12

Top View

Top View

iNTR
ViR

cs
.HC

26
27
28
I

ADC0848

17
16
15
14
13
12

086
087
DGNO
NC

VREF
AGNO

eHS

TLIHISOI6-29

Top View

See Ordering Information
. 2-225

CD

-=r
CD

8c

~
-=r
-=r
CD

CI
(,)

C

cc

Absolute Maximum Ratings

(Notes 1 & 2)
Lead Temperature (Soldering, 10 seconds)
Dual-In-Line Package (Plastic)
Dual-In-Line Package (Ceramic)
Molded Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (Vee>
Voltage
Logic Control Inputs
At Other Inputs and Outputs
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Storage Temperature
Package Dissipation at TA= 25'C
ESD Susceptibility (Note 4)

6.5V
-0.3V to + 15V
-0.3Vto Vee+0.3V
5mA
20mA
- 65'C to + 150'C
B75mW
BOOV

260"C
300'C
215'C
220'C

Operating Conditions (Notes 1 &2) ..
Supply Voltage (Vee>
Temperature Range
ADCOB44BCN, ADCOB44CCN,
ADCOB4BBCN,ADCOB4BCCN
ADCOB44BCJ, ADCOB44CCJ,
ADCOB4BBCJ, ADCOB4BCCJ.
ADCOB4BBCV, ADCOB4BCCV

Electrical Characteristics The following specifications apply fo~ Vee =

4.5 Voe to 6.0 Voe
. TMINS;TAS;TMAX
O'CS;TAS;70'C
-40"CS;TAS;B5'C

5 Voe unless otherwise specified.

Boldface limits apply from TMIN to TMAX; all other limits TA = Tj = 25'C.

Parameter

ADC0844BCJ
ADC0844CCJ
ADC0848BCJ
ADC0848CCJ

Conditions

Tested
Limit
(Note 6)

Typ
(Note 5)

ADC0844BCN, ADC0844CCN
ADC0848BCN, ADC0848CCN
ADC0848BCV, ADC0848CCV
Design
Typ
Limit
(Note 5)
(Note 7)

Tested
Limit
(Note 6)

Design
Limit
(Note 7)

±1f2

±y,.

±1

±1

Limit
Units

CONVERTER AND MULTIPLEXER CHARACTERISTICS

Maximum Total
VREF=5.00Voe
(Note B)
Unadjusted Error
ADCOB44BCN, ADCOB4BBCN, BCV
ADCOB44BCJ, ADCOB4BBCJ
ADCOB44CCN, ADCOB4BCCN, CCV
ADCOB44CCJ, ADCOB4BCCJ

±y,.
±1

LSB
LSB
LSB
LSB

Minimum Reference
Input Resistance

2.4

1.1

2.4

1.2

1.1

kO

Maximum Reference
Input Resistance

2.4

5.9

2.4

5.4

5.9

kO

Maximum Common-Mode
Input Voltage

(Note 9)

Vee+ 0 .05

Vee + 0.05 Vee + 0.05

V

Minimum Common-Mode
Input Voltage

(Note 9)

GND-0.05

GND-0;05 GND-0.05

V

DC Common-Mode Error

Differential Mode

± 1f16

±%

± 1f16

±%

±%

LSB

Power Supply Sensitivity

Vee=5V±5%

±1f16

±%

±1f16

±Ys

±%

LSB

Off Channel Leakage
Current

(Note 10)
On Channel = 5V,
Off Channel = OV

-1

-0.1

-1

/LA

1

0.1

1

/LA

On Channel = OV,
Off Channel = 5V
DIGITAL AND DC CHARACTERISTICS

VIN(1), Logical "1" Input
Voltage (Min)

Vee=5.25V

2.0

2.0

2.0

V

VIN(O), Logical "0" Input
Voltage (Max)

Vee=4.75V

0.8

O.B

0.8

V

IIN(1), Logical "1" Input
Current (Max)

VIN=5.0V

1

/LA

0.005

2-226

1

0.005

Electrical Characteristics The following specifications apply for Vcc = 5 Voc unless otherwise specified.
Boldface limits apply from T MIN to TMAX; all other limits TA = Tj = 25°C. (Continued)

Parameter

ADC0844BCJ
ADC0844CCJ
ADC0848BCJ
ADC0848CCJ

Conditions
Typ
(Note 5)

Tested
Limit
(Note 6)

-0.005

-1

ADC0844BCN, ADC0844CCN
ADC0848BCN, ADC0848CCN
ADC0848BCV, ADC0848CCV
Design
Limit
(Note 7)

Ty!!
(Note 5)

Tested
Limit
(Note 6)

Design
Limit
(Note 7)

Limit
Units

DIGITAL AND DC CHARACTERISTICS (Continued)
IIN(O). Logical "0" Input
Current (Max)

VIN=OV

VOUT(I). Logical "I"
Output Voltage (Min)

Vcc=4.75V
IOUT= -360 IJ.A
IOUT= -10 IJ.A

VOUT(O). Logical "0"
Output Voltage (Max)

Vcc=4.75V
IOUT=I.6mA

lOUT. TRI-STATE Output
Current (Max)

VOUT=OV
VOUT=5V

-0.Q1
0.Q1

-3
3

ISOURCE. Output Source
Current (Min)

VOUT=OV

-14

ISINK. Output Sink
Current (Min)

VOUT=VCC

Icc. Supply Current (Max)

CS= 1. VREF Open

-0.005

-1

IJ.A

2.4
4.5

2.8
4.6

2.4
4.5

V
V

0.4

0.34

0.4

V

-0.Q1
0.. 01

-0.3
0.3

-3
3

IJ.A
IJ.A

-6.5

-14

-7.5

-6.5

rnA

16

8.0

16

9.0

8.0

mA

1

2.5

1

2.3

2.5

mA

AC Electrical Characteristics The following specifications apply for Vcc = 5Voc. tr = t, = IOns unless
otherwise specified. Boldface limits apply from T MIN to T MAX; all other limits TA = Tj = 25°C.
Parameter

Conditions

te. Maximum Conversion Time (See Graph)

Typ
(Note 5)

Tested
Limit
(Note 6)

Design
Limit
(Note 7)

Units

30

40

60

IJ.s

150

tw(WFi). Minimum WR Pulse Width

(Note 11)

50

tACC. Maximum Access Time (Delay from Falling Edge of
RD to Output Data Valid)

CL = 100pF
(Note 11)

145

225

ns

t1H.IoH. TRI-STATE Control (Maximum Delay from Rising
Edge of RD to Hi-Z State)

CL= 10pF.RL= 10k
(Note 11)

125

200

ns

tWI. tRI. Maximum Delay from Falling Edge of WR or RD to
Reset of INTR

(Note 11)

200

400

ns

tos. Minimum Data Set-Up Time

(Note 11)

50

100

ns

tOH. Minimum Data Hold Time

(Note 11)

0

50

CIN. Capacitance of Logic Inputs

5

ns

ns
pF

5
pF
COUTo Capacitance of Logic Outputs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.

Note 2: All voltages are measured wHh respect to the ground pins.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V- or VIN > V+) the absolute value of the current at that pin should be
limited to 5 rnA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 4: Human body model. 100 pF discharged through a 1.5 kO resistor.
Note 5: Typicals are at 2S'C and represent most likely parametric norm.
Note 6: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 7: Design limits are guaranteed by not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 8: Total unadjusted error includes offset, full-scals, linearity. and multiplexer error.

2-227

•

Nota 9: For V,N (-) :;, V,N (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input, which will forward-conducl for analog
input voltages one diode drop below ground or one diode drop greater than Vee supply. Be careful during testing at low Vee levels (4.5V), as high level analog
inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs -near full-scale. The spec allows 50 mV
forward bias of either diode. This means that as long as the analog V,N does not exceed the supply voltage by more than 50 mV, the output code will be cooect. To
achieve an absolute 0 Vee to 5 Vee input voltage range will therefore require a minimum supply voltage of 4.950 Vee over temperature vartations, Initial tolerance
and loading.
Nota 10: Off channelleekage current is measured after the channel selection.
Note 11: The temperature coefficient is 0.30/0/'C.

Typical Performance Characteristics
Logic Input Threshold
Voltage vs Supply Voltage
~

1.1

~

1

20

i

15

0-

10

~

'"

&.ID

I I

vee -SU"LY VULTAGE IVucl

:i

Vc~~5V

I

ADJUSTEDI

I

-

40

...

50

..
z

u

...

~~

10

o

2

o

4.5

3

Conversion Time vs
Temperature

III

-75 -50 -21 a 25 50 75 100 -125
TEMPERATURE I'CI

TA=25'C

¥lIEF (VI

•>=
Iiii,..

o

50

I:

\..
o

:i

..... ....

- Conversion Time vs VSUPPLY
&0

TA=25'C
(ZERO AND FULL-SCALE-

- -r--

~ 0.5
iii

-

IS+Vof=fvt

Linearity Error vs VREF

0.5

I

r-..

~RCEVoC=2.4~

I,D

!
I

......

Yl:c;,5V

1 ,.5

I""" ,Voc=5V

-75 -50 -25 0 25 50 75 100 125
TEMPERATURE ('CI

UD

&.2&

JYl:C=5VoC

.....

~CEVoC=OVJ

o

1.3

4.71

2

25

-SI'C ~ TA l> "2I'C

I
UD

Power Supply Current vs
Temperature

Output Current vs
Temperature

40

30
20

~~

, ., ~

.,.

u

Unadjusted Offset Error vs
VREF Voltage
- 14

Vcc=5

4.75
5
1.21
SUPPLY VOIJAIIE (VI

"

1111111 VINI~:~'NI-J~~I
Vos=2mV
1111m
TA=2S'C

12

;;
:;!

10

1111111

iii15

i..

10

o

,

'4

o

-75-50-25 0 25 50 75 100 125
TEMPERATURE ('CI

0.01

f-

rf-

!!!
0.1

1.0

¥REF (VI
TL/H/5016-3

2-228

TRI-STATE Test Circuits and Waveforms
Vcc

Vcc

DATA :::
TL/H/5016-4

OUTPUTS
GND

~~IH

~

--------=
TLlH/5016-5

1,= 20 no

toH

Vcc

toH. CL = 10 pF

Vcc

10k

GNO

~
OH

VCC
DATA

---

OUTPUTS'

lOll

VOL
TL/H/5016-7

t,. = 20 ns

TL/H/S016-6

Leakage Current Test Circuit
5V

•

ADC0B48

1 ' " - - -....... CH210N/OFFI
CH3 ION/OFFI
CH410N/OFFI
CHS ION/OFFI"
CH6 ION/OFFI'
CH7 ION/OFFI"
CH810N/OFFI"

CHANNEL
VOL11lGE
SELECT

'NOT lNCWOEO ON ADC0B44

2-229

TLlH/5016-6

Timing Diagrams
Programming New Channel Configuration and Starting a Conversion

cs
Viii

"

r

\

/

iiii

te
INTR _____ J

:::.;::: -----TL/H/5016-9
Nole I: Read strobe must occur at least 600 ns after the assertion of interrupt to guarantee reset of lIITR.
Nole 2: MA

sta~ds for MUX addrs.ss:

Using the Previously Selected Channel Configuration and Starting a Conversion
CI \

1

______

'

f

_ _...J

iiii

--~---------{

DBO-DB7
READING THE RESULT
OFTHE LAST
CONVERSION

2-230

}--

TUH/5016-10

»
c

CHl ~~
CH2
CH3

I

~

~"-

__ ~c

1D

oQ

D~ __

CC)

olio

CC)

LADDER AND DECODER
DAC

~

~~~

ClK

START

I-p-t

F/F

."

~

C

~

n
0'
~
!!.

CH4
CH5
L.-

+(-)

CH6

SIGN
SELECT

~:?I.

CH7

'"

CHB

~ +(-)

.JC)I..

l

"

-

~

G

4
SAR LATCH

~

m

9-BIT
SHIFT REGISTER

i5"

n

~

C

ii)'

j.

,-

CQ

B

AGND

DJ

3

ONE SHOT

~

~

MUX
DECODER

TRI·STAT£'
OUTPUT LATCHES

XFEII
"1"=OUTPUT
ENABLE

~
MUX
ADDRESS
LATCH

-I

fill

r

600RS

DELAY
MAO
MAl
MA2
MA3
MA4
,lSS

.

INTR

MSS,

DIGITAL OUTPUTS

':5
\.

[

~
TL/H/5016-11

8t80~av Itt80~av

Functional Description
ferred to the output latch and the TiiITR is asserted low.
Taking a; and RO low resets INTR output high and outputs
the conversion result on the data lines (OBO-OB7).

The AOC0844 and AOC0848 contain a 4-channel and 8channel analog input multiplexer (MUX) respectively. Each
MUX can be configured into one of three modes of operation differential, pseudo-differential, and single ended.
These modes are discussed in the Applications Information
Section. The specific mode is selected by loading the MUX
address latch with the proper address (see Table I and Table II). Inputs to the MUX address latch (MAO-MA4) are
common with data bus, lines (DBO-DB4) and are enabled
when the RD line is high. A conversion is initiated via the CS
and WR lines. If the data'from a previous conversion is not
read, the INTR line will be low. The falling edge of WR will
reset the INTR line high and ready the AID for a conversion
cycle. The rising edge of WR, with AD high, strobes the data
on the MAO/OBO·MA4/0B4 inputs into the MUX address
latch to select a new input configuration and start a conversion. If the AD line is held low during the entire low period of
WR the previous MUX configuration is retained, and the
data of the previous conversion is the output on lines OBODB7. After the conversion cycle (tc :s; 40 I£S), which ,is set
by the internal clock frequency, the digital' data is trans-

Applications Information
1.0 MULTIPLEXER CONFIGURATION
The design of these converters utilizes a sampled-data
comparator structure which allows a differential analog input
to be converted by a successive approximation routine.
The actual voltage converted is always the difference between an assigned" + .. input terminal and a .. -" input terminal. The polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive. If the aSSigned .. + .. input is less than the
.. -" input the converter responds with an all zeros output
code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels., The input channels can be
software configured into three modes: differential, single-

TABLE I_ ADC0844 MUX ADDRESSING
MUXAddress

CS

WR

MA2

MA1

X
X
X
X

L
L
L
L

L
L
H
H

L
H

L
L
L
L

L
L
L
L

H
H,
H
H

L
L
H
H

L
H
L
H

L
L
L
L

H
H
H

H
H
H

L
L
H

L
H
L

X

X

X

X

MAO

L

H

Channel#

RD
CH1

MA3

H
H
H
H

+

+

1I

H
H
H
H

L
L
L

+

1I

H
H
H

L

1I

L

1I

-

CH2

CH3

CH4

+

-

-

+

AGND

MUX
Mode

-

+

Differential

-

-

+

-

+

-

+
-

PseudoDifferential

-

+

-'

+

Single-Ended

Previous Channel Configuration

X=don'\ care

4 Single-Ended

CH1CHZCH3CH4-

r

(+)
(+)
(+)
(+)

2 Differential

CH1,CHZ{
ADC0844
,

cH3,cH4

AGND(-)

=

{_

1

+(-)
-(+)

ADC0844
+(-)
-(+)

TUH/5016-12

TL/H/5016-13

3 Pseudo-Differential

CH1- (+)
CHZ- (+)
CH3- (+)

CH1,CHZ{

=

Combined

~

ADC0844
CH3- +
CH4--";' +
AGND(-)

AOC0844

r

CH4- (-)
TL/H/5016-14

TUH/5016-15

FIGURE 1_ Analog Input Multiplexer Options

2-232

:J>

Applications Information

(Continued)

ended, or pseudo-differential. Figure 1 shows the three
modes using the 4-channel MUX ADC0844. The eight inputs
of the ADC0848 can also be configured in any of the three
modes. In the differential mode, the ADC0844 channel inputs are grouped in pairs, CH1 with CH2 and CH3 with CH4.
The polarity assignment of each channel in the pair is interchangeable. The single-ended mode has CH1-CH4 assigned as the positive input with the negative input being the
analog ground (AGND) of the device. Finally, in the pseudodifferential mode CH 1-CH3 are positive inputs referenced
to CH4 which is now a pseudo-ground. This pseudo-ground
input can be set to any potential within the input commonmode range of the converter. The analog signal conditioning
required in transducer-based data acquisition systems is
significantly simplified with this type of input flexibility. One
converter package can now handle ground referenced inputs and true differential inputs as well as signals with some
arbitrary reference voltage.

divider string used for the successive approximation conversion.
In a ratiometric system (Figure 2a), the analog input voltage
is proportional to the voltage used for the AID reference.
This voltage is typically the system power supply, so the
VREF pin can be tied to Vee. This technique relaxes the
stability requirements of the system reference as the analog
input and AID reference move together maintaining the
same output code for a given input condition.
For absolute accuracy (Figure 2b), where the analog input
varies between very specific voltage limits, the reference pin
can be biased with a time and temperature stable voltage
source. The LM385 and LM336 reference diodes are good
low current devices to use with these converters.
The maximum value of the reference is limited to the Vee
supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals
VREF/256).

The analog input voltages for each channel can range from
50 mV below ground to 50 mV above Vee (typically 5V)
without degrading conversion accuracy.

2.0 REFERENCE CONSIDERATIONS
The voltage applied to the reference input of these converters defines the voltage span of the analog input (the difference between VIN(MAX) and VIN(MIN») over which the 256
possible output codes apply. The devices can' be used in
either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a
voltage source capable of driving the minimum reference
input, resistance of 1.1 kO. This pin is the top of a resistor

3.0 THE ANALOG INPUTS
3~ 1 Analog Differential Voltage Inputs and CommonMode Rejection

The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected "+ .. and" -" inputs for a conversion (60
Hz is most typical). The time interval between sampling the

TABLE II. ADC0848 MUX Addressing
MUX Address

--r---r---,--..----i CS WR RD
MA4

MA3

MA2

MA1

x

L

X
X
X

L
L

L
L
L
L

L
L

X
X
X
X
L
L
L
L

H

L
H
L

L
L
L

H
H

L
L

H

H
H

L

L

H
H

H

L
L
L
L
L

H
H

L
L

L

L

L

L

L
H

H

H
H

L

H
H

H

H
H
H
H

L

u

H
H
H
H
H
H
H
H
H

H
L

H

L

H

H
H

H
H

L
H

L
L
L
L
L
L
L

L

L

L

L

H

H
H
L

H
L
H

H

L
L
L
H

L

H
H
H

H
H

H
H

H
H

L

L
H

H
H
H
H
H

H

L

L
L
L
L
L
L

X

X

X

X

X

L

L
L

L

H
H
H
H

+

CH2

CH3

+

CH4

CH5

CH6

CH7

+
+
+
+
+
+

+

H

Single-Ended

+

H

+
+
+

H

+
+
+

Pseudo:
Differential

+

+
+

+

H

U

MUX
Mode

+

H
H

U

AGND

Differential

+

H

u

CH8

+

H

L
H
L

L

Channel

i---r--,---,----r---r---r---r--,----I

CH1

H
L

L
L
L

H

MAO

L

Previous Channel Configuration
2-233

c
oo

00

.co.

.co.
.....

:J>

c
oo

00

.co.

CI:I

Applications Information (Continued)
U+" input and then the U_" inputs is % of a clock period.
The change in the common-mode voltage during this short
time interval can cause conversion errors. For a sinusoidal
common-mode signal this error is:

4.0 OPTIONAL ADJUSTMENTS
4.1 Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not ground,
a' zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any VIN (-) input at this VIN(MIN) value. This is
useful for either differential or pseudo-differential modes of
input channel configuration.

,, (tc)
"8

VERROR(MA)<) = Vpeak (2'lT fCM) X 0.5 X,

where fCM is the frequency of the common-mode signal,
Vpeak is its peak voltage value and is the conversion time.

tc

For a 60 Hz common-mode signal to generate a % LSB
error (:::: 5 mV) with the converter running at 40 ,...S, its peak
value would have to be 5.43V. This large a common-mode
signal is, much greater than that generally found in a well
designed data acquisition system.

The zero error of the AID converter relates to the location
of the first riser of the transfer function 'and can be measured by grounding the V- input and applying a small magnitude positive voltage to the V+ input. Zero error is the
difference between actual DC input voltage which is necessary to just cause an output digital code transition from 0000
0000 to 0000 0001 and the ideal % LSB value {% LSB = 9.8
mV for VREF=5.000 Vocl.

3.2 Input Current
Due to the sampling nature of the analog inputs, short duration spikes of durrent enter the U +" input and exit the" -"
input at the clock edges during the actual conversion. These
currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents
and cause an effective DC current to flow'1hrough the output resistance of the analog signal source. Bypass capacitors should not be used if the source resistance is, greater
than 1 kfi.

4.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1 % LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the VREF input for a digital output code changing
from 11111110 to 11111111.
4.3 Adjusting for an Arbitrary Analog Input Voltage
Range

3.3 Input Source Resistance
The limitation of the input source resistance due to the DC
leakage currents of the input multiplexer is important. A
worst-case leakage current of ± 1 ,...A 'over temperature will
create a 1 mV input error with a 1 kfi source resistance. An
op 'amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance
signal source be required.

If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A VIN (+) voltage which
equals this desired zero reference plus % LSB (where the
LSB is calculated for the desired analog span, 1 LSB =
analog span/256) is applied to selected U+" input and the
zero reference voltage .at the corresponding .. -" input
should then be adjusted to just obtain the OOHEX to 01 HEX
code transition.

5.

5Y

y

I

vec
CIII(+)
CH2(+)
CH3(+)
CIM(+)
CH5(+) AUC_
CHI(+)
CH7(+)
CHI(+)

YRJJ

~

r.:

l

.~

~

vcc

CH1(+)
CH2(+)
CH3(+)

0w-

,... .;!r1"x';I
1,;"

l.-xro
... J:IT~
1.25\o!:
-xi"
,is; ov'= .....x'i'

YREF f-

, CH4( +) AUC_
CH5(+)
CH6(+)
CH7(+1

-~Ff"
1.25 ov1.25V

HAGND

UK

. .,

1. 25Y

~~ LM385

(-)AIlHD ,

.1

.J..
...L.

TL/H/5016-16
TLlH/5016-17

a) Ratiometrlc

b) Absolute with a Reduced Span
FIGURE 2. Referencing Examples

2-234

Applications Information (Continued)
The full-scale adjustment should be made [with the proper
VIN (-) voltage applied] by forcing a voltage to the VIN (+)
input which is given by:
.

VMIN=the low end (the offset zero) of the analog range.
(Both are ground referenced.)
The VREF (or Vecl voltage is then adjusted to provide a
code change from FEHEX to FFHEX. This completes the adjustment procedure.
For an example see the Zero-Shift and Span Adjust circuit
below.

V (+) fs adl'=V
-1.5 [(VMAX-VMIN)]
IN
MAX
256
where VMAX=the high end of the analog input range and

Zero·Shlft and Span Adjust (2V ~ VIN ~ 5V)
vcc
(5VDC)

VIN(+)

Vcc

+
~10'F

VIN

':'

VINI-I

':'SETS
VDLTAGE
SPAN

1.2.

- - - - -,

ADCOB44

I
I
I

VREF

I
SETS ZERO
CDDE VDLTAGE
(2V)

330

I
_J

1k
2VDC
ZERO ADJ

2.n

I

LM331,z.5

':'

':'

':'

TUH/5016-18

fII

2·235

Applications Information (Continued)
Differential Voltage Input 9-Bit A/D
r---------------------~--~_--1 VIN(+)

Vee

.--t-----------'--,

AOC0848

TLlH/5016-20

Protecting the Input

Vee
(5

vue>

TL/H/5016-21

Diodes are 1N914

2-236

Applications Information

(Continued)

High Accuracy Comparators
5V

SYSTEM
TEST
POINTS

TUH/5016-22
00=81118 iIVIN(+»V,N(-;-)
OO=all 08 iIVIN(+)----------------------~"

WR>------r"'"
n>-......-r. . .

ADCDa48

Tl/H/5016-26

CSoWR will update the channel configuration and start a conversion,
'CS-RD will read the conversion data and start a new conversion without updat-

Ing the channel configuration.
Waning for the end of this conversion Is not necessary. A CSoWR can immediately follow the CSoRO,

2-238

Applications Information

l>
C
0
Q
co

(Continued)

.&lo

ADC0844-INS8039 Interface

.&lo
.....

5V

l>

5V

C

40

20

Vee

.&lo

=

\,Icc
DBO
DBl
DB2
OB3
DB4

INS8039

0
Q
co

OB5
086
DB7

12

17

13

16

14

15

15

14

16

13

17

12

18

11

19

jjjj

10

27

VREF
(+)CHl
(-)CH2

DB2IMA2
OB3/MA3
OB4
DB5

AOC0844

086

Wi!
jjjj

PIO
Pll

OB1/MAl

DB7
19

Wi!

DBO/MAO

18

cs
iNi'ii

(+)CH3
(-)CH4

TL/H/5016-27

0000

0410

0010

B9FF

0012
0014
0016

B820
89FF
2300

0018
001A

1450
2302

001C
001D

18
1450

SAMPLE PROGRAM FOR ADC0844-INS8039 INTERFACE
CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS
OH
ORG
JMP
BEGIN
;START PROGRAM AT ADDR 10
10H
;MAIN PROGRAM
ORG
R1,#OFFH
BEGIN:
MOV
;LOAD R1 WITH A UNUSED ADDR
;LOCATION
RO,#20H
MOV
;AID DATA ADDRESS
P1,#OFFH
;SET PORT 1 OUTPUTS HIGH
ORL
MOV
A,OOH
;LOAD THE ACC WITH AID MUX DATA
;CH1 AND CH2 DIFFERENTIAL
CALL
CONV
;CALL THE CONVERSION SUBROUTINE
A,#02H
;LOAD THE ACC WITH AID MUX DATA
MOV
;CH3 AND CH4 DIFFERENTIAL
INC
RO
;INCREMENTTHE AID DATA ADDRESS
CALL
CONV
;CALL THE CONVERSION SUBROUTINE
;CONTINUE MAIN PROGRAM
;CONVERSION SUBROUTINE
;ENTRY:ACC-AID MUX DATA
;EXIT: ACC-CONVERTED DATA

0050
0052
0053
0054
0056
0057
0059
005A

99 FE
91
09
3253
81
8901
AO
83

CONV:
LOOP:

ORG
ANL
MOVX
IN
JB1
MOVX
ORL
MOV
RET

50H
P1,#OFEH
@R1,A
A,P1
LOOP
A,@R1
P1 ,&01 H
@RO,A

2-239

;CHIP SELECT THE AID
; LOAD AID MUX & START CONVERSION
;INPUT INTR STATE
;IF INTR = 1 GOTO LOOP
;IF INTR = 0 INPUT AID DATA
;CLEAR THE AID CHIP SELECT
;STORE THE AID DATA
;RETURN TO MAIN PROGRAM

co
~
co
Q

~.....

r---------------------------------------------------------------------------------,
Applications Information

(Continued)

110 Interface to NSC800

~
~

VCC
5V

5V

co
Q

VREF
5V
ADCD848

(J

~
AD/DBD

C

cr:

CHI( +) ::fg:~
.....---tCH2(+) MA3/DB3

~ADO
ADl

~

=

CH3(+) MA4/~~~
r-~~~'::::::::1 CH4(
+1
.DB6
.------1CH5(+)

DB7

r---oi CH~( +)

5V
T1

CH7(+)
CH8(+)

AD6
AD7

DM8131
81

T2

B2
T3
B3
T4
B4
B5
T5
B6
TS
8TB OUT

AD11
ADl2
AD13
ADl4
ADl5
101M

TL/H/5016~28

SAMPLE PROGRAM FOR ADC0848-NSC800 INTERFACE
OOOS
OOOF
001F
3COO
0000'
0004'
OOOS'
OOOA'
OOOC'
OOOF'
0012'

OS090AOB
OCODOEOF
.OE1F
0616
210000'
11003C
EDA3

0014'

EB

0015'
0017'
001S'
001B'

3EOF
3D
C20013'
EDA2

0010'
001E'

EB
C2000E'

NCONV
DEL
CS
ADDTA

EQU
EQU
EQU
EQU

16
15
1FH
003CH

MUXDTA:

DB
DB
LD
LD
LD
LD
OUTI

OSH,09H,OAH,OBH
OCH,ODH,OEH,OFH
C,CS
B,NCONV
HL,MUXDTA
DE,ADDTA

EX

DE,HL

LD
DEC
JP
INI

A,DEL
A
NZ,WAIT

EX
JP

DE,HL
NZ,STCONV.

START:

STCONV:

WAIT:

;DELAY 50 ,...sec CONVERSION
;THE BOARD ADDRESS
;START OF RAM FOR AID
;DATA
;MUXDATA

;LOADAlD'S.MUX DATA
;AND START A CONVERSION
;HL= RAM ADDRESS FOR THE
;AlDDATA
;WAIT 50 ,...sec FOR THE
;CONVERSION TO FINISH
;STORE THE AID'S DATA
;CONVERTED ALL INPUTS?
;IF NOT GOTO STCONV

END
Note: This routine sequentially programs the MUX data latch in the signal-ended mode. For CHI-CHB a conversion is started, then a 50
complete a conversion and the data is stored at address ADDTA for CHI. ADDTA + I for CH2. etc.

2-240

"'S wait for the AID to

Ordering Information
Temperature
Range

Total Unadjusted Error
±% LSB

±1 LSB

ADCOB44BCN
ADC0844CCN

O'Cto +70'C
ADC084BBCN

ADCOB4BCCN
ADCOB44BCJ
ADCOB44CCJ
-40'Cto +B5'C

ADC0848BCJ
ADC084BCCJ
ADCOB4BBCV
ADCOB48CCV

2-241

MUX
Channels

Package
Outline

4

N20A
Molded Dip

8

N24C
Molded Dip

4

J20A
Cerdip

8

J24F
Cerdip

8

V28A
Molded Chip Carrier

~ r-~~--~--------~--------~--------------~----~-------------------------.
Lt)

;

&i

8
~

t!lNational Semiconductor

ADC0852! ADC0854
Multiplexed Comparator with 8-Bit Reference Divider
General Description
The ADC0852 and ADC0854 are CMOS devices that combine a versatile analog input multiplexer, voltage comparator, and an 8-bit DAC which provides the comparator's
threshold voltage (VTH). The comparator provides a "l-bit"
output as a result of a comparison between the analog input
and the DAC's output. This allows for easy implementation
of set-point, on-off or "bang-bang" control systems with
several advantages over previous devices.
The ADC0854 has a 4 input multiplexer that can be software
configured for single ended, pseudo-differential, and full-differential modes of operation. In addition the DAC's reference input is brought out to allow for reduction of the span.

once each clock cycle up to a maximum clock rate of
400kHz.
..

Features
•
•
•
•
•
•

The ADC0852 has a two input multiplexer that can be configured as 2 single-ended or 1 differential input pair. The
DAC reference input is internally tied to Vee.
The multiplexer and 8-bit DAC are programmed via a serial
data input word. Once programmed the output is updated

2 or 4 channel mUltiplexer
Diiferential or Single-ended input, software controlled.
Serial digital data interface
256 programmable reference voltage levels
Continuous comparison after programming
Fixed, ratio metric, or reduced span reference capability
(ADC 0854)

Key Specifications
• Accuracy, ± y. LSB or
• Single 5V power supply
• Low Power, 15 mW

±

1 LSB of Reference (0.2%)

ClK

VREF-----I

>-----00

-v·

AGNO-----...J

0 1 - -....- - - - - 1

-vee

cs-

-OGND

CHO

CH1

CH2

CH3

COM
Tl/H/5521-1

FIGURE 1_ ADC0854 Simplified Block Diagram (ADC0852 has 2 input channels,
COM tied to GND, VREF tied to Vee, V + omitted, and one GND connection)
2 Channel and 4 Channel Pin Out
ADC0852 2-CHANNEL MUX
Dual-In-Line Package

cs

ADC0854 4-CHANNEL MUX
Dual-In-Line Package

Vee (V REF)

CHO
CH1

3

GNO (COM)

4

ClK

AOC0852
5

cs

Vee

CHO

y+

00

CH1

3

01

CH2

4

TLlH/5521-10

Top View

AOC0854

12

01

11

ClK

10

00

CH3

5

COM

6

VR[F

OGNO

7

AGNO

AGND and COM internally connected to GND
VREF internally connected to Vee

TLlH/5521-11

Top View

Order Number ADC0852
See NS Package Number N08E

Order Number ADC0854
See NS Package Number N14A
2-242

:J>

c

Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices 'are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Current into V+ (Note 3)
15mA
Supply Voltage; Vcc (Note 3)
Voltage
Logic and Analog Inputs
Input Current per Pin
Input Current per Package
Storage Temperature
Package Dissipation
at TA = 25'C (Board Mount)

o
Q

260'C

ESD Susceptibility (Note 14)

2000V

....

4.5Voc to 6.3VoC

U1

Operating Conditions

6.5V

Supply Voltage, Vcc
Temperature Range

-0.3Vto VCC +0.3V
±5mA

TMIN ,;; TA';; TMAX
O'C,;; TA';; 70'C

ADC0854CCN, ADC0852CCN

±20mA

.'

- 65'C to + 150'C

','

0.8W

Electrical Characteristics

The following specifications apply for Vcc = V+ = 5V (no V+ on ADC0852),
VREF';; Vcc + 0.1V, fClK = 250 kHz unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA
= TJ = 25'C.
ADC0852CCN
ADC0854CCN
Parameter

Conditions

Typ
(Note 4)

Tested
Limit
(Note 5)

Design
Limit
(Note 6)

Units

±1

±1

LSB

20

my'

CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted
Error (Note 7)
ADC0852/4/CCN

VREF Forced to
5.000Voc

Comparator Offset
ADC0852/4/CCN

2.5

Minimum Total Ladder
Resistance

ADC0854
(Note 15)

3.5

1.3

1.3

. kO

Maximum Total Ladder
Resistance

ADC0854
(Note 15)

3.5

5.4

S.9

kO

Minimum ColTlmon-Mode
Input (Note 8)

All MUX Inputs
and COM Input

GND-0.05

GND-O.OS

V

Maximum Common-Mode
Input (Note 8)

All MUX Inputs
and COM Input

Vcc + 0.05

Vee + O.OS

V

±Yt6

±%
±%

±%
±%

LSB

±Yt6

DC Common-Mode Error
Power Supply Sensitivity

Vcc = 5V ±5%

Vz.. lnternal
diode
breakdown
at V+ (Note 3)

15mAintoV+
MIN
MAX

IOFF' Off Channel Leakage
Current (Note 9)

6.3
8.5
On Channel = 5V,
Off Channel = OV

-200

On Channel = OV,
Off Channel = 5V

+200

2-243

co
~
:J>

Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic) .

LSB
V
V

-1

p,A
nA

+1

p,A
nA

c
oQ

co
~

...an
co

CI

o
C

CC
.....
N

Electrical Characteristics (Continued)
The following specifications apply for VCC = V+ = SV (no V+ on ADC08S2), fCLK = 2S0 kHz unless otherwise specified.
Boldface limits apply from TMIN to TMAX; all other limits TA = TJ = 2S'C.
ADC0852CCN
ADC0854CCN

an
co

CI

g

Parameter

Conditions

Typ
(Note 4)

CC

Tested
Limit
(Note 5)

Design
Limit
(Note 6)

Units

+1

p.A
nA

-1

p.A
nA

CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)
ION, On Channel Leakage
Current (Note 9)

On Channel = SV,
Off Channel = OV

+200

On Channel = OV,
Off Channel = SV

-200

DIGITAL AND DC CHARACTERISTICS
VIN(I), Logical "1" Input
Voltage

VCC = S.2SV

2.0

2.0

V

VIN(O), Logical "0" Input
Voltage

Vcc = 4.7SV

0.8

0.8

V

IIN(I), Logical "1" Input
Current

VIN =.Vcc

O.OOS

1

1

p.A

IIN(O), Logical "0" Input
Current

YiN = OV

-O.OOS

-1

-1

p.A

VOUT(I), Logical "1" Output
Voltage

Vcc = 4.75V
lOUT = - 360 p.A
lOUT = -10 p.A

2.4
4.5

2.4
4.5

V
V

VOUT(O), Logical "0" Output
Voltage

lOUT = 1.6 mA,
Vcc = 4.75V

0.4

0.4

V

lOUT, TRI-STATE® Output
Current (DO)

CS =

Logical" 1"
VOUT = 0.4V
VOUT = 5V

-0.1
0.1

--'3
3

-3
3

p.A

ISOURCE

VOUT Short to GND

-14

-7.5

-6.5

mA

p.A.

ISINK

VOUT Short to Vcc

16

9.0

8.0

rnA

Icc Supply Current
ADC08S2

Includes DAC
Ladder Current

2.7

6.5

6.5

rnA

Icc Supply Current
ADC0854 (Note 3)

Does not Include DAC
Ladder Current

0.9

2.5

2.5

rnA

2-244

AC Characteristics tr = tf = 20 ns, T A = 25°C
Symbol

fClK

tOl

Parameter

Conditions

Clock Frequency

MIN

(Note 12)

MAX

Rising Edge of Clock

Typ
(Note 4)

Tested

Design

limit

limit

(NoteS)

(Note 6)

Units

10

Cl

=

kHz

650

100 pF

400

kHz

1000

ns

to "DO" Enabled
tr

tSET-UP

Comparator Response

Not Including

Time (Note 13)

Addressing Time

2

+

1".s

1/fClK

%
%

Clock puty Cycle

MIN

40

(Note 10)

MAX

60

CS Falling Edge or

MAX

250

ns

MIN

90

ns

1000

ns

Data Input Valid to
ClK Rising Edge
tHOlO

Data'input Valid after
ClK Rising Edge

tpdlo tpdO

ClK Falling Edge to

MAX

Cl

=

100 pF

MAX

Cl

=
=

10 pF, Rl

650

Output Data Valid
(Note 11)
tlH, tOH

Rising Edge of CS to
Data Output Hi-Z

CL

= 10k
= 2k

125
500

100 pF, RL

250

ns

500

ns

(see TRI-STATE Test Circuits)
C'N

Capacitance of logic

5

pF

5

pF

Input
COUT

Capacitance of logic
Outputs

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when
operating the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to ground.
Note 3: Internal zener diodes (approx. 7V) are connected from V+ to GND and Vee to GND. The zener atV+ can operate as a shunt regulator and is connected
to Vee via a conventional diode. Since the zener voltage equals the AID's breakdown voltage. the diode ensures that Vee will be below breakdown when the

device is powered from V +. Functionality is therefore guaranteed for V + operation even though the resultant voltage at Vec may exceed the specified Absolute
Max of 6.SV. II is recommended that a resistor be used to limit the max current into V +.
Note 4: Typicals arB at 25°C and represent most likely parametric norm.

Note 5: Tested and guaranteed to National AOQl (Average Outgoing

Q~ality

level).

Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 7: Total unadjusted error includes comparator offset, DAC linearity, and multiplexer error. It is expressed in lSBs of the threshold DAC's input code.
Note 8: For V,Ne -);' V,Ne +) the output will be O. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input
voltages one diode drop below ground or one diode drop greater than the Vce supply. Be careful, during testing at low Vee levels (4.SV), as high level analog inputs
(SV) can cause this input diode to conduct-especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward
bias of either diode. This means that as long as the analog V,N or VREF does not exceed the supply voltage by more than SO mV, the output code will be correct. To
achieve an absolute 0 Voc to 5 Voe input voltage range will therefore require a minimum supply voltage of 4.950 Vee over temperature variations, initial tolerance

and loading.
Note 9: leakage current is measured with the clock not switching.
Note 10: A 40% to 60% clock duty cycle range ensures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of
these limits then 1.6 p.S ,; ClK Low,; 60 p.S and 1.6 p.S ,; ClK HIGH,; ...
Note 11: With CS low and programming complete, DO is updated on each falling ClK edge. However, each new output Is based on the comparison completed O.S
clock cycles prior (see Figure 5).
Note 12: Error specs are not guaranteed at 400 kHz (see graph: Comparator Error vs. fcud.
Nota 13: See text, section 1.2.
Note 14: Human body model, 100 pF discharged through a 1.S kO resistor.
Note 15: Because the reference ladder of the ADC0852 is internally connected to Vee, ladder resistance cannot be directly tested for the ADC0852. Ladder

current is inCluded in the ADCOBS2's supply current speCification.

2-245

•

Typical Performance Characteristics
Internal DAC Linearity
Error vs VREF Voltage.

1.5

0.50

Vcc=5V
IClK = 250 kHz
TA=25'C

...;-;;; 1.25
1.0

~

0:

t::

15

0.5
z
:::; 0.25

i!5
z

"'0

2
3
VREF (Vocl

1

4

'ClKi 250

Output Current vs

20

i...

15

1

5

........ ~vDC=l

::>

.

ISOURCE

10

Iso•• Voc=0.4V

it

3

Ii

2

u

1

..•

E

-

0
-100 -50
0
50
100
TEMPERATURE ('CI

4

ISa:

a:
::>
u

I:
::>

...

I.

._t~~~~

i"""'o~ ""'"
..... r--~ ....

1.0 Vcc=5V

~

p.5

30

0:

iii 20

kr

r

CC i4.5V

-

V L.
25'C

0

50

100

0

150

100 200 300 400 500 600
ICLK (kHzI

IREF. Reference
Current vs. Temp. ADC0854
2.0

!....
il'i
a:

,

a:
::>
u
~

1\

1.5

il'i.
a:

vt~.o ~oc

-

;-

.

I"'- i'

"~

Iba:

""-

1.0

-50-25 0 25 50 15 100 125
TEMPERATURE ('CI

-50-25 0 25 50 75100 125
TEMPERATURE ('CI

Icc. Power Supply
Current vs. fCLK. ADC0854*
1.5

--

-25'C

10

\,

150

Icc. Power Supply Current
vs. Temperature. ADC0854*
1.5

c

1_""

Ii;

VOC=~

5

~

c
a:
c

ISOURCE Voc=2.4V

!

0:

Comparator Offset vs
Temperature

vc =5V

:c
.§.

~

....

125'C

40

TEMPERATURE ('CI

25 Temperature

VR~g5V

0

0
-100 -50

5

Comparator Error vs fCLK

50 c-Vcc=5V

VREF =5.0V

:::;

. 0

.....
~
::>

~ ........

0:

c
~
~ 0.25

iii 0.15
~

60

"

;;;

c

....

Internal DAC Linearity
Error vs Temperature

!

.......a:a:z

Vcc=15V

@2~C

1.0

::>

u

E
... 0.5

~

::>

a:

IcLkJ50 JHZ

~='r

1

0
-75-50-25 0 25 50 75 100 125
TEMPERATURE ('CI

~

'0
0

100

200

300

400

500

IClKlkHzI
TLlH/5521-2

"For ADC0852 add IREF

2-246

Timing Diagrams

.

Data Input Timing
Data Output Timing
CLK

DATA OUT (00) _ _ _ _ .I
TlIH/5521-4

TlIH/5521-3

TRI-STATE Test Circuits and Waveforms
Vee

DO

vee

CS

~
~

vee10k

DATA
OUTPUT
CL

Vee

1"

90%
50%
10%

GND~OH
Vee
DO

VOL

10%
TlIH/5521-5

Leakage Test Circuit
ION

ADC0854

1 _ _ _ _,

:::

1

(OFF)

-----.CH3

TlIH/5521-6

2-247

II

ADC0852! ADC0854

&!%

cs'

elK "

DI..!!
NOTE 1

Vee

::1 =i: t I, II:

NOTE'~ CH2
IU

CH3 5

1

,

es

111,110

~

EOCI

•

•

JL
MRALLEL
XFRTO
lATCH

ANALOG
'.,

,

,

MUX
(MUX CODE 0, 0, 0)

• TO INTERNAL
• CIRCUITRY
7V ZENER

VREF 9
TO
I N P U T F INTERNAL
CIRCUITS

1
11
':'

BV",3OV

12

1

......

~'to~

LADDER AND DECODER

,

'=' AOND

Note 1: For ADC0852; 01 Is input directly to the 0 input of
ODD/SIGN, select: is forced to a "1", AaND and COM are internally tied to DGND, only Vee is brought out, VREF is intemally
tied to Vee, only CH2 and CH3 are brought out

7

DGNDA-,

INPUT PROTECTION-ALL LOGIC INPUTS
TLIH/5521-7

FIGURE 2. Detailed Block Diagram

ClK

...... ...... ...... ...... ...... ...... ...... ......

.-

...... ...... ...... ...... ...... ......

10

11

12

14

13

15

16

•

cs

ADCOB54

{m
DO

III
I\)
~

CD

ADCOB52

{'
DO

-11-11)1 I

I

ClK~
11

12

13

14

15

Tl/H/5521-12

Nate: Valid Output can change only on Falling Edge of eLK.

FIGURE 3. Timing Diagram

"S80~Q\f I~S80~Q\f

II

~~--~----~------------~------------------------~----~~
II)

~

C'\I

II)

CD

S

Functional Description
In the first cycle (Figure 48), one input switch and the invert·
er's feedback switch are closed. In this interval, the input
capacitor (C) is charged to the connected input (V1) less the
inverter's bias voltage (VB, approx. 1.2 volts). In the second
cycle (Figure 4b) these ,two switches are opened and the
other (V2) input's switch is closed. The input capacitor now
subtracts its stored voltage from the second input and the
,difference is amplified by the ihverter's open loop gain. The
C
inverter input (VB') becomes VB - (V1 - V2) C + C and
,
S
the output will go high or low depending on the sign of VB'·
VB·

1. 1 The Sampled-data Comparator

The ADC0852 and ADC0854 utilize a sampled-data com·
parator structure to compare the analog difference between
a selected .. +" and .. -" input to an 8·bit programmable
threshold.
This comparator consists of a CMOS inverter with a capaci·
tively coupled input (Figure 4). Analog switches connect the
two comparator inputs to the input capacitor and also con·
nect the inverter's input and output. This device :in effect
now has one differential input pair. A comparison requires
two cycles, one for zeroing the comparator and another for
making the comparison.
.

FIGURE 4. Sampled-Data Comparator

Vl--oJ'~'

• Vo = VB
• VonC = VI-VB
• ,Cs = Stray Input Node Cap.

ICS

V2-o

• VB = Inverter Input Bias Voltage
TUH/5521-8

FIGURE 4a. Zeroing Phase,

.~'1"~ ..

C
• VB,-VB = (V2- V l) C+Cs

. --Y t'
,~ ,

.

-A

• Vo = --[CV2-CV1]
C+ Cs
• VoisdependentonV2-Vl
TUH/5521-9

,

FIGURE 4b. Compare Phase

A

ViN(+)Vl~Cl
ViN(-)

-A

V2~J'

Vo =
[Cl (V2 - Vl) + C2 (V4 - Va)]
Cl+ C2+ CS
,

- ~A
Cl + C2 + Cs

Vo

A

*Vnt(-)

V3~C2

*Vnt(+)

V4~J'

[~aCl + ~ac21

• Comparator Reads VTH'from'lntemal DAC Differentially

TUH/5521-14

FIGURE 4c. Multiple Differential Inputs

2·250

.--------------------------------------------------------------------.~

c(')

Functional Description

(Continued)
In actual practice, the devices used in the AOCOB52/4 are a
simple but important expansion of the basic comparator described above. As shown in Figure 4c, multiple differential
comparisons can be made. In this circuit, the feedback
switch and one input switch on each capacitor (A switches)
'are closed in the first cycle. Then the other input on each
capacitor is connected while all of the first switches are
opened. The change in voltage at the inverter's input, as a
result of the change in charge on each input capacitor (Cl,
C2), will now depend on both input signal differences.

vide multiple analog channels with software-configurable
single-ended, differential, or pseudo-differential operation.
The analog signal conditioning required in transducer-input
and other types of data acquisition systems is significantly
simplified with this type of input flexibility; One device package can now handle ground referenced inputs as well as
signals with some arbitrary reference voltage.
On the AOCOB54, the "common" pin (pin 6) is used as the
"-" input for all channels in Single-ended mode. Since this
input need not be at analog ground, it can be used as the
,common line for pseudo-differential operation. It may be tied
to a reference potential that is common'to all inputs and
within the input range of the comparator. This feature is
especially useful in single-supply applications where the analog circuitry is biased to a potential other than ground.
A particular input configuration is assigned during the MUX
addressing sequence which occurs prior to the start of a
comparison. The MUX address selects which of the analog
channels is to be enabled, what the input mode will be, and
the input channel polarity. One limitation is that diffe~ential
inputs are restricted to adjacent channel pairs. For example,
channel 0 and 1 may, be selected as a differential pair but
they cannot act differentially with any other channel.

1.2 Input Sampling and Response Time
The input phases of the comparator relate to the device
clock (ClK) as shown in Figure 5. Because the comparator
is a sampling device, its response characteristics are somewhat different from those of linear comparators. The VIN( + )
input i,s sampled first (ClK high) followed by VIN(-) (ClK
lOw). The output responds to those inputs, one half cycle
later, on ClK's falling edge.
The comparator's response time to an input step is dependent on the step's phase relation to the ClK signal. If an
input step occurs too late to influence the most imminent
comparator decision, one more ClK cycle will pass before
the output is correct. In effect, the response time for the
VIN( +) input has a minimum of 1 ClK cycle + 1 /JoS and a
maximum of 2 ClK cycles + 1 /JoS. The VIN( -) input's delay
will range from 112 ClK cycle + 1 /JoS to 1.5 ClK cycles +
1 /JoS since it is sampled after VIN( + ).
The sampled inputs also affect the device's response to
pulsed signals. As shown in the shaded areas in Figure 5,
pulses that rise and/or fall near the latter part of a ClK halfcycle may be ignored.

The channel and polarity selection is done serially via the 01
input. A complete listing of the input configurations and corresponding MUX addresses for the AOCOB52 and AOCOB54
is shown in tables I and II. Rgure 6 illustrates the analog
connections for the various input options.
The analog input voltage for each channel can range from
50 mV below ground to 50 mV above Vee (typically 5V)
without degrading accuracy.

1.3 Input Multiplexer
A unique input multiplexing scheme has been utilized to pro-

A VIN( +) AND VrH( _) SAMPLED (ZEROINGI
B VIN(_) AND VrH(+) SAMPLED

VrN( +) AND VrH( _) FOR
NEXT COMPARISON
D OUTPUT UPDATED
BASED ON A AND B
E VIN( _) AND VrH( +) FOR
NEXT COMPARISON
OUTPUT BASED
ONCANDE

ClK

SAMPLING UNCERTAINTY FOR TRANSIENTST
ON VIN(+) INPUT DURING THIS TIME

L

SAMPLING UNCERTAINTY FOR TRANSIENTS
ON VrNH INPUT DURING THIS TIME
TL/H/5521-13

FIGURE 5. Analog Input Timing

2-251

c
C»
en
......
N

~

C

(')

c
C»
en
~

Functional Description
(Continued)
,
TABLE II. MUX Addressing: ADC0852
Single Ended MUX Mode

TABLE I. MUX Addrl!SSlnll: ADC0854
Single-Ended MUX ..,ode .
MUXAddress
SGLI
j)jf

0001
SIGN

Channel

SELECT

0

+

1

0

0

1

'0

1

1

1

o.

1

1

1

3

~

1

MUXAddress

0

~

1

0

-

1

1

+
+

MUXAddress

Channel

:

..

1

0

0

+

.,..

0

0

1

0

1

Q

0

1

1

2

3

+

-

,.-

+

SGLI
DIF

0001

0
0

0

1

0

+

-

1

-

+

SIGN

,..

+
.,

I

,

.4 Single-End~d

,

0 - +.

4 Pseudo-Differential

0-+

,-+

,._+

~- +

2-+

3- +

3-+

V8IU~

CO!'!H

~

,.

1

Differential MUX Mode

;

·0

r

0

COM Is internally tied to A GND

Channel

-

SIGN

-

+

$ELECT

SIGN

0001

-

MUXAddress

0001

SGLI'
DIF

+

Differential MU~ Mode

SGLI
DIF

COM

+
i

Channel

*

2 Differe!1tla!
"

COM (-I

Mixed Mode

{- +
D"l_

,0, , {~ +(-1

-

2- +

1 - -(+)
+(-1
2,3 1{~
:--(+)

3- +

~ COM(-)

, ,.

VB/u":" .

*

FIGURE 6. All8log InP!lt Multiplexer Options for the ADC0854

...

2-252

TUH/5521-15

l:-

Functional Description

C

(Continued)

(')

be done indefinitely, without reprogramming the device, as
long as CS remains low. Each new comparator decision will
be shifted to the output on the falling edge of the clock.
However, the output will, in effect, "lag" the analog input by
0.5 to 1.5 clock cycles because of the time required to make
the comparison and latch the output (see Figure 5).
8. All internal registers are cleared when the CS line is
brought high. " another comparison is desired CS must
make a high to low transition followed by new address and
threshold programming.

2.0 THE DIGITAL INTERFACE
An important characteristic of the ADC0852 and ADC0854
is their serial data link with the controlling processor. A serial communication format eliminates the transmission of low
level analog signals by locating the comparator close to the
signal source. Thus only highly noise immune digital signals
need to be transmitted back to the host processor.
To understand the operation of these devices it is best to
refer to the timing diagrams (Figure 3) and functional block
diagram (Figure 2) while following a complete comparison
sequence.
1. A comparison is initiated by first pulling the CS (chip select) line low. This line must be held low for the entire addressing sequence and comparison. The comparator then
waits for.a start bit, its MUX assignment word, and an 8-bit
code to set the internal DAC which supplies the comparator's threshold voltage (VTH).
2. An external clock is applied to the ClK input. This clock
can be applied continuously and need not be gated on and
off.
3. On each rising edge of the clock, the level present on the
DI line is clocked into the MUX address shift register. The
start bit is the first logic "1" that appears on this line. All
leading zeroes are ignored. After the start bit, the ADC0852
expects the next 2 bits to be the MUX assignment word
while the ADC0854, with more MUX configurations, looks
for 3 bits.

I\)

"l:C

(')

o

CD
U1
~

3.0 REFERENCE CONSIDERATIONS I RATIOMETRIC
OPERATION
The voltage applied to the "VREF" input of the DAC defines
the voltage span that can be programmed to appear at the
threshold input of the comparator. The ADC0854 can be
used in either ratiometric applications or in systems with
absolute references. The VREF pin must be connected to a
source capable of driving the DAC ladder resistance (typ.
2.4 ko') with a stable voltage.
In ratiometric systems, the analog input voltage is normally
a proportion of the DAC's or AID's reference voltage. For
example, a mechanical position servo using a potentiometer
to indicate rotation, could use the same voltage to drive the
reference as well as the potentiometer. Changes in the value of VREF would not affect system accuracy since only the
relative value of these signals to each other is important.
This technique relaxes the stability requirements of the system reference since the analog input and DAC reference
move together, thus maintaining the same comparator output for a given input condition.
In the absolute case, the VREF input can be driven with a
stable voltage source whose output is insensitive to time
and temperature changes. The lM385 and lM336 are good
low current devices for this purpose.

4. Immediately after the MUX assignment word has been
clocked in, the shift register then reads the next eight bits as
the input code to the internal DAC. This eight bit word is
read lSB first and is used to set the voltage applied to the
comparator's threshold input (internal).
5. After the rising edge of the 11 th or 12th clock (ADC0852
or ADC0854 respectively) following the start bit, the comparator and DAC programming is complete. At this point the
DI line is disabled and ignores further inputs. Also at this
time the data out (DO) line comes out of TRI-STATE and
enters a don't care state (undefined output) for 1.5 clock
cycles:
6. The result of the comparison between the programmed
threshold voltage and the difference between the two selected inputs (VIN (+) - VIN ( -)) is output to the DO line on
each subsequent high to low clock transition.
7. After programming, continuous comparison on the same
selected channel with the same programmed threshold can

The maximum value of VREF is limited to the Vee supply
voltage. The minimum value can be quite small (see typical
performance curves) allowing the effective resolution of the
comparator threshold DAC to also be small (VREF = 0.5V,
DAC resolution = 2.0 mV). This in turn lets the designer
have finer control over the comparator trip point. In such
instances however, more care must be taken with regard to
noise pickup, grounding, and system error sources.

r--;::::::;t=;T'V

r-----;:=~::::;-T"
Vee

Vee

It

jSOU~'

ADC0a54

:- +

o

CD
U1

OV·1.25V

You

ADCDa54

VRu~ 1.25V

+

GN.

GNO

~

TLlH/5521-16

a) Ratiometric

b) Absolute with a Reduced Span
FIGURE 7. Referencing Examples

2-253

Ell

~ r-------------------------------------------------------------~

In

8
Q

"-'lM.-t---tYIHI+)

Vee

+ 5V

~10,.F

TLlH/5521-21

FIGURE 12. Protecting the Analog Input

fII
ADCOB52
GND
~ L-____________~F.C~~fC~H~I------------~

2
3
-----......-.
ANALOG INPUT

TLlH/5521-22

FIGURE 13. One Component Window Comparator
Requires no additional parts. Window comparisons can be accomplished by
inputting the upper and lower window limits into 01 on successive comparisons and observing the two outputs:
Two high outputs -+ input> window
Two low outputs

-)0

input < window

One low and one high -+ input Is wijhin window

2·255

..,.
."

co

CI

oQ

Typical Applications (Continued)

~
."

5V

nOVae
HI

co

g
c(

DO 10
4.711

CHO

CHI

COM

5V

2.73V+l0mV/'C
lk

2.73V

LM335
TEMP
SENSOR

2k
OffSET

4k
2k
RJLLSCALE

LM1D3
3.3V

rk

4k

TLlH/552t -23

FIGURE 14. Serial Input Temperature Controller
Note 1: ADC0854 does not require constent service from computer. Self controlled aller one write 10 01 if CS remains low.
Note 2: U,: Solid State Relay, Polter Brumfield #EOM10B22
Note 3: Set Temp via. OJ. Range: 0 to 125'C
33D

10V~~---'WII------"

Uk

DO 10

TL/H/5521-24

FIGURE 15. Load Cell Limit Comparator
• Differential Input ellimlnates need for Instrumentation amplifier
• A total of 4 load cells can be monitored by ADC0854

2-256

E;

Typical Applications (Continued)

o
C)
CD
U1

5V

• Vee

8 Vee

DO 8

DO 8

V...

N
......
>
o
o
C)

CD
U1

.;:..

ADe~

UND

GND

~~-----------f.~~f.~~--------~

~ ~------------~~~~----------~

IDDk

IDDk

IDDk

Ik

01
2N2222

TLlH/5521-26
TUH/5521-29

• 01 used in inverted mode for low VSAT

Hysteresis band

= 50 mV

FIGURE 16. Adding Comparator Hysteresis
250 kHz

5V
Vee

, r
TRIGGER
INPUT

av

Jiii

~_ _ _D:::0+=-6

~

VREF

111 000

11-

U- ov
lN4148
ADCD852

CHO
2

CHI
3

\jC

----5V

• --- VTH

OV

fI
TL/H/5521-27

FIGURE 17. Pulse-Width Modulator
• Range of pulse.widths controlled via Rio CI

2·257

~
II)

8

,---------------------------------------------------------------------------------,
Typical Applications (Continued)

~

250, k7HZ

II)

co

C)

8
5V

::

cc

.,,.. ... "

';.

~:~.

L.)>--~-+-I:..;_.;.::.i+>--....::DOT6~5V.I\ll1\aoll\k~10-k-4·~~~
ADCOB52

10k

4

.t_

,

"

1 F

r-~----~-.+.
I:~I----~CI;~·---~-~I:CU~-----.

C'I

g

I.

~-'~~58
.. ' ":'

GNO
~____________~C~HO~C~H~l----------~

2

-=::3

lk

~, lN4148

8200

5V
Tl/H/5521-28

FIGURE 18. Serial Input 8-Blt DAC

Ordering Information
Part Number

Analog Input'
Channels

Total
Unadjusted Error

ADC0852CCN

2

±1

N08E

O~Cto

ADC0854CCN

4

±1

N14A

O'Cto70"C

Package

Temperature
Range

,

'"

,
'

.'

2-258

.

70"C

l>

C

(")

o
co
o
G)

f}1National Semiconductor

.....

);

ADC08061 I ADC08062
500 ns AID Converter with S/H Function
and Input Multiplexer
General Description

C

g

co
o

G)

N

KeY,Specifications

Using a patented multi-step AID conversion technique, the
8-bit ADC08061 and ADC08062 CMOS ADCs offer 500 ns
(typ) conversion time, internal sample-and-hold (S/H), and
dissipate only 125 mW of power. The ADC08062 has a twochannel multiplexer. The ADC08061/2 family performs an
8-bit conversion using a 2-bit voltage estimator that generates the 2 MSBs and two low-resolution (3-bit) flashes that
.generat~ th~ 6 LSBs.
Input track-and-hold circuitry eliminates the need for an external·sample-and-hold. The ADC08061/2 family performs
accurate conversions of.tull-scale input signals that have a
frequency range of DC to 300 kHz (full-power bandwidth)
withoui need of aOn external S/H.
. The digital interface has been designed to ease connection
to microprocessors and allows the parts to be I/O or memo- .
ry mapped.

rl Resolution

• Conversion Time

.. Full Power Bandwidth
• Throughput rate
• Power Dissipation
• Total Unadjusted Error

8 bits
560 ns max (WR-RD Mode)
300 kHz
1.5 MHz
125 mW max
±% LSB and ±1 LSB

Features
III 1 or 2 input channels

•
•
•
•

No external clock required
Analog input voltage range from GND to V+
Overflow output available for cascading (ADC08061)
ADC08061 pin-compatible with the industry standard
ADC0820

Applications
. • Mobile telecommunications
• Hard disk drives
• Instrumentation
• Hi9.h-speed data acquisition systems

Block Diagram

,......l=:;---;::==::::;"1: orl'

DB7 (MSB)
DB6
DBS
DB4
DB3
DB2

OBI
DBO (lSB)

.v'

tNT

GND

MODE
'AOCOB061

CS

RD WR/RDY AO"
TUH/ll0B6-1

. "ADCOB062

2-259

N

B
c
~
.CD
Q

CO
Q

o
C
cc

Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor. Sales
Office/Distributors for availability and specifications.
Supply Voltage (V+)
6V
Logic Control Inputs
Voltage at Other Inputs and Outputs
Input Current at Any Pin (Note 3)

Lead Temperature (Note S)
J Package (Soldering, 10 sec.)
N Package (Soldering, 10 sec.)
WM Package (Vapor Phase, 60 sec.)
WM Package (Infrared; 1S sec.)
ESD Susceptibility (Note 6) .

-0.3VtoV+ + 0.3V
~0.3VtoV+ + 0.3V
SmA

Package Input Current (Note 3)

Operating Ratings (Notes 1 & 2)

20mA

Power Dissipation (Note 4)
J Package
N Package
WM Package
Storage Temperature

+300"C
+ 260"C
+21S·C
+ 220"C
2kV

TMIN ~ TA ~ TMAX

Temperature Range
ADCOB061/2BIN,
ADCOB061/2CIN,
ADCOB061/2BIWM,
ADCOB061/2CIWM
ADCOB061CMJ, .

B7SmW
B7SmW
B7SmW
.- 6S·C to + 1S0·C

ADCOB061CM~/BB3

.'

-40·C
-SS·C

Supply Voltage, (V +)

S: TA ~ BS·C

~

TA

~

12S·C

4.SVtoS.SV

Converter Characteristics

.

The following specifications apply for RD Mode, V+ = SV, VREF+ = SV, and VREF- = GND unless'otherwise specified.
Boldfac.limits apply for TA = T .. ;= TMIN to TMAX; all other limits TA ~ TJ = 2S·C.
Symbol
INL

Parameter

Conditions

Typical
(Note 7)

ADCOB061 12
BIN,BIWM

Inlegral Non Linearity

ADCOB061/2
CIN,CIVIIM, CMJ
TUE

Total Unadjusted Error

. ADCOB061 /2
BIN;BIWM
ADCOB061/2
CIN; CIWM, CMJ

Missing Codes
Reference Input Resistance

700
700

,Limits
(Note 8)

Units
(Limit)

±%

LSB(max)

±1

LSB(max)

±%

LSB(max)

±1

LSB (max)

0

Bits (max)

500
1250

o (max)

O(min)

VREF+

Positive Reference
Input Voltage

YRBPY+ .

V (min)
V (max)

VREF-

Negative Reference
Input Voltage

QND
YRBP+

V (min)
V (max)

VIN

Analog
Input Voltage

(Note 10)

QND - 0.1
Y+ + 0.1

V (min)
V (max)

On Channel Input
Current

On Channel Input = SV,
Off Channel Input ='OV (Note 11)

-0.4

-20

p.A (max)

On Channel Input = OV,
Off Channel Input = SV (Note 11)

-0.4

-20

p.A(max)

±1j,s

±%

LSB(max)

PSS

Powe~ Supply Sensitivity
"

.

v+ = SV ±S%, VREF = 4.7SV
All Codes Tested

Effective Bits

7.8

Bits

Full-Power Bandwidth

300

kHz

THD

Total Harmonic Distortion

O.S

%

SIN

Signal-to-Noise Ratio

SO

dB

IMD

Intermodulation Distortion

SO

dB

2-260

)ao

C

AC Electrical Characteristics
The following specifications apply for V+ = 5V, tr = tf = 10 ns, VREF+ = 5V, VREF- = OV unless otherwise specified.
Boldface limits apply for TA = T.. = TMIN to TMAX; all other limits TA = TJ = 25'C.
Symbol
tWR

Parameter
Write Time

Conditions
Mode Pin to V+;
(Figures 2a, 2b, and 3)

lAD

Read Time (Time from Falling Edge
of WR to Falling Edge of RD)

Mode Pin to V+; (Figure 2a)

IADw

RDWidth

Mode Pin to GND; (Figure 4)

tCONV

WR-RD Mode Conversion Time

Mode Pin to V +; (Figure 2a)

(twA

+ lAD + tACC1)

Typical
(Note 7)

Limits
(Note 8)

Units
(Limit)

100

100

ns(min)

350

350

ns(min)

200
400

250
400

ns(min)
ns(max)

500

560

ns(max)

RD Mode Conversion Time

Mode Pin to GND; (Figure 1)

655

900

ns(max)

tACCO

Access Time (Delay from Falling Edge
of RD to Output Valid)

CL s: 100 pF
Mode Pin to GND; (Figure 1)

640

900

ns(max)

tACCl

. Access Time (Delay from Falling Edge
of RD to Output Valid)

45
50

110

ns(max)

);:
C
oo
00

o0)

25
30

90

ns(max)

30

60

ns(max)

30

70

ns(max)

520

690

ns(max)

50

95

ns(max)

45

95

ns(max)

25

45

ns(max)

s: IiNTL

tACC2

Access Time (Delay from Falling Edge
of RD to Output Valid)

CL s: 10pF
CL = 100pF
lAD > 1iN'f[; (Figures 2b and 4)

IoH

TRI-STATE® Control (Delay from
Rising Edge of RD to HI-Z State)

RL = 3 ko., CL = 10 pF

t1H

TRI-STATE Control (Delay from
Rising Edge of RD to HI-Z State)

RL = 3 ko., CL = 10 pF

IiNTL

Delay from Rising Edge of
WR to Falling Edge of INT

(Figures 2b, and 3)
Mode Pin = V+,CL = 50pF

IiNTH

Delay from Rising Edge of
RD to Rising Edge of INT

CL = 50 pF; (Figures 1, 2a, 2b, and 4)

IiNTH

Delay from Rising Edge of
WR to Rising Edge of INT

CL = 50 pF; (Figure 3)

tROY

Delay from CS to RDY

Mode Pin = OV, CL = 50 pF,
RL = 3 ko. (Figure 1)

tiD

Delay from INT to Output Valid

RL = 3 ko., CL = 100 pF; (Rgure 3)

tRI

Delay from RD to INT

Mode Pin = V + , lAD

tN

Time between End of RD
and Start of New Conversion

(Figures 1, 2a, 2b, 3 and 4 )

s: IiNTL; (Figure 2a)

0

15

ns(max)

60

115

ns(max)

50

60

ns(min)

tAH

Channel Address Hold Time

(Figures 1, 2a, 2b, 3 and 4 )

10

60

ns(min)

tAS

Channel Address Setup Time

(Figures 1, 2a, 2b, 3 and 4 )

0

0

ns(max)

~

CS Setup Time

(Figures 1, 2a, 2b, 3 and 4)

0

0

ns (max)

(Figures 1, 2a, 2b, 3 and 4 )

0

0

ns (min)

tcsF/

CS Hold Time

CVIN

Analog Input Capacitance

25

COUT

Logic Output Capacitance

5

pF

CIN

Logic Input Capacitance

5

pF

2-261

00

0)

N

leRD

CL s: 10pF
CL = 100pF
Mode Pin to V+, lAD
(Figure2a)

g
o
....

pF

fII

DC Electrical Characteristics The following specifications apply for V+

= SV unless otherwise specified.

Boldface limits apply for TA = TJ = TMINto TMAX; all other limits TA = TJ = 2SoC.
Symbol
VIH

VIL

IIH

IlL

VOH

Conditions

Parameter
Logic "1" Input Voltage

Logic "O"lnputVoltage

Logic "1" Input Current

Log,ic "0" Input Current

Logic "1" Output Voltage

typical
(Note 7)

V+ = S.SV
Mode Pin
ADC08062
CS, WR, RD, AO Pins
ADC08061
CS, WR, RD Pins
V+ = 4.SV
Mode Pin
ADC08062
CS, WR, RD, AO Pins
ADC08061
CS, WR, RD Pins,
VIH = 5V
CS, RD, AO Pins
WRPin
Mode Pin
VIL = OV
CS, RD, WR, AO Pins
Mode Pin

O.OOS
0.1
SO

Logic "0" Output Voltage

TRI-STATE Output Current

4

3.5

V (min)

3.0

V (min)

2.2

V (min)

1.5

V (max)

0.4

V (max)

0.7

V (max)

1
3
200

p.A (max)
p.A (max)
p.A(max)

p.A(max) "

-2

V+ = 4.?SV

2.4

V (min)

4.5

V (min)

0.4

V (max)

V+ = 4.?SV
lOUT = 1.6 mA
DBO-DB?, OFL, INT, RDY

10

Units
(Limit)

-O.OOS

lOUT = - 360 p.A
DBO-DB?, OFL, INT
lOUT = -10 p.A
DBO-DB?, OFL, INT
VOL

Limits
(Note 8)

VOUT = S.OV
DBO-DB?, RDY

0.1

3

p.A(maX)

VOUT = OV
DBO-DB?, RDY

-0.1

-3

p.A (max)

-26

-6

rnA (min)

24

7

mA(min)

11.S

25

mA(max)

ISOURCE

Output Source Current

Your

ISINK

Output Sink Current

VOUT = SV
DBO-DB?, OFL, INT, RDY

Ic

Supply Current

CS = WR = RD = 0

= OV
DBO-DB?, OFL, INT

,

2-262

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

»
c
oo

the device beyond its specified operating ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee performance limits.
For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some
performance characteristics may degrade when the device is not operated under the listed test conditions.

en
.....
......

Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.

c
oo

Electrical Characteristics (Contjnued)

Note 3: When the input voltage (VIN) at any pin exceeds the power supply voltage (VIN < GND orVIN> V+), the absolute value of the current althat pin should be
limited to 5 rnA or less. The 20 rnA package input current specification limits the number of pins that can exceed the power supply boundaries with a 5 rnA current
limit to four.

Note 4: The power dissipation of this device under normal operation should never exceed 875 mW (Quiescent Power Dissipation + the loads on the digital
outputs). Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (e.g., when any input or
output exceeds the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX (maximum junction

temperature), fJ JA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature
is PDmax = (TJMAX - TAllfJJA or the number given in the Absolute Maximum Ratings, whichever is lower. The table below details TJMAX and fJJA for the various
packages and versions of the ADC06061 12.
Part Number

TJMAX

8JA

ADC08061/2BIN
ADC08061/2CIN
ADC08061/2BIWM
ADC08061/2CIWM

105
105
105
105

51
51
85
85

Note 5: See AN-450 "Surface Mounting Methods and Their Effect on Product Reliability" for other methods of soldering surface mount devices.
Note 6: Human body model, 100 pF discharged through a 1.5 kfl resistor.

Note 7: Typicals are at 25°C and represent most likely parametric norm.
Note 8: Limits are guaranteed to National's AOQL (Average Output Quality Level).
Note 9: Total unadjusted error includes offset, full-scale, and linearity errors.

Note 10: Two on-chip diodes are tied to each analog input and are reversed biased during normal operation. One is connected to V + and the other is connected to
GND. They will become forward biased and conduct when an analog input voltage is equal to or greater than one diode drop above V+ or below GND. Therefore,
caution should be exercised when testing with V+ ~ 4.5V. Analog inputs with magnitudes equal to 5V can cause an input diode to conduct, especially at elevated

temperatures. This can create conversion errors for analog signals near full-scale. The specification allows 50 mV forward bias on either diode; e.g., the output
code will be correct as long as the analog input signal does not exceed the supply voltage by more than 50 mY. Exceeding this range on an unselected channel will
corrupt the reading of a selected channel. An absolute analog input signal voltage range of OV ,; VIN ,; 5V can be achieved by ensuring that the minimum supply

voltage applied to V+ is 4.950V over temperature variations, initial tolerance, and loading.
Note 11: Off-channel leakage current is measured after the on-channel selection.

2-263

CO

o

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CO

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en

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o

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o

,---------------------------------------------------------------------------------,
TRI-STATE Test Circuits and Waveforms

g
~
....

v+

~

v+

Ro

g
cc

1-....--............0

DATA
OUTPUT

, GND

IH

~

3kn

: 'VOH "
DATA OUTPUTS
"
GND
'

90%

,

TL/H/ll086-2

TL/H/ll088-4

t,.

=

10 ns

tOH. CL = 10 pF

tOH

v+

v+
v+
3kn

, '--=:F:GND

DATA

t-~~---o OUTPUT

v+

oH

DATA OUTPUTS
,

V
OL

10%

TLlH/ll088-5

1L1H/ll088-3

I, = 10 ns

Timing Diagrams

RDY

-------------<

DATA B

>--

MULTIPLEXER CHANNEL ADDRESS

TL/H/ll086-6

FIGURE 1. RD Mode (Mode Pin Is Low)

2·264

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Timing Diagrams (Continued)

Q)

o
c:n
......

......
):le
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Q)

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N

't---+-r ----------------{

DATA B

}-

MULTIPLEXER CHANNEL ADDRESS

TL/H/110B6-7

FIGURE 2a. WR-RD Mode (Mode Pin Is High and tAD

,;; tooL>

----------------{

DATA B

}-

MULTIPLEXER CHANNEL ADDRESS

TL/H/110B6-B

FIGURE 2b. WR-RD Mode (Mode Pin is High and tAD

2-265

> tooL>

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Timing Diagrams

(Continued)

(,,)

~

cs

.......
.,...
CD

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Ro

(,,)

C

_____________ <

D~A

ADDR

MULTIPLEXER CHANNEL ADDRESS

E

TL/H/11086-10

FIGURE 4. RD Mode (Pipeline Operation) (Mode Pin is Low and

2-266

tROw must be between 200 ns and 400 ns)

r--------------------------------------------------------------------,~

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Typical Performance Characteristics
8~ r.:.::r--r~"--r--:--'
750

OHset Error vs .
Reference Voltage

Linearity Error vs
Reference Voltage

tCRD vs Temperature

D.6

1---+---,--+--1--7'1'---1

_

OA

I'

0.3

600

I!l

0.3

t;

0.2

a
~

O.1

o

550 '---:c-"-_......._'---:c-"-_-'
-100
'-50
50
100
150

o

AMBIENT TEMPERATURE(OC)

Supply Clirrent
vs Temperature

o

5 .

2

Logic Threshold
vs Temperature
10

v·:rv-- -Y+=5.0V

1.3

1

-100

-50

0

50

100

1.0
-100

150

1

20

~

-10

~

1':

-

rr-

1.2

§ -20
-10

.....

-40
-50

TEMPERATURE(OC)

0

50

4

Output Current
vs Temperature

Y+=5.5V

6L-~_~_L-~_~

2

40

u

g

CD

.........

REFERENCE .VOLTAGE (V)

L5

:E
!:l

........

o
1

100

150

-100·

TEMPERATURE (OC)

-50

---

0

Y+=5V

f--

50

'sauRCE

100

150

TEMPERATURE (OC)

TLlH/ll086-24

Connection Diagrams
V,N
DBO

Ne

Vllt1
DBO

DBI

OFL

DBI

V,N2

DB2

DB7

DB2

DB?
DB6

V+

Ai1

DB3

DB6

DB3

iii/RDY

DBS

iii/ROY

DBS

MODE

DB4

MODE

DB4

Rii
iNf

CS

Rii

9

12

VREF+

iN'i

CS
VRE~+

GND

10

11

VREr-

GND

VREr-

TL/HI11066-14

TLlH/ll066-1S

Dual-In-Llne and Wide-Body
Small-outllne
Packages J20A, N20A or M20B

Dual-In-Llne and Wide-Body
Smail-Outline
Packages N20A or M20B

Ordering Information
Industrial (- 40'C ~ T A ~ 85°C)

Package

ADCOB061 BIN, ADCOB061 CIN,
ADCOB062BIN, ADCOB062CIN

N20A

ADCOB061 BIWM, ADCOB061 CIWM,
ADCOB062BIWM, ADC08062CIWM

M20B

ADCOB061 CMJ,
ADCOB061CMJ/B83,5962

J20A

2-267

c

(")
Q

0.1

REFERENCE VOLTAGE (V)

16 ',---,--'..,--r--,--,

);

V+=5V

T,,=250 C

."\

ill

;.

"~

I~

i! ' 650 f----51'7:::h"c.-b""-+-'-I

\

T,,=25OC

1M

~ 700

0.5

V+=5V

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Pin Description
VIN, VIN1-8 These are analog inputs. The input range is
GND-50 mV S; VINPUT S; V+ + 50 mY. The
ADC08061 has a single input (VIN) and the
ADC08062 has· a two-channel multiplexer
(VIN1-2)·
DBO-DB7 TRI-STATE data outputs-bit 0 (LSB) through
bit 7 (MSB).

These are the reference voltage inputs. They
may be placed at any voltage between GND 50 mV and V+ + 50 mY, but VREF+ must be
greater than VREF-. Ideally, an input voltage
equal to VREF- produces an output code of 0,
and an input voltage greater than VREF+ 1.5 LSB produces an output code of 255.

WR-RD Mode (Logic high applied to MODE
pin)
WR: With CS low, the conversion is started on
the falling edge of WR. The digital result will be
strobed into the output latch at the end of conversion (see Figures 2a, 2b, and 3).

For the ADC08062, an input voltage on any unselected input that exceeds V + by more than
100 mVor is below GND by more than 100 mV
will create errors in a selected channel that is
operating within proper operating conditions.

WR/RDY

MODE

RD

This is the active low Chip Select input. A logic
low signal applied to this input pin enables the
RD and WR inputs. Internally, the CS signal is
ORed with RD and WR signals.

RD Mode (Logic low applied to MODE pin)
ROY: This is an open drain output (no internal
pull-up device). RDY will go low after the falling
edge of CS and return high at the end of conversion.
Mode: Mode (RD or WR-RD) selection inputThis pin is pulled to a logic low through an internal 50 /LA current sink when left unconnected.
RD Mode is selected if the MODE pin is left
unconnected or externally forced low. A complete conversion is accomplished by pulling RD
low until output data appears.
WR~RD Mode is selected when a high is applied to the MODE pin. A conversion starts with
the WR signal's risipg edge and then using RD
to access the data.
WR-RD Mode (logic high on the MODE pin)
This is the active low Read input. With a logic
low applied to the CS pin, the TRI-STATE data
outputs (DBO-DB7) will be activated when RD
goes low (see Figures 2a, 2b and 3).
RD Mode (logic low on the MODE pin)
With CS low, a conversion starts on the falling
edge of RD. Output data appears on DBO-DB7
at the end of conversion (see Figures 1 and 4).

INT

This is an active low output that indicates that a
conversion is complete and· the data is in the
output latch. INT is reset by the rising edge of
RD.

GND

This is the power supply ground pin. The
ground pin should be connected to a "clean"
gro'und reference point. :

Overflow Output. If the analog input is higher
than VREF+ - % LSB, OFL will be low at the
end of conversion. It can be used when cascading two ADC08061 s to achieve higher resolution (9 bits). This output is always active and
does not go into TRI-STATE as DBO-DB7 do.
When OFL is set, all data outputs remain high
when the ADC08061 's output data is read.
NC

No connection.

AO

This logic input is used to select one of the
ADC08062's input multiplexer channels. A
channel is selected as shown in the table below.

V+

2-268

ADC08062
AO

Channel

0
1

VIN1
VIN2

Positive power supply voltage input. Nominal
operating supply voltage is + 5V. The supply
pin should be bypassed with a 10 /LF bead tantalum in parallel with a 0.1 ceramic capacitor.
Lead length should be as short as possible.

Application Information
1.0 FUNCTIONAL DESCRIPTION
The ADCOB061 and ADCOB062 perform an 8·bit analog·to·
digital conversion using a multi-step flash technique. The
first flash generates the five most significant bits (MSBs)
and the second flash generates the three least significant
bits (LSBs). Figure 5 shows the major functional blocks of
the ADC08061/2's multi-step flash converter. It consists of
an over-encoded 21jz-bit Voltage Estimator, an internal DAC
with two different voltage spans, a 3-bit half-flash converter
and a comparator multiplexer.
The resistor string near the center of the block diagram in
Figure 5 forms the internal main DAC. Each of the eight
resistors at the bottom of the string is equal to 1/256 of the
total string resistance. These resistors form the LSB Ladder and have a voltage drop of 1/256 of the total reference
voltage (VREF+ - VREF-) across them. The remaining resistors make up the MSB Ladder. They are made up of
eight groups of four resistors connected in series. Each
MSB Ladder section has Va of the total reference voltage
across it. Within a given MSB Ladder section, each of the
MSB resistors has 8/256, or 1hz of the total reference

voltage across it. Tap pOints are found between all of the
resistors in both the MSB and LSB Ladders. Through the
Comparator Multiplexer these tap pOints can be connected,
in groups of eight, to the eight comparators shown at the
right of Figure 5. This function provides the necessary reference voltages to the comparators during each flash conversion.
The six comparators, seven-resistor string (estimator DAC),
and Estimator Decoder at the left of Figure 5 form the Voltage Estimator. The estimator DAC connected between
VREF+ and VREF- generates the reference voltages for
the six Voltage Estimator comparators. These comparators
perform a very low resolution AID conversion to obtain an
"estimate" of the input voltage. This estimate is then used
to control the Comparator Multiplexer, connecting the appropriate MSB Ladder section to the eight flash comparators. Only 14 comparators, six in the Voltage Estimator and
eight in the flash converter, are needed to achieve the full
eight-bit resolution, instead of 32 comparators that would be
needed by traditional half-flash methods.

VIN

~U+O-~--~----------~::::~~----'

13/16

11/16

DB7

...
D::

DB6

C

...
0

DB5

U

9/16

C

D::

7/16

~
:::Ii

8/256

Vl

7/256

...
i=

TRI-STATE
OUTPUT
BUFFER

DB4
DB3
DB2
DB1

6/256

8

DBO

5/16
5/256

3/16

4/256
I
I

1/256

I
I
I

--"

VRUTL/H/ll0B6-18

FIGURE 5. Block Diagram of the ADC08061 12 Multl·Step Flash Architecture

2-269

Application Information (Continued)
2.1 RDMode

A conversion begins with the Voltage Estimator comparing
the ~nalog input signal against the six tap voltages on the
estimator DAC. The estimator decoder then selects one of
the groups pf tap pOints along the MSB Ladder. These eight
tap pOints are then connected to the eight flash comparators. For example, if the analog input signal applied to VIN is
betWeen 0 and 3f.. of VREF (VREF = VREF+ - VREF-), the
estimator decoder instructs the comparator multiplexer to
select the eight'tap pOints between 8/256 and 2/8 of VREF
and connects them to the eight flash comparators. The first
flash conversion is now performed, producing the five MSBs
of data.
"
,

With a Iqgic low ,applie,d to t!1e MPDE pin" the cqnverter is
set to ,Read mode. In this configuration (see Figure 1), a
complete version"i,~ done by pulling AD low, and holding
low, until the conversion is complete ,and output data ap,
pears. This typically takes ,6,55 ns~ The rnT (interrupt) line
goes l,ow at the end of ~o(lversion'. A typical delay of 50 ns is
needed between the rising edge ,of RD (after the end of a
conversion) and the start of the, next conversion (by pullin,g
AD low). The RDY output goes low after the falling edgll of
CS and goes high at the ",nd-of-conversion. It can be used
to signal processor that 'the converter is 'bLisy or serve as a
system Transfer Acknowledge Signal. For the ADC08062
the datagenerated,by the firSt conversion cycle after powerup is from an unknown channel.,
',
,

a

The remaining three LSBs are generated next using the
same eight ,comparators that were used for the first flash
conversion. As determined by the results of the MSB flash,
a,vqltage from the MSB Ladder equivalent to the magnitude
of the five MSBs is subtracted from the analog input voltage
as, the upper switch is moved from position one to position
two: The resulting remainder voltage is applied to the eight
flash comparators and, Yiith the lower switch in position two,
compared with the eight tap pOints from the LSB Ladder.

2.2 RD Mode Plpellned Operation
Applications that require shorter AD pulse widths than those
used in tlie Read m'ode as described above can be
achieved by setting AD's width between 200 ns-400 ns
(Figure 4). AD pulse widths outside this range will create
conversion linearity errors. These errors are caused by exercising internal interface logic circuitry using CS andlor AD
during a conversion.
When AD goes low, a conversion is initiated and the data
from the previous conversion is available 6n the DBO-DB7
outputs. Aeading DO-D7 for the first two times after powerup produces random data. The data will be valid during the
third AD pulse that occurs after the first conversion.

By using the same eight comparators for both flash conversions, the number of comparators needed by the multi-step
converter is significantly reduced when compared to standard half-flash techniques.
Voltage Estimator errors as large as Y16 of VREF (16 LSBs)
will be corrected since the flash comparators are connected ,
to ladder voltages that extend beyond the range specified
by the Voltage Estimator. For example, if 7/16 VREF < VIN <
9/1. VREF the Voltage Estimator's comparators tied to the
tap pOints below o/t. VREF will output "1"s (000111). This is
decoded by the estimator decoder to "10". The eight flash
comparators will be placed at the MSB Ladder tap points
between % VREF and % VREF. The oVj;lrlap of Y16 VREF on
each side of the Voltage Estimator's span will automatically
correct an error of up to 16 LSBs (16 LSBs = 312.5 mV for
VREF = 5V). If the first flash conversion determines that the
input voltage is between % VREF and 4/8 VREF - LSB/2,
the Voltage Estimator's output code will be corrected by
subtracting "1". This results in a corrected value of "01". If
the first flash conversion determines that the input voltage is
between 8/16 VREF - LSB/2 and % VREF, the Voltage
Estimator's output code remains unchanged.
After correction, th~ 2-bit data from both the Voltage Estimator and the first flash conversion are decoded to produce
the five MSBs.' Decoding is similar to that of 'a 5-bit flash
converter since there are 32 tap pOints on the MSB Ladder.
However, 31 comparators are not needed since the Voltage
Estimator places the eight comparators along the MSB Ladder where reference tap voltages are'present that fall above
and below the magnitude of VIN. Comparators are not needed outside this selected range. If a comparator's output is a
"0", all comparators above it will also have outputs of "0"
and if a comparator's output is a "1", all comparators below
it will also have outputs of "1".

2.3 WR-RD (WR then RD) Mode
The ADC08061 12 is in the WR-RD mode with the MODE
pin tied high. A conversion starts on the falling edge of the
WA' Signal. There are two options for reading the output
data which relate to interface timing. If an interrupt-driven
scheme is desired, the user can wait for the iN"i' output to go
low before reading the conversion result (see Figure 2b ).
Typically, INT will go low 520 ns, maximum, after WA's risingedge. However, if a shorter conversion time is desired,
, the processor need not waiHor INT and can exercise a read
after only 350 ns (see Rgure 28). If AD is pulled low before
lfiIT goes low, lfiIT will immediately go low and data will appear at the outputs. This is the fastest operating mode (IRO
~ !iNTL> with a conversion time, including data access time,
of 560 ns. Allowing 100 ns for reading the conversion data
and the delay between cpnversions g'ives a total throughput
time of 660 ns (throughput rate of 1.5 MHz).
, 2.4 WR-RD Mode with Reduced Interface
System Connection, "
~ and AD can be tied Jow, using only WA to control the

start of conversion for applications that require reduced digital interface while operating in the WR-RD mode (Figure 3).
Data will be valid approximately'705 ns follo~ng WA's rising edge.
2.5 Multiplexer Addressing

2.0 DIGITAL INTERFACE
The ADC08061 12 has two basic interface modes which are
selected by connecting the MODE pin to a logic high or low.

,

The ADCo8062 has 2 multiplexer inputs. These are selected
using the AO multiplexer channel selection input. Table I

2-270

r--------------------------------------------------------------------,~

§

Application Information (Continued)
shows the input code needed to select a given channel. The
multiplexer address is latched when received but the multiplexer channel is updated aiter the completion of the current conversion.

4.0 ANALOG INPUT AND SOURCE IMPEDANCE
The ADCOB061/2's analog input circuitry includes an analog switch with an "on" resistance of 70n and capacitance
of 1.4 pF and 12 pF (see Figure 6). The switch is closed
during the AID's input signal acquisition time (while WR is
low when using the WR-RD Mode). A small transient current
flows into the input pin each time the switch closes. A transient voltage, whose magnitude can increase as the source
impedance increases, may be present at the input. So long
as the source impedance is less than 500n; the input voltage transient will not cause errors and. need not be filtered.
Large source impedances can slow· the charging: of the
sampling capaCitors and degrade conversion accuracy.
Therefore, only signal sources with output impedances less
than 5000. should be used if rated accuracy is to be
achieved at the minimum sample time (100 ns maximum). A
signal source with a high output impedance should have its
output buffered with an operational amplifier. Any ringing or
voltage shifts at the op amp's output during the sampling
period can result in conversion errors.
Correct conversion results will be obtained for input voltages greater than GND - 100 mV and less than V+ +
100 mY. Do not allow the signal source to drive the analog
input pin more than 300 mV higher than V+ , or more than
300 mV lower than GND. The current flowing through any
analog input pin should be limited to 5 rnA or less to avoid
permanent damage to the IC if an anal!)g input pin is forced
beyond these voltages. The sum of all the overdrive currents into all pins must be less than 20 mA. Some sort of
protection scheme should be used when the input signal is
expected to extend more than 300 mV beyond the power
supply limits. A simple protection network using resistors
and diodes is shown in Figure 8.

TABLE.I. Multiplexer Addressing
ADC08062
AO

Channel

0
1

V,N1
V,N2

The multiplexer address data must be valid at the time of
RD·s falling edge, remain valid during the conversion, and
can go high aiter RD goes high when operating in the Read
Mode.
The multiplexer address data should be valid at or before
the time of WR's falling edge, remain valid while WR is low,
and go invalid aiter WR goes high when operating in the
WR-RD Mode.
3.0 REFERENCE INPUTS
The two VREF inputs of the ADCOB061 12 are fully differential and define the zero to full-scale input range of the A to D
converter. This allows the designer to vary the span of the
analog input since this range will be equivalent to the voltage difference between VREF+ and VREF-. Transducers
with minimum output voltages above GND can also be compensated by connecting VREF- to a voltage that is equal to
this minimum voltage. By reducing VREF (VREF = VREF+
- VREF -) to less than 5V, the sensitivity of the converter
can be increased (i.e., if VREF = 2.5V, then 1 LSB =
9.B mV). The ADCOB061/2's reference arrangement also
facilitates ratiometric operation and in many cases the
ADCOB061/2's power supply can be used for transducer
power as well as the VREF source. Ratiometric operation is
achieved by connecting VREF- to GND and connecting
VREF+ and a transducer's power supply input to V+. The
ADCOB061/2's linearity degrades when VREF+ - IVREF-I
is less than 2.0V.

6.0 INHERENT SAMPLE-AND-HOLD
An important benefit of the ADCOB061/2's input architecture is the inherent sample-and-hold (S/H) and its ability to
measure relatively high speed signals without the help of an
external S/H. In a non-sampling converter, regardless of its
speed, the input must remain stable to at least % LSB
throughout the conversion process if full accuracy is to be
maintained. Consequently, for many high speed signals, this
signal must be externally sampled and held stationary during the conversion.
The ADCOB061 and ADCOB062 are suitable for DSP-based
systems because of the direct control of the S/H through

The voltage at VREF- sets the input level that produces a
digital output of all zeros. Though Y,N is not itself differential,.
the reference design affords nearly differential-input capability
for some measurement applications. Figure 6 shows one
possible differential configuration.
It should be noted that, while the two VREF inputs are fully
differential, the digital output will be zero for any analog input voltage if VREF- :;" VREF+.

TLlH/ll08S-19
'Represe~ts

a multiplexer channel in the ADC08062.

.

FIGURE 6. ADC08061 and ADC08062 Equivalent Input Circuit Model

2-271

...~

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I
...

Application Information (Continued)
Input Not Referred to GND

Power Supply as Reference

External Reference 2.SV Full-scale
(Standard Application)

VIN(+)

VIN(+)

!
c

TUH/ll086-21
TUH/ll066-22
"Signal source driving VIN( -) mus1 be capable of
sinking 5 rnA,

Note: Eiypass capacitors consis1 of a 0.1 ,.F ceramic In parallel with a 10 ,.F bead tantalum.

FIGURE 7, Analog Input Options

r--------.,
I
5V
I

I
I

VIN1 :

Cs

I
I

150

ftc

ViR/ROY INT

MODE ' AO

:

17

DB7
DB6
DBS

~-------OPTIONAL; SEE TEXT...

ADC08062

DB4
DB3
DB2
OBI

11

DBO

I IO.
+

10J.lF

1 J.lF

, TL/H/ll086-23

Nota the multiple bypass capecltors on the reference and power supply pins. VREF- should be, bypass to analog ground using multiple capacnors H it is not
grounded (see Section 7.0 "Layout, Grounds, and Bypassing"). VINI Is shown with an optional input protection network.

FIGURE 8. Typical Connection
the \Wi signal. The WR input Signal allows the AID to be
synchronized to a DSP system's sampling rate or to other
ADC08061 and ADC08062s.
The ADC08061 can perform accurate conversions of fullscale input signals at frequencies from dc to more than
300 kHz (full power bandwidth) without the need of an external sample-and-hold (S/H).

and, therefore, should have their own separate ground lines.
Best performance is obtained using separate ground planes
for the digital and analog parts of the system.
The analog inputs should be isolated from noisy Signal
traces to avoid having spurious signals couple to the input.
Any external component (e.g., an input filter capacitor) connected across the inputs should be returned to a very clean
ground point. IncorrecUy grounding the ADC08061/2 will result in reduced conversion accuracy.
The V+ supply pin, VREF+, and VREF- (if not grounded)
should be bypassed with a parallel combination of a 0.1 J.LF
ceramic capaCitor and a 10 J.LF tantalum capaCitor placed as
close as possible to the supply pin using short circuit board
traces. See Figures 7 and 8.

7.0 LAYQUT, GROUNDS, AND BYPASSING
In order to ensure fast, accurate conversions from the
ADC08061/2, it is necessary to use appropriate circuit
board layout techniques. Ideally, the analog-to-digital converter's ground reference should be low impedance and
free of noise from other parts of the system. Digital circuits
can produce a great deal of noise on their ground returns

2-272

f}1National Semiconductor

ADC08161
500 ns AID Converter with S/H Function and
2.SV Bandgap Reference
General Description

Key Specifications

Using a patented multi-step AID conversion technique, the
8-bit ADC08161 CMOS AID converter offers 500 ns conversion time, internal sample-and-hold (S/H), a 2.5V bandgap
reference, and dissipates only 100 mW of power. The
ADC08161 performs an 8-bit conversion with a 2-bit voltage
estimator that generates the 2 MSBs and two low-resolution
(3-bit) flashes that generate the 6 LBSs.

•
•
•
•
•
•

Input signals are tracked and held by the input sampling
circuitry, eliminating the need for an external sample-andhold. The ADC08161 can perform accurate conversions of
full-scale input signals at frequencies from DC to typically
more than 300 kHz (full power bandwidth) without the need
of an external sample-and-hold (S/H).
For ease of interface to microprocessors, this part has been
designed to appear as a memory location or I/O port without the need for external interfacing logic.

Resolution
Conversion time (teoNV)
Full power bandwidth
Throughput rate
Power dissipation
Total unadjusted error

8 Bits
560 ns max (WR-RD Mode)
300 kHz (typ)
1.5 MHz min
100 mW max
± 1h LSB and ± 1 LSB max

Features
• No external clock required
• Analog input voltage range from GND to V+
• 2.5V bandgap reference

Applications
•
•
•
•

Mobile telecommunications
Hard-disk drives
Instrumentation
High-speed data acquisition systems

Block Diagram

OFL
DB7 (MSB)
VIN

-t---+--I

DB6
DBS
DB.
DB3
DB2
DBl
DBO (LSB)

v+

iNT

GND

MODE

Cs

iW ViR/ROY
TL/H/11149-l

2-273

•

Absolute Maximum Ratings (Notes 1 & 2)

Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)
NPackage
WMPackage
Lead Temperature (Note 5)
N Package (Soldering, 10 sec.)
WM Package (Vapor Phase, 60 sec.)
.. WM Package (Infrared, 15 sec.)

-65·Cto + 150"C

Storage Temperature

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V+)
6V
-0.3VtoV+ + 0.3V
Logic Control Inputs
Voltage at Other Inputs and Outputs .-0.3VtoV+ + 0.3V

ESD Susceptibility (Note 6)

750V
I

Operating Ratings (Notes 1 &2)
Temperature Range
ADC08161 BIN,
' ADC08161CIN,
ADC08161 BIWM,
ADC08161CIWM
Supply Voltage, (V+)

5mA
20mA
875mW
875mW

TMIN s; TA';; TMAX
-40·C";; TA''';; 85·C

4.5Vto 5.5V

+ 260·C
+215·C
+ 220·C

. Converter Characteristics
The following specifications apply for RD Mode, V+ = 5V, VREF+ = 5V, and VREF- = GND unless otherwise specified.
Boldface limits apply fo~ TA = T .. = TMIN to TMAl6 all other limits TA = TJ ,= 25·C.
Symbol

Parameter

Conditions
I

Typical,
(Note 7)

Limits
(Note 8)

,Units
(Limit)

INL

Integral Non Linearity

VREF = 5V
ADC08161 BIN, BIWM

±%

LSB (max)

ADC08161 CIN;CIWM

±1

LSB (max)

TUE

Total Unadjusted Error (Note 9)

VREF = 5V
ADC08161 BIN, BIWM

±%

LSB(max)

ADC08161CIN, CIWM,

±1

LSB(max)

INL

Integral Non Linearity

VREF = 2.5V, All Suffixes

±1

LSB (max)

TUE

Total Unadjusted Error

VREF = 2.5V
ADC08161, All Suffixes

±1

LSB(max)

Missing.Codes

VREF = 5V
VREF = 2.5V

0
0
500
1250

Bits (max)
Bits (max)

YREFY+

V (min)
V (max)

GND
YREF+

V (min)
V (max)

GND - 0.1
Y+ + 0.1

V (min)
V (max)

-20

p.A(max)

-20

p.A (max)

Reference Input Resistance
VREF+

Positive Reference Input Voltage

VREF-

Negative Reference
Input Voltage

VIN

700
700

Analog
Input Voltage

(Note 10)

On-Channel Input Current

On Channel.lnput = 5V,
Off Channel Input = OV
(Note 11)
On Channel Input = OV,
Off Channel Input = 5V
(Note 11)

2-274

-0.4

..
-0.4

n(min)
n(max)

,.

Converter Characteristics

"
(Continued)
The following specifications apply for RD Mode, V+ = 5V, VREF+ = 5V, and VREF- = GND unless otherwise specified.
Boldface limits apply for TA = T" = TMIN to TMAl(j all other limits TA = TJ = 25°C.

Symbol
PSS

Parameter

Conditions
V+ = 5V ±5%,
VREF = 4.75V
All Codes Tested

Power Supply Sensitivity

Typical
(Note 7)

Limits
(Note 8)

Units
(Limit)

±1j,6

±y"

LSB (max)

Effective Bits

VIN = 4.85 Vp_p
fiN = 20 Hz to 20 kHz

7.8

Bits

Full-Power Bandwidth

VIN = 4.85 Vp _p

300

kHz

THD

Total Harmonic Distortion

VIN = 4.85 Vp_p
fiN = 20 Hz to 20 kHz

0:5

%

SIN

Signal-to-Noise Ratio

VIN = 4.85 Vp_p
fiN = 20 Hz to 20 kHz

50

dB

IMD

Intermodulation Distortion

VIN =' 4.85 Vp_p
fiN = 20 Hz to 20 kHz

50

dB

CVIN

Analog Input Capacitance

25

,pF

AC Electrical Characteristics
The following specifications apply for V+ = 5V, tr = t, = 10 ns, VREF+ = 5V, VREF- = OV unless otherwise specified.
Boldface limits apply for T A = TJ = TMIN to T MAX; all other limits T A = TJ = 25°C.

Symbol

Parameter

Conditions

ADC08161BIN, ADC08161CIN,
ADC08161BIWM, ADC08161CIWM
TypiCal
(Note 7)

Limit
(Note 8)

100

twA

Write Time

Mode Pin to V+
(Figures 2a, 2b, and 3)

100

lRiJ

Read Time (Time from Rising Edge
of WR to Falling Edge of RD)

Mode Pin to V+,
CMJ Suffix (Agure 2a)

350

tROW

RDWidth

Mode Pin to GND (Figure 4)

tcONV

WR-RD Mode Conversion Time
(tWR + tRD + tACC1)

Mode Pin to V+,
CMJ Suffix (Figure 2a)

500

tCRD

RD Mode Conversion Time

Mode Pin to GND,
CMJ Suffix (Figure 1)

655

tACCO

Access Time (Delay from Falling
Edge of RD to Output Valid)

CL!> 100 pF, Mode Pinto GND
CMJ Suffix (Figure 1)

640

tACC1

Access Time (Delay from
Falling Edge of RD
to Output Valid)

CL!> 10pF
CL = 100pF
Mode Pin to V +, tRD !> tlNTL
CMJ Suffix (Figure 2a)

45
50

Access Time (Delay from
Falling Edge of RD
to Output Valid)

CL!> 10 pF
CL = 100pF
tRD> tlNTL,
CMJ Suffix, (Figures 2b and 4)

25
30

TRI-STATE® Control
(Delay from Rising Edge
of RD to HI-Z State)

RL = 3 kO, CL = 10 pF
(Figures 1, 2a, 2b, 3, and 4)

Delay from Rising Edge of
WR to Falling Edge of INT

Mode Pin = V+, CL = 50 pF
(Figures 2b, and 3)

tACC2

t1H, tOH

l;N'i'L

2-275

200
400

350
515
250
400
560
790
900
940
900
940

Units
(Limit)

ns(miri)
ns(min)
ns(min)
ns(max)
ns(max)
ns(max)
ns(max)

110

ns
ns(max)

175

ns(max)

55

ns
ns(max)

60

ns(mai<)

30

60

ns(max)

520

690

ns(max)

•

..CD
..-

I

AC Electrical Characteristics

(Continued)
The following specifications apply for V+ = SV, tr = tf = 10 ns, VREF+ = SV, VREF- = OV unless otherwise specified.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 2SoC.

Symbol

tJm'H
lJm'H
tROY

tiD

Parameter

Delay from Rising Edge of

AD to Rising Edge of INT
Delay from Rising Edge of

WR to Rising Edge of INT
Delay from CS to ROY

Delay from iN'i'
to Output Valid

ADC08161BIN, ADC08161CIN,
ADC08161BIWM, ADC08161CIWM

Conditions

Units
(Umlt)

Typical
(Note 7)

Limit
(Note 8)

CL = SO pF,
CMJ Suffix (Figures 1, 2a, 2b, and 4)

SO

95
100

ns(max)

CL = SOpF,
CMJ Suffix (Figure 3)

4S

95
100

ns(max)

Mode Pin = OV, CL = SO pF,
RL = 3 kO,
CMJ Suffix (Figure 1)

2S

45
ns(max)

50

RL=3kO,CL= 100pF

0

15

ns (max)

60

115
175

ns(max)

SO

50

ns(min)

(Figure 3)

tRI

Delay from RD to INT

Mode Pin = V+, tRD s; tlNTL
CMJ Suffix (Figure 2a)

tN

TIme between End of AD
and Start of New Conversion

(Figures 1, 2a, 2b, 3 and 4)

tess

CSSetupTIme

(Figures 1, 2a, 2b, 3 and 4)

0

0

ns(max)

CS Hold Time .

(Figures 1, 2a, 2b, 3 and 4)

0

0

ns(max)

tesH

DC Electrical Characteristics
The following specifications apply for V+ = SV unless otherwise specified. Boldface limits appl)f for TA = T.. = TMIN to
TMAld all other limits TA = TJ = 2SoC.

Symbol

Parameter

Conditions

ADC08161BIN, ADC08161CIN,
ADC08161BIWM, ADC08161CIWM
Typical
(Note 7)

VIH

VIL

Logic "1" Input Voltage .

Logic "0" Input Voltage

V+ = S.SV
es, WR, RO, AO, A 1, A2 Pins
Mode Pin

V (min)

0.8
1.5

V (max)

O.OOS
0.1
SO

1
·3
200

p.A(max)

-0.005

-2

p.A(max)

2.4

V (min)

4.5

V (min)

V+ = 4.SV
Mode Pin

IlL

Logic "1" Input Current

Logic "0" Input Current

Units
(Limit)

2.0
3.5

CS, WR, RD, AO, A 1, A2 Pins
IIH

Limit
(Note 8)

VH = SV
CS, RD, AO, A 1, A2 Pins
WRPin
Mode Pin
VL = OV

CS, RO, WR, AO, A1, A2
Mode Pins
VOH

Logic "1" Output Voltage

V+ = 4.7SV
lOUT = - 360 p.A
080-087,
iN'i'
lOUT = -10 p.A
080-087, OFI, iN'i'

m,

2-276

DC Electrical Characteristics

(Continued)
The following specifications apply for V+ = SV unless otherwise specified. Boldface limits applv for T A = T .. = TMIN to
TMm all other limits TA = TJ = 2S'C.

Symbol

Parameter

Conditions

ADC08161BIN, ADC08161CIN,
ADCOB161BIWM, ADC08161CIWM,
Typical
(Note 7)

VOL

10

Logic "0" Output Voltage

TRI-STATE Output Current

V+ = 4.7SV
lOUT = 1.6 mA
DBO-DB7, OFL, INT, ROY
VOUT = S.OV
DBO-DB7, ROY
VOUT = OV
DBO-DB7, ROY

ISOURCE

Output Source Current

VOUT = OV
DBO-DB7, OFL, INT

ISINK

Output Sink Current

VOUT = SV
DBO-DB7, OFL, INT, ROY
CS = WR = RD= 0

Limit
(Note 8)

Units
(Limit)

0.4

V (max)

0.1

3

p.A(max)

-0.1

-3

p.A(max)

-26

-8

mA(min)

24

7

mA(min)

11.5

20

mA(max)

Ic

Supply Current

COUT

Logic Output Capacitance

S

pF

CIN

Logic Input Capacitance

S

pF

•

2-277

Bandgap Reference Electrical Characteristics
The following specifications apply for V+
other limits TA = TJ = 25°C.
IiIYm~ol

= 5V unless otherwise specified. Boldface limits apply for TIlIH to TIIAXI all

Parameter

Conditions

VREFOUT

Internal Reference Output Voltage

AVREF/AT

Internal Reference Temperature
COeffiCient

AVREF/AIL

Internal Reference Load
Regulation

Sourcing (0

Line Regulation

4.75V

S;

Ise

Short Circuit Current

VREV

= OV

AVREF/At

Long Term Stability

.,;

Start-Up Time

Typical
(Note 7)

LImits
(Note 8)

Units
(Limit)

2.5

2.5 ± 1.5%
2.5 ± 2.0%

. V (max)

"B"Grade
"C"Grade

40

V+

S;

+ 10 mAl

IL S;

S;

0.01

0.1

0.5

8.0

5.25V

..
V+:OV- 5V. CL

ppml"C

,.

= 220p.F

. O/O/mA (max)
mV(max)

35

mA(max)

200

ppm/kHr

40

ms

Note t: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
:the device beyond Its specified operating ratings. Operating Ratings indicate conditions for which the device Is functional. but do not guarantee performance limits.
For guaranteed speCifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions .listed. Some
perfor?'Bnce characteristics may degrade when the device is not operated under the listed test condnions.
:
Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply voltage (VIN < GND or VIN > V+), the absolute value the curre~t at that pin should be
limned to S mA or less. The 20 mA package input current specification limits the number of pins that can exceed the power supply boundaries with a 5 rnA currant
limit to four.

oi

Note 4: The power dissipation of this device under normai operation should never exceed 87S mW (Quiescent Power Dissipation + TTL Loads on the dignai
outputs). Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (e.g., when any input or
output exceeds the power supply). The maximum power diSSipation must be derated at elevated temperatures and is dictated by TJMAX (maximum lunction
temperature), 8JA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature
Is PDmax = (TJMAX - TIJI8JA or the number given in the Absolute Maximum Ratings, whichever Is lower. The table below details TJMAXand 8JA for the various
psckages and versions of the ADC08161.
Part Number

TJMAX

8JA

ADC08161 B/CIN
ADC08161B/CIWM

lOS
lOS

SI
8S

Note 5: See AN4S0 "Surface Mounting Methods and Their Effect on Product Reliability" for other methods of soldering surface mount devices.
Note 6: Human body model, 100 pF discharged through a I.S kfi resistor.
Note 7: Typicals are at 2S'C and represent most likely parametric norm.
Note 8: limits are guaranteed to National's AOQl (Average Output Quality level).
Note 9: Totai unadjusted error includes offset, full-scale, and linearity errors.
Note 10: Two on-Chip diodes are tied to each analog Input and are reversed biased during normal operation. One is connected to V+ and the other is connected to
GND. They will become forward biased and conduct when an analog input voltage is equal to or greater than one diode drop above V+ or below GND. Therefore,
caution should be exercised when testing with V + = 4.SV. Analog inputs with magnitudes equai to SV can cause an input diode to conduct, especially at elevated
temperatures. This can create conversion errors for analog signals near full-scale. The specification allows SO mV forward bias on either diode; e.g., the output
code will be correct as long as the anaiog Input signal does not exceed the supply voltage by more than SO mY. Exceeding this range on an unselected channel will
corrupt the reading of a selected channel. An absolute anaiog input slgnai voltage range of OV ,,; VIN ,,; SV can be achieved by ensuring that the minimum supply
voltage applied to V+ is 4.9S0V over temperature variations, inltiai tolerance, and loading.
Note 11: Off-channel leakage current is measured on the on-channel selection.

2-278

TRI-STATE Test Circuit and Waveforms
V+

V+
DATA

GND

t-~-~....-.o OUTPUT

'H

3k!l

VOH

DATA OUTPUTS

~
90%

GND
TUH/11149-2

TLlH/11149-4

tr= 10n5

tOH
V+

V+

3k!l
DATA

b~~--o OUTPUT

v+
DATA OUTPUTS
V
OL
TUH/11149-3

--=:t:H

10%

,,=

TLlH/11149-5

10ns

ROY

-------------<

DBO-DB7 - - - - - - -

DATA 8

•

)-TLlH/11149-6

FIGURE 1. RD Mode (Mode Pin is Low)

2~279

TRI-STATE Test Circuit and Waveforms (Continued)

TL/H/11149-7

FIGURE 2a. WR-RD Mode with tRD

s: tlNTL (Mode PI" Is High)

FIGURE 2b. WR-RD Mode with tRD

> tlNTL (Mode PI" Is High)

Tl/H/11149-B

2-280

TRI-STATE Test Circuit and Waveforms (Continued)

DBO-DB7

TL/H/11149-9

FIGURE 3. WR-RD Mode Reduced Interface System Connection with CS

= RD = 0 (Mode Pin is High)

DATA B } _______________

DBO-DB7

<

D~TA

TL/H/11149-10

FIGURE 4. RD Mode (Pipeline Operation); tRDW must be between 200 ns and 400 ns.
(Mode Pin is Low)

2-281

PI

Typical Performance Characteristics .
800

D.6

I

750
... 700

!II
1=

Vb v./
V
600-:p~

650

V

~

I
.r;

~..,

1'-

0"

'"

0..3

... ~ D.2
~
0.1

0

SO

100

0

150

AMBIENT TEMPERATURE (OC)

1

3

2

•

~
~

0

Y+=5Y

\

D.4

·0
-50

o.s

Y+=5Y
T"c25OC

o.s

2

/

Y =S.OY

550
-100

Offset Error vs
Reference Voltage

Linearity Error vs
Reference Vf)ltage

leRD vs Temperature

.5

'.

T,,=250(:

"'- f"""--..

D.3

~

ffi

~

D.2

0

0.1
0
0

5

REFERENCE VOLTAGE (V)

1

2

•

3

5

REFERENCE VOLTAGE(V)

"

Reference Output Voltage vs
Temperature

Supply Current vs Temperature
16

'4'

.s

~

!3

i

2.515

•

v~~ .
,. -Y+.s..

e
6
-100

YRErOUTPI"~

--

2.500

V

2.495

1.4

"'

/

2.505

~r-::::-

10

1.5

V"'=S:.1

·2.510

12_;~i'-.

Logic Threshold vs
Temperature

J

1.3

.!i!

1.2

!:l

/

U90

,

1/.

2M5
-50

0

50

100

150

-100

-50

TEUPERATURE(OC)

0

50

100

- --

Y+is,s•

E

::;E_
l-

1.1
1.0
-100

150

TEMPERATURE (OC)

Y+=5.0V

~

-so

0

so

100

150

TEMPERATURE (OC)

Output Current vs Temperature
.0
30

!

20

~

10

~

-10

!3
S

-20

-100

, .-

.;;;-- r--

0

-so
-.a

,

Y+1I5V .

~
'sOURCE

-so

0

-

so

TEMPERATURE (OC)

2-282

100

150

TL/H/"'49-"

»
c

Connection Diagram

oo
.....
en
.....
CI)

Dual-In-Llne and Wide-Body
Smail-Outline Packages

,

'"

VIN -

1

\...../

20 I-V+

080- 2

19 I- VREFOUT

I- OFL

081- 3

18

082- 4

171-087

083- 5

AOC08161

WR/ROY- 6

,

161-086
151-085

MOOE- 7

141-084

Rii-a

131-Cs

00-9

121- VREF+,
11 I-V REF _ '

GNO- 10

TL/H/11149-14

See NS Package Number N20A or M20A

W'R/RDY

Ordering Information
Industrial ( - 40"C

s: TA s: 8S"C)

ADC08161BIN, ADC08161CIN
ADC08161BIWM, ADC08161CIWM

DBO-DB7

WR-RD Mode (Logic high applied to MODE
pin)
WR: With CS low, the conversion is started on
the rising edge of WR. The digital result will be
strobed into the output latch at the end of conversion (see Figures 2a, 2b, and 3).

Package

N20A
M20B

RD Mode (Logic low applied to MODE pin)

Pin Description
VIN

..

RDY: This is an open drain output (no internal
pull-up device). RDY will go low after the falling
edge of CS and returns high at the end of conversion.

This is the analog input. The input range is
GND-50 mV s: VINPUT s: V+ + 50 mY.
TRI-STATE data outputs-bit 0 (LSB) through
bit 7 (MSB).

MODE

Mode: Mode (RD or WR-RD) selection inputThis pin is pulled to a logic low through an internal 50 p.A current sink when left unconnected.
RD Mode is selected if the MODE pin is left
unconnected or externally forced low. A complete conversion is accomplished by pulling RD
low until output data appears.
WR-RD Mode is selected when a high is applied to the MODE pin. A conversion starts with
the WR signal's rising edge and then using RD
to access the data.

RD

WR-RD Mode (logic high on the MODE pin)

This is the active low Read input. With a logic
low applied to the CS pin, the TRI-STATE data
outputs (DBO-DB7) will be activated when RD
goes low (see Figures 2a, 2b and 3).
RD Mode (logiC low on the MODE pin)

2-283

fI

-

-~

CD

r---------------------------------~------------~--~----------------~--~--~

Pin Description (Continued)

 (Note 3)
6.5V

Temperature Range

, TMIN S:TAS:TMAX
-40·CS:TAS: +S5·C

ADC1001CCJ
ADC1001CCJ-1

O·CS:TAS: + 70·C

RangeofVcc

4.5 VOC to 6.3 VOC

"

Logic Control Inputs
-0.3Vto +1SV '
Voltage at Other Inputs and Outputs -0.3Vto (Vcc+0.3V)
-65·C to + 150·C
Storage Temperature Range
Package Dissipation at T A = 25·C

S75mW
300·C

Lead Temp. (Soldering, 10 seconds)
ESD Susceptibility (Note 1P)

(Notes 1 &2)

"

SOOV

Converter Characteristics
Converter Specifications: VCC= 5 Voc, VREF/2 = 2.500 VOC, TMINS:TA'S:TMAX and fCLK= 410 kHz unless oiherwise specified.
Parameter

Conditions

Typ

Min

Unearity Error
Zero Error
Full-Scale Error
Total Ladder Resistance (Note 9)

Input Resistance at Pin 9

Analog Input Voltage Range

(Note 4) V(+) orV(-)

DC Common-Mode Error

Over Analog Input Voltage Range

Power Supply Sensitivity

Vcc=5 Voc±5% Over
Allowed VIN( +) and VIN( -)
Voltage Range (Note 4)

2.2

,

,

Max

Units

±1
±2
±2

LSB
LSB
LSB

Kn

4.S

GND-0.05

Vcc+0:05 .

±Va
±Va

VOC
LSB
LSB

.',

AC Electrical Characteristics
Timing Specifications: Vcc=5 VOC and TA=25·C unless otherwise specified.
Max

Units

Tc

Symbol

Conversion Time

Parameter

(Note 5)
fCLK=410 kHz

Conditions

SO
195

90
220

1/fCLK

fCLK

Clock Frequency

(NoteS)

100

1260

kHz

Clock Duty Cycle

Min

Typ

40

,,"S

60

%

4600

conv/s

CR

Conversion Rate In Free-Running
Mode

INTR tied to WR with
CS=O VOC, fCLK=410 kHz

tW(WR)L

Width of WR Input (Start Pulse
Width)

CS=O VOC (Note 6)

tACC

Access Time (Delay from
Falling Edge of RD to Output
Data Valid)

CL =100 pF

170

300

ns

t1H, tOH

TRI-STATE® Control (Delay
from Rising Edge of RD to
Hi-Z State)

CL = 10 pF, RL =10k
(See TRI-STATE Test
Circuits)

125

200

ns

tWI,tRI

Delay from Falling Edge
of WR or RD to Reset of INTR

300

450

ns

t1rs

INTR to 1st Read Set-Up Time

CIN

Input Capacitance of Logic
Control Inputs

5

7.5

pF

COUT

TRI-STATE Output
Capacitance (Data Buffers)

5

7.5

pF

150

,
550

2-290

ns

400

ns

l>

c

DC Electrical Characteristics

....o

The following specifications apply for Vcc=5 ¥DC and TMIN,;;TA';; TMAX, unless otherwise specified.

....

Symbol

Parameter

Conditions

Min

Typ

Q
Q

Max

Units

15

VDC

0.8

VDC

1

fLADC

CONTROL INPUTS [Note: ClK IN is the input of a Schmitt trigger circuit and is therefore specified separately]
VIN (1)

logical "1" Input Voltage

Vcc=5.25VDC

2.0

(Except ClK IN)
VIN(O)

logical "0" Input Voltage

Vcc=4.75 VDC

(Except ClK IN)
liN (1)

logical "1" Input Current

0.005

VIN=5 VDC

(All Inputs)
liN (0)

logical "0" input Current

VIN=OVDC

-1

-0.005

2.7

3.1

3.5

VDC

1.5

1.8

2.1

VDC

0.6

1.3

2.0

VDC

0.4

VDC

fLADC

(All Inputs)
CLOCK IN
Vr+

ClK IN Positive GOing
Threshold Voltage

Vr-

ClK IN Negative Going
Threshold Voltage

VH

ClK IN Hysteresis
(Vr+)-(Vr)

OUTPUTS AND INTR
Vour(O)

logical "0" Output Voltage

lour = 1.6 mA, Vcc=4.75 VDC

Vour(1)

logical "1" Output Voltage

10= -360 fLA, Vcc=4.75 VDC

2.4

10= -10 fLA, Vcc=4.75 VDC

4.5

lour

TRI-STATE Disabled Output
leakage (All Data Buffers)

VOUT=0.4 VDC
Vour=5VDC

VDC
VDC
0.1

-100

fLADC

0.1

3

/LADC

ISOURCE

VOUT Short to GND, T A = 25°C

4.5

6

mADC

ISINK

VOUT Short to VCC, TA = 25°C

9.0

16

mADC

POWER SUPPLY
Icc

Supply Current (Includes

fCLK=410 kHz,

ladder Current)

VREF/2=NC, TA=25°C
andCS=1

2.5

5.0

mA

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do' not apply when operating
the device beyond its specified ope~ating conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified. The separate A GND point should always be wired to the D GND.
Note 3: A zener diode exists, internally, from Vcc to GND and has a typical breakdown voltage of 7 Vec.
Note 4: For VIN(-):' VIN(+) the digital output code will be all zeros. Two on·chip diodes are tied to each analog input (see Block Diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low Vcc levels (4.SV),
as high level analog'inputs (SV) can cause this input diode to conduct-especially at elevated temperatures, and cause errors for analog inputs near fullscale. rhe
spec allows SO mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than SO mV, the output
code will be correct. To achieve an absolute 0 Voc to 5 Voe input voltage range will therefore require a minimum supply voltage of 4.950 Voe over temperature
variations, initial tolerance and loading.
Note 5: WHh an asynchronous start pulse, UP. to 8 clock periods may be required before the internal clock phases arB proper to start the conversion process. The
start request is internally latched, see Figure 1.
Note 6: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold
the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see riming Diagrams).

Note 7: All typical values are for TA = 2S·C.
Note 8: Accuracy is guaranteed at fCLK=410 kHz. At higher clock frequencies accuracy can degrade.
Note 9: The VREFJ2 pin is the center point of a two resistor divider (each resistor is 2.4kn) connected from Vee to ground. Total ladder input resistance is the sum
of these two equal resistors.

Note 10: Human body model, 100 pF discharged through a 1.S kn resistor.

2-291

~

8.....

~

r------------------------------------------------------------------------------------------,
Typical Performance Characteristics

~

logic Input Threshold
Voltage vs Supply Voltage

Delay From Failing Edge of
RD to Output Data Valid
vs Load Capacitance

f-f-'-5~'cldA~+lz5lc ~

5oo'~mm

1.8

~ u

">

~

1.6

H-+++-H7"f~+++-1H

1.5

H-+",-7o''l-H-++++-1H

~

~

f
;!
u

ii
~

~

1.4

CLK IN SchmHt Trip Levels
va Supply Voltage

~..
~

4oo~

S30o~

SliD
zoo

I"'-f-+++-H-+-+--I-+--IH

1.3 L....I.....L...J......L...J.....I.....L...............1....JL...J
4.50
4.7&
5.00
&.25
5.50

~
9

zoo

400

600

800

3.1
2.7

1-47.~Ir+-t~~~-++~

V + ..... 1-"
1-....++-1r+--+,±,I-:-:!--!c:-±±~
-55·C:S;T,AS+125·C

"~

2.3

H-+++-H-++++-H

~
;!

1.9

VTH-+++-H==-,;,jOi'1""FH

II:

..... 1-"-"'"

1.5 L-I.....L...J......L...J.....I.....L....................L-I
5.2&
5.&0
4.&0
4.7&
uo

100

o

I

3.5

1000

LOAO CAPACITANCE (pF)

VCC -SUPPLY VOLTAGE (VDC)

VCC -SUPPLY VDLTAGE (VDC) ,

Output Current vs
Temperature
8 r-T""':'T"'"T"""''''''''''''''V''''CIC-'='-5'''V''''O-C'''''
DATA OUTPUT f1-+*t-+-t-1I- BUFFERS
I

-ISINK "',,~"""I-l-..J
2 t:tj~~~_V....:O:.:Uc.:.T_=O_A_V...::;D;:.C.1-I""=
-50 -25 0 25 50 75 100 12&
TA - AMBIENTTEMPERATURE ('C)
TL/H/5675-2

TRI-STATE Test Circuits and Waveforms
t'H

fill

!Iii

DATA
OUTPUT

fS

J '*

':'

DATA VOH
OUTPUTS
GND
TLlH/5675-3

1ili

DATA
OUTPUT

':'

CL = 10 pF

VCC

--~911%

VCC
DATA
OUTPUTS

CL--

':'

tOH.

T

-',b

GND ___

10k

e1

911%

TL/H/5675-4

VCC

Jilj

""
511%
111%

1,=20 n.

tOH
VCC

vcc
GND

10k ~

CL...L

-==

r~
CL = 10 pF

t'H.

vcc

VOL

~

-10"

1,=20n.

TLlH/5675-5

2-292

50"
111%

TLlH/5675-6

l>
C

...
...oo

Timing Diagrams

o

START
CONVERSI: _ _ _ _"""""\\.._ _ _ _

/

fI_---..J·

~

~f-~
twl-

-

I-twliVft}l

-

"BUSY"

ACTUAL INTERNAL
STATUS OF THE
CONVERTER

OATA IS VALID IN
OUTPUT LATCHES

"NOT BUSY"

I - - - I TO • x '''ClK

INTERNAL T C -

(LAST DATA WAS READ)

1\

---------(LAST DATA WAS NOT REAO)

-

INT ASSERTED

1-1I2TCLK
TL/H/5675-7

Output Enable and Reset INTR
INTR RESET

•

2NO RD \,,_ _ _.../

-

TRI.SfATE'"
~- - - -

-

-

-<__
_

l_S_..J}- _ _
BYTE
•

TLlH/567S-B
Nole: All timing is measured from the 50% voltage points.

BYTE SEQUENCING FOR THE 2G-PIN ADC1001
Byte
8-Blt Data Bus Connection
Order DB7 DB6 DBS DB4
DB3 DB2 DB1 DBO
1st

MSB
Bit9 BitS Bit7 BitS Bit 5 Bit 4 Bit 3 Bit 2

2nd

LSB
Bit 1 Bit 0

0

0

2-293

0

0

0

0

....
....
o
g
c

c:c:

Functional Description
The ADC1001 uses an advanced potentiometric resistive
ladder network. The analog inputs, as well as the taps of
this ladder network, are switched into a weighted capacitor
array. The output of this capaCitor array is the input to a
sampled data comparator. This comparator allows the successive approxima~ion logic to match the analog difference
input voltage [VIN( + ) - VIN( -)1 to taps on the A network.
The most significant bit is tested first and aller 10 comparisons (80 clock cycles) a digital 10-bit binary code (all
"1"s=full-scale) is transferred to an output latch and then
an interrupt is asserted (INTA makes a high-to-Iow transition). The device may be operated in the free-running
mode by connecting INTA to the WA inut with CS=O. To
ensure start-up under all possible conditions, an external
WA pulse is required during the first power-up cycle. A conversion in .process can be interrupted by issuing a second
start command.
.

clocked in, which allows the conversion process to continue. If the set Signal were to still be present, this reset pulse
would have no effect and the 10-bit shill register would continue to be held in the reset mode. This logic therefore allows for wide CS and WA Signals and the converter will start
aller at least one of these signals returns high and the inter. nal clocks again provide a reset signal for the. start F/F.
Aller the "1" is clocked through the 1O-bit shill register
(which completes the SAA search) it causes the new digital
word to transfer to" the TAl-STATE output latches. When
this XFEA sigl)a! makes a high-to-Iow transition the one
shot fires, selting the INTA F/F. An inverting buffer then
supplies the INTR output signal.
Note that this SET control of the INTA F/F remains low for
aproximately 400 ns. If the data output is continuously enabled (CS and AD both held low), the INTA output will still
signal the end of the conversion (by a High-to-low transition), because the SET input can control the Q output of
the INTA F/F even though the AESET input is constantly at
a "1" level. This INTA output will therefore stay low for the
duration of the SET Signal.

On the high-to-Iow transition. of the WA input the internal
SAA latches and ""the shill register stages are reset. As long
as the CS input 'and WA input remain low, the AID will remain in a reset state. Conversion will start from 1to 8 clock
periods after at least one of these inputs makes a low-tohigh transition.
A functional diagram of the AID converter is shown in Figure 1. All of the inputs and outputs are shown and the major
logic control paths are drawn in heavier weight lines.
The conversion is initialized by taking CS and WA simultaneously low. This sets the start flip-flop (F IF) and the resulting "1" level resets the a-bit shill register, resets the Interrupt (INTA) F/F and inputs a "1"to the D flop, F/F1, which
is at the input end of the 1O-bit shill register. Internal clock
signals then transfer this "1" to the Q output of F/FI. The
AND gate, Gl, combines this "1" output with a clock signal
to provide a reset signal to the start F/F. If the set Signal is
no longer present (either WA or CS is a "1 ") the start FIF is
reset and the 10-bit shill register then can have the "1"

When data is to be read, the combination of both CS and
AD being low will cause the INTA F/F to be reset and the
TAl-STATE output latches will be enabled.
Zero and Full-Scale Adjustment
Zero error can be adjusted as shown in Figure 2. VIN( +) is
forced to + 2.5 mV (+ % LSB) and the potentiometer is
adjusted until the digital output code changes from 00 0000
0000 to 00 0000 0001.
. Full-scale is adjusted as shown in Figure 3, with the VREF/2
'. input. With VIN (+) forced to the desired full-scale voltage
less 1% LSBs (VFS-l% LSBs), VREF/2 is adjusted until
the digital output code changes from 11 1111 111 0 to 11
11111111.

(Vecl 5V
5V
~

VJN -

VIHI+)
AOC1001

lk

ADC1001

VIIS'/2

1.0M
..
10k ~-~Ww-....--I VJHI.,.)
10k

100

,.
• ~LM33&

...

C

-5V
TLlH/5675-9

TL/H/5675-1D

NOTE: VIN( -) should be biased so
that VIN( -);" - O.O~V when potentiometer
wiper Is set at most negative
voltage posRlon.

FIGURE 3. Full-Scale Adjust

FIGURE 2. Zero Adjust Circuit.

2-294

r--------------------------------------------------------------------.~

C

Typical Application

o
....
....

«:)
«:)

5V

CI

Vee

JiJj

CLK R

Wi\
11
12

13
14
IS
16
17
18

20
19
TRANSDUCER

10k

ClK IN

IIIYll

10·BIT RESOlUTID~
OVER ANY DESIRED
ANALOG INPUT
VOLTAGE RANGE

DB7
DB6

ADC1DDl

VINI+)

DBS
DB4

DIFF INPUTS
VINI-)

DB3
OB2
OBI
DBO

TLlH/5675-1

Block Diagram
RESET
INPUT PROTECTION
FOR ALL LOGIC INPUTS

F
INPUT

CLKB
TO INTERNAL
CIRCUITS

BV",30V

CLK B

VCC IVREF)o----t

LADDER
AND
OECODER

START CONVERSION
IF RESET' "0"

VREF/2o---~~--....,*-.,

INTR FIF
OAC
VeOUT)
AGNO
'::"

VCC

VINe+) o-"-I-+(l:J-~

AOC100l 20.pIN

~J
-I
1-400",

BINOTElIc:::::::::::::~==:>
............................_;,;;~;::;,~-L....................................-;~rI
iiii C
TRI.STATE CONTROL
RESET
",". OUTPUT ENABLE
Note 1: CS shown twice for clarity.

Note 2: SAR= Successive Approximation Register.

TL/H/5675-13

FIGURE 1

2-295

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

o

;

tflNational Semiconductor

ADC1005 10.. Bit J-tP Compatible AID Converter
General Description
The ADC1005 is a CMOS 10-bit successive approximation
AID converter. 'The 20-pin ADC1 005 outputs 1O-bit data in a
two-byte format for interface with 8-bit microprocessors.
The ADC1005 has differential inputs to permit rejection of
common-mode signals, allow the analog input range to be
offset, and also to permit the conversion of signals not referred to ground. In addition, the reference voltage can be
adjusted, allowing smaller voltage spans to be measured
with 10-bit resolution.

• Operates ratio metrically or with 5 Voc voltage reference or analog span adjusted voltage reference
• OV to 5V analog input voltage range with single
5V supply
• On-chip clock generator
• TLL/MOS input/output compatible
• 0.3" standard width 20-pin DIP
• Available in 20-pin molded chip carrier
package

Features

Key Specifications

• Easy interface to all microprocessors
• Differential analog voltage inputs

• Resolution
• Linearity Error
• Conversion Time

10 bits
±% LSB and ±1 LSB
50,..s

Connection Diagrams
ADCt005 Molded Chip Carrier Package

ADCt005 (for an a-bit data bus)

S~~~~

Dual-In-Line Package

cs

I:::

t::

I::::

t::

I:::

'i' 'i' 'i' 'i' 'i'

1

20

Veo

2

19

CLKR

3

18

BIT2 0

CLKIN- 4

17

BIT3 0

Cs-l

11~(MSB)BIT9/BITI

iNfR- 5

16

BIU 0

iiii-

10~OGND

V'N(+)- 6

15

BIT5 0

ViR -

V'N(_)

7

14

BIT6 0

AGND

8

13

BIT7 0

VREF

9

12

DGND

10

11

Rii
ViR

18 17 16 15 14
13~BIT7/0

CLKR-19
VCC -

12~BIT8/BITO(LSB)

20

2

9 ~ VREF

3

'\...4

5

6

7

8

~I~~~~
d->~.ff:<

BIT8 BITO(LSB)
(MSB) BIT 9 BIT 1

Top View

lSTBYTE 2NDBYTE
TLIH15261-1

Top View
See Ordering Information

2-296

TLIH15261-19

~

Operating Ratings

Absolute Maximum Ratings

(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
6.5V
Logic Control Inputs
-0.3V to + 15V
Voltage at Other Inputs and Outputs
Input Current Per Pin

(Notes 1 & 2)

Supply Voltage (Vee)

4.5Vt06.0V

Temperature Range
ADC1 005BCJ, ADC1005CCJ

TMN:S:TA:S:TMAX
-40'C:S:TA:S: + 85°C

ADC1 005BCJ-1, ADC1005CCJ-1,
ADC1005CCV

O'C:S:TA:S:70'C

-0.3VtoVee +0.3V
±5mA

Input Current Per Package

±20mA

Storage Temperature Range
Package Dissipation at T A= 25°C
Lead Temperature
(Soldering, 10 seconds)
Dual-In-Line Package (Ceramic)
Surface Mount Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
ESD Susceptibility (Note 8)

- 65'C to + 150"C
875mW

300'C
215°C
220'C
800V

Electrical Char9cteristics The following specifications apply for Vee =

5V, VREF = 5V, feLK = 1.8 MHz
unless otherwise specified. Boldface limits apply from T MIN to TMAX; All other limits:rA = Tj = 25°C.
ADC1005BCJ
ADC1005CCJ
Parameter

Conditions

Typ
(Note 5)

Tested
Limit
(Note 6)

ADC1005BCJ-1, ADC1005CCJ-1
ADC1005CCV
Design
Typ
Limit
(Note 5)
(Note 7)

Tested
Limit
(Note 6)

Design
Limit
(Note 7)

±0.5

±O.&

±1

±1

±0.5

±O.&

Limit
Units

Converter Characteristics
Linearity Error (Note 3)
ADC1005BCJ
ADC1005BCJ-1
ADC1005CCJ
ADC1005CCJ-1, CCV

±O.&
±1

Zero Error
ADC1005BCJ
ADC1005BCJ-1
ADC1005CCJ
ADC1005CCJ-1, CCV

±O.&
±1
, ±1

Fullscale Error
ADC1005BCJ
ADC1005BCJ-1
ADC1005CCJ
ADC1 005CCJ-1, CCV

±1

±O.&
±0.5

±O.&

±1

Reference
Input
Resistance

MIN
MAX

Common-Mode
Input (Note 4)

MIN
MAX

2.2

4.8
4.8

8.3

4.8
4.8

Vee + 0.0&
GND-O.O&

VIN(+) orVIN(-)

±1

±1

2.4
7.6

2.2
8.3

Vee + 0.05 Vee + 0.0&
GND-0.05 GND-O.O&

LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
kO
kO
V
V

DC Common-Mode
Error .

Over Common-Mode
Input Range

±Ys

±%

±Ys

±%

±%

LSB

Power Supply Sensitivity

Vee=5 Voe±5%
VREF = 4.75V

±Ys

±%

±Ys

±%

±%

LSB

2-297

o
o....
o
o

UI

~
o
.....

o

Electrical Charact,eristics (Qontinued) The following specifications applyfor VCC ;;= 5V. VREF =

5V. fClK =

1.-8 MHz unless otherwise specified. Boldface ,lim,lts apply from TMIN to TMAX; ~II other limits TA = T) = 25~C.

C

ADC1005BCJ
ADC1005CCJ'



1.7

9

1.&

, ~-5~'eldAk+\25Je j;.o'

~

1.5

iu

. 500

'Delayf'rom Fallln~ 'Edge ~f

"
ClK IN Schmitt Trip Levels
vs Supply Voltage

RD to Output Data Valid vs
load Capacitance
'

3,5
~.

"

1.3
4.6U

,

V.

~

I--

>, 2.7

..'"..'"

C>

200

III

2.3

!!

1.9

--fili"e~;:rA~ +121i"e

9
C>

~ 30U

~

3.1

C>

1

--

V_

~

~

3

I

~
400

. >.

I

.

. ',:'

100
4.75

5.25

5.00

o

5,50

200

400

eoo

BOO

1.5
4.&0

1000

LOAD CAPACITANCE (pF)

VCC -SUPPLY VOLTAGE (Voe)

Output Current vs
Temperatilre
B

4,7&

&,00

&.25

&.50

Vec -SUPPLY VOLTAGE (Voel

Typical Linearity Error
vs Clock Frequency
1

Vee= 5Vo

r---r---""",.--='

I---t~--+·;,::,:,:'v
~ 0,8
....
0.6

DATA OUTPUT
BUFFERS

IS~U~C~

"':'OUT "2,4 VDC

~

0,4 f--25~&-f....l~-+----,---I

_

0,2

~

0

fD -0.2

-0,4 f---+---+-----I
...;~ -.0,6
f---+---+---,

.

.

::; -0,8

r;;~m.K" OA VOC F

2
~50,

-2&

0 , 2&,. &0.

7&

IOU 12&

f---+---+---,

-1~-~-~~--~
2,6
1,0
1.8
0,2

CLOCK FREQUENC.' (MHz)

TA - AMBIENTTEMPERATURE ('C)

TLIHI5261-4'

Timing Diagrams
StartCotaverslcin .

\
(LAST DATA WAS READ)

I

....'

~

~~~.~,~------~

(LAST DATA WAS NOT READ)

TLlH15261-5

Output Enable and. Reset INTR
INTR RESET

Jiij

2NORO\

/

'--.- - I
I,..

DATA
OUTPurs- -

-

-

-

-

-

. '" . TRI·STATE"'
...,. .... -

--

J
-

-""\

LS
eYrE

}- __

'----'

TLlHI5261-6

Note: AI11Iming 19 measured from the 50% vo(1age points.

2-300

l>

c

o......

Timing Diagrams (Continued)

g

CI'I

Byte Sequencing for ADC1005
Byte
8·Blt Data Bus Connection
Order DB7 DBS
DB5 DB4 DB3 DB2 DB1

DBO

1st

MSB
Bit 9 BitS Bit 7 Bit 6 BitS Bit 4 Bit3 Bit 2

2nd

LSB
Bit 1 Bit 0

0

0

0

0

0

0

Block Diagram
RESET
INPUT PROTEcnON

FOR ALL LOGIC INPUTS
TO INTERNAL

I

CIRCUIT

elK 8

'NPUT

START CONVERSION
(FRESn-''D''

SAR

vREFo-------------~[~_:"j~.J~~!I~I1~~~~I.:L:A:Tc:H:J
OAC
(NOTE 2)

INTRF/F

vlOUTl

AGIO

fII

V'.I+lo-+-IH~:J--.t

V'.I-Io-+-....- . . I

AGeI0U5Za.,!N

"""""""IF

-J

1-400"

B~~EII1I"O:::::::::::::I:::~------------~;.;;;;.:;:~~----------------~s.rJ
o
TRI.sTATE CONTROL
RESET

Note 1: "CS shown

twice for clarity.

Note 2: SAR = Successive Approximation Register.

.,". OUTPUT ENABlE
FIGURE 1.

2·301

TL/H/5261-11

8...

8c

Functional Description
1.0 GENERAL OPERATION
A block diagram of the AID converter is shown in Figure 1
All of the inputs and outputs are shown and the major logic
control paths are drawn in heavier weight lines.

1.4 Free·Runnlng and Self·Clocklng Modes
For operation in the free-running mode an initializing pulse
should be used, following power-up, to ensure circuit operation. In this application, the CS input is grounded and the
WR input is tied to the INTR output. This WR and INTR
node should be momentarily forced to logic low following a
power-up cycle to ensure start up.
The clock for the AID can be derived from the CPU clock or
an external RC can be added to provide self-clocking. The
ClK IN makes' use of a Schmitt trigger as shown in Figure 2.

1.1 Converter Operation
The ADC1005 uses an advanced potentiometric resistive
ladder network. The analog inputs, as well as the taps of
this ladder network are switched into a weighted capacitor
array. The output of this capacitor array is the input to a
sampled data comparator. This comparator allows the successive approximation logic to match the analog input voltage [VIN( +) - VIN( -)1 to taps on the R network. The most
significant bit is tested first and after 10 comparisons (80
clock cycles) a digital 10-bit binary code (all "1"s = fullscale) is transferred to an output latch.

eLK R
19
R

1.2 Starting a Conversion
The conversion is initialized by taking CS and WR simultaneously low. This sets the start flip-flop (F IF) and the resulting "I" level resets the 10-bit shift register, resets the interrupt (INTR) F/F and inputs a "I" to the D flop, F/F1, which
is at the input end of the 10-bit shift register. Internal clock
signals then transfer this "I" to the Q ouput of F IFI. The
AND gate, Gl, combines this "I" output with a clock signal
to provide a reset signal to the start F/F. If the set signal is
no longer present (either WR or CS is a "I") the start F/F is
reset and the 10-bit shift register then can have the "I"
clocked in, allowing the conversion process to continue. If
the set signal were still present, this reset pulse would have
no effect and the 10-bit shift register would continue to be
held in the reset mode. This logic therefore allows for wide
and WFi signals. The converter will start after at least
one of these signals retur(ls high and the internal clocks
again provide a reset signal for the start FIF.
To summarize, on the high-to-Iow transition of the WR input
the internal SAR latches and the shift register stages are
reset. As long as the CS input and WR input remain low, the
AID will remain in a reset state. Conversion will start after at
least one of these inputs makes a low-ta-high transition.

eLK IN

,_ ....

~

4

eLK

AID '

TL/H/5261-12
,

'

1

fClK '" 1.1 RC

FIGURE 2. Self·Clocklng the AID
2.0 REFERENCE VOLTAGE
The voltage applied to the reference input of these converters defines the voltage span of the analog input (the difference between VIN(MAX) and VIN(MIN) over which the 1024
possible output codes apply. The devices can be used in
either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a
voltage source capable of driving the reference input resistance of typically 4.6 kG. This pin is the top of a resistor
divider string used for the successive approximation conversion.
In a ,atiol11etric system '(Figure 3a) the analog input voltage
is proportional to the voltage used for the AID reference.
This voltage is typically the system power supply, so the
VREF pin can be tied to Vee. This technique relaxes the
stability requirements of the system references as the analog input and AID reference move together maintaining the
same output code for a given input condition.
For absolute accuracy (Figure 3b), where the analog input
varies between very specific voltage limits, the reference pin
can be biased with a time and temperature stable voltage
source. The lM385 and lM336 reference diodes are good
low current devices to use with these converters.
The maximum value of the reference is limited to the Vee
supply voltage. The minimum value, however, can be small
to allow direct conversions of transducer outputs providing
less than a 5V output span. Particular care must be taken
with regard to noise pickup, circuit layout, and system error
voltage sources when operating with a reduced span due to
the increased sensitivity of the converter (1 lSB equals
VREF/l024).

cs

1.3 Output Control
After the "I" is clocked through the 10-bit shift register
(which completes the SAR search) it causes the new digital
word to transfer to the TRI-STATE output latches. When the
XFER Signal makes a high-to-Iow transition the one' shot
fires, setting the INTR F IF. An inverting buffer then supplies
the INTR output signal.
Note that this §:f control of the INTR F/F remains low for
approximately 400 ns. If the data output is continuously enabled (CS and RD both held low) the INTR output will still
signal the end of the conversion (by a high-to-Iow transition). This is because the §:f input can control the Q
output of the INTR F/F even though the RESET input is
constantly at a "I" level. This INTR output will therefore
stay low for the duration of the §:f signal.
When data is to be read, the combination of both CS and
Ri5 being low will cause the INTR F/F to be reset and the
TRI-STATE output latches will be enabled.

2-302

Functional Description

(Continued)

5V

5V

J
Vee

Vee

~VINI+I

YlNI+1

VREF

t--

2.6V

~ ~ LM385·2.6
-

1----oIVINI-I

YlNI-I

AGND

AGND

1

1

FIGURE 3a. Ratlometrlc

TUH/5261-17

TUH/5261-18

FIGURE 3b. Absolute with a Reduced Span

3.0 THE ANALOG INPUTS
input at 5V, this DC current is at a maximum of approximately 5 pA Therefore, bypass capaCitors should not be used at
the analog inputs or the VREF pin for high resistance sources (> 1 kO). If input bypass capaCitors are necessary for
noise filtering and high source resistance is desirable to
minimize capacitor size, the detrimental effects of the voltage drop across this input resistance, which is due to the
average value of the input current, can be eliminated with a
full-scale adjustment while the given source resistor and input bypass capaCitor are both in place. This is possible because the average value of the input current is a linear function of the differential input voltage.

3.1 Analog Differential Voltage Inputs and
Common·Mode Rejection
The differential inputs of these converters reduce the ef·
fects of common·mode input noise, which is defined as
noise common to both selected" + .. and" -" inputs (60 Hz
is most typical). The time interval between sampling the
.. + .. input and the .. -" input is half of an internal clock
period. The change in the common-mode voltage during this
short time interval can cause conversion errors. For a sinusoidal common-mode signal, this error is:

4

VERROR(MAX) = VPEAK (271' fCM) X fCLK

3.4 Input Source Resistance
large values of source resistance where an input bypass
capacitor is not used, will not cause e"ors if the input currents settle out prior to the comparison time. If a low pass
filter is required in the system, use a low valued series resistor (S:1 kO) for a passive RC section or add an op amp RC
active low pass filter. For low source resistance applications
(S:0.1 k.!1) a 4700 pF bypass capacitor at the inputs will
prevent pickup due to series lead induction of a long wire. A
1000 series resistor can be used to isolate this capaCitor both the R and the C are placed outside the feedback loop
- from the output of an op amp, if used.

where fCM is the frequency of the common-mode signal,
VPEAK is its peak voltage value and fCLK is the clock frequency at the ClK IN pin.
For a 60 Hz common-mode signal to generate a 1/4 lSB
error (1.2 mV) with the converter running at 1.8 MHz, its
peak value would have to be 1.46V. A common-mode signal
this large is much greater than that generally found in data
aquisition systems.
3.2 Input Current
Due to the sampling nature of the analog inputs, short duration spikes of current enter the .. + .. input and exit the .. - ..
input at the clock rising edges during the conversion. These
currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period.

3.5 Noise
The leads to the analog inputs (pins 6 and 7) should be kept
as short as possible to minimize input noise coupling. Both
noise and undesired digital clock coupling to these inputs
can cause system errors. The source resistance for these
inputs should, in general, be kept below 1 kO. larger values
of source resistance can cause undesired system noise
pickup. Input bypass capaCitors, placed from the analog inputs to ground, can reduce system noise pickup but can
create analog scale errors. See section 3.2, 3.3, and 3.4 if
input filtering is to be used.

3.3 Input Bypass CapaCitors
Bypass capacitors at the inputs will average the current
spikes noted in 3.2 and cause a DC current to flow through
the output resistances of the analog signal sources. This
charge pumping action is worse for continuous conversions
with the VIN( +) input voltage at full scale. For continuous
conversions with a 1.8 MHz clock frequency with the VIN( + )

2-303

Functional Description

(Continued)

4.0 OFFSET AND REFERENCE ADJUSTMENT
4.1 Zero Offset
The zero error of the AID converter relates to the location
of the first riser of the transfer function and can be measured by grounding the V(-) 'input' and applying a small
magnitude positive voltage to the V( +) input. Zero error is
the difference between the actual DC input voltage that is
necessary to just cause an output digital code transition
from 00 0000 0000 to 00 0000 0001 and the ideal 1/2 LSB
value (1/2 LSB = 2.45 mV for VREF = 5.0 Voe).
The zero of the AID normally does not require adjustment.
However, for cases where VIN(MIN) is not ground and in
reduced span applications (VREF < 5V), an offset adjustment may be desired. The converter can be made to output
an all zero digital code for an arbitrary input by biasing the
AID's VIN( -) input at that voltage. This utilizes the differential input operation of the AID.

zero reference voltage at the corresponding .. -" input
should then be adjiJsted to just obtain the OOOHEX 001 HEX
code transition.
The full-scale adjustment should be made [with the proper
VIN( -) voltage applied) by forcing a voltage to the VIN( + )
input given by:
V (+)FSadJ'=V
_1.5[(VMAX-VMIN)]
IN
,MAX
1024
where VMAX = the high end of the analog input range and
VMIN = the low end (the offset zero) of the analog range.
(Both are ground referenced).
The VREF (or Vee) voltage is then adjusted to provide a
code change from 3FFHEX to 3FEHEX. This completes the
adjustment procedure.
For an example see the Zero-Shift and Span-Adjust circuit
below.

4.2 Full Scale
The full-scale adjustment can be made by applying a differential input voltage that is 1Yz LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the VREF input for a digital output code that is just
changing from 1111111110to 1111111111.

5.0 POWER SUPPLIES
Noise spikes on the Vee supply line can cause conversion
errors as the comparator will respond to this noise. A low
inductance tantalum filter capacitor should be used close to
the converter Vee pin and values of 1 ,..F or greater are
recommended. If an unregulated voltage is· available in the
system, a separate LM340LAZ-5.0, TO-92, 5V voltage regulator for the converter (and the other analog circuitry) will
greatly reduce digital noise on the Vee supply.

4.3 Adjusting for an Arbitrary Analog
Input Voltage Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal that does not go to ground), this new zero reference
should be properly adjusted first. A VIN( +) voltage that
equals this desired zero reference, plus 1/2 LSB (where the
LSB is calculated for the desired af/alog span, 1 LSB =
analog span/1024) is applied to selected" + .. input and the

A single point analog ground that is separate from the logic
ground ppints should be used. The power supply bypass
capacitor and the self-clocking capaCitor ,(if used) should
both be returned to the digital ground. Any V REF bypass
capacitors, analog input filters capaCitors, or input signal
shielding should be returned to the analog ground point.

Vce

15VDCI

vcc~-i~----------------~

+

f'

o .F

ADC1005

3.9k

:~

?1.2k

ADJ

---,...-,

r--I
I

It

I

3V

1/2LM3~B

:r

--

SETS VOLTAGE SPAN

~;:~ lpF ~

SETS ZERO
CODE VOLTAGE

Z.lk

330

I
I

LM336·Z.5

j ~

I
I
I
I

I

L __________ JI

lk
ZVDC
ZERO ADJ

~

~

TL/H/5261-16

Figure 4. Zero-Shift and Span-Adjust (2V

2-304

~

VIN

~

5V)

~

o
o....

Typical Applications

o

5V
20

cs

VCC

iiii
Wit

ClK R

11

13
14
15
16
17

18

19
TRANSDUCER

10k

ClK.IN

INTR
12

o
en

10·BIT RESOLUTION
OVER
ANALOG INPUT
VOLTAGE RANGE

007

DB6
DB5

ADC1005

VIN(+'
DIFF INPUTS

DB4

VINH

DB3

A GND

DB2

5V

VREF

OBI

o GND

DBO

":'

10

TL/H/5261-13

Handling ± 5V Analog Inputs

Operating with Ratlometrlc Transducers

Vee 15 VDe)

Vee 15 VDC)

Vee

.....-If--I\\N(+'
3.3k

":'

20k
0.7 Vee
lk

¥REF

ZERO
ADJ

\\N(-I

Jl~F

VwEF

±5V

10 TURN
TRIM POT

lk

7.ik

3k

AGND

VINI-)

AGND

= 0.15 Vee

TL/H/5261-14

TL/H/5261-15

15% of Vee ,;; VXDR ,;; 85% of Vee

fII

TRI-STATE Test Circuits and Waveforms
Vee
Vee ---Ir~=--­
i!II

DATA :::
OUTPUTS
GND

~:IH

~

--------'=
TL/H/5261-9

t,.=20 ns

TLlH/5261-7

tOH
Vee

Vee

GND

DH

DATA
OUTPUT

Vee
DATA
OUTPUTS

~

-1011

VOL

',=20 ns

TLlH/5261-8

2-305

TLlH/5261-10

Ordering Information
Part Number

Package
Outline

Temperature
Range

ADC100SBCJ-1

J20A,

O"C to + 7(rC

ADC100SBCJ

J20A

-40'C to +8S'C

Linearity
Error
±%LSB

2-306

Part Number

Package
Outline

ADC100SCCV:

V20A

, ,ADC100SCCJ-1

J20A

ADC100SCCJ

J20A

Temperature
Range

Linearity
Error

O'Cto +70'C
±1 LSB
....::40·Cto +8S'C

,----------------------------------------------------------------,
t!lNational Semiconductor

~

g
.....
C)
.....

UI

A
......
~

g.....

ADC10154, ADC10158 10-Bit Plus Sign 4 J-LS ADCs

with 4", or 8",Channel MUX, Track/Hold and Reference
General Description

o.....

UI
CD

Features

The ADC101S4 and ADC101S8 are CMOS 10-bit plus sign
successive approximation A/D converters with versatile analog input multiplexers, track/hold function and a 2.SV
band-gap reference. The 4-channel or 8-channel multiplexers can be software configured for single-ended, differential
or pseudo-differential modes of operation.
The input track/hold is implemented using a capacitive array and sampled-data comparator.
Resolution can be programmed to be 8-bit, 8-bit plus sign,
10-bit or 10-bit plus sign. Lower-resolution conversions can
be performed faster.
The variable resolution output data word is read in two
bytes, and can be formatted left justified or right justified,
high byte first.

• 4~ or 8- channel configurable multiplexer
• Analog input track/hold function
• OV to SV analog input range with single + SV power
supply
• -SV to +SV analog input voltage range with ±SV supplies
• Fully tested in unipolar (single + SV supply) and bipolar
(dual ± SV supplies) operation
• Programmable resolution/speed and output data format
• Ratiometric or Absolute voltage reference operation
• No zero or full scale adjustment required
• No missing codes over temperature
• 'Easy microprocessor interface

Key Specifications

Applications

•
•
•
•
•
•
•
•

• Process control
• Instrumentation
• Test equipment

Resolution
Integral linearity error'
Unipolar power dissipation
Conversion time (10-bit + sign)
Conversion time (8-bit)
Sampling rate (10-bit + Sign)
Sampling rate (8-bit)
Band-gap reference

10-bit plus sign
±1 LSB (max)
33 mW (max)
4.4,...s (max)
3.2,...s (max)
166 kHz
207 kHz
2.SV ±2.0% (max)

ADC10158 Simplified Block Diagram
CLK

CHO
CHI
CH2
CH3

cs

WR

iii)

fII

~~--~~~~::~~~~~~~~~~~~~~~------r:~~mr

oBO (MAO)

OBI (MAl)
oB2 (MA2)

CH4

083 (MA3)

CH5

oB4 (MA4)

CH6

085 (ulS)

CH7

DB6
087

AV'

(a/iO)
(L/R)

VREF +
VREF

-

VREFOUT

0V'
OGNo

V'
TLlH/II225-1

2-307

,:8
....
c

Absolute Maximum Ratings (Notes 1 & 3)

Operating Ratings (Notes 2 & 3)

~o....

If Military/Aerospace specified devices are required;
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
PositiveSupplyVoltage(V+ = AV+ ~ DV+)
6.5V
,
-'S.5V
Negative Supply Voltage (\1-) "
' 13V '
Total Supply Yoltage (V+, - V-:) ,
, ,

Temperature Range
ADC1 0154CIN, ADC10154CIWM,
ADC1 0158CIN, ADC10158CIWM

....

o
C

i

Soldering Information
N Packages (10 Sec)
J Packages (10 Sec)
, SO Package (Note 7):'
Vapor Phase (60 Sec) "
Infrared (15 Sec) ,,--

,

VREF+
VREF-

DGND
:

-4.5Vto -5.5V
11V

AV+ +0~05 Voc to'V~ - 0.05,Voc

"

AV+ + 0.05 Voc to V:- - 0.05 Voc
0.5 Vocto V+

VREF (VREF+ - VREF-)

2000V ",

,,,

.,',

260'C
300'C

,-

21S'C
220'C

,

Storage Temperature"
Ceramic DIP Packages,
Plastic DIP and SO Packages

Bipolar Negative Supply
Voltage (V-)
'V+ -V'-

500mW

,

4.5 VOC to 5.5 Voc

Unipolar Negative Supply
Voltage (V-)

6.6V
Total Reference Voltage (VREF+ - VREF-)
Voltage at Inputs and
V- - 0.3VtoV+ +'0.3V
Outputs
Input Current at A~y Pi~ (Note 4)
±5mA
±20mA
Package Input Current (Note 4)
Package Dissipation at TA = 25'C (Note 5)
" ESC Susceptibility (Note 6) ,

-40'C:s; TA ~ +85'C

Positive Supply Voltage
(V+ = AV+ = DV+)

"

,Q

TMIN :s; TA:S; TMAX

, -65'Cto,+150'C
-40'Cto + 150'C
-,'

,.".

Electrical Characteristics

:'.,

."

ThefoliowingspecificationsapplyforV+ = AV+ '7' DV+ = + 5.0Voc, VREF+ = 5.000Voc, VREF- ='GND, v- = GNDfor
unipolar operation or V- = -5.0 Voc for bipolar operation, and fClK = 5.0 MHz unless otherwise specified. Boldfacell",lts
apply for, TA = TJ = T MIN to T MAX; ~II other liI:nits TA = TJ = 25'C. (Notes 8, 9, and 12)

Symbol

Parameter

..

,,-

CIN and CIWM
Suffixes

Typical
(Note 10)

Conditions
-"

,

, UNIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARA,CTERISTICS '
"

Resolution

,',:'

"'.

','

.

, .
.

.~

10

Unipolar Integral
Linearity Error

VREF+ = 2:SV
VREF+ = '5.0V

±0.5

Unipolar Full·Scale Error

VREF:I- = 2.5V
VREF+ = 5.0V

±0.5

,"

, Unipolar Offset Error

VREF+ = 2.5V
VREF+ = 5.0Y

, Unipolar Total Unadjusted
, Error (Note 13)

VREF-t = 2.5V
VREF~ = 5.0V

, Unipolar Power Supply
Sensitivity
Offset Error
Fuli·Scale Error
Integral Lin~arity Error

V-F = +5V ±10%
VREF+ = 4.5V
.

+ Sign

"

±1

±1.5

, LSB
LSB (Max)

H.B

LSB
[SB(Max)

±2

LSB
LSB(Max)

±1.5

;

±0.25
±0.25
±0.25

,'r'

"

2-308

Bits
LSB
LSB (Max)

±1

,

Units
(Limit)

Limits
(Not!! 11)

.: ' ..

±1
±1-

LSB (Max)
LSB (Max)
LSB

:I>

c

Electrical Characteristics
The following specifications apply forV+ = AV+ = DV+ = + 5.0 VOC, VREF+ = 5.000 Voc, VREF- =. GND, V- = GND for
unipolar operation or V- = -5.0 Voc for bipolar operation, and fCLK = 5.0 MHz unless otherwise specified. Boldface limits
apply for T A = TJ = T MIN to T MAX; all other limits TA = TJ = 25'C. (Notes 8, 9, and 12) (Continued)

Symbol

Parameter

......o
~
g
o

Conditions

Typical
(Note 10)

CINandCIWM
Suffixes
Limits
(Note 11)

Units
(Limit)

......
Q

UI
CD

BIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICS
Resolution
Bipolar Integral
Linearity Error

VREF+ = 5.0V

Bipolar Full-Scale Error

VREF+ = 5.0V

Bipolar Negative Full-Scale
Error with Positive-Full
Scale Adjusted

VREF+ = 5.0V

Bipolar Offset Error

VREF+ = 5.0V

Bipolar Total Unadjusted
Error (Note 13)

VREF+ = 5.0V

Bipolar Power Supply
Sensitivity
Offset Error
Full-Scale Error
Integral Linearity Error
Offset Error
Full-Scale Error
Integral Linearity Error

10 + Sign

Bits

±1

LSB(Max)

±1.25

LSB(Max)

±1.25

LSB(Max)

±2.5

LSB(Max)

±3

LSB(Max)

V+ = +5V ±10%
VREF+ = 4.5V

±0.5
±0.5
±0.25

±2.5
±1.5

LSB(Max)
LSB(Max)
LSB

V- = -5V ±10%
VREF+ = 4.5V

±0.25
±0.25
±0.25

±0.75
±0.75

LSB(Max)
LSB(Max)
LSB

UNIPOLAR AND BIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICS
Missing Codes

0

DC Common Mode
Error (Note 14)

VIN+ = VIN= VINwhere
+5.0V ~ VIN ~ -5.0V
+5.0V ~ VIN ~ OV

±0.25
±0.25

±0.75
±0.5

LSB(Max)
LSB (Max)

Reference Input Resistance

7

4.5
9.5

kll (Max)
kll (Max)

CREF

Reference Input Capacitance

70

VAl

Analog Input Voltage

(Y++0.05)
(Y--0.05)

V (Max)
V (Min)

CAl

Analog Input Capacitance

Bipolar
Unipolar
RREF

Off Channel Leakage
Current
(Note 15)

pF

pF

30
On Channel = 5V
Off Channel = OV

-400

-1000

nA(Max)

On Channel = OV
Off Channel = 5V

400

1000

nA(Max)

2-309

•

-=~g
o

o

Electrical Characteristics

ThEifoliowingspecificationsapplyforV+ = AV+ = DV+ = + 5.0Voc, VREF+ = 5.000Voc, VREF- = GND, v- = GNDfor
unipolar operation or V- = -5.0 VOC for bipolar operation,and fClK = 5.0 MHz unless otherwise specified. Boldface limits
,
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25'C. (Notes 8, 9, and 12) (Continued)
Symbol

Parameter

Conditions

Typical
(Note 10)

Limits
(Note 11)

Units
(Limit)

DYNAMIC CONVERTER AND MULTIPLEXER CHARACTERISTICS

 AV+ or DV+),the current at that pin should be limited to 5 mA.
The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an Input current of 5 mA to four.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJI118Xo 6JA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po = (TJmax - TtJI6JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJmax = 150"C. The typical thermal resistance (6JAl of these parts when board mounted follow: ADC10154 with BIN and CIN suffixes 65'C/W, ADCIOl54
with BIJ, CIJ and CMJ suffixes 49'C/W, ADCI 0154 with BIWM and CIWM suffixes 72"C/W, ADCI 0158 with BIN and CIN suffixes 59'C/W, ADCI 0158 with BIJ, CIJ,
and CMJ suffixes 46"C/W, ADCIOl58 with BIWM and CIWM suffixes 68'CIW.
Note 6: Human body model, 100 pF capaCitor discharged through a 1.5 kO resistor.
Note 7: See AN-450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section titled "Surface Mount" found In any post·1986 National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 8: Two on·chip diodes are tied to each analog input as shown below. They will forward-conduct for analog input voltages one diode drop below V- supply or

ov+

.-Q----~~
I

,n. t

TO INTERNAL
CIRCUITRY

Analog Inputs CHO,-CH7 _

~

.9
I
I

....

--~----.
TLlH/II225-4

one diode drop greater than V+ supply. Be careful during testing at low V+ levels (4.5V), as high level analog inputs (5V) can cause an Input diode to conduct,
especially at elevated temperatures, which will cause errors for analog inputs near full-scale. The specification allows 50 mV lorward bias of either diode; this
means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct Exceeding this range on an
unselected channel will corrupt the reading 01 a selected channel, This means that II AV+ and DV+ ara minimum (4.5 Voe) and V- is a m8ximum (-4.5 Voe) lull
scale must be ,; ± 4.55 Voe.

2-312

l>

C

o.....
o.....
en

Electrical Characteristics (Continued)

.
:IT

Note 9: A diode exists between AV+ and DV+ as shown below.

"

'

:Av+

oV+

...."'l>"

'

I
I

I
I
I

TO INTERNAL
CIRCUITRY

g
.....

,0

.....

TO INTERNAL
'CIRCUITRY

en
co
TLlH/11225-5

To guarantee accuracy, it is required that the AV+ and DV+ be connected together to a power supply with separate bypass filter at each V+ pin.
Note 10: Typicals are at TJ

~

TA

~

2S'C and represent most likely parametric norm.

Nole 11: Tested limits are guaranteed to National's AOQl (Average Outgoing Quality Level).
Note 12: One LSB is referenced to 10 bits of resolution.
Note 13: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
Note 14: For DC Common Mode Error the only specification that is measured is offset error.
Note 15: Channel leakage current is measured after the channel selection.

Note 16: All the timing specifications are tested at the TTL logic levels, VIL

~

O.BV for a falling edge and VIH

~

2.0V for a rising.

Ordering Information
Industrial -40'C"; TA"; 85'C

Package

ADC10154CIN

N24A

ADC10154CIWM

M24B

ADC10158CIN

N28B

ADC10158CIWM

M28B

"",.

tI

2·313

=

....
....o

Electrical Characteristics (Continued)

~........

----I'P(
~ ~~~~~~ALE

011,1111,1111(+1023)
011,1111,1110(+1022)

o

, ",

~
1------

000,0000,0010 (2)
000,0000,0001 (1)
000,0000,0000 (0)

"

,"

TRANSITION

""

-......!f-L=------------I

, ""
""
", "
100,0000,0001 (-1023)
100,0000,0000 (-1024)

.J NEJTIVE

FULL-SCALE
TRANSITION

TLlH111225-6

FIGURE 1A, Transfer Characteristic

ai'

'"

+3LSB

ci
II<

0

II<

ei

+2LSB
LINEARITY
ERROR
+1 LSB

NEGATIVE INPUT RANGE
NEGATIVE
FULL-SCALE ERROR
WITH POSITIVE
FULL-SCALE ADJUST

-1 LSB

POSITIVE INPUT RANGE

-2LSB

-3 LSB
OUTPUT CODE
(from -1024 to + 1023)
TLlH/11225-7

FIGURE 18. Simplified Error Curve vs Output Code

2-314

l>
C

Typical Converter Performance Characteristics

o....

....
Q

Total Positive Supply
Current (01 + + AI +)
vs Temperature

Total Positive Power
Supply Current (01 + + AI +)
vs Clock Frequency

lO~~~~~=-~~~

5
Av' • Dv' •
TA. = 25 G C

.en

....l>

'01:00

Offset Error
vs Temperature

il

C

o....

....
en
Q

·1111111

Bi~'~.r (V"

CD

• -5V)

i-""

O~~~~~~~~~

!nlpol.r,~Y.' • GN~!"

2

-55 -35 -IS 5 25 <15 65 85 IDS 125

10

TEMPERATURE (OC)

100

1000

1--1-\--1---1 VRE, - = GNO
felK = 5WHz
TA = 25°C

(V" • -5V)

2.5

'ii1 0.8

'ii1 2.0

.

..

~

~
Ii!
15

0.6

§

§

0.4

z

°oL.L-L.......J:::::::t=:::!
REFERENCE VOLTAGE (V)

r-r-...,..-.,....---:---......

0.8
0.6

§
~
fil

0.4

0.2

-80

0.0

-100
10000

70

'ii1

3

~

-

REFERENCE VOLTAGE (V)

AV" = Dv+ .. VRET + = +5.DV
VREr - • eND

I

=SNHz

I

v- .. GND

60 fcue

f A ·25OC

+

'/'

Sampling Rlt. • 108 kHz

~z

50

~

40

~
o

Unipolar

~ 'GNO)

1D-Bit Unsigned
Signal-to-Noise + THO Ratio
vs Input Signal Level

e

-60

==+5.0V
GND

f CLK ' 5MHz
1A = 25°C

Bipolar
(V" = -5V)

°

20

I I I I

D~

VR£F

I I'--..

0.0

Spectral Response with
50 kHz Sine Wave
Av' :: O~ • VREr + • +5.0V
¥tiEr • GNO
V" = GNO
'ii1
3 -20 'elK = S.,Hz
T. = 25 0 C
-40 Sampling Rata = 108 kHz. _

.

1.0

TEMPERATURE (OC)

Linearity Error vs
Clock Frequency

CLOCK FREQUENCY (kHz)

1.5 f-;

:; 0.5

0.0 '-~~...t.........L.......J.....J...-L-I.-'
-55 -35 -15 5 25 45 65 85 105125

I

t~

.1

z

:; 0.2

1000

Linearity Error vs
Reference Voltage

1.0

~

1
I--I----'t.-.....,r- Bipolar

100

-15 5 25 45 65 85105125
TEMPERATURE (oC)

Linearity Error
vs Temperature

6r--'--A~~'-~~'-v-m~+-=-+-'sv

10

-55~35

CLOCK FREQUENCY (kHz)

Offset Error vs
Reference Voltage

1.0

-2~~~~~~~~~

10000

, '/'

V

V

30

5 10 15 20 2S 30 35 40 45 50 55
FREQUENCY (kHz)

-30 -25

-20

-15

-10

-5

INPUT SIGNAl. LEVEL (dB)
TLlH/11225-8

2-315

m

an

"P-

C)

"P-

r-----------------~------~~----~~--~~--~--~----~~----------------------,

Typical Reference Performance
Characteristics .
,.
,

.~

Output Di'lff
. . Load Regulatlori .

an
"P-

+5.D

"P-

O

~

I
I

...0
+3.0

C)

!
!i1

+2.0

U

.'" ,-0.5
oCI
-,.0

SOURCING

-1.5
-2.5

.

l
10mV

'oS

""""",..-If-+-++-+-l
0 I--f"~::..j_=-=
..+_-+-'i
2

,'.5. . , r--t:::=.;~t-.....
~.--r--I--+~

, ,I:l

T.

.

;" ;.-1 r--I--+~~r--f-'"+~

..

i

~21-+-+-:-:I-'-I-1-+--l

"""

-3r--I--+~--r--I--+~

I I
I I ..

'-2.0
6

4r-~~~--r-~-+~

,

'.,

+1.0

s~~~~~~'--r-'

I

SiNKING

VB Temperature
(3 Typical Parts)

Line Fiegulatl9ri
(3 Typlclli Parts)

-4r-~-+~~r--I--+~

3

4 3 2 I 0 ~I -2 -,3
SOURCING
SINKING
OUTPUT CURRENT (mAl

~

-75

~UPPLY VOLTAGE

Available.
Output
VB Supply Voltage.

-

-25 0 25

...... r-..
...... I-....
75

.

,25

JUNCTION TEMPERATURE

C,urrent

20

,8
~

!

16

14

.,

j 1:
.

~

,~

,

.,.'

J

8

J

,V
.'
. SUPPLY VOLTAGE
TL/HI1 '225-9

,"t,

2~16

r--------------------------------------------------------------------.~

C

Leakage Current Test Circuit

(")

.....

Q
.....

+5V

U1

~C

IOfF
CHO

(")
.....

ADC10158

L..-___

Q

.....

U1

-r-----~'"""CHI

CD

CH2
CH3
CH4
CH5
CH6

Channel
Vollage
Selecl

CH7

TLlH/11225-10

TRI-STATE Test Circuits and Waveforms
v+

t.

Ro
GND

I-.....-t+

DATA
OUTPUT

VOH
DATA
OUTPUT GND
TLlH/11225-12

TL/H/11225-11

V+---+:m.::--GIlD

DATA

1-+--, OUTPUT

v·

IG.

II

DATA
OUTPUT VOL._ _.....
TL/H/11225-14
TL/H/11225-13

2-317

co

an
....
CI
....
g

r---------~----------------------------------------------------------------------,

Timing Diagrams

•....an

CI
....
g

CLK
CLK+2
(In'.rna')

®

-----Ie

090-097

Analog
'npu'

___ :~~_'o: _____

L
----+1'1
\IL. _....J(

-!!- ______________ -!!- ____

~
__. _ _ _ _ _ _ _ ___!.,.

TR.-STATE _______ _

__----~r~--------------

~

Hold
Capacitor
Vortage

(Internal)

TL/H111225-15

DIAGRAM 1. Starting a Conversion with New MUX Channel and Output Configuration

CLK

®



o

Timing Diagrams (Continued)

o....

....
CII
~
o
o
....
....
Q

CLK

CLK + 2
(Internal)

I

Cs

WR

-

~Ni'L

INT

~I-

l-

I

\
tACC _

TRI-STATE
DBO-DB7 - - - - - - - - - - - - - - - - - - -

I

I

I-- ~C

Q

g:

I

I-tP-l

I

\

i- ~R--l

g

I

J
\

- -

lcRRii

I

t-J
r\

~H' tOH

-----9------8-----'

BYTE 1

TUH/11225-17

DIAGRAM 3. Reading the Conversion Result

Multiplexer Addressing and Output Data Configuration Tables
TABLE I. ADC10154 and ADC10158 Output Data Configuration
Resolution

10-Bits
10-Bits

+ Sign
+ Sign

10-Bits
10-Bits
a-Bits
a-Bits
a-Bits
a-Bits

+ Sign
+ Sign

Output

Control Input

Right-Justified
Left-Justified
Right-Justified

Data Bus Output Assignment

Data

Data Format
8/10

U/S

L/ii

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DBO

L

L

L

Sign
a

Sign
7

Sign
6

Sign
5

Sign

Sign

MSB

4

3

2

9
LSB

First Byte Read
Second Byte Read

Sign

MSB

2

9
LSB

a
L

7
L

6
L

5
L

4

3

L

First Byte Read
Second Byte Read

L
a

L
7

L
6

L
5

L

L

MSB

4

3

2

9
LSB

First Byte Read
Second Byte Read

a
L

7
L

6
L

5
L

4

3
L

First Byte Read
Second Byte Read

Sign
3

Sign

2

Sign
LSB

First Byte Read
Second Byte Read

4

3

2

L

L

L

First Byte Read
Second Byte Read

L
LSB

First Byte Read
Second Byte Read

LSB
L

First Byte Read
Second Byte Read

L
L

L

H

H
L

Left-Justified

L

H

H

MSB

2

9
LSB

Right-Justified

H

L

L

Sign
MSB

Sign
7

Sign
6

Sign
5

Sign

Sign
LSB

MSB
L

7
L

6
L

5
L

L
MSB

L
7

L
6

L
5

L
4

MSB
L

7
L

6
L

5
L

4
L

Left-Justified
Right-Justified
Left-Justified

H
H
H

L

H
H

H
L

H

2-319

4

L

L

L

3

2

3

2

L

L

Ell

co

It)
.CI
.-

Multiplexer Addressing and Output Data Configuration Tables (Continued)

o
c

TABLE II. ADC10158 Multiplexer Addressing

~

:;
.-

MUXAddress
MA4 MA3 MA2 MA1

CHO CH1

CI

[;
C

a"Its~o~:>a"

II

Connection Diagrams
Dual-In Line and SO Packages
Av+

Dv+

Av+

Cs
iiii

ViR

CHO

2

CLK

CHI

3

26

CHO

INT

CH2

4

25

CH 1

DBO (MAO)

CH3

CLK

CH2

DBI (MAl)

CH4

INT

CH3

DB2 (MA2)

CHS

DBO (MAO)

VREFOUT
VREF +

DB3 (MA3)

CH6

DBI (MAl)

CH7

DB2 (MA2)

VREF -

DB5 (Ut'S)

VREFOUT
VREF +

DB3 (MA3)

DB4

VDGND

DB6 (aiTo)
12

TL/H/II225-2

WR

DB6 (aiTo)
DB7 (L/R)

DGND

Order Number ADC10154
NS Package Numbers
J24A, M24B or N24A

Cs
iiii

DBS (ut'S)

VTop View

Dv+

27

DB4 (101M)

VREF '-

DB7 (L/R)

2a

TLlH/11225-3

Top View

Order Number ADC10158
NS Package Numbers'
J28A, M28B or N28B

1.0 Pin Descriptions
AV+

DV+

DGND

V-

This is the positive analog supply. This pin
should be bypassed with a 0.1 ,...F ceramic capacitor and a 10 ,...F tantalum capacitor to the
system analog ground.
This is the positive digital supply. This supply
pin also needs to be bypassed with 0.1 ,...F ceramic and 10 ,...F tantalum capacitors to the
system digital ground. AV+ and DV+ should
be bypassed separately and tied to same power supply.
This is the digital ground. All logic levels are
referred to this ground.
This is the negative analog supply. For unipolar
operation this pin may be tied to the system
anaJqg ground or to a negative supply source.
It should not go above DGND by more than
50 mY. When bipolar operation is required, the
voltage on this pin will limit the analog input's
negative voltage level. In bipolar operation this
supply pin needs to be bypassed with 0.1 ,...F
ceramic and 10 ,...F tantalum capacitors to the
system analog ground.
These are the positive and negative reference
inputs. The voltage difference between VREF+
and'VREF- will set the analog input voltage
span.
This is the internal band-gap voltage reference
output. For proper operation of the voltage reference, this pin needs to be bypassed with a
330 ,...F tantalum or electrolytic capaCitor.
This is the chip select input. When a logic low is
applied to this pin the iNA and AD pins are
enabled.

RD

WR

INT

ClK

This is the read control input. When a logic low
is applied to this pin the digital outputs are enabled and the jjijj output is reset high.
This is the write control input. The rising edge
of the signal applied to this pin selects the mUltiplexer channel and initiates a conversion.
This is the interrupt output. A logic low at this
output indicates the completion of a conversion.
This is the clock input. The clock frequency directly controls the duration of ,the conversion
time (for example, in the 10-bit bipolar mode
tc = 22/fcLK) and the acquisition time (tA =

6IfCLKl·
DBO(MAO)- These are the digital data inputs/outputs. DBO
DB7 (l/R) is the least Significant bit ,of the digital output
word; DB7 is the most significant bit in the digital output word (see the Output Data Configuration table). MAO through MA4 are the digital
inputs for the multiplexer channel selection
(see the Multiplexer Addressing tables). U/S
(Unsigned/Signed), B/10, (B/10-bit resolution)
and l/R (left/Right justification) are the digital
input bits that set the AID's output word format
and resolution (see the Output Data Configuration table). The conversion time is modified by
the chosen resolution (see Electrical AC Characteristics table). The lower the resolution, the
faster the conversion will be.
CHO-CH7 These are the analog input multiplexer channels. They can be configured as single-ended
inputs, differential input pairs, or pseudo-differential Inputs (see the Multiplexer Addressing
tables for the input polarity assignments).

2-322

»
c

2.0 Functional Description
held and the actual conversion begins. The number of
clocks required for a conversion is given. in the following
table:
.

The ADC10154 and ADC10158 use successive approximation to digitize an analog input voltage. Additional logic has
been incorporated in the devices to allow for the programmability of the resolution, conversion time and digital output
format. A capacitive array and a resistive ladder structure
are used in the DAC portion of the AID converters. The
structure of the DAC allows a very simple switching scheme
to provide a very versatile analog input multiplexer. Also,
inherent in this structure is a sample/hold. A 2.5V CMOS
band-gap reference is also provided on the ADC10154 and
ADC10158.

Conversion Type
8-Bit
8-Bit

10-Bit
10-Bit

2.1 DIGITAL INTERFACE
The ADC10154 and ADC10158 have eight digital outputs
(DBO-DB8) and can be easily interfaced to an 8-bit data
bus. Taking CS and WR low simultaneously will strobe the
data word on the data-bus into the input latch. This word will
be decoded to determine the multiplexer channel selection,
the A/D conversion resolution and the output data format.
The following table shows the input word data-bit assignment.
DBO

I DB1 I DB2 I DB3 I DB4

MAOi MA 1

I MA2 JMA3j MA4

MUXAddress

DB5
U/S

output data format

I DB6 I DB7

I 8/10 I LlR
Control
Input Data

8

16

9

18

10

20

11

22

Upon completion of the conversion, INT goes low to signal
the AID conversion result is ready to be read., Taking CS
and RD low will enable the digital output buffer and put byte
1 of the conversion result on DBO through DB7. The falling
edge of RD resets the INT output high. Taking CS and RD
Iowa second time will put byte 2 of the conversion result on
DB7-DBO. Table I defines the DBO-DB7 assignement for
different Control Input Data. The second read does not have
to be completed before a new conversion is started.
Taking CS, WR and RD low simultaneously will start a conversion without changing the multiplexer channel assignment or output configuration and resolution. The timing diagram in Figure 2 shows the sequence of events that implement this function. Refer to Diagrams 1, 2, and 3 in the
Timing Diagrams section for the timing constraints that must
be met.
Start

Output first
byte of data

+ Sign

ClK
Cycles(N)

Since the ClK + 2 signal is internal to the ADC, it is initially
impossible to know which falling edge of ClK corresponds
to the falling edge of ClK + 2. For the first conversion, the
riSing edge of WR should occur at least tws ns before any
falling edge of ClK. If this edge happens to be on the rising
edge of ClK + 2, this will 'add 2 ClK cycles to the total conversion time. The phase of the ClK + 2 signal can be determined at the end of the first conversion, when INT goes low.
INT always goes low on the falling edge of the ClK + 2 signal. From the first falling edge of INT onward, every other
falling edge of ClK will correspond to the falling edge of
ClK + 2. With the phase of ClK + 2 now known, the conversion time can be minimized by taking WR high at least tws
ns before the falling edge of ClK + 2.

DBO through DB4 are assigned to the multiplexer address
data bits zero through four (MAO-MA4). Tables II and III
describe the multiplexer address assignment. DB5 selects
unsigned or signed (U/S) operation. DB6 selects 8- or 10-bit
resolution. DB7 selects left or right justification of the output
data. Refer to Table I for the effect the Control Input Data
has on the digital output word.
The conversion process is started by the rising edge of WR,
which sets the "start conversion" bit inside the ADC. If this
bit is set, the converter will start acquiring the input voltage
on the next falling edge of the internal ClK + 2 signal. The
acquisition period is 3 ClK + 2 periods, or 6 ClK periods.
Immediately after the acquisition period the input signal is

Slart a Convertlon with
n.w NUX IIIIlgnment and

+ Sign

CLK+2
Cycles

Output 2nd
byte of data

I;

Conv,r,lon with

t1Id MUX a.slgnment and
output data format

Start
Output first
byte of data

Output 2nd
byte of data

I.

Conversion with

DId NUX assignment and .
output data format

TLlH/11225-19

FIGURE 2. Starting a Conversion without Updating the Channel Configuration, Resolution, or Data Format

2-323

o
.....
o
.....
en

....»
~

c
o
.....
o
.....
en
co

:8.
....

....
g
Q

~....
Q

[)
C
C

2.0 Functional Description (Continued)
The switch position information at the completion of the
successive' approximation routine is a direct representation
of the digital output. This information is then manipulated by
the Digital Output decoder to the programmed format. The
reformatted data is then available to be strobed onto the
data bus (DBO-DB7) via the digital output buffers by taking
CS and RD low.

Digital Interface Hints:
• Reads and writes' can be completely asynchronous to,

ClK.
• In addition to the timing indicated in Diagrams 1 -3. CS
can be tied low permanently or taken low for entire conversions. eliminating all the CS guardbands (teR. tRC.
tew. twc)·
• If CS is used as shown in Diagrams 1-3. the CS guardbands (tCR. tRC. tew, twcl between CS and the RD and
iNA signals can safely be ignored as long as the following
two conditions are met:
1) When initiating a write, CS and iNA must be simultaneously low for at least tw(WF!j ns (see Diagra~ .1>:
The "start" conversion" bit will be set on the rising
edge of WR or CS, whichever is first.
,
,
2) When reading data, understand that data will not be
valid untiltACC 'ns after both CS and RD go 101"" The
output data will enter TRI-STATE tlH'ns or IoH ns after
eitherCS or RD goes high (see Diagrams,2 and 3).

3.0' Applications Information
3.1 MULTIPLEXER CONFIGURATION
The design of these converters utilizes a sampled-dat~
comparator structure which allows a differential analog input
to be converted by the successive approximation routine.
The actual voltage converted is always the difference between an assigned" +" input terminal and a "-" input terminal. The polarity of each input terminal or pair of input
terminals being converted indicates which line the converter
expects to be the most positive: If the assigned "+ " input is
less than the" -" input the converter responds with an all
zeros output code when configured for unsigned operation.
When configured for signed operation the AID responds
with the appropriate output digital code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels. The input channels can be
software configured into three modes: differential, singleended, or: pseudo-differential. Figure 3 shows the three
modes using the 4-channel MUX of the ADC10154. The
eight inputs of the ADC1 0158 can also be configured in any
of the three modes. The single-ended mode has CHO-CH3
assigned as the positive input with the negative Input being
the VREF- of the device. In the differential mode, the
ADC10154 channel inputs, are grouped in pairs, CHO with
CHI and CH2 with CH3. The polarity assignment of each
channel in the pair is interchangeable. ,Finally, in the pseudo-differential mode CHO-CH2 are positive inputs referred
to CH3 which is now a pseUdo-ground. This pseudo-ground
input can be set to any potential within the input commonmode range of the converter. The analog signal,conditio!1ing,
required in transducer-based data acquisition systems is
significantly simplified with this type of input flexibility. On~
converter package can now handle ground-referred inputs
and true differential inputs as well as signals referred to a
specific voltage.
The analog input voltages for each channel can range from
50 mV below V- (typically ground for unipolar operation or
.,...5V for bipolar operation) to 50 mV above V+ = DV+ =
AV+ (typically 5V) without degrading conversion accuracy.
If the voltage on an unselected c~annel exceeds these limits it may corrupt the reading of the selected channel.

2.2 ARCHITECTURE
Before a conversion is started, during the analog input sampling period, the sampled data comparator is zeroed. As the
comparator is being zeroed the channel assigned to be the
positive input is connected to the' AID's input capacitor:
(See the Digital Interface section for a description of the
assignment procedure.) This charges the input 32C capacitor of the DAC to the positive analog input voltage. The
switches shown in the DAC portion of the detailed block
diagram are set for this zeroing/acquisition period. The voltage at the input and output of the comparator are at equilibrium at this point in time. When the conversion is started the
comparator feedback switches are opened and the 32C input capacitor is then switched to the assigned negative input voltage. When the comparator feedback switch opens a
fixed amount of charge Is trapped on the common plates of
the capacitors. The voltage at the input of the comparator
moves away from equilibrium when the 32C capacitor is
switched to the assigned negative input voltage, causing the
output of the comparator to go high ("1 ") or low ("0"). The
SAR next goes through an algorithm, controlled by the output state of the comparator, that redistributes the charge on
the capacitor array by SWitching the voltage on one side of
the capacitors in the array. The objective of the SAR algorithm is to retum the voltage at the input of the comparator
as close as possible to equilibrium.' ,

CHO

+

CHf

+
+
+

CHO, {
CHI
AOC10f54

+(-)

CHO

+

- (+)

CHf

+

CH2

+

ADCfDf54
CH2, {
CH3

2 Single Ended
and 1 Differential

3 P~eudo-Dlfferentlal

' 2 Differential

4 Single-Ended

+(-)

- (+)

- (+) ADC10154
+

ADCf Of 54

+(-)
CH3

CH3
VREF

-

+

TL/H/11225-20

FIGURE 3. Analog Input Multiplexer Options

2-324

~--------------------------------------------------------------,~

3.0 Applications Information (Continued)

capacitor will yield a typical noise floor of 200 nVrms/~.
The 2.5V reference output is referred to t~e negative supply
pin (V-). Therefore. the voltage at VREFOut will always
be 2.SV greater than the voltage applied to V-. Applying
this voltage to VREF+ with VREF- tied to V- will yield an
analog voltage span of 2.5V. In bipolar operation the voltage at VREFOut will be at -2.5V when V- is tied to -5V.
For the single-ended multiplexer mode the analog input voltage range will be from - 5V to - 2.5V. The pseudo-differential and differential multiplexer modes allow for more flexibility in the analog input voltage range since the "zero" reference voltage is set by the actual voltage applied to the assigned negative input pin. The drawback of using the internal reference in the bipolar mode is that any noise on the
-5V tied to the V- pin will affect the conversion result. The
bandgap reference is specified and tested in unipolar operation with V- tied to the system ground.

3.2 REFERENCE CONSIDERATIONS
The voltage difference between the VREF+ and VREF- inputs defines the analog input voltage span (the difference
between VIN(Max) and VIN(Min)) over which the 2 n (where n
is the programmed resolution) possible output codes apply.
In the pseudo-differential and differential modes the actual
voltage applied to VREF+ and VREF- can lie anywhere between the AV+ and V-. Only the difference voltage is of
importance. When using the single-ended multiplexer mode
the voltage at VREF- has a dual function. It simultaneously
determines the "zero" reference voltage and. with VREF+.
the analog voltage span.
The value of the voltage on the VREF+ or VREF- inputs
can be anywhere between AV+ + 50 mV and V- 50 mY. so long as VREF+ is greater than VREF-. The
ADC10154 and ADC10158 can be used in either ratio metric
applications or in systems requiring absolute accuracy. The
reference pins must be connected to a voltage source capable of driving the minimum reference input resistance of
4.5 kfi.
The internal 2.5V bandgap reference in the ADCl 0154 and
ADCl 0158 is available as an output on the VREFOut pin. To
ensure optimum performance this output needs to be bypassed to ground with 330 ",F aluminum electrolytic or tantalum capacitor. The reference output is unstable with capacitive loads greater than 100 pF and less than 100 ",F.
Any capacitive loads :5: 100 pF or 2100 ",F will not cause
the reference to oscillate. Lower output noise can be obtained by increasing the output capacitance. The 330 ",F

In a ratiometric system (Figure 4a). the analog input voltage
is proportional to the voltage used for the AID reference.
This voltage may also be the system power supply. so
VREF+ can also be tied to AV+. This technique relaxes the
stablity requirements of the system reference as the analog
input and AID reference move together maintaining the
same output code for a given input condition.
For absolute accuracy (Figure 4b). where the analog input
varies between very specific voltage limits. the reference pin
can be biased with a time- and temperature-stable voltage
source that has excellent initial accuracy. The LM4040 and
LM185 references are suitable for use with the ADC10154
and ADC10158.

+5V

.~

+5V

~
6800
Av+
CHO

_1\",7260
Av+
CHO

oV+

Dv+
VRErOUT

CHl

LM4040-4
ADC10154

CHl
Vm

CH2

+

TUH/ll22S-22

b. Absolute Using a 4.096V Span

TL/H/1122S-21

a_ Ratiometric Using the Internal Reference
FIGURE 4. Different Reference Configurations

2-325

c
o.....
o
.....
C1I

~
......

~

C

o
.....
o.....
C1I

CO

~
....
CI
....
g

~
....
CI
....
o
Q
III(

3.0 Applications Information (Continued)
The minimum value of VREF (VREF = VREF+ - VREF-)
can be quite small (see Typical Performance Characteristics) to allow direct conversion of transducer outputs providing less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system
error voltage sources when operating with a reduced span
due to the increased sensitivity of the converter (1 LSB
equals VREF/2n).
3.3 THE ANALOG INPUTS.
Due to the sampling nature of the analog inpu1s, at the clock
edges short duration spikes of ·currenf will be seen on the
selected assigned negative input. Input bypass capacitors
should not be used if the source resistance is greater than
1 kG since they will average the AC current and cause an
effective DC current to flow through the analog input source
resistance. An op amp RC active lowpass filter can provide
both impedance buffering and noise filtering should a high
impedance signal source be required. Bypass capacitors
may be used when the source impedance is very low without any degradation in performance..
In a true differential input stage, a signal that is common to
both "+" and "-" inputs is cancelled. For the ADC10154
and ADC1 0158, the positive input of a selected channel pair
is only sampled once before the start of a conversion during
the acquisition time (tAl. The negative input needs to be
stable during the complete conversion sequence because it
is sampled before each decision in the SAR sequence.
Therefore, any AC common-modE! signal present on the analog inputs will not be completely cancelled and will cause
some conversion errors. For a sinusoid common-mode signal this error is:

Verror(Max) = VPEAK (2'ITfCM)(tC)
where fCM is the frequency of the common-mode signal,
VPEAK is its peak voltage value, and tc is th·e AID's maximum conversion time (Ie = 22/fCLI< for 10-bit plus sign
resolution). For example, for a 60 Hz common-mode signal
to generate a 1f4 LSB error (1.24 mV) with a 4.5 /Ls conversion time, its peak value would have to be approximately
731 mV.

analog full-scale voltage range and then adjusting the VREF
voltage (VREF = VREF+ - VREF-) for a digital output
code changing from 011 1111 1110 to 011 1111 1111. In
bipolar signed operation this only adjusts the positive full
scale error. The negative full-scale error will be as specified
in the Electrical Characteristics after a positive full-scale adjustment.
.
3.4.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A plus input voltage which
equals this desired zero reference plus % LSB (where the
LSB is calculated for the desired analog span, using 1 LSB
= analog span/2 n, n being the programmed resolution) is
applied to selected plus input and the zero reference voltage at the corresponding minus input should then be adjusted to·just obtain the OOOHEX to 001 HEX code transition.
The full-scale adjustment should be made [with the proper
minus input voltage applied) by forcing a voltage to the plus
input which is given by:

VIN( + ) fs adj = VMAX - 1.5 [(VMAX 2~ VMIN)]
where VMAX equals the high end of the ananlog input range,
VMIN equals the low end (the offset zero) of the analog
range and n equals the programmed resolution. Both VMAX
and VMIN are ground referred. The VREF (VREF = VREF+
- VREF-) voltage is then adjusted to provide a code
change from 3FEHEX to 3FFHEX. Note, when using a pseudo-differential or differential multiplexer mode where VREF +
and VREF- are placed within the V+ and V- range, the
individual values of VREF+ and VREF- do not matter, only
: the difference sets the analog input voltage span. This completes the adjustment procedure.
3.5 INPUT SAMPLE-AND-HOLD
The ADC1 0154/8's sample/hold capacitor is implemented
in the capacitor array. After the channel address is loaded,
the array is switched to sample the selected positive analog
input. The rising edge of WR loads the multiplexer addressing information. The sampling period for the assigned positive input is maintained for the duration of the acquisition
time (tAl, i.e., approximately 6 to 8 clock cycles after the
rising edge of WR. .
An acquisition window of 6 clock cycles is available to allow
the voltage on the capacitor array to settle to the positive
analog input voltage. Any change in the analog voltage on a
selected positive input before or after the acquisition window will not effect the AID conversion result.
In the simplest case, the array's acquisition time is determined by the RON (9 kG) of the multiplexer switches, the
stray input capacitance CS1 (3.5 pF) and the total array (CLl
and stray (CS2) capacitance (CL + CS2 = 48 pF). For a
large source resistance the analog input can be modeled as
an RC network as shown in Figure 5. The values shown
yield an acquisition time of about 1.1 ,...S for 10-bit unipolar
or 10-bit plus sign bipolar accuracy with a zero-to-full-scale
change in the input voltage. External source resistance and
capacitance will lengthen the acquisition time and should be
accounted for. Slowing the clock will lengthen the acquisition time, thereby allowing a larger external source resistance.

3.4 OPTIONAL ADJUSTMENTS

3.4.1 Zero Error
The zero error of the AI D converter relates to the location
of the first riser of the transfer function (see Figure 1) and
can be measured by grounding the minus input and applying
a small magnitude positive or negative voltage to the plus
input. Zero error is the difference between actual DC input
voltage which is necessary to just cause an output digital
code transition from 000 0000 0000 to 000 0000 0001 (10bits plus sign) and the ideal % LSB value (% LSB = 2.44
mV for VREF = + 5.000V and 10-bit plus sign resolution).
The zero error of the AID does not require adjustment. If
the minimum analog input voltage value, VIN(Min), is not
ground, the effetive "zero" voltage can be adjusted to a
convenient value. The converter can be made to output an
all zeros digital code for this minimum input voltage by biasing any minus input to VIN(Min). This is useful for either the
differential or pseudo-differential input channel configurations.
3.4.2 Full-scale
The full-scale adjustment can be made by applying a differential input voltage which is 1% LSB down from the desired

2-326

~----------------------------------------------------~~

3.0 Applications Information

c
o....

(Continued)
SNR vs Input Frequency
70

'iii"
.:!!.

60

0

50

...'"en

40

I

30

......z

20

in

10

~

0
z

.sI
TLlH/11225-23

FIGURE 5. Analog Input Model
The curve "Signal to Noise Ratio vs. Output Frequency"
(Figure 6) gives an indication of the usable bandwidth of the
ADC10154/ADC10158. The signal-to-noise ratio of an ideal
AID is the ratio of the RMS value of the full scale input
signal amplitude to the value of the total error amplitude
(including noise) caused by the transfer function of the AID.
An ideal10-bit plus sign AID converter with a total unadjusted error of 0 LSB would have a signal-to-noise ratio of about
68 dB, which can be derived from the equation:
SIN = 6.02(n)

C>

10-BIt Ro..lull..

Id..1 to-BII

AID

10

100

1000

INPUT FREQUENCY (kHz)
TL/H/11225-24

FIGURE 6. ADC101541 ADC10158
Signal-to-Noise Ratio vs Input Frequency
The sample-and-hold error specifications are included in the
error and timing specifications of the AID. The hold step
and gain error sample/hold specs are included in the
ADC10154/ADC1015B's total unadjusted, linearity, gain
and offset error specifications, while the hold settling time is
included in the AID's maximum conversion time specification. The hold droop rate can be thought of as being zero
since an unlimited amount of time can pass between a conversion and the reading of data. The data is lost aiter a new
conversion has been completed.

2-327

~C

U1
CD

1

+ 1.8

U1

o
....
o
....

0

where SIN is in dB and n is the number of bits. Figure 2
shows the signal-to-noise ratio vs. input frequency of a typical ADC1 0154/ADC1 0158 with % LSB total unadjusted error. The dotted lines show signal-to-noise ratios for an ideal
(noiseless) 10-bit AID with 0 LSB error and an AID with a 1
LSB error.

o....

f8
.....
o
.....
o
c
cc
.....

3.0 Applications Information

(Continued)
Protecting the Analog Inputs

+5V

+5V

-=t

II)

.....
o
.....

>-....t-..... VIN

g

V+

V+

cc

Rl

R2

(AI

ADC10154
ADC10158"

R3

ADC10154
ADC101S8

+ A2)IIA3 ,;; Ik

TLlHf11225-25

Note'!: Diodes are IN914.
Note 2: The protection diodes should be able to withstand the output current of the op amp under current limit

Zer0-5hlft and Span-Adjust for Signed or Unsigned, Unipolar, Single-Ended
Multiplexer Assignment, Analog Input Range of, 2V :;;; V,N :;;; 4.5V
V+t-~t---.-----------------~

ADC10154
, ADC101S8
VREF -

lion

4.5VOC
VREF + t-~...----.-------...----.-----..
+

......-+_............ 1/201 LM611

+

1/2 01 LM611

.=I2,l'r

'I % resistors
TLlH/II225-26

2·328

~---------------------------------------------------------------------,>

c

o
.-

t(JNational Semiconductor

B
.-

;;;
c
o.-

ADC 1031/ ADC 1034lADC 1038 1O-Bit ,Serial
I/O A/D Converters with Analog Multiplexer
and Track/Hold Function,

cCo)

0l:Io
.....
>
c

General Description

Features

The ADC1031 , ADC1034 and ADC1038 are 10-bit successive approximation AID converters with serial I/O. The serial input, for the ADC1034 and ADC1038, controls a singleended analog multiplexer that selects one of 4 input channels (ADC1034) or one of 8 input channels (ADC1038). The
ADC1034 and ADC1038 serial output data can be configured into a left- or right-justified format.
An input track/hold is implemented by a capacitive reference ladder and sampled-data comparator. This allows the
analog input to vary during the AID conversion cycle.
Separate serial 110 and conversion clock inputs are provided to facilitate the interface to various microprocessors.

• Serial I/O (MICROWIRETM compatible)
• Separate asynchronous converter clock and serial data
110 clock
• Analog input track/hold function
• Ratlometric or absolute voltage referencing
• No zero or full scale adjustment required
• OV to SV analog input range with single SV power
supply
• TTL/MaS input/output compatible
• No missing codes

Key Specifications
•
•
•
•
•
•

Applications
•
•
•
•

Engine control
Process control
Instrumentation
Test equipment

10 bits
Resolution
±1 LSB (max)
Total unadjusted error
SV ±S%
Single supply
20mW (max)
Power dissipation
13.7 p.s (max)
Max. conversion time (fC = 3 MHz)
10 p.s (max)
Serial data exchange time (fs = 1 MHz)

Connection Diagrams,
Dual-In-Llne and 50 ~ackages
Sa.K- 1
2

cs-

V,N - 3
GND- 4

\J
ADCl031

1SI-Vee

iiE-l

8 r-Vee

Of

71-CcLK
61-00

cs

5I- VREF+

2
3

CHO

4

CH1-

5

ADC1034

'-"

DI- 1

15 r-CcLK
141- Sa.K

CHO:- 2
CHl- 3

13 r-SARS

CH2- 4

20
19

Vee

cs

18

CcLK
171-Sa.K
ADCl038' 16 r-iiE
15 SARS

121-00

CH3- 5

CH2- 6

CH4- 6

Top View

11I- VREF+

CH3- 7

10r-VREF-

CH5- 7

14

00

ADC1031 In NS Package N08E

DGND- 8

91-AGND

CH6- 8

13

vBEl

CH7- 9

12

VREF-

DGND- 10

11

AGND

TL/H/l0556-4

TLlH/l0556-3

Top View
TL/H/l0556-2

ADC1034In N5 Packages
JI6A, M16B or N16E

Top View
ADC1038 In NS Packages
J20A, M20B or N20A

Ordering Information'

r-------------~--~~._~~--__,

Industrial -40"C

s: TA s:

+85"C

Package

ADC1031CIN

NOSE

ADC1034CIN

N16E

ADC1034CIWM

M16B

ADC1038CIN

N20A

ADC1038CIWM

M20B

Military -55'C

s: TA s:

+ 125'C

Package

ADC1034CMJ

J16A

ADC103SCMJ

J20A

2-329

o
.cCo)

CD

Absolute Maximum Ratings (Notes 1 & 3)

Operating Ratings (Notes 2 & 3)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
' 6.5V
Supply Voltage (Vee>

Temperature 'Range

Voltage at Inputs and Outputs
Input Current at Any Pin (Note 4)
Package Input Current (Note 4)

ADC1031CIN,
ADC1034CIN,
ADC1034CIWM,
ADC1038CIN,
ADC1038CIWM,
ADC1034CMJ, ADC1038CMJ

.,..Q.3VtoVee +,0.3V
±5mA
±20mA

Package Dissipation
at TA = 25·C (Note 5)

Supply Voltage (Vee)
Reference Voltage
(VREF = VREF+ - VREF-)

500mW

ESD Susceptability (Note 6)
'Soldering Information
N Package (10 sec.)
J Package (10 sec.)
SO Package (Note 7): "
Vapor Phase (60 sec.)
Infrared (15 sec.)

2000V

TMIN ,s; TA ,s; TMAX
-40·C,s; TA,s; +85·C
,

-55·C,s; TA,s; +125·C
4.75 Voe to 5.25 Voc
2.0 Voe to Vee + O.05V

260·C
300"C
215·C
220·C

Storage Temperature

- 65·C to + 150·C

Electrical Characteristics

The following specifications apply for Vee = +5.0V, "REF = +4:6V, f8 = 700 kHz, and fe = 3 MHz unless otherwise
specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25·C.
SymbOl,

Parameter

"

Conditions

Typical
(Note 8)

Limit
(Note 9) ,

Units
(Limits)

CONVERTER AND MULTIPLEXER CHARACTERISTICS
, Total
Error

Un~dju~ted'

I

CIN, CIWM, CMJ

(Note 10)

±1

, LSB(max)

10

Bits (min)

5
11

kO
kO(min)
kO(max)

(Vee + 0.05)

V (max)

+ 0.05)

(GND - 0.05)

V (max)
V (min)

5.0

200
500

nA(max)
nA(max)

5.0

-200
-500

nA(max)
nA(max)

5.0

-200
-500

nA(max)
nA(max)

5.0

200
500

nA(max)
nA(max)

±1/4

LSB(max)

±1/4

LSB (max)

Differential Linearity
RREF

VREF
VIN

Reference Input Resistance

8

Reference Voltage
'Analog Input Voltage
On Channel Leakage Current

..

(Note 12)
Off Channel Leakage Current
(Note 12)
Power Supply
Sensitivity

I Zero Error
I Full Scale Error

(Vee

(I':-Iote 11)

= 5 Voe.
= 0 Voe
On Channel = 0 Voe.
Off Channel = 5 Voe
On Channel = 5 Voe.
Off Channel = 0 VOC
On Channel = 0 Voc,
Off Channel = 5 Voc
On Channel
Off Channel

4.75 Voe ,s; Vee ,s; 5.25 VOC

2·330

Electrical Characteristics

(Continued)
The following specifications apply for Vcc = +5.0V, VREF = +4.6V, fs = 700 kHz,and fc = 3 MHz unless,otherwise
specified. Boldface limits apply for T A = TJ = T MIN to T MAX; all other limits T A = TJ = 2S"C.

..
Symbol

Parameter

Conditions

Typical
(Note 8)

Umlt
(Note 9)

Units
(Umlts)

DIGITAL AND DC CHARACTERISTICS
VIN(l)

Logical "1" Input Voltage

Vcc = 5.25 Voc

2.0

V (min)

VIN(O)

Logical "0" Input Voltage

Vcc = 4.75 Voc

0 ••

V (max)

IIN(l)

Logical "1" Input Current

VIN = 5.0Voc

IIN(O)

Logical "0" Input Current

VIN = OVoc

VOUT(l)

Logical "1" Output Voltage

Vcc = 4.75 Voc
lOUT = -360 p.A
lOUT = -10 p.A

VOUT(O)

Logical "0" Output Voltage

lOUT

TRI-STATE Output Current

ISOURCE Output Source Current

0.005

2 ••

p.A (max)

-0.005

-2••

p.A (max)

2.4
4 ••

V (min)
V (min)

0.4

V (max)

Vcc = 4.75 Voc
lOUT = 1.6mA
VOUT = OV

-0.01

-3

p.A(max)

VOUT = 5V

0.Q1

3

p.A(max)

VOUT = OV

-14

-8••

mA(min)

ISINK

Output Sink Current

VOUT = Vcc

16

8.0

mA(min)

Icc

Supply Current

a:: =

1.5

3

mA(max)

0.7
4.0

3.0

MHz (min)
MHz (max)

HIGH,VREFOpen

AC CHARACTEf{ISTICS
fc
fs

Conversion Clock (CCLK)
Frequency
Serial Data Clock (ScLKl

fc = 3 MHz, R/[ = "O~'

183

Frequency (Note 13)

fc = 3 MHz, R/L = "1"

622

fC = 3 MHz, R/L = "0" or R/L = "1"

2

kHz (min)
kHz (min)

1.0

MHz (max)

Tc

Conversion Time

Not Including MUX Addressing and
Analog Input Sampling Times

41 (1/fC)
+ 200n.

(max)

teA

Analog Sampling TIme

After Address is Latched,CS = Low

4 •• (1/fs)
+ 200n.

(max)

tACC

Access Time Delay from CS or OE
Falling Edge to DO Data Valid

OE = "0"

100

200

ns(max)

tSET-UP

Set-up Time of
Falling
Edge to SCLK Rising Edge

75

150

ns(min)

tlH, toH

Delay from OE or
Rising
Edge to DO TRI-STATE

100

120

ns(max)

tHOI

01 Hold Time from SCLK Rising Edge

0

.0

ns(min)

ISOI

01 Set-up Time to SCLK Rising Edge

50

100

ns (min)

a::

a::

RL = 3 kn, CL = 100pF

2-331

fII

Electrical Characteristics

(Continued)
The following specifications apply for Vcc=
4.6V. fs = 700 kHz. and fc =
5.0V. VREF =
specified. Boldface limits apply for ,TA = T J =, T MIN to T MAX; all other limits T A = T J = 25·,C.

+

+

' Parameter

Symbol

Conditions

3 MHz unless otherwise

Typical
(NoteS)

Limit
(Note

9)

Units
(Limits) ,

AC CHARACTERISTICS (Continued)
tHOO

DO Hold Time from SCLK Falling Edge

RL = 30 kO. CL = 100 pF

tO~~

Delay from SCLK Falling

RL = 30 kO. CL = 100 pF

Edge to DO Data Valid
tROO

DO Rise Time

,

RL = 30kO.
CL = 100 pF

tFOO

' DO Fall Time

RL = 30kO.
CL ,= 100 pF

CIN

Input Capacitance

70

10

ns(min)

150

250

ns(max)
ns(max)

'35

75

Low'toHigh

75

150

ns(max)

TRI-STATE to Low

35

75

ns(max)

High to Low

75

150

ns(max)

TRI-STATE to High

Analog Inputs (CHO-CH7)

50

pF

All Other Inputs

7.5

pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device Is functional, but do not guarantee specific performance limits. For guaranteed speCifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
: may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respeCt to AGND and DGND, unless otherwise specified.
Note 4: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < DGND, or VIN > Vec) the current at that pin should be limited to 5 rnA. The
20 ~A maximum package input current rating limits the number. of pins that can safely exceed the power supplies with an input current o( 5 rnA to four pins.
Note 5: The maximum power diSSipation must be derated at elevated temperatures and is dictated by TJmax, 6JA and the ambient lemperature, TA, The maximum
allowable power dissipation at any temperature is Po = (TJmax - TfoJI6JA or the number given in the Absolute, Maximum Ratings, whichever is lower. For this
device, TJmax = 125"C. The Iypicaltherrnal resistance (6JA) of these paris when board mounted follow: ADCI031 with CIN suffixes 7I'C/W, ADCI034 with CMJ
suffixes 52'C/W, ADCI034 with CIN suffixes 54'C/W, ADCI034 with CIWM suffixes 70'C/W, ADCI038 with CMJ suffixes 5'.r'C/W, ADCI038 with CIN suffixes
46'C/W, ADC1038 with CIWM suffixes 64'C/W.
~ote

6: Human body model, 100 pF capacitor discharged through a 1.5 kO resistor.

Note 7: See AN450 "Surlace Mounting Methods and Their Effect on Product Reliability" or LinBBr Databook section "Surlace Mount" for other methods of
soldering surface mount devices.
Note 8: Typicals are ai TJ

= 25'C and represent most likely par~metric norm.

Note 9: Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 10: Total unadjusted error Includes offset, full-scale, linearity, multiplexer, and hold step errors.
Note 11: Two on'Chlp diodes are tied to ~ach analog input. They will forward,conduct for analog input voltages one diode drop below ground or one diode drop
greater than Vee supply. Be, careiul during testing at low Vee levels (4.5V), as high level analog inputs (5V) can'cause an input diode to conduct, especially at
elevated temperatures, which will cause errors for analog Inputs near full-scale. The spec allows 50 mV forward bias of either diode; this means that as long as the
analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. Exceeding this range on an unselected channel will corrupt the
reading of a selected channel. To achieve an absolute 0 Vee to 5 Vee input voltage range will therefore require a minimum supply voltage of 4.950 Vee over
temperature variations, initial tolerance and loading.
Note 12: Channel leakage current Is measured after the channel selection.
Note 13: In order to synchronize the serial data exchange properly, SARS needs to go low after completion of the serial 110 data exchange. If this does not occur
lI)e output shift register will be reset and the correct output data lost. The minimum limit for SeLK will depend on CcLK frequency and whether right-justified or leftjustlfled, and can be determined by the following equations:
fS> (8.5/41)(fc) with right-justification (R/L = "I") and fS > (2.5/41) (fc) with left-iustificatlon (R/L = "0").

"

2-332

r--------------------------------------------------------------------,~

Typical Performance Characteristics
Power Supply Current
(Icc) VB CCLK

Power Supply Current (Icc)

Reference Current (IREF)
vs Ambient Temperature

VB Ambient Temperature

vee = v RFF = +5V
VRU- = AGND

]: 1.0 CcLl( = 3.0 MHz H-+-t--t--l

15
~

T""R

~

~ lD~V-R~U~+~=~4-V++-~Vee~=~4~3~5V~
0.5 1-+++-H1I++l--H-Hi++Hl

~ o.s

...

0.0 L-..l-L..L.JWJ.U-...J.....I...l..J.J..l.W

lOOk

30CIc

1M

311

10M

Ca.K = 3.0 MHz
Sa.!( = 700 kHz

~

0.75

I

I

0~~...J....~~~~-L~

-60-40-20 0 20 40 60 BD 100120140

AMBIENT TEMPERAlURE ("1:)

AMBIENT TEMPERAlURE ("1:)

Linearity Error vs
Ambient Temperature

Vee = VRrF+ = +5V
VRU- = AGND

vee = vRFF+ = +5V
VRU- = AGND

Scu! = 700 kHz -+t+t+tH!
TA = 25"1:

0.50

I D.251=-~+H+!#-~~

§"2.0

a

;;
g....
o
~

Linearity. Error VB
Reference Voltage
lDr-~---~~~--'

Reference Voltagl=V REF+ - VREF'-

'§'

Ccuc = 3.0 MHz
SCIJ( = 700kHz

o.a

:!!.

:!!.
«

15~~-T-r-+-r++~

~

lD~~-+-r-r++_+-~

;

o.s~~~~~~~

a

~ 05~~=4=+=+:t:t~~
m0.25 H-+-++-+-I-I-+-+-l

-liO-.IO-2O 0 20 <10 60 60100 1201<10

Linearity Error VB
CCLK Frequency

~....
0100

"

o~~----~~~...J....~

Ca.K FREQUENCY (Hz)

:!!.

rI

VRu-=AGNO

Scu! = 700 kHz
0.75

g
....
a....

«

a

Ill>

1--+--+--+
I

1\

TA = 25"C

Vee

= S.OV

Ca.!( = 3.0MHz
Sell( = 700kHz

\

I : I--l--+-~-I---l--l

1o~~~~~~~~~

lOOk

30CIc

1.1111

:tOM

-60 -.10-20 0 20 40 60 60 100 120 1<10

10M

1

2

3

4

RUERENCE VOLTAGE (V)

AMBIENT TEMPERAlURE ("1:)

Ca.K FREQUENCY (Hz)

Zero Error VB
Reference Voltage
O'S~R.-M-~n-c.-v-o~~·-g.-=-VRFF~+--V-RFF~­
~

D.4

~

I

:!!. 0.3 1--+-\\-+«

a
~

TA =25"C

f----1l-\-+--+Ca.!(vee= 3.0= 5.DV
MHz

•

Sa.!( = 700 kHz

D.2

0.1
0
0

1

2

3

4

5

REFERENCE VOLTAGE (V)
TL/H110556-5

2·333

~ r-----------------------------------------------------------------------------~

a..-

g

Test Circuits

i

~..-

5.OV

~~

~

.Leakage Current

DO except "TRI-STATE"

tlH, toH
TEST POINT

5V
Uk

CHO(ON)

...ADC_l_0_38_00
.....

YM07000
or Equlwllonl

C")

CHI (OFF)

o
..-

~

C~2(OFF)

TL/H/l0556-6
TL/H/l0556-7

.

CH7(OFF)

Channel
select
TL/H/l0556-8

Timing Diagrams· :
DO High to Low State

DO Low to High State

_:::~II_ t FOO

~

DO "TRI-STATE" Rise
and Fall Times

RDO

2.4V~

2.4V
O.4V

TLlH/lOS56-9

TLlH110556-10

00 1.2V -

TRI-STATE

tFDO
TL/H/l0556-11

DO Data Output Timing

DI Data Input Timing

SCLK~

~~
DI

TL/H/l0556-12

TL/H/l0556-13

2-334

~

Timing Diagrams (Continued)

r +-..

ADC1031 CS High during Conversion

Conversion Time
41 Ce

S Analog
II
TI
amp ng me

CeLl( continuously

leA =4.5

enabled

SCLK

o
-.
o
w
-.
.....

---l

g

..
-.
o

LK.

w

IS

\~--~--------~/

.....
:aD
o-.

B
CD

DO

r
Scuc

cs

-r

TL/H/l0556-14

ADC1038/ADC1034 CS High during Conversion

boc.~~I~~ = "0" In cyclo N-l)
--1 Sam~~I:~nm' L
I leA =
I

(00 I,II-Justilled

b~:~..N:~ = "I" In cyclo ·N)
--1 sem::~~m. L
I leA =
I

4.5 SaJ(

1234567891

I

4.5 SCLK

1

12345618911

--'r!
r!

l&..._ _ _ _ _

0[1

(00 righl-Iustlfl,d

Ul

'--__________________
~____________~------~r~
~r~

01

6 Leading Zeroes

00
Result of Conversion N-1

Result of Conversion N

~~ ----------------------~~~~----------------------~

Convenlon 11m.

41~

41~

(Conversion must complete after DO Is clocked out)

(Conversion must complete after DO Is clocked out)
TL/H110556-1S

CcLK continuously enabled

2-335

Timing Diagrams (Continued)

rl

Cycle N

(00 Ioft-JUIIIfIed, boClu..

•

.

a L~W

,Anllognme
Sampling

I.'

~

,ADC1038'-rADC1034 ContlnuOUSIYeyCIe N+I

r

R/L' = "O"'n cycle N-I)

leA = 4.5 Scuc

~

,

r

(00 righi-Justified bocau..

'

,',

-1

Analognm.
Sampling

R/ii ,= ",I" ,In ~yc'. N),
'

leA =,4.5 Scu<,

.

Scuc

I--

csl
iiEl

!I

!I--

rl--

II

01

,

00

~ 6 leiding ;...;..

HoIUR 01 eon..",,,, N-l
SAlIS

I!---'-,

Convo~~nme

--------------~

I~

__________________

~

eonvorslonnme

41~

4"~

(ConvInIon mull 'campltlt aRt, 00 b clocked out)

(eon_Ion mull ....p1t\. IRt, 00 Is clack.d out)
'. TLlH/l0556-16

CcLK continuously ensbled

Multiplexer Address/Channel Assignment Tables
ADC1038 '
MUXAddre88
A2

A1

AO

0

0
0

0

1
'1

0

0
0

0

1
1

0

ADC1034

.

MlJ~ Address

Analog
Channel
Selected

A2

A1

·AO,

X
X
X
X

,0
0

0

CHO

1

• _. C?1-i1

1
1

0

CH2
CH3

,
"

0
0
0
1
1
1
1

1
1
1
1

CHO
CH1
CH2
CH3
CH4
CH5
CH6
CH7

Nota: "X" = don't care

2~336

Analog
Channel
Selected

1

,

»
c
0

......

lr\

CCLK

rl

~ 4
Reset

I

+4
Reset

I

0

Vee

I

I

DGND

I

n-

SCLK

cs -~
DI

RIC

rD=

AD
Address
BH 3

Al
Address
BH 2

A2
Address
BH 1

Q

R

R

R

Q

1 I
RJ

1

Q

lJ
CHO
CHl
CH2
CH3
CH4
CH5
CH6
CH7

ANALOG
INPUT
MULTIPLEXER

~

m
0'

.

Q

~

~
I~

CLK

J
L

VRu+ VREt

I--

~~:
". r- "'''''' ~
CS·OE

load
PARALLEL LOAD
16 BIT SHIFT REGISTER

FORMAT
SELECT

~ DO

Ql0 f-

r-- CLK

I

~

D)

Reset

1LJ

~cs

I

c.a
3

0

L
DAC

iii"

SARS

SUCCESSIVE APPROXIMATION REGISTER

[}/

AGND

n
="
C

-[>0--[>0- ~

EOC

--f-f-f-f-f-f-f-

:s

1

I

ADDRESS DECODER
Co)

:s

0"

C CLOCK DELAY for
ACQUISITION
R
(4.5 SCLK)

0
R

'....."

""

C

n

?

'"

Co)

Q)

SCLK

OE
TLlH/l0556-17

8eo~~av l"eOl~av I~&o~~av

II

CD

B
..-

r-------------------------------------------------------------------------------------,
1.0 Pin Descriptions

~

CCLK'

..-

The clock applied to this input controls the successive approximation conversion time interval.
The clock frequency applied to this input can be
between 700 kHz and 4 MHz.

ScLK

The serial data clock input. The clock applied to
this input controls the rate at which the serial
data ,exchange occurs a(ld the analog sampling
time available to acquire an analog input voltage.
The rising edge loads the information on the 01
pin into the multiplexer address shift register (address register). This address controls which
channel of the analog input multiplexer (MUX) is
selected.

i

~

sg
..c(

VREF+

The positive analog voltage reference for the analog inputs. In order to maintain accuracy the
voltage range of VREF (VREF = VREF+ VREF-) is 2.5 VOC to 5.0 Voc and the voltage at
VREF+ cannot exceed Vee + 50 mV. In the
AOC1031 VREF- is always GNO.

,VREF:

The negative voltage, reference for the analog inputs. In order to maintain accuracy the voltage at
this pin must not go below O!3NO and AGNO by
more than 50 mV or exceed 4P% of VCC (for Vee
= 5V, VREF- (max) = 2V). In the AOC1031
VREF- is internally connected to the GNO pin.

VCC

The power supply pin. The operating voltage
range of VCC is 4.75 VOC to 5.25 VOC. Vcc
should be bypassed with 10 /LF and 0.1 /LF capacitors to digital ground for proper operation of
the AlO converter.

OGNO,
AGNO

The digital and' analog ground pins for the
AOC1034 and the AOC1038. In order to maintain
accuracy the voltage difference between these
two pins must not exceed 300 mV.

GNO

The digital and ,analog ground pin for the
AOC1031.
'

The falling edge shifts the t!ata resulting from the
previous AlO conversion out on 00. CS and OE
enable or disable the above functions.
01

The serial data Input pin; The data applied to this
pin is shifted by ScLK into the multiplexer address register. The first 3 bits of data (AO-A2)
are the MUX channel address (see the Multiplexer Address/Channel Assignment tables). The
fourth bit (R/L) determines the data format of the
conversion result in the conversion to be started.
When R/L is low the output data format is leftjustified; when high it is right-justified. When right- .
justified, six leading "O"s are output on 00 before the MSB information; thus the complete conversion result' is shifted out in 16 clock periods.

00

The data output pin. The AlO conversion result
(00-09).Is output on this pin. This result can be
left- or right-justified depending on the value of
R/L bit shifted in on 01.

SARS

This pin is an output and indicates the status of
the internal successive approximation register
(SAR). When high, it signals that the A/O conversion is in progress . .This pin is set high after the
analog 'input sampling time (tCA) and remains
high'for 41 CcLK periods. When SARS goes low,
the output shift register haS been loaded with the
cOnversion result and another AlO conversion
'
sequence can be started.
The chip select pin. When a low is applied to this
pin, the rising edge of SCLK shifts the data on 01
into the address register. In the AOC1031 this pin
alSo functions as the OE pin.

OE

The output enable pin. When OE and CS are
both low the falling edge of SCLK shifts out the
previous AlO conversion data on the 00 pin.

CHOCH7

Tl'!e analog inputs of the MUX. A channel input is
selected by the address information at the 01 pin,
which is loaded on the rising edge of SCLK into
the address register.
Source impedances (Rs) driving these inputs
should be kept below 1 kO. If Rs is greater than
1 kO, the sampled data comparator will not have
enough time to acquire the c9rrect value ofthe
applied input voltage.
'

2.0 Functional Description
2.1 DIGITAL INTERFACE
The ADC1034 and AOC1038 implement their serial interface via seven digital control lines. There are two clock inputs for the ADC1034/ADC1038. The SCLK controls the
rate at which the serial data exchange occurs and the duration of the analog sampling,time window. The CcLK controls
the conversion time and must be continuously enabled. A
low on CS enables the, rising edge of SCLK to shift in the
serial multiplexer addressing data on the 01 pin. The first
three bi~ of this data select the analog input channel for the
AOC1038 and the AOC1034 (see the Channel Addressing
Tables). The following bit, R/L, selects the output data format(right-justified or left-justified) for the conversion to be
started. With CS and OE low the 00 pin is active (out of
TJ;lI-STATE) and the falliligedge of SCLK shifts out the data
from the previous analog conversion. When the first conversion is started the data shifted out on 00 is erroneous as it
depends on the state of the Parallel Load 16-Bit Shift Register on power up, whiqh is unpredictable.
The ADC1031 implements its serial interface with only four
control pins since it has only one analog input and comes in
an eight pin mini-dip package. The SCLI<', CCLK, CS and 00
pins are available for the serial interface. The output data
format eannot be selected and ,defaults to a left-justified
format. The state of 00 is controlled by CS only.
2.2 OUTPUT DATA FORMAT
When R/L is low the output data format is left-justified;
when high it is right-justified. When right-justified, six leading
"O"s are output on DO before the MSB, and the complete
conversion result is shifted out in 16 clock periods.
2.3.0 CS HIGH DURING CONVERSION

The voltage applied to these inputs should not
exceed Vee or go below OGNO or AGNO by
more than 50 mV. Exceeding this range on an
unselected channel will corrupt the reading of a
selected channel.

With a continuous SCLK input, CS must be used to synchronize the serial data exchange. A valid CS is recognized if it
occurs at least 100 ns (!sET-UP) before the rising edge of
SCLK, thus causing data to be input on 01. If this does not

2-338

An acquisition window of 4.5 SCLK cycles is available to
allow the ladder capacitance to settle to the analog input
voltage. Any change in the analog voltage before or after
the acquisition window will not effect the A/D conversion
result.

2.0 Functional Description (Continued)
occur there will be an uncertainty as to which SCLK rising
edge,will clock in the first bit of data. CS must remain low
during the complete I/O exchange. Also, DE needs to be
low if data from the previous conversion needs to be accessed.

In the most simple case, the ladder's acquisition time is determined by the Ron (9 k!l) of the multiplexer switches, the
CSt (3.5 pF) and the total ladder (CLl and stray (CS2) capacitance (48 pF). For large source resistance the analog input
can be modeled as an RC network as shown in Figure 1.
The values shown yield an acquisition time of about 3 /Ls for
10 bit accuracy with a zero to a full scale change in the
reading. External source resistance and capacitance will
lengthen the acquisition time and should be accounted for.

2.3.1 CS LOW CONTINUOUSLY
Another way to accomplish synchronous serial communication is to tie CS low continuously and use SARS and SCLK to
synchronize the serial data exchange. SCLK can be disabled
low during the conversion time and enabled after SARS
goes low. With CS low during the conversion time a zero will
remain on DO until the conversion is completed. Once the
conversion is complete, the falling edge of SARS will shift
out on DO the MSB before SCLK is enabled. This MSB
would be a leading zero if right-justified or 09 if left-justified.
The rest of the data will be shifted out once SCLK is enabled
as discussed previously. If CS goes high during the conversion sequence DO is put into TRI-STATE, and the conversion result is not affected so long as CS remains high until
the end of the conversion.

g
....

S
....
);
C
o
....

S

~
c

....o

«:)
Co)

CD

The curve "Signal to Noise Ratio vs Output Frequency"
(Figure 2) gives an indication of the usable bandwidth of the
ADC1031/ADC1034/ADC1038. The signal to noise ratio of
an ideal AID is the ratio of the RMS value of the full scale
input signal amplitude to the value of the total error amplitude (including noise) caused by the transfer function of the
AID. An ideal 10 bit AID converter with a total unadjusted
error' of 0 LSB would have a signal to noise ratio of about
62 dB, which can be derived from the equation:

2.4 TYING SCLK and CCLK TOGETHER

SIN = 6.02(N)

SCLK and CCLK can be tied together. The total conversion
time will increase because the maximum clock frequency is
now 1 MHz. The timh1g diagrams and the serial I/O exchange time (10 SCLK cycles) remain the same, but the conversion time (TC = 41 CCLK cycles) lengthens from a minimum of 14 /Ls to a minimum of 41 /Ls. In the case where CS
is low continuously, since the applied clock cannot be disabled,' SARS must be used to synchronize the data output
on DO and initiate a new conversion. The falling edge of
SARS sends the MSB information out on DO. The next rising edge of the clock shifts in MUX address bit A2 on 01.
The following clock falling edge will clock the next data bit
of information out on DO. A conversion will be started after
MUX addressing information has been loaded in (3 more
clocks) and the analog sampling time (4.5 clocks) has
elapsed. The ADC1031 does not have SARS. Therefore, CS
cannot be left low continuously on the ADC1031.

+ 1.8

where SIN is in dB and N is the number of bits. Figure 2
shows the signal to noise ratio vs. input frequency of a typical ADC1031/4/8 with Ya LSB total unadjusted error. The
dotted lines show signal-to-noise ratios for an ideal (noiseless) 10 bit AID with 0 LSB error and an AID with a 1 LSB
error.
The sample-and-hold error specifications are included in the
error and timing specifications of the AID. The hold step
and gain error sample/hold specs are taken into account in
the ADC1031/4/8's total unadjusted error specification,
while the hold settling time is included in the AID's maximum conversion time specification. The hold droop rate can
be thought of as being zero since an unlimited amount of
time can pass between a conversion and the reading of
data. However, once the data is read it is lost and another
conversion is started.

3.2 INPUT FILTERING

3.0 Analog Considerations

Due to the sampling nature of the analog input, transients
will appear on the input pins. They are caused by the ladder
capacitance and internal stray capacitan'ce charging current
flowing into VIN. These transients will not degrade the AID's
performance if they settle out within the sampling window.
This will occur if external source resistance is kept to a minimum.

3.1 THE INPUT SAMPLE AND HOLD
The ADC1031/4/8's sample/hold capacitor is implemented
in its capacitive ladder structure. After the channel address
is received, the ladder is switched to sample the proper analog input. This sampling mode is maintained for. 4.5 SCLK
cycles after the multiplexer addressing information is loaded
in. For the ADC1031 14/8, the sampling of the analog input
starts on SCLK'S 4th rising edge.

V Ideal 10 Bit AID
'iii" 60 ··....:···:i"···.-I:··:I····· ••••••••
~

l1!

40

g
Ii2

Vee VREr+ = +5V
\
30 VREr
AGND, -+-j---:t,J--I
Ie = 700kHz
20 IS = 311HZ

....I

~

TUH/10558-18

\ to Bft

AID with ilLSBJ\

Talal Unadjusted Error 1\

=

=

RS
TA

= 504

=250C
2k

FIGURE 1. Analog Input Model

....

50

""

.\: ••••

:-r...-LI
~

o
~

4k

I"+---1-+--+-1
6k

8k 10k 12k

INPUT FREQUENCY (Hz)

TUH/10558-19

FIGURE 2. ADC1031/4/8 SIgnal to

No... R.1Io velnput Frequency
2-339

fII

3.0 Analog Considerations (Continued)'
Power Supply as Reference

External Reference 2.5V Full Scale

Input Not Referred to GND

,

CHO-CH7

VIN (+)

VIN~-)
Uk

AGND
AGND
VREf+

5V

Lt.t385-2.5
VREf-

Lt.t385-2.5
VIN (-) - - -....--1 vREF-

TL/H/l0556-20
TL/H/l0556-21

TL/H/l0556-22

'Current, path must ',still exist Irom VrN(-) io
ground

.

FIGURE 3. Analog Input Options
ment also facilitates ratio metric operation and in many
cases the chip power supply can be used for transducer
power as well as the VREF source.

3.3 REFERENCE AND INPUT
The two VREF inputs of the ADC1031 14/8 are fully differential and define t,he zero to full-scale input range of the A to 0
converter. This allows the designer to easily vary the span
of the analog input since this range will be equivalent to the
voltage difference between VREF+ and VREF-' By reducing VREF (VREF = VREF+ - VREF-) to less ,than 5V, the
sensitivity of the converter can be increased (i.e., if VREF ,=
2V then 1 LSB = 1.95 mY). The input/reference arrange-

This reference flexibility lets the inp'ut span not only be varied but 'also o,ffset from zero. The voltage at VREF - sets the
input level which produces a 'digital output of all zeros.
Though VIN is not itself differential, the reference design
allows nearly differential-input capability for .many measurement applications. Figure 3 shows some of the configura'
tions that are possible.
The ADC1031 has no VREF- pin. VREF- is internally tied to
GND.

Power Supply Bypassing
VIN '

=---.....,

="---.....,

Vee ...

VCC ...

ADC1034

ADC1034

r---~'" VREF+

r-===:::j:==-1 VREf+
,......;=~,.VREf-

;::;::::::::..~ AGND
SIGNAL GND
~

_ _~DGND

POWER GND
TL/H/l0556-23

~_,...-~DGND

TL/H/l0556-24

2-340

Protecting the Analog Inputs
+5V

+5V
+15V

>-...-8.........-----R Vill

Rl

R2

Vee

>-Wlr-....-¥I""""-t Y,N Vee

ADC1031
ADC1034
ADC1038

ADCl031
Alicl034
ADCl038

R3

TLlH/l0556-26

Diodes are IN914

(Rl ~ R2)//R3::S1k
TL/H/lD556-25

Zer~hlft

and Span-Adjust (2V

s: V,N s: 4.5V)

Vee
Y,N
ADC1034
ADC1038

.E0J.l~.IJ.1F
4.5 Voc

VREF-

VREF+

5 VOC:t5%

+

lJ.1~20k

ZERO
ADJ
1/2 of LM611

2 Voc
lOOk

10k

16k

+

'1 % resistors

2-341

TLlH/l0556-27

tt/National Semiconductor

ADC10731/ ADC10732/ ADC1 0734/ ADC10738
10-Bit Plus Sign Serial I/O A/D Converters
with Mux, Sample/Hold and Reference
General Description

Features

This series of CMOS 10-bit plus sign successive approximation AID converters features versatile analog input multiplexers, sample/hold and a 2.5V band-gap reference. The
1-, 2-, 4-, or 8-channel multiplexers can be software configured for single-ended or differential mode of operation.

• OV to 5V analog input range with single 5V power
. supply
• Serial I/O (MICROWIRE compatible)
• 1-, 2-, 4-, or 8-channel differential or single-ended
multiplexer
• Software or hardware power down
• Analog input sample/hold function
• Ratiometric or absolute voltage referencing
• No zero or full scale adjustment required
• No missing codes over temperature
• TIL/CMOS input/output compatible
• Standard DIP and SO packages

An input sample/hold is implemented by a capacitive reference ladder and sampled-data comparator. This allows the
analog input to vary during the AID conversion cycle.
In the differential mode, valid outputs are obtained even
when the negative inputs are greater than the positive because of the 10-bit plus sign output data format.
The serial I/O is configured to comply with the NSC
MICROWIRETM serial data exchange standard for easy interface to the COPSTM and HPCTM families of controllers,
and can easily interface with standard shift registers and
microprocessors.

Applications
• Medical instruments
• Portable and remote instrumentation

Key Specifications
10 bits plus sign
5V
37 mW (Max)
18 p.W
5 p's (Max)
74 kHz (Max)
2.5V ± 2% (Max)

• Resolution
• Single supply
• Power dissipation
- I·n powerdown mode
. • Conversion time
• Sampling rate
• Band-gap reference

• Test equipment

ADC10738 Simplified Block Diagram
eLK
"

cs

PO

SARS

".

00

,"

01

CHO
CHI
CH2
CH3
CH4
CH5
CH6
CH7

COW
AV+
AGND
VREr +

OUTPUT
SHIrT
REGISTER

VREr VRErOUT
OV+
DGNO

TL/H111390-1

2-342

r--------------------------------------------------------------------,~

C

Connection Diagrams for Dual-In-Line and SO Packages
AV+

16

DV+

o....

AV+

20
19

cs

2

15

VREFOUT

CHO

(+)

3

14

CLK

CHI

Cs

SARS

CH2

DI

DO

CH3

ClK

(-)
N.C.
PD

VREF -

N.C.

SARS

VREF +

COM

DO

N.C.

AGND

Top View

~o

VREFOUT

DGND

TL/H/11390-2

....~

DV+

PD

VREF -

DGND

VREF +

N.C.

AGND

....

!13

~....
o

~
w

See NS Package Number N16E or M16B

TLlH/11390-4

Top View

See NS Package Number N20A or M20B

~C
o
....
~

W

01»
DV+

AV+

CHO

2

VREFOUT

CHO

VREFOUT

CHI

3

Cs

CHI

cs

N.C.

4

01

CH2

01

N.C.

5

CLK

CH3

ClK

AV+

DV+

N.C.

6

SARS

CH4

SARS

COM

7

DO

CH5

DO

PD

8

VREF -

CH6

VREF -

VREF +

CH7

VREF +

AGND

COM

DGND
N.C.

10

11

TUH/11390-3

Top View

AGND

PO

N.C.

OGNO

N.C.

See NS Package Number N20A or M20B

TL/H/11390-5

Top View

See NS Package Number N24A or M24B
Connection Diagram for the SSOP Package

Ordering Information
DV+
AV+

2

CHO

20

VREFOUT

19

Cs
OJ

CHI

4

CLK

CH2

5

SARS

CH3

6

N.C.

7

COM

8

VREF +

PO

9

N.C.

10

AGNO

OGNO

ADC10734

DO
VREF -

TL/H/11390-34

See NS Package Number MSA20

2-343

Industrial Temperature Range
-40'C"; TA"; +85"C

Package

ADC10731CIN
ADC10731CIWM
ADC10732CIN
ADC10732CIWM
ADC10734CIMSA
ADC10734CIN
ADC10734CIWM
ADC10738CIN
ADC10738CIWM

N16E
M16B
N20A
M20B
MSA20
N20A
M20B
N24A
M24B

•

Absolute Maximum Ratings

(Notes 1 & 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors ',or availability and speclflcaUons.
SupplyVoltage(V+ = AV+ = DV+) ,
6.5V
6.5V
Total Reference Voltage (VREF+ -VREF"")
V+ + 0.3Vto -0.3V
Voltage at Inputs and Outputs
Input Current at Any Pin (Note 4)
30mA
Package Input Current (Note 4)
120mA
Package Dissipation at TA = 25·C (Note,5)
500mW
ESD Susceptability (Note 6)
Human Body Model
2500V
Machine Model
150V
Soldering Information
N packages (10 seconds)
260·C
SO Package (Note 7)
Vapor Phase (60 seconds)',
215·C
Infrared (15 seconds)
220"C
-40·Cto + 150"C
Storage Temperature

Operating Ratings (Notes 2 and 3)
Operating Temperature Range
TMIN s: TA s: TMAX
ADC10731CIN, ADC10731CIWM,
ADC10732CIN, ADC10732CIWM,
ADC10734CIN, ADC10734CIWM,
ADC10734CIMSA, ADC10738CIN,
ADC10738CIWM
- 40"C s: TA s: + 85·C
SupplyVoltage(V+ ~ AV+ = DV+)
+4.5Vto +5.5V
AV+ ;: 50 mV to -50 mV
VREF+
AV+ +50inVto -50mV
VREF+0.5VtoV+
VREF (VREF+-VREF-)

Electrical Characteristics

The following specificationsapplyforV+ = AV+ = DV+ = +5.0Voc, VREF+ = 2.5 Vee, VREF- = GND, VIN- = 2.5Vfor
Signed Characteristics, VIN- = GND for Unsigned Characteristics and fClK = 2.5 MHz unless otherwise specified. Boldface
limits apply for TA = TJ = TIlIN to TIIA](; all other limits TA = TJ = + 25·C. (Notes 8, 9 and 10)
Symbol

Conditions

Parameter

.

SIGNED STATIC CONVERTER CHARACTERISTICS

Typical
(Note 11)"

,1;."

Units
(Um"s)

10 + Slln

Bits

±2.0

LSB(max)

±1.2S

LSB(max)

Positive and Negative
Full-Scale Error

±1.S

LSB(max)

Offset Error

±1.S

LSB(max)

±0.2
±0.2
±0.1

±1.0
±1.0
;!:0.7S

LSB(max)
LSB(max)
LSB(max)

±0.1

±0.33

LSB(max)

Resolution with No Missing Codes

.,' .
:" .. '

Umlts
,(Note 12)

TUE

Total Unadjusted Error (Note 13)

INL

Positive and Negative Integral
Linearity Error

"Power Supply Sensitivity
Offset Error
+ Full-Scale Error
- Full-Scale Error

V+

DC Common Mode Error (Note 14)

= +5.0V ±10%

VIN+ = VIN- = VINwhere' '
5.0V ~ VIN ~ OV

Multiplexer Channel to
Channel Matching

±0.1

LSB

,
.,.,

"
I

"

2-344

l>
C

Electrical Characteristics (Continued)
The following specifications apply for V+ = AV+ = DV+ = +5.0 VOC, VREF+ = 2.5 Voc, VREF- = GND, VIN- = 2.5V for
Signed Characteristics, VIN- = GND for Unsigned Characteristics and fClK = 2.5 MHz unless otherwise specified. Boldface
limits apply for TA = T J = TMIN to TMAX; all other limits T A = T J = + 25~C. (Notes 8, 9 and 10) (Continued)
Symbol

Parameter

"

Conditions

Typical
(Note 11)

Limits
(Note 12)

Units
(Limits)

10

Bits

UNSIGNED STATIC CONVERTER CHARACTERISTICS

o....
o
.....

....

Co)

);
C

o
o
.....

....

TUE

Total Unadjusted Error (Note 13)

VREF+ = 4.096V

±0.75

LSB

~
l>

INL

Integral Linearity Error

VREF+

=

±0.50

LSB

o
....

Full-Scale Error

VREF+ = 4.096V

±1.25

LSB(max)

Offset Error

VREF+ = 4.096V

±1.25

LSB(max)

Resolution with No Missing Codes

Power Supply Sensitivity
Offset Error
Full-Scale Error

4.096V

V+ = +5.0V ±10%
VREF+ = 4.096V

±0.1
±0.1

LSB
LSB

DC Common Mode Error (Note 14)

VIN+ = VIN- = VIN
where + 5.0V :
C

o
....

~
Co)
co

DYNAMIC SIGNED CONVERTER CHARACTERISTICS

S/(N+D)

Signal-to-Noise Plus Distortion Ratio

VIN = 4.85 Vpp,
and fiN = 1 kHz to 15 kHz

67

dB

ENOB

Effective Number of Bits

VIN = 4.85 Vpp,
and fiN = 1 kHz to 15 kHz

10.8

Bits

THD

Total Harmonic Distortion

VIN = 4.85 Vpp,
and fiN = 1 kHz to 15 kHz

-78

dB

IMD

Intermodulation Distortion

VIN = 4.85 Vpp,
and fiN = 1 kHito 15 kHz

-85

dB

Full-Power Bandwidth

VIN = 4.85 Vpp, where
S/(N + D) Decreases 3 dB

380

kHz

Multiplexer Channel to Channel Crosstalk

fiN = 15 kHz

-80

dB

2-345

•

Electrical Characteristics

(Continued)
The following specifications apply forV+ = AV+ = DV+= +5.0 VOC, VREF+ = 2.5 Voc, VREF- = GND, VIN- = 2.5Vfor
Sigl)ed Characteristics, VIN- = GNDJor Unsigned Characteristics and fCLK := 2.5 MHz unless otherwise specified. Boldface
Ilmlla apply for TA = T.. = TMIII to TIIAX; all other limits T A = TJ = + 25°C. (Notes .8, 9 and 10) (Co(ltinued)
Symbol

Conditions

Parameter

Signal-to-Noise Plus Distortion Ratio

Effective Bits

THO

IMD

Total Harmonic Distortion

Intermodulation Distortion

Full-Power Bandwidth

Limits
(Note 12)

Units
(Limits)

,.

DYNAMIC UNSIGNED CONVERTER CHARACTERISTIC
S/(N+D)

Typical
(Note 11)

VREF+ = 4.096V,
VIN = 4.0 Vpp, and
fiN =1 kHz to 15 kHz

.

60

dB'

VREF+ = 4.096V,
VIN = 4.0 Vpp, and
fIN.= 1 kHz to 15 kHz

9.8

Bits

VREF+ = 4.096V,
VIN = 4.0 Vpp, and
fiN = 1 kHz to 15 kHz

-70

dB

VREF+ = 4.096V,
VIN = 4.0 Vpp, and
fiN = 1 kHz to 15 kHz

-73

dB

VIN = 4.0 Vpp,
VREF+ = 4.096V,
where S/(N + D) decreases 3 dB

380

kHz

-80

dB

Multiplexer Channel to Channel Crosstalk . fiN = 15 kHz,
VRI:F+ = 4.096V

...

REFERENCE INPUT AND MULTIPLEXER CHARACTERISTICS
Reference Input Resistance

CREF'

:

Reference Input Capacitance

7
5.0
9.5
70

CIM

MUX Input Capacitance

Off Channel Leakage Current (Note 15)

On Channel Leakage Current (Note 15)

pF
-50
AY+ +50mY

MUX Input Voltage
47
On Channel
Off Channel
On Channel
Off Channel

=
=
=
=

5Vand
OV
OV and
5V

On Channel
Off Channel
On Channel
Off Channel

=
=
=
=

5Vand
OV
OVand
5V

kO
kO(min)
kO(max)

mV(min)
(max)
pF

-0.4

-3.0

!IA(max)

0.4

3.0

p.A(max)

0.4

3.0

!IA(max)

-0.4

-3.0

p.A(max)

l>

Electrical Characteristics (Continued)

"
The following specificationsapplyforV+ = AV+ =,DV+ = +S.O Voc. VREF+ = 2.S Voc. VREF- = GND. VIN- = 2.SVfor
Signed Characteristics. VIN- = GND for Unsigned Characteristics and fClK = 2.S MHz unless otherwise specified. Boldface
limits apply for TA = TJ = T.IN to TMAX; all other limits TA = TJ = +2SoC. (Notes 8.9 and 10) (Continued)
Symbol

Parameter

.'

Typical
(Note 11)

Conditions

Limits
(Note 12)

Units
(Limits)' .

2.SV ±O.S%

VREFOut

Reference Output Voltage

AVREF/AT

VREFDut Temperature Coefficient

AVREF/All

Load Regulation. Sourcing

OmA,;; Il';; +4mA

±0.003

AVREF/All

Load Regulation. Sinking

OmA,;;ll';; -1mA

±0.2

2.5V ±2%

±40
±O.O5.
±O.6

~
I\)
C

%/mA(max)
%/mA(max)

SV ±10%

±0.3

±2.5

mV(max)

13

22

mA(max)

Noise Voltage

10 Hz to 10 kHz. Cl = 100 p.F

S

p.V

±120

ppm/kHr

100

ms

Start-Up Time

o.....

ppm/DC

VREFDut = OV

tsu

i>
c

.....

Line Regulation

Long-term Stability

c:1
.....

V(max)

Short Circuit Current

AVREF/At

o
.....
Q

Q

REFERENCE CHARACTERISTICS

Isc

C

l>

o
.....
Q
.......

Co)

A-

i>

g
.....
Q

.......

Co)

CCI

Cl = 100p.F

DIGITAL AND DC CHARACTERISTICS
VIN(1)

Logical "1" Input Voltage

V+ = S.SV

VIN(O)

Logical "0" Input Voltage

V+ = 4.SV

IIN(1)

Logical "1" Input Current

VIN = S.OV

2.0

V(min)

0.8

V(max)

O.OOS

+2.5

.p.A(max)

-O.Oo'S

-2.5

p.A(max)

2.4
4.5

V(min)
V(min)

IIN(O)

Logical "0'" Input Current

VIN = OV

VOUT(1)

Logical "1" Output Voltage

V+ = 4.SV. lOUT = -360 p.A
V+ = 4.SV.IOUT = -10 p.A

VOUT(O)

Logical "0" Output Voltage

V+ = 4.SV.IOUT = 1.6 rnA

lOUT

TRI-STATE Output Current

VOUT = OV
VOUT = SV

+Isc

Output Short Circuit Source
Current

VOUT = OV. V+ = 4.SV

-Isc

Output Short Circuit Sink Current

VOUT= V+ = 4.SV

30

15

mA(min)

10+

Digital Supply Current
(Note 17)

CS = HIGH. Power Up
CS = HIGH. Power Down
CS = HIGH. Power Down.
andCLKOff

0.9
0.2
O.S

1.3
0.4
50

mA(max)
mA(max)
p.A(max)

Analog Supply Current
(Note 17)

CS = HIGH. Power Up

2.7
3

&.0
15

mA(max)
p.A(max)

Reference Input Current

VREF+ = +2.SVand
CS = HIGH. Power Up

0.&

mA(max)

IA+

IREF

CS = HIGH. Power Down

-0.1
+0.1·
-30

,.'.

.
.,

..
~.-

.'

..

2·347

,

0.4 ,.

V(min)

-3.0,
+3.0

p.A(max)
p.A(/Tlax)

-15

mA(min)

fI

~
o
,..

,...

o

c

~

S
,..

g
~

Electrical Characteristics (Continued)
The following specifications apply for V+ = AV+ = DV+ = +5.0 Vee, VREF+ = 2.5 VOC, VREF- = GND, VIN- = 2.5V for
Signed Characteristics, VIN - = GND for Unsigned Characteristics and fClK = 2.5 MHz unless otherwise specified. Boldface
limits apply for TA' = TJ ,,; TMIN to TliAx; all other limits TA = TJ = + 25°C. (Note 16)
Symbol

fClK

s,..
c(

......
,..

,

Clock Frequency ,

o

Limits
(Note 12)

3.0
5

2.5

MHz(max) ,
kHz{min)

,40
60

%(min) ,
%(max)

Clock Duty Cycle

Ie

Conversion Time

"

CO)

s,..

Typical
(Note 11)

Units
(Limits)

AC CHARACTERISTICS

CO)

g

Conditions

Parameter

tA

Acquisition Time

Iscs

~ Set-Up Time, Set-Up Time from Falling Edge of

cc(
CS to Rising Edge of Clock

12

12

5

5

4.5

4.5

Clock
Cycles
/-ts{max)
Clock
Cycles,
/-ts(max)

2

2

14
{I leLK
-' 14 ns)

30
'(1 tCLK
-30 ns)

ns{min)
(max)

IsOI

01 Set-Up Time, Set-Up Time from Data Valid on
01 to Rising Ec!ge of Clock

16

25

ns(min)

tHOI

01 Hold Time, Hold Time of 01 Data from Rising
Edge of Clock to Data not Valid on 01

2

25

ns(min)

30

50

ns(min)

tAT

DO Access Time from Rising EdQe of CLK When
~ is "Low" during a Conversion

tAC

DO or SARS Access Time from US, Delay from
Falling Edge of QS to Data Valid on DO or SARS

30

70,

ns(max)

tOSARS

Delay from Rising Edge of Clock to Falling Edge of
SARS when CS is "Low"

100

200

ns{max)

tHOO

DO Hold Time, Hold Time of Data on DO after
Falling Edge of Clock

20

35

ns{max)

tAD

DO Access Time from Clock, Delay from Falling
Edge of Clock to Valid Data of DO

40

80

ns(max)

40

50

ns{max)

30'

ns(min)

1 CLK

1CLK

cycle(min)

tlH, toH
toes
leS(H)

"

Delay from Rising Edge of CS to DO or SARS
TRI-STATE
Delay from Falling Edge of Clock to Falling Edge of

CS
US "HIGH" Time for AID Reset after Reading of
Conversion Result'

20

"

leS(L)

ADC10731 Minimum CS "Low" Time to Start a
Conversion

1 CLK

1CLK

cycle(min)

tsc

Time from End of Conversion to US Going "Low"

5CLK

5CLK

cycle(min)

tpD

Delay from Power-Down command to 10% of
Operating Current

1

/-ts

tpc

Delay from Power-Up Command to Ready to Start
a New Conversion

10

/-ts

CIN

Capacitance of Logic Inputs

7

pF

COUT

Capacitance of Logic Outputs

12

pF

.,

2-348

:r:.-

c

Electrical Characteristics (Continued)
Nole 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Nole 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifcations and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device Is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to GND, unless otherWise specified.

NOle 5: The maximum power dissipation must be derated at elevated temperatlJres and is dictated by TJmex. 9 JA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po = (TJmex - TAll9JA or the number given In the Absolute Maximum Ratings, whichever is lower. For this
device, TJmex = 150'C. The typical thermal resistance (6JAl of these Paris when board mounted can be found in the following table:
Thermal Resistance

Package Type

ADCI0731CIN

B'Z'C/W

NI6E

ADCI0731CIWM

90'C/W

MI6B

ADCI0732CIN

47"C/W

N20A

ADCI0732CIWM

80'C/W

M20B

ADC10734CIMSA

I 34'C/W

MSA20

. ADCI0734CIN

47"C/W

N20A

ADCI0734CIWM

80'C/W

M20B

ADCI0738CIN

60'C/W

N24A

ADCI0738CIWM

75"C/W

M24B

....o

Co)

CO

AV+

1;1
-------

-~

J~

I

U
-.....-+_....-. CIRCUITRY
TO INTERNAL

.-~~-------

TL/H111390-6
Nota 9: No connection exists between AV+ and DV+ on the chip.
To guarantee accurecy, "is required that the AV+ and DV+ be connected together to a power supply with separate bypass filter at eacn V+ pin.
Note 10: One LSB is referenced to 10 bits of resolution.
Note 11: Typicals are at TJ "'" TA = 25"C and represent most likely pararmetric norm.
O~ality

Level).

Nota 13: Total unadiusted error includes ollset, full·scale, linearity, multiplexer, and hold step errors.
Note 14: The DC common·mode error is measured in the differential multiplexer mode with the aSsigned positive and negative input channels shorted together.
Nota 15: Channel leakage current Is measured after the channel selection.
Nota 16: All the timing specHications are tested at the TTL logic levels, VIL = 0.8V for a falling edge and VIH = 2.0V for a rising. TRI-STATE voltage level is forced
to 1.4V.
Nota 17: The voltage applied to the digital inputs will allect the current drain during power down. These devices are tested with CMOS loglo level. (logic Low = OV
and loglc High = SV). TTL levels increase the current, during power down, to about 300 ,.A.

2·349

~
C
o
....

:r:.c
o
....

Note 8: Two on-ohip diodes are tied to each analog input as shown below. They will forward·conduct for analog input voltages one diode drop below ground or one
diode drop greater than V+ supply. Be careful during testing at low V+ levels (+4.5V), as high level analog inputs (+5V) can cause an input diode to conduct,
especially at elevated temperatures, which will cause errors In the conversion result. The speCification allows 50 mV forward bias of either diode; this means that as
long as the analog VIN does not exceed the supply voltage by inore than 50 mV, the output code will be oorrect Exceeding this range on an unselected channel will
corrupt the reading of a selected channel. If AV+ and DV+ are minimum (4.5 VocJ and full scale must be s: +4.55 Voe.

I

Co)
I\)

-'="
.....

Nota 7: See AN-450 "SUrface Mounting Methods and Their Ellect on Product Reliability" or the section titied "Surtace Mount" found in any post 1986 National

p-

....
....o

(')

....o

Semiconductor Linear Data Book for other methods of-soldering surtace mount devices.

Nole 12: Tested limits are guaranteed to National's AOOL (Average OutgOing

~

Co)

Note 6: The human body model is a 100 pF capacitor discharged through a 1.5 kll resistor into each pin. The machine model Is a 200 pF capac"or discharged
directly into each pin.

ANALOG INPUTS CHO-CH7

....

Co)

C

Note 4: When the Input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > AV+ or DV +), the current at that pin should be limited to 30 mAo
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 rnA to four.

Part Number

....
o....

(')

co
~
o

....

r---------------------------~----------------~----------------------------------,

Electrical Characteristics (Continued)

o
Q

~
~
o....
g

011,1111,1111 (+1023)
011,1111,1110 (+1022)



C

Leakage Current Test Circuit

n
....

....
....
.....
C)
Co)

+5V

0-

I

.... '

,,,
,,
,,
I

--

:I>
C

n
....

CHO

....
C)

ADC10738

(.t)

N
.....

CHl

:I>
C

~ CH2

n
....

~ CH3

~

CH4
~
""""

CHANNEL
VOLTAGE
SELECT

Co)

,a:..

.....

CH5

~ CH6

:I>

'-- CH7

,

n
....

TUH/11390-9

~.

C

C)

C»

Typical Performance Characteristics
Analog Supply Current (IA + )
va Temperature

Analog Supply Current (IA + )
vs Clock Frequency

5

Digital Supply Current (ID + )
vs Temperature

5
AY+ = +5V
2.5 ~H~

,

2

AY+ = +5V
fA = 25°C

,

'elK -

0Y+=5. 1
'eLK = 2.5 MHz

1

-;;

.

..5
'_

3

~

3

.

2

....
~

..5

:,

2

..5

1

1

0
-55 -35 -15 5 25 '5 65 85 105125

0
100

TEMPERATURE (oC)

1000

Digital Supply Current (lD + )
vs Clock Frequency

~

1
~

e;
.... 1-"

"

I
~

-1

-2
100

1000

CLOCK FREQUENCY (kHz)

10000

~

"'-

0

t;

~

'elK

1

~

:i!

Offset Error
vs Temperature
•2

AY+ = 0Y+ = +5.0V
VR,,- = GNO
= 2.5 MHz _
TA, = 25°C

0Y+ = +5V
fA = 25°C

-.

TEMPERATURE (Oc)

Offset Error
vs Reference Voltage
2

0

-1
-55 -35-15 5 25 '5 65 85 105125

10000

CLOCK FREQUENCY (kHz)

2

..5
':.>

0

0

1

2

3

,

REFERENCE VOi.TAGE (v)

5

1

AY+ = OY+ = +5V
VREf+ = 4.096V
Vm - = GNO
'eLK = 2.5 MHz

0

-1

-2
-55-35-15 5 25 '5 65 85 105125
TEMPERATURE (Oc)
TL/H/11390-33

2-351

:g
r-..

....
o

(;)

Typical Performance Characteristics

oc(

~
(;)

....

1.0

~

O.B

o
o

i

0.6

~

!

~

....
o
(;)

Linearity Error
vs Reference Voltage

Linearity Error
vs Clock Frequency

.......

2.5

I

0.4

AI/'

!

=01/' =+5.0Y

VREF+
VREF-

0.2

= 4.096V

::;

=GHO

=oIf' = +5.0V
=GND '
felK = 2.5 MHz
TA =25°C

\

1.5

I\..

1.0

.......

0.5

TA = 25°C

o
~
....

0.0

0.0

100

1000

10000

Linearity Error
vs Temperature
2

AI/'
VRFI-

\

:"CD' 2.0

~

::;

(Continued)

---

li'

~

-

I

!

.........

= =
=

AI/' 01/' +5.0V
VREF+ 4.096V
VREF- • GND

-1

::;

'elK ... 2.5 MHz

-2
-55-35-155 25456585105125

o

TEMPERATURE (oC)

REFERENCE VOLTAGE IV) ,

CLOCK FREQUENCY (kHz)

CO)

r-..

10-Blt Unsigned
Signal·to-Noise + THO Ratio
vs Input Signal Level .

....

(;)

o
·0
c(

70
li'
3

.

60

~

Avt'

::I

,

50

.~
~.

./

40

20rA-I/'~=-D~I/'-=--+5-.0-y'--r~-'

20~----------~--~

=

ov" = +S,OY

VREF+ • +4.09&Y
'I" • VREF'- • GND
SAIIPUNG RATE = 70 kHz
'elK = 2.5 11Hz

fA ~ 25°C,

Power BanClwldth Response
with 380 kHz Sine Wave

Spectral Response with
34 kHz Sine Wave

,,/

=

AI/' 01/'
+s.OV
o VREr+ = ".096V
"iii
VRU c GND
3
-20 'eLk = 2.5 MHz

7

~

..-+-+-.l

!

in

-20

...

:;J

-~_.

~ 120

•

-100

L--I--lJ'-'--'-.L.L.__' - - '

5'

10: 15

20

25

30

35

50 100 150 200 250 300 350 400

FREQUENCY (kHz)

INPUT SIGNAL LEVEL (dB)

= 2.5 MHz

-80 ~r!i-.rthm.mI=1:r.f1rl1l

~1',

-1001'1

30
-30 -25 -20 -15 -10, -5

felK

TA = 25 0 C
-40 SAMPLING RATE = 70 kHz
-60 S/(N+D);o ~8 dB +-,-+-+-H

~

-60

= ".D96V

, vAir = GND'

cl -40 TA ,= 2S oC
~
SAMPLING RATE '= 70 kHz

~ -8°~fliiiJ_

",'

o vREt

FREQUENCY (k,Hz), .

TLIHI11390-23

Typical Reference Performance ~haracteristics
Output Drift '
vs Temperature
(3 Typical Parts)

Line Regulation

Load Regulation

....L
• 20 mY 1+++++++++++.(..I..j,.j,.!.Id

\

!

..

SINKING \

>Ia

1
'

~

,

'SOURCING

1

2

"T

.

~

\i!

\

1-t+I+H++++++t++1H-i

!:;

li!

~.

.

-1

-2
-3 -2 -1 0

3

4

5

6

-55-35-155 25 45 65 85105125

SINKING
SOURCING
OUTPUT CURRENT (mA)

SUPPLY VOLTAGE (V)

Available
Output Current
, vs Supply Voltage

~

..s

i

il

..~

20
18
18
14
12
10

JUNCTION TEMPERATURE (OC)

,

,
J
J

, ./
SUPPLY VOLTAGE

. 2·352

TLlHII1390-24

.--------------------------------------------------------------------,~

c

TRI-STATE Test Circuits and Waveforms
v+
v+
ADC10738 .........-

....
o.....
....

(")

t,.

c.:I

--+-11-__-

);

c

....
o

GND

DATA
......... OUTPUT

(")

IH

I~

DATA
OUTPUT

VOH

~

.....
c.:I
N

90%

);
C

GND

TL/H/113S0-10

TL/H/11390-11

v+

v+

~

t,.

V+

....

(")
c.:I

--+-11-__-

~

);
C

....
o

(")

GND

DATA
ADC10738 I--~""-. OUTPUT

~IoH

I~

DATA
OUTPUT

.....

~

:+ _______~~
10%

OL

TL/H/113S0-12

TLlH/113S0-13

Timing Diagrams

01

DO

TRI-STATE

fill

TL/H/11390-14

FIGURE 2. 01 Timing

1..JUl.Sl

CLK

r---r-l-r

cs

'cS(H)

01

tIH ,IoH
DO

TRI-STATE

SARS

TRI-STATE TLlH/113S0-1S

FIGURE 3. DO Timing
2-353

~ r-------------------------------~----------------------------------------~--,

~
o

....

Timing Diagrams (Continued)

o
c

~
S
....

elK

g
cc
....
N
~

....o

8
~
,...o....
....
g

01

DO

C")

cc

TRI-STATE
SARS
TL/H/11390-16

FIGURE 4. Delayed DO Timing
'1

ClK

Cs~.\,
.
~ l'-'-~fp-c---~--

PO

~r----'-t--'fp-D-----------------~~~--·---.~---~-u--------------------

r

IA+

" ' - - , . . ._ _ _ _ _ _ _ _

TL/H/11390-17

FIGURE 5. Hardware Power Up/Down Sequence

ClK

01

TL/H/11390-18

FIGURE 6. Software Power Up/Down Sequence

2-354

Timing Diagrams (Continued)

~
SARS

TRI-STATE

~--------------~!~!------------~,---

ANALOG
SIGNAL

SAMPLEO
SIGNAL

--~~;~~~;~--------------~!I~-------------TUH/I1390-19

Note: IfCS is low during power up of the power supply voltages (AV+ and DV+) then CS needs
invaJid.

to go high for Ics{H). The data output aflerthe first conversion is

FIGURE 7. ADC10731 es Low during Conversion

2-355

ADC107311ADC 107321ADC107341ADC10738
-I

3'
s'
ea
C

ci'...
""3
fit

'§

a

eLK

:::J

c:

!

cs
DI

~

DO

J~~~
TRI-STATE

---------r~;rS--~--~r--~

(11

en

I--"\.
SARS

\. . ----------~------__.,IS

ANALOG
SIGNAL
.~

. TRI-STATE

,-

____-'ls--=

SAMPLED
SIGNAL
TL/H/11390-20

FIGURE 8. ADC10732, ADC10734 and ADC10738 ~ Low during Conversion
Note: II CS is low during power up 01 the power supply voltages (AV+ and DV+) then CS needs to go high lor tcs(H). The data output alter the first conversion is not valid.

::!
3
S"
ec
C

iii"

ec

rJ
3

til

(')
o

~
s-

elK

c:


o
o....

TABLE I. AOC10738 Multiplexer Address Assignment
MUXAddress
MAO

MAl

MA2

SINGI
OIFF

0001

1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
0

PU
1

MA3

(j

MUX
MODE

MA4
CHO

SELl

SELO

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

1
1
1
1

0
0

1
1

1
0
1
0
1
0
1

X

X

X

X

SIGN

C)

Channel Number

CHl

CH2

CH4

CH3

CH5

CH6

COM

+

C)

-

+
+
+
+

......

Co)

oIioo
......

l>

g
....

-

+

-

+
-

+

-

+

~

-

+

-

+

+

-

-

+

Co)

Differential

Power Down (All Channels Disconnected)

TABLE II. AOC10734 Multiplexer Address Assignment
MUXAddress
MAO

MAl

Channel Number

MA2

MA3

PU

SINGI
OIFF

0001

1
1
1
1

1
1
1
1

0
0

1
1
1
1
0

SELl

SELO

0

1
1

0
0
0
0

1
0
1

0
0
0
0

0
0
1
1

0
0
0
0

0
1
0
1

X

X

X

X

SIGN

MUX
MODE

MA4
CHO

CHl

CH2

CH3

COM

+

-

+

-

+
+
+

-

-

+

+

-

-

+

Single-Ended

Differential

Power Down (All Channels Disconnected)

TABLE III. AOC10732 Multiplexer Address Assignment
MUXAddress
MAO

MAl

MA2

PU

SINGI
OIFF

0001

1
1

1
1

0

1
1
0

Channel Number
MA3

MA4
CHO

SELl

SELO

0
0

0
0

+

1

0
0

0
1

0
0

0
0

+

X

X

X

X

SIGN

2-359

-

CHl

COM

+

-

-

+

o

o
....
C)

-

+

1

Single-Ended

-

+

1

N
....
l>

-

+

1

....
;;
o
o
....
......
Co)

-

1

1
1

CH7

MUX
MODE

Single-Ended
Differential

Power Down (All Channels Disconnected)

Q)

Pin Descriptions
ClK

DI

DO

CS

PD

SARS

CHO-CH7 These are the analog inputs of the MUX. A
channel input is selected, by the address information at the DI pin, which is loaded on the riSing edge of ClK into the address register (see
Tables I-III).
The voltage applied to these inputs should not
exceed AV+ or go below GND by more than
50 mV. Exceeding this range on an unselected
channel will corrupt the reading of a selected
channel.
COM
This pin is another analog input pin. It can be
used as a "pseudo ground" when the analog
multiplexer is single-ended.
This is the positive analog voltage reference input. In order to maintain accuracy, the voltage
range VREF (VREF = VREF+-VREF-) is
0.5 Voc to 5.0 Voc and the voltage at VREF+
cannot exceed AV+ +50 mV.
The negative voltage reference input. In order to
maintain accuracy, the voltage at this pin must
not go below GND - 50 mV or exceed AV+
+ 50 mV.
'
AV+,
DV+
These are the analog and digital power supply
pins. These pins should be tied to the same
power supply and bypassed separately. The operating voltage range of AV+ and DV+ is
4.5 Voc to 5.5 Voc.
This is the digital ground pin.
DGND
AGND
This is the analog ground pin.

The clock applied to this input controls the !juccessive approximation conversion time interval,
the acquisition time and the rate at which the
serial data: exchange occurs. The rising edge
loads the information on the 01 pin into the multiplexer address shift register. This address controls which channel of the analog input multiplexer (MUX) is selected. The falling edge shifts
the data resulting from the AID conversion out
on DO. CS enables or disables the above functions. The clock frequency applied to this input
can be between 5 kHz and 3 M~z.
This is the ,serial data input pin. The data applied
to this pin is shifted by ClK into the multiplexer
address register. Tables I through III show the
multiplexer address assignment.
The data output pin. The AID conversion result
(DBO-SIGN) are clocked out by the failing edge
of ClK on this pin.
This is the chip select input pin. When a logic
low is applied to this pin, the rising edge of ClK
shifts the data on DI into the address register.
This low also brings DO out of TRI-STATE after
a conversion has been completed.
This is the power down input pin. When a logic
high is applied to this pin the AID is powered
down. When a low is applied the AID is powered up.
"
This is the successive approximation register
status output pin. When CS is high this pin is in
TRI-STATE. With CS low this pin is active high
when a conversion is in progress and active low
at all other times.

2-360

»
c

Applications Hints
The ADC10731/2/4/8 use successive approximation to
digitize an analog input voltage. The DAC portion of the AID
converters uses a capacitive array and a resistive ladder
structure. The structure of the DAC allows a very simple
switching scheme to provide a versatile analog input multiplexer. This structure also provides a sample/hold. The
ADC1 0731 /2/4/8 have a 2.5V CMOS bandgap reference.
The serial digital I/O interfaces to MICROWIRE and
MICROWIRE+.

device during power .down. CMOS logic levels will give the
least amount o,f current drain (3 p.A). TTL logic levels will
increase the total current drain to 200 p.A.
These devices have resistive reference ladders which draw
600 p.A with a 2.5V reference voltage. The internal band
gap reference voltage shuts down when power down is activated. If an external reference voltage is used, it will have to
be shut down to minimize the total current drain of the device.

1_0 DIGITAL INTERFACE

2.0 ARCHITECTURE
Before a conversion is started, during the analog input sampling period, (tA), the sampled data comparator is zeroed.
As the comparator is being zeroed the channel assigned to
be the positive input is connected to the A/D's input capacitor. (The assignment procedure is explained in the Pin Descriptions section.) This charges the input 32C capacitor of
the DAC to the positive analog input voltage. The switches
shown in the DAC portion of Figure 11 are set for this zeroing/acquisition period. The voltage at the input and output
of the comparator are at equilibrium at this time. When the
conversion is started, the comparator feedback switches
are opened and the 32C input capacitor is then switched to
the assigned negative input voltage. When the comparator
feedback switch opens, a fixed amount of charge is trapped
on the common plates of the capacitors. The voltage at the
input of the comparator moves away from equilibrium when
the 32C capacitor is switched to the assigned negative input
voltage, causing the output of the comparator to go high
("1 ") or low ("0"). The SAR next goes through an algorithm,
controlled by the output state of the comparator, that redistributes the charge on the capacitor array by switching the
voltage on one side of the capacitors in the array. The objective of the SAR algOrithm is to return the voltage at the
input of the comparator as close as possible to equilibrium.

There are two modes of operation. The fastest throughput
rate is obtained when CS is kept low during a conversion.
The timing diagrams in Figures 7 and 8 show the operation
of the devices in this mode. CS must be taken high for at
least tCS(H) (1 ClK) between conversions. This is necessary
to reset the internal logic. Figures 9 and 1(1 show the operation of the devices when CS is taken high while the
ADC10731/2/4/8 is converting. CS may be taken. high during the conversion and kept high indefinitely to delay the
output data. This mode simplifies the interface to other devices while the ADC10731/2/4/8 is busy converting.
1.1 Getting Started with a Conversion
The ADC10731/2/4/8 need to be initialized after the power
supply voltage is applied. If CS is low when the supply voltage is applied then CS needs to be taken high for at least
tCS(H) (1 clock period). The data output after the first conversion is not valid.
1.2 Software and Hardware Power Up/Down
These devices have the capability of software or hardware
power down. Figures 5 and 6 show the timing diagrams for
hardware and software power up/down. In the case of hardware power down note that CS needs to be high for tpc
after PD is taken low. When PD is high the device is powered down. The total quiescent current, when powered
down, is typically 200 p.A with the clock at 2.5 MHz and
3 p.A with the clock off. The actual voltage level applied to a
digital input will effect· the power consumption of the

The switch position information at the completion of the
successive approximation routine is a direct representation
of the digital output. This data is then available to be shifted
on the DO pin.

2-361

o
......
......
Co)
......
......
(;)

»
c

o
......
......
Co)
N
......
(;)

»
c

o
......
(;)
......

Co)

0l:Io
......

»
c

o
......
(;)
......
Co)
co

•

ADC107311ADC107321ADC107341 ADC10738

»

""2.

(;'

I»

0'
:::J
(I)

-':

::::t
3'

..

,

-:

p-------- --------------------------------------------------.

"-

:
I
CHI

I
CH3
CH4
CH5

~I
~

CHG
CH7
COM

VREF

I
I
I
I
I

-:1"""'"-:1"""'"-:1"""'"-:1"""'"-:1"""'"-:1"""'"-

--,,,,,,"-

: -,,,,,,"._I

------

II

..

DAC

Ie

IC

IC

2C

::;= .' ::;=

=:=

-

-

32C II

CHO

CH2

Analog MUX

2C

IC

::;=

::;;:

2C

4C '

=~.= ~

::;~

Vx .:

'; BC

'-=~

1SC

32C

r- t ~ t

\4:t t~ .t ~ t
1

1

~'

;-

'1

"

.~

~~
-

,r-'

'~7

.=

=~

( I)

'ata

\i"1 t \f1t1'1 t '11 ".

V.....

'§
~
::>

!

..
'

AZ,

.

ii03C

-.

R/2

R

.'

R/2
11.5R
2R
R

-

R

---------- ----------- ---- -----

VREF +

FROM
MULTIPLEXER
ADDRE5S
DECODER

,

,

, ....

,

OBO

DBI

DB2

DB3

...
DB4

, ...

--- --- --- ---

DB5

--, ...

, ...

DBG

DB7

DBB

OB9

FROM SAR

I
I
I
I

.

SIGN

FROM
. CONTROL
LOGIC

TO
SAR

TUH111390-28

FIGURE 11. Detailed Diagram of the ADC10738 DAC and Analog Multiplexer Stages

l>

C

Applications Hints (Continued)
output noise can be obtained by increasing the output capacitance. A 100 ,.,.F capacitor will yield a typical noise floor
of 200 nVlJHZ. The pseudo-differential and differential multiplexer modes allow for more flexibility in the analog input
voltage range since the "zero" reference voltage is set by
the actual voltage applied to the assigned negative input
pin.
In a ratiometric system (Figure 13a), the analog input voltage is proportional to the voltage used for the AID reference. This voltage may also be th'e system power supply, so
VREF+ can also be tied to AV+. This technique relaxes the
stability requirements of the system reference as the analog
input and AID reference move together maintaining the
same output code for a given input condition.

3.0 APPLICATIONS INFORMATION
3.1 Multiplexer Configuration
The design of these converters utilizes a sampled·data
comparator structure, which allows a differential analog in·
put to be converted by the successive approximation rou·
tine.
The actual voltage converted is always the difference be·
tween an assigned" +" input terminal and a "-" input ter·
minal. The polarity of each input terminal or pair of input
terminals being converted indicates which line the conv'erter
expects to be the most positive.
A unique input multiplexing scheme has been utilized to pro·
vide multiple analog channels. The input channels can be
software configured into three modes: differential, single·
ended, or pseudo·differential. Figure 12 illustrates the three
modes using the 4·channel MUX of the ADC10734. The
eight inputs of the ADC10738 can also be configured in any
of the three modes. The single·ended mode has CHO-CH3
assigned as the positive input with COM serving as the neg·
ative input. In the differential mode, the ADC10734 channel
inputs are grouped in pairs, CHO with CHl and CH2 with
CH3. The polarity assignment of each channel in the pair is
interchangeable. Finally, in the pseudo·differential mode
CHO-CH3 are positive inputs referred to COM which is now
a pseudo·ground. This pseudo·ground input can be set to
any potential within the input common·mode range of the
converter. The analog signal conditioning required in trans·
ducer·based data acquisition systems is significantly simpli·
fied with this type of input flexibility. One converter package
can now handle ground·referred inputs and true differential
inputs as well as signals referred to a specific voltage.
The analog input voltages for each channel can range from
50 mV below GND to 50 mV above V+ = DV+ = AV+
without degrading conversion accuracy. If the voltage on an
unselected channel exceeds these limits it may corrupt the
reading of the selected channel.

For absolute accuracy (Figure 13b), where the analog input
varies between very specific voltage limits, the reference pin
can be biased with a time- and temperature·stable voltage
source that has excellent initial accuracy. The LM4040,
LM4041 and LM185 references are suitable for use with the
ADCl 0731 12/4/8.
.

o
....
o

........

....
.......
Co)

l>

C

o
....
o

fj

N

i>
c
o
....
o

........

Co)

~
.......
l>
C

o
....
~
CD

The minimum value of VREF (VREF = VREF+ -VREF-) can
be quite small (see Typical Performance Characteristics) to
allow direct conversion of transducer outputs providing less
than a 5V output span. Particular care must be taken with
regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the
increased sensitivity of the converter (1 LSB equals VREFI
1024).
'
3.3 The Analog Inputs
Due to the sampling nature of the analog inputs, at the clock
edges short duration spikes of current will be seen on the
selected assigned negative input. Input bypass capacitors
should not be used if the source resistance is greater than
1 kO since they will average the AC current and cause an
effective DC current to flow through the analog input source
resistance. An op amp RC active lowpass filter can provide
both impedance buffering and noise filtering should a high
impedance signal source be required. Bypass capacitors
may be used when the source impedance is very low without any degradation in performance.

3,2 Reference Considerations
The voltage difference between the VREF+ and VREF- in·
puts defines the analog input voltage span (the difference
between VIN(Max) and VIN(Min» over which 1023 positive
and 1024 negative possible output codes apply.

In a true differential input stage, a signal that is common to
both "+" and "-" inputs is canceled. For the
ADC10731/2/4/8, the positive input of a selected channel
pair is only sampled once before the start of a conversion
during the acquisition time (tA)' The negative input needs to
be stable during the complete conversion sequence because it is sampled before each decision in the SAR sequence. Therefore, any AC common-mode signal present
on the analog inputs will not be completely canceled and
will cause some conversion errors. For a sinusoid commonmode signal this error is:

The value of the voltage on the VREF+ or VREF- inputs
can be anywhere between AV+ + 50 mV and -50 mV, so
long as VREF+
is greater than VREF-' The
ADCl 0731/2/4/8 can be used in either ratio metric applications or in systems requiring absolute accuracy. The reference pins must be connected to a voltage source capable
of driving the minimum reference input resistance of 5 kO.
The
internal
2.5V
bandgap
reference
in
the
ADC10731 12/4/8 is available as an output on the VREFOut
pin. To ensure optimum performance this output needs to
be bypassed to ground with 100 ,.,.F aluminum electrolytic or
tantalum capaCitor. The reference output can be unstable
with capacitive loads greater than 100 pF and less than
100 ,.,.F. Any capacitive loading less than 100 pF and
greater than 100 ,.,.F will not cause oscillation. 'Lower

VERROR(max) = VPEAK (2 '11' fCM) (te)
where fCM is the frequency of the common-mode signal,
VPEAK is its peak voltage value, and tc is the AID's conversion time (te = 12/fcLKl. For example, for a 60 Hz common-mode signal to generate a % LSB error (0.61 mV) with
a 4.8 ,.,.S conversion time, its peak value would have to be
approximately 337 mV.

2-363

•

Applications Hints (Continued)

4 Single-Ended
CHO,
CHl

CHO, {
CHl

+(-)

ADC10734

ADC10734

CH2
CH3
COM

4 PsuedoDifferential

2 Differential

CH2, {
CH3

+(-)

CHO

+

CHl

+

CH2

+

CH3

+

-(+)

AOC10734

COM

FIGURE 12. Analog Input Multiplexer Options

2 Single-Ended
and 1 Differential

+(-)

CHO {
CHl

- (+) ADC10734

CH2

+

CH3
COM

+

-

TL/H/11390-27

a. Ratlo'metrlc Using the Internal Reference
+5V

-- Rt. <= 7,.2_6_n~_......"!-_
Av+

oV+

TL/H/11390-29

b. Absolute Using a 4.096V Span
+5V

68011

t-t---;I--t---+I

Av+
CHO

t-t---;I---'" CH 1

Dv+

LIot4040-4.1
ADC10734

HI---+lCH2

TL/H/11390-30

FIGURE 13. Different Reference Configurations

2·364

Applications Hints

>
C
o....

(Continued)
3.5 The Input Sample and Hold
The ADC10731/2/4/8's sample/hold capacitor is implemented in the capacitor array. Alter the channel address is
loaded, the array is switched to sample the selected positive
analog input. The sampling period for the assigned positive
input is maintained for the duration of the acquisition time
(tA) 4.5 clock cycles.

3.4 Optional Adjustments
3.4.1 Zero Error
The zero error of the A/D converter relates to the 'location
of the first riser of the transfer function '(see Figure 1) and
can be measured by grounding the minus input and applying
a small magnituqe voltage to the plus input. Zero error is the
difference between actual DC input voltage which is necessary to just cause an output digital code transition from
000 0000 0000 to 000 0000 0001 and the ideal % LSB
value (% LSB = 1.22 mV for VREF = + 2.500V).
The zero error of the AID does not require adjustment. If
the minimum analog input voltage value, VIN(Min), is not
ground, the effective "zero" voltage can be adjusted to a
convenient value. The converter can be made to output an
all zeros digital code for this minimum input voltage by biasing any minus input to VIN(Min). This is useful for either the
differential or pseudo-differential input channel configurations.

This acquisition window of 4.5 clock cycles is available to
allow the voltage on the capacitor array tei settle to the positive analog input voltage. Any change in the analog voltage
on a selected positive input before or alter the acquisition
window will not effect the AID conversion result.
In the simplest case, the array's acquisition time is determined by the RON (3 kn) of the multiplexer switches, the
stray input capacitance CSl (3.5 pF) and the total array (CLl
and stray (CS2) capacitance (48 pF). For a large source
resistance the analog input can be modeled as an RC net·
work as shown in Figure 14. The values shown yield an
acquisition time of about 1.1 ,,"S for 10-bit unipolar or 10-bit
plus sign accuracy with a zero-to-full-scale change in the
input voltage. External source resistance and capacitance
will lengthen the acquisition time and should be accounted
for. Slowing the ·clock will lengthen the acquisition time,
thereby allowing a larger external source resistance.

3.4.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1% LSB down from the desired
analog full-scale voltage range and then adjusting the VREF
voltage (VREF = VREF+ - VREF-) for a digital output code
changing from 011 1111 1110 to 01 ~ 1111 1111. In bipolar
signed operation this only adjusts the positive full scale error.
3.4.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A plus input voltage which
equals this desired zero reference plus % LSB is applied to
selected plus input and the zero reference voltage at the
corresponding minus input should then be adjusted to just
obtain the 000 0000 0000 to 000 0000 0001 code transition.

Q
.....

....W

i>
c
o
....

~

N
.....
>
C
o
.;.0.

Q
.....
w

:t
>
c
o....
~

w

C»

TLlH/113S0-25

FIGURE 14. Analog Input Model
, The signal-to-noise ratio of an ideal AID is the ratio of the
'RMS value of the full scale input signal amplitude to the
value of the total error amplitude (including noise) caused
by the transfer function of the ideal AID. An ideal 1O-bit plus
sign AID converter with a total unadjusted error of 0 LSB
would have a signal·to-(noise + distortion) ratio of about 68
dB, which can be derived from me equation:

The full-scale adjustment should be made [with the proper
minus input voltage applied] by forcing a voltage to the plus
input which is given by:
VIN( +) Is adj = VMAX - 1.5 [ (VMAX 2~ VMIN) ]

where S/(N

where VMAX equals the high end of the'analog input range,
VMIN equals the low end (the offset zero) of the analog
range. Both VMAX and VMIN are ground referred. The VREF
(VREF = VREF+ - VREF-) voltage is then adjusted to provide a code change from 011 1111 1110 to 011 1111 1111.
Note, when using a pseudo-differential or differential multiplexer mode where VREF+ and VREF- are placed within
the V+ and GND range, the individual values of VREF and
VREF- do not matter, only the difference sets the analog
input voltage span. This completes the adjustment proce·
dure.

2-365

S/(N + D) = 6.02(n) + 1.8
+ D) is in dB and n is the number of bits.

•

co ,---------------------------------------------------------------------------------,

('I')

.....
I:)

.....
cc(

Applications Hints (Continued)

o

+5V

.....
-.:t
.....
.....

+5V

('I')

'"
'-

o

...
'-

.....
N

-:::....'"0

cc(

VIN

470n

N

('I')

.....
.....
o
c

R3

u
c

c

c(

(AI

+

DV'

'"

~
'N
'-

'"....o

u

I:)

c(
.....
.....
.....

>...J,W....+-\M.......

DV+

VIN

I:)

c(

A2)IIA3 ,; Ik

TLlH/11390-31

('I')

I:)

.....
o
cc(

Note I: Diodes are IN914.

Note 2: The protection diodes should be able to withstand the output current of the op amp under current limit.

FIGURE 15. Protecting the Analog Inputs

~ A~~-1~--~~----------------_,
'N
'-

...

4.3k
2.5 Voc

COM~-1~---.------._----~--__+

+

5 Voc ±10%

1

J.I£:[,

ZERO
ADJ

20k

47.5k*

FS
ADJ
L-....__- ..... l/2 of LM611

B2k

lOOk

+
.. 1% resistors
TL/H/11390-32

FIGURE 16. Zero-Shift and Span-Adjust for Signed or Unsigned, Single-Ended
Multiplexer Assignment, Signed Analog Input Range of O.5V ,;; VIN ,;; 4.5V

2·366

f}1National Semiconductor

Ace 10831, Ace 10832, Ace 10834, Ace 10838

10=Bit Plus Sign Serial 1/0 AID Converters
with MUX, Sample/Hold and Reference
General Description

Features

This series of CMOS 1O-bit plus sign successive approximation AID converters features versatile analog input multiplexers, sample/hold and a 2.5V band-gap reference. The
1, 2, 4 or 8-channel multiplexers can be software configured
for single-ended or differential mode of operation.

• - 5V to + 5V analog voltage, range with ± 5V supplies
• Serial 110 (MICROWIRE compatible)
• 1, 2, 4, or 8-channel differential or single-ended
multiplexer
• Software or hardware power down
• Analog input sample/hold function
• Ratiometric or Absolute voltage referencing
• No zero or full scale adjustment required
• No missing codes over temperature
• TTl/MOS input/output compatible
• Standard DIP and SO packages

An input sample/hold is implemented by a capacitive reference ladder and sampled-data comparator. This allows the
analog input to vary during the AID conversion cycle.
In the differential mode, valid outputs are obtained even
when the negative inputs are greater than the positive because of the 10-bit plus sign output data format.
The serial 110 is configured to comply with the NSC
MICROWIRETM serial data exchange standard for easy interface to the COPSTM and HPCTM families of controllers,
and can easily interface with standard shift registers and
microprocessors.

Key Specifications
10 bits plus sign
±5V
59 mW (Max)
33 p.W
5 p.s (Max)
74 kHz (Max)
2.5V ±2% (Max)

•
•
•
•
•

Resolution
Dual supply
Power dissipation
In power down mode
Conversion time
II Sampling rate
• Band-gap reference

Applications
• Medical instruments
• Remote instrumentation
• Test equipment

ADC10838 Simplified Block Diagram
ClK

CS

PO

SARS

•

DO

DI

CHO
CHI
CH2
CH3
CH4
CH5
CH6
CH7
COM

AV+

VREF -

VREFOUT

____

____--I
t-;::==::::::::::::;-.........~:-;~-T7TTl'"rr:~...---...

AGNO
VREF + :!=~=-

--1-!..r....JO....JO~:-::-~~.&....&...'

DECODER

11

OUTPUT
SHIFT
REGISTER

DV+
DGND

VTl/H/11391-1

2-367

~
~

..-

8c(

t

~
..-

8c(

i

..-

Connection Diagrams for Dual-In-Line and SO Packages
16

DV+

AV+

cs

2

15

VREFOUT

CHO

(+)

3

14

ClK

CH1

cs

AV+

(-)

DV+
2

VREFOUT

SARS

CH2

Dr '

DO

CH3

ClK

PD

VREF -

N.C.

DGND

VREF +

COM

N.C.

V-

AGND

DO

PD

8c(

VREF -

DGND
TLIH111391-2

V-

'Top View

10

12

VREF +

1j

AGND

See NS Package Number N16E or M16B

TLIH111391-4

Top View
, See NS Package Number N20A or M20B,
20

AV+

DV+

CHO

VREFOUT

CH1

cs

N.C.

01

N.C.

ClK

ADC10832

N.C.

11

cs

..

DI
ClK
SARS

ADC10838

CH5

VREF +
10

3

CH4

VREF -

DOND

VREFOUT

CH1

CH3

DO

PD

DV+
2

CH2

SARS

COM

V-

AV+
CHO

DO

CH6

AGND

VREF -

CH7

VREF +

COM

TL/H/11391-3

Top View
See NS Package Number N20A or M20B

,AGND

PD

11

14

V-

DGND

12

'13

VTLlH111391-5

Top View
See NS Package Number N24A or M24B

Ordering Information
Industrial Temperature Range
-40"C s: TA s: +85"C

Package

ADC10831CIN
ADC10831CIWM
ADC10832CIN
ADC10832CIWM
ADC10834CIN
ADC10834CIWM
ADC10838CIN
ADC10838CIWM

N16E
M16B
N20A
M20B
N20A
M20B
N24A
M24B

2-368

Absolute Maximum Ratings

(Notes 1 & 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Positive Supply Voltage (V + = AV + = DV+)
+6.0V
Negative Supply Voltage (V-)
Total Supply Voltage (V+ - V-I
Total Reference Voltage (VREF+ -VREF-)

Storage Temperature

Operating. Ratings

TMIN :s; TA:S; TMAX
ADC10B31CIN, ADC10B31CIWM,
ADC10B32CIN, ADC10B32CIWM,
ADC10B34CIN, ADC10B34CIWM,
ADC10B3BCIN,ADC10B3BCIWM -40'C:s; TA:S; +85'C

-6.0V
12V
+6.0V

Package Dissipation at T A

= 25'C (Note 5)

ESD Susceptability (Note 6)
Human Body Model
Machine Model
Soldering Information
N packages (10 seconds)
SO Package (Note 7)
Vapor Phase (60 seconds)
Infrared (15 seconds)

+ 4.5V to + 5.5V

Positive Supply Voltage

V+ + 0.3V to V- - 0.3V
Voltage at other Inputs and Outputs V+ + 0.3V to -0.3V
Package Input Current (Note 4)

(Notes 2 and 3)

Operating Temperature Range

Voltage at Analog Inputs
(CHO·CH7 and COM)

Input Current at Any Pin (Note 4)

-40'Cto +150'C

(V+

=

=

DV+)
Negative Supply Voltage (V-)

30mA

AV+

VREF+

120mA

VREF-

500mW

VREF (VREF+ -VREF-)

- 4.5V to - 5.5V
AV+ +50mVto -50mV
AV+ +50mVto -50mV
+0.5VtoV+

2S00V

150V
260'C
215'C
220'C

Electrical Characteristics

The following specifications apply for V+ = AV+ = DV+ = +5.0 VOC, VREF+ = +4.096 Voc, VREF- = VIN- = GND,
V- = -5.0Voc, and fCLK = 2.5 MHz unless otherwise specified. Boldface limits appfy forTA = TJ = TIlIN to TMAX; all
other limits TA = TJ = + 25'C. (Notes B, 9 and 10)

Symbol

Parameter

Conditions

Typical
(Note 11)

Limits
(Note 12)

Units
(Limits)

STATIC CONVERTER CHARACTERISTICS

10

Resolution with No Missing Codes

+ Sign

Bits

±2;0

LSB(max)

±1.25

LSB(max)

Positive and Negative
Full·Scale Error

±1.5

LSB(max)

Offset Error

±1.5

LSB(max)

TUE

Total Unadjusted Error (Note 13)

INL

Positive and Negative Integral
Linearity Error

Power Supply Sensitivity
Offset Error
+ Full·Scale Error
- Full·Scale Error
DC Common Mode Error (Note 14)

=

+5.0V ±10%
orV- = -5.0 ±10%

±0.2
±0.2
±0.1

±1.0
±1.0
±0.75

LSB(max)
LSB(max)
LSB(max)

VIN+ = VIN- = VINwhere
+S.OV ~ VIN ~ -SV

±0.15

±O.&

LSB(max)

V+

Multiplexer Channel to
Channel Matching

±0.1

2·369

LSB

•

Electrical Characteristics

(Continued)
The following specifications apply for V+ = AV+ = DV+ = +5.0 Vec;VREF+ = +4.096 Vec, VREF- = VIN- = GND,
V- = -5.0 Vec, and fCLK = 2.5 MHz unless otherwise specified. Boldface limits applv for TA = TJ = TMIN to TMAX;
all other limits TA = TJ' = +25D C. (Notes 8, 9 and 10) (Continued)
Symbol

Conditions

Typical
(Note 11)

VIN = 8.0 Vpp,
Sampling Rate = 74 kHz
and fiN = 1 kHz to 15 kHz

67

VIN = 8.0 Vpp,
Sampling Rate = 74 kHz
and fiN = 1 kHz to 15 kHz

10.8

Bits

VIN = 8.0 Vpp,
Sampling Rate = 74 kHz
and fiN = 1 kHz to 15 kHz

-78

dB

VIN = 8.0 Vpp,
Sampling Rate = 74kHz
and fiN = 1 kHz to 15 kHz

-85

dB

VIN = 8.0 Vpp, where
S/(N + D) Decreases 3 dB
Sampling Rate = 74kHz

380

kHz

fiN = 15 kHz
Sampling Rate

-80

dB

Parameter

Limits
(Note 12)

Units
(Limits)

DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D)

Effective Number of Bits

ENOB,'

...
i...

THO

8cc

Signal-to-Noise Plus Distortion Ratio

Total Harmonic Distortion

IMD

Intermodulation Distortion

Full-Power Bandwidth

Multiplexer Channel to Channel Crosstalk

=

74 kHz

dB

"

'

,

REFERENCE INPUT AND MULTIPLEXER CHARACTERISTICS
Reference Input Resistance

CREF

'.

Reference Input Capacitance

MUX Input Capacitance
Off Channel Leakag,e Current (Note 15)

On Channel Leakage Current (Note 15)

I

kO
kO(min)
kO(max)

Y- -50mY
AY+ +50mY

(min)
(max)

70

MUX Input Voltage
CIM

5.0
9.5

7

pF

47

= + 5V and
= - 5V
= -5Vand
= + 5V
On Channel = + 5V and
Off Channel = + 5V
On Channel = - 5V and
Off Channel = + 5V
On Channel
Off Channel
On Channel
Off Channel

2-370

pF

-0.4

-3.0

/LA(max)

0.4

3.0

/LA(max)

0.4

3.0

/LA(max)

-,0.4

-3.0

/LA(max)

~

C

Electrical Characteristics (Continued)
The following specifications apply for V+ = AV+ = DV+ = +5.0 Voc. VREF+ = +4.096 Voc. VREF- = VIN- = GND.
V- = -5.0 Voc. and fCLK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX;
all other limits TA = TJ = +25'C. (Notes B. 9 and 10) (Continued)
Symbol

Parameter

Conditions

Typical
(Note 11)

Limits
(Note 12)

Units
(Limits)

2.5V ±0.5%

2.5V ±2%

V(max)

REFERENCE CHARACTERISTICS
VREFOut

Reference Output Voltage

~VREF/~T

VREFOut Temperature Coefficient

±40

load Regulation. Sourcing

OmAS; ILS; +4mA

~VREF/~IL

load Regulation. Sinking

o mA S; IL S;

Line Regulation

5V ±10%

Short Circuit Current

VREFOut = OV

Noise Voltage

10 Hz to 10 kHz, CL = 100,..F

~VREF/~t

long-term Stability

tsu

Start-Up Time

<:)
01)
Co)

....
~

C

....
c

(")
01)
Co)

~VREF/~IL

Isc

o....

-1 mA

CL = 100,..F

ppm/'C

~
~

C

....

(")

±0.003

±0.05

%/mA(max)

±0.2

±0.6

%/mA(max)

±0.3

±2.5

mV(max)

.!'-

13

22

mA(max)

c
o....

5

,..V

±120

, ppm/kHr

100

ms

<:)
01)
Co)

~

g

Co)
01)

DIGITAL AND DC CHARACTERISTICS
VIN(l)

logical "1" Input Voltage

V+ = 5.5V

2.0

V(min)

VIN(O)

logical "0" Input Voltage

V+ = 4.5V

0.8

V(max)

IIN(l)

logical "1" Input Current

VIN = 5.0V

IIN(O)

logical "0" Input Current

VIN = OV

VOUT(l)

logical "1" Output Voltage

V+ = 4.5V, lOUT = -360,..A
V+ = 4.5V.loUT = -10,..A

VOUT(O)

logical "0" Output Voltage

V+ = 4.5V, lOUT = 1.6 mA

lOUT,

TRI-STATE Output Current

VOUT = OV
VOUT = 5V

+Isc

Output Short-Circuit Source
Current

VOUT = OV, V+ = 4.5V

M05

+2.5

,..A(max) ,

-0.005

-2.5

,..A(min)

2.4
4.5

V(min) ,
V(min)

0.4

V(min),

-0.1
+0.1

-3.()
+3.0

,..A(min) ,
,..A(max)

-30

-15

mA(max)

-ISC

Output Short-Circuit Sink Current

VOUT= V+ = 4.5V

30

15

mA(min)

10+

Digital Supply Current
(Note 17)

CS =
CS =
CS =

HIGH, Power Up
HIGH, Power Down
HIGH. Power Down,
and ClK Off

0.9
0.2
0.5

1.3
0.4
,50

mA(max)
mA(max)
,,..A(max)

IA+

Positive Analog Supply Current
(Note 17)

2.7
3.0

6.0
15

mA(max)
,..A(max)

IA-

Negative Analog Supply Current
(Note 17)

~ =
CS =
CS =

-2.7'
-3.0

-4.5
-15

mA(min)
,..A(min)

IREF

Reference Input Current

0.6 '

mA(max)

HIGH, Power Up
HIGH, Power Down

HIGH. Power Up
CS = HIGH, Power Down

VREF+ = +2.5Vand
CS = HIGH, Power Up

2-371

fII

Electrical Characteristics

(Continued)
The following specifications apply for V+ = AV+ = DV+ = +5.0 VOC, VREF+ = +4.096 VOC, VREF- = VIN = GND,
V- = -5.0 VOC, and fClK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = T.. = T.IN to T.AX;
all other limits T A = TJ = + 25'C. (Note 16)
Symbol

Parameter

Conditions

Typical
(Note ,11)

Limits
(Note 12)

Units
(Umlts)

3.0
5

2.5

MHz(max)
kHz(min)

40

%(min)
%(max)

AC CHARACTERISTICS
fClK

Clock Frequency
Clock Duty Cycle

eo
Ie

Conversion Time

12
5

5

tA

Acquisition Time

4.5

4.5

. tscs

OS Set-Up Time, Set-Up Time from Falling Edge of
CS to Rising Edge of Clock

,
tSOI

DI Set-Up Time, Set-Up Time from Data Valid on
DI to Rising Edge of Clock

tHol

DI Hold Time, Hold Time of DlData from Rising
Edge of Clock to Data not Valid on DI

tAT
tAC

DO Access Time from Rising Edge ofClK When

Clock
Cycles
/Ls(max)
Clock
Cycles
/Ls(max)

2

2

14
(1 tClK
,- 14 ns)

30
(1ICLK
-30ns)

ns(min)
(max)

16

25

ns(min)

2

25

ns(min)

30

50

ns(min)

30

70

ns(max)

,

es is "low" during a Conversion
' DO or SARS Access Time from es, Delay from
Falling Edge of es to Dllta Valid on DO or SARS

12

tOSARS

Delay from Rising Edge of Clock to Falling Edge of
SARS when CS is "low','

100

200

ns(max)

tHOO

DO Hold Time, Hold Time of Data on DO after
Failing Edge of Clock

20

45

ns(max)

tAD

DO Access Time from Clock, Delay from Falling
Edge of Clock to Valid Data of DO

40

80

ns(max)

tlH, ioH

Delay from Rising Edge of CS to DO or SARS
TRI-STATE

40

50

ns(max)

20

30

ns(min)

1 ClK

1CLK

cycle(min)

1 ClK

1CLK

cycle(min)

5ClK

5CLK

cycle(min)

tocs
tcs(H) ,

Delay from Falling Edge of Clock to Falling Edge of

es
es "HIGH" Time for AID Reset after Reading of
Conversion Result

tcs(l)

ADC10731 Minimum OS "low" Time to Start a
Conversion

tsc

Time from End of Conversion to

tpo

Delay from Power-Down command to 10% of
Operating Current

tpc

Delay from Power-Up Command to Ready to Start
a New Conversion

CIN

Capacitance of logic Inputs

7

pF

COUT

Capacitance of logic Outputs

h

pF

es Going "low"

1

2-372

10

/Ls
/Ls

Electrical Characteristics

(Continued)

Nota 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Nota 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specHic performance limits. For guaranteed specifcatlons and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 3: All volmges are measured with respect to GND, unless otherwise specified.

Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, OJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po = (TJmax - TAllOJA or the number given In the Absolute Maximum Ratings, whichaver Is lower. For this
device, TJmax = 150'C. The typical thermal resistance (OJAl of these Paris when board mounted can be found in the following table:
Part Number

Thermal Resistance

Package Type

82'CIW

N16E

ADC10831CIN

:s:O

Note 4: When the Input voltage (VIN) at any pin exceeds the power supplies (VIN < V- or VIN > AV+ or DV+), the current at that pin should be limited to 30 mAo
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.

....o

(")
CIt
Co)

j')

:s:O

....

(")

i

Co)

ADC10831CIWM

90'C/W

M16B

ADC10832CIN

47'C/W

N20A

ADC10832CIWM

80'C/W

M20B

ADC10834CIN

47'C/W

N20A

(")

ADC10834CIWM

80'C/W

M20B

i

ADC10838CIN

60'C/W

N24A

ADC10838CIWM

75'C/W

M24B

~

:s:O

....

Co)

CIt

Note 6: The human body model is a 100 pF capacitor discharged through a 1.5 kO resistor into each pin. The machine model is a 200 pF capac~or discharged
directly into each pin.
Note 7: See AN·450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section titied "Surtace Mount" found in any post 1986 National
Semiconductor Linear Data Book for other methods of soldering surtace mount devices.
Note 8: Two on-ohip diodes are tied to each analog input as shown below. They will forward-conduct for analog input voltages one diode drop below V- or one
diode drop greater than V+ supply. Be careful during testing at low V+ and V- levels (±4.5V), as high level analog inputs (±5V) can cause an input diode to
conduct, especially at elevated temperatures, which will cause errors In the conversion result. The specification allows 50 mV forward bias of either diode; this
means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. Exceeding this range on an
unselected channel will corrupt the reading of a selected channel. If AV+ and DV+ are minimum (4.5 Vocl and V- is a maximum (-4.5 Voc) full scale must be
,,; ±4.55 Voe.

AV+

1;1
p-' - - - - - - -

I

..,

n. I ... .. TO INTERNAL
ANALOG INPUTS CHO-CH7 _U-I-....- . CIRCUITRY
-=-

.-A"-------

•

TL/H/11391-6
Note 9: No connection exists between AV + and DV + on the chip.
To guarantee accuracy, it is required that the AV+ and DV+ be connected together to a power supply with separate bypass finer at eacn V+ pin.
Note 10: One LSB is referenced to 10 bits of resolution.
Note 11: Typicals are at TJ

=

TA

=

25°C and represent most likely pararmetric norm.

Note 12: Tested limits are guaranteed to National's AOQL (Average OutgOing Quality Level).
Note 13: Total unadjusted error includes offsel, full·scale, linearity, multiplexer, and hold step errors.
Note 14: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 15: Channel leakage current is measured after the channel selection.
Note ·16: All the timing specifications are tested at the TIL logic levels, VIL

= 0.8V for a falling edge and VIH = 2.0V for a rising. TRI-STATE voltage level is forced

to 1.4V.
Note 17: The voltage applied to the digital inputs will affect the current drain during power down. These devices are tested with CMOS logic levels (logiC Low
and logic High = 5V). TIL levels increase the power down current to about 300 pA.

2-373

= OV

Electrical Characteristics (Continued)
011,1111,1111 (+1023)
011,1111,1110 (+1022)

.

"

",
ZERO TRANSITION

I
....
CO
CI
....

C')

g
C

~

"
""

"

"
""

,"

""

"

--r--

--"'POSIT1VE
fULL-SCALE
TRANSITION
"

"

"

100,0000,000 1 (-I 023)
100,0000,0000 (-1024)

fULL-SCALE
TRANSITION
ANALOG INPUT VOLTAGE (Y,N
VREf

= V,N {+) - V,N {-»

= VREf {+) - VREfH

TLlH111391-7

FIGURE 1A. Transfer Characteristic

'iii'

V,N{-»V,N {:)

.

d
~

LINEARITY
ERROR

+3LSB

0

+2LSB
LINEARITY
ERROR
+1 LSB

-1 LSB

POSITIVE INPUT RANGE

-2LSB

-3LSB
OUTPUT CODE
(from -1024 to +1023)
TLlH111391-B

FIGURE 1B. Simplified Error Curve VB Output Code

2·374

~

c
o.....
o

Leakage Current Test Circuit
+5V

CD

0-

....1
-5V

Co)
.....

'orr

I

1

~:

~

c

CHO

o
.....

ADC10838

o

CD

CHI

1
1
1
1

1S

~ CH2

~

~ CH3

c
o
.....
o

CH4

I

'~
"""
~
.....

CHANNEL
VOLTAGE
SELECT

..

CH5

CD

CH6

Co)

~

CH7

~

TLlH111391-9

c

o.....
o
CD
Co)

CD

2-375

Typical Performance Characteristics
Analog Supply Current (IA + )
·vs Clock Frequency

Analog Supply Current (IA +)
vs Temperature
Av+

I-t-t-t-+- feLK

Digital Supply Current (ID + )
vs Temperature

Av+ = +5V
TA = 25 0 C -ttftt---1H-H+Hii

= +5V'·
- 2.5 ~H~

Dv+ = 5V I
felK
2.5 MHz

=

1
~

..s

:....:

2 1-1-+-+-+-+-I---+-I-l

O~~~~W-~-L~~

O~~~~-L~-L-L~

-55 -35 -15 5

25 45 65 85 105125

100

1000

TEMPERATURE (OC)

TA

Offset Error
vs Reference Voltage

Offset Error
vs Temperature

Av+ = Dv+ • +5.0V
vREr- = GND
feLK = 2.5 MH. _
'A
25°C

= +5V

=

TEMPERATURE (Oc)

CLOCK FREQUENCY (kH.)

Digital Supply Current (ID + )
vs Clock Frequency
Dv+

1
-55 -35-15 5 25 45 65 85 105125

10000

25°C

1

=

"

Av+ = Dv+ = +5V
VREf+ = 4.096V
Vm - = GND
felK = 2.5 MHz

~

i-"

-2

1
100

1000

10000

1

2,5

~

0.8

'iO' 2.0

~

0.6

!

0.4

51

1.5

!

1.0

e\

=
= GND

::;

VRE'
feLK

\

e\
Av+ = Dv+ = +5.0V
VREF+
4.096V

Av+

\

~

VREr-

-55 -35-15 5 25 45 65 85 105125

4

TEMPERATURE (Oc)

Linearity Error
vs Reference Voltage

I,D

0.2

2

REFERENCE VOLTAGE (V)

Linearity Error
vs Clock Frequency

::;

TA

Linearity Error
vs Temperature

= Dv+ = +5.0V
= GND

= 2.5 MHz
= 25°C

~

~

!

'" r- -.....

0.5

~

::;

TA = 25°C

0.0

0.0
100

1000

10000

1

~

"

60

ovt

~

50

;!

40

o

SAt.fPlING RATE = 70 kHz

V

f--

V'
V

-25

-20

=

=

'iO' -20

= 2.5 MHz
=

3

-20

'elK

i&t
~

-.40

TA
25°C
SAMPLING RATE = 10 kHz

~

§

M

-60

1il-8°~_ _ _
-IOO~
-15

Power Bandwidth Response
with 380 kHz Sine Wave

Av+
Dv+
+5.0V
v",+ = 4.096V -r--+--t-Ti

v",- = GND

'iO'

;i

1il
30
-30

=

_ _ _-L~-L-L~
TEN PERATURE (Oc)

Spectral Response with
34 kHz Sine Wave

= +S.OV

VREF+ a: U.096V
• GND

V

~

20r-----~------r_-r_,

\{" = VREr-

felK = 2.5 11Hz
fA = 25°C

ffi

~

Av+ =

Av+ = 0V+ = +5.0V
VREF+ = 4.096V
VREF- = GND
felK
2.5 MHz

-55 -35-15 5 25 45 65 85 105125

4

REFERENCE VOLTAGE (V)

10-Blt Unsigned
Signal-to-Noise + THO Ratio
vs Input Signal Level
'iO'

-1

-2

o

CLOCK FREQUENCY (kH.)

70

-11-1-+-+-+-+-I--+-I-l
_2~~~~-L~-L-L~

o

CLOCK FREQUENCY (kH.)

M

t;

~

-10

-5

INPUT SIGNAL LEVEL (dB)

5

10

15

20

25

FREQUENCY (kHz)

30

35

-40

;;I -60
1;
in

-80

-100
50 100 150 200 250 300 350 400
FREQUENCY (kHz)

TLlH/11391-10

2-376

l>
C

Typical Reference Performance Characteristics

Load Regulation

.....
o

Line Regulation

\

-

- ..

SINKING \

>'r!i
<1

r;URCING

0
-1

CD

Output Drift
vs Temperature
(3 Typical ~arts)

Co)

.....

....L H-HH-t-t+tt+++~1-1;;1
t H+t-H-t-H-t-H-t-H-H-H

\

'- ~

(')

20 mV

~

-2

1

-3

-2
-3 -2 -1

-4
0

1

2

3

4

5

6

2

SINKING
SOURCING
OUTPUT CURRENT (rnA)

3

4

-SS -35-15 5

6

SUPPLY VOLTAGE ('I)

Available
Output Current
vs Supply Voltage
20
18

':<

16

.5

14

ii:l

12

!;

,

,

10

l/

8

/

:=
5

25 45 65 85 105 125

JUNCTION TEMPERATURE (OC)

, k'"
SUPPLY VOLTAGE

TL/H/11391-11

•

2-377

co
CO)
co

r-----------~--------~----------------------------------------------------~--__.

TRI-STATE Test Circuits and Waveforms

....
g
o

V+

cc

.-

V+

CO)

CO

o
....
o

t-....- .........

DATA
OUTPUT

GND

c

cc.
N
CO)

DATA
OUTPUT

,

'co

GND

TL/H/11391-12

o
....

VOH

±

H

90%

'

TLlH/11391-13

o

c

V+

cc

V+

t,.
V+

....
co
o
....

CO)

DATA
ADC10838 t-~~-. OUTPUT

g

GND

I~

cc

DATA
OUTPUT
,TLlH/11391-14
TLlH/11391-15

Timing Diagrams

DO - - - - - - - - - TRI-STATE - - - - - - - - -

TL/H/11391-16

FIGURE 2. 01 Timing

ClK

DI

DO - - - - TRI-STATE ---~

SARS

TRI-STATE TLlH/11391-17

FIGURE 3. 00 Timing
2-378

.--------------------------------------------------------------------.~

c

Timing Diagrams (Continued)

n
....
o
....
CD

Co)

~

CLK

c

n
....
o

CD

to)

j')
~

c

n
....

01

o

CD

Co)

.!'"

DO

~

c

n
....

TRI-STATE

o

CD

SARS

Co)

TLlH/11391-18

FIGURE 4. Delayed DO Timing

eLK

cs~\

~r=I'--~--

,:: ~".~--t-Ip-D------iFo--r-tsu---------~~_ _ _ _ _ _ _ _ _ _ _ _-J~
TL1H/11391-19

FIGURE 5. Hardware Power Up/Down Sequence

ClK

01

I----Ipo

TL/H/11391-20

FIGURE 6. Software Power Up/Down Sequence

2·379

CD

co .---------------------------------------------------------------------------------,

.~

....o
g

.-

Timing Diagrams (Continued)

011(

(f)

CO

elK

o

o.
~

~

(f)

CO

....o

DO

011(

SARS

oc,

....

~~

. ________________________

~~

~I~j--------------------J,----

(f)

co

o
.....

o
c011(

ANALOG
SI~HAl

'SAMPlED
SIGNAL

TL/H/11391-21

Note: If eli! is low during power up of the power supply voltages (AV+ and DV+) then Cll needs to go high for tcS(H)" The data out~ut after the first conversion is
invalid.
,,'
.
FI~URE

7.. ~pC10831 CS Low during Conversion

2·380

-I

~:

::J

I.Q

C

iii'

.,

I.Q
D)

3

til

1?
~

g.

ClK

t:



a

elK

::J

c:

~

cs

~I

Co>

DO

SARS

CJ)

I\)

ANALOG
SIGNAL

~~

~r-

SAMPLED
SIGNAL

IS

5,

----.
TUH/11391-23

FIGURE 9. ADC10831 Using CS to Delay Output of Data afer a Conversion has Completed
Note: If ~ is low during power up of the power supply voltages (AV+ and DV+) then ~ needs to go high for Ics(H). The date output aiter the first conversion is not valid.

-t

3"

S"
ea
C

iii"
ea

iii
3(I)

l'
a
""

ClK

~
Os

DI

III

c.>
c.>

DO

0>

SARS

ANALOG

~

SIGNAL

r-=

--

SAMPLED
SIGNAL

TL/H/11391-24

FIGURE 10. ADC10832, ADC10834 and ADC10838 Using CS to Delay Output of Data after a Conversion has Completed
Note: II CS is low during power up of the power supply voltages (AV+ and DV+) then CS needs to go high for tcS(H)' The data output after the first conversion is not valid.

8£80~:>a\f 't£8o~:>a\f '~£8o~:>a\f '~£8o~:>a\f

II

TABLE I. AOC10838 Multiplexer Address Assignment
MUXAddress
MAO

....
~
....
o
CO)

cc(

MA1

MA2

PU

SING!
DIFF

ODD!
SIGN

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

0
0

0

MA3

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

0
0
0
0

0'
0

0

1
1

0

0
0

1
1

0,

0

1
1
1
1

X

X

X

X

0

CH1

CHQ
SELO

0
0
0

,

MUX
MODE

MA"

SEL1

0

'

Channel Number
CH2

CH3

CH4

CH5

CH6

CH7

-

+
+

1

+
+

1

+

-

+
+

1

-

+

-

+

1

-

+
-

Single-Ended

-

+

1

1'
0
1

COM

1-

-

-

+

Differential

+,
-

+

-

+

1

Power Down (All Channels Disconnected)

TABLE II. ADC10834 Multiplexer Address Assignment
Channel Number'

MUXAddress
MAO

MA1

MA2

MA3

PU

SING!
OIFF

ODD!
SIGN

1
1
1
1

1
1
1
1

1
1
1
1

0

0
0

0

X

CHO'
SEL1

SELO

0
0

0

0

0

1

1

0
0

0

0

0

0
0
0

1
0

X

X

1

0
0
0

1
1

"

X

MUX
MODE

MA4
CH1

CH2

CH3

COM

-

+
+

-

-

+
+

1

+

-

-

+

1

+

-

-

+

Single-Ended

"

Differential

Power Down (All Channels Disconnected)

TABLE III. AOC10832 Multlp!exer Address Assignment
MUXAddress

Channel Number

MAO

MA1

MA2

PU

SING!
OIFF

ODD!
SIGN

SEL1

SELO

1
1

1
1

0
1

0
0

0
0

+

1
1

0

0

0
0

-

1

0
0

+

0

-

+

0

X

X

X

X

MA3

MA4
,CHO

2-384

CH1

COM

+

-

MUX
MODE

Single-Ended
Differential

Power Down (All Channels Disconnected)

Pin Descriptions
ClK

DI

DO

es

PD

SAAS

The clock applied to this input controls the successive approximation conversion time interval,
the acquisition time and the rate at which the
serial data exchange occurs. The rising edge
loads the information on the DI pin into the mUltiplexer address shift register. This address controls which channel of the analog input multiplexer (MUX) is selected. The falling edge shifts
the data resulting from the AID conversion out
on DO. CS enables or disables the above functions. The clock frequency applied to this input
can be between 5 kHz and 3 MHz.

CHO-CH7 These are the analog inputs of the MUX. A
channel input is selected by the address iliformation at the DI pin, which is loaded on the rising edge of ClK into the address register (see
Tables I-III).
The voltage applied to these inputs should not
exceed AV+ or go below V- by more than
50 mV. Exceeding this range on an unselected
channel will corrupt the reading of a selected
channel.
COM

This is the serial data input pin. The data applied
to this pin is shifted by ClK into the multiplexer
address register. Tables I through III show the
multiplexer address assignment.
The data 0utput pin. The AID conversion result
(DBO-SIGN) ,are clocked out by the falling edge
of ClK on this pin.
This is the chip select input pin. When a logic
low is applied to this pin, the rising edge of ClK
shifts the data on DI into the address register.
This low also brings DO out of TAl-STATE after
a conversion has been completed.
This is the power down inpLlt pin. When a logic
high is applied to this pin the AID is powered
down. When a low is applied the AID is powered up.
This is the successive approximation register
status output pin. When CS is high this pin is in
TAl-STATE. With
low this pin is active high
when a conversion is in progress and active low
at all other times.

AV+,
DV+

es

V-

DGND
AGND

2-385

This pin is another analog input. When the analog multiplexer is single ended this input serves
as the zero reference level for inputs CHO-CH7
(see Tables I-III). COM can serve as a "pseudo
ground" that has an input voltage range of AV+
+ 50 mV to V- - 50 mV. In most cases, COM
will be grdunded. When the MUX is set in the
differential pairs mode, COM is not used and
may be grounded.
This is the positive analog voltage reference input. In order to maintain accuracy, the voltage
range VREF (VREF = VREF+-VREF-) is
0.5 Voc to 5.0 Voc and the voltage at VREF+
cannot exceed AV+' +50 mV.
The negative voltage reference input. In order to
maintain accuracy, the voltage at this pin must
not go below GND - 50 mV or exceed AV+
+ 50 mV. VREF- must always be less than
VREF+·
These are the analog and digital positive power
supply pins. These pins should be tied to the
same power supply and bypassed separately.
The operating voltage range of AV+ and DV+
is 4.5 Voc to 5.5 Voc.
This is the negative analog supply pin. The operating voltage range of V- is -4.5V to -5.5V.
This supply pin needs to be bypassed with
0.1 p.F ceramic and 10 p.F tantalum capacitors
to the system analog ground.
This is the digital ground pin.
This is the analog ground pin.

:r:IC
o......
Q

CD
W

......

:r:-

IC

o
......
Q
CD
W

~

:r:-

IC

o
......
Q

CD
W

~"".

:r:-

IC

o
......
Q

CD
W
CD

~ .-----------------------------------------------------------~------~
CO)
~

o.-

g
CI:
..;CO)
~

o.-

o

cc(

~
~

'0

.-

g
c.c

Applications Hints

The ADC10S31/2/4/S use 'successive approximation to
digitize an analog input voltage. The DAC portion of the AID
converters uses a capacitive array and a resistive ladder
structure. The structure of the DAC allows a very simple
switching scheme to provide a versatile analog input multiplexer. This structure also provides a sample/hold. The
ADC10S31/2/4/S have a 2.5V CMOS bandgap reference.
The serial digital I/O interfaces to MICROWIRE and
MICROWIRE +.

device during power down. CMOS logic levels will give the
least amount of current drain (3 p,A). TIL logic levels will
increase the total power down current dra,in to 300 p,A.
These devices'have resistive reference ladders which draw
600 p,A with a 2.5V reference voltage. The internal band
gap reference voltage shuts down when power down is activated. If an external reference voltage is used, it will have to
be shut down to minimize the total current drain of the device.

1.0 DIGITAL INTERFACE
There are two modes' of operation. The fastest throughput
rate is obtained when
is' kept low during a conversion.
The timing diagrams in Figures 7 and 8 show the operation
of the devices in this mode. CS must be taken high for at
least tcS(H) (1 CLK) between conversions. This is necessary
to reset the internal logic. Figures 9 and 10 show the operation of the devices when
is taken high while the
:ADC10S31/2/4/S is converting.
may be taken high during the conversion and kept high Indefinitely to delay the
output data. This mode simplifies the interface to other devices while the ADC10S31/2/4/S is busy converting.

2.0 ARCHITECTURE ,
Before a conversion is started, during the. analog input sampling period, ,{tAl, the sampled data comparator is zeroed.
As tlie comparator is being zeroed the channel assigned to
be the positive input is connected to the AID's input capacitor. (The assignmentprocedure is e1

"C

"2-

(;'
D)

0'
::l
til

::E:

5'

r--------

ur

------------------------------~--------------------~

Analog MUX

'§

32C

CHO

::>

gc

CHI

(D

B

CH2
CH3
CH.

~

CHS

~I

CH6
CH7

COM

VREF

..
: I

.- -----.I
I
I
I

-

.I.

II
II
II
II
II
II

103C

II.SR
2R

VREF +

FROU
MULTIPLEXER
ADDRESS
DECODER

DBO

DBI

DB2

DB3

DB4

DBS

DB6

DB7

DBB

DB9

FROU SAR

SIGN

FROM
COIITROL
LOGIC

TO
SAR
TL/H/11391-25

FIGURE 11. Detailed Diagram of the ADC10838 DAC and Analog Multiplexer Stages

8£80~!)a\f 't£80~!)a\f '~£80~!)a\f '~£80~!)a\f

II

Applications Hints (Continued)
output noise can be obtained by increasing the output capacitance. A 100 ",F capacitor will yield a typical noise floor
of 200 nVI JHz. The pseudo-differential and differential multiplexer modes allow for more flexibility in the analog input
voltage range since the "zero" reference voltage is set by
the actual voltage applied to the assigned negative input
pin.
In a ratiometric system (Agure 138), the analog input voltage is proportional to the voltage used for the AID reference. This voltage may also be the system power supply, so
VREF+ can also be tied to AV:t-. This technique relaxes the
stability requirements of the system reference as the analog
input and AID reference move together maintaining the
same output code for a given input condition.

3.0 APPLICATIONS INFORMATION
3.1 Multiplexer Configuration
The design. of these converters utilizes a sampled-data
comparator structure, which allows a differential analog input to be converted by the successive approximation routine.

....

C")

CD

o....

o
~

The actual voltage converted is always the difference between an assigned" +" input terminal and a "-" input terminal. The polarity of each input terminal or pair of input
terminals being converted indicates which line the converter
expects to be the most positive.
A unique input multiplexing scheme has been utilized to pro, vide multiple analog channels. The input channels can be
software configured into three modes: differential, singleended, or pseudo-differential. Figure 12 iliustrates the three
modes using the 4-channel MUX of the ADC10834. The
eight inputs of the ADCl 0838 can also be configured in any
of the three modes. The single-ended mode has CHO-CH3
assigned as the positive input with COM serving as the negative input. In the differential mode, the ADC10834 channel
inputs are grouped in pairs, CHO with CHl and CH2 with
CH3. The polarity assignment of each channel in the pair is
interchangeable. Finally, in the pseudo·differential mode
CHO-CH3 are positive inputs referred to COM which is now
a pseudo-ground. This pseudo-ground input can be set to
any potential within the input common-mode range of the
converter. The analog signal conditioning required in transducer-based data acquisition systems is significantly simplified with this type of input flexibility. One converter package
can now handle ground-referred inputs and true differential
inputs as well as signals referred to a specific voltage.
The analog input voltages for each channel can range from
50 mV below V- to 50 mV above V+ = DV+ = AV+
without degrading conversion accuracy. If the voltage on an
unselected channel exceeds these limits it may corrupt the
reading of the selected channel.

For absolute accuracy (Figure 13b), where the analog input
varies between very specific voltage limits, the reference pin
can be biased with a time- and temperature-stable voltage
source that has excellent initial accuracy. The LM4040,
LM4041 and LM185 references are suitable for use with the
ADC10831 1214/8.
The minimum value of VREF (VREF = VREF+ -VREF-) can
be quite small (see Typical Performance Characteristics) to
allow direct conversion of transducer outputs providing less
than a 5V output span. Particular care must be taken with
regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the
increased sensitivity of the converter (1 LSB equals VREFI
1024).
3.3 The Analog Inputs
Due to the sampling nature of the analog inputs, at the clock
edges short duration spikes of current will be seen on the
selected assigned negative input. Input bypass capacitors
should not be used if the source resistance is greater than
1 kn since they will average the AC current and cause an
effective DC current to flow through the analog input source
resistance. An op amp RC active lowpass filter can provide
both impedance buffering and noise filtering should a high
impedance signal source be required. Bypass capacitors
may be used when the source impedance is very low without any degradation in performance.

3.2 Reference Considerations
The voltage difference between the VREF+ and VREF- .inputs defines the analog input voltage span (the difference
between VIN(Max) and VIN(Min» over which 1023 positive
and 1024 negative possible output codes apply.

In a true differential input stage, a Signal that is common to
both "+ " and "-" inputs is canceled. For the
ADC10831 12/4/8, the positive input of a selected channel
pair is only sampled once before the start of a conversion
during the acquisition time (tA)' The negative input needs to
be stable during the complete conversion sequence because it is sampled before each decision in the SAR sequence. Therefore, any AC common-mode signal present
on the analog inputs will not be completely canceled and
will dause some conversion errors. For a sinusoid commonmode Signal this error is:

The value of the voltage on the VREF+ or VREF- inputs
can be anywhere between AV+ + 50 mV and GND
-50 mY, so long as VREF+ is greater than VREF-' The
ADC10831/2/4/8 can be used in either ratiometric applications or in systems requiring absolute accuracy. The reference pins must be connected to a voltage source capable
of driving the minimum reference input resistance of 5 kn.
The
internal
2.5V
bandgap
reference
in
the
ADCl 0831/2/4/8 is available as an output on the VREFOut
pin. To ensure optimum performance this output needs to
be bypassed to ground with 100 ",F aluminum electrolytic or
tantalum capacitor. The reference output can be unstable
with capacitive loads greater than 100 pF and less than
100 ",F. Any capacitive loading less than 100 pF and
greater than 100 ",F will not cause oscillation. Lower

VERROR(max) = VPEAK (2 7T fCM) (Ie)
where fCM is the frequency of the common-mode signal,
VPEAK is its peak voltage value, and tc is the AID's conversion time (Ie = 12/fCLK). For example, for a 60 Hz common-mode signal to generate a % LSB error (0.61 mY) with
a 4.8 "'S conversion time, its peak value would have to be
approximately 337 mY.

2-388

l>
C

Applications Hints (Continued)

o
....
o
co
Co)

4 Single-Ended
·CHO

CHO. {
CHI

CHI
CH2
CH3
COM

+

4 PsuedoDifferential

2 Differential

AOC10834

+(-)

CHO

-(+)

CHI
AOC10834

CH2.:{
CH3

+(~)
-(+)

AOC10834

2 Single-Ended·
and 1 Differential.
CHO {
CHI

+(-)
-(+) AOC10834

CH2

CH2

+

CH·3

CH3
COM

+

COM

TL/H/11391-26

FIGURE 12. Analog Input Multiplexer Options

a. Ratiometric USing the Internal Reference
. +5V

.. ~

-- 1\ ~ r72_6_n~~....Ii.:-....
Av+ oV+
~~t-+-+--+---I CHO

lOOI'F

+

~.H-+--'" CHI

<.......- ... CH3

TL/H/11391-27

b. Absolute Using a ± 4.096V Span

·VREF + AV+

.,,;.H------t CHO
LM91404.1

lOOk·

"';'''''''----1 CHI
. ·AOC10832
COM

Lt.tC6081

·0.1 % Resistors

TL/H/11391-28

FIGURE 13. Different Reference Configurations

2-389

....

Applications Hints (Continued)
3.5 The Input Sample and Hold

3.4 Optional Adjustments
3.4.1 Zero Error
The zero erro~ of the AID converter relates'to'the location
of the first riser of the transfer function (see Figure 1) and
can be measured by grounding the minus input and applying
a small magnitude voltage to the plus input. Zero error is the
difference between actual DC input voltage which is necessary to just cause an output digital code transition from
000 0000 0000 to 000 0000 0001 and the ideal1f2 LSB value
(1f2 LSB = 2.0 mV for VREF = + 4.096V).
The zero error of the AID does not require adjustment. If
the minimum analog input voltage value, VIN(Min), is not
ground, the effective "zero" voltage can be adjusted to a
convenient value. The converter can be made to output an
all zeros digital code for this minimum input voltage by biasing any minus input to VIN(Min). This is useful for either the
differential or pseudo-differential input channel configurations.

The ADC10831/2/4/8's sample/hold capacitor is implemented in the capacitor array. After the channel address is
loaded, the arrliY is switched to sample the selected positive
analog input. The sampling period for the aSSigned positive
" input is maintained for the duration of the acquisition time
(tA) 4.5 clock cycles.
This acquisition window of 4.5 clock cycles is available to
allow the voltage on the capacitor array to settle to the positive analog input voltage, Any change in the analog voltage
on a selected positive input before or after the acquisition
window will not effect the A/D conversion result.
In the simplest case, the array's acquisition time is determined by the RON (3 kO) of the multiplexer switches, the
stray input capacitance CSl (3.5 pF) and the total array (CLl
and stray (CS2) capacitance (48 pF). For a large source
resistance the analog input can be modeled as an RC network as shown in Figure 14. The values shown yield an
acquisition time of about 1.1 ".S for 1O-bit unipolar or 10-bit
plus sign accuracy with a zero-to-full-scale change in the
input voltage. External source resistance and capacitance
will lengthen the acquisition time and should be accounted
for. Slowing the clock will lengthen the acquisition time,
thereby allowing a larger external source resistance.

3.4.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is l1f2 LSB down from the desired
analog full-scale voltage range and then adjusting the VREF
voltage (VREF = VREF+ - VREF-) for a digital output code
changing from 011 1111 1110 to 011 1111 1111. In bipolar
signed operation this only adjusts the positive full scale' error.
3.4.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an anaiog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A plus input voltage which
equals this desired zero reference plus 1f2 LSB is applied to
selected plus input and the zero reference voltage at the
corresponding minus input should then be adjusted to just
obtain the 000 0000 0000 to 000 0000 0001 code transition.
The full-scale adjustment should' be made [with the proper
minus input voltage applied] by forcing a voltage to the plus
input which is given by:

TLlH/11391-29

FIGURE 14. Analog Input Model
The signal-to-noise ratio of an ideal AID is the ratio of the
RMS value of the full scale input signal amplitude to the
value of the total error amplitude (including noise) caused
by the transfer function of the ideal A/D. An ideal 10-bit plus
sign AID converter with a total unadjusted error of 0 LSB
would have a signal-to-(noise + distortion) ratio of about 68
dB, which can be derived from the equation:
S/(N + D) = 6.02(n) + 1.8

VIN( +) fs adj = VMAX - 1.5 [ (VMAX 2~ VMIN) ]

where S/(N

where VMAX equals the high end of the analog input range,
VMIN equals the low end (the offset zero) of the analog
range. Both VMAX and VMIN are ground referred. The VREF
(VREF = VREF+ - VREF-) voltage is then adjusted to provide a code change from 011 11111110 to 011 1111 1111.
Note, when using a pseudo-differential or differential multiplexer mode where VREF+ and VREF- are placed within
the V+ and GND range, the individual values of VREF and
VREF - do not matter, only the difference sets the analog
input voltage span. This completes the adjustment procedure.

2-390

+

D) is in dB and n is the number of bits.

l>

e

Applications Hints (Continued)
+5V

+5V

DV'

VIN

470n

R2

R3

'"
CD
0

+

0
C»
Co)

!"
l>

CD

e

0

u
c

U
c

....0

0

'"

'"

(R1

....

CD
......
....
......
....

:::'"

:::-

Co)

l>
e
0

DV'

VIN

CD
......
...
......
....

R1

....
0
C»
....
0

C»
Co)

R2)/lR3 ,;; 1k

TL/H/11391-30

~

l>

e

Note 1: Diodes are 1N914.

....
0

0

Note 2: The protection diodes should be able to withstand the output current of the op amp under current limit.

FIGURE 15. Protecting the Analog Inputs

2-391

C»
Co)

C»

~

~

~

,--------------------------------------------------------------------------------,

til

Nat ion a I S e m i con due to r

ADC 1061 1O-Bit High-Speed p.P-Compatible
A/D Converter with ,Track/Hold Function '
General Description

Features

Using a modified half-flash conversion technique, the 10-bit
ADC1061 CMOS analog-to-digital converter offers very fast
conversion times yet dissipates a maximum of only 235 mW.
The ADC1061 performs a 10-bit conversion in two lowerresolution "flashes", thus yielding a fast AID without the
cost, power dissipation, and other problems associated with
true flash approaches.
The analog input voltage to the ADC1061 'is tracked and
held by an internal sampling circuit. Input signals at frequencies from DC to greater than 160 kHz can therefore' be digitized accurately without the need for an external sampleand-hold circuit.

•
•
•
•
•
•

For ease of interface to microprocessors, the ADC1 061 has
been designed to appear as a memory location or I/O port
without the need for external interface logiC.

1.8 /Ls maximum conversion time to 10 bits
Low power dissipation: 235 mW (maximum)
Built-in track-and-hold
No externill clock 'required
Single + 5V supply
No missing codes over temperature

Applications
.', Waveform digitizers
• Disk drives
• Digital signal processor front ends
• Mobile telecommunications

Simplified Block and Connection Diagrams
DB9 (USB)

Dual-In-Llne Package

DBB
DB7
OUTPUT
LATCH
AND
TRJ-STATE
BUFFERS

DBB
DBS
DB4
DB3
DB2
DBl
DBD (LSB)

iN'f

DBO (LSa)

DVec

iNT
S/H

DBI

RD

DB3

DB2

cs

DB4

AVec

DBS

VREFVIN

DB6

VREF+
GND

DB7
9

12

DB8

10

11

DB9 (MSB)

5/H
TL/H/l0559-2

Order Number
ADC1061CIJ, ADC1061CIN,
ADC1061CIWM or ADC1061CMJ
See NS Package J20A,
M20BorN20A

Ordering Information
Industrial (-40"C ,;;; TA ,;;; 85·C)
ADC1061CIJ

Package
J20A

ADC1061CIN

N20A

ADC1061CIWM

M20B

Military (-55·C ,;;; TA';;; 125"C)
ADC1061CMJ

TL/H/l0559-1

Top View

Package
J20A

2-392,

~

C

Absolute Maximum Ratings

(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-D.3Vto +6V
SupplyVoltage(V+ = AVee = DVecl
-D.3VtoV+ +D.3V
Voltage at any Input or Output
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)

SmA

Power Dissipation (Note 4)

2DmA
87SmW

ESD Susceptibility (Note S)

1SDDV

SOldering 1i1(orm~tio~ (Note 6)
N Package (10. seconds)
J Package (1D'seconds)
SO ~ackage (Note 6):
Vapor ~has~ (60 ,seconds)
Infrared (1S seconds)

26D'C
3DD'C
21S'C
220'C

Junction Te~perature, Tj
'
\'
'
' Storage Temperature Range

+1SD'C
-6S'C to + 1SD'C

Opei'atirigRatings (Notes 1 & 2)
Temperature Range
ADC1D61CIJi ADC1D61CIN,
ADC1D61CIWM
ADC1061CMJ

TMIN ,;; TA ,;; TMAX
-:-4D'C';; TA';; +8S'C
-SS'C ,;; TA ,;; + 12S'C

Supply Voltage Range

4.SVtoS.SV

Converter Characteristics

The following specifications apply for V+ = +5V, VREF(+) = 5V, and VREF(-)
limits apply for T A = TJ = T MIN to T MAX; a" other limits TA = TJ = 25'9'
Symbol

Parameter

Conditions

'7'

GND unless otherwise specified. Boldface

Ty~lcal
(Note 7)

Resolution

Limit
(Note 8)

Units
(Limit)

10

Bits

Total Unadjusted Error

±1.D

±2.0

LSB (Max)

Integral Linearity Error

±O.3

±1.5

LSB (Max)

±1.0

LSB (Max)

±D.1

:i:,1.0

LSB (Max)
LSB (Max)

Differential Linearity Error
Offset Error
Fu"scale Error

±D.5

±1.0

RREF

Reference Resistance

0..65

0.4

kO(Min)

RREF

Reference Resistance

0..65

0 ••

kO(Max)

VREF(+)

VREF( +) Input Voltage

Y+ + 0.05

V (Max)
V (Min)

VREFI-)

VREIl-tlnput Voltage

GND - 0.05

VREF(+)

VREF( + ) Input Voltage

YRBF(-)

V (Min)

VREF(-)

VREF( -) Input Voltage

YREF(-)

V (Max)

VIN

Input Voltage

V+ + 0.05

V (Max)

VIN

Input Voltage
Analog Input Leakage Current

es = V+, VIN = V+
CS

Power Supply Sensitivity

= V+, VIN = GND

V+ = 5V ±5%
VREF = 4.7SV

2-393

....
....

C')

GND - 0.05

V (Min)

0..0.1
0..0.1

3
-3

",A (Max)
",A (Max)

±D.125

±0.5

LSB

~

....
CD
o
....
g
cc

DC Electrical Characteristics
The following specifications apply for V+ = +5V, VREF(+) = 5V, and VREF(->= GNDlmless otherwise specified. Boldface
limits apply for T A = T J = T Mit'" to TMAXi all other limits TA = TJ' = 25°C.
Symbol

Parameter

Conditions

;

Typical
,(Note 7)

Limit
(Note 8)

Units
(Limits)

VIN(1)

Logical "1" Input Voltage

V+ =,5.25V

2.0

V (Min)

VIN(O)

Logical "0" Input Voltage

V+ = ~t75V

0.8

V (Max)

IIN(1)

Logical "1" Input Current

VIN(1) = 5V

0.005

1.0

/LA (Max)

IIN(O)

Logical "0" Input Current

VIN(O) = OV

-0.005

-1.0

/LA (Max)

VOUT(1)

Logical "1" Output Voltage- -

V+ = 4.75V lOUT = -360/LA
V+ = 4.75V lOUT = -10/LA

2.4
4.5

V (Min)
V (Min)

VOUT(O)

Logical "0" Output Voltage,

V+ = 4.75V lOUT = 1.6 mA

0.4

V (Max)

lOUT

TRI·STATE~

VOUT = 5V
VOUT = OV

0.1
-0.1

SO
-SO

/LA (Max)
/J,A(Max)

Dice

DVce Supply Current

CS = WR = RD = 0

0.1

2

mA(Max)

Alcc

AVcc Supply Current

CS = WR = RD = 0

30

45

mA(Max)

Output Current

AC Electrical Characteristics
The following specifications apply for V+ = +5V, tr = t, = 20 ns, VREF(+)= 5V, and VREF(-) = GND unless otherwise
specified. Boldface limits apply for TA = TJ =TMIN to TMAXi all other limits TA = TJ = 25°C.
Symbol
tCONV

Parameter
Conversion Time from Rising Edge
-of 8/H to Falling Edge of TNT

Conditions
Mode 1

Typical
(Note 7)

Limit
(Note 8)

Units
(Limits)

1.2.

1.8

JLs (Max)

1.B

2.4

/Ls (Max)

20

50

ns(Max)

tCRD + 50

ns(Max)

250

ns(Max)

20

50

ns(Max)

10

50

ns(Max)

tC~D

Conversion Time for MODE 2
(RDModeJ -.

Mode 2

tACC1

Access Time (Delay from Falling
Edge of RD to Output Valid)

Mode1;CL = 100pF

tACC2

Access Time (Delay from Falling
Edge of F!D to Output Valid)

Mode 2; CL = 100 pF

tSH

Minimum Sample Time

(Figure 1); (Note 9)

t1H,tOH

TRI·STATE Control (Delay from Rising
Edge of RD to High.Z State)

RL = 1k,CL = 10pF

tlNTH

-pelay from Rising Edge of RD
to Rising Edge of INT

tiD

Delay from INT to Output Valid

20

' 50

ns(Max)

tp

Delay from End of Conversion
to Next Conversion

10

20

ns(Max)

SR

Slew Rate for Correct
Track·and·Hold Operation

2.5

CL = 100pF

2·394

VIJLs

AC Electrical Characteristics

(Continued)
The following specifications apply for V+ = +5V,lr = tf = 20 ns, VREF(+) = 5V, and VREF(-)
specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25'C.
Parameter

Symbol

Conditions

Typical
(Note 7)

=

GND unless otherwise

Limit
(NoteS)

Units

CVIN

Analog Input Capacitance

35

pF

COUT

Logic Output Capacitance

5

pF

CIN

Logic Input Capacitance

5

pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings Indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

'

Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V- or VIN > V+) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperaturas and Is dictated by TJMAX; 9JA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po ~ (TJMAX - T,v19JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX = IS0'C, and the typical thermal resistance (9J,v when board mounted is 47'C/W for the plastic (N) peckage, 85'C/W for the ceramic (J) package,
and 65'C/W for the small ouiline (WM) package.
Note 5: Human body model, 100 pF discharged through a 1.5 kO resistor.
Note 6: See AN-450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section tilled "Surface Mount" found in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at 25'C and represent most likely parametric norm.
Note 8: Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 9: Accuracy may degrade if tSH is shorter than the value specified.

TRI-STATE Test Circuits and Waveforms
Vee

y

DATA
ADC10611-.....
I -......-~ OUTPUT

l. i_

CL

RL

~

TL/H/l0559-4
TL/H/l0559-3

Vee

y

ROO-

-=:j t:.

Vee

~

R

L

DATA
OUTPUT

ADCI061

~

-

Vee
Ir
. 50%.I,f 90%
GND---f 10%

i--

rlOH
DATA Vee ~,..OUTPUT VOL
10%

-.J

CL

TL/H/l0559-6
TL/H/l0559-5

2-395

.... r------------------------------------------------------------------------------------------,

8

~

Timing Diagrams

',--_..;..JI

,

,

S/H --------~~t~~'-------------------------------------------

,

,

"
,
------------------,-,'.,--------------------~~~------~),"--------.

','------

~

,

----------------~:~--------~\:

i---

lCONV - - - : '"----__

i--------~ii_', ' ,

~'"""!".....;.- I1H·IoH

--------,----------------..------:.<, J >-----IACe1 -:: '

000-009

;._ tiNTH

i!=,'
__

TLlH/l0559-7

FIGURE 1. Mode 1. The conversion time (tCONV) Is determined by the Internal timer.

\. --___ ---

\".'!-:___________________________--______ 1
.J

Ics --: :S/H and iiii

'r.. _----~'"--------------------------,~-----,(-':
,
\ ' :" ),','------------Ip

"". - - - - - - !cRD

,iNT

.: : _ --:
~D-,

;._ tiNTH

,i

:..

DOO-D09

.:

~

>--------I

--------_,..~~~~~~~~~~~~....-De.-ta-Va-n-d...

TL/H/l0559-B

FIGURE 2. Mode 2 (RD Mode). The conversion time (tCRO) Includes
the sampling time, and is determined by the internal timer.

2·396

Typical Performance Characteristics
Zero (Offset) Error
vs Reference Voltage
1.0

...
~
...

o.a

= +5V

...

';j'

~

...
...15
...15~

\

Q.6

0

~

......c

1.0

I I
AVec = DVcc
TJ - 2S"C

';j'

15

Linearity Error vs
Reference Voltage

""-

OA

N

0.2

........

z

::::;

....... ~

AVec = DVec - +5V
TJ 2S"C

OB

=

0.6

r-

OA

~

0.2
0.0

0.0
I

2

345

4

I

REFERENCE VOLTAGE, VREF+ - VREF- (V)
TL/H/l0559-9

TUH/l0559-10

Mode 2 Conversion Time
vs Temperature

Mode 1 Conversion Time
vs Temperature
~

1.6

.3

IA

j

..r

1.2

i!!

1.0

z

o.a

-AVec

2.2

];2.D

JIB

:

-75

i!!

= DVec = vREF = +5V

z

0

25

so

IA
1.2

AVcc

= DVcc = VREF = +5V

I ~~
8

Q.6

'"

OA

~
-so -25

....... r-

..r 1.6

I:
~

5

REFERENCE VOLTAGE, VREF+ - VREF_ (V)

75 100 125

JUNCTION TEMPERATURE, TJ ("C)

D.2
0.0
-75

-so -25

0

25

so

75 100 125

JUNCTION TEMPERATURE, TJ ("C)
TUH/l0559-11

TUH110559-12

Pin Descriptions
Symbol
DVec,
AVec
(1,6)

iNT (2)

Symbol

Function
These are the digital and analog positive
supply voltage inputs. They should
always be connected to the same
voltage source, but are brought out
separately to allow for separate bypass
capaCitors. Each supply pin should be
bypassed with a 0.1 ",F ceramic
capaCitor in parallel with a 10 ",F
tantalum capacitor.

'CS(5)

This is the active low interrupt output.
INT goes low at the end of each
conversion, and returns to a high state
following the rising edge of RD.

S/H(3)

This is the Sample/Hold control input.
When this pin is forced low, it causes
the analog input Signal to be sampled
and initiates a new conversion.

RD(4)

This is the active low Read control input.
When this pin is low, any data present in
the ADC1 061's output registers will be
placed on the data bus. In Mode 2, the
Read signal must be low untillNT goes
low. UntillNT goes low, the data at the
output pins will be incorrect.
2-397

Function
This is the actilie low Chip Select control
input. This pin enables the 8/H and RD
inputs.

VREF-,
VREF+
(7,9)

These are the reference voltage inputs.
They may be placed at any voltage
between GND - 50 mV and Vee +
50 mV, but VREF + must be greater than
VREF -. An input voltage equal to
VREF - produces an output code of 0,
and an input voltage equal to VREF + 1LSB produces an output code of 1023.

VIN(S)

This is the analog input pin. The
impedance of the source should be less
than 5000. for best accuracy and
conversion speed. To avoid damage to
the ADC1 061, VIN should not be
allowed to extend beyond the power
supply voltages by more than 300 mV
unless the drive current is limited. For
accurate conversions, VIN should not
extend more than 50 mV beyond the
supply voltages.

-~--------------------------------~

8-

gC

connected, in groups, to the sixteen comparators at the
right of the diagram.

Pin Descriptions (Continued)
Symbol
GND (10)

DBO-DB9

Function
This is the power supply ground pin. The
ground pin should be connected to a
"clean" ground reference point.
These are the TRI-STATE output pins.

On the left side of the diagram is a' string of seven resistors
connected between VREF + - VREF _. Six comparators
compare the input voltage with the tap voltages on the resistor string to.provide an estimate of the input voltage. This
estimate is then used to control the multiplexer that connects the MSB Ladder to the sixteen comparators on the
right. Note that the comparators on the left needn't be very
accurate; they simply provide an estimate of the input voltage. Only the sixteen comparators on the right and the six
on the left are necessary to perform the initial six-bit flash
conversion, instead of the 64 comparators that would be
required using conventional half-flash methods.
To perform a conversion, the estimator compares the input
voltage with the tap voltages on the seven resistors on the
left. The estimator decoder then determines which MSB
Ladder tap points will be connected to the sixteen comparators on the right. For example, assume that the estimator
determines that VIN is between 11/16 and 13/16 of VREF.
The estimator decoder will instruct the comparator mux to
connect the 16 comparators to the taps on the MSB Ladder
between 10/16 and 14/16 of VREF. The 16 comparators
will then perform the first flash conversion. Note that since
the comparators are connected to Ladder voltages that extend beyond the range indicated by the estimator circuit,
errors in the estimator as large as 'Aa of the reference voltage (64 LSBs) will be corrected. This first flash conversion
produces the six most Significant bits of data.

(11-20)

Fu nctional Description
The ADC1061 digitizes an analog input signal to 10 bits accuracy by performing two lower-resolution "flash" conversions. The first flash conversion provides the six most significant bits (MSBs) of data, and the second flash conversion
provides the four least significant bits (LSBs).
Figure 3 is a simplified block diagram of the converter. Near
the center of the diagram is a string of resistors. At the
bottom of the string of resistors are 16 resistors, each of
which has a value 1/1024th the resistance of the whole
resistor string. These lower 16 resistors (the LSB Ladder)
therefore have a voltage drop of 16/1024, or 1/64th of the
total reference voltage (VREF+ - VREF..,.) across them.
The remainder of the resistor string is made up of eight
groups of eight resistors connected in series. These comprise the MSa Ladder. Each section of the MSB Ladder
has 118th of the total reference voltage across it, and each
of the MSB 'resistors has 1/64th of the total reference voltage across it. Tap pOints across all of these resistors can be
VIN

~-------------------------,

VRU+--~~-+---------t------I
8
14/16

13/16

8
~~!""--I ~

ffi

~12/161

11/16

CD

!!I

2

:

4/16 1

9/16
DBO-DB9

7/16

10

16/1024

5/16.

16

3/16
1/1024

VRU- __....IL..-__________________.....
TL/H/10559-13

FIGURE 3. Block Diagram of the Modified Half-Flash Converter Architecture

2-398

Functional Description

MODEl
In this mode, the S/H pin controls the start of conversion.
S/H is pulled low for a minimum of 250 ns. This causes the
comparators in the "coarse" flash converter to become active. When S/H goes high, the result of the coarse conversion is latched and the "fine" conversion begins. After approximately 1.2
(1.8
maximum), jjij'j' goes low, indicating that the conversion results are latched and can be read
by pulling RD low. Note that CS must be low to enable S/H
or RD. CS is internally "ANDed" with the sample and read
control signals; the input voltage is sampled when CS and
S/H are low, and is read when CS and RD are low.

(Continued)

The remaining four LSBs may now be determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input voltage (as determined by the first flash) is subtracted
from the input voltage and compared with the tap points on
the sixteen LSB Ladder resistors. The result of this second
flash conversion is then decoded, and the full 10-bit result is
latched.

,..S

Note that the sixteen comparators used in the first flash
conversion are reused for the second flash. Thus, the halfflash conversion techniques used in the ADC1061 needs
only a small fraction of the number of comparators that
would be required for a traditional flash converter, and far
fewer than would be used in a conventional half-flash approach. This allows the ADC1061 to perform high-speed
conversions without excessive power drain.

,..S

MODE 2
In Mode 2, also called "RD mode", the S/H and RD pins
are tied together. A conversion is initiated by pulling both
pins low. The ADC106l samples the input voltage and
causes the coarse comparators to become active. An internal timer then terminates the coarse conversion and begins
the fine conversion.
About 1.8 ,..s (2.4
maximum) after S/H and RD are
pulled low, INT goes low, indicating that the conversion is
complete. Approximately 20 ns later the data appearing on
the TRI-STATE output pins will be valid. Note that data will
appear on these pins throughout the conversion, but will be
valid only after INT goes low.

Applications Information

,..S

1.0 Modes of Operation
The ADC1061 has two basic digital interface modes. These
are illustrated in Figure 1 and Figure 2.

cs
5

~------~--~~--~~--~------'11

DB9 (MSB)

8

vIN----1
GND 10

ADC1061

7

VREF+

+

+ ,....:::::....+---+~=-~~-- +5V

10),Y·'J1.F 10Jl.Y·,)'F¥D.,)'F
TL/H/1D559-14

FIGURE 4. Typical connection. Note the multiple bypass capaCitors on the reference
and power supply pins. If VREF - is not grounded, it should also be bypassed to
ground using multiple capaCitors (see 5.0 "Power Supply Considerations").

2-399

'

8
....
i....

ir-------------------------------------------~

....

(.)

Q

c:c

2.0 Reference Considerations

achieved at the,l11inimum sample time. If the sampling time
, i sincreased, the source impedance can be 'larger. If a signal
The ADC1061 has two reference inputs. These inputs,
source has a high output impedance, its output should be
VREF+ and VREF-, are fully differential and define the zero
buffered with an operational amplifier. The operational amto ftill-scale range of the input sig!1al, The reference inputs
plifier's output should be well-behaved when driving a
switched 35 pF/600n load. Any ringing or voltage shifts at
can be connected to span the entire supply voltage range
(VREF- = OV, VREF+ = Vee) for ratiometric applications,
the op amp's output during the sampling period'can result in
or they can be con!1ected to di,fferent voltages (as 19n9 as
conversion errors.
they are between ground and VcClwhen other input spans
are, required. Reducing the overall VREF span to less than
Correct conversion results will be obtained for input volt5V increases the sensitivity of the converter (e.g., if VREF =
ages greater than GND - 50 mV and less than V+ +'
2V, then 1LSB = 1.953 mVJ. Note, however, that linearity
50 mV. Do not allow the signal source t6 drive the analog
and offset errors become larger when lower reference voltinput pin more than 300 mV higher than AVec and DVcc,'or
ages are used. See the Typical Performance Curves ,for
more than 300 mV lower than GND.lf the analog input pin is
more information. Reference voltages less than 2V are, not
forced beyond these voltages, the current flowing through
recommended.
the pin ShOlild be limited to 5 mA or less to avoid permanent
damage to the ADC10S1.
In most applications, VREF- will simply be connected to
ground, but it is often useful to have an input span that is
4.0 Inherent Sample-and-Hold
offset from ground. This situation is easily accommodated
Because
the ADC1 OS1 samples the input signal once during
by the reference configuration used in the ADC10S1.
each conversion, it is capable of measuring relatively 'fast
VREF- can be connected to a voltage other than ground as
input Signals without the help of an externa,l !1ample-hold. In
long as, the reference for this pin is capable of sinking cura conventional successive-approximation AID converter,
rent. If VREF- is connected to a voltage ,other than ground,
regardless of speed, the input signal must be stable to betbypass it with multiple capacitors.
ter than ± % LSB during each conversion cycle or signifiSince the resistance between the two reference inputs can
cant errors will result. Consequently, even for many relativebe as low as 400n, the voltage source driving the reference
ly slow input Signals, the signals must be externally sampled
inputs should have low output impedance. Any noise on eiand held constant during each conversion.
ther reference input is a potential cause of conversion erThe ADC10S1 can perform accurate conversions of input
rors, so each of these pins must be supplied with a clean,
Signals at frequencies from DC to greater than 1S0 kHz
low noise voltage source. Each reference pin should norwithout the need for external sampling circuitry.
mally be bypassed with a 10 JIoF tantalum and a 0.1 JIoF
ceramic capaCitor. More bypassing may be necessary in
some systems.
The choice of reference voltage source will depend on the
requirements of the system. In ratiometric data acquisition
systems with a power supply-referenced sensor, the reference inputs are normally connected to Vee and GND, and
no reference other than the power supply is necessary. In
absolute measurement systems requiring 10-bit accuracy, a
reference with better than 0.1 % accuracy will be necessary.

5.0 Power Supply Considerations
The ADC1061 is designed to operate from a +5V (nominal)
power supply. There are two supply pins, AVec and DVcc.
These pins allow separate external bypass capacitors for
the analog and digital portions of the circuit. To guarantee
accurate conversions, the two supply pins should be connected to the same voltage source, and each should be
bypassed with a 0.1 JIoF ceramic capacitor in parallel with a
10 JIoF tantalum capacitor. Depending on the circuit board
layout and other system considerations, more bypassing
may be necessary.
It is important to ensure that none of the ADC1 OS1 's input or
output pins are ever driven to a voltage more than 300 mV
above AVec and DVcc, or more than 300 mV below GND.lf
these voltage limits are exceeded, the overdrive current into
or out of any pin on the ADC10S1 must be limited to less
than 5 mA, and no more than 20 mA of overdrive current (all
overdriven pins combined) should flow. In systems with multiple power supplies, this may require, careful attention to
power supply sequencing. The ADC1 OS1 's power supply
pins should be at the proper voltage before signals are applied to any of the other pins.

3.0 The Analog Input

The ADC10S1 samples the analog input voltage once ev~ry
conversion cycle. When this happens, the input is briefly
connected to an impedance apprOximately equal to soon in
series with 35 pF. Short-duration current spikes can there-'
fore be observed at the analog Input during normal operation. These spikes are normal and do riot degrade the convertor's performance.
Note that large source impedances can slow the charging of
the sampling capacitors and degrade conversion accuracy.
Therefore, only signal sources with output impedances less
than 500n should be used if rated accuracy is to be

2-400

r--------------------------------------------------------------------,~

C

6.0 Layout and Grounding
All bypass capacitors should be located as close to the converter as possible and should connect to the converter and
to ground with short traces. The analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input. Any external component (e.g., a
filter capacitor) connected across the converter's input
should be connected to a very clean 'ground return' point.
Grounding the component at the wrong point will result in
reduced conversion accuracy.

In order to ensure fast, accurate conversions from the
ADC1 061, it is necessary to use appropriate circuit board
layout techniques. The analog ground return path should be
low-impedance and free of noise from other parts of the
system. Noise from digital circuitry can be especially troublesome, so digital grounds should always be separate from
analog grounds. For best performance, separate ground
planes should be provided for the digital and analog parts of
the system.

o....

i....

•

2-401

i....

~....

t!lNational Semiconductor
..

"

'

.

N
CD
CI
CI

ADC10061/ADC10062/ADC1006410~Bit

~....

General Description

600 ns

.... AID. Converter With Input Multiplexer and Sample/Hold

8....
g
cr:

.. Features

Using an innovative, patented multistep· conversion technique, the 10-bit ADC10061, ADC10062, and ADC10064
CMOS analog-to.cJigital converters offer sub-microsecond
conversion times yet dissipate a maximum of only 235 mW.
The ADC10061, ADC10062, and ADC10064 perform a
10-bit conversion in two lower-resolution "flashes", thus
yielding a fast AID without the cost, power dissipation, and
other problems associated with true flash approaches. The
ADC10061 is pin-compatible with the ADC1061 but much
faster, thus providing a convenient upgrade path for the
ADC1061.
The analog input voltage to the ADC1 0061, ADC10062, and
ADC10064 is sampled and held by an internal sampling circuit. Input signals at frequencies from dc to over 200 kHz
can therefore be digitized accurately without the need for an
external sample-and-hold circuit.
The ADC10062 and ADC10064 include a "speed-up" pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 350 ns
with only a small increase in linearity error.
For ease of interface to microprocessors, the ADC1 0061 ,
ADC10062, and ADC10064 have been designed to appear
as a memory location or 1/0 port without the need for external interface logic.

•
•
•
•
•

Built-in sample-and-hold
Single + 5V supply
1, 2, or 4-input multiplexer options
No external clock required
Speed adjust pin for faster conversions (ADC10062 and
ADC10064). See ADC10662/4 for high speed guaranteed performance.

Key Specifications
600 ns typical,
900 ns max over temperature
800 kHz
Sampling Rate
235 mW (max)
Low power dissipation
± 1.0 LSB (max)
Total unadjusted error
No missing codes over temperature

• Conversion time to 10 bits
•
•
•
•

Applications
•
•
•
•

Digital signal processor front ends
Instrumentation
Disk drives
Mobile telecommunications

Ordering Information
ADC10061
Industrial (-40"C

S;

TA

S;

+85'C)

ADC1 0061 BIN, ADC1 0061 CIN
ADC1 0061 BIWM, ADC1 0061 CIWM

IMilitary (- 55'C TA
IADC10061CMJ/883
S;

S;

+ 125'C)

ADC10064
Industrial (-40"C s; TA

Package
N20A Molded DIP
M20B Small Outline
Package

Military (-55'C

J20ACerdip

Industrial (-40"C

S;

TA

S;

+85'C)

IMilitary ( - 55'C TA
IADC10062CMJ/883
S;

S;

+ 125'C)

S;

TA

ADC10064CMJ/883

ADC 10062

ADC10062BIN, ADC10062CIN
ADC1 0062BIWM, ADC1 0062CIWM

S;

+85'C)

ADC1 0064BIN, ADC1 0064CIN
ADC10064BIWM, ADC10064CIWM

Package
N24A Molded DIP
M24B Small Outline
Package
J24ACerdip

·u.s. Patent Number 4918449
2-402

S;

+125'C)

Package
N28B Molded DIP
M28B Small Outline
Package
J28ACerdip

I
I

Absolute Maximum Ratings

Operating Ratings (Notes 1, 2)

(Notes 1,2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.3Vto +6V
SupplyVoltage(V+ = AVee = DVecl
Voltage at Any Input or Output
-0.3VtoV+ + 0.3V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)

5mA
20mA

Power Dissipation (Note 4)

875mW
2000V

ESD Susceptability (Note 5)
Soldering Information (Note 6)
N Package (10 Sec)
J Package (10 Sec)
_SO Package:
Vapor Phase (60 Sec)
Infrared (15 Sec)
Storage Temperature Range
Junction Temperature

Temperature Range
TMIN ,;; TA';; TMAX
ADC1 0061 BIN, ADC1 0061 BIWM,
ADC10061CIN, ADC10061CIWM,
ADC10062BIN, ADC10062BIWM,
ADC10062CIN, ADC10062CIWM,
ADC10064BIN, ADC10064BIWM,
ADC10064CIN,
-40'C';; TA';; +85'C
ADC10064CIWM
ADC10061CMJ/883, ADC10062CMJ/883,
-55'C,;; TA';; +125'C
ADC10064CMJ/883
Supply Voltage Range

4.5Vt05.5V

260'C
300'C
215'C
220'C
-65'C to + 150'C
150'C

Converter Characteristics
The following specifications apply for V+ = +5V, VREF(+) = +5V, VREF(-) = GND, and Speed-Adjust pin unconnected
unless otherwise specified. Boldface limits apply for TA = T J = T Min to T Max; all other limits TA = TJ = + 25'C.
Symbol

Parameter

Conditions

Typical
(Note 7)

. Resolution

pmlt
(Notes 8, 10)

Units
(Limit)

10

Bits-

±0.6/±:t.1
±1.0/± 1.5

LSB(max)
LSB(max)
LSB

Offset Error

±_1

LSB(max)

Full·Scale Error

±1

LSB(max)

±1.0/± 1.5
±1.5/±2.0

LSB(max)
LSB (max)
LSB

0

(max)

±%

LSB
LSB (max)

Integral Linearity Error

Total Unadjusted Error

BIN, BIWM Suffixes
CIN, CIWM, CMJ SUffixes
RSA = 18kfi

BIN, BIWM Suffixes
CIN, CIWM, CMJ Suffixes
All Suffixes, RSA = 18 kfi

±0.5

±0.5

Missing Codes
Power Supply Sensitivity

V+
V+

THD

Total Harmonic Distortion

fiN
fiN

~NR

Signal·to·Noise Ratio

fiN
fiN

Effective Number of Bits

fiN
fiN

= 5V ±5%, VREF = 4.5V
= 5V ±10%, VREF = 4.5V
= 10 kHz, 4.85 Vp.p
= 160 kHz, 4.85 Vp.p
= 10 kHz, 4.85 Vp.p
= 160 kHz, 4.85 Vp.p
= 10kHz, 4.85 Vp.p
= 160 kHz, 4.85 Vp.p

±1f16
0.06
0.08

%
%

61
60

dB
dB

9.6
9.4

Bits
Bits

RREF

Reference Resistance

650

400

fi(min)

RREF

Reference Resistance

650

900

fi(max)

VREF(+)

VREF(+) Input Voltage

Y+ + 0.05

V (max)

"VREF(-)

VREF(-) Input Voltage

GND- 0.05

V (min)

VREF{+l

VREF(+J Input Voltage

YREF(-)

V (min)

VREF{-)

VREF(-) Input Voltage

YREF(+)

V (max)

Y,N

Input Voltage

Y+ + 0.05

V (max)

V,N

Input Voltage

GND - 0.05

V (min)

3
-3

p.A(max)
p.A(max)

OFF Channel Input Leakage Current
ON Channel Input Leakage Current

CS =
CS

=

V+, Y,N
V+, Y,N
2-403

=
=

V+
V+

0.01
±1

•

..
CD

g

..-

I
..-

g
....c..-

8..g
c

DC Electrical Characteristics
The following specifications apply forV+ = +5V, VAEF(+) = 5V VAEF(-) = GND, and Speed Adjust pin unconnected unless
otherwise specified. Boldface limits apply for TA = ,TJ = T MIN to T MAX; all other limits TA = TJ = + 25°C.
Symbol

Typical
(Note 7)

Conditions

Parameter

=
=

VIN(1)

Logical "1" Input Voltage

V+

VIN(O)

Logi!)al "0" Input Voltage

V+

IIN(1)

Logical"~1" Input Current

VIN(1)

5.5V

2.0

V (min)

0.8

V (max)

0.005

3.0

p.A(max)

-0.005

-3.0

p.A (max)

2.4
4.25

V (min)
V (min)

0.4

V (max)

0.1
-0.1

50
-50

p.A(max)
p.A (max)

1.0
1.0

2

'mA(max)
mA(max)

30
30

45

mA(max)
mA(max)

=

5V

IIN(O)

Logical "0" Input Current

VIN(O) OV

Logical "1" Output Voltage

V+
V+

=
=

4.5V, lOUT
4.5V, lOUT

=
=

-3S0 p.A
-10 p.A

VOUT(O)

Logical "0" Output Voltage

V+

=

4.5V, lOUT

=

1.S mA

lOUT

TRI-STATE!!> Output Current

VOUT
VOUT

Dlcc

DVcc Supply Current

CS = S/H =
CS = S/H =

AVcc Supply Current

CS =
CS =

Units
(Limits)

4.5V

VOUT(1)

AlcC

Limit
(Notes 8, 10)

=
=

5V
OV

S/H
S/H

=
=
= RD =
= RD =
RD
RD

=
=
0, RSA =
0, RSA =
0, RSA
0, RSA

00

18 kO
00

18 kO

AC Electrical Characteristics
The following specifications apply for V+ = +5V, tr = t, = 20 ns, VAEF(+) = 5V, VAEF(-) = GND, and Speed Adjust pin
unconnected unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ =
+ 25°C.
Sym~ol

!coNV

leAD

Conditions

Parameter

Typical
(Note 7)

Limit
(Notes 8, 10)

Units
(Limits)
ns(max)
ns(max)
ns

Mode 1 Conversion Time
from Rising Edge of S/H
to Falling Edge of INT

BIN, BIWM, CIN,
CIWM Suffixes
CMJSuffixes
RSA = 18k

SOO
SOO
375

750/900

Mode' 2 Conversion Time

BIN, BrWM, CIN,
CIWM Suffixes
CMJ Suffixes
Mode 2, RSA := 18k

850
850
530

1400
1500

ns(max)
ns(max)
ns

30

60

ns(max)

900

ICRD + 50

ns(max)

250

ns(max)

30

60

ns(max)

,25

50

ns(max)

50

ns(max)

tACC1

Access Time (Delay from Falling
Edge of RD to Output Valid)

Mode 1; CL

=

100 pF

tACC2

Access Time (Delay from Falling
Edge of RD to Output Valid)

, Mode 2; CL

='

100 pF

tSH

Minimum Sample Time

(Figure 1); (Note 9)

t1H, toH

TRI-STATE Control (Delay
from Rising Edge of RD
to High-Z State)

RL

tlNTH

Delay from Rising Edge of RD
to Rising Edge of INT

CL

tp'

Delay from End of Conversion
to Next Conversion

=

=

1k, CL

100pF

2-404

=

1000

10 pF

~

Ie

AC Electrical Characteristics (Continued)
=

=

=

The following specifications apply for V+
+5V, tr
tf
20 ns, VREF(+)
unconnected unless otherwise specified. Boldface limits apply for TA
TJ
25°C.

=

+

Symbol

Parameter

Conditions

= 5V, VREF(-) = GND, and Speed Adjust pin
= TMIN to TMAX; all other limits TA = TJ =
Typical

Limit

Units

(Note 7)

(Note 8)

(Limits)

tMS

Multiplexer Control Setup Time

10

75

ns(max)

tMH

Multiplexer Hold TIme

10

40

ns(max)

CVIN

Analog Input Capacitance

35

COUT

Logic Output Capacitance

5

pF(max)

CIN

Logic Input Capacitance

5

pF(max)

pF(max)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

o
.....

g
en
.....
.....
~

g
.....
CI

=
en
~
~

Ie

o
.....

CI
CI

en

.Do

functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed test conditons.
Note 2: All voltages arB measured with respect to GND, unless otherwise specified.

Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > V+) the absolute value of current althat pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 8JA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD ~ (TJMAX - TNI8JA or the number given in the Absolute Maximum Ratings, whichever is lower. In most
cases, the maximum derated power dissipation will be reached only during fault conditions. For these dBvices, TJMAX for a board-mounted device can be found
from the tables below:
ADC10061
Suffix

ADC10062

8JA("C/W)

Suffix

ADC10064

8JA("C/W)

Suffix

8JA("C/W)

CMJ

54

CMJ

48

CMJ

44

BIN,CIN

70

BIN,CIN

60

BIN,CIN

53

BIWM,CIWM

85

BIWM,CIWM

82

BIWM,CIWM

78

Note 5: Human body model, 100 pF discharged through a 1.5 kll resistor.
Note 6: See AN·450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section titled "Surfaca Mount" found in a currant National
Semiconductor linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at

+ 25'C and represent must likely parametric norm.

Note 8: Limits ara guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 9: Accuracy may degrade if isH is shorter than the valua specified. See curves of Accuracy vs tSH.
Note 10: A military RETS electricai test spacification is available on request. At time of prinling, the ADC10061CMJ/883, ADC10062CMJ/883, and
ADC10064CMJ/883 RETS specification complies fully with the boldface limits in this column.

2-405

•

Typical Performance Characteristics
Zero (Offset) Error
vs Reference Voltage

Linearity Error
vs Reference Voltage

Analog Supply Current
vs Temperature

I~~~~~~~--~

I~~r-r-~~-=~~~

4O~~~-r~~~~

1--1--1-+ AVa: .. OVa: .. +5V

!

~1--I--I-+-~~.-'~-'-4-4

,'\.

I ~ I-+--t-~I,+-1-+-+-1
I

D.4 1-+---l-+-If-30'of--I;--+--l

....

CI2 HH-+-+-t-""""""'food--i

AVa:" 5.5V

1-t-t-t-AVa:" ova:" +5V
TAa~

!

I

A"a:" 5.ov

~ 1--+-+-+-11--+-+-+-1
~ 1-+-+-+-+-+-1;;;::+-1

I:

I I I

AVa:" 4.5V

I-t-t--I--I-+-+....
-+--'I'
O~~~~~.L-~~

-«5 -ss -15 5 25 .., 85 811 105 125
AM.oo lDIPERATURE ('Ie)

REFERENCE VOLTAGE, V.+ • V._ (V)

Conversion Time
vs Temperature

Digital Supply Current
vs Temperature

Conversion Time
vs Temperature

aD~~~-r~~~~

A~a:I=~a:~~HT

:g

i :: HH-+-+-+-++-+--I

I:

t-+-t---t-+-t-t--t-+-I
1III..........
-!1
..........1-5.....
5-25
........,"--11
......11.........
105--'125

I :~tLL"'I'7"I;­

I

500 t-+-+-+- ~Vi" ~a:7f
400-«5'-'-ss-......15.......
5 -~
.......
l'-.II1-85
. ......105......125

AllllllT1EII'EIIAlURE (Ge)

I

aD

T =~
A

/"'1

~rrTA" .55"C

500

I-t--i-t-t-+-t

=2110

z
100 I-t--I--I-+-+ Va: .. 5V

V."SV

SPEED-UP IIE5ISRlII,

O~"--"--"""""""""~~~

o W 20 lID 40

lIsA (leA)

50

SPEEO-UP RESISIIIR.

10 70 10

lIsA (leA)

I

100 -

I&

aD700 t-+-+-+- AVa: = OVa: " 5.5V

~Iiii;: AVa:" OVa:" 5.ov-

aD-«5'-'-ss
.........
-1-5.....5-25
........,"--85
......85.........
III-I~25
AM.oo lDIPERATURE (Ge)

Spectral Response with
100 kHz Sine Wave Input

"",,_4.IIV,.,.
........,

2O~-r--r-------~

01--+--+

iIi!

9

II I-t--I--I-+-+
~~
_

-+

OVa:"4.5V

~

..J

.-:.",..-

-

i

J.

TA=I~. ~i"""

700
'laD

10 70 10

AV

", a:"
.J 1000'"

Conversion Time
vs Speed-Up Resistor
(ADC10062 and ADC10064 Only)

aD~~~~~~~~

50

-

1100 H~-:±--I--:-!::+++-I

AM.OO lDIPERATURE ('Ie)

Conversion Time
vs Speed-Up Resistor
(ADC10062 and ADC10064 Only)

o 10 20 lID 40

12IIO~r-r~....,...,..-r~_~2::1

'i

-20 1---+--1-

=--==;s:
T.. _JIIC

S/IIfoD),III.II.
-401---+--~~--+-~

I -eo~-+--t--~
-eottl~u.~~I~~;
1~
I!:

-100

o

50

100

150

2110

250

FREQUENCY (JcHz)

Spectral Response with
100 kHz Sine Wave Input
2Or-~--~--------~

vcc· ....• ..
Yoo'4.I5Y"

o

'A-"

~ -201---+--1-'=;::
Ii!
S/IIfoD)'. .II.
9 -401--~--+--+--+-~

TL/H/ll020-2

2-406

Typical Performance Characteristics (Continued)
Linearity Change
vs Speed-Up Resistor
(ADC10062 and ADC10064 Only)

Signal-to-Noise + THD Ratio
vs Signal Frequency

70
'iii'
.:!!.

4

~

...z

0

~

50

c.>

40

u

20 10 -

!!!

-

30

0

Z

I

f'!
.!.

~

iii

=
=

3

~

0

i!:
it

tolode 1
Vee 5V
VREF 5V

'iii'

60

'"0
'"
15

Vee=VREF=+5V
VIN = 4.85 Vp_p

-

T" =250(;

-

Source Impedance = 600.0.
Sampling Rate = 512kHz

20k

SDk lOOk

T"

~~

'"i:5z

\(

:::;

"""<: ::::.

o
o

200k

Linearity Change
vs Speed-Up Resistor
(ADC10062 and ADC10064 Only)
4

~

...z
c.>

...

0

~

'"
i:5
~

~

~ D.5
15 D.4

=-550(;
=250(;
T" =1250(;

~

I

10

\

:

~ 0.1

~~

o
o

0.0
20

30

tolodel
Vee = 5V
VREF = 5V
T" = 250(;

i ~;

T"
T"

I

20

~:

U

...'"'"'"

J""o4.-

10

1.0

:J:

2

25;:

Linearity Error Change
vs Sample Time

tolode 2
Vee = 5V
VREF = 5V

3

~

T" = 1250(;
I
I

SPEED-UP RESISTOR, RSA (k.D.)

FREQUENCY (Hz)

'iii'

=-550(;

f-- T"

~

o
10k

2

30

SPEED-UP RESISTOR, RSA (k.D.)

\
i'...
.......

o

20 40 60 80 100 120 140 160 180 200
SAtolPLE TltolE, tSH (ns)
TL/H/ll020-4

2-407

II

i....

g

ig
....

TRI-STATE Test Circuits and Waveforms
Vee

ADC10061
ADC10062
ADC10064

1-....- ....-.

DATA
OUTPUT

~
....

TUH/ll020-6

8....

TLlH/ll020-5

o

c

cc

Vee

Vee

_ Vee --+-100__RD
ADC10061
ADC10062
ADC10064

1-""-'"
I

GND
DATA
OUTPUT

DATA Vee
OUTPUT VOL _ _ _"'

CL

TUH/ll020-8

TL/Hlll020-7

Timing Diagrams

cs \'-..;.......;..~l,'r---------------~\,-_~I
,
,
5/H

---""\7: isH -f,r---------------------

, SO
(ADC10062 and
ADC10064 only)

SI
(ADC10064 only)

,

,

I

I

=:x x,,.----------------------------------------.'

VALID

~

~tllS'

~

---v
-.J!\

VALID

,

:-+tllH

X"''~---------+__________________________________

\

~

I

: - - - _ - ' :.- tlNTH

iNi'

:

'

I

DOO-D09

," 'r-----

----------....;------------~'
\
t . . - - tcoNV -----.I

:

tAcel - :
I

I

f- -: ' f-

,,

t1H• 10M

>_____ _

1 1

.----------~----------------I-<
,"

TUH/ll020-9

FIGURE 1. Mode 1. The conversion time (tcoNV) Is set by the Internal timer.

2-408

r--------------------------------------------------------------------.~

C

Timing Diagrams (Continued)

S/H

and

(')

cs

-----~..-i---------------------I- ____ _

RD

\-----------=1. t: ___ _
.IX,

50 _ _ _
(ADC 10062 and
• •
ADC 10064 only)
'tots - :

(ADC10064

on~y)

VALID

X,,,------------------------

'-'

-:

: - - \tH

X X,,__________________;-._____

___

VALID

:•
'eRD
;

•,
'

:

\:

,

:.

000 - 009

tACC2

.:

-

_~NTH
_ _ __

I l:--

r

:1

-.J':-~H'
.

>-----'oH

------~
~at. Valid
~,

TUH/ll020-10

FIGURE 2. Mode 2 (RD Mode). The conversion time (teRD) Includes the
sampling time and Is determined by the Internal timer.

Simplified Block Diagram
VREF+

VREF+

DB9 (IoISB)

6 Bit Flash A/D
(6 IoISBs)

VREFVIN', VINO"

DB8

6

VREF-

DB7

VIN1 "

6

OUTPUT
LATCH
AND
TRI-STATE'
BUFFERS

VIN2' "
VIN3'"

54

AVec
DVcc

DB6

DDS
DB4
DB3
DB2

VREF+

OBI

4 Bit Flash A/D
(4 LSBs)

4

DBD (LSB)

VREF-

SPEED
ADJ"

iNT

GND'

....
....

AGND"

DGND"

Cs

Rij

5/H

SO" 51'"
TL/H/ll020-1

'ADC10061 Only
"ADC10062 and ADC10064 Only
'''ADC10064 Only

2-409

<:)
<:)

G)

~

c

....

(')
<:)

~

~

c

....

(')
<:)
<:)

G)
~

...

CD
0
0

Connection Diagrams

0
C

Dual-In-Une 'Package

....

CC
.....

'"
CD
0
0

....

0

~
.....

....
CD
0
0

....
8CC

DVec

iNT
5/H
iiD

10

20

DBO (lSB)

2

19

OBI

3

18

DB2

4

17

DB3

iNT
5/H
iiD

16

DB4

cs

cs

5

AVec

6

15

DBS

VREFVIN

7

14

DB6

8

13

DB7

VREF+
GND

9

12

DB8

10

11

DB9 (IASB)

ADC10061

Dual-In-Llne Package

Dual-In-Llne Package
DVec

10

24

DBO (lSB)

2

23

OBI

3

22

DB2

AVec

TL/H/ll020-11

iNT
5/H
iiD

DB3
ADC10062

TOp View

DVec

VREFVINO
VIN1

DBO (LSB)

27

OBI

3

26

DB2

4

25

DB3

5

24

DB4

cs

DB5

SO

23

DBS

DB6
DB7 '

SI

ADC10064 22

DB6

AVec

21

N.C.

VREFVINO
VIN1

20

DB7

VIN2

17

SPEED ADJ

VIN3

16

DGND

VREF+

15

AGND

DB9 (IASB)
SPEED ADJ
13

28

2

DB4

DBB

VREF+
AGND

10

DGND
TL/H/ll020-12

Top View

19

DBB

18

DB9 (IASB)

TL/H/ll020-13

Top View

Pin Descriptions
DVee. AVec These are the digital and analog positive supply voltage inputs. They should always be
connected to the same voltage source. but
are brought out separately to allow for separate bypass capacitors. Each supply pin
should tie bypassed with a 0.1 ,...F ceramic
capaCitor in parallel with a 10 ,...F tantalum
capacitor to ground.
jjijf

This is the active low interrupt output. jjijf
goes low at the end of each conversion. and
returns to a high state following the, rising
edge of RD.
"

5/H

This is the Sample/Hold control input. When
this pin is forced low (and CS is low). it causes the analog input signal to be sampled and
initiates a new conversion.

RD

This is the' active low Read control input.
are low. any data presWhen this AD and
ent in the output registers will be placed on
the data bus.

es
SO. Sl

These are the reference voltage inputs. They
may be placed at any voltage between GND
and Vee. but VREF+ must be greater than
VREF-. An input voltage equal to VREFproduces an output code of O. and an input
voltage equal to (VREF+ - 1 LSB) produces
an output code of 1023.
VIN. VINO. "These are the analog' input pins. The
ADC10061 has' one input (VIN). the
VIN1. VIN2.
ADC10062 has two inputs (VI NO and VIN1).
VIN3
and the ADC10064 has four inputs (VINO.
VIN1. VIN2 and VlliI3). 'The impedance of the
source should be less than 500n for best accuracy and conversion speed. For accurate
conversions. no input pin (even one that is
not selected) should' be driven more than
50 mV above Vec or 50 mV below ground.

es

GND. AGND. These are the power supply ground pins. The
ADC10061 has a single ground pin (GND).
DGND
and the ADC10062 and ADC10064 have separate analog and digital ground pins (AGND
and DGND) for separate bypassing of the analog and digital supplies. The ground pins
should be connected 'to a stable. noise-free
system ground. For the devices with two
ground pins. both pins should be returned to
the same potential.

This is the active low ChipSelect control input. When low. this 'pin enables the m5 and
5/H pins.
"
,
On the multiple-input devices (ADC10062
and ADCl 0064). these pins select,the analog
input that will be connected to the AID during
the conversion. The input is selected based
on the state of SO and Sl when 5/H makes
its High-ta-Low transition (See the Timing Diagrams). The ADC10064 includes both SO
and 51. The ADCl 0062 Includes Just SO. and
the ADC10061 includes neither.

2-410

DBO-DB9

These are the TRI,STATE ou~put pins.'

SPEEDADJ

(ADC10062 and ADC10064 only). This pin is
normally left unconnected. but by connecting
a resistor between this pin and ground. the
conversion time can be reduced. See the
Typical Performance Curves and the table of
Electrical Characteristics.

.--------------------------------------------------------------------.~

c

Functional Description
The ADC10061, ADC10062 and ADC10064 digitize an analog input signal to 10 bits accuracy by performing two lowerresolution "flash" conversions. The first flash conversion
provides the six most significant bits (MSBs) of data, and
the second flash conversion provides the four least significant bits LSBs).

To perform a conversion, the estimator compares the input
voltage with the tap voltages on tile seven resistors on the
left. The estimator decoder then determines which MSB
Ladder tap paints will be connected to the sixteen comparators on the right. For example, assume that the estimator
determines that VIN is between 11/16 and 13/16 of VREF.
The estimator decoder will instruct the comparator MUX to
connect the 16 comparators to the taps on the MSB ladder
between 10/16 and 14/16 of VREF. The 16 comparators will
then perform the first flash conversion. Note that since the
comparators are connected to ladder voltages that extend
beyond the range indicated by the estimator circuit, errors in
the estimator as large as 1/16 of the reference voltage
(64 LSBs) will be corrected. This first flash conversion produces the six most significant bits of data-four bits in the
flash itself, and 2 bits in the estimator.
The remaining four LSBs are now determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input voltage (as determined by the first flash) is subtracted
from the input voltage and compared with the tap points on
the sixteen LSB Ladder resistors. The result of this second,
four-bit flash conversion is then decoded, and the full 1O-bit
result is latched.
Note that the sixteen comparators used in the first flash
conversion are reused for the second flash. Thus, the mUltistep conversion technique used in the ADC10061,
ADC10062, and ADC10064 needs only a small fraction of
the number of comparators that would be required for a
traditional flash converter, and far fewer than would be used
in a conventional half-flash approach. This allows the
ADC10061 , ADC10062, and ADC10064 to perform highspeed conversions without excessive power drain.

Figure 3 is a simplified block diagram of the converter. Near
the center of the diagram is a string of resistors. At the
bottom of the string of resistors are 16 resistors, each of
which has a value 1/1 024 the resistance of the whole resistor string. These lower 16 resistors (the LSB Ladder) therefore have a voltage drop of 16/1024, or 1/64 of the total
reference voltage (VREF+ - VREF-) across them. The remainder of the resistor string is made up of eight groups of
eight resistors connected in series. These comprise the
MSB Ladder. Each section of the MSB Ladder has Va of the
total reference voltage across it, and each of the LSB resistors has 1/64 of the total reference voltage across it. Tap
paints across these resistors can be connected, in groups
of sixteen, to the sixteen comparators at the right of the
diagram.

On the left side of the diagram is a string of seven resistors
connected between VREF+ and VREF-. Six comparators
compare the input voltage with the tap voltages on this resistor string to provide a low-resolution "estimate" of the
input voltage. This estimate is then used to control the multiplexer that connects the MSB Ladder to the sixteen comparators on the right. Note that the comparators on the left
needn't be very accurate; they Simply provide an estimate of
the input voltage. Only the sixteen comparators on the right
and the six on the left are necessary to perform the initial
six-bit flash conversion, instead of the 64 comparators that
would be required using conventional half-flash methods.

--t-----i----..

VREF+ - -....

14/16

13/16

!!i

11/16

.:5
UI

:::I

,

12/16,
4/16'
2/16

9/16

!!i
~

16/1024
7/16

5/16

.~
~

DBO- DB9

10

1
I
I

3/16

1/1024'

VRIF_
TUH/ll020·14

FIGURE 3. Block Diagram of the Multistep Converter Architecture

2-411

n
....
o
oCJ)

....
.....

~

c
o....
o
o

C»
....,

......
~

c
o....
o

o

CJ)
~

~ r---------------------------~--------~--------------------------------------------------_,

CD
Q

Q
.....

g
c(
.....
C'II
CD
Q
Q

.....

o
c
~
.....
CD
Q
Q

.....

o

cc(

Applications Information
1.953 mV). Note; however, that linearity and offset errors
become larger when lower reference voltages are used.
See the Typical Performance Curves for more information.
For this reason, reference voltages less than 2V are not
recommended.
In most applications, VREF _ will simply be connected to
ground, but it is often useful to have an input span that is
offset from ground. This situation is easily accommodated
by the reference configuration used in the ADC10061,
ADC10062, and ADC10064. VREF- can be connected to a
voltage other than ground as long as the voltage source
connected to this pin is capable of sinking the converter's
reference current (12.5 rnA Max @ VREF = 5V).lf VREF- is
connected to a voltage other than ground, bypass it with
multiple capacitors.

1.0 MODES OF OPERATION
The ADC1 0061, ADC10062, and ADC1 0064 have two basic
digital interface modes. Figure 1 and Figure '.2 are timing
diagrams for the two modes. The ADC10062. and
ADC10064 have input multiplexers that are controlled by
the logic levels on pins So and. S1 when 8tH goes low.
Table I.is a truth table showing how the input channneis are
assigned.
Model
In this mode, the 8tH pin controls the start of conversion.
5tH is pulled low for a minimum of 250 ns. This causes the
comparators in the "coarse" flash converter to become ac·
tive. When 8tH goes high, the result of the coarse conversion is latched and the "fine" conversion begins. After
600 ns (typical), INT goes low, indicating that the conversion
results are latched and can be read by pulling RD low. Note
that CS must be low to enable 8tH or RD. CS is internally
"ANDed" with 5tH and RD; the input voltage is sampled
when CS and 5tH are low, and data is read when CS and
RD are low. INT is reset high on the rising edge of RD.

Since the resistance between the two reference inputs can
be as low as 4000, the voltage source driving the reference
inputs should have low output impedance. Any noise on either reference input is a potential cause of conversion errors, so each of these pins must be supplied with a clean,
low noise voltage source. Each reference pin should be bypassed with a 10 ,.,.F tantalum and a 0.1 ,.,.F ceramic.

T~BLE I. Input Multiplexer Programming
51

ADC10064
Channel
So

So

0

0

VINO

0

0

1

VINI

1

1
1

0

VIN2

1

ADC10062
Channel

3.0 THE ANALOG INPUT
The ADCl 0061, ADCl 0062, and ADCl 0064 sample the analog input voltage once every conversion cycle. When this
happens, the input is briefly connected to an impedance
approximately equal to 6000 in series with 35 pF. Short-dUration current spikes can therefore be observed at the analog.input during normal operation. These spikes are normal
and do not degrade the converter's performance.
Large source impedances can slow the charging of the
sampling capaCitors and degrade conversion accuracy.
Therefore, only Signal sources with output impedances less
than 5000 should be used if rated accuracy is to be
achieved at the minimum sample time (250 ns maximum). If
the sampling time is increased, the source impedance can
be larger. If a signal source has a high output impedance, its
output should be buffered with an operational amplifier. The
operational amplifier's output should be well-behaved when
driving a switched 35 pFt600010ad. Any ringing or voltage
shifts at the op amp's output during the sampling period can
result in conversion errors.

VINO
VINI

(b)

VIN3

(a)
Mode 2
In Mode 2, also called "RD mode", the 5tH and RD pins
are tied together. A conversion is initiated by pulling both
pins low. The AID converter samples the input voltage and
causes the coarse comparators to become active. An internal timer then terminates the coarse conversion and begins
the fine conversion. 850 ns (typical) after 5tH and RD are
pull low, INT goes low, indicating that the conversion is
completed. Approximately 20 ns later the data appearing on
the TRI-STATE output pins will be valid. Note that data will
appear on these pins throughout the conversion, but until
INT goes low the data at the output pins will be the result of
the previous conversion.

Correct conversion results will be obtained for input voltages greater than GND - 50 mV and less than V+ +
50 mV. Do not allow the signal source to drive the analog
input pin more than 300 mV higher than AVec and DVee, or
more than 300 mV lower than GND. If an analog input pin is
forced beyond these voltages, the current flowing through
the pin should be limited to 5 rnA or less to avoid permanent
damage to the IC. The sum of all the overdrive currents into
all pins must be less than 20 rnA. When the input signal is
expected to extend more than 300 mV beyond the power
supply limits, some sourt of protection scheme should be
used. A Simple network using diodes and resistors is shown
in Figure 4.

2.0 REFERENCE CONSIDERATIONS
The ADC1 0061 , ADC10062, and ADC10064 each have two
reference inputs. These inputs, VREF+ and VREF-, are fully
differential and define :the zero to full-scale range of the
input signal. The reference inputs can be connected to span
the entire supply voltage range (VREF- = OV, VREF+ =
Veel for ratiometric applications, or they can be connected
to different voltages (as long as they are between ground
and Veel when other input spans' are required. Reducing
the overall VREF span to less than 5V increases the sensitivity of the converter (e.g., if VREF = 2V, then 1 LSB =

2-412

):.

Applications Information

C

o....

(Continued)

.----------.
:
+5V

o
o0)

I
I

:

....
.....
):.

7
100

100

10
V +.I\II,..,.....-M~-----,~,

18

INO

VIN , ---'2-1
VIN2 ---'3-1

._--------(Optional; see text)

C

DB9 (t.lSB)

o
o

DB7

ADC10064

VIN3 ---'5-1

o
....
0)
I\)

.....
):.

DBS

C

o
....

AGND

8
a...,.--~~~~~~--~""T"---""'
DGND

.--....--__4_...--

+5V

___
""'-;2;;-8 DBO (lSB)
17

0)

"'"

RSA (Optional; see text)

TUH/ll020-15

FIGURE 4. Typical Connection. Note the multiple bypass capacitors on the reference and power supply pins. If VREFIs not grounded,lt should also be bypassed to analog ground using multiple capacitors (see 5.0 "Power Supply
Considerations"). AGND and DGND should be at the same potential. VINO is shown with an input protection network.
Pin 171s normally left open, but optional "speedup" resistor RSA can be used to reduce the conversion time.
4.0 INHERENT SAMPLE-AND-HOLD
Because the ADC10061 , ADC10062, and ADC10064 sam·
pie the input signal once during each conversion, they are
capable of measuring relatively fast input signals without the
help of an external sample·hold. In a non-sampling succes·
sive-approximation AID converter, regardless of speed, the
input signal must be stable to better than ± 1/2 LSB during
each conversion cycle or significant errors will result. Con·
sequently, even for many relatively slow input Signals, the
signals must be externally sampled and held constant during each conversion if a SAR with no internal sample·andhold is used.

The ADC1 0061 has a single ground pin, and the ADC1 0062
and ADC10064 each have separate analog and digital
ground pins for separate bypassing of the analog and digital
supplies. The devices with separate analog and digital
ground pins should have their ground pins connected to the
same potential, and all grounds should be "clean" and free
of noise.
In systems with multiple power supplies, careful attention to
power supply sequencing may be necessary to avoid overdriving inputs. The AID converter's power supply pins
should be at the proper voltage before digital or analog signals are applied to any of the other pins.

Because they incorporate a direct sample/hold control in·
put, the ADC1 0061, ADC10062, and ADC1 0064 are suitable
for use in DSP·based systems. The 5/H input allows syn·
chronization of the AID converter to the DSP system's sam·
piing rate and to other ADC1 0061 s, ADC10062s, and
ADC10064s.
The ADC10061 , ADC10062, and ADC10064 can perform
accurate conversions of input signals with frequency components from DC to over 160 kHz.

6.0 LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC10061, ADC10062, and ADC10064, it is necessary to
use appropriate circuit board layout techniques. The analog
ground return path should be low-impedance and free of
noise from other parts of the system. Noise from digital circuitry can be especially troublesome, so digital grounds
should always be separate from analog grounds. For best
performance, separate ground planes should be provided
for the digital and analog parts of the system.

5.0 POWER SUPPLY CONSIDERATIONS
The ADC10061, ADC10062, and ADC10064 are deSigned
to operate from a + 5V (nominal) power supply. There are
two supply pins, AVec and DVcc. These pins allow separate external bypass capacitors for the analog and digital
portions of the circuit. To guarantee accurate conversions,
the two supply pins should be connected to the same volt·
age source, and each should be bypassed with a 0.1 p.F
ceramic capaCitor in parallel with a 10 p.F tantalum capacitor. Depending on the circuit board layout and other system
conSiderations, more bypassing may be necessary.

All bypass capacitors should be located as close to the converter as possible and should connect to the converter and
to ground with short traces. The analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input. Any external component (e.g., a
filter capacitor) connected across the converter's input
should be connected to a very clean ground return point.
Grounding the component at the wrong point will result in
reduced conversion accuracy.

2·413

PI

~

CD

g

Applications Information (Continued)

8

7.0 DYNAMIC PERFORMANCE

.,...

~

N
CD
Q

Q
.,...
o

c

cc
.....
.,...
CD
Q
Q

.,...
(.)

c

cc

One way of describing the AID's performance as a function
of signal frequency is to make a plot of "effective bits" versus frequency. An ideal AID converter with no linearity errors or self-generated noise will have a signal-to-noise ratio
equal to (6.02n + 1.8) dB, where n is the resolution in bits
of the AID converter. A real AID converter will have some
amount of noise and distortion, and the effective bits can be
found by:

Many applications require the AID converter to digitize AC
signals. but conventional DC integral and differential nonlin·
earity specifications don't accurately predict the AID corio
verter's performance with AC input signals. The important
specifications for AC applications reflect the converter's
ability to digitize AC signals without significant spectral er·
rors and without adding noise to the digitized signal. Dynamic characteristics such as signal-to-noise ratio (SNR) and
total harmonic distortion (THD), are quantitative measures
of this capability.
An AID converter's AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal
waveform is applied to the AID converter's input, and the
transform is then performed on the digitized waveform. The
resulting spectral plot might look like the ones shown in the
typical performance curves. The large peak is the fundamental frequency, and the noise and distortion components
(if any are present) are visible above and below the fundamental frequency. Harmonic distortion components appear
at whole multiples of the input frequency. Their amplitudes
are combined as the square root of the sum of the squares
and compared to the fundamental amplitude to yield the
THD specification. Typical values for THD are given in the
table of Electrical Characteristics.
Signal-to-noise ratio is the ratio of the amplitude at the fundamental frequency to the rms value at all other frequencies, excluding any harmonic distortion components. Typical
values are given in the Electrical Characteristics table. An
alternative definition of signal-to-noise ratio includes the distortion components along with the random noise to yield a
signal-to-noise-plus-distortion ration, or S/(N + D).

( ff . ) _ S/(N
n e ectlve -

+ D) (dB)

- 1.8

6.02

where S/(N + D) is the ratio of signal to noise and distortion, which can vary with frequency.
As an example, an ADC10061 with a 5 Vp_p, 100 kHz sine
wave input signal will typically have a signal-to-noise-plusdistortion ratio of 59.2 dB, which is equivalent to 9.53 effective bits. As the input frequency increases, noise and distortion gradually increase, yielding a plot of effective bits or
S/(N + D) as shown in the typical performance curves.

8.0 SPEED ADJUST
In applications that require faster conversion times, the
Speed Adjust pin (pin 14 on the ADC10062, pin 17 on the
ADC10064) can significantly reduce the conversion time.
The speed adjust pin is connected to an on-Chip current
source that determines the converter's internal timing. By
connecting a resistor between the speed adjust pin and
ground as shown in Figure 4, the internal programming current is increased, which reduces the conversion time. As an
example, an 18k resistor reduces the conversion time of a
typical part from 600 ns to 350 ns with no significant effect
on linearity. Using smaller resistors to further decrease the
conversion time is possible as well, although the linearity
will begin to degrade somewhat (see curves). Note that the
resistor value needed to obtain a given conversion time will
vary from part to part, so this technique will generally require
some "tweaking" to obtain satisfactory results.

The THD and noise performance of the AID converter will
change with the frequency of the input signal, with more
distortion and noise occurring at higher signal frequencies.

2-414

tJ1National Semiconductor

ADC 104611ADC 104621 ADC 10464 10-Bit 600 ns
AID Converter with Input Multiplexer and SamplelHold
General Description

Features

Using an innovative, patented multistep' conversion technique, the 10-bit ADC10461 , ADC10462, and ADC10464
CMOS analog-to-digital converters offer sub-microsecond
conversion times yet dissipate a maximum of only 235 mW.
The ADC10461 , ADC10462, and ADC10464 perform a
10-bit conversion in two lower-resolution "flashes", thus
yielding a fast AID without the cost, power dissipation, and
other problems associated with true flash approaches. Dynamic performance (THD, SIN) is guaranteed. The
ADC10461 is pin-compatible with the ADC1061 but much
faster, thus providing a convenient upgrade path for the
ADC1061.

•
•
•
•
•

The analog input voltage to the ADC1 0461, ADC10462, and
ADC10464 is sampled and held by an internal sampling circuit. Input signals at frequencies from dc to over 200 kHz
can therefore be digitized accurately without the need for an
external sample-and-hold circuit.
The ADC10462 and ADC10464 include a "speed-up" pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 350 ns
with only a small increase in linearity error.

Built-in sample-and-hold
Single + 5V supply
1, 2, or 4-input multiplexer options
No external clock required
Speed adjust pin for faster conversions (ADC10462 and
ADC10464)

Key Specifications
• Conversion time to 10 bits
•
•
•
•

600 ns typical,
900 ns max over temperature
800 kHz
Sampling Rate
235 mW (max)
Low power dissipation
-60 dB (max)
Total harmonic distortion (50 kHz)
No missing codes over temperature

Applications
•
•
•
•

Digital signal processor front ends
Instrumentation
Disk drives
Mobile telecommunications

For ease of interface to microprocessors, the ADC1 0461,
ADC10462, and ADC10464 have been designed to appear
as a memory location or 1/0 port without the need for external interface logic.

Ordering Information
ADC10461
Industrial

(-40'C ,;; TA ,;; +85'C)

ADC10464
Industrial

Package

(-40'C ,;; TA ,;; +85'C)

N20A Molded DIP
M20B Small Outline

ADC10461CIN
ADC1 0461 CIWM

ADC10464CIN
ADC10464CIWM

ADC10462
Industrial

(-40'C ,;; TA';; +85'C)
ADC10462CIN
ADC10462CIWM

Package
N24A Molded DIP
M24B Small Outline

·U.S. Patent Number 49t8449

2-415

Package
N28B Molded DIP
M28B Small Outline

Absolute Maximum Ratings (Notes 1,2)

Operating Ratings

Soldering Information (Note 6)
N Package (10 Sec)
SO Package:
Vapor Phase (60 Sec)
infrared (15 Sec)

(Notes 1, 2)
Temperature Range
TMIN ,,; TA ,,; TMAX
ADC1 0461 CIN, ADC10461CIWM,
ADC10462CIN, ADC10462CIWM,
ADC10464CIN,
-400C"; TA"; +85·C
ADC10464CIWM

20mA

Power Dissipation (Note 4)
ESD Susceptability (Note 5)

+ 150·C
'150·C

Junction Temperature

Supply Voltage (V+ = AVcc = DVcc)
-0.3Vto +6V
-0.3VtoV+ + 0.3V
Voltage at Any Input or Output
Input Current at Any Pin (Note 3)
5mA
Package Input Current (Note 3)

- 65·C to

Storage Temperature Range

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

875mW
2000V

4.5Vt05.5V

Supply Voltage Range

260·C
.,

215·C
220·C

Converter Characteristics
The following specifications apply for V+ = +5V, VREF(+) =:' +5V, VREF(-) = GND, and Speed Adjust pin unconnected
unless otherwise specified. Boldface limits apply for TA = T J = T Min to T Max; all other limits TA = TJ = + 25·C.
Symbol

Conditions

Parameter

Typical
(Note 7)

Resolution
Integral Linearity Error

10
RSA ~ 18 k.!l

±0.5
±1

LSB (max)

±1

LSB(max)

0

(max)

RSA ~ 18 k.!l

±0.5

Power Supply Sensitivity

V+ = 5V ±5%, VREF = 4.5V '
V+ = 5V ±10%, VREF = 4.5V

± '116
±Ys

Total Harmonic Distortion

fiN
fiN
fiN
fiN

-68
-66
-62
-58

Signal·to-Noise Ratio

ENOB

Bits
LSB

Full·Scale Error

Missing Codes

SNR

Units
(Limit)

Offset Error

Total Unadjusted Error

THD

Limit
(Note 8)

Effective Number of Bits
"

=
=
=
=

1 kHz, 4.85 Vp.p
50 kHz, 4.85 Vp.p
100 kHz, 4.85 Vp_p
240 kHz, 4.85 Vp.p

fiN =' 1 kHz, 4.85 Vp.p
fiN = 50 kHz, 4.85 Vp_p
fiN = 100 kHz, 4.85 Vp_p

61
60
60

fiN = 1 kHz, 4.85 Vp_p
fiN = 50 kHz,A.85 Vp_p

9.6
9.5

LSB

LSB
LSB
-60

58

9

dB
dB (max)
dB
dB
dB
dB (min)
dB
Bits
Bits (min)

RREF

Reference Resistance

650

400

.!l(min)

650

900

.!l (max)

RREF

Reference Resistance

VREF(+)

VREF( +) Input Voltage

Y+ + 0.05

V (max)

VREF(-)

VREF( -) Input Voltage

GND - 0.05

V (min)

VREF(+)

VREF( +) Input Voltage

YREF(-)

V (min)

VREF(-)

VREF( -) Input Voltage

YREF(+)

V (max)

VIN

Input Voltage

Y+ + 0.05

V (max)

VIN

Input Voltage

GND - 0.05

V (min)

3
-3

IJ-A (max)
IJ-A(max)

OFF Channel Input Leakage Current
ON Channel Input Leakage Current

CS = V+, VIN = V+
V+, VIN = V+

CS =

2-416

0.01
±1

:J>

c

DC Electrical Characteristics
The following specifications apply forV+ = +5V, VREF(+) = 5V VREF(-) = GND, and Speed Adjust pin unconnected unless
otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = + 25D C.
Symbol

Parameter

Typical
(Note 7)

Conditions

Limit
(NoteS)

Units
(Limits)

VINci)

Logical "1" Input Voltage

V+

=

5.5V

2.0

V (min)

VIN(O)

Logical "0" Input Voltage

V+

=

4.5V

0.8

V (max)

IIN(1)

Logical "1" Input Current

VIN(1)

=

5V

IIN(O)

Logical "0" Input Current

VIN(O) OV

VOUT(1)

Logical "1" Output Voltage

V+
V+

=
=

4.5V, lOUT
4.5V, lOUT

=
=

-360/LA
-10/LA

VOUT(O)

Logical "0" Output Voltage

V+

=

4.5V, lOUT

=

1.6 rnA

lOUT

TRI-STATE Output Current

VOUT
VOUT

Dice

DVcc Supply Current

CS = 8tH =

Alce

AVcc Supply Current

=
=

5V
OV

CS

=

=

RD
RD

=
=

0, RSA
0, RSA

=
=

18 k!l

CS
CS

= StH =
= 8tH =

RD
RD

=
=

0, RSA
0, RSA

=
=

18 k!l

8tH

tCONV

ICRD

Conditions

/LA (max)

c

V (min)
V (min)

o.;:.

0.4

V (max)

0.1
-0.1

50
-50

/LA (max)
/LA (max)

1.0
1.0

2

mA(max)
mA(max)

30
30

45

mA(max)
rnA (max)

00

00

Units
(Limits)

CIN,
CIWM Suffixes
Mode 2, RSA = 18k

850
530

1400

ns(max)
ns

30

60

ns(max)

900

tcRD + 50

ns(max)

250

ns(max)

30

60

ns(max)

25

50

ns (max)

50

ns(max)

Access Time (Delay from Falling
Edge of RD to Output Valid)

Mode 2; CL

=

100 pF

isH

Minimum Sample Time

(Figure 1); (Note 9)

t1H, toH

TRI-STATE Control (Delay
from Rising Edge of RD
to High-Z State)

RL

Delay from Rising Edge of RD
to Rising Edge of INT

CL

tp

Limit
(NoteS)

Mode 2 Conversion Time

tACC2

tlNTH

Typical
(Note 7)

ns(max)
ns

100 pF

=

=

1k,CL

=

10pF

100pF

Delay from End of Conversion
to Next Conversion

2-417

......

2.4
4.25

750t900

=

.;:.

en

N

-3.0

600
375

Mode 1; CL

c
o
.....
o

-0.005

CIN,
CIWM Suffixes
RSA = 18k

Access Time (Delay from Falling
Edge of RD to Output Valid)

:J>

/LA (max)

Mode 1 Conversion Time
from Rising Edge of 5tH
to Falling Edge of INT

tACC1

......

3.0

AC Electrical Characteristics

Parameter

o

ct
.....

0.005

The following specifications apply for V+ = +5V, tr = tf = 20 ns, VREF(+) = 5V, VREF(-) = GND, and Speed Adjust pin
unconnected unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ =
+ 25D C.
Symbol

o
.....

:J>

o
.....
en

.;:.

...
....~

o

~
~

o
....

o
c

AC Electrical Characteristics (Continued)

,:

",'

=

+5V. tr = t, = 20 ns. VREF(+) = 5V. VREF(-) = GND, and Speed Adjust pin
unconnected unless otherwise specified. Boldface limits apply for TA = TJ = ,TMIN to TMAX; all other limits TA = TJ =
25°C. (Continued)

The following specifications apply for V+

+

Parameter

Symbol

Conditions

Typical

Limit

Units

(Note 7)

(Note 8)

(Umlts)
ns(max)

tMS

Multiplexer Control Setup Time

,10

75

tMH

Multiplexer Hold Time

10

40

~
o

CVIN

Analog Input Capacitance

35

pF(max)

COUT

Logic Output Capacitance

5

pF(max)

c
cr:

CIN

Logic Input Capacitance

5

pF

~
....

....
o

ns(max)

(maX)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. These ratings do not guarantee specifIC performance limits, however, For guaranteed specHications and test conditions, see the Electricai Characteris.
tics. The guaranteed specifications apply only for the test conditions listed, Some performance characteristics may deg,,!oo when the device Is not operated under
the listed test conditons.
Note 2: All voltegss are measured

w~h

respect to GND, unless otherwise specHied.

Note 3: When the input voltage (YIN) at any pin exceeds the power supply rails (YIN < GND or VIN > V+) the absolute value of current at that pin should be limited
to 5 rnA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an Input current of 5 mA to four.
Nota 4: The maximum power dissipation must be derated at elevated temperatures and Is dictated by TJMAX, 0JA and the ambient temperature, TA. The maximum
allowable power diSSipation at any temperature is Po = (TJMAX -, TAl/OJA or the number given in the Absolute Maximum Ratings, whichever is lOwer. In'most
cases, the maximum derated power dissipation will be reached only during fault conditions. For these devices, TJMAX for a board-mounted device can be found
, from the tables below:
ADC10461
Suffix
CIN
CIWM

ADC10462

°JArC/W) ,

70
85

Suffix

ADC10464
Suffix

8JArC/W)

,8JArC/W)

CIN

60

CIN

53

CIWM

82

CIWM

78

Nota 5: Human body model,100 pF discharged'through a 1.5 kn resistor.
Note 6: See AN-450 "Surface Mounting Methods and Their Effect on Product Reliability" or'the section titled "Surface Mount" fou~d in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Nota 7: Typicals represent most likely parametric norm.
Note 8: Umits are guaranteed to National's AOOL (Average Outgoing aual~ Level).
Nota 9: Accuracy may degrade if isH is shorter than the value specHied. See curves of Accuracy VB isH.

"

,

"

-

,

"

2-418

Typical Performance Characteristics
Zero (Offset) Error
vs Reference Voltage
to

Linearity Error
vs Reference Voltage
1.0

= DYcc = +5V
= 25°C

AVec

fA

o.s

~

...

~

\

0.6

~

:il
i5

0

e;
0

I'

0,4

;;:

r-....

0,2

.....

r:
~::;

~

AVec :I DVcc
TA = 25°C

0.8

1

2

3

4

......

0,4

"'

0,2

to
]: 0.9

I

g 0.8

-.1. 1 ,I,

~

~

Q

0.7
0.6

DVec

0.5

....,e:::;

DVcc = 5.DV

r-

0,4

I
~

~~ee 1= D~cc ~

700

~~

0.3

!Ii

;:

0.2

~

0.1

u

SOD

AMBIENT TEMPERATURE (OC)

0400

%

300

~0

200

;:

~

800
700

r;;: 2~i.c

A?'

I

I

500

/

400

/. , TA = -55·C

0

i
8

=

f-"'"

w

%

Mode 1
Vee
SV
VREr = 5V

300

20

30

40

50

60

70

1200
]:

1100

Mode 2

~vec

~ 1000

!

900

~
%
8

.!o""'::

800
AVec = DVec = 5.5V
700
600
-55 -35 -15 5

80

25 45 65 85 105 125

Spectral Response with
100 kHz Sine Wave Input
Vcc .. Vur =+5V
V1M =4.S5Vp-p

0

TA",Z5"C
Sourc.lmlMdanc.= 50Q

m

Sampnng Rat. =512kH:r

~ -20

~

V

200

;

Node 2
Yee = SV
YREr = 5V

S/(N+D)= !59.21dB

-40
-60
-80

I

II

I....

0

10

20

30

50

40

60

70

80

SPEED-UP RESISTOR. RSA (kll)

0

I

"', ,.,'

-100

SPEED-UP RESISTOR. RSA (kll)

f-r\-

AVec = OVee = 5.0V -

liio.i

%

iii

~ 4.~V

= DVec

~~

-

AMBIENT TEMPERATURE (OC)

0
10

25 45 65 85 105 125

Conversion Time
vs Temperature

= 250C

TA

100

0
0

0
-55 -35 -15 5

20

12~OC

....
"§

TA 1=

600

"

100

I-I I

I

I

AVec = ".SV

AMBIENT TEMPERATURE (OC)

25 45 65 85 105 125

!
;:

~ VTA = -55°C

u

HT

= ~.5V
= S.OV

10

Conversion Time
vs Speed-Up Resistor
(ADC10462 and ADC10464 Only)

600

't."'

--

AMBIENT TEMPERATURE (OC)

Conversion Time
vs Speed-Up Resistor
(ADC10462 and ADC10464 Only)

7' I-

~

....

AVec

"~

5

~ r-tAVec = DVcc 7";:;';
I "1 I -I I

400
-55 -35 -15 5

25-456585105125

4!5V

~~~'I

600

0

TA=I~

I

20

Q

iii

500

4

AVec = DVec = 5.0V

%

0.0
-55 -35 -15 5

30 ....

Conversion Time
vs Temperature

_u

= 4.SV

3

.... rr..... ,....

REFERENCE VOLTAGE. VRE,+ - Vm _ (V)

800

OVec = 5.5V

2

AVec

"'U

:ii
1

40

u

Ii

Digital Supply Current
vs Temperature

~
~

:1

0.6

5

REFERENCE VOLTAGE. Vm+ - VRE ,- (V)

~

= +SY

0.0

0.0

is

Analog Supply Current
vs Temperature

50

100

150

J.,
"1"

200

250

FREQUENCY (kHz)

Spectral Response with
100 kHz SIne Wave Input
20

vcc=vREr=+sv
VIN= ..·85Vp"'p

0
m

~

~

:I
(;

TA=2SOC

SOll.rctlmp,danc."SOOl),

-20

Sampling Rat, .. 512 kHz

=

S/(H+D) 59.11 dB

-40
-60

in

-80

I

II

I I

J.JLI

-'" '1,00

I''''''

-100

0

50

100

150

~REQUENCY

200

250

(kHz)

TL/HI1110B-l

2419

Typical Performance Characteristics (Continued)
. Signal-to-Noise + THD Ratio
vs Signal Frequency

•

70

Linearity Change
vs Speed-Up Resistor
(ADC10462 and ADC10464 Only)
Nod,1
Vee = 5Y

60~--~~-HHtH---~

VREf

50 f-'-~f-H-hf++H--+--i

=5Y

<40 f--f-H-+1f++H--+--i

=

Vee VREF = +5V
Vltt = 4.85 Vp_p
TA=250C

30-

20-

I~\('

Source Impedance =6000.

10-

Sampling Rat, = 512kHz:

o
20k

Linearity Change
vs Speed-Up Resistor
(ADC10462 and ADC10464 Only) .

=

~
"""'"

o
o

TA = -SS"C

Linearity Error Change
vs Sample Time
~

0.9

;

0.8

~

0.7

~

0.6

~

o.s

Mode I
Veo = sv
VREf

= sv

T. = 2S"C

~ '0.3

~

TA = 125°C

10

<40

30

f5 0.4

= 25°C

~

~J'4w
~

1.0

Mod. 2
Vee
SV
VREF' = 5V

TA

TA '= 12SOC

SPEED-UP RESISTOR, RSA (kO)

FREQUENCY (Hz)

•

"'(

o

200k

SOk lOOk

TA = -S5"C

~=2S"Ct

!i

I

D.2
0.1

0.0

20

I'.
D 20<4060601001201<40160160200

30

SPEED-UP RESISTOR, RSA (kO)

SAMPLE TIME, isH (no)
TL/H/11108-2

2-420

.-------------------------------------------------------~-----------.~

c
o....

TRI-STATE Test Circuits and Waveforms

C)

A-

....

en
ADC10461
ADC10462
ADC10464

~
c
o
....

DATA
I-.....--~-+ OUTPUT

C)
~

TLIH111108-4

en
I\)

~

c
o....

TLlH111108-3

C)

_

Vee

RD

--1-1,.--

it
A-

GND

RL
ADC10461
DATA
ADC10462 I-"'--I~ OUTPUT
ADC10464

DATA Vee
OUTPUT VOL _ _ _""
TLIH111108-6

TLIH111108-5

Timing Diagrams

Cs~\-.-i-----""
,

' __---'I

,

-,rr----------------------,,
x,"'....,..-------------------:-+

5/H ----~~~H
50
(ADC10462 and
ADC10464 only)

51

==x......:
--:

:=J(

VALID
'-- t MS '
VALID

,

tMH

X,.-.------------------

(ADC10464 only)

\

~

1

: _ _ _ _ ..1,
_

'--:

tCONV

~
'

I

000-009 - - - - - - - - - - -

tlNTH

,1,,-----

--------+-------~'
iNT

:--

:

t Acel - :
I

:-- - :

' :-- t lH, toH

";"...I>,-------

I I

+- - - - - - - - - - - - - - - - -'- ~"'__

TLIH111108-7

FIGURE 1. Mode 1. The conversion time (tCONV) is set by the internal timer.

2·421

•

~ r-~------------------------------------------------------------------------------,

!...

Timing Diagrams (Continued)

o
c

i...
o

o
c
~

...~
...o
o

cc(

\

,

:,

'------

,.....c

- - - - - - . . . .1-,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

5/H and

Ro

,

------~\~________________________1_:~~~--:------.

J).c'-VA-L-,D~),c~-------------------

SO
(ADC10062 and _ _ _
ADC10064 only)
lus-:

51
(ADC10064 only)

___JX

. .- - - - - _

'-'
-: :--IuH
VALID

X~

___________________.;_------

:!-o.-------

'cRD - - - - - - - . . , .,

,
\'

,
:

I

,.
000 - 009

t ACC2

-

:

• :

~NTH

',----'I
' ,
;.-

r

~'r-- ~H' IoH

_ _ _ _ _ _I'!!'!!"!!"!!"!!"l!'!!"!!"!!"!!"l!'!!"!!"!!"!!"l!'!!"!!"!!"!!"l!'!!"!!"!!"!!"l!'!!"!!"!!·-Da-t-a-V-al-id.....~ _____ •

,
TUH111108-8

FIGURE 2. Mode 2 (RD Mode). The conversion time (tcRD) includes the
sampling time and is determined by the Internal timer.

Simplified Block Diagram
VREF +

VREF +

DB9 (IotSB)

6 Bit Flash A/D
(6 MSBs)

VREFVIN', VINO"

DBB

VREF-

DB7

VIN1"

6

DB6

VREF +

VIN2•••

DBS

6 Bit DAC

VIN3 •••

DB4
VREF -

DB3
DB2

VREF +

---s.-

AVec
DVcc

DBI

4 Bit Flash A/D
(4 LSBs)

DBO (LSB)

4

VREF-

SPEED
ADJ"

iNT

GND'

AGND"

DGND"

cs

Rii

5/H

SO"

51'"
TL/H/11108-9

'ADC10461 Only
"ADC10462 and ADC10464 Only
'''ADC10464 Only

2·422

l>
t:J

o....

Connection Diagrams

Q

Dual-In-Line Package
DVcc

iNi
S/H
RD

cs

10

20

DBO (lSB)

2

19

OBI

18

DB2

17
5

ADC10461

DVcc

DBO (lSB)

10

.;0.

....

en

Dual-In-Line Package

Dual-In-Line Package
DVcc

DB3

iNi
S/H
RD

DB3

iNi
S/H
RD

16

DB4

cs

DB4

cs

OBI
DB2

10

28

2

27

DB'1

26

DB2

25

DB3

24

DB4

23

DB5

22

DB6

4

DBO (lSB)

);

g....
Q
.;0.

en

N
.....

l>
C

AVec

15

DB5

SO

DB5

SO

VREF-

14

DB6

AVec

DB6

51

Y,N

13

DB7

VREF-

DB7

AVec

21

N.C.

Q
.;0.

VREF +

12

DBS

V,NO

DB8

VREF-

20

DB7

.;0.

11

DB9 (MSB)

GND

10

TLlHlf110B-l0

Top View

ADC10462

7

ADC10464

Y'N!

10

DB9 (~SB)

V,NO

19

DB8

VREF +

11

SPEED ADJ

18

DB9 (~SB)

AGND

12

Y'N!
V,N2

17

SPEED ADJ

V,N3

16

DGND

15

AGND

13

DGND
TL/HIf 11 OB-l1

Top View

VREF +

14

o
....
en

TLlH/l!I08-12

Top View

Pin Descriptions
DVcc, AVee These are the digital and analog positive supply voltage inputs. They should always be
connected to the same voltage source, but
are brought out separately to allow for separate bypass capacitors. Each supply pin
should be bypassed with a 0.1 ,...F ceramic
capacitor in parallel with a 10 ,...F tantalum
capacitor to ground.
INT
This is the active low interrupt output. INT
goes low at the end of each conversion, and
returns to a high state following the rising
edge of RD.
5/H
This is the Sample/Hold control input. When
this pin is forced low (and CS is low), it causes the analog input signal to be sampled and
initiates a new conversion.
RD
This is the active low Read control input.
When this RD and CS are low, any data present in the output registers will be placed on
the data bus.
CS
This is the active low Chip Select control input. When low, this pin enables the RD and
5/H pins.
50,51
On the multiple-input devices (ADC10462
and ADC1 0464), these pins select the analog
input that will be connected to the AID during
the conversion. The input is selected based
on the state of SO and 51 when 5/H makes
its High-to-Low transition (See the Timing Diagrams). The ADC10464 includes both SO
and 51. The ADC10462 includes just SO, and
the ADC1 0461 includes neither.

These are the reference voltage inputs. They
may be placed at any voltage between GND
and Vee, but VREF+ must be greater than
VREF-. An input voltage equal to VREFproduces an output code of 0, and an input
voltage equal to (VREF + - 1 LSB) produces
an output code of 1023.
These are the analog input pins. The
Y,N, V,NO,
ADC10461 has one input (V,N), the
V'N1, V'N2,
ADC10462 has two inputs (V,NO and V,N1),
V,N3
and the ADC10464 has four inputs (V, NO,
V'N1, V,N2 and V,Nal. The impedance of the
source should be less than soon for best accuracy and conversion speed. For accurate
conversions, no input pin (even one that is
not selected) should be driven more than
50 mV above Vee or 50 mV below ground.
GND, AGND, These are the power supply ground pins. The
DGND
ADC10461 has a single ground pin (GND),
and the ADC1 0462 and ADC1 0464 have separate analog and digital ground pins (AGND
and DGND) for separate bypassing of the analog and digital supplies. The ground pins
should be connected to a stable, noise-free
system ground. For the devices with two
ground pins, both pins should be returned to
the same potential.
DBO-DB9
These are the TRI-STATE output pins.
SPEEDADJ (ADC10462 and ADC10464 only). This pin is
normally left unconnected, but by connecting
a resistor between this pin and ground, the
conversion time can be reduced. See the
Typical Performance Curves and the table of
Electrical Characteristics.

2-423

•

Functional Description
The ADC10461 , ADC10462 and ADC10464 digitize an analog input signal to 10 bits accuracy by performing two lowerresolution "flash" conversions. The first flash conversion
provides the· six most significant bits (MSBs) of data, and
the second flash conversion provides the four least significant bits LSBs).

To perform a conversion, the estimator compares the input
voltage with the tap voltages on the seven resistors'on the
left. The estimator decoder then determines which MSB
Ladder tap pOints will be connected to the sixteen comparators on the right. For example, assume that the estimator
determines that VIN is between 11/16 and 13/16 of VREF.
The estimator decoder will instruct the comparator MUX to
connect the 16 comparators to the taps on the MSB ladder
between 10/16 and 14/16 ofVREF. The 16 comparators will
then perform the first flash conversion. Note that since the
comparators are connected to ladder voltages that extend
beyond the range indicated by the estimator circuit, errors in
the estimator as large as 1/16 of the reference voltage
(64 LSBs) will be corrected. This first flash conversion produces the six most significant bits of data-four bits in the
flash itself, and 2 bits in the estimator.

Figure 3 is a simplified block diagram of the converter. Near
the center of the diagram is a string of resistors. At the
bottom of the string of resistors are 16 resistors, each of
which has a value 1/1024 the resistance of the whole resistor string. These lower 16 resistors (the LSB Ladder) therefore have a voltage drop of 16/1024, or 1/64 of the total
reference voltage (VREF+ - VREF-) across them. The remainder of the resistor string is made up of eight groups of
eight resistors connected in series. These comprise the
MSB Ladder. Each section of the MSB Ladder has % of the
total reference voltage across it, and each of the LSB resistors has 1164 of the total reference voltage across it. Tap
points across these resistors can be connected, in groups
of sixteen, to the sixteen comparators at the right of the
diagram.

The remaining four LSBs are now determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input voltage (as determined by the first flash) is subtracted
from the input voltage and compared with the tap points on
the sixteen LSB Ladder resistors. The result of this second,
four-bit flash conversion is then decoded, and the full 10-bit
result is latched.
Note that the sixteen comparators used in the first flash
conversion are reused for the second flash. Thus, the multistep conversion technique used in the ADC10461 ,
ADC10462, and ADC10464 needs only a small fraction of
the number of comparators that would be required for a
traditional flash converter, and far fewer than would be used
in a conventional half-flash approach. This allows the
ADC10461 , ADC10462, and ADC10464 to perform highspeed conversions without excessive power drain.

On the left side of the diagram is a string of seven resistors
connected between VREF+ and VREF-. Six comparators
compare the input voltage with the tap voltages on this resistor string to provide a low-resolution "estimate" of the
input voltage. This estimate is then used to control the multiplexer that connects the MSB Ladder to the sixteen comparators on the right. Note that the comparators on the left
needn't be very accurate; they simply provide an estimate of
the input voltage. Only the sixteen comparators on the right
and the six on the left are necessary to perform the initial
six-bit flash conversion, instead of the 64 comparators that
would be required using conventional half-flash methods.

V~.----~--+---------;------,

13/16

11/16

9/16

~

16/1024

~

7/16

i:::l
5/16

3/16

~

DBO-DB9

10

16
I
I
I

1/'024 '

VREF-

TLlHI11108-13

FIGURE 3. Block Diagram of the Multistep Converter Architecture

2-424

l>

o

Applications Information
1.0 MODES OF OPERATION
The ADC1 0461, ADC1 0462, and ADC10464 have two basic
digital interface modes. Figure 1 and Figure 2 are timing
diagrams for the two modes. The ADC10462 and
ADC10464 have input multiplexers that are controlled by
the logic levels on pins So and S1 when S/H goes low.
Table I is a truth table showing how the input channneis are
assigned.

1.953 mV). Note, however, that linearity and offset errors
become larger when lower reference voltages are used.
See the Typical Performance Curves for more information.
For this reason, reference voltages less than 2V are not
recommended.
In most applications, VREF- will simply be connected to
ground, but it is often useful to have an input span that is
offset from ground. This situation is easily accommodated
by the reference configuration used in the ADC10461 ,
ADC10462, and ADC10464. VREF- can be connected to a
voltage other than ground as long as the voltage source
connected to this pin is capable of sinking the converter's
reference current (12.5 mA Max @ VREF = 5V). If VREF- is
connected to a voltage other than ground, bypass it with
multiple capacitors.

Mode 1
In this mode, the S/H pin controls the start of conversion.
S/H is pulled low for a minimum of 250 ns. This causes the
comparators in the "coarse" flash converter to become active. When S/H goes high, the result of the coarse conversion is latched and the "fine" conversion begins. After
600 ns (typical), INT goes low, indicating that the conversion
results are latched and can be read by pulling RD low. Note
that CS must be low to enable S/H or RD. CS is internally
"ANDed" with S/H and RD; the input voltage is sampled
when CS and S/H are low, and data is read when CS and
RD are low. INT is reset high on the rising edge of RD.

ADC10464

ADC10462

So

Channel

So

Channel
VINO

0

0

VINO

0

0

1

VINI

1

1

0

VIN2

1

1

o
~
.....

.......
l>

o
o
.....
o
.j:o.
Q)

N
.....

l>

o
o
.....
o

.j:o.
Q)
.j:o.

Since the resistance between the two reference inputs can
be as low as 400n, the voltage source driving the reference
inputs should have low output impedance. Any noise on either reference input is a potential cause of conversion errors, so each of these pins must be supplied with a clean,
low noise voltage source. Each reference pin should be bypassed with a 10 ,...F tantalum and a 0.1 ,...F ceramic.

TABLE I. Input Multiplexer Programming
51

o
.....

3.0 THE ANALOG INPUT
The ADC1 0461 , ADC10462, and ADC10464 sample the analog input voltage once every conversion cycle. When this
happens, the input is briefly connected to an impedance
approximately equal to 600n in series with 35 pF. Short-duration current spikes can therefore be observed at the analog input during normal operation. These spikes are normal
and do not degrade the converter's performance.
Large source impedances can slow the charging of the
sampling capaCitors and degrade conversion accuracy.
Therefore, only signal sources with output impedances less
than 500n should be used if rated accuracy is to be
achieved at the minimum sample time (250 ns maximum). If
the sampling time is increased, the source impedance can
be larger. If a signal source has a high output impedance, its
output should be buffered with an operational amplifier. The
operational amplifier's output should be well-behaved when
driving a switched 35 pF/600n load. Any ringing or voltage
shifts at the op amp's output during the sampling period can
result in conversion errors.

VINI

(b)

VIN3

(a)
Mode 2
In Mode 2, also called "RD mode", the S/H and RD pins
are tied together. A conversion is initiated by pulling both
pins low. The AID converter samples the input voltage and
causes the coarse comparators to become active. An internal timer then terminates the coarse conversion and begins
the fine conversion. 850 ns (typical) after S/H and RD are
pull low, INT goes low, indicating that the conversion is
completed. Approximately 20 ns later the data appearing on
the TRI-STATE output pins will be valid. Note that data will
appear on these pins throughout the conversion, but until
INT goes low the data at the output pins will be the result of
the previous conversion.

Correct conversion results will be obtained for input voltages greater than GND - 50 mV and less than V+ +
50 mV. Do not allow the signal source to drive the analog
input pin more than 300 mV higher than AVec and DVee, or
more than 300 mV lower than GND. If an analog input pin is
forced beyond these voltages, the current flowing through
the pin should be limited to 5 mA or less to avoid permanent
damage to the IC. The sum of all the overdrive currents into
all pins must be less than 20 mA. When the input signal is
expected to extend more than 300 mV beyond the power
supply limits, some sourt of protection 'scheme should be
used. A simple network using diodes and resistors is shown
in Figure 4.

2.0 REFERENCE CONSIDERATIONS
The ADC10461 , ADC10462, and ADC10464 each have two
reference inputs. These inputs, VREF + and VREF _, are fully
differential and define the zero to full-scale range of the
input signal. The reference inputs can be connected to span
the entire supply voltage range (VREF- = OV, VREF+ =
Vecl for ratiometric applications, or they can be connected
to different voltages (as long as they are between ground
and Vecl when other input spans are required. Reducing
the overall VREF span to less than 5V increases the sensitivity of the converter (e.g., if VREF = 2V, then 1 LSB =

2-425

•

~

CD
~

C)
..-

(.)

C

 V+) the absolute value of current at that pin should be limited
to 5 rnA or less. The 20 rnA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 rnA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 8JA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po ~ (TJMAX - Tp,)18JA or the number given in the Absolute Maximum Ratings, whichever Is lower. In most
cases, the maximum derated power dissipation will be reached only during fault conditions. For these devices, TJMAX for a board-mounted device can be found
from the tables below:
ADC10662

Suffix
GIN
GIWM

ADC10664

Suffix

BJArC/W)
60
82

GIN
GIWM

9JArC/W)

53
78

Note 5: Human body model, 100 pF discharged through a 1.5 kG resistor.
Note 6: See AN·450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section titled "Surface Mount" found in a current National
Semiconductor Unear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals represent most likely parametric norm.
Note 8: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 9: Accuracy may degrade if tSH is shorter than the value specified. See curves of Accuracy VB isH.
Note 10: THD, SNR, and ENOS are tested in Mode 1. Measuring these quantities in Mode 2 yields similar values.

fI

2-431

i...

Typical Performance Characteristics

i...

1.0

Linearity Error
vs Reference Voltage
1.0

0.8

'iii

'iii

a

I

i

'\.

G.4

g

a

~

0.'

~~

" r-....

0.2

AVec = avec = +sv

'3

5

REFERENCE VOLTAGE, VRE'. - VIEF_ (V)

I

0.8
0.7

I
u

~

~

= 4.5V
DVec

= 5.0V f--

~

0.2
I
O.
0.0
-55 -35 -15 5 25 45 65 85 105 125

~,

"

0.2

j

400

oJ
;:

380

'"z
~

8

AVec

1,/

320

~

~

"z

500

~

300

8

200

;:

9

200

z

Mod. I
Vee = 5V

100

o
o W

H

50 4D 50 50

"sA

'/
,I'

~

'"

-55-35-15 5 25 45 65 85 105125
'TEMPERATURE (06)

~

'/ 'AY
/

400

50

Spectral Response with
100 kHz Sine Wave Input
20

I---'"

--

TA.

V

Source Imptdance =son
Sampllnll Rat.- 512 kHz

§ -40

S/(N+D)=51.2Sd

~

Vee • 5V

-60
-60

VREr = SV

-100
10 20 30 40 50 60 70 80
SPEED-UP RESISTOR,

(kll)

V,N -4.85Vp-p
T,,=25 O C

'iii
3 -20

:;I

Mod,2

o
o

vcc "V.EF=+5V

= 25°C

' / T• • -55°C

100

VREr ;: 5V

SPEED-UP RESISTOR,

./

.50

350

300
-55 -35-15 5 25 45 65 85 105125

:; 600

= -55°C

I

AVec = DVcc = 5,OV

m
8 400

340

700 T.'. J5 0 C

S
8

~~~.~6

550

Conversion Time vs
Speed-Up Resistor

~

(OC)

Conversion Time
vs Temperature

'"

li

500

::;rTA

TEMPERATUR~

;:

800

400

AVee • 4.5V

Ii1

360

Conversion Time vs
Speed-Up Resistor

Jz 300

AMBIENT

TEMPERATURE (OC)

= 12~ ;7 I--' ~2JOC

,

-I'"""

.Y
..; 500

BOO

TA

-

AVec' 5.0V

-55 -35-15 5 25 45 65 85 105125

!

=DVcc = S.ov

....

l- t-"
I-

o

600

'.od, !!
's. =,..Ok~ 1.

AM81ENT TEMPERATURE (OC)

]:

t:;:

REFERENCE VOLTAGE, VIE" - VIE'_ (V)

,~

0.3

I-'"

.....

0.4

]< 420
I..:::

AVcr; • 5.5V

0.6

440

0.6 DVec
0.5
G.4

40

30

Conversion ,rIme
vs Temperature

I

-D~ec ~' 5!5V

~

O.B

Digital Supply Current
vs Temperature
'-:C 1.0
.5.. G.9

1

0.0 '--'---'--'--'_.1--'--'--'
I
5

0.0
I

Analog Supply Current
vs Temperature

TA = 25°C·

TA ;: 25°C

(J

!i

Zero (Offset) Error
va Reference Voltage
AVee = DVee = .5V

"s.

I

-,.'
o 50

I
100

I
ll.
150

IJ.
200

250

FREOUENCY (kHz)

(kll)

Spectral Response with
100 kHz Sine Wave Input
20

=

Vee = VREF +5V
V.N=4.85Vp_p

T,,=25 0 C

'iii'
Sourct ImptdanCi =6004
.:9. -20f--f--t SampllngRate=512kHz
d
S/(H+D) = 59.11 d

~ -40f--f--t--t--+--~

I -60f--f--t--t--+--~
-80 1+11r:+-+tt
1-r.rI--:--tH
II-t-ti

IJ..&,

••

II.

-100~~~~f!~~!1~~~
o

50

100

150

200

250

FREQUENCY (kHz)
TUH/11192-1

2-432

r--------------------------------------------------------------------,~

~
....

Typical Performance Characteristics (Continued)
Signal-to-Noise + THO Ratio
va Signal Frequency

....
~

4

70

....o

(")

Wod.1

Vee = 5V

60

vR£f = sv

S!

~

I

Linearity Change
vs Speed-Up Resistor

E

50

0

i

~

JO

vee =VR[F = +5V

-

~~ ~~25~C
TA:

Y,N =USVp_ p

~ i:l
20

TA = -55°C

TA ""25°C
Source Impedance D 6O011
Sampling Rat. = 512kHz

10

'~OC

1'< ~~
o

o

10k

20k

SIlk toOk

o

200k

Linearity Change va
Speed-Up Resistor

....

I..
u

~

TA a -550C

o
o

TA " 25·C

~

~

TA ., 125.~

~

I

JO

lIsA

~

(kO)

Mod. I
Vee • 5Y
vREr = 5V
TA. 250 e

0.7
0.6
0.5

0.4
0.3
0.2
0.1
0.0

=

~

......
020~lIIl1Oto012OM01601I10200

10
SPEEO-UP RESISTOR,

1.0

os
~ 0.8

Vee a SV
VREf = 5V

~~

20

Linearity Error Change
vs Sample Time

"ode 2

~

10

SPEEO-UP RESISTOR,

FREQUENCY (Hz)

lIsA

SAMPLE TIME, isH (n,)

(kO)

TLlH/11192-2

2-433

TRI-STATE Test Circuits and Waveforms
Vce

I-"'_"__

",

~ DATA.
OUTPUT

TUH/",92-4
TUHi"'92-3

_

Vce--t'~~

RD

1\
ADC10662
ADC10664

-

IG.

DATA
OUTPUT

DATA : :
OUTPUT V
.
OL

TUHI11'92-6
TUH/,"'92-5

Timing Diagrams

cs ~:

.

i.~----------\'.

I

:::::x
•

50

____JI

___~' 'I"--------------~------\::~H -i
i

5/H

--=il-~H

~"

I

I

:VALID

I

I

,._:_ _ _ _ _ _ _ _ _~---~---------

*"....;1_______________________

- : '-\lSi I
.....:
H\lH
_ _ _ _ _-

--A
~

51
(ADC10664 only)

- - -

I~

VALID

X,,-I___________~.----------:
\
1
I

I

I

I

I~

II

I•

L- --l
tcONV

_

•

:-'NTH

II~

:

r-----------~---------------..:-<
:

000-009

_ _.J,

II

lAce, --:

_ _ __

II r-

-l .

I

~H·IoH

>-----I

TUH/",92-7

FIGURE 1. Mode 1. The conversion time (tcONV) Is set by the Internal timer.

2-434

r--------------------------------------------------------------------,.~

C

Timing Diagrams (Continued)

---""\:

o

.;...

I

o

,
,
,~I---------------------------..J

s/H

and

Rii

------+~~~

_____________~-----,(J:'~'t:---:--------

.:

so

----~).c'--vA-L-,D~),c~------------------------------------.l--------____
~

SI

(ADCI06U .only)

I

X'----------------------------------------------

:•

'cRD

•,

,
:

\"

.

,

:.
DOO -D09

C

.....
o
8l
.a:o.

.',,

~'us:

......
.--'uH
VALID.

--"'X

~
(")

I

tACC2

;

.:

: - - \NTH

','

.

:.

--,';-

.

- - - - - - _ DataV.lid

~H'

'oH

>-----,

TLlH/11192-8

FIGURE 2. Mode 2 (RD Mode). The conversion time (tcRD) Includes the
sampling time and is determined by the internal timer.

Simplified Block Diagram
VREF+

VREF +
...-_ _ _ _ _ _.... 6-Bit Flash AID
(6 MSBs)

VREF-

VINO

--I--I......~--

VREF- -

1---40++1

....._ - -......

DB7

VINI .......--I......- - V ' .......--1......- _ _
IN2
VIN3 '

6

DBIi
DBS

-I-t......-..~"'"""-(

6-Bit DAC

DB4

' -_ _ _ _....-- VREF-

DBl
DB2

VREF +

AVec
DVcc

DB9 (MSB)
DBS

6

"""64

.A/D I----I-M
(4 LSBi)
4

L -_ _ _.... 4-BII Flash

VREF- -

DBI

fI

DBD. (LSB)

....._ - - _..

SPEED

ADJ

GND'

AGND

DGND

cs

Rii

s/H

SO

Sl'
TL/H/11192-9

'ADC10664 Only

2-435

....
C&)
C&)

c

Connection Diagrams

U

Q

e(
......
N

II...
U

Q

e(

Dual-In-Llne Package

Dual-In-Llne Package

24

DBO (lSB)

23

OBI

iNT

s/H
Ro

DB2

5/H
Ro

DB2

DB3

Cs

DB4

Cs

DB4

DB5

SO

DB5

AVec

DB6

51

DB6

VRErVINO

DB7

AVec

N.C.

DB8

VRErVINO

DB7

DB9 (MSB)
SPEED ADJ

VIN1

DBB (MSB)

DGND

VIN2
VIN3

SPEED ADJ
DGND

VREr.

AGND

DVec

10.

INT

ADC10662

VIN1
13

DVec

10

DBO (lSB)

DB3

DB8

TL/H111192-10

Top View

28

TL/H/11192-11

, Top View

Pin Descriptions
DVee, AVee These are the digital and analog positive supply voltage inputs. They should always be
conne~ed to the same voltage source,' but
are brought out separately to allow for separate bypass capacitors. Each supply pin
should be bypassed with a 0.1 /tF ceramic
capacitor in parallel with a 10 /tF tantalum
capacitor, to ground.
This is the active low interrupt output. iiii'i"
goes low at the end of each conversion, and
returns, to a high state following the rising
edge of AD.
'S/H
This is th!l Sample/Hold control Input. When
this pin is forced low (and <:;'S is low), it causes the analog input Signal to be sampled and
initiates Ii new conversion.
AD
This is the active low Aead control input.
When this 'lID and <:;'S are low, any data present in the output registers will be placed on
the data bus.
This is the active low Chip Select control input. When low, this pin enables the AD and
'S/H pins.
SO,SI
These pins select the analog input that will be
connected to the AID during the conversion.
The input is selected based on the state of
SO and 51 when 'S/H makes its High-to-Low
transition (See the Timing Diagrams). The
ADC10664 includes both SO and 51. The
ADC10662 includes just SO.

These are the reference voltage inputs. They
may be placed at any voltage between GND
and Vee, but VREF+ must be greater than
VREF-. An input voltage equal to VREFproduces an output code of 0, and an input
voltage equal to (VREF + - 1 LSB) produces
an output code of 1023.
VINO, VIN1,
These are the analog input pins. The
VIN2, VIN3
ADC10662 has two inputs (VINO and VIN1)
and the ADC10664 hils four inputs (VINO,
VIN1, VIN2 and VIN3). The impedance of the
source should be less than 5000 for best accuracy and conversion speed. For accurate
conversions, no input pin' (even one that is
not selected) should be driven more than
50 mV above Vee or 50 mV below ground.
GND, AGND, These are the power supply ground pins. The
ADC10662 and ADC10664 have separate
DGND
analog and digital groiJnd pins (AGND and
DGND) for separate bypassing of the analog
and digital supplies. The ground pins should
be'connectedto a stable, noise-free system
ground. Both pins should be returned to the
same potential.
DBO-DB9
These are the TAl-STATE output pins.
SPEED ADJ By connecting a resistor between this pin and
ground, the conversion time can be reduced.
The specifications listed in the table of Electrical Characteristics apply for a speed adjust
resistor (AsAl equal to 14.0 kO (Mode 1) or
8.26 kO (Mode 2). See the Typical Performance Curves and the table of Electrical Characteristics.

2-436

Functional Description
The ADC10662 and ADC10664 digitize an analog input signal to 10 bits accuracy by performing two lower-resolution
"flash" conversions . .The first flash conversion provides the
six most significant bits (MSBs) of data, and the second
flash conversion provides the four least significant bits
LSBs).

To perform a conversion, the estimator compares the input
voltage with the tap voltages on the seven resistors on the
left. The estimator decoder then determines which MSB
Ladder tap pOints will be connected to the sixteen comparators on the right. For example', assume that the estimator
determines that VIN is between 11/16 and 13/16 of VREF.
The estimator decoder will instruct the comparator MUX to
connect the 16 comparators to the taps on the MSB ladder
between 10/16 and 14/16 of VREF. The 16 comparators will
then perform the first flash conversion. Note that since the
comparators are connected to ladder voltages that extend
beyond the range indicated by the estimator Circuit, errors in
the estimator as large as 1/16 of the reference voltage
(64 LSBs) will be corrected. This first flash conversion produces the six most significant bits of data-four bits in the
flash itself, and 2 bits in the estimator.
The remaining four LSBs are now determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input voltage (as determined by the first flash) is subtracted
from the input voltage and compared with the tap pOints on
the sixteen LSB Ladder resistors. The result of this second,
four-bit flash conversion is then decoded, and the full 1O-bit
result is latched.
Note that the Sixteen comparators used in the first flash
conversion are reused for the second flash. Thus, the mUltistep conversion technique used in the ADC10662 and
ADC10664 needs only a small fraction of the number of
comparators that would be required for a traditional flash
converter, and far fewer than would be used in a conventional half-flash approach. This allows the ADC10662 and
ADC10664 to perform high-speed conversions without excessive power drain.

Figure 3 is a simplified block diagram of the converter. Near
the center of the diagram is a string of resistors. At the
bottom of the string of resistors are 16 resistors, each of
which has a value 1/1024 the resistance of the whole resistor string. These lower 16 resistors (the LSB Ladder) therefore have a voltage drop of 16/1024, or 1/64 of the total
reference voltage (VREF+ - VREF-) across them. The remainder of the resistor string is made up of eight groups of
eight resistors connected in series. These comprise the
NiSB Ladder. Each section of the MSB Ladder has Va of the
total reference voltage across it, and each of the LSB resistors has 1/64 of the total reference voltage across it. Tap
points across these resistors can be connected, in groups
of 'sixteen, to the sixteen comparators at the right of the
diagram.

On the left side of the diagram is a string of seven resistors
connected between VREF+ and VREF-. Six comparators
compare the input voltage with the tap voltages on this resistor string to provide a low-resolution "estimate" of the
input voltage. This estimate is then used to control the multiplexer that connects the MSB Ladder to the sixteen comparators on the right. Note that the comparators on the left
needn't be very accurate; they simply provide an estimate of
the input voltage. Only the sixteen comparators on the right
and the six on the left are necessary to perform the initial
six-bit flash conversion, instead of the 64 comparators that
would be required using conventional half-flash methods.
V,N

-+----+-----,

VREr• - -.....

II

13/16

11/16

9/16

7/16

§
5/16

~

,6
I
I
I

1/1024 I
3/16

VREF-

TLlH/11192-12

FIGURE 3. Block Diagram of the Multistep Converter Architecture

2·437

Applications Information
Note, however, that linearity and offset errors become larg·
er when lower reference voltages are used. See the Typical
Performance Curves for more information. For this reason,
reference voltages less than 2V are not recommended.

1.0 MODES OF OPERATION
rhe ADC1 0662 and ADC10664 have two basic digital inter·
face modes. Figure 1 and Figure 2 are timing diagrams for
th.9 two modes. The ADC10662 and ADC10664 have input
multiplexers that are controlled by the logic levels on pins
So anq S1 when S/H goes low. Table I is a truth table show·
ing how,the input channneis are assigned.

In most applications, VREF- will simply be connected to
ground, but it is often useful to have an input span that is
offset from ground. This situation is easily accommodated
by the reference configuration used in the ADC10662 and
ADC10664. VREF- can be connected to a voltage other
than ground as long as the voltage source connected to this
pin is capable of sinking the converter's reference current
(12.5 mA Max @ VREF = 5Y). If VREF- is connected to
voltage other than ground, bypass it with multiple capaci·
tors.
'

Mode 1
In this mode; the S/H pin controls the start of conversion.
~/H is pulled low for a'minimum of 150 ns. This causes the
comparators in the "coarse" flash converter to become ac·
tive. When ~tH goes high, the result of the coarse conver7
sion is latched and the "fine" conversion begins. After
360 ns (typical), INT goes low; indicating that the conversion
results are latched and can be read by pulling Rl5low. Note
that ~ must be low to enable S/H or RD. ~ is internally
"ANDed" with S/H and RD; the input voltage is sampled
when ~ and ~/H are low, and data is read when CS and
RD are low. i1'ii'f is reset high on the rising edge of RD.

a

Since the resistance between the two reference inputs can
be as low as 400n, the voltage source driving the reference
inputs should have low output impedance. Any noise on ei·
ther reference input is a potential cause of conversion er·
rors, so each of these pins must be supplied with a clean,
low noise voltage source. Each reference pin should be by·
passed with a 10 ,...F tantalum and a 0.1 ,...F ceramic.

TABLE I. Input Multiplexer Programming
ADC10664
Channel

ADC10662

So

Sl

So

0

0

VINO

0

0

1

VINI

1

1

0

VIN2

1

1

3.0 THE ANALOG INPUT
The ADC10662 and ADC10664 sample the analog input
voltage once every conversion cycle. When this happens,
the input is briefly connected to an impedance approximately equal to 600n in series with 35 pF. Short·duration current
spikes can therefore be observed at the analog input during
normal operation. These spikes are normal and do not de·
grade the converter's performance.
Large source impedances can slow the charging of the
sampling capaCitors and deg'rade conversion accuracy.
Therefore, only signal sources with output impedances less
than 500n should be used if rated accuracy is to be
achieved at the minimum sample time (250 ns maximum). If
the sampling time is increased, the source impedance can
be larger. If a signal source has a high output impedance, its
output should be buffered with an operational amplifier. The
operational amplifier's output should be well·behaved when
driving a switched 35 pF/600n load. Any ringing or voltage
shifts at the op amp's output during the sampling period can
result in conversion errors.
Correct conversion results will be obtained for input volt·
ages greater than GND - 50 mV and less than V+ +
50 mY. Do not allow the signal source to drive the analog
input pin more than 300 mV higher than AVec and DVec, or
'more than 300 mV lower than GND. If an analog input pin is
forced beyond these voltages, the current flowing through
the pin should be limited to 5 mA or less to avoid permanent
damage to the IC. The sum of all the overdrive currents into
all pins must be less than 20 mAo When the input signal is
expected to extend more than 300 mV beyond the power
supply limits, some sourt of protection scheme should be
used. A simple network using diodes and resistors is shown
in Figure 4.

Channel
VINO
VINI

(b)

VIN3

(a)
Mode 2
In Mode 2, also called "RD mode", the ~/H and RD pins
are tied together. A conversion is initiated by pulling both
pins low. The AID converter samples the input voltage and
causes the coarse comparators to become active. An inter·
nal timer then terminates the coarse conversion and begins
the fine conversion. 470 ns (typical) after 5tH and RD are
pulled low, i1'ii'f goes low, indicating that the conversion is
completed. Approximately 20 ns later the data appearing on
the TRI·STATE output pins will be valid. Note that data will
appear on these pins throughout the conversion, but until
INT goes low the data at the output pins will be the result of
the previous conversion.
2.0 REFERENCE CONSIDERATIONS
The ADC10662 and ADC10664 each have two reference
inputs. These inputs, VREF+ and VREF-, are fully differen·
tial and define the zero to full·scale range of the input Signal.
The reference inputs can be connected to span the entire
supply voltage range (VREF- = OV, VREF+ = Vee) for
ratiometric applications, or they can be connected to different voltages (as long as they are between ground and Vecl
when other input spans are required. Reducing the overall
VREF span to less than 5V increases the sensitivity of the
converter (e.g., if VREF = 2V, then 1 LSB = 1.953 mY).

2-438

Applications Information (Continued)
+5V

ADC10664

. . . .----r---""T"----.,...----r-.......
17

28

DBD (LSB)

14.0k (Mode 1)
!!sA 8.26k (Wode 2)

TUH/11192-13

FIGURE 4. Typical Connection. Note the multiple bypass capacitors on the reference and power supply pins. If VREFis not grounded, it should also be bypassed to analog ground using multiple capacitors (see 5.0 "Power Supply
Considerations"). AGND and DGND should be at the same potential. VIND is shown with an input protection network.
4.0 INHERENT SAMPLE·AND-HOLD
Because the ADC10662 and ADC10664 sample the input
signal once during each conversion, they are capable of
measuring relatively fast input signals without the help of an
external sample-hold. In a non-sampling successive-approximation AID converter, regardless of speed, the input Signal
must be stable to better than ± 1/2 LSB during each conversion cycle or significant errors will result. Consequently,
even for many relatively slow input Signals, the Signals must
be externally sampled and held constant during each conversion if a SAR with no internal sample-and-hold is used.
Because they incorporate a direct sample/hold control input, the ADC10662 and ADC10664 are suitable for use in
DSP-based systems. The 5/H input allows synchronization
of the AID converter to the DSP system's sampling rate and
to other ADC10662s, and ADC10664s.

In systems with multiple power supplies, careful attention to
power supply sequencing may be necessary to avoid overdriving inputs. The AID converter's power supply pins
should be at the proper voltage before digital or analog signals are applied to any of the other pins.
6.0 LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC10662 and ADC10664, it is necessary to use appropriate circuit board layout techniques. The analog ground return path should be low-impedance and free of noise from
other parts of the system. Noise from digital Circuitry can be
especially troublesome, so digital grounds should always be
separate from analog grounds. For best performance, separate ground planes should be provided for the digital and
analog parts of the system.
All bypass capacitors should be located as close to the converter as possible and should connect to the converter and
to ground with short traces. The analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input. Any external component (e.g., a
filter capacitor) connected across the converter's input
should be connected to a very clean ground return point.
Grounding the component at the wrong point will result in
reduced conversion accuracy.

The ADC10662 and ADC10664 can perform accurate conversions of input signals with frequency components from
DC to over 250 kHz.
5.0 POWER SUPPLY CONSIDERATIONS
The ADC10662 and ADC10664 are deSigned to operate
from a + 5V (nominal) power supply. There are two supply
pins, AVec and DVcc. These pins allow separate external
bypass capaCitors for the analog and digital portions of the
circuit. To guarantee accurate conversions, the two supply
pins should be connected to the same voltage source, and
each should be bypassed with a 0.1 /LF ceramic capacitor in
parallel with a 10 /LF tantalum capaCitor. Depending on the
circuit board layout and other system considerations, more
bypassing may be necessary.
The ADC10662 and ADC10664 have separate analog and
digital ground pins for separate bypassing of the analog and
digital supplies. Their ground pins should be connected to
the same potential, and aU grounds should be "clean" and
free of noise.

7.0 DYNAMIC PERFORMANCE
Many applications require the AID converter to digitize AC
Signals, but conventional DC integral and differential nonlinearity specifications don't accurately predict the AID converter's performance with AC input signals. The important
specifications for AC applications reflect the converter's
ability to digitize AC signals without significant spectral errors and without adding noise to the digitized Signal. Dynam-

2·439

io....
Q

C

i....
o

c
c

Applications Information (Continued)
ic characteristics such as signal-to-noise ratio (SNR) and
total harmonic distortion (THO), are quantitative measures
of this capability.

sus frequency. An ideal AID converter with no linearity errors or self-generated noise will have a signal-to-noise ratio
equal to (6.02n + 1.8) dB, where n is the resolution in bits
of the AID converter. A real AID converter. will have some
amount of noise and distortion, and the effective bits can be
found by:

An AID converter's AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal
waveform is applied to the AID converter's input, and the
transform is then performed on the digitized waveform. The
resulting spectral plot might look like the ones shown in the
typical performance curves. The large peak is· the fundamental frequency, and the noise and distortion components
(if any are present) are visible above and below the fundamental frequency. Harmonic distortion components appear
at whole multiples of the input frequency. Their amplitudes
are combinec;l as the square root of the sum of the squares
and compared to the fundamental amplitude to yield the
THO speCification. Guaranteed limits for THO are given in
the table of Electrical Characteristics.

( ff e . ) _ S/(N
n e ctlVe -

+ D) (dB)

-1.8

6.02

where S/(N + D) is the ratio of signal to noise and distortion, which can vary with frequency.
As an example, an ADC10662 with a 4.85 Vp_p, 100 kHz
sine wave input signal will typically have a signal-ta-noiseplus-distortion ratio of 59.2 dB, which is equivalent to 9.53
effective bits. As the input frequency increases, noise and
distortion gradually increase, yielding a plot of effective bits
or S/(N + D) as shown in the typical performance curves.

8.0 SPEED ADJUST

Signal-to-noise ratio is the ratio of the amplitude at the fundamental frequency to the rms value at all other frequencies, excluding any harmonic distortion components. Guaranteed limits are given in the Electrical Characteristics table.
An alternative definition of signal-to-noise ratio includes the
distortion components along with the random noise to yield
a signal-to-noise-plus-distortion ration, or S/(N + D). .

The speed adjust pin is connected to an on-Chip current
source that determines the converter's internal timing. By
connecting a resistor between the speed adjust pin and
ground as shown in Figure 4, the internal programming current is increased, which reduces the conversion time. The
ADC10662 and ADC10664 are speCified and guaranteed for
operation with RSA = ·14.0 kn (Mode 1) or RSA = 8.26k
(Mode 2). Smaller resistors will result in faster conversion
times, but linearity will begin to degrade as RSA becomes
smaller (see curves).

The THO and noise performance of the AID converter. will
change with the frequency of the input Signal, with more
distortion and noise oCcurring at higher signal frequencies.
One way of describing the AID's performance as a function
of Signal frequency is to make a plot of "effective bits" ver-

2-440

~

c
o
.....
N
::c

t!lNational Semiconductor

~c

ADC12H0301 ADC12H0321 ADC 12H0341 ADC12H038,
ADC120301 ADC 120321 ADC120341 ADC12038
Self-Calibrating 12-Bit Plus Sign Serial 1/0
AID Converters with MUX and Sample/Hold

o
.....
N

::c
C)
~

N

General Description

Features

The ADC12030, and ADC12H030 families are 12-bit plus
sign successive approximation A/D converters with serial
I/O and configurable input multiplexers. The ADC12032/
ADC12H032, ADC12034/ADC12H034 and ADC12038/
ADC12H038 have 2, 4 and 8 channel multiplexers, respectively. The differential multiplexer outputs and AID inputs
are available on the MUXOUTt, MUXOUT2, AlDIN1 and
AlDIN2 pins. The ADC12030/ADC12H030 has a two channel multiplexer with the multiplexer outputs and AID inputs
internally connected. The ADC12030 family is tested with a
S MHz clock, while the ADC12H030 family is tested with an
8 MHz clock. On request, these AIDs go through a self
calibration process that adjusts linearity, zero and full-scale
errors to less than ± 1 LSB each.

• Serial I/O (MICROWIRE Compatible)
• 2, 4, or 8 channel differential or single-ended
multiplexer
• Analog input sample/hold function
• Power down mode
• Variable resolution and conversion rate
• Programmable acquisition time
• Variable digital output word length and format
• No zero or full scale adjustment required
I! Fully tested and guaranteed with a 4.096V reference
• OV to SV analog input range with single SV power
supply
• No Missing Codes over temperature

The analog inputs can be configured to operate in various
combinations of single-ended, differential, or pseudo-differential modes. A fully differential unipolar analog input range
(OV to + SV) can be accommodated with a single + SV supply. In the differential modes, valid outputs are obtained
even when the negative inputs are greater than the positive
because of the 12-bit plus sign output data format.
The serial I/O is configured to comply with the NSC
MICROWIRETM. For complementary voltage references see
the LM4040, LM4041 or LM9140.

Key Specifications
12-bit plus sign

• Resolution
II 12-bit plus sign conversion time
- ADC12H030 family
- ADC12030 family
• 12-bit plus sign throughput time
- ADC12H030 family
- ADC12030 family
II Integral linearity error

S.S J.Ls (max)
8.8 J.Ls (max)

......
~

C

o
.....
N

::::t:
C)

~

J!4

~

o.....
~

~

~
o
.....
~

N

~

o.....
N
C)

~.
C

Cs'

PD

CONY

CCLK

;

SCLK

00

IoIUXOUT1

0----'

O.,OUI2 [Jfo----'

A/.,N2o------'
".+0--+
".+0--+

::::t:

B
.co.

o
.....
N

ADC12038 Simplified Block Diagram

A/DIN I

N

~

8.6 J.Ls (max)
14 J.Ls (max)
±1 LSB (max)
SV ± 10%
33 mW (max)
100 J.LW (typ)

• Single supply
• Power dissipation
-Power down

Applications
• Medical instruments
• Process control systems
• Test equipment

~
C
o
.....

66

DeND

AOND

TLlH111354-1

2-441

CD

'(W)

0

C'III
......
C,).

Connection Diagrams

O.

20-Pin Dual-In-Line and
Wide Body SO Packages

16-Pln Dual-In-Line and
Wide Body SO Packages

.....
.,C
(W)

o·
C'III

CHO

Vo+

CHO

C,)

CHI

CCLK

CHI

0

COIot

·N

OOR

.....

....C'
(W)

SCLK

5

EOC

0

N
......

VREF VREF +

CJ
.0
C

8

OGNO

'e;

SCLK
01 .

MUXOUT1,

00

A/DIN 1

cs

MUXOUT2

CONY

A/01~2

VA+

VREF -

00

ADC12032

cs

AOCI2HO~2

CONY
EDC

VREF +

(W)

0
N

TUH/11354-6

Top View

......
C,)

OGNO

Vo+
CCLK

COM

01

AOC12030
AOC12H030

20

COR

V~+

10

0
C

TUH/11354-7

Top View

fIi

,(W)

0

::c
N

.......

.:"

24-Plri Dual-In-Line and
Wide Body SO Packages

28-Pin Dual-In-Llne and
Wide Body SO Packages

C,)

0

'.

.,C....

(W).

0

:c
N

.....
C,)

0

C
.....

Vo'
OOR

CHO

1

28

Vo+

CHI

CHI

2

27

OOR .

CH2

CCLK

CH2

26

CCLK

CH3

SCLK

CH3

25

SCLK

COM

01

CH4

24

01

MUXOUTI

00

CH5

23

DO

A/DIN 1

Cs

CH6

22

Cs

CONY

CH7

EOC

COM

CHO

N

MUXDUT2

0

A/01H2

(W)

:c
.....
C,)

.N

0
'C

....

24

VREF VREF +

PO

OGNO

VA+

0

:c

PO
AGNO

A/DIN 1
MUXOUT2

VREf '"

VRE~-

A!01N2

Top View

TL/H/11354-B

OGNO

vA+

14

'N

.....

, TopVlew

g
c

Ordering Information
Industrial Temperature Range
-40"C ~ TA ~ +8SoC

Package,

ADC12H030CIN, ADC12030CIN

N16E

ADC12H030CIWM, ADC12030CIWM

M16B

ADC12H032CIN,.ADC12032CIN
ADC12H032CIWM, ADC12032CIWM

N20A
'M20B

ADC12H034CIN, ADC12034CIN

N24C

ADC12H034CIWM, ADC12034CIWM

M24B

ADC12H038CIN, ADC12038CIN

N28B

ADC12H038CIWM, ADC12038CIWM

M28B

2-442

CONY
EDC

MUXOUTI

AGHO

'0.

'(W)

AOC12038
ADC 12H038 21

TUH/11354-9

J>

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications_
Positive Supply Voltage
(V+ = VA+ = Vo+)
6.5V
Voltage at Inputs and Outputs
-O.3Vto V+ +0.3V
except CHO-CH7 and COM
Voltage at Analog Inputs
CHO-CH7 and COM

Operating Temperature R\lnge
ADC12030CIN, ADC12030CIWM,
ADC12H030CIN, ADC12H030CIWM,
ADC12032CIN, ADC12032CIWM,
ADC12H032CIN, ADC12H032CIWM, "
ADC12034CIN, ADC12034CIWM,
ADC12H034CIN, ADC12H034CIWM,
ADC12038CIN, ADC12038CIWM,
ADC12H038CIN,
ADC12H038CIWM
-40·C"; TA"; +85·C

GND -5VtoV+ +5V
300mV
±30mA
±120 mA

IVA+ -vo+1
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at
TA = 25·C (Note 4)
ESD Susceptability (Note 5)
Human Body Model
Soldering Information
N Packages (10 seconds)
SO Package (Note"6):
Vapor Phase (60 seconds)
Infrared (15 seconds)
Storage Temperature

C

Operating Ratings (Notes 1 & 2)

(Notes 1 &2)

Supply Voltage (V + = VA + = Vo +)

OVtoVREF+
1VtoVA+

(VREF+ + VREF-)

Q

);
C

o
.....

I\)

::I:
Q

Co)
I\)

C

::E:
Q
Co)

~C

o.....

2

I\)

::E:

AlDIN1, AlDIN2, MUXOUT1
and MUXOUT2 Voltage Range

Q

Co)

SX'

A/D IN Common Mode Voltage Range

-65·C to + 150·C

Co)

o
.....
I\)

VREF(VREF+ -VREF-)
VREF Common Mode Voltage Range

215·C
220·C

Q

);

VREF-

260·C

::E:

,,; 100 mV
OVtoVA+

VREF+

1500V

I\)

+ 4.5V to + 5.5V

IVA + - Vo + I

500mW

o.....

l>

(VIN+ + VIN-)
2

C

o.....

I\)

Q

Converter !Electrical Characteristics

Co)

Q

The following specifications apply for V+ = VA + = Vo + = + 5.0 VOC, VREF+ = + 4.096 VOC, VREF- = 0 VOC, 12-bit +
sign conversion mode, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK = fSK =
5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, Rs = 25!l, source impedance for VREF+ and VREF- ,,;
25!l, fully-differential input with fixed 2.048V common-mode voltage, and 10(tcKl acquisition time unless otherwise specified.
Boldface limits apply for TA = TJ = TMIN to TMAXi all other limits TA = TJ"= 25·C. (Notes 7, 8 and 9)
Symbol

Parameter

Conditions

Typical
(Note 10)

Limits"
(Note 11)

Units
(Limits)

12+ sign

Bits (min)

STATIC CONVERTER CHARACTERISTICS

o
.....

I\)

Q
Co)
I\)

);
C
o
.....
I\)

Resolution with No Missing Codes
+ILE

Positive Integral Linearity Error

After Auto-Cal (Notes 12, 18)

±1/2

±1

LSB(max)

-ILE

Negative Integral Linearity Error

After Auto-Cal (Notes 12, 18)

±1/2

±1

LSB (max)

DNL

i>
c

Differential NOI'!-Linearity

After Auto-Cal

:1:1

LSB (max)

Positive Full-Scale Error

After Auto,Cal (Notes 12, 18)

±1/2

±3.0

LSB (max)

Negative Full-Scale Error

After Auto-Cal (Notes 12, 18)

±1/2

±3.0

" LSB(max)

Offset Error

After Auto-Cal (Notes 5, 18)
VIN(+) = VIN (-) = 2.048V

±1/2

±2

LSB (max)

DC Common Mode Error

After Auto-Cal (Note 15)

±2

±3.5

LSB (max)

Total Unadjusted Error

After Auto-Cal
(Notes 12, 13 and 14)

±1

Resolution with No Missing Codes

8-bit + sign mode

Positive Integral Linearity Error

8-bit + sign mode (Note 12)

Q

~fI

c
o.....

I\)

Q

TUE

+INL

LSB
8 + sign

Bits (min)

±1/2

LSB (max)

-INL

Negative Integral Linearity Error

8-bit + sign mode (Note 12)

±1/2

LSB (max)

DNL

Differential Non-Linearity

8-bit + sign mode

±3/4

LSB(max)

Positive Full-Scale Error

8-bit + sign mode (Note 12)

±1/2

LSB(max)

2-443

Co)

CD

CD

a,...
('II

o

c

cC
.....
'III'
CO)

o

('II
,...

o
c
cC
.....
('II
CO)

Converter Electrical Characteristics (Continued)
The following specifications apply for V+ = VA + = Vo+ = +S.O Voc, VREF+ = +4.096 Voc, VREF- = 0 Voc, 12-bit +
sign conversion mode, fCK = fSK = B MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H03B, fCt< ,= fSK =
S MHz for the ADC12030, ADC12032, ADC12034 and ADC1203B, Rs =2Sn, source impedance for VREF+ and VREF- :5:
2Sn, fully-differential input with fixed 2.04BV common-mode voltage, and 10(tcKl acquisition time unless otherwise specified.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 2SoC. (Notes 7, Band 9)
Symbol

o
c

CO)

o

TUE

c

B-bit + sign mode (Note 12)

±1/2

LSB (max)

8-bit + sign mode,
aller Auto-Zero (Note 13)
VIN( +) = VIN( -) = + 2.04BV

±1/2

LSB (max)

B-bit' + sign mode
aller Auto-Zero
(Notes 12, 13 and 14)

±3/4

LSB(max)

Total Unadjusted Error

Multiplexer Channel to Channel
Matching

cC

ai
CO)

o

Power Supply Sensitil(ity

:::E:

....
('II

g
~

o

:::E:

....

('II

o
c

~

CO)

o

:::E:
('II

LSB

V+ = +SV ±10%
VREF = +4.096V
±O.S
±O.S
±O.S
±O.S
±O.S

Output Data from
"12-Bit Conversion of Offset"
(see Table V)

(Note 20)

Output Data from
"12-Bit Conversion of Fuil-Scale"
(see Table V)

(Note 20)

±1
±1.5
±1.5

LSB(max)
LSB(max)
LSB(max)
LSB
LSB

+10
-10

LSB(max)
' LSB(min)

4095
4093

LSB (max)
LSB(min)

UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D)

Signal-to-Noise Plus
Distortion Ratio

fiN = 1 kHz, VIN = S Vpp, VREF+ = 5.0V
fiN = 20 kHz, VIN = 5Vpp, VREF+ = 5.0V
fiN = 40kHz, VIN = 5 Vpp, VREF+ = 5.0V

-3 dB Full Power Bandwidth

VIN = S Vpp, where S/(N+ D) drops 3 dB

:::E:
('II

cC

±O.OS

Offset Error
+ Full-Scale Error
- Full-Scale Error
+ Integral Linearity Error
- Integral Linearity Error

,~

....
g

Units
(Limits)

Negative Full-Scale Error

....
o

~
o

Limits
(Note 11)

Offset Error

('II

....
g

Typical
(Note 10)

STATIC CONVERTER CHARACTERISTICS (Continued)

~
,...

~
o

Conditions

Parameter

69.4
68.3
65.7

dB
dB
dB

31

kHz

77.0
73.9
67.0

dB
dB
dB

40

kHz

DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D)

Signal-to-Noise Plus
Distortion Ratio

fiN = 1 kHz, VIN = ±5V, VRE~+ = 5.0V
fiN = 20kHz, VIN = ±5V, VREF+ = 5.0V
fiN = 40kHz, VIN = ±5V, VREF+ = 5.0V

-3 dB Full Power Bandwidth

VIN = ±5V, where S/(N+ D) drops 3 dB

2-444

l>

C

Electrical Characteristics
The following specifications apply for V+ = VA + = Vo+ = +5.0 VOC, VREF+ = + 4.096 VOC, VREF- = 0 VOC, 12·bit +
sign conversion mode, fCK ';' fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK = fSK =
5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, Rs = 250, .source impedance for VREF+ and VREF- ~
250, fully·differential input with fixed 2.048V common·mode v(lltage, and 10(tCK) acquisition time unless otherwise specified.
Boldface limits apply for T A = T J = T MIN to T MAXi all other limits T A = T J = 25'C. (Notes 7, 8 and 9)
Symbol

Parameter

Typical
(Note 10)

Conditions

limits
(Note 11)

Units
(Limits)

CREF

Reference Input Capacitance

85

pF

AlDINl and AlDIN2 Analog Input
Capacitance

75

pF

w

~C
o
....
N

:::z::

;;
o....
N

VIN
VIN

=
=

:::z::

+ 5.0V or
OV

±0.1

±1.0

/LA (max)

GND - 0.05
VA+ + 0.05

V (min)
V (max)

CCH

CHO-CH7 and COM Input Capacitance

10

pF

CMUXOUT

MUX Output Capacitance

20

pF

RON

Q

C

CHO-CH7 and COM Input Voltage

On Channel Leakage (Note 16)
CHO-CH7 and COM Pins

:::z::

Q

CA/O

Off Channel Leakage (Note 16)
CHO-CH7 and COM Pins

N

w

REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHAR~CTERISTICS

AlDINl and AlDIN2 Analog Input
Leakage Current

o....

On Channel
Off Channel

=
=
=
=

OV and
SV

0.01

0.3

/LA (max)

On Channel
Off Channel

=
=

SV and
OV

0.01

0.3

/LA (max)

On Channel
Off Channel

=
=

OV and
SV

-0.01

-0.3

/LA (min)

0.01

0.3

/LA (max)

1150

o (max)

On Channel
Off Channel

=
=

SV and
OV

-0.01

-0.3

/LA (min)

MUX On Resistance

VIN = 2.SVand
VMUXOUT = 2.4V

8S0

RON Matching Channel to Channel

VIN = 2.5Vand
VMUXOUT = 2.4V

S

%

Channel to Channel Crosstalk

VIN

-72

dB

90

kHz

5 Vpp, fiN

MUX Bandwidth

=

40 kHz

~
o....
N
C

:::z::
Q

~

l>
C

....

B
~
c
....

C)

~

VMUXOUT
VMUXOUT

=

w

C)

MUXOUT1 and MUXOUT2
Leakage Current

5.0V or
OV

Q

~
C

o
....
~

~fI
c
o
....

~
w
co

2·445

DC and Logic Electrical Characteristics
The following specifications apply for V+ = VA + = Vo+ = +5.0 Voc, VREF+ = +4.096 Voc, VREF- = 0 Voc, 12-bit +
sign conversion mode, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK = fSK =
5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, Rs = 250, source impedance for VREF+ and VREF- ,;;
250, fully-differential input with fixed 2.048V common-mode voltage, and 10(tcK> acquisition time unless otherwise specified.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. (Notes 7,8 and 9)
Symbol

Conditions

Parameter

Typical
(Note 10)

Limits
(Note 11)

Units
(Limits)

2.0

V (min)

CCLK, CS, CONY, 01, PO AND SCLK INPUT CHARACTERISTICS
VIN(l)

logical "1" Input Voltage

V+ = 5.5V

VIN(O)

l,ogical "0" Input Voltage

V+ = 4.5V

IIN(l)

logical "1" Input Current

VIN = 5.0V

IIN(O)

logical "0" Input Current

VIN = OV

0.8

V (max)

0.005

1.0

p.A(max)

-0.005

-1.0

p.A(min)

2.4
4.25

V (min)
V (min)

DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
logical "1" Output Voltage

V+ = 4.5V, lOUT = -360 iJ.A
V+ = 4.5V, lOUT = - 10 iJ.A

VOUT(O)

logical "0" Output Voltage

V+ = 4.5V,IOUT = 1.6 mA

lOUT

TRI-STATE Output Current

VOUT = OV
VOUT = 5V

-0.1
0.1

+Isc

Output Short Circuit Source Current

VOUT ='OV

-Isc

Output Short Circuit Sink Current

VOUT = Vo+

VOUT(l)

0.4

V (rilax)

-3.0
3.0

iJ.A(max)
iJ.A(max)

14

6.5

mA(min)

16

8.0

mA(min)

mA(max)

CS =

POWER SUPPLY CHARACTERISTICS
10+

IA+

IREF

Digital Supply Current
ADC12030, ADC12032, ADC12034
and ADC12038

Awake
HIGH, Powered Down, CClK on
CS = HIGH, Powered Down, CClK off

1.6
600
20

2.5

Digital Supply Current
ADC12H030, ADC12H032, ADC12H034
and ADC12H038

Awake
HIGH, Powered Down, CClK on
HIGH, Powered Down, CClK off

2.3
0.9
20

3.2

CS =
CS =

mA
mA
p.A

Awake
HIGH, Powered Down, CClK on
HIGH, Powered Down, CClK off

2.7
10
0.1

4.0

mA(max)

CS =
CS =

Awake
HIGH, Powered Down

70
0.1

Positive Analog Supply Current

Reference Input Current

CS =

2-446

iJ.A
iJ.A

iJ.A
iJ.A
iJ.A
iJ.A

c»
.....
N

AC Electrical Characteristics

(')

The following specifications apply for V+ = VA + = Vo+ = +5.0 VOC, VREF+ = +4.096 VOC, VREF- = 0 VOC, 12-bit +
sign conversion mode, tr = tf = 3 ns, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038,
fCK = fSK = 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, Rs = 25n, source impedance for VREF+ and
VREF- s; 25n, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise
specified. Boldface limits apply for T A = T J = T MIN to T MAX; all other limits T A = T J = 25'C. (Note 17)

B

Symbol

Parameter

Typical
(Note 10)

Conditions

ADC12H030/2/4/8

ADC12030/2/4/8

Limits
(Note 11)

Limits
(Note 11)

Units
(Umits)

fCK

10
1

8

5

MHz (max)
MHz (min)

fSK

Serial Data Clock
SCLK Frequency

10
0

8

5

MHz (max)
Hz (min)

Conversion Clock
Duty Cycle

40
60

40
60

% (min)
% (max)

Serial Data Clock
Duty Cycle

40
60

40
60

% (min)
% (max)

44(teK)

44(tCK)

(max)

5.5

8.8

/Ls (max)

21(teK)

21(tCK)

(max)

2.625

4.2

/Ls (max)

6(tCK)
7(tCK)

6(teK)
7(teK)

(min)
(max)

0.75
0.875

1.2
1.4

/Ls (min)
/Ls(max)

10(teK)
11(teK)

10(tCK)
11(tCK)

(min)
(max)

1.25
1.375

2.0
2.2

/Ls (min)
/Ls (max)

18(teK)
19(teK)

18(teK)
19(tCK)

(min)
(max)

2.25
2.375

3.6
3.8

/Ls (min)
/Ls (max)

34(tCl()
35(tCK)

34(teK)
35(tCK)

(min)
(max)

4.25
4.375

6.8
7.0

/Ls (min)
/Ls (max)

4944(teK)

4944(teK)

(max)

618.0

988.8

/Ls (max)

76(tCK)

76(tCK)

(max)·

9.5

15.2

/Ls (max)

2(tCK)
3(teK)

2(tCK)
3(teK)

(min)
(max)

0.250
0.375

0.40
0.60

/Ls (min)
/Ls (max)

9(laK)

9(laK)

(max)

1.125

1.8

/Ls (max)

8(laK)

8(laK)

(max)

1.0

1.8

/Ls (max)

Conversion Time

12-Bit + Sign or 12-Bit

44(tCK)

8-Bit + Sign or 8-Bit

tA

Acquisition Time
(Note 19)

21 (teK)

6 Cycles Programmed

6(teKl

10 Cycles Programmed

18 Cycles Programmed

34 Cycles Programmed

tCKAL

tAZ

tSYNC

tooJ:f

~

Self-Calibration Time

Auto-Zero Time

10(tCK)

18(teK)

34(teKl

4944(teKl

76(teKl

Self-Calibration or
Auto-Zero Synchronization
Time from DOR

2(tcKl

DOR High Time
when CS is Low
Continuously for Read
Data and Software
Power Up/Down

9(tsK)

COIiIV Valid Data Time

8(tsKl

2-447

~
c

(')

Conversion Clock
(CCLK) Frequency

tc

::t:

.....
N

::t:

oCo)

N

i>
c
(')

.....
N

::t:

oCo)

~

»
c

(')
.....
N

::t:

oCo)
!JD

»
c

(')
.....
N

oCo)

~

»
c

(')
.....
N

o
~

i>
c

(')
.....
N

o

~.
C

(')

.....

N

o

Co)
CI)

CD

'CO)

o

AC Electrical Characteristics (Continued)

cc

The following specifications apply for V+ = VA + = Vo+ = +5.0 VOC, VREF+ = +4.096 Voc, VREF- = 0 Voc, 12-bit +
sign conversion mode, tr = t, = 3 ns, fCK '= fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038,
fCK = fSK = 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, Rs = 250, source impedance for VREF+ and
VREF- ,;; 250, fully-differential input with fixed 2.048V common-mode voltage, and 10(tcKl acquisition time unless otherwise
specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. (Note 17)

....
g
('II

~

....~
g

....cc
~

....
g

Symbol

Parameter

Conditions

Typical
(Note 10)

Limits
(Note 11)

Units
(Limits)

tHPU

Hardware Power-Up Time, Time from
PO Falling Edge to EOC Rising Edge

140

250

,p-s (max)

tspu

Software Power-Up Time, Time from
Serial Data Clock Falling Edge to
EOC Rising Edge

140

250

p-s (max)

20

50

ns(max)

30

ns(min)

0

5

ns(min)

40

100

ns(max)

('II

....cc
o

a....

tACC

Access Time Delay from

tSET-UP

CS Falling Edge to DO Data Valid
Set-Up Time of CS Falling Edge to

('II

g

Serial Data Clock Rising Edge

cc

t:4
CO)
o
:::r::
('II

tOELAY

Delay from SCLK Falling
Edge to CS Falling Edge

....

tlH, toH

Delay from CS Rising Edge to
DO TRI-STATE®

~

tHOI

5

15

ns(min)

a

01 Hold Time from Serial Data
Clock Rising Edge

:::r::
('II

IsOI

....
o

01 Set-Up Time from Serial Data
Clock Rising Edge

5

10

ns(min)

c

tHOO

DO Hold Time from Serial Data
Clock Falling Edge

25

50
5

ns(max)
ns(min)

('II
CO)

tO~~

Delay from Serial Data Clock
Falling Edge to DO Data Valid

35

50

ns(max)

....

tRoD

DO Rise Time, TRI-STATE to High
DO Rise Time, Low to High

RL = 3k, CL = 100 pF

10
10

30
30

ns(max)
ns(max)

DO Fall Time, TRI-STATE to Low
DO Fall Time, High to Low

RL = 3k, CL = 100 pF

12
12

30
30

ns(max)
ns(max)

o
c

....cc
o
:::r::
('II

o
....~
o
CO)
o

~
....
o
c
cc

"

tFDO
"

RL = 3k,CL = 100pF

RL = 3k, CL = 100 pF

te~

Delay from CS Falling Edge
to DOR Falling Edge

25

45

n;;(max)

tso

Delay from Serial Data Clock Falling
Edge to DOR Rising Edge

25

45

ns(max)

CIN

CapaCitance of Logic Inputs

10

pF

COUT

Capacitance of Logic Outputs

20

pF

2-448

l>
C

Electrical Characteristics (Continued)
Nole I: Absolute Maximum Ratings indicate limits beyond which damage 10 the device may occur. Operaling Ratings Indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.
Nole 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIW at any pin exceeds the power supplies (VIN < GND or VIN > VA + or Vo +), the current at that pin should be limited to 30 rnA.
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input Current 0130 rnA to lour.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, BJA and the ambient temperature, TA- The maximum
allowable power dissipation at any temperature is Po = (TJmax - TpJlBJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJmax = 150'C. The typical thermal resistance (0JpJ of these parts when board mounted follow:

Thermal
Resistance

Part Number

BJA

53'C/W

ADC12H030CIN, ADC12030CIN
ADC12H030CIWM, ADC12030CIWM

70'C/W

ADC12H032CIN, ADC12032CIN

46'C/W

ADC12H032CIWM, ADC12032CIWM

64'C/W

ADC12H034CIN, ADC12034CIN

42'C/W

ADC12H034CIWM, ADC12034CIWM

57'C/W

ADC12H038CIN, ADC12038CIN

40'C/W

ADC12H038CIWM, ADC12038CIWM

50'C/W

Nole 5: The human body model Is a 100 pF capaCitor discharged through a 1.5 kU resistor into each pin.
Note 8: See AN450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section tiUed "Surface Mount" found in any post 1986 National
Semiconductor Unear Data Book for other methods of soldering surface mount devices.
Note 7: Two on-chlp diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA + or 5V below GND
will not damage this device. However, errors in the AID conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage
magnitude of selected or unselectad analog input go above VA + or below GND by more than 50 mY. As an example, If VA + is 4.5 Voc, full·scale input voltage
must be :S:4.55 Voc to ensure accurate conversions.

.

r--- -----

ANALOG

INPUTS

1

..,
.. ~

~

..

TO INTERNAL
CIRCUITRY

. _-- -----

I.

GND

TL/H/11354-2
Note 8: To guarantee accuracy, it Is required that the VA + and Vo + be connected together to the same power supply with separate bypass capacitors at each V+
pin.
Note 9: With the lesl condition for VAEF (VREF+ - VREF-) given as +4.096V, the 12·bit LSB is 1.0 mV and the 8·blt LSB is 16.0 mY.
No.. 10: Typicals are at TJ = TA = 25'C and represent most likely parametriC norm.
Nole 11: Tested 'limits a;e g~ar&~i';ed to National's AOQL (Average Outgoing Quality Level).
Note 12: Po81tive Integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full·
scale and zero. For negative Integral linearity error, the straight line passes through negative full·scale and zero (see Figures Ib and Ie).
Note 13: Zero error is a measure of the deviation from the mid·scale voltage (a code of zero), expressed in LSB. It is the worst·case value of the code transitions
between I to 0 and 0 to + 1 (see Figure 2).
Nole 14: Total unadjustad error Includes offset, full·scale, linearity and multiplexer errors.
Note 1&: The DC common·mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 11: Channel leakage current Is measured after the channel selection.
Note 17: Timing epeclIIcations are tested al Ihe TIL logic levels, VIL = O.4V for a falling edge and VIH = 2.4V for a rising edge. TRI·STATE output voltage is forced
to 1.4V.
Note 18: The ADC12030 family's self·calibration technique ensures linearity and offset errors as specilied, but noise inherent in the self-calibration process will
result in a maximum repeatability uncertainty of 0.2 LSB.
Note 11: If SCLK and CCLK are driven from the same clock source, then tA is 6, 10, 18 or 34 clock periods minimum and maximum.
Note III: Tile "12·a. CanverIIon of 0ffMt"1/KI"12·a. Convll1lon of Full-Scale" modes are intended to test the functionality of the device. Therefore, the output
data from theM model.,. not III IndICatIon of the accuracy of • conversion result.

2-449

I\)

::E:

oCo)
o
......

l>
C

(")
-"
I\)

::E:

o

Co)
I\)

......

l>
C

(")
-"
I\)

::E:

oCo)

~
l>
C

(")
-"
I\)

::E:

o
J»

Co)

l>
C

(")

.....

I\)

oCo)

~C

(")

.....

I\)

VA+

1
1

(')
-"

o
~
......
~

g
-"

I\)

o

~fJI

c(")
-"

I\)

oCo)

CO

Electrical Characteristics (COntinued)
. .,:
0,1111,1111, 111l(+4095)
0,1111,1111,111 0(+4094)
"

'~E
FULL-SCALE

",

TRANSITION

,,///'
0,0000,0000,0010(+2)
0,0000,0000,0001 (+1)
0,0000,0000,0000(0)

f--------

"

VIN +

> VIN _

-l

_""T+E===2Z~ER~0~T~R~A~NS~IT~10~N!...._ _ _ _ _ _ _

,
VIN _

> VIN +

' "

...co

/,/,/'/

~~~
~

0-

::>

o

~IVE

FULL-SCALE
TRANSITION

z
...

ucn~

t-o w
0

u

VREF = VREF + - VREF V,N = VIN + - VIN _
GND:S VIN + :S VA+
GND :S VIN _ :S VA +

1,0000,0000,0001 (-4095)
1,0000,0000,0000 (-4096)
ANALOG INPUT VOLTAGE (VIN )

FIGURE 18. Transfer Characteristic

+12LSB
POSITIVE
FULL-SCALE
ERROR

NEGATIVE
FULL-SCALE
ERROR

OUTPUT CODE
(f~.m -4096

t. +4095)
T1:1H/113ri4":11

FIGURE 1b. Simplified Error Curve vs Output Code without Auto-Callbratlon or Auto-Ze~ Cycles
,,::

2-450

Electrical Characteristics (Continued)
+3LSB
+2LSB
OFFSET

+1 LSB

1ERROR

--j~~-----------------------

T

'NEGATIVE
""" INTEGRAL
LINEARITY
ERROR

POSITIVE
FULL-SCALE
ERROR

j

t

-4096
NEGATIVE
FULL-SCALE
ERROR

POSITIVE
INTEGRAL
LINEARITY "ERROR
""

-1 LSB
-2 LSB
-3 LSB
OUTPUT CODE
(from -4096 \0 +4095)
TL/H/11354-12

FIGURE lc. SImplified Error Curve vs Output Code after Auto-Callbratlon Cycle

+2

+1

I!l

8

0

!55--------------~----T~~~-------------I- OFFSET VOLTAGE
'"
-1

-2
ANALOG INPUT VOLTAGE (VIN )

FIGURE 2. Offset or Zero Error Voltage

2-451

TL/H/11354-13

cor-~--------------~--------------------------------------------------------------,

i!....

~

Typical Performance Characteristics

The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. The performance for 8-bit
sign mode is equal to or better than shown. (Note 9)

~
CI)

....~

~
N

CI)

Q

N
....

~~

Linearity Error Change

....
~

~...

..'"

0.15

V..+=Vo+=SV
0.10 VREf' = 4.096V VREf =

....
N

"

~

('0' ; "'0-) J2.~4S~ ~ ....

0.05

TA = 25°C

u

~

~
z

....
~

I

1/

-0.05

Linearity Error Change
va Temperature

...~
'"u

/

0.00

!

-0.10

:;

,,,

0.15
0.10

.r::

!.

o

_I v: = VD' ':. 5V
VREf = OV
, I I I fe =5MHZ

~
~

~

I
~

:N

VREF' = 4.096V VREF- = OV

0.15

fe

5MHz

III

' \ ' • 25°C

0.10

1\

0.05

z

....

=2.048Y- ----

/

"-

.....V

'"

:;

'-

-0.05

;
"

4.75

5.00

5.25

5.50

'"u
i!5

-0.10

V:i VD':5V
VREf = OV

~

0.2

"

I

~
~

~

+2

'-

0.1

0

o

....
~

I
I

0.4

VA,+=YD+=5V rJ~,.l
0.2 VREf' =4.096V VREF- = 0

TA = 2 °C

....

~

-2

~

-3~--HL--~--~~~-1

~

..

-0.2

JED fUlL-SCAL

~

-OJ

:!l

-0.6

1\

~IT

~II

~

~FUtJ.uI- ~II

III

('O',;VIN-·tO,4S~
-0.8
o 1 2 3 4 5 6

I

~~

;..t

7

B 9 10

v: tV:
. (J!!L.J!!:

-1.0

III 2.048V
-1.5
2
-60 -.10 -20 0 20 40 60 SO 100 120 140

CONVERSION CLOCK FREQUENCY (MHz)

TEMPERATURE (DC)

Zero Error Change
va Clock Frequency

....
~
III
:ll

;
-0.4 ~+-'++=+:....t--I--+--I

I
I
~

N

i

::l

REFERENCE VOLTAGE (V)

0.10

Ll

71'\

-

3

Ie = 5M~

5.50

1

VIN.

t

VIN_)

-

VREF +

2

V

I

I

-0.10

I[

-0.15
-60 -40 -20 0 20 40 60 SO 100 120 140
TEMPERATURE (DC)

-3

1 2

\:1

1\

3 4 5 6 7 8 9 10

Zero Error Change
va Supply Voltage
0.12

l
=

~A = ~50C

o

II

CONVERSION CLOCK FREQUENCY (MHz)

VA = VD = V
Ie = 5MHz
VREf- = ov

.... 1- ....

-0.05

5.25

1\,

,'\

-0.4

Zero Error Change
va Reference Voltage

VA = VD = 5V
VREi=OV

C'"· ;YIN-) = 2.048V

~

TA = 25 0C

-0.2

SUPPLY VOLTAGE (V)

_vRrl =4.096V

0,05

5.00

i-

("'N+; "'N-) = 2.048V
0.2

-0.6

0.15

.1.J

VA. II YD+ • 5Y
VREF+·4.096V VIII:;· OVr-

'"

Zero Error Change
va Temperature
~

0.4

u

4.75

....

4

I

r-r--, /1\/ I \ ,

'C·SMHz

VREF'

3

~

2~~~~~

-1

"

2

0.6

I

c
.:(

1

....

I

0+ = V

~-;~iDl

r.......

o

REFERENCE VOLTAGE (V)

+1 VREF-"':'=.!!O!"V-+--:--+__-+__-l
(VIN• t YIN-,\ = VIEr t

0II:II:

N

v,: =

2

TA = 25°«
fe;; SMHz

:;

Full-Scale Error Change
va Reference Voltage

....

.2

Full-Scale Error Change
.va Clock Frequency

SUPPLY VOLTAGE (v)

:N

(IH+I+VIN) = VIEF

\
\

0.3

!

~

TEMPERATURE (DC)

~

-0.05
4.50

0..4

-0.15
-60 -40 -200 20 40 &0 BO 100 120 140

1 2 3 4 5 6 7 S 9 W

tlN+ ;V1N _)

0.20

!

0.00

Linearity Error Change
va Supply Voltage
0.25

~

0.5

~(IN' ; VIN_) = 2.D4SV

0.05

0.6

....

I.

CONVERSION CLOCK FREQUENCY (MHz)

....

Linearity Error Change
va Reference Voltage

~VR[r+ = 4.096V

:;

-0.15

....~

~
fIlf
a::c

va Clock Frequency
1-1 ov-::::;;oo
J

+

....
~
~

...z

0.08

......

,

VlI[f -4.096V VItU-·OV

(INt ; VIN _)

0.04

~

2.048V

"-i"

5

i

III

le=5MHz
T • SoC

-0.04

~ t-

-O.OB
-0.12

o

2
VRE

?

3

4

REFERENCE VOLTAGE (V)

4.50

4.75

5.00

5.25

5.50

SUPPLY VOLTAGE (V)

TUH/'1354-14

2-452

»

Typical Performance Characteristics

(Continued)
The following curves apply for 12·bit + sign mode after auto·calibration unless otherwise specified. The performance for B·bit
sign mode is equal to or better than shown.

+

g
....
N

:z::

Q

Co)

Analog Supply Current
vs Temperature
~.S

"<
.5

a:::i
i:l

~

iil
co

9

;!

...

V~:=VD+

3.5

Y~.=t5Y

3.0

2.~

I

fc =5t.1Hz

~.O

Digital Supply Current
vs Clock Frequency

I

Y.

1::::;;"-

u:.. ~::::~

·60·~·20

0 20

~o

TA =25 0C
......

~

0.0
B01001201~0

TEMPERATURE (oc)

I

2

3

~

5

6

B 9 W

7

Co)

;;

O.B

HY-+-+-+-+-++-+-l

N

0.6~...,...l~..,...J....,...J...,..I-,..J-,,.J....,..L.,-J

Q

·60 -40 ·20 0 20

~o

-r--r-

60 BO 100 120 I~O

TEMPERATURE (oe)

CONYERSION CLOCK FREQUENCY (MHz)

TL/H111354-15

Typical Dynamic Performance Characteristics
The following curves apply for 12·bit

:z::

Q

~::t=P::!=i=I~~
VD" =4.SV
I-=+:::::t=*::j...j...bd-l--l--l
r-

V

Ie

o
....
N

1.0

1.2

o

VD+"S.5V

VD+=SV

/

O.~

Hri-+-"=-+-J.'i..=,.::5.::;"Hr:'-+-l
fC

uW:t:t:±::!=1=I:::t:::j:..j

/~

O.B

~
60

1.6

~

1.2

i

I

1.5

~

1.6

i:l

Y.~='i5Y

2.0

2.0

I.B .,;-;-r-,-,--.::Y":C"=::"YD••..,..,

v/ _VD't=5V

~

--::8: ~:::tr~

2.5

"<
.5

i5

Digital Supply Current
vs Temperature

Ie

o
....

:z::

Co)

oIioo
.....

»

g
....
N
:z::

+ sign mode after auto·calibration unless otherwise specified.

B
»
Ie

!»
o

Bipolar Spectral Response
with 1 kHz Sine Wave Input

----

-20

....3 -40
~

.
;

RS;::: GODll
YIN = 5V
TA =250C ,) ,~
vA+=VO+=VREt=SV
fc =5MHz
Sampling Rate=;~

-60

S/N = 77.43 dB
S/(N+D) = 76.01 dB

~

~

o
-20

....

.3 -40

~

.

-60

Bipolar Spectral Response
with 10 kHz Sine Wave Input

Rs = 60011

-

v,. =5V

r-

TA =250C ,)
VA+;::: Vo +;::: VREF ;::: SV
fC;::: 5 MHz
Sampling Rate =73.5 kHz

- r- I-

S/N = 77 .B9 d~.;:r.;:::
S/(N.D) = 7U3 dB

~ -80

-80

in

Ii

-100

in

I

o

....
3 ... 40
g
~

I
C.L,
VA+=VO+=VREt=

Q

V,.=5V
TA = 25 O

Co)

Q
.....

v
fc =5t.1Hz
Samping Rat&=73.5KHz

»

g
....

S/(N+D) = 72.29 dB

-80

,I

in

-100

I

.1

II,

,~.

-120

-120

o

5

10

20

IS

25

30

35

o

-120
5

10

15

20

25

30

35

o

5

FREQUENCY (kHz)

FREQUENCY (kHz)

10

15

o
....
N

RS = 60011

-60 S/N = 77.54dB

;;:.

i3

I

.I

-100

-20

Bipolar Spectral Response
with 20 kHz Sine Wave Input

20

25, 30

35

FREQUENCY (kHz>'

8
~

»
Ie
o
....
~

o

Bipolar Spectral Response
with 30 kHz Sine Wave Input

I

-20

~~:;~:+C;::: vRJ+ =~y

.... -40

fC=St.tHz
Sampling Rate=73.SkHz

~

S/N = 77 .24 dB
S/(N+D) = 70.05 dB

I

-100
-120

o Rs = 60011

Rs = 60011

-20 V'N =5V

o

5

10

15

20

25

FREQUENCY (kHz)

30

35

-20

-80

,~

~
;;:.

i3

I

Iii
-100 II
o

10

I

-80

15

20

25

FREQUENCY (kHz)

30

I

in

-100

35

o

5

I

I
10

15

20

N

Co)

CD

.-

II
25

I"""

30

35

FREQUENCY (kHz)

TL/H111354-16

2·453

~.

g
....
Q

Sampling Rate=73.5kHz
-60 S/N = 70.55 dB
S/(N+D) = 66.~~dt

-120
5

Y,.=5V

TA

~

f C =5t.fHz

~

-120

o Rs = 60011

= 25°C ,.L< J,
VA,+ =VD+ =VREF+ = 5V
.... -40 'c=5MHz

~~+==2;oOp= VRE~+ = ~v

§
in

IWI

v,. =5V I

Sampnng Rale = 73.5 kHz
-60 S/N=73.62dB
S/(N+D) = 6B.03dB

;;:.

III I

Bipolar Spectral Response
with 50 kHz Sine Wave Input

Bipolar Spectral J:lesponse
with 40 kHz Sine Wave Input

CD

C")

~
..-

g

Typical Dynamic Performance Characteristics (Continued)

cr:
.......
..,.

Bipolar Spurious Free
Dynamic Range

C")

CI

95

..-

90

'"

o
c
cr:

~
C")
CI

'"..-

'iii
3

85

~
~

~;;;

C

........

cr:
.....
CI

80

lis = 60011
75 TA = 25°C
VA+=VD+=v, +=5V
5MHz
70
Sam!ling ,tillit'5 kjZ
VIN - 5Vp_p
65
lr1'
10/

'c·

C")

'"

..-


e

Timing Diagrams (Continued)

o
....

N

::J:

ADC12038 Read Data without Starting a Conversion Using CS

CI

Co)

CCLK

CI
.....

SCLK

e
o
....

:I>
N

::J:

CI
Co)

N
.....

:I>

e
o....
N

::J:

CI

01

Co)

.....
~

DO

~~~-------------------------

I'-__A-__~__-n__~~~~__~~~ OBO

:I>

e

o
....
N

OOR ~~________________________~I~

::J:

CI
Co)

EOC

--------------------~I~I----------------~-----TL/H/11354-24

!I'
:I>

e
o....
~
Co)

ADC12038 Read Data without Starting a Conversion with CS Continuously Low

1..rl.rLrlrlIl..JlSl

CCLK

~n

SCLK

'-' ~~S--------------

cs

~

Co)

N

i>
e
o
....
N
B

CONY

~

e

01

DO

~e
....o

o
....

DBD

DBl

DB2

N
CI

DBD

Co)

co

DDR

___________________~I~-----L--~--

EOC

------------------------------~§ISI----------~I~I-----------------TUH/11354-25

2·457

co

C')

~

r---~----------------------------------------------------------~~--------------~

Timing Diagrams (Continued)
ADC12038 Conversion Using CS with 8-Blt Digital Output Format

CCLK

SCLK

01

DO

DaR ~~_____________________~

r

5\-i

roc

~!r-----""'.

Tl/H/11354-26

ADC12038 Conversion Using CS with 16-Blt Digital Output Format

CCLK

SCLK

DO

5S-;

roc

r

l-.....§l-l- - -....

TL/H/11354-51

2-458

Timing Diagrams (Continued)
ADC12038 Conversion with ~ Continuously Low and 8·Blt Digital Output Format

CCLK

SCLK

01

EOC

DBO

.DB7

DO

----------------~~. Sl--;

~~S----r

TUHfl1354-28

ADC12038 Conversion with ~ Continuously Low and 16-Blt Digital Output Format

§~

. __....r

~~~

EOC

TLfHf11354-29

2·459

Timing Diagrams (Continued)
ADC12038 Software Power Up/Down Using CS with 16.81t Digital Output Format

CCLK

SCLK

01

~'+-+-+-+-f

DO

p;::~
EOC

XXXXXXXXXXXXXXX)-.IoJ\,.,...-t-4M-+

circuitry

2500

Co)

..110-

To ADC pin

~

2500

C

IN914

....

(")

'"X

TL/H/11354-34

Q

Co)

FIGURE 3. Protecting the MUXOUT1, MUXOUT2, AlDIN1 and AlDIN2 Analog Pins

SR
~

C

....

(")

'"

V+

Q

Co)

Analog
Input
Voltage

Assigned

>-----1 (+) INPUT

~

+5V

~

C

o....

vo +

~

I
Analog
Input
Voltage

I

I

ADC

>-----1

Assigned
(-) INPUT

VREF +

Co)

.....
'"
~

------o

I-.....":':'-f--::-....

I

I

C

+4.096V

....

(")

'"

Q

I

~fII
c
....

VREF -

(")

'"

Q

Co)

co
DGND

AGND

Analog
Input
Voltage >-----------~"""'"-------'
Ground
Reference
TL/H/11354-35

'Tantalum
"Monolithic Ceramic or better

FIGURE 4_ Recommended Power Supply Bypassing and Grounding

2-463

Tables
TABLE I. Data Out Formats
DO Formats

DBO DB1 DB2 DB3 DB4 DB5 DB6 DB7 DBB DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16

17

X

Bits

MSB 13
Sign MSB
First Bits

9

10

9

8

7

6

5

4

7

6

5

4

3

.2

1

LSB

4

3

2

1

LSB

X

X

10

9

8

6

5

X

Sign MSB

Sign MSB

with

Bits

Sign

17
LSB
Bits

1

2

3

4

5

6

7

8

9

10

MSB

Sign

LSB 13
LSB
First Bits

1

2

3

4

5

6

'7

8

9

10

MSB

Sign

LSB

1

2

3

4

5

6

0

0

0

0

MSB

10

9

6

5

4

3

9
Bits
16
Bits

MSB 12
MSB
First Bits

7

6

5

4

MSB

6

5

4

3

2

1

LSB

16
LSB
Bits

1

2

3

4

5

6

LSB 12
LSB
First Bits

1

2

3

4

5

1

2

3

4

5

8
Bits

LSB

1

LSB

X

X

X

X

2

1

LSB

0

0

0

'.

8

8

7

8

9

Bits

2

MSB Sign

10

without
Sign

'3

3

2

1

LSB

7

8

9

10

MSB

6

7

8

9

10

MSB

6

MSB

0

x = High or Low slate.
TABLE II. ADC12038 Multiplexer Addressing
Analog Channel Addressed
and Assignment
with AlDIN1 tied to MUXOUT1
and AlDIN2 tied to MUXOUT2

MUX
Address

AID Input
Polarity
Assignment

Multiplexer
Output
Channel
Assignment

Mode

DIO 011 012 013 CHO CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM AlDIN1 A/DIN2 MUXOUT1 MUXOUT2
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

+

+

+

-

-

+
+

-

+
+
+
+

+

-

+

-

-

-

-

+
-

+

-

+

-

+
+
+
+
+
+
2-464

-

+
+
+
+
+
+
+
+

-

-

+
+
+
+
-

-

-

CHO
CH2
CH4
CH6
CHO
CH2
CH4
CH6

CH1
CH3
CH5
CH7
CH1
CH3
CH5
CH7

Differential

CHO
CH2
CH4
CH6
CH1
CH3
CH5
CH7

COM
COM
COM
COM
COM
COM
COM
COM

Single-Ended

Tables (Continued)

.

TABLE III. AOC12034 Multiplexer Addressing
Analog Channel Addressed
and Assignment
with AlDIN1 tied to MUXOUTl
and AlDIN2 tied to MUXOUT2

MUX
Address
DID

011

012

CHO

CHl

L
L

L
L
H
H

L
H

+

-

L

-

H

L
L

H

L
L
H
H
H
H

H
H

CH2

+

CH3

+

-

-

+

COM

-

+

L

+

-

+

L

-

+

H

AID Input
Polarity
Assignment

Multiplexer
Output
Channel
Assignment

Mode

AlOINl

AlOIN2

MUXOUTl

MUXOUT2

+
+
+
+
+
+

-

CHO
CH2
CHO
CH2

CHl
CH3
CHl
CH3

Differential

CHO
CH2
CH1
CH3

COM
COM
COM
COM

Single-Ended

-

+
+
-

TABLE.IV. AOC12032 and AOC12030 Multiplexer Addressing

MUX
Address
DID

011

L·

Analog Channel Addressed
and Assignment
with AlDIN1 tied to MUXOUT1
and AlDIN2 tied to MUXOUT2
CHO

CHl

+

+

L
L

H

-

H
H

L

+

H

COM

-

+

-

AID Input
Polarity
Assignment

Multiplexer
Output
Channel
Assignment

Mode

AlOINl

AlOIN2

MUXOUTl

MUXOUT2

+

-

+

CHO
CHO

CHl
CHl

Differential

+
+

-

CHO
CH1

COM
COM

Single-Ended

Note: ADC12030 and ADC12H030 do not have AlDIN1. AlD.IN2. MUXOUT1 and MUXOUT2 pins.

2-465

Tables (Continued)
TABLE V. Mode Programming
AOC12038

0,10

011'

012

AOC12034

010

011

012

AOC12030
and
AOC12032

010

011

013

014

015

016

017

013

014

015

016

012

013

014

015

See Tables 11,111 or IV

L

L

L

See Tables 11,111 or IV

L

L

L

L

L

H

L

8 Bit Conversion

8 or 9 Bit MSB First

L

L

H

H

12 Bit Conversion of Full-Scale

12 or 13 Bit MSB First

See Tables II, III or IV

L

H

L

L

12 Bit Conversion

12 or 13 Bit LSB First

See Tables II, III or IV

L

H

L

H

12 Bit Conversion

16 or 17 Bit LSB First

See Tables II, III or IV
L
"

L

L

L

See Tables 11,111 or IV

.;,

Mode Selected
(Current)

00 Format
(next Conversion
Cycle)

L

12 Bit Conversion

12 or 13 Bit MSB First

H

12 Bit Conversion

16 or 17 Bit MSB First

L

H

H

L

8 Bit Conversion

8 or 9 Bit LSB First

L

L

L

L

L

H

H

H

12 Bit Conversion of Offset

12 or 13 Bit LSB First

L

L

L '

L

H

L

L

L

Autoeal'

No Change

L

L

L

L

H

L

L

H

Auto Zero

No Change

L

L

L

L

H

L

H

l

Power Up

No Change

~

L

L

L

H

L

H

,H

Power Down

No Change

L

L

L

L

H

H

L

L

Read Status Register

No Change

L

L

L

L

H

H

L

H

Data Out without Sign

No Change

H

L

L

L

H

H

L

H

Data Out with Sign

No Change

L

L

L

L

H

H

H

L

Acquisition Time-6 CCLK Cycles

No Change

L

H

L

L

H

H'

H

L

Acquisition TIme-10 CCLK Cycles

No Change

H

L

L

L

H

H

H

L

Acquisition Time-18 CCLK Cycles

No Change

H

H

L

L

H

H

H

L

Acquisition Time-34 CCLK Cycles

No Change

L

L

L

L

H

H

H

H

User Mode

No Change

H

Test Mode
(CH1-CH7 become Active Outputs)

No Change

H

X

X

X

H

H

H

Nole: The AID powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12·bR

X

~

+ sign conversion, power up, 12· or 13·bit MSB first, and user mode,

Don't Care

TABLE VI. Conversion/Read Data Only Mode Programming

"

x

CS

CONV

PO

Mode

L

L

L

See Table V for Mode
Read Only (Previous DO Format), No Conversion,

L

H

L

H

X

L

Idle

X

X

H

Power Down

= Don't Care

l>
C

o......

Tables (Continued)

N

::z::
o

TABLE VII. Status Register
Status Bit
Location

DBD

DB1

DB2 '

Status Bit

PU

PD

Cal

(0)

DB3

DB4

DBS

DB6

DB7

DBB

B or9

12 or 13

16 or 17

Sign

Justification

Test Mode

When "High"
the
conversion
resull will be
output MSB
first. When
"Low" the
resullwill be
output LSB,
first.

When "High"
the device is
in test mode .
When "Low"
the device is
in user mode.

l>

Device Status
"High"
indicates a
Power Up
Function Sequence is
in progress

"High"
indicates a
Power Down
Sequence is
in progress

DO Output Format Status
"High"
indicates an
Auto-Cal
Sequence is
in progress

"High"
"High"
indicates an 8 indicates a 12
or 9 bit format or 13 bit
format

"High"
indicates a 16
or 17 bit
format

"High"
indicates that
the sign bit is
included.
When "Low"
the sign bit is
not included.

1.1 Interface Concepts
The example in Figure 5 shows a typical sequence of
events after the power is applied to the ADC12030/2/4/8:

The configuration of the ADC12030/2/4/8 on power up dElfaults to 12-bit plus sign resolution, 12- or 13-bit MSB First,
10 CCLK acquisition time, user mode, no Auto Cal, no Auto
Zero, and power up mode. Changing the aquisition time and
turning the sign bit on and off requires an 8-bit instruction to
be issued to the ADC. This instruction will not start a conversion. The instructions that select a multiplexer address and
format the output data do start a conversion. Figure 6 describes an example of changing the configuration of the
ADC12030/2/4/8.
During liD sequence 1, the instruction on 01 configures the
ADC12030/2/4/8 to do a conversion with 12-bit +sign resolution. Notice that when the 6 CCLK Acquisition and Data
Out without Sign instructions are issued to the ADC, 110
sequences 2 and 3, a new conversion is not started. The
data output during these instructions is from COnversion N
which was started during 110 sequence 1. The Configuration Modification timing diagram describes in detail the sequence of events necessary for a Data Out without Sign,
Data Out with Sign, or 6/10/18/34 CCLK Acquisition time
mode selection. Table V describes the actual data necessary to be input to the ADC to accomplish this configuration
modification. The next instruction, shown in Figure 6, issued
to the AID starts conversion N + 1 with 8 bits of resolution
formatted MSB first. Again the data output during this 110
cycle is the data from conversion N.
The number of SCLKs applied to the AID during any conversion 110 sequence should vary in accord with the data
out word format chosen during the previous conversion liD
sequence. The various formats and resolutions available
are shown in Table I. In Figure 6, since 8-bit without sign
MSB first format was chosen during 110 sequence 4, the
number of SCLKs required during 110 sequence 5 is 8. In
the following liD sequence the format changes to 12-bit
without sign MSB first; therefore the number of SCLKs required during 110 sequence 6 changes accordingly to 12.

Trash

Trash

Status Data
(Col low)

(0)

N

.......

l>
C

o
......
N
::z::
o

(0)
.j:o.

.......

l>

c

N

1.2 Changing Configuration

Read status

::z::
o

o
......

1.0 DIGITAL INTERFACE

Read Status

C

o
....
N

Application Hints

DO

o
.......

12-BiHSign
ConY 1

12-Bit+SI9j

Status Dota

Cony 1
Data

Conv2

I

TLlH/11354-36

FIGURE 5. Typical Power Supply Power Up Sequence
The f,irst instruction input to the AID via 01 initiates Auto Cal.
The data output on DO at that time is meaningless and is
completely random. To determine whether the Auto Cal has
been completed, a read status instruction is issued to the
AID. Again the data outputat that time has no significance
since the Auto Cal procedure modifies the data in the output
shift register. To retrievethe status information, an additional read status instruction is issued to the AID. At this time
the status data is available on DO. If the Cal signal in the
status word, is low Auto Cal has been completed. Therefore, the next instruction issued can start a conversion. The
data output at this time is again status information. To keep
noise from corrupting the AID conversion, status can not be
read during a conversion. If CS is strobed and is brought low
during a conversion, that conversion is prematurely ended.
EOC can be used to determine the end of a conversion or
the AID controller can keep track in software of when it
would be appropriate to comnmunicate to the AID again.
Once it has been determined that the AID has completed a
conversion, another instruction can be transmitted to the
AID. The data from this conversion can be accessed when
the next instruction is issued to the AID.
Note, when CS is low continuously it is important to transmit
the exact number of SCLK cycles, as shown in the timing
diagrams. Not doing so will desynchronize the serial communication to the AID. (See Section 1.3.)

1.3 CS Low Continuously Considerations
When CS is continuously low, it is important to transmit the
exact number of SCLK pulses that the ADC expects. Not
doing so will desynchronize the serial communications to
the ADC. When the supply power is first applied to the ADC,

2-467

::z::
o
(0)

JR
l>
C

o
......

N

o

(0)

o
.......

l>

c

o
......

N

o

(0)

N

.......

l>

c
o......
N

o

~fI
c

o
......

N

o

(0)

CD

Application Hints

(Continued)
it will expect to see 13 SCLK pulses for each I/O transmis-,
sion. The number of SCLK pulses that the ADC expects to
see is the same as the digital output word length. The digital
output word length is controlled by the Data Out (DO) format. The DO format maybe changed any time a conversion
is started or when the sign bit is turned on or off. The table
below details out the number of clock periods ,required for
different DO formats:

12-Bit MSB or LSB First

16-Bit MSB or LSB first

SIGN OFF

8

SIGN ON

9

SIGN OFF

12

SIGN ON

13

SIGN OFF

16

SIGN ON

17

DIO DI1

CSStrobed

Auto Cal

13SCLKs

8SCLKs

Read Status

13SCLKs

8SCLKs

Read Status

13SCLKs

8SCLKs

+ Sign Conv 1
12-Bit + Sign Conv 2

13SCLKs

8SCLKs

13SCLKs

13 SCLKs

12-Bit

ADC12H030
ADC12030

L

H

L

L

H

L

X

X

ADC12H032
ADC12032

L

H

L

L

H

L

X

X

ADC12H034
ADC12034

L

H

L

L

L

H

L

X

ADC12H038
ADC12038

L

H

L

L

L

L

H'

L

1.5 Power Up/Down
The ADC may be powered down at any time by taking the
PD pin HIGH or by the instruction input on DI (see Tables V
and VI, and the Power Up/Down timing'diagrams). When
the ADC is powered down in this way, the circuitry necessary for an AI D conversion is deactivated. The circuitry necessary for digital I/O is kept active. Hardware power up/
down is controlled by the state oUhe PD pin. Software power-up/down is controlled by the instruction issued to the
ADC. If a software power up instruction is issued to the ADC
while,a hardware power down is in effect (PD pin high) the
device Will,' remain in the power-down state. If a software
power down instruction is issued to the ADC while a hardware power up is in effect (PO pin low), the device will power
down. When the device is powered down by software, it
may be powered up by either i!,!suing a software power up
instruction or by taking PD pin high and then low. If the
power down command is issued during an AID conversion,
thil.t conversion is disrupted. Therefore, the data output after
power up cannot be relied upon.

The miniber of clock pulses required for an I/O ~xchange
may be different for the case when CS'is left low,continuously vs the case when CS is cycled. Take the I/O sequence detailed in Figure 5 (Typical Power Supply Sequence) as an example: The table below lists the number of
SCLK pulses required for each instruction:
"
CSLow
Continuously

DI2 DI3 DI4 DI5 DI6 DI7

Where X can be a logic high (H) or low (l).

If erroneous SCLK pulses desynchronize the' communications, the simplest way, to recover is by cycling' the power
'supply to the device. Not being able to easily resynchronize
the device is a shortcoming of leaving CS low continuously.

Instruction

DI Data

,Part Number

Number of
SCLKs
Expected

DO Format
8-Bit MSB or LSB First

,In Figure 6 the only times when the channel configuration
could be modified would be during 110 sequences 1, 4, 5
and 6. Input channels are reselected before the start of
each new conversion. Shown below is the data bit stream
required on DI, during I/O sequence number 4 in Figure 6,
to set CH1 as the positive input and CHO as the negative
input for the different versions of ADCs:

1.4 Analog Input Channel Selection
The data input on DI also selects the channel configuration
for a particular AID conversion (see Tables II, III, IV and V).

I/o s.q~.nc.1

01

Cony N
12-Bit+Sign
IASB First
'CHO

H

2

3

6 CClK,
Acquisition

Data Out
without Sign

I

r

5

Cony N+1
B-Bit
IASB First

f-t

Cony N+2
12-Bit
LSB First

f-t

Cony N+3
12-Bit
LSB First

00
TUH/11354-37

FIGURE 6. Changing the ADC's Conversion Configuration

2-468

Application Hints (Continued)
1.6 User Mode and Test Mode
An instruction may be issued to theADC to put it into test
mode. Test mode is used by the manufacturer to verify com·
plete functionality of the device. During test mode CHOCH7 become active outputs. If the device is inadvertently
put into the test mode with CS continuously low. the serial
communications' may be desynchronized. Synchronization
may be regained by cycling the power supply voltage to the
device. Cycling the power supply voltage will also set the
device into user mode. If CS is used in the serial interface.
the ADC may be queried to see what mode it is in. This is
done by issuing a "read STATUS register" instruction to the
ADC. When bit 9 of the status register is high. the ADC is in
test mode; when bit 9 is low the ADC. is in user mode. As an
alternative to cycling the power supply. an instruction sequence may be used to return the device to user mode. This
instruction sequence must be issued to the ADC using CS.
The following table lists the instructions required to return
the device to user mode:

01 Data

Instruction

After returning to user mode with the user mode instruction
the power up, data with or without sign. and acquisition time
instructions need to be resent to ensure that the ADC is in
the required state before a conversion is started.
1.7 Reading the Data Without Starting a Conversion
The data from a particular conversion may be accessed
without starting a new conversion by ensuring that the
CONY line is taken high during the I/O sequence. See the
Read Data timing diagrams. Table VI describes the operation of the CONY pin.

2.0 DESCRIPTION OF THE ANALOG MULTIPLEXER
For the ADC12038. the analog input multiplexer can be configured with 4 differential channels or 8 single ended channels with the COM input as the zero reference or any combination thereof (see Figure 7). The difference between the
voltages on the VREF+ and VREF- pins determines the
input voltage span (VREF). The analog input voltage range is
o to VA + . Negative digital output codes result when VIN - >
VIN+. The actual voltage at VIN- orVIN+ cannot go below
AGND.

DID 011 012 013 014 015 016 017

x

8 Single-Ended Channels
with COM
as Zero Reference

4 Differential
Channels

TEST MODE

H

X

X

X

H

H

H

H

Reset
Test Mode
Instructions

L

L

L

L

H'

H

H

L

L

L

L

L

H

L

H

L

L

L

L

L

H

L

H

H

+(-)
-(+)

CHO
CHl
CH2
CH3

USER MODE

L

L

L

L

H

H

H

H

Power Up

L

L

L

L

H

L

H

L

+(-)
-(+)

CH4
CH5

Set DO with
or without
Sign

H
or
L

+(-)
-(+)

CH6
CH7

L

L

L

H

H

L

H

Set
Acquisition
Time

H
or
L

H
or
L

L

L

H

H

H

L

Start
a
Conversion

H
or
L

H
or
L

H
or
L

H
or
L

L

H
or
L

H
or
L

H
or
L

+(-)
-(+)

+
+
+
+
+
+
+
+

TUH/11354-3B

TL/H/11354-39

FIGURE 7
CHO. CH2. CH4. and CH6 can be aSSigned to the MUXOUT1 pin in the differential configuration. while CH1. CH3.
CH5, and CH7 can be assigned to the MUXOUT2 pin. In the
differential configuration. the analog inputs are paired as follows: CHO with CH1. CH2 with CH3. CH4 with CH5 and CH6
with CH7. The AlDIN1 and AlDIN2 pins can be aSSigned
positive or negative polarity.

= Don'l Care

2-469

Application Hints (Continued)
With the single-ended' multiplexer configuration CHO
through CH7 'can be assigned to the MUXOUT1 pin. The
COM pin is always assigned to the MUXOUT2 pin. AlDIN1
is assigned as the positve input; AlDIN2 is assigned as the
negative input. (See Figure 8).
Differential
Configuration

.... 1

CH1
CH3
CH5
CH7

.... 1

--]

CHO
CH1
CH2
, CH3
CH4
CH5
CH6
CH7

Muic OUT1

-

.... 1

2.1 Biasing for Various Multiplexer Configurations
Figure 9 is an example of blasin'g the device for single-ended operation. The sign bit is always low. The digital output
range is 0 0000 0000 0000 to 0111111111111. One LSB
is equal to 1 mV (4.1V/4096 LSBs).

Single-Ended
Configuration

-

CHO
CH2
CH4
CH6

The Multiplexer assignment tables for the ADC12030,2,4,B
(Tables II, III, and IV) summarize the aforementioned functions for the different versions of AIDs.

Muic OUT2

........

....... -

COM

....
....

MUX oun

TLlH111354-4D

AlOIN1 and AlDIN2 can be as·
signed as the + or - Input

'MUx OUT1

TLlH/11354-41

AlDIN1 Is + Input
AlDIN2 is - input

FIGURE 8

VAt

ANALOG
INPUT
VOLTAGE
RANGE
OV TO 4.096V

"v
ASSIGNED
(+) INPUT

CHO
CHI
CH2

10
CH7

+S.OV
Vo+

12-BITS UNSIGNED
ASSIGNED
(-) INPUT

ADC1203Y
COM

VREF +
I-....----~......-

....- - - -..._o

+4.096V

LM4040-4.1
DGND
ANALOG
, INPUT
VOLTAGE
GROUND
REFERENCE

AGND

r-...-------....- -...
TL/H/11354-46

FIGURE 9. Single-Ended Biasing

2-470,

li-

e

Application Hints (Continued)
periods, the input biasing resistor needs to be 600n or less.
Notice though that the input coupling capacitor needs to be
made fairly large to bring down the high pass comer. Increasing the acquisition time to 34 clock periods (with a
5 MHz CCLK frequency) would allow the 600n to increase
to 6k, which with a 1 poF coupling capacitor would set the
high pass corner at 26 Hz. Increasing R, to 6k would allow
R2 to be 2k.

For pseudo-differential signed operation, the biasing circuit
shown in Figure 10 shows a signal AC coupled to the ADC.
This gives a digital output range of -4096 to + 4095. With a
2.5V reference, as shown, 1 LSB is equal to 610 poV. Although, the ADC is not production tested with a 2.5V reference, linearity error typically will not change more than 0.1
LSB (see the curves in the Typical Electrical Characteristics
Section). With the ADC set to an acquisition time of 10 clock

o
....

I\)

::::t:
C)
Co)
C)

.....

li-

e

o
....

I\)

::::t:

C)
Co)
I\)

ANALOG
INPUT
VOLTAG(
RANGE
OV TO 5.0V

.....

VA+

"v

>-I

ASSIGNED
(+) INPUT

12-BITS SIGNED
60011
(DEPENDS ON
ACQUISITION
TIM()

li-

CHO
CHI
CH2

e

o
....

10

VO+

CH8

RI

I\)

::::t:

C)
Co)

ADC1203Y

ASSIGNED
(-) INPUT

.....
"'"

li-

VREF +

COM

e

o
....
I\)

::::t:

C)
Co)

LM9140-2.5

s»

li-

ANALOG
INPUT
VOLTAGE
"

e
o....

>--+______.....;....._---1

GROUND
• REFERENCE
TLlH/I1354-47

e

with a single + 5V supply. Using an adjustable version of the
LM4041 to set the full scale voltage at exactly 2.048V and a
lower grade LM4040D-2.5 to bias up everything to 2.5V as
shown in Figure 12 will allow the use of all the ADC's digital
output range of -4096 to +4095 while leaving plenty of
head room for the amplifier.
Fully differential operation is shown in Figure 13. One LSB
for this case is equal to (4.1V/4096) = 1 mV.

, ANALOG
INPUT

....-JV'<'Ir---, ~~~~~GE

ov
ANALOG
INPUT
VOLTAGE

TO 5.0V

CHO '

12-BITS SIGNED

CH 1

10

ADC1203Y
VREF +

1---q.,~~'9-:--:-"':'1I...,..-:-............t---o +2.5V

LM9140-2.5

ANALOG
INPUT
VOLTAGE
GROUND
REFERENCE

I\)
C)
Co)
I\)

.....
li-

e

o
....
I\)
C)

~.
e
I\)
C)
Co)
CIC)

+5.0V

CH8

ASSIGNED

o
....

o
....

>-------f CH2

T COM
L....--6------~("'-)",I_NP_U-I

.....
li-

FIGURE 10. Pseudo-Differential Blasing with the Signal Source AC Coupled Directly into the ADC
An alternative method for biasing pseudo-differential operation is to use the + 2.5V from the LM9140 to bias any amplifier circuits driving the ADC as shown in Figure 11. The
value of the resistor pull-up biasing the LM9140-2.5 will depend upon the current required by theop 'amp biasing circuitry.
In the circuit of Figure 11 some voltage'range is lost since
the amplifier will not be able to,swing to +5Vand GND

I\)
C)
Co)
C)

>--+------......;:.....----1
TL/H/I1354-48

FIGURE 11. Alternative Pseudo-Differential Biasing

2-471

Application Hints (Continued)
4N4LOG
INPUT
VOLTAGE
RANGE
.---'VV\ro-.... 2.SV:l:2.048V
12-81TS SIGNED

ANALOG
INPUT
VOLTAGE

CHO
CHI
-~=~CH2
ASSIGNED
10
(+) INPUT CH8

> .....
_k
L - _....._ _ _ _

ASSIGNED

"f--O+5.0V

ADC 1203Y

~~-(;..-.;..).;;.IN;;..PU;..T.... COM

VREF + I-....~~~~~~~~-.....-

....-o +2.048V

LM4040D-2.5

ANALOG
INPUT
VOLT4GE >----~~---1
GROUND
REFERENCE
TLlH/I1354-49

FIGURE 12. Pseudo-Differential Biasing wHhout the LoSI of Digital Output Range

.....-O+s.OV

ADC1203Y

FULLY DIFFERENTIAL
12-BIT PLUS SIGN

AN4LOG
INPUT
VOLTAGE
RANGE
O.4SV TO 4.SSV

V'
4SSIGNED
(-) INPUT

CHI
CH3
CHS

I

II

lk

VREF + .........- -...- -...- - -....--oU.1V

or
CH7
VREF -

LM4040-4.1

4N4LOG
INPUT
VOLTAGE >----~~GROUND
REFERENCE

....
TLlH/I1354-50

FIGURE 13. Fully Differential Blallng

2-472

~

C

Application Hints (Continued)

o
....
N

3.0 REFERENCE VOLTAGE
The difference in the voltages applied to the VREF't- and
VREF- defines the analog input span (the difference· between the voltage applied between two multiplexer inputs or
the voltage applied to one of the multiplexer inputs and analog ground), over which 4095 positive and 4096 negative
codes exist. The voltage sources driving VREF+ or VREFmust have very low output impedance and noise. The circuit
in Figure 14 is an example of a very stable reference appropriate for use with the device. .
VIN

•

::J:

v'
A

oCo)

~C
o
....
N

::J:

tE

~ 0.6

oCo)

v,.+. O.5V

N

;;
C
o
....

,::

+12V to +ISV

I.akn
0.2

N

v,,·

::J:

oCo)

+12V to +15V

l"1

. ~. :

VREf OUT
2.46kn
0.1"

-=

. ".. '.

+4.096V

:.:.;:' .

>--+-----+

Ao
.....

.

.~.

0.6 VA..... D.5V

V...

....

-=

·Tantalum

TL/H/11354-45

TL/H/11354-42

FIGURE 15. VREF Operating Range

FIGURE 14. Low Drift Extremely
Stable Reference Circuit· .

4.0 ANALOG INPUT VOLTAGE RANGE
The ADC12030/2/4/S's fully differential ADC generate a
two:s complement output that is found by using the equations shown below:

The ADC 12030/2/4/8 clm be used in eith'er ratiometric or
absolute reference applications. In ratiometric systems, the
analog input voltage is proportional to the voltage used for
the ADC's reference voltage. When this voltage is the system power supply, the VREF+ pin is connected to VA + and
VREF- is connected to ground. This technique relaxes the
system reference stability requirements because the analog
input voltage and the ADC reference voltage move together. This maintains the same output code for given input conditions. For absolute accuracy, where the analog input voltage varies between very specific voltage limits, a time and
temperature stable voltage source can be connected to the
reference inputs. Typically, the reference voltage's magnitude will require an initial adjustment to null reference voltage induced full-scale errors.
Below are recommended references along with some key
specifications.
Output
Voltage
Tolerance

Temperature
. Coefficient

LM4041 CI-Adj

±0.5%

LM4040AI-4.1

Part Number

for (1·2-bit) resolution the Output Code =
(VREF+ - VREF-)
for (S-bit) resolution the Output Code =

+1V

±100ppm1'C

+4.096V

OV

±0.1%

±100ppm1'C

+4.096V

OV

LM9140BYZ-4.1

±0.5%

±2Sppml'C

+4.096V

OV

LM368Y-5.0

±0.1%

±20ppml'C

Adjustable

+2ppml'C

VIN-

~FJI

m

OV

0,1111,1111,1111

+3V

OV

0,1011,1011,1000

+2.499V +2.500V 1,1111.1111,1111
+4.096V 1,0000,0000,0000

5.0 INPUT CURRENT

2-473

o

g
....

At the start of the acquisition window (tA) a charging current
,flows into or out of the analog input pins (AlDIN1 and
AlDIN2) depending on the input voltage polarity. The analog input pins are CHO-CH7 and COM when AlDIN1 is tied
to MUXOUT1 and AlDIN2 is tied to MUXOUT2. The peak
value of this input current will depend on the actual input
voltage applied, the source impedance and the internal multiplexer switch on resistance. With MUXOUT1 tied to
AlDIN1 and MUXOUT2tied to AlDIN2 the internal multiplexer switch on resistance is typically 1.6 kO. The AlDIN1
and AlDIN2 mux on resistance is typically 7500.

The reference voltage inputs are not iully differential. The·
ADC12030/2/4/S will not generate correct conversions or
comparisons if VREF+ is taken below VREF-' Correct conversions result when VREF+ and VREF- differ by 1V and
remain, at all times, between ground and VA +. The VREF
common mode range, (VREF+ + VREF7")/2 is restricted to
(0.1 x VA+) to (0.6 X VA+). Therefore, with VA+ = SV
the center of the reference ladder should not go below O.SV
or above 3.0V. Figure 15 is a graphic representation of the
voltage restrictions on VREF+ and VREF-'

~
C
o
....
N

Digital
Output
Code

+1.5V

OV

oCo)

~

. Round off to the nearest integer value between -4096 to
4095 for 12-bit resolution' and between - 256 to 255 for
S-bit resolution if the result of the above equation is not a
whole number.
Examples are shown in the table below:

VIN+

~

o
....
N

Co)

(VREF+ - VREF-)

VREF-

oCo)

!»

o
....

(VIN+ - VIN-) (256)

VREF+

N

::J:

~

(VIN+ - VIN-) (4096)

+2.5V

Circuit of Figure 14

~

C

o

3.S2kn
0.1"

N

oCo)

~ r-----------------------~----~----------------------------------------------~

,(0)

....~
,~
~

(0)

....~

~....

~

8cr:

~....
g
cr:

fIf

~
....

N

i
:c
N

....

g

i
N
....

8cr:,
....

Application Hints (Continu~)
1.0 INPUT SOURCE RESIST~CE
For low impedance voltage sources «6000), the input
charging current will decay, before the, end of the S/H's
acquisition time of 2 p.s(1.0 CCLK perio~s with fc = ,5 MH:I;),
to a value that will not Introdu"e any C9nve[lIion errors. For
high source impedances, the S/H's ,acqui$ition time can be
increased to 18 or 34 CCLK periods. :For,les;s'ADC resolution and/or slower CCLK frequenci,~s the,S/H's acql,lis.ition
time may be decreased to 6 CqLK periods. To ,~$t"nnirie
the number of clock periods (NC>required for'the acquisition
time with a specific source impedailC$.fcir Jhe,van'Ous resolutions the following equations can be used:
12 Bit + Sign Ne = [Rs + 2.31 X fe x 0;824
8 Bit + Sign Ne = IRs + 2.31 x'le x 0.~7
Where fc is the conversion clock (OCLK) fr~quency in MHz
and Rs is the external source resistance in kO. As an example, operating with a resolution ,of 12 Bits+sigr:l, a5 MHz
clock frequency and m81Cimum acquistion time of ~4 conversion clock periods the ADC's analOg inputs can handle a
source impedance as high as 6 kO: The acquisition 'time
may also be extended,to compensate 'for the settling or
response time of external CircuitrY connect~d between the
MUXOUT and AlDIN pins.
'
The acquisition time tA is started by a falO1)9
of SCLK
and ended by a rising edge of CCLK (see timing diagrams).
If SCLK and CCLK are asynchronous ol)e extra CCLK clock
period may be Inserted into tile programmed acquisition
time for synchronization. Therefore with aSllYchronouli
SCLK and CCLKs the acquisition time will change from conversion to conversion.
'

a.ONOISE
The leads to each of the analog multiplexer input pins
should be' kept as short as possible. This will minimize input
noise and clock frequency coupling that can cause cO,lwersion errors. Input filtering can be used to reduce the effects
of the noise sources•

9.0 POWER SUPPLIES
Noise spikes on the VA + and Vo + supply lines can cause
Conversion errors; the cOmparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. The
minimum power supply bypassing capacitors recommended
are low inductance tantalum capaCitors of 10 p.F or greater
paralleled with 0.1 p.F monolithic ceramic capaCitors. More
or different bypassing may be necessary depending on the
overall system requirements. Separate bypass cap,aeitors
should 'be used for the VA + and Vo + supplies and placed
as close as possible to these pins.
10.0 GROUNDING
The ADC12030/2/4/8's performance can be maximized
through proper grounding techniques. These include the
use of separate analog and digital ground planes. The digital ground plane is placed under all components that handle
digital signals, while the analog ground plane is placed under all components that handle analog signals. The digital
and analog ground planes are connected together at only
one pOint, either the power supply ground or at the pins of
the ADC. This greatly reduces the occurence of ground
loops and noise.
Shown in Figure 16 is the ideal ground plane layout for the
ADC12038 along with ideal placement o( the bypass capacitors. The circuit board layout shown.!n Figure 16 uses three
bypass capacitors: 0.01 p.F (C1) and 0.1 p.F (C2) surface
mount capacitors and 10 p.F (C3) tantalum capacitor.

edQe'

7.0 INPUT BYPASS CAPACITANCE
External capacitors (0.01 p.F-0.1 p.F) can be connected between the analog input pins, CHO-CH7. and analog ground
to filter any noise caused by inductive pickup a~sOciated
with long input leads. These capacitors will not degrade the
conversion accuracy.

~....
N

0,
Q

cr:

, TLlH/11354-43

FIGURE 11. Ideal Ground Plane

2-474

Application Hints (Continued)
noise + distortion ratio (S/(N + 0», effective bits, full power bandwidth, aperture time and aperture jitter are quantitative measures of the AID converter's capability.
An AID converter's AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal
waveform is applied to the AID converter's input, and the
transform is then performed on the digitized waveform.
S/(N + D) and SIN are calculated from the resulting FFT
data, and a spectral plot may also be obtained. Typical values for SIN are shown in the table of Electrical Characteristics, and spectral plots of S/(N + D) are included in the
typical performance curves.
The AID converter's noise and distortion levels will change
with the frequency of the input Signal, with more distortion
and noise occurring at higher signal frequencies. This can
be seen in the S/(N + D) versus frequency curves. These
curves will also give an indication of the full power bandwidth (the frequency at which the S/(N + D) or SIN drops
3 dB).

11.0 CLOCK SIGNAL LINE ISOLATION
The ADC12030/2/4/B's performance is optimized by routing the analog input! output and reference signal conductors
as far as possible from the conductors that carry the clock
signals to the CCLK and SCLK pins. Ground traces parallel
to the clock signal traces can be used on printed circuit
boards to reduce clock signal interference on the analog
input/output pins.

12.0 THE CALIBRATION CYCLE
A calibration cycle needs to be started after the power supplies, reference, and clock have been given enough time to
stabilize after initial tum-on. During the calibration cycle, correction values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall full-scale,
offset, and linearity errors down to the specified limits. Fullscale error typically changes ± 0.4 LSB over temperature
and linearity error changes even less; therefore it should be
necessary to go through the calibration cycle only once after power up if the Power Supply Voltage and the ambient
temperature do not change significantly (see the curves in
the Typical Performance Characteristics).

Effective number of bits can also be useful in describing the
AID's noise performance. An ideal AID converter will have
some amount of quantization noise, determined by its resolution, which will yield an optimum SIN ratio given by the
following equation:
SIN = (6.02 x n + 1.B)dB

13.0 THE AUTO-ZERO CYCLE
To correct for any change in the zero (offset) error of the
AID, the auto-zero cycle can be used. It may be necessary
to do an auto-zero cycle whenever the ambient temperature
or the power supply voltage change significantly. (See the
curves titled "Zero Error Change VB Ambient Temperature"
and "Zero Error Change VB Supply Voltage" in the Typical
.
Performance Characteristics.)

where n is the AID's resolution in bits.
The effective bits of a real AID converter, therefore, can be
found by:
.( ff . ) _ SIN(dB) - 1.B
n e ectlve 6.02
As an example, this device with a differential signed 5V,
10 kHz sine wave input signal will typically have a SIN of
7B dB, which is equivalent to 12.6 effective bits.

14.0 DYNAMIC PERFORMANCE
Many applications require the AID converter to digitize AC
signals, but the standard DC integral and differential nonlinearity specifications will not accurately predict the AID converter's performance with AC input signals. The important
specifications for AC applications reflect the converter's
ability to digitize AC signals without significant spectral errors and without adding noise to the digitized signal. Dynamic characteristics such as signal-ta-noise (SIN), signal-to-

15.0 AN RS232 SERIAL INTERFACE
Shown on the follOwing page is a schematic for an RS232
interface to any IBM and compatiblePCs. The DTR, RTS,
and CTS RS232 signal lines are buffered via level translators and connected to the ADC1203B's DI,SCLK, and DO
pins, respectively. The 0 flip flop drives the ~ control line.

2-475

co
C")

r-------------------------------------~----------~------~------------------------------_,

~.

....

Application Hints (Continued)

o
c

,+5V .'

~
o
....

+5V

C")

5 t.tHz·

N

g

1/40S14C89

0 1 1 - - - - - - - - - -.....

CC
.....
N

001----------+-+---,
csl-------,

C")

o
.N

....
o

>C~~CTS

RS232

c

~

Connector

oC")
o

N
....

U.096V

o

c

CC

OGNO

+5V

t.tM7474
; TUH/I1354-44
Note: VA+, Vo+, and VREF+ on theADC12038 each have 0.01 p.F and 0.1 "F chip caps, and 10 "F tantalum caps. All logic devices are bypassed with 0.1 "F
caps.'
.

The assignment of the RS232 port is shown below

. B7

I 3FE
I Output Address I 3FC

COM1 llnput Address

B6 . B5

B4

B3.

B2 .. B1

BO

X

X

X

CTS

X'

X

X

X

X

X

X

0

X

X

RTS

DTR

A sample program, written in Microsoft QuickBasic, _is
shown on the n'ext page. The program prompts for data
mode select instruction tobe.sent to the AID. This can. be
found from the Mode Programming table shown earlier. The
data should be entered in "1"s and "O"!! as shown. the
table with 010 first. Next the program prompts for the number of SCLKs required for the programmed mode select instruction. For instance, to send all "O"s to the AID, selects
CHO as the +input, CH1 as the -input, 12-bit conversion,
and 13-bit MSB first data output format (if the sign bit was
not turned off by a previous instruction). This would require
13 SCLK periods since the output data format is 13 bits. The

part powers up with No Auto Cal, No Auto Zero, 10 'CCLK
Acquisition Time, 12-bit conversion; data out with sign, pow:
er up,12- or 13:bit MSB first,. and user mode. Auto Cal, Auto
Zero, Power l!Ipand Power Down instructions ,do. not
change these default settings:' The following power up sequence should be followed:

in

1:Flun the program
2. ,Prior, to responding to the prompt apply the power to the
ADC12038
'
3. Respond to the program prompts
II is recommended that the first instruction issued to the
ADC12038 be Auto Cal (see Section 1.1).

2-476

Application Hints (Continued)
'variables DOL=Data Out word length, DI=Data string tor AID DI input,
,
DO=A/D result string
'SET CS# HIGH
OUT &H3FC, (&H2 OR INP (&H3FC»
'set RTS HIGH
OUT &H3FC, (&SFE AND INP(&H3FC»
'setDTR LOW
OUT lH3FC, (&HFD AND INP(&H3FC»
'set RTS LOW
OUT &H3FC, (&HEF AND INP(&H3FC»
'set B4 low
10
LINE INPUT "DI data tor ADC12038 (see Mode Table on data sheet)"; DI$
INPUT "ADC12038 output word length (8,9,12,13,16 or 17)"; DOL
20
'SET CS# HIGH
OUT &H3FC, (&H2 OR INP (&H3FC»
'set RTS HIGH
OUT &H3FC, (&HFE AND INP(&H3FC»
'set DTR LOW
OUT &H3FC, (&HFD AND INP(&H3FC»
'set RTS LOW
'SET CS# LOW
OUT &H3FC, (&H2 OR INP (&H3FC»
'set RTS HIGH
OUT &H3FC, (&Hl OR INP(&H3FC»
'set DTR HIGH
OUT &H3FC, (&HFD AND INP(&H3FC»
'set RTS LOW
'reset DO variable
DO$=" "
OUT &H3FC, (&Hl OR INP(&H3FC»
'SET DTR HIGH
OUT &H3FC, (&HFD AND INP(&H3FC»
'SCLK low
FOR N=l TO 8
Temp$=MID$(DI$,N,l)
IF Temp$="O"THEN
OUT &H3FC,(&Hl OR INP(&H3FC»
ELSE OUT &H3FC, (&HFE AND INP(&H3FC»
END IF
'out DI
OUT &H3FC,(lH2 OR INP(&H3FC»
'SCLK high
IF (INP(&H3FE) AND 16)=16 THEN
DO$=DO$+"O"
ELSE
DO$=DO$+"l"
END IF
'input DO
'SET DTR HIGH
OUT &H3FC, (&Hl OR INP(&H3FC»
OUT &H3FC, (&HFD AND INP(&H3FC»
'SCLK low
NEXT N
IF DOL>8 THEN
FOR N=9 TO DOL
'SET DTR HIGH
OUT &H3FC,(&Hl OR INP(&H3FC»
OUT &H3FC,(&HFD AND INP(&H3FC»
'SCLK low
OUT &H3FC,(&H2 OR INP(&H3FC»
'SCLK high
IF (INP(&H3FE) AND &H10)=&H10 THEN
DO$=DO$+"O·
ELSE
DO$=DO$+"l"
END IF
NEXT N
END IF
OUT &H3FC,(&HFA AND INP(&H3FC»
'SCLK low and DI high
FOR N=l TO 500
NEXT N

PRINT DO$
INPUT "Enter "C" to convert else "RETURN" to alter DI data"; s$
IF s$="C" OR s$="c" THEN
GOTO 20
ELSE
GOTO 10
END-IF
END

2·477

~ r-------~--------~----------------------------------------------------__,

9
C'I
..o
c
cc

t!lNational Semiconductor

~
CO)

ADC12L030/ ADC12L032/ ADC12L034/ ADC12L038
9C'I 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O
....
U
A/D Converters with MUX and Sample/Hold
C
~

C'I

9....
C'I

g
~

CO)

9C'I

....
g
cc

General Description

Features

The ADC12L030 family is 12-bit plus sign successive approximation AID converters with serial I/O and configurable
input multiplexers. These devices are fully tested with a single 3.3V power supply. The ADC12L032, ADC12L034 and
ADC12L038 have 2, 4 and 8 channel multiplexers, respectively. Differential multiplexer outputs and AID inputs are
available on the MUXOUT1, MUXOUT2, AlDIN1 and
AlDIN2 pins. The ADC12L030 has a two channel multiplexer with the multiplexer outputs and AID inputs internally
connected. On request, these A/Os go through a self cali'
bration process that adjusts linearity, zero and full-scale er- '
rors to less than ± Yz LSB each.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or pseudo-differential modes. A fully differential unipolar analog input range
(OV to +3.3V) can be accommodated with a single +3.3V
supply. In the differential modes, valid outputs are obtained
even when the negative inputs are greater than the positive
because of the 12-bit plus sign two's compliment output
data format.
The serial I/O is configured to comply with NSC's MICROWIRETM and Motorola's SPI standards. For complementary
voltage references see the LM4040, LM4041 or LM9140
data sheets.

• OV to 3.3V analog input range with single 3.3V power
supply
,
• Serial I/O (MICROWIRE and SPI Compatible) ,
• 2, 4, or 8 channel differential or single-ended,
multiplexer
• Analog input sample/hold function
• Power down mode
• Variable resolution and conversion rate
• Programmable acquisition time
• Variable digital output word length and format
• No zero or full scale adjustment required
• Fully tested and guaranteed with a 2.5V reference
• No Missing Codes over temperature

Key Specifications
•
•
•
•
•
•

12-bit plus sign
8.8 p.s (min)
73 kHz (max)
±1 LSB (max)
3.3V ±100/0
15 mW (max)
40 p.W (typ)

Resolution
12-bit plus sign conversion time
12-bit plus sign sampling rate,
Integral linearity error
Single supply
Power dissipation
-Power down

Applications
• Portable Medical instruments
• Portable computing
• Portable Test equipment

ADC12L038 Simplified Block Diagram
Cs

PD

CONY

CCLK

seCk

t..,=~====t=L--.rIEOC

~--------------t-----+-~COOi

CHO
CHI
CH'

DO

CH'

C"'
CHS
CHO

CH7
COM

WUXOUTI
A/DIN I

0------'

MUXOUT21J+------'

AIm" 0---------1

v•• 1J-+
Vo·1J-+

66

DGND

AGND

TLlH/1,830-,

2-478

.--------------------------------------------------------------------.>
c

Connection Diagrams

....o
N

16·Pin Dual·ln·Llne and
Wide Body SO Packages
CHO

16

Vo+

CHO

20

Vo +

19

CCLK

CHI

2

15

CCLK

CHI

COM

3

14

SCLK

COM

OOR

01
AOC12l030

[OC

VREf -

11

01

DO

A/DIN 1

DO

cs

MUXOUT2

cs

VREf +

CONV

A/01N2

OGNO

VA+

VREf -

[OC

VREf +

OOR

TL/H/11830-2

Q

Co)

~

>
C
....o
N

b

SClK

MUXOUT1

Top View

r

20·Pin Dual·ln·Llne and
Wide Body SO Packages

Co)

N

......

>
C

o....

CONV

N

b

Co)

0l:Io
......

OGNO

>
c

TL/H/11830-3

Top View

o
....
N

b

Co)

24·Pin Dual·ln·Line and
Wide Body SO Packages
CHO

24

Vo+

CHO

CHI

23

OOR

CHI

CH2

22

CClK·

CH2

CH3

21

SClK

CH3

COM

20

01

CH4

01

IAUXOUT1

19

DO

CH5

DO

18

cs

CH6

cs

CONY

CH7

[OC

COM

AOC12L034

A/OINI
MUXOUT2
A/01N2

VREf -

10

PO

YREf +

11

AGNO

DGND

12

13

Top View

co

28·Pin Dual·ln·Line and
Wide Body SO Packages

VA+
TL/H/11830-4

28
2

CCLK
4

SCLK

CONY
[OC
PO

10

19

A/DIN 1

11

18

AGNO

MUXOUT2

12

17

VREf +

A/DIN2

13

16

VREf -

OGND

14

15

VA+

Ordering Information
NSPackage
Number

ADC12L030CIN

N16E

ADC12L030CIWM

M16B

ADC12L032CIN

N20A

ADC12L032CIWM

M20B

ADC12L034CIN

N24C

ADC12L034CIWM

M24B

ADC12L038CIN

N28B

ADC12L038CIWM

M28B

2-479

20

MUXOUT1

Top View

Industrial Temperature Range
-40'C :s: TA :s: +85'C

Yo·
DOR

TL/H/11830-5

CD

9.....
N

~9
N
.....
oQ

cc
.....

!
.....
o

;
N

.....
o
~

Absolute Maximum Ratings (Notes 1 &2)

Operating Ratings (Notes 1 & 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications_

Operating Temperature Range

Positive Supply Voltage
(V+ = VA+ = Vo+)

TMIN ~ TA ~ TMAX
ADC12L030CIN, ADC12L030CIWM,
ADC12L032CIN, ADC12L032CIWM,
ADC12L034CIN, ADC12L034CIWM,
ADC12L03BCIN,
-40·C ~ TA ~ +8S·C
ADC12L038CIWM

6.SV

Voltage at Inputs al)d Outputs
except CHO-CH7 and COM
Voltage at Analog Inputs
CHO-CH7 and COM

-0.3VtoV+ +0.3V

SupplyVoltage(V+

=

VA+

=

Vo+)

+ 3.0V to + S.SV
~

IVA+ - vo+1

100 mV

GND -SVtoV+ +SV

VREF+

OVto VA+

300mV

VREF-

±30mA

VREF (VREF+ - VREF-)
VREF Common Mode Voltage Range

OVtoVREF+
WtoVA+

IVA+ - vo+1
Input Current at Any Pin (Note 3)

±120 mA

Package Input Current (Note 3)
Package Dissipation at
T A = 25·C (Note 4)

(VREF+ + VREF-)
2

SOOmW

ESD Susceptability (Note S)
Human Body Model

lS00V

Soldering Information
N Packages (10 seconds)

260"C

0.1 VA + to 0.6 VA +

A/DIN1, AlDIN2, MUXOUTl
and MUXOUT2 Voltage Range
AID IN Common Mode Voltage Range
(VIN+ + VIN-)

SO Package (Note 6):
Vapor Phase (60 seconds)
Infrared (15 s~c0rlds)

OVto VA+

2

215"C
220·C

OVtoVA+

- 6S·C to + lS0·C

Storage Temperature

Converter Electrical Characteristics
The following specifications apply for V+ = VA + = Vo+ = +3.3 VOC, VREF+ = +2.S00 VDC, VREF- = 0 VOC, 12-bit +
sign conversion mode, fCK = fSK = 5 MHz, Rs = 2S.o, source impedance for VREF+ and VREF- ~ 2S.o, fully-differential input
with fixed 1.2S0V common-mode voltage, and 10(tcKl acquisition time unless otherwise specified. Boldface limits apply for
TA = T .. = TMIN to TMAX; all other limits TA = TJ = 2S·C. (Notes 7, Band 9)
Symbol

Parameter

Conditions

Typical
(Note 10)

12+ sign

Bits (min)

After Auto-Cal (Notes 12, 1B)

±1/2

±1

LSB (max)

±1/2

±1

LSB (max)

±1

LSB (max)

Limits
(Note 11)

Units
(Limits)

STATIC CONVERTER CHARACTERISTICS
Resolution with No MisSing Codes
+ILE

Positive Integral Linearity Error

-ILE

Negative Integral Linearity Error

After Auto-Cal (Notes 12, 18)

DNL

Differential Non-Linearity

After Auto-Cal

Positive Full-Scale Error

After Auto-Cal (Notes 12, 18)

±1/2

±2

LSB(max)

Negative Full-Scale Error

After Auto-Cal (Notes 12, 18)

±1/2

±2

LSB (max)

Offset Error

After Auto-Cal (Notes S, 1B)
VIN(+) = VIN (-) = 1.2S0V

±1/2

±2

LSB (max)

DC Common Mode Error

After Auto-Cal (Note IS)

±2

±3.5

LSB(max)

Total Unadjusted Error

After Auto-Cal
(Notes 12, 13 and 14)

±1

TUE

LSB

Resolution with No MiSSing Codes

8-bit + sign mode

8 + sign

Bits (min)

+INL

Positive Integral Linearity Error

8-bit + sign mode (Note 12)

±1/2

LSB (max)

-INL

Negative Integral Linearity Error

8-bit + sign mode (Note 12)

±1/2

LSB(max)

DNL

Differential Non-Linearity

8-pit + sign mode

±3/4

LSB (max)

Positive Full-Scale Error

8-bit + Sign mode (Note 12)

±1/2

LSB (max)

2-4BO

Converter Electrical Characteristics (Continued)
The following specifications apply forV+ = VA+ = Vo+ = +3.3 VOC, VREF+ = +2.500 VOC, VREF- = 0 VOC, 12-bit +
sign conversion mode, fCK = fSK = 5 MHz, Rs = 250, source impedance for VREF+ and VREF- :s; 250, fully-differential input
with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for
Ta = To! = TMIN to TMAX; all other limits TA = TJ = 25°C. (Notes 7, 8 and 9)
Symbol

Parameter

Typical
(Note 10)

Conditions

Limits
(Note 11)

Units
(Limits)

STATI.C CONVERTER CHARACTERISTICS (Continued)

TUE

Negative Full-Scale Error

8-bit + sign mode (Note 12)

±1/2

LSB (max)

Offset Error

8-bit + sign mode,
after Auto-Zero (Note 13)
VIN(+) = VIN(-) = + 1.250V

±1/2

LSB (max)

8-bit + sign mode
after Auto-Zero
(Notes 12,13 and 14)

±3/4

LSB (max)

Total Unadjusted Error

Multiplexer Channel to Channel
Matching

±0.05

=

Power Supply Sensitivity
Offset Error
. + Full-Scale Error
- Full-Scale Error
+ Integral Linearity Error
- Integral Linearity Error

V+

Output Data from
"12-Bit Conversion of Offset"
(see Table V)

(Note 20)

Output Data from
"12-Bit Conversion of Full-Scale"
(see Table V)

(Note 20)

LSB

+3.3V ±10%
±0.5
±0.5
±0.5
±0.5
±O.5

±1
±1.5
±1.5

LSB (max)
LSB(max)
LSB (max)
LSB
LSB

+10
-10

LSB (max)
LSB(min)

4095
4093

LSB (max)
LSB(min)

UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS

S/(N+D)

Signal-to-Noise Plus
Distortion Ratio
- 3 dB Full Power Bandwidth

= 1 kHz, VIN = 2.5 Vpp
= 20 kHz, VIN = 2.5 Vpp
= 40 kHz, VIN = 2.5 Vpp
VIN = 2.5 Vpp, where S/(N +

fiN
fiN
fiN

0) drops 3 dB

69.4
68.3
65.7

dB
dB
dB

31

kHz

77.0
73.9
67.0

dB
dB
dB

40

kHz

DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS

S/(N+D)

Signal-to-Noise Plus
Distortion Ratio
-3 dB Full Power Bandwidth

= 1 kHz, VIN = ± 2.5V
= 20 kHz, VIN = ± 2.5V
= 40 kHz, VIN = ± 2.5V
VIN = ±2.5V, where S/(N+D) drops 3 dB

fiN
fiN
fiN

2-481

•

Electrical Characteristics
The following specifications apply for V+ = VA + = Vo+ = +3.3 VOC, VREF+ = + 2.500 Voc, VREF- = 0 Voc, 12·bit +
sign conversion mode, fCK = fSK = 5 MHz, Rs = 250, source impedance:for VREF+ and VREF- :5: 250, fully-differential il1put
with fixe,d 1.250V common-mode voltage, and 10(tcK> acquisition time unless otherwise specified. Bo,dfae. limIts apP'ly for
TA = T.. = TMINtoTMAX; all other IimitsTA = TJ = 25"C. (Notes 7, 8'and 9)

I
Parameter

Sjmbol

Conditions

Typical
(Note 10)

Limits
(Note 11)

Units
(Llmlis)

REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
CREF "

Reference Input CapaCitance

85

pF

CA/O

AlDIN1 and AlDIN2 Analog Input
Capacitance

75

pF

AlDIN1 and AlDIN2 Analpg Input
Leakage Current

VIN = +3.3Vor
VIN = OV,

±0.1

±1.0

poA(max)

..

GND - 0.05
VA+ + 0.05

V (min)
V (max)

CHO-CH7 and COM Input Voltage

CcH

CHO-CH7 and COM Input Capacitance
MUX Output CapaCitance

CMUXOUT

Off Channel Leakage (Note 16)
CHO-CH7 and COM Pins

,

!
~

On Cham;el Leakage (Note 16)
CHO-CH7 and COM Pins

MUXOUT1 and MUXOUT2
Leakage Current
RON

MUX On Resistance
RON Matching Channel to Channel
Channel to Channel Crosstalk

On Channel = 3.3Vand
Off Channel = OV

10

pF

20

pF

-0.3

poA(min)

' 0.01

0.3

p.A(max)

On Channel = 3.3Vand
Off Channel =OV

0.01

0.3

poA(max)

On Channel = OV and
Off Channel = 3.3V

-0.01

-0.3

poA(min)

VMUXOUT = 3.3Vor
VMUXOUT = OV

,0.01

0.3

poA (max)

On Channel = OV and
Off Channel = 3.3V

VIN = 1.65V and
VMUXOUT = 1.55V
VIN = 1.65V and
VMuxour = 1.55V
VIN = 3.3 Vpp; fiN = 40 kHz

MUX Bandwidth

-0.01

,I

.

'

1300

°(max)

·1900
,.

5

,

.

%

-72

dB

90

kHz

,

"

:

,
2-482

DC and Logic Electrical Characteristics
The following specifications apply for V+ = VA + = Vo+ = +3.3 Voc, VREF+ = +2.500 Voc, VREF- = 0 VOC, 12-bit +
sign conversion mode, fCK = fSK = 5 MHz, Rs = 250, source impedance for VREF+ and VREF- ,;; 250, fully-differential input
with fixed 1.250V common-mode voltage, and 10(tcK) acquisition time unless otherwise specified. Boldface limits apply for
TA = T" = TMIN to TMAX; all other limits TA = TJ = 25'C. (Notes 7, 8 and 9)
Symbol

Parameter

Conditions

Typical
(Note 10)

Limits
(Note 11)

Units
(Limits)

CCLK. CSt CONV. 01. PO AND SCLK INPUT CHARACTERISTICS
VIN(1)

Logical "1" Input Voltage

V+ = 3.6V

2.0

V (min)

VIN(O)

Logical "0" Input Voltage

V+ = 3.0V

0.8

V (max)

. IIN(H

Logical "1" Input Current

VIN = 3.3V

0.005

1.0

,..A(max)

IIN(O)

Logical "0" Input Current

VIN = OV

-0.005

-1.0

,..A(min)

2.4
2.9

V (min)
V (min)

DO. EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
VOUT(1)

Logical "1" Output Voltage

I

I

VOUT(O)

Logical "0" Output Voltage

lOUT

TRI-STATE Output Current

V+ = 3.0V, lOUT = -360,..A
V+ = 3.0V, lOUT = - 10,..A
V+ = 3.0V, lOUT = 1.6 rnA
. VOUT = OV
VOUT = 3.3V

-0.1
0.1

0.4

V (max)

-3.0
3.0

,..A(max)
,..A (max)

+Isc

Output Short Circuit Source Current

VOUT = OV

14

8.5

rnA (min)

-Isc

Output Short Circuit Sink Current

VOUT = Vo+

16

8.0

rnA (min)

POWER SUPP!-Y CHARACTERISTICS
10+"

Digital Supply Current

Awake
CS = HIGH, Powered Down, CCLK on
CS = HIGH, Powered Down, CCLK off

1.1
600
12

1.5

rnA (max)
,..A
,..A

IA+

Positive Analog Supply Current

Awake
CS = HIGH, Powered Down, CCLK on
CS = HIGH, Powered Down, CCLK off

2.2
10
0.1

3.0

rnA (max)
,..A
,..A

Awake
CS = HIGH, Powered Down

70
0.1

,
IREF

Reference Input Current

I

2-483

,..A

,..A

AC Electrical Characteristics
The following specifications apply for V+ = VA + "" Vo+ = +3.3 VOC, VREF+ = +2.500 VOC, VREF- = 0 Voc, 12-bit +
sign conversion mode, tr = tf = ,3 ns, fCK = fSK = 5, MHz, Rs = 250, source impedance for VREF + and VREF - ~ 250, fullydifferential input with fixed 1.250V common-mode voltage, and 10(lcK) acquisition time unless otherwise specified. Boldface
limits apply for T A = T J = T MIN to T MAX; all other limits T A ",; TJ = 25°C. (Note 17)
Typical
(Note 10)

Limits
(Note 11)

Units
(Limits)

5

MHz (max)
MHz (min)

5

MHz (max)
Hz (minj

Conversion Clock Duty Cycle

40
80

% (min)
% (max)

Serial Data Clock Duty Cycle

40
80

% (min)
% (max)

Symbol

Parameter

Conditions

fCK

Conversion Clock (CCLK) Frequency

10
1

fSK

Serial Oata Clock SCLK Frequency

10
0

te

tA

Conversion Time

Acquisition Time
(Note 1.9)

I

12-8it + Sign or ,12-8it

44(tCK)

44(tcK>

(max)

8.8

,",s(max)

8-8it + Sign or 8-Bit

21(lcKl

21(tcK)

(max)

4.2

,",s(max)

6 Cycles Programmed

10 Cycles Programmed

18 Cycles Programmed

34 Cycles Programmed

IcAL

tAZ

tsVNC

trn5Fi

tcoNV

"

Self-Calibration Time

6(lcKl

10(lcKl

18(lcKl

34(lcK)

4944(tcKl

Auto-Zero Time

76(tCK)

Self-Calibration or Auto-Zero
Synchronization Time from DOR

2(lcKl

DOR High Time when 'CS is Low
Continuously for Read Data and Software
PowerUp/Down

9(tsKl

~ Valid Data Time

8(tsKl

2-484

8(tcK>
7(tcK)

. (min)
(max)

1.2
1.4

j.t.s(min)
, ,",s(max)

10(tcK)
11(tcK)

(min)
(max)

2.0
2.2

,",s(min) ,
,",s(max)

18(tcK)
19(tcK)

(min)
(max)

3.8
3.8

,",s(min)
,",s(max)

34(tcK)
35(tcK)

(min)
(max)

8.8
7.0

,",s(min)
p.B(max)

4944(tCK)

(max)

988.8

,",s(max)

78(tcK>

(max)

15.2

,",s(max)

2(tCK)
3(tcK>

(min)
(max)

0.40
0.80

,",s(min)
,",s(max)

9(tsK)

(max)

1.8

,",s(max)

8(tsK)

(max)

1.8

,",s(max)

AC Electrical Characteristics (Continued)
The following specifications apply for V+ = VA + = VD+ = +3.3 VDC, VREF+ = +2.500 VDC, VREF-·"" 0 VDC, 12-bit +
sign conversion mode, t, = tf = 3 ns, fCK = fSK = 5 MHz, Rs = 250, source impedance for VREF+ and VREF- s: 250, fullydifferential input with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface
limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25'C. (Note 17)
Symbol.

Parameter

Conditions

Typical
(Note 10)

Limits
(Note 11)

Units
(Limits)

tHPU

Hardware Power-Up Time, Time from
PO Falling Edge to EOC Rising Edge

250

700

p.s(max)

tspu

Software Power-Up Time, Time from
Serial Data Clock Falling Edge to
EOC Rising Edge

500

700

p.s(max)

tACC

Access Time Delay from
CS Falling Edge to DO Data Valid

25

60

ns(max)

tSET-UP

Set-Up Time of CS Falling Edge to
Serial Data Clock Rising Edge

50

ns(min)

tDELAY

Delay from SCLK Falling
Edge to CS Falling Edge

0

5

ns(min)

t1H, tOH

Delay from CS Rising Edge to
DO TRI-STATE®

70

100

ns (max)

tHDI

01 Hold Time from Serial Data
Clock Rising Edge

5

15

ns(min)

tsDI

01 Set-Up Time from Serial Data
Clock Rising Edge

5

10

ns(min)

tHDO

DO Hold Time from Serial Data
Clock Falling Edge

65
5

ns(max)
ns (min)

50

90

ns(max)

RL

RL

=

=

3k, CL

3k,CL

=

=

100 pF

100pF

35

tDDO

Delay from Serial Data Clock
Falling Edge to DO Data Valid

tRDO

DO Rise Time, TRI-STATE to High
DO Rise Time, Low to High

RL

=

3k, CL

=

100 pF

10
10

40
40

ns(max)
ns(max)

tFDO

DO Fall Time, TRI-STATE to Low
DO Fall Time, High to Low

RL

=

3k, CL

=

100 pF

15
15

40
40

ns(max)
ns(max)

tCD

Delay from CS Falling Edge
to DOR Falling Edge

50

80

ns(max)

tSD

Delay from Serial Data Clock Falling
Edge to DOR Rising Edge

45

80

ns(max)

CIN

Capacitance of Logic Inputs

10

pF

COUT

Capacitance of Logie Outputs

20

pF

2-485

CD

CO)

9C'o/

~§

C'o/

o
C

Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate condtlions for which the device Is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test condtllons listed. Some performance characteristics may degrade when the device is not operated under. the listed test
I
conditions.
Note 2: All voltages are measured with respeCt to GND, unless otherwise specHied.
Note 3: When the input voltage (YIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA + or Vo +), the current at that pin should be limited to 20 mA.
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 20 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, 8JA and the ambient temperature, TA.. The maximum
allowable power dissipation at any temperature is Po ~ (TJmax - TAll8JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJmax ~ 150'C. The typical thermal resistance (GlJAl of these parts when board mounted follow:



o
o....

Electrical Characteristics (Continued)

N
0,1111,1111,1111(+4095)
0,1111,1111,1110(+4094)

"

.---r::E

FULL-SCALE
TRANSITION

, ",
"

o
o--"
N

oCo)
N
.......
J>

"
V1N +

> V1N _

0,0000,0000,001 O( +2)
0,0000,0000,000 1( + 1)
f - - - - - - - - - 0,0000,0000,0000(0)

Co)

o
J>

r-

", "
",'

b

.......

_-.-+~c:::==:":'ZE~R~O:"':T~R~A~NS:':IT~IO~N~_ _ _ _ _ _ _ _--j

o

o
....
N

r-

",
",

,"

oCo)

," "

, ",

r.::IVE
FULL-SCALE
TRANSITION

"'J>"

.......
VREF = VREF + - VREF VIN = VIN + - VIN _
GND :S VIN + :S VAt
GND :S VIN _ :S VAt

o

o....

N

b

Co)

CIC)

1,0000,0000,0001 (-4095)
1,0000,0000,0000 (-4096)

ANALOG INPUT VOLTAGE (VIN )
TLlH/11630-7

FIGURE 1a. Transfer Characteristic

+ 12 LSB
POSITIVE
FULL-SCALE
ERROR

NEGATIVE
FULL-SCALE
ERROR

-12 LSB
OUTPUT CODE

(from -4096 to +4095)
TL/H/11630-6

FIGURE 1b. Simplified Error Curve vs Output Code without Auto·Calibration or Auto-Zero Cycles

2·487

Electrical Characteristics (Continued)
+3LSB
POSITIVE
INTEGRAL
LINEARITY,,-

+2 LSB
+1 LSB

-J ________________________ _

T

'NEGATIVE
"'" INTEGRAL
LINEARITY
ERROR

-1 LSB
-2 LSB

__

ERROR

'"

.J

-----------------------

f

-4096
NEGATIVE
FULL-SCALE
ERROR

OFFSET

! ERROR

POSITIVE
FULL-SCALE
ERROR

'@'

'"
.:.
Ill:

0

...

Ill:
Ill:

-3 LSB

OUTPUT CODE
(from -4096 to +4095)
TLlH/II830-9

FIGURE 1c. Simplified Error Curve va OutlJut Code after Auto-Calibration Cycle

+2

+1

§

0
~---------------r--~+-~--------------

~

--T, I-- OFFSET VOLTAGE

o

-1

-2
ANALOG INPUT VOLTAGE (v,N)
TL/H/II830-10

FIGURE 2. Offset or Zero Error Voltage '

2-488

Typical Performance Characteristics

The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. The performance for 8-bit
sign mode is equal to or better than shown. (Note 9)

Linearity Error Change
vs Temperature

Full-Scale Error Change
vs Temperature

...d
:u~
'"
o

-0.05

1-+-+-+--+-+'4...-+--1
'I'

-0.101--1--+-11-+--+-1--1--1

;
:j

1:

-0.15 '--'-....1....J'--'--'-...J_J........J
-60 -40 -20 0 20 40 60 80 100

1.5

r-'-..,,..-::-r~C-~"!""""::::1
VA' - VD' = '3.3V

1.0

.!
I-

05

t-- __J.(VIN + ;

,I

VREr + = +2.S0DV. VREr - = OV

-0.51-

~-+E y~
fC =5t.1Hz

0.101--Prl-1-1-+--+-I--I--I

~u

0.05

d

I-I-+-~"*-+-+-+-t--l

0.00 Ie = 5 MHz t---i".-!-t-+-l
"
VREr - = OV
" ' .......
:: -0.05 Vo,,' = '2.S00V --+-"1"000:+1--1
VAt = Vo+ = +3.3Y
-0.10 (V,N' - V
1--1,N-)
- - 2 - - = '1.2S0V
-0.15 L............:::-_ _ _ _..J........!........I

~
~

-60 -40 -20 0

20 40 60 80 100

TEMPERATURE (Oc)

Full-Scale Error Change
Voltage
0.8 r--r-,--::-r---c-c--...,--,
VB Supply

...
d.

.1

0.4 - VREF +

0.20;;;;;;: POS

i

0.0

~

-0.4 -

~

-0.2

d.~

~ .... NEG

'"

~

. -0.08

....,

i'...

0.00 VA' = Vo'
-0.0"'

VREF+

VREF fe

= OY

- V,N _)

3.1

3.2

_-

3.1

~

3.3

= +1.250Y
3.4

3.5

fC =5MHz

3.0 1--+--+-1--1--+-1-+--1

.. 2.5 1--+--+-1--1--+-1-,:;;.....-1

t

i--"'~

'" 2.0

3.4

3.5

3.6

SUPPLY VOLTAGE (V)

.~

...... ~

f-+,.....
~~F-+-++-+-I
~

I.SL.......J.......J........L..-L~_L.......J......J

-60 -40 -20 0

20 40 60 80 100

TEMPERATURE (Oc)

Digital Supply Current
vs Temperature

1.6 r-~-:""'---""-r-'-""
VAt = Vo. = +3.3V
Ie = SMH,

0~L......~J--L-L~_L......~

-li0 -40 -20 0

20 40 60 80 100

TEMPERATURE (Oc)
TL/H/11830-11

2-489

r-

oc.,)
o
.......

»
c

o-"

I\)

b

c.,)
I\)

»
c

o
......

I\)

b
3.6

3.5 r------,.-...,...-r-,
VA,+ = Vo+ = +3.lV

Ii:

-+--I--t--I
3.3

3.2

Analog Supply Current
vs Temperature

~

-0.12 L -_-_-..:-2::::_-_=_'_'_·2_S_0V_.l...---l
3.0

P-k;;:-

= 25 0C..........

i3

-"''I<:---...,o:-+-t--I

= +2.S00V

= 5MHz

(V,N '

TA

--2--

3.0

!-

TA = 250C~

~

I

SUPPLY VOLTAGE (v)

"-

0.04

~

FULL-SCALE

(VIN + - V1N _)

I\)

.......

-0.6

Zero Error Change
vs Supply Voltage

i

rULL-S:::p~

I

20 40 60 80 100

0.12 r--,.-...,..-.,--,--.-...,
0.08

.1_

VREf - = OV

1 Ie = SMH,

~

TEMPERATURE (OC)

...

1

VA' =VD'

= +2.S00V,

~

~
~

-1.0

-1.5
-60 -40 -20 0

Zero Error Change
vs Temperature
r--,--.-,--,--,--r-.,--,

...

V1N _} = +1.2S0V

~ULL-SCAL~~

.
0.0

TEMPERATURE (oc)

0.15

I,

+

»
c
o......

c.,)

.,:..

.......

»

c
o......

I\)

b

c.,)
Q)

§
....N
o

Test Circuits

c

C")

9N

....
o

f

DO "TRI-5TATE" (tlH. tOH)
TEST POINT

....
'OS'

c(

I·rem;,.

cc(

....

00

I

~.w.;-

,."

C")

9N

2.2k
A.OC12L038 DO ......--4~...~•
10110107000
or Equi.alent

G.

'-

N

DO except "TRI-5TATE"
3.3V
TEST POINT

TLlH/11830-15

....
o

cc(

TLlHI11830-16

....

Leakage Current

C)

9

+3.3V

....

N

ADC12L038

o
~

·• .

.....- - f CH2(orr)
CH7(Orr)
TLlH/11830-17

Timing Diagrams
DO Failing and Rising Edge

DO "TRI·STATE" Failing and RIsing Edge

'Roo

\00
DO

DO

1.2V -TRI-STATE

TL/H/11630-18
TLlHI11830-19

01 Data Input nmlng

SCLKLJUU~
IoELAY....j

t sETuP

TLlH/11830-ZO

2·490

Timing Diagrams (Continued)
DO Data Output Timing Using C!
2

4

TLlH/11830-21

DO Data Output Timing with C!i Continuously Low

o

2

3

4

SClK
'sET-UP

cs
tACC
DO

'cD
DOR

[DC
TLlHI11830-22

ADC12L038 Auto Calor Auto Zero

FII

DOR -,~__________________~~

11--;

EOC

r

~11------·

Tl/H/11830-23

Note: DO output data Is not valid during this cycle.

2-491

Timing Diagrams (Continued)
ADC12L038 Read Data without Starting a Conversion Using CS
CCLK

SCLK

01

~~~-------------------------

OBI A-__
DB2 ~___&__~__~~~ OBO
L--JL-__

DO

EOC

-------------------------------1\'1-1---------------------------------TL/H/11830-24

ADC12L038 Read Data without Sta~tlng ~ Conversion with CS Continuously Low

1..I1.rLrlrLrLrln

CCLK

~I--I----

SCLK

cs
CONY

-.
01'

DOR

~D-B-0~-DB-'-.A-'D-B-2~---&--~~~~~~------~I__D-B-O------~--~---­
________________________~§~----~1---JL----

EOC

------------------------------~§II------------~§lI------------------

DO __

TUHI11830-25

2-492

»
c

Timing Diagrams (Continued)

o
......
~

r

oc.,)
o
......

ADC12L038 Conversion Using CS with 8·81t Digital Output Format

»

c
o......
~

r

oc.,)
~

......
»
c

o......
~

b

c.,)

"'"
»

......

c

o
......
~

b

~------------~~

c.,)

CD

r

ll-u·

~Sr----"""'·

TL/H/11830-26

ADC12L038 Conversion Using CS with 16·8it Digital Output Format

CCLK

SCLK

til

CS

DI

DO

DOR

1J--j

EOC

r

'-----lSj-------I·

TL1H/11830-27

2·493

m ,--------------------------------------------------------------------------,

CI)

9C'II

Timing Diagrams (Continued)

..-

g

ADC12L038 Conversion with CS Continuously Low and 8·Blt Digital Output Format

:!
""II'

9

CCLK

C'II

8~

SCLK

C'II

9
C'II

..-

g
c

g
9C'II

..-

011

.01

00

o
c
<

EOC

OBD

012

013

Dl4

DIS

OB2

OB3

OB4

OBS

OB6

OBD

OB7

----------------~~IS--;

r

~S_S----.I.

TL/H/11830-28

ADC12L038 Conversion with CS Continuously Low and 16·Bit Digital Output Format

CCLK

SCLK

01

DO

..

~ ~~~--D_~~I~---------- ~

--------------------~~~--~~----~
IS-;

EOC

r

~S_S---....·

TUH/11830-29

2-494

.--------------------------------------------------------------------,~

CJ

o....

Timing Diagrams (Continued)

a
I\)

ADC12L038 Software Power Up/Down Using CS with 16-8it Digital Output Format

~CJ
o....

CCLK

I\)

b

Co)
I\)

SCLK

;;
CJ
o
....
I\)

b
.0.
.....
Co)

~

CJ

o
....
I\)

~

DO

p~::~
EOC

XXXXXXXXXXXXXXX)(]

Power

________________________________~II~----~r--

Up

EOC
TLlH/11830-30

ADC12L038 Software Power Up/Down with CS Continuously Low and 16-81t Digital Output Format

lspu

CCLK

SCLK

01

DO

_____J~~R_n_~~~~-B~-J~~R-n-~~~~--~~~--------~~OO-O­

~~p---------~---

p~::~
EOC

XXXXXXXXXXXXXXX)(]

Power

_____________________________~II-----I~I______~r__

Up

II-----IS----~-

EOC
TL/H/11830-31

2-495

,.

§
N
....

I
....

Timing Diagrams (Continued)
ADC12L038 Hardware Power Up/Down

PO

N

~

§

N
....

I
9N

______

~------------------~:~--------------~r=---,..~r-~-:u--------_+----

CCLK

SCLK

EDC

xxxx>4
TlIH/11830-32

Nole: Hardware power up/down may occur at any time. II PO is high while a conversion is in progress thaI conversion will be corrupted and erroneous data will be
stoned In the output shift reglstar.

....

~

ADC12L038 Configuration Modification-Example of a Status Read
'Cycle N
Cycle N+ 1
Program Read status ~--_...- - - - - - - - Start a Conyerslon - - - - - - -....
DO Data from Cycle N-l
DO Sialus Dala
8-bil plus Sign Conyers ion

~
CCLK,
SCLK

CS

CONY
01

010 DII

Dl2

Dl3

DI4

015

DIS

017

I I I

DO

D

N-l Data

DB1 002 DB3 DB.. DDS OBI DB7

OBI

Stalus Data

iiiii

I~l

EOC

r
Tl/HI11830-33

~ In order for all 9 bits of status inlonnation to be accessible Ihe last conversion programmed before Cycle N needs to haye a resolution of 8 bits plus sign,
12 bits, 12 bits plus sign, or grealer.

2-496

Pin Descriptions
CCLK

SCLK

DI

DO

EOC

CS

maturely ended. The data in the output latches
may be corrupted. Therefore, when CS is
brought back low during a conversion in progress the data output at that time should be ignored .. CS may also be left continuously low. In
this case it is imperative that the correct number
of SCLK pulses be applied to the ADC in order
to remain synchronous. After the ADC supply
power is applied, it expects' to see 13 clock
pulses for each I/O sequellce. The number of
clock pulses the ADC expects is the same as
the digital output word length. This word length
can be modified by the data shifted in on the
DO pin. Table V details the data required.
DaR
This is the data output ready pin. This pin is an
active push/pull output. It is low when the conversion result is being shifted out and goes high
to signal that all the data has been shifted out.
CONV
A logic low is required on this pin to program
any mode or change the ADC's configuration as
listed in the Mode Programming Table (Table V)
such as 12-bit conversion, B-bit conversion,
Auto Cal, Auto Zero etc. When this pin is high
the ADC is placed in the read data only mode.
While in the read data only mode, bringing CS
low and pulsing SCLK will only clock out on DO
any data stored in the ADCs output shift register. The data on DI will be neglected. A new
conversion will not be started and the ADC will
remain in the mode and/or configuration previously programmed. Read data only cannot be
performed while a conversion, Auto-Calor
Auto-Zero are in progress.
PD
This is the power down pin. When PD is high
the AID is powered down; when PD is low the
A/D is powered up. The A/D takes a maximum
of 700 !JoS to power up after the command is
given.
CHO-CH7 These are the analog inputs of the MUX. A
channel input is selected by the address information at the DI pin, which is loaded on the
rising edge of SCLK into the address register
(see Tables II through IV).
The voltage applied to these inputs should not
exceed VA + or go below GND. Exceeding this
range on an unselected channel will corrupt the
reading of a selected channel.
COM
This pin is another analog input pin. It is used as
a pseudo ground when the analog multiplexer is
single-ended.
MUXOUT1, These are the multiplexer output pins.
MUXOUT2
These are the converter input pins. MUXOUT1
AlDIN1,
is usually tied to AlDIN1. MUXQUT2 is usually
A/DIN2
tied to AlDIN2. If external circuitry is placed between MUXOUT1 and AlDIN1, or MUXOUT2
and AlDIN2 it may be necessary to protect
these.pins. The voltage at these pins should not
exceed VA + or go below AGND (see Figure :1).

The clock applied to this input controls the sucessive approximation conversion time interval
and the acquisition time. The rise and fall times
of the clock edges should not exceed 1 !Jos.
This is the serial data clock input. The clock
applied to this input controls the rate at which
the serial data exchange occurs. The rising
edge loads the information on the DI pin into
the multiplexer address and mode select shift
register. This address controls which channel of
the analog input multiplexer (MUX) is selected
and the mode of operation for the AID. With CS
low the falling edge of SCLK shifts the data resulting from the previous ADC conversion out
on DO, with the exception of the first bit of data.
When CS is low continuously, the first bit of the
data is clocked out on the rising edge of EOC
(end of conversion). When CS is toggled the
falling edge of CS always clocks out the first bit
of data. CS should be brought low when SCLK
is low. The rise and fall times of the clock edges
should not exc,eed 1 !Jos.
This is the serial data input pin. The data applied to this pin is shifted by the rising edge of
SCLK into the multiplexer address and mode
select register. Tables II through V show the assignment of the multiplexer address and the
mode select data.
The data output pin. This pin is an active push/
pull output when CS is Low. When CS is High
this output is in TRI-STATE. The AID conversion result (DO-D12) and converter status data
are clocked out by the falling edge of SCLK on
this pin. The word length and format of this result can vary (see Table I). The word length and
format are controlled by the data shifted into
the multiplexer address and mode select register (see Table V).
This pin is an active push/pull output and indicates the status of the ADC12L030/2/4/B.
When low, it Signals that the AID is busy with a
conversion, auto-calibration, auto-zero or power
down cycle. The rising edge of EOC signals the
end of one of these cycles.
This is the chip select pin. When a logic low is
applied to this pin, the rising edge of SCLK
shifts the data on DI into the address register.
This low also brings DO out of TRI-STATE. With
CS low the falling edge of SCLK shifts the data
resulting from the previous ADC conversion out
on DO, with the exception of the first bit of data.
When CS is low continuously, the first bit of the
data is clocked out on the rising edge of EOt
(end of conversion). When CS is toggled the
falling edge of CS always clocks out the first bit
of data. CS should be brought low when SCLK
is low. The falling edge of CS resets a conversion in progress and starts the sequence for a
new conversion. When CS is brought back low
during a conversion, that conversion is pre-

2-497

»
c
o....
I\)

r-

Q

w

~

g
..:.
I\)

r-

Q

~
»
c

o
....
I\)

r-

Q

w

~
C
o....
I\)

r-

Q

w

co

Pin Descriptions (Continued)
VREF+

VA + • Vo + These are the analog and digital power supply
pins. VA + and Vo + are not connected together

This Is the positive analog voltage reference In·
put. In order to maintain accuracy the voltage
range of VREF (VREF = VREF+ - VREF-) is
1 Voc to 3.3 Voc and the voltage at VREF+
cannot exceed VA +. See Figure 4 for recom·
mended bypassing.
The negative voltage reference input. In order
to maintain accuracy the voltage at this pin
must not go below GND or exceed VA +. (See
Figure 4).
'

on the chip. These pins should be tied to the
same power supply and bypassed separately
(see Figure 4). The operating voltage range of
VA + and Vo + is 3.0 VOC to 5.5 VOC.
DGND

This is the digital ground pin (see Figure 4).

AGND

This is the analog ground pin (see Figure 4 ).

lN914
From
external >-.4J\Itr-+--"M,.....~ To ADC pin
250.(1
. ~ircuitry
IN914

TLlH/11830-34

FIGURE 3. Protecting the MUXOUT1, MUXOUT2, AlDIN1 and A/DIN2 Analog Pins

V+
Analog
Input
Voltage

Assigned
(+) INPUT

+3.3V

Vo +

Analog
Input
Voltage

I I I

ADC
Assigned
(-) INPUT

+2.S00V

VREF +

I I'I
VREF -

DGND

Analog
Input
Voltage

AGND

> ___________ ....--------1
~

Ground
Reference
TLlH/1183D-35

'Tantalum
··Monolithic Ceramic or better

FIGURE 4. Recommended Power Supply Bypassing and Grounding

2·498

Tables
TABLE I. Data Out Formats
DO Formats

DBO DB1 DB2 DB3 DB4 DB5 DB6 DB7 DBB DB9 DB10 DB11 DB12 DB13 DB14 OB15 DB16

17
Bits

X

X

MSB 13
Sign MSB
First Bits

9
Bits

with
Sign

10

9

8

7

6

5

4

7

6

5

4

3

2

1

LSB

4

'3

2

1

LSB

Sign MSB

X

X

10

9

8

6

5

Sign MSB

3

2

1

LSB

X

X

X

X

17
LSB
Bits

1

2

3

4

5

6

7

8

9

10

MSB

Sign

LSB 13
LSB
First Bits

1

2

3

4

5

6

7

8

9

10

MSB

Sign

LSB

1

2

3

4

5

6

0

0

0

0

MSB

10

9

8

7

6

5

4

3

2

1

LSB

10

9

8

7

6

5

4

3

2

1

LSB

MSB

6

5

4

3

2

1

LSB

16
LSB
Bits

1

2

3

4

5

6

7

8

9

10

MSB

0

0

0

0

LSB 12
LSB
First Bits

1

2

3

4

5

6

7

8

9

10

MSB

1

2

3

4

5

6

MSB

9
Bits
16
Bits

MSB 12
MSB
First Bits

8
Bits

without
Sign·

8
Bits

LSB

MSB Sign

x = High or Low state.
TABLE II. ADC12L03B Multiplexer Addressing
Analog Channel Addressed
and Assignment
with AlDIN1 tied to MUXOUT1
and AlDIN2 tied to MUXOUT2

MUX
Address

AID Input
Polarity
Assignment

Multiplexer
Output
Channel
Assignment

Mode

DIO DI1 DI2 DI3 CHO CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM AlOIN1 A/DIN2 MUXOUT1 MUXOUT2
L
L
L
L
L
L
L
L

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

+

H
H
H
H
H
H
H
H

L
L
L
L
H

L
L
H
H
L
L

L
H
L

+

H
H
H

H
H

-

+

-

+

-

+

+

-

+

-

+

H
L
H

-

+
-

-

+
+

-

+

H
'L

-

+
+
+
+

-

+

-

+
+
+
2·499

-

-

-

-

+
+
+
+

+
+
+
+
+
+
+
+

-

-

CHO
CH2
CH4
CH6
CHO
CH2
CH4
CH6

CH1
CH3
CH5
CH7
CH1
CH3
CH5
CH7

Differential

CHO
CH2
CH4
CH6
CH1
CH3
CH5
CH7

COM
COM
COM
COM
COM
COM
COM
COM

Single-Ended

Tables (Continued)
TABLE III. ADC12L034 Multiplexer Addressing
, Analo!l Chann,el Addressed
and Assignment
with AlDIN1 tied to MUXOUT1
and AlDIN2 tied to MUXOUT2

"
"

'

MUX
Address

DIO

DI1

DI2

CHO

'CH1

L
L
L
L

L
L
H
H

L
H
L
H

+

-

H
H
,H
H

L

L

+

L
H
H

H

,

CH2

-

+

A/DIN2

MUXOUT1

MUXOUT2

-

+
+

-

+

CH1'
CH3
CH1
CH3

Differential

-

CHO
CH2
CHO
CH2

COM
COM
COM
COM

Single-Ended

-

CHO
,CH2
CH1
CH3

Multl~lexer

Addressing

COM

-

+

-

+

H

, TABLE IV. ADC12L032 and ADC12L030
Analog Channel Addressed
and Assignment
' with A/DIN1 tied to MUXOUT1
and A/DIN2 tied to MUXOUT2

MUX
Address
DI1 '

CHO

,'CH1

L
L.

L

-+

-

H

'-

+

H
H

L
H

+

DIO

-

-

Multiplexer
Output
Channel
,Assignment

AID Input
'Polarity
Assignment

COM

-

+

+
+

+
+
:1+

-

+

L

-

-

,-

Mode

A/DIN1

CH3

+

Multiplexer
Output
Channel
Assignment

, 'AiD Input
Polarity
Assignment

-

Mode

A/DIN1

.AlDIN2

MUXOUT1

MUXOUT.2

+

,,-

CHO
CHO

CH1
CH1

Differential

CHO
CH1

COM
COM

Single-Ended

-

+

+
+

-

Note: ADC12L030 does not have AlDIN1, AlDIN2, MUXOUT1 and MUXOUT2 pins,
"

"

'"

"

,
"

"

,

,

'

'

,

..
..

,

,

.. "
",

,

'

,
":

,

,

,

~

C

Tables (Continued)

o....
N

TABLE V. Mode Programming
AOC12L038

010

011

012

AOC12L034

010

011

012

AOC12L030
and
AOC12L032

010

011

013

014

015

016

017

013

014

015

016

012

013

014

015

t;;

Mode Selected
(Current)

00 Format
(next Conversion
Cycle)

See Tables 11,111 or IV

L

L

L

L

12 Bit Conversion

12 or 13 Bit MSB First

See Tables II, III or IV

L

L

L

H

12 Bit Conversion

16 or 17 Bit MSB First

See Tables II, III or IV

L

L

H

L

8 Bit Conversion

8 or 9 Bit MSB First

L

L

H

H

12 Bit Conversion of Full~Scale

12 or 13 Bit MSB First

See Tables II, III or IV

L

H

L

L

12 Bit Conversion

12 or 13 Bit LSB First

See Tables II, III or IV

L

H

L

H

12 Bit Conversion

16 or 17 Bit LSB First

See Tables II, III or IV

L

H

H

L

8 Bit Conversion

8 or 9 Bit LSB First

L

L

H

H

H

12 Bit Conversion of Offset

12 or 13 Bit LSB First

~

g....
N

b
w

~
C

o

....
N

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

Auto Cal

No Change

L

L

L

L

H

L

L

H

Auto Zero

No Change

L,

L

L

L

H

L

H

L

Power Up

No Change

L

L

L

L

H

L

H

H

Power Down

No Change

L

L

L

L

H

H

L

L

Read Status Register

No Change

L

L

L

L

H

H

L

H

Data Out without Sign

No Change

H

L

L

L

H

H

L

H

Data Out with Sign

No Change

L

L

L

L

H

H

H

L

Acquisition Time-6 CCLK Cycles

No Change

L

H

L

L

H

H

H

L

Acquisition Time-1 0 CCLK Cycles

No Change

H

L

L

L

H

H

H

L

Acquisition TIme-18 CCLK Cycles

No Change

H

H

L

L

H

H

H

L

Acquisition Time-34 CCLK Cycles

No Change

L

L

L

L

H

H

H

H

User Mode

No Change

H

Test Mode
(CH1-CH7 become Active Outputs)

No Change

H

X

X

X

H

H

H

Note: The AID powers upwHh no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12·bit + sign conversion, power up, 12· or 13·bit MSB first and user mode.
X

= Oon't Care
TABLE VI. Conversion/Read Oata Only Mode Programming
CS

CONV

PO

Mode

L

L

L

See Table V for Mode

L

H

L

Read Only (Previous DO Format)
No Conversion

H

X

L

Idle

X

X

H

Power Down

x = Don't Care

2-501

b
w

~

o
....
N

b
w

CD

CD
CI)

....
.....
8

,0

Tables (Continued)

N

TABLE VII. Status Register

~

CI)

9N

Status Bit
Location

DBO

DB1

DB2

DB3

DB4

Status Bit

PU

PD

Cal

Bor9

12 or 13

'Function

"High"
indicates
ilPower
Up
Sequence
isin'
' progress

"High"
indicates
an AutoCal
Sequence
isin
progress

"High"
indicates
an80r9
bit format

"High"
indicates
a 120r
13 bit
format

Device Status

....

Co)
'

5!
....
N

S
....
....
N

~

'.

"High"
indicates
a power
Down
Sequence
isin
progres~

DB5 ,

DB6

DB7

DBB

16 or 17

Sign

Justification

Test Mode

DO Output Format Status
"High"
indicates
a 160r
17 bit
format

"Low"
the sign
bit is not
included.

"

9....

"High"
indicates
that the
sign bit is
included.
'
When

When "High" . When
"High" the
the
conversion
device is in
result will be
test mode.
outputMSB
When
first. When
"Low" the
·"Low"the
device is in
result will be
user mode.
outputLSB
first.

Application Hints

N

,

o

, 1.0 DIGITAL INTERFACE

C

o
N

b
w

L

H

L

L

H

L

X

X

ADC12L032

L

H

L

L

H

L

X

X

ADC12L034

L

H

L

L

L

H

L

X

o

ADC12L038

L

H

L

L

L

L

H

L

N

1.6 User Mode and Test Mode

2-503

o

N

ADC12L030

An instruction may be issued to the ADC to put it into test
mode. Test mode is used by the manufacturer to verify complete functionality of the device. During test mode CHOCH7 become active outputs. If the device is inadvertently
put into the test mode with CS low continuously, the serial
communications may be desynchronized. Synchronization
may be regained by cycling the power supply voltage to the
device. Cycling the power supply voltage will also set the
device into user mode. If CS is used in the serial interface,
the ADC may be queried to see what mode it is in. This is
done by issuing a "read STATUS register" jnstruction to the
ADC. When bit 9 of the status register is hfgh the ADC is in
test mode; when bit 9 is low the ADC is in user mode. As an
alternative to cycling the power supply, an instruction sequence may be used to return the device to user mode. This
instruction sequence must be issued to the ADC using CS.

The number of clock pulses required for an I/O exchange
may be different for the case when CS is left low continuously vs. the case when CS is cycled. Take the I/O sequence detailed in Figure 5· (Typical Power Supply Sequence) as an example. The table below lists the number of
SCLK pulses required for each instruction:

o

i>
c

~

The ADC may be powered down at any time by taking the
PD pin HIGH or by the instruction input on DI (see Tables V
and VI, and the Power Up/Down timing diagrams). When
the ADC is powered down in this way the circuitry necessary
for an AID conversion is deactivated. The circuitry necessary for digital I/O is kept active. Hardware power up/down
is controlled by the state of the PD pin. Software power up/
down is controlled by the instruction issued to the ADC. If a
software power up instruction is issued to the ADC while a
hardware power down is in effect (PO pin high) the device
will remain in the power-down state. If a software power
down instruction is issued to the ADC while a hardware
power up is in effect (PD pin low), the device will power
down. When the device is powered down by software, it
may be powered up by either issuing a software power up
instruction or by taking PO pin high and then low. If the
power down command is issued during an A/D conversion,
that conversion is disrupted. Therefore, the data output after
power up cannot be relied on.

If erroneous SCLK pulses desynchronize the communications, the simplest way to recover is by cycling the power
supply to the device. Not being able to easily resynchronize
the device is a shortcoming of leaving CS low continuously.

b
w

o

DI2 DI3 DI4 DI5 DI6 DI7

1_5 Power Up/Down

8

SIGN ON

DI Data
DIO Dll

Where X can be a logic high (H) or low (L).

Number of
SCLKs
Expected

DO Format

N

~
o
~

b
w

c»

co

9
...
C\I

o
c

~
"'II'

9
...

r-----------------------------------------------------------------------~--------,

Application Hints (Continued)
The following table lists the instructions required to return
the device to user mode:

4 Differential
Channels
+(-)
-(+)

Di Data

,Instruction

DID 011 012 013 014 015 016 017

C\I

TEST MODE

H

X

X

X

H

H

H

H

RESET

L

L

L

L

H

H

H

L

i...

+(-)
-(+)

TEST MODE

L

L

L

L

H

L

H

L

, INSTRUCTIONS

L

L

L

L

H

L

H

H

+(-)
-(+)

C\I

USER MODE

L

L

L

L

H

H

H

H

o

Power Up

L'

L

L

L

H

L

H

L

Set DO with
or without
Sign

H
or
L

L

L

L

H

H

L

H

Set
Acquisition
Time

H
or
L

H
or
L

L

L

H

H

H

L

Start
a
Conversion

H
or
L

H
or
L

H
or
L

H
or
L

L

H
or
L

H
or
L

H
or
L

~
9...
o
C\I

~

+
+
+
+
+
+
+
+

+(-)
-(+)

o
c

S Single-Ended Channels
with COM
as Zero Reference

TL/H/11830-38
TUH/11830-39

FIGURE 7
CHO, CH2, CH4, and CH6 can be aSSigned to the MUXOUTl pin in the differential configuration, while CH1, CH3,
CH5, and CH7 can be aSSigned to the MUXOUT2 pin. In the
differential configuration, the analog inputs are paired as follows: CHO with CH1, CH2 with CH3, CH4 with CH5 and CH6
with CH7. The AlDINland AlDIN2 pins can be assigned
positive or negative polarity.
With the single-ended multiplexer configuration CHO
through CH7 can be aSSigned to the MUXOUn pin. The
COM pin is always assigned to the MUXOUT2 pin. AlDINl
is assigned as the positive input; AlDIN2 is aSSigned as the
negative input. (See Figure 8).

x = Don't Carli
After returning to user mode with the user mode instruction
the power up, data with or without sign, and acquisition time
instructions need to be resent to ensure that the ADC is in
the required state before a conversion is started.

Differential
Configuration
CHO
CH2
CH4
CH6

1.7 Reading the Data Without Starting a Conversion
The data from a particular conversion may be accessed
without starting a new conversion by ensuring that the
~ line is taken high during the I/O sequence. See the
Read Data timing diagrams. Table VI describes the operation of the CONY pin.

CHI
CH3
CH5
CH7

Single-Ended
Configuration

1

-I-

... 1

.... I'-

1

M

M

OUlI

OUT2

CHO
CHI
CH2
CH3
CH4
CH5
CH6
CH7

...
....

COM
TL/H/11830-40

AlDIN1 and AlDIN2 can be assigned as the + or - input

);Ux OUlI

...tc

2.0 DESCRIPTION OF THE ANALOG MULTIPLEXER
For the ADC12L038, the analog input multiplexer can be
configured with 4 differential. channels or 8 single ended
channels with the COM input as the zero reference or any
combination thereof (see Figure 7). The difference between
the voltages on the VREF+ and VREF- pins determines the
input voltage span (VREF). The analog input voltage range is
oto VA +. Negative digital output codes result when VIN- >
VIN + ~ The actual voltage at VIN - or VIN + cannot go below
AGND.

~

MUX OUT2
TL/H/11830-41

AlDIN1 is + input
AlDIN2 is - input

FIGURES
The Multiplexer aSSignment tables for the ADC12L030,2,4,8
(Tables II, III, and IV) summarize the aforementioned functions for the different versions of AIDs.
2.1 Blasing for Various Multiplexer Configurations
Figure 9 is an example of biasing the device for singh~-end­
ed operation. The sign bit is always low. The digital output
range is 0000000000000 to 01111 1111 1111. 'One LSB
is equal to 610 jJ-V (2.5V/4096 LSBs).

2-504

r--------------------------------------------------------------------.~

C

Application Hints (Continued)

o
....
~

ANALOG
INPUT
VOLTAGE
RANGE
OV TO 2.SV

CHO
CHI
CH2

Av
ASSIGNED
(+) INPUT

b
w
Q
.....

+3.3V

~

c
o....

to
CH7

~

12 BITS UNSIGNED
ASSIGNED
(-) INPUT

b
w

ADC12L03Y

"""':";"'--1

COM

~
......

VREF + 1-.....~-:-":'1I_:_~~~_:_--+-O +2.SV

~

c
o....
~

b
w
,a:o.
.....

LM9140BYZ-2.5
OGND

AGND

~

C

ANALOG
INPUT
VOLTAGE
GROUND
REFERENCE

o....
~

>-_...-----;....-~.,......-...J

b
w

CD

TUH/11830-46

FIGURE 9. Single-Ended Biasing
For pseudo-differential signed operation the biasing circuit
5 MHz CCLK frequency) would allow the 6000 to increase
shown in Figure 10 shows a signal AC coupled to the ADC.
to E?k, which with a 1 /LF coupling capacitor would set the
high pass corner at 26 Hz. The value of R1 will depend on
This gives a digital output range of -4096 to +4095. With a
1.25V reference, as shown, 1 LSB is equal to 305 /LV. AIthe value of R2.
though the ADC is not production tested with a 1.25V referAn alternative method for biasing pseudo-differential operaence linearity error typically will not change more than 0.3
tion is to use the + 2.5V from !he LM9140 to bias any ampliLSB. With the ADC set to an acquisition time of 10 clock·
fier circuits driving the ADC as shown in Figure 11. The
periods the input biasing resistor needs to be 6000 or less.
value of the resistor pull-up biasing the LM9140-2.5 will deNotice though that the input coupling capacitor needs to be
pend upon the current required by the op amp biasing cirmade fairly large to bring down the high pass corl)er. In'
cuitry.
creasing the acquisition time to 34 clock periods (with a
Fully differential operation is shown in Figure 12. One LSB
for this case is equal to (2.5V/4096) = 610 mV.

ANALOG
INPUT
VOLTAGE
RANGE
OV TO 2.SV

VAt

>-I

Av
ASSIGNED
(+) INPUT

12 BITS SIGNED

R2
600n
(DEPENDS ON
ACQUISITION
TIME)

ASSIGNED
(-) INPUT

CHO
CHI
CH2

to
CHB

+3.3V
Vo+

ADC12L03Y
COM

VREF + I-......,.......,......~~-.....-....,.......-

....-o

+1.2SV

LM4041 AIZ-l.25
OGND

AGND

ANALOG
INPUT
VOLTAGE >--f-------~-GROUND
REFERENCE

.....
TLlH/11830-47

FIGURE 10. Pnuda-Dlfferentlal Bla81ng with the Signal Source AC Coupled Directly Into the ADC

2~505

mr-------------------------------------------------------------------~

§

...
N

Application Hints (Continued)
ANALOG
INPUT
VOLTAGE
RANGE
OV TO 2.5V

..§~

...
g
N

~

VA+

12 BITS SIGNED

ANALOG
INPUT
VOLTAGE

/'v (+)ASSIGNED
INPUT

~

~

ASSIGNED
INPUT

H

9N

...
g

CHO
CHI
CH2

~..------....+3.3V

to

Vo+

CH8

AOt12L03Y
VREF +

COlli

.......--...--.. . --4-....

--0 +1.25V

cc

...~

Lt,44041 AIZ-1.2

N

§

ANALOG
INPUT
VOLTAGE >-~I-------~---I
GROUND
REFERENCE
TUH/11830-48

FIGURE 11. Altematlve Pseudo-Differential Biasing

ANALOG
A. .
CHO
INPUT
• ~
CH2
VOLTAGE >-~~~ CH4
RANGE
ASSIGNED
or
O.4V TO 2.9V
(+) INPUT CH6

VO+

t-....- -....- -.....-..J
lk

AOC12L03Y

FULLY DIFFERENTIAL
12 - BIT PLUS SIGN

ANALOG
INPUT
VOLTAGE
RANGE
O.4V TO 2.9V

.....-O+3.3V

vA
ASSIGNED
INPUT

H

CHI
CH3
CH5

VREF +

.......~~...- -.....- - -....--o +2.5V

or
CH7
VREF -

Lt,49140BYZ-2.5

ANALOG
INPUT
VOLTAGE >-----1I~--I
GROUND
REFERENCE
TL/H/11830-50

FIGURE 12. Fully Differential BlaBlng
3.0 REFERENCE VOLTAGE
The difference in the voltages applied to the VREF+ and
VREF- defines the analog Input span (the difference between the voflage applied between two multiplexer inputs or
the voltage applied to one of the multiplexer Inputs and analog ground), over which 4095 positive and 4096 negative
codes exist. The voltage sources driving VREF+ or VREFmust have very low output Impedance and noise.

The ADC12L030/2/4/8 can be used in either ratiometric or
absolute reference applications. In ratiometric systems, the
analog input voltage is proportional to the voltage used for
the ADC's reference voltage. When this voltage is the system power supply, the VREF + pin is connected to VA + and
VREF-is connected to ground. This technique relaxes the

2-606

Application Hints (Continued)
system reference stability requirements because the analog
input voltage and the ADC reference voltage move together. This maintains the same output code for given input conditions. For absolute accuracy, where the analog input voltage varies between very specific voltage limits, a time and
temperature stable voltage source can be connected to the
reference inputs. Typically, the reference voltage's magnitude will require an initial adjustment to null reference voltage induced full-scale errors.

4.0 ANALOG INPUT VOLTAGE RANGE
The ADC12L030/2/4/B's fully differential ADC generate a
two's complement output that is found by using the equations shown below:
for (12-bit) resolution the Output Code =
(VIN+ - VIN-) (4096)
(VREF+ - VREF )
for (B-bit) resolution the Output Code =

Below are recommended references along with some key
specifications.

Part Number

Output
Voltage
Tolerance

Temperature
Coefficient
(max)

LM4041CIM3-AdJ

±0.5%

±100ppm/oC

LM4040AIM3·2.S

±0.1%

±100ppm/oC

LM9140BVZ·2.S

±0.5%

±25ppml"C

LM368Y·2.S

±0.1%

±20ppm/oC

(VIN+ - VIN-) (256)
(VREF+ - VREF-)
Round off to the nearest integer value between -4096 to
4095 for 12-bit resolution and between - 256 to 255 for Bbit resolution if the result of the above equation is not a
whole number.
Examples are shown in the table below:

The reference voltage inputs are not fully differential. The
ADC12L030/2/41B will not generate correct conversions or
comparisons if VREF+ is taken below VREF-. Correct conversions result when VREF+ and VREF- differ by 1V and
remain, at all times, between ground and VA +. The VREF
common mode range, {VREF+ + VREF-)/2, is restricted to
{0.1 x VA+) to (0.6 x VA+). Therefore, with VA+ = 3.3V
the center of the reference ladder should not go below
0.33V or above 1.9BV. Figure 13 is a graphic representation
of the voltage restrictions on VREF+ and VREF-.

VREF+

VREF-

VIN+

VIN-

Digital
Output
Code

+2.5V

+1V

+1.5V

OV

0,1111,1111,1111

+2.500V

oli

+2V

OV

0,1100,1100,1101

+2.500V

OV.

+2.500V

OV

+2.499V +2.500V 1,1111,1111,1111
OV

+2.500V 1,0000,0000,0000

5.0 INPUT CURRENT
At the start of the acquisition window {tAl a charging current
flows into or out of the analog input pins (AlDIN1 and
AlDIN2) depending on the input voltage polarity. The analog input pins are CHO-CH7 and COM when AlDIN1 is tied
to MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak
value of this input current will depend on the actual input
voltage applied, the source impedance and the internal multiplexer switch on resistance. With MUXOUT1 tied to
AlDIN1 and MUXOUT2 tied to AlDIN2 the internal multiplexer switch on resistance is typically 1.6 kO. The AlDIN1
and AlDIN2 mux on resistance is typically 7500.

is:

6.0 INPUT SOURCE RESISTANCE

.:. 0.1 VA+· O.5V

For low impedance voltage sources «6000), the input
charging current will decay, before the end of the S/H's
acquisition time of 2).Ls (10 CCLK periods with fe = 5 MHz),
to a value that will not introduce any conversion errors. For
high source impedances, the S/H's acquisition time can be
increased to 1B or 34 CCLK periods. For less ADC resolution and/or slower CCLK frequencies the S/H's acquisition
time may be decreased to 6 CCLK periods. To determine
the number of clock periods {Nol required for the acquisition
time with a specific source impedance for the various resolutions the following equations can be used:

>'IJ.

TL/H/11830-43

12 Bit + Sign Ne =

FIGURE 13. VREF Operating Range

8 Bit +

IRs +

2.31 x fe x 0.824

Sign Ne = [Rs + 2.31 x fe x 0.57
Where fe is the conversion clock (CCLK) frequency in MHz
and Rs is the external source resistance in kO. As an exam-

2·507

I
9N

...-

I
N
...-

~
N

§
N
...-

~~
9

N
...o
cc(

Application Hints (Continued)
pie, operating with a resolution of 12 Bits+sign, a 5 MHz
clock frequency and maximum acquistlon, time oj 34 conversion clock periods the AOC's analog inputs can handle a
source impedance as high as 6 kO. The acquisition time
may also be extended to compensate for the settling or
response time of external circuitry connected between the
'
MUXOUT and AlDIN pins.

minimum power supply bypassing capacitors recommended
are low inductance tantalum capacitors of 10 /tF or greater
paralleled with 0.1 /tF monolithic ceramic capacitors. More
or different bypassing may be necessary depending on the
overall system reqUirements. Separate bypass capacitors
should be used for the VA + and Vo + supplies and placed
as close as possible to these pins. .
.

The acquisition time (tAl is started by a fallirig edge of SCLK
and ended by a rising edge of CCLK (see Timing Diagrams).
If SCLK and CCLK are asynchronous one extra CCLK clock
period may be inserted into the programmed acquisition
time for synchronization. Therefore With asriychronous
SCLK and CCLK the acquisition time will change from conversion to conversion.
'.

10_0 GROUNDING
The ADC12L030/2/4/S's performance can be maximized
through proper grounding techniques. These. 'include the
use of separate analog and digital ground planes. The digital ground plane is placed under ail components that handle
digital signals, while the analQQ ground plane is placed under all components that handle analog signals. The digital
and analog ground planes are connected together at only
one pOint, either the power supply ground or at the pins of
the ADO. This greatly reduces the occurence of ground
loops and noise.
.,
.

7.Q INPUT BYPASS CAPACITANCE
External capacitors (0.01 /tF-0.1 /tF) can be connected between the analog input pins, CHO-CH7, and analog ground
to filter any noise caused by inductive pickup associated
with long input leads. These capacitors will not degrade the
conversion accuracy.

Shown in Figure 14 is the ideal ground plane layout for the
ADC12L03S along with ideal placement of the bypass capacitors. The circuit board layout shown in Figure 14 uses
three bypass capacitors: 0.01 /tF (C1) and 0.1 /tF (C2) surface mount capacitors and 10 /tF (C3) tantalum capacitor.

,8.0 NOISE
The' leads to each of the analog multiplexer input pins
should be kept as short as possible. This Will minimize input
noise and clock frequency coupling that can cause conver'sit:>n errors. Input filtering can be used to reduce the .effects
of the noise sources.
.

11.0 CLOCK.SIGNAL LINE ISOLATION
The ADC12L030/2/4/S's performance is optimized by routing the analog input/output and reference Signal conductors
as far as possible from the conductors that carry the clock
signals to the CCLK anQ SCLK pins. Grpund traces parallel
to the clock Signal traces' can be used. on printed circuit
boards to reduce clock signal interference on, the analog
input/output pins.

9.0 POWER SUPPLIES
Noise spikes on the VA + and Vo+ supply lines can cause
conversion errors; the comparator Will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. The

TL/H/II830-44

FIGURE 14. Ideal Ground Plane for the ADC12L038

2-50S

Application Hints (Continued)

>C
.....
N
b
(')

An AID converter's AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal
waveform is applied to the AID converter's input, and the
transform is then performed on the digitized waveform.
S/(N + D) and SIN are calculated from the resulting FFT
data, and a spectral plot may also be obtained.
The AID converter's noise and distortion levels will change
with the frequency of the input signal, with more distortion
and noise occurring at higher signal frequencies. This can
be seen in the S/(N + D) versus frequency curves. These
curves will also give an indication of the full power bandwidth (the frequency at which the S/(N + D) or SIN drops
3 dB).

12.0 THE CALIBRATION CYCLE

A calibration cycle needs to be started after the power sup·
plies, reference, and clock have been given enough time to
stabilize after initial turn on. During the calibration cycle, correction values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall full-scale,
offset, and linearity errors down to the specified limits. Fullscale error typically changes ± 0.4 LSB over temperature
and linearity error changes even less; therefore it should be
necessary to go through the calibration cycle only once after power up if the Power Supply Voltage and the ambient
temperature do not change significantly (see the curves in
the Typical Performance Characteristics).

Effective number of bits can also be useful in describing the
AID's noise performance. An ideal AID converter will have
some amount of quantization noise, determined by its resolution, which will yield an optimum SIN ratio given by the
following equation:
SIN = (6.02 x n + 1.8) dB

13.0 THE AUTO-ZERO CYCLE

To correct for any change in the zero (offset) error of the
A/D, the auto-zero cycle can be used. It may be necessary
to do an auto-zero cycle whenever the ambient temperature
or the power supply voltage change significantly. (See the
curves titled "Zero Error Change vs Ambient Temperature"
and "Zero Error Change vs Supply Voltage" in the Typical
Performance Characteristics.)

where n is the AID's resolution in bits.
The effective bits of a real AID converter, therefore, can be
found by:

Co)

Q
......

>C
o.....
N

b

Co)

N

......

>-

C

(')

.....

N

b

Co)

~
.......

>-

C

(')

.....
N

b

Co)
OC)

.)
S/N(dB) - 1.8
(
n effective =
6.02

14.0 DYNAMIC PERFORMANCE

Many applications require the AID converter to digitize AC
Signals, but the standard DC integral and differential nonlinearity specifications will not accurately predict the AID converter's performance with AC input signals. The important
specifications for AC applications reflect the converter's
ability to digitize AC signals without significant spectral errors and without adding noise to the digitized signal. Dynamic characteristics such as signal-to-noise (SIN), signal-tonoise + distortion ratio (S/(N + Dj), effective bits, full power bandwidth, aperture time and aperture jitter are quantitative measures of the A/D converter's capability.

As an example, this device with a ±2.5V, 10 kHz sine wave
input signal will typically have a SIN of 78 dB, which is
equivalent to 12.6 effective bits.

fJI

2-509

co
CO)

9N

....

8
~

CO)

.---------------------------------------------------------------------------------~

Application Hints (Continued)
to the ADC12L038's DI, SCLK, and DO pins, resPectively.
The D flip flop drive the CS control line.

15.0 AN RS232 SERIAL INTERFACE
Shown below is a schematic for an RS232.interface to any
IBM and compatible PCs. The DTR, RTS, and CTS RS232
signal lines are buffered via level translators and connected

9N

....

8
~
N

CHO

+3.3V

RTS

CO)

9N

....

SMHz

OTR

o
c

~

CH4

CO)

CHS ADC12L038

~

9N

CH6

CS .....- - - - - - .

....
o

D I I - - - - - - - - - -....

.>()+8=7 CTS

CONY

RS232

EOC

C
8 THEN
FOR N=9 TO DOL
OUT &H3FC, (&Hl OR INP (&H3FC))
OUT &H3FC, (&HFD AND INP (&H3FC))
OUT &H3FC, (&H2 OR INP (&H3FC))

b

,jIo,

~

o
....

I\)

~

'reset DO variable
'SET DTR HIGH
'SCLK low

'SCLK high

'Input DO
'SET DTR HIGH
'SCLK low

'SET DTR HIGH
'SCLK low
'SCLK high

IF (INP(&H3FE) AND &H16)=&H16 THEN
DO$=DO$+"O"
ELSE
DO$=DO$+"l"
END IF
NEXT N
END IF
OUT &H3FC, (&HFA AND INP(&H3FC))
'SCLK low and DI high
FOR N=l TO 500
NEXT N
PRINT DO$
INPUT "Enter "C· to convert else "RETURN" to alter DI data"; s$
IF s$="C" OR s$="c" THEN
GOTO 20
ELSE
GO TO 10
END IF
END
2·511

fI

t!lNational Semiconductor

ADC 12130/ADC 12132/ADC 12138 Self-Calibrating 12-Bit
Plus Sign Serial I/O A/D Converters with MUX and
Sample/Hold
General Description

Features

The ADC12130, ADC12132 and ADC12138 are 12-bit plus
sign successive approximation AID converters with serial
I/O and configurable input multiplexer. The ADC12132 and
ADC12138 have a 2 and an 8 channel multiplexer, respectively. The differential multiplexer outputs and AID inputs
are available on the MUXOUT1, MUXOUT2, AlDIN1 and
AlDIN2 pins. The ADC12130 has a two channel multiplexer
with the multiplexer outputs and AID inputs internally connected. The ADC12130 family is tested with a 5 MHz clock.
On request, these A/ Ds go through a self calibration 'process that adjusts linearity, zero and full-scale errors to typically less than ± 1 LSB each.

•
•
•
•
•
•
•
•

The analog inputs can be configured to operate in various
combinations of single-ended, differential, or pseudo-differential modes. A fully differential unipolar analog input range
(OV to + 5V) can be accommodated with a single + 5V supply. In the differential modes, valid outputs are obtained
even when the negative inputs are greater than the positive
because of the 12-bit plus sign output data format.
The serial I/O is configured to comply with the NSC
MICROWIRETM. For complementary voltage references see
the LM4040, LM4041 or LM9140.

•
•
•
•
•
•

Serial I/O (MICROWIRE, SPI and aSPI Compatible)
2 or 8 channel differential or single-ended multiplexer
Analog input sample/hold function
Power down mode
Programmable acquisition time
Variable digital output word length and format
No zero or full scale adjustment required
OV to 5V analog input range with single 5V power
supply

Key Specifications
Resolution
12-bit plus sign conversion time
12-bit plus sign throughput time
Integral linearity error
Single supply
Power dissipation
-3.3V
- 3.3V power down
-5V
- 5V power down

12-bit plus sign
8.8""s (max)
14""s (max)
±2 LSB (max)
3.3Vor 5V ±10%
15 mW (max)
40 ""W (typ)
33 mW (max)
100 ""W (typ)

Applications
• Pen-based computers
• Digitizers
• Global positioning systems

ADC12138 Simplified Block Diagram
Cs'

PD

CONY

CClK

selK

~~===t==L-.cEDC

01

~--------------;------r--~Dai

CHO
CHI
CH'

DO

CH'
CH.
CH.
CH'
CH7
COW

NUXQUT1
A/DIN I
MUXOUT2
A/DIN'

VA'

0------'
[]4-------'

0------'

0--

Vo.o--

DGND

AGND

TUH112079-1

2-512

)0-

e

Connection Diagrams

o
....

....

I\)

16-Pln Dual-In-Llne and
Wide Body SO Packages

28-Pln Dual-In-Llne, SSOP and
Wide Body SO Packages

CHO- 1

16 -Vo +

CHO- 1

28 f-Vo+

CH1- 2

15 -CCLK

CH1- 2

27 f-OOR

COM- 3

14 -SCLK

CH2- 3

26

13 -01

CH3- 4

25 f- SCLK

12 -DO

CH4- 5

24 f-Ol

OOR- 4

Co)

;;e
o....
.....
I\)

I- CCLK

....~
)0-

AOC12130
EOC- 5
VREF - -

6

11

-es

CH5- 6

23 1-00

VREF + -

7

10 -CONY

CH6- 7

22

OGNO -

8

9 -

AOC12138

VA+
TL/H/12079-2

21 f- CONY

COM- 9

20 f-EOC

10

19

A/0IN1- 11

20-Pln SSOP Package
CHO- 1

20 ,... Vo+

CH1- 2

19 :- CCLK

COM- 3

18 -SCLK

MUXOUT1- 4
A/DlNl- 5

Co)

CCI

I-po

18 f-AGNO

MUXOUT2 -

12

17

A/OIN2 -

13

16

OGNO -

14

f- VREF +

I-VREF 15 I-V A+
TL/H/12079-3

Top View

17 -01
AOC12132

....

I\)

I-es

CH7- 8

MUXOUTI -

Top View

e
o
....

16 :-00

-es

MUXOUT2 -

6

15

A/DlN2 -

7

14 -CONY

VREF - -

8

13 -EOC

VREF + -

9

12 -OOR
11 -VA+

OGNO- 10

TLlH/12079-47

Top View

Ordering Information
Industrial Temperature Range
-40"C ~ TA ~ +85'C
ADC12130CIN

NSPackage
Number
N16E,

Dual-In-Line
ADC12130CIWM

M16B,
Wide Body SO

ADC12132CIMSA

MSA20,SSOP

ADC12138CIN

N28B,

Dual-In-Line
ADC12138CIWM

M28B

ADC12138CIMSA

MSA28,SSOP

2-513

•

CD

(II)

.....
N
.....

g
CC
....
N

(II)

.....
N
.....
o
c

~

(II)

.....
N
.....
o
c
CC

Absolute Maximum Ratings (Notes 1 & 2)

Operating Ratings (Notes 1 & 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Operating Temperature Range
TMIN ~ TA ~ TMAX
ADC12130CIN, ADC12130CIWM,
ADC12132CIMSA, ADC12138CIMSA,
ADC12138CIN,ADC12138CIWM -40·C ~ TA ~ +85·C

Positive Supply Voltage
(V+ = VA+ = Vo+)
Voltage at Inputs and Outputs
except CHO-CH7 and COM
Voltage at Analog Inputs
CHO-CH7 and COM

6.5V

SupplyVoltage(V+

-0.3VtoV+ +0.3V

(VREF+ + VREF-)
2

1500V

Soldering Information
N Packages (10 seconds)

260·C

SO Package (Note 6):
Vapor Phase (60 seconds)
Infrared (15 seconds)
Storage Temperature

0.1 VA + to 0.6 VA +

AlDIN1, AlDIN2, MUXOUT1
and MUXOUT2 Voltage Range

500mW

ESD Susceptability (Note 5)
Human Body Model

OVto VA+
OVtoVREF+
1VtoVA+

VREF(VREF+ -VREF-)
VREF Common Mode Voltage Range

300mV
±30mA
±120mA

Package Dissipation at
TA = 25·C (Note 4)

+ 3.0V to + 5.5V
~ 100 mV

VREF+
VREF-

GND -5VtoV+ +5V

IVA+ - vo+1
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)

= VA+ = Vo+)

IVA+ - vo+1

OVto VA +

AID IN Common Mode Voltage Range
(VIN+ + VIN-)
2

OVtoVA+

215D C
220"C
- 65·C to + 150·C

Converter Electrical Characteristics
The following specifications apply for (V+ = VA + = Vo+ = +5V, VREF+ = +4.096V, and fully differential input with fixed
2.048V common-mode voltage) or (V+ = VA + = Vo + = 3.3V, VREF+ = 2.5V and fully·differential input with fixed 1.250V
common-mode voltage), VREF- = OV, 12-bit + sign conversion mode, source impedance for analog inputs, VREF- and
VREF + ~ 250, fCK = fSK = 5 MHz, and 10 (tcK) acquisition time unless otherwise specified. Boldfade IImlls apply for T A
= T.. = TMIN to TMAXI all other limits TA = TJ = 25·C. (Notes 7, 8 and 9)
Symbol

Parameter

Conditions

Typical
(Note 10)

Limits
(Note 11)

Units
(Limits)

12 + sign

Bits (min)

STATIC CONVERTER CHARACTERISTICS
Resolution

!

+ILE

Positive Integral Linearity Error

After Auto-Cal (Notes 12, 18)

±1/2

±2

LSB(max)

-ILE

Negative Integral Linearity Error

After Auto-Cal (Notes 12, 18)

±1/2

±2

LSB(max)

DNL

Differential Non-Linearity

After Auto-Cal

±1.5

LSB(max)

Positive Full-Scale Error

After Auto-Cal (Notes 12, 18)

±1/2

±3.0

LSB (max)

Negative Full-Scale Error

After Auto-Cal (Noles 12, 18)

±1/2

±3.0

LSB(max)

Offset Error

After Auto-Cal (Notes 5, 18)
VIN(+) = VIN (-) = 2.048V

±1/2

±2

LSB(max)

TUE

DC Common Mode Error

After Auto-Cal (Note 15)

±2

LSB(max)

Total Unadjusted Error

After Auto-Cal
(Notes 12, 13 and 14)

±1

LSB

2·514

I

»
c

Converter Electrical Characteristics
The following specifications apply for (V+ = VA + = Vo+ = +5V, VREF+ = +4.096V, and fully differential input with fixed
2.048V common-mode voltage) or (V+ = VA + = Vo+ = 3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V
common-mode voltage), VREF- = OV, 12-bit + sign conversion mode, source impedance for analog inputs, VREF- and
VREF+ ,;;; 25!l, fCK = f5K = 5 MHz, and 10 (tcK! acquisition time unless otherwise specified. Boldfade limits apply for TA
= T .. = TMIN to TMAX; all other limits TA = TJ = 25'C. (Notes 7, 8 and 9) (Continued)
Symbol

Conditions

Parameter

Typical
(Note 10)

Limits
(Note 11)

Units
(Limits)

o
.....
N
.....
Co)
~

»
c

o.....
.....
N

Co)

N

);

STATIC CONVERTER CHARACTERISTICS (Continued)

C

Multiplexer Channel to Channel
Matching
Power Supply Sensitivity

±0.05

LSB

±0.5
±0.5
±0.5
±0.5
±0.5

LSB
LSB
LSB
LSB
LSB

69.4
68.3
65.7

dB
dB
dB

31

kHz

77.0
73.9
67.0

dB
dB
dB

40

kHz

V+ = +5V ±10%
VREF = +4.096V

Offset Error
+ Full-Scale Error
- Full-Scale Error
+ Integral Linearity Error
- Integral Linearity Error

o
.....
N
.....
Co)
CD

UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D)

Signal-to-Noise Plus
Distortion Ratio
-3 dB Full Power Bandwidth

= 1 kHz, VIN = 5 Vpp, VREF+ = 5.0V
= 20 kHz, VIN = 5 Vpp, VREF+ = 5.0V
= 40 kHz, VIN = 5 Vpp, VREF+ = 5.0V
VIN = 5 Vpp, where S/(N + D) drops 3 dB

fiN
fiN
fiN

DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D)

Signal-to-Noise Plus
Distortion Ratio
-3 dB Full Power Bandwidth

= 1 kHz, VIN = ±5V, VREF+ = 5.0V
= 20 kHz, VIN = ±5V, VREF+ = 5.0V
= 40 kHz, VIN = ±5V, VREF+ = 5.0V
VIN = ±5V, where S/(N+D) drops 3 dB

fiN
fiN
fiN

•

2-515

:g
,..
C'\I
,..

Co)

!i.....
C'\I

,..
C'\I
,..
o
c
C")

~,..
C'\I
,..

g

Electrical Characteristics
The following specifications apply for (V+ = VA + = Vo+ = +5V, VREF+ = +4.096V, and fully differential input with fixed
2.048V common-mode voltage) or (V+ = VA + = Vo+ = +3.3V, VREF+ = 2.5V and fully-differential input with fixed 1.250V
common-mode voltage), VREF- = OV, 12-bit + sign conversion mode, source impedance for analog inputs, VREF- and
VREF+ :s: 250, fCK = f8K = 5 MHz, and 10 (teKl acquisition time unless otherwise specified. Boldtade limits apply for TA
= T.. = T.IN to TMAX; all other limits TA = TJ = 25°C. (Notes 7, 8 and 9)
Symbol

"

Parameter

Conditions

Typical
(Note 10)

Limits
(Note 11)

Units
(Limits)

REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
CREF

Reference Input Capacitance

85

pF

CAlO

A/DIN1 and AlDIN2 Analog Input
CapaCitance

75

pF

±0.1

".A

GND - 0.05
VA+'.+ 0.05

V

cc

AlDIN1 and AlDIN2 Analog Input
Leakage Current

VIN = + 5.0V or
VIN = OV

CHO-CH7 and COM Input Voltage
CCH

CHO-CH7 and COM Input CapaCitance

10

pF

CMUXOUT

MUX Output CapaCitance

20

pF

On Channel = 5V and
Off Channel = OV

-0.Q1

".A

On Channel = OV and
Off Channel = 5V

0.01

".A

On Channel = 5Vand
Off Channel = OV

0.01

".A

On Channel = OV and
Off Channel = 5V

-0.Q1

".A
".A

Off Channel Leakage (Note 16)
CHO-CH7 and COM Pins

On Channel Leakage (Note 16)
CHO-CH7 and COM Pins

RON

MUXOUT1 and MUXOUT2
Leakage Current

VMUXOUT = 5.0Vor
VMUXOUT = OV

0.Q1

MUX On Resistance

VIN = 2.5V and
VMUXOUT = 2.4V

850

RON Matching Channel to Channel

VIN = 2.5V and
VMUXOUT = 2.4V

5

Channel to Channel Crosstalk

VIN = 5 Vpp, fiN = 40 kHz

MUX Bandwidth

2-516

1900

o (max)
%

-72

dB

90

kHz

):00

C

DC and Logic Electrical Characteristics
The following specifications apply for (V+ = VA + = Vo+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed
2.048V common-mode voltage) or (V+ = VA+ = Vo+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed
1.250V common-mode voltage), VREF- = OV, 12-bit + sign conversion mode, source impedance for analog inputs, VREFand VREF+ ,;: 25.11, fCK = fSK = 5 MHz, and 10 (tcK> acquisition time unless otherwise specified. Boldfade limits apply for
TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25'C. (Notes 7, 8 and 9)

Symbol

Parameter

Typical
(Note 10)

Conditions

V+ = VA+ =
Vo+ = 3.3V

V+ =VA+ =
Vo+ = 5V

Limits
(Note 11)

Limits
(Note 11)

2.0

2.0

Units
(Limits)

Logical "1" Input
Voltage

VA+ = Vo+ = V+ +10%

VIN(O)

Logical "0" Input
Voltage

VA+ = Vo+ = V+ -10%

IIN(l)

Logical "1" Input
Current

VIN = V+

IIN(O)

Logical "0" Input
Current

VIN = OV

(0)

o

):00

C

o
.....
N
.....

(0)

N

):00

C

o
.....

CCLK, CS, CONV, 01, PO AND SCLK INPUT CHARACTERISTICS
VIN(l)

o.....
N
.....

N

V (min)

.....

(0)

CD

0.8

0.8

V (max)

0.005

1.0

1.0

/LA (max)

-0.005

-1.0

-1.0

/LA (min)

VA+ = Vo+ = V+ - 10%,
lOUT = - 360 /LA

2.4

2.4

V (min)

VA+ = Vo+ = V+ - .10%,
lOUT = -10/LA

2.9

4.25

V (min)

0.4

0.4

V (max)

-3.0
3.0

-3.0
3.0

/LA (max)

DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
VOUT(l)

Logical "1"
Output Voltage

VOUT(O)

Logical "0"
Output Voltage

VA+ =Vo+ =V+ -10%
lOUT = 1.6 mA

lOUT

TRI-5TATE
Output Current

VOUT = OV
VOUT = V+

-0.1
-0.1

+Isc

Output Short
Circuit Source
Current

VOUT = OV

-14

Output Short
Circuit Sink
Current

VOUT = Vo+

-Isc

mA
16
mA

POWER SUPPLY CHARACTERISTICS
10+

IA+

IREF

Digital Supply
Current
Positive Analog
Supply Current
Reference Input
Current

1.5

2.5

mA(max)
/LA
/LA

3.0

4.0

10
0.1

mA(max)
/LA
/LA

70
0.1

/LA
/LA

CS = HIGH, Powered Down, CCLK on
CS = HIGH, Powered Down, CCLK off

600
20

CS = HIGH, Powered Down, CCLK on
CS = HIGH, Powered Down, CCLK off
CS = HIGH, Powered Down, CCLK on
CS = HIGH, Powered Down, CCLK off

2-517

fII

.,..
=
.,..
N

~....
~
.,..

.,..

N

~

~.,..
N
.,..
~

AC Electrical Characteristics
The following specifications apply for (V+ = VA + = Vo+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed
2.048V common-mode voltage) or (V+ = VA + = Vo + = + 3.3V, VREF+ =. + 2.5V and fully-differential input with fixed
1.250V common-mode voltage), VREF- = OV, 12-bit + sign conversion mode, source impedance for analog inputs, VREPand VREF+ ~ 250, fCK = f8K = 5 MHz, and 10 (lcK) acquisition time unless otherwise specified. Boldface limits apply for
TA = T.. = TMIN to TMAX; all other limits TA = TJ = 25°C. (Note 17)
Parameter

Symbol

Conditions

Typical
(Note 10)

Limits
(Note 11)

Units
(Limits)

fCK

Conversion Clock
(CCLK) Frequency

10
1

5

MHz (max)
MHz (min)

f8K

Serial Data Clock
SCLK Frequency

10
0

5

MHz (max)
Hz (min)

Conversion Clock
Duty Cycle

40
60

% (min)
% (max)

Serial Data Clock
Duty Cycle

40
60

% (min)
% (max)

CC

Ie
tA

Conversion Time

Acquisition Time
(Note 19)

12-Bit + Sign or 12-Bit

6 Cycles Programmed

10 Cycles Programmed

18 Cycles Programmed

34 Cycles Programmed

.leAL

tAZ

IsVNC

trn:>fi
~

Self-Calibration Time

44(leK)

6(tcKl

10(tcKl

18(leKl

34(leK)

4944(leK)

Auto-Zero Time

76(lcK)

Self-Calibration or
Auto-Zero Synchronization
Time from DOR

2(leK)

DOR High Time when CS is Low
Continuously for Read Data and Software
Power Up/Down

9(IsKl

~Valid Data Time

B(IsKl

2-518

44(tCK)

(max)

8.8

/Ls (max)

6(tCK)
7(tcK)

(min)
(max)

1.2
1.4

/Ls (min)
/Ls (max)

10(tcKl
11(tcK)

(min)
(max)

2.0
2.2

/Ls (min)
/Ls (max)

18(tcK)
19(tcK)

(min)
(max)

3.6
3.8

/Ls (min)
/Ls (max)

34(tcKl
35(tCK)

(min)
(max)

6.8
7.0

/Ls (min)
/Ls(max)

4944(tcKl

(max)

988.8

/Ls (max)

76(tCK)

(max)

15.2

/Ls (max)

2(tcK)
3(tcK)

(min)
(max)

0.40
0.60

/Ls (min)
/Ls (max)

9(tsK)

(max)

1.8

/Ls (max)

8(tsK)

(max)

1.6

/Ls (max)

:J>

The following specifications apply for (V+ = VA + = Vo+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed
2.048V common-mode voltage) or (V+ = VA + = Vo+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed
1.250V common-mode voltage), VREF- = OV, 12-bit + sign conversion mode, source impedance for analog inputs, VREFand VREF+ s: 250, fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for
TA = T" = TMIN to TMAXl all other limits TA = TJ = 25'C. (Note 17) (Continued)
Symbol

Parameter

......o
c
C

AC Electrical Characteristics

Conditions

Typical
(Note 10)

Limite
(Note 11)

Units
(Limits)

N

Cot)

":J>

......
C

o

I\)
Cot)

N

tHPU

Hardware Power-Up Time, Time from
PO Falling Edge to EOC Rising Edge

500

700

JLs (max)

tspu

Software Power-Up Time, Time from
Serial Data Clock Falling Edge to
EOC Rising Edge

500

700

JLs (max)

tACC

Access Time Delay from
CS Falling Edge to DO Data Valid

25

tSET-UP

Set-Up Time of CS Falling Edge to
Serial Data Clock Rising Edge

tOELAY

Delay from SCLK Falling
Edge to CS Falling Edge

tlH, toH

Delay from CS Rising Edge to
DOTRI-STATE®

tHOI

;;;

......o
C

N

Cot)

co

60

ns(max)

50

ns(min)

0

5

ns(min)

70

100

ns(max)

01 Hold TIme from Serial Data
Clock Rising Edge

5

15

ns(min)

tSDI

01 Set-Up Time from Serial Data
Clock Rising Edge

5

10

ns(min)

tHOO

DO Hold Time from Serial Data
Clock Falling Edge

35

65
5

ns(max)
ns(min)

tooo

Delay from Serial Data Clock
Falling Edge to DO Data Valid

50

90

ns(max)

tRoO

DO Rise Time, TRI-STATE to High
DO Rise Time, Low to High

RL = 3k, CL = 100 pF

10
10

40
40

ns(max)
ns(max)

tFDO

DO Fall Time, TRI-STATE to Low
DO Fall Time, High to Low

RL = 3k,CL = 100pF

15
15

40
40

ns(max)
ns(max)

tCD

Delay from CS Falling Edge
to DOR Falling Edge

45

80

ns(max)

tSD

Delay from Serial Data Clock Falling
Edge to DOR Rising Edge

45

80

ns(max)

CIN

Capacitance of Logic Inputs

10

pF

COUT

Capacitance of Logic Outputs

20

pF

RL = 3k, CL = 100 pF

RL = 3k,CL = 100pF

2-519

....~N
....
o
c

~
....
....
o

AC Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings Indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance IimHs. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some perfimnance characteristics may degrade when the device is not operated under the listed test
conditions.
'

C')

Note 2: All volteges are measured with respect to GND, unless otherwise specified.

N

Note 3: When the input voltage {VIJV at any pin exceeds the power supplies (\tIN < GND or VIN > VA + or Vo +), the current at that pin should be limHed to 30 rnA
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies wHh an Input current of 30 mA to four.

~....
...
o

Note 4: The maximum power dissipation must be derated at elevated temperafures and is dictated by TJmax, 9JA and the ambient tempereture, TA. The maximum
allowable power dissipation at any temperature is Po = (TJmax - TNI9JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJmax = 150'C. The typical thermal resistance (0JN of these parts when board mounted follow:

C')

N

Thermal'
ResIstance

Part Number

6JA

c

CC

53·C/W

ADC12130CIN
ADC12130CIWM

70·C/W

ADC12132CIMSA

134·C/W

ADC12138CIN

40·C/W

ADC12138CIWM

50·C/W

ADC12138CIMSA

125·C/W

Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kn resistor into each pin.
Note 6: See AN450 "Surface Mounting Methods and Their Effect on Product ReliabilHy" or the section tiUed "Surface Mount" found in any posI1986 National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Two on·chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnRude up to 5V above VA + or 5V below GND
will not damage this device. However, errors in the AID conversion can occur Cd these diodes are forward biased by more than 50 my) If the input voHage
magnitude of selected or unselected analog input go above VA + or below GND by more than 50 mV. As an example, if VA + is 4.5 VOC' full-scale input voltage
must be :s: 4.55 Voc to ensure accurate conversions.

r--- -----l-

ANALOG
INPUTS

t-+-'w.,.....~..~-+
I
L
I

TO INTERNAL
CIRCUITRY

-l________
~~

GND

_

TLlHI12079-4

Note 8: To guarantee accuracy, it is required that the VA + and Vo + be connected tcgether to the same power supply with separate bypass capacitors at each V+

pin ..
Note 9: With the test condition for VREF (VREF+ - VREF-) given as +4.096V, the 12·bH LSB isl.0 mY. For VREF = 2.5V, the 12-b1t LSB Is 610 ".V.
Note 10: Typicals are at TJ = TA = 25°C and represent most likely parametric norm.
Note 11: Tested IimHs are guaranteed to National's AOQL (Average Outgoing QualHy Level).
Note 12: PosHive integral linearity error is defined as the deviation of the analcg value, expressad in LSBs, from the straight line that passes through pOSitive fullscale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figures Ib and Ic).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It Is the average value of the code tranSitions
between -1 to 0 and 0 to + 1 (see Figure 2).
Note 14: Total unadjusted error includes offset, full·scale, linearity and multiplexer errors.
Note 15: The DC common·mode error is measured in the differential multiplexer mode with the assigned posHive and negative input channels shorted together.
Note 16: Channel leakage current is measured after the channel selection.

Note 17: Timing specifications are tested at the TTL logic levels, VOL = O.4V for a falling edge and VOL = 2.4V for a rising edge. TRI-STATE output voHage Is
forced to 1.4V.
Note 18: The ADC12130 family's self-calibration technique ensures linearity and offset errors as specified, but noise Inherent In the self-calibratlon process will
r.sult in a maximum repaatabilHy uncertainty of 0.2 LSB.
Note 19: If SCLK and CCLK are driven from the same clock source, then tA is 6,10,18 or 34 clock periods minimum and maximum.

Note 20: The "12-Bit Conversion of Offset" and "12-Bit Conversion of Full·Scale" modes are intended to test the functionalHy of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.

2-520

:J>

c

o
....

AC Electrical Characteristics (Continued)

....

~

Co)

Q

0,1111,1111,1111 (+4095)
0,1111,1111,111 o( +4094)
"

~E

",

,,

FULL -SCALE
TRANSITION

VIN + > VIN -

(+ 1) _-r-+..E===:2Z=E~RO~T~R~A~NS~I~TIO~N~_ _ _ _ _ _ _-I
1--------0,0000,0000,0001
0,0000,0000,0000(0)
1,1111,1111,1111 (-1)
1,1111,1111,1110 (-2)
VREF = VREF + - VREF VIN = VIN + - VIN GND :S VIN + :S VA+
GND :S VIN - :S VA+

1,0000,0000,0001 (-4095)
1,0000,0000,0000 (-4096)
ANALOG INPUT VOLTAGE (VIN )
TL/H/12079-5

FIGURE la. Transfer Characteristic

+12 LSB
+8 LSB

NEGATIVE
FULL-SCALE
ERROR

POSITIVE
FULL-SCALE
ERROR

-4LSB
-8 LSB
LINEARITY
ERROR

-12LSB
OUTPUT CODE

(from -4096 to +4095)
TL/H/12079-6

FIGURE lb. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles

2-521

g
....
N
....
Co)

//,/'

0,0000,0000,001 o( +2)

);;

~o....
....

~

Co)

co

AC Electrical Characteristics (Continued)
+3 LSB
+2 LSB
OFFSET

+1 LSB

1ERROR

_J ________________________ _

T

POSITIVE
FULL-SCALE
ERROR

j

t

-4096
NEGATIVE
FULL-SCALE
ERROR

POSITIVE
INTEGRAL
LlNEARITY,,ERROR
.........

'"

NEGATIVE
INTEGRAL
LINEARITY
ERROR

-1 LSB
-2 LSB
-3LSB
OUTPUT COOE

(from -4096 to +4095)
TUH/12079-7

FIGURE 1c. Simplified Error Curve vs Output Code after Auto-Callbratlon Cycle

+2

+1

...o

8

a

~---------------,---1~~----------------

~

--l

~

OFFSET VOLTAGE

o
-1

-2
ANALOG INPUT VOLTAGE (VIN )

FIGURE 2. Offset or Zero Error Voltage

2-522

TUH/12079-8

Typical Performance Characteristics
The following curves apply for 12-bit

+

sign mode after auto-calibration unless otherwise specified.

Linearity Error Change
vs Clock Frequency
0.15

~
l:il

(IN'; VIN_) ~ 2.b48~i-"'''''''

>-

-0.05

~
::;

-0,10

~

1/
1

2

3

"

5

6

7

8

I"

0.05

>-

-0.05

'"

-0.10

0.25

s

~

0.20

g'"
~

~
~

0.15

f-

f-

\

0.05

~

I'-

./

V

V-

-0.05
4.50

+2

S

~

+1

w

~

w

~

4.75

5.00

5.25

d.
"z

0.4

r--or--:---,-.,--,-..,-.,....,

=

V

-0.2

I-hI-N\II-+¥+Jf+--?' -60 SiN = 77 .54 dB
S/{N+D) = 72.29 dB

I"
10

I

~

I

o

RS - 600n
V'N=5V

.3 -40, fc

z

Bipolar Spectral Response
with 30 kHz Sine Wave Input

;;;-

;;;-

SiN = 77.89dB
S/{N+O) = 74.93dB

I-

FREQUENCY (kHz)

-20

.~

fe;: 5 MHz
Sampling Rate=;~

,I

-100

10

,!

·20

v/ =va+;: VREF+ = sv

-80

-120

o

TA=25 0 C

I-

-

in

I

VIN ;: 5V

I-

~

~

-80

-100

-40 -20

VA+~VD+;:VREF+=5V

;;;.;g -40 f ~

RS = 600n

VIN = 5V

r-r-f- r--

-20

Bipolar Spectral Response
with 20 kHz Sine Wave Input

Bipolar Spectnil Response
with 10kHz Sine Wave Input

25

FREQUENCY (kHz)

30

35

1"'''

o

10

15

20

25

30

35

FREQUENCY (kHz)

TL/H/12079-11

•

2-525

Typical Dynamic Performance Characteristics

+ sign mode atter auto-calibration unless otherwise specified. (Continued)

The following curves apply for 12-bit
Bipolar Spurious Free
Dynamic Range
95
90

....

3

~

..
~

~

......

85

-

....3

"

80

Rs = 600n
75 Til. = 25°C
YA+=VD+=v, +=5V
Ic = 5 MHz
70
g
3. 5
Sam!lin
VIN SVp_ ~iti
p
65

l"fflll

II 11

11,0

z

;n-

80

80

78

78

76

76

74
72
70

klZ

10'

~

'"

30
20
10

o

.......

k'"

/'

V

FIN = 1 kHz

1/

62
60

IIi'

102

-

....3

-40

§

- -

-60

~

-80

hI

-100

..
~

z

iii

....3

..~
~

z

III.... .1

I. i'l

-100

o

~~rN:6)~%~:5-i r-

....
3

-

I-

-40

I-

§

-

-60

-

I-

;!

-80

iii

J

iii

5

10

IS

20

25

30

10

IS

20

25

30

35

o

~~rN:~:~I:o~:~

Hl Jj. I

5

I

-20

~~+==2;:+C= VRE~+ = Jv

J J 1,1

-100

....
3

o

~
~

iii

I IJ

iJJ

10

IS

20

25

30

35

Unipolar Spectral Response
with 40 kHz Sine Wave Input

RS = 600n
Y,N = 5V

-BO

35

=

FREQUENCY (kHz)

-40 f C=5MHz
Sampling Rata=73.SkHz
-60 S/N=71.06dB
S/(N+O) = 6B.25 dB

-120
5

RS = 600n
V,N = 5V
T, = 25°C.! .~
VA+ =Vo+ VREr+= 5Y
fC=5WHz
Sampling Ralo = 13.5 kHz

JI.oI.

-100

Unipolar Spectral Response
with 30 kHz Sine Wave Input
-20

-40 fC =5MHz
Sampling Rate = 13.5 kHz
-60 SIN = 72.06 dB
S/(N+D) = 69.48 dB

-120

fC=SNHz

-20

-120
o

I

T

10'

FREQUENCY (kHz)

~~+==2;;.C= VRE~+ = !v

-80

HI'

5

Unipolar Spectral Response
with 10 kHz Sine Wave Input

-120
0

Unipolar Spectral Response
with 20 kHz Sine Wave Input

§

.J.. !.

Sampling Rate = 73.5 kHz

- -

INPUT SIGNAL LEVEL (dB)

....3

I

jamlrt·

samrnr

i"-

FREQUENCY (kHz)

RS = 600n
VIN =5V
T, = 25°C
VA+ =Vo+ =VREF+ = SV

-

-20

Rs = 600n
V,N =5V

H~:vp-p

60

UnIpolar Spectral Response
with 1 kHz Sine Wave Input

iii

-70 -60 -50 -40 -30 -20 -10

-20

V,N

FREQUENCY (kHz)

1/

/

-

62

80

40

~

70

72

64

FREQUENCY (kHz)

~

74

:;;;

Unipolar Signal-to-Noise
+ DistortIon RatIo
vs Input Signal Level

....3

....3.

~ lill
11111
11111

68 Rs=600nllJlI
T, = 25°C .[11111
66
VA+=VD+=~"f~li5V
64 fc =5MHz

68
66

Rs = 600n
70 TA = 25°C
VA+ = Yo+ = YREt = SV
60 fc=SMHz
Sampling Rata =73.5 kHz
50

Unipolar Signal-to-Nolse
+ Distortion Ratio
vslnputFnequency

Unipolar Signal-to-Noise Ratio
vs Input Frequency

Rs = 600n
Y,N = 5V

I

~~+==2~:+C=VRE~+ = ~V

-40 f C=5NHz
Sampling Rate=73.5kHz
-60 S/N=70.37dB
S/(N+O) = 67.01 dB
-80
-100

It

Iiii ....L~

o

5

hi

-120
5

FREQUENCY (kHz)

10

15

20

25

30

35

FREQUENCY (kHz)

10

15

20

25

30

35

FREQUENCY (kHz)

Unipolar Spectral Response
with 50 kHz Sine Wave Input
-20

....3
~

~
:;;!

~

RS = 600n
VIN =5V
T, = 25°C
.•~
VA+ Vo+ = VREF+ = SV

I

!.

=

-40 fC =5MHz
Sampling Rate = 73.5 kHz
-60 SIN = 6B.B7 dB
~i'(N+D) = 65.B4dB

I

-BO

.11

-100

1

-120
o

5

10

15

20

"

25

.1

30

35

FREQUENCY (kHz)
TL/H/12079-12

2-526

.--------------------------------------------------------------------.~

-~
-c

Test Circuits

o

I \)

i

DO except "TRI-8TATE"

DO "TRI·STATE" (t1H. tOH)
, TEST POINT

s.OV

c

. TEST POINT

I'~"'" 001 ,~'"'

NM07000

o

2.2k

I \)

AOC12138 DO I-"'-~-t.--.

~

MM07000

G.

or Equivalent

TL/H/12079-13

i>
o

--

o

I \)

Co)

CD

TUH112079-14

Leakage Current
+5.0V

AOC12138

CHO(ON)

CH 1(OFF)

+----1 C~2(OFF)
:'
•

.

CH7(Orr)
TUH/12079-15

Timing Diagrams
DO Failing and Rising Edge

DO "TRI·STATE" Failing and Rising Edge
~oo
DO

00

FJI

1.4V -TRI-STATE

TUH/12079-16

'roo
TLlH/12079-17

DI Data Input Timing

TL/H/12079-18

2·527

Timing Diagrams (Continued)
DO Data Output Timing Using CS
. 0

4

TL/H/12079-19

DO Data Output Timing with CS Continuously Low.
SCLK

'sET-UP

cs
IACC

00
'cO
OOR

roc
TL/H/12079-20

ADC12138 Auto Calor Auto Zero

DOR -,~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~

S~

EOC

r

L-....s~!- - - - -....

TL/H/12079-21

Note: DO output data is not valid during this cycle.

2-528

g
....

Timing Diagrams (Continued)

....

N

ADC12138 Read Data without Starting a Conversion Using CS

~

:I>

CCLK

C

o....
N
.....

SCLK

-g
Co)

N

:I>

....
....
N

Co)

co

~

DBn

11

DBO

.....---------ss~I

DOR - ,

EOC

--------------------~H~----------------------TLlH/12079-22

ADC12138 Read Data without Starting a Conversion with CS Continuously Low
CCLK

1nI1.SVUlSLrL

SCLK

~~s----

EI
DO

DBO

DBI

DB2

DBn

DBO

--------------------~s~----~~~---

EOC

----------------------~------~Sjr----------~Srj-----------------TLlH/12079-23

2·529

Timing Diagrams (Continued)
ADC12138 Conversion Using CS with 16·81t Dlgltal'Output Format

l\-i

EOC

r

~I-I---"'·

TL/H/12079-24

ADC12138 Conversion with CS Continuously Low and 16·81t Digital Output Format

l\-i

EOC

r

~II----""""·

TL/H/12079-25

2·530

»
c
o......

Timing Diagrams (Continued)

N

......
Co)

ADC12138 Software Power Up/Down Using CS with 16-Bit Digital Output Format

.....
C)

»

g
......
i\)
......

Co)

~C

o.....

N

......
Co)
CD

~;~ XXXXXXXXXXXXXXX~
Power

Up

__~__________________________~I1~~____~r__

EOC
TLlH/12079-26

ADC12138 Software Power Up/Down with CS Continuously Low and 16-Blt Digital Output Format

fII

~;~ XXXXXXXXXXXXXXX~
Power
Up
EOC

I~I------+--

----------------------------~I~~I____~r__

Tl/H/12079-27

2-531

co
CO)

,..

,..
N

Timing Diagrams (Continued)

o
c

ADC12138 Hardware Power Up/Down

~

,..
N
,..
o
c
CO)

~

,..
N
,..
o
c

PO

__. . .I---------!!-------.....,E~··I_\-Up-Pu---_+--

CCLK

CO)

c:c

SCLK

[OC

XXXXX)

!~I--------------~~----~
TLlH/12079-2B

Nole: Hardware power up/down may occur at any time. " PO is high while a conversion Is in progress that conversion will be corrupted and erroneous data will be

stored in the output shift register.

ADC12138 Configuration Modification-Example of a Status Read

I

Cycle N
Cycle Nt 1
01 Program Read Status - - - - . r o - - - - - - - D I Start a Conversion -------<~
DO Data from Cycle N-l
DO Status Data

12-bit Conversion

CCLK

SCLK

01
DO

DBO OBI

N-l Data

082 083 DB. DBS DB6

CB7

DBB

Status Oata

!~I-I_-,r

[OC

TL/H/12079-29

2·532

Pin Descriptions
CCLK

SCLK

01

DO

EOC

CS

The clock applied to this input controls the sucessive approximation conversion time interval and
the acquisition time. The rise and fall times of the
clock edges should not exceed 1 '""S.
This is the serial data clock input. The clock applied to this input controls the rate at which the
serial data exchange occurs. The rising edge
loads the information on the 01 pin into the multiplexer address and mode select shift register.
This address controls which channel of the analog input multiplexer (MUX) is selected and the
mode of operation for the AID. With CS low, the
falling edge of SCLK shifts the data resulting from
the previous AOC conversion out on DO, with the
exception of the first bit of data. When CS is low
continuously, the first bit of the data is clocked
out on the rising edge of EOC (end of conversion). When CS is toggled, the falling edge of CS
always clocks out the first bit of data. ~ should
be brought low when SCLK is low. The rise and
fall times of the clock edges should not exceed
1 ,""S.
This is the serial data input pin. The data applied
to this pin is shifted by the rising edge of SCLK
into the multiplexer address and mode select register. Tables II through IV show the assignment of
the multiplexer address and the mode select
data.
The data output pin. This pin is an active push/
pull output when CS is low. When CS is high, this
output is TRI-STATE. The AID conversion result
(080-0812) and converter status data are
clocked out by the falling edge of SCLK on this
pin. The word length and format of this result can
vary (see Table I). The word length and format
are controlled by the data shifted into the multiplexer address and mode select register (see Table IV).
This pin is an active push/pull output and indicates the status of the AOC12130/2/B. When
low, it Signals that the AID is busy with a conversion, auto-calibration, auto-zero or power down
cycle. The rising edge of EOC signals the end of
one of these cycles.
This is the chip select pin. When a logic low is
applied to this pin, the rising edge of SCLK shifts
the data on 01 into the address register. This low
also brings DO out of TRI-STATE. With CS low,
the falling edge of SCLK shifts the data resulting
from the previous AOC conversion out on ~O,
with the exception of the first bit of data. When
CS is low continuously, the first bit of the data is
clocked out on the rising edge of EOC (end of
conversion). When CS is toggled, the falling edge
of CS always clocks out the first bit of data. CS
should be brought low when SCLK is low. The
falling edge of CS resets a conversion in progress
and starts the sequence for a new conversion.
When e'S is brought back low during a conversion, that conversion is prematurely terminated.
The data In the output latches may be corrupted.
Therefore, when ~ is brought back low during a
conversion in progress the data output at that

time should be ignored. CS may also be left
continuously low. In this case it is imperative
that the correct number of SCLK pulses be applied to the AOC in order to remain synchronous. After the AOC supply power is applied it
expects to see 13 clock pulses for each I/O
sequence. The number of clock pulses the AOC
expects is the same as the digital output word
length. This word length can be modified by the
data shifted in on the DO pin. Table IV details
the data required.
This is the data output ready pin. This pin is an
active push/pull output. It is low when the conversion result is being shifted out and goes high
to signal that all the data has been shifted out.
A logic low is required on this pin to program
any mode or change the AOC's configuration as
listed in the Mode Programming Table (Table
IV) such as 12-bit conversion, Auto Cal, Auto
Zero etc. When this pin is high the AOC is
placed in the read data only mode. While in the
read data only mode, bringing ~ low and pulsing SCLK will only clock out on DO any data
stored in the AOCs output shift register. The
data on 01 will be neglected. A new conversion
will not be started and the AOC will remain in
the mode and/or configuration previously programmed. Read data only cannot be performed
while a conversion, Auto~Cal or Auto-Zero are
in progress.
PO
This is the power down pin. When PO is high
the AlO'is powered down; when PO is low the
AID is powered up. The AID takes a maximum
of 700 '""S to power up after the command is
given.
CHO-CH7 These are the analog inputs of the MUX. A
channel input is selected by the address information at the 01 pin, which is loaded on the
rising edge of SCLK into the address register
(see Tables II and III).
The voltage applied to these inputs should not
exceed VA + or go below GNO. Exceeding this
range on a,n unselected chanrielwill corrupt the
reading of a selected channel.
COM
This pin is another analog input pin. It is used as
a pseudo ground when the analog multiplexer is
single-ended.
MUXOUT1, These are the multiplexer output pins.
MUXOUT2
AlOIN1,
These are the converter input pins. MUXOUT1
is usually tied to AlOIN1. MUXOUT2 is usually
AlOIN2
tied to AlDIN2. If external circuitry is placed between MUXOUT1 and AlOIN1, or MUXOUT2
and AlOIN2 it may be necessary to protect
these pins. The voltage at these pins should not
exceed VA + or go below AGND (see Figure 3).
This is the positive analog voltage reference input. In order to maintain accuracy, the voltage
range of VREF (VREF = VREF+ - VREF-) is
1 Voc to 5.0 Voe and the voltage at VREF+
cannot exceed VA +. See Figure 4 for recommended bypassing.

2-533

Pin Descriptions (Continued)
The negative voltage reference input. In order
to maintain accuracy. the voltage at this pin
must not go below GND or exceed VA +. (See
Figure 4).
VA-:-. Vo+ These are the analog and digital power supply
pins. VA + 'and Vo + are not connected together
on the chip.' These pins should be tied to the
'same power supply and bypasSed separately
(see Figure, 4). The op~rating voltage range of
VA + and Vo + is 3.0 'Voe to 5.5 Voe.
DGND
This is the digital ground pin (see Figure 4).
AGND
This is the analog ground pin: (see Figure 4 ).
VREF-

1N914

250n
IN914

,

,

'

TL/H/12079-30

FIGURE 3. Protecting the MUXOUT1, MlIXOUT2,
A/DIN1. and AlDIN2 Analog Pins

V+
Analog
Assigned
Input ">-----1 (+) INPUT
,Voltage '"

,+5V

+

Vo

I
Analog
In'put
Voltage'

-

ADC

>-----1

Assigned
(-) INPUT

VREF +

I

I
------o +4.096V

I-.....>=-...""'!"....

I
I I
..,.
VREF -

DGND

AGND

Analog
Input
Voltage >--.;....-....;.------~t_--------'
Ground
,Reference'
TLlH/12079-31

'Tantalum
"MonalHhlc Ceramic or better '

'FIGURE 4. Recommended Power Supply Bypassing and Grounding

2-534

Tables
TABLE I. Data Out Formats
DO Formats

DBO DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16

17
X
X
MSB Bits
First 13
Sign MSB
Bits

with
Sign

9

8

7

6

5

4

7

6

5

4

3

2

1

LSB

4

5

6

7

8

9

10

MSB

Sign

3

4

5

6

7

8

9

10

MSB

Sign

0

0

MSB

10

9

8

7

6

5

4

10

9

8

7

6

5

4

3

2

1

LSB

1

2

3

4

5

6

7

8

9

10

MSB

1

2

3

4

5

6

7

8

9

10

MSB

17
LSB
LSB Bits
First 13
LSB
Bits

16
0
MSB Bits
First 12
MSB
Bits
without
Sign
16
LSB
LSB Bits
First 12
.'
LSB
Bits

x=

10

X

X

10

9

8

1

2

3

1

2

0

Sign MSB

3

2

1

LSB

X

X

X

X

3

2

1

LSB

0

0

0

0

High or Low state.

TABLE II. ADC12138 Multiplexer Addressing
Analog Channel Addressed
and Assignment
with AlDIN1 tied to MUXOUT1
and AlDIN2 tied to MUXOUT2

MUX
Address

AID Input
Polarity
Assignment

Multiplexer
Output
Channel
Assignment

Mode

DID 011 012 013 CHO CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM A/DIN1 AlDIN2 MUXOUT1 MUXOUT2
L
L
L
L
L
L
L
L

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

+

H
H
H
H

L
L
L
L

H
H

H
H
H

L
H
L
H
L

+

H

L
L
H
H
L
L

H

H

H

H
H

L
H

-

+

+

-

-

+
+

-

+

-

+

-

-

-

-

+
+
+

-

+
+
+

2-535

-

-

+
+
+
+

-

+

+

+
+
+
+

-

+
+
+
+
+
+
+
+

-

-

-

CHO
CH2
CH4
CH6
CHO
CH2
CH4
CH6

CH1
CH3
CH5
CH7
CH1
CH3
CH5
CH7

Differential

CHO
CH2
CH4
CH6
CH1
CH3
CH5
CH7

COM
COM
COM
COM
COM
COM
COM
COM

Single-Ended

II

Tables (Continued)
TABLE III. AOC12130 and AOC12132 Multiplexer Addressing
Analog Channel Addressed
and Assignment
with AlDIN1 tied to MUXOUT1
and AlDIN2 tied to MUXOUT2

MUX
Address

Multiplexer
Output
Channel
Assignment

AID Input
Polarity
Assignment

COM

Mode

010

011

CHO

CH1

A/01N1

A/01N2

MUXQUT1

MUXOUT2

L
L

L
H

+

-

+

-

-

+

-

.+

CHO
CHO

CH1
CH1

Differential

H
H

L
H

+

+
+

-

CHO
CH1

COM
COM

Single-Ended

-

+

-

Note: ADC12130 do ncit have AlDIN1, AlDIN2, MUXOUT1 and MUXOUT2 pins.

TABLE IV. Mode Programming
AOC12138
AOC12130
and

010

011

012

013

015

.014

016

017
Mode Selected
(Current)

DO Format
(next Conversion
, Cycle)

011

012

013

014

See Tables II or III

L

L

L

L

1'2 Bit Conversion

12 or 13 Bit MSB First

See Tables II or '"

L

L

L

H

12 Bit Conversion

16 or 17 Bit MSB First

See Tables II or '"

L

H

L

L

12 Bit Conversion

12 or 13 Bit LSB First

010

015

AO~12132

L

H

L

H

12 Bit Conversion

16 or 17 Bit LSB First

L

L

L

L

H

L

L

L

Auto Cal

No Change

L

L.

L

L

H

L

L

H

Auto Zero

No Change

L

L

L

L

H

L

H

L

Power Up

No Change

~

L

L

L

H

L

H

H

Power Down

No Change

L

L

L

L

H

H

L

L

Read Status Register (LSB First)

NoCliange

L

L

L

L

H

H

L

H

Data Out without Sign

No Change

H

L

r.

L

H

H

L

H

Data Out with Sign

NdChange

See Tables II or '"

..

L

L

L

L

H

H

H

L

Acquisition Time-6 CCLK Cycles

No Change

L

H

L

L

H

H

H

L

Acquisition Time-1 0 CCLK Cycles

No Change

H

L

L

L

H

H

H

L

Acquisition Time-18 CCLK Cycles

No Change

H

H

L

L

H

H

H

L

Acquisition Time-34 CCLK Cycles

No Change

L

L

L

L

H

H

H

H

User Mode

No Change

H

.Test Mode
(CH1-CH7 become Active Outputs)

No Change

H

X

X

X

H

H

H

Note: The AID powers up with no Auto cal, no Auto Zero, 10 CCLK acquisition time,12-bit + sign conversion, power up,12- or 13-bit MSs First, and user mode.
X = Don't Care

TABLE V. Conversion/Read Data Only Mode Programming
CS

CON V

PO

Mode

L

L

L

See Table IV for Mode

L

H

L

Read Only (Previous DO Format). No Conversion.

H

X

L

Idle

X

X

H

Power Down

X = Don't care

2-536

:tO

......

Tables (Continued)

o

I\)

TABLE VI. Status Register

Co)

Status Bit
Location
Status Bit

DBO

DB1

DB2

PD

Cal

. PU

DB4

DEl3

12 or 13

Device Status
"High'"
indicates a
Power Up
Function Sequence is
in progress

High"
indicates a
Power Down
Sequence is
in progress
II

, DBS

DB6

DB7.

DBB

16 or 17

Sign

Justification

Test Mode

Not used

'"High'"
indicates a 12
or 13 bit
format

"High'"
indicates a 16
or 17 bit
format

'"High'"
indicates that
the sign bit is
included.
When "Low'"
the sign bit is
not included,

......
I\)

DO Output Format Status

"High"
indicates an
Auto·Cal
Sequence is
in progress

~o

(')

When '"High'"
the
conversion
result will be
output MSB
first. When
"Low'" the
result will be
output LSB
first.

When '"High'"
the device is
in test mode.
When "Low'"
the device is
in user mode.

~o

......
co

(')
I\)

Co)

Application Hints
1.0 DIGITAL INTERFACE

1.2 Changing Configuration

1.1 Interface Concepts

The configuration of the ADC12130/2/8 on power up defaults to 12-bit plus sign resolution, 12- or 13-bit MSB First,
10 CCLK acquisition time, user mode, no Auto Cal, no Auto
Zero,. and power up mode, Changing the acquisition time
and turning the sign bit· on and off requires an 8·bit instruction to be issued to the ADC. This instruction will not start a
conversion. The instructions that select. a multiplexer ad"
dress and format the output data do start a conversion. Rgure 6 describes an example of changing the configuration of
the ADC12130/2/S.

The example in Figure 5 shows a typical sequence of
events after the power is applied to the ADC12130/2/8:
Read Status

00

Trash

Trash

Read Status

Status Data

(Cal low)

, 2-BIt+5ign
Cony 1

12-Bit+Sign I
ConY 2 I

Status Dota

Cony 1

Data

J

TLIH112079-32

During 110 sequence 1, the instruction on 01 configures the
ADC12130/2/8 to do a conversion with 12-bit +sign resolution.. Notice that when the 6 CCLK Acquisition and Data
Out without Sign instructions are issued to the ADC, I/O
.sequences 2 and 3, a new conversion is not started. The
data output during these instructions is from conversion N
which was started during I/O sequence 1, The Configuration Modification timing diagram describes in detail the sequence of events necessary for a Data Out without Sign,
Data Out with Sign, or 6110/18/34 CCLK Acquisition time
mode selection, Table IV describes the actual data necessary to be input to. the ADC to accomplish this configuration
modification, The next instruction, shown in Figure 6, issued
to the AID starts conversion N + 1 with 16-bit format with 12
bits of resolution formatted MSB first. Again the data output
during this 110 cycle is the data from conversion N.
The number of SCLKs applied to the AID during any conversion I/O sequence should vary in accord with the data
out word format chosen during the previous conversion I/O
sequence. The various formats. and resolutions available
are shown in Table I. In Figure 6, since 16-bit without sign
MSB first format was chosen during 110 sequence 4, the
number of SCLKs required during I/O sequence 5 is 16. In
the following I/O sequence the format changes to 12-bit
without sign MSB first; therefore the number of SCLKs required during, I/O s~quence 6 changes accordingly to 12,

FIGURE S. Typical Power Supply Power Up Sequence
The first instruction input to the AID via 01 initiates Auto Cal,
The data output on DO at that time is meaningless and is
completely random. To determine whether the Auto Cal has
been completed, a read status instruction is issued to the
AID. Again the data output at that time has no significance
since the Auto Cal procedure modifies the data in the output
shift register, To retrieve the status information, an addition·
al read status instruction is issued to the AID. At this time
the status data is available on DO. If the Cal signal in the
status word, is low Auto Cal has been completed. Therefore, the next instruction issued can start a conversion. The
data output at this time is again status information. To keep
noise from corrupting the AID conversion, status can not be
read during a conversion. If CS is strobed and is brought low
during a conversion, that conversion is prematurely ended.
EOC can be used to determine the end of a conversion or
the AID controller can keep track in software of when it
would be appropriate to comnmunicate to the AID again.
Once it has been determined that the AID has completed a
conversion, another instruction can be transmitted to the
AID. The data from this conversion can be accessed when
the next instruction is issued to the AID.
Note, when CS is low continuously it is important to transmit
the exact number of SCLK cycles, as shown in the timing
diagrams. The Data Out Format sets the number of SCLK
cycles required in the next I/O cycle. A 12-bit no sign format
will require 12 SCLKs to be transmitted; a 12-bit plus sign
format will require 13 SCLKs to be transmitted, etc. Not doing so will desynchronize the serial communication to the
AID. (See Section 1.3.)

1.3 CS Low Continuously Considerations
When CS is continuously low, it is important to transmit the
exact number of SCLK pulses that the ADC expects, Not
doing so will desynchronize the serial communications to
the ADC. When the supply power is first applied to the ADC,

2-537

II

co ,---------------------------------------------------------------------------------,

....
N
....
g
CO)

4(

~
CO)

....
....
o
N

c

~....

Application Hints (Continued)

N

12-Bit MSB or LSB First

16-Bit MSB or LSB first

Part
Number

Number of
SCLKs
Expected

DO Format

....
o
cc(

In Figure 6 the only times when the channel configuration
couid be modified would be during I/O sequences 1, 4, 5
and 6. Input channels are reselected before the start of
each new conversion. Shown below is the data bit stream
required on 01, during I/O sequence number 4 in Figure 6,
to set CH1 as the positive input and CHO as the negative
input for the different versions of ADCs:

it will expect to see 13 SCLK pulses for each I/O transmission. The number of SCLK pulses that the ADC expects to
see is the same as the digital output word length. The digital
output word length is controlled by the Data Out (DO) format. The DO format maybe changed any time a conversion
is started or when the sign bit is turned on or off. The table
below details out the number of clock periods required for
different DO formats:

SIGN OFF

12

SIGN ON

13

SIGN OFF

16

SIGN ON

17

CSStrobed

13SCLKs

8SCLKs

Read Status

13SCLKs

8SCLKs

Read Status

13SCLKs

8SCLKs

12-Bit

+ Sign Conv 1
+ Sign Conv 2

DI2

013

014

DIS

016

DI7

H

L

L

H

L

X

·X

AOC12138

L

H

L

L

L

L

H

L

1.5 Power Up/Down

Auto Cal

12-Bit

011

L

The ADC may be powered down at any time by taking the
PO pin HIGH or by the instruction input on 01 (see Tables IV
and V, and the Power Up/Down timing diagrams). When the
ADC is powered down in this way, the circuitry necessary for
an AID conversion is deactivated. The circuitry necessary
for digital I/O is kept active. Hardware power up/down is
controlled by the state of the PO pin. Software power-up/
down is controlled by the instruction issued to the ADC. If a
software power up instruction is issued to the ADC while a
hardware power down is in effect (PO pin high) the device
will remain in the power-down state. If a software power
down instruction is issued to the ADC while a hardware
power up is in effect (PO pin low), the device will power
down. When the device is powered down by software, it
may be powered up by either issuing a software power up
instruction or by taking PO pin high and then low. If the
power down command is issued during an AID conversion,
that conversion is disrupted. Therefore, the data output after
power up cannot be relied upon.

The number of clock pulses required for an 1/0 exchange
may be different for:the case when ~ is left low continuously vs the case when ~ is cycled. Take the I/O sequence detailed in Figure 5 (Typical Power Supply Sequence) as an example. The table below lists the number of
SCLK pulses required for each instruction:
i5SLow
Continuously

DID

AOC12130
and
AOC12132

Where X can be a logic high (H) or low (L).

If erroneous SCLK pulses desynchronize the communications, the simplest way to recover is by CYCling the power
supply to the device. Not being able to easily resynchronize
the device is a shortcoming of leaving ~ low continuously.

Instruction

01 Data

13SCLKs

8SCLKs

13SGLKs

13SCLKs

1.4 Analog Input Channel Selection
The data input on 01 also selects the channel configuration
for a particular AID conversion (see Tables II, '" and IV).

I/o

Sequence

DI

I

2

Cony N
12-Bit+Sign
t.lSB First
CHO

H

6 CCLK
Acquisition

,5

4

Data Out
without Sign

b

Cony N+ 1
16-Bit
t.lSB First

r..

Cony N+2
12-Bit
LSB First

r..

Cony N+3
12-Bit
LSB 'First

DO
TLlH/12079-33

FIGURE 6. Changing the ADC's Conversion ConfiguraUon

2-538

~----------------------------------------------------~~

c

Application Hints (Continued)
1.6 User Mode and Test Mode
An instruction may be issued to the ADC to put it into test
mode. Test mode is used by the manufacturer to verify complete functionality of the device. During test mode CHOCH7 become active outputs. If the device is inadvertently
put into the test mode with CS continuously low, the serial
communications may be desynchronized. Synchronization
may be regained by cycling the power supply voltage to the
device. Cycling the power supply voltage will also set the
device into user mode. If CS is used in the serial interface,
the ADC may be queried to see what mode it is in. This is
done by issuing a "read STATUS register" instruction to the
ADC. When bit 9 of the status register is high, the ADC is in
test mode; when bit 9 is low the ADC, is in user mode. As an
alternative to cycling the power supply, an instruction sequence may be used to return the device to user mode. This
instruction sequence must be issued to the ADC using CS.
The following table lists the instructions required to return
the device to user mode:
01 Data

Instruction
010 011

012 013 014 015 016 017

TEST MODE

H

X

X

X

H

H

H.

H

Reset
Test Mode
Instructions

L

L

L

L

H

H

H

L

L

L

L

L

H

L

H

L

L

L

L

L

H

L

H

H

USER MODE

L

L

L

L

H

H

H

H

Power Up

L

L

L

L

H

L

H

L

Set DO with
or without
Sign

H
or
L

L

L

L

H

H

L

H

Set
Acquisition
Time

H
or
L

H
or
L

L

L

H

H

H

L

Start
a
Conversion

H
or
L

H
or
L

H
or
L

H
or
L

L

H
or
L

H
or
L

H
or
L

After returning to user mode with the user mode instruction
the power up, data with or without sign, and acquisition time
instructions need to be resent to ensure that the ADC is in
the required state before a conversion is started.
1.7 Reading the Data Without Starting a Conversion
The data from a particular conversion may be accessed
without starting a new conversion by ensuring that the
CONY line is taken high during the I/O sequence. See the
Read Data timing diagrams. Table V describes the operation of the CONY pin.
2.0 DESCRIPTION OF THE ANALOG MULTIPLEXER
For the ADC12138, the analog input multiplexer can be configured with 4 differential channels or 8 single ended channels with the COM input as the zero reference or any combination thereof (see Figure 7). The difference between the
voltages on the VREF+ and VREF- pins determines the
input voltage span (VREF). The analog input voltage range is
oto VA + . Negative digital output codes result when VIN - >
VIN+. The actual voltage atVIN- orVIN+ cannot go below
AGND.
8 Single-Ended Channels
with COM
4 Differential
Channels
as Zero Reference

+(-)
-(+)
+(-)
-(+)

+(-)
-(+)
+(-)
-(+)
TL/H/12079-34

TL/H/12079-35

FIGURE 7
CHO, CH2, CH4, and CH6 can be assigned to the MUXOUT1 pin in the differential configuration, while CH1, CH3,
CH5, and CH7 can be assigned to the MUXOUT2 pin. In the
differential configuration, the analog inputs are paired as follows: CHO with CH1, CH2 with CH3, CH4 with CH5 and CH6
with CH7. The AlDIN1 and AlDIN2 pins can be assigned
positive or negative polarity.

x = Don't Care

2-539

o
....
N
....

~
C

o....
N
....

W

;;
C

o....
N
....

W
00

Application Hints (Continued)
With the single-ended multiplexer configuration CHO
through CH7 can be assigned to the MUXOUT1 pin. ,The
COM pin is always assigned to the MUXOUT2 pin. AlDIN1
is assigned as the positve input; AlDIN2 is assigned as the .
negative input. (See Figure 8) ..
,Differential
Configuration
CHO
CH2
CH4
CH6
CHI
CH3
CH5
CH7

...

Single-Ended
Configuration

-

MUx OUTI

... 1
... 1

MUx,. OUT2

CHO
CHI
CH2
CH3
CH4
',CH5
CH6
CH7

,

COM

2.1 Biasing for various Multiplexer Configurations
Figure 9 is.an examplE!,of biasi.rig the device for single-end-

ed operation. The sign bit is always low. The digital ou1put
range isO 0000 0000 0000 to a 1111 1111 1111 •.One LSB
is equallo 1 mV (4.1V/4096 LSBs).

...

....... -

~ OUTI

:...

....
MUX OUT2

TLJH/f2079-36

AlDINI and AlDIN2 can be assigned as the + or - input

The Multiplexer assignment tables for the ADC12130/2/8
(Tables II and III) summarize the aforementioned functions
for the different versions of AIDs.

TUH112079-37

AlDIN1 is + Input
. A/DIN2'is - input

FIGURE 8

ANA'LOG
INPUT
".VOLTAGE
RANGE
, OV TO 4.096V
(OV TO 2.5V)
12-BITS UNSIGNED

VA+

Av
ASSIGNED
(+l INPUT

ASSIGNED
INPUT

H

CHO
CHI
CH2

to
CH7

+5.0V
(+3.3Vl
Vo+

ADC1213X
COM

VREf + .......- -...,....-...- - -...--0 +4.096V
(+2.5Vl

VREf -

',.

- - LM4040-:-4.1

!

ANAtOG '
INPUT .<.
VOLTAGE >--4~------~-:---'
GROUND
REfERENCE
TUH/12079-38

FIGURE 9_ Single-Ended Biasing

2-540

~

C

Application Hints (Continued)
to an acquisition time of 10 clock periods, the input biasing
resistor needs to be 600n or less. Notice though that the
input coupling capaCitor needs to be made fairly large to
bring down the high pass corner. Increasing the acquisition
time to 34 clock periods (with a 5 MHz CCLK frequency)
would allow the 600n to increase to 6k, which with a 1 ",F
coupling capaCitor would set the high pass corner at 26 Hz.
Increasing R, to 6k would allow R2 to be 2k.

For pseudo-differential signed operation, the biasing circuit
shown in Figure 10 shows a signal AC coupled to the ADC.
This gives a digital output range of - 4096 to + 4095. With a
2.5V reference, as shown, 1 LSB is equal to 610 )LV. Although, the ADC is not production tested with a 2.5V reference, when VA + and Vo + are + 5.0V linearity error typically will not change more than 0.1 LSB (see the curves in the
Typical Electrical Characteristics Section). With the ADC set
VA+

ANALOG
INPUT
VOLTAGE
RANGE
OV TO S.OV
(OV TO 2.5V)
12-BITS SIGNED

>-I

Av
ASSIGNED
(+) INPUT

6001l
(DEPENDS ON
ACQUISITION

Rl
ASSIGNED
(-) INPUT

TI~E)

~
.....
~

C

o....
N

......
Co)

;;
o
....
....
N

+5.0V
(+3.3V)

Co)

c»

Vo+

CHB

N
....

C

CHD
CHI
CH2

to

o
....

ADC1213X

--1--....- ....-0 (+1.25V)
+2.SV

VREF + 1-.....- -....

COM

VREF DGND

LM9140-2.5
(LM4041AIZ-l.2)

AGND

ANALOG
INPUT
VOLTAGE )--4------.....;~---I
GROUND
REFERENCE
TL/H/12079-39

FIGURE 10. Pseudo-Differential Biasing with the Signal Source AC Coupled Directly into the ADC
An alternative method for biasing pseudo-differential operation is to use the + 2.5V from the LM9140 to bias any ampli-.
fier circuits driving the ADC as shown in Figure 11. The
value of the resistor pull·up biasing the LM9140-2;5 will depend upon the current required by the op amp biasing circuitry.
In the circuit of Figure 11 some voltage range is lost since
the amplifier will not be able to swing to +5V and GND
ANALOG INPUT
VOLTAGE
RANGE
OV TO S.OV
(OV TO 2.5V)
12-81TS SIGNED
ANALOG
INPUT
VOLTAGE

vA+

CHB
1 Mil
ASSIGNED
(-) INPUT

Fully differential operation is shown in Figure 13. One LSB
for this case is equal to (4.1V/4096) = 1 mV.

CHO
CHI
CH2

to

>-I

with a Single + 5V supply. Using an adjustable version of the
LM4041 to set the full scale voltage at exactly 2.048V and a
lower grade LM4040D-2.5 to bias up everything to 2.5V as
shown in Figure 12 will allow the use of all the ADC's digital
output range of -4096 to +4095 while leaving plenty of
head room for the amplifier. ..

+5.0V
(+3.3V)
Vo +

ADC1213X •
COM

VREF + t-~:-:-:"""':..-:-:--=-,":":"-:-.....-P--o + 2.5V
(+1.25V)

LM9140-2.5
DGND
ANALOG
INPUT
VOLTAGE
GROUND
REFERENCE

AGND

(LM4041AIZ-l.2)

)--t-------.----'
TL/H112079-40

FIGURE 11. Alternative Pseudo-Differential Biasing
2-541

fII

Application Hints (Continued)
'.

ANALOG
INPUT
VOLTAGE
RANGE
2.SV:l:2.04BV
12-BITS SIGNED

Av
ANALOG
INPUT
VOLTAGE

>1

ASSIGNED
(+) INPUT

VA+,

CHO
CHI
CH2
10
CHB'

+S.OV
VD+

+S.OV

!tAil
ASSIGNED
(-) INPUT

ADC1213X

I

VREF +

COM

LM4040D-2.5

I

-

I

I

I

2k

-

+2.04BV

I

VREF -

LM4041-ADJ
OGNO

AGND

ANALOG
INPUT
VOLTAGE
GROUND
REFERENCE
TUH/12079-41

FIGURE 12. Pseudo-Differential Biasing without the Loss of Digital Output Range

ANALOG
INPUT
VOLTAGE
RANGE
O.4SV TO 4.SSV
(O.4V TO 2.9V)

A.
•

.

"-/

CHO
CH2

ASSIGNED
(+) INPUT

or
CH6

~~-O+S.OV

>---...... CH4

FULLY DIFFERENTIAL
12-BIT PLUS SIGN

V'

(+3.'3V)

VD+ 1-......_ _....._ _..._-'

ADC1213X

ANALOG
CH I
INPUT
CH3
VOLTAGE >---~ CHS
RANGE
ASSIGNED
or
O.4SV TO 4.SSV
(-) INPUT CH7
(O.4V TO 2~9V)

--f-----+--o H.IV

VREF + I -....- -....

(+2.SV)

LM4040-4.1
(LM9140BYZ-2.S)

ANALOG
INPUT
VOLTAGE >----~~GROUND
REFERENCE

.......
TUH/12079-42

FIGURE 13. Fully Differential Biasing

2-542

»
c

Application Hints (Continued)

o....
VA

The difference in the voltages applied to the VREF+ and
VREF- defines the analog input span. (the difference be·
tween the voltage applied between two multiplexer inputs or
the voltage applied to one of the multiplexer inputs and ana·
log ground), over which 4095 positive and 4096 negative
codes exist. The voltage sources driving VREF+ or VREFmust have very low output impedance and noise. The circuit
in Figure 14 is an example of a very stable reference appropriate for use with the device.
YIN

....
~C
I\)

3.0 REFERENCE VOLTAGE

~

....o
....

I\)

~

~
C
o
....
....

~

t

O.ly,,+-O.5V

>=

+12V to +ISV

I\)

1,8kIl

~

CD
+12V to t15V

~"1 -=

2.46kIl
0.1%

VREf OUT
+4.096V

..........,..---1 >--+-_--t--+

3.S2kIl
0.1%

-=

*Tantalum

TlIH/12079-44

Tl/H/12079-43

FIGURE 15. VREF Operating Range

FIGURE 14. Low Drift Extremely
Stable Reference Circuit

4.0 ANALOG INPUT VOLTAGE RANGE

The ADC12130/2/B can be used in either ratiometric or absolute reference applications. In ratiometric systems, the
analog input voltage is proportional to the voltage used for
the ADC's reference voltage. When this voltage is the system power supply, the VREF+ pin is connected to VA + and
VREF- is connected to ground. This technique relaxes the
system reference stability requirements because the analog
input voltage and the ADC reference voltage move together. This maintains the same output code for given input conditions. For absolute accuracy, where the analog input voltage varies between very specific voltage limits, a time and
temperature stable voltage source can be connected to the
reference inputs. Typically, the reference voltage's magnitude will require an initial adjustment to null reference voltage induced full-scale errors.

The ADC12130/2/B's fully differential ADC generate a
two's complement output that is found by using the equation
shown below:
for (12-bit) resolution the Output Code =
(V,N+ - V'N-) (4096)
(VREF+ - VREF )
Round off to the nearest integer value between -4096 to
4095 if the result of the above equation is not a whole number.
Examples are shown in the table below:

Below are recommended references along with some key
specifications.
Output
Voltage
Tolerance

Temperature
Coefficient

LM4041CI-Adj

±0.5%

±100ppm1'C

LM4040AI-4.1

±0.1%

±100ppm/oC

LM9140BYZ-4.1

±0.5%

±25ppml'C

LM368Y-5.0

±0.1%

±20ppml'C

Adjustable

±2ppm/oC

Part Number

Circuit of Figure 14

The reference voltage inputs are not fully differential. The
ADC12130/2/B will not generate correct conversions or
comparisons if VREF+ is taken below VREF-' Correct conversions result when VREF+ and VREF- differ by 1V and
remain, at all times, between ground and VA +. The VREF
common mode range, (VREF+ + VREF-)/2 is restricted to .
(0.1 X VA+) to (O.BX VA+). Therefore, with VA+ = 5V
the center of the reference ladder should not go below 0.5V
or above 3.0V. Figure 151. a graphic representation of the
voltage restrictions on VREF+ and VREF-'

2-543

VREF+

VREF-

V,N+

V'N-

Digital
Output
Code

+2.5V

+1V

+1.5V

OV

0,1111,1111,1111

+4.096V

OV

+3V

OV

0,1011,1011,1000

+4.096V

OV

+4.096V

OV

+2.499V +2.500V 1,1111,1111,1111
OV

+4.096V 1,0000,0000,0000

5.0 INPUT CURRENT
At the start of the acquisition window (tAl a charging current
flows into or out of the analog input pins (AlDIN1 and
A/DIN2) depending on the input voltage polarity. The analog input pins are CHO-CH7 and COM when AlDIN1 is tied
to MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak
value of this input current will depend on the actual input
voltage applied, the source impedance and the internal multiplexer switch on resistance. With MUXOUT1 tied to
AlDIN1 and MUXOUT2 tied to AlDIN2 the internal multiplexer switch on resistance is typically 1.6 kO. The AlDIN1
and AlDIN2 mux on resistance is typically 7500.

•

CD

....
....
U
C")

C\I

C

~
....
....
U
C")

C\I

C

~....
....
C\I

(.)

C

.e:,......~CTS

RS232
Interface
Connector

~

+4.096V

+5V

1A1A74C74
TLlH/12079-46

Not.: VA +, Vo+. and VAEF+ on the ADC12138 each have 0.01 I'F and 0.1 I'F chip caps, and 10 I'F tantalum caps. All logic devices are bypassed with 0.1 I'F
caps.

The assignment of the RS232 port is shown below

B7
COM1

I Input Address I 3FE
I Output Address I 3FC

B6

B5

B4

B3

B2

B1
X

X

RTS

DTR

X

X

X

CTS

X

X

X

X

X

0

X

X

A sample program, written in Microsoft QuickBasic, is
shown on the next page. The program prompts for data
mode select instruction to be sent to the AID. This can be
found from the Mode Programming table shown earlier. The
data should be entered in "1"s and "O"s as shown in the
table with 010 first. Next the program prompts for the number of SCLKs required for the programmed mode select instruction. For instance, to send all "O"s to the AID, selects
CHO as the +input, CH1 as the -input, 12-bit conversion,
and 13-bit MSB first data output format (if the sign bit was
not turned off by a previous instruction). This would require
13 SCLK periods since the output data format is 13 bits. The
part powers up with No Auto Cal, No Auto Zero, 10 CCLK

BO

Acquisition Time, 12·bit conversion, data out with sign, pow·
er up, 12· or 13·bit MSB First, and user mode. Auto Cal,
Auto Zero, Power Up and Power Down instructions do not
change these default settings. Since there is no CS signal to
synchronize the serial interface the following power up se·
quence should be followed:
1. Run the program
2. Prior to responding to the prompt apply the power to the
ADC12138
3. Respond to the program prompts
It is recommended that the first instruction issued to the
ADC12138 be Auto Cal (see Section 1.1).

2·546

c»

Application Hints (Continued)

o
....

'variables DOL=Data Out word length, DI=Data string for AID DI input,
DO=A/D result string
'SET CS# HIGH
OUT &H3FC, (&H2 OR INP (&H3FC)
OUT &H3FC, (&HFE AND INP(&H3FC)
OUT &H3FC, (&HFD AND INP (&H3FC)

'set RTS HIGH
'SET DTR LOW
'SET RTS LOW

OUT &H3FC, (&HEF AND INP(&H3FC»
'set B4 low
10
LINE INPUT "DI data for ADC12l38 (see Mode Table on data sheet)"; DI$
INPUT "ADC12l38 output word length (12,13,16 or 17)"; DOL
20

N
....

Co)

.....
(:)

»
c
o....

....
N

Co)

N
.....

»
c
o
....
N
....

Co)

CO

'SET CS# HIGH
OUT &H3FC, (&H2 OR INP (&H3FC)
OUT &H3FC, (&HFE AND INP(&H3FC)
OUT &H3FC, (&HFD AND INP (&H3FC)

'set RTS HIGH
'SET DTR LOW
'SET RTS LOW

'SET CS# LOW
OUT &H3FC, (&H2 OR INP (&H3FC)
OUT &H3FC, (&Hl OR INP(&H3FC)
OUT &H3FC, (&HFD AND INP (&H3FC)

'set RTS HIGH
'SET DTR HIGH
'SET RTS LOW
'reset DO variable
'SET DTR HIGH
'SCLK low

DO$=""
OUT &H3FC, (&Hl OR INP(&H3FC)
OUT &H3FC, (&HFD AND INP(&H3FC»
FOR N = 1 TO 8
TempS = MID$(DI$, N, 1)
IF TempS="O" THEN
OUT &H3FC, (&Hl OR INP(&H3FC»
ELSE OUT &H3FC, (&HFE AND INP(&H3FC»
END IF
OUT &H3FC, (&H2 OR INP(&H3FC»
IF (INP(lH3FE) AND 16) = 16 THEN
DO$ = DO$ + "0·
ELSE
DO$ = DOS + "1"
END IF
OUT &H3FC, (&Hl OR INP(&H3FC)
OUT &H3FC, (&HFD AND INP(&H3FC»
NEXT N
IF DOL> 8 THEN
FOR N=9 TO DOL
OUT &H3FC, (&Hl OR INP(&H3FC)
OUT &H3FC, (&HFD AND INP(&H3FC»
OUT &H3FC, (&H2 OR INP(&H3FC»

'out DI
'SCLK high

'Input DO
'SET DTR HIGH
'SCLK low

'SET DTR HIGH
'SCLK low
'SCLK high

IF (INP(&H3FE) AND &H10) = &H10 THEN
DO$ = DOS + "0"
ELSE
DO$ = DO$+"l"
END IF
NEXT N
END IF
OUT &H3FC, (&HFA AND INP(&H3FC»
FOR N = 1 TO 500
NEXT N
PRINT DOS
INPUT "Enter ·C" to oonvert else "RETURN" to alter DI data"; sS
IF sS = ·C" OR sS = "c" THEN
GOTO 20
ELSE
GOTO·10
END IF
END
2-547

'SCLK low and DI high

U) r-----------------~--------------------------------------------------------~

C'II
C'II

....
g
~

tfJ

Nat ion a I S e m i con d

uc~ 0 r

U)

o

.... ADC1205/ADC1225 12-Bit Plus Sign
C'II

(.)

c

c:c:

JLP Compatible AID Converters

General Description

Key Specifications

The ADC1205 and ADC1225 are CMOS, l2-bit plus sign
successive approximation AID converters. The 24-pin
ADC1205 outputs the l3-bit data result in tWo 8-bit bytes,
formatted high-byte first with sign extended. The 28-pin
ADC1225 outputs a l3-bit word in parallel for direct interface to a l6-bit data bus.

• Resolution-12 bits plus sign
• Linearity Error-± 1 LSB
• Conversion,Time-l00 P.s

Negative numbers are represented in 2's complement data
format. All digital signals are fully TTL and MaS compatible.

• Compatible with all p.Ps '
• True differential analog voltage inputs
II OV to 5V analog voltage range with 'single 5V supply
II TTL/MaS input/output compatible
iii Low power-25 mW max
• Standard 24-pin or 28-pin DIP

Features

A unipolar input (OV to 5V) can be accommodated with a
single 5V supply, while a bipolar input (-5V to +5V) requires the addition of a 5V negative supply.
The ADC1205C andADC1225C have a maximum non-linearity of 0.0224% of Full Scale.
.

Connection and Functional Diagrams
Dual-ln·Llne Package
y-

"

DlBITAl.Ycc

23

DB7IDB12

ANALDBBHD

"21

086/0812

YREF

211

08410812

"11

083/0811

17

I.

DBlIDB.

15

Ilii'

13

STATlJS

VJNf-1
ViNI+)

ANALOBYcc

ADe12115

Yo.
eLKIN

\ViI

CI

10

1111

"

OI1lITALGNO

I
I

085/0812

OB2/DB10-BYST

DBD/DBB

,.

12

OGNO

rr------

~N(+I

...

II

AIlAL08Vcc

"""225

eLKIN

!iii

mr

I

I

I

SUCCESSIVE
APPROXIMATION
REGISTER

BYTE
SEQUENCER

I

1

TRI-STATE"
OUTPUT

AND

!:,~~

LATCH

ONLY

I

LADDER

I
I

DECODER

AND

L~

___________

I

~--~

20

C!

10

III

11

DlorrALBIID

"13

Iii'f

Z1

I

I

I

I
I

"'0

....I

,

I

23

...

BUYOUT

... ""
. ......
. ......,
...
11

Vee

-~

'

I

II

ANALOaOND

DIGITAL
STATUS

I

Tl/H/5676-1

DIJITALVa:

VlI,+)

READY
DUT

I

~N(-I

'l1li-1

iiii Wii

I

Dual·ln·Llne Package
y-

cs

CONTRDl
AND
TIMING

I
I
I
Vos

1lEA0,y,OUT

Top View

ClK
IN

"
"

17

AGNO

.B4

VREF

Vee

...

TLlH/5676-3

" '"'10
"

,.

Top View

ANALOG

DIS

See Ordering Information
TLlH/5676-2

2-548

l>

Absolute Maximum Ratings

c

Operating Conditions (Notes 1 & 2)

(Notes 1 & 2)

Temperature Range
ADC1205CCJ, ADC1225CCD
ADC1205CCJ-1, ADC1225CCD-1
Supply Voltage (DVee and AVeC>
Negative Supply Voltage (V-)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (DVee and AVeC>
6.5V
Negative Supply Voltage (V-)
-15VtoGND
Logic Control Inputs
-0.3Vto +15V
Voltage at Analog Inputs
(V-)-0.3V to Vee+0.3V
[VIN(+), VIN(-)l
-0.3V to (Vee+0.3)V
Voltage at All Outputs, VREF, Vas
Input Current per Pin
±5mA
Input Current per Package
±20mA
Storage Temperature Range
- 65·C to + 150·C
Package Dissipation at TA = 25·C
B75mW
300·C
Lead Temp. (Soldering, 10 seconds)
ESD Susceptibility (Note 12)
BOOV

TMIN,;:TA,;:TMAX
-40·C,;:TA';: +B5·C
0·C,;:TA,;:70·C
4.5 Voe to 6.0 Voe
-15VtoGND

Electrical Characteristics

ADC1205CCJ, ADC1225CCD
Conditions

Typ
(Note 8)

Design
Tested
Limit
Limit
(Note 9) (Note 10)

ADC1205CCJ-1, ADC1225CCD·1
Typ
(Note 8)

Limit
Units

Tested
Limit
(Note 9)

Design
Limit
(Note 10)

±1

±1

LSB
LSB

CONVERTER CHARACTERISTICS
Linearity Error
Unipolar Input
ADC1205CCJ, ADC1225CCD
Range
ADC1205CCJ-1, ADC1225CCD-1 (Note 11)

±1

Unadjusted Zero Error

Unipolar Input
Range

±2

±2

±2

LSB

Unadjusted Positive and Negative
Full-Scale Error

Unipolar Input
Range

±30

±30

±30

LSB

Negative Full-Scale Error

Unipolar Input
Range, Full
Scale Adj. to
Zero

±y.

LSB

±2

±2

LSB
LSB

±y.

Linearity Error
Bipolar Input
ADC1205CCJ, ADC1225CCD
Range
ADC1205CCJ-1, ADC1225CCD-1 (Note 11)

±2

Unadjusted Zero Error

Bipolar Input
Range

±2

±2

±2

LSB

Unadjusted Positive and Negative
Full-Scale Error

Bipolar Input
Range

±30

±30

±30

LSB

Negative Full-Scale Error

Bipolar Input
Range, Full
Scale Adj. to
Zero

±2

±2

±2

LSB

6

15

6

15

ppml"C

Maximum Offset Temperature
Coefficient

0.5

1.5'

0.5

1.5

ppml"C

Minimum VREF Input Resistance

4.0

2

4.0

2

2

kO

Maximum VREF Input Resistance

4.0

8

4.0

B

8

kO

Maximum Gain Temperaturei
Coefficient

N

<:)

U1
.......

l>

c
o
....
N
N

U1

The following specifications apply for DVee = AVec = 5V, VREF = 5V, felK = 1.0 MHz, V- = -5V for bipolar input range, or
V- = GND for unipolar input range unless otherwise specified. Bipolar input range is defined as -5.05V ,;: VIN(+) ,;: 5.05V;
-5.05V ,;: VIN(-) ,;: 5.05Vand IVIN(+) - vIN(-)1 ,;: 5.05V. Unipolar input range is defined as -0.05V ,;: VIN(+) ,;: 5.05V;
-0.05V ,;: VIN(-) ,;: 5.05V and IVIN(+) - vIN(-)1 ,;: 5.05V. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ
= 25·C (Notes 3, 4, 5, 6, 7).

Parameter

o
....

2-549

Electrical Characteristics (Continued)
The following specifications apply for DVCC = AVec = 5V. VREF = 5V. felK = 1.0 MHz. V- = -5V for bipolar input range. or
V- = GND for unipolar input range unless otherwise specified. Bipolar input range is defined as -5.05V s: VIN(+) s: 5.05V;
-5.05V s: VIN(-) s: 5.05V,and IVIN(+) - vIN(-)1 s: 5.05V. Unipolar input range is defined'as -0.05V 'S: VIN(+) s: 5.05V;
-0.05V s: VIN(-) s: 5.05V and IViN(+) - vIN(-)Is: 5.05V. Boldface limits apply from TMIN to TMAX; all other limits TA'=: TJ
=: 25'C (Notes 3. 4. 5. 6. 7).
ADC1205CCJ, ADC1225CCD
Parameter

Conditions

Typ
(Note 8)

Tested
Limit
(Note 9)

ADC1205CCJ-1, ADC1225CCD"1

,Design
Typ
Umlt
, (Note 8)
(Note 10)

Tested
Limit
(Ncite 9)

Design
Limit
(Note 10)

LlmH
Units

GND-0.05

GND-0.05

V

CONVERTER CHARACTERISTICS (Continued)
Minimum Analog Input
Voltage

Maximum Analog Input
Voltage.

Unipolar Input
Range
Bipolar Input
Range
Unipolar Input
Range
Bipolar Input
Range

DC Common-Mode Error
Power Supply Sensitivity

GND-0.05

-Ve- 0.05 -Vee""'O.05 ' V

-Vee- 0•05
Vee+ O•05

.

Vee + 0.05
±Ya

±%

±Ya

Vee + 0.05

Vee + 0.05

V

Vee + 0.05

Vee + 0.05

V

±%

±%

LSB

±%
±%

±%
±%

LSB
LSB

±%

±%

l:SB

V

AVcc=DVe,e=
5V±5%.
V-=-5V±5%

Zero Error
Positive and Negative
Full-Scale Error
Linearity Error

±%
±%

,

±%

DIGITAL AND DC CHARACTERISTICS
VIN(1). logical "1" Input
Voltage (Min)

Vee=5.25V.
All Inputs except
ClKIN

2.0

2.0

2.0

VIN(O). logical "0" Input
Voltage (Max)

Vee = 4.75V.
All Inputs except
ClKIN

0.8 '

0.8

',0.8

IIN(1). logical"1'~ Input
Current (Max)

IlIN=5V

0.005

1

0.005

1

/LA

IIN(O). logical "0" Input
Current (Max)

VIN=OV

-0.005

-1

-0.005

-1

/LA

VT+ (Min). Minimum J;>ositiveGoing Threshold Voltage

ClKIN

3.1

2.7

3.1

2.7

2.7

V

VT+ (Max). Maximum Positive- ClKIN
Going Threshold Voltage

3.1

3.5

3.1

3.5

3.5

V

VT- (Min). Minimum Negative- ClKIN
Going Threshold Voltage

1.8

1.4

1.8

1.4

1.4

V

VT- (Max). Maximum Negative- ClKIN
Going Threshold Voltage

1.8

2.1

1.8

2.1

2.1

V

VH(Min). Minimum Hysteresis
[VT+ (Min) - VT- (Max)]

ClKIN

1.3

0.6

1.3

0.6

0.6

V

VH(Max). Maximum Hysteresis
[VT+(Max)-VT-(Mln)]

ClKIN

1.3

2.1

1.3

' ,2.1

2.1

'V

2-550

c.

V

~

C

Electrical Characteristics (Continued)
The following specifications apply for DVCC = AVCC = SV, VREF = SV, fClK = 1.0 MHz, V- = -'-SV for bipolar input range, or
V- = GND for unipolar input range unless otherwise specified. Bipolar input range is defined as -S.OSV :s: VIN(+) :0: S.OSV;
-S.OSV :0: VIN(-) :0: S.OSV and IVIN(+) - vIN(-)1 :0: S.OSV. Unipolar input range is defined as -o.OSV :0: VIN(+) :0: S.OSV;
-O.OSV:O: VIN(-) :0: S.OSV and iVlN(+) - vIN(-)1 :0: S.OSV. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ
= 2S'C (Notes 3, 4, S, 6, 7).
ADC1205CCJ, ADC1225CCD
Parameter

Conditions

Typ
(Note 8)

Tested Design
Limit
Limit
(Note 9) (Note 10)

ADC1205CCJ-1, ADC1225CCD-1
Typ
(Note 8)

Tested
Limit
(Note 9)

Limit
Design
Units
Limit
(Note 10)

DIGITAL AND DC CHARACTERISTICS (Continued)
VOUT(l), Logical "1" Output
Voltage (Min)

Vcc=4.7SV
IOUT= -360,..A
IOUT= -10,..A

VOUT(O), Logical "0" Output
Voltage (Max)

Vcc=4.7SV
IOUT=1.6mA

lOUT, TRI-STATE Output Leakage VOUT=OV
Current (Max)
VOUT=SV

2.4
4.5

2.4
4.S

2.4
4.5

V
V

0.4

0.4

0.4

V

-0.Q1
0.01

-3
3

-0.Q1
0.01

-0.3
0.3

-3
3

,..A
,..A
rnA

ISOURCE, Output Source Current
(Min)

VOUT=OV

-12

-6.0

-12

-7.0

-6.0

ISINK, Output Sink Current (Min)

VOUT=SV

16

8.0

16

9.0

8.0

mA

1

3

1

2.S

3

rnA

DlcC, DVCC Supply Current (Max) fClK= 1 MHz, CS= 1
AICC, AVcC Supply Current (Max) fClK= 1 MHz, cs= 1

1

3

1

2.S

3

rnA

1-, V- Supply Current (Max)

10

100

10

100

100

,..A

fClK= 1 MHz, CS= 1

AC Electrical Characteristics
The following specifications apply for DVCC=AVcc=S.OV, t r =tf=20 ns and TA=2S'C unless otherwise specified.
Parameter

Conditions

Typ
(Note 8)

Tested
Limit
(Note 9)

1.0
1.0

0.3
1.S

Design
Limit
(Note 10)

Limit
Units

fClK, Clock Frequency

MIN
MAX

Clock Duty Cycle

MIN
MAX

40
60

%
%

TC, Conversion Time

MIN
MAX
MIN
MAX

108
109
108
109

1/fClK
1lfClK
,..s
,..s

fClK = 1.0 MHz
fClK= 1.0 MHz

MAX

MHz
MHz

220

3S0

ns

tACC, Access Time (Delay from
Falling Edge of RD to
Output Data Valid) (Max)

Cl =100 pF

210

340

ns

tlH, tOH, TRI-STATE Control (Delay
from Rising Edge of RD to
Hi-Z State) (Max)

Rl =2k, Cl =100 pF

170

290

ns

tPDJ,.READYOUTj' RD or WR to
RE DYOUT Delay (Max)

2S0

400

ns

tpD(INTj,RD or WR to Reset of INT
(Max)

2S0

400

ns

tW(WR)l, WR Pulse Width

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating ratings.
Note 2: All voltages are measured with respect to ground, unless otherwise specified.
Note 3: A parasitic zener diode exists internally from AVec and DVcc to ground. This paras~tic zener has a typical breakdown voltage of 7 Vee.

2-SS1

o......
N

o

UI
.....

~

c

n
......

N
N
UI

II)

N

....
o

,N

c

AC Electrical Characteristics

(Continued)
Note 4: Two on-chip diodes ara lied 10 each analog inpul as shown below.

'DIGITAL Vee

~o

N
..-

g
c(

DR VJNI+I
VJNh I

r ....-r-..--I~ TO INTERNAL CIRCUITRY

TL/H/5676-4

Errors in Ihe AID conversion can occur If Ihese diodes are forward biased more than 50 mY. This means Ihat if AVec and DVcc are minimum (4.75 Vocl and V- is
minimum <'':'4:75Vocl, full·scale musl be ,; 4,8VoC.
"
Note ,5: A diode exists between analog Vec and digital Vo-

I

Avee:nl TO INTERNAL CIRCUITRY ,
TO INTERNAL CIRCUITRY
DVee
,

40

I

!
I
I

TL/H/5676-2D

To guaranlee accuracy, il is required Ihallhe AVcc and DVcc be connected together 10 a power supply with separate bypass filters at each Vee pin.
No" 6: A'dlode exists between analog ground and digital ground.

A~ALOG GROUND ~ TO INTERNAL CIRCUIT"Y
DIGITAL GROUND

~

TO INTERNAL CIRCUITRY

TUH/S676-2t

To guarantee accuracy, It Is required that the analog ground and digital ground be connected together externally.
Note 7: Accuracy is guaranteed at fCLK=t.O MHz. At higher clock frequencies accuracy may degrade.
Note 8: Typicals are at 2S'C and represent most likely parametric norm.
Note 9: Testad and guaranteed to National's AOOL (Average Outgoing Quality Level).
Note 10: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 11: Linearity error is defined as the deviation of the analog value, expressed In LSBs, from the straight line which passes through positive full scale and zero,
alter adiusting zero erroi. (See Figuf9s Ib and Ie).
Note 12: Human body mode!; 100 pF di~arged through a 1.5 kIl resistor.

(4095) 0,1111,1111,1111
(4094) 0,1111,1111,1110

POSmYE
FULL·SCALE
TRANSITION

1,0000,0000,0001 (-4095)
I,DDDD,ODDD,DDDD (-4096)

ANALOG INPUT VOLTAGE [VINI +1- VINHI

FIGURE 1a. Transfer Characteristic

2·552

TL/H/5676-8

~

C

...o

o
N

.....
U'I

~

...
C

o

~

U'I

-3 LSB

OUTPUT COOE

(FROM - 4091 TO + 4095)
TUH/5676-22

FIGURE 1b. Simplified Error Curve vs. Output Code Without Zero and Fullscale Adjustment

+3 LSB
+2 LSB

NEGATIVE

POSITIVE

FULLSCALE

UNEARITY ERROR

ERROR

+1 LSB

FULLSCALE

ERROR

-1 LSB

-2 LSB

-3 LSB
OUTPUT CODE
(FROM -409& TO +4095)
TL/H/5676-23

FIGURE 1c. Simplified Error Curve vs. Output Code after Zero/Fullscale Adjustment
Vee

....-1---.... ~~~T

IIIJ

RL

Vee ----i~:::::-­

iiii
GND

VoH ---~!II
DATA OUTPUT

':"

GNO - - - -

#
Vee

Iiii

Vee
L

Vee

DATA
OUTPUT

--tJir'::::::--

iiii
GND

CL

':" I

Vee

_toH~

OATAOUTPUT
VoL _ _ _ _.3 10%
TUH/5676-7

FIGURE 2. TRI-5TATE Test Circuits and Waveforms

2·553

~

...
g
N
N

i...
~

r---------------------------------------------------------------------------------,
Timing Diagrams
CLKlN

~

--u-u-u-u-u
I-T-I

~

-------.,~~____J!r---\.,~.____JI

,.-~--""'I"I

,~_____JI

~~

II

I
109T

II

INf
liiI

a''''

II

DBS-------------------~---~-----~----HIGH BYTE ON ADCI205
13-BIT OATA ON ADC1225

LOW BYTE DN ADCI2D5
13·BIT OATA ON ADCI225
TLIHI5676-15

FIGURE 3. Timing Diagram

TLlHI5676-13

FIGURE 4. Ready Out

TLIH15676-14

FIGURE 5. Data Out

2-554

l:o
C
0

"1NQ SZZl:lDVlID.:I

~

u
~

g

g

....

;=

;.

e e e ;;
~

~

e

~

~

~
g

~

g

'",

N
0
U1

~

iii

g

.....
l:o
c

~

;::!

....

0

N
N
U1

E
f!

...

til

...C
CJ

o

iii
OJ
c

o
~

r".-----

I"

C
:::I
II..

I~

cD
UJ

a:

~

CJ

iL

fII
r----~

:I
I

r-~r-+---+-------~~

~

r-

il;:1
:;1
:

-:"

~I

I
I

I
I

I
I

I

I
I
I
I
I
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~:

1

"I
0

ffi I

ill I

>:1
~I

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I
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I

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:

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!.

2-555

-;

7

! I

i

§!

I

"'
r---------------------------------------------------------------------------------,
N
N
.... Functional Description
o
c

~
....~
o

c

CC

Setting CC enables the UPDATE LOGIC [12]. This logic
controls the transfer of data from the SAR LOGIC to the
OUTPUT LATCH [6] and resets the internal logic in preparation for a new conversion. This means that when EOC
goes high, a new conversion can be immediately started
since the internal logic has already been reset. In the same
way, data is transferred to the OUTPUT LATCH prior to issuing an interrupt. This assures that data can be read immediately after INT goes low.

1.0 THE AID CONVERSION

1.1 STARTING A CONVERSION
When using the ADC1225 or ADC1205 with a microprocessor, starting an A-to-D conversion is like writing to an external memory location. The WR and CS lines are used to start
the conversion. The simplified logic (Figure 6) shows that
the falling edge of WR with CS low clocks the D-type flipflop and initiates the conversion sequence. A new conversion can therefore be restarted before the end of the previous sequence. INT going low indicates the conversion's
end.

2.0 READING THE AID
The ADC 1225 makes all thirteen bits of the conversion
result available in parallel. Taking CS and RD low enables
the TRI-STATE® output buffers. The conversion result is
represented in 2's complement format.

1.2 THE CONVERSION PROCESS (Numbers designated
by [] refer to portions of Flgur:e 6.)
The SARS LOGIC [2] controls the A-to-D conversion process. When 'sars' goes high the clock (clk) is gated to the
TIMING GENERATOR [9]. One of the outputs of the TIMING GENERATOR, Tz, provides the clock for the Successive Approximation Register, SAR LOGIC [5]. The Tz clock
rate is Va of the CLK IN frequency.
Inputs to the 12-BIT DAC [II] and control of the SAMPLED
DATA COMPARATOR [10] sign logic are provided by the
SAR LOGIC. The first step in the conversion process is to
set the sign to positive (logic '0') and the input of the DAC to
000 (HEX notation). If the differential input, VIN(+)-VIN(-),
is positive the sign bit will remain low. If it is negative the
sign bit will be set high. Differential inputs of only a few
hundred microvolts are enough to provide full logic swings
at the output of the SAMPLED DATA COMPARATOR.
The sign bit indicates the polarity of the differential input. If it
is set high, the negative input must have been greater than
the positive input. By reversing the polarity of the differential
input, VIN(+) and VIN(-) are interchanged and the DAC
sees the negative input as positive. The input polarity reversal is done digitally by changing the timing on the input sampling switches of the SAMPLED DATA COMPARATOR.
Thus, with almost no additional circuitry, the AID is extended from a unipolar 12-bit to a bipolar 12-bit (12-bit plus sign)
device.
After determining the input polarity, the conversion proceeds with the successive approximation process. The SAR
LOGIC successively tries each bit of the 12-BIT DAC. The
most significant bit (MSB), Bl1 ," has a weight of 112 of VREF.
The"next bit, Bl0, has a weight of % VREF. Each successive
bit is reduced in weight by a factor of 2 which gives the least
significant bit (LSB) a weight of 1/4096 VREF.

The ADC1205 makes the conversion result available in two
eight-bit bytes. The output format is 2's complement with
extended sign. Data is right justified and presented high
byte first. With CS low and STATUS high, the high byte
(DBI2-DB8) will be enabled on the output buffers the first
time RD goes low. When RD goes Iowa second time, the
low byte (DB7-DBO) will be enabled. On each read operation, the 'byst' flip-flop is toggled so that on successive
reads alternate bytes will be available on the outputs. The
'byst' flip-flop is always reset to the high byte at the end of a
conversion. Table 1 below shows the data bit locations on
the ADC1205.
The ADC1205's STATUS pin makes it possible to read the
conversion status and the state of the 'byst' flip-flop. With
RD, STATUS and CS low, this information appears on the
data bus. The 'byst' status appears on pin 18 (DB2/DB10).
A low output on pin 18 indicates that the next data read will
be the high byte. A high output indicates that the next data
read will be the low byte. A high status bit on pin 22 (DB61
DBI2) indicates that the conversion is in progress. A high
output appears on pin 17 (DB1/DB9) when the conversion
is completed and the data has been transferred to the output latch. A high output on pin 16 (DBO/DB8) indicates that
the conversion has been completed and the data is ready to
read. This status bit is reset when a new conversion is initiated, data is read, or status is read. When reading status or a
conversion result, STATUS should always change,states at
least 600 ns before RD goes low. If the conversion status
information is not needed, the STATUS pin should be hardwired to V+. Table 2 summarizes the meanings of the four
status bits.
TABLE I. Data Bit Locations, ADC1205

When the MSB is tried, the comparator compares the DAC
output, VREF/2, to the analog input. If the analog input is
greater than VREF/2 the comparator tells the SAR LOGIC to
set the MSB. If the analog input is less than VREF/2 the
comparator tells the SAR LOGIC to reset the MSB. On the
next bit-test the DAC output will either be % VREF or %
VREF depending on whether the MSB was set or not. Following this sequence through for each successive bit will
approximate the analog input to within I-bit (one part in

HIGH BYTE DB12 DB12 DB12 DB12 DBII DB10 DB9 DB8

TABLE II. Status Bit Locations and Meanings
Status
Bit
Location

Status
Bit

DB6

SARS

"High" indicates that
the conversion is in
progress

DB2

BYST

"Low" indicates that
the next data read is
the high byte.
"High" indicates that
the next data read is
the low byte

4096). '
On completion of the LSB bit-test the conversion-complete
flip-flop (CC) is set, signifying that the conversion is finished.
The end-of-conversion (EOC) and interrupt (INn lines are
not changed at this time. Some internal housekeeping tasks
must be completed before the outside world is notified that
the conversion is finished.

2-556

Meaning

Condition to
Clear Status
Bit

Status write
or toggle it
with data
read

~
o.....
N

Functional Description (Continued)
TABLE II. Status Bit Locations and Meanings
(Continued)
Status
Status
Bit
Bit
Location
DB1

DBO

EOC

~

Condition to
Clear Status
Bit

Meaning

"High" indicates that
it is the end of the
conversion and the
data is ready to read

.-

iiii oRWii

"High" indicates that
the conversion is
completed and data is
transferred to the
output latch.

INT

\~--------~
-31/2T

I

~EAOY

-----+-'1'1-

OUT

(PD(READY OUT) -

3.0 INTERFACE
3.1 RESET OF INTERRUPT

-

tpD(READY OUT)

TLlH/5676-10

3.3 RESETTING THE AID
All the internal logic can be reset, which will abort any conversion in process and reset the status bits. The reset function is achieved by performing a status write (CS, WR and
STATUS are low).

3,2 READY OUT

3.4 ADDITIONAL TIMING AND INTERFACE OPTIONS

To simplify the hardware connection to high speed microprocessors, a READY OUT line is provided. This allows the
A-to-D to insert a wait state in the ,.,.P's read cycle. The
equivalent circuit and the timing diagram for READY OUT is
shown in Figures 1 and 8.

ADC1225
1. WR and RD can be tied together with CS low continuously or strobed. The previous conversion's data will be
available when the WR and RD are low as shown below.
One drawback is that, since the conversion is started on the
falling edge and the data read on the rising edge of WR/RD,
the first data access will have erroneous information depending on the power-up state of the internal output latches.

CS'RO~
CS'WR
READY OUT

CC

If the WR/RD strobe is longer than the conversion time,
INTR will never go low to signal the end of a conversion.
The conversion will be completed and the 'output latches will
be updated. In this case the READY OUT signal can be
used to sense the end of the conversion since it will go low
when the output latches are being updated.

TL/H/5676-9

FIGURE 7. READY OUT Equivalent Circuit

cs

S

LJ
,
,"

Rii

INTR

TC

LJ
I:

OATA
(080-0812)

.
I
I

I

I

I

I

I
I

I

I
I

I
I

I

I

I

I

'11

'11
(

LJ
I
I

I

I

I

LJ

I

I

I

I

I

I

I

REAOYOUT

C

o
.....
N

FIGURE 8. READY OUT Timing Diagram

INT goes low at the end of the conversion and indicates that
data is transferred to the output latch. By reading data, INT
will be reset to high on the leading edge of the first read (RD
going low). INT is also reset on the leading (falling) edge of
WR when starting a conversion.

'iVR

:J>

N
UI

cc

Data read or
status read
or status
write

CI

UI
.....

)

(

)
TL/H/5676-24

FIGURE 9

2-557

II

U)

N

N
.,..

g

....C
:g
N
.,..

g
C

r---------------------------------------------------------------------------------,
Functional Description (Continued)
cs

~L..__ _ _ _ _ _ _ _ _ _

Wi!

__II ____________ _

~
I

f

Rii
INTR .

U

READY OUT
I

DATA
(080-0812)

(

OLD DATA

I

~
I

Te

I.

TUH/5676-25

FIGURE 10

cs-,
Wi!lI.
I

LJ
Te-------:

LJ

Rii
INTR

READY OUT

'Il

DATA
(080-0812)

c:::::>
TUH/5676-26

FIGURE 11

cs

-----------------------------------------------

L...J
Rii

----------------------------------------

u

READY OUT

DATA - - - - - - - - - - - - - - - - _ , . - - - - - - - - - (080-0812)
OLD DATA
,;.,NEW",;,;..;DA,;.,t;;,;A_ _ __

X\.___

TUH/5876-27

FIGURE 12

2-558

J>

Functional Description

c

o
....

(Continued)

Cs

N

o

U1

........

ViR

'.

,
,
,I
,
,
,I
,
,
,

R5
INTR

DATA
(DBO-DBI2)

..,

Te

N
N
U1

,

,
,
,
,
,
,

LJ
X

READY OUT

J>

c
o....

11,

11,

LJ
X

OLD DATA

NEW DATA
TL/H/5676-28

ADe1225
-

cs

1
6

.! 74C

rt> -b+_

RD

INTR

ViR

fl4-+DATA
(DBO-D812)

READY OUT

TLlH/5676-29

FIGURE 13
When using this method of conversion only one strobe is
necessary and the rising edge of WR/RD can be used to
read the current conversion results. These methods reduce
the throughput time of the conversion since the RD and WR
cycles are combined.

3. Tying CS and RD low continuously and strobing WR to
initiate a conversion will also yield valid data. The INTR will
never go low to signal the end of a conversion and the
digital outputs will always be enabled, so using INTR to
strobe the WR line for a continuous conversion cannot be
done with this part.
A simple stand-alone circuit can be accomplished by driving
WR with the inverse of the READY OUT signal using a simpie inverter as shown below.

2. With the standard timing WR pulse width longer than the
conversion time a conversion is completed but the INTR will
never go low to signal the end of a conversion. The output
latches will be updated and valid information will be available when the RD cycle is accomplished.

I

ViR

'LJ

'LJ
,

LJ,,

LJ
,
,
,
,

R5
INTR

I,
,

I

I

I

Cs

,

,
I

,
,

,

,I
,
,

,
,
,
I

Te

"

READY OUT

DATA
(DBO-DB7)

Il

Il

(

(

)

MOST
SIGNIFICANT
BYTE

.,I,

)

LEAST.
SIGNIFICANT
BYTE

FIGURE 14

2-559

TLIH/5676-30

Functional Description

(Continued)
ADC1205
Case 1 would be the' only one that would appy to the
ADC1205 since two AD strobes are necessary to retrieve
the 13 bits of information on the 8 bit data bus. Simultaneously strobing ii'\iR" and, AD low will enable the most significant byte on DBO-DB7 and start a conversion. Pulsing
WFi/Rri low before the end of this conversion will enable
the least significant byte of data on the outputs and restart a
conversion;

through the output resistance of the analog signal source.
This charge pumping action is worse for continuous conversions with the VIN( +) input voltage at full-scale. For continuous conversions with a 1 MHz clock. frequency and the
VIN! + ) input at 5V, the average input current is approximately 5 p.A. For this reason bypass capaCitors should not be
used 'at the analog inputs for high resistance sources
(RSOURCE 100 0).
If input bypass capacitors are necessary for noise filtering
and high source resistance is desirable to minimize capaCitor
size, the detrimental effects of the voltage drop across this
input resistance, due to the average value of the input current, can be minimized with a full-scale adjustment while the
given source resistance and input bypass capacitor are both
in place. This is effective because the average value of the
input current is a linear function of the differential input voltage.

4.0 REFERENCE VOLTAGE
The voltage applied to the reference input of the converter
defines the voltage span of the analog inputs (the difference
between VIN(+) and VIN(-), over which 4096 positive output codes and 4096 negative output codes exist. The
A-to-D can be used in either' ratiometric or absolute reference applications. VREF must be connected to a voltage
source capable of driving" the reference input resistance
(typically 4 kO).

5.4 INPUT SOURCE RESISTANCE
large values of source resistance where an input bypass
capacitor is not used, will not cause errors as the input currents settle out prior to the comparison time. If a low pass
filter is required in the system, use a low valued series resistor (RS;100 0) for a passive RC section or add an op amp
RC active low pass filter. For low source resistance applications, (RsoURCE S; 100 0) a 0.001 p.F bypass capacitor at
the inputs will prevent pickup due to series lead inductance
of a long wire. A 100 0 series resistor can be used to isolate
this capacitor - both the Rand C are placed outside the
feedback loop - from the output of an op amp, if used.

In a ratiometric system, the analog input voltage is proportional to the voltage used for the AID reference. When. this
voltage is the system power supply, the VREF pin 'can be
tied to Vee. This technique relaxes the stability requirement
of the system reference as the analog input and AID reference move together maintaining the same output code for a
given input condition.
For absolute accuracy, where the analog Input varies between very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
In general, the magnitude of the reference voltage will require an initial adjustment to null out full-scale errors.

5.5 NOISE
The leads to the analog inputs should be kept as short as
possible to minimize input noise coupling. Both noise and
undesired digital 'clock coupling to these inputs can cause
errors. Input filtering can be used to reduce the effects of
these sources, but careful note should be taken of sections
5.3 and 5.4 if this route is taken.

5.0 THE·ANALOG INPUTS'
5.1 DIFFI;RENTIAL VOLTAGE INPUTS AND COMMON
MODE REJECTION,
The differential inputs of the ADC1225 and ADC1205 actually reduce the effects of common-mode input noise, i.e.,
signals common to both VIN( +) and VIN! _) inputs (60 Hz is
most typical). The time interval between sampling the," + ..
and" -" input is 4 clock periods. Therefore, a change in the
common-mode voltage during this short time interval may
cause conversion errors. For a sinusoidal common-mode
Signal the error would be:

6.0 POWER SUPPLIES
NoiSe spikes on the VCC supply line can cause conversion
errors' as the comparator will respond to this noise. Low
inductance tantalum capaCitors of 1p.F or greater are recommended for supply bypassing. Separate bypass caps
should be placed close to the DVee and AVee pins. If an
unregulated voltage source is available in the system, a separate LM340LAZ-5.0 voltage regulator for the A-to-D's Vcc
(and other analog circuitry) will greatly reduce digital noise
on the supply line.

4·
VERROR(MAX) = VPEAK (2'IT fCM) -fClK
where fCM is the frequency of the common-mode Signal,
VPEAK is its peek voltage value and fClK is the converter's
clock frequency. In most cases VERROR will not be significant. For a 60 Hz common-mode, signal to generate a %
LSB error (300 p.V) with the converter running at 1 MHz its
peak value would have to be 200mV.

7.0 ERRORS AND REFERENCE VOLTAGE
ADJUSTMENTS
7.1 ZERO ADJUST
The zero error of the AID converter relates to the location
of the first riser of the transfer function and can be measured by grounding the VIN(-) input and applying a small
magnitude positive voltage to the VIN( +) input. Zero error is
the difference between the actual DC input ,voltage necessary ·to just cause an output digital code transition from all
zeroes to 0,0000,0000,0001 and the ideal Yz LSB value (Yz
LSB=0.61 mV for VREF=5 Vee). Zero error can be adjusted as shown in Figure 15. VIN(+) is forced to 0.61 mV, and
VIN(-) is forced to OV. The potentiometer is adjusted until
the digital output code changes from all zeroes to
O,OOO,OOOO,OOOt.

5.2 INPUT CURRENT
Due to the sampling nature of the analog inputs, short duration spikes of current enter the .. + .. input and exit the .. -"
input at the leading clock edges during the actual conversion. These currents decay rapidly and do not cause errors
as the internal comparator is strobed at the end of a clock
period.
5.3 INPUT BYPASS CAPACITORS
Bypass capacitors at the inputs will average the current
spikes mentioned in 5.2 and cause a DC current to flow

2-560

~

Functional Description (Continued)
tude of the VREF input so that the output code is just changIng from 0,1111,1111,1110 to 0,1111,1111,1111.

A simpler, although slightly less accurate, approach is to
ground VIN(+) and VIN(-), and adjust for all zeros at the
output. Error will be well under % LSB if the adjustment is
done so that the potentiometer is "centered" within the
0,000,000 range. A positive voltage at the Vas input will
reduce the output code. The adjustment range is + 4 to
-30 LSB.

39K

Bipolar Inputs
Do the same procedure outlined above for the unipolar case
and then change the differential input voltage so that the
digital output code is just changing from 1,0000,0000,0001
to 1,0000,0000,0000. Record the differential input voltage,
Vx. the ideal differential input voltage for that transition
should be;

0.61 mV

( -VF

+5V

+.:!L)
8192

Calculate the difference between Vx and the ideal voltage;

t:.. = Vx - (-VF

+.:!L)
8192

Then apply a differential input voltage of;
TUH/5676-11

(Vx -

FIGURE 15. Zero Adjust Circuit

%)

and adjust the magnitude of VREF so the digital output
code is just changing from 1,0000,0000,0001 to
1,0000,0000,0000. That will obtain the positive and negative
full-scale transition with symmetrical minimum error.

7.2 POSITIVE AND NEGATIVE FULL·SCALE
ADJUSTMENT
Unipolar Inputs
Apply a differential input voltage which is 1.5 LSB below the
desired analog full·scale voltage (VF) and adjust the magni·

Typical Applications

'Input must have some
current return path to
signal ground

r------1Vuq+1

DVCC~====~--,

....----i\\N(-J

AVec ~==::::::----

...

• 0.

f!I

'*

V-r-----I

91+----t
Wlil+----t

RIII+---f
IRTI--.....
READY OUT t----1..

OBlI-_~
TUH/5676-12

2·561

o
.....
~

~o.....

N
N
U1

U)

~
,..

g

r-------------------------------------------------------------------------------------,
Typical Applications (Continued)

cc
......

Protecting the Input

U)

Q

-Ycc

C'\I
,..

(5YOC)

g
cc

Vce

+-

T

10 ,.l'

':'

'

ADC1205
ADC1225

-

YIN(-)

TUH/5676-16

Diodes are lN914

Operating with Ratiometric Transducers
vee
-(5Voel

+

T T

500
ZERO

O1
.

ADJ

500

ADC1205
ADC1225

10

,.F

OVee
3.9k

VREF
'VIN(-)

= 0.15 Vee

15% 01 Vee'; VXDR ,; 85% of Vee
TL/H/5676-17

2·562

»

Typical Applications

c
o.....

(Continued)

'"o

Bipolar Input Temperature Converter

CI1
.......

»
c

5V

o
.....

+

~ID"F~D.l

'"
N

CI1

lDV
DVee

DVee

VREF

TL/H/5676-18

+ 150 to

- 55°C with 0.04°C resolution

Note: • resistors are 1 % metal film types

Strain Gauge Converter with .025% Resolution and Single Power Supply

fII

330

lDV~,---------~~~-------,__~~__~~

3.3k*

5.1V

ZENER
VREF

DVcc

AVec

ADC12D5
ADC1225

TL/H/5676-19

Note: 1)* resistors are 1% metal film types
2) LF412 power

+ 10V and ground

2-563

Ordering Information
Temperature Range
Non-Linearity

I

0.024%

Package Outline

O"C to 70"C
AOC1205CCJ-1
J24A

I
I

-40"Cto +85"C

AOC1225CCO-1

AOC1205CCJ

0280

J24A

I
I

ADC1225CCO
0280

,

2-564

I!fINational Semiconductor

ADC12062
12-Blt,1 MH2, 75 mW AID Converter
with Input Multiplexer and Sample/Hold
General Description

Features

Using an innovative' multistep conversion technique, the
12-bit ADC12062 CMOS analog-to-digital converter digitizes
signals at a 1 MHz sampling rate while consuming a maximum of only 75 mW on a single + 5V supply. The
ADC12062 performs a 12-bit conversion in three lower-resolution "flash" conversions, yielding a fast AID without the
cost and power dissipation associated with true flash approaches.

•
•
•
•

The analog input voltage to the ADC12062 is tracked and
held by an internal sampling circuit, allowing high frequency
input Signals to be accurately digitized without the need for
an external sample-and-hold circuit. The multiplexer output
is available to the user in order to perform additional external Signal processing before the signal is digitized.
When the converter is not digitizing signals, it can be placed
in the Standby mode; typical power consumption in this
mode is 100 p.W.

Built-in sample-and-hold
Single + 5V supply
Single channel or 2 channel multiplexer operation
Low Power Standby mode

Key Specifications
•
•
•
•
•

Sampling rate
Conversion time
Signal-to-Noise Ratio, fiN = 100 kHz
Power dissipation (fs = 1 MHz)
No missing codes over temperature,

1 MHz (min)
740 ns (typ)
69.5 dB (min)
75 mW (max)
Guaranteed

Applications
•
•
•
•
•

Digital signal processor front ends
Instrumentation
Disk, drives
Mobile telecommunications
Waveform digitizers

Block Diagram
, ,

~.

AVCC'DVCC
I

l:l

>0:

.ff

I

I

'~
ADC I N - + - - - + i

Sample
and
Hold

---

r+

12-Bit AID Converter

MUX OUT . .- - - - - ,

r-

•

Output
Latch
and
TRI-STAT[
Buffers

~2 DBODB11

",",- ~ '0."" J""'___________T........

I

V ,_Lo.
IN2
,..

Timing and Control Circuitry

I
SO

DGND

AGND

t-+"INT
t -+ [OC

f'f' f' _'t. f' 't_
Cs s/il Rii OE MODE to

Ordering Information

r--------------------r--------------------,
Industrial (-40'C TA + 85')
Package
~

~

ADC12062BIV

V44 Plastic Leaded Chip Carrier

ADC12062BIVF

VGZ44A Plastic Quad Flat Package

ADC12062CIV

V44 Plastic Leaded Chip Carrier

ADC12062CIVF

VGZ44A Plastic Quad Flat Package

ADC12062EVAL

Evaluation Board

2-565

TLlH111490-1

Absolute Maximum Ratings (Notes 1,2)
Soldering lriformation (Note 6)
V Package, Infrared, 15 seconds
VF Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.3Vto +6V
Supply Voltage (Vee = DVee = AVecl
Voltage at Any Input or Output
Input Current at Any Pin (Note 3)

-0.3VtoVee + O.3V
25mA

Package Input Current (Note 3)
Power Dissipation (Note 4)
ESD Susceptibility (Note 5)

+300'C
+215'C
+ 220'C
-65'Cto + 150'C

Storage Temperature Range
Maximum Junction Temperature (TJMAX)

50mA
875mW

150'C

Operating Ratings (Notes 1, 2)

2000V

Temperature Range
TMIN ,;: TA';: TMAX
ADC12062BIV, ADC12062CIV,
ADC12062BIVF, ADC12062CIVF -40'C';: TA';: +85'C
4.5Vt05.5V
Supply Voltage Range (DVee = AVecl

Converter Characteristics

The following specifications apply for DVee = AVec = +5V, VREF+(SENSE) =
+4.096V, VREF-(SENSE) = AGND, and fs = 1 MHz,unless otherwise specified. Boldface limits apply forTA = TJ from
TMIN to TMAX; all other limits TA =TJ = +25'C.
Symbol

Parameter

Conditions

Typ
(Note 7)

limit
(Note 8)
12

Bits

Differeritial Linearity Error

TA = 25'C
TMINto TMAX

±OA

±0.8
±0.95

LSB (max)
LSB (max)

Integral Linearity Error
(Note 9)

TMIN to TMAX (BIV Suffix)

±OA

± 1.0

LSB (max)

TA = + 25'C (CIV Suffix)
TMIN to TMAX (CIV Suffix)

±OA

±1.0
±1.5

LSB (max)
LSB (max)

Offset Error

TMIN to TMAX (BIV Suffix)

±0.3

±1.25

LSB (max)

TA = + 25'C (CIV Suffix)
TMIN to TMAX (CIV Suffix)

±O.3

±1.25
±2.0

LSB (max)
LSB (max)

TMIN to TMAX (BIV Suffix)

±0.2

±1.0

LSB (max)

TA = + 25'C (CIV Suffix)
TMIN to TMAX (CIV Suffix)

±0.2

±1.0
± 1.5

LSB (max)
LSB (max)

± 1.0

LSB (max)

500
1000

!l(min)
!l(max)

AVec

V (max)

Resolution

Full Scale Error

Power Supply Sensitivity
(Note 15)

DVee = AVec = 5V ±10%

RREF

Reference Resistance

VREF(+)

VREF + (SENSE) Input Voltage

VREF(-)

VREF-(SENSE) Input Voltage

VIN

Input Voltage Range

To VIN1, VIN2, or ADC IN

ADC IN Input Leakage

AGND to AVec - 0.3V

CADe

CMUX

Units
(Limit)

750

ADC IN Input Capacitance

0.1

AGND

V (min)

AVec + 0.05V
AGND - 0.05V

V (max)
V (min)

3

p.A(max)

25

pF

MUX On·Channel Leakage

AGND to AVec - 0.3V

0.1

3

p.A(max)

MUX Off·Channel Leakage

AGND to AVec - 0.3V

0.1

3

p.A(max)

7

pF

fiN = 100kHz

92

dB

Multiplexer Input Cap
MUX Off Isolation

2·566

Dynamic Characteristics

(Note 10) The following specifications apply for DVee = AVec = +5V,
VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, Rs = 250, fiN = 100 kHz, 0 dB from fullscale, and fs = 1 MHz, unless
otherwise specified. Boldfacellmlls apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = + 25°C.
Symbol

Parameter

Conditions

Typ
(Note 7)

Limit
(Note 8)

Units
(Limit)

SINAD

Signal-to-Noise Plus
Distortion Ratio

TMINtoTMAX

71

68.0

dB (min)

SNR

Signal-to-Noise Ratio
(Note 11)

TMINto TMAX

72

69.5

dB (min)

THD

Total Harmonic Distortion
(Note 12)

TA = +25°C
TMINtoTMAX

-82

-74

-70

dBc(max)
dBc(max)

ENOB

Effective Number of Bits
(Note 13)

TMINto TMAX

11.5

11.0

Bits (min)

IMD

Intermodulation Distortion

fiN

=

102.3 kHz, 102.7 kHz

-80

dBc

DC Electrical Characteristics

The following specifications apply for DVee = AVec = +5V,
VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, and fs = 1 MHz, unless otherwise specified. Boldface limits apply
for T A = T J from TMIN to TMAXi all other limits TA = TJ = + 25°C.
Symbol

Parameter

Conditions

VIN(l)

Logical "1" Input Voltage

DVce

VINIO)

Logical "0" Input Voltage

DVee

=
=

AVec
AVec

=
=

Typ
(Note 7)

limit
(Note 8)

Units
(Limit)

+5.5V

2.0

V (min)

+4.5V

0.8

V (max)

IINll)

Logical "1" Input Current

0.1

1.0

,.,.A(max)

IINIO)

Logical "0" Input Current

0.1

1.0

,.,.A(max)

VOUTll)

Logical "1" Output Voltage

2.4
4.25

V (min)
V (min)

0.4

V (max)

3

,.,.A(max)

DVcc = AVec = +4.5V,
lOUT = - 360 ,.,.A
lOUT = -100,.,.A

VOUTIO)

Logical "0" Output Voltage

DVcc = AVec = +4.5V,
lOUT = 1.6 mA

lOUT

TRI-STATE® Output
Leakage Current

Pins DBO-DB11

COUT

TRI-STATE Output Capacitance

Pins DBO-DB11

CIN

Digital Input Capacitance

0.1
5

pF

4

pF

Dice

DVcc Supply Current

.2

Alec

AVec Supply Current

10

ISTANDBY

Standby Current (Dice + Alec)

PD

=

OV

3

mA(max)

12

mA(max)

20

,.,.A

..

2-567

»
c

o.....
~

Q)

N

AC Electrical. Characteristics

The following specifications apply for DVcc =e. AVcc ,= +5V,
VREF+(S'ENSE) = +4.096V"VREF':"(SENSE) = AGND, and fs = 1 MHz, unless otherwise spec.ified. Boldface limit. apply
for TA = TJ from TMIN'to TMAX; all other·limits TA' =c TJ = + 25°C.
.'

,
Symbol

Parameter

Conditions

,','

fs' '

Typ
(Note 7)

Maximum Sampling Rate

Limit
(Note 8)
.'

l'

MHz (min)

600
980

ns(min)
ns(max)

(1/tTHROUGHPUT)
tCONV

Conversion Time
(SIR Low to EDC High)

tAD

Aperture Delay
(S/H Low to Inpu~ Voltage Held)

Is/R

SIH Pulse Width

IEOC

SIH Low 10 EDC Low

tACC

Access Time
(RD Low or DE High to Data Valid)

t1H, toH

.,

740

20

. CL

=

100 pF:

TRI-STATE Control
(RD High or DE Low to Databus TRI-STATE)

RL

=

1k,CL

tmi'H

Delay from RD Low to INT High

CL

100pF

tmi'i:.

,

Delay from EDC High to INT Low

CL

=
=

Units.

(Umlts)

ns

5
550

ns(min)
ns(max)

95

60
125

ns(min)
ns(max)

10

20

ns(max)

25

40

ns(max)

35

60

nS(max)

:"'35

-10

ns (min)
ns(max)

15

ns(max)

,
=

10pF

..
100pF

-25

tUPDATE

EOC High to New Data Valid

tMS'

Multiplexer Address Setup Time
,(MUX Address Valid to EOC L9w)

50

ns(min)

tMH

Multiplexer Address Hold Time.
(EOC Low to MUX Address Invalid)

50

ns(min)

~S

CS Setup Time
Low to RD Low, SiR Low, or DE High)

20

ns(min)

20

ns(min)

tesH

5

(es

cs Hold Time
(CS High aiter RD High, StH High, or OE Low)

twu

Wake-Up Time
(PO High to FirstS/H ~ow)

1

p.s

NOle 1: AbSolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate cOnditions for which the device is
funCtional. These ratings do not guarantee specific performance. limits, however. For guaranteed specifications and test conditions, see the Electrical Characteris-

tics, The guaranteed specifications apply only for the test conditions listed, Some performance characteristics may degrade when the device is not operated under
the listed test conditions.
.
,
Nole 2: All voltages are measured wHh respect to GND (GND ~ AGND ~ DGND), unless otherwise specified,
Nole 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > VCe! the absolute value of cuirent at that pin should be
limited to 25 mA or less, The 50 mA package input current limits the number of pins that can safely exceed the power supplies with an Input current of 25 mA to
two,
Nole 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, OJA and the ambient temperalllre TA, The maximum
allowable power dissipation at any temperature is Po ~ (TJMAX - TA)/OJA or the number given in the Absolute Maximum Ratings, whichever is lower. 0JA for the V
(PLCC) package is 55·C/W. OJA for the VF (PQFP) package is 62·C/W, In most cases the maximum derated power dissipation will be reached only during fault
condHions.

2-568

l>
C

Note 5: Human body model, 100 pF discharged through a 1.5 kn resistor. Machine model ESD rating is 200V.
Note 6: See AN-4S0 "Surface Mounting Methods and Their Effect on Product Reliability" or the section titled "Surface Mount" found in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.

o
....

Note 7: Typicals are at + 2S'C and represent most likely parametric norm.

g

Note 8: Tested limits are guaranteed to National's AOQL (Average OutgOing Quality Level).

N

Note 9: Integral Linearity Error is the maximum deviation from a straight line between the measured offset and full scale endpoints.
Note 10: Dynamic testing of the ADCt2062 is done using the ADC IN input. The input multiplexer adds harmonic distortion at high frequencies. See the graph in the
Typical Performance Characteristics section for a typical graph of THO performance vs input frequency with and without the input multiplexer.
Note 11: The signal-to-noise ratio is the ratio of the Signal amplitude to the background noise level. Harmonics of the input Signal are not included in its calculation.
Note 12: The contributions from the first nine harmonics are used in the calculation of the THO.
Note 13: Effective Number of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB

= (SINAD

-

1.76)/6.02.

Note 14: The digital power supply current takes up to 10 seconds to decay to its final value after PO Is pulled low. This prohibits production testing of the standby
current. Some parts may exhibit significantly higher standby currents than the 20 }J-A typical.

Note 15: Power Supply Sensitivity Is defined as the change in the Offset Error or the Full Scale Error due to a change in the supply voltage.

TRI-STATE Test Circuit and Waveforms
DVcc

DVcc

Rii
GND

Rii

DATA
OUTPUT

ADC

IG.

lit.
DVcc

-

DATA
OUTPUT

TUH/11490-2

GND
TL/H/11490-3

DVcc

DVcc

DVcc

Rii
GND

Rii

FJI

DATA
OUTPUT

ADC

IG.

DVcc
DATA
OUTPUT

TL/H/11490-4

GND
TLlH/11490-5

2-569

N
CD

CI

N
....

Typical Performance Characteristics

~

Offset and Fullscale
Error Change vs
Reference Voltage

a;

~

.,'"
'"u
z

I
~

~

il.SO

.,

z

I;;
~

:1:0.6

Drco = AVco = 5.0V

TA =2SoC _ _
I-fSAt,jPLE;:; 1.0 UHz

:tl.2S
:tI,OO

1\

'0.75

1\\

:1:0.50

w

.- r-

~ :to.s

~
rULL.SCALE

::"-...{.

~

~

Droo = AVoo = 5.DV

Mux ON Resistance vs
Input Voltage
3BO

I--

TA =250C _ _
I-'SoUfPlE = 1.0 MHz
I--

-

t!

'0.3

~

"

:1::0.2
:1:0.1

r....

t-

-

~

260

z

'BO

x

'40

~

'00
60

..s

~

il

i
~

2.'

.....

--- --

5.5V
5.25V
5.0V...

4.75V

-

......

4.5V

"<

I"

..s

r-...
r-... ......

z

"
......

~
~

il

i
~

I"

~

1.9
-55-35-'5 5 25 45 65 B5 '05'25

'0.0
9.5

V
/IV

BOO

'1

790

w
:I

;:::

780
770

~
!:!

760

8

740

~

11

~

0

-5

1

]

5+- I-

I~
~

750

-;

5.0V

)1.:'- f...::

4.SV

l"-

.
w

-

;:::

....... ~

-!:::= i::='
I

~
1:i

'05

90

=

-40dB

=

;;.-:: P""

~

-90
-BO

601----~~-~~~

601-------~~------~

-70

501----~~------~

50~------~~------~

30

1SANPLE;:; 1.0 MHz

fiN = 0 dB from fullscale

20

30

fSA t.4PLE
fiN

20

= 1.0 MHz
=0 dB from

-------------r-------~~~~----------------OBO-OBII

XIo..._____O_A_TA_(..n_-...1l_ _ _ _ _"

>C

JIo_ _ _ _ _ _O_A_TA_(..n..
l ________

TL/H/11490-10

FIGURE 2. High Speed Interface Timing (MODE = 1, OE = 1, CS = 0, RD = 0)

icsH

s/H

or

--......I)

TUHII1490-11

FIGURE 3. ~ Setup and Hold Timing for siR, RD, and .OE

Connection Diagrams

""

>

..

o

(.)

~

C

c

c'"

:5

N

z

c.J
Z

TLIHII1490-29

TOp View

Top View
2-572

»
c

Pin Descriptions
AVcc

DVcc

AGND,
DGND1,
DGND2

DBO-DB11

MUXOUT
ADCIN

SO

These are the two positive analog supply
inputs. They should always be connected
to the same voltage source, but are
brought out separately to allow for separate bypass capacitors. Each supply pin
should be bypassed to AGND with a
0.1 /loF ceramic capacitor in parallel with a
10 /loF tantalum capacitor.
This is the positive digital supply input. It
should always be connected to the same
voltage as the analog supply, AVcc. It
should be bypassed. to DGND2 with a
0.1 /loF ceramic capacitor in parallel with a
10 /loF tantalum capacitor.
These are the power supply ground pins.
There are separate analog and digital
ground pins for separate bypassing of the
analog and digital supplies. The ground
pins should be connected to a stable,
noise-free system ground. All of the
ground pins should be returned to the
same potential. AGND is the analog
ground for the converter. DGND1 is the
ground pin for the digital control lines.
DGND2 is the ground return for the output
databus. See Section 6.0 LAYOUT AND
GROUNDING for more information.
These are the TRI-STATE output pins, enabled by RD, CS, and bE.
These are the analog input pins to the multiplexer. For accurate conversions, no input pin (even one that is not selected)
should be driven more than 50 mV below
ground or 50 mV above Vcc.
This is the output of the on-board analog
input multiplexer.
This is the direct input to the 12-bit sampling AID converter. For accurate conversions, this pin should not be driven more
than 50 mV below AGND or 50 mV above
AVcc·
This pin selects the analog [nput that will
be connected to the ADC12062 during the
conversion. The input is selected based on
the state of SO when EOC makes its highto-low transition. Low selects VIN1, high
selects VIN2.

MODE
CS

OE

s/H

PO

This pin should be tied to DVcc.
This is the active low Chip Select control
input. When low, this pin enables the RD,
s/H, and OE inputs. This pin can be tied
low.
This is the active low Interrupt output.
When using the Interrupt Interface Mode
(Figure 1), this output goes low when a
conversion has been completed and indicates that the conversion result is available in the output latches. This output is
always high when RD is held low (Figure
2).
This is the End-of-Conversion control output. This output is low during a conversion.
This is the active low Read control input.
When RD is low (and CS is low), the INT
output is reset and (if OE is high) data appears on the data bus. This pin can be tied
low.
This is the active high Output Enable control input. This pin can be thought of as an
inverted version of the RD input (see Figure 6). Data output pins DBO-DB11 are
TRI-STATE when,OE is low. Data appears
on DBO-DB11 only when OE is high and
CS and RD are both low. This pin can, be
tied high.
This is the Sample/Hold control input. The
analog input signal is held and a new conversion is initiated by the falling edge of
this control input (when CS is low).
This is the Power Down control input. This
pin should be held high for normal operation. When this pin is pulled low, the device
goes into a low power standby mode.

VREF + (FORCE), These are the positive and negative voltVREF-(FORCE) age reference force inputs, respectively.
Se,e Section 4, REFERENCE INPUTS, for
more information.
VREF+(SENSE), These are the positive and negative voltVREF-(SENSE) age reference sense pins, respectively.
See Section 4, REFERENCE INPUTS, for
more information.
VREF/16
This pin should be bypassed to AGND with
a 0.1 /loF ceramic capacitor.
TEST
This pin should be tied to DVcc.

2-573

o
....
N
(;)

en

N

Functional Description
The ADC12062 performs a 12-bit analog-to-digital conversion using a 3 step flash technique. The first flash determines the six most significant bits, the second flash generates four more bits, and the final flash resolves the two least
significant bits. Figure 4 shows the major functional blocks
of the converter. It consists of a 2%-bit Voltage Estimator, ,a
resistor ladder with two different resolution voltage spans, a
sample/hold capacitor, a 4-bit flash converter with front end
multiplexer, a digitally corrected DAC, and a capacitive voltage divider.
The resistor string near the center of the block diagram in
Figure 4 generates the 6-bit and 1O-bit reference voltages
for the first two conversions. Each of the 16 resistors at the
bottom ,of the string is equal to V,024 of the total string resistance. These resistors form the LSB Ladder· and have a
voltage drop of V,024 of the total reference voltage (VREF +
- VREF-) across each of them. The remaining resistors
form the MSB Ladder. It is comprised of eight groups of
eight resistors each connected in series (the lowest MSB
ladder resistor is actually the entire LSB ladder). Each MSB
Ladder section has 'Is of the total reference voltage across
it. Within a given MSB ladder section, each of the eight MSB
resistors has Y64 of the total reference voltage across it. Tap
points are found between all of the resistors in both the
MSB and LSB ladders. The Comparator Multiplexer can
connect any of these tap points, in two adjacent groups of
eight, to the sixteen comparators shown at the right of
Figure 4. This function provides the necessary reference
voltages to the comparators during the first two flash conversions.
The six comparators, seven-resistor string (Estimator DAC
ladder), and Estimator Decoder at the left of Figure 4 form

the Voltage Estimator. The Estimator'DAC, connected between VREF+ and VREF-, generates the reference voltages for the six Voltage Estimator comparators. The comparators perform a very low resolution A/D conversion to
obtain an "estimate" of'the input voltage. This"estimate is
used to control the placement of the Comparator Multiplexer, donnecting the appropriate MSB ladder section to the
sixteen flash comparators. A total of only 22 comparators (6
in the Voltage Estimator and, 16 in the flash converter) is
required to quantize the input to 6 bits, instead of the 64 that
would be required using a traditional 6-bit flash.
Prior to 'a conversion, the Sample/Hold switch is closed,
allowing the voltage on the 81H capaCitor to track the input
voltage. Switch 1 is in position 1. A conversion begins by
opening the Sample/Hold switch and latching the output of
the Voltage Estimator. The estimator decoder then selects
two adjacent banks of tap points along the M8B ladder.
These sixteen tap pOints are then connected to the sixteen
flash converters. For example, if the' input voltage is between 5As and 'l',S of VREF (VREF = VREF+ - VREF-), the
estimator decoder instructs the comparator multiplexer to
select the sixteen tap points between % and % (0/16 and
0/,6) of VREF and connects them to the sixteen comparators.
The first flash conversion is now performed, producing the
first 6 MSBs of data.
'
At this pOint, Voltage Estimator errors as large as V,6 of
VREF will be corrected since the comparators are connected to ladder voltages that 'extend beyond the range specified by the Voltage Estimator. For example, if f1A6)VREF
< VIN < (9A6)VREF, the Voltage Estimator's comparators
tied to the tap points below (9As)VREF will output "1"s
(000111). This is decoded by the estimator decoder to "10".
The 16 comparators will ,be placed on the M8B ladder

'Note: The weight of each resistor on the LSB ladder is actually equivalent
10 four 12-ml LSBs. II Is called the LSB ladder because It has the
highest resolution of alilhe ladders in Ihe converter.
Hold
V'N
V...+ (SENSE)

VREr+(rORCE)

o--'t----------~s.mpl.

S/H

, I Cap

0--+--------.

O-'t-~----1===:t-i---~I--:--t-:---,--,
7/8

13/16
6/8

0911
0910

11/16
2/8

9/16

DB9

i

&

DB8
1/8

j
7/16

.

~

15/1024

;
5/16

3/16

DB7

Output
Buffer

DB6
DB5

16/1024

;S

TRI-STATE

DB4

16

DB3
DB2
DBI

14/1024

Cap.

13/1024

Voltage
Divider

16

DBO

12/1024
I

1/1024
VREr_ (rORCE)

0-...- - - - - - -..

VREr-(SENSE)

0---------..1

TLlH/11490-14

FIGURE 4. Functional Block Diagram

2-574

Functional Description

(Continued)
Voltage Estimator, first flash, and second flash to yield the
final 12-bit result.

tap pOints between ("!a)VREF and (%)VREF. This overlap of
(1!1e)VREF will automatically cancel a Voltage Estimator error of up to 256 LSBs. If the first flash conversion determines that the input voltage is between ("!a)VREF and
«%)VREF - LSB/2), the Voltage Estimator's output code
will be corrected by subtracting "1", resulting in a corrected
value of "01" for the first two MSBs. If the first flash conversion determines that the input voltage is between (%)VREF
- LSB/2) and (%)VREF, the voltage estimator's output
code is unchanged.
The results of the first flash and the Voltage Estimator's
output are given to the factory-programmed on-chip
EEPROM which returns a correction code corresponding to
the error of the MSB ladder at that tap. This code is converted to a voltage by the Correction DAC. To generate the next
four bits, SWI is moved to position 2, so the ladder voltage
and the correction voltage are subtracted from the input
voltage. The remainder is applied to the sixteen flash converters and compared with the 16 tap points from the LSB
ladder.

By using the same sixteen comparators for all three flash
conversions, the number of comparators needed by the
multi-step converter is significantly reduced when compared
to standard multi-step techniques.

Applications Information
1.0 MODES OF OPERATION
The ADC12062 has two interface modes: An interrupt/read
mode and a high speed mode. Figures 1 and 2 show the
timing diagrams for these interfaces.
In order to clearly show the relaiionship between SIH, CS,
RD, and OE, the control logic decoding section of the
ADC12062 is shown in Figure 6.
Interrupt Interface
As shown in Figure 1, the falling edge of siR holds the input
voltage and initiates a conversion. At the end of the conversion, the EOC output goes high and the TNi output goes
low, indicating that the conversion results are latched and
may be read by pulling RD low. The falling edge of AD resets the INT line. Note that CS must be low to enable siR

The result of this second conversion is accurate to 10 bits
and describes the input remainder as a voltage between two
tap, pOints (VH and Vu on the LSB ladder. To resolve the
last two bits, the voltage across the ladder resistor (between
VH and Vu is divided up into 4 equal parts by the capacitive
voltage divider, shown in Figure 5. The divider also creates
6 LSBs below VL and 6 LSBs above VH to provide overlap
used by the digital error correction. SWI is moved to position 3, and the remainder is compared with these 16 new
voltages. The output is combined with the results of the

orAD.
High Speed Intertace
This is the fastest interface, shown in Figure 2. Here the
output data is always present on the databus, and the INT to
RD delay is eliminated.

~----------------~
To LSB

Ladder

4V

+ov

3V

+1~

~=VL +4LSB
~=VL +3lSB

TUH/11490-15

FIGURE 5. The Capacitive Voltage Divider

2-575

»
o
o
....

g
N

Applications Information (Continued)
·ADC12062

s!ii

RD.
OE

INT from internal state machine ----+1'-....:..1
TUH/11490-16

FIGURE 6. ADC Control Logic
,

",'.

2.0 THE At.!ALOG INPUT
The analog input.of the ADC12062;can be modeled as two
small resistances in series with the capacitance of the input
hold capaCitor (GIN), as shown in Figure.7, The SIH switch
is closed during the Sample period, and open during Hold.
The source has to charge GiN to the input voltage within the
sample period. Note that the source impedance of the input
voltage (RSOURCE) has a direct effect on the time it takes to
charge CIN. If RSOURCE is too large, the voltage across GIN
will not settle to within 0.5 LSBs of VSOURCE before the
conversion begins, and the conversion results will be incorrect. From a dynamiC performance viewpoint, the combination of RSOURCE, RMUX, Rsw, and CIN form a low pass
filter. Minimizing RSOURCE will increase the frequency response of the input stage of the converter.
Typical values for the components shown in Figure 7 are:
RMUX = 100n, Rsw = 100n, and CIN = 25 pF. The-set.
.
tling time to n bits is:
tsETILE = (RSOURCE ~ RMUX 'I- Rsw) •

The bandwidth of the input circuit is:
L3d8 = 1/(2' 3.14' (RSOURCE + RMUX

FClr maximum performance, the impedance of the source
driving the ADG12062 should be made as small as possible.
A source impedance of 100n or less is recommended. A
plot of dynamic performance vs. source impedance is given
in the Typical Performance CharactE1ristics section.
If the signal source has a high output impedance, its output
should be buffered with an operational amplifier capable of
driving a switch~d 25 pF/1 oon load. Any ringing or instabilities at the op amp's output during the sampling period can
result in conversion errors. The LM6361 high speed op amp
is a good choice for this application due to its speed and its
ability to drive large capacitive loads. Figure 8 shows the
LM6361 driving the ADC IN input of an ADC12062. The
100 pF capacitor at the input of the converter absorbs some
of the high frequency transients generated by the SIH
switching, reducing the op amp transient response requirements. The 100 pF capacitor should only be used with high
speed op amps that are unconditionally stable driving capacitive loads.

CIN • n • In (2).

+ Rsw)' GIN)

.------------------------------•
•
•

ADC12062

VIN1 :

!\tux

RSOURCE

•

••

NUX OUT'

•••
•

•

.I
Rsw
ADC IN.•
~--,",,;';";'~.I--""S/H ~To Comparators

!

Switch

IGN

••
•
._-----------------------------_.
FIGURE 7. Simplified ADC12062 Input Stage

2-576

TLlH/11490-17

Applications Information

(Continued)

p-------------------------------

:'

ADC12062'

V,N, :

Inpu! signal
(Through Multiplexer)

»-------------.:;.:.;.+:--

>

Rr.iux

V,N2 :
I
I

MUX OUT I
I
I

+12V

I

I
I

Inpu! signal> ___ _
(Direct)

ADC IN I

RSW

I

S/i1 ~ To Comparators
Swi!ch

GN

._-----------------------------_.

TlIH/11490-18

FIGURE 8. Buffering the Input with an LM6361 High Speed Op Amp
Another benefit of using a high speed buffer is improved
THO performance when using the multiplexer of the
AOC12062. The MUX on-resistance is somewhat non-linear
over input voltage, causing the RC time constant formed by
C'N, RMUX, and Rsw to vary depending on the input voltage.
This results in increasing THO with increasing frequency.
Inserting the buffer betWeen the MUX OUT and the AOC IN
terminals as shown in Figure 8 will eliminate the loading on
RMUX, significantly reducing the THO of the multiplexed system.
Correct converter operation will be obtained for input voltages greater than AGNO - 50 mV and less than AVec +

50 mY. Avoid driving the signal source more than 300 mV
higher than AVec, or more than 300 mV below AGNO. If an
analog input pin is forced beyond these voltages, the current flowing through that pin should be limited to 25 rnA or
less to avoid permanent damage to the IC. The sum of all
the overdrive currents into all pins must be less than 50 rnA.
When the input signal is expected to extend more than
300 mV beyond the power supply limits for any reason (unknown/unc~mtrollable input voltage range, power-on transients, fault conditions, etc.) some form of input protection,
such as that shown in Figure 9, should be used.

+5V

•

AVec

+12V

ADC12062

>----11""""---411---''''''''''...--1 ADC IN or Y,N

-12V
AGND

TLlH/11490-19

FIGURE 9. Input Protection

2-577

Applications Information (Continued)
3.0 ANALOG MULTIPLEXER
The ADC12062 has an inp!lt multiplexer that is controlled by
the logic level on pin SO when EOC goes low, as shown in
Figures 1 and 2. Multiplexer setup and hold times with respect to the SIH input can be determined by these two
equations:
'

signal is returned to the ADC IN input and digitized. If no
additional signal processing is required, the MUX OUT pin
should be tied directly to the ADC IN pin.
See Section 9.0 (APPLICATIONS) for a simple circuit that
will alternate between the two inputs while converting at full
speed.

tMS (wrt SIR) = tMS - tEOC (min) = 50 - 60 = -10 ns

4.0 REFERENCE INPUTS

tMH (wrt SIR) = tMH + lEoe (max) =; 50 + 125 = 175 ns
Note that tMS (wrt SIR) is a negative number; this indicates
that the data on SO must become valid within 10 ns after
SIH goes low in order to meet the setup time requirements.
SO must be valid for a length of

In addition to the fully differential VREF + and VREF _ reference inputs used on most National Semiconductor ADCs,
the ADC12062 has two sense outputs for precision control
of the ladder voltage. These sense inputs compensate for
errors due to IR drops between the reference source and
the ladder itself. The resistance of the reference ladder is
typically 750.0. The parasitic resistance (Rp) of the package
leads, bond wires, PCB traces, etc. can easily be 0.5.0 to
1.0.0 or more. This may not be significant at 8-bit or 10-bit
resolutions, but at 12 bits it can introduce voltage drops
causing offset and gain errors as large as 6 LSBs.
The ADC12062 provides a means to eliminate this error by
bringing out two additional pins that sense the exact voltage
at the top and bottom of the ladder. With the addition of two
op amps, the voltages on these internal nodes can be
forced to the exact value desired, as shown in Rgure 10.

(tMH + tEOC (max» - (tMS - tEOC (min» = 185 ns.
Table I shows how the input channels are assigned:
TABLE I. ADC12062 Input
Multiplexer Programming

SO

Channel

0
1

VIN1
VIN2'

The output of, the multiplexer is available to the user via the
MUX OUT pin. This outpu,t allows the user to perform additional signal processing, such as filtering or gain, before the

.-----------------------

I

ADC12062

VREf+(SENSE)! R.

lkn

4.096V

soon
~----~~~~----+----.~~~

I

LN4040 - 4.1

/

I

Vref = (Vref+)-(Vref-) = 4.096V
Rf = o.sn (force line impedance)
Rs = 10n (sensa line impedance)
Rladder 0; 7son

Reference
Ladder

soon

1 kn

I

I
VREF- (SENSE) I
I
I

._----------------------

TUH/11490-20

FIGURE 10. Reference Ladder Force and Sense Inputs

2-578

Applications Information

(Continued)

Since the current flowing through the SENSE lines is essentially zero, there is negligible voltage drop across Rs and the
1 kn resistor, so the voltage at the inverting input of the op
amp accurately represents the voltage at the top (or bottom) of the ladder. The op amp drives the FORCE input and
forces the voltage at the ends of the ladder to equal the
voltage at the op amps's non-inverting input, plus or minus
its input offset voltage. For this reason op amps with low
Vos, such as the LM627 or LM607, should be used for this
application. When used in this configuration, the ADC12062
typically has less than 0.5 LSB of offset and gain error without any user adjustments.

The reference inputs are fully differential and define the
zero to full-scale range of the' input signal. They can be
configured to span up to 5V (VREF- = OV, VREF+ = 5V),
or they can be connected to different voltages (within the
OV to 5V limits) when other input spans are required. The
ADC12062 is tested at VREF- (SENSE) = OV, VREF+
(SENSE) = 4.096V. Reducing the reference voltage span to
less than 4V increases the sensitivity (reduces the LSB size)
of the converter; however noise performance degrades
when lower reference voltages are used. A plot of dynamic
performance vs reference voltage is given in the Typical
Performance Characteristics section.

The 0.1 J.LF and 10 J.LF capacitors on the force inputs provide high frequency decoupling of the reference ladder. The
500n force resistors isolate the op amps from this large
capacitive load. The 0.01 J.LF/I kn network provides zero
phase shift at high frequencies to ensure stability. Note that
the op amp supplies in this example must be, ± 10V to
± 15V to meet the input/output voltage range requirements
of the LM627 and supply the sub-zero voltage to the
VREF- (FORCE) pin. The VREF/16 output should be bypassed to analog ground with a 0.1 J.LF ceramic capacitor.

If the converter will be used in an application where DC
accuracy is secondary to dynamic performance, then a simpler reference circuit may suffice. The circuit shown in Figure 11 will introduce several LSBs of offset and gain error,
but INL, DNL, and all dynamic specifications will be unaffected.
All bypass capacitors should be located as close to the
ADC12062 as possible to minimize noise on'the reference
ladder. The VREF/16 output should be bypassed to analog
ground with a 0.1 J.LF ceramic capacitor.
The LM4040 shunt voltage reference is available with a
4.096V output voltage. With initial accuracies as 'low as
± 0.1 %, it makes an excellent reference for the ADC12062.

.---------------------.--.
I

I

I

ADC12062

VREf+ (SENSE) :
NC~I--'"

4.096V
60n

"

I
""

:

VREf+'(fORCE) I

t-----.-----.-~

LM4040 - 4. I

~

, 10 ,ur T

o. I ,ur T

-=

-=

r

-=

-I -I

4.093V
/

"

VREf - (fORCE)

VREf - (SENSE) i
NC-+---'

~

O.003V

TL/H/I1490-21

FIGURE 11. Using the VREF Force Pins Only

2-579

Applications Information (Continued)
From Power Supply

5.0 POWER SUPPLY CONSIDERATIONS
The ADC12062 is designed to operate from a single +5V
power supply. There are two analog supply pins (AVec) and
one digital supply, pin (DVcc). These pins allow separate
external bypass capacitors for the analog and digital portions of the circuit; To guarantee proper operation of the
converter, all three supply pins should be conn'ected to the
same voltage source. In 'systems with separate analog and
digital supplies, the converter should be powered from the
analog supply.
The ground pins are AGND (analog ground), DGND1 (digital
input ground), and DGND2 (digital output ground). These
pins allow for, three separate ground planes for these sections of the chip; Isolating the analog section from the two
digital sections reduces digital interference in the analog circuitry, Improving the dynamic performance of the converter.
Separating the digital outputs from the digital inputs (particularly the S/H input) reduces the possibility of ground bounce
from the 12 data lines ca,using jitter on the S/H input. The
analog ground plane should be connected to the Digital2
ground plane at the ground return for the power supply. The
Digital1 ground plane should be tied to the Digital2 ground
plane at the DGND1 and DGND2 pins.
Both AVec pins,should be bypassed ,to the AGND ground
plane with 0.1 p.F ceramic capacitors. One of the two AVcc
pins should also be bypassed with a 10 p.F tantalum capacitor. DVCC should be byPassed to the DGND2 ground plane
with a 0.1 p.F capacitor in parallel with a 10 p.F tantalum
capacitor.

TLIHI11490-22

FIGURE 12. PC Board Layout
7.0 DYNAMIC PERFORMANCE
The ADC12062 is AC tested and its dynamic performance is
guaranteed. In order to meet these specifications, the clock
source driving the S/H input must be free of jitter. For the
best AC performance, a crystal oscillator is recommended.
For operation at or near the ADC12062's 1 MHz maximum
sampling rate, a 1 MHz squarewave will provide a good signal for the S/H input. As long as the duty cycle is near 50%,
the waveform will be low for about 500 ns, which is within
the 550 ns limit. When operating the ADC12062 at a sample
rate of 910kHz or below, the pulse width of the S/H signal
must be smaller than half the sample period.

6.0 LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC12062, it is necessary to use appropriate circuit board
layout techniques. Separate analog and digital ground'
planes are required to meet datasheet AC and DC limits.
The analog ground plane should be low-impedance and free
of noise from other parts of the system.
All bypass capacitors should be located as close to the converter as possible and should connect to the converter and
to ground with short traces. The analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input. Any external component (e.g., a
filter capacitor) connected across the converter's input
should be connected to a very clean analog ground return
point. Grounding the component at the wrong pOint will result in Increased noise and reduced conversion accuracy.

+5V Digital

lk

MM74HC4538

Figure 12 gives an example of a suitable layout, including
power supply routing, ground plane separation, and bypass
capacitor placement. All analog circuitry (input amplifiers, '
filters, reference components, etc.) should be placed on the
analog ground plane. All digital circuitry and I/O lines (excluding the S/H input) should use the digital2 ground plane
as ground. The digital1 ground plane should only be used
for the siR signal generation.

r

0.1 J'F
4.7k

12 pF

14 V
XTAL
OSC

5 B

To

t'----+S/H
Input

4,8, II, 12,
13,14,15
TUHI11490-23

FIGURE 13. Crystal Clock Source

Figure 13 is an example of a low jitter S/H pulse generator
that can be used with the ADC12062 and allow operation at
sampling rates from DC to 1 MHz. A standard 4-pin DIP
crystal oscillator provides a stable 1 MHz squarewave.
Since most DIP oscillators have TTL outputs, a 4.7k pullup
resistor is used' to raise the output high voltage to CMOS
input levels. The output is fed to the trigger input (falling
2-580

r--------------------------------------------------------------------.~

Applications Information

C

(Continued)

edge) of an MM74HC4538 one-shot. The 1k resistor and 12
pF capacitor set the pulse length to approximately 100 ns.
The StH pulse stream for the converter appears on the Q
output of the HC4538. This is the StH clock generator used
on the ADC12062EVAL evaluation board. For lower power.
a CMOS inverter-based crystal oscillator can be used in
place of the DIP crystal oscillator. See Application Note
AN-340 in the National Semiconductor CMOS Logic Databook for more information on CMOS crystal oscillators.

converter is turned,off. but other devices connected to it (op
amps, microprocessors) still have power. Note that if there
is no power to the converter, DGND = AGND = DVee =
AVec = OV, so all inputs should be within ±300 mVof
AGND and DGND.
Driving a high capacitance digital data bus. The more
capacitance the data bus has to charge for each conversion, the more instantaneous digital current required from
DVee and DGND. These large current spikes can couple
back to the analog section, decreasing the SNR of the converter. While adequate supply bypassing and separate analog and digital ground planes will reduce this problem, buffering the digital data outputs (with a pair of MM74HC541s,
for example) may be necessary if the converter must drive a
heavily loaded databus.

8.0 COMMON APPLICATION PITFALLS
Driving Inputs (analog or digital) outside power supply
ralls. The Absolute Maximum Ratings state that all inputs
must be between GND - 300 mV and Vee + 300 mV. This
rule is most often broken when the power supply to the

9.0 APPLICATIONS
2's Complement Output

ADC12062

"::Pi..,,

MM74HC240

OB10

OB10

O B 9 1 - - - - - OB9
0~8

0~8

.

.

DBa 1 - - - - - DBa

TL/H/11490-24

Ping·Ponging between VIN1 and VIN2

l.rl.r
- - - - - - I siR

O B l l l - - - - - - - - - - - - OBll

O B O I - - - - - - - - - - - - OBO

ADC12062
r--

CLR
EOC 1 - - - - 0 ClK

so

Q ..._

....._ _ Channel

Bit

Ro Cs

TL/H/11490-2S

2-581

o....
N

Q

Q)

N

Applications Information

(Continued)

. AC Coupling Bipolar Inputs

ADC12062

VREF + (SENSE)

VREF + (FORCE)

I

I

Reference
Ladder

4.7kll

4.7 kll

VREF - (FORCE)

I

VREF- (SENSE)

0.1 ",F
Mylar

Input

I
VIN1

1----111---+-+----------------;...;;--VIN2

1

I n p u t 2 - - - - I I - - - -.....-------------.....;;~---

._---------------------_.

0.1 ",F
Mylar

TL/H/11490-26

2-582

tflNational Semiconductor

ADC12662
12-Blt, 1.5 MHz, 200 mW AID Converter
with Input Multiplexer and Sample/Hold
General Description

Features

Using an innovative multistep conversion technique, the
12-bit ADC12662 CMOS analog-to-digital converter digitizes
signals at a 1.5 MHz sampling rate while consuming a maximum of only 200 mW on a single + 5V supply. The
ADC12662 performs a 12-bit conversion in three lower-resolution "flash" conversions, yielding a fast AID without the
cost and power dissipation associated with true flash approaches.

•
•
•
•

Built-in sample-and-hold
Single + 5V supply
Single channel or 2 channel multiplexer operation
Low Power Standby mode

Key Specifications
•
•
•
•
•

The analog input voitage to the ADC12662 is tracked and
.held by an internal sampling circuit. allowing high frequency
input signals to be accurately digitized without the need for
an external sample-and-hold circuit. The ADC12662 feature
two sample-and-hold/flash comparator sections which allow the converter to acquire one sample while converting
the previous. This pipelining technique increases conversion speed without sacrificing performance. The multiplexer
output is available to the user in order to perform additional
external signal processing before the signal is digitized.

Sampling rate
Conversion time
Signal-to-Noise Ratio. fiN = 100 kHz
Power dissipation (fs = 1.5 MHz)
No missing codes over temperature

1.5 MHz (min)
580 ns (typ)
67.5 dB (min)
200 mW (max)
Guaranteed

Applications
•
•
•
•
•

When the converter is not digitizing signals. it can be placed
in the Standby mode; typical power consumption in this
mode is 250 p.W.

Digital signal processor front ends
Instrumentation
Disk drives
Mobile telecommunications
Waveform digitizers

ADC12662 Block Diagram
w

~

1il

g ei5
+
~

w

ADC IN - t - - - I H

~

~ ~

AVec DVcc

1il ~
i5
e g

'"'

::, ::,

>~

>'"
'I

Sample
and ... 12-8it A/D Converter ....
Hold

----:

MUX OUT

+1----..,

Output
Latch

&D80-

TRI~~~ATE r-,-----... DB11
Buffers

'",-' ,."_ UI. . .____. . . ______.T....,
..

v..

Timing and Control Circuitry

IN2 -

~'INT
~ EOC

I
SO

DGNO

AG'ND

Cs s,fH Rii

OE MODE

PO

Ordering Information

,-------------------,---------------------,
Industrial (- 40°C s: TA s: + 85°)
Package
ADC12662CIV

V44 Plastic Leaded Chip Carrier

ADC12662CIVF

VGZ44A Plastic Quad Flat Package

ADC12062EVAL

Evaluation Board

2-583

TUH/llB76-1

f8

....
o
C'I

c

cc

Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-O.3Vto +6V
Supply Voltage (Vee = DVee = AVeC>
Voltage at Any Input or Output
-0.3V to Vee + 0.3V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)
ADC12662CIV
ESD Susceptibility (Note 5)

,

Soldering Information (Note 6)
V Package, Infrared, 15 seconds

+300·C

VF Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

215·C
220"C
-65'Cto + 150"C

25 rnA

Storage Temperature Range

50 rnA

Maximum Junction Temperature (TJMAX)

150"C

Operating Ratings (Notes 1, 2)

875mW

Temperature Range
ADC12662CIV, ADC12662CIVF

2000V

Supply Voltage Range (DVee

TMIN:S; TA:S; TMAX
-40·C:OS; TA:S; +85'C

= AVec)

4.75V to 5.25V

Converter Characteristic~

Tl:1e following specifications apply for DVee = AVec = +5V, VREF+(SENSE) =
+4.096V, VREF-(SENSE) = AGND, and fs = 1.5 MHz, unless otherwise specified. Boldface limit. apply for TA = T..
from TMIN to TMAX; all other limits TA =;' 'I:J = '+25'C.
Symbol

Typ
(Note 7)

Limit
(Note 8)
12

Bits

±0.4

±0.9S

LSB(max)

, TMIN to TMAX

±0.4

±1.S

LSB(max)

Offset Error

TMINto TMAX

±0.3

±2.0

LSB(max)

Full-Scale Error

TMINtoTMAX

±O.3

'±1.5

LSB(max)

±0.75

LSB(max)

500
1000

o (min)
o (max)

Parameter
Resolution

Conditions
"

Differential Lin~arity Error
Integral Linearity Error
(Note 9)

Power Supply Sensitivity ,
(Note 15)

TMIN to TMAX ,

DVee

= AVec = 5V ±5%

Units
(Limit)

RREF

Reference Resistance

VREF(+)

VREF + (SENSE) Input Voltage

AVec

V (max)

VREF(-)

VREF -(SENSE) Input Voltage

AGND

V (min)

VIN

Input Voltage Range

To VIN1, VIN2, or ADC IN

AVcc+0.05V
AGND - O.OSV

V (max)
V (min)

ADC IN Input Leakage

AGNDtoAVee - 0.3V

0.1

3

p.A(max)

CADe

ADC IN Input Capacitance
MUX On-Channel Leakage

AGNDtoAVee - O.3V

0.1

3

p.A (max)

MUX Off-Channel Leakage '

A(,>ND to AVec. - 0.3V

0.1

3

p.A (max)

CMUX

750

25

Multiplexer Input Cap
MUX Off Isolation

fiN

= 100 kHz

2-584

pF

7

pF

9?

dB

Dynamic Characteristics

(Note 10) The following specifications apply for DVee = AVec = +5V,
VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, Rs = 250, fiN = 100 kHz, 0 dB from fullscale, and f9 = 1.5 MHz, unless
otherwise specified. Boldface limits appl, for T A = T.. from TMIN to TMAXi all other limits TA = TJ = + 25°C.
Symbol

Parameter

Conditions

Typ
(Note 7)

Limit
(Note 8)

Units
(Limit)

SINAD

Signal-to-Noise Plus
Distortion Ratio

TMINtoTMAX

70

07.0

dB (min)

SNR

Signal-to-Noise Ratio
(Note 11)

TMINto TMAX

70

07.5

dB (min)

THD

Total Harmonic Distortion
(Note 12)

TMINto TMAX

-80

-70

dBc(max)

ENOB

Effective Number of Bits
(Note 13)

TMINto tMAX

11.3

10.a

Bits (min)

IMD

Intermodulation Distortion

fiN

=

88.7 kHz, 89.5 kHz

-80

dBc

DC Electrical Characteristics

The following specifications apply for DVec = AVec = +5V,
VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, and f9 = 1.5 MHz, unless otherwise specified. Boldface limits appl,
for T A = T .. from TMIN to TMAXi all other limits TA = TJ = + 25°C.
Symbol

Parameter

Conditions

VIN(1)

Logical "1" Input Voltage

DVee = AVec

VIN(O)

Logical "0" Input Voltage

DVee = AVec

IIN(1)

Logical "1" Input Current

IIN(O)

Logical "0" Input Current

VOUT(1)

Logical "1" Output Voltage

=
=

Typ
(Note 7)

Limit
(Note 8)

Units
(Limit)

+5.5V

2.0

V (min)

+4.5V

o.a

V (max)

0.1

1.0

p.A(max)

0.1

1.0

p.A(max)

2.4
4.2.

V (min)
V (min)

0.4

V (max)

3

p.A(max)

DVee = AVec = +4.5V,
lOUT = - 360 p.A
lOUT = -100 p.A

VOUT(O)

Logical "0" Output Voltage

DVec = AVec = +4.5V,
lOUT = 1.6mA

lOUT

TRI-STATE Output
Leakage Current

Pins DBO-DB11

COUT

TRI-STATE Output CapaCitance

Pins DBO-DB11

CIN

Digital Input CapaCitance

0.1
5

pF

4

pF

Dlec

DVee Supply Current

2

3

mA(max)

Alec

AVec Supply Current

32

37

mA(max)

ISTANDBY

Standby Current (Dice + Alec)

PD

=

OV

50

"

2-585

p.A

~

r-----------------------------------------------------------------------------------------~

CD
CD

AC Electrical Characteristics' The following specifications apply for DVCC = AVec = +5V,
VREF+(SENSE)' = +4.096V, VREF-(SENSE)'= AGND, and fs =1.5 MHz, unless otherwise specified. Boldface limits apply
for TA = TJ from TMIN to TMAxl'ali other limits TA = TJ = + 25°C.

....
o
~

c

 Vecl the absolute value of current at that pin should be
limited to 25 rnA or less. The 50 rnA package input current limits the number of pins that can safely exceed the power supplies with an input current of 25 rnA to
two.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 8JA and the ambient temperature TA. The maximum
allowable power dissipation at any temperature is Po = (TJMAX - TA)/8JA or the number given in the Absolute Maximum Ratings, whichever is lower. 8JA for the V
(PLCC) package is 55°C/W. 8JA for the VF (PQFP) package is 62°C/W. In most cases the maximum derated power dissipation will be reached only during fault
conditions.
Note 5: Human body model, 100 pF discharged through a 1.5 kn resistor. Machine model ESD rating is 200V.
Note 6: See AN-450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section titled "Surface Mount" found in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at

+ 25°C and

represent most likely parametric norm.

Note 8: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level),

2-586

>-

C

Nole 9: Integral Linearity Error Is the maximum deviation from a straight line between the measured offset and full scale endpoints.
Nole 10: Dynamic testing of the AOC12662Is done using the ADC IN Input. The Input multiplexer adds harmonic distortion at high frequencies. See the graph in the
Typical Performance Characteristics section for a typical graph of THO performance vs Input frequency with and without the Input multiplexer.

o
....

Nole 11: The signal-to-nolse ratio Is the ratio of the Signal amplitude to the background noise level. Harmonics of the input signal are not Included In its calculation.
Note 12: The contributions from the first nine harmonics are used In the calculation of the THO.

N

Note t3: Effective Number of Bits (ENOS) is calculated from the measured signal-to-noise plus distortion ratio (SINAO) using the equation ENOS = (SINAD 1.76)/6.02.
Note 14: The digital power supply current takes up to 10 seconds to decay to Its final value after PO is pulled low. This prohibits production testing of the standby
current. Some parts may exhibit significantly higher standby currents than the 50 f'A typical.
Note 15: Power Supply Sensitivity is defined as the change in the Offset Error or the Full Scale Error due to a change In the supply voltage.

TRI-STATE Test Circuit and Waveforms
DVcc

DVcc
RD
GND

Rii

DATA
OUTPUT

ADC

I

RL
CL

DVcc
DATA
OUTPUT

TLlH/11876-2

GND
TLlH111876-3

DVCC

DVCC

DVcc

Rii
GND

Rii

DATA
OUTPUT

ADC

I~

DVcc
DATA
OUTPUT

TLlH/11876-4

GND
TL/H/11876-5

2-587

~
en

Typical Performance Characteristics'

~

Offset and Fullscale
Error Change vs
Reference Voltage

tl.50

~

TA = 25 0C,--1-'SAMPLE 1.5 MHz

:t:1.25

=

\

~ :1::1.00
to.75
to.50

~

~

~

:1:0 •.4

~

:1:0.3

380

t- -

to.S

~

r-D~ec = AVec = 5.0V

FULLSCALE

K

OFFSEIl'

I

I--

TA=250C,--_
I-fS.A"PlE = 1.5 MHz_ I--

-

'0.2

~
:::;

:to. 1

~

.......

z

~ 140

"

0.0

--

2. 1

5.0V...

4.75V

......

r-...
r-... '"

"-

2.0

.,- '"
/

1

.......

./

30

I

5.~V~

4.75V

!;;;;::;;
f-~

/
1/

§
u

~

i

~

";:::

~

15

~

110

]:

620
l

~

600

L5~_ ¢,
,
~
I

f-

.~,

/

590

\,~
580

4.75JI"
570
-55-35-15 5

5.JV

../, i
~~

- .-

--~'

J
~

";:::

~

8

25 45 65 85 105125

100 4.75V
5.0V
5.25V
95

80
70

40
DVec = AVec = 5.0V
TA = 25°C

30 20 _fSANPLE
fiN
10

'"

=I.S MHz
_=0 dB from full scale

o
10

"

r-......
~

f'N (kHz)

1000

f-J.s

sr:~~: -!780.16d:; - r - r -

I- DVee = AVec = 5.0V 1-1-

~ 17

-60dB

r

f-

TA = 25°C

liI"

. ,1.

I

-80dB

--: po'

L."

-100dB

80

160

LJ'•

320
480
640
800
240
400
560
720

AMBIENT TEMPERATURE (OC)

FREQUENCY (kHz)

SNR vs Input Frequency
(ADCln)

THO VB Input Frequency
(ADCln)
-90

-.......

60

-80

1""'-0...

-70

'""-

-60

50

ill

40
30 -

aVec = AVec = 5.DV
TA=250C

20 _fSAWPLE = 1.51.1Hz
fiN 0 dB from fullscale 10

=

10

-50

-40 DVec = AVcc = 5 . 0 V -30 --:-- TA = 25°C
'SAMPLE = 1.5 MHz
-20 ~flN = 0 dB from fullscale-10

o
100

I-

8"/5 = 1.6 MSPS.-::ttfiN = 94 kHz, 0 dB from
fullse.,. - - r NR: 71.3d8 _ _ I-

-40dB

~~

85
-55-35-15 5 25 45 65 85 105125

70

I-20dB

Ih
V

~~

90

80

50

: Spectral Response
OdB r-

105

SINAD VB Input Frequency
(ADCln)

"""-

INPUT VOLTAGE (V)

fS = 1.5 MHz

AMBIENT TEMPERATURE (OC)

60

0

EOC Delay Time (tEOC)
vs Temperature

fS'; 1.5INH;

610

140f-f-H-~'-i'-i'-i'-i'-i-;

120
100
80
~
60
40
is
20
0

ANBIENT TENPERATURE (oc)

Conversion Time (tcONV)
vs Temperature
oS
<;

5.0

~

AMBIENT TEMPERATURE (OC)

630

4.0

;:: 200 f-f-H-!HH'-i'-i'-i'-i-i
15 180 f-f-It-1HHHH-t-t-t
160 f-f-H-!It-I'-i'-i'-i'-i'-i-i

28
-55 -35-15 5 25 45 65 85 105125

25 45 65 85 105125

3.0

260r-r-r7~~~~~~~

32

I'

2.0

~ 240 f-f-H\HI- DVec = AVc,," =.E~
12W
~=25~

29
1.9
-55-35-15 5

1.0

Current Consumption In
. Standby Mode vs Voltage
on Digital Input Pins

I""'"

5.25V

33

5.25V

~

ANALOG INPUT VOLTAGE (V)

Analog Supply Current
vs Temperature
34

,.- r,.-,...

'l~

/IJ~

l:::::l::;;iOi'=

REFERENCE VOLTAGE. (VREF+)-(VREF _) (V)

2.3

~

i .\

~~f-"

100

1

1

rJ

220 AVec = 5.0V
AVec = 5.5V
180

60

Digital Supply Current
vs Temperature

...

300

0

~

0.0

REFERENCE VOLTAGE. (VREF+)-(VREF -) (V)

2.2

S

=25°C

~ 260 AVec = 4.5V
I;;
I~

~

TA

340
~

'\

ffi

'\ ~

0.00

"ii1
~

\~

~ :1:0.25

I;;

t-

\\

ffi

I

to.6

D~CC = AVec = 5.0V

~

Mux ON Resistance
vs Input Voltage

Linearity Error Change
vs Reference Voltage

o
100
f'N (kHz)

1000

10

100

1000

fiN (kHz)

TLlH/I I B76-6

2-588

Typical Performance Characteristics
SINAO VB Input Frequency
(Through Mux)

(Continued)

SNR VB Input Frequency
(Through Mux)

THO VB Input Frequency
(Through Mux)

80r---------r--------,

80r---------r--------,

-80 r - - - - - - - - - r - - - - - - - - ,

70~-.~~_t--------,

70~~~~P-__~~

-70-

SO~--------~------~

30 - TA= 2S'C ----------1

40~-------+--------,
DVCC AVec =S.OV
30 - TA=2SOC----------1

20 _ fSAWPLE

20

10~--------~------~

10

-

fiN

-l

100

1

fiN

(kHz)

90

80

7S~----+------r~'~--,

70

'

SO
.40

DVec = AVec = S.OV
......... \
65 r- TA=2S oC -----f---"'-' ' ',,''<1'\,
fiN 0 dB from fuUscale
\'

=

I
'1
........ 1
,-

60 ~

'\

70~~~~~~~~~

:
I

~

=

-lsi I.SMHz

20
10

I
I

n
'='~~~r
~

2

3

o

10000

SOURCE IMPEDANCE (n)

= 100kHz

30

o

SO~----~----~~~~

.l
I
I

aVec =AVec S.OV
-TA =2S oC----t---l
-~IH =DdB fro~m
fullscale_
fiN

60 I- fiN = 100 kHz ----+-----\1
ss ~-fs-=-'-.S+M-HZ----l.---THO
1000

1000

SNR and THO VB
Reference Voltage

- - - ......

100

100

1

fiN (kHz)

SNR and THO VB Source
Impedance

10

OL----~---~

1000

(kHz)

8Sr-~--r-----~----'
80

-20 _fSAIIIPl[= 1.5 MHz

fiN = 0 dB from""fu:;;:".=
••"'I.:---l
-10 ~--------~------~

L - - I_ _

1000

-SO I - - - - - I - -............
-'::O"'~

-40 I------I--,---~~
DVCC =AVec = 5.DV
-30 -TA=2S0C---------l

fSAMPLE = 1.5 MHz
fiN = 0 dB {rom fullscale

o '--_ _ _

OL----~---~

100

~

=

=1.5 MHz :::-.:=:;:---1
fiN =0 dB (rom fuUseele

1

-60 I - - - -.........
-p...~-__l

601-----1----............
--="-/

601-----......--1"....,..---1
so 1-----1--..............
-.::0.".,...-/
401---,----1---'---4
DVec =AVec =S.OV

1

4

5

REFERENCE VOLTAGE, (VREr+)-(VREF -) (V)

TLlH/11876-7

II

2-589

~

.~

-~
~

r---------------------------------------------------------------------------------,
Timing Diagrams
-

IAD.I_

XI

n

X

n+ 1

----------~---------~

-----------------

ITHROUGHPUT

-~
.-

n+2

'cONV

t.IS/ii

s/jj

V

troc l-

EOC

- -

so

-

n+ 1

-

~H

r-~'NTH-1 - · _ - e >- .
C
n+2

'NTl -

it-

fNr - - '

l,....-_ _ _

Ro \

OBO-OBll

~s ; ; -

l.-

-<

IACCJ
DATA (n-1)

::::'I

!=I'H,OH

DATA (n)

TLlHlllB76-9

FIGURE 1. Interrupt Interface Timing (MODE = 0, OE = 1)

V,N

_-t--JT'-_________
n+_'_ _ _ _ _ _ _ _ _ _ _n_+_2_ __
I-------ITHROUGHPUT - - - - - - - . f
1--------'cONV - - - - - \

s/ii

EDC

so
OBO-OB"

n+'

I::
Xr--------:-~--...;,.Xll'-------O-AT-A~(n~J-----'uPDATE

DATA (n - 1)

TlIH111B76-10

FIGURE 2. High Speed Interface Timing (MODE

= 0, OE = 1, CS = 0, RD = 0)
tcsH

s/ii

OE

Tl1H111876-13

FIGURE 3. CS Setup and Hold Timing for SIR, RD, and OE

2·590

l>

g
.....

Connection Diagrams

N

en
en

N

VINI

DB7

VINI

1

NC

8

38

DB6

Ne

2

VIN2

9

37

DB5

VIN2

NC

10

36

DB4

NC

MUX OUT

11

35

DB3

MUX OUT

ADC IN

12

34

NC

AGND

13

33

DB2

ADC12662CIV

0

4

33

DB7

32

DB6

31

DB5

30

DB4
DB3

ADC12662CIVF

ADC IN

NC

AGND

DB2
DBl

AVec

14

32

DBl

AVcc

DGNDl

15

31

DBO

DG~Dl

SO

16

30

EOC

SO

10

EOC

29

INT

Po

11

INT

Po
u
u

>
C

DBO

c-

'" u
zto zc z

'"
Q

C

Q

Z

U
Z

to

'"
Q

TLlH/11876-15

TLlH/11876-29

Top View

Top View

Pin Descriptions
AVec

DVcc

AGND,
DGND1,
DGND2

DBO-DBll

These are the two positive analog supply
inputs. They should always be connected
to the same voltage source, but are
brought out separately to allow for separate bypass capacitors. Each supply pin
should be bypassed to AGND with a
0.1 tJoF ceramic capacitor in parallel with a
10 tJoF tantalum capacitor.
This is the positive digital supply input. It
should always be connected to the same
voltage as the analog supply, AVec. It
should be bypassed to DGND2 with a
0.1 tJoF ceramic capacitor in parallel with a
10 tJoF tantalum capacitor.
These are the power supply ground pins.
Th,ere are separate analog and digital
ground pins for separate bypassing of the
analog and digital supplies. The ground
pins should be connected to a stable,
noise-free system ground. All of the
ground pins should be returned to the
same potential. AGND is the analog
ground for the converter. DGNDl is the
ground pin for the digital control lines.
DGND2 is the ground return for the output
databus. See Section 6.0 LAYOUT AND
GROUNDING for more information.
These are the TRI-STATE output pins, enabled by RD, CS, and OE.
These are the analog input pins to the multiplexer. For accurate conversions, no input pin (even one that is not selected)
should be driven more than 50 mV below
ground or 50 mV above Vee.

MUXOUT
ADCIN

SO

MODE
CS

2-591

This is the output of the on-board analog
input multiplexer.
This is the direct input to the 12-bit sampling AID converter. For accurate conversions, this pin should not be driven more
than 50 mV below ground or 50 mV above
Vee·
This pin selects the analog input that will
be connected to the ADC12662 during the
conversion. The input is selected based on
the state of SO when EOC makes its highto-low transition. Low selects VIN1, high
selects VIN2.
This pin should be tied to DGND1.
This is the active low Chip Select control
input. When low, this pin enables the RD,
siR, and OE inputs. This pin can be tied
low.
This is the active low Interrupt output.
When using the Interrupt Interface Mode
(Figure. 1), this output goes low when a
, conversion has been completed and indicates that the conversion result is available in the output latches. This output is
always high when RD is held low (Figure
2).
This is the End"Clf-Conversion control output. This output is low during a conversion.
This is the active low Read control input.
When RD is low (and CS is low), the INT
output is reset and (if OE is high) data appears on the data bus. This pin can be tied
low.

Pin Descriptions (Continued)
OE

This is the active high Output Enable control input. This pin can be thought of as an
inverted version of the RD input (see Figure 6). Data output pins DBO-DBll are
TRI-STATE when OE is low. Data appears
on DBO-DBll only when OE is high and
CS and RD are both low. This pin can be
tied high.
This is the Sample/Hold control inp~t. The
analog input signal is held and a new conversion is initiated by the falling edge of
this control input (when
is low).
This is the Power Down control input. This
pin should be held high for normal operation. When this pin is pulled low, the device
goes into a low power standby mode.

S/H

This pin should be bypassed to AGND with
a 0.1 p.F ceramic capaCitor.
TEST

Functional Description
The ADC12662 performs a 12-bit analog-to-digital conversion using a 3 step flash technique. The first flash determines the six most significant bits, the second flash generates four more bits, and the final flash resolves the two least
significant bits. Figure 4 shows the major functional blocks
of the converter. It consists of a 2%-bit Voltage Estimator, a
resistor ladder with two different resolution voltage spans, a
sample/hold capacitor, a 4-bit flash converter with front end
multiplexer, a digitally corrected DAC,.and a capacitive voltage divider. To pipeline the converter, there are two sample/hold capaCitors and 4-bit flash sections, which allows
the converter to acquire the next input sample while converting the previous one. Only one of the flash converter
pairs is shown in Figure 4 to reduce complexity.

es

PO

This pin should be tied to DVcc.

VREF+(FORCE)' These are the positive and negative voltVREF-(FORCE) age reference force inputs, respectively.
See Section 4, REFERENCE INPUTS, for
more information.
VREF.+(SENSE), These are the positive and negative voltVREF-(SENSE) age reference sense pins, respectively.
See Section 4, REFERENCE INPUTS, for
more information.

Hold
V,N o--+-----------~
Sample

S/H

.I. Cap

0--+---------,
VREF + (FORCE) o-....-I----....j~===.-'"T----Oi;-----I---'

V~EF+ (SENSE)

13/16

7/8

6/8
11/16
2/8
9/16

7/16

I/B

16/1024

16

15/1024

5/16

3/16

14/1024

Cap.
Vollage

13/1024

Divider

16

DBll
DB10
DB9
DBB
DB7
DB6
DB5
DB4
DB3
DB2
OBI
DBO

12/1024
I

1/1024
'VREF- (FORCE)

0-....- - - - - - - -...

. VREF- (SENSE)

0--..:..-------..1
TL/H/llB7B-1B

FIGURE 4_ Functional Block Diagram
2-592

~-------------------------------------------------------------------------, ~

CI

Functional Description (Continued)
Prior to a conversion, the Sample/Hold switch is closed,
allowing the voltage on the S/H capacitor to track the input
voitage. Switch 1 is in position 1. A conversion begins by
opening the Sample/Hold switch and latching the output of
the Voltage Estimator. The estimator decoder then selects
two adjacent banks of tap points along the MSB ladder.
These sixteen tap pOints are then connected to the sixteen
flash converters. For example, if the input voltage is between 0/16 and V16 of VREF (VREF = VREF+ - VREF-), the
estimator decoder instructs the comparator multiplexer to
select the sixteen tap points between % and % ('Yt6 and
o/1a) of VREF and connects them to the sixteen flash converters. The first flash conversion is now performed, producing the first 6 MSBs of data.

The resistor string near the center of the block diagram in
Figure 4 generates the 6-bit and 10-bit reference voltages
for the first two conversions. Each of the 16 resistors at the
bottom of the string is equal to "'It024 of the total string resistance. These resistors form the LSB Ladder' and have a
voltage drop of "'It024 of the total reference voltage (VREF +
- VREF-) across each of them. The remaining resistors
form the MSB Ladder. It is comprised of eight groups of
eight resistors each connected in series (the lowest MSB
ladder resistor is actually the entire LSB ladder). Each MSB
Ladder section has Va of the total reference voltage across
it. Within a given MSB ladder section, each of the eight MSB
resistors has 1164 of the total reference voltage across it. Tap
points are found between all of the resistors in both the
MSB and LSB ladders. The Comparator Multiplexer can
connect any of these tap points, in two adjacent groups of
eight, to the sixteen comparators shown at the right of Figure 4. This function provides the necessary reference voltages to the comparators during the first two flash conversions.

At this point, Voltage Estimator errors as large as "'It6 of
VREF will be corrected since the flash converters are connected to ladder voltages that extend beyond the range
specified by the Voltage Estimator. For example, if
Wla)VREF < VIN < (9!ta)VREF, the Voltage Estimator's comparators tied to the tap points below (o/,6)VREF will output
"1 "s (000111). This is decoded by the estimator decoder to
"10". The 16 comparators will be placed on the MSB ladder
tap pOints between (%)VREF and (%)VREF. This overlap of
("'Ita)VREF will automatically cancel a Voltage Estimator error of up to 256 LSBs. If the first flash conversion determines that the input voltage is between (%)VREF and
«%)VREF - LSB/2), the Voltage Estimator's output code
will be corrected by subtracting "1 ", resulting in a corrected
value of "01 " for the first two MSBs. If the first flash conversion determines that the input voltage is between
(%)VREF - LSB/2) and (%)VREF, the voltage estimator's
output code is unchanged.

'Note: The weight of each resistor on the LSB ladder Is actually equivalent
to four t2-bit LSBs. It is called the LSB ladder because it has the
highest resolution of all the ladders in the converter.

The six comparators, seven-resistor string (Estimator DAC
ladder), and Estimator Decoder at the left of Figure 4 form
the Voltage Estimator. The Estimator DAC, connected between VREF+ and VREF-, generates the reference voltages for the six Voltage Estimator comparators. The comparators perform a very low resolution AID conversion to
obtain an "estimate" of the input voltage. This estimate is
used to control the placement of the Comparator Multiplexer, connecting the appropriate MSB ladder section to the
sixteen flash comparators. A total of only 22 comparators (6
in the Voltage Estimator and 16 in the flash converter) is
required to quantize the input to 6 bits, instead of the 64 that
would be required using a traditional 6-bit flash.

The results of the first flash and the Voltage Estimator's
output are given to the factory-programmed on-chip
EEPROM which returns a correction code corresponding to
the error of the MSB ladder at that tap. This code is converted to a voltage by the Correction DAC. To generate the next
four bits, SWI is moved to position 2, so the ladder
voltage and the correction voltage are subtracted from the
input voltage. The remainder is applied to the sixteen flash
converters and compared with the 16 tap points from the
LSB ladder.

2-593

o
....
~

G)

N

Functional Description (Continued)

Applications Information

The result of this second conversion is accurate to 10 bits
and describes the input remainder as a voltage between two
tap pOints (VH and VLJ on the LSB ladder. To resolve the
last two bits, the voltage across the ladder resistor (between
VH and VLJ is divided up into 4 equal parts by the capacitive
voltage divider, shown in Figure 5. The divider also creates
6 LSBs below VL and 6 LSBs above VH to provide overlap
used by the digital error correction. SWI is moved to position 3, and the remainder is compared with these 16 new
voltages. The output is combined with the results of the
Voltage Estimator, first flash, and second flash to yield the
final 12-bit result.
By using the same sixteen comparators for all three flash
conversions, the number of comparators needed by the
multi-step converter is significantly reduced when compared
to standard multi-step techniques.

1.0 MODES OF OPERATION
The ADC12662 has two interface modes: An interruptI read
mode and a high speed mode. Figures 1 and 2 show the
timing diagrams for these interfaces.
In order to clearly show the relationship between SIH, CS,
RD, and DE, the control logic decoding section of the
ADC12662 is shown in Figure 6.
Interrupt Interface
As shown in Figure 1, the falling edge of SIH holds the input
voltage and initiates a conversion. At the. end of the conversion, the EDC output goes high and the INT output goes
low, indicating that the conversion results are latched and
may be read by pulling RD low. The falling edge of RD resets the INT line. Note that CS must be low to enable SIH
or RD.
High Speed Interface
The Interrupt interface works well at lower speeds, but few
microprocessors could keep up with the 1 /-'S interrupts that
would be generated if the ADC12662 was running at full
speed. The most efficient interface is shown in Figure 2.
Here the output data is always present on the databus, and
the INT to RD delay is eliminated.

VH

_1--------,
To lSB
Ladder

1VH:3VL = VL + IlSB

TLlH/11B76-17

FIGURE 5. The Capacitive Voltage Divider

ADC12662

s/H

DE

INT from internal state machine ---+l...J

TLlH/11B76-1B

FIGURE 6. ADC Control Logic

2-594

r--------------------------------------------------------------------,~

Applications Information

C

(Continued)

2.0 THE ANALOG INPUT
The analog input of the AOC12662 can be modeled as two
small resistances in series with the capacitance of the input
hold capacitor (C'N), as shown in Figure 7. The SIH switch
is closed during the Sample period. and open during Hold.
The source has to charge G,N to the input voltage within the
sample period. Note that the source impedance of the input
voltage (RSOURCE) has a direct effect on the time it takes to
charge C,N. If RSOURCE is too large, the voltage across G,N
will not settle to within 0.5 LSBs of VSOURCE before the
conversion begins. and the conversion results will be incorrect. From a dynamic performance viewpoint, the combination of RSOURCE, RMUX, Rsw, and G,N form a low pass
filter. Minimizing RSOURCE will increase the frequency response of the input stage of the converter.
Typical values for the components shown in Figure 1 are:
RMUX = lOOn, Rsw = loon, and G,N = 25 pF. The settling time to n bits is:

the maximum source impedance that will allow the input to
settle to '12 LSB (n = 13) at full speed is - 2.8 kn. To
ensure % LSB settling over temperature and device-to-device variation, RSOURCE should be a maximum of 5000.
when the converter is operated at full speed.
If the signal source has a high output impedance, its output
should be buffered with an operational amplifier capable of
driving a switched 25 pF/l00n load. Any ringing or instabilities at the op amp's output during the sampling period can
result in conversion errors. The LM6361 high speed op amp
is a good choice for this application due to its speed and its
ability to drive large capacitive loads. Figure 8 shows the
LM6361 driving the AOG IN input of an ADC12662. The 100
pF capacitor at the input of the converter absorbs some of
the high frequency transients generated by the SIH switching, reducing the op amp transient response requirements.
The 100 pF capacitor should only be used with high speed
op amps that are unconditionally stable driving capacitive
loads.

tSETILE = (RSOURCE + RMUX + Rsw) • C,N • n • In (2).
The bandwidth of the input circuit is:

Another benefit of using a high speed buffer is improved
THO performance when using the multiplexer of the
ADG12662. The MUX on-resistance is somewhat non-linear
over input voltage, causing the RG time constant formed by
C,N, RMUX, and Rsw to vary depending on the input voltage.
This results in increasing THD with increasing frequency.
Inserting the buffer between the MUX OUT and the AOC IN
terminals as shown in Figure 8 will eliminate the loading on
RMUX, significantly reducing the THO of the multiplexed system.

LSdS = 1/(2' 3.14' (RSOURCE + RMUX + Rsw)' C,N)
The AOC12662 is operated in a pipelined sequence, with
one hold capacitor acquiring the next sample while a conversion is being performed on the voltage stored on the
other hold capacitor. This gives the squrce over tCONV seconds to charge the hold capacitor to its final value. At
1.5 MHz, the settling time must be less than 667 ns. Using
the settling time equation and component values given,

•p------------------------------•
•
•

ADC12662

V,N1 •

Rt.tux

RSOURCE
,A.

••
•

MUX OUT.

VSOURCE

••
•
••

~
Rsw
ADC IN.•
,/._
,--....;.;::..:....:;..;.a.--"'S/H ~ To Comparators
:

Switch

IGN

••
•

~-------------------------------.TLlH/11876-19

FIGURE 7. Simplified ADC12662 Input Stage

2-595

o....
N

Q)
Q)

N

~

CD

....~
g

r---------------------------------------------------------------------------------,
Applications Information

(Continued)
I.-------------~----------------I

ADC12662

c(

VIN! :

Input signal

»-------------.;;.;.;.+:--

Rt.ux

VIN2 I

(Through Multiplexer)

I
I
I

MUX OUT I
I
I
I
I
I

+12V
Input signal> ___ _
(Direct)

ADC INI
I

RSW
SjH ~ To Comparators

I..L
._-----------------------------_.
I
I
I
I
I
I

C

Switch

IN

TLlH/11876-20

FIGURE 8. Buffering the Input with an LM6361 High Speed Op Amp

Correct converter operation will be obtained for input voltages greater than AGND - 50 mV and less than AVec +
50 mY. Avoid driving the signal source more than 300 mV
higher than AVec, or more than 300 mV below AGND. If an
analog input pin is forced beyond these voltages, the cur·
rent flowing through that pin should be limited to 25 mA or
less to avoid permanent damage to the IC. The sum of all

the overdrive currents into all pins must be less than 50 mA.
When the input signal is expected to extend more than
300 mV beyond the power supply limits for any reason (un·
known/uncontrollable input voltage range, power·on tran·
sients, fault conditions, etc.) some form of input protection,
such as that shown in Figure 9, should be used.

+5V

AVec

+12V

ADC12662

-12V
AGND

TLlH/11876-21

FIGURE 9. Input Protection

2·596

Applications Information (Continued)
3.0 ANALOG MULTIPLEXER

tional signal processing, such as filtering or gain, before the
signal is returned to the ADC IN input and digitized. if no
additional signal processing is required, the MUX OUT pin
shouid be tied directly to the ADC IN pin.
See Section 9.0 (APPLICATIONS) for a simple circuit that
will alternate between the two inputs while converting at full
speed.

The ADC12662 has an input multiplexer that is controlled by
the logic level on pin SO when EOC goes low, as shown in
Figures 1 and 2. Multiplexer setup and hold times with respect to the siR Input can be determined by these two
equations:
tMS (wrt S/Fi) = tMS - tEee (min) = 50 - 60 = -IOns
tMH (wrt SIFi) = tMH + tEee (max) = 50 + 125 = 175 ns
Note that tMS (wrt S/Fi) is a negative number; this indicates
that the data on SO must become valid within IOns after
SIR goes low in order to meet the setup time requirements.
SO must be valid for a length of

4.0 REFERENCE INPUTS
In addition to the fully differential VREF+ and VREF- reference inputs used on most National Semiconductor ADCs,
the ADC12662 has two sense outputs for precision control
of the ladder voltage. These sense inputs compensate for
errors due to IR drops between the reference source and
the ladder itself. The resistance of the reference ladder is
typically 750n. The parasitic resistance (Rp) of the package
leads, bond wires, PCB ,traces, etc. can easily be 0.5n to
1.0n or more. This may not be significant at 8-bit or 10-bit
resolutions, but at 12 bits it can introduce voltage drops
causing offset and gain errors as large as 6 LSBs.
The ADC12662 provides a means to eliminate this error by
bringing out two additional pins that sense the exact voltage
at the top and bottom of the ladder. With the addition of two
op amps, the voltages on these internal nodes can be
forced to the exact value desired, as shown in Figure 10.

(tMH + tEee (max) - (tMS - tEee (min) = 185 ns.
Table I shows how the input channels are assigned:
TABLE I. ADC12662 Input
Multiplexer Programming
SO

Channel

0
1

VINI
VIN2

The output of the multiplexer is available to the user via the
MUX OUT pin. This output allows the user to perform addi-

r-----------------------

I
I

1 kll

VREF + (SENSE) : Rs

ADC12662
4.096V

SOOll
/
>-~---..-.....wv--.

I

LM4040 - 4.1

I

til

Vref = (Vref+)-(Vref-) = 4.096V
Rf = O.Sll (force line impedance)
Rs = lOll (sense line impedance)
Rladder = 7S011

O.OOOV

/

Reference

Ladder

OP-07
lkll

L....---------+---'\M..--------I.JII\ro-.....
VREF- (SENSE) I
I
I

._----------------------

TL/HI11878-22

FIGURE 10. Reference Ladder Force and SenHlnpute

2-597

Applications Information (Continued)
Since the current flowing through the SENSE lines is essentially zero, there is negligible voltage drop across Rs and the
1 kn resistor, so the voltage at the inverting input of the op
amp accurately represents the voltage at the top (or bottom).of the ladder. The op amp drives ~he FORCE. input and
forces the. voltage at the ends of the ladder to equal the
voltage at the op amps's non-iilVerting input, plus or minus
its input offset voltage. For this reason op amps with low
Ves, such as the LM627 or LM607, should be used for this
application. When used in this configuration, the ADC12662
has less than 2 LSBs of offset and 1.5 LSB of, gain error
without any user adjustments.

The reference inputs are fully differential and define the
zero to full-scale range of. the input Signal. They can be
configured to span up to 5V (VREF- = OV, VREF+ = 5V),
or they can .be connected to different voltages ·(within the
OV to 5V limits) when other input spans are required. The
ADC12662 is tested at VREF·- (SENSE) = OV, VREF+
(SENSE) = 4.096V. Reducing the reference voltage span to
less than 4V increases the sensitivity (reduces the LSB size)
of .the converter; however noise performance degrades
when lower reference voltages are used. Aplo~ of ,dynamic
performance vs reference voltage is given in the Typical
Performance Characteristics section.

The 0.1 ,...F and 10 ,...F capacitors on the force inputs provide high frequency decoupling of the reference ladder. The
500n force resistors isolate the op amps from this large
capacitive load. The 0.01 ,...F/1 kn network provides zero
phase shift at high frequencies to ensure stability .. Note that
the op amp supplies in this example must be ± 1OV to
± 15V to meet the inpull output voltage range requirements
of the LM627 and ·supply the sub-zero voltage to the
VREF- (FORCE) pin. The VREF/16 output should be bypassed to analog.ground with a 0.1 ,...F ceramic capacitor.

If the converter will be used in an application where DC
accuracy is secondary to dyna~ic performance, then a simpler reference circuit may.suffice. The circuit shown in Figure 11 will introduce several LSBs of offset and gain error,
but INL, DNL, and all dynamic specifications will be unaffected.
All bypass capacitors should be located as close to the
ADC12662 as possible to minimize noise on the reference
ladder. The VREF/16 output shoiJld be bypassed to analog
ground with a 0.1 ,...F ceramic capacitor.
The LM4040 shunt voltage reference is available with a
4.096V output voltage. With initial accuracies as low as
± 0.1 %, it makes an excellent reference for the ADC12662.

ADC12662

VREF + (SENSE)

+5:!'f:.5 %

NC-!----,
4.096V

~

60n
LM4040 - 4.1

4.093V
VREF+(FORCE)

/

,".~-1-0-1'-~F""-O-.I-I'-"~""'----i--""·
.4~

I

-== -

I

.

1~

~

'"

VREF/16

1-'

Reference
Ladder

~
~
~

'"
~

--~

VREF - (FORCE)

. VREF - (SENSE)

i

NC-+-......

""

O.003V

.
----------------------.

FIGURE 11. Using the VREF Force Pins Only

2-598

,

TL/H/11876-23

r--------------------------------------------------------------------,~

Applications Information

o
o....

(Continued)

~

From Power Supply

5.0 POWER SUPPLY CONSIDERATIONS
The ADC12662. is designed to operate from a single + 5V
power supply. There are two analog supply pins (AVcC> and
one digital supply pin (DVcC>. These pins allow separate
external bypass capacitors for the analog and digital por·
tions of the circuit. To guarantee proper operation of the
converter, all three !!upply pins should be connected to the
same voltage source. In systems with separate analog and
digital supplies, the converter stiould be powered from the
analog supply.
The ground pins are AGND· (analog ground), DGND1 (digital
input ground), and DGND2 (digital output ground). These
pins allow for three separate ground planes for these sections of the chip. Isolating the analog section from the two
digital sections reduces digital interference in the analog circuitry, improving the dynamic performance of the converter.
Separating the digital outputs from the digital inputs (particularly the SIR input) reduces the possibility of ground bounce
from the 12 data lines causing jitter on the SIR input. The
analog ground plane should be connected to the Digital2
ground plane at the ground return for the power supply. The
Digital1 ground plane should be tied to the Digital2 ground
plane at the DGND1 and DGND2 pins.
Both AVcc pins should be bypassed to the AGND ground
plane with 0.1 poF ceramic capacitors. One of the two AVec
pins should also be bypassed with a 10 poF tantalum capacitor. DVcc should be bypassed to the DGND2 ground plane
with a 0.1 poF capacitor in parallel with a 10 poF tantalum
..
.
capacitor.

N

TUH/11876-24

FIGURE 12. PC Board Layout
7.0 DYNAMIC PERFORMANCE
The ADC12662 is AC tested and its dynamic performance is
guaranteed. In order to meet these specifications, the clock
source driving the SIR input must be free of jitter. For the
best AC performance, a crystal oscillator is recommended.
For operation at or near the ADC12662's 1.5 MHz maximum
sampling rate, a 1.5 MHz squarewave will provide a good
signal for the SIR input. As long as the duty cycle is near
50%, the waveform will be low for about 333 ns, which is
within the 400 ns limit. When operating the ADC12662 at a
sample rate of 1.25 MHz or below, the pulse width of the
slH signal must be smaller than half the sample period.

6.0 LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC12662, it is necessary to use appropriate circuit board
layout techniques. Separate analog and digital ground
planes are required to meet datasheet AC and DC limits.
The analog ground plane should be low-impedance and free
of noise from other parts of the system.
All bypass capacitors should be located as close to the converter as possible and should connect to the converter and
to ground with short traces. The analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input. Any external component (e.g., a
filter capacitor) connected across the converter's input
should be connected to a very clean analog ground return
point. Grounding the component at the wrong point will result in increased noise and reduced conversion accuracy.
Figure 12 gives an example of a suitable layout, including
power supply routing, ground plane separation, and bypass
capacitor placement. All analog circuitry (input amplifiers,
filters, reference components, etc.) should be placed on the
analog ground plane. All digital circuitry and 110 lines (excluding the SIR input) should use the digital2 ground plane
as ground. The digital1 ground plane should only be used
for the SIH signal generation.

fII

+5V Digital

lk

MM74HC453B

12 pf
Q 6

(i7VLr

To

S/H
Input

4. B. 11. 12.
13.14.15

TUH/11876-25

FIGURE 13. Crystal Clock Source

Figure 13 is an example of a low jitter SIR pulse generator
that can be used with the ADC12662 and allow operation at
sampling rates from DC to 1.5 MHz. A standard 4-pin DIP
crystal oscillator provides a stable 1.5 MHz squarewave.
Since most DIP OSCillators have TIL outputs, a 4.7k pullup
resistor is used to raise the output high voltage to CMOS
input levels. The output Is fed to the trigger input (falling

2-599

Applications Information (Continued)
edge) of an MM74HC4538 one-shot. The 1k resistor and
12 pF capacitor set the pulse length to approximately 100
ns. The SIR pulse stream for the converter appears on the
Q output of the HC4538. This is the SIR clock generator
used' on the ADC12062EVAL evaluation board. For lower
power, a CMOS inverter-based crystal oscillator can be
used in place of the DIP crystal oscillator. See Application
Note AN-340 in the National Semiconductor CMOS Logic
Databook for more information on CMOS crystal oscillators.

converter is turned off, but other devices connected to it (op
amps; microprocessors) still have power. Note that if there
is no power to the converter, DG·ND = AGND = DVee =
AVec = OV, so all inputs should be within ±300 mV of
AGND and DGND.
Driving a high capacitance digital data bus. The more
capacitance the data bus has to charge for each conversion, the more instantaneous digital current required from
DVee and DGND. These large current spikes can ·couple
back to the analog section, decreasing the SNR of the converter. While adequate supply bypassing and separate analog and digital ground planes will reduce this problem, buffering the digital data outputs (with a pair of MM74HC541s,
for example) may be necessary if the converter must drive a
heavily loaded databus.

8.0 COMMON APPLICATION PITFALLS
Driving Inputs (analog or digital) outside power supply
rail•• The Absolute Maximum Ratings state that all inputs
must be between GND - 300 mVand Vee + 300 mY. This
rule is most often broken when the power supply to the

9.0 APPLICATIONS
2's Complement Output

ADC12662
OBll
O B 1 0 t - - - - - DB10
OB9

DB9

0~8

,

D~8

Olio

DaO

,

TUH/11876-26

Plng-Ponglng between VINt .and VINZ

1..l1.r

OBll

sjii

DBll

,
,
,,

,
,,

DBO

DBD

ADC12662

ClR
EOC

r-- SO

Roes

VV

ClK

1
0

PR

Q

Channel
Bit

o~
TL/H/11876-27

Applications Information (Continued)
AC Coupling Bipolar Inputs

.----------------------I

VREr + (SENSE):

~;>------------------;I----'

ADC12662

••

VREF + (FORCE) •

.....

10J.l~0.IJ.I~

I-

I-

-

I k/l

10011
20-Turn

-

0.1 J.I;J",

I

Reference
Ladder

I

10J.l~0.IJ.I~

I
I kll

4.7 kll

4.7 kll

...

VREr_ (FORCE)

10J.lg;;

I-

-

...
0.1 J.lF
My

Input 1
Input 2

I'r
II
0.1 J.lF

O.'J.I~

:

-..

I:
-

••
._----------------------

Mylar

TL/H/11878-28

2-601

y- r-------------------------------------------------------------------------------~

•

~

I!fINational Semiconductor

ADC 1241 Self-Calibrating 12-Bit Plus
Sign JLP-Compatible AID Converter
with Sample-and-Hold .
General Description

Key SpeCifications

The ADC1241 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter. On request, the
ADC1241 goes through a self-calibration cycle that adjusts
positive linearity and full-scale errors to less than ± Y:z LSB
each and zero error to less than ± 1 LSB. The ADC1241
also has the ability to go through an Auto-Zero cycle that
corrects the zero error during every conversion.
The analog input to the ADC1241 is tracked and held by the
internal circuitry, and therefore does not require an external
sample-and-hold. A unipolar analog input voltage range (OV
to + 5V) or a bipolar range (- 5V to + 5V) can be accommodated with ± 5V supplies.

•
•
•
•
•
•

The 13-bit word on the outputs of the ADC1241 gives a 2'5
complement representation of negative numbers. The digital inputs and outputs are compatible with TIL or CMOS
logic levels.

12 Bits plus Sign
13.8",5 (max)
±Y:z LSB (±0.0122%) (max)
±1LSB (max)
±1LSB (max)
70mW (max)

Resolution
Conversion Time
Linearity Error
Zero Error .
Positive Full Scale Error
Power Consumption

Features
• Self-calibrating
• Internal sample-and-hold
• Bipolar input range with ± 5V supplies and single
+ 5V reference
• No missing codes over temperature
• TIL/MaS input/output compatible
• Standard 28-pin DIP

Applications
• Digital Signal Processing
• High Resolution Process Control
• Instrumentation

Simplified Schematic
Y,N

Connection Diagram

0-2--,.. ........_--_------1

Dual-In-Line Package
VIN

28

DV~

VREF

27

DBI2(5Ign)

AGND

4

AV~~

3

AY~

2

Y-

VREF~
3

AI

AGHD~

6

Viii

5

CLKIN

V-~

DBO (LS9)
D91

26

DB11(M5B)

25

DBl0

24

089

23
ADC1241 22
21

DB8
DB7
DB6

CAL

9

20

DBS

cs

10

19

DB4

D92

Rii

11

lB

DB3

DB3

EOC

12

17

DB2

DB4

iiif

13

16

DBI

DB5

DOND

14

IS

DBO(LSB)

DB6
TL/HI1 0554-2

D97
D9B

D99
D91D
D911 (MSB)
D912 (Sign)

Conlrolloglc

TLJH/1D554-1

2-602

Top View

Order Number ADC1241CMJ,
ADC1241CMJ/883, ADC1241BIJ or
ADC1241CIJ
See NS Package Number J28A

Operating

Absolute Maximum Ratings

(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
6.5V
Supply Voltage (Vee = DVee = AVec)
-6.5V
Negative Supply Voltage (V-)
Voltage at Logic Control Inputs
Voltage at Analog Input (VIN)

Temperature Range
TMIN:;:;TA:;:;TMAX
ADC1241 BIJ, ADC1241 CIJ
-40'C:;:;TA:;:; + 85'C
ADC1241CMJ, ADC1241CMJ/883 -55'C:;:;TA:;:; + 125'C
DVee and AVee Voltage
(Notes 6 & 7)
Negative Supply Voltage (V-)

-0.3Vto (Vee + 0.3V)
(V- -0.3V) to (Vee + 0.3V)

Reference Voltage
(VREF, Notes 6 & 7)

0.3V
±5mA

AVec-DVee (Note 7)
Input Current at any Pin (Note 3)
Package Input Current (Note 3)

»
c

R~tings (Notes 1 &2)

o
.....
N

~

.....

4.5Vto 5.5V
-4.5V to -5.5V
3.5Vto AVec + 50 mV

±20mA
875mW

Power Dissipation at 25'C (Note 4)
Storage Temperature Range

-65'Cto + 150'C
2000V

ESD Susceptability (Note 5)
Soldering Information
J Package (10 sec)

300'C

Converter Electrical Characteristics
The following specifications apply for Vee = DVee = AVec = +5.0V, V- = -5.0V, VREF = +5.0V, and feLK = 2.0 MHz
unless otherwise specified. Boldface limits apply for TA = T J = T MIN to T MAX; all other limits TA = TJ = 25'C. (Notes 6, 7
and 8)
Symbol

Parameter

Conditions

Typical
Limit
(Note 9) (Notes 10, 18)

Units
(Limit)

STATIC CHARACTERISTICS
Positive Integral
Linearity Error

After Auto·Cal
(Notes 11 & 12)

±%
±1

LSBmax

After Auto-Cal
(Notes 11 & 12)

±1

LSB(max)

±1

LSB(max)

Differential Linearity

After Auto-Cal (Notes 11 & 12)

'12

Bits(min)

Zero Error

After Auto-Zero or Auto-Cal
(Notes 12 & '13)

±1

LSB(max)

±1

LSB(max)

±11 ±2

LSB(max)

Negative Integral
Linearity Error

ADC1241BIJ
ADC1241CMJ, CIJ
ADC1241BIJ
ADC1241 CMJ, CIJ

Positive Full-Scale Error

After Auto-Cal (Note 12)

Negative Full-Scale Error

After Auto-Cal (Note 12)

±v.

CREF

VREF Input Capacitance

80

CIN

Analog Input Capacitance

65

VIN

Analog Input Voltage
Power Supply
Sensitivity

pF
pF

V- - 0.05
Vee + 0.05
Zero Error (Note 14) AVec = DVcc = 5V ±5%,
VREF = 4.75V, V- = -5V ±5%
Full-Scale Error
Linearity Error

LSB(max)

V(min)
V(max)

±'Is

LSB

±'Is

LSB

±'Is

LSB

dB

DYNAMIC CHARACTERISTICS
S/(N+D) Unipolar Signal-to-Noise+ Distortion
Ratio (Note 17)

fiN = 1 kHz, VIN = 4.85 Vp_p

72

fiN = 10kHz, VIN =, 4.85 Vp_p

72

dB

S/(N+D) Bipolar Signal-to-Noise + Distortion
Ratio (Note 17)

fiN = 1 kHz, VIN = ±4.85 Vp_p

76

dB

tAp

fiN = 10 kHz, VIN = ±4.85 Vp_p

76

dB

Unipolar Full Power Bandwidth (Note 17)

VIN = OV to 4.85V

32

kHz

Bipolar Full Power Bandwidth (Note 17)

VIN = ±4.85 Vp_p

25

kHz

Aperture Time

100

ns

Aperture Jitter

100

PSrms

2-603

EI

DigibJl and DC Electrical Characteristics

The following specifications apply for VCC = DVee = AVcc =
unless otherwise specified. Boldface limits apply for TA = TJ
(Notes 6 and 7)
Symbol

Parameter

+ 5.0V, V- =

-5.0V, VREF = + 5.0V, and fClK = 2.0 MHz
= TMIN to TMAX; all other limits TA = TJ = 25°C.

Condition

VIN(1)

logical "1" Input Voltage for
All Inputs except ClK IN

Vee

= 5.25V

VIN(O)

logical "0" Input Voltage for
All Inputs except ClK IN

Vcc

= 4.75V

IIN(1)

Logical "1" Input Current

VIN

IIN(O)

logical "0" Input Current

VIN

= 5V
= OV

VT+

Typical
(Note 9)

Limit
(Notes 10, 18)

Units
(Limits)

2.0

V(min)

0.8

V(max)

0.005

1

/-lA(max)

-0.005

-1

/-lA(max)

ClK IN Positive-Going
Threshold Voltage

2.8

2.7

V(min)

VT-

CLK IN Negative-Going
Threshold Voltage

2.1

2.3

V(max)

VH

ClK IN Hysteresis
IVT+(mln) - VT-(max))

0.7

0.4.

V(min)

VOUT(1)

logical "1" Output Voltage

2.4
4.5

V(min)
V(min)

Vee = 4.75V:
lOUT = -360/-lA
lOUT = -10/-lA

VOUT(O)

logical "0" Output Voltage

Vee = 4.75V
lOUT = 1.6mA

lOUT

TRI-STATEIII> Output leakage
Current

= OV
= 5V
VOUT = OV
VOUT = 5V
fClK = 2 MHz, CS = "1"
fClK = 2 MHz, CS = "1"
fClK = 2 MHz, CS = "1"

·ISOURCE

Output Source Current

.ISINK

Output Sink Current

Dlee

DVee Supply Current

Aicc

AVee Supply Current

I-

V- Supply Current

0.4 ...

V(max)

VOUT

-0.01

-3

J1A(max)

VOUT

0.01

3

/-lA(max)

-20

-8.0

mA(min)

20

8.0

mA(min)

1

2

mA(max)

2.8

8

mA(max)

2.8

8

mA(max)

2-604

J>

AC Electrical Characteristics
The following specifications apply for DVcc = AVcC = +5.0V. V- = -5.0V. Ir = tf = 20 ns unless otherwise specified.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25'C. (Notes 6 and 7)
Symbol
fClK

Parameter

Conditions

Typical

Limit

Units

(Note 9)

(Notes 10. 18)

(Limits)

2.0

Clock Frequency

Clock Duty Cycle

tc

Conversion Time

MHz(min)

4.0

MHZ(max)

27(IIfClK)

tA

Acquisition Time

RSOURCE = 500.

(Note 15)

fClK = 2.0 MHz

tz

Aula Zero Time

toAi:

Calibration Time

tw~)l

Calibration Pulse Width

tw{WFj)l

Minimum WFi Pulse Width

tACC

Maximum Access Time

%
40

%(min)

60

% (max)

27(1/fcLK>

+ 300ns

13.5

fClK= 2.0 MHz

7(l/fClK)

+ 300ns

(Note 16)

(max)
"s

26

fClK = 2.0 MHz

(max)
"s

7(1/fCLK>

3.5

fClK = 2.0 MHz

N

.....
""'

MHz

0.5

50

g.....

26

lIfCLK(max)

13

"s

1396

llfClK

698

706

"s (max)

60

200

ns(min)

60

200

ns(min)

50

85

ns(max)

30

90

ns(max)

100

175

ns(max)

Cl = 100pF

(Delay from Falling Edge of
RD to Output Data Valid)
toH. t'H

TRI-STATE Control (Delay

Rl=lkn.

from Rising Edge of AD

Cl = '100pF

to Hi-Z State)
tpO(lN'i')

Maximum Delay from Falling Edge of
RD or WFi to Reset of iiiii

Note 1: Absolute Maximum Ratings Indicate Hmils beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. but do not guarantee specific performance limits. For guaranteed specRications and test conditions. see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to AGND and DGND. unless otherwise specified. ,
Note 3: When the Input voltage (VIN> at any pin exceeds the power supply rails (VIN < V- or VIN > (AVec or DVcC>. the current at that pin should be Hmited to
SmA. The 20 mA maximum package input current rating allows the vottage at any four pins. with an input current limit of S rnA. to simultaneously exceed the power
supply voltages.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX (maximum junction temperature). 6JA (package
junction to ambient thermal resistance). and TA (ambient temperature). The maximum allowable power dissipation at any temperature is POmax ~ (TJmax T/'JIllJA or the number given In the Absolute Maximum Ratings. whichever is lower. For this device. TJmax ~ 12S·C. and the typical thermal resistance (6J/'J of the
ADC1241 with CMJ. BIJ. and CIJ suffixes when board mounted is 47'C/W.
Note 5: Human body model. 100 pF discharged through a 1.5 kO resistor.
Note 6: Two on-chip diodes are tied to the analog input as shown below. Errors In the Ala conversion can occur if these diodes are forward biased more than
SOmV.

DVec

28

,,r-VIN

1

, ..
,, -:..

-----

~

TO INTERNAL

CIRCUITRY

I

._-

~

-----

5

yTLlH110554-3
TIIII _ilia! H AVec IIICI DVec are minimum (4.75 Voc)lIICI V- 18 mulmum (-4.75 Voc). full·1CU must be :;; 4.8 Voc,

2·805

EI

AC Electrical Characteristics

'"

(Continued)

.

Note 7: A diode exists between AVec and DVec as shown below.

•I
.

I

'

A v e c : r r : TO INTERN,AL
I
CIRCUITRY
I
I

DVec 28

'I
I
I

'

TO INTERNAL
CIRCUITRY
.

TL/H/l0554-4
To guarantee accuracy, It is required that the AVec and DVec be connected together to a power supply with separate bypass fitters at each Vee pin.
Nole 8: Accuracy Is guaranteed at feLK = 2.0 MHz. At higher and lower clock frequencies accuracy may degrade. See curves In the Typical Performance
Cheracteristics Section.
'
,'
Nole 9: Typlcals are al TJ = 25"C and represent most likely parametric nonn.
Note 10: Umits are guaranteed to National's AOOL (Average Outgoing Quality Level)•.
Note 11: Positive linearity error Is deflned as the deviation of the analog value, expressed In LSBs, from the straight line that passas thro~gt\ positlv~ full scale and'
zero. For negative Iinaarity error the straight line passes Ihrough negative full scale and zero. (See FI{Jures. tb and ttl).
Note 12: The ADC1241's self-calibration technique ensures linearity, full scale, and aflset errors as specified, but noise inherenllnthe self-calibration process will
. result In a repeatability uncertainty of ±0.20 LSB.
'
Note 13: If TA changes then an Aulo-Zero or Aulo-cal cycle will have 10 be re-started, see Ihe typical performance characteristic curves.
Note 14: After an Auto-Zero Or Auto-Cal cycle allhe specified power supply extremes.
Note 15: If the clock is asynchronous to the falling edge of WFI an uncertainty of one clock period will exist In Ihe interval of lA, Iherefore making'the minimum tA '=
6 clock periods and the maximum IA = 7 clock periods. If the falling edge of Ihe clock Is synchronous to the rising edge of WR then tA will be exactly 6.5 clock

ps"ods.
Note 16: The rns:c line musl be high before any other conversion is started. ,
Note 17: The specifications for these parameters are valid after an Auto-Cal cycle has been completed.
Note 18: A military RETS elect"callesl spscification Is available on requesL AI time of printing; the ADC1241CMJ/883 RETs'speCification complies fully WIth llie'
boldface limits In Ihls column.
"
"
.

(+4095)0,1111,1111,1111
(+4094) 0,1111,1111,1110

2)

!;

0,0000,0000,0001 _--r--I-l~::::==~Z~ER~02TRA~NS~m~O~N_ _ _ _ _ _~
1-------- ~0)1) 0,0000,0000,0000
"
'
INPUT VOLTAGE
0,0000,0000,0010

' +~REF

§ -VREF
""
""",

r.::::

"",

FULL-SCALE TRANSITION

1,0000,0000,0001 (-4095)
1,0000,0000,0000 (-4096)
ANALOG INPUT VOLTAGE (VIN)
TUH/l0554-5

FIGURE 1a. Transfer Characteristic

2·606

:I>

c

AC Electrical Characteristics (Continued)

o
.....

...,

~

.....

+I2LS8

OUTPUT CODE

(from -4096 to +4095)

TLiH/I0554-6

FIGURE 1b. Simplified Error Curve vs Output Code Without Auto-Calor Auto-Zero Cycles

+3LS8

NEGAllVE INPUT RANGE

-2LS8

POS1IIVE INPUT RANGE

-3LS8
OUTPUT CODE
(from -4096 to +4095)

TL/H/10554-7

FIGURE 1c. Simplified Error Curve vs Output Code After Auto-Cal Cycle

Typical Performance Characteristics

1.6

I"

§'1.2
.:!!. 1.0

i

~

DB

:

~

\
\

AVec = DVec = +5.0V
V"=-5.DV
fCLJ( = 2NHz
TA = +25OC

,

o
o

I

.... ~ ~

1\

"-

Q.2

2

•

Zero Error Change vs
Ambient Temperature

Zero Error vs VREF

"., ~
I""

"

~

AVec=DVec = +5.oV
V"=-5.DV
fax = 2NHz
VREF = +5.DV
No eolllnUon
No Autozero

-2
-55 -35 -15 5 25 015 65 85 lOS 125

3
VREF (V)

AMBIENT TDlPERATURE (OC)

2-807

TL/HI10554-6

~ r---------~----------------------------------------------------------------------------------__,

~
~

o
~

Typical Performance Characteristics

Linearity Error vs Clock
Frequency

Linearity Error vs VREF
1A

:!!.

I

I

AVec = DYec = +S.DY
=-5.DY
fClJ( = 2 MHz
TA = +25CC

or

\

lD

\

\

OB
0.&

,

lD

O:J AVec=OVec = +5.0V
y"=-5.OV
vI/EF = +5.OV
:!!.o.s TA = +25CC

i

112

or=-5.OV

-

'I

I

M

2

o
o

3

-

-ID
a.OCK fREQUENCY (MHz)

Bipolar Signal-to- '
Noise + Distortion Ratio vs
Input Frequency
90

Unipolar Signal-toNoise + Distortion Ratio vs
Input Frequency

,

"'

80

:!

N.:!,'"
Rs=2000
V/N=t2.5Vp-p

70

.

~

C~

I

_r_,

1/N=1 kHz
I

AYt:cD'lcc·YIEl'CI.5.O¥'

X

o
o

100

100

200 300 400 500 600

INPUT SOURCE IMPEDANCE (A)

Unipolar Signal-toNoise + Distortion Ratio vs
Input Signal Level

+

I

10
INPUT fREQUENCY (kHz)

Bipolar Signal-toNoise Distortion Ratio vs
Input Signal Level
'

1

r--

or=-5.OV

1.0

" I

IIVIN=U.sVp-p

1

r-'/N=25kHz
T.=25CC
AVec= ovec =VI/EF=+5.OV
20 or=-S.DY
r-fClJ(=2MHz
r-Sampling froqu ...y = 55 kHz

Rs-200l1 """-'
,V/N=2.5Vp-p
80 T.:25CC
AVec = OVec =VI/U=+5.DY
50
fClJ(=211Hz
SompOng froquollCy = 55 kHz

40

100

VIN=t5.0Vp-p

Ti
1

INPUT fREQUENCY (kHz)

v.... I.O,"
T......

80

V/N = 5.0 Vp-p

8"

TA =25CC
DYec = AVec =VI/EF =+S.OV
or=-5.DY
50
fClJ(=2MHz
Sampling frequency = 55 kHz
40
lD
10

lis·.....

I

111111

80

.1
.,....

IJI

11111

Bipolar Signal-toNoise + Distortion Ratio vs
Input Source Impedance

90

V'N=t5Vp-p
80

-55 -35 -15 5 ZI 

c

1.0 Pin Descriptions
DVee (28),
AVec (4)

V- (5)

DGND (14),
AGND (3)

The digital and analog ground pins. AGND
and DGND must be connected together externally to guarantee accuracy.

VREF(2)

The reference input voltage pin. To maintain
accuracy the voltage at this pin should not
exceed the AVec or DVee by more than
50 mV or go below 3.5 VDC.

VIN (1)

The analog input voltage pin. To guarantee
accuracy the voltage at this pin should not
exceed Vee by more than 50 mV or go below
V- by more than 50 mY.

CS (10)

The Chip Select control input. This input is
active low and enables the WR and RD functions.

RD (11)

The Read control input. With both CS and RD
low the TRI-STATE output buffers are enabled and the INT output is reset high.
The Write control input. The converison is
started on the rising edge of the WR pulse
when CS is low.
The external clock input pin. The clock frequency range is 500 kHz to 4 MHz.

WR(7)

CLK(8)
CAL (9)

AZ(6)

EOC(12)

INT(13)

DBO-DB12
(15-27)

The digital and analog positive power supply
pins. The digital and analog power supply
voltage range of the ADC1241 is + 4.5V to
+ 5.5V. To guarantee accuracy, it is required
that the AVec and DVee be connected together to the same power supply with separate bypass filters (10 p.F tantalum in parallel
with a 0.1 p.F ceramic) at each Vee pin.
The analog negative supply voltage pin. Vhas a range of -4.5V to -5.5V and needs a
bypass filter of 10 p.F tantalum in parallel with
a 0.1 p.F ceramic.

The TRI-STATE output pins. The output is in
two's complement format with DB12 the sign
bit, DB11 the MSB and DBO the LSB.

....o
N

....""

2.0 Functional Description
The ADC1241 is a 12-bit plus sign AID converter with the
capability of dOing Auto-Zero or Auto-Cal routines to minimize zero, full-scale and linearity errors. It is a successiveapproximation AID converter consisting of a DAC, comparator and a successive-approximation register (SAR). AutoZero is an internal calibration sequence that corrects for the
AID's zero error caused by the comparator's offset voltage.
Auto-Cal is a calibration cycle that not only corrects zero
error but also corrects for full-scale and linearity errors
caused by DAC inaccuracies. Auto-Cal minimizes the errors
of the ADC1241 without the need of trimming during its fabrication. An Auto-Cal cycle can restore the accuracy of the
ADC1241 at any time, which ensures its long term stability.
2.1 DIGITAL INTERFACE
On power up, a calibration sequence should be initiated by
pulsing CAL low with CS, RD, and WR high. To acknowledge the CAL signal, EOC goes low after the falling edge of
CAL, and remains low during the calibration cycle of 1396
clock periods. During the calibratioFl sequence, first the
comparator's offset is determined, then the capacitive
DAC's mismatch error is found. Correction factors for these
errors are then stored in internal RAM.
A conversion is initiated by taking CS and WR low. The AZ
(Auto Zero) signal line should be tied high or low during the
conversion process. If AZ is Iowan auto zero cycle, which
takes approximately 26 clock periods, occurs before the actual conversion is started. The auto zero cycle determines
the correction factors for the comparator's offset voltage. If
AZ is high, the auto zero cycle is skipped. Next the analog
input is sampled for 7 clock periods, and held in the capacitive DAC's ladder structure. The EOC then goes low, signaling that the analog input is no longer being sampled and
that the AID successive approximation conversion has
started.

The Auto-Calibration control input. When
CAL is low the ADC1241 is reset and a calibration cycle is initiated. During the calibration cycle the values of the comparator offset
voltage and the mismatch errors in the capacitor reference ladder are determined and
stored in RAM. These values are used to correct the errors during a normal cycle of AID
conversion.
The Auto-Zero control input. With the AZ pin
held low during a conversion, the ADC1241
goes into an auto-zero cycle before the actual AID conversion is started. This Auto-Zero
cycle corrects for the comparator offset voltage. The total conversion time (tel is increased by 26 clock periods when Auto-Zero
is used.

During a conversion, the sampled input voltage is successively compared to the output of the DAC. First, the acquired input voltage is compared to analog ground to determine its polarity. The sign bit is set low for positive input
voltages and high for negative. Next the MSB of the DAC is
set high with the rest of the bits low. If the input voltage is
greater than the output of the DAC, then the MSB is left
high; otherwise it is set low. The next bit is set high, making
the output of the DAC three quarters or one quarter of full
scale. A comparison is done and if the input is greater than
the new DAC value this bit remains high; if the input is less
than the new DAC value the bit is set low. This process
continues until each bit has been tested. The result is then
stored in the output latch of the ADC1241. Next EOC goes
high, and INT goes low to signal the end of the conversion.
The result can now be read by taking CS and RD low to
enable the DBO-DB12 output buffers.

The End-of-Conversion control output. This
output is low during a conversion or a calibration cycle.
The Interrupt control output. This output goes
low when a conversion has been completed
and indicates that the conversion result is
available in the output latches. Reading the
result or starting a conversion or calibration
cycle will reset this output high.

2-611

•

... r------------------------------------------------------------------------------------------,
2.0 Functional Description
~

C"I

(Continued)

~

g
cc

Digital Control Inputs

CS

WR

"lI'
"l.F
"lI'
"lI'
1
0

X
X

AID Function

JiD

CAL

AZ

"lI'

1

1

"lI'

1
1
1
1

1
1
0
0

X
X

"lI'

1

1

"lI'
X

"lI'

1

0

Start Conversion without Auto-Zero
Read Conversion Result without Auto-Zero
Start Conversion with Auto-Zero
Read Conversion Result with Auto-Zero
Start Calibration Cycle
Test Mode (D82, D83, D85 and D86 become active)

FIGURE 1. Function of the AID Control Inputs
The table in Rgure 1 summarizes the effect of ~he digital
control inputs on the function of the ADC12~1. The Test
Mode, where RD is high and CS and ~ are low, is used by
the factory to thoroughly check out the operation of the
ADC1241. Care should be taken not to inadvertently be in
this mode, since D82, D83, D85, and D86 become active
outputs, which may cause data bus contention.

3.0 Analog Considerations
3.1 REFERENCE VOLTAGE
The voltage applied to the reference input of the converter
defines the voltage span of the analog input (the difference
between VIN and AGND), over which 4095 positive output
codes and 4096 negative output codes exist. The A·to·D
can be used in either ratiometric or absolute reference ap·
plications. The voltage source driving VREF must have a
very low output impedance and very low noise. The circuit in
Figure 2 is an example of a very stable reference that is
.
appropriate for use with the ADC1241.

2.2 RESETTING THE AID
All internal logic can be reset, which wil! abort any conversion in process. The AID is reset whenever a new conversion is started by taking CS and WR low. If this is done when
the analog input is being sampled or when EOC is low, the
Auto-Cal correction factors may be' corrupted, therefore
making it necessary to do an Auto-Gal cycle before the next
conversion. This is true. with or without Auto-Zero. The Calibration Cycle cannot be reset once started. On power-up
the ADC1241 automatically goes through a Calibration Cycle that takes typically 1396 qlock cycles.
'

VIN

In a ratiometric system, the analog input voltage is propor~
tional to the voltage used for the AID reference. When this
voltage is the system power supply, the VREF pin can be
tied to Vee. This technique relaxes the stability requirement
of the system reference as the analog input and AID refer·
ence move together maintaining the same output code for
given input condition.

=+12V to +15V

3.52k.Cl
0.1%

62k4

TL/H/l0S54-17
·Tantalum

FIGURE 2. Low Drift Extremely Stable Reference Circuit

2-612

3.0 Analog Considerations (Continued)

TL/H/10554-1B

FIGURE 3. Analog Input Equivalent Circuit
For absolute accuracy, where the analog input varies be·
tween very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
In general, the magnitude of the reference voltage will require an initial adjustment to null out full-scale errors.

ductance tantalum capacitors of 10 p.F or greater paralleled
with 0.1 p.F ceramic capaCitors are recommended for supply
bypassing. Separate bypass capaCitors whould be placed
close to the DVcc, AVcc and V- pins. If an unregulated
voltage source is available in the system, a separate
LM340LAZ-5.0 voltage regulator for the A-to-D's Vee (and
other analog circuitry) will greatly reduce digital noise on the
supply line.

3.2 INPUT CURRENT
A charging current will flow into or out of (depending on the
input voltage polarity) of the analog input pin (VIN) on the
start of the analog input sampling period (tA>. The peak value of this current will depend on the actual input voltage
applied.
3.3 INPUT BYPASS CAPACITORS
An external capaCitor can be used to filter out any noise due
to inductive pickup by a long input lead and will not degrade
the accuracy of the conversion result.
3.4 INPUT SOURCE RESISTANCE
The analog input can be modeled as shown in Figure 3.
External Rs will lengthen the time period necessary for the
voltage on CREF to settle to within 112 LSB of the analog
input voltage. With fCLK = 2 MHz tA = 7 clock periods =
3.5 p.s, Rs :s; 1 kO will allow a 5V analog input voltage to
settle properly.

3.7 THE CALIBRATION CYCLE
On power up the ADC1241 goes through an Auto-Cal cycle
which cannot be interrupted. Since the power supply, refer. ence, and clock will not be stable at power up, this first
calibration cycle will not result in an accurate calibration of
the AID. A new calibration cycle needs to be started after
the power supplies, reference, and clock have been given
enough time to stabilize. During the calibration cycle, correction values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall gain, offset,
and linearity errors down to the specified limits. It should be
necessary to go through the calibration cycle only once after power up.
3.8 THE AUTO-ZERO CYCLE
To correct for any change in the zero (offset) error of the
AID, the auto-zero cycle can be used. It may be necessary
to do an auto-zero cycle whenever the ambient temperature
changes significantly. (See the curved titled "Zero Error
Change vs Ambient Temperature" in the Typical Performance Characteristics.) A change in the ambient temperature
will cause the Vos of the sampled data comparator to
change, which may cause the zero error of the AID to be
greater than ± 1 LSB. An auto-zero cycle will maintain the
zero error to ± 1 LSB or less.

3.5 NOISE
The leads to the analog input pin should be kept as short as
possible to minimize input noise coupling. Both noise and
undesired digital clock coupling to this input can cause errors. Input filtering can be used to reduce the effects of
these noise sources.
3.6 POWER SUPPLIES
Noise spikes on the VCC and V- supply lines can cause
conversion errors as the comparator will respond to this
noise. The AID is especially sensitive during the auto-zero
or auto-cal procedures to any power supply spikes. Low in

2-613

~

~
~

~

,------------------------------------------------------------------------------------------,
4.0 Dynamic Performance
Power Supply Bypassing

Many applications require the AID converter to digitize ac
signals, but the standard dc integral and differential nonlinearity specifications will not accurately predict the AID converter's performance with ac input signals. The important
specifications for ac applications reflect the converter's ability to digitize ac signals without significant spectral errors
and without adding noise to the digitized signal. Dynamic
characteristics such as signal-to-noise;/, distortion ratio
(S/(N + D», effective bits, full power bandwidth, aperture
time and aperture jitter are quantitative measures of the
AID converter's capability.

AVec

1-=:0==:::---'

ADC1241

-~;::::!!!!i~ AGND
V-

An·A/D converter's ac performance can be measured using
Fast Fourier'Transform (FFT) methods. A sinusoidal waveform ,is applied to the AID converter's input, and the transform is then performed on the digitized waveform. S/(N + D)
is calculated from the resulting FFT data, and a spectral plot
may also be obtained. Typical values for S/(N+D) are
shown in the table of Electrical Characteristics, and spectral
plots are included in the typical perfqrmance curves.

t-=-===::---,

~.I~r~10~r~·
TL/H/l0554-19

-Tantalum

Protecting the Analog Inputs
+5V

The AID converter's noise and distortion levels will change
with the frequency of the input signal, with more distortion
and' noise occurring at' higher signal frequencies. This can
be seen in theS/(N+D) versus frequency curves. These
curVes will also'give an indication of the full power bandwidth (the frequency at which the Si(N + D) drops 3 dB).
Two samplelhold ~pecificatio"s, aperture time and. aperture
jitter,. are included in the "Dynamic Characteristics table
since the ADC1241 has the ability to track and hold the
anaiog input voltage. Aperture time is the delay for the AID
to respond to the hold command. In the case of the
ADC1241, the hold Command is interl)ally generated. When
the Auto-Zero function is not being used, the hold command
occurs at tlie end of the acquisition window,or seven clock
periods after the rising edge of the WR. The delay between
the internally generated hold command and the time that
the ADC1241 actually holds the input signal is the aperture
time. For the ADC1241, this time is typically 100 ns. Aperture jitter is the change in the aperture time from sample to
sample. Aperture jitter. is useful in determining the maximum
slew rate of the input signal foria given accuracy. For example, an ADC1241 with 100 ps of aperture jitter operating with
a 5V reference can have an effective gain variation of about
1 LSB with an input signal whose slew rate is 12 VI p.s.

-12V

TUH/l0554-20

2-614

til

Nat ion a I S e m icon due to r

ADC1242

12-81t Plus Sign Sampling AID Converter
General Description

Key Specifications

The ADC1242 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter. On request, the
ADC1242 goes through a self-calibration cycle that adjusts
positive linearity error to less than ± 1 LSB full-scale error to
less than ±3 LSB, and zero error to less than ±2 LSB. The
ADC1242 also has the ability to go through an Auto-Zero
cycle that corrects the zero error during every conversion.

•
•
•
•
•
•

The, analog input to the ADC1242 is tracked and held by the
internal circuitry, and therefore does not require an external
sample-and-hold. A·unipolar analog input voltage range (OV
. to +5V),or a bipolar range (-5V to +5Vl ,can be accom, mOdated with, ± 5V supplies.
'"
The 13-bit word on the outputs of the ADC1242 gives a 2's
complement representation of negative numbers. The digital inputs and outputs are compatible with TTL or CMOS
logic levels.

12 Bits plus Sign
13.8 J.l.s (max)
±1 LSB (± 0.0244%) (max)
±2 LSB (max)
±3 LSB (max)
70 mW (max)

Resolution
Conversion Time
Linearity Error
Zero Error
Positive Full Scale Error
Power Consumption

Features
• Self-calibrating
• Internal sample-and-hold
• Bipolar input range with ± 5V supplies and single
+ 5V reference
• No missing codes over temperature
• TTL/MaS input/output compatible
• Standard 28-pin ceramic DIP

Applications
• Digital Signal Processing
• High Resolution Process Control
• .Instrumentation

Simplified Schematic
V,N

~

~

AVcc 0--+

,

..........-

Connection Diagram

......- - - - - - - 1

Dual-In-Llne Package

Correction
DAC

2

V'ErO--+
AGND

o--!-..
5

15

V-o--+

DBO (lSB)
OBI

28

DB2

DVcc'o--+

DB3

I~

DGND 0--+

V,N

I

28

DVec

VREr
AGND

2

27

08 I 2(SI;n)

3

26

08 II (WSB)

~

25

0810

AVec
V-

5

2~

089

Ai

6

23

DBB

iii

7

ADCI242 22

DB7

eLKIN

8

21

DB.

CAL

9

20

DB5

cs

10

19

DB~

iii

II

18

DB3
DB2

EOC

12'

17

DB~

iNi'

13

16

DB5

DGND

OBI
DBO(LSB)

DB6

TL/H/I1735-2 .

DB7
DB8
DB9
DBIO
DBII (WSB)
DBI2 (Sign)

TLlH111735-1

2-615

Top View

Order Number ADC1242CIJ
See NS Package Number J28A

•

C'II

. 'Oil'

C'II
,..
o
cc(

Absolute Maximum Ratings (Notes 1 &2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee = DVee
Negative Supply Voltage (V-)

= AVeC>

(V- -O.SV) to (Vec + 0.3V)
±5mA
±20mA

Power Dissipation at 25·C (Note 4)

Reference Voltage
(VREF. Notes 6 and 7)

S,75mW
- 65·C to, + 150·C

Storage Temperature Range

TMIN,;;:TA,;;:TMAX
-400C,;;:TA';;: +85"C

DVee and AVec Voltage
(Notas 6 an~ 7)
Negative Supply Voltage (V-)

O.SV

Package Input Current (Note S)

SOOOC

Temperature Range
ADC1242CIJ

-O.SV to (Vec+ O.SV)

AVee-DVee (Note 7)
Input Current at any Pin (Note S)

2000V

Soldering Information
J Package (10 seconds)

Operating Ratings (Notes 1 a~d 2)

-6.5V

Voltage at Logic Control Inputs
Voltage at Analog Input (VIN)

6.5V

ESD Susceptability (Note 5)

4.5Vt05.5V
-4.5Vto -5.5V
S.5V to AVec + 50 mV

,

Converter Electrical Characteristics

The following specifications apply for Vee = DVec = AVec = +5.0\1', V- = -5.0V. VREF = +4.096V. and feLK ,;, 2.0 MHz
unless otherwise specified. Boldface limlta appl, for Ta = T .. = TMIN to TIIAX; all other limits T A = TJ = 25°C. (Notes
.
.
,
6. 7 and S)
Parameter

Symbol,

Conditions

Typical
Limit
(Note 9) (Notes 10,18)

Units
(Limit)

STATIC CHARACTERISTICS

.,

Positive Inlegral
Linearity Error

After Auto-cal .
(Notes 11 and 12)

±1

LSB(max)

Differential Linearity

After Auto-cal (Notes 11 and 12)

12

Bits(min)

Zero Error

After Auto-Zero or Auto-cal
(Notes 12 and 13)

±2

LSB(max)

Positive and Negative Full-Scale Error

After Auto-Cal (Note 12)

±3

LSB(max)

CREF

VREF Input Capacitance

SO

CIN

Analog Input Capacitance

65

VIN

Analog Input Voltage

pF
pF
V- - 0.08
Vee + 0.08

Power Supply
Sensitivity

Zero Error (Note 14) AVec = DVee = 5V ±5%.
VREF = 4.75V. V- = -5V ±5%
Full-Scale Error

V(min)
V(max)

±Ya

LSB

±Ya

LSB

±Ya

LSB

72

dB

72

dB

76

dB

76

dB

32

kHz

25

kHz

Aperture Time

100

ns

Aperture Jitter

100

PSrms

Linearity Error
DYNAMIC CHARACTERISTICS
S/(N+D) Unipolar Signal-to-Noise + Distortion
Ratio (Note 17)

S/(N+D) Bipolar Signal-to-Noise+ Distortion
Ratio (Note 17) .
Unipolar Full Power Bandwidth (Note 17)
Bipolar Full Power Bandwidth (Note 17)
tAp

= 1 kHz. VIN = 4.S5 Vp•p
fiN = 10 kHz. VIN = 4.85 Vp-p
fiN = 1 kHz. VIN = ±4.S5 Vp•p
fiN = 10 kHz. VIN = ±4.85 Vp-p
VIN = OV to 4.85V
VIN = ±4.85 Vp•p
fiN

2-616

):.

C

Digital and DC Electrical Characteristics

The following specifications apply for Vcc = DVcc = AVcc = +S.OV, V'" = -S.OV, VREF = +4.096V, and fClK = 2.0 MHz
unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 2SoC.
(Notes 6 and 7)
Symbol

Parameter

Condition

VIN(l)

logical "1" Input Voltage for
All Inputs except ClK IN

Vcc

= S.2SV

VIN(O)

logical "0" Input Voltage for
All Inputs except ClK IN

Vcc

= 4.7SV

IIN(l)

logical "1" Input Current

VIN
VIN

= 5V
= OV

Limit
(Notes 10, 18)

Units
(Limits)

2.0

V(min)

0.8

V(max)

0.005

1

,...A(rnax)

Typical
(Note 9)

IIN(O)

logical "0" Input Current

-O.OOS

-1

,...A(rnax)

VT+

ClK IN Positive-Going
Threshold. Voltage

2.8

2.7

V(min)

VT-

ClK IN Negative-Going
Threshold Voltage

2.1

2.3

V(max)

VH

ClK IN Hysteresis
[VT+(min) - VT-(rnax)l

0.7

0.4

V(min)

VOUT(l)

logical "1" Output Voltage

2.4
4.5

V(min)
V(min)

Vcc = 4.7SV:
lOUT = -360,...A
lOUT = -10,...A

VOUT(O)

logical "0" Output Voltage

Vcc = 4.7SV
lOUT = 1.6 rnA

lOUT

TRI-STATE® Output leakage
Current

ISOURCE

Output Source Current

ISINK

Output Sink Current

Dlcc

DVcc Supply Current

Alcc

AVcc Supply Current

I-

V- Supply Current

= OV
VOUT = SV
VOUT = OV
VOUT = SV
fClK = 2 MHz, ~ = "1"
fClK = 2 MHz, CS = "1"
fClK = 2 MHz, CS = "1"
VOUT

2-617

0.4

V(max)

-3

,...A(max)

0.01

3

,...A(max)

-20

-8.0

mA(min)

20

8.0

mA(min)

1

2

mA(max)

2.8

6

mA(max)

2.8

6

mA(max)

-0.01

o
....

t

AC Electrical Characteristics
The following specifications apply for DVOO = AVOO = +5.0V, V- = -5.0V, tr = tf = 20 ns unless otherwise specified.
Boldface limits applY'for TA = T .. = TMIN to TMAX; all other limits TA = TJ = 25'C. (Notes 6 and 7)

Symbol
fOLK

Paraineter

Conditions

Typical

Limit

Units

(Note 9)

(Notes 10, 18)

(Limits)

Clock Frequency

2.0

Clock Duty Cycle

to

tA

Acquisition Time

RSOUROE = 500

(Note 15)

fOLK = 2.0 MHz

tz

Auto Zero Time

tW(OAl)l

Calibration Pulse Width

tW(WR)l

Minimum WR Pulse Width

tAOO

Maximum Access Time

MHz(max)
%
40

%(min)

60

% (max)

27(1/fCLK) + 300 ns

(max)

7(1/fCLK) + 30.0 ns

(max)

26

1IfOLK(max)

13.5
7(1IfOlK)

ILs

3.5

ILs

26
fOLK = 2.0 MHz

Calibration Time

4.0

27(1IfOlK)
fOlK= 2.0 MHz

teAl:

MHz(min)

50

Conversion Time

fOLK = 2.0 MHz
(Note 16)

MHz

0.5

13,

ILs

1396

1IfOlK

698

706

ILs(max)

60

200

ns(min)

60

200

ns(min)

50

85

ns(max)

30

90

ns(max)

100

175

ns(max)

Cl = 100pF

(Delay from Falling Edge of .
RD to Output Data Valid)
ioH, tlH

TRI-STATE, Control (Delay

RL = 1 kO,

from Rising Edge of RD

Cl = 100pF

to Hi-Z State)
tpD(INn

Maximum Delay from Falling Edge of
RD or WR to Reset of INT
.'

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, Operating Ratings indicate conditions for. which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics, The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device Is not operated under the listed test
conditions.
Note 2: All vollsges are measured with respect to AGND and DGND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V- or VIN > (AVec or DVecl, the current at that pin should be limited to
5 mAo The 20 mA maximum package input current rating allows the voltage at any four pins, with an Input current limit of 5 mA, to simullsneously exceed the power
supply vollsges.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX (maximum junction temperature), 6JA (package
junction to ambient thermal resislsnce), and TA (ambient temperature), The maximum allowable power dissipation at any temperature is POmax ~ (TJmax TA)/6JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax ~ 125'C, and the typical thermal resislsnce (8JN of the
ADC1242 CIJ when board mounted Is 47"O/W.
Nole 5: Human body model, 100 pF discharged through a 1.5 k!l resistor,
Note 6: Two on-Chip diodes arB tied to the analog input as shown below. Errors in the AID conversion can occur if these diodes are forward biased more than
50mV.
DVcc
28

~-

VIN

1

- j------

I
I
I
I
I
I
~--

~~
~~

TO INTERNAL
CIRCUITRY

1------

5

V-

TUH/11735-3

This means that if AVee and DVec are minimum (4,75 Vocl and V- is maximum (-4.75 Vocl, full·scale must be

2-618

s:

4,8 Vee.

~

AC Electrical Characteristics

C

o
....

(Continued)

Note 7: A diode exists between AVec and DVee as shown below.

N

"'"

I

N

1
1
A v c c : r : TO INTERNAL
1
CIRCUITRY

DVcc

28:

TO INTERNAL
CIRCUITRY

1
1

TLlH/11735-4

To guarantee accuracy, it is required that the AVec and DVee be connected together to a power supply with separate bypass filters at each Vee pin.
Nole 8: Accuracy is guaranteed al felK
Characteristics Section.

Note 9: Typicals arB at TJ

=

~

2.0 MHz. At higher and lower clock frequencies accuracy may degrade. See curves in Ihe Typical Performance

2S C and represent most likely parametric norm.
G

Note 10: Limits are guaranteed to National's AOQl (Average Outgoing Quality Level).

Note 11: Positive linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full scale and
zero. For negative linearity error the slraighlline passes Ihrough negalive full scale and zero. (See Figures tb and te).
Note 12: The ADC1242's self-calibration technique ensures linearity. full scale, and offset errors as specified, but noise inherent in the self·calibration process will
result in a repeatability uncertainty of ±0.20 lSB.
Note 13: If TA changes then an Auto-Zero or Auto-Cal cycle .will have to be re-started, see the typical performance characteristic curves.
Note 14: After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes.
Note 15: If the clock is asynchronous to the falling edge of WR an uncertainty of one clock period will exist in the interval of tA, therefore making the minimum tA ~
6 clock periods and the maximum tA ~ 7 clock periods. If the falling edge of the clock is synchronous to the rising edge of WR then IA will be exactly 6.5 clock
periods.
Note 16: The CAL line must be high before any other conversion is started.
Note 17: The specifications for these parameters are valid after an Auto-Cal cycle has been completed.·
Note 18: A militaoy RETS electrical test specification is available upon request. At time of printing, the ADC1241CMJ/BB3 RETS specification complies fully with the
boldface limits in this column.

(+4095)0,1111,1111,1111 - (+4094)0,1111,1111,1110 - "
",

~SITIVE

FULL -SCALE
TRANSITION

////'
(2) 0,0000,0000,0010

(1) 0,0000,0000,0001
(0) 0,0000,0000,0000

r--'

-

.

_,....I-_I=,..,......t=-=~Z=ER~O'-T~R~AN~S~IT~IO~N_ _ _ _ _ _-III INPUT VOLTAGE
-1,1111,1111,1111 (-1)
-1,1111,1111,1110(-2)

,

+VREF

""",

"""""
.-rCIVE
fULL -SCALE TRANSITION

-

-

1,0000,0000,0001 (-4095)
1,0000,0000,0000 (-4096)

ANALOG INPUT VOLTAGE (VIN )
TL/H/I1735-5

FIGURE 1a_ Transfer Characteristic

2-619

•

~

...
~

~

.---------------------------------------------------------------------------------,
AC Electrical Characteristics (Continued)
+12LSB

-12LSB

OUTPUT CODE

(from -4096 to +4095)

TL/H/11735-6

FIGURE 1b. Simplified Error Curve vs Output Code without Auto-Calor Auto-Zero Cycles

+3LSB

NEGATIVE INPUT RANGE

-2LSB

POSITIVE INPUT RANGE

-3LSB

OUTPUT CODE

(from -4096 to +4095)

TL/H/11735-7

FIGURE 1c. Simplified Error Curve vs Output Code after Auto-Cal Cycle

Typical Performance Characteristics

1.6
1,01
~

1.2

.:!!.

1.0

iii
I:i

0.6

~

~
N

Zero Error Change vs
Temperature

Zero Error vs VREF

0.6
0,01

0.2

o
o

\

\
\

2 Ambient

AVec = DVcc = +S.OV
V" = -S.OY
feLk = 2 MHz
TA • +25 0 C

I

~

1~

'\

I'

,'" ~
~

'"

AVec = DVec = +5.0V

V" =-5.0Y
lelK
2 MHz
YREF = +S.OY

=

No Calibration

No Autozlro

-2
-55-35-155 25 45 65 65105125

3

YREF (V)

AMBIENT TEMPERATURE (Oc)

2-620

TLlH/11735-8

Typical Performance Characteristics

Linearity Error vs Clock
Frequency

Linearity Error vs VREF

'ii1
~

.:!!.

t.O

I

0.8

~z

AVec = DVec = +5.0V
'f' =-5.0V
'elK = 2111Hz
TA = +25 c C

1\
\
\

0.8

iiie;

0.4

1:

0.3

~::;

0'"

::;

0.2

o

t.O

80

90

70

3

~

Rs = 200n Y,N = z2.5 Vp_p
60 TA = 25°C
DVec = AVec = VREF = +5.0V
50 'f'=-5.0V
'elK = 2 MHz
Sampling Frequency = 55 kHz
40
t.O
to

~

~

~

I

60 AVec" DVcc" VRU " +5.0'1

::.;;~.:~

'ii1

'Q

~

40

I

A.Vec = DVcc = VREF

80

-70 -60 -50 -40 -30 -20 -to

60

'ii1

3

40

I

I·

fCUC"
Sampling Fr.qUInC1
• 55kf1z

200 300 400 50D 600

Bipolar Spectral Response
with 10 kHz Sine Wave Input
.,-SD4
YlHllts.OYp- p
TAII 25 DC
AVDC -DVCC -Yw -.s.ov
.,.II-S.OY
'cull21i1Hz

~

y

I

V fiN = 20 kHz

V

48

'ii1

24

§

-24

3

I

V

,V

Sampling Fr.qIl,nc,.-55kHz

S/(N+D) II 7'.03 d

-48

-72
-96
5.0

to

t5

20

Unipolar Spectral Response
with 1 kHz Sine Wave Input

Unipolar Spectral Response
with 10 kHz Sine Wave Input
lis-son

Is·son
YLM=s.OYp- p
TA=250C
AVoc II DVce =Vau II +5.0Y
"'--5.0Y
'CLIC= 211IH:r

48

"Voe " DVcc II Vau" .5.0'1

V- .. ~5.0V
'elK- 2111 Hz

Sampling Fnq1.11l1Cl.55kHz
S/(N+D)1I71.55d

25

FREQUENCY (kHz)

INPUT StGNAL LEVEL (dB)

Is-50ft
\'IH"":tS.DVp- p
T... II Z5 0 C

-24

tOO

= t kHz

I

AVcc"OVCC"VRU= .5.0'1

V'--,.".
2MHz

rr-

INPUT SOURCE INPEDANCE (n)

-70 -60 -50 -40 -30 -20 -to

Bipolar Spectral Response
with 1 kHz Sine Wave Input

24

o

tOO

f'N

I

I

40 fiN =25kHz
TA = 25°C
AYec = DVcc == VREF := +S.OV
20
r-'f' '-S.OV
'ClK::I 2 MHz
ISampling Frequency = 55 kHz

o

INPUT SIGNAL LEVEL (dB)

§

!s1l200a

' \ Y,N = u.s Vp_p

o

to

VIM ""5.0V,_,
T... IIZ5OC

20

",

o

'ii1

=+S.OY

" I

II

Unipolar Signal-toNoise + Distortion Ratio vs
Input Signal LevliIl

7

X' I

3

ITI

INPUT FREQUENCY (kHz)

.~

48

S

Sampling Frequency = 55 kHz

t.O

~
20

~

R =200n ",.~ =2.5~
60 T"s z:z 250C
IN
poOp

40

fiN = 20kHz

SunplinD FreqUlncl
"55kHz

VIN == :1:5.0 Yp_p

60

50 'f' =-5.0V
feLK = 2MHz

=f kHz I-..

I

80

'ii1
3

Bipolar Signal-toNoise + Distortion Ratio vs
Input Signal Level

TA-noc

-t.O ~.L-.J--'-...J....-'---L.-L--L--'
-55 -35 -t5 5 25 45 65 85 tOS t25
ANBIENT TENPEAATURE (oC)

70

tOO

No Autoztro

Bipolar Signal-toNoise + Distortion Ratio vs
Input Source Impedance

V,N = 5.0 VP_P

INPUT FREQUENCY (kHz)

fiN

~

4.0

IIIIII I

80

'ii1

3

VIM,"tS.DYp- p

3.0

CLOCK FREQUENCY (MHz)

.1
.,....

lis" 2000

2.0

Unipolar Signal-toNoise + Distortion Ratio vs
Input Frequency

V'~~5V
I
IN
P"P

-

Ot-

O~~~~~~--~~

90

3

No Calibration

J

~ -O.S I-+-++-+-+-I-+-+-l

VREF (V)

80

VREf' := +5.0V

~

Bipolar Signal-toNoise + Distortion Ratio vs
Input Frequency

S

0.51-+-++-+-+ fClK = 2 MHz

0.2

o

'ii1

v-. -S.OY

I

O.t

o

Full Scale Error Change vs
Ambient Temperature
t.O r-r-r-r-:A"Vec--c'=D:::~:-ec-=~+.s;-:.o::;"tv

0.8
0.7 AVCC = DVCC = +S.OV
'f' =-5.0V
'ii1
~ 0.6 VREF = +S.OV
~
O
0.5 TA = +25 C

1.4

1.2

(Continued)

Sampling Fr.qu.ncJ.55kHz

S/(N+D)=72.lld

VIN-S.OVp- p
TA II 2SOC
AVDC II DVcc " Via II +S.ov
"'''-S.OV
fcuc" 2WHz

48

'ii1

24

§

-24

3

Sampling Fr.qIl'RCJ=55kHz

=

S/(NtD) 72.05d

;I -48

-48

~

-72
-96

-96
5.0

to

t5

20

FREQUENCY (kHz)

25

-72
-96

5.0

to

t5

20

FREQUENCY (kHz)

25

5.0

to

t5

20

25

FREQUENCY (kHz)
TLlH/11735-9

2-621

fII

Test Circuits
Vee

ADC1242

t-.....- ....- .

DATA
OUTPUT

TLIHI1173S-11
TLIH111735-10

Vee
_
RD
ADC1242

t-+--+

DATA
OUTPUT

DATA

t,.
Vee - - i - I r - -

:::---=ik~
~%

OUTPUT VOL

TUH11173S-13
TUHI11735-12

FIGURE 2. TRI-STATE Test Circuits and Waveforms

Timing Diagrams
Auto-Cal Cycle (CS

= 1, WFi = X, RD = X, AZ = X, X = Don't Care)

CLOCK

: _______5 ""', t
1

----~

[~

..
Auto-Cal
C,.le
... 1396 clocks

} . . . - -_ _ _ _ _ _ __

\~--------------~!I~----------------~

.

oo------------------------~!I~----------------------------------TUH11173S-14

2-622

l>

c

Timing Diagrams (Continued)

o
.....

...

N

Normal Conversion with Auto-Zero (CAL = 1. AZ = 0)

N

''-_...J/

~H ·'oH

A1.

---"---i---__l

tOC

IZ
Auto-Zero'" 26 clocks

--+~-

IA
Acquisistlon
... 7 clocks

iNT --------------~H~----------~!~----~__ll------~I

D~-~12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TUH/11735-15

Normal Conversion without Auto-Zero (CAL = 1. AZ = 1)

CLOCK~~

\

/

I

,

I

~~

I

H

.J
tOC

I----

I

-~H·'oH

/

IA
Acqulslstlon
... 7 cJocks

Ipd(iNT)_

I

Ie

\

C

1

Conversion

DBO-DBI2

.______ ~ ______________________ "'--------2~:.:~-------~A::-0 ------------TL/H/11735-16

2-623

•

1.0 Pin Descriptions
DVee (28),
AVec (4)

The digital and analog positive power supply
pins. The digital and analog power supply
"voltage range of the ADC1242 Is + 4.5V to
'+5.5V. To guarantee accuracy, it is'required
that the AVec and DVec be, connected together'to the same power supply with separate bypass filiers (10 p.F tantalum in parallel
with a 0.1 p.F ceramic) at each Vee pin.
V- (5)
The analog negative supply voltage pin. Vhas a range of -4.5V to -5.5V and needs a
bypass filter of 10 p.F tantalum in parallel with
a 0.1 p.F ceramic.
DGND (14), The digital and analog ground pins. AGND
AGND (3)
and DGND must be connected together externally to guarantee accuracy.
The reference input voltage pin. To maintain
VREF(2)
accuracy the voltage at this pin should not
exceed the AVec or DVee by more than
50 mil or go below 3.5 VDC.
VIN (1)
The analog input voltage pin. To guarantee
accuracy the voltage at this pin should not
exceed Vec by more than 50 mV or go below
V- by more than 50 mV.

OS (10)
RD(11)

WR (7)

ClK (8)

wu: (9)

AZ (6)

EOC (12)

Tiii'f (13)

DBO-DB12
(15-27) ,

The TRI-STATE output pins. The output is in
two's complement format with DB12 the sign
bit, DB11 the MSB and DBO the lSB.

2.0 Functional Description
The ADC1242 is a 12-bit plus sign AID converter with the
capability of doing Auto-Zero or Auto-Cal routines to minimize zero, full-scale and linearity errors., It is a successiveapproximation AID converter consisting of a DAC, comparator and a successive-approximation 'r'egister (SAR). AutoZero is an Internal calibration sequence that corrects for the
AID's zero error caused by the comparator's offset voltage.
Auto-Cal is a calibration ,cycle that not only corrects zero
error but also corrects for full-scale and linearity errors
caused by DAC inaccuracies. Auto-Cal minimizes the errors
of the ADC1242 without the need of trimming during its fab" rication. An Auto-Cal cycle can restore the accuracy of the
ADC1242 at anytime, which ensures its long term stability.

2.1 DIGITAL INTERFACE
On power up, a calibration sequence should be initiated by
pulsing CAL low with CS, RD, and WR high. To acknowledge the
Signal, EOC goes low after the falling edge of
CAL, and remains low during the calibration cycle of 1396
clock periods. During the calibration sequence, first the
comparator's offset is determined, then the capacitive
DAC's mismatch error is found. Correction factors for these
errors are then stored in internal RAM.
A conversion is initiated by taking CS and WR low. The AZ
(Auto Zero) signal line should be tied high or low during the
conversion process. If A'l. is Iowan auto zero cycle, which
takes approximately 26 clock periods, occurs before the actual conversion is started. The auto zero cycle determines
the correction factors for the comparator's offset voltage. If
A'l. is high, the auto zero cycle is Skipped. Next the analog
input is sampled for 7 clock periods, and held in the capacitive DAC's ladder structure. The EOC then goes low, signaling that the analog input is no longer being sampled and
that the AID successive approximation conversion has
started.
During a conversion, the sampled input voltage is successively compared to the output of the DAC. First, the acquired input voltage is compared to analog ground to determine its polarity. The sign bit is set low for poSitive input
voltages and high for negative. Next the MSB of the DAC Is
set high with the rest of the bits low. If the input voltage is
greater than the output of the DAC, then the MSB is left
high; otherwise it is set low. The next bit is set high, making
the output of the DAC three quarters or one quarter of full
scale. A comparison is done and if the input is greater than
the new DAC value this bit remains high; If the input is less
than the new DAC value the bit is set low. This process
continues until each bit has been tested. The result is then
stored in the output latch of the ADC1242. Next EOC goes
high, and lliI'f goes low to Signal the end of the conversion.
The result can now be read by taking CS and RD low to
enable the DBO-DB12 output buffers.

wu:

The Chip Select control input. This input is
active low and enables the WR and RD functions.
The Read control input. With botli OS and RD
low the TRI-STATE output buffers are enabled and the INT output is reset high'.
The Write control input. The converison is
started on the rising edge of the WR pulse
when CS is low.
"The external clock input pin. The clock frequency range is 500 kHz to 4 MHz.
The Auto-Calibration control input. When
CAL is low the ADC1242 is reset and a calibration cycle is initiated. During the calibration cycle the values of the comparator offset
voltage and the mismatch errors in the capacitor reference ladder are determined and
'stored in RAM. These values are used to correct the errors during a normal cycle of AID
conversion.
Th,e Auto-Zero control input. With the AZ pin
held low during a conversion, the ADC1242
goes into an auto-zero cycle before the actual AID conversion is started. This Auto-Zero
cycle corrects for the comparator offset voltage. The total conversion time (te) is increased by 26 clock periods when Auto-Zero
is used.
The End-of-Conversion control output. This
output is low during a conversion or a calibration cycle.
The Interrupt control output. This output goes
low when a conversion has been completed
and indicates that the conversion result is
available in the output latches. Reading the
result or starting a conversion or calibration
cycle will reset this output high.

2-624

l>

c

2.0 Functional Description (Continued)

o
....

Digital Control Inputs

~
~
~

AID Function

CS

WR

RD

CAL

AZ

"""IS
"""IS
"""IS
"""IS
1
0

"""IS
1
"""IS
1
X
X

1
"""IS
1
"""IS
X
1

1
1
1
1
"""IS
0

1
1
0
0
X
X

Start Conversion without Auto-Zero
Read Conversion Result without Auto-Zero
Start Conversion with Auto-Zero
Read Conversion Result with Auto-Zero
Start Calibration Cycle
Test Mode (DB2, DB3, DB5 and DB6 become active)

FIGURE 3. Function of the AID Control Inputs
The table in Figure 3 summarizes the effect of the digital
control inputs on the function of the ADC1242. The Test
Mode, where RD is high and CS and CAL are low, is used by
the factory to thoroughly check out the operation of the
ADC1242. Care should be taken not to inadvertently be in
this mode, since DB2, DB3, DB5, and DB6 become active
outputs, which may cause data bus contention.

3.0 Analog Considerations
3.1 REFERENCE VOLTAGE
The voltage applied to the reference input of the converter
defines the voltage span of the analog input (the difference
between VIN and AGND), over which 4095 positive output
codes and 4096 negative output codes exist. The A-to·D
can be used in either ratiometric or absolute reference applications. The voltage source driving VREF must have a
very low output impedance and very low noise. The circuit in
Figure 4 is an example of a very sta~le reference that is
appropriate for use with the ADC1242.
In a ratiometric system, the analog input voltage is propor~
tional to the voltage used for the AID reference. When this
voltage is the system power supply, the VREF pin can be
tied to Vee. This technique relaxes the stability requirement
of the system reference as the analog input and AID reference move together maintaining the same output code for
given input condition.

2.2 RESETTING THE AID
All internal logic can be reset, which will abort any conversion in process. The AID is reset whenever a new conversion is started by taking CS and WR low. If this is done when
the analog input is being sampled or when EOC is low, the
Auto-Cal correction factors may be corrupted, therefore
making it necessary to do an Auto-Cal cycle before the next
conversion. This is true with or without Auto-Zero. The Calibration Cycle cannot be reset once started. On power-up
the ADC1242 automatically goes through a Calibration Cycle that takes typically 1396 clock cycles.
VIN

= +12V

10 +15V

To ADC1242 VGC

1.8 kll

•

2.46 kll
0.1%

3.52 kll
0.1%

62 kll

TUH/11735-17

'Tantalum

FIGURE 4. Low Drift Extremely Stable Reference Circuit

2-625

~

"'~="

o
cr:

r---------------------------------------------------------------------------------,
3.0 Analog Considerations (Continued)

c

TL/H/11735-18

FIGURE 5. Analog Input Equivalent Circuit
For absolute accuracy, where the analog input varies between very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
In general, the magnitude of the, reference voltage ,will' require an initial adjustment to null out full-scale errors.

ductance tantalum capacitors of 10 p.F cir greater paralleled
with 0,1 p.F ceramic capacitors are recommended for supply
bypassing. Separate bypass capacitors whould be placed
close to the DVcc, AVec and V~ pins. If an unregulated
voltage source is available in the system, a separate
LM340LAZ-5.0 voltage regulator for the A'to-D's Vcc (and
other analog circuitry) will greatly reduce digital noise on the
supply line.

3.2 INPUT CURRENT
A charging current will flow into or out of (depending on ,ihe
input voltage polarity) of the analog input pin (VIN) on 'the
start of tlie analog input sampling period (tA)' The peak value of, this current will depend on the actual input voltage
applied.
. .

3.7 THE CALIBRATION CYCLE
On power up the ADC1242 goes through al} Auto-Cal cycle
which cannot be interrupted. Since the power supply, reference, and clock' will not be stable at power- up, this first
calibration cycle will not -result in an accurate calibration of
the AID. A new calibration cycle needs to be started after
the power supplies,' reference, and clock have been given
enough time ,to stabilize. During the calibration cycle, correction values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall gain; offset,
and linearity errors down to the specified limits. It should be
necessary to go through the calibration cycle only once after power up.,

3i3 INPUT BYPASS CAPACITORS
An external capacitor can be used to filter out any nOise, due
to inductive pickup by a long input lead and will not degrade
the accuracy of the conversion result.
3.4INP,UT SOURCE,RESISTANCE
The analog input can be modeled as. shown in Figure 5.
External RSE will lengthen the'time period necessary for the
voltage on CREF to settle to within % LSB of the analog
input voltage. With fClK = 2 'MHz tA = 7 clock periods =
3.5 P.s, RSE :;;; 1 k{}' will allow a 5V analog input voltage to
settle properly.
3.5 NOISE
The leads to the analog input pin should be kept as short as
possible to minimize input noise coupling. Both noise and
undesired digital clock coupling to this input can cause errors. Input filtering can be used to reduce the effects of
these noise sources.
.
3.6 POWER SUPPLIES
Noise spikes on the Vcc and V- supply lines can cause
conversion errors as the comparator will respond to this'
noise. The AID is especially sensitive during the auto:zero
or auto-cal procedures'to any pciwer supply spikes. Low in

3.B THE AUTO-ZERO CYCLE
To correct for any change in the zero (offset) error of the
AID, the auto-zero cycle can be used. It may be necessary
to do an auto-zero cycle whenever the ambient temperature
changes ,significantly. (See the curved titled "Zero Error
Change vs Ambient Temperature" in the Typical Performance Characteristics.) A ch'ange in the ambient temperature
will cause the Vas of the sampled data comparator to
change, which may cause the zero error of the AID to be
, g'reater than the amount specified. An auto-zero cycle will
maintain the zero error to the amount specified or less.

2-626

4.0 Dynamic Performance
Many applications require the AID converter to digitize ac
signals, but the standard dc integral and differential nonlinearity specifications will not accurately predict the AID converter's performance with ac input signals. The important
specifications for lIC applications reflect the converter's ability to digitize ac signals without significant spectral errors
and without adding noise to the digitized signal. Dynamic
characteristics such as signal-to-noise + distortion ratio
(S/(N + D», effective bits, full power bandwidth, aperture
time and aperture jitter are quantitative measures' of the
AID converter's capability.
An AID converter's ac performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal waveform is applied to the AID converter's input, and the transform is then performed on the digitized waveform. S/(N + D)
is calculated from the resulting FFT data, and a spectral plot
may also be obtained. Typical values for S/(N+D) are
shown in the table of Electrical Characteristics, and spectral
plots are inCluded in the typical performance curves.

Power Supply Bypassing

r-----1

vlN

DVcc

""'"==:====:::--""""'

AVcc

i-I!I!;====:--J

ADC1242

l

--~==~~ AGND
r----"I DGND

~.1~~10~~
TL/H/11735-19

·Tantalum

Protecting the Analog Inputs
+5V

The AID converter's noise and distortion levels will change
with the frequency of the input signal, with more distortion
and noise occurring at higher signal frequencies. This can
be seen in the SI (N + D) versus frequency curves. These
curves will also give an indication of the full power bandwidth (the frequency at which the SI (N + D) drops 3 dB).
Two sample/hold specifications, aperture time and aperture
jitter, are included in the Dynamic Characteristics table
since the ADC1242 has the ability to track and hold the
analog input voltage. Aperture time is the delay for the AID
to respond to the hold command. In the case of the
ADC1242, the hold command is internally generated. When
the Auto-Zero function is not being used, the hold command
occurs at the end of the acquisition window, or seven clock
periods after the rising edge of the WR. The delay between
the internally .generated hold command and the time that
the ADC1242 actually holds the input signal is the aperture
time. For the ADC1242, this time is typically 100 ns. Aperture jitter is the change in the aperture time from sample to
sample. Aperture jitter is useful in determining the maximum
slew rate of the input signal for a given accuracy. For example, an ADC1242 with 100 ps of aperture jitter operating with
a 5V reference can have an effective gain variation of about
1 LSB with an input signal whose slew rate is 12 VI /Ls.

-12V

TL1H/11735-20

fII

2-627

tflNational Semiconductor

ADC12441 Dynamically-Tested Self-Calibrating 12-Bit
Plus Sign AID Converter with Sample-and-Hold
General Description

Applications

The ADC12441 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter whose dynamic
specifications (S/N, THD, etc.) are tested and guaranteed.
On request, the ADC12441 goes through a self-calibration
cycle that adjusts positive linearity and full-scale errors to
less than ± % LSB each and zero error to less than
± 1 LSB. The ADC12441 also has the ability to go through
an Auto-Zero cycle that corrects the zero error during every
conversion.
The analog input to the ADC12441 is tracked and held by
the internal circuitry, and therefore does not require an external sample-and-hold. A unipolar analog input voltage
range (OV to + 5V) or a bipolar range ( - 5V to + 5V) can be
accommodated with ± 5V supplies.
The 13-bit word on the outputs of the ADC12441 gives a 2's
complement representation of negative numbers. The digital inputs and outputs are compatible with TTL or CMOS
logic levels.

• Digital signal processing
• Telecommunications
• Audio
• High resolution process control
• Instrumentation

Key Specifications
•
•
•
•
•
•
•
•
•
•

12 bits plus sign
13.8 ",s (max)
76.5 dB (min)
-75 dB (max)
100 ns
100 PSrms
±1 LSB (max)
±1 LSB (max)
70 mW (max)
55 kHz (max)

Resolution
Conversion Time
Bipolar Signal/Noise
Total Harmonic Distortion
Aperture Time
Aperture Jitter
Zero Error
Positive Full Scale Error
Power Consumption @ ± 5V
Sampling rate

Features
• Self-calibration provides excellent temperature stability
• Internalsample-and-hold
• Bipolar input range with single +5V reference

Simplified Block Diagram

Connection Diagram

V,. o--!-,... . . . . . _-_-----~

Dual-In-Llne Package
V,.

1

VREF

AGND

4

AVec 0---+
2
VREF 0---+

AVec
V-

0-:...

ViR

AGND

A'i.

5
V- 0---+

ClKIN

15

000 (lSB)

2B
DVCCO---+

DGND

4
5

o-!!.

CAL

001

cs

002

Rii

DB3

EOC

004

iNT

DOS

DGND

•

9
10
11
12
13
14

2B
27
26
25
24
23
ADC12441 22
21
20
19
I.
17
16
15

DVec

DB12 (Sign)
0011 (~SB)
0010
DB9
DB.
DB7
DB6
DB5
DB4
DB3
DB2
OBI
DBO (lSB)

006
Tl/H/l1017-2

007
13

Top View

DBB
009
0010
0011

0012 (Sign)

r-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-,12

nc

Conlrol logle

L----~r__r-r___r-_r_"""'lI:__-----'
110 17

111 1 9

cs

Rii

Wii

CAL

16

13

(~SO)

_
EOC
INT

IB

A'i ClKIN

Tl/H/l1017-1

2-628

Order Number
ADCI2441CMJ, ADC12441CMJ/883
or ADC12441CIJ
See NS Package Number J28A

Absolute Maximum Ratings (Notes 1 & 2)

Operating Ratings (Notes 1 & 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Temperature Range
ADC12441 CIJ
ADCI2441CMJ.
ADC12441 CMJ/BB3

Supply Voltage (Vee .;, DVee
Negative Supply Voltage (V-)

=

AVecl

6.5V
-6.5V

-55'C ~ TA ~ +125'C

DVee and AVec Voltage
(Notes6& 7)
Negative Supply Voltage (V-)

Voltage at Logic Control Inputs
-0.3V to (Vee + 0.3V)
Voltage at Analog Inputs
(V- -0.3V) to (Vee+0.3V)
(V'N and VREF)
0.3V
AVee-DVee (Note 7)
Input Current at Any Pin (Note 3)
±5mA
Package Input Current (Note 3)
±20mA
Power DiSSipation at 25'C (Note 4)
Storage Temperature Range

TMIN ~ TA ~ TMAX
-40'C ~ TA ~ +B5'C

4.5Vto 5.5V
-4.5V to -5.5V

Reference Voltage
(VREF. Notes 6 & 7)

3.5Vto AVec + 50 mV

B75mW
-65'Cto + 150'C
2000V·

ESD Susceptability (Note 5)
Soldering Information
J Package (10 sec.)

300'C

Converter Electrical Characteristics
The following speCifications apply for Vec = DVcc = AVee = +5.0Y. V- = -5.0V. VREF = +5.0V. Analog Input Source
Impedance = 600n. and fClK = 2.0 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX;
all other limits TA = TJ = 25'C. (Notes 6. T and B)
Symbol

Parameter

Conditions

Typical
(Note 9)

Limit
(Note 10)

Units
(Limit)

STATIC CHARACTERISTICS

V,N

Positive Integral Linearity Error

After Auto·Cal (Notes 11 & 12)

±Yz

LSB

Negative Integral Linearity Error

After Auto·Cal (Notes 11 & 12)

±%

LSB

Positive or Negative Differential Linearity

After Auto·Cal (Notes 11 & 12)

12

Bits

Zero Error

After Auto·Zero or Auto·Cal
(Notes 12 & 13)

Positive Full-Scale Error

After Auto·Cal (Note 12)

Negative Full-Scale Error

After Auto·Cal (Note 12)

±Yz

Analog Input Voltage
Power Supply
Sensitivity

±1

LSB(max)

±1

LSB(max)

±11 ±2

LSB(max)

V- -'0.05
Vee + 0.05

V(min)
V(max)

Zero Error (Note 14) AVcc = DVcc = 5V ±5%,
VREF = 4.75V. V- = -5V ±5%
Full·Scale Error

±Ya
±Va

LSB

Linearity Error

±Va

LSB

LSB

CREF

VREF Input Capacitance (Note lB)

BO

pF

C,N

Analog Input Capacitance

65

pF

DYNAMIC CHARACTERISTICS
Bipolar Effective Bits
(Note 17)
Unipolar Effective Bits
(Note 17)

SIN

SIN

Bipolar Signal·to·Noise Ratio
(Note 17)

Unipolar Signal·to·Noise Ratio
(Note 17)

= 1 kHz, V,N = ± 4.B5V
fiN = 20 kHz. V,N = ± 4.B5V
fiN = 1 kHz, V,N = 4.B5 Vp•p
fiN = 20 kHz. V,N = 4.B5 Vp•p
fiN = 1 kHz, V,N = ±4.85V
fiN = 10 kHz, V,N = ±4.B5V
fiN = 20 kHz. V,N = ±4.B5V
fiN = 1 kHz. V,N = 4.B5 Vp•p
fiN = 10 kHz, V,N = 4.B5 Vp•p
fiN = 20 kHz. V,N = 4.B5 Vp•p
fiN

2·629

12.6
12.6

Bits
12.4

Bits (min)

11~6

Bits (min)

II.B
II.B

Bits

7B

dB

7B

dB

7B

76.5

73

dB

·73
73

dB (min)

dB
71.5

dB (min)

Converter Electrical Characteristics
The following specifications apply for Vee = oVee =. AVcc = +5.0V, V- = -5.0V, VREF = +5.0V, Analog Input Source
Impedance =, 600n, and fClK = 2.0 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX;
all other limits TA = TJ = 25'C. (Notes 6,7 and 8) (Continued)
Symbol

Typical
Limit
(Note 9) (Notes 10, 19)

Conditions

Parameter

Units
(Limit)

DYNAMIC CHARACTERISTICS (Continued)
THO

THO

=
=
=
=

=

±4.85V

-82

=

-80

Bipolar Total Harmonic Distortion
(Note 17)

fiN

Unipolar Total Harmonic Distortion
(Note 17)

fiN

Bipolar Peak Harmonic or
Spurious Noise (Note 17)

= 1 kHz, VIN = ±4.85V
fiN = 10 kHz, VIN = ±4.85V
fiN = 20 kHz, VIN = ±4.85V
fiN = 1 kHz, VIN = 4.85 Vp.p
fiN = 10 kHz;'VIN = 4.85Vp•p
fiN = 20 kHz, VIN = 4.85 Vp-p
VIN = ±4.85V, flN1 = 19:375 kHz,
flN2 = 20.625 kHz
VIN = 4.85 Vp_p, flN1 = 19.375 kHz,
flN2 = 20.625 kHz
VIN = ±4.85V (Note 17)
VIN = 4.85 Vp_p (Note 17)

fiN

fiN

1 kHz, VIN

19.688 kHz, VIN
1 kHz, VIN

=

±4.85V

-82

4.85 Vp-p

19.688 kHz, VIN

=

4.85 Vp_p

fiN

Unipolar Peak Harmonic or
Spurious Noise (Note 17)

Bipolar Two Tone Intermodulation
Distortion (Note 17)
Unipolar Two Tone Intermodulation
Distortion (Note 17)'
-3 dB Bipolar Full Power Bandwidth
-3 dB Unipolar Full Power BlI;ndwidth

dB

-75

dB (max)
dB

-75

-80
-88

dB (max)
dB

-84

dB

-80

dB

-90

dB

-86

dB

-82

dB

-78

-74

dB (max)

-78

-73

dB (max)

25

20

kHz (Min)

30

20

kHz (Min)

Aperture Time

100

ns

Aperture Jitter

100

PSrms

Digital and DC Electrical Characteristics
The.follQwing speCifications apply for OVcc == AVcc = +5.0V, V- = -5.0V, VREF = +5.0V, and fClK = 2.0 MHz unless
otherwise specified. Boldface limits apply for T A = TJ = TMIN to T MAX; all other limits T A = TJ = 25'C.
(Notes 6 arid 7)
Symbol

Parameter

Typical
(Note 9)

Conditions

VIN(1)

Logical "1" Input Voltage for
Allinputs,except ClK IN

Vee"; 5.25V

VIN(O)

logical "0" Input Voltage for
All Inputs except ClK IN

Vee

IIN(1)

logical "1" Input Current

VIN

IIN(O)

Logical "0" Input Current

VIN

VT+

=
=
=

4.75V

Limit
(Notes 10, 19)

Units
(Limits)

2.0

V (min)

0.8

V (max)

5V

0.005

1

/LA (max)

OV

-0.005

-1

/LA (max)

ClK IN Positive-Going
Threshold Voltage

2.8

2.7

V (min)

VT-

ClK IN Negative-Going
Threshold Voltage, .

2.1

2.3

V (max)

VH

ClK IN Hysteresis
[VT+ (min) - VT- (max)]

0.7

0.4'

V (min)

VOUT(1)

logical "1" Output VoltagE!

2.4
4.5

V (min)
V (min)

0.4

V (max)

VOUT/Ol

logical "0" Output Voltage

Vcc = 4·75V:
lOUT = -360/LA
lOUT = -10/LA
Vcc

=

4.75V, lOUT

2-630

=

1.6 mA

Digital and DC Electrical Characteristics
The following specifications apply for DVcc = AVcc = +5.0V, V- = -5.0V, VREF = +5.0V, and fCLK = 2.0 MHz unless
otherwise specified. Boldface limits apply for TA = TJ = T MIN to TMAX; all other limits TA = TJ = 25°C.
(Notes 6 and 7) (Continued)
Symbol

Parameter

Conditions,

Typical
(Note 9)

Limit
(Notes 10, 19)

Units
(Limits)

TRI-STATE';' Output Leakage
Current

VOUT = OV

-0.01

-:l

",A (max)

VOUT = 5V

0.01

3

",A (max)

ISOURCE

Output Source Current

VOUT = OV

-20

-6.0

mA(min)

ISINK

Output Sink Current

VOUT = 5V

20

8.0

mA(min)

Dice

DVcc Supply Current

fCLK = 2 MHz, CS = "1"

1

2

mA(max)

Aicc

AVcc Supply Current

fCLK = 2 MHz, CS = "1"

2.8

6

mA(max)

I-

V- Supply Current

fCLK = 2 MHz, CS = "1"

2.8

6

mA(max)

lOUT

AC Electrical Characteristics
The following specifications apply for DVcc = AVec = +5.0V, V- = -5.0V, tr = t, = 20 ns unless otherwise specified.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. (Notes 6 and 7)
Symbol
fCLK

Parameter

Conditions

Units
(Limits)

0.5
4.0

2.0

MHz (min)
MHz (1l1ax)

40
60

%
% (min)
% (max)

27(1/fCLK) + 300 ns

(max)

7(1/fCLK) + 300ns

(max)

26(1/fCLK)

(max)

50

te

Conversion Time

tA

Acquisition .Time

tz

Auto Zero Time

teAL

Calibration Time

tW(CAL)L

Calibration Pulse Width

tW(WR)L

Minimum WR Pulse Width

tACC

Maximum Access Time
(Delay from Falling Edge of
RD to Output Data Valid)

CL = 100pF

TRI-STATE Control
(Delay from Rising Edge of
RD to Hi-Z State)

RL = 1 kn,
CL = 100pF

27(1/fCLK)
fCLK= 2.0 MHz

(Note 15)

RSOURCE = 50n
fCLK = 2.0 MHz

",s,

13.5
7(1/fCLK)
3.5
26(1/fCLK)

fCLK = 2.0 MHz

tpD(INT)

Limit
(Notes 10, 19)

Clock Frequency

Clock Duty Cycle

toH, t1H

Typical
(Note 9)

",s

13

",s

1396(1/fcLK)

max

fCLK = 2.0 MHz

698

706

",s(max)

(Note 16)

60

200

ns(min)

60

200

ns(min)

50

85

ns(max)

30

90

ns(max)

100

175

ns(max)

Maximum Delay from Falling Edge of
RD orWR to Reset of INT

Nate 1: Absolute Maximum Ratings indicate IimHs beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specHications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to AGND and DGND, unless otherwise specified.
Note 3: When the input voltage (YIN) at any pin exceeds the power supply rails (YIN < V- or VIN > (AVec or DVec), the current at that pin should be limited to
5 mAo The 20 mA maximum package Input current rating allows the voltage at any four pins, with an input current limit of 5 mA, to simultaneously exceed the power
supply voltages.

2-631

AC Electrical Characteristics

(Continued)

Nole 4: The 'power dissipation 01 this device under normal operation should never exceed 169 mW (Quiescent Power Dissipation +. TTL Loads on the ,digital
outputs). Caution should be taken not to exceed absolute maximum power rating when the, device Is oparating In,a severe lault condition (ex, when, any inputs or
outputs exceed the power supply). The maximum power dissipation must be derated at elevated temperatures and is diC1eted by TJmax (maximum junction
temparatura), 8JA (package Junelion to ambient thermal resistance), and TA (ambienttemparature). The maximum allowable power dissipation at any temperature
Is POmax = (TJmax - TAll8JA or the number given In the Absolute Maximum Ratings, whichever is lower. For this device, TJmax = 125'C, and the typical thermal
resistance (8JAl 01 the ADC12441 with CMJ and CIJ suffixes when board mounted Is 47'C/W.
'
Note 5: Human body model, 100 pF'dlscharge,hhrough a 1.5 kn resistor.
, Note 6,: Two on-ehlp diodes, are 'tied to the analog input as shown below. Errors in the AID conversion can occur il these diodes are lorward biased more than
5 0 m V . '

TLlH/ll 017-3
This means that II AVa; and OVa; are minimum (4,75 Vocl and V- is maximum (-4.75 Vocl, lull·scale must be
Note 7: A diode exist. between AVa; and OVa; as shown below.

~

4.8 Vro

,

I

A~:XI
, , TO
INTERNAL
CC 4
I
ClRCUIIRY
I

,

DVcc 28:

TO'INTERNAl
ClRCUIIRY

I

'

I

Tl/H/l1017-4

T~ guarantee "ccuracy, H Is required that the AVa;,and OVa; be connected together to a power supply with separate bypass filters at each Vrx phi
Nole 8: Accuracy Is guaranteed at lelK = 2.0 MHz. At higher and lower clock Irequencies accuracy may degrade, See curves In the Typical Performance
Charaeleristics section.
'
Note 9: Typicals are at TJ = 25'C and represent most likely parametric norm.
Note 10: Umlts ara guaranteed to National's AOOL (Average Outgoing QualHy LeveQ.
Note 11: Positive lineerity error Is defined as the deviation of the analog value, expressed in LSBs, from lhe straight line that passes through positive full scale and
zero. For negative'linearity error}l1e straight line passes through negative full scale and zero. (See FIgures Ib and Ie.)
,
Nole 12: The ADC12441 's self-calibration technique ensures lineerity, lull scale, and offset errors as specified, but noise Inherent in the sell·calibratlon process will
result in a repeatability uncertainty of ± 0.20 LSB.
Note 13: II T1\ changes thim an Auto-Zero or Auto-Cal cycle will have to be r...started (see the Typical Performance Characteristic curves).
Nole 14: After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes.
Nole 15: II the clock is asynchronous to tha Ialling edge 01 WI'! an uncertainty of one clock period will exist in the Interval of tA, therefore makl"g Iha minimum
tA " 6 clock periods and the maximum tA = 7 clock periods. If the falling edge 01 the clock Is synchronous to the rising edge of WI'! then tA will be ,exactiy 6.5 clock
periods.
'
Note 18: The llA[ line must be high belore a conVersion is started.
Note 17: The specifications lor these parameters are valid after an Auto-Cal cycle has been completed.
Note 18: The ,ADC1244t reference ladder Is composed solely of capaCitors.
Nole ,19: A MilHary RETS Electrical Test Specification is available on request. At time 01 printing the ADCt2441CMJ/883 RETS complies fully with the boldlace
limits In this column.
(+4095)0,1111 ,till ,1111
(+4094)0,1111,1111,1110

§

11----

_r-t-<==-_--'Z=E"'RO:..1RAN="'S:.:;mo:::N::...._ _-,-_ _--i INPUT VOLTAGE

I-VRU

+VREF'

,~:/,.//'"
FUll-SCALE TilANsmoN

1,0000,0000,0001 (-4095)
1,0000,0000,0000 (-4096)
ANALOG INPUT VOLTAGE (VIW

FIGURE 1a. Transfer Characteristic

2-632

Tl/H/l1017-5

r--------------------------------------------------------------------,
Electrical Characteristics (Continued)
+12lSB

OUTPUT CODE
(from -4096 to .+4095)

.TL/H/11017-8

FIGURE. 1b. Simplified Error Curve vs Output Code wl,hout Auto-Calor Auto-Zero Cycles

+3LSB
POSITIVE

+2LSB.

NEGATIVE
FUll-SCALE
ERROR

ZERO
ERROR

+1 LSB

.:.-.:.--=--i!'-'-'-'-'-'-"-'-=r--=--=1I-"-ii.....,prr-T==.::~.........:..:...:c...:'_=_T'--"''F'_.:..:.f_ INPUT VOLTAGE

,.=--=..!

-llSB
NEGATIVE INPUT RANGE

POSITIVE INPUT RANGE

-2LSB
-3LSB
OUTPUT CODE
(from -4096 to +4095)

TL/H/11017-7

FIGURE 1c. Simplified Error Curve vs Output Code after Auto-Cal Cycle

Typical Performance Characteristics
Zero Error Change vs
Ambient Temperature

Zero Error vs VREF
1.6

\

'iii' 1.2
~

.:!!. 1.0

""
0

....""""
0
....""

N

2

~

1.4

OB

\

AVcc = DVcc = +5.0V
V-=-5.0V
fClK = 214Hz
TA = +25OC

a.'iii'...

\

:J:

<.>

1\

D.6

0.2

""

""""
....
0

....""
N

2

3

4

". i--""
-1

". i--""

".

.....

". r'AVcc=DVcc = +5.0V
V-=-5.0V
fClK = 214Hz
VREF = +5.0V
No Calibration
No Autozero

-2
-55 -35 -15 5 25 45 65 85 105 125

D

o

0

0

"I'...

0.4

,..

'"<

:z

5

VREF (V)

AMBIENT TE... PERATURE (OC)

2-633

TL/H/ll017-B

~

....~
t....

~

"'II'
"'II'

C'I

r-----------------------------------------------------------------------------------------------,
Typical Performance Characteristics

(Continued)

~

g

o
o
....
tflNational Semiconductor
~
....
ADC1251 Self-Calibrating 12-Bit Plus Sign

AID Converter w!th Samp~e-and-Hold
General Description
The ADC1251 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter. On request, the
ADC1251 goes through a self-calibration cycle that adjusts
for any zero, full scale, or linearity errors. The ADC1251 also
has the ability to go through an Auto-Zero cycle that corrects the zero error during every conversion.
The analog input to the ADC1251 is tracked and held by the
internal circuitry, so an external sample-and-hold is not required. The ADCt 251 has an 8/H control input which directly controls the track-and-hold state of the AID. A unipolar
analog input voltage range (0 to + 5V) or a bipolar range
( - 5V to + 5V) can be accommodated with ± 5V supplies.
The 13-bit data result is available on the eight outputs of the
ADC1251 in two bytes, high-byte first and sign extended.
The digital inputs and outputs are compatible with TTL or
CMOS logiC levels.

Features

•
•
•
•

8-bit JLP/DSP interface
Bipolar input range with a single + 5V reference
No missing codes over temperature
TTL/MaS input/output compatible

Key Specifications
•
•
III
•
III
•
III

Resolution
Conversion Time
Sampling Rate
Linearity Error
Zero Error
Full Scale Error
Power Consumption

12 bits plus sign
8 JLs (max)
83 kHz (max)
±0.6 LSB (±0.0146%) (max)
±1 LSB (max)
± 1.5 LSB (max)
113 mW (max)
@ ± 5V

Applications
Digital signal processing
III High resolution process control
C Instrumentation
III

III Self-calibration provides excellent temperature stability
III Internal sample-and-hold

Simplified Block Diagram

Connection Diagram
Dual-In-Line Package

-..-_-------1

.
I
V,N ~ ';':
I

,4,
5/H

e>--+

VREf

e>--+

EOC

AVec

4

CAL

24

e>--+

22

AOCI251

CLKIN

21

00

20

OB7/0B12

19

OB6/0B12

18

OB5/DBI2

17

084/0BI2

9

16

OB3/0BII

cs

1D

15

OB2/0BIO

DOl/DOg

S/H

11

OBI/OB9
OBD/OB8

002/0010

12

DVec

000/008

v- e>--+

DGND

iffi

3

ViR

3
AGND Q----JIio
5

e>--+

23

Az

2

DVee

24

yo

4

AVec

VIN
VR£F
AGNO

003/0011

TL/HI11024-2

D04/oB12
D05/DB12
D06/DB12
DB7/oBI2

. . Eoe

r----------------~

~_,,_.._,,_.._,,_.._,,----r--roo
5/H

Cs

WR

Rii

CAL

AI

elKIN

TLlH/11024-1

Top View

Ordering Information
Industrial
(- 400C ,;; TA ,;; + a5.C)
ADC1251BIJ,
ADC1251CIJ

Military
(-55·C ,;; TA';;

J24A

+ 125.C)

ADC1251CMJ,
ADC1251 CMJ/883
2-641

Package

Package
J24A

•

Absolute Maximum Ratings

Operating Ratings

(Notes 1 & 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
6.5V
SupplyVoltage(Vcc = DVcc = AVcc) ,
-6.5V
Negative Supply Voltage (V-)
Voltage at Logic Control Inputs
-0.3Vto (Vcc+0.3V)
Voltage at Analog Inputs
(V- -0.3V) to (Vcc+0.3V)
(VREF, VIN)
0.3V
AVcc-Dilcc (Note 7)
Input Current at Any Pin (Note 3)
±5mA
±20mA
Package Input Current (Note 3)
Power Dissipation at 25'C (Note 4)
875mW
Storage Temperature Range
ESD Susceptability (Note 5)

(Notes 1 & 2)

Temperature Range
ADC1251 BIJ, ADC1251 CIJ
ADC1251CMJ
ADC1251CMJ/883

TMIN s: TA s: TMAX
-40'C s: TA s: + 85'C
-55'C s: TA s: +125'C
-55'C:s: TA:S: +125'C

DVcc and AVcc Voltage
(Notes6& 7)
Negative Supply Voltage (V-)

4.5Vto 5.5V
-4.5V to -5.5V

Reference Voltage
(VREF, Notes 6 & 7)

"

3.5Vto AVcc+50 mV

- 65'C to + 150'C
2000V

Soldering Information
, J Package (10 sec.)

300'C

Converter Electrical Characteristics
The following specifications apply for VCC = DVCC = AVCC = +5.0V, V- = -5.0V, VREF = +5.0V, AZ = "1", fClK =
3.5 MHz and tested using WR control unless otherwise specified. Boldface limits apply for TA = TJ = T MIN to T MAX; all other
limits TA = TJ = 25'C. (Notes 6, 7 and 8)
,Parameter

Symbol

Typical
Limit
(Note 9) (Notes 10, 19)

Conditions

~nlts

(Limit)

STATIC CHARACTERISTICS
Positive Integral
Linearity Error

ADC1251BIJ
ADC1251CIJ

After Auto-Cal
(Notes 11 & 12)

ADC1251CMJ
Negative Integral
Linearity Error

ADC1251BIJ
ADC1251CIJ

After Auto-Cal
(Notes 11 and 12)

ADC1251CMJ
After Auto-Cal (Notes 11 and 12)

Missing Codes
Zero Error (Notes 1? and 13)

AZ

=

"0" and fClK

=

=

AZ

Negative Full-Scale Error (Note 12)

AZ =

"0" and fClK

1.75 MHz

=

1.75 MHz

=

1.75 MHz

After Auto-Cal Only
"0" and fClK

After Auto-Cal Only
CREF

VREF Input Capacitance (Note 18)

80

CIN

Analog Input Capacitance

65

VIN

Analog Input Voltage
Power Supply Sensitivity

LSB(max)

±i

LSB(max)

±i

LSB(max)

±0.6

LSB(max)

±i

LSB(max)

±i'

LSB(max)

0

After Auto-Cal Only
positive Full-Scale ErrOr (Note 12)

±0.6

±2

LSB(max)

±2.0/±,3.0

LSB(max)

±i.5

LSB(max)

±1.5/±2.0

LSB(max)

±i.5

LSB(max)

±1.5/±2.0

LSB(max)
pF
pF

V- - 0.05
Vee + 0.05
Zero Error (Note 14) AVCC = DVcc = 5V ±5%,
VREF = 4.75V, V- = -5V ±5%
Full-Scale Error
Linearity Error

"

2-642

±Ys

V(min)
V(max)
LSB

±Ys

LSB

±Ys

LSB

Converter Electrical Characteristics (Continued)

»
c

"

-

The following specifications apply for Vee = DVee = AVee = +S.OV, V- = -S.OV, VREF = +S.OV, AZ = ,"1" and felK
= 3.S MHz unless otherwise specified. Boldface limits apply for TA.= TJ = TMIN to TMAX; all other limits TA = TJ = 2SoC.
(Notes 6, 7 and 8)
Conditions

Typical
(Note 9)

Unipolar Signal-to-Noise+ Distortion
Ratio (Note 17)

fiN = 1 kHz, VIN = 4.85 Vp_p

72

dB

fiN = 20 kHz, VIN = 4.8S Vp_p

72

dB

Bipolar Signal-to-Noise+ Distortion
Ratio (Note 17)

fiN = 1 kHz, VIN = ±4.85V

76

dB

fiN = 20 kHz, VIN = ±4.8SV

76

dB

-3 dB Unipolar Full Power Bandwidth

VIN = 4.8SV, (Note 17)

32

kHz

-3 dB Bipolar Full Power Bandwidth

VIN = ,±4.8SV, (Note 17)

2S

kHz

Symbol

Parameter

Limit
(Notes 10, 19)

o....
N

....U1

Units
(Limit)

DYNAMIC CHARACTERISTICS
S/(N+D)

S/(N+D)

tAp

Aperture Time

100

ns

Aperture Jitter

100

PSrms

Digital and DC Electrical Characteristics
The following specifications apply for DVee = AVee = +5.0V, V- = -S.OV, VREF = +5.0V, and felK = 3.5 MHz unless
otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAXi all other limits TA = TJ = 2SoC. (Notes 6 and 7)
Symbol

Parameter

Conditions

Typical
(Note 9)

Limit
(Notes 10, 19)

Units
(Limit)

2.0

V(min)

0.8

V(max)

VIN(1)

Logical "1" Input Voltage for
All Inputs except ClK IN

Vee = S.2SY

VIN(O)

logical "0" Input Voltage for
All Inputs except ClK IN

Vee = 4.7SV

IIN(1)

logical "1" Input Current

VIN = 5V

O.OOS

1

/LA(max)

IIN(O)

logical "0" Input Current

VIN = OV

-O.OOS

-1

/LA(max)

VT+

ClK IN Positive-Going
Threshold Voltage

. 2.8

2.7

V(min)

VT-

ClK IN Negative-Going
Threshold Voltage

2.1

2.3

V(max)

VH

ClK IN Hysteresis
[VT+(min) - VT-(max))

0.7

0.4

V(min)

VOUT(1)

logical "1" Output Voltage

2.4
4.5

V(min)
V(min) .

0.4

V(max)'

Vee = 4.7SV:
lOUT = -360/LA
lOUT = -10)LA

VOUT(O)

logical "0" Output Voltage

Vee = 4.75V,
lOUT = 1.6 mA

lOUT

TRI-STATE® Output leakage
Current

VOUT = OV

-0.01

-3

)LA(max)

VOUT = SV

0.01

3

/LA(max)

ISOUReE

Output Source Current

VOUT = OV

-20

-6.0

mA(min)

ISINK

Output Sink Current

VOUT = SV

20

8.0

mA(min)

Dlee

DVee Supply Current

CS = "1"

1

2.5

mA(max)

Alee

AVee Supply Current

CS = "1"

4

10

mA(max)

I-

V- Supply Current

CS = "1"

2.8

10

mA(max)

2-643

•

....
....
o

In
N

AC Electrical Characteristics
The following specifications apply for DVcC = AVCC = +5.0V, V- = -5.0V, tr = tl = 20 ns unless otherwise specified.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ "" 25'C. (Notes 6 and 7)

c

ocr:

Symbol

Parameter

Conditions

Typical

Limit

Units

(Note 9)

(Notes 10, 19)

(Limit)

Clock Frequency

fClK

MHz
0.5

MHz(min)

6.0
Clock Duty Cycle

Ie

Conversion Time Using WR
to Start a Conversion

fClK

Conversion Time Using S/H
to Start a Conversion

tA

Acquisition Time (Note 15)

tlA

Internal Acquisition Time

=
=

3.5 MHz, AZ

= "1"
= "0"

1.75 MHz, AZ

AZ = "1"
fClK

=

3.5 MHz, AZ

RSOURCE

=

=

"1"

50n

(When Using WR' Control Only)
Auto Zero Time + Acquisition Time

tZA

1M

=

%(min)

60

% (rTuix)

27(1/fCLK) + 250 ns

(max)

7.7

7.95

/Ls(max)

15.4

15.65

/Ls(max)

34(1/fClK)

34(1/fCLK) +250 ns

(max)

9.7

9.95

/Ls(max)

3.5

3.5

/Ls(min)

7(1/fClK)

7(1/fCLK)

(max)

33(1/fclK)

33(1/fCLK) + 250 ns

(max)

1.75 MHz

18.8

19.05

/Ls(max)

200

350

ns(max)

Using S/H Control

100

150

ns(max)

1399(1/fclK>

1399 (1/fCLK)

(max)

399

400

/Ls(max)

Calibration Time
fClK

tW(~L Calibration Pulse Width

40

Using WR Control

fClK
to(EOC)l Delay from Hold Command
to Falling Edge of EOC

MHz(max)
%

27(1/fClK)

fClK

Ie

,3.5

50

=

3.5 MHz

200

ns(min)

200

ns(min)

50

95

ns(max)

30

70

ns(max)

of RD or WR' to Reset of INT

100

175

ns(max)

Delay between Successive RD Pulses

30

60

ns(min)

Minimum WR Pulse Width

tACC

Maximum Access Time

60

"

60

tW(WFi)l

(Note 16)

Cl'*' 100pF

(Delay from Falling Edge of

R'I5 to Output Data Valid)
toH, t1H

TRI-STATE Control

Rl

=

1 kn, Cl

=

100 pF

(Delay from Rising Edge of
"

tpD(1N'i')

tRR

R'I5 to Hi-Z State)
Maximum Delay from Falling Edge

Note 1: Absolute Maximum Ratings Indicate limits beyond which damage to the device may occur. Operating Ratings Indicate conditions lor which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics, The guaranteed
specifications apply only lor the test condnlons listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to AGND and DGND, unless otherwise ~pecilied.
Note 3: When the Input voltage (YIN) at any pin exceeds the power supply rails (VIN < V- or VIN > (AVec or DVec), the current at that pin should be limited to
5 mAo The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current limit 01 5 mA, to simultaneously exceed the power
supply voltages. ,
Note 4: The power dissipation 01 this device 'under normal operation shouid never exceed 191 mW (Quiescent Power Dissipation + 1 TTL load on each digital
output). Caution should be taken not to exceed absolute maximum power rating when the device is operating in severe fault condition (ex. when any inputs or
outputs exceed the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction
temperature), 8JA (package iunction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperatur~
Is POmax = (TJmax - TA)/8JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax = 150'C, and the typical thermal
resistance (8JN 01 the ADC1251 with CMJ, BIJ, and CIJ suffixes when board mounted is 51'C/W.
Note 5: Human body model, 100 pF discharged through a 1.5 kn resistor.

2-644

l>

Electrical Characteristics (Continued)

g
.....

Note 6: Two on-chip diodes are tied 10 the analog input as shown below. Errors in the AID conversion can occur if these diodes are forward biased more than
50 mV. This means that if AVcc and DVcc are minimum (4.75 Vee) and V- is maximum (-4.75 Vee), the analog input full-scale voltage must be :s: ±4.8 Vec.

U'1
.....

N

DVcc

TL/H/ll024-4

Note 7: A diode exists between AVec and DVcc as shown below.
I

I'
I

AVCC:II:I

DVcc

24:

~~R~~~::AL .
TO INTERNAL
CIRCUITRY

I
I

TL/H111024-5

To guarantee accuracy, it is required that the AVec and DVcc be connected together to a power supply with separate bypass filters at each Vec pin.
Note 8: Accuracy is guaranteed at fCLK = 3.5 MHz. At higher or lower clock frequencies accuracy may degrade. See the Typical Performance Characteristics
curves.
Note 9: Typicals are at TJ = 25"C and represent most likely parametric norm.
Note 10: Umits are guaranteed to National's AOQL (Average OutgOing Quality Level).
Note 11: Positivelineanty error is defined as the deviation of the analog value, exprassed in LSBs, from the straight line that passes through positive full scale and
zero. For negative linearity error the straight line passes through negative full scale and zero. (See Figuf9s Ib and Ie).
Note 12: The ADC1251's self-calibration technique ensures linearity. full scale, and offset errors as specified, but noise inherent in the self-calibration process will
result in a repeatability uncertainty of ± 0.20 LSB.
Note 13: If TA changes then an Auto-Zero or Auto-Cal cycle will have to be re-started. Sae the typical performance characteristic curves.
Note 14: After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes.
Note 15: When using the WR control to start a conversion if the clock is asynchronous to the rising edge of WR an uncertainty of one clock period will exist in the
end of the Interval tA, therefore making tA end a minimum 6 clock periods or a maximum 7 clock periods after the rising edge of WR. If the falling edge of the clock
is synchronous to the rising edge of WR then tA will end exactly 6.5 clock periods after the rising edge of WFi. This does not occur when S/H control is used.
Nota 16: The Wi[ line must be high before a conversion is started.
Note 17: The specifications for these parameters are valid after an Auto-Cal cycle has been completed.
Note 18: The ADC1251 reference ladder is composed solely of capacitors.
Note 19: A MiI~ary RETS Electrical Test Specification is available on request. At time of printing the ADC1251CMJ/883 RETS specification complies fully with the
boldface limits in this column.
(+4095)0,1111,1111,11 11
(+4094)0,1111,1111,1110

~O

1-------

(2) 0,0000,0000,0010
(1) 0,0000,0000,0001
ZERO TRANSmON
(0) 0,0000,0000,0000 -.-+-'==--=::...::==::.....-------lINPUT VOLTAGE

5 -VREF

+VREF

~.::................
FULL-SCALE TRANSmoN

1,0000,0000,0001 (-4095)
1,0000,0000,0000 (-4096)
ANALOG INPUT VOLTAGE (YIN)

FIGURE 1a. Transfer Characteristic

2-645

TLlH/l1024-6

•

Electrical Characteristics (Continued)
+12LSB

-12LSB

OUTPUT CODE
(from -4096 to +4095)

TL/H/ll024-7

FIGURE 1b. Simplified Error Curve vs Output Code without Auto-Cal or Auto-Zero Cycles

+3LSB
NEGATIVE
FULL-SCAlE
ERROR

POSITIVE
ZERO
ERROR

:.r-.:.*=--.:.-..:-,*;-:-:.:-:.:-::...::,-F-"""Y=:.;.;....,.....-r-q==.::::..::..1-=-=-=:..=...!:.r-9,=--.:.-..:-'f- INPUT VOLTAGE
-1 LSB
NEGATIVE, INPUT RANGE

POSITIVE INPUT RANGE

-2LSB
';'3LSB
OUTPUT CODE
(from -4096 to +4095)

TLlH/ll024-8

FIGURE 1c. Simplified Error Curve vs Output Code after Auto-Cal Cycle

Typical Performance Characteristics
Zero Error Change vs
Ambient Temperature

Zero Error vs VREF
1.6

\

1.4
1

r-. r-. t-..

= =

~

, i--"

AVec DVec +5.DV
Y-=-5.DV
1 fQJC = 3.51/Hz
VREI"=+5.DV
No Callbrallon
No Auto-Z...

-2

-ss -35-15

5 25 45 65 85 105125

AMBIENT TEMPERATURE (OC)

s1.2

g

1.0

~

Q.4

\
\

I o.ao.a

Linearity Error vs VREF
1.4

AVec = DVec = +5.DV
V-=-5.0V
IQJC = 3.5 MHz
TA =+25"1:

1.2

'§'
~

\

1.0

\
\
\

AVec = DVec = +5.DV
V-=-5.DV
IQJC =3.5 MHz
TA =+25OC

1\

"- ..........

112

o

o

2

3

-

4

5

VREI" (V)
TLlH/l1024-9

2-646

:I>

Typical Performance Characteristics

DB

r~::~;-cc-=-;rN::cc-=-;+':"5.-::0V:-r---r-'

! 0.5~ I
! K~rn:Pr

.s

I

OA

;

n2 f---t-+-1I--+-+-----j

o·

I--t-+--II--l---.,.",V~-i
~ M~+-~~~~~~

~f-HIgI18y"

088-0012

Iow.y"
DBO-DB7

TLlH/ll024-17

2-649

Timing Diagrams (Continued)
Using WR Control to Start a Conversion without Auto-Zero (CAL = 1, AZ = 1)

'ClOC'~11.rLJln
a~

~

IACeb

r---""""""-----i
.. 27 docks

"',......,/OB12

~

JRt-oSlAlt

--T-------------.----~~----------~----~~--------------,
-;,',
•
. , '

HIghBytt

---

008·0012

TL/H/ll024-18

Using 5tH Control to Start a Conversion without Auto-Zero (AZ = 1, CAL. "" 1)

Cs~,-.__________!~______~'/
.

H

.

.. S/H. - ,. { ,....;---------11-------.1]
. .

iiR@

~I_----'--

tA Acquisition

----~

!

.-I-Io(''')L

[oe --------------~!~.~----~I

I
'P'(iNT)-

1 - - - - - Con.,;rslon ----~\1--1-.1-1
N34clocks
DBO/D88-D87/D1I12

-----------------.,S---------

TRI-STATE

tACC-b ----0

-----------.,50-----------

HlghS)'t,

LO'II'Byte

088-0812

DBO-DB7

TLlH/ll024-19

2-650

:J>
C

1.0 Pin Descriptions
OVec (24),
AVec (4)

The digital and analog positive power supply
pins. The digital and analog power supply
voltage range of the AOC1251 is +4.5V to
+ 5.5V. To guarantee accuracy, It Is required
that the AVec and OVee be connected together to the same power supply with separate bypass capacitors (10 ""F tantalum in
parallel with a 0.1 ""F ceramic) at each Vee
pin.

V- (5)

The analog negative supply voltage pin. Vhas a range of -4.5V to -5.5V and needs
bypass capacitors of 10 ""F tantalum in parallel with a 0.1 ""F ceramic.

OGNO (12),
AGNO (3)

The digital and analog ground pins. AGNO
and OGNO must be connected together externally to guarantee accuracy.

VREF(2)

The reference input voltage pin. To maintain
accuracy the voltage at this pin should not
exceed the AVee or OVec by more than
50 mV or go below + 3.5 Voc.

The Chip Select control input This input is
active low and enables the WR', R15 and S/H
functions.

RO(23)

The Read control input. With both ~ and R15
low the TRI-STATE output buffers are enabled and the TNT output is reset high.

WR(7)

The Write control input. The conversion is
started on the rising edge of the WR pulse
when CS is low. When this control line is
used the end of the analog input voltage acquisition window is internally controlled by the
AOC1251.

S/H (11)

The external clock input pin. The typical clock
frequency range is 500 kHz to 6.0 MHz.

CAL (9)

The Auto-Calibration control input. When
CAL is low the AOC1251 is reset and a calibration cycle is initiated. During the calibration cycle the values of the comparator offset
voltage and the mismatch errors in the capacitor reference ladder are determined and
stored in RAM. These values are used to correct the errors during a normal cycle .of AID
conversion.

AZ(6)

The Auto-Zero control input. With the 7i.'l. pin
held low during a conversion, the AOC1251
goes into an auto-zero cycle before the actual AID conversion is started. This Auto-Zero
cycle corrects for the comparator offset voltage. The total conversion time (te) is increased by 26 clock periods when Auto-Zero
is used.

INT(21)

The Interrupt control output. This output goes
low when a conversion has been completed
and indicates that the conversion result is
available in the output latches. Reading the
result or starting a conversion or calibration
cycle will reset this output high.

OBO/OB8OB7/0B12
(13-20)

The TRI-STATE output pins. Twelve bit plus
sign output data access is accomplished using two successive ROs of one byte each,
high byte first (OB8-0B12). The data format
used is two's complement sign bit extended
with OB12 the sign bit, OB11 the MSB and
OBO the LSB.

I\)

....

CI1

2.0 Functional Description

2.1 DIGITAL INTERFACE
On power up, a calibration sequence should be initiated by
pulsing CAL low with CS and 8/H high. To acknowledge the
CAL signal, EOC goes low after the falling edge of CAL, and
remains low during the calibration cycle of 1399 clock periods. During the calibration sequence, first the comparator's
offset is determined, then the capacitive OAC's mismatch
errors are found. Correction factors for these errors are then
stored in internal RAM.

The sample and hold control input. This control input can also be used to start a conversion. With CS low the falling edge of S/H
starts the analog input acquisition window.
The rising edge of S/H ends the acquisition
window and starts a conversion.

CLKIN(8)

The End-of-Converslon control output. This
output is low during a conversion or a calibration cycle.

The AOC1251 is a 12-bit plus sign AID converter with the
capability of doing Auto-Zero or Auto-Cal routines to minimize zero, full-scale and linearity errors. It is a successiveapproximation AID converter consisting of a OAC, comparator and a successive-approximation register (SAR). AutoZero is an internal calibration sequence that corrects for the
AID's zero error caused by the comparator's offset voltage.
Auto-Gal is a calibration cycle that not only corrects zero
error but also corrects for full-scale and linearity errors
caused by OAC inaccuracies. Auto-Cal minimizes the errors
of the AOC1251 without the need for trimming during its
fabrication. An Auto-Cal cycle can restore the accuracy of
the AOC1251 at any time, which ensures accuracy over
temperature and time.

The analog input voltage pin. To guarantee
accuracy the voltage at this pin should not
exceed Vee by more than 50 mV or go below
V- by more than 50 mV.
C8(10)

EOC(22)

o
....

A conversion can be initiated by taking CS and WR low. If
AZ is Iowan Auto-Zero cycle, which takes approximately 26
clock periods, is inserted before the analog input is sampled
and the actual conversion is started. AZ must remain low
during the complete conversion sequence. After Auto-Zero
the acquisition opens and the analog input is sampled for
approximately 7 clock periods. If AZ is high, the Auto-Zero
cycle is not inserted after the rising edge of WR. In this case
the acquisition window opens when the ADC1251 completes a conversion, Signaled by the riSing edge of EOC. At
the end of the acquisition window EOC goes low, Signaling
that the analog input is no longer being sampled and that
the AID successive approximation conversion has started.

2-651

fII

.1.1)
.-

C'I

o
C

 must
start after the conversion result high and low bytes have
been read. This is necessary since activating and deactivating the digital outputs (DBO/DB7-DBB/DB12) causes current fluctuations in the ADCt251 's internal DVcc lines. This
generates digital noise which couples into the capacitive
ladder that stores the analog input voltage. Therefore, the
time interval between the rising edge of EOC and the second read is inappropriate for analog input voltage acquisition.

>---......-1>

"

TLll;lll1D24-21

FIGURE 5. Switching between a Conversion with and
without Auto-Zero when Using WR Control

3.3 INPUT CURRENT
Because the input network of the ADC1251 is made up of a
switch and a network of capacitors a charging current will
flow into or out of (depending on the input voltage polarity)
the analog input pin (VIN) on the start of the analog input
sampling period. The peak value of this current will depend
on the actual input voltage applied and the source resistance.
3.4 NOISE
The leads to the analog input pin should be kept as short as
possible to minimize input noise coupling. Both noise and
undesired digital clock coupling to this input can cause errors. Input filtering can be used to reduce the effects of
these noise sources.

When WR is used to start a conversion with AZ low the
Auto-Zero cycle is inserted before the acquisition window. in

2-653

•

~

~
..-

8c

r------------------------------------------------------------------------------------------,
3.0 Analog Considerations (Continued)
change. Since Auto-Zero cannot be activated with 5/H conversion method it may be necessary to do a calibration cycle more than once.

3.5 INPUT BYPASS CAPACITORS
An external capacitor can be used to filter out any noise due
to inductive pickup by a long input lead and will not degrade
the accuracy of the conversion result.

3.9 THE AUTO-ZERO CYCLE
To correct for any change in the zero (offset) error of the
AID, the Auto-Zero cycle can be used. It may be necessary
to do an Auto-Zero cycle whenever the ambient temperature changes significantly. (See the curve titled "Zero Error
Change vs Ambient Temperature" in the Typical Performance Characteristics.) A change in the ambient temperature
will cause the Vas of the sampled data comparator to
change, which may cause the zero error of the AID to be
greater than ± 1 LSB. An Auto-Zero cycle will maintain the
zero error to ± 1 LSB or less.

3.6 INPUT SOURCE RESISTANCE
The analog input can be modeled as shown in 'Figure 6.
External Rs will lengthen the time period necessary for the
voltage on CREF to s~ttle to within % LSB of the analog
input voltage. With tA = 3.5 p.s, Rs ,;; 1 kO will allow a 5V
analog input voltage to settle properly.

3.7 POWER SUPPLIES
Noise spikes on the Vee and V- supply lines can cause
conversion errors as the comparator will respond to this
noise. The AID is especially sensitive during the Auto-Zero
or -Cal procedures to any power supply spikes. Low inductance tantalum capacitors of 10 p.F or greater paralleled
with 0,1 ,...F ceramic capaCitors are recommended for supply
bypassing. Separate bypass capacitors should be placed
close 'to the DVec, AVec and V-'pins. If an unregulated
voltage source is available in the system, a separate
LM340LAZ-5,0 voltage. regulator for the A-to-D's Vee (and
other" analog circuitry) will greatly reduce digital noise on the
supply line.
.

4.0 Dynamic Performance
Many applications. require the AID converter to digitize AC
Signals, but the standard DC integral and differential nonlinearity specifications will not accurately predict the AID converter's performance with AC input signals. The important
specifications for AC applications reflect tlie converter's
ability to digitize AC, signals without significant spectral errors and without adding noise to the digitized signal. Dynamic characteristics such as signal-to-noise + distortion ratio
(S/(N + D», effective bits, full power bandwidth, aperture
time and aperture jitter are quantitative measures of the
AID converter's capability.
An AID converter's AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal
waveform is applied to the AID converter's input, and the
transform is then performed on the digitized waveform. SI
(N + D) is calculated from· the resulting FFT data, and a
spectral plot may also be obtained. Typical values for SI
(N + D) are shown in the table of Electrical Characteristics,
and spectral plots are included in the typical performance
curves.
The AID converter's noise and distortion levels will change
with the frequency of the input signal, with more distortion
and noise occurring at higher signal frequencies. This can
be seen in the S/(N+D) versus frequency curves. These
curves will also give an indication of the, full power bandwidth (the frequency at which the S/(N + D) drops 3 dB).

3.8 THE CALIBRATION CYCLE
On power up the ADC1251 goes through an Auto-Cal cycle
which cannot be interrupted. Since the power supply, reference, and clock will not be stable at power up, this first
calibration cycle will not result in an accurate calibration of
the AID. A new calibration cycle needs to be started aiter
the power supplies, reference, and clock have been given
enough time to stabilize. During the calibration cycle, correction values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall full scale,
offset, and linearity errors down 'to the specified limits. Full
scale error typically changes ± 0.2 LSB over temperature
and linearity error changes even less; therefore it should be
,necessary to go through the calibration cycle only once aft~r power up ,it Auto-Zero is ,used to correct'the zero error

TL/H/11 024-22

FIGURE 6. Analog Input Equivalent Circuit

2-654

.--------------------------------------------------------------------.>
c
4.0 Dynamic Performance (Continued)
o
....
N
the ADC1251 actually holds the input signal is the aperture
Two sample/hold specifications, aperture time and aperture
....
time. For the ADC1251, this time is typically 100 ns. Aperjitter, are included in the Dynamic Characteristics table
CII

ture jitter is the change in the aperture time from sample to
sample. Aperture jitter is useful in determining the maximum
slew rate of the input signal for a given accuracy. For example, an ADC1251 with 100 ps of aperture jitter operating with
a 5V reference can have an effective gain variation of about
1 LSB with an input signal whose slew rate is 12 V/",s.

since the ADC1251 has the ability to track and hold the
analog input voltage. Aperture time is the delay for the AID
to respond to the hold command. In the. case of the
ADC1251 when using the 5/H control to start a conversion,
the hold command is generated by the rising edge of 5/H.
The delay between the rising edge of 5/H and the time that

5.0 Typical Applications
Power Supply Bypassing
OVcc ....=:!"====--~

, - - - - - t V,N

,---::===--....

VREF

=:!"====---

AVec ....

AOCI251

--~::::::!!!ii~ AGNO
V-

t-I!!!===----.

~.,P~,OP~

r---~OGNO.

• Tantalum
•• Ceramic

TL/H/l1024-23

Protecting the Analog Inputs
+5V

-12V

TLiH/ll024-24

Note: External protection diodes should be able to withstand the op amp current limit

2-655

.- r--------------------------------------------------------------------------------,
~
.-

~

tfI N a t~

0

n a I S e m i c on due tor

ADC 12451 Dynamically-Tested Self-Calibrating
12-Bit Plus Sign AID Converter with Sarrlple~and-Hold
General Description
The ADC12451 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter whose dynamic
specifications (S/N, THO, etc.) are tested and guaranteed.
On request, the ADC12451 goes through a self-calibration
cycle that adjusts linearity, zero and full-scale errors. The.
ADC12451 also has the ability to go through an Auto-Zero.
cycle that corrects the zero error during every bonversion.
The analog input to the ADC12451 is tracked and held by
the Internal circuitry, so an external sample-and-hold is not
required. The ADC12451 has a S/~ control input which directly controls the track-and-hold state of the AID. A unipolar analog input voltage range (OV to + 5V) or a bipolar
range (- 5V to + 5V) can be accommodated with ± 5V supplies.
The 13-bit data result is available on the eight outputs of the
ADC12451 in two bytes, high-byte firstand sign.extended.
The digital Inputs and outputs are compatible with TTL or
CMOS logic levels.

Applications
• Digital Signal Processing
• Audio

• Telecommunications
• High Resolution Process Control
• Instrumentation

Features
•
•
•
•

Self-calibration provides excellent temperature stability
Internal sample-and-hold
8-bit I£P/DSP interface·
Bipolar input range with a single + 5V reference

Key Specifications
•
•
•
•
•
•
•
•
•
•

Simplified Block Diagram
V,N

12 bits plus sign
7.7 I£s (max)
83 kHz (max)
73.5 dB (min)
- 78.0 dB (max)
100 ns
100 PSrrns
±2 LSB (max)
± 1.5 LSB (max)
113 mW (max)

Resolution
.
Conversion Time
Sampling Rate
Bipolar Signal/Noise
Total Harmonie Distortion
ApertUre Time
Aperture Jitter
Zero Error
Positive Full-Scale Error
Power Consumption @ ± 5V

Connection Diagram
Dual·ln·Une Package

o-!...& ~,-.-.....------------1
I
I

AVec

4

24
23
22
21

0--+

yo

5

2D

097/0812

2

Ai
VIii

19
18

086/0812
DBS/0812

V1N
. VREF

,',

s/H

1

AGHD
AVec

4

VREFo--+
AGND

3

0--+
5

v-o--+
DBD/DBa
DVec

DBI/DB9

24

0--+

DBl/DB1D
DB3/DB11

DGNDA

AllC12451

iiii
EOC

00

CU<1N

8

17

084/0812

CAL

9

16

10

IS

DBS/0811
082/0810

5/H . II

14
13

DBO/DBB

cs

DGND

12

081/DB9

TLlH1I1025-2

DB4/DBll
DBS/DBll

DVec

Top View

DB6/DBll
DB7/DBll

EDC

~

__~~~~~~~~~~________r-~oo
S/H

Cs

iii

iiii

CAL

Ai

ClKIN

TLlH/ll025-1

Ordering Information
Industrial
(-40'C s: TA s: 85"C)

ADC12451CIJ

J24A

Military
(-55"C s: TA s: 12S0 C) Package

ADC12451 CMJ,
ADC12451 CMJ/883
2-656

Package

J24A

Absolute Maximum Ratings (Notes 1 & 2)

Operating Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
6.5V
SupplyVoltage(Vcc = DVcc = AVcc)
Negative Supply Voltage (V -)
-6.5V

Temperature Range
ADC12451 CIJ
ADC12451CMJ,
ADC12451CMJ/883

Power Dissipation at 25'C (Note 4)
Storage Temperature Range

TMIN ,;; TA';; TMAX
-40'C ,;; TA ,;; +85'C
-55°C,;; TA';; + 125°C

DVee and AVec Voltage
(Notes 6 & 7)
Negative Supply Voltage (V-)

Voltage at Logic Control Inputs
-0.3Vto (Vcc + 0.3V)
Voltage at Analog Inputs
(V- -0.3V) to (Vcc + 0.3V)
(VIN, VREF)
0.3V
AVcc·DVcc (Note 7)
±5mA
Input Current at any Pin (Note 3)
Package Input Current (Note 3)
±20mA

»
c

(Notes 1 & 2)

Reference Voltage
(VREF, Notes 6 & 7)

4.5Vto 5.5V
-4.5Vto -5.5V
3.5VtoAVcc + 50mV

875mW
-65'Cto +150'C
2000V

ESD Susceptability (Note 5)
Soldering Information
J Package (10 Seconds)

300'C

Converter Electrical Characteristics
The following specifications apply for Vcc = DVcc = AVcc = +5.0V, V- = -5.0V, VREF = +5.0V, using 5/H input for
conversion control, and fClK = 3.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all
other limits TA = TJ = 25°C. (Notes 6, 7 and 8)
Symbol

Parameter

Conditions

Typical
(Note 9)

Limit
(Note 10, 19)

Units
(Limit)

STATIC CHARACTERISTICS
Positive Integral Linearity Error

After Auto·Cal, (Notes 11 & 12)

±1f2

LSB

Negative Integral Linearity Error

After Auto·Cal, (Notes 11 & 12)

±1f2

LSB

Positive or Negative Differential Linearity

After Auto·Cal (Notes 11 & 12)

12

Bits

Zero Error (Notes 12 & 13)

AZ = "0", fClK = 1.75 MHz

±1

LSB

After Auto·Cal Only
Positive Full·Scale Error (Note 12)

AZ = "0", fClK = 1.75 MHz
Auto·Cal Only

Negative Full·Scale Error (Note 12)

AZ = "0", fClK = 1.75 MHz

Analog Input Voltage
Power Supply Sensitivity Zero Error (Note 14) AVec = DVcc = 5V ±5%,
VREF = 4.75V, V- = -5V ±5%
Full-Scale Error

LSB(max)

±1.5/±2.S

LSB(max)

LSB

±1

Auto·Cal Only
VIN

±2/±3.0
±1

LSB

±1.5/±3.0

LSB(max)

\f- - O.OS
\fcc + O.OS

V(min)
V(max)

±Ya

LSB

±Ya

LSB

±Ya

LSB

CREF

VREF Input Capacitance

80

pF

CIN

Analog Input Capacitance

65

pF

Linearity Error

DYNAMIC CHARACTERISTICS
Bipolar Effective Bits (Note 17)

Unipolar Effective Bits (Note 17)

SIN

Bipolar Signal to Noise Ratio (Note 17)

fiN = 1 kHz, VIN = ±4.85V

12.6

fiN = 20.67 kHz, VIN = ±4.85V

12.6

fiN = 1 kHz, VIN = 4.85 Vp•p

11.8

fiN = 20.67 kHz, VIN = 4.85 Vp.p

11.8

fiN = 1 kHz, VIN = ±4.85V

78

fiN = 10 kHz, VIN = ±4.85V

78

fiN = 20.67 kHz, VIN = ± 4.85V

78

2-657

Bits

11.9

Bits(min)

11.1

Bits(min)

Bits

dB
dB

73.5

dB(min)

o......
N

~

U1
......

Converter Electrical Characteristics

(Continued)
The following specifications apply for Vcc = DVcc = AVcc = +5.0V, V- = -5.0V, VREF = +5.0V, using 5/H input for.
conversion control, and fCLK = 3.5 MHz unless otherwise specified. Boldface limits apply for. TA = T J = TMIN to TMAX; all
other limits TA = TJ = 25°C. (Notes 6, 7 and 8)
Symbol

Parameter

Conditions

Limit
Typical
(Note 9) (Note 10, 19)

Units
(Limit)

DYNAMIC CHARACTERISTICS (Continued)

SIN

Unipolar Signal to Noise Ratio (Note 17)

fiN
fiN

= 1 kHz, VIN = 4.85 Vp.p
= 10 kHz, VIN = 4.85 Vp•p

= 20.67 kHz, VIN = 4.85 Vp.p
fiN = 1 kHz, VIN = ± 4.85V
fiN = 20.67 kHz, VIN = ±4.85V
fiN = 1 kHz, VIN = 4.85 Vp.p
fiN = 20.67 kHz, VIN = 4.85 Vp.p
fiN = 1 kHz, VIN = ± 4.85V
fiN = 10 kHz, VIN = ±4.85V
fiN = 20 kHz, VIN = ±,:4.85V
fiN = 1 kHz, VIN = 4.85 Vp•p
fiN = 10 kHz. VIN = 4.85 Vp.p
fiN = 20 kHz, VIN = 4.85 Vp•p
VIN = ±4.85V, flN1 = 19.375 kHz,
flN2 = 20kHz
VIN = 4.85 Vp.p, flN1 = 19.375 kHz,
flN2 = 20 kHz
VIN = ± 4.85V, (Note 17)
VIN = 4.85 Vp•p, (Note 17)
fiN

THD

THD

Bipolar Total Harmonic Distortion (Note 17)

Unipolar Total Harmonic Distortion (Note 17)

Bipolar Peak Harmonic or Spurious Noise
(Note 17)

Unipolar Peak Harmonic or Spurious Noise
(Note 17)

Bipolar Two Tone Intermodulation Distortion
(Note 17)
Unipolar Two Tone Intermodulation Distortion
(Note 17)
-3 dB Bipolar Full Power Bandwidth
-3 dB Unipolar Full Power Bandwidth

73

dB
dB

73

68.7

73

dB(min)

-82

dB

-80

-78.0

. dB(max)

-73.1

dB(max)

-82

dB

-80
-88

dB

-84

dB

-80

dB

-90

dB

-86

dB

-82
-78

dB
dB'(max)

..

dB(max)

-78
25

20.67

kHz(min)

32

20.67

kHz(min)

Aperture Time

100

·ns·

Aperture Jitter

100

pSrms

I

2·658

~

C

Digital and DC Electrical Characteristics
The following specifications apply for DVcc = AVcc = +S.OV, V- = -S.OV, VREF = +S.OV, and fCLK = 3.S MHz unless
otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 2S'C. (Notes 6 and 7)
Symbol

Parameter

Condition

Typical
(Note 9)

Limit
(Note 10, 19)

Units
(Limit)

2.0

V(min)

0.8

V(max)

VIN(l)

logical "1" Input Voltage for
All Inputs except ClK IN

VCC = S.2SV

VIN(O)

logical "0" Input Voltage for
All Inputs except ClK IN

Vcc = 4.7SV

IIN(l)

logical "1" Input Current

VIN = SV

O.OOS

1

J.'A(max)

IIN(O)

logical "0" Input Current

VIN = OV

-O.OOS

-1

J.'A(max)

VT+

ClK IN Positive-Going
Threshold Voltage

2.8

2.7

V(min)

VT-

ClK IN Negative-Going
Threshold Voltage

2.1

2.3

V(max)

VH

ClK IN Hysteresis
IVT+(min) - VT-(max)l

0.7

0.4

V(min)

VOUT(l)

logical "1" Output Voltage

2.4
4.5

V(min)
V(min)

0.4

V(max)

Vcc = 4.7SV:
lOUT = - 360 J.'A
lOUT = -10 J.'A

VOUT(O)

logical "0" Output Voltage

Vcc = 4.7SV,
lOUT = 1.6mA

lOUT

TRI-STATE® Output leakage
Current

VOUT = OV

-0.Q1

-3

J.'A(max)

VOUT = SV

0.Q1

3

J.'A(max)

ISOURCE

Output Source Current

VOUT = OV

-20

-6.0

mA(min)

ISINK

Output Sink Current

VOUT = SV

20

8.0

mA(min)

Dlcc

DVcc Supply Current

CS = "1"

1

2.5

mA(max)

Alcc

AVcc Supply Current

CS = "1"

2.8

10

mA(max)

I-

V- Supply Current

CS = "1"

2.8

10

mA(max)

AC Electrical Characteristics·
The following specifications apply for DVCC = AVcc = +S.OV, V- = -S.OV, tr = tf = 20 ns unless otherwise specified.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 2S'C. (Notes 6 and 7)
Symbol
fCLK

Parameter

Conditions

Typical
(Note 9)

Clock Duty Cycle

tc

Units
(Umlt)

3.5

MHz
MHz(min)
MHz(max)

40
60

%
%(min)
% (max)

27(1/fCLK) + 250n5

(max)

Clock Frequency
O.S
6.0

tc

Limit
(Note 10, 19)

Conversion Time using WR
to start a Conversion

Conversion Time using StH
to start a Conversion

SO

27(1tfCLK)
fCLK = 3.S MHz, AZ = "1"

7.7

7.95

J.'s(max)

fCLK = 1.75 MHz, AZ = "0"

15.4

15.65

J.'s(max)

34(1tfcu

(max)

399

400

p.s(max)

60

200

ns(min)

60

200

ns(min)

50

95

ns(max)

30

70

ns(max)

100

175

ns(max)

30

60

ns(min)

ICA[

Calibration Time

tW(CAl)l

Calibration Pulse Width

tW(WR)l

minimum WR Pulse Width

tACC

maximum Access Time

fClK = 3.5 MHz
(Note 16)

Cl = 100pF

(Delay from Falling Edge of
RD to Output Data Valid)
tOH, tlH

TRI-STATE Control (Delay

Rl = 1 kO,

from Rising Edge of RD

Cl = 100pF

to Hi-Z State)
tpD(lND

maximum Delay from Falling Edge
of RD or WR to Reset of INT

tRR

Delay between Successive RD Pulses

Nole 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specilic performance limits. For guaranteed specifications and test condHions, see the Electrical Characteristics. The guaranteed
,speCifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Nole 2: All voltages are measured with respect to AGND and DGND, unless otherwise specified.
Nole 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V- or VIN > (AVcc or DVccl, the current at that pin should be limited to
5 rnA. The 20 rnA maximum package input current rating allows the voltage at any four pins, with an input current IimH of 5 rnA, to simultaneously exceed the power
supply voltages.
Nole 4: The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation + 1 TTL Load on each digital
output). Caution should be taken' not to exceed absolute maximum power rating when the device Is operating In a severe fault condition (ex. when any inputs or
outputs. exceed the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMax (maximum junction
temperature), 8JA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature
is PCMax ~ (TJMax - TA)/8JA or the number given In the Absolute Maximum Ratings, whichever Is lower. For this device, TJMax ~ 150"C, and the typical thermal
resistance (8JA) of the ADC12451 wHh CMJ, and CIJ suffixes when board mounted is 51·C/W.
Nole 5: Human body model, 100 pF discharged through a 1.5 kO resistor.
Nole 6: Two on-Chip diodes are tied to Ihe analog input as shown below. Errors in the AID conversion can occur if these diodes are forward biased more than
50 ·mV. This means that if AVec and DVec are minimum (4.75 Vccl and V- is maximum (-4.75 Vocl, the analog input full-scale voltage must be'; ±4.8 Vec.
DVcc

24

------

r-I

VIN

1

I
I
I
I
I

~~
~

~--

TO INTERNAL
CIRCUITRY

.
------

5
VTL/H/ll025-4

2-660

Electrical Characteristics (Continued)
Nate 7: A diode exists between AVec and DVcc as shown below.
I

I
I
A v e e : r : TO INTERNAL
I
CIRCUITRY

DVec 24

l

TO INTERNAL
CIRCUITRY

I
I

TLlH/II025-5
To guarantee accuracy, it Is required that the AVec and DVcc be connected togelher 10 a power supply with separate bypass filters at each Vec pin.
Nata 8: Accuracy is guaranteed atlCLK = 3.5 MHz. At higher or lower clack Irequencies accuracy may degrade, see the typical performance characterislic curves.

Nate 9: Typicals era at TJ = 25'C and represenl most likely parametric norm.
Nate to: Umils are guaranteed to National's AOQL (Average Outgoing Quality Level).
Nate 11: Posilivelinearity error is delined as the deviation 01 the analog value, expressed in LSBs, Irom Ihe slralght line that passes through positive lull scale and
zero. For negative linearity error the siralghiline passes through negativ~ lull scale and zero. (See Figures tb and te).
Nate 12: The ADC12451 's sell-calibrallon technique ensures linearity, lull scale, and ollset errors as specified, but noise Inherent in the self-calibration process will
result in a repeatability uncertainty 01 ± 0.20 LSB.
Nate 13: II TA changes then 'an Auto-Zero or Auto-Cal cycle will have to be re-started, see the typical performance characteristic curves.
Nale 14: Aller an Auto-Zero or Auto-Cal cycle at the specified power supply extremes.
Nate 15: When using the WFi control to start a conversion ilthe clack is asynchronous to the rising edge olWR an uncertainty 01 one clock period will exist in the
end 01 the Interval alIA, therelore making tA end a minimum 6 clock periods or a maximum 7 clock periods aller the riSing edge 01 WR. lIthe lalling edge 01 the
clock is synchronous to the rising edge olWR then tA will end exactly 6.5 clock periods allerthe rising edge olWl'!. This does not occur when S/H contrails used.
Nate 16: The c:lAC line must be high belore a conversion Is started.
Nata 17: The specifications lor these parameters era va!id aller an Auto-Cal cycle has been completed.
Nate 18: The ADC12451 relerence ladder is composed solely 01 capacitors.
Nale 19: A military RETS electrical test specijication Is available on request. At time 01 printing, the ADC12451 CMJ/883 RETS specification complies fully with the
boldface limits In this column.

(+4095)O,IIII,II11,IIII-f(+4094)0,1111,1111,1110 - I ",

"",

"

~SITIVE
FULL-SCALE
TRANSmON

"

,"

~O-

(2) 0,0000,0000,0010
(1) 0,0000,0000,0001
(0) 0,0000,0000,0000

-VREF

r--','

-

_-,,...!.-.JpoooooJ!::::===
-~Z~ER~O....!.TR~A~NS~m~O~N_ _ _ _ _ _-I1
I INPUT VOLTAGE
-1,1111,1111,1111(-1)
- 1,1111,1111,1110(-2)

- - -

+VREF

1,0000,0000,0001 (-4095)
1,0000,0000,0000 (-4096)

ANALOG INPUT VO~TAGE (VIN)
TL/H/II025-6

FIGURE la. Transfer CharacterIstIc

2-661

•

.- r-------------------------------------------------------------------------------------,
~

C'\I
.-

Electrical Characteristics (Continued)

~

+12LSB
+8 lSB

,
_~

"

Positive
full-Scale
Error

_____________ i
INPUT VOLTAGE

+4095

-8lSB
-12LSB
OUTPUT CODE
(from -4096 to +4095)

,TUH/ll025-7

FIGURE 1b. Simplified Error Curve vs Output Code without Auto-Cal or Auto·Zero Cycles
'+3lSB

NEGAllVE
fUll-SCALE
ERROR

POSITIVE

+2lSB
ZERO
ERROR

+1 LSB

=--.:.-.:~_ilc.=-'-'-'"'-::.;-=i=__=_=lr=.;...,..r_;Fi"_1'=c='-Jiioi.....=.:c.='_=_t'-""'F_=f_ INPUT VOLTAGE

=r=-l

-1 lSB
NEGAllVE INPUT RANGE

-2LSB

POSITIVE INPUT RANGE

-3LSB
OUTPUT CODE
(from -4096 to +4095)
TL/H/ll025-8

FIGURE 1c. Simplified Error Curve vs Output Code after Auto-Cal Cycle

Typical Performance Characteristics
Zero Error Change vs
Ambient Temperature
U

2

Zero Error vs VREF

1.4

'§'

r-. ........

-2

...- ...- 10-'"

AVec = DVec = +S.OY
Y-=-S.DV
fOU( =UWHz
VR£F=+S.DV
No_lion
No Auto-ZInI

-55 -35-15 5 25 45 65 85 105125

AW9ENT 1EIfPfRATURE (OC)

12

.!!. 1.0

I
~

0.8
0.8
Q.4

\

AVec = OYec=+5.OY
V-=-S.DV
faJ( =3.5 MHz
TA =+25OC

1\
\

12

'§'

.t!.

1.0

~.

\

AVec=OYec=+S,OY
V-=-5.OV
faJ( =3.5 MHz
TA =+25OC

\

\
\.

"- ........ i - -

02

o
o

Linearity Error vs VREF
1.4

2

'3

o
o

VR£F (V)
TUH/ll025-9

2·662

Typical Performance Characteristics
Linearity Error vs
Clock Frequency
M~~~~~-r--r-,

§"

AVec=DVec=+S,DV
0.7 V-=-S.OV -1--+-+--1
VREF ' 'S.OV -1--+-+--1
TA =.2SOC

D.6

~ 0.51--+-+--I-+-t--J

a O.4I--+-+--1-+~ofV'-l
V

I:

1--+-+--1-+-+--1

rul-+--~-+--+--+--4

»
c

(Continued)

Full Scale Error Change vs
Ambient Temperature
lD,-r;r;-,-,-,-,-,-,

! os~
;

0

I

~~Il:PV

e;
I--"I<~ Fua Sca~ ~
~
AVcc=DYcc=+5'ov
~
li -o.s Y- = -S.QY

~

.

I

;;t

1

I

1-

-40 flN =25kHz
TA=2SOC

_

fCLJ(= 3.S MHz

::ac::.-:n

. _

o Sampling Frequency = 83 kHz

o

100

200

300

400

500

600

INPUT SOURCE IMPEDANCE (II)

AMBIENT TEMPERATURE (OC)

Bipolar Signal-toNoise+ Distortion Ratio vs
Input Frequency

'VIN =t2.5V

20 ~c;~:'~=VREF=+S,OV

-1Jl NoAIItoo-Zlru
-55 -35 -15 S 2S l5 65 85 lOS 125

a.OCK F1IEQUENCY (MHz)

I

I I

In'60
~

fax '3.5.~1

'"

0.0'---'---'----''----'---'----'
02.040
6.0

eo

Bipolar Signal-to.Noise + Distortion Ratio vs
Input Source Impedance

Unipolar Signal-toNoise + Distortion Ratio vs
Input Frequency

Unipolar Signal-toNoise + Distortion Ratio VB
Input Signal Level
eo~~~--r-----~~

90

eo
70

'"'
vlN=tsv

t=tm:+m::ttttttm

70~hlil

N..'~~'=t2.5V

60 Rs=60011

60 TA=2SOC

so

TA=25OC

DVec = AVec = vREF = .s.ov
V""=-S.OV

fcu<=3.5MHz
40 Sampling fnoquoncy = 83 kHz

1.0

10

so
.co

Sampling Frequency 83 kHz

100

!
0'
l
::::::

..

'r!
-ho£f-+I
C;~HzI
X
I
V f =20kHz

Sa_ . . -,

,-

,V

O~~~~~~~~~

,N

=UkHz

V.. =:l:5V
r"a25OC

"iii" -20
~

H-_+__ AVCC=DYCC=V~:~=

!;l -40 H--+--

9

fcu:=UIiIHz

_ .........'"
./(1<+.)=,.... "

S : H--+--+---I----H

-40 -30 -20 -10

0

INPUT SIGNAL LEVU (dB)

Bipolar Spectral Response
with 10 kHz Sine Wave Input

...----,----r1---::-,,:-:'504=

ofr---t--

-so

-70 -60

100

Bipolar Spectral Response
with 1 kHz Sine Wave Input
20

Y I

I

........ '..._, /f'N = 20kHz
=.. ""
..,

INPUT F1IEQUENCY (kHz)

TA
I
I
60 AYcc =GYcc =VREr =+5JIY

40

40

20 1---l-7Itf-/-+-+--J-1---l

10

lD

fIN = 1 kHz ~

=,...,

~

=

Bipolar Signal-toNoise + Distortion Ratio vs
Input Signal Level
V,,=I5.OY

~~'"

~

fCLJ(=3.SMHz

INPUT fREQUENCY (kHz)

eo ........

"""-vIN =2.SVp-p

AVec = DVec=VREF = +S.OV
V"" =-S.DV

flN =1kHz ........

TAO"'"
. II
""60 AYcc=DVcc=V_=+5.OV -hol'l-+-t

VIN,~~'OVp-p

t=t"",*"",III"*,,,
1Il-lor--~J+I.I.jj
RS = 60011

~:=p-p

....-r-rrrT11"""-11111.,.....",..".

90
eo~+-~~~~++~~

20

I

......
Y.. =:I:5V

0

' .. =25'C

S- -20 1-_+__ AYa;=DYc:c=V~::=
~
fax=U.'"

§ -40 1--+-;I

~

Slmplng RaIe=l5kHz

S/(H+D) R 75.IIdB

-60
-60
-100

-120
0.0

O~~~--~~~--~

-70 -60

-so

-40 -30 -20 -10

_ _.L-_...u
20D
30D
40D
F1IEQUENCY (kHz)

~_..J...._--'-

0

INPUT SIGNAL LEVEL (dB)

Bipolar Spectral Response
with 20 kHz Sine Wave Input
2O'---r---r---~..~=~
...
~
-%0 1-_+_-fAYa:IIIW=.V~::

~

~

9

o

T,,=25OC

i

fCUC=5.5UHz
Sl.mptltll.tt=Uktb;

./(...)="......

I : 1--1+---4f--,-+--+l
aiiIil~~I~iliIiijiitl.i~

-100
-120 '--__-'-__--'-_~_........u
0.0
10.0
2M
3D.O
010.0
fREQUENCY (kHz)

'iii"

~

~

---+----+1

V.=5Yp-p

_ _U
3D.O
010.0

~_..L.._--'-_.....J.

10.0

H--+--

fCUC=3.5YHz
~Rate.831db:

;;I

H--.-+--+--h--+/

20D

F1IEQUENCY (kHz)

',,=25C'C

AVcc=OVcc·V':!:::

i!j

-111O~~.~
I~~~

40D

S- -20 H-_+__

~

==":.;:k'"

-120
0.0

30D

0

'..,=25CC

C=i~YHz

j :

2D.O

Unipolar Spectral Response
with 1 kHz Sine Wave Input
20
,,,=504

YIN=:lSV

-2D AVcc=DVcc=VRl7=+SV

-40

10.0

F1IEQUENCY (kHz)

Bipolar Spectral Response
with 40 kHz Sine Wave Input
20 r:..-=-::504:-r---:-r-----;-----n

VtI =:I:5V

01---+----1-

-120
0.0

10.0

~

-40

S/CN+')='2.33"

-60
-60
-100
-120
0.0

d ...l

10.0

2D.O

30D

40D

fREQUENCY (kHz)

TL/H/ll02S-10

2-663

o
....
N
.co.
....
UI

.~
.-

r-------------------------------------------------------------------------------------~

Typical Performance Characteristics

~

Unipolar Spectral Response
. with 10 kHz Sine Wave Input

.......

20

AYfiC -

~-2D

-100
-120
lID

.......

wcc·

yo.-

IIID

2DD

3QO

'A-zsac
yo .....

V-.-Sy

w- UIINI

fwc- uWHz
S....... Rdt.UIdfz
Sj(JItD)-71.24d1

.11

-100
-120
lID

«10

I

I

~3

IIID

FREQUDICY (kHz)

2DD

~".UIdII

S/III+Dl.1IWdI

L

3QO

.......

AVcc·twcc·y.,.:·sv

A'lcc·Il¥c:c-.··sv

.-

Unipolar Spectral Response
with 40 kHz Slile Wave Input
'fIfDSY,..,

',czst'C

""'........

..

I.

20

v.. _sv,.,

'._2PC
V
of5Y

........... Uldfr
S/(lI+D).72.Ot.

-«I

I:

Unipolar Spectral Response
with 20 kHz Sine Wave Input

V• .SY,..,

.0

~

20

(Continued)

-100
-120
lID

«10

FREQUENCY (kHz)

I

I
IIID

2DD

3QO

"

«10

FREQUENCY (kHz)

TLlH/11025-ll

Test Circuits

iiii

DATA
OUTPUT

ADC12451

-.

I~

RL
TL/H111025-13
TL/H111025-12

Vee

Vee

iiii
RL

iiii

-

VIN(O)
DATA
OUTPUT

ADC12451

VIN (I)

DATA Vee
OUTPUT: VOL _ _ _.I

I~

TLlHI11025-15
TLlH/11025-14

FIGURE 2. TRI-8TATE Test Circuits and Waveforms

2-884

l>
C

Timing Diagrams

o
.....
N

"'"
.....

UI

Auto-Cal Cycle
CLOCK

1

ill
-

'w(CAL)L

I--

cs~
1------------

'ill
Auto-Cal Cycle
'" 1399 clocks

}

I S ·
--------------------~S----------~

,.....-----------

.
\ ......

roc

iii~
CS =1
\Wi;; x

iffi =x
Ai = x
S/H = 1
X = Don't Cara
TL/H/ll025-16

Using WR Control to Start a Conversion with Auto-Zero (CAL
CLOCK

=

1, AZ

= 0)

L..rrSl..JU~JLf1.1
S1

\

SS

IS

IS

IS

to.

~

H

RD,

IS
roc

Aut~Z.ro'" 26 clocks

-+--

AcquIsition _ _J'---!S----..J
... 7 clocks

~

~
Conversion

______________________ ~ ':,~::~ ______________ ~::O~k~ __ ~_: __ -0-1 - - - - - - .wto-Zero end Acquisition

DBO/D98-DB7/O"2

HIgh Byte
Oa8-D812

Low Byte

DSO-0B7

TLlH111025-17

2-665

...
...~

Timing Diagrams (Continued)

~

Using WR Control to Start a Conversion without Auto-Zero (~ 1, AZ = 1)

~

I

I

I

@

~ 1--.".....

I--

r-- Internal
- 7 '.clocks
0.18)'

....I

~~

-

-'D(EOC)L

I

'.

Acquisition

'Pd!iiii)I

Ie
.....-

-27......

DSOIM'-DB1 IM12

r-

I

k
EOC

IA

\

C

J- --..f
'... -

==:>-----------------~r-----!~~~------~r---------------

b
HIgh S,t.
DBl-DB12

--------~
low B)'te
.....DD7

TL/H/ll025-18

Using 5tH Control to Start a Conversion without Auto-Zero (AZ = 1, CAL = 1)

Cs~'--________~!________
H

~

i/H

JI
.

,------11----'1
~I__---tAo Acquisition

----.j

I

~ ..~oc~

,.c

::
DBO/DBS-DB7/DBI2 - - - - - - - - - - - - - - - -

-';5- -- -- --_ ..

t

. ,::n., ----.j--r-~------+--

.. 34 clockl

TRI-STATE - - - -

lACe

I'::....-..

-------04r-----------L.)---H1l1hBIl'
DBI-DI12

low Byt.
D80-D1I7

TL/H/ll025-19

2-666

-----»
1.0 Pin Descriptions
DVee (24),
AVec (4)

V- (5)

The digital and analog positive power supply
pins. The digital and analog power supply
voltage range of the ADC12451 is +4.5V to
+5.5V. To guarantee accuracy, it is required
that the AVec and DVee be connected together to the same power supply with separate bypass capacitors (10 p.F tantalum in
parallel with a 0.1 p.F ceramic) at each Vee
pin.
, The analog negative supply voltage pin. Vhas a range of -4.5V to -5.5V and needs
bypass capacitors of 10 p.F tantalum in parallel with a 0.1 p.F ceramic.

DGND (12),
AGND (3)

The digital and analog ground pins. AGND
and DGND must be connected together externally to guarantee accuracy.

VREF(2)

The reference input voltage pin. To maintain
accuracy the voltage at this pin should not
exceed the AVec or DVee by more than
50 mV or go below +3.5 Voe.

The Chip Select control input. This input ill
active low and enables the WA, AD and S/H
functions.

AD (23)

The Aead control input. With both CS and RD
low the TAl-STATE output buffers are enabled and the INT output is reset high.

WA(7)

The Write control input. The conversion is
started on the rising edge of the WA pulse
when CS is low. When this control line is
used the end of the analog input voltage acquisition window is internally controlled by the
ADC12451.

S/H (11)

The sample and hold control input. This control input can also be used to start a conversion. With CS low the falling edge of S/H
starts the analog input acquisition window.
The rising edge of 5/H ends the acquisition
window and starts a conversion.

CLKIN (8)

The external clock input pin. The typical clock
frequency range is 500 kHz to 6.0 MHz.

CAL (9)

The Auto-Calibration control input. When
CAL is low the ADC12451 is reset and a calibration cycle is initiated. During the calibration cycle the values of the comparator offset
voltage and the mismatch errors in the capacitor reference ladder are determined and
stored in RAM. These values are used to correct the errors during a normal cycle of AID
conversion.

7iiZ (6)

The Auto-Zero control input. With the AZ pin
held low during a conversion, the ADC12451
goes Into an auto-zero cycle before the actual AID conversion is started. This Auto-Zero
cycle corrects for the comparator offset voltage. The total conversion time (te) is increased by 26 clock periods when Auto-Zero
is used.

EOC(22)

The End-of-Conversion control output. This
output is low during a conversion or a calibration cycle.

INT(21)

The Interrupt control output. This output goes
low when a conversion has been completed
and indicates that the conversion result is
available in the output latches. Reading the result or starting a conversion or calibration cycle will reset this output high.

DBO/DBB-

The TRI-STATE output pins. Twelve bit pius
sign output data access is accomplished using
two successive RDs of one byte each. high
byte first (DBB-DB12). The data format used
is two's complement sign bit extended with
DB12 the sign bit, DB11 the MSB Rnd DBO the
LSB.

DB7/DB12
(13-20)

N

2.0 Functional Description
The ADC12451 is a 12-bit plus sign AID converter with the
capability of dOing Auto-Zero or Auto-Calibration routines to
minimize zero, full-scale and linearity errors. It is a succe!'sive-approximation AID converter consisting of a DAC.
comparator and a successive-approximation register (SAR)
Auto-Zero is an internal calibration sequence that corrects
for the AID's zero error caused by the comparator's offset
voltage. Auto-Cal is a calibratio!! cycle that not only corrects
zero error but also corrects for full-scale and linearity errors
caused by DAC inaccuracies. Auto-Cal minimizes the errors
of the ADC12451 without the need of trimming during its
fabrication. An Auto-Cal cycle' can restore the accuracy of
the ADC12451 at any time, which ensures accuracy over
temperature and time.

The analog input voltage pin. To guarantee
accuracy the voltage at this pin should not
exceed Vee by more than 50 mV or go below
V- by more than 50 mV.
CS (10)

....,..c
en
...

(")

2.1 DIGITAL INTERFACE
On power up, a calibration sequence should be initiated by
pulsing CAL low with CS and 5/H high. To acknowledge the
CAL signal, EOC goes low after the falling edge of CAL, and
remains low during the calibration cycle of 1399 clock periods. During the calibration sequence, first the comparator's
offset is determined, then the capacitive DAC's mismatch
error is found. Correction factors for these errors are then
stored in internal RAM.
A conversion is initiated by taking CS and WR low. If AZ is
Iowan Auto-Zero cycle, which takes approximately 26 clock
periods, is inserted before the analog input is sampled and
the actual conversion is started. AZ must remain low during
the complete conversion sequence. After Auto-Zero the acquisition opens and the analog input is sampled for appproximately 7 clock periods. If AZ is high, the Auto-Zero cycle is
not inserted after the rising edge of WR. In thi~ Gase the
acquisition window opens when the ADC12451 completes a
conversion, signaled by the rising edge of EOC At the end
of the acquisition window EOC goes low. signaling that the
analog input is no longer being sampled an.d that the AID
successive approximation conversion hl''1 !';tarted

2·867

PI

....
c:s
....
o
&I)

c

cC

2.0 Functional Description (Continued)
A conversion sequence can also be controlled by the 5/H
and CS inputs. Taking CS and 5/H low starts the acquisition
window for the analog input voltage. The rising edge of 5/H
immediately puts the AID in the hold mode and starts the
conversion. Using 5/H will simplify synchronizing the end of
the acquisition window to other signals, which may be necessary in a DSP environment.

the operation of the ADC12451. Care should be taken not to
inadvertently be in this mode, since DB2, DB3, DB5, and
DB6 become active outputs, which may cause data bus
contention.
2.2 RESETTING THE AID
The ADC12451 is reset whenever a new conversion is started by taking CS and WR or 5/H low. If this is done when the
analog input is being sampled or when EOC is low, the
Auto-Cal correction factors may be corrupted, therefore requiring an Auto-Cill cycle before the next conversion. When
using WR or 5/H without Auto-Zero (AZ = 1) to start a
conversion, a new conversion can be restarted only after
EOC has gone high signaling the end of the current conversion. When using WR with Auto-Zero (AZ = 0) a new conversion can be restarted during the first 26 clock periods
after the rising edge of WR (tz) or after EOC has returned
high without corrupting the Auto-Cal correction factors.
The Calibration Cycle cannot be reset once started. On
power-up the ADC12451 automatically goes through a Calibration Cycle that takes typically 1399 clock cycles. For reasons that will be discussed in Section 3.8, a new calibration
cycle needs to be started after the completion of the automatic one.

During a conversion, the sampled input voltage is successively compared to the output of the DAC. First, the acquired input voltage is compared to analog ground to determine its polarity. The sign bit is set low for positive input
voltages and high for negative. Next the MSB of the DAC is
set high with the rest of the bits low. If the input voltage is
greater than the output of the DAC, then the MSB is left
high; otherwise it is set low. The next bit is set high, making
the output of the DAC three quarters or one quarter of full
scale. A comparison is done and if the input is greater than
the new DAC value this bit remains high; if the input is less
than the new DAC value the bit is set low. This process
continues until each bit has been tested. The result is then
stored in the output latch of the ADC12451. Next INT goes
low, and EOC goes high to signal the end of the conversion.
The result can now be read by taking CS and RD low to
enable the DBO/DB8-DB7/DB12 output buffers. The high
byte of data is relayed first on the data bus outputs as
shown below:

I

DBOI DB1/1 DB2/1 DB3/1 DB41
DBB DB9 I DB10 I DBll DB12

DBSI
DB12

I

DB61
DB12

I

DB7I
DB12

I

I Bit 8 I Bit 9 I Bit 10 I MSB I Sian Bit I Sian Bit I Sian Bit I Sian Bit I
Taking CS and RD Iowa second time will relay the low byte
of data on the data bus outputs as shown below:

I I I I I I

DB51
DB12

DB61
DB12

DB71
DB12

I

BitS

BitS

Bit7

DBOI
DBB
LSB

DB11
DB9

I

Bitl

DB21
DB10

I

Bit2

DB31
DBll

I

Bit3

DB41
DB12

I

Bit4

I

I
I

The table in Figure :3 summarizes the effect of the digital
control inputs on the function of the ADC12451. The Test
Mode, where RD and 5/H are high and CS and GAL are
low, is used during manufacture to thoroughly check out

Digital Control Inputs

AID Function

SIH

RD

CAL

AZ

IS

1

1
1

.lJ"

1
1

lJ"

1
1
1
1
1

1
1
1
0
0

X
X

CS

WR

lJ"
lJ"
lJ"
lJ"
lJ"
1
0

X
X

IS
1

1
1
1
1

lJ"

X

lJ"

X

1

0

1

3.0 Analog Considerations
3.1 REFERENCE VOLTAGE
The voltage applied to the reference input of the converter
defines the voltage span of the analog input (the difference
between VIN and AGND), over which 4095 positive output
codes and 4096 negative output codes exist. The A-to-D
can be used in either ratiometric or absolute reference applications. The voltage source driving VREF must have a
very low output impedance and very low noise. The circuit in
Figure 4a is an example of a very stable reference that is
appropriate for use with the ADC12451. The simple reference circuit of Figure 4b may be used when the application
does not require a low full-scale error.

Start Conversion without·Auto-Zero
Start Conversion synchronous with rising edge of 5/H without Auto-Zero
Read Conversion Result without Auto-Zero
Start Conversion with Auto-Zero
Read Conversion Result with Auto-Zero
Start Calibration Cycle
Test Mode (DB2, DB3, DB5, and DB6 become active)

FIGURE 3 •.Functlon of the AID Control Inputs

2-668

3.0 Analog Considerations (Continued)
VIN

= +12Y to +15Y

to AOCl2451

vREF+ =+5V

To ADe12.51 Vee = +5V

+I2V 10 +ISV ...._ _ _--.

~}

9 :0 ADCI2451

-t:

GND

TL/H/11025-21

Errors without any trims:
25·C
. - 40·C to + 85·C
Full Scale
±O.075%
±O.2%
Zero
±O.024%
±O.024%
Linearity
± Yz LSB
± Yz LSB
FIGURE 4b. Simple Reference Circuit

• Tantalum

.. Ceramic

TL/H/II025-20

FIGURE 4a. l.ow Drift Extremely Stable Reference Circuit

this method the acquisition window is internally controlled
by the ADC12451 and lasts for approximately 7 clock periods. Since. the acquisition window needs to be at least
3.5 ,...S at all times, when using Auto-Zero the maximum
clock frequency is limited to 2 MHz. The zero error with the
Auto-Zero cycle is production tested at a clock frequency of
1.75 MHz. This accommodates easy switching between a
conversion with the Auto-Zero cycle (fCLK = 1.75 MHz) and
without (fCLK = 3.5 MHz) as shown in Figure 5.

In a ratiometric system, the analog input voltage is proportional to the voltage used for the AID reference. When this
voltage is the system power supply, the VREF pin can be
tied to Vce. This technique relaxes the stability requirement
of the system reference as the analog input and AID reference move together malntaining the same output code for a
given input condition.
For absolute accuracy, where the analog input varies between very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
In general, the magnitude of the reference voltage will require an initial adjustment to null out full-scale errors.
3_2 ACQUISITION WINDOW
As shown in the timing diagrams there are three different
methods of starting a conversion, each of which affects the
acquisition window and timing.
With Auto-Zero high a conversion can be started with the
WR or S/H controls. In either method of starting a conversion the riSing edge of EOC signals the actual beginning of
the acquisition window. At this time a voltage spike may be
noticed on the analog Input of the ADC12451 whose amplitude is dependent on the input voltage and the source resistance. The timing· diagrams for these two methods of
starting a conversion do not show the acquisition window
starting at this time because the acquisition time (tA> must
start after the conversion result high and low bytes have
been read. This is necessary since activating and deactivating the digital outputs (DBO/DB7-DB8/DB12) causes current fluctuations in the ADC12451 's internal DVcc lines.
This generates digital noise which couples into the capacitive ladder that stores the analog input voltage. Therefore,
the time interval between the rising edge of EOC and the
second read is inappropriate for analog input voltage acquisition.
When Wft is used to start a conversion with 7ii'l low the .
Auto-Zero cycle is inserted before the acquisition window. In

2-669

J1.IU1 }----.-ob
3.5WH.

TL/H/11025-22

FIGURE 5_ Switching between II Conversion with and
without Auto-Zero when Using WR Control
3.3 INPUT CURRENT
Because the input network of the ADC12451 is made up of
a switch and a network of capacitors a charging current will
flow into or out of (depending on the input voltage polarity)
of the analog input pin (VIN) on the start of the analog input
sampling period. The peak value of this current will depend
on the actual input voltage applied and the source resistance.
3.4 NOISE
The leads to the analog input pin should be kept as short as
possible to minimize input noise coupling. Both noise and
undesired digital clock coupling to this input can cause errors. Input filtering can be used to reduce the effects of
these noise sources.

fII

~ r-----~------------~--------------------------------------------------------------------~

an
~

3.0 Analog Considerations (Continued)

g

3.5 INPUT BYPASS CAPACITORS

~

c

change. Since Auto·Zero cannot be activated with 5/H con·
version method it .may be necessary to do a calibration cy·
cle more than once.

An external capacitor can be used to filter out any noise due
to inductive pickup by a long input lead and will not degrade
the accuracy of the conversion result.

3.9 THE AUTO·ZERO CYCLE
To correct for any ch,ange in th~ zero (offset) error of the
AID, the auto·zero cycle can be used. It may be necessary
to do an auto·zero cycle whenever the ambient temperature
changes significantly. (See the curve titled "Zero' Error
Change vs Ambient Temperature" in the Typical Perform·
ance Characteristics.) A change in the ambient temperature
will cause the Vos of the sampled data comparator to
change, which may cause the zero error of the AID to be
greater than ± 1 LsB. An auto·zero cycle will typically main·
tain the zero err.o~ to, ± 1 LsB or less.

3.6 INPUT SOURCE RESISTANCE
The analog input can be modeled as shown in Figure 6.
External Rs will lengthen the time period necessary for the
voltage on CREF to settle to within Yz LsB of the analog
input voltage. With tA = 3.5 /Ls, Rs ,;; 1 kG will allow a 5V
analog, input voltage to settle properly.
3.7 POWER SUPPLIES
Noise spikes on the Vee and V- supply lines can cause
conversion errors as the comparator will respond to this
noise. The AID is especially sensitive during the Auto·Zero
or ·Cal procedures to any power supply spikes. Low induc·
tancetantalum capacitors of 10 /LF or greater paralleled
with 0.1 /LF ceramic capacitors are recommended for supply
bypassing. Separate bypass capacitors should be placed
close to the DVee, AVec and V- pins. If an unregulated
voltage source is available in the system, a separate
LM340LAZ·5.0 voltage regulator for tlie A·to·D's Vee (and
other analog circuitry) will greatly reduce digital noise on the
supply line.

4.0 Dynamic, Performance
Many applications 'require ·the AID converter to digitize ac
signals, but the standard dc integral and differential nonlin·
earity specifications will not accurately' predict the AID con·
verter's performance with a6 input signals. The important
specifications for ac applications reflect the converter's abil~
ity to digitize ac Signals without significant spectral errors
and without adding noise to the digitized signal. Dynamic
characteristics such as signal·to·noise (SIN), signal·to·
noise+distortion ratio (s/(N+D», effective bits, full power
bandwidth, aperture time and aperture jitter are quantitative
measures of the AID converter's capability.

3.8 THE CALIBRATION CYCLE
On power up the ADC12451 goes through an Auto·Cal cy·
cle which cannot be interrupted. Since the power supply,
reference, and clock will not be stable at power up, this first
calibration cycle will not result in an accurate calibration of
the AID. A new calibration cycle needs to be started after
the power supplies, reference, and clock have been given
enough time to stabilize. During the calibration cycle, cor·
rection values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog·to·digital conversion to bring the overall full·scale,
offset, and linearity errors down to the specified limits. Full·
scale error typically changes ± 0.2 LsB over temperature
and linearity error changes even less; therefore it should be
necessary to go through the calibration cycle only once af·
ter power up if Auto·Zero is used to correct the. zero error

An AID converter's ac perform.ance can be measured. using
Fast Fourier Transform (FFT) methods. A sinusoidal wave·
form is applied
the. ~/D converter's input, and tlie trans·
form is then performed on the digitized waveform; s/(N + D)
and SIN are calcu.lated from the resulting FFT data, and Ii
spectral plot may also be obtained. Typical values for SIN
are shown In the table of Electrical Characteristics, and
spectral plots of s/(N+ D) are included in the typical per·
formance' curves. ..

to

The AID converter;s noise and distortion levei~ will 'change
with the, frequency oltha input Signal, with more distortion
and noise occurring at higher signal frequencies. This can
be seen in the s/(N+D) versus frequency curves. 'These
curves will also give an indication of the full power band·
width (the frequency'at whic~ the s/(N+D) or SIN drops
3 dB).

RIMT

VIN

_o--J\Jyvv-...-:l....:l+-~.Yv-.......
:l-l
Co'![

-.

I Cs

IC

REr

TL/H/ll025-23

FIGURE 6. Analog Input Equivalent Circuit

2·670

l>

4.0 Dynamic Performance (Continued)
Effective number of bits can also be useful in describing the
AID's noise performance. An ideal AID converter will have
some amount of quantization noise, determined by its resolution, which will yield an optimum SIN ratio given by the
following equation:
SIN = (6.02 x n + t.8) dB

Two samplelhold specifications, aperture time and aperture
jitter, are included in the Dynamic Characteristics table
since the ADC12451 has the ability to track and hold the
analog input voltage. Aperture time is the delaY,for the AID
to respond to the hold command. In the case of the
ADC12451, the hold command is internally generated.
When the Auto-Zero function is not being used, the hold
command occurs at the end of the acquisition window, or
seven clock periods after the rising edge of the WR. The
delay between the internally generated hold command and
the time that the ADC12451 actually holds the input signal is
the aperture time. For the ADC12451. this time is typically
100 ns. Aperture jitter is the change in the aperture time
from sample to sample. Aperture jitter is useful in determining the maximum slew rate of the input signal for a given
accuracy. For example, an ADC12451 with 100 ps of aperture jitter operating with a 5V reference can have an effective gain variation of about 1 LSB with an input signal whose
slew rate is 12 VI p.s.

where Ii is the AID's resolution in bits.
The effective bits of a real AID converter, therefore, can be
found by:
n(effective) = S/N(dB)-1.8
6.02
As an example, an ADC12451 with a ±5V, 10 kHz sine
wave input Signal will typically have a SIN of 78 dB, which is
equivalent to 12.6 effective bits.

5.0 Typical Applications
Power Supply Bypassing

.-----1 VIN

r---==~::::=o'" VREF

DVcc I-~===---...

AVec

I-~===---'

ADC12451

l

--;::::!:!~!J! AGND

~.1 J.lF~10J.lF~

.----~DGND

• Tantalum
•• Ceramic

TLlH/l1025-24

Protecting the Analog Inputs
+5V

TL/H/ll025-25

Note: External protection diodes should be able to withstand the op amp current limit.

2-671

g
....
.roo
....
N

CI1

:

~ r-------------------------------------------------------------------------------~

~

~

tilIV,a t ion a I Semiconductor

......
~

.....
C)

CD
~

8cc

ADC160711 ADC16471
16-Bit Delta-Sigma 192 ksl s Analog-to-Digital Converters
General Description

Key Specifications

16 bits
The ADC160711ADC16471 are 16-bit delta-sigma analog• Resolution
to-digital converters using 64 x oversampling at
• Total harmonic distortion
-94 dB (typ)
12.288 MHz. A 5th-order comb filter and a 246 tap FIR deci48 kHz output data rate
-80 dB (typ)
mation filter are used to achieve an output data rate of up to ,
192 kHz output data rate
192 kHz. The combination of oversampling and internal digi192 kHz (min)
• Maximum output data rate
tal filtering greatly reduces the external anti-alias filter re• Power dissipation
quirements to a simple RC low pass filter. The FIR filters
-Active
offer linear phase response, 0.005 dB passband ripple, and
500 mW (max)
192 kHz output data rate
~90 dB stopband rejection. The ADC16071/ADC16471's
275 mW (max)
48 kHz output data rate
analog fourth-order modulator uses switched capacitor
6.5 mW (max)
- Power-down
technology. A built-in fully-differential bandgap voltage reference is also included in the ADC16471. The ADC16071
Key Features
has no .internal reference and requires externally applied
• Voltage reference (ADC16471 only)
reference voltages.
• Fourth-order modulator
The ADC16071/ADC16471 use an advanced BiCMOS pro• 64 x oversampling with a 12.288 MHz sample rate
cess for a low power consumption of 500 mW (max) while
• Adjustable output data rate from 7 kHz to 192 kHz
operating from a single 5V supply. A power-down mode re• Unear-phase digital anti-aliasing filter:
duces the power supply current from 100 mA (max) in the
- 0.005 dB passband ripple
active mode to 1.3 rnA (max).
- 90 dB stopband rejection
The ADC16071/ADC16471 are ideal analog-to-digital front
• Single + 5V supply
ends for signal processing applications. They provide a
• Power-down mode
complete high resolution signal acquisition system that re• Serial data interface compatible with popular
quires a minimal external anti-aliasing filter, reference, or
DSP devices
interface logic.
The ADC16071/ADC16471's serial interface is compatible
with the DSP56001, TMS320, and ADSP2100 digital signal
processors.

Connection Diagram
VREr+-

,.

\....../

VREr- - 2
VMlo -

24 -VIN +
23 -VIN _

AGNO- 4

21 ~V:

MGNO- 5

20 ~VN

OGNO- 6
OGNO- 7
SFMT- 8

ADC18071
ADC16471

Medical instrumentation
Process control systems
Test equipment
High sample-rate audio
Digital Signal Pr.ocessing (DSP) analog front-end
Vibration and noise analysis .

Ordering Information

22 ~PD

3

Applications
•
•
•
•
•
•

Part No.

Package

NSPackage
No.

ADC16471CIN
ADC16471CIWM
ADC16071 CIN
ADC16071CIWM

24-Pin Molded DIP
24-Pin SOIC
24-Pin Molded DIP
24-Pin sale

N24C
M24B
N24C
M24B

19 ~Vo+
18 r-Vo+
17 r-TSI

TIIO- 9

16 r-OOE

TM1- 10

15 r-FSO

rSI- 11

14 -SOD

.ClK- 12

13 -SCD
TLlH/11454-2

2-672 '

>-

C

Block Diagram

....
en

(")

o
....,

ADC16471

VA

vJ

vo'

vo'

AGNO

MGNO

OGNO

....
.....

OGNO

00000000

>-

C

....
....

(")

en
~

DIFFERENTIAL

"'--+-_-1 ~~~f~~~
REFERENCE

OOE

COMB
FILTER

FIR
FILTER

TIMING AND CONTROL lOGIC

SOO

FSI
ClK

fSO
TSI

SFMT

mo

mI

Po

SCO
TLlH/11454-1

ADC16071

VA

vJ

Vo

Vo

AGND

MGND

DGND

DGND

00000000

II
DOE

COMB
FilTER

FIR
filTER

TIMING AND CONTROL lOGIC

rSI
elK

SERIAL
INTERFACE

SOO

fSO

srWT

TNO

TN 1

Po

SCO
TLlH111454-22

2-673

Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors lor availability and specifications.

ESD Susceptibility (Note 5)
Human Body Model
Machine Model

Supply Voltage (VA +, Vo+, and VM+)

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

+6.5V

-0.3VtoVo+ + 0.3V

Logic Control Inputs
Voltage at Other
Inputs and Outputs

-0.3VtoVA+

=

VM+ + 0.3V

Input Current at Any Pin (Note 3)

150·C
- 65·C to + 150"C

Lead Temperature
N Package (Soldering, 10 sec.)
WM Package (Infrared, 15 sec.)
WMPackage (Vapor Phase, 60 sec.)

Ratings (Notes 1 and 2)

Temperature Range
(Tmin S; T A S; T max>
-40·C
ADC16471 CIN, ADC16071 CIN,
ADC16471CIWM, ADC16071CIWM

±100mA

Maximum Junction Temperature (Note 4)
Storage Temperature

Op~rating

±25mA

Package Input Current (Note 3)

4000V
250V

S;

Supply Voltage
VA+, Vo+, VM+

300·C
220·C
215·C

TA

S;

+ B5·C

4.75V to 5.25V

Converter Electrical Characteristics
The following specifications apply for VM+ = VA + = Vo+ = 5.0Voc, VMIO = VA + 12 = 2.50V, VREF+ = VMIO + 1.25V,
VREF- = VMIO - 1.25V, fClK = 24.576 MHz, and dynamic tests are performed with an input signal magnitude set at -6 dB
with respect to a full-scale input unless otherwise specified. Boldface limits apply for T A = T J = T min to T max; all other
limits T A = TJ = 25·C.
Symbol

Parameter

Typical
(Note 6)

Conditions

Limits
(Note 7)

Units
(Limit)

16

Bits

76

72

dB (min)

0.010

0.022

% (max)

0.010

0.017

% (max)

-88

-77

dBFS(min)

80

dB (min)
dB (min)

Resolution
fClK

=

24.576 MHz (f.

=

192 kHz)

=

S/(N+D)

Signal-to-Noise + Distortion Ratio

Measurement bandwidth
fiN = 19 kHz

THD

Totai Harmonic Distortion

fiN

Intermodulation Distortion

f1

Converter Noise Floor (Note 8)

Measurement Bandwidth

=

0.45fs

Measurement bandwidth
fiN = 5kHz

=

0.45fs

IMD

'ClK

=

6.144 MHz (I.

S/(N+D)
THD
IMD

=

= 19 kHz
= 18.5 kHz, f2 =

0.45fs

19.5 kHz

48 kHz)

Signal-to-Noise + Distortion Ratio
Total Harmonic Distortion
Interrnodulation Distortion
Converter Noise Floor (Note 8)

fiN
f1

=
=

5kHz
4 kHz, f2

85
0.002

=

5.5 kHz

Measurement Bandwidth

0.003

=

0.45fs

-99

73
0.0055

0.008
0.009

0.01
-92

% (max)
% (max)
% (max)
% (max)

-89

dBFS(min)
dBFS(min)

±1.0

%FS(max)

OTHER CONVERTER CHARACTERISTICS
ZIN

Input Impedance (Note 9)

flAv

Gain Error

34
±0.2

kO

VOS

Input Offset Voltage

15

IA

Analog Power Supply Current

23

31

mA(max)

1M

Modulator Power Supply Current

fClK
fClK

24.576 MHz
6.144 MHz

1.6
0.4.

2.4
0.8

mA(max)

10

Digital Power Supply Current

fClK
fClK

24.576 MHz
6.144 MHz

50
13·

65
23

mA(max)

Ispo

Power-Down Supply Current

IA + 10 + 1M

0.25

1.3

mA

0.375

0.5

W

Po

=
=
=
=

Power Dissipation

VA+/2

VMID
2-674

mV

V

Digital Filter Characteristics
The following specifications apply for VA+ = Vo+ = VM+ = 5V unless otherwise specified.
TA = T" = Tml n to Tmall; all other limits TA = TJ = 25°C.
Symbol

Parameter

Conditions

Typical
(Note 6)

Limits
(Note 7)

Units
(Umlt)

Stopband Rejection

-90.0

dB

Passband Ripple

±0.005

dB

3 dB Cutoff Frequency

0.45

fs

Data Latency

3,968

Clock Cycles

Reference Characteristics (ADC16471 Only)
The following specifications apply for VA + = Vo+ = VM+ = 5V, unless otherwise specified.
= T" = Tml n to T mall ; all other limits TA = TJ = 25°C.
Symbol

Boldfacallmlt. apply for

Parameter

Conditions

Boldtacallmlt. apply tor TA

Typical
(Note 6)

Limits
(Note 7)

+
+

VREF+

Positive Internal Reference
Output Voltage

VMIO

VREF-

Negative Internal Reference
Output Voltage

VMIO -1.25

d(VREF+VREF-)/dT

Internal Reference
Temperature CoeffiCient

dVREF+/dl

Positive Internal Reference
Load Regulation

Sourcing (0 mA:S: I :s: + 10 rnA)
Sinking (-1 mA:S: I :s: 0 rnA)

3.4

6.0

dVREF-/dl

Negative Internal Reference
Load Regulation

Sinking (-1 mA:s: I :s: 0 rnA)
Sourcing (0 rnA :s: I :s: 10 rnA)

3.2

6.0

Typical

Limits
(Note 7)

+ 1.25

Units
(Limit)

1.175
1.325

V (min)
V (max)

YMID - 1.325
YMID"" 1.175

V (min)
V (max)

YMID
YMID

30

ppml"C

mV(max)

Input Reference Characteristics (ADC16071 Only)
The following specifications apply for VA +
Symbol

=

Vo+

=

Parameter

VREF+

Positive Reference Voltage

VREF-

Negative Reference Voltage

VREF+-VREF-

Total Reference Voltage

VM+

=

5V.
Conditions

(Note 6)
1
VA+
0
VA+ - 1 .
1
VA+

2·675

Units
V
V
V
V
V
V

DC Electrical Characteristics
The following specifications apply for VA + = Vo+ = VM+ =' 5V unless otherwise specified. Boldface limits apply for TA
=, TJ = T.I. to T.AX; all other limits TA = TJ = 25D C.
Symbol
VIH

Parameter
logic High Input Voltage

Typical
(Note 6)

Conditions
Vo+ = 5.25V

Limits
(Note 7)

Units
(Limit)

VD+

2.3

V (max)
V (min)

0.8
-0.3

V (max)
V (min)

Vil

logic low Input Voltage

Vo+ = 4.75V

VOH

logic High Output Voltage

logic High Output Current = -400/LA,
Vo+ = 4.75V

2.4

V (min)

VOL

logic low Output Voltage

logic low Output Current = 2 mA,
Vo+ = 5.25V

0.5

V (max)

IIN(l)

,logical

IIN(O)

logical "0" Input Current

Irsl

SDO TRI-STATEII!> leakage Current

VIN = OAV to 2AV

CIN

logic Input Capacitance

VIN

"1~'

Input Current '

=

1.0

5.0

/LA (max)

-1.0

-5.0

/LA (max)

1.0

5.0

/LA (max)

5

OtoVo+

pF

AC Electrical Characteristics for Clock In (ClK), Serial Clock Out (SCO), and
Frame Sync In (FSI)
The following specifications apply for VA + , = Vo + = VM + = 5V unless otherwise specified. Boldface limits apply for TA
= TJ = T.IN to T.AX; all other limits TA = TJ = 25D C.
Symbol

Parameter

fClK

ClK Frequency Range
(fClK = 1/tclK)

tclK

ClKPeriod
(tClK

=

Conditions

Typical
(Note 6)

1/fClKl

Limits
(Note 7)

Units
(Limit)

25
1

MHz (max)
MHz (min)

1000
40

ns(max)
ns(min)
ns(min)

tClKl

ClK low Pulse Width

16

tclKH

ClK High Pulse Width

14

ns(min)

tR

ClK Rise Time

10
3

ns(max)
ns(min)

tF

ClKFaliTime

10
3

ns(max)
ns(min)

tFSllOW

Minimum Frame Sync Input
low Time before Frame Sync
Input Asserted High

2

tclK (min)

tFSISU

Frame Sync Input Setup Time

10

ns(min)

tFSIH

Frame Sync Input Hold Time

10

ns(min)

tscoo

Serial Clock Output Delay
Time from Rising Edge
ofClK

20
5

ns(max)
ns(min)

4

tClK

tsco

12

Serial Clock Output Period

2-676

AC Electrical Characteristics for Frame Sync Out (FSO), Serial Clock Out
(SCO), and Serial Data Out (SDO)
The following specifications apply for VA + = Vo+ = VM+ = 5V unless otherwise specified. Boldfacallmlts apply for TA

= T .. = TMIN to TMAX; all other limits TA = TJ = 25'C.
Parameter

Symbol
tSCOFSOH

Conditions

Typical
(Note

Delay from Serial Clock Out to
Frame Sync Output Low

tsoov

Delay from Serial Clock Out to
Serial Data Output Valid

tFSIFSOL

Limits
(Note

7)

Units
(Limit)

o
.....

G)

(:)
~

.....
i;
C
o
.....
en
0l:Io

Delay from Serial Clock Out to
Frame Sync Output High

tSCOFSOL

6)

»
c

2

5

ns(max)

2

5

ns(max)

3

8

ns(max)

8

tCLK(max)

Delay from Frame Sync Input to
Frame Sync Output Low

~

.....

AC Electrical Characteristics for Data Output Enable (DOE)
The following specifications apply for VA + = vo+ = VM+ = 5V unless otherwise specified. BoldfacaUmlts apply for TA

= T .. = TMIN to TMAX; all other limits TA = TJ = 25'C.
Symbol

Parameter

Typical

Conditions

(Note

6)

Limits
(Note

7)

Units
(Umit)

tOOEE

Data Output Enable Delay Time

20

25

ns(max)

tOOEO

Data Output Disable Delay Time

16

20

ns(max)

Note 1: Absoluie Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions lor which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All volleges are measured with respect to GNO, unless otherwise specified.
Note 3: When the input vollege (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > (VA + , VM + , or Vo +)), the current althat pin should be limited
to 25 mAo The 100 mA maximum package input current rating allows the voltage at any four pins, wilh an input current of 25 mA each, to simultaneously exceed the
power supply volleges.
Note 4: The maximum power dissipation is a function of the maximum junction temperature (TJ(MAXll, total thermal resistance (6JtJ, and ambient temperature (TtJ.
The maximum allowable power dissipation at any ambient temperature is PO(max) = (TJ(max) - TtJI6JA. When board mounted, the ADC16071/ADC16471's
typical thermal reslstence is:
Order Number

6JA

AOC16071CIN, ADCI6471CIN

47"C/W

AOC16071CIWM, ADC16471CIWM

72'C/W

Note 5: Human body model, 100 pF discharge through a 1.5 kn resistor. The machine model is a 200 pF capacitor discharged directly into each pin.
Note 6: Typicals are at TA

= 25'C and represent most likely parametric norm.

Nota 7: Umits are guaranteed to National's AOQl (Average Output Qualily level).
Note 8: The VIN + pin is shorted to the VIN - pin.
Note 9: The input Impedance between VIN + and VIN _ due to the effective resistance of the switch capaCitor Input varies as follows:
1012
ZIN =
2.35' (fCt)

2·677

•

Typical Performance Characteristics
+

S/(N
80
70

a;.3

~

~

90

_~~=lb~z

88

'IN=80 kHz

60 _ TA=25°C
Vo+ = S.OOY
50 -VA+ = S.DDY

/

,

40

/

86

a;- 84

/

/

30

--

~

80 I-- Y,N = -6 dB
76

r- ~=::~o~H2

f--- VD+ = 5,00V

.3

76

~

75

72
71

70L----'----'---~

70

48

96

144

=

VIN -6 dB
fs=192kHz- t-fiN =20kHz- t-Vo+ =5.00~_
t-VA+ S.ODY

74
73

~

72

-80 -70 -60 -50 -40 -30 -20 -10 0

=

I
-50 -25

192

Spectral Response,
fs = 192 kHz,
'
fiN = 20kHz

Spectral Response,
fs = '192 kHz,
fiN = 80kHz

r--,-,--r-,--r---,

0.0

0

25

50

75

100

Ambient Temperature (Oe)

Is (kHz)

VIN Amplitude (dBFS)

0.0

--

.... r-....

74 f-- VA1'=SIO OV

/

+ D) vs Temperature

n

a;-

i--.

82
78

S/(N
80
79
78

.3

~

/

20
10

S/(N + D) vs Output
Data Rate (fs)

D) vs VIN Amplitude

Spectral Response,
fs = 48kHz,
fiN = 5kHz

r--,-,--r-,--r---,

0.0

r--,-,--r-,--r---,

-20.00 f-'.-+I-+--If--+--'--I

-20.00 1--+-+--If--+--I--1

-20.00 1--H1-+--I--+-+--1
-40.00 f-'--+lf-4--' T;

-4Q.OO f--+I-+--If-

-40.00

-60.00 f--+I-+--If-

-60.00

-80.00 I--+I-+--If--+-+--I

-80,00 1--+~+--If--+--I--1

-80,00 1--H1-+--If--+-+--1

-100,01--HI-+-Hf--'+-+--I

-100,01--+-+--If--+-f--1

-100.0 1--+.lb-+--I-+l--+--1

-120,0

-120.0

-120.0

m

-60.00 1--+lf-4--. v.

~

-140.0
,6.0k 32.0k 48,Ok 64.0k 80,Ok 96,Ok

l6.0k 52.0k "S.Ok 64.0k aO.Ok 96.0k

rREQUENCY (Hz)

Analog Supply Current
(IA + 'M) vs Temperature
30

I

29
28

'<

.s

.
~

-~

56

25

./

22
21

'<
.s

,/
~

24
23

_0

.."

./

20
-50 -25

I

55
54

fs =192kHI

50

75

Analog Supply Current
(IA + 'M) vs Output
Data Rate (fs)

50
49

Ambient Temperature (oe)

I

29
28

27 I-- VA+ = 5'.00V
26 I--~D+=5.00V
TA = 25°C
.;;< 25
-~ 24
23

-- -

46
-50 -25

100

30

I

53 I-- ~A+ = loov
52 I-- ~o+ = 5.00V
Is = 192 kHz
51

48
47
25

rREQUENCY (Hz)

Digital Supply Current
10 vi; Temperature

I

27 I-- ~A+ = d.oov
26 f--- ~D+ = 5,00V

0,0 4,00k 8.00k 12,Ok 16,Ok 20,Ok 24,Ok

rREQUENCY (Hz)

'<

.

.s

i,....-o

25

50

75

22
21

-- -

20
48

100

Ambient Temperature (oe)

Digital Supply Current
(10) vs Output Data
Rate (fs)

96

144

192

IS (kHz)

Frequency Response of
Digital Filter

100
00
80

'<
.s
.P

-20

70 I--VA+=~'OOV
60 I--~D+ = 5.00V
TA = 25°C
50
40
30
20
10 ~

.........

fS = 192 kHz

a;- -40
.3 -60

"".,..,

"...

-80

~

-100

Woi ...

II

-140

o

192

,11..

"'W"'I'IIIlII' 'I"

-120

o
48

"=>~

~

g

~ ~~0IWlg1~1~

,NPUT FREQUENCY (kHz)
TL/H111454-24

2-678

~
o....
en

CI

.....
....
.......

ClK

~

C

o
....
Ci)
~

.....
....
FSI

SCQ

TLlH/11454-B

FIGURE 1. Timing Diagrams for Clock Input (ClK),
Frame Sync Input (FSI), and Serial Clock Output (SCO)

2-679

ADC16071! ADC16471

eLK

FSI

seo

'0'

~
'-'

8
~

Ip

I

FSO

~

(J)

I SDO

CJ)

0

r.~

f

- - - + - - - - - - - - - + - ' 1' '1-'1_ _ _M

'U1

~:

'fJ.

01

n

DO

\\

;~

irSIFSOL

FSO

"

!

~I
SDO

_ _ _ _ _ _ _ _ _ _ _""--_____MI

I\.JI

~:=JJ

01

'fJ.

DO

\\

TUH/11454-4

FIGURE 2. Detailed TIming Diagrams for Frame Sync Input (FSI), Frame Sync Out (FSO), Serial Clock Out (SCO), and Serial Data Out (SOO)

1 - - - - - - - - - - - - - - - - - - - - - - - 128

elK CYCLES - - - - - - - - - - - - - - - - - - - - - - - - - l

elK

~,

seo

0

'"g
"

"~ I
I\)

m

FSO

____~O

r

~

"
l:0O

~

crs

VALID DATA FOR 16

seQ

CYCLES

II

ZERO FOR LAST 16

seQ

CYCLES

~~~

__
VALID

eo

~
~

'i'

"§ I rso

"
"

lOW FOR FIRST 16

seQ

CYCLES

HIGH FOR LAST 16

sea

CYCLES

ZERO FOR LAST 16

seQ

CYCLES

~

I
SDO

VALID DATA FOR 16

sea

CYCLES

VALID

TLlH/114S4-S

FIGURE 3. Timing Diagrams for Frame Sync Out (FSO), Serial Clock Out (SCO), and Serial Data Out (500)

~LP9~~a\f HL09~~a\f

ADC160711ADC16471

CLK

fSI (UASTER) ''''')HlP

I\)

~

t

('"

Jl ".

xC=::JI

fco

\~

1\

Jl"
1\

IX" U " ) "

IJL-~D

--1-)- - - : - - - -

1\

( ...

IX ... If
TUH/11454-6

FIGURE 4. Master/Slave Mode TImIng Diagrams

DOE

»
o
o....

........,

(MAST ER/
SIN GLE)

2.3

G)

0.8

Q

.......
....

i>
o

o
....
.......
....

G)

DOE

01:00

(SLAV E)

---'
~ 'OOEE

'OOED

SOO

TLlH/11454-7

FIGURE 5. Timing Diagrams for Data Output Enable (DOE) and Serial Data Out (500)

Pin Description
VREF+, VREF- These are the ADC16471's internal differential reference's bypass pins. Their nominal output voltage is ± 1.25V centered
around the voltage at the VMID pin, typically
VA+/2. VREF+, VMID, and VREF- should
be bypassed with a parallel combination of
10 ,.F and 0.1 ,.F capacitors. For the
ADC16071, these are the reference voltage
inputs. VREF+ and VMID should be bypassed with a parallel combination of 10 ,.F
and 0.1 ,.F capacitors.
This pin is the internal differential reference's VA + 12 output pin. VMID should be
bypassed with a parallel combination of
10 ,...F and 0.1 ,...F capacitors.
These are the ADC's differential input pins.
Signals applied to these pins can be singleended or differential with respect to the
VMID voltage.
This is the input pin used to activate the
power-down mode. When a logic lOW (0)
is applied to this pin the supply current
drops from 100 mA (max) to 1.3 mA (max).
This is the connection to system analog
AGND
ground. Internally, this ground is connected
to the analog circuitry, including the fourthorder modulator.
This is the connection to system digital
DGND
ground. Internally, this ground is connected
to all digital circuitry except the modulator's
clock.
This is the ground pin for the modulator'S
MGND
clock. It should be connected to analog
ground through its own connection that is
separate from that used by AGND.
This pin is the connection to the system analog voltage supply. Best performance is
achieved when this pin is bypassed with a
parallel combination of 10 ,...F and 0.1 ,...F
capacitors.

SFMT

TMO, TM1
FSI

ClK

SCO

SDO

2-683

This is the modulator'S supply pin. VM+ should
be connected to the system analog voltage
supply with a circuit board trace or connection
that is separate from that used to supply VA + .
Best performance is achieved when this pin is
bypassed with a parallel combination of 10 ,...F
and 0.1 ,...F capacitors.
This pin is the connection to the system digital
voltage supply. Best performance is achieved
when this pin is bypassed with a parallel combination of 10 ,.F and 0.1 ,.F capacitors.
This is the Serial Format pin. The logic level
applied to the SFMT pin determines whether
conversion data shifted out of the 500 pin is
valid on the rising or falling edge of seo. It also
controls the format of the Frame Sync Out
(FSO) signal. See the Serial Interface section
for details.
Used to enabled test mode during production.
Connect both pins to DGND.
This is the Frame Sync Input pin. FSI is an
input used to synchronize the ADC160711
ADC16471's conversions to an external source.
The state of FSI is sampled on the falling edge
of elK. See the Serial Interface section for
details.
This is the clock signal input pin. The signal applied to this pin sets the sample rate of the
ADC16071 1ADC16471's modulator to fClK/2.
The frequency range can be 1 MHz ,;;; fClK ,;;;
25 MHz.
This is the Serial Clock Output pin. The
ADC16071 1ADC16471's serial data transmission is synchronous with the seo signal. seo
has a frequency of fClK/4. See the Serial Interface section for details.
This is the Serial Data Output pin. The
ADC16071/ADC16471's conversion data is
shifted out from this pin synchronous to the
seo signal. See the Serial Interface section
for details.

~'r-------------------------------------------------------------------------------------,

~

Inf~rmation

Pin Description (Continued)

Applications

FSO

TYPICAL PERFORMANCE RESULTS
Figure 6 ShOws a 16k point FFT plot of the baseband output
spectrum during conversion of a 24 kHz input Signal.

~

o
c
cc
.....
~

r...

i:
~

o
c

cc

TSI

DOE

This is the Frame Sync Output pin. FSO is used
to synchronize an external device to the
ADC16071/ADC16471's 32 SCO cycle data
transmission frame. The format of the signal on
FSO depends on the logic level applied to the
SFMT pin. See the Serial Interface section for
details.
This is the Time Slot Input pin. TSI can be used
to allow two ADC16071/ADC16471's to share a
Single serial data line. The logic level applied to
TSI controls the active state of the ADC16071 /
ADC16471's DOE pin. See the Serial Interface
and the Two Channel Multiplexed Operation
sections for details.
This is the Data Output Enable pin. DOE is used
to control SDO's TRI-STATE output buffer. The
active state of DOE is controlled by the logic level applied to the TSI pin. See the Serial Interface and the Two Channel Multiplexed Operation sections for details.

CLOCK GENERATION
The ADC16071/ADC16471 requires a sampling-clock signal that is free of ringing (over/undershoot of no more than
100 mVp•p) and has a rise and fall time in the range of 3 ns10 ns. We have tested and recommended crystal clock oscillators from Ecliptek (EC1100 series) and SaRonix
(NCH060 and NCH080 series). Both of these families use
HCMOg logic circuitry for very fast rise and fall times.

O~--~----.-------~-r----~---r----~---'-------'

SINAD = 77.11
-20r----------r-r--------t----------r~+=SV ~~------~

vD+ = SV
S.~.6 dBFS)

VIN = 0.90 Vrms

-40 r - - - - - - - - - - r - r - - - - - - - i t - - - - - - - - - - r fiN = 24 kHz .. --r-----;-~

Iii"

..

.:g.

-60

..,

:E

0.
E

<

-80

, i

Frequency (x 104 Hz)
TL/H/11454-13

. i'IGURE 6. Typical Perform.ance 01 the ADC160711 ADC16471 at Is = 192 kHz, liN ,= 24 kHz

2-684

Applications Information

(Continued)
Due to the data latency of the ADC16071 I ADC16471 's digital filters, the first 31 conversions following a frame sync
input signal will represent inaccurate data, unless the frame
cycle intervals. If no
syncs are applied at constant 32
FSI signal is applied (FSI is kept High or Low), the
ADC16071/ADC16471 will internally create a frame sync
cycles.
every 32

Overshoot and ringing can be reduced by adding a series
damping resistor between the crystal oscillator:s output (pin
8) and the ADC16071/ADC16471's CLK (pin 12), as shown
in Figure 7. The actual resistor value is dependent on the
board layout and trace length that connects the oscillator or
CLK source to the ADC. A typical starting value is son with
a range of 27n to 150n.

l

I

sca

sca

The Data Output Enable pin (DOE), is used to enable and
disable the output of data on SDO. When DOE is deactivated, SDO stops driving the serial data line by entering a high
impedance TRI-STATE. DOE's active state matches the
logic level applied to the Time Slot Input pin (1SI). If a logiC
Low is applied to TSI, the ADC16071/ADC16471's SDO pin
will shift out data when DOE is Low, and be in a high impedance TRI-STATE when DOE is High. If a logic High is applied to TSI, SDO will shift out data when DOE is High, and
be in a high impedance TRI-STATE when DOE is Low.

iCLK
RD
12tADC16(O/4)7111
GENERATION IJ---,\~---IICLK
CIRCUITRY
27 -150n

.....__......

TLlH111454-23

FIGURE 7. Damping Resistor Reduces
Clock Signal Overshoot
SERIAL INTERFACE
The ADC16071 and the ADC16471 have three serial interface output pins: Serial Data Output (SDO), Frame Sync
Output (FSO), and Serial Clock Output (SCO). SCO has a
frequency of fCLK/4. Each of the ADC160711 ADC164 71 's
16-bit conversions is transmitted within the first half of the
data transmission frame. A data transmission frame is 32
SCO cycles in duration. Two's complement data shifts out
on the SDO pin beginning with bit 15 (MSS) and ending with
bit 0 (LSS), taking 16 SCO cycles. SDO then shifts out
zeroes for the next 16 SCO cycles to maintain compatibility
with two channel multiplexed operation.
The serial data that is shifted out of the SDO pin is synchronous with SCO. Depending on the logic level applied to the
Serial Format pin (SFMT), the data on the SDO pin is valid
on either the falling or rising edge of SCO. If a logiC Low is
applied to SFMT, then the data on SDO is valid on the failing edge of SCO. If a logic High is applied to SFMT, then
the data on SDO is valid on the rising edge of SCO. See
Figure 2.

TWO CHANNEL MULTIPLEXED OPERATION
Two ADC16071 IADC16471 's can easily be configured to
share a single serial data line and operate in a "stereo", or
two channel multiplexed mode. They share the serial data
bus by alternating transmission of conversion data on their
respective SDO pins. One of the ADC16071/ADC16471's,
the Master, shifts its conversion data out of SDO during the
first 16
cycles of the data transmission frame. The
other ADC16071 IADC16471, the Slave, shifts its data out
during the second 16 SCO cycles of the data transmission
frame.
The Slave is selected by applying a logic High to its TSI pin
and a logic High to its SFMT pin. The Master is chosen by
applying a logic Low to its TSI pin and a logic High to its
SFMT pin. As shown in Figure 8, the Master's FSO is used
to control the DOE of both the Master and the Slave as well
as to synchronize the two ADC16071/ADC16471's by driving the Slave's Frame Sync Input pin, FSI. As the Master
finishes transmitting its 16 bits of conversion data, its FSO
goes High. This triggers the Slave's FSI, causing the Slave
to begin transmitting its 16 bits of conversion data.

sca

The FSO signal is used to synchronize other devices to the
ADC16071 I ADC164 71 's data transmission frame. Depending on the logic level applied to SFMT, the signal on FSO is
either a short pulse (approximately one SCO cycle in duration) ending just before the transmission of bit 15 on SDO,
or a square wave with a period of 32 SCO cycles going low
just before the transmission of bit 15 and gOing high just
after the transmission of bit o. If a logic Low is applied to
SFMT, FSO will be high for approximately one
cycle
and fall low just before the transmission of bit 15 and stay
low for the remainder of the transmission frame. If a logic
High is applied to SFMT, FSO will be low during the transmission of bits 15-0 and high during the next 16 SCO cycles. See Figure 3.

The Master's DOE is active Low and the Slave's DOE is
active High. Since the same signal, the Master's FSO, is
connected to both of the converters' DOE pins, one converter will shift out data on its SDO pin while the other is in
TRI-STATE, allowing the two ADC16071/ADC16471's to
share the same serial data transmission line.

sca

POWER SUPPLY AND GROUNDING
The ADC16071/ADC16471 has on-chip 50 pF bypass capacitors between the supply-pin bonding pads and their corresponding grounds. There are 24 of these capacitors, 6 for
the analog section and 18 for the digital, resulting in a total
value of 1200 pF. They help control ringing on the on-chip
power supply busses, especially in the digital section. Further, they help enhance the baseband noise performance of
the analog modulator.

The Frame Sync Input (FSI), is used to synchronize the
ADC16071/ADC16471's conversions to an external source.
The logic state of FSI is captured by the ADC160711
ADC16471 on the falling edge of ClK. If an FSIIow to high
transition is sensed between adjacent ClK falling edges,
the ADC16071/ADC16471 will interrupt its current data
transmission frame and begin a new one. See Figure 4.

2-685

til

~

:

r-------------------------------------------------------------------------------------,
Applications Information (Continued)

~

~

AOC18(O/4)71

lSI

FSO

~

i

011(

SOO

.' SFMT

"

~

g

~

-

MAS1ER

~

SCO

ClK

OOE

FROM PROCESSOR
, 'Vo+

y

AOC16(O/4)71

lSI

SLAVE

, FSI

,

FSO

SOO

SFMl

"

-

SCO

• r---t
,

.

ClK

"

DOE

1 MHz ~ 'elK ~ 25 MHz
"

,

, TL/H/II454-14

,FIGURE 8. Two Channel Multiplexed Operation Connection Diagram
Best converter pertormance iS'achieved when these Internal bypass capacitors are supplemented with additional exiemal power-supply d~upling capacitors. This ensures the
lowest ae-bypass impecflince path for the ADC160711
ADC16471's dynamic' current requirements. Each of the
ADC16071 IADC16471 's four supply pins should be individually bypassed, using a parallel combination of 10 ",F (tantalum) and 0.1 ",F (monolithic ceramic), to its corresponding
ground pin:
" '
VA+ (Pin 21) -+ AGND (Pin 4)
VM + (Pin 20) -+ MGND (Pin 5)
Vo+ (Pin 19) -+ DGND (Pin 6)
.Vo+ (Pin 18) -+ .DGND (Pin 7)
Short lead lengths are mandatory. Therefore, surface mount
capacitors are strongly recommended.

ANALOG INPUT
The ADC16071 and the ADC1647t generate a two,'s complement output determined by the following equation:
'0
C d
(VIN+ - VIN-) (32768)
utput 0 e ='
,
, (VREF+ - VREF-)
Round off to the nearest integer value between -32768
and 32767.
'
.'
"
.
"

The signals applied to VIN+ and VIN- m,ust be between
VA + and analog ground. For accurate conversions, the absolute difference between VIN+ and VIN-, ,should be less
than the difference between VREF +, and VREF-' Best harmonic performance will result when a differential voltage is
applied to VIN+ and VIN- that has a common n:Jode voltage
,
at or below VMIO.
Due to overloadi~g in the ADC1607,11 ADC16471's
modulator, performance degrades considerably as the input amplitude approaches, full scale. With an input that peaks at
-2 dB from ,full scale, S/(N -+- D) is about '2 dB worse than
with a -'-6 dB input.,With a -1 dB input, S/(N
D) can be
10 dB 'i"orse than with a, -6 dB, input.

Ai

POWER SUPPLY VOLTAGES FOR BEST
PERFORMANCE
While adequate performance will be achieved by operating
the ADC16071/ADC16471 with +5V connected to VA+,
VM+ and Vo+, dynamic performance, as measured by
S/(N + D), can be further enhanced by slightly raising the
analog supply voltage and lowering the digital supply voltage.

+

2-686

Applications Information

(Continued)

ANALOG SIGNAL CONDITIONING
The ADC16071/ADC16471's digital comb and FIR filter
combine to create the band-limiting anti-aliasing filter, generating a steep cutoff at the upper range of the sampled
baseband. Additional external filtering is needed to ensure
that the best conversion performance is maintained. The
external filtering uses a simple R-C lowpass filter. A suggested circuit is shown in Figure 9. The values of Rl, R2, Cl,
C2, and Cs are found using the following equation:

have film dielectrics. Of these, polypropylene and polystyrene are the best. These are followed by polycarbonate and
mylar. If ceramic capaCitors are chosen, use only capacitors
with NPO dielectrics.
INTERNAL DIFFERENTIAL BANDGAP REFERENCE
A fully differential bandgap reference generates local feedback voltages, VREF+ and VREF-, for the analog modulator. The outputs of this reference are trimmed to be equal to
VMID plus or minus 1.25V. This gives a differential reference
voltage of 2.5V which results in a ±2.5V differential input
range. The ADC16071 does not have the internal differential bandgap reference, allowing the user the flexibility to
determine the full scale range by using an external voltage
reference.

1
ie(-SdS) = 6wRG

where R = Rl = R2 and C = Cl = C2 = Cs.
The effects of the external filter are minimized by choosing
a minimum cutoff frequency equal to fClK/32. As an example, for fClK equal to 6.144 MHz, set Rl = Ri = 82.5fl and
Cl = C2 = Ca = 3300 pF. This sets the input network's
cutoff frequency at 194 kHz. For fClK equal to 24.576 MHz,
set Rl = R2 = 20fl and Cl = C2 = Cs =·3300 pF. This
sets the input network's cutoff frequency at 803 kHz.

EXTERNAL VOLTAGE REFERENCE FOR THE
ADC16071
Figure 10 shows the suggested connection diagram for the
ADC16071. The LM4041-ADJ is set to 2.0V and is applied
to the ADC16071's VREF+ input.
The reference voltage must be free of noise. This is accomplished using the same capacitor combination used with the
ADC16471's reference pins with the exception of VREF-,
which is connected to analog ground.

RELATION BETWEEN CAPACITOR DIELECTRIC AND
SIGNAL DISTORTION
For any capacitors connected to the ADC160711
ADCl6471's analog inputs, the dielectric plays· an important
role in determining the amount of distortion generated in the
input signal. The capacitors used must have low dielectric .
absorption. This requirement is fulfilled using capacitors that

,rlr!.
,rlr!.
,rlr!.

••
*"

J\JlIlrc-

1 MHz < lelK

Figures 11 and 12 show the suggested circuits for ac-coupled applications.

VRE ,+

VIN +

VRE'~

VIN -

VMID
AGND
MGND
DGND
DGND

RI

+

R2

Suggested values:
R, = R2 = 200. 5%. metal 111m
C, = C2 = C3 = 3S00 pF. 5%.
polypropylene

Po 1---=--"",\
vA+ I-:"'~*~--\-:
VCl4. 75V - 5.25V
.vu+
vo+
.. V +

¥ \ 75V - 5.25V
1--+-I1--.¥*=---/-D4.

. D

SfMT

TSI

TMO

ODE

fI

!J..f

TMI

,SO

fSI

500 t t - - - - - - . } T o host processor

ClK.

SCO

< 25 MHz

-=

TLlH/11454-15

'Parallel combination 01 10 ,.F tan·
talum and a 0.1 ,.F monolithic ce·
ramie capaCitors.

FIGURE 9. Typical ConnectIon Diagram for the ADC16471

2·687

Applications Information (Continued)
4.5V-5.5V
60411

",

10 kll

Suggested values:
.
Rt = R2 = 200, 5%, mellil film
Ct = C:! = Ca = 3300 pF, 5%,
polypropylene .

LN4041-ADJ

III

1-1:---4--,0 4. 75V - 5.25V
t-f-'I-1p::---iC 4. 75V - 5.25V

DGND
DGND
SFNT

JU1flf

1 MHz < 'elK < 25 MHz

TNO

DOE

TNI
FSI

FSO
SDO

1+-----..

}
To host processor

I(C:LK~____~S~CO~-----+
..

'Parallel combination of 10 ,.F tantalum and a 0.1 ,.F monolRhic ceramic capacRors.

TUHI11454-18

FIGURE 10. Typical Connection Diagram for the ADC16071

Suggested values:
.
Rt = R2 - 200, 5%, metal film
Ct = C:! = C:! =. 3300 pF, 5%,
polypropylene

t-1:----T-'O 4.75V - 5.25V
t-t-'F-r:---J:i4.75V - 5.25V

JU1flf

I MHz <'eLK < 25 NHz

TNO

DDE

TNI

FSO

FSI

SDO I + - - - - -..

CLK

sea

}T. h.st p,....,.,

..,.
'Parallel combination of 10 ,.F tan.
talum and a 0.1 ,.F monolithic ceramic capaCitors.

TUHI11454-17

FIGURE 11. Typical Connection Diagram for the ADC16471 with AC-Coupled Inputs
4.5V- 5.5V

III
tf!c
r_~:60~4Ln~_~~~~----~~~~~~~~
10kll

H~wJ.~--+-tA

LN4041-ADJ

t--'"'..1.~ 2 x 2.2 pF FILM

I II

Suggested values:
Rt = R2 = 200, 5%, metal film
Cl = C2 = Ca = 3300 pF, 5%,
polypropylene

1-'t:----+.,c4. 75V - 5.25V

6.19kll

III

t-HHP::---lC4. 75V - 5.25V

'Parallel combination of 10 ,.F Ia/I.
talum and a 0.1 ,.F monolRhlc ceramic capacRora.

TUHI11454-18

FIGURE 12. Typical Connection Diagram for the ADC16071 with AC-Coupled Inputs

2-688

~

C

Applications Information (Continued)

o
....

DSPINTERFACES

~
....

en

The ADC16071/ADC16471 was designed to connect to popular DSPs without intervening "glue logic". Figures 13, 14, and 15
show suggested connection schematics for the DSP56001, TMS320C3x, and the ADSP-2101 families.

ADC16071/ADC16471

OSPS6001

FSO

pcs (FSR)

SOO

PC7 (SRO)

SCO

PC6 (SCK)

=
~
....

SFMT ~

OOE ~

-:..:TUH/11454-19'

FIGURE 13. Interface Connections between the ADC16071/ADC16471 and the Motorola DSP56001 '

ADC16071/AOCl6471

TMS320C3x

FSO

FSR

SDO

DR

SCO

CLKR

SFMT

r--

ODE

r--

-:..:TUH/11454-20

FIGURE 14. Interface Connections between the ADC16071/ADC16471 and the Texas Instruments TMS320C3x

ADSP-2102

ADC16071/ADCl6471
FSO

RFS

SDO

DR

SCO

SCLK

SFMT ~

DOE

-

-:..:rL/H/11454-21

FIGURE 15. Interface Connections between the ADC16071/ADC16471 and the Analog Devices ADSP-2101

2-689

);
C
o
....

9-

f3

r-------------------------------------------------------------------------------------,

:I tflNational

Semiconductor

<

.:

9-

f3

:::E

.... LM131A/LM131, LM231A/LM231, LM331A/LM331
....I
9-

~

:::E

....I

<
9-

~
:::E

....I
....
9-

CO)
9-

:::E

....I

<
9-

CO)

9-

:::E

....I

Precision VOltage-to-Frequency Converters

General Description
The LM131/LM231/LM331 family of voltage:to-frequency
converters are ideally suited for use in simple low-cost circuits for analog-to-digital conversion, precision frequencyto-voltage conversion, long-term integration, linear frequency modulation or demodulation, and many other functions.
The output when used as a voltage-to-frequency converter
is a pulse train at a frequency precisely proportional to the
applied input voltage. Thus, it provides all the inherent advantages of the voltage-to-frequency conversion techniques, and is easy to apply in all standard voltage-to-frequency converter applications. Further, the LM131 AI
LM231A1LM331A attains a new high level of accuracy versus temperature which could only be attained with expensive voltage-to-frequency modules. Additionally the LM131
is ideally suited for use in digital systems at low power supply voltages and can provide low-cost analog-to-digital conversion in microprocessor-controlled systems. And, the frequency from a battery powered voltage-to-frequency converter can be easily channeled through a simple photoisolator to provide isolation against high common mode levels.
The LM131/LM231/LM331 utilizes a new temperaturecompensated band-gap reference circuit, to provide excellent accuracy over the full operating temperature range, at
power supplies as low as 4.0V. The precision timer circuit

has low bias currents without degrading the quick response
necessary for 100 kHz voltage-to-frequency conversion.
And the output is capable of driving 3 TIL loads, or a high
voltage output up to 40V, yet is short-circuit-proof against
Vee·

Features
• Guaranteed linearity 0.Q1 % max
• Improved performance in existing voltage-to-frequency
conversion applications
• Split or single supply operation
• Operates on single 5V supply
.. Pulse output compatible with all logic forms
• Excellent temperature stability, ± 50 ppm/DC max
• Low power dissipation, 15 mW typical at 5V
• Wide dynamic range, 100 dB min at 10kHz full scale
frequency
• Wide range of full scale frequency, 1 Hz to 100 kHz
• Low cost

Typical Applications
:

Ct

o.OhF*

:(
LMI31
LM231
LM331

,0"'0%

3

+~VS

1

CL
,..,~.F

•

22",k,...._MY_L_AR_~.
+-"'VI

RL
101111

J:

VLOGIC

J

lOUT
10kHz
FULL-SCALE

14
-::!:-

",,* ":"

12kf1"*

~k*
47±11IlI

/.

-Vs

~~I~ST

}-

(OPTIONAL)
OFFSET ADJUST
TL/H/568D-1

'Use stable components wllh .low temperature coefficients. See Typical Applications section; .
··O.1,u.F or 1p.F, See "Principles of Operation."

FIGURE 1. Simple Stand-Alone VOltage-to-Frequency Converter
with ± 0_03% Typical Linearity (f = 10 Hz to 11 kHz)
2-690

r-

Absolute Maximum Ratings (Ncite 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
LM131A1LM131
40V
Continuous
Continuous
-0.2Vto +Vs
TMIN
TMAX
-SS'Cto + 12S'C

Supply Voltage
Output Short Circuit to Ground
Output Short Circuit to Vee
Input Voltage
Operating Ambient Temperature Range
Power Dissipation (PD at 2S'C)
and Thermal Resistance (OjN
(H Package) PD

LM231A/LM231
40V
Continuous
Continuous
-0.2Vto +Vs
TMIN
TMAX
-2S'Cto +8S'C

LM331A/LM331
40V
Continuous
Continuous
-0.2Vto +Vs
TMIN
TMAX
O'Cto +70'C

.....
==
w
.....

»
.....
r.....
==
w
.....
.....
r-

:::
N
w
.....

»
......
r-

==

N

670mW
1S0'C/W

°jA
(N Package) PD
°jA
(M Package) PD
°JA
Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (PlastiC)
Metal Can Package (TO-S)
ESD Susceptibility (Note 4)
Metal Can Package (TO-S)
Other Packages

260'C
260'C

1.2SW
100'C/W
1.2SW
8S'C/W

1.2SW
100'C/W

260'C

260'C

W
.....
......

r-

w
==
w
.....
»
......

r-

w
==
w

.....

2000V

soov

SOOV

Electrical Characteristics TA = 2S'C unless otherwise specified (Note 2)
Parameter
VFC Non-Linearity (Note 3)

Typ

Max

Units

4.SV :S: Vs :S: 20V

Conditions

±0.003

±0.01

TMIN :S: TA:S: TMAX

±0.006

±0.02

% FullScale
% FulIScale

±0.024

±0.14

% FullScale

1.00
1.00

1.0S
1.10

kHz/V
kHz/V

:\:30
±20

±1S0
±SO

ppm/'C
ppml"C

0.01
0.006

0.1
0.06

%/V
%/V

VFC Non-Linearity
In Circuit of Figure 1

Vs

=

Conversion Accuracy Scale Factor (~ain)
LM131, LM131A, LM231, LM231A
LM331 , Uil331A
.

VIN

=

Temperature Stability of Gain
LM131/LM231/LM331
LM131A/LM231A1LM331A

TMIN :S: TA :S: TMAX, 4.SV :S: Vs :S: 20V

Change of Gain with Vs

4.SV:S:Vs:S: 10V
10V:S: Vs:S: 40V

1SV, f

=

Min

10 Hzto 11 kHz

-10V, Rs

=

14 kO
0.9S
0.90

=

Rated Full-Scale Frequency

VIN

Gain Stability vs Time
(1000 Hrs)

TMIN:S: TA:S: TMAX

Overrange (Beyond Full-Scale) Frequency

VIN

=

10.0

-10V

kHz
±0.02

% FullScale

10

-11V

%

INPUT COMPARATOR
Offset Voltage
LM131 ILM231 ILM331
LM131A1LM231A1LM331A

TMIN:S: TA:S: TMAX
TMIN :S: TA :S: TMAX

Bias Current
Offset Current
Common-Mode Range

TMIN:S: TA:S: TMAX

2-891

-0.2

±3
±4
±3

±10
±14
±10

mV
mV
mV

-80

-300

nA

±8

±100

nA

Vee- 2.O

V

PI

Electrical Characteristics TA= 25"C unless otherwise specified (Note 2) (Continued)
Parameter

Conditions

Min

Typ

Max

Units

0.63

0.667

0.70

X Vs

±10
200
200

±100
1000
500

nA
nA
nA

10.22

0.5

V

135
136

144
156

/LA
/LA

TIMER
Timer Threshold Voltage, Pin 5
Input Bias Current, Pin 5
All Devices
LM131/LM231/LM331
LM131A1LM231A1LM331A
VSAT PIN 5 (Reset)

Vs = 15V
OV S:VPIN 5 s: 9.9V
VPIN5 = 10V
VPIN5 = 10V
1= 5mA

CURRENT SOURCE (Pin 1)
Output Current
LM131, LM131A, LM231, LM231A
LM331, LM331A

Rs=14kO, VPIN1=0

Change with Voltage

OVS:VPIN 1S:10V

0.2

1.0

/LA

TA=TMAX

0.01
0.02
2.0

1.0
.10.0
50.0

nA
nA
nA

Current Source OFF Leakage
LM131, LM131A
LM231 , LM231A, LM331, LM331A
All Devices

126
116

Operating Range of Current (Typical)

(10to 500)

/LA

REFERENCE VOLTAGE (Pin 2)

Stability vs Temperature

±60

' Voc
Voc
'ppm/DC

Stability vs Time, 1000 Hours

±0.1

%

LM131, LM131A, LM231, LM231A
LM331 , LM331A

1.76
1.70

1.89
1.89

2:02
2.08

, LOGIC OUTPUT (Pin 3)
VSAT

1=5mA
1=3.2 mA (2 TIL Loads), TMINS:TAS:TMAX

OFF Leak8.ge

0.15
0.10
±0.05

0.50
0.40
1.0

V
V
/LA

3.0
4.0
3.0
4.0

4.0
6.0
6.0
8.0

mA
mA

SUPPLY CURRENT
LM131, LM131A, LM231,
LM231 A
LM331, LM331A

Vs=5V
Vs=40V
Vs=5V
Vs=40V

2.0
2.5
1.5
2.0

mA
mA

Note 1: Absolute Maximum Ratings Indicate IImHs beyond which damage to the device meyoccur. DC and AC electrical specifications do not apply when operating,
,the device beyond its specified operating conditions.
Note 2: All specifications apply in the circuit of Figure 3, with 4.0V:S:Vs:S:40V, unless otherwise noted.
Note 3: Nonlinearity Is defined as the deviation offOUT from VIN x (10 kHz/-10 Vocl when the circuit has been 1rimmed for zero error at 10 Hz and at 10 kHz,
over the frequency range 1 Hz to 11 kHz. For lhe liming capaCitor, Or, use NPO ceramic, Teflon., or polyatyrene.
Note 4: Human body model. 100 pF discharged through a 1.5 kO resistor.

2·692

r-----------------------------------------------------------------------------~~

....a:w
....

Functional Block Diagram
Vee'
1---------

I

----------,
, 1

~

I

....w
......

I

....~

1

I
1
1
1

~

• 1

is

~
....

1
1

>......

1 COMPARATOR

I----+-+---ll-I...r
I----+-T""--ll-TH...HOLD

~

~

•

r

CURRENT

2

i'll
'ROUTPUT
ED.ENe':
,
I :-i----,

,

!RS
I
I
I

:: .,

....
......

I,

~

,

REFERENCE

~

a:

....

1-1---t-t--i......e

~

1
1 1
1 _L
I -rei
1 1
- - - - - ____ ,_1 I

~
w

2.

*

Pin numbers apply to 8-pin package. only. See connection diagram for LM231 WM pin numbers.

FIGURE1a

*

w
....

TL/H/56BD-2

fI

2-693

.- r---------------------------------------------------------------------------------,
CW)
CW)

~
;c.-

~."

CW)

N

~

;c.~

....:::E......

Typical Performance Characteristics
(All electrical characteristics apply for the circuit of Figure 3, unless otherwise noted.)
Nonlinearity Error, LM131
Family, as Precision V·to·F
Converter (Figure 3)

=
ffi

" +O.D2

Sl'ECLIMIT

..'

.

1

~ -D.DI

.·8

CW)

.-

Ht.HllllII-tIl&fflIIl-t1lH1tH1l

co

2'_0.D2

1
ID

-D.03
D.DDDI D.DDI D.DI

12

FREOUENCY. kHz

....:::E
;c.-

ID

POWER .SUFFL Y VOLTAGE. Vs

+2.0
+1.&
"'.~ +1.0

..
...

1.924

> 1.922
f:i 1.820
~ 1.11.

i5
:iI
il:

r-I-....

1.914
1.!I12

8.91

8.14 ..................................................

..25

TEMPERATURE. 'C

1-+--+-+--1-+--1

IG

ID

IGO

+75

ffi
~

-0.01
~ -8,02

.

:

-=--

I-

~
;::
'"

IDD

"- r....

5D

ii!

I--'

!i

'1

-&D

S

-D.D4
10

12

-76

-25

FREQUENCY, kHz

>

~

"

2.D

1.1
1.2
1.8

D.4

I

)

1
1

+D.D4

1.!25'C

~+O.03

+12& +15D

r:

0

..

-0.02

:.,.9
:-- ri¥-'
SPEC

!

t"T ~.

1-0.03

~ -D.DI

,.

~

-'

i'" +0.02 t;;;;;; r--~AXI~UM
..... +0.01
111111111'

"/

lD

+J5

Nonlinearity Error, Precision
F-to-V Converter (Figure 6)

I

Ii I
-55'cf

U

+25

TEMPERATURE, ·C

Output Saturation Voltage vs
lOUT (Pin 3)

IfII

21 25 30 31 4D

18

' I r- r- '"'"

l-

V

12D

'+l2&'C

VaUFFLY. V

oS

1/

2.'

.... ~ F-

Input Current (Pins 6, 7) vs
Temperature

liD

3l

ID II

lD 15 2D 2& 30 35 4D

C

~ -0.03

Power Drain vs VSUPPLY

~
~~

5

VSUFFLY. V

+0.01

'"
:i

5

-U!C,

~

+125 +1&0

li!+O.DZ

fREOUENCY. kHz

.JI'C

"'i III!.

+0.14

I-+-I-t--I--I--I
4D

+25

~ to.03

~ ....., I-+r-~_fo=::bo"""'-I
i i -am t--t--t--t---t-+---l
:; -D.I3 t--t--t--t-+--t---l
2'

TYPICAL

101"-

2DO

D ....od::--+--t--+--+--I

-D.D4

-1.5

Nonlinearity Error, LM131
(Figure 1)

t-+-t--t--t--t-rl
t-+-t--t--t--t"i-l
f5 +D.DI t--t--t--t-+--tf-l
~

"D.5
-1.D

,,~~

IJIIIIII

IA "III

TEMPERATURE. ·C

100 kHz Nonlinearity Error,
LM131 Family (Figure 4)
+OlM

~

I~

~f.~i_

-2.D

1.91D
...75

+12&

I~, l.illII ~

I--l - I--

+1.5
D

co

I-

t'-- '"

1.918

~ +D.D3
li! +Dm

51DI52D213D354D

Outpu~ Frequency vs
VSUPPLY

1.928

+J&

D.DDO

IDD

1.92&

+25

i-'" ~

D.DDI

1.93D

lD.D4

-&5 -25

SPEC LIMIT
0.D1D

co

VREF vs Temperature,
LM131A

r-r-I""'1r-1....,.-r-i-"'T""

ID.OI

.~

1.1

...

!

FREOUENCY. kHz

Frequency vs Temperature,
LM131A

CW)

'">", .
!: DAI5

.::;
'"

!:

SPEC LIMIT

-D.D4

'. D.D2D

m+0.01 HtHIII-ItllIIHllIIIf-fflilHifllll-tHII
~

1....03

oml

Htllt-tttlIIHtlllll-fflIIHilNtHllI

",'

+0.81

S D
~~:

Nonlinearity VB Power Supply
Voltage

+0.03 mlllll'"lTIIIIl"ITlllrTTlllrnTlrTIIIIIII

1 '1

+0.14
~ +0.83
+D.D2

.-

Nonlinearity Error, LM131
Family

I"

,.

"
, ,·1

-D.D4
za

3D

laUT,1IIA

4D

10

&D

12

FREOUENCY. kHz

TLlH/568D-3

2-694

Typical Applications (Continued)
PRINCIPLES OF OPERATION OF A SIMPLIFIED
VOLTAGE-TO-FREQUENCY CONVERTER
The LM131 is a monolithic circuit designed for accuracy and
versatile operation when applied as. a voltage-to-frequency
(V-to-F) converter or as a frequency-to-voltage (F-to-V) converter. A simplified block diagram of the LM131 is shown in
Figure 2 and consists of a switched current source, input
comparator, and 1-shot timer.

DETAIL OF OPERATION, FUNCTIONAL BLOCK
DIAGRAM (FIGURE tal
The block diagram shows a band gap reference which provides astable 1.9 Voe output. This 1.9 Voe is well regulated
over a Vs range of 3.9V to 40V. It also has a: flat, low temperature coefficient, and typically changes less than Y:z %
over a 100'C temperature change.
The current pump circuit forces the voltage at pin 2 to be at
1.9V, and causes a current i=1.90V/Rs to flow. For
Rs = 14k, i = 135 ,..A. The precision current reflector provides a current equal to i to the current switch. The current
switch switches the current to pin 1 or to ground depending
on the state of the Rs flip-flop.
The timing function consists of an Rs flip-flop, and a timer
comparator connected to the external RICI network. When
the input comparator detects a voltage at pin 7 higher than
pin 6, it sets the -RS flip-flop which turns ON the current
switch and the output driver transistor. When the voltage at
pin 5 rises ,to % Vee, the timer comparator causes the Rs
flip-flop to reset. The reset transistor is then turned ON and
the current switch is turned OFF.

The operation of these blocks is best understood by going
through the operating cycle of the basic V-to-F converter,
Figure 2, which consists of the simplified block diagram of
the LM131 and the various resistors and capacitors connected to it.
The voltage comparator compares a positive input voltage,
V1, at pin 7 to the voltage, Vx, at pin 6. If V1 is greater, the
comparator will trigger the 1-shot timer. The output of the
timer will turn ON both the frequency output transistor and
the switched current source for a period t =1.1 RPI' During
this period, the current i will flow out of the switched current
source and pr~vide a fixed amount of charge, Q = i x t, into
the capacitor, CL. This will normally charge Vx up to a higher
level than V1. At the end of the timing period, the current i
will turn OFF, and the timer will reset itself.

However, if the input comparator still detects pin 7 hIgher
than pin 6 when pin 5 crosses % Vee, the flip-flop will not
be reset, and the current at pin 1 will continue to flow, in its
attempt to make the voltage at pin 6 higher than pin 7. This
condition will usually apply under start-up conditions or in
the case of an overload voltage at signal input. It should be
noted that during this sort of overload, the output frequency
will be 0; as. soon as the signal is restored to the working
range, the output frequency will be resumed.
The output driver transistor acts to saturate pin 3 with an
ON resistance of about 50n. In case of overvoltage, the
output current is actively limited to less than 50 mAo

Now there is no current flowing from pin 1, and the capacitor CL will be gradually discharged by RL until Vx falls to the
level of V1. Then the comparator will trigger the timer and
start another cycle.
The currentflowing into CL is exactly lAVE = i X (1.1 X RICt>
X f, and the current flowing out of CL is exactly Vx/RL ""
V,N/RL. If Y,N is doubled, the frequency will double to maintain this balance. Even a simple V-to-F converter can provide a frequency precisely proportional to its input voltage
over a wide range of frequencies.

.,

The voltage at pin 2 is regulated at 1.90 Voe for all values of
i between 10 ,..A to 500 ,..A. It can be used as a voltage
reference for other components, but care must be taken to
ensure that current is not taken from it which could reduce
the accuracy of the converter.

c,

L

.:....---'llllv----......l~

PRINCIPLES OF OPERATION OF BASIC VOLTAGETO-FREQUENCY CONVERTER (FIGURE 1)
The simple stand-alone V-to-F converter shown in Figure 1
includes all the basic Circuitry of Figure 2 plus a few components for improved performance.
A resistor, R'N= 100 kn±10%, has been added in the path
to pin 7, so that the bias current at pin 7 (- 80 nA typical)
will cancel the effect of the bias current at pin 6 and help
provide minimum frequency offset.
The resistance Rs at pin 2 is made up of a 12 kG fixed
resistor plus a 5 kO (cermet, preferably) gain adjust rheostat. The function of this adjustment is to trim out the gain
tolerance of the LM131, and the tolerance of RI, RL and Ct.

VLOGIC

FREQUENCY
OUTPUT

TLiH/5680-4

FIGURE 2_ Simplified Block Diagram of Stand-Alone
Voltage-la-Frequency Converter Showing LM131 and
External Components

2-695

•

..
CO)

~
;c

..
..

:I
:!.....
~

:!
;c

..
:!.....
....
~..
..
:!
CO)

N

CO)

CO)

~-----------------------------------------------------------------------------------------,

Typical Applications

(Continued)
For best results, all the components should be stable lowtemperature-coefficient components, such a.smetal-film resistors. The capacitor should have low dielectric absorption;
dependirg on the temperature characteristics desired,NPO
cerainic, polystyrene, Teflon or polypropylene are best
suited.
. .

The averagl;l current fed into the op amp's summing pOint
(pin 2) is i X (1.1 R,Ct) x f which is perfectly balanced with
-VIN/RIN. In this circuit, the voltage offset of the LM13t
input comparator does not affect the offset or accuraby of
the V-to~F converter as it does in the stand-alone V-to-F
converter; nor does the LM131 bias current or offset current. "1stead, the offset voltage and offset current of the
operational amplifier are the only limits on how small the
signal can be accurately converted. Since op amps with
voltage offset well below 1 mV and offset currents well below 2 nA are available at low cost, this circuit is recommended for best accuracy for small signals. This circuit also' responds immediately to any change of input signal (which a
stand-alone circuit does not) so that the output frequency
will be an accurate representation of VIN, as quickly as 2
output pulses' spacing can be measured.

A capacitor CIN is added from pin 7 to ground to act as a
filter for VIN. A value of 0.Q1 p.F to 0.1 p.F will be adequate in
most cases; however, in cases where better filtering is required, a 1 p.F capacitor can be used. When the RC time
constants are matched at pin 6 and pin 7, a voltage step at
VIN will cause a step change in fOUT. If CIN is much less
than Ct., a step at VIN may cause fOUT to stop momentarily.
A 470 resistor, in series with the 1 p.F CL, is added to give
hysteresis effect which helps the input comparator provide
the excellent linearity (0.03% typical).

In the precision 'mode, excellent linearity is obtained because the current source (pin 1) is always at ground potential and that voltage does not vary with V,N or foUT. (In the
stand-alone V-to-F converter, a major cause of non-linearity
is the output impedance at pin 1 which causes i to change
as a function of VIN).
The circuit of Figure 4 operates in the same way as Rgure 3,
but with the necessary changes for high speed operation.

DETAIL OF OPERATION OF PRECISION V-TO-F
CONVERTER (FIGURE 3)
In this circuit, integration is performed by using a conventional operational amplifier and feedback capacitor, CF.
When the integrator's output crosses the nominal threshold
level at pin 6 of the LM131, the timing cycle is initiated.

Vs
ll1k'ID!1

IIlk ,ID!1" "

r-¥o,."..... VLDGIC

'1_

...._---:mz

~

. ',' V

:f

IDDk ,,"" ":'

RHEOSTAT
GAIN
ADJUST

CF
D.DDbF
MYLAR

--U--.

-I~U - - ' \ M - - - -....

FULL SCALE

FULL-SCALE

I."

Uk

fOUT

=

-V,N. Rs • .2..
2.09V R'N

RtCt

lN4D02

TL/H/5680-5

'Use slable componenls wlih low temperature coefficients. See Typical Applications section.
"This resistor cen be 5 k!l or 10 k!l for VS=8V to 2W. but must be 10 k!l for VS=4.SV to BV.
'''Use low offset voltage and low offset current op amps for AI: recommended types LM108, LM30BA,

LF411A

FIGURE 3. Standard Test Circuit and Applications Circuit, PreCision Voltage-to-Frequency Converter

2-696

r-

Typical Applications (Continued)

Co)

DETAILS OF OPERATION, FREQUENCY-TOVOLTAGE CONVERTERS (FIGURES 5 AND 6)

0.1 second time constant. and settling of 0.7 second to
0.1 % accuracy.
In the precision circuit. an operational amplifier provides a
buffered output and also acts as a 2-pole filter. The ripple
will be less than 5 mV peak for all frequencies above 1 kHz.
and the response time will be much quicker than in Figure 5.
However. for input frequencies below 200 Hz. this circuit will
have worse ripple than Figure 5. The engineering of the filter
time-constants to get adequate response and small enough
ripple simply requires a study of the compromises to be
made. Inherently. V-to-F converter response can be fast.
but F-to-V response can not.

In these applications. a pulse input at fiN is differentiated by
a CoR network and the negative-going edge at pin 6 causes
the input comparator to trigger the timer circuit. Just as with
a V-to-F converter. the average current flowing out of pin 1
is IAVERAGE = i x (1.1 RtCtl x f.
In the simple circuit of FIGURE 5. this current is filtered in
the network RL = 100 kn and 1 J.LF. The ripple will be less
than 10 mV peak. but the response will be slow. with a

Vs

.....
r-

....
==

....
......
rCo)

~
N

....
Co)

~

~

N

....
......
rCo)

3:

Co)
Co)

....

RI

•.'.tl"-

1a.t1~·*

3:
....
....
J>

~
r-

....01\1\"'"_

3:
Co)

....
Co)

VLDGIC

---0 :~~H'

1-:-.....

FULL SCALE

III·

·Use stable components with low temperature coefficients.
See Typical Applications section.

OAIN
ADJUST
CF
41D,F

"This resistor can be 5 kl'l or 10 kl'l for VS=BV to 22V.

-~~O-~~~----~--~
FULL SCALE

but must be 10 kl'l for VS=4.5V to BV.
'''Use low offset voltage and low offset current op amps for AI:
recommended types LF411 A or LF356.

II14DDZ

II

TUH/56BO-6

FIGURE 4. Precision Voltage-to-Frequency Converter,
100 kHz Full-Scale, ±0.03% Non-Linearity
+VS-+4,5VTO.ZOV

+Vs= +15V

,,.

"

&.11k! 1"-

410pf

tl.--1H-=---~

'I. -f .....---------'-1
.I1../"l.lL

Cl,41Gpf

lOUT
~"",-"",--VOUT

12k''''

's

's {

{".......
Sk'

Sk'

TUH/5690-7
VOUT

= fiN

X 2.09V

x

RL

As x (RM>

VOUT = -fiN X 2.09V

'Use stable components wHh low temperatura coefficients.

RF

x As x (RM>

TLlH/56BO-8

(Vs - 2V)

SELECTRx=~

FIGURE 5. Simple Frequency-to-Voltage Converter,
10 kHz Full-Scale, ± 0.06% Non-Linearity

'Use stable components with low temperature coefficients.

FIGURE 6. Precision Frequency·to·Voltage Converter,
10 kHz Full·Scale with 2·Pole Filter, ±0.01%
Non-Linearity Maximum
2-697

~
(I')
(II)

r-----------------------------------------------------------------------------------------------,

~
...I
c(

....

Typical Applications

(Continued)

Light Intensity to Frequency Converter

~

(II)
(II)

+SVTO +15V

~
...I

....
~

Uk

(II)

N

:3
~
~

(II)

N
~

...J
....
~

(II) .
~

TLlH/5680-9

~

...J

'L 14F-1, L14G-1 or L14H-1, ph010 transistor (General Electric Co.) or similar

~
~

(II)
~

~
...J

Temperature to Frequency Converter

v,

"133'

1=---1-...- . fOUToTEMP
".,lh '''AI "HarK
c,
a.al~F

TLlH/5690-10

Basic Analog-ta-Dlgltal Converter Using
Voltage-ta-Frequency Converter

Long-Term Digital Integrator Using VFC

'V,

'VI

aATA

}

amUT

Ta
CDWUTER

v,.

TLlH/588D-11

TLlH/588D-12

2-698

Typical Applications (Continued)
Analog-to-Digital Converter with Microprocessor
'VI

TLlH/S680-13

Remote Voltage-ta-Frequency Converter with 2-Wire Transmitter and Receiver
FREQUENCY
OUTPUT

TL/H/S680-14

Voltage-to-Frequency Converter with Square-Wave Output Using + 2 Flip-Flop
+VS' +4.0VOC TO +15Voc
CLR

PRE

+VS

47k
VFC
CIRCUIT
USING
LM331

fI

IOUT=F/2
SQUARE
WAVE

Tl/H/S680-1S

Voltage-to-Frequency Converter with Isolators
+VS

+VLOGIC

Ik
TO COMPUTER
OR
COUNTER
TO F·TIJ.V
CONVERTER
UIINO LMI31

+--D*-- ~~
OPTOISOLATOR

4N28 DR

SIMILAR

TL/H/S680-16

2-699

Typical Applications (Continued)

£."

VOltage-to-Frequency Converter with Isolators
+VS
+VLDGIC

>4,...--11>0--'OUT

L--,r--,'OUT

COMPARATOR
WITH
HVSTERESIS

TL/H/56SD-17

VOltage-to-Frequency Converter with Isolators.
+VS
+VLOGIC

TELEMETRV
USING
RF LINK

TLlH/5680-18

Voltage-to-Frequency Converter with Isolators
+VS
+VLOGIC

Ik
TO COMPUTER
OR
TO COUNTER
OR
TO F·TO·V
CONVERTER
USING LMI3I

TLlH/5680-19

2-700

Connection Diagrams
Metal Can Pllclcage

Dual·ln·Llne Package

\Is

CURRENT
OUTPUT

I

Vs

REFERENCE
CURREflT

2

COMPARATOR
INPUT

FREOUENCY
OUTPUT

3

THRESHOLD

RIC

GND

Notr. Metal case is connecled 10 pin 4 (GND.)

TL/H/5680-20

TOP VIEW

TLlH/5680-21

Order Number LM131H/883 or LM131AH/883
See NS Package Number H08C

Order Number LM231AN, LM231N, LM331AN,
or LM331N
See NS Package Number N08E

Srnall-outllne Package
Current
Output
Reference
Curront
NC
Frequency
Output

14

NC
NC
NC
Vs
Comparator
Input
NC

GND
NC

Ric

Threshold
TL/H/5680-24

Top View

Order Number LM231WM
Sea NS Package Number M14B

2·701

LM131A/LM131/LM231A/LM231/LM331A/LM331

.w

.~~

v •

W
:::r

oJ;
;::;;:r

CD

3

an'

-L-c,

~'

0 ..

A1

3

o"JI~

~~I(UltlJ%

r [:9
":'

~

o

..... -

~J,f

il ~

~.

I

11111111

~ ~---.lIIll1 'II

v - ......

=r

I

111I

l

~:

.n

FR£~=:~·"';"'___""'''t.-I--f~~j~~~~~~~~~~=~~~~~~~§~
R'.

~

.-iH-'H'-,

"

---l~:-:---;:l::i==+==P17:;;

RIC.!...'
COMPARATOR 7

INPUT

THRESHOLD.!..--==t-""1r::::;===--_H~_t-1

~

m

'i'
r.l

...

~

:~:.

RZ.<

'DOS

~,Jy'

,...;,

~~ 'i'~

Section 3
Digital-to-Analog
Converters

•

Section 3 Contents
Digital-to-Analog Converters Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-to-Analog Converters Selection Guide ..........•...............•...............
DAC08001DAC0801 IDAC0802 8-Bit DI A Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC0808/DAC0807/DAC0806 8-Bit DI A Converters . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . .
DAC0830/DAC0831/DAC0832 8-Bit ""p Compatible Double-Buffered DI A Converters. . . . . .
DAC0854 Quad 8-Bit Voltage-Output Serial DI A Converter with Readback . • . . . . . . . . . . . . . . .
DAC0890 Dual 8-Bit ""P-Compatible DI A Converter. . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . • . . .
DAC1006/DAC1007/DAC1008 ""p Compatible, Double-Buffered D/A Converters..........
DAC1 020/DAC1 021 IDAC1 022. 10-Bit Binary Multiplying DI A Converters. . . . . . . . . . . . . . • . . .
DAC1220/DAC1222 12-Bit Binary Multiplying DI A Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC1054 Quad 1O-Bit Voltage-Output Serial DIA Converter with Readback. . . . . . . . . . . . . . . .
DAC1208/DAC1209/DAC121 0/DAC1230/DAC1231 IDAC1232 12-Bit ""p Compatible
Double-Buffered DI A Converters ....... ~ . . . . . . . . . • . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . .
DAC1218/DAC1219 12-Bit Binary Multiplying DI A Converters .....•.....•.•......••.••.. ,

3-2

3-3
3-4
3-6
3-15
3-23
3-41
3-53
3-63
3-83
3-83
3-93
3-105
3-121

t!lNational Semiconductor

Definition of Terms
DI A Converters
Differential Nonlinearity: Ideally, any two adjacent digital
codes correspond to output analog voltages that are exactly
one LSB apart. Differential non-linearity is a measure of the
worst case deviation from the ideal 1 LSB step. For example, a DAC with a 1.5 LSB output change for a 1 LSB digital
code change exhibits % LSB differential non-linearity. Differential non-linearity may be expressed in fractional bits or
as a percentage of full scale. A differential non-linearity
greater than 1 LSB will lead to a non-monotonic transfer
function in a DAC.

MSB (Most Significant Bit): In a binary coded system this
is the bit that has the largest value or weight. Its value is one
hal! of full scale.
Multiplying DAC: In a sense, every DAC is a multiplying
DAC since the output voltage (or current) is equal to the
reference voltage times a constant determined by the digital
input code divided by 2n (n is the number of bits of resolution). In a two quadrant multiplying DAC the reference voltage or the digital input code can change the output voltage
polarity. I! both the reference voltage and the digital code
change the output voltage polarity, four quadrant multiplication exists.
Offset Error (Zero Error): The output voltage that exists
when the input digital code is set to give an ideal output of
zero volts. All the digital codes in the transfer curve are
offset by the same value. Offset error is usually expressed
in LSBs.

Gain Error (Full Scale Error): The difference between the
output voltage (or current) with full scale input code and the
ideal voltage (or current) that should exist with a full scale
input code.
Gain Temperature Coefficient (Full Scale Temperature
Coefficient): Change in gain error divided by change in
temperature. Usually expressed in parts per million per degree Celsius (ppm/'C).
Integral Nonlinearity (Linearity Error): Worst case deviation from the line between the endpoints (zero and full
scale). Can be expressed as a percentage of full scale or in
fractions of an LSB.
LSB (Least-Significant Bit): In a binary coded system this
is the bit that carries the smallest value or weight. Its value
is the full scale voltage (or current) divided by 2n, where n is
the resolution of the converter.
Monotoniclty: A monotonic function has a slope whose
sign does not G:hange. A monotonic DAC has an output that
changes in the same direction (or remains constant) for
each increase in the input code. The converse is true for
decreasing codes.

Power Supply Rejection (Power Supply Sensitivity): The
sensitivity of a converter to changes in the dc power supply
voltages.
Resolution: The sf)1allest analog increment corresponding
to a 1 LSB converter code change. For converters, resolution is normally expressed in bits, where the number of analog levels is equal to 2n.
!>ettJlng Time: The.time from a change in input code until a
DAC's output Signal remains within ± % LSB (or some other
specified tolerance) of the final value.

•
3-3

tflNational Semiconductor

01 A Converter Selection Guide

Part
No.

:

Resolution
(Bits)

Linearity

@25'C
% (Max)

Settling
Time

(+%LSB)

Supplies
(V)

Temperature
Range·

M

Package

I

C

Comments

ADC0852

8

0.19

5

•

•

8·PinDIP

DAC, Comparator,
Serial Input

ADC0854

8

0.19

5

•

•

14·Pin DIP

DAC, Comparator,
Serial Input

DAC0800

8

0.19

100 ns

±5to ±15

•

16·PinDIP
16·PinS.C.

High·Speed
Multiplying

DAC0801

8

0.39

100 ns

±5to ±15

•

16·PinDIP
16·PinS.C.

High·Speed
Multiplying

DAC0802

8

0.10

100 ns

±5to ±15

•

16·Pin DIP
16·PinS.C.

High·Speed
Multiplying

DAC0806

8

0.78

150 ns

±5to±15

•

16·PinDIP
16·PinS.C.

Multiplying

DAC0807

8

0.39

150 ns

±5to±15

•

16·Pin DIP
16·PinS.C.

Multiplying

DAC0808

8

0.19

150 ns

±5to ±15

•

16·Pin DIP
16·PinS.C.

Multiplying

•

20·PinDIP
20·PinS.C.
20·PinPCC

II-P Compatible
4·Quadrant
Multiplying

•

20·PinDIP

II-P Compatible
4·Quadrant
Multiplying

•

20·PinDIP
20·PinS.C.
20·Pin PCC

II-P Compatible
4-Quadrant
Multiplying

•

20·PinDIP
20·PinS.O.

Quad Serial
DACwith
Readback

•

20·Pin DIP

Dual Voltage
CutputDAC

•

DAC0830

8

0.05

1 II-s

5to 15

DAC0831

8

0.10

1l1-s

5to 15

DAC0832

8

0.20

1l1-s

5to 15

DAC0854

8

0.19

2.711-s

5

DAC0890

8

0.19

2.711-s

5to 15

·DAC1001

10

0.1

500ns

5to 15

•

24·Pin DIP

II-P Compatible
Double Buffered

DAC1002

10

0.2

500ns

5to 15

•

24·PinDIP

II-P Compatible
Double Buffered

DAC1006

10

0.05

500 ns

5to 15

•

20·PinDIP

II-P Compatible
Double Buffered

DAC1007

10

0.1

500 ns

5to 15

•

20·PinDIP

II-P Compatible
Double Buffered

DAC1008

10

0.2

500ns

5to 15

•

20·PinDIP

II-P Compatible
Double Buffered

3·4

•
•

•

c
.......

01 A Converter Selection Guide (Continued)
Part
No.
DAC1020
DAC1021

Resolution
(Bits)
10
10

:J>

Unearlty
@25"C
% (Max)

Settling
Time
(+Yz LSB)

Supplies
(V)

0.05

500ns

5to 15

0.1

500ns

Temperature
Range·
M

10

0.2

500ns

5to 15

DAC1054

10

0.02

3.7 )J.s

5

C

•

•

•

5to 15

DAC1022

I

•
•

•

•

•

Package

Comments

16-Pin DIP

4-Quadrant
Multiplying

16-Pin DIP

4-Quadrant
Multiplying

16-Pin DIP

4-Quadrant
Multiplying

24-Pin DIP
24-PinSO

Quad Serial DAC
with Readback

DAC1208

12

0.018

1 )J.s

5to 15

•

•

24-Pin DIP

)J.P Compatible
4-Quadrant
Multiplying

DAC1209

12

0.024

1 )J.s

5to 15

•

•

24-Pin DIP

)J.P Compatible
4-Quadrant
Multiplying

DAC1210

12

0.05

1 )J.s

5to 15

•

•

24-Pin DIP

)J.P Compatible
4-Quadrant
Multiplying

DAC1218

12

0.012

1 )J.s

5to 15

•

•

18-PinDIP

4-Quadrant
Multiplying

DAC1219

12

0.024

1 )J.s

5to 15

•

•

18-Pin DIP

4-Quadrant
Multiplying

DAC1220

12

0.05

500 ns

5to 15

0

•

18-Pin DIP

4-Quadrant
Multiplying

DAC1222

12

0.2

500ns

5to 15

•

•

18-Pin DIP

4-Quadrant
Multiplying

DAC1230

12

0.Q18

1 )J.s

5to 15

•

•

20-PinDIP

)J.P Compatible
4-Quadrant
Multiplying

DAC1231

12

0.024

1 )J.s

5to 15

•

•

20-PinDIP

)J.P Compatible
4-Quadrant
Multiplying

DAC1232

12

0.05

1 )J.s

5to 15

•

•

20-Pin DIP

)J.P Compatible
4-Quadrant
Multiplying

'Ambient temperature range for "M" is -S5"C to + 125"C. "I" is -2S"C to +8S"C or -40"C to +8S'C, "C" O"C to +70'C.

3-5

o
o

~
i....

rJ)

(I)

ii'

2-

O·
:s

G)

c

c:
(I)

tflNational Semiconductor

DAC0800/DAC0801/DAC0802 8-Bit Digital-to-Analog
Converters
General Description
The DACOBOO, DACOB02, DAC0800C, DAC0801C and
DAC0802C are a direct replacement for the DAC-08, DAC08A, DAC-08C, DAC-08E and DAC-08H, respectively.

The DACOBOO series are monolithic B-bit high-speed current-output digital-to-analog converters (DAC) featuring typical settling times of 100 ns. When used as a multiplying
DAC, monotonic performance over a 40 to 1 reference cur-'
rent range is possible. The DACOBOO series also features
high compliance complementary current outputs to allow
differential output voltages of 20 Vp-p with simple resistor
loads as shown in Figure 1. The reference-to-full-scale current matching of better than ± 1 LSB eliminates the need for
full-scale trims in most applications while the nonlinearities
of better than ± 0.1 % over temperature minimizes system
error accumulations.

Features
•
•
•
•
•
•
•
•
•
•
..

The noise immune inputs of the DACOBOO series will accept
TTL levels with the logic threshold pin, VLC, grounded.
Changing the VLC potential will allow direct interface to other logic families. The performance and characteristics of the
device are essentially unchanged over the full±4.5V to
± lBV power supply range; power dissipation is only 33 mW
with ± 5V supplies and is independent of the logic input
states.

100 ns
Fast settling output current
±1 LSB
Full scale error
±0.1%
Nonlinearity over temperature
±10 ppml"C
Full scale current drift
-10V to +lBV
High output compliance
Complementary current outputs
Interface directly with TTL, CMOS, PMOS and others
2 quadrant wide range multiplying capability
Wide power supply range
±4.5V to ±18V
Low power consumption
33 mW at ± 5V
Low cost

Typical Applications
10V
DIGITAL INPUTS
'MSI

YYYY?YY?
10V O-,\1\5k,..,..-t 145 I

7 I

10k

~

10k

lOUT

B 10 11 12 4
[
-

}

DACOIDO

ik
"""'Wll""'"lii

~

p--

LSI \

VDUT TO 20 Vp'p

~3__~16~_1~3__~1~2~::----~-o

~ILLc~ tJ·~

- rJ1.F

r-

rour
TLlH/5686-1

FIGURE 1. ± 20 Vp-p Output Digital-to-Analog Converter (Note 4)

Ordering Information
Non-Linearity
±O.l%FS
±0.19% FS
±0.19% FS
±0.39%FS

Order Numbers

Temperature
Range
O·C S; TA S; +70·C
-55·C S; TA S; +125·C
COC S; TA S; +70·C
COC S; TA S; +70·C

J Package (J16A)*
DAC0802LCJ
DAC0800W
DAC0800LCJ

DAC-08HQ
DAC-08Q
DAC·08EQ

'DevIces may be ordered by using either order number.

3-6

N Package (N16A)*

SO Package (M16A)

DAC0802LCN

DAC-08HP

DAC0802LCM

DACOBOOLCN
DACOBOl LCN

DAC-08EP
DAC-OBCP

DAC0800LCM
DAC0801LCM

Absolute Maximum Ratings

(Note 1)
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V+ - V-)
±1BVor36V
Power Dissipation (Note 2)
500mW
Reference Input Differential Voltage
V- toV+
(V14to V15)
Reference Input Common-Mode Range
V- toV+
(V14, V15)
Reference Input Current
5mA
V- to V- plus 36V
Logic Inputs
Analog Current Outputs (VS - = -15V)
4.25 mA
ESD Susceptibility (Note 3)
TBDV
Storage Temperature
-65·Cto + 150·C

260·C
300·C
215·C
220·C

Operating Conditions (Note 1)
Temperature (TA)
DACOBOOL
'DACOBOOLC
DACOB01LC
DACOB02LC

Min

Max

Units

-55
0
0
0

+125
+70
+70
+70

·C
·C
·C

·c

Electrical Characteristics

The following specifications apply for Vs = ± 15V, IREF = 2 mA and TMIN 5: T A 5:
T MAX unless otherwise specified. Output characteristics refer to both lOUT and lOUT.
Symbol

Parameter

Min
B
B

IReSOlullOn
Monotonicity
Nonlinearity

ts
tPLH,
tPHL
TCIFS
VOC
IFS4
IFSS
Izs

Settling Time

DAC0800L/
DAC0800LC

DAC0802LC

Conditions

To ± Yo LSB, All Bits Switched
"'ON"' or "'OFF"', TA= 25·C
DACOBOOL
DACOBOOLC
TA=25·C

Typ

:

100

Max Min
B
B
B
B
±0.1

IFSR

VIL
VIH

Logic Input Levels
Logic "'0"
Logic "'1"

IlL
IIH

Logic Input Current
Logic "'0"'
LogiC "'1"

VIS
VTHR

Logic Input Swing
Logic Threshold Range

V-= -5V
V-= -BVto -1BV

0
0

0.1
2.0
2.0

1.0
2.1
4.2

2.0
VLC=OV
-10V:S:VIN:S: +O.BV
2V:S:VIN:S: + 1BV
V-=-15V
Vs= ±15V

Reference Bias Current
Reference Input Slew Rate (Figure 12)
4.5V:s:V+ :S:1BV
PSSIFS+ Power Supply Sensitivity
-4.5V:S:V-:S:1BV
PSSIFSIREF=1mA
Power Supply Current
Vs= ±5V,IREF=1 mA
1+
1115
dlldt

0
0

±0.39

Bits
Bits
%FS

150

ns
ns
ns

35
35
±10

60
60
±50
1B -10

35
35
±10

60
ns
60
ns
±80 ppml"C
1B
V

1.99

2.04 1.94

1.99

2.04

rnA

±1

±B.O

±2

±16

",A

0.2
2.0
2.0

2.0
2.1
4.2

0.2
2.0
2.0

4.0
2.1
4.2

IJoA
rnA
rnA

O.B

V
V

-2.0
0.002

-10
10

1B -10
13.5 -10
-3.0
-1.0

1B
13.5
-3.0

,.A
,.A
V
V

0
0

O.B

4.0

:

135
150

2.0

B.O
0.0001 0.01
0.0001 0.01

Units

Max

100
100

2.0

-2.0 -10
-2.0
0.002
0.002 10
-10
1B -10
-10
13.5 -10
..,1.0 ...,.3.0
-1.0
4.0

Typ
B
B
100

0.8

VLC=OV

DAC0801LC

Max Min
B
B
B
B
±0.19

135

Propagation Delay
Each Bit
35
60
All Bits Switched
35
60
Full Scale Tempco
±10 ±50
-10
Output Voltage Compliance Full Scale Current Change
1B -10
 20 M!l Typ
Full Scale Current
VREF= 10.000V, R14= 5.000 k!l 1.9B4 1.992 2.000 1.94
R15 = 5.000 k!l, TA= 25·C
Full Scale Symmetry
±0.5 ±4.0
IFS4- IFS2
Zero Scale Current
Output Current Range

Typ
B
B

-10
10

B.O
0.0001 0.01
0.0001 0.01

4.0

,.A

8.0
0.0001
0.0001

0.01
0.01

mAllJos
%/%
%/%

3.B
2.3
-4.3 -5.B

2.3
-4.3

3.B
-5.B

2.3
-4.3

3.B
-5.B

rnA
rnA

2.4
3.B
-6.4 -7.B

2.4
-6.4

3.B
-7.B

2.4
-6.4

3.B
-7.B

rnA
mA

2.5
3.B
-6.5 -7.B

2.5
-6.5

3.B
-7.B

2.5
-6.5

3.B
-7.B

rnA
rnA

Vs=5V, -15V,/REF=2mA
1+
1-'
Vs= ± 15V,IREF=2 rnA
/+
/-

3-7

Electrical Characteristics (Continued)
The following specifications apply for Vs = ± 15V, IREF
characteristics refer to both lOUT and lOUT.
Symbol

Parameter

= 2 rnA and TMIN s:
DAC0802LC

Conditions

Min
Po

Power Dissipation

±5V, IREF=1 rnA
5V,-15V, IREF=2 rnA
±15V, IREF=2 rnA

Typ
33
lOB
135

Max'
48
136
174

TA

s:

TMAX unless otherwise specified. Output

DAC0800LI
DAC0800LC
Typ
Min
Max
33
4B
lOB
136
135
174

DAC0801LC
Typ
33
108
135

Min

Units

,Max
48
136· .:
174

rnW
rnW
rnW

Note 1: Absoiute Maximum Ratings Indicate limits beyond which damage to the device may occur. DC and AC electrical specHicatlons do not apply when operating
the device beyond its specified operating conditions.
Note 2: The maximum junction temperature of the DAC0800. DACOS01 and DAC08021s 125"C. For operating at eievated temperatures. devices in the Dual-in-Line
J package must be derated based on a thermal resistance of 1OO'C/W. junclion-Io-ambient 17S·C/W for the molded Dual-in-Line N peckage and 100'C/W for the
Small Outiine M package.
Note 3: Human body model. 100 pF discharged through a 1:5.kn resistor.
Note 4: Pin-out numbers for the DAC080X represent the Dual-in-Line package. The Small Outiine package pin-out differs from the Dual-In-Une package.

Connection Diagrams
Dual-In-Llne Package
THRESHOLD 1
CONTROL. VLC.

Small Outline Package

y+

16 COMPENSATION

•

VREF(+)

15 VREFH

'.lOuT

1
2

VREF<-)
COt.lPENSATI

./
./

!

I

::

lD

"'!;"

leD

!;

"

I LS8-IBnA

200
150

~

;:

.~

100
50
0
0.010,2 0.05.0.1 0,02 0.5 I

o

2

12
10
8
8
4
2
0
-2
-4
-6
-8
-10
-12
-14

5 10

R14- R15-lk
RL ~ SOD
ALL 81TS "ON"
VRI5 - OV

./
I"'-

";'0.1

0.2

IFS - OUTPUT FULL SCALE CURRENT (mAl

IREF - REFERENCE CURRENT (mAl

~

2

1\

0.5

10

FREQUENCV (MHz)
Curve 1: Cc= 15 pF, VIN=2 Vp·p
centered atIY.
Curve 2: Cc= 15 pF, VIN=50 mVp-p
centered at 200 mY.
Curve 3: Cc=O pF, VIN=IOO mVp-p
at OV and applied through 50 neon·
nected to pin 14.2V applied to A14.

4
. 3.6

1

Reference Amp
Common-Mode Range

.

i:l

,....

!;

"
I

5.>

.2.B
2.4
2
1,6
'1.2
0,1

2.B
2,4
2.2
2

TA - TMIN TO TMAX
ALL BITS·"ON" '1

"Il

ffi

. Logic Input Current
vs Input Voltage

I I
I I

~ ~::
IRE~= limA f-

~

Il

IRE~"O~mA-

D.4

2

6

10

14 IB

VIS - REFERENCE COMMON·MOOE VOLTAGE (VI

i'o

1

.....

O,B
0.&
0,4
0,2

o

o
-2

r-.

.; 1.4
I
1.2

V=-15V -V--5V
+V"15V
IREF =2 mA

-14 -10 -6

VTH - VLC vs Temperature

-50

-12-10-8-6-4-202 4 6 81012141618

50

100

150

TA - TEMPERATURE ('CI

Vi - LOGIC INPUT VOLTAGE (VI

Note. Positive common-mode range is
always (V +) - 1.5V

Output Current vs Output
Voltage (Output Voltage
Compliance)
2.B

".!ill...

2.4

~

1.6

.

~,.

"

~V"~5V

I I

II

rR~F")mA

•

Bit Transfer
Characteristics

6

10 14

Vo - OUTPUT VOLIAGE (VI

"I

0.4

IREF=2mA
811

0,8
812
-V" -IBV
0,2

ftA- -Vs-5V
_\.

83
84

-,!.
-I,

o

.' ,

2

0.6

!:

IREFI-oLA

-14 -10 -6 -2

!;

::,.

I

5.> 0.4

".!...

1.2

~
~

'REF-2mA

1.2

I

1.4

ALLI8ITrON;' TA"TMINTOTMAX
-vL_IJv

0.8

Output Voltage Compliance
vs

18

-50

50

100

TA - TEMPERATURE ("CI

150

-12-10-8-6-4-2024681012141118
VL- LOGIC INPUT VOLTAGE (VI
TL/H/S6B8-3

Note. BI-B8 have Identical.transfer characteris·
tics. Bits are fully switched with less than y. LSB
error, at less than ± 100 mV from actual thresh·
old. These switching points are guaranteed to lie
between 0.8 and 2V over the operating tempera·
ture range (VLC = OV).

3-9

I

Typical Performance Characteristics
Power Supply Current
vs +y

.....
....

I

1
5
Il!

I-

....

',

a

6 I 10 12 14 11 11 ZO

i
i

j
a

2 4

r-,...J,Ll !v

1-,-

I I I

1-1-~!I~

1+

I 11

~

I-

1 II
-II

-4 -I -I -11-12-14-11-11-20

II

1.

111

TA - TEWliRATURE ("~I

V- NEOATIVE 'OWER SUPPLY IV)

Vee - POSITIVE POWER SUPPLY IVI

ALL IITI H'OH OR LOW
'REF·a.A I I

i

1
a -2

10

I

I~ WItH I~EFI. It••

i

Ii

I

-I- -UITJIRJF.U-r-

I
a

Power Supply Current
va Temperature

ALL IITS IIAY BE H18" OR LOW
- - -'I-.rnIIR~F·~ ... -1-

ALL IITS HIGH OR LOW

Q

I

(Continued)

Power Supply Current
vs-Y

TUH/5686-4

Equivalent Circuit

TUH/5686-15

Typical Applications

FIGURE 2
(Continued)

DIGITAL INPUTS

MSI

IFS '" +VREF x~
RREF
256
10 + 10 = IFS for all
logic slates

LSB'

B1IZBlB48S88Bl ••

~ +v REf r-t-t+~H.;-f;"*"~

rd\\f
R1S

'.

For fixed reference. TIL operation.
typical values are:

-VREF

VREF =' 10.OOOV
RREF = 5.000k

~r

R15'" RREF

Cc = O.OI,.F
-v

VLC - OV (Ground)

.v
TL/H/5686-5

FIGURE 3. Basic Positive Reference Operation (Note 4)

......

".

~UFo-~~~1l'~·

IFS '" -VREF x ~
RREF
256

TUH/5686-21

____________~==~o

for~~!l~~£.~'ation6111
.... -.~ ............

FIGURE 5. Bale NegatIve Reference Operation (Note 4)

FIGURE 4. Recommended Full Scale Adjustment Circuit
(Note 4)

3·10

,-----------------------------------------------------------------------, c
r;o
Typical Applications (Continued)
c»

o
o
.....

DIGITAL INPUTS

• MS.
B1 1283 84 85

au

LSB
87 BI

g

EO

n
o

c»

o

IREf"2mA

.....

g

n
o

TL/H/5686-17

c»

o

B1 B2 B3 B4 B5 B6 B7 B8 IOmA
1 1
1 1
1
1
1
1 1.992
1
1
1 1 1 1
1 0 1.984
1 0
0 0 0
0 0
1 1.008

Full Scale
Full Scale-LSB
Half Scale + LSB
Half Scale
Half Scale-LSB
Zero Scale + LSB
Zero Scale

1
0
0
0

0
1
0
0

0
1
0
0

0
1
0
0

0
1
0
0

0
1
0
0

0
1
0
0

0
1
1
0

1.000
0.992
0.008
0.000

lomA
Eo
EO
0.000 -9.960 0.000
0.008 -9.920 -0.040
0.984 -5.040 -4.920
-5.000
-4.960
-0.040
0.000

0.992
1.000
1.984
1.992

-4.960
-5.000
-9.920
-9.960

FIGURE 6. Basic Unipolar Negative Operation (Note 4)

'0 4
+10.0DQV
r----------~~~~'Dk~~

DACOIOO

"

ra

.Dk

I

TL/H/5686-6

B1 B2 B3 B4 B5 B6 B7 B8
Pos. Full Scale
1
Pos. Full Scale-LSB 1
Zero Scale + LSB
1
Zero Scale
1
Zero Scale - LSB
0
Neg. Full Scale + LSB 0
Neg. Full Scale
0

1
1
0
0
1
0
0

1
1
0
0
1
0
0

1
1
0
0
1
0
0

1
1
0
0
1
0
0

1
1
0
0
1
0
0

1
1
0
0
1
0
0

Eo
-9.920
-9.840
-0.080
0.000
+0.080
+9.920
+10.000

1
0
1
0
1
1
0

Eo
+ 10.000
+9.920
+0.160
+0.080
0.000
-9.840
-9.920

FIGURE 7. Basic Bipolar Output Operation (Note 4)

..R,

..

'

E~

DACDIGO

ra

III

VREF

-'" 2X)
(2i8+2ii

where X Is the input code and
RL = l'IL = RREF

I

TL/H/5686-18

If RL

= Ai: within

± 0.05%, oulput is symmetrical about ground

B1 B2 B3 B4 B5 B6 B7 B8
Pos. Full Scale
POs. Full Scale - LSB
(+ )Zero Scale
(- )Zero Scale
Neg. Full Scale + LSB
Neg. Full Scale

1
1
1
0
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
0
0
1
1
0

EO
+9.960
+9.880
+0.040
-0.040
-9.880
-9.960

FIGURE 8. Symmetrical Offset Binary Operation (Note 4)

3-11

N

Typical Applications (Continued)

EO

....O oro -IFS' RL

DACOBOO

>~

TL/H/5686-19

For complementary oUlput (operation as negative logic DAC), connect Invert·
ing Input of op amp to 1Q (pin 2), connect 10 (pin 4) to ground.

FIGURE 9. Positive Low Impedance Output Operation (Note 4)

266

IFS'"

OAI:IIIII

2s6

IREF

"L

TLlH/5686-20

For complementary output (operation as a negative logic DAC) connect non-in·
verting input of op am 10 1Q (pin 2); connect 10 (pin 4) tei ground.

FIGURE 10. Negative Low Impedance Output Operation (Note 4)

VTH = VLC + 1.4V
15V CMOS, HTL, HNIL
VTH

= 7.6V
PMOS
VTH-DV

+vREF

\>
RREF ~{OPTIONAL RESISTOR
.
~ FOR OFFSET IIPUlI

..

r-----'..J~~

RIN

o-"""'fY-~.:---t14
REO -ZIG

OACIIIIDI

Rp

NO CAP

It
TLlH/5686-10
TL/H/5668-9

Note. Do not exceed negative logic input range of DAC.

FIGURE 12. Pulsed Reference Operation (Note 4)

FIGURE 11. Interfacing with Various Logic Families

3-12

Typical Applications

~

(Continued)

o
C»
o
o
......

(a) IREF :;" peak negative swing of liN

g

(")

(b)

VIN~

-

+ VREF must be above peak positive swing of VIN

o

C»

o
.....
.....
C

VIN~

g

OACOBOO

Rli
IOPTIONALI

o-JIIVYo--I15
L..._ _ _ _ _ _ _J

C»

o

r~~~~:~~~-

DAC08DD

N

TL/H/56B6-12

TL/H/56B6-11

FIGURE 13. Accommodating Bipolar References (Note 4)

FDR TURN "ON". VL' 2.7V
FOR TURN "OFF". VL =O.7V

V Cl~~-f
L
5V

"""'C
VOUT
IX PROBE

r-

O.4V

OV
OV

...J--O.4V
15k
RREF

R15
_""..1\r--I15

DACDBDD
ID.U.T.I

•

-15V
TO D.U.T.

13

T

O•, • F
15V

-15V
TL/H/56B6-7

FIGURE 14. Settling Time Measurement (Note 4)

3-13

Typical Applications

(Continued)

av

5V STOP' .
CONVERSION

I
FREE
RUN

18

5V

VC1:
DMZHZ
SAR
GND
DO 01 02 Q3 Q4 OS Q8 07
3 4 I 8 " 12 13 14

lSI
15V

5V

8-BIT tGITAl
WORD

15V
R4
3.8M

MSI
VREF

RI
511

10 I I 7 I 5
12 "
14 LSI 17 88 II. 14 13 B2 MSI
2
VR'
Iii

R2
511

DAcom

R3
Ik

Ik

Ik

-15V
51

lOOk

Note. For I ,... conversion time with 8-bH resolution and 7-bit accuracy. an
LM361 comparator replaces the LM319 and the reference current is doubled
by reducing RI, R2 and R3 to 2.5 kO and R4 to 2 MO.
TL/H/5686-B

FIGURE 15. A Complete 2 ,.... Conversion Time, 8-81t AID Converter (Note 4)

3-14

tJ1National Semiconductor

OAC0808/0AC0807/0AC0806 8-Bit 01 A Converters
General Description
The DAC0808 series is an 8-bit monolithic digital-to-analog
converter (DAC) featuring a full scale output current settling
time of 150 ns while dissipating only 33 mW with ± 5V supplies. No reference current (IREF) trimming is required for
most applications since the full scale output current is typically ± 1 LSB of 255 IREF/ 256. Relative accuracies of better than ± 0.19% assure 8-bit monotonicity and linearity
while zero level output current of less than 4 /LA provides
8-bit zero accuracy for IREF:2:2 rnA. The power supply currents of the DAC0808 series are independent of bit codes,
and exhibits essentially constant device characteristics over
the entire supply voltage range.
The DAC0808 will interface directly with popular TIL, DTL
or CMOS logic levels, and is a direct replacement for the

MC150B/MC140B. For higher speed applications, see
DAC0800 data sheet.

Features
Relative accuracy: ± 0.19% error maximum (DAC0808)
Full scale current match: ± 1 LSB typ
7 and 6-bit accuracy available (DAC0807, DACOB06)
Fast settling time: 150 ns typ
Noninverting digital inputs are TIL and CMOS compatible
• High speed multiplying input slew rate: 8 mAl/Ls,
• Power supply voltage range: ± 4.5V to ± 18V
• Low power consumption: 33 mW @ ± 5V

•
•
•
•
•

Block and Connection Diagrams
MSI

Dual-In-Llne Package

LSB

jyyyyyyy
RANGE

NCIN.'U'...!.

Order Number
DAC0808, DAC0807,
orDAC0806
See NS Package
Number J16A,
M16AorN16A

CURRENT SWITCHES

CONTROL

I

II

Ro2R UDDER

L--_ _ _

~

DND'

BIAS CIRCUIT

VREF{+lo--H;::::=::;---:t::~=::::;-"'--'r-o'
T
J NPN CURRENT
Vee
~

,.......-

SDURCE'AIR

VRlFI_'V" R';;r.NC'....
....
L.,..,
l.!Ci! !UR!! R'! !N'!.!A••! 't....!:
L~~~~.~.:J~--.Jr'" c.....

V~E

u

.N• ..!.

.!.!.'''''-'
.!!.VREFC••

VEE..!
I ••

...!

MSI A1..!

'!!'_...n••

DAC_

SERIEI

.. ..!.

A'...!.
....!.

~'cc
(o!!."'11

fll.A'

.!!..,
.!...'
TLlH/5687-2

TLlH/5687-1

Small-Outline Package
16f-A. LSB

VCC - 1
2

v...,(+)-

IS f-A7

V",(-)- 3

1. f-A6

COWPENSATION- •

13 f-AS

He (N.TE 2)- 5

12f-A<

GHD- 6

11 f-A3

7

I. f-A2

V,,-

1.- B

•

9 f-Al WSB

TLlH/5687-13

Top View

Ordering Information
ACCURACY OPERATING TEMPERATUREf-_ _ _ _ _ _ _,...:O:::.:R..::D:::.:E::.R:..:N.:.;U:.:;M::.:B:::.:E::.R:.:S:.......-._ _ _ _ _ __
RANGE
J PACKAGE (J16A)'
N PACKAGE (N16A)*
SO PACKAGE (M16A)
7-bit
6-bit

O·C:O::TA:O::+75·C
O·C:O::TA:O::+75·C

1
DAC0808LCNlIMC1408P8
DACOB07LCJ: MC140BL7 DAC0807LCN MC1408P7
DAC0806LCJ MC140BL6 DAC0806LCN MC1408P6

'Note. Devices may be ordered by using either order number.

3-15

DAC0808LCM
DAC0807LCM
DAC0806LCM

Absolute Maximum Ratings (Note 1)

,

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Supply ,Voltage
Vcc
','"
1BVec
- 1BVoc
VEE
Digit~llnput Voltage, V5-V12
-10Vecto + 1BVec
Applied Output Voltage, Vo
-,11.vecto + 1BVec

Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (Plastic)
Dual-In-Line Package (Ceramic)
Surface Mount Package
Vapor Phase (SO seconds),
Infrared (15 seconds)

+

Reference Current, 114
Reference Amplifier Inputs, V14, V15
Power'Dissipation (Note 3)

Vcc, VEE
1000mW

ESD Susceptibilio/ (Note 4)

TBD

2S00C
3000C
215·C
220·C

Operating Ratings

5mA

..

-'-S5·C to + 150·C

Storage Temperature Range

'
o

,

TMIN ~ TA ~ TMAX
~TA ~ +75·C

Temperature ,Range
DACOBOBLC Series '

'Electrical Characteristics'

(Vcc = 5V, VEE,= -15Vec, VREF/R14 = 2 mA, DACOBOB:TA= -55·Cto + 125·C, DACOBOBC, DACOB07C, DACOBOSC, TA
= O·C to + 7S·C, and all digital' inputs at high'logic level unless otherwise noted.)

Symbol
E,

Parameter
Relative Accuracy (Error Relative
to Full Scale 10)
DACOBOBLC (LM140B-B)
DACOB07LC(LM140B-7), (Note 5)
DACOBOSLC (LM140B-S), (Note 5)
Settling Time to Within % LSB
(Includes tpLH)

Conditions

150

:rA= 25·C, (Figure 5) ,

MSB
VIH
VIL

Digital Input Logic Levels
Hiph Level, Logic "1"
Low Level, Logic "0"

MSB

Digital Input Current
High Level
Low Level

VIH = 5V
VIL'= O:BV

Reference Input Bias Current

(FigureS)

Output Current Range

(FigureS)

30

100

±20

%
%
%
ns
ns
pp'm'·C

(FigureS)
2
, O.B

Vec
Vec

0
-0.003

0.040
-O.B

mA
mA

-1

-3

p.A

0
0

2.0
2.0

2.1
4.2

inA
mA

1.9

1.99
0

2.1
4

mA
p,A

-0.55, +0.4
-5.0, +0.4

Vec
Vec

(FigureS)

VEE = -5V
VEE = -15V, TA = 25·C

Output Voltage Compliance (Note 2)
VEE= -5V,IREF=1 mA
VEE Below -1 OV

Units

(Figu~5)

Output Full Scale Current Drift

Output Current, All' Bits Low

Max

%

T A = 25·C (Note S),

TClo

Output Current

;

±0.39
±0.7B

Propagation Delay Time , '

10

Typ

±O.19

tpLH, tpHL

115

Min

(Figure 4)

VREF = 2.000V,
R14 = 10000,

(FigureS)
'(RgureS)
E, ~ 0.19%, TA = 25·C

,

3-1S

Electrical Characteristics

(Continued)
(Vee = 5V, VEE = -15 Voe, VREF/R14 = 2 mA, DAC0808: TA = -55'Cto + 125'C, DAC0808C, DAC0807C, DAC0806C, TA
= O'C to 1- 75'C, and all digital inputs at high logic leve! unless otherwise noted.)
Symbol

Parameter

SRIREF

Reference Current Slew Rate

(Figure 6)

Output Current Power Supply
Sensitivity

-5V ,;;; VEE';;; -16.5V

Power Supply Current (All Bits
Low)

(Figure 3)

C.'ndilions

Min

Typ

4

8

lee
lEE
Power Supply Voltage Range

0.05

2.7

p.AN

2.3
-4.3

22
-13

mA
mA

5.0
-15

5.5
-16.5

Voe
Voe

33
106
90
160

170
305

mW
mW
mW
mW

4.5
-4.5
Vee
Vee
Vee
Vee

'.

All Bits High

Units
mAlp.s

TA = 25'C, (Figure 3)

Vee
VEE
Power Dissipation
All Bits Low

Max

=
=
=
=

5V, VEE = -5V
5V, VEE = -15V
15V, VEE = -5V
15V, VEE = -15V

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified opereting conditions.
Note 2: Range control is not required.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 8JA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature Is Po = (TJMAX - TAllO JA or the number given in the Absolute Maixmum Ratings. whichever is lower. For this

device, TJMAX = 125'C, and the typical junction.to-ambient thermal resistance of the dual-in-line J package when the board mounted is 100"C/W. For the dual-inline N package, this number increasesto 175'C/W and for the small outline M package this number is 100·C/W.
Note 4: Human body model, 100 pF discharged through a 1.5 kG ,esistor.
Note 5: All current switches are tested to guarantee at least 50% of rated current

Note 6: All bits switched.
Note 7: Pin-out numbers for the DALOSOX represent the dual-in-line package. The small outline package pinout differs from the dual-in-line package.

Typical Application
vcc- sv

l

MSB A'

13

0-::

A3a-;

DlG.TAL

,.PUTS

A'O-;

L..i~ ~

S>l

1""'·:>-~·\I'''I/I'',---o1D.OOOV=VREF
..

A'~

I I

:5
DAC....

~

':

-

T'T,D'"
_~

•

SOOOk

1

"'51

~+

Vo=10V

(A1

A2

~3TPUT
AS)

2+4+"'256

VEE --tSV

TL/H/5687-3

FIGURE 1.

+ 10V Output Digital to Analog Converter (Note 7)

3-17

Typical Performance Characteristics
Vee = 5V, VEE = -15V, TA ;,. 25'C, unless otherwise noted
logic Input Current vs
Input Voltage

Bit Transfer Char..cterlstlcs
1.4

".!...

.
..=
..
il

~
~

I I III

I I III
-11-10-1-1-4-10 14 I ,1012141118

".!

VEE - -16V

§..

1.1

!;

1.2

~

ALL IITS "ON"
VEE--5V

I

I

.~

k

-v- -15V
0.4

A3
A4

ftlt-V--5v
0.2

11~-JmA

a
-14 -10 -8 -I

0.1

2

&

10 14 18

'. T~ - TEMPERATURE I'CI

Typical Power Supply
Current vs Temperature

~

I:

..II
~

~

i

-

r'"

li C

1.0
-60

60

IfC

a

o

100

160

TEMPERATURE rCI

Reference I"put
Frequency Response

S

:!!

;

lEE WITH 114 - O.Z mA

VEE - NEGATIVE POWER SUPPLY IVI

3.0
1.0 - I -

-",

a

~ ~

f-

I I

4.0

ALL IITS HIGH DR LOW
1,,-ZmA
lEE

-4 -I -1-10-12-14-18-11-20

lEE

5.0

Typical Power Supply
Current vs Vee

IcC

a -2

8.0

TEMPERATURE roCI

J

I~E JTH ~14 UA

ALL 81TS HIGH OR LOW
1,4- ZmA

7.0

a

-IZ I-J'-'-'--'-.......-'-.........t.-.........
60
IUD
160
-50

I-f--I--IIEE'WIT~II~-lm ' f-i-

0.4

-55 -3J-19 ·-1 IJ 35 53 JI 89 10J 115

..il
=

Typical Power Supply
Current vs VEE
ALL BITS HIGH OR LOW

.... r-.,

E0

"Ii

-8

t'r-.,

10.2

.!

VG - OUTPUT VGLTAGE IVI

o

u

!

ii:

!1 0.4

i

0••

8.0

I I
I I
1!4.LA

0.1

i

II:

Output Voltage Compliance
vs Temperature

114=2mA

1

i

1.2

VL - LOGIC INPUT VOLTAGE IVI

u

I;co

9

I!:

~~
,it

-12-10-8-1-4-2024 I 11012141111

Output Current vs Output
Voltage (Output Voltage
Compliance)
2.4

~1

0.1

VL - LOGIC INPUT VOLTAGE IVI

2.1

2

:>

1

g

~

; 1.' -- -~ 1.6
...........
.. 1.4

0.8

I!:

AI THROUGH AI

114"ZmA

1.Z

Logic Threshold Voltage va
Temperature

I'\.

-&

~ -~

I
B

A

C

a:: -12

-14
-II
2 4

I

I 10 lZ 14 18 11 ZO

VCC - POSITIVE POWER SUPPLY IVI

0.1

0.3

1

10

1- FREQUENCY IMHz)
TLlH/5687 -5

Unless otherwise specified: R14 =
R15 = 1 kO, C = 15 pF, pin 16 to
VEE; RL = 500, pin 4 to ground.
Curve A: Large Signal Bandwidth
Method of Figure 7, VREF = 2 Vp-p
offset 1 V above ground.
Curve B: Small Signal Bandwidth
Method of Figure 7, RL = 2500, VREF
= 50 mVp-p offset 200 mV above
ground.
Curve C: Large and Small Signal
Bandwidth Method of Figure 9 (no op
amp, RL = 500), Rs = 500, VREF =
2V, Vs = 100 mVp-p centered at OV.

3-18

&I
- -. .'"T...... ;:

3·19

CD

~

<:)

0

Test Circuits
Vee

ce
....e

VI and 11 apply to inputs A1-A8.
The resistor tied to pin 15 is to temperature compensate the
bias current and may not be necessary for all applications.

.....
<:)

CD
<:)

~

e
....
CD
<:)

CD

~e

.
(A1
10 = K "2

AI
A3

DIGITAL

INPUTS

r:1

A2

A3

A4

A5

A6

A7

A8 )

+ 4" + 8 +16 + 32 + 64 + 128 + 256

A4

A5

where K "" VREF
R14
and AN = "1" if AN is at high level
AN = '.'0" if AN is at low level

F-o--,...-....-o ~8TPUT

AI
Al
A.

"L

',-

'EEr

v"

TL/H/5687-6

FIGURE 3. Notation Definitions Test Circuit (Note 7)
.sa

A'

A'

I·BIT
COUNTER

TUH/5687-7

FIGURE 4. Relative Accuracy Test Circuit (Note 7)

ZAV---,-------...
DAV

"

OIV

T
111 ":"

US( AL TO ONO FOR TURN "Off"
MEASUREMENT IStE TEXT)

SETTLING TIME
. .. (,IGUREIiI

O,1",
.
FOR SETTLING TIME

"·'&C1_TV'
TO:t1/2LSI

I=-<:>---"'~H>'O :~~~~LE:~ral~I:I:~
~CDS2IPF
TRANSIENT
RESPONSE
1N4454 (LOW CAPACITANCE,
FASTRECOYERY DIODE)

RL -10

-1000V--fP'-----.....Ji

VEE

PI.4TDGND

TL/H/5687 -8

FIGURE 5. Transient Response and Settling Time (Note 7)
3·20

c):00

Test Circuits (Continued)

n
c

Vee

Vee

CD
C

CD
......

RI40, RI5

C

):00

AI
A2

814
n15

15

A3

"'REF

J"""L

......
......
C

A4

):00

A5

lii "1....1"

A6
A7
SCOPE

2m:~

RL

A8

-=

SLEWING
TIME
dl

1

SEE TEXT FOR VALUES OF e

dV

iii = iii iii"

VEE
TLlHis687 -10

FIGURE 7. Positive VREF (Note 7)

TL/H/5687-9

FIGURE 6. Reference Current Slew Rate Measurement (Note 7)
Vee

Vs

R14 .. RIS
RS
R14

AI
Al
A3
A4
A5

AI

A6

Al

A7

A3

A4

A8

AS

When

Vs = 0,114 = 2.0 mA

Vo = [VREF + Vs ] (A) RO
R14

RS

A6
A7
SEE TEXT FOR VALUES OF e

A8
RO

VEE
TLlH/S687-11

FIGURE 8. Negative VREF (Note 7)
Co

>-C~HE-oVO

TL/H/5687-12

FIGURE 9. Programmable Gain Amplifier or
Digital Attenuator Circuit (Note 7)

Application Hints
REFERENCE AMPLIFIER DRIVE AND COMPENSATION
The reference amplifier provides a voltage at pin 14 for con·
verting the reference voltage to a current. and a turn·around
circuit or current mirror for feeding the ladder. The reference
amplifier input currrent, 1,4, must always flow into pin 14,
regardless otthe set·up method or reference voltage polarity.

R15 can be tied to a negative voltage corresponding to the
minimum input level. It is possible to eliminate R15 with only
a small sacrifice in accuracy and temperature drift.
The compensation capacitor value must be increased with
increases in R14 to maintain proper phase margin; for R14
values of 1, 2.5 and 5 k!l, minimum capacitor values are 15,
37 and 75 pF. The capacitor may be tied to either VEE or
ground, but using VEE increases negative supply rejection.

Connections for a positive voltage are shown in Figure 7.
The reference voltage source supplies the full current 114.
For bipolar reference signals, as in the multiplying mode,

3·21

C')
C
CD
C

C')
C
CD
C

en

Application Hints (Continued)
A negative reference voltage may be used if R t 4 is grounded and the reference voltage is applied to R15 as shown In
Figure 8. A high input impedance is the main advantage of
this method. Compensation involves a capacitor to Vee on
pin 16, using the values of the previous paragraph. The negative reference voltage must be at least 4V above the Vee
supply. Bipolar input signals may be handled by connecting
R14 to a positive reference voltage equal to the peak positive input level at pin 15.

the excellent temperature tracking of the monolithic resistor
ladder. The reference current may drift with temperature,
causing a change in the absolute accuracy of output current. However, the DAC0808 has a very low full-scale current drift with temperature.
The DAC0808 series is guaranteed accurate to within ± Yz
LSB at a full-scale output current of 1.992 mA. This corresponds to a reference amplifier output current drive to the
ladder network of 2 mA, with the loss of 1 LSB (8 !LA) which
is the ladder remainder shunted to ground. The input current
to pin 14 has a guaranteed value of between 1.9 and 2.1
mA, allowing some mismatch in the NPN current source
pair. The accuracy test circuit is shown in Figure 4. The 12bit converter Is calibrated for a full-scale output current of
1.992 mAo This is an optional step since the DAC0808 accuracy is essentially the same between 1.5 and 2.5 mAo Then
the DAC0808 circuits' full-scale current is trimmed to the
same value with R14 so that a zero value appears at the
, error amplifier output. The counter is activated and the error
band may be displayed on an oscilloscope, detected by
comparators, or stored in a peak detector.
Two 8-bit D-to-A converters may not be used to construct a
16-bit accuracy D-to-A converter. 16-bit accuracy implies a
total error of ±Yz of one part in 65,536 or ±0.00076%,
which is much more accurate than the ±0.019% specification provided by the DAC0808.

When a DC'reference voltage is used, capaCitive bypass to
ground is recommended. The 5V logic supply is not recommended as a reference voltage. If a well regulated 5V supply which drives logic is to be used as the reference, R14
should be decoupled by connecting it to 5V through another
resistor and bypassing the junction of the 2 resistors with
0.1 /Lf to ground. For reference voltages greater than 5V, a
clamp diode is recommended between pin 14 and ground.
If pin 14 is driven by a high impedance such as a transistor
clJrrent source, none of the above compensation methods
apply and the amplifier must be heavily compensated, decreasing the overall bandwidth.

OUTPUT VOLTAGE RANGE
The voltage on pin 4 is restricted to a range of -0.55 to
0.4V when Vee = -5V due to the current switching methods employed in the DAC0808.
The negative output voltage compliance of the DAC0808 is
extended to - 5V where the negative supply voltage is more
negative than -1 OV. Using a full-scale current of 1.992 mA
and load resistor of 2.5 kO between pin 4 and ground will
yield a voltage output of 256 levels between 0 and
-4.980V. Floating pin 1 does not affect the converter
speed or power dissipation. However, the value of the load
resistor determines the switching time due to increased voltage swing. Values of RL up to 5000 do not significantly
affect performance, but a 2.5 kO load increases worst-case
settling time to 1.2 /Ls (when all bits are switched ON). Refer
to the subsequent text section on Settling TIme for more
details on output loading.

MULTIPLYING ACCURACY
The DAC0808 may be used in the multiplying'mode with
8-bit accuracy when the reference current Is varied over a
range of 256: 1. If the reference current in the multiplying
mode ranges from 16 /LA to 4 mA, the additional error contributions are less than 1.6 !LA. This is well within 8-bit accuracy when referred to full-scale.
A monotonic converter is one which supplies an increase in
current for each increment in the binary word. Typically, the
DAC0808 is monotonic for all values of reference current
above 0.5 mAo The recommended range for operation with
a DC reference current is 0.5 to 4 mAo

OUTPUT CURRENT RANGE

SETTLING TIME

The output current maximum rating of 4.2 mA,may be used
only for neg~tive supply voltages more negative than -8V,
due to the increased voltage drop across the resistors in the
reference current amplifier.

The worst-case switching condition occurs when all bits are
switched ON, which corresponds to a low-to-high transition
for all bits. This time is typically 150 ns for settling to within
± Yz LSB, for 8-bit accuracy, and 100 ns to Yz LSB for 7 and
6-bit accuracy. The tum OFF is typically under 100 ns.
These times apply when RL ~ 5000 and Co ~ 25 pF.

ACCURACY
Absolute accuracy is the measure of each output current
level with respect to its intended value, and is dependent
upon relative accuracy and full-scale current drift. Relative
accuracy is the measure of each output current level as a
fraction of the full-scale current. The relative accuracY of the
DAC0808 is essentially constant with temperature due to

Extra care must be taken in board layout since this is usually
the dominant factor in satisfactory test results when measuring settling time. Short leads, 100 /LF supply bypassing
for low frequencies, and minimum scope lead length are all
mandatory.

3-22

tflNational Semiconductor

DAC0830/DAC0831/DAC0832 8-Bit JLP
Compatible, Double-Buffered D to A Converters
General Description

Features

The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying
DAC designed to interface directly with the 8080, 8048,
BOB5, ZBOI!>, and other popular microprocessors. A deposited silicon-chromium R-2R resistor ladder network divides
the reference current and provides the circuit with excellent
temperature tracking characteristics (0.05% of Full Scale
Range maximum linearity error over temperature). The circuit uses CMOS current switches and control logic to
achieve low power consumption and low output leakage
current errors. SpeCial circuitry provides TTL logic input voltage level compatibility.
Double buffering allows these DACs to output a voltage corresponding to one digital word while holding the next digital
word. This permits the simultaneous updating of any numberof DACs.
The DAC0830 series are the 8-bit members of a family of
microprocessor-compatible DACs (MICRO-DACTM). For applications demanding higher resolution, the DAC1000 series
(10-bits) and the DAC1208 and DAC1230 (12-bits) are available alternatives.

• Double-buffered, single-buffered or flow-through digital
data inputs
• Easy interchange and pin-compatible with 12-bit
DAC1230 series
• Direct interface to all popular microprocessors
• Linearity specified with zero and full scale adjust onlyNOT BEST STRAIGHT LINE FIT.
• Works with ±10V reference-full 4-quadrant
multiplication
• Can be used in the voltage switching niode
• Logic' inputs which meet TTL voltage level specs (1.4V
logic threshold)
• Operates "STAND ALONE" (without p.P) if desired
• Available in 20-pin small-outline or molded chip carrier
package

Key Specifications
1 p.s
8 bits
8, 9, or 10 bits

• Current settling time
• Resolution
• Linearity
(guaranteed over temp.)
• Gain Tempco
• Low power dissipation
• Single power supply

0.0002% FS/oC
20mW
5 to 15 Voe

Typical Application
CONTROL BUS

'Allows easy upgrade 10 12·bll DAC1230,
See application hints

CI

,,,.

•

DB7

~

00.7

DBO
LSB

aaaD BUS

TL/H/560B-I

Connection Diagrams (Top Views)
Dual·ln·Llne and
Small·Outllne Packages

"
19

Vee

12·bit DAC1230 series to

ItE (BY1EII iiffi)t

iiRi

permR interchanging from

vee

20

12

WR,

2

10

GNO

GN03

9

Rib

" XFE'
" '"
"

'~ILSBI

"

v..,

'.

GNU

13

10

tThis is necessary for the

ILE 11YTE1/BYT£Zlt

17

01,
01,

Molded Chip Carrier Package

an S·bit to a 12·bR DAC
with No PC board changes

01,
01,

and no software changes,

017111S8)

See applications section.

II

'oun

11

lou"

DI,(USB)

cs ,

10m

I' louT1
4

5

6

7

8

TL/H/560B-22
TLlH/560B-21

3-23

Absolute Maximum Ratings (Notes 1 & 2)

"

" LeadTemperature (soldering,',10 sec.)
DUal-ln-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package,'
Vapor ptiase (60 sec.)
Infra~ed (15 sec.)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
Voltage at Any Digital Input

17VDe

:

Vee t.o GND"
±25V

Voltage at VREF Input'
Storage Temperature Range

Operating Conditi()ns

-65·Cto + 1500C

Package Dissipation
at TA = 25·C (Note 3)

,','

Part numbers with 'LCWM' suffix
Part numbers with 'LCV' suffix:

-100 mVtciVee
BOOV

215·C
·220·C

"

Temperature Range
Part'~umbers with 'LCN' suffix

, 500mW

DC Voltage Applied to
loun or IOUT2 (Nots 4)
ESD Susceptability (Note 14)

260·C
300·C

"

TMINS;TAS;TMAX
O·Cto +700C
O·Cto +70·C
O·Cto +70·C
- 40·C to + 85·C

Part numbers with 'LCJ' 'suffix
Part numbers with 'L.!' suffix
Voltage at Any Digitlllinput

- 55·C to + 12S·C
, ,

..

VeetoGND

VREF = 10.000 VDe unless o~herwisenoted. Boldface limits ~PPIY over te~pera.
ture, TMIN S;,TA S;TMAX. For all' other limits TA = 25·C.

Electrical Characteristics

,',L.

"

",

Parameter

Conditions
;

Vee ,;". 5,Vbe ±S%
" Vee = 4.75 VDe
Vee = 12 VDe ±5%
Vee =, 15.75 VDe
Limit
See
to 15VDC ±5%"
Units
Note
Tested
Design Lilnit
Typ.,
Limit
(Note 12)
(Note 6)
(Note 5)

CONVERTER CHARACTERISTICS
B

Resolution "
Linearity Error Max

Zero and full scale adjusted
-10VS;VREFS; +10V

"

DACOB30W & LCJ
DAC0832W & LCJ
DACOB30LCN, LCWM & LCV
DACOB31lCN
DAC0832LCN, LCWM & LCV
Differential Nonlinearity
Max
DACOB30W & LCJ
DACOB32W & LCJ
DACOB30LCN, LCWM & LCV
DACOB31LCN
DAC0832LCN, LCWM & LCV

"

Zero and fU,1I scal~ adjusted'
-10VS;VREFs; + 10V

Monotonicity

-10VS;VREF
S; + 10V

Gain Error Max

Using Internal Rib
-10VS;VREFS; + 10V

Gain Error,Tempco Max

Usinll internal Rib

. Power Supply Rejection

Reference Input

I
I

8

B

0.05
0.2
O.OS
0,1
0.2

0.05
0.2
0.05
0.1 .
0.2

%FSR
%FSR
%FSR
%FSR
%FSR

0.1
0.4
0.1
0.2
0.4

0.1
0.4
0.1
0.2
0.4

%FSR
%FSR
%FSR
%FSR
%FSR

8
B

8
8

,bits
bits

±1

±1

%FS

0.0006

%
FSrC

4,8

LJ&LCJ
LCN, LCWM & LCV

4
7

±0.2
0.0002

..

;

,

~

All digital inputs latched high
Vcc= 14.5Vto 15.SV
11.5Vto 12.5V
, 4.5V to S.5V

' 0.0002
0.0006
0.013

0.0025

20

20

Min

15

10

10'

3

,
3-24

.

0.Q15

15

VREF= 20 Vp-p, f= 100 kHz
All data inputs latched low

:

%
FSRIV

Max

Output Feedthrough Error

bits

4,B

"

kO
'kO
mVp-p

Electrical Characteristics VREF= 10.000 Voc unless otherwise noted. Boldface limits apply over temperature, TMIN,;;TA,;;TMAX' For all other limits TA = 25'C. (Continued)

Parameter

See
Note

Conditions

Vee = 4.75 Voe
Vee = 15.75 Voe
Typ
(Note 12)

Tested
Limit
(Note 5)

Vee = 5Voe ±5%
Vee = 12Voe ±5%
to15Voe±5%

Output
Capacitance

C

Limit
Units

Dc:;ign Limit
(Note 6)

C

J>

(")
I:)
CI)

All data inputs
latched low

LJ &LCJ
LCN, LCWM & LCV

IOUT2

All data inputs
latched high

LJ &LCJ
LCN, LCWM & LCV

IOUT1
IOUT2

All data inputs
latched low

45
115

pF

IOUT1
IOUT2

All data inputs
latched high

130
30

pF

Digital Input
Currents

Supply Current
Drain

Logic Low

10

100
50

100
100

nA

100
50

100
100

nA

LJ
4.75V
LJ
15.75V
LCJ
4.75V
LCJ
15.75V
LCN, LCWM, LCV

0.6
0.8
0.7
0.8
0.95

0.8

LJ 8. LCJ
LCN, LCWM, LCV

2.0
1.9

2.0
2.0

Voc

Min

Logic High

Max

Digital inputs <0.8V
LJ & LCJ
LCN, LCWM, LCV

-50

-200
-160

Digital inputs>2.0V
LJ &LCJ
LCN, LCWM, LCV

0.1

+10
+8

+10
+10

1.2

3.5

3.5

1.7

2.0

Max

I:)
CI)
(:.)

.....

IOUT1

Max

J>

(")

........

DIGITAL AND DC CHARACTERISTICS
Digital Input
Voltages

I:)
CI)

w
I:)
.......

CONVERTER CHARACTERISTICS (Continued)
Output Leakage
Current Max

c
~

LJ & LCJ
LCN, LCWM, LCV

3-25

-200 '
-200

Voc

/-,A
/-,A
/-,A

mA

W
N

Electrical Characteristics VREF= 1 0.000 Voe unless otherwise noted. Boldface limits apply over.temperature, T MIN,;:TA,;:TMAX. For all other limits T A =

25°C. (Continued)

Vcc= 15.75 Voc
Parameter

Symbol

Conditions

See
Note

Typ
(Note 12)

Vcc= 12Voc±5%

Vcc=4.75Voc

to 15 Voc ±5%

Tested

Design

Limit

Limit

(Note 5)

(NoteS)

Typ
(Note 12)

Tested

Vcc= 5Voc
±5%
Design

Limit

Limit

(Note 5)

(NoteS)

Limit
Units

AC CHARACTERISTICS
Current Setting

ts

VIL =OV. VIH=5V

Write and XFER

tw

VIL =OV. VIH=5V

Pulse Width Min
tos

Data Setup Time
Min

tOH

Data Hold Time

VIL =OV. VIH=5V

Min
les

Control Setup Time VIL =OV. VIH=5V
Min

leH

Control Hold Time

11

100

VIL =OV. VIH=5V

Min

9

100

9

110

"'S
600

900
375

320

900
50

30

50

250

0

0

600

320
10

900
ns

900

1100
0

900

600

30

320
0

375

320

250

320

9

9

250

320

9
VIL =OV. VIH=5V

1.0

1.0

Time

1100

0

0

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond Its specified operating condHions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, OJA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po ~ (TJMAX - TA)/OJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX ~ 125"C (plastic) or 150"C (ceramic), and the typical junction.to-ambient thermal resistance of the J package when board mounted is 80"C/W. For
the N package, this number increases to 100"C/W and for the V package this number is 120'C/W.
Note 4: For current swHching applications, both ioun and IOUT2 must go to ground or the "Virtual Ground" of an operational amplifier. The linearity error is
degraded by approximately Vos ... VREF. For exampie, if VREF ~ 10V then a I mV offset, Vos, on loun or IOUT2 will introduce an additional 0.01 % linearity error.
Note 5: Tested limits are guaranteed to National's AOQL (Average OutgOing Quality Level).
Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgOing quality levels.
Note 7: Guaranteed at VREF~ ± 10 Voc and VREF~ ± I Voc.
Note 8: The unit "FSR" stands for "Full Scale Range." "Linearity Error" and "Power Supply Reiection" specs are based on this unil to eliminate dependence on a
particular VREF value and to indicate Ihe true performance of the part. The "Linearity Error" specification of the DAC0830 is "0.05% of FSR (MAX)". This
guarantees that aiter performing zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within
0.05% x VREF of a straight line which passes through zero and full scale.

a

Note 9: Boldface tested limits apply to the Wand LCJ suffix parts only.
Note 10: A lOOnA leakage current wHh Rfb~20k and VREF~IOV corresponds to a zero error of (100X10- 9x20XI03)XIOO/IO which is 0.02% of FS.
Note 11: The entire write pulse must occur within the valid data interval for the specified tw, tos, tOH, and ts to apply.
Note 12: Typicals are at 25'C and represent most likeiy parametric norm.
Note 13: Human body model, 100 pF discharged through a 1.5 kn resistor.

3-26

Switching Waveform
YIH---_

ILE. CS.

---+f""CH

5011

5011

YIL
YIH------__..

5011
YIL

YIH

5011

DATA BITS

VAUD DAC DATA

5011

YIL

irIS-F:

IOUT1 loun

f\f'v
-------'J -

SmLED TD
±'hLSB
TLIH/560B-2

Definition of Package Pinouts
Control Signals (All control signals level actuated)
CS:
Chip Select (active low). The CS in combination with ILE will enable WR1.
ILE:
Input Latch Enable (active high). The ILE in
combination with CS enables WR1.
WR1:
Write 1. The active low WR1 is used to load the
digital input data bits (01) into the input latch.
The data in the input latch is latched when WR1
is high. To update the input latch-CS and'WRl
must be low while ILE is high.
WR2:
Write 2 (active low). This signal. in combination
with XFER. causes the a-bit data which is available in the input latch' to transfer to the OAC
register. '
XFER: 'Transfer control signal (active low). The
XFER will enable WR2.

Vee:

GNO:

Other Pin Functions
010.017: Digital Inputs. 010 is the least significant bit
(LSB) and 017 is the most significant bit (MSB).
IOUT1:
OAC Current Output 1. loun is a maximum
for a digital code of all 1's in the OAC register,
and is zero for all O's in OAC register.
IOUT2:
OAC Current Output 2. IOUT2 is a constant
minus loun, or loun + IOUT2 = constant (I full
scale for a fixed reference voltage).
Rib:
Feedback Resistor. The feedback resistor is
provided on the IC chip for use as the shunt

feedback resistor for the external op amp which is
used to provide an output voltage for the OAC.
This on-chip resistor should always be used (not
an external resistor) since it matches the resistors
which are used in the on-chip R-2R ladder and
tracks these resistors over temperature.
Reference Voltage Input. This input connects an
external precision voltage source to the internal R2R ladder. VREF can be selected over the range of
+ 10 to -10V. This is also the analog voltage input for a 4-quadrant multiplying OAC application.
Digital Supply Voltage_ This is the power supply
pin for the part. Vcc can be from + 5 to + 15Voc.
Operation is optimum for + 15Voc.
The pin 10 voltage must be at the same ground
potential as loun and IOUT2 for current switching
applications. Any difference of potential (Vos pin
10) will result in a linearity change of
Vospin 10
3VREF
For example, if VREF = 10V and pin 10 is 9mV
offset from loun and IOUT2 the linearity change
will be 0.03%.
Pin 3 can be offset ±100mV with no linearity
change, but the logic input threshold will shift.

3-27

•

~

I

,---------------------------------------------------------------------------------,
Linearity Error

.....
.-

~

.....
o
~

~

DIGITAL INPUT

DIGITAL INPUT

DIGITAL INPUT
TL/H/5608-3

a) End point test after
zero and fs adj.

b) Best straight line

c) Shifting fs adj. to pass
best straight line test

Definition of Terms
Settling Time: Settling time is the time required from a code
transition until the DAC output reaches within ± %LSB of
the final output value. Full-scale settling time requires a zero
to full-scale or full-scale to zero output change.

Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DACOB30
has 28 or 256 steps and therefore has B-bit resolution.
Linearity Error: Linearity Error is the maximum deviation
from a straight line passing through the endpoints of the
DAC transfer characteristic. It is measured after adjusting
for zero and full-scale. Linearity erroris a parameter intrinsic
to the device and cannot be externally adjusted.

Full·Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DACOB30 series, full-scale is VREF -1lSB.
For VREF= 10V and unipolar operation, VFULL.SCALE=
10.0000V-39mV=9.961V. Full-scale error is adjustable to
zero,

National's linearity "end point test" (a) and the "best
straight line" test (b,c) used by other suppliers are illustrated
above. The ','end pOint test" greatly simplifies the adjustment procedure by eliminating the need for multiple iterations of checking the linearity and then adjusting full scale
until the linearity is met. The "end point test" guarantees
that linearity is met after a single full scale adjust. (One adjustment vs. multiple iterations of the adjustment.) The "end
point test" uses a standard zero and F.S. adjustment procedure and is a much more stringent test for DAC linearity.

Differential Nonlinearity: The difference between any two
consecutive codes in the transfer curve from the theoretical
1 LSB is differential nonlinearity.
Monotonic: If the output of a DAC increases for increasing
digital input code, then the DAC is monotonic. An B-bit DAC
which is monotonic to B bits simply means that increasing
digital input codes will produce an increasing analog output.

Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.

(MSa) ill,

Va.,

14
DI.o-~l--I
15

',2

DI.o-....:::.l---1
16
DI,o-....:::.l---1
DI,o---"l--I

8-BIT
MULTIPlYING
D/A
CONVERTER

I"

loun
IDUT1

DI20-~>--I

(LSB)

DI,o--.::......--1
DI, o---I--i

RIO

I
II·

I
I
11

I
I
I

CS o-.:~~)

II
120

~~

21

lsi

r-ov.c

WR,o-~I-----~~~
17

I

I

h
r-o GND

ILE

iffii

I

I

'NDTE: WHEN [l= "1",

a DUTPUTSFOLLDW D INPUTS:

1'0

J.!!'-.o GND

L ______~E~~~'~~A~~I~LA~~:... _ _ J

TL/H/56D8-4

FIGURE 1. DAC0830 Functional Diagram
3-2B

Typical Performance Characteristics
Digital Input Threshold
vs. Temperature

Digital Input Threshold
vs. Vee

2.4 r-r-r-r-r-,-,-,-,.-,

-

2.4

2.0 1-+--+--+--+-+-+-+-+-1
'"

~

1.6

i"rr-r-~

'"

t-r-!~=15VDC

~ 121-+-t'~~~~-f~~~~
i= .
-!;--r-

i!

~
~

=_5+VDC,,+r--+r--f~

:

1-+-+-+-+-+-+--1-+-1

5

0.8 I-+--+--+-'V'+'
0.4

r--r--,---r-,--r--,--,

I--t--t--+-+,-L.,- ~1..
~

1.6
1.2

~

0.1

c

~:5'C
TA=125°C

I--l--I--

§:
~

0

~

Gain and Unearity Error
Variation vs. Supply Voltage

§:

I

...... .... ~

TA. AM81ENT TEMPERATURE ('CI

Write Pulse Width

Data Hold Time

~

-0.05 1-+-+-+--+--+---1-i

~
..

250

1-+--1-+--1--1--+--+-+---1

;::

9

i!5

~ -0.075

~

5 -0.100 r--+--+---;I--1--t--t--l

a::

~

j

Vee. SUPPLY VOLTAGE (VDCI

......

-0.0751-+--t--iHH- Vee=j15V?,j
-0.1 L......l...-.l...-.l...-.l...-.l...-.l..-.l..-_.l-.JL
-55-35-15 5 25 45 65 85 105125

:Ii

15

0

~ -0.025 1-+-+-+-+-+-+--1-+-1
i3 -0.05 I-'l-'l-'l-'l-'l-+-+-+-l

-0.0251--f---.t~ ERJORI-t--t---I

10

0.025

ill

Vee. SUPPLY VOLTAGE (VI

+0.025.-..,--;--.--...---.--,--,
... ~INEARITY ERROR
0.000 I-+-f=::::~+--+-t--l

liNEARITY ERROR
"'GAIN ERROR

0.05

;!;

~5~5~-3~5--1~5~5-2~5-4~5-6=5~85~1~05~125
TA. AM81ENT TEMPERATURE ('CI

r-r-r-r-r-r-r-r-,-,

0.075

r-+--t-4=-+-+-t--J
0.4 1-+-+-1-+-+---'1--1

:!! 0.8

0;

0;

5

2.0

Gain and Linearity Error
Variation vs. Temperature

-55-35-15 5 25 45 65 85 105.125
TA. AMBIENT TEMPERATURE ('CI

200 1-+-+-+-+-+-+-+-+-1
150 VCC=5~'_1- VCC=12V. 1-1VIH=3~
VIH~=3V Vcc=5V.
100 I-- VCC=15V. I12V. 15V
V
Ll '1J3V
VIH =5V
50

~~~~:;$~~~\I~

-~-~-~

5 ~ ~ M ~W5n5
TA. AM81ENT TEMPERATURE ('CI
TUH/5608-5

DAC0830 Series Application Hints
These DAC's are the induslly's first microprocessor compatible, double-buffered 8-bit multiplying D to A converters.
Double-buffering allows the utmost application flexibility
from a digital control point of view. This 20-pin device is also
pin for pin compatible (with one exception) with the
DAC1230, a 12-bit MI8RO-DAC. In the event that a system's analog output resolution and accuracy must be upgraded, substituting the DAC1230 can be easily accomplished. By tying address bit Ao to the ILE pin, a two-byte ,...p
write instruction (double precision) which automatically increments the address for the second byte write (starting
with Ao="1") can be used. This allows either an 8-bit or the
12-bit part to be used with no hardware or software changes. For the simplest 8-bit application, this pin should be tied
to Vee (also see other uses in section 1.1).
Analog Signal control versatility is provided by a precision R2R ladder network which allows full 4-quadrant multiplication of a wide range bipolar reference voltage by an applied
digital word.

system to be updated to their new analog output levels
simultaneously via a common strobe signal.
The timing requirements and logic level convention of the
register control Signals have been designed to minimize or
eliminate external interfacing logic when applied to most
popular microprocessors and development systems. It is
easy to think of these converters as 8-bit "write-only" memory locations that provide an analog output quantity. All inputs to these DAC's meet TTL voltage level specs and can
also be driven directly with high voltage CMOS logic in nonmicroprocessor based systems. To prevent damage to the
chip from static discharge, all unused digital inputs should
be tied to Vee or ground. If any of the digital inputs are
inadvertantly left floating, the DAC interprets the pin as a
logic "1".

1.1 Double-Buffered Operation
Updating the analog output of these DAC's in a double-buffered manner is basically a two step or double write operation. In a microprocessor system two unique system addresses must be decoded, one for the input latch controlled
by the CS pin and a second for the DAC latch which is
controlled by the XFER line. If more than one DAC is being
driven, Figure 2, the CS line of each DAC would typically be
decoded individually, but all of the converters could share a
common XFER address to allow simultaneous updating of
any number of DAC's. The timing for this operation is
shown, Figure 3.

1.0 DIGITAL CONSIDERATIONS
A most unique characteristic of these DAC's is that the 8-bit
digital input byte is double-buffered. This means that the
data must transfer through two independently controlled 8bit latching registers before being applied to the R-2R ladder network to change the analog output. The addition of a
second register allows two useful control features. First, any
DAC in a system can simultaneously hold the current DAC
data in one register (DAC register) and the next data word in
the second register (input register) to allow fast updating of
the DAC output on demand. Second, and probably more
important, double-buffering allows any number of DAC's in a

It is important to note that the analog outputs that will
change after a simultaneous transfer are those from the
DAC's whose input register had been modified prior to the
XFER command.

3-29

DAC0830 Series Application Hints (Continued)'

ANALOG
OUTPUT I

ANALOG
OUTPUT 2

ANALOG
OUTPUT n
SYSTEM"
DAC DISABLe ~-----.

svsr;T~~

)------..-.....- - -__....
'TIE TO LOGIC IIF NOT NEEDED (SEE SEC. 1.1).

FIGURE 2. Controlling Mutlple DACs

OATABUS

~$ti~,--l
_---:-_ _
~2-

cs
Wiii" WR2

\
\

l2

/

U
(INPUT LATCH
UPDATED

n

XFEIi
ILE

\ ~-----CER LATCHE~

ANALOG OUTPUT"
UPDATED

\

=LOGIC "I"

TL1H/5608-8

FIGURE 3
The ILE pin is an active high chip select which can be de·
coded from the address bus as a qualifier for the normal CS
signal generated during a write operation. This can be used
to provide a higher degree of decoding unique control sig·
nals for a particular DAC, and thereby create a more efficient,addressing scheme.

one controlling the DAC's to take over control of the data
bus and control lines. If this second system were to use the
same addresses as those decoded for DAC control (but for
a different purpo,se) the ILE function would prevent the
DAC's from being erroneously alte~ed.
In a "Stand-Alone" system the control Signals are generated by discrete'logic, In this case double-buffering can, be
controlled by simply taking CS and XFER to a logic "0", ILE
to a logic "1" and pulling WR;'low to load data to the input
latch. Pulling \fffi2low will'then update the analog output. A
logic "1" on either,of these lines will prevent the changing
of the analog output.

Another useful application of the ILE pin of each DAC in a
multiple DAC system is to tie these inputs together and use
this as a control line that can effectively "freeze" the outputs of all the DAC's at their present value. Pulling this line
low latches the input register and prevents new data from
being written to the DAC. This can be particularly useful in
multiprocessing systems to allow a processor other than the

3-30

DAC0830 Series Application Hints (Continued)

--'YWI&~"'

DATA BUS _ _ _

____

~--~\~--------~/

\

!

ANA~LD:;:"G-----D;::A-;1TA
OUTPUT UPDATED
ILE= LOGIC "1";

LATCHED

TLJH/5608-7

Wl'!2 and ~ GROUNDED
FIGURE 4

1.2 Single-Buffered Operation
In a microprocessor controlled system where maximum
data throughput to the DAC is of primary concern, or when
only one DAC of several needs to be updated at a time, a
single·buffered configuration can be used. One of the two
internal registers allows the data to flow through and the
other register will serve as the data latch.

be met or erroneous data can be latched. This hold time is
defined as the length of time data must be held valid on the
digital inputs after a qualified (via CS) WR strobe makes a
low to high transition to latch the applied data.
If the contrOlling device or system does not inherently meet
these timing specs the DAC can be treated as a slow memory or peripheral and utilize a technique to extend the write
strobe. A simple extension of the write time, by adding a
wait state, can simultaneously hold the write. strobe active
and data valid on the bus to satiSfy the minimum WR pulsewidth. If this does not provide a sufficient data hold time at
the end of the write cycle, a negative edge triggered oneshot can be included between the system write strob~ and
the WR pin of the DAC. This is illustrated in Figure 5 for an
exemplary system which provides a 250ns WR strobe time
with a data hold time of less than 10n5.
The proper data set-up time prior to the latching edge (La to
HI transition) of the WR strobe, is insured if the WR pulsewidth is within spec and the data is valid on the bus for the
duration of the DAC WR strobe.

Digital signal feedthrough (see Section 1.5) is minimized if
the input register is used as the data latch. Timing for this
mode is shown in Figure 4.
Single-buffering in a "stand·alone" system is achieved by
strobing WR1 low to update the DAC with CS, WR2 and
XFER grounded and ILE tied high.
1.3 Flow-Through Operation
Though primarily designed to provide microprocessor interface compatibility, the MICRO-DAC's can easily be configured to allow the analog output to continuously reflect the
state of an applied digital input. This is most useful in applications where the DAC is used in a continuous feedback
control loop and is driven by a binary up-down count~r, or in
function generation circuits where a ROM is continuously
providing DAC data.
Simply grounding CS, WR1, WFi2, and XFER and tying ILE
high allows both internal registers to follow the applied digital inputs (flow-through) and directly affect the DAC analog
output.

1.5 Digital Signal Feedthrough
When data is latched in the internal registers, but the digital
inputs are changing state, a narrow spike of current may
flow out of the current output terminals. This spike is caused
by the rapid switching of internal logic gates that are responding to the input changes.

1.4 Control Signal Timing
When interfaCing these MICRO-DAC to any microprocessor,
there are two important time relationships that must be considered to insure proper operation. The first is the minimum
WR strobe pulse width which is specified as 900 ns for all
valid operating conditions of supply voltage and ambient
temperature, but typically a pulse width of only 180ns is
adequate if VcC=15VOC. A second consideration is that
the guaranteed minimum data hold time of 50ns should

There are several recommendations to minimize this effect.
When latching data in the DAC, always use the input register as the latch. Second, reducing the Vcc supply for the
DAC from + 15V to + 5V offers a factor of 5 improvement in
the magnitude of the feedthrough, but at the expense of
internal logic switching speed. Finally, increaSing Cc (Figure
8) to a value consistent with the actual circuit bandwidth
requirements can provide a substantial damping effect on
any output spikes.

3-31

•

DAC0830 Series Application Hints (Continued)

.' .... ,

"

.

;."

DATA BUS

WRITE

~~~1?e

---.f

WRITE

~~~~:

---"1-

ONE
SHOT

-+!

I

I

NORMAL
ONE WAIT '
WRITE STROBE ~ STATE - (250 ns)

WR

(250 ns)

(OUTPUT OF - - - . ,
ONE·SHOT)

L

OACWR
:_1
~PULSE WIDTH~
(3SOns)

'_I

DAC
DATA HOLD TIME
(ISOns)
TL/H/5608-8

FIGURE 5. AccommOdating a High Speed System
2.0 ANALOG CONSIDERATIONS

Figure 6. The' MOS switches' operate in the current mode'

The fundamental purpose of any D to A converter is to provide an accurate analog output quantity which is representative of the applied digital word. In the case of 'the DAC0830,
the output, IOUT1' is a current directly proportional to the
product of the applied reference voltage and the digital input
word. For application versatility, a second output, IOUT2' is
provided as a current directly proportional to the complement of the digital input. Basically:
I ' - VREF x Digital Input.
OUTl- 15 kO
256'

with a small voltage drop across them and can therefore
switch currents of either polarity. This is the basis for the 4quadrant multiplying feature of this, D~C, '
2.2 Basic Unipolar Output Voltage
To maintain linearity' of output' current with changes in the
applied digital code, it is important that the voltages at both
of the current 'output pins be as near ground potential
(OVoc) as possible. WithVREF'= + 10V every millivoltappearing at either IOUTI or IOUT2 will cause a 0.01% linearity
error. In most applications this output current is'converted to
a voltage by using an op amp as shown in Figure 7. '

'

I
VREF 255-Digitallnput
OUT2=
15 kO X
256
,

,

The inverting input of the op amp is a "virtual ground" created by the feedback from its output through the internal 15
kO resistor, Rib: All of the output current (determined by'the
digital input and the reference voltage) will flow through RII;
to the output of the amplifier. Two-quadrant operation can
be obtained by reversing the polaritY' of VREF thus causing
loun to flow, into the DAC and be sourced from the output
of the amplifier. The output voltage, in either case, is always
equal to lou'n x Rib and is the opposite Polarity of the refer'"
'
,
ence voltage:

where ,the digital input is the decimal (base 10) equivalent of
the applied 8-bit binary word (0 to 255), VREF is the voltage
at pin 8 and 15 kO is the nominal value of the internal resistance, R, of the R-2R ladder network (discuSsed in Section
2.1),
Several factors external to the DAC itself must be considered to maintain analog accuracy and are covered in subsequent sections.
'
2; 1 The Current Switching R·2R Ladder
The analog circuitry, Figure 6, consists of a silicon-chromium (SiCr or Sicchrome) thin film R-2R ladder which is deposited on the surface oxide of the monolithic chip. As a result,
there are no parasitic diode problems witli the ladder (as
there may be with diffused resistors) so the reference voltage, VREF, can range -10V to + 10V even if Vcc for the
device is 5Voc.
The digital input code to the DAC simply controls the position of the SPDT current switches and steers the available
ladder current to either IOUTI or IOUT2 as determined by the
logic input level ("1" or "0") respectively, as shown in

The reference 'can be either a stable DC vOltage'source or'
an AC signal anywhere in the range from ":'10V to + 1OV.
The PAC can be thought of as a digitally controlled attenuator: the output' voltage is always less than or equal to the
applied reference voltage. The VREF terminal of the device
presents a nominal impedance of 15 kO to ground to external circuitry.
Always use the internal Rib resistor to create an output voltage since this resistor matches (and tracks with temperature) the value of the resistors used to generate the output
current (IOUTI).

3-32

g

DAC0830 Series Application Hints (Continued)

(")

o

co

VREf

Co)

....
~o
co
.......

o-_-"""I\r-_-o\M._ • • • • • • • r-JVl.fv-......- - - - .

0,

2R

Co)

"1"

~g

'-T-.....-t--....-t----~+-...~I_---.!.._-......-t'l vour= -(lOUT! x Rib)

= VREF (D1GI::~'INPUT"o

\

FIGURE 7

Vos ADJUST

Vee

TLlHf560B-9

2.3 Op Amp Considerations
The op amp used .in Figure 1 should have offset voltage
nulling capability (See Section 2.5).

This configuration features several improvements over existing circuits for bipolar outputs with other multiplying
DACs. Only the offset voltage of amplifier 1 has to be nulled
to preserve linearity of the DAC. The offset voltage error of
the second· op amp (although a constant output voltage error) has no effect on linearity. it should be nuilltld only if
absolute output accuracy is required. Finally, the values of
the resistors around the second amplifier do not have to
match the internal DAC resistors, they need only to match
and temperature track each other. A thin film 4-resistor network available from Beckman Instruments, Inc. (part no.
694-3-Rl0K-D) is ideally suited for this application. These
resistors are matched to 0.1 % and exhibit only 5 ppm/DC
resistance tracking temperature coefficient. Two of the four
available 10 kO resistors can be paralieled to 'form R in
Figure 9 and the other two can be used independently as
the resistances labeled.2R.
.
,
.
.

The selected op amp should have as Iowa value of input
bias current as possible. The product of the bias current
times the feedback resistance creates an output voltage error which can be significant in low reference voltage applications. BI-FET op amps are highly recommended for use
with these DACs.because of their very low input current.
Transient response and settling time of the op amp are important in fast data throughput applications. The largest stability problem is the feedback pole created by the feedback
resistance, RIb, and the output capacitance of the DAC.
This appears from the op amp output to the (-) input and
includes the stray capacitance at this node. Addition of a
lead capacitance, Cc in Figure 8, greatly reduces overshoot
and ringing at the output for a step change in DAC output
current.
Finally, the output voltage swing of the amplifier must be
greater than VREF to allow reaching the full scale output
voltage. Depending. on the loading on the output of the amplifier and the available op amp supply voltages (only ± 12
volts in many development systems), a reference voltage
less than 10 volts may be necessary to obtain the full analog output voltage' range.

2.5 Zero Adjustment
For accurate conversions, the input' offset voltage of the
output amplifier must always be nulled. Amplifier offset errors create an overall degradation of DAC linearity.
The fundamental purpose of.zeroingis to make the voltage
appearing at the DAC outputs as near OVoc as possible.
This is accomplished for the typical DAC - op amp connection (Figure i) by shorting out RIb, the amplifier feedback
resistor, and adjusting the Vos nulling potentiometer of the
op amp until the output reads zero volts. This is done, of
course, with an applied digital code of all 'zeros if IOUT1 is
driving the op amp (all one's for lour2l. The short around
RIb is then removed and the converter is zero adjusted.

2.4 Bipolar Output Voltage with a Fixed Reference
The addition of a second op amp to the previous circuitry
can be used to generate a bipolar output voltage from a
fi~ed reference voltage. This, in effect, gives sign significance to .the MSB of the digital input word and allows twoquadrant multiplication of the reference voltage. The polarity
of the reference can also be reversed to realize full 4-quadrant multiplication: ±VREFX ±Digital Code = ±Vour. This
circuit is shown i(1 Figure 9..

3-33

•

DAC0830 Series Application Hints (Continued)
Cc

IOUT;;'l""'o::::~"""~"'--I
VIEF

OAC0830

IOUTf3.2""_-+~~-I

OPAmp

Cc

ts
(0 to Full Scale)

LF356
LF351
LF357'

22pF
22pF
10 pF

5/Ls
2/Ls

4/LS

'2.4 kG RESISTOR ADDED FROM -INPUT TO
GROUND TO INSURE STABILITY

FIGURES

v

-v

OUT- REF

(DIGITALCODE-128)
128

TLlH/5608-10

1 LSB='VREFI
128
Input Code
MSB .......... LSB
'THESE RESISTORS ARE AVAILABLE FROM
BECKMAN INSTRUMENTS, INC. AS THEIR
PART NO. 694-3-Rl0K-D

-VREF

VREF-1 LSB
VREF/2
0
-1 LSB

-IVREFI + 1 LSB
-IVREFI/2

1
1
1
0

1
1
0
1

1 1 1
000
000
1 1 1

0

o
o

1 1 1 1 1 1 -'VREFI_ 1 LSB
2
0 o 0 0 0 0
-IVREFI

0

1 1 1
000
000
1 1 1

IDEALVOUT
+VREF

o ,

+1 LSB
IVREFI + 1 LSB
2
+IVREFI

FIGURE 9
2.6 Full-scale Adjustment
In the case where ~he matching of Rib to the R value of the
manner from the standard current switching configuration.
R-2R ladder (typically ± 0.2%) is insufficient for full-scale
The reference voltage is connected to one of the current
accuracy in a particular application, the VREF voltage can be
output terminals (lOUTl for true binary digital control, IOUT2
adjusted or an external resistor and potentiometer can be
is for complementary binary) and the output voltage is taken
added as shown in Figuf810 to provide a full-scale adjustfrom the normal VREF pin. The converter output is no~ a
ment.
.
voltage in the range from OV to 255/256 VREF as a function
of the applied digital code as shown in Figure 11.
The temperature coefficients of the resistors used for this
adjustment are an important concern. To prevent degradation of the gain error temperature coefficient by the external
resistors, their temperature coefficients ideally would have
to match that of the internal DAC resistors, which is a highly
impractical constraint. For the values shown in Figuf8 10, if
the resistor and the potentiometer each had a temperature
coefficient of ± 100 ppml"C maximum, the overall gain error
temperature coefficent would be degraded a maximum of
0.0025%I"C for an adjustment pot setting of less than 3%
of Rib.
2.7 Using the DACOnO In a Voltage Switching
Conffguratlon
The R-2R ladder can also be operated as a voltage switching network. In this mode the ladder is used in an inverted

TLlH/560B-l1

FIGURE 10. Adding Full-Scale Adjustment

3-34

DAC0830 Series Application Hints (Continued)
8 (VRff)
o.::-1_~,,""_...JI,M.-_

ov .. 'louT" :

2R

••••• -1......w ..........~..,.,......

Vw
2R

(rl~BIT J

2R

2R

I I__I I····
II I
_ _ _...___

L._-t-_~i

_

~i

_

I(~~:l

t---4___t-_..:;(la::.uT:.::ll~l1~: +2.5Vac REFERENCE
(lauTll12 ~

_

TL/H/5608-12

FIGURE 11. Voltage Mode Switching
This configuration offers several useful application advantages. Since the output is a voltage, an external op amp is
not necessarily required but the output impedance of the
DAC is fairly high (equal to the specified reference input
resistance of 10 kG to 20 kG) so an op amp may be used
for buffering purposes. Some of the advantages of this
mode are illustrated in Figures 12, 13, 14 and 15.

gain error on the voltage difference between Vee and the
voltage applied to the normal current output terminals. This
is a result of the voltage drive requirements of the ladder
switches. To ensure that all 8 switches turn on sufficiently
(so as not to add significant resistance to any leg of the
ladder and thereby introduce additional linearity and gain
errors) it is recommended that the applied reference voltage
be kept less than + 5VDe and Vee be at least 9V more
positive than VREF. These restrictions ensure less than
0.1 % linearity and gain error change. Figures 16, 17and 18
characterize the effects of bringing VREF and Vee closer
together as well as typical temperature performance of this
voltage switching configuration.

There are two important things to keep in mind when using
this DAC in the voltage switching mode. The applied reference voltage must be positive since there are internal parasitic diodes from ground to the loun and IOUT2 terminals
which would turn on if the applied reference went negative.
There is also a dependence of conversion linearity and
1"'"'.....--0+15V Vee

,.......--o+15V

r......;::.c;--v:~~~1,b.

__....

..:+~2.5V REFEIISICE

LM336
la~~

_ _.....

LM3311

....---~3~1::0'

.......-----+
+15V

-15
3O/c
TLlH/560B-13
• voltage switching mode eliminates output signal inversion and therefore a
need for a negative power supply.

.• VOUT=2.5V (..£.-1)
128

• Zero code output voltage is limited by the low level output saturation voH·
age of the op amp. The 2 kll pull-down resistor helps to reduce this voltage.

• Slewing and settling time for a full acale output change is :::: 1.8,.s

• Vas of the op amp has no effect on DAe linearity.

FIGURE 13. Obtaining a Bipolar Output from a Fixed
Reference with a Single Op Amp

FIGURE 12. Single Supply DAC

3-35

•

~
C")

~

~.........

,---------------------------------------------------------------------------------,
DAC0830 Series Application Hints (Continued)

C")

~

+1ov(~:)

-10V" VoUT"

~
.....
C)
C")

co
C)

t

a .. VPAC .. ~:: (2.5VI

~

-15

AV=+8

FIGURE 14. Bipolar Output with Increased Output Voltage Swing

+15V

1=

..---.{=

UT

>---.--o=VMAXVoL:::

=VtIIN

.....- - - - - '

o

• Only a single

CODE (01

255

TUH/5608-14

+ 15V supply required

, • Non·interactive full-scale and zero code output adjustments
• VMAA and VMIN must be ,;; +5VOC and ~OV.

1

• ,Incremental OUtput Step~ 256 (VMAX - VMIN).
'0
255
.VOUT~tse;;....---....-0 VOUT
C,

-15V
TLlH/5608-16

2~6)

-V'N (256)
• VOUT=--O--

• CEOUIV= Cl ( 1 +

• When 0 = O. the amplifier will go open loop and the output will saturate.

• Maximum voltage across the equivalent capacitance is
limited to Vo MAX ~:6amp)

• Feedback impedance from the - input to the output varies from 15 kG to
DO as the input code changes from full·scale to zero.

1+0
• C2 is used to improve settling time of op amp.

3-37

Applications (Continued)
Variable fo. Variable 0o. Constant BW Bandpass Filter
Rs

·OUT

Tl/H/5608-17
• 10 =

fKD
.
"256. 00 = fKD (2Aa + AH. 3dbBW =
27rA,C'
"256, Aa(K + 1)'

whereC,

=

C2 = C;K =

~andAI
As

Aa(K + I)
27rA,C(2Ra,.. RI)

= AolOAC = 15k

• Ho = 1 lor AIN = A4 = AI
• Aange 01 10 and a Is :::: 16 to 1 lor circuit shown. The
range can be extended to 255 to 1 by replacing AI with a
second OAC0630 driven by the same digital Input word.
• Maximum 10 X

a product should be ,;: 200 kHz.

DAC Controlled Function Generator
+15V

I

+15V

75k

SYMMETRY::
TRtM
-15V
WAVESHAPE..-#'
TRIM

2k

., r-+15
U

-15

SQUARE WAVE

OUTPUT

TUH/5608-1 B

• OAC controls the Irequency 01 sine, square, and triangle outputs.

o

• I = 256(20k)C lor VOMAX

= VOMIN 01 square wave output and AI = 3 A2.

• 255 to 1 linear Irequency range; oscillator stops with 0 = 0
• Trim symmetry and wavs-shape lor minimum sine wave distortion.

3·38

Applications (Continued)
Two Terminal Floating 4 to 20 mA Current Loop Controller
INPUT

IN4001

LM334
20Q

50ug

LM3290
LM3290

TLlH/5608-19

lOUT = VREF

[2.. +
Rl

_0_] [1
256RIb

+

&]
R3

• DACOB30 linearly controls the current flow from the input terminal to the
output terminal to be 4 rnA (for 0=0) to 19.94 mA (for 0=255).
• Circuit operates with a terminal voltage differential of 16V to 55V.
• P2 adjusts the magnitude of the output current and PI adjusts the zero
to full scale range of output currenl
• Digital inputs can be supplied from a processor using opto Isolators on
each input or the DAC latches can flow·through (connect control lines to
pins 3 and 10 of the DAC) and the input data can be set by SPST toggle
sw~ches to ground (pins 3 and 10).

DAC Controlled Exponential Time Response

•

IOUT1........1~1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--,

r

DAC0B30
IOUT2~~~""'O

VREF

VFINAL

VINITIAL ...;J

10

> ....-o~UT
,

10k

V= 2~6(VOUT - VIN) + ~~VJN

"

YFlrw.

VJNITIAL ..... \
T«TOOANOC

TLlH/5608-20

• Output responds exponentially to input changes and automatically stops
when VOUT= VIN
• Output time constant is directly proportional to the DAC input code and
capacitor C
• Input voltage must be positive (See section 2.7)

3·39

Ordering Information

,,,

Temperature Range
Non
Linearity

' O"Cto +70'

- 40"C to + 8S'C

-SS'C to + 125'C

DAC0830LCM

DAC0830LCV

DAC0830LCJ

DAC0830LJ

DAC0832LCN

DAC0832LCM

DAC0832LCV

. DAC0832LCJ

DAC0832LJ

N20A-Molded DIP

M20B Small Outline

V20A Chip Carrier

0.05% FSR

DAC0830LCN

0.1% FSR

DACQ831LCN

0.2% FSR
Package Outline

,

,.,'

'.

"

"

,

..

".1.,

3·40

\.

J20A....:..ceramic DIP

f}1National Semiconductor

DAC0854 Quad 8-Bit Voltage-Output
Serial DI A Converter with Readback
General Description

Features

The DAC0854 is a complete quad 8-bit voltage'output digital-to-analog converter that can operate on a single 5V supply. It includes on-chip output amplifiers, internal voltage reference, and a serial microprocessor interface. By combining
in one package the reference, amplifiers, and conversion
circuitry for four 0/A converters, the DAC0854 minimizes
wiring and parts count and is hence ideally suited for applications where cost and board space are of prime concern.
The DAC0854 also has a data readback function, which can
be used by the microprocessor to verify that the desired
input word has been properly latched into the DAC0854's
data registers. The data readback function simplifies the design and reduces the cost of systems which need to verify
data integrity.·
.

• Single + 5V supply operation
• MICROWIRE serial interface allows easy interface to
many popular microcontrollers including the COPSTM
and HPCTM families of microcontrollers
• Data read back capability
• Output data can be formatted to read back MSB or
LSB first.
• Versatile logic allows selective or global update of the
DACs
• Power fail flag
• Output amplifiers can drive 2 kG load
• Synchronous/asynchronous update of the DAC outputs

The logic comprises a MICROWIRETM-compatible serial interlace and control circuitry. The interface allows the user to
write to anyone of the input registers or to all four at once.
The latching· registers are double-buffered, consisting of 4
separate input registers and 4 DAC registers. Double buffering.allows all 4 DAC outputs to be updated simultaneously.
The four reference inputs allow the user to configure the
system to have a separate output voltage range tor each
DAC. The output voltage of each DAC can range between
0.3V and 2.8V and is a function of VB lAS, VREF, and the
input word.

Key Specifications
•
•
•
•
•
•
•
•

Applications
•
•
•
•

Connection Diagram

Guaranteed monotonic over temperature
±% LSB max
Integral linearity error
2.7 ,",S max
Output settling time
0.3V to 2.8V
Analog output voltage range
4.5V to 5.5V
Supply voltage range
10 MHz max
Clock frequency
95 mW max
Power dissipation (telK = 10 MHz)
2.65V ±2% max
On-board reference

Automatic test equipment
Industrial process controls
Automotive controls and diagnostics
Instrumentation

Ordering Information
Industrial (- 40·C

VOUT2 -

20 I- VREF2

1

19

VBIAS1- 2

CS-3
AO-4
CLK- 5
00- 6.

.-.

I- VOUT1

18 I- VREF1

DAC0854·

15

I- VREF3

GNO- 7

14I-VOUT3

INT- 8

13 ,... VBIAS2

01- 9
OVcc -

12 I- VREF4

11 --VOUU

10

DAC0854CIJ

J20A Ceramic DIP

DAC0854BIWM,DAC0854CIWM

M20B Small Outline

< TA <

DAC0854CMJ/883

16 I- VREF OUT

TL/H/11261-1

Top View

3-41

Package
N20A Molded DIP

Military (-55"C

171- AVcc

< T A + 85·C)

DAC0854BIN, DAC0854CIN

+125·C)
J20A Ceramic DIP

Absolute Maximum Ratings

(Notes 1 & 2)
If Military/Aerospace specified devices are required,

"

please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 24)

300"C
26O"C

SO Package
Vapor Phase (60 sec.)
Infrared (15 sec.) (Note 7)

7V
Supply Voltage (AVcc, DVcd
±5.5V
Supply Voltage Difference (AVcc-DVec)
GND -0.3Vto
Voltage at Any Pin (Note 3)
AVec/DVec +0.3V
Input Current at Any Pin (Note 3)
5mA
'20mA
Package Input Current (Note 4)
.Power Dissipation (Note 5)
ESD Susceptibility (Note 6)

Soldering Information
J Package (10 sec.)
N Package (10 sec.)

215·C
220"C
-55·Cto + 150·C

Storage Temperature

Operating Ratings (Notes 1 & 2)
4.5Vt05.5V
Supply Voltage
±IV
Supply Voltage Difference (AVce - DVec)
Temperature Range
TMIN < TA < TMAX
DAC0854BIN. DAC0854CIN,
DAC0854CIJ, DAC0854BIWM,
DAC0854CIWM
-40"C < TA < 85·C
DAC0854CMJ/883
-55·C < TA < 125°C

105mW
1250V

Converter Electrical Characteristics
The following specifications apply for AVec = DVcc = 5V, VREF = 2.65V, VBIAS = 1.4V, Rl = 2 kG (Rl is the load resistor on
the analog outputs - pins 1, 11, 14, and 19) and fClK = 10 MHz unless otherwise specified. Boldf.c. limit. .ppl. for T A
= T.. from TMIN to TMAX' All other limits apply for TA = 25°C.
Symbol

Parameter

Conditions

Typical
(Note I)

Limit

UnHs

(Note I)

(Umlts)

8

8

bits

8

8

bits

±O.S

LSB(max)

STATIC CHARACTERISTICS
n

= 10 MHz

Resolution

fClK

Monolonicity

(Note 10)

Integral Linearity Error
DAC0854BIN, DAC0854BIWM
DAC0854CIN, DAC0854CIJ,
DAC0854CIWM, DAC0854CMJ

(Note 11)

Differential Linearity Error
Fullscale Error

(Note 12)

±1.0

LSB(max)

±1.0

LSB(max)

±3S

mV

-30

Fullscale Error Tempco

(Note 13)

Zero Error

(Note 14)

Zero Error Tempco

(Note 13)

-30

Power Supply Sensitivity

(Note 15)

-42

-34

dB (max)

(Note 16)
Cl = 200pF

1.5

2.1

".s

(Note 16)
, Cl = 200pF

1.8

2.7

".s

ppml"C
±3S

mV
ppm 1°C

DYNAMIC,CHARACTERISTICS
ts+

,

ts":'

Positive Voltage Output
Settling Time
Negative Voltage Output
, Settling Time
Digital Crosstalk

(Note 17)

1.8

mVp•p

Digital Feedthrough

(Note 18)

8.5

mVp-p

Clock Feedthrough

(Note 19)

3.3

mVp-p

Channel·to·Channellsolation

(Note 20)

-78

dB

Glitch Energy

(Note 21)

7

nV-s

38

mV

(Note 22)

-49

dB

Peak Value of Largest Glitch
PSRR

Power Supply Rejection Ratio

3·42

Converter Electrical Characteristics (Continued)
The following specifications apply for AVcc = DVcc = 5V, VREF = 2.65V, VBIAS = 1.4V, RL = 2 kfi (RL is the load resistor on
the analog outputs - pins 1, 11, 14, and 19) and fCLK = 10 MHz unless otherwise specified. Boldface limits apply for TA
= T J from TMIN to TMAX. All other limits apply for T A = 25°C.
Symbol

Parameter

Typical
(Note 3)

Conditions

Limit
(Note 4)

Units
(Limits)

DIGITAL AND DC ELECTRICAL CHARACTERISTICS

=
=

=
=

5.5V

2.0

V (min)

4.5V

0.8

V (max)

5

".A(max)

VIN(1)

Logical "1 " Input Voltage

AVcc

VIN(O)

Logical "0" Input Voltage

AVcc

IlL

Digital Input Leakage Current

1

CIN

Input Capacitance

4

COUT

Output Capacitance

VOUT(1)

Logical "1" Output Voltage

ISOURCE

VOUT(O)

Logical "0" Output Voltage

ISINK

VI NT

Interrupt Pin Output Voltage

10 kfi Pullup

Is

Supply Current

Outputs Unloaded

DVcc
DVcc

pF

5

=

=

0.8 rnA

3.2 mA

14

pF

2.4

V (min)

0.4

V (max)

0.4

V (max)

19

mA

4
10

kfi(min)
kfi(max)

REFERENCE INPUT CHARACTERISTICS
VREF

Input Voltage Range

RREF

Input Resistance

CREF

Input Capacitance

0-2.75
7
Full-Scale Data Input

V

40

pF

VBIAS INPUT CHARACTERISTICS
VBIAS

CBIAS

0.3-1.4

V

Input Leakage

1

".A

Input Capacitance

9

pF

VBIAS Input Voltage Range

BANDGAP REFERENCE CHARACTERISTICS (CL
VREFOUT

Output Voltage

.6.VREF/.6.T

Tempco

.6.VREF/.6.IL

Isc

=

220".F)

2.65 ± 2%
(Note 23)

22

=

Line Regulation

4.5V < Vcc < 5.5V, IL

Load Regulation

0< IL < 4mA
< IL < 4 mA; CMJ Suffix
-1 < IL < OmA

o
Short Circuit Current

VREFOUT

=

OV

4 mA

V
ppml"C

2

5

mV

2
2
2.5

6

mV
mV
mV

15

12

mA

AC ELECTRICAL CHARACTERISTICS
tos

Data Setup Time

10

ns(min)

tOH

Data Hold Time

0

ns(min)

tcs

Control Setup Time

15

ns(min)

tCH

Control Hold Time

0

ns(min)

tMIN

Clock Frequency

10

MHz (max)

tH

Minimum Clock High Time

20

ns(min)

tL

Minimum Clock Low Time

40

ns(min)

3-43

•

Converter Electrical Characteristics (Continued)
The following specifications apply for AVcc = DVcc = 5V, VREF = 2.65V, VBIAS = 1.4V, RL = 2 kO (RL is the load resistor on
the analog outputs - pins 1, 11, 14, and 19) and fCLK = 10 MHz unless otherwise specified. Boldface Ilmils apply for 'TA
= T J from TMIN to TMAX. All other limits apply for T A = 25°C.
Symbol

Parameter

Typical
(Note 3)

Conditions

Limit
(Note 4)

Units
(Umlts)

AC ELECTRICAL CHARACTERISTICS (Continued)
tCZl

Output Hi-Z to Valid 1

37

ns(max)

tczo

Output Hi-Z to Valid 0

42

ns(max)

t1H

CS to Output Hi-Z

10 kO with 60 pF

130

ns(max)

tOH

CS to Output Hi-Z

10 kO with 60 pF

117

ns(max)

Nole 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device Is
functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Converter Electrical
Characteristics. The guaranteed specifications apply only for the test conditions listed. Some perfonnance characterlslics may degrade when the device is not
operated under the lis1ed test conditions.
Nole 2: All voltages are measured with respect to ground, unless otherwise specified.
Note 3: When the input voltage (V,N) at any pin exceeds the power supply rails (V,N < GND or Y,N > V+) the absolute value of current at that pin should be limited
to 5 mA or less.
Nole 4: The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 20 mAo
Nole 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperatura), 0JA
(package junction to ambient thennal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is
POmax ~ (TJmax - TAl/0JA or the number given in the Absolute Maximum Ratings, whichever is lower. The table below details TJmax and 0JA for the various
packages and versions of the DACOB54.
Part Number
DACOB54BIN,DACOB54CIN
DACOB54BIJ, DACOB54CIJ
DACOB54BIWM, DACOB54CIWM
DACOB54CMJ/BB3

TJmaxrC)
125
125
125
150

0JArClW)
48
53
64
53

Nole 6: Human body model, 100 pF discharged through a t.5 kO resistor.
Note 7: See AN450 "Surface Mounting Methods and Their Effect on Production Reliability" of the section titled "Surface Mount" found In any current Linear

Databook for other methods of soldering surface mount devices.
Note 8: Typicals are at TJ = 25'C and represent most likely parametric norm.
Nole 9: Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Nole 10: A monotonicity of B bits for the DACOB54 means that the output voltage changes In the same direction (or remains constant) for each Increase in the Input
code.
Note 11: Integral linearity error is the maximum deviation of the output from the line drawn between zero and full-scale (excluding the effects of zero error and fullscale error).
Nole 12: Full-scale error is measured as the deviation from the ideal 2.BOOV full-scale output when VREF
Nole 13: Full-scale error tempco and zero error tempco are defined by the following equation:
Error tempco

~ [Error (TMAxI - Error (TMIN)
VSPAN

= 2.650V and VelAS =

1.400V.

1 [TMAX1~ TMIJ

where Error (TMAxl is lhe zero error or full-scale error at TMAX (in volts), and Error (TMINI is the zero error or full-scale error at TMIN (in volts); VSPAN is the output
voltage span of the DACOB54, which depends on VelAs and VREF.
Nole 14: Zero error is measured as the deviation from the ideal 0.310V output when VREF = 2.650V, VelAs ~ 1.400V, and the digital input word is all zeros.
Nole 15: Power Supply Sensitivity is the maximum change in the onset error or the full-scale error when the power supply diners from its optimum 5V by up to
0.25V (5%). The load resislor RL ~ 5 kO.
Nole 16: PosHive or negative settling time is defined as the time taken for the output of the DAC to settle to its final full-scale or zero outpul to within ±0.5 LSB.
This time shall be referenced to the 50% pOint of the positive edge of CS, which inHiates the update of the analog outputs.
Nole 17: Digital crosstalk Is the glitch measured on the output of one DAC while applying an all Os to all 1s transition at the input of the other DACs.
Note 18: All DACs have full-scale outputs latched and 01 is clocked with no update of the DAC outputs. The glHch Is then measured on the DAC outputs.
Nole 19: Clock feedthrough is measured for each DAC with its output at full-scale. The serial clock is then applied to the DAC at a frequency of to MHz and the
glitch on each DAC full-scale output is measured.
Nole 20: Channel-to-channel isolation is a measure of the enect of a change in one DAC's output on the output of another DAC. The VREF of the first DAC is varied
between 1.4V and 2.65V at a frequency of 15 kHz while the change in full-scale output of the second DAC Is measured. The first DAC is loaded with all Os.
Nole 21: Glitch energy is the diHerence between the positive and negative glHch areas at the output of the DAC when a 1 LSB digital input code change is applied
to the inpul The glHch energy will have its largest value at one of the three maior transitions. The peak value of the maximum glitch is separately specified.
Nole 22: Power Supply Reiection Ratio is measured by varying AVec ~ DVec between 4.75V and 5.25V with a frequeney of 10 kHz and measuring the proportion
of this signal imposed on a full-scale output of the DAC under consideration.
Nole 23: The bandgap reference tempco is defined by the following equation:
Tempco ~ [VREF (TMAxI - VREF (TMIN)
VREF (TROOM)

1 [TMAX1~ TMIJ

where TROOM = 25'C, VREF (TMAX) is the reference output at TMAX, and similarly for VREF (TMIN) and VREF (TROOM).
Nole 24: A MilHary RETS specification is available upon request.

3-44

o

»
o

Typical Converter Performance Characteristics
Zero Error vs
Temperature

c01)

Full-Scale Error
vs Temperature
-5",,-.-.-.-r~~'-'

16

s

oS

I
~

~

Ycc·SY
YRD' =-2.15V
VIlAS. 1.40Y

~

fa.JC-IOWHz
-16
-60
-20
20

60

100

140

~

14

~

13

>-

~

11
10
-60 -30

TEMPERATURE (Oc)

-48

-48

-50

-50

....

.....

~

~

-54

-20

20

60

100

.....

-54

140

-60

90

120 150

Supply Current vs
Cloclt Frequency

;I'

V

I I I

..... 1-""

Vee = S.OY

V

I I I
I

-58

-58

60

v~c ~ 5.!V

-52

-56

-58

30

16

~

i"'"

0

TEMPERATURE (Oc)

Full-Scale Error PSRR
vs Temperature

-46

-60

12

-30 L...JL..l-1-1-'--'--'--'--...L..J
-60
-20
20
60
100
140

Zero Error PSFiR
VB Temperature

-52

-::

a

fCLK =10MHz

15

-25 ~~~-+-++-+-t--H

TEMPERATURE (Oc)

....
.:!!.

'<

5 -20~~~-+-++~~~~

-8
-12

::~:S=EI,~'~:~

B -15 Hf-'~qr--:-t-t--++++-l

....

-4

HH--t--t-t--t VREF = 2.G5V
-10

""

vee=·v.I.1

Vcc=5V.!.

!

UI

Supply Current
vs Temperature

II
-20

TEMPERATURE (Oc)

20

60

100

140

v~c ~ 4.!V

T = 25°C

o

2

4

6

8

10

CLOCK FREa. (MHz)

TEMPERATURE (Oc)

TL/H111261-2

Typical Reference Performance Characteristics
Bandgap Voltage

Line Regulation
vs Temperature

VB Temperature

2.660

:E

...::>

2.6

....

2.655

/

...
a..

,

0

2.650

fi

'"~...

'"

.5
l:;
~

If

/
2.2

~

2.0

-20

20

60

100

/'

2.4

2.645

2.640
-60

= 4mA

'>

::>

tl

,.

Vee = 5V:l:l0%
IL

1.8
-60

140

V

V

-20

II

1/

20

60

100

140

TEMPERATURE (DC)
TLlH111261-3

TL/H111261-4

3-45

TRI-STATE Test Circuits and Waveforms
DVee

CS
DATA
t - -....----4I~- OUTPUT
tOka

DATA
OUTPUTS

DVCC

-1

50"

GNO~"'H

'

DVcc~,
ONO

-----..;;;:=-

TUH/11261-6

TL/H/11261-5

DVec
DVee

CS

10ka

DATA
t - -....--4~- OUTPUT
OATA
OUTPUTS

-1

.. &

DVCC

50"

DVcc
ONO

_

'0"
TL/H/11261-8

TUH/11261-7

Timing Waveforms
Data Output 1'ImIng

Data Input Timing
elK

elK

00

TL/H/11261-10

01

TLlH/11261-9

Timing Diagrams
elK

CS

01

l ~-----------~

I.

At

I-----Instructlon

VOUT

____________~r

DI

D2

D3

D4

05

Byt.,----.~I

061;:,1
;

M

-------+"~
Settltcl to '/2 lS8

i

Is+

• I
I
I

•:
TL/H/11261-11

FIGURE 1. Write to One DAC with Update of Output (AU = 1)

3·46

Timing Diagrams (Continued)

, '.' ",'1";1 ,r;;1L ,

elK

_______

~

~v

L..J'~I

Cs~~______________________~------r-

LJ

DI~

I

"'1.o----lnstrUCtiDn

~"

DATA BITS·

Byt.,----.~I

TUH/11261-12

, OACs are written to LSB first.
OACI is written to first, then OACs 2, 3, and 4.

FIGURE 2. Write to All DACs with Update of Outputs (AU = 1)

elK

Cs

01

l

~

__________________ ____ ____
~

~

~r

'~I________~A_l~A_O~~~~~~~~~'~~~~'~~~~

~

I.

f.o------Instructlon

DO

Byt.-----.~I

TRISTATE

FIGURE 3. Read One DAC, DO Changes on Failing Edge, DO LSB First

01

om

TUH/II261-13

= 1)

•

, ' ... ,1;1
____
.."LJrJLJI

elK

Cs

MSB~

I

lSB

~

l
~

___----'nL---!"'_
~~'''''''>''-·'
_
__

'''-''I'

~I

I.

1+------lnst=tiDn Byt.------.......
DO

TRISTATE

.. ,
DATA BiTS·
TL/H/11261-14

'OACI is read first, then oJiCs 2, 3, and 4.

FIGURE 4. Read All DACs, DO LSB First, DO Changes on Falling Edge

"0'

3·47

om ,,; 1)

.

1ft

Z

u

Block Diagram

~
8k

19

VOUT1

2
VBrAS1

AU

4

VOUT2

eLK

cs

MICROWIR£T11

INT

AND

8k

LOGIC
14

DI

VOUT3

13

DO

VBrAsz

11
Vouu

TUH/11261-15

Pin Description
Voun(19)
VOUT2(1)
VOUT3(14)
VOUT4(11)
VREFOUT(16)

VBIAS1(2)
VBIAS2(13)

GND(7)
DVcc(10)
AVCC(17)

The voltage output connections of the
four DACS. These provide output
voltages in the range O.3V-2.SV.

AU(4)

When this pin is taken low, all OAC outputs
will be asynchronously updated. CS must be
held high during the update.
The voltage reference inputs for the four
DACs. The allowed range is OV-2.75V.

VREF1(1S)
VREF2(20)
VREF3(15)
VREF4(12) .
CS(3)
The Chip Select control input. This input is
active low.
CLK(5)
The external clock input pin.
01(9)
The serial data input. The data is clocked in
LSB first. Preceding the data byte are 4 or 6
bits of instructions.
00(6)
The serial data output. The data can be
clocked out either MSB or LSB first,and on
either the positive or negative edge of the
clock.
INT(S)
The power interrupt output. On an
interruption of the power supply, this pin
goes low. Since this pin has an open drain
output, a 10 kO pull-up resistor must be
connected to the supply.

The internal voltage reference output.
The output of the reference is 2.65V
±2%. This pin should be bypassed with
a 220 "F capacitor.
VBIASl is connected to the non-inVerting
inputs of output amplifierS 1 and 2,
thereby setting the virtual ground
voltage for OAC's 1 and 2, while VBIAS2
performs this function for OAC's 3 and 4.
The allowed range isO.3V -1.4V.
The system ground pin. Connect to
clear) ground point.
The digital and analog power supply
pins. The power supply range of the
DACOS54 is 4.5V - 5.5V. To guarantee
accuracy, it is required that the AVec
and DVcc pins be bypassed separately
with bypass capacitors of 10 J£F
tantalum in parallel with 0.1 "F ceramic.
3-48

Applications Information
FUNCTIONAL DESCRIPTION

The current output IOUT2 is applied to the internal output
amplifier and converted to a voltage. The output voltage of
each DAC is a function of VBIAS, VREF, and the digital input
word, and is given by

The DACOB54 is a monolithic quad B-bit digital-to-analog
converter that is designed to operate on a single 5V supply.
Each of the four units is comprised of an input register, a
DAC register, a shift register, a current output DAC, and an
output amplifier. In addition, the DACOB54 has an onboard
bandgap reference and a logic unit which controls the internal operation of the DACOB54 and interfaces it to microprocessors.
Each of the four internal B-bit DACs uses a modified R-2R
ladder to effect the digital-to-analog conversion (Figure 5).
The resistances corresponding to the 2 most significant bits
are segmented to reduce glitch. energy and to improve
matching. The bottom of the ladder has been modified so
that the voltage across the LSB resistor is much larger than
the input offset voltage of the buffer amplifier. The input
digital code determines the state of the switches in the ladder network. The sum of currents loun and IOUT2 is fixed
and is given by
I
OUT1

DATA
VOUT = 2 (VREF-VBIAS)-256

511

255·

12B

12B

+ -VBIAS--VREF

The output voltage range for each DAC is 0.3V-2.8V. This
range can be achieved by using the internal2.65V reference
and a voltage divider network which provides a VBIAS of
1.40V (Figure 6). In this case the DAC transfer function is
.
(DATA)
VOUT = 2.5~

+ 0.310

The output impedance of any external reference that is
used will affect the accuracy of the conversion. In order that
this error be less than "h LSB, the output impedance of the
external reference must be less than 7.Bfl.

+I

- (VREF - VBIAS) 255
OUT2 R
256
3R

VREF

-t--...,.--t-'\M....,.""",.,....IP-'IM....JVo.,.,....P--.....-

_ _- - - .

VOUT

TL/H/11261-16

FIGURE 5. Equivalent Circuit of R-2R Ladder and Output Amplifier

•

VREF1

10.0k

VOUT1
VBIASI

~.11'

VREF2
VOUT2

~--I-- VOUT3

11.3k
'£201'

~.11'.J:2.01'

-

5V
TL/H/11261-17

FIGURE 6. Generating a VBIAS = 1.40V from the Internal Reference
3-49

,~
II)

I

r---------------------------------------------------------------------------------,
Digital Interface
Table I lists the instruction set for the WRITE mode when
writing to only a single DAC, and Table II lists the instruction
set for a global write. The DA.Gs are always written to LSB
first All DACs will be written to if the global bit (G) is high;
DAC 1 is written to first, then DACs 2, 3 and 4 (in that order).
If the update bit is high, then the DAC output will be updated
pn the rising edge of CS; otherwise, the new data byte will
be placed only in the input register. Chip Select (CS) must
remain low for at least one clock cycle after the last data bit
has been entered. (See Figures 1 and 2)

The DAC0854 has two interface modes: a WRITE mode
and a READ· mode. The WRITE mode is used to convert an
8-bit digital input word into a voltage. The READ mode is
used to read back the digital data that was sent to one or all
of the DACs. These modes are selected by the appropriate
setting of the RD/WR bit, which is part of the instruction
byte. The Jnstruction byte precedes the data byte at the 01
pin. In both modes, a high level on the Start Bit (SB) alerts
the DAC to respond to the remainder of the input stream.

TABLE I. WRITE Mode Instruction Set (Writing to a Single DAC)
SB

RD/WR

Bit #1

Bit #2

1

0

0

0

0

0

1

0

0

0

0

1

Write DAC 2, no update of DAC outputs

0

Write DAC 3, no update of DAC outputs

U

G

AI

AO

Description

Bit #3 Bit #4 Bit #5 Bit #6
Write DAC 1, no update of DAC outputs

1

0

0

0

1

1

0

0

0

1

1

Write DAC 4, no update of DAC outputs

1

0

0

1

0

0

Write DAC 1, update DAC 1 on CS rising edge

1

0

0

1

0

1

Write DAC 2, update DAC 2 on CS rising edge

1

0

0

1

1

0

Write DAC 3, update DAC 3 on ~ riSing edge

1

0

0

1

1

1

Write DAC 4, update DAC 4 on CS rising edge

TABLE II. WRITE Mode Instruction Set (Writing to all DACs)'
SB

' RDiwR

G

U

Bit #3

Bit #4

Description

Blt# 1

Bit #2

1

0

~

0

Write !ill DACs, no update of outputs

1

0

1

1

Write all DACs, update all outputs on CS rising edge

.....
"

3-50

Digital Interface (Continued)
Table III lists the instruction set for the READ mode. By the
appropriate setting of the global (G) and address (A1 and
AO) bits, one can select a specific DAC to be read, or one
can read all the DACs in succession, starting with DAC 1.
The RtF bit determines whether the data changes on the
rising or the falling edge of the system clock. With the RtF
bit high, the data changes on the rising edge that occurs 1%
clock cycles aiter the end of the instruction byte. With the
RtF bit low, the data changes on the falling edge that oc-

curs 1 clock cycle aiter the end of the instruction byte. One
can choose to read the data back MSB first or LSB first by
setting the MtL bit. (See Figures 3 and 4)
An asynchronous update of all the DAC outputs can be
achieved by taking AU low. The contents of the input registers are loaded into the DAC registers, with the update occurring on the falling edge of AU. CS must be held high
during an asynchronous update.
All DAC registers will have their contents reset to all zeros
on power up.

TABLE III. READ MODE Instruction Set
SB

RD/WR

G

RIF

MIL

A1

AO

Bit #1

Bit #2

Bit #3

Bit #4

Bit #5

Bit #6

Bit #7

Description

1

1

0

0

0

0

0

Read DAC 1, LSB first, data changes on the falling edge

1

1

0

0

0

0

1

Read DAC 2, LSB first, data changes on the falling edge

1

1

0

0

0

1

0

Read DAC 3, LSB first, data changes on the falling edge

1

1

0

0

0

1

1

Read DAC 4, LSB first, data changes on the falling edge

1

1

0

0

1

0

0

Read DAC 1, MSB first, data changes on the falling edge

1

1

0

0

1

0

1

Read DAC 2, MSB first, data changes on the falling edge

1

1

0

0

1

1

0

Read DAC 3, MSB first, data changes on the falling edge

1

1

0

0

1

1

1

Read DAC 4, MSB first, data changes on the falling edge

1

1

0

1

0

0

0

Read DAC 1, LSB first, data changes on the rising edge

1

1

0

1

0

0

1

Read DAC 2, LSB first, data changes on the rising edge

1

1

0

1

0

1

0

Read DAC 3, LSB first, data changes on the rising edge

1

1

0

1

0

1

1

Read DAC 4, LSB first, data changes on the rising edge

1

1

0

1

1

0

0

Read DAC 1, MSB first, data changes on the rising edge

1

1

0

1

1

0

1

Read DAC 2, MSB first, data changes on the rising edge

1

1

0

1

1

1

0

Read DAC 3, MSB first, data changes on the rising edge

1

1

0

1

1

1

1

Read DAC 4, MSB first, data changes on the rising edge

1

1

1

0

0

1

0

Read all DACs, LSB first, data changes on the falling edge

1

1

1

0

1

1

0

Read all DACs, MSB first, data changes on the falling edge

1

1

1

1

0

1

0

Read all DACs, LSB first, data changes on the rising edge

1

1

1

1

1

1

0

Read all DACs, MSB first, data changes on the riSing edge

Power Fall Function

Power Supplies

If a power failure occurs on the system using the DAC0854
then the iN'i' pin will be pulled low on the next power-up
cycle. To force this output high again and reset this flag, the
GS pin will have to be brought low. When this is done the
iN'i' output will be pulled high again via an external 10 kO
pull-up resistor. This feature may be used by the microprocessor to discard data whose integrity is in question.

The DAC0854 is designed to operate from a + 5V (nominal)
supply. There are two supply pins, AVec and DVcc. These
pins allow separate external bypass capacitors for the analog and digital portions of the circuit. To guarantee accurate
conversions, the two supply pins should each be bypassed
with a 0.1
ceramic capacitor in parallel with a 10
tantalum capacitor.

,...F

3-51

,...F

•

•

In

,~

~
c'

Typical Applications
10k

10.2k

1M

> .....- VOUT ,
AVec
VOUT1

470k

VREf1

1-....- - - ,

VREF OUT

30.1k

VBIAS11----....

10k,

DAC0854

TUH/11261-18

FIGURE 7. Trimming the Offset of a 5V Op Amp Biased at Mid Supply

14k
1M
>+-VOUT
AVec
VOUT1
VREF1

470k

lk

VREF OUT

215k

~201'r
VBIASl

200k

DAC0854

, TUH/11261-19

F:IGURE 8. Trimming the Offset of a Dual Supply Op Amp Blased·at Ground

VOUT
10.0k

75k
VOUT1

VREF1 1-....- -....-,.....

VREF OUT

10.0k

VBIAS11----....

DAC0854

11.3k

TL/H/11261-20

FIGURE 9. Bringing the Output Range Down to Ground

3·52

~o

IJ1National Semiconductor

CD
CD

o

DAC0890
Duai 8-bii f.LiP-CompaiullJie

DH~Hta';mto-Ai1a;og

General Description

[J

Converter

Guaranteed monotonic over temperature

IJ Internal precision bandgap reference

The DAC0890 is a complete dual 8-bit voltage output digitalto-analog converter that can operate on a single 5V supply.
It includes on-chip output amplifiers, precision bandgap voltage reference, and full microprocessor interface.

[J

Two calibrated output ranges; 2.55V and 10.2V

IJ 2 ,...s settling time for full-scale output change
[J

No external trims

Each DAC0890 output amplifier has two externally selectable output ranges, OV to 2.55V and OV to 1O.2V. The amplifiers are internally trimmed for offset and full-scale accuracy
and therefore require no external user trims.

IJ Microprocessor interface

The DACP890 is'supplied in 20-pin ceramic DIP package.

c Automotive controls
C Disk drive motor controls
IJ Automatic test equipment

Applications
IJ Industrial processing controls

features
.. Two 8-bit voltage output DACs
.. 4.75V to 16.5V single operation

Block Diagram
DGHD

CSi

csz

WR

080-DB7

y+

TL/H/l 0592- I

Ordering Information
Industrial ( - 40'C ,,; TA ,,;
DAC0890CIJ

+ 05"C)

Connection Diagram
Dual-In-Line Package

Pacl(age
J20ACerdip

(LSB) DBO

1

20

v-

OBI

2

19

SENSE 1

DB2

3

18

VOUT1

DB3

4

17

SELECT 1

DB4

5

DB5

6

16

AGHD

15

5El.ECT2

DB6

14

(USB) DB7

13

VOUT2
SENSE 2

9

12

DGHD

10

11

CSZ

WR
CSi

DAC0890

TL/H/l0592-2

Top View

3-53

•

Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Positive Supply Voltage (V+)
Voltage at Any Pin (Note 3)

Soldering Information

20V
GND -0.3toV+ +0.3V

Input Current at Any Pin (Note 3)

5mA

Package Input Current (Note 4)

20mA

Power Dissipation (Note 5)
ESD Susceptability (Note 6)

300"C
- 65°C to 150"C

Junction Temperature

(Note 5)

Operating Ratings (Notes 1 & 2)
Temperature Range
TMIN S; TA S; TMAX
DAC0890CIJ

1.0W
2000V

-40"C S; TA S; +85°C
4.75 to 16.5V

Positive Supply Voltage, V +

Output Short-Circuit Protection
Duration

J package (10 sec.)
Storage Temperature

Indefinite

+

Electrical Characteristics The following specifications apply for V+

= + 5V and V+ =
15V and AGND =
DGND = OV, unless otherwise specified. Boldface limits apply forTA = TJ = TMIN toTMAXi all other limits TA = TJ = 25°C.

Symbol

Typical
(Note 7)

Limit
(Note 8)

Units

Resolution

8

Bits(min)

Monotonicity

8

Bit(min)

Parameter

Conditions

±O.5

LSB(min)

Fullscale Error

±0.16

±1.5/±2.5

LSB(max)

Zero Error

±1.0/±2.0

LSB(max)

Integral Linearity Error

Full Scale DAC-to-DAC
Tracking (Note 9)

±0.25

LSB

-74
-66

dB
dB

Glitch Energy
(Note 11)

45

V-ns

Digital Feedthrough
(Note 12)

60

V-ns

2
3

p's
p.s

Analog Crosstalk
(Note 10)

V+ = 15V, 10.2V range
V+ = 5V, 2.55V range

ts

Positive Output Settling
Time (Note 13)

ClOAD S; 500 pF
ClOAD S; 1000 pF

10

Output Current Drive
Capability

(Note 14)

Isc

Output Short Circuit
Current (Note 15)

V+ = 15V

PSRR

Power Supply Rejection
Ratio
(Nole 16)

f < 30Hz
10.2Vrange
13.5V S; V+ S;16.5V

7

15

ppm/% (max)

2.55Vrange
13.5V S; V+ S; 16.5V
4.75V S; V+ S; 5.25V
4.75V S; V+ S; 16.5V

4
4
4

59
20

ppm/%(max)
ppm/%(max)
ppm/%

All Inputs Low
V+ = 16.5
V+ = 4.75

25
23

30/35

mA(max)
mA

IS

Supply Current

8

5/3.5

20

mA(min)
mA

VILD

Data Logic Low Threshold

0.8

V (max)

VIHD

Data Logic High Threshold

2_0

V (min)

Vile

Control Logic Low
Threshold

0.8

V (max)

3-54

Electrical Characteristics (Continued)
The following specifications apply for V+

Boldface limits apply for TA
Symbol

=

TJ

=

=

+5V and V+

=

+ 15V and AGND

TMIN to TMAX; all other limits TA

Parameter

Conditions

=

TJ

=

=

DGND

=

OV, unless otherwise specified.

25'C.

Typical
(Note 7)

Limit
(Note 8)

Units

2.2

V (min)

Control Logie High

VIHC

Threshold
2.2

25

/LA (max)

tWR

Write Time

18

40

ns(min)

tos

Data Setup Time

18

35

ns(min)

Digital Input Current

(Note 17)

tOH

Data Hold Time

3

tcs

Control Setup Time

18

tcH

Control Hold Time

ns(max)

40

ns(min)

0

ns(max)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operaling
the device beyond Its specified operating ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee performance limits.
For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test c9nditions listed. Some
performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to AGND, unless otherwise specified.
Note 3: When Ihe input voltage (VIN) at any pin exceeds the power supply rails (VIN

< AGND or VIN > V+) the absolute value of current at thai pin should be

limited to 5 rnA or less.
Note 4: The sum of the currents al all pins that are driven beyond the power supply voltages should not exceed 20 rnA.

Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX. 8JA and the ambient temperature, TA. The maximum
allowable power dissipation al any temperature is Po = (TJMAX - TA)/6JA or the number given in the Absolule Maximum Ratings, whichever is lower. The
TJMAX("C) and 6JA("C/W) for Ihe DAC0890CIJ are 125'C and 53'C/W, respectively.

I
I

Part Number
DAC0890CIJ

I
I

TJMAX("C)
125

I
I

6JA("C/W)
53

I
I

Note 6: Human body model, 100 pF discharged through a 1.5 kO resistor.
Note 7: Typicals are at 25'C, unless otherwise specified, and represent the most likely parametric norm.
Note 8: Guaranteed to National's AOQL (Average Oulgoing Quality Level).
Note 9: Full Scale DAC-to·OAC Tracking is defined as the change In the voltage difference between Ihe full scale output levels of OA91 and DAC2. The result Is
expressed in LSBs and il referred to the full-scale voltage difference at 25'C.
Note 10: Analog Crosstaik is a measure of the change in one DAC's full scale output voltage as the second DAC's output voltage changes value. Ills measured as
the voltage change in one DAC's full scale output voltage divided by the voltage range through which the second DAC's output has changed (zero 10 full scale).

This ratio is then expressed in dB.
Note 11: Glitch Energy is a worst case measurement, over the entire input code range, of transients that occur when changing code. The positive and negative

areas of the transient waveforms are summed together to obtain the value listed.
Note 12: Digttal Feedthrough is measured with both OAC outputs lalched at full scale and a 2 ns, 5V step applied 10 all 8 data inputs. This gives the worst case
digital feedthrough for the DAC0890.
Note 13: Settling TIme is specified for a positive full scale step to ± '12 LSB. Settling time for negative steps will be slower but may be improved with an external
pull·down resistor. Negalive settling lime to ± Yo LSB can be calculated for each range where Is = 6.23 (CLoAm (RLOAO/l0 kO) for the high range and Is = 6.23
(CLOAO) (RLOAD/2.5 kO) for the low range.
Note 14: Output Current Drive Capability is the minimum current that can be sourced by the output amplifiers wilh less Ihan
sinking capability is provided by a passive internal resistance of 10 kO in the high range and 2.5 kO in the low range.

Yo LSB reduction in full scale. Currenl

Note 15: Output Short Circuit Current is measured with the output at full-scale and shorted to AGND.
Note 16: Power Supply Rejection Ratio is a measure of how much the output voltage changes (in parls-per-million) per change (in percent) in Ihe power supply
voltage.
Note 17: Digital Input Current is measured with OV and V+ input levels. The limit specified is the higher of these two measurements.

3·55

•

I

Typical Performance Characteristics
Offset Drift
vs Temperature

Fullscale Drift
vs Temperature

G.4

0.6

1.0

~

,

'\.
i'.. ,....

--100..

.....

-55

25

85

-55

125

-15

....

25

-

t--.

I

2.55Y Range

t--.

85

o

-55

125

:.- r-T

-, "

25

85

....

--

-15

i '\
i"i ,
......
20

Temporature (etc)

2.0

4.75YSV+SI6.5V

30

1--"'"

t-

~

1/

'"

1os=1wR
1a!=5nl

25

Temperature (etc)

85

125

2.0

4.75YSV+ S 16.5V

1.8

1.6

.., 1.6

J 1~

-15

25

85

125

I

i!: 1~

4.75Y SY+ S 16.5V

", r". .....

,.~

,....

i' ....

11.2

1.0

1.0

0.8

0.8

-55

"

'" /

. /V

Control Threshold
vs Temperature

1.8

~ 1.2

10

-15

~

l"- t-

Temp,ralure (etc)

Data Threshold
vs Temperature

55

/

-55

125

10.2Y Ran~

2.5SY f"nr

o
85

I\..

5

Temperalure (etc)

Write Time
vs Temperature

,/

15

10.2Y Range

25

125

25

cil

-55

85

!O

10

125

25

Power Supply Rejection
vs Temperature

-95

-15

-15

T'mperature (etc)

Analog Crosstalk
vs Temperature

G.4

....

O.1

Temperalure (etc)

-55

-55

V

-0.2
-15

Fullscale Dac to Dac
Tracking
vs Temperature

15

V

"

Temperature (etc)

-0.4
-55

0.3

/

'\

-1.0

!

Integral Linearity
vs Temperature

-15

25

Temperature (etc)

85

125

-55

-15

25

85

125

T,mperalure (etc)
TUH/l0592-3

3-56

I

Typical Performance Characteristics
Supply Current
vs Temperature

Short Circuit Current
vs Temperature

30

~

25

2D

4.0

40

-

V+= 16.5V

-l-J.

1
a ,,"~

Digital Input Current
VI Temperature

V+=4.75V

r--. r--.

!
1
a
~

30

V+=~
2D

}

~

15
-55

-15

85

25

-

10

-55

125

I- ~

V+=4.75V

tl

Tempe",tu .. (CC)

-15

85

25

125

Minimum Supply Voltage
vs Temperature
(10.2V Range)

r- t-

Minimum Supply Voltage
vs Temperature
(2.55V Range)

I

~~skt,/

r-- ....

I
-15

25

85

125

VI Temperature

CIII

-55

15

25

Max Power Dissipation

u

-........

-15

Tompora.... (CC)

&.0

-

-55

Temperature (CC)

13

4.7SV. V+:IS II.5V
Inpul=OV

-55

125

Temp.",t... (CC)

-15

25

85

CIIJ

I

125

T.mp....turo (CC)

Power Supply Rejection
vs Frequency
105

~
E

,5

I
~

!

J

104
105
102

&I

101
100

Freq.ency (Hz)
TUHII0592-4

3-57

Q

en
co

Q
(.)

Timing Waveforms

g

tcs

CS1;2
tCH

,1.
,

tWR

"

WR
tos

!.
DATA

,vouT i.2

tDH

DATA VALID

','

Settled to 1/2 LSB

1-------.,-'-t5 -,- - - - - - 1

3-58

TL/H/10592-5

Connection Diagram
Dual-In-Llne Package

20 r-V+
19 r-SENSE 1

(LS8) 080- 1

081- 2

092- 3
083- 4

084- 5
085- 6

DAC0890

OB6- 7

18 r-VOUT1
17 -SELECTI
16 -AGND
15 -SELECT2
14 rVOUT2
13 r-SENSE2

(IotS8) 087- 8

Wii-9

12 r-OGNO

CS1- 10

11 r-CS2
TL/H/10592-2

Pin Description
DBO-DB7 (1-8) These pins are data inputs for each of the
internal 8-bit DACs. DBO is the least-sig-

VOUT2 (14)

DAC2's voltage output connection. It provides two full-scale output voltage ranges,
2.55V and 10.2V.

This Is the WRITE command input pin.
This input is used in conjunction with
and "CS2 to write data into either of the
internal DACs. The data is latched into a
selected DAC with the rising edge of either WR or ~ for DAC1 or CS2 for
DAC2, whichever occurs first.
This is the input pin used to select DACI.
This input is used In conjunction with the
WR input to write data into either of the
Internal DACs. The data is latched into
DAC1 with the rising edge of either CSI or
WR, whichever occurs first.

SELECT 2 (15)

The two output voltage ranges available
from DAC2 are selected by connecting
this pin to SENSE2 for the 2.55V full-scale
range and leaving it unconnected for the
10.2V full-scale range.
The system digital ground is connected to
this pin. For proper operation, this and
DGND must be connected together.
The two output voltage ranges available
from DACI are selected by connecting
this pin to SENSEI for he 2.55V full-scale
range and leaving it unconnected for the
10.2V full-scale range.

This is the input pin used to select DAC2.
This input is used in conjunction with the
WR input to write data into either of the
internal DACs. The data is latched into
DAC2 with the rising edge of either CS2 or
WR, whichever occurs first.
The system digital ground is connected to
this pin. For proper operation, this and
AGND must be connected together.

VOUT1 (18)

niflcant-bit.
WR(9)

CS1 (10)

i5S2 (11)

DGND(12)

SENSE 2 (13)

cs-r

AGND (16)

SELECT 1 (17)

SENSE 1 (19)

V + (20)

DAC2's' output sense connection. When
this pin is connected to the VOUT2's load
impedance, the feedback loop will compensate for any voltage drops between
the VOUT2 pin and the load.

3-59

DAC1's voltage output connection. It provides two full-scale output voltage ranges,
2.55V and 10.2V.
DAC1's output sense connection. When
this pin is connected to the VOUT1's load
impedance, the feedback loop will compensate for any voltage drops between
the VOUTI pin and the load.
The power supply voltage, ranging from
4.75V to 16.5V, is applied to this pin. It
should be bypassed, to AGND, with a 0.01
- 0.1 p.F ceramic capacitor in parallel
with a 2.2 - 22 p.F electrolytic capacitor.

II

C) r-------------------------------------------~--------~------~------------------,
G)

co

C)

~

Functional Description
The DAC0890 is a monolithic dual 8-bit bipolar Digital-to-Analog converter comprising six major functional blocks designed to operate on a single supply as low as 5V (±5%).
These include two latch/DAC combinations, two high-speed
output amplifiers, band-gap reference, and control/interface
logic.
'

externally set through the range select pin. The two ranges
araOV to 2.55V and OV to 10.2V. The internal resistors that
set the gain are matched to the unit resistor of the R/2R
ladder. This ensures that these resistors match over process variations and temperature. This greatly reduces gain
variatioris that would exist if external gain setting resistors
were used.

The two internal 8-bit DACs use equal valued current sources. Controlled by a corresponding bit in the input data, each
current source's output is switched into either an R/2R ladder or AGND. Each internal DAC has an 8-bit latch to store
a digital input. See Figure 1.
The high-speed output amplifiers operate in the non-inverting mode. The R-2R's output current is applied to the output
amplifier and converted to a voltage. The amplifier's gain is

An' internal band-gap reference and its control amplifier generate a full scale reference voltage for the DACs. It produces a 1.2V output from a single supply.
The DAC0890 provides a TIL and CMOS-compatible control inte,rface and allows writing and latching digital values to
each of the internal DACs.

Vour

t-¥v"v---o SENSE
t-¥V"v---o SELECT
t - - - - - o AGND
TUH/10592-7

FIGURE 1_ Simplified Internal Schematic (One DAC Shown), "

"

3-60

--.

Applications Information

Grounding and Power Supply
Bypassing

Full-Scale Output Voltage Range Selection
The DAC0890 has been designed for ease of use. All refer·
ence voltage and output amplifier connections are internal.
All trims such as full-scale (gain) and zero (offset) are performed during manufacturing. Therefore, no external trimming is required to achieve the specified accuracy. The only
external connections required select the desired full-scale
output voltage range.

Proper grounding is essential to extract all the precision and
full rated performance that the DAC0890 is capable of delivering. Typical applications for the DAC0890 include operation with a microprocessor. In this environment digitalnQise
is prevalent and anticipated. Therefore, special care must
be taken to ensure that proper operation will be achieved.
The DAC0890 uses two ground pins, AGND and DGND, to
minimize ground drops and noise in the analog signal paths:
Figure 3 details the proper bypassing and ground connections.
-

The tWo full-scale output voltage ranges are selected by
connecting SENSE, SELECT and VOUT as shown in Figure
2a, b. The 2.55V range can be used with supply voltages as
low as 4.75V. The 10.2V range can be selected with supplies as low as 12.0V.

The DAC0890's best performance can be ensured by connecting 0.01 }.tF to 0.1 }.tF ceramic capacitor in parallel with
an electrolytic of 2.2 }.tF to 22 }.tF between the V+ pin and
AGND.

From
R-2R ladder---....

output

Sense Inputs
The SENSE inputs (pins-13 and 19) allow compensation for
voltage drops in long output lines to remote loads. This
places the drops in the internal amplifier's feedback loop.
An example of this is shown in Figure 3. The I-R drop, which
might be caused by printed circuit board traces or long cables, between the VOUT2 and the load impedance RL is
placed inside the feedback loop if SENSE1 is connected
directly to the load. This forces the .voltage at the load to be
the correct value. It is important to remember that the voltage at the DAC0890's VOUT pins may become higher than
the full-scale· output voltage selectE!d using the. SELECT
pins. Therefore, the power supply voltage applied to V+
must be ~ 2.2V above the resulting output voltage, (at pins
14 and 18) when the SENSE inputs are l;Isect '

AGND
16

TLlH/l0592-B

FIGURE 2a. OV to 2.55V Output Voltage Range

From
R - 2R ladder - - -....

The SENSE inputs have a finite input impedance. The
range-setting resistors load the output with 2.5 kG when the
OV to 2.55V range is selected and 10 kG when the OV to
10.2V range is selected.

output

+15V

SELECT
17(15)
(LSB) DBO

AGND

DBl

16

OV to 10.2V

DB2

N.C.

DB3
DB4

TLlH/l0592-9

FIGURE 2b. OV to 10.2V Output Voltage Range

DB5

DAC0890

To System
Analog Ground
OV to 2.55V

DB6

Power Supply Voltage

(MSB) DB7

Viii
CS1

The DAC0890 is designed to operate on a single power
supply voltages +4.75V and + 16.5V. For 2.55V full-scale
operation the power supply voltage can be as low as
+4.75V. When the 10.2V full-scale is used the supply voltage needs to be between + 12V to + 16.5V.

CS2o--=====..J

RL

TLlH/l0592-10

FIGURE 3. Typical Connection Showing Power Supply
Bypassing, and the Use of SENSE Inputs

3-61

&I

I

is offset and scaled to achieve a -1.27V to + 1.28V output
range with the addition of a -5V supply. The required offset
is generated with an LM385-1.2V reference. The external
output amplification is provided by the LMC660. The output
voltage is generated with a complementary binary offset input code.

Minimizing Settling Time
The DAC0890's output stage uses a passive pull-down resistor to achieve single supply operation and an output voltage rang", that includes ground. This results in a negativegoing settling time that is longer than the settling time or
positive-going signals. The actual settling time is dependant
on the load resistance and capacitance. If available, a negative power supply can be used to improve the negative settling time by connecting a pull down resistor between the
output and the negative supply. The resistor's value is chosen so that the current through the pull down resistor is not
greater than 0.5 mA when the output voltage is OV. See

Microprocessor Interface
When interfacing with a microprocessor, the DAC0890 appears as a two byte write-only memory location for memory
mapped and I/O mapped input-output. Each of the internal
DACs is chosen through one of the two chips selects, CS1
or CS2. The action of the control Signals is detailed in Table
I. The data is latched on the rising edge of either Chip Select or WR, whichever occurs first for a given selected DAC.
For interfacing ease, WR can be tied low and CS1 or CS2
can be used to latch the data. Both DACs can be updated
simultaneously by pulling both ~ and CS2 low. Further
versatility is provided by the ability of WR and CS1 and/or
CS2 to be tied together.

F1gU1'fJ4.

TABLE I DAC0890 Control Logic Truth Table
Input
Data

(In k4)

0
1

TUH/l0592-11

FIGURE 4. Improving Negative Slew Rate

0

Bipolar Operation

1
0
1

While the DAC0890 was designed to operate on· a single
positive supply voltage and generate a unipolar output voltage, bipolar operation is still possible if a negative supply is
available or added. As shown in Figure 5, the output voltage

WR

CS

DACData

0

0

0

0
0

0
1

t
t

0

t
t

X

0
0
1

X

X

X

1

1
1

X

Latch
Condition

0
1
0
1
previous data
previous data
previous data

"transparent"
"transparent"
latching
latching
latching
latching
latching
latching
latching

5k4

""'"

u.t385-1.2V
O~""'

OUTPUT
-1.27V to
•. _+1.28V

___

--J

-5V

TL/H/l0592-12

FIGURE 5. Bipolar Operation

3-62

g
....

(")

tflNational Semiconductor

«:)
«:)

~
C

DAC 1006/DAC 1007/DAC 1008 J-LP Compatible,
Double-Buffered D to A Con"erters

l;
....

«:)
«:)

General Description

Features

The DAC1006/7/8 are advanced CMOS/Si-Cr 10-, 9- and
8-bit accurate multiplying DACs which are designed to interface directly with the 8080, 8048, 8085, Z-80 and other popular microprocessors. These DACs appear as a memory location or an 1/0 port to the IJ.P and no interfacing logic is
needed.
These devices, combined with an external amplifier and
voltage reference, can be used as standard 01 A converters;
and they are very attractive for multiplying applications
(such as digitally controlled gain blocks) since their linearity
error is essentially independent of the voltage reference.
They become equally attractive in audio signal processing
equipment as audio gain controls or as programmable attenuators which marry high quality audio signal processing
to digitally based systems under microprocessor control.
All of these DACs are double buffered. They can load all 10
bits or two 8-bit bytes and the data format is left justified.
The analog section of these DACs is essentially the same
as that of the DAC1020.
The DAC1006 series are the 10-bit members of a family of
microprocessor-compatible DAC's (MICRO-DACTM'S). For
applications requiring other resolutions, the DAC0830 series
(8 bits) and the DAC1208 and DAC1230 (12 bits) are available alternatives.

II Uses easy to adjust END POINT specs, NOT BEST

Part #

Accuracy
(bits)

DAC1006

10

DAC1007

9

DAC1008

8

Pin

Description

20

For leftjustified
data

CONl~L

BUS

STRAIGHT LINE FIT

«:)
«:)

EJ Low power consumption

Direct interface to all popular microprocessors
Integrated thin film on CMOS structure
Double-buffered, single-buffered or flow through digital
data inputs
Loads two 8-bit bytes or a single 10-bit word
Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
Works with ± 10V reference-full 4-quadrant multiplication
Operates STAND ALONE (without IJ.P) if desired
Available in 0.3" standard 20-pin package
Differential non-linearity selection available as special
order

[J
[J

IJ

19
[J

IZI

c
[J
[J

Output Current Settling Time
Resolution
Linearity

[J
[J

Gain Tempco
c Low Power Dissipation
(including ladder)
IJ Single Power Supply
[J

500 ns
10 bits
10,9, and 8 bits
(guaranteed over temp.)
-0.0003% of FS/oC
20 mW
5 to 15 VDC

•

DAC1006/1007/1008
WR

I

Bytl1/Byl12

r

XFER

R

DB7

oB
~

=:OAlA BUS
OBO

==

g

l! +vcr::F~CI

4

3

1

20 14

MICRO·OAC·
13
20 PIN 10

LSB

-v.~

'REF

::>- BOBD BUS

2

CCI

Key Specifications
c

Typical Application

rc

.........
~....

~

lOUT 1

12~0
11

1

IOUT2

>1.
_

OA

VOUl

+

- ' NOTE: FOR DETAILS OF BUS
CONNECTION SEE SECTION 6.0
TUH/5688-1

3-63

Absolute Maximum Ratings

(Notes 1 & 2)

If Military/Aerospace specified devices are required,

ESD Susceptibility (Note 11)
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)

please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
Voltage at Any Digital Input

17Voc
VeetoGND
±25V

Voltage at VREF Input
Storage Temperature Range

Operating Ratings

Package Dissipation at TA = 25·C (Note 3)
DC Voltage Applied to loun or IOUT2
(Note 4)

500mW

260·C
300"C

(Note 1)

Temperature Range
Part numbers with
"LCN" and "LCWN" suffix

- 65·C to + 150·C

BOOV

TMIN

s: TA s: TMAX
O"Cto 70·C

Voltage at Any Digital Input

-100 mVto Vee

VeetoGND

Electrical Characteristics
Tested at Vee = 4.75 Voe and 15.75 VDe, TA=25·C, VREF= 10.000 VDe unless otherwise noted
Parameter

Conditions

See
Note

Vcc= 12Voc±5%
to 15Voc±5%
Mln_
Typ_
Max_

Resolution
Linearity Error

Differential
Nonlinearity

Monotonicity

Endpoint adjust only
TMIN 2.0V

6

VIL =OV, VIH=5V,
TA=25'C

B

TMIN:;;TA:;;TMAX

9

VIL =OV, VIH=5V,
TA=25'C

VIL =OV, VIL =5V,
TA=25'C

tCH

VIL = OV, VIH = 5V,
TA=25'C

nA

200

200

nA

0.7,O.B

Voc
Voc

p.Aoc
p.Aoc

2.0
-40

-150

-40

-150

1.0

+10

1.0

+10

500

500

ns

150
320

60
100

320
500

200
250

ns
ns

9

150
320

BO
120

320
500

170
250

ns
ns

9

200
250

100
120

320
500

220
320

ns
ns

9

150
320

60
100

320
500

1BO
260

ns
ns

9

10
10

0
0

10
10

0
0

ns
ns

TMIN:;;TA:;;TMAX
Control Hold Time

200

......
......

~

.....
o

TMIN:;;TA:;;TMAX
tcs

o

l;
.....

o

TMIN:;;TA,;;TMAX

Control Set Up
Time

200

2.0

tw

VIL =OV, VIH=5V
TA=25'C

Max.

CO

Write and XFER
Pulse Width

tOH

Typ.

O.B,O.B

VIL =OV, VIH=5V

Data Hold Time

Min.

o
o

10

Is

tos

Max.

......
Units

6

Current Settling
Time

Data Set Up Time

Typ.

Vcc= 5Voc± 5%

TMIN,;;TA:;;TMAX

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking.
Note 4: For current switching applications, both faun and IOUT2 must go to ground or the "Virtual Ground" of an operational amplifier. The linearity error is
degraded by approximately VOS+VREF. For example, if VREF= 10V then a 1 mV offset, Vos, on lOUT! or IOUT2 will introduce an additional 0.01 % linearity error.

Note 5: Guaranteed at VREF= ±10 Voc and VREF= ±1 Voc.
Note 6: TMIN=O'C and TMAX=70'C for "LCN" and "LCWM" suffix parts.
Note 7: The unit "FSR" stands for "Full Scale Range." "Linearity Error" and "Power Supply Rejection" specs are based on this unit to eliminate dependence on a
particular VREF value and to indicate the true performance of the part The "Linearity Error" specification of the DACI006 is "0.05% of FSR (MAX)." This
guarantees that after performing a zero and full scale adjustment (See Sections 2.5 and 2.6), the plot of the I 024 analog voltage outputs will each be within
0.05%XVREF of a straight line which passes through zero and full scale.
Note 8: This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (tw) of 320 ns. A typical part will operate with tw
of only 100 ns. The entire write pulse must occur within the valid data interval for the specified tw, tos, tOH, and Is to apply.
Note 9: Guaranteed by design but not tested.
Note 10: A 200 nA leakage current with Rfb=20K and VREF=IOV corresponds to a zero error of (200XIO-9X20XI03)XIOO+IO which is 0.04% of FS.
Note II: Human body model, 100 pF discharged through a 1.5 kO resistor.

3-65

CD ,---------------------------------------------------------------------------------,

g

.-

g

Switching Waveforms

§.-

CS. BYTElIBYTEZ

g
§
.-

OAT~

g

BITS

IOUT1· IOUT2
TL/H/5688-2

Typical Performance Characteristics
Errors vs. Supply Voltage
I.ODD " JNENiITY

g
:Ii

-.025

-.050

:=

-.075

!...

E~ROR
V

i5

E

-.IID

Errors vs. Temperature
'0.100

I I
I I
"lIN~RIT~ ER~OR r-

0.075

~

g

0.050

I

I

0.825
D.DOD

iii

1=:::

5

" BAlM ERROR

-

I- -

500

~

i

I~

"BAlN ERROR

I I

-U7S

400

~ 3DD

I T""

200
100

I I

I
;

5IlD

ui

400

....

.'"

~

!5

~NL!DVI
r- VINH

vc~=Jv

V

' VCC=15V-

VCC=10V

J-P-

),. I-" I-"

I-"

AMBIENT TEMPERATURE ('Cj

Data Hold Time, tOH

.

I

!:

jV

500

_~NL~ovl

1

jNHtVtjV

e

ui 400

.J. J.

300
zoo

tyo

3

-55 -35-15 5 25 45 65 85 105125

Data Setup Time, tos

Control Setup Time, tcs

I

i TTi
II

o

-0.11!!55_35_15 5 25 46 65 B5 105125
AMBIENT TEMPERATURE ('C)

6
10
IS
SUPPLY VOLTADE Vee (VOC)

I-~NL~OV I
NH

I

'iT

0

-.125

Write Width, tw

ill
VCC-l0V VcC=15V-

1\

VCC=5V

100

o

.... ~

,.:... .J. I-" ~
..!.

-55 -35 -15 5

....

.J

~

.LVJC=I'0V
300 Vcc =5V

~

zoo

B
=

100

25 45 65 85 105 125

o

~

.........

V~C=15V

....~

--

-55 -35 -15

TA. AMBIENT TEMPERATURE ('C)

5 25 45 65 85 105 125

TA. AMBIENT TEMPERATURE ('C)

Digital Input Threshold
vs. Temperature
2.4

2.01-+-+-+-\-t--t--l

2.0

E

E

~

~

I.....

1.2

E!

0.1

~

~

ii!:

~

;

0.4
0.0

1.6
1.2

r-- ......
..... r-..

.....
1'0 1"'-0

0.8
0.4

10

0.0

16

-55-35-16 5 25 45 65 85 105126

TEMPERATURE ('C)

SUPPLY VOLTADE VCC (V)

3-66

TUH/5688-3

g

Block and Connection Diagrams
DAC100S/1007l1008 (20·Pin Parts)

(MSB) 019
018
017
016
015
Dl4
013
012
011
(LSB) DID

13

9
8
7
6
5
19
18
17
16
15

11
12
0

10 BIT
MULTIPLYING
01 A CONVERTER

en
......
C

±VREF
IOUT2

Cl

10UTl

Wii

VCC
DI4
DI3
DI2
Dll
Dlo (LSB)

Byt.l/Biii"I

illii
DI5
Dis
DI7
DIB
(MSBI Dig
GNO

XFER STROBE
VCC
CONTROL LOGIC

o

DAC100S/1007/1008
(20·Pln Parts)
Dual·in·Llne Package

RFB

1.1
2nd
BYTE
BYTE
STROBE STROBE

o
.....
o

DACIDDS
DAC1DD7
DACIDDB
14
13
12
11

lD

GNO

RFB
VREF
10UTl
IOUT2
TL/H/S688-28

Top View
See Ordering information
BYTE 11

USE DAC1006/1007/100B
FOR LEFT JUSTIFIED DATA

BYTE 2

TL/H/S688-S

DAC1006/1007/1008-Simple Hookup for a "Quick look"

+~"'o-t-------..,
SWI
lK

+15VOC

>....;........-o+VOUT

o
o
o

lK
_

+15VOC

LSB~15~""""---'--'

'A TOTAL OF 10
INPUT SWITCHES
& 1 K RESISTORS

o Voe .. VOUT .. + VREF

(tm)

-15VOC
TLlH/S688-7

Noles:
1. For VREF= -10.240 VDC the output voltage steps are approximately 10 mV each.
2. SW1 is a normally closed switch. While SW1 is closed, the DAG register is latched and new data
can be loaded into the input latch via the 10 SW2 switches.
When SW1 is momentarily opened the new data is transferred from the input latch to the DAG register and is latched when SW1 again closes.

3-S7

li.....
o

o
......
......

c
.....

»
o
o

oQ)

1.0 DEFINITION OF PACKAGE PINOUTS
1.1 Control Signals (All control signals are level actuated.)
CS: Chip Select -

RFB: Feedback Resistor - This is provided on the IC chip
for use as the shunt feedback resistor when an external op
amp is used to provide an output voltage for the DAC. This
on-chip resistor should always be used (not an external resistor) because it matches the resistors used in the on-chip
R-2R ladder and tracks these resistors over temperature.

active low, it will enable WR.

WR: Write - The active low WR is used to load the digital
data bits· (DI) into the input latch. The data in the input latch
is latched when WR is high. The 10-bit input latch is split
into two latches; one holds 8· bits and the other holds 2 bits.
The Bytel/Byte2 control pin is used to select both input
latches when Bytel/Byte2 = 1 or to overwrite the 2-bit input
latch when in the low state.
Byte1/Byte2: Byte Sequence Control - When this control
is high, all ten locations of the input latch are enabled. When
low, only two locations of the input latch are enabled and
these two locations are overwritten on the second byte
write: On the DAC1006, 1007, and 1008, the Byte1/Byte2
must be low to transfer the 10-bit data in the input latch to
the DAC register.

VREF= Reference Voltage Input - This is the connection for
the external preciSion voltage source which drives the R-2R
ladder. VREF can range from -10 to + 10 volts. This is also
the analog voltage input for a 4-quadrant multiplying DAC
application.
Vee: Digital Supply Voltage - This is the power supply pin
for the part. Vee can be from + 5 to + 15 Voe. Operation is
optimum for + 15V. The input threshold voltages are nearly
independent of Vee. (See Typical Performance Characteristics and Description in Section 3.0, T2L compatible logic
inputs.)

XFER: Transfer Control Signal, active low - This signal, in
combination with others, is used to transfer the 1O-bit data
which is available in the input latch to the DAC register see timing diagrams.

GND: Ground - the ground pin for the part.
1.3 Definition of Terms
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DAC1006
has 2 10 or 1024 steps and therefore has 10-bit resolution.

1.2 Other Pin Functions
011 (i=O to 9): Digital Inputs- Dlo is the least significant bit
(LSB) and Dig is the most significant bit (MSB).

Linearity Error: Linearity error is the maximum deviation
from a straight line passing through the endpoints of the
DAC transfer characteristic. It is measured aiter adjusting
for zero and full-scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.

IOUT1: DAC Current Output 1 - IOUT1 is a maximum for a
digital input code of all 1s and is zero for a digital input code
of all Os.
IOUT2: DAC Current Output 2 IOUT1' or
I
+I
OUT1 OUT2

IOUT2 is a constant minus

National's linearity test (a) and the "best straight line" test
(b) used by other suppliers are illustrated below. The "best
straight line" requires a special zero and FS adjustment for
each part, which is almost impossible for user to determine.
The "end point test" uses a standard zero and FS adjustment procedure and is a much more stringent test for DAC
linearity.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output (which is the worst case).

1023 VREF
1024 R

where R "" 15 kG.

b. Best Straight Line

a. End Point Test After Zero and FS Adj.

DIGITAL INPUT

DIGITAL INPUT
TLIH/S688-8

3-68

Settling Time: Settling time is the time required from a code
transition until the DAC output reaches within ± % LSB of
the final output value. Full·scale settling time requires a zero
to full-scale or full-scale to zero output change.

3.0 TTL COMPATIBLE LOGIC INPUTS
To guarantee TTL voltage compatibility of the logic inputs, a
novel bipolar (NPN) regulator circuit is used. This makes the
input logic thresholds equal to the forward drop of two diodes (and also matches the temperature variation) as occurs naturally in TTL. The basic circuit is shown in Figure 1.
A curve of digital input threshold as a function of power
supply voltage is shown in the Typical Performance Characteristics section.

Full-Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC1006 series, full-scale is VREF-1 LSB.
For VREF= -10V and unipolar operation, VFULL-SCALE = 10.0000V - 9.8mV = 9.9902V. Full-scale error is adjustable to zero.

4.0 APPLICATION HINTS

Monotonlcity: If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. A 10-bit
DAC with 10-bit monotonicity will produce an increasing analog output when all 10 digital inputs are exercised. A 10-bit
DAC with 9-bit monotonicity will be monotonic when only
the most significant 9 bits are exercised. Similarly, a-bit
monotonicity is guaranteed when only the most significant a
bits are exercised.

The DC stability of the VREF source is the most important
factor to maintain accuracy of the DAC over time and temperature changes. A good single point ground for the analog
signals is next in importance.
These MICRO-DAC converters are CMOS products and
reasonable care should be exercised in handling them prior
to final mount.ing on a PC board. The digital inputs are protected, but permanent damage may occur if the part is subjected to high electrostatic fields. Store unused parts in conductive foam or anti-static rails.

2.0 DOUBLE BUFFERING
These DACs are double-buffered, microprocessor compatible versions of the DAC1020 10-bit multiplying DAC. The
addition of the buffers for the digital input data not only allows for storage of this data, but also provides a way to
assemble the 10-bit input data word from two write cycles
when using an 8-bit data bus. Thus, the next data update for
the DAC output can be made with the complete new set of
10-bit data. Further, the double buffering allows many DACs
in a system to store current data and also the next data. The
updating of the new data for each DAC is also not time
critical. When all DACs are updated, a common strobe signal can then be used to cause all DACs to switch to their
new analog output levels.

4.1 Power Supply Sequencing 8< Decoupllng
Some IC amplifiers draw excessive current from the Analog
inputs to V-when the supplies are first turned on. To prevent damage to the DAC - an external Schottky diode connected from loun or IOUT2 to ground may be required to
prevent destructive currents in IOUTl or IOUT2. If an LM~ 41
or LF356 is used - these diodes are not required.
The standard power supply decoupling capacitors which are
used for the op amp are adequate for the DAC.

+VCC
13 ++VTHII)
/'
VOIAS
ITO OTHER INPUTS)

~

CMOS LOGIC

o

S··VTHRESHOLO=21J1
TUH/5688-9

FIGURE 1. BasiC Logic Threshold Loop

3-69

4.2 Op Amp Bias Current & Input Leads
The op amp bias current (IB) CAN CAUSE DC ERRORS. BIFETTM op amps have very low bias current, and therefore
the error introduced is negligible. BI-FET op amps are
strongly recommended for these DACs.

able ladder current to the loun output pin. These MOS
switches operate in the current mode with a small voltage
drop across them and can therefore switch currents of either polarity. This is the basis for the 4-quadrant multiplying
feature of this DAC.

The distance from the IOUTl pin of the DAC to the inverting
input of the op amp should be kept as short as possible to
prevent inadvertent noise pickup.

5.1.1 Providing a Unipolar Output Voltage with the
DAC In the Current Switching Mode
'
A voltage output is provided by making use of an external
op amp as a current-to-voltage converter. The idea is to use
the internal feedback resistor, RFB, from the output of the
op amp to the inverting (-) input. Now, when current is
entered at this inverting input, the feedback action of the op
amp keeps that input at ground potential. This causes tlie
applied input current to be diverted to the feedback resistor.
The output voltage of the op amp is forced to a voltage
given by:

5.0 ANALOG APPLICATIONS
The analog section of these DACs uses an R-2R ladder
which can be operated both in the current switching mode
and in the voltage switching mode.
The major product changes (compared with the DAC1020)
have been made in the digital functioning of the DAC. The
analog functioning is reviewed here for completeness. For
additional analog applications, such as multipliers, allenuators, digitally controlled amplifiers and low frequency sine
wave 'oscillators, refer to the DAC1020 data sheet. Some
basic circuit ideas are presented in this section in addition to
complete applications circuits.
5.1 Operation

VOUT = -(Ioun XRFB)
Notice that the sign of the output voltage depends on the
direction of current flow through the feedback resistor.
In current switching mode applications, both cilrrent output
pins (IOUTl and IOUT2) should be operated at 0 VDC. This is
accomplished as shown in Figure 3. The capacitor, Cc, is
used to compensate for the output capacitance of the DAC
and the input capacitance of the op amp. The required feedback resistor, RFB, is available on the chip (one end is internally tied to IOUT1) and must be used since an external
resistor will not provide the needed matching and temperature tracking. This circuit can therefore be simplified as

II, Current Switching Mode

The analog circuitry, Figure 2, consists of a silicon-chromium (Si-Cr) thin film R-2R ladder which is deposited on the
surface oxide of the monolithic chip. As a result, there is no
parasitic diode connected to the VREF pin as would exist if
diffused resistors were used. The reference voltage input
(VREF) can therefore range from -10V to + 10V.
The digital input code to the DAC simply controls the position of the SPDT current switches, SWO to SW9. A logical 1
digital input causes the current switch to steer the avail-

DIGITAL INPUT CODE
(MSBI

017- _ • _.

OIB
1

019

o

011

DID (LSBI
1
TERMINATION

o
R

R

+"1""'.....-+'1""'.........1

:!: VREF 0-.....

2R

':"

RIB

R

......- t -....- t -....--+.....~+-4>-.....-oIOUTl
......- -....- -....----4.....- - 4 - - - - o 1 0 UT2
R '"15kll

FIGURE 2. Current Mode Switching

Vcc

(lNTERNALI

Rn

lOUT 1

(+15Vocl
Cc
+VREF

MICRO-DAC

':"

>--OVOUT = -(IOUTI x RIBI

':" ':"

FIGURE 3. Converting lOUT to VOUT

3-70

OP AMP Cc pF RJ ts ,...S T~/H/5688-10
LF356

22

00

LF351

24

00

3

4

LF357

10

2.4k

1.5

shown in Figure 4, where the sign of the reference voltage
has been changed to provide a positive output voltage. Note
that the output current, IOUT1' now flows through the RFB
pin.

where VREF can be positive or negative and 0 is the signed
decimal equivalent of the 2's complement processor data.
(-512S:0S: + 511 or 1000000000S:0S:0111111111). If the
applied digital input is interpreted as the decimal equivalent
of a true binary word, VOUT can be found by:

5.1.2 Providing a Bipolar Output Voltage with the
DAC In the Current Switching Mode
The addition of a second op amp to the circuit of Figure 4
can be used to generate a bipolar output voltage from a
fixed reference voltage Figure 5. This, in effect, gives sign
significance to the MSB of the digital input word to allow two
quadrant multiplication of the reference voltage. The polarity
of the reference can also be reversed to realize the full fourquadrant multiplication.

0-512)
VO=VREF ( ~

0:s:0:S:1023

With this configuration, only the offset voltage of amplifier 1
need be nulled to preserve linearity of the OAC. The offset
voltage error of the second op amp has no effect on linearity. It presents a constant output voltage error and should be
nulled only if absolute accuracy is needed. Another advantage of this configuration is that the values of the external
resistors required do not have to match the value of the
internal OAC resistors; they need only to match and temperature track each other.

The applied digital word is offset binary which includes a
code to output zero volts without the need of a large valued
resistor common to existing bipolar multiplying OAC circuits.
Offset binary code can be derived from 2's complement
data (most common for signed processor arithmetic) by inverting the state of the MSB in either software or hardware.
After doing this the output then responds in accordance to
the following expression:

A thin film 4 resistor network available from Beckman Instruments, Inc. (part no. 694-3-R10K-0) is ideally suited for this
application. Two of the four available 10 kG resistor can be
paralleled to form R in Figure 5 and the other two can be
used separately as the resistors labeled 2R.
Operation is summarized in the table below:

o

VO=VREFX512

2'sComp.
(Decimal)
+511
+256

o
-1
- 256
-512

with: 1 LSB =

2'sComp.
(Binary)

Applied
Digital Input

0111111111
0100000000
0000000000
1111111111
1100000000
1000000000

1111111111
1100000000
1000000000
0111111111
0100000000
0000000000

I~~~I

Applied
True Binary
(Decimal)
1023
768
512
511
256

o

VOUT
VREF-1 LSB
VREF/2

-IVREFI + 1 LSB
-IVREFI/2

-1 LSB
-VREF/2
-VREF

+1 LSB
+IVREFI/2
+IVREFI

o

o

Vee
IDUTl

( +15VoC}

-VREF

•

MICRO-OAC

o voe " VOUT "

+ VREF

(lift)

FIGURE 4. Providing a Unipolar Output Voltage

±VREF

TLlH/5688-11

FIGURE 5. Providing a Bipolar Output Voltage with the DAC In the Current Switching Mode

3-71

IX)

8.....

~

......
,....
o

o
.....

~

~
o
o
.....

o

~

5.2 Analog Operation In the Voltage Switching Mode

Notice that this is unipolar operation since all voltages' are
positive. A bipolar output voltage can be obtained by using a
single op amp as shown in Figure 10. For a digital input
code of all zeros, the output voltage from the VREF pin is
zero volts. The external op amp now has a single input of
+ V and is operating with a gain of -1 to this input. The
output of the op amp therefore will be at - V for a digital
input of all zeros. As the digital code increases, the output
voltage at the VREF pin increases.
'

Some useful application'circuits result if the R-2R ladder is
operated in the voltage switching mode. There are two very
important things to remember when using the DAC in the
voltage mode. The reference voltage (+ V) must always be
positive since there are parasitic diodes to ground on the
IOUTl pin which would turn on if the reference voltage went
negative. To maintain a degradation of linearity less than
±O.005%, keep +V s; 3 VDe and Vee at least 10V more
positive than + V. Figures 6 and 7 show these errors for the
voltage switching mode. This operation appears unusual,
since a reference voltage (+ V) is applied to the IOUTl pin
and the voltage output is the VREF pin. This basic idea is
shown In Figure 8.

Notice that the gain of the op amp to voltages which are
applied to the (+) input is + 2 and the gain to voltages
which are applied to the input resistor, R, is -1. The output
voltage of the op amp depends on both of these inputs and
is given by:

This VOUT range can be scaled by use of a non-inverting
gain stage as shown in Figure 9.

VOUT=(+V) (-1)+VREF(+2)

+.1

~

+.1
t;. LINEARITY ERROR

+.05

II:

lil
:Ii

J.......r

.
;!;

t;. GAIN ERROR

w

z

-.05

, I'

..

.........

;!;

t;.GAIN ERROR

w

~ .,..05
U

1

C=j5Y

-.1

o

,

, t;. LINEARITY ERROR
~ +.05

-

'"'"'"
:Ii

c
~

I

1/

1-j'=jY

234567
REFERENCE VOLTAGE. +V (VDcl

-.1 0

2

4

6

a

10 12 14

16

SUPPLY VOLTAGE, VCC (Voci

FIGURE 6

FIGURE 7
DIGITAL INPUT CODE
(MSal

017 __ • _ _

Dla

Dig

o

011
DID (LSal

o

1

0

1

+'I."""'_-!A,"""'_-I----- _"""'' ' ' '_-+--'WIr-I-=-

(VREFI
YoUT O-......

R

2R

2R

o " VOUT " 2.5 Voc

a-m)

2R

2R

2R

2R

R ",'5kll

SWg

Vcc

"VREF"

( +15Vocl

MICRO-oAC

VOUT

R2
OVoc" VoUT" +2.5VOC

(1+ Rl)(lm)
TL/H/56BB-12

FIGURE 9. Amplifying the Voltage Mode Output (Single Supply Operation)

3-72

~.....

Vcc

o
o
en
.....

511)
-2.5 VOC " VOUT" 2.5VOC ( 512
"VREF"

~

VOUT

-0.

oQ

.....
.....

+V
( +2.500VOC)

~

(LM336)

.....

FIGURE 10. Providing a Bipolar Output Voltage with a Single Op Amp

o
o

OCI

+V
(+2.500 VOC)

>--OVOUT

"VREF"

o" VOAC "

+2.5 VOC

(lgm

TUH/5666-13

FIGURE 11. Increasing the Output Voltage Swing
The output voltage swing can be expanded by adding 2
resistors to Figure 10 as shown in Figure 11. These added
resistors are used to attenuate the + V voltage. The overall
gain, Av( -), from the + V terminal to the output of the op
amp determines the most negative output voltage, - 4( + V)
(when the VREF voltage at the + input of the op amp is
zero) with the component values shown. The complete dynamic range of VOUT is provided by the gain from the (+)
input of the op amp. As the voltage at the VREF pin ranges
from OV to +V(1023/1024) the output of the op amp will
range from -10 VDC to + 10V (1023/1024) when using a
+ V voltage of + 2.500 VDC. The 2.5 VDC reference voltage
can be easily developed by using the LM336 zener which
can be biased through the RFB internal resistor, connected
toVcc·

If the VOS is to be adjusted there are a few points to consider. Note that no "dc balancing" resistance should be used
in the grounded positive input lead of the op amp. This resistance and the input current of the op amp can also create
errors. The low input biasing current of the BI-FET op amps
makes them ideal for use in DAC current to voltage applications. The VOS of the op amp should be adjusted with a
digital input of all zeros to force IOUT= 0 mA. A 1 kO resistor
can be temporarily connected from the inverting input to
ground to provide a dc gain of approximately 15 to the Vos
of the op amp and make the zeroing easier to sense.
5.4 Full·Scale Adjust
The full-scale adjust procedure depends on the application
circuit and whether the DAC is operated in the current
switching mode or in the voltage switching mode. Tech·
niques are given below for all of the possible application
circuits.

5.3 Op Amp Vos Adjust (Zero Adjust) for Current
Switching Mode
Proper operation of the ladder requires that all of the 2R
legs always go to exactly 0 VDC (ground). Therefore offset
voltage, Vos, of the external op amp cannot be tolerated as
every millivolt of Vos will introduce 0.01 % of added linearity
error. At first this seems unusually sensitive, until it becomes
clear the 1 mV is 0.01 % of the 10V reference! High resolution converters of high accuracy require attention to every
detail in an application to achieve the available performance
which is inherent in the part. To prevent this source of error,
the Vos of the op amp has to be initially zeroed. This is the
"zero adjust" of the DAC calibration sequence and should
be done first.

5.4.1 Current Switching with Unipolar Output Voltage
After doing a "zero adjust," set all of the digital input levels
HIGH and adjust. the magnitude of VREF for
1023
.
VOUT= -(Ideal VREF) 1024
This completes the DAC calibration.

3·73

5.4.2 Current Switching with Bipolar Output Voltage

5.4.3 Voltage Switching with a Unipolar Output Voltage

The circuit of Figure 12 shows the 3 adjustments needed.
The first step is to set all of the digital inputs LOW (to force
IOUT1 to 0) and then tri'm "zero adj." for zero volts at the
inverting input (pin 2) of OA 1. Next. with a code of all zeros
still applied. adjust "-FS adj .... the reference voltage, for
VOUT= ± I(ideal VREF)I. The sign of the output voltage will
be opposite that of the applied reference.

Refer to the circuit of Figure 13 and set all digital inputs
LOW. Trim the "zero adj." for VOUT=O Voc±1 mY. Then
set all digital inputs HIGH and trim the "FS Adj." for:

Finally. set all of the digital inputs HIGH and adjust" + FS
adj." for VOUT=VREF (511/512). The sign of the output at
this time will be the same as that of the reference voltage.
The addition of the 2000 resistor in series with the VREF pin
of the DAC is to force the circuit gain error from the DAC to
be negative. This insures that adding resistance to RIb. with
the 5000 pot. will always compensate the gain error of the
DAC.

Refer to Figure 14 and set all digital inputs LOW. Trim the
"- FS Adj." for VaUT= - 2.5 Veo. Then set all digital inputs
HIGH and trim the "+ FS Adj." for VOUT= +2.5 (511/512)
Vee. Test the zero by setting the MS digital input HIGH and
all the rest LOW. Adjust Vas of amp #3. if necessary. and
recheck the full·scale values.

R1)1023
VaUT=(+V) ( 1 + R2 1024
5.4.4 Voltage Switching with a Bipolar Output Voltage

I+FS ADJ)
500

I-FS ADJ)
±VREF
200

¥OUT

511 )
- VREF<:VOUT<: + VREF ( 512

FIGURE 12. Full Scale Adjust - Current Switching with Bipolar Output Voltage

VCC

I +15VDC)
"VREF"

MICRO·OAC

.....-o VOUT

.>?~

DVDC < VDUT < 2.5VOC

(1 +~)Om)

FS ADJ.
TUH/5688-14

FIGURE 13. Full Scale Adjust - Voltage Switching with a Unipolar Output Voltage

3·74

+V
+FS

MICRo·OAC

-FS ADJ.

/~OOg
+r--:

......
r-

(2.56VOC)

A~J.

~

R" MATCH TO 0.01"

~
S -J . . rVI
~-

lood

p-

R"

R"

15K

15K

1.78K

~b-

~

+ 3

I-ovauT

-2.5V < VaUT < u(IH) V
TLlH/5688-15

FIGURE 14. Voltage Switching with a Bipolar Output Voltage

6.0 DIGITAL CONTROL DESCRIPTION
The DAC1006 series of products can be used in a wide
variety of operating modes. Most of the options are shown
in Table 1. Also shown in this table are the section numbers
of this data sheet where each of the operating modes is
discussed. For example, if your main interest in interfacing
to a ,...p with an 8-bit data bus you will be directed to Section
6.1.0.
The first consideration is "will the DAC be interfaced to a ,...p
with an 8-bit or a 16-bit data bus or used in the stand-alone
mode?" For the 8-bit data bus, a second selection is made
on how the 2nd digital data buffer (the DAC Latch) is updated by a transfer from the 1st digital data buffer (the Input
Latch). Three options are provided: 1) an automatic transfer
when the 2nd data byte is written to the DAC, 2) a transfer
which is under the control of the J.LP and can include more
than one DAC in a simultaneous transfer, or 3) a transfer
which is under the control of external logiC. Further, the data
format can be either left justified or right justified.
When interfacing to a ,...p with a 16-bit data bus only two
selections are available: 1) operating the DAC with a single
digital data buffer (the transfer of one DAC does not have to
be synchronized with any other DACs in the system), or

2) operating with a double digital data buffer for simultaneous transfer, or updating, of more than one DAC.
For operating without a ,...p in the stand alone mode, three
options are provided: 1) using only a single digital data buffer, 2) using both digital data buffers....,.. "double buffered," or
3) allowing the input digital data to "flow through" to provide
the analog output without the use of any data latches.
To reduce the required reading, only the applicable sections
of 6.1 through 6.4 need be considered.
6.1 Interfacing to an 8-Blt Data Bua
Transferring 10 bits of data over an 8-bit bus requires two
write cycles and provides four possible combinations which
depend upon two basic data format and protocol decisions;
1. Is the data to be left justified (considered as fractional
binary data with the binary point to the left) or right justified (considered as binary weighted data with the binary
point to the right)?
2. Which byte will be transferred first, the most significant
byte (MS byte) or the least significant byte (LS byte)?

Table 1
Operating Mode

,...p Control Transfer

Automatic Transfer

Eldema' Tranafer

Section

Figure No.

Section

Figure No.

SectIon

Figure No.

6.2.1

16

6.2.2

16

6.2.3

16

Data Bus
8-Bit Data Bus (6.1.0)
Left Justified (6.1 .1 )
16-Bit Data Bus (6.3.0)

Single Buffered
6.3.1

Stand Alone (6.4.0)

Double Buffered
6.3.2

17

Single Buffered
6.4.1

17

Double Buffered

17

6.4.2

3-75

17

Flow Through
Not Applicable
Flow Through
NA

=
g
.,...

r-~----~----------------------------~----------------------------~

g
......

These data possibilities are shown in Figure 15. Note that
the justification of data depends on how the 10-bit data
word is located within the 16-bit data source (CPU) register.
In either case, there is a surplus of 6 bits and these are
shown as "don't care" terms (" x ") in this figure.
.

~

All of these DACs load 10 bits on the 1st write cycle. A
particular set of 2 bits is then overwritten on the 2nd write
cycle, depending on the justification of the data. For all left
justified data options, the 1st write cycle rilUst contain the
MS or Hi Byte data group.
.

"oo

.....
cD
o
o
.,...

o

~

parts require the MS or Hi Byte data group to be transferred
on the 1st write cycle.
6.2 Controlling Data Transfer for an 8-Bit Data Bus
Three operating modes are possible for controlling the
transfer of data from the Input Latch to the DAC Register,
where it will update the analog output voltage. The simplest
is the automatic transfer mode, which causes the data
transfer to occur at the time of the 2nd write cycle. This is
recommended when the exact timing of the changes of the
DAC analog output are not critical. This typically happens
where each DAC is operating individually in a system and
the analog updating of one DAC is not required to be synchronized to any other DAC. For synchronized DAC updating, two options are provided: p.P control via a common
XFER strobe or external update timing control via an external strobe. The details of these options are now shown.

6.1.1 For Left Justified Data
For applications which. require left justified data, DAC10061008 can be used. A simplified logic diagram which shows
the external connections to the data bus and the internal
functions of both of the datil. buffer registers (Input Latch
and DAC Register) is shown in Figure 16. These

DAC1006/100711008 (20-Pln Parts for Left Justified Data)
1----8·8IT 8 Y T E , - - - - f - - - 8·BlT8VTE----I

'''.j' ",

'.1·
','

,I

HI BYTE

1

LOmE

'I~SB&++++~.&+BI·I·I·I·I x Ix I

.

'I

';,

I

I

~

HIBm

x I x I x I x

I

I·

1

LOBm

x IMSB&++US{IFIED:DATfHuaj'
TLlH/56BB-16

FIGURE 15. Fitting a 10-Blt I;)ata Word Into 16 Available Bit Locations

I

,

OBi

,

i.
8·BIT

DATA BUS

I
g
8 '
T
6
5
1
18
1

,

DS.

Dig (MSB)

D
D
0
8·BIT
0 INPUT
LATCH
TO
CURRENT
SWITCHES

DI. (LSBI

16'
15

'.'1

Brt.lIBYii1

CI
Wli

WHEN:

ClIffiIEWIl=l,D

fmIlT~~o~ ~~~TS.
AT D IS LATCHED.

(ml mil
.

TL/H/56B8-17

FIGURE 16. Input Connections and Controls for DAC1006/1007/1008 Left Justified Data

3-76

6.2.1 Automatic Transfer
This makes use of a double byte (double precision) write.
The first byte (8 bits) is strobed into the input latch and the
second byte causes a simultaneous strobe of the two remaining bits into the input latch and also the transfer of the
complete 10·bit word from the input latch to the. DAC regis~er.. This is shown in the following timing diagram; the paint
In time where the analog output is updated is also indicated
on this diagram.

6.2.3 Transfer Using an External Strobe
This is similar to the previous operation except the XFER
signal is not provided by the ",p, The timing diagram for this
is:
DAC1006/1007/1008 (20-Pln Parts)

DAC1006/1007/1008 (20-Pln Parts)

-\DA~BII'~

Viii

" - - " LATCH

~yt.

\/

mii~-J

I'LAL

BII' 2

2~FER
I LATCH DAC

-.'-rl_

LOAD BII.l

'Viii I

r--

LOAD BII·2
1

~~~3~
UPDATED

LATCH

\lJ-~:;

Byt.lI
Byii1
BVIJ 1I1J11 2

l~

REGISTER

:-----

~?'-----TL/H/5688-20

6.3 Interfacing to a 16-Blt Data Bus

TlIH/56B8-1 B

'SIGNIFIES CONTROL INPUTS WHICH ARE DRIVEN IN PARALLEL

The interface to a lS·bit data bus is easily handled by can·
necting to lOaf the available bus lines. This allows a wiring
selected right justified or left justified data format. This is
shown in the connection diagram of Figure 17, where the
use of DBS to DB15 gives left justified data operation. Note
that any part number can be used and the Bytel/Byte2 can·
trol should be wired Hi.

6.2.2 Transfer Using ",p Write Stroke
The input latch is loaded with the first two write strobes. The
XFER signal is provided by external logic. as shown below,
to cause the transfer to be accomplished on a third write
strobe. This is shown in the following diagram:
DAC100.6/1007/1008 (20-Pln Pari!!)

9

\'--_-J/\. . ._-JtLG
LOAD BII' 1

LOAD BjII 2

OUTPUT
UPDATED

LATCH GAC
REGISTER

iiiii-vr-B~tr
LATCH BII' 2

mii
BjIIlIliiii1

l2

2\

2\jJ
r----

•

I

l~-----

WHERE THE XFER CONTROL CAN BE GEHERAlED BY USING ASECOND CHIP SELECT AS:

~g

00

olm

AND THE Bm CONTROL CAN BE DERIVED FROM THE ADDRESS BUB SIG1IALS.

TL/H/5688-19

3·77

LEFT ,
, DAC1DDB/l007l1D01 flO-PIN PARTS)
JUSTIFIEO,
OB15 9' 019 (MSB)
BOO
7

II.BIT
OATA

~

10·BIT

0

'";:~I
,
5 ===:10
0

BUS,)~=~19::====~0
8
o
17
16
1
OBI,DI$(LSB)

0

~:
INPUT
LATCH

0
0
0

0
0'''"===:1
01-

0
0
0
0

TO
CURRENT
swm:HES

0
0
0
0

I'

eJ2~=+~J
W1it
CD:J:DL

WHEN:

,I

Dmr EIiDI:r=1,Q

,

(ml'ffiii4~-=OI...J-----------'

OUTPUTS FOLLOW 0 INPUTS.
DTmrEliDl:r 0. DATA
AT 0 IS LATCHED.

=

3'

+VCC~ (EQUIVALENT LOGIC SHOWN
By1Il/i;ii2 : FOR THIS PIN HIGH)
TUH/51188-21

FIGURE 17. Input Connections and Logic for DAC1006/1007/100B with 16-Blt Data Bus

ThreE! operating modes arEi pOssible: flow'through, sil'1gle
buffered, or double buffered. The timing diagram!! for these
are shown below:
'

6.4 Stand Alone Operation

For applications for a DAC which lire not under poP control
(stand alone) there are two basic operating modes, single
buffered and double buffered. The timing diagrams for these
are shown below:
'

6.3.1 Single Buffered
DAC100611007/100B (200Pln Parts)

6.4.1 Single Buffered
DAC1006/1007/1008 (2o-Pln Parts)

\L____..JI,

XFEA AND LATCH
"' DAC REGISTER

-

~~~ _U,
UPDATElI

r-

IRA TO DAC IlUllTEA
Iy1Il/ijiil

"INPUT DATA IS
LATCHED
LOAD INPUT LATCH

l~nPIIT
LATCH

\

/

'

LATCIIU _II OAC l E _

ANALDl/'

g:

c=r=~r·EUlIVUI

6.4.2 Double Buffered
DAC100611007/100B (2Q.Pln Parts)·

6.3.2 Double Buffered
DAC100611007/100B (20-Pln Parts)

LOAD IIIPUT LATCH,-_ _ _ _ __

Wi \

ffiii
By1IlIijiil = 1

I-LATCH 111M LATCH

==

IIIPUT DATA IS LATCHED

Wi--~~~----------

/

\i~

UPDATED--

LOAD 11M LATCH

TUH/51188-23

ANALDD

8~~-"'--..,.......I
XFER
TUH/568B-22

'F... a connection diag,am of this operating mode use Figure 1610' the Logic and Ftg1Jf8 1710' the Data (nput connections.

3-78

7.0 MICROPROCESSOR INTERFACE
The logic functions of the DAC1 DOS family have been oriented towards an ease of interface with all popular ""Ps. The
following sections discuss in detail a few useful interface
schemes.

The circuit will perform an automatic transfer of the 10 bits
of output data from the CPU to the DAC register as outlined
in Section S.2.1, "Controlling Data Transfer for an 8-Bit Data
Bus."
Since a double byte write is necessary to control the DAC
with the INS8080A, a possible instruction to achieve this is a
PUSH of a register pair onto a "stack" in memory. The 1Sbit register pair word will contain the 10 bits of the eventual
DAC input data in the proper sequence to conform to both

7.1 DAC1001l1l2 to INS8080A, Interface'
Figure 18 illustrates the simplicity of interfacing the
DAC100S to an INS8080A based microprocessor system.

Your

TLlH/5688-24
NOTE: DOUBLE BYTE STORES CAN BE USED.

e.g. THE INSTRUCTION SHLD FOOl

STO~ES

THE L

REG INTO Bl AND THE H REG INTO B2 AND
TRANSFERS THE RESULT TO THE DAC REGISTER.
THE OPERAND OF THE SHLD INSTRUCTION MUST
BE AN ODD ADDRESS FOR PROPER TRANSFER.

FIGURE 18. Interfacing the DAC1000 to the INS8080A CPU Group

3-79

•

PIA, and the LOW byte is loaded into ORB: The la-bit data
transfer to the DAC and the corresponding analog output
change occur simultaneously upon CB2 going L9W under
program control. The la-bit data word in the DAC register
will be latched (and hence VOUT will be fixed) when CB2 is
brought back HIGH.
,
,
If both output ports of the PIA are not available, it is possible
to 'interface the DACl 006 through
Single port without
much effort. However; additional logic at the CB2(or CA2)
lines or access to some of the 6800 system control lines will
be required.

the requirements of the DAC (with regard to left justified
data) and the implementation of the PUSH instruction which
will output the high!lr order byte of the, register pair (i.e.,
register B of ,the BC pair) ~irst. The DAC will actually appear
as a two-byte "stack" in memory to the CPU. The auto-decrementing of the stack pointer during a PUSH allows using
address bit a of the stack pOinter as the Bytel /Byte2 and
~ strobes if bit 0 of the stack pOinter address -1,
(SP-l), is a "1" as presented to the' DAC. Additional ad~
dreSs decOding by the DM8131 will generate a uniqueDAC
chip select (CS) and synchronize this CS to the tWo memory
write strobes of the PUSH instruction.
To reset the stack pointer so new data may be output to the
same DAC, a POP instruction followed by instructions to
insure that proper data is in the DAC data register pair before it is "PUSHED" to the DAC should be executed, as the
POP instruction will arbitrarily alter the contents of a register
pair.
Another double byte write instruction is Store Hand L Direct
(SHLD), where the HL register pair would temporarily contain the DAC data and the two sequential addresses for the
DAC are specified by the instruction op code. The auto incrementing of the DAC address by the SHLD instruction
permits the same siinple scheme of' using address bit 0' to
generate the byte number and transfer strobes.

a

7.3 NOise Considerations
A typical digital/microprocessor bus environment is a tremendous potential source of high frequency noise which
can be coupled to sensitive analog circuitry. The fast edges
of the data and address bus signals generate frequency
components of 10's of megahertz and can cause noise
spikes to appear at the' DAC output These noise spikes
occur when the data bus changes state or when data is
transferred between the latches of the device.
In ,'lOW frequency or DC applications, low pass filtering can
, reduce these noise spikes. This is accomplished byovercompensating the DAC output amplifier by increasing the
value of the feedback capacitor (Cc in Ftgure 3).
In applications requiring a fast transient response from the
DAC and op amp, filtering may not be feasible. Adding a
latch, DM74LS374, as shown in Figure 20 isolates the device from the data bus, thus eliminating noise spikes that
occur every time the data bus changes state. Another method for eliminating noise spikes is to add a sample and hold
after the DAC op amp. This also has the advantage of eliminating noise, spikes when changing d,igital codes.

7.2 DAC1006 to MC6820/1 PIA Interface
In Figure 19 the DAC1006 is interfaced to an M6800 system ,
through an MC6820/1 Peripheral Interface Adapter (PIA). In
this case the CS pin of the DAC is grounded since the PIA is
already mapped In the 6800 system memory space and no
decoding Is necessary. Furthermore, by using both Ports A
and B of the PIA the la-bit data transfer, assumed left'
justified again in two 8-bit bytes, is greatly simplified. The
HIGH byte is loaded into Output Register A (ORA) of the

PilI
PAg 2
PS7
PIli

el2

PS&

PS5
PSc
PSa
PS2
PSI
PIa 10
VOUT

Tl/H/5688-25

FIGURE 19. DAC1000 to MC6820/1 PIA Interface

3-80

AlIALOO

OUTfUr

+15V

'--+--~
ADDRESS>--::tj"}oJ..t:~J
DECODER

L.r CI FROM

NOTE: DATA HOLD TIME REDUCED TO THAT OF DM74LS374 ('" 10 ns)

SYSTEM WI!

ADDRE::~~~~>__-L'/C>-----"'"

(LOWFOR8ml

HIGH FOR aYTE 21

FIGURE 20. Isolating Data Bus from DAC Circuitry to Eliminate Digital Noise Coupling

MSB

LSB

15V
15k

MICRO·OAC
OAC1006 SERIES
VREFIN

YoUT

V-

V-

TUH/5688-28

FIGURE 21. Digitally Controlled Ampllfler/Attenuator
7.4 Digitally Controlled Ampllfler/Attenuator
An unusual application of the DAC, Figure 21, applies the
input voltage via the on-chip feedback resistor. The lower
op amp automatically adjusts the VREF IN voltage such that
IOUT1 is equal to the input current (VIN/Rfe). The magnitude
of this VREF IN voltage depends on the digital word which is
in the DAC register. IOUT2 then depends upon both the
magnitude of VIN and the digital word. The second op amp
converts IOUT2 to a voltage, VOUT, which is given by:

Note that N = 0 (or a digital code of all zeros) is not allowed
or this will cause the output amplifier to saturate at either
±VMAX' depending on the sign of VIN.
To provide a digitally controlled divider, the output op amp
can be eliminated. Ground the IOUT2 pin of the DAC and
VOUT is now taken from the lower op amp (which also drives
the VREF input of the DAC). The expression for VOUT is now
given by

1023-N)
VOUT=VIN ( - - N - ,where OIVv-_"IVI....---1'-'11vv-_"IVI....-,.--'-I,
2R

IR

In

~

2R

In

2n

In

In

2R

zn

--'1.'.

l

2n

~,

~~t~~1~~1~~1~~1f~1f~1~~1f~1~;1: f~1f~1

:I

1

I
I
I

I
I
I

I

I

I

I

I

~

l,

b

A'

AI

IIISII

I

I

I
I
I

I

I
I
I

b

b

l,

l,

A1

AI

I

.3

.b

A5

A&

I

I
I
I

I

b

b
AID

A.

I
I
ILSa)

GN.

'OUlZ

'DUT'

,:
I

:

I

I l,

I

l,

LA: _ .:: __ .J

~fEED8ACK

TL/H/56B9-1

Ordering Information

10-BIT DI A CONVERTERS

Temperature Range
NonLinearity

-40"Cto 85'C

O'Cto 70"C

0.05%

OAC1020LCN

A07520LN,A07530LN

0.10%

OAC1021LCN

A07520KN,A07530KN

0.20%

OAC1022LCN

OAC1020LCV

OAC1020LlV

A07520JN,A07530JN

Package Outline

V20A

N16A
12-BIT D/A CONVERTERS

Temperature Range
NonLinearity

I

I

0.05%
0.20%

-40'Cto

O'Cto 70"C
OAC1220LCN
OAC1222LCN

Package Ou1line

I

I

A07521LN,AD7531LN

OAC1220LCJ

A07521JN,A07531JN

OAC1222LCJ

N18A

I

I

+ 85'C

AD7521 LD,AD7531 LO
AD7521JD,A07531JO
J18A

Nota. Devices may be ordered by eHher part number.

3-83

~

~
....
N
N

Q

......

g
o....
N
N
N

N
N
N

.....
g

~
C

~
N

.....
N

-g
N

«:)

-g
.....
N

Absolute Maximum Ratings (Note 5)

Operating Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
V+ toGnd
17V
VREFtoGnd
Digital Input Voltage Range
DC Voltage at Pin 1 or Pin 2 (Note 3)
Storage Temperature Range

Temperature (TA)
DAC1020LlV, DAC1220LCJ,
DAC1222LCJ
DAC1020LCN, DAC1020LCV,
DAC1021LCN
DAC1022LCN, DAC1220LCN
DAC1222LCN

±25V
V+ toGnd
-100mVtoV+
- 65·C to + 150·C

Lead Temperature (Soldering, 10 sec.)
Dual·ln·Line Package (plastiC)
Dual-In-Line Package (ceramic) .

Min

Max

Units

-40

+S5

·C

0

+70
+70
+70

·C
·C
·C

0
0

260·C
3000C

soov

ESD Susceptibility (Note 4)

«:)

~

g

Electrical Characteristics (V+
Parameter

= 15V, VREF = 10.000V, TA = 25·C unless otherwise specified)

Conditions

«:)

Resolution
Linearity Error

10-Bit Parts
9-Bit Parts
S·Bit Parts

Full·Scale Error

-10V,;;VREF';; + 10V,
(Notes 1 and 2)

Full·Scale Error Tempco

TMIN V+) the absolute value of current at that pin should be lim~ed

Note 4: The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 30 mAo
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJm.. (maximum junction temperature), 0JA
(package junction to ambient thennal reSistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is
POmax = (TJmax - TA)/0JA or the number given in the Absolute Maximum Ratings, whichever is lower. The table below details TJmax and 0JA for the various
packages and versions of the DACI054.

I

Part Number

I

TJmax('C)

I

0JA('C/W)

I

I

DACI054CIN
DACI054CIWM

I

125
125

I

42
57

I

Note 6: Human body model, 100 pF discharged through a 1.5 kO resistor.
Note 7: See AN450 "Surface Mounting Methods and Their Effect on Production
Databook for other methods of soldering surface mount devices.
Note 8: Typicals are at TJ
Note 9:

Um~s

Reliabil~"

of the section titled "Surface Mount" found in

a~y

current Unear

= 25'C and represent most likely parametric norm.

are guaranteed to National's AOQL (Average OutgOing

Qual~

Level).

Note 10: A monotonicily of 10 bHs for the DACI054 means that the output voltage changes in the same direction (or remains constant) for each increase in the
input code.

Note 11: Integrallinearily error is the maximum deviation of the output from the line drawn between zero and full·scale (excluding the effects of zero error and full·
scale error).
Note 12: Full·scale error is measured as the deviation from the ideal 2.800V full·scale output when VREF
Note 13: Full-scale error tempco and zero error tempco are defined by the following equation:
E
rror tempco

=

[Error (TMAxl - Error (TMIN) ]
VSPAN

[

= 2.650V and VBIAS = I :400V.

10·
]
TMAX TMIN

where Error (TMAxl is the zero error or full-scale error at TMAX (in volts), and Error (TMIN) is the zero error or full-scele error at TMIN (in volts); VSPAN is the output
voltage span of the DACI054, which depends on VBIAS and VREF.
Note 14: Zero error is measured as the deviation from the ideal 0.302V output when VREF = 2.650V, VBIAS = 1.400V, and the digilallnput word Is all zeros.
Note 15: Power Supply Sensit~ is the maximum chenge In the offset error or the full-scale error when the power supply differS' from its optimum 5V by up to
C.50V (10%). The load resistor RL = 2 kO.
Note 16: Positive or negative seHling time Is defined as the time taken for the output of the DAC to settle to its final full·scale or zero output to within ±0.5 LSB.
This time shall be referenced to the 50% pOint of the positive edge of ml, which initiates the update of the analog outputs.
Note 17: Digital crosstalk is the glitch measured on the output of one DAC while applying an all Os to all I s transition at the

i~put

of the other DACs.

Note 18: All DACs have full-scale outputs latched and 01 is clocked with no update of the DAC outputs. The glitch is then measured on the DAC outputs.
Note 19: Clock feedthrough is measured for each DAC wHh its output at full-scale. The serial cl~ck Is then applied to the DAe'at a frequencY of 10 MHz and the
glitch on each DAC full-scale output is measured.
Note 20: Channel·to-channel isolation is a measure of the effect of a change in one DAe's output on the output of another DAC. The VREF of the first DAC is varied
between 1.4V and 2.65V at a frequency of 15 kHz while the change in full·scale output of the second DAe is measured: The first DAC is loaded w~h all Os.
Note 21: Glitch energy Is the difference between the pOSitive and negative glitch areas at the output of the DAC when a I LSB digital input code change Is applied
to the input. The glitch energy will have Its largest value at one of the three major transitions. The peak value of the maximum glitch Is separatOly specified.
Note 22: Power Supply Rejection Ratio is measured by varying AVec

= DVcc between 4.50V and 5.50V with a frequency of 10 kHz and measuring the proportion

of this signal imposed on a full·scale output of the OAe under consideration.

Note 23: The bandgap reference tempco is defined by the largest value from the following equations:
Tempco(TMAX)

=

[VREF(TMAxl- VREF(TROOM)]
VREF (TROOM)

[

10·
] or Tempco (TMIN)
TMAX - TROOM

=

[VREF(TMIN) - VREF(TROOM)]
VREF (TROOM)

where TROOM = 25'C, VREF (TMAxl is the reference output at TMAX, and slmllariy for VREF (TMINl and VREF (TROOMl.
Note 24: A Military RETS specification is available upon request.

3-96

[TROO:~ TMIJ

Typical Converter Performance Characteristics
Zero Error vs
Temperature
5

'>

..........

'>
~

20

0

o .....

.5

r--....

-5

~

~ -10 - Vcc =5V

=
fyK =

'r

"-r-.,

g§

f"'.- I"-

~ -15

5

"'

Vee =sv

"'- -25

V81AS

50

75

(Oc)

IO

0

25

50

75

...

-44

./

3

..- ~ I-

I

I

I

Vee = 5.0V +10r:.,...-

,..

-44

g;
~

.5

I-

~

z

I-

0

25

50

75

"':;

~

~

75

100

15

14

-

1-

13

~

-50
-50

100

50

~
~
~

~ q:5.0V-l0%

-46

-50

25

Vee = S.OV
TA = 25°C

':?

~

TE~PERATURE

I
0

Supply Current vs
Clock Frequency

-48

-50 -25

I
-25

16

-42

,..

I
feLK = 1014Hz

TEMPERATURE (Oc)

-40

-42

- ~~. .1.
~.
5.0V-Vee = 4.5V

5

Full-Scale Error PSRR
vs Temperature

Vee = S.OV :I: 10%

-46

-- hZt::::F
vr -

r-- -

0
-50

100

......... - hI ee =I 5.5V

-

TEMPERATURE (oc)

-40

-48

i
i

=1.40V

-fYK='loWHZ
-50 -25

100

Zero Error PSRR
vs Temperature

~

'"
.5

15

-30
25

TE~PERATURE

~
~

r""-

~ -20 - VREF = 2.6SV

UHZ

0

..........

a::: -10

-20
-50 -25

-

-5

.5

VR£F = 2.6SV
1."'OV

-15 _ VB1AS

!

Supply Current
vs Temperature

Full-Scale Error
vs Temperature

12
-25

(Oc)

0

25

50

75

100

0

TEMPERATURE (Oc)

2

4

6

8

10

CLOCK FREQUENCY (kHz)

Integral Non-Linearity
Error vs Temperature
0.4

0.2

~

,

..........
+INL

V-:';'=5r '
VR£F = 2.65~_
VS1AS = 1.40V
fCI.K= leMHz

0.0

~

z

T

-INL

-0.2

-0.4
-50

-25

0

25

L
50

II

~

75

100

TEMPERATURE (Oc)

TL/H/11437-2

Typical Reference Performance Characteristics
Bandgap Voltage
vs Temperature

Line Regulation
vs Temperature

2.660

2.0

E

~~

!

2.650
",..

1.5

.5
l:>

..

1.0

>~

2.630

Vce = 5.0V

0
-50

2.810
-25

0

Vee

0.5

2.620

-50

_

'>

2.640

\j

~

- ....

~I"'"

25

TE~PERATURE

50

75

100

-25

0

= 5V :t

I'

= 4 mA
1

25

50

10%

I

75

100

TEMPERATURE (Oc)

(oc)

TLlH/11437-4

TL/H/II437-3

3-97

TRI-STATE Test Circuits and Waveforms
DVcc

cs

t - -....-~P-- ~~~~UT
10kn

DATA
OUTPUTS

DVCC~

~

50%

;:~
GND

.
TLlH/II437-6

Tl/H/11437-5

DVcc
DVcc

CS

10kn

t - -....-~.....-

~~~~UT
DATA
OUTPUTS

-1

,. f?

DVCC

50%

DVcc
GND

_

10%
Tl/H/11437-8

TLlH/II437-7

Timing Waveforms
Data Input Timing

Data Output Timing

elK

elK

00

TLlH/II437-10

01
TLlH/II437-9

Timing Diagrams
elK

CSI~

__________________________

~r
I

.

I

DI

~

I

~A_l~__AO~I~~s~~~_D_8~__D7~~D_6~_D_5~__D4~__D_3~_D_2~1'_D_l~I_"l=~~B~__~1

I

i r-1
I

.•o-----Instruction Bytel----i'I
""

VOUT

--------------------------------------------------------------------------~~
'1

I

Is.

i:

,I

Settled 101/2 l S B - - :
Tl/H/11437-11

FIGURE 1. Write to One DAC with Update of Output (AU

3·98

=

1), 10 MHz Maximum CLK Rate

Timing Diagrams (Continued)

---------~

CLK

~~~

______________________________

LJ

DI~

I

~r_

DATA BITS'

1,...>----lnstrUCtion Byt.,---......JI

Tl/H/11437-12

• OACs are written to MSB first.
OACl is written to first, then OACs 2, 3, and 4.

FIGURE 2, Write to All DACs with Update of Outputs (AU = 1).10 MHz Maximum ClK Rate

elK

~-'~

__________________________________________

DI~

~r-

A 1 A O _

I.'-----Instruction

Byte------I.I

DO --------TRI-STATE

-------i.~l~SB~_.J_ _.JL_L_.L_.l_J._J._.J~~~S~BJ~TRI-STATETl/H/11437-13

FIGURE 3. Read One DAC, DO lSB First, DO Changes on Failing Edge of ClK (AU = 1),5 MHz Maximum ClK Rate

_____ 5sLfLJ

ClK

~ ~~------------------------------~
Dlf@i

~

n

~-----I

~

~~=====~

....

I,...>------Instruction 8yte------I.1

DO

-------TRI-STATE----------I::D~A~TA~BI~TS~.:J~TRI-STATE.
TL/HI11437-14

'OACl is read first, then OACs 2, 3, and 4.

FIGURE 4. Read All DACs, DO lSB First, DO Changes on Falling Edge of ClK (AU = 1),5 MHz Maximum ClK Rate

3·99

•

~r-----------------------------------------------------------~

....~

g

Block Diagram

DGND

AGND

20

Your1
VBIASI
24
YBIAS2

Au

11

23

VOUT2

ClK

Cs
iiii'
DI

12

MICROWIRE™
AND
lOGIC

I.
17
V. UT3

DO
16

VBIAS3
15
VBIAS•
13

Your"

VREr1

VREF2

VREF3

V. EF4

VREF OUT

TUH/11437-15

Pin Description
VOUT1(2),
VOUT2(23),
VOUT3(17),
VOOT4(13)

The voltage output connections of the
four DACS. These provide output
voltages in the range 0.3V-2.8V.

AU(11)

When this pin is taken low, all DAC outputs
will be asynchronously updated. CS must
be held high during the update. AD must be
held high during Read back.

VREF<)UT(21)

The internal voltage reference output.
The output of the reference is 2.65V
±2%.

The voltage reference inputs for the four
DACs. The allowed range is OV-2.75V.

VBIAS1(3),
VSIAS2(24);
VSIAS3(16),
VSIAS4(15)

The non-inverting inputs of the 4 output
amplifiers. These pins set the virtual
ground voltage for the respective DACs.
The allowed range is 0.3V-1.4V.

VREF1(1),
VREF2(22),
VREF3(1B),
VREF4(14)
CS(9)

The Chip Select control input. This input is
active low.
The external clock input pin.

AGND(20),
DGND(5)

The analog and digital ground pins.

DVcc(4,6),
AVcc(19)

The digital and analog power supply
pins. The power supply range of the
DAC1054 is 4.5V-5.5V. To guarantee
accuracy, it is required that the AVcc
and DVcc pins be bypassed separately
with bypass capaCitors of 10 I'F
tantalum in parallel with 0.1 I'F ceramic.

CLK(8)

3-100

DI(10)

The serial data input. The data is clocked in
MSB first. Preceding the data by1e are 4 or
6 bits of instructions. The read back
command requires 7 bits of instructions.

DO(7)

The serial data output. The data can be
clocked out either MSB or LSB first, and on
either the positive or negative edge of the
clock.

INT(12)

The power interrupt output. On an
interruption of the digital power supply, this
pin goes low. Since this pin has an open
drain output, a 10 kG pull-up resistor must
be connected to the supply.

Applications information
FUNCTIONAL DESCRIPTION
The DAC1054 is a monolithic quad 10-bit digital-to-analog
converter that is designed to operate on a single 5V supply.
Each of the four units is comprised of an input register, a
DAC register, a shift register, a current output DAC, and an
output amplifier. In addition, the DAC1054 has an onboard
bandgap reference and a logic unit which controls the internal operation of the DAC1054 and interfaces it to microprocessors.

The current output IOUT2' summed with the correction current lEE PROM, is applied to the internal output amplifier and
converted to a voltage. The output voltage of each DAC is a
function of VBIAS, VREF, and the digital input word, and is
given by

Each of the four internal 10-bit DACs uses a modified R-2R
ladder to effect the digital-to-analog conversion (Figure 5).
The resistances corresponding to the 2 most significant bits
are segmented to reduce glitch energy and to improve
matching. The bottom of the ladder has been modified so
that the voltage across the LSB resistor is much larger than
the input offset voltage of the buffer amplifier. The input
digital code determines the state of the switches in the ladder network. An internal EEPROM, which is programmed at
the factory, is used to correct for linearity errors in the resistor ladder of each of the four internal DACs. The codes
stored in the EEPROM's memory locations are converted to
a current, IEEPROM, with a small trim DAC. The sum of currents IOUTl and IOUT2 is fixed and is given by

The output voltage range for each DAC is 0.3V-2.8V. This
range can be achieved by using the internal 2.65V reference
and a voltage divider network which provides a VBIAS of
1.40V (Figure 6). In this case the DAC transfer function is

1023
DATA 2047
VOUT=2(VREF-VBIAS)--+--VBIAS---VREF
1024 512
512

(DATA)
VOUT = 2.5 1024 + 0.30244
The output impedance of any external reference that is
used will affect the accuracy of the conversion. In order that
this error be less than % LSB, the output impedance of the
external reference must be less than 20.

I
+ I
_ (VREF - VBIAS) 1023
OUTl
OUT2 R
1024

TUH/11437-16

FIGURE 5. Equivalent Circuit of R·2R Ladder and Output Amplifier

IO.Ok

>--+- VOUTI

VREF1

(0.3V- 2.8V)

VSIASI

.E.'~

VREF2

>--+-VOUT2 (0.3V - 2.8V)
VSIAS2

VREF3

>--+- VOUT3

(0.3V - 2.8V)

>---1-- VOUT4

(O.3V - 2.8V)

VSIASJ

VREF4

VSIAS4

11.3k

TL/H/11437-17

FIGURE 6. Generating a VBIAS = 1.40V from the Internal Reference, Typical Application
3-101

•

Digital Interface
The DAC1054 has two interface modes: a WRITE mode
and a READ mode. The WRITE mode is used to convert a
10-bit digital input word into a voltage. The READ mode is
used to read back the digital data that was sent to one or all
of the DACs. The WRITE mode maximum clock rate is
10 MHz. READ mode is limited to a 5 MHz maximum clock
rate. These modes are selected by the appropriate setting
of the RD/WR bit, which is part of the instruction byte. The
instruction byte precedes the data byte at the DI pin. In both
modes, a high level on the Start Bit (SB) alerts the DAC to
respond to the remainder of the input stream.
Table I lists the instruction set for the WRITE mode when
writing to only a single DAC, and Table" lists the instruction
set for a global write. Bits AO and A 1 select the DAC to be
written to. The DACs are always written to MSB first. All
DACs will be written to sequentially if the global bit (G) is

high; DAC 1 is written to first, then DACs 2, 3 and 4 (in that
order). For a global write bits AO and A 1 of the instruction
byte are not required (see Figure 2 timing diagram). If the
update bit (U) is high, then the DAC output(s) will be updated on the rising edge of ~; otherwise, the new data byte
will be placed only in the input register. Chip Select ('CS)
mu!!t remain low for at least one clock cycle after the last
data bit has been entered. (See Figures 1 and 2)
When the U bit is set Iowan asynchronous update of all the
DAC outputs can be achieved by taking AU low. The contents of the input registers are loaded into the DAC registers, with the update occurring on the falling edge of AU. ~
must be held high during an asynchronous update.
All DAC registers will have their contents reset to all zeros
on power up.

TABLE I. WRITE Mode Instruction Set (Writing to a Single DAC)

U

SB

RD/WR

Bit #1

Bit #2

1

0

0

0

0

1

0

0

0

1

0

0

0

1

0

0

1

0

1

0

1
1

G

A1

AD

Description

Bit #3 Bit #4 Bit #5 Bit #6
0

Write DAC 1, no update of DAC outputs

0

1

Write DAC 2, no update of DAC outputs

1

0

Write DAC 3, no update of DAC outputs

0

1

1

Write DAC 4, no update of DAC outputs

0

1

0

0

Write DAC 1, update DAC 1 on CS rising edge

0

1

0

1

Write DAC 2, update DAC 2 on CS rising edge

0

0

1

1

0

Write DAC 3, update DAC 3 on CS rising edge

0

0

1

1

1

Write DAC 4, update DAC 4 on CS rising edge

TABLE II. WRITE Mode Instruction Set (Writing to all DACs)
SB

RD/WR

G

U

Bit # 1

Bit #2

Bit #3

Bit #4

1

0

1

0

1

0

1

1

Description
Write all DACs, no update of outputs
' Write all DACs, update all outputs on CS rising edge

3-102

Digital Interface (Continued)
following rising clock edges. With the RIF bit low, DO goes
out of TRI-STATE on the falling edge that occurs 1 clock
cycle after the end of the instruction byte; the data will continue to be sequentially clocked by the next falling clock
edges. The rising edge of CS returns DO to TRI-STATE.
Read back with the RIF bit set high is not MICROWIRE
compatible. One can choose to read the data back MSB
first or LSB first by setting the MIl bit. (See Figures 3 and
4)

Table III lists the instruction set for the READ mode. By the
appropriate setting of the global (G) and address (A1 and
AO) bits, one can select a specific DAC to be read, or one
can read all the DACs in succession, starting with DAC 1.
The RIF bit determines whether the data changes on the
rising or the falling edge of the system clock. With the RIF
bit high, DO goes out of TRI-STATE on the rising edge that
occurs 1112 clock cycles after the end of the instruction byte;
the data will continue to be sequentially clocked out by the

g
o
....
o
en

~

TABLE III. READ MODE Instruction Set
SB

RD/WR

G

RIF

MIL

A1

AO

Bit #1

Bit #2

Bit #3

Bit #4

Bit #5

Bit #6

Bit #7

1

1

0

0

0

0

0

Read DAC 1, LSB first, data changes on the falling edge

1

1

0

0

0

0

1

Read DAC 2, LSB first, data changes on the falling edge

Description

1

1

0

0

0

1

0

Read DAC 3, LSB first, data changes on the falling edge

1

1

0

0

0

1

1

Read DAC 4, LSB first, data changes on the falling edge

1

1

0

0

1

0

0

Read DAC 1, MSB first, data changes on the falling edge

1

1

0

0

1

0

1

Read DAC 2, MSB first, data changes on the falling edge

1

1

0

0

1

1

0

Read DAC 3, MSB first, data changes on the falling edge

1

1

0

0

1

1

1

Read DAC 4, MSB first, data changes on the falling edge

1

1

0

1

0

0

0

Read DAC 1, LSB first, data changes on the rising edge

1

1

0

1

0

0

1

Read DAC 2, LSB first, data changes on the rising edge

1

1

0

1

0

1

0

Read DAC 3, LSB first, data changes on the rising edge

1

1

0

1

0

1

1

Read DAC 4, LSB first, data changes on the rising edge

1

1

0

1

1

0

0

Read DAC 1, MSB first, data changes on the rising edge

1

1

0

1

1

0

1

Read DAC 2, MSB first, data changes on the rising edge

1

1

0

1

1

1

0

Read DAC 3, MSB first, data changes on the rising edge

1

1

0

1

1

1

1

Read DAC 4, MSB first, data changes on the rising edge

1

1

1

0

0

1

0

Read all DACs, LSB first, data changes on the falling edge

1

1

1

0

1

1

0

Read all DACs, MSB first, data changes on the falling edge

1

1

1

1

0

1

0

Read all DACs, LSB first, data changes on the rising edge

1

1

1

1

1

1

0

Read all DACs, MSB first, data changes on the rising edge

Power Fail Function

Power Supplies

The DAC1054 powers up with the INT pin in a Low state. To
force this output high and reset this flag, the CS pin will have
to be brought low. When this is done the iNT output will be
pulled high again via an external 10 kO pull-up resistor. Anytime a power failure occurs on the DVee line, the INT will be
set low when power is reapplied. This feature may be used
by the microprocessor to discard data whose integrity is in
question.

The DAC1054 is designed to operate from a + 5V (nominal)
supply. There are two supply lines, AVec and DVec. These
pins allow separate external bypass capacitors for the analog and digital portions of the circuit. To guarantee accurate
conversions, the two supply lines should each be bypassed
with a 0.1 JoLF ceramic capacitor in parallel with a 10 JoLF
tantalum capacitor.

3-103

•

~

It)

.S!

r------------------------------------------------------------------------------------------,

g

Typical Applications
10k

10.2k

Y,N ---YIII'v------1I_-..;....Jt,JIIv---.
:t:2.5V

1M

"our
>~-+OV AVec
VOUT1

+5V

.

VREF1

1-.....- -....--.....,

VREF OUT

470k

to.Ok

VBIAS1

J-----.

DAC1054

1'.3k

154k

137k

TL/H/11437-18

FIGURE 7. Trimming the Offset of a 5V Op Amp Whose Output Is Biased at 2.5V
"
.
"
.
'~

16.2k

Your

6.73k

TL/H/11437-18

...FIGURE 8. Trimming the C?Hset of a Dual Supply Op Amp (VIN Is Groun!l Referenced).

VOUl1

VREF1 1 -. . .- -....- - 0 1

VREF OUT

,E20 P F
VBIAS11----.....

DAC1054

1'.3k

TUH/11437-20

FIGURE 9. Bringing the Output Range Down to Ground

3-104

.----------------------------------------------------------------------,0

~
.....

IJ1National Semiconductor

I\)

Q

CO

.......

MICRO-DAC™ DAC1208/DAC1209/DAC1210/DAC12301
DAC1231/DAC1232 12-Bit, ILP Compatible,
Double-Buffefed D to A Converters
General Description

Features

The DAC1208 and the DAC1230 series are 12-bit multiplying D to A converters designed to interface directly with a
wide variety of microprocessors (8080, 8048, 8085, 2-80,
etc.). Double buffering input registers and associated controllines allow these DACs to appear as a two-byte "stack"
in the system's memory or I/O space with no additional interfacing logic required.
The DAC1208 series provides all 12 input lines to allow single buffering for maximum throughput when used with 16-bit
·processors. These input lines can also be externally configured to permit an 8-bit data Interface. The DAC1230 series
can be used with.an 8-bit data bus directly as it internally
formulates the 12-bit DAC data from its 8 input lines. All of
these DACs accept left-justified data from the processor.
The analog section is a precision silicon-chromium (Si-Cr)
R-2R ladder network and twelve CMOS current switches.
An inverted R-2R ladder structure is used with the binary
weighted currents switched between the IOUTl and IOUT2
maintaining a constant current in each ladder leg independent of the switch state. Special circuitry provides TTL logic
input voltage level compatibility.
The DAC1208 series and DAC1230 series are the 12-bit
members of a family of !f]icroprocessor compatible DACs
(MICRO-DACSTM). For applications requiring other resolutions, the DAC1000 series for 10-bit and DAC0830 series
for 8-bit are available alternatives.

... Linearity specified with zero and full-scale adjust only
[I Direct interface to all popular microprocessors
II Double-buffered, single-buffered or flow through digital
data inputs
I!I Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
m Works with ± 1OV reference-full 4-quadrant
multiplication
!l Operates stand-alone (without ~P) if desired
r::J All parts guaranteed 12-bit monotonic
III DAC1230 series is pin compatible with the DAC0830
series 8-bit MICRO-DACs

1 ~s
12 Bits

13 Current Settling Time
iii Resolution

I:J Linearity (Guaranteed

over temperature)
Gain Tempco
r::J Low Power Dissipation
I:J Single Power Supply

10,11, or 12 Bits of FS
1.3 ppmrC
20 mW
5 VDC to 15 VDC

.Typical Application
CONTROL BUS

fS

VCC

san
fULL·SCALE
A~JUST

I&V

.."'111----1\1

w

DATA BUS

,>-o--VOUT

-15V

TUH/5690-1

3-105

I\)

Q

.....
CD

~.....
I\)
.....

Q
.....

~.....

I\)
Co)

Q

.......

~
.....
.....
.......
I\)
Co)

~
.....

Key Specifications

til

o
~
.....

I\)
Co)
I\)

C\I

C'I)

C\I
.,..
o

~
......
.,..

C'I)

C\I
.,..

~......
cC'I)

C\I
.,..

~

......
c

.,..
C\I
.,..

~......
en

c

C\I
.,..

Absolute Maximum Ratings

Supply Voltage (Vecl
Voltage at Any Digital Input

co
c

o
~

Lead Temperature (Soldering, 10 sec.)

-65'Cto + 150'C

Package Dissipation at TA = 25'C
(Note 3)

500mW

DC Voltage Applied to IOUT1 or IOUT2
(Note 4)
ESD Susceptability

3000C

Temperature Range
TMIN s: TA s: TMAX
DAC1208LCJ, DAC1209LCJ,
DAC1210LCJ, DAC1230LCJ,
DAC1231LCJ, DAC1232LCJ,
DAC1231L1N, DAC1232L1N
-40'C s: TA s: +85'C
DAC1208LCJ·1, DAC121 OLCJ·1,
DAC1230LCJ·1, DAC1231 LCJ·1,
DAC1232LCJ·1, DAC1231 LCN,
DAC1232LCN, DAC1231 LCWM,
. DAC1232LCWM
OOC s: TA s: +700C

17VDe
VectoGND
±25V.

Voltage at VREF Input
Storage Temperature Range

Range of Vee
Voltage at Any Digital Input

-100mVtoVee
800V

4.75 Voeto 16 Voe
VcctoGND

Electrical Characteristics
VREF= 10.000 VDe, Vee = 11.4 Voe to 15.75 Voe unless otherwise noted. Boldface limits apply from TMIN to TMAX (see
Note 13); all other limits TA = TJ = 25'C.

~......
C\I
.,..

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Notes 1 and 2)

Parameter

Conditions

Notes

Resolution
Linearity Error
(End Point Linearity)

Differential Non·Linearity

Gain Error (Max)

Output Capacitance

IOUT2

12

12

12

Bits

±0.018
±0.024
±0.050

·±0.018
±0.024
±0.05

%ofFSR
%ofFSR
%ofFSR

±0.018
±0.024
±0.050

±0.018
±0.024
±0.05

% ofFSR
% ofFSR
.% ofFSR

12

4,7,13

4

12

12

Using Internal RFb
V,el = ±10V, ±1V

7

-0.1

0.0
-0.2

All Digital Inputs
Latched High

VREF=20 Vp·p, f= 100 kHz
All Data Inputs Latched
Low
All Data Inputs
Latched High
All Data Inputs
Latched Low

7

-0.1

7

±1.3

7

±3.0

±30

13

15
15

10
20

9

3.0

13
All Data Inputs Latched
Low
All Data Inputs Latched
High

Bits
%ofFSR
%ofFSR

±8.0

ppm of FSI'C
ppm of FSRIV

10
20

kn
mVp~p

200
70
70
200

pF
pF
pF
pF

2.0

2.5

mA

IOUT1
IOUT2
IOUT1
IOUT2

Supply Current Drain
Output Leakage Current
IOUT1

Units

Zero and Full·Scale
Adjusted
DAC1208, DAC1230
DAC1209, DAC1231
DAC1210, DAC1232

Reference Input Resistance (Min)
Reference Input Resistance (Max)
Output Feedthrough Error

Design
Limit
(Note 6)

4,7,13

Gain Error Tempco
Power Supply Rejection

Tested
Limit
(Note 5)

Zero and Full·Scale
Adjusted
DAC1208, DAC1230
DAC1209, DAC1231
DAC1210, DAC1232

Monotonicity
Gain Error (Min)

Typ
(Note 10)

11,13

0.1

15

15

nA

11,13

0.1

15

15

nA

Digital Input Threshold

Low Threshold
High Threshold

13
13

0.8
2.2

0.8
2.2

Voe
VOC

Digital Input Currents

Digital Inputs <0.8V
Digital Inputs > 2.2V

13
13

-200
10

-200
10

""Aoe
""AoC

3·106

Electrical Characteristics (Continued)
= 10.000 VDC, VCC = 11.4 VDC to 1S.7S VDC unless otherwise noted. Boldface limits apply from TMIN to TMAX (see
Note 13); all other limits TA = TJ = 2S'C.

VREF

Symbol

Parameter

Conditions

See

Typ

Note

(Note 10)

Tested

Design

Limit

Limit

(NoteS)

(Note 6)

Units

Current Setting Time

VIL

= OV, VIH = SV

1.0

tw

Write and XFER

VIL

= OV, VIH =

SO

SV

Pulse Width Min.
VIL = OV, VIH

Data Setup TIme Min.

8

,...s
320

320

= 5V

70

320

Data Hold TIme Min.

VIL

= OV, VIH = SV

'30

90

90
Control Setup Time Min.

VIL = OV, VIH

= SV

60

ns

320

320
tCH

~....

Control Hold Time Min.

VIL

= OV, VIH = SV

0

10

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specilied operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: This SOO mW specification applies for all packages. The low intrinsic power dissipation of this pari (and the fact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking.
Note 4: Both loun and IOUT2 must go to ground or the virlual ground of an operational amplHier. The linearity error is degraded by apprOximately Vos'" VREF. For
example, H VREF=10V then a 1 mV offse~ VOS, on loun or IOUT2 will introduce an additional 0.01% linearity error.
Nota 5: Tested and guaranteed to National's AOQL (Average OutgOing Quality Level).

Note 7: The un~ FSR stends for full-scale range. Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a parlicular
VREF value to indicate the true performance of the part. The Unearity Error specification of the DAC1208 is 0.012% of FSR(max). This guarantees that after
performing a zero and full-scale adjustment, the plot of the 4096 analog voltage outputs will each be within 0.012% X VREF of a straight line which passes through
zero and full-scale. The un~ ppm of FSR(parts per million of full-scale range) and ppm of FS(parts per million of full-scale) are used for convenience to define specs
of very small percentage values, typical of higher accuracy converters. In this instance, I ppm of FSR=VREF/l0S is the conversion factor to provide an actual
outpul voltage quantity. For example. the gain error tempco spec of ±6 ppm of FSrC represents a worst-case full-scale gain error change wilh temperalure from
-4O'C to +85'C of ±(6)(VREF/l0S)(12S'C) or ±O.75 (10- 3) VREF which Is ±0.075% of VREF.
Note 8: This spec implies Ihal all parts are guaranteed to operate with a write pulse or transfer pulse width (tw) of 320 ns. A typical pari will operate ~h tw of only
100 ns. The entire write pulse must occur within the valid data interval for the specified tw, los. tOH and Is to apply.
Note 9: To achieve this low feedthrough in the D package, the user must ground the metal lid. If the lid is left floating the feedthrough is typically 6 mY.
Note 10: Typicals are at 25'C and represent Ihe mosllikely parametric norm.
Note 11: A 10 nA leakage currenl with RFb=20k and VREF=IOV corresponds to a zero error of (10XIO-9X20XI03)XI00% 10V or 0.002% of FS.
Note 12: Human body model. 100 pF discharged through a 1.5 kO resistor.
Note 13: Tesled limit for -1 suffix parts applies only at 25'C.

Connection Diagrams

.ND.1
DI•

...!
DACt.

DI,

DACUGI,
DActlSl

..J.

VaEF

j!l..m

.ND...!.

.!!."R2

~XfER

D~...!.

~XFER

DI• ...!.

f!!- D17

DI,...!.

fl!. DI,

DI,

..!!

-.. .!!
••• .!!

DAC1ue.
DACI131.
DAelm

~DllI(MS11

- .. ...!.

~IDun

••• ..!!

tl'- D,,{D1iJ
fl1.DI'lDlli

~DI"ID~i

..!.

v_.. "'!'

~DII'

DI11LSlI..!

~'YTEII1""ffi1

j!l.. aYTEl/inTI

~D~

DII...!

.!!. Vee

Wiii...!.

jl!.DI,

D" ...!.
DI, ...!

Dual-In-Llne Package

.. ..!.

~vcc

.. ...!

Wiiiol

fl!.olnCMIIJIDI:.1

r!!-IDun

~IDUTI
TOP VIEW

fl!.laun

TL/H/5690-2

TOPYIEW

See Ordering Information
3-107

g
o
....
N
....
o

~....

-~
N

Co)

o

....
N
....
.....
Co)

~....
N

Co)

N

Note 6: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Guaranteed for Vee = 11.4V to IS.7SV
and VREF = -IOV to + 10V.

Dual-In-Line Package

CD
.....

......

320

tcs

o

o

ts

tDH

N

«XI
.....

N

AC CHARACTERISTICS

tDS

~....

~

...
~

r------------------------------------------------------------------------------------------,
Switching Waveforms

g
.....

tcs----I

...~
...

CS, BYTE l/WiTZ

~
i...

511%
V,L ________ .,,_ _ _ _ _ _ _

+_-'

VIH

liii
VIL

~

VIH

~

.50%

DATA BITS

SO%

VIL

......

ts_~

Ci
~

10UTt,IOUTZ

g
~...

g
.....
CD

...

o

~

g

511%

_ _______

..Jr~SE"LEDTD
"/2 LSB

TLlH/5690-3

Typical Performance Characteristics
Digital Input Threshold
vsVee
~

~

~
..
j!;

..

Digital Input Threshold vs
Temperature

Z.4

2.4

2.0

~ 2.0
TA!-eic

1.&

1.2

~

~

0.8

Ci

OA

o

ITA .,21fC

TA-asoc f-

--

~

l..-

1.6

~

i-- Ii--

10

ffi
!!

:-o.oas
:E

li

25 45 &5 85

-35 -15

~

400

..."

~
~

-11",

200

I

100

fl

15

!9

I
l - i-

I-

5

VI~L-~V

25 45 65 IS

I

vrTT

SOD

v

r····m

400

V~c·~v,1

300

VCC"5V,

I

- -

r-t--r- - ----: ... !== -:-

200

I

r-~~

S' 100

r-- -

Vec -15V

5

25

45

65

85

-35 -15

TA - AMBIENTTEMPERATURE I'CI

Write Pulse Width, tw

5

25

45

65

85

TA - AMBIENTTEMPERATURE I'CI

Data Set-Up Time; tos

VI~L _~

I
VINH' 3V TO 5V

I

:!

SOD

VI~L .Jv

I

VINH' 3V TO 5V

~
;: 400

~ 400

~

300

100

."
S
"..

f- r- ::rc~!OV
-35 -15

VCC - SUPPLY VOLTAOE IVDcl

.s
""

I
Vce' 5V

z

Zl

I
VINH -3VT05V

300

~LlNEARITY'

Data Hold Time, tOH

VI~L -~V

500

-

TA - AMBlENTTEMPERATURE rCI

Control Set-Up Time, tes

A

I-

.....01

TA - AM81ENTTEMPERATURE reI

~'GAr;;"ERRJR

IiJ. 200

~

~+~
-",-".

,.

,.

~-O.o05

t-t-t-t--l-+-+-+-+--l
-35 -15 5

I

i

ffi

..

- -~~ERR!R- -

500

0.00&

z

0.8

IS

10

~

t-t-t-t-+

~

TA-ZS'C

~ D.D05

..

t--"'::,...;I:--l-+-

0.01

!!

Gain and Linearity Error
Variation vs Supply Voltage
0.01

VCC- 15 VDC
~

t-t-t-P""'''''''oC!'o+--I--l

,VCC-SUPPLY VOLTAGE IV)

~

r-""";,-,-.,-,---,--.--.-..,
I-t-+-+-+-+-+-++-l

~ 1.2

is 0.4

o

Gain and Linearity Error
Variation vs Temperature

ff-

-::::: ~
-VCC"OV

~ 300
S 200

-

"I
M

S' 100

-- R

_~CC'5V

CC "OV_

5

25

45

&5

r--r--

Vcc· , &V

VCC-15V
-35 -15

I-

_

15

-35 -15

TA - AMBIENTTEMPERATURE I'CI

5

25

45

&5

85

TA - AM81ENTTEMPERATURE rCI
TL/H/5690-4

3-108

the DAC1230, DAC1231, and DAC1232 must be connected
to ground. It is important that lOUT1 and lOUT2 are at ground
potential for current switching applications. Any difference
of potential (Vos on these pins) will result in a linearity
change of

Definition of Package Pinouts
CONTROL SIGNALS (all control signals are level actuateq)
CS: Chip Select (active low). The 'CS will enable WR1.
WR1: Write 1. The active low WR1 is used to load the digital
data bits (01) into the input latch. The data in the input latch
is latched when WA1 is high. The 12-bit input latch is split
into two latches. One holds the first 8 bits, while the other
holds 4 bits. The Byte 1/Byte 2 control pin is used to select
both latches when Byte l/Byte 2 is high or to overwrite the
4-bit input latch when in the low state;

For example, if VREF = 10V and these ground pins are 9
mV offset from lOUT1 and lOUT2' the linearity change will be
0.03%.

Definition of Terms

Byte lIByte 2: Byte Sequence Control. When this control is
high, all 12 locations of the input latch are enabled. When
low, only the four least significant locations of the input latch
are enabled.
WR2: Write 2 (active low). The WR2 will enable XFER.

Resolution: Resolution is defined as the reciprocal of the
number of discrete steps in the DAC output. It is directly
related to the number of switches or bits within the DAC. For
example, the DAC120B has 212 or 4096 steps and therefore
has 12-bit resolution.
linearity Error: Linearity error is the maximum deviation
from a straight line passing through the endpoints of the
DAG transfer characteristic. It is measured after adjusting
for zero and full·scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.

XFER: Transfer Control Signal (active low). This signal, in
combination with WR2, causes the 12-bit data which is
available in the input latches to transfer to the DAC register.
DID to 0111: Digital Inputs. DID is the least significant digital
input (lSB) and 0111 is the most significant digital input
(MSB).

National's linearity test (a) and the best straight line test (b)
used by other suppliers are illustrated below. The best
straight line (b) requires a special zero and FS adjustment
for each part, which is almost impossible for the user to
determine. The end point test uses a standard zero FS adjustment procedure and is a much more stringent test for
DAC linearity.

IOUT1: DAC Current Output 1. loun is a maximum for a
digital code of all 1s in the DAC register, and is zero for all
Os in the DAC register.
IOUT2: DAC Current Output 2. IOUT2 is a constant minus
IOUT1' or IOUT1 + IOUT2 = constant (for a fixed reference
voltage). This constant current is
VREF X ( 1 -

4d96)

~

o
.....
N

o

co
......

~.....

N

oCQ

.....

~
.....
N
.....
o
......

~
.....
N
c,,)

o
.....
C

~
.....
N

c,,)
.....
......

~.....
N

c,,)

N

Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.
Settling Time: Full-scale current settling time requires zero
to full-scale or full-scale to zero output change. Settling time
is the time required from a code transition until the DAC
output reaches within ± % lSB of the final output value.

divided by the reference input resistance.
RFb: Feedback Resistor. The feedback resistor is provided
on the IC chip for use as the shunt feedback resistor for the
external op amp which is used to provide an output voltage
for the DAC. This on-chip resistor should always be used
(not an external resistor) since it matches the resistors in
the on-chip R-2R ladder and tracks these resistors over
temperature.

Full·Scale Error: Full-scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC120B or DAC1230 series, full-scale is
VREF-1 LSB. For VREF= 10V and unipolar operation,
VFULL.SGALE = 1O.OOOOV - 2.44 mV = 9.9976V. Full-scale
error is adjustable to zero.

VREF: Reference Voltage Input. This input connects an external precision voltage source to the internal R-2R ladder.
VREF can be selected over the range of 10V to -10V. This
is also the analog voltage input for a 4-quadrant multiplying
DAC application.
Vee: Digital Supply Voltage. This is the power supply pin for
the part. Vee can be from 5 Vee to 15 VeG. Operation is
optimum for 15 VeG.

Differential Non·linearity: The difference between any
two consecutive codes in the transfer curve from the theoretical 1 LSB is differential non-linearity.
Monotonic: If the output of a DAC increases for increasing
digital input code, then the DAC is monotonic. A 12-bit DAC
which is monotonic to 12 bits simply means that input increasing digital input codes will produce an increasing ana·
log output.

GND: Pins 3 and 12 of the DAC1208, DAC1209, and
DAC1210 must be connected to ground. Pins 3 and 10 of

DIGITALINI'UT

a) End Point Test After Zero
and FS Adjust

b) Shifting FS Adjust to Pass
Best Straight line Test
3-109

TLlH/5690-5

•

N

r---------------------------------------------------------------------------------~

C')

,...
o
N

~
......

C ')

,...

N

o
~
......
oC')

,...
N

g
......
o
,...
,...

N

All of the digital inputs to these DACs contain a unique
threshold regulator circuit to maintain TIL voltage level
compatibility independent of the applied Vee to the DAC.
Any input can also be driven from higher voltage CMOS
logic levels in non-microprocessor based systems. To prevent damage to the chip from static discharge, all unused
digital inputs should be tied to Vee or ground. As a troubleshooting aid, if any digital input is inadvertently llilft floating,
the DAC will interpret the pin as a logic "1".

Application Hints
1.0 DIGITAL INTERFACE
These DACs are designed to provide all of the necessary
digital input circuitry to permit a direct interface to a wide
variety of microprocessor systems. The timing and logic level convention of the input control signals allow the DACs to
be treated as a typical memory device or 1/0 peripheral with
no external logic required in most systems. Essentially
these DACs can be mapped as a two-byte stack in memory
(or 1/0 space) to receive their 12 bits of input data in two
successive 8-bit data writing sequences. The DAC1230 series is intended for use in systems with an 8·bit data bus.
The DAC1208 series provides all 12 digital input lines which
can be externally configured to be controlled from an 8-bit
bus or can be driven directly from a 16-bit data bus.

Double buffered digital inputs allow the DAC to internally
format the 12-bit word used to set the current switching R2R ladder network (see section 2.0) from two 8-bit data
write cycles. Figures 1 and 2 show the internal data registers and their controlling logic circuitry. The timing diagrams
for updating the DAC output are shown in sections 1.1, 1.2
and 1.3 for three possible control modes. The method used
depends strictly upon the particular application.

g
......
Q)

o

,...

N

g
......
CO

o

N
,...
o

DII1IMSB }

01.
01,

01,
OIB
01,

19
20

,

OlolLSI}

WRI

I·BIT
INPUT
LATCH

Q

0

Q

0
0

Q

0

1

::::12

of---of----

.... .!! loun

0---of---0 ____
12·8IT Q
DAe
REGISTER 11

'2·811
MULTIPLYING
DIA
CONVERTER

I--f----

L....!!

LE

•
"
:::'2

o

Q

-~
-i!!-

0 - - - - MS•

0
0

0

7

illii 11
WR2

Q

I

cs

0
0

Q

e

013

BYTElIiVffi

0
0
0

4

~

01 2
01,

0
0
0

11
II

01.

•

0

"

16

:J

0

Of---D

01---

o 4·BIT
o ~:~~~

11 f - - - 0

0

Q

Q I--of---of----

p-

Q

f--f---

0
0

!!
!...
!!.

LSB

Vee
GND
GND

LE

1LE

When
When

~

CE = I, Q oulput. follow 0 Input.
CE = 0, Q outputs are latched

FIGURE 1. DAC1208, DAC1209, DAC1210 Functional Diagram

13
0111IMSB1I013 }
01,01012 }
15
OlglOl, }
16
01. 1010}
01,
5
01.
e
01,
' Dl4 7

"

0

0

0
0

Q

0
0

0
1--0 ____

0
0

0
0

of---0 ____

Q

0

0
0

Q

0
0

0

Q

0

•

0

I·BIT
INPUT
LATCH

of----

o

012·11T 0 OAe
REGISTER Q

Q

0

Q----

Q

0

Q----

0

0 ____

0

Q ----

Q

-

MSB

!.
!!.
.... ll loun

U·8rT
MULTIPLYING

-

OIA
CONVERTER

i!-

LE
0

o 4·81T
o ~:~~1
0
BYTE "BYTE 2

"
1
;::2
11

~.

::J

ru-

f--f--0 I-of---

~

LSB

f!.
il!.

Vee
GND
GNO

LE

ILE

When
When

:J

CE =I, Q oulpul. follow 0 Input.
CE =0, Q oulpul. arelalched
TL/H/5690-6

FIGURE 2. DAC1230, DAC1231, DAC1232 Functional Diagram

3-110

c

lj

Application Hints (Continued)
1.1 Automatic Transfer
The 12-bit DAC word is automatically transferred to the DAC register and the R-2R ladder when the second write (the 4 LSBs of
the data) occurs.
DATA IUS

---<'"__

v_AL_ID_ _

.J)>-----~('"_ _V_A_LlD_~)>------'....;...-

\'-___~f

~....
N
....

'"_ _ _ _ _=-::::-:=:::-_ _

XfEii

.....

0'

/J

ANALDG DUTPUT
PDATED
i";:::':':':A!;N"'AL"'D"'"G"'DU""T""PU"'T\
. _
LATCHED

\'-_---Jf
LDAD I·IIT INPUT
LATCH (4.IIT INPUT
LATCH ALSD CHANGEDI

'~

o....
N
W

DVERWRITE THE 4·IIT
INPUT LATCH AND TRANSfER
ALL 12 alTS TO THE O/A

TLiH/S690-7

1.2 Independent Processor Transfer Control
In this case a separate address is decoded to provide the XFER signal.'This allows the processor to load the next required DAC
word but not change the analog output until some time later, most useful for the simultaneous updating of several DACs in a
system where their XFER lines would be tied together.
DATA IUS

~
....
N

.....

InEI~------------------------------~\

Wiil AND Wii1

o

CD
.....

Q
CQ

a~~________~f
AND

....
N

----«:===~VA~L~ID===:)~---..;...~('"_ _VA_Ll_D_.J>- _ - - - - - - - - - - -__

o
.....
C

~
....
N
W
....
.....

~
....
N
W
N

\'"______..J.l:....~:: : : : : : : : : :

anE 1/iiVft2

\\... _ _~f
Wiil AND WiiZ

ANALOD DUTPUT
UPDATED
ANALDD OUTPUT
LATCHED

.

LOAD HIT INPUT
LATCH 14·11T INPUT
LATCH ALSD CHANGEDI

OVERWRITE 4-8IT
INPUTLATCH

TRANSfER 12·IIT DAC
WDRD TD THE D/A

TL/H/5690-8

1.3 Transfer via an External Strobe
This method is basically the same as the previous operation except the XFER signal is provided by a device other than the
processor. This allows the DAC to hold the code for a conditional analog output signal which will be required on demand from an
external monitoring device (an analog voltage comparator for instance).
'

_V_A_Ll_D_...J)~---« ....._ _VA_LI_D_...J)~--...

DATAIUS---« .....

\ ....._ _ _ _ _ _ _ _ _ _ _ _ _

InEI/IVTE2

-

l--.;;...--------r -- - -- -- -- -- --------------I

WRI

.

LDAD 8·IIT INPUT
LATCH 14-8IT INPUT
LATCH ALSD CHANGEDI

.

DVERWRITE 4·IIT
INPUTLATCH

WIl2 lied 10 a logic low (OV)

ANALOG OUTPUT UPDATED
AND LATCHED

TLiH/5690-9

3-111

•

~ ~--------------------------------------------------------------------------------,
CO)
~

....

g
....
....
CO)
~

....

g
g
....
~

g

Application Hints (Continued)

Ci

r--HIIYTE-r-LO IYTE-I

....

IIISB"::OACOATAFLSI

~

g
...•
....~

IYTE I

x-

....
~

1.6 Flow·Through Operation
Through primarily deSigned to provide microprocessor inter·
face compatibility, the MICRO·DACs can easily be config·
ured to ailow the analog output to continuously reflect the
state of an applied digital input. This is most useful in appli·

x x x xl

IYTEZ
TUH/5690-10

don'l care

FIGURE 3. Left-Justlfled Data Format

g
~

1.5 16-Blt Data Bus Interface
The' DAC120B series provides all 12 digital input, lines to
permit a direct parallel interface to a 16-bit data bu!? In this
instance, double buffering is not always necessary (unless a
simultaneous updating of several DACs or a data transfer
via an external strobe is desired) so the 12-bit DAC register
can be wired to flow·through whereby its Q outputs always
reflect the state of its 0 inputs. The external connections
required and the timing diagram for this single buffered ap·
plication are shown in Rgure 4. Note that either left or right·
justified data from the processor can be accommodated
with a 16-bit data bus.

1.4 Left·Justlfled Data Format
It is important to realize that the input registers of, these
DACs are arranged to accept a left·justified data word from
the microprocessor with the most significant B bits coming
first (Byte 1) and the lower 4 bits second. Left justification
simply means that the binary point is assumed to be located
to the left of the most significant bit. Figure 3 shows how the
12 bits of DAC data should be arranged in 2 B·bit registers
of an B·bit processor before being written to the DAC.

Interface Timing
JUSTIFIED
RIGHT LEFT
Dill

-----O': .;.::::::..t
151 Msa

011& ....

g

1::.
8

Q

D

171

Q

o

~:::::::::~~:~:zol:~::~ 0LATCH
I~:~~

~
II-IIT ......
DATA IUS

----0.::::---1

0

41

Q

Q
Q

Ii
Q

51
•

DID

12·BIT

Q

OAC
REGISTER

I
I
I

084

TO
CURRENT
SWITCHES

Q
Q

Q

il

il

VCC

SYSTEM

iiii STROlE

18-BIT

DATA IUS

cs

<

VALID

~

>
I

OUTPUT
iiiil ANALOGUPDATED

ANALOG OUTPUT
LATCHED
TL/H/5690-11

XFER and WF!2 grounded; Byte ./Byte 2 tied 10 Vee.

FIGURE 4. 16-Blt Data Bus Interface for the DAC1208 Series

3-112

Application Hints (Continued)
incrementing, the address for Byte 2) from propagating
through the address word and changing any of the bits decoded for CS or XFER. Figure 5 shows how to prevent this
effect.
The same problem can occur from a borrOw when an autodecremented address is used; but only if the processor's
address outputs are inverted before being decoded.

cations where the DAC is used in a continuous feedback
control loop and is driven by a binary upldown counter, or in
function generation circuits where a ROM is continuously
providing DAC data.
Only the DACt20B, DAC1209, DAC1210 devices can have
all 12 inputs flow-through. Simply grounding CS, WR1, WR2
and XFER and tying Byte 1IByte 2 high allows both internal
registers to follow the applied digital inputs (flow-through)
and· directly affect the DAC analog output.

1.8 Control Signal Timing
When interfacing these MICRO,-DACs to any microprocessor, there are two important time relationships that must be
considered to insure proper operation. The first is the minimum WR strobe pulse width which is specified as 320 ns for
Vcc= 11.4V to 15.75V and operation over temperature, but
typically a pulse width of only 250 ns is adequate. A second
consideration is that the guaranteed minimum data hold
time of 90 ns should be met or erroneous data can be
latched. This hold time is defined as the length of time data
must be held valid on the digital inputs after a qualified (via
CS) WR strobe makes a low to high transition to latch the
applied data.
If the controlling device or system does not inherently meet
these timing specs the DAC can be treated as a slow memory or peripheral and utilize a technique to extend the write
strobe. A simple extension of the write time, by adding a
wait state, can simultaneously hold the write strobe active
and data valid on the bus to satisfy the minimum WR pulse

1.7 Address Decoding Tips
It is possible to map the MICRO-DACs into system ROM
space to allow more efficient use of existing address decoding hardware. The DAC in effect can share the same addresses of any number of ROM locations: The ROM outputs
will only be enabled by a READ of its address (gated by the
system READ strobe) and the DAC will only accept data
that is written to the same address (gated by the system
WRITE strobe).
The Byte 1/Byte 2 control function can easily be generated
by the processor's least significant address bit (AO) by placing the DAC at two consecutive address locations and utilizing double-byte WRITE instructions which automatically increment or decrement the address. The CS and XFER signals can then be decoded from the remaining address bits.
Care must be taken in selecting the actual address used
for Byte 1 of the DAC to prevent a carry (as a result of
Write
Cycle
First
(Byte 1)
Second
(Byte 2)

Address Bits
15

2

\.

J

T

Decoded to
AddressDAC

1·

0··

0

1

1

0

·Starting with a 0 prevents a carry on address incrementing .
• 'Used as Byte 1/!lyi92 Control.

FIGURE 5

ANALOG
OUTPUT

DATA ~
BUS--.J\

SYSTEM
WRITE STROBE

DATA VALID

~

_NORMAL
WRITE STROBE

1250 n~

SYSTEM DATA HOLO TIME 111m!
ONE WAIT_-i-_t-_ _
STATE

1250 ..,

Wii
IOUTPUT OF
ONE-SHOTI

TUH/5690-12

FIGURE 6. Accommodating a High Speed System
3-113

Application Hints (Continued)
easily accomplished by over-compensating the DAC output
amplifier by increasing the value of its feedback capacitor.
In applications requiring a fast output response, from the
DAC and op amp, filtering may not be feasible. In this event,
digital Signals can be completely isolated from the DAC
circuitry, by the use of a DM74LS374 latch,' until a valid
CS signal is applied to update the DAC. This is shown in,

width: If this does not provide a sufficient data hold time at
the end of the write cycle,'a negative edge triggered'oneshot can be included between the system write strobe and
the WR pin of the DAC. This is illustrated in Figure 6 for an
e~emplary !lystem which pr,ovides a 250 ns WR strobe time
with a d,ata hold time of only 10 ns. ,
The proper. data set-up time prior to the latching edge (low
to high transition) of the WR strobe, is insured if the WR
pulse width is within spec and the data is valid on the bus for
the duration. of, the 'DAC WR strobe.

Figure 7.
A single TRI-STATEIIl> data buffer such as the DM81 LS95
can be used to isolate any number of DACs in II, system.
Figure 8 shows this isolating circuitry and decoding hardware for a multiple DAC analog output card. Pull-up resistors are used on the buffer outputs to limit the impedance at
tne DAC digital inputs when the card is not selected. A
unique feature of this card is that the DAC XFER strobes are
controlled by the data bus. This allows a very flexible update
of any combination of analog 'outputs via a transfer word
which would contain a zero in the bit pOSition assigned to
any of the DACs required to change to a new output value.

1."

Qigltal Signal Feedthrough
A typical microprocessor is a tremendous potential source
of high frequency noise which'can, be coupled to sensitive
analog circuitry. The fast edges of the data and address bus
signals generate frequency components of 1D's of megahertz and may cause fast transients to appear at the DAC
output,- even when data is latched internally.
In low frequency of DC applications, low pass filtering can'
reduce' the" magnitude of any fast transients. This is most

ANALOG
OUTPUT

CS FROM .....H I - - - - - ,
ADDRESS ....
DECODER '

+ ..........r ......

Wii :ro~~ ~+-iH
Xffii FROM

+-+-.....,1-"

ADDRESS ....
DECODER
ADDRESS BIT 0

H~:: ~~: :~~~ ~ ~-t-....,~")o-_______.......
TLlH/5690-13

FIGURE 7. Isolating Da~ Bus from DAC Circuitry to Eliminate Digital NOise Coupling

3-114

Application Hints (Continued)

IV

~"

8G"IUS

r-

All
A14
A13
AIl
An
AID

BI
BI
B4
B3
BI
Bl

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DB
D5
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va
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AB
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VB

A4

V4
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A3
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D4
D3
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DAC1Z30

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11/3 DM70L97 BUFFER

5.1.

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VI

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rn

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DAC1Z30

r---c: xm

lV

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5.1.

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mur

:;-

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DMIILSlI
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D7

-

TB
T5
T4

~z

f--o

BDARD
SELECT

&.1.

DMI131
BUS CDUP

D=~tciiDER
0
I
Z
3

....... D
A3
AZ

AI

C

CD'

A

o~

SELEC~

L:~~B~ER
D3
DZ
Dl
DO

-

GI
A4
A3
AZ

AI
GND

DAC
BUS

04
01

B

TRANSFER

•

HI
CSZ
CS3

V4
Y3
VZ
VI

•

0

IV
~

r"'~~
5.1.

_
XFR3
XFRZ
XFRI
XFRD

r;:

CS!
'Dl

XFR3

WAf

~ WiIT

DAC1Z30

'DZ

r-Bi::IIIIIIDL

VCCrr5V

I

",~:O.I.F
TLlH/569D-14

FIGURE 8. TRI-5TATE® Buffers Isolate the Data and Control Lines from the DACs.
A Transfer Word Provides a Flexible Update.

3-115

N

~

....

~....
.....
C")

N
....

~

C;
C")

N
....

~

C;

....
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....

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.....
G)

CI
N

....

~
.....
CD
CI

N
....
o

<
c

r-------------------------------------------------------------------------~

Application Hints (Continued)
2.0 ANALOG APPLICATIONS
The analog output signal for these DACs is derived from a
conventional R-2R current switching ladder network. A detailed description of this network can be found on the
DAC1000 series data sheet. Basically, output IOUT1 provides a current directly proportional to the product of the
applied reference voltage and the digital input word. A second output, IOUT2 will be a current proportional to the com-,
plement of the digital input. Specifically:

The inverting input of the op amp is a virtual ground created
by the feedback from its output through the internal 15 kO
resistor, RFb. All of the output current (determined by the
digital input and the reference voltage) will flow through RFb
to the output of the amplifier. Two-quadrant operation can
be obtained by reversing the polarity of VREF' thus, causing
IOUT1 to flow into the DAC and be sourced from the output
of the amplifier. The output voltage, in either case, is always
equaltq IOUT1 x RFb and is the opposite polarity of the ref,erence voltage .
The reference can be either a stable DC voltage source or
an AC signal anywhere in the range from -10V to +10V.
The DAC can be thought of as a digitally controlled attenuator: the output voltage is always less than the applied reference voltage. The VREF terminal of the device presents a
nominal impedance of 15 kO to ground to external circuitry.
Always use the internal RFb resistor to create an output
voltage since this resistor matches (and tracks with temperature) the value of the resistors used to generate the output
current (IOUT1).
The selected op amp should have as low a valu~ of input
bias current as possible. The product of the bias current
times the feedback resistance creates an output voltage error which can be significant in low reference v91tage applications. BI-FETTM op a(T1ps are highly recommended for use
with these DAC~ because of their very low input current.

I
VREF
D
OUT1 = R
x 4096:
I
VREF
OUT2 = 'R

x

4095 - D
4096

where D is the deci,mal equivalent of the applied 12-bit bi~a­
ry word (ranging from 0 to 4095), VREF is the voltage applied to the VREF terminal and R is the internal resistance of
the R-2R ladder. R is nominally 15 kO .
2.1 Obtaining a Unipolar Output Voltage
To maintain linearity of output current with changes in the
applied digital code, it is important that the voltages at both
of the current output pins be as near ground, potential (0
Voc) as possible. With VREF= + 10V every millivolt appearing at either IOUT1 or IOUT2 will cause a 0.01 % linearity
error. In most applications this output curre,nt is converted to
a voltage by using an op amp as shown in Figure 9.

FULL-SCALE ADJUST

D

1&V

>~"'OVOUT

DAC1208

-15V
Tl.!H/5690-15

VoUT

~

-(IOUT1 x'RFbl

= -VREFlO)
4096
for 0 ,,;; '0 ,,;; 4095

FIGURE 9. Unipolar Output Configuration

3-116

c

»
o

Application Hints (Continued)
Transient response and settling time of the op amp are important in fast data throughput applications. The largest stability problem is the feedback pole created by the feedback
resistance, RFb, and the output capacitance of the DAC.
This appears from the op amp output to the (-) input and
includes the stray capacitance at this node. Addition of a
lead capacitance, Cc in Figure 9, greatly reduces overshoot
and ringing at the output for a step change in DAC output
current.

internal feedback resistor, RFb, matches the R-2R ladder
resistors. A negative gain error indicates that RFb is a smaller resistance value than it should be. To adjust this gain
error, some resistance must always be added in series with
RFb. The 50!} potentiometer shown is sufficient to adjust
the worst-case gain error for these devices.
2.2 Bipolar Output Voltage from a Fixed Reference.
The addition of a second op amp to the unipolar circuit can
generate a bipolar output voltage from a fixed reference
voltage. This, in effect, gives sign significance to the MSB of
the digital input word to allow two quadrant multiplication of
the reference voltage. The polarity of the reference can also
be reversed to realize full 4-quadrant multiplication. This circuit is shown in Figure 10.
This configuration features several improvements over existing circuits for a bipolar output shown with other multiplying DACs. Only the offset voltage of amplifier 1 affects the
linearity of the DAC. The offset voltage error of the second
op amp (although a constant output error) has no effect on
linearity. In addition, this configuration offers a non-interactive positive and negative full-scale calibration procedure.

2_1.1 Zero and Full-Scale Adjustments
For accurate conversions, the input offset voltage of the
output amplifier must always be nulled. Amplifier offset errors create an overall degradation of DAC linearity.
The fundamental purpose of zeroing is to make the voltage
appearing at the DAC outputs as near 0 Vae as possible.
This is accomplished by shorting out RFb, the amplifier feedback resistor, and adjusting the vas nulling potentiometer of
the op amp until the output reads zero volts. This is done, of
course, with an applied digital code of all zeros if IOUT1 is
driving the op amp (all ones for IOUT2). The short around
RFb is then removed and the converter is zero adjusted.
A unique feature of this series of DACs is that the fuli-scale
or gain error is guaranteed to be negative. The gain error
specification is a measure of how close the value of the

......

N

o(X)

......
c
»
o
......
N

o

CD
......

c
»
o......
N

......

o
......

c
»
o
......

N

W

o
......

c
»
o
......

N

W

......
......

~

o......
N

W

N

(+FULL·SCALE
ADJUST)

2R
10k

15V

±VREF

(-FULL-SCALE
ADJUST)

24
VCC

10
VREF

VDUT

D - 2048)TLlH/5690-16

VOUT~VREF ( ~

forO s D s 4095
1 LSB

Input Code
MSB •••••. LSB

IdealVOUT
+VREF

-VREF

111111111111

VREF -1 [SB

-IVREFI + 1 LSB

110000000000

VREF/2

-IVREFI/2

100000000000

0

0

011111111111

-1 LSB
- VREF _ 1 LSB
2
-VREF

+1 LSB
IVREFI + 1 LSB
2
+IVREFI

001111111111
000000000000

FIGURE 10. Bipolar Output Voltage Configuration

3-117

~

IVREFI
2048

•

N

Cf)

r-------------------------------------------------------------------------~

N

....

Application Hints (Continued)

....
~
....

To calibrate the bipolar output circuit, three adjustments are
required. The first step is to set all of the digital inputs LOW
(to force IOUT1 to 0) then null the Vos of amplifier 1 by
setting the voltage at its inverting input (pin 2no zero volts.
Next, with a code of all zeros still applied, adjust" -fullscale adjust", the reference voltage, for VOUT= ± IVREF ideall. The polarity of the output voltage at this time will be
opposite that of the applied reference. Finally, set all of the
digital inputs· HIGH and adjust "+ full-scale adjust" for
2047
VOUT = VREF 2048·

g
....
~

C;
Cf)

....
N

....~o

2.2.1 Zero and Full-scale Adjustments

....
N
....

The polarity of the output will be the same as that of the
reference voltage. .
3.0 APPLICATION IDEAS
In this section the digital input word is represented by the
letter 0 and is equal to the decimal equivalent of the 12-bit
binary input. Hence 0 can be any integer value between 0
and 4095.

Composite Amplifier for Good DC Characteristics and Fast Output Response

~

C

11

0;
o

16k

....
N

g

',DV

REFERENCE

;0

....~

• Combines the low Vas,

D,47.F

low YOS drift and low

~

..._H_-o-l&V

bias current of the
LMll with the fast
response of lhe LF351.

; ; . : . - - - - 6 - oVOUT

• Settling time'" 8 "S
for a zero to full·
scale transition

High Voltage, Power DAC
lk

...---o120V

r--~~-+JII..",.

VOUT

IDDVMAX
.'DDmA

I&V

-IDV
REFERENCE

-YREFD [
R2
R2]
YOUT=---- 1 + - + 4096
RFb R1

RI

.

Uk

TLIH/5690-17

3-118

c
~
o
....

Application Hints (Continued)

N

High Current Controller

o
co

....

5V~50V

~....
N

o

.....
CD

~....

OAC1Z3D

-IV
REFERENCE

N
....

RFb

9

o
.....

I
I

C

~
....

N
W

I

....o
~
....
........
....~

I

L __ ....:.

N
W

RSENSE

In

lOW

TL/H/5690-1B

N
W
N

8-Bit Course, 4-Bit Vernier DAC

CLOCK
CLOCK
ENABLE

15V

VOUT

I ~I'-:"

CS FROM
ADDRESS
DECODER
SYSTEM

Wii STROBE

TUH/5690-20

3-119

•

Ordering Information
Non-Linearity

Part Number

Package

Temperature
Range

DAC1208LCJ

0.018%

J24ACerdip

- 40·C to + 85·C

DAC1208LCJ-1

0.018%

J24ACerdip

O·Cto +70·C

J24ACerdip

- 40·C to + 85·C

J24ACerdip

- 40·C to + 85·C
O·Cto +70·C

DAC1209LCJ

0.024%

DAC1210LCJ

0.050%

DAC1210LCJ-1

0.050%

J24ACerdip

DAC1230LCJ

0.018%

J20ACerdip

- 40·C to + 85·C

DAC1230LCJ-1

0.018%

J20ACerdip

O·Cto +70·C

DAC1231LCJ

0.024%

J20ACerdip

-40·Cto +85·C

DAC1231 LCJ-1

0.024%

J20ACerdip

OOCto +70·C

.

'

DAC1231LCN

0.024%

N20A Plastic

O·Cto +700C

DAC1231 LCWM

0.024%

M20BSO

OOCto +700C

DAC1231LIN

0.024%

N20APIastic

-400Cto +85·C

DAC1232LCJ

0.050%

J20ACerdip

-400C to +85·C

DAC1232LCJ-1

0.050%

J20ACerdip

OOCto +700C

DAC1232LCN

0.050%

N20A Plastic

O·Cto +70·C

DAC1232LCWM

0.050%

M20BSO

OOCto +700C

DAC1232LIN

0.050%

N20A Plastic

-40·Cto +85·C

-

3-120

~

~
....
N
....
co

tflNational Semiconductor

......

~....

DAC1218/DAC1219
12=Bit Binary Mu!t!p!yang DI A Converter

....

N

CD

General Description
The DAC121B and the DAC1219 are 12-bit binary, 4-quadrant multiplying D to A converters. The linearity, differential
non-linearity and monotonicity specifications for these converters are all guaranteed over temperature. In addition,
these parameters are specified with standard zero and fullscale adjustment procedures as opposed to the impractical
best fit straight line guarantee.
This level of precision is achieved though the use of an
advanced silicon-chromium (SiCr) R-2R resistor ladder network. This type of thin-film resistor eliminates the parasitic
diode problems associated with diffused resistors and allows the applied reference voltage to range from - 25V to
25V, independent of the logic supply voltage.
CMOS current switches and drive circuitry are used to
achieve low power consumption (20 mW typical) and mini'
mize output leakage current errors (10 nA maximum).
'Unique digital input circuitry maintains TTL compatible input
threshold voltages over the full operating supply voltage
range.
The DAC121B and DAC1219 are direct replacements for
the AD7541 series, AD7521 series, and AD7531 series with
a significant improvement in the linearity specification. In
applications where direct interface of the D to A converter to

a microprocessor bus is desirable, the DAC120B and
DAC1230 series eliminate the need for additional interface
logic.

Features
II Linearity specified with zero and full-scale adjust only
II Logic inputs which meet TTL voltage level specs (1.4V

logic threshold)
± 1OV reference-full 4-quadrant
multiplication
II All parts guaranteed 12-bit monotonic
II Works with

Key Specifications
II Current Settling Time

1 p.s
12 Bits
12 Bits (DAC121 B)
11.Bits (DAC1219)
1.5 ppml"C'
20mW
5 Voc to 15 Voc

II Resolution
II Linearity (Guaranteed

over temperature)
II Gain Tempco
II Low Power Dissipation
II Single Power Supply

Typical Application

Connection Diagram

DIGITAL
INPUT

Dual-In-Llne Package

.

IOUTI

II

•

loun

VREF
1&

GND
ANALOG
DUTPUT

±lOV

I.

AIIMSII

14

A2
I~V

RFb

17

Vee
A12 (LSBI
All

A3

A4
15V
A.
TL/H/5691-1

10
A&

A7

TUH/5691-15

where: AN - 1 if digital input is high

TOp View

AN - 0 if digital input is low

Ordering Information
Package Outline

Temperature Range

O"Cto +70"C

- 40·C to + ,,5·C

I
I

DAC121 BLCJ-1

DAC121BLCJ

J1BA Cerdip

DAC1219LCJ

J1BACerdip

Non
Linearity

0.012%
0.024 %

3-121

.,...

~

~.....

Absolute Maximum Ratings (Notes 1 and 2)

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Temperature Range
DAC1218LCJ,DAC1219LCJ
DAC1218LCJ-1

.,...
o
ct
c

Supply Voltage (Vccl
Voltage at Any Digital Input

Range ofVcc
Voltage at Any Digital Input

.,...

IN

co
.,...

IN

17Voc
VcctoGND
±25V
-65·C to + 150·C

Voltage at VREF Input
Storage Temperature Range

Package Dissipation at TA = 25·C (Note 3)

TMIN s'TA s TMAX
-40·C s TA s +85·C
O·C s TA s 70·C
5 Voc to 16 Voc
VcctoGND

500mW
-100 mV to Vcc

DC Voltage Appli,ed to,IOUT1 or IOUT2
(Note 4)
Lead Temp. (Soldering, 10 seconds)
ESD Susceptibility (Note 11)

300·C
800V

Electrical Characteristics
VREF = 10.000 Voc;Vcc ~ 11.4 Voc to 15.75 Voc unless otherwise noted. Boldface limits apply from TMIN to TMAX (see
Note 9); all other limits TA = TJ = 25·C.
Conditions

Parameter

Notes

Resolution
Linearity Error
, (End Point Linearity)

Differential Non-Linearity

Zero and Full-Scal,e
Adjusted
DAC1218
DAC1219

4,5,9

Zero and Full-Scale
Adjusted
DAC1218
DAC1219

4,5,9

Monotonicity
Gain Error (Min)
Gain Error (Max)

Using Internal RFb,
VREF = ±10V, ±1V

Gain Error Tempco
Power Supply Rejection

All Digital Inputs High

Typ
(Note 10)

Tested
Limit
(Note 11)

Design
Limit
(Note 12)

Units

12

12

12

Bits

±0.O18
±0.024

±0.O18.
±0.024

±0.O18
±0.024

±0.O18
±0.024
12

12

12

5

-0.1

0.0

% ofFSR

5

-0.1

-0.2

% ofFSR

5

±1.3

5

±3.0

±6.0
±30

9

15

10

10

9

15

20

20

Output Feedthrough Error

VREF = 120 Vp-p, f = 100 kHz
All Data Inputs Low

6

3.0

Output Capacitance

All Data Inputs
High
All Data Inputs
Low

9

IoUT1
IOUT2

ppm of FSrC

kO
kO
mVp·p

200
70
70
200

pF
pF
pF
pF

2.0

2.5

mA

10
10

10
10

nA
nA

IOUT1
IOUT2
IOUT1
IOUT2

Supply Current Drain

Bits

ppm of FSRIV

(Min)

Output Leakage Current

% ofFSR
% ofFSR

4

(Max)

Reference Input Resistance

,%ofFSR
%ofFSR

7,9
All Data Inputs Low
All Data Inputs High

Digital Input Threshold

Low Threshold
High Threshold

9

0.8
2.2

0.8
2.2

Voc
Voc

Digital Input Currents

Digital Inputs  2.2V

9

-200
10

-200
10

lJAoc
,..Aoc

ts Current Settling Time

RL = 1000, Output Settled
to 0.01 %, All Digital Inputs
Switched Simultaneously

1

3-122

,..s

o

»

Electrical Characteristics Notes
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.

o
.....
N

.....

Q:)

.......

Note 2: All voltages are measured with respecllo GND, unless olherwise specified.
Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking.
Note 4: Both IOUT1 and IOUT2 must go to ground or the virtual ground of an operational amplifier. The linearity error is degraded by approximately Vas -:- VREF. For
example, if VREF= 10V then a 1 mV offset, Vos. on loun or IOUT2 will introduce an additional 0.01 % linearity error.

g

o
.....
N

Note 5: The unit FSR stands for full-scale range. Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a particular
VREF value to indicate the true performance of the part. The Linearity Error specification of the DAC1218 is 0.012% of FSA. This guarantees that after performing a
zero and full-scale adjustment, the plot of the 4096 analog voltage outputs will each be within 0.012% x VREF of a straight line which passes through zero and fullscale. The unit ppm of FSR (parts per million of full-scale range) and ppm of FS (parts per million of full-scale) are used for convenience to define specs of very
small percentage values, typical of higher accuracy converters. 1 ppm of FSR = VREF/1 06 is the conversion factor to provide an actual output voltage quantity. For
example, the gain error tempco spec of ±6 ppm of FSrC represents a worst-case full-scale gain error change with temperature from -40°C to +85°C of
±(6)(VREF/l06)(12S'C) or ±0.7S (10- 3) VREF which is ±0.07S% of VREF.
Note 6: To achieve Ihis low feedlhrough in Ihe 0 package, Ihe user musl ground Ihe melal lid. If Ihe lid is left floaling Ihe feedthrough is typically 6 mY.
Note 7: A 10 nA leakage currenl wilh RFb~20k and VREF~ 10V corresponds 10 a zero error of (lOX 10- 9 X20X 103)X 100% 10V or 0.002% of FS.
Note 8: Human body model, 100 pF discharged Ihrough I.S kn resislor.
Note 9: Tesled limil for -1 suffix parts applies only aI2S'C.
Note 10: Typicals are al2S'C and represenllhe most likely paramelric norm.
Note 11: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 12: Design limits are guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.

Typical Performance Characteristics
Digital Input Threshold
vs Temperature

Digital Input Threshold
vsVcc
2.4

~

I

2.0

i

~

1.6

TA. - 40,l

a:
:c

U

TA-25'C

13

I

0-

TA .'85'C

~

~

a
co

0.8

f--

I
I

0.4
0

5

0

-- f- f-

I--"

10

-35-15 5

15

25 45 65 85

TA - AMBIENT TEMPERATURE I'C)

VCC - SUPPLY VOLTAGE IV)

Gain and Linearity Error
Variation vs Supply Voltage

Gain and Linearity Error
Variation vs Temperature

§

0.01

&I

TA "'25°C

Vee -IS VDC

f-t--++-+-t", G~IN r- -

g 0.005 1-+-+-+---1-ho+='~l''''+-+~
.""' ....

::i

0

H;::;;;j:~...
:rI"'~A':":LlN;;;;E;;:AR;;;IT!;-Y-l

~ -0.005

1-+-...~~---1-I-+-+-+~

z

"5

-O.Oll-+-+-+---1-t-+-+-+~

-55 -35 -15

5

10

25 45 65 85 105 125

TA - AMBIENTTEMPERATURE I'C)

15

Vee -SUPPLY VOLTAGE IVUC)
TL/H/5691-2

3·123

~.-------------------------------------------~------~

---~«;
---N

N

~

Definition of Package Pinouts
(A1-A12): Digital Inputs. A12 is the least significant digital
input (lSB) and A 1 is the most significant digital input
(MSB).
IOUT1: DAC Current Output 1. IOUT1 is a maximum for a
digital input of all 1s, and is zero for a digital input of all Os.
loun: DAC Current Output 2. IOUT2 is ~ constant minus
IOUT1' or IOUT1 + IOUT2 = constant (for a fixed reference
voltage).

DAC transfer characteristic. It is measured after adjusting
for zero and full scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.
National's linearity test (a) and the best straight line test (b)
used by other suppliers are illustrated below. The best
straight line (b) requires a special zero and FS adjustment
for each part, ,which is almost impossible for the user to
, determine. The end point test uses a standard zero FS adjustment procedure and is a much more stringent test for
DAC linearity.
'

RFb: Feedback Resistor. The feedback resistor is provide~
on the IC chip for use as the shunt feedback resistor for the
externai op amp which is used to provide an output voltage
for the DAC. This on-chip resistor should always be used
(not an external resistor) since it matches the resistors in
the on-chip R-2R ladder and tracks these resistors over
temperature.

Power Supply Sensltn;lty: Power supply, sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.
Settling Time: Full-scale current settling time requires zero
to full-scale or full-scale to zero output change. Settling time
is ,the time required from' a code transition until the DAC
output reaches within ± 1/2 lSB of the final output value.

VREF: Reference Voltage Input. This input connects to an
external precision voltage source to the internal R-2R ladder. VREF can be selected over the range of 10V to -10V.
This is also the analog voltage input for a 4-quadrant multiplying DAC application.

Full-scale Error: Full-scale error is a measure of the output
error between an ideal DAC and ihe actual device output.
Ideally, for the DAC1218 full-scale is VREF-1 lSB. For
VREF= 10V
and
unipolar
operation,
VFULLSCALE=10.0000V-2.44 mV=9.9976V. Full-scale error is
adjustable to zero.
Differential Non-Linearity: The difference between any
two consecutive codes in the transfer curve from the theoretical 1 lSB is differential non-linearity.
Monotonic: If the output of a DAC increases for increasing
digital input code, then the DAC is monotonic. A 12-bit DAC
which is monotonic to 12 bits simply means that input increasing digital input codes will produce an increasing analog output.

Vee: Digital Supply Voltage. This is the power supply pin for
the part. Vcc can be from 5 Vee to 15 Vec. Operation is
optimum for 15 Vec.
GND: Ground. This is the ground for the circuit.

Definition of Terms
Resolution: Resolution is defined as the reciprocal of the
number of discrete steps in the DAC output. It is directly
related to the number of switches or bits within the DAC. For
example, the DAC1218 has 212 or 4096 steps and therefore
has 12-bit resolution.
Linearity Error: Linearity error in the maximum deviation
from a straight line passing through the endpoints of the

b) Shifting FS adjust to pass best straight line test

a) End point test after zero and FS adjust

TL/H/5691-3

3-124

c

l;
....

Application Hints
The DAC1218 and DAC1219 are pin-far-pin compatible with
the DAC1220 series but feature 12 and 11-bit linearity specifications. To preserve this degree of accuracy. care must
be taken in the selection and adjustments of the output amplifier and reference voltage. Careful PC board layout is important. with emphasis made on compactness of components to prevent inadvertent noise pickup and utilization of
single paint grounding and supply distribution.

co

To generate an output voltage and keep the potential at the
current output terminals at OV. an op amp current to voltage
converter is used. As shown in Figure 2. the current from
loun flows through the feedback resistor. forcing a proportional voltage at the amplifier output. The voltage at loun is
held at a virtual ground potential. The feedback resistor is
provided on the chip and should always be used as it
matches and tracks the R value of the R-2R ladder. The
output voltage is the opposite polarity of the applied reference voltage.

1.0 BASIC CIRCUIT DESCRIPTION
Figure 1 illustrates the R-2R current switching ladder network used in the DAC1218 and DAC1219. As a function of
the logic state of each digital input. the binarily weighted
current in each leg of the ladder is switched to either loun
or IOUT2' The voltage potential at IOUTl and IOUT2 must be
at zero volts to keep th~ current in each leg the same. independent of the switch state.

2.1 Amplifier Considerations
To maintain linearity of the output voltage with changing
digital input codes the input offset voltage of the amplifier
must be nulled. The resistance from loun to ground
(Rloun) varies non-linearly with the applied digital code
from a minimum of R with all ones applied to the input to
near 00 with an all zeros code. Any offset voltage between
the amplifier inputs appears at the output with a gain of

The switches operate with a small voltage drop across them
and can therefore conduct currents of either polarity. This
permits the reference to be positive or negative. thereby
allowing 4-quadrant multiplication by the digital input word.
The reference can be a stable DC source or a bipolar AC
signal within the range of ± 10V. for specified accuracy. with
an absolute maximum range of ± 25V. The reference can
also exceed the applied Vee of the DAC.

1+~.
Rloun
Since RloUTl varies with the input code. a~y offset will ~e­
grade output linearity. (See Note 4 of Electncal Charactenstics.)

The maximum output current from either IOUTl or IOUT2 is
equal to

If the desired amplifier does not have ollset balanCing pins
available (it could be part of a dual or quad package) the
nulling circuit of Figure 3 can be used. The voltage at the
non-inverting input will be set to - Vos initially to force the
inverting input to OV. The common technique of summing
current into the amplifier summing junction cannot be used
as it directly introduces a zero code output current error.

VREF(max) (4095)
R
4096'
where R is the reference input resistance (typically 15 k!l).
A high level on any digital input steers current to IOUTl and
a low level steers current to IOUT2.

ZR

GNU

r

IOUTZ

I
I

I
I
I

~

AI
(MSI)

I
I
I

&

A2

I
I
I

A

A3

I
I
I

~

A4

I
I

I
I
I

bAS

A6

b

I
I
I

b

Al

I
I

I
AI

A9

AID

All

A

AI!

(lS8)

RFEEDIACK

TLlH/5691-4

Nole: Switches shown in digital high state.

FIGURE 1. The R·2R Current Switching Ladder Network

3·125

....
....
C
I\)

2.0 CREATING A UNIPOLAR OUTPUT VOLTAGE
(A DIGITAL ATTENUATOR)

l;
....

....

I\)
(g

~

r--------------------------------------------------------------------,

IN

.....

g
.....

Application Hints (Continued)
FULL-SCALE
ADJUST
RFb
(INTERNAL) I.

CIO

.....
.....

IN

~

MSI

IIY

18

DACI211

VOUT ~ -VREF (

AI

A2

A3

"2 + 4" + B

YDUT

AI2 )

+ ... 4096

where: AN ~ I if digital input is high

-I5Y

TL/H/5691-5

AN ~ 0 if digital input is low

FIGURE 2. Unipolar Output Voltage

DACt2t.

TL/H/5691-6

FIGURE 3. Zeroing an Amplifier Which Does Not Have Balancing Provisions

2.3 Output Settling Time
The output voltage settling time for this circuit in response
to a change of the digital input code (a full-scale change is
the worst case) is a combination of the DAC's output current
settling characteristics and the settling characteristics of the
output amplifier. The amplifier settling is further degraded by
a feedback pole formed by the feedback resistance and the
DAC output capacitance (which varies with the digital code).
First order compensation for this pole is achieved by adding
a feedback zero with capacitor Cc shown in Figure 2.
In many applications output response time and settling is
just as important as accuracy. It can be difficult to find a
single op amp that combines excellent DC characteristics
(low Vos, Vos drift and bias current) with fast response and
settling time. BI-FET op amps offer a reasonable compromise of high speed and good DC characteristics: The circuit
of Figure 4 illustrates a composite amplifier connection that
combines the speed of a BI-FET LF351 with the excellent
DC input characteristics of the LM11. If output settling time
is not so critical, the LM11 can be used alone.
Figure 5 is a settling time test circuit for the complete voltage output DAC circuit. The circuit allows the settling time of
the DAC amplifier to be measured to a resolution of 1 mV
out of a zero to ± 1OV full-scale output change on an oscilloscope. Figure 6 summarizes the measured settling times
for several output amplifiers and feedback compensation
capacitors.

The selected amplifier should have as Iowan input bias
current as possible since input bias current contributes to
the current flowing through the feedback resistor. BI-FETTM
op amps such as the LF356 or LF351 or bipolar op amps
with super /3 input transistors like the LM11 or LM308A produce negligible errors.
2.2 Zero and Full-Scale Adjustments
The fundamental purpose is to make the output voltages as
near 0 VDC as possible. This is accomplished in the circuit
of Figure 2 by shorting out the amplifier feedback resistance, and adjusting the Vos nulling potentiometer of the op
amp until the output reads zero volts. This is done, of
course, with an applied digital input of all zeros if IOUT1 is
driving the op amp (all ones for IOUT2). The feedback short
is then removed and the converter is zero adjusted.
A unique characteristic of these DACs is that any full-scale
or gain error is always negative. This means that for a fulls~ale input code the output voltage, if not inherently correct,
Will always be less than what it should be. This ensures that
adding an appropriate resistance in series with the internal
feedback resistor, RFb, will always correct for any gain error.
The 500 potentiometer in Figure 2 is all that is needed to
adjust the worst case DAC gain error.
Conversion accuracy is only as good as the applied reference voltage, so providing a source that is stable over time
and temperature is important.

3-126

~....

Application Hints (Continued)

....
N

00
......

~
....
....
N

Cl:)

OAC1ZI.
0.1

>'-----o.......OVOUT

TL/H/5691-7

FIGURE 4. Composite Output Amplifier Connection

15V
PULSE GENERATOR
INPUT
IV-IV

19:H-....
±1DV

SETTLE
SIGNAL
OUT
(TOSCOPEI

Diodes are 1N4148

."1"'D.F

-IIV

TL/H/5691-8

FIGURE 5. DAC Settling Time Test Circuit

Amplifier

Cc

Settling Time to 0.01 %

LM11
LF351
LF351
Composite
LM11·LF351
LF356

20pF
15 pF
30pF

30 !Jos
8!Jos
5!Jos

20pF

8!Jos

15 pF

6!Jos

FIGURE 6. Some Measured Settling Times

3·127

•

~ r-------------------------------------------------------------------~

.....
.....

,C\I

~
.....
co
.....
C\I
.....

~

Application Hints (Continued)
where D is the decimal equivalent of the true binary input
word. This configuration inherently accepts a code (halfscale or D=2048) to provide OV out without requiring an
external % LSB offset as needed by other bipolar multiplying DAC circuits .
Only the offset voltage of amplifier A 1 need be nulled to
preserve linearity. The gain setting resistors around A2 must
match and track each other. A thin film, 4-resistor network
available from Beckman Instruments, Inc. (part no. 694-3R10K-D) is ideally suited for this application. Two of the four
resistors can be paralleled to form R and the other two can
be used separately as the resistors labeled 2R.
Operation is summarized in the table below:

3.0 OBTAINING A BIPOLAR OUTPUT VOLTAGE
FROM A FIXED REFERENCE
The addition of a second op amp to the circuit of Figure 2
can generate a bipolar output voltage from a fixed reference
voltage (Figure 7). This, in effect gives sign significance to
the MSB of the digital input word to allow two quadrant mul·
tiplication of the reference voltage. The polarity of the reference voltage can also be reversed to realize full 4-quadrant
multiplication.
The output responds in accordance to the following expression:
D - 2048)
Vo = VREF ( 2048
' 0 ,;; D ,;; 4095

Applied
DIgital Input
MSB

0
0
0

Decimal
Equivalent

LSB

0
1
0

0
0

1
0
0

1
0
0

1
0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0
1
0
0

0
0

0
0

0
0

0
0

0
0

0
0

4095
3072
' 2048
2047
1024
0

VOUT
+VREF

-VREF

VREF-1 LSB
VREF/2
0
-1 LSB
-VREF/2'
-VREF

- VREFI + 1 LSB
-IVREFI/2
0
+1 LSB
+IVREFI/2
+IVREFI

Where 1 LSB = IVREFI
2048

.FULL-SCALE
ADJUST
2R'

15V
tVREF
-FULL-SCALE
ADJUST

2R·
lDk

2R·
DACI21.

17
VREF

.>=....-oVOUT

GND

2&.

!

2R·
10k

ZERO
ADJUST

I&V

'0.1 % matching

TL/H/5691-9

FIGURE 7. Obtaining a BIpolar Output from a Fixed Reference

3-128

g
....
co
.......
g
o....
....
co
o....

Application Hints (Continued)
3.1 Zero and Full-Scale Adjustments

4.0 MISCELLANEOUS APPLICATION HINTS
The devices are CMOS products and reasonable care
should be exercised in handling them to prevent catastrophic failures due to electrostatic discharge.
During power-up supply voltage sequencing, the negative
supply of the output amplifier may appear first. This will typically cause the output of the op amp to bias near the negative supply potential. No harm is done to the DAC, however,
as the on-Chip 15 k!1 feedback resistor sufficiently limits the
current flow from IOUT1 when this lead is clamped to one
diode drop below ground.
As a general rule, any unused digital inputs should be tied
high or low as required by the application. As a troubleshooting aid, if any digital input is left floating, the DAC will
interpret that input as a logical 1 level ..

The three adjustments needed for this circuit are shown in
Figure 7. The first step is to set all of the digital inputs LOW
(to force IOUTt to 0) and then trim "zero adjust" for zero
volts at the inverting input (pin 2) of OA 1. Next, with a code
of all zeros still applied, adjust" - full-scale adjust", the reference voltage, for VOUT = ± I(ideal VREF)I. The sign of the
output voltage will be opposite that of the applied reference.
Finally, set all of the digital inputs HIGH and adjust" + fullscale adjust" for VOUT= VREF (511/512). The sign of the
output at this time will be the same as that of the reference
voltage. This + full-scale adjustment scheme takes into account the effects of the Vos of amplifier A2 (as long as this
offset is less than 0.1 % of VREF) and any gain errors due to
external resistor mismatch.

Additional Application Ideas
For the circuits shown, D represents the decimal equivalent of the binary digital input code. D ranges from 0 (for an all zeros
input code) to 4095 (for an all ones input code) and for any code can be determined from:
D = 204B(A1) + 1024(A2) + 512(A2) + ... 2(A11)
where AN = 1 if that input is high
AN = 0 if that input is low

+

1(A12)

DAC Controlled Amplifier
VIN

vee

1&

I&V

VREF 1"1",,7_ _ _-,

15V

>""",>--0

VOUT' -vIN(40aBI

o

TLlH/5691-10

3-129

I\)

I\)

Additional Application Ideas (Continued)
Offsetting the Zero Code Output Voltage

15Y

1& YCC

>-4I_OVOUT

R2
c· 2VREFR2
VZoroShift = Rl + R2
TLlH/5691-11

High Current Controller
6V-+6DV

I.V

-IY
REFERENCE

RFlo

1.

10UT1..,.I~---...=.f
2

I
I
I

o

= 1 Amp (D)
4096

I
IL __ _
RSENSE

10

lOW

TLlH/5691-12

Additional Application Ideas (Continued)
DAC Controlled Function Generator
15V

• C1 controls maximum frequency
• <0.5% sino wave THO over range
• Range 30 kHz maximum
• Uneatily-OAC lim~

o

I

• f - 4096 (4/3 RFb C)

SINE OUT

15V

'V
15k

ct-+1DVPK

25k

OFFSET
ADJUST

-15V

..--'II\f\r--.....'W'Ir-.......- -...-o

±7V

JL

SQUARE OUT

,IV

I.

lOUT. 1

Vee
OAe1Z1.

TUH/5691-13

Digitally Programmable Pulse-Width Generator
liV-r.

DV-.J

to

L
"

INITIALIZING

Uk

s~:~~o-"'1----""",'II\.....- - - - ,

&I

Uk

_I MI_
rn-'''-''\;-'

- 15V OC

-+-f
u!..I 11 II ~MAX
:
to t~ MIN
TUH/5691-14

PW ow C(7.5V) (0\088) (REbI
OIVREF

3-131

Section 4
Voltage References

•

Section 4 Contents
Voltage Reference Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . • • . . . . . . • . . . . . . . . . . .
LH0070 Series BCD Buffered Reference .•.....•...................•.•..............•.
LH0071 Series Precision Buffered Reference ..........•...............•....••...••...•
LM113/LM313 Reference Diode.......... .. .. . .....•................... ..... ........
LM129/LM329 Precision Reference..................................................
LM134/LM234/LM334 3-Terminal Adjustable Current Sources.... .•.. ....... .... .... ....
LM 136-2.5/ LM236-2.5/ LM336-2.5V Reference Diodes. . . . . . . • . . . . . . . . . . . . . . . . . . . . . • . . . .
LM136-5.0/LM236-5.0/LM336-5.0V Reference Diodes. . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . .
LM169/LM369 Precision Voltage References. ... ... ........... ..•. ....... ..........•..
LM185/LM285/LM385 Adjustable Micropower Voltage References.. . . . . .. . . . . . . . . . . . . .. .
LM 185-1.2/LM285-1.2/ LM385-1.2 Micropower Voltage Reference Diodes. . . . . . . . . . . . . . . . .
LM185-2.5/LM285-2.5/LM385-2.5 Micropower Voltage Reference Diodes. • . . . . . . . . . . . • . . .
LM199/LM299/LM399/LM3999 Precision References... ........... .............. ......
LM368-2.5 Precision Voltage Reference. . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . • . . . . • • .
LM368-5.0, LM368-10 Precision Voltage References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM4040 Precision Micropower Shunt Voltage Reference ................................
LM4041 Precision Micropower Shunt Voltage Reference ..•.....•.•.•.•....••........••.
LM4431 Micropower Shunt Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . .
LM9140 Precision Micropower Shunt Voltage Reference .........•.....•....•.........•.

4·2

4-3
4-8
4-8
4-12
4-15
.4-20
4-29
4-36
4-43
4-53
4-60
4-67
4-73
4-82
4-88
4-94
4-113
4-125
4-131

tfI National

~

s=

Semiconductor

CQ

CD

::u

!!.
CD
(i;
:::J
n

Voltage Reference Selection Guide

CD

(f)

CD

CD

n

Shunt Type
Reverse Breakdown
Voltage (VR)

O·

Device

Temperature
Drift

Operating
Voltage
Temp.
Tolerance
Range· Max, TA = 25'C ppml'C
(Max)

Over
Range

Output
Operating
Dynamic
Current Range, IR Impedance
(Typ)

1.2"
1.2'·
1.2··
1.2"
1.2'·

LM4041A-1.2
LM40418-1.2
LM4041 C-1.2
LM4041 0-1.2
LM4041 E-1.2

I
I
I
I
I

±0..1%
±0.2%
±0.5%
±1.0%
±2.0%

1.22
1.22
1.22
1.22

LM113-2
LM113-1
LM113
LM313

M
M
M
C

±1%
±2%
±5%
±5%

1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235

LM1858X-1.2
LM1858Y-1.2
LM185-1.2
LM285AX-1.2
LM285AY-1.2
LM285A-1.2
LM2858X-1.2
LM2858Y-1.2
LM285-1.2
LM385AX-1.2
LM385AY-1.2
LM385A-1.2
LM3858X-1.2
LM3858Y-1.2
LM3858-1.2
LM385-1.2

M
M
M
I
I
I
I
I
I
C
C
C
C
C
C
C

±1%
±1%
±1%
±0.32%
±0.32%
±0.32%
±1%
±1%
±1%
±0.32%
±0.32%
±0.32%
±1%
±1%
±1%
+2%, -2.4%

30
50
150
30
50
150
30
50
150
30
50
150
30
50
150
150

- 55'C to + 125'C
- 55'C to + 125'C
- 55'C to + 125'C
-40'Cto +85'C
-40'Cto +85'C
- 40'C to + 85'C
-40'Cto +85'C
- 40'C to + 85'C
- 40'C to + 85'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C

10 /LA to 20 mA
10 /LA to 20 mA
10 /LA to 20 mA
10 /LA to 20 mA
10 /LA to 20 mA
10 /LA to 20 mA
10 /LA to 20 mA
10/LAt020mA
10 /LA to 20 mA
10 /LA to 20 mA
10 /LA to 20 mA
10 /LA to 20 mA
15 /LA to 20 mA
15 /LA to 20 mA
15 /LA to 20 mA
15 /LA to 20 mA

1
1
1
0.2
0.2
0.2
1
1
1
0.2
0.2
0.2
1
1
1
1

1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)

LM1858
LM1858X
LM1858Y
LM2858X
LM2858Y
LM285
LM3858X
LM3!l58Y
LM385

M
M
M
I
I
I
C
C
C

±1%
±1%
±1%
±1%
±1%
±2%
±1%
±1%
±2%

150
30
50
30
50
150
30
50
150

- 55'C to + 125'C
- 55'C to + 125'C
- 55'C to + 125'C
- 40'C to + 85'C
- 40'C to + 85'C
- 40'C to + 85'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C

10 /LA to 20 mA
10 /LA to 20 mA
10 /LA to 20 mA
10 /LA to 20 mA
10 /LA to 20 mA
10 /LA to 20 mA
13 /LA to 20 mA
13 /LA to 20 mA
13 /LA to 20 mA

0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4

1.225V to 10V (Adj)
1.225V to 10V (Adj)

LM40410'AOJ
LM4041 C-ADJ

I
I

±0.5%
±1.0%

150
100

- 40'C to + 85'C
- 40'C to + 85'C

60 /LA to 12 mA
65 /LA to 12 mA

2.0
2.0

1.24 to 6.3 (Adj.)
1.24 to 6.3 (Adj.)
1.24 to 6.3 (Adj.)
1.24 to 8.3 (Adj.)
1.24 to 6.3 (Adj.)
1.24 to 6.3 (Adj.)

LM611AM
tLM611M
LM611AI
LM6111
LM611C
ttLM613AM

M
M
I
I
C
M

±0.6%
±0.6%
±0.6%
±2.0%
±2.0%
±0.8%

80
150
80
150
150
80

- 55'C to + 125'C
- 55'C to + 125'C
-40'Cto +85'C
-40'Cto +85'C
O'Cto +70'C
- 55'C to + 125'C

16 /LA to 10 mA
16 /LA to 10 mA
16 /LA to 10 mA
16 /LA to 10 mA
16 /LA to 10 mA
16/LAt010mA

0.2
0.2
0.2
0.2
0.2
0.2

100
100
100
150
150

- 40'C to
-40'Cto
-40'Cto
-40'Cto
-40'Cto

+ 85'C
+85'C
+85'C
+85'C
+85'C

100 (Typ) - 55'C to + 125'C
100 (Typ) - 55'C to + 125'C
100 (Typ) - 55'C to + 125'C
100 (Typ)
O'Cto +70'C

4-3

60
60
60
65
65

/LA to 12 mA
/LA to 12 mA
/LA to 12 mA
/LA to 12 mA
/LA to 12 mA

1.5 Max
1.5 Max
1.5 Max
2.0 Max
2.0 Max

500
500
500
500

/LA to 20 mA
/LA to 20 mA
/LA to 20 mA
/LA to 20 mA

1.0 Max
1.0 Max
1.0 Max
1.0 Max

:::J
G)
C

a:
CD

CP

"C

·s

"0

1.24 to 6.3
1.24 to 6.3
1.24 to 6.3
1.24 to 6.3
1.24 to 6.3
1.24 to 6.3
1.24 to 6.3
1.24 to 6.3
1.24 to 6.3

Output
Operating
Dynamic
Current Range, IR Impedance
(Typ)

ttLM613M
LM613AI
LM6131
LM613C
LM614AM
:j:LM614M
LM614AI
LM6141
LM614C

M
I
I
C
M
M
I
I
C

±2.0%
±0.6%
±2.0%
±2.0%
±0.6%
±2.0%
±0.6%
±2.0%
±2.0%

150
80
150
150
80
150
80
150
150

-55'C to + 125'C
-40'Cto + 85'C
-40'Cto +85'C
O'Cto +70'C
- 55'C to + 125'C
-55'C to + 125'C
-40'Cto + 85'C
-40'Cto +85'C
O'Cto +70'C

2.49
2.49
2.49
2.49
2.49
2.49

LM136A
LM136
LM236A
LM236
LM336
LM336B

M
M
I
I
C

±1%
±2%
±1%
±2%
±4%
±2%

72
72
72
72
54
54

-55'C to + 125'C
-55'C to + 125'C
- 25'C to + 85'C
- 25'C to + 85'C
O'Cto +70'C
O'Cto +70'C

400 ",A to
400 ",A to
400 ",A to
400 ",A to
400 ",A to
400 ",A to

2.5"
2.5"
2.5'*
2.5"
2.5*'
2.5"
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5

LM4040A-2.5
LM4040B-2.5
LM4040C-2.5
LM4040E-2.5
LM4431-2.5
LM9140BY-2.5
LM185BX-2.5
LM185BY-2.5
LM185B-2.5
LM285AX-2.5
LM285AY-2.5
LM285A-2.5
LM285BX'2.5
LM285BY-2.5
LM285-2.5
LM385AX-2.5
LM385AY:2.5
LM385A-2.5
LM385BX-2.5
LM385BY-2.5
LM385B-2.5
LM385-2.5

I
I
I
I
I
C
I.
M
M
M
I
I
I
I
I
I
C
C
C
C
C
C
C

±0.1%
±0.2%
±O.5%
±1.0%
±2.0%
±2.0%
±0.5%
±1.5%
±1.5%
±1.5%
±0.8%
±0.8%
±0.8%
±1.5%
±1.5%
±1.5%
±0.8%
±0.8%
±O.8%
±1.5%
±1.5%
±1.5%
.±3%

100
100
100
150
150
30 Typ.
25
30
50
150
30
50
150
30
50
150
30
50
150
30
50
150
150

-40'Cto + 85'C
-; 40'C to + 85'C
-40'Cto +85'C
-40'Cto +85'C
-40'Cto +85'C
O'C to. + 70'C
-40'Cto +85'C
- 55'C to + 125'C
- 55'C to + 125'C
- 55'C to + 125'C
-;40'C to + 85'C
-40'C to + 85'C
-40'Cto +85'C
-40'Cto +85'C
-40'C to + 85'C
-40'C to + 85'C
-40'C to + 85'C
-40'Cto + 85'C
-40'Cto + 85'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C

65 ",A to 15 mA
65 ",A to 15 mA
65 ",A to 15 mA
70 ",A to 15mA
70 ",A to 15 mA
100 ",A to 15 mA
60 ",A to 15 mA
20 ",A to 20 mA
20 ",A to 20 mA
20 ",A to 20 mA
20 ",A to 20 mA
20 ",A t020 mA
20 ",A to 20 mA
20 ",A to 20 mA
20 ",A to 20 mA
20 ",A to 20 mA
20 ",A to 20 mA
20 ",A to 20 mA
20 ",A to 20 mA
20 ",A to 20 mA
20 ",A to 20 mA
20 ",Ato20mA
20 ",A to 20 mA

0.8 Max
0.8 Max
0.8 Max
0.9 Max
1.1 Max
1.0
0.8 Max
1
1
1
0.2
0.2
0.2
1
1
1
0.2
0.2
0.2
1
1
1
1

4.1 '*
4.1*'
4.1*'
4.1

LM4040A-4.1
LM4040B-4.1
LM4040C-4.1
LM4040D-4.1
LM9140BY-4.1

I
I
I
I
I

±0.1%
±0.2%
±0.5%
±1.0%
±0.5%

100
100
100
150
25

-40'Cto
-40'Cto
-40'Cto
-40'Cto
-40'Cto

68 ",A to
68 ",A to
68 ",A to
73 ",A to
68 ",A to

1.0 Max
1.0 Max
1.0 Max
1.3 Max
1.0 Max

5.0
5.0
5.0
5.0
5.0
5.0
5.0"
5.0"
5.0"

LM136A
LM136
LM236A
LM236
LM336B
LM336
LM4040A-5.0
LM4040B-5.0
LM4040C-5.0.·

M
M
I
I
C
C
I
I
I

±1%
±2%
±1%
±2% .
±2%
±4%
±0.1%·
±0.2%
±0.5%

72
72
72
72
54
.54
100
100

-55'C to + 125'C
- 55'C to + 125'C
- 25'C to + 85'C
- 25'C to + 85'C
O'Cto +70'C
O'Cto +70'C
-40'C to +85'C
-40'C to +85'C
-40'Cto +85'C

4.1 ,.

(Adj.)
(Adj.)
(Adj.)
(Adj.)
(Adj.)
(Adj.)
(Adj.)
(Adj.)
(Adj.)

Temperature
Operating
Voltage
Drift
Temp.
Tolerance
Over
Range* Max, T A = 25'C ppml"C
. Range
(Max)

LM4040D~2.5

I

4-4

ioo

+85'C
+85'C
+ 85'C
+85'C
+85'C

16",Atol0mA
16",Atol0mA
16",Atol0mA
16 ",A to 10 mA
16",Atol0mA'
16",Atol0mA
16",Atol0mA
16 ",A to 10mA
16 ",A to 10 mA
10 mA
10 mA
10 mA
10 mA
10 mA
10 mA

15 mA
15 mA
15mA
15 mA
15 mA

400 ",A to 10 mA
400 ",A tc? 10 mA
400 ",A to 10mA
400 ",A to 10 mA
400 ",A to 10 mA
400 ",A to 10 mA
74 ",A to 15 mA
74 ",A to 15 mA
74 ",A to 15 mA

0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.4
0.4
0.4
0.4
0.4
0.4

1.0 Max
1.0 Max
1.0 Max
1.0 Max
1.4 Max
1.4 Max
1.1 Max
1.1 Max
1.1 Max

Shunt Type

~

(Continued)

Reverse Breakdown
Voltage (VR)

Device

Temperature
Operating
Voltage
Drift
Temp.
Tolerance
ppml'C
Over
Range' Max, T A = 2S'C
(Max)
Range

Output
Operating
Dynamic
Current Range, IR Impedance
(Typ)

5.0··
5.0
6.9
6.9
6.9
6.9
6.9
6.9
6.9

LM4040D·5.0
LM9140BY·S.O
LM129A
LM129B
LM129C
LM329A
LM329B
LM329C
LM329D

I
I
M
M
M
C
C
C
C

6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95

LM199A
LM199A·20.
LM199
LM299A
LM299A·20
LM299
LM399A
LM399A·50
LM399
LM3999

M
M
M
I
I
I
C
C
C
C

8.2"
8.2"
8.2"
8.2"

LM4040A·8.2
LM4040B·8.2
LM4040C·8.2
LM4040D·8.2

I
I
I
I

±0.1%
±0.2%
±0.5%
±1.0%

100
100
100
150

-40'Cto
-40'Cto
-40'Cto
- 40'C to

+85'C
+85'C
+85'C
+ 85'C

91 ,..A to
91 ,..A to
91 ,..Ato
96,..Ato

15 mA
15 mA
15 mA
15mA

1.5 Max
1.5 Max
1.5 Max
1.9 Max

10.0"
10.0"
10.0"
10.0"
10.0

LM4040A·10.0
LM4040B·10.0
LM4040C·10.0
LM4040D·10.0

I
I
I
I
I

±0.1%
±0.2%
±0.5%
±1.0%
±0.5%

100
100
100
150
25

-40'Cto
- 40'C to
- 40'C to
- 40'C to
- 40'C to

+85'C
+ 85'C
+ 85'C
+ 85'C
+ 85'C

100,..A to 15 mA
100,..A to 15 mA
100,..A to 15 mA
110,..At015mA
100 f£A to 15 mA

1.7 Max
1.7 Max
1.7 Max
2.3 Max
1.7 Max

.-

LM9140BY.l0~0

±1.0%
±0.5%
+3%,-2%
+3%,-2%
+3%,-2%
±5%
±5%
±5%
±5%

150
25
10
20
SO
50
50
20
100

-40'Cto +85'C
-40'Cto +8S'C
-S5'Cto + 125'C
-5S'C to + 125'C
-5S'Cto + 125'C
O'Cto +70~C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C

79,..At01SmA
74,..At01SmA
600,..A to 15 mA
600,..A to 15 mA
600,..A to 15 mA
600,..A to 15 mA
600,..A to 15 mA
600,..A to 15 mA
600,..A to 15 mA

±2%
0.5
-55'Cto + 125'C 500,..A to 10 mA
Same as LM199A with 20 ppm guaranteed long term drift.
±2%
1.0
- 55'C to + 125'C 500 ,..A to 10 mA
±2%
0.5
- 25'C to + 85'C .500,..At010mA
Same as LM299A with 20 ppm guaranteed long term drift.
±2%
1
-25'Cto +85'C 500,..A to 10 mA
±5%
1
O'Cto +70'C
500,..A to 10 mA
Same as LM399A with 50 ppm guaranteed long term drift.
±5%
500,..A to 10 mA
2
O'Cto +70'C
±5%
5
O'Cto +70'C
600,..A to 10 mA

1.5 Max
1.1 Max
0.6
0.6
0.6
0.8
0.8
0.8
0.8
0.5
0.5
0.5
0.5
0.5
0.5
0.6

'C (Commercial) = o'c to 70'C. I (Industrial) = -2S'C to +8S'C for the LM236 and LM299, I = -40"C to +8S'C for all others.
M (Military) = -SS'C to + 12S'C
"Available in SOT·23 Package.
tLM611 has on·board Op Amp.
ttLM613 has on·board Dual Op Amp and Dual Comparator.
*LM614 has on,board Quad Op Amp.

Current References
Output Current
Range
2,..Atol0mA
2,..A to 10 mA
2,..A to 10 mA
2,..A to 10 mA
2,..Atol0mA
2,..A to 10 mA
2,..Atol0mA

Device

LM134
LM134·3
LM134·6
LM234
LM234·3
LM234·6
LM334

Operating
Temperature
Range
-55'C to + 125'C
-S5'C to + 125'C
-55'C to + 125'C
-25'C to + 100'C
- 25'C to + 100'C
- 25'C to + 100'C
O'Cto +70'C

2,..A to 10,..A

10,..Ato 1 mA

1 mAtoSmA

Operating
Voltage
Range

±8%
N/A

±3%
±1%
±2%
±3%
±1%
±2%
±6%

±5%
N/A
N/A
±5
N/A
N/A
±8%

1Vt040V
lVt040V
1Vt040V
1Vt040V
1Vt040V
1Vt040V
1Vt040V

Set Current Error

N/A
±8%
N/A
N/A
±12%

'Set current changes linearly with temperature at a rate of O.33%I'C.

4·5

Set Current
Temperature
Dependence'
0.96Tto 0.104T
0.98Tto 0.1 02T
0.97Tto 0.1 03T
0.96T to 0.104T
0.98T to 0.1 02T
0.97T to 0.1 03T
0.96T to 0.1 04T

iif
ca
CD

::1:J

!!.
CD
CiJ
::::II
n
CD

en
CD

CD

n

O·
::::II

Q

c:

a:
CD

Series Type (Buffered Output)
Output·
Voltage

Device

Temperature
Oper.
Voltage
Drift
Temp.
Tolerance
ppml'C
Over
Range' Max, TA = 25·C
(Max)
Range

Load Reg.
ppm/mA

Operatl~g

Current
Range

Quiescent
Current
(mA)

0.2 (Adj) tLM10
0.2 (Adj) tLM108
0.2 (Adj) tLM10C

M
I
C

±2.5%
·±2.5%
±5.0%

20typ
20typ
30typ

- 55·C to + 125·C
- 25·C to + 85·C
O·Cto +700C

100
100
100

OmAto+lmA
OmAto +1 rnA
OmAto +1 mA

0.27
0.27
0.30

2.5
2.5

LM368Y-2.5
LM368-2.5

C
C

±0.2%
·±0.2%

20
30

O·Cto +700C
O·Cto +70·C

25
25

OmAto +10mA
OmAto +10mA

0.55
0.55

5.0
5.0

LM3688Y-5.0·
LM368-5.0

C
C

. ±0.1%
±0.1%

20
30

O·Cto +700C
O·Cto +700C

·10
10

-10mAto +10mA
-10 mA to +10 mA

0.35
0.35

10
10
10
10
10
10
10
10
10
10
10

LM1698
LM169
LH0070-2
LH0070-0
LH0070-1
LM3698
LM369
LM369C
LM368Y-l0
LM368-10
LM369D

M
M
M
M
M
C·
C
C
C
C
C

±0.05%
±0.05%
±0.05%
±0.1%
±0.1%
±0.05%
±0.05%
±0.05% .
±0.1%
±0.1%
±0.1%

3
5
8
40
20
3
5
10
20
30
30

- 55·C to + 125·C
- 55·C to + 125·C
- 25·C to + 25·C
-25·Cto +25·C
-25·Cto +25·C
O·Cto +70·C
O·Cto +70·C
O·Cto +700C
O·Cto +700C
O·Cto +70·C
O·Cto +70·C

8
8
60
60
60
8
8
8
10
10
8

-10mAto +10mA
-10mAto+l0rnA
Ot05mA
OmAt05mA
OmAt05mA
-10mAto +10mA
-10mA~0 +10mA
-10mAto +10mA
-10mAto +10mA
-10mAto +10mA
-10mAto +10mA

1.8
1.8
5
5
5
1.8
1.8
1.8
0.35
0.35
2

10.24
10.24
10.24

LH0071-2
LH0071-1
LH0071-0

M
M
M

±0.05%
±0.1%
±0.1%

8
20
40

-40·C to + 85·C
-40·C to + 85·C
- 25·C to + 25·C

60
60
60

OmAt05mA
OmAt05mA
OmAt05mA

5
5
5

"C (Commercial)

= O"C to 70"C, I (Industrial) =

-40"C to. + 5S'C, M (Military)

= - SS'C to

+ t 2S'C

tReference has on-board Op Amp.

Low Current Reference Diodes
Operating

Output
Voltage

Device

3.0
3.3
3.6
3.9

LM103-3.0
LM103-3.3
LM103-3.6
LM103-3.9

"M (Military)

=

Range'

Voltage
Tolerance
Max, TA = 25·C

M
M
M
M

±10%
±10%
±10%
±10%

Te~p.

Temperature
Drift
ppml'C
(Max)

Over
Range

-1700
-1500
-1400
-1300

-55·Cto
-55·Cto
- 55·C to
- 55·C to

-55'Cto +t2S'C

..

4-6

+
+
+
+

125·C
125·C
125·C
125·C

Operating
Current Range, I~

Output
Dynamic'
Impedance
(Typ)

10 "A to 10 mA
10 p.A to 10 mA
10 "A to 10 mA
10 "A to 10 mA

25
25
25
25

"Reference Grade" Voltage Regulators
Output
Voltage

Device

Operating
Temperature
Range

Output
Voltage
Output
Variation
Load Reg. Line Reg.
Quiescent
Current
Tolerance
Over Operating ppm/mA
Current
ppm/V
(Max)
Max. TA = 2S'C
Range

Adjustable:
LP2951
-55'C to + 150'C
1.235V to 30V LP2951AC -40'Cto + 125'C
-40'C to + 125'C
LP2951C

±O.S%
±0.5%
±1%

±0.5%
±0.5%
±1%

100
100
200

42
42
83

100mA
100mA
100 rnA

120 ",A
120 ",A
120 ",A

5V. 3.3V, 3.0V LP2950AC -40'Cto + 125'C
5V, 3.3V, 3.0V LP2950C
-40'Cto +125'C

±0.5%
±1%

±0.5%
±1%

100
200

42
83

100mA
100 rnA

120 ",A
120 ",A

5V, 3.3V, 3.0V LP2980A
5V, 3.3V, 3.0V LP2980

±0.5%
±1%

2.5%
3.5%

140
140

50 rnA
50 rnA

95 ",A
95 ",A

-25'Cto + 125'C
- 25'C to + 125'C

• Included In Output Variation Over Operating Range specification.

4-7

..

.....- r-------------------------------------------------------------------------------------,
Q
Q

::I:
....I

......
Q

8
::I:
....I

f}1National Semiconductor

LH0070 Series Precision BCD Buffered Reference
LH0071 Series Precision Binary Buffered Reference
General Description
The LH0070 and LH0071 are precision, three terminal, voltage references consisting of a temperature compensated
zener diode driven by a current regulator and a buffer amplifier. The devices provide an accurate reference that is virtually independent of input voltage, load current, temperature
and time. The LH0070 has a 10.000V nominal output to
provide equal step sizes in BCD applications. The LH0071
has a 10.240V nominal output to provide equal step sizes in
binary applications.
The output voltage is established by trimming Ultra-stable,
low temperature drift, thin film resistors under actual operating circuit conditions. The devices are shortcircuit proof in
both the current sourcing and Sinking directions.

them ideal choices as reference voltages in precision 0 to A
and A to 0 systems.

Features

The LH0070 and LH0071 series combine excellent long
term stability, ease of application, and low cost, making

• Accuracy output voltage
1OV ± 0.02%
LH0070
LH0071
10.24V ± 0.02%
11.4V to 40V
• Single supply operation
0.20
• Low output impedance
0.1 mVIV
• Excellent line regulation
20,...Vp-p
• Low zener noise
• a-lead TO-5 (pin compatible with the LM109)
• Short circuit proof
a mA
• Low standby current

Equivalent Schematic

Connection Diagram

~---O."

.3

TO-5 Metal Can Package
YOUT

.,
R.

BOTTOM VIEW

Tl/H/5550-7

Order Number LH0070-0H, LH0071-0H, LH0070-1H,
LH0071-1H, LH0070-2H or LH0071-2H
See NS Package Number H03B

3

•••

ICASEI

TL/H/5550-1

Typical Applications
Statistical Voltage Standard

'Output Voltage Fine Adjustment

.15Vo-.....- -....._ - - -....._ - - - - ,

+f5V

100
t-:------oVOUT

IDD
~_ _ _ _ _ _ _ _ __V'y.D~~-o~~~T

OPTIONAL

+

T

r-'W_...-W\'O---'W_-""O-15V
TL/H/5550-9

TL/H/5550-8

'Nole: The output of the LH0070 and LH0071 may be adiusted to a precise voltage by using the above cirCllit since the supply current of the devices is
relatively small and constant with temperature and input voltage. For the circuit shown. supply sensitivities are degraded slightly to 0.01 %IV change in VOUT
for changes in VIN and V -.

An additional temperature drift of 0.0001 %I"C is added due to the variation of supply current with temperature of the LH0070 and LH0071. Sensitivity to the
value of RI, R2 and R3 is less than 0.001 %1%.

4-8

r

:::c
Q

Absolute Maximum Ratings

Q

Short Circuit Duration
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temp. (Soldering. 10 seconds)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 4)
Supply Voltage
40V
Power Dissipation (See Curve)
SOOmW

Continuous
± 20mA
-55'Cto + 125'C
-S5'C to ± 150'C
300'C

Electrical Characteristics (Note 1)
Parameter

Conditions

Min

Output Voltage
LH0070
LH0071

TA=25'C

Output Accuracy
-0, -1
-2

TA=25'C

Output Accuracy
-0, -1
-2

TA= -55'C, 125'C

Output Voltage Change With
Temperature
-0
"
-1
-2

(Note 2)

Line Regulation
-0, -1
-2

13V:>:VIN:>:33V, Tc=25'C

±0.03
±0.02

RL = 50 k{}

Load Regulation

o mA:>: lOUT:>: 5 mA

Quiescent Current

' 13V:>:VIN:>:33V,IOUT=0 mA
I1VIN=20V From 23VTo 33V

Output Noise Voltage

BW=0.1 Hz To 10 Hz, TA=25'C
1";'120 Hz

Output Resistance

1

Units

V
V
±0.1
±0.05

%
%

±0.3
±0.2

%
%

±0.02
±0.01

±0.2
±0.1
±0.04

%
%
%

0.02
0.01

0.1
0.03

%
%

40

V

0.Q1

0.03

%

3

5

mA

0.75

1.5

mA

11.4

Ripple Rejection

Long Term Stability
-0,-1
-2

Max

10.000
10.24

Input Voltage Range

Change In Quiescent Current

Typ

20

/LVp-p

0.01

%lVp-p

0.2

O.S

{}

±0.2
±0.05

%/yr.
%/yr.

TA = 25'C (Note 3)

Thermal Resistance
Tj = 150'C
Dja (Junction to Ambient)
200
'C/W
Die (Junction to Case)
100
'C/W
Note 1: Unless otherwise specified, these specifications apply for VIN~IS.0V, RL ~ 10 kil, and over the temperature range of -SS'C,;TA'; + 12S'C.
Note 2: This specification is the difference In output voltage measured at TA~ 8S'C and TA~ 2S'C or TA~ 2S'C and TA~ - 25'C with readings taken after test
chamber and device-under-test stabilization at temperature using a suitable precision voltmeter.

Note 3: This parameter is guaranteed by design and not tested.
Note 4: Refer to the following RETS drawings for military specifications:
RETS0070·0H for LHOO70·0H
RETS0071-0H for LHOO71-0H
RETS0070·1 Hfor LH0070·1 H
RETS0071-1H for LH0071-1H
RETS0070-2H for LHOO70·2H
RETS0071·2H for LHOO71-2H

"

4-9

~
r

:::c
Q
Q

.....
-0.

~

8

r-------------------------------------------------------------------------------~--------~

Typical Performance Characteristics

3

~

§
3

7111

Quiescent Current vs Input
Voltage

Maximum Power Dissipation
II11'C
9JC' -w,TJ(MAXI"5rc

~

f- TA'-SS'C

~J A20rc
'--

'\.

'\..

"-

W

p-

'\

2i

50

75

100

"

125

~

TA-+25°C
-TA'+125'C

.>- .....

i.-'

I
150

5

10

15

20

25

30

..=
.ili
eg
.~

600

0

5 -600

r--r--r-....,--T""'""'T""..........,

0.2

I-+-+-t-+-+-t--l

~~
,,.. >

0.1

~~
~~ -0.1
-0.2 I-+-r-+--+-+-+--~

-8.3 L.......L...-L......I__J.......L..-L--I
-50 -25 a 25 50 75 100 125
CASE TEMPERATURE ("CI

Output Short Circuit
Characteristics
r--r~;-,,-~~~~

I LL

iJ'oo,

-600

w

..=.

35

12
500

~

INPUT VOLTAGE (VI

Step Load Response

!z

0.3
w

..IS

/

V

AMBIENT TEMPERATURE ('CI

Normalized Output Voltage
vs Temperature

CL '10pF

I I I
I I I

-

..,.
mAH+
CL' O.OI.F

DELTA CURRENT' 5
PULSE WIDTH' 2.,
2

10

3

TIME"'~

1&

20

25

30

OUTPUT CURRENT (mAl

TL/H/5550-2

Noise Voltage

10~V

VERT: 'jjjV,'

HORIZ:~
DIV.

BW·0.II1lT010Hz

TL/H/5550-6 .

Typical Applications (Continued)
Expanded Scale AC Voltmeter
INca04

ICD-IIDY PEAK

30k

47~

IW

NOMINAL
l1JVrms
AC LINE

Ik

10"F
2DDV

F-.......J\J..,.,~~o(,0DV CAl.
3k

TLIH/5550-4

4-10

r-

S

Typical Applications (Continued)

Q

~
r-

....

Dual Output Bench Power Supply
+--.---------~------------~-------------,

:::c

Q
Q

.....
....

r-"II\iIr"'---~'\I\,----l--+--';::"O:~:::T

I

.n

Precision Process Control Interface

....

1"""----------""""~-

----.I5V

4-Z01ll~

INPUT i

10

VOUT: IOV FORZDI'IA

""

DVFOR4mA

",-"-"-+---11.

10....
241..

24.3"

....

"'~--Yll'Ir--...~'I'v_---ZERO

'"

Boosted Reference For
Low Input Voltages

Negative 10V Reference

O--,...---1--o'12V
HUll
~-~-oVOUT

"'--oOVOUT

-IIV
TL/H/5550-5

4-11 .

....
C")

~
....
....

t!lNational Semiconductor

== LM113/LM313 Reference Diode

....I

General Description
The LMl13/LM313 are temperature compensated, low voltage reference diodes. They feature extremely-tight regulation over a wide range of operating currents in addition to an
unusually-low breakdown voltage and good temperature
stability.

• Dynamic impedance of 0.3n from 500 /LA to 20 mA
• Temperature stability typically 1% over-55'C to 125'C
range (LMl13), O'C to 70'C (LM313)
• Tight tolerance: ± 5%, ± 2% or ± 1%
The characteristics of this reference recommend it for use in
bias-regulation circuitry, in low-voltage power supplies or in
battery powered equipment. The fact that the breakdown
voltage is equal to a phYSical property of silicon-the energy-band gap vOltage-makes it useful for many temperature-compensation and temperature-measurement functions.

The diodes are synthesized using transistors and resistors
in a monolithic integrated circuit. As such,. they have the
same low noise and long term stability as modern IC op
amps. Further, output voltage of the reference depends only
on highly-predictable properties of components in the IC; so
they can be manufactured and supplied to tight tolerances.

Features
• Low breakdown voltage: 1.220V

Schematic and Connection Diagrams
Metal Can Package

"

UK

....

NOle: Pin 2 Cflnnected to case.

"

TOPVIEW

111

Order Number
LM113H, LM113H/883,
LM113-1H, LM113-1H/883,
LM113-2H, LM113-2H/883,
orLM313H
See NS Package Number H02A

.,

TL/H/5713-1

Typical Applications
Low Voltage Regulator
Level Detector for Photodlode

.,

""

2NZ9D5

TIL
OUTPUT

DI

lM313
IZV

~\M,+;';;':;---""'VOUT~2V
R3
n.3K

"

"
"

7.7K

tSolid tantalum.
TL/H/5713-2

4-12

riii:

........

Absolute Maximum Ratings
-6S'Cto +1S0'C

....r-

300'C

....

Co)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 3)
Power Dissipation (Note 1)
100mW
Reverse Current
SOmA

Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)

iii:
Co)
Co)

Operating Temperature Range
LM113
LM313

-SS'C to+ 12S'C
O'Cto +70'C

SOmA

Forward Current

Electrical Characteristics (Note 2)
Parameter

Conditions

Min

Typ

Max

Units

1.160
1.210
1.19S

1.220
1.22
1.22

1.280
1.232
1.24S

V
V
V

O.S rnA ,;; IR ,;; 20 rnA

6.0

1S

mV

IR = 1 rnA
IR=10mA

0.2
0.2S

1.0'
0.8

n
n

Forward Voltage Drop

IF = 1.0 rnA

0.67

1.0

V

RMS Noise Voltage

10Hz';; f ,;; 10kHz
IR = 1 rnA

Reverse Breakdown Voltage
Change with Current

O.SmA';; IR';; 10mA
TMIN ,;; TA';; TMAX

Breakdown Voltage Temperature
Coefficient

1.0 rnA ,;; IR ,;; 10 rnA
TMIN ,;; TA';; TMAX

Reverse Breakdown Voltage
LM113/LM313
LM113-1
LM113-2

IR = 1 rnA

Reverse Breakdown Voltage ,
Change
Reverse Dynamic Impedance

S

p.V
15

mV

0.01

'Yo/'C

Note 1: For operating at elevated temperatures, the device must be derated based on a t 50"C maximum junction and a thermal resistance of BO"C/W junction to
cass or 440°C/W junction to ambient.

Nole 2: These specifications apply for TA = 25"C, unless stated otherwise. At high currents, breakdown voltage should be measured with lead lengths less than Yo
inch. Kelvin contact sockets ar'1 also recommended. The diode should not be operated with shunt capacitances between 200 pF and 0.1 f'F, unless Isolated by at
least a loon resistor, as it may oscillate at some currents.
Note 3: Refer to the following RETS drawings for military specifications: RETSI13·1X for LMI13·1, RETSI13·2X for LM113·2 or RETS113X for LM113.

Typical Performance Characteristics
Temperature Drift
1.240 r-r-r-,.....,......,-.,--r-.,........,

Reverse Dynamic Impedance

ilL

~1230~~~+-+-+-+-4-4-~

10

....
...."'
......
..~

II

1111111

s:
oS 8

"'z

"'

~

Reverse Characteristics

Urrnnrr--r"Tn~~,

6

~

§: 1.220

~

=

1.210

",..._

~"~-r-r-+-+-+~~~

I-+-+-+-+-+-+-+-+--l

2

::>

1.200 '-'-'-'--.L-.L-.L-..L....L......
-55 -35 -15 5 25 45 65 85 105 12~

TEMPERATURE I"CI

4

!:;

0
-2
0.3

REVERSE CURRENT ImAI

1
10
REVERSE CURRENT (mAl

3D

TUH/5713-3

4-13

Typical Performance Characteristics (Continued)
Reverse Characteristics

Reverse Dynamic Impedance

10-'

Noise Voltage

100

~

Ik)1VJ ~CI

40 t+HItIIt-II+

25'C

10-'

0.2

0.4

0.&

a..

0.1

1.0

IA

1.2

100

10k

REVERSE VOLTAGE IVI

...~

Response Time
2.0

I

1.5
1.5

~

"

T"-55'C

. ; 1.0
~ 0.5

a

0.5

-

~

~=-

10k
lk
FREIIUENCY IH,I

30

lOOk

Maximum Shunt Capacitance

,~,

OurUT -

J
':'

I

0""'"

~

::>

~

1M

FREIIUENCY 1Hz)

Forward Characteristics

2.0

lOOk

30 ........................
10
100

:NP~T

T.·2S'C
ImlS'C

I

10

I
I

50

I
a

12

FORWARO CURRENT ImAI

1&

20

TIME 1.,1

10>

.10'
111"· 111"
CAPACITANCE IpFI

la'
TUH/5713-4

Typical Applications (Continued)
Amplifier Biasing for Constant Gain with Temperature
+15V

Constant Current Source'

OUTPUT

---11.

&........

Thermometer

HDK

n,

I'

,,,
• Adjust lor OV at O'C
tAdjust lor 100 mVl'C

,IK
-11Y

TUH/5713-5

4-14

r--------------------------------------------------------------------------------, ri!i:
....
~

tfINational Semiconductor

~

fi:

fii
CC)

LM 129/LM329 Precision Reference
General Description
The LM129 and LM329 family are precision multi-current
temperature-compensated 6.9V zener references with dynamic impedances a factor of 10 to 100 less than discrete
diodes. Constructed in a single silicon chip, the LM129 uses
active circuitry to buffer the internal zener allowing the device to operate over a 0.5 mA to 15 mA range with virtually
no change in performance. The LM129 and LM329 are
available with selected temperature coefficients of 0.001,
0.002, 0.005 and 0.01 %rc. These new references also
have excellent long term stability and low noise.
A new subsurface breakdown zener used in the LM129
gives lower noise and better long-term stability than conventional IC zeners. Further the zener and temperature compensating transistor are made by a planar process so they
are Immune to problems that plague ordinary zeners. For
example, there is virtually no voltage shift in zener voltage
due to temperature cycling and the device is insensitive to
stress on the leads.

simplifies biasing and the wide operating current allows the
replacement of many zener types.
The LM129 is packaged in a 2-lead TO-46 package and is
rated for operation over a - SS"C to + 12S"C temperature
range. The LM329 for operation over O"C to 70"C is available in both a hermetic TO-46 package and a TO-92 epoxy
package.

Features
•
•
•
•
•
•
•
•

0.6 mA to 15 mA operating current
0.6n dynamic impedance at any current
Available with temperature coefficienis of 0.001 %/oC
7p,V wideband noise
5% initial tolerance
0.002% long term stability
Low cost
Subsurface zener

The LM129 can be used in place of conventional zeners
with improved performance. The low dynamic impedance

Connection Diagrams
Metal Can Package (T0-46)

Plastic Package (TO-92)

TUH/5714-4

Bottom View
Order Number LM329BZ,
LM329CZ or LM329DZ
See NS Package Z03A

TL/H/5714-6

Bottom View
Pin 2 is electrically connected to case

Order Nu~ber LM129AH, LM129AH/883, LM129BH,
LM129BH/883, LM129CH, LM329AH, LM329BH,
LM329CH or LM329DH
See NS Package H02A

Typical Applications
Simple Reference
9VTO 4DV

AS

TUH/5714-1

4-15

•

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 2)
Reverse Breakdown Current
30mA
Forward Current
2mA
Operating Temperature Range
LM129
- 55·C to + 125·C
LM329
O·Cto +70·C

Storage Temperature Range
Soldering Information
TO·92 package: 10 sec.
TO·46 package: 10 sec.

-55·Cto
, +150"C
260·C
300·C

.Electrical Characteristics (Note 1)
Parameter

"

LM129A,B,C

LM329A, B, C, D

Min

Typ

Max

6.7

,6.9

Conditions

Units

Max

Min

Typ

7.2

6.6

6.9

7.25 '

V

14

9

20

mV

1

O.B

2

7

100

Reverse Breakdown Voltage

TA = 25°C,
0.6mA,;;: 'R';;: 15mA

Reverse Breakdown Change
with Current (Note 3)

TA = 25°C,
0.6 mA ,;;: IR ,;;: 15 mA

9

Reverse Dynami,c Impedance
(Note 3)

TA = 25°C, IR = 1 mA

0.6

RMS Noise

TA = 25·C,
10 Hz,;;: F,;;: 10 kHz

7

Long Term Stability
(1000 hours)

TA = 45°C ± 0.1°C,
IR = 1 mA ± 0.3%

20

Temperature Coefficient
LM129A, LM329A
LM129B, LM329B
LM129C, LM329C
LM329D

'R = 1 mA

Change In Reverse Breakdown
Temperature Coefficient

1 mA,;;: IR ,;;: 15 mA

1

1

ppml"C

Reverse Breakdown Change
with Current

1 mA,;;: IR ,;;: 15 mA

12

12

mV

'J

{1

"

6
15
30

20

20
10
20
50

6
15
30
50

' p.V
ppm

10
20
50
100

ppm/·C
ppml"C
ppm/oC
ppml"C

{1
Reverse Dynamic Impedance
1 mA,;;: IR ,;;: 15 mA
O.B
1
Note 1: These speCifications apply for -55'C ,. TA ,. + 125'C for the LM129 and O'C ,. TA ,. +70'C for the LM329 unless otherwise specified. The maximum
iunction temperature for an LM129 Is t50'C and LM329 Is t OO'C. For operating at elevated temperature, devices in T0-46 package must be derated based on a
thermal resistance of 44O'C/W junction to ambient or BO'C/W junction to case. For the T0-92 package, the derating Is based on lBO'CIW junction to ambient with
0.4' leads from a PC board and t60'C/W junction to ambient with 0.125' lead length to a PC board.
Note 2: Refer to RETS129H for LM129 family military specifications.
Note 3: These changes are tested on a pulsed basis with a low duty-<:ycle. For changes versus temperature, compute in terms of tempco.

4·16

Typical Applications (Continued)
Adjustable Bipolar Output Reference

Low Cost 0-2SV Regulator
VIN

H~--VOUT

35V

SDk

lSV

+ISV

OUTPUT

>~~--6.9 S; VOUT S; 6.9
LM129

50k>...--.....;~

6.9V

240

-lSV

LM329

JDpF

570

TUH/5714-8

150

-lOY

TL/H/5714-7

OV to 20V Power Reference
2SV TD4DV'-...- - - - - - - - - - -_ _ _ _ _..._ _ _ _ _ _ _.......

LM19Sk
LM129

20k ~~-'M_"'-'M\r'""+--t

B.9V

....--+--+-...JV'w~--~- OVTO
20V
lA
lk

-SV
TL/H/5714-9

External Reference for Temperature Transducer
15V

lk

}

LM1Z9
6.9V

OUTPUT
10mV/'K

LM3911H

INPUT

lN457

TUH/5714-2

4-17

Typical Applications

(Continued)
Positive Current Source

------1_-___. .

lDVT04DV'-....- -....

358
0.1%
2Dk
0.111

LM129

6.9V
2Dk

0.1%

4.:11<

TLlH/5714-11

Buffered Reference with Single Supply
.15V-....- - - - - - - - . . ,
9k

1.5k

>~~-10V

LM1Z9

6.9V

TLlH/5714-3

Schematic Diagram

D3
6.3V

30 pF

10k

2k

Uk

~------~--~--------~------------~--~2
4·18

-

TL/H/5714-10

Typical Performance Characteristics
Reverse Characteristics

Response Time

Forward Characteristics

10-' , - - , . - - , - - . , - - , - - , - - ,

1.2 , - - - , - - - , - - . . . , . . . - - ,

OUTPUT
310-'

~
3 10-

3

I---+-+-+--HH---j

JTj.15~C- /.../ I
r--

~
z

'"

f--

~

1---+-+-

UK

~

'"

~

~ 10~ f---+~+~T-~F---+---j

6.15

6.85

6.95

,.~

INPUT

tI,

f--

INPUT-

r--

.~w -i.-....:

20
10

1.05

100

REVERSE VOLTAGE IVI

200

300

~
'"

0.8

I----t---''t::;;-=-Jr-r--l

;

0.6

1---+--::::....""'---+-.,;.'-1

~
Ii!

OA

~

coo

0.01

TIME bois)

Dynamic Impedance

~

Reverse Voltage Change

Zener Noise Voltage

"i

.."

ISO

Tj' ~55'C

-

Tj z

1.0

>

~

/.

10

5

us·e / : r \

I

100

,.

oS 100

~25'C

-

",

I
10

~

~~

Tj· -5S'C

0.1

~

~25'CTi·125~

.=Tj"25'C

"

10

FORWARD CURRENT ImAI

100

..a"

1.01---!---1--+---..I

w

lk

FREQUENCY (Hz)

10k

o
lOOk

./
o

10

50
10

REVERSE CURRENT ImAI

100

1k

10k

lOOk

FREQUENCY 1Hz!

TUH/5714-12

Low Frequency Noise Voltage

0.01 Hz'S t-s; 1 Hz

10
TIME IMINUTESI

4·19

TUH/5714-5

III

IfINational Semiconductor

LM 134/LM234/LM334
3·Terminal Adjustable Current Sources
General Description
The LM134/LM234/LM334 are 3-terminal adjustable current sources featuring 10,000:1 range in operating current,
excellent current regulation and a wide dynamic voltage
range of 1V to 40V. Current is established with one external
resistor and no other parts are required. Initial current accuracy is ±3%. The LM134/LM234/LM334 are true floating
current sources with no separate power supply connections.
In addition, reverse applied voltages of up to 20V will draw
only a few dozen microamperes of current, allowing the devices to act as both a rectifier and current source in AC
applications.

LM234-3 and LM134-6/LM234-6 are specified as true temperature sensors with guaranteed initial accuracy of ± 3'C
and ± 6'G, respectively. These devices are ideal in remote
sense applications because series resistance in long wire
runs does not affect accuracy. In addition, only 2 wires are
required.
The LM134 is guaranteed over a temperature range of
- 55'C to + 125'C, the LM234 from - 25'G to + 100'C and
the LM334 from Q'G to + 70'G. These devices are available
in TO-46 hermetic, TO-92 and SO-8 plastic packages.

Features

The sense voltage used to establish operating current in the
LM134 is 64 mV at 25'C and is directly proportional to absolute temperature ('K). The simplest one external resistor
connection, then, generates a current with '" + 0.33%I'C
temperature dependence. Zero drift operation can be obtained by adding one extra resistor and a diode.
Applications for the current sources include bias networks,
surge protection, low power reference, ramp generation,
LED driver, and temperature sensing. The LM134-31

•
•
•
•
•
•

Operates from 1V to 40V
0.02%1V .current regulation
Programmable from 1 /LA to 10 mA
True 2-terminal operation
Available as fully specified temperature sensor
±3% initial accuracy

Connection Diagrams
so-a
Surface Mount Package

N{S

17 Is

·
0

so-a Alternative Pinout
Surface Mount Package

Y7

N{S

N{S

N{S

TO-46
Metal Can Package

ROO

f2

1_1

!lFPl4
R
yo
yo
y+

t3

14

TL/H/5697-24

Bottom View

Order Number LM334SM
See NS Package
Number MOaA

Order Number LM134H,
LM134H-3, LM134H-6,
LM234H or LM334H
See NS Package
Number H03H

Typical Application
Basic 2-Terminal Current Source
WIN

ISETIIV'"
R

CJ

i

....-

I

~-.!~..... VA

...... 1 V1..,-\

-VIN

RSET

.......
TL/H/5697 -1

4-20

R

V-

TL/H/5697 -10

v- Pin is electrically
connected to case.

TL/H/5697-25

Order Number LM334M
See NS Package
Number MOaA

v-

TL/H/5697-12

R'tNe

V"

o
v+

v+

Ys

TO-92
Plastic Package

Bottom View
Order Number LM334Z,
LM234Z-3 or LM234Z-6
See NS Package
NumberZ03A

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sal~s
Office/Distributors for availability and specifications.
V+ to V- Forward Voltage
LMI34/LM234/LM334
40V
LMI34-3/LMI34·6/LM234·3/LM234·6
30V
V+ to V- Reverse Voltage
20V
R Pin to V- Voltage
5V
Set Current
10mA
Power Dissipation
400mW
ESO Susceptibility (Note 5)
2000V

Operating Temperature Range (Note 4)
- 55·C to + 125·C
LMI34/LMI34·3/LMI34·6
- 25·C to + 100·C
LM234/LM234·3/LM234·6
O·Cto +70·C
LM334
Soldering Information
TO·92 Package (10 sec.)
2600C
TO·46 Package (10 sec.)
30Q·C
SO Package
215·C
Vapor Phase (60 sec.)
Infrared (15 sec.)
220·C
See AN·450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix 0) for other methods of
soldering surface mount devices.

Electrical Characteristics (Note 1)
Parameter

LM134/LM234

Conditions
Min

Set Current Error, V+ = 2.5V,
(Note 2)

10 /-LA!> ISET!> 1 mA
1 mA5 rnA
2 /-LA!>ISET<10 /-LA

Ratio of Set Current to
Bias Current

100/-LA!>ISET!>1 rnA
1 rnA!> ISET!> 5 rnA
2 /-LA!> ISET!> 100 /-LA

Minimum Operating Voltage

2 /-LA!>ISET!> 100 /-LA
100 /-LA < ISET!>1 mA
1 mA5 rnA

Average Change in Set Current
with Input Voltage

2/-LA!> ISET!> 1 mA
1.5!>V+ !>5V
5V!>V+ !>40V .
1 mA5 rnA
1.5V!>V!> 5V
5V!>V!>40V

Temperature Dependence of
Set Current (Note 3)

Typ

LM334
Max

Min

Typ

3
5
8
14

18
14
18

23

6
8
12
14

23

0.02

0.05
0.03

0.02
0.01

0.03
0.02
0.96T

25 /-LA!> ISET!> 1 mA

Effective Shunt Capacitance

T
15

18
14
18

26
V
V
V
0.1
0.05

0.03
0.02
1.04T

0.~6T

T
15

%
%
%

26

O.B
0.9
1.0

O.B
0.9
1.0

om

Units
Max

%IV
%IV
%IV
%IV

1.04T
pF

Note 1: Unless otherwise specified. tests are performed at TI=25'C with pulse testing so that junction temperature does not change during test.
Note 2: Set current is the current flowing into the V+ pin. For the Basic 2·Terminal Current Source circuit shown on the first page of this data sheet. ISET is
determined by the following formula: ISET=67.7 mV/RSET (@
@TI=25'C(227 p.VI"C).

25~C).

Set current error is expressed as a percent deviation from this amount. ISET increases at

0.336%I"C

Note 3: ISET is directly proportional to absolute temperature ("K). ISET at any temperature can be calculated from: ISET= 10 (TITol where 10 is ISET measured at To
("K).
Note 4: For elevated temperature operation, TI max is:
LM134
150"C
LM234
125'C
LM334
100"C
Thermal Resistance

TO·92

TO-46

SO·8

Oja: (Junction to Ambient)

180"C/W (0.4" leads)
160"C/W (0.125" leads)

440'C/W

165'C/W

N/A

3Z'C/W

80"C/W

Ole (Junction to Case)

Note 5: Human body model, 100 pF discharged through a 1.5 kO resistor.

4·21

•

Electrical Characteristics

(Note 1) (Continued)

Typ

Min
Set Current Error, V+ = 2.5V,
,
(Note 2)

Max

Min

Typ

±1

100 fLA,;;:ISET,;;:1 rnA

Units

Max

±2

%

±6

°C

Tj=2So

±3

Equivalent Temperature Error
Ratio of Set Current to
Bias Current

14

Minimum Operating Voltage

LM134~6, LM234-6

LM134-3, LM234-3

, Conditions

Parameter

'

Average Change in Set Current
with Input Voltage

18

26

100 fLA ISET::;;l rnA

0.9

100 fLA,;;:ISET,;;:1 rnA
1,5::;;V+::;;5V
5V::;;V+,;;:30V

0.02
0.01

0.05
0.03

T

1,02T

0.98T

Temperature Dependence of
Set Current (Note 3) and

14

18

26

v

0.9

0.97T

0.02
0.01

0.01
0.05

T

1.03T

±2

Equivalent Slope Error
Effective Shunt Capacitance

%/V
%/V

±3

pF

15

15

%

Typical Performance Characteristics
_. Maximum Slew Rate for
Linear Operation

Start-Up
10/'A HHr+-++-!I::::-'-+-+-1
I\,
;-200,.
o 1-f'-"f-t--+-+-1-'
Irl-+--1
IOU /'A H11\-li
\P-+_-++1--!15"-"0,.
.......+-+-1
0 ~f-"I''-+-I--+-iIH-+'-+-i

]i

IrnA Hh3I

100

10

lk

IrnA

10k

1DmA
TIME (Note scaI.i:hlngas It nch current level)

FREQUENCY (Hz)

Transient Response
1
0
-I

l

t;

*'

1\

-

IV

_2,.1

I "I

II

ISET-1mA

Y+TQY--5Y
AV-O.4V

1\ t';!.; 500"

5·
0
-5
10
0
-10

Voltage Across RSET (VR)

LJ L

~-fi

'SET-IOU/'A
-j 1 1

I.. L
I" 1
50,,!_

-

1\

1 1 1
'SET-'O/'A
I

I

I

TIME {Noll sui, chin.. for ••h cur,...,)

86
82

/

78
74
70

/'

/

66
62
58
54

Current Noise
10k

~...
ill

~

/
/'

50
46
-50 -25

III

Ik

-iSET-SmA
riSET - IrnA
100
riSEr - 100 /'A

=

10

I='SET-'O/'A

III
I
0 25 50 75 100 121
TEMPERATURE rC)

10

lk
10k
100
FREQUENCY (Hz)

lOOk

TLlH/5697-2

4-22

Typical Performance Characteristics

(Continued)

Turn-On Voltage

Ratio of ISET to IBIAS

18
0

~
II:

16

1/

V

14
12,

1~ ~~,~--~--~--~--~

OA

0.6

0.8

1.2

1.0

1A

10~

ImA

100~

Y+TOY-YOlTAGE

IOmA

IseT
TUH/5697-29

TL/H/5697 -3

The LM134 has been designed for ease of application, but a
general discussion of design features is presented here to
familiarize the designer with device characteristics which
may not be immediately obvious. These include the effects
of slewing, power dissipation, capacitance, noise, and contact resistance.

Since (for a given set current) IBIAS is simply a percentage
of ISET, the equation can be rewritten

Application Hints

ISET =

( _ n)
n-l
where n is the ratio of ISET to IBIAS as specified in the Elec·
trical Characteristics Section and shown in the graph. Since
n is typically 1S for 2 p.A :s; ISET :s; 1 rnA, the equation can
be further simplified to

CALCULATING RSET
The total current through the LM134 (I SET) is the sum of the
current going through the SET resistor (lR) and the LM134's
bias current (IBIAS), as shown in Figure 1.

ISET =

ify+

O.
CJ
V-

181AS~

+

t
!-

IR

~

RSET

THERMAL EFFECTS
Internal heating can have a significant effect on current regulation for ISET greater than 100 p.A. For example, each IV
increase across the LM134 at ISET = 1 mA will increase
junction temperature by z O.4°C in still air. Output current
(ISET) has a temperature coefficient of ZO.33%/OC, so the
change in current due to temperature rise will be
(0.4) (0.33) = 0.132%. This is a 10:1 degradation in regulation compared to true electrical effects. Thermal effects,
therefore, must be taken into account when DC regulation is
critical and ISET exceeds 100 p.A. Heat sinking of the T0-46
package or the TO-92 leads can reduce this effect by more
than 3:1.

TL/H/5697-27

FIGURE 1. Basic Current Source
A graph showing the ratio of these two currents is supplied
under Ratio of ISET to IBIAS in the Typical Performance
Characteristics section. The current flowing through RSET is
determined by VR, which is approximately 214 p.VI"K
(64 mV/29SoK - 214 p.VI"K).
ISET = IR

+ IBIAS =

VR
-RSET

(M59) = 227 p.VI"K
RSET

SLEW RATE
At slew rates above a given threshold (see curve), the
LM134 may exhibit non-linear current shifts. The slewing
rate at which this occurs is directly proportional to ISET. At
ISET = 10 p.A, maximum dV/dt is O.OIV/p.s; at ISET =
1 rnA, the limit is IV1p.s. Slew rates above the limit do not
harm the LM134, or cause large currents to flow.

R

vR

(~)

RSET
for most set currents.

+VIN
ISET

(~)
RSET

+ IBIAS

4-23

•

~
C')
C')

:E
....
....
~

C')

N

~

~

C')
,..

:E
....I

,---------------------------------------------------------------------------------,
Application Hints (Continued)
SHUNT CAPACITANCE

used to terminate the LM134. Slope error ,after trim will normally be less than ± 1%. To maintain this accuracy, however, a low temperature coefficient resistor must be used for
RSET·
A 33 ppm(OC drift of RSET will give a 1% slope error because the resistor will normally see about the same temperature variations as the LM 134. Separating RSET from the
LM134 requires 3 wires and has lead resistance problems,
so is not normally recommended. Metal film resistors with
less than 20 ppm/DC drift are readily available. Wire wound
resistors may also be used where best stability is required.

In certain applications, the 15 pF shunt capaCitance of the
LM134 may have to be reduced, either because of loading
problems or because it limits the AC output impedance of
the current source. This can be easily accomplished by buffering the LM134 with an FET as shown in the applications.
This can reduce capaCitance to less than 3 pF and improve
regulation by at least an order of magnitude. DC characteristics (with the exception of minimum input voltage), are not
affected.
NOISE

APPLICATION AS AZERO TEMPERATURE
COEFFICENT CURRENT SOURCE

Current noise generated by the LM134 is approximately 4
times the shot noise of a transistor. If the LM134 is used as
an active load for a transistor amplifier, input referred noise
will be increased by about 12 dB. In many cases, this is
acceptable and a single stage amplifier can be built with a
voltage gain exceeding 2000.

Adding a diode and a resistor to the standard LM134 configuration can cancel the temperature-dependent characteristic of the LM134. The,circuit shown in Figure 3 balances the
positive tempco of the LM134 (about +0.23 mVlOC) with
the negative tempco of a forward-biased silicon diode
(about -2.5 mV/oC).

LEAD RESISTANCE
The sense voltage which determines operating current of
the LM134 is less than 100 mY. At this level, thermocouple
or lead resistance effects should be minimized by locating
the current selling resistor physically close to the device.
Sockets should be avoided if possible. It takes only 0.70
contact resistance to reduce output current by 1 % at the
1 mA level.

v+ ~,ISET

C}
0'

SENSING TEMPERATURE
The LM134 makes an ideal remote temperature sensor because its current mode operation does not lose accuracy
over long wire runs. Output current is directly proportional to
absolute temperature in degrees Kelvin, according to the
following formula:

R

+

IBIAS~

11

1N457 ~

ISET = (227 ""VI"K) (T)
RSET
Calibration of ,the LM134 is greatly simplified because of the
fact that most of the initial inaccuracy is due to a gain term
(slope error) and not an offset. This means that a calibration
consisting of a gain adjustment only will trim both slope and
zero at the same time., In addition, gain adjustment is a one
pOint trim because the output of the LM134 extrapolates to
zero at OOK, independent of RSET or any initial inaccuracy.

t
JVR

y-

r"-

-

R1

R2

+

t

vo

~

12

~ ISET
TLlH/5697 -28

FIGURE 3. Zero Tempco Current Source
The set current (lSET) is the'sum of 11 and 12, each contributing approximately 50% of the set current, and IBIAS. IBIAS is
usually included in the I, term by increasing the VR value
used for calculations by 5.9%. (See CALCULATING RSET.)
ISET = I, + 12 + IBIAS, where
I, = VR and
, , R,'

12

= VR +

R2

Vo

The first step is to minimize the tempco of the Circuit, using
the following equations. An example is given using a value
of +227 ""VloC as the tempco of the LM134 (which in~
cludes the IBIAS component), and - 2.5 mVI"C as the tempco of the diode (for best results, this value should be directly
measured or obtained from the manufacturer of the diode).

TLlH/5697 -4

FIGURE 2. Gain Adjustment

ISET = I, + 12

This property of the LM134 is illustrated in the accompanying graph. Line abc is the sensor current before trimming.
Line a'b'c' is the desired output. A gain trim done at T2 will
move the output from b to b' and will simultaneously correct
the slope so that the output at T1 and T3 will be correct.
This gain trim can be done on RSET or on the load resistor

dlSET

""'dT"'" =

dl,
dl2
dT + dT

;:::: 227 ""VI"C + 227 ""vioc - 2.5 mVI"C
R,
= 0 (solve for tempco = 0)

4-24

R2

.-----------------------------------------------------------------------------, r
3:

...

Application Hints (Continued)

Co)

R2 _ 2.5 mVI'C - 227 ",VI'C _
Rl 227 ",VI'C
- 10.0

The values of Rl and R2 can be changed to standard 1 %
resistor values (Rl = 1330 and R2 = 1.33 kO) with less
than a 0.75% error.
If the forward voltage drop of the diode was 0.65V instead
of the estimate of 0.6V (an error of 8%), the actual set current will be

With the Rl to R2 ratio determined, values for Rl and 'R2
should be determined to give the desired set current. The
formula for calculating the set current at T = 25'C is shown
below, followed by an example that assumes the forward
voltage drop across the diode (Vo) is 0.6V, the voltage
across Rl is 67.7 mV (64 mV + 5.9% to account for'IBIAS),
and R2/Rl = 10 (from the previous calculations).

+ ----::-R2---

67.7 mV
= -1-33--

67.7 mV + 0.65V
+ -~-:-13:c3:-::0-c--

+ 12 + IBIAS
VR + VR + Vo

ISET = 11
=

I

If the estimate for the tempco of the diode's forward voltage
drop was off, the tempco cancellation is still reasonablyeffective. Assume the tempco of the diode is 2.6 mV/'C instead of 2.5 mVI'C (an error of 4%). The tempco of the
circuit is now:

10.0 Rl

SET-~

This circuit will eliminate most of the LM134's temperature
coefficient, and it does a good job even if the estimates of
the diode's characteristics are not accurate (as the following
example will show). For lowest tempco with a specific diode
at the desired ISET, however, the circuit should be built and
tested over temperature. If the measured tempco of ISET is
positive, R2 should be reduced. If the resulting tempco is
negative, R2 should be increased. The recommended diode
for use in this circuit is the 1N457 because its tempco is
centered at 11 times the tempco of the LM134, allowing R2
= 10 Rl. You can also use this circuit to create a current
source with non-zero tempcos by setting the tempco component of the tempco equation to the desired value instead
of D.

dlsET = dll
dT
dT

+ dl2
dT

= 227 ",VI'C
1330
=

+ 227 ",VI'C -

2.6 mVI'C
13300

-77nA/'C

A 1 rnA LM 134 current source with no temperature compensation would have a set resistor of 6BO and a resulting
tempco of
227 ",VI'C= 3.3 ",AI'e
680
So even if the diode's tempco varies as much as ± 4 % from
its estimated value, the circuit still eliminates 98% of the
LM134's inherent tempco.

EXAMPLE: A 1 rnA, Zero-Tempco Current Source
First, solve for Rl and R2:
0.134V
ISET ;:: 1 rnA = - - - Rl
Rl = 1340 = 10 R2
R2 = 13400

Typical Applications
Ground Referred Fahrenheit Thermometer

Terminating Remote Sensor for Voltage Output

R4
56k

+VIN

r-JV""--+---------

+VIN ~3V

l-oooo4I~------- VOUT" 10 mVrF
10'F~T~25D'F

r

LM336Z
2.5V*

RL

-

TL/H/5697-15

'Select R3 = VREF/583 y.A. VREF may be any stable pOsitive voltage ,,2V
Trim R3 to calibrate

4-25

~

......
""
r

3:
Co)
Co)

an error of less than 5%.

+ 0.6V
;:: - - + -'-'-'-'--':''=-=--'-'-':'';''

r
3:

""

= 1.049 rnA

Rl
R2
67.7 mV
67.7 mV

Rl
_ 0.134V

67.7 mV

+ 0.65V

67.7 mV
I
SET = -R-l--

......
""

VOUT' (lSET)(RL)

- 10mvrKFDR
RSET-non
RL '10kn

TL/H/5697-14

Typical Applications (Continued)
Low Output Impedance Thermometer
VIN~4.8V

R3*

)CI1(4o~~~...."V6D\lD""",_ VOUT"10 mVfK
ZOUTS 10DlJ

'Output Impedance of the LM134 at the "R" pin is
-R2
approximately 16 where R2 is the equivalent
external resistance connected from the V- pin to

ground. This negative rasistance can be raduced
by a factor of 5 or mora by inserting an equivalent
resistor R3 ~ (R2/16) In series with the output.
TL/H/5697 -6

Low Output Impedance Thermometer

Higher Output Current
+VIN

+VIN
RZ
300
Rl~

Cl
0.0022

)a'"'....--~.....- Vour = 10 mVfK
ZourSzn

R

R3

110
RSEl

TL/H/5697-S

'Select Rl and Cl for optimum stability

TL/H/5697-16

Mlcropower Bias
+VIN

Low Input Voltage Reference Driver
+VIN ~ VREF + 200 mV - - . - - - - - -.....

Vour· Vz + 84 mV. zS'e
IOUTs3mA
01
LM1Z8
LM138
. LM113
ETE.

HZ

120
-VIN
TL/H/5697-17
TLlH/5S97-18

4-26

Typical Applications (Continued)
Ramp Generator
+VIN

. .- - -....--VOUT

RESETJL

TLlH/5697-19

1.2V Regulator with 1.8V Minimum Input

1.2V Reference Operates on 10 /LA and 2V
+VIN"=ZV

VIN"= I.BV

R3
3.6k

R

)CI*-f';;"""'o4I~-'V\""'-- VOUT-I.ZV

RZ*

lOUT SlpA

....I+J'IAI...--"'-VOUT

RX

TLiH/5715-16

4-33

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

i

~
....

Typical Applications (Continued)
Op Amp with Output Clamped

Bipolar Output Reference
5V

RF

U)

~
N

~
~

2k

~

'2V -W\r-...- i



-

10
0

-

5

OUTPUT

... r:-II

r---,r---r--,.-...,...-...,

10-1

TJ"Zi~C

II
I IINPUT I I
I I
J

>
~ ,10.... 1---i-~..!iiIIf""--+--,+---l

1.1

TIME",,)

Temperature Drift
5.110

5180

:>

;; 5.040
CD

..
i

~ 5.000

~

",

.,

~ 4.920
,

,.

4.110

1.2

....

4.960

IR"'1mA

.j I

r-

.
....,.~
;

-.... .... ....
t-

a

1.0

CD

D.B

>

D.B

,.

D.4

f

~

4.140
-55 -35 -15

3.5

4.5

5.5

Forward Characteristics

-

.,

Z.5

, REVERSE VOLTAGE IV)

'-,---,.---,r---.

D.2

D

5 25 45 65 85 105 125

0.001

1.11

D.l

10

FORWARG CURRENT ImAi

TEMPERATURE I'C)

TL/H/5716-B

Application Hints
The LM136-5.0 series voltage references are much easier
to use than ordinary zener diodes. Their low impedance and
wide operating current range simplify' biasing in almost any
circuit. Further, either the, breakdown voltage or the temper- ,
ature coefficient can be adjusted to optimize circuit performance.
Figure 1 shows an LM136-5.0 with a 10k potentiometer for
adjusting the reverse breakdown voltage. With the addition
of R1 the breakdown voltage can be adjusted without affecting the temperature coefficient of the device. The adjustment range is usually sufficient to adjust for both the
initial device tolerance and inaccuracies in buffer circuitry.

4-38

If minimum temperature coefficient is desired, four diodes
can be added in series with the adjustment potentiometer
as shown in Figure 2. When the device is adjusted to 5.00V
the temperature coefficient is minimized. Almost any silicon
Signal diode can be used for this purpose such as a 1N914,
1N4148 or a 1N457. For proper temperature compensation
the diodes should be in the same thermal environment as
the LM136-5.0. It is usually sufficient to mount the diodes
near the LM136-5.0 on the printed circuit board. The absolute resistance of the network Is not critical and any value
from 2k to 20k will work. Because of the wide adjustment
range, fixed resistors should be connected in series with the
pot to make pot selting less critical.

r-

iii:
....

Application Hints (Continued)

Co)

en

U.
C
......
r-

iii:
N

Co)

en
I

en

~

Rl
LMI36·5.0 . - -..., 10k

r-

iii:
Co)

.

Co)

en

-

en
C

TL/H/5716-9

FIGURE 1. LM136-5.0 with Pot for Adjustment of
Breakdown Voltage (Trim Range = ± 1.0V Typical)

v+
I rnAJ.

RS

lN914

...._ _...~Rl
LMI36·5.0 ..
2k
5k

IN914

_

TL/H/5716-10

FIGURE 2. Temperature Coefficient Adjustment
(Trim Range = ± O.5V Typical)

Typical Applications

(Continued)

Precision Power Regulator with Low Temperature Coefficient
LM3t7

VIN

INPUT

....-~~-----~~-VOUT

Rl
626

'Adjust for 6.25V across At

4-39

TLlH/5716-11

Typical Applications (Continued)
5VCrowbar
V+ - - -.....- - -....- - -

LM331·&,O

SENSITIVE GATE

100

StR

200

TL/H/5716-12

Adjustable Shunt Regulator
VIN>ZV+VOUT _'VIR,.,s_

...- - - -...- - - - - - - , . . . .

~~r;~~ov

TLlH/5716-13

'Linear Ohmmeter

v>
LM334

5k
1%

>--+-VOUT

RX

TUH/5716-14

4-40

Typical Applications

r3:
......

(Continued)

w

Op Amp with Output Clamped

·

en
en
(:)
.......
r3:
I\)
w
en
en
(:)
.......
r3:
w
w
en
en

Bipolar Output Reference
5V

·

5k

2k

'2V

·

-'W'v-.---I
±2.5V

(:)

5k
-5V

5.0V Square Wave Calibrator

10V Buffered Reference
12V$V,N $36V --<)-------,
2Dk
1%

10V

2k

JIJ~--"""--""""P-- OUTPUT
lDV
4Ii<--KCALIBRATE
LMI36·5.0
10k

CAL

Wide Input Range Reference

Low Noise Buffered Reference
1.SV

LM334

5V

......-+--VOUT·5.DV

10k
CAL

TLlH/5716-6

4·41

LM136-S.0/LM236-S.0/LM336-S.0

en
n
:::r

CD

3
c;.

I»

+
25k

C

RI
5Dk

ADJ
50k

S·
CQ

iii
3

R5
24k

08

25k

C2
20 pF

R4
10k

CI
30pF

~
Q2

RIO
Uk

TL/H/5716-16

tfI

Nat ion a I Se m i con due t o,r

tM169/LM369 Precision Voltage Reference
General Description

Features

The LM169/LM369 are precision monolithic temperaturecompensated voltage references. They are based on a buried zener reference as pioneered in the LM199 references.
but do not require any heater. as they rely on special temperature-compensation techniques (Patent Pending). The
LM169 makes use of thin-film technology enhanced by the
disprete laser trimming of resistors to achieve excellent
Temperature coefficient (Tempco) of Vout (as low as 1
ppm/·C). along with tight initial tolerances (as low as 0.05%
max). The trim scheme is such that individual resistors are
cut 'open rather than being trimmed (partially cut). to avoid
resistor drift caused by electro migration in the trimmed area.
The LM169 also provides excellent stability vs. changes in
Input voltage and output current (both sourcing and sinking).
The devices have a 10.000V output and will operate in either series or shunt mode; the output is short-circuit-proof to
ground. A trim pin is available which permits fine-trimming of
Vout. and also permits filtering to greatly decrease the output noise by adding a small capacitor (0.05 to 0.5 tJoF).

•
•
•
•
•
•
•
•

3 ppml"C
Low Tempco
±5 mV
Excellent initial accuracy
4 ppmlV
Excellent line regulation
±o.a,n
Excellent output impedance
Excellent thermal regulation ±20 ppm/100 mW
Low noise
Easy to filter output noise
Operates in series or shunt mode

(max)
(max)
(max)
(max)
(max)

Applications
•
•
•
•
•

High-Resolution Data Acquisition Systems
Digital volt meters
Weighing systems
Precision current sources
Test Equipment

Connection Diagrams
Metal Can Package (H)

Dual·ln·Llne Package (N)
or S.O. Package (M)

·o's.

*

+VIN

2

•

3

7·
6

GROUND

4

5

,

VOUT

'

FILTER AND

TRIt.4 PIN
TL/H/9110-5

Top View
Order Number LM369DM, LM369DMX,·· LM369N,
LM369BN, LM369CN or LM369DN
See NS Package Number M08A or N08E

GROUND
TL/H/9110-1

Top View
(Case is connected to ground.)

"X denotes 2500 units on Tape and Reel and is not included in the device
part number marking

·00 not connect; internal connection for factory trims.

To-226 Plastic Package (RC)

V..,.8 "'"NO

Order Number LM169H, LM169BH,
LM169H/883, LM369H or LM369BH
See NS Package Number H08C

+VIN

Bottom View
Order Number LM369DRC
See NS Package Number RC03A

4-43

TL/H/9110-28

Absolute Maximum Ratings

(Note 8)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Input Voltage (Series Mode)
35V
Reverse Current (Shunt Mode)
Power Dissipation (Note 7)

50mA
600mW

Storage Temperature Range
Operating Temperature Range
LM169H,LM169H/883
LM369

-60'C to + 150'C
(Tj min to Tj max)
-55'C to + 125'C
O'Cto +70'C

Soldering Information
DIP (N) or Plastic (RC) Package, 10 sec.
+ 260"C
H08 (H) Package, 10 sec.
+300'C
SO (M) Package, Vapor Phase (60 sec.)
+215'C
Infrared (15 sec.)
+ 220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.
ESD Tolerance
800V
C,ap = 100 pF, Rzap = 1.5k

Electrical Characteristics, LM169, LM369
Parameter

Conditions

Vaut Nominal

Typical

(Note 1)
Tested
Limits
(Notes 2, 13)

Design
Limit
(Note 3)

+10.000

Units
(Max
Unless
Noted)
V

Vaut Error

(Note 11)

50
0.50

±500
±5

Vaut Tempco
LM169B. LM369B
LM169, LM369
LM369C
(Note 6) (Note 11)

Tmin 0=

51

52

FREQUENCY
SELECTOR

AMPLIl\JDE
SELECTOR

(1101Hz, 976Hz)

(10V,10mV)

1oI1oI74HC04

TL/H/9110-22

Precision Wide-Range Current Sink

10V

lout

=RX"

Al = LMll, LM607 or similar.
(V3 + 2V) ,;; Vou! ,;; + 20V.
01,02 = high Bela NPN, 2N3707, 2N3904 or similar.

-20V
TLlH/9110-19

Digitally Variable Supply
+15V
2

IN

LM369

OUT

VOU! = -10V x (Digitally Set Gain).

Al - LMllA, LM607, or similar.
MDAC = DACl220, DACl208, DAC1230, or similar.

TLlH/9110-20

4-51

II

CD
CD

ell)

.......
::::i

r------------------------------------------------------------------------------------------,
Typical Applications (Continued)
Ultra-Low-Nolse Statistical Reference

CD

CD
,...

+15V

...

::::i

REPEAT
. . " . - - -.....--~,......--...... - - - - - - , - - - - -AS
._..; ... _.
DESIRED
I

I

: U.l369:--.
I
I

•
•

• __ • • •
•

:

_.... -

-=

SEE
NOTE

R

I
I

I
I

I

t.

::R

.....--_....---.....---+---....-OUTPUT
OPTIONAL OUTPUT BUFFER

17>--

10K

BUFFERED
OUTPUT

TUH/9110-23

2000 ,,; R ,,; Ik
When N pieces of LM369 are used, the Vout noise is decreased by a factor of

iN

If the output buffer is not used, for lowest noise add 0.1 ".F Mylar" from ground to pin 5 of each LM369.

LM169 Block Diagram
+vs
VOUT

6K

t"~1~1K r i....--~~~=t::t---=::J:=---1

5

L--!.-------=t:===:t==~
4
•• PATENT PENDING
·Do not connect; internal connection for factory trim.

4-52

TRIM AND
FILTER

GROUND
TUH/9110-15

,-------------------------------------------------------------------------, r

s:
......

t!lNational Semiconductor

CD
U1

LM 185/LM285/LM385
Adjustable Micropower Vo;tage Re1ei"ei1ces

U1

.......
r

s:
N
CD

.......

r

:::

CU
CD
U1

General Description
The LM185/LM285/LM385 are micropower 3-1erminal adjustable band-gap voltage reference diodes. Operating from
1.24 to 5.3V and over a 10 )J-A to 20 mA current range, they
feature exceptionally low dynamic impedance and good
temperature stability. On-chip trimming is used to provide
tight voltage tolerance. Since the LM185 band-gap reference uses only transistors and resistors, low noise and
good long-term stability result.
Careful design of the LM185 has made the device tolerant
of capacitive loading, making it easy to use in almost any
reference application. The wide dynamic operating range
allows its use with widely varying supplies with excellent
regulation.
The extremely low power drain of the LM 185 makes it useful
for micropower circuitry. This voltage reference can be used
to make portable meters, regulators or general purpose an-

alog Circuitry with battery life approaching shelf life. Further,
the wide operating current allows it to replace older references with a tighter tolerance part.
The LM185 is rated for operation over a -55°C to 125°C
temperature range, while the LM285 is rated -40°C to 85°C
and the LM385 O°C to 70°C. The LM185 is available in a
hermetic TO-46 package and a leadless chip carrier package, while the LM285/LM385 are available in a low-cost
TO-92 molded package, as well as S.O.

Features
Adjustable from 1.24V to 5.30V
Operating current of 10 )J-A to 20 mA
Ell 1% and 2% initial tolerance
/ill 1 D. dynamic impedance
III Low temperature coefficient
III
Ii!

Connection Diagrams
TO-46
Metal Can Package

TO-92
Plastic Package

SO Package
Ne

Fa

TL/H/5250-9

TL/H/S2S0-1

Bottom View

Bottom View

Order Number LM285BXZ,
LM285BYZ, LM285Z, LM385BXZ,
LM385BYZ, LM385BZ or LM385Z
See NS Package Number Z03A

Block Diagram

Order Number
LM185BH, LM185BH/883,
LM185BYH or LM185BYH/883
See NS Package Number H03H

Ne

Ne

Ne
TLlH/S2S0-10

Order Number LM285M, LM285BYM,
LM385BM or LM385M
See NS Package Number M08A

Typical Applications
1.2V Reference
9V

5.0V Reference
9V
A1

A1

VOUT

~ 1.24 (~+ 1)

50k

500k

.---.q--5V

....--1.24V

A2
120k

TL/H/S2S0-13

A3

364k
TL/H/S2S0-14
TLlH/S2S0-2

4-53

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 2)
Reverse Current
30mA
Forward Current
Operating Temperature Range (Note 3)
LM185 Series
LM285 Series
LM385 Series
Storage Temperature

Soldering Information
TO-92 Package (10 sec.)
TO-46 Package (10 sec.)
SO Package
Vapor Phase (60 sec.)
Infrared (15 sec.)

260'C
300'C

215'C
220'C
See An-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

10mA
-55'Cto 125'C
- 40'C to 85'C
O'Ct070'C
- 55'C to 150'C

Electrical Characteristics (Note 4)
LM185, LM285

Conditions

Parameter

Reference Voltage

IR

=

100 ",A

Typ

1.240

LMI85BX, LM185BY
LMI85B, LM285BX,
LM285BY

LM385
LM385BX,
LM385BY

LM285

,.

LM385

Typ
Tested Design Tested Design
Limit
Umlt
Umit .Limit
(Note 5) (Note 6 (Note 5) (Note 6)

Tested
Limit
(Note 5)

Design Tested Design
Umlt
Limit
'Limit
(Note 6) (Note 5) (Note 6)

1.252

1.265

1.270 1.240 1.252

1.255

1.265

1.270

1.215

1.205

1.228

1.215

1,215

1.205

1
10

1.5
20

1
15

1.5
25

1
15

.1.5
25

'Units
(Limit)

,
V
(max)
V
(min)

1.255
1.228

1.215
Reference Voltage
IMIN-4-...---,
RI
22k

Iq =

7O~A

o < lOUT < 50 mA

R2
3k

R3
1M

"'---"--"'--tl-R7
332k

VOUy
5V

1%

H3
20k

+
RB

C2
500"F

1M
1%

-IIY
R6
22k

TUH/5250-5

4·56

Typical Applications (Continued)
Voltage Level Detector

Voltage Level Detector

HI
lZ0k

81
lZ0k

HZ

8Z
1M

1M

R3

<-IZV
LEO ON

83
330

ZOO

>-lZV
LED ON

-5V

-5V

Fast Positive Clamp
2.4V + aVD1

Bidirectional Clamp
±2.4V

I.

81

Your

+
50pA

8Z

01
IN914

OZ
IN914
H3
Z4~K'

H4
Z40K

Bidirectional Adjustable Clamp
± 1.8V to ± 2.4V

Bidirectional Adjustable Clamp
±2.4Vto ±6V

TlIH/5250-6

U) r-----------------------------------------------------------~--------~----------------~_,

CD

C")

:i;;,
~
:::E

....
...I

Typical Applications

-

Current Source
+15V

OT02DmA
+5V

U)

Rl
3900

CD

:1:2%

....

lN4DD2

...I

D2

:::E

(Continued)

Simple Floating Current Detector

Rl

R2
47Dl

01'

I"" < lOUT < lDDmA

N.C.

IDUT-..!J!!.
Rl

ITHRESHOLD- 1.24V + ~ '" 3.2 mA
Rl
4N28 BAIN

Precision Floating Current Detector

-

DT02DmA

Rl
33211
:1:·1.%

D2
1114G112

01'

TL/H/5250-7

• 01 can be any LED, VF= 1.5V to 2.2V at 3 rnA. 01 may act as an
indicator. 01 will be on H IniRESHOLD lalls below the threshold current
except with 1=0.

4-58

r-----------------------------------------------------------------------------'r
.....
==
Typical Applications (Continued)
co
Centigrade Thermometer, 10 mV/oC

r-------.--

Rl

UI

'"
r
==
~

Freezer Alarm

9V

R5
5Dk

10k

UI
.......
r

2.73V

:s::
Co)

co

UI
4.5V

=
R5
12k

TLlH/5250-11

BEEPS AT TEMPEIIlII\JRES ABOVE THAT SET
BY Rl (RANGE IS _30°F 10 +12DoFI
TL/H/5250-12

Schematic Diagram

R6
2DDk
REFERENCE
R7
5Dk

R8
3DOk

FEEDBACK

(FBI

TL/H/5250-B

Connection Diagrams (Continued)
20

19

18

17

ADJo-_:"'-....I

16
15
.
12

I~

13

TL/H/5250-15

Order Number LM185BE/883
See NS Package Number E20A

4-59

...."!•

."

~
::E

t!lNational Semiconductor

...I

"...."! LM 185-1.2/LM285-1.21 LM385-1.2
J,

,

co
C'I

::E
...I

C'....i
•

."

....

co

::E
...I

Micropower Voltage Reference Diode

General· Description
The LM185-1.2/LM285-1.2/LM385-1.2 are micropower
2-terminal band-gap voltage regulator diodes. Operating
over a 10 /LA to 20 rnA current range, they feature exceptionally low dynamic impedance and good temperature stability. On-chip trimming is used to provide tight voltage tolerance. Since the LM185-1.2 band-gap reference uses only
transistors and resistors, low noise and good long term stability result.

The LM185-1.2 is rated for operation over a -55·C to
125·C temperature range while the LM285-1.2 is rated
-40·Cto 85·Cand the LM385-1.2 OOC:to 70·C. The LM1851.2/LM285-1.2 are available in a hermetic T0-46 package
. and the LM285-1.2/LM385-1.2 are also available in a lowcost TO-92 molded package, as well as "S.O. The LM1851.2 is also available in a hermetic leadless chip carrier package.

Careful design of th!3 LM185-1.2 has made the device exceptionally tolerant of capacitive loading, making it easy to
use in almost any reference application. The wide dynamic
operating range allows its use with widely varying supplies
with excellent regulation.
The extremely low power drain of the LM185-1.2 makes it
useful for micropower circuitry. This voltage reference can
be used to make portable meters, regulators or general purpose analog circuitry with battery life approaching shelf life.
Further, the wide operating current allows it to replace older
references with a tighter tolerance part.

Features
•
•
•
•
•
•

±4 mV (±0.3%) max. initial tolerance (A grade)
Operating current of 10 /LA to 20 mA
0.60. max dynamic impedance (A grade)
Low temperature coefficient
Low voltage reference-1.235V
2.5V device and adjustable device also available
- LM185-2.5 series and LM185 series, respectively

Connection Diagrams
TO-92
Plastic Package (Z)

~

TUH/551 8-1 0

Bottom View
Order Number LM285Z-1.2,
LM285AZ-1.2, LM285AXZ-1.2,
LM285AYZ-1.2, LM285BXZ-1.2,
LM285BYZ-1.2, LM385Z-1.2,
LM385AZ-1.2, LM385AXZ-1.2,
LM385AYZ-1.2, LM385BZ-1.2,
LM385BXZ-1.2 or LM385BYZ-1.2
See NS Package Number Z03A

TO-46
Metal can Package (H)

Q

D

.

TUH/5518-8

Bottom View

Order Number LM185H-1.2,
LM185H-1.2/883, LM185BXH-1.2,
LM185BYH-1.2/883, LM285H-1.2,
LM285BXH-1.2 or LM285BYH-1.2
See NS Package Number H02A

S

so Package

·8

NC7

"C&

NCs

1
NC

2
NC

3
NC

4

TL/H/5518-9

Order Number LM285M-1.2,
L~285AM-1.2, LM285AXM-1.2,
LM285AYM-1.2, LM285BXM-1.2,
LM285BYM-1.2, LM385M-1.2,
LM385AM-1.2, LM385AXM-1.2,
LM385AYM-1.2, LM385BM-1.2,
LM385BXM-1.2 or LM385BYM-1.2
See NS Package Number M08A

Typical Application
SO Package
Alternate Pinout

"{7

is "ts

Wide Input
Range Reference
VIN· 2.3V TO JOY

Order Number LM385SM-1.2,
LM385ASM-1.2 or LM385BSM-1.2
See NS Package Number M08A

LM334

4.31<
OUT

U!4V

~ ~M3I1-1.2
TL/H/5518-11
TL/H/5518-8

4-60

r-

s:::
......
CD

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 2)
Reverse Current
Forward Current

Storage Temperature
Soldering Information
TO-92 package: 10 sec.
TO-46 package: 10 sec.
SO package: Vapor phase (60 sec.)
Infrared (15 sec.)

260'C
·300'C
215'C
220'C
See AN·450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other method!? of soldering surface mount devices.

30mA
10mA

Operating Temperature Range (Note 3)
LM185-1.2
LM285-1.2
LM385-1.2

-55'C to + 150'C

-55'Cto +125'C
-40'C to + 85'C

Tested
Limit
(Notes 5, 8)

1.235

LM385A-1.2
LM385AX-1.2
LM385AY-1.2
Design
Limit
(Note 6)

1.231
1.239

1.230

7

Typ
1.235

1.220
1.245

1.235

8

10

7

1
10

Tested
Limit
(Note 5)

Design
Limit
(Note 6)

1.231
1.239

1.225
1.245

Units
(Limit)

V(Min)
V(Max)
V(Min)
V(Max)
p.A
(Max)

8

10

1.5

1

1.5

mV
(Max)

20

10

20

mV
(Max)

Reverse Breakdown
Voltage Change with
Current

IMIN ~ IR ~ 1 mA

Reverse Dynamic
Impedance

IR = 100 p.A, f = 20 Hz

Wideband Noise (rms)

IR = 100p.A,
10Hz ~ f ~ 10kHz

60

60

p.V

Long Term Stability

IR = 100 p.A, T = 1000 Hr,
TA = 25'C ±0.1'C

20

20

ppm

Average Temperature
Coefficient (Note 7)

1M IN ~ IR ~ 20mA
X Suffix
Y Suffix
All Others

1 mA

~

IR

~

.

CD

LM285A-1.2
LM285AX-1.2
LM285AY-1.2
Typ

Minimum Operating
Current

•
......

~
.....
rs:::
c.:I
~

Conditions

IR=100p.A

CD

(J1

......

Electrical Characteristics (Note 4)

Reverse Breakdown
Voltage

~
.....
rs:::
N

(J1

0'Ct070'C

Parameter

V'
......

20 mA
0.2

0.6

0.2

1.5

30
50

n
(Max)

30
50
150

4-81

0.6

1.5

ppml'C
(Max)

150

Electrical Characteristics (Continued) (Note 4)

Parameter

Conditions

Typ

TA = 25°C.
10 joLA s: IR

s: 20 rnA

Minimum Operating
Current
Reverse Breakdown
Voltage Change with
Current

Reverse Dynamic
Impedance

10joLA
1 rnA
IR

s:

s:

IR

IR

s:

LM385-1.2
Units
(Limit)

1.223
1.247

8

10

20

15

20

15

20

p.A
(Max)

1

1.5

1

1.5

1

1.5

mV
(Max)

10

20

20

25

20

25

mV
(Max)

s: 20 rnA

= 100 p.A. f = 20 Hz

IR = 100 p.A. T = 1000 Hr.
TA = 25°C ±0.1°C

1.205
1.260

1.235

1 rnA

Wideband Noise (rms) IR = 100 p.A.
10Hz s: f s: 10kHz
Long Term Stability

LM385B-1.2
LM385BX-1.2
LM385BY-1.2

Tested
Design Tested Design Tested Design
Limit
Limit
Limit"
Limit
Limit
Limit
(Notes 5, 8) (Note 6) (Note 5) (Note 6) (Note 5) (Note 6)

..
Reverse Breakdown
Voltage

LM185-1.2
LM185BX-1.2
LM185BY-1.2
LM285-1.2
LM285BX-1.2
LM285BY-1.2

1.223
1.247

'V(Min)
V(Max)

1

n

60

p.V

20

ppm

Average Temperature IR = 100 p.A
Coefficient (Note 7) , X Suffix
Y Suffix
All Others

30
50

30
50
150

150

150

ppm'oC
ppml"C
ppml"C
(Max)

Note 1: Absolute Maximum Ratings Indicate IimHs beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
Intended to be functional, but do net guarantee speCific performance limits, For guaranteed speCifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed.
Note 2: Refer to RETS185H·l.2 for military specHications.
Note 3: For elevated temperatura operation, Tj max is:
LM185
150"C
LM285
125"C
LM385
l00'C
Thermal Reatstance

T().92

TO·46

SO..

8JA ijunction to ambient)

18O'C/W (0.4' leads)
170"C/W(0.125" leads)

44O"C/W

165"C/W

N/A

80"C/W

N/A

8JC ijunction to case)

..

Note 4: Parameters Identified wHh boldface type apply at temperature extremes. All other numbers apply at TA = TJ
Note 5: Guaranteed and 100% production tested.

= 25"C.

Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate average outgoing qualily levels.
Note 7: The average temperature coefficient is defined as the maximum deviation of reference voltage at all measured temperatures between the operating TMAX
and TMIN, divided by TMAX - TMIN' The measured temperatures are -55'C, -4O'C, O"C, 25'C, 70"C, 85'C, 125'C.
Note 8: A military RETS electrical specification is available on request.

4-62

~
....
CD
......

Typical Performance Characteristics

U1

Reverse Characteristics

Reverse Characteristics

.....
N

;;

CD

..
g
..
.sw

..
B
....
ffi

10

..'"
~
.."'"
w

~

~

::l

~
.....
r-

>

~>

!l:

U1

a

w

r2

:s:::
Co)

0.4

CD

U1

....•

~

~

-2

0.2

OA

0.6

0.8

1.0

1.2

0.01

1.4

Temperature Drift of 3
Representative Units

~

1.240

~

!i!

L.o-

~

1.230

Ii!

I'"

i""o

I'

1.220

100
FORWARD CURRENT (mAl

Reverse Dynamic Impedance

roo

i-'"

!\i

10

-....

Reverse Dynamic Impedance
10k

100 r-rTlTnnI'"'TT

'~=I~o~~-

~ 1.250

0.1

REVERSE CURRENT (mAl

REVERSE VOLTAGE (VI

1.260

T.

£w

.."'"

S

atl

10

fil
~

a!

!o!

0.1

~
~

!.

I

-=!!!
"

...~
w

300

~

200
100

"'

~
!!!

1/

100

V

.,- V
Ik

10k

lOOk

1M

FR£OUENCY (Hz)

Response Time
2.0

•

1.5

60

.
iii
..

a

50
40

1.0
0.5

~

30

!;;

20

>

10

10

JIIIIID

11111111
100

10

Filtered Output Noise

400

10

,i-:-'"'

100

70

;;

0

10

~

10

REVERSE CURRENT (mAl

Noise Voltage
6DO

/

100

I

~'"

-55-35-15 5 25 45 65 85105125
TEMPERATURE IDC)

500

= 25"C
= 100pA

~

"iii

'R,'0o.A

'R

Ik

O.

TOO

1k

'Ok

FREQUENCY (Hz)

lOOk

~
.....
r-

:s:::

10

100

.-=

Forward Characteristics

1k

"III

CUTOFF FREQUENCY (Hz)

lOOk

200

400

aDo

TlME(.S)

TLlH/5518-3

4-63

Typical Applications (Continued)
Mlcropower Reference
from 9V Battery

Reference from
1.5V Battery

f

1.5V

9V5Dak

k
}

l.2V

'::'

LM385~1.Z

1.2V
'::' LM385-1.2

TL/H/5518-2

Mlcropower' 5V Regulator

Micropower' 10V Reference

r-.------...

-------~.,;...--VIN~&.2V

-

IQ

. - - - _....--VIN·15V

....-_..... 10V

>~

r---....

VO=5V
~~ IL ~ 100mA

150 pF

3.5M

390k

+. 4.7~F
500k

TANTALUM

LM38i-1.2

10M

2k

"10 '" 20 p.A standby current
"10 '" 30 p.A

Precision 1 ,..A to 1 mA Current Sources

LM385-1.2

.
LM385-1.2

Cl
150pF

1.5V TO 27V - - - -. .- - -......""',.,.....
-1.5V TO -27V --";'-"---+-""~...I

-3OV
1.23V

"lOUT

= Fi2

4-64

TL/H/5518-4

Typical Applications (Continued)
METER THERMOMETERS
O'C -100'C Thermometer

Lower Power Thermometer

150

1.HO
1.6V*
BkTO

12kt

R4
220

• 2N3638 or 2N2907 select for Inverse HFE '" 5
t Select for operation at 1.3V

*

la '" 600 fLA

to 900 fLA

calibration
1. Short LM38S·1.2. adjust R3 for IOUT=temp at 1 fLAI'K
2. Remove short, adjust R2 for correct reading in centigrade

tla at 1.3V" SOO fLA
la at 1.6V '" 2.4 rnA

O'F - 50'F Thermometer

Micropower Thermocouple Cold Junction Compensator

v·
2k
til

5.1k

1M

1%
MERCURY
CELL

y-

+

TCADJ

500

1.J45V
1.J-1.6V
R2

R4

100

THERMOCOUPLE

Rl

+

\_,
COLD JUNCTION
ISOTHERMAL
WITH LMJ34

Calibration

TL/H/5518-5

1. Short LM38S·1.2. adjust R3 for lOUT = temp at 1.8 fLAl'K
2. Remove short. adjust R2 for correct reading in 'F

Adjustment Procedure
1. Adjusl TC ADJ pot until voltage across Rl equals Kelvin temperature
multiplied by the thermocouple Seebeck coefficient
2. Adjust zero ADJ pot until voltage across R2 equals the thermocouple
Seebeck coefficient multiplied by 273.2.
Voltage
Thermocouple
Seebeck
Rl
R2
VoHage
Type
Coefficient (0)
(0)
AcrossRl AcrossR2
@2S'C
(fLVI'C)
(mY)
(mY)
15.60
14.32
J
52.3
523 1.24k
11.78
T
lk
12.77
42.8
432
11.17
K
40.8
12.17
412 9530
1.766
5
6.4
1.908
63.4 1500
Typical supply current 50 fLA

4·65

Typical Applications (Continued)
Centigrade Thermometer

Calibration
1. Adjust RI so that VI = temp at 1 mVrK
2. Adjust V2 to 273.2 mV

t.5V'

tlo for 1.3V to 1.6V battery volt·
age = 50 ".A to 150 ".A

TL/H/5518-1

Schematic Diagram

TL/H/5518-7

Connection Diagrams (Continued)
-GND

••
•
3

1

5
6

..

'

2

r

~

2.

19

17

~

16

7

••

18

IS
14
1011

12

13

TLlH/5518-12

Order Number LM185E·1.2/883
See NS Package Number E20A

4-66

f}1National Semiconductor

LM 185-2.5/LM285-2.5/LM385-2.5 Micropower
Voltage Reference Diode
General Description
The LM1B5-2.5/LM2B5-2.5/LM3B5-2.5 are micropower 2terminal band-gap voltage regulator diodes. Operating over
a 20 p.A to 20 mA current range, they feature exceptionally
low dynamic impedance and good temperature stability. Onchip trimming is used to provide tight voltage tolerance.
Since the LM-1B5-2.5 band-gap reference uses only transistors and resistors, low noise and good long term stability
result.
Careful design of the LM1B5-2.5 has made the device ex-'
ceptionally tolerant of capacitive loading, making it easy to
use in almost any reference application. The wide dynamic
operating range allows its use with widely varying supplies
with excellent regulation.
The extremely low power drain of the LM1B5-2.5 makes it
useful for micropower circuitry. This voltage reference can
be used to make portable meters, regulators or general purpose analog circuitry with battery life approaching shelf life.

Further, the wide operating current allows it to replace older
references with a tighter tolerance part. For applications requiring 1.2V see LM1 B5-1.2.
The LM1 B5-2.5 is rated for operation over a - 55·C to
125·C temperature range while the LM2B5-2.5 is rated
-40·C to B5·C and the LM3B5-2.5 O"C to 70·C. The LM1 B52.5/LM2B5-2.5 are available in a hermetic TO-46 package
and the LM2B5-2.5/LM3B5-2.5 are also available in a lowcost TO-92 molded package, as well as S.O. The LM1 B5-25
is also available in a hermetic leadless chip carrier package.

Features
•
•
•
•
•
•

±20 mV (±O.B%) max. initial tolerance (A grade)
Operating current of 20 ,...A to 20 mA
0.6.0 dynamic impedance (A grade)
Low temperature coefficient
Low voltage reference-2.5V
1.2V device and adjustable device also availableLM1B5-1.2 series and LM1B5 series, respectively

Applications
Wide Input Range Reference

Micropower Reference from 9V Battery

t

YIN· 3.1V TO lOV

av

200k

LM334

Uk

Z.5V

OUT

',;l~M3B5.2.5

2.SV

':' LM385-2.5
TUH/5519-2

'*

TL/H/5519-12

Connection Diagrams
10-92

10-46

Plastic Package

Metal Can Package

TL/H/5519-8

Bottom View
Order Number LM285Z-2.5,
LM285AZ-2.5, LM285AXZ-2.5,
LM285AYZ-2.5,
LM285BXZ-2.5, LM285BYZ-2.5,
LM385Z-2.5, LM385AZ-2.5,
LM385AXZ-2.5, LM385AYZ-2.5,
LM385BZ-2.5, LM385BXZ-2.5
or LM385BYZ-2.5
See NS Package Number Z03A

8

SO Package
8

NC
17

Nt&

NC
5

I

,........
~

TL/H/5519-13

Bottom View
Order Number LM185H-2.5,
LM185H-2.5/883
LM 185BXH-2.5, LM185BXH-2.5/883,
LM185BYH-2.5, LM185BYH2.5/883,
LM285H-2.5, LM285BXH-2.5
or LM285BYH-2.5
See NS Package Number H02A

4-67

+

TL/H/5519-11

Order Number LM285M-2.5,
LM285AM-2.5, LM285AXM-2.5,
LM285AYM-2.5, LM285BXM-2.5,
LM285BYM-2.5, LM385M-2.5,
LM385AM-2.5, LM385AXM-2.5,
LM385AYM-2.5, LM385BM-2.5,
LM385BXM-2.5 or LM385BYM-2.5
See NS Package Number M08A

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 2)
'. "
,
Reverse Current
30mA
10mA
Forward Current

Storage Temperature
Soldering Information
TO-92 Package (10 sec.)
TO-46 Package (10 sec.)
SO Package
Vapor Phase (60 sec.)
Infrared (15 sec.)

Operating Temperature Range (Note 3)
LM185-2.5
-55·C to + 125·C
- 40·C to + 85·C
LM285-2.5
O·C.t070·C
.LM38S-2.S

-55·C.to

+ 150"C
260"C
300"C
215·C
220"C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

..

Electrical Characteristics (Note 4)
LM285A-2.5
LM285AX·2.5
LM285AY·2.5

"

Paran'leter

Conditions

Typ

Tested
. Limit
(Notes 5, 8)
Reverse Breakdown
Voltage

IR = 100,..A

2.500

2.480
2.520

.2.500
Minimum Operating
Current
Reverse Breakdown
Voltage Change with
Current

Design
Limit
(Note 6)

LM385A·2.5
LM385AX-2.5
LM385AY·2.5
Tested
Limit
(Note 5)
2.480
2.S20

2.460
2.535

12
1M IN :s: IR :s: 1mA
1 mA :s: IR :s: 20 mA

Design
Limit
(Note 6)

2.470
2.530

Units
(Limits)

V(Min)
V(Max)
V(Min)
V(Max)
j.£A
(Max)

18

20

18

20

1

1.5

1

1.5

mV
(Max)

10

20

10

20

mV
(Max)

0.6

0.6

1.5

1.5

:n

..

;

Reverse Dynamic
Impedance

IR = 100,..A,
f = 20Hz

0.2

Wideband Noise (rms)

IR = 100,..A
10Hz:s:f:s: 10kHz

120

,..V

Long Term Stability

IR = 100,..A,
T = 1000 Hr,
TA = 2S·C ±0.1·C

20

ppm

Average Temperature
Coefficient (Note 7)

IMIN:S: IR:S: 20mA
X Suffix
Y Suffix
All Others

30
50

30
50
150

..

4-68

ppml"C
(Max)

150

r-

i!!:
....
CD

Electrical Characteristics (Continued) (Note 4)

Parameter

Conditions

LM18S-2.S
LM18SBX-2.S
LM18SBY-2.S
LM28S-2.S
LM28SBX-2.S
LM28SBY-2.S

Typ

Tested
Limit
(NotesS,8)
Reverse Breakdown
Voltage

TA = 25"C,
20 !LA ,;; IR ,;; 20 mA

Minimum Operating
Current

Design
Limit
(Note 6)

2.462
2.538

2.5
13

CJ1

LM38S-2.S

Units
(Limit)

Design
Limit
(Note 6)

Tested
Limit
(Note S)
2.425
2.575

2.462
2.538

r-

i!!:
(.)

CD

V(Min)
V(Max)

20

30

20

30

20

30

!LA
(Max)

1.5

2.0

2.5

2.0

2.5

mV
(Max)

1 mA ,;; IR ,;; 20 mA

10

20

20

25

20

25

mV
(Max)

Reverse Dynamic
Impedance

IR = 100 ",A,
f = 20Hz

Wideband NQise (rms)
Long Term Stability

1

.n

IR = 100 ",A,
10 Hz ,;; f ,;; 10 kHz

120

",V

IR = 100",A,
T = 1000Hr,
TA = 25"C ±O.l"C

20

ppm

= 100 ",A
30
50

30
50
150

All Others

150

150

ppml"C
ppml"C
ppml"C
(Max)

Note 1: Absolute Maximum Ratings indicate IimHs beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test ~ondHlons, see the Electrical Characteristics.

The guaranteed specifications apply only for the test conditions listed.
Note 2: Refer to RETS18SH·2.S for military specifications.
Note 3: For elevated temperature operalion, TJ MAX is:
LM18S
lSO"C
LM28S
125'C
LM38S
100"C
Thermal Resistance
6jB (Junction to Ambient)
6jB (Junction 10 case)

TO·92

TO....&

180"C/W (0.4' Leads)
44O"C/W
170"C/W (0.12S' Leads)

N/A

80'C/W

SO-S

16S'C/W
N/A

Note 4: Parameters Identified with boldface type apply allemperalure extremes. All other numbers apply at TA = TJ = 2S'C.
Note 5: Guaranteed and 100% production tesled.
Note 6: Guaranteed, but noll00% production tesled. These limils are nol used 10 calculate average outgoing quality levels.
Note 7: The average temperature coefficient is defined as the maximum deviation of reference voltage at all measured temperatures between the operating TMAX

and TMIN, divided byTMAX-TMIN' The measurad temperalures are -SS'C, -40"C, O'C, 2S'C, 70"C, 8S'C, 12S'C.
Note 8: A military RETS electrical specification evailable on request.

4-69

CD

C71

Design
Limit
(Note 6)

1

IR

I\)

I\)

Tested
Limit
(Note S)

20 !LA ,;; IR ,;; 1 mA

X Suffix
Y Suffix

r-

i!!:
CJ1

Reverse Breakdown
Voltage Change with
Current

Average Temperature
Coefficient (Note 7)

·
•

I\)

C71

LM38SB-2.S
LM38SBX-2.S
LM38SBY-2.S

·

CJ1
I\)

C71

Typical Performance Characteristics
100

Reverse Characteristics

Rev.erse Characteristics
18

s:

.!

12

m

TA _25°e

~w

e

0,1

""""""_.l--+_.l--I.---J
D.B

1.0 1.5
2.0 2.5
REVEIISE VOLTAGE (V)

0.01

1.2

~
>

0.'

I

OA

~

t~r Tilil

-4

3.0

~
w

1\

~

~

Forward Characteristics

il~~.I,~!I~1

0.1

10
REVE~SE CURRENT (mAl

o L..U.J.III.I'-1..LLWI'-L.WWIL...L1
Ul

IDO

§

~2.5ID

~

w

~2.500
!:;

i

i

10

~Z.4&D
2,451

5 25 45

/'

/

10,

3.0

I-rtl+tt1Il--H

1000

~

100

i

1k

10k

I

...;.....

~f

-

.~

T

~

"
100

-:;:-

-

!:;

10

AI
~

1.0

~

100

200

1M

/' 'OUTPut

2.0

m

400

10011

Response Time

120 r-rrrtn'm-T'T-nTmr--r-ITI111m
100

',Il

1k

FREQUENCY (Hz)

Filtered Output Noise
li~"G1~"

1200

100

REVERSE CURRENT (mAl

Noise Voltage
1400

I

10

IS 85 '05 12&

TEMPERATURE reI

~

. jV

0.1

-55 -35 -15

~

:V

101

1

~

:2.470

IR·IDD~A

w

l;!

u

fi!UIO

II!

~A·25°C

,.

§

100

g

....

~

~2A90
w

100

10k

'R-1DDI-IA

2.520

10

Reverse Dynamic
Impedance

IUDD

2.530

. 0.1

foRWARD CURRf:NT (mAl

Revers.e Dynamic
Impedance

Temperature Drift

l-+tH1t11-+ti'*llll-+HtlHt-HtHltH

10

lOOk

,.

10.

FREDUENCY 1Hz)

10k

INPUT

'0

lOOk

200

0110

800

TIME "'~

CUTOFf FREOUENCY (HI)

TLlH/5519,-3

Connection Diagram
- GND

.M_M·

MM

•

3

2

1

20

5

)

•

~

"IE
"II
IS •

"II

7
8

19

•

10 11

12

131"'~

TL/H/5519-14

Order Number LM185E-2.5/883
See NS Package Number E20A
4-70

LM385-2.5 Applications
Mlcropowero 10V Reference

Mlcropowero 5V Regulator

r---_,~
....--

1""!'------....-------..

;....--'vIN~5.2V

VIN·,5V

5UUk

r-_..........-4~VD =5V
IL

~

lDOmA

lOOk

+

LM385·2.5

10M

4.1 ~F
TANTALUM

2k
TLiH/5519-10

'10 .. 30 /LA standby current
TL/H/5519-9

'10'" 40 "A

Precision 1 /LA to 1 mA Current Sources
LMJ85·2.5

LM385·2.5

Cl
150pF

----.J\M,.......

-1.5V TO -27V - - - -...---+~NIr_..t

1,5V TO 27V - - - -...

-JOV
'IOUT-

2~V

TLiH/5519-4

METER THERMOMETERS
O'C-100"C Thermometer

O"F-50"F Thermometer
Ik

Ii

R4
100

R4

220

TLiH/5519-5

callbraUon

calibration ,

1. Short LM385-2.5. adjust R3 for IOUT=temp at I,.ArK

1. Short LM385-2.5. adjust R3 for lOUT = lemp at 1.8 /'A/'K

2. Remove shorl, adjust R2 for correct reading In centigrade

2. Remove short, adjust R2 for correct reading in 'F

4-71

U) r-~----------------~------~~--------------~------------~~~--------~------,

~
~

LM385-2.5 Applications (Continued)
Micropower Thermocouple Cold Junction Compensator.,

~

y+

~

Ui

I. Adjust TC ADJ pot until voltage across RI equals Kelvin temperature
muHiplled by the thennocouple Seebeck coefficient. .

1M
1%

fS

~

Adjustment Procedure

'210
,1%

~
U)

y-

3Y +

:;:
....

CD

HZ

~

,-,
THERMOCOUPLE

+

2. Adjust" zero ADJ pot until voltage across R2 aquals the thermocoupIa
Seebeck coefficient multiplied by 273.2.

TC AD!
500

LITHIUM

RI

+
METER

\_,
COLD JUNCTION
ISOTHERMAL
WITH LM334

TLlH/5519-6

Thermocouple
Type

J
T
K

S

Seebeck
Caefficient
(".vrC)
52.3
42.8
40.8
6.4'

R1
(.0.)

R2
(0)

523
432
412
63.4

1.24k
1k
953.0.
150.0.

Voltage
Acfo.sR1
@2S"C
(my)
15.60
12.77
12.17
1.908

Voltage
AcrossR2
(my)

Improving Regulation of Adjustable
Regulators

14.32
11.78
11.17
1.766

Typical supply current 50 p.A

TLlH/5519-7

Schematic Diagram'

R6

ZOOk

R7
SDk

500k

SOOk

TLlH/5519-1

4-72

,-------------------------------------------------------------------------, r

....
==
CD

tflNational Semiconductor

~
r

==
CD
~

LM 199/LM299/LM399/LM3999 Precision Reference

CD
......

General Description

Co)

r

~

The LM199 series are precision, temperature-stabilized
monolithic zeners offering temperature coefficients a factor
of ten better than high quality reference zeners. Constructed on a single monolithic chip is a temperature stabilizer
circuit and an active reference zener. The active circuitry
reduces the dynamic impedance of the zener to about 0.50
and allows the zener to operate over 0.5 rnA to 10 rnA current range with essentially no change in voltage or temperature coefficient. Further, a new subsurface zener structure
gives low noise and excellent long term stability compared
to ordinary monolithic zeners. The package is supplied with
a thermal shield to minimize heater power and improve temperature regulation.
The LM199 series references are exceptionally easy to use
and free of the problems that are often experienced with
ordinary zeners. There is virtually no hysteresis in reference
voltage with temperature cycling. Also, the LM199 is free of
voltage shifts due to stress on the leads. Finally, since the
unit is temperature stabilized, warm up time is fast.
The LM199 can be used in almost any application in place
of ordinary zeners with improved performance. Some ideal
applications are analog to digital converters, calibration
standards, precision voltage or current sources or precision
power supplies. Further in many cases the LM199 can replace references in existing equipment with a minimum of
wiring changes.

Connection Diagrams

The LM199 series devices are packaged in a standard hermetic TO-46 package inside a thermal shield. The LM199 is
rated for operation from - 55·C to + 125·C while the LM299
is rated for operation from - 25·C to + B5·C and the LM399
is rated from O·C to + 70·C.
The LM3999 is packaged in a standard TO-92 package and
is rated from O·C to + 70·C

Features
II Guaranteed 0.0001 %I"C temperature coefficient
iii Low dynamic impedance -

0.50

II Initial tolerance on breakdown voltage -

2%

II Sharp breakdown at 400 /LA
III Wide operating current -

500 /LA to 10 mA

II! Wide supply range for temperature stabilizer

• Guaranteed low noise
CI Low power for stabilization - 300 mW at 25·C
II Long term stability - 20 ppm
II Proven reliability, low-stress packaging in TO-46 integrated-circuit hermetic package, for low hysteresis after
thermal cycling. 33 million hours MTBF at TA = + 25·C
(TJ = +86·C)
101 Certified long term stability available.
III MIL-STD-883 compliant

Functional Block Diagrams
LM 199/LM299/LM399

Metal Can Package (TO-46)

+
TlIH/5717-14

Top View
LM199/LM299/LM399 (See Table on fourth page)
NS Package Number H04D

TUH/5717-15

LM3999

Plastic Package TO·92

~.ooo

Q

TlIH/5717-10

BotlomVlew
LM3999 (See Table on fourth page)
NS Package Number Z03A
TlIH/5717-11

4-73

CD
CD

......
r

==
Co)

:8
CD

Absolute Maximum Ratings
Specifications for Military/Aerospace products are not
contained in this datasheet. Refer to the following Reliability Electrical Test Specifications documents:
RETS199X for LM199, RETS199AX for LM199A.
Temperature Stabilizer Voltage
LM199/LM299/LM399
LM3999

40V
36V

Reverse Breakdown Current

20 rnA

Forward Current
LM199/LM299/LM399
LM3999

40V
-0.1V

Reference to Substrate Voltage V(RS) (Note 1)
Operating Temperature Range
LM199
LM299
LM399/LM3999

- 55'C to + 125'C
'-- 25'C to + 85'C
- O'C to + 70'C

Storage Temperature Range

- 55'C to + 150'C

Soldering Information
TO·92 package (10 sec.)
TO-46 package (10 sec.)

1 rnA
-0.1 rnA

+ 260'C
+300'C

Electrical Characteristics (Notes 2, 5)

Reverse Breakdown Voltage

0.5 mA:O: IR :0: 10 rnA

Reverse Breakdown Voltage
Change with Current

0.5 rnA :0: IR:O: 10mA

Reverse Dynamic Impedance

IR = 1 rnA

Reverse Breakdown
Temperature Coefficient

LM199H/LM299H

Conditions

Parameter

Max

Min

Typ

.·Max

6.8

6.95

7.1

6.6

6.95

7.3

V

6

9

6

12

mV

1

0.5

1.5

n

0.00003

0.0002

%rC
%rC
%rC
%rC

7

50

/LV

0.00003
0.0005
0.00003

LM199
LM299
LM399

RMS Noise

10 Hz:o: f:o: 10 kHz

7

Long Term Stability

Stabilized,22'C:O:TA:O:28'C,
1000Hours,IR=1 mA±0.1%

20

Temperature Stabilizer
Supply Current

TA=25'C, Still Air, Vs=30V
TA = - 55'C

8.5
22

Temperature Stabilizer
Supply Voltage

0.0001
0.0015
0.0001
20

Vs = 30V, TA = 25'C

Initial Turn-on Current

9:O:Vs:O:40, TA= + 25'C, (Note 3)

Electrical Characteristics

ppm

20
14
28

8.5

40

9

Warm·Up Time to 0.05%

Units

Typ

. 0.5

-55'C:O:TA:O: +85'C }
+ 85'C:O:TA:O: + 125'C
-25'C:O:TA:O:85'C
O'C:O:TA:O: +70'C

LM399H

Min

15

9

40
3

3
200

140

mA
V
sec.

140

rnA

200

(Note 2)
LM3999Z

Parameter

Conditions

Reverse Breakdown Voltage

0.6mA:o: IR:O: 10mA

Reverse Breakdown Voltage
Change with Current

0.6 rnA :0: IR:O: 10mA

Units
Min

Typ

Max

6.6

6.95

7.3

V

6

20

mV

0.6

2.2

n

0.0002

0.0005

%rC

Reverse Dynamic Impedance

IR = 1 mA

Reverse Breakdown
Temperature Coefficient

O'C:O: TA :0: 70'C

RMS Noise

10Hz :0: f :0: 10kHz

7

/LV

Long Term Stability

Stabilized, 22'C :0: T A :0: 28'C,
1000 Hours, IR = 1 rnA ±0.1 %

20

ppm

Temperature Stabilizer

T A = 25'C, Still Air, Vs = 30V

12

Temperature Stabilizer
Supply Voltage

-

Warm-Up Time to 0.05%

Vs = 30V, TA = 25'C

Initial Turn-On Current

9:0: Vs :0: 40, TA = 25'C

18

rnA

36

V

5

4·74

140

sec.
200

rnA

Electrical Characteristics (Notes 2, 5)
Parameter

LM199AH, LM299AH

Conditions

Reverse Breakdown Voltage

0.5 mA ,;;; IR ,;;; 10 mA

Reverse Breakdown Voltage
Change with Current

O.5mA:S: IR';;; 10mA

Reverse Dynamic Impedance

IR = 1 mA

Reverse Breakdown
Temperature Coefficient

-550 C:S:TA:S:+85°C}
+ 85°C:S:TA';;; + 125°C
-25°C:S:TA:S:85°C
0°C:S:TA:S:+70°C

Max

Min

Typ

Max

6.8

6.95

7.1

6.6

6.95

7.3

V

6

9

6

12

mV

0.5

1.5

n

0.00003

0.0001

%I"C
%,OC
%I"C
%I"C

7

50

/LV

LM299A
LM399A

0.5

1

0.00002
0.0005
0.00002

0.00005.
0.0010
0.00005
20

RMS Noise

10Hz:S:f:S: 10kHz

7

Long Term Stability

Stabilized,22°C,;;;TA:S:28°C,
1000 Hours, IR= 1 mA±0.1 %

20

Temperature Stabilizer
Supply Current

TA=25°C, Still Air, Vs=30V
TA =- 55°C

8.5
22

Vs = 30V, TA = 25°C

Initial Turn-on Current

9:S:Vs:S:40, TA= + 25°C, (Note 3)

ppm

20
14
28

8.5

40

9

Warm-Up Time to 0.05%

Units

Typ

LM199A

Temperature Stabilizer
Supply Voltage

LM399AH

Min

9

15

40

3

3

140

200

mA
V
sec.

140

200

mA

Electrical Characteristics (Notes 2, 5)
Parameter

LM199AH-20, LM299AH-20

Conditions

Reverse Breakdown Voltage

0.5 mA:S:IR:S:10 mA

Reverse Breakdown Voltage
Change With Current

0.5 mA,;;;IR';;;1O mA

-55°C:S:TA,;;;85° }
85°C:S:TA,;;;125°C
-25°C,;;;TA:S:85°C
0°C:S:TA:S:70"C

Units

Typ

Max

Min

TVp

Max

6.8

6.95

7.1

6.6

6.95

7.3

V

6

9

6

12

mV

0.5

1.5

Reverse Dynamic Impedance IR = 1 mA
Reverse Breakdown
Temperature Coefficient

LN!399AH-50

Min

LM199A
LM299A
LM399A

0.5

1

0.00002
0.0005
0.00002

0.00005
0.0010
0.00005
0.00003 0.0001

n
%,OC
%I"C
%I"C
%,OC

RMSNoise

10 Hz:S:f:S:10 kHz

7

20

7

50

/LV

Long Term Stability

Stabilized,22'C:S:TA:S:28'C,
1000 Hours, IR=1 mA±0.1%

8

20

9

50

ppm

Temperature Stabilizer
Supply Current

TA= 25'C, Still Air, Vs = 30V
TA=55°C

8.5
22

14
28

8.5

15

Temperature Stabilizer
Supply Voltage

9

Warm-Up Time to 0.05%

Vs=30V, TA = 25°C

Initial Turn-on Current

9,;;;Vs:S:40, TA = 25'C, (Note 3)

40

40

V

200

mA

3

3
140

9

200

140

mA

s

Nole I: The substrate is electrically connected to the negative terminal of the temperature stabilizer. The voltage that can be applied to either terminal of the
reference is 40V more positive or 0.1V more negative than the substrate.
Note 2: These specifications apply for 30V applied to the temperature stabilizer and - 55'C:<:TA:<: + 125'C for the LM199; - 25'C:<:TA:<: +85'C for the LM299 and
O'C:<:TA:<: +70'C for the LM399 and LM3999.
Nole 3: This Initial current can be reduced by adding an appropriate resistor and capacitor to the heater circu~. See the performance characteristic graphs to
determine values.

Nole 4: Do nol wash the LM199 with its polysulfone thermal shield in TCE.
Note 5: A mil~ary RETS electrical test specification is available for the LMI99H/BB3, LMI99AH/BB3. and LMI99AH-20/BB3 on request.

4-75

Ordering Information
Initial
Tolerance

IrCto +7lrC

2%
5%

LM399H
LM399AH

5%

LM3999Z

Guaranteed Long
Term Stability

LM399AH-50

- 2S'C to + 8S'C

"

HS
Package

-SS'C to + 12S'C

LM299AH

LM199AH, LM199AH/883

H04D

LM299H

LM199H, LM199H/883

H04D
Z03A

LM299AH-20
,

LM199AH-20, LM199AH-20/883

H04D

_Certified Long Term Drift
The National Semiconductor LM199AH-20, LM299AH-20,
and LM399AH-50 are ultra-stable Zener reierences specialIy selected from, the production runs of LM199AH,
LtV1299AH, LM399AH and tested to confirm a long-term stabilityof 20,20, or 50 ppm 'per 1000 hours, respectively. The
devices are measured every 168 hours and the voltage of
each device is logged and compared in such a way as to
show the deviation from its initial value. Each measurement
is taken with a probable-worst-case deviation of ±2 ppm,
compared to the Reference Voltage, which is derived from
several groups of NBS-traceable references such as
LM199AH-20's, 1N827's, and saturated standard ce!ls, so

that the deviation of anyone group will not cause false indications. Indeed, this comparison process has recenUy been
automated using a specially prepared computer program
which is custom-designed to reject noisy data (and require a
repeat reading) and to record the average of the best 5 of 7
readings, just as a sagacious standards engineer will reject
unbelievable readings.
The typical characteristic for the LM199AH-20 is shown balow. This computerized print-out form of each reference's.
stability is shipped with the unit

Typical Characteristics
National Semiconductor
Certified Long Term Drift
Hrs

Drift

168
336
504
672
840
1008

-20
-24
-36
-34
-40
-36

LM199AH-20
Part #6849
Umlts
LM199AH-20 140 p.V
LM299AH-20 140 p.V
LM399AH-20 3,50 p.V

0
R

813

I
F

413

pV

a

T

-...

-413

Testing Conditions
Heater Voltage
Zener Current
Ambient Temp.

1213

30V
1 mA
25'C

--.

-86

-1213
0

168

336

5134

672

840 11308

HOURS
TLlH/5717-12

4-76

Typical Performance Characteristics
Reverse Characteristics

Dynamic Impedance

Reverse Voltage Change
100

...

ic

1.0

~C ~ ~

~

10'"

."

VrA1f.ABILlZ~1
&.&5

6.B5

7.05

!..

.!

-1

....

"

~

STABILIZED IT, .90 CI_

T, "'25 C

-2

J25 C

I

I

L

I

Ik

10k

o

lOOk

fREOUENCV IHoi

Heater Current

--

c

....

I

i

12
16
HEATER ON TIME -ISECI

~

E
!!

B5 105

Heater Surge Limit Resistor vs
Minimum Supply Voltage at
Various Minimum Temperatures

:s.

BOO

..

600 ~~~~~~1--+~~

;;

SOD

W

~ 700

150

...... r--.

25 45 65

TEMPERATURE rCI

;::

i:::; 400

.......

~ 300 I-+--+-I--¥-~,> 9D"CI

'"~

",.

...

,

TIME

TLiH/5717-3

~

INPUT-

lOG

10

QU"UI

10
10

TIME IMINUTES!

f-f-f--

'.'UI

200

r--

300

400

I.~

TLiH/5717-7

4-77

•

Typical Applications
Single Supply Operation

Split Supply Operation
+15V---..----,

9V TO 40V-~~---..,

'5'

TEMPERATURE

lEMPERATURE

STABILIZER

STABILIZER

69[JV

695V

-15V

Negative Heater Supply with
Positive Reference

Buffered Reference
With Single Supply

-I5V-------,

.15V--. . .- - - -. . .- - - - - - - _ ,

'"

Ok

15k

TEMPERATURE

TEMPERATURE

STABILIZER

STABILIZER

695V

lOV

G95V

9V TO
J]V

Positive Current Source
10V TO 4(1V-....- - - -........;.-....------_-------

Square Wave Voltage Reference

Portable Calibrator'

----L-

8.8k
·'Sy

I-

10F
1.SIe

5Dk

...-0lil11--....--1<0lil......- .....-+"'\
TEMPERATURE
STABILIZER

OUT'UT

1%

. "f

lOOk

18V--

18011

IN4&l

lM199

19k

1%
B.DSY

oTO

IOV
INPUT

3k

SQUARE WAVE

L..+_--..,;L:::M~"::._~I-.... TRIM

'Warm-up time 10 seconds; intermittent operation does not degrade longierm stablllty_

PreCision Clamp'

14V Reference

II

CLAMP
INPUT

n.
TEMPERATURE
STABILIZER
B.9SY
LM199

....- - - - - -....--OUT'UT

.15V--+-----.

IN914

15k

+

TEMPERATURE

STABILIZER

TEMPERATURE
STABILIZER

&9SV

B.95V

LMI99

lM199

IN914

":" ·Clamp will sink 5 rnA when Input goes more positive than reference

TLlH/5717-5

4-79

Typical Applications (Continued)
OV to 20V Power Reference
Z5V'04DV--~~---~~---------

.

_____"'_______,
LMII5K

TEMPERATURE
STAIILlZER
'.9SV

"'-~I--t--"""tIY--""-:m~:V

LM191

-5V,

Bipolar Output Reference
50k

·'5V--~~---...,

75k

OUTPUT '&.IV

TEMPERATURE
STABILIZER

" .. )

= V. LM324A or
V. LM3S8A
TL/H/6446-S

R = Thin Film Real810r Ne1Work,
±O.05% Matching and 5 ppm Tracking
(Beckman 694-3-R-l0K-A),
(Caddock T-914-10K-l00-0S)
or similar.

4-86

Typical Applications (Continued)
Multiple Output Voltages
y+

y+

_

......-.lL&.1IIIIIV

r--'--,!....~~-

2.511GV

2.7.

TLlHI8446-9
TLlHI8446-10
R = Thin Film Resistor Network
0.05% Malching and 5 ppm Tracking
(Beckman 694-3-R-l0K-A),
(Caddock T-914-10K-l00-05)

or similar.

Reference with Booster

100 mA Boosted Reference
y+;,uv

Y+;'&.DV

3.3
2N28117

1.
j......lIoO.,..!..._-l____....._ vour =
1110-2110

2.500V

~ (OPl101W.

i-a.;..,~_..J

~ PRE-I.OAD)

____....._ vour =

2.50OV

------..1
TLlHI8446-11
TLlHI8446-12

4-88

Typical Applications

(Continued)

Buffered High-Current Reference with Filter
+5.DV

10k

10k

3.3

L---+--I----:I-----1H> VOUy-Z.5DDV
Uk

TL/H/8446-13

Simplified Schematic Diagram
r-----------------~-_9-v+

20
-C>--~-VOUT

10k

1.5k

75k

50k

5pF

50k

!--()-oWII- TRIM

55k

----------~--~~--~----o_-~--_4-----v'Reg. u.S. Pat. Off.

4-87

TL/H/8446-14

!

:5

tflNationat Semiconductor

LM368-5.0 and lM368-10 Precision Voltage References
General Description

Features

The LM368 is a precision. monolithic. temperature-compensated voltage reference. The LM368 makes use of.thin-film
technology enhanced by the discrete laser trimming of resistors to achieve excellent Temperature coefficient
(Tempco) of VOUT (as low as 5ppml'C). along with tight
initial tolerance. (as low as 0.02%). The trim scheme is such
that individual resistors are cut open rather than being
trimmed (partially cut). to avoid resistor drift caused by electromigration in the trimmed area. The LM368 also provides
excellent stability vs. changes in input voltage and output
current (both sourcing and sinking). This device is available
in output voltage options of 5.0V and 10.0V and will operate
in both series or shunt mode. Also see the LM368-2.5 data
sheet for a 2.5V output. The devices are short circuit proof
when sourcing current. A trim pin is made available for fine
trimming of VOUT or for obtaining intermediate values without greatly affecting the Tempco of the device.

•
•
•
•
•
•
•
•
•

300 p,A operating current
Low output impedance
Excellent line regulation (.0001 %IV typical)
Single-supply operation
Externally trimmable
Low temperature coefficient
Operates in series or shunt mode
10.0V or 5.0V
Excellent initial accuracy (0.02% typical)

Connection Diagram
Metal Can Package

He

yTLlH/5522-1

Top View
'case connected to V-

Order Number LM36SYH-10,
LM36SYH-5.0, LM36SH-10, LM36SH-5.0
See NS Package Number HOSC
.

Typical Applications
Series Regulator

Shunt Regulator

13Y-3OV

I~+'-

1 mA·l0mA

l

2
5.000V

TL/H/5522-2

TL/H/5522-3

4·88

Absolute Maximum Ratings

(Note 8)

Input Voltage (Series Mode)

35V

Reverse Current (Shunt Mode)

50 rnA

Power Dissipation
Storage Temperature Range
Operating Temperature Range

- 60'C to + 150'C

Soldering Information
TO-5 (H) Package, 10 sec.
+300'C
See AN-450 "l:)urface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.

600mW

LM368

O'Cto +70'C

Electrical Characteristics (Note 1)
LM368
Parameter

Conditions

Typical

VOUT Error

Load Regulation
(Note 4)

s: VIN s: SOV
o mA s: ISOURCE s: 10 mA
-10 mA s: ISINK s: 0 mA

Thermal Regulation

T = 20 mS (Note 5)

Line Regulation

(VOUT +3V)

Quiescent Current
Change of Quiescent Current vs. VIN

(VOUT +SV)

Temperature Coefficient
of VOUT (see graph): LMS68Y
(Note 6)
LMS68

O'C
O'C

Short Circuit Current

VOUT = 0

Noise:

s: VIN s: SOV

s: TA s: 70'C
s: TA s: 70'C

10.0V: 0.1-10Hz
100Hz -10 kHz
6.2V: 0.1 -10Hz
100Hz -10 kHz
5.0V: 0.1 -10Hz
100Hz -10 kHz

VouTAdjust Range: 10.000V
5.000V

Tested
Limit
(Note 2)

Design
Limit
(Note 3)

±0.02

±0.1

0/0

±0.0001

±0.0005

0/01V

±O.OOOS
±O.OOS

±0.001
±o.o08

%/mA
%/mA

±0.005

±0.Q1

0/0/100 mW

250

S50

p.A

3

5

p.AIV

±11
±15

±20

SO

70

±30
100

SO
1100
20
700
16
575
OV

s: VPIN5 s: VOUT

Units
(Max. unless
noted)

4.5-17.0
4.4-7.0

ppml'C
ppml'C
rnA
uVp-p
nV/.JHz
uVp-p
nV/.JHz
uVp-p
nV/.JHz

6.0-15.5
4.5-6.0

V min.
V min.

Note 1: Unless otherwise noted, these specifications apply: TA = 2S'C, VIN = ISV,ILOAD = 0,0';; CL ,;; 200 pF, CircuH is operating in Series Mode. Or, circuit is
operating in Shunt Mode, VIN = + ISV or VIN = Your, TA = + 2S'C, ILOAD = -1.0 rnA, 0 s: CL ,;; 200 pF.
Note 2: Tested Limits are guaranteed and 100% tested in production.
NOle 3: Design Umlts are guaranteed (but not 100% production tested) over the Indicated temperature and supply voltage ranges. These limits are not used to
calculale outgoing qualHy levels.
Note 4: The LM3B8 has a Class B output, and will exhibit transients at the crossover point. This point occurs when the device is asked to sink approximately
120 ,..A. In some applications it may be advantageous to preload the output to either VIN or Ground, to avoid this crossover point
Note 6: Thermal Regulation is defined as the change in the output Voltage at a time T after a step change in power dissipation of 100 mW.
Note 6: Temperature Coefficient of Vour is defined as the worst case delta·Vour measured at Specified Temperatures divided by the total span of the Specified
Temperature Range (See graphs). There is no guarantee that the Specified Temperatures are exactly at the minimum or maximum deviation.
Note 7: In metal can (H), 8J_C Is 7S'C/W and 8J_A is ISO'C/W.
Note 8: Absolute Maximum Ratings indicate IimHs beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its Rated Operating Conditions (see Note 1 and Conditions).

4-89

Typical Performance Characteristics

. Dropout Voltage VS. Output Current
(Series Mode Sourcing Current)

Quiescent Current VS. Input
Voltage and Temperature

400

..
.-. .......

~

~ ~ I-""

25'C-

~ i-""

~

....

~5~'CI

~
{fl

...

25'C

~

-55'C

... 125;5 ... 10-

~

o

I

40

10
2D
3D.
INPUT VOLTAGE (V)

o

3\.

10

~4

..
~

=
co.

..!.

I"! :III"

l!i
II!
!!!

~

-10

~

I.I1II

0.1

I

~

EO.OOI

I.J'

iil

0.01
lOOk

10

~

~

""

/

I

0.0001
100
lk
10k
Fll£QUENCY(Hz) .

0
GUTPUT CURRENT (mA)

10

100

I
>"

SOURCING

Output Impedance VS. Frequency
(Sinking Current) .

Ripple Rejection VS. Frequency .

iii

~.

10

-1

"

-2

10

~ 0.01

~

0.1

.

OUTPUT CURRENT (mA)

100

g

SINKING

...~
-3
-4

0

Output Impedance VS. Frequency
(Sourcing Current)

...zw

'"I"'"

>"

.!!.

:II

~
=
co

~

o

Output Change VS.
Output Current

E

'

125'C

(Note 1)

31-

.! ....

g

3l~

10

iI

~

~

~

~

0.1

0.01
100

lk
10k lOOk
FREQUENCY (Hz)

1M

10

100
lk
10k
FREQUENCY (Hz)

lOOk.

Temperature Coefficient:
LM368-10 (Curve A)

~ ~
I

I
1'_

--, IT,
:\J. ji
7

i""""

l-17O"':":

,

: I
-55 -40

0

25

7885

125

TEMPERATURE ('C)
Typical Temperature Coefficient Calculations:
TLIH/5522-4

.LM368·Uj (see Curve A)
T.C.=7.7 mVl(70'xl0V)
=11 Xl0E-6=llppm/'C

Output Noise vs. Frequency·

I
I

(1) LM368 alone.

...... ~

(2) with 0.01 ,..1 Mylar. Trim to Gnd.
(3) with Ion in series with 10,..1, VOUT to Gnd.
(4) with Both.

"'"

..... ..JOYI
6V

o

1.

1.
lk
FalEllCY (Hz)

1l1li

TLlH/5522-5

4-90

Typical Applications
Narrow Range Trimmable Regulator (± 1 % min.)

Wide Range Trlmmable Regulator
y+

6.

~
LM368

5

.

r...lL.:.'.!...__...._ vou,

VOUT

2M

HI
20k

4

TL/H/5522-7

TL/H/5522-B

Improved Noise Performance

r ......

-I-!---_-VOUT

Adjustable Zener
y+

1 mA-l0

10""

mAl
TL/H/5522-10

± 10V, ± 5V References
Y+

r..,l,;-,.L---
Reverse Current
LM4040·2.5
LM4040·4.1
LM4040·5.0
LM4040·8.2
LM4040·10.0

+215·C
+ 220·C
+ 260·C

-40"C

s: TA s:

+85·C

60pAt015mA
68".A to 15 mA
74".A to 15 mA
91 ".A to 15 mA
100".A to 15 mA

LM4040-2.5
Electrical Characteristics
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25·C. The grades A and B deSignate initial
Reverse Breakdown Voltage tolerances of ±0.1% and ±0.2%, respectively.

Symbol

VA

lAM IN

I:NA/,H

aVA/alA

Parameter

Reverse Breakdown Voltage

IA = 100".A

Reverse Breakdown Voltage
Tolerance (Note 6)

IA = 100 pA

Units
(Umlt)

±2:5
±'19

±5.0
±21

mV(max)
mV(max)

60
&5

60
&5

".A
jA.A(max)
pA(max)

±100

±100

0.8
1.0

0.8
1.0

mV
mV(max)
mV(max)

6.0
8.0

6.0
8.0

mV
mV(max)
mV(max)

0.8

0.8

.{}(max)

V

45

Average Reverse Breakdown
Voltage Temperature
Coefficient

IA=10mA
IA = 1 mA
IA = 100".A

±20
±15
±15

Reverse Breakdown Voltage
Change with Operating
Current Change

IAMIN

s:

0.3

Reverse Dynamic Impedance

LM4040BIM
LM4040BIM3
LM4040BIZ
Limits
(Note 5)

2.500

Minimum Operating Current

1 mA

ZA

Typical
(Note 4)

Conditions

LM4040AIM
LM4040AIM3
LM4040AIZ
Umlts
(Note 5)

s:

IA

IA

s: 1 mA
s:

15 mA

IA = 1 mA, f = 120 Hz,
lAC = 0.11A

2.5

0.3

ppml"C
ppm/·C (max)
ppml"C

.{}

eN

Wideband Noise

IA = 100".A
10Hz s: f s: 10kHz

35

",Vrms

aVA

Reverse Breakdown Voltage
Long Term Stability

t = 1000 hrs
T = 25·C ±0.1·C
IA = 100".A

120

ppm

4·97

LM4040-2.S

(Continued)

Electrical Characteristics (Continued)
Boldface limits apply forTA = TJ = T MIN to T MAXi all other limits TA = TJ = 25°C. The grades C, D and E designate initial
Reverse Breakdown Voltage tolerances of ±0.5%, ±1.0% and ±2.0%, respectively.
Symbol

VR

IRMIN

Parameter

Conditions

Reverse Breakdown Voltage

IR = 100 /LA

Reverse Breakdown Voltage
Tolerance (Note 6)

IR = 100 /LA

2.500

Minimum Operating Current

±20
±15
±15

IRMIN

1 lilA

ZR

:s: IR :s:
:s: IR :s:

1 mA

15 mA

Reverse Dynamic Impedance IR = 1 mA, f = 120 Hz
lAC = 0.11R

eN

Wideband Noise

AVR

Reverse Breakdown Vollage 1= 1000 hrs
Long Term Stability
T = 25°C ±0.1°C
IR = 100 /LA

IR = 100 /LA
10Hz:S:f:S: 10kHz

Units
(Umlt)

V
±12
±29

±25
±49

±50
±74

mV(max)
mV(max)

60
65

65
70

65
70

/LA
/LA (max)
/LA (max)

±100

±150

±150

0.8
1.0

1,0
1.2

1.0
1.2

mV
mV.(max)
mV(max)

6.0
8.0

8.0
10.0

8.0
10.0

mV
mV(max)
mV(max)

0.9

1.1

1.1

0
O{max)

45

AVR/AT Average Reverse Breakdown IR=10mA
Voltage Temperature
IR = 1 mA
Coefficient
IR = 100 /LA
AVR/AIR Reverse Breakdown Voltage
Change wilh Operating
Current Change

LM4040CIM LM4040DIM LM4040EIM3
LM4040CIM3 LM4040DIM3 LM4040EIZ
Typical
LM4040CIZ LM4040DIZ
(Note 4)
Limits
Limits
Limits
(Note 5)
(Note 5)
(Note 5)

0.4

2.5

0.3

ppml"C
ppm/DC (max)
ppml"C

35

/LVrms

120

ppm

4-98

r

s:

LM4040-4.1

o""'"

""'"

,0

Electrical Characteristics

Boldface limits apply for T A = TJ = T MIN to T MAX: all other limits T A = TJ
Reverse Breakdown Voltage tolerances of ± 0.1 % and ± 0.2%, respectively.

Symbol

VR

IRMIN

AVR/AT

Parameter

Conditions

Reverse Breakdown Voltage

IR

Reverse Breakdown Voltage
Tolerance (Note 6)

IR

=
=

=
=
=

10mA
1 mA
100 /LA

±30
±20
±20

IRMIN ,s; IR ,s; 1 mA

0.5

IR = 1 mA,f
lAC = O.IIR

=

120Hz,

Units
(Limit)

V
±4.1
±31

±8.2
±35

mV(max)
mV(max)

68
73

68
73

/LA
/LA (max)
/LA (max)

±100

±100

0.9
'1.2

0.9
1.2

mV
mV(max)
mV(max)

7.0
10.0

7.0
10.0

mV
mV(max)
mV(max)

1.0

1.0

.n
.n (max)

50

Average Reverse Breakdown Voltage IR
Temperature Coefficient
IR
IR

Reverse Dynamic Impedance

LM4040AIM
LM4040BIM
LM4040AIM3 LM4040BIM3
Typical
LM4040AIZ
LM4040BIZ
(Note 4)
Limits
Limits
(Note 5)
(Note 5)

100 /LA

1 mA,s; IR ,s; 15 mA

ZR

25°C. The grades A and B designate initial

4.096

100 /LA

Minimum Operating Current

AVR/AIR Reverse Breakdown Voltage Change
with Operating Current Change

=

3.0

0.5

ppml"C
ppml"C (max)
ppml"C

eN

Wideband Noise

IR = 100 /LA
10Hz,s; f,s; 10kHz

80

/LVrms

AVR

Reverse Breakdown Voltage Long
Term Stability

t = 1000 hrs
T = 25°C ±O.I°C
IR = 100 /LA

120

ppm

.4-99

"

LM4040-4.1

(Continued)

Electrical Characteristics (Continued)
Boldface limits apply for T A = TJ = T MIN toTMAX; all other limits TA "" TJ ,= 25°C. The grades C and D designate initial
Reverse Breakdown Voltage tolerances of ±0.5% and ±1.0%, respectively.
Symbol

VR

IRMIN

AVR/AT

Parameter

Conditions

Reverse Breakdown Voltage

'IR = 100 ",A

Reverse Breakdown Voltage
Tolerance (Note 6)

IR = 100 ",A

Minimum Operating Current

IRMIN ~ IR ~ 1 mA

1mA~IR~15mA

ZR

Reverse Dynamic Impedance

4.096

IR = 1 inA, f = 120 Hz,
lAC"" 0.11R

±30
±20
±20

Units
(Umlt)

V
±20
±47

±41
±81

mV(max)
mV(max)

68
73

73
78

",A
",A (max)
",A (max)

±100

±150

ppml"C
ppm/DC (max)
ppml"C

0.9
1.2

1.2

1.5

mV
mV(max)
mV(max)

7.0
10.0

9.0
13.0

mV
mV(max)
mV(max)

1.0

1.3

o (max)

50

Average Reverse Breakdown Voltage IR = 10mA
Temperature Coefficient
IR = 1 mA
IR=100",A

AVR/AIR Reverse Breakdown Voltage Change
with Operating Current Change

LM4040CIM LM4040DIM
LM4040CIM3 LM4040DIM3
Typical
LM4040CIZ
LM4040DIZ
(Note 4)
LImits
Limits
(Note 5)
(Note 5)

0.5

3.0

0

0.5

eN

Wideband Noise

IR = 100 ",A
10Hz ~ f ~ 10kHz

80

",Vrrns

AVR

Reverse Breakdown Voltage Long
Term Stability

t = 1000 hrs
T = 25°C ±0.1°C
IR = 100 ",A

120

ppm

LM4040-S.0

Electrical Characteristics
Boldface limits apply for TA = TJ = TMIN to TMAXi all other limits TA = TJ = 25°C. The grades A and B designate initial
Reverse Breakdown Voltage tolerances of ±0.1% and ±0.2%, respectively.

Symbol

VR

IRMIN

!J.VR/!J.T

Parameter

Conditions

Reverse Breakdown Voltage

IR=100"A

Reverse Breakdown Voltage
Tolerance (Note 6)

IR = 100 ",A

Minimum Operating Current

IRMIN :s; IR :s; 1 mA

1 mA:S; IR :s; 15 mA

ZR

Reverse Dynamic Impedance

IR = 1 mA, f = 120 Hz,
lAC = 0.11R

±30
±20
±20

Units
(Limit)

V

5.000
±5.0
±38

±10
±43

mV(max)
mV(max)

74
80

74
80

",A
",A (max)
",A (max)

±100

±100

1.0
1.4

1.0
1.4

mV
mV(max)
mV(max)

8.0
12.0

8.0
12.0

mV
mV(max)
mV(max)

1.1

1.1

fi
fi(max)

54

Average Reverse Breakdown Voltage IR=10mA
Temperature Coefficient
IR = 1 mA
IR = 100 ",A

!J.VR/!J.IR Reverse Breakdown Voltage Change
with Operating Current Change

LM4040AIM LM4040BIM
LM4040AIM3 LM4040BIM3
Typical
LM4040AIZ
LM4040BIZ
(Note 4)
Limits
Limits
(Note 5)
(Note 5)

0.5

3.5

0.5

ppml"C
ppml"C (max)
ppml"C

eN

Wideband Noise

IR = 100 ",A
10Hz:S;f:s; 10kHz

80

",Vrms

!J.VR

Reverse Breakdown Voltage Long
Term Stability

t = 1000 hrs
T = 25°C ±0.1°C
IR = 100 ",A

40

ppm

4·101

LM4040-5.0 (Continued)

Electrical Characteristics

(Continued)
Boldface limits apply for T A = TJ = T MIN to T MAX: all other limits TA = TJ = 25°C. The grades C and 0 designate initial
Reverse Breakdown Voltage tolerances of ±0.5%and ± 1.0%, respectively.

Symbol

VR

IRMIN

AVR/AT

Parameter

Conditions

Reverse Breakdown Voltage

IR = 100 p.A

Reverse Breakdown Voltage
Tolerance (Note 6)

IR = 100 p.A

Minimum Operating Current

IRMIN s; IR s; 1 mA

1 mA s; IR s; 15 mA

ZR

Reverse Dynamic Impedance

IR = 1 mA, f = 120 Hz,
lAC = O.lIR

±30
±20
±20

Units
(Limit)

V

5.000
±25
±58

±50
±99

mV(max)
mV(max)

74
80

79
85

p.A
p.A(max)
p.A(max)

±100

±150

1.0
1.3

1.3
1.8

mV
mV(max)
mV(max)

8.0
12.0

10.0
15.0

mV
mV(max)
mV(max)

1.1

1.5

n
n(max)

54

Average Reverse Breakdown Voltage IR = 10mA
Temperature Coefficient
IR = 1 mA
IR = 100 p.A

AVR/AIR Reverse Breakdown Voltage Change
with Operating Current Change

LM4040CIM LM4040DIM
LM4040CIM3 LM4040DIM3
Typical
LM4040CIZ
LM4040DIZ
(Note 4)
Limits
Limits
(Note 5)
(Note 5)

0.5

3.5

0.5

ppml"C
ppmI"C(max)
ppml"C

eN

Wideband Noise

IR = 100 p.A
10Hzs;fS; 10kHz

80

p.Vrms

AVR

Reverse Breakdown Voltage Long
Term Stability

t = 1000 hrs
T = 25°C ±O.l°C
IR = 100,..A

120

ppm

4-102

LM4040-S.2
Electrical Characteristics
Boldface limits apply for T A = T J = T MIN to T MAX; all other limits T A = TJ
Reverse Breakdown Voltage tolerances of ± 0.1 % and ± 0.2%, respectively.

Symbol

VR

Parameter

Reverse Breakdown Voltage
Reverse Breakdown Voltage
Tolerance (Note 6)

IRMIN

t"vR/AT

Conditions

IR
IR

=
=

Average Reverse Breakdown Voltage IR
Temperature Coefficient
IR
IR

Reverse Dynamic Impedance

LM4040AIM LM4040BIM
LM4040AIM3 LM4040BIM3
LM4040AIZ
LM4040BIZ
Limits
Limits
(NoteS)
(NoteS)

150 /LA

=
=
=

IRMIN

±40
±20
±20

10mA
1 mA
150 /LA

:s: IR :s:
:s:

IR

:s:

IR = 1 mA, f
lAC = 0.11R

1 mA

15 mA

=

120 Hz,

Units
(Limit)

V
±8.2
±61

±16
±70

mV(max)
mV(max)

91

91

95

95

/LA
/LA (max)
/LA (max)

±100

±100

ppml'C
ppml'C (max)
ppml'C

1.3

1.3

2.5

2.5

mV
mV(max)
mV(max)

10.0
18.0

10.0
18.0

mV
mV(max)
mV(max)

1.5

1.5

n
n(max)

67

1 mA

ZR

Typical
(Note 4)

25'C. The grades A and B deSignate initial

8.192

150 /LA

Minimum Operating Current

AVR/AIR Reverse Breakdown Voltage Change
with Operating Current Change

=

0.6.

7.0

0.6

eN

Wideband Noise

IR = 150 /LA
10Hz:S:f:S: 10kHz

130

/LVrms

AVR

Reverse Breakdown Voltage Long
Term Stability

t = 1000 hrs
T = 25'C ±0.1'C
IR = 150 /LA

120

ppm

4-103

LM4040-8.2 (Continued)

Electrical Characteristics

(Continued)
Boldface limits apply for TA ',= TJ = TMIN to TMAXi all other limits TA = TJ = 25°C. The grades C and 0 designate initial
Reverse Breakdown Voltage tolerances of ±0.5% and ±1.0%, respectively.

Symbol

VR

IRMIN

/iVA/liT

Parameter

Conditions

Reverse Breakdown Voltage

IR= 150,...A

Reverse Breakdown Voltage
Tolerance (Note 6)

IR = 150,...A

Minimum Operating Current

Average Reverse Breakdown Voltage IR=10mA
Temperature Coefficient
IR = 1 mA
IR=150,...A

1 mA~ IR ~ 15mA

eN
/iVR

Reverse DYnamic Impedance
Wideband Noise
Reverse Breakdown Voltage Long
Term Stability

8.192

IR = 1 mA, f = 120 Hz,
lAC = 0.11R

±40
±20
±20

Units
(Umlt)"

V
±41
±84

±82
±182

mV(max)
mV(max)

91

95

96
100

,...A
,...A(max)
p.A(max)

±100

±1S0

1.3
2.5

1.7
3.0

10.0
18.0

15.0
24.0

mV
mV(max)
mV(max)

1.5

1.9

n
n(max)

67

/iVR//iIR Reverse Breakdown Voltage Change 'IRMIN'~ IR ~ 1 mA
with Operating Current Change

ZR

LM4040CIM LM4040DIM
LM4040CIM3 LM4040DIM3
Typical
LM4040CIZ
LM4040DIZ
(Note 4)
Umlts
Limits
(Note 5)
(Note 5)

0.6

7.0

0.6

ppm/DC '
ppm/DC (max)
ppml"C
mV
, mV(max)
mV(max)

IR = 150,...A
10 Hz ~ f ~ 10 kHz

130

""Vrms

t = 1000 hrs
T = 25°C ±0.1°C
IR = 150,...A

120

ppm

4-104

LM4040-10.0

Electrical Characteristics
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. The grades A and B designate initial
Reverse Breakdown Voltage tolerances of ±0.1 % and ±0.2%, respectively.

Symbol

VR

IRMIN

/:;'vR/AT

Parameter

Conditions

Reverse Breakdown Voltage

IR = 150p.A

Reverse Breakdown Voltage
Tolerance (Note 6)

IR = 150p.A

Minimum Operating Current

IRMIN :S: IR :S: 1 mA

1 mA:S: IR :S: 15 mA

ZR

Reverse Dynamic Impedance

LM4040AIM LM4040BIM
LM4040AIM3 lM4040BIM3
LM4040AIZ
LM4040BIZ
Limits
Limits
(NoteS)
(Note S)

10.00

IR = 1 mA,f= 120Hz,
lAC = 0.11R

±40
±20
±20

Units
(Limit)

V
±10
±75

±20
±85

mV(max)
mV(max)

100
103

100
103

p.A
p.A(max)
p.A(max)

±100

±100

1.5
3.5

1.6
3.5

mV
mV(max)
mV(max)

12.0
23.0

12.0
23.0

mV
mV(max)
mV(max)

1.7

1.7

n
n(max)

75

Average Reverse Breakdown Voltage IR=10mA
Temperature Coefficient
IR = 1 mA
IR = 150p.A

AVR/AIR Reverse Breakdown Voltage Change
with Operating Current Change

Typical
(Note 4)

0.8

8.0

0.7

ppmrc
ppmrC(max)
ppmrc

eN

Wideband Noise

IR = 150p.A
10Hz:s: f:S: 10kHz

180

p.Vrms

AVR

Reverse Breakdown Voltage Long
Term Stability

t = 1000 hrs
T = 25°C ±0.1°C
IR = 150p.A

120

ppm

.

4-105

II

LM4040-10.0 (Continued)

"

.,

Electrical Characteristics

(Continued)
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25'C. The grades C and.D designate initial
Reverse Breakdown Voltage tolerances of ±0.5% and ±1.0%, respectively.

Sym~ol

Parameter

Conditions

.'

Typical
(Note 4)

"

VR

Reverse Breakdown Voltage
Reverse Breakdown Voltage

IR
IR

=
=

!J.VR/!J.T

150 /-LA

Minimum Operating Current

Average Reverse Breakdown Voltage

IR=10mA

Temperature Coefficient

IR

Reverse Breakdown Voltage Change

=
=

1 mA

±,20

150 p.A

±20

IRMIN ~ IR ~ 1 mA

0.8

1mA~IR~15mA

eN

Reverse Dynamic Impedance

Wideband Noise

= 1 mA,f =
lAC = 0.11R
IR = 150/-LA

IR

120Hz,

10Hz~f~ 10kHz

!J.VR

LM4040DIZ

Limits

Limits

(Note 5)

(Note 5)

Units
(Limit)

V
±50'

±100

mV(max)

±115

±198

mV(max)

100

110

p.A(max)

103

113

= 1000 hrs
= 25'C ±0.1'C
IR = 150 p.A

Reverse Breakdown Voltage Long

t

Term Stability

T

/-LA
p.A(max)

±40

with Operating Current Change

ZR

LM4040CIZ

75

IR
!J.VR/!J.IR

LM4040DIM
LM4040DIM3

10.00

150 /-LA

Tolerance (Note 6)
IRMIN

LM4040CIM
LM4040CIM3

,ppmrc
±100

±150,

ppmrC(max)
ppmrc
mv

1.5

2.0

mV(max)

3.5

4.0

mV(max)

12.0

18.0

mV(max)

23.0

29.0

8.0

mV

0.7

mV(max)
n

"

1.7

2.3

n(max)

180

p.Vrm•

120

ppm

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specHic performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), 9JA Ounction to
ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature Is POmax = (TJmax - Tp)1 9JA or the
number given in the Absolute Maximum Ratings, whichever is lower. For the LM4040, TJmax = 12S"C, and the typical thermal resistance (9JA), when board
mounted, is 18S"C/W for the M package, 326"C/W for the SOT·23 package, and 180"C/W with 0.4" lead length and 17O"C/W with 0.12S" lead length for the
T0-92 package.
Note 3: The human body model Is a 100 pF capaCitor discharged through a I.S kG resistor into each pin. The machine model Is a 200 pF capacHor discharged
directly into each pin.
Note 4: Typicals are at TJ

= 2S"C and represent most likely parametriC norm.

Note 5: Limits are 100% production tested at 2S"C. Limits over temperature are guaranteed through correlation using Statistical Quality Control (SOC) methods.
The limits are used to calculate National's AOQL.
Note 6: The boldface (over·temperature) limit for Reverse Breakdown Voltage Tolerance is defined as the room temperature Reverse Breakdown Voltage
Tolerance ± [(I\. VAl I\.n(6S"C)(VA)J. I\.VAl I\. T is the VA temperature coefficient, 6S"C is the temperature range from -40"C to the reference point of 2S"C, and VA
is the reverse breakdown voltage. The total over·temperature tolerance for the different grades is shown below:
A.grade: ±0.7S% = ±0.1% ±100 ppml"C X 6S"C
B.grade: ±0.85% = ±0.2% ±100 ppml"C X 6S"C
C-grade: ±1.15% = ±O.S% ±100 ppm/"C X 6S"C
D-grade: ± 1.98% = ± 1.0% ± 150 ppm/"C X 6S"C
E.grade: ±2.98% = ±2.0% ±IS0 ppm/"C X 6S"C
Therefore, as an example, the A·grade LM4040·2.S has an over·temperature Reverse Breakdown Voltage tolerance of ±2.SV X 0.75%

4-106

=

±19 mV.

Typical Performance Characteristics
Temperature Drift for Different
Average Temperature Coefficient

+0.5
+0.4
+0.3
~

!Ill

Output Impedance va Frequency

lk~~~~~~~~--~,

lR= 150pA

+0.2

::: +0.1

'"~

0
i3 -0.1
>"" -0.2

'" ""'"

..........

--

.

100

........ ~

-0.3

-

-- --

~

"

-22 ppml'°C

:-.......

"
----

-51 ppmi'°C

-0.4

./

0

20

40

60

<.>
:z:

10

"'...a.."

'--

/'

~

-0.5
-40 -20

S...

/+12ppm/oC

C>

<"1

""

80

0.1

100

L.....J...LJ.LIWI....J....LJ.LWJL.....J...LJ.LLWL....J..LWIW

100

lk

TEMPERATURE (OC)

10k

1M

rOOk

fREQUENCY (Hz)
TL/H/11323-4

TLlH/11323-10

Reverse Characteristics and
Minimum Operating Current

Output Impedance vs Frequency

lk~~.-=<=r-----.----,

120

"<
-3

100

......
'"
...'"
...'"~

S...
<.>
:z:

...a..~

....

~ ~~ l~:

100

\tI.y.\~

80

G\),e.te.~~ S~\\\.,.
."

-)0"'.

;,lc. ,.~"

>
0

:z:

10

:0

<.>
VI

.<"1

'"

0.1

60
40

lk

10k'

lOOk

J

0

L-J...LJ.IJLWL....J..LLWIIL-J...LJ.IJLWL....J..LWIW

100

(

20

0

1M

2

4

6

8

10

REVERSE VOLTAGE (v)

. fREQUENCY (Hz)

TL/H/11323-12

TLlH/11323-11

Noise Voltage vs Frequency

~......
>
-3
...
VI

i5

10

rR~

5.0

TJ - 25 O C=

"'2.0

"'-

1.0

.....

vR -

10V

-

5V-

~

2.5V

0.5

:z:

II

-

0.2
0.1
1

10

100

lk

fREQUENCY (Hz)

4·107

10k

lOOk
TL/H/11323-13

C)

"II'

~

r--------------------------------------------------------------------------------,
Start-Up Characteristics

:E
...I

.

Rs

,... 0."" ,~ .:=i?Ir'04-0-f
....--VT}"""":'TL/H/11323-5

LM4040·2.S

Rs = 30k

sl---+-+-+--+-r.--+-f--t--t--;

~

0 f--I--t--+--+--f--+--I----t--+--I

z

->
3

1+H+t+-H+/+++t-I++-H+i1++
AfH-t+t++++I+H+t+-H+/++++t

21--I---I--I---II--+-~I--I--I--I--f

. >'"

...................................... .

01--+--1--1--1--1--1--1--1-'--+--1
20

40

60

80

RESPONSE TIME (po)

LM4040·S.0

RS

=

30k

TlIH/11323-7

LM404Q-10.0

Rs = 30k

~
z°I-+-f-+-f--f--f-+---"I-+--1
->

41--I--I--I---JI--I--I--I--II--I--f

~2
~

.... ~

o

10r--r-r--r--~~--f-~--~-r~

W
........... .
100

200

"> s
~ o ....

II

~

300

400

~.

o

RESPONSE TIME (po)

100

200

300

400

RESPONSE TIME (po)
TL/H/11323-B

TL/H/11323-9

4-108

r-----------------------------------------------------------------------------~r

s::
-'lao

Functional Block Diagram

o
-'lao
o

r---~~----~~--~----------~~--_o+

TUH/11323-14

Applications Information
The LM4040 is a precision micro-power curvature-corrected
bandgap shunt voltage reference. For space critical applications, the LM4040 is available in the sub-miniature SOT-23
surface-mount package. The LM4040 has been designed
for stable operation without the need of an external capacitor connected between the "+" pin and the "-" pin. If,
however, a bypass capacitor is used, the LM4040 remains
stable. Reducing deSign effort is the availability of several
fixed reverse breakdown voltages: 2.500V, 4.096V, 5.000V,
8.192V, and 10.000V. The minimum operating current increases from 60 p.A for the LM4040-2.5 to 100 p.A for the
LM4040-10.0. All versions have a maximum operating current of 15 mAo

enough to supply at least the minimum acceptable la to the
LM4040 even when the supply voltage is at its minimum and
the load current is at its maximum value. When the supply
voltage is at its maximum and Il is at its minimum, Rs
should be large enough so that the current flowing through
the LM4040 is less than 15 mA.
Rs is determined by the supply voltage, (Vs), the load and
operating cumint, (Il and la), and the LM4040's rovorso
breakdown voltage, YR.
Rs = Vs - VR
Il + la

Typical Applications

LM4040s in the SOT-23 packages have a parasitic Schottky
diode between pin 3 (-) and pin 1 (Die attach interface
contact). Therefore, pin 1 of the SOT-23 package must be
left floating or connected to pin 3.
The 4.096V version allows single +5V 12-bit ADCs or
DACs to operate with an LSB equal to 1 mY. For 12-bit
ADCs or DACs that operate on supplies of 10V or greater,
the 8.192V version gives 2 mV per LSB.
In a conventional shunt regulator application (Figure 1), an
external series resistor (Rs) is connected between the supply voltage and the LM4040. Rs determines the current,that
flows through the load (ILl and the LM4040 (la). Since load
current and supply voltage may vary, Rs should be small

TLlH/11323-15

FIGURE 1. Shunt Regulator

4-109

~
...

Typical Applications (Continued)

:::&

.....

OVee

VIN

ADC12451
10
23

11
20

19
18

17
16

15
14
13

Cs

12-bit

RD

+

iii

Sign

+5V
AVec
• +
,IIOI'F

8p,s

S/H
OB7/0812

Analog-

086/0812

to-

085/0812

Digital

084/0812

909n

lM4040-4.1

Converter

AGNO

083/0811
12

OGNO

082/0810
081/089

V·

OBO/088
elKIN

EOC

22

5

.

iNr

.:E 1O I'F,

21

J'U"lIU""
3.5 MHz

··Ceramic monolithic
-Tantalum

FIGURE 2. LM404o·4.1's Nominal 4.096 breakdown voltage gives ADC124511 mV/LSB

Tl/H/I1323-16

+15V

IN4148

IN4148

15kn

IN4148

15kn'IN4148

-15V

:>--------------~--o~m

-15V

TUH/I1323-17

FIGURE 3. Bounded amplifier reduces saturation·lnduced delays and can prevent succeeding stage damage.
Nominal clamping voltage Is ± 11.5V (LM404o's reverse breakdown voltage + 2 diode VF).

4·110

r-------------------------------------------------------------------------~--,

r

5:

Typical Applications (Continued)

"'"
Q

"'"

Q

10kn

0.1 )JF

.:::r:.

02

-5V

01 - 06 = lN914

04

470n

5kn
-5V

+5V
5kn
06

TL/H/11323-18

FIGURE 4. Protecting Op Amp input. The bounding voltage is ± 4V with the LM4040·2.5
(LM4040's reverse breakdown voltage + 3 diode VF).

+5V ±5%

....LM4040-4.1

....- - - - - - - - - - - o + 4 . 0 9 6 V
47kn,O.1%
47 kn, 0.1%

>--....-o-4.096V

-5V

FIGURE 5. Precision

±4.096V Reference

4-111

TL/H/11323-19

C)

g

~,

r---~----------------------------------------------------------------------------,

Typical Applications (Continued)

...I
12V
30k

12

AoUT

LF13006
LF13007

DIGITAL
CONTROL

LM4040-2.S

+12V

2
INPUT

0.1 ).IF

ANA
GND

...rl

16

7
1/2LMC6062

DUAL
OP-AMP 3

~~---AJ'Iv---+! lOUT
249Sl,O.S%

I
_ 2.5V [ ___
1 __ ]
OllT - 2490 gain set "
TLlH/11323-20

FIGURE 6. Programmable Current Source

LM4040-2.5

12V
LM4040-2.5

lOUT·

-1.0V TO -12V

R2

--+--W""".....

--....:;·~.....

'lollT

= 2.5V
R2

-15V
TL/H/11323-21

FIGURE 7. Precision 1 p.A to 1 mA Current Sources

4-112

TL/H/11323-22

tflNational Semiconductor

LM4041
Precisiol1 Micropower Shullt VoUage Reierel1ce
II Reverse breakdown voltage options of 1.225V and

General Description
Ideal for space critical applications, the LM4041 precision
voltage reference is available in the sub-miniature (3 mm x
1.3 mm) SOT-23 surface-mount package. The LM4041's
advanced design eliminates the need for an external stabilizing capacitor while ensuring stability with any capacitive
load, thus making the LM4041 easy to use. Further reducing
deSign effort is the availability of a fixed (1.225V) and adjustable reverse breakdown voltage. The minimum operating
current is 60 p.A for the LM4041-1.2 and the LM4041-ADJ.
Both versions have a maximum operating current of 12 rnA.
The LM4041 utilizes fuse and zener-zap reverse breakdown
or reference voltage trim during wafer sort to ensure that the
prime parts have an accuracy of better than ± 0.1 %
(A grade) at 25°C. Bandgap reference temperature drift curvature correction and low dynamic impedance ensure stable
reverse breakdown voltage accuracy over a wide range of
operating temperatures and currents.

adjustable
II Contact National Semiconductor Analog Marketing for

parts with extended temperature range

Key Specifications (LM4041-1.2)
± 0.1 % (max)
20 p.V rms (typ)
60 p.A to 12 rnA
-40°C to +85°C
100 ppml"C (max)

II Output voltage tolerance (A grade, 25°C)
II Low output noise (10 Hz to 10 kHz)
II Wide operating current range
II Industrial temperature range
II Low temperature coefficient

Applications
II Portable, Battery-Powered Equipment
II Data Acquisition Systems
II Instrumentation
II Process Control
III

Energy Management

II Product Testing

Features

III

II Small packages: SOT-23, TO-92, and SO-8

Automotive

II Precision Audio Components

II No output capacitor required
II Tolerates capacitive loads

Connection Diagrams

:ID

50-8

SOT-23

NCffiS+ NCmS

':~-

1.2V

ADJ

TL/H/11392-1

7 He
+

NC 2

7 Ne

HC 2

NC 3

6 Ne

He 3

6 HC

_ 4

5 Ne

_ 4

5 FB

TLlH/11392-40

"This pin must be left floating or
connected to pin 3.

1.2V

ADJ
TLlH/11392-2

Top View

Top View

See NS Package Number M03B
(JEDEC Registration TO-236AB)

See NS Package Number M08A

TO-92
FB

NC

8

@)

1.2V

ADJ
TLlH/11392-3

Bottom View
See NS Package Number Z03A

4-113

TL/H/11392-32

TLlH/11392-31

Ordering Information
Reverse Breakdown
Voltage Tolerance at 25'C
and Average Reverse Breakdown
Voltage Temperature Coefficient

M3(SOT-23)

± 0.1 %, 100 ppml'C max (A grade)

LM4041AIM3-1.2

LM4041 AIZ-l.2

LM4041AIM-l.2

See NS Package
Number M03B

See NS Package
NumberZ03A

See NS Package
Number M08A

LM4041 BIM3-1.2

LM4041BIZ-l.2

LM4041BIM-l.2

See NS Package
Number M03B

See NS Package
NumberZ03A

See NS Package
Number M08A

LM4041 CIM3-1.2
LM4041 CI M3-AOJ

LM4041 CIZ-l.2,
LM4041 CIZ-AOJ

LM4041CIM-l.2,
LM4041 CIM-AOJ

See NS Package
Number M03B

See NS Package
NumberZ03A

See NS Package
Number M08A

LM4041DIM3-1.2
LM4041DIM3-AOJ

LM4041DIZ-l.2,
LM4041DIZ-AOJ

LM4041DIM-l.2,
LM4041DIM-AOJ

See NS Package
Number M03B

See NS Package
NumberZ03A

See NS Package
Number M08A

LM4041 EI M3-1.2

LM4041EIZ-l.2

See NS Package
Number M03B

See NS Package
NumberZ03A

± 0.2%, 100 ppm/'C

ma~

(B grade)

± 0.5%, 100 ppml'C max (C grade)

± 1.0%, 150 p'pm/'C max (0 grade)

± 2.0%, 150 ppml'C max (E grade)

Package
Z(TO-92)

M (50-8)

SOT-23 Package Marking Information
Only three fields of marking are possible on the SOT-23's small surface. This table gives the meaning of the three fields.
Part Marking
R1A
R1B
R1C
R1D
R1E
RAC
RAO

Field Definition
First Field:
R = Reference
Second Field:
1 = 1.225V Voltage Option
A = Adjustable
Third Field:
A-E = Initial Reverse Breakdown
Voltage or Reference Voltage Tolerance
A = ±O.l%, B = ±0.2%, C"; ±0.5%,0 = ±1.0%, E

4-114

= ±2.0%

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

ESD Susceptibility
Human Body Model (Note 3)
Machine Model (Note 3)

Reverse Current

20mA

Forward Current

10mA

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

Maximum Output Voltage
(LM4041-ADJ)
Power Dissipation (TA
MPackage
M3 Package
Z Package

=

15V

Operating Ratings (Notes 1 & 2)

25°C) (Note 2)

Storage Temperature

Temperature Range
(Tmin';; TA';; Tmax)

540mW
306mW
550mW

-40°C,;; TA ,;; +85°C

Reverse Current
LM4041-1.2
LM4041-ADJ

- 65°C to + 150°C

Lead Temperature
M and M3 Packages
Vapor phase (60 seconds)
Infrared (15 seconds)
Z Package
Soldering (10 seconds)

2kV
200V

60 J-LAto 12mA
60 J-LA to 12 mA

Output Voltage Range
LM4041-ADJ

+215°C
+ 220°C

1.24Vto 10V

+ 260°C

LM4041·1.2
Electrical Characteristics

Boldface limits apply for TA = T J = TMIN to TMAX; all other limits T A = TJ
Reverse Breakdown Voltage tolerances of ± 0.1 % and ± 0.2%, respectively.

Symbol

VR

IRMIN

IlVR/IlT

IlVR/ IlIR

Parameter

Conditions

Reverse Breakdown Voltage

IR

Reverse Breakdown Voltage
Tolerance (Note 6)

IR

=
=

100J-LA

Minimum Operating Current

LM4041BIM
LM4041BIM3
LM4041BIZ
limits
(Note 5)

Units
(Limit)

±1.2
±9.2

±2.4
±10.4

mV(max)
mV(max)

60

60

65

65

J-LA
J-LA(max)
J-LA(max)

±100

±100

1.5
2.0

1.5
2.0

mV
mV(max)
mV(max)

6.0
8.0

6.0
8.0

mV
mV(max)
mV(max)

1.5

1.5

!1
!1 (max)

V

45

=
=
=

Average Reverse Breakdown
Voltage Temperature
Coefficient

IR
IR
IR

10mA
1 mA
100J-LA

±20
±15
±15

Reverse Breakdown Voltage
Change with Operating
Current Change

IRMIN ,;; IR ,;; 1 mA

0.7

Reverse Dynamic Impedance

LM4041AIM
LM4041AIM3
LM4041AIZ
Limits
(Note 5)

1.225

100J-LA

1 mA ,;; IR ,;; 12 mA

ZR

Typical
(Note 4)

= 25°C. The grades A and B designate initial

IR

= 1 mA, f =
= 0.11R
= 100J-LA

120 Hz,

4.0

0.5

lAC
eN

Wide band Noise

IR
10Hz';; f,;; 10kHz

IlVR

Reverse Breakdown Voltage
Long Term Stability

t = 1000 hrs
T = 25°C ±0.1°C
IR

=

100J-LA

4-115

ppml"C
ppml"C (max)
ppml"C

20

J-LV,ms

120

ppm

LM4041-1.2 (Continuedt
Electrical Characteristics (Continued)
Boldface limits apply for T A = T" = T.IN to T.AXI all other limits TA = TJ = 25'C. The grades C, D and E designate
initial Reverse Breakdown Voltage tolerances of ±0.5%, ±1.0% and :j:2.0%, respectively.

Symbol

VR

IRMIN

Parameter

LM4041CIM LM4041DIM LM4041EIM3
LM4041CIM3 LM4041DIM3 LM4041EIZ
Typical
LM4041CIZ LM4041DIZ
(Note 4)
Limits
Limits
Limits
(Note 5)
(Note 5)
(Note 5)

Conditions

Reverse Breakdown Voltage

'R = .100 /LA

Reverse Breakdown Voltage
Tolerance (Note 6)

IR=10~/LA

1.225

Minimum Operating Current

IiVR/IiIR Reverse Breakdown Voltage
Change with Operating.
Current Change

IR = 1 mA
IR=100/LA

±20
±15
±15

IRMIN ,;; IR ,;; 1 mA

0.7

1 mA ,;; 'R ,;; 12 mA

ZR

V
±12

±25

±14

±24

±36

60

65

65

65

70

70

±100

±150

±150

ppml'C
ppml'C (max)
ppml'C

1.5

2.0

2.0

2.0

25

2.5

mV
mV(max)
mv(max)

6.0

8.0

8.0

8.0

10.0

10.0

mV
mV(max)
mV(max)

1.5

2.0

2.0

0
O(max)

2.5

Reverse Dynamic Impedance IR = 1 mA, f = 120 Hz
. lAC = 0.11R

eN

Wideband Noise

IiVR

Reverse Breakdown Voltage t = 1000 hrs
Long Term Stability
T = 25'C ±0.1'C
IR = 100 /LA

IR = 100/LA
10Hz';; f,;; 10kHz

Units
(Limit)

±6
45

t:NR/IiT Average Reverse Breakdown IR=10mA
Voltage Temperature
Coefficient

.,

0.5

mV(max)
mV(max)
/LA
/LA (max)
/LA (max)

.

20

/LVrms

120

ppm

LM4041-ADJ (Adjustable)
Electrical Characteristics
Boldface limits apply for TA = T" = T.IN to T.AXi all other limits TJ = 25'C unless otherwise specified (SOT-23, see Note
7), IRMIN ,;; IR ,;; 12 mA, VREF ,;; VOUT ,;; 10V. The grades C and D designates initial Reference Voltage Tolerances of ±0.5% and
± 1%, respectively for VOUT = 5V.

Symbol

VREF

IRMIN

Conditions

Typical
(Note 4)

Reference Voltage

IR = 100 /LA, VOUT = 5V

1.233

Ref!3rence Voltage
Tolerance (Note 8)

IR = 100 /LA, VOUT = 5V

Parameter

.

Minimum Operating Current

LM4041CIM
LM4041CIM3
LM4041CIZ

(Note 5)

LM4041DIM
LM4041DIM3
LM4041DIZ
(Note 5)

±6.2

±12

±14

±24

60

65

65

70

V
mV(max)
mV(max)

,..A

45

4-116

Units
(Limit)

/LA (max)
,..A (max)

LM4041-ADJ (Adjustable) (Continued)
Electrical Characteristics (Continued)
Boldface limits appl, for TA

= T.. = T.IN to T.AX; all other limits T J = 25'C unless otherwise specified (SOT-23, see
Note 7), IRMIN :;;: IR :;;: 12 mA, VREF :;;: VOUT :;;: 10V. The grades C and 0 designates initial Reference Voltage Tolerances of
±0.5% and ± 1 %, respectively for VOUT = 5V.
LM4041CIM
Symbol

aVREF/alR

Parameter

Typical

Conditions

Reference Voltage

IRMIN :;;: IR :;;: 1 mA

Change with Operating

SOT-23: VOUT

<:

(Note 4)

1 mA:;;: IR :;;: 12 mA

aVREF/aVO Reference Voltage Change

<:

aVREF/aT

ZOUT

(NoteS)

(Note 5)

1.5

2.0

mV(max)

2.0

2.5

mV(max)

mV

mV

1.6V (Note 7)

4

6

mV(max)

6

8

mV(max)

-2.0

-2.5

mVIV(max)

-2.5

-3.0

mVIV(max)

100

150

nA{max)

120

200

nA(max)

±100

±150

ppml'C (max)

-1.3

IR = 1 mA

Feedback Current

Average Reference Voltage

LM4041DIZ

2

with Output Voltage Change

IFB

Units
(Limit)

LM4041CIZ

0.7

1.6V (Note 7)

Current Change

SOT-23: VOUT

LM4041DIM

LM4041CIM3 LM4041DIM3

mVIV

60

nA

IR =

10mA

20

Temperature Coefficient

IR =

1 mA

15

(Note B)

IR=100j.LA

15

ppml'C

0.3
2

n
n

20

j.LVrms

120

ppm

Dynamic Output Impedance

VOUT = 5V,

ppml'C

IR = 1 mA, f = 120 Hz,
lAC = 0.11R
VOUT = VREF
VOUT = 10V

eN

aVREF

Wideband Noise

IR = 100j.LA
VOUT = VREF
10Hz:;;: f:;;: 10kHz

Reference Voltage Long

t = 1000 hrs, IR = 100 j.LA

Term Stability

T = 25'C ±0.1'C

Nole 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee speCific performance limits. For guaranteed specifications and test conditions. see the Electrical Characteristics. The guaranteed
specHications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), 8 JA (junction to
ambient thermal resistance), and TA (ambient tempeniture). The maximum allowable power dissipation at any temperature is POmax = (TJmax ~ TAJI6JA or the
number given in the Absolute Maximum Ratings. whichever is lower. For the LM4041, TJmax = 12S'C, and the typical thermal resistance (6JAJ, when board
mounted, is 18S'C/W for the M package, 326"C/W for the SOT-23 package, and 180"C/W with 0.4" lead length and 170'C/W with 0.12S" lead length for the
T()'92 package.
Nate 3: The human body model is a 100 pF capacitor discharged through a I.S kll resistor into each pin. The machine model is a 200 pF capaCitor discharged
directly into each pin.
Note 4: Typicals are at TJ = 25°C and represent most likely parametric norm.

Nole 5: Limits are 100% production tested at 2S·C. Limits over temperature are guaranteed through correlation using Statistical Ouality Control (SOC) methods.
The limits are used to calculate National's AOOL.
Nole 6: The boldface (over-temperature) limit for Reverse Breakdown Voltage Tolerance is defined as the room temperature Reverse Breakdown Voltage
Tolerance ± [(~VRI ~n(6S·C)(VR»). ~ VRI ~ T is the VR temperature coefficient, 6S'C is the temperature range from -40"C to the reference pOint of 2S'C, and VR
is the reverse breakdown voltage. The total over-temperature tolerance for the different grades is shown below:
A-grade: ±0.7S% = ±0.1% ±100 ppml"C X 6S'C
B-grade: ±0.8S% = ±0.2% ±100 ppml"C x 6S'C
C·grade: ±1.15% = ±O.S% ±100 ppml"C x 6S'C
O-grede: ±1.98% = ±1.0% ±IS0 ppm/'C x 6S'C
E-grade: ±2.98% = ±2.0% ±IS0 ppml"C X 6S'C
Therefore, as an example, the A·grade LM4041·1.2 has an over-temperature Reverse Breakdown Voltage tolerance of ±1.2V X 0.7S% = ±9.2 mV.
Nate 7. When VOUT ,;; 1.6V, the LM4041-ADJ in the SOT-23 package must operate at reduced IR. This is caused by the series resistance of the die attach
between the die (-) output and the package H output pin. See the Output Saturation (SOT-23 only) curve in the Typical Performance Characteristics section.
Nole 8. Reference voltage and temperature coefficient will change with output voltage. See Typical Performance Characteristics curves.

4-117

II

....
..,.
~

:IE

Typical Performance Characteristics

....I

Temperature Drift for Different
. Average Temperature Coefficient
+0.5
+0.4
+0.3

'" .....

~ +0.2

-:;

Output Impedance vii FreqUenCy :

lk

.

,

'R = 150 pA
LM4041-1.2

+0. r I'-...

~

-

s...

-

/+12 ppm/DC

.........

_0
~ -0.1
>'" ':'0.2

,

I'~

.• :...
........ :-- .
~

u
:z

'"---- -

....:--+-----,,.."'----1

100

.........

0.1

0

20

40

60

80

100

L....J....LJ.IWL....l.J.J.W.III-L.U.WIIL-l.J.J.LL1IU

100

lk

TEt.tPERATURE (OC)

10k

TL/H/11392-19

TL/H/11392-4

Reverse Chara~terlstlcs and
Minimum Operating Current

Noise Voltage
1000

.~
..5

I:!

600

\

:z

200

"<..3

80

:z

60

......
...
......>

.
400

o

100

'R=200 I'A
TJ =25 O C
LM4041-1.2
LII4041-ADJ: VotJT = VREF

800
.~

II<
II<

::>

u

\

III
II<
II<

o
1

10

100

lk

10k

40

~

20

o

TJ=25°~

V

o

lOOk

Typical

/

FREQUENCY (Hz)

0.4

LII4041-1.2

0.8

1.2

1.6

5

>-

0

z

1.5

~

1.0

~

0.5

TLlH/11392-9

I

Rs,30k

TJ =25 0 C
Rs=30k
LIoI4041-1.2

rl

V,N
1 Hz rat.

\
TL/H/I1392-8 ..

i'.

0

o

8

2.0

. REVERSE VOLTAGE (V) .
TL/H/11392-5

~

114

lOOk

FREQUENCY (Hz)

12

16

REsPONSE TIME (ps>,
TL/H/11392-7

4·118

Typical Performance Characteristics

(Continued)
Reference Voltage vs Temperature
and Output Voltage

Reference Voltage vs Output
Voltage and Temperature
1.244
1.240

...
...'"""

~

1.236

~!~OC
25°C

-40~ ~,

0

...

,

1.232

u

i:'i 1.228
'"

...

-40°C
~ ~.

1.220

o

...
...

1.232

VOUT=VRE

VOUT =5V

u

'i

z

~

~

85°~

1.224

I-"

1.236

>

'"

--

LM4041-ADJ
IR=1 mA

1.240

'"""
:;
0

.

...~
'"

~

"'111

I-

>

1.244

LM4041-AOJ

1.228

VOUT =10V

1.224

r-

1.220
-40 -20

10

4

2

0

20

40

--

60

80

100

TEMPERATURE (Oc)

OUTPUT VOLTAGE (V)
TUH/11392-11

TL/H/11392-10

Feedback Current vs Output
Voltage and Temperature

Output Saturation
(SOT-23 Only)
1.7
1.6

80~~+---+---4---~--~

~
z
0
;::

60r---~--~~~~--~---;

1.5

""=>
'"

1.4

""en

1.3

I-

40r---~---+----r---~---;

l-

=>

0l-

1.2

=>

20r---~---+----r---~---;

0

1.1

O~--~--~--~--~-----'

o

4

2

2:

10

4

8

OUTPUT VOLTAGE (V)

Output Impedance vs Frequency

Output Impedance vs Frequency
lk

lk

100

z

8""
0-

12
TLlH/11392-33

TL/H/11392-12

S...
u

10

OUTPUT CURRENT (mA)

s...
u

z

10

8""
0-

II

100

10

::!!

::!!

0.1

L......L..J...1.I.lllIJ.......L.J...LLUJll....l...UJlllU.....J...llU.UlI

100

lk

10k

lOOk

1M
fREQUENCY (Hz)

fREQUENCY (Hz)

TL/H/11392-14

TL1H/11392-13

4-119

~
~

~

~

r------------------------------------------------------------------------------------------,
Typical Performance Characteristics

(Continued)

Reverse Characteristics

ra STEPS (V)
o

100

~

80

15

60

...

40

2

4

.3
....
LM4041-ADJ

""""=>
<>
en

2V/stap

...>
""

Vour

./

ffi

20
TJ=25 OC
LM4041-ADJ

o I
o

4

2

8

TUH/11392-16

10

OUTPUT VOLTAGE (v)
TUH/11392-15

Large Signal Response

I

-4~OC ~UT~UT

10

8

II.

o

t-

+15V

1

Ii.

J

4

2

1=
INPUT

LM4041-ADJ
TJ=-4DOC
25 0 C
85 0 C

,

-~~OC

~

II

I~

ITUH/11392-18

o

10

20

30

40

RESPONSE TIUE (ps)
TL/H/11392-17

Functional Block Diagram

TL/H/11392-21

'LM4041-ADJ only
.. LM4041-1.2 only

4·120

r-----------------------------------------------------------------------------, r
==

Applications Information

0l:Io

The LM4041 is a precision micro-power curvature-corrected
bandgap shunt voltage reference. For space critical applications, the LM4041 is available in the sub-miniature SOT-23
surface-mount package. The LM4041 has been designed
for stable operation without the need of an external capacitor connected between the "+" pin and the "-" pin. If,
however, a bypass capacitor is used, the LM4041 remains
stable. Design effort is further reduced with the choice of
either a fixed 1.2V or an adjustable reverse breakdown voltage. The minimum operating current is 60 /LA for the
LM4041-1.2 and the LM4041-ADJ. Both versions have a
maximum operating current of 12 mA.

Note that the actual output voltage can deviate from that
predicted using the typical aVREF/aVO in equation (2): for
C-grade parts, the worst-case aVREF/aVO is -2.5 mVIV
and Vy = 1.246V. For D-grade parts, the worst-case
aVREFI!:..vO is -3.0 mVIV and Vy = 1.248V.
The following example shows the difference in output voltage resulting from the typical and worst case values of
aVREF/aVO: Let Vo = +9V. Using the typical value of
aVREF/aVO, VREF is 1.228V. Choosing a value of
R1 = 10 kO, R2 = 63.272 kO. Using the worst case
a VREFI a Vo for the C-grade and D-grade parts, the output
voltage is actually 8.965V and 8.946V, respectively. This results in possible errors as large as 0.39% for the C-grade
parts and 0.59% for the D-grade parts. Once again, resistor
values found using the typical value of aVREF/aVO will
work in most cases, requiring no further adjustment.

LM4041s using the SOT-23 package have pin 1 connected
as the (-) output through the package's die attach interface.
Therefore, the LM4041-1.2's pin 1 must be left floating or
connected to pin 3 and the LM4041-ADJ's pin 1 is the (-)
output.
In a conventional shunt regulator application (Figure 1), an
external series resistor (Rs) is connected between the supply voltage and the LM4041. Rs determines the current that
flows through the load (Ill and the LM4041 (Ia). Since load
current and supply voltage may vary, Rs should be small
enough to supply at least the minimum acceptable la to the
LM4041 even when the supply voltage is at its minimum and
the load current is at its maximum value. When the supply
voltage is at its maximum and IL is at its minimum, Rs
should be large enough so that the current flowing through
the LM4041 is less than 12 mAo

Typical Applications
Vs
(

Rs •

~ IQ+ Il

-------0
_Il

VR ....

Lt.t4041~ ~~ IQ
-:.::-

TUH/11392·22

Rs is determined by the supply voltage, (Vs), the load and
operating current, (IL and la), and the LM4041's reverse
breakdown voltage, VR.

FIGURE 1. Shunt Regulator

R - Vs - VR
S - IL + la .
The LM4041-ADJ's output voltage can be adjusted to any
value in the range of 1.24V through 10V. It is a function of
the internal reference voltage (VREF) and the ratio of the
external feedback resistors as shown in Figure 2. The output is found using the equation
Vo = VREF'

(~~ +

1)

t---t--oVo
Lt.t4041-AOJ

~~
-:.::-

(1)

Rl
R2

-:.::-

where Vo is the desired output voltage. The actual value of
the internal VREF is a function of Vo. The "corrected" VREF
is determined by

Tl/H/I1392-34·

FIGURE 2. Adjustable Shunt Regulator

VREF' = VO(aVREF/aVO) + Vy
(2)
where Vo is the desired output voltage. aVREF/aVO is
found in the Electrical Characteristics and it typically
-1.3 mVIV and Vy is equal to 1.240V. Replace the value of
VREF' in equation (1) with the value found using equation
(2).

4-121

....~

....
g

..
:::E

Typical Applications (Continued)

.....

+15V
15kll

IN4148

IN4 148

6.98 kll

50kll

IN41'48

15 kll

IN4148

-15V

fir

>-......:----:--...-0 Your
0.1 pF.I.
-15V

TL/H/11392~24

FIGURE 3. Bounded amplifier reduces saturation-induced delays and can prevent succeeding stage damage.
Nominal clamping voltage Is ± Vo (LM4041's reverse breakdown voltage) + 2 diode VF.

+

~

Rl
120k

~

R2
1M

Rl
,120k

+

Dl~r

A

r, ~

FB

l.II4D41-ADJ

R2
1M

<-12V
R3

>-12V
R3
330

LED ON

200
-5V

TLlH111392-20

FIGURE 4•.voltage Level Detector

1~

LED ON

-5V

TLlH11'1392-23

FIGURE 5. Voltage Level Detector

Rl '
~--. .-

VOUT

-. . ._

VOUT

R2

• ...;.;;.......-..;.;~r l.M4041-ADJ

02
IN914
R3

240k
LM4D41-ADJ

TL/H111392-26

R4
240k

FIGURE 7. Bidirectional Clamp ± 2.4V
TLlH111392-25

FIGURE 6. Fast Positive Clamp
2.4V + ~VD1

Typical Applications (Continued)

It

VI.

It

HI

VIN
HI
VOYT

VOYT

02
1N457

AZ
31D1t

HZ
330k

Lt.t4041-ADJ

02
IN457

LM4041-ADJ '1~:':"--.

+
Lt.l4041-ADJ ~~~--"'--1

LM4041-ADJ

01
IN457

H4
330k

TL/H/11392-36

TLlH/11392-35

FIGURE 8. Bidirectional Adjustable
Clamp ± 2.4V to ± 6V

FIGURE 7. Bidirectional Adjustable
Clamp ±18Vto ±2.4V

-

+15V

OT020mA

IN4D02

+5V
AI

+
3100
:0:2% . ._....:;...

D2

DI'

rvI
~

-=

1"", < lOUT < 100mA

lOUT a I.:~V
TL/H/11392-38
TL/H/11392-37

FIGURE 10. Current Source

FIGURE 9. Simple Floating Current Detector

-

OTOHmA

•

+5V

+

01'

TLlH/11392-39

FIGURE 11. Precision Floating Current Detector
'01 can be any LED. VF = 1.5V to 2.2V at 3 mAo 01 may act as an
01 will be on H ITHRESHOLD falls below the threshold current.
excapt with I = O.

Indicator.

4·123

.......
~

~

Typical Applications (Continued)
12V
30k

12

"oUT

LF13006
LF13007

DIGITAL
CONTROL

LM4041-1.2

+12V

2
INPUT

0.1 J.lF

ANA
GND

...d

-

16

7

I

OUT

~~[

>'-1----"M-..... ~ lOUT
123.0,0.5%

__1_]

1230 gain se1 ..

TLlH/11392-27

FIGURE 12. Programmable Current Source

LM4041-1.2

12V
LM4041-1.2

lOUT'
-1.0V TO -12V

R2

--.....;;.·--4_--f-.......W\r-......

'lOUT

~

1.2V

R2

-15V
TLlH/11392-28

FIGURE 13. Precision 1 p.A to 1.mA Current Sources

4-124

TL/H/11392-29

,-------------------------------------------------------------------------, r
3i:
~
~

t!lNational Semiconductor

....
c.:I

LM4431
Micropower Shunt Voltage Reference
General Description

Key Specifications

Ideal for space critical applications, the LM4431 voltage reference is available in the sub-miniature (3 mm x 1.3 mm)
SOT-23 surface-mount package. The LM4431 's advanced
design eliminates the need for an external stabilizing capacitor while ensuring stability with any capacitive load, thus
making the LM4431 easy to use. The operating current
range is 100 p.A to 15 mA.

•
•
•
•
•

The LM4431 utilizes fuse and zener-zap reverse breakdown
voltage trim during wafer sort to ensure that the parts have
an accuracy of better than ± 2.0% at 25·C. Bandgap reference temperature drift curvature correction and low dynamic impedance ensure stable reverse breakdown voltage accuracy over a wide range of operating temperatures and
currents.

Features
•
•
•
•

Output voltage tolerance 25·C
Low output noise (10 Hz to 10 kHz)
Wide operating current range
Commercial temperature range
Low temperature coefficient

±2.0% (max)
35 p.Vrms (typ)
100 p.A to 15 mA
O·C to +70·C
30 ppml"C (typ)

Applications
•
•
•
•
•
•
•

Portable, Battery-Powered Equipment
Data Acquisition Systems
Instrumentation
Process Control
Energy Management
Product Testing
Power Supplies

Small package: SOT-23
No output capacitor required
Tolerates capacitive loads
Fixed reverse breakdown voltage of 2.50V

Connection Diagram
SOT-23

TL/H/11374-1

·This pin must be left floating or connected to pin 3.

Top View

.

Order Number LM4431M3-2.5
See NS Package Number M03B
(JEDEC Registration TO-236AB)

SOT-23 Package Marking Information
Only three fields of marking are possible on the SOT-23's small surface. The following table gives the meaning of the three
fields.
Part Marking

Field Definition

S2E

First Field:
S = Reference
Second Field:
2 = 2.500V Voltage Option
Third Field:
E = Initial Reverse Breakdown Voltage Tolerance of ± 2.0%

4-125

Absolute Maximum Ratings (Note 1)
ESD Susceptibiiity
2 kV
Human Body Model (Note 3)
200V
Machine Model (Note 3)
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Reverse Current
20mA
Forward Current
10mA
Power Dissipation (TA = 25'C) (Note 2)
M3 Package
306mW
- 65'C to + 150'C
Storage Temperature
Lead Temperature
M3 Package
Vapor phase (60 seconds)
Infrared (15 seconds)

Operating Ratings (Notes 1 & 2)
Temperature Range
(Tmin"; TA"; Tmax)
Reverse Current
LM4431-2.5

+215'C
+ 220'C

O'C,,; TA

~

+70'C

100 /LA to 15 mA
:

LM4431-2.5

Electrical Characteristics
Boldface limits apply for TA = TJ = TMIN to TMAX; all other lirriits TA = TJ = 25'C.

Symbol

VR

IRMIN

Parameter

Conditions

Reverse Breakdown Voltage

IR = 100/LA

Reverse Breakdown Voltage
Tolerance

IR = 100 /LA

Typica,l
(Note 4)

LM4431M3
limits
(Note 5)

V

2.500
±50

mV(max)

100

/LA
/LA (max)

45

Minimum Operating Current

IlVR/IlT

Average Reverse Breakdown
Voltage Temperature
Coefficient

IR=10mA
IR = 1 mA
IR = 100/LA

±30
±30
±30

IlVRI IlIR

Reverse Breakdown Voltage
Change with Operating
Current Change

IRMIN ,,; IR ,,; 1 mA

0.4

1 mA ,,; IR ,,; 15 mA

U,nits
(Limit)

ppml'C
ppml'C
ppml'C
1.0
1.2

mV
mV(max)
mV(max)

8.0
25

mV
mV(max)
mV(max)

2.5

1.0

n

IR = 100/LA
10Hz"; I"; 10kHz

35

/LVrins

t = 1000 hrs
T = 25'C ±O.l'C
IR = 100/LA

120

ppm

ZR

Reverse Dynamic Impedance

IR = 1 mAl = 120Hz
lAC = 0.1 iR

eN

Wideband Noise

IlVR

Reverse Breakdown Voltage
Long Term Stability

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), OJA (junction to

ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature Is PDrnax = (TJrnax - TpJI9JA or the
number given in the Absolute Maximum Ratings, whichever is lower. For the LM4431, TJrnax = I 25'C, and the typical thermal resistance (9JpJ, when board
mounted, is 326'C/W for the SOT·23 package.
Nole 3: The human body model is a 100 pF capaCitor discharged through a 1.5 kO resistor into each pin, The machine model is a '200 pF capaCitor discharged
directly into each pin.
Nole 4: Typlcals are at TJ = 25'C and represent most likely parametric norm.
Nole 5: Limits are 100% production tested at 25'C, Limits over temperature are guaranteed through correlation using Statistical Quality Control (SQC) methods.
The limits are used to calculate National's AOQL.

4-126

Typical Performance Characteristics
Temperature Drift for Different
Average Temperature Coefficient
+0,5

Output Impedance vs Frequency

+0,4

,

lk ~

IR = 150 p.A

TJ = 25°C
,.l.IR = O,IIR

+0,3
~
~

+0,2

<.'>

:z
«

13

S

/,,+12ppm/oC

::; +0,1

I::-:::"
r--: r-'

0

F=

-0,1

>a:. -0.2

- ----

.L
-..........:

-

-0,4

U

::!

D:

IV

-0,5

0,1
0

10

20

30

40

50

60

70

100

/

;

~-IP.F

IR -150

"-

. l1.....

=0

"
,,~'A

V

10

«

8

. . . "z

-22 ppm/DC
-51 ppm/oC"
1

-0,3

"":z

~

... ... -

,

,

100

TANTALUM

'"~~
J

.....<

IR=1 mA

''''''

"""I

lk

TEMPERATURE (OC)

Llln,

10k

Xc "'"

lOOk

1M

FREQUENCY (Hz)
TL/H111374-2

TL/H/11374-3

Noise Voltage

Reverse Characteristics and
Minimum Operating Current

1400
IR = 200 p.A
TJ = 25°C

100

"<
-3

80

~

60

IRMIN
Typical
TJ = 25°C

1200

- c-

1000

@

0-

>
..s
""(5
V)

=0

u

""
V)

40

.....V

5
>

'"""

/

:z

4

20

800

"

i'o..

400
200
0

~
0

\

600

II

0

1\

10

1
1

2

3

4

5

100

lk

10k

lOOk

FREQUENCY (Hz)

REVERSE VOLTAGE (V)

TL/H/11374-5
TL/H/11374-4

Start-Up Characteristics
LM4431-2,5

,:::i?"t f

Rs

=

30k

Rs

'.' 0'"", ",

5

~
z

.... .... .... .... .... .... .... .... . ... . ...

0

>-

TJ = 25°C
3

TLlH/11374-6

2:- 1
~

A

-

2

f-- f--

.... .... ....

0
0

20

. ... ....

.... ....

40

60

00,

. ...

80

RESPONSE TIME (p.s)
TLlH/11374-7

4-127

,...
C')

:::

:3

Functional Block Diagram

TLlH/11374-8

Applications Information
The LM4431 is a micro-power curvature-corrected 2.5V
bandgap shunt voltage reference. For space critical applications, the LM4431 is available in the sub-miniature SOT-23
surface-mount package. The LM4431 has been designed
for stable operation without the need of an external capacitor connected between the "+" pin and the "-" pin. If,
however, a bypass capacitor is used, the LM4431 remains
stable. The operating current range is 100 /LA to 15 mA.
The LM4431'sSOT-23 package has a parasitic Schottky
diode between pin 3 (-) and pin 1 (Die attach interface
contact). Therefore, pin 1 of the SOT-23 package must be
left floating or connected to pin 3.
In a conventional shunt regulator application (Figure 1), an
external series resistor (Rs) is connected between the supply voltage and the LM4431. Rs determines the current that
flows through the load (Id and the LM4431 (10)' Since load
current and supply voltage may vary, Rs should be small
enough to supply at least the minimum acceptable 10 to the
LM4431 even when the supply voltage is at its minimum and
the load current is at its maximum value. When the supply
voltage is at its maximum and Il is at its minimum, Rs

should be large enough so that the current flowing through
the LM4431 is less than 15 mA.
Rs is determined by the supply voltage, (Vs), the load and
operating current, (Il and 10), and the LM4431's reverse
breakdown voltage, VR.
R - Vs - VR

s-10IQ

Typical Applications

TLlH/11374-9

FIGURE 1_ Shunt Regulator

4-128

r-----------------------------------------------------------------------------,~

i:

Typical Applications (Continued)

~
~

....
w

+5V

-5V

>-------.....- 0 Your

-5V

TUH111374-10

FIGURE 2. Bounded amplifier reduces saturation-induced delays and can prevent succeeding stage damage.
Nominal clamping voltage is ±3.9V (LM4431's reverse breakdown voltage +2 diode VF).

10kll

0.1 /IF
D2

D4

•

.:::c.
-5V

Dl - D6

=lN914

47011

5kll

+5V

-5V
Skll
D6

TL/H/11374-11

FIGURE 3. Protecting Op Amp Input. The bounding voltage is ± 4V with the LM4431
(LM4431's reverse breakdown voltage + 3 diode VF).

4·129

.. r------------------------------------------------------------------------------------------,
~
~

::&

Typical Applications (Continued)

...I
12V
30k

12

AoUT

LF13006
LF13007

DIGITAL

LM4431

CONTROL

+12V

2

INPUT

ANA
GND
16

1/2 LMC6062

DUAL
OP-AMP 3

I

OUT

>~>---4IYv..... lIOUT
24911,0.5%

=~[-1-1
24911 gain set ""
TL/H/11374-12

FIGURE 4. Programmable Current Source

12V

LM4431

Lt.f4431

'lOUT

= 2.5V
R2

-15V
TL/H/11374-13

FIGURE 5. Precision 1 p.A to 1 mA Current Sources

4-130

TL/H/11374-14

t!lNational Semiconductor

LM9140
Precision Micropower Shunt Voltage Reference
General Description
The LM9140's reverse breakdown voltage temperature coefficients of ± 25 ppmfOC are ideal for precision applications. The LM9140's advanced design eliminates the need
for an external stabilizing capacitor while ensuring stability
with any capacitive load, thus making the LM9140 easy to
use. Further reducing design effort is the availability of several fixed reverse breakdown voltages: 2.500V, 4.096V,
5.000V, and 10.000V. The minimum operating current increases from 60 /LA for the LM9140-2.5 to 100 p.A for the
LM9140-10.0. All versions have a maximum operating current of 15 mAo
The LM9140 utilizes fuse and zener-zap reverse breakdown
voltage trim during wafer sort to ensure that the prime parts
have an accuracy of better than ±0.5% (B grade) at 25'C.
Bandgap reference temperature drift curvature correction
and low dynamic impedance ensure stable reverse breakdown voltage accuracy over a wide range of operating temperatures and currents.

Features
• Guaranteed temperature coefficient of ±25 ppmfOC
• Reverse breakdown voltage tolerance of ±O.5%
• Small paCkage: TO-92

• No output capaCitor required
• Tolerates capacitive loads
• Fixed reverse breakdown voltages of 2.500V, 4.096V,
5.000V, and 10.000V

Key Specifications (LM9140-2.5)
•
•
•
•
•

Temperature coefficient
±25 ppmfOC (max)
Output voltage tolerance
±0.5% (max)
Low output noise (10 Hz to 10 kHz)
35 /LVrms (typ)
Wide operating current range
60 /LA to 15 mA
Industrial temperature range
-40'C to +85'C

Applications
•
•
•
•
•
•
•
•

Portable, Battery-Powered Equipment
Data Acquisition Systems
Instrumentation
Process Control
Energy Management
Product Testing
Automotive
Precision Audio Components

Connection Diagrams
NC

TO-92
+

TUH/11393-2

Bottom View
See NS Package Number Z03A

Ordering Information
.---------------------.-----------~

Reverse Breakdown
Voltage Tolerance at 25'C
and Average Reverse Breakdown
Voltage Temperature Coefficient

0.5%,25 ppmfOC max

Z{TO-92)

LM9140BYZ-2.5,
LM9140BYZ-4.1,
LM9140BYZ-5.0,
LM9140BYZ-l0.0

4-131

Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Reverse Current
20 rnA
Forward Current
10mA
Power Dissipation (TA = 25'C (Note 2)
ZPackage
550mW
Storage Temperature
- 65'C to + 150'C
Lead Temperature
Z Package
Soldering (10 seconds)

ESO Susceptibility
2kV
200V

Human Boddy Mode (Note 3)
Machine Model (Note 3)

Operating Ratings (Notes 1 and 2)
Temperature Range
(Tmin S; T A S; T max>
Reverse Current
.LM9,140-2.5
LM9140-4.1
LM9140-5.0
LM9140-10.0

+ 260'C

-40'C

..

S;

TA

S;

+85'C

60/-,At015mA
68/-,A to 15 rnA
74/-,A to 15 rnA
100 /-,A to 15 rnA

LM9140BYZ-2.5
Electrical Characteristics
Boldface limits apply for TA = T .. = TMIN to TMAX; all other limits TA = TJ = 25'C
Symbol
VR

IRMIN

aVR/aT

aVR/aIR

Parameter

Conditions

Reverse Breakdown Voltage

IR = 100/-,A

Reverse Breakdown Voltage
Tolerance (Note 6)

IR=100/-,A

IR = 10mA
IR = 1 mA
IR = 100/-,A

Reverse Breakdown Voltage
Change with Operating
Current Change

IRMIN

Reverse Dynamic Impedance
Wideband Noise

aVR

Reverse Breakdown Voltage
Long Term Stability

Units
(Limit)

±12.5
±16.6

mV(max)
mV(max)

60
65

/-,A
/-,A(max)
/-,A(max)

V

45

Average Reverse Breakdown
Voltage Temperature
Coefficient (Note 7)

eN

Limits
(Note 5)

2.500

Minimum Operating Current

1 rnA

ZR

Typical
(Note 4)

S;

S;

IR

S;

. ±10
±10
±10
1 mA

IR :s; 15 rnA

Ii=! = 1 rnA, f = 120 Hz,
lAC = 0.11R

0.3

t = 1000 hrs
25'C ±0.1'C
IR = 100/-,A

120

4-132

mV
mV(max)
mV(max)

6.0
8.0

mV
mV(max)
mV(max)

0.8

o (max)

0.3

35

,

ppm/'q
ppm/'C (max)
ppml'C

0.8
1.0
2.5

IR = 100/-,A
10Hz S; f S; 10kHz

T=

±25

0

/-,V rms

ppm
'.,

LM9140BYZ-4.1
Electrical Characteristics
Boldfae.llmits apply for TA =.TJ = TIlIN to TIIAX; all other limits TA = TJ = 25°C
.. Parameter

Symbol
VA

Conditions

=

Reverse Breakdown Voltage

IA

Reverse Breakdown Voltage
Tolerance (Note 6)

IA = 100/LA

100/LA

Minimum Operating Current

IAMIN

aVA/1lT

aVA/alA

eN
aVA

.'

Units
(Limit)

±20.S
±27.1

mV(max)
mV(max)

68
73

/LA
/LA (max)
/LA (max)

4.096

Average Reverse Breakdown
Voltage Temperature·
Coefficient (Note 7)

IA = 10mA
IA=1mA
IA = 100 /LA

±10
±10
±10

Reverse Breakdown Voltage
Change with Operating
Current Change

lAM IN s; IA s; 1 mA

0.5

Reverse Dynamic Impedance

Limits
(Note 5)

V

50

1 mA s; IA s; 1SmA

ZA

Typical
(Note 4)

IA = 1 mA, f = 120 Hz,
lAC = 0.11A

±25

ppml"C
ppml"C (max)
ppml"C

0.9
1.2

mV
mV(max)
mV(max)

7.0
10.0

mV
mV(max)
mV(max)

1.0

n
n(max)

3.0

0.5

Wideband Noise

IA = 100 /LA
10 Hz s; f s; 10kHz

80

/LVrms

Reverse Breakdown Voltage
Long Term Stability

t = 1000 hrs
T = 25°C ±0.1°C
IA = 100 /LA

120

ppm

4-133

LM9140BYZ-5.0

"

Electrical Characteristics
Boldface limits apply for TA
Symbol
VR

= TJ

Parameter" ,
Reverse Breakdown Voltage
Reverse Breakdown Voltage
Tolerance (Note 6)

IRMIN

AVR/AT

AVR/AIR

"

= TMIN to TMAX; all other limits TA = TJ' = 25'C
, Conditions

= 100 p.A
IR = 100 p.A

5.000

IR

Minimum Operating Current

55

= 10mA
= 1 mA
= 100 "A

Average Reverse Breakdown
Voltage Temperature
Coefficient (Note 7)

IR
IR
IR

R,everse Breakdown Voltage
Change with Operating
Current Change

IRMIN

s: IR s:

Uml..
(NoteS)

Typical
(Note 4)

,

eN
AVR

Reverse Dynamic Impedance

s: 15 mA"

IR = 1 mA,f
lAC = 0.11R

= 120Hz,

Wideband Noise,

IR = 100 "A
10 Hz s: f s: 10kHz

Reverse Breakdown Voltage
Long Term Stability
'.

t = 1000 hrs
T = 25'C ±0.1'C
IR = 100 "A

4-134

V

74
80

'".A (max)
".A (max)

p.A

',,±21

0.5

ppm/'C
ppml'C (max)
ppm/'C

1A

mV
mV(max)
mV(max)

8.0
12.0

mV
'mV(max)
,mV(max)

1.1

n
n(max)

1.0
1 mA s; IR

..

mV(max)
mV(max)

..

ZR

..

±25.0
±33.1
I.

," '±10
±10
±10
1 mA,

"

Unl,"
(Umlt)

3.5

0.5

....:.

80

"Vrms

.,'
120

ppm

.s:::

LM9140BYZ-10.0

CO

.....

01:00

o

Electrical Characteristics
Boldface I.imits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C
Symbol
VA

Parameter

Typical
(Note 4)

Conditions

Reverse Breakdown Voltage

IA = 150JJ.A

Reverse Breakdown Voltage

IA = 100JJ.A

aVAII::..T

aVA/aiR

Minimum Operating Current

V
±50.0

mV(max)

±66.3

mV(max)

100

JJ.A(max)

103

JJ.A(max)

75

Average Reverse Breakdown

IA = 10mA

±10

Voltage Temperature

IA = 1 mA

±10

Coefficient (Note 7)

IA = 150 JJ.A

±10

Reverse Breakdown Voltage

IRMIN :s:; IA :s:; 1 mA

0.8

JJ.A

ppml"C
±2S·

Current Change
1 mA:s:; IA :s:; 15 mA

Reverse Dynamic Impedance

mV
1.6

mV(max)

3.S

mV(max)

12.0

mV(max)

23.0

mV(max)

1.7

O(max)

8.0

IA = 1 mA, f = 120 Hz,

mV

Wideband Noise

IA = 150JJ.A
10Hz:s:; f:s:; 10kHz

aVA

Reverse Breakdown Voltage

t = 1000 hrs

Long Term Stability

T = 25°C ±0.1°C

0

0.7

lAC = 0.11A
eN

ppmI"C(max)
ppml"C

Change with Operating

ZA

Units
(Limit)

10.00

Tolerance (Note 6)
IAMIN

Limits
(Note 5)

180

JJ.Vrms

120

ppm

IA = 150JJ.A
Note 1: Absolute Maximum Ratings indicate lim"s beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electricel Characteristics. The guaranteed
specifications apply only for the test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some
performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: The maximum power dissipation must be derated at elevated temperatures and Is dictated by TJrnax (maximum junction temperature). 6JA Ounction to
ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDMAX = (TJmax - TAl/OJA or the
number given in the Absolute Maximum Aatings, whichever is lower. For the LM9140, TJmax = 125'C, and the typcial thermal resistance (OJAl, when board
mounted, is 170'C/W with 0.125' lead length for the TO·92 package.

Note 3: The human body model is a 100 pF capacitor discharged through a 1.5 kll resistor Into each pin. The machine mode is a 200 pF capacitor discharged
directly into each pin.
Note 4: Typicals are at TJ

= 25'C and represent most likely parametric norm.

Note 5: Limits are 100% production tested at 25°C. Limits over temperature are
The lim"s are used to calculate National's AOQL.

guarantee~

through correlation using Statistical Quality Control (SaC) methods.

Note 6: The boldface (over·temperature) limit for Reverse Breakdown Voltage Tolerance is defined as a room termperature Reverse Breakdown Voltage Tolerance
± [AVA/AT) (65'C) (VA)]. AVA/AT is the VA temperature coefficent, 65'C is the temperature range from -40'C to the reference point of 25'C, and VA is the
reverse breakdown voltage. The total over·temperature tolerence for the different grades is shown below:
B·grade: ±0.66% = ±0.5% ±25 ppm/'C x 65'C
Therefore, as an example, the B·grade LM9140·2.5 has an over·temperalUre Reverse

Brea~down

Voltage tolerance of ±2.5V

x

0.66%

=

±16.6 mV.

Note 7: The average temperature coefficient is defined as the maximum deviation of reference voltage at all measured temperatures between the operating TMAX
and TMIN, divided by TMAX - TMIN. The measured temperatures are -55'C, -40'C, O'C, 25'C, 70'C, 85'C and 125'C.

4·135

~
0;

....

:E

Typical Performance Characteristics
Temperature Drift for Different
Average Temperature Coefficient
+0.5
+0.4
+0.3

g

+0.2

Ill. +0.1
Z

0

5 -0.1

>'" -0.2

Output Impedance va Frequency
lk

IR= 1501'''
+3ppm/ oC

.......... J

-

'-0.3

r-..

/'

-22 ppm/oC

-0.5
-20

-

...........

-0.4
-4~

.-

1'"+12 ppm/oC

Lf~

0

20

40

60

.0.1

80

100

L...J..J.JJ.WIL...L..L.LWIIL....I.J.JJ.WIL...L..LJ.WW

100

Ik

TEMPERATURE (OC)

10k

111

lOOk

FREQUENCY (Hz)
TLlH/11393-3

TL/H/11393-4

Reverse Characteristics and
Minimum Operating Current

Output Impedance VB Frequency
lk~~~~=r-----'----~

..

~

100

S...
u
Z

...

j§

.,>

120

...

100

.3

......

.. ; ;
~

'-I.v.l'~

80

"L""

Gu"f"

,

"t.\I'

•

.1""'

'"'"u

10

60

:>

...

...'"~

0.

VI

2!

~

40

II<

(
)

20
. 0

O. I L...J...J.1.lWIL....J...I.J.UJ.\'L-L..U.I.lIII1.;.J..J..l.LlWI
100
lk
10k. lOOk
1M

o

2

4

Noise Voltage vs Frequency
·10

IR~

5.0

TJ,=25 O

1.0

til

0.5

<;

......

2.0

.3

...

?--TJ i 25
6

0

C

8

10
TLlH/I1393-6

l'L/H/11393-5

.....
>

/

...

~ \

REVERSE VOLTAGE (v)

FREQUENCY (Hz)

~.

>

~

Z

'"

Z

"

C=

VR =10V_ I--5V __

D-

2.5V I----'

0.2
0.1
1

10

100

Ik

FREQUENCY (Hz)

4-136

10k

lOOk
TL/H/11393-7

Start-Up Characteristics

TL/H/11393-8

LM9140-2.5

~

RS = 30k

0 I--t-~i-+-t-±--+-t-+-i---t

%

>-

-

2r--r-t--r-H--r-t--r-~-r~

20

. O.

40

60,

80

RESPONSE TIME (ps)
TL/H/11393-9

LM914Q..5.0

'>

. LM9140-10.0

RS = 30k

RS = 30k

10~~~~~~--+--+--~~~~

................................... .

,",:ol--+--I--+--I--±---I--+-I--I---I
TJ = 25°C

>-

4r--r-t--r~~-r-t--r~~-r~

>'"

10r-~-r--r-~~--~~--w--r~

LJ

~2

~5

.... ~ .•..•.......
0~~-+--r-+--r-1~+-~-+~

o

100

200

300

If

>'" 0 .... ~

400

100

RESPONSE mtE (ps)

II

....

200

300

Il ......
400

RESPONSE TIME (ps)
TLlH/11393-10

TLlH/11393-11

4-137

~

a;

...

:E

Functional Block Diagram
r----.------~--~~--------~~--~+

TL/H/11393-12

Applications Information
The LM9140 is a precision micro·power curvature·corrected
bandgap shunt voltage reference. The LM9140 has been'
designed for stable operation without the need of an exter·
nal capacitor connected between the" + .. pin and the" -"
pin. If, however, a bypass capacitor is used, the LM9140
remains stable. Reducing design effort is the availability of
several fixed reverse breakdown voltages: 2.500V, 4.096V,
5.000V, and 10.000V. The minimum operating current in·
creases from 60 p.A for the LM9140·2.5 to 100 p.A for the
LM9140·10.0. All versions have a maximum operating cur·
rent of 15 mAo
The 4.096V version allows single + 5V 12·bit ADCs or
DACs to operate with an LSB equal to 1 mV. For 12·bit
ADCs or DACs that operate on supplies of 10V or greater,
the 8.192V version gives 2 mV per LSB.
In a conventional shunt regulator application (Figure 1), an
external series resistor (Rs) is connected between the sup·
ply voltage and the LM9140. Rs determines the current that
flows through the load (Ill and the LM9140 (10). Since load
current and supply voltage may vary, Rs should be small
enough to supply at least the minimum acceptable 10 to the
LM9140 even when the supply voltage is at its minimum and
the load current is at its maximum value. When the supply

voltage is at its maximum and Il is at its minimum, Rs
should be large enough so that the current flowing through
the LM9140 is less than 15 mA.
RS is determined by the supply voltage, (Vs), the load and
operating current, (Il and 10), and the LM9140's reverse
breakdown voltage, VR.
Rs = Vs - VR
Il + 10

Typical Applications

TLlH/11393-2D

FIGURE 1. Shunt R~gulator

4·138

.-----------------------------------------------------------------------------~

r

i:

....

Typical Applications (Continued)

CD

~

DVcc ",,2:;;4~_ _ _....._""",

~--"""-O+5V

AVec ....4.;........_ _---1,...._-'
90911

LN9140-4.1

'Tantalum
• 'Ceramic monolithic

FIGURE 2. LM9140-4.1's Nominal 4.096 breakdown voltage gives ADC124511 mVlLSB

TUH/11393-13

+15V

IN4148

15 kll

IN4148

-15V

>-------..

-oVOUT

-15V

TLlH/11393-14

FIGURE 3. Bounded amplifier reduces saturation-induced delays and can prevent succeeding stage damage.
Nominal clamping voltage Is ± 11.5V (LM9140's reverse breakdown voltage + 2 diode VF).
4·139

~

a;
~

Typical Applications (Continued)

10kll

O.lI'F

.:c.

02

-

04

01-D6=lN914

-5V
470ll

5kll
-5V

+5V
5kll
06

TL/H/11393-15

FIGURE 4. Protecting Op Amp Input. The bounding voltage Is ± 4V with the LM9140-2.5
(LM9140's reverse breakdown voltage + 3 diode VF)'

+5V:t5"

t - -....- - - - - - - - - - - o U . 0 9 6 V
LM9140-4.1

47 kll. 0.1"
47 kll. 0.1"

>--....-o-4.096V

-5V

FIGURE 5. Precision ± 4.096V Reference

4·140

TLlH/11393-16

r-----------------------------------------------------------------------------'r
5:
CD
Typical Applications (Continued)
....
0l:Io

o
12V
30k

12
AoUT

Lf13006
Lf130D7

DIGITAL
CONTROL

LM9140-2.5

+12V

2
INPUT

ANA
GND
16

7
1/2LMC6062
DUAL
OP-AMP 3

>~---'IIyY-"'"
249U,O.5%

IOUT ~ 249U
2.5V [_1_]
gain set

!

lOUT

#

TLlH/11393-17

FIGURE 6. Programmable Current Source

LM9140-2.5

12V
LM9140-2.5

'lOUT ~ 2.5V
R2

-15V
TLlH/11393-18

FIGURE 7. Precision 1 "A to 1 mA Current Sources

4·141

TL/H/11393-19

•

Section 5
Temperature Sensors

Section 5 Contents
Temperature Sensors Selection Guide.................... ..... .......................
lM34/lM34A1lM34C/lM34CAllM34D Precision Fahrenheit Temperature Sensors .......
lM35/lM35A1lM35C/lM35CA/lM35D Precision Centigrade Temperature Sensors.......
lM45B/lM45C SOT-23 Precision Centigrade Temperature Sensors.. ........... .........
lM50B/lM50C Single Supply Precision Centigrade Temperature Sensors. . . . . . . . . . . . . . . . .
lM134/lM234/lM334 3-Terminal Adjustable Current Sources... .... ........... .... .....
lM135/lM235/lM335/lM135A1lM235A1lM335A Precision Temperature Sensors. . . . . . . .

5·2

5-3
5-4
5-12
5-21
5-28
5-29
5-38

~

3

'C
CD

t;tINational Semiconductor

a
c

iiJ
en
CD

Temperature Sensor
Selection Guide

::s

t...,

o...
en
CD

CD
n

'Accuracy

Output Scale

LM34A
LM34
LM34CA
LM34C
LM34D

Part

-50'Fto
-50'Fto
-40'Fto
-40'Fto
+32'F to

Temp'. Range
+300'F
+300'F
+230'F
+230'F
+212'F

±2.O'F
±3.0'F
±2.0'F
±3.0'F
±4.O'F

10 mVI'F
10mVI'F
10 mV/'F
10 mVI'F
10 mV/'F

LM35A
LM35
LM35CA
LM35C
LM35D

-55'Cto + 150'C
- 55'C to + 150'C
-40'Cto +110'C
-40'C to + 110'C
O'C to + 100'C

± 1:0'C
±1.5'C
±1.0'C
±1.5'C
±2.O'C

10 mVI'C
10mVl'C
10 mV/'C
10mV/'C
10 mV/'C'

LM45B
LM45C

- 20'C to + 100'C
- 20'C to + 100'C

±2.0'C
±3.0'C

10mV/'C
10mVl'C

- 55'C to + 125'C
-55'C to + 125'C
. ~25'C to + 100'C
-25'Cto +100'C
O'Cto +70'C

±3.0'C
±6.0'C
±3.0'C
±6.0'C
±6.0'C

ISET a:

±1.3'C
±2.0'C
±1.3'C
±2.0'C
±2.O'C
±4.0'C

10 mVl'K
10 mVI'K
10 mVl'K
10 mVI'K
10 mVI'K
10 mV/'K

LM134·3
LM134·6
LM234·3
LM234·6
LM334
LM135A
LM135t
LM235A
LM235
LM335A
LM335

- 55'C to
- 55'C to
-40'Cto
- 40'C to
- 40'C to
- 40'C to

"

+ 150'C
+ 150'C
+125'C
+ 125'C
+ 100'C
+ 100'C

'Note: Accuracy is measured over T(Min) to T(Max) uncalibrated
Note: The LM134/234/334 3·Tenninal Adjustable current sources Datasheet can be found In Section 4.
tNote: Militlll)' screening available

,.

..

,

,

5-3

ISET a:
ISET a:
ISET a:
ISET a:

'K
'K
'K
'K
'K

o::s·

G)

c

a:

CD

tflNational Semiconductor

LM34/LM34A/LM34C/LM34CA/LM34D
Precision Fahrenheit Temperature Sensors
General Description
while the LM34C, LM34CA and LM34D are also available in
the plastic TO-92 transistor package. The LM34D is also
available in an a-lead surface mount small outline package.
The LM34 is a complement to the LM35 (Centigrade) temperature sensor.

The LM34 series are precision integrated-circuit temperature sensors, whose output voltage is linearly proportional to
the Fahrenheit temperature. The LM34 thus has an advantage over linear temperature sensors calibrated in degrees
Kelvin, as the user is not required to subtract a large constant voltage from its output to obtain convenient Fahrenheit scaling. The LM34 does not require any external calibration or trimming to provide typical accuracies of ± V2°F at
room temperature and ±1V2°F over a full -50 to +3000F
temperature range. Low cost is assured by trimming and
calibration at the wafer level. The LM34's low output impedance, linear output, and precise inherent calibration make
interfacing to readout or control circuitry especially easy. It
can be used with single power supplies or with plus and
minus supplies. As it draws only 75 ",A from its supply, it has
very low self-heating, less than 0.2°F in still air. The LM34 is
rated to operate over a -50° to +300°F temperature
range, while the LM34C is rated for a -40° to + 2300F
range (OOF with improved accuracy). The LM34 series is
available packaged in hermetic TO-46 transistor packages,

Features
•
•
•
•
•
•
•
•
•
•
•

Calibrated directly in degrees Fahrenheit
Linear + 10.0 mVloF scale factor
1.00F accuracy guaranteed (at + 77"F)
Rated for full -500 to + 300°F range
Suitable for remote 'applications
Low cost due to wafer-level trimming
Operates from 5 to 30 volts
Less than 90 ".A current drain
Low self-heating, 0.1aoF in still air
Nonlinearity only ±O.SOF typical
Low-impedance output, 0.40 for 1 mA load

Connection Diagrams
T0-46
Metal Can Package'

so-a

T0-92
Plastic Package

Small Outline Molded Package

vourO'
8 +VS
BOTTOM VIEW
TL/H/6685-1

'Case is connected to negative pin (GND).

Order Numbers LM34H, LM34AH,
LM34CH, LM34CAH or LM34DH
See NS Package Number H03H

TL/H/8685-2

Order Number LM34CZ,
LM34CAZ or LM34DZ
See NS Package Number Z03A

N.e.

2

7

N.C.

3

6

N.C.
N.C.

GND

4

5

N.e.
TL/H/6865-20

Top View
N.C. = No Connection

Order Number LM34DM
See NS Package Number MOSA

Typical Applications
+Vs
CHOOSE R, = ( - Vs)/50 ,..A

Your

Vour= +3,000 mY AT +300 oF
=+750 mVAT +75°F

=-500 mY AT -50°F
TL/H/6865-3

FIGURE 1. Basic Fahrenheit Temperature Sensor
(+5°to +300"F)

-Vs
TLlH/8685-4

FIGURE 2. Full-Range Fahrenheit Temperature Sensor

5-4

Absolute Maximum Ratings (Note 10)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Lead Temp.
TO-46 Package (Soldering, 10 seconds)
TO-92 Package (Soldering, 10 seconds)

Supply Voltage

+35Vto -0.2V

Output Voltage

+6Vto -1.0V

Output Current

10mA

SO Package (Note 12):
Vapor Phase (60 seconds)
Infrared (15 seconds)

Storage Temperature,
TO-46 Package
TO-92 Package
SO-8 Package

215'C
220'C

Specified Operating Temp. Range (Note 2)

-76'F to + 356'F
-76'Fto +300'F
-65'Cto + 150'C

TMINtoTMAX
-50'Fto +300'F
-40'Fto +230'F
+ 32'Fto +212'F

LM34, LM34A
LM34C, LM34CA
LM34D

800V

ESD Susceptibility (Note 11)

+300'C
+ 260'C

DC Electrical Characteristics (Note 1, Note 6)
LM34A
Parameter

Accuracy (Note 7)

Conditions

=
=
=
=

Typical

Tested
Limit
(Note 4)

+77'F
O'F
TMAX
TMIN

±0.4
±0.6
±O.B
±O.B

Nonlinearity (Note 8)

TMIN';;: TA';;: TMAX

±0.35

Sensor Gain
(Average Slope)

TMIN ,;;: TA';;: TMAX

+10.0

+9.9,
+ 10,1

Load Regulation
{Note 3)

TA = +77'F
TMIN ,;;:TA';;: TMAX
0';;: IL';;: 1 mA

±0.4
±0.5

±1.0

Line Regulation (Note 3)

TA = +77'F
5V,;;: Vs';;: 30V

±0.01
±0.02

±0.05

75
131
76
132

90

Quiescent Current
{Note 9)

Change of Quiescent
Current (Note 3)

TA
TA
TA
TA

Vs =
Vs =
Vs =
Vs =

+5V, +77'F
+5V
+30V, +77'F
+30V

4V ,;;: Vs ,;;: 30V, + 77'F
5V,;;: Vs';;: 30V

Temperature Coefficient
of Quiescent Current
Minimum Temperature
for Rated Accuracy

In circuit of Figure 1,
IL = 0

Long-Term Stability

Tj

= T MAX for 1000 hours

LM34CA
Design
Limit
(Note 5)

±1.0

Typical
±0.4
±0.6
±O.B
±0.8

±2.0
±2.0
±0.7

Tested
Limit
(Note 4)
±1.0

±0.30

:to.6

+10.0

+9.9,
+10.1

mV/'F, min
mVl'F, max

±3.0

mV/mA
mV/mA

±O.1

mVIV
mVIV

±2.0
±3.0

±0.4
±0.5

±1.0

±0.01
±0.02

±0.05

±O.1

90

163

75
116
76
117

2.0

3.0

0.5
1.0

+0.30

+0.5

+3.0

+5.0

92

+0.5
+1.0

2.0

±0.16

Units
(Max)
'F
OF
'F
'F
OF

±2.0

±3.0

160

Design
Limit
(NoteS)

142

p.A
p.A
p.A
p.A

3.0

p.A
p.A

+0.30

+0.5

p.AloF

+3.0

+5.0

'F

±0.16

139
92

'F

Note 1: Unless otherwise noted, these specifications apply: -50'F ,;: Ti ,;: + 300'F for the LM34 and LM34A; -40'F ,;: Tj ,;: +230'F for the LM34C and
LM34CA; and +32'F,;: TJ';: + 212'Fforthe LM34D. Vs = +5 Vdc and ILOAD = 50 I'A in the circuit of Figure 2; +6 Vdcfor LM34 and LM34A for 230'F ,;: TJ ,;:
300'F. These specifications also apply from + 5"F to TMAX in the circuit of Rgure 1.
Note 2: Thermal resistance of the T0-46 package is 720'F/W junction to ambient and 43'F/W junction to case. Thermal resistance of the T0-92 package is
324'F/W junction to ambient. Thermal resistance of the small outline molded package is 400'F/W junction to ambient. For additional thermal resistance information see table in the Typical Applications section.
Note 3: Regulation Is measured at constant junction temperature using pulse testing with a low duty cycle. Changes in output due to heating effects can be
computed by multiplying the internal dissipation by the thermal resistance.
Note 4: Tested limits are guaranteed and 100% tested in production.
Note 5: Design limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage ranges. These limits are not used to
calculate outgoing quality levels.
Note 6: Specification in BOLDFACE TYPE apply over the full rated temperature range.
Note 7: Accuracy Is defined as the error between the output voltage and 10 mVI'F times the device's case temperature at specified conditions of voltage, current,
and tamperature (expressed In 'F).
Note 8: Nonlinearity Is defined as the deviation of the output-voltage-versus-temperature curve from the best-fit straight line over the device's rated temperature

range.
Note 9: Quiescent current Is defined In the circuit of Figure 1.
Note 10: Absolute Maximum Ratings indlcata limits beyond which damage to the device may occur. DC and AC electrical speCifications do not apply when
operating the device beyond Its rated operating condHions (see Note 1).
Note 11: Human body model, 100 pF discharged through a 1.5 kU resistor.
Not. 12: See AN-450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section titled "Surface Mount" found in a current National
Semiconductor Unoar Data Book lor other methods of soldering surface mount devices.

5-5

•

DC Electrical Characteristics (Note 1. Note 6) (Continued)
LM34
Parameter

Accuracy. LM34. LM34C
(Note 7)

Accuracy. LM34D
(Note 7)

Conditions

= +77"F
= O°F
= TMAX
= TMIN
TA = +nOF
TA = TMAX
TA = TMIN
TA
TA
TA
TA

Typical

Tested
limit
(Note 4)

±0.8
±1.0
±1.6
±1.6

±3.0
±3.0

±1.0

TMIN ,,;: TA";: TMAX

.±0.8

Sensor Gain
(Average Slope)

TMIN";: TA";: TMAX

+10.0

+9.8,
+10.2

Load Regulation
(Note 3)

TA = +77"F
TMIN";: TA";: +150°F
0,,;: IL";: 1 mA

±OA

±2.5

Line Regulation (Nofe 3)

TA = +77"F
5V,,;: Vs";: 30V

Change of Quiescent
Current (Note 3)

±0.5

±4.0
±4.0

OF
OF
OF

±0.4

±1.0

OF

+10.0

+9.8,
+10.2

mVI"F. min
mV/oF. max

±8.0

mVlmA
mV/mA

±0.2

mVIV
mVIV

154

IJoA

159

/loA
/loA

5.0

/loA
/loA

±1.2
±1.8
±1.8

±3.0

±OA

±2.5

100

181

0.5
1.0

3.0

5.0

+0.30

+0.7

+0.30

+0.7

/loA/oF

+3.0

+5.0

+3.0

+5.0

OF

+0~5
+1.0

3.0

= T MAX for 1000 hours

OF
OF
OF
OF

±2.0

75
118
76
117

4V ,,;: Vs ,,;: 30V. + nOF
5V,,;: Vs";: 30V

Tj

±3.0
±3.0
±4.0

±0.8
±1.0
±1.6
±1.6

±0.1

100

Long-Term Stability

Units
(Max)

±0.Q1
±0.02

75
131
76
132

In circuit of Figure 1.
IL = 0

Design
limit
(Note 5)

±0.2

= +5V. +noF
= +5V
= +30V. +77"F
= +30V

Minimum Temperature
for Rated Accuracy

Tested
Limit
(Note 4)

±0.5

±0.1

Temperature Coefficient
of Quiescent Current

Typical

±8.0

±0.01
±0.02

Vs
Vs
Vs
Vs

Design
Limit
(Note 5)

±2.0

Nonlinearity (Note 8)

Quiescent Current
(Note 9)

LM34C. LM34D

178
103

±O.16

±O.16

5-6

/loA

103

OF

Typical Performance Characteristics
Thermal Resistance
Junction to Air
45

720

~

~

540

z

:!5

r:i

-'
c
lIE

15
:z:

...

120

40

~

..

~~t
-ITOr
o
400

20

8...

15
10

:E

180

;::

5

o
800

1200 1600

2000

ci!
z

BO

~

60

..
....
~

.
z

40

6.0

20

~

I

,.

I 1,"

~

1
,,~ ~l

~~

TO·92

o

800

1200

1600

5.0

:i
~

TIME IMINI

Quiescent Current vs.
Temperature
(In Circuit of Figure 1)

r--r-...,.--.---.....---.

160

...~

1-'-'--+--+""';--,

4.0

ia
...
§

1-'-'--+--::I!Jif-+-,

It

ill

V

3.0

.

r=_~-f

:;

2.0 ............._......L_--'-_.......- - I
-100
100 200
300 400

TIME (SEC)

3.0 HIOIIiJ,\;;,-f-f-1---o!

i

!!!

100

::>

CI

BO

f

i15

~

V

il!

L

::>

~

~

:IE!
~

60

-100

100

60
40
20

200

300

100

TEMPERATURE (OF)

100

200

300

Accuracy vs. Temperature
(Guaranteed)

~

~

, ./

80

i'" ,

TEMPERAIURE 1°F)

180

120

100

-100

r-1-.-.--.--r.=.,....,.....,

4.0

200

140

~

IA'

120

Accuracy vs. Temperature
(Guaranteed)

220

::>

...

140

TEMPERATURE 1°F)

Quiescent Current vs. Temperature (In Circuit of Figure 2;
-Vs = -5V, R1 = 100k)

160

I
o

~

-20

~

I

40
20

2000

~

til

60

-20

400

w

"

·~.92

......

)~

'I'

Minimum Supply Voltage
vs. Temperature

Thermal Response In
Stirred 011 Bath

:I
!I

80

AIR VELOCITY (FPMI

120
TJ46 """
~

:3
!I
u:

AIR VELOCITY (FPM)

100

100

w

25

~

360

~

35
3D

!Z

o

...~

Thermal Response In
Stili Air

Thermal Time Constant

200

5.0
4.0
3.0
2.0
1.0
0
-1.0
-2.0
-3.0
-4.0
-5.0
-100

300

TEMPERATURE (OFI

100

200

300

400

TEMPERATURE (OF)
TLIH/6685-5

Noise Voltage

Start·Up Response
6

1600 rTTTTTmrrrnrrmr"TTrmm-rmmn
1400

~
~...
~

z

H-tttlllllt-ttlltttll!-+ttHltt-ftHCItIl

1200
1000 ~

.~~

~~

1.5

800

600

1.0

400

0.5

~

200
0
10

100

lk

10k

o

lOOk

FREQUENCY (Hz)

10 20 30 -40 50 60

TlME (microsecond,)
TUH/8685-21

5-7

Typical Applications
The LM34 can be applied easily in the same way as other
integrated-circuit ,temperature sensors. It can be glued or
cemented to a surface and its temperature will be within
about O.02"F of the surface temperature. This presumes
that the ambient air temperature is almost the same as the
surface temperature; if the air temperature were much higher or lower than the surface temperature, the actual temperature of the, LM34' die would be at an intermediate temperature between the surface temperature and the air temperature. This is expecially true for the TO-92 plastic package,
where the copper leads are the principal thermal path to
carry heat into thei device, so its temperature might be closer to the air temperature than to the surface temperature.

used to insure that moisture cannot corrode the LM34 or its
connections.
These devices are sometimes soldered, to a' small, lightweight heat fin to decrease the'thermal time, constant and
speed up the response in slowly-moving air,' On the other
hand, a small thermal mass may be added to the sensor to
give the steadiest reading despite small deviations in the air
temperature.

Capacitive Loads
Like most micropower circuits, the LM34 has a limited ability
to drive heavy capacitive loads. The LM34 by itself is able to
drive 50 pF without special precautions. If he,avier loads are
anticipated, it is easy to isplate or decouple the load with a
resistor; see Figure 3. Or you can improve the tolerance of
capacitance with a series R-C damper from output to
ground; see Figure 4. When the LM34 is applied with a
499.0. load resistor (as shown), it is relatively immune to
wiring capacitance because the capacitance forms a bypass
from ground to input, not 'on the output. However, as with
any linear circuit connected to wires i!1 a l:I.ostile' environment, its performance can be affected adversely by intense
electromagnetic sources such as relays, radi,o transmitters,
motors with arcing brushes, SCR~s tranSients, etc., as its
wiring can act as a receiving antenna and its internal junctions can act as rectifiers. For best results in such cases, a
bypass capaCitor from VII';' to ground and a series 'R-C
damper such as 75.0. in series with 0.2 or 1 p.F from output
to ground are often useful. These are shown in the following
circuits.

To minimize this problem, be sure that the wiring to the
LM34, as it leaves the device, is held at the same temperature as the surface of interest. The easiest way to do this is
to cover up these wires with a bead of epoxy which will
insure that the leads and wires are all at the same temperature as the surface, and that the LM34 die's temperature will
not be affected by the air temperature.
The TO-46 metal package can also be soldered to a metal
surface or pipe without damage. Of course in that case, the
V _ terminal of the circuit will be grounded to that metal.
Alternatively, the LM34 can be mounted inside a sealed-end
metal tube, and can then be dipped into a bath or screwed
into a threaded hole in a tank. As with any IC, the LM34 and
accompanying wiring and circuits must be kept insulated
and dry, to avoid leakage and corrosion. This is especially
true if the circuit may operate at cold temperatures where
condensation can occur. Printed-circuit coatings and varnishes such as Humiseal
and epoxy paints or dips are often,
,
Temperature Sensor,
Single Supply, - 51r to + 30lrF

+;s

LM34'J-~+}

t---+- _
lN914 ~ ..

HEAVY CAPACITIVE LOAO, WIRING, ETC.
TL./H/66B5-7

VOUl

FIGURE 3. LM34 with Decoupllng from Capac,itive Load

18k

f-

r -,- - ....- - - - - ' - -

10%

~,

1

TLlH/6685-6

"""

I

LM34

I

1,1
'1\
I.F'!'
.
1
7&n

IL. ___ ....._ _...........+_
0,1 "F BYPASS
(OPTIONALI

\
HEAVY CAMCITIVE LOAD. WIRING. ETC.
TLlH/6685-B

FIGURE 4. LM34 with R-C Damper
Temperature Rise of LM34 Due to Self-Heating (Thermal ReSistance) ,
Conditions
Still air
Moving air
Still oil
Stirred 011
(Clamped to metal,
infinite heat sink)

TO-46,
No Heat Sink

TO-46,
Small Heat Fin°

To-92,
No Heat Sink

720°F/W
180"F/W
180"F/W
9lrF/W

180°F/W
72°F/W
72"F/W
54°F/W

324°F/W
162"F/W
162°F/W
81°F/W

TO-92,
Small Heat Fin"
252"F/W
126"F/W
126"F/W,
72°F/W

. S0-8
No Heat Sink

SO-8
Small Heat Fin° °

4(jO"F/W
190°F/W

200°F/W
160°F/W

(43°F/W)

(95°F/W)

'Wakefield type 201 or I' disc of 0.020' sheet brass, soldered to case. or similar.
"T0-92 and S0-8 packages glued and leads soldered to I' square of

v.,' printed circuit board with 2 oz copper foil, or similar.
5-8

,-----------------------------------------------------------------------------, r
5:
Co)

Typical Applications (Continued)

~
r
5:
Co)

Two-Wire Remote Temperature Sensor
(Output Referred to Ground)

Two-Wire Remote Temperature Sensor
(Grounded Sensor)
5V

~r

5V

5:

CA)
~

+

4990
1%

o
......

= 10mVl'F (TA+3'F)

VOUT
FROM

+3'F TO +

HEAT
FINS

100'F

;;:a--,........-

HEAT
FINS

...."""'....-

r

5:
Co)

TWISTED PAIR

~

VOUT a lD mV/oF (TA+3°F)
FROM +3°FTO +IDDoF

~

r
5:
Co)

TWISTEDMIH

~_.,..._

o

~

c

TUH/6685-9

TUH/6685-10

4-to-20 mA Current Source
(0 to + 100"F)

Fahrenheit Thermometer
(Analog Meter)
+5V

r - -...------1.-+.-+6VTO +30V

2N2107

-""'-"'02
1%

62.5
0.5%

TL/H/6685-12

TUH/6685-11

Expanded Scale Thermometer
(50" to 80" Fahrenheit, for Example Shown)

Temperature-to-Dlgltal Converter
(Serial Output, + 128'F Full Scale)

r--------...--....---+

+9V
-"""'-"OUT

2k

2600

5V

+

t--'\fV¥_..JVIh-..,

SEHIALOATA
OUTPUT

100"".60 mV
FULL SCALE

GNO
CLOCK
io-_ _ ENABLE

10k

.....- -...-_----GROUNO

L-_-+_~

TL/H/6685-14

TUH/8685-13

5·9

•

Typical Applications (Continued)
LM34 with Voltage-to-Frequency Converter and Isolated Output
(3"F to + 3000F; 30 Hz to 3000 Hz)
.

OUT

100 ko.
0.01 pF

TL/H/6685-15

Bar-Graph Temperature Display
(Dot Mode)
67
+7V

68

20~F*
~~

18

I

---I'
HEAT
FINS

~

LM34

-

V~

71

72

17

16

73

74 75

, , , ,, .,~ ., r ., ,.. ,, ,, ,r .,.~ .~ ,,2o
~ ~ . ~ ~ ~i~
GOk

~

15

14

13

12

"

LM3914

-¥ +~:

4

5

6

7

8

9

II

17

18

10

16

15

'"

14

~

13

12

II

10

'LM3914
II

-:Ii ..~~
..

Ik'

4

5

6

7

g
'NI:

I

8k

.

+7V

LEOS

( +2.25V)

I

Va

Vc
4020'

1.Ok'

T'~F ~
.

'"

"

lOUT

+

-

70

., , ,~ ,~ ~ ~ ,

":"

+

69

/, 50011

....

4020'

4020'

Ik'

2k'

~

-;: ~Ik

/, ·Ik
':.ir

TLlH/6685-18

•=

I % or 2% film resistor

-Trim RB for VB

= 3.525V

-Trim RC for Vc = 2.725V
-Trim RA for VA = 0.OB5V
-Example, VA

5-10

+

40 mVl'F X T AMBIENT

= 3.2B5V' at BO'F .

Typical Applications (Continued)
Temperature-to-Dlgltal Converter
(Parallel TRI-STATE® Outputs for Standard Data Bus to JLP Interface, 128 'F Full Scale)

r-................ ................................
~

............-+5V

~~

16k

+

OUT

IN

PARALLEL DATA
OUTPUT

GNO
l5n

+
I.F

INTR

YREF
0.64Y

lk

Cs
iii
L.-_ _ _ iiii

2k

r.............................................................................-GROUND

TLlH/668S-17

Temperature Controller
+15V
3k

HEATER
INDICATOR

TEMP. ADJUST
. SDk

2k

\ ~ ________________
~ JI

I

I

I

THERMALLY COUPLED
SUPOINT
(10 mVI"F)

ACTUAL
TEMPERATURE
(10 mV/'F)
TLlH/B68S-18

Block Diagram

1.590 VPTAT
(AT 77'F)

........~~-+....,

~t-

+Vs

QZ

VaUT=10mV/'F

Va

0.865 RZ
nR1

!

RZ

TLlH/B685-19

5-11

tflNational Semiconductor

LM35/LM35A/LM35C/LM35CA/LM35D
Precision Centigrade Temperature Sensors
General Description
available packaged in hermetic TO-4S transistor packages,
The LM35 series are precision integrated-circuit temperature sensors, whose output voltage is linearly proportional to
while the LM35C, LM35CA, and LM35D are also available in
the Celsius (Centigrade) temperature. The LM35 thus has
the plastic TO-92 transistor package. The LM35D is also
an advantage over linear temperature sensors calibrated in °
available in an 8-lead surface mount small outline package
and a plastic TO-202 package.
Kelvin, as the user is not required to subtract a large con:
stant voltage from its output to obtain convenient Centi' '
grade scaling. The LM35 does not require any external calibration or trimming to provide typical accuracies of ± %OC
• Calibrated directly in ° Celsius (Centigrade)
at room temperature and ± %OC over a full - 55 to + 150~C
• Linear + 10.0 mV/oC scale factor
temperature range. Low cost is assured by trimming and
• 0.5°C accuracy guaranteeable (at + 25°C)
calibration at the wafer level. The LM35's low output imped• Rated for full - 55° to + 1500C range
ance, linear output, and precise inherent calibration make
• Suitable for remote applications
interfacing to readout or control circuitry especially easy. It
• Low cost due to wafer-level trimming
can be used with single power supplies, or with plus and
minus supplies. As it draws only SO p,A from its supply, it has
• Operates from 4 to 30 volts
very low self-heating, less than 0.1°C in still air. The LM35 is
• Less than SO p,A current drain
rated to operate over a-55° to + 150°C temperature
• Low self-heating, 0.08°C in still air
range, while the LM35C is rated for a -40° to +1100C
• Nonlinearity only ± %OC typical
range (-10° with improved accuracy). The LM35 series is
• Low impedance output, 0.1 {} for 1 mA load

Features

Connection Diagrams
TO-46
Metal Can Package'

so-a

TO-92
Plastic Package

Small Outline Molded Package

~

VOUTOa +Vs

BOTTOM VIEW

BOTTOM VIEW

,N.C.

2,

7

N.C.

N.C.

3

6

N.C.

GND

4,

5

N.C.

TUH/5516-2
TUH/5516-1

'Case Is connected to negative pin (GND)

Order Number LM35H, LM35AH,
LM35CH, LM35CAH or LM35DH
See NS Package Number H03H
TO-202
Plastic Package

TL/H/551B-21

Order Number LM35CZ,
LM35CAZ or LM35DZ
See NS Package Number Z03A

Top View
N.C. = No Connection

Order Number LM35DM
See NS Package Number M08A

Typical Applications
+Vs

I'·r~=.'"~,.
TL/H/5516-3

FIGURE 1. Basic Centigrade
Temperature
Sensor (+ 2"C to + 1500C)

TUH/551B-4
Choose Rt = - Vs/50 pA
Vour= +1,500 mVat +150'C

+Vs

GND

= +250 mVat +25"C

Your

= -550 mVat -55'C
TL/H/5516-24

FIGURE 2. Full·Range Centigrade
Temperatura SenIOr

Order Number LM35DP
See NS Package Number P03A

5-'2

r-

Absolute Maximum Ratings

3:
w
U'I
.......

(Note 10)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

+S5Vto -0.2V

Output Voltage

+6Vto -1.0V

Output Current

10mA

Storage Temp., TO-46 Package,

-60'Cto +180'C

TO-92 Package,

-60'C to + 150'C

SO-8 Package,

-65'C to + 150'C

TO-202 Package,

-65'C to + 150'C

SO Package (Note 12):
Vapor Phase (60 seconds)

215'C

Infrared (15 seconds)

220'C

ESD Susceptibility (Note 11)

2500V

Specified Operating Temperature Range: T MIN to T MAX
(Note 2)

r-

3:
w
U'I

»

.......

r-

3:
(;.)
U'I

LMS5, LMS5A

- 55'C to + 150'C

LMS5C, LMS5CA

-40'C to + 110'C

LMS5D

O'C to + 100'C

o.......
r-

3:
w
U'I

o

»
.......

Lead Temp.:

r-

TO-46 Package, (Soldering, 10 seconds)

SOO'C

TO-92 Package. (Soldering. 10 seconds)

260'C

3:
w

+2S0'C

o

TO-202 Package, (Soldering, 10 seconds)

U'I

Electrical Characteristics (Note 1) (Note 6)
LM35A
Parameter

Accuracy
(Note 7)

Conditions

TA= + 25'C
TA= -10'C
TA=TMAX
TA=TMIN

Typical
±0.2
±O.S
±0.4
±0.4

Tested
Limit
(Note 4)
±0.5
±1.0
±1.0

Nonlinearity
(Note 8)

TMINsTAsTMAX

±0.18

Sensor Gain
(Average Slope)

TMINsTAsTMAX

+10.0

+9.9,
+10.1

Load Regulation
(NoteS)OsILs1 rnA

TA= +25'C

±OA

±1.0

TMINsTAsTMAX

±0.5

Line Regulation
(NoteS)

TA= +25'C
4VsVssSOV

±0.01
±0.02

±0.05

Quiescent Current
(Note 9)

Vs=
Vs=
Vs=
Vs=

56
105
56.2
105.5

67

Change of
Quiescent Current
(NoteS)

+5V, +25'C
+5V
+SOV, +25'C
+SOV

4VsVssSOV. +25'C
4VsVssSOV

Temperature
Coefficient of
Quiescent Current

LM35CA
Design
Limit
(Note 5)

±0.35

Typical

Tested
Limit
(Note 4)

±0.2
±O.S

±0.5

±OA
±OA

±1.0
± 1.5

±0.15

±0.3

'C

+10.0

+9.9,
+ 10.1

mV/,C

±OA

±1.0

±0.5
±0.01
±0.02

±0.05

±O.1

67

133

56
91
56.2
91.5

1.0

2.0

0.2
0.5

+0.39

+0.5

+2.0

0.2
0.5

Minimum Temperature
for Rated Accuracy

In circuit of
Figure t.IL =0

+1.5

Long Term Stability

TJ=TMAX. for
1000 hours

±0.08

68

1.0

Units
(Max.)

'C
'C
'C
'C

± 1.0

±3.0

131

Design
Limit
(Note 5)

±3.0

mV/mA
mV/mA

±O.1

mV/v
mV/v

116

/1- A
/1- A
/1- A
/1- A

2.0

/1- A
/1- A

+0.39

+0.5

/1-Al'C

+1.5

+2.0

'C

±0.08

114
68

'C

Note 1: Unless otherwise noted. these specifications apply: -55'C:>TJ:> + 150'C for the LM35 and LM35A; -40':>TJ:> + 110'C for the LM35C and LM35CA; and
O':>TJ:> +100'C for the LM35D. Vs= +5Vdc and ILOAO=50 p.A, in the circuit of Figure 2. These specifications also apply from +2'C to TMAX in the circuit of
Figure 1. Specifications in boldface apply over the full rated temperature range.
Note 2: Thermal resistance of the TO-46 package is 400'C/W. junction to ambient, and 24'C/W junction to case. Thermal resistance of the TO-92 package is
180'C/W junction to ambient. Thermal resistance of the small outline molded package Is 220'C/W junction to ambient. Thermal resistance of the TO-202 package
is 85'C/W junction to ambient. For additiOnal thermal realstance Information see table In the Applications section.

5-1S

Electrical Characteristics (Note 1) (Note 6)

(Continued).
LM35C, LM35D

LM35
Parameter

Conditions

Typical

Accuracy,

TA= +25'C

±0.4

LM35, LM35C

TA= -10'C

±0.5

(Note 7)

TA=TMAX

±O.B

TA=TMIN

±O.B

Tested

Design

Limit

Limit

(Note 4)

(Note 5)

Typical

±0.4

±1.0
±1.5
±1.5

Design

Units

Limit

Limit

(M!lx.)

(Note 4)

(Note 5)

±1.0

'C

±0.5

±1.5

'C

±O.B

±1.5

'C

±O.B

±2.0

'C

Accuracy,
LM35D

TA= + 25'C
TA=TMAX

±0.6
±0.9

(Note 7)

TA=TMIN

Nonlinearity

TMIN:S:TA:S:TMAX

±0.3

TMIN:S:TA:S:TMAX

+10.0

±0.5

Tested

±1.5

'C
±2.0

'C

±0.9

±2.0

'C

±0.2

±0.5

'C

+9.8,

mVl'C

(Note B)
Sensor Gain
(Average Slope)
Load Regulation

TA=+25'C

±0.4

(Note3)0:S:IL:S:1 mA

TMIN:S:TA:S:TMAX

±0.5
±0.01

Line Regulation

TA=+25'C

(Note 3)

4V:S:VS:S:30V

Quiescent Current

Vs= +5V, + 25'C

(Note 9)

VS=+5V

105

VS= +30V, +25'C

56.2

VS=+30V

+10.2

±2.0

±0.4
±5.0

±0.5

±0.2

±0.02

±0.1

±0.02
56

+10.0

+9.8,
+10.2

±0.01

BO

56
158

B2

±0.1

mV/mA
mVIV

±0.2
BO

mVIV
/LA

138
B2

91.5
0.2

/LA
/LA

141
2.0

/LA

Change of

4V:S:Vs:S:30V, + 25'C

0.2

Quiescent Current
(Note 3)

4V:S:Vs:S:30V

0.5

3.0

0.5

3.0

/LA

+0.39

+0.7

+0.39

+0.7

/LAf'C

+1.5

+2.0

+1.5

+2.0

'C

Temperature

2.0

mV/mA
±5.0

91
56.2

161

105.5

±2.0

/LA

Coefficient of
Quiescent Current
Minimum Temperature

In circuit of

for Rated Accuracy

Figure 1, IL =0

Long Term Stability

TJ=TMAX,for
1000 hours

±O.OB

±O.OB

'C

Note 3: Regulation is measured at constant iunction temperature, using pulse testing with a low duty cycle. Changes in output due to heating effects can be
computed by multiplying the internal dissipation by the thermal resistance.
Note 4: Tested Umits are guaranteed and 100% tested in production.

Note 5: Design Limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage ranges. These limits are not used to
calculate outgoing quality levels.
Note 6: Specifications in botdface apply over the full rated tempereture range.
Note 7: Accuracy is defined as the error between the output voltage and 10mv/'C times the device's case temperature, at specified conditions of voltage, current,
and temperature (expressed in ·C).
Note 8: Nonlinearity is defined as the deviation of the output-voltage-versus-temperature curve from the best-fit straight line, over the device's rated tempe~ture
range.

Note 9: Quiescent current is defined in the circuit of Figure I.
Note 10: Absolute Maximum Ratings indicate IimHs beyond which damage to the device may occur. DC and AC electrical specifications do not apply when
operating the device beyond its rated operating conditions. See Note t.
Note 11: Human body model, 100 pF discharged through a 1.5 kn resistor.
Note 12: See AN-450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section titled "Surface Mount" found in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.

5-14

Typical Performance Characteristics
Thermal Resistance
Junction to Air

Thermal Time Constant

400

~

E

~

300

~

z

I! 200

i

\
"

1100

m

o

.
I-

z
j!

~
...

TII-46

~

:E

;::

TO-92

o

400

800 1200 1600
AIR VELOCITY (FPM)

120

...:3

80

;;l

60

iI£
z

Ii:

"co

40

ffi

20

.
a:

-~
.... ~
I.... TII-92
II
1

w

25
20
15
10
5

I" J"'o

~

.

2

40

.L~

60

I

20

~

-20

o

400 800 1200 1600 2000
AIR VELOCITY (FPM)

2

4

TIME (MINUTES)

Quiescent Current
vs. Temperature
(In Circuit of Figure 1.)

Minimum Supply
Voltage vs. Temperature
4.4 r-1-r--r-...-'--..--r-l,...,

160

4.2

140
1120

3.8 HH--t-+-t~tIF~T-I
3.6 HH--t--bA.~rIF-+-H
§! 3.4 HH,jCJoq,I£f-++-H
3.2 H-71""'rIF:. 3.0 ~:.oor.""I-+2.8
2.6
2.4 L..J-L.-1......I..-.l-.L....L-f..-1...J
-75 -25 25
75
125 175
TEMPERATURE ('C)
w

•

I-

!!j

100

"

a:

B 80

i

l-

.

4
6
TIME (SECONDS)

Ii:
"co

ill

~ 4.0

~.

80

I-

i!

.~

o

T~.46

TO·92

o

~

;;l
z

\

,\

2000

~

-20

!! 100

o

Thermal Response in
Stirred Oil Bath
!!100

45
40
35
30

l .!

..
f:l
5

60

"""

1.00'

40
20

o
-75 -25

25
75
125
TEMPERATURE ('C)

175

TLlH/5516-17

Quiescent Current
vs. Temperature
(In Circuit of Figure 2.)
2.0

180

1.5

~160

I
i

140
~ 120

100
fa 80

~

Accuracy vs. Temperature
(Guaranteed)

2l1li

60

1.00'

.1'

40
-75

I

"
"
"

-25 25
75
125
TEMPERATURE ('C)

LM35

1.0

I""'" ~~

0.5

1"""'"""

::!

~-0.5

..

•

~-1.0
I!! -1.5

I.

~~

1uI~_r-

m
::!

IIfI

0

,;;;;;;:;;j",

~-O.5
~-1.0

~

I-

LJ35J-t-

..",

-2.0
-75

175

TYPICAL

Accuracy vs. Temperature
(Guaranteed)
2.5
2.0
~ 1.5
"' 1.0
0.5

-25
25
75
125
TEMPERATURE ('C)

175

........

1rIL1:"Ir~

,. ,

LM35D
LM35C

,,

~t+
r"t. rrt'f ~~ ""rL~3~CA

iIi-l.S
-2.0
-2.5
-75

I

LM35

1ow..1'11

TYP1CAL

I....

',t(f

fr'A r"1'110

-25

LM35C-

L~3~D-

25
75 125
TEMPERATURE ('C)

175

TL/H/5516-18

Noise Voltage

Start-Up Response

III

16l1li
14l1li
1200

~
~

10IIII

,s.

6l1li

III
co

6l1li

'"

.:~

-

4l1li

£
S

,:>

2!10

o

10

1l1li

lk

10k

~

0.6

lOOk

0.4
0.2

o

"
v

0102030405060

FREQUENCY (Hz)

llME (microseconds)
TLlH/5516-22

5-15

cr------------------------------------------------------------an
Cf)

:;
~
~
::::E

...(3
.......
an
Cf)
::::E

~
Cf)

.......an
...
::::E
Cf)

::::E

Applications

The LM35 can be applied easily in the same way as other
integrated-circuit temperature sensors. It can be glued or
cemented to a surface and its temperature will be within
about O.Ol°C of the surface temperature.
This presumes that the ambient air temperature is almost
the same as the surface temperature; if the air temperature
were much higher or lower than the surface temperature,
the actual temperature of the LM35 die would be at an intermediate temperature between the surface temperature and
the air temperature. This is expecially true for the TO-92
plastic package, where the copper leads are the principal
thermal path to carry heat into the device, so its temperature might be closer to the air temperature than to the surface temperature.
To minimize this problem, be sure that the wiring to the
LM35, as it leaves the device, is held at the same temperature as the surface of interest. The easiest way to do this is
to cover up these wires with a bead of epoxy which will
insure that the leads and wires are all at the same temperature as the surface, and that the LM35 die's temperature will
not be affected by the air temperature.

The TO·46 metal package can also be soldered to a metal
surface or pipe without damage. Of course, in that case the
V - terminal of the circuit will be grounded to that metal.
Alternatively, the LM35 can be mounted inside a sealed-end
metal tube, and can then be dipped into a bath or screwed
into a threaded hole in a tank. 'As with any IC, the LM35 and
accompanying wiring and circuits must be kept insulated
and dry, to avoid leakage and corrosion. This is especially
true if the circuit may oper!lte at cold temperatures where
condensation can occur. Printed-circuit coatings and varnishes such as Humiseal and epoxy paints or dips are often
used to insure that moisture cannot corrode the LM35 or its
connections.
These devices are sometimes soldered to a small light·
weight heat fin, to decrease the thermal time constant and
speed up the response in slowly-moving air. On the other
hand, a small thermal mass may be added to the sensor, to
give the steadiest reading despite small deviations in the air
temperature.

Temperature Rise of LM35 Due To self·heating (Thermal Resistance)
TO·C6,
T0-46,
TO·92,
T0-92,
SO-8
SO-8
TO·202
TQ.202 '"
no heat sink small heat fin' no heat sink small heat fin" no heat sink small heat fin" no heat sink small heat fin
Still ai,
Moving ai,

400"C/W
lOO'C/W

Still oil

IOO"C/W
50"C/W

Stirred oil
(Clamped to metal,
Infinite heat sink)

100"C/W

180"C/W

140'C/W

220"C/W

40"C/W
40"C/W
30"C/W

90"C/W

70"C/W
70"C/W

105'C/W

90'C/W

45'C/W

40'C/W

IIO'C/W
90'C/W

85'C/W
25'C/W

(55'C/W)

(24'C/W)

60"C/W
40'C/W

(23'C/W)

, Wakefield type 201, 0' I" disc of 0.020" sheet brass, soldered to case, or similar.
.. TQ.92 and SO-8 packages glued and leads soldered to I" square of 'A." printed circuit board with 2 oz. foil or similar,

Typical Applications (Continued)

I

+
LM35

r----

HEAVY CAPACITIVE LOAD. WIRING. ETC.

:l'DUTiiiiT'II2k~-:eE===::t TO AHIGH·IMPEDANCE LOAD

O,I,.F BYPASS
OPTIONAL

T

I

....L.

"'1'
I

l

IL. ___ _

TL/H/5516-19

FIGURE 3. LM35 with Decoupling from Capacitive Load

T +

LM35

-

HEAVY CAPIICITIVE LOAD. WIRING, ETC.

lUO!!!UT-r--lE===~
r
75

;::~I,.F
TL/H/5516-20

FIGURE 4. LM35 with R·C Damper
capacitance because the capacitance forms a bypass from
ground to input, not on the output. However, as with any
linear circuit connected to wires in a hostile environment, its
performance can be affected adversely by intense electromagnetic sources such as relays, radio transmitters, motors
with arcing brushes, SCR transients, etc, as its wiring can
act as a receiving antenna and its internal junctions can act
as rectifiers. For best results in such cases, a bypass capacitor from Y,N to ground and a series R-C damper such as
750 in series with 0.2·or 1 ",F from output to ground are
often useful. These are shown in Figures 13, 14, and 16.

CAPACITIVE LOADS
Like most micropower circuits, the LM35 has a limited ability
to drive heavy capacitive loads. The LM35 by itself is able to
drive 50 pf without special precautions. If heavier loads are
anticipated, it is easy to isolate or decouple the load with a
resistor; see Figure 3. Or you can improve the tolerance of
capacitance with a series R·C damper from output to
ground; see Agure 4.
When the LM35 is applied with a 2000 load resistor as
shown in Figure 5, 6, or 8, it is relatively immune to wiring

5·16

r-----------------------------------------------------------------------------'r

5:
Co)

Typical Applications (Continued)

~

~

5V

Co)

~

HEAT
FINS

~

TWISTED PAIR

Co)

~
.....

~

Co)

UI

HEAT
ANS

~

TWISTED PAIR

TL/H/5516-6

FIGURE 6. Two-Wire Remote Temperature Sensor
(Output Referred to Ground)
TL/H/5516-5

FIGURE 5. Two-Wire Remote Temperature Sensor
(Grounded Sensor)
,. - - - -.~--.....:--- 5V

+Vs

I

I
0.1,.,. I
BYPASS - ' OPTIDNAL T~-""--'

....._+-]VOUT

I
I

TWISTED PAIR

2k
III

I
L ___ 1-_ _~~""'_ ~~~=~~~~~(~~~I!NT+10~C)

TL/H/5516-7

FIGURE 7. Temperature Sensor, Single Supply, -55· to
+ 150·C

TLlH/5516-B

FIGURE 8. Two-Wire Remote Temperature Sensor
(Output Referred to Ground)
+Vs

r - - -....- - - - - -............ +5V TO +3OV

(6VTO 20V)

a.....:;=~<5D

YoUT=

+1.0 mv/oF
TL/H/5516-9

FIGURE 9. 4-To-20 rnA Current Source (O"C to

+ 100·C)

TLlH/5518-10

FIGURE 10. Fahrenheit Thermometer

5-17

~

Co)

UI

C

c

In
Cf)

:E
...J

~

~----------------------------------------------------------------------,

Typical Applications (Continued)

5V

BY

Cf)

:E

....

(3

111O,.A.

In

FULL·SCALE

60mV

Cf)

:i

....
....
~

Cf)

~

TL/H/5516-11

FIGURE 11. Centigrade Thermometer (Analog Meter)

TUH/5516-12

;t;

FIGURE 12. Expanded Scale Thermometer
(50" to 80" Fahrenheit, for Example Shown)

Cf)

....

:E

~-------------1~---------1~--~5V

SERIAL
DATA OUTPUT

CLOCK
'------.. ENABLE

TUH/5516-13

FIGURE 13. Temperature To Digital Converter (Serial Output) (+ 12S"C Full Scale)

r-------~------------------~-----------5V
16k

PARALLEL

IN

DATA

OUTPUT

¥REF

----r..,.......,.a

O.64V ....
2k

cs

.......----.. iiii
.......- -...... Wii

'---~--~-----~--~~----GND

TL/H/5516-14

FIGURE 14. Temperature To Digital Converter (Parallel TRI-5TATE® Outputs for
Standard Data Bus to p.P Interface) (128"C Full Scale)

5-18

Typical Applications (Continued)
------------'F----------~

20k
67

68

69

70

71

72

73

74

75

76

7V
*20,.1'

,.

~ n'. ~~ n 'n ~~ n

':'

n m

~

~

+
HEAT

FINS

~

LM35

4

!3

5

f

10

~

~

~

.., 2OLEOs
10

18

LM3914

6

7

8

I.!.. WI

Uk·

7V

~

I.

LM3914

-¥

~

n
I~~ 7"; ~~ n 7~ t~ 7~ ~~ n 7";
F-

~~

18

-..11

~

-:Ii

~3

-

7V

4

5

6

7

8 .1.9

Ne

VA

lOUT

I

~ 200·

Vc

Va
499·

499·

lk'

Uk·

Uk·

;.

Il,.1'

~c

;:

lk

lk

~

":::-

;: VnAIk

~.

--

TL/H/55t6-16

• = 1% or 2% film resislor
-Trim AB for VB = 3.075V
-Trim Ac for Vc=1.955V
-Trim AA for VA=O.075V + l00mVl'C
-Example, VA = 2.275V at 22'C

x Tamblenl

FIGURE 15. Bar-Graph Temperature Display (Dot Mode)

6V

6.8k

lk

fOUT

lOOk

0.01

~F

lOOk

47

TLlH/5516-15

FIGURE 16. LM35 With Voltage-To-Frequency Converter And Isolated Output
(2"C to + 150"C; 20 Hz to 1500 Hz)

5-19

Block Diagram

1.38 ¥lor",
~t-----~--t-..,

VuuT=ID IIIY/·C
0.125 R2

aRl

TL/H/5516-23

5-20

,-------------------------------------------------------------------------, r

""~==
U1

t!lNational Semiconductor

r

LM45B/LM45C
SOT..23 Precasion Centigrade Temperaiure Sensors
General Description

• Portable Medical Instruments

The LM45 series are precision integrated-circuit temperature sensors, whose output voltage is linearly proportional to
the Celsius (Centigrade) temperature. The LM45 does not
require any external calibration or trimming to provide accuracies of ± 2'C at room temperature and ± S'C over a full
- 20 to + 100'C temperature range. Low cost is assured by
trimming and calibration at the wafer level. The LM45's low
output impedance, linear output, and precise inherent calibration make interfacing to readout or control circuitry especiallyeasy. It can be used with a single power supply, or with
plus and minus supplies. As it draws only 120 /LA from its
supply, it has very low self-heating, less than O.2'C in still
air. The LM45 is rated to operate over a -20' to +100'C
temperature range.

•
•
•
•
•

Applications
• Battery Management
• FAX Machines
• Printers

HVAC
Power Supply Modules
Disk Drives
Computers
Automotive

Features
•
•
•
•
•
•
•
•
•
•
•

Calibrated directly in ' Celsius (Centigrade)
Linear + 10.0 mV/'C scale factor
±S'C accuracy guaranteed
Rated for full - 20' to + 100'C range
Suitable for remote applications
Low cost due to wafer-level trimming
Operates from 4.0V to 10V
Less than 120 /LA current drain
Low self-heating, 0.20'C in still air
Nonlinearity only ±O.S'C max over temp
Low impedance output, 200 for 1 mA load

Connection Diagram

Ul
SOT-23

VS

+

Order
Number

GND

3

Vo

SOT-23
Device
Marking

Supplied As

LM45BIMS

T4B

250 Units on Tape and Reel

LM45BIMSX

T4B

SOOO Units on Tape and Reel

LM45CIMS

T4C

250 Units on Tape and Reel

LM45CIMSX

T4C

SOOO Units on Tape and Reel

TLlH/11754-1

Top View
See NS'Package Number M03B
(JEDEC Registration TO-2S6AB)

Typical Applications
+VS

+Vs

(4.DV TO 10V)

(4.0V TO 10V)

$
LM45
_

~VOUT

OUTPUT
VOUT
(10 mv/oe x Temp °e)

=

VOUT
VOUT

=

=

+ 1,000 mV at + 100 0
+250 mV at +25 o

e

TtRl

e

-Vs

TL/H/I1754-S

FIGURE 1. Basic Centigrade Temperature
Sensor (+ 2.5'C to + 100'C)

Choose Rl

=

-VS/SO,.A

VOUT= (10 mV/'C

x

TLlH/11754-4

Temp 'C)

VOUT= +1,000 mVat +100'C
= +250 mVal +2S'C
= -200 mVat -20'C

FIGURE 2_ Full-Range Centigrade
Temperature Sensor (- 20'C to + 100'C)

5-21

""==

~

Absolute Maximum Ratings (Note 1)
Supply Voltage
Output Voltage
Output Current
Storage Temperature
Lead Temperature
SOT Package (Note 2):
Vapor Phase (60 seconds)
Infrared (15 seconds)

+12Vto -0.2V
+Vs + 0.6Vto -1.0V
10mA
-65·Cto +150·C

ESO Susceptibility (Note 3):
Human Body Model
Machine Model

2000V
TBO

Operating Ratings (Note 1)
Specified Temperature Range
(Note 4)
LM45B, LM45C
Operating Temperature Range
LM45B, LM45C
Supply Voltage Range (+ Vs)

215·C
220·C

TMINto TMAX
- 200C to + 1000C
-40·C to + 125·C
+4.0Vto +10V

Electrical Characteristics Unless otherwise noted, these specifications apply for + Vs =

+ 5Vdc and ILOAD =
+ 50 ",A, in the circuit of Figure 2. These specifications also apply from + 2.5·C to TMAX in the circuit of Figure 1 for + Vs =
+5Vdc. Boldface limits apply for TA = T.. = TMIN to TMAX; all other limits TA = TJ = + 25·C, unless otherwise noted.
LM45B
Parameter

Conditions

Typical

LM45C

Limit
(Note 5)

Typical

Limit
(Note 5)

Units
(Umlt)

Accuracy
(Note 6)

TA=+25·C
TA=TMAX
TA=TMIN

±2.0
±3.0
±3.0

±3.0
±4.0
±4.0

·C(max)
·C(max)
·C(max)

Nonlinearity
(Note 7)

TMIN:S:TA:S:TMAX

±O.B

±O.B

·C(max)

Sensor Gain
(Average Slope)

TMIN:S:TA:S:TMAX

+9.7
+10.3

+9.7
+10.3

mVrC(min)
mVrC(max)

Load Regulation (Note B)

O:S:IL:S: +1 mA

±35

±35

mV/mA(max)

Line Regulation
(Note B)

+4.0V:S: +Vs:S: + 10V

±O.BO
±1.2

±O.BO
±1.2

mVIV(max)
mVIV(max)

Quiescent Current
(Note 9)

+4.0V:s: +VS:S: +10V, +25·C
+4.0V:S: +Vs:S: +10V

120
160

120
160

",A (max)
",A (max)

Change of Quiescent
Current (Note 8)

4.0V:s:+Vs:S:l0V

2.0

2.0

",A (max)

Temperature Coefficient
of Quiescent Current

+2.0

Minimum Temperature
for Rated Accuracy

In circuit of
Figure 1, IL =0

Long Term Stability (Note 10)

TJ = TMAX, for 1000 hours

+2.0
+2.5

±0.12

",ArC
+2.5

±0.12

·C(min)
·C

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electriCal specifications do not apply when operating
the device beyond its rated operating conditions.

Note 2: See AN-450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section tiUed "Surface Mount" found in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.

Note 3: Human body model, 100 pF discharged through a 1.5 kll resistor. Machine model. 200 pF discharged diractly Into each pin.
Note 4: Thermal resistanca of the SOT-23 package is 260"C/W, junction to ambient when attached to a printed circuH board with 2 oz. foil as shown in Figur9 3.
Note 5: Umits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 6: Accuracy is defined as the' error between the output voltage and 10 mv/oC times the device's case temperature, at speCified conditions of voltage. current,
and temperature (expressed in °C).

Note 7: Nonlinearity is defined as the deviation of the outpUl·voltage-versus-temperature curve from the best-iii slraightllne, over the device's rated temperature
range.

Note 8: Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output due to heating effects can be
computed by multiplying the internal dissipation by the thermal resistance.
Note 9: Quiescent current is measured using the circuit of Figure 1.

Note 10: For best long-term stability, any precision circuit will give best resu"s if the un" is aged at a warm temperature, andlor temperature cycled for at least 46
hours before long-term life test begins. This is especially true when a small (Surface·Mount) pari is wave·soldered; allow time for stress relaxation to occur.

5-22

Typical Performance Characteristics
To generate these curves the LM45 was mounted to a printed circuit board as shown in Figure 3.
Thermal Resistance
Junction to Air

~

400

60

.350

50
~

r"-_

8

~

'"

40

~

.

\

30

100

o

200

400

600

800

1000

10

200

AIR VELOCITY (FPM)

~
~
t;:

80

I

60

3g

20

\. = 500 "~,",,
3.5

.

160

20

30

40

50

140

i3

130

a

!1
'"

)""

120

......

'"

./

w

~

~
~

90
80

~

60

J

f

80

z

!1

50"A

75

25

50

75

100

.....

1'j

70

,...V

V

,...

~ ......

60

100 125

0

50

25

75

100

TEMPERATURE (Oc)

-1

LM4se
I
LM4s8

...

Noise Voltage

(MAX)

1400

(MAX)
(TYP)

1200

(TYP)

.......
...

r--

(TYP)

~
l

~

-2

...r I'!"I"
...rl'!"l"

-3

-4

-5
-50 -25

~

'1'~
",. ~

LM458
I
LM45C

1000

[\

800
600
400

(MIN)
(MIN)

200
0

0

25

50

75 100 125 150

TEMPERATURE (oe)

10

100

lK

10K

lOOK

FREQUENCY (Hz)
Ground Plane
on 062 copper
clad board.

Supply Voltage
VB Supply Current
":<

50

. '-,......

0

15

TEMPERATURE (Oe)

.3

25

u.1J.l...... I-i.i. LJ.J. IJ.l-

~

, vV
-25

0

..... I-i.i.

u

0

100

100

~
~
~

u

Accuracy vs Temperature
(Guaranteed)

LV

110

W: ..

.."..

1800

I =I+5.0I

:;

z

50

-50 -25

60

= +5V

90

TEMPERATURE (Oe)

+Vs

.3

~

~

2
10

I I

100 f-+VS

.3

,.,.

ILI~

2.5

Quiescent Current
vs Temperature
(In Circuit of Figure 2)

~

Quiescent Current
vs Temperature
(In Circuit of Figure 1)

..o=~

L

TIME (SEC)

-::( 150

o
TIME (MINUTES)

IL = lmA"

<>

i

o
o

o

1000

":<

E

40

~

800

110

~

o

600

20

4.5

..,..., -'"""

~

400

I

~ IIII

Start-Up Voltage
vs Temperature

-

100

60
40

AIR VELOCITY (FPM)

Thermal Response
in Stirred Oil Bath
with Heat Sink

g

-

to-

o
o

z

V

/

80

:s

t;:

\

20

;=

150

100

~
~

z

~

250

« 200

~

120

g

u

~ 300

:n
~

Thermal Response In Still Air
with Heat Sink (Figure 3)

Thermal Time Constant

Start-Up Response

I-~A =12S~C
I(
IJ

70
50

I

40

I

30

~

20
10

o
o

11
1

2

3

4

5

6

7

8

o

9 10

+VS Supply Voltage (V)

10

20

30 40

50

60

TIME (".)
TLlH111754-5

---

5-23

TLlH111754-23

FIGURE 3. Printed Circuit Board Used
for Heat Sink to Generate All Curves.
'12" Square Printed Circuit Board
with 2 oz. Foil or Similar

•

Applications
into a threaded hole in a tank. As with any IC, the LM45 and
accompanying wiring and circuits must be kept insulated
and dry, to avoid leakage and corrosion. This is especially
true if the circuit may operate at cold temperatures where
condensation can occur. Printed-circuit coatings and varnishes such as Humiseal and epoxy paints or dips are often
used to insure that moisture cannot corrode the LM45 or its
connections.

The LM45 can be applied easily in the same way as other
integrated-circuit temperature sensors. It can be glued or
cemented to a surface and its temperature will be within
about 0.2'C of the surface temperature.
This presumes that the ambient air temperature is almost
the same as the surface temperature; if the air temperature
were much higher or lower than the surface temperature,
the actual temperature of the LM45 die would be at an intermediate temperature between the surface temperature and
the air temperature.

Temperature Rise of LM45 Due to Self-Heating
(Thermal'Reslstance)
SOT-23
SOT-23"
small heat fin'
no heat sink
Still air
450'C/W
260'C/W
180'C/W
Moving air

To ensure good thermal conductivity the backside of the
LM45 die is directly attached to the GND pin. The lands and
traces to the LM45 will, of course, be part of ,the printed
circuit board, which is the object whose temperature is being measured. These printed circuit board lands and traces
will not cause the LM45s temperature to deviate from the
desired temperature.

• Heat sink used Is 'I.' square printed circuit board with 2 oz. foil with part
attached as shown In Fl{}UftJ 3.
.. Part soldered to 30 gauge wire.

Alternatively, the LM45 can be mounted inside a sealed-end
metal tube, and can then be dipped into a bath or screwed

Typical Applications

r----

CAPACITIVE LOADS
Like most micropower circuits, the LM45 has a limited ability
to drive heavy capacitive loads. The LM45 by itself is able to
drive 500 pF without special precautions. If heavier loads
are anticipated, it is easy to isolate or decouple the load with
a resistor; see Figure 4. Or you can improve the tolerance of
capacitance with a series R-C damper from output to
ground; see Figure 5.

0.1"" BYPASS
OPIIONAL

I

~

"1'

I

~ +

LM45

HEAVY CAMCITIVE LOAD, WlR1NG.

erc.

rI~OUT~I~iE===::E
15

I

IL ____

;:,1,.1'

~----~--~------_

TL/H/I1754-9

Any linear circuit connected to wires in a hostile environ'
ment can have its performance affected adversely by intense electromagnetic sources such as relays, radio transmitters, motors with arcing brushes, SCR transients, etc, as
its wiring can act as a receiving antenna and its internal
junctions can act as rectifiers. For best results in such cases, a bypass capacitor from VIN to ground and a series R-C
damper such as 75.!l in series with 0.2 or 1 p.F from output
to ground, as shown in' Figure 5, are often useful.

FIGURE 5. LM45 with R-C Damper

+Vs

lBk
1l1li

hur-J~-it=t=t=t=::E TO AHIGH·IMPEDANCE LDAD

TUH/I1754-12

FIGURE 6. Temperature Sensor,
Single Supply, - 20'C to + 100'C

TL/H/11754-8

FIGURE 4. LM45 with Decoupling from Capacitive Load

5-24

~----------------------------------------------------------------------------,

r

3:

Typical Applications (Continued)

01:00

en

lID
......
r

+Vs
(6V TO 10V)

3:

r - - -...- - - - - -........... +6V TO +IOV

01:00

en

o

10k
1%

ADJ

VOUT=

+1.0 mV/'F
26.4k

.......="+~60

1%

18k

LM4041·1.2
TL/H/11754-14

FIGURE 7. 4·to·20 mA Current Source (O'C to

1.0M
1%

+ 100'C)

TLlHI11754-15

FIGURE 8. Fahrenheit Thermometer

5V

9V

100 pl..
60 mY
FULL·SCALE

TLlH/11754-16

FIGURE 9. Centigrade Thermometer (Analog Meter)

TL/H/11754-17

FIGURE 10. Expanded Scale Thermometer
(50' to 80' Fahrenheit, for Example Shown)

r-------------.---------~------5V
IN

SERIAL
DATA OUTPUT

REf
1.28V....,I""'I'..,....

CLOCK
" " ' - - 4 ENABLE

'---+-....---+----....---- GND

TL/H/11754-18

FIGURE 11. Temperature To Digital Converter (Serial Output) (+ 128'C Full Scale)

5·25

Typical Applications (Continued)
r-----~~--------------~---------~
"'HALLEL
DATA
OUTPUT

IN

VaEF

1.28V----,.,..,..,ro'

cs

'----4iiii
'-----4Wii
~--~~'-----------------~~-------aND
TUH/I1754-19

FIGURE 12. Temperature To Digital converter (Parallel TRI-STATES Outputs for
Standard Data Bus to ,..p Interface) (128'C Full Scale)

-----------'F----------~

20k
7Y

67

68

::f20~F

68

70

. ~ ~~ ~~ 7~

":"

71

72

73

n ~~ n

-

74

7~

'-

75

7S

n

7S

7S

7U~ 7~ 7~ n
10

18

n

~

LM411

4

5

7Y

+
HEAT
ANS

~'3.

n

H

U

. ~~ ~~ ~~ Z~

H

7~

68

7~7

2D LEOs

10

18

LM3914

LJI

~

LM3914

6

7
8
Uk"

l!...W'.Ji
•

,3
7Y

4

5

6

7

8 -'_9

He

VA

lOUT

I

200*

Ve

Va
499"

.499"

Ik'

Uk·

+

r'~F

Uk"

~

~.

;.

./0 It

~B

Ik

~

~

/0 It
.ioo

TUHI11754-20

• = I % or 2% film resistor
-Trim Aa for Va = 3.075V
-Trim Ac lor Vc= 1.955V
-Trim A" lor V,,=O.075V + IOOmVI'C x Tamblont
-Example, V" = 2.275V at 22'C
.

FIGURE 13. Bar-Graph Temperature Display (Dot Mode)

5-26

Typical Applications (Continued)

lOUT

TLlH111754-21

FIGURE 14. LM45 With Voltage-To-Frequency Converter And Isolated Output
(2.5'C to + 100'C; 25 Hz to 1000 Hz)

Block Diagram
1.38 "'AT

-

...---+--t-......

VoUT .10 mV/'C

Vo

nRl

!
TLlH/11754-22

iii

5·27

ADVANCE . INFORMATION

t(JNational Semiconductor

LM50B/LM50C
Single-Supply Centigrade Temperature Sensor
•
•
•
'.
•

General Description

Battery Management
Automotive
FAX Machines
Printers
~ortable Medical Instruments

The LM50 is a precision integrated·circuit temperature sensor that can sense a -40'C to + 125'0 temperature range
using a single positive supply. The LM50's output voltage is
linearly proportional to Celsius (Centigrade) temperature'
(+ 10 mV1'0) and has a DC offset of + 500 mY. The offset
• HVAC
,
allows reading negative temperatures without the need for a . '. Power Supply Modules
negative supply. The ideal output voltage of· the LM50'
ranges from + 100 mV to + 1.75V for a -:-40'Q to + 12$'C "Features
temperature range. The LM50 does not require any external
Calibrated directly in • Celsius (Centigrade)
calibration or trimming to provide accuracies of ±3'C at
Linear + ·10.0 mV/'C scale· factor
room temperature and ±4'C over the full -40'C to
± 2'C accuracy guaranteed at + 25'C
+ 125'C temperature range. Trimming and calibration of the
Specified for full -40' to + 125·q·range
LM50 at the wafer level assure low cost and high accuracy.
Suitable for remote applications
The LM50's linear output, + 500 mV offset, and factory caliLow cost due to wafer-level trimming
bration simplify circuitry required in a single supply environOperates from 4.5V to 10V
ment where reading negative temperatures is required. Because the LM50's quiescent current is less than 130 p.A,
Less than 130 p.A current drain
self-heating is limited to a very low 0.2·C in still air.
Low self-heating, less than 0.2·C in still air
Nonlinearity less than 0.8·C over temp

Applications

• Computers
• Disk Drives

Connection Diagrams
SOT-23

+VSDI

GND

3
Vo

Order
Number

S01':'23
Device Marking

Supplied As

LM50BIM3

T5B

LM50CIM3

T5C

250 Units on Tape and Reel

Top View

LM50BIM3X

T5B

3000 Units on Tape and Reel

See NS Package Number M03B
(JEDEC Registration TO-236AB)

LM50CIM3X

T5C

3000 Units on Tape and Reel

TLlH/I2370-1

TO-92
Plastic Package

~

250 Units on Tape and Reel

Typical Applications
+Vs

S

(4.5V TO lOY)

LM50

BOTTOM VIEW

TL/H/12370-2

Order Number LM50BIZ
orLM50CIZ
See NS Package Number Z03A

-

OUTPUT

Your = (10 mY/oC x Temp °C) +500 mV
Your = +1.750V at +125 0 C
Your = +750 mV at +25 0 C
Your = + 100 mV at -40°C
TLlH/12370-3

FIGURE 1. Full-Range Centigrade Temperature Sensor (- 40"C to

5-28

+ 125"C)

ttlNational Semiconductor

LM 134/LM234/LM334
3-Terminal Adjustabls Current Sources
General Description
LM234-3 and LM134-6/LM234-6 are specified as true temperature sensors with guaranteed initial accuracy of ± 3'C
and ± 6'C, respectively. These devices are ideal in remote
sense applications because series resistance in long wire
runs does not affect accuracy. In addition, only 2 wires are
required.
The LM134 is guaranteed over a temperature range of
- 55'C to + 125'C, the LM234 from - 25'C to + 100'C and
the LM334 from O'C to + 70'C. These devices are available
in TO-46 hermetic, TO-92 and 50-8 plastic packages.

The LM134/LM234/LM334 are 3-terminal adjustable current sources featuring 10,000:1 range in operating current,
excellent current regulation and a wide dynamic voltage
range of 1V to 40V. Current is established with one external
resistor and no other parts are required. Initial current accuracy is ±3%. The LM134/LM234/LM334 are true floating
current sources with no separate power supply connections.
In addition, reverse applied voltages of up to 20V will draw
only a few dozen microamperes of current, allowing the devices to act as both a rectifier and current source in AC
applications.
The sense voltage used to establish operating current in the
LM134 is 64 mV at 25'C and is directly proportional to absolute temperature (,K). The simplest one external resistor
connection, the'n, generates a current with:::: +0.33%I'C
temperature dependence. Zero drift operation can be obtained by adding one extra resistor and a diode.

Features
!II Operates from 1V to 40V

.. 0.02%1V current regulation
II Programmable from 1 p,A to 10 mA
Ii:! True 2-terminal operation
I!I Available as fully specified temperature sensor
.. ± 3% initial accuracy

Applications for the current sources include bias networks,
surge protection, low power reference, ramp generation,
LED driver, and temperature sensing. The LM134-3/

Connection Diagrams
SO-S
Surface Mount Package

N{a

17 Is

!1 P

SO-S Alternative Pinout
Surface Mount Package

N{S

N{a

N{7

,Ll

!R2 ,P
,'NC.4
...

.,.

p~4

TO-46
Metal Can Package
y+

N,CS N{S

-Or

TL/H/5697-12

, Bottom View
v- Pin is electrically

TLlH/5697 -25

TLlH/5697 -24

Order Number LM334M
See NS Package
Number MOSA

connected to case.

Order Number LM334SM
See NS Package
Number MOSA

Order Number LM134H,
LM134H-3, LM134H-6,
LM234H or LM334H
See NS Package
Number H03H

Typical Application
BasiC 2-Terminal Current Source
+VIN

ISETIIv<

6.
~l

j

~~~~ VA

'eIABI
ISETI

.....
V-

-VIN

I

RSET

-""'-'
TLlH/5697 -1

5-29

TO-92
Plastic Package
y+ R

8

Y-

TLlH/5697 -10

Bottom View
Order Number LM334Z,
LM234Z-3 or LM234Z-6
See NS Package
NumberZ03A

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
V+ to V- Forward Voltage
LM134/LM234/LM334
40V
30V
LM134-3/LM134-6/LM234-3/LM234-6
V+ to V- Reverse Voltage
20V
R Pin to V- Voltage
SV
Set Current
10mA
Power Dissipation
400mW
ESD Susceptibility (Note S)
2000V

Operating Temperature Range (Note 4)
LM134/LM134-3/LM134-6
- SS·C to + 12S·C
LM234/LM234-3/LM234-6
- 2S·C to + 1000C
OOCto +70·C
LM334
Soldering Information
260·C
TO-92 Package (10 sec.)
300·C
TO-46 Package (10 sec.)
SO Package
21S·C
Vapor Phase (60 sec.)
220·C
Infrared (lS sec.)
See AN-4S0 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.

Electrical Characteristics (Note 1)
Parameter

LM134/LM234

Conditions
Min

Set Current Error, V+ = 2.SV,
(Note 2)

10/LAs;ISETS;1 mA
1 mA

~
a::

1.

1/

V

",
~

I

RSET= Uk- -

,,

lpA

.1.

RSET= 680n-

r
10pA

18

RSET,san=
I

I

loopA

20

RSErl4Sl

14

I

0.8

0.8

1.0

I'

12

1.2

10pA

1A

100pA

Y+TOY-YOLTAGE·

lmA

IOmA

ISET
TLlH/5697 -29

TLiH/5697 -9

The LM134 has been designed for ease of application, but a
general discussion of design features is presented here to
familiarize the designer with device characteristics which
may not be immediately obvious. These include the effects
of slewing, power dissipation, capacitance, noise, and contact resistance.

Since (for a given set current) IBIAS is simply a percentage
of ISET' the equation can be rewritten

Application Hints

ISET =

RSET

CALCULATING RSET

-:or

SLEW RATE

y+

<':J
V"

IBIAS~

At slew rates above a given threshold (see curve), the
LM134 may exhibit non-linear current shifts; The slewing
rate at which this occurs is directly proportional to ISET. At
ISET = 10 p.A, maximum dV/dt is O.OtV/p.s; at ISET =
1 mA, the limit is tV1p.s. Slew rates above the limit do not
harm the LM134, or cause large currents to flow.

R

+

t
-l

VR
'R ~

RSET

THERMAL EFFECTS
Internal heating can have a significant effect on current regulation for ISET greater than 100 p.A. For example, each 1V
increase across the LM134 at ISET = 1 mA will increase
junction temperature by ::::: O.4°C in still air. Output current
(ISET) has a temperature coefficient Of ::::: 0.33%/OC, so the
change in current due to temperature rise will be
(0.4) (0.33) = 0.132%. This is a 10:1 degradation.in regula- tion compared to true electrical effects. Thermal effects,
thereiore, must be taken into account when DC regulation is
critical and ISET exceeds 100 p.A. Heat sinking of the T0-46
package or the TO-92 leads can reduce this effect by more
than 3:1.
I'"

'SET ~ .
TLlH/5697 -27

FIGURE 1. Basic Current Source
A 'graph showing the ratio of these two currents is supplied
under Ratio of ISET to ISlAS in the Typical Performance
Characteristics section. The current flowing through RSET is
determined by VR, which is approximately 214 p.VI"K
(64 mVl298°K - 214 p.VI"K).
ISET = IR

n - 1

ISET = ( VR ) (1.059) = 227 p.VloK
RSET
RSET
. for most set currents.

+V'N

(~-

(_
n .)

where n is the ratio of ISET to IBIAS as specified in the Elec. trical Characteristics Section and shown in the graph. Since
n is typically 18 for 2 p.A :5: ISET :5: 1 mA, the equation 'can
'
be further simplified to

The total current through the LM134 (ISET) is the sum of the
current going through the SET resistor (lR) and the LM134's
bias current (I BIAS), as shown in Figure 1.

'SET ~

(~)

+ IBIAS =

VR

--

RSET

+ IBIAS

5-32

r-------------------------------------------------------------------------------------~

Application Hints (Continued)
SHUNT CAPACITANCE

used to terminate the LM134. Slope error after trim will normally be less than ± 1%. To maintain this accuracy, however, a low temperature coefficient resistor must be used for
RSET·
A 33 ppml"C drift of RSET will give a 1% slope error because the resistor will normally see about the same temperature variations as the LM134. Separating RSET from the
LM134 requires 3 wires and has lead resistance problems,
so is not normally recommended. Metal film resistors with
less than 20 ppml"C drift are readily available. Wire wound
resistors may also be used where best stability is required.

In certain applications, the 15 pF shunt capacitance of the
LM1,34 may have to be reduced, either because of loading
problems or because it limits the AC output impedance of
the current source. This can be easily accomplished by buffering the LM134 with an FET as shown in the applications.
This can reduce capacitance to less than 3 pF and improve
regulation by at least an order of magnitude. DC characteristics (with the exception of minimum input voltage), are not
affected.
NOISE
Current noise generated by the LM134 is approximately 4
times the shot noise of a transistor. If the LM134 is used as
an active load for a transistor amplifier, input referred noise
will be increased by about 12 dB. In many cases, this is
acceptable and a single stage amplifier can be built with a
voltage gain exceeding 2000.

r-

s:::
....
Cot)
~

.....
rs:::
N
Cot)
~

.....
rs:::
Cot)
Cot)
~

APPLICATION AS A ZERO TEMPERATURE
COEFFICENT CURRENT SOURCE
Adding a diode and a resistor to the standard LM 134 configuration can cancel the temperature-dependent characteristic of the LM134. The circuit shown in Figure 3 balances the
positive tempco of the LM134 (about +0.23 mVI"C) with
the negative tempco of a forward-biased silicon diode
(about - 2.5 mV I"C).

LEAD RESISTANCE
The sense voltage which determines operating current of
the LM134 is less than 100 mV. At this level, thermocouple
or lead resistance effects should be minimized by locating
the current setting resistor physically close to the device.
Sockets should be avoided if possible. It takes only 0.7fi
contact resistance to reduce output current by 1 % at the
1 mA level.

R

+

t

SENSING TEMPERATURE
The LM134 makes an ideal remote temperature sensor because its current mode operation does not lose accuracy
over long wire runs. Output current is directly proportional to
absolute temperature in degrees Kelvin, according to the
following formula:

VR

Rl

~

R2

+

t

I
(227 p.VI"K)(n
SET =
RSET

vo

~

Calibration of the LM134 is greatly simplified because of the
fact that most of the initial inaccuracy is due to a gain term
(slope error) and not an offset. This means that a calibration
consisting of a gain adjustment only will trim both slope and
zero at the same time. In addition, gain adjustment is a one
point trim because the output of the LM 134 extrapolates to
zero at OOK, independent of RSET or any initial inaccuracy.

TUH/5697-2B

FIGURE 3. Zero Tempco Current Source
The set current (ISET) is the sum of 11 and 12, each contributing approximately 50% of the set current, and IBIAS. IBIAS is
usually included in the 11 term by increasing the VR value
used for calculations by 5.9%. (See CALCULATING RSET.)
ISET =

h

+ 12 + IBIAS, where

I - VR
1 -

R;""

and

I _ VR + Vo
2 - ---R-2-

The first step is to minimize the tempco of the circuit, using
the following equations. An example is given using a value
of +227 p.VI"C as the tempco of the LM134 (which includes the IBIAS component), and - 2.5 mV I"C as the tempco of the diode (for best results, this value should be directly
measured or obtained from the manufacturer of the diode).

TUH/5697-4

FIGURE 2. Gain Adjustment

ISET = 11 + 12

This property of the LM134 is illustrated in the accompanying graph. Line abc is the sensor current before trimming.
Line a'b'c' is the desired output. A gain trim done at T2 will
move the output from b to b' and will simultaneously correct
the slope so that the output at T1 and T3 will be correct.
This gain trim can be done on RSET or on the load resistor

dlSET = dll + dl2
dT
dT
dT
:::: 227 p.VI"C + 227 p.V/oC - 2.5 mV/oC
Rl
= 0 (solve for tempco = 0)

5-33

R2

1:11

Application Hints (Continued)
The values of R, and R2 can be changed to standard 1%
resistor values (R, = 1330 and R2 = 1.33 kO) with less
than a 0.75% error.
If the forward voltage drop of the diode was 0.65V instead
of the estimate of 0.6V (an error of 8%), the actual set current will be

R2 _ 2.5 mVloC - 227IJ.VloC 0
227IJ.V/oC
- 10.
R, With the R, to R2 ratio determined, values for R, and R2
should be determined to give the desired set current. The
formula for calculating the set current at T = 25°C is shown
below, followed by an example' that assumes the forward
voltage drop across the diode (Vo) is 0.6V, the voltage
across R, is 67.7 mV (64 mV + 5.9% to account for IBIAS>,
and R2/R1 = 10 (from the previous calculations).

67.7 mV .::..67:..:,.7:...:.:.:m.:.V;,.:+....:0:,:.6:.:5:.;,V
ISET=---+
.
R1
R2
= 67.7 mV + 67.7·mV + 0.65V
133
1330
= 1.049 mA
an error of less than 5 %.
If the estimate for the tempco of the diode's fOrvl(ard voltage
drop was off, the tempco cancellation is still reasonably effective. Assume the tempco of the diode is 2.6 mV
instead of 2.5 mVloC (an error of 4%). The tempco of the
circuit is now:

ISET = I, + 12 + IBIAS
= VR + VR + Vo
R2
R,
::::: _67_.7_m_V + .:.67;,,;.,;,.7.:.;,m;,.:V_+,;,....:0;,.:.6:.;,V
R,
10.0R,
_ 0.134V

I

rc

SET-~

This circuit will eliminate most of the LM134's temperature
coefficient, and it does a good job even if the estimates of
the diode's characteristics are not accurate (as the following
example will show). For lowest tempco with a specific diode
at the desired ISET' however, the circuit should be built and
tested over temperature. If the measured tempco of ISET is
positive, R2 should be reduced. If the resulting tempco is
negative, R2 should be increased. The recommended diode
for use in this circuit is the 1N457 because its tempco is
centered at 11 times the tempco of the LM134, allowing R2
= 10 R,. You can also use this circuit to create a current
source with non-zero tempcos by setting the tempco component of the tempco equation to the desired value instead
of O.
EXAMPLE: A 1 mA, Zero-Tempco Current Source
First, solve for R1 and R2:
0.134V
ISET:::::1mA=-R1
R, = 1340 = 10R2
R2 = 13400

dlSET = dl, + dl2
dT
dT
dT
= 227 p'vrc + 227 p.V1°C - 2.6 mVloC
133n
1330n
= -77nAI"C
A 1 mA LM134 current source with no temperature compensation would have a set resistor of 68n and a resulting
tempco of
227 p'vrc _
°
68n
- 3.3 p.A/ C
So even if the diode's tempco varies as much as ±4% from
its estimated value, the circuit still eliminates 98% of the
LM134's inherent tempco.

Typical Applications
Terminating Remote Sensor for Voltage Output

Ground Referred Fahrenheit Thermometer
R4

+V'N

5&k

.--~~-,...-------+VIN

"

10

Noise Voltage
3&0
.lz"lmA
Tj'25°C

§

..

~

f:: TI'-6rc

u

..

~

.. ",
!l!
oS

..A

==Tj'IZrC

!iz
"

HN~UT

320

I

10

I

RT

·1.....

I

REVERSE VOLTAGE (VI

Dynamic Impedance

T~

·W

146 185

100

I-- ~UTP~ -I r'N'UT

....
..i

105

TEMPERATURE (OCI

REVERSE CURRENT (mAl

I

&5

"
2

11

280

lOa
,.

100

II1l<

10Da

10

Thermal Resistance
Junction to Air
45
40

g 100

t- .301

35

w

;'
ffi 100
i!:

30

8
!il;:::

15

I-

\

g

~, T004'

I:S..;
TD-IZ

25
20

400

0:' 40
~
z 20

lZ00

1800

1000

I

..
I-

TD045

~
~

" ..2:l"'"+TD
8IlI

&0

z

1\
1\

400

AIR VELOCITY (FPMI

lOOk

'"

80

~

I I
D·

.~
>

10

10k

Thermal Response
InStill Air
.

'Thermal Time Constant

I.

lk

FREQUENCY (Hz)

400

ZOO

100

FREQUENCY (Hz)

TIME ""I

!~

"

24lI

TjoISOC-

I

0.1
2

~

TT2y-

i~

0.1
-S5 -15

10

.,.tTj'2S0C-

TI"-SSoC

~

A"J..1""

o~"""

E

~

.. I-"

~"~5oL

:::::~

o

Reverse Characteristics
10

IT/.1_ 6S!C
I

V

Calibrated Error

I

800

1200

1500

4

2000

6

TIME (MINUTESI

AIR VELOCITY (FPMI

Thermal Response In
Stirred 011 Bath

Forward Characteristics
1.4

glaD

3
~

..
~
0:

"

I-

'"~

ID

40

20

1.2

'"

10

....
..""
•..

E
w
!:;
>

:1
'/

-

1.0
0.8

""'

~T' 5°C
f"-

0.6

c

DA

~

~

~

{1.1~~oc

0.2

o

I

j

......

-"

.....

Tj-12S0C

I 11111

0.1
TIME (SECONDSI

10
FORWARD CURRENT (.. AI
. TLfHf5696-3

5·40

Application Hints
CALIBRATING THE LM135

To insure good sensing accuracy several precautions must
be taken. Like any temperature sensing device, self heating
can reduce accuracy. The LM135 should be operated at the
lowest current suitable for the application. Sufficient current,
of course, must be available to drive both the sensor and
the calibration pot at the maximum operating temperature
as well as any external loads.

Included on the LM135 chip is an easy method of calibrating
the device for higher accuracies. A pot connected across
the LM135 with the arm tied to the adjustment terminal allows a 1-point calibration of the sensor that corrects for
inaccuracy over the full temperature range.
This single point calibration works because the output of the
LM135 is proportional to absolute temperature with the extrapolated output of sensor going to OV output at O'K
(- 273. 15'C). Errors in output voltage versus temperature
are only slope (or scale factor) errors so a slope calibration
at one temperature corrects at all temperatures.

If the sensor is used in an ambient where the thermal resistance is constant, self heating errors can be calibrated out.
This is possible if the device is 'run-with a temperature stable
current. Heating will then be proportional to zener voltage
and therefore temperature. This makes the self heating error proportionalto'absolute temperature the same as scale
factor errors.
'

The output of the device (calibrated or uncalibrated) can be
expressed as:

WATERPROOFING SENSORS
Meltable inner core heat shrinkable tubing such as manufactured by Raychem can be used to make low-cost waterproof sensors. The LM335 is inserted into the tubing about
112" from the end and the tubing heated above the melting
pOint of the core. The unfilled 112" end melts and provides a
seal over the device.

VaUTT = VaUTT x.:!:.

o To
where T is the unknown temperature and To is a reference
temperature, both expressed in degrees Kelvin. By calibrating the output to read correctly at one temperature the output at all temperatures is correct. Nominally the output is
calibrated at 10 mVI'K.

Typical Applications
Basic Temperature Sensor

Calibrated Sensor

Wide Operating Supply

v·

v+

5V-40V

Rl

Rl
OUTPUT
10mVfK

....- - 4.....LM335 . -....~ 10k

OUTPUT 10 mVfK,

*

~---------------

-

TUH/5698-9

'Calibrale for 2.9S2V at 2S'C
TL/H/S698-10

Minimum Temperature Sensing

Average Temperature Sensing
15V

ISV

6k

6k

r-----~~----1.....~i~!~rK

TAVG 130 mV/'Kl

Remote Temperature Sensing

.£Tj. ~~
LM33S~

LM33S'

~

TL/H/5698-4

TLlH/5698-19

Wire length for I'C error due to wire drop
IR = 1 mA
IR = 0.5 mAo
TL/H/5698-18

AWG
14
16
18
20
22
24
'For IR

5-41

FEET
4000
2500
1600
1000
625
400

FEET
8000
5000
3200
2000
1250
800

= 0.5 rnA, the trim pot must be deleted.

Typical Applications

(Continued)

Isolated Temperature Sensor
0035

15V

15V
II'

L:: :J
---

•

BOURNS

4251-l1li7

~____+-_1.8ft~7~1-0~"~
ZIo

511

lNI14

11111 .

lUi
lNI14
-15V

-I5V

TLlH/569B-20 .

Simple Temperature Controller

...

laV-3IV-1~---------------I-~""------

LMUle

TLlH/569B-5

Simple Temperature Control
LM335

5V-4IIV
L - _....~11111
SET
TEMPERATURE
3k

"
-IOV

TL/H/569B-21

5-42

r-----------------------------------------------------------------------------'r
Typical Applications

3:

(Continued)

-0.
Co)
(II

Ground Referred Fahrenheit Thermometer

.....
r

3:

Centigrade Thermometer

'5V

"

N

Co)
(II

.....
r

15V

15V

"

12k

,.,"
.

LM335

..._ ........I".VI·'

Ok

.,"
'Ok

OUTPUT

...--6~.~~~~-.-~~~~:
'"

'"

3:
w
Co)
JI'I
r
3:
-0.
Co)

~

"

r
'"
3:

-1.V

N

TLlH/5698-22

Co)

• Adjust A2 for 2.554V across LM336.

TL/H/5698-23

Adiust Al for correct outpul

'Adjuslfor 2. 7315V at output of LM308

~
.....
r

3:

Co)
Co)

Fahrenheit Thermometer

~

15V

'Ok

'"
"

4.55"

.

OUTPUT
} tmvfF

+---~~~~~~~~
LII335

.,

'a'

L1I33&

.,

'a'

.

TL/H/569B-24

'To calibrate adjust A2 for 2.554V across LM336.
Adjust Al for correct outpul

THERMOCOUPLE COLD JUNCTION COMPENSATION
Compensation for Grounded Thermocouple
'Select R3 for proper thermocouple type
15V

THERMOCOUPLE
J
T
K
S

4.n
ZOO,

'"

R3
(±1%)
3770
308.0.
293.0.
45.8.0.

SEEBECK
COEFFICIENT
52.31£vrc
42.81£VrC
40.81£Vrc
6.41£V/oC

Adjustments: Compensates for both sensor and resistor tolerances

1. Short LM3298
2. Adjust R1 for Seebeck Coefficient times ambient tempera~re (in degrees
K) across A3. .

H,

. -....<'011

3. Short LM335 and adjust A2 for voltage across A3 corresponding to thermocouple type

J

'2.

THERMOCOUPLE

T

-15V
TL/H/6698-6

5-43

14.32 mV
11.79 mV

K
S

11.17 mV
1.768 mV

III

Typical Applications

(Continued)
Single Power Supply Cold Junction Compensation

16V
10k
·Select R3 and R4 for thermocouple type

200k

THERMOTHERMOCOUPLE

Rl
10k

LM335

~3

COUPLE

+,

"::"

"::"

15V

R3

R4

SEEBECK
COEFFICIENT

J

1.05K

3850.

,52.3 P.V I'C

T

8560.

3150.

42.8 p.VI'C

K

8160.

3000.

40.8 p.VI·C

S

1280.

46.30.

6.4 p.V/·C

Adlustments:
1. Adjust Rl for !he .voltage across R3 equal 10 the Seebeck Coefficient
times ambient temperature in degrees Kelvin.
2. Adjust R2 for vonage across R4 corresponding to thermocouple

+,

20Gk
1M

R3

LM329a

OUTPUT

Ilk
"::"

J

14.32mV

T

11.79mV

K

11.17 mV

S

1.768mV

R4

"::"

TL/H/5698-11
Centigrade Calibrated Thermocouple Thermometer

10k 1:: ~I-~r LM335

al.k

I"

Termlnale thermocouple reference junction In
close proximity 10 LM335.

LM329B

Adjustments:
-15V

422

lOOk

1%

1%

I. Apply signal In place of thermocouple and ad·
just R3 for a gain of 245.7.
2. Short non.inverting input of LM308A and out·
put of LM3298 to ground.

R3
ik

3. Adjust RI so that VOUT

= 2.982V @ 25'C.

4. Remove short across LM3298 and adjust R2
. so that VOUT = 246 mV @ 25'C.
5. Remove short across thermocouple.

TL/H/5698-12
Fast Charger for Nickel-Cadmium Batteries

Differential Temperature
.
Sensor

..-----,

1:-------t~--------~----~~------~------------

r------1~liV

12k

12k
ll1e

10k

20G
10k

·._"'C~~L

\
_--"P~2Bk

OJ
LM:t35

01 t

LM335~-""'-""
10k
TLlH/5698-7

TNIIlllALLYCOU.LI'- -

-

-

-

tAdjust 01 10 50 mV greater Vz thin 02.
Charge tsrmlnates on
temperature ~se. Couple 0210 ballelY.

sec

5-44

-

-

.....c.IV-IZV

I

"::"

TL/H/5896-13

Typical Applications (Continued)
Differential Temperature Sensor
15V
ZOOk

IZk

12k
20k
OUTPUT

IODmvrc

ZOk

180k
LM335

&Ok
ZERO

TL/H/5698-14

Variable Offset Thermoineter*
Ik

15V

15V

0---'.& ....
CLOSE
FOR

Ivrc

Y"'''''J..
-

IOk2k

OUTPUT
_ll1O mV/'C

LM335

-15V

IOkt
ZERO

1.18k

lM329a

t Adjust lor zero with sensor at O"C and lOT pol set at O'C
'Adjust lor zero output with lOT pot set at 100"C and sensor
at lOO'C
*Output nssds difference batwean temperatura and dial setting
ol10Tpot

Zk
-15V
TUH/58I18-15

5-45

Typical Applications

(Continued)

Ground Referred Centigrade Thermometer

Air Flow Detector'
r--~""15V

20k

Uk

18k
15V

OUTPUT
IOmvrc

OUTPUT-HIGH
WITH AIR FLOW

Zk

TLlH/5698-17

'SsH heating is

u~ed

to delect air flow

-15V
TL/H/5696-16

Definition of Terms
Operating Output Voltage: The voltage appearing across
the positive and negative terminals of the device at specified conditions of operating temperature and current.
Uncallbrated Temperature Error: The error between the
operating output voltage at 10 mV;oK and case temperature
at specified conditions of current and case temperature.

Calibrated Temperature Error: The error between operating output voltage and case temperature at 10 mV;oK over
a temperature range at a specified operating current with
the 25'C error adjusted to zero.

5-46

Section 6

Sample and Hold

-.~--

----- -

-- ----

-

--

---~

Section 6 Contents
Sample and Hold Definition ofTerms................ .............. ..... ........... ....
Sample and Hold Selection Guide ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LF198/LF298/LF398/LF198A1LF398A Monolithic Sample and Hold Circuits ..............
LF13006/LF13007 Digital Gain Set...................................................

6·2

6-3
6-4
6-5
6-15

t!lNational Semiconductor

Sample and Hold
iDeiiniiion of Terms
Acquisition Time: The time required to acquire a new analog input voltage once a sample command has been given.
A signal is "acquired" when it has settled within a specified
. error band around its final value of output voltage. The maximum value of the acquisition time occurs when the hold
capacitor must change to a full-scale voltage change. Note
that acquisition time is not just the time required for the
output to settle, but also includes the lime required for all
internal nodes to settle so that the output assumes the
proper value when switched to the hold mode.

Feedthrough Attenuation Ratio: The fraction of the input
Signal that appears at the output while the S/H is in hold
mode.
Gain Error: The ratio of output voltage swing to input voltage swing in the sample mode expressed as a percent difference.
Hold Capacitor Leakage Current: The current which flows
into or out of the hold capacitor while the S/H is in hold
mode.
Hold Settling Time: The time required for the output to
settle within a specified error band after the "hold" logiC
command has been given.
Hold Step: The voltage step at the output of the sample
and hold when switching from sample mode to hold mode
with a steady (DC) analog input voltage.

Aperture Jetter: The uncertainty in the aperture time. Aperture jitter results from noise which is superimposed on the
hold command which affects its timing.
Aperture Time (Aperture Delay): The delay required between "Hold" command and an input analog transition, so
that the transition does not affect the held output.

Sample-to-Hold Transient: The transient that appears at
the output due to a sample-to-hold transition.

Droop Rate: The rate at which the output voltage is changing in hold mode as a result of leakage from the hold capacitor.
Dynamic Sampling Error: The error introduced into the
held output due to a changing analog input at the time the
hold command is given. Error is expressed in mV with a
given hold capacitor value and input slew rate. Note that
this error term occurs even for long sample times.

6-3

CD
"C

·s
CJ

c

o

t!lNational Semiconductor

:g
CD

~

Sample and Hold Selection Guide

"C

"0
:::E:

"C
C

'"
"S.

LF198A

LF398A

LF198

LF398

LF298

Units

0,01

0,01

0.02

0.02

0.02

"loMax

Offset Voltage

2

3

5

10

5

mVMax

Droop Rate (25°C)
Cs = 1000pF
'Cs =10000 pF

30
3

30
3

30
3

30
3

30
3

mVlsec

Acquisition Time (25°C)
Cs =1000pF
Cs = 10000pF

4

4

4

4

4

p.s

20

20

20

20

20

CD

E

cZ

Accuracy
Gain/Offset Error

Aperture Time (25°C)

250

250

250

250

250

'ns

Temperature Range

-55 to +125

Oto +70

-55 to + 125

Oto +70

-25to +85

°C

Low Drift

General
Purpose

General
Purpose

Low Drift

Comment

Low Drift

6-4

r-------------------------------------------------------------------------, ."
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.....
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CD
CO

t!lNational Semiconductor

~

CD
CO

LF198/LF298/LF398,LF198A/LF398A

.....
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2J
CD
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Monolithic Sample-anti-Hold Circuits
General Description

Features

The LF198/LF298/LF398 are monolithic sample-and-hold
circuits which utilize BI-FET technology to obtain ultra-high
dc accuracy with fast acquisition of signal and low droop
rate. Operating as a unity gain follower, dc gain accuracy is
0.002% typical and acquisition time is as low as 6 /-'S to
0.01 %. A bipolar input stage is used to achieve low offset
voltage and wide bandwidth. Input offset adjust is accomplished with a single pin, and does not degrade input offset
drift. The wide bandwidth allows the LF198 to be included
inside the feedback loop of 1 MHz op amps without having
stability problems. Input impedance of 10100 allows high
source impedances to be used without degrading accuracy.

• Operates from ± SV to ± 18V supplies
• Less than 10 /-,S acquisition time
• TTL, PMOS, CMOS compatible logic input
• O.S mV typical hold step at Ch = 0.01 /-,F
• Low input offset
• 0.002% gain accuracy
• Low output noise in hold mode
• Input characteristics do not change during hold mode
• High supply rejection ratio in sample or hold
• Wide bandwidth
• Space qualified
Logic inputs on the LF198 are fully differential with low input
current, allowing direct connection to TTL, PMOS, and
CMOS. Differential threshold is 1.4V. The LF198 will operate from ± SV to ± 18V supplies.

P-channeljunction FET's are combined with bipolar devices in
the output amplifier to give droop rates as low as S mV Imin
with a 1 /-,F hold capacitor. The JFET's have much lower
noise than MOS devices used in previous designs and do
not exhibit high temperature instabilities. The overall design
guarantees no feed-through from input to output in the hold
mode, even for input signals equal to the supply voltages.

An "An version is available with tightened electrical specifications.

Typical Connection and Performance Curve
Acquisition Time

10

...
~

OUTPUT

ANALOG INPUT

- --.:I' -

j~~I;iill

1000~.

,V _ _ SAWPlE

-"OGle
---'
OV HOLD

100

INPUT

0.001

0.01

0.1

HOLD CAPACITOR 1J,if)

TL/H/5692-2

Connection Diagrams
Dual-In-Llne Package

Small-Outline Package

Metal Can Package
LOGIC

V·

LOGIC

INPUT

OFFSET ADJUST

NC
OFFSET
ADJUST

2

1

INPUT

lOGIC
REFERENCE

'h

..

OUTPUT

NC

v-

v'

NC

LOGIC

NC

LOGIC REFERENCE

NC

Ne

OUTPUT

~

OFFSET
ADJUST

TLlH/5692-15

TQPVIEW

TLlH/5692-11

Order Number LF398N or LF398AN
See NS Package Number N08E

Order Number LF298M or LF398M
See NS Package Number M14A

vTOP VIEW

TL/H/5692-14

Order Number LF198H,
LF198H/883,LF298H,
LF398H, LF198AH or LF398AH
See NS Package Number H08C

6-S

."

.....
CD

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r
2J
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CO

»

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
±18V
Supply Voltage
500mW
Power Dissipation (Package Limitation) (Note 1)

Lead Temperature (Note 3)
H package (Soldering, 10 sec.)
N package (Soldering, 10 sec.)
M package:
Vapor Phase (60 sec.)
. Infrared (15 s~c.)

Operating Ambient Temperature Range
LF198/LF198A
-55'Cto +125'C
LF298

260"C
260'C
215'C
220'C

Thermal Resistance (8JAl (typicals)
H package
215'C/W (Board mount in still ~ir)
85'C/W (Board mount in
400LF/min air flow)
115'C/W
N package
106'C/W
M package

-25'Cto +85'C

LF398/LF398A
O'Cto +70'C
Storage Temperat!Jre Range
- 65'C to + 150'C
Input Voltage
Equal to Supply Voltage
Logic To Logic Reference Differential Voltage +7V, -30V

8JC (H package, typical) 20'C/W

(Note 2)
Output Short Circuit Duration
Hold Capacitor Short Circuit Duration

Indefinite
10 sec

Electrical Characteristics

The following specifcations apply for -Vs + 3.5V s: VIN s: +Vs - 3.5V, +Vs = +15V, -Vs = -15V, TA = TJ = 25'C,
Ch = 0.01 p.F, RL = 10 kO, LOGIC REFERENCE = OV, LOGIC HIGH = 2.5V, LOGIC LOW = OV unless otherwise spepified.
Parameter

LF198/LF298

Conditions
Min

LF398

Typ

Max

. Tj = 25'C
Full Temperature Range

1

Input Bias Current, (Note 4)

Tj = 25'C
Full Temperature Range

5

Input Impedance

TJ

Gain Error

Tj = 25'C, RL = 10k
Full Temperature Range

Feedthrough Attenuation Ratio
at 1 kHz

Tj

Output Impedance

Tj = 25'C, "HOLD" mode
Full Temperature Range

Input Offset Voltage, (Note 4)

=

=

=

25'C, Ch

=

=

Tj

Tj~25'C

Logic and Logic Reference Input
Current

Tj

Leakage Current into Hold
Capacitor (Note 4)

Tj = 25'C, (Note 6)
Hold Mode

Acquisition Time to 0.1 %

AVOUT

Hold Capacitor Charging Current

VIN-VOUT

0.01 p.F, VOUT = 0

25'C

Supply Voitage Rejection Ratio

VOUT

Differential Logic Threshold

Tj

Input Offset Voltage, (Note 4)
Input Bias Current, (Note 4)

86

0.01 p.F

"HOLD" Step, (Note 5)

25'C, Ch

0.002

=

=

10V,Ch ='1000pF
Ch = 0.01 p.F

=

2V

Max

3
5

2

7
10

'mV
mV

25
75

10

50
100

nA
·nA

0.01
0.02

%
%

1010
0.005
0.02

96

0.004
80

0.5

2
4

0.5
4.5

dB

0
0

0.5

4
6

2.0

1.0

2.5

mV

5.5

4.5

6.5

mA

2

10

2

10 .

p.A

30

100

30

200

pA

4
20

4
20

5

5

mA

80

110

' dB

0.8

1.4

2.4

V

2

3

mV
mV

25
50

nA
nA

0

80

110

0.8

1.4

2.4

Tj = 25'C
Full Temperature Range

1

1
2

2

Tj = 25'C
Full Temperature Range

5

25
75

10

6-6

0

90

25'C

=

Units

Typ

1010

25'C

Supply Current, (Note 4)

=

Min

p.s
p.s

Electrical Characteristics

The following specifcations apply for -Vs + 3.5V s: VIN s: +Vs - 3.5V. +Vs = + 15V. -Vs = -15V. TA = Tj = 25D C.
Ch = 0.01 ,...F. RL = 10 kn. LOGIC REFERENCE = OV. LOGIC HIGH = 2.5V. LOGIC LOW = OV unless otherwise specified.
(Continued)
LF198A

Conditions

Parameter

Min

Typ

Input Impedahce

Tj = 25DC

1010

Gain Error

Tj = 25D C. RL = 10k
Full Temperature Range

0.002

Tj = 25D C. Ch = 0.01 ,...F

Output Impedance

Tj = 25DC. "HOLD" mode
Full Temperature Range

0.5

Tj = 25D C. Ch = O.Q1,...F. VOUT = 0

0.5

"HOLD" Step. (Note 5)

Min

Units

Typ

Max

n

1010
0.005
0.01

96

Feedthrough Attenuation Ratio
at 1 kHz

86

LF398A
Max

0.004
86

%
dB

90

n
n

0.5

4

Supply Current. (Note 4)

%

0.005
0.01

6
1.0

mV

4.5

5.5

4.5

6.5

mA

Logic and Logic Reference Input
Current

Tj = 25 C

2

10

2

10

,...A

Leakage Current into Hold
Capacitor (Note 4)

Tj = 25D C. (Note 6)
Hold Mode

30

100

30

100

pA

Acquisition Time to 0.1 %

AVOUT = 10V. Ch = 1000 pF
Ch = 0.01,...F

4
20

6
25

4
20

6

,...s

25

D

Hold Capacitor Charging Current

VIN-VOUT = 2V

Supply Voltage Rejection Ratio

VOUT = 0

90

110

5

Differential Logic Threshold

Tj = 25 C

0.8

1.4

D

2.4

,...s

5

mA

90

110

dB

0.8

1.4

v

2.4

Note 1: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX. 8JA. and the ambient temperature. TA. The maximum
allowable power dissipation at any temperature is Po = (TJMAX - T/J18JA. or the number given in the Absolute Maximum Ratings. whichever is lower. The
maximum iunction temperature. TJMAX. for the LF198/LF198A is 150'C; for the LF298. 115·C; and for the LF398/LF398A. l00'C.
NOle 2: Although the differential voltage may nol exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without
causing damage tQ the circuit For proper logic operation, however, one of the logic pins must always be at least ZV below the positive supply_ and 3V _above_the________ negaliye_suppJYL__
_------------- - - - --- -- - ----- ---------- -- --- ---Nole 3: Se8 AN-450 "Surface Mounting Methods and their effectS on Product Reliability" for other methods of soldering surface mount devices.
Note 4: These parameters guaranteed over a supply voltege range of ±5 to ±18V, and an input range of -Vs + 3.5V ,. VIN ,. +Vs - 3.5V.

s:

Note Hold step is sensitive to stray capacitive coupling between input logiC Signals and the hold capacitor. 1 pF. for instance. will create an additional 0.5 mV
step with a 5V logic swing and a 0.01 "F hold capacitor. Magnitude of the hold step is inversely proportionaito hold capacitor vaiue.
Note 6: Leakage current is measured at ajunction temperature of 25·C. The effecta of junction temperature rise due to power dissipation or elevated ambient can
be calculated by doubling the 25·C value for each II·C increase in chip temperature. Leakage is guaranteed over full input signal range.
Note 7: A military RETS electricaitest specification is available on request The LF198 may also be procured to Stendard Military Drawing
MIL-STD-38510 part ID JM38510/12501SGA.

;J 5962-8760801 GA

or to

Typical Performance Characteristics
Dielectric Absorption
Error In Hold CapaCitor

Aperture Timeo
500

I

I

450 v+ .. y- = 15V
40a 4VOUT S;1 mV
4vIN -IDV
350
I I
DINEGATIVE
311
25DI- INPUT STEP
/
20D
'f"'" , . POSITIVE
15D
INPUT STEP
10D~

::!

.........

"

D

"

100

~~~~~11I1oo

100

-

lD

.."i5 ..
,. ..
=
...
z
z

!

lD

:>
oS
•1

ili

-10

I I I

I I I

-5D -25 D 25 5D 15 100 125 150
JUNCTIDN, TEMPERATURE I·CI

D.l
D.l

1

10

SAMPLE TIME (ms1

'See Definition of Terms

D.l
100

10 '

100

IODD

INPUT SLEW RATE 1V/"t!
TLlH/5692-3

6-7

Typical Performance Characteristics (Continued)
"Hold" SeHlIng Tlme~ .

Ou,put.Droop Rate,
100

~~_"V-"15V

1.8

SETTLING TO I mV

1.1
1A
1.2

10

]

iii

I-

-

D.I
D.I

0.1

0.4

'"

."

....

0.2
10-4
100 pF' 1000 pF

D.OM

O.M

0.01
100 pF

I.F

1000 pF

O.oM

o

D.1.F

-50 -25 0

25

so 75 100 125 ISO

JUNCTION TEMPERATURE ec)

HOLD CAPACITOR

HOLD CAPACITOR

·See definition

Leakage Current into Hold
Capacitor
5

100

VS=·15V
VOUT=O
HOLD MODE

10

80

;

70

I-

~
""

!

t-

/

ill

i

Phase and Gain (Input to
Output, Small Signal)

-5

60

-10

50

I-

40

~
z
C
...

30

I

10-1

10-.2
-50 -25

20
10

a

a

25

Ik

75 100 125 150

50

10k.

JUNCTION TEMPERATURE rCI

140
ii 120

..'"
~
.!$
!i"

100

sa
80

I

~UPPlY

o
lk

10k

10l1li

10

r--..
-50 -25

I

1&

-110

10

i -1DO
-80
!i" -10

I-

~

~

I"'--t-.,

-5
-10
-15
-50 -25

.......

""

I f"o..

SINKING

ri'-)o...

.....

a

25

so

-0.8

!i

-1

-15 -10

75 100 121 150

-5

a.

10

15

Output Noise

a

25

50

1111111 I
111111111

~

100

!..

sa

•... OLO·'
MODE

10

40

SAMPLE

mli~1

20

a

76 100 121 150

10

1110

Hfll-+-±'-II+I-I!YH+ V7.1" 0

TI'25'C

j

lA

E

1.•

1.2
I

,

m 0.6

-70
-50'

I

0.4

a:

0.2

!1
lk

10k lOOk

1M

a

.

---; ~ ~"illO"C
_Tj'25"~

~ . 0.'

1110

r--.....
........ ::-...

r-I-

-

.

T·' -51"C'"

~I"
I

-15 -10

f-- f--

I
I

...... ...

-5

10

1&

INPUT val TAGE (VI

"

6-8

lOOk

Hold Step vs Input Voltage
1.'

9

FREQUENCY (H~

I.

2

:g

e

..

10

Ik

FREQUENCY (Hz)

-so

'JUNCTION TEMPERATURE ('C)

- -- .......

-0.•

~

Feedthrough ReJection RatiO
(Hold Mode)
-130 mlrTmrTT1"':"""'v"7+~,V---'-II-V'"
-120 Htll-tftff-ttttHHt VIN '10 Vp·p

25

......

~
~

JUNCTION TEMPERATURE rCI

Input Bias Current

i

.....

~ -OA

I I
I I

o

1M

FREQUENCY (Hz)

.20

...

0.4

~ D~
".! -8.2

120

~I

2
100

!;

~

140

SOURCING

11

I'l:

20

."

:::;

Tj"25'C
RL'10k
SAMPLE MODE

INPUT VOLTAGE (V)

I I
I I

14

8
~

POSITIVE

40

~
on

D.•

~ 0.6

180

I\.

18

NEGATIVE
SUPPLY

!:i
,.:ll

~

Output Short Circuit Current
20
18

~~=.2~~C'15V

g

10M

1M

...
":;l"c

1

FREQUENCY (Hzl

Power Supply ReJection
160

lOOk

iii

!:i

Gain Error

~

TLlH15692-4

r-----------------------------------------------------------------------------, -n
r

....

Typical Performance Characteristics (Continued)

CCI

Output Transient at Start
of Sample Mode

• I1\
• I

o.
o.
o.2
~

0

~

-0. 2

•

~ -0.

0..

o.

-0. 2

N

40

il
ll7

CH=O.OOI,uF

!

20

~
'"'"

-20

ser

~

-1-\7.LP~
•

RAf <

~kHz,

('r-I

V

-60

C.=o.ol~f

a

0.5 1.0 1.5 2.0 2.5 3.0 3.5 .4.0

M U

~

~

12 1.. 1.

1~

TINE CJ.&s)

TLlH/5692-12

11IIE (}u)

-n
....
CCI
;.......

.f

-40

t~SA"PLE RATE > 3kHz

o

~
.......
r
-n
~

60

1\

2
0--

....

co
r
-n

Output Transient at Start
of Hold Mode

TL/H/5692-13

Logic Input Configurations
TTLBoCMOS
3V

s: VLOGIC (Hi State) s: 7V

RI"

n
.J
Threshold

HOLO

2.BV

.

R2

LSAMPLE

= 1.4V

5.6k

Threshold = 1.4V
'Select for 2.BV at pin B

___ v+ ____ ~_ ---------------

CMOS

--v'- 7V-:S:-VLoGIC (HfState~15V-

20k

30k'

.n

30k

HOLO

.J
Threshold

= 0.6 (V+) + 1.4V

20k

LSAMPLE

Threshold = 0.6 (V +) - 1.4V

OpAmpDrive

+13V HSAMPLE

- -13

-

.

HOLD

B2k

+13VRo

LD

.-

B.2k

--J\N\,...........
4.1k

-13V

SAMPLE

4.7k

Threshold '" + 4V
Threshold = -4V

6-9

TLlH/5692-6

r
~

CCI

;

~ r-------------------------------------------------------------------~

~

i~
.....

~

~

.....

-m
~

Application Hints
Hold Capacitor

tor on the chip. This means that at the 'moment the "hold"
command arrives, the hold capacitor voltage may be somewhat different than the actual analog input. The effect of
these delays is opposite to the effect created by delays in
the logic which switches the circuit from sample to hold. For
example, consider an analog input of' 20 Vp-p at 10kHz.
Maximum dV/dt is 0.6 VljJ.s. With no analog phase delay
and 100 ns logic' delay, one could expect up to (0.1 jJ.s)
(0.6V I jJ.s) = 60 mV error if the "hold" signal arrived near
maximum dVldt of the input. A positive-going input would
give a +60 mV error. Now assume a ,1 MHz (3 dB) bendwidth for the overall analog loop. This generates a phase
delay of 160 ns. If the hold capacitor sees this exact delay,
then error due to analog delay will be (0.16 jJ.s) (0.6 V/jJ.s)
= -96 mV. Total output error is +60 mV (digital) -96 mV
(analog) for a total of -36 mV. To add to the confusion,
analog delay is proportioned to hold capaCitor value while
digital delay remains constant. A family of curves (dynamic
sampling error) Is Included to help estlr'nate errors.
'PI curve labeled Aperture Time has been included for sampling conditions where the input is steady during the sampling period, but may experience a sudden change nearly
coincident with the "hold" command. This curve is based on
a 1 mV error fed into the output.
A second curve, Hold Senling Time indicates the time required for the output to settle to 1 mV after the "hold" command.

Hold step, acquisition time, and droop rate are the major
trade-offs in the selection of a hold capacitor value. Size
and cost may also become important for larger values. Use
of the curves included with this data stieet should be helpful
in selecting a reasonable, value of capacitance. Keep in
mind that for fast repetition rates or tracking fast signals, the
capacitor drive currents may cause a significant temperature rise in the LF198.
A significant source of error in an accurate sample and hold
circuit is dielectriC absorption in the hold capacitor. A mylar
cap, for instance, may "sag back" up to 0.2% after a quick
change in voltage. A long sample time is required before the
circuit can be put back into tlie hold mode with this type of
capacitor. Dielectrics with very low hysteresis are polystyrene, polypropylene, and Teflon. Other types such as mica
and polycarbonate are not nearly as good. The advantage
of polypropylene over polystyrene is that it extends the maximum ambient temperature from 85'C to 100"C. Most ceremic capacitors are unusable with > 1 % hysteresis. c&.
ramic "NPO" or "COG" capacitors are now available for
125'C operation and also 'have low dielectric absorption.
For more exact data, see the curve Dielectric Absorption
Error. The hysteresis numbers on the curve are final values,
taken after full relaxation. The hysteresis error can be significantly reduced if the output of the LF198 is digitized quickly
after the hold mode is initiated. The hysteresis relaxation
time constant in polypropylene,'for instance, is 10-50 ms.
If A-to-D conversion can be made within 1 ms, hysteresis
error will be reduced by a factor of ten.

'

Digital Feedthrough
Fast rise time logic signals can cause hold errors by feeding
externally into the analog input at the same time the amplifier is put Into the hold mode. To minimize this problem,
board layout should keep logic lines as far as possible from
the analog input and the Ch pin. Grounded guarding traces
may also be used around the input line, especially if it is
driven from a high impedance source. Reducing high amplitude logic signals to 2.5V will also help.

DC and AC Zeroing
DC zeroing is accomplished by connecting the offset adjust
pin to the wiper of a 1kfl' potentiometer which has one end
tied to V + and the other end tied through a resistor to
ground. The resistor should be selected to give ~ 0.6 mA
through the 1k potentiometer.
AC zeroing (hold step zeroing) can be obtained by adding
an inverter with, the adjustment pot tied input to output. A
10 pF capacitor from the wiper to the hold capacitor will give
±4 mV hold step adjustment with a 0.01 jJ.F hold capaCitor
and 5V logic supply. For larger logic swings, a smaller capaCitor « 10 pF) may be used.

Guarding Technique

Logic Rise Time
For proper operation, logic Signals intathe LF198 must have
a minimum dV/dt of 1.0 VljA-S. Slower signals will cause
excessive hold step. If a RIC network is used in front of the
logic input for signal delay, calculate the slope of the waveform at the threshold point to ensure that it is at least
1.0 VljJ.s.
Sampling Dynamic Signals
Sample error to moving input signals probably causes more
confusion among sample-and-hold users than any other parameter. The primary reason for, this is that many users
make the assumption that the sample and hold amplifier is
truly locked on to the Input signal while in the sample mode.
In actuality, there are finite phase delays through the circuit
creating an Input-output differential for fast moving signals.
In addition, although the output may have settled, the hold
capacitor has an additional lag due to the 3000. series resis-

lonllllVIEW

Tl/H/5692-5

Use 10·pln layout_ Guard around Ch Is tied to output_

6-10

r-----------------------------------------------------------------------------~r

....

."

Functional Diagram

CD

CI)

......
r

."
N
CD

OFFSET

r-I
I
I
I
I
INPUT

3

2

--------,-----...,
.
I
.

I

~
r

."
....
CD

I
I

1

+

11

~

OUTPUT

I

1
LODIC

r

."

I

1
LODICD
REFERENCE

CI)
......

/1

I
I
I
I

300

_./

.

L _________ _
I

CI)

!!:
r

."
Co)

CD

;

-----'

HOLD
CAPACITOR

TlIHI5692-1

Typical Applications (Continued)
X1000 Sample & Hold

Sample and Difference Circuit
(Output Follows Input in Hold Mode)

VOUT

lSV

~~

HI

OF:::~ :>4'-'W\r-<.....~

O.OM

ADJUST

VIN
VOUT

-15V

~
--~-

VOUT
VIN

':'

'For lower gains, the lMI08 must be frequency compensated

100

Use:::: Av pF from comp 2

to ground

6-11

I--JWo-ll----'

.----

_~-RESET

-----~ -LTR~CK

---

= VB + AVIN(HOLOMODE)
TlIHI5692-7

Typical Applications (Continued)
Ramp Generator with Variable Reset Level
15Y

Integrator with Programmable Reset Level

v+
RI

Uk

-IIY

01
LMI13
1.2Y

RESET
LEYEL
INPUT

RESET
LEYEL
INPUT

OUTPUT

>=--i--6-00,OUTPUT

RZ
ZGIIk
III

RESET

5Y-n
By-J

L-

RAMP
DIFFERENTIAL
INTEGRATING
INPUT

1

RI
1M

",

o-"'W\r-....--"I
AV

.~~";;' ~g~ ramp rate ;IT =

R3
1M

1.2V
(R2) (CIll

1%
R4
lO1Ik
III

Output Holds at Average of Sampled Input

Increased Slew Current

OUTPUT

Fast Acquisition, Low Droop Sample & Hold

Reset Stabilized Amplifier (Gain of 1000)
Ik

1M

III

1"

OUTPUT

>~----",,-oOUT'UT

-1&Y

INPUT

31k

5Y-n
Dy-J

L-

--l I---

RESET PULSE
~2ml

Vos ,,; 20,.V (No trim)
ZIN:::: 1 Mn
AVos:::: 30,.Vlsec
At

AVos:::: 01uVl'C
AT

.

r

6-12

r-

"TI
....

Typical Applications

(Continued)
Synchronous Correlator for Recovering
Signals Below Noise Level

~
......
r-

2·Channel Switch

15V

~

15V

CQ

CD

......
r-

OUTPUT FREQUENCY

SET BY SWEEP RATE

.A

~~~~r-~t-OO~

.A.. ~IIGNAL

" V

V

NPUT

."

"B"INPUT

-I rIO.,
R5

10k

IZk

A

B
Gain
1 ± 0.02% 1 ± 0.2%
10100
47kO
liN
BIN
"" 1 MHz "" 400kHz
Crosstalk -90 dB
-90dB
@1 kHz
s: 6mV
s: 75 mV
Offset

1L

LM122H
TIMER
R&
ZDk
5 10

&

C3
410.F

R4
SOD

NC

'Select C1 to filter lowest frequency

TO SCOPE SWEEP
OUTPUT. SCALE R3
TO OBTAIN ~ UTO 3V
AT PIN 6.

component of input noise
"Select C2

@ '"

5 X 1O- 6/fIN

DC & AC Zeroing

Staircase Generator
ISV

DC
---VOS~'-~ ~

ZERO

CD

!:
r-

"B"SELECT

R2
1M

~~

.....
CQ

ov--I L-

....nr

R3

."

"A"SELECT
5V-n

SYNCHRONOUS
CLOCK INPUT

4

~
CQ
CD
......
r-

"A"INPUT

~

---~~.-.

15V

RESET
5V-n

ov-..I L-

RI
4.lk

>.':...-9---"'9'-0 OUTPUT
D3
LM113
1.2V

CLOCK
5V-n

n

R&*
SDk

ov-I L.J LRS
11k

T

C2
300.F
15V

':'

R4
Uk

I

RB

IZk
",,,,,,,,,,,,,-o15V

R9
3k
OZ
IN914

T

C4
300 F
•

':'

TUH/5692-9

'Select for step height
50k .... '" 1V Step

6·13

~

CD

l>

Typical Applications (Continued)
Capacitor Hysteresis Compensation

INPUT

>:....-....0

Differential Hold

OUTPUT

HI
200k

-L
Vs

LOGIC

'Select for time constant C1

-=-T

JL

= 1:0k

••Adjust for amplitude
TlIH/5692-10

Definition of Terms
Hold Step: The voltage step at the output of the sample
and hold when switching from sample mode to hold mode
with a steady (dc) analog input voltage. Logic swing is 5V.
Acquisition Time: The time required to acquire a new analog input voltage with an output step of 10V. Note that acquisition time is not just the time required for the output to
settle, but also includes the time required for all internal
nodes to settle so that the output assumes the proper value
when switched to the hold mode.

Hold Settling Time: The time required for the output to
settle within 1 mV of final value after the "hold" logic command.
Dynamic Sampling Error: The error introduced into the
held output due to a changing analog input at the time the
hold command is given. Error is expressed in mV with a
given hold capacitor value and input slew rate. Note that
this error term occurs even for long sample times.
Aperture Time: The delay required between "Hold" command and an input analog transition, so that the transition
does not affect the held output.

Gain Error: The ratio of output voltage swing to input voltage swing in the sample mode expressed as a per cent
difference.

6-14

til

!;;

....

Co)

o
o

Nat ion a I S e m ,i con due tor

G)

......
r-

....

."

LF13006/LF13007 Digital Gain Set

Co)

o

o
.....

General Description
The LF13006 and LF13007 are precision digital gain sets
used for accurately setting non-inverting op amp gains.
Gains are set with a 3-bit digital word which can be latched
in with WR and CS pins. All digital inputs are TTL and CMOS
compatible. .
The LF13006 shown below will set binary scaled gains of 1,
2, 4, 8, 16, 32, 64, and 128. The LF13007 will set gains of 1,
2,5,10,20,50, and 100 (a common attenuator sequence).
In addition, both versions have several taps and two uncommitted matching resistors that allow customization of the
gain.
The gains are set with precision thin film resistors. The low
temperature coefficient of the thin film resistors and their
excellent tracking result in gain ratios which are virtually independent of temperature.

The LF13006, LF13007 used in conjunction with an amplifier not only satisfies the need for a digitally programmable
amplifier in microprocessor based systems, but is also useful for discrete applications, eliminating the need to find
0.5% resistors in the ratio of 100 to 1 which track each
other over temperature.

Features
•
•
•
•
•
•

TTL and CMOS compatible logic levels
Microprocessor compatible
Gain error 0.5% max
Binary or scope knob gains
Wide supply range + 5V to ± 18V
Packaged in 16-pin DIP

Block Diagram and Typical Application (LF13006)

1SV

-1SV

ov

HI

R2
Lfl_

r--------------t-EXl
r-------....-BOUT

DIG IN
2

INPUT

DIG IN
LSB 1

.

DATA BUS

CONTROL
LINES

Vau.

TL/H/S114-1

Note: R'" 15 kll

Order Number LF13006N or LF13007N
See NS Package Number N16A

6-15

Absolute Maximum Ratings

Operating Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, V+ to V36V
Supply Voltage, V+ to GND
25V

Operating Temperature Range
Lead Temp. (Soldering, 10 seconds)

Voltage at Any Digital Input
Analog Voltage

-40"Cto +85'C
260"C

V+ toGND
V+ to (V- + 2V)

Electrical Characteristics (Note 2)
Parameter

Conditions

Typ
(Note 3)

Tested
Limit
(Note 4)

Design
Limit
(Note 5)

Units

0.5

0.5

%(max)

Gain Error

AOUT= ±10V
ANAGND=OV
IINPUT < 10 nA

0.3

Gain Temperature Coefficient

AOUT= ±10V
ANAGND=OV

0.001

Digital Input Voltage
Low
High
Digital Input Current
Low
High

%/'C

1.4
1.6

0.8
2.0

0.8
2.0

V(max)
V(min)

-38
0.0001

-100
1

2
-1.7

5
-5

-100
1
5
-5

!£A(max)
!£A(max)
mA(max)

Positive Power Supply Current

VIL =OV
VIH=5V
All Logic Inputs Low

Negative Power Supply Current

All Logic Inputs Low

Write Pulse Width, tw

VIL =OV, VIH=5V

150

ns(min)

Chip Select Set-Up TIme, tcs

VIL =OV, VIH=5V

250

ns(min)

Chip Select Hold Time, tcH

VIL =OV, VIH=5V

0

ns(min)

DIG IN Set-Up Time, tos

VIL =OV, VIH=5V

150

ns(min)

DIG IN Hold Time, tOH

VIL =OV, VIH=5V
(Note 4)

60

ns(min)

Switching Time for Gain Change

mA(max)

ns(max)

200

Switch On Resistance

3

Unit Resistance, R

15

12-18

R1 and R2 Mismatch

0.3

0.5

kO
kO
% (max)

0.5'

R1 IR2 Temperature Coefficient
0.001
%I'C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond Its specified operating conditions.
Note 2: Parameters are specified atV+ =15Vand V- = -15V, MinV+ to ground voltage Is 5V. Min V+ to V- vonageIs 5V. Boldlace numbera apply ovar lull
operating temperatura ranga.. All other numbers apply at TA = Tj = 25'C.
Note 3: Typlcals are at 25"C and represent most likely parametric norm.
Note 4: Guaranteed and 100% production tested.
Nota 6: Guaranteed (but not 100% production tested) over the operating temperature, These limits are not used to calculate outgoing quality levels.
Nota 6: Settling time lor gain change Is the switching time lor gain change plus settling time (see section on Settling Time).
Note 7: WR minimum high threshold voltage increases to 2.4V under the extreme condHlons when all three dlgHallnputs are simultaneously taken lrom OV to 5Vat
a slew rate of greater than 500Vl"s.

Connection Diagram
GAIN TABLE

Dual-In-Llne Package
Gain

Digital Input
LF13006
DIGln3

DIGln2

DIGln1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

AoUT
1
2
4
8
16
32
64
128

BOUT
1
1.25
2.5
5
10
20
40
80

DIGBND- 1

LF13007
AoUT
1
1.25
2
5
10
20
50
100

BOUT
1
1
1.6
4
8
16
40
80

6-16

U

ISI-WOND

INPUT- 2

151-82

v--

141-He

3

v+- •

13

00- 5

12

Baur- 6
iiii-7

r- R1
r- Aoor

111-Ci
101-0I81N3

11181Nl- •

91- 018 1M2
TDPV1EW

TUH/5114-2

r-----------------------------------------------------------------------------, ."
r
....W
Switching Waveforms
Q
Q

en
.....
r

....
W

."

les

cs

Q

ViH

Q

......

VIH

Wii
VIL

~

'--~

los

ViH5ii%

DATA BITS
VIL

5011

TUH/5114-3

Block Diagram and Typical Application (Continued) (LF13007)

:-1- -{- -i- -~-i-j-

- -- -,
LFl3007

r---------....- m

r - - - - - - . L - S DUT

DECODE

I
I

-1- - -1-

L.
INGIN

DIG IN

010 IN

MSB3

2

LSB 1

C1

DAllIBUS

\VII

CONTROL
UNES
TL/H/5114-4

Note: R .. 15 kO

6·17

~ r-------------------------------------------------------------------------------~

I....

Typical Performance Characteristics

~
....

Positive Power Supply
Current vs Temperature

g
....

C")

~

I-"tc-f-t..,..-t-+++-f

5.0

i

I
B

Negative Power Supply
Current vs Temperature

o

Digital Input Threshold vs
Temperature

Vs= ±5V

-1.0

~±10VI__

4.0

i- 2.0 100" i""'"

3.0

1ii-3.0

2.0

B-4.0

1.0

-5.0

~

~~

E

~ -Vs =±15V

)"

2.5

i...

-vttr

I!li

~ 0.5

o tttt±:±±I:±::I
-55

-15

25

65

105

-55

-15

TEMPERATURE ('C)

::>

::>

_ 2.0

9co 1.6

50

.

-55'C
I
f3 1.2 '-25'C

:z:

40

I

i!:

~

3D

i!i

20

0.8 - l r C
0.4

o

25'

55
105
TEMPERATURE ('C)

-15

o

---- .....

i".ooo

..... ~

I".",

i
;

200

100

Vs=±5V.....

~ttr

o

!400

-15

11

Vs=±5V ~ ~

.... ~.

~:~ ~ ....--

-55

I

-

Vs= ±2OV

55
105
TEMPERATURE ('C)

-15

25

v8=:f~\,.

Chip Select Set-Up Time, tea

a

i!!! 300

.... """ ~"'"

Vs=±15V

25
55
TEMPEJWURE ('C)

-55

20

6
10
15
SUPPLY VOLTAGE (V)

iuI 400

o

Write Width, tw

!]1300

~

500

l00

-15

400

Data Set-Up Time, 'tDS

i

.

..... i-'

500

!!i
~ 2G0

25
55
105
TEMPERATURE ('C)

-55

500

~

10
-55

o

105

2.4

60

Iii
........

65

Digital Input Threshold vs
Supply Voltage

ro~~~-r'-~~~

~

25

TEMPERATURE ('C)

Logical 0 Input Bias Current
vs Temperature

Vs=±15V , - -

~

.. 1.5

!i

300

;::

~200
C

~
Vs= ±5V

100, 'd1ov

o

-56

,

,"i-'"
Vsj±1 5V
Vs=±2OV

-15

25

65

105

TEMPERATURE ('C)
TUH/5114-5

~

U.
105

!;;

....

Application Information

W

use of a lead capaCitor from the inverting input to the output
of the amplifier. A lead capacitor is effective whenever the
feedback around an amplifier is reSistive, whether with discrete resistors or with the LF13006/7. It compensates for
the feedback pole created by the parallel resistance and
capaCitance from the inverting input of the op amp to AC
ground.
Settling Time Test Circuit

FLOW-THROUGH OPERATION
THE LF13006, LF13007 can be operated with control lines
CS and WR grounded. In this mode new data on the digital
inputs will immediately set the new gain value. Input data
cannot be latched in this mode.
INPUT CURRENT
Current flowing through the input (pin 2) due to bias current
of the op amp will result in a gain error due to switch impedance. Normally this error is very small. For example, 10 nA
of bias current flowing through 3 kO of switch resistance will
result in an error of 30 p.V at the summing node. However,
applications that have significant current flowing through the
input must take this effect into account.
SETTLING TIME

10/GAIN
o

Settling time is a function of the particular op amp used with
the LF1300617 and the gain that is selected. It can be optimized and stability problems can be prevented through the

T

OUT

IN

TL/H/5114-6

Typical Settling Time Curves

3-

l
Ili lk
14

J:

100

=
0-

100

!i

l

Ili lk

14

.=
=

Ii

~

~

l'!

Ii!
W

lk

.

!e

,.~

!!!
'"
!e

iii

co

Ii!
w

10

..

..

l'!

10

co

0-

.
:IE

;:

;:

;:
z

z

z

5

1

::I

Iii

0

'"

2

4 6 B 10 12
LEAD CAPACITOR (pF)

14

'"

10

w

:IE

:IE

100

::I

1

0

2

4 6 B 10 12
LEAD CAPACITOR (pF)

14

Iii

1
0

'"

2

4
6 B 10 12
LEAD CAPACITOR (pF)

14

TLlH/5114-7

Typical Applications
Variable CapaCitance Multiplier
C.ffoctive

~

Variable Time Constant Filter

Cl (gain set #)

Time constant

Note: Output swing at input op amp

~ ~ Cl

N ~ setting of LF13006

is multiplied by set gain. Signal

1
(range ~ 128 to 1)

range may be limited.

IN

12

ADur
12
ADUT

LF13006
LF13D07
15
INPUT 2

LF13006
LF13007

DIGITAL
CONTROL

14

15

2 INPUT
'::"

14

13

Cl
ANA
GND
16

ANA
GND
16

DIGITAL
CONTROL

BUFFERED
ALTERED~_~~~

OUTPUT

DU~(~i.~~~

'::"
TL/H/5114-9

TL/H/5114-B

6-19

C)
C)
Q)

....
I"""
"T1
....
W
C)

Q

.....

·......
CI
CI

....
LL

C")

...J

Typical Applications

(Continued)
Switchable Gain of ± 1 .

Programmable Current Source'

.;0

DIGITAL
IN

15Y

....~

3Dk

u..

...J

15
12
AOUT

.. lFI30D6

lF13DD6
lF13DD7

VOUT

,

LM385-1.2V

INPUT

ANA
GND
TLlH/5114-11

Note: Digital code = 000, VOUT=VIN;
Digital code=OOI, VOUT= -VIN

Programmable Differential Amp'
TL/H/5114-10

DIGITAL
IN

1.2V [
1
]
lOUT = 1200 gain set 1/

Inverting Gains
-IN

LfI3DD6
LF13DD7

ANA
16 GND

AOUT 12

DIGITAL
CONTROL
INPUr
+IN
LF130116
LF13DD7

16
ANA
GND
14

LF13DD6
LF13DD7

15

DIGITAL
IN

YaUT

YaUT

TL/H/5114-12

Inverting gain with high input im-

AUUT
12

pedance can be obtained with the
LFI3006, LF13007 by using the two

TL/H/5114-13

on-board resistors and a dual op

amp as shown.
Note 1: Actual gain = set gain-l
since LF13006s are in
"inverting mode".
Note 2: Set gain must be
same on both LFI3006s.

6-20

r-

Typical Applications
Altered Gain Range

."

.....

(Continued)

Co)

One Octave per Bit Function Generator

Variable Gains of Almost 1

Q
Q

en
......
r-

."

.....

OUT

~

Q

......
15

LF13OD6

12
AOUT

2 INPUT

2 INPUT
LF13OD6

INPUT 2

13
DIGITAL
CONTROL

13
DIGITAL
CONTROL

ANA
GND
16

AOUT

12

ANA
GND
16

TLlH/5114-14

TLlH/5114-16

10k

10k

TLlH/5114-15

GAINS
AOUT
1
1.8
3

GAINS
9
1.8
1.29
1.125
1.059
1.029
1.014
1.007

BOUT
1
1.2

2

6

4
4.8
5.33
5.65

7.2
8
8.47

Programmable Instrumentation Amp

Attenuator (0 dB to - 42 dB In 6 dB steps)
INPUT
12
AoUT

10k

LFl3DD6

ANA

LFI3DD6
LF13007

16 GNo

AoUT 12

10k
DUTPUT

INPUT

A-------I

ANA
GND
16
TLlH/5114-17

Note 1: VOUT=N (A-B). N=set gain.

TL/H/5114-1B

Note 2: All 10k resistors 0.1% matched.

6-21

Section 7
Active Filters

-----

------"

-

-- - - - -

---~

~-

- ------------

•

Section 7 Contents
Active Filters Definition of Terms.. . . .. . . . . .. . . . . . . . . .. . . . .. . . .. .. .. .. . . . .. . . . . . . . . . . .
Active Filters Selection Guide.............................. ..................... .....
LMF40 High Performance 4th-Order Switched Capacitor Butterworth Low-Pass Filter .......
LMF60 High Performance 6th-Order Switched Capacitor Butterworth Low-Pass Filter .......
LMF90 4th-Order Elliptic Notch Filter ................ , ., ............................ ...
LMF100 High Performance Dual Switched Capacitor Filter.... ................ ...........
LMF380 Triple One-Third Octave Switched Capacitor Active Filter........ ................
MF4 4th Order Switched Capacitor Butterworth Lowpass Filter............. ..............
MF5 Universal Monolithic Switched Capacitor Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MF6 6th Order Switched Capacitor Butterworth Lowpass Filter...........................
MF8 4th Order Switched Capacitor Bandpass Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MF10 Universal Monolithic Dual Switched Capacitor Filter...............................

7-2

7-3
7-4
7-5
7-19
7-37
7-57
7-79
7-89
7-102
7-117
7-135
7-157

»n

~.

tflNational Semiconductor

::!!

ii

1-s·

Active Filters
Definition of Terms

(I)

;::;:

o·
::l

-

o

Vz

felK: the switched capacitor filter external clock frequency.

HOHP: the gain in (V IV) of the high pass output of each

fo: center of frequency of the second order function complex pole pair. fo is measured at the bandpass output of
each Vz MF1 0, and it is the frequency of the bandpass peak
occurrence.
Q: quality factor of the 2nd order function complex pole pair.
a is also measured at the bandpass output of each Vz MF1 0
and it is the ratio of fo over the -3 dB bandwidth of the 2nd
order bandpass filter. The value of a is not measured at the
lowpass or highpass outputs of the filter, but its value relates to the possible amplitude peaking at the above outputs.
HOBP: the gain in (V IV) of the bandpass output at f = f o.

MF10 as f fCLK/2.
Qz: the quality factor of the 2nd order function complex zero
pair, if any. (az is a parameter used when an allpass output
is sought and unlike a it cannot be directly measured).

HOlP: the gain in (V IV) of the lowpass output of each
MF10atf- o Hz.

--

-t

..,.

(I)

3

o

fz: the center frequency of the 2nd order function complex
zero pair, if any. If fz is different from fo, and if the az is
quite high it can be observed as a notch frequency at the
all pass output.
fnotch: the notch frequency observed at the notch output(s)
of the MF10.

Vz

HON1: the notch output gain as f -

0 Hz.

HON2: the notch output gain as f -

fCLK/2.

------~----

---------~----------

------

-------

fI

7-3

IfI

National Semiconductor

Active Filter Selection Guide

Device #
MF10 (5, T)
MFB (T)

Type

Function

Max
Order

Max Freq
Accuracy.

Freq
Rlmge "

Typ.Q
Accuracy

Max
F·xQ

Universal

Universal

4th

±O.S%

0.1-30 kHz

±2%

,200kHz

Bandpass

Chebyshev
Butterworth,

4th

±1.0%

0:1-20 kHz

±2%

5 MHz·

MFS(5, T)

Lowpass

Butterworth

Sth

±1.0%

0.1-20 kHz

N/A '

MF5(5)

Universal

Universal

2nd

±1.0%

0.1-30 kHz

±S%

MF4(5)

Lowpass

Butterworth

4th

±O.S%

0.t-20kHz

N/A,

N/A

LMF40(5, T)

Lowpass

Butterworth

4th

±1.0%

0.1-40 kHz,

N/A

N/A

LMFSO(5, T)

Lowpass

Butterworth

6th

±1.0%

0.1-30 kHz

N/A

N/A

LMF100 (5, T)

Universal

Universal

4th

±O.S%

0.1-40 kHz

±2%

1.BMHz

4th

±1%

0.1-30 kHz

N/A

N/A

12th

±0.5%
(typ)

0.1-25 kHz

N/A

N/A

LMF90(5, T)

Notch

Elliptic

LMF3BO

Triple
One-Third Octave

Triple
Bandpass

S Surface Mount Available
T Extended Temperature Available
'For the MFa use clock frequency for the parameter F. For all other parts use the center or cut off frequency.

N/A
200kHz

,-------------------------------------------------------------------------, r

:s:::

]2

t!lNational Semiconductor

o

LMF40 High Performance 4th-Order
Switched-Capacitor Butterworth Low-Pass Filter
General Description

Features

The LMF40 is a versatile, easy to use, precision 4th-order
Butterworth low-pass filter fabricated using National's high
performance LMCMOS process. Switched-capacitor techniques eliminate external component requirements and alIowa clock-tunable cutoff frequency. The rati'o of the clock
frequency to the low-pass cutoff frequency is internally set
to 50-to-l (LMF40-50) or 100-to-l (LMF40-100). A Schmitt
trigger clock input stage allows two clocking options, either
self-clocking (via an external resistor and capacitor) for
stand-alone applications, or for tighter cutoff frequency control, an external TTL or CMOS logic compatible clock can
be applied. The maximally flat passband frequency response together with a DC gain of 1 V IV allows cascading
LMF40 sections together for higher-order filtering.

• Cutoff frequency range of 0.1 Hz to 40 kHz
• Cutoff frequency accuracy of ± 1.0%, maximum
II Low offset voltage, ± 100 mV, maximum, ± 5V supply
• Low clock feedthrough of 5 mVp_p, typical
II Dynamic range of BB dB, typical
• No external components required
• B-pin mini-DIP or 14-pin wide-body small-outline packages
II 4V to 14V single/dual supply operation
II Cutoff frequency set by external or internal clock
• Pin-compatible with MF4

Applications
II Communication systems

• Instrumentation
II Automated control systems

Block and Connection Diagrams
fiLTER OUT

Dual-In-Line Package

y+

LTER
CLK I H [
. J
8 'FJ
CLKR
2
7

or

_________ !....s.~ __ L _____6

fiLTER IN

I(

5~IiF

1(4

TL/H/l0557-2

AGND

Top View

CLKIN

Small-Outline-Wide-Body Package
CLK IN

1

HC

L.Sh
TLlH/l0557-1

"Pin numbers in parentheses are for the 14-pin package

Ordering Information
NOSE

LMF40CIWM-50

M14B

LMF40CIWM-l00

M14B

HC

12

or

4

11

HC

L.Sh

5

10

HC

6

9

I(

7

8

Top View

Military (-55"C ~ TA ~ +125'C)
LMF40CMJ-50, LMF40CMJ-l00

FJLTER

13

AGND
HC

~IiF
TL/HI1 0557-3

Package

LMF40CIN-50, LMF40CIN-l00

14

HC

CLK R
CLKR

Industrial (-40'C ~ TA ~ +85'C)

_AGND_______ _

JOBA

7-5

•

Absolute Maximum Ratings
(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V+ -V-)
15V
V- - 0.2V to V+ + 0.2V
Voltage at Any Pin

Lead Temperature
N Package, Soldering (10 sec.)
J Package, Soldering (10 sec.)
WM Package, Vapor Phase (60 sec.) (Note 16)
WM Package,lnfrared (15 sec.)

Input Current at Any Pin (Note 13)

5mA

Package Input Current (Note 13)

20mA

ESD Susceptibility (Note 12)
Pin 1 CLKIN

Power Dissipation (Note 14)

2000V
1700V

Operating Ratings (Notes 1 & 2)

500mW
-65·C to + 150·C

Storage Temperature

+ 260·C
+300·C
+215·C
+ 220·C

Temperature Range
TMIN S; TA S; TMAX
LMF40CIN-50, LMF40CIN-100
LMF40CIWM-50,
. -40·CS;TAs; +85·C
LMF40CIWM-100
LMF40CMJ-50, LMF40CMJ-100 - 55·C S; T A S; + 125·C
Supply Voltage.Range (V+ - V-)

4Vto 14V

Filter Electrical Characteristics
The following specifications apply for fCLK = 500 kHz. Boldface limits apply for T A = TJ = TMIN to TMAX: All other limits T A
= TJ =.25·C.

Symbol

Parameter

Typical
10)

Conditions

(Not~

Limits
(Note 11)

Units
(Limit)

2

Hz (min)
MHz (max)

Y+ = +5Y, Y- = -5Y
fCLK

Clock Frequency Range
(Note 17)
5
..

IS

Supply Current

CMJ
CIN, CIJ, CIWM

3.5/7.0
3.5i 5.0

mA(max)
mA(max)

Ho

DC Gain

RSource S; 2 kO

+ 0.05 1 + 0.05

dB (max)
dB (min)

-0.151 -0.20
fCLK/fc

AfCLK/fcl A T

AM IN

Clock to Cutoff
Frequency Ratio
(Note 3)
LMF40-50
LMF40-100

49.80 ± 0.8% 1 49;aO
99.00 ± 0.8% 199.00

Clock to Cutoff Frequency
Ratio Temperature
Coefficient
LMF40-50
LMF40-100
Stopband Attenuation

24.0

7-6

(max)
(max)

ppml"C
ppm/·C

5
5
At2fc

± 1.0"10
± 1.0"10

dB (min)

r

s::

Filter Electrical Characteristics (Continued)
The following specifications apply for fCLK
= TJ = 25°C.
Symbol

=

V+

Parameter

+5V, V-

=

=

."

500 kHz. Boldface limits apply for T A

Typical
(Note 10)

Conditions

TJ

=

T MIN 'to T MAX: All other limits T A

Limits
(Note 11)

Units
(Limit)

±80/±100
±801 ±100

mV(max)
mV(max)

+3.91 +3.7
-4.21 -4.0

V (min)
V (max)

0l:Io

o

-5V (Continued)

Unadjusted DC
Offset Voltage
LMF40-50
LMF40-100

Vas

=

=

Va

Output Swing

RL

Isc

Output Short Circuit
Current (Note 8)

Source
Sink

5 kn

Dynamic Range
(Note 4)
Additional Magnitude
Response Test Points
(Note 6)
LMF40-50
LMF40-100
Clock Feedthrough

fiN
fiN
fiN
fiN

=
=
=
=

mA
mA

88

dB

12 kHz
9 kHz

- 7.50 ± 0.26 1 - 7.50 ± 0.30
-1.46 ±0.121 -1.46 ±0.16

dB (max)
dB (max)

6 kHz
4.5 kHz

-7.15 ±0.261 -7.15 ±0.30
-1.42 ±0.12/-1.42 ±0.16

dB (max)
dB (max)

Filter Output
VIN

90
2.2

=

mVp_p

5

ov

Filter Electrical Characteristics The following specifications apply for fCLK = 250 kHz. Boldface limits
applyforTA

=

TJ

Symbol

=

TMIN to TMAX: All other limits TA

Parameter

=

TJ

Conditions

=

25°C.
Typical
(Note 10)
~.-

V+

=

fCLK

+2.5V, V-

=

.-

Limits
(Note 11)

Units
(Limit)

1.0

Hz (min)
MHz (max)

-2.5V

Clock Frequency Range
(Note 17)
5

Is

Supply Current

CMJ
CIN, CIJ, CIWM

2.1/4.0
2.1/3.0

mA(max)
mA(max)

Ha

DC Gain

Rs:5:2kn
fCLK = 250 kHz

+ 0.05 1 + 0.05

dB (max)
dB (min)

fCLK
fCLK/fc

Clock to Cutoff
Frequency Ratio
LMF40-50

LMF40-100
(Note 3)

=

-0.15/-0.20
-0.1

500 kHz

= 250 kHz
fCLK = 500 kHz
fCLK

fCLK
fCLK

dB

49.80 ±0.8%

(max)

99.00 ± 1.0% 1 99.00 ± 1.2%

(max)

fI

49.80
±0.6%

= 250 kHz
= 500 kHz

99.00
±1.2%

,

7-7

Filter Electrical Characteristics (Continued)
The following specifications apply for fCLK = 250 kHz. Boldface limits apply forTA = TJ = TMIN to TMAX: All other limits TA
= TJ = 25'C.
Symbol

Parameter

Conditions

Typical
(Note 10)

limits
(Note 11)

Units
(limit)

V+ = +2.5V,V- = -2.5V(Continued)
ilfCLKlfcl  V+) the absolute value of the current at that pin should
be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply voltages with 5 rnA current limit to four.
Note 14: The maximum power dissipation must be de·rated at elevated temperatures and is dictated by TJMAX, 8JA, and the ambient temperature TA. The
maximum allowable power dissipation is PD = (TJMAX - TAll8JA or the number given in the Absolute Maximum Ratings, whichever is lower. For the LMF40,

TJMAX = 125'C, and the typical junction·to·ambient thermal resistance, when board mounted, is 67'C/W for the LMF40CIN, 62'C/W for the LMF40CIJ and
LMF40CMJ, and 78'C/W for the LMC40CIWM.
Note 15: In popular usage the term cutoff frequency defines that frequency at which a filter's gain drops 3.01 dB below its DC value. Equations (2) and (3) and
design example 2.1, however, use the term cutoff frequency (fb) to define that frequency at which a filter's gain drops by a variable amount as determined from the
given design specifications.

Note 16: See AN·450 "Surface Mounting Methods and Their Effect on Product Reliability" for other methods of soldering surface mount devioes or see the section
titled "Surface Mount" in the Linear Dsts 800k.
Note 17: The nominal ratio of the clock frequency to the low·pass cutoff frequency is internally set to 50·to·l (LMF40·50) or 100·to·l (LMF40·100).

7-9

•

Typical Performance Characteristics
fCLK/fe Deviation
vs Power Supply Voltage

os

D.6

Uotf40-50
'CLJ(" 500 kHz
TA=25CC -

0.7

1

-Il2

10

4

12

14

-ss

POWER SUPPlY VOLTAGE (V)

25

65

0.1

0.0

-Il2

z

-D.3

!:!

-0.4

ii

!

-0.1

g

......

'CLJ("S~~
T
A=25CC

-0.&
4

10

12

1"-

tf

LMF40-So
ia.K= SOD kHz
-D.3

14

-ss

POWER SUPPLY VOLTAGE (V)

112

!
......

Uotf40-S0_

25

65

I

-1.0

!:!

-1.4

~

D.05

105

r-t-"

f5

10

4

12

14

..!.~~

.....

r-

-Il2

-ss

-IS

25

65

~

Vs=SV

I
..

I/~

o

D.5

1

Uotf40-100
'CLK=SoOrZ
TA=25CC

-a;-

-Il2

SUPPLY VOLTAGE (V)

14

I
UotF4o-100
'ClK= SIOo krz·

III

g

-D.6

z

-1.0

!:!

-1.4
-1.8

-!III

-15

Z5

65

TEMPfRATURE ("C)

1.5

\
2.5

2J)

, . ,""vs=IOYI

I\..

~

-Il2

12

1.0

112

11

10

~4s=IOY~

I

DC Gain Deviation
its Clock Frequency

~ -0.10

4

-I

DC Gain Deviation
vs Temperature

Vs=SV.IOY

-D.2O

I/

CLOCK FREQUENCY (MHz)

.......... i-' .....

!:!

v~=;p ' - l -

.,
-s

105

112

fo"

2.5

2J)

I I
I I

DC Gain Deviation
vs Power Supply Voltage

I,..o ....

1.5

UotF40-IOo

TEMPERATURE (CC)

0.10

1.0

-0.I

SUPPLY VOLTAGE (V)

I

D.5

+3

~J,~ ,.....

0.0

LMf40-IOO
'cUe= SOO kHz
TA=2SCC I

-o.IS

o

\

fCLKlfe Deviation
vs Clock Frequency

0.1

-0.10

I
I

CLOCK FREQUEHCY (MHz)

UotF40-I~~.
'Cf,OkHZ

1,..0-

....

vs=sv

fCLKlfe Deviation
vs Temperature
112

0.10

i'

\

A"

YS:=IOY

-D.6

TEMPERATURE (CC)

fCLKlfe Deviation
vs Power ,Supply Voltage

2.5

2J)

,

Uotf40-50

-Il2

-1.8

-IS

1.5

DC Gain Deviation
vs Clock Frequency

..........

0.0

1.0

D.5

CLOCK FREQUENCY (MHz)

V~'~-

I

-o.s

o

DC Gain Deviation
vs Temperature

0.1

I

I

\'If

-s

105

1'\

Vs=10V

TEMPERATURE (CC)

DC Gain Deviation
vs Power Supply Voltage

-,

-3

T

-IS

V

I

Vs=loV

-0.1

Vs=5V

I

1

f-l- I.,;

~T=-fF

0.0

0.1

U.tf40-SO

+3

VS=jJ

'ClK= 400 kHz
VsiSt

D.3

~

f5

Uot~40-Sol
'CLJ(" SOD kHz

D.5

!

fCLKlfe Deviation
vs Clock Frequency

fCLKlfe Deviation
vs Temperature

105

~

II

'I.

Vs=5~ r-rLMF40-50

",

I

I
o

1

D.5

1.0

1.5

2J)

2.5

CLOCK FREQUENCY (MHz)

TLlH/10557-5

7-10

Typical Performance Characteristics
Power Supply Current
vs Power Supply Voltage
3.0

(Continued)

Positive Voltage Swing
vs Power Supply Voltage

Power Supply Current
vs Temperature
4.D

fClK= 500 kHz
TA=25"C

'~500kHz

'cue= 500 kHz

./

T.=25"C
RL= 5 kll

3.5

1/
1/

]:

Ys=IOV)i ~

2.5

,
1A

3.D

V

.....

2.D

.A'

~

"",I-'"
1.5

Ys=jY

1.0

1.0

4

10

12

1
-15

-55

14

POWER SUPPLY VOLTAGE (V)

Negative Voltage Swing
vs Power Supply Voltage

10

.....

Negative Voltage Swing
vs Temperature

I

..

Y =10Y

£

f~500kHz

>

.....

-7
12

I'

~

Ys =5Y

i""'"

-5.5

-15

-55

25

105

65

-55

10

10

'"

.....

"- 1'1,.,

--

-

-----

~jY

..... ~

~ ~O~

-~

12

14

-15

POWER SUPPLY VOLTAGE (V)

25

105

65

---1--1-11

-

--

~~

~ ~r;n

~~
....
..... "
.",

T.=125"C

11
I I

0.5
-55

--

T.=-5~ 1-"',

f~500kHz

-20

---

T.=25"C
1.5

V

'~500tz

-

2.D

1.0
T.=25"C

105

65

ClK R Trigger Threshold
vs Power Supply Voltage
2.5

-,---- --

25

1IIIPERATURE ("C)

DC Offset Voltage Deviation
vs Temperature

1-1-

10

-15

1IIIPERATURE ("C)

DC Offset Voltage Deviation
vs Power Supply Voltage

4

Y!':'0Y

-4.5

z

1

14

POWER SUPPLY VOLTAGE (V)

-30

-

III -3.5 RL=5kll
~
0

.....
r....

"I- ......

VS=5V

-2.5

!

RL=5kll

10

14

Positive Voltage Swing
vs Temperature

f~500kHz

r'I..

12

POWER SUPPLY VOLTAGE (V)

f~500kHz

4

105

65

1IIIPERATURE ("C)

TA=2S"C r-

....

25

4

10

12

14

POWER SUPPLY VOLTAGE (V)

1IIIPERATURE ("C)

Schmitt Trigger Threshold
vs Power Supply Voltage

TI=2~
Yr+

I'
1

"

4

'/

'" "

~

~~

,

6

II
~

.... ~

Yr

10

12

14

POWER SUPPLY VOLTAGE (V)
TL/H/l0557-6

7-11

0

~

u.
:::::i

....I

Pin Descriptions
(Numbers in ( ) are for 14-pin package).
Pin
11

1
(1)

2
(3)

3
(5)

5
(8)
6

(10)

Pin
Name
" 'ClKIN

ClKR

L. Sh

FilTER
OUT
AGND

Pin

Function

11

ACMOS Schmitt-trigger input
to be used with an external
CMOS logic level clock. Also
used for self clocking Schmitttrigger oscillator (see Section
1.1).
A TTL logic level clock input
when in split supply operation
(± 2.OY to ± 7V) with L. Sh
tied to system ground. This pin ,
becomes a low impedance
output when L. Sh is tied to
Y-. Also used in conjunction
with the ClK IN pin for a self
clocking Schmitt-trigger
oscillator (see Section 1.1).
, The TTL input signal must not
exceed the supply voltages by
more than 0.2Y.
level shift pin; selects the
logic threshold levels for the
clock. When tied to Y- it
enables an internal TRISTATE® buffer stage between
the Schmitt trigger and the
internal clock level shift stage
thus enabling the ClK IN
Schmitt-trigger input and
making the ClK R pin a low
impedance output. When the
voltage level at this input
expeeds 25% (V+ - Y-) +
Y- the internal TRI-STATE
buffer is disabled allowing the
ClK R pin to become the
clock input for the internal
clock level-shift stage. The
ClK R threshold level is now
2Y above the voltage on the L.
Sh pin. The ClK R pin will be
compatible with TTL logic
levels when the lMF40 is
operated on split supplies with
the L. Sh pin connected to
system ground.
The output of the low-pass
filter.
The analog ground pin. This
pin sets the DC bias level for
the filter section and must be
tied to the system ground for
split supply operation ,or to
mid-supply for single supply
operation (see Section 1.2).
When tied to mid-supply this
pin should be well bypassed.

7,4
(7, ~2)

8
,(14)

Pin
Name
Y+,Y-

Function

FilTER'
IN

The positive and negative
supply pins. The total power
supply range is 4Y,to 14Y.
Decoupling these pins with
0.1, p.F capacitors is highly, '
recommended.
,
The input to the low-pass filter.
To minimize gain errors the
source impedance that drives
this input should be less than
2k (see Section 3). For single
supply operation the input
signal must be biased to midsupply or AC coupled through
a capacitor.

1.0 LMF40 Application Information
The lMF40 is a non-inverting unity gain low-pass fourth-order Butterworth switched-capacitor filter. The switch~d-ca­
pacitor topology makes the cutoff frequency (where the gain
drops 3.01 dB below the DC gain) a direct ratio (100:1 or
50:1) of the clock frequency supplied to the filter. Internal
integrator time constants set the filter's cutoff frequency.
The resistive element of these integrators is aCtually 'a capaCitor which is "switched" at the clock frequency (for a
detailed discussion see Input Impedance section). Varying
the clock frequency changes the value of this resistive element and thus the time constant of the integrators. The
clock-to-cutoff-frequency ratio (fClKlfcl is set by the ratio of
the input and feedback, capacitors in the integrators. The
higher the clock-to-cutoff-frequency' ratio the closer this approximation is to the theoretical Butterworth response.
1.1 CLOCK INPUTS
The lMF40 has a Sch,mitt-trigger inverting ,buffer which can
be used to construct a simple R/C oscillator. Pin 3 is connected to Y-, making Pin ,2 a low impedance output. The
oscillator's frequency is nominally

which is typically
1

fClK '" 1.37 RC

(1 a)
for Vee = lOY.
Note that fClK is dependent on the buffer's threshold levels
as well as the resistor/capacitor tolerance (see Figure 1).
Schmitt-trigger threshold voltage levels can change significantly causing the R/C oscillator's frequency to vary greatly
from part to part.
Where accurate cutoff frequency is required, an external
clock can be used to drive the ClK R input of the lMF40.
This input is TTL logiC level compatible and also presents a
very light load to the external clock source (- 2 p.A). With
split supplies and the level shift (L. Sh) tied to system
ground, the logic level is about 2Y. (See the Pin Description
, for l. Sh).

7-12

.:s:::

1.0 LMF40 Application Information (Continued)
1.2 POWER SUPPLY
The LMF40 can be powered from a single supply or split
supplies. The split supply mode shown in Figure 2 is the
most flexible and easiest to implement. Supply voltages of
± 5V to ± 7V enable the use of TTL or CMOS clock logic
levels. Figure 3 shows AGND resistor-biased to V+ 12 for
single supply operation. In this mode only CMOS clock logic.
levels can be used, and inpu1 signals should be capacitorcoupled or biased near mid-supply.

As an example, with a source impedance of 10 k!l. the overall gain would be:
1 M!l.
Av = 10 k!l. + 1 M!l. = 0.99009 or -0.086 dB

1.3 INPUT IMPEDANCE

The filter's cutoff frequency (fel has a lower limit due to
leakage currents through the internal switches draining the
charge stored on the capacitors. At lower clock frequencies
these leakage currents can cause millivolts of error. For example:

Since the maximum overall gain error for the LMF40 is
+0.05, -0.15 dB @ 25'C with Rs ,,; 2 k!l. the actual gain
error for this case would be -0.04 dB to -0.24 dB.

1.4 CUTOFF FREQUENCY RANGE

The LMF40 low-pass filter input (FILTER IN) is not a high
impedance buffer input. This input is a switched-capacitor
resistor equivalent, and its effective impedance is inversely
proportional to the clock frequency. The equivalent circuit of
the filter's input can be seen in Figure 4. The input capacitor
charges to VIN during the first half of the clock period; during the second half the charge is transferred to the feedback capacitor. The total transfer of charge in one clock
cycle is therefore = CIN VIN, and since current is defined
as the flow of charge per unit time, the average input curren\
becomes

fCLK = 100 Hz, ILeakage = 1 pA, C = 1 pF

V1pA
_
- 1 pF (100 Hz) - 10 mV
The propagation delay in the logic and the settling time required to acquire a new voltage level on the capacitors limit
the 1i\ter's accuracy at high clock frequencies. The amplitude characteristic on ± 5V supplies will typically stay flat
until fCLK exceeds 1.5 MHz and then peak at about 0.1 dB
at the corner frequency with a 2 MHz clock. As supply voltage drops to ±2.5V, a shift in the fCLK/fe ratio occurs which
will become noticeable when the clock frequency exceeds
500 kHz. The response of the LMF40 is still a good approximation of the ideal' Butterworth low-pass 'characteristic
shown in Figure 5.

a

liN = alT
(where T equals one clock period) or
CINVIN
liN AVE = - T - = CIN VIN fCLK
The equivalent input resistor (RIN) then can be expressed
as
. VIN
1
RIN=-=--liN
CIN fCLK
The input capacitor is 2 pF for the LMF40-50 and 1 pF for
the LMF40-100, so for the LMF40-100

2.0 Designing with the LMF40

Given any low-pass filter specification, two equations will
come in handy in trying to determine whether the LMF40 will
do the job. The first equation determines the order of the
1 X 1012
1 X 1012
1 X 1010
low·pass filter required to meet a given response specifica______tiQn: ______ ~ _______ - ------ -------- -------- -------~_ _ _R_IN = iCLK __:je~ 1Q(L:~
log [(100.1Amin - 1)/(100.1Amax - 1)]
and
n=
(2)
5 X 1011
5 X 1011
1 X 1010
2 log (fs/fb)
RIN = - - - = - - - = - - where n is the order of the filter, Amin is the minimum stopfCLK
fe x 50
fe
band attenuation (in dB) desired at frequency fs, and Amax is
for the LMF40-50. The above equation shows that for a
the passband ripple or attenuation (in dB) at cutoff frequengiven cutoff frequency (fel, the input resistance of the
cy fb (Note 15). If the result of this equation is greater than
LMF40-50 is the same as that of the LMF40-100. The high4, more than one LMF40 will be required.
er the clock-to-cutoff-frequency ratio, the greater equivalent
The attenuation at any frequency can be found by the folinput resistance for a given clock frequency.
lowing equation:
This input resistance will form a voltage divider with the
Attn (I) = 10 log [1 + (100.1Amax - 1)(flfb)2n]dB
(3)
source impedance (RSouree). Since RIN is inversely proportionalto the cutoff frequency, operation at higher cutoff fre·
where n = 4 for the LMF40.
quencies will be more likely to attenuate the input signal
2.1 A LOW-PASS DESIGN EXAMPLE
which would appear as an overall decrease in gain to the
output of the filter. Since the filter's ideal gain is unity, the
Suppose the amplitude response specification in Figure 6 is
given. Can the LMF40 be used? The order of the Butteroverall gain is given by:
worth ~pproximation will have to be determined using (1):
AV =
RIN
Amin = 18 dB, Amax = 1.0 dB: fs = 2 kHz, and fb = 1 kHz
RIN + RSource
If the LMF40-50 or the LMF40-100 were set up for a cutoff
log[(101.8 - 1)/(100.1 - 1)]
frequency of 10kHz the input impedance would be:
n=
2 log(2)
= 3.95
RIN =

I!

'0

1 x 1010
10kHz = 1 M!l.

Since n can only take on integer values, n = 4. Therefore
the LMF40 can be used. In general, if n is 4 or less a single
LMF40 can be utilized.

7-13

,.

2.0 Designing with the LMF40 (Continued)
Likewise, the attenuation at fs can be found using (3) with
the above values and n = 4:
Attn (2 kHz) = 10 log[1 + 100.1 - 1)(2 kHz/1 kHz)B]
= 18.28 dB
This result also meets the design specification given in Fig#re 6 again verifying that a single LMF40 section will be
adequate.
Since the LMF40's cutoff frequency (fc), which corresponds
to a gain attenuation of -3.Q1 dB, was not specified in this
example, it needs to be calculated. Solving equation (3)
where f = fc as follows:
f = f .[100.1(3.01 dB) - 1 ]1/(2n l
c
Ii (100.iAmax _ 1)
_
[100.301 - 1 ]I/B
- 1 kHz 100.1 _ 1
= 1.184 kHz
where fc = fClK 150 or fCLK/100. To implement this example for the LMF40-50 the clock frequency will have to be set
tofClK = 50(1.184 kHz) = 59.2 kHz, or tor the LMF40-100,
fCLK = 100 (1.184 kHz) = 118.4 kHz.

ureBa.

In determining whether the cascaded LMF40s will yield a
filter that will meet a particular amplitude response specification, as above, equations (4) and (5) can be used, shown
below.

-=

2.3 CHANGING CLOCK FREQUENCY
INSTANTANEOUSLY
The LMF40 responds well to an instantaneous change in
clock frequency. If the control signal in Figure 9 is low the
LMF40-50 has a 100 kHz clock making fc = 2 kHz; when
this signal goes high the clock frequency changes to 50 kHz
yielding tc = 1 kHz. As Figure 9 illustrates, the output signal
changes quickly and smoothly in response to a sudden
change in clock frequency.
'
The step response of the LMF40 in Figure .10 is dependent
on fc. The LMF40 responds as a classical fourth-order Butterworth low-pass filter.
2.4 ALIASING CONSIDERATIONS
~liasing effects have to be considered when input signal
frequencies exceed half the sampling rate. For the LMF40
this equals half the clock frequency (fcud. When the input
signal contains a component at a frequency higher than half
the clock frequency tCLK/2, as in Figure 11a, that component will be "reflected" about fCLK/2 into the frequency
range below fClK/2, as in Figure 11b. If this component is
within the passband of the filter and of large enough amplitude it can cause problems. Therefore, if frequency cbmponents in the input signal exceed fCLK/2 they must be attenuated before being applied to the LMF40 input. The necessary amount of attenuation will vary depending on system
requirements. In critical applications the signal components
above fClK/2 will have to be attenuated at least to the filter's residual noise level.

2.2 CASCAD'It4G LMF40s
When a steeper stopband attenuation rate is required, two
LMF40s can be cascaded (FlfJure 7) yielding an 8th order
slope of 48 dB per octave. Because the LMF40 is a Butterworth filter and therefore has no ripple in its passband,
when LMF40s are cascaded the resulting filter also has no
ripple in its passband. Likewise the DC and passband gains
will remain at 1V1V. The resulting response is shown in FIfJ-

n=

Equation (4) will determine whether the order of the filter is
adequate (n s; 4) while equation (5) can determine the actual stopband attenuation and cutoff frequency (fel nece,ssary
to obtain the desired frequency response. The design procedure would be identical to the one shown in. Section 2.0.

log[(10,o.OSAmln - 1)/(10Q.OSAmax - 1)]

;..;;.:::.::.:..;.co.:.--.:..-:--:--~~

2Iog(fslfb)

___

(4)

Attn (I) = 10 log [1 + (100.05Amax - 1) (flfb)2]dB
where.' n ''''; 4 (the order of each filter).

(5)

1=

1

RC In[ (vee -Vt- ) (Vt

vee- vt +

LMF40

1 ..

R

3

2

(Vcc

L.SH

vTL/H/l0557-7

FIGURE 1. Schmitt Trigger RIC Oscillator

7-14

1

'i":37iiC
= 10y)

+)]

vt -

2.0 Designing with the LMF40 (Continued)

5V-n n
-5V--1 U L

ClK IN

FilTER IN

N.C. 2 ClK R

v+!-=--......-

N.C.

5V
O.lpF

5V:n..rL
OV

3
VIH;;' 0.8 Vee
VIL ,; 0.2 Vee
Vee = V+ - V-

I

ClK IN

O.lpF

LIIF40
l.SH

AGND

4y-

8

7
v+ j-:--......
-+5V

2 CLK R
3

-5V

FILTER IN

FILTER OUT

Tl/H/10557-8

6

5
TL/H/10557-9

(a)

(b)

FIGURE 2. Split Supply Operation with CMOS Level Clock (a), and TTL Level Clock (b)

IOV-n n
ov-1 U L

ClK IN

FilTER IN

~"'--Ir

VIN

Btl!.

N.C.

2

y+ 7

ClK R

10V

I

lMF40

O.IPF
10 kl!.

AGND ~....----_~-.
lOkI!.
FilTER OUT

0.1 }.

:::E

-60
-70
-90
100

IIllr,"

fCLK= 750 kHz~

feLK;;,), MH,i

I
11111111 I

11111111
lk

10k

..\'ft

\\ "oS'

-~

~
~

\'

lOOk,

FREQUENCY (Hz)

TLlH/l0557-16

FIGURE 5d. LMF40-50 Amplitude
, Response with ± 2.SV Supplies

m~

I!l

E
~

::l!

AYIN =-18 "-' - --- - - - -- -- - - -- --

o

'fb=l kHz f.'=2kHz
FREQUENCY (Hz)
TLlH/l0557-17

FIGURE 6. Design Example Magnitude Response
Specification. The response of the filter design
must fall within the shaded area of the specification.

7-16

lOOk

TL/H/l0557-15

II~j

II(§;\~

-so

10k

FIGURE 5c. LMF40-100 Amplitude
Response with ± 2.5V Supplies

~..,..~

-20

~\

-90 LUJ.WlD-lllllllllLl

TLlH/l0557-14

10

~

~

fREQU~CY (Hz)

FIGURE 5b. LMF40-S0 Amplitude
Response wlth± SV Supplies

FIGURE 5a. LMF4D-100 Amplit!lde
Response with '± 5V Supplies

\

-;, 'S

f-c:.

FREQUENCY (Hz)

fREQUENCY (Hz)

-

-so I-+Hf!IIH1':'~lIH-~1':~-~1<~llI-iHfl
-70

lOOk

10k

\

16'

-20
-30
-<10

-80 H++I-HllH-+mtHIIt

~o~~~-L~~~WWUU~

100

11
2.'
I"'\'..~\ ~\n-'lI1\;'>';\I.-t111

-10

iii'

2.0 Designing with the LMF40 (Continued)
lMF40

v-

y+

FILTER
IN

5

LMF40

7

4

FILTER
OUT

ClK R
2

v-

y+

rlLTER
IN

ClK R

4

7

2

FILTER
OUT

V+=+5Vo---~~---o--~--+---------------~~~~
V-=-5Vo---4-------~~~-----------------~------~

----------------------------...J

feLK o-----------------....

TL/H/l0557-1B

FIGURE 7. Cascading Two LMF40s

10

()O

0

-1000

"'10
'iii'

-20

..,c

-30

:z

I:

-40

:::E

-50

~
::0

...'"

f CLK =20kHz

Vs=:l:5V

"'

-2000

\'r~1!...

l~

-3000

!21-4000

\

:>:

D.

CASCADED~ 1\

\ \

-60
-70

~

-80
10

100

r\
\

1000

-5000

-7000

\

-8000

5000

FREQUENCY (Hz)

\
\
~

-6000

\

\

Vs =:1: 5V
fCLK ,= 20 kHz _

o

........

-

2

3



...
t:

Do

!I

1

IS
2

t
-.!!..+ I

t
IS

-.!!.. -I

2

2

FREQUENCY

1

Is
2

t
-.!!.. +1

Is

2

FREQUENCY
TL/H/l0557-22

TLlH/l0557-23

(a) Input Signal Spectrum

(b)Output Signal Spectrum. Note that the Input signal at
fs/2 + f causes an output signal to appear at fs/2 - f.

FIGURE 11. The phenomenon of aliasing In sampled-data systems. An input signal whose
frequency is greater than one-half the sampling frequency will cause an output to appear
at a frequency lower than one-half the sampling frequency. In the LMF40, fs = fCLK'

7-18

I!J1National Semiconductor

LMF60 High Performance
6th-Order Switched Capacitor
Butterworth Lowpass Filter
General Description

Features

The LMF60 is a high performance, precision, 6th-order Butterworth lowpass active filter. It is fabricated using National's LMCMOS process, an improved silicon-gate CMOS process specifically designed for analog products. Switchedcapacitor techniques eliminate external component requirements and allow a clock-tunable cutoff frequency. The ratio
of the clock frequency to the low-pass cutoff frequency is
internally set to 50: 1 (LMF60-50) or 100: 1 (LMF60-100). A
Schmitt trigger clock input stage allows two clocking options, either self-clocking (via an external resistor and capacitor) for stand-alone applications, or for tighter cutoff frequency control, a TTL or CMOS logic compatible clock can
be directly applied. The maximally flat passband frequency
response together with a DC gain of 1V IV allows cascading
LMF60 sections for higher-order filtering. In addition to the
filter, two independent CMOS op amps are included on the
die and are useful for any general signal conditioning applications. The LMF60 is pin- and functionally-compatible with
the MF6, but provides improved performance.

l1li

Cutoff frequency range of 0.1 Hz to 30 kHz

l1li Cutoff frequency accuracy of ± 1.0%, maximum
l1li Low offset voltage ±100 mV, maximum, ±5V supply
l1li Low clock feedthrough of 10 mVp _p, typical
l1li Dynamic range of

88 dB, typical

l1li Two uncommitted op amps available
l1li No external components required
l1li 14-pin DIP or 14-pin wide-body S.O. package
.. Single/Dual Supply Operation:
+4V to +14V (±2V to ±7V)
l1li Cutoff frequency set by external or internal clock
l1li Pin-compatible with the MF6

Applications
l1li Communication systems
l1li Audio filtering

II Anti-alias filtering
iii Data acquisition noise filtering
!!I Instrumentation
II High-order tracking filters

14

N.INn

Lh

OUT

Va,

CLKR
V-

AlNO

CLK

V·

L-----------~----------~-fIAl"D

INYZ
INVI

Va
fiLTER

IN

fiLTER

'los All

IN
TUH/9294-2

Top View
INV2

N.lNn

Order Number LMF60CMJ-50,
(5962-9096 701MCA or
LMF60CMJ50/883),
LMF60CMJ-100, or
(5962-9096 702MCA
or LMF60CMJ100/883)
See NS Package Number J14A

TUH/9294-'

Order Number LMF60CIWM-50
or LMF60CIWM-100
See NS Package Number M14B

cue

IN

CUI R

L.Sb

V+

v-

Order Number LMF60CIN-50
or LMF60CIN-100
See NS Package Number N14A

7-19

,.

Absolute Maximum Ratings (Note 1)
Soldering Information:
• N Package: 10 sec.
• J Package: 10 sec.
• SO Package: Vapor Phase (BO sec.)
Infrared (15 sec.) (Note B)

If MIlitary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V+ - V-) (Note 2)
15V
V+ + 0.2V
Voltage at Any Pin
V- - 0.2V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)
Storage Temperature
ESD Susceptibility (Note 5)
CLKIN Pin

2BO"C
300·C
215·C
220·C

Operating Ratings (Note 1)

5mA

Temperature Range
TMln S; TA S; TMax
LMFBOCIN-50, LMFBOCIN-100
LMFBOCIJ-50, LMFBOCIJ-100,
LMFBOCIWM-50,
-40"C S; TA S; + 85·C
LMFBOCIWM-100
LMFBOCMJ-50, LMFBOCMJ-100,
LMFBOCMJ50/883,
-55·C S; TA S; + 125·C
LMFBOCMJ100/883
Supply Voltage (V+ - V-)
4Vto 14V

20mA
500mW
-B5·Cto + 150"C
2000V
1700V

Filter Electrical Characteristics

The following specifications apply for fCLK = 500 kHz (Note 7) unless otherwise specified. Boldface limits apply for T A
= TMIN to TMAXi all other limits TA = TJ = 25·C.
Symbol
y+

=

Parameter

+SY, Y-

fCLK
Is

=

Typical
(Note 8)

Conditions

=

TJ

Limits
(Note 9)

Units
(Limits)

1.5

Hz (Min)
MHz (Max)

-SY

Clock Frequency Range
(Note 1B)

5

Total Supply Current
VIN

Ho

DC Gain

RSour~e

fCLK/fc

Clock to
Cutoff
Frequency
Ratio (Note 10)

OV

S;

Filter
Opamp

12.0

10
5

mA(Max)
mVp-p
mVp-p

/
/

0.10
-0.2B

2 kO

0.10
-0.30

dB (Max)
dB (Min)

LMFBO-50

49.00 ±0.8%

149.00 ± 1;0%

(Max)

LMFBO-100

98.10 ±0.8%

198.10 ± 1.0%

(Max)

Temperature Coefficient
offCLK/fc
AMIN

Stopband Attenuation

Vos

DC Offset
Voltage

VOUT

Output Voltage
Swing (Note 2)

Isc

Output Short Circuit
Current (Note 11)

4

ppmfOC
38

dB (Min)

±100
±150

mV(Max)
mV(Max)

At2 X fc

LMFSO-50
LMFBO-100
+3.9
-4.2
Source
Sink

Dynamic Range
(Note 12)
Additional
Magnitude
Response
Test Points
(Note 13)

1

7.0

=

Clock Feedthrough

LMFBO-50

fiN
fiN

LMFSO-100

fiN
fiN

= 12 kHz
= 9kHz
= 6kHz
= 4.5 kHz

7-20

1
I

+3.7
-4.0

V (Min)
V (Max)

90
2.2

mA
mA

88

dB
-9.45 ±0,46 . 1-9.45 ± 0.50

dB

-0.87 ±0.16

/-0.87 ±0.20

dB

-9.30 ±0.46

/-9.30 ±0.50

dB

-0.87 ±0.16

/-0.87 ±0.20

dB

Filter Electrical Characteristics (Continued)
The following specifications apply for fClK = 250 kHz (Note 7) unless otherwise specified. Boldface limits apply for TA
= TMINtoTMAX;all other limits TA = TJ = 25°C.
Symbol
V+

=

Parameter

+2.5V, V-

fClK
Is

=

Typical
(Note 8)

Conditions

=

TJ

Limits
(Note 9)

Units
(Limits)

750

Hz (Min)
kHz (Max)

-2.5V

Clock Frequency Range
(Note 16)

5

Total Supply Current

5.0

=

Clock Feedthrough
(Peak to Peak)

VIN

Ho

DC Gain (with
RSource s; 2 kn)

fClK

=

fClK
fClK/fc

Clock to
Cutoff
Frequency
Ratio
(Note 10)

fClK

=
=
=
=
=

LMF60-50

fClK
LMF60-100

fClK
fClK

Filter
Opamp

OV

AMIN

Stopband Attenuation
DC Offset
Voltage

VOUT

Output Voltage
Swing (Note 2)

Isc

Output Short Circuit
Current (Note 11)
Dynamic Range
(Note12)---Additional
Magnitude
Response
Test Points
(Note 13)

1
1

dB (Max)
dB (Min)

49.00 ±O.S%

149.00 ± 1.0%

(Max)

9S.10 ±O.S%

198.10 ± 1.0%

(Max)

-O.OS

500 kHz
250 kHz

dB

49.00 ±0.60/0

500 kHz
250 kHz

9S.10 ±0.60/0

500 kHz

4

ppmrc

At2 X fc

Rl

=

+1.4
-2.0

5kO

LMF60-50

---

fiN
fiN

LMF60-100

fiN
fiN

=
=
=
=

---

---

--

---

36

dB (Min)

±60
±90

mV(Max)
mV(Max)

1
1

+1.2
-1.8

42
0.9

Source
Sink
---

mA(Max)

0.10
-0.30

LMF60-50
LMF60-100

------

6.5

mV
mV
0.10
-0.26

250 kHz

Temperature Coefficient
offClK/fc

Vos

1

6
3

____ 8:1_~ __

V (Max)
V (Min)
mA
mA

--------~------------------

~-~dB-

6kHz

-9.45 ±0.46 1-9.45 ±0.50

dB

4.5 kHz

-0.S7 ±0.16 1-0.87 ±0.20

dB

3 kHz

-9.30 ±0.46 1-9.30 ±0.50

dB

2.25 kHz

-0.S7 ±0.16 1-0.87 ±0.20

dB

-----

•
7-21

Op Amp Electrical Characteristics
Boldface limits apply for TA =TJ = TMIN toTMAX; all other limits TA
Symbol

Parameter

== TJ = 2SoC.

Conditions

Typical
(Note 8)

Limits
(Note 9)

Units
(Limits)

±20

mV(Max)

V+ = +5V, V- = -5Y
Vas

Input Offset Voltage

IB

Input Bias Current

CMRR

Common Mode Rejection
Ratio (Op Amp # 2 Only)

Test Input Range =
-2.2Vto +1.SV

Va

Output Voltage Swing

RL = SkO

10

pA

55
3.S
-4.2

Source
Sink

I
I

dB

3.6

-4.0

90
2.1

V (Min)
V (Max)

Isc

Output Short Circuit
Current (Note 13)

mA
mA

SR

Slew Rate

4

V/)LS

AvaL

DC Open loop Gain

SO

dB (Min)

GBW

Gain Bandwidth Product

2.0

MHz

y+ = +2.5V, V- = -2.5V

±20

mV(Max)

Vas

Input Offset Voltage

IB

Input Bias Current

CMRR

Common Mode Rejection
Ratio (Op Amp #2 Only)

Test Input Range =
-0.9Vto +O.SV

Va

Output Voltage Swing

RL = SkO

Isc

Output Short Circuit
Current (Note 13)

SR

Slew Rate

3

V/)LS

AvaL

DC Open loop Gain

74

dB (Min)

GBW

Gain Bandwidth Product

2.0

MHz

10

pA

55

,
Source
, Sink

,

1.3
, -1.S

dB

1.1
-1.8

/
/

42
0.9

V (Min)
V (Max)
mA
mA

Logic Input-Output Characteristics
The following specifications apply for V- = OV (Note 15), LSh = OV unless otherwise specified. Boldface limits apply for TA
= TJ = TMIN to TMAX;all other limits TA = TJ = 2SoC.
Symbol

Parameter

Conditions

Typical
(Note 8)

Limits
(Note 9)

Units
(Limits)

2.0
0.8

V (Min)
V (Max)

TTL CLOCK INPUT, CLK R PIN (NOTE 14)
VIH
VIL

TTL Input
Voltage

logical "1"
logical "0"

V+ = +SV,V- = -SV

VIH
VIL

ClKR Input
Voltage

logical "1"
logical "0"

V+ = +2.SV, V- = -2.SV

2.0
0.6

Maximum leakage
Current at ClK R

2.0

7-22

/

0.4

V (Min)
V (Max)
)LA

Logic Input-Output Characteristics

(Continued)
The following specifications apply for V- = OV (Note 15), L.Sh = OV unless otherwise specified. Boldface limits apply for TA
= TJ = TMIN to TMAX; all other limits TA = TJ = 25'C.
Symbol

Parameter

Conditions

Typical

Limits

Units

(NoteS)

(Note 9)

(Limits)

I
I

6.0
8.9

V (Max)

I
I

2.9
4.4

V (Max)

I
I

1.3
3.9

V (Max)

I
I

0.8
2.0

V (Max)

I
I

2.1
7.6

V (Max)

I
I

0.9
3.8

V (Max)

I
I

9.0
4.5

V (Min)

I
I

1.0
0.5

V (Max)

I
I

3.7
1.2

rnA (Min)

I
I

3.7
1.2

rnA (Min)

SCHMITT TRIGGER
VT+

Positive Going Input

V+ = 10V

6.1

Threshold Voltage

8.8
V+ = 5V

3.0
4.3

VT-

Negative Going Input

V+ = 10V

1.4

Threshold Voltage

3.8
V+ = 5V

0.7
1.9

VT+ -VT-

Hysteresis

V+ = 10V

2.3
7.4

V+ = 5V

1.1
3.6

VOH

Logical "1" Voltage

10= -10~A,Pin11
VOL

Logical "0" Voltage

10 = -10 ~A, Pin 11
ISOURCE

Output Source
Current, Pin 11

ISINK

Output Sink
Current, Pin 11

V+ = +10V
V+ = +5V

4.6

V+ = +10V
V+ = +5V

0.4

CLKRtoVV+ = +10V

4.9

V+ = +5V

1.6

9.1

0.9

V (Min)

V (Min)

V (Min)

V (Min)

V (Min)

V (Min)

V (Min)

V (Max)

rnA (Min)

CLKRtoV+
V+ = +10V

4.9

V+ = +5V

1.6

rnA (Min)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. Specified Electrical Characteristics do not apply when operating the device outside its specified conditions.
Note-2:-AII-voltages-are measured-with respect to-AGND,-unles..-otherwlse-speclfled~--- - - - - - - - - - - - - - - - - - ----- - ---- ------- --- - - - - - - - - Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V- or VIN > V+) the absolute value of current at that pin should be limited
to S mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with S rnA to four.
Note 4: The Maximum power dissipation must be derated at elevated temperat~res and is dictated by TJ Max. 8JA, and the ambient temperature TAo The maximum
allowable power dissipation is PD ~ (TJ Max - TAl/9JA or the number given in the absolute ratings, whichever is lower. For this device, TJ Max ~ 12S'C, and the
typical junction-to·ambient thermal resistance of the LMF60CCN when board mounted Is 67·C/W. For the LMF60CIJ this number decreases to 6'Z'C/W. For the
LMF60CIWM, BJA ~ 7S·C/W.

Note 5: Human body model: 100 pF discharged through a 1.S kfl resistor.
Note 6: See AN450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section tilled "Surface Mount" found in any current Linear Databook
for other methods of soldering surface mount devices.
Note 7: The specifications given are for a clock frequency (feuo of SOO kHz at +SV and 250 kHz at ±2.SV. Above this frequency, the cutoff frequency begins to
deviate from the specified error band over the temperature range but the filter still maintains its amplitude characteristics. See application hints.
Note 8: Typlcals are at 2S'C and represent the most likely parametric norm.
Note 9: Guaranteed to National's Average OutgOing Quality Level (AOQl).
Note 10: The cutoff frequency of the filter is defined as the frequency whera the magnitude response is 3.01 dB lass than the DC gain of tha filter.
Note 11: The short circuit source current is measured by forcing the output to its maximum positive swing and then shorting that output to the nagative supply. The
short circuit sink current is measured by forCing the output being tested to its maximum negative voltage and then shorting that output to the positive supply. These
are worst case conditions.
Note 12: For ±SV supplies the dynamic range is referenced to 2.62 Vnns (3.7V peak), where the wideband noise over a 20 kHz bandwidth is typically 100 ",V. For
±2.5V supplies the dynamic range is referenced to 0.849 Vrms (1.2V peak), where the wideband noise over a 20 kHz bandwidth is typically 75 "'Vnn•.
Note 13: The filter's magnitude response is tested at the cutoff frequency, fe, at fiN

~

2 fe, and at tihese two additional frequencies.

Note 14: The LMF60 is operated with symmetrical supplies and L.Sh is tied to GND.
Note 15: For simplicity all the logiC levels (except for the TTL input logic levels) have been referenced to Vand ± 2.SV supplies.

~

OV. The logic levels will scale accordingly for ±SV

Note 16: The nominal ratio of the clock frequency to the low-pass cutoff frequency is internally set to SO·to·l (LMF60-50) or 100·to-l (LMF60-100).

7-23

-

C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

~

::iii

Typical Performance Characteristics

...I

fCLK/fC Deviation
vs Power Supply Voltage

fCLK/fC Deviation
vs Temperature
Il2D

0.10

+5
LMF60-50

0.10

.... ~

-

~~~5~0
I

4

10

12

r-I f~ = 5100 klHZ
-o.21J

-55

14

-15

-

LMF60-100
~LJ!=500kHZ-

AI~"CI

I

I

-0.15
4

10,

III +1

~

It

I

1

1

1
65

1

I

-s
105

o

I

l
ill

...

po
====

",

' -15

65

"""~ ....

~

I

+1

105

o

2D

2.5

0.2

.....

Vs=IOV

-

vs=~ '\
-15

25

65

TEMPERATURE (CC)

105

I~I

V =IOV'

~:Vs=5V- -

-ILM~60i5~

-1.8

-0.3

N. '

1\
- rA,:,25"C

-0.25

-55

,
,~

lJotF60-50
'ax= 500 kHz

14

•.5

DC Gain Deviation
vs Clock Frequency

I

POWER SUPPLY VOLTAGE (V)

o.s

I
I
I
•.0

DC Gain Deviation
vs Temperature

.......

12

H-Js;;;~ .... ."JIII

CLOCK FREQUENCY (MHz)

I-

lJotF60-50
TA=25"C
!CLjC= 500 kHz

I

1:>00

TEMPERATURE (CC)

0.1

,

~

-s
25

,

1 - - vs,=..!..f

-3

1 1
-55

2.5

2D

lJotF60-100

.. -1 1 - -

I!Vsn

-1l2D

•.5

+3

~

14

1.0

fCLK/fC Deviation
vs Clock Frequency
+5

V 1=l
sl

-0.10

o.s

CLOCK FREQUENCY (MHz)

,I

0.10

DC Gain Deviation
vs Power Supply Voltage

10

j

LMF60-50
TA =25"C

LMF60-100
!cue = 500 kHz

I-

12

Vs=IOV-

1"'" .....

-1

fCLKIfC Deviation
vs Temperature

POWER SUPPLY VOLTAGE (V)

o.os

25

Il2D

1/
-0.10

t;;;

r---r- -~s15v:

TEMPERATURE (CC)

fCLK/fC"Devlatlon
vs Power Supply Voltage

I.;'

+3

-0.10

0.10

....

1

Vs=IOV

-

POWER SUPPLY VOLTAGE, (V)

....

1

H-+-

~ i-""

I

o.os

1

~.L

I fiirfoorHZI-

-0.15

1

Vsl=5J-

".

-0.10

fCLK/fC Deviation
vs Clock Frequency

o

o.s

1.0

II

I

1.5

2D

2.5

CLOCK FREQUENCY (MHz)
TL/H/9294-3

7-24

r-----------------------------------------------------------------------------, i:
r
Typical Performance Characteristics

;R

(Continued)

o

DC Gain Deviation
vs Power Supply Voltage

DC Gain Deviation
va Temperature

DC Gain Deviation
va Clock Frequency

0.I

CI.05

G.2

VS=IOV

-

14

1.;""""

1-1-

1 -' ~

10

12

60

ss

fax

I'

"" ""

'\

"10

12
POWER SUPPLY VOLTAGE (V)

I'
14

o

D.5

1.0
1.5
2.D
a.OCl( FlIEQUENCY (MHz)

2.5

8.D

~

I

I
I I

Power Supply Current
va Temperature
7])

TA=25OC
= 500 kHz

..... 1'-00

f~=5OOkHz

105

Power Supply Current
va Power Supply Voltage

5.D

1'-00

-1.8

-15
25
65
TEMPERATURE (OC)

-55

14

DC OHset Voltage Deviation
vs Power Supply Voltage

1\

Vs =5V ....

fF~5~k~

POWER SUPPLY VOLTAGE (V)

4

1\
1\
L..\

LIIF60-loo

f-~s=~V

0060-100
-0.3

I

, ....

F60-loo

~;::kHZ

-60

~

vsl=ll

~

"

Positive Voltage Swing
vs Power Supply Voltage

10

12
POWER SUPPLY VOLTAGE (V)

14

V

...f-r

I--"

S =1 5V

2.D
-55

Negative .Voltage Swing
va Power Supply Voltage

VS=IOV

--r

"""

10
4

r-lax Lsol. kJz

-15
25
65
TEMPERATURE (OC)

105

Positive Voltage Swing
va Temperature

I
RL=5k

Vs-!.IJ-

II
II
II =1500kHz
i l I I- hV~2~

I

l.o~~~~~~~~~

4

10

12

POWER SUPPLY VOLTAGE (V)

14

~.o~~~~~~~~~

4

10

12

POWER SUPPLY VOLTAGE (V)

14

1 I

I])

-55

-15
25
65
TEMPERATURE (OC)

105
TLfHf9294-4

•
7·25

Typical Performance Characteristics
Negative Voltage Swing
va Temperature
-2.0

CLK R Trigger Threahold
va Power Supply Voltage

Schmitt Trigger Threshold
vs Power Supply Voltage
10.0

2.5

I I

I I

1

VS~5V

II

TA =-55"1

II
II

RL =5V
fcue = 1500 lHZ .
J I _L

I

1
65

[.0"

I'" 1--:[;0"
....... 1--:: ,,;...-~
~f..-"

1
105

o.s

lEIIPERATURE(OC)

10
12
POWER SUPPlY VOLTAGE M

Crosstalk from Filter
toOpAmps

lD'

~

~

~

o

11111111111

-20

lD'

-40

~

-60

~

.-60

§ -eo

~

i""

-100

...

I;'

.......

....!-1'""
.
1
fcue = 500 kHz

68101214
POWER SUPPlY VOLTAGEM

'[~I

-eo

r-

-100

-120

14

I......

Crosstalk from Either
Op Amp to Filter

-20

T~~~5~

-40

VT2.0

fCljC = 500 kHz

4

,

~

ITAj'2jOCI-

,

TA=25OC

V~+

....... c.,... [.0";"-

TA=25OC

Vs=IOV

1 1
-15
25

8.D

>"":;"'-

I
-55

(Continued)

-120

10

100

Ik

10k

10

lOOk

100

FIlEOUEHCY (Hz)

Ik

10k

lOOk

FREOUEHCY (Hz)

Equivalent Input Noise
Voltage of Op Amps

IJIJ

240

I'o

10

100

Ik

10k

lOOk

FIlEQUEHCY (Hz)
TLlH/9294-5

7-26

Crosstalk Test Circuits
From Filter to Op-Amps

20Hz-20kHz
IVRWS

TLlH/9294-6

From Either Op-Amp to Filter Output

20Hz-20kHz ""

IVRWS

TLlH/9294-7

Pin Description

(Pin Numbers)
Description
Pin
Description
The output of the lowpass filter will typielK IN (9)
A CMOS Schmitt-trigger input to be
cally swing to within 1V of each supply
used with an external CMOS logic level
rail.
clock. Also used for self-clocking
FILTER IN (8)
The input to the lowpass filter. To miniSchmitt-trigger oscillator (See Section
mize gain errors the source impedance
1.1).
__________ that dri~s 11'1i~ lI1PJlljIl'1ouldll~I!~~JI'1!l-rL. ___QI,.I< BJl1)_____JLTIL.IQgiQ-.lll.l1elJ;lQciLlI'1pulwhen in_
2k (See Section 1.4). For single supply
split supply operation (± 2V to ± 7V) and
operation the input signal must be biL. Sh tied to system ground. This pin beased to mid-supply or AC coupled.
. comes a low impedance output when
VOsADJ (7)
This pin is used to adjust the DC offset
L.Sh is tied to V-. Also used in conjunction with the ClK IN pin for self clocking
of the filter output; if not used it must be
tied to the AGND potential. (See Section
Schmitt-trigger oscillator (See Section
1.3)
1.1).
L.Sh (12)
level shift pin, selects the logic threshAGND(5)
The analog ground pin. This pin sets the
old levels for the desired clock. When
DC bias level for the filter section and
tied to V- it enables an internal TRIthe non inverting input of Op-Amp # 1
STATE® buffer stage between the
and must be tied to the system ground
Schmitt trigger and the internal clock
for split supply operation or to mid-suplevel shift stage thus enabling the ClK
ply for single supply operation (See SecIN Schmitt-trigger input and making the
tion 1.2). When tied to mid-supply this
ClK R pin a low impedance output.
pin should be well bypassed.
When the voltage level at this input exVOl is the output and INV1 is the invertVOl (4),
ceeds [25% (V+ - V-) + V-I the inINV1 (13)
ing input of Op-Amp # 1. The non-invertternal TRI-STATE® buffer is disabled aling input of this Op-Amp is internally
lowing the ClK R pin to become the
connected to the AGND pin.
clock
input for the internal clock level
V02 is the output, INV2 is the inverting
V02(2),
shift stage. The ClK R threshold level is
input, and NINV2 is the non-inverting inINV2 (14),
now 2V above the voltage applied to the
NINV2 (1)
put of Op-Amp # 2.
l.Sh pin. Driving the ClK R pin with TTL
V+ (6), V- (10)
The positive and negative supply pins.
logic levels can be accomplished
The total power supply range is 4V to
through the use of split supplies and by
14V. Decoupling these pins with 0.1 fJ.F
tying the l.Sh pin to system ground.
capacitors is highly recommended.
Pin
FilTER OUT (3)

7-27

•

1.0 LMF60 Application Hints
'frequency is dependent on the buffer's threshold levels as
well as on the resistor/capacitor tolerance (See Figurs 1).

The LMF60 is comprised of a non-inverting unity gain lowpass sixth-order Butterworth switched capacitor filter section and two undedicated CMOS Op-Amps. The switchedcapaCitor topology makes the cutoff frequency (where the
gain drops 3.01 dB below the DC gain) a direct ratio (100:1
or 50:1) of the clock frequency supplied to the lowpass filter.
Internal integrator time constants set the filter's cutoff frequency. The resistive element of these integrators is actually a capacitor which is "switched" at the clock frequency
(for a detailed discussion see Input Impedance section).
Varying the clock frequency changes the value of this resistive element and thus the time constant of the integrators.
The clock to' cutoff frequency ratio (fClK/fc) is set by the
ratio of the input and feedback capacitors in the integrators.
The higher the clock to cutoff frequency ratio (or the sampling rate) the closer the approximation is to the theoretical
Butterworth response. The LMF60 is available in fClK/fc
ratios of 50:1 (LMF60-50) or 100:1 (LMF60-100).

Schmitt-trigger threshold voltage levels can vary significantly causing the R/C oscillator's frequency to vary greatly
from part to part.
Where accuracy in fc is required an external clock can be
used to drive the CLK R input of the LMF60. This input is
TTL logic level compatible and also presents a very light
load to the external clock source (- 2 p.A) with split supplies and L.Sh tied to system ground. The logic level is programmed by the voltage applied to level shift (L.Sh) pin (See
the Pin Description for L.Sh pin).
1_2 POWER SUPPLY BIASING
The LMF60 can be biased from a single supply or dual split
, supplies. The split s\lpply mode shown in Figures 2 and 3 is
the most flexible and easiest to implement. As discussed
earlier split supplies, '± 2V to ± 7V, will enable the use of
TTL or CMOS clock logic levels. Figure 4 shows two
schemes for single supply biasing. In this mode only CMOS
clock logic levels can,be used.

1.1 CLOCK INPUTS
The LMF60 has a Schmitt-trigger inverting buffer which can
be used to construct a simple R/C oscillator. The oscillator

= RC In[ (Vee -

1

VT-) VT+
Vee - VT+ VTTypically lor Vee = V+ - V- = 10V:
IClK

1
IClK = 1.37 RC

LNF60
TL/H/9294-8

FIGURE 1_ Schmitt Trigger RIC Oscillator

,:'1

7-28

1.0 LMF60 Application Hints (Continued)
If the LMFSO-50 or the LMFSO-l00 were set up for a cutoff
frequency of 10kHz the input impedance would be:
1 x 1010
R'N = 10kHz = 1 Mn

cies these leakage currents can cause millivolts of error, for
example:
fCLK = 100 Hz, ILEAKAGE = 1 pA, C = 1 pF

The propagation delay in the logic and the settling time required to acquire a new voltage level on the capacitors increases as the LMFSO power supply voltage decreases.
This causes a shift in the fCLK/fc ratio which will become
noticeable when the clock frequency exceeds 500 kHz. The
amplitude characteristic will stay within tolerance until fCLK
exceeds 750 kHz and will peak at about 0.4 dB at the cutoff
frequency with a 2 MHz clock. The response of the LMFSO
is still a reasonable approximation of the ideal Butterworth
lowpass characteristic as can be seen in Figure 7.

1 Mn
Av = 10 kn + 1 Mn = 0.99009 (-8S.4 mdB)
Since the maximum overall gain error for the LMFSO is + 0.1
dB, - 0.3 dB with a Rs :;;: 2 kn the actual gain error for this
case would be +0.21 dB to -0.39 dB.
1.5 CUTOFF FREQUENCY RANGE
The filter's cutoff frequency (fel has a lower limit caused by
leakage currents through the internal switches discharging
the stored charge on the capacitors. At lower clock frequen-

10

0

-10

-10

-20
-30

E

-.ul

'"-c

-50

5...
...'"

~

...c

...

....I

,,,

10

0
'Iii'

'Iii'

1 pA
1 pF (100 Hz) =10 mV

v=

In this example with a source impedance of 10k the overall
gain, if the LMFSO had an ideal gain of 1 (0 dB) would be:

-20
-30

~

:!l

-EO

~s

~

~

'i \

-.ul

-50

'\

\

~

\ ~i

~

~\.

-EO

-70

-70

-EO

-Ill
10

\

\

50

10

,i

\

5IXl

sac

SIc

100
lk
10k lOOk
FREQUENCY (Hz)

5IXlk
1M

TLlH/9294-17

TL/H/9294-1B

FIGURE 7a. LMF60-100 ± SV Supplies
~~~ _______ ~mplltud~R~sJl()l1s~~____ ~_~_

10
0

~

-10
'Iii'
c

-20
-30 r--

I:

-.ul

...
...-c

~

=>

....I

'"

r--

-50

\

\

FIGURE~7b.LMF60-S0

Amplitude Response - -- ~

0
-10
'Iii'

~
\

c\,~~\ ,\

~

...c
E
...
...'"
....I

\
1\ \

-EO

-70
10

50

100

J

SIc
sac 500<
lk
lac
100<
1M
FREQUENCY (Hz)

-30

t

~

it

-50
-EO

~:\

1

i-

,\

1\

10

TL/H/9294-19

\

~ r-~c> r-~ \~ ~-

-40 ~

-Ill

5IXl

\

~

-20

-70

\r\,

-Ill

,

10

~~I
~
\ ,fi-

\\ i \\ , i

± SV Supplies

50

100

SIc
sac 500<
lk
10k 100<
1M
FREQUENCY (Hz)

5IXl

TL/H/9294-20

FIGURE 7e. LMF60-100 ± 2.SV Supplies
Amplitude Response

FIGURE 7d. LMF60-S0 ± 2.SV Supplies
Amplitude Response

7-29

,.

1.0 LMF60 Application Hints (Continued)
NJNV2

1

14

INV2

13

INVI
l.Sh

12
11
10

N.INV2
V02

ClKIN

FILlER
IN

_

14
13

FilTER OUT
Vo
AGND

CLKR

V"

1
2

-S.OV

+5.0V

JlfL +SV
-SV

INV2

12

y+

9

VosADJ
O.I/,F

_

Tl/H/9294-9

FIGURE 2. Dual Supply Operation LMF60 Driven with
CMOS Logic Level Clock (VIH;;' V+ - 0.3 Vs and
VIL ~ V- + 0.3 Vs where Vs = V+ .- V-)

O.lp~

TLlH/9294-10

FIGURE 3. Dual Supply Operation
LMF60 Driven with TTL Logic Level Clock

LMF60

OV-Pc;-

>---1

J1IlSV
OV
-S.OV

11
10

.10V
3
10kll

FILTER

OUT

O.II'F

CMOS
CLOCK
LEVELS

Tl/H/9294-11

a) Resistor Biasing of AGND

lMF60

3 FilTER

our

O.I/,F

Tl/H/9294-12

b) Using Op-Amp 2 to Buffer AGND
FIGURE 4. Single Supply Operation
7-30

1.0 LMF60 Application Hints (Continued)
2Dkll

5kll

2Dkll

v-~v+

FilTER
OUT

FILTER
IN

3

LNF6D

(a)
Tl/H/9294-13

(b)
Tl/H/9294-14

FIGURE 5. Ves Adjust Schemes

1.3 OFFSET ADJUST
The VosADJ pin is used in adjusting the output offset level
of the filter section. If this pin is not used it must be tied to
the analog ground (AGND) level, either mid-supply for single
ended supply operation or ground for split supply operation.
This pin sets the zero reference for the output of the filter.
The implementation of this pin can be seen in Figure 5. In
5(a) DC offset is adjusted using a potentiometer; in 5(b) the
Op-Amp integrator circuit keeps the average DC output level at AGND. The circuit in 5(b) is therefore appropriate only
for AC-coupled signals and signals biased at AGND.
1.4 INPUT IMPEDANCE
The LMF60 lowpass filter input (FILTER IN pin) is not a high
impedance buffer input. This input is a switched capacitor
resistor equivalent, and its effective impedance is inversely
-proportlOnalto the clockfrequency.ine eqwvaI8mclrcuifor
the input to the filter can be seen in Figure 6. The input
capacitor charges to the input voltage (VIN) during one half
of the clock period, during the second half the charge is
transferred to the feedback capacitor. The total transfer of
charge in one clock cycle is therefore a = CINVIN, and
since current is defined as the flow of charge per unit time
the average input current becomes
liN = a/T

The equivalent input resistor (RIN) then can be defined as
1
RIN = VIN/IIN = - - CINfcLK
The input capacitor is 2 pF for the LMF60-50 and 1 pF for
the LMF60-100, so for the LMF60-100
1 X 1012
1 X 1012
1 X 1010
RIN = - - - = - - - = - - fCLK
fc X 100
fc
and
5 X 1011
5 X 1011
1 X 1010
RIN = - - - = - - - = - - fCLK
fc X 50
fc
for the LMF60-50. As shown in the above equations, for a
given cutoff frequency (fc) the input impedance remains the
same for the LMF60-50 and the LMF60-100. The higher the
clock to cutoff frequency ratio, the greater equivalent input
-- -- -resiSfancEHoragiven-clock frequency:-ASllfecutott-fre~- quency increases the equivalent input impedance decreases. This input resistance will form a voltage divider with the
source impedance (RSOURCE). Since RIN is inversely proportional to the cutoff frequency, operation at higher cutoff
frequencies will be more likely to load the input signal which
would appear as an overall decrease in gain at the output of
the filter. Since the filter's ideal gain is unity, its overall gain
is given by:

(where T equals one clock period) or
.
CINVIN
liN = - T - = CINVINfCLK

FllTER~
INPUT

R
IN

-

AV =

I

+ RSOURCE

NON-OVERLAPPING
a.OCKS

~n ij~~

__ _

+

:

RIN

RIN

~~--.

AGND
TLlH/9294-15

IH- elN, ClK

a) Equivalent Circuit for LMF60 Filter Input

I

AGND

:
TUH/9294-16

b) Actual Circuit for LMF60 Filter Input
FIGURE 6. LMF60 Filter Input

7-31

•

2.0 Designing with the LMF60
Given any lowpass filter specification, two equations will
come in handy in trying to determine whether the LMF60 will
do the job. The first equation determines the order of the
lowpass filter required:
log (100.1AMin - 1) - log(100.1AMax - 1)
n=
2 log (fs/fb)
(1)

To implement this example for the LMF60-50 the clock frequency will have to be set to fCLK = 50(1.119 kHz) =
55.95 kHz or for the LMF60-100 fCLK = 100(1.119 kHz) =
111.9 kHz
2.2 CASCADING LMF60s
In the case where a steeper stopband attenuation rate is
required two LMF60's can be cascaded (Rgure 9) yielding a
12th order slope of 72 dB per octave. Because the LMF60
is a Butterworth filter and therefore has no ripple in its passband, when LMF60's are cascaded the resulting filter also
has no ripple in its passband. Likewise the DC and passband gains will remain at 1VIV. The resulting response is
shown in Figure 10.

where n is the order of the filter, AMin is the minimum stopband attenuation (in dB) desired at frequency fs, and AMax is
the passband ripple or attenuation (in dB) at frequency fb. If
the result of this equation is greater than 6, then more than
a single LMF60 is required.
The attenuation at any frequency can be found by the following equation:
(2)
Attn(!) = 10 10g[1 + (100.1AMax - 1) (f/fb)2n]dB

In determining whether the cascaded LMF60's will yield a
filter that will meet a particular amplitude response specification, as above, equations 3 and 4 can be used, shown
below.
log (100.05 Amin - 1) - log(100.05AMax - 1)
n=
2 log (fs/fb)
(3)

where n = 6 (the order of the filter).
2.1 A LOWPASS DESIGN EXAMPLE
Suppose the amplitude response specification in Figure 8 is
given. Can the LMF60 be used? The order of the Butterworth approximation will have to be determined using eq. 1:
AMin

Attn(!) = 10 10g[1

= 30 dB, AMax = 1.0 dB, fs = 2 kHz, and fb = 1 kHz
n

=

10g(103 '- 1) - log(100.1 - 1)
2 log(2)

= 5.96

1) (f/fb)2n] dB

(4)

Equation 3 will determine whether the order of the filter is
adequate (n ,;;: 6) while equation 4 can determine if the
required stopband attenuation is met and what actual cutoff
frequency (fe) is required to obtain the particular frequency
response desired. The design procedure would be identical
to the one shown in Section 2.1.

Since n can only take on integer values, n = 6. Therefore
the LMF60 can be used. In general, if n is 6 or less a single
LMF60 stage can be utilized.
Likewise, the attenuation at fs can be found using equation
2 with the above values and n = 6 giving:
Alten (2 kHz) = 10 log [1 + (100,1 - 1) (2/1)12]

2.S IMPLEMENTING A "NOTCH" FILTER WITH THE
LMF60
A "notch" filter with 60 dB of attenuation can be obtained by
using one of the Op-Amps available in the LMF60 and three
external resistors. The circuit and amplitude response are
shown in Figure ".
The frequency where the "notch" will occur is equal to the
frequency at which the output signal of the LMF60 will have
the same magnitude but be 180 degrees out of phase with
its input signal. For a sixth order Butterworth filter 180·
phase shift occurs where f = fn = 0.742 fc. The attenuation at this frequency is 0.12 dB which must be compensated for by making R1 = 1.014 X R2.
Since R1 does not equal R2 there will be a gain inequality
above and below the notch frequency. At frequencies below
f n), the signal through the filter
the notch frequency (f
has a gain of one and is non-inverting. Summing this with
the input signal through the Op-Amp yields an overall gain
of two or + 6 dB. For f :> fn, the signal at the output of the
filter is greatly attenuated thus only the input signal will appear at the output of the Op-Amp. With R3 = R1 = 1.014
R2 the overall gain is 0.986 or - 0.12 dB at frequencies
above the notch.

= 30.26 dB
This result also meets the design specification given in Figure 8 again verifying that a Single LMF60 section will be
adequate.

~MAX=-~~~~~~

L~ -------------l"""
fb= Ik

+ (100.05AMax -

where n = 6 (the order of each filter).

«

f,=2k

FREQUENCY (Hz)
Tl/H/9294-21

FIGURE 8. Design Example Magnitude Response
Specification Where the Response of the Filter Design
Must Fall Within the Shaded Area of the Specification
Since the LMF60's cutoff freqency fc, which corresponds to
a gain attenuation of -3.01 dB, was not specified in this
example it needs to be calculated. Solving equation 2 where
f = fc as follows:
[100.1(3.01 dB) - 1)]1/(2n)
_
fe - fb (1 00' 1AMax _ 1)
= 1 (100.301 - 1 )1/12

100.1 - 1
= 1.119kHz

where fc = fCLK/50 or fCLK/1 00.

7-32

,-----------------------------------------------------------------------------, r

s:

2.0 Designing with the LMF60 (Continued)

;;R
Q

LMF60

...

... 8

~

FILTER
IN

LMF60

OUT
VOSADJ AGND

5

7

y+

LSh
12

If"

6

FIlTER
OUT

IN
VosADJ AGND

CLKR

10

-4J

... 8
3 ...
....
ru
FIlTER FIlTER

7

11

~

O. IPF

v+=+SV

5

LSh
J12

y+
6

CLKR
10

11

=F
O.lpF::

1f"=-SVo---------------~--~-----------------4----------~

f~K>-----------------~~------------------------------~~

m

LOGIC LEVELS
TLlH/9294-22

FIGURE 9. Cascading Two LMF60s

10

Vs:.r-If"= lOY

0
-10

'CD'
::2-

...
Q

E

-'
Q.

::E

<

\\

-20
-3D

J
\ 1\

,,

-«l

-60

-60
--~~--- -----0000.
0.1

~~di·

\ \ .... LMF60

-50

-70

fCLlC=SOkHz

~

1\

TWO LMF60s-+

II ""

1\
5

10

FREQUENCY (kHz)
TUH/9294-23

FIGURE 10b. Phase Response
of Two Cascaded LMF60·50s

FIGURE 10a. One LMF60·50 vs.
Two LMF60·50s Cascaded

•
7-33

2.0 Designing with the LMF60 (Continued)
VOSADJ

7

LMF60

1---4-(

R3

~~S CLK

R2

Rl

s:~rui ~""------+'~'N~O~TC~H~"----..1
FILTER OUTPUT
TL/H/9294-25

FIGURE 118. "Notch" Filter
+10
0
ai'

-10

E
....
"-

-211

;2.

...c

...
::E

-30
-.lO

-50

10

50

100

FREQUENCY (Hz)

500

lK
TLlH/9294-26

FIGURE 11b. LMF60·S0 "Notch" Filter Amplitude Response

7·34

2.0 Designing with the LMF60 (Continued)
2.4 CHANGING CLOCK FREQUENCY

component will be "reflected" about fCLK/2 into the frequency range belowfcLK/2 as in Figure 14b. If this component is within the passband of the filter and of large enough
amplitude it can cause problems. Therefore if frequency
components in the input signal exceed fCLK/2 they must be
attenuated before being applied to the LMF60 input. The
necessary amount of attenuation will vary depending on
system requirements. In critical applications the signal components above fCLK/2 will have to be attenuated at least to
the filter's residual noise level. An example circuit is shown
in Figure 15 using one of the uncommitted Op-Amps available in the LMF60.

IN~TANTANEOUSLY

The LMF60 will respond well to a sudden change in clock
frequency. Distortion in the output signal occurs at the transition of the clock frequency and lasts approximately three
cutoff frequency (fc) cycles. As shown in Figure 12, if the
control signal is low the LMF60-50 has a 100 kHz clock
making fC = 2 kHz; when this signal goes high the clock
frequency changes to 50 kHz yielding 1 kHz fc.
The transient response of the LMF60 seen in Figure 13 is
also dependent on the fe and thus the fCLK applied to the
filter. The LMF60 responds as a classical sixth order Butterworth lowpass filter.

TL/H/9294-28

TL/H/9294-27

FIGURE 13. LMF60-50 Step Input Response,
Vertical = 2VIDlv., Horizontal =
1 ms/Div., fCLK = 100 kHz

fiN - 1.5 kHz (Scope TIme Base - 2 ms/Div)

FIGURE 12. LMF60-50 Abrupt Clock Frequency Change

2.5 ALIASING CONSIDERATIONS
Aliasing effects have to be taken into consideration when
input Signal frequencies exceed half the sampling rate. For
!h~_LMF~O._ this..@.Ql!.al~halC tbEL !1! V+), the current at that pin should be limited to 5 mAo The 20 mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 rnA to four.

•
7-43

Typical Performance Characteristics
Notch Depth vs
Clock Frequency

Notch Depth vs
Supply Voltage

E~~~~~mr-n~rn

!

J

40

Notch Depth
vs Temperature
~rnrn"OTTTTr~~m

~rr.~~rT~-rrT'"

I-t-HttfIIt-t:~~++
60
100

1000

,-55 -35 -15 5 25 45 65 85 105 125

10000

CLOCK FREQUENCY (kHz)

SUPPLY VOLTAGE (tV)

Power Supply Current
vs Power Supply Voltage

Power Supply Current
vs Temperature

2.5

10"

If

II

1

2.4

!ii

2.2

.

i
L...L...L...J.....L..L...L...L...J.....L..I....L..J,...J...J

I

6

2.8

I
~

~

6O~+1~~~~~++1

7D

H-+vt:6I"'1-+HT~=--,25i=r"1

60

80

60 Ir:O=R=GND

10

100

11111
11111 II
w=v+,o=GND,R=v-III'1 I

0.5

11111 II
TA=25OC
Vs-t5V

W= ,O=GND,
R= ,..,.=5OOkHz
W=O = R=GNO~f~ =12~Olk~H

W-D=R-GNO

~gl
~
=O=V-,R=VO,Icu<=IB7kHz

111111

~

AMBIENT TEMPERATURE (OC)

Passband Width vs
Temperature
0.6 rn-;-rOTTTTrTT"rnrn,

10000

Passband Width vs
Clock Frequency
0.6

.....,.,..

1000

CLOa< FREQUENCY (kHz)

Vs=t.V

-55 -35 -15 5 25 45 65 85 105 125

i

100

~

40

SUPPLY VOLTAGE (tV)

W= v+,O=GNO,R'~'V-

40 W=O=V-,R=v+

eo

50

i

!:l

Offset Voltage vs
Temperature
90

Passband Width vs
Supply Voltage

1~

AMBIENT TEMPERATURE (OC)

100

1

140 -

III

-55 -35 -15 5 25 45 65 85 105 125

l~rT~w~=~,y+~,D~=~G~NO~R~=~V-=-~

o~~_=~=_r~,--,=~,~ax~'=_"~.'IKm~

]:
§!

1.8

l00rt~rClJ(T=,'~-r+;Z--B~-r+;

40

CIJ(=

2.0

Offset Voltage vs
Supply Voltage

~O;R=GNOz

1110 TA=25OC
160 Vs=t5V

1!e U

2.8

POWER SUPPLY VOLTAGE (tV)

eo

Offset Voltage VB
Clock Frequency

30

I I I I I I
ITA =25OCI I
fClJ( =500 kHz

2.0

TEMPERATURE (OC)

W=D=V-,R=v+
0.1
1

100

1000

10000

CLOCK FREQUENCY (kHz)

Stopband Width VB
Clock Frequency
o.os~~~&-~H*~++~

w=v+, 0= GND, R=V::IHh:-Hf+HIHfI
OA
OA

1+I-H-H-++++-++H-1m1

0.(14 ~1-H~&-++'*TUL=:¥"o!rH-ififl

H-t-+-I++++++-+++-l

~

D.2 rt-lw-=l-o+=V--I--,RI-=+v+-:I,-fClJ(rt=-+'-67I-k+-l
Hz

0.1

0.1

ffi:l:mmmr:rnrrJ

-55 -35 -15 5 25 45 65 85 105 125

1
SUPPLY VOLTAGE (tV)

AMBIENT TEMPERATURE (OC)

100

1000

10000

CLOa< FREQUENCY (kHz)

TL/HI10354-3

7-44

Typical Performance Characteristics
Stopband Width
vs Supply Voltage
1;

0.06 TA = 25"C

I I I

I I

1;

ill

D.05

~

ruM~~~f~c~~=r5TO,Ok_Hrz~
1~+1

'"

I I I

~

It
§

!ii

-..lll

II
W=v+,D=GND,R=V""

W=D=R=GND,f~=250kHz

<>

i:iii

I I

H-t--+.:,-;;-::.I!:::I~I..
IL-I'-::+.;;-I!;-;:';d

Il.03

H-t-H-FM;j:;l=I::FFH

0,02

W=D=V-.R=v+.fctK =167kHz

~
~

~

O.!I6WJI 1111 111111
D.05 W=Y+.'D=GND,R=V"",fc~=500kHz

lTHVs=t5V

ruM

~

!jl

0.02

MI

MI~~~~~~~~~

I+-H-H-H-H-H--++",ITo
l-r-l

W=0=R=GND'fc~=250kIH;

Il.03

<>

l±ttttU*:rtttttfffl
W=D=V"",R=V+'~~L~lMJHZ

Clock-to-Center-Frequency
Ratio Deviation
vs Supply Voltage
D.4rT-r--rT-r--rT,.....,rT,.....,-'-'
D.2 I-+T.;'=_2r-:5T"C'+-I-+-HI-t:.I-'I""H

ili

~~

tic>

S
,\,
~

03 vs

~

02

~~

0.1

=>~

S

~

0.0 -

~

H--t-H-+JH--HH--H-H

-0.4 1-++f---t,~I-+-HH--H-H
-D.6L...J.....J.....L..J....J.~L...J.....J.....L..J....J....L.J

10000

RL -5kll

8 TA =25OC
osmVE SWING-

-2

ti ~-o.ol
~-D.02

NEGATIVE SWING

-4
-6

~-0.03

-B
-10

d-0.04

I

AI.IBIENT TEMPERATURE (OC)

Positive Output Voltage
Swing vs Load Resistance

I

R=GND

1000

Output Swing
vs Supply Voltage

-55 -35 -IS 5 25 45 65 85 105 125

1111

100

0,02

SUPPLY VOLTAGE (tV)

~

II

.II

L -.......~~..........WJJ'"-~.u..wu

10
VS=t5V

~~ 0.00

I

R=v';

R'';Y.

10

=>~

-02

III
R=V"" or GND

-0.1

1-++-1-++-1-+?1H--H-H

0.0

R=V;

CLOCK FREQUENCY (kHz)

0,0.1

Il.03

TA=~~~
III,

Cloclt-to-Center-Frequency
Ratio Deviation
vs Temperature

~

C:~t FreqU~~

-vslil~V H+t+Itt!W'TI+t+
IttHl

~;:

TEMPERATURE (OC)

SUPPLY VOLTAGE (tV)

~g

~

tf~

-55 -35 -IS 5 25 45 65 85 105 125

I

~
1;

Clock-to-Center-Frequency
Ratio Deviation

Stopband Width
vs Temperature

~

...

(Continued)

SUPPLY VOLTAGE (tV)

Negative Output Voltage
Swing vs Load Resistance

~

-3.8

~

-4.2

f-\-H-1-tt1\It-H-I-fWT"=="'2~5OC;M1#Hl

5

-4.4

f-I\H-ttI\It-1-t1ICLK~500kHz

I

-4.8
-3.9

t:tl:tttll:ttctmD:!I1I

Positive Output Swing
vs Temperature

1111

.. r;;;~~~~tm~flmm-····
·-_·_~--4.011l1
--~--4SF
1111 I
~
::::
~

4.2

o

TA -25OC
vs=:l:SV

t~~~~~~~t~+fCItt~It-=_50+-0+-kttHZttHl

I

4.1

~

4.01I+++ttlltl--t-I-tltfHl--t+++t+Hl

>

~

3,9L-J-WJ.lllJ.l.-I....l..J.J..Lllll--.w...L.WJ.U
I
10
100
1000

g

Vs -:l:5V

~ -4.6f-rN-ttI\It-H-~It-++H#m
I

LOAD RESISTANCE (kll)

10

100

1000

LOAD RESISTANCE (kll)

4.3

I+H-+-+:*-++-++++++++I

4.2

i"'r-H--H--H-++++++++++I

4.1~~~~~~~~~

-55 -35 -IS 5 25 45 65 85 105 125
AMBIENT T£IIPERATURE (OC)

Negative Output Swing
vs Temperature
~
~

~

-4.5~~~TTTTTTTTTT'"

RL=5klllll
Vs =t 5V 1+-H-I+-f+Jf+I+!-1

HzT+H--H--H-+-J.o19
-4.6 fCLK =r'5F00j-'kT'

AUBIENT TEMPERATURE (OC)
TL/H/10354-4

7-45

O'-------------------------------------------------------------~

8!
~

Pin Descriptions
W (Pin 1)

R (Pin 2)

lD(Pin3)

V- (Pin 8)

This three-level logic input sets the width of
the notch. Notch width is fc2-fcl (see Figure
1). When W is tied to V+ (pin 14), GND (pin
13), or V- (pin 8), the notch width is 0.55 fa,
0.26 fa, or 0.127 fo, respectively.
This three-level logic input sets the ratio of
the clock frequency (fCLK) to the center frequency (fo). When R is tied to V+, GND, or
V-, the clock-to-center-frequency ratio is
33.33:1, 50:1, or 100:1, respectively.
This three-level logic input sets the division
factor of the clock frequency divider. When
lD is tied to V+, GND, or V-, the division
factor is 716, 596, or 2, respectively.

VOUT (Pin 9)
D (Pin 10)

XTAl2 (Pin 4) This is the output of the internal crystal oscillator. When using the internal oscillator,
the crystal should be tied between XTAl2
and XTAL1. (The capacitors are internalno external capaCitors are needed for the
oscillator to operate.) When not using the
internal oscillator this pin should be left
open.
XTAll (Pin 5) This is the crystal oscillator input. When using the internal oscillator, the crystal should
be tied between XTAll and XTAl2. XTAL1
can also be used as an input for an external
clock signal swinging from V+ to V-. The
frequency of the crystal or the external
clock will be divided internally by the clock
divider as determined by the programming
voltage on pin 3.
ClK (Pin 6)
This is the filter clock pin. The clock signal
appearing on this pin is the filter clock
(fcud. When using the internal crystal oscillator or an external clock signal applied to
pin 5 while pin 7 is tied to V+, the ClK pin is
the output of the divider and can be used to
drive other lMF90s with its rail-to-rail output
swing. When not using the internal crystal
oscillator or an external clock on pin 5, the
ClK pin can be used as a CMOS or TIL
clock input provided that pin 7 is tied to
GND or V-. For best performance, the duty
cycle of a clock Signal applied to this pin
should be near 50%, especially at higher
clock frequencies.
XlS (Pin 7)
This is a three-level logic pin. When XlS is
tied to V +, the crystal oscillator and frequency divider are enabled and ClK (pin 6)
is an output. When XlS is tied to GND (pin
13), the crystal oscillator and frequency divider are disabled and pin 6 is an in-rut for a
clock swinging between V- and V . When
XlS is tied to V -, the crystal oscillator and
frequency divider are disabled and pin 6 is a
TIL level clock input for a clock signal
swinging between GND and V+ or between
V- and GND.

This is the negative power supply pin. It
should be bypassed with at least a 0.1 p.F
capacitor. For single-supply operation,
connect this pin to system ground.
This is the filter output.
This two-level logiC input is used to set the
depth of the notch (the attenuation at fo).
When D is tied to GND or V-, the typical
notch depth is 48 dB or 39 dB, respectively. Note, however, that the notch depth is
also dependent on the width setting (pin
1). See the Electrical Characteristics for
tested limits.

VIN2 (Pin 11)

This is the input to the difference amplifier
section of the notch filter.

VINl (Pin 12)

This is the input to the internal bandpass
filter. This pin is normally connected to pin
11. For wide bandwidth applications, an
anti-aliasing filter can be inserted between
pin 11 and pin 12.

GND(Pin 13)

This is the analog ground reference for the
lMF90. In split supply applications, GND
should be connected to the system
ground. When operating the lMF90 from a
single positive power supply voltage, pin
13 should be connected to a "clean" reference voltage midway between V+ and

V+ (Pin 14)

This is the positive power supply pin. It
should be bypassed with at least a 0.1 p.F
capaCitor.

V-.

1.0 Definition of Terms
Amax: the maximum amount of gain variation within the filter's passband (See Figure 1). For the lMF90, AMax is
nominally equal to 0.25 dB.
Aml n: the minimum attenuation within the notch's stopband.
(See Figure 1). This parameter is adjusted by programming
voltage applied to pin 10 (D).
Bandwidth (BW) or Passband Width: the difference in frequency between the notch filter's two cutoff frequencies.
Cutoff Frequency: for a notch filter, one of the two frequencies, fCl and fC2 that define the edges of the passband. At these two frequencies, the filter has a gain equal to
the passband gain.
feLK: the frequency of the clock signal that appears at the
ClK pin. This frequency determines the filter's center frequency. Depending on the programming voltage on pin 2
(R), feLK will be either 33.33, 50, or 100 times the center
frequency of the notch.
fo or fNotch: the center frequency of the notch filter. This
frequency is measured by finding the two frequencies for
which the gain -3 dB relative to the passband gain, and
calculating their geometrical mean.
Passband: for a notch filter, frequencies above the upper
cutoff frequency (fC2 in Figure 1 ) and below the lower cutoff
frequency (fCl in Figure 1).

7-46

r-----------------------------------------------------------------------------,
:s:
"TI
1.0 Definition of Terms (Continued)
2.0 Applications Information
CD
~

Passband Gain: the notch filter's gain for signal frequencies near dc or fCLK/2. The passband gain of a notch filter is
also called "HON'" For the LMF90, the passband gain is
nominally 0 dB.
Passband Ripple: the variation in gain within the filter's
passband.

o

2.1 FUNCTIONAL DESCRIPTION
The LMF90 uses switched-capacitor techniques to realize a
fourth-order elliptic notch transfer function with 0.25 dB
passband ripple. No external components other than supply
bypass capacitors and a clock (or crystal) are required.
As is evident from the block diagram, the analog Signal path
consists of a fourth-order bandpass filter and a summing
amplifier. The analog input Signal is applied to the input of
the bandpass filter, and to one of the summing amplifier
inputs. The bandpass filter's output drives the other summing amplifier input. The output of the summing amplifier is
the difference between the input signal and the bandpass
output, and has a notch filter characteristic. Notch width and
depth are controlled by the dc programming voltages applied to two pins (1 and 10), and the center frequency is
proportional to the clock frequency, which may be generated externally or internally with the aid of an external crystal.
The clock-to-center-frequency ratio can be one of three different values, and is selected by the voltage on a three-level
logic input (pin 2).

Stopband: for a notch filter, the range of frequencies for
which the attenuation is at least Amin (f81 to f82) in Figure
1 ).
Stop Frequency: one of the two frequencies (f81 and f82)
at the edges of the notch's stopband.
Stopband Width (SBW): the difference in frequency between the two stopband edges (f82-f81)'

The clock signal passes through a digital frequency divider
circuit that can divide the clock frequency by any of three
different factors before it reaches the filters. This divider can
also be disabled, if desired. Pin 7 enables and disables the
frequency divider and also configures the clock inputs for
operation with an external CMOS or TTL clock or with the
internal oscillator circuit.

frequency
TUH/10354-5

FIGURE 1. General Form of Notch Response

13

12

11

10

9

8

---~ YOUT~~~Y-

LMF90

+2, +596, +716

lD
3

XTAL2

4

XTAL1
5

elK
6

XlS
7
TLIH/10354-6

FIGURE 2. LMF90 Block Diagram

7-47

•

2.0 Applications Information

(Continued)

2.2 PROGRAMMING PINS
The LMF90 has five control pins that are used to program
the filter's characteristics via a three-level logic scheme. In
dual-supply applications, these inputs are tied to either V + ,
V-, or GND in order to select a particular set of characteristics. For example, the W input (pin 1) sets the filter's passband width to 0.55 fo, 0.26 fo or 0.127 fo when the W input is
connected to V+, GND, or V-, respectively. Applying Vand GND to the D input (pin 10) will set the notch depth to
40 dB or 30 dB, respectively.

2.3 DIGITAL INPUTS AND OUTPUTS
As mentioned above, the CLK pin can serve as either an
input or an output, depending on the programming voltage
on XLS. When CLK is operating as a TTL input, it will operate properly in both dual-supply and single-supply applications, because it has two logic thresholds-one referred to
V-, and one referred to GND. When operating as an output,
CLK swings rail-to-rail (CMOS logic levels).
XTAL1 and XTAL2 are the input and output pins for the
internal crystal oscillator. When using the internal oscillator
(XLS connected to V+), the crystal is connected between
these two pins. When the internal oscillator is not used,
XTAL2 should be left open. XTAL1 can be used as an input
for an external CMOS-level clock signal swinging from Vto V+. The frequency of the crystal or the external clock
applied to XTAL1 will be divided by the internal frequency
divider as determined by programming voltage on the LD
pin.

The R input (pin 2) is another three-level logic input, and it
sets the clock-to-center-frequency ratio to 33.33:1, 50:1, or
100:1 for input voltages equal to V+, GND, or V-, respectively. Note that the clock frequency referred to here is the
frequency at the CLK pin and at the frequency divider output
(if used). This is different from the frequency at the divider's
input. LD (pin 3) sets the frequency divider's division factor
to either 716, 596, or 2 for input voltages equal to V+, GND,
or V-, respectively. XLS (pin 7) enables and disables the
crystal oscillator and clock divider. When XLS is connected
to the positive supply, the oscillator and divider are enabled,
and CLK is the output of the divider and can drive the clock
inputs of other LMF90s. When XLS is connected to GND,
the oscillator and divider are disabled, and the CLK pin becomes a clock input for CMOS-level signals. Connecting
XLS .to the negative supply disables the oscillator and divider and causes CLK to operate as a TTL-level clock input.

2.4 SAMPLED-DATA SYSTEM CONSIDERATIONS
OUTPUT STEPS
Because the LMF90 uses switched-capacitor techniques, its
performance differs in several ways from non-sampled (continuous) circuits. The analog signal at the input to the internal bandpass filter (pin 12) is sampled during each clock
cycle, and, since the output voltage can change only once
every clock cycle, the result is a discontinuous output signal.
The bandpass output takes the form of a series of voltage
"steps", as shown in Figure 3. The steps are smaller when
the clock frequency is much greater than the signal frequency.
Switched-capacitor techniques are used to set the summing
amplifier's gain. Its input and feedback "resistors" are actually made from switches and capacitors. Two sets of these
"resistors" are alternated during each clock cycle. Each
time these gain-setting components are switched, there will
be no feedback connected to the op amp for a short period
of time (about 50 ns). This generates very low-amplitude
output signals at felK + fiN, felK - fiN, 2 felK + fiN, etc.
The amplitude of each of these intermodulation components will typically be at least 70 dB below the input signal
amplitude and well beyond the spectrum of interest.

Using an external 3.579545 MHz color television crystal with
the internal oscillator and divider, it is possible to build a
power line frequency notch for 50 Hz or 60 Hz line frequencies or their second and third harmonics using the LMF90. A
60 Hz notch is shown in the Typical Application circuit on
the first page of this data sheet. Connecting LD to V +
changes the notch frequency to 50 Hz. Changing the clockto-center-frequency ratio to 50:1 results in a second-harmonic notch, and a 33:1 ratio causes the LMF90 to notch
the third harmonic.
Table I Illustrates 18 different combinations of filter bandwidth, depth, and clock-to-center-frequency ratio obtained
by choosing the appropriate W, D, and R programming voltages.

TABLE I. Operation of LMF90 Programming Pins. Values given are for nominal levels of attenuation.
R
D

V- (fClKlfO
W
V-

V-

GND
V+

GND

GND
v+

V-

Amln
(dB)

BWlfo

-30
-30
-30
-35
-40
-40

= 100)

GND (fClKlfO

SBWlfo

Amin
(dB)

BWlfo

0.12
0.26
0.55

0.019
0.040
0.082

-30
-30
-30

0.12
0.26
0.55

0.010
0.024
0.050

-35
-40
-40

7-48

= 50)

V+ (fClKlfO

= 33.33)

SBWlfo

Amln
(dB)

BWlfo

SBW/fo

0.12
0.26
0.55

0.019
0.040
0.082

-30
-30
-30

0.12
0.26
0.55

0.019
0.040
0.082

0.12
0.26
0.55

0.010
0.024
0.050

-35
-40
-40

0.12
0.26
0.55

0.010
0.024
0.050

2.0 Applications Information (Continued)
ALIASING

tion, however, so it is best to use the highest available
clock-to-center-frequency ratio (100:1) and set the RC filter
cutoff frequency to about 15 to 20 times the notch frequency. This will provide reasonable attenuation of high-frequency input signals, while avoiding degradation of the overall
notch response. If the anti-aliasing filter's cutoff frequency is
too low, it will introduce phase shift and gain errors large
enough to shift the frequency of the notch and reduce its
depth. A cutoff frequency that is too high may not provide
sufficient attenuation of unwanted high-frequency signals.

Another important characteristic of sampled-data systems is
their effect on signals at frequencies greater than one-half
the sampling frequency. (The lMF90's sampling frequency
is the same as the filter's clock frequency. This is the frequency at the ClK pin). If a signal with a frequency greater
than one-half the sampling frequency is applied to the input
of a sampled-data system, it will be "reflected" to a frequency less than one-half the sampling frequency. Thus, an input
signal whose frequency is fs/2 + 10Hz will cause the system to respond as though the input frequency was fs/2 10 Hz. This phenomenon is known as "aliasing". Aliasing
can be reduced or eliminated by limiting the input signal
spectrum to less than f s/2.

100:1

In some cases, it may be necessary to use a bandwidth
limiting filter (often a simple passive RC low-pass) ahead of
the bandpass input. Although the summing amplifier uses
switched-capacitor techniques, it does not exhibit aliasing
behavior, and the anti-aliasing filter need not be in its input
signal path. The filter can be placed ahead of pin 12 as
shown in Figure 4, with the non-band limited input Signal
applied .to pin 11. The output spectrum will therefore be
wideband; although limited by the bandwidth of the summing amplifier's output buffer amplifier (typically 1 MHz),
even if fClK is less than 1 MHz. Phase shift in the anti-aliasing filter will affect the accuracy of the notch transfer func-

50:1

TUH/l0354-7

FIGURE 3. Output waveform of a sWitched-capacltor
filter. Note the voltage steps caused by sampling
at, the clock frequency.

:c
12

11

10

9

8

3

4

5

6

7
TLlH/l0354-B

FIGURE 4. Using a simple passive low-pass filter to prevent aliasing In the presence of high-frequency input signals•

7-49

•

C) r-----------------------------------------------------------------------------------------~

~

::::E

...I

2.0 Applications Information (Continued)
NOISE
Switched-capacitor filters have two kinds of noise at their
outputs. There is a random, "thermal" noise component
whose level is typically on the order of hundreds of microvolts. The other kind of noise is digital clock feedthrough.
This will have an amplitude in the vicinity of 50 mV peak-topeak. In some applications, the clock noise frequency is so
high compared to the signal frequency that it is unimportant.
In other cases, clock noise may have to be removed from
the output signal with, for example, a passive low-pass filter
at the lMF90's output pin.

At the maximum clock frequency of 1.5 MHz, the lowest
typical value for the effective RIN at the VINl input is therefore 222 kO. Note that RIN increases as fClK decreases, so
the input impedance will be greater than or equal to this
value. Source impedance should be low enough that this
input impedance doesn't significantly affect gain.
The summing amplifier input impedance at VIN2 is calculated in a similar manner, except that CIN = 5.0 pF. This yields
a minimum Input impedance ,of 133 kO at VIN2. When both
inputs are connected together, the combined input impedance will be 83.3 kO with a 1.5 MHz filter clock.

CLOCK FREQUENCY LIMITATIONS
The performance characteristics of a switched-capacitor filter depend on the switching (clock) frequency. At very low
clock frequencies (below 10Hz), the time between clock
cycles is relatively long, and small parasitic leakage currents
cause the internal capaCitors to discharge sufficiently to affect the filter's offset voltage and gain. This effect becomes
more pronounced at elevated operating temperatures.
At higher clock frequencies, performance deviations 'are primarily due to the reduced time available for the internal operational amplifiers to settle. Best performance with high
clock frequencies will be obtained when the filter clock's
duty cycle is 50%. The clock frequency divider, when used,
provides a 50% duty cycle clock'to the filter, but when an
external clock is applied to ClK, it shoul~ have a duty cycle
close to 50% for best performance.

TL/H/10354-9

FIGURE 5. Simplified LMF90 bandpass section Input
stage. At frequencies well below the center frequency,
the input impedance appears to be resistive.

2.5 POWER SUPPLY AND CLOCK OPTIONS
The lMF90 is designed to operate from either Single or dual
power supply voltages from 5V to 15V. In either case, the
,supply pins should be well-bypassed to minimize any feedthrough of power supply noise into the filter's signal path.
Such feedthrough can Significantly reduce the depth of the
notch. For operation from dual supply voltages, connect V(pin 8) to the negative supply, GND (pin 13) to the system
ground, and V+ to the positive supply.

Input Impedance
The input to the bandpass section of the lMF90 (VIN1) is
similar to the switched-capacitor circuit shown in Figure 5.
During the first half of a clock cycle, the 81 switch closes,
charging CIN to the input voltage VIN. During the second
half-cycle, the 82 switch closes, and the charge on CIN is
transferred to the feedback capaCitor. At frequencies well
below the clock frequency, the input impedance approximates a resistor whose value is
1
RIN=---'
CINfClK
At the bandpass filter input, CIN is nominally 3.0 pF. For a
worst-case calculation of effective RIN, assume CIN =
3.0 pF and fClK = 1.5 MHz. Thus,

For single supply operation, simply connect V- to system
ground and GND (Pin 13) to a "clean" reference voltage at
mid-supply. This reference voltage can be developed with a
pair of resistors and a capacitor as shown in Figures 10
through 16. Note that for single supply operation, the threelevel logic inputs should be connected to system ground
and V+ 12 instead of V- and GND. The ClK input will operate properly with TTL-level clock signals when the lMF90 is
powered from either single or dual supplies because it has
two TTL thresholds, one referred to the V- pin and one
referred to the GND pin. XLS should be connected to the
V- pin when an external TTL clock is used. Figures 6
through 16 illustrate a wide variety of power supply and
clock options.

RIN (Min) = 4.5 x 110 _ 6 = 222 kO.

7-50

.-----------------------------------------------------------------------------,
2.0 Applications Information (Continued)

==
J:
Q

DUAL-SUPPLY CLOCK OPTIONS
+5V

VOUT

-5V

To V- or GND.
See Table 1.

14

13

~

12

11
VIN2

10
D

I .0•1 J.\F
9

VOUT

8
V-

LMF90

feLK
fO=-R-

R= 33.3, 50, or 100.
S•• Tabl. 1.

3
To

5

4

V+, V-, or GND.
Se. Tabl. 1.

CLK
6

XLS
7

t--_ _ _ _ _ Ext.rnal Clock In

r'1 r'1 r-1 +5V
.....J W
L..J L-5V
felK
TLlH/l0354-10

FIGURE 6. Dual supply; external CMOS-level clock. Internal frequency divider disabled.
-5V

+5V
To V- or GND.
S•• Tabl. 1.
----~ 14~--~-~- t3----~---12----

v+

GND

VIN1

11------- 10------ 9- --------- - g - - D

VIN2

VOUT

---=------- --------------

V-

LMF90

feLK
'O=-R-

=

R 33.3, 50, or 100.
S•• Tabl. 1.

LD
3

To

XTAL2

XTAL1

4

5

V+, V-,or GND.
S.e Table 1.

CLK
6

XLS
7

I -_ _ _ _ _ Extemal

Clock In

r'1 r'1 r'1 +5V
.....J W
L..J L OV
fClK
TL/H/l0354-11

FIGURE 7. Dual supply; TTL-level clock. Internal frequency divider disabled.

7-51

2.0 Applications Information (Continued)
DUAL-SUPPLY CLOCK OPTIONS
+5V

Vour

-5V

To V- or GHD.
See Table 1.
13

14

12

11
V,N2

10
0

.I.0•1 .uF
9

8

Vour

V-

Ix 1
IO=LDX1l
R= 33.3, 50, or 100.
See Table 1.
lD=2,596,or 716.
See Pin Description.

LMF90

ClK
3

To

V+, V-, or GND.
See Table 1.

5

4

To V+, V-,or GHD.
See Pin Descrlpllon.

6

XlS
7

+5V
'--_ _ _ _ _ _ _ _ _ _ External Clock In
~

...J

~

W

r-1
L-

L..J

+5V
-5V

Ix
TL/H/l0354-12

FIGURE 8. Dual Supply; external CMOS-level clock. Internal frequency divider enabled.
Output of logic divider available on pin 6.
+5V

Vour

-5V

9

8

To V- or GHD.
See Table 1.
14

VOUT

ICRYS 1
10 =""LD x11

LMF90

R=33.3,50,or 100.
See Table 1.
lD=2,596,or 716.
See Pin Description.

ClK
2

To

V+, V-, or GHD.
See Table 1.

3

4

5

To V·, V-, or GND.
See Pin Descrlpllon.

XlS
7
+5V
TLlH/l0354-13

FIGURE 9. Dual supply; Internal crystal clock OSCillator.
Internal frequency divider enabled. Output of logic divider available on pin 6.

7-52

2.0 Applications Information

(Continued)

SINGLE·SUPPLY CLOCK OPTIONS
0.1 }'F
+5V

VOUT

10k
To V- or GND.
S•• Tabl. 1.
12

13

14

11
VIN2

10
D

8

VO UT

V-

LMF90

ICLK
10=-R-

=

R 33.3, 50, or 100.
S•• Table 1.

3

5

4

CLK
6

XLS
7

+2.5V
'--_ _ _ _ _ Extemal Clock In

To V+, V-, or GND.
S•• Tabl. 1.

r1 r1 r-1 +5V
..J W
L-I L.. OV
ICLK
TLlH/l0354-14

FIGURE 10. Single

+ 5V supply; external TTL·level clock. Internal frequency divider disabled.

+5V
10k
_~O.I}'F

14

To V- or GND.
____ ~ Tabl'-_~ _______'-_________________ _

10k

____ _
13

12

10

11

9

8

VOUT

IX 1
10 =Ul xjf

LMF90

R=33.3, 50, or 100.
See Table 1.
LD=2,596,or 716.

S•• Pin Description.

3

To

V+, V-,or GND.
S.e Table 1.

5

4

To V+, V-,or GND.
See Pin D.scrlptlon.

CLK
6

XLS
7

+5V
'--_ _ _ _ _ _ _ _ _ _ Extemal Clock In

r1 r1 r1 +5V
..J W
L-I L.. OV
IX

FIGURE 11. Single + 5V supply; external CMOS·level clock.
Internal frequency divider enabled. Output of logic divider available on pin 6.

7·53

TL/H/l0354-15

2.0 Applications Information (Continued)
SINGLE-8UPPLY CLOCK OPTIONS
0.1 J.lF
+10V

Y,N

VOUT

10k

To V- or GND.
See Tabl. 1•

.I.o•1J.1r
14

10

9

v+

VOUT

8

V-

LMF90

fCLK

fO=-R-

R=33.3,50,or 100.

S.e Tabl. 1.

3
To

5

4

V+, V-,or GND.
Se. Tabl. 1.

ClK

XLS

6

7

....._ _ _ _ _ Extemal Clock In

r-1 r-1 . , +5V
W
L..J L. OV

-l

fCLK
TL/H/l0354-16

FIGURE 12. Single

+ 10V supply; external TTL.JevIII clock. Internal frequency divider disabled.

O.IJ.1r
+10V

VOUT

10k
To V- or GND.

Sa. Table 1.
9

14

8

Vour

LMF90

fCLK

fO=-R-

R= 33.3, 50, or 100.
S•• Tabl. 1.

4 .

3
To

CLK
6

5

V+, V-,or GND.

XLS
7
+5V

S•• Table 1.

....._ _ _ _ Ext.mal Clock In

r-1 r-1 r-1 +10V
W
L..J L. OV

-l

fCLK
. :.:.

FIGURE 13. Single

.

'"

+ 10V supplYi exte~al CMOS-level clock. Internal frequency divider disabled.
7-54

TUH/l0354-17

r-----------------------------------------------------------------------------~

r

i:

2.0 Applications Information (Continued)

!

SINGLE·SUPPLY CLOCK OPTIONS
+10V

Vour

10k

To" or GHD.
Se, Table 1•

.:c0.l J.lF

14

10

9

8

Vour

"
fX 1
fO=lDXjf

LMF90

=

R 33.3, 50, or 100.
See Table 1.
LD=2,596,or 716.
See Pin Description.

2

To

V+, ",or GND.
See Table 1.

3

5

To V+, ",or GND.
See Pin Description.

ClK

XLS

6

7

+10V
' -_ _ _ _ _ _ _ _ _ _ Exlemal Clock In

r-1 r-1 11 +10V
....I W
W
Lov
fx
TlIHI10354-18

FIGURE 14. Single + 10V supply; external CMOS-level clock.
Internal frequency divider enabled. Output of logic divider available on pin 6.

Vour

+5V or +10V
10k

- - -----

-----~--

-101(-- -- --------- ---

To" or GND.

--Si8TiibteT:---~-

-------

-----~

~~------ -~------

.:c0.l J.lF

10

14

v+

9

8

Vour

fCRYS

1

fO ='"Iij"'-xjf

LMF90

=

R 33.3, 50, or 100.
See Table 1.
lD=2, 596,or 716.
See Pin Description.

LD
3

To

V+, 'V,or GND.
See Table 1.

To V+, 'V,or GND.
See Pin Description.

XTAL2

XTAl1
5

"

CLK
6

XLS
7

+5V or +10V
TlIH/l0354-19

FIGURE 15. Single

+ 5V or + 10V supply; Internal crystal clock oscillator. Internal frequency divider enabled.
Output of logic divider available on pin 6.

7·55

LMF90

~

'a

C;'

!.

»

'a

"2-

~'

0'

,v,.

+SV

.. ~ ..
~

..,.

Jl~ rl"~O"I'F ~
•

I+SV

_5V ::l

Vour

.

-=

10

IVour

Your.

LMF90

LMF90

·NON-OVERLAPPING
CLOCi( GENERATOR

&.

Ol

I

Lo V+) the absolute value of current at that pin should be limited
. to 5 mA or less. -The sum of the currents at all pins that are driven bayond the powar supply voltages should not exceed 20 mAo
Nota 3: Too maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 8JA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po = (TJMAX - TNI8JA or the number given In the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX = 125'C, and the typical junction-to-amblent thennal resistance of the LMF100ACN/CCN/CIN when board mounted is 55'C/W. For the
LMF100AJ/CIJ, this number increases to 95'C/W and for the LMF100CIWM this number is 66"C/W.
Note 4: The accuracy of the Q value Is a function of the center frequency (fo). This is illustrated in the curves under the heading "Typical Peformance Cha";cterls. tics".
Nota 5: VOSIo Vos2, and Vosa refer to the internal offsets as discussed In the Applications Infonnation section 3.4.
Nota 6: Crosstalk between the Internal filter sections Is measured by applying a 1 VRMS 10 kHz signal to one bendpass filter section Input and grounding the input
of the other bandpass filter section. The crosstalk Is the ratio between the output of the grounded filter section and the 1 VRMS Input signal of the .other section .
. Note 7: The short circuit source current is measured by forcing the output. that Is being tested to Its maximum positive voltage swing and then shorting that output to
the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting
that output to the positive supply. These are the worst case conditions.
Note 8: Typlcals are at 25'C and represent most likely parametriC norm.
Note 9: Tested limits are guaranteed to National's AOQL (Average OutgOing Quality LeveQ.
Note 10: Design lim"s are guaranteed to National's AOQL (Average Outgoing Quality L,evel) but are not 100% tested.
Note 11: Human body model, 100 pF discharged through a 1.5 kfl resistor.
Note 12: In 50:1 mode the output noise is 3 dB higher.
Note 13: In 50:1 mode the clock feedthrough is 6 dB higher.
Note 14: A milhary RETS specHication is available upon request.

"~

7-60

.

r-

==

Typical Performance Characteristics

."
~

o

o
Power Supply Current vs
Temperature

Power Supply Current vs
Power Supply Voltage
12

9.0 / '

]:

]:

11

1
a

10

./
./
./

9

b

8:

oil

,

8

~

.e

./
./

J
~

7
5
10
15
Power Supply Voltag. (V)

20

r-.

I

6

......- i-"'"

~

!,5
t

...... ~

-~

.......

~

1

~.

-55 -35 -15 5 25~ 65 85105125
T.mp....ture (OC)

/
3V

Ii'

---

-3

V,=t2.5V-

r./

.

.....

fClk=IMH:_
TA =25OC
-" 99.6 ' - - r--VPlnI2=OV-

'-

-5
100

101

102

1005

-.

./

_0100.0

.....

Q=2

_fs

/

995

60

~

60

-

100

V
j

V

,

1005

:8

500 1000 1500 2000 2500 3000 3500
felk (kHz)

60

«l

20

100

80

Q

V,=:I2.5V
TA =25OC
Vpln 12 = +2.5,

/I

/ ~/
I

_0100.0

.....

1/

,j

,.

fCLKIfO Ratio vs fCLK
52

Q=10//

Q=100/

~_0

51

-"

50

I
I

I

Q=100!

~Q=I~j

;,.

995

99.0
0

-

I

r-Q=2 ......

r

V

49

1000

2000

felk (kHz)

3000

0

500

1000

1500

2000

2500

folk (kHz)
TL/H/5645-8

7·61

-

I
0

Q=2/
99.Q

--

TA=25OC- - VPlnI2=(- -

Q

V.=:I2.5V
-TA=25OC
Vpln 12=OV

- -

'elk= 1 MHz

-"

fCLKIfO Ratio VB fCLK

Q=10j

Q=IOO

0

V. = t2.5V =

"

49.8

49.2

101.0

V.=t5V
r- TA =25OC
Vpln12=OV

:8

i

~49.6

99.2

fCLKIfO Ratio vs fCLK
101.0

r--r---

49.4

20

103

V,=t5V

5O.Q

99.4

°

103

102

L

V.=t5V

Load R••s!anc. (kll)

,

./

_099.8

1\

101

fCLKIfO Ratio vs Q
---

~

z:

,..."'""
Load R.oJs!anc. (kll)

V,=t5V

011lO.D

-~

V,=t5V
~

50.2

_ 100,2

8

V,=:I2.5V

2

fCLK/fo Ratio vs Q

V.=:I2.5V

-- - -

f
,5.

....

4

~

101l.4

-21"-

5 6
7
Supply Voltag. (t V)
~

3

1
lrP

-5

Negative Output Voltage
Swing vs Load Resistance

~

2

~

-~

i'

z

2f- f- V.=tJ.5V

~
~

RlOAO=511l

~

....

-8

5

V,=:I2.5V

.fen

-

Positive Output Voltage
Swing vs Load Resistance

~ -3
RlOAO =5 kll

RlOAO = 5 kll
TA =25OC

-6

V,=t5V

-

r""

0

Negative Output Swing
vs Temperature

1
-55 -35 -15 5 25 ~ 65 85 105 125
T.mp....ture (OC)

-

"...'

2

~ -2

h=250kHz

75

8

V.=t5V

3

i

!

V,=t2.5V

8.0

-2

~

f

.

~

t'...

Positive Output Swing
vs Temperature
5

~

m

7.0
-55 -35 -15 5 25 ~ 65 85 105 125
T.mp....ture (OC)

6

0

~

r-.

8.5

1
a

TA=25OC
f olk = 250 kHz -

V =tsV""

Output Swing vs
Supply Voltage

8

i:i:
~

Typical Performance Characteristics (Continued)

fCLKlfO Ratio va Temperature

fCLKlfO Ratio va fClK
52

j

-

tI"

Q=I00

".

y

<-

l./

-

Q Deviation va Clock

j

Q=IOO

-Ii

0

o

k
Q=V

'i
cr

4

~

2

50:1
_Vt U •5V
_·A=25"1:

J

I
/0=10
~
Q=2;-'

I

.!!.

.J.'
-2

cr

i

0

Q=IOO

o

500

1000

1500

2000

Maximum fo vs Q at

O!¢~J.~5X

Q
Rallo OovIation < III

50:1

50

1500

2000

o

2
V,=:t2.5V/

V~=:t~V

~ r-..

V
/V

r'= ~2iV

~~i5V

-

mod.r. . . . "-"
.......

-

--.

-

Nominal Q=10

J
.!!.

r- ...........

cr

:!

&

0

30

"

100:1 mod. 1,""

'\.'\

V~.5V-

.......

-1

-55-:55-15 5 25 45 65 85 105125
Tlmponolu.. ("1:)

Maximum fo vs Q at
60

I

--......I

50

35:1 modo lb

I

30

"" 1\.\,

...... .

I'\.'\..

'"

,

~

V,=:t5V

«l

50 50:1 modo 1 --......
,,\

2500

Va = ±2.5V

TA=25"C
Q DoYlellon <5"
Ratio OovIalion < 1"

70 35:1 modo 1b "'-

1000 1500 2000
Frequlncy (kHz)

~J.RaIio
100:1
'clk= 1MHz

Maximum fo vs Q at
110

500

Q Deviation va Temperature

J

90

It- "-

100:1 mod. 1

1000

Vs= ±5.0V

90 35:1 modo

70

'\ Q= 10
'\
0=100'

-2

-6

500

1
-55 -:55 -15 5 25 45 65 85 105 125
Tlmporolure ("1:)

V. = ±7~5V

'-

i

-4

I

2500

Frequency (kHz)

130

./ 11\
\.

I

Ratio 50:1
'cIk=IYHz
Nominal Q= 10

n

f
/

I

Q Deviation vs Temperature

II \

Q=2

TA=25"C

I
I

0=2

o

2
Rallo 100:1
V,=:t5V
TA =25"1:

Rallo 100:1
V =U.5V

Frequ.ncy (kHz)

8

110

Q Deviation va Clock
Frequency

o

500 1000 1500 2000 2500 3IlOO 3500
Frequoncy (kHz)

-

Tompo",lu .. ("1:)

0=10

a

. -2

1Tr

6

Q Deviation va Clock
Frequency

-4

I

Q=IOO

8

.!!.

0=10
'elk= 1 MHz

;'

V 1
99.8
-55 -:55 -15 5 25 45 65 85 105 125

VPlnI2=Y+-

10
Q=10

---:

I I

/
~

12

20

50:1
I-- V,=:t5V
TA = 25"1:

v.JU~V I-'-

)ggs

,!~ltHz'-

_I'

I I

100.0

Q Deviation vs Clock
Frequency

Frequency

-10

./

0

:;

. -55 -:55 -15 5 25 45 65 85 105 125
Tompo",luro ("1:)

500 1000 1500 2000 2500 3IlOO 3500

'elk (kHz)

~

,,

,

0=2

o

r--r-- V)U~5V 17 <-,-

,/

V,~u~

,

V,=:t5V
Q=I ,0

Vpln 12=:t5V

)50

49

fCLKlfO Ratio va Temperature
100.1

r- Jv,~u~
A= 25"1:

51

.

20

10

Q~:'~5X

Rallo DoYIaIIon < III

.........

"

50:1 modo 1

......... \
1\.\

100:1 mod. 1

.........

I

~\
I'-~

liP

o

Q

Q

TL/H/5845-9

7-62

...
!!:

....

LMF100 System Block Diagram

."

8
INV.

AGND

CLICa

50/100
L Sh

INV.

Vii

V. N/AP/HI's SIB
TLlH/5645-1

Pin Descriptions
LP(1,20), BP(2,19), The second order lowpass, bandpass and notch/allpass/highpass'
N/AP/HP(3,18)
outputs. These outputs can typically
swing to within 1V of each supply

5A/B(6)

-'-----------when'.irriVlii9-a5-k1floaa~-F'or opti~----

INV(4,17)

51(5,16)

mum performance, capacitive loading on these outputs should be minimized. For signal frequencies above
15 kHz the capacitance loading
should be kept below 30 pF.
The inverting input of the summing
opamp of each filter. These are high
impedance inputs. The non-inverting
input is internally tied to AGND so
the opamp can be used only as an
inverting amplifier.
51 is a signal input pin used in
modes 1b, 4, and 5. The input impedance is 1/fCLK X 1 pF. The pin
should be driven with a source impedance of less than 1 kO. If 51 is
not driven with a signal it should be
tied to AGND (mid-supply).

This pin activates a switch that connects one of the inputs of each filter's second summer either to AGND
(5A1B tied to V-) or to the lowpass

- ' - - ..-~___:---(tP)-output-(5A7Btiecrto-V+}.This - -- - - - - "
offers the flexibility needed for configuring the filter in its various modes
of operation.
VA + (7)*
This is both the analog and digital
positive supply.
Vo+(8)*
This pin needs to be tied to V+ except when the device is to operate
on a single 5V supply and a TTL level clock is applied. For 5V, TTL operation, Vo + should be tied to ground
(OV).
VA -(14), Vo-(13) Analog and digital negative supplies.
VA - and Vo - should be derived
from the same source. They have
been brought out separately so' they
can be bypassed by separate capacitors, if desired. They can also ba tied
together externally and bypassed
with a single capacitor.

•

7-63

1.0 Definitions ofTerms

Pin Descriptions (Continued)
LSh(9)

CLK(10,11)

50/100(12)·

AGND(15)

Level shift pin. This is used to ac-,
commodate various clock levels with
dual or"single supply operation. With '
dual ± 5V supplies and CMOS (± 5V)
or TTL (OV-5V) clock levels, LSh
should be tied to system ground.
For OV-10V single supply operation I
the AGND pin should be biased at
+ 5V and the LSh pin should be tied
to the system ground for TTL clock
levels. LSh should be biased at+ 5V
for ± 5V CMOS clock levels.
The LSh pin is tied to system ,ground
for ± 2.5V operation. For single 5V
operation the LSh and VD+ pins are
tied to system ground for TTL clock
levels.
Clock inputs for the two switched ,ca- '
pacitor filter sections. Unipolar or bipolar clock levels may be applied to
the CLK inputs according to the programming voltage applied'to the LSh
pin. The duty cycle of the clock
should be close to 50%, especially
when clock frequencies above
200 kHz are used. This allows the
maximum time for the internal
opamps to settle, which yields optimum filter performance.
By tying this pin to V + a 50: 1 clock
to filter center frequency ratio Is obtained. Tying this pin at mid-supply
(i.e., system ground with dual supplies) or to V- allows the filter to operate at 'a 100:1 clock to center fre. quency'ratio.
This is the analog ground pin. This
pin should be connected to the system ground for dual supply operation
or biased to mid-supply for single
supply operation. For a further discussion of mid-supply biasing techniques see the'Applications Informa:' tion (Section 3.2). For optimum filter
performance a "clean" ground must
, be provided.

fCLK: the frequency of the external clock signal applied to
pin'10 or 11.
:' fo: center frequency of the second order function complex
pole pair. fo is measured at the bandpass outputs of the
LMF100, and is the frequency of maximum bandpass gain.
(Figure 1).
fnotch: the frequency of minimum (idealiy zero) gain at the
notch outputs.

.fz: the center frequency qf·the second order complex zero
pair; if any. If fz is different from fo and if Oz is high, it can be
observed as the frequency of a notch at the alipass output.
(Figure 13).

Q: "quality factor" of the 2nd order filter. a is measured at
the bandpass outputs of the LMF100 and is equal to fo divided'by the :-3 dB bandWidth of the 2nd order bandpass
filter (figure tJ. The value of a determines the shape of the
2nd order filter responses' as shown in Figure 6.

Qz: the quaiity factor of the second order complex zero pair,
if any. az is related to the allpass characteristic, which is
written:
HOAP ( s2 - s;o
HAP(S) =

+ 1JJ02)

z
s2

+,SlJJo +

a

1JJ02

where az = a,for an ali-pass response.
HOBP: the gain (in VIV) of the bandpass output at f = fo.
HOLP: the gain (in VIV) of the lowpass output as f (Figure 2).

0 Hz

HOHP: the gain (In VlV) of the hlghpass output as f fCLK/2 (Rgure 3).
'
HON: the gain (in VIV) of the notch output as, f 0 Hz
an!l as f fCLK/2, when the notch filter hai equal gain
abclve an,d below the center frequency (Figure 4). When the
low-frequency gain differs from the high-frequency gain, as
in modes 2 and 3a (FigufBS 10 and 12), the two quantities
below are used in place of HON. '

HON1: the gain (in VlV) of the notch output as f HON2: the gain (in VIV) of the
I:

'This device Is pin-far-pin compatible with the MF10 except for the following
changes:
1. Unlike the MF10,. the LMF1 00 h~ ~ single positive supply pin (VA +).
2. On the LMF100 Vo+ Is a control pin and Is not the digital positive supply
as on the MF10.
3. Unlike the MF10. the LMF100 does not support the currant limHing mode,
When the 50/100 pin is tied to V- the LMF100 will remain in the 100:1
mode.

7-84

~otch output as f

-

0 Hz.
fCLK/2.

,-----------------------------------------------------------------------------,
1.0 Definitions of Terms (Continued)

~

iii:

."

.....

o
o
;;:-

HOBP

1-----.,.......

~ 0.707 HOBP 1-----1-1--\.

iB

90

So

45

1----""'"

~ Ol----+~
iE -45 I----+-+-""""'-

!

I------t-H---"'.....

-90

IL 10 IH
I (LOG SCALE)

IL I, IH
I (LOG SCALE)

TL/H/5645-20

TLlH/5645-19

(b)

(a)

FIGURE 1. 2nd-Order Bandpass Response

>
~

Hop

HULP

;; 0.707 HOLP

D

f-;;;;;:;:;;;;;;....I\

6'

I----f-''''-

ljj -9D

!1

t-

~

1i

-1SD

I-----''IL

1----+---=-

Ip Ie
I (LDG SCALE)

10
I (LOG SCALE)

TL/H/5645-21

TL/H/5645-22

(a)

(b)
HOp = HOLP X

!~1
Q

_

1

4Q2

FIGURE 2. 2nd-Order Low-Pass Response

--------~

---------~--

----------------

HOP~=:::;;~!!!-.-t"

~

HOHP

ljj-9D ~-----::lr

z D.707 HOHP

~

~

-180

10
I (LOG SCALE)

Ie
Ip
I (LOG SCALE)

TL/H/5645-24

TLlH/5645-23

(b)

(a)

fp = fO

x

fI

[~1 - 2~2]-1

HOp = HOHP X

!~1
Q

1
_

1

4Q2

FIGURE 3. 2nd-Order High-Pass Response

7-65

g
....

II.

1.0 Definitions of Terms (Continued)

!I

+ (J)o2)
+ S{J)o + {J)o2

HN(S) = HON(S2

90
;:'

HON

;;:
Z 0.707 HON

I---~,--~---

jij

S2

Q

~

45

III

0

Q = _fO_; fO =
fH - fL

IE -45 1----40..
-90

~

fL = fO

(;~ + ~(ia)2 + 1 )

fH =fO

(2~ + ~C~)2 + 1 )

____~~____~•
... IofH

ILIa fH
, (LOB SCALE)

, (LOB SCALE)

TUH/5645-25

TLlH/5645-26

(a)

(b)

.f1iJH

FIGURE 4. 2nd-order Notch Response

;:' HAP

1----,---

~
ril- 180 I--------.:~

~

~

iE
-360

10

t:::====±==::::
10

, (LOB SCAlE)

, (LOG SCALE)

TUH/5645-27

TLlH/5645-28

(b)
FIGURE 5. 2nd-order All-Pass Response

(a)

(a) Bandpass

(b) Low Pass

20

20

10

10

-

f--0-l0

!z

~

Z -10

jij

-20

......

-10

0-0.5~

jij

Q=~

pO=5-!-

~=0.707~

'1

-20 1- 0 0. 2

Z -10

~,
"

0.5 1
FREOUENCY (Hz)

0.1

10

~

0.2

0.5 1.0

2.0

5.0

FREOUENCY (Hz)

(d) Notch

0=0.5
0=0.2

-20

-30

"

J_

-40

i

...«

,........

-30

-30

0=10

10

L~~=!±
~0=1

0=1

...

(c) High-Pass
20

'"

-40

10

0.1

0.2

0.5 1.0 2
. FREQUENCY (Hz)

5

10

(e) All-Pass

20

:::t"" -

10

...

"

;- -10

jij
-20

-60
6" -120

~:~-

:!l

i

I'-.....WOr-l

R3
TLlH/5845-17

FIGURE 17. MODE 6c

OUlt

IN2

OUT2

Rl

INI >-Jlll.~" . . 1--1

TLlH/5845-37

Equivalent Circuit

OUTI
INI

OUT2

>---1 :~---1

IN2>------I
TL/H/5845-3B

K=&
R1
OUT1

= -~IIN1dt-1.IIN2dt

OUT2

= 1.1 OUT1 dl

T

T

T

FIGURE 18. MODE 7

7-72

r
3:

2.0 Modes of Operation (Continued)

."

TABLE I. Summary of Modes. Realizable filter types (e.g. low-pass) denoted by asterisks.
Unless otherwise noted, gains of various filter outputs are Inverting and adjustable by resistor ratios.
Mode
1
1a

Number of
Resistors

Adjustable
fCLKlfO

3

No

2

No

May need input buffer. Poor dynamics
for high Q.

3

No

Useful for high
frequency applications.

3

Yes (above
fClK/50 or
fClK/100)

4

Yes

Universal StateVariable Filter. Best
general·purpose mode.

7

Yes

As above, but also
includes resistortuneable notch.

3

No

Gives Allpass response with HOAP = - 1
and HOlP = -2.

4

Yes

Gives flatter all pass
response than above
if Rl = R2 = 0.02R4'

3

Yes

Single pole.

(2)
HOlPl = + 1
2
-R3 - - - - ---- - -- ~HOlP2 == R2-

Yes

Single pole.

3

No

Single pole.

2

Yes

Summing inte~tor with
adjustable time constant.

BP

LP

·

·

(2)
HOBPl = -Q
HOBP2 = + 1

·
·

4

•

•

S

·

·
·

2

3

3a

6a
6b

6c

N

AP

·

HOlP=+1

·
·
·
·

1b

HP

·
·
·
·

•

·

•

·
·

·

·

·

7

.....
0
0

Notes

3.0 Applications Information
The LMF100 is a general purpose dual second-order state
variable filter whose center frequency is proportional to the
frequency of the square wave applied to the clock input
(fClK)' The various clocking options are summarized in the
following table.
Clocking Options
Clock Levels

LSh

VD+

-SVand +SV
-SVand +SV

TTL (OV to + SV)
CMOS (-SVto +SV)

ov
ov

+SV
+SV

OVand 10V
OVand 10V

TTL (OV to SV)
CMOS (OV to + 10V)

OV
+SV

+10V
+10V

OV

+2.SV

OV
+2.SV

OV
+SV

Power Supply

- 2.SV and + 2.SV CMOS
(-2.SVto +2.SV)
OVandSV
TTL (OV to + SV)
OVandSV
CMOS (OV to + SV)

By connecting pin 12 to the appropriate dc voltage, the filter
center frequency, fo, can be made equal to either fClK/1 00
or fClK/SO. fo can be very accurately set (within ±0.6%) by
using a crystal clock oscillator, or can be easily varied over
a wide frequency range by adjusting the clock frequency. If
desired, the fClK/fo ratio can be altered by external res istors as in Figures 10, 11, 12. 13, 14, 15 and 16. This is
useful when high-order filters (greater than two) are to be
realized by cascading the second-order sections. This allows each stage to be stagger tuned while using only one
clock. The filter Q and gain are set by external resistor ratios.
All of the five second-order filter types can be built using
either section of the LMF100. These are illustrated in Figures 1 through 5 along with their transfer functions and
some related equations. Figure 6 shows the effect of Q on
the shapes of these curves.

7-73

•

gr---------------------------------------------------------------------~

.....

II.

~

3.0 Applications Information (Continued)
In most filter designs involving multiple second-order
stages, it is best to place the stages with lower 0 values
ahead of stages with higher 0, especially when the higher 0
is greater than 0.707. This is due to the higher relative gain,
at the center frequency of a higher-O stage. Placing a stage
with lower 0 ahead of a higher-O stage will provide some
attenuation at the center frequency and thus help avoid clipping of signals near this frequency. For this example, stage
A has the lower 0 (0.785) so it will be placed ahead of the
other stage.

3.1 DESIGN EXAMPLE
In order to design a filter using the LMF100, we must define
the necessary values of three parameters for each secondorder section: fa, the filter section's center frequency; Ho,
the passband gain; and the filter's O. These are determined
by the characteristics required of the filter being designed.
As an example, let's assume that a system requires a
fourth-order Chebyshev low-pass filter with 1 dB ripple, unity
gain at dc, and 1000 Hz cutoff frequency. As the system
order is four, it is realizable using both second-order sections of an LMF100. Many filter design texts (and National's
Switched Capacitor Filter Handbook) include tables that list
the characteristics (fa and 0) of each of the second-order
filter sections needed to synthesize a given higher-order filter. For the Chebyshev filter defined above, such a table
yields the following characteristics:
fOA = 529 Hz
fOB = 993 Hz

For the first section, we begin the design by choosing a
convenient value for the input resistance: R1A = 20k. The
absolute value of the passband gain HOLPA is made equal
to 1 by choosing R4A such that: R4A = -HOLPAR1A = R1A
= 20k. If the 50/100/CL pin is connected to mid-supply for
nominal 100:1 clock-to-center-frequency ratio, we find R2A
by:

OA = 0.785
OB = 3.559

R
= R
fOA2
=
4
(529)2_
2A
4A (fCLK/100)2
2 X 10 X (1000)2 - 5.6k and

For unity gain at dc, we also specify:
RSA = OA ~R2AR4A = 0.785~5.6 X 103 X 2 X 104 = 8.3k

HOA = 1

The resistors for the second section are found in a similar
fashion:

HOB = 1
The desired clock-to-cutoff-frequency ratio for the overall
filter of this example is 100 and a 100 kHz clock Signal is
available. Note that the required center frequencies for the
two second-order sections will not be obtainable with clockto-center·frequency ratios of 50 or 100. It will be necessary
fCLK
.
to adjust - - externally. From Table I, we see that Mode 3
fa

RIB = 20k
R4B = RIB = 20k
R

_
fOB2
_
(993)2 _
, 2B - R4B(fCLK/100)2 - 20k(1iiOO)2 - 19.7k
RSB = OB~R2BR4B =3.559~1.97 X 104 x 2 x 104 = 70.6k
The complete circuit is shown in Figure 19 for split ±5V
power supplies. Supply bypass capacitors are highly recom·
mended.

can be used to produce a low-pass filter with resistor-adjustable center frequency.

RIB
20k

LPA

LP S

BPA

BPB

N/AP/HPA

N/ AP/HPB

INVA

VIN

SIA
-5V

INVS

LIAFIOO

19

R3B
70.6k

18

R2B
19.7k

17

SIS

VAt

VA-

VD+

VO-

0.1

14
-5V
0.1

50/100/CL
10

..fl..Il..

20

AGND

SA/s

+5V

VOUT
R4B
20k

CLKA

CLKs

11

CLOCK IN
feu< 100 kHz

=

TLIH/S64S-30

FIGURE 19. Fourth-order Chebyshev low-pass filter from example In 3.1.
± SV power supply. OV-SV TTL or ± 5V CMOS logic levels.

7-74

,-----------------------------------------------------------------------------, r

i:

3.0 Applications Information (Continued)

"'T'I
.....
o

o

RIB
20k

. . - - - - Vour

....w.......... LPA

lPe
BPe
N/ AP/HP e

INVA

20k
5

INVe

SI A

U.tFIOO

20

R4B
20k

19

R3B
70.6k

18

R2B
19.7k

17

51 8
AGND

SAle
+IOV-"""1HH....""-I VA+

VA-

VD+

VD-

0.1

50/IOO/Cl
ClKA

ClK8

II

J1J'1. -t!:~=~====~~

CLOCK IN
fCLK = 100 kHz

__J

TL/H/5645-31

FIGURE 20. Fourth-order Chebyshev low-pass filter from example In 3.1. Single + 10V power supply. OV-5V TTL logic
levels. Input signals should be referred to half-supply or applied through a coupling capacitor.

v+

v+

....- ....-flYf-

...._--

~~-------.~ =5V

TYPICAL VALUES:
2k <:R <:100k
0.1 p.F <:C <:410 p.F

470k

__

~._.

V+

~--"--"----"2

TLlH/5645-33
TLlH/5645-32
TLlH/5645-34

(a) Resistive Divider with
Decoupllng Capacitor

(b) Voltage Regulator

(c) Operational Amplifier
with Divider

FIGURE 21. Three Ways of Generating V2+ for Single-5upply Operation

7-75

,.

C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
C)

....
LL

3.0 Applications Information

...J

3.2 SINGLE SUPPLY OPERATION

Typical values for these offsets with SAIB tied to V+ are:

The LMF100 can also operate with a single-ended power
supply. Figure 20 shows the example filter with a single-ended power supply. VA + and Vo + are again connected to the
positive power supply (4 to 15 volts), and VA - and Vo - are
connected to ground. The AGNO pin must be tied to V+ 12
for single supply operation. This half-supply point should be
very "clean", as any noise appearing on it will be treated as
an input to the filter. It can be derived from the supply voltage with a pair of resistors and a bypass capacitor (Figure
21a), or a low-impedance half-supply voltage can be made
using a three-terminal voltage regulator or an operational
amplifier (Figures 21b and 21c). The passive resistor divider
with a bypass capacitor is sufficient for many applications,
provided that the time constant is long enough to reject any
power supply noise. It is also important thatthe half-supply
reference present a low impedance to the clock frequency,
so at very low clock frequencies the regulator or op-amp
approaches may be preferable because they will require
smaller capacitors to filter the clock frequency. The main
power supply voltage should be clean (preferably regulated)
and bypassed with 0.1 p.F.

VOSI = opamp offset = ±5 mV
VOS2 = ±30 mV at 50:1 or 100:1

:5

(Continued)

Vosa = ±15 mV at 50:1 or 100:1
When SAIB is tied to V-, VOS2 will approximately halve.
The dc offset at the BP output is equal to the input offset of
the lowpass integrator (Vosa). The offsets at the other outputs depend on the mode of operation and the resistor ratios; as described in the following expressions.
Mode 1 and Mode 4

(6

VOS(N)

= VOSI

VOS(BP)

= Vosa
= VOS(N) - VOS2

VOS(lP)

+ 1 + IIHolPII) -

V~sa

Mode 1a
1)
VOS3
Vos(N.INV.BP) = ( 1 + Q VOS1 - Q
VOS(INV.BP)

= Vosa
= Vos(N.INV.BP) - VOS2

Vos(LP)

3.3 DYNAMIC CONSIDERATIONS

Mode 1b

The maximum signal handling capability of the LMF1 ~O, like
that of any active filter, is limited by the power supply voltages used. The amplifiers in the LMF100 are able to swing
to within about 1 volt of the supplies, so the input Signals
must be kept small enough that none of the outputs will
exceed these limits. If the LMF100 is operating on ± 5 volts,
for example, the outputs will clip at about 8Vp_p. The maximum input voltage multiplied by the filter gain should therefore be less than 8V Pop'
Note that if the filter Q is high, the gain at the lowpass or
highpass outputs will be much greater than the nominal filter
gain (Figure 6). As an example, a lowpass filter with a Q of
10 will have a 20 dB peak in its amplitude response at fa. If
the nominal gain of the filter (HOlP) is equal to 1, the gain at
fa will be 10. The maximum input signal at fa must therefore
be less than 800 mV p_p when the circuit is operated on ±5
volt supplies.

R2)
R2
R2
= VOSI ( 1 + - + - - Vosa
R3
R1
R3

VOS(N)

= Vosa

VOS(BP)

= VOS(N) _ VOS2

VOS(LP)

2

2

Mode 2 and Mode 5
2)
1
(R
Rp + 1 VOSI X 1 + R2/R4

VOS(N)

1
+ VOS2 1 +R4/R2

Vosa
Qv1 +R2/R4

Rp = R111R311R4
= Vosa
= VOS(N) - VOS2.

VOS(BP)
VOS(lP)

Also note that one output can have a reasonable small voltage on it while another is saturated. This is most likely for a
circuit such as the notch in Mode 1 (Figure 7). The notch
output will be very small at fa, so it might appear safe to
apply a large signal to the input. However, the bandpass will
have its maximum gain at fa and can clip if overdriven. If one
output clips, the performance at the other outputs will be
degraded, so avoid overdriving any filter section, even ones
whose outputs are not being directly used. Accompanying
Figures 7 through 17 are equations labeled "circuit dynamics", which relate the Q and the gains at the various outputs.
These should be consulted to determine peak circuit gains
and maximum allowable signals for a given application.

Mode 3
=VOS2
=Vosa

VOS(HP)
,VOS(BP)
VOS(lP)

= VOSI [1 + ::] - VOS2(::)
- \losa(::)
Rp = R111R211R3

Mode 6a and 6c

3.4 OFFSET VOLTAGE

The LMF1 ~O's switched capacitor integrators have a slightly
higher input offset voltage than found in a typical continuous
time active filter integrator. Because of National's new
LMCMOS process and new design techniques the internal
offsets have been minimized, compared to the industry
standard MF10. Figure 22 shows an equivalent circuit of the
LMF100 from which the output dc offsets can be calculated.

VOS(HP)

= VOS2

VOS(lP)

Ra
Ra)
R3
= VOSI ( 1 + - + - - VOS2
R2
Rl
R2

Mode6b
VOS(lP (N.INV))
VOS(lP (INV»)

7-76

r-

3.0 Applications Information

s::
"T1

(Continued)

......
o
o

LP

TL/H/5645-12

FIGURE 22. Offset Voltage Sources
In many applications, the outputs are ac coupled and dc
offsets are not bothersome unless large signals are applied
to the filter input. However, larger offset voltages will cause
clipping to occur at lower ac signal levels, and clipping at
any of the outputs will cause gain nonlinearities and will
change fo and Q. When operating in Mode 3, offsets can
become excessively large if R2 and R4 are used to make
fClK/fo significantly higher than the nominal value, especially if Q is also high.
For example, Figure 23 shows a second-order 60 Hz notch
filter. This circuit yields a notch with about 40 dB of attenuation a(60 Hz. A notch is formed by subtracting the bandpass output of a mode 3 configuration from the input using

the unused side B opamp. The Q is 10 and the gain is 1 VIV
in the passband. However, fCLKIfO = 1000 to allow for a
wide input spectrum. This means that for pin 12 tied to
ground (100:1 mode), R4/R2 = 100. The offset voltage at
the lowpass output (LP) will be about 3V. However, this is an
extreme case and the resistor ratio is usually much smaller.
Where necessary, the offset voltage can be adjusted by using the circuit of Figure 24. This allows adjustment of VOS1,
which will have varying effects on the different outputs as
described in the above equations. Some outputs cannot be
adjusted this way in some modes, however (VOS(BP) in
modes 1a and 3, for example).

R4
R3
R2
VIN

Rl

2
3

4

LPA

LPB

BPA

BPB

N/AP/HPA~N/AP/HPB

INVA
Sl A

-5V

SA/B
7

+5V
0.1 )'F
elK IN.n..n.
'clk=60kHz

VA+
Vo+

INVB
lMF100

Sl B
AGND
VA-

20

18

50/100

ClKA

elKs

---

17

RI

16

Rh

----

Rl
R2
- - -R3
R4
Rg
RI
Rh

=
=
=
=
=
=
=

100 kO
1 kO
100 kO
100 kO
10 kO
10 kO
10 kO

15
14

Vo-

lSh.

VOUT

19

-5V
0.1 )'F

TL/H/5645-39

FIGURE 23. Second-Order Notch Filter

7-77

I:)
I:)

u:::

:5

3.0 Applications Information

(Continued)
5V SUPPLY

-=

R3
TL/H/5645-13

FIGURE 24. Method for Trimming Ves
Another characteristic of sampled-data circuits is that the
output signal changes amplitude once every ~mpling period, resulting in "steps" in the output voltage which occur at
the clock rate (Figure 25). If necessary, these can be
"smoothed" with a simple R-C low-pass filter at the LMF100
output.
The ratio of fCLK to fe (normally either 50:1 or 100:1) will
also affect performance. A ratio of 100: 1 will reduce any
aliasing problems and is usually recommended for wideband input signals. In noise-sensitive applications, a ratio of
100:1 will result in 3 dB lower output noise for the same filter
configuration.
The accuracy of the fCLK/fo ratio is dependent on the value
of Q. This is illustrated in the curves under the heading
"Typical Performance Characteristics". As Q is changed,
the true value of the ratio changes as well. Unless the Q is
low, the error in fCLK/fo will be small. If the error is too large
for a specific application, use a mode that allows adjustment
of the ratio with external resistors.

3.5 SAMPLED DATA SYSTEM CONSIDERATIONS
The LMF100 is a sampled data filter, and as such, differs in
many ways from conventional continuous·time filters. An im·
portant characteristic of sampled·data systems is their ef·
fect on signals at frequencies greater than one-half the
sampling frequency. (The LMF100's sampling frequency is .
the same as its clock frequency.) If a signal with a frequency
greater than one-half the sampling frequency is applied to
the input of a sampled data system, it will be "reflected" to
a frequency less than one-half the sampling frequency.
Thus, an input signal whose frequency is f9/2 + 100 Hz will
cause the system to respond as though the input frequency
was f9/2 - 100 Hz. This phenomenon is known as "aliasing", and can be reduced or eliminated by limiting the input
signal spectrum to less than f8/2. This mai in some cases
require the use of a bandwidth-limiting filter ahead of the
LMF100 to limit the input spectrum. However, since the
clock frequency is much higher than the center frequency,
this will oilen not be necessary.

1110:1

50:1

TLlH/5645-35

FIGURE 25. The Sampled-Data Output Waveform

7-78

~National

Semiconductor

LMF380 Triple One-Third Octave
Switched-Capacitor Active fUteli
General Description
The LMF380 is a triple, one-third octave filter set designed
for use in audio, audiological, and acoustical test and measurement applications. Built using advanced switched-capacitor techniques, the LMF380 contains three filters, each
having a bandwidth equal to one-third of an octave in frequency. By combining several LMF380s, each covering a
frequency range of one octave, a filter set can be implemented that encompasses the entire audio frequency range
while using only a small fraction of the number of components and circuit board area that would be required if a conventional active filter approach were used. The center frequency range is not limited to the audio band, however.
Center frequencies as low as 0.125 Hz or as high as 25 kHz
are attainable with the LMF380.
The center frequency of each filter is determined by the
clock frequency. The clock signal can be supplied by an
external source, or it can be generated by the internal oscillator, using an external crystal and two capacitors. Since the
LMF380 has an internal clock frequency divider (+ 2) and
an output pin for the half-frequency clock signal, a single
clock oscillator for the top-octave LMF380 becomes the
master clock for the entire array of filters in a multiple
LMF380 application.

Accuracy is enhanced by close matching of the internal
components: the ratio of the clock frequency to the center
frequency is typically accurate to ± 0.5%, and passband
gain and stopband attenuation are guaranteed over the full
temperature range.

Features
II Three bandpass filters with one-third octave center fre-

quency spacing
iii Choice of internal or external clock
1:::1

No external components other than clock or crystal and
two capacitors

Key Specifications
Passband gain accuracy: Better than 0.7 dB over
temperature
III Supply voltage range: ±2V to ±7.5V or +4V to +14V
tl

Applications
t:l
[J
[J

Real-Time Audio Analyzers (ANSI Type E, Class II)
Acoustical Instrumentation
Noise Testing

Simplified Block Diagram

r

6
- ' OSClllATOR/ r-- XTAll
I IlEVEl SHIFT!:R~~XTAl2

llotF380

H

(DIVIDER (+ 2+

r!2- ClK OUT

tCLK

INl

IN2

IN3

11

J
I

12

14

.I

BANDP~SS 1
tal

= ~~K

~
BANDPASS 2
tCLK

'I

t02 = 62.5

J

BANDP~SS 3

l

.!.
t03

= ~~K

1

5

I
I

4

1
I

1

3

OUTl

•

OUT2

OUT3

TLlH/11123-1

7-79

Absolute Maximum Ratings

(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.3Vto +16V
Total Supply Voltage
Voltage at Any Pin
V- - 0.3VtoV+ + 0.3V
Input Current per Pin (Note 3)
Total Input Current (Note 3)

Power Dissipation (Note 5)

Surface Mount Package (Note 4)
, Vapor Phase (60 seconds)
Infrared (15 seconds)

215·C
220·C

2000V
"

Operating Ratings (Note 1)
Temperature Range
LMF380CIN, LMF380CIV,
LMF380CIJ
LMF380CMJ
Supply Voltage (V+ - V-I

Lead Temperature (Soldering 10 sec.)
300·C

-65·Cto + 15,,"C

ESD Susceptibility (Note 6)

±5mA
±20mA

Dual-In-Line Package (Plastic)

500mW
150·C

Maximum Junction Temperature
Storage Temperature Range

TMIN

:
-40·C s: TA S;' + 85·C
-55·C s: TA S:+125·C
4.0',(to 14V
,10 Hz to 1:2~ MHz

Clock Input Frequency

Filter Electrical Characteristics The following specifications apply for V+

s: TA s: TMAX

= + 5V, V- =' -5V, and fClK
TJ = 25·C.

= 320 kHz unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits apply forTA =
Typical
(Note 7)

Symbol

Parameter

fCLK:fOl

Clock-to-Center-Frequency Ratio, Filter 1

50:1
62.5:1

Conditions

fClK:f02

Clock-to-Center-Frequency Ratio, Filter 2

fCLK:f03

Clock-to-Center-Frequency Ratio, Filter 3

Al

Gain atfl = 3720 Hz (Filter 1),
2960 Hz (Filter 2), 2340 Hz (Filter 3)

(Note 9)

A2

Gain atf2 = 6080 Hz (Filter 1),
4820 Hz (Filter 2), 3820 Hz (Filter 3)

(Note 9)

Aa

Gain atf3 = 6200 Hz (Filter 1),
4960 Hz (Filter 2), 3940 Hz (F.ilter 3)

(Note 9

A4

Gain atf4 = 6400 Hz (Filter 1),
5080 Hz (Filter 2), 4040 Hz (Filter 3)

(Note 9)

A5

Gain atf5 = 6540 Hz (Filter 1),
5180 Hz (Filter 2),4120 Hz (Filter 3)

(Note 9)

Ae

Gain at fe = 6720 Hz (Filter 1),
5340 Hz (Filter 2), 4240 Hz (Filter 3)

(Note 9)

A7

Gain atf7 = 8900 Hz (Filter 1),
7060 Hz (Filter 2), 5600 Hz (Filter 3)

(Note 9)

Vas

Output Offset Voltage, Each Filter

En

Total Output Noise, OUT1
Total Output Noise, OUT2
Total Output Noise, OUT3

Cl

Limit
(Note 8)

Units
,(Umlt)

.,

80:1
"':30

dB (max)

+0.1

0.1 ± 0.7

dB (max)

0.0

-0.0 ± 0.7

dB (max)

-0_2

-0.2 ± 0.7

dB (max)

-0.1

-0.1 ± 0.'7

dB (max)

± 0.7

-20

dB (max)

+50

+120
-30

mV(max)
mV(min)
",Vrms

200

pF

-67

dB

10

mVp_
p

VIN

Clock Feedthrough, Each Filter,

V+ = +5V, V- = -5V

VOUT

Output Voltage Swing

Rl = 5kO

+4.2
-4.6

THD

Total Harmonic Distortion

VIN = 1 Vrms, f = fa

0.05

Is

Supply Current

fa

dB (max)

-22

Crosstalk

6.0

7-80

-0.15

240
210
190

Maximum Capacitive Load

= 1 Vrms, f =

-32

+0.15

0.1 Hz to 20 kHz

:

+3.8
-4.2

V (min)
V (max)

9.0

mA(max)

%

ris:

Logic Input and Output IElectrical Characteristics
The following specifications for V+ = + 5V and V- = -5V unless otherwise specified. Boldface limits apply for TWIIN to
TMAX; all other limits apply for TA = TJ = + 25°C.
Symbol

Parameter

Tested
Limit
(Note 8)

Units
(Limit)

-5V

+3.0
-3.0

V (min)
V (max)

OV

+8.0
+2.0

V (min)
V (max)

+1.5
-1.5

V (min)
V (max)

+4.0
+1.0

V (min)
V (max)

V+ -1.0
V- + 1.0

V (min)
V (max)

±20

p.A (max)

Logical "1"
Logical "0"

V+

=

5V, V-

Logical "1"
Logical "0"

V+

=

10V, V-

=

VIH
VIL

Logical "1"
Logical "0"

V+

=

2.5V, V-

=

VIH
VIL

Logical "1"
Logical "0"

V+

=

5V, V-

VIH
VIL
VIH
VIL

XTAl1
CMOS Clock
Input Voltage

VOH
VOL

Clock Output Logical "1"
Clock Output Logical "0"

liN

Input Current XTAL 1

Typical
(Note 7)

Conditions

lOUT
lOUT

=

=

= -1 mA
= +1 mA

-2.5V

OV

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed test conditions.

Note 2: All voltages are measured with respect to GND unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < V- or VIN > V +), the current at that pin should be limited to 5 mAo The 20 mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 4: See AN450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section titled "Surface Mount" found in any volume of the Linear
Data Book Rev. 1 for other methods of soldering surface mount devices.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is a function of TJmax, 8JA, and the ambient temperature, TA. The
maximum allowabla power dissipation at any temperature is Po = (TJmax - T AJI8JA or the number given in the Absolute Maximum Ratings, whichever is lower.
For guaranteed operation, TJmax = 125"C. The typical thermal resistance (8JAJ of the LMF380N when board-mounted is 51"C.W. 8JA is typically 5Z'C/W for the
LMF380J, and 86"C/W for the LMF380V.
Note 6: Human body model, 100 pF discharged through a 1.5 kG resistor.
Note 7: Typicals are at TJ

= 25"C and rapresent tha most likely parametric norin.

Note 8: Umits are guaranteed to National's Averge Outgoing Quality Level (AOQL).
Note 9: The nominal test frequencies are: fl = 0.58 fO, f2 = 0.95 fO, f3 = 0.98 fO, f4 = fO, f5 = 1.02 fO, f6 = 1.05 fo, and f7 = 1.39 fo.,The actual tast
frequencies listed In tha table ma), differ s1i911tl¥ from the nominal values.

7-81

~
CO
o

o

~

r-----------------------------------------------------------------------------,
Typical Performance Characteristics

:E
...I

Power Supply Current
vs Temperature
.

Power Supply Current
vs Power Supply Voltage
7

7

fCL~ = 320 kHz
TA =25OC

~-

feJ= 320 kH%

-

~~

Positive Output Swing
vs Load Resistance

I

TA= 2 ! #

Vs ~ t5V

Vs= :t'Y

1
1.=t2.5V

4
POWER SUPPLY VOLTAGE (tV)

TA=25°r

E

iii

I

....

-2

1111

RL =5kll

1111

vs= .t5Y

Vs =:l:2.5V

I
I
Vs= :l:5V

NJI
liT
1

100

~
~

~

-3
-4

TAO AMBIENT TEMPERATURE (OC)

Filter'

12JMI
TTi I

Offset Voltage
vs Clock Frequency
20

'CLK= 3

E

~~

20

V
/--,fi""'"

15

VS= t5V

.1

10

I

~

VS=t2·5V

II/ 1/

III LI

o
-55 -35 -15 5

2

SUPPLY VOLTAGE (tV)

Vs= :t5Y

TAo AMBIENT TEMPERATURE (DC)

20

TA =25°C
'elK = 320 kHz
30

o

I

Vs =:t2·5V

-2

Offset Voltage
vs Temperature

nlter'_L

10

iii

-55 -35 -15 5 25 45 65 85 105 125

Offset Voltage
vs Supply Voltage

>"
oS

E
"z

I 1/ 1/
1/1/1
1/ 1/ I

-5
-55 -35 -15 5 25 45 65 85 105 125

LOAD RESISTANCE (kJl)

40

RL =51d1

-1

o
10

100

Negative Output Swing
vs Temperature

III

Vs= t2.5V

-5

10
LOAD RESISTANCE (kll)

Positive Output Swing
vs Temperature

-3
-4

1

TAo AMBIENT TEMPERATURE (OC)

Negative Output Swing
vs Load Resistance
-1

11111
Lillll

o

4
-55 -35 -15 5 25 45 65 85 105 125

2

~

Ys= :l:2.5V

I
I

25 45 65 85 105 125

TAO AMBIENT TEMPERATURE (OC)

E

~

0

>

15

rllter1

J

TnT,

1111
Vs= t5V
10

1111

~

Vs =:l:2.5V

Tnl
o

IIII

100 300 500 700 900 1100 1300 1500 1700
CLOCK rREQUENCY (kHz)

TL/H/III23-4

7-82

1.0 p.F to 10.0 p.F tantalum capacitor
should also be used. For single-supply operation, connect this pin to system ground.

Connection Diagrams
Dual-In-Line Package
GND- 1

\....../

CLOCK OUT

This is the clock output pin. It can drive the
clock inputs (XTAL 1) of additional LMFSBOs
or. other components. The clock output frequency is one-half the clock frequency at
XTAL1.
These are the signal inputs to the filters.

This is the positive power supply pin. It
should be bypassed with at least a 0.1 p.F
ceramic capacitor. For best results, a 1.0
p.F to 10.0 p.F tantalum capacitor should
also be used.

161-V'

N.C.- 2

lSI-N.C.

QUT3- 3

141-IN3

OUT2- 4

13I-N.C.

QUT1- 5

121-IN2

XTAL1- 6

III-IN!

INPUT1,
INPUT2,
INPUT3

XTAL2- 7

10 I-CLK OUT

V+

V-- 8

9I-N.C.
TL/H/11123-2

Top View
Order Number LMF380CIJ, LMF380CMJ or LMF380CIN
See NS Package Number J16A or N16E

functional Description

The LMF3BO contains three fourth-order Chebyshev bandPlastic Chip Carrier Package
pass filters whose center frequencies are spaced one-third
of an octave apart, making it ideal for use in "real time"
audio spectrum analysis applications. As with other
switched-capacitor filters, the center frequencies are pro/
3 2 1 20 19
portional to the clock frequency applied to the IC; the center
OUT3 - 4
18 I- IN3
frequencies of the LMF3BO's three filters are located at
QUl2 - 5
17 I- N.C.
fCLK/50, fCLK/62.5, and fCLK/BO.
N.C.- 6
161-IN2
The three filters in an LMF3BO cover a full octave in frequency, so that by using several LMF3BOs with clock freOUTl- 7
15 I- N.C.
quencies separated by a factor of 2n, a complex audio proN.C.- 8
141-INI
gram can be analyzed for frequency content over a range of
9 10 11 12 13
several octaves. To facilitate this, the CLK OUT pin of the
LMF3BO supplies an output clock signal whose frequency is
one-half that of the incoming clock frequency. Therefore, a
single clock source can provide the clock reference for all of
TLlH/11123-3
the 30 filters (10LMF3BOs) in a real time analyzer that covTop View
ers the entire 10-octave audio frequency range. The
LMF3BO contains an internal clock oscillator that requires
Order Number LMF380CIV
an external crystal and two capacitors to operate. Sin@~
__ ~ ____~S=e=e~N=S~P~acJs_age_Num_ber_'l20A _
~------~-"cIOcKCIlvlder IS on-board, only a single crystal is needed for
the top-octave filter chip; the remaining devices can derive
Pin Description
their clock signals from the master. If desired, an external
GND
This is the analog ground reference for the
oscillator can be used instead.
LMF3BO. In split supply applications, GND
Figure 1 shows the magnitude versus frequency curves for
should be connected to the system ground.
the three filters in the LMF3BO. Separate input and output
When operating the LMF3BO from a single
pins are provided for the three internal filters. The input pins
positive power supply voltage, pin 1 should
will normally be connected to a common signal source, but
be connected to a "clean" reference voltcan also be connected to separate input signals when necage midway between V+ and V-.
essary.
N.C.

These pins are not connected to the internal circuitry.

OUT1, OUT2,

These are the outputs of the filters.

0

OUTS
XTAL1

XTAL2

V-

'in'

This is the crystal oscillator input pin. When
using the internal oscillator, the crystal
should be tied between XTAL 1 and XTAL2.
XTAL 1 also serves as the input for an external CMOS-level clock.
This is the output of the internal crystal
oscillator. When using the internal oscillator, the crystal should be tied between
XTAL1 and XTAL2.

~

z
::;:

'"

,.

J YIVI\

1 /\/\
L J

-10

I

-20

I

~

II I I 1\ ,

1\

I V

-30

/ 1/1
,

-40
1000

10000
FREQUENCY (Hz)

This is the negative power supply pin. It
should be bypassed with at least a 0.1 p.F
ceramic capacitor. For best results, a

TL/H/11123-6

FIGURE 1. Response curves for the three filters in the
LMF380. The clock frequency is 250 kHz.
7-B3

_~~_ _

C)
CI)

~
::;

r---------------------------------------------------------------------------------,
Applications Information
POWER SUPPLIES
100:1

The LMF380 can operate from a total supply voltage (V+ V-) ranging from 4.0V up to 14V, but the choice of supply
voltage can affect circuit performance. The IC depends on
MaS switches for its operation.'AIi such switches have inherent "ON" resistances, which can cause small delays in
charging internal capacitances. Increasing the supply voltage reduces this "ON" resistance, which improves the accuracy of the filter in high-frequency applications. The maximum practical center frequency improves by roughly 10% to
20% when the supply voltage increases from 5V to 10V.

50:1

TL/H/11123-8

Dynamic range is also affected by supply voltage. The maximum signal voltage swing capability increases as supply
voltage increases, so the dynamic range is greater with
higher power supply voltages. It is therefore recommended
that the supply voltage be kept near the maximum operating
voltage when dynamic range andlor high-fr/lquency performance.are important.
'

FIGURE 2. Swltched-Capacltor Filter Output Waveform.
Note the sampling "steps".
ALIASING
Another important characteristic of sampled-data systems is
their effect on signals at frequencies greater than one-half
the sampling frequency, fs. (The LMF380's sampling frequency is the same as the filter clock frequency). If a signal
with a frequency greater than one-half the sampling frequency is applied to the input of a sampled-data system, it
will be "reflected" to a frequency less than one-half the
sampling frequency. Thus, an input signal whose frequency
is f8/2 + 10Hz will cause the system to respond as though
the input frequency was f8/2 - 10Hz. If this frequency
happens to be within the passband of the filter, it will appear
at the filter's output, even though it was not present in the
input signal. This phenomenon is known as "aliasing". Aliasing can be reduced or eliminated by limiting the input signal spectrum to less than f8/2. In some cases, it may be
necessary to use a bandwidth-limiting filter (often a simple
passive RC low-pass) between the signal source and the
switched-capacitor filter's input. In the application example
shown in Figure 3, two LMF60 6th-order low-pass filters provide anti-aliasing filtering.

As with all switched·capacitor filters, each of the LMF380's
power supply pins should be bypaSsed with a minimum of
0.1 ,..F located close to the chip. An additional 1 ,..F to
10 ,..F tantalum capacitor on each supply pin is recommended for best results.
'

Sampled-Data System
Considerations
CLOCK CIRCUITRY
The LMF380's clock input Circuitry accepts an external
CMOS-level clock signal at XTAL1, or can serve as a selfcontained oscillator with the addition of an external 1 MHz
crystal and two 30 pF capacitors (see Figure 3).
The Clock Output pin provides a clock Signal whose frequency is one-half that of the clock signal at XTAL1. This
allows multiple LMF380s to operate from a single internal or
external clock oscillator.

OFFSET VOLTAGE
Switched-capacitor filters often have higher offset voltages
than non-sampling filters with similar topologies. This is due
to charge injection from the MaS switches into the sampling
and integrating capaCitors. The LMF380's offset voltage
ranges from a minimum of -30 mV to a maximum of
+120 mY.

CLOCK FREQUENCY LIMITATIONS
The performance characteristics of a switched-capacitor filter depend on the switching (clock) frequency. At very low
clock frequencies (below 10Hz), thl;! time between clock
cycles is relatively long, and small parasitic leakage currents
cause the internal capaciiors to discharge sufficiently to affect the filter's offset voltage and gain. This effect becomes
more pronounced at elevated operating temperatures.

NOISE
Switched-capacitor filters have two kinds of noise at their
outputs. There is a random, "thermal" noise component
whose amplitude is typically on the order of 210 p.V. The
other kind of noise is digital clock feedthrough. This will
have an amplitude in the vicinity of 10 mV peak-lo-peak. In
some applications, the clock noise frequency is so high
compared to the signal frequency that it is unimportant. In
other cases, clock noise may have to be removed from the
output signal with, for example, a passive low-pass filter at
the LMF380's output (see Figure 4).

At higher clock frequencies, performance deviations are
due primarily to the reduced time available for the internal
operational amplifiers to settle. For this reason, when the
filter clock is externally generated, care should be taken to
ensure that the clock waveform's duty cycle is as close to
50% as pOSSible, especially at high clock frequencies.
OUTPUT STEPS
Because the LMF380 uses switched-capacitor techniques,
its performance differs in several ways from non-sampled
(continuous) circuits. The analog signal at any input is sampled during each filter clock cycle, and since the output voltage can change only once every clock cycle, the result is a
discontinuous output signal. The output Signal takes the
form of a series of voltage "steps", as shown in Figure 2 for
clock-to-center-frequency ratios of 50:1 and 100:1.

INPUT IMPEDANCE
The LMF380's input pins are connected directly to the internal biquad filter sections. The input impedance is purely capacitive and is approximately 6.2 pF at each input pin, including package parasitics.

7-84

.-----------------------------------------------------------------------------,~

iii:

Typical Applications

~

m

lMHz

30 F

C)

~1;llrpI3~

-

=
==
=
=
=
==
==
=
=
=
=
=------=

11
12
14

LNF380 .

5
4
3

20 kHz BANO OUT
16 kHz BAND OUT
12.5 kHz BAND OUT

500 kHzl~O
11
12
14

LMF380

5
4
3

10 kHz BAND OUT
8 kHz BAND OUT
6.25 kHz BAND OUT

250 kHzll0
6
11
12
14

r

8

12

3

11

LMF60-100

12

Jl7

14

-5V

3

5 kHz BAND OUT
4 kHz BAND OUT
3.13 kHz BAND OUT

125 kHz I~O
•.
6

ig"fe = 2.5 kHz

,

tM;;O-

5
4

LMF380

5
4
3

2.5 kHz BAND OUT
2 kHz BAND OUT
1.56 kHz BAND OUT

62.5 kHz I~O

-

11
12
14

LMF380

5
4
3

1.25 kHz BAND OUT
1kHz BAND OUT
781 Hz BAND OUT

31.25 kHz I~O

11
12
14

------- ----------

-~----

LMF380

11
14

r

-5V

,

LMF60-100
E7

-

~
3 Ie = 312 Hz

3

625 HZ BAND OUT
500 Hz BAND OUT
391 Hz BAND OUT

-15:625 ~Hz I ~O ,----- - - - - - - - - -

12
8

5
4

LMF380

5
4
3

---------I----~

313 Hz BAND OUT
250 Hz BAND OUT
195 Hz 'BAND OUT

7.8125 kHzl~O

11
12
14

LMF380

5
4
3

156 Hz BAND OUT
125 Hz BAND OUT
97.7 Hz BAND OUT

3.90625 kHzl~O
11
12
14

LMF380

5
4
3

78.1 Hz BAND OUT
&2.5 Hz BAND OUT

•

48.8 Hz BAND OUT

1.953125 kHzl~O

,::;::;

11
12
14

-

LMF380

5
4
3

39.1 Hz BAND OUT
31.3 Hz BAND OUT
24.4 Hz BAND OUT
TUH/11123-7

FIGURE 3. Complete, one-third octave filter set for the entire audio frequency range. Ten LMF380s provide the thirty
bandpass filters required for this function. Power supply connections and bypass capacitors are not shown. Pin
numbers are for the dual-In-Ilne package.

7-85

O'-------------------------------------------------------------~

co
C')

u.

:IE
....I

Typical Applications (Continued)
tional to the peak signal voltage, it provides a good indication of the voltage swing. Generally, the output of the peak
detector must have a moderately fast (about 1 ms) attack
time and a much slower (tens or hundreds of milliseconds)
decay time. The actual attack and decay times depend on
the expected application. An average detector responds to
the average value of the rectified input signal and provides a
good solution when measuring random noise. An average
detector will normally respond relatively slowly to a rapid
change in input amplitude. An rms detector gives an output
that is proportional to signal power, and is therefore useful
in many instrumentation applications, especially those that
involve complex signals.

THIRD-OCTAVE ANALYZER FILTER SET
The circuit shown in Figure 3 uses the LMF380 to implement a Va-octave filter set for use in "real time" audio program analyzers. Ten LMF380s provide all of the bandpass'
filtering for the full audio frequency range. The power supply
connections are not shown, but each power supply pin
should be bypassed with a 0.1 /-LF ceramic capacitor in parallel with a 1 /-LF tantalum capacitor.
The first LMF380, at the top of Rgure 3, handles the highest
octave, with center frequencies of 20 kHz, 16 kHz, and
12.6 kHz. It also contains the 1 MHz master clock oscillator
for the entire system. Its Clock Out pin provides a 500 kHz
clock for the second LMF380, which supplies 250. kHz to
the third LMF380, and so on.

Peak detectors and average-responding detectors require
precision rectifiers to convert the bipolar input signal into a
unipolar output. Half-wave rectifiers are relatively inexpensive, but respond to only one polarity of input signal; therefore, they can potentially ignore information. Full-wave rectifiers need more components, but respond to both polarities
of input'signal. Examples of half- and full-wave peak- and
average-responding detectors are shown in Figure 4. The
component values shown. may need to be adjusted to meet
the requirements of a particular application. For example,
peak detector attack and decay times may be changed by
changing the value of the "hold" capacitor.

If the audio input signal were applied to all of the LMF380
input pins, aliasing might occur in the lower frequency filters
due to audio components near their clock frequencies. For
example, the LMF380 at the bottom of Figure 3 has a clock
frequency equal to 1.953125 kHz. An input signal at
1.93 kHz will be aliased down to 23.125 Hz, which is near
the band center of the 24.4 Hz bandpass filter and will appear at the output of that filter.
This problem is solved by two LMF60-100 6th order Butterworth low-pass filters serving as anti-aliasing filters, as
shown in Figure 3. The first LMF60-1 00 is connected to the
input signal. The clock for this LMF60 is 250 kHz and comes
from pin 10 of the second LMF380. The cutoff frequency is
therefore 2.5 kHz. The output of this firSt LMF60-1 00 drives
the inputs of the fifth, sixth, and seventh LMF380s. The seventh LMF380 has a 15.625 kHz clock, so aliasing will begin
to become a problem around 15.2 kHz. With a sixth-order,
2.5 kHz low-pass filter preceding this circuit, the attenuation
at 15.2 kHz is theoretically about 94 dB, which prevents
aliaSing from occuring at this bandpass filter.
.

The input to each detector should be capacitively-coupled
as shown in Figure 4. This prevents any errors due to voltage offsets in the preceding circuitry. The cutoff frequency
of the resulting high-pass filter should be less than half the
center frequency of the band of interest.
Note that a passive low-pass filter is shown at the input to
each detector in Figure 4. These filters attenuate any clockfrequency signals at the outputs of the third-octave
switched-capacitor filters. The typical clock feedthrough at a
filter output is 10 mV rms, or 40 dB down from a nominal
1 Vrms signal amplitude. When more than 40 dB dynamic
range is needed, a passive low-pass filter with a cutoff frequency about three times the center frequency of the bandpass will attenuate the clock feedthrough by about 24 dB,
yielding about 64 dB dynamiC range. The component values
shown produce a cutoff frequency of 1 kHz; changing the
capacitor value will alter the cutoff frequency in inverse proportion to the capaCitance.

The output of the first LMF60 also drives the input of the
second LMF60, which provides anti-aliasing filtering for the
three LMF380s that handle the lowest part of the audio fre~
quency spectrum.
Note that no anti-aliasing filtering is provided for the four
LMF380s at the top of Figure 3. These devices will not encounter aliasing problems for frequencies below about
120 kHz; if higher input frequencies are expected, an additional low-pass filter at VIN may be required.

The offset voltage of the operational amplifier used in the
detector will also affect the detector's dynamic range. The
LF353 used in the circuits in Figure 3 is appropriate for systems requiring up .to 40 dB dynamic range.

DETECTORS
In a real-time analyzer, the amplitude of the signal at the
output of each filter is displayed, usually in "bar-graph"
form. The AC signal at the output of each bandpass filter
must be converted to a unipolar signal that is appropriate for
driving the display circuit.
.

DISPLAYS
The output of the detector will drive the input of the display
circuit. An example of an LEO display driver using the
LM3915 is shown in Figure 5. The LM3915 drives 10 LEOs
with 3 dB steps between LEOs; the total display range for an
LM3915 is therefore 27 dB. Two LM3915s can be cascaded
to yield a total range of 57 dB. See the LM3915 data sheet
for more information.

The detector can take any of several forms. It can respond'
to the peaks of the input Signal, to the average value, or to
the rms value. The best type of detector depends on the'
application. For example, peak detectors are useful when
monitoring audio program signals that are likely to overdrive
an amplifier. Since the output of the peak detector is propor-

7-86

r-----------------------------------------------------------------------------, r

==
~

Typical Applications (Continued)
(a)

~

(b)

100kO

100kO

TLlH/11123-9
TLlH/11123-10

(c)
100 kll 1%

100 kll
1%
210kll

200 kll 1%

TL/H/11123-11

(d)
100kO 1%

-----~~----VIN

=f _9.1kll _ _ _10llk1l_~

-

- - - - ---

~--~~--------------I-----

C1N 0.02)1F
100 kll
1%

200 kO 1%

>~""'-VOUT

TL/H/11123-12

FIGURE 4. Examples of detectors for audio signals. (a) Half-wave peak detector. (b) Half-wave average detector.
(c) Full-wave peak detector. (d) Full-wave average detector. All diodes are 1N914 or 1N4148.lnput RC low-pass filters
attenuate clock noise from switched-capacitor filters; values shown are for 1 kHz cutoff frequency. CIN should be at
least 0.27 ,...F for frequency bands below 50 Hz and 0.1 ,...F for higher frequencies. Power supplies (not shown) should
be bypassed with at least 0.1 ,...F close to the amplifiers.

7-87

•

i

~

:;

Typical Applications

(Continued)
+5V

. 2.2 JLF Tantalum +
or 10 JLF Aluminum
electrolytic .'

L~3915

TUH/11123-13

FIGURE 5. LED display using LM3915 bar graph driver. The Input voltage range Is 2V full-scale, with 3 dB per step.

7-88

t!lNational Semiconductor

MF4 4th Order Switched Capacitor Butterworth
Lowpass FUter
General Description

Features

The MF4 is a versatile, easy to use, precision 4th order
Butterworth low-pass filter. Switched-capacitor techniques
eliminate external component requirements and allow a
clock-tunable cutoff frequency. The ratio of the clock frequency to the low-pass cutoff frequency is internally set to
50 to 1 (MF4-50) or 100 to 1 (MF4-100). A Schmitt trigger
clock input stage allows two clocking options, either selfclocking (via an external resistor and capacitor) for standalone applications, or for tighter cutoff frequency control an
external TTL or CMOS logic compatible clock can be applied. The maximally flat passband frequency response together with a DC gain of 1 VIV allows cascading MF4 sections together for higher order filtering.

• Low Cost
• Easy to use
II 8-pin mini-DIP or 14-pin wide-body S.O.
• No external components
III 5V to 14V supply voltage
• Cutoff frequency range of 0.1 Hz to 20 kHz
• Cutoff frequency accuracy of ± 0.3%· typical
• Cutoff frequency set by external clock
II Separate TTL and CMOS/Schmitt-trigger clock inputs

Block and Connection Diagrams
Dual-In-Llne Package
ALTER

CLKIN
ALTER
OUT

IN

CLKH
L. Sh

yy+

IN

AGND

TLIH/S064-2

4TH ORDER
BUTTERWORTH
LOWPASS FILTER

ALTER

y-

Order Number MF4CN-50
or MF4CN-100
See NS Package Number NOSE

LJr--"-+--'"
Small-Outline
Wide-Body Package
CLKIN

CLKR

L. Sh
TLIH/S064-1

14

FILTER IN

NC

2

13

NC

CLKR

3

12

y+

NC

4

11

NC

L. SH

5

10

AGND

NC

6

9

NC

V-

7

a

FILTER OUT
TLIH/S064-2S

Top View
Order Number MF4CWM-50
or MF4CWM-100
See NS Package Number M14B

7-89

,.

Soldering Information:

Absolute Maximum Ratings (Notes 1,2)

260'C
215'C
• SO Package: Vapor Phase (60 sec.)
Infrared (15 sec.)
220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

• .N Package: 10 sec.

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V+ -V-)
14V
V+ + 0.2V
Voltage At Any Pin
V- - 0.2V
Input Current at Any Pin (Note 14)
Package Input Current (Note 14)
Power Dissipation (Note 15)
Storage Temperature
ESD Susceptibility (Note 13)

Operating Ratings

5mA
20mA
500mW
150'C
BOO V

(Note 2)

Temperature Range
MF4CN-50, MF4CN-100
MF4CWM-50, MF4CWM-100
Supply Voltage (V+ -V-)

Tmin
O"C
O'C

:s; TA
:s; TA
:s; TA

:s; Tmax
:s; 70'C
:s; 70'C

5Vto 14V

Filter Electrical Characteristics The following specifications apply for fCLK :s; 250 kHz (see Note 5) unless
otherwise specifij;ld. Boldface limits apply for TMIN to TMAX: all other limits TA = TJ = 25·C.
MF4-50
Parameter

Conditions

MF4-100

Tested
Design
Tested
Design
Typical
Typical
Limit
Limit
Limit
Limit
(Note 10)
(Note 10)
(Note 11) (Note 12)
(Note 11) (Note 12)

Unit

Y+"= +5Y, Y- = -5Y
fe, Cutoff Frequency
Range (Note 3)

I

Min
Max

Supply Current
Maximum Clock
Feedthrough
(Peak-to-Peak)

0.1
20k
felk = 250 kHz

Filter Output

3.5

Rsource :s; 2 kO

fClk/fc Temperature
Coefficient
at2fc

0.0

±0.15

49.96
±0.3%

49.96
±1%

±0.15

3.5

mA

-25.0

RL = 10kO

I

+4.0
-4.5

-24.0

-24.0

Dynamic Range (Note 4)

0.0

±0.15

99.09
±0.3%

99.09
±1.0%

±0.15

-25.0

+3.5
-4.0

+3.5
-4.0

80
f = 6000 Hz

-7.57
±0.47

-7.57
±0.47

f = 4500Hz

-1.44
±0.12

-1.44
±0.12

+4.0
-4.5

-24.0

-24.0

dB
mV

+3.5
-4.0

+3.5
-4.0

V
V

50
1.5

mA
mA

82

dB

dB

f = 3000Hz

-7.21
±0.2

-7.21
±0.2

f = 2250Hz

-1.39
±0.1

-1.39
±0.1

7-90

dB

ppml"C

-400

50
1.5

Source
Sink

mV

±30

-200

DC Offset Voltage
Minimum Output Swing

3.5

25

±15

Stopband Attenuation (Min)

2.5

Hz

Yin = OV

felk/fe, Clock to Cutoff
Frequency Ratio

Additional Magnitude
Response Test Points
(Note 6)
fclk = 250 kHz

3.5

25

Ho, DC Gain

Output Short Circuit
Current (Note B)

2.5

0.1
10k

dB

Filter Electrical Characteristics

The following specifications apply for feLK :s:; 250 kHz (see Note 5) unless
otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25·C. (Continued)
MF4-50
Parameter

Conditions

MF4-100

Design
Design
Tested
Tested
Typical
Typical
Limit
Limit
Limit
Limit
(Note 10)
(Note 10)
(Note 11) (Note 12)
(Note 11) (Note 12)

Unit

Y+ = +2.5Y, Y- = -2.5Y
fc Cutoff Frequency
Range (Note 3)

I

min
max

0.1
10k

Supply Current

fclk = 250 kHz

1.5

Maximum Clock
Feedthrough
Filter Output
(Peak-to-Peak)

Vin = OV

15

Ho.DCGain

Rsource :s:; 2 kO

2.25

0.0

±0.15

50.07
±0.3%

50.07
±1.0%

feLK/fe Temperature
Coefficient

±25
-25.0

at2fc

±0.15

Minimum Output Swing

RL = 10kO

+1.S
-2.2

I

Source
Sink

Dynamic Range (Note 4)
Additional Magnitude
Response Test Points
(Note 6)
(fc = S kHz)
- Magnitudellr----

2.25

0.0

±0.15
99.16
±1.0%

rnA

±0.15

±60
-24.0

-24.0

+1.0
-1.7

+1.0
-1.7

dB

ppml"C

-25.0

-24.0

-24.0

+1.0
-1.7

+1.0
-1.7

-300

dB
mV

+1.S
-2.2

V
V

28
0.5

28
0.5

rnA
rnA

78

78

dB

fclk = 250 kHz

f = 6000 Hz
f = 4S00Hz

-7.57
±0.47

-7.57
±0.47

dB

-1.46
±0.12

-1.46
±0.12

dB

f = 3000 Hz

(fc = 2.5 kHz)
Magnitude

2.25

mV

99.16
±0.3%

-1S0

DC Offset Voltage

Output Short Circuit
Current (Note 8)

1.5

Hz

15

fclk/fc. Clock to Cutoff
Frequency Ratio

Stopband Attenuation (Min)

2.25

0.1
5k

f =.2250 Hz

-7.21
±0.2

-7.21
±0.2

-1.39
±0.1

-1.39
±O.1

dB

Logic Inp.ut-Output Characteristics

The following specifications apply for V- = OV (see Note 7) unless
otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 2S·C.
Parameter

Conditions

Typical
(Note 10)

Tested
Limit
(Note 11)

Design
Limit
(Note 12)

Unit

SCHMITT TRIGGER
VT+. Positive GOing Threshold
Voltage

Min
Max

V+ = 10V

Min
Max

V+ = SV

7.0
3.S

7-91

6.1

6_1

8.9
3.1
4.4

3.1
4.4

V
V

Logic Input-Output Characteristics The following specifications apply for Votherwise specified. Boldface limits apply for T MIN to T MAX; all other limits T

Parameter

Conditions

A= t.J =

= OV (see Note 7) unless

25'C. (Continued)

Typical
(Note 10)

Tested

Design

, limit

Umlt

(Note 11)

(Note 12)

1.3

1.3
3.8

Unit

SCHMITT TRIGGER (Continued)
V T -. Negative Going Threshold

Min

Voltage

Max
Min

V+ = 10V

3.0

Min

V

2.3
7.6

V

3.8

1.2
3.8

V

V+ = 10V

9.0

9.0

V

V+ = 5V

4.5

4.5

V

V+ =,10V

1.0

1.0

V

V+ = 5V

0.5

0.5

V

1.5

V+ = 10V

4.0

Max
Min

V+ = 5V
2.0

Max
Minimum logical "1" Output Voltage

10 =

-10/LA

(pin 2)
Maximum logical "0" Output Voltage

lo= IO /LA

(pin 2)
Minimum Output Source Current

ClK R Shorted

(pin 2)

to Ground

Maximum Output Sink Current

ClK R Shorted

(pin 2)

toV+

V

0.6
1.9

V+ = 5V

Max
Hysteresis (VT+-VT -)

3.8
0.6
1.9
2.3
7.6
1.2

V+ = 10V

6.0

3.0

3.0

mA

V+ = 5V

1.5

0.75

0.75

mA

V+ = 10V

5.0

2.5

2.5

mA

V+ = 5V

1.3

0.65

0;65

mA

TTL CLOCK INPUT, ClK R PIN (Note 9)
Maximum VIL. logical "0" Input Voltage

0.8

Minimum VIH. logical "1" Input Voltage

2.0

V

2.0

/LA

Maximum leakage Current at ClK R Pin

L. Sh Pin at Mid-Supply

V

Note 1: Absolule Maximum Ratings indicalellmlls beyond which damage 10 Ihe device may occur. AC and DC electrical specifications do not apply when operating
Ihe device beyond ils specilled operating condiIJons.
Note 2: All voltages are wilh respect 10 GND.
Note 3: The culoff frequency 01 Ihe filter is defined as the Irequency where Ihe magnilude response is 3.Q1 dB less than the DC gain 01 the Iilter.
Note 4: For ±SV,supplies the dynamic range is relerenced 10 2.82 Vrms (4V peak) where the wideband noise over a 20 kHz bandwldlh Is typically 280 ,.Vrms lor
Ihe MF4·S0 and 230 ,.Vrmslor Ihe MF4·100. For ± 2.SV supplies the dynamic range is relerenced to 1.06 Vrms (1.SV peak) where Ihe wldeband noise over a 20
kHz bandwldlh Is typically 130 ,.Vrms lor both the MF4·S0 and the MF4·100.
Note 5: The specifications lor the MF4 have been given lor a clock Irequency (Icud 01 2S0 kHz or less. Above ths clock frequency Ihe cutoff lrequency begins to
deviale Irom the specified error band 01 ± 0.6"!'o but the filler slill maintains ils magnHude characterislics. See Application Hints.
Note 6: Besides checking the cutoff frequency (fel and the stopband attenuation at 2 fe, two addHionai'lrequencies are used 10 check Ihe magnilude response of
Ihe filter. The magnHudes are referenced 10 a DC gain of 0.0 dB.
Note 7: For simplicity alilhe logic levels have been relerenced to Vand ± 2.SV supplies,

= OV (except lor Ihe TIL input logic levels). The logic levels will scale accordingly for ±SV

Note 8: The short circuil source current is measured by forCing the oulpulthat is being tested to Its maximum positive voltage swing and then shorting that output to
the negative supply. The short circuit sink current Is measured by forcing the oulpulthat Is being tested to its maximum negative voltage and then shorting that
oulput to the positive supply. These are worst case condHions.
Note 9: The MF4 Is operating with symmetrical splH supplies and L. Sh is tied to ground,
Note 10; Typicals are at2S'C and represent most likely parametric norm.
Note 11: Guaranteed to National's Average Oulgoing Quality Level (AOOL).
Note 12: Guaranteed, but not 100% production tested. These limits are not used to determine outgoing quality levels.
Note 13: Human body model; 100 pF discharged through a I.S kG resistor,
Note 14: When the inpul voltage (YiN) at any pin exceeds the power supply rails (VIN < V- or VIN > V+) the absolute value 01 current at ttiat pin should be limited
to,S rnA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a S mA current limit to four.
Note 15: Thermal Resistance

8JA (Junction to Ambient) N Package, .• , ....... 105'C/W.
8JA M Package .............. , •••.......•••••• 95'C/W.

7-92

Typical Performance Characteristics
Power Supply Current
vs Power Supply Voltage
TA=25CC ,I,

4D

'£?

I

FCLJ( = 250 kHz

3.6

I

I

II

l2

2.11

V

I

V

1.6

3.4

~

I..J...-'

~

~

15

I" 100

...,1-"

I

I

V

i'...

I/"
s.o

5.5 6.0 6.5 7/J

""
""'

2.5 3.0 3.5 4D 04.5

s.o

Negative Voltage Swing
vs Temperature

~=10kll

,
:

z

01.10

III

4D5

!:l

3.55

~

3SO

~

Q.2

"

25

85

"

TA=25ocL
-FCLK=250kHz
WF4- 100

\

0.1

\ j\

11.

0.0

-o.z

125

!.,..oo .......

.....

1

... c-

I

Vs=t5,OV'

1

MF4-100
TAj+2SCC

-S
1
100

.

/
I'

-IS

25

B5

125

TEMPERATURE(CC)

fCLK/fe Deviation
vs Power Supply Voltage
Q.2

-

..

I. ,

TA=25CCL
. FctJ(=250kHz
WF4-50

----

0.1

.1

-

I'"

s.o

-o.z

5.5 6.0 6.5 7/J

2.5 3.0 3.5 4D 04.5

s.o

5.5 6.0 6.5 7/J

POWER SUPPLY VOLTAGE (tv)

fCLK/fe Deviation
va Temperature
0.&

16
14
12
10

II
r;
I'
I'-~
=hs~-'
C-

-3

/

-ss

fCLK/fe Deviation
vs Clock Frequency

.vr:
IS

-- -

1/
/

3.65
3.80

POWER SUPPLY VOLTAGE (tv)

IIA

-2

I I

RLOAO= 10kll

0.0

~

2.5 3.0 3.5 4D 04.5

fCLKlfe Deviation
vs Clock Frequency

I..

125

-0.1

TEMPERATURE (CC)

-I

85

Q.3

..- - - - - - - -

~

-- -

I

25

VS=i5.OV
I
FCIJ(=250kHz

r-

5.5 6.0 6.5 7/J

-0.1

-IS

I

r-

oUXI

~

fCLK/fe Deviation
vs Power Supply Voltage

III

/

-55

I

-IS

Positive Voltage Swing
vs Temperature

Q.3

,
,,

Vs -U.5V

~

POWER SUPPLY VOLTAGE (tv)

POWER SUPPLY VOLTAGE(tVJ

_V~=~5~1·J
FCLJ(= 250 kHz

~

-55

~

II I I

2.5 3.0 3.5 4D 04.5

1.8
1.6
1.4

~ 01.15
to

,

~=10kll

.... --

TEMPERATURE(CC)

TA=2So
FCIJ(=2S0kHz

J

I

Vs=iS.OV

.

2.2
2.0

4.20

~

V

I

1000

500

V

FCLJ( =250kHz

~

2

,/

/

,

3.0
2.11
2.6
2.4

1.2

Negative Voltage Swing
vs Power Supply Voltage

r

.

~

Vs =U,5V

Positive Voltage Swing
vs Power Supply Voltage

,I.

§
~

'"
CLOCK FREQUENCY (kHz)

TA =2SOJ
r-FCLJ(= 250 kHz
RLOAO=10k4

l2

]:
0

POWER SUPPLY VOLTAGE(iVJ

6

-.4.30

TA =25CC

i'

1.8
1.6

5.5 6.0 6.5 7/J

Power Supply Current
vs Temperature

......

2.6
2.4

1/

s.o

2.5 3.0 3.5 4D 04.5

I
I
vs =t5·oY.,..

I

~

2.0

Power Supply Current
vs Clock Frequency

,

1\

1
500

CLOCK FREOUENCY (kHz)

1000

I..

Q.4

I

8
6
4
2

- e- 11

Vs=USV

o

WF4-S0
TA=+2SCC

e- - e~=tS.OV

...
-2

:x

I.

0.0

-o.z

500
CLOCK FREQUENCY (kHz)

1000

Vs=i5.0~

.J..{'

.

ro..vs=u.sv

"'

-Q.4

-0.&

'.

-u.s
-1.0

100

MF4-1001 1
FctJ(=250kHz

Q.2

-ss

-IS

25

85

125

TEMPERATURE(CC)
TL/H/5064-9

7-93

fI

~
:IE

Typical Performance Characteristics

DC Gain Deviation
Power Supply Voltage

felK/fe Deviation
VB Temperature
0.04

MF4-50 I
fa.JC= 250 kH

0.1

I :,

;.'

--r -

......1\

.

-G.4

-0.G4

\
~

-15

as

25

..,..

~ -0.G2

1-0.04
a; -0.06
~

!:!

-0.08
-0.1

.:s.

0.01

D
a;

-0.01

~ -0.02

-0.05
2.5 3.0 3.5 4.G 4.5 5.0 5.5 6.0 6.5 7.0

2.5 3.0 3.5 4.G 4.5 5.0 5.5 6.0 6.5 7.0

POWER SUPPLY VOLTAGE (tv)

POWER SUPPLY VOLTAGE (*V)

DC Gain Deviation

DC Gain Deviation
VB Temperature

.AI
I
I '\"I...Vs=U.OV

0.12

~

-~

\
\

I
I

I
I

-55

-15

lD'

.....

V;=U.5Y\

MF4-50
fa.JC= 250 kHz

...... ....

~

!!l
z

0.08

-<

0.06

z

0.G4

!:!

0.02

G

i1

.

0.10

,

,

MF4-100
fa.JC = 250 kHz

.
-

,

,

V.=U.5V I-, ' -

......

.

s=U.ov

-0.02
25

I """
II

-o.G4

VB Temperature

-....

~

0

!,l-0.03

-0.05

125

TEMPERATURE ("C)

o

I
I

~ -0.02

TA=25"C I
fa.JC2 = 250 kHz
MF4-S0- I-

lD' 0.02

~

~ -o.o~
a;

!,l -0.03

0.G4
0.03

fa.JC= 250 kHz
MF4-100 -

0.02
0.01

!!l

I I

'\

-0.3

-o.s

!

s~*J.OY

VB

TA=25"C~I~

0.03

!\Vs =U.5V

.. -o.z

DC Gain Deviation
Power Supply Voltage

VB

Q3

G.2

(Continued)

85

-55

125

lEMPERATURE ("C)

-15

25--

85

125

TEMPERATURE ("C)

TLlH/5064-10

7-94

50:1) of the clock frequency supplied to the filter. Internal
integrator time constants set the filter's cutoff frequency.
The resistive element of these integrators is actually a capacitor which is "switched" at the clock frequency (for a
detailed discussion see Input Impedance Section). Varying
the clock frequency changes the value of this resistive element and thus the time constant of the integrators. The
clock-to-cutoff-frequency ratio (fCLKfcl is set by the ratio of
the input and feedback capaCitors in the integrators. The
higher the clock-to-cutoff-frequency ratio the closer this approximation is to the theoretical Butterworth response. The
MF4 is available in fCLK/fc ratios of 50:1 (MF4-50) or 100:1
(MF4-100).

Pin Descriptions
(Numbers in ( ) are for 14-pin package.)

Pin
#
1
(1)

2
(3)

3

Pin

Function
Name
ClK IN A CMOS Schmitt-trigger input to be used
with an external CMOS logic level clock.
Also used for self clocking Schmitt-trigger
oscillator (see section 1.1).
ClKR A TTL logic level clock input when in split
supply operation (± 2.5V to ± 7V) with L. Sh
tied to system ground. This pin becomes a
low impedance output when L. Sh is tied to
V-. Also used in conjunction with the ClK
IN pin for a self clocking Schmitt-trigger
oscillator (see section 1.1). The TTL input
signal must not exceed the supply voltages
by more than 0.2V.

1.1 CLOCK INPUTS
The MF4 has a Schmitt-trigger inverting buffer which can be
used to construct a simple RIC oscillator. Pin 3 is connected to V- which makes Pin 2 a low impedance output. The
oscillator's frequency is nominally

L. Sh

level shift pin; selects the logic threshold
1
levels for the clock. When tied to V- it
(1)
enables an internal tri-state buffer stage
fCLK = RCln [(VCC - Vr) (VT+)]
between the Schmitt trigger and the internal
VCC - VT +
VT clock level shift stage thus enabling the
which, is typically
ClK IN Schmitt-trigger input and making the
1
ClK R pin a low impedance output. When
(1 a)
fCLK "" 1.69 RC
the voltage level at this input exceeds 25%
(V+ - V-I + V- the internal tri-state
for Vee = 10V.
buffer is disabled allowing the ClK R pin to
Note that fCLK is dependent on the buffer's threshold levels
become the clock inputfor the internal
as well as the resistorlcapacitor tolerance (see Figure 1).
clock level-shift stage. The ClK R threshold
Schmitt-trigger threshold voltage levels can change significantly causing the RIC oscillator's frequency to vary greatly
level is now 2V above the voltage on the l.
Sh pin. The ClK R pin will be compatible
from part to part.
Where accurate cutoff frequency is reqUired, an external
with TTL logiC levels when the MF4 is
clock can be used to drive the ClK R input of the MF4. This
operated on split supplies with the L. Sh pin
connected to system ground.
input is TTL logic level compatible and also presents a very
FilTER The output of the low-pass filter. It will
light load to the external clock source (- 2 p.A). With split
5
(8) OUT
typically sink 0.9 mA and source 3 mA and
supplies and the level shift (L. Sh) tied to system ground,
swing to within 1V of each supply rail.
the logic level is about 2V. (See the Pin Description for L.
--6-AGND-TlieariaJoggrounlrpm.This-pin-sets-thErDC- ----Sh):---~ ---- ~--(5)

~ias level for the filter section an.d must be
tied to the system ground for split supply
operation or to mid-supply for single supply
operation (see section 1.2). When tied to
mid-supply this pin should be well
bypassed.
7,4 V+, V- The positive and negative supply pins. The
(7,12)
total power supply range is 5V to 14V.
Decoupling these pins with 0.1 p.F
capacitors is highly recommended.

(1 0)

1.2 POWER SUPPLY
The MF4 can be powered from a single supply or split supplies. The split supply mode shown in Figure 2 is the most
flexible and easiest to implement. Supply voltages of ± 5V
to ± 7V enable the use of TTL or CMOS clock logic levels.
Figure 3 shows AGND resistor-biased to V+ 12 for single
supply operation. In this mode only CMOS clock logic levels
can be used, and input signals should be capacitor-coupled
or biased near mid-supply.
1.3 INPUT IMPEDANCE
The MF4 low-pass filter input (FilTER IN) is not a high impedance buffer input. This input is a switched-capacitor resistor equivalent, and its effective impedance is inversely
proportional to the clock frequency. The equivalent circuit of
the filter's input can be seen in Figure 4. The input capacitor
charges to Vin during the first half of the clock period; during
the second half the charge is transferred to the feedback
capacitor. The total transfer of charge in one clock cycle is
therefore
= CinVin, and since current is defined as the
flow of charge per unit time, the average input current becomes

FilTER The input to the low-pass filter. To minimize
8
gain errors the source impedance that
(14) IN
drives this input should be less than 2K (see
section 1.3 of the Application Hints). For
single supply operation the input signal
must be biased to mid-supply or AC coupled
through a capapitor.

1.0 MF4 Application Hints

a

The MF4 is a non-inverting unity gain low-pass fourth-order
Butterworth switched-capacitor filter. The switched-capacitor topology makes the cutoff frequency (where the gain
drops 3.01 dB below the DC gain) a direct ratio (100:1 or

lin = OIT

7-95

,.

~ r-----------------------------------------------------------------~--------------,

u..

:::I!!

1.0 MF4 Application Hints (Continued)
.
.

.
(where T equals one clock period) or

,

which will become noticeable when the clock frequencY e)(~
ceeds 250 kHz. The response of the MF4 is still a good
approximation of the ideal Butterworth low-pass characteristic shown in Figure 5.

---:r,.

CinVin'
lin =
= .CinVinfClK
The equivalent input resistor (Rin) then can be expressed as

2.0 Designing With The MF4

Rin = Vin = ._1_._
lin' CinfClK
The input capacitor is 2 pF for the MF4-50 and 1 pFfor the
MF4-100, so for the MF4~100
'1 x 1012
1 X 1012
1 X 1010
Rin = - - - = - - - = - - fClK
fc X 100
fc
and
5 X 1011
1 X 1010
5 X 1011
Rin = - - - = - - - = - - fClK
fc X 50
fo
for the MF4-50. The above equation shows that for a given
cutoff frequency (fel, the input resistance of the MF4-50 is
the same as that of the MF4-100. The higher the clock-tocutoff-frequency ratio, the greater equivalent input resistance for a given clock frequency~ .

Given any low-pass filter specificaiion, two equations will
come in handy in trying to determine whether the MF4 will
do the job. The first equation determines the order of the
low-pass filter required to meet a given response specification:
.
log [(100.1Amin - 1)/(100.1Amax - 1)]
n=
2 log (fs/fb) .
..
(2)
where n is the order of the filter, Amin is the minimum stopband attenuation (in dB) desired at frequl;lncy fs, and Amax is
the passband ripple or attenuation (in dB) at cutoff frequency fb. If the result of this equation is greater than 4, more
.
than a Single MF4 is required.
The attenuation at any frequency Can be found by the following equl;ltion:
Attn (f) = 10 log [1 + (100.1Amax'- 1) (f/fb)2n] dB (3)

This input resistance will form a voltage divider with the
source impedance (Rsouroel. Since Rin is inversely proportional to the cutoff frequency, operalion at higher cutoff frequencies will be more likely to load the input. signal which
would appear !\s an overall decrease in gain to the output of
the filter. Since the filter's ideal gain is unity, the overall gain
is given by:
.

where n = 4 for the I\!IF4.
2.1 A LOW·PASS DESIGN EXAMPLE
Suppose the amplitude response speCification in Figure 6 is
given .. can the MF4 be used? The order of the Butterworth
approximation will'have .to be,determined using (1):

A -

Rin
y - Rin + Rsource
If the MF4-50 or the MF-l00 were set up for a cutoff frequency of 10kHz the inpu~ impedance would be:
.1 x 1010
.Rin= 10kHz,=IMO

Amln = 18 dB, Amax = 1:0 dB, fs = 2 kHz, and fb = 1 kHz
. log [(101.8 - 1)/(1!jO.l - 1)]
n =
= 3.95
..
210g(2)
.
Since n can only take on integer values, n = 4. Therefore
the MF4 can be used. In general, if n. is 4 or less a single
MF4 stage can be utilized.
Likewise, the attenuation at fs can be found using (3) with
the above values and n = 4:
Attn (2 kHz) = 10 log [1 + 100.1 - 1)(2 kHz/1 kHz)8] =
18.28 dB

In'this example with a source imRedance of 10K the overall
gain, if the MF4 had an ideal gain of 1 or 0 dB, would be: ..
1 MO
Ay = 10 kO + 1 MO = 0.99009 or ;-0.086 dB
Since the l"(1aximum overall gain error for the MF4.' is
± 0.15 dB with Rs :<;; 2 kO the actual gain error for this case
would be +0.06 dB to -0.24 dB.

This result also 'meets the design specification given in Fig·
ure 6 again verifying that a single Mf4 section will be adequate.
Since the MF4's cutoff frequency (fc), which corresponds to
a gain attenuation of -3.01 dB, was not specified in this
example, it needs to be calculated. Solving equation 3
where f = fc as follows:
. =
[(100.1(3.01 dB) ...:. 1 ]1I(2n)
fc
fb (100.1Amax _ 1)
,

1.4 CUTOFF FREQUENCY RANGE
The filter's cutoff' frequency (fel has a lower limit due to
leakage currents through. the internal switches draining the
charge stored on the capaCitors. At lower clock frequencies
these leakage currents can cause millivolts of error, for example:
.

_
,[100.301 - 1.]1/8
- 1 kHz 100.1 _ 1

fClK = ,10.0 Hz,' Ileakage = 1 pA, C = 1 pF
V=

1 pA
= 10 mV
1 pF (100 Hz)
"

= 1.184 kHz
where f~ = fCLI(/50 or fClK/1 00. To implement this example for the MF4-50 the clock frequency wili have to be set to
fClK = 50(1.184 kHz) = 59.2 kHz, ,or for the MF4-1 00, fClK
= 100(1.184 kHz) = 118.4 kHz.
.
'

The propagation delay in the logic and the settling time required to acquire a new voltage level on the capaCitors limit
the fiiter's accuracy at high clock frequencies. The amplitude characteristic on ± 511 supplies will typically stay flat
until fClK exceeds 750 kHz and then peak at about 0.5 dB
at the corner frequency with a 1 MHz clock. As supply volt~
age drops to ± 2.5V, a shift in the fClK/fo ratio occurs

2.2 CASCADING MF4s

When a steeper stopband atten~atiein rat~is, required, iwei,
MF4s can be cascaded (Figure 7) yielding an 8th order

7·96

2.0 Designing With The MF4 (Continued)
slope of 48 dB per octave. Because the MF4 is a Butterworth filter and therefore has no ripple in its passband when
MF4s are cascaded, the resulting filter also has no ripple in
its passband. Likewise the DC and passband gains will remain at1VIV. The resulting response is shown in Figure 9.

MF4-50 has a 100 kHz clock making fe = 2 kHz; when this
signal goes high the clock frequency changes to 50 kHz
yielding fe = 1 kHz. As the Figure illustrates, the output
signal changes quickly and smoothly in response to a sudden change in clock frequency.
The step response of the MF4 in Figure 10 is dependent on
f e. The MF4 responds as a classical fourth-order Butterworth low-pass filter.

In determining whether the cascaded MF4s will yield a filter
that will meet a particular amplitude response specification,
as above, equations 3 and 4 can be used, shown below.
n = log[(100 .05A min - 1)/(10.0 .05A max - 1)]
(2)
2 log (fs/fe)
Attn (f) = 10 log [1 + (10 0.05A max - 1)(f/fel2] dB (3)

2.4 ALIASING CONSIDERATIONS
Aliasing effects have to be considered when input signal
frequencies exceed half the sampling rate. For the MF4 this
equals half the clock frequency (fcu-....Wll-LJI--I

TLlH/50B6-21

FIGURE 12. MODE 4

7-110

i:
.."

2.0 Modes of Operation (Continued)

(II

MODE 6a: Single Pole, HP, LP Filter (See Figure 14)

MODE 5: Numerator Complex Zeros, BP, LP
(See Figure 13)

fo .

=

~1

+ R2 x IClKor~1 + R2 X IClK
R4 100
R4
50

fz

=

~1

- R1 x IClKor~1 _ R1 x IClK
R4 100
R4
50

Q

= 41 + R2/R4 X

:~

Qz

= 41

:~

H0z1

= gain at C.Z. output (as I -+ 0 Hz)

H0z2

= gain at C.Z. output (as f -+ ICt) =

R1/R4 X

= cutoff frequency 01 LP or HP output
R2 fClK R2 IClK
= R3 ffio°r R3 50
HOlP
HOHP

MODE 6b: Single Pole LP Filter (Inverting and NonInverting) (See Figure 15)

-R2(R4-R1)
R1 (R4+R2)

Ie

-R~2

HOSp =_(=R2 + 1) X R3

R1

R3
R1
R2
R1

= cutoff Irequency 01 LP outputs
R2 IClK R2 IClK
"" R3 100 or R3 50

HOlP1 = 1 (non-inverting)
R3
HOlP2 =
R2

R2

HOlP =_(R2 + R1) X R4
R2 + R4
R1
H4

HI

___ ~ __ .________ ~ _____ ~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ------.-IL1HL506§'"-22~_

FIGURE 13. MODE 5
HP

SI

LP

H1

~5
YTL/H/5066-23

FIGURE 14. MODE 6a
LP,
(NON INY) YIII

LI'2 (lNY)

TUH/5066-24

FIGURE 15. MODE 6b

7·111

2.0 Modes of Operation (Continued)
T~BLE

Mode
1

I. Summary of Modes. ~eallzable filter types (e.g. low-pass) denoted bY,asterlsks, Unless otherwlse,noted"
gains of various filter outputs are inverting and adjustable by resistor ratios. , ,
BP

LP

*

*

HOBP1=-Q
HOBP2=+1

HOLP= +1

(2)
1a

2

*

I

HP

AP

N

*

*

*

Number of
resistors

Adjustable

3

No

2

No

3

Yes (above
fCLK/50 or
fCLK/100)

fCLKlfo

:

3

3a

4

*
*
*

*'
*

*

6a
6b

May need input buffer. Poor dynamics
forhighO.
\

Universal StateVariable Filter. Best
general-purpose mode.

*

- Yes

*

7

Yes

As above, but also'-'
includes resistortuneable notch.

*

3'

No

Gives Allpass response with HOAP = -1
and HOLP= -2.

*

4

Gives flatter allpass
response than above
if R1 = R2 = 0.02R4'

3

Single pole.

2

Single pole

*

*
*
*
(2)

Notes

4

.-

5

,

*

HoLp= +1
-R3
HOLP2=""Fi2

3.0 Applications Information

,

The MF5 is a general-purpose second-order state variable
filter whose center frequency is proportional to the frequency of the square wave applied to the clock'input (fClK>. By
connecting pin 9 to the appropriate DC voltage, the filter
center frequency fo can be made equal to either fClK/100
or fCLK/50. fo can be very accurately set (within ± 0.6%) by
using a crystal clock oscillator, or can be easily varied over
a wide frequency range by adjusting the clock frequency. If
desired, the fClK/fo ratio can be altered by external resistors as in Figures 9, 10, 11, 13, 14, and 15. The filter 0 and
gain are determined by external resistors.

From the specifications, the filter parameters are:
fo=200 Hz, HOLP= -2, and, for Butterworth response,
, 0=0.707.
In .section 2.0 are several modes of operation for the MF5,
each having different characteristics. Some allow adjustment of fCLKlfo, others produce different combinations of
filter types, some are inverting while others are non-inverting, etc. These characteristics are summarized in Table I. To
keep the example Simple, we will use mode 1, which has
notch, bandpass, and lowpass outputs, and inverts the signal pOlarity. Three external resistors determine the filter's 0
and gain. From the equations accompanying Figure 7,
0=R3/R2 and the passband gain HOlP = -R2/R1' Since
the input signal is driving a summing junction through R1,
the input impedance will be equal to R1. Start by choosing a
value for R1. 10k is convenient and gives a reasonable input
impedance. For HOLP = -2, we have:

All of the five second-order filter types can be built using the
MF5. These are illustrated in Figures 1 through 5 along with
their transfer functions and s(lme related equations. Figure
6 shows the effect of 0 on the shapes of these curves.
When filter orders greater than two are desired, two or more
MF5s can be cascaded. The MF5 also includes an uncommitted CMOS operational amplifier for additional signal processing applications.
i

R2 = -R1HOlP = 10k x 2 = 20k.
For 0 = 0.707 we have:

3.1 DESIGN EXAMPLE
An example will help illustrate the' MF5 design procedure.
For the example, we will design a 2nd order Butterworth
low-pass filter with a cutoff frequency of 200 Hz, and a passband gain of - 2. The circuit will operate from a ± 5V power
supply, and the clock amplitude will be ± 5v (CMOS) levels). "
7-112

R3 = R20 = 201< x 0.707 = 14.14k. Use 15k.
For operation on ±5V supplies, V+ is connected to +5V,
V- to -5V, and AGND to ground. The power supplies
should be "clean" (regulated supplies are preferred) and
0.1 J.LF bypass capacitors are recommended.

:

:

3.0 Applications Information

(Continued)

+5V

HI
10k R3
15k
H2.20k

l5h

Y'

... _____ J
I

51

INVI

BP

I
I
I
I
I

I

I

I

L

ClK

LP

14

Vour
-5V

JUU"L
20kHz
±5Y DR OV T115V

TL/H/5066-25

FIGURE 16. 2nd-Order Butterworth Low-Pass Filter of Design
Example. For f~~K = 50, Connect Pin 9 to

+ 5V, and

Change Clock Frequency to 10 kHz.

10V

~

-

~--- ---~----.".~

HI
lDk H3
15k

- T--

~5h

0.1

H2.10k

y+

INVI

... _____ J

BP

I

I
I
I

I
I

I
I
I

,.

L

ClK

LP

14
VaUT

20kHz.

OVTII 5Y DR
OVTlll0V

TLiH/506B-26

FIGURE 17. Butterworth Low-Pass Circuit of Example, but Designed for Single-Supply Operation

7-113

~r---------------------------------------------------------~

u..

:::E

3.0 Applications Information (Continued)
v+
V+

~
R

':"

T

C

v+

v+
T

TYPI:AL VALUES:
2k:sR:slDDk
4.7 ,.F:sCS47D,.F

":'

TL/H/S066-27

(a) Resistive Divider with
Decoupling Capaciter

TL/H/5066-2B

(b) Voltage Regulator

TUH/S066-29

(c) Operational Amplifier
with Divider

FIGURE 18. Three Ways of Generating V2+ for Single-supply Operation

For a cutoff frequency of 200 Hz, the external clock can be
either 10 kHz with pin 9 connected to V+ (50:1) or 20 kHz
with pin 9 tied to AGND or V- (100:1). The voltage on the
Logic Level Shift pin (7) determines the logic threshold for
the clock input. The threshold is approximately 2V higher
than the voltage applied to pin 7. Therefore, when pin 7 is
grounded, the clock logic threshold will be 2V, making it
compatible with 0-5 volt TTL logic levels and ± 5 volt
CMOS levels. Pin 7 should be connected to a clean, low-impedance (less than 1000n) voltage source.

these limits. If the MF5 is operating on ±5 volts, for example, the outputs will clip at about 8Vp_p. The maximum input
voltage multiplied by the filter gain should therefore be less
than 8Vp_p.
Note that if the filter has high Q, the gain at the lowpass or
highpass outputs will be much greater than the nominal filter
gain (Figure 6'). As an example, a lowpass filter with a Q of
10 will have a 20 dB peak in its amplitude response at fo. If
the nominal. gain of the filter HOLP is equal to 1, the gain at
fo will be 10. The maximum input signal at fo must therefore
be less than 800 mVp-p when the circuit is operated on ±5
volt supplies.
Also note that one output can have a reasonable small voltage on it while another is saturated. This is most likely for a
circuit such as the notch in Mode 1 (Rgure 7). The notch
output will be very small at fo, so it might appear safe to
apply a large signal to the input. However, the bandpass will
have its maximum gain at fo and can clip if overdriven. If one
output clips, the performance at the other outputs will be
degraded, so avoid overdriving any filter section, even ones
whose outputs are not being directly used. Accompanying
Figures 7 through 15 are equations labeled "circuit dynamics", which relate the Q and the gains at the various outputs.
These should be consulted to determine peak circuit gains
and maximum allowable signals for a given application.

The complete circuit of the design example is shown for a
100:1 clock ratio in Figure 16.
3.2 SINGLE SUPPLY OPERATION
The MF5 can also operate with a single-ended power supply. Figure 17 shows the example filter with a single-ended
power supply. V+ is again connected to the positive power
supply (8 to 14 volts), and V- is connected to ground. The
AGND pin must be tied to V+ /2 for single supply operation.
This half-supply point should be very "clean", as any noise
appearing on it will be treated as an input to the filter. It can
be derived from the supply voltage with a pair of resistors
and a bypass capacitor (Figure 18a), or a low-impedance
half-supply voltage can be made using a three-terminal voltage regulator or an operational amplifier (Figures 18b and
18e). The passive resistor divider with a bypass capaCitor is
sufficient for many applications, provided that the time constant is long enough to reject any power supply noise. It is
also important that the half-supply reference present a low
impedance to the clock frequency, so at very low clock frequencies the regulator or op-amp approaches may be preferable because they will require smaller capacitors to filter
the clock frequency. The main power supply voltage should
be clean (preferably regulat~d) and bypassed with O.l/loF.

3.4 OFFSET VOLTAGE
The MF5's switched capacitor integrators have a higher
equivalent input offset voltage than would be found in a
typical continuous-time active filter integrator. Figure 19
shows an equivalent circuit of the MF5 from which the output dc offsets can be calculated. Typical values for these
offsets are:

3.3 DYNAMIC CONSIDERATIONS
The maximum signal handling capability of the MF5, like
that of any active filter, is limited by the power supply voltages used. The amplifiers in the MF5 are able to swing to
within about 1 volt of the supplies, so the input signals must
be kept small enough that none of the outputs will exceed

Vosl = opamp offset = ±5mV
Vos2= -185mV@50:1

-310mV@100:1

Vos3= +115mV@50:1

+240mV@100:1

The dc offset at the BP output is equal to the input offset of
the lowpass integrator (Vos3). The offsets at the other outputs depend on the mode of operation and the resistor ratios, as described in the following expressions.

7-114

3.0 Applications Information

(Continued)

Mode 1 and Mode 4

Mode 2 and Mode 5

(~+ 1 +IIHoLPI!) - V~S3

VOS(N)

'" VOSI

VOS(BP)

;=

VOS(LP)

= VOS(N) - VOS2

Mode 1a
Vos(N.lNV.BP) =

VOS(N)

=

(

R2' )
RIl + 1, VOSI X

Voss

( + Q1)
1

" 1

1 + R2/R4

1

' VOS3

+ VOS2 1 + R4/R2 - Q.j1 + R2/R4 :
Rp ,= R111R211R4

VOSI -

Voss

Q

Vos(lNV.BP)

= Voss

Vos(LP)

= Vos(N.INV.BP) - VOS2

VOS(BP)

= VOS3

VOS(LP)

= VOS(N) - VOS2

Mode 3
VOS(HP)

=VOS2

VOS(BP)

=VOS3

,

VOS(LP)

R4 ( R 2 '
= - - VOS3
R2 R3

)

R4 (
:- R2 1

R2)

+ Rp

+ VOS2 +
, '

VOS1; Rp = R111R311R4

TUHI5066-30

FIGURE 19. Block Diagram Showing MF5
Offset Voltage Sources

5V SUPPLY

R
1M

R4

R3
TLlH15066-31

FIGURE 20. Method for Trimming VOS,
See Text, Section 3.4

7-115

•

~ r-----------------------~--------------------------------------------------------,

U.

:::E

3.0 Applications Information (Continued)
ing", and can be reduced or eliminated by limiting the input
signal spectrum to less than fs/2. This may in some cases
require the use of a bandwidth-limiting filter ahead of the
MF5 to limit the input spectrum. However, Since the clock
frequency is much higher than the center frequency, this will
often not be necessary.

For most applications, the outputs are AC coupled and DC
offsets are not bothersome unless large signals are applied
to the filter input. However, larger offset voltages will cause
Clipping to occur at lower ac Signal levels, and clipping at
any of the outputs will cause gain nonlinearities and will
change fa and Q. When operating in Mode 3, offsets can
become excessively large if R2 and R4 are used to make
felK/fo significantly higher than the nominal value, especially if Q is also high. An extreme example is a bandpass filter
having unity gain, a Q of 20, and felK/fo = 250 with pin 9
tied to V- (100:1 nominal). R4/R2 will therefore be equal to
6.25 and the offset voltage at the lowpass output will' be
about + 1.9V. Where necessary, the offset voltage can be
adjusted by using the circuit of Figure 20. This allows adjustment of Vos1, which will have varying ,effects on the different
outputs as described in the above equations. Some outputs
cannot be adjusted this way in some modes, however
(Vos(BP) in modes 1a and 3, for example).

Another characteristic of sampled-data circuits is that the
Ol.ltput signal changes amplitude once every sampling period, resulting in "steps" in the output voltage which occur at
the clock rate. (Figure 21) If necessary, these can be
"smoothed" with a simple R-C low-pass filter at the MF5
output.
The ratio of felK to fe (normally either 50:1 or 100:1) will
also affect performance. A ratio of 100:1 will reduce any
aliasing problems and is usually recommended for wideband input signals. In noise sensitive applications, however,
a ratio of 50:1 may be better as it will result in 3 dB lower
output noise. The 50: 1 ratio also results in lower DC offset
voltages, as discussed in 3.4.

3.5 SAMPLED DATA SYSTEM CONSIDERATIONS

The accuracy of the felK/fo ratio is dependent on the value
of Q. This is illustrated in the curves under the heading
"Typical Performance Characteristics". As Q is changed,
the true value of the ratio changes as well. Unless the Q is
low, the error in felK/fo will be small. If the error is too large
for a speCific application, use a mode that allows adjustment
of the ratio with external resistors.

The MF5 is a sampled data filter, and as such, differs in
many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect on signals at frequencies greater than one-half the
sampling frequency. (The MF5's sampling frequency is the
same as its clock frequency). If a Signal with a frequency
greater than one-half the sampling frequency is applied to
the input of a sampled data system, it will be "reflected" to
a frequency less than 'one-haH the sampling frequency.
Thus, an input signal whose frequency is f8/2 + 100 Hz will
cause the system to respond as though the input frequency
was fs/2 - 100 Hz. This phenomenon is known as "alias-

It should also be noted that the product of Q and fa should
be limited to 300 kHz when fa < 5 kHz, and to 200 kHz for
fa> 5 kHz.

1l1li:1

50:1

TLfH/5066-32

FIGURE 21. The Sampled-Data Output Waveform

7-116

tfI Nat ion a l

S e m.i con due tor

MF6 6th Order Switched Capacitor
Butterworth Lowpass Filter
General Description

Features

The MF6 is a versatile easy to use, precision 6th order Butterworth lowpass active filter. Switched capacitor techniques eliminate external component requirements and alIowa clock tunable cutoff frequency. The ratio of the clock
frequency to the lowpass cutoff frequency is internally set to
50 to 1 (MF6-50) or 100 to 1 (MF6-100). A Schmitt trigger
clock input stage allows two clocking options, either selfclocking (via an external resistor and capacitor) for standalone applications, or an external TTL or CMOS logic compatible clock can be used for tighter cutoff frequency control. The maximally flat passband frequency response together with a DC gain of 1 VIV allows cascading MF6 sections for higher order filtering. In addition to the filter, two
independent CMOS op amps are included on the die and
are useful for any general signal conditioning applications.

•
•
•
•
•
•
•

No external components
14-pin DIP or 14-pin wide-body S.D. package
Cutoff frequency accuracy of ± 0.3% typical
Cutoff frequency range of 0.1 Hz to 20 kHz
Two uncommitted op amps available
5V to 14V total supply voltage
Cutoff frequency set by external or internal clock

Block and Connection Diagrams
All Packages
N.IIM

INV2

Va

INVl

FlUER
OUT

L8~

Vol
-- AGNII-----_ - -

CLKR

MNO

~-'-.--CUI
IN

v+
Vaz

FlIJER
IN

YoIAD.I

INV!

TL/H/S06S-2

Top View
Order Number MF6CWM-50
or MF6CWM-100
See NS Package Number M14B

TUH/S06S-1

Order Number MF6CN-50
or MF6CN-100
See NS Package Number N14A
Order Number MF6CJ-50
or MF6CJ-100
See NS Package Number J 14A

7-117

til

Absolute Maximum Ratings (Note 11)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
14V
Voltage at Any Pin
V- - 0.2V. V+ + 0.2V

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.

Input Current at Any Pin (Note 13)

Temperature Range

Package Input Current (Note 13)
Power Dissipation (Note 14)
Storage Temperature
ESD Susceptibility (Note 12)

Operating Ratings (Note 11)

5mA

MF6CWM-50, MF6CWM-l00
MF6CJ-50, MF6CJ-l00

- 65'C to + 150'C

Supply Voltage (VS

800V

Soldering Information
N Package (10 sec.)
J Package (10 sec.)
SO Package
Vapor Phase (60 sec.)
Infrared (15 sec,)

TMIN 5: TA 5: TMAX
O'C 5: TA 5: +70'C

MF6CN-50, MF6CN-l00

20mA
500mW

O'C,;; TA 5: +70'C
-40'C 5: TA';; +85'C

= V+-V-)

5Vto 14V

260'C
300'C
215'C
220'C

Filter Electrical Characteristics

The following specifications apply for lelK ,;; 250 kHz (see Note 3) unless
otherwise specified. Boldface limits apply for TMIN to T MAXi all other limits TA = TJ = 25'C.
MF6CWM-50, MF6CWM-100,
MF6CN-50, MF6CN-100
Parameter

Conditions
Typical
(NoleS)

Tested
Limit
(Note 9)

Design
Limit
(Note 10)

MF6CJ-50, MF6CJ-100
Typical
(NoleS)

Tested
Limit
(Nole9)

Design
Limit
(r~ote 10)

Units

V+ = +5V, V- = -5V
Ie, Cutoff
Frequency
Range
(Note 1)

MF6-50
MF6-100

Min
Max
Min
Max

Total Supply Current
Maximum Clock
Feedthrough

ICLK=250 kHz

Filter Output
OpAmpl0ut
OpAmp 2 Out

Ho,
DC Gain
MF6-50
MF6-100

DC
Offset Voltage

MF6-50
MF6-100

Minimum Output
Voltage Swing

Dynamic Range
(Note 2)
Additional
MagnHude
Response Test
Points (Note 4)

4.0

6.0

8.5

0.0

0.1
20k
0.1
10k
4.0

8.5

30
25
20

30
25
20
Rsource
,;; 2kn

IClKlfe,
Clock to Cutoff
Frequency Ratio

Maximum Output
Short Circuit
Current (Note 6)

0.1
20k
0.1
10k

±0.30

±0.30

0.0

Hz

mA
mV
(peak-topeak)

±0.30

dB

49.27±0.3% 49.27±1% 49.27±1% 49.27±0.3% 49.27±1%
98.97±0.3% 9B.97±1% 98.97±1% 9B.97±0.3% 98.97±1%
-200
-400
Rl=10kn

+4.0
-4.1

-200
-400
+3.5
-3.B

+3.5
-3.5

+4.0
-4.1

mV
+3.5
-3.5

V

Source
Sink

50
1.5

50
1.5

mA

MF6-50
MF6-100

B3
81

B3
81

dB

MF6-50 'ClK=250 kHz
f=6000 Hz
1=4500 Hz

-9.47
-0.92

-9.47±0.6 -9.47±O.75
-0.92±0.6 -O.92±0.4

-9.47
-0.92

-9.47±O.75
-0.92±O.4

dB

MF6-100 'ClK = 250 kHz
'=3000 Hz
'=2250 Hz

-9.48
-0.97

-9.4B±0.3 -9.48±0.7S
-0.97±0.3 -O.97±0.4

-9.48
-0.97

-9.48±O.75
-0.97±O.4

dB

7-118

s:::

."

Filter Electrical Characteristics (Continued) The following specifications apply for fCLK :s: 250 kHz (see

en

Note 3) unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = T J = 25°C.
MF6CWM·SO, MF6CWM·100
MF6CN·SO, MF6CN·100
Parameter

Conditions

MF6CJ·SO, MF6CJ·100

Tested
Limit
(Note 9)

Design
Limit
(Note 10)

MFS·50 IClK=250 kHz
11=6000 Hz
12 =8000 Hz

-36

-36

-36

MF6·100 IClK=250 kHz
11 =3000 Hz
12=4000 Hz

-36

-36

-36

Typical
(Note 8)

Typical
(Note 8)

Tested
Limit
(Note 9)

Units

Design
Limit
(Note 10)

Y+ = + SV, V- = -SV (Continued)
Attenuation Rate

dBI
octave
dBI
octave

Y+ = +2.SV, V- = -2.SV
Ie. Cutoff
Frequency
Range
(Note 1)

MF6·50

0.1
10k
0.1
5k

Min
Max
Min
Max

MF6·100

Total Supply Current

IClK=250 kHz

Maximum Clock
Filter Outpu
Feedthrough
OpAmp10ut
Op Amp 2 Out
Ho,DCGain

2.5

4.0

4.0

20
15
10
R.ource:S: 2 kO

0.0

0.1
10k
0.1
5k
2.5

4.0

mA

20
15
10
±0.30

±0.30

0.0

Hz

mV
(peak·topeak)
±0.30

dB

fClJ(lfe• Clock to
Cutoff Frequency
Ratio

MF6-50
MF6·100

DC
Offset Voltage

MF6·50
MF6·100

Minimum Output
Voltage Swing

49.10±0.3% 49.10±2% 49.10±3% 49.10±0.3% 49.10±3%
98.65±0.3% 98.65±2% 98.65 ± 2.25% 98.65±0.3% 98.65 ± 2.25%
-200
-400
Rl=10kO

_MaximumDutput
Short Circuit
Current (Note 6)

",ource
Sink

- -

Dynamic Range (Note 2)
Additional
Magnitude
Response Test
Points (Note 4)

Attenuation
Rate

+1.5
-2.2

-200
-400
+1.0
-1.7

+1.0
-1.5

- - 2 S - - I---

+1.5
-2.2

0.5

28
0.5

77

77

mV
+1.0
-1.5

V
~-~

mA
dB

MF6-50 IClK= 250 kHz
1=6000 Hz
1=4500 Hz

-9.54
-0.96

-9.54±0.6 -9.54±0.75
-0.9S±0.3 -0.96±0.4

-9.54
-0.96

-9.54±0.75
-0.96 ± 0.4

dB

MFS·100 lClK=250 kHz
1=3000 Hz
1=2250 Hz

-9.67
-1.01

-S.67±0.6 -9.67±0.75
-1.01 ±0.3 -1.01 ±0.4

-9.S7
-1.01

-9.67±0.75
-1.01±0.4

dB

MF6·50 lClK= 250 kHz
11=6000 Hz
12=8000 Hz

-36

-36

-36

MF6·100 IClK = 250 kHz
11 =3000 Hz
12=4000 Hz

-36

-36

-36

7·119

dBI
octave

dBI
octave

•

Op Amp Electrical Characteristics
!'!oldfacelimits apply forTMINtoTMAX;all otherlimitsTA =

tJ =

25°C.

MF6CN-50; MF~CN-100,
MF6CWM-50, MF6CWM-100
Parameter

Conditions
Typical
• (Note 8)

,

MF6CJ-50, MF6CJ-100

Tested
Limit
(Note 9)

Design
Limit
(Note 10)

Typical
(Note 8)

Tested
Limit
(Note 9)

±20

±20

' ±8.0

±20

Design
Limit
(Note 10)

Units

Y+ = .+5Y, Y- = -5Y
Input Offset Voltage

±8.0

Input Bias Current

10

CMRR,(OpAmp #2 Only)

VCM1 = 1.8V,
VCM2 = -2.2V

Outpilt Voltage Swing

RL =10 kO

10

mV
pA

60

55

dB

+3.6
-4.0

+4.0
-4.5

+3.6
-4.0

V

80
6.0

54
2.0

80
6.0

60

55

+4.0
-4.5

+3.8
-4.0

Maximum Output Short Source
Circuit Current (Note 6)
Sink

54
2.0

65
4.0

Slew Rate

7.0

7.0

DC Open Loop Gain

72

72

dB

Gain Bandwidth Product

1.2

1.2

MHz

, mA
V/ILS'

Y+ ,= +2.5Y, Y- = -2.5Y
±8.0

Input Offset Voltage
Input Bias Current

±20

±20

±B.O

10

CMRR (Op-Amp #2 Only)

VCM1 = +0.5V,
VCM2 = -0.9V

Output Voltage Swing

RL = 10kO

±20

10

60

55

+1.5
-2.2

+1.3
-1.7

+1.1
-1.7

m'il
pA

60

55

dB

+1.5
-2.2

+ 1.1
-1.7

V

Maximum Outpu~ Short Source
Circuit Current (Note 6)
Sink

24
1.0

24
1.0

mA

Slew Rate

6.0

6.0

V/ILS

DC Open Loop Gain

67

67

dB

Gain Bandwidth Product

1.2

1.2

MHz

,

,

"

7-120

Logic Input-Output Electrical Characteristics The following specifications apply for V(see Note 5) unless otherwise specified. Boldface limits apply for T MIN to T MAX; all other limits T A
MF6CN·50, MF6CN·100
MF6CWM·50, MF6CWM·100
'Parameter

Conditions

Typical
(Note 8)

Tested
Limit
(Note 9)

=

iii:

=

.."

en

OV

T J = 25°C.

MF6CJ·50, MF6CJ·100

Design
Typical
Limit
(Note 8)
(Note 10)

Tested
Limit
(Note 9)

Design
Limit
(Note 10)

Units

TTL CLOCK INPUT, ClK R PIN (Note 7)
Maximum VIL, Logical "0"
' Input Voltage
Minimum VIH. Logical "1"
Input Voltage
Maximum Leakage Current

LSh Pin at

atCLKR Pin

Mid· Supply

0.8

0.8

0.8

V

2.0

2.0

2.0

V

2.0

2.0

2.0

",A

SCHMITT TRIGGER
VT + • Positive GOing
Threshold Voltage

Min

V+

=

10V

7.0

6.1
8.9

6.1
8.9

7.0

6.1
8.9

V

V+

=

5V

3.5

3.1
4.4

3.1
4.4

3.5

3.1
4.4

V

V+

=

10V

3.0

1.3

1.3
3.8

3:0

3.8

1.3
3.8

V

Max
Min
Max

VT-. Negative Going
Threshold Voltage

Hysteresis (VT + -

VT -)

Min
Max
Min
Max

V+

=

5V

1.5

0.6
1.9

0.6
1.9

1.5

0.6
1.9

V

Min

V+

=

10V

4.0

2.3
7.6

2.3
7.6

4.0

2.3
7.6

V

V+

=

5V

2.0

1.2
3.8

1.2
3.8

2.0

'1.2
3.8

V

V+ = 10V

9.0

=

4.5

9.0
4.5

9.0
4.5

V

1.0
0.5

1.0
0.5

V

Max
Min
Max
Minimum Logical "1" Output
Voltage (Pin 11)
Maximum Logical "0" Output
Voltage (Pin 11)

10

=

-10",A

10

=

10",A

V+

V+ = 10V

1.0

=
=
=

0.5

V+

Minimum Output Source

CLKRTied

V+

Current (Pin 11)

to Ground

V+

Maximum OutpufsmJ(
Current (Pin 11)

-CLKRTied
toV+

5V

5V
10V

6.0

3.0

5V

1.5

0.75

~OV
V+

=

5V

5.0

2.5

1.3

0.65

3.0
0.75

6.0
1.5

3.0
0.75

2.5
0.65

5.0

2.5
0.65

1.3

mA

mA

Note 1: The cutoff frequency of the filter is defined as the frequency where the magnitude response is 3.01 dB less than the DC gain of the filter.
Note 2: For ±SV supplies the dynamic range is referenced to 2.82 Vrms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 ",Vrms for
the MF6·S0 and 2S0 ",Vrms for the MF6-100. For ±2.SV supplies the dynamic range is referenced to 1.0S Vrms (I.SV peak) where the wideband noise overa20
kHz bandwidth is typically 140 ",Vrms for both the MF6-S0 and the MFS-l00.
Note 3: The specifications for the MF6 have been given for a clock frequency (felK) of 2S0 kHz and less. Above this clock frequency the cutoff frequency begins to
deviate from the specified error band of ± 1.0% but the filter still maintains its magnitude characteristics. See Application Hints, Seelion I.S.
Note 4: Besides checking the cutoff frequency (fel and the stopband attenuation at 2 fe, two additional frequencies are used to check the magnitude response of
the filter. The magnitudes are referenced to a DC gain of 0.0 dB.
Note 5: For simplicity all the logic levels have been referenced to Vlevels).

= OV and will scale accordingly for ±5V and ±2.SV supplies (except for the TTL input logic

Note 6: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to
the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting
that output to the positive supply. These are the worst-case conditions.

Note 7: The MF6 Is operating with symmetrical split supplies and L.Sh is tied to ground.
Note 8: Typicals are at 25'C and represent most likely parametric norm.
Note 9: Tested limits are guaranteed to National's AOQL (Average OutgOing Quality Level.
Note 10: DeSign limits are guaranteed, but not 100% tested. These limits are not used

to calculate outgoing quality levels.

Note 11: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when
operating the device beyond its specified conditions.
Note 12: Human body model, 100 pF discharged through a 1.5k n r.sistor.
Note 13: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V- or VIN > V+) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 14: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 9JA, and the ambient temperature, TA. The
maximum allowable power diSSipation at any temperature is Po = (TJMAX - TpJI9JA or the number given in the Absolute Maximum Ratings, whichever is lower.
For this device, TJMAX = 125'C, and the typical junelion-to-amblent thermal resistance of the MF6CN when board mounted is 67"C/W. For the MF6CJ this number
decreases to 62"C/W. For MF6CWM, 9JA = 78·C/W.

7-121

•

ff

:::E

Typical Performance Characteristics

E

~ ..

i:!i

!!

Schmitt Trigger Threshold Voltage
. 'vs Power Supply Voltage

Crosstalk from Filter
to Op-Amps (MF6-100)
-2D

13

12 V-=OV
TA=25"C
11

-40

10
9

....

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6

5
2
1

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....

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4

3

6 7 8

Vrt

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9 10 11 12 13 14

100

V+ POWER SUPf'LY VOLTAGE (V)

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(Hz)

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(Hz)

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Equivalent Input Noise
Voltage of Op-Amps

@:

10

100

FRIIIUENCY (Hz)

(Hz)

Crosstalk from Either Op-Amp
to Filter Output (MF6-100)

las

0

lK

fR[QUENC'(

Crosstalk from Filter
to Op-Amps (MF6-S0)

!;l

Crosstalk from Either Op-Amp
to Filter Output (MF6-S0)

1011(

~
"
S

Ys =IOV,
T =25"C

5110

300

100'
0
10

100

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FRUlUENC'(

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,1OIIC

(Hz)
TL/H/5!J65-9

7-122

Typical Performance Characteristics (Continued)
Positive Voltage Swing vs
Power Supply Voltage
(Op Amp Output)
5JI
5.4

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III

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Positive Voltage Swing vs
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./

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TEIIPERATURE (CC)

1 " -------15
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,

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Negative Voltage Swing vs
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Op Amp Outputs)

£

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4.1

POWER SUPPLY VOLTAGE (V)

TA=25CC
'CLJ(= 2S0 kHZ
RL=IOkll

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'CLJ(=2S0 kHZ
RL=IOkll

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(Filter and Op Amp Outputs)
-2.4

£
III

POWER SUPPLY VOLTAGE (V)

-2.6

4.2

........

LL

2.1
1.7

./

Positive Voltage Swing vs
Temperature (Filter and
Op Amp,Outputs)

~

I"'- • _

, -55-35-15 5 2S 45 65 85 105125

5.1

~

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4.3

3.9
3.5
3.1
2.7
5

6

7

8

9

10 11

12 13

POWER SUPPLY VOLTAGE (V)

TEMPERATURE (CC)

TL/H/5065-35

•
7·123

ff

::::!

Typical Performance Characteristics (Continued)

felK/fe Deviation
VB Temperature

felK/fe Deviation
VB Clock Frequency
~

3.0
2.D
1.0

Ji -1~
~

~~~~5;; _

,

RL=IMli-

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o.a r:~:~~O~HZ

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100 2DD :lOO 4DD 500 600 700 600 900 1000
CLOCK FREQUENCY (kHZ)

::::;

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:;;

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L

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fCLl(= Z50 kHZ

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......

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100 2DD :lOO 4DD 500 600 700 6DD 900 1000

8

9

10 11

12 13

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TA=25CC ..
feLK = 250 kHZ

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felK/fe Deviation·
VB Power Supply Voltage

MFS-l00
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RL=10kll

1/

/

POWER SUPPLY VOLTAGE (V)

felK/fe Deviation
VB Temperature

~

r--.

-1.0

TEMPERATURE (CC)

felK/fe Deviation
VB Clock Frequency

.-

.'

'\

-1.0

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felK/fe Deviation
VB Power Supply Voltage

I
I

Ji
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is

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is
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5678910111213

TEMPERATURE (CC)

POWER SUPPLY VOlTACE (V)

CLOCK FREQUENCY (kHZ)

Tl/H/5065-S6

DC Gain Deviation
VB Temperature
0.12
0.D9

;;;~

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VB Power Supply Voltage

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5

6

7

8

9

10 11

12 13

POWER SUPPLY VOLTAGE (V)

o

100 2DD :lOO 400 500 600 700 6DD 900 1000
CLOCK FREQUENCY (kHZ)

DC Gain Deviation

DC Gain Deviation

DC Gain Deviation

VB Power Supply Voltage

VB Clock Frequency

..... k:ys=5V

-'0/.

T

-0.Q4
-0.0&

~

Q.4

VB Temperature
0.02

~

o.a
o.a

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-o.s

TEMPERATURE (CC)

~

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/

;;;-

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-0.12

\

-55-35-15 5 25 45 65 85 105125

'i -o.D2

-

Q.02 ~=10kll

~ ~Q.02
~

1.2
TA=25CC
1.0
MF6-50l.

L

TA=25CC ••
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;;;-Q.04 MF6-50

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DC Gain Deviation
VB Clock Frequency

~

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Vs -IOV

I

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TEMPERATURE (CC)

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!

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RL= 10kll

, ....

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-0,10

-1.0
5

6

7

8

9

10 11

12 13

POWER SUPPLY VOLTAGE (V)

o 100 2DD:lOO 400 500 600 700 6DD 900 1000
CLOCK FREQUENCY (kHZ)
Tl/H/5065-S9

7-124

Crosstalk Test Circuits
From Filter to Opamps

20Hz-20kHz
1VRWS

TLIH/S06S-10

From Either Opamp to Filter Output

20Hz-20kHz 'V
1VRWS

TL/H/S06S-11

Pin Descriptions (Pin Numbers)
Pin
FilTER OUT (3)

FilTER IN (8)

VosADJ (7)

AGND(5)

V01 (4),
INVI (13)

Description
The output of the lowpass filter.
It will typically sink 0.9 mA and
source 3 mA and swing to within
1V of each supply rail.
The input to the lowpass filter.
To minimize gain errors the
source impedance that drives
this input should be less than 2k
(see section 1.4-':-For single------supply operation the input signal
must be biased to mid-supply or
ACcoupled.
This pin is used to adjust the DC
offset of the filter output; if not
used it must be tied to the
AGND potential. (See section
1.3)
The analog ground pin. This pin
sets the DC bias level for the
filter section and the noninverting input of Op-Amp # 1
and must be tied to the system
ground for'split supply operation
or to mid-supply for single
supply operation (see section
1.2). When tied to mid-supply
this pin should be well
bypassed.
V01 is the output and INVI is
the inverting input of Op-Amp
# 1. The non-inverting input of
this Op-Amp is internally
connected to the AGND pin.

7-125

Pin
V02(2),
INV2(14),
NINV2(1)

Description
V02 is the output, INV2 is the
inverting input, and NINV2 is the
non-inverting input of Op-Amp
#2.
The positive and negative
supply pins. The total power
supply range is 5V to 14V.

V+(6), V-(10)

__
ClK IN (9)

ClKR(II)

L. Sh (12)

DecolJ!l~th_esElpjn!ll'Vith_

0.1 Jl.F capacitors is highly
recommended.
A CMOS Schmitt-trigger input to
be used with an external CMOS
logic level clock. Also used for
self-clocking Schmitt-trigger
oscillator (see section 1.1).
A TTL logic level clock input
when in split supply operation
(± 2.5V to ± 7V) and L. Sh tied
to system ground. This pin
becomes a low impedance
output when L. Sh is tied to V-.
Also used in conjunction with
the ClK IN pin for a self
clocking Schmitt· trigger
oscillator (see section 1.1).
level shift pin, selects the logiC
threshold levels for the desired
clock. When tied to V- it
enables an internal tri-state
buffer stage between the
Schmitt trigger and the internal
clock level shift stage thus
enabling the ClK IN Schmitttrigger input and making the
elK R pin a low impedance
output.

Pin Descriptions (Pin Numbers) (Continued)
Pin
L. Sh (12)

3.01 dB below the DC gain) a direct ratio (100:1 or 50:1) of
the clock frequency supplied to the lowpass filter. Internal
integrator time constants set the filter's cutoff frequency.
The resistive element of these integrators is actually a capacitor which is "switched" at the clock frequency (for a
detailed discussion see Input Impedance Section). Varying
the clock frequency changes the value of this resistive element and thus the time constant of the integrators. The
clock to cutoff frequency ratio (fCLK/fc) is set by the ratio of
the input and feedback capacitors in the integrators. The
higher the clock to cutoff frequency ratio (or the sampling
rate) the closer this approximation is to the theoretical Butterworth response. The MF6 is available in fCLK/fc ratios of
50:1 (MF6-50) or 100:1 (MF6-100).

Description
When the voltage level at this
input exceeds [25%(V+ - V-I
+ V-I the internal tri-state
buffer is disabled allowing the
ClK R pin to become the clock
input for the .internal clock level
shift stage. The ClK R
threshold level is now 2V above
the voltage applied to the L. Sh
pin. Driving the ClK R pin with
TTL logic levels can be
accomplished through the use
of split supplies and by tying the
L. Sh pin to system ground.

1.1 CLOCK INPUTS
The MF6 has a Schmitt-trigger inverting buffer which can be
used to construct a simple R/C oscillator. The oscillator's
frequency is dependent on the buffer's threshold levels as
well as on the resistor/capacitor tolerance (see Figure 1).

1.0 MF6 Application Hints
The MF6 is comprised of a non-inverting unity gain lowpass
sixth order Butterworth switched capacitor filter section and
two undedicated CMOS Op-Amps. The switched capacitor
, topology makes the cutoff frequency (where the gain drops

to VfCLK
,

= _-.-,-;-;-....:.17.""-'-:-:--,

RCln[(VCC-VT-)VT +]
VCC - VT+ VTTypically for Vee = V+ - V- = 10V:
1

fCLK ,= 1,69 RC

MF6
. TL/H/5065-12

FIGURE 1. Schmitt Trigger RIC Oscillator

+S.OV

N.INV2

1

14

INV2

N.INV2

14

INV2

V02

2

13

V02

2

13

FILTER OUT
Val
AGND

3

12

INVI
L.Sh

3

12

lHVl
l.Sh

4

11

4

11

S

10

FilTER OUT
Val
, AGHD

S

10

6

9

6

9

7

8

y+
VosADJ

7

8

ClKR

yClKIN
FILTER
IN

-S.DV

+S.OV

..n.n.+SV
-SV

v+
Vos'ADJ

TlIH/5065-3

ClKR

y-

..n.n. ~V
OV
-S.OV

ClKIN

TLlH/5065-4

FIGURE 2. Dual Supply Operation
MF6 Driven with CMOS Logic Level Clock
(YIH ~ 0.8YccandYIL ~ 0_2 Ycc where Ycc = y+ - V-I

FIGURE 3. Dual Supply Operation
MF6 Driven with TTL Logic Level Clock

7-126

Application Hints (Continued)

0.1 j"F

DV

0

I

I

'-----..J

MF6

V~

3

FILTER
OUT

0.1 j"F

J1fL

lDV
OV

CMOS
CLOCK

LEVELS

TLiH/S06S-14

a) Resistor Biasing of AGND

MF6

3

FILTER
OUT

JUL

,.

IOV
OV

CMOS
CLOCK
LEVELS

TL/H/5065-15

b) Using Op·Amp 2 to Buffer AGND
FIGURE 4. Single Supply Operation

7-127

~
:::IE

Application Hints (Continued)
24 kJl

5 kJl

22 kJl

V-~V+

FilTER IN
8

nlTER

VOSADJ
7

OUT

Vos

FilTER
IN

3

FilTER
OUT

ADJ
8

3

7

6TH ORDER
BUTTERWORTH

nlTER

6TH ORDER
BUTTERWORTH

t.lF6

FilTER
(a)
AGND

TL/H/5065-16

(b)
TUH/6065-17

FIGURE 5. Vas Adjust Schemes
Schmitt-trigger threshold voltage levels can change significantly causing the RIC oscillator's frequency to vary greatly
from part to part.

FilTER
INPUT >--.IIIVY--+-1

Where accuracy in fe is required an external clock can be
used to drive the CLK R input of the MF6. This input is TTL
logic level compatible and also presents a very light load to
the external clock source (- 2 /LA) with split supplies and
L. Sh tied to system ground. The logic level is programmed
by the voltage applied to level shift (L. Sh) pin (See the Pin
description for L. Sh pin).

RIM

TUH/6065-18

a) Equivalent Circuit for MF6 Filter Input

1.2 POWER SUPPLY BIASING
The MF6 can be biased from a single supply or dual split
supplies. The split supply mode shown in Figures 2 and 3 is
the most flexible and easiest to implement. As discussed
earlier split supplies, ± 5V to ± 7V, will enable the use of
TTL or CMOS clock logic levels. Figure 4 shows two
schemes for Single supply biasing. In this mode only CMOS
clock logic levels can be used.
1.3 OFFSET ADJUST
The VosADJ pin is used in adjusting the output offset level
of the filter section. If this pin is not used it must be tied to
the analog ground (AGND) level, either mid-supply for single
ended supply operation or ground for split supply operation.
This pin sets the zero reference for the output of the filter.
The implementation of this pin can be seen in Figure 5. In
5(a), DC offset is adjusted using a potentiometer; in 5(b), the
Op-Amp integrator circuit keeps the average DC output level at AGND. The circuit in 5(b) is therefore appropriate only
for AC-coupled signals and signals biased at AGND.

TL/H/5085-19

b) Actual Circuit for MF6 Filter Input
FIGURE 6. MF6 Filter Input
transferred to. the feedback capacitor. The total transfer of
charge in one clock cycle is therefore = ClnVln, and since
current is defined as the flow of charge per unit time the
average input current becomes

a

1.4 INPUT IMPEDANCE

lin = OIT
(where T equals one clock period) or

The MF6 lowpass filter input (FILTER IN pin) is not a high
impedance buffer input. This input is a switched capacitor
resistor equivalent, and its effective impedance is inversely
proportional to the clock fraquency. The equivalent circuit of
the input to the filter can be seen in Figure 6. The input
capacitor charges to the input voltage (VI,,) during one half
of the clock period, during the second half the charge is

ClnVln
.
lin = - T - = ClnVinfClK
The equivalent input resistor (Ri,,) then can be defined as
Rin

1

= Vln/iin = - C
f

InClK
The Input capacitor is 2 pF for the MF6-50 and 1 pF for the

7-128

~--------------------------------------------------------------.~

~

Application Hints (Continued)
MF6-100, so for the MF6-100
1

x 1012

1 X 1012

fCLK

fe

Since the maximum overall gain error for the MF6 is
± 0.3 dB with a Rs :s; 2 kO the actual gain error for this case
would be +0.21 dB to -0.39 dB.

1 X 1010

R =---=---=--.n

x 100

fe

1.5 CUTOFF FREQUENCY RANGE
The filter's cutoff frequency (fcl has a lower limit caused by
leal(age currents through the internal switches discharging
the stored charge on the capacitors. At lower clock frequencies these leakage currents can cause millivolts of error, for
example:

and
5 X 1011
1 X 1010
5 X 1011
R =---=---=--.n
fCLK
fe X 50
fe
for the MF6-50. As shown in the above equations for a given
cutoff frequency (fcl the input impedance remains the same
for the MF6-50 and the MF6-100. The higher the clock to
center frequency ratio, the greater equivalent input resistance for a given clock frequency. As the cutoff frequency
increases the equivalent input impedance decreases. This
input resistance will form a voltage divider with the source
impedance (Rsource). Since Rin is inversely proportional to
the cutoff frequency, operation at higher cutoff frequencies
will be more likely to load the input signal which would appear as an overall decrease in gain to the output of the filter.
Since the filter's ideal gain is unity its overall gain is given
by:

fCLK = 100 Hz, Ileakage = 1 pA, C = 1 pF

V

1pA
=10mV
1 pF (100 Hz)

The propagation delay in the logic and the settling time required to acquire a new voltage level on the capacitors increases as the MF6 power supply voltage decreases. This
causes a shift in the fCLK/fe ratio which will become noticeable when the clock frequency exceeds 250 kHz. The amplitude characteristic will stay within tolerance until fCLK exceeds 500 kHz and will peak at about 0.5 dB at the corner
frequency with a 1 MHz clock. The response of the MF6 is
still a reasonable approximation of the ideal Butterworth
lowpass characteristic as can be seen in Figure 7.

A Rin
y - Rin + Rsouree
If the MF6-50 or the MF6-100 were set up for a cutoff frequency of 10kHz the jnput impedance would be:

2.0 Designing with the MF6
Given any lowpass filter specification two equations will
come in handy in trying to determine whether the MF6 will
do the job. The first equation determines the order of the
lowpass filter required:

1 X 1010
Rin = 10kHz = 1 MO
In this example with a source impedance of 10k the overall
gain, if the MF6 had an ideal gain of 1 or 0 dB, would be:

n =

1 MO
Ay = 10 kO + 1 MO = 0.99009 or - 86.4 mdB

log (10°·1 Amin-1) - log (100.1 Amax - 1)

1\

!----=20~~f-c,t

5~

-30
-«l

~i\

.Io<"\"'
\--+
~r~ \ t \ - f - I - - - - - I - - -

~\

~'r-i'

,++,-H-lirl-r-.lT"H
:! -SO.l
.l .lll.l

i---JIH--4I-+--\HrH
~ -so 1-+l-+l-+-t\---iH
-ml--++--++---I\--++--+'-I

-6lL-~00~~~~~~~~~~

-6lL-~00~~~~~~~~5CK~

-«ll-t-t

-m H,rl-t-t-t,t--i,-Ht-Lj-1
-70 i--'\t-t-+t,r,tt+--i-;
10

100
lK
1(1(
FREQUENCY (Hz)

-70

llX1<

1--+\+-+1,H
1,1--+H+-

10

100
lK
1(1(
FREQUENCY (Hz)

llX1<
TL/H/5065-21

TUH/5065-20

FIGURE 7a_ MFS-100 ± 5V Supplies
Amplitude Response

I

FIGURE 7b_ MFS-50 ± 5V Supplies
Amplitude Response

..ll

10

!

-1~ I-I,§~ ~kr-

-211
-30 t -

l!i

l!i l!i

-«l

"

-70

\

00

100

i

l!i-

-70

\

~

lK

-30

~ -«l
:: -so
-m

I'~

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10

~ ~: ~ J~ -Il\- ~l

~ ~ Itt~-

;1;

_-so
-m
-6l

(1)

2 log (fs/fb)

-1~'

~-:~ 1l~~'11~

=

~

1(1(

J,

•

.t~ t~ ~~,

,
1---fH--aI,+--+l-f--H

-6l L--!00!;1l---;;~~--;~!"lL.......~!u'

5CK

10

llX1<

FREQUENCY (Hz)

100

lK

1(1(

llX1<

FREQUENCY (Hz)
TLlH/5065-23

TLlH/5065-22

FIGURE 7d. MFS-50 ± 2.5V Supplies
Amplitude Response

FIGURE 7e. MFS-l00 ±2.5V Supplies
Amplitude Response

7-129

:f

:s

Designing with the MF6 (Continued)
To implement this example for the 'MF6-50 the clock frequency will have to be set to fCLK = 50(1.116 kHz) = 55.8
kHz or for the MF6-100 fCLK = 100(1.116 kHz) = 111.6
kHz.

where n is the order of the filter, Amin is the minimum stopband attenuation (in dB) desired at frequency fs, and Amax is
the passband ripple or attenuation (in dB) at frequency fb. If
the result of this equation is greater than 6, then more than
a single MF6 is required.
The attenuation at any frequency can be found by the following equation:
'
Attn(f)

=

10 log [1

+ (100.1Amax-1) (flfb)2n] dB

2.2 CASCADING MFSs
In the case where a steeper stopband attenuation rate is
required two MF6's can be cascaded (Figure 9) yielding a
12th order slope of 72 dB per octave. Because the MF6 is a
Butterworth filter and therefore has no ripple in its passband, when MF6s are cascaded the resulting filter also has
no ripple in its passband. Likewise the DC and passband
gains will remain at 1VIV. The resulting response is shown
in Figure 10.
In determining whether the cascaded MF6s will yield a filter
that will meet a particular amplitude response speCification,
as above, equations 3 and 4 can be used, shown below.

(2)

where n = 6 (the order of the filter).
2.1 A LOWPASS DESIGN EXAMPLE
Suppose the amplitude response specification in Figure 8 is
given. Can the MF6 be used? The order of the Butterworth
approximation will have to be determined using eq. 1:
Amin

= 30 dB, Amax = 1.0 dB, fs = 2 kHz, and fb = 1. kHz
n

=

log (10 3 - 1) -log(10 0.1 - 1)
2 log(2)

= 5.96
n

Since n can only take on integer values, n. = 6. Therefore
the MF6 can be used. In general, if n is 6 or less a single
MF6 stage can be utilized.

Attn(f) = 10 log [1

= 30.26 dB

fs=2k

TL/H/5065-24

FIGURE 8. Design Example Magnitude Response
Specification Where the Response of the Filter Design
Must Fall Within the Shaded Area of the Specification
Since the MF6's cutoff frequency fe, which corresponds to a
gain attenuation of -3.01 dB, was not specified in this example it needs to be calculated. Solving equation 2 where f
= fe as follows:
b

+

(3)
(4)

6 (the order of each filter).

2_3 IMPLEMENTING A "NOTCH" FILTER WITH THE MFS
A "notch" filter with 60 dB of attenuation can be obtained by
using one of the Op-Amps, available in the MF6, and three
external resistors. The circuit and amplitude response are
shown in Figure 11.
The frequency where the "notch" will occur is equal to the
frequency at which the output signal of the MF6 will have
the same magnitude but be 180 degrees out of phase with
its input signal. For a sixth order Butterworth filter 180"
phase shift occurs where f = fn = 0.742 f e. The attenuation
at this frequency is 0.12 dB which must be compensated for
by making R1 = 1.014 X R2.
Since R1 does not equal R2 there will be a gain inequality
above and below the notch frequency. At frequencies below
the notch frequency (f < < f n), the signal through the filter
has a gain of one and is non-inverting. Summing this with
the input signal through the Op-Amp yields an overall gain
of two or + 6 dB. For f > > fn, the signal at the output of the
filter is greatly attenuated thus only the input signal will appear at the output of the Op-Amp. With R3 = R1 = 1.014
R2 the overall gain is 0.986 or -0.12 dB at frequencies
above the notch.

fREQUENCY (Hz)

e-

=

(10°. 05 Amax - 1) (f/fb)2n] dB

Equation 3 will determine whether the order of the filter is
adequate (n ,,; 6) while equation 4 can determine if the
required stopband attenuation is met and what actual cutoff
frequency (fe) is required to obtain the particular frequency
response desired. The design procedure would be identical
to the one shown in section 2.1.

This result also meets the design specification given in Figure 8 again verifying that a single MF6 section will be adequate.

f _f

log (100.05Amin_1) -log(100.05Amax-1)
2 log (fs/fb)

where n

Likewise, the attenuation at fs can be found using equation
2 with the above values and n = 6 giving:'
Atten (2 kHz) = 10 log [1 + (10 0.1 - 1) (2 kHz/1 kHz)12]

fb= lk

=

[(100.1(3.01 dB) - 1)]1/(2n)
(100.1 Amax _ 1)

100.301 - 1 ]1/12
= 1 kHz [ 100.1 _ 1
= 1.119kHz

where fe = fCLK/50 or fCLK/100.

7-130

Designing with the MF6 (Continued)
MF6

...

MF6

13

..,.!-

~

~

-~

8

I--I--l.J"""-l.. -

FILTER
IN

FILTER FILTER
OUT
IN
Vos ADJ AGND

FILTER
OUT

LSh

V-

CLKR

10

6

11

-::!:~=+5Vo----------'~-+---r------------~~-;------~
~=-5Vo-------------~~--~-----------------4-----------J

feLK

m

>------------....- - - - - - - - - - - - - - - - - - - '

LOGIC LEVELS
TL/H/S065-25

FIGURE 9. Cascading Two MF6s

10r--r~TTnT~--~----'

o 1-++!-++~,-Vr:x;:....r-I{"=lOV

-10

Cl
~

-20

~

-.40

...

...'"

0..

-30

~

f elk = 50kHz

\\

\\

~SN

II
F6

1--+-I-+t+tttt-~\rl-t-tt+tH

-so I--+-I-+t+tttt--H\\-\H-tt+tH

\

-EO 1--+-i-+++++++---',l+-IlH-t,+++H
-70 1--t--t--I-t+It!+-\-I+t++1-H
lWO MF6s ~
-8l 1---+--+-1-1"-H,,i"t
-t-N+ttH
1
-90 '---'-...!.....L...L.I.L.W._.L:-!....l-J.J..L..UJ
0.1- - s-----1O---------

,,1---1\-,

- FREQUENC¥-(Hz)TliH/S065-27

FREQUENCY (kHz)
TL/H/5065-26

FIGURE lOa. One MF6·50 vs. Two MF6·50s Cascaded

FIGURE lOb. Phase Response of
Two Cascaded MF6·50s

fI

7·131

If
:i

Designing with the MF6 (Continued)
VOSADJ

7
MF6

t---+<

R3

5Vs
OV.
fCll(

R2

Rl

+ ______.......

SIGNAL ......._ _ _ _ _ _
INPUT

.. NOTCH ..
FILTER OUTPUT
TLlH/5065-26

FIGURE 11a. "Notch" Filter

+10
0
'iii'

-10

:::>

-20

...

-30

~

...c
5"::E

-<40
-50

10

50

100

500

lK

FREQUENCY (Hz)
TL/H/5065-29

FIGURE 11b. MF6-50 "Notch" Filter Amplitude Response

7-132

Designing with the Mf6 (Continued)
2.4 CHANGING CLOCK FREQUENCY
INSTANTANEOUSLY
The MF6 will respond favorably to a sudden change in clock
frequency. Distortion in the output signal occurs at the tran·
sition of the clock frequency and lasts approximately three
cutoff frequency (fel cycles. As shown in Figure 12, if the
control signal is low the MF6·S0 has a 100 kHz clock mak·
ing fe = 2 kHz; when this signal goes high the clock frequency changes to SO kHz yielding 1 kHz fe.
The transient response of the MF6 seen in Figure 13 is also
dependent on the fe and thus the fClK applied to the filter.
The MF6 responds as a classical sixth order Butterworth
lowpass filter.

TLlH/5065-31

TL/H/5065-S0
fiN = 1.5 kHz (scope time base = 2 ms/div)

FIGURE 12. MFS-SO Abrupt Clock Frequency Change

FIGURE 13. MFS-SO Step Input Response, Vertical =
2V/dlv., Horizontal = 1 ms/dlv., fCLK = 100 kHz
the input signal contains a component at a frequency higher
than half the clock frequency, as in Figure 14a, that compo·
. nent will be "reflected" about fClK/2 into the frequency
range below fClK/2 as in Figure 14b. If this component is
within the passband of the filter and of large enough ampli·
tude it can cause problems. Therefore if frequency components in the input signal exceed fClK/2 they must be attenu·
ated before being applied to ihe-MF6 input. The necessary
amount of attenuation will vary depending on system reo
quirements. In critical applications the signal components
above fClK/2 will have to be attenuated at least to the fil·
ter's residual noise level. An example circuit is shown in
Figure 15 using one of the uncommitted Op·Amps available
in the MF6.

2.S ALIASING CONSIDERATIONS
Aliasing effects have to be tallen into consideration when
input signal frequencies exceed half the sampling rate. For
--the-MF6--this-equals-haIHhe-elock-frequeney-(fCtK).when--------------'--_ _ _ _ _ _ _ _ _ _ 1_ _ _ __

Is

-.!!. -I

Is

2

2

Is
2

-.!!. +1

Is

2

FREQUENCY

FREQUENCY
TLlH/5065-S7

TL/H/5065-38

(a) Input Signal Spectrum

(b) Output Signal Spectrum. Note that the input signal at
f5/2 + f causes an output signal to appear at f5/2 - f.

Figure 14. The phenomenon of aliasing in sampled-data systems. An input signal whose frequency Is greater than onehalf the sampling frequency will cause an output to appear at a frequency lower than one-half the sampling frequency.
In the MFS, fs = fCLK'

7·133

fI

~

:&

Designing with the MF6 (Continued)
VosADJ
7
Mr6
VOUT

C2

R4

R1

R2

R3

INV1
TlIH/50e5-54
10=

1
2...4R1R~IC2

Ho = R4fRs (Ho = 1 when Rs and R4 are omitted and V02 Is direc1ly tied to INV2):

Design Procedure:
plckCl
R2=_I_
20C10)0
lor a 2nd Order Butterworth 0 = 0.707

R2=~
ClIo

make Rl = R2
and
C2= _ _I_ _
(2'11'1oR1l2Cl
Note: The parallel combination 01 R4 (il used), Rl and R2 should be ;, 10 kO in order not to load Op·Amp #2.

FIGURE 15. Second Order Butterworth Anti-Aliasing Filter Using Uncommitted Op-Amp #2

7-134

tflNational Semiconductor

MFa 4th-Order Switched Capacitor Bandpass Filter
General Description

Features

The MF8 consists of two second-order bandpass filter
stages and an inverting operational amplifier. The two filter
stages are identical and may be used as two tracking second-order bandpass filters, or cascaded to form a single
fourth-order bandpass filter. The center frequency is controlled by an external clock for optimal accuracy, and may
be set anywhere between 0.1 Hz and 20 kHz. The ratio of
clock frequency to center frequency is programmable to
100:1 or 50:1. Two inputs are available for TTL or CMOS
clock signals. The TTL input will accept logic levels referenced to either the negative power supply pin or the ground
pin, allowing operation on single or split power supplies. The
CMOS input is a Schmitt inverter which can be made to selfoscillate using an external resistor and capacitor.
By using the uncommitted amplifier and resistors for negative feedback, any all-pole (Butterworth, Chebyshev, etc.)
filter can be formed. This requires only three reSistors for a
fourth-order bandpass filter. Q of the second-order stages
may be programmed to any of 31 different values by the five
"Q logiC" pins. The available Q values span a range from
0.5 through 90. Overall filter" bandwidth is programmed by
connecting the appropriate Q logic pins to either V+ or V-.
Filters with order higher than four can be built by cascading
MF8s.

•
•
•
•

Center frequency set by external clock
Q set by five-bit digital word
Uncommitted inverting op amp
,4th-order all-pole filters using only three external
resistors
• Cascadable for higher-order filters
• Bandwidth, response characteristic, and center
frequency independently programmable
II Separate TTL and CMOS clock inputs
• 18 pin 0.3" wide package

Key Specifications
• Center frequency range 0.1 Hz to 20 kHz
• Q range 0.5 to 90
• Supply voltage range 9V to 14V (±4.5V to ±7V)
• Center frequency accuracy 1 % over full temperature
range

Typical Application & Connection Diagrams
Dual-In-Line Package

120k.o.

---

OUI

30k.o.

18

C

30k.o.

+5V
+5V

JlI1..r

B

2

17

D

A

3

16

AGND

4

15

F1 IN
F1 OUT

F21N

5

14

A OUT

F2 OUT

6

A IN

mClK

7

V+

CMOS ClK

8

V-

RC

9

50/100
TLlH/B694-2

-5V

CLOCK IN

-5V

+5V

Order Number MF8CCJ
orMF8CCN
See NS Package Number
J18Aor N18A

-5V
TLlH/B694-1

Fourth-Order Butterworth Bandpass Filter

7-135

Top View

fI

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VS = V+ - V-I
-0.3V to + 15V
V- -0.3VtoV+ +0.3V
Voltage at any Input (Note 2)
Input Current at any Input Pin (Note 2)
±1 mA
±1 mA
Output Short·Circuit Current (Note 7)
Power Dissipation (Note 3)
500mW
-65·C to + 150·C
Storage Temperature
Soldering Information:
J Package:
10 sec.
N Package:
10 sec.
SO Package:
Vapor Phase (60 sec.)
Infrared (15 sec.)
ESD rating is to be determined.

See AN·450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering sur·
face mount devices.

Operating Ratings (Note 1)
Temperature Range
TMIN ~ TA ~ TMAX
MF8CCN
O·C ~ TA ~ +700C
MF8CCJ
-40·C ~ TA ~ +85·C
SupplyVoltage(Vs = V+ - V-I
+9Vto +14V
fClK x Q Range.
for 10 Hz ~,fClK ~ 250 kHz
for 250 kHz ~ fClK ~ 1 MHz

260·C
3000C
215·C
220·C

anyQ
fClK x Q ~ 5 MHz

Filter Electrical Characteristics The following specifications apply for V+ = +5V, V- = -5V, CLOAD =
50 pF and RLOAD = 50 kO on filter output unless otherwise specified. Boldface limits apply for TMIN to TMAX: all other limits
TA = TJ = 25·C.
MF8CCN
Parameter
(Notes 4, 5)

Symbol

Ho
Q

Gain atfo

R

fClKlfo
Gain atfo
Q

Ho
Q
R
Ho
Q
R

Q

fClK/fo
Gain atfo
Q.

Conditions

fClK = 250 kHz
100:1
ABCDE = 11100
fClK = 250 kHz
100:1
ABCDE = 10011
fClK = 250 kHz
50:1
ABCDE =' 00001

fClK/fo
Gain atfo

Typical
(Note 9)
6.02 ±.05

6.02 ±0.2

3.92 ±2% 3.92 ±10%
99.2 ±0.3% 99.2 ±1%
6.02 ±0.2

6.02 ±0.5

15.5 ±3% 15.5 ±12%

AR/RTH fClKlfo Deviation Vs = ±5V ±5%
from Theoretical fClK ~ 250 kHz
(See Table I)
Q

Q

fClK = 250 kHz, 50:1
ABCDE = 00110

Dynamic Range ABCDE = 11100
ABCDE = 10011
(Note 6)
ABCDE = 00001
Clock
Feedthrough

Filter and Op Amp
fClK ~ 250 kHz
Q~ 1
Q> 1

Is

Maximum Supply fClK = 250 kHz, no
Current
loads on outputs

Vos

Maximum Filter
Output Offset
Voltage

fClK = 250 kHz, Q = 4
50:1
100:1

Minimum Filter
Output Swing

RlOAD = 5kO
(Note 6)

VOUT

Typical
(Note 9)

Tested
Limit
(Note 10)

6.02 ±0.05

6.02 ±0.2

3.92 ±2%

3.92 ±10%

Design Units
Limit
(Note·ll)
dB

99.2 ±0.3% 99.2 ±1% .

,

99.7 ±0.3% 99.7 ±1%

6.02 ±0.2

6.02 ±0.5

15.5 ±3%

15.5 ±12%

99.7 ±0.3%

99.7±1%

5.85 ±0.4

5.85 ±1

5.85,±0.4

5.85 ±1

55 ±5'Yo

55 ±14%

55 ±5%

55 ±14%

dB

dB

49.9 ±0.2% 49.9 ±1%

49.9 ±0.2% 49.9 ±1%

Vs = ±5V ±5%
6.02 ±0.5
fClK ~ 250 kHz
AQ/QTH Q Deviation from Vs = ±5V ±5%
Theoretical
±5%
fClK ~ 250 kHz, Q > 1
(See Table I)
fClK ~ 100 kHz,
±2%
1 

'"'
~

i

~

-10

100
90

~

~

!i!

TA~
NO LOAD

"

10

~O

102

loJ

104

!z

"

105

FREQUENCY (HI)

Q~5~

-....;;:

-D.2
-D.4

~=15.8

"\.

-os

~
<> -os

'\

-ID
-50

100

g

25

:li

15

<>

I-

TA=+25~

'e:"'

'-

Vs=t5V
RL=50 k4

0

I

f~~~rp~

<>

Q=57 \
-25

0

25

50

75

-20

!:;

-30

il:
iil

-40

"

10'

-50

100

20
10
5
0
-51-10 f-15 f-

Q=57
TA=+25"C
Vs=t5V
RL=50k4

-20 f-

-f~~~rp~

-25

106
CLOCK FREQUENCY (Hz)

Negative Power
Supply Rejection
20

!.

VS=t5V.
10 'CLr 250 kHz
Q=15.8
TA=25CC
-10

.B
;J

I\..

20

~

vs-:t5v.L RL=50k4
CL=50pFQ::4

50:1 and 100:1

Q=4

20

I\..

40
30

z

0

Ic~l25kHz

Q=4

0

Positive Power
Supply Rejection

I

50

'e:"'

'\f

CLOCK FREQUENCY (Hz)

vs~

I\..

Q.2

I

t7

Op Amp-Open Loop
Frequency Response

......

<>

!C

SUPPLY VOLTAGE (V)

!

Q.4

~

I

60
70
60

~

Q.6

Q vs Clock Frequency-

-ID
t6

75

Q.B

Q vs Clock Frequency-

-5 f-

<>

:t5

50

g

TEMPERATURE (CC)

':t4

25

t7

TEMPERATURE (CC)

I-

Q=4

/

-os

0

:t6

50:1 and 100:1

!C

-

f-

Q~'5.B

IL I - ~

f-

fo'"

C=

vr

O_/,

z

t5

Q vs TemperaturelD

J

r

Q=57

V

V

V

SUPPLY VOLTAGE (V)

50:1 and 100:1

lD

~=50pF

L

Q=57
0 Q=4

/'

-D.05

/

ODS

./

",

V

t4

~=50pF

0

!C

-0.01

105

Vs=:t5V
RL=50 k4-----, '---

~

.

1111

'CLK=125,~

Is'

'CLK= 125 kHz
T.=25CC
CUi _ RL=50k4

ODI

fCLK/fo Ratio vs
Temperature-50:1 Mode

g

il';

~

'CLK= 125 kHz
TA=25CC

f- RL=50k4
ODZ f-~=50pF

CLOCK FREQUENCY (Hz)

fCLK/fo Ratio vs
Temperature-100:1 Mode

E

0,03

,~1

III

10'

0D4

;

~

III

97

1111

il';
o

~I~

Vs=t5V
TA=25CC
NO LOAO

II-

III

I~'o LOAD

~

99

~If

Vs=:t5V
TA=25CC

Voltage-50:1 and
100:1 Mode

!z

I
100:1

I'-..

J
~ 50:1

".

r-

I

!.

VS=t5V,
10 'c~250kHz
Q=15.B
TA=25CC
-10 l-

B -20 f-

i;l

i.
:::>

-30

I-

-40

~

-50

fI

if
~

I
107

103
FREQUENCY (Hz)

FREQUENCY (Hz)
TL/H/8694-24

7-139

co

u..
::a:

Typical Performance Characteristics

!
~
~

~
~
z
o

~

'"
~

Positive Swing vs
Load Resistance
600
500

!

JJ.l.Uj

VS=i5V
T.=25OC

OP-ANP

400

200

1111

~

RLTER

!
ji!

1111

iii

1~

103

100

-100

~

-300

Vs=i5V

-500

OA

V

0.1

i'QP-AMP
z

i6

i7

~

-0.1

~

-D.2

iii

;'

L

-so

-25

'\
!'\.

.'\

~

a

-2
-4
-6
-6

I'\.
"\

V

-1

25

0

50

75

100

ji!

o.OS

VS=iSV
Rl =5kll

V

iii
"e:
0

~

~

25

50

75

100

/'
/

-0.05

V

/

-0.10

~

/

/

-so

-25

0

60

so

!

N

~

14
12
10

~

12.5

~

10.0
7:'

s.o

"~
~

O

o
-2

102

~

100

V

/. , /

/

z

i
t:;
~

o

i7

~

100:1

20
10
-10
-20
-30

V

~50:1

./

V

A

-40
is

:t4

'"

i6

i7

SUPPLY VOLTAGE (V)

Filter Offset Voltage vs Clock
Frequency-50:1 and 100:1

Filter Offset Voltage vs
Temperature-50:1 and 100:1

TA=2SOC
Vs=iSV
NO LOAD
f-Q=4

VS=t5V
'elK= 2S0 kHz
NO LOAD
V'N=OV
-Q=4

0.0
-2:'

-S.O
;:; -7:'
t:; -10.0
~ -12:'
o
103
G:

7S

TA-2SOC.I.
'elK= 2S0 kHz

30 r- Q=4

2:'

\

SO

40 f- NO lOAD

/

i6

25

Filter Offset Voltage
vs Supply Voltage

/

is

V

TEMPERATURE (OC)

SUPPLY VOLTAGE (V)

Filter Offset Voltage vs
Q-50:1 and 100:1

1()""1

0

U

TEMPERATURE (OC)

-4
-6

0.10

!;;:

z

TA=2SOC
'elK= 2S0 kHz
NO lOAD
r-V'N=OV

~

-50 -25

/

V

/

~

Supply Current vs
Supply Voltage

I'\.

-10

~

/

i7

Positive Swing vs Temperature
(Filter and Op Amp)

TEMPERATURE (OC)

Vs=i5V
'elK= 250 kHz
NO lOADV'N=OV -

"

i6

SUPPLY VOLTAGE (V)

-D.3

Supply Current vs
Temperature

I\.

is

(!)

SUPPLY VOLTAGE (V)

"

r-..." I"-...

r-.... ........

105

VS=i5V
Rl=skn

ji!

10

-5

11111
1~

103

02

-'l

OP-AMP

-6

TA=jJ]

-600

V V
./.:!""

~

FilTER

OP-AMP

Negative Swing vs Temperature
(Filter and Op Amp)

V

is

~

-4

LOAD RESISTANCE (n)

£

v:

iii

\

Positive Swing vs
Supply Voltage

FILTER"""':

T.=2SOC
Rl = 5 kll

~

ji!

LOAD RESISTANCE (n)

T.=2SOC
Rl =5kll

-3

-200

z

1111
-100

Negative Swing vs
Supply Voltage

~

~
~

RLTER

V

100

Negative Swing vs
Load Resistance

on

II

300

(Continued)

-1

.....

-2

1~

-3

105

CLOCK FREQUENCY (Hz)

-so

-

-25

0

/

V

/
/
25

so

75

100

TEMPERATURE (OC)
TLlH/6694-2S

7-140

1.0 Application Information

(Continued)

AGND

SO/1 00

TIL
CLK

CMOS
CLK

TUH/B694-3

FIGURE 1. Simplified Block Diagram of the MF8

Vour2

4

AGND
10

7

......

~--~.--~-~-~---~~

TL/H/B694-4

FIGURE 2a. Separate Second-Order "Tracking" Filters

Your

fI
TL/H/B694-5

FIGURE 2b. Fourth-Order Bandpass Made by Cascading Two Second-Order Stages

7-141

=r-----------------------------------------------------------------~--

u.
::i

1.0 Application Information (Continued)
R2

r-.....JIM,....-------------...-v

OUT

RF

TL/H/8894-6

FIGURE 2c. Multiple Feedback Loop Connection
Clock signals derived from a crystal-controlled oscillator are
recommended when maximum center frequency accuracy
is desired, but in less critical applications the MFa can generate its own clock signal as in Figures 30 and 40. An external resistor and capacitor determine the oscillation frequency. Tolerance of these components and part-to-part variations in Schmitt-trigger logic thresholds limit the accuracy of
the RC clock frequency. In the self-clocked mode the TTL
Clock input should be connected to either pin 11 or pin 12.

1.2 CLOCKS
The MFa has two clock input pins, one for CMOS logic levels and the other for TTL levels. The TTL (pin 7) input automatically adjusts its switching threshold to enable operation
on either single or split power supplies. When this input is
used, the CMOS logic input should be connected to pin
II(V-). The CMOS Schmitt trigger input at pin a accepts
CMOS logic levels. When it is used, the TTL input should be
connected to either pin 11 (V-) or pin 12 (V+). The basic
clock hookups for single and split supply operation are
shown in Figures 3 and 4.

,.
A
AGND
F2 IN
F2 OUT
-5V
5V J 1 J L
-5V

17

2

16

,.
15

MFa

13

mCLK

12

CMOS ClK

II

RC

10

Fl IN
FlOUT
A OUT

A IN
V+

5VJ1JL
OV

+5V

v-

-5V

50/100

~--+5V

CMOS CLK

-5V

llf-!..---5V
10 50/100

RC

,TLlH/8694-7

TL/H/8694-8

(a) MFa Driven with CMOS Logic Level Clock

(b) MFa Driven with TTL Logic Level Clock

C
B
A
AGND
F2 IN
F2 OUT

-5V

C

v

TTL ClK
CMOS ClK
RC

1

18

2

17

3

16

4
5

15
MFB

14

6

13

7

12

8

11

9

10

D

fClK

1

=

RClnl(VS-vr.) (VT+)I
Vs - VT +
VT_
Typically for Vs· = 10V
1
feLK = 1.69FiC

E
F1 IN
FlOUT
A OUT
A IN

V+
V-

·Vs

= V+

- V-

+5V
-5V

50/100
TL/H/8694-9

(c) MFa Driven with Schmitt Trigger Oscillator
FIGURE 3. Dual Supply Operation

7-142

1.0 Application Information

(Continued)
pled to the filter input or biased to V+ 12. It is strongly recommended that each power supply pin be bypassed to
ground with at least a 0.1 J.tF ceramic capacitor. In single
supply applications, with V- connected to ground, V+ and
AGND should be bypassed to system ground.

1.3 POWER SUPPLIES AND ANALOG GROUND
The MFa can be operated from single or dual-polarity power
supplies. For dual-supply operation, the analog ground (pin
4) should be connected to system ground. When single supplies are used, pin 4 should be biased to V+ 12 as in Figures
3 and 4. The input Signal should either be capacitively cou-

18

D

17

E

3

16

AGND

4

15

FI IN
FlOUT

F2 IN

5

14

A OUT

C

IOV
10k

B

2

A

•
MF8

F2 OUT

13

A IN

-%-

TTL ClK

7

12

V+

CMOS ClK

8

11

V-

RC

9

10

50/100

JLf[IOV

5V DC

+IOV

OV
TLlH/8694-10

(a) MFa Driven with CMOS Logic Level Clock

10V
10k

V-0.IP.F

10k

C

I

B

2

•

18

D

17

E

A

3

16

FI IN

AGND

4

15

FlOUT

F2 IN

5

MF8

F2 OUT
JLf[+SV
OV

TTL ClK

7

CMOS ClK

8

RC

9
Tl/H/B694-11

------(b}-MF8-Driven-with-1"I'"b-~gic'Glock----------------I----

C

10V
10k

10k

18

D

17

E

3

16

FI IN

AGND

4

IS

F1 OUT

B

2

A

e

F2 IN

5

14

A OUT

F2 OUT

6

13

A IN

MF8

fClK ~
RCIN

r

I s=

Typically for Vs

Vs
~

VT-) (VT+)
VT+
VT10V

1

fClK

TTL ClK

7

12

V+

CMOS ClK

8

11

V-

RC

9

10

50/100

= 1.69 RC

+IOV

TLlH/B694-12

(c) MFa Driven with the Schmitt Trigger Oscillator
FIGURE 4. Single supply operation. The AGND pin must be biased to mid-supply.
The Input signal should be dc biased to mid-supply or capacitor-coupled to the input pin.

7-143

I

II

1.0 Application Information (Continued)
1.4 MULTIPLE FEEDBACK LOOP CONFIGURATION
The multi·loop approach to building bandpass filters is high·
Iy flexible and stable, yet uses few external components.
Figure 5 shows the MFB's internal operational amplifier and
two second·order filter stages with three external resistors
in a fourth·order multiple feedback configuration. Higher-order filters may be built by adding more second-order sections and feedback resistors as in Figure 6. The filter's response is determined by the clock frequency, the clock-tocenter-frequency ratio, the ratios of the feedback resistor
values, and the as of the second-order filter sections. The
design procedure for multiple feedback filters can be broken
down into a few simple steps:

HOIP

-.L
"rfAx
T

w..1"---saw----I
~.
.-..-.. -.-.•....•.•...•.
·..... ....
...:...~..,
·..:.....-.......- :.....:..
:
_: •• _ct •• _
•••• : ••••
.- .. - ....._
1...."-- .- •• .. -•• .
••••
r-;'1--;... •••• ••
•••••••• ..-- _....
...- ... ....- ..- ..- .

.-. . . . . .-..-.. .. . . T'

• ••••••••• +--BW--+ •• - ••••••. AMIN

fC1

IOBP

fC2

FREQUENCY
TL/H/8694-15

1) Determine the characteristics of the desired filter. This
will depend on the requirements of the particular application. For a given application, the required bandpass response can be shown graphically as in Figure 7, which
shows the limits for the filter response. Figilre 7 also makes
use of several parameters that must be known in order to
design a filter. These parameters are defined below in terms
of Figure 7.

FIGURE 7. Graphical representation of the amplitude
response specifications for a bandpass filter. The
filter's response should fall within the shaded area.

IDENTICAL SECOND ORDER STAGES

TL/H/8B94-13

FIGURE 5. General fourth·order multiple-feedback bandpass filter circuit. MFa pin numbers are shown.
RN
RN- 1
R3
R2
Ro

R,

VIN

TUH/8694-14

FIGURE 6. By adding more second-order filter stages and feedback resistors,
higher order multiple-feedback filters may be built.

7-144

3::

1.0 Application Information

"T1

(Continued)

Q)

Table I shows the available 0 values; the nearest value is
8.5, which is programmed by tying pins 1, 2, 3, and 18 to V+
and pin 17 to V-.

fC1 and fC2: The filter's lower and upper cutoff frequencies.
These define the filter's passband.
.
fS1 and fS2: The boundaries of the filter's stopband.

Note that the resistor values obtained from the tables are
normalized for center frequency gain Hesp = 1. For different gains, simply divide Ro by the desired gain.
5) Choose the clock-to-center-frequency ratio. This will
nominally be 100:1 when pin 10 is connected to pin 12(V+)
and 50:1 when pin 10 is connected to pin 11(V-). 100:1
generally gives a response curve nearer the ideal and fewer
(if any) problems with aliasing, while 50:1 allows operation
over the highest octave of center frequencies (10kHz to 20
kHz). Supply the MF8 with a clock Signal of the appropriate
frequency to either the TTL or CMOS input, depending on
the available clock logic levels.

BW: The filter's bandwidth. BW = fC2 - fC1'
SBW: The width of the filter's stopband. SBW = fS2 - fS1.
10: The center frequency of the filter. fo is equal to the geometric mean of fC1 and fC2: fo = ~fC1fC2' fo is also equal to
the geometric mean of fS1 and fS2.
Hosp: The nominal passband gain of the bandpass filter.
This is normally taken to be the gain at fo.
fo/BW: The ratio of the center frequency to the bandwidth.
For second-order filters, this quantity is also known as "0".
SBW/BW: The ratio of stopband width to bandwidth. This
quantity is also called "Omega" and may be represented by
the symbol "0".

TABLE I. Q and Clock-to-Center-Frequency Ratio
Versus Logic Levels on "Q-set" Pins

Amax: The maximum allowable gain variation within the filter
passband. This will depend on the system requirements, but
typically ranges from a fraction of a dB to 3 dB.

50:1 mode

100:1 mode

Amin: The minimum allowable attenuation in the stopband.
Again, the required value will depend on system constraints.

ABCDE

FCLK/Fo

Q

FCLK/Fo

Q

2). Choose a Butterworth or Chebyshev response characteristic. Butterworth bandpass filters are monotonic on either side of the center frequency, while Chebyshev filters
will have "ripple" in the passband, but generally faster attenuation outside the passband. Chebyshev filters are specified according to the amount of ripple (in dB) within the
passband.

10000
11000
01000
10100
00100
01100
11100
01010
10010
10110
00010
11110
00110
11001
11010
11101
01001
10011
10101
01110
10001
10111
11011
11111
00101
01011
00111
00001
01101
00011
01111

43.7
45.8
46.8
48.4
48.7
48.9
49.2
49.3
49.4
49.4
49.5
49.6
49.6
49.6
49.7
49.7
49.7
49.7
49.7
49.7
49.8
49.8
49.8
49.8
49.8
49.8
49.8
49.9
49.9
49.9
49.9

0.45
0.71
0.96
2.0
2.5
3.0
4.0
5.0
5.7
6.4
7.6
8.5
10.6
11.7
12.5
13.6
14.7
15.8
16.5
17
19
22
27
30
33
40
44
57
68
79
90

94.0
95.8
96.8
98.4
98.7
98.9
99.2
99.3
99.4
99.4
99.5
99.6
99.6
__
99~6__
99.7
99.7
99.7
99.7
99.7
99.7
99.8
99.8
99.8
99.8
99.8
99.8
99.8
99.9
99.9
99.9
99.9

0.47
0.73
0.98
2.0
2.5
3.0
4.0
5.0
5.7
6.4
7.6
8.5
10.6

3) Determine the filter order necessary to meet the response requirements defined above. This may be done with
the aid of the nomographs in Figures 8 and 9 for Butterworth and Chebyshev filters. To use the nomographs, draw
a line through the desired values on the AMAXI AMIN scales
to the left side of the graph. Draw a horizontal line to the
right of this point and mark its intersection with the vertical
line corresponding to the required ratio SBW/BW. The reqUired-filter order will be equal to the number of the curve
falling on or just above the intersection of the two lines. This
is illustrated in Figure 10 for a Chebyshev filter with 1 dB
ripple, 30 dB minimum attenuation in the stopband, and
SBW/BW = 3. From the Figure, the required filter order is
6.
4) The design tables in section 2.0 can now be used to find
the component values that will yield the desired response
for filters of order 4 through 12. The "Kn" give the ratios of
resistors "Rn" to RF, and KQ is 0 divided by fo/BW.
As an example of the Tables' use, consider a fourth-order
Chebyshev filter with 0.5 dB ripple and fo/BW = 6. Begin by
choosing a convenient value for RF, such as 100 kO. From
the "0.5 dB Chebyshev" filter table, Ko = Ro/RF = 1.3405.
This gives Ro = RF X 1.345 = 134.05k. In a similar manner, R2 is found to equal 201.61 k. 0 is found using the
column labeled KQ. This gives 0 = KQ x fo/BW = 8.4174.

7-145

r--1'L1

12.5
13.6
14.7
15.8
16.5
17
19
22
27
30
33
40
44
57
68
79
90

fII

IX)

La.

::i

1.0 Application Information (Continued)
in numerical order: Filter 1 (pins 16 and 15) should always
precede Filter 2 (pins 5 and 6). If a second MFa is used,
Filter 2 of the first MF8 should precede Filter 1 of the second MF8, and so on.
.
.'

Higher-order filters are designed in a similar manner. An
eighth-order Chebyshev with 0.1 dB ripple, center frequency
equal to 1 kHz, and 100 Hz bandwidth, for example, could
be built as in Figure 11 with the following component values:
Ro = 79.86k
RF = lOOk
R2 = 57.82k
Ra = 188.08k
R4 = 203.42k
pins I, 3, 17 and 18 high, pin 2 low. For 100:1 clock-to-center-frequency ratio, pin lOis tied to V+ and the clock frequency. is 100 kHz. For 50:1 clock-to-center-frequency ratio,
pin 10 is tied to V- and the clock frequency is 50.kHz.

Dynamic Considerations
Some filter response characteristics will result in high gain
at certain intemal nodes, particularly at the op amp output.
This can cause clipping in intermediate stages even when
no clipping is evident at the filter output. The consequences
are significant distortion and degradation of the overall
transfer function. The likelihood of clipping at the op amp
output becomes greater as RF/Ro increases. As the design
tables show, RF/Ro increases with increasing filter order
and increasing ripple. It is good practice to keep out-of-band
input signal levels small enough that the first stage can't
overload.

When building filters of order 4 or higher, best performance
will always be realized when the filter blocks are cascaded

7-146

iii:

~

AMAX(dB)

2

1

AM1N(dB)

--

-~

3

4

678910

5

12
40- r11
140 II

10

130 -

V

120 20- I-

V

9

110-

V

V

100 10- r9
8
7
6

5
4
3

2
1
0.8
0.6
0.4
0.3
0.2

___Q.J- r0.09
0.06
0.04
0.02

0.01- r0.005

8

90-

12/

80- ---

/

7

!f

70- --60- ---

5
I

108

----- -

4

3
I-

VII /
V

2

J. '//
III '/ V

1

--

,

-~

VI I J

IV
II /

l-

6
4
2
I
0.5

-l- I---

01

2

i

1/

II'

/~

./

/

II'~

~I

L

./

;,

,,/

V

~""

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io" io"

-

.... " , .....
n=2
;,;..-

//£ /' k...- ........

~".,-

I

/

V'

V

!78

I

V'

V

J

30- 20

,V

J
V
// 1

50- --40- ---

V

10 I
L

6

V

3

4

5

678910

SBW
BW
TL/H/8694-16

FIGURE 8. Butterworth Bandpass Filter Design Nomograph

•

2

3

45678910
I
1/

I
I

V

II

121/

j

/

/

/

J

1/

/

I

II /
I II

V
1/

II

1I

J
L

I

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V

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V

V 10 11

I I

If

V

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I

lL

1I

1/

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V

j.o'

/ II / V
IJ I /
1/ VV
1/ II J

~

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./

fi, 'I

'/ I) v
11 /

i/J!/ /'" /

V

n=2 1,.-1--- i-"'''''''"

/

...- ,;;;.

,~

2

3

4

5

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SBW
BW
TL/H/6694-17

FIGURE 9. Chebyshev Bandpass Filter Design Nomograph

7·148

2

--

-r-

45678910

3

1/

12

If

I
40 -

I

11

'I

140 --

12 I
10

130 --

201--

9
8

8

90-80-70 - 60--

'-N

1.0
0.8
0.6
0.4
0.2

0.1 -

7

0.02

10-8
6
4
2
1

0.5--

--

3

2

/

I

/

5

-~4

20- "

-'-

If

6

/ I/

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//

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II /

/1 II
'/ J

/

Ii II
1 {II /
////
~

I!

1/

II

V

V

V

6

/
/

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/

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V

i-"i-'

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I

J

If

V L

I 1//

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V

I

j

30

0.06
0.04

0.005

V

-

40- -

~-0;08

0.01 -i-

1/

11 n

7

6
5
4

J

V -/
/ /

100 -r10j - -

If

I

9

110-'-

V
V

il

120 -:-

'I

J

/

V

/

V

-

~
n=2
,;;;;. .... ~

V

V
2

.......

3

i"'"

45678910
TL/H/8694-18

FIGURE 10. Example of Chebyshev Bandpass Nomograph Use.
SBW
Amax = 1 dB, Amln = 30 dB, and BW = 3, resulting In n = 6.

7-149

•

:f
::E

1.0 Application Information

(Continued)

R.

~~R3~~~---------------------------------------------------------------------------~~~~

-5V

-5V

ClOCK IN

...nn.rL
TLlH/8694-19

FIGURE 11. Eighth-Order multiple-feedback bandpass filter using two MFSs. The circuit shown
accepts a TTL-level clock signal and has a clock-to-center-frequency ratio of 100:1.
1.5 TRACKING AND CASCADED SECOND-ORDER
BANDPASS FILTERS
The individual second-order bandpass stages may be used
as "stand-alone" filters without adding external feedback
resistors. The clock frequency and Q logic voltages set the
center frequency and bandwidth of both second-order
bandpass filters, so the two filters will have equivalent responses. Thus, they may be used as separate "tracking"
filters for two different signal sources as in Figure 2a, or
cascaded as in Figure 2b. For individual or cascaded second-order bandpass filters, the -3 dB bandwidth and the
amplitude response are given by the following two equations:
BW(-3) =

H(s) = [2 x

~~2(1/N) -

_6
s

2

3

4

5

ssw

6

7

8

9 10

f!II

TLlH/8694-21

1

(1)

_]N

(2)

FIGURE 13. Design Nomograph for Cascaded
Identical Second-Order Bandpass Filters

s2+ 6S+W02

r-~~---~-r---~~

10

1-+--1'--+-+-+--1

= the Q of each second order bandpass stage
= the center frequency of the filter in Hertz

Wo

= 2 '/Tfo = the center frequency of the filter in radians

per second

where
BW( - 3) = the - 3 dB bandwidth of the overall filter
~

Q
fo

N

n

= the number of cascaded second-order stages = 2

H(s) = the overall filter transfer function
H(s) for a second order bandpass filter is plotted in Figure
12. Curves are shown for several different values of Q. Center frequency is normalized to 1 Hz and center-frequency
gain is normalized to 0 dB.

0_1

To find the necessary order n for cascaded second-order
bandpass filters using the nomograph in Figure 13, first determine the -3 dB bandwidth BW(-3), stopband width
SBW, and minimum stopband attenuation Amin' Draw a vertical line up from SBW/BW(-3), and a horizontal line
across from Amin' The required order is shown on the curve
just above the point of intersection of the two lines. Remember that each second-order filter section will have a center
frequency gain of 2, so the overall gain of a cascaded filter
will be 2N.

TL/H/B694-20

FIGURE 12. H(s) For second-order bandpass filters with
various values of Q. Ho normalized In each case to 0 dB.

Cascading filters in this way may provide acceptable performance when minimum external parts count is very impor-

7-150

1.0 Application Information

(Continued)
was f8/2 - 10 Hz. This phenomenon is known as "aliasing". Aliasing can be reduced or eliminated by limiting the
input signal spectrum to less than f8/2. This may in some
cases require the use of a bandwidth-limiting filter (a simple
passive RC network will generally suffice) ahead of the MFa
to attenuate unwanted high-frequency signals. However,
since the clock frequency is much greater than the center
frequency, this will usually not be necessary.

tant, but much greater flexibility and better performance will
be obtained by using the feedback techniques described in

1.4.
1.6 INPUT IMPEDANCE
The input to each filter block is a switched-capacitor circuit
as shown in Figure 14. During the first half of a clock cycle,
the input capacitor charges to the input voltage Vin, and
during the second half-cycle, its charge is transferred to a
feedback capacitor. The input impedance approximates a
resistor of value

Output Steps
Another characteristic of sampled-data circuits is that the
output voltage changes only once every clock cycle, resulting in a discontinuous output signal (Figure 15). The "steps"
are smaller when the clock-to-center-frequency ratio is
100:1 than when the ratio is 50:1.

1
Rin"'---·
CinfCLK
Gin depends on the value of Q selected by the Q logic pins,
and varies from about 1 pF to about 5 pF. For a worst-case
calculation of Rin, assume Cin = 5 pF. Thus,

Clock Frequency Limitations
The performance characteristics of a switched-capacitor filter depend on the switching (clock) frequency. At very low
clock frequencies (below 10Hz), the internal capacitors begin to discharge slightly between clock cycles. This is due to
very small parasitic leakage currents. At very low clock frequencies, the time between clock cycles is relatively long,
allowing the capacitors to discharge enough to affect the
filters' output offset voltage and gain. This effect becomes
stronger at elevated operating temperatures.
At higher clock frequencies, performance deviations are primarily due to the reduced time available for the internal integrating op amps to settle. For this reason, the clock waveform's duty cycle should be as close as possible to 50%,
especially at higher frequencies. Filter Q shows more variation from the nominal values at higher frequencies, as indicated in the typical performance curves. This is the reason
for the different maximum limits on Q accuracy at fCLK =
250 kHz and fCLK = 100 kHz in the table of performance
specifications.

.
1
Rin(mln) '" 5 X 10-12fCLK

TLlH/B694-22

FIGURE 14_ Simplified MF8 Input Stage

At the maximum clock frequency of 1 MHz, this gives
Rln "" 200k. Note that Rln increases as fCLK decreases, so
the input impedance should never be less than this number.
Source impedance should be low enough that the gain isn't
Center Frequency Accuracy
significantly affected.
_ _ _ _ _ _ _---'I,.,d"'ea
__Ic:ly, the ratio fCI Klfo should be Rrecisel~rliO,_d~ -~-pending on the logic voltage on pin 10. However, as Table I
1.7-01lTPUiDRIVE
shows, this ratio will change slightly depending on the Q
The filter outputs can typically drive a 5 kO load resistor to
selected. As the table shows, the largest errors occur at the
over ±4V peak-to-peak. Load resistors smaller than 5 kO
lowest values of Q.
should not be used. The operational amplifier can drive the
minimum recommended load resistance of 5 kO to at least
±3.5V.
1.8 SAMPLED-DATA SYSTEM CONSIDERATIONS

100:1

Aliasing
The MFa is a sampled-data filter, and as such, differs in
many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect on signals at frequencies greater than one-half the
sampling frequency. (The MFa's sampling frequency is the
same as its clock frequency). If a signal with a frequency
greater than one-half the sampling frequency is applied to
the input of a sampled-data system, it will be "reflected" to
a frequency less than one-half the sampling frequency.
Thus, an input signal whose frequency is f8/2 + 10 Hz will
cause the system to respond as though the input frequency

50:1

TL/H/B694-23

FIGURE 15. Output Waveform of
MF8 Showing Sampling Steps

7-151

fII

2.0 Design Tables for Multiple Feedback Loop Bandpass Filters
BUTTERWORTH RIPPLE3dB
Order

Ko

K2

4
6
8
10
*12

2.0000
2.3704
2.9142
3.6340
4.5635

4.0000
2.6667
2.0000
1.6000
1.3333

Ks

K4

9.1429
5.8284
4.4112
3.5800

K5

14.3145
6.9094
4.3198

27.2014
11.5043

Ks

Kg

49.0673

1.4142
1.5000
1.5307
1.5451
1.5529

CHEBYSHEV RIPPLE 0.01 dB
Order

Ko

K2

4
6
8
*10

1.9041
1.8277
1.4856
1.0171

3.6339
1.8450
0.9919
0.5740

Ks

K4

6.6170
3.1209
1.7484

5.0414
1.2943

Ks

Ks

KQ
0.4489
0.9438
1.4257
1.8908

4.8814

CHEBYSHEV RIPPLE 0.02 dB
Order

Ko

K2

4
6
8
*10

1.8644
1.7024
1.2893
0.8163

3.4922
1.6787
0.8707
0.4934

~

Ks
6.0772
2.7661
1.5155

4.0779
0.9879

Ks

Ks

Kg
0.5393
1.0849
1.6106
2.1179

3.7119

CHEBYSHEV RIPPLE 0.03 dB
Order

Ko

K2

K3

4
6
8
*10

1.8341
1.6183
1.1688
0.7034

3.3871
1.5713
0.7977
0.4467

5.7231
2.5491
1.3786

K4

3.5270
0.8252

Ks

K6

KQ
0.6016
1.1808
1.7362
2.2724

3.0938

CHEBYSHEV RIPPLE 0.04 dB
Order

Ko

K2

4
6
8
*10

1.8085
1.5535
1.0814
0.6264

3.3009
1.4908
0.7454
0.4139

K3

K4

5.4548
2.3919
1.2818

3.1471
0.7181

Ks

Ks

KQ
0.6508
1.2560
1.8348
2.3940

2.6883

CHEBYSHEV RIPPLE 0.05 dB
Order

Ko

K2

4
6
8
*10

1.7860
1.5002
1.0129
0.5686

3.2268
1.4260
0.7046
0.3888

K3

K4

5.2373
2.2685
1.2072

2.8609
0.6402

K5

Ks

KQ
0.6923
1.3191
1.9175
2.4961

2.3938

CHEBYSHEV RIPPLE 0.06 dB
Order

Ko

K2

4
6
8
*10

1.7657
1.4548
0.9566
0.5230

3.1612
1.3717
0.6713
0.3685

~

K3
5.0536
2.1670
1.1467

2.6336
0.5800
7-152

K5

2.1666

Ks

KQ
0.7285
1.3741
1.9897
2.5852

3:

."
C»

2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued)
CHEBYSHEV RIPPLE .07 dB
Order

Ko

K2

4
6
8
·10

1.7471
1.4150
0.9089
0.4856

3.1020
1.3249
0.6431
0.3516

K3

K4

4.8943
2.0808
1.0959

2.4466
0.5316

Ks

Ks

KQ
0.7609
1.4232
2.0543
2.6649

1.9842

CHEBYSHEV RIPPLE .08 dB
Order

Ko

K2

4
6
8

1.7298
1.3795
0.8675

3.0478
1.2837
0.6187

K3

K4

4.7534
2.0060

Ks

Ks

KQ
0.7905
1.4679
2.1130

2.2887

CHEBYSHEV RIPPLE .09 dB
Order

Ko

K2

4
6
8

1.7136
1.3475
0.8311

2.9978
1.2469
0.5973

K3

K4

4.6271
1.9400

Ks

K6

KQ
0.8177
1.5090
2.1671

2.1529

CHEBYSHEV RIPPLE 0.1 dB
Order

Ko

K2

4
6
8

1.6983
1.3183
0.7986

2.9512
1.2137
0.5782

K3

K4

4.5125
1.8809

Ks

K6

KQ
0.8430
1.5473
2.2176

2.0343

CHEBYSHEV RIPPLE 0.2 dB
Order

Ko

K2

K3

K4

Ks

K6

4--'------ ~5751----- ~5998

6
8

1.1128
0.5891

0.9894
0.4551

3.7271
1.4954

KQ
1.0378
1.8413
2.6057

1.3309

CHEBYSHEV RIPPLE 0.3 dB
Order

Ko

K2

4
6
·8

1.4833
0.9835
0.4732

2.3575
0.8560
0.3861

K3

K4

·3.2501
1.2760

Ks

K6

KQ
1.1804
2.0568
2.8914

0.9885

CHEBYSHEV RIPPLE 0.4 dB
Order

Ko

K2

K3

K4

4
6
·8

1.4067
0.8888
0.3956

2.1698
0.7618
0.3391

2.9088
1.1250

. Ks

K6

KQ
1.2988
2.2363
3.1299

0.7792

CHEBYSHEV RIPPLE 0.5 dB
Order

Ko

K2

4
6
·8

1.3405
0.8143
0.3389

2.0161
0.6897
0.3040

K3

K4

2.6447
1.0114
7·153

0.6365

Ks

K6

KQ
1.4029
2.3944
3.3406

•

2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued)

,

CHEBYSHEV RIPPLE 0.6 dB
Order

Ko

K2

4
6
°8

1.2816
0.7530
0.2952

1.8857
0.6316
0.2762

Order

Ko

K2

4
6
°8

1.2283
0.7012
0.2601

1.7727
0.5834
0.2535

K3

K4

2.4305
0.9212

Ks

ICe·

Kg
1.4975
2.5385
3.5329

0.5326

CHEBYSHEV RIPPLE 0.7 dB

K3

K4

2.2515
0.8471

Ks

K6

KQ
1.5852
2.6724
3.7119

0.4535

CHEBYSHEV RIPPLE 0.8 dB
Order

Ko

K2

4
6
°8

1.1797
0.6564
0.2314

1.6731
0.5424
0.2344

K4

K3
2.0983
0.7846

Ks

K6

KQ
1.6678
2.7989
3.8811

0.3913

CHEBYSHEV RIPPLE 0.9 dB
Order

Ko

K2

4
6
°8

1.1347
0.6171
0.2073

1.5841
0.5068
0.2181

K3

K4

1.9650
0.7309

Ks

K6

KQ
1.7464
2.9194
4.0426

0.3413

CHEBYSHEV RIPPLE 1.0 dB
Order

Ko

K2

4
6
°8

1.0930
0.5822
0.1869

1.5039
0.4756
0.2038

K3

K4

1.8475
0.6840

Ks

ICe

KQ
1.8219
3.0354
4.1981

0.3002

CHEBYSHEV RIPPLE 1.1 dB
Order

Ko

K2

4
6
°8

1.0539
0.5509
0.1693

1.4310
0.4479
0.1913

K3

K4

Order

Ko

K2

K3

4
6
°8

1.0173
0.5226
0.1540

1.3643
0.4231
0.1801

1.6487
0.6056

1.7428
0.6426

Ks

K6

KQ
1.8949
3.1476
4.3487

0.2660

CHEBYSHEV RIPPLE 1.2 dB

K4

Ks

K6

Kg
1.9657
3.2567
4.4952

0.2372

CHEBYSHEV RIPPLE 1.3 dB
Order

Ko

K2

4
6
°8

0.9828
0.4969
0.1406

1.3029
0.4006
0.1701

K3

K4

1.5634
0.5724

7-154

0.2125

Ks

ICe

Kg
2.0348
3.3633
4.6385

3:
-n

2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued)
CHEBYSHEV
Order

Ko

K2

4
6

0.9501
0.4733

1.2461
0.3803

RIPPLE 1.4 dB

K3

Ko

K2

4
6

0.9192
0.4515

1.1934
0.3616

Ko

K2

4
6

0.8897
0.4315

1.1443
0.3445

Ko

K2

4

0.8617
0.4128

1.0983
0.3287

6

K6

K4

Ks

K6

RIPPLE 1.6 dB

K4

Ks

K6

RIPPLE 1.7 dB

K4

K3

Ks

K6

Ko

K2

0.8350
0.3955

1.0553
0.3141

Order

Ko

K2

4
6

0.8095
0.3793

1.0148
0.3005

Order

Ko

K2

K3

4
6

0.7850
0.3641

0.9767
0.2878

1.1308

RIPPLE 1.8 dB

K3

K4

Ks

K6

KQ
2.3624
3.8706

1.2321
CHEBYSHEV

KQ
2.2986
3.7717

1.2883

4
6

KQ
2.2341
3.6717

1.3490

Order

KQ
2.1688
3.5705

K3

CHEBYSHEV

KQ

RIPPLE 1.5 dB

1.4145

CHEBYSHEV
Order

Ks

2.1024
3.4678

K3

CHEBYSHEV
Order

K4

1.4857
CHEBYSHEV

Order

CD

RIPPLE 1.9 dB

K3

K4

Ks

K6

KQ
2.4255
3.9687

1.1797
CHEBYSHEV RIPPLE 2.0 dB

CHEBYSHEV
Order

Ko

K2

K3

4
6

0.7616
0.3498

0.9407
0.2759

1.0850
CHEBYSHEV

Order

Ko

K2

4
6

0.7391
0.3364

0.9067
0.2648

K4

Ks

K6

KQ
2.4881
4.0660

RIPPLE 2.1 dB

K4

Ks

K6

KQ
2.5503
4.1628

RIPPLE 2.2 dB

K3
1.0420

7-155

K4

Ks

K6

KQ
2.6122
4.2591

II

200

Design Tables for Multiple Feedback Loop Bandpass Filters (Continued)
CHEBYSHEV RIPPLE 2.3 dB

Order

Ko

Kz

4
6

0.7176
0.3237

0.8744
0.2544

Ks

K4

K5

Ks

KQ
2.6737
4.3550

1.0016
CHEBYSHEV RIPPLE 2.4 dB

Order

Ko

K2

4
6

0.6968
0.3118

0.8438
0.2446

Ks

K4

K5

.K6

KQ
2.7350
4.4507

0.9635

CHEBYSHEV RIPPLE 2;5 dB
Order

Ko

Kz

4
6

0.6769
0.3005

0.8148
0.2353

Ks

K4

K5

Ks

KQ
2.7962
4.5462

0.9275

CHEBYSHEV RIPPLE 2.6 dB
Order

Ko

K2

4
6

0.6577
0.2897

0.7871
0.2265

Ks

K4

K5

Ks

KQ
2.8573
4.6415

0.8935

CHEBYSHEV RIPPLE 2.7 dB
Order

Ko

Kz

4
6

0.6392
0.2796

0.7607
0.2182

Ks

K4

K5

K6

KQ
2.9183
4.7368

0.8612

CHEBYSHEV RIPPLE 2.8 dB
Order

Ko

Kz

4
6

0.6213
0.2699

0.7356
0.2104

Ks

~

K5

K6

KQ
2.9792
4.8322

0.8306

CHEBYSHEV RIPPLE 2.9 dB
Order

Ko

Kz

4
6

0.6041
0.2607

0.7116
0.2029

Ks

K4

K5

Ka

KQ
3.0402
4.9276

0.8016

CHEBYSHEV RIPPLE 3.0 dB
Order

Ko

Kz

4
6

0.5875
0.2519

0.6886
0.1959

Ks
0.7739

K4

K5

K6

Ko
3.1013
5.0231

Note: Multiple feedback loop filters of higher order than those specified In Ihe tables will oscillate due 10 phase shill althe outpul of Ihe summing amplifier. This
phase shift Is nollhe faull of the MFa; ills inherent in Ihis type of mulliple feedback loop lopology. In addilion, all fillers marked wilh an aslerisk (0) will be unstable
fer Q s; 1, due 10 phase shifts caused by the MFa's switched·capacitor deSign approach.

7·156

"T1
==
.....
Q

f)1National Semiconductor

MF10
UniVerS8~ Ml!J)nlO~DtlliM~ !Dt!la~

Switched!

CalPaci~o>D" fn~~eli"

General Description
The MF10 consists of 2 independent and extremely easy to
use, general purpose CMOS active filter building blocks.
Each block, together with an external clock and 3 to 4 resistors, can produce various 2nd order functions. Each building
block has 3 output pins. One of the outputs can be configured to perform either an allpass, highpass or a notch function; the remaining 2 output pins perform lowpass and bandpass functions. The center frequency of the lowpass and
bandpass 2nd order functions can be either directly dependent on the clock frequency, or they can depend on both
clock frequency and external resistor ratios. The center frequency of the notch and allpass functions is directly dependent on the clock frequency, while the highpass center frequency depends on both resistor ratio and clock. Up to 4th
order functions can be performed by cascading the two 2nd
order building blocks of the MF10; higher than 4th order
functions can be obtained by cascading MF10 packages.

Any of the classical filter configurations (such as Butterworth, Bessel, Cauer and Chebyshev) can be formed.
For pin-compatible device with improved performance refer
to LMF100 datasheet.

featllJi"IaS
o Easy to use

o Clock to center frequency ratio accuracy ± 0.6%

o
o

o
o
o

o

o

System

Bloc~(

Filter cutoff frequency stability directly dependent on
external clock quality
Low sensitivity to external component variation
Separate highpass (or notch or allpass), bandpass, lowpass outputs
foX Q range up to 200 kHz
Operation up to 30 kHz
20-pin 0;3" wide Dual-In-Line package
20-pin Surface Mount (SO) wide-body package

Conl1'Dlac~ion

Diagram

Diagram

Surface Mount and Dual-In-Line
Pacl(age

LPA

20

~--I----~----4-~-----i-------------B~A~Z-------~ !t

INV.

lP B
--B B

N/ AP/HPA

3

18

N/ AP/HP B

INVA

4

17

INVB

SI A 5

16

SIB

6
7

15

AGND

14

VA-

AGHO

SA/B
VA+
Vo+

8

13

Vo-

CLiI.

lSh

9

12

50/100/Cl

CU V+) the absolute value of current at that pin should be limited
to 5 rnA or less. The 20 rnA package input current limits the number of pins that can exceed the power supply boundaries with a 5 rnA current limit to four.

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 8JA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJMAX - TIJI8JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX = 125'C, and the typical junction·to·ambient thermal resistance of the MF10ACN/CCN when board mounted is 55'C/W. For the MF10AJ/CCJ, this
number increases to 95'C/W and for the MF10ACWM/CCWM this number Is SS'C/W.
Note 4: The accuracy of the Q value is a function of the center frequency (fa). This is illustrated in the curves under the heading "Typical Performance
Characteristics".
Note 5: VOS1o Vos 2• and Vosa refer to the intemal offsets as discussed in the Applications Information Section 3.4.

Note 6: For ±5V supplies the dynamic range is referenced to 2.B2V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 p.V rms for
the MF10 with a 50:1 CLK ratio and 2BO p.V rms for the MF10 with a 100:1 CLK ratio.
Note 7: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to
the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting
that output to the positive supply. These are the worst case conditions.
Note 8: Typicals are at 25'C and represent most likely parametric norm.
Note 9: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 10: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Nota 11: Human body model, 100 pF discharged through a 1.5 kn resistor.

7·159

•

C)
..-

U.

:iii

r-----------------------------------------------------------------------------~--,

Typical Performance Characteristics

14D

1
u
~

11.0

~

I

jA=25.lc

13D -MODE 1

I

'I

12.0 _'o=5kHz

10.0

I

9.0

I

Positive Output Voltage Swing
vs Load Resistance
(N/ AP/HP Output)

Power Supply Current
vs Power Supply Voltage

L

8.0

ill

-3D

!:i

-3.5

5.2
5.0

50'"

4.8 1-::I..loI#II!f-!-I+i't!m~-+t1flltl1

~

4.6

~..o :~t;~~~~~~n~
~EiB4ff·5mV~0=LTtSfUPffP~UES~tt~

4.0
3.8 I!!
3.6,k

10k

Negative Output
Swing vs Temperature
-3.7

..
z

ill

!:i

-3.8

1

-3.9
-4.D
-41

1

5

...u

~

-.u

0

z

-4.6
--1.7

#

(RL=3.5k

1

i~V
~'

-NObtf)

-.\.3
-4.5

vsb

450

I-

#

(RL=5.0kJl)

#~
~

25

85

-55

125

1.0
0.5

VS=i5Vl-)..
NOMINA~
WODE 1
fCLK=±Z
f
-

0.0

~=100:1

\

-os

0.20

1
..

I.....

~
i5

..

-V~~5V

I'

85

25

I'~

-0.10
-0.15

85

-55

125

2S

-15

125

100

6.0
5.5

1

f-

-85

1
..

V

25

V~=tI5V
TA=25"C

9

:~~~L = 10.0
I

1 ,I.
~=100:1

2.0
105
1.0
0.5
0.0

-1.0

100 20D 30D 40D SOD BOD 70D BOD 90D IODD
CLOCK FREQUENCY (kHz)

fCLK/fO Deviation
vs Temperature
0.D6

0.D5

"

100 20D 30D 40D SOD BOD 70D BOD 90D IODD

CLOCK FREQUENCY (kHz)

0.D5 YS=i5V 1

VS=t5v'.±

0.D4
0.D3
0.D2

NOMINf~
UODE 1

:.....

fCLK,~~~

I"

0.01

1:5
IL

,.

.......

-os
125

fcue
lI =100:1 fa .-f-I-

.. -O.D3

1'00

5.0
4.5
4D
3.5
3D

fCLK/fo Deviation
vs Temperature

I

1000

SOD
CLOCK FREQUENCY(kHz)

0.D6

.J.

100:1

~

TEMPERATURE("C)

I.
-TA=25"C
,I
-NOMINA.. Q= 10.0
-MODE I
-ICLK
-To=50:1

./

Q Deviation vs
Clock Frequency

'

"

J;l-

#

fCLK=50"
lO
•

-O.OS

/

1M

.1

i~=25DkH~_

\

0.10

Clock Frequency
18.0
16.0
14.D
12.0
10.0
8.0
6.0
4D
2.0
0.0
-2.0

lOOk

Vs=t5V
TA =25"C
MODE 1
NOMINAL C= 10.0

NOUINA~~tr
JaDE 1

1\

0.15

Q Deviation vs
20.0

10k

Crosstalk vs Clock
Frequency

~S=~5.Jft±

0.25

TEMPERATURE ("C)

22.D

lk

LOAD RESlSTANCE(Jl)

O.OS

l"- i'"
-15

1M

#~

25

-15

0.00

-1.0
"'55

• -6.5 VOLT SUPPUES

-6.D

(~=3.6kJl)'-

0.30

. -..... i'.

+ -6.0 VOLT SUPPUES

-5.5

Q Deviation vs
Temperature

3D

1
.

+ -5.5 VOLT SUPPUES

-5.0

TElJPERATURE ("C)

Q Deviation vs
Temperature

105

-4.5

~NDTCH-:-<

~

TEMPERATURE ("C)

2.0

• -5.0 VOLT SUPPUES

.:;r

#

-l10

2.5

z

1111

+-4.5 VOLT SUPPLIES

-4.D

.

AND L r +
7. ~ ~+NDPAS~
(\5.~kJll

-15

~

IIII

Vs~iJV- 9AlDpks lND ILO~~::;; ---;
~

~

#
#

~

TAN*

-2.5

Positive Output Swing
vs Temperature

,h#

-55

lOOk

z

LOAD RESISTANCE(Jl)

POWER SUPPLY VOLTAGE (V)

E

-2.0

...

10.0 11.0 12.0 13D 14.D

9.D

..

E

/

7.0

-1.5

E ~~~~~~~Hffi~~~m

I ~:: F-;~jjjjj§~mt:nmm
b

V

8.0

6Ar-rnmnr-rrnmrr-TTTInm
6.2 1-t-+l'tIItIt-H-HttIIft-'

Negative Output Voltage
Swing vs Load
Resistance (N/AP/HP Output)

NOMINAL Q= 10.0
0.D4
MODE 1 1
0.D3 1CUC=2?D kHz

I:
..

-oJM

0.00

-O.D5

-0.01

-om

-o.D6

-O.D2

-o.oa

-O.D3

-o.D9

-oJM

-55

-15

25

TEMPERATURE("C)

85

125

f~~=50:1

, 1/

I

I

"

I

I
-55

-15

25

85

125

TEMPERATURE ("C)
TL/HI1 0399-2

7-160

s::

Typical Performance Characteristics
fCLK/fO Deviation
vs Clock Frequency

."

.....

(Continued)

CI

Deviation of fCLK
vs Nominal Q fo

fCLKlfO Deviation
vs Clock Frequency
I~~~~-.~-r-r~~

U 1.2 _

1.0 -

..

~

-

M -

0.4

vs~uv_HII--t-+-I--II

TA=-.!:25=:-,"C,,-:-!I--+-+-l--I-fl

~~~~1f_Q-'-=r'-cD·rD-t--t--I-f-t
I

IClK=~D:lf-f-f-f---JJ-/-I
10

+++++-1--1

H-+-+-H-+--1I1
-1t-l

0.2

HH-t-+-+-t---tl-+--I

-0.2

L.......1--l.......J.......L...
......
.J..-.....J.......L....J.......I

100 200 300 0400 500 600 700 800 900 1000
CLOCK FREQUENCY (kHz)

CLOCK FREQUENCY (kHz)

-3.0

0.1

1.0

10

100

NOMINAL Q

Deviation of fCLK
vs Nominal Q fo

NOYINAL Q
TLlH/l0399-3

Pin Descriptions
LP(1,20), BP(2, 19), The second order lowpass, bandpass
SAls(6)
This pin activates a switch that connects
NIAP/HP(3, 18)
and notch/all,..,pa,.,s....s"'/h...i9...h,..p....a....,ss"-c-"'o...
utt'"Pu...t""s."---_ _ _ _ _ _ _---'o"'n-"e'--'o""-f-"th"'e<-'i"-'n...
pu~t.~s~oLeachJilter's.JIilc~t----These outputs can typically sink 1.5 mA
summer to either AGND (SAIS tied to
and source 3 mAo Each output typically
V-) or to the lowpass (LP) output (SAIS
swings to within tV of each supply.
tied to V+). This offers the flexibility
needed for configuring the filter in its
The inverting input of the summing opINV(4,17)
amp of each filter. These are high imvarious modes of operation.
VA + (7),Vo + (8)
Analog positive supply and digital posipedance inputs, but the non-inverting intive supply. These pins are Internally
put is internally tied to AGND, making
INVA and INVs behave like summing
connected through the IC substrate and
junctions (low impedance, current intherefore VA+ and Vo+ should be deputs).
rived from the same power supply
Sl is a signal input pin used in the allsource. They have been brought out
Sl(5,16)
pass filter configurations (see modes 4
separately so they can be bypassed by
and 5). The pin should be driven with a
separate capacitors, if desired. They
can be externally tied together and bysource impedance of less than 1 kG. If
Sl is not driven with a signal it should be
passed by a single capacitor.
VA-(14),Vo-(13) Analog and digital negative supplies.
tied to AGND (mid-supply).
The same comments as for VA + and
Vo + apply here.

II

7-161

C)

--

u.

::&

.---------------------------------------------------------------------------------~

Pin Descriptions (Continued)

1.0 Definition of Terms·

LSh(9)

fCLK: the frequency of the external clock Signal applied to
pin 10 or 11.

CLKA(10),
CLKB(11)

50/100/CL(12)

AGND(15)

Level shift pin; it accommodates various
clock levels with dual or single supply
operation. With dual ± 5V supplies, the
MF10 can be driven with CMOS clock
levels (±5V) and the LSh pin should be
tied to the system ground. If the same
.supplies as above are used but only TIL
clock levels, derived from OV to + 5V
supply, are available, the LSh pin should
be tied to the system ground. For single
supply operation (OV and + 10V) the
VA -, Vo - pins should be connected to
the system ground, the AGND pin
should be biased at + 5V and the LSh
pin should also be tied to the system
ground for TIL clock levels. LSh should
be biased at + 5V for CMOS clock levels in 10V single-supply applications.

fo: center frequency of the second order function complex
pole pair. fo is measured at the .bandpass outputs of the
MF10, and is the frequency of maximum bandpass gain.
(Figure 1)

fn~tch: the frequency of minimum (ideally zero) gain at the
notch outputs.
fz: the center frequency 01 the second order complex zero
pair, if any. If fz is different from fo and if Qz is high, it can be
observed as the frequency of a notch at the allpass output.
(Figure 10)

Q: "quality factor" of the 2nd order filter. Q is measured at
the bandpass outputs of the MF10 and is equal to fo divided
by the - 3 dB bandwidth of the 2nd order bandpass filter
(Figure 1). The value of Q determines the shape of the 2nd
order filter responses as shown in Figure 6.
Qz: the quality factor of the second order complex zero pair,
if any. Qz is related to the allpass characteristic, which is
written:

Clock inputs for each switched capacitor filter building block. They should both
be of the same level (TIL or CMOS).
The level shift (LSh) pin description discusses how to accommodate their levels. The duty cycle of the clock should
be close to 50% especially when clock
frequencies above 200 kHz are used.
This allows the maximum time for the
internal op-amps to settle, which yields
optimum filter operation.

where Qz = Q for an all-pass response.

HOBP: the gain (in VIV) of the bandpass output at 1 = fo.

By tying this pin high a 50:1 clock-to-filter-center-frequency ratio is obtained.
Tying this pin at mid-supplies (i.e, analog
ground with dual supplies) allows the filter to operate at a 100:1 clock-to-center-frequency ratio. When the pin is tied
low (i.e., negative supply with dual supplies), a simple current limiting circuit is
triggered to limit the overall supply current down to about 2.5 mA. The filtering
action is then aborted.

HOLP: the gain (in V IV) of the lowpass output as f (Figure 2).

0 Hz

HOHP: the gain (in VIV) of the highpass output as f fCLK/2 (Figure 3).
HON: the gain (in V IV) of the notch output as f 0 Hz
fCLK/2, when the notch filter has equal gain
and as f above and below the center frequency (Figure 4). When the
low-frequency gain differs from the high-frequency gain, as
in modes 2 and 3a (Figures 11 and 8), the two quantities
below are used in place of HON.
HON1: the gain (in V IV) of the notch output as f 0 Hz.
HON2: the gain (in V IV) of the notch output as f fCLK/2.

This is the analog ground pin. This pin
should be connected to the system
ground for dual supply operation or biased to mid-supply for single supply operation. For a further discussion of midsupply biasing techniques see the Applications Information (Section 3.2). For
optimum filter performance a "clean"
ground must be provided.

7-162

"T1
==
.....
Q

1.0 Definition of Terms (Continued)
>"

-

90
451-----"'11.
~ 01----1-"1"..
if -45 l - - - - I - P.......

~

HOBP ~---_

~ 0.707 HUp I---~'+""'"

~

-00

Q=~lo=AA
IH - IL

~--~-+~~~

IL=Io(;~+~(fcJr +1)

IL 10 IH

,.. I, IH
1(LOG SCALE)

1(LOG SCALE)
TL/H110399-6

TLlH/l0399-5

IH = 10 (fcJ +

(b)

(a)

~(fcJr + 1 )

"'0 = 2".10

FIGURE 1. 2nd-Order Bandpass Response

::

H~~ I;;;;;;;;;;;;;;;;;~

~

;-o.7D7HOLP ~---+-~
Ip

IC=IOX~(I- 2~2) +~(1- 2~2r +1

:Jj-9o ~---"""""

~

~

-180 l----+-~"..-

I,

Ip=IO~I- 2~

10

1(LOG SCALE)

1 (LoGSCALE)

TLlH/l0399-7

TLlHI1 0399-8

(a)

(b)

FIGURE 2. 2nd-Order Low-Pass Response

'-===7J!.~---

~

Hop tHOHP
z 0.7D7 HOHP

;:

1-

~

90

-180

I,

10

Ip

I (LOG SCALE)

1(LOU-SCALE)

TL/HI10399-10

TL/H110399-9

(b)

(a)

Ip= 10 x

[~1 - 2~r

HOp = HOHpX :"~1- 1
Q
402
FIGURE 3. 2nd-Order High-Pass Response

7-163

C)
.....

U.

::::&

r-------------------------------------------------------------------------------------~

1.0 Definitions of Terms (Continued)
90

>'
;;;

~ 45

HON

;z- 0.707 HON
iii

1-----4E-~---

~

0

iE -45 I---~
-90 L...-____J....:...J...._ _....

It. fo IH

It. fo IH

1(LOG SCALE)

1(LOG SCALE)

TLlH/l0399-1 )

TL/H/l0399-12

(a)

(b)
FIGURE 4. 2nd-Order Notch Response

~

t--------''''

!ii-180

IE

t:::==±:=~:

-360

10

10

1(LOG SCALE)

1(LOG SCALE)
TLlH/l0399-14

TL/HI10399-13

(b)

(a)

FIGURE 5. 2nd-Order All-Pass Response

(a) Bandpass

(b) Low Pass

201=+=+=+=+=+=1

10

20

~+-~--+-~--~4

10

t--

L~b

Q=1

!z

!z: -10 1--hf!C-H

iii

iii

-10

-20

o

......
0.5

~
~

.......

1- 0 10.2

!i=

'",

....

10

0.1

0.2

0.5 1.0 2.0

-60

if -120

:iI

-20

i

1--+--+"""
I--+--+-"'---"l'<

-3DO

-360

5

0,5 1.0

2

5

10

FREDUENCY (Hz)

0=5

.....

-180

1-+-+-+---1--+-1
0.1 0.2 0.5
1.0 2
FREOUENCY (Hz)

"

0.1 0.2

i""oo. 0=0.2

.......

... -240

-40 '---'---'---'---'-........--1

-3~

10

~

V

(e) All-Pass

1-+-+--+-+--+---1

...
;- -10

-3~

-40

FREOUENCY (Hz)

(d) Notch
2O;....;..T"""'"T""-r--r----,---.
10

,.2_

,

5.0

ITr~"""~

,
II< ..... 0=~.5_
o
1/

~

FREOUENCY (Hz)

.Q-l0:- I--

r:-0=0~7~ ,

.

-40
1

10

0.707-

~

-3~

0.5

High-Pass
20(c)I-+Q=~-

J p~=5+-

c--Q= IO

10

~=1

0.1

0.2

0.5

I'\.

1"""-

1

2

5

10

FREOUENCY (Hz)
TL/H110399-15

FIGURE 6. Response of various 2nd-order filters as a function of Q.
Gains and center frequencies are normalized to unity.

7-164

3:

."

.....

2.0 Modes of Operation
The MF10 is a switched capacitor (sampled data) filter. To
fully describe its transfer functions, a time domain approach
is appropriate. Since this is cumbersome, and since the
MF10 closely approximates continuous filters, the following
discussion is based on the well know frequency domain.
Each MF10 can produce a full 2nd order function. See Table I for a summary of the characteristics of the various
modes.
MODE 1: Notch 1, Bandpass, Lowpass Outputs:
fnotch = fo (See Figure 7)
fo
= center frequency of the complex pole pair
fCLK

=

a
BW

=

..!Q. =

o

R3
R2

BW
= quality factor of the complex pole pair
= the -3 dB bandwidth of the bandpass output.

Circuit dynamics:
HOLP =

Hosp

Q

or Hosp = HOLP X a

= HON X O.
HOLP(peak) "" a x HOLP (for high a's)
MODE 1a: Non-Inverting BP, LP (See Figure 8)

fCLK

ffio°r 50

fO

fnotch = center frequency of the imaginary zero pair = fo.

= fCLK or fCLK
100
50
R3
R2

0) = -

:~

a

Hosp = Bandpass gain (at f = fo) = -

:~

HOLP = -1; HOLP(peak) "" a
R3
HOSP1= -R2

HOLP = Lowpass gain (as f -

HON = Notch output gain as

~ ::::: ?CLK/2} = -R~2

x HOLP (for high a's)

HOSP2= 1 (Non-Inverting)
Circuit Dynamics: HOSPl = a
Note: VIN should be driven from a low impedance

« 1 kO) source.

TUH/10399-16

FIGURE 7. MODE 1

TLlH/10399-17

FIGURE 8. MODE 1a

7-165

fI

....

o

II-

::!

2.0 Modes of Operation (Continued)
MODE 2: Notch 2, Bandpass, Lowpass: fnotch < fo
(See Figure 9)
fo
= center frequency
= fClK ~R2
100 R4
fnotch =

Q

fClK

+ 1 or

fClK
50

MODE ;i: Highpass, Bandpass, Lowpass Outputs
(See FIgure 10)

~R2 + 1
R4

Q

= quality factor of the complex pole pair

roo or 50

=

~)

Filter dynamics: HOBP = Q ~HOlP HON2 =

{R2 x

V'R4

VFi4

R3
R2

HOHP= H'Ighpass G'
aln ( as f

fClK)
-2

,R2
= -R1

' R3
HOBP = Lowpass Gain ( atf = fo ) = - R1

HOlP = Lowpass output gain (as f 0)
R2/R1
R2/R4 + 1
HOBP = Bandpass output gain (at f = fo) = -R3/R1
HON1 = Notch output gain (as f 0)
R2/R1
R2/R4 + 1
HON2 = Notch output gain (asf -

YR4

or fClK X
50

{R2

= fClK X '
100

fClK

= quality factor of the complex pole pair
~R2/R4 + 1
'
R2/R3

{R2

fo

HOlP = LowpassGain ( as f -

0) = -

:~

Circuit dynamics: R2 = HOHP;
R4
HOlP
HOBP = .;/i';H'O-H-P""X"'H-O-lP- x Q
HOlP(peak) "" Q X HOlP (for high Q's)
HOHP(peak) "" Q X HOHP (for high Q's)

= -R2/R1

~H~N1, HON2
R4

TLIHll0399-18

FIGURE 9. MODE 2

,r

Ce•

-I~ I
R4

TLIH110399-19
·In Mode 3, the feedback loop is closed around the input summing amplifier; the finite GBW product of this op amp causes a slight Q enhancement. If this is a
problem, connect a small capacHor (10 pF - 100 pF) across R4 to provide some phase lead.

FIGURE 10. MODE 3

7-166

2.0 Modes of Operation

(Continued)
MODE 3a: HP, BP, LP and Notch with External Op Amp
(See Figure 11)
fClK
fo

= 100

o

=

fR2

x VFi4

fR2

fClK

or

MODE 4: Allpass, Bandpass, Lowpass Outputs
(See Figure 12)
= center frequency
fO

50 x VFi4

fClK

= 100 or

fR2 x R3
VFi4 R2

fCLK

50;

fz· = center frequency of, the complex zero ::::: fo

R2
HOHP = -R1

o

fo
R3
= BW = R2;

R3

HOBP = -R1

Oz = quality factor of complex zero pair =

R4
HOlP = -R1

For AP output make R1 = R2

= notch frequency = fClK fRh
100 vA;

or fClK

,50

HOAp. = Allpass gain (at 0

fRh

vA;

Hn1
Hn2

=

-+ 0) =

gain of notch ( as f -+

2

R1

R2 ' )
= - ( R1 + 1 =-2

110 (~HOlP - ~HOHP )11

= gain of notch (as f

< f < fClK) = - R2 = -1

HOlP = Lowpass gain (as f -+ 0)

= gain of notch at
f = fo =

:~

HOBP = Bandpass gain (at f = fo)

~ X HOlP

= _ R3 (1

R2

f~lK)

+ R2)
R1

= _ 2 (R3)

R2

+

x 0

= (HOAP
1)0
'Due to the sampled data nature 01 the filter, a slighl mismatch ollz and 10
occurs causing a 0.4 dB peaking around 10 01 the allpass filter amplitude
response (which theoretically should be a straight line). II this Is unacceptable, Mode 5 Is recommended.

Circuit Dynamics: HOBP = (HOlP)

R

= -!..!!I X HOHP

Rh

R4

R1
_ _ _ _ _V_'N ___ _

vNOTCH

OUT
TL/H/l0399-20

FIGURE 11. MODE 3a

fI

Rl

~6
v,

TL/H/l0399-21

FIGURE 12. MODE 4

7-167

....
C)

LL

::i!!

r---------------------------------------------------------~----------------------,

2.0 Modes of Operation (Continued)
MODE 5: Numerator Complex zeros, BP, LP
(SeeF/gure 13)
fo

=

~1 + R2 X fClK

n

R4

or

lee

~1 + R2

~ f~~ or ~1 -

=

Q

=

41 + R2/R4 X :~

Qz

=

41 -

= cutoff frequency of lP or HP output
=

X fClK

'R4

fz

MODE 6a: Single Pole, HP, LP Filter (See Figure 14)

:: X

50

f~~K

HOlP

Rl/R4 X R3
Rl

-R2(R4 - Rl)

+ R4)

(

= gain at C.Z. output

HOBP = _

(R2
Rl

HOlP = _(R2

R2

+

as f -

fe

f)'
Ct

=

= cutoff frequency of lP outputs

R2 fClK
R2 fClK
'" R3 lee or R3 50

-R2

R1

HOlP1 = 1 (non-inverting)

1) XR3
R2

+ Rl) ~
+ R4

'

R3
Rl

MODE 6b: Single Pole LP Filter (Inverting and Non-Inverting) (See Figure 15)

= gain at C.Z. output (as f - , 0. Hz)

Rl(R2

R2 fClK
R2 fClK
R3 lee or R3 50'"

R3

HOlP2 = -R2

R4
Rl

TUH/l0399-22

FIGURE 13. MODE 5

~6
y-

TUH/l0399-23

FIGURE 14. MODE 6a

TLIHll0399-24

FIGURE 15. MODE 6b

7-168

:s::
'T1

2.0 Modes of Operation (Continued)
TABLE I. Summary of Modes. Realizable filter types (e.g. low-pass) denoted by asterisks.
Unless otherwise noted, gains of various filter outputs are Inverting and adjustable by resistor ratios.
Mode

BP

LP

1

•

•

1a

(2)
HOBPt = -0
HOBP2 = +1

HOLP + 1

2
3
3a

4
5
6a

·
·
·
·
·

6b

·
•
·
·
·•
(2)
HOLPt = +1
-R3
HOLP2 = R2

HP

N

AP

3

Adjustable
fCLKlfO
No

2

No

3

Yes (abovefCLK/50
or fCLK/1 00)

4

Yes

Universal State-Variable
Filter. Best general-purpose mode.

7

Yes

As above, but also includes
resistor-tuneable notch.

3

No

Number of
Resistors

•

·
•
··.
.
·

4

.....
o

Notes

May need input buffer.
Poor dynamics for
highO.

Gives Allpass response with
HOAP = -1 and HOLP = -2.
Gives flatter all pass response
than above if Rt = R2 = 0.02R4.

3

Single pole.

2

Single Pole.

3.0 Applications Information
The MF10 is a general-purpose dual second-order state
variable filter whose center frequency is proportional to the
frequency of the square wave applied to the clock input
(fcud. By connecting pin 12 to the appropriate DC voltage,
the filter center frequency fo can be made equal to either
fCLK/100 or fCLK/50. fo can be very accurately set (within
±60/0) by using a crystal clock oscillator, or can be easily
varied over a wide frequency range by adjusting the. clock
frequency. If desired, the fCLKIfO ratio can be altered by
external.resistors.asinFigures 9~1'd,-1-1~13~14-and-1.5~The-filter 0 and gain are determined by external resistors.
All of the five second-order filter types can be built using
either section of the MF10. These are illustrated in Rgures 1
through 5 along with their transfer functions and .some related equations. Figure 6 shows the effect of 0 on the shapes
of these curves. When filter orders greater than two are
desired, two or more MF10 sections can be cascaded.

filter. For the Chebyshev filter defined above, such a table
yields the following characteristics:
faA = 529 Hz
OA = 0.785
fOB = 993 Hz
OB = 3.559
For unity gain at DC, we also specify:
HOA

=

1

HOB = 1
The desired clock-to-cutoff-frequency ratio for the overall
-filtarof this-ejxam-plei:n 00-anda100-kFrzClocKsignaris-available. Note that the required center frequencies for the
two second-order sections will not be obtainable with clockto-center-frequency ratios of 50 or 100. It will be necessary

3.1 DESIGN EXAMPLE

to adjust fCLK externally. From Table I, we see that Mode 3
fa
can be used to produce a low-pass filter with resistor-adjustable center frequency.
In most filter designs involving multiple second-order
stages, it is best to place the stages with lower 0 values
ahead of stages with higher 0, especially when the higher 0
is greater than 0.707. This is due to the higher relative gain
at the center frequency of a higher-O stage. Placing a stage
with lower 0 ahead of a higher-O stage will provide some
attenuation at the center frequency and thus help avoid clipping of signals near this frequency. For this example, stage
A has the lower 0 (0.785) so it will be placed ahead of the
other stage.
For the first section, we begin the design by choosing a
convenient value for the input resistance: R1A = 20k. The
absolute value of the passband gain HOLPA is made equal

In order to design a second-order filter section using the
MF10, we must define the necessary values of three parameters: fa, the filter section's center frequency; Ho, the passband gain; and the filter's O. These are determined by the
characteristics required of the filter being deSigned.
As an example, let's assume that a system requires a
fourth-order Chebyshev low-pass filter with 1 dB ripple, unity
gain at DC, and 1000 Hz cutoff frequency. As the system
order is four, it is realizable using both second-order sections of an MF10. Many filter design texts include tables that
list the characteristics (fo and 0) of each of the second-order filter sections needed to synthesize a given higher-order

7-169

PI

.... r-----------------------------------------------------------------------------,

o
u..

:::E

3.0 Applications Information (Continued)

The resistors for the second ·section are found in a similar
fashion:

to 1 by choosing R4A such that: R4A = -HOLPA R1A =
R1A = 20k. If the 50/100/CL pin is connected to mid-supply for nominal 100:1 clock-to-center-frequency ratio. we
find R2A by:
.

R1B = 20k
. R4B = R1 B = 20k
fOB2
R2B = R4B (fCLK/l00)2

_
fOA2
_
4
(529)2_
R2A - R4A(fCLK/l00)2 - 2 X 10 X ('1'OoOi2 - 5.6kand
R3A

=

QA ~R2AR4A

=

0.785 ~5.6 x 103 X 2 x 104

=

8.3k

IPa

BPA

BPs
N/AP/HPs

INVA

INVa

SI A

-

-5V

=

19.7k

vour

IPA

N/AP/HPA

2Dk

(993)2
20k('1'OoOi2

R3B = QB~R2BR4B = 3.559~1.97Xl04X2Xl04 = 70.6k
The complete circuit is shown in Figure 16 for split ±5V
power supplies. Supply bypass capacitors are highly recommended.
RIB
2Dk

VIN

=

20

R4B
2Dk

18
17

SIs

MF1D

AGND

SA/a

VA+5V

-5V

Vo0.1

5D/IDD/CL

-

10

CLKA

CLKa

-

11

CLDCKIHIlfi
fCLl( = 1DO kHz
TL/H/lD399-25

FIGURE 16. Fourth-Order Chebyshev Low-Pass Filter from Example In 3_1.
± 5V Power Supply. OV-5V TTL or - 5V ± 5V CMOS Logic Levels.
RIB
20k

Your

IPA

IPa

BPA

BPa
N/AP/HPa

IHVA
SIA

INVa

NFiD

SA/S

Sla
AGND

VAt

VA-

VO"

vo5D/IDD/CL
CLKg

20

R4B
2Dk

19

R3B
7D.6k

18

R2B
19.7k

17
16
15
14

0.1

13
12
11

TLlH/lD399-26

FIGURE 17. Fourth'()rder Chebyshev Low-Pass Filter from Example In 3.1.
Single + 10V Power Supply. OV-5V TTL Logic Level.. Input Slgnall
Should be Referred to Half-Supply or Applied through a Coupling Capacitor.

7-170

is:

3.0 Applications Information

....
C

."

(Continued)

v+

v+

'
fr
':"

T":'

,,,!,'WB,
2k,;;R ,;;100k

o.I,..F ,;;C ,;;470,..F
TUH/l0399-28
TL/H/l0399-27

(a) Resistive Divider with
Decoupllng Capacitor

(b) Voltage Regulator

TL/H/l0399-29

(c) Operational Amplifier
with Divider

FIGURE 18. Three Ways of Generating

V+

""2 for Single-Supply Operation

3.2 SINGLE SUPPLY OPERATION
10 will have a 20 dB peak in its amplitude response at fo. If
the nominal gain of the filter HOlP is equal to I, the gain at
The MFI 0 can also operate with a single-ended power supfo will be 10. The maximum input Signal at fo must therefore
ply. Figure 17 shows the example filter with a single-ended
be less than 800 mVp_ p when the circuit is operated on
power supply. VA + and Vo + are again connected to the
± 5V supplies.
positive power supply (BV to 14V), and VA - and Vo - are
connected to ground. The AGNO pin must be tied to V+ /2
Also note that one output can have a reasonable small voltfor single supply operation. This half-supply point should be
age on it while another is saturated. This is most likely for a
very "clean", as any noise appearing on it will be treated as
circuit such as the notch in Mode 1 (Figure 7). The notch
output will be very small at fo, so it might appear safe to
an input to the filter. It can be derived from the supply voltage with a pair of resistors and a bypass capacitor (Figure
apply a large Signal to the input. However, the bandpass will
18a), or a low-impedance half.supply voltage can be made
have its maximum gain at fo and can clip if overdriven. If
one output clips, the performance at the other outputs will
using a three-terminal voltage regulator or an operational
amplifier (Figures 18b and 18e). The passive resistor divider
be degraded, so avoid overdriving any filter section, even
with a bypass capacitor is sufficient for many applications,
ones whose outputs are not tieing directly used. Accompaprovided that the time constant is long enough to reject any
nying Figures 7 through 15 are equations labeled "circuit
power supply noise. It is also important that the half-supply
dynamics", which relate the Q and the gains at the various
reference present a low impedance to the clock frequency,
outputs. These should be consulted to determine peak circuit gains and maximum allowable signals for a given appliso at very low clock frequencies the regulator or op-amp
cation.
approaches may be preferable because they will require
smaller ~apacitonUo_JiJteUhe_clock_trequency. _The _main ---:r.4"OFFSETVOl:TAGE--------- -----"" ,,--- -,,--" - - - - - - - power supply voltage should be clean (preferably regulated)
The MF10's switched capacitor integrators have a higher
and bypassed with 0.1 /LF.
equivalent input offset voltage than would be found in a
3.3 DYNAMIC CONSIDERATIONS
typical continuous-time active filter integrator. Figure 19
The maximum signal handling capability of the MF10, like
shows an equivalent circuit of the MF10 from which the outthat of any active filter, is limited by the power supply voltput DC offsets can be calculated. Typical values for these
offsets with SAIS tied to V+ are:
ages used. The amplifiers in the MF10 are able to swing to
within about 1V of the supplies, so the input signals must be
Vos1 = opamp offset = ±5 mV
kept small enough that none of the outputs will exceed
-300 mV @ 100:1
Vos2 = -150 mV @50:1
these limits. If the MF10 is operating on ±5V, for example, '
-140 mV @ 100:1
VosS = -70mV@50:1
the outputs will clip at about 8 Vp_ p• The maximum input
When SAIS is tied to V-, Vos2 will approximately halve. The
voltage multiplied by the filter gain should therefore be less
DC offset at the BP output is equal to the input offset of the
than 8 Vp _ p.
lowpass integrator (Vos3). The offsets at the other outputs
Note that if the filter Q is high, the gain at the lowpass or
depend on the mode of operation and the resistor ratios, as
highpass outputs will be much greater than the nominal filter
described in the following expressions.
gain (Agure 6). As an example, a lowpass filter with a Q of

•

7-171

3.0 Applications Information (Continued)
Mode 1 and Mode 4
VOS(N)
VOS(BP)
VOS(LP)

~ode 1a

1

I

II)

= VOS1 (0 + 1 IHOLP

Mode 2 and Mode 5

Vosa

-

a

VOS(N)

= VOS3
= VOS(N)-VOS2

Vos(N.lNV.BP) =

R2)
1
= ( Rp + 1 VOS1 X 1 + R2/R4
1
VOS3
+VOS!21 +R4/R2 - Q,/1 + R2/R4
Rp = R1//R3//R4

(1 )
VOS3
1 +0 VOS1-

a

-VOS(BP) = Vosa
VOS(LP)

VOS(INV.BP)

= Vosa

VOS(LP)

= VOS(N.'NV.BP)-VOS2

= VOS(N) - VOS2

Mode 3
VOS(HP) = VOS2
VOS(BP)
VOS(LP)

= VOS3 [ R 4 ]
(R4)
= VOS1 1 + Rp - VOS2 R2

-VOS3 (::) Rp = R1/1R2//R3
-lP

TLlH/10399-30

FIGURE 19. MF10 Offset Voltage Sources
5V SUPPLY

-=

R3
TL/H/10399-31

FIGURE 20. Method for Trimming Vos

7-172

3:

3.0 Applications Information

."

.....
Q

(Continued)

For most applications, the outputs are AC coupled and DC
offsets are not bothersome unless large signals are applied
to the filter input. However, larger offset voltages will cause
clipping to occur at lower AC signal levels, and clipping at
any of the outputs will cause gain nonlinearities and will
change fa and Q. When operating in Mode 3, offsets can
become excessively large if R2 and R4 are used to make
fClK/fO significantly higher than the nominal value, especially if Q is also high. An extreme example is a bandpass
filter having unity gain, a Q of 20, and felK/fo = 250 with
pin 12 tied to ground (100:1 nominal). R4/R2 will therefore
be equal to 6.25 and the offset voltage at the lowpass output will be about + 1V. Where necessary , the offset voltage
can be adjusted by using the circuit of Figure 20. This allows
adjustment of VOS1, which will have varying effects on the
different outputs as described in the above equations. Some
outputs cannot be adjusted this way in some modes, however (VOS(BP) in modes 1a and 3, for example).

was f5/2 - 100 Hz. This phenomenon is known as "aliasing", and can be reduced or eliminated by limiting the input
signal spectrum to less than f9/2. This may in some cases
require the use of a bandwidth-limiting filter ahead of the
MF10 to limit the input spectrum. However, since the clock
frequency is much higher than the center frequency, this will
often not be necessary.
Another characteristic of sampled-data circuits is that the
output signal changes amplitude once every sampling period, resulting in "steps" in the output voltage which occur at
the clock rate (Figure 21). If necessary, these can be
"smoothed" with a simple R-C low-pass filter at the MF10
output.
The ratio of felK to fe (normally either 50:1 or 100:1) will
also affect performance. A ratio of 100:1 will reduce any
aliasing problems and is usually recommended for wideband input signals. In noise sensitive applications, however,
a ratio of 50:1 may be better as it will result in 3 dB lower
output noise. The 50:1 ratio also results in lower DC offset
voltages, as discussed in Section 3.4.

3.5 SAMPLED DATA SYSTEM CONSIDERATIONS
The MF10 is a sampled data filter, and as such, differs in
many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect on signals at frequencies greater than one-half the
sampling frequency. (The MF10's sampling frequency is the
same as its clock frequency.) If a signal with a frequency
greater than one-half the sampling frequency is applied to
the input of a sampled data system, it will be "reflected" to
a frequency less than one-half the sampling frequency.
Thus, an input signal whose frequency is f5/2 + 100 Hz will
cause the system to respond as though the input frequency

The accuracy of the fClK/fo ratio is dependent on the value
of Q. This is illustrated in the curves under the heading
"Typical Performance Characteristics". As Q is changed,
the true value of the ratio changes as well. Unless the Q is
low, the error in felK/fo will be small. If the error is too large
for a specific application, use a mode that allows adjustment
of the ratio with external resistors.
It should also be noted that the product of Q and fa should
be limited to 300 kHz when fa < 5 kHz, and to 200 kHz for
fa> 5 kHz.

100:1
--~~-~~~------~~--

50:1

TUH/l0399-32

FIGURE 21. The Sampled-Data Output Waveform

7-173

+--~--

Section 8
Analog Switches/
Multiplexers

•

Section 8 Contents
Analog Switches/Multiplexers Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
Analog Switches/Multiplexers Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0014/AH0014C DPDT, AH0015/AH0015C Quad SPST, AH0019/AH0019C Dual
DPST-TILlDTL Compatible MOS Analog Switches. . .... .... .. ... . .. . ..... . .. . . ..... .
AH501 0/ AH5011 / AH5012 Monolithic Analog Current Switches ..........................
AH5020C Monolithic Analog Current Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LF11331/LF13331/LF11332/LF13332/LF11333/LF13333,LF11201/LF13201/LF11202/
LF13202 Quad SPST JFET Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LF13508 8-Channel Analog Multipll;l1'er,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LF13509 4-Channel Differential Analog Multiplexer .....................................

8-2

8-3
8-4
8-5
8-9
8-20
8-28
8-39
8-39

»
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Analog Switch
Definition of Terms

::::J'

I

c

-...

CD

5"

;:;:

c)"
j

RON: Resistance between the output and the input of an

current ID going into the switch and the current Is going out
of the switch.
tRAN: Delay time when switching from one address state to
another.
tON: Delay time between the 50% points of an enable input
and the switch ON condition.
tOFF: Delay time between the 50% points of the enable
input and the switch OFF condition.

addressed channel.
Cs: Capacitance between any open terminal "S" and
ground.
Co: Capacitance between any open terminal "0" and
ground.
lo-Is: Leakage current that flows from the closed switch
into the body. This leakage is the difference between the

8·3

o

';r}

3

til

ttl

National Semiconductor

Analog Switch/Multiplexer Selection Guide

Part Number

Function

Logic Input

AH5011
AH5012

QUADSPST

TIL,CMOS
TIL,CMOS

LF11201/LF13201
LF11202/LF13202
LF11331/LF13331
LF11332/LF13332
LF11333/LF13333

QUADSPST

TIL
TIL
TIL
TIL
TIL

AH5020

Vs

TON/TOFF

(Typ)

ns(Typ)

-

RON

n

150/300
. 150/300

100
150

±15
±15
±15
±15
±15

90/500
90/500
90/500
90/500
90/500

200
200
200
200
200
150

DUALSPDT

TIL,CMOS

4-CHANNEL

TIL,CMOS

-

150/300

AH5010

150/300

150

LF13509

4-CHANNEL DIFFERENTIAL

TIL,CMOS

±18

1600/200

350

LF13508

a-CHANNEL

TIL,CMOS

±18

1600/200

350

8-4

~

o

....

o
~
.......

f:}1National Semiconductor

:J>

:%:

AH0014/AH0014C* DPDT, AH0015/AH0015C Quad
SPST, AH00191 AH0019C* Dual DPST-TTL/DTL
Compatible MOS Analog Switches

o

o
....
~

o
.......
:J>

:%:

o

General Description
This series of TTLlDTL compatible MaS analog switches
feature high speed with internal level shifting and driving.
The package contains two monolithic integrated circuit
chips: the MaS analog chip is similar to the MM450 type
which consists of four MaS analog switch transistors; the
second chip is a bipolar I.C. gate and level shifter. The series is available in hermetic dual-in-line package.
These switches are particularly suited for use in both military
and industrial applications such as commutators in data acquisition systems, multiplexers, AID and D/ A converters,
long time constant integrators, sample and hold circuits,
modulators/demodulators, and other analog signal switching applications.

o
....
en

The AH0014, AH0015 and AH0019 are specified for operation over the - 55'C to + 125'C military temperature range.
The AH0014C, AH0015C and AH0019C are specified for
operation over the - 25'C to + 85'C temperature range.

.......

Features

o
.......

•
•
•
•
•
•
•
•

±10V
500 ns

Large analog voltage switching
Fast switching speed
Operation over wide range of power supplies
Low ON resistance
High OFF resistance
Analog signals in excess of
Fully compatible with DTL or TTL logic
Includes gating and level shifting

2000
1011 0
25 MHz

:J>
:%:

o

o
....
en

:J>

:%:

o

o
....
CO

.......

:J>
:%:

o

o
....
co

o

Block and Connection Diagrams
QuadSPST
ANALOG 8:
IN AI,

~

ANALOG 9:

•

IN B1

I

7:

ANALOG
INAl,
ANALOG 6:

:

i 10

ANALOG

--:-00 --......;,""-0111 1

ANALOG
IN 1

:

,

~

• ~

~ANALOG

,, ,,

,

OUT 1

AN~g~~~Lfl
'5

:

ANALOG
OUT 2

AN~

_____n~~2 J--i-'--nn~E-! - - - - -12

11:,
•

I

7;

~:

•

I

I

I

I

I

I

: ;0

~~LfG

A~O~~~'~i:
~:~~:j'iT\""
~~~L~G
,
t. _________

13 - - - - - - .:.L-GND

LOGIC
A
LOGIC

__

un __ _

~~Wo

2
1
16
15
LOGIC LOGIC LOGIC LOGIC

4

8
Note: All logic inputs shown at logic "1".

3

2

Note: All logic Inputs shown allogie "1".

TUK/Hil25-1

Order Number AH00140 or AHOO14CO
See NS Package Number 0140

I

TLiK/l0125-2

Order Number AH00150 or AH0015CO
See NS Package Number 016C
OualOPST

ANALOG 6.--------------.
INAI~

,

ANALOGJj:..: _

1.lJ....ANALOG

~;

INBt.

I

ANALOG 9.

I

I

I

•

IN A2

,

ANALOG 8,
IN 02 ,

OUTt

I

,
I

"y:
~:

~~NALOG
01112

'
,

:iL
:,t___~'~'
_______ hT~

NOIe: All logic Inputs shown allogie "1".

~~

I 2

13 12

LOGIC
LOGIC
A1
Al
LOGIC
LOGIC

01

82

Order Number AH00190 or AHOO19C0
See NS Package Number 0140
'Previously called NHOO14/NHD014C and NH0019INH0019C

8-5

TLiK/l0125-3

•

o
Q)
..-

g

:I:
c(

C;
..Q
Q

:I:

c(
.....

Absolute Maximum Ratings
V+ IV- Voltage Differential
Logic Input Voltage
Storage Temperature Range
Operating Temperature Range
AH0014, AH0015, AH0019
AH0014C, AH0015C, AH0019C
Lead Temperature (Soldering, 10 se6)

If Military/Aerospace specified devices are required,.
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Vcc Supply Voltage
7.0V
V- Supply Voltage
-30V
V+ Supply Voltage
+30V

o

II)

..Q
Q

:I:

~
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c(

Parameter,
Logical "1" Input Voltage
Logical "0" Input Voltage
Logical "I" Input Current

Q
Q

Logical "0" Input Current

:I:

Logical "I" Input Current

Condltlor:1s

= 4.5V
Vee = 4.5V·
Vcc

p.A

0.2

0.4

mA

0.85

1.6

iliA

1.5
0.22
0.22

3.0
0.41
0.41

mA
mA
mA

75
150

200
600

n
n
n

25
25
0.1
30

200
200
10
100

pA
nA
nA
nA

40
40
0.05.
4

400
400
10
50

pA
nA
nA

10

pF

11

13

pF

600

750

ns

= 5.5V, VIN = OV

= + 10V
= -10V

lOll

Analog Switch OFF Resistance

AH0014C, AH0015C, AH0019C
Analog Input (Drain) Capacitance

V

p.A

VIN (Analog)
VIN (Analog)

Analog Switch Output Leakage
Current-Each Output (Note 4)
AH0014, AH0015, AH0019

Units

1

Analog Switch ON Resistance-Each Gate

AH0014C, AH0015C, AH0019C

Max

5

= 2.4V
= 5.5V, VIN = 5.5V
Vee = 5.5V, VIN = 0.4V
'Vcc = 5.5V, VIN = 4.5V
Vee

Analog Switch Input Leakage CurrentEach Input (Note 4) ,
AH0014, AH0015, AHOO19

Typ

2.0

Vcc

Power Supply Current Logical "0"
Input-Each Gate (Note 3)
AH0014, AHOO14C
AH0015, AHOO15C
AH0019, AHOO19C

c(

Min

Vee == 5.5V, "IN

Q

Q

- 55'C to: + 125'C
- 25'C tei + 85'C
3000C

V

Power Supply Current Logical "I"
Input-Each Gate (Note 3)

:I:

+ 1500C

0.8

c(

;;r
..-

-:-65~Cto

Electrical Characteristics (Notes 1 and 2)

......
o
'Oil'
..-

40V
. 5.5V

VIN

= -10V

= 25'C
= 125'C
= 25'C
= 700C
VOUT = -10V

TA
TA
TA
TA

TA
TA
TA
TA

= 25'C
= 125'C
= 25'C
= 700C

1 MHz @ Zero Bias

Output Source Capacitance

1 MHz @ Zero Bias

Analog Turn-OFF Time-toFF

See Test Circuit; TA = 25'C

8

I1A

Analog Turn-ON Time-tON
See Test Circuit; TA .;, 2sOC
AH0014, AH0014C
350
425
ns
AH0015, AH0015C
100
150
ris
AH0019, AHOO19C
100
150
ns
Note I: MinImax limits apply across the guaranteed temperature range of -55'C to + 125'C for AHOOI4. AHOOI5. AHOOl9 and -25'C to + 85'C for AHOOI4C.
AHOOI5C. AHOOI9C. V- = -20V. V+ = +10V and an analog test current of 1 rnA unless otherwise specHled.
Note 2: All typical values are measured at TA = 25'C with Vee = 5.0V. V+ = + ~OV. V- = -22V.
Note 3: Current measured is drawn from Vee supply.
Note 4: All analog switch pins except measurement pin are tied to V+.

8-6

r--------------------------------------------------------------------.~

::I:

Analog Switch Characteristics (Note 2)
RON vs Temperature
125

I

,V

..... .....

75

so

RON vs Temperature
125

V,"~V~=+10V

100

.... I-'

1

100

l:l

75

ill

SO

:!

~

l.:
?

25

o

-sso

250

-150

SSO

CI
CI

VINI=V~UT=OV

-

, l/

RON vs Temperature
225

/

25

::I:

200

CI
CI

Ii!
ill
ill

175

o
"'"
......

:!

~"""

VINI=V~UT=-IOV

1

l.:
?

....

/

~

~

150

::I:

V

CI
CI

....
C7I

'",

125

i.-"

"""

100
-sso

105"

AMBIENT TEMPERATURE (DC)

....
......
"'~"

25"

-150

SSO

l>
::I:

105"

CI
CI

....

AMBIENT TEMPERATURE (DC)

AMBIENT TEMPERATURE (DC)

C7I

o
......
Leakage vs V,N (Channel "OFF")
50

75

v+=10V

~~~~O~CT

'i'

50

E
~

........

20 CHANNa "ON:'_ CHAJ!N;:~H':-

V-=-2OV

25

~

==CHANNa
"ON"
V-=-10V",

~~~~~~FF"

-75

1
-10 -8 -6 -4 -2 0 +2'" +6 +8 +10

+10

-10

-5

l!5
l'l

-10

I

-20

'"

Vcc= 5.0V
V""=-22V
v+=8.OY

125DC

!i!
~

Driver Gate V,N vs VOUT

+S

!:!i

r-.~

I{'

10

+10

25DC

....

CD

CI
CI

....
CD

-15

-2S

CI
CI

l>
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-5SDC

r-

~

::I:

o

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ANALOG VIH (V)

1.0 1.5 2.0

30

2.5

3.5

INPUT VOLTAGE (V)
TL/K/l0125-6

Schematic (Single Driver Gate
and MOS Switch Shown)

Analog SWitching Time Test Circuit

+IOV:o:J.f'VOUT
VIN

y+ ANALOG
IN

-Do '
•••

RL

6.8k
~---

4;5k----------- - - --ANA[OG

fOUT

TL/K/l012S-8

A
B

7k

OV--+-:-I
TL/K/l0125-9

4,Sk

V+

TL/K/l0125-7

Selecting Power Supply Voltage
The graph shows the boundary conditions which must be
used for proper operation of the unit. The range of operation
for power supply V- is shown on the X axis. It must be
between -25V and -BV. The allowable range for power
supply V+ is governed by supply V-. With a value chosen
for V-. V+ may be selected as any value along a vertical
line passing through the V- value and terminated by the
boundaries of the operating region. A voltage difference between power supplies of at least 5V should be maintained for
adequate signal swing,

B-7

25
20
15
10
S
0
-S
-10
-IS
-20
-2S

•
TL/K/l0125-10

Typical Applications
Integrator

Reset Stabilized Ainpllfier
AH0014

RESET

,- - - - - - - - -

I
I

~

- - AH0014 ;

r

Your

TLlK/l0125-4

TlIK/l0125-5

8·8

»

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.....

tt/National Semiconductor

C)

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AHS0101 AHS01.11 AHS012 Monolithoc
Analog Current Switches

en

.....
.....
C)

i>
::c

El Active filters

General Description

en

III Signal multiplexers/demultiplexers

A versatile family of monolithic JFET analog switches economically fulfills a wide variety of multiplexing and analog
switching applications.
Even numbered switches may be driven directly from standard 5V logic, whereas the odd numbered switches are intended for applications utilizing 10V or 15V logic. The monolithic construction guarantees tight resistance match and
track.

IJ
IJ
IJ
IJ

c
iii

C)
.....

Multiple channel AGC
Quad compressors/expanders
Choppers/demodul!ltors
Programmable gain amplifiers
High impedance voltage buffer
Sample and hold

N

feaiures

For voltage switching applications see LF13331, LF13332,
and LF13333 Analog Switch Family, or the CMOS Analog
Switch Family.

Interfaces with standard TTL and CMOS
[] "ON" resistance match
[] Low "ON" resistance
IJ Very low leakage
[J Large analog signal range
[J High switching speed
EI Excellent isolation between
channels
CI

Applications
• AID and 0/ A converters
.• Micropower converters
• Industrial controllers
• Position controllers
• Data acquisition

2.0.
100.0.
50 pA
±10V peak
150 ns
80 dB
at 1 kHz

Connection and Schematic Diagrams (All switches shown are for logical "1" input)
Dual-In-Llne Package

Dual-In-Line Pacl(age

"

"

13

15

"

LOGIC DRIVE

11

4 CHANNEL
MUX

4SPST
SWITCHES

"13

5VLOGIC
AH5010C
AH5012C
J5V !-.QG1C_~ - - - - - - - _AI-I5D.l-1C_

10

"- - - - -

------~---

11

10

TOP\lIEW

AH5010C MUX Switches
(4-Channel Version Shown)
Order Number AH5010CN
See NS Package Number M14A or N14A

Tap VIEW

AH5011C and AH5012C SPST Switches
(Quad Version Shown)
Order Number AH5011CN,
AH5012CM or AH5012CN
See NS Package Number M16A or N16A

120--+--'

100--+---'

II

120--+----'

130--,"--'

"

15

COMMON DRAIUS

UNCOMMlnED DRAINS TL/H/S659-1

Note: All diode cathodes are internally connected to the substrate.

8-9

•

Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Input Voltage
AHS01 0/ AHS011 / AHS012
Positive Analog Signal Voltage
Negative Analog Signal Voltage
Diode Current

-

30V
30V
-1SV
10mA

Drain Current
Soldering Information:
N Package 10 sec
SO Package Vapor Phase (60 sec.)
Infrared (1S sec.)
Power Dissipation
Operating Temperature Range
Storage Temperature Rang'e

30mA
300"C
21SoC
220°C
SOOmW
- 2SoC to + 8SoC
- 6SoC to + 1S0°C

Electrical Characteristics AH5010 and AH5012 (Notes 2 and 3) ,
Symbol

Conditions

Typ

Max

Units

0.01

0.2
10

nA
nA

Vso=0.7V, VGs=3.8V
TA=8SoC

0.02

0.2
10

nA
nA

Leakage Current "ON"

VGO=OV, Is=1 mA
TA=8SoC

0.08

1
200

nA
nA

IG(ON)

Leakage Current "ON"

VGo=OV, Is= 2 mA
TA=8SoC

0.13

S
10

nA
p.p,

IG(ON)

Leakage Current "ON"

VGO=OV, Is= -2 mA
TA=8SoC

0.1

10
20

nA
p.A

rOS(ON)

Drain-Source Resistance

VGs=0.3SV, Is=2 mA
TA= +8SoC

90

1S0
240

0
,0

Parameter

IGSX

Input Current "OFF"

10(OFF)

Leakage Current "OFF"

IG(ON)

4.SV~VGO~11V,

Vso=0.7V

TA=8SoC

VOIODE

Forward Diode Drop

10=0.SmA

rOS(ON)

Match

VGS = OV, 10=1 mA

TON

Turn "ON" Time

TOFF
CT

Turn "OFF" Time
CrossTalk

0.8

V

4

20

0

See AC Test Circuit

1S0

SOO

ns

See AC Test Circuit

300

SOO

See AC Test Circuit

120

ns
dB

Electrical Characteristics AH5011 (Notes 2 and 3)
Parameter

Typ

Max

Units

0.01

0.2
10

nA
nA

Vso=0.7V, VGs=10.3V
TA=8SoC

0.01

0.2
10

nA
nA

Leakage Current "ON"

VGo=OV,ls= 1 mA
TA=8SoC

0.04

O.S
100

nA
nA

IG(ON)

Leakage Current "ON"

VGO=OV, Is=2 mA
TA=8SoC

2
1

nA
p.A

IG(ON)

Leakage Current "ON"

VGo=OV, Is= -2 mA
TA=8SoC

S
2

nA
p.A

rOS(ON)

Drain-Source Resistance

VGS= 1.SV, Is=2 mA
TA=8SoC

100
160

0
0

Symbol

'GSX

Input Current "OFF"

10(OFF)

Leakage Current "OFF"

IG(ON)

Conditions
11V~VGO~1SV,

VSo=0.7V

TA=8SoC

VOIOOE

Forward Diode Drop

10=0.SmA

rosION)

Match

VGS=OV, 10=1 mA

TON

Turn "ON" Time

See AC Test Circuit

Turn "OFF" Time

See AC Test Circuit

60

0.8

V

10

0

1S0

SO

ns

300

SOO

2

ns
TOFF
CT
CrossTalk
See AC Test Circuit. f = 100 Hz.
120
dB
Note ,: Absolute maximum ratings Indicate limits beyond which damage to the device may occur. DC and AC eleCtrical specmcations do not apply when operating
the device beyond its spacified operating conditions.
Note 2: Test conditions 25'C unless otherwise noted.
Note 3: "OFF" and "ON" notation refers to the conduction state of the FET switch.
Note 4: Thermal Resistance:
N14A.N16A
M14A,M16A

8JA

9Z'C/W

115"C/W

8-10

.--------------------------------------------------------------------,~

%

Test Circuits and Switching Time Waveforms

(II

....

<:)
<:)

);

Cross Talk Test Circuit
r------+~1~6V~---------,

%

(II

....
....

<:)

;;
%
....

10k

(II

<:)

.-o VO

~6:....____

N

UT

10k

10k
-15V

+5Vor+15V

Time Waveforms
+5V or +15V

AC Test Circuit

__'!A = tl0V
OV
VOUT

VOUT

--o (CL $ 10 pFJ

r - - -....

OV

OV

VA = -10V

TUH/5659-2

8-11

•

~ r-----------------------------------------------------------------------------------------~

i

~....

Typical Performance Characteristics

....

~

::I:

~

lOUD
~c

=.!.

::I:

iEB

----41--0 ANALOG
OUTPUT

FIGURE 1. Use of Compensation FET
ID = Is - IG(DNI

-.

VA c+IOV ()o-V\,.".-<>-..---i

RZ

TL/H/5659-4

FIGURE 2. On Leakage Current, IG(ON)

8-13

::::t:

en
C)

.....

.....
.....
)0::::t:

g:
.....
N

~r-----------------------------------------------------------------I
.....
Applications Information (Continued)
~

~.....

.....

Where: VA(MAX)

~

~.....
~

:::c

c:c

Accordingly:

= Peak. amplitude of the analog
. input signal .

Ao

= Desired accuracy

IG(ON)
loss

= Leakage at a given Is
= Saturation current of the FET
switch·

I'll M·· ~ VA(MIN) Ao
( AX)

"'20.mA
In a typical application, VA might = ±10V, Ao=0.1%,
O'C~TA~8S'C. The criterion of equation (2b) predicts:
.
(10V)
R1(MIN)~ (20,~A) S kG

(MIN)

= Number of channels

Selection of R2, of course, depends on the gain desired and
for unity gain R1 = R 2 . · ·
Lastly, the foregoing discussion has ignored resistor tolerances, input bias current and offset voltage of the op ampall of which should be considered in setting the overall gain
accuracy of the circuit.

1 x10-6

Since equation (2a) predicts a higher value, the 10k resistor
should be used.

TTL Compatibility

The "OFF" condition of the FET also affects gain accuracy.
As shown in Figuf6 3, the leakage across Q2, IO(OFF) represents a finite error in the current arriving at the summing
junction of the op amp.

The AH series can be driven with two different logic voltage
swings: the even numbered part types are specified to be
driven from standard 5V TIL logic and the odd numbered
types from 1SV open collector TIL.

'D '"

Q2

N

= "OFF" leakage of a given FET
switch ..
As an example, if N = 10, Ao = 0.1 %, and IO(OFF) ~ 10 nA
at 8S'C for the AH5010. R1(MAX) i.s:
.
(1V)(10- 3)·
R1(MAX)~(10)(10X10 9) 10k

~ (10V)(10-3)~10 kG

R1

Ao .

= Minimum value of the analog input signal
= Desired accuracy

IO(OFF)

For R1 = Sk, Is '" 10VlSk or 2 mAo The electrical characteristics guarantee an IG(ON) ~ 1,iAat 8S'C for the AH5010.
Per the criterion of equation (2a):
R1

(N) IO(OFF)

Where: VA(MIN)

-

Is + 'DIOFF)

I~

"OFF"

I
I
TUHf5659-5

FIGURE 3

8-14

Applications Information

»
::E:
en

(Continued)

Standard TTL gates pull-up to about 3.5V (no load). In order
to ensure tum-off of the even numbered switches such as
AH5010, a pull-up resistor, REXT, of at least 10 kO should
be placed between the 5V Vee and the gate output as
shown in Figure 4.
Ukewise, the open-collector, high voltage TTL outputs
should use a pull-up resistor as shown in Figure 5. In

both cases, t(OFF) is improved for lower values of REXT at
the expense of power dissipation in the low state.
Definition of Terms
The terms referred to in the electrical characteristics tables
are as defined in Figure 6.

o
.....
o

.....

»
::E:
g:
.....
.....

"»
::E:
g:

.....

r--------,
I
I
I
I
I
I

+5V

10k
RUT

> ....~OANAlOG
OUTPUT

(2k
TO
10k)

lOGIC
INPUT

1
1

(VIN)

I

I

I

N

ANALOG
INPUT IVA)

-

_..JI

~~~-..:-..:.

FIGURE 4. Interfacing with

A~N"'Ac.-lftCOG-----

-+5V-OR-+15V-

I

I

I
I
I

I

-"~---~------

-- --

-----~-- --~---

-~---~---

-- - - -

----~-

INPUT (VA)

r-------,
I
I
I
I

+ 5V TTL

10k

> ....~OANALOG

+15V

OUTPUT

RUT

(2kTO
10k)
lOGIC
INPUT
(Vin)

FIGURE 5. Interfacing with

+ 15V Open Collector TTL

8-15

TUH/5659-6

•

Applications Information

(Continued)
ROSION ) COMPENSATING
,ELEMENT'

Is

R;

VA~~IV~~~--~S
-..--~

SHUNT~
ELEMENT

FIGURE 6. Definition of Terms

Typical Applications
De-Glitched Switch for Noiseless Audio Switching

OFF
RC TYPICALLY

.r

(1

ms-l0 msl
Rf

AUDIO
SIGNAL 0----'\1"",....----4......"
INPUT
>'-4!~-o OUT

TL/H/5659-7

8-16

~

Typical Applications

::J:
UI

(Continued)

o
....
o

3-Channel Multiplexer with Sample and Hold

);

::J:

en

o
....
....

i>
::J:
UI

o
....
N

11
ANALOG
INPUTS

10k

I

9

I

10k

I

L __ •

10k

II

4

I
_____ ..JI
12

I

1

CHARACTERISTICS: TYPICAL OUTPUT
VOLTAGE DRIFT

14

''--~-'

<5mVlsec

CHANNEL
SELECT

SAMPLE/HOLD
SELECT

TLlH/5659-8

8·Bit Binary (BCD) Multiplying 01 A Converter'
12.5k
V.

r-------,

I

I
I

15k

FULL-SCALE ADJUm~ENT
Zk
~

________

~-~50k-

*Recommended resistor array connection for 01 A application
VA

lOOk
1

1&

i

.........

40R8
lOR7
SWITCH
2 OR & CONNECTIDN

8

12.lk

9
lOR 5

20
25k

10k

lOOk

I':"

I
I
I
I
I
I
I
I
I
I

I

TL/H/S659-12

2 Beckman resistor arrays
Part .. 698-1-R lOOk B recommended

R, (lIT 1, + G2 12 + G3 13 + Cf:""-_-0

':'

.....
.....
~

EOUT

:i:
(II
<:)

.....

':'

11

N

r

10k

I

I

I
I
I
I
I
I
I
I

6

lOOk

9

1M

13

10M

I

L_

--1 CHARACTERISTICS: GAIN' -EI0"O

UT •

RF.

12

GAIN SELECT

TL1H/5659-10

8-19

~~

tfI

Nat ion a I S e m i con due .t 0 r

AH5020C Monolithic Analog Current Switch
General Description

Applications

This versatile dual monolithic JFET analog switch economically fulfills a wide variety of multiplexing and analog switching applications.

• AID and DIA converters'

These switches may be driven directly from' standard 5V
logic.
The monolithic construction guarantees tight resistance
match and track.

Features
•
•
•
•
•
•
•

Interfaces with standard TTL
"ON" resistance match
Low "ON" resistance
Very low leakage
Large analog signal range
High switching speed
Excellent isolation between
channels

20
1500
50 pA
±10V peak
150 ns
80 dB
at 1 kHz

• Micropower converters
• Industrial controllers
• Position controllers
• Data acquisition
• Active filters
• Signal multiplexers/demultiplexers
• Multiple channel AGC
• Quad compressors/ expanders
• Choppers/demodulators
• Programmable gain'amplifiers
• High impedance voltage buffer
• Sample and hold
For voltage switching applications see LF13201, LF13202,
LF13331, LF13332, and LF13333 Analog Switch Family, or
the CMOS Analog Switch ,Family.

Connection and Schematic Diagrams (All switches shown are for logical "1")
Dual-in-Line Package

TUH/5166-1

Top View
Order Number AH5020CJ
See NS Package Number J08A

4

8'

5
TL/H/5166-2

Note: All diode cathodes are Internally COI1nec1ec1 to the substrate.

8-20

l>

:::E:

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Input Voltage
30V
Positive Analog Signal Voltage
30V
-15V
Negative Analog Signal Voltage
Diode Current
10mA

(JI

Drain Current
Power Dissipation
Operating Temp. Range
Storage Temperature Range
Lead Temp. (Soldering. 10 seconds)

30mA
500mW
-25'Cto +85'C
-65'Cto + 150'C
300'C

Electrical Characteristics (Notes 2 and 3)
Symbols

Parameter

Conditions

Typ

Max

Units

0.01
0.01

0.1
0.2
10

nA
nA
nA

0.01

0.2
10

nA
nA

IGSX

Input Current "OFF"

VGO = 4.5V. VSO = 0.7V
VGO = 11V. VSO = 0.7V
TA = 85'C. VGO = 11V. VSO = 0.7V

10(OFF)

Leakage Current "OFF"

VSO = 0.7V. VGS
TA = 85'C

IG(ON)

Leakage Current "ON"

VGO = OV. Is
TA = 85'C

= 1 mA

0.08

1
200

nA
nA

IG(ON)

Leakage Current "ON"

VGO = OV. Is = 2 mA
TA = 85'C

0.13

5
10

nA
/LA

IG(ON)

Leakage Current "ON"

VGO = OV.ls
TA = 85'C

0.1

10
20

/LA

150
240

n
n

0.8

V

= 3.8V

= -2mA

rOS(ON)

Drain-Source Resistance

VGS = 0.5V. Is
TA = +85'C

VOIOOE

Forward Diode Drop

10

= 2 mA

90

= 0.5mA

nA

rOS(ON)

Match

VGS = O. 10 = 1 mA

2

20

n

TON

Turn "ON" Time

See ac Test Circuit

150

500

ns

TOFF

Turn "OFF" Time

See ac Test Circuit

300

500

CT

CrossTalk

See ac Test Circuit

120

- ._-

--

Note 1: Absolute Maximum Ratings indicate limits beyond
the device beyond its specified operating conditions.

ns
dB

whichdamageto tile caviee -mayoccur.- DC-and-AC-electrlcal specifications-do not apply when operating--

Note 2: Test condHions 25'C unless otherwise noted.
Note 3: "OFF" and "ON" notation refers to the conduction state of the FET switch.
Note 4: Thermal Resistance:
8JA (Junction to Ambient) .......... NI A
8JcCJunciion to Case) ........... .. N/A

8-21

o
o

N

o

Test Circuits
.Cross Talk Test Circuit

AC Test Circuit

111lt

VOUT

r - -....--o (CL:s10 pF)

10k

>:.....-..... VOUT

TlIH/5166-4

TlIH/5166-3

Switching Time Waveforms

ov
O.8V --t-~~--t-~
VOUT

VA = +IOV
ov
ov
VOUT

VA'" -1OV--1r---f'---+--"'"
TLlH/5166-5

8·22

r--------------------------------------------------------------------,~

::c

Typical Performance Characteristics

U'I

~o

rtGS(Off) @ vos - -15V. ~ = - InA
IDS @~=-1 mAo Vos=OV
1III@Vos=-15V.Vos=OVPULS

~

c

(')

10k

~

!iiII!

loss

~i-"

IG

Leakage Current, ID(OFF)
vs Temperature

Parameter Interaction

./

Ik

...

::::>

I

./

100

I

lOS

J

I)

10
1.0
1.0
5 10
100
VGs-GATE·SOURCE CUTOFF VOLTAGE (V)

I

I

45 55 65 75
TEMPERATURE (OC)

I

85

10
25

35

TLlH/5166-6

TL/H/5166-7

"ON" Resistance, rDS(ON)
vs Temperature
150

S'

;; 125

5VTTL

li!

il! 100
m 75

:::;;;00 i"'"

5Vs:!.

Cross Talk, CT vs Frequency

-

.L

10=-1 mA

-120 rr..,..,.,rr-r"'T'T"-""""'''''''''''';''=
-110 H"OiH-IhH-Ht--H~V;A = ± 10V
~-100 ~~~~~~~-r++H
~ -90 ~+tH-'N::~~~-r++H

.-- ~

~ -80 ~-I-l1f1-++I!!k-H-l+l-+-+#I
Ii; -70 1+++I'1-++Hl~~i-t-ttH
~ -&0 ~+tH-~~~li9Iod-++H
-50 ~+tH-~~~~-f'!f"I+I

...... ~TTL/IOL5V CMOS

~

):

'i'

t; -40 I-t-tffii-t-Htt-+-Htt-t-Htf
-30 I-t-tffii-t-Htt-+-Htt-t-Htf
-20r+~~-H*-r+Ht-~+H

o
25

35

45 55 65 75
TEMPERATURE rC)

-10 L..L..J.J.U-L..J.J.U-L..J.J.U-L-LW
100
lk
10k
lOOk
1M
FREQUENCY (Hz)

85
TLlH/5166-8

TL/H/5166-9

Leakage Current vs
Drain-Gate Voltage

----!i':000::~ii~~~!i;:Ii~1-

:i

!

.--

Transconductance vs
Drain Current
100 TA=25"C
Voo=-5V
'=1 kHz

.------~--\"'-=--+-=i-fo_l-r++Iff+___+_H_++I+H

I~ 10~~3i~~~~~
~
lE-~~~~~~~

5.0
10
15
20
DRAIN-GATE VOLTAGE (V)

-0.1

25

-1.0
DRAIN CURRENT (mA)

-10
TLlH/5166-11

TL/H/5166-10

Drain Current vs Bias
Voltage
-25

11

Normalized Drain Resistance
vs Bias Voltage

§'OO

Vos=-lDV
.=1 kHz
TA=25"C

1\
\

......

~
'"

~.

,

-.l \
\

~

o

o

ia
\.

!

"-

co

,
"'"

:IE

'"z

Vos(OFF) @ -lOY. -10 pA

-

J

o
TLlH/5188-12

-I--

5.0

i

1.0
2.0
3.0
DATE-SOURCE VOLTAGE (VI

t::
f=

l-

J

10

I 2.0

I"-

-

50 IDSb=~
I
Yos
-YGS(OFF
20

... "'"

~

0.2 0.4
0.6 0.8 1.0
IYos IYoS(OFF) I-NORMAUZED
DATE-TO-SOURCE VOIlAGE (V)
TLlH/5188-13

8-23

Applications Information
THEORY OF OPERATION
The AH5020 analog switches are primarily intended for operation in current mode switch applications; i.e., the drains
of the FET switch are held at or near ground by operating
into the summing junction of an operational al1)plifier. Limiting the drain voltage to under a few hundred millivolts eliminates the need for a special gate driver, 'allowing the
switches to be driven directly by standard TTL.
If only one of the two switches, in each package is used to
apply an input signal to the 'input of an op amp, the other
switch FET can be placed in the feedback path in order to
compensate for the "ON" resistance of the switch FET as
shown in Figure 1.

NOISE IMMUNITY
The switches with the source diodes grounded exhibit improved noise immunity for positive analog signals in the
"OFF" state. With VIN = 15V and the VA = 10V, the
source of 01 is clamped to about 0.7V by the diode (VGS =
14.3V) ensuring that ac signals imposed on the10V input
will not gate the FET "ON".
SELECTION OF GAIN SETTING RESISTORS
Since the AH5020 analog switches are operated in current
mode, it is generally advisable to make the signal current as
large as possible. However, currenUhrough'the FET switch
tends to forward bias tlie source to gate junction and the
signal shunting diode resulting, in leakage through these
junctions. As shown in Figure 2, IG(ON) represents a finite
error in'the current reaching the summing junction of the op
amp.

The closed-loop gain of Figure 1 is:

A

veL =

R2
- R1

+ roS(ON)02
+ roS(ON)Ol

Secondly, the roS(ON) of the FET begins to "round" as Is
approaches loss. A practical rule of thumb is to maintain Is
at less than Yto of loss.
Combining the criteria from the above discussion yields:

For R1 = R2, gain accuracy is determined by the roS(ON)
match between 01 and 02. Typical match between 01 and
02 is 2fl resulting in a gain accuracy of 0.02% (for Rl = R2
= 10 kn).

Rl MIN :<: VA(MAXl AD
()
,IG(ON)

(2a)

or:

:<: VA(MAX)

(2b)

lossIl0
whichever is larger.

HI

10k

H2
10k

>~_~~ANALDa
OUTM

TL/H/5166-14

FIGURE 1. Use of Compensation FET

IS"'~

,Rl-

R2

, Tl/H/5166-15

FIGURE 2. On Leakage Current, IG(ON)

8-24

r--------------------------------------------------------------------.>
Applications Information
Where VA(MAX)
AD
IG(ON)
loss

::J:
U1

(Continued)

o
~
o

Accordingly:

= Peak amplitude of the analog input
signal
= Desired accuracy
= Leakage at a given Is
= Saturation current of the FET switch
= 20mA

o

R1 MAX :s:VA(MIN) AD
. (
) (N) IO(OFF)
Where VA(MIN) . = Minimum value for the analog input signal
AD
= Desired accuracy
N
= Number of channels
IO(OFF)
= "OFF" leakage of a given FET switch

In a typical application, VA might = ±10V, AD =0.1%, O'C
:s: TA :s: 85'C. The criterion of equation (2b) predicts:
10V
R1(MIN);;: 20 mA =5 kn

As an example, if N=10, Ao=0.1%, and IO(OFF) :s: 10 nA
at 85'C for the AH5020. R1(MAX) is:
(1V)(10- 3)
R1(MAX) :s: (10)(10 x 10-9) 10k

10
For R1 = 5k, Is "" 10V/5k or 2 mA. The electrical characteristics guarantee an IG(ON) :s: 1/LA at 85'C for the
AH5020. Per the criterion of equation (2a):
(10V)(10- 3)
R1(MIN);;: 1 x 10 6 ;;: 10 kn

Selection of R2, of course, depends on the gain desired and
for unity gain R1 = R2.
Lastly,
ances,
amp overall

Since equation (2a) predicts a higher value, the 10k resistor
should be used.

the foregoing discussion has ignored resistor tolerinput bias current and offset voltage of the op
all of which should be considered in setting the
gain accuracy of the circuit.

The "OFF" condition of the FET also affects gain accuracy.
As shown in Figure S, the leakage across Q2, IO(OFF) represents a finite error in the current arriving at the summing
junction of the op amp.

II"~

81VAI .....WIr-<>-...-

R2

....

"'~--~--~--~------

R1

TL/H/5166-16

FIGURE 3. Off Leakage Current, ID(OFF)

8·25

--

-~.------

o ,-----------------------------------------------------------------------,
o
~

In
~

~

Applications Information

(Continued)

TTL COMPATIBILITY
Standard TTL gates pull-up to about 3.5V (no Iqad). In order
to ensure turn-off of the AH5020, a pull-up resistor, REXT of
at least 10 kO should be placed between the 5V Vee and the
gate output as shown in Figure 4.

DEFINITION OF TERMS
The terms referred to in the electrical characteristics tables
are as defined in Figure 5.

ANALOG
INPUT (VAl

r-:--~--, sv

Am
ANALOG

(2k
TO

OUlPUT

10k)

I
I
I
L::
_ _ _':'
_ _':' .J
I 5V _
m GATE

LOGIC
INPUT (VII)

TLlH/5166-17

FIGURE 4. Interfacing with

+ 5V TTL

VA ......WII-.....---::--,

a.:,:-

TLlH/5166-1B

FIGURE 5. Definition of Terms

8-26

~-------------------------------------------------------------------,~

:I:

Typical Applications

U1

o
N
o

o
Deglltched Switch for Noiseless Audio Switching
OFF

ftC TYPICALLY

1 ms-l0 ms
rON

ftl

AUDIO
SIGNAL --,\Mr--"'~~
INPUT

> ....-OUT

TIJH/5166-19

Gain Programmable Amplifier

-

liN

10k

>---+-EoUT

--I=,

.....

~=;.....-

I
I
I
I
I
I
I

10k

-.;.o.-'\j~-t-

- - - -- --

-~--~---I----

lOOk

. Characteristics: Gain

L __ _

= - EIOUT = RFS
IN

2
GAIN SELECT

TLlH/5166-20

8-27

~

~
C')

r----------------------------------------------------------------------------,

.... ttlNational Semiconductor

II.
...I

......
~
o

SPST JFET Analog Switches
....
.... Quad
LF11331, LF13331 4 Normally Open Switches with Disable
~
....
.... LF11332, LF13332 4 Normally Closed Switches with Disable
~

o

~
C')

....
II.
...I
......
....
~
....
....
II.
...I

~

C')
C')
C')

....
....
....
....

II.
...I
C')
C')
C')

LF11333, LF13333 2 Normally Closed Switches and 2 Normally Open Switches with Disable
LF11201, LF132014 Normally Closed Switches
LF11202, LF13202 4 Normally Open Switches

General Description

Features

These devices are a monolithic combination of bipolar and
JFET technology producing the industry's first one chip
quad JFET switch. A unique circuit technique is employed to
maintain a constant resistance over the analog voltage
range of ± 10V. The input is designed to operate from mini~
mum TTL levels, and switch operation also ensures a breakbefore-make action.
These devices operate from ± 15V supplies and swing a
± 10V analog signal. The JFET switches are designed for
applications where a dc to medium frequency analog signal
needs to be controlled .

• Analog signals are not loaded
• Constant "ON" resistance for signals up to ± 10V and
100 kHz
• Pin compatible with CMOS switches with the advantage
of blowout free handling
• Small signal analog signals to 50 MHz
• Break-before-make action
toFF < toN
• High open switch isolation at 1.0 MHz
-50 dB
• Low leakage in "OFF" state
< 1.0 nA
• TTL, DTL, RTL compatibility
• Single disable pin opens all switches in package on
LF11331, LF11332,LF11333
• LF11201 is pin compatible with DG201

~

....
~

C')
C')
C')

....

II.
...I

Test Circuit and Schematic Diagram

......
~
C')
C')

....
....
II.
...I
......
....
....
II.
...I
......
....
........
C')
C')
C')

r-------,

IA
ANALOG7
INPUT (YAI

Is
I

'ili>'.

LOGIC- .
INPUT y
IN

(LOGIC "0" < D.8VJ
(LOGIC "'" > 2.D¥)

L. _

A

I

cc +15Y
FIGURE 1. Typical Circuit for One Switch

C')
C')

-15Y

_

I

I
-l :!cc:.......J

-fV!!., ttb

Inl

I,I r:L':'

.J

__ I YAI
~

,

I

.~~

01 _

,~

TL/H/S667-2

~

lOGIC
IN

'--_--o-v..
FIGURE 2. Schematic DIagram (Normally Open)

8-28

TLlH/5667-12

r-

Absolute Maximum Ratings

Supply Voltage (Vee - VEE)
Reference Voltage
Logic Input Voltage

36V
VEES:VRS:Vee
VR-4.0VS:VINS:VR+6.0V

Analog Voltage

VEE s: VA s: Vee + 6V;
VAS:VEE+36V

Analog Current

IIAI<20mA

Co)
Co)

Power Dissipation (Note 2)
Molded DIP (N Suffix)
Cavity DIP (0 Suffix)
.operating Temperature Range
LF11201, 2 and LF11331, 2, 3
LF13201, 2 and LF13331, 2, 3

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 1)

SOOmW
900mW
- SsoC to + 12SoC
O'Cto + 70°C
-6SoC to + 1S0'C

Storage Temperature
Soldering Information
Nand 0 Package (10 sec.)
SO Package
Vapor Phase (60 sec.)
Infrared (1S sec.)

300'C
21 SoC
220'C

Electrical Characteristics (Note 3)
Symbol

Parameter

LF11331/2/3
LF11201/2

Conditions

LF1333112/3
LF1320112 Units

Min Typ Max Min Typ Max
RON

"ON" Resistance

VA=O,lo=1 rnA

RON Match "ON" Resistance Matching
Analog Range
VA
Leakage Current in "ON" Condition
IS(ON) +
IO(ON)
Source Current in "OFF" Condition
IS(OFF)

Switch "ON,"Vs=Vo= ±10V
Switch "OFF," Vs= + 10V,
Vo=-10V
Switch "OFF," Vs= + 10V,
Vo= -10V

TA=2SoC

1S0
200
TA=2SoC
S
±10 ±11
TA=2SoC
0.3
3
TA=2SoC
0.4
3
0.1
TA=2SoC
3

IO(OFF)

Drain Current in "OFF" Condition

VINH
VINL
IINH

Logical "1" Input Voltage
Logical "0" Input Voltage
Logical "1" Input Current

VIN=SV

TA=2SoC

IINL

Logical "0" Input Current

VIN=0.8

TA=2SoC

200
300
20

Delay Time "ON"
tON
Delay TIme "OFF"
tOFF
tON-toFF Break-Before·Make
CS(OFF) . Source-Capacitance_
Drain Capacitance
CO(OFF)
CS(ON) + Active Source and Drain Capacitance
COlON)
"OFF" Isolation
ISO(OFF)
Crosstalk
CT
SR
Analog Slew Rate
Disable Current
IDiS
-------~

Vs= ±10V, (Figure 3)
Vs= ± 10V, (Figure 3)
Vs= ±10V, (Figure 3)

TA=2SoC
TA=2S'C
TA=2SoC

SwjtcIL"QEE,"Vs=±~_O_V m~~A=2SoC

Switch "OFF," Vo = ± 10V
Switch "ON," Vs=Vo=OV

TA=2S'C
TA=2SoC

(Figure 4), (Note 4)
(Figure 4), (Note 4)
(NoteS)
(Figure 5), (Note 6)

TA=2S'C
TA=2S'C
TA=2S'C
TA=2S'C

lEE

Negative Supply Current

All Switches "OFF," Vs= ±10V TA=2S'C

IR

Reference Supply Current

All Switches "OFF," Vs = ± 1OV TA = 2SoC

Icc

Positive Supply Current

All Switches "OFF," Vs= ±10V TA=2S'C

---

V
nA
nA

S
100
S
100

nA
nA
nA
nA

0.4
3
0.1
3

10
30
10
30

2.0
0.8
10
2S
0.1
1

0.8
3.6 40
100
0.1
1

SOO
SOO
90
90
80
80
4.0 - - 4.0 - - - 3-:0
3~O
S.O
S.O
-so
-6S
SO
0.4 1.0
0.6 1.S
3.0
4.2
2.0
2.8
4.S
6.3

n
n
n

1S0 2S0
200 3S0
10 SO
±10 ±11
S
0.3 10
100
3
30

2.0
3.6

S.O
7.S
4.0
6.0
6.0
9.0

V
V
/loA
/loA
/loA
/loA
ns
ns
ns
pF

Co)
Co)
Co)

Co)
Co)

N

......
r-

'"71
....
Co)
Co)
Co)

N

......
r-

'"71
.....
.....
Co)
Co)
Co)

......
r'"71
.....
Co)
Co)
Co)
Co)

......
r'"71
.....
.....
N
.....
......
C)

r-

'"71
.....
Co)
N

C)
.....
......

r-

'"71
.....
.....

p r ~~~-N
pF

-so
dB
-6S
dB
SO
V//los
0.6 1.S rnA
0.9 2.3 rnA
4.3 7.0 rnA
6.0 10.S rnA
2.7 S.O rnA
3.8 7.S rnA
7.0 9.0 rnA
9.8 13.S rnA

Nota 1: Refer to RETSF11201X, RETSF11331X, RETSF11332X and RETSF11333X for military specificalions.
Nota 2: For operaling al high temperature Ihe molded DIP products musl be deraled based on a + 100'C maximum junction lemperalure and a Ihermal resislance
of + 150'C/W, devices in the cavity DIP are based on a +ISO'e maximum junction temperalure and are derated at ±100'C/W.
Nota 3: Unless otherwise specified, Vcc= +15V, VEE= -15V, VR=OV, and limits apply for -55'C<:TA<: + 125'C for Ihe LF11331/2/3 and Ihe LF11201/2,
-2S'C<:TA<:+8SOC forthe LF13331 12/3 and the LF13201 12.
Note 4: These paramelers are limiled by Ihe pin 10 pin capacitance of Ihe package.
Note 5: This Is the analog signal slew rate above which the signal is distorted as a result of finite internal slew rates.

Nota 6: All swltchas In the device are turned "OFF" by salurating a transistor at the disable node as shown in Rguro 5. The delay lime will be approximately equal
to the toN or toFF plus the delay Introduced by Ihe externallransistor.
Note 7: This graph Indicate. the analog current at which 1% of the analog current is lost when the drain is positive wilh respect to the source.
Note 8: 8JA (Typical) Thermal Resistance
Molded DIP (N)
8SOCIW
Cavity DIP (D)
100'C/W
Small Outline (M)
10S'C/W
8-29

'"71
....
....
....
......
r'"71
....
....
......
r'"71
....
....

......
r'"71
.....
Co)
N

C)

N

N

C)

N

C")

..~

~

C)

Connection Diagrams (Top View for SO and Dual-In-Line Packages) (All Switches Shown are For Logical "0")
LF11331/LF13331
IN.

04

LF11332/LF13332

53

03.

52

02

53

03

N
..-

..LL.
.....
.....

..C)

N

C")

..-

LL.

.....
.......
..-

~
..-

.......
.....

LL.

IN, . 01

C")
C")
C")
C")

51

'VA -VEE

IN,

IN •

01

02

LF11201lLF13201

LF11333/LF13333

..LL.
.....

04

IN.
TLfHf5667-13

TLfHf5667-1

53

03

52

02

04

IN J

NC

53

VA

52

~
C")
C")

..-

..-

LL.
.....

~

C")
C")
C")

..-

LL.

.....

.......
N

C")

C")
....-

IN,

01

81

VA

-VEE

LL.
.....
.......

..-

C")
C")
C")

..-

IN"

IN •

LF11202/LF13202
04

S4

-Vee

NC

53

01

-v..

02

IN •
TUHf5667 -15

TLfHf5667-14

Order Number LF13201D, LF11201D, LF11201D/883,
LF13202D,LF11202D,LF11202D/883,LF13331D,
. LF11331D, LF11331D/883, LF13332D, LF11332D,
LF11332D/883, LF13333D, LF11333D or LH11333D/883
See NS Package Number D16(:

03

LL.
.....
.......

......-

C")
C")

Order Number LF13201M, LF13202M, LF13331M,
LF13332M or LF13333M.
See NS Package Number M16A

LL.

.....

Order Number LF13201N, LF13202N, LF13331N,
LF13332N or LF13333N
See NS Package Number N16A

01

51

-VEE

VA

52

IN.
TLfHf6667-16

8-30

r-----------------------------------------------------------------------------~

Co)
Co)

Delay Time, Rise Time, SeHlIng Time, and Switching Transients
.,5V

,yo

-11V

r

....
....
....
'"
r
."
....
....
r
'"
."
........
."

Test Circuit and Typical Performance Curves
I

v1· +lv

v.I ••110V

VD

I
v..

..

I

J'N

Co)
Co)
Co)

~

\
\

r-

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V'N

.! I

I \V.

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r-

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r

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200nsldiv

200nsldiv

I
VD

~

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VAl. -lOY

v.

..

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v:

v~ ._15V

I

J••~v

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I
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~

r-

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r-r- -

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Co)
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r
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2DOnsJdi,

Additional Test Circuits
v,.
·v.

50.

DV

....
....
o....
'"
r
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....
o....
......
r
."
....
....
I\)

Co)
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l.GV
-'SV

....
....

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t

J'N

TLlH/5667 -3

+15V

'"
r
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Co)
Co)

200nsldiv

200nsldiv

Co)
Co)
Co)
I\)

so.

~T-------~----'

Vo

"------ --v~.,ov---------

~

I\)
......

IIV

r

."
....

v,.

Co)
I\)

o

I\)

V.

T'OPf

-IOV
,,

4.0

~

Z.O

o

10M

1 1.0

I

Iii

~

:i'
il
~

,....NEGATIVE UEEl-

1-4""",+-1-+---1

6.0

'.0
1--1'''''''-1--'*'=-=1::::::-1

iii Z.O

REFEjENCE I'A)

a L--J__-L__ __
-100
so
60
100
~

o

FREQUENCV (Hd

TEMPERATURE I C)

-I

'.0

...

.",

50

c

.!

iii

200

..-

2.0

Supply Current

-60

u..

Z.O

VA • VEl! +5.0Y
ALL SWITCHES OfF

400

C")
C")
C")

a
4.0

10

-40

!

tOFF

ANALOG CURRENT (mAl

-ZO

"i!i
~

l'
I--

100

Crosstalk and "OFF"
Isolation vs Frequency
Using Test Circuit
of Figure 5

&00

t--I'--to.

;: 200

'--

Vn"-15V
VA ,,0

&.0

ISO

t-.~ ~PUTPULSEI

JOO

!l!

Vee;; 15V

TEMPERATURE (OC)

600

!

]

o

so

+Vcc • '5V, -VEE· -fSV
TIME MEASURED FROM

I'--r-. I- 511% INPUT PULSETO 10%

400

40

10

Switching Times

u..

u..

J IZO

5GO

1/

V

-l-I-

80

~
C")

-I
.....
N

1&0

mA:'"

60

~

....-

I~:::: ~~~~
lAo "0.1
VA -0

VA (VOLTS)

N

C")

ZOO

120

I::)

Break·Before·Make Action

240

40

~
.....
..-

~

vV

y

120

2

1&0
140

C")
..-

1&0

-Vu '"-'5Y
I.., = 0.1 mA

160

"'"
J

nON" Resistance

"ON" Resistance

"ON" Resistance

5.0

10

15

20

2S

SUPPLY VOLTAGE ('V)

~--J

150

TEMPERATURE (" C)

C")

C")
....-

..-

5.0

C")
C")
C")

C 4.0
.!

~
.....

~

....C")
C")
....-

;

i

100.000
10,000

c

;:Iooo

J.O
z.O

=
~ too

1.0

10

oUJIIIULJ..IJIIILLWa..JJJJJILJ.JJWILJ.!IIWI

u..

a

-I

tOO

10

Uk

r.;--:-=-;;--:-=,--""",,,,,,,

10

g

I
-100

tOk lOOk 1.0M

U

~

w
u

~

~

6.0

:::::-

'.0

~+CDION:

"1'0'Vcc·'&V
" -

VEE ·-,IV

o
50

50

100

150

10

-6.0

'2.0

Z.O

6.0

--10

10

-6.0

-Z.O

VA (VOLTS)

-zo
iii

]

a

..

~

~

60

r--

40
ZO

j

I

"

I"'---- r-..

il
g

-12

1,\

-8.0

~

I-

C

Vcc"'15V
VEE· 15Y
VIN =+5.0V
VR "'OV

a
50

60

TEMPERATURE 1 ci

toO

150

10M
fRE~UENCY

100M

"-

-100

50

D

;.
il

"'

50

i

t-....

100

TEMPERATURE I"CI

IH"

'.0

.3

cc -4.0

a
-100

-1&

10

10
(NOTE 61

Vee ='15V
Vu"' .5Y

60

6.0

Logical "1" Input Bias
Current

va Temperature

100

Z.O

VA (VOLTS)

Maximum Accurste
Analog Current

Slew Rate of Analog
Voltage Above Which
Signal loading Occurs

~

T

!:stOFFI

Z.O

TEMPERATURE ( C)

FREQUENCY IHd

Switch CapaCitances

Switch Leakage Current

Switch Leakage Currents

Supply Current

~
.....

15D

8.0

1\

'\

'.0

........ I---

I-

2.0

a
-too

50

5D

100

150

TEMI'ERATURE rCI

TLlH/5667 -5

8·32

r-

."

Application Hints

::::

GENERAL INFORMATION
These devices are monolithic quad JFET analog switches
with "ON" resistances which are essentially independent of
analog voltage or analog current. The leakage currents are
typically less than 1 nA at 25°C in both the "OFF"and "ON"
switch states and introduce negligible errors in most appli·
cations. Each switch is controlled by minimum TTL logic
levels at its input and is designed to turn "OFF" faster than
it will turn "ON." This prevents two analog sources from
being transiently connected together during switching. The
switches were designed for applications which require
break.before·make action, no analog current loss, medium
speed switching times and moderate analog currents.

LEAKAGE CURRENTS
The drain and source leakage currents, in both the ON and
the OFF states of each switch, are typically less than 1 nA
at 25°C and less than 100 nA at 125°C. As shown in the
typical curves, these leakage currents are Dependent on
power supply voltages, analog voltage, analog current and
the source to drain voltage.
DELAY TIMES

...j::

(0)
(0)

."

w

~

...

j::
~

...

Because these analog switches are JFET rather than
CMOS, they do not require special handling.
LOGIC INPUTS
The logic input (IN), of each switch, is referenced to two
forward diode drops (1.4V at 25°C) from the reference sup.
ply (VR) which makes it compatible with DTL, RTL, and TTL
logic families. For normal operation, the logic "0" voltage
can range from 0.8V to -4.0V with respect to VR and the
logic "1" voltage can range from 2.OV to 6.0V with respect
to VR, provided VIN is not greater than (Vee- 2.5V). If the
input voltage is greater than (Vee - 2.5V), the input current
will increase. If the input voltage exceeds 6.0V or -4.0V
with respect to VR, a resistor in series with the input should
be used to limit the input current to less than 100,.,.A.
ANALOG VOLTAGE AND CURRENT

The delay time OFF (tOFF) is essentially independent of
both the analog voltage and temperature. The delay time
ON (tON) will decrease as either (Vee-VA) decreases or
the temperature decreases.

~

POWER SUPPLIES
The voltage between the positive supply (Vecl and either
the negative supply (VEE) or the reference supply (VR) can
be as much as 36V. To accommodate variations in input
logic reference voltages, VR can range from VEE to
(Vee- 4.5V). Care should be taken to ensure that the power
supply leads for the device never become reversed in polar·
ity or that the device is never inadvertantly installed back·
wards in a test socket. If one of these conditions occurs, the
supplies would zener an internal diode to an unlimited cur·
rent; and result in a destroyed device.
SWITCHING TRANSIENTS
When a switch is turned OFF or ON, transients will appear
at the load due to the internal transient voltage at the gate
of the switch JFET being coupled to the drain and source by
the junction capacitances of the JFET. The magnitude of
these transients is dependent on the load. A lower value RL
produces a lower transient voltage. A negative transient oc·
curs during the delay time ON, while a positive transient
occurs during the delay time OFF. These transients are rela·
tively small when compared to faster switch families.
DISABLE NODE

~
~

I\)

j::
~

j::
~
.....

~
~

r-

~
~
~

j::
~

N
Q

~

Analog Voltage
!;;
Each switch has a constant "ON" resistance (RON) for ana·
...
log voltages from (VEE+5V) to (Vcc-5V). For analog volt·
~
ages greater than (Vee-5Vj, the switch will remain ON in·
~
dependent of the logic input voltage. For analog voltages
j::
less than (VEE + 5V), the ON resistance of the switch will
."
increase. Although thEL§YoIi1cILYli!l~oLoRerate~ormally ---==-c=-=-::o
------------------------1-::::--when the analog voltage is out of the previously mentioned
This node can be used, as shown in Figure 5, to turn all the
I\)
range, the source voltage can go to either (VEE+36V) or
switches in the unit off independent of logic inputs. Normal·
~
(Vee+ 6V), whichever is more positive, and can go as nega·
Iy, the node floats freely at an internal diode drop (:::::0.7V)
j::
tive as VEE without destruction. The drain (D) voltage can
above VR· When the external transistor in Figure 5 is satu·
~
also go to either (VEE+36Vj or (Vee+6Vj, whichever is
rated, the node is pulled very close to VR and the unit is
(0)
more positive, and can go as negative as (Vee- 36Vj with·
disabled. Typically, the current from the node will be less
~
out destruction.
than 1 mAo This feature is not available on the LF11201 or
I\)
LF11202 series.
Analog Current
+Vcc
With the source (S) positive with respect to the drain (D), the
RON is constant for low analog currents, but will increase at
higher currents (>5 mAl when the FET enters the satura·
tion region. However, if the drain is positive with respect to
the source and a small analog current loss at high analog
currents (Note 6) is tolerable, a low RON can be maintained
for analog currents greater than 5 mA at 25°C.
v,.

r-----

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FIGURE 5. Disable Function

8·33

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Typical Applications
Sample and Hold with Reset

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Programmable Inverting Non-Inverting Operational Amplifier
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Programmable Gain Operational Amplifier

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GAIN SELECT

TL/H/5667 -7

8·34

r-

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(Continued)
Demultiplexer

,,,.

r-

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MultiplexerIMixer

r-

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a-Channel Analog Commutator with 6-Channel Select Logic

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0
ANALOG
INPUTS

(

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14.

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BCHANNEL
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SELECT RESET

.....
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r- LFi,ii1

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TUH/5667 -10

8-37

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N
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LL.
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(Continu~d)
DSB Modulator-Demodulator

CI
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LL.
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MODULATOR
,,'I

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8·38

TUH/5667-11

r-------------------------------------------------------------------------'r

...

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Co)

tflNational Semiconductor

CI1

o

.....
r
CD

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."

LF13508 8-ChannelAnalog Multiplexer
lF13509 4 Channei Differential Analog Multiplexer

Co)

CI1

oCQ

g

General Description
The LF1350B is an B-channel analog multiplexer which connects the output to 1 of the B analog inputs depending on
the state of a 3-bit binary address. An enable control allows
disconnecting the output, thereby providing a package select function.
This device is fabricated with National's BI-FET technology
which provides ion-implanted JFETs for the analog switch
on the same chip as the bipolar decode and switch drive
circuitry. This technology makes possible low constant
"ON" resistance with analog input voltage variations. This
device does not suffer from latch-up problems or static
charge blow-out problems associated with similar CMOS
parts. The digital inputs are designed to operate from both
TTL and CMOS levels while always providing a definite
break-before-make action.
The LF13509 is a 4-channel differential analog multiplexer.
A 2-bit binary address will connect a pair of independent

analog inputs to one of any 4 pairs of independent analog
outputs. The device has all the features of the LF1350B
series and should be used whenever differential analog inputs are required.

Features
•
•
•
•
•
•
•
•
•
•

JFET switches rather than CMOS
No static discharge blow-out problem
No SCR latch-up problems
Analog signal range 11V, -15V
Constant "ON" resistance for analog signals between
-11V and 11V
"ON" resistance 3BO n typ
Digital inputs compatible with TTL and CMOS
Output enable control
Break-before-make action: tOFF = 0.2 /Ls; toN = 2 /Ls typ
Lower leakage devices available

Functional Diagrams and Truth Tables
LF13508
EN

A2

AI

AD

A2

EN
-VEE

GND

Vee

sa

S7

S6

S5

S4

53

S2

SI

A1

AO

SWITCH
ON

-W·e - L - L I - L - - 5 1 L
L
L
H
H

H
H
H
H
H
H
H
L

L
H
H
L
L
H

H
H
X

H

H
L
H
L
H
L
H

X

X

52
S3
54
S5
56
57
S8
NONE

LF13509
EN

AI

AD

-VEE

GND

DB

S4B

S3B

S2B

SIB

S4A

SlA

SZA

SIA

DA
TL/H/5668-1

8·39

EN

A1

AO

L
H
H
H
H

X

X

L
L
H
H

L

H
L
H

SWITCH
PAIR ON
None
51
S2
S3
54

m

CI

In

Absolute Maximum Ratings

it
....I

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

CO)

.....
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CI

In
CO)
..-

U.

....I

Positive Supply - Negative Supply (Vee-VEE)
Positive Analog Input Voltage (Note 1)
Negative Analog Input Voltage (Note 1)

36V
Vee
,',-VEE

Positive Digital Input Voltage

Vee
-5V

Negative Digital Input Voltage
Analog Switch Current

Power Dissipation (Po at 25"C)
(Notes 2 & 7)
Molded DIP (N)
500mW
Po
Cavity DIP (D)
900mW
Po
Small Outline, (SO) Po
500mW
,Maximum Junction Temperature (TjMAXl
100"C
Operating Temperature Range
O"C~TA~ +70"C
Storage Temperature Range
- 65"C to + 150"C
Lead Temperature
D Package (Soldering, 10 seconds)
N Package (Soldering, 10 seconds)
..
Surface Mount Package (SO) "
Vapor Phase (60 seconds)
Inlrared (15 seconds)

Ilsl<10mA

300"C
260"C
215"C
220"C

,

Electrical Characteristics (Note 3)
Symbol

"

Parameter

LF13508
LF13509

Conditions
PoIIln

RON
~RON

"ON" Resistance
~RON

with Analog Voltage

VOUT=OV,ls=100,...A
, ,-10V~VOUT~ +10V,ls=100,...A

TA=25"C
TA=25"C

Swing

RON Match

RON Match Between Switches

VOUT=OV,ls=100,...A

TA=25"C

IS(OFF)

Source Current in "OFF"
Condition

Switch "OFF", Vs=11, Vo= -11,
(Note 4)

TA=25"C

Drain Current in "OFF"
Condition

Switch "OFF", VS='11, Vo= -11,
(Note 4)
,

TA=25"C

Leakage Current in "ON"
Condition

Switch ':ON" Vo = 11 V, (Note 4)

TA=25"C

IO(OFF)
IO(ON)

. Typ
380

650

500

850

0

0.01

1

%

20

150

Digital "1"lnput Voltage

VINL

Digital "0" Input Voltage

IINL

Digital "0" Input Current;

VIN=0.7V

TA=25"C

IINL(EN)

Digital "0" Enable Current

VEN=0:7V

TA=25"C

0

,0

5

nA

0.09

50

nA

20

nA

0.6

500

nA

20

nA

500

nA

1

VINH

Units
Max

2.0

V
0.7

V

1.5

30

,...A

40

,...A

1.2

,30

,...A

40

,...A

tTRAN

Switching Time 01 Multiplexer

(Figure 1), (Note 5)

TA=25"C

1.8

!oPEN
tON(EN)

Break-Belora-Make

(Figure 3)

TA=25"C

1.6

Enable Delay "ON"

(Figure 2)

TA=25"C

1.6

tOFF(EN)

Enable Delay "OFF"

(Figure 2)

TA=25"C

0.2

,...S
,...S
,...S
,...S

ISO(OFF)
CT

"OFF" Isolation

(Note 6)

TA=25"C

-66

dB

Crosstalk

LF13509 Series, (Note 6)

TA=25"C

-66

dB

CS(OFF)

Source Capacitance ("OFF")

Switch "OFF", VOUT=OV,
Vs=OV

TA=25"C

2.2

pF

CO(OFF)

Drain Capacitance ("OFF")

Switch "OFF", VOUT=OV,
Vs=OV

TA=25"C

11.4

pF

lec

Positive Supply Current

All Digital Inputs Grounded

TA=25"C

lEE

Negative Supply C!Jrrent

All Digital Inputs Grounded

8-40

TA=25"C

7.4

12

rnA

7.9

15

rnA

2.7

5

rnA

2.8

6

rnA

r-

"T1
......

Electrical Characteristics (Continued)

(0)

Note 1: If the analog input voltage exceeds this limit, the input current should be limited to less than 10 rnA.

U1

Note 2: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TjMAX. 9jA, and the ambient temperature,
T A. The maximum available power dissipation at any temperature is Po = (TjMAX- T A)!OjA or the 25°C POMAX, whichever is less.

.....
r-

oCI)

Note 4: Conditions applied to leakage tests insure worse case leakages. Exceeding 11Von the analog input may cause an "OFF" channel to turn "ON".

"T1
......
(0).

Note 5: Lots Bre sample tested to this parameter. The measurement conditions of Figure 1 insure worse case transition time.

o

Note 3: These specifications apply for Vs= ±15V and over the absolute maximum operating temperature range (TLSTA:S:TH) unless otherwise noted.

Note 6: "OFF" isolation is measured with all switches "OFF" and driving a source. Crosstalk is measured with a pair of switches "ON", driving channel A and

measuring channel B. RL ~200, CL ~7 pF,

Vs~3

Vrms,

f~500

kHz.

Note 7: Thermal Resistance 0jA (Junction to Ambient)

Molded DIP (N)
Cavity DIP (D)

150'C/W
100'C/W

Connection Diagrams
LF13508
Dual-In-Line (N or D) or Small Outline (SO) Pacl(ages
A1

A2

116

GND

15

Vee

55

13

14

51

56
11

12

Al

5a
10

r--

2
EN

4

3
51

5

6

1

53

52

54

GNU

J'6

9

l-

I

AD

LF13509
Dual-In-Line (N or OJ or Small Outline (SO) Packages
Vee

15

14

51B

52B

13

12

53B
11

54B
10

-

r--

P

2

1
AD

9

3

4

SIA

EN

TOP VIEW

5
52A

6
S3A

1
54A

P

TOPV1EW
TL/H/5668-2

Order Number LF13509D
See NS Package Number D16C
Order-Number-lF13509M-------See NS Package Number M16A
Order Number LF13509N
See NS Package Number N16A

Order Number LF13508D
See NS Package Number D16C
---- Order Number LF13508M-See NS Package Number M16A
Order Number LF13508N
See NS Package Number N16A

AC Test Circuits and Switching Time Waveforms
15V

Vec
EN

A2

Al

SI
S2-S1

lF1350a

S8

AO
LOGIC
INPUT

TL/H/5668-3

FIGURE 1. Transition Time

8-41

U1

<0

AC Test Circuit and Switching Time Waveforms (Continued)
16V

Vee
SI
LF1350B S2-S8

t-o--.,

VoUT

ENABLE
INPUT
-15V

FIGURE 2. Enable Times

15V

loV
SI

S2-S71-0-+,
lF13508

VoUT

S8

LOGIC

INPUT
DRIVE

INPUT
-15V

lV~

ovJ

'-TUH/566B-4

FIGURE 3. Break-Before-Make

Transition Times and Transients
VA-10V

VA=5V

VIN

VIN

>

>

~

~
GND

GND

Vo

Vo

,.S1DIV

I.S/DIV

TUH/566B-5

TLiH/566B-6

VA=-5V

VA=OV
GilD

GND

Vo
vlN

VIN

>

~

~
~

'IASJDIV

TUH/566B-7

TUH/566B-8

Test Circuit
15V

GilD

Vee

TL/H/5666-10

TL/H/566B-9

8·42

r-

"TI
.....
Co)

Typical Performance Characteristics

U'I

"ON" Resistance

"ON" Resistance
800

400

_1~.JOo.~

100

g

3&0

~o

z

o
.. 340

DO
300

200
100

Switch Leakage
Currents

!

ti
::!

.

~IOIOFFI

100

il

-G.l
IOIGr FI

-10

i
~

10

g;

~

I--

'TRA~

~~

-15 -10

10

-5

15

-&5

ANALOG VOLTAGE IVI

IA

~

!:O"

0.1

""'iSIOFFI

3

'A L

_~JC"'&~

65

9&

12&

"OFF" Isolation and
Crosstalk

-

~~ _ .

V

. -40
50ii
3 - BO

z

5 -1080
0

'OPEN

./

~

35

3D

/

~E~5~

-25

TEMPERATURE rCI

Enable Delay Times
(Figure 2)

VC~ -15~
I- VEE" -15V
-j-.- -

"

~

-IOIOFFI~

0.01

1&

Switching Times
(Figures 1 and 3)

1.5

1010NI

.
.."'"

IOIONI
Is OFFI

ANALOG VOLTAGE IVI

]

10

10
-5

Switch Leakage
Currents

100

-I

!

0
-1

ANALOG INPUT CURRENT ImAI

100NI
ISIOFFI

-2

Switch Leakage
Currents

1000

0.1

2.&

+~-

o
TEMPERATURE I'CI

3.&

~

i""

100

ANALOG INPUT VOLTAGE IVI

-1& -10

Co)

400

200

-55 -35 -15 5 25 45 65 85 105 125

VCC "nv
f-VEE" -1&V
TA ",25'C

...B

"TI
.....
U'I

..~ 3DO

-10 -8 -8 -4 -2 0 2 4 8 8 10

10

1
ki

g

,;'

.,., i-""

,....

.. 300
VCC "15V
VEE" -15V
lA"O
TA"25'C

500

~

500
400

TA - 25'C
VCC-15V
VEE - -15V

&00

VCC "15V
600 -VEE--15V

380

Q

co
......
r-

"ON" Resistance
100

-

~

- 90
'OFFEN-

0.5

-1 DO
-1 10

-55 -25

35

85

95

125

-55

-25

35

TEMPERATURE eCI

Bias Currents

\

VCC -15V
VEE --15V VLOGIC - OV

..... ~

.......

o

~~PLY

-25

35

6&

TEMPERATURE rCI

.."..

G:

-----

95

125

lOOk

1M

lDM

FREQUENCY IH.I

I

'''-!!
........ ...... ......... .......
lEN

-55

10k

125

Supply Currents
10

~

95

TEMPERATURE rCI

3

,\'

&5

-ISUPPLY

~

I

-

24
22
20
18
16
14
12
10

Switch Capacitances

COIONI

COIOFFI

CSIOFFI

1

2

I

o
-55 -2&·

3&

8&

TEMPERATURE rCI

o
8&

12&

-12-10-1-8-4 -2 0 2 4 & 8 10 12
ANALOG VOLTAGE IVI
TL/H/566B-ll

8-43

Application Hints
The LF11508 series is an 8-channel analog multiplexer
which allc;>ws the connection of a single load to 1 of 8 different analog inputs. These multiplexers incorporate JFETs in
a switch configuration. which insures a constant "ON" resistance over the analog voltage range of the device. Four TTL
compatible inputs are provided; a 3-bit binary decode to select a particular channel and an enable input used as a
package select. The switches operate with a break-beforemake action preventing the temporary connection of 2 analog inputs during switching. Because these multiplexers are
fabricated with the BI-FET process rather than CMOS, they
do not require special' handling.
The LF11509 series is a 4-channel differential multiplexer
which allows two loads to be connected to 1 of 4 different
pairs of analog inputs. The LF11509 series also has all the
features of the LF11508.

LEAKAGE CURRENTS
Leakage currents will remain within the specified value as
long as the drain and source remain within the specified
analog voltage range. As the switch terminals exceed the
positive analog voltage range "ON" and "OFF" leakage
currents increase. The "ON" leakage increases due to an
internal clamp required by the switch structure. The "OFF"
leakage increases because the gate to source reverse bias
has been decreased to the point where the switch becomes
active. Leakage currents vary slightly with analog voltage
and will approximately double for every 10·C rise in temperature.
SWITCHING TIMES AND TRANSIENTS
These multiplexers operate with a break-before-make
switch action. The turn off time is much faster than the turn
on time to guarantee this feature over the full range of analog input voltage and temperature. Switching transients are
introduced when a switch is turned "OFF". The amplitude of
these transients may be reduced by increasing the load capacitance or decreasing the load resistance. The actual
charge transfer in the transient may be reduced by operating on reduced power supplies. Examples of switchirig times
and transients are shown in the typical characteristic
curves. The enable function switching times are specified
separately from switch-ta-sWitch transition times and may
be thought of as package-to-package transition times.

ANALOG VOLTAGE AND CURRENT
The "ON" resistance, RON, of the analog switches is constant over a wide input range from positive (Vee) supply to
negative (-VEE) supply.
The analog input should not exceed either positive or negative supply without limiting the current to less than 10 mA;
otherwise the rnultiplexer may get damaged. For proper operation, however, the positive analog voltage should be kept
equal to or less than Vee - 4V as this will increase the
switch leakage in both "ON" and "OFF" state and it may
also cause a false turn "ON" of a normally "OFF" switch.
This limit applies over the full temperature range.
The maximum allowable switch "ON" voltage (the drop
across the switch in the "ON" condition) is ± 0.4V over temperature. If this number is to exceed the input current should
be limited to 10 mAo
The "ON" resistance of the multiplexing switches varies
slightly with analog current because they are JFETs running
at OV gate to source. The JFET characteristics shown in
Figure 4 indicates how RON tends to vary with current. A
lower RON is possible when the source voltage is negative
with respect to the drain voltage because the JFET becomes enhanced. Caution should be used when operating
in this mode as this may forward-bias an internal transistor
and cause high currents to flow in the switches. Thus, the
drain voltage should never be greater than 0.4V positive
with respect to the source voltage without limiting the drain
current to less than 10 mAo

LOGIC INPUTS AND ENABLE INPUT
Switch selection in the LF11508 series is accomplished by
using a 3-bit binary decode while the LF11509 series uses a
2-bit decode. These binary logic inputs are compatible with
both TTL and CMOS logic voltage levels. The maximum
positive voltage applied to these inputs may exceed Vee but
should not exceed -VEE+36V. The maximum negative
vciltage should not be less than 4V below ground as this will
cause an internal device to zener and all the switches will
turn "ON".
As shown in the schematic diagram, the logic low bias current will flow until the PNP input is raised above the 3 diode
reference (:::: 2.1 V). Above this voltage the input device becomes reverse biased and the input current drops to the
leakage of the reverse biased junction «0.1 p.A).

s

1.6

:i..

..

co

1.2

3.6

~

1.B

:c

.!

D

i-'"
-2

VSD

D

.!!'

. O.B
0.4

'I.~

'"

,

/

-1.8

II

-16

-1

-2

vsolVI

-1
VSD (VI

FIGURE 4. JFET Characteristics

8-44

TlIH/5668-12

,-----------------------------------------------------------------------------, r
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Typical Applications
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DATA ACQUISITION SYSTEM
A SIMPLIFIED SYSTEM DISCUSSION
Analog multiplexers (MUX) are usually used for multi·chan·
nel Data Acquisition Units (DAU). Figure 5 shows a system
in INhich 8 different analog inputs are sampled and convert·
ed into digital words for further processing. The sample and
hold circuit is optional, depending on input speed require·
ments and on AID converter speed.
Parameters characterizing the system are:
System Channels: The number of multiplexer channels.
Accuracy: The conversion accuracy of each individual sam·
pie with the system operating at the throughput rate.

A. ACCURACY CONSIDERATIONS
1. Multiplexer's Influence on System Accuracy (Figure 6).
a. The error, (E), caused by the finite "ON" resist·
ance, RON, of the multiplexing switches is given
by:
100

+ Rs + boRON)

BITS

ts(ON)
TO 1/2LSB

0.2
0.05
0.01
O.OOOB

8
10
12
16

6.2t
7.61
9t
11.8t

."
-0.

Co)

U'I
Q

CD

+ Rs) II RIN

ts(OFF): is the time it takes to discharge Cs within
a tolerable error. The "OFF" settling time should
be taken into account for bipolar inputs where its
effects will appear as a worse case of doubling
of the ts(ON).
2. Sample and Hold Influence on System Accuracy

For a discussion on system structure, addressing mode and
processor interfacing, see application note AN-159.

1 .+ RIN/(RON

ERROR %

1 = Cs (RON

Speed or Throughput Rate: Number of samples/secondl
channel the system can handle.

E(%) =

c»
.....
r

TABLE I.

The sample and hold, if used, also introduces errors into
the system accuracy due to:
• Offset voltage of sample and hold
• Droop rate in the Hold mode
• TA: Aperture time or time delay between the time of a
digital Hold command and the actual Hold occurance
• Taq: Acquisition time or time it takes to acquire an
analog input and settle within a predetermined error
band
• Hold step: Error created during the Sample to Hold
mode caused by an undesirable charge injected into
the Hold capacitor Ch.
For more details on sample and hold errors, see the
LF19B/LF29B/LF39B data sheet.
3. AID Converter Influence on System Accuracy

where:

RIN = following stage input impedance
boRON = "ON" resistance modulation which is
negligible for JFET switches like the LF11508
Example: Let RON = 450 0, boRON = 0, Rs = 0, TA
= 25°C and allowable E = 0.01 % which is equivalent
to 112 LSB in a 12-bit system:

The "accuracy" of the AID converter is the best possible
system accuracy. In most data acquisition systems, the
~~--~~-- --~-~,AlD-converterJs_thamosLexpensive-single~comp-onem, ____
, so its error will often dominate system error. Care should
be taken that MUX, S/H and input source errors do not
Note that if temperature effects are included, some
exceed system error requirements when added to AID
gain (or full scale) drift will occur; but effects on linearity
errors. For instance, if an B·bit accuracy system is ,desired
are small.
and an 8-bit AID converter is used, the accuracy of the
b. Multiplexer settling time (ts):
MUX and S/H should be far better than B bits.
ts(ON): is the time required for the MUX output to
For details on AID converter specifications, see AN-156.
settle within a predetermined accuracy, as
4.5 MO

shown in Table I.

'

Cs (Figure 6): MUX output capacitance + fol·
lowing stage input capacitance + any stray ca·
pacitance at this node.

PRECONDITIONED [
ANALOG INPUTS

j.BITSWORO

CONVERSION COMPLETE

TUH/5668-13

FIGURE 5. Random-Addressed, Multiplexed DAU

FIGURE 6. a-Channel MUX
8-45

~ __ ~.

Typical Applications

(Continued)
where TA is the aperture time of the S/H. This represents an input slew rate improvement by a factor: Tel
TA. Here again, the slew rate error is not affected by
the acquisition time of the Sample and Hold since conversion will start aiter the S/H has settled. An important thing to notice is that the sample and hold errors
will add to the total system error budget,· therefore, the
inequality of the AV'WAt expression should become
more stringent

B. SPEED CONSIDERATIONS
In the system of Figure 5 with the S/H omitted, if n·bit accu·
racy is desired, the change of the analog input voltage
should be less than ± 1/2 LSB over the AID conversion
time Te. In other words, the analog input slew rate, (rate of
change of input voltage), will cause a slew-induced error
and its magnitude, with respect to the total system error, will
depend on the particular application.

Example: T e = 40 p.s, T A = 0.5 p.s, n = 8: TcITA = 80

<±1/2LSB=~
AVINI
At max
Te
2" X Te

So the use of a S/H allows a speed improvement by
nearly two orders of magnitude.
The maximum throughput rate can be calculated by:

where VFS is the full scale voltage of the AID. Note that
slew induced errors are not affected by the MUX switch time
since we can let the unit settle before starting conversion.

Th. R

Example: Let Te = 40 p.s (MM4357), VFS = 10V and n
= 8.
.

Notice that TMUX does not affect the AVIN/At expression
nor the throughput rate of the system since it may be
switched and settled while the Sample and Hold is In the
Hold mode. This is true, provided that: TMUX < TA + Te.

AVIN I
< 1mV
At max
p.s

C. SYSTEM EXAMPLE (FIgure 7)

which is a very small number. A 10 Vp-p sine wave of a
frequency greater than 32 Hz will have higher slew rate
than this. The maximum throughput rate of the above 8channel system would be calculated using both the AID
conversion time and the sum of MUX switch "ON" time
and settling time, i.e.:
Th. R I

max

The LF398 S/H with a 1000 pF hold capacitor, has an acquisition time of 4 p.s to 0.1 % (1/4 LSB error for 8 bits) and
an aperture time of less than 200 p.s. On the other hand,
aiter the hold command, the output will settle to ± 0.05 mV
in 1 p.s. This, together with the acquisition time, introduces
approximately a ± 1/4 LSB error. Allowing another 1/4 LSB
error for hold step and gain non-linearity, the maximum slew
error (AVIN/At) should not exceed 1/4 LSB or:

= 8(T 1 T xl = 3k samples/secl
e + MU
channel

TMUX = TON

AVIN
At

1

1
1
X256 TA

-- ~ - X -

+ TS(ON)

4

~5mVlp.s

(which is the maximum slew rate of a 5 V peak sine wave.
Also notice that, due to the above input slew restrictions,
the analog delay caused by the finite BW of the S/H and the
digital delay caused by the response time of the controller
will be negligible. The maximum throughput rate of the system is:

Also notice that Nyquist sampling criteria would allow
each channel to have a signal bandwidth of 1.5 kHz max,
while the slew limit dictates a maximum frequency of 32
Hz. If the input Signal has a peak-to-peak voltage less
than 10V, the allowable maximum input frequency can be
calculated by:
f

Imax = 8(TA + Taq
1
.
+ Te)

Th. R Imax = 8(5

_ (Slew Rate)max
MAX 'lTVp-p

+ ~0)10

6 = 2800 samples/sec/ch.

If the system speed requirements are relaxed, but the AID
converter is still too slow, then an inexpensive S/H can be
built by using just a capacitor and a low cost FET input op
amp as shown in Figure 8.

On the other hand, if the input voltage is not band-limited a
low pass filter with an attenuation of 30 dB or better at 1.5
kHz, should be connected in front of the MUX.
1. Improving System Speed with a Sample and Hold
The system speed can be improved by using the
S/H shown in Figure 5. This allows a much greater
rate of change of VIN.

8-46

Typical Applications (Continued)
15V -15V
lBV
BV

r -,;; - - -:,;; - ,
I
I

I
I
I

">_-':I'-V'::'N::.o+~IZ~L_,.,..._.."..A_O_CO..;.D~DP_C....;;~~~~ ~
SC

I

ClK

•

11

I
15V

EN

AD

16

15

AI

AZ

Uk

} ..liT WORD

EOC

•
EOC: End of Conversion

I
I

SC: Start Conversion
-IZV

I _______
Ik
,:,1
L
.J

....._ _ _...o()~~~~!N.UT
~~~~~~~~~~

BVo-.........

':'

"0"--,
SIH--.J
SC

Dec
ClK EN
AO

H

r1

r,

r,

IJ

IJ

IJ

p~CP~

r1
r'

AI
AZ

II

~------IL--I
J

r,
~,

r

l

u

I

IJ

......

rL.

n

n

,r

r,

rL

r'

L-_

n

L,
r-

fl

TLlH/5888-14

FIGURE 7b. Timing Diagram
8-47

•

Typical Applications (Continued)
An alternate way to increase the system channel is shown
in Figure 10, where the enable pins are used to disable one
MUX while the other is sampling. With this method, many 8channel multiplexers can be connected, but ,the parasitic
capacitance at the common output node will keep increasing and will eventually degrade the settling time, !s(ON)'
Also, the MUX speed will now affect the system throughput.
If, for instance, this method was used instead of second
level multiplexing, the system of Figure 9 will lose half of its
speed. If, however, speed is not the prime system requirement, the approach of Figure 10 is more cost effective.

D. DOUBLING THE SYSTEM CHANNEL CAPABILITY
This is done in two different ways. First, we can use second
level multiplexing with speed benefits, as shown in Figure 9.
A fast 2-channel multiplexer, made by the dual analog
switch AM182, accepts the outputs of each 8-chann!)1 MUX,
LF13508, and then feeds them sequentially into an' 8-bit
successive approximation AID converter. With this technique, the throughput rate of the system can again be made
independent of the LFi3508 speed. Looking at the timing
diagram, when the AID, converter converts the analog value
of an upper multiplexer channel, we switch channels in the
lower multiplexer for the next conversion. This can be done
provided that:

E. DIFFERENTIAL INPUT SYSTEMS
Systems operating in industrial environments may require
an instrumentation amplifier'to separate the desired analog
signal from any common-mode signal' present. The
LFl1509 was designed to provide 4 pairs of differential input -Signals to the input of an instrumentation amplifier for
further process.

TMUX ,;: Tc + 1 CP
The LF356 connected as unity gain buffers are used' because of the low input impedance of the AID; they are connected between multiplexers for speed optimization. With a
maximum clock freqUency of 4.5 MHz:
106
Th. R = 16 X 2 = 31.25ksamples/sec/channel
and
aVIN

At

Imax < 256
10' l'
X 2jAoS, =

"

19.5 mV / jAos for 10VFS

15V

-15V

- - -+ TO A/O

SAMPLE

'
"
HOlD=U,

EN

AD

AI

A2

I

CHANIllEl SelECT
TLiHI566B-15
o The acquisijion time, TA, of the Sample and Hold

d~pends upon: R~N' loss of sWijches, ,ZOUT of switches

01055"'1.5 mA, ZOUT=40 kfl

' ,

o VIN=10V, Ch;'" 1000 pF, TA=20 fts to 0.1%,

o Error created by charge injection during Hold mode: AVE'" \0 pF (14.5V-VIN)/Ch

FIGURE 8, Inexpensive Sample and Hold

8-48

...

~----------------------------------------------------------------------'r

"TI

Typical Applications (Continued)

W

g:

r------~-----------l

15V

I
I
I
I
I
I
I
I
I
I
IL _ _ _ _

-lSV

5V

SZ

,5V

-15V

...

W
CJ1

o

CD

_ _ _ _ ~~~~

~---

------,

r-------I
I
I
I
I
I
I
I
I
I
IL

CD

r
'"
"TI

I
I
I
I
I
I
I
I
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I

to

DM2502

I

LSBo..,~=~
MSB

I
I
I
I

I5V

o,:.;:..:;.;.=::.;.----¢

I5V

'V

3.9M

0.01

~F

":'"

'::"

-15V_ _ _
______
__
_________
15V
-15V
8.BIT S.A. AID

I
I
I
I

~

FIGURE 9a. A Fast 16-Channel DAU with Second Level Multiplexing

eLK

.JUWUlJUUUU1JUUU1.nfUWUlJ1JU1ruUUUlJl

SI _ _---'
S2

I

I

I

I

0

I

I
I

I
AI

AU

1'-

I

i

I

DC"q

,.

U

~gep--J

"

U

2.

U

2'

U

11

U

3'

U

..

U

I

4.

L
TL/H/5668-16

FIGURE 9b. Timing Diagram

8-49

Typical Applications (Continued)
1SV

-11V

",,-,1>-<,,,0 TO SiH OR 11/0

1.

15":"

MMI4C11I

IIV -15V

TLlH/5668-17

FIGURE 10. A 1S-Channel Multiplexer with SequenUaI MulUplexlng

8-50

~--------------------------------------------~5

Schematic Diagrams

LF13508

Co)

g:
co
.....
r-

-n
....
i§
Co)

------~~----~-.----_+~r_--------~~

8·61

Schematic Diagrams (Continued)

LF13509

--------~---r~----~~

8·52

Section 9
Surface Mount

Section 9 Contents
Packing Considerations (Methods, Materials and Recycling) .............................
Board Mount of Surface Mount Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Soldering Profiles-Surface Mount .....................................
AN-450 Small Outline (SO) Package Surface Mounting Methods-Parameters and Their Effect
on Product Reliability .............................................................
Land Pattern Recommendations .....................................................

9-2

9-3
9-19
9-23
9-24
9-35

tflNational Semiconductor

Packing Considerations

(Methods, Materials and Recycling)

Transport Media
All NSC devices are prepared, inspected and packed to insure proper physical support and to protect during transport
and shipment. All assembled devices are packed in one or
more of the following container forms-immediate containers,- intermediate containers and outer/shipping containers.
An example of each container form is illustrated below.

INTERMEDIATE CONTAINER
Tape Ik Re.1
BQX

IMMEDIATE CONTAINER
Reel

TLlP/11809-4

\ ----It--~----'\
~_
~_
\ J

TL/P/11809-1

Ie Dey ice

Label

'tk<°

\ Rail/Tub.

TL/P/11809-5

Rail/Tube

TLlP/11809-2

Trays
TL/P/11809-8

OUTER/SHIPPING CONTAINER
TLlP/11809-3

&I
TLlP/11809-7

9-3

-

Methods of immediate carrier packing include insertion of
components into molded trays and rails/tubes, mounting of
components onto tape and reel or placement in corrugated
cartons. The immediate containers are then packed into intermediate containers (bags or boxes) which specify quantities of trays, rails/tubes or tape and reels. Outer/shipping
containers are then filled or partially filled with intermediate
containers to meet order quantity requirements and to further insure protection from transportation hazards. Additional dunnage filler material is required to fill voids within the
intermediate and outer/shipping containers.

-

Levels of Product Packing
IMMEDIATE CONTAINER
The first level of product packing is the immediate container.
The immediate container type varies with the product or
package being packed. In addition, the materials used in the
immediate container depend on the fragility, size and profile
of the product. The four types of immediate containers used
by NSC are rails/tubes, trays, tape and reel, and corrugated
and chipboard containers.
Rails/tubes are generally made of acrylic or polyvinyl chloride (PVC) plastics. The electrical characteristics of the material are altered by either intrinsically adding carbon fillers,
and/or topically coating it with antistatic solution. Refer to
Table I for rail/tube material and recyclabillty information.

General Packing Requirements
NSC packing methods and materials are designed based on
the following considerations:
-

Ease of handling-it should be easy to assemble, load
and unload products in and from it; and
Impacts to the environment-it shall be reusable and
recyclable.

Optimum protection to the products-it must provide adequate protection from handling (electrostatic discharge) and transportation hazards;

TABLE I. Plastic Rail/Tube and Stopper Requirements
Rail

Package
Type

Material

Code/Symbol
(Note 1)

DIP's
Plastic
Ceramic
Sidebraze

Polyvinylchloride
Polyvinylchloride
Polyvinylchloride

OS/PVC
OS/PVC
OS/PVC

Pin
Pin
Pin

Polyamide
Polyamide
Polyamide

07/PA
07/PA
07/PA

Yes
Yes
Yes

PLCC

Polyvinylchloride

OS/PVC

Plug

Rubber

07/SBR

Yes

TapePak

Polyvinylchloride

OS/PVC

Plug

Rubber

07/SBR

Yes

Flatpack

Polyvinylchloride

OS/PVC

Pin

Polymide

07/PA

Yes

Cerpack

Polyvinylchloride

OS/PVC

Pin

Polymide

07/PA

Yes

TO-220/202

Polyvinylchloride

OS/PVC

Pin

Polymide

07/PA

Yes

TO-5/B
(in Carrier)

Polyvinylchloride

OS/PVC

Pin

Polymide

07/PA

Yes

SOP

Polyvinylchloride

OS/PVC

Plug

Rubber

07/SBR

Yes

LCC
1BL-44L

Polyvinylchloride

OS/PVC

Plug

Rubber

07/SBR

Yes

Type

Stopper
Material

Note 1: ISO 1043-1 Inlernallonal Standards-Plaslic Symbols.
SAE J1344 Marking of Plaslic Parts.
ASTM D 1972-91 Siandard Practice for Generic Marking of Plaslic Products.
DIN 6120, German Recycling Syslems, RESY for paperbased and VGK for plastic packing malerials.

9-4

Code/Symbol
(Note 1)

Recyclability

Molded injection and vacuum formed trays can be either
conductive or static dissipative. Molded injection trays are
classified as either low-temperature or high-temperature

depending on the material type. Vacuum formed trays are
only used in ambient room temperature conditions. Refer to
Table II for tray material and recyclability information.

TABLE II. Tray Requirements
Tray

Package
Type

Class

PQFP(AII)

Material

Recyclability
(Note 1)

CodelSymbol
(Note 1)

Binding Type

High Temperature

Polyethersulfone

Yes

Low Temperature

Acrylonitrilebutadiene
Styrene

Yes

PGA, LOCC
CERQUADs
andLCC
(48 leads-125 leads)

Low Temperature
Only

ABS/PVC

Yes

07/ABS-PVC

Wire Tie

PPGA

Low Temperature
Only

Polyarylsulfone

Yes

07/PAS

Wire Tie

Tape and reel is a multi-part immediate container system.
The reel is made of either polystyrene (PS) material coated
with antistatic solution or chipboard. The embossed or cavity tape is made of either PVC or PS material. The cover tape

07lPES
07lABS

Wire Tie or
Nylon Strap
Wire Tie or
Nylon Strap

is made of polyester (PET) and polyethylene (PE) materials.
Refer to Table III for tape and reel material and recyclability
Information.

TABLE 111_ Tape and Reel Requirements
Cover Type

Reel
Package
Type

Codel
Material

Symbol
(Note 1)

Codel
Symbol
(Note 1)

Material

Carrier Tape

Codel
Material

Symbol
(Note 1)

Paper Tape

Recyclability
(Note 1)

TO-92

Chipboard

Resy

N/A

SOP-23

Polystyrene
Chi!l!loard

06/PS
Resy

Polystyrene

06/PS

PVC

03/PVC

Yes

SOP,SSOP
and PLCC

Polystyrene
Polyethylene

06/PS

Polyester

07/PET-PE

PVC

03/PVC

Yes

Note 1: 150 1043-1 International Standards-Plastic Symbols.
SAE J1344 Marking of Plastic Parts.
ASTM D 1972-91 Standard Practice for Generic Marking of Plastic Products.
DIN 6120, German ReCYCling Systems, RESY for paperbased and VGK for plastiC packing materials.

9-5

Yes

!o
~

Q)

Corrugated containers are generally constructed with fibreboard facings·and a fluted ·corrugated.medium in between
the facings. Chipboard containers are comprised of just one

fibreboard facing. Facings and corrugated medium are kraft
(brown) fibreboard, and generally single wall· construction.
Refer to Table IV for material and recyclability information.

"CI

·iii
c

TABLE IV. Fibreboard Container Requirements

o
o

0)

c

~

i

Pack Method
Package
Type

Materllli
Corrugate~

·.TO-92/18,
TO-46/5,
TO-39,220,
TO-202/126,
TO-237

Container Type
Immediate (IMM)
Intermediate (I NT)
Outer or Shipping (SHP)

Codel
Symbol
(Note 1)
Resy

IMM

Reeyelabllity

Yes

(E070BOX)

All Products

Corrguated

Resy

INTandSHIP

Yes

All Products

3-PlyPaper
(Padpak)

Resy

Dunnage

Yes

Plastic
Bubble Sheet

04/PE

Dunnage

Yes

"

All Products
PLCC

Note 1: ISO 1043-1 International Standards-Plastlc Symbols.
SA!; J13,1;'! Marklng 01 Plastic Parts. .
.
ASTM 01972-91 Standard Practice for Generic Marklng of Plastic Products.
DIN 6120. German Recycling Systems. RESY for paperbased and VGK for plastic packing materials:

INTERMEDIATE CONTAINERS
The second level of product packing is the int~rmediate
container. Three types on intermediate containers are used
by NSC. They are plastic bags, moisture barrier bags and
corrugated cartons/boxes.
.
Two types of plastic bags ,are used and usage of each type
depends on the product or package being packed ..Conductive bags are made of polyvinylchloride plastic material. The
electrical characteristics of the bag are altered by adding

carbon fillers which make the bag black (opaque) in color.
Conductive bags are used on products or packages that are
packed in static dissipative (SO) rails/tubes. Static shielding
bags are made of two layers of SO polyethylene sheets with
a metallized film separating the sheets. Refer to Table V for
material and recyclability information.
Moisture barrier bags are used on rail/tube, tape and reel,
and tray packs 'for moisture sensitive products. NSC uses
National Metallizing's Stratoguard™ 4.6.

"tI

TABLE V. Conductive and Static
Shielding Bag Requirements
Package
Type
All Prod. in
Rails

Container
Type

Material
Type

Conductive Polyethlene
Bag

TO·92/B1,
Static
TO·46/5,
Shielding
TO·39/220, Bag
TO·202/126,
TO·3/237

Polyethlene
Alum. Laminant

Corrugated cartons/boxes are generally constructed with fi·
breboard facings and a fluted corrugated medium in between the facings. Facings and corrugated medium are kraft
(brown) fibreboards, and are generally of single wall construction. Carton style varies with the product that it will con·
tain. For example, packing of a rail/tube will require the use
of a carton with a roll end from lock (REFL) deSign. Other
products generally use the regular slotted container (RSC)
box. Refer to Table IV for material and recyclability informa·
tion.

Mat'l
and
Mat'l
Symbol Recyclability
(Note 1)
04/PE

N/A

Yes
No

. OUTER/SHIPPING CONTAINERS
The third level of product packing is the outer/shipping container. The outer/shipping containers use by NSC are similar to the corrugated containers used for immediate and intermediate packaging, but are heavier in facing thickness.
The style generally used is the regular slotted container
(RSC) box and can be single, double or triple wall, depend·
ing on the total weight of products being transported or
shipped. Refer to Table IV for material and recyclability information.

TABLE VI. Drypack Bag Requirements
Package
Type
TapePak
PLCC
(52·B4L)
PQFP

Container
Type
Drypack
Bag

Material
Type
Stratoguard™ 4.6

Mat'l
and
Mat'l
Symbol Recyclablllty
(Note 1)
N/A

OTHER PACKING MATERIALS

No

Additional dunnage and void filler materials are required to
fill voids within the intermediate and outer/shipping contain·
ers. Two types of dunnage/filler material are Padpack and
bubble pack. Padpak is a machine processed, 3-ply kraft
paper sheet dunnage system. Refer to Table IV for material
and recyclability information.

Note 1: ISO 1043-1 International Standard&-PlaSilc Symbols.
SAE J1344 Marking of Plastic Parts.
ASTM 01972-91 Standard Practice for Generic Marking of Plastic
Products.
DIN 6120, German Recycling Systems, RESY for paperbased and
VGK for plastic packing materials

Bubble pack is made of polyethylene plastic sheets with air
pockets trapped in between the plastiC layers and can be
either static dissipative or conductive. Refer to Table IV for
material and recyclability information.

-~~-----------------

9·7

D)

n

~

3'

CC

oo

=
c:

UI

...
CD

!.

o·
=
UI

o

15

r-----------------------------------------~--~--~--------------------------~

i
Q

C

i

Immediate Container Pack Methods
The following table identifies the primary immediate container pack method for all hermetic and plastic packages offered by
National Semiconductor. A secondary immediate container pack method is identified where applicable.

Immediate Packing Method for Ceramic Packages
Package
Type
(Code)
Ceramic Sidebrazed
Dual-In-Line
Package (SB)

Ceramic Leadless
Chip Carrier (LCC)

Package
Marketing
Drawing
D08C

Primary
Immediate
Container

Secondary
Immediate
Container

Method

Quantity

Rail/Tube

35

D14D

Rail/Tube

25

D16C

Rail/Tube

20

D18A

Rail/Tube

20

D20A

Rail/Tube

18

D20B

Rail/Tube'

Hi

D24C

Rail/Tube

15

D24H

Rail/Tube

15

D24K

Rail/Tube

15

D28D

Rail/Tube

13

D28G

Rail/Tube

13

D28H

Rail/Tube

13

D40C

Rail/Tube

9

D40J

Rail/Tube

9

D48A

Rail/Tube

7

D52A

Rail/Tube

7

E20A

Rail/Tube

50

EA20B

Rail/Tube

50

E24B

Tray

25

E28A

Tray

28

EA028C

Tray

100

E32A

Rail/Tube

35

E32B

Rail/Tube

35

E32C

Rail/Tube

35

E40A

Rail/Tube

35

E44A

Rail/Tube

25

E48A

Tray

25

E68B

Tray

48

E68C

Tray

48

E84A

Tray

42

E84B

Tray

42

9-8

Method

Quantity

Immediate Packing Method for Ceramic Packages (Continued)
Primary
Immediate
Container

Secondary
Immediate
Container

Package
Type
(Code)

Package
Marketing
Drawing

Method

Quantity

Ceramic Quad
J-Bend (CQJB)

El28A

Tray

96

EL44A

Tray

80

EL44B

Tray

80

EL44C

Tray

80

EL52A

Tray

50

EL68A

Tray

44

EL68B

Tray

44

EL68C

Tray

44

EL84A

Tray

42

EL28B

Rail

15

Ceramic Quad
Flatpack
(CQFP)

EL64A

Box

36

EL100A

Tray

12

E1116A

Tray

12

EL132B

Tray

20

E1132C

Tray

20

E1132D

Tray

20

E1164A

Tray

12

E1172B

Tray

12

Quantity

Tray

12

F10B

Carrier/Rail

19

Carrier/Box

200

F14C

Carrier/Rail

19

Carrier/Box

200

1=16B

Carrier/RaiL

19

Carrier/Box

200

E1172C
Ceramic
Flatpack

Method

9-9

--

.

o

~----------------------------------------------------~-------------------------------

o

Immediate Packing Method for Ceramic Packages (Continued)

C

~CD

~o

(.)
Q

C

:iii!

~
a.

Package
Type
(Code)

Ceramic pual-InLine Package
(Cerdip)

Ceramic Small
Outline Package,
Wide

Package
Marketing
Drawing

Primary
Immediate
Container

Secondary
Immediate
Container

Method

Quantity

J08A

Rail/Tube

40

J14A

Rail/Tube

25

J16A

Rail/Tube

25

J18A

Rail/Tube

20

J20A

Rail/Tube

20

J22A

Rail/Tube

17

J24A

Rail/Tube

15

J24AQ

Rail/Tube

15

J24B-Q

Rail/Tube

15

J24CQ

Rail/Tube

15

J24E

Rail/Tube

16

J24F

Rail/Tube

15

J28A

Rail/Tube

12

J28AQ

Rail/Tube

12

J28B

Rail/Tube

12

J28BQ

Rail/Tube

12

J28CQ

Rail/Tube

13

J32B

Rail/Tube

11

J32AQ

Rail/Tube

11

J40A

Rail/Tube

9

J40AQ

Rail/Tube

9

J40BQ

Rail/Tube

9

MC16A

Rail/Tube

45

MC20A

Rail/Tube

36

MC20B

Rail/Tube

36

MC24A

Rail/Tube

30

MC28A

Rail/Tube

26

MC28B

Rail/Tube

26

9-10

Method

Quantity

Immediate Packing Method for Ceramic Packages (Continued)
Package
Type
(Code)
Ceramic Pin Grid
Array (CPGA)

--

-----

-~-----

Primary
Immediate
Container

Package
Marketing
Drawing

Method

Quantity

U44A

Tray

80

U68B

Tray

42

U68C

Tray

42

U68D

Tray

42

U68E

'Tray

42

U75A

Tray

35

U84A

Tray

42

U84B

Tray

42

U84C

Tray

42

U99A

Tray

25

U100A

Tray

30

U109A

Tray

25

U120A

Tray

30

U120C

Tray

30

U124A

Tray

30

U132A

Tray

. 30

U132B

Tray

30

U144A

Tray

20

U156A

Tray

20

U156B

Tray

20

U169A

Tray

20

---U-1Z3A

Tray

20

U175A

Tray

20

U180A

Tray

20

U223A

Tray

20

U224A

Tray

20

U257A

Tray

12

U259A

Tray

12

U299A

Tray

12

U301A

Tray

12

U303A

Tray

12

U323A

Tray

12

9·11

Secondary
Immediate
Container
Method

Quantity

o ,---------------------------------------------------------------------------------,
C

~

CD
"CI

·iii

8
0')

c

Immediate Packing Method for Ceramic Packages (Continued)
Package
Type
(Code)

Package
Marketing
Drawing

Primary
Immediate
Container
Method

Cerpack

~

a.

Cerquad

Cerquad, EIAJ

Secondary
Immediate
Container

Quantity

Method

Quantity

W10A

Carrier/Rail

19

Carrier/Box

200

W14B

Carrier/Rail

19

Carrier/Box

200

W14C

Carrier/Rail

19

Carrier/Box

200

W16A

Carrier/Rail

19

Carrier/Box

200

W20A

Carrier/Rail

19

Carrier/Box

200

W24C

Carrier/Rail

15

Carrier/Box

BO

W2BA

Carrier/Rail

15

Carrier/Box

BO

WA28D

Carrier/Rail

15

Carrier/Box

BO

Rail/Tube

15

W24B
W56B

Tray

20

W64A

Tray

20

W6BA

Tray

12

WB4A

Tray

12

WABOA

Tray

B4

WABOAQ

Tray

B4

W120A

Tray

12

W144A

Tray

12

Wl44B

Tray

12

W160A

Tray

12

W208A

Tray

12

9·12

Immediate Packing Method for Metal Cans
Package
Type
(Code)

Package
Marketing
Drawing

Primary
Immediate
Container
Method

TO-5

Quantity

H06C

Tray

100

Secondary
Immediate
Container
Method
Carrier/Rail

Quantity
18

HOBA

Tray

100

Carrier/Rail

18

H08C

Tray

100

Carrier/Rail

18

H10C

Tray

100

Cerrier/ Rail

18

TO-18

HOSC

Box

1800

Tray

100

TO-S9

HOSA

Tray

100

Carrier/Rail .

18

HOSB

Tray

100

Carrier/Rail

18

HA04E

Tray

100

Carrier/Rail

18

H02A

Box

1800

Tray

100

HOSH

Box

1800

Tray

100

H04A

Box

1800

Tray

100

H04D

Box

1800

Tray

100

HOSJ

Box

1800

Tray

100

H04C

Box

1800

Tray

100

TO-46

TO-52
TO-72

•
9-1S

o

.-----------------------------------------------------------------------------~

o

Immediate Packing Method for Plastic Packages

C

~

CI»
-:g

"iii

8
Q

C

:iii!
u

:.

Primary
Immediate
Container

Secondary
Immediate
Container

Package
Type
(Code)

Package
Marketing
Drawing

Method·

Quantity

Method

Quantity

Sm·all
Outline
Transistor
(SOT-23)

. M03A

Tape and Reel

3000/
10000

Bulk/Bag

500

M03B

Tape and Reel

3000/
10000

Bulk/Bag

500

MOBA

Rail/Tube

95

Tape and Reel

2500

Rail/Tube

55

Tape and Reel

2500

M14B

Rail/Tube

50

Tape and Reel

1000

M16A

Rail/Tube

48

Tape and Reel

2500

M16B

Rail/Tube

45

Tape and Reel

1000

M20B

Rail/Tube

36

Tape and Reel

1000

M24B

Rail/Tube

30

Tape and Reel

1000

M28B

Rail/Tube

26

Tape and Reel

1000

M14D

Rail/Tube·

47

Tape and Reel

1000

M16D

Rail/Tube

47

Tape and Reel

1000

M20D

Rail/Tube

37

Tape and Reel

1000

Small
Outline
Package,
JEDEC
(SOP)

Small
Ouiline
Package,
EIAJ
(SOP)
Shrink
Small
Outline
Package,
JEDEC
(SSOP)
Shrink
Small
Outline
Package,
EIAJ
(SSOP)
Very
Small
. Outline
Package
(VSOP)

M14A

MQA20

Rail/Tube

54

Tape and Reel

2500

MQA24

Rail/Tube

54

Tape and Reel

2500

MS48A

Rail/Tube

29

Tape and Reel

1000

MS56A

Rail/Tube

25

Tape and Reel

1000

MSA20

Rail/Tube

65

Tape and Reel

1000

MSA24

Rail/Tube

58

Tape and Reel

1000

MS40A

Rail/Tube

34

Tape and Reel

1000

M40A

Rail/Tube

34

Tape and Reel

1000

Tray

156

Thin
Small
Outline
Package,
EIAJ
(TSOP)

MBH32A

Thin
Shrink
Small
Outline
Package,
EIAJ
(TSSOP)

MTA20

Tape and Reel

9-14

2500

-a
~

Immediate Packing Method for Plastic Packages (Continued)

~

Package
Type
(Code)

Package
Marketing
Drawing

Primary
Immediate
Container
Method

Molded
Dual-In-Line
Package
(MDIP)

TO-202

+------

T0-237

TO-226

s·
oo

Secondary
Immediate
Container

Quantity

NOBE

RaU/Tube

40

N14A

Rail/Tube

25

N16A

Rail/Tube

20

N16E

Rail/Tube

25

N16G

Rail/Tube

20

N1BA

Rail/Tube

20

N20A

Rail/Tube

1B

N22A

Rail/Tube

15

N22B

Rail/Tube

15

N24A

Rail/Tube

15

N24C

Rail/Tube

15

N24D

Rail/Tube

15

N24E

Rail/Tube

15

N2BB

Rail/Tube

13

N40A

Rail/Tube

9

N4BA

Rail/Tube

7

Method

CQ

Quantity

a:
CD

a
o·
:::::II
til

P03A

Rail/Tube

45

Box

300

P03B

Rail/Tube

45

Box

300

P03C

Rail/Tube

45

Box

300

P03D

Rail/Tube

45

Box

300

P03E

Rail/Tube

45

Box

300

P03F

Rail/Tube

45

Box

300

P03G

Rail/Tube

45

Box

300

P03H

Rail/Tube

45

Box

300

P03J

Rail/Tube

45

Box

300

P04A

Rail/Tube

45

Box

300

P11A

Rail/Tube

15

R03A

Box

1500

Tape and Reel

2000

R03B

Box

1500

Tape and Reel

2000

R03C

Box

1500

Tape and Reel

2000

R03D

Box

1500

Tape and Reel

2000

RC03A

Box

1500

Tape and Reel

2000

RC03B

Box

1500

Tape and Reel

2000

RC03C

Box

1500

Tape and Reel

2000

RC03D

Box

1500

Tape and Reel

2000

9-15

:::::II
til

o
C

o

~

CI»
-g

·iii
c

o
o
Q

C

r-------~------------------------------------------------------------------------~
Immediate Packing Method for Plastic Packages (Continued)
Package
Type
(Code)

Package
Marketing
Drawing

Primary
Immediate
Container
Method

TO·220

:iii!

i

Secondary
Immediate
Container.

Quantity

Method

Quantity

TA02A

Rail/Tube

45

Box

300

T020

Rail/Tube

45

Box

300

TA03A

Rail/Tube

45

Box

300

TA03B

Rail/Tube

~5

Box

300

TA030

Rail/Tube

45

Box

300

T03A

Rail/Tube

45

Box

300

T03B

Rail/Tube

45

Box

300

T030

Rail/Tube

45

Box

300

T03F

Rail/Tube

45

Box

300

T05A

Rail/Tube

45

Box

300

T05B

Rail/Tube

45

Box

300

T05C

Rail/Tube

45

Box

300

T050

Rail/Tube

45

Box

300

T05E

Rail/Tube

45

Box

300

T05F

Rail/Tube

45

Box

300

TA05A

Rail/Tube

45

Box

300

TA05B

Rail/Tube

45

Box

300

TA11A

Rail/Tube

20

Box

300

TA11B

Rail/Tube

20

Box

300

TA11C

Rail/Tube

20

Box

300

TA110

RaIl/Tube

20

Box

300

TA11E

Rail/Tube

20

Box

300

TA12A

Rail/Tube

20

Box

300
300
300

TA15A

Rail/Tube

20

. Box

TA23A

Rail/Tube

15

Box

TapePak®

TP40A

Coinstack
Tube

100

Flat Rail

Plastic Pin
Grid Array
(PPGA)

UP124A

Tray

30

UP159A

Tray

20

UP175A

Tray

20

V20A

Rail/Tube

40

Tape and Reel

1000

V28A

Rail/Tube

35

Tape and Reel

750

V32A

Rail/Tube

30

Plastic
Leaded Chip
Carrier
(PLCC)

25

V44A

Rail/Tube

25

Tape and Reel

500

V52A

Rail/Tube

22

Tape and Reel

500

V68A

Rail/Tube

18

Tape and Reel

250

V84A

Rail/Tube

15

Tape and Reel

250

9·16

,-----------------------------------------------------------------------------,
Immediate Packing Method for Plastic Packages (Continued)
Package
Type
(Code)

Primary
Immediate
Container

Package
Marketing
Drawing

Method
Plastic Quad
Flatpack
(PQFP)

TO-92

Method

ea
o
o
::s

!!.

Quantity

Q.
CD

a
o·
::s

VEF44A

Tray

96

VBG48A

Tray

60

VHG80A

Tray

60

VJE80A

Tray

84

VCC80A

Tray

50/66

VCE100A

Tray

84

VLJ100A

Tray

50

VJG100A

Tray

60

VNG144A

Tray

60

VUL160A

Tray

24

VQL160A

Tray

24

VUW208A

Tray

24

VF132A

Tray

36

VF196A

Tray

21

Z03A

Box

1800

Tape and Reel

2000

Z03B

Box

1800

Tape and Reel

2000

Z03C

Box

1800

Tape and Reel

2000

Z03D

Box

1800

Tape and Reel

2000

Z03E

Box

1800

Tape and Reel

2000

Z03G

Box

1800

Tape and Reel

2000

Z03H

Box

1800

Tape and Reel

2000

Z03J

Box

1800

Tape and Reel

2000

(I)

----1-----

Labeling
and outer/shipping container labels. The tape and reel, and
intermediate container labels are National's own format
while the outer/shipping container label is based on the
EIA-556-A label standard.

National Semiconductor offers 3 standard bar code labels;
reel and intermediate container labels for Tape and Reel;
intermediate container label other than for Tape and Reel;

NSC Standard Tape and Reel Label

(P) CPN: CPNl23456789012

1
(0)

1111111111
aTY: 1000

111111111111111111111111111111

XYZ CCI"PANY

11111111111111111111111111111111111111111
PO *I: PO 123456789012
·(0) O/C: P9236
NSID: DM74ALS253WM

111111111111111111111I1111111111111

~C: ~C~~~5678912
TLlP/11809-8

This label is placed on the reel (immediate container) as
well as on the intermediate box.

9-17

~

s""

Secondary
Immediate
Container

Quantity

~

U)r--------------,
C

o

~

CP
'C

"iii
c

..

xyz COt'Pft..lY

( P) CPN

o
o
C

u

:.

CPN 1234567890

111111111

at

:si2

NSC Standard Intermediate Container Label

(C) CTV 1000

IIIIIIIIIIII~II

(D) D.C. P9236

111111111111111111111111111111111

( A) P. o. PO 123456789012

I I I I I I I I~I I I I I I I I I I I I I I I I I I I I I ~I I I1

I

111111

11111·

NSID
: Dt174R...S253JM
p" L.
: PL1234
FIN OPT : SPEC1234
.
REQA
: RV1234
LOT
: LOT 123456789
BOX 01 OF 03
.
t-FlTIOI'R.. SEMICCN)IJCTOR
TL/P/11809-9

NSC Standard Outer/Shipping Container Label

li.iiiiiliiliiiiiiliil . . ;;'111-=!:~ 5C

I----:-=(z=-==-=)
SPECI::-:-:--AL:--~---,
.

~

1

SHIP TO ftDDIIIIESS

a

SHIP TO

SHIP TO ADDRESS :I
SHIP TO fllDDRESS 4.

.

SHIP TO ADDRESS 5

PACKAGE COlNT

10000 EA

02

~05

.

PACKAGE WEIGHT

1000 KG 2540 L8
(P)

~60W CPN12345678901234567890

1 ~1I1 1 il l~I I I I I I I I I ~ I ~1I1 1 ~111I111I1~1I1111111111111111
TL/P/11809-10

9-18

.

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tflNational Semiconductor

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Board Mount of Surface Mount Components

o

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n

II)

CD

Abstract

Due to the limited number of devices that are surface mount
components, it is necessary to mix both lead inserted components and surface mount components on the same
board.

In facing the challenges of "Surface Mount Technology",
many manufacturers of printed circuit boards have taken
steps to convert some portions of their boards to this process. However, as the availability of all products as surface
mount components is still limited, many have had to mix
lead-inserted components with surface mount devices
(SMD's). Furthermore, to take advantage of using both
sides of the board, some surface mounted components are
adhered to the bottom side of the board while the top side is
reserved for the conventional lead-insert packages and fine
pitch surface mount packages.
There are three surface mount processes in hi-volume use
today:
'
1. WAVE SOLDER; the surface mounted components are
adhered to the bottom side of the, board while the top
side is reserved for the lead-inserted packages. The surface, mouni components are subjected to severe thermal
stress when they are immersed into the molten solder.

Some components such as relays and switches are made of
materials which would not be able to survive the temperature exposure in a vaPClr phase or IR furnace.

P

b

P

W Board Assem Iy rocedures

There are two considerations in which through-hole ICs may
be combined with surface mount components on the PW
Board:
a) .Whether to mount ICs on one or both sides of the board.
b) The sequence of soldering using Vapor Phase, IR or
Wave Soldering singly. or a combination of two or more
methods.
The various processes that may be employed are:

:s:::
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CD

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tn,

A) WAVE SOLDER BEFORE VAPOR/IR REFLOW

2. INFRA·RED mass reflow; the surface mount components are placed on the solder. paste which has been
applied to the board, the solder joints are formed when
the board is passed thru the reflow media. The surface
mount devices are subjected to a controlled thermal environment.

SOLDER
1. Components on the same side of PW Board. Lead insert
standard DIPS onto PW Board Wave solder (conventional).'Wash and lead trim. Dispense solder paste on SEM
pads. Pick and place SMDs onto PvV Board. Bake Vapor
.
phase/lR reflow. Clean.

3. VAPOR PHASE mass reflow; the surface mount coo;po:
2. Components on opposite side of PW Board. Lead insert
nellts_a(e_ma~Etd_(mJh_e .solder ~aste which has been
standard DIPs onto PW Board Wave Solder (conventionapplied to. the board, tbe solder joints are formed w=.hc-:e"-n'--------a·I);-Cleanand-lead trim;-lnvert-PW-Board,Dispensedrop -- .. _ _ ..the board is passed thru the reflow media. The surface
of adhesive on SMD sites (optional for smaller components). Pick and place SMDs onto board. Bake/Cure.
mount devices are subjected to a controlled thermal enInvert board to rest on raised fixture. Vapor/IR rellow
vironment, more severe than Infra-red but much less
than wavesolder.
soldering. Clean.
A discussion of the effecfof these processes on the reliilbility of plastic semiconductor packages follows.

B) VAPORilR REFLO.w SOLDER THEN WAVE SOLDER
1. Components on the same side of PW Board. Solder
'. paste screened on SMD side of Printed Wire Board. Pick
and place SMDs. Bake Vapor/IR reflow. Lead insert on
same side as SMD's. Wave solder. Clean and trim underside of PCB.
'

Role of Wave Soldering 'in
Application of SMDs
The generally acceptable methods of soldering SMDs are
vapor phase rellow soldering and IR reflow soldering, both
requiring application of solder paste on PW boards prior to
placement of the components. However, sentiment still exists for retaining the use of the old wave soldering machine.
The reasons being:
Most PC Board Assembly houses already possess wave
soldering eqUipment. Switching to another technology such
as vapor phase soldering requires substantial investment in
equipment and people.

C) VAPOR/IR REFLOW ONLY
1. Compo'rients' on the same side of PW Board Trim and
form 'standard DIPs in "gull wing" configuration. Solder
paste screened on PW Board. Pick and place SMDs and
, DIPs. Bake Vapor/lR reflow. Clean.
.
2. Components on opposite sides of PW Board. Solder
paste screened on SMD-side of Printed Wire Board. Adhesiv~ dispensed at ceJ'ltrallocation, of each component.
Pick and place SMDs. B!'\ke. Solder paste screened on
all pads on DIP-side or alternatively apply solder rings
(performs) on leads. Lead insert Dips. Vapor/IR rellow.
'
Clean and lead 'trim.

9-19

•

~CP
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1:
~

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~

~

-

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i

ID

Transition Temperature

PW Board Assembly Procedures
(Continued)
D) WAVE SOLDERING ONLY
1. Components on opposite sides of PW board. Adhesive
dispense on SMD side of PW Board. Pick and place
SMDs. Cure adhesive. Lead insert top side with DIPs.
Wave solder with SMDs down and into solder bath.
Clean and lead trim.

A-U=4.6

~~~;;:::;::::::;::~,~~::::=:;
T (Oe)
100 110 120 130 140 150 160,170 180

All of the above assembly procedures can be divided into
three categories for IC. Reliability considerations:

Tg

1) Components are subjected to both a vapor phasellR
heat cycle then followed by a wave-solder heat cycle or
vice versa.

TL/P/11828-1

FIGURE 1. Thermal Expansion and Glass

2) Components are subjected to only a vapor phasellR
heat cycle.
'

Conventional Wave Soldering

3) Components are subjected to wave-soldering only and
SMDs are subjected to heat by immersion into a solder
pot.
Ot these three categories, the last is the most severe regarding heat treatment to a semiconductor device. However, note that semiconductor molded packages generally
possess a coating of solder on their leads as a final finish
for solderability and protection of base leadframe material.
Most semiconductor manufacturers solder-plate the component leads, while others perform hot solder dip. In the latter
case the packages may be subjected to total immersion into
a hot solder bath unller controlled conditions (manual operation) or be partially immersed while in a "pallet" where
automatic wave or DIP soldering processes are used. It is,
therefore, possible to subject SMDs to solder heat under
certain conditions and not cause catastrophiC failures.

Most wave soldering operations occur at temperatures between 240·C-260·C. Conventional epoxies for encapsulation have glass-transition temperatures between 140"C170·C. An I.C. directly exposed to these temperatures risks
its long term functionality due to epoxy/metal separation.
Fortunately, there are factors that can reduce that element
of risk:
1. The PW board has a certain amount of heat-sink effort
and tends to shield the components from the temperature of the solder (if they were placed on the top side of
the board). In actual measurements, DIPs achieve II temperature between 120·C-150·C in a'5-second pass over
the solder. This accounts for the fact that DIPs mounted
in the conventional manner are reliable.
2) In conventional soldering, only the tip of each lead in DIP
would experience the solder temperature because the
epoxy and die are standing abol(e the PW board and out
of the solder bath.

Thermal Characteristics of Molded
Integrated Circuits

Effect on Package Performance by
Epoxy-Metal Separation

Since Plastic DIPs and SMDs are encapsulated with a thermoset epoxy, the thermal characteristics of the material
generally correspond to a TMA (Thermo-Mechanical Analysis) graph. The critical parameters are (a) its Linear thermal
expansion characteristics and (b) its glass transition temperature after the epoxy has been fully cured. A typical TMA
graph is illustrated in Figure 1. Note that the epoxy changes
to a higher thermal expansion once it is subjected to temperatures exceeding its glass transition temperature. Metals
(as used on leadframes, for example) do not have this characteristic and generally will have a consistent Linear thermal
expansion over the same temperature range.

In wave soldering, it is necessary to use fluxes to assist the
solderability of the components and PW boards. Some facilities may even process the boards and components through
some form of acid cleaning prior to the soldering temperature. If separation occurs, the flux residues and acid residues (which may be present owing to inadequate cleaning)
will be forced into the package mainly by capillary action as
the residues move away from the solder heat source. Once
the package is cooled, these contaminants are now trapped
within the package and are available to diffuse with moisture
from the epoxy over time. 'It should be noted that electrical
tests performed immediately after soldering generally will
give no indication of this potential problem. In any case, the
end result will, be corrosion of the chip metalization over
time and premature failure of the device in the field.

In any good reliable plastic package, the choice of leadframe material should be such to match its thermal expansion properties to that of the encapsulating epoxy. In the
event that there is a mismatch between the two, stresses
can build up at the interface of the epoxy and metal. There
now exists a tendency for the epoxy to separate from the
metal leadframe in a manner similar to that observed on
bimetallic thermal range.
In most cases when the packages are kept at 'temperatures
below their glass transition, there is a small possibility of
separation at the epoxy-metal Interface. However, If the
package is subjected to temperature above its glass-transition temperature, the epoxy will expand much faster than
the metal and the probability of separation is greatly increased.

9-20

,--------------------------------------------------------------------------, m
Vapor Phase/lR

Re~low

TABLE IV. Vapor Phase vs. Wave Solder

S(Qlira1el1'ing

In both vapor phase and IA reflow soldering, the risk of
separation between epoxy/metal can also be high. Maximum operating temperatures are 219'C (vapor phase) or
240'C (IA) and duration may also be longer (30 sec-60
sec). On the same theoretical basis, there should also be
separation. However, in both these methods, solder paste is
applied to the pads of the boards; no fluxes are used. Also,
the devices are not immersed into the hot solder. This reduces the possibility of solder forcing itself into the epoxyleadframe interface. Furthermore, in the vapor phase system, the soldering environment is "oxygen-free" and considered "contaminant free". Being so, it could be visualized
that as far as reliability with respect to corrosion, both of
these methods are advantageous over wave soldering,

1. Vapor phase (60 sec. exposure @ 217'C)
=

!5:

oC

9 failures/1723 samples

= 0.5% (average over 32 sample lots)
2. Wave solder (2 sec total immersion @ 260'C)
= 16 failures/1201 samples
=

Bias moisture test 85% R.H.

Device:

85'C for 2,000 hours
LM324M

CD

:s:
o

This proprietary accelerated bias/moisture pressure-test is
significant in relation to the life test condition at 85'C and
85% relative humidity. One cycle of approximately 100
hours has been shown to be equivalent to 2,000 hours in
the 85/85 condition. Should the packages start to fail within
the first cycle in the test, it is anticipated that the boards with
these components in the harsh operating environment
(85'C/85% AH) will experience corrosion and eventual
electrical failures within its first 2,000 hours of operation.

Solder Dip
4 Sec @260'C
Solder Dip
4Sec@260'C

c

Solder Dip
6Sec@260'C

Whether this is significant to a circuit board manufacturer
will obviously be dependent on the products being manufactured-anathe-WorRlTfal1ship-or-reliability-standards~Gerreral~-­

Iy in systems with a long warranty and containing many
components, it is advisable both on a reputation and cost
basis to have the most reliable parts available.

Mounted

0/114

0/84

2/144(1.4%)

0/85

13/248 (5.2%)

0/83
1176(1.3%)

~Ol~!p~ _ _ _ -141-127-(-11.0%)- -31-79(3.8%)10 Sec@ 260'C

Package:
Device:

Test Results

Unmounted

-

SO-14 lead
LM324M

Since the package is of very small mass and experiences a
rather sharp thermal shoe/I followed by stresses created by
the mismatch in expansion, the results show the packages
being susceptible to failures after being immersed in excess
of 6 seconds in a solder pot. In the second case where the
packages were mounted, the effect of severe temperature
excursion was reduced. In any case, because of the repeated treatment, the package had failures when subjected in
excess of 6 seconds immersion in hot solder. The safety
margin is therefore recommended as maximum 4 seconds
immersion. If packages were immersed longer than 4 seconds, there is a probable chance of finding some long term
reliability failures even though the immediate electrical test
data could be acceptable.

The comparison of vapor phase and wave-soldering upon
the reliability of molded Small-Outline packages was performed using the bias moisture test (see Table IV). It is
clearly seen that vapor phase reflow soldering gave more
consistent results. Wave soldering results were based on
manual operation giving variations in soldering parameters
such as temperature and duration.

9-21

:::I

TABLE V. Summary of Wave Solder Results

ControlNapor Phase
15 sec@ 215'C

r J)

c

(')

Test:

In Table V we examine the tolerance of the Small-Outlined
(SOIC) package to varying immersion time in a' hot solder
pot. SO-14 lead molded pacllages were subjected to the
bias moisture test after being treated to the various soldering conditions and repeated four (4) times. End point was an
electrical test after an equivalent of 4,000 hours 85/85 test.
Aesults were compared for pacllages by themselves
against packages which were surface-mounted onto a FA-4
printed wire board.

A bias moisture test was designed to determine the effect
on package performance. In this test" the packages are
pressured in a steam chamber to accelerate penetration of
moisture into the package. An electrical bias is applied on
the device. Should there be any contaminants trapped within the package, the moisture will quicldy form an electrolyte
and cause the electrodes (which are the lead fingers), the
gold wire and the aluminum bond-pads of the silicon device
to corrode. The aluminum bond-pads, being the weakest
link of the system, will generally be the first to faiL

--

:::I
,0

;.

1.3% (ave;age over 27 sample lots)

Package: SO-14 lead

Bias Moisture Test

oIl)

a

oo
3
o

"C

:::I

@

:::I
UI

sc

CP

c

8E

o
u

c::;,

o

:::IE
CP
u

Finally, Table VI examines the bias moisture test performed
on surface mount (SOIC) components manufactured by various semiconductor houses. End point was an electrical test
after an equivalent of 6,000 hours in an 85/85 test. Failures
were analyzed and corrosion was checked for in each case
to detect flaws in package integrity.

Package
SO-8

-

Vapor
Phase
30 sec

Wave
Solder
2 sec

Wave
Solder
4 sec

Wave
Solder
6 sec

Wave
Solder
10 sec

ManufA
ManufB
ManufC

8/30'
2/30'
0/30

1/30'
8/30'
0/29

0/30
2/30'
0/29

12/30'
22/30'
0/30

16/30'
20/30'
0/30

ManufD
Manuf E
Manuf F
NSC

1/30'
1/30"
0/30
0/30

12/30'
0/30
0/30
0/30

14/30'
0/30
0/30
0/30

2/30'
0/30
0/30
0/30

tn

c

::;,

o

:::IE

'E
8
m

Based on the results presented, it is noted that surfacemounted components are as reliable as standard molded
DIP packages. Whereas DIPs were never processed by being totally immersed in hot solder wave during printed circuit
board soldering, surface mounted components. such as
SOICs (Small Outline) are expected to survive a total immersion in the hot solder in order to capitalize on maximum
population on boards. Being constructed from a thermoset
plastic of relatively low T9 compared to the soldering temperature, the ability of the package to survive is dependent
on the time of immersion and also the cleanliness of material. The results indicate that one should limit the immersion
time of the package in the solder wave to a maximum of 4
seconds in order to truly duplicate the reliability of a DIP. As
the package size is reduced, as in a SO-8 lead, the requirement becomes even more critical. This is shown by the various manufacturers' performance. Results indicate there is
room for improvement since not all survived the hot solder
immersion without compromise to lower reliability.

TABLE VI. U.S. Manufacturing Integrated Circuits
Reliability in Various Solder Environments
(# Failure/Total Environment)

~
::;,

'0

Summary

·CorrosiOn failures
··No Visual Defects-Nan-corrosion failues

Test Accelerated Bias Moisture Test: 85% R.H.l85'C. 6,000 equivalent
hours

9-22

-"'"

ttl

::IJ

83

National Semiconductor

3CI)
~

Recommended Soldering Profiles-Surface Mount

a.
CI)
a.
en
o

a::
....

CI)

3"

Ramp Up DC/sec

Maximum

Dwell Time:;, 1B3°C

Solder Temperature

IR
Profile

Vapor
Phase

6°C/sec

4°C/sec

24°C/sec

4°C/sec'

2°C/sec'

••

..

2°C/sec

Minimum
Maximum

135°C

N/A

N/A

Recommended

120°C

N/A

N/A

Recommended

aT

Wave
Solder

Minimum

110°C

N/A

N/A

Maximum

N/A

B5 seconds

B5seconds

Recommended

N/A

75 seconds'

75 seconds'

Minimum

N/A

30 seconds"

Maximum

260°C

2400C'"

219°C

Recommended

240°C

..

215°C'

..

215°C'

Minimum
Dwell Time @ Max.

Maximum

~~--

10 seconds

75

Minimum

..

70 seconds

Maximum

No Information

4°C/sec

4°C/sec

4°.c:!sec

2°C/sec

..

2°C/sec

Recommended

-~~

Note: Temperature In degrees celclus. N/A

No Information

'"U

!
c

~

iii:

oc

~

..

5 seconds

3 seconds

Minimum
boT

.,

4 seconds

Recommended

Ramp Down DC/sec

..

CC

..

1 second

..

= Not Applicable.

= The temperature differential between the final preheat stage and the soldering stage. Temperature measured at the component lead area.

'Will vary depending on board density, geometry, and package type.
"Will vary depending on package types, and board denSity.
••• For plastic packages; ceramic packages maximum may be 250°C.

•
9·23

Small Outline (SO) Package
Surface Mounting MethodsParameters and Their
Effect on Product Reliability

National Semiconductor
Application Note 450
Josip Huljev
W. K. Boey

The SO (small outline) package has been developed to
meet customer demand for ever-increasing miniaturization
and component density., '

In order to achieve reliability performance comparable to
DIPs-SO packages are designed and built with materials
and processes that effectively compensate for their small
size.
All SO packages tested on 85%RA, 85'C were assembled
on PC conversion boards using vapor-phase reflow soldering. With this approach we are able to measure the effect of
surface mounting methods on reliability of the process. As
illustrated in Figure A no significant difference was detected
between the long term reliability performance of surface
mounted S.O. packages and the DIP control product for up
to 6000 hours of accelerated 85%/85~C testing.

COMPONENT SIZE COMPARISON
S.O. Package

~

r--

TYPICALLY 0.050" LEADSPACING

SURFACE·MOUNT PROCESS FLOW
The standard process flowcharts for basic surface-mount
operation and mixed-lead insertion/surface-mount operations, are illustrated on the following pages.

TL/F/8766-1

Standard DIP Package

Usual variations encountered by users of SO packages are:
• Single-sided boards, surface-mounted components only.
• Single-sided boards, mixed-lead inserted and surfacemounted components.

~

I---:- TYPICALLY 8.1l1li- WDSPACING

TLlF/8766-2

Because of its small size, reliability of the product assembled in SO packages needs to be carefully evaluated.
SO packages at National were internally qualified for 'production under the condition that they be of comparable reliability performance to a standard dual in line package under
all accelerated environmental tests. Figure A is a summary
of accelarated bias moisture test performance on 30V bipolar and 15V CMOS product assembled in SO and DIP (control) packages.

• Double-sided boards, surface-mounted components only.
• Double-sided boards, 'mixed-lead inserted and surfacemounted components.
In consideration of these variations, it became necessary for
users to utilize techniques involving wave soldering and adhesive applications, along with the commonly-used vapor,phase solder reflow soldering technique~
PRODUCTION FLOW
Basic Surface-Mount Production Flow

V+= 15VCMOS
30V BIPOLAR
85% RH/85"C
TEST CONDITION

DIP

o

2000

4ODO

6000

TEST TIME (HRS)
TLlF/8766-3

FIGURE A

TUF/8766-4

9-24

Thermal stress of the packages during surface-mounting
processing is more severe than during standard DIP PC
board mounting processes. Figure B illustrates package
temperatLire versus wave soldering dwell time for surface
mounted packages (components are immersed into the
molten solder) and the standard DIP wave soldering process. (Only leads of the package are immersed into the mol.'
ten solder).

Mixed Surface-Mount and Axial-Leaded Insertion
Components Production Flow

SOLDER TEMPERATURE 260"C

o

1 2 3 4 5 6 7 8 9 10 SEC.
DWELL mtE
TUF/8766-6

FIGUREB

For an ideal package, the thermal expansion rate of the
encapsulant should match that of the leadframe material in
order for the package to maintain mechanical integrity during the soldering process. Unfortunately, a perfect matchup
of thermal expansion rates with most presently used packaging materials is scarce. The problem lies primarily with the
epoxy compound.
Normally, thermal expansion rates for epoxy encapsulant
and metal lead frame materials are linear and remain fairly
close at temperatures approaching 160'C, Figure C. At lower temperatures the difference in expansion rate of the two
materials is not great enough to cause interface separation.
However, when the package reaches the glass-transition
~ --c-~ -.----temperature-fF-g)-ef~epoxy~(typically-160~165·G),__the-ther--- ----~--~

mal expansion rate of the encapsulant increases sharply,
and the material undergoes a transition into a plastic state.
The epoxy begins to expand at a rate three times or more
greater than the metal leadframe, causing a separation at
the interface.

TL/F/8766-5

z
a
z
~

iii

....x
-'
-<
:::;:

....a::

al

i=

I

I

100 110 120 130 140 150 160,170 180

Tg

T(OC)
TUF/8766-28

FIGUREC

9-25

When this happens during a conventional wave soldering
process using flux and acid cleaners, process residues and
even solder can enter the cavity created by the separation
and become entrapped when the material cools. These
contaminants can eventually diffuse into the interior of the
package, especially in the presence of moisture. The result
is die contamination, excessive leakage, and even catastrophic failure. Unfortunately, electrical tests performed immediately following soldering may not detect potential flaws.

The basic component-placement systems available are
classified as:
(a) In-line placement
-

Boards indexed under head and respective components placed
(b) Sequential placement
-

Most soldering processes involve temperatures ranging up
to 260'C, which far exceeds the glass-transition temperature of epoxy. Clearly, circuit boards containing SMD packages require tighter process controls than those used for
boards populated solely by DIPs.

-Individual components picked and placed onto boards

Standard DIP package

Group 2 -

SO packages vapor-phase reflow soldered on
PC boards

Group 3-6 SO packages wave soldered on PC boards
dwell time 2 seconds
dwell time 4 seconds

5-

dwell time 6 seconds

6-

dwell time 10 seconds

o

2000

4000

-

Multiple pickup heads

-

Whole array of components placed onto the PCB at
the same time

(d) Sequential/simultaneous placement

Group 1 -

4-

Either a X-V moving table system or a 0, X-V moving
pickup system used

(c) Simultaneous placement

Figure D is a summary of accelerated bias moisture test
performance on the 30V bipolar process.

Group 3 -

Fixed placement stations

-

-

X- Y moving table, multiple pickup heads system

-

Components placed on PCB by successive or simultaneous actuation of pickup heads

The SO package is treated almost the same as surfacemount, passive components requiring correct orientation in
placement on the board.
Pick and Place Action

6000

TEST TIME (HRS)
TL/F/8766-7

FIGURED

It is clear based on the data presented that SO packages
soldered onto PC boards with the vapor phase reflow process have the best long term bias moisture performance
and this is comparable to the performance of standard DIP
packages. The key advantage of reflow soldering methods
is the clean environment that minimized the potential for
contamination of surface mounted packages, and is preferred for the surface-mount process.

Tl/F/B766-8

BAKE

This is recommended, despite claims made by some solder
paste suppliers that this step be omitted.
The functions of this step are:

When wave soldering is used to surface mount components
on the board, the dwell time of the component under molten
solder should be no more than 4 seconds, preferrably under
2 seconds in order to prevent damage to the component.
Non-Halide, or (organic acid) fluxes are highly recommended.

• Holds down the solder globules during subsequent reflow
soldering process and prevents expulsion of small solder
balls.
• Acts as an adhesive to hold the components in place during handling between placement to reflow soldering.
• Holds components in position when a double-sided surface-mounted board is held upside down going into a vapor-phase reflow soldering operation.

PICK AND PLACE

The choice of automatic (all generally programmable) pickand-place machines to handle surface mounting has grown
considerably, and their selection is based on individual
needs and degree of sophistication.

• Removes solvents which might otherwise contaminate
other equipment.
• Initiates activator cleaning of surfaces to be soldered .
• Prevents moisture absorption.

9-26

,--------------------------------------------------------------------------,
The process is moreover very simple. The usual schedule is
about 20 minutes in a 65'C-95'C (dependent on solvent
system of solder paste) oven with adequate venting. Longer
bake time is not recommended due to the following reasons:

VAPOR-PHASE REFLOW SOLDERING
Currently the most popular and consistent method, vaporphase soldering utilizes a fluoroinert fluid with excellent
heat-transfer properties to heat up components until the solder paste reflows. The maximum temperature is limited by
the vapor temperature of the fluid.
The commonly used fluids (supplied by 3M Corp) are:

• The flux will degrade and affect the characteristics of the
paste.
'
• Solder globules will begin to oxidize and cause solderability problems.

~

Z

•

~

CII

C)

• FC-70, 215'C vapor (most applications) or FX-38
- FC-71 , 253'C vapor (low-lead or tin-plate)
HTC, Concord, CA, manufactures equipment that utilizes
this technique, with two options:

• The paste will creep and after reflow, may leave behind
residues between traces which are difficult to remove and
vulnerable to electro-migration problems.

- Batch systems, where boards are lowered in a basket and
subjected to the vapor from a tank of boiling fluid.
-In-line conveyorized systems, where boards are placed
onto a continuous belt which transports them into a concealed tank where they are subjected to an environment
of hot vapor.
Dwell time in the vapor is generally on the order of 15-30
seconds (depending on the mass of the boards and the
loading density of boards on the belt).

REFLOW SOLDERING
There are various methods for reflowing the solder paste,
namely:
• Hot air reflow
• Infrared heating (furnaces)
• Convectional oven heating
• Vapor-phase reflow soldering
o Laser soldering

Vapor-Phase Profile

For SO applications, hot air reflow/infrared furnace may be
used for low-volume production or prototype work, but vapor-phase soldering reflow is more efficient for consistency
and speed. Oven heating is not recommended because of
"hot spots" in the oven and uneven melting may result. Laser soldering is more for specialized applications and requires a great amount of investment.

RECOMMENDED

R ( [ ] 20 DEG C/s.c )

A

HOT GAS REFLOW/INFRARED HEATIN.G
A hand-held or table-mount air blowElr (with appropriate orifice mask) can be used.
The boards are preheated to about 1OODC an~ then subjected to an air jet at about 260'C. This is a slow process and
results'may be inconsistent due to various heat-sink properties of passive components.

U

R

TIME
TUF/8766-28

INFRARED REFLOW SOLDERING ,
j=--_ _ _~ln~-LineCp'!veyorlzed Vapo!:Phase Soldering _ _,_ _ _ _ _ _ ,
Useo! an-infrared -furnace- is currentlytne mosfpopular
CONOENSATION
method to automate mass reflow, the heating is promoted
'~COILS
by use of IR lamps or panels. Early objections to this method were that certain materials may heat up at different rates
under IR radiation and could result in damage to those com.
ponents (usually sockets and connectors). This has been
minimized by using far-infrared (non-focused) systems and
VAPOR
PROOUCT
_
convected air.
- - Infrare,d Profile
- UUU - aELT -~ - - - - - -

J

L

nnn

RECOMMENDED

1---

1

COILS

,T

COILS

c::::::::::::>
LIQUID
IMMERSION HEATER
TL/F/8766-9

R ( [ ] 1 DEG C/s.c

o

)

The question of thermal shock is asked frequently because
of the relatively sharp increase in component temperature
from room temperature to 215'C. SO packages mounted on
representative boards have been tested and have shown
little effect on the integrity of the packages. Various packages, such as cerdips, metal cans and TO-5 cans with glass
seals, have also been tested.

50 100 150 199 250 300
TIME
TL/F/8766-27

9-27

•

Batch-Fed Production Vapor-Phase Soldering Unit

Vapor-Phase Furnace '

SECONDARY

PRIMARY

TLlF/8766-11

TL/F/8768-10
;'"

Solder Joints ,on a SO-14 Package on PCB

Solder Joints on a 80-14 Package on PCB

TL/F/8766-12

TLlF/8766-13

9-28

PRINTED CIRCUIT BOARD
The SO package is molded out of clean, thermoset plastic
compound and has no particular compatibility problems with
most printed circuit board substrates.
The package can be reliably mounted onto substrates such
as:
o G10 or FR4 glass/resin
o FR5 glass/resin systems for high-temperature
applications

common and well-tried method. The paste is forced through
the screen by a V-shaped plastic squeegee in a sweeping
manner onto the board placed beneath the screen.
The setup for SO packages has no special requirement
from that required by other surface-mounted, passive components. Recommended working specifications are:
0 Use stainless-steel, wire-mesh screens, #80 or #120,
wire diameter 2.6 mils. Rule of thumb: mesh opening
should be approximately 2.5-5 times larger than the average particle size of paste material.

• Polymide boards, also high-temperature
applications
o Ceramic substrates

Use squeegee of Durometer 70.
Experimentation with squeegee travel speed is recommended, if available on machine used.
o Use solder paste of mesh 200-325.
0
0

General requirements for printed circuit boards are:
• Mounting pads should be solder-plated whenever
applicable.
o

0

Solder masks are commonly used to prevent solder bridging of fine lines during soldering.
The mask also protects circuits from processing chemical
contamination and corrosion.

0
0

If coated over pre-tinned traces, residues may accumulate
at the mask/trace interface during subsequent reflow,
leading to possible reliability failures.
Recommended application of solder resist on bare, clean
traces prior to coating exposed areas with solder.
General requirements for solder mask:
_ Good pattern resolution.

Emulsion thickness of 0.005" usually used to achieve a
solder paste thickness (wet) of about 0.008" typical.
Mesh pattern should be 90 degrees, square grid.
Snap-off height of screen should not exceed Va" , to avoid
damage to screens and minimize distortion.

SOLDER PASTE
Selection of solder paste tends to be confusing, due to numerous formulations available from various manufacturers.
In general, the following guidelines are sufficient to qualify a
particular paste for production:
0 Particle sizes (see following photographs). Mesh 325 (approximately 45 microns) should be used for general purposes, while larger (solder globules) particles are preferred for lead.less components (LCC). The larger particles
can easily be used for SO packages.
0 Uniform particle distribution. Solder globules should be
spherical in shape with uniform diameters and minimum
amount of elongation (visual under 100/200 x magnification). Uneven distribution causes uneven melting and subsequent expulsion of smaller solder balls away from their
proper sites.

- Complete coverage of circuit lines and resistance to
flaking during soldering.
- Adhesion should be excellent on substrate material to
keep off moisture and chemicals.
- Compatible with soldering and cleaning requirements.
SOLDER PASTE SCREEN PRINTING

With the initial choice of printed circuit lithographic design
and substrate material, the first step in surface mounting is
the"application"ofsolder"paste.--- "---_ _ _ _--'o"'C"'o"'m"Jl1osition, generally 60/40 or 63/37 Sn/Pb. Use 62/36
Sn/Pb with 2% Ag in the presence of Au on the soldering
The typical lithographic "footprints" for SO packages are
area. This formulation reduces problems of metal leaching
from soldering pads.
illustrated below. Note that the 0.050" lead center-center
spacing is not easily managed by commercially-available air
pressure, hand-held dispensers.
• RMA flux system usually used.
USing a stainless-steel, wire-mesh screen stencilled with an
0 Use paste with aproximately 88-90% solids.
emulsion image of the substrate pads is by far the most

9·29

RECOMMENDED SOLDER PADS FOR SO PACKAGES

so-a, SO-14, SO-16

So-16L,So-20

IIII "

0.045" :I: 0.005"

r····~

0.245"

. . ····1

0.160"

L-I••••
I
I- -I

0.030" :1:0.005"

'GE ••• ~1°O·

1-0.050"TYP
TlIF/8766-14

SOT-23
0.030" :1:0.005"1

I-

0.030· :1:0.005"--1

1-

~'

1-:J.TYp
TL/F/6766-15

ii"

"

,'"

·'I.-tl-f
TL/F/8766-16

Comparison of Particle Size/Shape of Various Solder Pastes
200

200 x Alpha (62/36/2)

TlIF/8766-17

x Kester (63/37)

TL/F/B766-1B

9-30

r--------------------------------------------------------------------,~

Z

Comparison of Particle SizelShape of Various Solder Pastes (Continued)

i

200 x Fry Metal (63137)

Solder Paste Screen on Pads

TL/F/B766-20

TL/F/8766-19

200 ESL (63137)

TL/F/B766-21

9-31

CLEANING

Hot-Air Rework Machine

The most critical process in surface mounting SO packages
is in the cleaning cycle: The package is mounted very close
to the surface of ·the substrate and has a tendency to collect
residue left behind after reflow soldering. .
Important considerations in cleaning are:
• Time between soldering and cleaning to be as short as
possible. Residue should not be allowed to solidify on the
substrate for long periods of time, making it difficult to
dislodge.
• A low surface tension solvent (high penetration) should be
employed. CFC solvents are being phased out as they are
hazardous to the environment. Other approaches to
cleaning are.commercially available and should be investigated on an individual basis considering local and government environmental rules.

TUF/B7BB-23

lead tips or, if necessary, solder paste can be dispensed
onto the pads using a varimeter. After being placed into
position, the solder is reflowed by a hot-air jet or even a
standard soldering iron.

Prelete or 1,1,1-Trichloroethane
Kester 5120/5121

WAVE SOLDERING
In a case where lead insertions are made on the same
board as surface-mounted components, there is a need to
include a wave-soldering operation in the process flow.
Two options are used:
• Surface mounted' componerits are placed and vapor
phase reflowed before auto-insertion of remaining components. The board is carried over a standard wave-solder
system and the underside of the board (only lead-inserted
leads) soldered.

• A defluxer system which allows the workpiece to be subjected to a solvent vapor, followed by a rinse in pure solvent and a high-pressure spray lance are the basic requirments for low-volume production.
• For volume. production, a conveyorized, multiple hot solvent spray/jet system is recommended.
• Rosin, being a natural occurring material, is not readily
soluble in solvents, and has long been a stumbling block
to the cleaning process. In recent developments, synthetic flux (SA flux), which is readily soluble in Freon TMS
solvent, has been developed. This should be explored
where permisSible.

• Surface-mounted components are placed in position, but
no solder paste is used. Instead, a drop of adhesive about
5 mils maximum in height with diameter not exceeding
25% width of the package is used to hold down the package. The adhesive is cured and then proceeded to autoinsertion on the reverse side of the board (surface-mounted side facing down). The assembly is then passed over a
"dual wave" soldering system. Note that the surfacemounted components are immersed into the molten solder.
Lead trimming will pose a problem after soldering in the
latter case, unless the leads of the insertion components
are pre-trimmed or the board specially designed to localize
certain areas for easy access to the trim blade.

The dangers of an inadequate cleaning cycle are:
• Ion contamination, where ionic residue left on boards
would cause corrosion to metallic components, affecting
the performance of the board.
• Electro-migration, where ionic residue and moisture present on electrically-biased boards would cause dentritic
growth between close spacing traces on the substrate,
resulting in failures (shorts).
REWORK
Should there be a need to replace a component or re-align
a previously disturbed component, a hot air system with appropriate orifice masking to protect surrounding components may be used.
When rework is necessary in the field, specially-designed
tweezers that thermally heat the component may be used to
remove it from its site. The replacement can be fluxed at the

The controls required for wave soldering are:
• Solder temperature to be 240-260"C. The dwell time of
components under molten solder to be short (preferably
kept under 2 seconds), to prevent damage to most components and semiconductor devices.
• RMA (Rosin Mildly Activated) flux or more aggressive OA
(Organic Acid) flux are applied by either dipping or foam
fluxing on boards prior to preheat and soldering. Cleaning
procedures are also more difficult (aqueous, when OA flux
is used), as the entire board has been treated by flux (unlike solder paste, which is more or less localized). Nonhalide OA fluxes are highly recommended.

Hot-Air Solder Rework Station

RETRACT POSITION

----c------_.
,
HEAT SHIELD

/'~B
-----

-:~;±~!~~B:O:AR:D:ON

• Preheating of boards is essential to reduce thermal shock
on components. Board should reach a temperature of
about 100·C just before entering the solder wave.

x-v TABLE

• Due to the closer lead spacings (0.050" vs 0.100" for
dual-in-line packages), bridging of traces by solder could
occur. The reduced clearance between packages also
causes "shadowing" of some areas, resulting in poor solder coverage. This is minimized bY'dual-wave solder systems.

HOTAIR-TL/F/8788-22

9·32

:I>

z

Mixed Surface Mount and Lead Insertion

J..

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Q

ADHESIVE

/\

~\L7dF=\
(b) Opposite Sides

(a) Same Side

tttt
PREHEAT

SOLDER FLOW
TUF/8766-24

A typical dual-wave system is illustrated below, showing the
various stages employed. The first wave typically is in turbulence and given a transverse motion (across the motion of
the board). This covers areas where "shadowing" occurs. A
second wave (usually a broad wave) then proceeds to perform the standard soldering. The departing edge from the
solder is such to reduce "icicles," and is still further reduced
by_an_air~!1j!~plac~d_cJo3!e_to_ttLe final sold_ering step. This_
air knife will blow off excess solder (still in the fluid stage)
which would otherwise cause shorts (bridging) and solder
bumps.

Dual Wave

AQUEOUS CLEANING
• For volume production, a conveyorized system is often
used with a heated recirculating spray wash (water temperature 130'C), a final spray rinse (water temperature
45-55'C), and a hot (120'C) air/air-knife drying section.
• For low-volume production, the above cleaning can be
done manually, using several water rinses/tanks. Fastdrying solvents, like alcohols that are miscible with water,
are sometimes used to help the drying process.
• Neutralizing agents which will react with the corrosive materials in the flux and produce material readily soluble in
water may be used; the choice depends on the type of flux
used.

TL/F/8766-25

CONFORMAL COATING
Conformal coating is recommended for high-reliability PCBs
to provide insulation resistance, as well as protection
against contamination and degradation by moisture.
Requirements:
o Complete coating over components and solder jOints.

• Final rinse water should be free from chemicals which are
introduced to maintain the biological purity of the water.
These materials, mostly chlorides, are detrimental to the
assemblies cleaned because they introduce a fresh
amount of ionizable material.

o Thixotropic material which will not flow under the pack-

ages or fill voids, otherwise will introduce stress on solder
jOints on expansion.
o Compatibility and possess excellent adhesion with PCB
material/components.
o Silicones are recommended where permissible in

application.

9·33

SMD Lab Support
Techniques-Develop techniques for handling different
materials and processes in surface mounting.
Equipment-In conjunction with equipment manufacturers,
develop customized equipments to handle high density,
new technology packages developed by National.
In-House Expertise-Availability of in-house expertise on
semiconductor research/development to assist users on
packaging queries.

FUNCTIONS
Demonstration-Introduce first-time users to surfacemounting processes.
Service-Investigate problems experienced by users on
surface mounting.
Reliability Builds-Assemble surface-mounted units for reliability data acquisition.

9-34

t;;'

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Land Pattern Recommendations

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The following land pattern recommendations are provided as guidelines for board layout and assembly purposes.
These recommendations cover the following National Semiconductor packages: PLCC, PQFP, SOP, SSOP and TSOP.

~

For SOT-23 (5-Lead) and TO-263 (3- or 5-Lead) packages, refer to land patterns shown in the Physical Dimensions for MA05A
and TS3B or TS5B packages, respectively.

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Body Body
Inner Pad
Outer Pad
Outer Pad
Land
Count
Size Size
to Tip
to Tip
Width
Pitch
to Pad Edge to Pad Edge to Pad Edge to Pad Edge Width
No.
(mm) (mm)
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
20

10.03

10.03

0.53

1.27

6.73

6.73

10.80

10.80

11.43 11.43

8.89

8.89

28

12.57

12.57

0.53

1.27

9.27

9.27

13.34

13.34

0.63

11.43 14.05

32

12.57

15.11

0.53

1.27

9.27

12.00

13.34

16.00

0.63

16.51 16.51

44

17.65

17.65

0.53

1.27

14.35

14.35

18.42

18.42

0.63

19.05 19.05

52

20.19

20.19

0.53

1.27

16.89

16.89

20.96

20.96

0.63

24.13 24.13

68

25.27

25.27

0.53

1.27

21.97

21.97

26.04

26.04

0.63

29.21 29.21

84

30.35

30.35

0.53

1.27

27.05

27.05

31.12

31.12

0.63

0.63

II
9-35

o ,---------------------------------------------------------------------------------,

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Inner Pad
Outer Pad
Land
Body Body Count Lead Tip Lead Tip Lead Lead/Pad
to Tip
Width
Pitch
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Size Size
to Tip
(mm) (mm)
No.
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)

7

7

40

9.29

9.29

0.26

0.50

7.50

7.50

9.78

9.78

0.30

7

7

48

9.40

9.40

0.27

0.50

6.88

6.90

10.42

10.40

0.32

10

10

44

13.35

13.35

0.45

0.80

10.53

10.53

14.47

14.47

0.55

10

10

52

14.15

14.15

0.38

0.65

9.08

9.08

15.17

15.17

0.43

12

12

64

14.00

14.00

0.38

0.65

11.48

11.48

15.02

15.02

0.43

14

14

80

18.15

18.15

0.38

0.65

13.08

13.08

19.17

19.17

0.43

14

20

80

17.80

23.80

0.35

0.80

13.50

19.50

18.50

24;50'

0.40

14

14

100

17.45

17.45

0.30

0.50

13.08

13.08

18.47

18.47

0.35

14.

20

100

17.80

23.80

0.30

0.65

13.50

19.50

18.50

24.50

0;35

20

20

100

24.30

18.30

0.40

0.65

21.28

15.28

25.32

19.32

0.45

24

24

132

24.21

24.21

0.30

0.64

21.67

21.67

25.23

25.23

·0.40

28

28

120

32.15

32.15

0.45

0.80

27.88

27.88

33.17

33.17

0.55

28

28

128

31.45

31.45

0.45

0.80

28.03

28.03

32.47

32.47

0.55

144

32.15

32.15

0.38

0.65

28.03

28.03

33.17

33.17

0.43

28

28

28

28

160

32.40

32.40

0.38

0.65

29.48

29.48

33.42

33.42

0.43

28

28

208

30.60

30.60

0.30

0.50

28.08

28.08

31.62

31.62

0.35

9·36

JEDEC Small Outline and Shrink Small Outline Packages (SOP and SSOP)

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(In)

Lead
Width
(In)

0.150

8

0.144

0.244

0.150

14

0.144

0.244

0.150

16

0.144

0.300

14

A

B
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to Pad Edge
(In)

X
Pad
Width
(In)

P
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Pitch
(In)

Inner Pad
to Pad Edge
(In)

0.020

0.050

0.094

0.294

0.028

0.020

0.050

0.094

0.294

0.028

0.244

0.020

0.050

0.094

0.294

0.028

0.3300

0.4100

0.0190

0.0500

0.2800

0.4600

0,0270
0.0270

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0.300

16

0.3300

0.4100

0.0190

0.0500

0.2800

0.4600

0.300

20

0.3300

0.4100

0.0190

0.0500

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0.4600

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24

0.3300

0.4100

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0.0500

0.2800

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28

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29

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0.025

0.145

0.281

0.014

0.150

24

0.185

0.241

0.010

0.025

0.145

0.281

0.014

0.300

48

0.340

0.420

0.012

0.025

0.300

0.460

0.016

0.300

56

0.340

0.420

0.012

0.025

0.300

0.460

0.016

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No.

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Size
(mm)

,(mm)

X
Pad
Width
(mm)

B
Outer Pad

A
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to Pad Edge
(mm)

to~adEdge

(mm)

SOP TYPE II

0.400

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1.270

5.010

9.270

0.600

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20 '

6.600 '

8.'100

0.400

0.650

5.584

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24

6.600

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0.650

5.584

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0.451

5.300

14

6.280

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5.300

16

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20

5.300
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SSOP TYPE III "

7.500

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1

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TSOPTYPEI

18.500 1

32

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1

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1

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9-38

7.884

17.984

1

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11.516

21.216

1

1

0.452

0.301

Section 10
Appendices/
Physical Dimensions

~-----

---------------------------1---

Section 10 Contents
Appendix A General Product Marking and Code Explanation .............................
Appendix B Device! Application Literature Cross-Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix D Military Aerospace Programs from National Semiconductor ...................
Appendix E Understanding Integrated Circuit Package Power Capabilities. . . . . . . . . . . . . . . . ..
Appendix F How to Get the Right Information from a Datasheet. . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . ..
Bookshelf
Distributors

10·2

10-3
10-4
10-10
10-20
10-25
10-29

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Appendix A
General Product Marking & Code Explanation
LF

11
356

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(Opti~"C)

I

Ceramic Leadless Chip Carrier (LCC)
GlasslMetal Flat Pak (%" x %")
G
12 Lead TO-8 Metal Can (MIG)
Multi-Lead Metal Can (MIG)
H
H-05
4 Lead M/C (TO-5) } Shipped with
H-46
4 Lead M/C (TO-46)
Thermal Shield
J
Lo-Temp Ceramic DIP
J-8
8 Lead Ceramic DIP ("MiniDIP")
J-14
14 Lead Ceramic DIP (-14 used only when
product is also available in -8 pkg).
TO-3 M/C in Steel, except LM309K
K
which is shipped in Aluminum
KC
TO-3 M/C (Aluminum)
K Steel TO-3 M/C (Steel)
M
Small Outline Package
M3
3-Lead Small Outline Package
M5
5-Lead Small Outline Package
Molded DIP (EPOXY B)
N
N-01
Molded DIP (Epoxy B) with Staggered Leads
N-8
8 Lead Molded DIP (Epoxy B) ("Mini-DIP")
N-14
14 Lead Molded DIP (Epoxy B)
(-14 used only when product is also
available in -8 pkg).
P
3 Lead TO-202 Power Pkg

Device Number (Generic Type)
and Suffix Letter (Optional)
Aor B: Improved
Electrical
Specification
C, I, E or M: Temperature
Range
Device Family (See Below)

Device Family
ADC
AF
AH
DAC
OM
I-tS
LF
LH
LM

Data Conversion
Active Filter
Analog Switch (Hybrid)
Data Conversion
Digital (Monolithic)
Hybrid
Linear (BI-FETTM)
Linear (Hybrid)
Linear (Monolithic)

LMD
LP
LPC
MF
LMF

Linear DMOS
Linear (Low Power) .
Linear CMOS (Low Power)
Linear (Monolithic Filter)
Linear Monolithic Filter

--~LM~C~---~----~Li~n-ea-r~CM()S-------------

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3,5,11, & 15 Lead TO-263 Surf. Mt. Power Pkg
3,5,11,15 & 23 Lead TO-220 PWR Pkg (EpoxY B)
Multi-lead Plastic Chip Carrier (PCC)
Lo-Temp Ceramic Flat Pak
Wide Body Small Outline Package
DATE CODE
1ST DIGIT - CALENDAR YEAR
2ND DIGIT - 6-WEEK PERIOD
IN CALENDAR YEAR
3RD &: 4TH DIGITS - WAFER LOT CODE

MILITARY- 883& M38510
1SU2ND DIGITS-CALENDAR YEAR
3RD & 4TH DIGITS - CALENDAR WORK WEEN
(EXAMPLE: 9201 = 1ST WEEK OF 1992)
MILITARY ONLY
ESD
(ELECTROSTATIC DISCHARGE)
SENSITIVITY INDICATOR

INDICATES PLANT
OF MANUFACTURE

LOGO
PART NUMBER
PIN 1 ORIENTATION

WAfER LOT
CODE

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DATE CODE
NON-MILITARY
2ND DIGIT - CALENDAR YEAR
3RD.!c4TH DIGITS-CALENDAR WORK WEEN

INDICATES PLANT
Of MANUfACTURE

iCI.
C

E
F

Package Type (See Right)

L -_ _ _ _ _ _ _

o

Package Type
o
GlasslMetal DIP

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TL/XX/OO27 -3
TL/XX/0027 -2

PIN 1 ORIENTATION

10-3

t!fINational Semiconductor

Appendix B
Devicel Application Literature· Cross-Reference
Application Literature

Device Number

ADCXXXX ...................................................•......•..•..•.........•..•..•..............•.AN-156
ADC80 ........ : •.................•..............................•..............................•..•......AN-360
ADC0801 ............................... ~ ............ : ........ AN-233, AN-271, AN-274, AN-280, AN-281, AN-294, LB-53
ADC0802 .................................................................... AN-233, AN-274, AN-280, AN-281, LB-53
ADC0803 ................. : ................................................. AN-233, AN-274, AN-280, AN-281, LB-53
ADC08031 ............................................................................•.........•..........AN-460
ADC0804 ............................................ AN-233, AN-274, AN-276, AN-280, AN-281, AN-301 , AN-460, LB-53
ADC0805 ................................................................... AN-233, AN-274, AN-280, AN-281, LB-53
ADC0808 ..................................................................................AN-247, AN-280, AN-281
ADC0809 .........................................................................................AN-247,AN-280
ADC0816 ...........................•............... , .............................. AN-193, AN-247, AN-258, AN-280
ADC0817 ..................................................................................AN-247, AN-258, AN-280
ADC0820 ........................................................................................•.....•...AN-237
ADC0831 ........ : ................................................................................AN-280,AN-281
ADC0832 ......... : .............. ~ ..... " ........................................................... AN-280, AN-281
ADC0833 ........................................... '.' ......•........•.......................•..... AN-280, AN-281
ADC0834 ...............................................................................•.....•..•.AN-280, AN-281
ADC0838 .........................................................................................AN-280,AN-281
ADC1001 .....................•.......................••...................................AN-276, AN-280, AN-281
ADC1005 ................................................................•..............••.•..•..•........AN-280
ADC10461 .......................................................•....•...................................AN-769
ADC10462 ..... .' .................•......•..•........•..••........•..•..•...........•..•................. '. :AN-769
ADC10464 ...............................•.................: ................................... .' .......... AN-769
ADC10662 ..................................................................................................AN-769
ADC10664 ...........................................•.....•..•.....•........... : ...........•............. AN-769
ADC12030 .................................................................. : .........................•... AN-929
ADC12032 ................................................................................................AN-929
ADC12034 ................................•.............................•.......................•.........AN-929
ADC12038 .•...........................•...............•.........•.•...........•............•.............AN-929
ADC12H030 ...............................................................................................AN-929
ADC12H032 ...............................................................................................AN-929
ADC12H034 ................................•...........................................•..•...............AN-929
ADC12H038 ................................................................................................AN-929
ADC12L030 ...............•....•.........•..•.•...•.......................................................AN-929
ADC12L032 ...........................................•................... ; ...................•........... AN-929
ADC12L034 ...........................................••....•...•••.....•.....•..•.....•..................AN-929
ADC12L038 ........................................•.........................•.......................•....AN-929
ADC1210 ..•...•.................•........•...............•......•....••...•......•.••..•....•......•..•..AN-245
ADC12441 ....•.....•..•..•.......•........•..•..•.....••.....•.......................•....•••.•..•..•....AN-769
ADC12451 ..................••.....•..•..•.••.••..••••.••..•..•........•...............•......•.......•.•.AN-769
DACXXXX .........•.............................•..•••..•.•••.•...•..•.•••.•...••••.•.....•........•......AN-156
DAC0800 ...........................•...........••.•.••.....••.....•.••.....•.•..••....•..•..•...•.••..•.•AN-693
DAC0830 •••.•..•...................•.....•...............•........•..•..•..•.............••.••....•.•.•.• AN-284
10-4

Device/ Application Literature Cross-Reference

(Continued)

Application Literature

Device Number

DAC0831 .........................................................................................AN-27l , AN-284
DAC0832 ............................................................•................•...........AN-27l, AN-284
DAC1006 .......................................................................... AN-27l, AN-275, AN-277, AN-284
DAC1007 .......................................................................... AN-27l, AN-275, AN-277, AN-284
DAC1008 ..........................................................................AN-27l, AN-275, AN-277, AN-284
DAC1020 ................................................................. AN-263, AN-269, AN-2293, AN-294, AN-299
DAC102l .................................................................................................AN-269
DAC1022 .................................................................................................AN-269
DAC1208 ......................................................................................... AN-27l , AN-284
DAC1209 ......................................................................................... AN-27l , AN-284
DAC12l0 ..................................................................•...................... AN-27l,AN-284
DAC12l8 .................................................................................................AN-293
DAC12l9 ................................. : ............................................................... AN-693
DAC1220 ....................................•....................................................AN-253, AN-269
DAC122l .................................................................................................AN-269
DAC1222 ..........................................................................•......................AN-269
DAC1230 .................................................................................•.•.............AN-284
DAC123l .............................................•..............•............................ AN-27l, AN-284
DAC1232 .........................................................................................AN-27l, AN-284
DAC1280 ............. .'...........................................................................AN-26l,AN-263
DH0034 ...................................................................................................AN-253
DH0035 ....................................................................................................AN-49
INS8070 ...................•..............................................................................AN-260
LFlll ..............................•.......................................................................LB-39
LF155 ............................................................................................AN-263,AN-447
LF198 ............................................................................................AN-245, AN-294
LF3ll .......................................................................................................AN-30l
LF347 ....................................... AN-256, AN-262, AN-263, AN-265, AN-266, AN-30l, AN-344, AN-447, LB-44
tF351 .........................................• AN-242, AN-263,-AN-266,AN.2Z1.-AN--215,AN~93,JI.N-447',)I,pp_elldix_C_ _ _ _ _ _ _
LF351 A ......•............................................................................................AN-240
LF351 B ........................................................•...............•......................Appendix D
LF353 .................... AN-256, AN-258, AN-262, AN-263, AN-266, AN-27l, AN-285, AN-293, AN-447, LB-44, Appendix D
LF356 ..................................................... AN-253, AN-258, AN-260, AN-263, AN-266, AN-27l, AN-272,
AN-275, AN-293, AN-294, AN-295, AN-30l, AN-447, AN-693
LF357 ......................................................................................AN-263,AN-447, LB-42
LF398 .................................•...........................•. AN-247, AN-258. AN-266, AN-294, AN-298, LB-45
LF4ll .............................................................................AN-294, AN-30l , AN-344, AN-447
LF4l2 .....................................................................AN-272, AN-299, AN-30l , AN-344, AN-447
LF441 ............................................................................................AN-30l,AN-447
LF13006 ..................................................................................................AN-344
LF13007 ..................................................................................................AN-344
LF1333l ..........................................................................................AN-294, AN-447
LH0002 .....................................................................AN-13, AN-227, AN-263, AN-272, AN-30l
LH0024 .................•..•............ : ..........•..............................•....................... AN-253
LH0032 ...........................................................................................AN-242, AN-253
LH0033 ....................................................................................AN-48, AN-227, AN-253
LH006S •••.•..•.••.••.•......•••.•......................•.•.............•...•............•................AN,-227
LH0070 ••.••••..••.•.••..••.•.••.••••.••..•.••••.•.••••••••••.•.•...•.•.•................................. AN-SOl
LH007l ••.••••••.••.•..••...•••.•..••••.•••.••.•..•..••.••..•........•.............•..•..........•........ AN-245
LH0094 .........••.•.....•..•....••.••.••••..••.••.•••.•...•.•........•.....•.•.......•.....•..........•.. AN-30l
LH010l ........................................•...•......•..•.............................................AN-261

10-5

,-----------------------------------------------------------------------------,

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Device!Application Literature Cross-Reference (Continued)

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,Device Number

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Application Literature

LH1605 ..........•............••............•........•..•......•.....•............•...................•...AN-343
LH2424 ..•..........•......................•.................................................•............AN-867
LM10 ...•........•......................... AN-211. AN-247. AN-258. AN-271. AN-288. AN-299. AN-300. AN-460. AN-693
LM11 .................•......•..........•..•.....•.•....•.........•........ AN-241. AN-242. AN-260. AN-266. AN-271
LM12 .................. : .........•.....•...••..•.....•..•....•.•......•......•..........•. AN-446. AN-693. AN-706

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LM101 .............•.........•. : ...................................... AN-4. AN-13. AN-20. AN-24. LB-42. Appendix A

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LM102 .•........................•....................................... AN-4. AN-13. AN-30. LB-1. LB-5. LB-6. LB-11
LM105 ......••...•....•.... ,...........•.....•............•....•..•............................ AN-23. AN-11 O. LB-3

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LM101A ..........•.....•. AN-29. AN-30. AN-31. AN-79. AN-241 AN-711. LB-1. LB-2. LB-4. LB-8. LB-14. LB-16. LB-19; LB-28
LM103 .............................•.....•.......•.................•............•....•.....•.......AN-110.LB-41

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LMt06 ......•.........•..........•...•.•....................•....•......•.............•........AN-41. LB-6. LB-12

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LM107 ........... ,....................................................... AN-20. AN-31. LB-1. LB-12. LB-19. Appendix A

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LM108 .•..•........•.........•...•.....•..•..•...... AN-29.AN-30, AN-31. AN-79. AN-211. AN-241. LB-14. LB-15. LB-21

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LM108A ......................................................................................,.AN-260. LB-15. LB-19

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LM109 ..............................................................................................AN-42.LB-15
LM109A .................................................................................................. : ... LB-15
LM110 .....•...............•......................................•.................................. LB-11. LB-42
LM111 ..... ~ .............................................................. AN-41. AN-103. LB-12. LB-16. LB-32; LB-39
LM112 •.... ; ........•..........................................................•........•..................LB-19
LM113 .••.....•....•........•..•..•...•..•...•.....••.........•....•...... AN-56. AN-110. LB-21. LB-24. LB-28. LB-37
LM117 .............•••...•..........•.••.......•....••..........•..........•. AN-178.AN-181. AN-182. LB-46. LB-47
LM117HV ............................................................................................ LB-46. LB-47
LM118 ...•....•..•.........•...................•...........•...•.....•....... LB-17. LB-19. LB-21. LB-23. Appendix A
LM119 ...•.....•..••....•....•..•......•........••..•..•..•..••...............•......................••...•LB-23
LM120 .....................................................................................................AN-182
LM121 .•........•....•....•..........•...........•...................•.....•. AN-79. AN-104. AN-184. AN-260. LB-22
LM121A .....................................................................................................LB-32
LM122 ................•.•..........• '..•...•.•....•.••.•......•..••.....•......•..•.........•........ AN-97. LB-38
LM125 ......................................................................................................AN·82
LM126 •..........•.•.. '.....................................................................................AN·82
,LM129 ..•.••...........•...•..........•........•.••............................... AN-173. AN-178. AN-262. AN-266
LM131 ......... ; ...... '.................................................................. AN-210. AN-460. Appendix D
LM131A ...... : .•....••..••.•........•...•...•..••..•...........•..•..••..•........•.......................AN-210
LM134 ........ ; ,,'.' .................................................................................. LB-41.AN-460
LM135' .: ......... : ........................................................ AN-225. AN-262. AN-292. AN-298. AN-460
LM137 ••....•..•...•..•..••..•.... :' ....•........••..•.••..•..••.•...•.........•.....................•...... LB-46
LM137HV ............. : .................................................................................... LB-46
LM138 ..... ;.' ... ' ........................................................................................... LB-46
LM139 ........... '........................................................................................... AN-74
LM143 •...........•..........•.....•......•...•.••........••.....•...••...•.................•..... AN-127.AN-271
LM148 ••.•..•• , ......••. , .•.•.. , •. , •...•...•.•...•.••..•.......... '" •... , •.... , •..... " ., .•...•.•.....•.• AN-260
LM150 .•.... ;' •..............•.......•...•..............................................................•..• LB-46
LM158 ......... '...........................................................................................AN-116
LM160 .....••.•..•...•..•...•.••.. , •.... " ., ....•..••.•.••.................. , .. , .. , ..•............•........ AN-87
LM161 ....•..•......•.....•...................' ..........................................•..•....... AN-87. AN-266
LM163 ...•••••.••..••..•...............•..................................................................AN-295
LM194 .....•.••.•.••..•...•.•....•..........•......................................................AN-222. LB-21
LM195 •....••.•.•.•..••..••••••••.••••••••.•••.••.••••••••..•.....••..••••..••.••.•••....••....•......•..• AN-110
LM199 •..•..•........•••..•..•..•••••..••.•.•••..•.••..•••••••••••.••.•••••••••.••.••.•..••••..••• AN-161.AN-260
LM199A ..•.••...•........•.........•...........••.........•..•..•..•..•..•.•...•.•....••..•..••..•.••..••AN-161
LM211 ••••...•.....•..........................•..•..•..•.....................................'...........•.. LB-39

10-6

DevicelApplication Literature Cross-Reference (Continued)
Device Number

Application Literature

LM231 ....................................•...............................................................AN-210
LM231A .......................................................•..•.................•.......•.............AN-210
LM235 ......................................................................................•.............AN-225
LM239 .....................................................................................................AN-74
LM25B .......................................•......................................•.......•....•......•.AN-116
LM260 .................................•.•.....................••..•.......•...............................AN-B7
LM261 .....................................................................................................AN-B7
LM34 ...........................................•.....................................................•...AN-460
LM35 .....................................................................................................AN-460
LM301A ................•..........................................•...•.... : .............. AN-17B, AN-1Bl, AN-222
LM30B ............................................................. AN-BB, AN-l B4, AN-272, LB-22, LB-2B, Appendix D
LM30BA .......................•.....••............................................•.................AN-225,LB-24
LM309 ............................................................................................AN-17B,AN-1B2
LM311 ..................... AN-41, AN-l03, AN-260, AN-263, AN-2BB, AN-294, AN-295, AN-307, LB-12, LB-16, LB-1B, LB-39
LM313 .......................................•............................•...............•...............AN-263
LM316 .............................................................•...•..................................AN-25B
LM317 .................•.....................................................•...............AN-17B, LB-35, LB-46
LM317H ..........................•.••.........................•............................................ LB-47
LM31B, .............................................................................................AN-299, LB-21
LM319 .................•......................•...........................................AN-B2B, AN-271 , AN-293
LM320 ......................................................•..........................................•..AN-2BB
LM321 ..................................................................................•..................LB-24
LM324 ............................................. AN-BB, AN-25B, AN-274, AN-2B4, AN-30l, LB-44, AB-25, Appendix C
LM329 .......................................................•............ AN-256, AN-263, AN-2B4, AN-295, AN-301
LM329B ...................•..............................................•..•.•........•...•.....•.•.....AN-225
LM330 ...........•..............................................•....•..•..•...•......••.•...•............AN-301
LM331 ................................ AN~21 0, AN-240, AN-265, AN-27B, AN-2B5, AN-311, LB-45, Appendix C, Appendix D
LM331A ............................•................................ '........................... AN-2l0,AppendixC
L.,.,t334_~~._.......................•.•.................................•.....••..............AN-242, AN-256, AN-2B4
LM335 ....
-:-.AN:225,-AN-263;AN~295
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LM336 ............................•...................... ' ....... ' ............. : .......... AN-202, AN-247, AN-li5B
LM337 .......................................•.............................................................LB-46
LM33B .•......................................•...................................................... LB-49, LB-51
LM339 .................•................................................................•..AN-74,AN-245, AN-274
LM340 .....................•................................................................•.•.•.AN-l 03, AN-l B2
LM340L. ................•...................................................'.............................. AN-256
LM342 .......................................•................•...•.......................................AN-28B
LM346 .........................................•...........•..............................•........AN-202, LB-54
LM34B .•.............................................................................................AN-202, LB-42
LM349 ..................................................................... ~ ...........................•... LB-42
LM35B ................................................. AN-116, AN-247, AN-271, AN-274, AN-2B4, AN-29B, Appendix C
LM35BA ...........•.•..............................................................................•..AppendixD
LM359 .............................................................................................AN-27B,AB-24
LM360 ..........................................••........................•.•...............•........•.....AN-B7
LM361 ..........•..............•......................•...................•...•....................AN-B7,AN-294
LM363 ..............•..........•.......................................•..................................AN-271
LM3BO .•.................................................•..............•.•......•.............•..•AN-69,AN-146
LM3B5 .........•............................•..........•..• AN-242, AN-256, AN-301, AN-344, AN-460, AN-693, AN-777
LM3B6 ... : .................................................................................................. LB-54
LM391 .....................................••...........•........•..............•••....•.. .' •..•...•..•...• AN-272
LM392 ............................•.....•..••..•..••.•...••..•..•.. ~ ...•..•.................•....• AN-274, AN-2B6
10-7

--- ---------

Devicel Application Literature Cross-Reference (Continued)
Device Number

Application Literature

LM393 ..............•............................................................. AN-271, AN-274, AN-293, AN-694
LM394 .............................•... : .................... AN-262, AN·263, AN-271, AN-293, AN-299, AN-311, LB-52
LM395 .............................................. AN-178, AN-181 , AN-262, AN-263, AN-266, AN-301 , AN-460, LB-28
LM399 .....................................................................................................AN-184
LM555 ...................•.........•................................................................AN.694, AB· 7
LM556 ................................................................. : .................................... AB-7
LM565 .................................................................... : ..........•............. AN-46, AN-146
LM566 ...................................................................... : .... : ......................... AN-146
LM604 .. .' .................................................................................................AN-460
LM628 ........................... : ................................................................ AN-693, AN·706
LM629 .................•......•......................................................•.... AN-693, AN-694, AN· 706
LM709 ....................•.........................................................................AN-24, AN-30
LM710 ............................ : .......................................... : ...................... AN-41, LB-12
LM725 .'.•.................•...............•................. '............................................... LB-22
LM741 ................... : ......... ~ ............................... .' ............... .' ....... : .. AN-79, LB-19, LB-22
LM833 .......•......•......................................................................................AN-346
LM1036 ........................•.............. : .......... .' ................................................ AN-390
LM1202: ......... : .........................................................................................AN-867
LM1203.••......••.••...................... : ............................................................... AN-861
LM1204 .•............. ·.•.......•................... ·...•................................................... AN-934
LM1458 ............................•......................................................................AN-116
LM1524 ...................•...•...................................................AN-272, AN-288, AN-292, AN-293
LM1558 ..............•.........•..•.......................................................................AN-116
LM1578A : .....: .............................................................................................AB-30
LM1823 .....................••.•................ , ........................................................... AN-391
LM1830 .... : .......................................................... : ................................•... AB-10
LM1865 .................................................... : ............................................... AN-390
LM1886 ..•......................•.•................. .' ......... ~ ..... : ...................................... AN·402
LM1889 ..... ' ............................................... '............................................... AN-402
LM1894 ......... : ......................................................................... AN-384, AN-386, AN·390
LM2419 ..................
. : •................•..............................................................AN·861
.
LM2577 ............................................................. : ............................. AN-776, AN·777
LM2876 ....•.................... : .... : ..............................................................•..... AN-898
LM2889 ........ : ..............•..•.....•........•............................................. : ... AN-391, AN-402
LM2907 ............ :· .... : .................................................................................AN-162
LM291.7 .. .'................................. : •............................................................. AN-162
LM2931 ..........................•.•.................... : .................................•................ AB-12
LM2931CT ................................................................... : ............................. AB-11
LM3045, .......................•..........................................................................AN-286
LM3046 ...............•....•.........................................................•............AN-146, AN-299
LM3089 ......................... : .......•...... : ..........•............................................... AN-147

LM~524 ......... : ................ : .. : .............................................. AN-272, AN-288, AN-292, AN-293

LM3525A .................................................................................................AN-694
~M3578A

...................................................................................................AB-30

LM3875 .................... .' ..............................................................................AN-898
LM3876 .......... : ..................•...•........•.................•......................................AN-898
LM3886 ........................................................................ : ........................... AN-898
LM3900 ........................ .' ...................................... AN-72, AN-263, AN-274, AN-278, LB-20, AB-24
LM3909 ....................................................................................................AN-154
LM3914 ......................... : .......... : : ...... : ......................................... AN-460, LB-48, AB-25
LM3915 ........................... .' .......................................................................AN-386
LM3999 . .'.........................•................................................................ .' ...... AN-161
10-8

Device! Application Literature Cross-Reference

(Continued)

Application Literature

Device Number

LM4250 .............................................................................................AN·88. LB·34
LM6181 ........................................................................................... AN·813. AN·840
LM7800 ...................................................................................................AN· 178
LM12454 .................................................................................. AN·90S. AN·947. AN·949
LM 12458 .................................................................................. AN·906. AN·947. AN·949
LM12H454 ................................................................................ AN·90S. AN·947. AN·949
LM12H458 ................................................................................ AN·906. AN·947. AN·949
LM12L458 ................................................................................. AN·90S. AN·947. AN·949
LM18293 .................................................................................................AN·706
LM78L 12 .................................................................................................AN· 146
LM78S40 .................................................................................................AN· 711
LMC555 .......................................................................................... AN·460. AN·828
LMC660 ..................................................................................................AN·856
LMC835 ..................................................................................................AN·435
LMC6044 ................................................................................. '.' .............. AN·856
LMC6062 .................................................................................................AN·856
LMC6082 .................................................................................................AN·856
LMC6484 .................................................................................................AN·856
LMD18200 ........................................................................................ AN·694. AN·B28
LMF40 ....................................................................................................AN·779
LMF60 ....................................................................................................AN·779
LMF90 ....................................................................................................AN·779
LMF100 ..................................................................................................AN·779
LMF3BO ..................................................................................................AN·779
LMF390 ..................................................................................................AN·779
LP324 ....................................................................................................AN·284
LP395 ....................................................................................................AN·460
LPC660 ...................................................................................................AN·B56
MF4 ....................... '~'-'" ................................... ,_..-'--"_"_"_.... '-' ............ ~,--,--.AN·77L __ _
MF5 ......................................................................................................AN·779
MF6 ......................................................................................................AN·779
MFB ......................................................................................................AN·779
MF10 .............................................................................................AN·307. AN·779
MM2716 ................................................................................................... LB·54
MM541 04 ...................................................................................AN·252. AN·287. LB·54
MM57110 .................................................................................................AN·3B2
MM74COO ..................................................................................................AN·88
MM74C02 ..................................................................................................AN·88
MM74C04 ..................................................................................................AN·88
MM74C948 ....................................................... .' ........................................ AN·193
MM74HC86 .......................................................................................AN·861.AN·867
MM74LS13B ................................................................................................ LB·54
MM53200 .................................................................................................AN·290
2N4339 ....................................................................................................AN·32

D
10·9

~ r-------------------------------~--~~--------------------------------------------------_.

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-Appendix D
Military Aerospace Programs
from National Semiconductor

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This appendix Is intended to provide a brief overView of
military products available from National Semiconductor, The process flows and catagorles shown below are
for general reference only. For further information and
availability, please contact the Customer Response
Center at 1-800-272-9959, MllitarylAerospace Marketing
group or your local sales office.

Process Flows
(Integrated Circuits)

National Semiconductor's Military/Aerospace Program is
founded on dedication to excellence. National- offers complete support across the broadest range of products with
the widest selection of qualification levels and screening
flows. These flows include:

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JANS

QML products processed to
MIL-I-38535 Level S or V for. Space
level applications.

JANB

QML products processed to
MIL-I-38535 Level B or Q for
Military applications.

SMD

QML products processed to a
Standard Microcircuit Drawing with
Table I Electricals controlled by
DESC.

883

QML products processed to
MIL-STD-883 Level B for Military
applications.

MLP

Products processed on the
Monitored Line (Program)
developed by the Air Force for
Space level applications.

-MIL

Similar to MIL-STD-883 with
exceptions noted on the Certificate
of Conformance.

MSP

Military Screening Products for _
initial release of advanced
products.

MCP

Commercial products processed in
a military assembly. Electrical
testing performed at 25°C, plus
minimum and maximum operating
temperature to commercial limits.

MCR

Commercial products processed in
a military assembly. Electrical
testing performed at 25°C to
commercial limits

MRP

Military Ruggedized Plastic ,
products processed to avionics
requirements.

MRR

Commercial Ruggedized plastic
product processed in a commercial
assembly with electrical testing at
25°C.

MPC

Commercial plastic products
processed in a commercial
assembly with electrical testing at
25°C.

c(

10-10

Description

_ QML: The purpose of the QML program, which is adNational offers both 883 Class Band 883 Class S prodministered by the Defense' Electronics Supply Center
uct. The screening requirements for both classes of prod(DESC)" is to provide the military community with stanuct are outlined in Table III.
dardized products that have been manufactured and
As with SMDs a manufacturer is allowed to use his standard electrical tests provided that all critical parameters
screened to the highest quality and reliability standards
in facilities that have been certified by the government.
are tested. Also, the electrical test parameters, test conTo achieve QML status, manufacturers must submit
ditions, test limits and test temperatures must be clearly
their facilities, quality procedures and design philosodocumented. At National Semiconductor, this information
phies to a thorough audit aimed at confirming their abiliis available via our Table I (formerly RETS, Reliability
ty to produce product to the highest design and quality
Electrical Test Specification Program). The Table I document is a complete description of the electrical tests perstandards. They must be listed on DESC's Qualified
formed and is controlled by our QA department. Individual
Manufacturer List (QML) before devices can be marked
and shipped as QML product.
copies are available upon request.
Two processing levels are specified within MIL-I-38535,
Some of National's products are produced on a flow simithe QML standard: Class S (typically specified for
lar to MIL-STD-883. These devices are screened to the
space and strategic applications) and Class B (used for
same stringent requirements as 883 product, but are
tactical missile, airborne, naval and ground systems).
marked as -MIL; specific reasons for prevention of comThe requirements for both classes are defined within
pliancy are clearly defined in the Certificate of ConformMIL-STD-883. National is one of the industry's leading
ance (C of C) shipped with the product.
suppliers of both classes.
_ Monitored Line Program (MLP): is a non JAN Level S
program developed by the Air Force. Monitored Line
- Standard Microcircuit Drawings (SMD)_ SMDs are issued to provide standardized versions of devices ofproduct usually provides the shortest cycle time, and is
fered under QML. MIL-STD-883 screening is coupled
acceptable for application in several space level programs. Lockheed Missiles and Space Company in Sunwith tightly controlled electrical test specifications that
allow a manufacturer to use his standard electrical
nyvale, California, under an Air Force contract, provides
"on-site" monitoring of product processing, and as aptests. Table I explains the marking of JAN devices, and
Table II outlines current marking requirements for QMLI
propriate, program management. Monitored Line orders
SMD devices. Copies of MIL-I-38535 and the QML can
generally do not allow "customizing", and most flows
be obtained from the Naval Publications and Forms
do not include quality conformance inspection. Drawing
Center (5801 Tabor Avenue, Philadelphia, PA 19120,
control is maintained by the Lockheed Company.
212/697-2179. A current listing of National's SMD of_ Military Screening Program (MSP): National's Military
Screening Program was developed to make screened
ferings can be obtained from our authorized distributors, our sales offices, our Customer Response Center
versions of advanced products such as gate arrays and
(Arlington, Texas, 817/468-6300), or from DESC.
microprocessors available more quickly. Through this
- MIL-STO-883_ Originally intended to establish uniform
program, screened product is made available for prototypes and breadboards prior to or during the QML activtest methods and procedures; MIL-STD-883 has also
ities. MSP products receive the 100% screening of Tabecome the general specification for n.o~-SMD milit.ary
product. MIL-STD-883 defines the minimum ~eqUlreble III, but are not subjected to Group C and D quality
ments for a device to be marked and advertised as
conformance testing. Other criteria such as electrical
-883-compliant.-Qesign--a~d -construction- ?riteria,do?u---- --testing anCfl9mperaturerange-wilnra:ry-depending-upon mentation controls, electncal and mechanical screening
individual device status and capability.
requirements, and quality control procedures are outlined in paragraph 1.1.2 of MIL-STD-883.

10-11

a3
z

~
oj
!!.
(/)

CD

3
oj

(;'
Q,

c

g
.,
-- - - - -

~

~:::I

r-----------------------------------------------------------------------------------------------,

"0

TABLE I. JAN S or B Part Marking

c

8

's

[

~

"ii

iz

-e
E

en
E
E
0)

e

Dei)

U

a

JAN
Package
Designation

Lead Finish
A = Solder Dipped
B = Tin Plate
C = Gold Plate
X = Any lead finish above
is acceptable

A
B
C
D

Device Package
(see Table II)

c

o

TABLE I·A. JAN Package Codes

~~8.!!.~/XXXXXyyy

-

Screening Level

E

S or B
Device Number on

F
G
H
I

Slash Sheet
- S l a s h Sheet Number
'-----For radiation hard devices
this slash is replaced by the
Radiation Hardness ,Assurance
Designator (M, D, R, or H of

J
K
L
M
N
P

t.tIL-I-38535)
'------t.tIL-t.t-38510
'-------------JAN Prefix
TUXX/0030-1

II)

e

Q

R
S
T
U
V
W
X
Y
Z
2
3

~

~

~

~

,~

"0
C

eI)

a.
c.

cC

Microcircuit Industry Description

14·pin %" x %" (Metal) Flatpak
14·pin 0/.." x %" (Metal) Flatpak
14·pin %" x %" Dual·ln·Line
, 14·pin %" x %" (Ceramic) Flatpak
16'pin %" x %" Dual·ln·Line
16·pin %" x %" (Metal or Ceramic) Flatpak
B·pin TO·99 Can or Header
10·pin %" x %" (Metal) Flatpak
1O·pin TO·1 00 Can or Header
24·pin Yz" x 1%" Dual·ln·Line
24·pin %" x %" Flatpak
24'pin %" x 1%" qual·ln·Line
12·pin TO·1 01 Can or Header
(Note 1)
B·pin %" x %" Dual·ln·Line
40·pin 3!te" X2Y16" Dual·ln·Line
20·pin %" x 1'1ft." Dual·ln·Line
20·pin %" x Yz" Flatpak
(Note 1)'
(Note 1)
1B·pin %" X10/1e" Dual·ln·Line
22'pin %" x 1Ye" Dual·ln·Line
(Note 1)
(Note 1)
(Note 1)
20·terminal 0.350" x 0.350" Chip Carrier
2B·terminal 0.450" x 0.450" Chip Carrier

Note 1: T~ese I~lters are assigned ,to packages by Individual detail specifications and may be assigned to different packages in different specifications.

10·12

»

TABLE II. Standard Military Drawing
(SMD) Marking

TABLE II·A. SMD Package Codes
SMD
Package
Designation

5962-~02MXA

t'~ no,,"

C
D
E
F

(Solder)

Package Codes
(see Table IIA)
Class Designator
M
MIL-STD-SS3
B or Q
Class B
S or V
Class C

=

l......--

.

,

H
I

X
y

Drawing Number -

P
2

Year of Issue

In

The n
and n_n can
be replaced by RHA

R

designations

s=
-<

~

(;
(II

"0
I»

n

CD

"'tI

(;
CD

ii1

Note 2: Th~se letlers are assigned to packages by individual detail specifi·
cations and may be assigned to different packages in different specifica-

= 10 krad
= 100 krad

>r

~

14-pin Flatpak
14-pinCDIP
16-pinCDIP
" 16-pin Flatpak
B-pin TO-99 Can
10-pin (Metal) Flatpak
1O-pin TO-l 00 Can
(Note 2)
(Note 2)
B-pinC DIP
20-pin LCC
20-PinDIP

G

=
=

Device Number

D
R

Microcircuit Industry Description

"0
"0
CD
::::II
C.

tions.

.-.
3(II

o
3
z

Federal Stock Class

-o·

TL/XX/OO30-2

I»

TABLE 111.100% Screening Requirements
ClassS

Screen

::::II

e.

Class B

Method

Reqmt

Method

Reqmt

1.

Wafer Lot Acceptance

5007

All Lots

2.

Nondestructive Bond Pull (Note 14)

2023

1000/0

3.

Internal Visual (Note 1)

2020, Condition A

1000/0

2010, Condition B

1000/0

4.

Stabilization Bake (Note 16)

1OOB, Condition C, Min
24 Hrs. Min

1000/0

1OOB, Cond"ition C; Min
24 Hrs. Min

1000/0

5.

Temperature Cycling (Note 2)

1010, Condition C

1000/0

1010, Condition C

1000/0

6.. -

Constant Acceleration

2001, Condition E Min
Y1 Orientation Only

1000/0

7.

Visual Inspection (Note 3)

8.

Particle Impact Noise Detection (PIND)

9.

-~

.-~~--

2001, Condition E Min
"y 1 Orientation Only

1000/0
2010, Con"dition A (Note 4)

1000/0

1000/0
1000/0

Serialization

(NoteS)

100,-0

10.

Interim (Pre-Bum-In) Electrical Parameters

Per Applicable Device
Specification (Note 13)

1000/0

Per Applicable Device
Specification (Note 6)

11.

Burn-In Test

1015
240 Hrs. @ 125'C Min
(Cond. F Not Allowed)

1000/0

1015
160 Hrs. ~ 125'C Min

12.

Interim (Post Burn-In)
Electrical Parameters

Per Applicable Device
Specification' (Note 3)

1000/0

10·13

~
3

n·
o

:

1000/0

::::II
C.
C

-..
n

o

TABLE III_ 100% Screening Requirements (Continued)

Method

Reqmt

1015; Test Condition A, C,
72 Hrs. @ 150'C Min
: (Cond. F Not Allowed)

100%

13.

Reverse Bias Burn-In (Note 7)

14.

Interim (Post-Burn-In) Electrical
Parameters

Per Applicable Device
Specification (Note 13)

15.

PDA Calculation

5% Parametric (Note 14),
3 % Functional

16.

Final Electrical Test (Note 15)
a) Static Tests
1) 25'C (Subgroup 1, Table I, 5(05)
2) Max & Min Rated Operating Temp.
(Subgroups 2, 3, Table I, 5005) i
b) Dynamic Tests or Functional Tests
1) 25"C (Subgroup 4 or 7)
2) Max and Min Rated Operating Temp.
(Subgroups 5 and 6 or B, Table I,
5005)
c) Switching Tests 25'C
(Subgroup 9, Table I, 5005)

Per Applicable Device
Specification

Seal Fine, Gross

1014

17.

",

ClaasS

Screen

100%
All Lots

ClassS

Method

Reqmt

Per Applicable Device
Specification

100%

5% Parametric (Note 14)

All Lots

Per Applicable Device
Specification
100%
100%

~

100%
100%

100%
100%

100%
100%

100%

100%

100%
(Note B)

lB.

Radiographic (Note 10)

2012 Two Views

100%

19.

Qualification or Quality Conformance,
Inspection Test Sample Selection

(Note 11)

Sarnp.

20.

External Visual (Note 12)

2009

100%

1014

(Note 11)

100%
(Note 9)

Samp.
100%

Note 1: Unless otherwise specified, at the manulacturer's option, test samples for Group B, bond strength (Method 5005) may be randomly selected prior )0 or
lollowing intemal visual (Method 5004), prior to sealing provided all other specification requirements are satislied (e.g., bond strength requirements Shall, apply to
.,:"
each inspection lot, bond 'Iallures shall be counted even II,the bond would have failed internal visual).
Note 2: For Class B devices, this test may be replaced with thermal shock Method lOll, Test Condition A, minimum.
Note 3: At the manulactur~~s option, vlsuallnspecllon lor catastrophlc,lailures may be conducted alter each of the thermal/mechanical screens, alter the
sequence or alter seal test. Catastrophic lailures are defined as missing leads, broken packages, or lids ofl.
Note 4: The PIND test may be performed In any sequence alter step 6 and prior to step 16. See MIL·I·38565 paragraph 40.6.3. ,
Note 5: Class S devices shall be serialized prior to Interim eleCtrical parameter measurements.
Note 6: When specHied, all devices shall be tested' lor Ihose parameters r~q~iring della Calculations.
Note 7: Reverse bias bum·in is a requirement only when specified in the applicable device specHication. The order 01 performing burn-in and reverse bias bum~n
may be inverted.
Note 8: For Class S devices, the seal iesl may be performed In any sequence between step 16 and step 19, but it shall be peilormed alter all sheering and 1~lng
operations on the terminals.
Note 9: For Class B devices, the fine and gross seal tests shall be performed separately or together in any sequence and order between step 6' and step 20 except ,
that thay shall be performed alter all shearing and lormlng operations on the terminals. When 100% seal screen cannof be performed alter shearing and lormlng
(e.g., Ilatpaks and chip camers) the seal screen shall be done 100% prior to thase operations and a sample test (LTPD ~ 5) shall be performed on each inspection
lot lollowing these operations. lithe sample,lails, 100% rescreening shall be required.
Note 10: The radiographic sCreen may be performed In any sequence alter stap 9.
Note 11: Samples shall be selected lor tes~ng In accordance with the'specific deViCe class and lot requirements 01 Method 5~05.
Note 12: Cxtema/ Visual shall be perlJrmed on the lot any time alter step 19' and prior to shipment.
Note 13: Read and record is required at steps 10 and 12 only lor those perameters lor which post·bum·ln delta measurements are speclfied. All parameters shall
be read and recorded at step 14.
Note 14: The PDA shell apply to all subgroup 1 parameters at25"C and all delta parameters.
Note 15: Only one view is required lor Ilat packages and leadless chip carriers wHh leads on all lour sides.
Note 16: May be performed at any time prior to step 10.

..

10-14

---=
l:o

'a
'a

Military Analog Products Available from National Semiconductor

(1)

Device

Package
Styles
(Note 1)

Description

::J

Process
Flows
(Note 2)

SMD/JAN
(Note 3)

LF44~M

LF444M
LHOO02
LH0021
LH0024
LH0032
LH0041
LH0101
LM10
LM101A
LM108A
LM118
LM124
LM124A
LM146
LM148
LM158A
LM158
LM611AM
LM613AM

D,J
H
H
H
H
H
H
H,J
H
H
D

Wide BW Quad JFET Op Amp
JFET Input Op Amp
JFET Input Op Amp
JFET Input Op Amp
JFET Input Op Amp
JFET Input Op Amp
Low Offset, Low Drift JFET Input
Low Offset, Low Drift JFET Input-Dual
Low Power JFET Input
LOw Power JFET Input-Dual
Low Power JFET Input-Quad

SMD/JAN
883
883
883
883
883
883/JAN
883/JAN
883
883
883

H

Buffer Amp
1.0 Amp Power Op Amp
High Slew Rate Op Amp
Ultra Fast FET-Input Op Amp
0.2 Amp Power Op Amp
PowerOpAmp

II-MIL"
"·MIL"

K
H
G
G

K

>C'

C

I

HIGH PERFORMANCE AMPLIFIERS AND BUFFERS
LF147
LF155A
LF156
LF156A
LF157
LF157A
LF411M
LF412M
LF441M

a.

"-MIL"
"-MIL"
"-MIL"
"-MIL"

H
J,H,W
J,H,W
J,H
J,E,W
J,E,W
J
J,E
J,H
J,H
J
J,E

Super-Block™ Micropower Op Amp/Ref
883/SMD
General Purpose Op Amp
883/JAN
Precision Op Amp
883/JAN
FastOpAmp
883/JAN
Low Power Quad Op Amp
883/JAN
Low Power Quad
883/JAN
Quad Programmable Op Amp
883
Quad 741 Opamp
883/JAN
Low Power Dual Op Amp
883/SMD
Low Power Dual Op Amp
883/SMD
883/SMD
Super-Block Op Amp/Reference
Super-Block Dual Op Amp/Dual Comp/Ref
883/SMD
~tM61-.tAM-- - ; 1 - - - - -Super-Block euad0p-Amp/Ret--- - - - -883/SMB
LM709A
H,J,W
General Purpose Op Amp
883/SMD
LM741
J,H,W
General Purpose Op Amp
883/JAN
General Purpose Dual Op Amp
883/JAN
LM747
J,H

111906

111904
111905

-

-

-

5962-87604

i!
;:::;:

...
III

'<

l:o

(1)
..,.

0

til

'a
III

n
(1)

"tJ
..,.

0

ca
..,.
III

3til

..,.
0

3

Z

III

0'
!!.
::J

110103
110104
110107
111005

en
(1)

/11006

::J

/11001
5962-8771002
5962-8771001

3

n'
0
a.

c

n

0..,.

-

7800701
/10101
/10102

LM6118
LM6121
LM6125
LM6161
LM6162
LM6164
LM6165
LM6181AM
LM6182AM

J,E
H,J
H
J,E,W
J,E,W
J,E,W
J,E,W
J
J

VIP Dual Op Amp
VIP Buffer
VIP Buffer with Error Flag
VIP Op Amp (Unity Gain)
VIP Op Amp (Av > 2, - 1)
VIP Op Amp (Av > 5)
VIP Op Amp (Av > 25)
VIP Current Feedback Op Amp
VIP Current Feedback Dual Op Amp

883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD

5962-91565
5962-90812
5962-90815
5962-89621
5962-92165
5962-89624
5962-89625
5962-9081802
5962-9460301

LMC660AM
LMC662AM
LPC660AM
LPC662AM
LMC6482AM
LMC6484AM

J
J
J
J
J
J

Low Power CMOS Quad Op Amp
Low Power CMOS Dual Op Amp
Micropower CMOS Quad Op Amp
Micropower CMOS Dual Op Amp
Rail to Rail CMOS Dual Op Amp
Rail to Rail CMOS Quad Op Amp

883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
663/SMD

5962-9209301
5962-9209401
5962-9209302
5962-9209402
5962-9453401
5962-9453402

OP07

H

Precision Op Amp

883

-

II
10-15

Military Analog Products Available from National Semiconductor (Continued)
Device

Package
Styles
(Note 1)

Description

Process
Flows
(Note 2)

SMD/JAN
(Note 3)

COMPARATORS
LF111
LH2111
LM106
LM111
LM119
LM139
LM139A
LM160
LM161
LM193
LM193A
LM612AM
LM613AM

H
J,W
H,W
J,H,E,W
J,H,E,W
J,E,W
J,E,W
J,H
J,H,W
J, H
J,H
J
J, E

LM615AM
LM710A*
LM711A*
LM760

J
J,H,W
J,H,W
J, H

Voltage Comparator
Dual Voltage Comparator
Voltage Comparator
Voltage Comparator
High Speed Dual Comparator
Quad Comparator
Precision Quad Comparator
High Speed Differential Comparator
High Speed Differential Comparator
Dual Comparator
Dual Comparator
Dual-Channel Comparator/Reference
Super-Block Dual Comparator/
Dual Op Amp/ Adj Reference
Quad Comparator/Adjustable Reference
Voltage Comparator
Dual LM710
High Speed Differential Comparator

"-MIL"
883/JAN
883/SMD
883/JAN
883/JAN
883/JAN
883/SMD
883/SMD
883/SMD
883
883/JAN
883/SMD
883/SMD

/10305
8003701
/10304
/10306
/11201
5962-87739
8767401
5962-87572

-

/11202
5962-93002
5962-93003

883
883/JAN
883/JAN
883/SMD

-

883/SMD
883/JAN
883/JAN
883/JAN
883/SMD
883/SMD
883
"-MIL"
883/JAN
883
883
883/JAN
883/JAN
883
883
883
883
883/JAN
883/JAN
883/JAN
883
883
883
883
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883
883/JAN
883/SMD
883/SMD

5962-89588
/10701BXA
/1 0701 BYA
/11703,/11704
7703402XA
7703402YA

/10301
/10302
5962-87545

"Formerly manufactured by Fairchild Semiconductor as part numbers I'A71 0 and I'A711.

LINEAR REGULATORS
Positive Voltage Regulators
LM105
LM109
LM109
LM117
LM117HV
LM117HV
LM123
LM138
LM140-5.0
LM140-6.0
LM140-8.0
LM140-12
LM140-15
LM140-24
LM140A-5.0
LM140A-12
LM140A-15
LM140K-5.0
LM140K-12
LM140K-15
LM140LAH-5.0
LM140LAH-12
LM140LAH-15
LM150
LM2940-5.0
LM2940-8.0
LM2940-12
LM2940-15
LM2941
LM431
LM723
LP2951
LP2953AM

H
H
K
H,E,K
H
K
K
K
H
H
H
H
H
H
K
K
K
K
K
K
H
H
H
K
K
K
K
K
K
H,K
H,J, E
H,E,J
J

Adjustable Voltage Regulator
5V Regulator, 10 = 20 mA
5V Regulator, 10 = 1A
Adjustable Regulator
Adjustable Regulator, 10 = 0.5A
Adjustable Regulator, 10 = 1.5A
3A Voltage Regulator
5A Adjustable Regulator
0.5A Fixed 5V Regulator
0.5A Fixed 6V Regulator
0.5A Fixed 8V Regulator
0.5A Fixed 12V Regulator
0.5A Fixed 15V Regulator
0.5A Fixed 24V Regulator
1.0A Fixed 5V Regulator
1.0A Fixed 12V Regulator
1.0A Fixed 15V Regulator
1.0A Fixed 5V Regulator
1.0A Fixed 12V Regulator
1.0A Fixed 15V Regulator
100 mA Fixed 5V Regulator
100 mA Fixed 12V Regulator
100 mA Fixed 15V Regulator
3A Adjustable Power Regulator
5V Low Dropout Regulator
8V Low Dropout Regulator
12V Low Dropout Regulator
15V Low Dropout Regulator
Adjustable Low Dropout Regulator
Adjustable Shunt Regulator
Precision Adjustable Regulator
Adjustable Micropower LDO
250 mA Adj. Micropower LDO

10-16

-

-/10702
-

-/10703
/10704

-

-

-/10706
/10707
/10708

-

5962-89587
5962-90883
5962-90884
5962-90885.
TBD

-

/10201
5962-38705
5962-9233601 .

»

"t::J
"t::J
CD

Military Analog Products Available from National Semiconductor (Continued)

Device

Package
Styles
(Note 1)

::l

Process
Flows
(Note 2)

Description

SMD/JAN
(Note 3)

a.

)C'

C

I

LINEAR REGULATORS (Continued)

~
;::;:

Negative Voltage Regulators
LM120-5.0
LM120-8.0
LM120-12
LM120-15

H
H
H
H

Fixed 0.5A Regulator,
Fixed 0.5A Regulator,
Fixed 0.5A Regulator,
Fixed 0.5A Regulator,

VOUT
VOUT
VOUT
VOUT

= -5V

= -15V

883/JAN
883
883/JAN
883/JAN

LM120-5.0
LM120-12
LM120-15

K
K
K

Fixed 1.0A Regulator, VOUT = -5V
Fixed 1.0A Regulator, VOUT = -12V
Fixed 1.0A Regulator, VOUT = -15V

883/JAN
883/JAN
883/JAN

/11505
/11506
/11507

LM137A
LM137A
LM137
LM137HV
LM137HV

H
K
H,K
H
K

Precision Adjustable Regulator
Precision Adjustable Regulator
Adjustable Regulator
Adjustable (High Voltage) Regulator
Adjustable (High Voltage) Regulator

883/SMD
883/SMD
883/JAN
883/SMD
883/SMD

7703406XA
7703406YA
/11803,/11804
7703404XA
7703404YA

LM145-5.0
LM145-5.2

K
K

Negative 3 Amp Regulator
Negative 3 Amp Regulator

883/SMD
883

5962-90645

= - 8V
= -12V

/11501

/11502
/11503

-

....

II)

'<

»
CD
....
0

0
"C

II)

n

CD

'1J
....
0
CQ
....
II)

30

....

0

3
Z

II)

SWITCHING REGULATORS
LM1575-5
LM1575-12
LM1575-15
LM1575-ADJ
LM1575HV-5
LM1575HV-12
LM1575HV-15
LM1575HV·ADJ
LM1577-12
LM1577-15
LM1577-ADJ

0'

J,
J,
J,
J,
K
K
K
K
K
·K
K

K
K
K
K

Simple Switcher™ Step·Down, VOUT = 5V
Simple Switcher Step·Down, VOUT = 12V
Simple Switcher Step·Down, VOUT = 15V
Simple Switcher Step·Down, Adj VOUT
Simple Switcher Step·Down, VOUT = 5V
Simple Switcher Step· Down, VOul' = 12V
Simple Switcher Step·Down, VOUT = 15V
Simple Switcher Step-Down, Adj VOUT
SimpleSwitcherStep·Up, VOUT = 12V
Simple Switcher Step·Up, VOUT = 15V
Simple Switcher Step·Up, Adj VOUT

883/SMD
883/SMD
883/SMD
883/SMD
883
883
883
883
883/SMD
883/SMD
883/SMD
883/SMD

5962-89586

883/SMD

5962-88761

883/SMD
883/SMD
883/SMD
883/SMD

7702806
7702807
7702808
7702809

Reference Diode with 5% Tolerance
Reference Diode with 1 % Tolerance
Reference Diode with 2% Tolerance

883/SMD
883/SMD
883/SMD

5962-8671101
5962-8671102
5962-8671103

Precision Reference, 10 ppm/'C Drift
Precision Reference, 20 ppm/'C Drift
2.5V Reference Diode, 1 % VOUT Tolerance
5V Reference Diode, 1 % VOUT Tolerance
2.5V Reference Diode, 2% VOUT Tolerance
5V Reference Diode, 2% VOUT Tolerance

883/SMD
883/SMD
883
883/SMD
883
883

5962-8992101XA
5962-8992102XA

LM1578

H

750 rnA S'liitching Regulator

LM78S40'

J

Universal Switching Regulator Subsystem

._--

5962-9167201
5962-9167301
5962-9167401
5962-9167101

::l

!!!.

en
CD

3

-

(i'
0

-

a.

-

5962-9216701
5962-9216801
5962-9216601

::l

c

n

0

....

'Formerly manufactured by Fairchild Semiconductor as the ,..A78S40DMQB.

VOLTAGE REFERENCES
LM103-3.0
LM103-3.3
LM103-3.6
LM103-3.9
LM113
LM113-1
LM113-2
LM129A
LM129B
LM136A-2;5
LM136A-5.0
LM136-2.5
LM136-5.0

H
H
H
H
H
H
H
H
H
H

H
H
H

Reference Diode,
Reference Diode,
Reference Diode,
Reference Diode,

BV
BV
BV
BV

= 3.0V
= 3.3V
= 3.6V .
= 3.9V

8418001

-

-

III
10-17

Military Analog Products Available from National Semiconductor (Continued)

Device

Package
Styles
(Note 1)

Description

Process
Flows
(Note 2)

10V Precision Reference, Low Tempco 0.05% Tolerance
Adjustable Micropower Voltage Reference
2.5V Micropower Reference Diode, Ultralow Drift
Adjustable Micropower Voltage Reference
1.2V Micropower Reference Diode, Low Drift
2.5V Micropower Reference Diode, Low Drift
1.2V Micropower Reference Diode, Low Drift
2.5V Micropower Reference Diode, Low Drift
Precision Reference, Low Tempco
Precision Reference, UltralowTempco
Precision Reference, Ultralow Tempco
Super-Block Op Amp/Reference
Super-Block Dual-Channel Comparator/Reference
Super-Block Dual Op Amp/DuaIComp/Dual Ref
Super-Block Quad Op Amp/Reference
Super-Block Quad Comparator/Reference
Precision BCD Buffered Reference
Precision BCD Buffered Reference
Precision BCD Buffered Reference

883
883/SMD
883/SMD
883
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883
883
883/SMD
883/SMD
883/SMD
883/SMD
"-MIL"
"-MIL"
"-MIL"

8-Bit p'p-Compatible
8-Bit Analog Data Acquisition
& Monitoring System
8-Bit Analog Data Acquisition
& Monitoring System
8-Bit Multistep ADC
1O-Bit Multistep ADC
10-Bit Multistep ADC w/Dual
Input Mutiplexer
10-Bit Multistep ADC w/Quad
Input Multiplexer
12-Bit Plus Sign Self-Calibrating
with Sample/Hold Function
Dynamically-Tested ADC1241
12-Bit Plus Sign Self-Calibrating
with Sample/Hold Function
Dynamically-Tested ADC1251
Quad 8-Bit D/A Converter
with Read Back
Quad 10-Bit D/ A Converter
with Read Back
12-Bit Data Acquisition System
12-Bit Data Acquisition System

883/SMD
883/SMD

5962-90966
TBD

883/SMD

TBD

883/SMD
883/SMD
883/SMD

TBD
TBD
TBD

883/SMD

TBD

883/SMD

5962-9157801

883/SMD
883/SMD

5962-9157802
5962-9157801

883/SMD
883/SMD

TBD
TBD

883/SMD

TBD

883/SMD
883/SMD

5962-9319501
5962-9319502

SMD/JAN
(Note 3)

VOLTAGE REFERENCES (Continued)
LM169
LM185B
LM185BX2.5
LM185BY
LM185BY1.2
LM185BY2.5
LM185-1.2
LM185-2.5
LM199
LM199A
LM199A-20
LM611AM
LM612AM
LM613AM
LM614AM
LM615AM
LH0070-0
LH0070-1
LH0070-2

H
H,E
H
H
H
H
H,E
H,E
H
H
H
J

J
J, E
J
J
H
H
H

-.

' ;,

5962-9041401
5962-8759404

5962-8759405
5962-8759406
5962-8759401
5962-8759402
5962-8856102
5962-8856101

-

-

,

5962-9300201
5962-9300301
5962-9300401
TBD

-

DATA ACQUISITION
ADC08020L
ADC0851

J
J

ADC0858

J

ADC08061CM
ADC10061CM
ADC10062CM

J
J
J

ADC10064CM

J

ADC1241CM

J

ADC12441CM
ADC1251CM

J
J

ADC12451CM
DAC0854CM

J
J

DAC1054CM

J

LM12458M
LM12H458M

EL,W
EL,W

10-18

):.
"C
"C
CD

Military Analog Products Available from National Semiconductor (Continued)
Package
Styles
(Note 1)

Device

Description

Process
Flows
(Note 2)

SMD/JAN
(Note 3)

BB3/SMD
BB3/SMD
BB3/SMD
BB3/SMD

5962-90967
5962-90967
5962-9096B
5962-9153301

DATA ACQUISITION SUPPORT
Switched Capacitor Flit rs
LMF60CMJ50
LMF60CMJ100
LMF90CM
LMF100A
Sample and Hold
LF19B
Motion Control
LMD1B200-2

6th Order Butterworth Lowpass
6th Order Butterworth Lowpass
4th Order Elliptic Notch
Dual 2nd Order General Purpose

J
J
J
J,E

:s

CL

;C'

~
s:
-<
it'

a
(II

"C
I»

I
I

H

0

I
I

Monolithic Sample and Hold

Dua13A, 55V H-Bridge

I
I

SMD/JA

BB3/JAN

I
I

5962-B760B
/12501
5962-9232501

Nole 1: D: Side·Brazed DIP
Nole 2: Process Flows
E: Leadless Ceramic Chip Carrier
JAN - JM3B5tO, Level B
G: Metal Can (TO-B)
SMD = Standard Milnary Drawing
H: Metal Can (TO·39, TO·5, TO·99, TO·t 00)
BB3 = MIL·STD-8B3 Rev C
J: Ceramic DIP
·MI L = Exceptions to BB3C noted on
K: Metal Can (T0-3)
Carlifieate of Conformance
W: Flatpak
Note 3: Please call your local sales ollice to determine price and availability of space·level products. All "LM" prefix products in this guide are availble with space·
level processing.

n

CD

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a

co
iil
3
(II

-

a3
z

a0'
:s

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(J)

CD

3

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c
g
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CL

10-19

II)

CI)

~

8.
ca

o

A,(lNational Semiconductor

VI'

l-

i

Appendix E
Understanding Integrated Circuit
Package Power Capabilities

a.
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-e

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i:3

1:1

~

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c
=sc

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CI)

1:1
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W
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=sc
CI)

c..
c..

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:g
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CD

a.

Q.

c(

DETERMINING DEVICE OPERATING
JUNCTION TEMPERATURE

The slope of the straight line between these two points is
minus the inversion of the thermal resistance. This is referred to as the derating factor.
, 1
Derating Factor = - a-"JA
As mentioned, Figure 5 is a plot of the safe thermal operating area for a device in a 16-pin molded'DIP. As long as the
intersection of a vertical line defining the maximum ambient
temperature (70'C in our previous example) and maximum
device package power (600 mW) remains below the maximum package thermal capability line the junction temperature will remain below 150'C-the limit for a molded package. If the intersection of ambient temperature and package
power fails on this line, the maximum junction temperature
will be 150'C. Any intersection that occurs above this line
will result in a junction temperature in excess of 150'C and
is not an appropriate operating condition.

From the above equation the method of determining actual
worst-case device operating junction temperature becomes
straightforward. Given a package thermal characteristic,
liJA, worst-case ambient operating temperature, T A(max),
the only unknown parameter is device power dissipation,
PD. In calculating this parameter, the dissipation of the integrated circuit due -to _its own supply has to be considered,
the dissipation within the package due to the external load
must also be added. The power associated with the load in
a dynamic (switching) situation must also be considered.
For example, the power associated with an inductor or a
capacitor in a static versus dynamic (say, 1 MHz) condition
is significantly different.
The junction temperature of a device with a total package
power of 600 mW at 70'C in a package with a thermal resistance of 63'C/W is 10S'C.
TJ = 70'C

+ (63'C/W) x

2.4

(0.6W) = 10S'C

The next obvious question is, "how safe is 10S'C?"

~

MAl(IMUM AL,LOWABLE JUNCTION TEMPERATURES

z

~

What is an acceptable maximum operating junction temperature is in itself somewhat of a difficult question to answer.
Many companies have established their own standards
based on corporate policy. However, the semiconductor industry has developed some defacto standards based on the
device package type. These have been well accepted as
numbers that relate to reasonable (acceptable) device lifetimes, thus failure rates.

I

1.2

~

THERMAL CAPABILITY

,=:=:!:Y-=--~;LlNE

t---'-

I--

O~~~NG~~ SLO~=--L
I

"

8JA-

0.8 1'D=600nM
I'
0.4 OPERATlNG_"fI-_-t:-_~~~+-i

POINT TA=70'C,_+I'~~_-I

O~~I~~_~I~_~~~

25

50

75

100 125

150

175

TEMPERATURE I'C)
TUH/9312-5

FIGURE 5. Package Power Capability
vs Temperature
The thermal capabilities of all integrated circuits are expressed as a power capability at 25'C still air environment
with a given derating factor. This simply states, for every
degree of ambient temperature rise above 25'C, reduce the
package power capability stated by the derating factor
which is expressed in mW/'C. For our example-a liJA of
63'C/W relates to a derating factor of 15.9 mW/'C.

Let us use this new information and our thermal equation to
construct a graph which displays the safe thermal (power)
operating area for a given package type. Figure 5 is an example of such a graph. The end points of this graph are
easily determined. For a: 16-pin-molded package, the maximum allowable temperature is 150'C; at this point no power
dissipation is allowable. The power capability at 25'C is
1.9SW as given by the following calculation:

@

1.6

a::

National Semiconductor has adopted these industry-wide
standards. For devices fabricated in a molded package, the
maximum allowable junction temperature is 150'C. For
these devices assembled in ceramic or cavity DIP packages, the maximum allowable junction temperature is
175'C. The numbers are different because of the differences in package types. The thermal strain associated with the
die package interface in a cavity package is much less than
that exhibited in a molded package where the integrated
circuit chip is in direct contact with the package material.

PD

2.0 1iL-;---t---t-'--t----1!---t
I'
MAXIMUM PACiwE I - -

a;

I

I
16.~'N
I--t-+-~I- MOLfED PACKAGE

FACTORS INFLUENCING PACKAGE
THERMAL RESISTANCE
As discussed earlier, improving any portion of the two primary thermal flow paths will result in an improvement in
overall thermal resistance junction· to-ambient. This section
discusses those components of thermal resistance that can
be influenced by the manufacturer of the integrated circuit. It
also discusses those factors in the overall thermal resistance that can be impacted by the end user of the integrated
circuit. Understanding these issues will go a long way in
understanding chip power capabilities and what can be
done to insure the best possible operating conditions and,
thus, best overall reliability.

, - TJ(max)-TA _ 150'C-25'C _ 19 W
25 C liJA
63'C/W - . S

10-22

Die Size
Figure 6 shows a graph of our 16-pin DIP thermal resistance
as a function of integrated circuit die size. Clearly, as the
chip size increases the thermal resistance decreases-this
relates directly to having a larger area with which to dissipate a given power.

110
w

~i

"'2

~"li

100

~i
~~!ii

80

mEa

70

!I::!.

60

-,co;l:
cto:" ....
2z ..

7~

""

TL/H/9312-B

FIGURE 8. Thermal Resistance vs
Board or Socket Mount
AirFlow
When a high power situation exists and the ambient temperature cannot be reduced, the next best thing is to provide air
flow in the vicinity of the package. The graph of Figure 9
illustrates the impact this has on thermal resistance. This
graph plots the relative reduction in thermal resistance normalized to the still air condition for our 16·pin molded DIP.
The thermal ratings on National Semiconductor's interface
circuits data sheets relate to the still air environment.

TUH/9312-6

Lead Frame Material

Figure 7 shows the influence of lead frame material (both
die attach and device pins) on thermal resistance. This
graph compares our same 16-pin DIP with a copper lead
frame, a Kovar lead frame, and finally an Alloy 42 type lead
frame-these are lead frame materials commonly used in
the industry. Obviously the thermal conductivity of the lead
frame material has a significant impact in' package power
capability. Molded interface circuits from National Semiconductor use the copper lead frame exclusively.
170

130

~~~

J:::!'

;;! 0.9
2

ffi

.....

-

--~I-~-~----90
70
50
1

1.0

II:

Iii-PIN MOLDED DIP

;;!~ iI 110

7~

~ 1.1

'"
==
i3

~BOARD MOUNT-STILL AIR

:EzC)

i'~

roo.

FIGURE 6. Thermal Resistance vs Die Size

!!! iii

~OCKET

2
3 4 5 678910
DIE SIZE (kMIL2)

2
3 4 5 6 78910
DIE SIZE (kMIL2)

~i

70

r--.~

50

150

..

~ t-.... ....r-...

60

......

""

~-

80

7~
.;; ~

!:!iii

~

90

;;!~~
2Z ..
ffi S! 0
=1:;

w

90

100

!:!iii

i!E

0.8

~

0.7

I I I 11~p1N

~

I'"I'i'

.

A~
KpVAR

_ _ ___ _ _ _

DIE

flZF

lk MIL2

.,....
III

Jki.J2

2

g;

0.6
z
I
q: 0.5

MOLDED~C~E

o

500
1000
AIR FLOW (UNEAR FEET/MINUTE)

._..

--JLLH~3~

FIGURE 9. Thermal Resistance vs Air Flow

~

Other Factors
A number of other factors influence thermal resistance. The
most important of these is using thermal epoxy in mounting
ICs to the PC board and heat sinks. Generally these techniques are required only in the very highest of power appli·
cations.
Some confusion exists between the difference in thermal
resistance junction·to-ambient (IIJA) and thermal resistance
junction-to-case (IIJcl. The best measure of actual junction
temperature is the junction·to-ambient number since nearly
all systems operate in an open air environment. The only
Situation where thermal resistance junction-to-case is important is when the entire system is immersed in a thermal bath
and the environmental temperature is indeed the case temperature. This is only used in extreme cases and is the exception to the rule and, for this reason, is not addressed in
this application note.

2
3 4 5 678910
DIE SIZE (kMIL2)
TL/H/9312-7

FIGURE 7. Thermal Resistance vs
Lead Frame Material
Board vs Socket Mount
One of the major paths of dissipating energy generated by
the integrated circuit is through the device leads. As a result
of this, the graph of Figure 8 comes as no surprise. This
compares the thermal resistance of our 16-pin package soldered into a printed circuit board (board mount) compared
to the same package placed in a socket (socket mount).
Adding a socket in the path between the PC board and the
device adds another stage in the thermal flow path, thus
increasing the overall thermal resistance. The thermal capabilities of National Semiconductor's interface circuits are
specified assuming board mount conditions. If the devices
are placed in a socket the thermal capabilities should be
reduced by approximately 5% to 10%.

NATIONAL SEMICONDUCTOR
PACKAGE CAPABILITIES

Figures 10 and 11 show compOSite plots of the thermal
characteristics of the most common package types in the
National Semiconductor Linear Circuits product family. Figure 10 is a compOSite of the 'copper lead frame molded

10-23

_ _ _. _ .

package. Figure 11 is a composite of the ceramic (cavity)
DIP using poly die attach. These graphs represent board
mount still air thermal capabilities. Another, and final, thermal resistance trend will be noticed in these graphs. As the
number of device pins increase in a DIP the thermal resistance decreases. Referring back to the thermal flow chart,
this trend should, by now, be obvious.

The package power ratings are specified as a maximum
power at 25'C ambient with an associated derating factor
for ambient temperatures above 25·C. It is easy to determine the power capability at an elevated temperature. The
power specified at 25'C should be reduced by the derating
factor for every degree of ambient temperature above 25'C.
For example, in a given product data sheet the following will
be found:
Maximum Power Dissipation' at 25'C
Cavity Package
1509 mW
Molded Package 1476 mW

RATINGS ON INTEGRATED CIRCUITS DATA SHEETS
In conclusion, all National Semiconductor Linear Products
define power dissipation (thermal) capability. This information can be found in the Absolute Maximum Ratings section
of the data sheet. The thermal information shown in this
application note represents average data for characterization of the indicated package. Actual thermal resistance can
vary from ± 10% to ±15% due to fluctuations in assembly
quality, die shape, die thickness, distribution of heat sources
on the die, etc. The numbers quoted in the linear data
sheets reflect a 15% safety margin from the average numbers found in this application note. Insuring that total package power remains under a specified level will guarantee
that the maximum junction temperature will not exceed the
package maximum.

• Derate cavity package at 10 mW/'C above 2S'C; derate molded package
at 11.8 mW/'C above 2S'C.

If the molded package is used at a maximum ambient temperature of 70'C, the package power capability is 945 mW.
PD@70'C=1476mW-(11.8mW/'C)X(70'C-25'C)
= 945mW

Cavity (J Package) DIP'
Poly Die Attach Board
Mount-Still Air
140 ....----,r---r-"""T-T--r-r-r-n

Molded (N Package) DIp·
Copper Leadframe-HTP
Die Attach Board MountStill Air

~-

120

!i ii

100

!i
~~5

~~~

I-=~=+-t-++I+H

80

~~,

60 I--+....,t.l+,,,"

~':2.

40

1----j::...!:!.{•• -~8-4IbI-I+H

20

L - _......._....L.......L.....L....l....L..Io..U

7~

3

4 5 6 78910

DIE SIZE (kMIL2)
'Packages from 8- to 20-pin 0.3 mil width

30 f--"c...:=.-¥-... ·,~.-l!8-40-4iil+'H

TUH/9312-11

22-pin 0.4 mil width

10 '-_-'----''-'--'-'-J....LJU
3 4 5 6 7 8 910
1
DIE SIZE (kMIL21
'Packages from 8· to 20-pin 0.3 mil width

24- to 48-pin 0.6 mil width

FIGURE 11. Thermal Resistance vs Die Size
vs Package Type (Cavity Package)

TL/H/9312-10

22·pin 0.4 mil width

TO-263 (5 Package)
Board Mount, Still Air

24- to 40·pin 0.6 mil width

FIGURE 10. Thermal ResIstance vs Die SIze
vs Package Type (Molded Package)

80

;;......
u
~

Surface Mount (M, MW Packages),
Board Mount, StilI AIr
180

..........

160

;;......
u

~

140
120

«

3A), thermal resistance may be
lower. Consult product datasheet for more information.
lOOk

FIGURE 13. Thermal Resistance (typ. ') for 3-, 5-,
and 7-L TO-263 packages mounted on 1 oz.
(O.036mm) PC board foil

TUH/9312-12

FIGURE 12. Thermal Resistance for "SO" Packages
(Board Mount)

10-24

t!lNational Semiconductor

APPENDIX F
How io Get the Right Information From a Data Sheet
Not All Data Sheets Are Created Alike, and False Assumptions Could Cost an Engineer Time and Money

By Robert A. Pease
When a new product arrives in the marketplace, it hopefully
will have a good, clear data sheet with it.

Every year, for the last 20 years, manufacturers have been
trying to explain, with varying success, why they do not measure the Zin per se, even though they do guarantee it.
In other cases, the manufacturer may specify a test that can
be made only on the die as it is probed on the wafer, but
cannot be tested after the die is packaged because that
Signal is not accessible any longer. To avoid frustrating and
confusing the customer, some manufacturers are establishing two classes of guaranteed specifications:

The data sheet can show the prospective user how to apply
the device, what performance specifications are guaranteed
and various typical applications and characteristics. If the
data-sheet writer has done a good job, the user can decide
if the product will be valuable to him, exactly how well it will
be of use to him and what precautions to take to avoid
problems.

o The tested limit represents a test that cannot be doubted, one that is actually performed directly on 100 percent
of the devices, 100 percent of the time.
o The design limit covers other tests that may be indirect,
implicit or simply guaranteed by the inherent design of
the device, and is unlikely to cause a failure rate (on that
test), even as high as one part per thousand.

SPECIFICATIONS

The most important area of a data sheet specifies the characteristics that are guaranteed-and the test conditions that
apply when the tests are done. Ideally, all specifications that
the users will need will be spelled out clearly. If the product
is similar to existing products, one can expect the data
sheet to have a format similar to other devices.

Why was this distinction made? Not just because customers
wanted to know which specifications were guaranteed by
testing, but because the quality-assurance group insisted
that it was essential to separate the tested guarantees from
the design limits so that the AQL (assurance-quality level)
could be improved from 0.1 percent to down below
100 ppm.

But, if there are significant changes and improvements that
nobody has seen before, then the writer must clarify what is
meant by each specification: Definitions of new phrases or
characteristics may even have to be added as an appendix.
For example, when fast-settling operational amplifiers were
first introduced, some manufacturers defined settling time
as the time after slewing before the output finally enters and
stays within the error-band; but other manufacturers includedthe~slewing~time-in-their-definition. Because both groups ___ ~
made their definitions clear, the user was unlikely to be confused or misled.
However, the reader ought to be on the alert. In a few cases, the data-sheet writer is playing a specsmanship game,
and is trying to show an inferior (to some users) aspect of a
product in a light that makes it lool~ superior (which it may
be, to a couple of users).
GUARANTEES
When a data sheet- specifies a guaranteed minimum value,
what does it mean? An assumption might be made that the
manufacturer has actually tested that specification and has
great confidence that no part could fail that test and still be
shipped. Yet that is not always the case.
For instance, in the early days of op amps (20 years ago),
the differential-input impedance might have been guaranteed at 1 Mfi-but the manufacturer obviously did not measure the impedance. When a customer insisted, "I have to
know how you measure this impedance," it had to be explained that the impedance was not measured, but that the
base current was. The correlation between Ib and Zin permitted the substitution of this simple dc test for a rather
messy, noisy, hard-to-interpret test.

Some data sheets guarantee characteristics that are quite
expensive and difficult to test (even harder than noise) such
as long-term drift- (20 ppmor50 ppm over 1,000 hOllfSj'-.--~I-----The data sheet may not tell the reader if it is measured,
tested or estimated. One manufacturer may perform a 100percent test, while another states, "Guaranteed by sample
testing." This is not a very comforting assurance that a part
is good, especially in a critical case where only a long-term
test can prove if the device did meet the manufacturer's
specification. If in doubt, question the manufacturer.
TYPICALS

Next to a guaranteed specification, there is likely to be an, other in a column labeled "typical".
It might mean that the manufacturer once actually saw one
part as good as that. It could indicate that half the parts are
better than that specification, and half will be worse. But it is
equally likely to mean that, five years ago, half the parts
were better and half worse. It could easily signify that a few
parts might be slightly better, and a few parts a lot worse;
after all, if the noise of an amplifier is extremely close to the
theoretical limit, one cannot expect to find any1hing much
better than that, but there will always be a few noisy ones.
If the specification of interest happens to be the bias current
(lb) of an op amp, a user can expect broad variations. For
example, if the specification is 200 'nA maximum, there
might be many parts where Ib is 40 nA on one batch (where
the beta is high), and a month later, many parts where the Ib
is 140 nA when the beta is low.

Reprinted by permission from Electronic Engineering Times.

10-25

Absolute Maximum Ratings (Note 11)
Lead Temp. (Soldering, 4 seconds)
TO-46 Package

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
+35Vto -0.2V
+6Vto -1.0V
Output Voltage
Output Current
Storage Temperature,
T0-46 Package

+3'oO"C

TO-92 Package

+ 260'C

Specified Operating Temp. Range (Note 2)

10mA
-76'Fto +356'F

TO-92 Package

*

LM34, LM34A
LM34C, LM34CA

TMINtoTMAX
-50'Fto +300"F
-40'Fto+230'F

LM34D

+ 32'F to + 212'F

- 76'F to + 300'F

DC Electrical Characteristics (Note 1, Note 6)
LM34A
Parameter

Accuracy (Note 7)

Nonlinearity (Note 8)
Sensor Gain
(Average Slope)

Conditions

= +77'F
= O'F
= TMAX
= TMIN
TMIN s: TA s: TMAX
TMIN s: TA s: JMAX
TA = +77'F
TMIN s: TA s: TMAX
OS: IL s: 1 rnA

Line Regulation (Note 3)

TA
5V

Quiescent Current
(Note 9)

Change of Quiescent
Current (Note 3)

Typical
±0.4
±0.6
±0.8
±0.8

TA
TA
TA
TA

Load Regulation
(Note 3)

Temperature Coefficient
of Quiescent Current
In circuit of Figure 1,
IL = 0

Long-Term Stability

Tj

=

TMAX for 1000 hours

LM34CA
Design
Limit
(NoteS)

±2.0
±2.0
±0.7

+10.0

+9.9,
+10.1

±0.4
±O.&

±1.0

±0.01
±0.02

±0.05

75
131
76
132

90

Typical
±0.4
±0.6
±0.8
±0.8

±1.0

±0.35

= +77'F
s: Vs s: 30V
Vs = +5V, +77'F
Vs = +5V
Vs = +30V, +77'F
Vs = +30V
4V s: Vs s: 30V, + 77'F
5V s: Vs s: 30V

Minimum Temperature
for Rated Accuracy

Tested
Limit
(Note 4)

Tested
Limit
(Note 4)

±3.0
±0.8

of·

+10.0

+9.9,
+10.1

my/OF, min
mV/'F,max

±3.0

mV/mA
mV/mA

±O.1

mVIV
mVIV

±O.o1
±0.02

±0.05

±O.1

90

163

75
118
76
117

3.0

0.5
1.0

+0.30

+0.5

+3.0

+5.0

2.0

±0.16

of
OF
'F
of

±0.30

±1.0

+0.5
+1.0

±2.0
±2.0

±0.4
±O.S

92

Units
(Max)

±1.0

±3.0

160

Design
Umlt
(NoteS)

'142

p.A
p.A
p.A
p.A

3;0

p.A
p.A

+0.30

+0.5

p.AloF

+3.0

+5.0

of

±0.16

139
92
2.0

OF

Note 1: Unless otherwise noted, these specHications apply: -SO'F " TI " + 300'F lor the LM34 and LM34A; -40'F " TI " +230'F lor the LM34C and
LM34CA; and +32'F" TI " + 212'Florthe LM34D. Vs = +S Vdc and ILOAD = SO p.A in the circuital Figure2; +6 Vdc lor LM34 and LM34A lor 230'F " Ti "
300'F. These specifications also apply Irom + S'F to TMAX in the circuH 01 Fl[Jure 1.
Note 2: Thermal resistance 01 the T0-46 package is 292'FIW iunction to ambient and 43'F{W junction to case, Thermal resistance of the TO·92 package is
324'F{W Junction fa ambient.
Note 3: Regulation is measured at constant junction temperature using pulse testing with a low duty cycle. Changes in output due to heating effects can be
computed by multiplying the internal disslpetlon by the thermal resistance.
Note 4: Tested limits are guaranteed and 100% tested In production,
Note 5: Design limits are guaranteed (but not 100% production tested) over the Indicated temperature and, supply voltage ranges. These limits are not used to
calculate outgoing quality levels,
Note 6: SpecHication In BOLDFACE TYPE apply over the full rated temperature range.
Note 7: Accuracy Is defined as the error between the output voltage and 10 mV{'F times the device's <:&se temperature at sPecified conditions of voltage, current,
and temperature (expressed In 'F).
Note 8: Nonlinearity is defined as the deviation of the output·voltage·versus·temperature curve from the best·fit straight line over the device's rated temperature
range.

Note 9: Quiescent currenl Is defined In the circuit of Figure
Note 10: Contact factory i~r availability of LM34CAZ.

1.

**

Note 11: Absolute Maximum Ratings indicate limlta beyond which damage to the device may occur. DC and AC electrical specifications do not apply when
operating the device beyond its rated operating conditions (see Note 1).

10-26

Another example is the application hint for the LF156 family:
"Exceeding the negative common-mode limit on either input
will cause a reversal of the phase to output and force the
amplifier output to the corresponding high or low state. Exceeding the negative common-mode limit on both inputs will
force the amplifier output to a high state. In neither case
does a latch occur, since raising the input back within the
common-mode range again puts the input stage and, thus
the amplifier, in a normal operating mode."
That's the kind of information a manufacturer should really
give to a data-sheet reader because no one could ever
guess it.
Sometimes, a writer slips a quirk into a characteristic curve,
but it's wiser to draw attention to it with a line of text. This is
because it's better to make the user sad before one gets
started, rather than when one goes into production. Conversely, if a user is going to spend more than 10 minutes
using a new product, one ought to spend a full five minutes
reading the entire data sheet.

A POint-By-Point Look
Let's look a little more closely at the data sheet of the National Semiconductor LM34, which happens to be a temperature sensor.
Note 1 lists the nominal test conditions and test circuits in
which all the characteristics are defined. Some additional
test conditions are listed in the column "Conditions", but
Note 1 helps minimize the clutter.
Note 2 gives the thermal impedance, (which may also be
shown in a chart or table).
Note 3 warns that an output impedance test, if done with a
long pulse, could cause significant self-heating and thus,
error.
Note 6 is intended to show which specs apply at all rated
temperatures.
Note 7 is the definition of the "Accuracy" spec, and Note B
the definition for non-linearity. Note 9 states in what test
circuit the quiescent current is defined. Note 10 indicates
that one model of the family may not be available at the time
of printing (but happens to be available now), and Note 11 is
the definition of Absolute Max Ratings.
• Note-the "4 seconds" soldering time is a new standard
for plastic packages.
•• Note-the wording of Note 11 has been revised-this is
the best wording we can devise, and we will use it on all
future datasheets.

FINE PRINT
What other fine print can be found on a data sheet? Sometimes the front page may be marked "advance" or "preliminary." Then on the back page, the fine print may say something such as:
"This data sheet contains preliminary limits and deSign
specifications. Supplemental information will be published
at a later date. The manufacturer reserves the right to make
changes in the products contained in this document in order
to improve design or performance and to supply the best
possible products. We also assume no responsibility for the
use of any circuits described herein, convey no license under any patent or other right and make no representation
that the circuits are free from patent infringement."

APPLICATIONS

Another important part of the data sheet is the applications
section. It indicates the novel and conventional ways to use
a device. Sometimes these applications are just little ideas
to tweak a reader's mind. After looking at a couple of applications, one can invent other ideas that are useful. Some
applications may be of no real interest or use.
In fact, after a device is released to the marketplace in a
In other cases, an application circuit may be the complete
preliminary status, the engineers love to make small im~rovements and upgrades in spe~i!ica~ions and .cha~acterisdefinition of the system's performance; it can be the test
circuit in which the specification limits are defined, tested
t~cs, and hate to degra~e a speclfl~atlon from Its first pubandguaranteed~Butrin all other instances, the_performance _ _ _hshe_~value-but occasionally that IS nec_e_s--;sa_ry-,:-,---cc----cof a typical application circuit is not guaranteed, it is only
Another item in the fine print is the manufacturer's teletypical. In many circumstances, the performance may dephone number. Usually it is best to refer questions to the
local sales representative or field-applications engineer, bepend on external components and their precision and
matching. Some manufacturers have added a phrase to
cause they may know the answer or they may be best able
their data sheets:
to put a questioner in touch with the right person at the
factory.
"Applications for any circuits contained in this document are
Occasionally, the factory's applications engineers have all
for illustration purposes only and the manufacturer makes
the information. Other times, they have to bring in product
no representation or warranty that such applications will be
engineers, test engineers or marketing people. And somesuitable for the use indicated without further testing or moditimes the answer can't be generated quickly-data have to
fication."
be gathered, opinions solidified or pOlicies formulated beIn the future, manufacturers may find it necessary to add
fore the manufacturer can answer the question. Still, the
disclaimers of this kind to avoid disappointing users with
telephone number is the key to getting the factory to help.
circuits that work well, much of the time, but cannot be easily guaranteed.

ORIGINS OF DATA SHEETS

The applications section is also a good place to look for
advice on quirks-potential drawbacks or little details that
may not be so little when a user wants to know if a device
will actually deliver the expected performance.
For example, if a buffer can drive heavy loads and can handle fast signals cleanly (at no load), the maker isn't doing
anybody any favors if there is no mention that the distortion
goes sky-high if the rated load is applied.

Of course, historically, most data sheets for a class of products have been closely modeled on the data sheet of the
forerunner of that class. The first data sheet was copied to
make new versions.
That's the way it happened with the UA709 (the first monolithic op amp) and all its copies, as well as many other similar families of circuits.

10-27

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10·50

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10-51

o

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3 Lead Molded TO-226
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All dimensions are in inches (millimeters)

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NS Package Number V20A
0.350

~~:~~~

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0.0 17±0.004 TYP
4

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V20A (REV L)

10·52

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NS Package Number V28A

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All dimensions are in inches [millimeters]

c

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10·53

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NS Package Number VGZ44A

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C

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10-54

3 Lead Molded TO-92
NS Package Nu!!,ber Z03A
All dimensions are in inches [millimeters]

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00.175-0.185:
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10·55

NOTES

t!lNational Semiconductor
Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
For datasheets on new products and devices still in production but not found in a databook, please contact the National
Semiconductor Customer Support Center at 1-800-272-9959.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. M/S 16-300
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090

ADVANCED BiCMOS LOGIC (ABTC, IBF, BiCMOS SCAN, LOW VOLTAGE
BiCMOS, EXTENDED TTL TECHNOLOGY) DATABOOK-1994
ABTC/BCT Description and Family Characteristics • ABTC/BCT Ratings, Specifications and Waveforms
ABTC Applications and Design Considerations. Quality and Reliability. Integrated Bus Function (IBF) Introduction>
54174ABT3283 Synchronous Datapath Multiplexer. 74FR900/25900 9-Bit 3-Port Latchable Datapath Multiplexer
54/74ACTQ3283 32-Bit Latchable Transceiver with Parity Generator/Checker and By1e Multiplexing
SCAN18xxxA BiCMOS 5V Logic with Boundary Scan. 74LVT Low Voltage BiCMOS Logie
VME Extended TTL Technology for Backplanes

ALS/AS LOGIC DATABOOK-1990
Introduction to Advanced Bipolar Logic. Advanced Low Power Schottky. Advanced Schottky

APPLICATION SPECIFIC ANALOG PRODUCTS DATABOOK-199S>
Audio Circuits

0

Video Circuits. Automotive. Special Functions • Surface Mount

ASIe-DESIGN~MANUAttGATE-ARRAYS-&- STANDARDCEl:l:S;;";;;1987>~
SSI/MSI Functions. Peripheral Functions. LSIIVLSI Functions. Design Guidelines. Packaging

CMOS LOGIC DATABOOK-1988
CMOS AC Switching Test Circuits and Timing Waveforms 0 CMOS Application Notes. MM54HC/MM74HC
MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. Surface Mount

CLOCK GENERATION AND SUPPORT (CGS) DESIGN DATABOOK-1994
Low Skew Clock Buffers/Drivers. Video Clock Generators • Low Skew PLL Clock Generators
Crystal Clock Generators

COP8™ DATABOOK-1994
COP8 Family. COP8 Applications • MICROWIRE/PLUS Peripherals • COP8 Development Support

CROSSVOLTTM LOW VOLTAGE LOGIC SERIES DATABOOK-1994
LCX Family. LVXTranslator Family. LVX.sus Switch Family. LVX Family. LVQ Family. LVT Family

DATA ACQUISITION DATABOOK-199S
Data Acquisition Systems. Analog-to-Digital Converters. Digital-to-Analog Converters. Voltage References
Temperature Sensors • Active Filters • Analog Switches/Multiplexers. Surface Mount

DATA ACQUISITION DATABOOK SUPPLEMENT-1992
New devices released since the printing of the 1989 Data Acquisition Linear Devices Databook. >

DISCRETE SEMICONDUCTOR PRODUCTS DATABOOK-1989
Selection Guide and Cross Reference Guides. Diodes. Bipolar NPN Transistors
Bipolar PNP Transistors. JFET Transistors • Surface Mount Products • Pro-Electron Series
Consumer Series. Power Components. Transistor Datasheets • Process Characteristics

DRAM MANAGEMENT HANDBOOK-1993
Dynamic Memory Control. CPU Specific System Solutions. Error Detection and Correction
Microprocessor Applications

EMBEDDED CONTROllERS DATABOOK-1992
COP400 Family. COP800 Family. COPS Applications. HPC Family. HPC Applications
MICROWIRE and MICROWIRE/PLUS Peripherals. Microcontroller Development Tools

FDDI DATABOOK-1994
Datasheets • Application Notes

F100K ECl lOGIC DATABOOK & DESIGN GUIDE-1992
Family Overview. 300 Series (Low-Power) Datasheets • 100 Series Datasheets • 11 C Datasheets
Design Guide • Circuit Basics • Logic Design • Transmission Line Concepts • System Considerations
Power Distribution and Thermal Considerations. Testing Techniques • 300 Series Package Qualification
Quality Assurance and Reliability. Application Notes·

FACTTM ADVANCED CMOS lOGIC DATABOOK-1993
Description and Family Characteristics. Ratings, Specifications and Waveforms
Design Considerations" 54AC/74ACXXX .. 54ACT/7 4ACTXXX • Quiet Series: 54ACQ/74ACQXXX
Quiet Series: 54ACTQ/74ACTQXXX. 54FCT /74FCTXXX • FCTA: 54FCTXXXA/74FCTXXXA/B

FAST® ADVANCED SCHOTTKY TTL lOGIC DATABOOK-1990
Circuit Characteristics. Ratings, Specifications and Waveforms. Design Considerations. 54F/74FXXX

FAST® APPLICATIONS HANDBOOK-1990
Reprint of 1987 Fairchild FAST Applications Handbook
Contains application information on the FAST family: Introduction. Multiplexers. Decoders. Encoders
Operators • FIFOs • Counters • TTL Small Scale Integration • Line Driving and System Design
FAST Characteristics and Testing. Packaging Characteristics

HIGH-PERFORMANCE BUS INTERFACE DATABOOK-1994
QuickRing • Futurebus + IBTL Devices • BTL Transceiver Application Notes • Futurebus + Application Notes
High Performance TTL Bus Drivers. PI-Bus. Futurebus+ IBTL Reference

IBM DATA COMMUNICATIONS HANDBOOK-1992
IBM Data Communications • Application Notes

INTERFACE: DATA TRANSMISSION DATABOOK-1994
TIAIEIA-232 (RS-232). TIAIEIA-422/423. TIAIEIA-485. Line Drivers. Receivers. Repeaters
Transceivers. Low Voltage Differential Signaling. Special Interface. Application Notes

liNEAR APPLICA nONS HANDBOOK-1994
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from Natic,mal Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.

lOCAL AREA NETWORKS DATABOOK-1993 SECOND EDITION
Integrated Ethemet Network Interface Controller Products. Ethernet Physical Layer Transceivers
Ethernet Repeater Interface Controller Products. Token-Ring Interface Controller (TROPIC)
Hardware and Software Support Products. FDDI Products. Glossary and Acronyms

LOW VOLTAGE DATABOOK-1992
This databook contains information on National's expanding portfolio of low and extended voltage products. Product datasheets
included for: Low Voltage Logic (LVQ), Linear, EPROM, EEPROM, SRAM, Interface, ASIC, Embedded Controllers, Real Time
Clocks, and Clock Generation and Support (CGS).

MASS STORAGE HANDBOOK-1989
Rigid Disk Pulse Detectors. Rigid Disk Data Separators/Synchronizers and ENDECs
Rigid Disk Data Controller • SCSI Bus Interface Circuits • Floppy Disk Controllers. Disk Drive Interface Circuits
Rigid Disk Preamplifiers and Servo Control Circuits. Rigid Disk Microcontroller Circuits. Disk Interface Design Guide

MEMORY DATABOOK-1994
FLASH. CMOS EPROMs • CMOS EEPROMs. PROMs. Application Notes

MEMORY APPLICATIONS HANDBOOK-1994
FLASH. EEPROMs • EPROMs • Application Notes

OPERATIONAL AMPLIFIERS DATABOOK-1995
Operational Amplifiers. Buffers 0 Voltage Comparators. Active Matrix/LCD Display Drivers
Special Functions 0 Surface Mount

PACKAGING DATABOOK-1993
Introduction to Packaging 0 Hermetic Packages 0 Plastic Packages. Advanced Packaging Technology
Package Reliability Considerations • Packing Considerations • Surface Mount Considerations

POWER IC's DATABOOK-1995
Linear Voltage Regulators 0 Low Dropout Voltage Regulators. Switching Voltage Regulators
Motion Control. Surface Mount

PROGRAMMABLIE lOGIC DEVICE DATABOOK AND
DESIGN GUIDE-1993
Product Line Overview • Datasheets 0 Design Guide: Designing with PLDs • PLD Design Methodology
PLD Design Development Tools. Fabrication of Programmable Logic. Application Examples

REAL TIME CLOCK HANDBOOK-1993
RELIABILITY HANDBOOK-1987
Reliability and the Die • Internal Construction 0 Finished Package. MIL-STD-883. MIL-M-38510
The Specification Development Process 0 Reliability and the Hybrid Device. VLSIIVHSIC Devices
Radiation Environment. Electrostatic Discharge. Discrete Device. Standardization
Quality Assurance and Reliability Engineering· Reliability and Documentation. Commercial Grade Device
European Reliability Programs. Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor 0 The Total Military/ Aerospace Standardization Program
883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-38510 Class B Products
Radiation Hardened Technology. Wafer Fabrication. Semiconductor Assembly and Packaging
Semiconductor Packages 0 Glossary of Terms 0 Key Government Agencies 0 AN/ Numbers and Acronyms
Bibliography 0 MIL-M-3851 0 and DESC Drawing Cross Listing

SCANTM DATABOOK-1994
Evolution of IEEE 1149.1 Standard. SCAN BiCMOS Products. SCAN ACMOS Products. System Test Products
Other IEEE 1149.1 Devic,es

TELECOMMUNICATIONS-1994
COMBO and SLiC Devices • ISDN • Digital Loop Devices. Analog Telephone Components. Software. Application Notes

VHC/VHCT ADVANCED CMOS LOGIC DATABOOK-1993
This databook introduces National's Very High Speed CMOS (VHC) and Very High Speed TIL Compatible CMOS (VHCn
designs. The databook includes Description and Family Characteristics • Ratings, Specifications and Waveforms
Design Considerations and Product Datasheets. The topics discussed are the advantages of VHCIVHCT AC Performance,
Low Noise Characteristics and Improved Interface Capabilities.

NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS
ALABAMA
Huntsville
Anthem Electronics
(205) 890-0302

San Jose ' '
Anthem Electronics
(408) 453-1200

Future Electronics Corp.

Future Electronics Corp.

(408) 434-1122

(205) 830-2322

Hamilton/Hallmark

Hamilton/Hallmark

(408) 435-3500

(205) 837-8700

Pioneer Technology

Largo
Future Electronics Corp.
(813) 530-1222

MARYLAND
Columbia
Anthem Electronics

Hamilton/Hallmark

(410) 995-6640

(813) 541-7440

Bell Industries

Orlando
Chip Supply
"Die Distributor"

(410) 290-5100

Future Electronics Corp.
(410) 290-0800

Pioneer Technology

(408) 9~9100

(407) 298-7100

Hamilton/Hallmark

(205) 837-9300

Zeus Elect. an Arrow Co.

Time Electronics

(410) 988-9800

Time Electronics
(205) 721-1134

ARIZONA
Phoenix
Future Electronics Corp.
(602) 968-7140

Hamilton/Hallmark
(602) 437-1200

Scottsdale
Alliance Electronics Inc.
(602) 483-9400

Tempe
Anthem Electronics
(602) 966-6600

Bell Industries
(602) 966-3600

Pioneer Standard
(602) 350-9335

Time Electronics
(602) 967-2000

CALIFORNIA
Agoura Hills
Bell Industries
(816) 865-7900

Future Electronics Corp.
(818) 865-0040

Pioneer Standard
. (818) 865-5800

Time Electronics
(818) 707-2890

Calabasas
F/X Electronics
(818) 591-9220

Chatsworth
Anthem Electronics
(818) 775-1333

CostaMesa
Hamilton/Hallmark
(714) 641-4100

Irvine
Anthem Electronics

(408) 629-4789

Sunnyvale
Bell Industries
(408) 734-8570

(407) 657-3300

Time Electronics

GEORGIA
Duluth
Anthem Electronics

(408) 734-9890

Tustin
Time Electronics
(714) 669-0216

Woodland Hills
Hamilton/Hallmark
(818) 594-0404

Time Electronics
(818) 593-8400

COLORADO
Denver
Bell Industries
(303) 691-9270

Englewood
Anthem Electronics
(303) 790-4500

Hamilton/Hallmark
(303) 790-1662

Pioneer Technology
(303) 773-8090

:rime ElectrOnics
(303) 799-5400

Lakewood
Future Electronics Corp.
(303) 232-2008

CONNECTICUT
Cheshire
Future Electronics Corp.
(203) 250-0093

Hamilton/Hallmark
(203) 271-2644

Meriden
Bell Industries
(203) 639-6000

Shelton
Pioneer Standard

(714) 768-4444

(203) 929-5600

Bell Industries

Wallingford
Advent Electronics

(714) 727-4500

Future Electronics Corp.
(714) 453-1515

Pioneer Standard
(714) 753-5090

Zeus Elect. an Arrow Co.
(7,14) 581-4622

Rocklin
Anthem Electronics
(916) 624-9744

Bell Industries
(916) 652·0418

Roseville
Future Electronics Corp.
(916) 783-7877

Hamilton/Hallmark
(916) 624-9761

San Diego
Anthem Electronics
(619) 453-9005

Bell Industries
(619) 576-3294

Future Electronics Corp.
(619) 625-2800

Hamilton/Hallmark
(619) 571-7540

Pioneer Standard
(619) 514-7700

Time Electronics
(619) 674-2800

(407) 641-6566

Winter Park
Hamilton/Hallmark

(800) 982-0014

Waterbury
Anthem EI~ronics
(203) 575-1 75

FLORIDA
Altamonte Springs
Anthem Electronics

(404) 931-9300

Hamilton/Hallmark
(404) 623-4400

Pioneer Technology
(404) 623-1003

Time Electronics
(404) 623-5455

Norcross
Future Electronics Corp.
(404) 441-7676

ILLINOIS
Addison
Pioneer Standard
(709) 495-9660

Bensenville
Hamilton/Hallmark
(709) 860-7780

Des Plaines
Advent Electronics
(800) 323-1270

Elk Grove Village
Bellindustriss
(709) 640-1910

Hoffman Estates
Future Electronics Corp.
(708) 882-1255

Itasca
Zeus Elecl an Arrow Co.
(708) 595-9730

Schaumburg
Anthem Electronics
(708) 884-0200

Time Electronics
(708) 303-3000

INDIANA
Fort Wayne
Bell Industries
(219) 422-4300

Indianapolis
Advent Electronics Inc.
(800) 732-1453

Bell Industries
(317) 875-8200

Future Electronics Corp.

(407) 831-0007

(317) 469-0447

Bell Industries

Hamilton/Hallmark

(407) 339-0078

(317) 872-8875

Future Electronics Corp.

Pioneer Standard

(407) 665-7900

(317) 573-0880

Pioneer Technology
(407) 834-9090

Deerfield Beach
Future Electronics Corp.
(305) 426-4043

Pioneer Technology
(305) 428-8877

Fort Lauderdale
Hamilton/Hallmark
(305) 484-5482

Time Electronics
(305) 484-1864

Indialantic
Advent Electronics
(600) 975-8669

Lake Mary
Zeus Elect. an Arrow Co.
(407) 333-9300

IOWA
Cedar Rapids
Advent Electronics
(800) 397-8407

Hamilton/Hallmark
(319) 393-0033

KANSAS
Lenexa
Hamilton/Hallmark
(913) 669-4747

Overland Park
Future Electronics Corp.
(913) 649-1531

Seymour Electronics
(410) 992-7474

Time Electronics
(410) 720-3600

Gaithersburg
Plon_ Technology
(301) 921-0660

MASSACHUSETTS
Andover
Bell Industries
(508) 474-8680

Bolton
Future Electronics Corp.
(508) 779-3000

Lexington
Pioneer Standard
(617) 661-9200

Newburyport
Rochester Electronics
"Obsolete Products"
(508) 462-9332

Norwood
Gerber Electronics
(617) 769-6000

Peabody
Hamilton/Hallmark
(508) 532-3701

Time Electronics
(508) 532-9m
Tyngsboro
Port Electronics
(509) 649-4660

Wilmington
Anthem Electronics
(509) 657-5170

Zeus Elect. an Arrow Co.
(509) 658-0900

MICHIGAN
Farmington Hills
Advent Electronics
(800) 572-9329

Grand Rapids
Future Electronics Corp.
(616) 698-6800

Pioneer Standard
(616)698-1800

Uvonla
Future Electronics Corp.'
(313) 261-5270

O'Fallon
Advent Electronics
(800) 888-9566

Plymouth
Hamilton/Hallmark
(313) 416-5800

Pion_ Standard
(313) 418-2157

Wyoming
A. M. Electronics, Inc.
(616) 531·9300

MINNESOTA
Bloomington
Hamilton/Hallmark
(612) 661-2600

Eden Prairie
Anthem Electronics
(612) 944-5454

Future Electronics Corp.
(612) 944-2200

Pioneer Standard

KENTUCKY
Lexington
Hamilton/Hallmark

Minnetonka
Time Electronics

(606) 288-4911

(612) 931-2131

(612) 944-3355



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