1995_Silicon_Systems_Communications_Products 1995 Silicon Systems Communications Products

User Manual: 1995_Silicon_Systems_Communications_Products

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The Company
Silicon Systems specializes in the design and manufacture of application-specific,
mixed-signal integrated circuits (MSICs®). It offers a sophisticated line of custom and
standard ICs aimed primarily at the storage, communications and industrial marketplace.
The company, which is headquartered in California, 30 miles south of Los Angeles, was
founded in 1972 as a design center. It soon entered into manufacturing and today has
fabrication sites in California and approximately 2,000 employees worldwide. Additional
operations include assembly and test facilities in California and Singapore, and design
engineering centers in California, Colorado, Tokyo and Singapore.
Reliability and quality are built into Silicon Systems' products through the use of statistical
problem solving techniques, analytical controls, and other quantitative methods. Silicon
Systems has successfully met quality standards established by the International Organization
of Standardization that governs ISO 9000 certification regulations. Silicon Systems' domestic
facilities have received ISO 9001 certification for Quality Management Systems applicable to
design and manufacture, and, Silicon Systems' Singapore facility has achieved ISO 9002
certification which is pertinent to production and installation.
The company is committed to the goal of customer satisfaction through the on-time delivery of
defect-free products that meet or exceed the customer's expectations and requirements. Listed
in the back of this publication is a worldwide network of sales representatives and distributors
ready to serve you.
CERTIFIED

ISO

9001

~ISI=I ....

~

~ ~1--

'~

----

Silicon Systems, Inc.
Quality Management Systems

- - - - - - - 1 9 9 5 Data Book

NOTICE
All products listed herein and subsequently sold by Silicon Systems, Inc. are subject to the
terms and conditions contained in the Silicon Systems Order Acknowledgment Form
applicable to the sale, including those pertaining to warranty, patent infringement and
limitation of liability. Purchasers of these products acquire no rights in the technology
incorporated therein, absent the express written consent of Silicon Systems, Inc. Silicon
Systems, Inc. makes no warranty, express or implied, with regard to the information set forth
in this publication, nor does it warrant that the products described herein are merchantable
or suitable for a particular purpose. Silicon Systems, Inc. reserves the right to discontinue
production of any product, change a product specification and/or revise product pricing at any
time with, or without, notice.
Applications requiring mechanical and electrical parameters outside of the published
specifications are not recommended without additional review and acceptance by Silicon
Systems, Inc. Silicon Systems, Inc. further assumes no responsibility for the use of any
integrated circuit technology other than integrated circuit technology embodied in a Silicon
Systems, Inc. product. These products are not authorized for use as components in life
support devices or other medical systems.

© Copyright 1995 Silicon Systems, Inc. All rights reserved. Product and company names listed are trademarks of their
respective companies.
K-Series integrated circuits are protected by the following patents:
4,691,172/4,777,453/4,847,868/4,866,739/4,870,370 /4,789,995

Contents

Target, Advanced and
Preliminary Information
In this data book the following conventions
are used in designating a data sheet
''Target,'' "Advanced" or "Preliminary":
Target SpecificationThe target specification is intended as an
initial disclosure of specification goals for
the product. Product is in first stages of
design cycle.
Advance InformationIndicates a product still in the design cycle,
undergoing testing processes, and any
specifications are based on deSign goals
only. Do not use for final design.
Preliminary DataIndicates a product not completely released to production. The specifications
are based on preliminary evaluations and
are not guaranteed. Small quantities are
available, and Silicon Systems should be
consulted for current information.
III

Index
Page #
Contents ................................................................................................................................................... III
Index ........................................................................................................................................................ IV
Numerical Product Index ........................................................................................................................ VII
Discontinued Parts List ...........................................................................................................................VII
Product Selector Guide ......................................................................................................................... VIII

Section 1.

CUSTOM SOLUTIONS ................................................................................................................ 1-0

Section 2.

QUALITY ASSURANCE AND RELIABILITy ............................................................................. 2-0

Section 3.

K-SERIES SINGLE-CHIP MODEM FAMILY
K-Series Modem Family Introduction ......................................................................................................................3-0
73K212L
Bell 212A/103 Single-Chip Modem ........................................................................................... 3-1
73K221 L
CCITT V.22, V.21 Single-Chip Modem ................................................................................... 3-25
73K222L
V.22, V.21, Bell 212A Single-Chip Modem ............................................................................. 3-51
73K222U
Single-Chip Modem with UART .............................................................................................. 3-77
73K224L
V.22bislV.221V.21, Bell 212A1103 Single-Chip Modem ........................................................ 3-117
73K302L
Bell 212A, 103, 202 Single-Chip Modem .............................................................................. 3-149
73K321 L
CCITT V.23, V.21 Single-Chip Modem ................................................................................. 3-177
73K322L
CCID V.23, V.22, V.21 Single-Chip Modem ........................................................................ 3-201
73K324L
CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem ........................................ 3-229

Section 4.

CONTROLLERS & SPECIAL MODEM PRODUCTS
73D2248/2348
73M550/15501

2550
73M291 0/291 OA

NEW

73M2918/2918A

73M223

Section 5.

Microcontroller ........................................................................................................................4-11
Plug and Play Microcontroller and UART (abridged data sheet) ............................................ 4-49
1200 Baud FSK Modem .......................................................................................................... 4-51

ANALOG SIGNALLING & SWITCHING PRODUCTS
75T201
7ST202/203

75T204
75T2089/90/91

7ST980
78A207

Section 6.

MNP5, V.42 bis Datacom Modem Device Set ......................................................................... .4-1
Universal Asynchronous ReceiverlTransmitter with FIFOs .......................................................... *

Integrated DTMF Receiver ....................................................................................................... S-1
SV Low-Power DTMF Receiver ................................................................................................ 5-9
SV Low-Power Subscriber DTMF Receiver ............................................................................ 5-17
DTMF Transceivers ................................................................................................................ 5-2S
Call Progress Tone Detector ................................................................................................... 5-33
MFR1 Receiver .......................................................................................................................5-39

PCM PRODUCTS
78P236
78P2361
78P2362
78P300
78P304A
78P7200

DS-3 Line Interface ...............................................................................................................:....... *
STS-1 Line Interface ..................................................................................................................... *
34.368 Mbitls Line Interface ......................................................................................................... *
T1/E1 Integrated Short-Haul Transceiver with Receive Jitter Attenuation ................................ 6-1
Low-Power T1/E1 Integrated Short Haul Transceiver with Receive Jitter Attenuation ........... 6-17
E3/DS-3 Line Interface with Receive Equalizer ...................................................................... 6-35

* Data Sheet available upon request

IV

Page #
Section 7.

NEW
NEW
NEW
NEW
NEW
Section 8.

LAN PRODUCTS
780902
7808373
7808392
7808392L
7808377
7808378
7802250

Ethernet Twisted-Pair Media Attachment Unit .......................................................................... 7-1
3V/5V PCMCIA Ethernet Combo ............................................................................................ 7-15
Ethernet Coaxial Transceiver .................................................................................................. 7 -59
Low Power Ethernet Coaxial Transceiver ............................................................................... 7-71
1 OBase-T Ethernet Combo for Plug and Play ......................................................................... 7 -73
Enhanced PCMCIA Ethernet Device ...................................................................................... 7-75
155 Mbitls ATM Line Transceiver ........................................................................................... 7-77

PROGRAMMABLE ELECTRONIC FILTERS

(See Product Selector Guide, pg. IX, for a complete listing of filter products offered)
32F8001/8002

32F8003
32F8101
32F8120
32F8130/8131

32F8144

Section 9.

NEW

Section 10.

Low-Power Programmable Electronic Filter .............................................................................. 8-1
Low-Power Programmable Electronic Filter ............................................................................ 8-13
Low-Power Programmble Electronic Filter .............................................................................. 8-23
Low-Power Programmable Electronic Filter ............................................................................ 8-33
Low-Power Programmable Electronic Filter ............................................................................ 8-41
Programmable Electronic Filter ............................................................................................... 8-49

APPLICATION NOTES AND GLOSSARY
K-Series Application Notes
K-Series General Application Notes ........................................................................................................................9-1
- Setting DTMF Levels for 1200 Bitls K-Series Modems ........................................................................................ 9-5
- SSI 73K212A High Speed Connect Sequence .................................................................................................... 9-6
- V.22 & V.22bis Connect Sequences .................................................................................................................... 9-7
- Remote Loop Handshake Sequence ................................................................................................................... 9-8
- SSI 73K224L Retrain at 2400 bitls ....................................................................................................................... 9-9
- 551 73K212, 73K222 Originate & Answer Handshake Sequences ................................ ; .................................. 9-10
- SSI 73K224L Originate & Answer Handshake Sequences ................................................................................ 9-12
- Troubleshooting the Modem Design ............................................................................. ,..... ,.............................. 9-14
78P236/2361 1236217200 Demo Board Application Note ....................................................................................... 9-17
7808373 Technical Reference Guide ................................................................................................................... 9-27
DTMF Receiver Application Guide ........................................................................................................................ 9-71
GLOSSARY ..........................................................................................................................................................9-85
Voiceband Modem Standards Reference Chart .................................................................................................... 9-97

PACKAGING/ORDERING INFORMATION
Packaging Index ................................................................................................................................................ 10-0
Small Form Factor Package Selector Guide ......................................................................................................... 10-1
Plastic DIP 8, 14,16 and 18 Pins .......................................................................................................................... 10-4
Plastic DIP 20, 22, 24 and 245 Pins ..................................................................................................................... 10-5
Plastic DIP 28, 32 and 40 Pins .............................................................................................................................. 10-6
Cerdip 8, 14, 16 and 18 Pins ................................................................................................................................. 10-7
Cerdip 22, 24 and 28 Pins ..................................................................................................................................... 10-8
Ouad (PLCC) 20 and 28 Leads ............................................................................................................................. 10-9
Ouad (PLCC) 32 and 44 Leads ........................................................................................................................... 10-1 0
Ouad (PLCC) 52 and 68 Leads ........................................................................................................................... 1 0-11
Ouad Flatpack (OFP) 52, 100 Leads .................................................................................................................. 10-12
Ouad Flatpack (QFP) 128 Leads ........................................................................................................................ 10-13
Thin Quad Flatpack (TOFP) 32, 48 Leads .......................................................................................................... 10-14
Thin Ouad Flatpack (TOFP) 64, 80 and 100 Leads ............................................................................................ 10-15
Thin Ouad Flatpack (TQFP) 120 and 128 Leads ................................................................................................ 10-16
Thin Ouad Flatpack (TOFP) 144 Leads .............................................................................................................. 10-17
Very Thin Ouad Flatpack (VTOFP) 32, 48 and 64 Leads ................................................................................... 10-18
Very Thin Ouad Flatpack (VTOFP) 100 Leads ................................................................................................... 10-19
Very Thin Quad Flatpack (VTQFP) 120 Leads ................................................................................................... 10-20
Ultra Thin Quad Flatpack (UVQFP) 64 and 100 Leads ....................................................................................... 10-21

v

Page #
Section 10.

PACKAGING/ORDERING INFORMATION (continued)
SON 8, 14 and 16 Leads ..................................................................................................................................... 10-22
SOL 16, 18, 20, 24 and 28 Leads ....................................................................................................................... 10-23
SOL 34 Leads
......................................'........................................................................................................ 10-24
SOW 32 Leads
.............................................................................................................................................. 10-24
SaM 36 Leads
.............................................................................................................................................. 10-24
SaM 44 Leads
.............................................................................................................................................. 10-25
VSOP 20, 24 Leads ............................................................................................................................................. 10-25
VTSOP 16, 20 Leads .......................................................................................................................................... 10-26
UTSOP 20, 36 Leads .......................................................................................................................................... 10-27
Ordering Information ........................................................................................................................................... 10-28

Section 11.

SALES OFFICES/DISTRIBUTORS ............................................................................................ 11-1

VI

Numerical Index
SSI Device Numbers

Page #

32FS001/8002 ....................................................................... 8-1
32FS003 .............................................................................. 8-13
32FS1 01 .............................................................................. 8-23
32FS120 .............................................................................. 8-35
32FS130/8131 ..................................................................... 8-43
32FS144 .............................................................................. 8-51
73K212L ................................................................................ 3-1
73K221 L .............................................................................. 3-25
73K222L .............................................................................. 3-51
73K222U ............................................................................. 3-77
73K224L ............................................................................ 3-117
730224S/2348 ....................................................................... 4-1
73K302L ............................................................................ 3-149
73K321 L ............................................................................ 3-177
73K322L ............................................................................ 3-201
73K324L ............................................................................ 3-229
73M223 ............................................................................... 4-51
73M291 0/291 OA .................................................................. 4-11
73M2918/2918A .................................................................. 4-49
73M55011550/2550 ................................................................... *

SSI Device Numbers

Page #

75T201 .................................................................................. 5-1
75T202/203 ........................................................................... 5-9
75T204 ................................................................................ 5-17
75T2089/90/91 .................................................................... 5-25
75T980 ................................................................................ 5-33
78A207 ................................................................................ 5-39
78P236 ...................................................................................... *
78P2361 .................................................................................... *
78P2362 .................................................................................... *
78P300 .................................................................................. 6-1
78P304A .............................................................................. 6-17
78P7200 .............................................................................. 6-35
7802250 .............................................................................. 7-77
7808373 .............................................................................. 7-15
7808377 .............................................................................. 7-73
7808378 .............................................................................. 7 -75
7808392 .............................................................................. 7-59
780S392L ............................................................................ 7-71
780902 .................................................................................. 7-1

*Oata Sheet available upon request.

Discontinued Parts List
The following parts are no longer supplied or supported by Silicon Systems.

Part #

Part #

7302180
7302240
7302247F
7302404
7302420/2421
730246
7302950
73K212 (12V Version)
73K221 (12V Version)
73K222 (12V Version)
73K312L
73M214
73M376
73M450U1450/2450
73M650/1650

75T957
75T981
75T982
78A093A/B
78P233A
78P234
78P8050
78P8060
7808330
7808360
7808370

VII

Communications Products Selector Guide
Device Number

8212
8103

8202

CCIlT
V.21

CCITT
V.23

CCIlT CCIlT Description
V.22 V.22bis

Power
Supply

Available
Packages

K-SERIES SINGLE CHIP MODEM FAMILY

551 73K212L
551 73K2125L

X
X

551 73K221L
551 73K222L

X

X
X
X

551 73K2225L
551 73K224L

X
X
X

X
X
X

X
X
X

551 73K2245L

X

X

X

551 73K302L

X
X

551 73K2215L

551 73K222U

X
X
X

low power, integrated single-chip modem

+5V

73K212L with serial interface only

+5V

28 DIP, 28 PLCC
22 DIP

low power, integrated single-chip modem

+5V

22, 28 DIP, 28 PLCC

73K221 L with serial interface only

+5V

22 DIP

low power, integrated single-chip modem

+5V

22, 28 DIP, 28 PLCC

73K222L with serial interface only

+5V

22 DIP

73K222L with 16C450 UART

+5V

40 DIP, 44 PLCC

X

Bell 212A1103, CCITT V.22bisN.221V.21

+5V

28 DIP, 28, 32 PLCC,

X

73K224L with serial interface

+5V

22 DIP

Bell 212A120211 03

+5V

28 DIP, 28 PLCC

Bell 212A1202/1 03; serial interface only

+5V

22 DIP

CCITT V.23N.21

+5V

28 DIP, 28 PLCC
22 DIP

I

52 QFP, 64 TQFP

551 73K3025L
551 73K321L

~

X
X
X

551 73K321 5L
551 73K322L
551 73K3225L
551 73K324L

X
X

B212

X
X

X
X
X
X
X

73K321 L with serial interface only

+5V

X

CCITT V.23N.22N.21

+5V

28 DIP, 28 PLCC

X
X

73K322L with serial interface only

+5V

22 DIP

CCITT V.22bisN.22N.23N.21

+5V

28 DIP, 28, 32 PLCC,
52 QFP, 64 TQFP

X

I

I
I

CONTROLLERS AND SPECIAL MODEM PRODUCTS

I

modem device set wI AT, MNP

+5V

Various QFP & TQFP

551 73M223

1200 bitls modem IC,
compact HDX V.23 modem

+5V

16 DIP, 16 50L

551 73M550

16C550 pin compatible UART
Receive and Transmit FIFOs

+5V

40 DIP, 44 PLCC, 48 GT

551 73M1550

28-pin version of 73M550,
full UART in 28-pin package

+5V

28 DIP, PLCC

551 73M2550

28-pin version of 73M550
adds J.lPR5T function

+5V

28 DIP, PLCC

551 73M291 0/291 OA

Microcontroller device

551 73M291812918A

Plug & Play Microcontroller & UART

551 73D2248/2348

I

X

X

X

+3V1+5V
+3.3V1+5V

Various QFP & TQFP
100 QFP

I

Communications Products Selector Guide
Device Number

Circuit Function

Features

Power

Available Packages

ANALOG SIGNALLING AND SWITCHING PRODUCTS

SSI751201

Integrated DTMF Receiver

binary coded 2-of-8 output

+12V

22 DIP

SSI 75T202

Integrated DTMF Receiver

low power, binary output

+5V

18 DIP

SSI 75T203

Integrated DTMF Receiver

early detect, binary output

+5V

18 DIP

SSI75T204

Integrated DTMF Receiver

low power, binary output

+5V

14 DIP, 16 SO

SSI7512089

Integrated DTMF Transceiver

generator & receiver, IlP interface

+5V

22 DIP

SSI 75T2090

Integrated DTMF Transceiver

like 75T2089 wI call progress detect

+5V

22 DIP

SSI 75T2091

Integrated DTMF Transceiver

like 75T2090 wI early detect

+5V

28 DIP, PLCC

SSI 75T980

Imprecise Call Progress Detector

energy detect in 305-640 Hz band, Teltone

+5V

8 DIP

SSI78A207

Integrated MF Receiver

detects central office toll signals

+5V

20 DIP

SSI78P236

DS-3 Line Interface

T3 clock & data recovery, transmit equalization

+5V

28 DIP, PLCC

SS1781'2361

STS-1 Line Interface Transceiver

STS-1 clock & data recovery, transmit equalization

+5V

28 DIP, PLCC

SSI 78P2362

CEPT E-3 Line Interface Transceiver

E3 clock & data recovery, transmit equalization

+5V

28 DIP, PLCC

SSI 78P300

T1/E1 Short Haul Transceiver

receive jitter attenuation

+5V

28 DIP, PLCC

SSI78P304A

Low-Power 38P300

receive jitter attenuation

+5V

28 DIP, PLCC

5S178P7200

DS-3/E3 Line Interface Transceiver

DS-3/E3 transceiver wlreceive equalization
& higher transmitter drive

+5V

28 DIP, PLCC

PCM PRODUCTS

x

LAN PRODUCTS

SSI78Q902

10BaseT MAU Transceiver

direct interface to twisted pair and AUI

+5V

28 DIP, PLCC

5S178Q2250

ISS Mbitls ATM Transceiver for NRZ

on-chip clock/data recovery

+5V

48 TQFP

SSI78Q8373

Single-chip Ethernet IC for PCMClA

on-chip PCMCIA bus logic, 1OBaseT Transceiver

5S178Q8377

Single-chip Ethernet for ISAlPnP

on-chip Plug & Play logic, 1OBaseT transceiver

5S178Q8378

Single-chip Ethernet for PCMCIA

on-chip PCMCIA multi-function logic

SSI78Q8392

802.3 Coax Transceiver

pin-compatible w/NSC 8392

-9V

16 DIP, 28 PLCC

SSI 78Q8392L

Low-power Coax Transceiver

pin-compatible w/NSC 8392

-9V

16 DIP, 28 PLCC

3V or 5V
+5V
3V or 5V

100 TQFP
128 QFP
100 TQFP

I

Communications Products Selector Guide
Device Number

Circuit Function

Features

PROGRAMMABLE FILTERS

551 32FB001/B002

Low Power Prog. Elect. Filter

551 32FB003

Prog. Electronic Filter

7-Pole Equiripple Active Filter, Prog. Ic IPulse Slimming,S - 13 MHz

551 32FB011/B012

Prog. Electronic Filter

7-Pole Bessel Active Filter, Prog. Ic IPulse Slimming, (5 - 13 MHz, B011) (6-15 MHz, B012)

7-Pole Equiripple Active Filter, Prog. Ic IPulse Slimming, 9 - 27 MHz (B001), 6-1B MHz (B002)

S51 32FB020lB022

Low Power Prog. Elect. Filter

7-Pole Equiripple Active Filter, Prog. Ic IPulse Slimming, 1.5 - B MHz

S51 32FB030

Prog. Electronic Filter

7-Pole.Equiripple Active Filter, Prog. Ic /Pulse Slimming, 250 kHz - 2.5 MHz

SSI32F8101/02/03/04

Low Power Dgtl. Prog. Filter

(8101/02/03) - 8001/02103 w/Serial Port & DACs, 95 mW, (8004) - Similar to 8103, Ic range 3-9 MHz

551 32FB120

Low Power Dgtl. Prog. Filter

32FB020 with serial port and DACs

5S132FB130/31

Low Power Dgtl. Prog. Filter

32FB030 with serial port and DACs / 32FB131

551 32FB144

Low Power Dgtl. Prog. Filter

2 zerol7-pole linear phase filter, 7-bit serial shift register, 7-27 MHz
----

><

-

-

-

= 150 kHz < Ic < 1.5 MHz
-

-

-

-

Section

1

CUSTOM
SOLUTIONS

I

1-0

CUSTOM SOLUTIONS

Faster to market for mixed-signal applications

SILICON SYSTEMS LEADS THE WAY
DEVELOPING MIXED-SIGNAL CUSTOM
PRODUCTS.

Whatever your mixed-signal design application, Silicon
Systems gives you a competitive advantage. In communications, disk drives, other storage products, automotive control
systems, or other analog/digital sig nal processing applications,
you can depend on our technical know-how to do the job right
and turn your design around faster.

This is a story about leadership. Silicon Systems is dedicated to taking the point in the creation of high-performance,
application-specific custom, mixed-signal integrated circuits
(MSICs®).

CMOS. Bipolar. BiCMOS. Analog. Digital.
We've done it

Such dedication means we bring a lot to the party. Including truly innovative analog, digital, and mixed analog/digital
ICs. A full complement of mixed-signal CMOS, BiCMOS and
Bipolar waferfabrication processes, state-of-the-art automated
design tools, production, assembly, test, and QA capability.

Our designers are an experienced bunch. They're uniquely
able to take a look at your specific application problem and
move quickly to the right IC solution.
Our team is particularly adept at identifying key issues
such as power, cost and performance trade-offs. So we can
gear our efforts toward delivering you an optimized solution,
manufactured with the appropriate fab process.

No one's more experienced
Morethan 20 years of successfullC design work makes us
the most experienced engineering team in the MSICs field. Add
it all up and you get a company that saves you time and money
while delivering you the most sophisticated mixed-signal custom ICs you can get.
... , .'"
I.·>,~,,·

I.

>.
IA

.. ,

..,

.., ....

. . . .,

.,

.

Application

SiliconSystems·Desiglled·.Exal1lples

....

CMOS Analog Processing

For analog continuous time, sampled data
(switched-capacitor implementation), and
high-current power transistor applications.
low power, high density capability also
supports inclusion of ROMs, RAMs, and
other analog/digital subsystems.

• Complete single-chip 2400 bit/s modem
14.4 kbps modem chip set
• Direct-broadcast satellite descrambler
• Servo and spindle motor controllers with 1.0
Amp motor interfaces
• High-resolution analog data acquisition
• Cellular baseband processor

BiCMOS Signal Processing

For high-performance, low noise,
wideband signal acquisition and processing applications. Offers TTL, CMOS
and/or ECl logic interfaces with high
current drive.

•
•
•
•
•
•
•

Sub 1 nV/'<'Hz HDD RIW amplifiers
AGC, pulse detection amplifiers
High-speed data separators
Wideband transceivers
Plls (phase locked loops)
Optical signal processing
Digital cellular, PCS IF circuits

Digital CMOS

For ASIC controllers, digital signal
processors, sequencers and data path
applications with on-board ROM, RAM,
and PlA sub-systems. Offers standard
TTL and/or CMOS logic interfaces.

•
•
•
•
•

Digital communications lAN devices
Hard disk drive controllers
SCSI interface controllers
UARTs
Digital signal processors for hard
disk servo and telecommunications

1-1

1

CUSTOM SOLUTIONS

The right mix of analog and digital

SOPHIST/CA TED TOOLS FOR
STRUCTURED CUSTOM DESIGN

Providing total analog/digital systems on a chip allows you
to meet your cost and performance objectives whether you're
designing the next generation of communication, computer
peripheral, or industrial control systems.

At each of six design centers capable of worldwide service
- Tustin, San Jose and Nevada City, California; Longmont,
Colorado; Tokyo and Singapore - Silicon Systems employs
PEGASYS, any internal design automation system developed
from carefully s~lected vendor tools and our own proprietary
software. Using Mentor Graphics workstations of both electrical
and physical design, PEGASYS helps create complex designs
while significantly reducing schedules, costs and errors.

We've turned to CMOS to effectively implement lowpower, highly integrated systems solutions for everything from
modems and cellular phones to hard disk drive controllers and
digital signal processors.
We've gone the BiCMOS route to meet the high-performance needs of products like wideband transceivers, wireless
IF modems, RIW amplifiers, low-noise amplifiers, pulse detectors, high-speed data separators and high-performance, lowpower combo devices.

By integrating third-party tools and custom software, we're
better able to design and analyze mixed-signal integrated
circuits in all CMOS, Bipolar and BiCMOS technologies. It's an
approach that has given us the edge in mixed-signal design and
helped put Silicon Systems' customers in a favorable position
in the marketplace.

Dracula'
I

Extraction'"

I

I~-'DRC D~'I~
ICrules'

Dracula'

Hspice'

PEGASYS Design System
1-2

• Product and company
names are trademarks of
their respective companies

CUSTOM SOLUTIONS

Specffically, PEGASYS brings the following to each design:

Capabilities include:

• Fully integrated design environment

• Chip floor planning

• Methodology for precision circuit design

• Analog device generators

• Integrated electrical and physical design

• Schematic driven layo .... t

• Unique blend of full-custom and automated layout
techniques

• On-line point-to-point routing

• Complete layout verification

• Automatic place and route

• Full mixed-signal parasitic extraction

• Support of custom cells, standard cells, and compiled
blocks in any combination

• Compaction

Our design automation staff integrates the third-party tools
and optimizes their use on the Mentor platform. This framework
can easily accommodate new tools when needed, and it
enables us to support a combination of analog and digital
design techniques in all CMOS, Bipolar and BiCMOS chip
designs. By mixing design methodologies, we can achieve
optimum systems performance, even when schedules are
tight.

• Design rule checking (drc)
• Layout-versus-schematic verification (Ivs)
• Parasitic extraction/back annotation
• Output in industry standard GDS format
In the first generation Pegasys system, Silicon Systems
pioneered a device-generator based approach to precision
analog layout. In partnership with Mentor Graphics, we have
enhanced this technique for our current system, based on
Mentor Graphics va ICstation® tools. ICstation® provides tremendous flexibility, combined with ease of customization, to
fully support analog and mixed-signal designs. A variety of
layout styles and techniques are combined to meet each chip's
specific requirements. Rigorous verification checks ensure the
quality and accuracy of the layout, for both physical and electrical properties. Post-layout simulation uses true parasitic modeling to handle remaining problems before first silicon fabrication.

Electrical design
A single CAE (computer aided engineering) environment
provides for schematic capture, synthesis, simulation, and fautt
grading. We support this software with extensive libraries of
pre-designed cells and components. Highly specialized cells or
components can be designed and enhanced where required.
We simulate each circuit to meet precise performance specifications using:
• Analog circuit simUlation
• Digital logic simulation

STATE OF THE ART CMOS DIGITAL AND
ANALOG PROCESSES

• VHDL simulation
• Mixed-mode simulation

Silicon Systems offers four proven CMOS process technologies for creating cost effective, highly integrated systems solutions. These processes combine small geometry digital circuit
capability with high performance analog capability. Table 1 summarizes Silicon Systems' CMOS process capabilities.
Our newest CK process is designed to support high
breakdown, high current power FETs, 15V NPNs for specialized analog needs, poly capacitors and resistors, low noise
differential amplifiers and high performance A/D and D/A converters. It also includes highly optimized and silicon area
efficient digital cells including DSPs, microcontrollers,
sequencers, memory managers and data paths.
The CJ process provides high performance analog and
digital cells and includes the same analog and digital complex
devices in our CK process.
Our CG process supports high-performance analog circuitry with precision poly-poly capacitors. Complex analog
circuitry includes 1.25 Amp power FETs, 12-bit switched capacitor analog to digital converters and low distortion operational amplifiers and filters. Complex digital circuitry includes
DSPs, microcontrollers, sequencers, memory mangers and
data paths.

• Switched-capacitor filter simulation
• Analog and mixed-mode behavioral simulation
Admittedly, simulation alone is not the key to perfecting
performance. That's why we work aggressively to refine our
understanding of models to make them work with simulation.
Inside our progressive device modeling and characterization
(DMC) laboratory, we develop accurate circuit simulation models and parameters. The DMC lab provides complete device
model data for our processes using capabilities such as AC
measurement, statistical analysis and worst-case modeling.
Accurate models are a cornerstone of our design-for-quality
approach.
To ensure high quality test vectors, production test vectors
are derived from simulation vectors using the TSSI tools early
in the design process. The industry-standard Zycad fault simulator is then used to determine fault coverage.

Physical design
Our PEGASYS layout system aids the mask designer
through all physical design phases, ensuring consistency
throughout the design cycle. This flexible, fully integrated
environment supports a broad range of layout techniques, from
full-custom to full-automation.
1-3

I

CUSTOM SOLUTIONS

BIPOLAR & BICMOS PROCESS
TECHNOLOGIES
Our bipolar MSICs take advantage of a high-performance
Bipolar process, BN (for 5V applications).

BN - Low-powerl 8 GHz Bipolar at 5 volts
Because we employ full oxide isolation in our BN process,
we can fabricate very fast, very small transistors and reduce
sidewall capacitances. This supports not only high speed, but
low power.
The BN process features high-performance NPN transistors to support mixing high-performance emitter coupled logic
(ECL) with analog circuitry. To provide for strict TTL I/Ocompatibility, we use superior PtSi Schottky diodes.
The resulting speed and packing density allows you to
effectively implement dense high-performance, low-power
Bipolar analog/digital capability into your system designs.
For a feature-by-feature comparison of Silicon Systems'
BN Bipolar process, see Table 3.

BiCMOS process technologies
Our BiCMOS process portfolio is expanding to support the
evolving demands of the mixed-signal IC market. Now in
production is our BCA process which combines 13 GHz NPNs
with 1.01l CMOS features to support the design of efficient, high
performance, mixed-signal circuits. High bandwidth analog
circuits can be combined with dense digital logic to support the
development of 5V data channels with transfer rates into the
120+ MbiVs range, while maintaining low power consumption.
The BCA technology has also allowed our designers to develop
3V only circuits to address very low power applications.
Our second generation BiCMOS process, BCB, will provide the next step in performance with a parallel improvement
in circuit density. BCB advances our BiCMOS with o.all CMOS
feature sizes and improved interconnect capability resulting in
a significant performance step for CMOS logic. This will allow
implementation of mixed-signal circuits that support data transfer rates well beyond 200 MbiVs, while maintaining very low
power dissipation. The dense digital advantages of BCB will
also expand the possibilities for cost effective customization
and programmability in both 5V and 3V environments.
For a summary of our BiCMOS processes see Table 2.

1-4

CUSTOM SOLUTIONS

.............

. . •. . .••..• >
!

.....

I<.i<

'''''''''.;I;;,

I H'-

•. . »<
......

>

Application
........ Voltage BVDSS

............

Drawn
Gate·· . .
Length

...

..

Interconnect Pitches
Poly 1 Metal 1 Metal· 2

Features

CG

Si-Gate, dual metal,
dual poly, PWell

5V

7V

1.5 11

3.011

4.511

6.011

• DDD SID structure
• Poly-poly capacitors
• Shrinkable to 1.211

CJ

Si-Gate, dual metal,
dual poly, NWell

5V

7V

1.011

2.011

3.011

3.311

• Ldd SID structure
• Poly-poly capacitors
• Shrinkable to O.SI1

CK

Si-Gate, dual metal,
dual poly, NWell

5V

7V

O.SI1

1. 611

2.011

2.411

•
•
•
•
•

Ldd SID structure
Poly-poly capacitors
Shrinkable to 0.511
High voltage FETs
15V NPNs

TABLE 1: CMOS Process Chart

.? . . . .......
··

.-~':"~~

><

...........

.,.<

BCA:

BCB:

..>

..

..... ••.. lf~.

·tS~U~~

Drawn
Gate
Length

5V

10V

1.011

i

A

5V

SV

O.SI1

Interconnect Pitches
Poly IMO M1 M2 BVCEO
2.611

1.611

3.211 3.SI1 5.011

2.411 2.011 2.411

SV

SV

NPNFt Emitter
13 GHz

1.011

15 GHz

O.SI1

Features
Bipolar:
• High Periormance NPNs
• Polysilicon emitters
• PtSi Schottky Diodes
• Poly resisters
• Gate Oxide Capacitors
• Poly Capacitors
• Sidewall Oxide Isolation
• Fuses

CMOS:
• Lightly Doped Drains

TABLE 2: BiCMOS Process Chart

><> .............
t'TOC855.

aVD.,><······ . · •. . .••· ·

BN

Oxide-isolated

..

..

.

M2

BVcEO

NPNFt

Emitter
Size

M1
Pitch

Pitch

Features

6V

SGHz

2.011

4.511

S.OI1

•
•
•
•
•
•

TABLE 3: Bipolar Process Chart

1-5

..

High periormance NPNs
PtSi Schottky diodes
Nitride capacitors
Ion implanted resistors
Sidewall oxide isolation
Collectorlbase plugs

I

CUSTOM SOLUTIONS

Quality that delivers

A SUPERIOR FINISH FOR CMOS, BIPOLAR
ANDBICMOS

With effective systems such as PROMIS and our designfor-quality approach in place, Silicon Systems is prepared to
deliver you finished products you can really depend on. On
time. And within budget.

You might say this is the payoff window. The benefits of our
process technologies, design tools and our unique custom
approach all come together during wafer fabrication, test and
assembly.

For details on how you can take best advantage of Silicon
Systems' custom mixed-signal IC solutions, see your nearest
Silicon Systems representative, or contact us. Silicon Systems, Inc.
14351 Myford Road, Tustin, CA 92680-7022. 714-573-6000.
FAX: (714) 573-6914.

Our two manufacturing centers, located in Tustin and
Santa Cruz, California, can offer specialized capabilities to
match your particular fabrication requirements. Both facilities
provide you with high resolution stepper photolithography technology, positive resist, dry plasma etch systems, high current
ion implantation and automatic sputtering.
Fabrication sites in both Tustin and Santa Cruz accommodate
4- and 6-inch waferfabrication and Bipolar, CMOS and BiCMOS
processes.

The right package
Silicon Systems offers a wide range of packages to meet
the small footprint requirements of advanced storage and
communication products. We continue to be innovative in
surface mount technology by providing PLCC, SO, VSOP,
VTSOP, OFP, TOFP, VTOFP and UTOFP packages. At our
ISO 9002-certified Singapore assembly & test facility we have
the full capability to support high quality automated packaging
while also maintaining rapid cycle times.

Design Components
• Schematic Capture
• Simulation
• Netlisting

Rnal Design Review

Promls. Quality through CAM
Process and Management Information System (PROM IS)
underscores our commitment to computer-aided manufacturing (CAM). And to delivering you a superior quality product on
time.

• Automatic Placing
and Routing or
Hand-Packed Layout
• Automatic Circun
Trace

We use PROM IS to facilitate the data required in our
manufacturing, monitoring and statistical process control (SPC)
systems.
With PROMIS we more effectively manage our inventory,
accurately track wafers in process, and closely monitor the
clean room environment.

Test Program Creation
Photomask
WaferFab
Prototype
(Assembly, Test, Ship)

PROMIS also assists our SPC efforts, as does ourcommitment to fully train all of our manufacturing personnel in SPC
basics.

We design for quality

Evaluate Prototype

It's our view that quality is nothing less than absolute
customer satisfaction. To achieve it, we begin far "upstream" in
the product development process. Our design-for-quality
approach scrutinizes the design itself with statistically based
models, comprehensive simulation tools and vigorous design
reviews.
The results of such an effort are IC products that boast
lower defect rates, higher parametric performance and far
fewer redesigns. Moreover, our persistence in improving quality keeps us focused on finding better and faster ways to satisfy
future customer demands.

Customer Interface for Full-Custom
and Cell-Based Designs

1-6

Section

2

RELIABILITY &
QUALITY ASSURANCE

2

•

CONTINUOUS IMPROVEMENT
MISSION ~ OBJECTIVE STATEMENT
Mission
Be the supplier of choice by exceeding customer
expectations through continuous improvements in our
products, systems and services.

Objectives
Provide world class quality in our products and services
through focus on:
Customer Partnering
Cycle Time Improvement
Process and System Improvements
Develop a culture that ensures the consistent use of
continuous improvement tools and fact based decision
methodology by:
Senior Management Leadership
Employee Empowerment
Aggressive Goal Setting and Performance Measurement
Communication and Celebration of Successes

2-0

Reliability and
Quality Assurance

SECTION 1
1.1

Our Reliability and Quality Assurance organizations are
committed to working closely with our customers to provide
assistance and a continually improving level of product quality.

INTRODUCTION

Silicon Systems is committed to the goal of customer satisfaction through the on-time delivery of defect free products
that exceed the customer's expectations and requirements.
This section outlines Silicon Systems' ongoing activities for
the control and continual improvement of quality in every
aspect of our organization.

1.2

SILICON SYSTEMS' QUALITY MANDATE:

CONTINUOUS IMPROVEMENT
Continuous improvement is Silicon System's strategic thrust
for the 1990's. In order to ensure that all aspects of our
business are encompassed by this mandate, Corporate
Reliability & Quality Assurance has been chartered with the
responsibility for developing, educating and overseeing the
worldwide continuous improvement process. The continuous improvement initiative will lead to developing a new
organizational culture, changing attitudes and stronger ownership and accountability for total customer satisfaction.

Silicon Systems is diligently working to maintain and improve
its position as a world-class provider of mixed-signal integrated circuits (MSICs®).
We realize and practice the concept that quality and reliability
must be designed and built into our products. In addition,
Silicon Systems utilizes rigid inspections and data analysis to
evaluate the acceptability and variation existing in incoming
materials and performs stringent outgoing quality verification. The manufacturing process flow is encompassed by an
effective system of test/inspection checks and in-line monitors which focus on the control and reduction of process
variation. These gates and monitors ensure precise adherence to prescribed standards and procedures.

1.3

CHARACTERISTICS OF SILICON SYSTEMS'

CONTINUOUS IMPROVEMENT PROCESS
Executive Steering Committee leadership and direction - defines the right things to do and provides
guidance - the right way to do them.
Continuous improvement is measured everywhere and
by everyone. Metrics that reflect pride in accomplishment are celebrated.

Silicon Systems also incorporates the use of statistical process control techniques into company operations. The control and reduction of the process variation by the use of
statistical problem solving techniques, analytical controls
and other quantitative methods ensures that Silicon Systems'
products maintain the highest levels of quality and reliability.

Benchmarking is employed as a method to shorten
learning curves and ensure successful ventures.
Quality management and employee empowerment are
encouraged at all levels.

~ -1'--_.Si.".9"".0.re_..
.•

F.A. Lab

FIGURE 1: Organizational Chart
2-1

I

Reliability and
Quality Assurance
Supplier partnership is a critical element of our quality
strategy.

It is the practice of Silicon Systems to have corporate quality
and reliability objectives encompass all of its activities. This
starts with a strong commitmentof support from the corporate
level and continues with exceptional customer support long
after the product has been shipped.

This is the essence of Silicon Systems - a total quality
involved company -forward looking and immersed in the goal
of customer satisfaction and best-in-class business pursuits.
1.4

Silicon Systems emphasizes the belief that quality and reliability must be built into all of its products by ensuring that all
employees are educated in the quality philosophy of the
company. Some of the features built into Silicon Systems
quality culture include:

CORPORATE RELIABILITY AND
QUALITY ASSURANCE

It is the objective of the Corporate Reliability and Quality
Assurance organization to ensure that proactive quality
systems are in place to ensure that Silicon Systems' products
will meet or exceed customer requirements and expectations. In addition, the Reliability and Quality Assurance
organization works to facilitate the timely implementation of
solutions and monitors the effectiveness of corrective actions. These organizational strategies support the continuing
enhancement of quality consciousness throughout Silicon
Systems.
1.5

1.

Structured training programs directed at wafer fabrication, test, process control personnel and supporting
organizations.
- Team-based problem solving methodologies.
- Corporate-wide training of quality philosophy and
statistical methods.

2.

Stringent in-process inspections, gates, and monitors.

3.

Rigorous evaluation of designs, materials, and processing procedures.

4.

Stringent electrical testing (100% and QC AQUSampie
testing).

5.

Ongoing reliability monitors and process verifications.

6.

Real-time use of statistical process control
methodology.

7.

Corporate level audits of manufacturing, subcontractors, and suppliers.

8.

Timely corrective action system.

9.

Control of non-conforming material.

ISO 9000 CERTIFICATION

Silicon Systems has determined that ISO 9000 certification
is an important strategy for achieving total customer satisfaction. Our Singapore assembly and test operations facility has
been ISO 9002 certified through. SISIR and our domestic
facilities' quality systems have been ISO 9001 certified
through Intertek. We believe strongly that ISO 9000
certification proves that Silicon Systems is doing the right
things to do things right.

These focused quality methods result in products which
deliver superior performance and reliability in the field.

SECTION 2: QUALITY ASSURANCE
2.1

2.2.1

QUALITY OBJECTIVES

INCOMING INSPECTIONS

Incoming inspection plays a key role in Silicon Systems'
quality efforts. Small variations in incoming material can
traverse the entire production cycle before being detected
much later in the process. By paying strict attention to the
monitoring of materials at the earliest possible stage, variation can be reduced, resulting in a stable uniform process.

While all Silicon Systems employees have direct responsibility
for quality in theirfunctions, the Quality Assurance Organizations have the ultimate responsibility for the reliable performance of our products. This is accomplished through the
development, administration and assessment offormal quality systems which assure Silicon Systems' management, as
well as our customers, that products will fulfill the requirements of customer purchase orders and all other specifications.

2.2.2 IN-PROCESS INSPECTIONS
Silicon Systems has established key inspection monitors in
the following strategic areas: wafer fabrication, wafer probe,
assembly, and final test.

Corporate Quality Assurance supports, coordinates and actively participates in the formal qualification of suppliers,
material, processes, and products, and the administration of
quality systems to assure that our products meet Silicon
Systems quality standards. Product Quality Assurance provides the liaison between Silicon Systems and the customer
for all product quality related concerns. Manufacturing Quality
Assurance administers the manufacturing quality systems
and reports quality monitor data to the factory.

Quality control monitors have been integrated throughout the
manufacturing flow, so that data may be collected and analyzed to verify the results of intermediary manufacturing
steps. This data is used to document quality trends or long
term improvements in the quality of specific operations.

2-2

Reliability and
Quality Assurance
sign-related functions include ensuring that process specification revisions are translated into updated design parameters and the translation of manufacturing process capability
into design guidelines. This is accomplished through the
identification and monitoring of critical process and device
parameters. Wafer level test at the early stages of process
development also plays a critical role. These elements, included in Silicon Systems design for quality effort, support the
development of robust design rules which are as insensitive
as possible to inherent manufacturing variation. The result is
a product that delivers predictable and reliable long term
performance.

2.5

PPM REDUCTION PROGRAM

The primary purpose of a PPM reduction program is to
provide a formalized feedback system in which data from
nonconforming products can be used to improve future
product consistency and reliability. The action portion of this
program is accomplished in three stages:

FIGURE 2
Quality Assurance Relationships
Quality Steering Committee

1.

Identification of defects by failure mode.

2.

Identification of defect causes and initiation of corrective
action.

3.

Measurement of results and setting of improved goals.

The data summarized from the established PPM program is
compiled as a ratio of units rejectedltested. This ratio is then
expressed in terms of defective parts per million (PPM).
Founded on a statistically valid database of PPM data and an
established five-year strategic plan identifying PPM improvement goals, Silicon Systems has consistently achieved excellent quality standards and will continue to progressively
improve PPM standards.

Abnormality control is being used to enhance the effectiveness of this process. In process monitors such as oxide
integrity, electromigration immunity and other parameters
monitor long term reliability as well as circuit performance.

2.3 QUALITY STEERING COMMITTEE
The Corporate, Product and Manufacturing Quality Assurance organizations work closely together to provide leadership in the development, integration and assessment of
Silicon Systems' worldwide quality systems and procedures.

2.6

COMPUTER AIDED MANUFACTURING CONTROL

Computer Aided Manufacturing (CAM) is used throughout
Silicon Systems for the identification, control, collection and
dissemination of timely information for logistics control. Silicon Systems also uses this type of computerized system for
statistical process control and manufacturing monitoring.
PROMIS, (PROcess Management and Information System),
displays approved/controlled recipes, processes, and procedures; tracks work-in-process; reports accu\ate inventory
information; allows continuous recording of facilities data;
contains statistical analysis capabilities; and much more.
PROMIS allows for a paperless facility, a major element in
minimizing contamination of clean room areas.

This team approach ensures that policies and procedures are
standardized and facilitates rapid improvement in products,
processes and services.

2.4 DESIGN FOR QUALITY
Since the foundation of a reliable product is rooted in the
design process, the Reliability and Quality Assurance organizations actively participate in comprehensive cross-functional reviews of design stages priorto the product's transition
to production status. These review stages assure a predictable and effective development cycle. Other important de-

2-3

I

Reliability and
Quality Assurance

TEST

CONDITIONS

PURPOSE OF EVALUATION

Biased temperature/humidity
Highly accelerated stress test (HAST)
High temperature operating life (HTOL)
Early Failure Rate
Steam pressure
Temperature cycling
Thermal shock
Salt atmosphere
Constant acceleration
Mechanical shock
Solderability
Lead integrity
Vibration, variable frequency
Thermal resistance
Electrostatic damage
Latch-up
Seal fine and gross leak

85°C/85° %RH
JDEC A110
Mil 883D, Method 1005
Mil 883D, Method 1005
121°C/15PSI
Mil 883D, Method 1010
Mil 883D, Method 1011
Mil 883D, Method 1009
Mil 883D, Method 2001
Mil 883D, Method 2002
Mil 883D, Method 2003
Mil 883D, Method 2004
Mil 883D, Method 2007
Silicon Systems Method
Mil 883D, Method 3015
Silicon Systems Method
Mil Std 883D, Method 1014

Resistance to high humidity with bias
Evaluates package integrity
Resistance to electrical and thermal stress
Detect infant mortality
Resistance to hiQh humidity
Resistance to thermal excursion (air)
Resistance to thermal excursion (liquid)
Resistance to corrosive environment
Resistance to constant acceleration
Resistance to mechanical shocks
Evaluates solderability of leads
Evaluates lead int~grity before board assembly_
Resistance to vibration
Evaluates thermal dissi~ation
Evaluates ESD susceptability
Evaluates latch-up susceptibility
Evaluates hermeticity of sealed packages

TABLE 1: Reliability Stress Tests

SECTION 3: RELIABILITY
3.1

database generated by means of accelerated stress testing
results in a high degree of confidence in predicting final use
performance. The qualification criteria used are periodically
reviewed to be consistent with Silicon Systems' increasing
quality and reliability goals in support of our customers.

RELIABILITY PROGRAM

A primary objective at Silicon Systems is to improve the
reliability of our products through characterization of our
manufacturing operations. The identification of specific failure
mechanisms occuring in the wafer fabrication and assembly
processes is a prerequisite to effective corrective action
aimed at reducing defects and improving quality and reliability.

3.3

Silicon Systems has defined various programs that will
characterize product reliability levels on a continuous basis.
These programs can be categorically described by:
1.
2.

Production monitors
Evaluations

4.

Failure analysis

5.

Wafer level reliability

6.

Data collection and presentation for improvement
projects

3.2

Table 1 lists reliability test methods that are in use at Silicon
Systems. This analysis of production monitor at Silicon
Systems provides valuable information on possible design/
process changes which assure continued improved reliability.
The monitors are periodically reviewed for effectiveness and
improvements.

Qualifications

3.

PRODUCTION MONITORS

This program has been established to randomly select a
statistically significant sample of production products for
subjection to maximum stress test levels in order to evaluate
the useful life of the product in a field use environment.

3.4

EVALUATIONS

The evaluation program at Silicon Systems is an ongoing
effort that defines standards which address the reliability
assessment of the circuit design, process parameters, and
package of a new product. This program continuously analyzes updated performance characteristics of product as they
undergo improvement efforts at Silicon Systems.

QUALIFICATIONS

Extensive qualification testing and data collection ensures
that all new product designs, processes, and packaging
configurations meet the absolute maximum ratings of design
and the worst case performance criteria for end users. A large

2-4

Reliability and
Quality Assurance
3.5

FAILURE ANALYSIS

3.8

The failure analysis function is an integral part of the Quality
and Reliability department at Silicon Systems. Silicon Systems has assembled a highly technical and sophisticated
failure analysis laboratory and staff. This laboratory provides
visual analysis, electrical reject mode analysis, and both
destructive and non-destructive data to aid the engineers in
developing corrective action for improvement. These test
analyses may include metallurgical, optical, chemical, electrical, SEM with X-ray dispersive analysis, and E-Beam noncontact analysis as needed.

3.9

The model basically states FR = A exp(-Ea/KT)
Where:

WAFER LEVEL RELIABILITY PROGRAM

The primary advantage of wafer level reliability testing is the
speed at which results can be derived, thereby providing
additional response time and an early warning of process
changes. This tool provides Silicon Systems with a very rapid
analysis tool which allows for the early identification of
possible problems and a determination of their origin.

FR

Failure rate

A

Constant

Ea

Activation Energy (eV)

K

Boltzmann's constant 8.62 x 10- 5 eVI degree K

T

Absolute temperature (degree K)

SECTION 4:

4.1

ELECTROSTATIC DISCHARGE
PROGRAM

ESD PREVENTION

Silicon Systems recognizes that the protection of Electrostatic Discharge (ESD) sensitive devices from damage by
electrical transients and static electricity is vital. ESD safe
procedures are incorporated throughout all operations which
come in contact with these devices. Continuous improvement in the ESD protection levels is being accomplished
through the incorporation of increasingly robust protection
devices during the circuit design process as well as work area
improvements_

The continuous improvement approach taken at Silicon
Systems uses wafer level reliability tests as tools to improve
the process, identify potential problems, determine the sources
of any process weakness and eliminate problems upstream
in the process. This results in a focus on reliability improvementthat goes well beyond merely determining the projected
lifetime of a product to a detailed characterization, measurement and control of the specific parameters which actuailly
determine product lifetime.

3.7

RELIABILITY PREDICTION METHODOLOGY

At Silicon Systems, the Arrhenius model is used to relate a
failure rate at an accelerated temperature test condition to a
normal use temperature condition.

These conclusive in-house testing and analysis techniques,
are complemented by outside support, such as scanning
acoustic microscopy, focused ion beam, and complete surface and material analysis. This allows Silicon Systems to
monitor all aspects of product manufacturing to ensure that
the product of highest quality is shipped to our customers.

3.6

RELIABILITY METHODS

The Reliability Program utilizes a number of stress tests that
are presently being used to define performance levels of our
products. Many of these stress tests are per MIL-STD-883D
as shown in Table 1.

Silicon Systems' quality activity incorporates several protection measures forthe control of ESD. Some of the preventive
measures include handling of parts at static safe-guarded
workstations, the wearing of wrist straps dudng all handling
operations, the use of conductive lab coats in all test areas
and all areas which handle parts and the packaging of
components in conductive or anti-static containers.

DATA COLLECTION AND PRESENTATION FOR
IMPROVEMENT PROJECTS

Data collected from each element of the Reliability program
is summarized for scope and impact and distributed among
all engineering disciplines in the company. This data facilitates improvement and provides our customers an opportunity to review the performance of our product.

2-5

•

NOTES

2-6

Section

3

K-SERIES
SINGLE-CHIP
MODEM FAMILY

3

I

Introduction
Silicon Systems' K-Series Family of One-Chip Modems
Silicon Systems is a leader in the design and manufacturing of CMOS VLSI modems. Currently, Silicon
Systems offers the most extensive line of one-chip
modem ICs available, with high-performance, costeffective designs suitable for a wide range of applications. Silicon Systems' fully compatible modem IC
family has redefined the modem IC as a universal
component which can be easily integrated into any
system. Designs can be upgraded to meet different
standards and speeds by simply substituting one KSeries IC for another. Using a K-Series family modem
IC in your application eliminates product obsolesence,
and minimizes development costs.

addition, an innovative bus structure makes a separate
controller unnecessary in dedicated integral designs.
All K-Series devices are available in low-power versions. This feature allows optimal performance with
single +5V supply operation and is unique to Silicon
Systems' products.
Silicon Systems' single-chip modem IC family is
designed to be the most effective solution for a wide
variety of modem applications. The products provide
for a full range of communications standards and
speeds up to 2400 bit/so Moreover, features can be
extended to include additional modes and higher
operating speeds without impacting existing designs.
Take advantage of these capabilities. Design for
tomorrow's needs today by using Silicon Systems'
K-Series modem IC family.

The Silicon Systems modem IC family consists of four
basic products:
1.

The SSI 73K222L, a multi-mode device which
combines both Bell 212AJ1 03 and V.22N.21 capability in one chip, with operating modes at 0 - 30,
600 and 1200 bit/so

2.

The SSI 73K222U which combines the functionality of the 73K222L with the industry standard
16C450 UART.

3.

The SSI 73K224L, a major technological breakthrough which provides 2400 bit/s V.22bis operation in addition to V.22N.21 and Bell 212AJ103
modes in a single IC.

4.

K-Series Modem Design Manual
The Silicon Systems K-Series Modem Design Manual
contains a large body of application literature for the
K-Series family of single chip modem products. This
manual is intended as a tutorial for those users who
may be designing with modems for the first time, and
also as a helpful guide for more experienced modem
designers.

K·SERIES
MODEM
DESIGN
MANUAL

The SSI 73K322L provides CCID V.22N.21 plus
V.23 Videotex modes.

New additions to Silicon Systems' modem IC family
extend the available operating modes and provide
features which greatly simplify integral modem design.
The SSI 73K324L offers V.22bis, V.22N.21 and V.23
operating modes on one chip. These products dramatically reduce external circuitry required for dedicated integral modem designs.
Silicon Systems' one-chip modem IC products represent technical achievements unmatched in the industry. An advanced Digital Signal Processor resides on
the same chip with sophisticated analog circuitry in the
SSI 73K224L and SSI73K324L products. "U" versions
of the K-Series devices integrate an industry standard
UART with full modem capability on a single chip. In

The K-Series Modem Design Manual is available
through our worldwide network of representatives and
distributors.
3-0

SSI73K212L
Bell 212A/103
Single-Chip Modem

January 1994

DESCRIPTION

FEATURES

The SSI 73K212L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a typical Bell 212A full-duplex modem.
Using an advanced CMOS process that integrates
analog, digital and switched-capacitor filter functions
on a single substrate, the SSI73K212L offers excellent
performance and a high level of functional integration
in a single 28-Lead PLCC, 28- or 22-pin 01 P configuration. The SSI 73K212L operates from a single +5V
supply.

One-chip Bell 212A and 103 standard compatible
modem data pump
Full-duplex operation at 0-300 bitls (FSK) or
1200 bitls (OPSK)
Pin and software compatible with other
SSI K-Series 1-chip modems
Interfaces directly with standard microprocessors
(8048, 80C51 typical)
Serial or parallel microprocessor bus for control

The SSI 73K212L includes the OPSK and FSK modulator/demodulator functions, call progress and handshake tone monitor test modes and a OTMF dialer.
This device supports all Bell 212A modes of operation
allowing both synchronous and asychronous communications.

Both synchronous and asynchronous modes of
operation
Call progress, carrier, precise answer tone and
long loop detectors
OTMF generators

Test features such as analog loop, digital loop, and
remote digitalloopback are provided. Internal pattern
generators are also included for self-testing. The SSI
73K212L is designed to appear to the systems designer as a microprocessor peripheral, and will easily
interface with popular one-chip microprocessors

Test modes available: ALB, OL, ROL, Mark, Space,
Alternating bit patterns
Precise automatic gain control allows 45 dB
dynamic range
CMOS technology for low power consumption
using 30 mW @ 5V
Single +5V supply

Serial port for data transfer

(Continued)

PIN DIAGRAM

BLOCK DIAGRAM

ClK
ADf>-MJ7

XTl1
XTl2

AD
VIA

0 - - -_ _

TXA

ALE D--~

os

D--~

RESET

m
~D
RXD

GND
RXA
VREF

ADO

RESET

AD1

ISET

AD2

RXClK

AD3

RXD

AD4

TXD

0------1

ADS
AD6

D-----------~

n--------------1

EXClK

AD7
ALE

INT

WR

TXA

RD

VDD

CAUTION: Use handling procedures necessary
for a static sensitive component.

0194 - rev.

3-1

I

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
DESCRIPTION (Continued)

Serial data from the demodulator is passed first
through the data descrambler and then through the
SYNC/ASYNC rate converter. The SYNC/ASYNC
convertor will reinsert any deleted stop bits and transmit output data at an intra-character rate (bit-to-bit
timing) of no greaterthan 1219 bit/so An incoming break
signal (lOW through two characters) will be passed
through without incorrectly inserting a stop bit.

(80C51 typical) for control of modem functions through
its 8-bit multiplexed address/data bus or serial control
bus. An ALE control line simplifies address demultiplexing. Data communications occurs through a separate serial port only.
The SSI73K212L is ideal for use in either free standing
or integral system modem products where full-duplex
1200 bit/s data communications over the 2-wire
switched telephone network is desired. Its high functionality, low power consumption and efficient packaging simplify design requirements and increase system
reliability. A complete modem requires only the addition of the phone line interface, a control microprocessor, and RS-232 level convertor for a typical system.
The SSI73K212L is part of SSi's K-Series family of pin
and function compatible single-chip modem products.
These devices allow systems to be configured for
higher speeds and Bell or CCITT operation with only a
single component change.

SYNCHRONOUS MODE
The Bell 212A standard defines synchronous operation only at 1200 bitls. Operation is similar to that of the
asynchronous mode except that data must be synchronized to a provided clock and no variation in data
transfer rate is allowable. Serial input data appearing at
TXD must be valid on the rising edge of TXCLK.
TXCLK is an internally derived 1200 Hz Signal in
internal mode and is connected internally to the
RXCLK pin in slave mode. Receive data at the RXD pin
is clocked out on the falling edge of RXCLK. The
ASYNCH/SYNCH converter is bypassed when synchronous mode is selected and data is transmitted out
at the same rate as it is input.

OPERATION

ASYNCHRONOUS MODE

DPSK MODULATOR/DEMODULATOR

Data transmission for the DPSK mode requires that
data ultimately be transmitted in a synchronous fashion. The SSI 73K212L includes ASYNC/SYNC and
SYNC/ASYNC converters which delete or insert stop
bits in order to transmit data within a 0.01% rate. In
asynchronous mode the serial data comes from the
TXD pin into the ASYNC/SYNC converter. The
ASYNC/SYNC converter accepts the data provided on
the TXD pin which normally must be 1200 bitls +1.0%,
- 2.5%. The rate converterwill then insert or delete stop
bits in orderto output a signal which is 1200 bitls ± .01 %
(±.01% is the required synchronous data rate
accuracy).

The SSI 73K212L modulates a serial bit stream into
dibit pairs that are represented by four possible phase
shifts as prescribed by the Bell 212A standard. The
baseband signal is then filtered to reduce intersymbol
interference on the bandlimited 2-wire telephone line.
Transmission occurs using either a 1200 Hz (originate
mode) or 2400 Hz carrier (answer mode). Demodulation is the reverse of the modulation process, with the
incoming analog signal eventually decoded into di-bits
and converted back to a serial bit stream. The demodulator also recovers the clock which was encoded into
the analog signal during modulation. Demodulation
occurs using either a 1200 Hz carrier (answer mode or
ALB originate mode) or a 2400 Hz carrier (originate
mode or ALB answer mode). The SSI73K212L uses a
phase locked loop coherent demodulation technique
for optimum receiver performance.

The serial data stream from the ASYNC/SYNC converter is passed through the data scrambler and onto
the analog modulator. The data scrambler can be
bypassed under processor control when unscrambled
data must be transmitted. The ASYNC/SYNC rate
converter and the data scrambler are bypassed in all
FSK modes. If serial input data contains a break signal
through one character (including start and stop bits) the
break will be extended to at least 2· N + 3 bits long
(where N is the number of transmitted bits/character).

FSK MODULATOR/DEMODULATOR
The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. In the Bell 103, the standard
frequencies of 1270 and 1070 Hz (originate, mark and

3-2

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
space) or 2225 and 2025 Hz (answer, mark and space)
are used. V.21 mode uses 980 and 1180 Hz (originate,
mark and space) or 1650 and 1850 Hz (answer, mark
and space). Demodulation involves detecting the received frequencies and decoding them into the
appropriate binary value. The rate converter and
scrambler/descrambler are bypassed in the 103 mode.

EXCLK. WR is then pulsed low and data transferred
into the selected register occurs on the rising edge of
WR.

SPECIAL DETECT CIRCUITRY
The special detect circuitry monitors the received
analog Signal to determine status or presence of carrier, call-progress tones, answer tone and weak received signal, (long loop condition). An unscrambled
mark request signal is also detected when the received
data out oft he DPSK demodulator before the descrambier has been highfor165.5ms±6.5ms minimum. The
appropriate detect register bit is set when one of these
conditions changes and an interrupt is generated for all
purposes except long loop. The interrupts are disabled
(masked) when the enable interrupt bit is set to O.

PASSBAND FILTERS AND EQUALIZERS
High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay equalization and rejection of out-of-band signals in the
receive channel. Amplitude and phase equalization
are necessary to compensate for distortion of the
transmission line and to reduce intersymbol interference in the bandlimited receive signal. The transmit
signal filtering approximates a 75% square root of
raised Cosine frequency response characteristic.

DTMF GENERATOR
The DTMF generator will output one of 16 standard
tone pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mode
is selected using the tone register and the transmit
enable (CRO bit D1) is changed from 0 to 1.

AGC
The automatic gain control maintains a signal level at
the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping and provides a total
receiver dynamic range of >45 dB.

PARALLEL BUS INTERFACE
Four 8-bit registers are provided for control, option
select and status monitoring. These registers are addressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as four consecutive memory locations. Two control registers and the tone register are
read/write memory. The status detect register is read
only and cannot be modified except by modem
response to monitored parameters.

SERIAL COMMAND INTERFACE
The serial command mode allows access to the
SSI 73K212L control and status registers via a serial
command port (22-pin version only). In this mode the
AO, A1 and A21ines provide register addresses for data
passed through the data pin under control of the RD
and WR lines. A read operation is initiated when the RD
line is taken low. The next eight cycles of EXCLK will
then transfer out eight bits of the selected address
location LSB first. A write takes place by shifting in eight
bits of data LSB first for eight consecutive cycles of
3-3

3

SSI73K212L
Bell 212A/103
Single-Chip Modem
PIN DESCRIPTION
POWER
28·PIN

22·PIN

TYPE

DESCRIPTION

GND

28

1

I

System Ground.

VDD

15

11

I

Power supply input, 5V ± 10% (?3K212l). Bypass with .1
and 22 f..lF capacitors to ground.

VREF

26

21

0

An internally generated reference voltage. Bypass with
0.1 f..lF capacitor to GND.

ISET

24

19

I

Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 MQ resistor. ISET should be bypassed to GND with a
0.1 f..lF capacitor.

NAME

PARALLEL MICROPROCESSOR INTERFACE
12

-

I

Address latch enable. The falling edge of ALE la~ches the
address on ADO-AD2 and the chip select on CS.

4-11

-

I/O

Address/data bus. These bidirectional tri-state multiplexed lines carry information to and from the internal
registers.

CS

20

-

I

Chip select. A low during the falling edge of ALE on this pin
allows a read cycle or a write cycle to occur. ADO-AD? will
not be driven and no registers will be written if CS (latched)
is not active. The state of CS is latched on the falling edge
of ALE.

ClK

1

2

0

Output clock. This pin is selectable under processor control
to be either the crystal frequency (for use as a processor
clock) or 16 x the data rate for use as a baud rate clock in
DPSK modes only. The pin defaults to the crystal frequency
on reset.

INT

1?

13

0

Interrupt. This open drain output signal is used to inform the
processor that a detect flag has occurred. The processor
must then read the detect register to determine which
detect triggered the interrupt. INT will stay low until the
processor reads the detect register or does a full reset.

RD

14

-

I

Read. A low requests a read of the SSI 73K212l internal
registers. Data cannot be output unless both RD and the
latched CS are active or low.

ALE
ADO-AD?

3-4

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
PARALLEL MICROPROCESSOR INTERFACE (Continued)
NAME

2S-PIN

22-PIN

TYPE

RESET

25

20

I

Reset. An active high signal on this pin will put the chip into
an inactive state. All control register bits (CRO, CR1 , Tone)
will be reset. The output of the CLK pin will be set to the
crystal frequency. An internal pull down resistor permits
power on reset using a capacitor to VDD.

WR

13

-

I

Write. A low on this informs the SSI 73K212L that data is
available on ADO-AD7 for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are low.

DESCRIPTION

SERIAL MICROPROCESSOR INTERFACE
AO-A2

-

5-7

I

Register Address Selection. These lines carry register
addresses and should be valid during any read or write
operation.

DATA

-

8

I/O

Serial Control Data. Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs data.

RD

-

10

I

Read. A low on this input informs the SSI 73K212L that
data or status information is being read by the processor.
The falling edge of the RD signal will initiate a read from the
addressed register. The RD signal must continue for eight
falling edges of EXCLK in order to read all eight bits of the
referenced register. Read data is provided LSB first. Data
will not be output,unless the RD signal is active.

WR

-

9

I

Write. Alowonthis input informs the SSI73K212L that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on
the DATA pin for eight consecutive falling edges of EXCLK
and then to pulse WR low. Data is written on the rising edge
ofWR.

Note:

In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the
pins; AD, A 1 , A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.
The Serial Control mode is provided in the parallel control versions by tying ALE high and CS low.
In this configuration AD7 becomes DATA and ADO, AD1 and AD2 become AD, A1 and A2,
respectively.

3-5

I

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
DTE USER INTERFACE
NAME

28-PIN

22-PIN

TYPE

EXCLK

19

15

I

External Clock. This signal is used in synchronous transmission when the external timing option has been selected.
In the external timing mode the rising edge of EXCLK is
used to strobe synchronous DPSK transmit data applied to
the TXD pin. Also used for serial control interface.

RXCLK

23

18

0

Receive Clock. The falling edge of this clock output is
coincident with the transitions in the serial received data
output. The rising edge of RXCLK can be used to latch the
valid output data. RXCLK will be valid as long as a carrier
is present.

RXD

22

17

0

Received Data Output. Serial receive data is available on
this pin. The data is always valid on the rising edge of
RXCLK when in synchronous mode. RXD will output constant marks if no carrier is detected.

TXCLK

18

14

0

Transmit Clock. This signal is used in synchronous transmission to latch serial input data on the TXD pin. Data must
be provided so that valid data is available on the rising edge
of the TXCLK. The transmit clock is derived from different
sources depending upon the synchronization mode
selection. In Internal Mode the clock is generated internally.
In External Mode TXCLK is phase locked to the EXCLK pin.
In Slave Mode TXCLK is phase locked to the RXCLK pin.
TXCLK is always active.

TXD

21

16

I

Transmit Data Input. Serial data for transmission is applied
on this pin. In synchronous modes, the data must be valid
on the rising edge of the TXCLK clock. In asynchronous
modes (1200 bitls or 300 baud) no clocking is necessary.
DPSK data must be 1200 bitls +1%, -2.5%.

DESCRIPTION

ANALOG INTERFACE AND OSCILLATOR
RXA

27

22

I

Received modulated analog signal input from the telephone line interface.

TXA

16

12

0

Transmit analog output to the telephone line interface.

XTL1
XTL2

2
3

3
4

I
I

These pins are for the internal crystal oscillator requiring
a 11.0592 MHz parallel mode crystal and two load capacitors to Ground. Consult crystal manufacturer for proper
valves. XTL2 can also be driven from an external clock.

3-6

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
REGISTER DESCRIPTIONS

line. CR1 controls the interface between the microprocessor and the SSI 73K212L internal state. DR is a
detect register which provides an indication of monitored modem status conditions. TR, the tone control
register, controls the DTMF generator, answer and
guard tones and RXD output gate used in the modem
initial connect sequence. All registers are read/write
except for DR which is read only. Register control and
status bits are identified below:

Four a-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AO, A 1 and
A2 address lines in serial mode, or the ADO, AD1 and
AD2 lines in parallel mode. In parallel mode the address lines are latched by ALE. Register CRO controls
the method by which data is transferred over the phone
REGISTER BIT SUMMARY

I

CRO

CONTROL
REGISTER

CRl

001

1
DETECT
REGISTER

DR

010

TONE
CONTROL
REGISTER

TR

011

CR2

100

CR3

101

10

110

CONTROL
REGISTER

ENABLE
DETECT
INTERRUPT

BYPASS
SCRAMBLER

RECEIVE
DATA

UNSCR.
MARKS

CARRIER
DETECT

TRANSMIT
DTMF

DTMF3

2
CONTROL
REGISTER
3
10
REGISTER

NOTE:

When a register containing reserved control
bits is written into, the reserved bits must be
programmed as O's.

3-7

CLK
CONTROL

1

TEST
MODE
0

ANSWER
TONE

CALL
PROGRESS

LONG
LOOP

DTMF2

DTMFl

DTMFO

RESET

TEST
MODE

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
REGISTER ADDRESS TABLE

OOOO=PWR DOWN
0OO1-INT SYNCH
0010-EXT SYNCH
0011=SLAVE SYNCH
0100=ASYNCH 8 BITSICHAR
0101=ASYNCH 9 BITSICHAR
0110=ASYNCH 10 BITSICHAR
0111 =ASYNCH 11 BITS/CHAR
1100=FSK

O-XTAL
1=16 X DATA
RATE OUTPUT
ATCLK PIN IN
DPSKMODE
ONLY

00XX=73K212L. 322L. 321 L
01 XX=73K221 L. 302L
10XX=73K222L
1100=73K224L
1110=73K324L
1101 =73K312L

3-8

O=DISABLE
TXA OUTPUT
1=ENABLE
TXAOUTPUT

O=ANSWER
1=ORIGINATE

SSI73K212L
Bell 212A/1 03
Single-Chip Modem

CONTROL REGISTER 0

05

04

03

02

01

DO

TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/
MODE 2
MODE 1
MODE 0
ENABLE ORIGINATE
MODE 3
BIT NO.

DO

NAME

CONDITION

Answer/
Originate

o

DESCRIPTION
Selects answer mode (transmit in high band, receive
in low band).
Selects originate mode (transmit in low band, receive in
high band).

01

o

Transmit

TXA.

Enable

Enables tran

TXA.

Note: Answer tone and OTMF TX control require TX
enable.

05,04,03,
02

Transmit
Mode

o

000

000

o

0

o

0

External synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internally to EXOLK pin, and a 1200 Hz clock must be
supplied externally.
Slave synchronous mode. Same operation as other
synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.

o

o

o

o

Internal synchronous mode. In this mode TXCLK is an
internally derived 1200 Hz signal. Serial input data
appearing at TXO must be valid on the rising edge of
TXCLK. Receive data is clocked out of RXO on the
falling edge of RXCLK.

o

o

o

Selects power down mode. All functions
disabled except digital interface.

0

Selects OPSK asynchronous mode - 8 bits/character
(1 start bit, 6 data bits, 1 stop bit).
Selects OPSK asynchronous mode - 9 bits/character
(1 start bit, 7 data bits, 1 stop bit).

o

Selects OPSK asynchronous mode - 10 bits/character
(1 start bit, 8 data bits, 1 stop bit).
Selects OPSK asynchronous mode - 11 bits/character
(1 start bit, 8 data bits, Parity and 1 stop or 2 stop bits).

3-9

•

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
CONTROL REGISTER 1

CR1
001
BIT NO.

07

06

05

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

ENABLE
DETECT
INTER.

NAME

CONDITION

04

02

01

DO

RESET

TEST
MODE
1

TEST
MODE
0

03

BYPASS
ClK
SCRAMB CONTROL

DESCRIPTION

01 DO
01, DO

02

03

04

05

Test Mode

Reset

ClK Control
(Clock Control)

Bypass
Scrambler

Enable Detect
Interrupt

0

0

Selects normal operating mode.

0

1

Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin. transmit enable bit must be low.

1

0

Selects remote digital loopback. Received data is
looped back to transmit data internally, and RXO is
forced to a mark. Data on TXO is ignored.

1

1

Selects local digital loopback. Internally loops TXO
back to RXO and continues to transmit data carrier at
the TXA pin.

0

Selects normal operation.

1

Resets modem to power down state. All control register bits (CRO, CR1. Tone) are reset to zero. The output
of the ClK pin will be set to the crystal frequency on
reset.

0

Selects 11.0592 MHz crystal echo output at ClK pin.

1

Selects 16 X the data rate. output at ClK pin in OPSK
modes only.

0

Selects normal operation. OPSK transmn data is passed
through scrambler.

1

Selects Scrambler Bypass. Bypass OPSK data is
routed around scrambler in the t~ansmit path.
--

0

Disables interrupt at INT pin.

1

Enables INT output. An interrupts will be generated
with a change in status of DR bits 01-04. The answer
tone and call progress detect interrupts are masked
when the TX enable bit is set. Carrier detect is masked
when TX OTMF is activated. All interrupts will be
disabled if the device is in power down mode.

3-10

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
CONTROL REGISTER 1

CR1
001
BIT NO.

(Continued)

07

06

05

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

ENABLE
OETECT
INTER.

NAME

CONDITION

04

03

BYPASS
ClK
SCRAMB CONTROL

02

01

00

RESET

TEST
MOOE
1

TEST
MOOE
0

DESCRIPTION

07 06
07,06

Transmit
Pattern

0

0

Selects normal data transmission as controlled
by the state of the TXO pin.

0

1

Selects an alternating mark/space transmit pattern for
modem testing.

1

0

Selects a constant mark transmit pattern.

1

1

Selects a constant space transmit pattern.

DETECT REGISTER

BIT NO.

NAME

CONDITION.

00

lONG lOOP

0

01

CAll
PROGRESS
OETECT

02

03

04

DESCRIPTION
Indicates normal received signal.

Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in
the 350 to 620 Hz call progress band.

ANSWER
TONE
DETECT

0

CARRIER
DETECT

0

UNSCRAMBlEO
MARK

0

No answer tone detected.
Indicates detection of 2225 Hz answer tone. The
device must be in originate mode for detection of
answer tone.
No carrier detected in the receive channel.
Indicated carrier has been detected in the received
channel.
No unscrambled mark.
Indicates detection of unscrambled marks in the
received data. A valid indication requires that
unscrambled marks be received for> 165.5 ± 6.5 ms.

3-11

I

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
DETECT REGISTER (Continued)

NAME

BIT NO.
D5

D5

D4

D3

D2

D1

DO

RECEIVE
DATA

UNSCR.
MARK

CARR.
DETECT

ANSWER
TONE

CALL
PROG.

LONG
LOOP

CONDITION

RECEIVE
DATA

DESCRIPTION
Continuously outputs the received data stream. This
data is the same as that output on the RXO pin, but it
is not disabled when RXD is tri-stated.

06,07

Not used.

TONE REGISTER

TR
011
BIT NO.

D7

05

D4

03

D2

D1

DO

RXD
OUTPUT
CONTR.

TRANSMIT
ANSWER
TONE

TRANSMIT
DTMF

DTMF3

DTMF2

DTMF 1

DTMFO

NAME

CONDITION

DESCRIPTION

03 D2 D1 DO
D3, D2,
D1, DO

DTMF

o
1

0
1

0
1

01

Programs 1 of 16 DTMF tone pairs that will be
transmitted when TX DTM F and TX enable bit (CRO, bit
D1) are set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT

o
3-12

DTMF CODE
D3 D2 D1 DO

000

0

TONES
LOW HIGH

941

1633

SSI73K212L
Bell 212A/1 03
Single-Chip Modem

TONE REGISTER (Continued)

TR
011

07

05

04

03

02

01

00

RXO
OUTPUT
CONTR.

TRANSMIT
ANSWER
TONE

TRANSMIT
OTMF

OTMF 3

OTMF 2

OTMF 1

OTMFO

BIT NO.
04

NAME

CONDITION

TRANSMIT
OTMF

o

DESCRIPTION
Disable OTMF.
Activates OTMF. The selected OTMF tones are
transmitted continuously when this bit is high (with
Transmit Enable, CRO-01). TX OTMF overrides all
other transmit functions.

TRANSMIT
ANSWER
TONE

05

07

RXO OUTPUT
CONTROL

Enables answer tone generator. A 2225 Hz answer
tone will be transmitted continuously when the Transmit Enable bit is set in CRO. The device must be in
answer mode.

o

Enables RXO pin. Receive data will be output on
RXO.
Oisables RXO pin. The RXO pin reverts to a high
impedance with internal, weak pull-up resistor.

10 REGISTER

10

07

06

05

04

03

10

10

10

10

10 .

110
BIT NO.

NAME

CONDITION
07 06 05 04

07, 06, 05
04

DESCRIPTION
Indicates Oevice:
73K321L

Oevice
Identification
Signature

3-13

•

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER

RATING

VDD Supply Voltage

14 V

Storage Temperature

-65 to 150°C

Soldering Temperature (10 sec.)

260°C

Applied Voltage

-0.3 to VDD + 0.3 V

--

Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.

RECOMMENDED OPERATING CONDITIONS
P~RAMETER

MIN

NOM

MAX

UNITS

VDD Supply Voltage

4.5

5

5.5

V

TA, Operating Free-Air
Temperature

-40

+85

°C

-0.01

+0.01

%

2.2

MQ

Clock Variation

CONDITIONS

(11.0592 MHz) Crystal or
external clock

External Components (Refer to Application section for placement.)
VREF Bypass capacitor

(External to GND)

0.1

Bias setting resistor
and ISET pins)

(Placed between VDD

1.8

ISET Bypass capacitor

(ISET pin to~ND)

0.1

IJ.F

VDO Bypass capacitor 1

(External to Gr'JD)

0.1

IJ.F

VDO Bypass capacitor 2

(External to GNO)

22

XTL 1 Load CapaCitor

Depends on crystal characteristics;

40

XTL2 Load Capacitor

from pin to GND

20

3-14

IJ.F
2

IJ.F
pF

SSI73K212L
Bell 212A11 03
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)
PARAMETER

CONDITIONS

100, Supply Current

ISET Resistor

MIN

NOM

MAX

UNITS

8

= 2 MQ

IDDA, Active

ClK = 11.0592 MHz

12

rnA

1001, Power-down

ClK = 11.0592 MHz

4

rnA

1002, Power-down

ClK = 19.200 kHz

3

rnA

--

Digital Inputs
VIH, Input High Voltage
Reset, XTl1 , XTl2

3.0

VDD

V

All other inputs

2.0

VDD

V

0.8

V

100

~

Vll, Input low Voltage

0

IIH, Input High Current

VI

= VIH Max

Ill, Input low Current

VI = Vil Min

-200

Reset Pull-down Current

Reset = VDD

1

Input Capacitance

All Digital Input Pins

~

50

~

10

pF

VDD

V

Digital Outputs
2.4

VOH, Output High Voltage

10H MIN = -0.4 rnA

VOL, Output low Voltage

10 MAX=1.6 rnA

0.4

V

VOL, ClK Output

10 = 3.6 rnA

0.6

V

RXD Tri-State Pull-up Curr.

RXD=GND

-50

~

CMAX, ClK Output

Maximum Capacitive load

15

pF

-1

3-15

•

SSI73K212L
Bell 212AJ1 03
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to + 85°C, VDD = recommended range unless otherwise noted.)
PARAMETERS

CONDITIONS

MIN

NOM

MAX

UNITS

PSK Modulator
Carrier Suppression

Measured at TXA

55

Output Amplitude

TX scrambled marks

-11

dB
-10.0

-9

dBmO

FSK Mod/Demod
Output Freq. Error

ClK

= 11.0592 MHz

-0.35

Transmit level

Transmit Dotting Pattern

-11

Harmonic Distortion
in 700-2900 Hz band

+.35

%

-10.0

-9

dBmO

THD in the alternate band
DPSK or FSK

-60

-50

dB

Output Bias Distortion

Transmit Dotting Pattern
InAlB@ RXD

±8

Total Output Jitter

Random Input in ALB @ RXD

---

-15

%

----

+15

%

DTMF Generator
-.25

Freq. Accuracy
Output Amplitude

low-Band, DPSK Mode

-10

-9

+.25

%

-8

dBmO

Output Amplitude

High-Band, DPSK Mode

-8

-7

-6

dBmO

Twist

High-Band to low-Band,
DPSK mode

1.0

2.0

3.0

dB

Long Loop Detect

DPSK or FSK

-38

-28

dBmO

Dynamic Range

Refer to Performance Curves

dB

45

Call Progress Detector

---

-34

Detect level

2-Tones in 350-600 Hz band

Reject level

2-Tones in 350-600 Hz band

Delay Time

-70 dBmO to -30 dBmO STEP

27

Hold Time

-30 dBmO to -70 dBmO STEP

27

0

dBmO

-41

dBmO

80

ms

80

ms

2

Hysteresis
Note: Parameters expressed in dBmO refer to the following definition:

o dB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.

3-16

dB

SSI73K212L
Bell 212A/1 03
Single-Chip Modem

ELECTRICAL SPECIFICATIONS (Continued)
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS

CONDITIONS

MIN

DPSK or FSK receive data

-49

NOM

MAX

UNITS

-42

dBmO

45

ms

carrier Detect
Threshold
Delay Time

-70 dBmO to -30 dBmO STEP

15

Hysteresis

Single tone detected

2

Hold Time

-30 dBmO to -70 dBmO STEP

10

24

ms

Detect Level

In FSK mode

-49

-42

dBmO

Delay Time

-70 dBmO to -30 dBmO STEP

20

45

ms

Hold Time

-30 dBmO to -70 dBmO STEP

10

30

ms

+2.5

%

300

Q

3

dB

Answer Tone Detector

-2.5

Detect Freq. Range

---"

- ---

-..

Output Smoothing Filter
---

200

TXA pin Output Impedance

~

Output load

TXA pin; FSK Single
Tone out for THD = -50 db
in .3 to 3.4 KHz

Spurious Freq. Compo

Frequency = 76.8 KHz

kQ

10

------

Frequency = 153.6 KHz

Clock Noise

TXA pin; 76.8 KHz

------

50

pF

-39

dBmO

-45

dBmO

1.0

mVms

CarrierVCO
Capture Range

Originate or Answer

Capture Time

-10 Hz to +10 Hz Carrier
Freq. Change Assum.

-10

._._-

40
--

..

+10

Hz

100

ms

+625

ppm

50

ms

~-

Recovered Clock
Capture Range

% of frequency
center frequency
(center at 1200 Hz)

Data Delay Time

Analog data in at RXA pin to
receive data valid at RXD pin

3-17

-625

-----

30

•

SSI73K212L
Bell 212A/1 03

Single-Chip Modem
ELECTRICAL SPECIFICATION

(Continued)

DYNAMIC CHARACTERISTICS AND TIMING
PARAMETERS

(Continued)

CONDITIONS

MIN

NOM

MAX

UNITS

Timing (Refer to Timing Diagrams)
TAL

CSIAddr. setup before ALE low

30

ns

TLA

CS/Addr. hold after ALE low

20

ns

TLC

ALE low to RD/WR low

40

TCL

RD/WR Control to ALE high

10

TRD

Data out from RD low

0

TLL

ALE width

60

TRDF

Data float after RD high

0

ns

---

ns
160

--

ns
ns

-

80

ns

TRW

RDwidth

200

25000

ns

TWW

WRwidth

140

25000*
.. _-

ns

TOW

Data setup before WR high

150

ns

TWO

Data hold after WR high

20

ns

TCKD

Data out after EXCLK low

TCKW

WR after EXCLK low

150

TDCK

Data setup before EXCLK low

150

TAC

Address setup before control**

50

ns

TCA

Address hold after control**

50

ns

TWH

Data Hold after EXCLK

20

ns

*

Maximum time applies to parallel version only.

**

Control for setup is the falling edge of RD or WR.
Control for hold is the falling edge of RD or the rising edge of WR.

3-18

--

200

f---------

ns
ns
ns

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
ALE

~
~

F4c
TlC

J

TRW

--\-

RD

.L

TCl

j

+

TlC

.L

'J

TlA

L

ADO-AD7

cs

--K

-=1-

TAL..

.I

TWW

--~

WR
TRD

~

I TWD

TRDF

~

I..

ADDRESS }------K READ DATA}------K ADDRESS

-~-

-4-

~ .. • ~I

TOW

~~

-4-

READ TIMING DIAGRAM (SERIAL VERSION)
EXClK

RD

AO-A2

DATA - - - f -

WRITE TIMING DIAGRAM (SERIAL VERSION)
EXClK

HTWW

-----r-------------------------------------r-~

TCKW

AO-A2

---+----------------

DATA

3-19

I,

TAC

IL

,

ITCA

•

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
APPLICATlONS INFORMATION
GENERAL CONSIDERATIONS
Figures 1 and 2 show basic circuit di~grams for
K -Series modem integrated circuits. K-Series products
are designed to be used in conjunction with a control
processor, a UART or RS-232 serial data interface,
and a DAA phone line interface to function as a typical
intelligent modem. The K-Series ICs interface directly
with Intel 8048 and 80C51 microprocessors for control
and status monitoring purposes.Two typical DAA arrangements are shown: one for a split ±5 or±12 volt
design and one for a single 5 volt design. These
diagrams are for reference only and do not represent
production-ready modem designs.

K-Series devices are available with two control interface versions: one tor a parallel multiplexed address/
data interface, and one for a serial interface. The
parallel version is intended for use with 8039/48 or
8031/51 microcontrollers from Intel or many other
manufacturers. The serial interface 22-pin version can
•be used with other microcontroJlers or in applications
where only a limited number of port lines are available
or the application does not lend itself to a multiplexed
address/data interface. The parallel versions may also
be used in the serial mode, as explained in the data
sheet pin description.
In most applications the controJlerwiJl monitor the serial
data for commands from the DTE and the received
data for break signals from the far end modem. In this
way, commands to the modem are sent overthe same
line as the transmitted data. In other applications the
RS-232 interface handshake lines are used for modem
control.

Cl

RS232
LEVEL
CONVERTERS

390 pF

CA I-f>.+-=C:----!
CB I--~-'----1
ALE

CF I-<,~=---i

cs

SSI
K-SERIES
LOW
POWER
FAMILY

BA
BB
DA

00
DB

US, U6
MC145406

...r

VRl
MOV
V250L20

R9
10K

FIGURE 1: BaSic Box Modem with Dual-Supply Hybrid
3-20

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
DIRECT ACCESS ARRANGEMENT (OAA)

signals will clip if a single-ended drive approach is
used. The bridged driver uses an extra op-amp (U1 A)
to invert the signal coming from the gain setting op-amp
(U1 B) before sending it to the other leg of the transformer. Each op-amp then supplies half the drive signal
to the transformer. The receive amplifier (U1 C) picks
off its signal at the junction of the impedance matching
resistor and the transformer. Because the bottom leg of
the transformer is being driven in one direction by U1 A
and the resistor is driven in the opposite direction at the
same time by U1 B, the junction of the transformer and
resistor remains relatively constant and the receive
Signal is unaffected.

The telephone line interfaces show two examples of
how the "hybrid" may be implemented. The split supply
design (Figure 1) is a typical two op-amp hybrid. The
receive op-amp serves two purposes. It supplies gain
to amplify the receive signal to the proper level for the
modem's detectors and demodulator, and it removes
the transmitted signal from the receive signal present
at the transformer. This is done by supplying a portion
of the transmitted signal to the non-inverting input of
the receive op-amp at the same amplitude as the signal
appearing at the transformer, making the transmit
signal common mode.

DESIGN CONSIDERATIONS

The single-supply hybrid is more complex than the
dual-supply version described above, but its use eliminates the need for a second power supply. This circuit
(Figure 2) uses a bridged drive to allow undistorted
signals to be sent with a single 5V supply. Because
DTMF tones utilize a higher amplitude than data, these

Silicon Systems 1-chip modem products include all
basic modem functions. This makes these devices
adaptable for use in a variety of applications, and as
easy to control as conventional digital bus peripherals.

Cl
390pF

* Note: Op-amp U1
must be rated for
single 5V operation.
R10 & R11 values
depend on Op-amp
used.

R4
37.4K 1%

+5V

C6

O.lnF

~~~\r'AI~~~~~
VRl
MOV
V250L20

VOLTAGE
REFERENCE

HOOK
RING

>---------'

~--------------------~

FIGURE 2: Single SV Hybrid Version
3-21

I

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
MODEM PERFORMANCE
CHARACTERISTICS

Unlike digital logic circuitry, however, modem designs
must properly contend with precise frequency tolerances and very low level analog signals, to ensure
acceptable performance. Using good analog circuit
design practices will generally result in a sound design.
Following are additional recommendations which
should be taken into consideration when starting new
designs.

The curves presented here define modem IC performance under a variety of line conditions while inducing
disturbances that are typical of those encountered
during data transmission on public service telephone
lines. Test data was taken using an AEA Electronics'
"Autotest I" modem test set and line simulator, operating under computer control. All tests were run fullduplex, using a Concord Data Systems 224 as the
reference modem. A 511 pseudo-random-bit pattern
was used for each data point. Noise was C-message
weighted and all signal-to-noise (SIN) ratios reflect
total power measurements similar to the CCITT V.56
measurement specification. The individual tests are
defined as follows.

CRYSTAL OSCILLATOR
The K-Series crystal oscillator requires a parallel mode
(antiresonant) crystal which operates at 11.0592 MHz.
It is important that this frequency be maintained to
within ±0.01% accuracy.
In order for a parallel mode crystal to operate correctly
and to specification, it must have a load capacitor
connected to the junction of each of the crystal and
internal inverter connections, terminated to ground.
The values of these capacitors depend primarily on the
crystal's characteristics, and to a lesser degree on the
internal inverter circuit. The values used affect the
accuracy and start up characteristics of the oscillator.

SER vs. SIN
This test measures the ability of the modem to operate
over noisy lines with a minimum of data-transfer errors.
Since some noise is generated in the best of dial-up
lines, the modem must operate with the lowest SIN
ratio possible. Better modem performance is indicated
by test curves that are closest to the BER axis. A
narrow spread between curves representing the four
line parameters indicates minimal variation in performance while operating over a range of aberrant operating conditions. Typically, a DPSK modem will exhibit
better BER-performance test curves receiving in the
low band than in the high band.

LA YOUT CONSIDERATIONS
Good analog/digital design rules must be used to
control system noise in orderto obtain highest performance in modem designs. The more digital circuitry
present on the PC board, the more this attention to
noise control is needed. The modem should be treated
as a high impedance analog device. A 22 mF electrolytic capacitor in parallel with a 0.1 mF ceramic capacitor between VDD and GND is recommended. Liberal
use of ground planes and larger traces on power and
ground are also highly favored. High speed digital
circuits tend to generate a significant amount of EMI
(Electro-Magnetic Interference) which must be minimized in order to meet regulatory agency limitations.
To accomplish this, high speed digital devices should
be locally bypassed, and the telephone line interface
and K-Series device should be located close to each
other near the area of the board where the phone line
connection is accessed. To avoid problems, power
supply and ground traces should be routed separately
to the analog and digital functions on the board, and
digital signals should not be routed near low level or
high impedance analog traces. The analog and digital
grounds should only connect at one point near the KSeries device ground pin to avoid ground loops. The KSeries modem IC's should have both high frequency
and low frequency bypassing as close to the package
as possible.

SER vs. Receive Level
This test measures the dynamic range of the modem.
Because signal levels vary widely over dial-up lines,
the widest possible dynamic range is desirable. The
minimum Bell specification calls for 36 dB of dynamic
range. SIN ratios are held constant at the indicated
values while the receive level is lowered from a very
high to very low signal levels. The width of the "bowl" of
these curves, taken at the BER point, is the measure of
dynamic range.

3-22

SSI73K212L
Bell 212A/1 03
Single-Chip Modem

SSI73K212L
BER vs SIGNAL TO NOISE

SSI73K212L
BER vs CARRIER OFFSET
10'2

10'2

I
\ I

HIGH BAND RECEIVE
,40dBm

~

I HIGH BAND RECEIVE

L DPSK OPERATION

DPS1~~ci~~~~ION

r-

\

\'~

10-3

10'3

\

~~

\'¥

f--

C2

--

Clor3002
r-t --,----,

~ ~~ ----l~
~

10-4

10

4

1\'\

\\"

10,5

10,5

10- ~
10- ~

1\ \

\\

10,6

6

4

B

10

12

--

-t

~-

\

~r-

10'6
12

14

8

4

,4

0

CARRIER OFFSET (HZ)

*SS173K212L

*SSI 73K212L
BER vs PHASE JITTER

10'2

I HIGH
BAND RECEIVE
DPSK OPERATION
I

C2lINE

r

-12

10'2

I HIGH BAND RECEIVE

I

DPSK OPERATION

t-

10'3 •

10'3

10'4

4

=

~ 3002 11.5 dB SIN
./

~
SIN

10,8 dB

/

\

10'5

k:::: r::::

10'5

-

~
f.-

./'
~

SIN

/

\
I

C2 10.8 dB SIN

I r--

~

15 dB
10,6

10,6
10

0

,10

-20

-30

-40

0

-50

4

8

12

16

PHASE JITTER (0 PEAK)

RECEIVE LEVEL (dBm)

*

,8

SIGNAL TO NOISE (dB)

BERvs RECEWE LEVEL

10

--1\

I C211.3dBSlN

'1\ '
2

I

300211.8dBSlN

\\\

"EO On" Indicates bit CR1 04 is set for additional phase equalization.

3-23

20

24

SSI73K212L
Bell 212A/1 03
Single-Chip Modem
PACKAGE PIN DESIGNATIONS

CAUTION: Use handling procedures necessary
for a static sensitive component.

(Top View)

ClK

GND

RXA
VREF
RESET
ISET

A1

GND

XTl1

RXA

XTL2

VREF

ADO

RESET

AD1

ISET

AD2

RXClK

AD3

RXD

RXClK

AD4

TXD

RXD

AD5

cs

TXD

ADS

EXClK

EXCLK

AD?

TXClK

ALE

INT

WR

TXA

TXA

RD

VDD

400-Mil
22-Pin DIP

4

3

2

1 28 27 26
25
24

8

PLCC PINOUTS
ARE THE SAME AS
THE 28-PIN DIP

23
22
21

10

20

11

19
12 13 14 15 16 17 18

GOO-Mil
28-Pin DIP

28-Pin
PLCC

ORDERING INFORMATION
PART DESCRIPTION

ORDER NO.

PKG.MARK

28-pin
Plastic Dual-In-Line

73K212L-IP

73K212L-IP

Plastic Leaded Chip Carrier

73K212L -IH

73K212L -IH

22-pin
Plastic Dual-In-Line

73K212SL -IP

73K212SL - IP

Ceramic Dual-In-Line

73K212SL - IC

73K212SL - IC

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914

0194 - rev.

3-24

Protected by the following Patents (4,691,172) (4,777,453)
©1989 Silicon Systems, Inc.

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem

January 1994

DESCRIPTION

FEATURES

The 881 73K221 L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a CCITT V.22 and V.21 compatible modem,
capable of 1200 or 0-300 bitls full-duplex operation
over dial-up lines. The 881 73K221 L is an enhancement of the 881 73K212L single-chip modem with
performance characteristics suitable for European and
Asian telephone systems. The 881 73K221 L produces
either 550 or 1800 Hz guard tone, recognizes and
generates a2100 Hz answer tone, and allows V.21 for
300 Hz F8K operation. The 881 73K221 L integrates
analog, digital, and switched-capacitor array functions
on a single substrate, offering excellent performance
and a high level of functional integration in a single 28or 22-pin DIP configuration. The 881 73K221 L, operates from a single +5 volt supply.

One-chip CCITT V.22 and V.21 standard compatible modem data pump
Full-duplex Operation at 0-300 bitls (FSK) or 600
and 1200 bitls (DPSK)
Pin and software compatible with other
SSI K-Series 1-chip modems
Interfaces directly with standard microprocessors
(8048, 80C51 typical)
Serial (22-pin DIP) or parallel (28-pin DIP or
PLCC) microprocessor bus for control
Serial port for data transfer

The 881 73K221 L includes the DP8K and F8K modulator/demodulator functions, call progress and handshake tone monitor test modes, and a tone generator
capable of producing DTMF, answer and 550 or
1800 Hz guard tone. This device supports
V.22 (Except mode v) and V. 21 modes of operation,

Test modes available: ALB, DL, RDL, Mark,
Space, Alternating bit patterns
Precise automatic gain control allows 45 dB
dynamic range
Space efficient 22- or 28-pin DIP or 28 Pin PLCC
packages
CMOS technology for low power consumption
using 30 mW @ 5V
Single +5 volt supply

Both Synchronous and Asynchronous modes of
operation
Call progress, carrier, preCise answer tone
(2100 Hz), and long loop detectors
DTMF, and 550 or 1800 Hz guard tone generators

(Continued)

BLOCK DIAGRAM

PIN DIAGRAM
ClK

ADO·AD7

'.----,"1

XTll

RXA

XTl2

VREF

lID o--~
Wli o--~
ALE o--~

ADO

RESET

ADl

ISET

RESET O--~

AD2

RXClK

os

O--~

AD3

RXD

AD4

TXD

ADS
TXD
RXD

AD6

o-------~

EXClK

AD7

o--------L_----.J

ALE

INT

WR

TXA

RD

VDD

CAUTION: Use handling procedures necessary
for a static sensitive component.

0194 - rev.

3-25

I

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
FSK modes. If serial input data contains a break signal
through one character~(including start and stop bits) the
break will be extended to at least 2· N + 3 bits long
(where N is the number of transmitted bits/character).

DESCRIPTION (Continued)
allowing both synchronous and asynchronous communications. The SSI 73K221 L is designed to appear
to the systems designer as a microprocessor peripheral, and will easily interface with popular one-chip
microprocessors (80C51 typical) for control of modem
functions through its 8-bit multiplexed address/data
bus or alternatively via the serial control bus. An ALE
control line simplifies address demultiplexing. Data
communications occurs through a separate serial port
only.

Serial data from the demodulator is passed first
through the data descrambler and then through the
SYNC/ASYNC rate converter. The SYNC/ASYNC
convertor will reinsert any deleted stop bits and transmit output data at an intra-character rate (bit-to-bit
timing) of no greaterthan 1219 bit/so An incoming break
signal (low through two characters) will be passed
through without incorrectly inserting a stop bit.
The SYNC/ASYNC converter also has an extended
Overspeed mode which allows selection of an output
range of either +1% or +2.3%. In the extended
Overspeed mode, stop bits are output at 7/8 the normal
width.

The SSI73K221 L is ideal for use in either free standing
or integral system modem products where full-duplex
1200 bit/s data communications over the 2-wire
switched telephone network is desired. Its high functionality, low power consumption and efficient packaging simplify design requirements and increase system
reliability. A complete modem requires only the addition of the phone line interface, a control microprocessor, and RS-232 level converter for a typical system.
The SSI 73K221 L is part of Silicon Systems' K-Series
family of pin and function compatible single-chip modem products. These devices allow systems to be
configured for higher speeds and Bell or CCITT operation with only a single component change.

SYNCHRONOUS MODE

The CC ITT V .22 standard defines synchronous operation at 600 and 1200 bit/s. The Bell 212A standard
defines synchronous operation only at 1200 bitls.
Operation is similar to that of the Asynchronous mode
except that data must be synchronized to a provided
clock and no variation in data transfer rate is allowable.
Serial input data appearing at TXD must be valid on the
rising edge of TXCLK.

OPERATION

TXCLK is an internally derived signal in Internal mode
and is connected internally to the RXCLK pin in Slave
mode. Receive data at the RXD pin is clocked out on
the falling edge of RXCLK. The ASYNC/SYNC converter is bypassed when Synchronous mode is
selected and data is transmitted at the same rate as it
is input.

ASYNCHRONOUS MODE

Data transmission for the DPSK mode requires that
data ultimately be transmitted in a synchronous
fashion, The SSI 73K221 L includes ASYNC/SYNC
and SYNC/ASYNC converters which delete or insert
stop bits in order to transmit data at a regular rate. In
Asynchronous mode the serial data comes from the
TXD pin into the ASYNC/SYNC rate converter. The
ASYNC/SYNC rate converter accepts the data provided on the TXD pin which normally must be 1200 or
600 bitls + 1.0%, - 2.5%. The rate converter will then
insert or delete stop bits in order to output a signal
which is 1200 or 600 bitls ± 0.01 %.

DPSK MODULATOR/DEMODULATOR

The SSI 73K221 L modulates a serial bit stream into
dibit pairs that are represented by four possible phase
shifts as prescribed by the V.22 standard. The
baseband signal is then filtered to reduce intersymbol
interference on the bandlimited 2-wire telephone line.
Transmission occurs on either a 1200 Hz (Originate
mode) or 2400 Hz carrier (Answer mode). Demodulation is the reverse of the modulation process, with the
incoming analog signal eventually decoded into di-bits
and converted back to a serial bit stream. The demodulator also recovers the clock which was encoded into
the analog signal during modulation. Demodulation

The serial data stream from the ASYNC/SYNC converter is passed through the data scrambler and onto
the analog modulator. The data scrambler can be
bypassed under processor control when unscrambled
data must be transmitted. The ASYNC/SYNC rate
converter and the data scrambler are bypassed in all

3-26

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
occurs using either a 1200 Hz carrier (Answer mode or
ALB Originate mode) or a 2400 Hz carrier (Originate
mode or ALB Answer mode). The SSI 73K221 L uses
a phase locked loop coherent demodulation technique
for optimum performance.
FSK MODULATOR/DEMODULATOR

The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. V.21 mode uses 980 and
1180 Hz (originate, mark and space) or 1650 and
1850 Hz (answer, mark and space). Demodulation
involves detecting the received frequencies and
decoding them into the appropriate binary value. The
rate converter and scrambler/descrambler are bypassed in the V.21 mode.

SERIAL COMMAND INTERFACE

The serial Command mode allows access to. the
SSI 73K221 L control and status registers via a serial
command port (22-pin version only). In this mode the
AO , A 1 and A2lines provide register addresses for data
passed through the data pin under control of the RD
and WR lines. A read operation is initiated when the RD
line is taken low. The first bit is available after RD is
brought low and the next seven cycles of EXCLK will
then transfer out the remaining seven bits of the selected address LSB first. A write takes place by shifting
in eight bits of data LSB first for eight consecutive
cycles of EXCLK. WR is then pulsed low and data
transferred into the addressed register on the rising
edge of WR.

PASSBAND FILTERS AND EQUALIZERS

SPECIAL DETECT CIRCUITRY

High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay equalization and rejection of out-of-band signals in the receive channel. Amplitude and phase equalization are
necessary to compensate for distortion of the transmission line and to reduce intersymbol interference in the
band limited receive signal. The transmit signal filtering
approximates a 75% square root of raised Cosine
frequency response characteristic.

The special detect circuitry monitors the received
analog signal to determine status or presence of carrier, call-progress tones, answer tone and weak
received signal (long loop condition). An unscrambled
mark signal is a Iso detected w he n the received data out
of the DPSK demodulator before the descrambler has
been mark for 165.5 ms ± 6.5 ms minimum. The
appropriate detect register bit is set when one of these
conditions changes and an interrupt is generated for all
conditions except long loop. The interrupts are disabled (masked) when the enable interrupt bit is setto O.

AGC
DTMF GENERATOR

The automatic gain control maintains a signal level at
the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping and provides a total
dynamic range of >45 dB.

The DTMF generator will output one of 16 standard
tone pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mode
is selected using the tone register and the transmit
enable (CRO bit D1) is changed from 0 to 1.

PARALLEL BUS INTERFACE

Four 8-bit registers are provided for control, optionselect and status monitoring. These registers are
addressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as four consecutive memory locations. Two control registers and the tone register are
read/write memory. The detect register is read only and
cannot be modified except by modem response to
monitored parameters.

3-27

•

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
PIN DESCRIPTION
POWER
28·PIN

22·PIN

TYPE

DESCRIPTION

GND

28

1

I

System Ground.

VDD

15

11

I

Power supply input, 5V ±1 0%. Bypass with 0.1 and 22 gF
capacitors to ground.

VREF

26

21

0

An internally generated reference voltage. Bypass with
0.1 J.lF capacitor to GND.

ISET

24

19

I

Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 MQ resistor. ISET should be bypassed to GND with a
0.1 J.lF capacitor.

NAME

PARALLEL MICROPROCESSOR INTERFACE
12

-

I

Address latch enable. The falling edge of ALE latches the
address on ADO-AD2 and the chip select on CS.

4-11

-

I/O

Address/data bus. These bidirectional tri-state multiplexed lines carry information to and from the internal
control registers.

CS

20

-

I

Chip select. A low on this pin during the falling edge of ALE
allows a read cycle or a write cycle to occur. ADO-AD7 will
not be driven and no registers will be written if CS (latched)
is not active. The state CS is a latched on the falling edge
of ALE.

ClK

1

2

0

Output clock. This pin is selectable under processor control
to be either the crystal frequency (for use as a processor
clock) or 16 x the data rate for use as a baud rate clock in
DPSK modes only. The pin defaults to the crystal frequency
on reset.

INT

17

13

0

Interrupt. This open drain output signal is used to inform the
processor that a detect flag has occurred. The processor
must then read the detect register to determine which
detect triggered the interrupt. INT will stay low until the
processor reads the detect register or does a full reset.

RD

14

-

I

Read. A low requests a read of the SSI 73K221 l internal
registers. Data cannot be output unless both RD and the
latched CS are active or low.

RESET

25

20

I

Reset. An active high Signal on this pin will put the chip into
an inactive state. All control register bits (CRO, CR1, Tone)
will be reset. The output of the ClK pin will be set to the
crystal frequency. An internal pull down permits power on
reset using a capacitor to VDD.

ALE
ADO-AD7

3-28

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
PIN DESCRIPTION

(Continued)

PARALLEL MICROPROCESSOR INTERFACE
NAME
WR

28·PIN

22·PIN

TYPE

13

-

I

(Continued)

DESCRIPTION
Write. A low on this pin informs the SSI 73K221 L that data
is available on ADO-AD7 for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are low.

SERIAL MICROPROCESSOR INTERFACE
AO-A2

-

5-7

I

Register Address Selection. These lines carry register
addresses and should be valid during any read or write
operation.

DATA

-

8

I/O

Serial Control Data. Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs data.

RD

-

10

I

Read. A low on this input informs the SSI73K221 L that data
or status information is being read by the processor. The
falling edge of the RD signal will initiate a read from the
addressed register. The RD signal must continue for eight
falling edges of EXCLK in order to read all eight bits of the
referenced register. Read data is provided LSB first. Data
will not be output unless the RD signal is active.

WR

-

9

I

Write. A low on this input informs the SSI 73K221 L that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on
the DATA pin for eight consecutive falling edges of EXCLK
and then to pulse WR low. Data is written on the rising edge
ofWR.

Note:

In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the
pins; AD, A 1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.
The Serial Control mode is provided in the parallel control versions by tying ALE high and CS low.
In this configuration AD7 becomes DATA and ADO, AD1 and AD2 become AD, A1 and A2,
respectively.

3-29

I

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
PIN DESCRIPTION (Continued)
DTE USER INTERFACE
DESCRIPTION

NAME

28·PIN

22·PIN

TYPE

EXCLK

19

15

I

External Clock. This signal is used in synchronous transmission when the external timing option has been selected.
In the External Timing mode the rising edge of EXCLK is
used to strobe synchronous DPSK transmit data applied to
the TXD pin. Alternately used for serial control interface.

RXCLK

23

18

0

Receive Clock. The falling edge of this clock output is
coincident with the transitions in the serial received data
output. The rising edge of RXCLK can be used to latch the
valid output data at RXD. RXCLK will be valid as long as a
carrier is present in DPSK synchronous modes.

RXD

22

17

0

Received Digital Data Output. Serial receive data is available on this pin. The data is always valid on the rising edge
of RXCLK when in Synchronous mode. RXD will output
constant marks if no carrier is detected.

TXCLK

18

14

0

Transmit Clock. This signal is used in DPSK synchronous
transmission to latch serial input data on the TXD pin. Data
must be provided sothat valid data is available onthe rising
edge of the TXCLK. The transmit clock is derived from
different sources depending upon the Synchronization
mode selection. In Internal Mode the clock is generated
internally. In External Mode TXCLK is phase locked to the
EXCLK pin. In Slave Mode TXCLK is phase locked to the
RXCLK pin. TXCLK is always active.

TXD

21

16

I

Transmit Data Input. Serial data for transmission is applied
to this pin. In Synchronous modes, the data must be valid
on the rising edge of the TXCLK. In Asynchronous modes
(1200/600 bitls or 300 baud) no clocking is necessary.
DPSK data must be 1200/600 bit/s +1%, -2.5% or +2.3%,
-2.5 % in extended Overspeed mode.

--

ANALOG INTERFACE AND OSCILLATOR
Received modulated analog signal input from the telephone line interface.

RXA

27

22

I

TXA

16

12

0

Transmit analog output to the telephone line interface.

XTL1
XTL2

2
3

3
4

I
I

These pins are for the internal crystal oscillator requiring
an 11.0592 MHz Parallel mode crystal. Load capacitors
should be connected from XTL 1 and XTL2 to Ground. XTL2
can also be driven from an external clock.

3-30

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
REGISTER DESCRIPTIONS

controls the interface between the microprocessor and
the 551 73K221 L internal state. DR is a detect register
which provides an indication of monitored modem
status conditions. TR, the tone control register, controls the DTMF generator, answer and guard tones and
RXD output driver used in the modem initial connect
sequence. All registers are read/write except for DR
which is read only. Register control and status bits are
identified below:

Four 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AO and A 1
address lines in Serial mode, orthe ADO and AD1lines
in Parallel mode. In Parallel mode ADO and AD1 lines
are latched by ALE. Register CRO controls the method
by which data is transferred over the phone line. CR1

REGISTER BIT SUMMARY

CRO

CONTROL
REGISTER
1
DETECT
REGISTER

TONE
CONTROL
REGISTER
CONTROL
REGISTER

CR1

001

ENABLE
DETECT
INTERRUPT

DR

010

RECEIVE
DATA

m

011

CR2

100

CR3

101

10

110

2
CONTROL
REGISTER
3

10
REGISTER

NOTE:

When a register containing reserved
control bits is written into, the reserved bits
must be programmed as O's.

3-31

BYPASS
SCRAMBLER

CLK
CONTROL

RESET

TEST
MODE
1

TEST
MODE
0

UNSCR.
MARKS

CARRIER
DETECT

ANSWER
TONE

CALL
PROGRESS

LONG
LOOP

TRANSMIT
DTMF

DTMF3

DTMF2

DTMF11
OVERSPEED

DTMFOI
GUARDI

I

SSI73K221L
CCllT V.22, V.21
Single-Chip Modem
REGISTER ADDRESS TABLE

0=1200 BrTlS DPSK
1=600 BIT/S DPSK

O=DISABLE
TXA OUTPUT
1=ENABLE
TXAOUTPUT

OOOO=PWR DOWN
0001=INT SYNCH
0010=EXT SYNCH
0011 .SLAVE SYNCH
0100=ASYNCH 8 BITs/CHAR
0101 =ASYNCH 9 BITSICHAR
0110=ASYNCH 10 BITS/CHAR
0111 =ASYNCH 11 BITS/CHAR
1100=FSK

O=DISABLE
1=ENABLE

O-NORMAL
O=XTAL
1=16 X DATA
1=BYPASS
SCRAMBLER RATE OUTPUT
ATCLK PIN IN
DPSKMODE
ONLY

O=ANSWER
1=ORIGINATE

O=NORMAL
1=RESET

0=1800 Hz G.T.
1=550 Hz G.T.

00XX=73K212L. 322L. 321 L
01 XX=73K221 L. 302L
10XX=73K222L
1100=73K224L
1110-73K324L
1101 =73K312L

3-32

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem

II

CONTROL REGISTER 0

CRO
000

D7
MOOUL.
OPTION

BIT NO.
DO

01

04
02
01
03
D5
TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT
ENABLE
MODE 3
MODE 2
MODE 1
MOOEO

DO
ANSWER/
ORIGINATE

NAME

CONDITION

Answer/
Originate

0

Selects Answer mode (transmit in high band, receive
in low band).

1

Selects Originate mode (transmit in low band, receive
in high band).

DESCRIPTION

transmit output at TXA

Transmit

0

'")I!:::

Enable

1

Enables transmit output at TXA.
Note: TX Enable must be set to 1 to allow AnswerTone
and OTMF transmission.

"l1P.!::

05 04 03 02
05,04,03,
02

Transmit
Mode

0

0

0

0

Selects Power Down mode. All functions disabled
except digital interface.

0

0

0

1

Internal Synchronous mode. In this mode TXCLK is an
internally derived 1200 Hz signal. Serial input data
appearing at TXO must be valid on the rising edge of
TXCLK. Receive data is clocked out of RXO on the
falling edge of RXCLK.

0

0

1

0

External Synchronous mode. Operation is identicalto
internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 1200 Hz ± 0.01 % clock must
be supplied externally.

0

0

1

1

Slave Synchronous mode. Same operation as other
Synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.

0

1

0

0

Selects OPSK Asynchronous mode - 8 bits/character
(1 start bit, 6 data bits, 1 stop bit).

0

1

0

1

Selects OPSK Asynchronous mode - 9 bits/character
(1 start bit, 7 data bits, 1 stop bit).

0

1

1

0

Selects DPSK Asynchronous
(1 start bit, 8 data bits, 1 stop bit)

0

1

1

1

Selects DPSK Asynchronous mode - 11 bits/character
(1 start bit, 8 data bits, Parity and 1 stop bit).
UI-'t;IQUUII

0

3-33

- 10 bits/character

I

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
CONTROL REGISTER 0

(Continued)

D7
CRO
000

D5

BIT NO.

D4

D3

D2

D1

DO

TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT
MODE 3
MODE 2
MODE 1
MODE 0
ENABLE

MODUL.
OPTION
NAME

CONDITION

ANSWER/
ORIGINATE

DESCRIPTION

Selects:
D7

DPSK mode at 1200 bit/so

Modulation

o

Option

X

DPSK mode at 600 bit/so
X = Don't care

CONTROL REGISTER 1

CR1
001
BIT NO.

D7

D6

D5

D4

D3

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

ENABLE
DETECT
INTER.

BYPASS
SCRAMB

ClK
CONTROL

NAME

CONDITION

02

01

DO

RESET

TEST
MODE
1

TEST
MODE
0

DESCRIPTION

D1 DO
01, DO

D2

03

Test Mode

Reset

ClK Control
(Clock Control)

0

0

Selects normal Operating mode.

0

1

Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable must be forced
low.

1

0

Selects remote digital loopback. Received data is
looped back to transmit data internally, and RXD is
forced to a mark. Data on TXD is ignored.

1

1

Selects local digital loopback. Internally loops TXD
back to RXD and continues to transmit carrier from
TXA pin.

0

Selects normal operation.

1

Resets modem to power down state. All control
register bits (CRO, CR1, Tone) are reset to zero. The
output of the ClK pin will be set to the crystal
frequency.

0

Selects 11.0592 MHz crystal echo output at ClK
pin.

1

Selects 16 Xthe data rate, output at ClK pin in DPSK
modes only.

3-34

SSI73K221L
CCITTV.22, V.21
Single-Chip Modem
CONTROL REGISTER 1

CR1
001
BIT NO.
04

05

(Continued)

07

06

05

04

03

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

ENABLE
DETECT
INTER.

BYPASS
SCRAMB

CLK
CONTROL

02

01

DO

RESET

TEST
MODE
1

TEST
MODE
0

NAME

CONDITION

Bypass
Scrambler

0

Selects normal operation. DPSK data is passed
through scrambler.

1

Selects Scrambler Bypass. Bypass DPSK data is
routed around scrambler in the transmit path.

Enable Detect
Interrupt

DESCRIPTION

0

Disables interrupt at INT pin.

1

Enables INT output. An interrupts will be generated
with a change in status of DR bits D1-D4. The answer
tone and call progress detect interrupts are masked
when the TX enable bit is set. Carrier detect is masked
when TX DTMF is activated. All interrupts will be
disabled if the device is in Power Down mode.
---

D7 D6
D7,D6

Transmit
Pattern

0

0

Selects normal data transmission as determined
by the state of the TXD pin.

0

1

Selects an alternating mark/space transmit pattern for
modem testing.

1

0

Selects a constant mark transmit pattern.

1

1

Selects a constant space transmit pattern.

DETECT REGISTER

DR
010
BIT NO.
DO

01

NAME

D5

D4

D3

D2

D1

DO

RECEIVE
DATA

UNSCR.
MARK

CARR.
DETECT

ANSWER
TONE

CALL
PROG.

LONG
LOOP

CONDITION

DESCRIPTION

Long Loop
Call Progress I-----------+----~____=_ _ _ _ _ _ _ _ _ _ _ _ ________I
Detect

Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in
the 350 to 620 Hz call progress band.

3-35

I

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
DETECT REGISTER (Continued)

DR
010
BIT NO.

NAME

02

Answer
Tone
Detect

05

04

03

02

01

DO

RECEIVE
DATA

UNSCR.
MARK

CARR.
DETECT

ANSWER
TONE

CALL
PROG.

LONG
LOOP

CONDITION

Indicates detection of 2100 Hz answer tone. The
device must be in Originate mode for detection of
answer tone.

Carrier
Detect

03

04

Indicates carrier has been detected in the received
channel.

Unscrambled
Mark

Indicates detection of unscrambled marks in the
received data. This may be used in the V.22 connect
sequence orfor requesting a remote modem to configure itself for remote digitalloopback. A valid indication
means that unscrambled marks have been received
for> 165.5 ± 6.5 ms.
Continuously outputs the received data stream. This
data is the same as that output on the RXD pin, but it
is not disabled when RXD is tri-stated.

Receive
Data

05

DESCRIPTION

TONE REGISTER

TR
011

07

06

05

04

RXD
OUTPUT
CONTR.

TRANSMIT
GUARD
TONE

TRANSMIT
ANSWER
TONE

TRANSMIT
OTMF

BIT NO.

NAME

CONDITION
06 04 00

00

OTMF 01
Guard Tone

03
OTMF3

02

01

DO

OTMF2

DTMF 11
OVERSPEEO

DTMF 01
GUARO

DESCRIPTION
00 interacts with bits 06, 05, and 04 as shown.

X

1

X

Transmit OTMF tones.

X

0

0

Transmits 1800 Hz guard tone.

X

0

1

Transmits 550 Hz guard tone.

_.. _"-----

-~--.-.--

04 01
01

OTMF 11

01 interacts with 04 as shown.

0

0

Asynchronous OPSK 1200 or 600 bitls +1.0% - 2.5%

0

1

Asynchronous OPSK 1200 or 600 bitls +2.3% -2.5%.

3-36

551 73K221L
CCITT V.22, V.21
Single-Chip Modem
TONE REGISTER (Continued)

TR
011

07

06

05

04

03

02

01

00

RXO
OUTPUT
CONTR.

TRANSMIT
GUARD
TONE

TRANSMIT
ANSWER
TONE

TRANSMIT
DTMF

DTMF3

DTMF2

DTMF 11
OVERSPEED

DTMF 01
GUARD

BIT NO.

NAME

03,02,
01, DO

DTMF 3,
2,1,0

CONDITION

DESCRIPTION

03 02 01 DO
0
1

0 01 1

0
1

Programs 1 of 16 DTMF tone pairs that will be
transmitted when TX DTM F and TX enable bit (CRO, bit
01) is set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT
1
2

04

05

DTMF CODE
03 02 01 DO
0
1

1

TONES
LOW HIGH
697
697

1209
1336

1

697

1477

0

770

1209

0
0

0
0

3

0

0

1

4

0

1

0

5

0

1

0

1

770

1336

6

0

1

1

0

770

1477

0

7

0

1

1

1

852

1209

8

1

0

0

0

852

1336

9

1

0

0

1

852

1477

0

1

0

1

0

941

1336

*

1

0

1

1

941

1209

#

1

1

0

0

941

1477

A

1

1

0

1

697

1633

0
1

770

1633

852

1633

0

941

1633

B

1

1

1

C

1

1

1

0

0

0

0

----

Transmit
DTMF

0

Disable DTMF.

1

Activates DTMF. The selected DTMF tones are transmitted continuously when this bit is high. TX DTMF
overrides all other transmit functions. Modem must be
in DPSK mode during DTMF transmission.

Transmit
Answer
Tone

0

Disables answer tone generator.

1

Enables answer tone generator. A 2100 Hz answer
tone will be transmitted continuously when the
Transmit Enable bit is set in CRO. The device must be
in Answer mode.

3-37

I

SSI73K221L
CCITI V.22, V.21
Single-Chip Modem
TONE REGISTER (Continued)

TR
011

07

06

05

04

RXO
OUTPUT
CONTR.

TRANSMIT
GUARD
TONE

TRANSMIT
ANSWER
TONE

TRANSMIT
OTMF

BIT NO.

03
OTMF3

02

01

DO

OTMF2

OTMF 11
OVERSPEED

OTMF 01
GUARD

NAME

CONDITION

TX Guard

0

Disables guard tone generator.

(Transmit
Guard Tone)

1

Enables guard tone generator (See DO for
selection of guard tones}.

RXO Output
Control

0

Enables RXO pin. Receive data will be output on
RXO.

1

Disables RXO pin. The RXO pin becomes a high
impedance with internal weak pull-up resistor.

06

07

DESCRIPTION

10 REGISTER

10

07

06

05

04

10

10

10

10

110
BIT NO.

NAME

CONDITION

07 06 05 04
07.06.05
04

Device
Identification
Signature

DESCRIPTION

Indicates Device:

~----------1-------------------------------------~

3-38

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
UNIT

RATING

PARAMETER

14

VDD Supply Voltage

--~

V

.. ---

-65 to 150

Storage Temperature

°C

260

Soldering Temperature (10 sec.)

°C
-

--~~-~----

V

-0.3 to VDD+0.3

Applied Voltage

Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
MIN

NOM

MAX

UNITS

VDD Supply voltage

4.5

5

5.5

V

TA, Operating Free-Air
Temperature

-40

+85

°C

-0.01

+0.01

%

2.2

MQ

PARAMETER

Clock Variation

CONDITIONS

(11.0592 MHz) Crystal or
external clock

----- -

External Components (Refer to Application section for placement.)
----~-----

VREF Bypass Capacitor

(External to GND)

0.1

Bias setting resistor

(Placed between VDD
and ISET pins)

1.8

ISET Bypass Capacitor

(ISET pin to GND)

0.1

VDD Bypass Capacitor 1

(External to GND)

0.1

VDD Bypass CapaCitor 2

(External to GND)

22

XTL 1 Load CapaCitor

Depends on crystal characteristics;

XTL2 Load CapaCitor

from pin to GND

~F

-----

2
--_.. _--

~F

--".

~F
~F
---_.--_.

40
20

3-39

pF

•

SSI73K221L
CClll V.22, V.21
Single-Chip Modem
ELECTRICAL SPECIFICATIONS

(Continued)

DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VOO = recommended range unless otherwise noted.)
PARAMETER

CONDITIONS

100, Supply Current

ISET Resistor

MIN

NOM

MAX

UNITS

8

12

mA

= 2 MQ

= 11.0592 MHz

100A, Active

ClK

1001, Power-down

ClK = 11.0592 MHz

IOD2, Power-down

ClK

---

= 19.200 KHz

--

Digital Inputs

4

mA

3

mA

VOO

V

---

VIH, Input High Voltage
Reset, XTl1 , XTL2

3.0

All other inputs

2.0

VOO

V

0

0.8

V

100

f.!A

Vll, Input low Voltage
IIH, Input High Current

VI = VIH Max

Ill, Input low Current

VI = Vil Min

-200

Reset Pull-down Current

Reset = VOO

1

Input Capacitance

All Digital Input Pins

-~f--

--

1----

f.!A
---_.-

50

f.!A

10

pF

Digital Outputs
VOH, Output High Voltage

10H MIN = -0.4 mA

VOO

V

VOL, Output low Voltage

10 MAX = 1.6 mA

0.4

V

VOL, ClK Output

10=3.6mA

0.6

V

-50

f.!A

15

pF

2.4

-1

RXD Tri-State Pull-up Curro

RXO = GNO

CMAX, ClK Output

Maximum Capacitive load

3-40

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.)
PARAMETERS

MIN

CONDITIONS

NOM

MAX

UNITS

-9

dBmO

PSK Modulator
Carrier Suppression

Measured at TXA

55

Output Amplitude

TX scrambled marks

-11

l_-~:]

dB

FSK Mod/Demod
Output Freq. Error

ClK

= 11.0592 MHz

-0.35

Transmit level

Transmit Dotting Pattern

-11

Harmonic Distortion
in 700-2900 Hz band

+ 0.35

%

-10

-9

dBmO

TH D in the alternate band
DPSK or FSK

-60

-50

dB

Output Bias Distortion

Transmit Dotting Pattern
InAlB@ RXD

±8

Total Output Jitter

Random Input in ALB @ RXD

-15

%

+15

----_._-.

%

DTMF Generator (Modem must be in DPSK mode to meet specifications)
- 0.25

Freq. Accuracy

-10

------_..

+ 0.25

%

-8

dBmO

-9

Output Amplitude

low Group, DPSK Mode

Output Amplitude

High Group, DPSK Mode

-8

-7

-6

dBmO

Twist

High-Group to low-Group

1.0

2.0

3.0

dB

Long Loop Detect

DPSK or FSK

-38

-28

dBmO

Dynamic Range

Refer to Performance Curves

dB

45

Call Prog ress Detector
Detect level

2-Tones in 350-600 Hz band

Reject level

2-Tones in 350-600 Hz band

Delay Time

-70 dBmO to -30 dBmO STEP

Hold Time

-30 dBmO to -70 dBmO STEP

0

dBmO

-41

dBmO

27

80

ms

27

80

ms

-34

-~---"-

2

Hysteresis
Note:

--

Parameters expressed in dBmO refer to the following definition:
5V Version
o dB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.

3-41

dB

I

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
CONDITIONS

MIN

Threshold

DPSK or FSK receive data

-49

Delay Time

-70 dBmO to -30 dBmO STEP

15

Hysteresis

Single tone detected

2

Hold Time

-30 dBmO to -70 dBmO STEP

10

PARAMETERS

MAX

NOM

UNITS

Carrier Detect

Answer Tone Detector
Detect Level

Not in V.21 mode

Delay Time

-70 dBmO to -30 dBmO STEP

20

Hold Time

-30 dBmO to -70 dBmO STEP

10

3°f:
J:~

-49.5

-2.5

Detect Freq. Range

+2.5

dBmO
ms
dB
ms

dBmO
ms
ms

%

Output Smoothing Filter
Output load

Spurious Freq. Compo

Output Impedance

Clock Noise

TXA pin; FSK Single

kn

10

Tone out for THO = -50 db
in 0.3 to 3.4 KHz

50

pF

Frequency = 76.8 kHz

-39

dBmO

Frequency = 153.6 kHz

-45

dBmO

TXA pin

200

TXA pin; 76.8 kHz

300

n

1.0

mVms

CarrierVCO
Capture Range

Originate or Answer

Capture Time

-10 Hz to +10 Hz Carrier
Frequency Change

-10
40

Recovered Clock
-625

Capture Range
Data Delay Time

Analog data in at RXA pin to
receive data valid at RXD pin

3-42

Hz

100

ms

+625

ppm

50

ms

J
1--

30

+10

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS

CONDITIONS

MIN

NOM

MAX

UNITS

Guard Tone Generator
Tone Accuracy

550 or 1800 Hz

-20

+20

Hz

Tone Level

550 Hz

-4.0

-3.0

-2.0

dB

-7.0

-6.0

-5.0

dB

-50

dB

-60

dB

(Below DPSK Output)

1800 Hz

Harmonic Distortion

550 Hz

700 to 2900 Hz

1800 Hz

------

Timing (Refer to Timing Diagrams)
TAL

CSI Addr. se!up before ALE low

30

TLA

CS/Addr. hold after ALE low

20

TLC

ALE low to RD/WR low

40

TCL

RD/WR Control to ALE high

10

TRD

Data out from RD low

-

ALE width

60

TRDF

Data float af~er RD high

0

TRW

RDwidth

200

TWW

WRwidth

140

TOW

Data setue}~~!.ore WR high

150

--

TWO

Data hold aft~r WR high
Data out after EXCLK low

TCKW

WR after EXCLK low

150

TDCK

Data setup before EXCLK low

150

TAC

Address setup before control**

50

TCA

Address hold after control**

50

TWH

Data hold after EXCLK

150

ns

-

ns
-

160

---

80

ns

25000

ns

25000*

ns

- -----

-----

ns
ns

--

------

~

TCKD

ns

.-----

0
- - ----

TLL

ns

---

ns

20

ns
"-_

-.----_.

200

... -.

ns
ns

- --

ns
----~

*

Maximum time applies to parallel version only.

**

Control for setup is the falling edge of RD or WR.
Control for hold is the falling edge of RD or the rising edge of WR.

---------"-----

3-43

ns

------

----

ns
ns

-----~------

I

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)

~

ALE

~
TLC

AD

TRW
~r-

TCL

-'r-

r
TLC

TLA

I.
ADO-AD?

.L

J

TWW

4-

WR

---K

cs ~-

TAL

'.I

ADDRESS

TRD

~

~D
.J.

TRDF

~

TDW

~ READ DATA ~

-i-

-~-

ADDRESS

~TA)t-

-J-

READ TIMING DIAGRAM (SERIAL VERSION)

I L

EXCLK

I'-----+---------------r

RD

::.-,r------+------------------------j-------

AO-A2

DATA

--+

WRITE TIMING DIAGRAM (SERIAL VERSION)
EXCLK

-t--------\HTWW

_ _t - -_ _ _ _ _ _ _ _ _ _ _ _ _ _

TCKW

AO-A2

-----+--------------------

DATA

3-44

IL

~

/TCA

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
APPLICATIONS INFORMATION

K-Series devices are available with two control interface versions: one for a parallel multiplexed address/
data interface, and one for a serial interface. The
parallel version is intended for use with 8039/48 or
8031/51 microcontrollers from Intel or many other
manufacturers. The serial interface 22-pin version can
be used with other microcontrollers or in applications
where only a limited number of port lines are available
or the application does not lend itself to a multiplexed
address/data interface. The parallel versions may also
be used in the Serial mode, as explained in the data
sheet pin description.

GENERAL CONSIDERATIONS
Figures 1 and 2 show basic circuit diagrams for
K-Series modem integrated circuits. K-Series products
are designed to be used in conjunction with a control
processor, a UART or RS-232 serial data interface,
and a DAA phone line interface to function as a typical
intelligent modem. The K-Series ICs interface directly
with Intel 8048 and 80C51 microprocessors for control
and status monitoring purposes. Two typical DM
arrangements are shown: one for a split ±5 or ±12 volt
design and one for a single 5 volt design. These
diagrams are for reference only and do not represent
production-ready modem designs.

In most applications the controllerwill monitor the serial
data for commands from the DTE and the received
data for break signals from the far end modem. In this
way, commands to the modem are sent over the same
line as the transmitted data. In other applications the
RS-232 interface handshake lines are used for modem
control.

Cl
390pF

CA

H>-+-,",=,,~

CB '"""'-~.----;

CC ........ ~-r--=--;

CD

WR

H>-+-=~

ALE

cs

SSI
K-SERIES

LOW
POWER
FAMILY

BA

1>11--'.:.:::'--+---+-t--t----;----j

BB

01.

DO
DB

us. us

MC145406

J

22K

FIGURE 1: Basic Box Modem with Dual-Supply Hybrid
3-45

VRI
MOV
V250L20

I

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
Signals will clip if a single-ended drive approach is
used. The bridged driver uses an extra op-amp (U1 A)
to invert the signal coming from the gain setting op-amp
(U1 B) before sending it to the other leg of the transformer. Each op-C}.mp then supplies half the drive signal
to the transformer. The receive amplifier (U1 C) picks
off its signal at the junction of the impedance matching
resistor and the transformer. Because the bottom leg of
the transformer is being driven in one direction by U1 A
and the resistor is driven in the opposite direction at the
same time by U1 B, the junction of the transformer and
resistor remains relatively constant and the receive
signal is unaffected.

DIRECT ACCESS ARRANGEMENT (DAA)

The telephone line interfaces show two examples of
how the "hybrid" may be implemented. The split supply
design (Figure 1) is a typical two op-amp bybrid. The
receive op-amp serves two purposes. It supplies gain
to amplify the receive signal to the proper level for the
modem's detectors and demodulator, and it removes
the transmitted signal from the receive signal present
at the transformer. This is done by supplying a portion
of the transmitted signal to the non-inverting input of
the receive op-amp at the same amplitude as the signal
appearing at the transformer, making the transmit
signal Common mode.

DESIGN CONSIDERATIONS

The single-supply hybrid is more complex than the
dual-supply version described above, but its use eliminates the need for a second power supply. This circuit
(Figure 2) uses a bridged drive to allow undistorted
signals to be sent with a single 5 volt supply. Because
DTMF tones utilize a higher amplitude than data, these

Silicon Systems 1-chip modem products include all
basic modem functions. This makes these devices
adaptable for use in a variety of applications, and as
easy to control as conventional digital bus peripherals.

Cl
390pF

* Note: Op-amp U1
must be rated for
single 5V operation.
R10 & R11 values
depend on Op-amp
used.

R4
37.4K 1%
'C3
0.1 nF

~I------<~

Tl
MIOCOM
671·8005
r-~~--------~-

C6
O.lnF

R7
20K 1%

~~~V\M~~~~--~
VRl
MOV
V250L20

VOlTAGE
REFERENCE

HOOK

>--_ _ _ _ _ _---1

RING

~--------------------------~

FIGURE 2: Single 5V Hybrid Version
3-46

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
MODEM PERFORMANCE
CHARACTERISTICS

Unlike digital logic circuitry, however, modem designs
must properly contend with precise frequency tolerances and very low level analog signals, to ensure
acceptable performance. Using good analog circuit
design practices will generally result in a sound design.
Following are additional recommendations which
should be taken into consideration when starting new
designs.

The curves presented here define modem IC performance under a variety of line conditions while inducing
disturbances that are typical of those encountered
during data transmission on public service telephone
lines. Test data was taken using an AEA Electronics'
"Autotest I" modem test set and line simulator, operating under computer control. A" tests were run fu"duplex, using a Concord Data Systems 224 as the
reference modem. A 511 pseudo-random-bit pattern
was used for each data point. Noise was C-message
weighted and a" signal-to-noise (SIN) ratios reflect
total power measurements similar to the CCITT V.56
measurement specification. The individual tests are
defined as follows.

CRYSTAL OSCILLATOR

The K-Series crystal oscillator requires a Parallel mode
(antiresonant) crystal which operates at 11.0592 MHz.
It is important that this frequency be maintained to
within ±0.01% accuracy.
In order for a Paralle I mode crystal to operate correctly
and to specification, it must have a load capacitor
connected to the junction of each of the crystal and
internal inverter connections, terminated to ground.
The values of these capacitors depend primarily on the
crystal's characteristics, and to a lesser degree on the
internal inverter circuit. The values used affect the
accuracy and start up characteristics of the oscillator.

BER vs. SIN

This test measures the ability of the modem to operate
over noisy lines with a minimum of data-transfer errors.
Since some noise is generated in the best of dial-up
lines, the modem must operate with the lowest SIN
ratio possible. Better modem performance is indicated
by test curves that are closest to the BER axis. A
narrow spread between curves representing the four
line parameters indicates minimal variation in performance while operating over a range of aberrant operating conditions. Typically, a DPSK modem will exhibit
better BER-performance test curves receiving in the
low band than in the high band.

LA YOUT CONSIDERATIONS

Good analogldigital design rules must be used to
control system noise in orderto obtain highest performance in modem designs. The more digital circuitry
present on the PC board, the more this attention to
noise control is needed. The modem should be treated
as a high impedance analog device. A 22 mF electrolytic capacitor in parallel with a 0.1 mF ceramic capacitor between VDD and GND is recommended. Liberal
use of ground planes and larger traces on power and
ground are also highly favored. High speed digital
circuits tend to generate a significant amount of EMI
(Electro-Magnetic Interference) which must be minimized in order to meet regulatory agency limitations.
To accomplish this, high speed digital devices should
be locally bypassed, and the telephone line interface
and K-Series device should be located close to each
other near the area of the board where the phone line
connection is accessed. To avoid problems, power
supply and ground traces should be routed separately
to the analog and digital functions on the board, and
digital signals should not be routed near low level or
high impedance analog traces. The analog and digital
grounds should only connect at one point near the KSeries device grou nd pin to avoid ground loops. The KSeries modem IC's should have both high frequency
and low frequency bypassing as close to the package
as possible.

BER vs. Receive Level

This test measures the dynamic range of the modem.
Because signal levels vary widely over dial-up lines,
the widest possible dynamic range is desirable. The
minimum Bell specification calls for 36 dB of dynamic
range. SIN ratios are held constant at the indicated
values while the receive level is lowered from a very
high to very low signal levels. The width of the "bowl" of
these curves, taken at the BER point, is the measure of
dynamic range.

3-47

I

SSI73K221L
CCITT V.22, V.21
Single-Chip Modem

·SS173K221L
BER vs SIGNAL TO NOISE

·SSI 73K221 L
BER vs CARRIER OFFSET
10-2

10-2

1HIGH BAND
RECEIVE ~
-40dBm

\

1

\

\~ ~~

\

10-3

600

I~ k\- f--

'1\ 1r--

10-3
C2

~~ H....--.----,
-~

C1or3002

\,\\

~ f\ 'c2
r-\

'\ ~~

\

\1'""

K,Cl or300~

300211.8dB SIN

\\1\

I C211.3dBSlN

10-5

\

l -I--

1111\

1\ 1\
6

l -I -

'l1 '

1\ \1\
4

10-4

\\

,\
10-6

r--

I\'l\

\ ,\

10-5

~

~

\

~\ r ~ \

2

~

\

BPS

10-4

II HIGH
BAND RECEIVE
DPSK OPERATION

DPSK OPERATION

,.......L..,

\ 1\
10

8

12

t!
I-"'r-

1\
\

-

l- I-,.....

I--1--1-

10-6
12

14

8

4

-4

0

-8

SIGNAL TO NOISE (dB)

CARRIER OFFSET (HZ)

·SSI 73K221 L
BER vs RECEIVE LEVEL

·SS173K221L
BER vs PHASE JITTER

-12

10-2

10-2

1HIGH
BAND RECEIVE ~
DPSK OPERATION
I

rI HIGH
BAND RECEIVE
DPSK OPERATION

C2L1NE

10-3

10-3

10-4

10-4

:-r-- ~ 300211.5dB SIN

f\.
SlN~

\

10-5

J-

L

V

. . .l/ :c-: . /

10_8 dB

V

I--:::::: ~ ~

10-5

I--

\

!

LC210.8dB SIN Jf - - f--

SlN-15dB

I

10-6
10

0

-10

I
-20

10-6
-30

-40

0

-50

4

•

8

12

16

PHASE JITTER (0 PEAK)

RECEIVE LEVEL (dBm)

"EO On" Indicates bit CR1 04 is set for additional phase equalization.

3-48

20

24

551 73K221L
CCITT V.22, V.21
Single-Chip Modem
PACKAGE PIN DESIGNATIONS

CAUTION: Use handling procedures necessary
for a static sensitive component.

(Top View)

CLK

GND

XTL1

RXA

XTL2
GND

RXA
VREF

XTl1

RESET
ISET
RXCLK

Al

RD
VDD

VREF

ADO

RESET

AD1

ISET

AD2

RXCLK

AD3

RXD

AD4

4

3

2

1282726
25

50=

TXD

RXD

ADS

CS

TXD

ADS

EXCLK

24

PLCC PINOUTS
ARE THE SAME AS
THE 28-PIN DIP

23
22

EXCLK

AD7

TXCLK

TXCLK

ALE

INT

10

20

tNT

WR

TXA

11

19

TXA

RD

VDD

400-Mil
22-Pln DIP

600-Mil
28-Pin DIP

21

12 13 14 15 16 17 18

28-Pin
PLCC

ORDERING INFORMATION
PART DESCRIPTION

ORDER NO.

PKG.MARK

28-Pin DIP

73K221L -IP

73K221L -IP

28-Pin PLCC

73K221L -IH

73K221L-IH

SSI 73K221 L with Parallel Bus Interface

SSI 73K212L with Serial Interface
22-Pin DIP

73K221 SL - IP

73K221 SL - IP

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
ofthird parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the rightto make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify thatthe data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914

0194 - rev.
3-49

Protected by the following Patents (4,691,172) (4,777,453)
©1989 Silicon Systems, Inc.

I

Notes:

3-50

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem

January 1994

DESCRIPTION

FEATURES

The 551 73K222L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a CCITT V.22, V.21 and Bell 212A compatible modem, capable of 1200 bitls full-duplex operation over dial-up lines. The 551 73K222L is an enhancement of the 551 73K212L single-chip modem
which adds V.22 and V.21 modes to the Bell 212A and
103 operation of the 551 73K212L. In Bell212A mode,
the 551 73K222L provides the normal Bell 212A and
103 functions and employs a 2225 Hz answer tone.
The 551 73K222L in V.22 mode produces either 550 or
1800 Hz guard tone, recognizes and generates a
2100 Hz answer tone, and allows 600 bitls V.22 or
0-300 bitls V.21 operation. The 551 73K222L integrates analog, digital, and switched-capacitor array
functions on a single substrate, offering excellent performance and a high level of functional integration in a
single 28- or 22-pin DIP configuration. The
551 73K222L operates from a single +5V supply.

One-chip CCITT V.22, V.21, Bell 212A and 103
standard compatible modem data pump
Full-duplex operation at 0-300 bltls (FSK) or 600 and
1200 bltls (OPSK)
Pin and software compatible with other
SSI K-Series 1-chip modems
Interfaces directly with standard microprocessors
(8048, 80C51 typical)
Serial or parallel microprocessor bus for control
Serial port for data transfer
Both synchronous and asynchronous modes of
operation including V.22 extended overspeed
Call progress, carrier, precise answer tone (2100 or
2225 Hz), and long loop detectors
OTMF, and 550 or 1800 Hz guard tone generators
Test modes available: ALB, OL, ROL, Mark, Space,
Alternating bit patterns
Precise automatic gain control allows 45 dB
dynamic range
CMOS technology for low power consumption using 30mW@5V
Single +5 volt supply

The 551 73K222L includes the DP5K and F5K modulator/demodulator functions, call progress and handshake tone monitor and a tone generator capable of
(Continued)

BLOCK DIAGRAM

PIN DIAGRAM

ADO-AD7

RD

:~
cs

RESET

g::=:::l
RXA

RESET

INT

AD4

0-----1

AD5
TXD
RXD

o--------.-t

ADS

0---------1

AD7

ALE
WR
RD

CAUTION: Use handling procedures necessary
for a static sensitive component.

0194 - rev.

3-51

I

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
DESCRIPTION (Continued)

The serial data stream from the ASYNC/SYNC converter is passed through the data scrambler and onto
the analog modulator. The data scrambler can be
bypassed under processor control when unscrambled
data must be transmitted. The ASYNC/SYNC converter and the data scrambler are bypassed in all FSK
modes. If serial input data contains a break signal
through one character (including start and stop bits) the
break will be extended to at least 2 • N + 3 bits long
(where N is the number of transmitted bits/character).

tone required for European applications. This device
supports V.22 (except mode v) and V. 21 modes of
operation, allowing both synchronous and asynchronous communications. Test features such as analog
loop, digital loop, and remote digital loopback are
supported. Internal pattern generators are also
included for self-testing. The SSI73K222L is designed
to appearto the systems designer as a microprocessor
peripheral, and will easily interface with popular
one-chip microprocessors (80C51 typical) for control
of modem functions through its 8-bit multiplexed
addressldata bus or serial control bus. An ALE control
line simplifies address demultiplexing. Data communications occurs through a separate serial port only.

Serial data from the demodulator is passed first
through the data descrambler and then through the
SYNC/ASYNC converter. The SYNC/ASYNC convertor will reinsert any deleted stop bits and transmit
output data at an intra-character rate (bit-to-bit timing)
of no greater than 1219 bit/so An incoming break signal
(low through two characters) will be passed through
without incorrectly inserting a stop bit.

The SSI73K222L is ideal for use in either free standing
or integral system modem products where full-duplex
1200 bitls data communications over the 2-wire
switched telephone network is desired. Its high functionality, low power consumption and efficient packaging simplify design requirements and increase system
reliability. A complete modem requires only the addition of the phone line interface, a control microprocessor, and RS-232 level converter for a typical system.
The SSI 73K222L is part of Silicon Systems' K-Series
family of pin and function compatible single-chip
modem products. These devices allow systems to be
configured for higher speeds and Bell or CCITT operation with only a single component change.

The SYNC/ASYNG converter also has an extended
overspeed mode which allows selection of an
overspeed range of either +1% or +2.3%. In the extended overspeed mode, stop bits are output at 7/8 the
normal width.
SYNCHRONOUS MODE
The CCITT V.22 standard defines synchronous operation at 600 and 1200 bit/so The Bell 212A standard
defines synchronous operation only at 1200 bit/so
Operation is similar to that of the asynchronous mode
except that data must be synchronized to a provided
clock and no variation in data transfer rate is allowable.
Serial input data appearing at TXD must be valid on the
rising edge of TXCLK.

OPERATION
ASYNCHRONOUS MODE

TXCLK is an internally derived signal in internal mode
and is connected internally to the RXCLK pin in slave
mode. Receive data at the RXD pin is clocked out on
the falling edge of RXCLK. The ASYNCH/SYNCH
converter is bypassed when synchronous mode is
selected and data is transmitted out at the same rate as
it is input.

Data transmission for the DPSK mode requires that
data ultimately be transmitted in a synchronous fashion. The SSI 73K222L includes ASYNC/SYNC and
SYNC/ASYNC converters which delete or insert stop
bits in order to transmit data within a ±0.01% rate. In
asynchronous mode the serial data comes from the
TXD pin into the ASYNC/SYNC converter. The
ASYNC/SYNC converter accepts the data provided on
the TXD pin which normally must be 1200 or 600 bitls
+ 1.0%, -2.5%. The converter will then insert or delete
stop bits in orderto output a signal which is 1200 or 600
bitls ± 0.01 % (± 0.01 % is required synchronous data
rate accuracy).

DPSK MODULATOR/DEMODULATOR
The SSI 73K222L modulates a serial bit stream into
di-bit pairs that are represented by four possible phase
shifts as prescribed by the Be1l212AorV.22 standards.
The baseband signal is then filtered to reduce intersymbol interference on the band limited 2-wire

3-52

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
PARALLEL BUS INTERFACE

telephone line. Transmission occurs using either a
1200 Hz (originate mode) or 2400 Hz carrier (answer
mode). Demodulation is the reverse of the modulation
process, with the incoming analog signal even~uallr
decoded into di-bits and converted back to a senal bit
stream. The demodulator also recovers the clock
which was encoded into the analog signal during
modulation. Demodulation occurs using either a
1200 Hz carrier (answer mode or ALB originate mode)
or a 2400 Hz carrier (originate mode or ALB answer
mode). The SSI 73K222L uses a phase locked loop
coherent demodulation technique for optimum
receiver performance.

Four 8-bit registers are provided for control, option
select and status monitoring. These registers are addressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as four consecutive memory locations. Two control registers and the tone register are
read/write memory. The detect register is read only and
cannot be modified except by modem response to
monitored parameters.
SERIAL COMMAND INTERFACE
The serial command interface allows access to the
SSI 73K222L control and status registers via a serial
command port (22-pin version only). In this mode the
AO ,A 1 and A21ines provide register addresses for data
passed through the data pin under control of the RD
and WR lines. A read operation is initiated when the RD
line is taken low. The first bit is available after RD is
brought low and the next seven cycles of EXCLK will
then transfer out seven bits of the selected address
LSB first. A write takes place by shifting in eight bits of
data LSB first for eight consecutive cycles of EXCLK.
WR is then pulsed low and data transferred into the
addressed register occurs on the rising edge of WR.
This interface mode is also supported in the 28-pin
packages. See serial control interface pin description.

FSK MODULATOR/DEMODULATOR
The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. In Bell 103, the standard
frequencies of 1270 and 1070 Hz (originate, mark and
space) or 2225 and 2025 Hz (answer, mark and space)
are used. V.21 mode uses 980 and 1180 Hz (originate,
mark and space), or 1650 and 1850Hz (answer, mark
and space). Demodulation involves detecting the received frequencies and decoding them into the
appropriate binary value. The rate converter and
scrambler/descrambler are bypassed in the 103 or
V.21 modes .
. PASSBAND FILTERS AND EQUALIZERS

SPECIAL DETECT CIRCUITRY

High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay equalization and rejection of out-of-band signals in the
receive channel. Amplitude and phase equalization
are necessary to compensate for distortion of the
transmission line and to reduce intersymbol interference in the bandlimited receive signal. The transmit
signal filtering approximates a 75% square root of
raised Cosine frequency response characteristic.

The speCial detect circuitry monitors the received a~a­
log signal to determine status or presence of car.ner,
call-progress tones, answer tone and weak received
signal (long loop condition). An unscrambled mark
request signal is also detected when the received data
out of the DPSK demodulator before the descrambler
has been high for 165.5 ms ± 6.5 ms minimum. The
appropriate detect register bit is set when one of these
conditions changes and an interrupt is generated for all
purposes except long loop. The interrupts are disabled
(masked) when the enable interrupt bit is set to O.

AGC

DTMF GENERATOR

The automatic gain control maintains a signal level at
the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping and provides a total
receiver dynamic range of >45 dB.

The DTMF generator will output one of 16 standard
tone pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mod~
is selected using the tone register and the transmit
enable (CRO bit D1) is changed from 0 to 1.

3-53

I

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
PIN DESCRIPTION
POWER
NAME

28-PIN

22-PIN

TYPE

DESCRIPTION

GND

28

1

I

System Ground.

VDD

15

11

I

Power supply input, 5V ±10% (73K222l). Bypass with .1
and 22 JlF capacitors to GND.

VREF

26

21

0

An internally generated reference voltage. Bypass with
.1 JlF capacitor to ground.

ISET

24

19

I

Chip current reference. Sets bias currentforop-amps. The
chip current is set by connecting this pin to VDD through a
2 MQ resistor. ISET should be bypassed to GND with a
.1 JlF capacitor.

PARALLEL MICROPROCESSOR INTERFACE
12

-

I

Address latch enable. The falling edge of ALE latches the
address on ADO-AD2 and the chip select on CS.

4-11

-

I/O

Address/data bus. These bidirectional tri-state multiplexed lines carry information to and from the internal
registers.

CS

20

-

I

Chip select. A low on this pin during the falling edge of ALE
allows a read cycle or a write cycle to occur. ADO-AD7 will
not be driven and no registers will be written if CS (latched)
is not active. The state of CS is latched on the falling edge
of ALE.

ClK

1

2

0

Output clock. This pin is selectable under processor control
to be either the crystal frequency (for use as a processor
clock) or 16 x the data rate for use as a baud rate clock in
DPSK modes only. The pin defaults tothe crystal frequency
on reset.

INT

17

13

0

Interrupt. This open drain output signal is used to inform the
processor that a detect flag has occurred. The processor
must then read the detect register to determine which
detect triggered the interrupt. INT will stay low until the
~rocessor reads the detect register or ~oes a full reset.

RD

14

-

I

Read. A low requests a read of the SSI 73K222l internal
registers. Data cannot be output unless both RD and the
latched CS are active or low.

RESET

25

20

I

Reset. An active high signal on this pin will put the chip into
an inactive state. All control register bits (CRO, CR1, Tone)
will be reset. The output of the ClK pin will be set to the
crystal frequency. An internal pull down resistor permits
power on reset using a capacitor to VDD.

ALE
ADO-AD7

3-54

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
PIN DESCRIPTION (Continued)
PARALLEL MICROPROCESSOR INTERFACE (Continued)
NAME

WR

28-PIN

22-PIN

-

13

TYPE

I

DESCRIPTION

Write. A low on this informs the SSI 73K222L that data is
available on ADO-AD? for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are low.

SERIAL MICROPROCESSOR INTERFACE

AO-A2

-

5-7

I

Register Address Selection. These lines carry register
addresses and should be valid during any read or write
operation.

DATA

-

8

I/O

Serial Control Data. Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs data.

RD

-

10

I

Read. A low on this input informs the SSI ?3K222L that
data or status information is being read by the processor.
The falling edge of the RD signal will initiate a read from the
addressed register. The RD signal must continue for eight
falling edges of EXCLK in order to read all eight bits of the
referenced register. Read data is provided LSB first. Data
will not be output unless the RD signal is active.

WR

-

9

I

Write. A low on this input informs the SSI?3K222L that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on
the DATA pin for eight consecutive falling edges of EXCLK
and then to pulse WR low. Data is written on the rising edge
of WR.

Note:

In the serial, 22-pin version, the pins ADO-AD?, ALE and CS are removed and replaced with the
pins; AO, A 1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.
The serial control mode is provided in the parallel control versions by tying ALE high and CS low.
In this configuration AD? becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2,
respectively.

3-55

I

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
PIN DESCRIPTION (Continued)
DTE USER
NAME

28·PIN

22·PIN

TYPE

EXCLK

19

15

I

External Clock. This signal is used in synchronous transmission when the external timing option has been selected.
In the external timing mode the rising edge of EXCLK is
used to strobe synchronous DPSK transmit data applied to
on the TXD pin. Also used for serial control interface.

RXCLK

23

18

0

Receive Clock. The falling edge of this clock output is
coincident with the transitions in the serial received data
output. The rising edge of RXCLK can be used to latch the
valid output data. RXCLK will be valid as long as a carrier
is present.

RXD

22

17

0

Received Data Output. Serial receive data is available on
this pin. The data is always valid on the rising edge of
RXCLK when in synchronous mode. RXD will output constant marks if no carrier is detected.

TXCLK

18

14

0

Transmit Clock. This signal is used in synchronous transmission to latch serial input data on the TXD pin. Data must
be provided so that valid data is available on the rising edge
of the TXCLK. The transmit clock is derived from different
sources depending upon the synchronization mode selection. In Internal Mode the clock is generated internally. In
External Mode TXCLK is phase locked to the EXCLK pin.
In Slave Mode TXCLK is phase locked to the RXCLK pin.
TXCLK is always active.

TXD

21

16

I

Transmit Data Input. Serial data fortransmission is applied
on this pin. In synchronous modes, the data must be valid
on the rising edge of the TXCLK clock. In asynchronous
modes (1200/600 bitls or 300 baud) no clocking is necessary. DPSK data must be 1200/600 bitls +1%, -2.5% or
+2.3%, -2.5 % in extended overspeed mode.

DESCRIPTION

ANALOG INTERFACE AND OSCILLATOR

RXA

27

22

I

Received modulated analog signal input from the telephone line interface.

TXA

16

12

0

Transmit analog output to the telephone line interface.

XTL1
XTL2

2
3

3
4

I
I

These pins are for the internal crystal oscillator requiring
a 11.0592 MHz parallel mode crystal. Load capacitors
should be connected from XTL 1 and XTL2 to Ground.
XTL2 can also be driven from an external clock.

3-56

SSI73K222L
V.22, V.21, Bell 212A
Single-Chip Modem
REGISTER DESCRIPTIONS

line. CR1 controls the interface between the microprocessor and the SSI 73K222L internal state. DR is a
detect register which provides an indication of monitored modem status conditions. TR, the tone control
register, controls the DTMF generator, answer and
guard tones and RXD output gate used in the modem
initial connect sequence. All registers are read/write
except for DR which is read only. Register control and
status bits are identified below:

Four 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AO, A 1 and
A2 address lines in serial mode, or the ADO, AD1 and
AD2 lines in parallel mode. In parallel mode the address lines are latched by ALE. Register CRO controls
the method by which data is transferred over the phone
REGISTER BIT SUMMARY

CRO

000

CRl

001

ENABLE
DETECT
INTERRUPT

BYPASS
SCRAMBLER

CLK
CONTROL

RESET

TEST
MODE

TEST
MODE
0

DR

010

RECEIVE
DATA

UNSCR.
MARKS

CARRIER
DETECT

ANSWER
TONE

CALL
PROGRESS

LONG
LOOP

TONE
CONTROL
REGISTER

m

011

TRANSMIT
DTMF

DTMF3

DTMF2

CONTROL
REGISTER
2

CR2

100

CONTROL
REGISTER

CR3

101

ID

110

CONTROL
REGISTER
1
DETECT
REGISTER

3
ID
REGISTER

NOTE:

When a register containing reserved control
bits is written into, the reserved bits must be
programmed as O's.

3-57

DTMF1!
OVERSPEED

I

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
REGISTER ADDRESS TABLE

0.1200 Bms DPSK
1-600 BITIS DPSK
O=BEll 103 FSK
1=V.21 FSK

OOOO=PWR DOWN
0001-INT SYNCH
0010=EXT SYNCH
0011.SlAVE SYNCH
0100-ASYNCH 8 BITSICHAR
01 01.ASYNCH 9 BITSICHAR
0110_ASYNCH 10 BITSICHAR
0111_ASYNCH 11 BITSICHAR
1100.FSK

O=DISABlE
TXAOUTPUT
1=ENABlE
TXAOUTPUT

O=ANSWER
1=ORIGINATE

O=XTAl
1-16XDATA
RATE OUTPJJT
ATClK PIN IN
DPSKMODE
ONLY

0=2225 Hz A.T.
1800 Hz G.T.
1=2100 Hz A.T.
500 Hz G.T.

OOXX-73K212l. 322l. 321l
01 XX-73K221l. 302l
10XX-73K222l
1100=73K224l
1110_73K324l
11 01 =73K312l

3-58

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
CONTROL REGISTER 0

CRO
000

M:~" II rII TRA~~MIT

UI"' I

BIT NO.
DO

01

:i:~,

':i:; : :i:

MODE 3

04

02

03

01

DO

TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/
MODE 2
MODE 1
MODE 0
ENABLE ORIGINATE

NAME

\,;UNUIIIUN

Answer/
Originate

0

Selects answer mode (transmit in high band, receive
in low band).

1

Selects originate mode (transmit in low band, receive
in high band).

0

ni~;:!hlp.~

1

Enables transmit output at TXA.
Note: TX Enable must be set to 1 to allow Answer Tone
and OTMF Transmiission.

Transmit
Enable

Ut:.~I~HI'"

IIUN

transmit output

05 04 03 02
05,04,03,
02

06

Transmit
Mode

0

0

0

0

Selects power down mode. All functions disabled
except digital interface.

0

0

0

1

Internal synchronous mode. In this mode TXCLK is an
internally derived 1200 Hz signal. Serial input data
appearing at TXO must be valid on the rising edge of
TXCLK. Receive data is clocked out of RXO on the
falling edge of RXCLK.

0

a

1

a

External synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 1200 Hz ± 0.01 % clock must
be supplied externally.

a a

1

1

Slave synchronous mode. Same operation as other
synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.

0

1

a a

Selects PSK asynchronous mode - 8 bits/character
(1 start bit, 6 data bits, 1 stop bit).

a

1

0

1

Selects PSK asynchronous mode - 9 bits/character
(1 start bit, 7 data bits, 1 stop bit).

a

1

1

a

Selects PSK asynchronous mode - 10 bits/character
(1 start bit, 8 data bits, 1 stop bit).

a

1

1

1

Selects PSK asynchronous mode - 11 bits/character
(1 start bit, 8 data bits, Parity and 1 or 2 stop bits).

1

1

a a
0

Selects FSK

II

Not used; must be written as a "0."

3-59

I

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
CONTROL REGISTER 0

(Continued)

D7
CRO
000

D5

MODUL.
OPTION

BIT NO.

D7

D3

D4

02

01

DO

TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/
MODE 2
MODE 1
MODE 0
ENABLE ORIGINATE
MODE 3
NAME

CONDITION

DESCRIPTION

Modulation
Option

x = Don't care
CONTROL REGISTER 1

CR1
001

07

06

D5

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

ENABLE
DETECT
INTER.

BIT NO.

NAME

01, DO

Test Mode

CONDITION

D4

03

BYPASS
ClK
SCRAMB CONTROL

02

01

DO

RESET

TEST
MODE
1

TEST
MODE
0

DESCRIPTION

D1 DO

D2

03

Reset

ClK Control
(Clock Control)

0

0

Selects normal operating mode.

0

1

Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable must be forced
low.

1

0

Selects remote digital loopback. Received data is
looped back to transmit data internally, and RXD is
forced to a mark. Data on TXD is ignored.

1

1

Selects local digital loopback. Internally loops TXD
back to RXD and continues to transmit carrier from
TXApin.

0

Selects normal operation.

1

Resets modem to power down state. All control
register bits (CRO, CR1, Tone) are reset to zero. The
output of the ClK pin will be set to the crystal
frequency.

0

Selects 11.0592 MHz crystal echo output at ClK
pin.

1

Selects 16 X the data rate, output arClK pin in DPSK
modes only.
3-60

SSI73K222L
V.22, V.21, Bell 212A
Single-Chip Modem
CONTROL REGISTER 1

CR1
001
BIT NO.
D4

D5

(Continued)

D7

D6

D5

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

ENABLE
DETECT
INTER.

D4

D3

BYPASS
ClK
SCRAMB CONTROL

D2

D1

DO

RESET

TEST
MODE
1

TEST
MODE
0

NAME

CONDITION

Bypass
Scrambler

0

Selects normal operation. DPSK data is passed
through scrambler.

1

Selects Scrambler Bypass. Bypass DPSK data is
routed around scrambler in the transmit path.

Enable Detect

DESCRIPTION

0

Disables interrupt at INT pin.

1

Enables INT output. An interrupts will be generated
with a change in status of DR bits D1-D4. The answer
tone and call progress detect interrupts are masked
when the TX enable bit is set. Carrier detect is masked
when TX DTMF is activated. All interrupts will be
disabled if the device is in power down mode.

D7 D6
D7,D6

Transmit
Pattern

0

0

Selects normal data transmission as controlled by the
state of the TXD pin.

0

1

Selects an alternating mark/space transmit pattern for
modem testing.

1

0

Selects a constant mark transmit pattern.

1

1

Selects a constant space transmit pattern.

DETECT REGISTER

BIT NO.

NAME

DO

long loop

D1

Call
Progress
Detect

D5

D4

D3

D2

D1

DO

RECEIVE
DATA

UNSCR.
MARK

CARR.
DETECT

ANSWER
TONE

CAll
PROG.

lONG
lOOP

CONDITION

DESCRIPTION

Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in
the 350 to 620 Hz call progress band.

3-61

I

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem

DETECT REGISTER

(Continued)

BIT NO.

NAME

02

Answer
Tone
Detect

05

04

03

02

01

DO

RECEIVE
DATA

UNSCR.
MARK

CARR.
DETECT

ANSWER
TONE

CALL
PROG.

LONG
LOOP

CONDITION

Indicates detection of 2225 Hz answer tone in Bell
mode or 21 00 Hz in CCITT mode. The device must be
in originate mode for detection of answer tone. For
CCITT answer tone detection, bit DO of the Tone
R
r must be set to a 1.

Carrier
Detect

03

Indicates carrier has been detected in the receive
channel.

Unscrambled
Mark
Detect

04

Indicates detection of unscrambled marks in
the received data. A· valid indication requires that
unscrambled marks be received for> 165.5 ± 6.5 ms.

Receive
Data

05

DESCRIPTION

Continuously outputs the received data stream. This
data is the same as that output on the RXO pin, but it
is not disabled when RXO is tri-stated.

TONE REGISTER

TR
011

07

06

RXO
OUTPUT
CONTR.

TRANSMIT
GUARD
TONE

BIT NO.
DO

NAME
OTMF 01
Answerl

Guard Tone

05

TRANSMIT TRANSMIT
OTMF
ANSWER
TONE
CONDITION

OTMF 11
Overspeed

03

02

01

DO

OTMF3

OTMF2

OTMF 11
OVERSPEED

OTMF 01
ANSWERI
GUARD

DESCRIPTION

06 05 04 DO

DO interacts with bits 06, OS, and 04 as shown.

X

X

1

X

Transmit OTMF tones.

X

0

0

0

Detects 2225 Hz in originate mode.

X

1

0

0

Transmits 2225 Hz in answer mode (8ell).

X

0

0

X

0

1
1

Transmits 2100 Hz in answer mode (CCITT).

1

1
0

0

0

Select 1800 Hz guard tone.

1

0

0

1

Select 550 Hz guard tone.

04 01
01

04

Detects 2100 Hz in originate mode.

01 interacts with 04 as shown.

0

0

Asynchronous OPSK +1.0% -2.5%.

0

1

Asynchronous OPSK +2.3% -2.5%.
3-62

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
TONE REGISTER

TR
011

07

06

RXO
OUTPUT
CONTR.

TRANSMIT
GUARD
TONE

BIT NO.

NAME

05

04

CONDITION

D2

D1

DO

DTMF2

DTMF 11
OVERSPEED

DTMF 01
ANSWERI
GUARD

D3

TRANSMIT TRANSMIT
DTMF
ANSWER
TONE

DTMF3

DESCRIPTION

D3 D2 D1 DO
D3, D2,
D1,DO

DTMF 3,
2,1,0

0
1

0
1

01

0
1

Programs 1 of 16 DTMF tone pairs that will be
transmitted when TX DTM F and TX enable bit (CRO, bit
D1) are set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT

DTMF CODE
D3 D2 D1 DO

1

0

0

2

0

0

0
1

I

TONES
LOW HIGH

1

697

1209

0

697

1336

3

0

0

1

1

697

1477

4

0

1

0

0
- -

770

1209

5

0

1

770

0

1

0
1

1

6

0

770

1336
1477

7

0

1

1

1

852

1209

8

1

0

0

0

852

1336

9

1

0

0

1

852

1477

0

1

0

1

0

941

1336

*

0
1

1

1

941

#

1
1

0

0

941

1209
1477

A

1

1

0

1

697

1633

B

1

1

1

0

770

1633

1

852
941

1633

---~

D4

Transmit
DTMF

Transmit
Answer
Tone

1

1

1

D

0

0

0------ 0

1633

0

Disable DTMF.

1

Activates DTMF. The selected DTMF tones are
transmitted continuously when this bit is high. TX
DTMF overrides all other transmit functions.

D5 D4 DO
D5

C

D5 interacts with bits D4 and DO as shown.

0

0

X

Disables answer tone generator.

1

0

0

Enables answer tone generator. A 2225 Hz answer
tone will be transmitted continuously when the Transmit Enable bit is set in CRO. The device must be in
answer mode.

1

0

1

Likewise a 2100 Hz answer tone will be transmitted.

3-63

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem

TONE REGISTER (Continued)

TR
011

07

06

RXO
OUTPUT
CONTR.

TRANSMIT
GUARD
TONE

BIT NO.

D7

04

TRANSMIT TRANSMIT
ANSWER
DTMF
TONE
CONDITION

NAME

06

05

03

02

01

DO

DTMF3

DTMF2

DTMF 11
OVERSPEED

DTMF 01
ANSWERI
GUARD

DESCRIPTION

Transmit
Guard Tone

0

Disables guard tone generator.

1

Enables guard tone generator (See DO for selection
of guard tones).

RXD Output
Control

0

Enables RXD pin. Receive data will be output on
RXD.

1

Disables RXD pin. The RXD pin reverts to a high
impedance with internal weak pull-up resistor.

10 REGISTER

10
110
BIT NO.

07

06

D5

D4

ID

ID

10

10

NAME

CONDITION

D7 06 D5 D4
D7,06

DESCRIPTION

Indicates Device:

Device
Identification
Signature

~----------4---------~~------------------------~

3-64

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER

RATING

VDD Supply Voltage

14V

Storage Temperature

-65 to 150°C

Soldering Temperature (10 sec.)

260°C

Applied Voltage

-0.3 to VDD+0.3V

-------------

-~

Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.

RECOMMENDED OPERATING CONDITIONS
MIN

NOM

VDD Supply voltage

4.5

5

T A, Operating Free-Air
Temperature

-40

PARAMETER

Clock Variation

CONDITIONS

-----

(11.0592 MHz) Crystal or
external clock

-0.01

-

MAX

UNITS

5.5

V

+85

°C

+0.01

%

---

External Components (Refer to Application section for placement.)
VREF Bypass Capacitor

(External to GND)

0.1

Bias setting resistor

(Placed between VDD
and ISET pins)

1.8

ISET Bypass Capacitor

(ISET pin to GND)

0.1

IlF

VDD Bypass Capacitor 1

(External to GND)

0.1

IlF

VDD Bypass Capacitor 2

(External to GND)

22

IlF

IlF
2

2.2

XTL 1 Load Capacitor

Depends on crystal characteristics;

40

XTL2 Load Capacitor

from pin to GND

20

3-65

Mn

pF

I

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
ELECTRICAL SPECIFICATIONS

(Continued)

DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)
PARAMETER

CONDITIONS

100, Supply Current

= 2 Mn
= 11.0592 MHz
ClK = 11.0592 MHz
ClK = 19.200 KHz

IDDA, Active
1001, Power-down
1002, Power-down

MIN

NOM

ISET Resistor

MAX

UNITS

12

mA

4

rnA

3

mA

VDD

V

VDD

V

0.8

V

100

50

J.IA
J.IA
J.IA

10

pF

VDD

V

0.4

V

0.6

V

-50

J.IA

15

pF

--

ClK

8

Digital Inputs
VIH Input Hiah Voltaae

1--

Reset, XTl1, XTl2

3.0

All other inputs

2.0

Vll, Input low Voltage

0

Reset Pull-down Current

= VIH Max
VI = Vil Min
Reset = VDD

Input Capacitance

All Digital Input Pins

IIH, Input High Current
Ill, Input low Current

VI

-- -

-200
1

Digital Outputs

RXD Tri-State Pull-up Curro

= -0.4 rnA
10 MAX = 1.6 rnA
10 = 3.6 rnA
RXD = GND

CMAX, elK Output

Maximum Capacitive load

VOH, Output High Voltage
VOL, Output low Voltage
VOL, ClK Output

IOH MIN

3-66

2.4

-1

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.)
PARAMETERS

CONDITIONS

MIN

NOM

MAX

UNITS

-9

dBmO

PSK Modulator
Carrier Suppression

Measured at TXA

55

Output Amplitude

TX scrambled marks

-11

-1~o=f

dB

FSK Mod/Demod
Output Freq. Error

ClK

= 11.0592 MHz

-0.35

Transmit level

Transmit Dotting Pattern

-11

Harmonic Distortion
in 700-2900 Hz band

+.35

%

-10.0

-9

dBmO

THD in the alternate band
DPSK or FSK

-60

-50

dB

Output Bias Distortion

Transmit Dotting Pattern
in ALB@ RXD

±8

Total Output Jitter

Random Input in ALB @ RXD

%

~----

-15

--

+15

%

DTMF Generator
Freq. Accuracy

-.25

+.25

%

Output Amplitude

low Band, DPSK Mode

-10

-9

-8

dBmO

Output Amplitude

High Band, DPSK Mode

-8

-7

-6

dBmO

Twist

High-Band to Low-Band, DPSK Mode

1.0

2.0

3.0

dB

Long Loop Detect

DPSK or FSK

-38

-28

dBmO

Dynamic Range

Refer to Performance Curves

-----

45

dB

-.~~-.----

Call Prog ress Detector

---

-34

Detect level

2-Tones in 350-600 Hz band

Reject level

2-Tones in 350-600 Hz band

Delay Time

-70 dBmO to -30 dBmO STEP

27

80

ms

Hold Time

-30 dBmO to -70 dBmO STEP

27

80

ms

Hysteresis
Note:

-.-.-~

--

2

0

dBmO

-41

dBmO

----

Parameters expressed in dBmO refer to the following definition:

o dB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.

3-67

dB

I

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DYNAMIC CHARACTERISTICS AND TIMING
PARAMETERS
Carrier Detect

(Continued)

CONDITIONS

MIN

NOM

MAX

UNITS

DPSK or FSK

Threshold

receive data

-49

-42

dBmO

Delay Time

-70 dBmO to -30 dBmO STEP

15

45

ms

Hysteresis

Single tone detected

2

Hold Time

-30 dBmO to -70 dBmO STEP

10

24

ms

-49.5

-42

dBmO

20

45

ms

10

30

ms

-2.5

+2.5

%

3.0

dB

Answer Tone Detector
Detect Level

Not in V.21 mode

Delay Time

-70 dBmO to -30 dBmO STEP

Hold Time

-30 dBmO to -70 dBmO STEP

Detect Freq. Range

Output Smoothing Filter
Output load

Spurious Freq. Compo

TXA pin; FSK Single

kG

10

Tone out for THD = -50 db
in .3 to 3.4 KHz

50

pF

Frequency = 76.8 kHz

-39

dBmO

Frequency = 153.6 kHz
TXA pin Output Impedance

Clock Noise

200
TXA pin; 76.8 KHz

-45

dBmO

300

G

1.0

mVrms

+10

Hz

100

ms

+625

ppm

50

ms

CarrlerVCO
Capture Range

Originate or Answer

Capture Time

-10 Hz to +10 Hz Carrier
Freq. Change Assum.

-10
40

Recovered Clock
Capture Range

% of frequency
center frequency
(center at 1200 Hz)

Data Delay Time

Analog data in at RXA pin to
receive data valid at RXD pin

3-68

-625

.30

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS

CONDITIONS

MIN

NOM

Guard Tone Generator
Tone Accuracy

MAX

--

-----

550 Hz

UNITS

--------

-20

1800 Hz

+20

Hz

-~

Tone level

550 Hz

-4.0

-3.0---

-2.0

dB

(Below DPSK Output)

1800 Hz

-7.0

-6.0
----

-5.0

dB

Harmonic Distortion

550 Hz

-50

dB

700 to 2900 Hz

1800 Hz

-60

dB

----

Timing (Refer to Timing Diagrams)
--,----

*

TAL

CS/Addr. setup before ALE Low

30

TLA

CSI Addr. hold after ALE Low

20

TlC

ALE Low to RDIWR Low

40

TCl

RD/WR Control to ALE High

10

TRD

Data out from RD Low

0

TlL

ALE width

60

TRDF

Data float after RD High

0

ns
ns

- - - - - c---

ns
ns
140

ns
ns

200

ns

TRW

RDwidth

200

25000

ns

TWW

WRwidth

140

25000

ns

TOW

Data setup before WR High

150

TWO

Data hold after WR High

20

TCKD

Data out after EXCLK Low

TCKW

WR after EXClK low

150

ns

TDCK

Data setup before EXClK Low

150

ns

ns
ns
200

ns

----

TAC

Address setup before control*

50

ns

TCA

Address hold after control*

50

ns

TWH

Data Hold after EXCLK

20

Control for setup is the falling edge of RD or WR.
Control for hold is the falling edge of RD or the rising edge of WR.

3-69

I

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
ALE

~
~
:...

TlC .. ~

RD

TRW

-r

1

TCl

-,1-

r
TlC

L
ADO-AD7

.L

TWW

J

I~

~ ~ .~I

+

WR

--K

cs ~-

TAL

TlA

TRD

TRDF

.tJ

~

~

ADDRESS } - - - K READ DATA}---K ADDRESS

-i-

-~-

I TWD

TOW

~~

-~-

READ TIMING DIAGRAM (SERIAL VERSION)
EXClK

RD

~~--------------r-

AO-A2

DATA - - +

WRITE TIMING DIAGRAM (SERIAL VERSION)
EXClK

-----+--------------------------------------~~

TCKW TAC

F

AO-A2.

---+-------------------------\+

DATA

3-70

HTWW
I~
TCA

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
APPLICATIONS INFORMATION
GENERAL CONSIDERATIONS
Figures 1 and 2 show basic circuit diagrams for
K-Series modem integrated circuits. K-Series products
are designed to be used in conjunction with a control
processor, a UART or RS-232 serial data interface,
and a DAA phone line interface to function as a typical
intelligent modem. The K-Series ICs interface directly
with Intel 8048 and 80C51 microprocessors for control
and status monitoring purposes. Two typical DAA arrangements are shown: one for a split ±5 or ±12
volt design and one for a single 5 volt design. These
diagrams are for reference only and do not represent
production-ready modem designs.

K-Series devices are available with two control interface versions: one for a parallel multiplexed address/
data interface, and one for a serial interface. The
parallel version is intended for use with 8039/48 or
8031/51 microcontrollers from Intel or many other
manufacturers. The serial interface 22-pin version can
be used with other microcontrollers or in applications
where only a limited number of port lines are available
or the application does not lend itself to a multiplexed
address/data interface. The parallel versions may also
be used in the serial mode, as explained in the data
sheet pin description.
In most applications the controller will monitorthe serial
data for commands from the DTE and the received
data for break signals from the far end modem. In this
way, commands to the modem are sent over the same
line as the transmitted data. In other applications the
RS-232 interface handshake lines are used for modem
control.

Cl

RS232
LEVEL
CONVERTERS

CA

390 pF

'"">-.j....:.!!.:,-----"

CB ......... ".,...-~

CC ......... ,-.-------,
CD

H>t-='----1

iNA
ALE

C§

SSI
K·SERIES
LOW
POWER
FAMILY

RXA

f..-.----l f.-----~

TXA

r---t t-~vvv '-<>-j

BA
BB

DA

I~~~--+--t--r-----j

DO

-_ _ _ _ _--.-J

RING

~----------------~

FIGURE 2: Single 5V Hybrid Version
3-72

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
Unlike digital logic circuitry, modem designs must
properly contend with precise frequency tolerances
and very low level analog signals, to ensure acceptable
performance. Using good analog circuit design practices will generally result in a sound design. Following
are additional recommendations which should be
taken into consideration when starting new designs.
CRYSTAL OSCILLATOR

The K-Series crystal oscillator requires a parallel mode
(antiresonant) crystal which operates at 11.0592 MHz.
It is important that this frequency be maintained to
within ±0.01% accuracy.
In order for a parallel mode crystal to operate correctly
and to specification, it must have a load capacitor
connected to the junction of each of the crystal and
internal inverter connections, terminated to ground.
The values of these capacitors depend primarily on the
crystal's characteristics, and to a lesser degree on the
internal inverter circuit. The values used affect the
accuracy and start up characteristics of the oscillator.

MODEM PERFORMANCE
CHARACTERISTICS
The curves presented here define modem IC performance under a variety of line conditions while inducing
disturbances that are typical of those encountered
during data transmission on public service telephone
lines. Test data was taken using an AEA Electronics'
"Autotest I" modem test set and line Simulator, operating under computer control. All tests were run fullduplex, using a Concord Data Systems 224 as the
reference modem. A 511 pseudo-random-bit pattern
was used for each data point. Noise was C-message
weighted and all signal-to-noise (SIN) ratios reflect
total power measurements similar to the CCITT V.56
measurement specification. The individual tests are
defined as follows.
BER vs. SIN

This test measures the ability of the modem to operate
over noisy lines with a minimum of data-transfer errors.
Since some noise is generated in the best of dial-up
lines, the modem must operate with the lowest SIN
ratio possible. Better modem performance is indicated
by test curves that are closest to the BER axis. A
narrow spread between curves representing the four
line parameters indicates minimal variation in performance while operating over a range of aberrant operating conditions. Typically, a DPSK modem will exhibit
better BER-performance test curves receiving in the
low band than in the high band.

LAYOUT CONSIDERATIONS

Good analogldigital design rules must be used to
control system noise in orderto obtain highest performance in modem designs. The more digital circuitry
present on the PC board, the more this attention to
noise control is needed. The modem should be treated
as a high impedance analog device. A 22 mF electrolytic capacitor in parallel with a 0.1 mF ceramic capacitor between VDD and GND is recommended. Liberal
use of ground planes and larger traces on power and
ground are also highly favored. High speed digital
circuits tend to generate a significant amount of EMI
(Electro-Magnetic Interference) which must be minimized in order to meet regulatory agency limitations.
To accomplish this, high speed digital devices should
be locally bypassed, and the telephone line interface
and K-Series device should be located close to each
other near the area of the board where the phone line
connection is accessed. To avoid problems, power
supply and ground traces should be routed separately
to the analog and digital functions on the board, and
digital signals should not be routed near low level or
high impedance analog traces. The analog and digital
grounds should only connect at one pOint near the
K-Series device ground pin to avoid ground loops. The
K-Series modem IC's should have both high frequency and low frequency bypassing as close to the
package as possible.

BER vs. Receive Level

This test measures the dynamic range of the modem.
Because signal levels vary widely over dial-up lines,
the widest possible dynamic range is desirable. The
minimum Bell specification calls for 36 dB of dynamic
range. SIN ratios are held constant at the indicated
values while the receive level is lowered from a very
high to very low signal levels. The width of the "bowl" of
these curves, taken at the BER point, is the measure of
dynamic range.

3-73

3

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem

*SSI 73K222L
BER vs SIGNALTO NOISE

*SSI 73K222L
BER vs CARRIER OFFSET
10-2

10-2

1

RECEIVE~
~dBm

r1

HIGH BAND

\

,

\

\~ I~~

\

10-3

600

"
~ k\- f--

BPS

\1\
\~\
~ rr- ~
Ir -

10-<4

DPSK OPERATION

\

10-3

~

,\l\
~\r\

i\

1\

1\ \1\

1\

\\

2

6

4

3002 11.8 dB SIN

'l\\

\ l\

10-5

10-4

\
KC101'3OO2J

1\\ ~ ~

10-5

t-

C2

~~ H'c;';~2
\: ~\- H ~
.---

\

\I~

HIGH BAND RECEIVE
DPSK OPERATION

---L.

8

\1'

12

\

-

!\

V l....I-

I-- ~

I-- f-I-- f-- I-'

1\ l\

10

~

1C211.3dBSlN

10-5

10-6
14

8

12

SIGNAL TO NOISE (dB)

4

-4

0

-8

-12

CARRIER OFFSET (HZ)

*SS173K222L
BER vs RECEIVE LEVEL

*SSI 73K222L
BER vs PHASE JITTER
10-2

10-2

I HIGH
BAND RECEIVEr
DPSK OPERATION
I

JI HIGH
BAND RECEIVE
DPSK OPERATION

C2 LINE

10-3

10-3

10-<4

10-4

-f-- ~

300211.5dBSlN

./

I'-

"

10-5

V

V' v v
V
"\
~ ~ I-

S/N-l0.8dB

)

t-

10-5

l

C210.8dBSlN]

r-- f--

S/N-15dB
10-6

10-6
10

0

-10

-20

-30

-40

-50

0

4

*

8

12

16

PHASE JITTER (0 PEAK)

RECEIVE LEVEL (dSm)

"EO On" Indicates bit CR1 04 is set for additional phase equalization.
3-74

20

24

SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
PACKAGE PIN DESIGNATIONS

CAUTION: Use handling procedures necessary
for a static sensitive component.

(Top View)

ClK

GND

RXA

GND

XTl1

RXA

XTl2

VREF

ADO

RESET

VREF
XTL1

RESET

XTL2

ISET

AD1

ISET

AD2

RXClK

AD3

RXD

4

3

2

1282726
25

RXCLK

A04

TXD

A1

RXD

ADS

cs

A2

TXD

AD6

EXClK

EXCLK

AD?

TXClK

TXCLK

ALE

INT

10

20

jNf

WR

TXA

11

19

TXA

RD

VDD

WR

9

AD
VDD

400-MII
22-Pln DIP

24

PlCC PINOUTS
ARE THE SAME AS
THE 28-PIN DIP

23
22
21

12 13 14 15 16 17 18

28-Pin
PLCC

6OO-MII
28-Pin DIP

ORDERING INFORMATION
ORDER NO.

PKG.MARK

SSI 73K222L with Parallel Bus Interface
28-Pin Dip
28-Pin PLCC

73K222L-IP
73K222L-IH

73K222L-IP
73K222L-IH

SSI 73K222L with Serial Interface
22-Pin Sip

73K222SL-IP
73K222SL-IC

73K222SL-IP
73K222SL-IC

PART DESCRIPTION

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914

0194 - rev.
3-75

Protected by the following Patents (4,691,172) (4,777,453)
©1989 Silicon Systems, Inc.

I

Notes:

3-76

SSI73K222U
Single-Chip Modem
with UART

December 1993

DESCRIPTION

FEATURES

The SSI 73K222U is a compact, high-performance
modem which includes a 8250N16C450 compatible
UART with the 1200 bitls modem function on a single
chip. Based on the SSI 73K222L 5V low power CMOS
modem IC, the SSI 73K222U is the perfect modeml
UART component for integral modem applications. It is
ideal for applications such as portable terminals and
laptop computers. The SSI 73K222U is the first fully
featured modem IC which can function as an intelligent
modem in integral applications without requiring a
separate dedicated microcontroller. It provides for data
communication at 1200, 600, and 300 biVs in a multimode manner that allows operation compatible with
both Bell 212N103 and CCITT V.22N.21 standards.
The digital interface section contains a high speed
version of the industrystandard 8250N16C450 UART,
commonly used in personal computer products. A
unique feature of the SSI 73K222U is that the UART
section can be used without the modem function,
providing an additional asynchronous port at no added
cost. The 551 73K222U is designed in CMOS teChnology and operates from a single +5V supply. Available
paGkaging includes 40-pin DIP or 44-pin PLCC for
surface mount applications.

• Modem/UART combination optimized for integral bus
applications
• Includes features of SSI 73K222L single-chip modem
• Fully compatible 16C450/8250 UART with 8250B or
8250A selectable interrupt emulation
• High speed UARTwili interface directlywith high clock
rate bus with no wait states
• Single-port mode allows full modem and UARTcontrol
from CPU bus, with no dedicated microprocessor
required
• Dual-port mode suits conventional designs using local microprocessor for transparent modem operation
• Complete modem functions for 1200 bitls (Bell 212A,
V.22) and 0-300 bitls (Bell 103, V.21)
• Includes DTMF generator, carrier, call-progress and
precise answer-tone detectors for intelligent dialing
capability
• On chip 2-wire/4-wire hybrid driver and off-hook relay
buffer
• Speaker output with four-level software driven volume
control
• Low power CMOS (40 mW) with power down mode
(15 mW)
• Operates from single +5V supply

PIN DIAGRAM

BLOCK DIAGRAM
TXD

XTL1

XTL2

ClK

TXAl

UDO
UDI

TXA2

UD2

RXA

UD3

SPKR

UD4
UDS
UD6
UD7

8250A I 16C450
UART

f-...'-----4-1

(CTS)! MAO

f------+i

(DSR)! MAt

1 - - - - - - 4 -. . (UA3) !MA2
1------4-1

UAO

DATA!(DTR)
RD!(ADS)

UAI

WR!(N!C)

UA2
DOSTR

1------4-1

(DCD)!DClK

DISTR

f------+i

(RTS)!iNf

C52

>----1-...

OH

RELAY
DRIVER

INTRPT

(Ai) J1f'RST

RESET

RXD

VDD VREF GND

Parentheses indicate single·port mode.

ISET STNDlN

CAUTION:

1293- rev.

3-77

Use handling procedures necessary
for a static sensitive component.

I

SSI73K222U
Single-Chip Modem
with UART
FUNCTIONAL DESCRIPTION

interrupt operation. The UART used in the
551 73K222U can be used with faster bus read and
write cycles than a conventional 16C450 UART. This
allows it to interface directly with higher clock rate
microprocessors with no need for external circuitry to
generate wait states.

The 551 73K222U integrates an industry standard
8250/16C450 UART fu nction with the modem capability provided by the 551 73K222l single chip modem IC.
The 551 73K222U is designed specifically for integral
microprocessor bus intelligent modem products. These
designs typically require the standard 8250 or higher
speed 16450 UART to perform parallel-to-serial and
serial-to-parallel conversion process necessary to interface a parallel bus with the inherently serial modem
function. The 551 73K222U provides a highly integrated design which can eliminate multiple components in any integral bus modem application, and is
ideal for internal PC modem applications.

The primary function of the UARTis to perform parallelto-serial conversion on data received from the CPU
and serial-to-parallel conversion on data received from
the internal modem or an external device. The UART
can program the numberof bits per character, parity bit
generation and checking, and the number of stop bits.
The UART also provides break generation and detection, detection of error conditions, and reporting of
status at any time. A prioritized maskable interrupt is
also provided.

The 551 73K222U includes two possible operating
modes. In the dual-port mode, the device is suitable for
conventional plug-in modem card designs which use a
separate local microprocessor for command interpretation and control of the modem function. In this mode,
a dedicated microcontroller communicates with the
551 73K222U using a separate serial command port.
In the single-port mode the main CPU can control both
the UART and modem function using the parallel data
bus.This allows very efficient modem design with no
local microprocessor required for dedicated applications such as laptop PC's or specialized terminals.

The UART block has a progammable baud rate generator which divides an internal 1.8432 MHz clock to
generate a clock at 16x the data rate. The data rate for
the transmit and receive sections must be the same.
For DPSK modulation, the data rate must be 1200 Hz
or 600 Hz. For F5K modulation, the data rate must be
300 Hz or less. The baud generator can create a clock
that supports digital transfer at up to 115.2 kHz. The
output of the baud generator can be made available at
the ClK pin under program control.
MODEM FUNCTION (881 73K222L)

To make designs more space effiCient, the
551 73K222U includes the 2-wire to 4-wire hybrid
drivers, off-hook relay -driver, and an audio monitor
output with software volume control for audible call
progress monitoring. As an added feature the UART
function can be used independent of the modem function, providing an added asynchronous port in a typical
PC application with no additional circuitry required.

The modem section of the SSI 73K222U provides all
necessary analog functions required to create a single
chip Bell 212A1103 and CCID V.22IV.21 modem,
controlled by the system CPU or a local dedicated
microprocessor. Asynchronous 1200 bitls DPSK (Bell
212A and V.22) and 300 baud FSK (Bell 103 and V.21)
modes are supported.
The modem portion acts as a peripheral to the microprocessor. In both modes of operation, control information is stored in register memory at specific address
locations. Inthe single-port mode, the modem section
can be controlled through the 16C450 interface, with
no external microcontroller required. The primary analog blocks are the DPSK modulator/demodulator, the
FSK modulator/demodulator, the high and low band
filters, the AGC, the special detect circuitry, and the
DTMF tone ge!1erator. The analog functions are performed with switched capacitor technology.

UART FUNCTION (16C450)
The UART section of the 551 73K222U is completely
compatible with the industry standard 16C450 and the
8250 UART devices. The bus interface is identical to
the 16450, except that only a single polarity for the
control signals is supported. The register contents and
addresses are also the same as the 16C450. To insure
compatibility with all existing releases of the 8250
UART deSign, external Circuitry normally used in PC
applications to emulate 8250B or 8250A interrupt operation has been included on the 551 73K222U.
A select line is then provided to enable the desired
3-78

SSI73K222U
Single-Chip Modem
with UART
PSK MODULATOR / DEMODULATOR

SPECIAL DETECT CIRCUITRY

The SSI 73K222U modulates a serial bit stream into
dibit pairs that are represented by four possible phase
shifts as prescribed by the Bell 212A or V.22 standard.
The baseband signal is then filtered to reduce intersymbol interference on the band limited 2-wire PSTN
line. Transmission occurs using either a 1200 Hz
(originate mode) or 2400 Hz carrier (answer mode).
Demodulation is the reverse of the modulation process, with the incoming analog signal eventually decoded into dibits and converted back to a serial bit
stream. The demodulator also recovers the clock which
was encoded into the analog signal during modulation.
The demodulator decodes either a 1200 Hz carrier
(originate carrier) or a 2400 Hz carrier (answer carrier).
The SSI 73K222U uses a phase-locked-loop coherent
demodulation technique that offers inherently better
performance than typical DPSK demodulators used by
other manufacturers.

The special detect circuitry monitors the received analog signal to determine status or presence of carrier,
call-progress tones, answer tone, and weak received
signal (long loop condition). An unscrambled mark
signal is also detected when the received data out of
the DPSK demodulator before the descrambler has
been high for 165.5 mS ±13.5 mS. The appropriate
status bit is set when one of these conditions changes
and an interrupt is generated for all monitored conditions except long loop. The interrupts are disabled
(masked) when the enable interrupt bit is set to a O.
DTMF GENERATOR
The DTMF generator will output one of 16 standard
dual-tones determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mode
is selected and the transmit enable (CRO bit 01) is
changed from a 0 to a 1.

FSK MODULATOR/DEMODULATOR

TEST FEATURES

The FSK modulator frequency modulates the analog
output signal using two discrete frequencies to represent the binary data. In Bell 103, the standard frequencies of 1270 Hz and 1070 Hz (originate mark and
space) and 2225Hz and 2025 Hz (answer mark and
space) are used. V.21 mode uses 980 Hz and 1180 Hz
(originate, mark and space) or 1650 Hz and 1850 Hz
(answer, mark and space). Demodulation involves
detecting the received frequencies and decoding them
into the appropriate binary value.

Test features such as analog loopback (ALB), remote
digital loopback, local digital loopback, and internal
pattern generators are also included.
LINE INTERFACE
The line interface ofthe SSI73K222U consists of a twoto-four wire hybrid, and an off-hook relay driver.
The two-to-four wire converter has a differential transmit output and requires only a line transformer and an
external impedance matching resistor. Four-wire
operation is also available by simply using either of the
transmit output signals.

PASSBAND FILTERS AND EQUALIZERS
A high and low band filter is included to shape the
amplitude and phase response of the transmit signal
and provide compromise delay equalization and rejection of out-of-band signals in the receive channel.
Amplitude and phase equalization is necessary to
compensate for distortion of the transmission line and
to reduce intersymbol interference in the band limited
receive signal. The transmit signal filtering approximates a 75% square root of raised Cosine frequency
response characteristic.

The relay driver output of the SSI 73K222U is an open
drain signal capable of sinking 20 mA, which can
control a line closu re relay used to take the line off hook
and to perform pulse dialing.
AUDIO MONITOR
An audio monitor output is provided which has a
software programmable volume control. Its output is
the received signal. The audio monitor output can
directly drive a high impedance load, but an external
power amplifier is necessary to drive a low-impedance

AGC
The automatic gain control maintains a signal level at
the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping, and provides a total
dynamic range of >45 dB.
3-79

I

SSI73K222U
Single-Chip Modem
with UART
PIN DESCRIPTION

GENERAL
NAME

DIP

PLCC

TYPE

VDD

40

44

I

+5V Supply ±1 0%, bypass with a .1 and a 22JlF capacitor
toGND

GND

20

22

I

System Ground

VREF

19

21

0

VREF is an internally generated reference voltage which is
externally bypassed by a 0.1 f,lF capacitor to the system
ground.

ISET

9

11

I

The analog current is set by connecting this pin to VDD
through a 2 Mn resistor. ISET should be bypassed to GN D.
Alternatively, an internal bias can be selected by connecting ISET to GND, which will result in a larger worst-case
supply current due to the tolerance of on-chip resistors.
Bypass with .1 f,lF capacitpr if resistor is used.

XTL1

25

27

I

XTl2

24

26

I

These pins are connections for the internal crystal
oscillator requiring an 11.0592 MHz crystal (9216Hz x
1200). XTl2can also be TIL driven from an external clock.

ClK

21

23

0

Output Clock. This pin is selectable under processor control to be either the crystal frequency (which might be used
as a processor clock) or the output of the baud generator.

RESET

10

12

I

Reset. An active signal (high) on this pin will put the chip into
an inactive state. The control register bits (except the
Receiver Buffer, Transmitter Holding, and Divisor latches)
will be reset. The output of the ClK pin will be set to the
crystal frequency. An internal pull-down resistor permits
power-on reset using a 0.1 JlF capacitor connected to the
5V supply.

STNDlN

15

17

I

Single-port mode select (active high). In a single-port
system there is no local microprocessor and all the modem
control is done through the 16C450 parallel bus interface.
The local microprocessor interface is replaced with UART
control signals which allow the device to function as a digital
UART as well as modem.

DESCRIPTION

3-80

SSI73K222U
Single-Chip Modem
with UART
PIN DESCRIPTION (continued)
UART INTERFACE
DIP

PLCC

TYPE

UAO-UA2
UA3

37-39
12

41-43
14

I
I

UART Address. These pins determine which of the UART
registers is being selected during a read or write on the
UART data bus. The contents of the DLAB bit in the
UART's Line Control Register also control which register is
referenced. In single-port mode, UAO-UA3 are latched
when ADS goes high. In dual-port, only UAO-UA2 are
used.

UDO-UD7

27-34

30-37

1/0

(3 state) UART Data. Data or control information to the
UART registers is carried over these lines.

DISTR

35

38

I

Data Input Strobe. A low on this pin requests a read of the
internal UART registers. Data is output on the DO-D7 lines
if DISTR and CS2 are active.

DOSTR

36

39

I

Data Output Strobe. A low on this pin requests a write of the
internal UART registers. Data on the DO-D7 lines are
latched on the rising edge of DOSTR. Data is only written
if both DOSTR and CS2 are active.

CS2

1

2

I

Chip Select. A low on this pin allows a read or write to the
UART registers to occur. In single port mode, CS2 is latched
on ADS.

INTRPT

5

7

0

(3 state) UART Interrupt. This signal indicates that an
interrupt condition on the UART side has occurred. If the
Enable 8250A interrupt bit in the interrupt Enable Register
is 0 the interrupt is gated by the DISTR signal to provide
compatibility with the 8250B. The output can be put in a high
impedance state with the OUT2 register bit in the Modem
Control Register. In single-port mode, INTRPT also becomes valid when a modem interrupt signal is generated by
the modem section's Detect Register.

RXD

6

8

1/0

Function is determined by STNDLN pin and bit 7, Tone
Control Register:

NAME

DESCRIPTION

STNDLN

D7

0

0

RXD outputs data received by modem.

1

0

RXD is electrically an input but signal is
ignored.

X

1

RXD is a serial input to UART.

3-81

I

SSI73K222U
Single-Chip Modem
with UART
PIN DESCRIPTION (continued)
UART INTERFACE (continued)
TXD

7

9

0

Function is determined by STNDLN pin and bit 7, Tone
Control Register:
---"'._-~.---

STNDLN

D7

0

0

1

0

TXD is forced to a mark.

X

1

TXD is a serial output of UART.

TXD is a serial output of UART.
-~

ANALOG I LINE INTERFACE
NAME

DIP

PLCC

TYPE

TXA1
TXA2

3
4

4

5

0
0

(differential) Transmitted Analog. These pins provide the
analog output signals to be transmitted to the phone line.
The drivers will differentially drive the impedance of the line
transformer and the line matching resistor. An external
hybrid can also be built using TXA 1 as a single ended
transmit signal.

RXA

16

18

I

Received Analog. This pin inputs analog information that is
being received by the two-to-four wire hybrid. This input
can also be taken directly from an external hybrid.

SPKR

17

19

0

Speaker Output. This pin outputs the received signal through
a programmable attenuator stage, which can be used for
volume control and disabling the speaker.
--

OH

18

20

0

Off-hook relay driver. This signal is an open drain output
capable of sinking 20mA and is used for controlling a relay.
The output is the complement of the OH register bit in CR3.

DESCRIPTION

3-82

SSI73K222U
Single-Chip Modem
with UART
PIN DESCRIPTION (continued)
UART CONTROL INTERFACE (STNDLN
(See Figure 1: Single-port mode)

=1)

NAME

DIP

PLCC

TYPE

ADS

23

25

I

Address Strobe. ADS is used to latch address and chip
select to simplify interfacing to a multiplexed Address/Data
Bus. UAO-UA3 and CS2 are latched when the ADS signal
goes high.

UA3

12

14

I

UART Address Bit 3. UA3 is used in single-port mode to
address the modem registers from the 16C450 interface.
If UA3 is 0, the normal 16C450 registers are addressed by
UAO-UA2 and if UA3 is 1, the modem registers are addressed. UA3 is latched when ADS goes high.

CTS

14

16

I

Clear to Send. This pin is the complement of CTS bit in the
Modem Status Register. The signal is used in modem
handshake control to signify that communications have
been established and that data can be transmitted.

DSR

13

15

I

Data Set Ready.This pin is the complement of DSR bit in
the Modem Status Register.The signal is used in modem
handshake to signify that the modem is ready to establish
communications.

DCD

11

13

I

Data Carrier Detect. This pin is the complement of DCD bit
in the Modem Status Register. The signal is used in modem
control handshake to signify that the modem is receiving a
carrier.

DTR

22

24

0

Data Terminal Ready.The DTR output is programmed
through a bit in the Modem Control Register. The signal is
used in modem handshake to signify that the 16C450 is
available to communicate.

RTS

2

3

0

Request to Send. The RTS output is programmed through
a bit in the Modem Control Register. The signal is used in
modem handshake to signify that the 16C450 has data to
transmit.

RI

8

10

I

Ring Indicator. This Indicates that a telephone ringing
signal is being received. This pin is the complement of the
RI bit in the Modem Status Register.

DESCRIPTION

3-83

I

SSI73K222U
Single-Chip Modem
with UART
PIN DESCRIPTION (continued)
MICROPROCESSOR INTERFACE (STNDLN
(See Figure 2: Dual-port mode)
NAME

= 0)

DIP

PLCC

TYPE

12-14

14-16

I

Modem Address Control. These lines carry register
addresses for the modem registers and should be valid
throughout any read or write operation.

DATA

22

24

I/O

Serial Control Data. Serial control data to be read/written is
clocked in/out on the falling edge of the DCLK pin. The
direction of data transfer is controlled by the state of the RD
pin. If the RD pin is active (low) the DATA line is an output.
Conversely, if the RD pin is inactive (high) the DATA line is
an input.

RD

23

25

I

Read. A low on this input informs the SSI 73K222U that
control data or status information is being read by the
processor from a modem register.

WR

26

28

I

Write. A low on this input informs the SSI 73K222U that
control dataor status information is available for writing into
a modem register. The procedure for writing is to shift in
data LSB first on the DATA pin for eight consecutive cycles
of DCLK and then to pulse WR low. Data is written on the
rising edge of WR.

DCLK

11

13

I

Data Clock. The falling edge of this clock is used to strobe
control data for the modem registers in or out on the DATA
pin. The normal procedure for a write is to shift in data LSB
first on the DATA pin for eight consecutive cycles of DCLK
and then to pulse WR low. Data is written on the rising edge
of WR. The falling edge of the RD signal must continue for
eight cycles of DCLK in order to read all eight bits of the
reference register. Read data is provided LSB first. Data
will not be output unless the RD signal is active.

INT

2

3

0

(with weak pull-up) Modem Interrupt. This output signal is
used to inform the modem processor that a change in a
modem detect flag has occurred. The processor must then
read the Modem Detect Register to determine which detect
triggered the interrupt. INTwili stay active until the processor reads the Modem Detect Register or does a full reset.

mPRST*

8

10

0

Microprocessor Reset. This output signal is used to provide a hardware reset to the microprocessor. This signal is
high if the RESET pin is high or the MCR bit D3 (OUT1) bit
is set.

MAO-MA2

DESCRIPTION

* NOTE: The mPRST pin is an upgraded function which was not included in the initial definition of the
SSI 73K222U.

3-84

CfSIlSII;rn;iXDII'fSNC

OH

VOO

VREF

GN>

ISET

999 9

I

RELAY

DRIVER

I

?

1.8432 MHZ

RiO----+--l

CS2

jjSTii
ill5SfR
(.oJ

Co
U1

ADiI

FIGURE 1:

en

Single-Port Mode

:::J

(Q
(1)

In the single-port mode, the SSI 73K222U is designed to be
accessed only by the main CPU,using the same parallel bus utilized
for data transfer. This mode is enabled when the STNDLN pin is at
a logic "1". Inthe single port mode, internal registers are accessed
by the main CPU to configure both the UART section and the

modem function, eliminating the need for a separate microcontroller. In this mode, multiplexed pins provide the eTS, DSR, DTR,
OED and RI signals normally associated with the UART function. A
separate pin, ADS, is used for bus control.

len
°en

~~­

::; "'C .......

'::rs:W

c:O"
»Q.N
:D(1)~

-43c:

....

Ail

WR

C5R

lNi'

\{)IJ

VF£F

GNO

ISET

999 9

I

"'LAY
DRIVER

POWER

I

=e~~
-:::s_

?

:::J"'CC ~

C:(i)w

»1"

1.1432 MHZ

.... 01\)
oN:::J"'1\)

-I _.

I\)

"ac:
3:

SPKR

,-------'

CS2
iiiSi'R
0i5STI'i

I
OIGITAl
lOOPBACK

CA)

~

FIGURE 2:
Dual-Port Mode

The dual-port mode allows use of a dedicated microprocessor for
control of the modem function, and is enabled when the STNDLN
pin = "0". This mode is useful for conventional plug-in card modem
designs where it is necessary to make the modem function transparent to the main CPU. In this mode, the SSI 73K222U's multiplexed pins form the serial command bus usedto communicate with
the external microprocessor. The RI, CTS, DSR, DTR, and DCD
logic functions must then be implemented using ports from the
dedicated microprocessor.

The serial control interface allows access to the control and status
registers via a serial command port. In this mode the MAO, MA1,
and MA2 lines provide register addresses for data passed through
the DATA pin under control of the RD and WR lines. A read operation is initiated when the RD line is taken low. The next eight
cycles of DCLK will then transfer out eight bits of the selected
address location LSB first. A write takes place by shifting in eight
bits of data LSB first for eight consecutive cycles of DCLK. WR is
then pulsed low and data transfer into the selected register occurs
on the rising edge of WR.

o
a.
(I)
3

SSI73K222U
Single-Chip Modem
with UART

UART CONTROL REGISTER OVERVIEW
DATA BIT NUMBER

REGISTER

UART
ADDRESS
UA3-UAO*

07

06

05

04

03

02

01

DO

RECEIVER
BUFFER
REGISTER
I (READ ONLYJ

RBR

0000
DLABzO

BIT7
(MSB)

BIT6

BIT 5

BIT4

BIT3

BIT2

BIT 1

BITO
(LSB)

TRANSMIT
HOLDING
REGISTER
('<'{RITE ONLYl

THR

0000
DLAB=O

BIT7
(MSB)

BIT6

BIT5

BIT4

BIT 3

BIT2

BIT 1

BITO
(LSB)

INTERRUPT
ENABLE
REGISTER

IER

0001
DLAB- 0

0

0

0

ENABLE
8250A!
16C450
INTERRUPT

ENABLE
MODEM
STATUS
INTERRUPT

ENABLE
REC. LINE
STATUS
INTERRUPT

ENABLE
THR
EMPTY
INTERRUPT

ENABLE
REC. DATA
AVAILABLE
INTERRUPT

INTERRUPT
10
REGISTER
(READ ONLY)

IIR

0010

0

0

0

0

0

INTERRUPT
10
BIT1

INTERRUPT
10
BITO

"0" IF
INTERRUPT
PENDING

LINE
CONTROL
REGISTER

LCR

0011

DIVISOR
LATCH
ACCESS
(DLAB)

SET
BREAK

STICK
PARITY

EVEN
PARITY
SELECT
(EPS)

PARITY
ENABLE
(PEN)

NUMBER
OF STOP
BITS
(STB)

WORD
LENGTH
SELECT 1
(WLS11

WORD
LENGTH
SELECT 0
(WLSQL

MODEM
CONTROL
REGISTER

MCR

0100

0

0

0

LOOP

ENABLE
INTERRUPT

mPRST
(OUT1IN
16C450)

REOUEST
TO SEND
(RTS)

DATA
TERMINAL
READY
(DTR)

TRANSMIT
HOLDING
REGISTER
EMPTY(THRE

BREAK
INTERRUPT
(BI)

FRAMING
ERROR
(FE)

PARITY
ERROR
(PE)

OVERRUN
ERROR
(OE)

DATA
READY
(DR)

I

IN(~~:~o)

LINE
STATUS
REGISTER

LSR

0101

0

TRANSMIT
SHIFT REG.
EMPTY
(TSRE)

MODEM
STATUS
REGISTER
(READ ONLy)

MSR

0110

DATA
CARRIER
DETECT
(DCD)

RING
INDICATOR
(RI)

DATA
SET READY
(DSR)

CLEAR
TO SEND
(CTS)

DELTA
DATA CARR.
DETECT
(DDCD)

TRAILING
EDGE RING
INDICATOR
(TERI)

DELTA
DATASET
READY
(DDSR)

DELTA
CLEAR
TO SEND
(DCTS)

SCRATCH
REGISTER

SCR

0111

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BITO

DIVISOR
LATCH
(LS)

DLL

0000
DLAB-l

BIT7

BIT6

BIT 5

BIT4

BIT3

BIT2

BIT 1

BITO

DIVISOR
LATCH
(MS)

DLM

0001
DLAB-l

BIT 15

BIT14

BIT13

BIT 12

BIT11

BIT 10

BIT9

BITS

* In single-port mode (STNDLN pin

= 1), all

four address lines UA3-UAO are used to address the UART Control Registers.

* In dual-port mode (STNDLN pin = 0), only three address lines UA2-UAO are used to address the UART Control Registers;
the UA3 pin becomes the MA2 pin in this mode.

3-87

I

SSI73K222U
Single-Chip Modem
with UART

MODEM CONTROL REGISTER OVERVIEW
ADDRESS
STNDLN
1
0

REGISTER

_MAO

UA3·
llAO

MA2·

DATA BIT NUMBER

D7

D6

D5

D4

03

02

01

DO

CONTROL
REGISTER
0

CAO

000

1000

MODULATION
OPTION

0

MODULATION
MODE

POWER
ON

CHARACTER
SIZE 1
(READ ONLY)

CHARACTER
SIZEO
(READ ONLY)

TRANSMIT
ENABLE

ORIGINATE!
ANSWER

CONTROL
REGISTER
1

CRl

001

1001

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

ENABLE
DETECT
INTERRUPT

BYPASS
SCRAMBLER

CLK
CONTROL

RESET

TEST
MODE
1

TEST
MODE
0

DETECT
REGISTER

DR

010

1010

DEVICE
SIGNATURE
1

DEVICE
SIGNATURE
0

RECEIVE
DATA

UNSCR.
MARK
DETECT

CARRIER
DETECT

ANSWER
TONE
DETECT

CALL
PROGRESS
DETECT

LONG
LOOP
DETECT

TONE
CONTROL
REGISTER

TONE

011

1011

RXDITXD
CONTROL

TRANSMIT
GUARD
TONE

TRANSMIT
ANSWER
TONE

TRANSMIT
DTMF

DTMF
3

DTMF
2

DTMF
1

GUARD!ANS~

CONTROL
REGISTER
2

CR2

100

1100

CONTROL
REGISTER
3

CR3

101

1101

SPEAKER
VOLUME
1

SPEAKER
VOLUME
0

OFF·HOOK

X

X

X

X

X

SCRATCH
REGISTER

SCR

110

1110

BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT 1

BITO

UART
CONTROL
REGISTER

UCR

111

1111

TXCLK
(READ ONLY)

X

DATA
CARRIER
DETECT (DCD)

DATA
SET
READY
(DSR)

CLEAR
TO
SEND
(CTS)

DTMFO
TONE

RESERVED FOR FUTURE USE

REQUEST
DATA
TERM. READY
TO SEND
(DTR)
(RTS)
(READ ONLY) (READ ONLY)

3-88

RING
INDICATOR
(RI)

SSI73K222U
Single-Chip Modem
with UART
UART REGISTER BIT DESCRIPTIONS

UART SECTION

RECEIVER BUFFER REGISTER (RBR) (READ ONLY)
STNDLN:
0
ADDRESS:
UA2 - UAO 000, DLAB 0

=

=

1
UA3 - UAO = 0000, DLAB = 0

This read only register contains the parallel received data with start, stop, and parity bits (if any) removed. The
high order bits for less than 8 data bits/character will be set to O.
TRANSMIT HOLDING REGISTER (THR) (WRITE ONLY)
STNDLN:
0
1
ADDRESS:
UA2 - UAO = 000, DLAB 0
UA3 - UAO = 0000, DLAB

=

=0

This write only register contains the parallel data to be transmitted. The data is sent LSB first with start, stop,
and parity bits (if any) added to the serial bit stream as the data is transferred.
INTERRUPT ENABLE REGISTER (IER)
STNDLN:
0
ADDRESS:
UA2 - UAO 001, DLAB

=

=0

UA3 - UAO

1
0001, DLAB

=

=0

This 8-bit register enables the four types of interrupts of the UART to separately activate the chip Interrupt
(INTRPT) output signal. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of the
Interrupt Enable Register. Similarly, by setting the appropriate bits of this register to a logic 1, selected
interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and the
active (high) INTRPT output fromthe chip. All other system functions operate in their normal manner, including
the setting of the Line Status and Modem Status Registers.
BIT NO.

NAME

CONDITION

DO

Received Data

1

This bit enables the Received Data Available Interrupt when set to logic 1 .

D1

Transmitter Holding
Register Empty

1

This bit enables the Transmitter Holding Register
Empty Interrupt, when set to logic 1.

D2

Receiver Line
Status Interrupt

1

This bit enables the Receiver Line Status Interrupt,
when set to logic 1.

D3

Modem Status

1

This bit enables the Modem Status Register Interrupt when set to interrupt_logic 1.

D4

8250N16450

1/0

Set for compatibility with 8250N16C450 UARTS.
Reset this bit to disable the gating of the INTRPT
interrupt line with the OISTR signal which is
needed for 8250B compatibility.

Not Used

0

05 - D7

DESCRIPTION

.-

These three bits are always logic O.

3-89

I

SSI73K222U
Single-Chip Modem
with UART
INTERRUPT 10 REGISTER (UR) (READ ONLY)
STNDLN:
0
1
ADDRESS:
UA2· UAO 010
UA3· UAO

=

UART SECTION

=0010

The IIR register gives prioritized information as to the status of interrupt conditions. When accessed, the IIR
freezes the highest priority interrupt pending and no other interrupts are acknowledged until the particular
interrupt is serviced by the CPU.
BIT NO.
DO

NAME

CONDITION

Interrupt Pending

0

This bit can be used in either a hardwired priortized
or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic 0, an interrupt
is pending and the IIR contents may be used as a
pointer to the appropriate interrupt service routine.

1

When bit 0 is a logic 1 , no interrupt is pending.

01,02

Interrupt 10 bits 0, 1

Table below

03 - 07

Not Used

0

DESCRIPTION

These two bits of the II R are used to identify the
highest priority interrupt pending as indicated in
the following table.
These five bits of the II R are always logic O.

INTERRUPT PRIORITY TABLE
02

01

DO

PRIORITY

0

0

1

-

1

1

0

1

0

0

0

TYPE

SOURCE

RESET
-

None

None

Highest

Receiver Line Status

Overrun Error,
Parity Error,
Framing Error or
Break Interrupt

Reading the Line
Status Register

0

Second

Receive Data
Available

Receive Data
Available

Reading the Rcvr.
Buffer Register

1

0

Third

Transmit Holding
Register Empty

Transmit Holding
Register Empty

Reading IIR Registe~
(if source of interrupt)
or Writing to Transmit
Holding Register

0

0

Fourth

Modem Status

Clear to Send or
Data Set Ready or
Ring Indicator or
Data Carrier Det.

Reading the Modem
Status Register

3-90

.-

SSI73K222U
Single-Chip Modem
with UART
LINE CONTROL REGISTER (LCR)
STNDLN:
0
UA2 - UAO 011
ADDRESS:

UART SECTION

1
UA3 - UAO = 0011

=

The user specifies the format of the asynchronous data communications exchange via the Line Control
Register. In addition to controlling the format, the user may retrieve the contents of the Line Control Register
for inspection. This feature simplifies system programming and eliminates the need for separate storage in
system memory of the line characteristics.
BIT NO.

NAME

CONDITION

°

00

Word Length Select

01

Word Length Select 1

DESCRIPTION
Bits DO and 01 select the number of data bits per
character as shown:
--~--.

01

00

0

0

5 bits

1

6 bits

1

0

7 bits

1

1

a bits

0
-.-

Word Length

02

Number of Stop Bits

o or 1

This bit specifies the number of stop bits in each
transmitted character. If bit 2 is a logic 0, one stop
bit is generated in the transmitted data. If bit 2 is a
logic 1 when a 5-bitword length is selected via bits
oand 1 , one-and-a-half stop bits are generated. If
bit 2 is a logic 1 when either a 6, 7, or a-bit word
length is selected, two stop bits are generated.
The receiver checks the first stop bit only, regardless of the number of stop bits selected.

03

Parity Enable

1

This bit is the Parity Enable bit. When bit 3 is a logic
1, a parity bit is generated (transmit data) or
checked (receive data) between the last data word
bit and stop bit of the serial data. (The parity bit is
used to produce an even or odd number of 1's
when the data word bits and the parity bit are
summed).

04

Even Parity Select

1 or 0

This bit is the Even Parity Select bit. When bit 3 is
a logic 1 and bit 4 is a logic 0, an odd number of
logic 1's are transmitted or checked in the data
word bits and parity bit. When bit 3 is a logic 1 and
bit 4 is a logic 1, an even number of logic 1's are
transmitted or checked.

3-91

I

SSI.73K222U
Single-Chip Modem
with UART
LINE CONTROL REGISTER (LCR) (Continued)
BIT NO.

05

UART SECTION

NAME

CONDITION

Stick Parity

1 or 0

DESCRIPTION
This bit is the Stick Parity bit. When bit 3 is a logic
1 and bit 5 is a logic 1, the parity bit is transmitted
and checked by the receiver as a logic 0 if bit 4 is
a logic 1 or as a logic 1 if bit 4 is a logic o.

05

04

0

0

Parity
-~---~---

ODD Parity

0

1

EVEN Parity

1

0

MARK Parity

1

SPACE Parity

1

06

Set Break

1

Output of modem is set to a spacing state. When
the modem is transmitting DPSK data if the Set
Break bit is held for one full character (start, data,
parity, stop) the ~reak will be extended to 2 N + 3
space bits (where N = # data bits + parity bit + 1
start + 1 stop). Any data bits generated during this
time will be ignored. See note below.

07

Divisor Latch Access
Bit (DLAB)

1

This bit is the Divisor Latch Access Bit (DLAB). It
must be set high (logic 1) to access the Divisor
Latches of the baud generator during a Read or
Write operation. It must be set low (logic 0) to
access the Receiver Buffer, the Transmitter Holding Register, or the Interrupt Enable Register.

NOTE: This feature enables the CPU to alert a terminal in a computer communications system. If the
following sequence is followed, no erroneous or extraneous characters will be transmitted because of the break.
1.

Load an all O's pad character in response to THRE.

2.

Set break in response to the next THRE.

3.

Wait for the Transmitter to be idle. (TSRE
to be restored.

= 1), and clear break when normal transmission has

During the break, the Transmitter can be used as a character timer to accurately establish the
break duration.

3-92

SSI73K222U
Single-Chip Modem
with UART
MODEM CONTROL REGISTER (MCR)
STNDLN:
0
UA2-UAO=100
ADDRESS:

UART SECTION

1
UA3 - UAO = 0100

The MCR register controls the interface with the modem. Bits 01 and DO are also available as read only bits
in the UART Control Register in the Modem Registers. In single-port mode, bits 01 and DO are available
inverted at the RTS and OTR pins.

DESCRIPTION

NAME

CONDITION

DO

OTR

1

This bit controls the Data Terminal Ready (OTR)
output. When bit 0 is set to a logic 1, the OTR
output is forced to a logic O. When bit 0 is reset to
a logic 0, the OTR output is forced to a logic 1.

01

RTS

1

This bit controls the Request to Send (RTS) output.
When bit 1 is set to a logic 1 , the RTS output is forced
to a 10gicO. When bit 1 is resetto a 10gicO, the RTS
output is forced to a logic 1.

02

mPRST*
(OUT1 in 16C450)

1

In single-port mode inactive unless loop = 1,
then functions as below (04). In dual-port mode
the mPRST pin is the logical OR of this bit and the
RESET pin.

03

Enable Interrupt
(OUT2 in 16C450)

0

Sets INTRPT
STNOLN = 1.

1

INTRPT output enabled.

LOOP

1

This bit provides a local loop back feature for diagnostic testing of the UART portion of the
SSI 73K222U. When bit 04 is set to logic 1, the
following occurs:

BIT NO.

04

05 - 07

pin

to

high

impedance

1.

TXO is forced to mark, RXO is ignored.

2.

The output of the Transmitter is looped to the
Receiver.

3.

The four modem control inputs to the UART
(CTS, OSR, OCO, and AI) are ignored and the
UART signals RTS, OTR, Enable Interrupt, and
mPRST are forced inactive.

4.

The UART signals RTS, OTR, Enable Interrupt, and mPRST are internally connected to
the four control signals CTS, OSR, OCO and
RI respectively. Note that the Modem Status
Register Interrupts are now controlled by the
lower fou r bits of the Modem Control Register.
The interrupts are still controlled by the Interrupt Enable Register.

These bits are permanently set to logic O.

0

• Note: The mPRST bit has an upgraded function which was not included in the initial definition of the SSI 73K222U.
3-93

if
..-

I

SSI73K222U
Single-Chip Modem
with UART
LINE STATUS REGISTER (LSR)
STNDLN:
0
ADDRESS:
UA2·UAO=101

UART SECTION

1
UA3· UAO = 0101

This register provides status information to the CPU concerning the data transfer.

NAME

CONDITION

DO

DR

1

The Data Ready (DR) bit is set to a 1 whenever a
complete incoming character has been received
and transferred into the Receiver Buffer Register.
Data Ready is reset to 0 by reading the data in the
Receiver Buffer Register or by writing a 0 into it
from the processor.

01

OE

1

The Overrun Error (OE) bit indicates that the data
in the Receiver Buffer Registerwas not read by the
CPU before the next character was transferred into
the Receiver Buffer Register, thereby destroying
the previous character. The OE indicator is reset
whenever the CPU reads the contents of the Line
Status Register.

02

PE

1

The Parity Error (PE) bit indicates that the received
character did not have the correct parity. The bit is
reset to Owheneverthe CPU reads the Line Status
Register.

03

FE

1

The Framing Error (FE) bit indicates that the received character did not have a valid stop bit. The
FE indicator is reset whenever the CPU reads the
contents of the Line Status Register. A framing
error will not occur in OPSK receive from the
modem due to the fact that missing stop bits are
reinserted.

04

BI

1

The Break Interrupt (BI) bit indicates that a break
has been received. A break occurs whenever the
received data is held to 0 for a full data word (start
+ data + stop) or for two full data words when
receiving in OPSK mode from the modem. The BI
bit is reset to 0 whenever the CPU reads the Line
Status Register.

05

THRE

1

The Transmit Holding Register Empty (THRE)
indicates that the Transmitter is ready to accept a
new character for transmission. The THRE bit is
reset when the CPU loads a character into the
Transmit Holding Register.

06

TSRE

1

The Transmit Shift Empty (TSRE) indicates that
both the Transmit Holding Register and the Transmit Shift Registers are empty .

07

-

0

Always zero.

BIT NO.

DESCRIPTION

....

3-94

_-_._-------

SSI73K222U
Single-Chip Modem
with UART
MODEM STATUS REGISTER (MSR) (READ ONLY)
STNDLN:
0
1
ADDRESS:
UA2 • UAO 110
UA3 • UAO

=

UART SECTION

=0110

This register provides the current state of the control signals from the modem. In addition, four bits provide
change information. The CTS, DSR, DCD, and RI signals come from the UART Control Register if
STNDLN = and from the CTS, DSR, DCD and RI pins (inverted) if STNDLN = 1. This register is READ ONLY.
The delta bits indicate whether the inputs have changed since the last time the Modem Status Register has
been read. In Loop Mode CTS, DSR, RI and DCD are taken from RTS, DTR, mPRST, and Enable Interrupt
in the Modem Control Register respectively.

°

BIT NO.

NAME

CONDITION

DO

DCTS

1

This bit is the Delta Clear to Send (DCTS) indicator. Bit indicates that the CTS input to the chip
has changed state since the last time itwas read by
the CPU.

01

DDSR

1

This bit is the Delta Data Set Ready (DDSR)
indicator. Bit 1 indicates that the DSR input to the
chip has changed state since the last time it was
read by the CPU.

02

TERI

1

This bit is the Trailing Edge of the Ring Indicator
(TERI) detector. Bit 2 indicates that the RI input to
the chip has changed state.

03

DDCD

1

This bit is the Delta Data Carrier Detect (DDCD)
indicator. Bit 3 indicates that the DCD input to the
chip has changed state.

04

CTS

1

This bit is the complement of the Clear To Send
(CTS) input. If STNDLN = 0, this reflects the status
of the UART Control Register bit. If bit 4 (loop) of
the MCR is set to a 1 , this bit is equivalent to RTS
in the MCR.

05

DSR

1

This bit is the complement of the Data Set Ready
(DSR) input. If STNDLN = 0, this reflects the status
of the UARTControl Registerbit. If bit40fthe MCR
is set to a 1, this bit is the equivalent of DTR in the
MCR.

06

RI

1

This bit is the complement of the Ring Indicator (RI)
input. If STNDLN = 0, this reflects the status of the
UART Control Register bit. If bit 4 of the MCR is set
to a 1, this bit is equivalent to mPRST in the MCR.

07

DCD

1

This bit is the complement of the Data Carrier
Detect (DCD) If STNDLN '" 0, this reflects the
status of the UART Control Register bit. If bit 4 of
the MCR is setto a 1, this bit is equivalentto Enable
Interrupt in the MCR.

DESCRIPTION

°

---

3-95

I

SSI73K222U
Single-Chip Modem
with UART
SCRATCH REGISTER (SCR)
STNDLN:
0
ADDRESS:
UA2 • UAO

UART SECTION

1
UA3 • UAO = 0111

=111

The Scratch Register is a dual port register which can be simultaneously accessed through both the UART
bus and the modem bus.This provides the possibility for the modem controller to communicate directly with
the central CPU. Note that if both processors write the Scratch Register, the data stored will be from whichever
processor last wrote the register.

DIVISOR LATCH (Least significant byte) (DLL)
STNDLN:
0
ADDRESS:
UA2 • UAO 000, DLAB 1

UA3 • UAO

=0000, DLAB =1

DIVISOR LATCH (Most significant byte) (DLM)
STNDLN:
0
ADDRESS:
UA2· UAO = 001, DLAB = 1

UA3 • UAO

=0001, DLAB =1

=

1

=

1

DIVISOR LATCH VALUE VS. DATA RATE
The Divisor Latch is two 8-bit write only registers which control the rate of the programmable baud generator.
The programmable baud generator generates an output clock by dividing an internal 1.8432 MHz clock by the
value stored in the divisor latch. This output clock has a value of 16X the data rate at which the modem will
operate. This output clock is available at pin 21 under the control of bit 3 (D3) of the Modem Control Register 1.
Upon loading either of the Divisor Latches the 16-bit device counter is immediately loaded, preventing long
counts on initial load. The following table shows divisor values for common data rates.

DESIRED
DATA RATE

DIVISOR USED
FOR 16x DATA
RATE CLOCK

% ERROR
DESIRED
GENERATED DATA RATE

DIVISOR USED
FOR 16 x DATA
RATE CLOCK

50

1

2304

4800

24

75

1

1536

7200

16

1047

9600

12

~---

110 1

% ERROR
GENERATED

-------~~--

----

--

-

1

134.5

857

0.058

19200

6
---..

--------~

159

1

768

38400

3

300

1

384

56000

2

600

2

192

1.

Data Rate valid for FSK transmission.

96

2.

Data Rate valid for halfspeed DPSK trans mission.

3.

Data Rate valid for normal 1200 BIT/S DPSK
transmission.

1200

3

1800

64

2000

58

2400

48

3600

32

0.69

3-96

2.86

SSI73K222U
Single-Chip Modem
with UART
MODEM REGISTER BIT DESCRIPTIONS
CONTROL REGISTER (CRO)
STNDLN:
0
ADDRESS:
MA2· MAO
BIT NO.
DO

01

1
UA3· UAO

=000

MODEM SECTION

=1000

NAME

CONDITION

Answer/Originate

0

Selects Answer Mode (transmit in high band, receive in low band).

1

Selects Originate Mode (transmit in low band,
receive in high band).

Transmit Enable

DESCRIPTION

0

Disables transmit output at TXA.

1

Enables transmit output at TXA.

--

NOTE: Answer tone and DTMF TX control require
Transmit Enable. If Transmit Enable is on, call
progress and answer tone detector interrupts are
masked.
02, 03

04

Character Size 0, 1

These bits are read only. These bits represent the
character size. The character size is determined
by the UART Line Control Register and includes
data, parity (if used), one start bit, and one stop bit.
03

02

0

0

8-bit character

Character length

0

1

9-bit character

1

0

1O-bit characte r

1

1

11-bit character

-----

Power ON

This bit controls the power down mode of the
SSI 73K222U, the analog, and most digital portions of the chip. The digital interface is active
during power down.

---------------

0

Power down mode.

1

Normal operation.

05

Modulation Mode

0

DPSK

1

FSK

06

Reserved

0

Must be written as zero.

07

Modulation Option

0

DPSK: 1200 biUs

----

600 biUs

1
FSK:

0
1

103 mode
V.21 mode

3-97

---- __ ----0

---- -

I

SSI73K222U
Single-Chip Modem
with UART
CONTROL REGISTER (CR1)
STNDLN:
0
MA2 • MAO
ADDRESS:
BIT NO.

DO, 01

D2

NAME
Test Mode

Reset

1
UA3· UAO

=001

CONDITION

MODEM SECTION

=1001
DESCRIPTION

D1

DO

0

0

Selects normal operating mode.

0

1

Analog loopback Mode. loops the transmitted
analog signal back to the receiver, and causes the
receiver to use the same center frequency as the
Transmitter. To squelch the TXA pin, transmit
enable bit must be forced low.

1

0

Selects remote digitalloopback. Received data is
looped back to transmit data internally, and RXD is
forced to a mark. Data in TXD is ignored.

1

1

Selects half-duplex. Internally performs a logical
AND of TXD and RXD to send to the UART
receiver. Both transmit and receive characters will
occur at the Receiver Buffer Register.

0

Selects normal operation.

1

Resets modem to power down state. All Control
Register bits (CRO, CR1, TONE) are reset to zero.
The output of the clock pin will be set to the crystal
frequency.

0

ClK pin output is selected to be an 11.0592 MHz
crystal echo output.

1

ClK pin output is selected to be 16 x the Data Rate
set by the UART divisor latch.

0

Selects normal operation. DPSK data is passed
through scrambler.

1

Selects Scrambler Bypass. DPSK data is routed
around scrambler in the transmit path.

--

D3

D4

ClK Control
(Clock Control)

Bypass Scrambler

3-98

SSI73K222U
Single-Chip Modem
with UART
CONTROL REGISTER (CR1) (Continued)
BIT NO.

05

06,07

MODEM SECTION

NAME

CONDITION

Enable Detect
Interrupt

0

Disables interrupts generated by Detect Register
bits D1 - D4 at INT pin in dual-port mode, or at
INTRPT pin in single-port mode. All interrupts
normally disabled in power down modes.

1

Enables interrupts generated by Detect Register
bits D1 - D4 at INT pin in dual-port mode, or at
INTRPT pin in single-port mode. An interrupt will
be generated with a change in status of DR bits
D1 - D4. The answer tone and call progress detect
interrupts are masked when the TX enable bit is
set. Carrier detect is masked when TX DTMF is
activated. All interrupts will be disabled if the
device is in power down mode. The interrupt is
reset when the DR register is read.

Transmit Pattern

DESCRIPTION

07

06

0

0

Selects normal data transmission as controlled by
the state of the TXD pin.

0

1

Selects an alternating mark/space transmit pattern
for modem testing.

1

0

Selects a constant mark transmit pattern.

1

1

Selects a constant space transmit pattern.

3-99

I

SSI73K222U
Single-Chip Modem
with UART
DETECT REGISTER (DR)
STNDLN:
ADDRESS:
MA2 - MAO

o

1
UA3 - UAO

=010

MODEM SECTION

=1010

NAME

CONDITION

DO

Long Loop

0
1

Indicates low received signal level « -38 dBm).

D1

Call Progress Detect

0

No call progress tone detected.

1

Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy
in the normal 350 to 620 Hz call progress bandwidth.

0

No answer tone detected.

1

Indicates detection of 2225 Hz answer tone in Bell
mode or21 00 Hz in CCITT mode. The device must
be in Originate Mode for detection of answer tone
for normal operation. For CCITT answer tone
detection, bit DO of the Tone Register must be set.

BIT NO.

DESCRIPTION

Indicates normal received signal.

--

D2

Answer Tone Received

D3

Carrier Oetect

0

No carrier detected in the receive channel.

1

Carrier has been detected in the receive channel.

D4

Unscrambled Marks

0

No unscrambled mark detected.

1

Indicates detection of unscrambled marks in the
received data. A valid indication requires that
unscrambled marks be received for > 165.5 ±
13.5 ms.

D5

Continuously outputs the received data stream.
This data is the same as that output on the RXD
pin, but it is not disabled when RXD is tri-stated.

Receive Data

----

06,07

Product Identified

07

06

0

0

SSI 73K212U (special order only)

0

1

SSI 73K221 U (special order only)

1

0

SSI73K222U

-~

Device Signature 0,1

3-100

SSI73K222U
Single-Chip Modem
with UART
TONE CONTROL REGISTER (TONE)
STNDLN:
0
ADDRESS:
MA2 - MAO = 011

MODEM SECTION

1
UA3 - UAO = 1011

The Tone Control Register contains information on the tones that are transmitted. Tones are transmitted only
if the Transmit Enable bit is set. The priority of the transmit tones are: 1) DTMF, 2) Answer, 3) FSK,
4) Guard.
BIT NO.
DO

NAME
DTMF 0 / Answer/
Guard Tone

DO, D1,
D2,D3

DTMF

CONDITION

DESCRIPTION

D6 D5 D4 DO

DO interacts with bits 06, 05, and 04 as shown:

X

X

1

X

Transmit DTMF tones.

X

1

0

0

Select 2225 Hz answer tone (Bell).

X

1

0

1

Select 2100 Hz answer tone (CCITT).

1

0

0

0

Select 1800 Hz guard tone.

1

0

0

1

Select 550 Hz guard tone.

Table below

Programs 1 of 16 DTM F tone pairs that will be
transmitted when TX DTMF and TX enable bit
(CRO, bit D1) is set. Tone encoding is shown
below.

KEYBOARD
EQUIVALENT

3-101

--

OTMF CODE
D3 D2 D1 DO

TONES
LOW
HIGH

1

0

0

0

1

697

2

0

0

1

0

697

1336

3

0

0

1

1

697

1477

4

0

1

0

0

770

1209

5

0

1

0

1

770

1336

0

770

1477

1

1

----

1209

6

0

7

0

1

1

1

852

1209

8

1

0

0

0

852

1336

9

1

0

0

1

852

1477

0

1

0

1

0

941

1336

*

1

0

1

1

941

1209

#

1

1

0

0

941

1477

A

1

1

0

1

697

1633

B

1

1

1

0

770

1633

C

1

1

1

1

852

1633

D

0

0

0

0

941

1633

I

SSI73K222U
Single-Chip Modem
with UART
TONE CONTROL REGISTER (TONE) (Continued)
D4

D5

D6

D7

TX DTMF

0

Disable DTMF.

(Transmit DTM F)

1

Activates DTMF. The selected DTMF tones are
transmitted continuously when this bit is high. TX
DTMF overrides all other transmit functions.

TXANS

D5

DO

D5 interacts with bit DO as shown.

(Transmit Answer Tone)

0

X

Disables answer tone generator.

1

0

Enables answer tone generator. A 2225 Hz answer tone will be transmitted continuously when
the transmit enable bit is set. The device must be
in answer mode.

1

1

Enables a 2100Hz answer tone generator, with
operation same as above.

TX Guard

0

Disables guard tone generator.

(Transmit Guard Tone)

1

Enables guard tone generator. (See DO for selection of guard tones).

RXD/TXD Control

CONTROL REGISTER (CR3)
STNDLN:
0
ADDRESS:
MA2· MAO
BIT NO.

NAME

DO - 04

Not Used

D5

Off Hook

D6,D7

MODEM SECTION

D7

Function is dependant on status of STNDLN pin.

0

0

RXD is output data received by modem, TXD is
serial output of UART.

1

0

RXD is electrically an input, but the signal is
ignored, TXD is forced to a mark.

X

1

RXD is serial input to UART, TXD is serial output
of UART.

STNDLN

1
UA3· UAO = 1101

=101

Speaker Volume 0, 1

CONDITION

DESCRIPTION
Not presently used.

0

Relay driver open.

1

Open drain driver pulling low.

D7

D6

0

0

Speaker volume control status.
---

Speaker off
---~----

0

1

-24 dB

1

0

-12 dB

1

1

OdB

3-102

--------------

SSI73K222U
Single-Chip Modem
with UART
SCRATCH REGISTER (SCR)
STNDLN:
0
ADDRESS:
MA2· MAO = 110

MODEM SECTION

1
UA3· UAO = 1110

The Scratch Register is a dual-port register which can be accessed either through the UART bus orthe modem
bus. It can be used for a communication path outside the data stream.
UART CONTROL REGISTER (UCR)
STNDLN:
0
ADDRESS:
MA2· MAO = 111

1
UA3· UAO

=1111

The UART Control Register contains the handshaking signals necessary for the microprocessor to communicate with the central CPU through the UART.
BIT NO.

NAME

CONDITION

CTS

1

01

OSR

1

02

OCO

1

03

RI

1

04

OTR

1

05

RTS

1

06

Not Used

07

TXCLK

00

DESCRIPTION
In dual-port mode, CTS, OSR, OCO and RI are
writeable locations which can be read through the
16C450 port in the Modem Status Register.

In the single-port mode, 00 - 03 are ignored and
the information for the Modem Status Register
comes directly from the external pins.

OTR and RTS are read only versions of the
same register bits in the Modem Contol Register.
---

Clock

TXCLK is the clock that the UART puts out with
TXO. The falling edge of TXCLK is coincident with
the transitions of data on TXO. TXCLK can also be
used for the microprocessor to send synchronous
data independent of the UART by forcing data
patterns using CR1 bits 6 and 7 before the rising
edge of TXCLK.

NOTE: Control Register 2 (CR2) is reserved for future products and is disabled.

3-103

I

SSI73K222U
Single-Chip Modem
with UART
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
TA = -40°C to 85°C, VDD = 5V ± 10%, unless otherwise noted.
PARAMETER

UNIT

RATING

VDD Supply Voltage

7

V

Storage Temperature

-65 to 150

°C

260

°C

-0.3 to VDD +0.3

V

Soldering Temperature (10 sec.)
Applied Voltage

NOTE: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
CONDITIONS

MIN

NOM

MAX

UNIT

VDD, Supply Voltage

4.5

5

5.5

V

TA, Operating Free-Air
Temperature

-40

85

°C

PARAMETERS

--

-~

External Component (Refer to application drawing for placement.)
VREF Bypass Capacitor 2

(VREF to GND)

0.1

/J- F

--

Bias Setting Resistor

(Placed between VDD
and ISET pins)

1.8

ISET Bypass Capacitor 2

ISET pin to GND

0.1

/J- F

VDD Bypass Capacitor 2

(VDDto GND)

0.1

/J- F

1

2

2.2

MO

----_.

XTL 1 Load Capacitor

From pin to GND

40

pF

XTL2 Load Capacitor

From pin to GND

20

pF

Input Clock Variation

- -

(11.0592 MHz)

-0.01

+0.01

%

--------

Hybrid Loading
R1

See Figure 3

R2
C

TXA Hybrid Loading

600

0

600

0

0.033

-

1. Optional for minimum worst case current consumption.
2. Minimum for optimized system layout; may require higher values for noisy environments.

3-104

/J- F

---------'---~~

SSI73K222U
Single-Chip Modem
with UART
DC ELECTRICAL CHARACTERISTICS
TA = -40°C to +85 °C, VDD = 5V ± 10%, unless otherwise noted.
PARAMETERS

CONDITIONS

MIN

NOM

MAX

UNIT

100, Supply Current
IDDA, Active

ISET Resistor = 2MQ

8

12

rnA

IDDA, Active

ISET = GND

8

15

mA

1001, Power-Down

ClK = 11.0592MHz

3

4

rnA

1002, Power-Down

ClK = 19.200KHz

2

3

rnA

100

J.lA
J.lA

0.8

V

-~

Digital Inputs
--~.-

Input High Current

IIH

VI = VDD

Input low Current

III

VI = 0

Input low Voltage

Vil

Input High Voltage

VIH

Except RESET & XTl1

2.0

Input High Voltage

VIH

RESET & XTl1

3.0

Pull Down Current

._--_._-

-200

5

RESET PIN

._--_..

V
V

-_._._--

--

Input Capacitance

--

30

J.lA

10

pF

Digital Outputs
Output High Voltage

VOH

lOUT = -1 rnA

2.4

-_ .._-

-

VDD

V
V

VOL UDO-UD7 and INTRPT

lOUT = 3.2 mA

0.4

VOL other outputs

lOUT = 1.6 rnA

0.4

V

lOUT = 3.2 rnA

0.6

V

ClK Output

VOL

OH Output

VOL

lOUT = 20 rnA

OH Output

VOL

lOUT = 10 rnA

Offstate Current INTRPT pin

----

-20

VO= OV

1.0

V

0.5

V

-~

20

-----_._--

---

J.lA

Capacitance
Inputs

Input Capacitance

ClK

Maximum capacitive load to pin

--I ~~

Analog Pins

pF

I

pF

-_. .

kQ

200

RXA Input Resistance

25

RXA Input Capacitance

3-105

pF

I

SSI73K222U
Single-Chip Modem
with UART
DYNAMIC CHARACTERISTICS AND TIMING
TA =-40°C to +85°C, VDD = 5V ± 10%, unless otherwise noted.
PARAMETERS

CONDITIONS

MIN

NOM

MAX

UNIT

DPSK Modulator
Carrier Suppression

Measured at TXA

55

Output Amplitude

ANS TONE 2225 or 2100 Hz

-11

-10.0

-9

dBmO,

DPSK TX Scrambled Marks

-11

-10.0

-9
---

dBmO

FSK Dotting Pattern

-11

-10.0

-9

dBmO

±5

Hz

FSK Tone Error

dB

.

Bell 103 or V.21

DTMF Generator
Freq. Accuracy

-.25

.25

%

Output Amplitude

Low Band, not in V.21 mode

-10

-9

-8

dBmO

Output Amplitude

High Band, not in V.21 mode

-8

-7

-6

dBmO

Long Loop Detect

DPSK or FSK

-40

-32

dBmO

Demodulator
Dynamic Range

DPSK or FSK

-~

45

Call Progress Detector

- -

Detect Level

2~Tones

Reject Level

2-Tones in 350-600 Hz Band

Delay Time

-70dBmO to -30 dBmO Step

27

Hold Time

-30dBmO to -70 dBmO Step

27

in 350-600 Hz Band

-39
---_._---

0

dBmO

-46

dBmO

80

ms

80

ms
dB

2

Hysteresis

Carrier Detect

dB

DPSK or FSK Receive

Threshold

Data

-49

-42

dBmO

Delay Time

-70 dBmO to -30 dBmO Step

15

45

ms

-30 dBmO to -70 dBmO Step

10

24

ms

-42

dBmO

2

Hysteresis
Hold Time

Answer Tone Detector

- ----

3.0

dB
--- --- -

-49.5

Detect Level Threshold

In FSK mode

Delay Time

-70 dBmO to -30 dBmO STEP

20

45

ms

Hold Time

-30 dBmO to -70 dBmO STEP

10

30

ms

+2.5

%

-2.5

Detect Frequency Range

---

1. All units in dBmO are measured at the line input to the transformer. The interface circuit inserts an 8 dB
loss in the transmit path (TXA1 - TXA2 to line), and a 3dB loss in the receive path (line to RXA).

3-106

SSI73K222U
Single-Chip Modem
with UART
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS

CONDITIONS

MIN

NOM

MAX

UNIT

Speaker Output
-1

Gain Error
Output Swing SPKR

10KII50 pF LOAD 5% THD

----

2.75

-..

f~~

dB
VP

--~-

CarrlerVCO
Capture Range

Originate or Answer

Capture Time

-10Hz to +10 Hz Carrier
Frequency change assumed

-10

10

Hz

100

ms

+625

ppm

30

50

ms

40

Recovered Clock
Capture Range

% of Center Frequency

Data Delay Time

Analog data in at RXA pin to
receive data valid at RXD pin.

-625

Guard Tone Generator
Tone Accuracy

550 or 1800 Hz

-20

+20

Hz

Tone Level

550 HZ

-4.0

-3.0

-2.0

dB

(Below DPSK Output)

1800 HZ

-7.0

-6.0

-5.0

dB

Harmonic Distortion

700 to 2900 HZ

-60

dB

MAX

UNIT

SERIAL BUS INTERFACE (See Figure 4)
The following times are for CL = 100 pF.
MIN

PARAMETER
TRD

Data out from Read

NOM

0

TCKD

Data out after Clock

TRDF

Data Float after Read

0

TRCK

Clock High after Read

200

TWW

Write Width

140

TOCK

Data Setup Before Clock

150

..

TCKH

Data Hold after Clock

20

TCKW

Write after Clock

150

TACR

Address setup before Control

1

50 - -

_------

140

ns

200

ns

200

ns
ns

10000

ns

_....-

ns

------ ---------- --------

ns
~.

~

..

TCAR

Address Hold after Control

TACW

Address setup before Write

50

TCAW

Address Hold after Write

50

ns
ns

50

1

ns

-----~-

1. Control is later of falling edge of RD or DCLK.

3-107

ns

-------

ns

----~----

--

•

SSI73K222U
Single-Chip Modem
with UART
PARALLEL BUS INTERFACE (See Figure 5) The following times are for CI
PARAMETER

MIN

MAX

Dual-Port Mode
RC

Read Cycle

= TAD + TRC

= 100 pF.
MIN

UNIT

Single-PortMode
340

240

MAX

ns

- 1-----

TDIW

DISTR Width

TODD

Delay DISTR to Data (read time)

THZ**

DISTR to Floating Data Delay

TRA

Address Hold after DISTR

20

20

ns

TRCS

Chip select hold after DISTR

20

20

ns

TAR*

DISTR Delay after Address

20

20

ns

TCSR

DISTR Delay after Chip Select

20

20

140

140

ns

ns

80

80
80
0

= TAW + TDOW + TWC

50

0

- -

80

ns

50

ns

---

ns

WC

Write Cycle

TDOW

DOSTR Width

80

80

ns

TDS

Data Setup

30

50

ns

TDH**

Data Hold

20

20

ns

TWA

Address Hold after DOSTR

20

20

20

20

TWCS

Chip select hold after DOSTR

TAW*

DOSTR delay after Address

20

20

TCSW

DOSTR delay after Chip Select

20

20

- ---- --_.
-------------

ns
ns
ns
ns

TADS

Address Strobe Width

40

ns

TAS

Address Setup Time

30

ns

TAH

Address Hold Time

TCS

Chip Select Setup Time

30

ns

TCH

Chip Select Hold Time

0

ns

0

--

--

ns

TRC

Read Cycle Delay

40

40

ns

TWC

Write Cycle Delay

40

40

ns

TAD

Address to Read Data

200

300

ns

*

TAR and TAW are referenced from the falling edge of eitherCS20rDISTRorDOSTR, which everis later.

**

THZ and TDH are referenced from the rising edge of CS2 or DISTR or DOSTR, which ever is earlier.

3-108

SSI73K222U
Single-Chip Modem
with UART

TXA1

R1

RXA < E - - - - - - l

c
TXA2

>.----'

110

1:1

6000
R2
(Nominal Telephone
Line Impedance)

TA Hybrid Loading
Analog Interface Hybrid Loading

FIGURE 3: TXA Hybrid Loading Analog Interface Hybrid Loading

READ MODE
DCLK

ADDRESS

DATA

WRITE MODE
DCLK

ADDRESS

DATA

FIGURE 4: Modern Serial Bus Timing
3-109

I

SSI73K222U
Single-Chip Modem
with UART

ADS
(STNDLN=1)

ADDRESS
UA2 (UA3)-UAO

DATA
UD7-UDO

FIGURE 5: UART Bus Timing

3-110

SSI73K222U
Single-Chip Modem
with UART
TYPICAL PERFORMANCE CHARACTERISTICS
The SSI 73K222U was designed using an integrated
analogldigital architecture that offers optimum performance over a wide range of line conditions. The
SSI 73K222U utilizes the circuit design proven in
SSl's 73K222L one-chip modem, with added enhancements which extend low signal level performance and increase immunity to spurious noise typically encountered in integral bus applications. The
SSI 73K222U provides excellent immunity to the types
of disturbances present with usage of the dial-up
telephone network. The following curves show representative Bit Error Rate performance under various
line conditions.

BER vs. SIN
This test measures the ability of the modem to function
with minimum errors when operating over noisy lines.
Since some noise is generated by even the best dialup lines, the modem must operate with as Iowa SIN
ratio as possible. Optimum performance is shown by
curves that are closest to the zero axis. A narrow
spread between curves for the four line conditions
indicates minimal variation in performance when operating over a range of line qualities and is typical of high
performance adaptive equalization receivers. High
band receive data is typically better than low band due
to the inherent design of PSK modems.

SSI73K222U
BER vs RECEIVE LEVEL

SSI73K222U
BER vs SIN

I HIGH
BAND RECEIVE ~
DPSK OPERATION

RECEIVE~

1--+-+-+-+-+-"\'+-"1,

~

HIGH BAND
·40 dBm
DPSK OPERATION

I

C2l1NE

1..--1-.
10.3

L.U
~

c(

\

\

a:
a:
0 10-4
a:
a:

\

L.U

I:::
CD

~\I\

\ l\

\

SIN = 10.8 dB

\

10.5

1I

\

'1\ ,
S/N-15dB

\' \
4

6

10

12

14

10

SIGNAL TO NOISE (dB)

-10

·20

·30

RECEIVE LEVEL (dBm)

3-111

·40

·50

I

SSI73K222U
Single-Chip Modem
with UART
BER vs. Receive Level
SSI73K222U
BER vs CARRIER OFFSET

This measures the dynamic range of the modem. As
signal levels vary widely over dial-up lines, the widest
dynamic range possible is desirable. The minimum
Bell specification calls for 36dB of dynamic range.
SIN ratios were held constant at the indicated values
while receive level was lowered from very high to very
low signal levels. The ''width of the bowl" of these
curves taken at the 10· BER point is a measure of the
dynamic range.

I HIGH BAND RECEIVE

I

DPSK OPERATION

f--

10-3

L.LI

!;t

a:

!5a:

BER vs. Carrier Offset

10-4

a:
L.LI

t::

J 3002 11.5 dB SIN

CD

This parameter indicates how the modem performance
is impacted by frequency shifts encountered in normal
PSTN operation. Flat curves show no performance
degradation from frequency offsets. The SSI K-Series
devices use a 2nd order carrier tracking phase-Iockedloop, which is insensitive to carrier offsets in excess of
10Hz. The Bell network specifications allow as much
as 7Hz offset, and the CCITT specifications require modems to operate with 7Hz of offset.

I

10-5

\

C2 10.8 dB SIN

~

-- - -'C -- i--- .-J.

12

I

1\

...-

~
f-""

~

-4

-8

-12

SIGNAL TO NOISE (dB)

APPLICATION
The SSI73K222U includes additional circuitry to greatly
simplify integral modem designs in either of two different configurations. The single-port mode represents
the most efficient implementation for an integral modem. Figure 9 shows a typical schematic using this
mode. In this configuration, the SSI 73K222U transfers data and commands through the single parallel
port. All modem control is provided by the main CPU,
eliminating the need for an external microcontroller
and supporting components. The SSI 73K222U is
unique in that access to both the UART and modem
sections is possible through the UART port. Also
shown is a separate serial port, which can be used
independent of the modem function when the modem

section is inactive. Figure 10 shows a more conventional integral modem deSign, in which a local microprocessor handles modem supervision, allowing the
modem function to be transparent to the main processor. Inclusion of the hybrid drivers, audio volume
control, and off hook relay driver reduces component
count for a highly efficient design. In either mode of
operation, the SSI 73K222U's ability to operate from a
single +5 volt power supply eliminates the need for
additional supply voltages and keeps power usage to
a minimum.
(See Figure 9 & 10: Typical Integral Applications
Single and Dual-Port Modes.)

3-112

U2

~B~
IRO

+5

~~

VOO

C4

I

51

C13~

~

=
C2~24
18pF

INTRPT GNO I
ISET

20

I 9
+5

XTL1

Xl

STNOALN

_15_ _ _~

t-I

XTL2

39

UAO

TXO

7

Al AJO

38

UAl

RXO

6

A2 A29

37

UA2

AO AJl

12

UAJ

23

_
ADS

AJ A28

+5

0.1 ~F

OPTIONAL
DIGITAL
SERIAL PORT

v'

A4 A27
A5 A26
CS2

A6 A25
A7 A24
A8 A23
A9 A22

SSI
73K222U

Ri~

~
W

1N4004
AENAll

--~

R7
22K

lOW 913

OOSTR

lOR 914

DISTR

08 A9
01

A8

UOO
28

02 A7

UOl

R5

U02

Fuseablc

03 A6

30

U03

D4 A5

311

U04

HI

LINE

MOVI
V250LA20A

05 A4

en
::::J

06 A3
07 A2
:

C9

Rs

.111

Fus0ablc

SPKR~f-

1<>

(Q
(I)

len
°en

==~­

RESET

::::;:"'C .......
::Ts:W
FIGURE 9: 73K222U Typical Integral Application Single-Port Mode

CO"
»0.1\)
:c(l)~
~3c

U2

PCBU5

A7

U1

3

+5

:S~~

VDD

J3
IAOO

COM 21NT

IA04 B24

COM liNT

C4
0.1 ~F

C'3~

~

+S>I

16pF

=

;:::;::::1_
::::r CC .......

C6

, .F

XTLI

C:iDw

8053

STNDALN~

XI

C2~

AO A31

VDD

PS:~

XTL2

_
g

10

I AXD

11

TXD

-------

A2 A29

ALE

r;-

»1"

N/C

.... 0 1 \ )
oN::::r1\)
I\)

+S>I

-I _.

N/C

"'Cc:

s:

SI

lPI.O

, ..

2

_

4

Pl.3

__

5

PI.4

M A27

o
a.

P1.1

P3.7

(t)

3

61

Pl.7
- .•- - - - - - - 7 PI.6
A6 A25

MAO

~4

I

eLK

Kd-

551

T

19

NIC

I XI

161 X2

"I~

A7

221<

,----

73K222U

LS04

~

6! PI.5

21

I

"PAST

.::...6_ _ _ _ _ _ _ _-l

1-1

I"

AEN

11

./>.

iOW
i5R

61:'\

36j
:::..j...-----------;;;135~
~------------------~

B14

"I

08 A

-I

27

'I

03 A6

I

I

30'

_I

31

04 A-

D5M

I

-I

07 A2

UDO

AS

'n

UDI

26

29
-+.__________----i

02 AI

DOSTR
DISTR

1

Fuseablc

UD2

U03

UD4

321

UD5

::

~:

MOV1

V250lA20A

TXA2

I 4

SPKA

~:F~351K r.
2nrF
~ f-.>:;-~~f-!

"F'

.5

1

/'

U4
LS'-)4

U5

3

MIDCOM

R9i

4

SPKA

rr -1. . J

'"F
"R4
7.,
.047.>.
.
6". '.

. 1~ ~o

[~on

III
AS

Fusc.bI •.

LM3Uf,

.OOI~_.,f "n.

C12

RESET 82

LINE
~A

6718005
I
I

I'

!

C6 !

[rl

_I

\j

FIGURE 10: 73K222U Typical Integral Application Dual-Port Mode

SSI73K222U
Single-Chip Modem
with UART
PACKAGE PIN DESIGNATIONS

CAUTION:

Use handling procedures necessary
for a static sensitive component.

(Top View)
VDD

Parentheses indicate single-port mode.
UAO
UA1

TXA1

UA2
INTRPT
6

INTRPT

7

RXD

8

TXD

5

43

UD6
ISET

UDS

42

41

DOSTR

0

UD7

DISTR

9

37

UD7

(R) IIl-PRST

10

36

UD6

11

35

UD5

33

RESET

UD4

ISET

(DCD)/DCLK

UD3

RESET

(UA3)/MA2

UD2

(DeD) I DCLK

13

(DSR)/MA1

UD1

(UA3)/MA2

14

UD2

UDO

(DSR)/MA1

15

(CTS)/MAO

UD1

UD4

(CTS)/MAO
STNDLN

UD3

UDO

WR/(N/C)

STNDLN
RXA

29
18

XTl1

19

20

21

22

24

25

26

..: 10
f..: Ie:

f-

23

27

28

-'

-'

x

x

I~

N/C

-l:l

SPKR

..:

XTl2

~

RD/(ADS)

cr:

fi: 16

Ul

I~

0

z

(!j

~

u

0

i?
f-

DATAl (DTR)

VREF

Iii)

N

f-

I~

Q.

ClK

GND

44-Pin
PLCC

600-Mil
40-Pin DIP

ORDERING INFORMATION
PKG.MARK

ORDER NO.

PART DESCRIPTION
SSI73K222U
40-Pin Plastic Dual-In-Line

73K222U-IP

44-Pin Plastic Leaded Chip Carrier

73K222U-IH

--

73K222U-IP
73K222U-IH

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.

Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX (714) 573-6914

1293 - rev.

3-115

©1989 Silicon Systems, Inc.

I

Notes:

3-116

SSI73K224L
V.22bis/V.22/V.21 ,
Bell 212A/1 03
Single-Chip Modem
January 1994

DESCRIPTION

FEATURES

The SSI 73K224L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a V.22bis compatible modem, capable of
2400 biVs full-duplex operation over dial-up lines. The
SSI 73K224L offers excellent performance and a high
level of functional integration in a single 28-pin DIP.
This device supports V.22bis, V.22, V.21, Bell 212A
and Bell 103 modes of operation, allowing both synchronous and asynchronous communication.The
SSI73K224L is designed to appear to the systems
designer as a microprocessor peripheral, and will easily interface with popular single-chip microprocessors
(80C51 typical) for control of modem functions through
its 8-bit multiplexed address/data bus or via an optional
serial control bus. An ALE control line simplifies address demultiplexing. Data communications normally
occur through a separate serial port. The SSI 73K224L
is pin and software compatible with the SSI 73K212L
and SSI 73K222L single-chip modem ICs, allowing
system upgrades with a single component change.

One-chip mUlti-mode V.22bisN.22N.21 and
Bell 212A11 03 compatible modem data pump
FSK (300 bit/s), OPSK (600, 1200 bitls), or QAM
(2400 bitls) encoding
Pin and software compatible with other
551 K-Series 1-chip modems
Interfaces directly with standard microprocessors
(8048, 80C51 typical)
Parallel microprocessor bus for control with a
wide range of package options
Selectable asynch/synch with internal bufferl
debuffer and scrambler/descrambler functions
All synchronous and asynchronous operating
modes (internal, external, slave)
Adaptive equalization for optimum performance
over all lines
Programmable transmit attenuation (16 dB, 1 dB
steps), selectable receive boost (+18 dB)
Call progress, carrier, answer tone, unscrambled
mark, 51, and signal quality monitors
OTMF, answer and guard tone generators

The SSI 73K224L operates from a single +5 V supply
for low power consumption.

Test modes available: ALB, OL, ROL, Mark, Space,
Alternating bit, 51 pattern
CMOS technology for low power consumption
(typically 100 mW @ 5V) with power-down mode
(15 mW@5V)
TTL and CMOS compatible inputs and outputs

The SSI73K224L is ideal foruse in either free-standing
or integral system modem products where full-duplex
(Continued)

BLOCK DIAGRAM

8-BIT
mp
BUS

UF

I
I

:AGC
I
I:

I
I
IL ____________________________ II

'ITON-ED~ET-Ec-TION-,I

0194 - rev.

3-117

GAIN BOOST

I

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
DESCRIPTION (Continued)
2400 bitls data communications over the 2-wire
switched telephone network is desired. Its high functionality, low power consu mption, and efficient packaging simplify design requirements and increase system
reliability.
The SSI73K224L is designed to be a complete V.22bis
compatible modem on a chip. The complete modem
requires only the addition of the phone line interface, a
control microprocessor, and RS-232 level converterfor
a typical system. Many functions were included to
simplify implementation of typical modem designs. In
addition to the basic 2400 bitls QAM, 600/1200 bitls
DPSK and 300 bit/s FSK modulatorldemodulator sections, the device also includes SYNCH/ASYNCH
converters, scramblerldescrambler, call progress tone
detect, DTMF tone generator capabilities and handshake pattern detectors. V.22bis, V.22, V.21 and Bell
212A1103 modes are supported (synchronous and
asynchronous) and test modes are provided for diagnostics. Most functions are selectable as options and
logical defaults are provided.

OPERATION

Demodulation is the reverse of the modulation process, with the incoming analog signal eventually
decoded into di-bits and converted back to a serial bit
stream. The demodulator also recovers the clock
which was encoded into the analog signal during
modulation.Demodulation occurs using either a
1200 Hz carrier (answer mode or ALB originate mode)
or a 2400 Hz carrier (originate mode or ALB answer
mode). Adaptive equalization is also used in DPSK
modes for optimum operation with varying line
conditions.
FSK MODULATOR/DEMODULATOR

The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. The Bell 103 standard frequencies of 1270 and 1070 Hz (originate mark and
space) and 2225 and 2025 Hz (answer mark and space)
are used when this mode is selected. V.21 mode uses
980 and 1180 Hz (originate, mark and space) or 1650
and 1850 Hz (answer, mark and space). Demodulation
involves detecting the received frequencies and decoding them into the appropriate binary value. The rate
converter and scramblerldescrambler are automatically
bypassed in the FSK modes.
PASSBAND FILTERS AND EQUALIZERS

QAM MODULATOR/DEMODULATOR

The SSI 73K224L encodes incoming data into quadbits represented by 16 possible signal points with
specific phase and amplitude levels. The baseband
signal is then filtered to reduce intersymbol interference on the bandlimited telephone network. The
modulator transmits this encoded data using either a
1200 Hz (originate mode) or 2400 Hz (answer mode)
carrier. The demodulator, although more complex,
essentially reverses this procedure while also recovering the data clock from the incoming signal. Adaptive
equalization corrects for varying line conditions by
automatically changing filter parameters to compensate for line characteristics.
DPSK MODULATOR/DEMODULATOR

The SSI 73K224L modulates a serial bit stream into
di-bit pairs that are represented by four possible phase
shifts as prescribed by the Bell 212A1V.22 standards.
The base-band signal is then filtered to reduce intersymbol interference on the bandlimited 2-wire PSTN
line. Transmission occurs on either a 1200 Hz (originate mode) or 2400 Hz carrier (answer mode).

High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay equalization and rejection of out-of-band signals. Amplitude
and phase equalization are necessary to compensate
for distortion of the transmission line and to reduce
intersymbol interference in the band limited receive
signal. The transmit signal filtering corresponds to a
75% square root of raised Cosine frequency response
characteristic.
ASYNCHRONOUS MODE

The Asynchronous mode is used for communication
with asynchronous terminals which may communicate
at 600,1200, or 2400 biVs + 1%, -2.5% even though the
modem's output is limited to the nominal bit rate ±.01 %
in DPSK and QAM modes. When transmitting in this
mode the serial data on the TXD input is passed
through a rate converter which inserts or deletes stop
bits in the serial bit stream in order to output a signal
that is the nominal bit rate ±.01%. This signal is then
routed to a data scrambler and into the analog modulator where quad-biVdi-bit encoding results in the out-

3-118

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
put signal. Both the rate converter and scrambler can
be bypassed for handshaking, and synchronous operation as selected. Received data is processed in
a similar fashion except that the rate converter now
acts to reinsert any deleted stop bits and output data to
the terminal at no greater than the bit rate plus 1%. An
incoming break signal (low through two characters) will
be passed through without incorrectly inserting a stop
bit.
The SYNC/ASYNC converter also has an extended
Overspeed mode which allows selection of an output
overspeed range of either +1% or +2.3%. In the extended Overspeed mode, stop bits are output at 7/8 the
normal width.
Both the SYNC/ASYNC rate converter and the data
descrambler are automatically bypassed in the FSK
modes.
SYNCHRONOUS MODE

Synchronous operation is possible only in the QAM or
DPSK modes. Operation is similar to that of the Asynchronous mode except that data must be synchronized
to a provided clock and no variation in data transfer rate
is allowable. Serial input data appearing at TXD must
be valid on the rising edge of TXCLK.
TXCLK is an internally derived 1200 or 2400 Hz signal
in Internal mode and is connected internally to the
RXCLK pin in Slave mode. Receive data at the RXD pin
is clocked out on the falling edge of RXCLK. The
asynchlsynch converter is bypassed when Synchronous mode is selected and data is transmitted at the
same rate as it is input.

PARALLEL BUS INTERFACE

Eight 8-bit registers are provided for control, option
select, and status monitoring. These registers are
addressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as seven consecutive memorylocations. Six control registers are readlwrite memory. The
detect and 10 registers are read only and cannot be
modified except by modem response to monitored
parameters.
SERIAL CONTROL INTERFACE

The serial Command mode allows access to the
SSI 73K324 control and status registers via a serial
control port. In this mode the AO, A1, and A2 lines
provide register addresses for data passed through the
DATA pin under control of the RD and WR lines. A read
operation is initiated when the RD line istaken low. The
next eight cycles of EXCLK will then transfer out eight
bits of the selected addresss location LSB first. A write
takes place by shifting in eight bits of data LSB first for
eight consectuive cycles of EXCLK. WR is then pulsed
low and data transfer into the selected register occurs
on the rising edge of WR.
DTMF GENERATOR

The DTMF generator controls the sending of the sixteen standard DTMF tone pairs. The tone pair sent is
determined by selecting TRANSMIT DTMF (bit 04)
and the 4 DTMF bits (00-03) of the TONE register.
Transmission of DTMF tones from TXA is gated by the
TRANSMIT ENABLE bit of CRO (bit 01) as with all
other analog signals.

3-119

I

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
PIN DESCRIPTION
POWER
NAME

TYPE

DESCRIPTION

GND

I

System Ground.

VDD

I

Power supply input, 5V -5% +10%. Bypass with .22 IlF and 22 IlF capacitors
to GND.

VREF

a

An internally generated reference voltage. Bypass with .22 IlF capacitor to
GND.

ISET

I

Chip current reference. Sets bias current for op-amps. The chip current is set
by connecting this pin to VDD through a 2 MQ resistor. Iset should be bypassed
to GND with a .22 IlF capacitor.

PARALLEL MICROPROCESSOR INTERFACE
ALE

I

Address latch enable. The falling edge of ALE latches the address on ADOAD2 and the chip select on CS.

ADOAD7

Address/data bus.These bidirectional tri-state multi-plexed lines carry information to and from the internal registers.

CS

I/O /
Tristate
I

ClK

a

Output clock. This pin is selectable under processor control to be either the
crystal frequency (for use as a processor clock) or 16 x the data rate for use
as a baud rate clock in QAM/DPSK modes only. The pin defaults to the crystal
frequency on reset.

INT

0

Interrupt. This open drain weak pullup, output signal is used to inform the
processor that a detect flag has occurred. The processor must then read the
detect register to determine which detect triggered the interrupt. INT will stay
active until the processor reads the detect register or does a full reset.

RD

I

Read. A low requests a read of the SSI 73K224l internal registers. Data
cannot be output unless both RD and the latched CS are active or low.

RESET

I

Reset. An active high signal on this pin will put the chip into an inactive state.
All control register bits (CRO, CR1, CR2, CR3, Tone) will be reset. The output
of the ClK pin will be set to the crystal frequency. An internal pu II down resistor
permits power on reset using a capacitor to VDD.

WR

I

Write. A low on this informs the SSI73K224l that data is available on ADO-AD7
for writing into an internal register. Data is latched on the rising edge of WR.
No data is written unless both WR and the latched CS are active (low).

Chip select. A low on this pin allows a read cycle or a write cycle to occur. ADOAD7 will not be driven and no registers will be written if CS (latched) is not
active. CS is latched on the falling edge of ALE.

Note: The serial control mode is provided in the parallel versions by tying ALE high and CS low. In this
configuration AD7 becomes DATA and ADO, AD1 and AD2 become AD, A1 and A2, respectively.

3-120

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
DTE USER INTERFACE
NAME

TYPE

EXCLK

I

External Clock. This signal is used in synchronous transmission when the
external timing option has been selected. In the external timing mode the rising
edge of EXCLK is used to strobe synchronous transmit data available on the
TXD pin. Also used for serial control interface.

RXCLK

OfTristate

Receive Clock. Tri-stateable. The falling edge of this clock output is coincident
with the transitions in the serial received data output. The rising edge of
RXCLK can be used to latch QAM or DPSK valid output data. RXCLK will be
active as long as a carrier is present.

0

Received Digital Data Output. Serial receive data is available on this pin. The
data is always valid on the rising edge of RXCLK when in synchronous mode.
RXD will output constant marks if no carrier is detected.

OfTristate

Transmit Clock. Tri-stateable. This signal is used in synchronous transmission
to latch serial input data on the TXD pin. Data must be provided so that valid
data is available on the rising edge of the TXCLK. The transmit clock is derived
from different sources depending upon the synchronization mode selection. In
Internal Mode the clock is generated internally. In External Mode TXCLK is
phase locked to the EXCLK pin. In Slave Mode TXCLK is phase locked to the
RXCLK pin. TXCLK is always active.

I

Transmit Digital Data Input. Serial data for transmission is input on this pin. In
synchronous modes, the data must be valid on the rising edge of the TXCLK
clock. In asynchronous modes (2400/1200/600 bitls or 300 baud) no clocking
is necessary. DPSK data must be +1%, -2.5% or +2.3%, -2.5 % in extended
overspeed mode.

RXD

TXCLK

TXD

DESCRIPTION

ANALOG INTERFACE AND OSCILLATOR
RXA

I

TXA

0

Transmit analog output to the phone line.

Received modulated analog signal input from the phone line.

XTL1
XTL2

I
I/O

These pins are for the internal crystal oscillator requiring a 11.0592 MHz
parallel mode crystal. Two capacitors from these pins to ground are also
required for proper crystal operation. Consult crystal manufacturer for proper
values. XTL2 can also be driven from an external clock.

3-121

I

SSI73K224L
V.22bis/V.22/V.21 , Bell 212A/1 03
Single-Chip Modem
PIN DESCRIPTION (continued)
SERIAL MICROPROCESSOR INTERFACE
NAME

TYPE

DESCRIPTION

AO-A2

I

Register Address Selection. These lines carry register addresses and should
be valid during any read or write operation.

DATA

I/O

Serial Control Data. Data for a read/write operation is clocked in or out on the
falling edge of the EXCLK pin. The direction of data flow is controlled by the
RD pin. RD low outputs data. RD high inputs data.

RD

I

Read. A low on this input informs the SSI 73K322L that data or status
information is being read by the processor. The falling edge of the RD signal
will initiate a read from the addresses register. The RD signal must continue
for eight falling edges of EXCLK in order to read all eight bits of the referenced
register. Read data is provided LSB first. Data will not be output unless the RD
signal is active.

WR

I

Wrne. A low on this input informs the SSI73K322L that data or status information
has been shifted in through the DATA pin and is available for writing to an internal
register. The normal procedure for a wrne is to shift in data LSB first on the DATA
pin for eight consecutive falling edges of EXCLK and then to pulse WR low. Data
is wrnlen on the rising edge of WR.

Note: In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the pins;
AO, A1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.

3-122

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
REGISTER DESCRIPTIONS
Eight 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AO, A1 and
A2 address lines in serial mode, or the ADO, AD1 and
AD2 lines in parallel mode. The address lines are
latched by ALE. Register CRO controls the method by
which data is transferred over the phone line. CR1
controls the interface between the microprocessor and

the SSI73K224L internal state. DR is a detect register
which provides an indication of monitored modem
status conditions. TR, the tone control register, controls the DTM F generator, answer and guard tones and
RXD output gate used in the modem initial connect
sequence. CR2 is the primary DSP control interface
and CR3 controls transmit attenuation and receive
gain adjustments. All registers are read/write except
forDR and IDwhich are read only. Register control and
status bits are identified below:

REGISTER BIT SUMMARY

CONTROL
REGISTER
0
CONTROL
REGISTER
1

CRO

CR1

000

MODULAllON
OPllON

MODULAllON
TYPE
1

TRANSMIT
MODE
2

MODULAllON
TYPE
0

001

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

ENABLE
DETECT
INTERRUPT

BYPASS
SCRAMBLER

TRANSMIT
MODE

TRANSMIT
MODE
0

TRANSMIT
ENABLE

ANSWER!
ORIGINATE

TEST
MODE
0

CLK
CONTROL

RESET

TEST
MODE

DETECT
REGISTER

DR

010

RECEIVE
LEVEL

PATTERN
S1DET

RECEIVE
DATA

UNSCR.
MARK
DETECT

CARRIER
DETECT

SPECIAL
TONE
DETECT

CALL
PROGRESS
DETECT

SIGNAL
aUALITY

TONE
CONTROL
REGISTER

TR

011

RXD
OUTPUT
CONTROL

TRANSMIT
GUARD
TONE

TRANSMIT
ANSWER
TONE

TRANSMIT
DTMF

DTMF3

DTMF2

DTMF1!
EXTENDED
OVERSPEED

DTMFO/GUARDI
ANSWER

CONTROL
REGISTER
2

CR2

100

TRANSMIT
S1

16 WAY

RESET
DSP

TRAIN
INHIBIT

EQUALIZER
ENABLE

CR3

101

TRANSMIT
ATTEN.
2

TRANSMIT
ATTEN.

3

TRANSMIT
ATTEN.
0

TXD
SOURCE

sa
SELECT 1

sa
SELECT 0

CONTROL
REGISTER

TRANSMIT
ATTEN.

3
SPECIAL
REGISTER

SR

101

TX BAUD
CLOCK

10

110

10

10
REGISTER

NOTE:

10

When a register containing reserved control
bits is written into, the reserved bits must be
programmed as O's.

3-123

I

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
REGISTER ADDRESS TABLE

ggg~:~~~~

OAM:
DPSK:

0=2400 BITIS
0=1200 BITIS
1=600BITIS
FSK: 0=103 MODE
1=V.21

----------'

0010=EXTSYNCH
001hSLAVE SYNCH
0100=ASYCH 8 BITs/CHAR
0101=ASYCH 9 BITs/CHAR
0110=ASYCH 10 BITs/CHAR
011hASYCH 11 BITs/CHAR
1XOO=FSK

0=1800 Hz G.T.
2225 Hz ANS TONE
GENERATED.
1=550 HzG.T.
2100 Hz ANS TONE
GENERATED &
DETECTED (V.21, V.22)

O=ACCESS CR3
,=ACCESS
SPECIAL
REGISTER

O=DSP IN
O=NORMAL
DEMOD MODE
DOTTING
hS1
,=DSP IN CALL
PROGRESS
MODE

00XX=73K212L, 322L, 321 L
01 XX=73K221 L, 302L
10XX=73K222L
1100=73K224L
1110=73K324L
1101=73K312L

3-124

O=RX=TX
,=RX='6 WAY

O=DSP
INACTIVE
1=DSP
ACTIVE

O=ADAPTEO
ACTIVE
hADAPT EO
FROZEN

O=ADAPTEO
IN INIT
1=ADAPTEO
OK TO ADAPT

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
CONTROL REGISTER 0

CRO
000

07

06

05

MOOUL.
OPTION

MOOUL.
TYPE 1

MOOUL.
TYPE 0

BIT NO.
00

01

NAME

04

Transmit
Enable

02

01

DO

TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/
MODE 2
ENABLE ORIGINATE
MODE 1
MOOEO

CONDITION

Answer/
Originate

03

DESCRIPTION

0

Selects answer mode (transmit in high band, receive
in low band).

1

Selects originate mode (transmit in lowband,receive in
high band).

0

Disables transmit output at TXA.

1

Enables transmit output at TXA.
Note: Transmit Enable must be set to 1 to allow
activation of Answer Tone or OTMF.

05 04 03 02
05,04,
03,02

Transmit
Mode

0

0

0

0

Selects power down mode. All functions disabled
except digital interface.

0

0

0

1

Internal synchronous mode. In this mode TXCLK is an
internally derived 600,1200 or 2400 Hz signal. Serial
input data appearing at TXO must be valid on the rising
edge of TXCLK. Receive data is clocked out of RXO on
the falling edge of RXCLK.

0

0

1

0

External synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 600, 1200 or 2400 Hz clock
must be supplied externally.

0

0

1

1

Slave synchronous mode. Same operation as other
synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.

0

1

0

0

Selects asynchronous mode - 8 bits/character (1 start
bit, 6 data bits, 1 stop bit).

0

1

0

1

Selects asynchronous mode - 9 bits/character (1 start
bit, 7 data bits, 1 stop bit).

0

1

1

0

Selects asynchronous mode -10 bits/character (1 start
bit, 8 data bits, 1 stop bit).

0

1

1

1

Selects asynchronous mode -11 bits/character (1 start
bit, 8 data bits, Parity and/or 1 or 2 stop bits).

1

X

0

0

Selects FSK operation.

--

---------------~

06 05
06,05

Modulation
Type

1

0

QAM

0

0

OPSK

0

1

FSK
3-125

I

SSI73K224L
V.22bis/V.22/V.21 , Bell 212A/1 03
Single-Chip Modem
CONTROL REGISTER 0
D7
CRO
000

D6

MODUL.
OPTION

D4

D5

MODUL.
TYPE 1

D2

D3

D1

DO

MODUL. TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/
ENABLE ORIGINATE
TYPE 0
MODE2
MODE 1
MODE 0

NAME

BIT NO.
D7

(Continued)

CONDITION

Modulation
Option

DESCRIPTION

0

QAM selects 2400 bit/so DPSK selects 1200 bit/so
FSK selects 103 mode.

1

DPSK selects 600 biVs.
FSK selects V.21 mode.

CONTROL REGISTER 1

CR1
001
BIT NO.

D7

D6

05

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

ENABLE
DETECT
INT.

NAME

CONDITION

D4

02

01

DO

RESET

TEST
MODE
1

TEST
MODE
0

03

BYPASS
ClK
SCRAMB CONTROL

DESCRIPTION

D1 DO
D1, DO

Test Mode

0

0

Selects normal operating mode.

0

1

Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same carrier frequency as the transmitter. To
squelch the TXA pin, TRANSMIT ENABLE bit as well
as Tone Reg bit D2 must be low.

1

0

Selects remote digital loopback. Received data is
looped back to transmit data internally, and RXD is
forced to a mark. Data on TXD is ignored.

1

1

Selects local digital loopback. Internally loops TXD
back to RXD and continues to transmit data camier at
TXA pin.

---

D2

D3

Reset

Clock Control

--------------

0

Selects normal operation.

1

Resets modem to power down state. All cont rol register
bits (CRO, CR1, CR2, CR3 and Tone) are reset to zero
except CR3 bit D2. The output of the clock pin will be
set to the crystal frequency.

0

Selects 11.0592 MHz crystal echo output at ClK pin.

1

Selects 16 X the data rate, output at ClK pin in DPSK/
QAM modes only.

3-126

SSI73K224L
V.22bis/V.22/V.21 , Bell 212A/1 03
Single-Chip Modem
CONTROL REGISTER 1

CR1
001

D4

D7

D6

D5

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

ENABLE
DETECT
INT.

BIT NO.
D4

D5

(Continued)

D3

BYPASS
ClK
SCRAMB CONTROL

D2

D1

DO

RESET

TEST
MODE
1

TEST
MODE
0

NAME

CONDITION

Bypass
Scrambler

0

Selects normal operation. DPSK and QAM data is passed
through scrambler.

1

Selects Scrambler Bypass. Bypass DPSK and QAM
data is routed around scrambler in the transmit path.

0

Disables interrupt at INT pin. All interrupts are normally
disabled in power down mode.

1

Enables INT output. An interrupt will be generated with
a change in status of DR bits D1-D4 and D6. The
answer tone and call progress detect interrupts are
masked when the TX enable bit is set. Carrier detect is
masked when TX DTMF is activated. All interrupts will
be disabled if the device is in power down mode.

Enable Detect
Interrupt

DESCRIPTION

D7 D6
D7,D6

Transmit
Pattern

0

0

Selects normal data transmission as controlled by the
state of the TXD pin.

0

1

Selects an alternating mark/space transmit pattern for
modem testing and handshaking. Also used for S1
pattern generation. See CR2 ~it D4.

1

0

Selects a constant mark transmit pattern.

1

1

Selects a constant space transmit pattern.

-~

DETECT REGISTER
D7
DR
010

RECEIVE
S1
lEVEL
PATTERN
INDICATOR DETECT

BIT NO.
DO

01

D6

NAME

D5

D4

D3

RECEIVE
DATA

UNSCR.
MARK
DETECT

CARR.
DETECT

CONDITION

D2

D1

DO

SIGNAL
ANSWER
CAll
QUALITY
PROG.
TONE
DETECT DETECT INDICATOR

DESCRIPTION

Signal Quality
Indicator

0

Indicates normal received signal.

1

Indicates low received signal quality (above average
error rate). Interacts with special register bits 02, D1.

Call Progress
Detect

0

No call progress tone detected.

1

Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in
the normal 350 to 620 Hz call progress bandwidth.
3-127

I

SSI73K224L
V.22bis/V.22/V.21 , Bell 212A/1 03
Single-Chip Modem
DETECT REGISTER (Continued)
07
DR
010

03

02

01

DO

CARR.
DETECT

ANSWER
TONE
DETECT

CALL
PROG.

SIGNAL
QUALITY
INDICATOR

NAME

CONDITION
0

No answer tone detected.

1

In Call Init mode, indicates detection of 2225 Hz
answer tone in Bell mode (TR bit 00=0) or 2100 Hz if
in CCID mode (TR bit 00=1). The device must be in
originate mode for detection of answer tone. Both
answer tones are detected in demod mode.

Carrier
Detect

0

No carrier detected in the receive channel.

1

Indicated carrier has been detected in the received
channel.

Unscrambled
Mark
Detect

0

No unscrambled mark.

1

Indicates detection of unscrambled marks in the
received data. Should be time qualified by software.

03

04

04
UNSCR.
MARK
DETECT

Answer Tone
Received

BIT NO.
02

05
RECEIVE
DATA

06

RECEIVE
S1
PADERN
LEVEL
INDICATOR DETECT

DESCRIPTION

05

Receive
Data

06

S1 Pattern
Detect

0

No S1 pattern being received.

1

S1 pattern detected. Should be time qualified by software. 81 pattern isdefined as adoubledi-bit (0011 00 .. )
unscrambled 1200 biVs DPSK signal. Pattern must be
aligned with baud clock to be detected.

Receive Level
Indicator

0

Received signal level below threshold, (typical", -25
dBmO); can use receive gain boost (+18 dB).

1

Received signal above threshold.

07

Continuously outputs the received data stream. This
data is the same as that output on the RXD pin, but it
is not disabled when RXD is tri-stated.

TONE REGISTER

TR
011

07

06

RXD
OUTPUT
CONTR.

TRANSMIT
GUARD
TONE

BIT NO.

NAME

05

04

TRANSMIT TRANSMIT
ANSWER
DTMF
TONE

CONDITION
06 05 04 DO

DO

(Continued)

DTMF 01
Answerl
Guard Tone

03

02

DTMF3

DTMF2

01

DO

DTMF 11
DTMF 01
EXTENDED ANSWERI
GUARD
OVERSPEED

DESCRIPTION
DO interacts with bits 06, 05, and 04 as shown.

X

X

1

X

Transmit DTMF tones.

X

1

0

0

Select Bell mode answer tone. Interacts with DR bit 02
and TR bit 05.

X

1

0

1

Select CCID mode answer tone. Interacts with DR bit
02 and TR bit 05.
3-128

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
TONE REGISTER (Continued)

TR
011

07

06

RXO
OUTPUT
CONTR.

TRANSMIT
GUARO
TONE

BIT NO.
00

05

NAME

CONDITION

OTMF 01
Answerl
Guard Tone

06 05 04 00

02

OTMF3 OTMF 21
4WIRE
FOX

01

00

DTMF 11
OTMF 01
EXTENDED ANSWERI
OVERGUARO
SPEED

DESCRIPTION
00 interacts with bits 06, 05, --and 04 as shown.

0

0

0

Select 1800 Hz guard tone.

0

0

1

Select 550 Hz guard tone.

04 01
OTMF 11
Extended
Overspeed

03

~~

1
1

01

04

TRANSMIT TRANSMIT
OTMF
ANSWER
TONE

01 interacts with 04 as shown.

0

0

Asynchronous QAM or OPSK +1.0% -2.5%. (normal)

0

1

Asynchronous QAM or OPSK +2.3% -2.5%. (extended
overspeed)

04 02
02

OTMF 21
4WIRE
FOX

0

0

Selects 2 wire duplex or half duplex

0

1

02 selects 4 wire full duplex in the modulation mode
selected. The receive path corresponds to the ANSI
ORIG bit CRO 00 in terms of high or low band selection.
The transmitter is in the same band as the receiver, but
does not have magnitude filtering or equalization on its
signal as in the receive path.

3-129

I

SSI73K224L
V.22bi s/V.22/V. 21 , Bell 212A/1 03
Single-Chip Modem
TONE REGISTER (Continued)

TR
011

D7

D6

RXD
OUTPUT
CONTR.

TRANSMIT
GUARD
TONE

BIT NO.

NAME

D3, D2,
D1,DO

DTMF 3,
2,1,0

D5

D4

D3

TRANSMIT TRANSMIT
ANSWER
DTMF
TONE

CONDITION

D2

D1

DO

DTMF 11
DTMF 0/
EXTENDED ANSWER/
OVERGUARD
SPEED

DTMF3 DTMF 2/
4WIRE
FDX

DESCRIPTION

D3 D2 D1 DO
0
1

0
1

0
1

o1

Programs 1 of 16 DTMF tone pairs that will be
transmittedwhenTX DTMF andTXenablebit (CRO, bit
D1) is set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT

D4

TX DTMF
(Transmit
DTMF)

DTMF CODE
D3 D2 D1 DO

TONES
LOW HIGH

1

0

0

0

1

697

1209

2

0

0

1

0

697

1336

3

0

0

1

1

697

1477

4

0

1

0

0

770

1209

5

0

1

0

1

770

1336

6

0

1

1

0

770

1477

7

0

1

1

1

852

1209

8

1

0

0

0

852

1336

9

1

0

0

1

852

1477

0

1

0

1

0

941

1336

*

1

0

1

1

941

1209

#

1

1

0

0

941

1477

A

1

1

0

1

697

1633

---

B

1

1

1

0----

770

1633

C

1

1

1

1

852

1633

D

0

0

0

0

941

1633

---------

..

-

0

Disable DTMF.

1

Activate DTMF. The selected DTMF tones are transmitted continuously when this bit is high. TX DTMF
overrides a" other transmit functions.

Note: DTM FO - DTM F2 should be set to an appropriate state after DTM F dialing to avoid unintended operation.

3-130

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
TONE REGISTER

(Continued)

D7

D6

D5

TR
011

RXD
OUTPUT
CONTR.

TRANSMIT
GUARD
TONE

BIT NO.

NAME

D4

TRANSMIT TRANSMIT
ANSWER
DTMF
TONE

CONDITION

Transmit
Answer Tone

D6

D7

D1

DTMF3 DTMF 21
4WIRE
FDX

DO
DTMF 1/
DTMF 01
EXTENDED ANSWERI
OVERGUARD
SPEED

DESCRIPTION

D5 04 DO

D5

D2

D3

D5 interacts with bits D4 and DO as shown. Also
interacts with DR bit D2 in originate mode. See Detect
Register description.

0

0

X

Disables answer tone generator.

1

0

0

In answer mode, a Bell 2225 Hz tone is transmitted
continuously when the Trans~~. Enable bit is set.

1

0

1

Likewise, a CCID 21 00 Hz answer tone is transmitted.

Transmit
Guard Tone

0

Disables guard tone generator:.

1

Enables guard tone generator. (See DO for selection of
guard tones.) Bit D4 must be zero.

RXD Output
Control

0

Enables RXD pin. Receive data will be output on RXD.

1

Disables RXD pin. The RXD pin reverts to a high
impedance with internal weak pull-up resistor.

CONTROL REGISTER 2

CR2
100

BIT NO.

D7

D6

D5

D4

0

SPEC
REG
ACCESS

CALL
INIT

TRANSMIT
S1

D3

D2

D1

DO

16WAY

RESET
DSP

TRAIN
INHIBIT

EQUALIZER
ENABLE

NAME

CONDITION

Equalizer
Enable

0

The adaptive equalizer is in.its initialized state.

1

The adaptive equalizer is enabled. This bit is used in
handshakes to control when the equalizer should calculate its coefficients.
_.-

D1

Train
Inhibit

0

The adaptive equalizer is active.

1

The adaptive equalizer coefficients are frozen.

D2

RESET DSP

0

The DSP is inactive and all variables are initialized.

1

The DSP is running based on the mode set by other
control bits

0

The receiver and transmitter are using the same decision plane (based on the Modulator Control Mode).

1

The receiver, independent of the transmitter, is forced
into a 16 point decision plane. Used for QAM handshaking.

DO

D3

16 Way

DESCRIPTION

_.-

3-131

I

SSI73K224L
V.22bis/V.22/V.21 , Bell 212A/1 03
Single-Chip Modem
CONTROL REGISTER 2 (Continued)

CR2
100
BIT NO.
04

07

06

05

04

0

SPEC
REG
ACCESS

CALL
INIT

TRANSMIT
S1

NAME

CONDITION

Transmit
S1

0

Callinit

0

1
06

Special
Register
Access

0
1

07

Not used at this time

0

02

01

DO

16WAY

RESET
OSP

TRAIN
INHIBIT

EQUALIZER
ENABLE

DESCRIPTION
The transmitter when placed in alternating mark/space
. mode transmits 0101 ...... scrambled or not dependent
on the bypass scrambler bit.
When this bit is 1 and only when the transmitter is placed
in alternating mark/space mode by CR1 bits 07, 06, and
in OPSK or QAM, an unscrambled repetitive double dibit
pattern of 00 and 11 at 1200 biVs (?1) is sent.
The OSP is setup to do demodulation and pattern
detection based on the various mode bits. Both answer
tones are detected in demod mode concurrently; TRDO is ignored.
The OSP decodes unscrambled mark, answer tone
and call ~rogress tones.
Normal CR3 access.
Setting this bit and addressing CR3 allows access to
the SPECIAL REGISTER. See the SPECIAL REGISTER for details.
---Only write zero to this bit.

1

05

03

CONTROL REGISTER 3
CR3
101

03,02,
01,00

Transmit
Attenuator

o

0

0

0-

Sets the attenuation level of the transmitted Signal
in 1dB steps. The default (03-00=0100) is for a transmit level of -10 dBmO on the line with the recommended hybrid transmit gain. The total range is 16 dB.

04
Receive
Gain Boost

Boost is in the path. This boost does not change
reference levels. It is used to extend dynamic range by
compensating for internally generated noise when
receiving weak signals. The receive level detect signal
and knowledge of the hybrid and transmit attenuator
will determine when boost should be enabled.

3-132

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
SPECIAL REGISTER

06
SR
101

05

03

02

01

RXUNOSCR
DATA

TXO
SOURCE

SIGNAL
QUALITY
LEVEL
SELECT1

SIGNAL
QUALITY
LEVEL
SELECTO

06

TXBAUO ClK

TXBAUO clock is the transmit baud-synchronous clock that can be used to
synchronize the input of arbitrary quad/di-bit patterns. The rising edge of
TXBAUO signals the latching of a baud-worth of data internally. Synchronous
data to be entered via the TXOAlT bit, CR3 bit D7, should have data
transitions that start 1/2 bit period delayed from the TXBAUO clock edges.

05

RXUNOSCR
DATA

This bit outputs the data received before going to the descrambler. This is
useful for sending special unscrambled patterns that can be used for
signaling.

03

TXO SOURCE

This bit selects the transmit data source; either the TXO pin if ZERO or the
TXOAlT ifthis bit isa ONE. The TRANSMIT PATTERN bits D7 and D6 in CR1
override either of these sources.

SIGNAL
OUALITY
lEVEL
SELECT

The signal quality indicator is a logical ZERO when the signal received is
acceptable for low error rate reception. It is determined by the value of the
Mean Squared Error (MSE) calculated in the decisioning process when
compared to a given threshold. This threshold can be set to four levels of error
rate. The SOl bit will be lowforgood or average connections. As the error rate
crosses the threshold setting, the SOl bit will toggle at a 1.66 ms rate. Toggling
will continue until the error rate indicates that the data pump has lost
convergence and a retrain is required. At that point the SOl bit will be a ONE
constantly. The SOl bit and threshold selection are valid for OAM and
OPSK only and indicates typical error rate.

02,01

NOTE: This register is "mapped" and is accessed by setting CR2 bit 06 to a ONE and addressing CR3. This
register provides functions to the 73K224l user that are not necessary in normal communications.
Bits 07-04 are read only, while 03-DO are read/write. To return to normal CR3 access, CR2 bit D6
must be returned to a ZERO.

3-133

I

SSI73K224L
V.22bis/V.22/V.21 , Bell 212A/1 03
Single-Chip Modem
ID REGISTER

10
110

07

06

05

04

10

10
2

10
1

10
0

3

BIT NO.

NAME

07,06,

Oevice
Identification
Signature

05, 04

CONDITION

DESCRIPTION

ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER

RATING

VOO Supply Voltage

7V

Storage Temperature

-65 to 150°C

Soldering Temperature (10 sec.)

260°C

Applied Voltage

-0.3 to VDD+0.3V

Note: A" inputs and outputs are protected from static charge using built-in, industry standard protection
devices and a" outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
PARAMETER

CONDITIONS

VDD Supply voltage

MIN

NOM

MAX

UNITS

4.5

5

5.5

V

-

-

External Components (Refer to Application section for placement.)
VREF Bypass capacitor

(VREF to GNO)

0.22

Bias setting resistor

(Placed between VDO and ISET pins)

ISET Bypass capacitor

(ISET pin to GNO)

0.22

j.!F

VOO Bypass capacitor 1

(VOOto GNO)

0.22

j.!F

VOO Bypass capacitor 2

(VOOto GNO)

22

XTL 1 Load Capacitance

Depends on crystal requirements

XTL2 Load Capacitance
Clock Variation

1.8

j.!F

TA, Operating Free-Air
Temperature
3-134

2.2

MQ

j.!F
18

39

pF

27

pF

-0.01

+0.01

%

-40

85

°C

18

Depends on crystal requirements
(11.0592 MHz) Crystal or external clock

2

SSI73K224L
V.22bis/V.22/V.21 , Bell 212A/1 03
Single-Chip Modem
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VOO = recommended range unless otherwise noted.)
PARAMETER

CONDITIONS

100, Supply Current

ClK

MIN

NOM

MAX

= 11.0592 MHz

---

ISET Resistor = 2 MQ
1001, Active

UNITS

-----

Operating with crystal oscillator,

18

25

rnA

5

rnA

0.8

V

VOO

V

VDD

V

100

50

J.lA
J.lA
J.lA

VDD

V

0.4

V

-50

J.lA

~-

ID02, Idle

< 5 pF capacitive load on ClK pin

3

-_.-

~-

--

Digital Inputs
Vll, Input low Voltage
VIH, Input High Voltage
All Inputs except Reset
XTl1,XTl2

2.0

Reset, XTl1 , XTl2

3.0

-

---

IIH, Input High Current

VI = VDD

Ill, Input low Current

VI =OV

Reset Pull-down Current

Reset = VDD

-200
2

~---~---.-

Digital Outputs
VOH, Output High Voltage

10= 10H Min
lOUT = -0.4 rnA

VOL, Output low Voltage

10 = lOUT = 1.6 mA

RXD Tri-State Pull-up Curr.

RXD = GND

2.4

-2

-------.-~---.-

Capacitance

-

Maximum Capacitive load
~-~-

ClK
Input Capacitance

Maximum permitted load
All Digital Inputs

3-135

----

--

---- _..

25

pF

10

pF

I

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.)
PARAMETERS

CONDITIONS

MIN

NOM

MAX

UNITS

-10.0

-9

dBmO

QAM/DPSK Modulator
Carrier Suppression

Measured at TXA

Output Amplitude

TX scrambled marks
ATI=0100 (default)

-11.5

Output Freq. Error

ClK = 11.0592 MHz

-.31

Transmit level

ATI = 0100 (Default)
Transmit Dotting Pattern

TXA Output Distortion

All products through BPF

Output Bias Distortion
at RXD

Dotting Pattern measured at RXD
Receive level -20 dBm, SNR 20 dB

Output Jitter at RXD

Integrated for 5 seconds

Sum of Bias Distortion and
Output Jitter

Integrated for 5 seconds

35

dB

---------

---------

FSK Modulator/Demodulator
+.20

0/0

-9

dBmO

-45

dB

-10

+10

%

£15

+15

0/0

+17

0/0

-9

dBmO

-40

dB

-11.5

--1---

-10.0

-17
----

Answer Tone Generator (2100 or 2225 Hz)
Output Amplitude

ATI = 0100 (Default level)

-11.5

Not in V.21
Output Distortion

1~1

Distortion pro<:!l:l~!s in receive band
------~

DTMF Generator

Not in V.21
-0.03

Freq. Accuracy
Output Amplitude

Low Band, An = 0100, DPSK Mode

-10

Output Amplitude

High Band, An = 0100, DPSK Mode

-8

Twist

High-Band to Low-Band, DPSK Mode

1.0

Receiver Dynamic Range

Refer to Performance Curves

-43

Call Progress Detector

In Call Init mode

+0.25

%

-8

dBmO

--_._--

~.-

Detect level

2.0

-6

dBmO

3.0

dB

-3.0

dBmO

0

dBmO

----_._--

-34

460 Hz test signal

-40

dBmO

Delay Time

-70 dBmO to -30 dBmO STEP

25

ms

Hold Time

-30 dBmO to -70 dBmO STEP

25

ms

Reject level

NOTE: Parameters expressed in dBmO refer to the following definition:

odB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.

3-136

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS

CONDITIONS

Carrier Detect

Receive Gain

Threshold

All Modes

Hysteresis

All Modes

Delay Time

FSK
DPSK
OAM

Hold Time

FSK
DPSK
OAM

Answer Tone Detectors

MIN

UNITS

-43

dBmO

2-- ---

70 dBmO to -6 dBmO

25

70 dBmO to -40 dBmO

25

._-_ ..

37

ms

37

ms

17

ms

17

ms

37

ms

-70 dBmO to -6 dBmO

7

-70 dBmO to -40 dBmO

7

-70 dBmO to -6 dBmO

25

-70 dBmO to -40 dBmO

25

37

ms

-6 dBmO to -70 dBmO

25

37

ms

-40 dBmO to -70 dBmO

15

30

ms

-6 dBmO to -70 dBmO

20

29

ms

21

ms

-40 dBmO to -70 dBmO

14

-6 dBmO to -70 dBmO

25

-40 dBmO to -70 dBmO

18

--

_. ---_.-

------

-

- -._. -_.-

32

ms

28

ms

-48

-43

dBmO

6

50

ms

6

50

ms

----

--

---------

DPSK Mode
Call Init Mode, 2100 or 2225 Hz

Hold Time

Pattern Detectors

MAX

-48

Detect Level
Detect Time

NOM

=On for lower input level measl!r~ments

DPSK Mode

---,----

S1 Pattern

-"--

Delay Time

For signals from -6 to -40 dBmO,

10

55

ms

Hold Time

-6 to -40 dBmO, Demod Mode

10

45

ms

.._----

Unscrambled Mark
Delay Time

For signals from -6 to -40

10

45

ms

Hold Time

caliinit Mode

10

45

ms

-28

dBmO

7

ms

-

Receive level Indicator

---

-22

Detect On
Valid after Carrier Detect

--

1

DPSK Mode

4

- ---_ .._-

Output Smoothing Filter

--

200

Output Impedance

TXA pin

Output load

TXA pin; FSK Single

300

- ---

Tone out for THD = -50 dB
in .3 to 3.4 kHz range

10

Q
KQ

-----

50

pF

Maximum Transmitted

4 kHz, Guard Tones off

-35

dBmO

Energy

10kHz, Guard Tones off

-55

dBmO

12 kHz, Guard Tones off

-65

dBmO

3-137

I

551 73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS

CONDITIONS

MIN

NOM

MAX

UNITS

Anti Alias Low Pass Filter
Out of Band Signal Energy
(Defines Hybrid TransHybrid loss requirements)

Level at RXA pin with receive
Boost Enabled
Scrambled data at 2400 bit/s
in opposite band
Sinusoids out of band

-14

dBm

-9

dBm

Transmit Attenuator
Range of Transmit Level

Default ATT=0100 (-10 dBmO) 1111-0000

Step Accuracy

-21

Output Impedance

-6

dBmO

+0.15

dB

300

z

1.5

mVrms

±7

Hz

--

-0.15
200

Clock Noise
TXA pin; 153.6 kHz

carrier Offset
Capture Range

_L__±_? ...

Originate or Answer

Recovered Clock
Capture Range

% of frequency (originate or

J
J

]+002

-0.02

answer)

%

Guard Tone Generator
Tone Accuracy

550 Hz

0/0

+1.2

- - f-----

1800 Hz

~--

-0.8

Tone Level

550 Hz

-4.5

-3.0

(Below QAM/DPSK
Output)

1800 Hz

-7.5

-6.1

Harmonic Distortion

550 Hz

(700 to 2900 Hz)

1800 Hz

-1.5

dB

-4.5

dB

-50

dB

-50

dB

--

------

---_.

Timing (Refer to Timing Diagrams)
Parallel Mode

_.

TAL

CSI Addr. setup before ALE Low

ns

30

TLA

CSI Addr. hold after ALE Low

6

ns

TLC

ALE Low to RDIWR Low

40

ns

TCL

RD/WR Control to ALE High

10

ns
-

TRD

Data out from RD Low

TLL

ALE width

90

TRDF

Data float after RD High

TRW

RDwidth

ns
ns

25
40

ns

--

70
3-138

ns

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
Parallel Mode

CONDITIONS

MIN

NOM

MAX

UNITS

(Continued)

TWW

WRwidth

70

TDW

Data setup before WR High

70

TWD

Data hold after WR High

20

TRCK

Clock High after RD Low

250

TAR

Address setup before RD Low

ns

-----

ns
ns

- -

Serial Mode
----~-

TRA

Address hold after RD Low

TRD

RD to Data valid

TRDF

Data float after RD High

TCKDR

Read Data out after Falling
Edge of EXCLK

T1

-------- f--------

0

ns
ns
ns

350

-

- -

300

ns

40

ns

300

ns

-- --------

TWW
TAW

-

WRwidth

350

Address setup before WR Low

ns

---_ ..._-

ns

50
-~

-------

TWA

Address hold after Rising
Edge of WR

50

ns

TCKDW

Write Data hold after Falling
Edge of EXCLK

200

ns

TCKW

WR High after Falling
Edge of EXCLK

330

TDCK

Data setup before Falling
Edge of EXCLK

T1, T2

Minimum Period

ns

50

ns

500

ns

NOTE: T1 and T2 are the low/high periods, respectively, of EXCLK in serial mode.

3-139

T1 + T2

I

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)

~

ALE

~

~
TlC

TRW

TCl

J

+

--+--

RD

1

TlC

TlA

L

ADO-AD7

cs

1

TWW

--K
-=-1-

TAL..

ADDRESS

TRD

J.!.I
>!--K

~

~D

TRDF

~
READ DATA

>!--K
-~-

-4-

TOW
ADDRESS

-4-

EXCLK

AO-A2

DATA

WRITE TIMING DIAGRAM (SERIAL VERSION)

--+1

T2

1--

EXCLK

--+1

T1

---/-----------------~-_tf;:,

DATA

3-140

'"

~A~

READ TIMING DIAGRAM (SERIAL VERSION)

AO-A2

J

---~

WR

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
APPLICATIONS INFORMATION
GENERAL CONSIDERATIONS
Figures 1 and 2 show basic circuit diagrams for
K-Series modem integrated circuits. K-Series products
are designed to be used in conjunction with a control
processor, a UART or RS-232 serial data interface,
and a OAA phone line interface to function as a typical
intelligent modem. The K-Series ICs interface directly
with Intel 8048 and 80C51 microprocessors for control
and status monitoring purposes. Two typical OM
arrangements are shown: one for a split ±5 or ±12 V
design and one for a single 5 V design. These diagrams
are for reference only and do not represent productionready modem designs.

C9
.1 nF

RS232
LEVEL
CONVERTERS

K-Series devices are available with two control interface versions: one for a parallel multiplexed address/
data interface, and one for a serial interface. The
parallel version is intended for use with 8039148 or
8031/51 microcontrollers from Intel or many other
manufacturers. The serial interface 22-pin version can
be used with other microcontrollers or in applications
where only a limited number of port lines are available
or the application does not lend itself to a multiplexed
address/data interface. The parallel versions may also
be used in the serial mode, as explained in the data
sheet pin description.
In most applications the control/erwill monitor the serial
data for commands from the DTE and the received
data for break signals from the far end modem. In this
way, commands to the modem are sent over the same
line as the transmitted data. In other applications the
RS-232 interface handshake lines are used for modem
control.

+ C8
22nF

CI
390 pF

CA

CB L...-'"l...t...="-CC L...-'"l-,-=,,----,

CD

WR

CF

as

ALE

SSI
K·SERIES
LOW
POWER
FAMILY

BA
BB
DA

DO
DB

<"1-I~~---+---+-f----I
<"1-I~~---+---+---'f----I

US,U6
MCI45406

..r

R9
10K

FIGURE 1: Basic Box Modem with Dual-Supply Hybrid

3-141

VRI
MOV
V250L20

3

SSI73K224L
V.22b is/V. 22/V. 21 , Bell 212A/1 03

Single-Chip Modem
DIRECT ACCESS ARRANGEMENT (DAA)

The telephone line interfaces show two examples of
how the "hybrid" may be implemented. The split supply
design (Figure 1) is a typical two op-amp hybrid. The
receive op-amp serves two purposes. It supplies gain
to amplify the receive signal to the proper level for the
modem's detectors and demodulator, and it removes
the transmitted signal from the receive signal present
at the transformer. This is done by supplying a portion
of the transmitted signal to the non-inverting input of
the receive op-amp at the same amplitude as the signal
appearing at the transformer, making the transmit
signal common mode.
The single-supply hybrid is more complex than the
dual-supply version described above, but its use eliminates the need for a second power supply. This Circuit
(Figure 2) uses a bridged drive to allow undistorted
signals to be sent with a single 5 volt supply. Because
DTMF tones utilize a higher amplitude than data, these

signals will clip if a single-ended drive approach is
used. The bridged driver uses an extra op-amp (U1 A)
to invert the signal coming from the gain setting op-amp
(U1 B) before sending it to the other leg of the transformer. Each op-amp then supplies half the drive signal
to the transformer. The receive amplifier (U1 C) picks
off its signal at the junction of the impedance matching
resistor and the transformer. Because the bottom leg of
the transformer is being driven in one direction by U1 A
and the resistor is driven in the opposite direction at the
same time by U1 B, the junction of the transformer and
resistor remains relatively constant and the receive
signal is unaffected.
DESIGN CONSIDERATIONS

Silicon Systems' 1-chip modem products include all
basic modem functions. This makes these devices
adaptable for use in a variety of applications, and as
easy to control as conventional digital bus peripherals.

C1
390pF

R4
37.4K 1%

. C3

* Note: Op-amp U 1
must be rated for
single 5V operation.
R10 & R11 values
depend on Op-amp
used.

0.1""

~ f-------<~

VR1
MOV

V2501.20

VOLTAGE
REFERENCE

HOOK

>--_ _ _ _ _---1

RING

~----------------~

FIGURE 2: Single 5V Hybrid Version
3-142

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
Unlike digital logic circuitry, modem designs must
properly contend with precise frequency tolerances
and very low level analog signals, to ensure acceptable
performance. Using good analog circuit design practices will generally result in a sound design. Following
are additional recommendations which should be
taken into consideration when starting new designs.
CRYSTAL OSCILLATOR

The K-Series crystal oscillator requires a parallel mode
(antiresonant) crystal which operates at 11.0592 MHz.
It is important that this frequency be maintained to
within ±0.01% accuracy.
In order for a parallel mode crystal to operate correctly
and to specification, it must have a load capacitor
connected to the junction of each of the crystal and
internal inverter connections, terminated to ground.
The values of these capaCitors depend primarily on the
crystal's characteristics, and to a lesser degree on the
internal inverter circuit. The values used affect the
accuracy and start up characteristics of the oscillator.
LA YOUT CONSIDERATIONS

Good analogldigital design rules must be used to control
system noise in order to obtain highest performance in
modem designs. The more digital circuitry present on
the PC board, the more this attention to noise control is
needed. The modem should be treated as a high impedance analog device. A 22 mF electrolytic capacitor in
parallel with a 0.22 mF ceramic capacitor between VDD
and GND is recommended. Liberal use of ground
planes and larger traces on power and ground are also
highly favored. The ISET resistor and capacitor should
be mounted near the ISET pin, away from digital signals.
High speed digital circuits tend to generate a significant
amount of EMI (Electro-Magnetic Interference) which
must be minimized in order to meet regulatory agency
limitations. To accomplish this, high speed digital devices should be locally bypassed, and the telephone line
interface and K-Series device should be located close to
each other near the area of the board where the phone
line connection is accessed. To avoid problems, power
supply and ground traces should be routed separately to
the analog and digital functions on the board, and digital
signals should not be routed near low level or high
impedance analog traces. The analog and digital
grounds should only connect at one pOint near the KSeries device ground pin to avoid ground loops. The KSeries modem IC's should have both high frequency
and low frequency bypassing as close to the package as
possible.

MODEM PERFORMANCE
CHARACTERISTICS
The curves presented here define modem IC performance under a variety of line conditions while inducing
disturbances that are typical of those encountered
during data transmission on public service telephone
lines. Test data was taken using an AEA Electronics'
"Autotest I" modem test set and line simulator, operating under computer control. All tests were run fullduplex, using a Hayes SmartModem™ 2400 as the
reference modem. A 511 pseudo-random-bit pattern
was used for each data point. Noise was C-message
weighted and all signal-to-noise (SIN) ratios reflect
total power measurements similar to the CCITT V.56
measurement specification. The individual tests are
defined as follows.
SER vs. SIN

This test measures the ability of the modem to operate
over noisy lines with a minimum of data-transfer errors.
Since some noise is generated in the best of dial-up
lines, the modem must operate with the lowest SIN
ratio possible. Better modem performance is indicated
by test curves that are closest to the BER axis. A
narrow spread between curves representing the four
line parameters indicates minimal variation in performance while operating over a range of aberrant operating conditions. Typically, a modem will exhibit better
BER-performance test curves receiving in the low
band than in the high band.
SER vs. Receive Level

This test measures the dynamic range of the modem.
Because signal levels vary widely over dial-up lines,
the widest possible dynamic range is desirable. The
minimum Bell specification calls for 36 dB of dynamiC
range. SIN ratios are held constant at the indicated
values while the receive level is lowered from a very
high to very low signal levels. The width of the "bowl" of
these curves, taken at the BER point, is the measure of
dynamic range.

3-143

3

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem

551 73K224L BER vs 5/N-DP5K LOW BAND
10-2

"

'"1\\

JI

\~

10-3

LOW BAND RECEIVE
-30dBm
DPSK OPERATION
1200 BITtS

551 73K224L BER vs S/N-DPSK HIGH BAND

t

10-2

"

1\,\

5a:

\

~

\~ ... .,...., '>--'

w
~

a:

w
CD

H

\

III

,\

10-5

/v \1 \

10-5

r--- 1.--"---,

I~~

\

1\ \

\\
\

11
\

10-6
4

6

8

\

10-6

14

12

10

16

Cl_ 3002, FLAT

\\
~\I\

I::

\

/"

Cl, C2, FLAT

I

\"

w

~

I::

t

,..,v

\1\

a:
a:
0 10'"
a:
a:

1\ \

10-4

-30dBm
DPSK OPERATION
1200 BITtS

\

\\
~
a:

I

1\'1\

10-3
\

W

J HIGH BAND RECEIVE

\~\

4

6

SIGNAL TO NOISE (dB)

8

12

10

14

16

SIGNAL TO NOISE (dB)

SSI73K224L
BER vs S/N-QAM-HIGH BAND

SSI73K224L
BER vs S/N-QAM-LOW BAND
10-2

10-2

,

~
10-3

I~

II

./

~
w
~

a:
a:
0 10'"
a:
a:

'~~ ~

w

~~

III

Ir;-~
...........
1L....:r-'

w

~

,

~
a:
a:
0 10'"
a:
a:
w

~\\

~~

r"c2l.

t-.... ,\'

1/

l' ~.1
(\

CD

'c2)

l\~~

10-5

1\'

\\

\\

~

1\\

1\
1\\

10-6

8

10

12

14

16

I

~~J

\~
3002

t::

~l IT

10-5

OAM OPERATION
2400 BITtS

~\

~

I::

II

.~

10-3

~0 I-- I--

~

II HIGH BAND
RECEIVE
-30dBm

~\

LOW BAND RECEIVE
-30dBm
OAM OPERATION
2400 BITtS

18

\'

10-6

8

20

10

12

14

16

SIGNAL TO NOISE (dB)

SIGNAL TO NOISE (dB)

3-144

18

20

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem

SSI 73K224L BER vs CARRIER OFFSET

II

HIGH BAND RECEIVE
-30 dBm
OAM OPERATION
2400 BITtS

t

10-3

LJ.J

~
a:
a:
0
a:
a:

10-4

I

LJ.J

I-

D5

H

I

\

10-5

..

'-

-12

-8

-4

,

300217 dB SIN

C217dBSiN

"':;1-"

I

-"'

,..-

4

12

CARRIER OFFSET (HZ)

3-145

SSI73K224L
V. 22bis/V. 22/V.21 , Bell 212A/1 03
Single-Chip Modem
PACKAGE PIN DESIGNATIONS
(Top View)

':~t4'· .~,.6i
",.· :. .·,• .~':

I~!i

44-Lead PLCC

",·.I:,

CLK

GND

XTL1

RXA

XTL2

VREF

29

:jJw¢.:\::r::::: ,

::,tMlWt?:"

41
31

30

RXA

ADO

RESET

28

VREF

AD1

ISET

27

RESET

AD2

RXCLK

..

~:

AD3

RXD

RXCLK

AD4

TXD

32-Lead PLCC

25

.:::~~~r?

RXD

AD5

cs

TXD

AD6

EXCLK

EXCLK

AD7

TXCLK

TXCLK

ALE

jNf

INT

WR

TXA

TXA

AD

VDD

,:\@$.tt):'

::,'t~~#.8::::;:
):5*f}?:

26

,,:::::::::':

ISET

40
N/C

32

24

:,\~I\:)<'

23

\:::::ij>,@¥.{

22
21
15

16

18

17

19

20
N/C

SaO-Mil
28-Pln DIP

400-MII
22-Pln DIP

32, 44-Pin PLCC

I--

w
!l2

:s
Q

~ Cx

Q

z a: a: z z

52 51

:s

:.::
...J

Q

<.:>
!JJ ~ Q x
~ Q Q
Z

I--

Z

<.:>

UJ

z

0

C

«

I--

C\I

...J

...J

I--

I--

x

x

:.::
...J
<.:>

50 49 48 47 46 45 44 43 42 41
N/C

c
Z

(!)

28

«
x

IJ...

27

26

a:

w

a:

>

AD1

25

R!=SET

24

ISET

23

RXCLK

INTB
N/C

N,c
RXA

TXA

N,c

NIC

N,c

34

6

33

GND
NIC

31

CLK

RXD

21

TXD

VDD
N/C

AD6

10

20

cs

N/C

AD7

11

19

EXCLK

RDB

XTAL1

11

WRB

XTAL2

12

NIC

N,c

13

ALE
14 15 16 17 18 19 20 21

22

NIC

10

N,c

AD3

22 23 24 25

12

13

14

15

16

17

w

I~

I~

c
c

I--

«
x

!~

...J



18

:.::
...J

x<.:>

I--

28-Pin PLCC

toV
CD
0
C\I
c Q Q 0 c c c c c Q c Q Q
« z z « « « « « « z « z z
CO)

It)

52-Lead QFP

CAUTION: Use handling procedures necessary
for a static sensitive comp.onent.

3-146

SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
PACKAGE PIN DESIGNATIONS
(Top View)

1e

64 63 62 61

ADO

Nrc
Nrc

60 59 58 57 56 55 54 53 52 51

50 49

2

g

Nrc

U

ISET

46

NrC

Nrc

45

RXCLK

Nrc

44

N/C

AD1

43

RXD

Nrc

42

N/C

AD2

41

N/C

40

TXD

AD3
AD4

10

39

Nrc

AD5

11

38

cs

AD6

12

37

EXCLK

Nrc

13

36

AD7

14

35
34

Nrc
Nrc
Nrc

33

N/C

Nrc
Nrc

15
16 17 18 19 20 21

22 23 24 25 26 27 28 29 30 31

32

64-Lead TQFP

I

CAUTION: Use handling procedures necessary
for a static sensitive component.

ORDERING INFORMATION
PART DESCRIPTION

ORDER NO.

PKG.MARK

SSI 73K224L with Serial Bus Interface
22-Pin Plastic Dual-In-Line

73K224LS-1 P

73K224LS-1 P

28-Pin Plastic Dual-In-Line

73K224L-IP

73K224L-IP

28-Pin Plastic Leaded Chip Carrier

73K224L-281H

73K224L-281H

32-Pin Plastic Leaded Chip Carrier

73K224L-321H

73K224L-321H

44-Pin Plastic Leaded Chip Carrier

73K224L-IH

73K224L-IH

52-Lead Quad Flat Pack Package

73K224L-IG

73K224L-IG

64-Lead Thin Quad Flat Pack Package

73K224L-IGT

73K224L-IGT

SSI 73K224L with Parallel Bus Interface

--

--

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
ofthird parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX (714) 573-6914

0194- rev.

3-147

Protected by the following patents:
(4,777,453), (4,789,995), (4,870,370), (4,847,868), (4,866,739)
©1989 Silicon Systems, Inc.

Notes:

3-148

SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem

'#""h"'61&-"1
January 1994

DESCRIPTION

FEATURES

The 551 73K302L is a highly integrated single-chip
modem Ie which provides the functions needed to
construct a Bell 202, 212A and 103 compatible
modem. The 551 73K302L is an enhancement of the
551 73K212L single-chip modem with Bell 202 mode
features added. The 73K302L is capable of 1200 or
0-300 biVs full-duplex operation over dial-up lines.
4-wire full-duplex capability and a low speed back
channel are also provided in Bell 202 mode. The
551 73K302L recognizes and generates a 900 Hz soft
carrier turn-off tone, and allows 103 for 300 bit/s F5K
operation. The SSI73K302L integrates analog, digital,
and switched-capacitor array functions on a single
substrate, offering excellent performance and a high
level of functional integration in a single 28 or 22pin DIP configuration. The 551 73K302L operates
from a single +5V supply with very low power
consumption.

One-ch ip Bell 212A, 103 and 202S/T standard
compatible modem data pump
Full-duplex operation at 0-300 bitls (FSK), 1200 bitls
(DPSK) or 0-1200 bitls (FSK) forward channel with or
without 0-150 bitls back channel
Full-duplex 4-wire operation in Bell 202 mode
Pin and software compatible with other
551 K-Series 1-chip modems
Interfaces directly with standard microprocessors
(8048, 80C51 typical)
Serial (22-pin DIP) or parallel microprocessor bus
for control
Serial port for data transfer
Both synchronous and asynchronous modes of
operation
Call progress, carrier, precise answer tone
(2225 Hz), soft carrier turn-off (SCT), and FSK mark
detectors
DTMF, answer, and SCT tone generators

The 551 73K302L includes the DP5K and F5K modulator/demodulator functions, call progress and handshake tone monitors, test modes, and a tone generator
capable of producing DTMF, answer, and 900 Hz soft
carrier turn-off tone. This device supports Bell
202, 212A and 103 modes of operation, allowing both

Test modes available: ALB, DL, RDL, Mark, Space,
Alternating bit patterns
CMOS technology for low power consumption
using 35 mW @ 5V from a single power supply

(Continued)

PIN DIAGRAM

BLOCK DIAGRAM

elK

AOO-AD7

XTL1
XTl2
RD

WR

0----+1

TXA

o---~

ALE o---~
CS o---~
RESET o---~

ADO
AD1

RXA

AD2
AD3

INT

o-------l

SMART
DIALING

AD4

&

TXD

0------......

F~~~S

RXD o--------~

AD5

J4.------..J

ADS
AD?
ALE
WR

RD

0194 - rev.

3-149

I

SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
DESCRIPTION (Continued)

(±.01% is the required synchronous data rate
accuracy).

synchronous and asynchronous communications.
The SSI73K302L is designed to appearto the systems
designer as a microprocessor peripheral, and will easily interlace with popular one-chip microprocessors
(80C51 typical) for control of modem functions through
its8-bit multiplexed address/data bus orvia an optional
serial command bus. An ALE control line simplifies
address demultiplexing. Data communications occurs
through a separate serial port only.

The SYNC/ASYNC converter also has an extended
overspeed mode which allows selection of an output
overspeed range of either +1% or +2.3%. In the extended overspeed mode, stop bits are output at 7/8 the
normal width.

The SSI73K302L is ideal for use in either free standing
or integral system modem products where multi-standard data communications is desired. Its high functionality, low power consumption and efficient packaging
simplify design requirements and increase system
reliability. A complete modem requires only the addition of the phone line interlace, a modem controller,
and RS232 level converter for a typical system.
Tri-mode capability in one-chip allows full-duplex Bell
212 and 103 operation or assymetrical Bell 202S
operation overthe 2-wire switched telephone network.
202T mode full-duplex operation at 1200 bit/s is also
possible when operating on 4-wire leased lines.
A soft carrier turn-off feature facilitates fast line turn
around when using the 202S mode for half-duplex
applications.
Th.e SSI 73K302L is part of Silicon Systems K-Series
family of pin and function compatible single-chip
modem products. These devices allow systems to be
configured for higher speeds and Bell or CCITT operation with only a single component change.

OPERATION

ASYNCHRONOUS MODE
Data transmission for the DPSK mode requires that
data ultimately be transmitted in a synchronous fashion. The SSI 73K302L includes ASYNC/SYNC and
SYNC/ASYNC converters which delete or insert stop
bits in order to transmit data at a regular rate. In
asynchronous mode the serial data comes from the
TXD pin into the ASYNC/SYNC converter. The
ASYNC/SYNC converter accepts the data provided on
the TXD pin which normally must be 1200 biVs + 1.0%,
2.5%. The rate converter will then insert or delete stop
bits in orderto output a signal which is 1200 biVs ± .01 %

3-150

The serial data stream from the transmit buffer or the
rate converter is passed through the data scrambler
and onto the analog modulator. The data scrambler
can be bypassed under processor control when
unscrambled data must be transmitted. If serial input
data contains a break Signal through one character
(including start and stop bits) the break will be
extended to at least 2 • N + 3 bits long (where N is the
number of transmitted bits/character).
Serial data from the demodulator is passed first
through the data descrambler and then through the
SYNC/ASYNC converter. The ASYNC/ASYNC converterwill reinsert any deleted stop bits and output data
at an intra-character rate (bit-to-bit timing) of no greater
than 1219 bit/so An incoming break signal (low through
two characters) will be passed through without incorrectly inserting a stop bit.
SYNCHRONOUS MODE

The Bell 212A standard defines synchronous operation at 1200 biVs. Operation is similar to that of the
asynchronous mode except that data must be synchronized to a provided clock and no variation in data
transfer rate is allowable. Serial input data appearing at
TXD must be valid on the rising edge of TXCLK.
TXCLK is an internally derived signal in internal mode
and is connected internally to the RXCLK pin in slave
mode. Receive data at the RXD pin is clocked out on
the falling edge of RXCLK. The ASYNCH/SYNCH
converter is bypassed when synchronous mode is
selected and data is transmitted out at the same rate as
it is input.
DPSK MODULATOR/DEMODULATOR

In DPSK mode the SSI 73K302L modulates a serial bit
stream into di-bit pairs that are represented by four
possible phase shifts as prescribed by the Bell 212A
standards. The base-band signal is then filtered to
reduce intersymbol interference on the bandlimited
2-wire telephone line. Transmission occurs using ei-

SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
ther a 1200 Hz (originate mode) or 2400 Hz (answer
mode) carrier. Demodulation is the reverse of the
modulation process, with the incoming analog signal
eventually decoded into di-bits and converted back to
a serial bit stream. The demodulator also recovers the
clock which was encoded into the analog signal during
modulation. Demodulation occurs using either a
1200 Hz carrier (answer mode or ALB originate mode)
or a 2400 Hz carrier (originate mode or ALB answer
mode). The SSI 73K302L uses a phase locked loop
coherent demodulation technique for optimum
receiver performance.
FSK MODULATOR/DEMODULATOR

The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. Bell 103 mode uses 1270
and 1070 Hz (originate, mark and space) or 2225 and
2025 Hz (answer, mark and space). Bell 202 mode
uses 1200 and 2200 Hz for the main channel and 387
and 487 Hz for the back channel. The modulation rate
of the back channel is up to 150 baud. Demodulation
involves detecting the received frequencies and
decoding them into the appropriate binary value. The
rate converter and scrambler/descrambler are automatically bypassed in the 103 or 202 modes.
PASSBAND FILTERS AND EQUALIZERS

High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay equalization and rejection of out-of-band signals in the
receive channel. Amplitude and phase equalization
are necessary to compensate for distortion of the
transmission line and to reduce intersymbol interference in the bandlimited receive signal. The transmit
signal filtering approximates a 75% square root of
raised Cosine frequency response characteristic.
AGC

The automatic gain control maintains a signal level at
the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping and provides a total
receiver dynamic range of >45 dB.

PARALLEL BUS INTERFACE
Four 8-bit registers are provided for control,option
select and status monitoring. These registers are ad3-151

dressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as four consecutive memory locations. Two control registers and the tone register are
read/write memory. The detect register is read only
and cannot be modified except by modem response to
monitored parameters. The parallel bus interface is not
available in the 22-pin package.
SERIAL COMMAND INTERFACE

The serial command interface allows access to the
SSI 73K302L control and status registers via a serial
command port. In this mode the AO , A1 and A2 lines
provide register addresses for data passed through the
data pin under control of the RD and WR lines. A read
operation is initiated when the RD line is taken low. The
first bit is available after RD is brough low and the next
seven cycles of EXCLK will then transfer out seven bits
of the selected address location LSB first. A write takes
place by shifting in eight bits of data LSB first for eight
consecutive cycles of EXCLK. WR is then pulsed low
and data transfer into the selected register occurs on
the rising edge of WR.
SPECIAL DETECT CIRCUITRY

The special detect circuitry monitors the received analog signal to determine status or presence of carrier,
answer tone and weak received signal (long loop
condition), special tones such as FSK marking and the
900 Hz soft carrier turn-off tone are also detected. A
highly frequency selective call progress detector provides adequate discrimination to accurately detect
lower quality call progress signals.
DTMF GENERATOR

The DTMF generator will output one of 16 standard
tone pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mode
is selected using the tone register and the transmit
enable (CRO bit D1) is changed from 0 to 1.
SOFT CARRIER TURN-OFF TONE GENERATOR

The soft carrier turn-off tone generator will output a
900 Hztone. When activated in Bell 202 main channel
transmit mode, the output signal will shift to 900 Hz,
maintaining phase continuity during the transition.

3

SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
PIN DESCRIPTION
POWER
28·PIN

22·PIN

TYPE

DESCRIPTION

GND

28

1

I

System Ground.

VDD

15

11

I

Power supply input, 5V ±10%. Bypass with .1 and 22 JlF
capacitors to GN D.

VREF

26

21

0

An internally generated reference voltage. Bypass with
.1 JlF capacitor to GND.

ISET

24

19

I

Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 Mn resistor. ISET should be bypassed to GND with a
.1 JlF capacitor.

NAME

PARALLEL MICROPROCESSOR INTERFACE
12

-

I

Address latch enable. The falling edge of ALE latches the
address on ADO-AD2 and the chip select on CS.

4-11

-

I/O

Address/data bus. These bidirectional tri-state multiplexed lines carry information to and from the internal
registers.

CS

20

-

I

Chip select. A low on this pin during the falling edge of ALE
allows a read cycle or a write cycle to occur. ADO-AD7 will
not be driven and no registers will be written if CS (latched)
is not active. The state of CS is latched 0 n the falling edge
of ALE.

ClK

1

2

0

Output clock. This pin is selectable under processor control
to be either the crystal frequency (for use as a processor
clock) or 16 x the data rate for use as a baud rate clock in
DPSK mode only. The pin defaults to the crystal frequency
on reset.

INT

17

13

0

Interrupt. This open drain output signal isused to inform the
processor that a detect flag has occurred. The processor
must then read the detect register to determine which
detect triggered the interrupt. INT will stay low until the
processor reads the detect register or does a full reset.

RD

14

-

I

Read. A low requests a read of the SSI73K302l internal
registers. Data cannot be output unless both RD and the
latched CS are active or low.

RESET

25

20

I

Reset. An active high signal on this pin will put the chip into
an inactive state. All control register bits (CRO, CR1, Tone)
will be reset. The output of the ClK pin will be set to the
crystal frequency. An internal pull down resistor permits
power on reset using a capacitor to VDD.

ALE
ADO-AD7

3-152

SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
PIN DESCRIPTION (Continued)
PARALLEL MICROPROCESSOR INTERFACE (Continued)
NAME
WR

2S-PIN

22-PIN

TYPE

13

-

I

DESCRIPTION
Write. A low on this informs the SSI 73K302L that data is
available on ADO-AD7 for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are active low.

SERIAL MICROPROCESSOR INTERFACE
AO-A2

-

5-7

DATA

-

RD

WR

I

Register Address Selection. These lines carry register
addresses and should be valid during any read or write
operation.

8

I/O

Serial Control Data. Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs data.

-

10

I

Read. A low on this input informs the SSI 73K302L that
data or status information is being read by the processor.
The falling edge of the RD signal will initiate a read from the
addressed register. The RD signal must continue for eight
falling edges of EXCLK in order to read all eight bits of the
referenced register. Read data is provided LSB first. Data
will not be output unless the RD signal is active.

-

9

I

Write. A low on this input informs the SSI73K302L that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on
the DATA pin for eight consecutive falling edges of EXCLK
and then to pulse WR low. Data is written on the rising edge
ofWR.

-----

Note:

-------

-

In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the
pins; AO, A 1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.
-

The serial control mode is provided in the parallel control versions by tying ALE high and CS low.
In this configuration AD7 becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2,
respectively.

3-153

I

SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
PIN DESCRIPTION (Continued)
DTE USER INTERFACE
NAME

28-PIN

22-PIN

TYPE

EXCLK

19

15

I

External Clock. This signal is used only in synchronous
DPSK transmission when the external timing option has
been selected. In the external timing mode the rising edge
of EXCLK is used to strobe synchronous DPSK transmit
data available on the TXD pin. Also used for serial control
interface.

RXCLK

23

18

0

Receive Clock. The falling edge of this clock output is
coincident with the transitions in the serial received DPSK
data output. The rising edge of RXCLK can be used to latch
the valid output data. RXCLK will be valid as long as a
carrier is present. In Bell 202 mode a clock which is 16 x
1200 or 16 x 150 baud data rate is output.

RXD

22

17

0

Received Data Output. Serial receive data is available on
this pin. The data is always valid on the rising edge of
RXCLK when in synchronous mode. RXD will output constant marks if no carrier is detected.

TXCLK

18

14

0

Transmit Clock.This signal is used only in synchronous
DPSK transmission to latch serial input data on the TXD
pin. Data must be provided so that valid data is available
on the rising edge of the TXCLK. The transmit clock is
derived from different sources depending upon the synchronization mode selection. In Internal Mode the clock is
1200 Hz generated internally. In External Mode TXCLK is
phase locked to the EXCLK pin. In Slave Mode TXCLK is
phase locked to the RXCLK pin. TXCLK is always active. In
Bell 202 mode the output is a 16 x 1200 baud clock or 16
x 150 baud to drive a UART.

TXD

21

16

I

Transmit Data Input. Serial data for transmission is applied
on this pin. In synchronous modes, the data must be valid
on the rising edge of the TXCLK clock. In asynchronous
modes (1200 or300 baud) no clocking is necessary. DPSK
must be 1200 biVs +1%, -2.5% or +2.3%, -2.5 % in
extended overspeed mode.

DESCRIPTION

ANALOG INTERFACE AND OSCILLATOR
RXA

27

22

I

Received modulated analog signal input from the telephone line interface.

TXA

16

12

0

Transmit analog output to the telephone line interface.

XTL1
XTL2

2
3

3
4

I
I

These pins are for the internal crystal oscillator requiring
a 11.0592 MHz parallel mode crystal and two load capacitors to Ground. XTL2 can also be driven from an external
clock.
3-154

SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
REGISTER DESCRIPTIONS
Four a-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AO and A 1
address lines in serial mode, orthe ADO and AD11ines
in parallel mode. The ADO and AD1lines are latched by
ALE. Register CRO controls the method by which data
is transferred over the phone line. CR1 controls the
REGISTER BIT SUMMARY

NOTE:

When a register containing reserved
control bits is written into, the reserved bits
must be programmed as O's.

3-155

interface between the microprocessor and the
551 73K302L internal state. DR is a detect register
which provides an indication of monitored modem
status conditions. TR, the tone control register, controls the DTMF generator, answer and guard tones and
RXD output gate used in the modem initial connect
sequence. All registers are read/write except for DR
which is read only. Register control and status bits are
identified below:

SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
REGISTER ADDRESS TABLE

0~103

FSK
1=202 FSK

OOOO=PWR DOWN
ll00=FSK
0010-EXT SYNCH
0011 =SLA VE SYNCH
01 OO=ASYNCH 8 BITs/CHAR
0101.ASYNCH 9 BITs/CHAR
0110.ASYNCH 10 BITSICHAR
0111=ASYNCH 11 BITSICHAR
ll00.FSK BELL 103 OR 202

O=ENABLE
l=DISABLE

O=DISABLE
TXA OUTPUT
l=ENABLE
TXAOUTPUT

IN 212, 103 MODES:
O=ANSWER
l=ORIGINATE
IN 202 MODE:
O.RECEIVE @ 1200 BIT/S,
TRANSMIT @ 150 BIT/S
1.RECEIVE@ 150 BIT/S,
TRANSMIT @ 1200 BIT/S

O=NORMAL
O=XTAL
O=NORMAL
1=BYPASS
1-16 X DATA
l=RESET
SCRAMBLER
RATE OUTPUT
l=ADD EXTRA
ATCLK PIN IN
PHASE Ea.
DPSK MODE ONLY
IN 202 ONLY

0=900 HZ SCT TONE IF
0=1%
IN ANSWER MODE
1=2.5%
.2225 HZ ANSWER TONE
O=NORMAL OPERATION
IN 103 OR 212 ORIGINATE
l=FULL DUPLEX IN 202 MODE
MODES
l=FSK MARK

OOXX.73K212L, 322L, 321 L
01 XX-73K221 L, 302L
10XX.73K222L
ll00-73K224L
1110.73K324L
1101.73K312L

3-156

SSI73K302L
Bell 212A, 103,202
Single-Chip Modem

II

CONTROL REGISTER 0

07
CRO
000

MOOUL.
OPTION

BIT NO.
DO

04

05

03

02

01

DO

TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT
MODE 3
MOOE2
MODE 1
MODE 0
ENABLE

ANSWER/
ORIGINATE

NAME

CONDITION

DESCRIPTION

Answer/
Originate

0

Selects answer mode in 103 and 212A modes (transmit in high band, receive in low band) or in Bell 202
mode, receive at 1200 bit/s and transmit at 150 biVs.

1

Selects originate mode in 103 and 212A modes (transmit in low band, receive in high band) or in Bell 202
mode, receive at 150 bit/s and transmit at 1200 bit/so
Note: This bit works with TR bit DO to program special
tones detected in Tone Register. See detect and tone
registers.

01

IIs~nIRS

0

Transmit
Enable

1

transmit output at TXA

Enables transmit output at TXA.
Note: Answer tone and OTMF TX control require TX
enable.

05,04,03,
02

Transmit
Mode

0

0

0

0

Selects power down mode. All functions disabled
except digital interface.

0

0

0

1

Internal synchronous mode. In this mode TXCLK is an
internally derived 1200 Hz Signal. Serial input data
appearing at TXO must be valid on the rising edge of
TXCLK. Receive data is clocked out of RXO on the
falling edge of RXCLK.

0

0

1

0

External synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internallyto EXCLK pin, and a 1200 Hz ± 0.01% clock must
be supplied externally.

0

0

1

1

Slave synchronous mode. Same operation as other
synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.

0

1

0

0

Selects OPSK asynchronous mode - 8 bits/character
(1 start bit, 6 data bits, 1 stop bit).

0

1

0

1

Selects OPSK asynChronous mode - 9 bits/character
(1 start bit, 7 data bits, 1 stop bit).

0

1

1

0

Selects OPSK asynchronous mode - 10 bits/character
(1 start bit, 8 data bits, 1 stop bit).

0

1

1

1

Selects OPSK asynchronous mode - 11 bits/character
(1 start bit, 8 data bits, Parity and 1 or 2 stop bits).
II.

3-157

I

SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
CONTROL REGISTER 0 (Continued)

D7
CRO
000

D5

TRANSMIT TRANSMIT
MODE 3
MODE 2

MODUL.
OPTION
NAME

BIT NO.

D4

CONDITION

D2

D3

D1

TRANSMIT TRANSMIT TRANSMIT
MODE 1
MODE 0
ENABLE

D7

ANSWER/
ORIGINATE

DESCRIPTION

~-------+--------~------------~-------~-------------

D7 D5 D4

DO

"0."

Selects:
~c:vn('''lrnrlnl

Modulation
Option

S

mode at 1200 biVs.

CONTROL REGISTER 1

CR1
001

BIT NO.

D7

D6

D5

D4

D3

D2

D1

DO

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

ENABLE
DETECT
INTER.

BYPASS
SCRAMB/
ADD
PH. EO.

ClK
CONTROL

RESET

TEST
MODE
1

TEST
MODE

NAME

CONDITION

a

DESCRIPTION

D1 DO
D1,DO

Test Mode

0

0

Selects normal operating mode.

0

1

Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable must be forced
low. Not supported in FDX202 mode.

1

0

Selects remote digital loopback. Received data is
looped back to transmit data internally, and RXD is
forced to a mark. Data on TXD is }gnored.

1

1

Selects local digital loopback. Internally loops TXD
back to RXD and continues to transmit carrier from
TXA pin.
-

D2

Reset

0

Selects normal operation.

1

Resets modem to power down state. All control
register bits (CRO, CR1, Tone) are reset to zero. The
output of the ClK pin will be set to the crystal
frequency.

3-158

SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
CONTROL REGISTER 1 (Continued)

CR1
001

BIT NO.
03

04*

05

07

06

05

04

03

TRANSMIT
PATTERN
1

TRANSMIT
PAITERN
0

ENABLE
DETECT
INTER.

BYPASS
SCRAMB/
ADD
PH. Ea.

ClK
CONTROL

NAME

CONDITION

ClK Control

02

01

DO

RESET

TEST
MODE
1

TEST
MODE
0

DESCRIPTION

0

Selects 11.0592 MHz crystal echo output at ClK
pin.

1

Selects 16 X the data rate, output at ClK pin in OPSK
modes only.

Bypass
Scrambler/
Add Phase
Equalization

0

Selects normal operation. OPSK data is passed
through scrambler.

1

Selects Scrambler Bypass. OPSK data is routed
around scrambler in the transmit path. In Bell 202
mode, additional phase equalization is added to the
main channel filters when 04 is set to 1.

Enable Detect
Interrupt

0

Disables interrupt at INT pin.

1

Enables INT output. An interrupt will be generated with
a change in status of DR bits 01-04. The special tone
and call progress detect interrupts are masked when
the TX enable bit is set. Carrier detect is masked when
TX OTMF is activated. All interrupts will be disabled if
the device is in power down mode.

07 06
07,06

Transmit
Pattern

0

0

Selects normal data transmission as controlled
by the state of the TXO pin.

0

1

Selects an alternating mark/space transmit pattern for
modem testing.

1

0

Selects a constant mark transmit pattern.

1

1

Selects a constant space transmit pattern.

* 04 should always be set to 1 when receiving 1200 bitls data and to 0 when transmitting 1200 bitls data in
202 mode.

3-159

I

SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
DETECT REGISTER

DR
010
BIT NO.

DO

01

NAME

CONDITION

Long Loop

o

DESCRIPTION

Indicates normal received signal.

Call Progress
0
No call progress tone detected.
Detect
I--------+--In-d-ic-a-te-s-p-r-es-e-n-c-e-o-f-c-al-I-p-ro-g-re-s-s-to-n-e-s-.-T-h-e-c-a-II~
progress detection circuitry is activated by energy in
the normal 350 to 620 Hz call progress band.

02

Special Tone
Detect

o

No special tone detected as programmed by
CRO bit DO and Tone Register bit DO.
(1) 2225 Hz answer tone if DO of TR=O and the device
is in Bell 103 or 212A originate mod/3.
(2) Soft carrier turn-off tone if DO of TR=O and the

device is in Bell 202 answer mode.
(3) an FSK mark in the mode the device is set to

receive if DO of TR is set to 1 .

03

Carrier Detect l---~---L-~~~~~~~~~~~~~~~---I
Indicated carrier has been detected in the received
channel.

04

Unscrambled
Mark
I--------+--(D-P-S-K-o-nl-y)-In-d-ic-a-te-s-d-e-te-c-tio-n-o-f-u-n-sc-r-am--bl-ed--~

05

Detect

marks in the received data. A valid indication requires
that unscrambled marks be received for> 165.5 ±
6.5 ms.

Receive
Data

Continuously outputs the received data stream.
This data is the same as that output on the RXD pin, but
it is not disabled when RXD is tri-stated.

06,07

3-160

SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
TONE REGISTER

TR
011

07

06

05

04

03

02

D1

DO

RXO
OUTPUT
CONTR.

TRANSMIT
SOFT
CARRIER
TURN-OFF
TONE

TRANSMIT
ANSWER
TONE

TRANSMIT
OTMF

OTMF3

OTMF 21
202
FOX

OTMF 11
OVERSPEED

OTMF 01
SPECIAL
TONE SEL

BIT NO.

NAME

DESCRIPTION

CONDITION
05 04 DO

DO

OTMF 01
Special Tone

DO interacts with bits 06, D4, and CRO as shown.

0

1

X

Transmit OTMF tones.

0

0

0

2225 Hz answer tone will be detected in 02 of DR if
originate mode is selected in CRO.
900 Hz SCT tone will be detected in 02 of DR if Bell 202
answer mode is selected in CRO.

Detect/Select
X

0

1

Mark of an FSK mode selected in CRO is to be detected
in 02 of DR.

1

0

0

2225 Hz answer tone will be generated when in
answer mode and transmit enable is selected in CRO.

1

0

1

2100 Hz answer tone will be generated when in
answer mode and transmit enable is selected in CRO.
01 interacts with 04 as shown.

04 01
01

02

OTMF 11
Overspeed

0

0

Asynchronous DPSK 1200 bitls _+1.0% -2.5%.

0

1

Asynchronous OPSK 1200 bitls +2.3% -2.5%.

OTMF2/202T
FOX

0

Enables 202 half-duplex operation if 04=0

1

Enables 202 full-duplex operation if 04=0

03 02 01 DO
03,02,
01,00

OTMF 3,
2,1,0

0
1

0
1

0 01 1

Programs 1 of 16 DTMF tone pairs that will be
transmitted when TX OTM F and TX enable bit (CRO, bit
D1) are set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT

1

1

0

0

2

0

0

0
1

3
4

0
0

0
1

1

1

0

0
0

1
1

0
1

1

0
1
1

0
1

0

0

5
6
7

_..

0

TONES
LOW HIGH
697
697
697
770
770

1209
1336
1477
1209
1336
1477

0
1

770
852

1209

852
852

1336
1477

941

1336

9

1

0

0

0
1

0

1

0

1

0

8

3-161

DTMF CODE
D3 D2 D1 DO

I

SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
TONE REGISTER

TR
011

(Continued)

07

06

05

04

03

02

01

DO

RXO
OUTPUT
CONTR.

TRANSMIT
SOFT
CARRIER
TURN-OFF
TONE

TRANSMIT
ANSWER
TONE

TRANSMIT
DTMF

DTMF3

DTMF 21
202T
FOX

DTMF 11
OVERSPEED

OTMF 01
SPECIAL
TONE SEL

BIT NO.

NAME

CONDITION

DESCRIPTION
KEYBOARD
EQUIVALENT

03,02,
01,00
(cont.)

DTMF CODE
03 02 01 DO

TONES
LOW HIGH

*

1

0

1

1

941

1209

#

1

1

0

Q

941

1477

A

1

1

1

697

1633

B

1

1

0
1

770
0
-----_.-

1633

C

1

1

1

1

852

1633

0

0

0

0

0

941

1633

Transmit
DTMF

0

Disable DTMF.

1

Activate OTMF. The selected DTMF tones are
transmitted continuously when this bit is high.
TX DTMF overrides all other transmit functions.

Transmit
Answer Tone

0

Disables answer tone generator.

1

Enables answer tone generator. A 2225 Hz
answer tone will be transmitted continuously when the
transmit enable bit is set. To transmit answer tone, the
device must be in answer mode.

06

Transmit
SCT Tone

0

Disables SCT tone generator.

1

Transmit SCT tone in Bell 202 mode.

07

RXD Output
Control

0

Enables RXD pin. Receive data will be output on
RXD.

1

Disables RXD pin. The RXD pin reverts to a high
impedance with internal weak pul_~~up resistor.

04

05

, " Notes for Tone Register use:
1.

To detect SCT tone, 202 answer mode must be selected. To transmit SCT tone, 202 originate mode must
be selected.

2.

For answer tone detection, 103 or 212 originate mode must be active. To transmit answer tone, the
73K302 must be in 103 or 212 answer mode.

3.

After completion of DTMF dialing, bit 02 should be reset unless 202 full-duplex mode is selected.

3-162

SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
10 REGISTER

10

07

06

05

04

10

10

10

10

110

BIT NO.

NAME

07,06

Device
Identification

CONDITION

DESCRIPTION
Indicates Device:

07 06 05 04

Signature

I

ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING

PARAMETER
VOO Supply Voltage

14V

Storage Temperature

-65 to 150°C

Soldering Temperature (10 sec.)

260°C

Applied Voltage

-0.3 to VDD+0.3V

--_ ..

---_.--

Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
PARAMETER

CONDITIONS

VDO Supply voltage
TA, Operating Free-Air Temp.
Clock Variation

(11.0592 MHz) Crystal or external clock

MIN

NOM

MAX

UNITS

4.5

5

5.5

V

-40

+85

°C

-0.01

+0.01

%

2.2

MQ

External Components (Refer to Application section for placement.)
_ _ 0-

VREF Bypass Capacitor

(External to GNO)

0.1

Bias setting resistor

(Placed between VDD and ISET pins)

1.8

ISET Bypass Capacitor

(ISET pin to GNO)

0.1

VDO Bypass Capacitor 1

(External to GNO)

0.1

VDO Bypass Capacitor 2

(External to GND)

22

XTL 1 Load Capacitor

Depends on crystal characteristics;

40

XTL2 Load Capacitor

from pin to GND

20

J.1F
2

J.1F
-

3-163

--

--~-

J.1F

-------

J.1F

,---

pF

SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)
PARAMETER

100, Supply Current
IDDA, Active
IDD1, Power-down
IDD2, Power-down

CONDITIONS
ISET Resistor

MIN

NOM

MAX

UNITS

8

12

rnA

= 2 MQ

= 11.0592 MHz
ClK = 11 .0592 MHz
ClK = 19.200 kHz
ClK

4

mA

3

mA

Digital Inputs
VIH, Input High Voltage
Reset, XTl1 , XTl2

3.0

VDD

V

All other inputs

2.0

VDD

V

0

0.8

V

100

~

Vll, Input low Voltage

Reset Pull-down Current

= VIH Max
VI = Vil Min
Reset = VDD

Input Capacitance

All Digital Input Pins

IIH, Input High Current
Ill, Input low Current

VI

~

-200
1

50

~

10

pF

VDD

V

0.4

V

0.6

V

-50

~

15

pF

Digital Outputs
VOH, Output High Voltage

10H MIN

= -0.4 rnA

2.4

= 1.6 mA

VOL, Output low Voltage

10 MAX

VOL, ClK Output

10 = 3.6 mA

= GND

RXD Tri-State Pull-up Curro

RXD

CMAX, ClK Output

Maximum Capacitive load

-1

Capacitance
Inputs

Capacitance, all Digital Input pins

XTl1, 2 load Capacitors

Depends on crystal

ClK

Maximum Capacitive load

3-164

15

10

pF

60

pF

15

pF

SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = Recommended range unless otherwise noted.)
PARAMETERS

CONDITIONS

MIN

NOM

DPSK Modulator
Carrier Suppression

Measured at TXA

45

Output Amplitude

TX scrambled marks

-11

-T~-

MAX

--T

UNITS

dB

-10 ---

-9

dBmO

~-'-.~

FSK Modulator

= 11.0592 MHz

-0.35

+0.35

%

Do~

-11

-10

-9

dBmO

-11.9

-10.9
---

-9.9

dBmO

Output Freq. Error

elK

Transmit level

Transmit

Pattern

Soft Carrier Turnoff Tone
Harmonic Distortion
in 700-2900 Hz band

-60

THO in the alternate band
DPSK or FSK

Output Bias Distortion

Transmit Dotting Pattern
In AlB@ RXD

Total Output Jitter

Random Input in ALB @ RXD

--

-50
--

-~

dB
----

%

±3
-10

+10

%

--.-~----

DTMF Generator

Must not be in 202 mode

Freq. Accuracy

--

-0.25

+0.25

%

Output Amplitude, Low group

DPSK mode

-10

-9

-8

dBmO

Output Amplitude, High group

DPSK mode

-8

-7

-6

dBmO

Twist

High-Band to low-Band

1.0

2.0

3.0

dB

Long Loop Detect

With Sinusoid

-38

-28

dBmO

Dynamic Range

Refer to Performance Curves

Note:

--

---

45

-------

Parameters expressed in dBmO refer to the following definition:
5V Version:
o dB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.

3-165

dB

I

SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
CONDITIONS

MIN

Detect Level

-3 dB points in 285 and 675 Hz

-38

PARAMETERS

NOM

MAX

UNITS

Call Prog ress Detector
dBmO

Reject Level

Test signal is a 460 Hz sinusoid

-45

dBmO

Delay Time

-70 dBmO to -30 dBmO STEP

20

40

ms

Hold Time

-30 dBmO to -70 dBmO STEP

20

40

ms

2

Hysteresis

dB

Carrier Detect
Threshold

DPSK or FSK receive data

-49

-42

dBmO

Delay Time
Bell 103

8

20

ms

Bell 212A

15

32

ms

Bell 202 Forward Channel

6

12

ms

Bell 202 Back Channel

25

40

ms

Bell 103

6

20

ms

Bell 212A

10

24

ms
ms

Hold Time

Bell 202 Forward Channel

3

8

Bell 202 Back Channel

10

25

ms
dB

2

Hysteresis
Special Tone Detectors
Detect Level

See definitions for
TR bit DO mode

-49

-42

dBmO

10

25

ms

Delay Time
Answer tone

4

10

ms

202 Main Channel Mark

10

25

ms

202 Back Channel Mark

20

65

ms

1270 or 2225 Hz marks

10

25

ms

900 Hz SCT tone

Preceded by valid carrier*

* If SCT duration >4ms, it is guaranteed to detect.

3-166

SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS

CONDITIONS

MIN

NOM

MAX

UNITS

Special Tone Detectors (Continued)
~~-

Hold Time

--

Answer tone

4

900 Hz SCT tone

1

--.-

15

ms

10

ms

202 Main Channel Mark

3

10

ms

202 Back Channel Mark

10

25

ms

1270 or 2225 Hz marks

5

15

ms

----.~.---

2

Hysteresis
Detect Freq. Range

Any Special Tone

dB

-3

----.---

-~-~-~

+3

%

Output Smoothing Filter
kQ

Output load

TXA pin; FSK Single
Tone out for THO = -50 dB
in 0.3 to 3.4 kHz

10

Out of Band Energy

Frequency> 12 kHz in all modes
See Transmit Energy Spectrum

Output Impedance

TXA pin

20

50

Q

Clock Noise

TXA pin; 76.8 kHz or 122.88 kHz
in 202 main channel

0.1

0.4

mVrms

------

50

pF

-60

dBmO

CarrierVCO
Capture Range

Originate or Answer

Capture Time

-10Hz to +10 Hz Carrier
Frequency Change

-10

+10

Hz

100

ms

+625

ppm

50

ms

~~-

40
----------

DPSK Recovered Clock
---r--~-~--~~

Capture Range

-625

% of data rate
(center at 1200 Hz)

Data Delay Time

Analog data in at RXA pin to
receive data valid at RXD pin

30
~-.------.--

Tone Generator
Tone Accuracy

DTMF or FSK tones

-5

+5

Hz

Tone Level

For DTMF, must not be in 202 mode

-1

+1

dB

3-167

I

SSI73K302L
Bell 212A, 103, 202

Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS

MIN

CONDITIONS

NOM

MAX

UNITS

Timing (Refer to Timing Diagrams)

*

TAL

CS/Addr. setup before ALE Low

TLA

CS/Addr. hold after ALE Low

25
20

TLC

ALE Low to RDIWR Low

30
-5
0

TCL

RD/WR Control to ALE High

TRD

Data out from RD Low

TLL

ALE width

TRDF

Data float after RD High

TRW

RDwidth

TWW

WRwidth

TDW

Data setup before WR High

30
0
200
140
40
10'

TWD

Data hold after WR High

TCKD

Data out after EXCLK Low

TCKW

WR after EXCLK Low

150

TDCK

Data setup before EXCLK Low

150

TAC

Address setup before control*

TCA

Address hold after control*

TWH

Data Hold after EXCLK

50
50
20

Control for setup is the falling edge of RD or WR.
Control for hold is the falling edge of RD or the rising edge of WR.

3-168

ns
ns

---

ns

-----

ns

--

--

140
_._---

ns
ns

5
25000
25000

ns
ns
ns
ns

- 1--

ns

200

ns
ns

-----

ns
ns
ns

--- ----

SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)

~

ALE

~_ _ _ _ _ _ __
TLC
TLC

I T~D

~

TAL

ADO-AD7

- { ADDRESS >l-------K READ DATA>l-------K ADDRESS >l-------K WRITE DATA}---

______

Cs~~-_ _-~~_ _ _ _ _ _-~~_ _~i-

READ TIMING DIAGRAM (SERIAL VERSION)
EXCLK

I~--~----------~

RD

AO-A2

DATA

--+

WRITE TIMING DIAGRAM (SERIAL VERSION)
EXCLK

HTWW

-----+--------------------------------------~--,i

TCKW

I~

AO-A2 - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + .

DATA

3-169

I ~
TCA

I

SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
APPLICATIONS INFORMATION
GENERAL CONSIDERATIONS
Figures 1 and 2 show basic circuit diagrams for
K-Series modem integrated circuits. K-Series products
are designed to be used in conjunction with a control
processor, a UART or RS-232 serial data interface,
and a OAA phone line interface to function as a typical
intelligent modem. The K-Series ICs interface directly
with Intel 8048 and 80C51 microprocessors for control
and status monitoring purposes.Two typical OAA arrangements are shown: one for a split ±5 or ±12
volt design and one for a single 5V design. These
diagrams are for reference only and do not represent
production-ready modem designs.

In most applications the contro"erwill monitorthe serial
data for commands from the OTE and the received
data for break signals from the far end modem. In this
way, commands to the modem are sent overthe same
line as the transmitted data. In other applications the
RS-232 interface handshake lines are used for modem
control.

+ C8

C9
.1 nF

CA
CB ' ./1, ..........

K-Series devices are available with two control interface versions: one for a para"el multiplexed address/
data interface, and one for a serial interface. The
para"el version is intended for use with 8039/48 or
8031/51 microcontro"ers from Intel or many other
manufacturers. The serial interface 22-pin version can
be used with other microcontro"ers or in applications
where only a limited number of port lines are available
or the application does not lend itself to a multiplexed
address/data interface. The para"el versions may also
be used in the serial mode, as explained in the data
sheet pin description.

22nF

C1
390pF

---.J

CC

CD

wri

I-I>'~':"""""

ALE
~

CF

SSI
K-SERIES

RXA

I-.--H-----~kCM

LOW
POWER

FAMILY
BA

f'::>-I~+--I---+--lf---t--!

BB
DA
DO
DB

US.U6

RESET

MC145406

f

R9

.5

10K

~

FIGURE 1: Basic Box Modem with Dual-Supply Hybrid

3-170

22K

VRI
MOV
V250L20

SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
signals will clip if a single-ended drive approach is
used. The bridged driver uses an extra op-amp (U1 A)
to invert the signal coming from the gain setting op-amp
(U1 B) before sending it to the other leg of the transformer. Each op-amp then supplies half the drive signal
to the transformer. The receive amplifier (U1C) picks
off its signal at the junction of the impedance matching
resistor and the transformer. Because the bottom leg
of the transformer is being driven in one direction by
U1A and the resistor is driven in the opposite direction
at the same time by U 1 B, the junction of the transformer
and resistor remains relatively constant and the receive signal is unaffected.

DIRECT ACCESS ARRANGEMENT (DAA)
The telephone line interfaces show two examples of
how the "hybrid" may be implemented. The split supply
design (Figure 1) is a typical two op-amp hybrid. The
receive op-amp serves two purposes. It supplies gain
to amplify the receive signal to the proper level for the
modem's detectors and demodulator, and it removes
the transmitted signal from the receive signal present
at the transformer. This is done by supplying a portion
of the transmitted signal to the non-inverting input of
the receive op-amp at the same amplitude as the signal
appearing at the transformer, making the transmit
signal common mode.

DESIGN CONSIDERATIONS

The single-supply hybrid is more complex than the
dual-supply version described above, but its use eliminates the need for a second power supply. This circuit
(Figure 2) uses a bridged drive to allow undistorted
signals to be sent with a single 5V supply. Because
DTMF tones utilize a higher amplitude than data, these

Silicon Systems' 1-chip modem products include all
basic modem functions. This makes these devices
adaptable for use in a variety of applications, and as
easy to control as conventional digital bus peripherals.

CI
390pF

R4

37.4K 1%

RI
C3

201< 1%

• Note: Op-amp U1
must be rated for
single 5V operation.
R10 & R11 values
depend on Op-amp
used.

0.1nf'

<1§--11----~

R2

201< 1%

R3
4751%

R6
22.1K

C6
0.1 nf'

R7
20K 1%

C5
750 pF

~~~~~~~--~
VRI

R9

MOV

20KI%

V25OL20

K~.

VOLTAGE
REFERENCE

HOOK

_

>--__________----.J

RI~ ~--------------------------------~

FIGURE 2: Single 5V Hybrid Version
3-171

I

SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
Unlike digital logic circuitry, modem designs must
properly contend with precise frequency tolerances
and very low level analog signals, to ensure acceptable
performance. Using good analog circuit design practices will generally result in a sound design. Following
are additional recommendations which should be
taken into consideration when starting new designs.
CRYSTAL OSCILLATOR
The K-Series crystal oscillator requires a parallel mode
(antiresonant) crystal which operates at 11.0592 MHz.
It is important that this frequency be maintained to
within ±O.01% accuracy.
In orderfor a parallel mode crystal to operate correctly
and to specification, it must have a load capacitor
connected to the junction of each of the crystal and
internal inverter connections, terminated to ground.
The values of these capacitors depend primarily on the
crystal's characteristics, and to a lesser degree on the
internal inverter circuit. The values used affect the
accuracy and start up characteristics of the oscillator.
LAYOUT CONSIDERATIONS
Good analog/digital design rules must be used to
control system noise in orderto.obtain highest performance in modem designs. The more digital circuitry
present on the PC board, the more this attention to
noise control is needed. The modem should be treated
as a high impedance analog device. A 22 mF electrolytic capacitor in parallel with a 0.1 mF ceramic capacitor between VDD and GND is recommended. Liberal
use of ground planes and larger traces on power and
ground are also highly favored. High speed digital
circuits tend to generate a significant amount of EMI
(Electro-Magnetic Interference) which must be minimized in order to meet regulatory agency limitations.
To accomplish this, high speed digital devices should
be locally bypassed, and the telephone line interface
and K-Series device should be located close to each
other near the area of the board where the phone line
connection is accessed. To avoid problems, power
supply and ground traces should be routed separately
to the analog and digital functions on the board, and
digital signals should not be routed near low level or
high impedance analog traces. The analog and digital
grounds should only connect at one point near the
K-Series device ground pin to avoid ground loops. The
K-Series modem IC's should have both high frequency and low frequency bypassing as close to the
package as possible.
3-172

MODEM PERFORMANCE
CHARACTERISTICS
The curves presented here define modem IC performance under a variety of line conditions while inducing
disturbances that are typical of those encountered
during data transmission on public service telephone
lines. Test data was taken using an AEA Electronics'
"Autotest I" modem test set and line Simulator, operating under computer control. All tests were run fullduplex, using a Concord Data Systems 224 as the
reference modem. A 511 pseudo-random-bit pattern
was used for each data point. Noise was C-message
weighted and all signal-to-noise (SIN) ratios reflect
total power measurements simifar to the CCITT V.56
measurement specification. The individual tests are
defined as follows.
SER vs. SIN
This test measures the abifity of the modem to operate
over noisy lines with a minimum of data-transfer errors.
Since some noise is generated in the best of dial-up
lines, the modem must operate with the lowest SIN
ratio possible. Better modem performance is indicated
by test curves that are closest to the BER axis. A
narrow spread between curves representing the four
line parameters indicates minimal variation in performance while operating over a range of aberrant operating conditions. Typically, a DPSK modem will exhibit
better BER-performance test curves receiving in the
low band than in the high band.
SER vs. Receive Level
This test measures the dynamic range of the modem.
Because signal levels vary widely over dial-up lines,
the widest possible dynamic range is desirable. The
minimum Bell specification calls for 36 dB of dynamic
range. SIN ratios are held constant at the indicated
values while the receive level is lowered from a very
high to very low signal levels . The width of the "bowl" of
these curves, taken at the BER pOint, is the measure of
dynamic range.

SSI73K302L
Bell 212A, 103,202
Single-Chip Modem

SSI73K302L
BERvsS/N

\

I

\

~

\ \

~
a:
a:
0
a:
a:
w

10-4

\\\

10-3

'\

\

\

1\\ \1

t::

[FLATWiO}
EO.

1\\'
~

i~ ~
\

FLAT W/EO.

:\

I

\~ Kc~~rol\

10-5

~ RECEIVE LEVEL
-30 dBm

BELL 202 MODE

10-6

1\ \
I \~ ~f2WiEOI ~
I \\

\\

4

10

r"--'
FLAT

\\\

\\ \

10-5

,\

\

\

\

\

,\ \

~.

\\ \

\

12

I

~

\'\

III

\.

'c1;3002
-,--,

'\ ~~ - ; -

10-4

t::

\

11

~

~
a:
a:
0
a:
a:
w

3002W/O ]
EO.

C2

~'¥ H

W

1\

\\

III

\

~ ~ I--

\

1\

I\~
\~

W

DPS~2~6~1~~iION

\

~

\\

HIGH BAND RECEIVE}=:
-30 dBm

\ I

\\

'\~

10-3

SSI73K302L
BER vs SIN

14

16

10

SIGNAL TO NOISE (dB)

12

14

SIGNAL TO NOISE (dB)

SSI73K302L
BER vs PHASE JITTER

SSI73K302L
BER vs RECEIVE LEVEL

I HIGH
BAND RECEIVE
DPSK OPERATION

.1 HIGH
BAND RECEIVE ~
DPSK OPERATION
I
C2 LINE

I-

10-3

--

10-4

j

3002 11 .5 dB SIN
./

I

/'
l .--

SIN -10.8 dB

\

1I

10-5

b:::::: ::::: .--

",

./'
~

rr

1
C210.8 dB SIN ~ I-- I--

r-r-

SIN = 15dB

"10

-10

-20

-30

-40

-50

12

RECEIVE LEVEL (dBm)

16

PHASE JITTER (DEG.)

3-173

20

24

SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem

SSI73K302L
BER vs CARRIER OFFSET

II HIGH
BAND RECEIVE ~
DPSKOPERATION
10-3

I

I

I

\
C211.3dBSAII

:..- :..- ~
~

12

300211.8dBS/N

-

I

~-

\

I--V
r-

-- ---4

-8

-12

CARRIER OFFSET (HZ)

3-174

SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
PACKAGE PIN DESIGNATIONS

CAUTION: Use handling procedures necessary
for a static sensitive component.

(Top View)

ClK

GND

RXA
VREF

RXA

XTL2

VREF

ADO

RESET

AD1

ISET

AD2

RXClK

AD3

RXD

RXClK

AD4

TXD

RXD

AD5

cs

TXD

ADS

EXClK

EXClK

AD7

TXClK

TXCLK

ALE

INT

INT

WR

TXA

TXA

RD

VDD

RESET
ISET

A1

GND

XTl1

400-MII
22-Pin DIP

SOO-Mil
28-Pln DIP

4

3

2

1282726
25
24

8

PLCC PINOUTS
ARE THE SAME AS
THE 28-PIN DIP

23
22
21
20
19

12 13 14 15 16 17 18

28-Pin
PLCC

ORDERING INFORMATION
ORDER NO.

PART DESCRIPTION

PKG.MARK

SSI 73K302L with Parallel Bus Interface
28-Pin Dip

73K302L-IP

73K302L-IP

28-Lead PLCC

73K302L-IH

73K302L-IH

73K302SL-IP

73K302SL-IP

SSI 73K302L with Serial Interface
22-pin Dip

Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914
Protected by the following Patents (4,691,172) (4,777,453)
0194 - rev.

3-175

©1989 Silicon Systems, Inc.

I

Notes:

3-176

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem

January 1994

DESCRIPTION

FEATURES

The SSI 73K321 L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a CCITT V.23 and V.21 compatible modem,
capable of 0-300 bitls full-duplex or 0-1200 bitls ha.lfduplex operation over dial-up telephone lines. The
73K321 L provides 1200 bit/s operation in V.23 mode
and300biVsinV.21 mode. TheSSI73K321Laisocan
both detect and generate the 2100 Hz answer tone
needed for call initiation. The SSI 73K321 L integrates
analog, digital, and switched-capacitor array functions
on a single substrate,offering excellent performance
and a high level of functional integration in a single 28or 22-pin DIP configuration. The SSI 73K321 L operates from a single +5V supply with very low power
consumption.

•

The SSI 73K321 L includes the FSK modulator/demodulator functions, call progress and handshake
tone monitortest modes, and a tone generator capable
of producing DTMF, answer, calling tones. The
SSI 73K321 L is designed to appear to the systems
designer as a microprocessor peripheral, and will easily interface with popular one-chip microprocessors
(80C51 typical) for control of modem functions through
its 8-bit multiplexed address/data bus orvia an optional
serial control bus. An ALE control line simplifies address demultiplexing. Data communications occurs
(Continued)
through a separate serial port only.

•

•
•
•

•
•

One-Chip CCITT V.23 and V.21 standard
compatible modem data pump
Full-duplex operation at 0-300 bitls (V.21) or
0-1200 bitls (V.23) forward channel with or
without 0-75 bitsls back channel
Full Duplex 0-1200 bitls (V.23) in 4-wire mode
Pin and software compatible with other
SSI K-Series 1-chip modems
Interfaces directly with standard microprocessors (8048, 80C51 typical)
Serial or parallel microprocessor bus for
control
Serial port for data transfer

•

Call progress, carrier, precise answer tone
(2100 Hz), calling tone (1300 Hz) and FSK mark
detectors

•
•

DTMF generator
Test modes available: ALB, DL, RDL, Mark,
Space, Alternating bit patterns

•

Precise automatic gain control allows 45 dB
dynamic range
Space efficient 28-pin PLCC package available
CMOS technology for low power consumption
using 30 mW @ 5V from a single power supply

•
•

BLOCK DIAGRAM

PIN DIAGRAM
eLK

XTL1
XTL2
RD~
WR~

TXA

ALE~

ADO
AD1

cs~

RXA

RESET~

AD2
AD3

INT

0------4

SMART
DIALING

AD4

&

AD5

DETECT
TXDO--------I~

FUNCTIONS

RXDD---------!

ADS
AD7
ALE
WR

RD

0194 - rev.

3-177

I

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
DESCRIPTION (Continued)
The SSI 73K321 L is ideal for either free standing or
integral system modem applications where multi-standard data communications over the 2-wire switched
telephone network is desired. Typical uses include
videotex terminals, low-cost integral modems and
built-in diagnostics for office automation or industrial
control systems. The 73K321 L's high functionality, low
power consumption and efficient packaging simplify
design requirements and increase system reliability in
these applications. A complete modem requires only
the addition of the phone line interface, a control
microprocessor, and RS-232 level converter for a
typical system. The SSI 73K321 L is part of Silicon
Systems K-Series family of pin and function compatible single-chip modem products. These devices allow
systems to be configured for higher speeds and Bell or
CCITT operation with only a single component change.

OPERATION
FSK MODULATOR/DEMODULATOR

The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. V.21 mode uses 980 and
1180 Hz (0 riginate, mark and space) or 1650 and
1850 Hz (answer, mark and space). V.23 mode uses
1300 and 2100 Hz for the main channel and 390 and
450 Hzforthebackchannel. The modulation rate of the
back channel is up to 75 baud. Demodulation involves
detecting the received frequencies and decoding them
into the appropriate binary value.
PASSBAND FILTERS AND EQUALIZERS

High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay equalization and rejection of out-of-band signals in the
receive channel. Amplitude and phase equalization
are necessary to compensate for distortion of the
transmission line and to reduce intersymbol interference in the bandlimited receive Signal.
AGC

The automatic gain control maintains a signal level at
the input to the demodulators which is constant to

within 1 dB. It corrects quickly for increases in signal
which would cause clipping and provides a total
receiver dynamic range of >45 dB.
PARALLEL BUS INTERFACE

Four 8-bit registers are provided for control, option
select and status monitoring. These registers are addressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as four consecutive memory locations. Two control registers and the tone register are
read/write memory. The detect register is read only and
cannot be modified except by modem response to
monitored parameters. The parallel bus interface is not
available with the 22-pin package.
SERIAL COMMAND INTERFACE

The Serial Command mode allows access to the SSI
73K321 L control ~nd status registers via a serial
command port. In this mode the AO , A 1 and A2 lines
provide register addresses for data passed through the
data pin under control of the RD and WR lines. A read
operation is initiated when the RD line is taken low. The
first bit is available after RD is brought low and the next
seven cycles of EXCLK will then transfer out seven bits
of the selected address location LSB first. A write takes
place by shifting in eight bits of data LSB first for eight
consecutive cycles of EXCLK. WR is then pulsed low
and data transferred into the selected register occurs
on the rising edge of WR.
SPECIAL DETECT CIRCUITRY

The special detect Circuitry monitors the received
analog Signal to determine status or presence of carrier, answer tone and weak received signal (long loop
condition), special tones such as FSK marking and the
1300 Hz calling tone are also detected. A highly frequency selective call progress detector provides adequate discrimination to accurately detect European
call progress Signals.
DTMF GENERATOR

The DTMF generator will output one of 16 standard
tone-pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded illto the tone register. Dialing is initiated when the DTMF mode is selected using the tone register and the transmit enable
(CRO bit D1) is changed from 0 to 1.

3-178

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
PIN DESCRIPTION
POWER
NAME

28-PIN

22-PIN

TYPE

DESCRIPTION

GND

28

1

I

System Ground.

VDD

15

11

I

Power supply input, 5V ±1 0%. Bypass with 0.1 and 22 IJ-F
capacitors to GND.

VREF

26

21

0

An internally generated reference voltage. Bypass with
0.1 IJ-F capacitor to GND.

ISET

24

19

I

Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 MQ resistor. ISET should be bypassed to GND with a
0.1 IJ-F capacitor.

PARALLEL MICROPROCESSOR INTERFACE
12

-

I

Address latch enable. The falling edge of ALE latches the
address on ADO-AD2 and the chip_ select on CS.

4-11

-

I/O

Address/data bus. These bidirectional tri-state multiplexed lines carry information to and from the internal
registers.

CS

20

-

I

Chip select. A low during the falling edge of ALE on this pin
allows a read cycle or a write cycle to occur. ADO-AD7 will
not be driven and no registers will be written if CS (latched)
is not active. The state of CS is latched on the falling edge
of ALE.

ClK

1

2

0

Output clock. This pin is the output of the crystal oscillator
frequency only in the SSI 73K321 .

INT

17

13

0

Interrupt. This open drain output signal is used to inform the
processor that a detect flag has occurred. The processor
must then read the detect register to determine which
detect triggered the interrupt. INT will stay low until the
processor reads the detect register or does a full reset.

RD

14

-

I

Read. A low requests a read of the SSI 73K321 l internal
registers. Data cannot be output unless both RD and the
latched CS are active or low.

RESET

25

20

I

Reset. An active high signal high on this pin will put the chip
into an inactive state. All control register bits (CRO, CR1,
Tone) will be reset. The output of the ClK pin will be set to
the crystal frequency. An internal pull down resistor permits
power on reset using a capacitor to VDD.

ALE
ADO-AD7

3-179

I

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
PIN DESCRIPTION (Continued)
PARALLEL MICROPROCESSOR INTERFACE (Continued)
NAME
WR

28·PIN

22·PIN

TYPE

13

-

I

DESCRIPTION
Write. A low on this informs the SSI 73K321 L that data is
available on ADO-AD7 for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are low.

SERIAL MICROPROCESSOR INTERFACE
AO-A2

-

5-7

DATA

-

RD

WR

Note:

I

Register Address Selection. These lines carry register
addresses and should be valid during any read or write
operation.

8

I/O

Serial Control Data. Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs data.

-

10

I

Read. A low on this input informs the SSI 73K321 L that
data or status information is being read by the processor.
The falling edge of the RD signal will initiate a read from the
addressed register. The RD signal must continue for eight
falling edges of EXCLK in order to read all eight bits of the
referenced register. Read data is provided LSB first. Data
will not be output unless the RD signal is active.

-

9

I

Write. A low on this input informs the SSI73K321 L that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on
the DATA pin for eight consecutive falling edges of EXCLK
and then to pulse WR low. Data is written on the rising edge
ofWR.

In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the
pins; AO, A 1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.
The Serial Control mode is provided in the 28-pin version by tying ALE high and CS low. In this
configuration AD7 becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2, respectively.

3-180

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
DTE USER INTERFACE
NAME

28·PIN

22·PIN

TYPE

EXCLK

19

15

I

External Clock. Used for serial control interface to clock
control data in or out of the 73K321 L.

RXCLK

23

18

0

Receive Clock. Aclockwhich is 16x1200,or16x 75 in V.23
mode, or 16 x 300 baud data rate is output in V.21.

RXD

22

17

0

Received Digital Data Output. Serial receive data is available on this pin. The data is always valid on the rising edge
of RXCLK when in Synchronous mode. RXD will output
constant marks if no carrier is detected.

TXCLK

18

14

0

Transmit Clock. TXCLK is always active. In V.23 mode the
output is either a 16 x 1200 baud clock or 16 x 75 baud, in
V.21 mode the clock is 16 x 300 baud.

TXD

21

16

I

Transmit Digital Data Input. Serial data for transmission is
input on this pin. In Asynchronous modes (1200 or 300
baud) no clocking is necessary.

DESCRIPTION

ANALOG INTERFACE AND OSCILLATOR
RXA

27

22

I

Received modulated analog signal input from the phone
line.

TXA

16

12

0

Transmit analog output to the phone line.

XTL1
XTL2

2
3

3
4

I

These pins are for the internal crystal oscillator requiring
a 11.0592 MHz Parallel mode crystal and two load capacitors to Ground. XTL2 can also be driven from an external
clock.

I

3-181

I

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
REGISTER DESCRIPTIONS
Four 8-bH internal registers are accessible for control
and status monitoring. The registers are accessed in
read or wrHe operations by addressing the AO and A 1
address lines in Serial mode, orthe ADO and AD1 lines
in Parallel mode. The ADO and AD1 lines are latched by
ALE. Register CRO controls the method by which data
is transferred over the phone line. CR1 controls the

interface between the microprocessor and the
SSI73K321L internal state. DR is a detect register
which provides an indication of Monitored modem
status conditions. TR, the tone control register, controls the DTM F generator, answer and guard tones and
RXD output gate used in the modem initial connect
sequence. All registers are read/write except for DR
which is read only. Register control and status bits are
identified below:

REGISTER BIT SUMMARY

CRO

CQIITROL
REGISTER
1

CR1

001

CLK
CQIITROL

RESET

TEST
MODE
1

TEST
MODE
0
LONG
LOOP

DETECT
REGISTER

DR

010

CARRIER
DETECT

SPECIAL
TQIIE

CALL
PROGRESS

TQIIE
CQIITROL
REGISTER

TR

011

DTMF3

DTMF2!
V.23 FOX

DTMF1

CQIITROL
REGISTER
2

CR2

100

CQIITROL
REGISTER
3

CR3

101

ID

110

ID
REGISTER

NOTE:

When a register containing reserved
control bits is written into, the reserved bits
must be programmed as O's.

3-182

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
REGISTER ADDRESS TABLE

0.V.23 FSK
1.V.21 FSK

OOOO.PWR DOWN _ _ _ _ _ _ _ _---'
lloo=FSK
0ool.TRANSMIT DTMF, CALL PROGRESS DETECTION

O=DISABLE
TXA OUTPUT
l=ENABLE
TXA OUTPUT

IN V.21 MODE:
O.ANSWER
1.0RIGINATE
IN V.23 MODE
O.RECEIVE @ 1200 BITIS,
TRANSM IT @ 75 BITIS
l=RECEIVE @ 75 BITIS,
TRANSMIT @ 1200 BITIS

I
O.HALF DUPLEX V.23
1.ALLOWS V.23 FULL
DUPLEX OPERATION

OOXX.73K212L. 322L. 321L
01XX.73K221L.302L
10XX.73K222L
ll00.73K224L
1110.73K324L
1101.73K312L

3-183

O.ANSWER TONE FREO .•2225 Hz
FSK MARK WILL BE INDICATED
BY SPECIAL TONE BIT IN DR
1.ANSWER TONE FREO .•2100 Hz
EITHER 2100 Hz (IN ORIG.) OR
1300 Hz (IN ANS.) WILL BE
INDICATED BY SPECIAL TONE
BIT IN DR

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
CONTROL REGISTER 0
05
TRANSMIT
MOOE3

CRO
000
BIT NO.
DO

NAME

CONDITION

Answer/
Originate

o

DESCRIPTION
Selects Answer mode in V.21 (transmit in high band,
receive in low band) or in V.23 mode, receive at
1200 biVs and transmit at 75 bit/s.
Selects Originate mode in V.21 (transmit in low band,
receive in high band) or in V.23 mode, receive at 75 biVs
and transmit at 1200 bit/s. If in V.23 and 02 of TR=1,
selects V .23 full duplex operation in 4-wire configuration.
Note: This bit works with TR bit DO to program special
tones detected in Tone Register. See detect and tone
registers.

01

Transmit
Enable

05,04,03,

Transmit
Mode

02
02

ects Power Down mode. All functions disabled except
ital interface.

06
07
FSK CCITT V.23 mode.
FSK CCITT V.21 mode.

3-184

SSI73K321L
celTT V.23, V.21
Single-Chip Modem
CONTROL REGISTER 1

CR1
001
BIT NO.
01, DO

02

07

06

05

04

03

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

ENABLE
DETECT
INTER.

ADD
PH. Ea.

ClK
CONTROL

NAME

CONDITION

Test Mode

01 DO

02

01

DO

RESET

TEST
MODE
1

TEST
MODE
0

DESCRIPTION

0

0

Selects Normal Operating mode.

0

1

Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable must be forced low.

1

0

Selects remote digitalloopback. Received data is looped
back to transmit data internally, and RXO is forced to a
mark. Data on TXO is ignored.

1

1

Selects local digitalloopback. Internally loops TXO back
to RXO and continues to transmit.data from TXA pin.

Reset

0

Selects normal operation.

1

Resets modem to power down state. All control register
bits (CRO, CR1, Tone) are reset to zero. The output of the
clock pin will be set to the crystal frequency.
Not supported in the SSI 73K321.See the TXClK and
RXClK pin descriptions for 16x t~e data rate clocks.

03

ClK Control
(Clock Control)

Program as
0

04

Add Ph. Eq.

0

Selects normal equalization.

1

In V.23 mode, additional phase equalization is added to
the main channel filters when 04 is set to 1.

0

Disables interrupt at INT pin. All interrupts are
normally disabled in Power Down modes.

1

Enables INT output. An interrupt will be generated with
a change in status of DR bits 01-03. The special tone and
call progress detect interrupts are masked when the TX
enable bit is set. Carrier detect is masked when TX OTM F
is activated. All interrupts will be disabled if the device is
in Power Down mode.

05

Enable Detect
Interrupt

--.-----~.--.--

07, 06

07 06
Transmit
Pattern

0

0

Selects normal data transmission as controlled by the
state of the TXO pin.

0

1

Selects an alternating mark/space transmit pattern for
modem testing.

1

0

Selects a constant mark transmit pattern.

1

1

Selects a constant space transmit pattern.

3-185

I

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
DETECT REGISTER

DR
010

DO

Long Loop

D1

Call Progress
Detect

D2

Special Tone
Detect

D2

D1

DO

SPECIAL
TONE

CALL
PROG.

LONG
LOOP

0

(1 ) 2100 Hz answertorie if DO of TR=1 and the device is
in V.21 Originate mode.
(2) 1300 Hz calling tone if DO of TR=1 and the device is
in V.21 or V.23 Answer mode.
(3) an FSK markforthe mode the device is setto receive
in if DO of TR = O.

D3

Carrier Detect

D5

Receive
Data

D6,D7

Continuously outputs the received data stream. This
data is the same as that output on the RXD pin, but it is
not disabled when RXD is tri-stated.
Not used.

3-186

SSI73K321L
celll V.23, V.21
Single-Chip Modem
TONE REGISTER

TR
011

07

06

05

04

03

02

01

RXO
OUTPUT
CONTR.

TRANSMIT
CALLING
TONE

TRANSMIT
ANSWER
TONE

TRANSMIT
OTMF

OTMF3

OTMF2

OTMF 1

BIT NO.
00

00
OTMF 01
ANS. TONEI
SPECIAL
TONEI SEL

NAME

CONDITION

OTMF 01
Answer Tonel

06 05 04 00

00 interacts with bits 06, OS, 04, and CRO as shown.

X

X

1

Transmit OTMF tones.

Special Tonel
OetectiSe lect

X

X

a a

Mark of an FSK mode selected in CRO is to be detected
in D2 of DR.

X

X

a

2100 Hz answer tone will be detected in D2 of DR if V.21
Originate mode is selected in CRO.

X

DESCRIPTION

--~---

1

1300 Hz calling tone will be detected in D2 of DR if V.21
or V.23 Answer mode is selected in CRO.
X

1

X

1

a a
a 1

Transmit 2225 Hz answer tone in Answer mode.
Transmit 2100 Hz answer tone in -Answer
mode.
--~

D3 D2 D1 DO
D3, D2,
01,00

DTMF 3,
2,1,0

a a a
1

1

1

01

Programs 1 of 16 DTMF tone pairs that will be
transmitted when TX DTMF and TX enable bit (CRO, bit
D1) is set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT

DTMF CODE
03 02 01 DO

---- t-------

1
2
3

0 a a 1
a a 1 a
a a 1 1
a 1 a a
- - r-a 1 0 1
-- r-- -a 1 1 a
1----a 1 1 1
1------- 1 0 0 a
- - r-----1 a a 1
1 a 1 a
--1----

-_.- e----

--~

4

5
6

---

----~

~-.-

-

--"--

--

TONES
LOW HIGH
697

1209

697

1336

697

1477

770

1209

770

1336

770

1477

852

1209

i----

--~

7
8
9

a

3-187

-----

----

- - - 1------

852

1336

852

1477

941

1336

I

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
TONE REGISTER

(Continued)

CONDITION

NAME

BIT NO.

DESCRIPTION
KEYBOARD
EQUIVALENT

D3, D2,
D1, DO
(Cont.)

06

*

1

0

1

1-

941

#

1

1

0

0

941

1477

A

1

1

0

1

697

1633

B

1

1

1

0

770

1633

C
D

1

1

1

1

852

1633

0

0

0

0
--

941

1633

1

Activates DTMF. The selected DTMF tones are transmitted continuously when this bit is high. TX DTMF
overrides all other transmit functions.

Transmit
Answer Tone

0

Disables answer tone generator.

1

Enables answer tone generator. A 21 00 Hz answer tone
will be transmitted continuously when the transmit enable bit is set. The device must be in-_..-Answer mode.

Transmit
Calling Tone

0

Disables calling tone generator.

1

Transmit calling tone in either mode.

RXD Output
Control

0

Enables RXD pin. Receive data will be output on RXD.

1

Disables RXD pin. The RXD pin reverts to a high impedance with internal weak pull-up resistor.

07

06

D5

D4

ID

ID

ID

ID

NAME

CONDITION
D7 D6 D5 04

07, 06, 05
04

---

1209

Disabled DTMF.

10 REGISTER

BIT NO.

TONES
LOW HIGH

0

07

ID
110

--

Transmit
DTMF

D4

05

DTMFCODE
D3 D2 D1 DO

DESCRIPTION
Indicates Device:

Device
Identification
Signature

3-188

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER

RATING

VDD Supply Voltage

14V

Storage Temperature

-65 to 150°C

Soldering Temperature (10 sec.)

260°C

Applied Voltage

-0.3 to VDD+0.3V

-

-~

Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.

RECOMMENDED OPERATING CONDITIONS
MIN

NOM

VDD Supply voltage

4.5

5

TA, Operating Free-Air
Temperature

-40

PARAMETER

Clock Variation

CONDITIONS

MAX

UNITS

5.5

V

+85

°C

- -----

(11.0592 MHz) Crystal or
external clock

-0.01

+0.01
-- -

%
-~

External Components (Refer to Application section for placement.)
(External to GND)

0.1

Bias setting resistor

(Placed between VDD
and ISET pins)

1.8

ISET Bypass Capacitor

(ISET pin to GND)

0.1

VDD Bypass Capacitor 1

(External to GND)

0.1

JlF

VDD Bypass Capacitor 2

(External to GND)

22

JlF

XTL 1 Load Capacitor

Depends on crystal characteristics;

VREF Bypass Capacitor

XTL2 Load Capacitor

1-----------

JlF
2

2.2

JlF

-------

40
~~----.

20

from pin to GND

3-189

MO

pF

I

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem

DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)
PARAMETER

CONDITIONS

100, Supply Current

ISET Resistor

IDOA, Active
1001, Power-down
1002, Power-down

MIN

NOM

MAX

UNITS

8

12

rnA

= 2 MQ

= 11 .0592 MHz
CLK = 11.0592 MHz
CLK = 19.200 kHz

CLK

4

rnA

3

rnA

VOO

V

VOO

V

0.8

V

100-

~

50

~

10

pF

VOO

V

0.4

V

------

Digital Inputs

-

-----

VIH, Input High Voltage
Reset, XTL 1, XTL2

3.0

All other inputs

2.0

VIL, Input Low Voltage

-- .-_.. -

0

--

= VIH Max

IIH, Input High Current

VI

ilL, Input Low Current

VI = VIL Min

-200

Reset Pull-down Current

Reset = VOO

1

Input Capacitance

All Oigitallnput Pins

-~----

~

----

--

Digital Outputs

---

VOH, Output High Voltage

10H MIN = -0.4 rnA

VOL, Output Low Voltage

10 MAX = 1.6 rnA

VOL, CLK Output

10 = 3.6 rnA

RXO Tri-State Pull-up Curr.

RXO = GNO

CMAX, CLK Output

Maximum Capacitive Load

2.4

-1

3-190

____

--

0"

0.6

V

-50

~

15

pF

--

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
{TA = -40°C to +85°C, VDD = Recommended range unless otherwise noted.}
CONDITIONS

MIN

Output Freq. Error

ClK = 11.0592 MHz

-0.35

Transmit level

Transmit Dotting Pattern

Harmonic Distortion
in 700-2900 Hz band

TH 0 in the alternate band FSK

PARAMETERS

NOM

FSK Modulator

MAX

UNITS

_.. _--

-11

+0.35

%

-10
.-

-9

dBmO

-60

-50

dB

-

-

Output Bias Distortion

Transmit Dotting Pattern in ALB @ RXD

Total Output Jitter

Random Input in ALB @ RXD

±3

%

-10

+10

%

I

NOTE: Parameters expressed in dBmO refer to the following definition:

o dB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.
DTMF Generator
+0.25

%

-8

dBmO

-7

-6

dBmO

2.0

3.0

dB

-28

dBmO

-0.25

Freq. Accuracy

-10

Output Amplitude

low Band, CRO bit 02=1

Output Amplitude

High Band, CRO bit 02=1

-8

Twist

High-Band to low-Band, as above

1.0

Long Loop Detect

Not valid for V.23 back channel

-38

Dynamic Range

Refer to Performance Curves

-

---

-9

43

dB

t--------.

Call Progress Detector
Detect level

-3 dB points in 285 and 675 Hz

Reject level

Test signal

Delay Time

-70 dBmO to -30 dBmO STEP

Hold Time

-30 dBmO to -70 dBmO STEP

i~a

- - 1----- ------ _.
-_._--

2

Hysteresis

dBmO

-38

460 Hz sinusoid

--

-45

dBmO

40

ms

40

ms
dB

- - - - t----

Carrier Detect
Threshold

-48

Single Tone

-43

dBmO

20

ms

---~-----

Delay Time

.. _._------

V.21

10

V.23 Forward Channe I

6

12

ms

25

40

ms

---

V.23 Back Channel
Hold Time

-

-----"_..

_-

1------

V.21
V.23 Forward Channel

---

V.23 Back Channel

-----

6

20

ms

3

8

ms

10

25

ms

2

Hysteresis

3-191

dB

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
PARAMETERS

(Continued)

CONDITIONS

MIN

See definitions for
TR bit DO mode

-48

Special Tone Detectors
Detect Level
Delay Time

-

~--

..

----

MAX

UNITS

-43

dBmO

---

---

-70 dBmO to -30 dBmO Step

2100 Hz answer tone

10

1300 Hz calling tone

10

390 Hz
V.23 back channel mark
980 or 1650 Hz
V.21 marks
Hold Time

NOM

__ .. - 25

ms

25

ms

20

65

ms

10

25

ms

.

--

-- -"----

-30 dBmO to -79 dBmO Step

2100 Hz answer tone

4

15

ms

1300 Hz calling tone

3

10

ms

390 Hz
V.23 back channel mark

10

25

ms

980 or 1650 Hz
V.21 marks

5

15

ms

---

----- -----

Hysteresis

2

Detect Freq. Range

Any Special Tone

-3

TXA pin; FSK Single
Tone out for THO = -50 dB
in .3 to 3.4 kHz

10

--------

+3

--_.

dB

%

Output Smoothing Filter
- -----

Output load

kQ
50

pF

-60

dBmO

~-

Out of Band Energy

Frequency> 12 kHz in all modes

Output Impedance

TXA pin, TXA Enabled

20

50

n

TXA pin; 76.8 kHz or
122.88 kHz in V.23 main channel

0.1

0.4

mVrms

Clock Noise

3-192

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS

CONDITIONS

Timing (Refer to Timing Diagrams)
TAL

NOM

MAX

UNITS

---

CS/Addr. setup before ALE Low

TLA

CSI Addr. hold after ALE Low

TLC

ALE Low to RDIWR Low

TCL

RD/WR Control to ALE High

TRD

Data out from RD Low

TLL

ALE width

TRDF

Data float after RD High

TRW

RD width

TWW

*

MIN

-

WRwidth

TOW

Data setup before WR High

25
20

ns

30
-5
0
30
0
200
140
40
10

ns

TWO

Data hold af!er WR High

TCKD

Data out after EXCLK Low

TCKW

WR after EXCLK Low

150

TDCK

Data setup before EXCLK Low

150

Address setup before control*

TCA

Address hold after control*

TWH

Data Hold after EXCLK

50
50
20

3-193

- --- ----

ns

-----.-

140

ns
ns

- -----

5

ns

25000
25000

ns
ns
ns
ns

----

200

----""

TAC

Control for setup is the falling edge of RD or WR.
Control for hold is the falling edge of RD or the rising edge of WR.

ns

--_._.
------_.
- .. - --

ns
ns
ns
ns
ns

I

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
ALE

~
~
TlC

RD

.L

TRW

-'r-

J

TCl

..,1-

r

-------

TLC

J

TWW

'J

TlA

L

ADO-AD7
CS

I

-~-

WR

---K

~-

TAL

l...L

TAD

~

I TWD

TRDF

~

I. .

ADDRESS )f-----K READ DATA)f-----K ADDRESS

-~-

-J-

TOW

~ .. ,t~1

~~

-J-

READ TIMING DIAGRAM (SERIAL VERSION)
EXClK

RD

AO-A2

DATA - - +

WRITE TIMING DIAGRAM (SERIAL VERSION)
EXClK

-----+--------------------------------------~--"

AO-A2 - - - 1 - - - - - - - - - - - - - - - - - - - - - - - 1 + ,

DATA

3-194

HTWW

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
APPLICATIONS INFORMATION
GENERAL CONSIDERATIONS
Figures 1 and 2 show basic circuit diagrams for
K-Series modem integrated circuits. K-Series products
are designed to be used in conjunction with a control
processor, a UART or RS-232 serial data interface,
and a DAA phone line interface to function as a typical
intelligent modem. The K-Series ICs interface directly
with Intel 8048 and 80C51 microprocessors for control
and status monitoring purposes.Two typical DAA
arrangements are shown: one for a split ±5 or ±12
volt design and one for a single 5 volt design. These
diagrams are for reference only and do not represent
production-ready modem designs.

K-Series devices are available with two control interface versions: one for a parallel multiplexed address/
data interface, and one for a serial interface. The
parallel version is intended for use with 8039/48 or
8031/51 microcontrollers from Intel or many other
manufacturers. The serial interface 22-pin version can
be used with other microcontrollers or in applications
where only a limited number of port.lines are available
or the application does not lend itself to a multiplexed
address/data interface. The parallel versions may also
be used in the Serial mode, as explained in the data
sheet pin description.
In most applications the controllerwill monitor the serial
data for commands from the DTE and the received
data for break signals from the far end modem. In this
way, commands to the modem are sent over the same
line as the transmitted data. In other applications the
RS-232 interface handshake lines are used for modem
control.

Cl
390 pF

RS232
LEVEL
CONVERTERS
RTS
CTS
OSR
OTR

CA
CB
CC
CO

OCO

CF

WR
ALE

/:S

SSI
K-SERIES
LOW
POWER
FAMILY

C2
300pF

TXO
RXO

BA
BB
OA
DO
DB

RXCLK
TXCLK

us.

U6

MC145406

VRl
MOV
V250L20

+5

o

~22K
FIGURE 1: BaSic Box Modem with Dual-Supply Hybrid

3-195

I

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
DIRECT ACCESS ARRANGEMENT (DAA)
The telephone line interfaces show two examples of
how the "hybrid" may be implemented. The split supply
design (Figure 1) is a typical two op-amp hybrid. The
receive op-amp serves two purposes. It supplies gain
to amplify the receive signal to the proper level for the
modem's detectors and demodulator, and it removes
the transmitted signal from the receive signal present
at the transformer. This is done by supplying a portion
of the transmitted signal to the non-inverting input of
the receive op-amp at the same amplitude as the Signal
appearing at the transformer, making the transmit
signal Common mode.
The single-supply hybrid is more complex than the
dual-supply version described above, but its use eliminates the need for a second power supply. This circuit
(Figure 2) uses a bridged drive to allow undistorted
signals to be sent with a single 5V supply. Because
DTMF tones utilize a higher amplitude than data, these

signals will clip if a single-ended drive approach is
used. The bridged driver uses an extra op-amp (U1 A)
to invert the Signal coming from the gain setting op-amp
(U1 B) before sending it to the other leg of the transformer. Each op-amp then supplies half the drive signal
to the transformer. The receive amplifier (U1 C) picks
off its signal at the junction of the impedance matching
resistor and the transformer. Because the bottom leg of
the transformer is being driven in one direction by U1 A
and the resistor is driven in the opposite direction at the
same time by U1 B, the junction of the transformer and
resistor remains relatively constant and the receive
signal is unaffected.

DESIGN CONSIDERATIONS
Silicon Systems' 1-chip modem products include all
basic modem functions. This makes these devices
adaptable for use in a variety of applications, and as
easy to control as conventional digital bus peripherals.

Cl
390pF

R4

37.41< 1%
C3

• Note: Op-amp U 1
must be rated for
single 5V operation.
R10 & R11 values
depend on Op-amp
used.

0.1 of'

@)---l f----------<~

+SV

R6
22.1K
C6
O.lof'

R7
20Kl%

CS
7S0pF

~~~~N~~~I--~
VRl
MOV

V2501..20

VOLTAGE
REFERENCE

HOOK

>-_ _ _ _ _- - . l

RING

FIGURE 2: Single 5V Hybrid Version
3-196

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
Unlike digital logic circuitry, modem designs must
properly contend with precise frequency tolerances
and very low level analog signals, to ensure acceptable
performance. Using good analog circuit design practices will generally result in a sound design. Following
are additional recommendations which should be
taken into consideration when starting new designs.
CRYSTAL OSCILLATOR

The K-Series crystal oscillator requires a Parallel mode
(antiresonant) crystal which operates at 11.0592 MHz.
It is important that this frequency be maintained to
within ±0.01% accuracy.
In order for a Parallel mode crystal to operate correctly
and to specification, it must have a load capacitor
connected to the junction of each of the crystal and
internal inverter connections, terminated to ground.
The values of these capacitors depend primarily on the
crystal's characteristics, and to a lesser degree on the
internal inverter circuit. The values used affect the
accuracy and start up characteristics of the oscillator.
LA YOUT CONSIDERATIONS

Good analog/digital design rules must be used to
control system noise in orderto obtain highest performance in modem deSigns. The more digital circuitry
present on the PC board, the more this attention to
noise control is needed. The modem should be treated
as a high impedance analog device. A 22 mF electrolytic capacitor in parallel with a 0.1 mF ceramic capacitor between VDD and GND is recommended. Liberal
use of ground planes and larger traces on power and
ground are also highly favored. High speed digital
circuits tend to generate a significant amount of EMI
(Electro-Magnetic Interference) which must be minimized in order to meet regulatory agency limitations.
To accomplish this, high speed digital devices should
be locally bypassed, and the telephone line interface
and K-Series device should be located close to each
other near the area of the board where the phone line
connection is accessed. To avoid problems, power
supply and ground traces should be routed separately
to the analog and digital functions on the board, and
digital signals should not be routed near low level or
high impedance analog traces. The analog and digital
grounds should only connect at one pOint near the KSeries device ground pin to avoid ground loops. The KSeries modem IC's should have both high frequency
and low frequency bypassing as close to the package
as possible.

MODEM PERFORMANCE
CHARACTERISTICS
The curves presented here define modem IC performance under a variety of line conditions while inducing
disturbances that are typical of those encountered
during data transmission on public service telephone
lines. Test data was taken using an AEA Electronics'
"Autotest I" modem test set and line simulator, operating under computer control. All tests were run fullduplex, using a Concord Data Systems 224 as the
reference modem. A 511 pseudo-random-bit pattern
was used for each data point. Noise was C-message
weighted and all signal-to-noise (SIN) ratios reflect
total power measurements similar to the CCITT V.56
measurement specification. The individual tests are
defined as follows.
BER vs. SIN

This test measures the ability of the modem to operate
over noisy lines with a minimum of data-transfer errors.
Since some noise is generated in the best of dial-up
lines, the modem must operate with the lowest SIN
ratio possible. Better modem performance is indicated
by test curves that are closest to the BER axis. A
narrow spread between curves representing the four
line parameters indicates minimal variation in performance while operating over a range of aberrant operating conditions. Typically, a DPSK modem will exhibit
better BER-performance test curves receiving in the
low band than in the high band.
BER

VS.

Receive Level

This test measures the dynamic range of the modem.
Because signal levels vary widely over dial-up lines,
the widest possible dynamic range is desirable. The
minimum Bell specification calls for 36 dB of dynamic
range. SIN ratios are held constant at the indicated
values while the receive level is lowered from a very
high to very low signal levels. The width of the "bowl" of
these curves, taken at the BER point, is the measure of
dynamic range.

3-197

3

SSI73K321L
CClll V.23, V.21
Single-Chip Modem

*SSI 73K321 L
BER vs RECEIVE LEVEL (V.23)

SSI73K321L
BER vs SIGNAL TO NOISE
10-2

10-2

I V.21 -40
OPERATION I
dBM

\

t

V.23 MAIN CHANNEL
RECEIVE OPERATION
C2 LINE, SIN = 9.5 dB

t--

FLAT HIGH BAND

\~

1\

10-3

Ir
10.3

,\

C2 HIGH BAND

1\\

\~

1\

w
~
a:

~~

\

10.4

~ ~ I--

~

\

~

~\

~I\.

3002 HIGH BAND

\

\

V

1\ f\.

10-5

'\

10-4

a:
a:
w
t=

\

~

J

OJ

l7

1_

II

10-5

\\

r\ \

\

\ I LOW BAND RECEIVE
FLAT, 3002, AND C2 LINES

/

\

\

~

10-6

_v

/

v

10.6
0

1

2

3

4

7

6

5

9

8

10

11

12

10

SIGNAL TO NOISE (dB)

*

10-2

./

H

C2 EO. OFF

I\

1\

10-3

I V.23 -40dBM
OPERATION

\

\

I\f\
,\

3002 EO. OFF

r~

l...-1"""

H

FLAT EO. OFF

\

\
BACK CHANNEL

I

j

10·5

II

\

t--

\

\

FLAT EO. ON

v

'1.\ V

\
2

4

6

8

10

12

C2EO.ON

~ I--

\

\

\

10.6
0

1- I--

~

1\ 1 1\

\~

~

-2

f-

1'( \

l\

...... t"-..

I--

3002 EO. ON

I'vV

10-4

14

-20

-30

-40

-50

16

18

20

=

"EO On" Indicates bit CR1 04 is set for
additional phase equalization.

** = 73K302L performance is similar to that
of the 73K322L V.23 operation
corresponds to Bell 202.

\

\ \

-10

RECEIVE LEVEL (dS)

*SSI 73K321 L
BER vs SIN (V.23 ONLY)**

~

0

22

SIGNAL TO NOISE (dB)

3-198

SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
PACKAGE PIN DESIGNATIONS

CAUTION: Use handling procedures necessary
for a static sensitive component.

(TOP VIEW)

ClK

GND

RXA

XTL2

VREF

RXA
VREF

XTLl

RESET

Al

GND

XTll

ADO

RESET

ADl

ISET

AD2

RXClK

ISET

AD3

RXD

RXCLK

AD4

TXD

RXD

ADS

CS

TXD

AD6

EXClK

4

,i

1

28

27 26

5~

25
24

Plee PINOUTS

ARE THE SAME AS
THE 28-PIN DIP

8

EXCLK

AD7

TXClK

ALE

INT

lOLi

INT

WR

TXA

11

TXA

RD

VDD

600-Mil
28-Pin DIP

2

6 '

TXCLK

400-Mil
22-Pin DIP

3

9

23
22
21
20

q

19
12 13 14 15 16 17 18

28-Pin
PLCC

ORDERING INFORMATION
ORDER NO.

PART DESCRIPTION

PKG.MARK

SSI 73K321 L with Parallel Bus Interface
28-Pin 5V Supply
Plastic Dual-In-Line

73K321 L-IP

73K321 L-IP

Plastic Leaded Chip Carrier

73K321L-IH

73K321 L-IH

73K321 SL-IP

73K321 SL-IP

SSI 73K321 L with Serial Interface
22-Pin 5V Supply
Plastic Dual-In-Line

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680, (714) 573-6000, FAX: (714) 573-6914

1292 - rev.

3-199

Protected by the following patents: (4,691,172) (4,777,453)
©1989 Silicon Systems, Inc.

I

Notes:

3-200

551 73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem

January 1994

DESCRIPTION

FEATURES

The SSI 73K322L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a CCITT V.23, V.22 and V.21 compatible
modem, capable of 1200 or 0-300 bit/s full-duplex
operation or 0-1200 biVs half-duplex operation with or
without the back channel over dial-up lines. The
SSI 73K322L is an enhancement of the SSI 73K221 L
single-chip modem with performance characteristics
suitable for European and Asian telephone systems.
The SSI 73K322L produces either 550 or 1800 Hz
guard tone, recognizes and generates a 2100 Hz
answer tone, and supports V.21 for 300 Hz FSK
operation. It also operates in V.23, 1200 biVs FSK
mode. The SSI73K322L integrates analog, digital, and
switched-capacitor array functions on a single
substrate,offering excellent performance and a high
level of functional integration in a single 28- or 22-pin
DIP configuration. The SSI73K322L operates from a
single +5V supply with very low power consumption.
The SSI 73K322L includes the DPSK and FSK
modulator/demodulator functions, call progress and
handshake tone monitor test modes, and a tone
generator capable of producing DTM F, answer, calling
and 550 or 1800 Hz guard tone. This device supports
V.23, V.22 (except mode v) and V. 21 modes of
operation, allowing both synchronous and

One-chip CCITT V.23, V.22 and V.21 standard
compatible modem data pump
Full-duplex operation at 0-300 bitls (FSK) or 600 and
1200 bitls (DPSK) or 0-1200 bitls (FSK) forward
channel with or without 0-75 bitls back channel
Interfaces directly with standard microprocessors
(8048, 80C51 typical)
Serial or parallel microprocessor bus for control
Serial port for data transfer
Both synchronous and asynchronous modes of
operation
Call progress, carrier, preCise answer tone
(2100 Hz), calling tone (1300 Hz) and FSK mark
detectors
DTMF and 550 or 1800 Hz guard tone generators
Test modes available: ALB, DL, RDL, Mark, Space,
Alternating bit patterns
Precise automatic gain control allows 45 dB
dynamic range
CMOS technology for low power consumption
using 30 mW @ 5V from a single power supply
Surface mount PLCC package available

(Continued)

BLOCK DIAGRAM

PIN DIAGRAM
28

ADO-A07

27

26

RD

~ GND
P RXA
VREF

TXA

WR
ALE
CS
RESET

RXA

AD2
AD3
AD4
ADS

INT

AD6
TXD
RXD

0--------+-1
o-------L-_..J

AD7

WR
RD

CAUTION: Use handling procedures necessary
for a static sensitive component.

0194 - rev.

3-201

I

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
DESCRIPTION (continued)
asynchronous communications. The SSI 73K322L is
designed to appear to the systems designer as a
microprocessor peripheral, and will easily interface
with popular one-chip microprocessors (80C51 typical) for control of modem functions through its 8-bit
multiplexed address/data bus or via an optional serial
control bus. An ALE control line simplifies address
demultiplexing. Data communications occurs through
a separate serial port only.
The SSI73K322L is ideal for use in either free standing
or integral system modem products where multi-standard data communications over the 2-wire switched
telephone network is desired. Its high functionality, low
power consumption and efficient packaging simplify
design requirements and increase system reliability. A
complete modem requires only the addition of the
phone line interface, a control microprocessor, and
RS-232 level converter for a typical system. The
SSI 73K322L is part of Silicon Systems K-Series family
of pin and function compatible single-chip modem
products. These devices allow systems to be configured for higher speeds and Bell or CCITT operation
with only a single component change.

OPERATION
ASYNCHRONOUS MODE

Data transmission for the DPSK mode requires that
data ultimately be transmitted in a synchronous fashion. The SSI 73K322L includes ASYNC/SYNC and
SYNC/ASYNC converters which delete or insert stop
bits in order to transmit data at a regular rate. In
Asynchronous mode the serial data comes from the
TXD pin into the ASYNC/SYNC converter. The
ASYNC/SYNC converter accepts the data provided on
the TXD pin which normally must be 1200 or 600 bit/s
+ 1.0%, -2.5%. The rate converter will then insert or
delete stop bits in order to output a signal which is 1200
or 600 biVs± 0.01% (± 0.01% is the crystal tolerance).
The SYNC/ASYNC converter also has an extended
overspeed mode which allows selection of an output
overspeed range of either +1% or +2.3%. In the extended overspeed mode, stop bits are output at 7/8 the
normal width.
The serial data stream from the transmit buffer or the
rate converter is passed through the data scrambler
and onto the analog modulator. The data scrambler

can be bypassed under processor control when
unscrambled data must be transmitted. If serial input
data contains a break signal through one character
(including sJart and stop bits) the break will be
extended to at least 2 • N + 3 bits long (where N is the
number of transmitted bits/character).
Serial data from the demodulator is passed first
through the data descrambler and then through the
SYNC/ASYNC converter. The ASYNC/ASYNC converterwill reinsert any deleted stop bits and output data
at an intra-character rate (bit-to-bit timing) of no greater
than 1219 biVs. An incoming break signal (low through
two characters) will be passed through without incorrectly inserting a stop bit.
SYNCHRONOUS MODE

The CCITTV.22 standard defines synchronous operation at 600 and 1200 bit/so Operation is similar to that of
the Asynchronous mode except that data must be
synchronized to a provided clock and no variation in
data transfer rate is allowable. Serial input data appearing at TXD must be valid on the rising edge of
TXCLK.
TXCLK is an internally derived signal in Internal mode
and is connected internally to the RXCLK pin in Slave
mode. Receive data at the RXD pin is clocked out on
the falling edge of RXCLK. The ASYNCH/SYNCH
converter is bypassed when Synchronous mode is
selected and data is transmitted out at the same rate as
it is input.
DPSK MODULATOR/DEMODULATOR

In DP5K mode the 551 73K322L modulates a serial bit
stream into di-bit pairs that are represented by four
possible phase shifts as prescribed by the V.22 standards. The base-band signal is then filtered to reduce
intersymbol interference on the bandlimited 2-wire
telephone line. Transmission occurs using either a
1200 Hz (Originate mode) or 2400 Hz carrier (Answer
mode). Demodulation is the reverse of the modulation
process, with the incoming analog signal eventually
decoded into di-bits and converted back to a serial bit
stream. The demodulator also recovers the clock
which was encoded into the analog signal during
modulation. Demodulation occurs using either a
1200 Hz carrier (Answer mode or ALB Originate mode)
or a 2400 Hz carrier (Originate mode or ALB Answer
mode). The SSI 73K322L uses a phase locked loop
. coherent demodulation technique for optimum
receiver performance.

3-202

SSI73K322L
CClll V.23, V.22, V.21
Single-Chip Modem
FSK MODULATOR/DEMODULATOR

The F5K modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. V.21 mode uses 980 and
1180 Hz (originate, mark and space) or 1650 and
1850 Hz (answer, mark and space). V.23 mode uses
1300 and 2100 Hz for the main channel and 390 and
450 Hz for the back channel. The modulation rate of
the back channel is up to 75 baud. Demodulation
involves detecting the received frequencies and
decoding them into the appropriate binary value. The
rate converter and scrambler/descrambler are automatically bypassed in the V.21 or V.23 modes.
PASSBAND FILTERS AND EQUALIZERS

High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay equalization and rejection of out-of-band Signals in the
receive channel. Amplitude and phase equalization
are necessary to compensate for distortion of the
transmission line and to reduce intersymbol interference in the bandlimited receive signal. The transmit
signal filtering approximates a 75% square root of
raised Cosine frequency response characteristic.
AGC

The automatic gain control maintains a signal level at
the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping and provides a total
receiver dynamic range of >45 dB.

passed through the data pin under control of the RD
and WR lines. A read operation is initiated when the RD
line is taken low. The first bit is available after RD is
brought low and the next seven cycles of EXCLK will
then transfer out seven bits of the selected address
location L5B first. A write takes place by shifting in eight
bits of data L5B first for eight consecutive cycles of
EXCLK. WR is then pulsed low and data transferred
int~e selected register occurs on the rising edge
ofWR.
SPECIAL DETECT CIRCUITRY

The special detect circuitry monitors the received
analog Signal to determine status or presence of carrier, answer tone and weak received signal (long loop
condition), special tones such as F5K marking and the
1300 Hz calling tone are also detected. A highly frequency selective call progress detector provides adequate discrimination to accurately detect European
call progress Signals.
DTMF GENERATOR

The DTMF generator will output one of 16 standard
tone pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mode
is selected using the tone register and the transmit
enable (CRO bit 01) is changed from 0 to 1.

PARALLEL BUS INTERFACE

Four 8-bit registers are provided for control, option
select and status monitoring. These registers are addressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as four consecutive memory locations. Two control registers and the tone register are
read/write memory. The detect register is read only and
cannot be modified except by modem response to
monitored parameters.
SERIAL COMMAND INTERFACE

The serial command interface allows access to the
551 73K322L control and status registers via a serial
command port (22-pin version only). In this mode the
AO , A 1 and A2lines provide register addresses for data
3-203

I

SSI73K322L
CCllT V.23, V.22, V.21
Single-Chip Modem
PIN DESCRIPTION
POWER
28-PIN

22-PIN

TYPE

DESCRIPTION

GND

28

1

I

System Ground.

VDD

15

11

I

Power supply input, 5V ±1 0%. Bypass with 0.1 and 22 J..lF
capacitors to GND.

VREF

26

21

0

An internally generated reference voltage. Bypass with
0.1 J..lF capacitor to GND.

ISET

24

19

I

Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 MQ resistor. ISET should be bypassed to GND with a
0.1 J..lF capacitor.

NAME

PARALLEL MICROPROCESSOR INTERFACE

12

-

I

Address latch enable. The falling edge of ALE latches the
address on ADO-AD2 and the chip select on CS.

4-11

-

1/0

Addressldata bus. These bidirectional tri-state multiplexed lines carry information to and from the internal
registers.

CS

20

-

I

Chip select. A low on this pin during the falling edge of ALE
allows a read cycle or a write cycle to occur. ADO-AD7 will
not be driven and no registers will be written if CS (latched)
is not active. The state of CS is latched on the falling edge
of ALE.

ClK

1

2

0

Output clock. This pin is selectable under processor control
to be either the crystal frequency (for use as a processor
clock) or 16 x the data rate for use as a baud rate clock in
DPSK modes only. The pin defaults to the crystal frequency
on reset.

INT

17

13

0

Interrupt. This open drain output Signal is used to inform the
processor that a detect flag has occurred. The processor
must then read the detect register to determine which
detect triggered the interrupt. INT will stay low until the
processor reads the detect register or does a full reset.

RD

14

-

I

Read. A low requests a read of the SSI 73K322l internal
registers. Data cannot be output unless both RD and the
latched CS are active or low.

RESET

25

20

I

Reset. An active high signal on this pin will put the chip into
an inactive state. All control register bits (CRO, CR1, Tone)
will be reset. The output of the elK pin will be set to the
crystal frequency. An internal pull down resistor permits
power on reset using a capacitor to VDD.

ALE
ADO-AD7

--

3-204

SSI73K322L
CClll V.23, V.22, V.21
Single-Chip Modem
PARALLEL MICROPROCESSOR INTERFACE (Continued)
NAME
WR

28·PIN

22·PIN

TYPE

13

-

I

DESCRIPTION
Write. A low on this informs the SSI73K322L that data is
available on ADO-AD7 for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are low.

SERIAL MICROPROCESSOR INTERFACE
AO-A2

-

5-7

DATA

-

RD

WR

I

Register Address Selection. These lines carry register
addresses and should be valid during any read or write
operation.

8

I/O

Serial Control Data. Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs d~ta.

-

10

I

Read. A low on this input informs the SSI73K322L that data
or status information is being read by the processor. The
falling edge of the RD signal will initiate a read from the
addressed register. The RD signal must continue for eight
falling edges of EXCLK in order to read all eight bits of the
referenced register. Read data is provided LSB first. Data
will not be output unless the RD si~~al is active.

-

9

I

Write. A low on th is input informs the SS I 73K322 L that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on
the DATA pin for eight consecutive falling edges of EXCLK
and then to pulse WR low. Data is written on the rising edge
ofWR.
- ...

--~------

Note:

In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the
pins;AO,A1, A2, DATA, and an unconnected pin. Also, the RDandWR controls are used differently.
The Serial Control mode is provided in the parallel control versions by tying ALE high and CS low.
In this configuration AD7 becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2,
respectively.

DTE USER INTERFACE
NAME

28·PIN

22·PIN

TYPE

EXCLK

19

15

I

DESCRIPTION
External Clock. This signal is used only in synchronous
DPSK transmission when the external timing option has
been selected. In the External Timing mode the riSing edge
of EXCLK is used to strobe synchronous DPSK transmit
data available on the TXD pin. Also used for serial control
interface.

3-205

I

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
RS·232 INTERFACE (Continued)
NAME

28-PIN

22·PIN

TYPE

RXCLK

23

18

0

Receive Clock. The falling edge of this clock output is
coincident with the transitions in the serial received DPSK
data output. The rising edge of RXCLK can be used to latch
the valid output data. RXCLK will be valid as long as a
carrier is present. In V.23 or V.21 mode a clock which is
16 x1200 (or 16 x 75) or 16 x 300 Hz baud data rate is
output, respectively, for driving a UART.

RXD

22

17

0

Received Data Output. Serial receive data is available on
this pin. The data is always valid on the rising edge of
RXCLK when in Synchronous mode. RXD will output
constant marks if no carrier is detected.

TXCLK

18

14

0

Transmit Clock. This signal is used only in synchronous
DPSK transmission to latch serial input data on the TXD
pin. Data must be provided so that valid data is available
on the rising edge of the TXCLK. The transmit clock is
derived from different sources depending upon the Synchronization mode selection. In Internal Mode the clock is
1200 Hz generated internally. In External Mode TXCLK is
phase locked to the EXCLK pin. In Slave Mode TXCLK is
phase locked to the RXCLK pin. TXCLK is always active. In
V.23 or V.21 mode the output is a 16 x 1200 (or 16 x 75) or
16 x 300 Hz baud clock, respectively for driving a UART.

TXD

21

16

I

Transmit Data Input. Serial data fortransmission is applied
on this pin. In Synchronous modes, the data must be valid
on the rising edge of the TXCLK clock. In Asynchronous
modes (1200 or 300 baud) no clocking is necessary. DPSK
must be 1200/600 bitls +1%, -2.5% or +2.3%, -2.5 % in
Extended Overs peed mode.

DESCRIPTION

ANALOG INTERFACE AND OSCILLATOR
RXA

27

22

I

Received modulated analog signal input from the telephone line interface.

TXA

16

12

0

Transmit analog output to the telephone line interface.

XTL1
XTL2

2
3

3
4

I
I

These pins are for the internal crystal oscillator requiring
a 11.0592 MHz Parallel mode crystal and two load capacitors to Ground. XTL2 can also be driven from an external
clock.

3-206

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
REGISTER DESCRIPTIONS
Four 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AO and A 1
address lines in Serial mode, orthe ADO and AD1 lines
in Parallel mode. The ADO and AD11ines are latched by
ALE. Register C RO controls the method by which data
is transferred over the phone line. CR1 controls the

interface between the microprocessor and the
SSI73K322L internal state. DR is a detect register
which provides an indication of monitored modem
status conditions. TR, the tone control register, controls the DTM F generator, answer and guard tones and
RXD output gate used in the modem initial connect
sequence. All registers are read/write except for DR
which is read only. Register control and status bits are
identified below:

REGISTER BIT SUMMARY

COOTROL
REGISTER
1
DETECT
REGISTER

CRO

000

CR1

001

DR

010

TOOE
COOTROL
REGISTER

m

011

COOTROL
REGISTER
2

CR2

100

CR3

101

10

110

COOTROL
REGISTER

ENABLE
DETECT
INTERRUPT

BYPASS
SCRAMBLER!
ADDPH.EQ.
(V.23)

CLK
COOTROL

RECEIVE
DATA

UNSCR.
MARKS

CARRIER
DETECT

SPECIAL
TONE

TRANSMIT
DTMF

DTMF3

DTMF21
V.23 FOX

3
10
REGISTER

NOTE:

When a register containing reserved
control bits is written into, the reserved bits
must be programmed as O's.

3-207

RESET

TEST
MODE
1

CALL
PROGRESS

TEST
MODE
0
LONG
LOOP

I

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
REGISTER ADDRESS TABLE

0=1200 BITtS DPSK
1=600 81TtS DPSK
O=V.23 FSK
1=V.21 FSK

O=DISABLE
TXA OUTPUT
1=ENABLE
TXA OUTPUT

OOOO=PWR DOWN
0001=INT SYNCH
001 O.EXT SYNCH
0011 =SLAVE SYNCH
0100=ASYNCH 8 BITSiCHAR
010hASYNCH 9 BITSiCHAR
0110=ASYNCH 10 BITSICHAR
011hASYNCH 11 BITS/CHAR
1100.FSK

IN V.21 OR V.22 MODE'
O=ANSWER
1.0RIGINATE
IN V.23 MODE:
O.RECEIVE @ 1200 BITtS,
TRANSMIT @ 75 BITtS
1=RECEIVE @ 75 BITtS,
TRANSMIT @ 1200 81TtS

O=XTAL
1=16 X DATA
RATE OUTPUT
AT CLK PIN IN
DPSKMODE
ONLY

O=NORMAL
1=ALLOWS V.23 FULL
DUPLEX OPERATION

00XX.73K212L, 322L, 321L
01XX.73K221L,302L
1OXX.73K222L
1100_73K224L
11 10.73K324L
1101 =73K312L

3-208

0=1800 Hz G.T. (V.22).
2225 Hz ANS TONE
GENERATED, FSK
MARK DETECT
SELECTED
1=550 Hz G.T. (V.22)
2100 Hz ANS TONE
GENERATED &
DETECTED (V.21 , V.22)
1300 Hz DETECTED (V.23)

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem

)I

CONTROL REGISTER 0

CRO
000

D7
MOOUL.
OPTION

BIT NO.
DO
high

04
03
02
01
D5
TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT
MODE 1
MOOEO
ENABLE
MOOE2
MODE 3

DO
ANSWER/
ORIGINATE

NAME

CONDITION

Answer/

0
Originate

DESCRIPTION
Selects Answer mode in V.21 and V.22 (transmit in
band), receive in low band or in V.23 HOX mode,
receive at 1200 bit/s and transmit at 75 bit/so

1

Selects Originate mode in V.21 and V.22 (transmit in
low band) ,receive in high band or in V.23 HOX mode,
receive at 75 bitls and transmit at 1200 bit/so
Note: This bit works with TR bit DO to program special
tones detected in Tone Register. See detect and tone
"'~":H"";:).

01

Transmit
Enable

')I~;mlp.~

0
1

transmit output at

Enables transmit output at
Note: Answer tone and OTMF TX control require TX
enable.

05 04 03 02
05,04,03,
02

Transmit
Mode

0

0

0

0

Selects Power Down mode. All functions disabled
except digital interface.

0

0

0

1

Internal Synchronous mode. In this mode TXCLK is an
internally derived 1200 Hz signal. Serial input data
appearing at TXO must be valid on the rising edge of
TXCLK. Receive data is clocked out of RXO on the
falling edge of RXCLK.

0

0

1

0

External Synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 1200 Hz ± 0.01 % clock must
be supplied externally.

0

0

1

1

Slave Synchronous mode. Same operation as other
Synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.

0

1

0

0

Selects OPSK Asynchronous mode - 8 bits/character
(1 start bit, 6 data bits, 1 stop bit).

0

1

0

1

Selects OPSK Asynchronous mode - 9 bits/character
(1 start bit, 7 data bits, 1 stop bit).

0

1

1

0

Selects OPSK Asynchronous mode - 10 bits/character
(1 start bit, 8 data bits, 1 stop bit).

0

1

1

1

Selects OPSK Asynchronous mode - 11 bits/character
(1 start bit, 8 data bits, Parity and 1 or 2 stop bits).

1

1

o

0

Selects FSK
3-209

VI-'''' I ClUV

I

I

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
CONTROL REGISTER 0 (Continued)
07
CRO
000

04

05

TRANSMIT
MODE 2

MOOUL.
OPTION

07 05 04
07

02

03

01

DO

TRANSMIT TRANSMIT
MODE 0
ENABLE

ANSWER/
ORIGINATE

Selects:

Modulation
Option

FSK CCITT V.21 mode.
CONTROL REGISTER 1

CR1
001

07

06

05

04

03

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

ENABLE
DETECT
INTER.

BYPASS
SCRAMB/
ADD
PH. Ea.

ClK
CONTROL

BIT NO.

NAME

01,00

Test Mode

CONDITION

02

01

DO

RESET

TEST
MODE
1

TEST
MODE
0

DESCRIPTION

01 DO

02

Reset

0

a

Selects normal operating mode.

0

1

Analog loopback mode. Loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable must be
forced low.

1

0

Selects remote digital loopback. Received data is
looped back to transmit data internally, and RXO is
forced to a mark. Data on TXD is ignored.

1

1

Selects local digital loopback. Internally loops TXD
back to RXO and continues to transmit carrier from
TXA pin.

0

Selects normal operation.

1

Resets modem to power down state. All control register bits (CRO, CR1 , Tone) are resetto zero. The output
of the ClK pin will be set to the crystal frequency.

3-210

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
CONTROL REGISTER 1

CR1
001

BIT NO.
03

04

05

(Continued)

07

06

05

04

03

02

01

DO

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

ENABLE
DETECT
INTER.

BYPASS
SCRAMB/
ADD
PH. Ea.

ClK
CONTROL

RESET

TEST
MODE
1

TEST
MODE
0

NAME

CONDITION

DESCRIPTION

0

Selects 11.0592 MHz crystal echo output at ClK
pin.

1

Selects 16 X the data rate, output at ClK pin in DPSK
modes only.

Bypass
Scrambler/

0

Selects normal operation. DPSK data is passed
through scrambler.

Add Phase
Equalization

1

Selects Scrambler Bypass. DPSK data is routed
around scrambler in the transmit path. In V.23 mode,
additional phase equalization is added to the main
channel filters when 04 is set to 1.

Enable Oetect

0

Disables interrupt at INT pin.

1

Enables INT output. An interrupts will be generated
with a change in status of DR bits 01-04. The special
tone and call progress detect interrupts are masked
when the TX enable bit is set. Carrier detect is masked
when TX DTMF is activated. All interrupts will be
disabled if the device is in power down
mode.
--

ClK Control

-~

07 06
07,06

Transmit
Pattern

0

0

Selects normal data transmission as controlled by the
state of the TXD pin.

0

1

Selects an alternating mark/space transmit pattern for
modem testing.

1

0

Selects a constant mark transmit pattern.

1

1

Selects a constant space transmit pattern.

3-211

I

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
DETECT REGISTER

DR
010
BIT NO.
DO

NAME

D5

D4

D3

D2

D1

DO

RECEIVE
DATA

UNSCR.
MARK

CARR.
DETECT

SPECIAL
TONE

CALL
PROG.

LONG
LOOP

CONDITION

DESCRIPTION

Long Loop

D1

Call Progress
Detect
1----------+--,-nd-i-ca-t-es-p-re-s-en-c-e-o-f-c-a-lI-p-rO-g-re-s-s-t-on-e-s-.-T-h-e-c-a-II-I
progress detection circuitry is activated by energy in
the normal 350 to 620 Hz call progress band.

D2

Special Tone
Detect

o

No special tone detected as programmed by CRO bit DO
and Tone Register bit DO.

(1) 2100 Hz answer tone if DO of TR= 1 and the device
is in V.21 or V.22 originate mode.
(2) 1300 Hz calling tone if DO of TR=1 and the device
is in V.21, or V.22 answer mode.
(3) an FSK mark in the mode the device is set to
receive.

D3

Carrier Detect I---~---L~~~~~~~~~~~~~~~-----J
Indicated carrier has been detected in the received
channel.

D4

Unscrambled
Ma~
I----------+--,-nd-i-ca-t-es-d-e-te-c-ti-o-n-of-u-n-s-cr-a-m-b-,e-d-m-a-r-ks-i-n----I
the received data. A valid indication requires that
unscrambled marks be received for> 165.5 ± 6.5 ms.
Receive
Data

D5

Continuously outputs the received data stream. This
data is the same as that output on the RXD pin, but it
is not disabled when RXD is tri-stated.

D7

3-212

SSI73K322L
CClll V.23, V.22, V.21
Single-Chip Modem
TONE REGISTER

TR
011

07

06

D5

04

RXD
OUTPUT
CONTR.

TRANSMIT
GUARD/
CALLING
TONE

TRANSMIT
ANSWER
TONE

TRANSMIT
DTMF

BIT NO.

NAME

CONDITION
D6 D5 D4 DO

DO

D2

D3

D1

DO

DTMF 21 DTMF 11
DTMF 01
DTMF3 V.23 FDX OVER- G.T./ANSW./
SPEED
SP. TONE!
SELECT

DESCRIPTION
DO interacts with bits D6, D4, and CRO as shown.

DTMFO

X

X

1

X

Transmit DTMF tones.

Guard Tone/
Answer Tone

1

X

0

0

Select 1800 Hz guard tone if in V.22 and Answer mode
inCRO.

Special T onel
DetecVSelect

1

X

0

1

Select 550 Hz guard tone if in V.22 and Answer mode
inCRO.

X

X

0

0

Mark of an FSK mode selected in CRO is to be detected
in D2 of DR.

X

X

0

1

2100 Hz answer tone will be detected in D2 of DR if
V.21 or V.22 Originate mode is selected in CRO.
1300 Hz calling tone will be detected in D20f DR ifV.21,
or V.22 Answer mode is selected in CRO.

D1

D2

X

1

0

0

Transmit 2225 Hz Answer Tone

X

1

0

1

Transmit 2100 Hz Answer Tone

DTMF 1/
Overspeed

D4 D1

D1 interacts with D4 as shown.

0

0

Asynchronous DPSK 1200 or 600 bitls +1.0% -2.5%.

0

1

Asynchronous DPSK 1200 or 600 bitls +2.3% -2.5%.

DTMF 2/
V.23 FDX

0

Half-duplex asymetric operati_on in V.23 mode.

1

Full-duplex (4-wire) operation in\(23 mode.

D3 D2 D1 DO
D3, D2,

DTMF 3,

0

0

0

0-

D1,DO

2,1,0

1

1

1

1

Programs 1 of 16 DTMF tone pairs that will be
transmitted when TX DTM F and TX enable bit (CRO, bit
D1) are set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT

3-213

DTMFCODE
D3 D2 D1 DO

TONES
LOW HIGH

1

0

0

0

1

697

2

0

0

1

0

697

1209
1336

3

0

0

1

1

697

1477

4

0

1

0

0

770

1209

5

0

1

0

1

770

1336

6

0

1

1

0

770

1477

7

0

1

1

1

852

1209

I

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem

TONE REGISTER (Continued)

TR
011

D7

D6

D5

D4

RXD
OUTPUT
CONTR.

TRANSMIT
GUARD/
CALLING
TONE

TRANSMIT
ANSWER
TONE

TRANSMIT
DTMF

SIT NO.

NAME

CONDITION

D2

D1

DO

DTMF 2/ DTMF 1/
DTMF3 V.23 FDX OVERSPEED

DTMF 0/
GUARD/
SPECIAL
TONE SEL

DESCRIPTION
KEYBOARD
EQUIVALENT

D3, D2,
D1, DO
(Cont.)

D4

D3

DTMFCODE
D3 D2 D1 DO

TONES
LOW HIGH

8

1

0

0

0

852

9

1

0

0

1

852

1477

0

1

0

1

0

941

1336

1336

*

1

0

1

1

941

1209

#

1

1

0

0

941

1477

A

1

1

0

1

697

1633

B

1

1

1

0

770

1633

C

1

1

1

1

852

1633

D

0

0

0

0

941

1633

Transmit
DTMF

0

Disable DTMF.

1

Activate DTMF.The selected DTMF tones are
transmitted continuously when this bit is high.
TX DTMF overrides all other transmit functions.

Transmit
Answer Tone

0

Disables answer tone generator.

1

Enables answer tone generator. A 2100 Hz answer
tone will be transmitted continuously when the transmit
enable bit is set. The device must be in Answer mode.
To transmit answer tone, the device must be in DPSK
Answer mode.

TX Guard or
Calling Tone

0

Disables guard/calling tone generator.

1

Transmit guard tone if in V.22 and answering;
otherwise transmit calling tone, in any other mode
including V.23 mode.

0

Enables RXD pin. Receive data will be output on
RXD.

1

Disables RXD pin. The RXD pin reverts to a high
impedance with internal weak pull-up resistor.

----_..

D5

D6

D7

RXD Output
Control

3-214

SSI73K322L
CClll V.23, V.22, V.21
Single-Chip Modem
10 REGISTER

ID
110

D7

D6

D5

D4

ID

ID

ID

ID

BIT NO.

NAME

D7, D6, D5

Device

DESCRIPTION

CONDITION
D7 D6 D5 D4

D4

Indicates Device:

Identification
Signature

I

ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER

UNIT

RATING

V

14

VDD Supply Voltage

1----

°c
°c

-65 to 150

Storage Temperature

f-----

Soldering Temperature (10 sec.)

260

Applied Voltage

-----

V

-0.3 to VDD+0.3

Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.

RECOMMENDED OPERATING CONDITIONS
PARAMETER

CONDITIONS

VDD Supply voltage

MIN

NOM

MAX

UNITS

4.5

5

5.5

V

+85

°c

-40

TA, Operating Free-Air Temp.

~----

Clock Variation

(11.0592 MHz) Crystal or external clock

-0.01

-

+0.01

%

----~~--~---

External Components (Refer to Application section for placement.)
(External to GND)

0.1

Bias setting resistor

(Placed between VDD and ISET pins)

1.8

ISET Bypass Capacitor

(ISET pin to GND)

0.1

J.lF

VDD Bypass Capacitor 1

(External to GND)

0.1

IJ.F

VDD Bypass Capacitor 2

(External to GND)

22

XTL 1 Load Capacitor

Depends on crystal characteristics;

40

XTL2 Load Capacitor

from pin to GND

20

VREF Bypass Capacitor

IJ.F

- .. -.-

3-215

2-_.• -

2.2

--_._-

Mn

J.lF
pF

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)
PARAMETER

CONDITIONS

100, Supply Current

ISET Resistor

I DDA, Active

MIN

NOM

= 2 MQ

IDD1, Power-down

ClK = 11.0592 MHz
ClK = 19.200 KHz

UNITS

12

rnA

---

ClK = 11.0592 MHz

IDD2, Power-down

MAX

8
- - f-----------------

--

4

rnA

3

rnA

Digital Inputs
VIH, Input High Voltage
Reset, XTl1 , XTl2

3.0

VDD

V

All other inputs

2.0

VDD

V

0

0.8

V

100

50

IJA
IJA
IJA

10

pF

VDD

V

Vll, Input low Voltage

= VIH Max
= Vil Min

IIH, Input High Current

VI

Ill, Input low Current

VI

Reset Pull-down Current

Reset = VDD

Input Capacitance

-.-~

-200
1

All Digital Input Pins

--------

--~-

---

Digital Outputs

-

.. _.. ' .

---

2.4

VOH, Output High Voltage

10H MIN = -0.4 rnA

VOL, Output low Voltage

10 MAX = 1.6 rnA

0.4

V

VOL, ClK Output

10 = 3.6 rnA

0.6

V

-50

IJA

15

pF

-1

RXD Tri-State Pull-up Curro

RXD = GND

CMAX, ClK Output

Maximum Capacitive load

--_._. -_._-

Capacitance

-

Inputs

Capacitance, all Digital Input pins

XTAl1, 2 load Capacitors

Depends on crystal characteristics

ClK

Maximum Capacitive load

3-216

15

-

10

pF

60

pF

15

pF

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = Recommended range unless otherwise noted.)
MIN

CONDITIONS

PARAMETERS

NOM

MAX

UNITS

-9

dBmO

DPSK Modulator
Carrier Suppression

Measured at TXA

45

Output Amplitude

TX scrambled marks

-11

ClK = 11.0592 MHz

-0.35

FSK Modulator

]

-10

dB

- ---

Output Freq. Error
Transmit level

Transmit Dotting Pattern

Harmonic Distortion
in 700-2900 Hz band

TH D in the alternate band
DPSK or FSK

+0.35

-11

-10

-9

~--------.~-~

Output Bias Distortion
Total Output Jitter

-60
--

Transmit Dotting Pattern
In AlB@ RXD

c------

-50

%

dBmO
~---

dB

.~-

%

±3
---

Random Inpu_t in ALB @ RXD

-10

---

+10

0/0

DTMF Generator
Freq. Accuracy

Must be in V.22 mode

-.25

Output Amplitude

low Band, V.22 mode

-10

Output Amplitude

High Band, '(22 mode

-8

+.25

%

-9

-8

dBmO

-7

-6

dBmO

-------~

High-Band to low-Band, V.22 mode

1.0

Long Loop Detect

With Sinusoid

-38

Dynamic Range

Refer to Performance Curves

Twist

1----------

2.0
.. - .. --.

3.0

dB

-28

dBmO

~~

Note:

-.-

45

Parameters expressed in dBmO refer to the following definition:

o dB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.

3-217

dB

I

SSI73K322L
CCllT V.23, V.22, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING

(Continued)

CONDITIONS

MIN

Detect Level

-3 dB points in 285 and 675 Hz

-38

Reject Level

Test signal is a 460 Hz sinusoid

Delay Time

-70 dBmO to -30 dBmO STEP

Hold Time

-30 dBmO to -70 dBmO STEP

PARAMETERS
Call Prog ress Detector

NOM

MAX

UNITS

-------.-

dBmO
--

-.~-~-

-45

dBmO

40

ms

40

ms

-~

-----

2

Hysteresis

dB
------

Carrier Detect
Threshold

DPSK or FSK receive data

-48

-43

--

dBmO

Delay Time
V.21

10

20

ms

V.22

15

32

ms

V.23 Forward Channel

6

12

ms

40

ms

25

V.23 Back Channel
Hold Time

--_.-

.

---------

,-

----

V.21

6

20

ms

V.22

10

24

ms

V.23 Forward Channel

3

8

ms

25

ms

f---

10

V.23 Back Channel

dB

2

Hysteresis

.--

Special Tone Detectors
Detect Level

,--

-48

See definitions for
TR bit DO mode

-43

dBmO

25

ms

Delay Time
10

2100 Hz answer tone

--

-

1300 Hz calling tone

10

25

ms

390 Hz
V.23 back channel mark

20

65

ms

3·218

SSI73K322L
CClll V.23, V.22, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
Special Tone Detectors

CONDITIONS

MIN

(Continued)

NOM

MAX

UNITS

25

ms

_ .._._-------.

980 or 1650 Hz
V.21 marks

10

~~~~-----

---

Hold Time
2100 Hz answer tone

4

1300 Hz calling tone

3

390 Hz
V.23 back channel mark

10

980 or 1650 Hz
V.21 marks

5

-_._------

15

ms

10

ms

25

ms

15

ms

._----

-------

Hysteresis

2
Any Special Tone

-3

Output load

TXA pin; FSK Single
Tone out for THD = -50 dB
in 0.3 to 3.4 kHz

10

Out of Band Energy

Frequency> 12 kHz in all modes

Output Impedance

TXA pin, TXA enabled

Detect Freq. Range

--_ ..•.. _-_ ...

dB

--.--

~-

----

+3

%

Output Smoothing Filter
----_._._-_ ..

Clock Noise

kQ
50

pF

-60

dBmO

20

50

Q

0.1

0.4

mVrms

+10

Hz

--------

TXA pin; 76.8 kHz or
122.88 kHz in V.23 main channel

~~-

---

CarrierVCO
-- ---

Capture Range

Originate or Answer

Capture Time

-10Hz to +10 Hz Carrier
Freq. Change Assum.

-10
40

l100

ms

_ _ _ _ _ L-_ _

Recovered Clock

~_

------

Capture Range

% of frequency
center frequency
(center at 1200 Hz)

Data Delay Time

Analog data in at RXA pin to
receive data valid at RXD pin

-625

+625

--~---

3-219

30

50

ppm

-~-

ms

I

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS

CONDITIONS

MIN

Tone Accuracy

550 or 1800 Hz

-20

Tone Level

550 Hz

-4.0

(Below DPSK Output)

1800 Hz

-7.0

Harmonic Distortion

550 Hz

NOM

MAX

UNITS

+20

Hz

-3.0

-2.0

dB

-6.0

-5.0

dB

-50

dB

Guard Tone Generator

700 to 2900 Hz

---

--- -------

Timing (Refer to Timing Diagrams)
TAL
TLA

CS/Addr. setup before ALE Low
-

25

-_._._-_

...

20

ns
ns

TLC

ALE Low to RDIWR Low

30

TCL

RD/WR Control to ALE High

-5

TRD

Data out from RD Low

0

TLL

ALE width

TRDF

Data float after

ns
140

30

B[) High

---.--

0

ns
ns

5

ns

TRW

RDwidth

200

25000

ns

TWW

WRwidth

140

25000

ns

-

TOW

Data setup before WR High

40

TWO

Data hold afterWR High

10

TCKD

Data out after EXCLK Low

ns
---_.

TCKW

WR after EXCLK Low

150

TDCK

Data setup before EXCLK Low

150

TAC

Address setup before control*

50

TCA

Address hold after control*

50

TWH

Data Hold after EXCLK

20

Control for setup is the falling edge of RD or WR.
Control for hold is the falling edge of RD or the rising edge of WR.

3-220

ns

--- --

200

-..

_-_.._-

ns
ns
ns
ns

----_ ...
~---------

*

ns

_---

CSI Addr. hold after ALE Low

ns

--

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
ALE

~
~

~
TlC

---..L

TRW

-+

AD

J

------~--

TCl

+

TlC

1

J
--~

TWW

WA
TlA

L
ADO-AD7

as

TAL

,

TRD

.I!.i

~D

TRDF

~

TDW

'"

-1( ADDRESS }-----K READ DATA}-----K ADDRESS ~~~

-=1-

-~-

-~-

-~-

~~--

READ TIMING DIAGRAM (SERIAL VERSION)
EXClK

I'------+--------~----------r

AD

AO-A2

DATA

--+

WRITE TIMING DIAGRAM (SERIAL VERSION)

--1

EXClK

r=

--+------,rI TWW

_ - - + - -_ _ _ _ _ _ _ _ _

TCKW

AO-A2

----f------------------~··-----·-tf

DATA

3-221

I~

I~

TCA

I

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
APPLICATIONS INFORMATION
GENERAL CONSIDERATIONS
Figures 1 and 2 show basic circuit diagrams for
K-Series modem integrated circuits. K-Series products
are designed to be used in conjunction with a control
processor, a UART or RS-232 serial data interface,
and a DAA phone line interface to function as a typical
intelligent modem. The K-Series ICs interface directly
with Intel 8048 and 80C51 microprocessors for control
and status monitoring purposes.Two typical DAA arrangements are shown: one for a split ±5 or ±12
volt design and one for a single 5 volt design. These
diagrams are for reference only and do not represent
production-ready modem designs.

CA >-D-4-='----1
CB K.f+=',....--i
CC K.f~--I
co >-D-~.!.-.4

ViR

CF K.f-+-"-'-'----t

cs

ALE

SSI
K-SERIES
LOW
POWER
FAMILY

In most applications the controller will monitorthe serial
data for commands from the DTE and the received
data for break signals from the far end modem. I n this
way, commands to the modem are sent over the same
line as the transmitted data. In other applications the
RS-232 interface handshake lines are used for modem
control.

+ C6

C9
.1

K-Series devices are available with two control interface versions: one for a parallel multiplexed address/
data interface, and one for a serial interface. The
parallel version is intended for use with 8039/48 or
8031/51 microcontrollers from Intel or many other
manufacturers. The serial interface 22-pin version can
be used with other microcontrollers or in applications
where only a limited number of port lines are available
or the application does not lend itself to a multiplexed
address/data interface. The parallel versions may also
be used in the Serial mode, as explained in the data
sheet pin description.

m=

22

m=

C1
390 pF

RXA

BA
BB

OA
00
DB
U5, U6
MC145406

RESET

TXA L..L-lI-...J\AlI/'-----_ _ _ _ _---1

RING

~------------------------~

FIGURE 2: Single 5V Hybrid Version
3-223

I

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
Unlike digital logic circuitry, modem designs must
properly contend with precise frequency tolerances
and very low level analog signals, to ensure acceptable
performance. Using good analog circuit design practices will generally result in a sound design. Following
are additional recommendations which should be
taken into consideration when starting new designs.

CRYSTAL OSCILLATOR
The K-Series crystal oscillator requires a Parallel mode
(antiresonant) crystal which operates at 11.0592 MHz.
It is important that this frequency be maintained to
within ±0.01 % accuracy.
In order for a Parallel mode crystal to operate correctly
and to specification, it must have a load capacitor
connected to the junction of each of the crystal and
internal inverter connections, terminated to ground.
The values of these capacitors depend primarily on the
crystal's characteristics, and to a lesser degree on the
internal inverter circuit. The values used affect the
accuracy and start up characteristics of the oscillator.

LAYOUT CONSIDERATIONS
Good analogldigital design rules must be used to
control system noise in orderto obtain highest performance in modem deSigns. The more digital circuitry
present on the PC board, the more this attention to
noise control is needed. The modem should be treated
as a high impedance analog device. A 22 mF electrolytiC capacitor in parallel with a 0.1 mF ceramic capaCitor between VDD and GND is recommended.
Liberal use of ground planes and larger traces on
power and ground are also highly favored. High speed
digital circuits tend to generate a significant amount of
EMI (Electro-Magnetic Interference) which must be
minimized in order to meet regulatory agency limitations. To accomplish this, high speed digital devices
should be locally bypassed, and the telephone line
interface and K-Series device should be located close
to each other near the area of the board where the
phone line connection is accessed. To avoid problems, power supply and ground traces should be
routed separately to the analog and digital functions on
the board, and digital signals should not be routed near
low level or high impedance analog traces. The analog
and digital grounds should only connect at one point
near the K-Series device ground pin to avoid ground
loops. The K-Series modem IC's should have both
high frequency and low frequency bypassing as close
to the package as possible.

MODEM PERFORMANCE
CHARACTERISTICS
The curves presented here define modem IC performance under a variety of line conditions while inducing
disturbances that are typical of those encountered
during data transmission on public service telephone
lines. Test data was taken using an AEA Electronics'
"Autotest I" modem test set and line Simulator, operating under computer control. All tests were run fullduplex, using a Concord Data Systems 224 as the
reference modem. A 511 pseudo-random-bit pattern
was used for each data point. Noise was C-message
weighted and all signal-to-noise (SIN) ratios reflect
total power measurements similar to the CCITT V.56
measurement specification. The individual tests are
defined as follows.

BER vs. SIN
This test measures the ability of the modem to operate
over noisy lines with a minimum of data-transfer errors.
Since some noise is generated in the best of dial-up
lines, the modem must operate with the lowest SIN
ratio possible. Better modem performance is indicated
by test curves that are closest to the BER axis. A
narrow spread between curves representing the four
line parameters indicates minimal variation in performance while operating over a range of aberrant operating conditions. Typically, a DPSK modem will exhibit
better BER-performance test curves receiving in the
low band than in the high band.

BER vs. Receive Level
This test measures the dynamic range of the modem.
Because signal levels vary widely over dial-up lines,
the widest possible dynamic range is desirable. The
minimum Bell specification calls for 36 dB of dynamic
range. SIN ratios are held constant at the indicated
values while the receive level is lowered from a very
high to very low signal levels. The width of the "bowl"
ofthese curves, taken atthe BER point, is the measure
of dynamic range.

3-224

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem

*SSI 73K322L
BER vs PHASE JITTER

SSI73K322L
BER vs CARRIER OFFSET

10-2

10-2

r-

I HIGH BAND RECEIVE
I DPSK OPERATION
10-3

10-4

10-3

I--

I--

t:!

10-4

3002".SdBSlN

/'

V

I\..
~

10-S

~~

v

\

II

I

10-5

rt--- I--

C210.8dB SIN

1\

I

C211.3cBSfN

\

--

tr

l -I-pcl -I--

--~

v
I---" l -

V
.....

10- 6

10-6
4

0

8

16

12

12

24

20

4

8

*SS173K322L
BER vs SIN (V.23 ONLY)

J.

1

V.23 OPERATION
-40dBM

\

\

.A'
M-~o~;1\~

\1\
\ \

3002 Ea. OFF

H FLAT Ea. OFF
r-.....

IW
~

10-2

I

1

V.21 OPERATION-t-40dBM

\

t--

L.--1'

10-3

3002 EO. ON

' " FLAT HIGH BAND

\

l-

\

\

I

I-- H FLATEO

ON

t
2

3002 HIGH BAN 0

'\

\

~

1/

,1/

~

10-5

\\

1
IC2 EO

IK"

1-.\

10-6
0

'"

\

~\.

I

\

-2

l- I--

~

I

10-5

-

~~

\

\

-

\~

\ 1\
I-- HBACK CHANNEL

-

f"'"

\

10-4

r-

C2 HIGH BANDj-

\\

i\

y~

'(

\~

1\

10-3

I

\ \

-12

-8

SSI73K322L
BER vs SIGNAL TO NOISE

10-2
\

-4

0

CARRIER OFFSET (HZ)

PHASE JITTER (0 PEAK)

4

6

8

10

V

1

\

J~ ~ I--

\
\

1

1\
J

LOW BAND RECEIVE
FLAT, 3002, AND C2 LINES

0

1

2

3

4

5

6

7

8

SIGNAL TO NOISE (dB)

"EO On" Indicates bit CR1 D4 is set for additional phase equalization.

3-225

~

I

10. 6

12 14 16 18 20 22

SIGNAL TO NOISE (dB)

*

I

300211.8dB SIN

Ie---' V

)-'

10-4

~

I HIGH
BAND RECEIVE
DPSK OPERATION

L

9

10 11

12

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem

*SS173K322
BER vs RECEVE LEVEL (V.23)

*SS173K322L
BER vs SIGNAL TO NOISE

10-2

10-2

JI V.23
MAIN CHANNEL
RECEIVE OPERATION
C2 LINE, SiN = 9.5 dB

r-

I HIGH BAND
RECEIVE ~
·40dBm

\

f--

I

\

10.3

.L.

\\\ ~~
BPS

\

10.3

600
BPS

.\

~ c\- I--'

\\L .---

\

\

Clor3002
~

..........
FLAT
r--

\

\\-0\ rf

C1 or 3002]

I

C2
'--~

\' ~'t r--i

\

\ 'l\

Sre \l\\

I

/

10-5

\'¥H

\\

~ r -C2

10-4

10-4

DPSK OPERATION

\ ,\

10.5

~\I\
\

1

\

\

'{

\

...-

\ \

10-6

10-6
10

0

-10

-20

-30

-40

2

-50

4

*SS173K322
BER vs RECEVE LEVEL
10.2

JHIGH
BAND RECEIVE ~
DPSK OPERATION
C2 LINE

10-3

10-4

SIN -11.3dB

\

10-5

I

S/N-15dB
10-6
10

0

-10

-20

-30

-40

-50

RECEIVE LEVEL (dBm)

*

6

8

\ \
10

SIGNAL TO NOISE (dB)

RECEIVE LEVEL (dB)

I

'1\ \
1\ \ \

1\ \ \

./

"EQ On" Indicates bit CR1 D4 is set for additional phase equalization_

3-226

12

14

SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
PACKAGE PIN DESIGNATIONS
(Top View)
CLK

GND

RXA

XTL2

VREF

RXA
VREF

XTL1

GND

XTL1

RESET
ISET

ADO

RESET

AD1

ISET

AD2

RXCLK

AD3

RXD

AD4

TXD

3

4

2

1

28

27 26

5('

RXD

ADS

CS

TXD

ADS

EXCLK

,!

EXCLK

AD7

TXCLK

9

TXCLK

ALE

INT

100

20

RD

INT

WR

TXA

11

19

VDD

TXA

RD

VDD

RXCLK
A1

400-Mil
22-Pin DIP

6

25

n

8

J

24

PlCC PINOUTS

23

ARE THE SAME AS
THE 28-PIN DIP

22

rl

12 13

14 15

21

16 17 18

28-Pin
PLCC

600-Mil
28-Pin DIP

CAUTION: Use handling procedures necessary
for a static sensitive component.

ORDERING INFORMATION
ORDER NO.

PART DESCRIPTION

PKG.MARK

SSI 73K322L with Parallel Bus Interface
28-Pin 5V Supply
Plastic Dual-In-Line

73K322L-IP

73K322L-IP

Plastic Leaded Chip Carrier

73K322L-IH

73K322L-IH

73K322SL -I P

73K322SL-IP

SSI 73K322L with Serial Interface
22-Pin 5V Supply
Plastic Dual-In-Line

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914

0194 - rev.

3-227

Protected by the following Patents (4,691,172) (4,777.453)
©1989 Silicon Systems, Inc.

I

Notes:

3-228

SSI73K324L
CCITT V.22bis, V.22, V.21, V.23, Bell 212A
Single-Chip Modem
April 1994

DESCRIPTION

FEATURES

The 881 73K324L is a highly integrated single-chip
modem IC which provides the functions needed to
design a Quad-mode CCITT and Bell 212A compatible
modem capable of operation over dial-up lines. The
881 73K324L adds V.23 capability to the CCITT
modes of Silicon Systems' 73K224 one-chip modem,
allowing a one-chip implementation in designs intended for European marKets which require this added
Modulation mode. The 881 73K324L offers excellent
performance and a high level of functional integration
in a single IC. The device supports V.22bis, V.22, Bell
212A, V.21, and V.23 operating modes, allowing both
synchronous and asynchronous operation as defined
by the appropriate standard.
The 881 73K324L is designed to appear to the
Systems Engineer as a microprocessor peripheral,
and will easily interface with popular one-chip
microcontrollers (80C51 typical) for control of modem
functions through its 8-bit multiplexed address/data
bus. A serial control bus is available for applications not
requiring a parallel interface. An optional package with
only the serial control bus is also available. Data
communications occurs through a separate serial port.
(Continued)

One chip Multi-mode CCITT V.22bis, V.22, V.21,
V.23 and Bell 212A compatible modem data pump
FSK (75, 300, 1200 bit/s), DPSK (600, 1200 bitls),
or QAM (2400 bitls) encoding
Pin and software compatible with other
SSI K-Series family one-chip modems
Interfaces directly with standard microprocessors
(8048, 80C51 typical)
Serial and parallel microprocessor bus for control
Selectable asynch/synch with internal bufferl
debuffer and scrambler/descrambler functions
All synchronous (internal, external, slave) and
Asynchronous Operating modes
Adaptive equalization for optimum performance
over all lines
Programmable transmit attenuation (16 dB, 1 dB
steps), and selectable receive boost (+18 dB)
Call progress, carrier, answer tone, unscrambled
mark, S1, and signal quality monitors
DTMF, answer, calling, SeT and guard tone
generators
Test modes available: ALB, DL, RDL; Mark, Space
and Alternating bit pattern generators
CMOS technology for low power consumption
4-wire full duplex operation in all modes

BLOCK DIAGRAM

8· BIT
mp
BUS

VF

0494 - rev.

3-229

CAUTION: Use handling procedures necessary
for a static sensitive component.

I

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DESCRIPTION (Continued)
The SSI 73K324L offers full hardware and software
compatibility with other products in Silicon Systems'
K-Series family of single-chip modems, allowing system upgrades with a single component change. The
SSI 73K324L is ideal for use in free-standing or integral
system modem products where full-duplex 2400 bit/s
operation with Alternate mode capability is required. Its
high functionality, low power consumption, and efficient packaging simplify design requirements and
increase system reliability. A complete modem
requires only the addition of the phone line interface, a
control microprocessor, and RS-232 level converters
for a typical system.
The SSI 73K324L is designed to provide a complete
V.22bis, V.22, Bell 212A, V.21, and V.23 compatible
modem on a chip. Many functions were included to
simplify implementation in typical modem designs. In
addition to the basic 2400 bitls QAM, 1200/600 bitls
DPSK and 1200/300/75 bitls FSK modulator/demodulator sections, the device also includes synch/asynch
buffering, DTMF, answer, soft carrier, guard, and calling tone generator capabilities. Handshake pattern
detectors simplify control of connect sequences, and
precise tone detectors allow accurate detection of call
progress, answer, calling, and soft carrier turn off tones.
All Operating modes defined by the incorporated standards are included, and Test modes are provided. Most
functions are selectable as options, and logical defaults are provided. The device can be directly interfaced to a microprocessor via its 8-bit multiplexed
address/data bus for control and status monitoring.
Data communications takes place through a separate
serial port. Data may also be sent and received through
the control registers. This simplifies designs requiring
speed buffering, error control and compression.

FUNCTIONAL DESCRIPTION
QAM MODULATOR/DEMODULATOR

The SSI 73K324L encodes incoming data into quadbits represented by 16 possible signal points with
specific phase and amplitude levels. The baseband
signal is then filtered to reduce intersymbol interference on the band limited telephone network. The
modulator transmits this encoded data using either a
1200 Hz (Originate mode) or 2400 Hz (Answer mode)
carrier. The demodulator, although more complex,

essentially reverses this procedure while also recovering the data clock from the incoming signal. Adaptive
equalization corrects for varying line conditions by
automatically changing filter parameters to compensate for line characteristics.
DPSK MODULATOR/DEMODULATOR

The SSI 73K324L modulates a serial bit stream into
di-bit pairs that are represented by four possible phase
shifts as prescribed by the Bell 212A1V.22 standards.
The baseband signal is then filtered to reduce intersymbol interference on the band limited 2-wire PSTN
line. Transmission occurs on either a 1200 Hz (Originate mode) or 2400 Hz carrier (Answer mode).
Demodulation is the reverse of the modulation process, with the incoming analog signal eventually decoded into di-bits and converted back to a serial bit
stream. The demodulator also recovers the clock
which was encoded into the analog signal during
modulation. Demodulation occurs using either a
1200 Hz carrier (Answer mode or ALB Originate mode)
or a 2400 Hz carrier (Originate mode or ALB Answer
mode). The SSI 73K324L use a phase locked loop
coherent demodulation technique that offers excellent
performance. Adaptive equalization is also used in
DPSK modes for optimium operation with varying
lines.
FSK MODULATOR/DEMODULATOR

The FSK modulator/demodulator produces a frequency modulated analog output signal using two
discrete freqLJencies to represent the binary data. V.21
frequencies of 980 and 1180 Hz (originate mark and
space), or 1650 and 1850 Hz (answer mark and space)
are used in V.21 mode. V. 23 mode uses 1300 and
2100 Hz forthe main channel or 390 and 450 Hz forthe
back channel. Demodulation involves detecting the
received frequencies and decoding them into the
appropriate binary value. The rate converter and
scrambler/descrambler are automatically bypassed in
the FSK modes.
PASSBAND FILTERS AND EQUALIZERS

High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and to provide compromise delay
equalization as well as rejection of out-of-band signals.
The transmit signal filtering corresponds to a -v75%
raised cosine frequency response characteristic.

3-230

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
ASYNCHRONOUS MODE

PARALLEL CONTROL INTERFACE

The Asynchronous mode is used for communication
with asynchronous terminals which may transfer data
at 600, 1200, or 2400 bitls + 1%, -2.5% even though the
modem's output is limited to the nominal bit rate ±.01%
in DPSK and QAM modes. When transmitting in this
mode the serial data on the TxD input is passed
through a rate converter which inserts or deletes stop
bits in the serial bit stream in order to output a signal
that is the nominal bit rate ±.01%. This signal is then
routed to a data scrambler and into the analog modulator where di-bit or quad-bit encoding results in the
output signal. Both the rate converter and scrambler
can be bypassed for handshaking and synchronous
operation as selected. Received data is processed in
a similar fashion except that the rate converter now
acts to reinsert any deleted stop bits and output data to
the terminal at no greater than the bit rate plus 1%. An
incoming break signal (low through two characters) will
be recognized and passed through without incorrectly
inserting a stop bit.

Eight 8-bit registers are provided for control, option
select, and status monitoring. These registers are
addressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as seven consecutive memory locations. Six contol registers are read/write. The detect
and ID registers are read only and cannot be modified
except by modem response to monitored parameters.

The SYNC/ASYNC converter has an extended
Overspeed mode which allows selection of an output
speed range of either +1% or +2.3%. In the extended
Overspeed mode, some stop bits are output at 7/8 the
normal width.
Both the SYNC/ASYNC rate converter and the data
descrambler are automatically bypassed in the FSK
modes.
SYNCHRONOUS MODE
Synchronous operation is possible only in the QAM or
DPSK modes. Operation is similar to that of the Asynchronous mode except that data must be synchronized
to a clock and no variation in data transfer rate is
allowable. Serial input data appearing at TXD must be
valid on the rising edge of TXCLK.

SERIAL CONTROL INT,ERFACE
The Serial Command mode allows access to the
SSI 73K324L control and status registers via a serial
control port. In this mode the AO, A 1, and A2 lines
provide register addresses for data passed through the
DATA pin under control of the RD and WR lines. A read
operation is initiated when the RD line istaken low. The
next eight cycles of EXCLK will then transfer out eight
bits of the selected addresss location LSB first. A write
takes place by shifting in eight bits of data LSB first for
eight consectuive cycles of EXCLK. WR is then pulsed
low and data transfer into the selected register occurs
on the riSing edge of WR.
TONE GENERATOR
The DTMF generator controls the sending of the sixteen standard DTM F tone pairs. The tone pair sent is
determined by selecting TRANSMIT DTMF (bit D4)
and the 4 DTMF bits (DO-D3) of the TONE register.
Transmission of DTMF tones from TXA is gated by the
TRANSMIT ENABLE bit of eRO (bit D1) as with all
other analog signals.
FULL DUPLEX OPERATION
Four-wire full duplex operation is allowed in all modes.
This feature allows transmission and reception in the
same band for four wire applications only.

TXCLK is an internally derived 1200 or 2400 Hz Signal
in Internal mode and is connected internally to the
RXCLK pin in Slave mode. Receive data at the RXD pin
is clocked out on the falling edge of RXCLK. The
asynchlsynch converter is bypassed when Synchronous mode is selected and data is transmitted out at
essentially the same rate as it is input.

3-231

3

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
PIN DESCRIPTION
POWER
NAME

TYPE

DESCRIPTION

GND

I

System Ground.

VDD

I

Power supply input, 5V -5% +10%. Bypass with 0.22 IJ,F and 22 IJ,F capacitors
to GND.

VREF

0

An internally generated reference voltage. Bypass with 0.22 IJ,F capacitor to
GND.

ISET

I

Chip current reference. Sets bias current for op-amps. The chip current is set
by connecting this pin to VDD through a 2 MQ resistor. Iset should be bypass~d
to GND with a 0.22 IlF capacitor.

PARALLEL MICROPROCESSOR INTERFACE
ALE

I

Address latch enable. The falling edge of ALE latches the address on ADOAD2 and the chip select on CS.

ADOAD7

Address/data bus.These bidirectional tri-state multi-plexed lines carry information to and from the internal registers.

CS

I/O /
Tristate
I

ClK

0

Output clock. This pin is selectable under processor control to be either the
crystal frequency (for use as a processor clock) or 16 x the data rate for use
as a baud rate clock in QAM/DPSK modes only. The pin defaults to the crystal
frequency on reset.

INT

0

Interrupt. This open drain weak pullup, output signal is used to inform the
processor that a detect flag has occurred. The processor must then read the
detect register to determine which detect triggered the interrupt. INT will stay
active until the processor reads the detect register or does a full reset.

RD

I

Read. A low requests a read of the SSI 73K324l internal registers. Data
cannot be output unless both RD and the latched CS are active or low.

RESET

I

Reset. An active high signal on this pin will put the chip into an inactive state.
All control register bits (CRO, CR1, CR2, CR3, Tone) will be reset. The output
of the ClK pin will be set to the crystal frequency. An internal pull down resistor
permits power on reset using a capacitor to VDD.

WR

I

Write. A low on this informs the SSI73K324l that data is available on ADO-AD7
for writing into an internal register. Data is latched o..!!1he rising edge of WR.
No data is written unless both WR and the latched CS are low.

Chip select. A low on this pin allows a read cycle or a write cycle to occur. ADOAD7 will not be driven and no registers will be written if CS (latched) is not
active. CS is latched on the falling edge of ALE.

Note: The Serial Control mode is provided in the parallel versions by tying ALE high and CS low. In this
configuration AD7 becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2, respectively.

3-232

SSI73K324L
CCITI V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
RS-232 INTERFACE
NAME

TYPE

EXCLK

I

External Clock. This signal is used in synchronous transmission when the
external timing option has been selected. In the External Timing mode the
rising edge of EXCLK is used to strobe synchronous transmit data available
on the TXD pin. Also used for serial control interface.

RXCLK

OfTristate

Receive Clock Tri-statable. The falling edge of this clock output is coincident
with the transitions in the serial received DPSK/QAM data output. The rising
edge of RXCLK can be used to latch the valid output data. RXCLK will be valid
as long as a carrier is present. In V.23 orV.21 mode a clock which is 16 x 1200/
75 or 16 x 300 Hz data rate is output, respectively.

0

Received Data Output. Serial receive data is available on this pin. The data is
always valid on the rising edge of RXCLK when in Synchronous mode. RXD
will output constant marks if no carrier is detected.

OfTristate

Transmit Clock Tri-statable. This signal is used in synchronous DPSK/QAM
transmission to latch serial input data on the TXD pin. Data must be provided
so that valid data is available on the rising edge of the TXCLK. The transmit
clock is derived from different sources depending upon the Synchronization
mode selection. In Internal Mode the clock is generated internally (2400 Hz for
QAM, 1200 Hz for DPSK or 600 Hz for half-speed DPSK). In External Mode
TXCLK is phase locked to the EXCLK pin. In Slave Mode TXCLK is phase
locked to the RXCLK pin. TXCLK is always active. In V.23 or V.21 mode the
output is a 16 x 1200/75 or 16 x 300 Hz clock, respectively.

I

Transmit Data Input. Serial data for transmission is input on this pin. In
Synchronous modes, the data must be valid on the rising edge of the TXCLK
clock. In Asynchronous modes (2400/1200/600 bit/s, or 75/300 baud) no
clocking is necessary. DPSK/QAM data must be +1%, -2.5% or +2.3%, -2.5
% in Extended Overspeed mode.

RXD

TXCLK

TXD

DESCRIPTION

ANALOG INTERFACE
Received modulated analog signal input from the phone line.

RXA

I

TXA

0

Transmit analog output to the phone line.

XTL1
XTL2

I
I/O

These pins are forthe internal crystal oscillator requiring a 11.0592 MHz
Parallel mode crystal. Two capacitors from these pins to ground are also
required for proper crystal operation. Consult crystal manufacturer for proper
values. XTL2 can also be driven from an external clock.

-

.

3-233

.-

I

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
PIN DESCRIPTION (continued)
SERIAL MICROPROCESSOR INTERFACE
NAME

TYPE

DESCRIPTION

AO-A2

I

Register Address Selection. These lines carry register addresses and should
be valid during any read or write operation.

DATA

1/0

Serial Control Data. Data for a readlwrite operation is clocked in or out on the
falling edge of the EXCLK pin. The direction of data flow is controlled by the
RD pin. RD low outputs data. RD high inputs data.

RD

I

Read. A low on this input informs the SSI 73K324L that data or status
information is being read by the processor. The falling edge of the RD signal
will initiate a read from the addressed register. The RD signal must continue
for eight falling edges of EXCLK in order to read all eight bits of the referenced
register. Read data is provided LSB first. Data will not be output unless the RD
signal is active.

WR

I

Wrtte. A low on this input informs the SSI73K324L that data or status information
has been shifted in through the DATA pin and is available for writing to an internal
register. The normal procedure for a wrtte is to shift in data LSB first on the DATA
pin for eight consecutive falling edges of EXCLK and then to pulse WR low. Data
is wrttten on the rising edge of WR.

Note: In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the pins;
AO, A1, A2, DATA, and EXCLK. Also, the RD and WR controls are used differently.

3-234

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
REGISTER DESCRIPTIONS
Eight 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AO, A1 and
A2 address lines in Serial mode, orthe ADO, AD1 and
AD2 lines in Parallel mode. The address lines are
latched by ALE. Register CRO controls the method by
which data is transferred over the phone line. CR1
controls the interface between the microprocessor and

the SSI 73K324L internal state. DR is a detect register
which provides an indication of monitored modem
status conditions. TR, the tone control register, controls the DTMF generator, answer, guard tones, SCT,
calling tone, and RXD output gate used in the modem
initial connect sequence. CR2 is the primary DSP
control interface and CR3 controls transmit attenuation
and receive gain adjustments. All registers are read/
write except for DR and 10 which are read only.
Register control and status bits are identified below:

REGISTER BIT SUMMARY

CONTROL
REGISTER
a

MODULATION
TYPE
a

TRANSMIT
MODE
2

TRANSMIT
PATTERN
a

ENABLE
DETECT
INTERRUPT

BYPASS
SCRAMBLER!
ADD PH. EQ.
(V.23)

RECEIVE
LEVEL

PATTERN
S1 DET

RECEIVE
DATA

RXD
OUTPUT
CONTROL

TRANSMIT
GUARDTONEI
SCT/CALUNG
TONE
SPECIAL
REGISTER
ACCESS

000

MODULATION
OPTION

001

TRANSMIT
PATTERN
1

DR

010

TONE
CONTROL
REGISTER

TR

all

CONTROL
REGISTER
2

CR2

100

CR3

101

CONTROL
REGISTER
1
DETECT
REGISTER

CONTROL
REGISTER

CRO

CR1

3

TXDALT

MODULATION
TYPE
1

TRANSMIT
MODE
a

TRANSMIT
ENABLE

ANSWER!
ORIGINATE

CLK
CONTROL

RESET

TEST
MODE
1

TEST
MODE
0

UNSCR.
MARK
DETECT

CARRIER
DETECT

SPECIAL
TONE
DETECT

CALL
PROGRESS
DETECT

SIGNAL
QUAUTY

TRANSMIT
ANSWER
TONE

TRANSMIT
DTMF

DTMF3

DTMF21
4WIRE FOX

DTMFll
OVERSPEED

DTMFO/GUARDI
ANSWER!
CALUNG/SCT

CALL
INITlAUZE

TRANSMIT
Sl

16 WAY

RESET
DSP

TRAIN
INHIBIT

EQUALIZER
ENABLE

TRANSMIT
ATTEN.
2

TRANSMIT
ATTEN.
1

TRANSMIT
ATTEN.
0

RECEIVE
GAIN
BOOST

TRISTATE
TX/RXCLK

SPECIAL
REGISTER

SR

101

TX BAUD
CLOCK

RX UNSCR.
DATA

ID
REGISTER

10

110

10

ID

NOTE:

When a register containing reserved control
bits is written into, the reserved bits must be
programmed as O's.

3-235

TRANSMIT
MODE
1

TRANSMIT
ATTEN.

3

I

SSI73K324L
CCllT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
REGISTER ADDRESS TABLE

~~~~::~~HN

OAM: 0=2400 Bms
DPSK: 0=1200 Bms
l:j100BmS
FSK: 0=V.23
bV.21

----------'

0010=EXT SYNCH
0011 =SLAVE SYNCH
0100=ASYCH 8 BfTSICHAR
010bASYCH 9 BfTSICHAR
0110=ASYCH 10 BITSICHAR
011bASYCH 11 BITSICHAR
lXOO=FSK

O=DISABLE
TXA OUTPUT
1=ENABLE
TXA OUTPUT

O=ANSWER
bORIGINATE
in V.23
O=BC xmil
hMCxmit

GUARD:

0·1800 HZ
1·550 HZ
ANS WER: 0 . 2225 HZ
1 ·2100 HZ
CALLING: 0·1300 HZ
SCT'
1 ·900 HZ

O=ACCESS CRa
bACCESS
SPECIAL
REGISTER

O=DSP IN
O=NORMAL
DEMOD MODE
DOTTING
1=DSP IN CALL
1=S 1
PROGRESS
MODE

00XX=73K212L,322L, 321 L
01XX=73K221L,302L
1OXX= 73K222L
1100=73K224L
1110=73K324L
1101=73K312L

3-236

O=RX=TX
1=RX=16 WAY

O=DSP
INACTIVE
bDSP
ACTIVE

O=ADAPTEO
ACTIVE
l=ADAPT EO
FROZEN

O=ADAPTEO
IN INiT
1=ADAPT EO
OK TO ADAPT

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
CONTROL REGISTER 0

CRO
000

D7

D6

MODUL.
OPTION

MODUL.
TYPE 1

BIT NO.
DO

D4

D5

D3

D2

D1

DO

MODUL. TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/
TYPE 0
MODE 2
MODE 1
MODEO
ENABLE ORIGINATE

NAME

CONDITION

Answer/
Originate

0

Selects Answer mode (transmit in high band, receive in
low band) or in V.23 HDX mode, receive at 1200 bitls
and transmit at 75 bit/so

1

Selects Originate mode (transmit in low band,receive
in high band) or in V.23 HDX mode, receive at 75 bitls
and transmit at 1200 bit/so

DESCRIPTION

Note: This bit works with Tone Register bits DO and D6
to program special tones detected in the Detect Register. See Detect and Tone Registers.
D1

Transmit

0

Enable

1

Disables transmit output at TXA.
Enables transmit output at TXA.
Note: Transmit Enable must be set to 1 to allow
activation of Answer Tone, DTMF, or Carrier.

D5 D4 D3 D2
D5, D4,
D3,D2

Transmit
Mode

0

0

0

0

Selects Power Down mode. All functions disabled
except digital interface.

0

0

0

1

Internal Synchronous mode. In this mode TXCLK is an
internally derived 600, 1200 or 2400 Hz signal. Serial
input data appearing at TXD must be valid on the rising
edge of TXCLK. Receive data is clocked out of RXD on
the falling edge of RXCLK.

0

0

1

0

External Synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 600, 1200 or 2400 Hz clock
must be supplied externally.

0

0

1

1

Slave Synchronous mode. Same operation as other
Synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.

0

1

0

0

Selects Asynchronous mode - 8 bits/character (1 start
bit, 6 data bits, 1 stop bit).
--

0

1

0

0

1

1

0

0

1

1

1

Selects Asynchronous mode - 11 bits/character (1 start
bit, 8 data bits, Parity and/or 1 or 2 stop bits).

1

X

0

0

Selects FSK operation.

-

1
--_ .. -

Selects Asynchronous mode - 9 bits/character (1 start
bit, 7 data bits, 1 stop bit).
Selects Asynchronous mode -1 0 bits/character (1 start
bit, 8 data bits, 1 stop bit).

-----

3-237

I

SSI73K324L
CCITI V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
CONTROL REGISTER 0 (Continued)
SIT NO.
D6,D5

NAME

CONDITION

Modulation

D6 D5
1 0

Type
D7

Modulation
Option

DESCRIPTION
QAM

0

0

DPSK

0

1

FSK

0

QAM selects 2400 bit/s. DPSK selects 1200 biVs.
FSK selects V.23 mode.
- -----

1

DPSK selects 600 biVs.
FSK selects V.21 mode.

CONTROL REGISTER 1

CR1
001
SIT NO.

D7

D6

TRANSMIT
PATIERN
1

TRANSMIT
PATIERN
0

NAME

D5

D4

D3

ENABLE
BYPASS
ClK
DETECT SCRAMBI CONTROL
INT.
ADD PH.EQ

CONDITION

D2

D1

DO

RESET

TEST
MODE
1

TEST
MODE
0

DESCRIPTION

D1 DO
D1,DO

D2

Test Mode

Reset

0

0

Selects Normal Operating mode.

0

1

Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same carrier frequency as the transmitter. To
squelch the TXA pin, transmit enable bit must be low.
Tone Register bit D2 must be zero.

1

0

Selects remote digitalloopback. Received data is looped
back to transmit data internally, and RXD is forced to a
mark. Data on TXD is ignored.

1

1

Selects local digitalloopback. Internally loops TXD back
to RXD and continues to transmit data_carrrier at TXA pin.

0

Selects normal operation.

1

Resets modem to power down state. All control register
bits (CRO, CR1, CR2, CR3 and Tone) are reset to zero
except CR3 bit D2. The output of the clock pin will be set
to the crystal frequency.

--

D3

ClK Control
(Clock Control)

0

Selects 11.0592 MHz crystal echo output at ClK pin.

1

Selects 16 X the data rate output at ClK pin in QAM and
DPSK only.

3-238

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
CONTROL REGISTER 1

CR1
001
BIT NO.
04

05

07,06

(Continued)

07

06

TRANSMIT
PATTERN
1

TRANSMIT
PATTERN
0

05

04

03

ENABLE
BYPASS
ClK
DETECT SCRAMB/ CONTROL
INT.
ADD PH.EO.

02

01

DO

RESET

TEST
MODE
1

TEST
MODE
0

NAME

CONDITION

Bypass
Scrambler/
Add Ph. Eq.

0

Selects normal operation. OPSK and OAM data is
passed through scrambler.

1

Selects Scrambler Bypass. OPSK and OAM data is
routed around scrambler in the transmit path. In the V.23
mode, additional phase equalization is added to the main
channel filters when 04 is set to 1.

Enable Detect
Interrupt

0

Disables interrupt at INT pin. All interrupts are normally
disabled in Power Down mode.

1

Enables INT output. An interrupt will be generated with a
change in status of DR bits 01-04 and 06. The answer
tone and call progress detect interrupts are masked
when the TX enable bit is set. Carrier detect is masked
when TX OTM F is activated. All interrupts will be disabled
if the device is in Power Down mode.

Transmit
Pattern

DESCRIPTION

07

06

0

0

Selects normal data transmission as controlled by the
state of the TXO pin.

0

1

Selects an alternating mark/space transmit pattern for
modem testing and handshaking. Also used for S1 pattern generation. See CR2 bit 04.

1

0

Selects a constant mark transmit pattern.

1

Selects a constant space transmit pattern.

1

3-239

I

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DETECT REGISTER
D7
DR
010

BIT NO.
DO

D1

D2

D6

RECEIVE
S1
LEVEL
PATTERN
INDICATOR DETECT

D5

D4

D3

D2

D1

DO

RECEIVE
DATA

UNSCR.
MARK
DETECT

CARRIER
DETECT

SPECIAL
TONE
DETECT

CALL
PROG.
DETECT

SIGNAL
QUALITY
INDICATOR

NAME

CONDITION

Signal Quality
Indicator

0

Indicates normal received signal.

1

Indicates low received signal quality (above average error
rate). Interacts with Special Register SQ bits D2, D1.

Call Progress
Detect

0

No call progress tone detected.

1

Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in the
normal 350 to 620 Hz call progress band.

Special Tone
Detect

0

Condition not detected

1

Condition detected

DESCRIPTION

---------

CRO DO TR DO CR205

D3

D4

D5

D6

D7

Carrier Detect

Unscr. Mark
Detect

1

0

1

2225 Hz ±10 Hz answer tone detected in V.22bis, V.22,
V.21 modes.

1

1

1

2100 Hz ±21 Hz answer tone detected in V.22bis, V.22,
V.21 modes.

0

X

0

900 Hz SCT tone detected in V.23 mode.

I

X

0

2100 Hz or 2225 Hz answer tone detected in QAM, DPSK,
or V.21 Mode.

0

No carrier detected in the receive channel.

1

Indicated carrier has been detected in the received
channel. Should be time qualified by software.

0

No unscrambled mark being received.

1

Indicates detection of unscrambled marks in the received
data. Should be time qualified by software.

Receive
Data

Continuously outputs the received data stream.
This data is the same as that output on the RXD pin, but it
is not disabled when RXD is tri-stated. - - - - - - -

S1 Pattern
Detect

0

No S1 pattern being received.

1

S1 pattern detected. Should be time qualified by software.
S1 is an unscrambled double dibit (11001100 ... ) sent in
DPSK 1200 bitls mode. Generated pattern must be properly aligned to transmitter qaud clock_!O be detected.

Receive Level
Indicator

0

Received signal level below threshold,
(== -25 dBmO);can use receive gain boost (+18 dB.)

1

Received signal above threshold.

3-240

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
TONE REGISTER
07
TR
011

06

05

04

RXD
TRANSMIT TRANSMIT
OUTPUT
GUARDI
ANSWER
CONTR. CALLING/SCT
TONE
TONE

SIT NO.

NAME

CONDITION
06 05 D4 DO

00,04,
05,06

TRANSMIT
OTMF

03

02

DTMF 21
WIRE
OTMF 3
FOX

01

DO

OTMF 11
OVERSPEED

OTMF 01
G.T.lANSW.I
CALLING/SCT
TONE/SEL

DESCRIPTION
DO interacts with bits 06, D5, 04, and CRO as shown.

DTMF 01
Guard Tonel
Answer Tonel
Cailing/SCT

X

X

1

X

Transmit DTMF tones (overides all other functions).

1

0

0

0

Select 1800 Hz guard tone if in V.22bis or V.22 and
Answer mode in CRO.

Tonel

1

0

0

1

Select 550 Hz guard tone if in V.22bis or V.22 and
Answer mode in CRO.

Transmit
Select

D1

Note: Bit DO also selects the answer tone detected in Originate mode, see
Detect Register Special Tone Detect (bit 02) for details.
1

0

0

0

1300 Hz calling tone will be transmittted if V.21, V.22,
V.22bis or V.23 Originate mode is selected in CRO.

X

1

0

0

Transmit 2225 Hz Answer Tone. Must be in OPSK
Answer mode.

X

1

0

1

Transmit 2100 Hz Answer Tone. Must be in OPSK
Answer mode.

1

0

0

1

900 Hz SCT (soft carrier turnoff) tone transmitted in
V.23 75 bitls Receive mode. (CRO bit DO = 1).

04 01
OTMF 11
Overspeed

02

01 interacts with 04 as shown.

0

0

Asynchronous OAM/OPSK +1% -2.5%. (Normal).

0

1

Asynchronous OAM/OPSK, 2400, 1200 or 600 bitls
+2.3% -2.5%. (Extended overspeed).

04 02
DTMF 21
4WIRE
FOX

0

0

Selects 2-wire full-duplex or half-duplex.

0

1

02 selects 4 wire full duplex in the Modulation mode
selected. The receive path corresponds to the ANSI
ORIG bit CRO DO in terms of high or low band selection.
The transmitter is in the same band as the receiver, but
does not have magnitude filtering or equalization on its
signal as in the receive path.

Note: DTMFO - DTM F2 should be set to an appropriate state after DTM F dialing to avoid unintended operation.

3-241

I

SSI73K324L
CCITI V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
TONE REGISTER
07
TR
011

(Continued)

06

05

04

RXO
TRANSMIT
TRANSMIT
GUARD/
OUTPUT
ANSWER
CONTR. CALLING/SCT
TONE
TONE

BIT NO.

NAME

CONDITION

03,02,
01, DO

DTMF 3,
2,1,0

04

=1

03

02

01

OTMF 21
DTMF3
WIRE
FOX

TRANSMIT
OTMF

DO

OTMF 11
DTMF 0/
OVERGUARD/
SPEED CALLING/SCT
TONE SEL

DESCRIPTION
Programs 1 of 16 DTMF tone pairs that will be
transmitted when TX DTM F and TX enable bit (CRO, bit
01) is set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT

DTMF CODE
03 02 01 DO

TONES
LOW HIGH

1

0

0

0

1

697

2

0

0

1

0

697

1336

1

697

1477

1209

3

0

0

1

4

0

1

0

0

770

1209

5

0

1

0

1

770

1336

0

770

1477

6

0

1

1

7

0

1

1

1

852

1209

8

1

0

0

0

852

1336

9

1

0

0

1

852

1477

0

1

0

1

0

941

1336

-----

07

RXO Output
Control

----

*

1

0

1

1

941

1209

#

1

1

0

0

941

1477

A

1

1

0

1

697

1633

B

1

1

1

0

770

1633

C

1

1

1

1

852

1633

0

0

0

0

0

941

1633

0

Enables RXD pin. Receive data will be output on
RXD.

1

Disables RXD pin.The RXD pin reverts to a high
impedance with internal weak pull-up resistor.

3-242

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
CONTROL REGISTER 2

CR2
100

BIT NO.

DO

01

02

03

04

05

06

07

06

05

04

0

SPEC
REG
ACCESS

CALL
INIT

TRANSMIT
S1

03
16 WAY

D1

DO

TRAIN
INHIBIT

EQUALIZER
ENABLE

02
RESET
OSP

NAME

CONDITION

Equalizer
Enable

0

The adaptive equalizer is in its initialized state.

1

The adaptive equalizer is enabled. This bit is used in
handshakes to control when the equalizer should
calculate its coefficients.

Train
Inhibit

0

The adaptive equalizer is active.

1

The adaptive equalizer coefficients are frozen.

RESET OSP

0

The OSP is inactive and all variables are initialized.

1

The OSP is running based on the mode set by other
control bits

0

The receiver and transmitter are using the same decision plane (based on the Modulator Control Mode).

1

The receiver, independent of the transmitter, is forced
into a 16 point decision plane. Used for QAM handshaking.

0

The transmitterwhen placed in alternating Mark/Space
mode transmits 01 01 .... scrambled or not dependent
on the bypass scrambler bit and Modulation mode.

1

When this bi~ is 1 and only when the transmitter is
placed in alternating Mark/Space mode by CR1 bits
07, 06, an unscrambled repetitive double dibit pattern
of 00 and 11 at 1200 bitls (S1) is sent.

0

The OSP is setup to do demodulation and pattern
detection based on the Various mode bits. Both answer
tones are detected in Oemod Mode concurrently; TR
DO is ignored.

1

The OSP decodes call progress, calling tones, unscrambled mark, and 2100 Hz and 2225 Hz answer
tones.

Special
Register
Access

0

Normal CR3 access.

1

Setting this bit and addressing CR3 allows access to
the SPECIAL REGISTER. See the SPECIAL REGISTER for details.

N/A

0

Must be 0 for normal operation.

16 Way

Transmit
S1

Cailinit

DESCRIPTION

--

07

3-243

I

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
CONTROL REGISTER 3
07
CR3
101

06

TXOALT TRISTATE
TXlRXCLK

BIT NO.

NAME

05

04

0

RECEIVE
ENABLE
BOOST

CONDITION

03

02

01

00

TRANSMIT TRANSMIT TRANSMIT TRANSMIT
ADEN.
ADEN.
ATTEN.
ATTEN.
2
1
0
3
DESCRIPTION

03 02 01 00

o-

Sets the attenuation level of the transmitted signal
in 1dB steps. The default (03-00=0100) is for a transmit level of -10 dBmO. The total range is 16 dB.

03,02,
01,00

Transmit
Attenuator

04

Receive
Gain Boost
(18 dB)

0

18 dB receive front end boost is not used.

1

Boost is in the path. This boost does not change
reference levels. It is used to extend dynamic range by
compensating for internally generated noise when
receiving weak signals. The receive level detect signal
and knowledge of the hybrid and transmit attenuator
setting wi" determine when boost should be enabled.

05

Not Used

0

Not used. Only write zeros this location.

06

Tristate
TXCLKlRXCLK

0

TXCLK, RXCLK outputs driven

1

TXCLK, RXCLK outputs in Tristate mode

TXOALT

Spec. Reg. bit 03=1

07

0
1

0
1

0
1

1

Alternate TX data source. See Special Register.

10 REGISTER
SPECIAL REGISTER
06

03

05

TXO
SOURCE

SR
101

02

01

SIGNAL
QUALITY
LEVEL
SELECT1

SIGNAL
QUALITY
LEVEL
SELECTO

06

TXBAUO CLK

TXBAUO clock is the transmit baud-synchronous clock that can be used to
synchronize the input of arbitrary quad/di-bit patterns. The rising edge of
TXBAUO signals the latching of a baud-worth of data internally. Synchronous
data to be entered via the TXOALT bit, CR3 bit 07, should have data
transitions that start 1/2 bit
riod
from the TXBAUO clock edges.

05

RXUNOSCR
OATA

This bit outputs the data received before going to the descrambler. This is
useful for sending special unscrambled patterns that can be used for signaling.

3-244

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
SPECIAL REGISTER (Continued)
NAME

BIT NO.
D3

D2, D1

DESCRIPTION

TXD SOURCE

This bit selects the transmit data source; either the TXD pin if ZERO or the
TXDALTifthisbit isaONE. The TRANSMIT PATTERN bits 07 and 06 in CR1
override either of these sources.

SIGNAL
OUALITY
LEVEL
SELECT

The signal quality indicator is a logical zero when the signal received is
acceptable for low error rate reception. It is determined by the value of the
Mean Squared Error (MSE) calculated in the decisioning process when
compared to a given threshold. This threshold can be set to four levels of error
rate. The SOl bit will be low for good or average connections. Asthe error rate
crosses the threshold setting, the SOl bit will toggle at a 1.66 ms rate. Toggling
will continue until the error rate indicates that the data pump has lost
convergence and a retrain is required. At that point the sal bit will be a ONE
constantly. The SOl bit and threshold selection are valid for OAM and DPSK
only.

D2

D1

TYPICAL
THRESHOLD VALUE

0

0

10-5

BER (default)

0

1

10-6

BER

1

0

10-4

BER

1

1

10-3

BER

UNITS
----

_.------

NOTE: This register is "mapped" and is accessed by setting CR2 bit D6 to a ONE and addressing CR3. This
register provides functions to the 73K324L user that are not necessary in normal communications.
Bits D7-D4 are read only, while 03-00 are read/write. To return to normal CR3 access, CR2 bit D6
must be returned to a ZERO.

ID
110

D7

D6

D5

D4

ID
3

ID
2

ID
1

ID
0

CONDITION

1

D3

I

BIT NO.

D7, D6, D5,

Device

0

Identification

0

1

Signature

1

0

1

1

0

0

SSI73K224L

1

1

1

0

SSI73K324L

1

1

0

1

SSI73K312L

D4

0

1

D1

DESCRIPTION
Indicates Device:

X

SSI73K212Lor73K322Lor73K321L

X

X

SSI73K221Lor73K302L

X

X

SSI73K222L

X

-------.-

3-245

I

DO

USER DEFINABLE PERSONALITY

NAME

D7 D6 D5 D4

D2

I

I

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER

RATING

VDD Supply Voltage

7V

Storage Temperature

-65 to 150°C

Soldering Temperature (10 sec.)

260°C

Applied Voltage

-0.3 to VDD+0.3V

Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
PARAMETER

CONDITIONS

VDD Supply voltage

MIN

NOM

4.5

5

External Components (Refer to Application section for placement.)

MAX

UNITS

5.5

V

_L
",---

(VREF to GND)

Bias setting resistor

(Placed between VDD
and ISET pins)

ISET Bypass capacitor

(ISET pin to GND)

0.22

~F

VDD Bypass capacitor 1

(VDDto GND)

0.22

~F

VDD Bypass capacitor 2

(VDDto GND)

22

XTL 1 Load Capacitance

Depends on crystal requirements

XTL2 Load Capacitance
Clock Variation

0.22

~F

VREF Bypass capacitor

1.8

TA, Operating Free-Air
Temperature

3-246

2

f---

2.2

MQ

~F

18

Depends on crystal requirements
(11.0592 MHz) Crystal or
external clock

- --

39

pF

27

pF

-0.01

+0.01

%

-40

85

°C

18

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VDD =recommended range unless otherwise noted.)
PARAMETER

CONDITIONS

100, Supply Current

ClK

MIN

NOM

MAX

UNITS

18

25

rnA

5

rnA

0.8

V

= 11.0592 MHz
= 2 MQ

ISET Resistor
IDD1, Active

Operating with crystal oscillator.

IDD2, Idle

< 5 pF capacitive load on ClK pin.

--_._--

Digital Inputs
Vll, Input low Voltage

- -

VIH, Input High Voltage
All Inputs except Reset
XTl1, XTl2

2.0

VDD

V

Reset, XTl1 , XTl2

3.0

VDD

V

100

~

IIH, Input High Current

VI = VDD

Ill, Input low Current

VI =OV

Reset PUll-down Current

Reset = VDD

-2

VOH, Output High Voltage

IO=IOH Min
lOUT = -0.4 rnA

2.4

VOL, Output low Voltage

10 = lOUT = 1.6 rnA

RXD Tri-State Pull-up Curr.

RXD

~

-200
-30

-70

~

VDD

V

0.4

V

-50

~

---'--------

Digital Outputs

= GND

-2

Capacitance

Maximum Capacitive load
ClK
Input Capacitance

All Digital Inputs

3-247

25

pF

10

pF

I

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.)
PARAMETERS

CONDITIONS

MIN

NOM

MAX

UNITS

QAM/DPSK Modulator
Carrier Suppression

Measured at TXA

Output Amplitude

TX scrambled marks
ATT=0100 (default)

35
-11.5

dB

f

-10.0

-9

dBmO

------

FSK Modulator/Demodulator
Output Freq. Error

ClK = 11.0592 MHz

Transmit level

ATT = 0100 (Default)
Transmit Dotting Pattern

TXA Output Distortion

All products through BPF

Output Bias Distortion
at RXD

Dotting Pattern measured at RXD
Receive level -20 dBm, SNR 20 dB

Output Jitter at RXD
Sum of Bias Distortion and
Output Jitter at RXD

-.31
-11.5

+0.20

%

-9

dBmO

-45

dB

-10.0

-10

+10

%

Integrated for 5 seconds

-1 S.

+15

%

Integrated for 5 seconds

-15

+15

%

-9

dBmO

-40

dB

-----

2100 Hz Answer Tone Generator
Output Amplitude

ATT = 0100 (Default level)
Not in V.21 or V.23 Mode

Output Distortion

Distortion products in receive band

DTMF Generator

-11.5

-_._---

Not in V.21 or V.23 mode

FreQ. Accuracy

=: 0100

-0.03

+0.25

0/0

-10

-8

dBmO

Output Amplitude

low Band ATT

OutlLut AmQlitude

Hiah Band ATT = 0100

-8

Twist

Hiah-Band to low-Band

1.0

Receiver Dynamic Range

Refer to Performance Curves

-43

Call Prog ress Detector

In Call Init mode

Detect level

460 Hz input sigIlal

2.0

--

-34

Reject level
DelavTime

-10

--

-70 dBmO to -30 dBmO STEP

Hold Time

-30 dBmO to -70 dBmO STEP

Hysteresis

@ 460 Hz input signal

-6

dBmO

3.0

dB

-3.0

dBmO

0

dBmO

-40

dBmO

25

ms

25

ms

2

NOTE: Parameters expressed in dBmO refer to the following definition:

odB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.
3-248

dB

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS

CONDITIONS

MIN

NOM

MAX

UNITS

-43

dBmO

Carrier Detect Receive Gain Boost "On" for Lower Input Level Measurements
Threshold

OAM/DPSK or FSK receive data

Hysteresis

All Modes

2

70 dBmO to -6 dBmO

25

70 dBmO to -40 dBmO

25

-70 dBmO to -6 dBmO

7

-70 dBmO to -40 dBmO

7

-70 dBmO to -6 dBmO

25

-70 dBmO to -40 dBmO

25

-6 dBmO to -70 dBmO

Delay Time

FSK
DPSK
OAM

Hold Time

-48

-- 1-------

-----_.- 1-------

dB

------

-

37
----- 1 - - - - - - -

-----

--1---

c-----

-----_.

ms

37

ms

17

ms

17

ms

37

ms

37

ms

25

37

ms

-40 dBmO to -70 dBmO

15

30

ms

DPSK

-6 dBmO to -70 dBmO

20

29

ms

-40 dBmO to -70 dBmO

14

21

ms

OAM

-6 dBmO to -70 dBmO

25

32

ms

28

ms

-43

dBmO

50

ms

FSK

-40 dBmO to -70 dBmO

---

-----

-

_._------

8

---

~~--------

Special Tone Detectors
Detect Level

See definitions for DO of Tone Register

-48
--

_ .. _--

- --

---

--

Delay and Hold Time
- - ------

2225 or 2100 Hz
answer tone
900 Hz SCT
Receive V.23 main channel

CalilNIT mode
2225 ± 10 Hz
2100±21 Hz

6

Tone Accuracy ±9 Hz

10

-----

45
~--------

Hysteresis

Pattern Detectors

2

-----

-

--.~----

ms
r----~~

dB

-- -

DPSK Mode
----

S1 Pattern
Delay Time

For signals from -6 to -40 dBmO,

10

Hold Time

Demod Mode

10

---

Unscrambled Mark

-------

--

ms
ms

45

ms

45

ms

-_.".-_._ ..-

Delay Time

For signals from -6 to -40

10

Hold Time

Demod or call Init Mode

10

--

-----_ ...

Receive Level Indicator

---

-22

Detect On

~---

Valid after Carrier Detect

55
45

DPSK Mode

1

3-249

4

-"-

-28

dBmO

7

ms

I

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS

CONDITIONS

MIN

NOM

MAX

UNITS

300

0

Output Smoothing Filter
Output Impedance
Output Load

TXA pin

200

TXA pin; FSK Single

--

10

kO

Tone out for THO = -50 dB
in 0.3 to 3.4 kHz range

50

pF

-35

dBmO

-55

dBmO

-65

dBmO

~---

Maximum Transmitted

4 kHz, Guard Tones off

Energy

10 kHz, Guard Tones off

----1--

12 kHz, Guard Tones off

--------_.

Anti Alias Low Pass Filter
Maximum allowed
Out-of-Band Signal Energy
(Defines Hybrid TransHybrid loss requirements)

Scrambled data at 2400 bit/s in
opposite band

-14
-9

Sinusoids out of band

---

Transmit Attenuator

r

dBm
dBm

----~----

Range of Transmit Level

Default ATT
1111-0000

= 0100 (-10 dBmO)

-21

-6

dBmO

+0.15

dB

----

-0.15

Step Accuracy
Clock Noise

mVrms

1.5

TXA pin; 153.6 kHz

--~

-------

Carrier Offset
Capture Range

Originate or Answer

-7

±5

r~_ +7

Hz

I~

%

Recovered Clock
Capture Range

% of data rate originate or answer

-.02

+.02

Guard Tone Generator
Tone Accuracy

550 Hz

Tone Level

550 Hz

-4.5

-3.0

(Below QAM/DPSK Output)

1800 Hz

-7.5

-6.1

Harmonic Distortion
(700 to 2900 Hz)

550 or 1800 Hz

%

+1.2
-0.8

1800 Hz

3-250

%

---

-1.5

dB

-4.5

dB

-50

dB

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS

CONDITIONS

MIN

Timing (Refer to Timing Diagrams)

NOM

UNITS

----------

Parallel Mode:

- --

TAL

CS/Addr. setup before ALE Low

30

TLA

CSI Addr. hold after ALE Low

6

TLC

ALE Low to RDIWR Low

40

TCL

RD/WR Control to ALE High

10

TRD

Data out from RD Low

TLL

ALE width

TRDF

Data float after RD High

TRW

MAX

--

ns
----

ns
ns
90

25

-

ns

---

ns
ns

--

40

ns

RDwidth

70

ns

TWW

WRwidth

70

ns

TOW

Data setup ~efore WR High

70

ns

TWO

Data hold after WR High

20

ns

TRCK

Clock high after RD

250

TAR

Address setup before RD low

TRA

Address hold after RD low

TRD

RD to data valid

TRDF

Data float after RD high

TCKDR

Read data out after falling edge
of EXCLK

TWW

WRwidth

TAW

Address setup before WR

50

TWA

Address hold after rising edge of WR

50

ns

TCKDW

Write data hold after falling edge
of EXCLK

200

ns

TCKW

WR high after falling edge of EXCLK

330

TDCK

Data setup before falling edge
of EXCLK

T1, T2

Minimum period

Serial Mode:

---

T1

ns
ns

0

ns

350
110

ns

50

ns

300

ns

---~----

350

ns

----

T1& T2

ns

50

ns

500

ns

Note: T1 and T2 are the lowlhigh periods, respectively, of EXCLK in Serial mode.

3-251

ns

--

I

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
ALE

~
~

~

TlC

I..L

TRW

-'t-

RD

~ TCl

.J

+

TlC

TLA

L

ADO-AD?

1

TWW

-+

WR

---K

cs ~-

TAL

"

J

TRD

~

~

I TWO

TRDF

~

I..

TOW

~ .. ••1

ADDRESS ) t - - - K READ DATA)t---K ADDRESS ) t - - - KWRITE DAT1--

-~-

-4-

-4-

READ TIMING DIAGRAM (SERIAL VERSION)
EXCLK

I~--~------------rAO-A2

+-----~~------------------------------

DATA

WRITE TIMING DIAGRAM (SERIAL VERSION)
EXCLK

AO-A2 - - - - - \ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - t t A

DATA

3-252

-----

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
APPLICATIONS INFORMATION
GENERAL CONSIDERATIONS
Figures 1 and 2 show basic circuit diagrams for
K-Series modem integrated circuits. K-Series products
are designed to be used in conjunction with a control
processor, a UART or RS-232 serial data interface,
and a DAA phone line interface to function as a typical
intelligent modem. The K-Series ICs interface directly
with Intel 8048 and 80C51 microprocessors for control
and status monitoring purposes.Two typical DAA
arrangements are shown: one for a split ±5 or ±12
volt design and one for a single 5 volt design. These
diagrams are for reference only and do not represent
production-ready modem designs.

C9
.1 nF

RS232
LEVEL
CONVERTERS

K-Series devices are available with two control interface versions: one for a parallel multiplexed address/
data interface, and one for a serial interface. The
parallel version is intended for use with 8039/48 or
8031/51 microcontrollers from Intel or many other
manufacturers. The serial interface 22-pin version can
be used with other microcontrollers or in applications
where only a limited number of port lines are available
or the application does not lend itself to a multiplexed
address/data interface. The parallel versions may also
be used in the Serial mode, as explained in the data
sheet pin description.
In most applications the controllerwill monitor the serial
data for commands from the DTE and the received
data for break signals from the far end modem. In this
way, commands to the modem are sent over the same
line as the transmitted data. In other applications the
RS-232 interface handshake lines are used for modem
control.

+

C8

22nF

C1
390 pF

CA H>-+--=:~

CBKI-~~

cc

KI-+--=::;..-...l

CD

H>+-=.!-...j

R4
20K

iNA
ALE

cs

SSI
K-SERIES
LOW
POWER
FAMILY

R4
5.1K

R3
3.6K

BA 1.>-1---::':-"'-+---t----1f---+--+BB

DA 1.>-r--,=::.=:.:----t----1f---+--DD
DB

RXCLK
TXCLK

us, us
MC14S406

..r

R9
10K

FIGURE 1: Basic Box Modem with Dual-Supply Hybrid

3-253

VR1

MOV
V250L20

I

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DIRECT ACCESS ARRANGEMENT (DAA)

data, these signals will clip if a single-ended drive
approach is used. The bridged driver uses an extra opamp (U1A) to invert the signal coming from the gain
setting op-amp (U1 B) before sending it to the other leg
of the transformer. Each op-amp then supplies half the
drive Signal to the transformer. The receive amplifier
(U1 C) picks off its signal at the junction of the impedance matching resistor and the transformer. Because
the bottom leg of the transformer is being driven in one
direction by U1A and the resistor is driven in the
oPPOsite direction at the same time by U1 B, the junction of the transformer and resistor remains relatively
constant and the receive signal is unaffected.

The telephone line interfaces show two examples of
how the "hybrid" may be implemented. The split supply
design (Figure 1) is a typical two op-amp hybrid. The
receive op-amp serves two purposes. It supplies gain
to amplify the receive signal to the proper level for the
modem's detectors and demodulator, and it removes
the transmitted signal from the receive signal present
at the transformer. This is done by supplying a portion
of the transmitted signal to the non-inverting input of
the receive op-amp at the same amplitude as the signal
appearing at the transformer, making the transmit
signal Common mode.

DESIGN CONSIDERATIONS

The single-supply hybrid is more complex than the
dual-supply version described above, but its use
eliminates the need for a second power supply. This
circuit (Figure 2) uses a bridged drive to allow undistorted signals to be sent with a single 5 volt supply.
Because DTM F tones utilize a higher amplitude than

Silicon Systems' 1-chip modem products include all
basic modem functions. This makes these devices
adaptable for use in a variety of applications, and as
easy to control as conventional digital bus peripherals.

Cl
390pF

R4

37.4K 1%
Rl
201< 1%

. C3
0.1nf'

• Note: Op-amp U1
must be rated for
single 5V operation.
R10 & R11 values
depend on Op-amp
used.

~
R2
201<1%

R3
4751%
Tl

MIDCOM
671-8005
+SV

R6
22.1K
C6
0.1 nf'

R7
2OKl%

CS
7S0pF

~
R9
20Kl%

02

VOlTAGE
REFERENCE

HOOK

>--_ _ _ _ _--l

RI~ ~--------------------------------~

FIGURE 2: Single 5V Hybrid Version
3-254

VRl
MOV
V2S0l20

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
Unlike digital logic circuitry, modem designs must
properly contend with precise frequency tolerances
and very low level analog signals, to ensure acceptable
performance. Using good analog circuit design practices will generally result in a sound design. Following
are additional recommendations which should be
taken into consideration when starting new designs.
CRYSTAL OSCILLATOR
The K-Series crystal oscillator requires a Parallel mode
(antiresonant) crystal which operates at 11.0592 MHz.
It is important that this frequency be maintained to
within ±0.01% accuracy.
In order for a Parallel mode crystal to operate correctly
and to specification, it must have a load capacitor
connected to the junction of each of the crystal and
internal inverter connections, terminated to ground.
The values of these capacitors depend primarily on the
crystal's characteristics, and to a lesser degree on the
internal inverter circuit. The values used affect the
accuracy and start up characteristics of the oscillator.
LAYOUT CONSIDERATIONS
Good analogldigital design rules must be used to control
system noise in order to obtain highest performance in
modem designs. The more digital circuitry present on
the PC board, the more this attention to noise control is
needed. The modem should be treated as a high impedance analog device. A 22 mF electrolytic capacitor in
parallel with a 0.22 mF ceramic capacitor between VDD
and GND is recommended. Liberal use of ground
planes and larger traces on power and ground are also
highly favored. High speed digital circuits tend to generate a significant amount of EMI (Electro-Magnetic Interference) which must be minimized in order to meet
regulatory agency limitations. To accomplish this, high
speed digital devices should be locally bypassed, and
the telephone line interface and K-Series device should
be located close to each other near the area of the board
where the phone line connection is accessed. To avoid
problems, power supply and ground traces should be
routed separately to the analog and digital functions on
the board, and digital signals should not be routed near
low level or high impedance analog traces. The analog
and digital grounds should only connect at one point
near the K-Series device ground pin to avoid ground
loops. The K-Series modem IC's should have both high
frequency and low frequency bypassing as close to the
package as possible. The ISET resistor and bypass
capacitor need to be as close to device as possible.

MODEM PERFORMANCE
CHARACTERISTICS
The curves presented here define modem IC performance under a variety of line conditions while inducing
disturbances that are typical of those encountered
during data transmission on public service telephone
lines. Test data was taken using an AEA Electronics'
"Autotest I" modem test set and line Simulator, operating under computer control. All tests were run fullduplex, using a Hayes 2400 Smartmodem™ as the
reference modem. A 511 pseudo-random-bit pattern
was used for each data point. Noise was C-message
weighted and all signal-to-noise (SIN) ratios reflect
total power measurements similar to the CCITT V.56
measurement specification. The individual tests are
defined as follows.
SER vs. SIN
This test measures the ability of the modem to operate
over noisy lines with a minimum of data-transfer errors.
Since some noise is generated in the best of dial-up
lines, the modem must operate with the lowest SIN
ratio possible. Better modem performance is indicated
by test curves that are closest to the BER axis. A
narrow spread between curves representing the four
line parameters indicates minimal variation in performance while operating over a range of aberrant operating conditions. Typically, a modem will exhibit better
BER-performance test curves receiving in the low
band than in the high band.
SER vs. Receive Level
This test measures the dynamic range of the modem.
Because signal levels vary widely over dial-up lines,
the widest possible dynamic range is desirable. The
minimum Bell specification calls for 36 dB of dynamic
range. SIN ratios are held constant at the indicated
values while the receive level is lowered from a very
high to very low signal levels. The width of the "bowl" of
these curves, taken at the BER point, is the measure of
dynamic range.

3-255

I

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem

SSI 73K324L BER vs SIN

SSI 73K324L BER vs SIN

PRELIMINARY

\\

II

\\

PRELIMINARY

HIGH BAND RECEIVE
-30

Cl

2

0::

X
0::

28

>

27

3

<..>

0

u.

W

Cl

c:

~

c:

32

31

Z

>

N/C

5

30
29

AD1

6

28

RESET

u.

w

<

Z

-J

~
-J

N/C

26

AD1

25

RESET

AD2

7

27

ISET

24

ISET

AD3

8

26

RXCLK

AD3

23

RXClK

AD4

9

25

RXD

AD4

22

RXD

ADS

10

24

TXD

ADS

21

TXD

AD6

11

23

CS

AD6

20

cs

AD7

12

22

EXCLK

19

EXClK

N/C

13

21

N/C

AD7
12

13

14

w

I~

I~

-J

<

15

16

17

18

~

I~

~
-J

0
0

>

f-

14

15

16

17

w

I~ I~

'0
0

-J

<..>

<

x

>

f-

~

0

:so

:l! ~

52 51

0

~

~ ~

0

0

~ :l!

19

20

~

I~

-J

f-

~

<..>

x

f-

32-Pin PLCC

28-Pln PLCC

Iii

18

~

gJ
0

'"
0

'"0
...J

0

~ :l! ~

50 49 48 47 46 45 44 43 42 41

40

ClK

GND

XTl1

RXA

39

NIC

38

INTB

37

NlC

ADO

RESET

RXA

38

TXA

AD1

ISET

VREF

NIC

35

NlC

NIC

34

NIC

GND

33

VDD

32

NIC

0

0 g g
~ 00(
00(
00(

.:!i
00(

:g ~ ~
00(

....

~

0

RXCLK

TXD

AD6

EXCLK

TXD

AD7

TXClK

EXCLK

ALE

INT

26

WR

TXA

0

AD

VDD

30

ROB

29

WRB

28

NIC

27

:l!

RESET
ISET

cs

NIC

8
00(

RXClK
RXD

AD5

XTAL2

2223 24 25

AD2
AD3
AD4

NIC

15 16 17 18 19 20 21

VREF

XTl2

:l! :l!

ALE

28-Pin DIP

52-Lead QFP

A1

RXD

TXCLK

RD

lNT
TXA

400-Mil
22-Pin DIP

CAUTION: Use handling procedures necessary
for a static sensitive component.

3-258

SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
CAUTION: Use handling procedures necessary
for a static sensitive component.

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

ADO

1.

~

N/C

2

47

ISET

46

N/C

N/C

N/C

N/C

45

RXCLK

NIC

44

N/C

AD1

43

RXD

N/C

42

N/C

AD2

41

N/C

AD3

40

TXD

AD4

10

39

N/C

ADS

11

38

os

AD6

12

37

EXCLK

N/C

13

36

N/C

AD7

14

35

N/C

NIC

15

34

NIC

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

I

N/C
N/C

64-Lead TQFP

ORDERING INFORMATION
PART DESCRIPTION

ORDER NO.

PKG.MARK

SSI 73K324L with Serial Bus Interface
22-Pin Plastic Dual-In-Line

73K324LS-IP

73K324LS-1 P

28-Pin Plastic Dual-In-Line

73K324L-IP

73K324L-IP

28-Pin Plastic Leaded Chip Carrier

73K324L-281H

73K324L-281H

32-Pin Plastic Leaded Chip Carrier

73K324L-321H

73K324L-321H

SSI 73K324L with Parallell Bus Interface

44-Pin Plastic Leaded Chip Carrier

73K324L-IH

73K324L-IH

52-Pin Quad Flat Pack Package

73K324L-IG

73K324L-IG

64-Lead Thin Quad Flat Pack Package

73K324L-IGT

73K324L-IGT

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is g ranted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914
Protected by the following patents: (4,777,453)
(4,789,995) (4,870,370) (4,847,868) (4,866,739)

3-259

0494 - rev
©1990 Silicon Systems, Inc ..

Notes:

3-260

Section

4

CONTROLLERS &
SPECIAL MODEM
PRODUCTS

I

4

I

j
j
j
j
j
j
j
j
j
j
j
j
j
j
j
j
I

j
j
j
j
j

I

j
I

j
j

j
j
4-0

j
j
j

SSI 73D2248A/2348A
MNP5, V.42bis Datacom
Modem Device Set

Rrf'i'em'·]I;1111~·lil
September 1994

DESCRIPTION

FEATURES
Combines modem and protocol controller

The SSI 7302248A12348A Chip Sets consists of two
CMOS integrated circuits which provide the data pump
and protocol functions required to implement a high
performance 2400 biVs modem with error control and
data compression. The 7302248A basic modem
function is provided by the SSI 73K224L modem chip
and is compatible with CCITT V.21, V.22, V.22bis and
Bell 103 and 212A protocols. The error control
functions are provided by modular software running in
the SSI730291 0 controller. Modules are available for
MNP4, and V.42. compression software modules can
be can be added to the controller; MNP5 and V.42bis
are available. Provisions for customization of the
command set are provided, forming the basis for an
international modem.

Supports 0 - 300, 1200 and 2400 bitls with both
sync and async modes
Modular software desig n allows custom ization
Modem protocols:
Bell 103, 212A
CCITT V.22, V.22bis
Error control/compression protocols
Available: MNP4, MNPS, CCITT V.42, V.42bis
Supports non-volatile memory to store user
configurations and phone numbers
CMOS design for low power consumption
TQFP packages available for PCMCIA
applications

The 7302348 differs from the 7302248A in that it uses
the 73K324L instead of the 73K224L forthe data pump.
The 73K324L replaces the Bell 103 300 baud FSK
mode of operation withthe CCITTV.231200baud FSK
mode. The software is also modified to support V.23.
The two products are otherwise identical.

MNP5, V.42bis Datacom
Modem Device Set

0994 - rev

4-1

CAUTION: Use handling procedures necessary
for a static sensitive component.

I

SSI 73D2248A/2348A
MNP5, V.42bis Datacom
Modem Device Set
FUNCTIONAL DESCRIPTION

TEST MODES

The SS173D2248A12348A chip set forms the basis for
an international modem design incorporating the most
advanced error control and compression algorithms.
The set consists of two chips, the S81 73K224L
(73K324L) modem and the 73D2910 controller.
Customization of the controller is one of the features of
this chip set; software modules allow the modem
vendor to provide a range of features from a standard
hardware platform.

The 7302248A12348A chip set has provisions for three
test modes: analog loopback, digital loopback and
remote digitalloopback. Analog loopback allows data
to be sent into the local modem, have it modulated and
then demodulated and returned to the local terminal.
Oigitalloopback requires the cooperation of the user at
the remote end and allows data to be sent to the remote
modem, demodulated, then remodulated and returned
to the local end. Remote digital loopback allows the
same capability, without the need for a remote operator;
signals are sent to the remote modem which perform
the switching task that a remote operator would have
done.

The 73K224L (73K324L) provides the QAM, PSK and
FSK modulator and demodulatorfunctions, call progress
and handshake tone monitors, test modes and a tone
generator capable of producing DTMF, answer and
CCITI guardtones. This single-chip modem supports
the V.22bis, V.22, V.21 and Bell 103/CCITI V.23/212A
operating protocols in both sync and async modes.
Low level functions of the controller provide for automatic
detection of OTE speed, auto-dial, auto-answer,
handshake with fa "back and call progress detection.

AT COMMAND INTERPRETER

The SSI 7302248A12348A includes an AT Command
Interpreter which is a superset of the Hayes 2400
SmartmodemTM command set. Common application
software will be able to control the modem though this
interpreter. Additional commands have been added to
provide for control of the MNP and CCITTV.42 modes.

The 7302910 controller handles both the low level
modem functions as we" as protocol negotiation and
protocol operation. Software modules can be chosen
to provide the desired protocols for product
customization and differentiation. In addition, the "AT'
command set source code will be available for those
desiring to provide unique or country dependent
features.

NON-VOLATILE MEMORY

A serial NVRAM provides 256 bytes of storage for
configuration information and telephone numbers.
Current hardware provides for a 2K bit memory of
which about 400 bytes are used for setup and telephone
number storage. The remaining 1600 bytes are
avaliable. Memory address space allocated to nonvolatile RAM is 8K, so an expansion factor of 4 is
available. Alternatively, the address space could be
decoded for more hardware functionality.

Basic capabilities of the modem are those found in the
73K224L (73K324L) single-chip modem and are listed
in the separate 73K224L (73K324L) data sheet.
AUTOMATIC HANDSHAKE

The 73D2248A12348A wi" automatically perform a
complete handshake with a called or calling modem
and enterthe data transfer mode. Afterthe link between
the two modems has been established, the modems
may remain in the normal data mode or negotiate a link
which has error control and data compression.
Commands are provided to inform the modem which
action is appropriate.

4-2

SSI 73D2248A/2348A
MNP5, V.42bis Datacom
Modem Device Set
PROTOCOLS
Mlcrocom Networking Protocol (MNP)
MNP4 is a protocol offering error control while MNP5
offers data compression. Data to be transmitted is
broken into blocks of varying sizes, depending on line
conditions, and sent to the remote modem along with
a 16-bit Cyclic Redundancy Check word. If the algorithm
used to derive the CRC word atthe transmitter does not
produce an identical word when exercised on the
received data, a line error is assumed, and the block is
repeated. Data compression is obtained by transmitting
a short set of characters for a longer redundant set. At
the receiver, the short string is replaced with the longer
string that it represented, and the data stream is
returned to its original state.

cCln V.42 AND V.42BIS

I

The CCITT has ratified a set of protocols which operate
in a mannersimilarto MNP. MNP4corresponds to V.42
while MNP5 corresponds with V.42bis. Greater
efficiency is offered, but the tradeoff is a larger memory
space requirement. MNP5 requires an 8K buffer, while
V.42bis requires 32K. Data files which show
compression ratios approaching 2:1 with MNP5 may
show ratios of nearly 4:1 with V.42bis.

ADDITIONAL INFORMATION
The Silicon Systems 7302248/2348 Design Manual
defines the AT commands. Please contact your local
Silicon Systems sales office or Silicon Systems
headquarters in Tustin for a copy of the SSi Protocol
Design Manual.

4-3

SSI 73D2248A/2348A
MNP5, V.42bis Datacom
Modem Device Set

AT COMMAND SUMMARY
Command

Description

Command

Description

enable features represented by result codes 0-7, 10-12

AT

command prefix - precedes command line

X4



carriage return character - terminates command line

YO

disable long space disconnect

A

go into answer mode; attempt to go to on-line state

Y1

enable long space disconnect

AI

re-execute previous command line;
not preceded by AT nor followed by 

ZO

reset modem

&CO

assume data carrier always present

80

select CCITI V.22 standard for 1200 biVs communication

&C1

track presence of data carrier

81

select 8e11212A standard for 1200 bitls communication

D

&00

ignore DTR signal

dial number that follows; attempt to go to on-line state, originate
mode

&D1

assume command state when an on-to-off
transition of DTR occurs

DS=n

dial stored number in location "n" (0-3)

&D2

EO

Disable character echo in command state

hang up and assume command state when an on-to-off
transition of DTR occurs

E1

Enable character echo in command state

&D3

reset when an on-to-off transition of DTR occurs

HO

go on hook (hang up)

&F

recall factory settings as active configuration

H1

go off hook; operate auxiliary relay

&GO

no guard tone

10

request product indentification code

&G1

550 Hz guard tone

11

perform checksum on firmware ROM; return checksum

&G2

1800 Hz guard tone

12

perform checksum on firmware ROM;
returns OK or ERROR result codes

&K

flow control method

&MO

asynchronous mode

LO or L 1 low speaker volume
L2

medium speaker volume

&M1

synchronous mode 1

&M2

synchronous mode 2

L3

high speaker volume

&M3

synchronous mode 3

MO

speaker off

&05

error control mode
automatic speed buffering (ASS)

M1

speaker on until carrier detected

&06

M2

speaker always on

&TO

terminate test in progress

M3

speaker on until carrier detected, except during dialing

&T1

initiate local analog loopback

00

go to on-line state

&T3

initiate local digitalloopback

01

go to on-line state and initiate equalizer retrain at 2400 biVs

&T4

grant request from remote modem for RDL

00

modem returns result codes

&T5

deny request from remote modem for RDL

01

modem does not return result codes

&T6

initiate remote digitalloopback

Sr

set pointer to register "r"

&T7

initiate remote digital loop back with self test

Sr=n

set register "r" to value "n"

&T8

initiate local analog loopback with self test

Sr?

display value stored in register "r"

&V

view active configuration, user profiles, and stored numbers
save storable parameters of active configuration

VO

display result codes in numeric form

&WO

V1

display result codes in verbose form (as words)

&XO

modem provides transmit clock signal

WO

negotiation progress result codes not returned

&X1

data terminal provides transmit clock signal

W1

negotiation progress result codes returned

XO

enable features represented by result codes 0-4

X1

enable features represented by result codes 0-5, 10-12

X2

enable features represented by result codes 0-6, 10-12

X3

enable features represented by result codes 0-5, 7,10-12

4-4

&X2

receive carrier provides transmit clock signal

&Zn=x

store phone number "x" in location "n" (0-3)

SSI 73D2248A/2348A
MNP5, V.42bis Datacom
Modem Device Set
Dial string arguments:
,= delay
; = return to command

@ = silent answer
s = dial stored number

! = flash
W = wait for tone

R=reverse mode

If the Nov RAM has not been initialized it may be necessary to power down/power up and type A T&F& W
to properly initialize modem state.

TABLE 1: Result Codes
Xn

VERBOSEITERSE RESULT CODES

XO

OKlO, CONNECT/1, RING/2, NO CARRIER/3, ERROR/4

X1

All functions of XO + CONNECT (RATE)/1 = 300, 5 = 1200, 10 = 2400

X2

All functions of X1 + NO DIAL TONE/6

X3

All functions of X1 + BUSY/7

X4

All functions of X3 + NO DIAL TONE/6, NO ANSWER/8

TABLE 2: S Registers Supported
Sn

FUNCTION

UNITS

SOl

Answer on ring

No. of rings on which to answer

000 2

S1

Ring counter

No. of rings accumulated

000

DEFAULT

S2

Escape code

ASCII CHR Decimal 0-127

043

S3

Carriage return

ASCII CHR Decimal 0-127

013

S4

Line feed

ASCII CHR Decimal 0-127

010

S5

Back space

ASCIICHR

008

S6

Wait for dial tone

Seconds

002

S7

Wait for carrier

Seconds

030

S8

Pause time

Seconds

002

S9

Carrier valid

100 milliseconds (0.1 sec)

006

S10

Carrier drop out

100 milliseconds (0.1 sec)

014

S11

DTMF tone duration

1 millisecond (0.001 sec)

070

S12

Escape guard time

20 milliseconds (0.05 sec)

050

S13
*S141

N/A

Unused
Decimal 0-255

Bit mapped register

Stored in NVRAM with &W command.
Modem will not answer until value is changed to 1 or greater.

4-5

170

I

SS173D2248A/2348A
MNP5, V.42bis Datacom
Modem Device Set
TABLE 2: S Registers Supported
NUMBER

(Continued)

FUNCTION

UNITS

DEFAULT

815

Unused

816

Test register

Decimal #

000

817

8pecial test register

Decimal 0-255

096

818

Test timer

Decimal 0-255

000

819

Unused

N/A

820

Unused

N/A

N/A

*8211

Bitmapped register

Decimal 0-255

*8221

Bitmapped register

Decimal 0-255

118

*8231

Bitmapped register

Decimal 0-255

007

000

824

Unused

825 1
8261

DTR delay

10 milliseconds (0.01 sec)

005

N/A

CT8 delay

10 milliseconds (0.01 sec)

001

*8271

Bitmapped register

Decimal 0-255

064

Decimal 0-9

000

836

Negotiation failure treatment

837

Desired modem line speed

838

Hang-up timeout

20

839

Current flow control setting

3

843

Current DCE speed

0

846

Protocol/Compression selection

2

848

Feature negotiation action

7

849

A8B Buffer low limit

1-249

8

850

A8B Buffer high limit

2-250

16

882

Break select register

895

Extended result code bit map

5

128
0

*The bitmapped register functions are equivalent to normal "AT" command modem registers.
1 8tored in NVRAM with &W command

4-6

SSI 73D2248A/2348A
MNP5, V.42bis Datacom
Modem Device Set
PACKAGE PIN DESIGNATIONS
(Top View)

NlC
NlC
NlC
NlC
NlC

N/C

N/C
USR50

NlC
USR51

A1

USR31

A2

USR30

A3

USR40

A4

USR41

A5

USR42

A6

USR43

A7

USR44

AS

USR45
USR46

A9
A10

USR47

A11

VND

A12

VPD

A13

USR20

A14

USR21

A15
PSEN

USR22

RESET

USR24

USR23

VND

USR25

OSCOUT

USR26

OSCIN

USR27

ClK20UT

N/C
N/C
N/C

NlC
NlC

N/C

NlC
NlC

NlC

ClI-ClCl

a..:Jxx

>Ol-CI:

;;;:

...J

()

5517302910
Controller
100-Lead QFP

CAUTION: Use handling procedures necessary
for a static sensitive component.

4-7

I

SSI 73D2248A/2348A
MNP5, V.42bis Datacom
Modem Device Set
PACKAGE PIN DESIGNATIONS (continued)
(Top View)

N!C
NIC

75

NlC

74

NlC

NlC

73

A1

72

USR51
USR31

A2

71

USR30

A3

70

USR40

A4

69

USR41

A5

68

USR42

A6

67

USR43

A7

USR44

AS

USR45

A9
A10

13

USR46
USR47

A11

14

VND

A12

15

VPD

A13

16

USR20

A14

17

USR21

A15
PSEN

18

USR22

19

USR23

RESET

20

USR24

VND

21

USR25

OSCOUT

22

USR26

OSCIN

23

USR27

NIC

24

NlC
NlC

NlC

5517302910

Controller
100-Lead TQFP

CAUTION: Use handling procedures necessary
for a static sensitive comp~nent.

4-8

SSI 73D2248A/2348A
MNP5, V.42bis Datacom
Modem Device Set

~

:::i

~ ~ ~ ~ ~ ~

:.::

..J

u

~

0
Z

(!)

~ ~

«
x

a:

tii

u.
UI

~ a:
> ~

64 63 62 61 60 59 58 57 56 55 54 53 52 51

en

UI

a:

50 49
NlC

ADO

N/C

ISET

N/C

NlC

N/C

RXClK

N/C

NlC
RXD

AD1

N/C

42

AD2

41

NlC
NlC
TXD

AD3
39

AD4

NlC

cs

AD5

EXClK

AD6
36

NlC

I

NlC
NlC

AD7

N/C

34

NlC

NlC

33

NlC

17 18 19 20 21

22 23 24 25 26 27 28 29 30 31

~ ~ «~ ~ I~ z

Q

10

a:

U

Z

~

Q

Q

z z

~ I~

~

U

X
fo-

Q

z

32

~

SSI73K224L
Single Chip Modem
64-Lead TQFP

:.::

foUI

~

..J

~

52 51

U
X

0

X

a: a:

:.::

:.::

U

U
~ xfo-

..J

~ ~

0
x
f0-

~ ~ I~

x
Ul

50 49 48 47 46 45 44 43 42 41

..J

40

NlC

39

NlC

38

INT

37

NIC

36

TXA

NlC

35

NlC

IIVC

34

IIVC

GND

33

VDD

IIVC

32

NlC

ClK

31

NlC

NlC

30

RD

XTL1

29

WR

XTL2

28

NlC

IIVC

27

ALE

15 16 17 18 19 20 21
0

Q

N

C'l

0
0
0
« ~ ~ « « «

v
0

<:

22 23 24 25 26
(Q

SSI73K224L
Single Chip Modem
52-Lead QFP

CAUTION: Use handling procedures necessary
for a static sensitive component.

4-9

,....

0
0
0
« « ~ « ~ ~
It'l

SSI 73D2248A/2348A
MNP5, V.42bis Datacom
Modem Device Set
PACKAGE PIN DESIGNATIONS (continued)
(Top View)

§
4

~

~

::i
~

l<:

..J

U

3

NlC

u.

0
Z
C!:l



18

~

I-

ClK

GND

XTL1

RXA

XTL2

VREF

ADO
AD1

ISET

AD2

RXCLK

AD3

RXD

AD4

TXD

cs

EXCLK

AD6

EXClK

NlC

AD7

TXCLK

ALE

INT

19

20

I~

l<:

WI

TXA

U

FD

VDD

x

I-

SSI73K224L
Single Chip Modem
32-Pin PLCC

SSI73K224L
Single Chip Modem
28-Pln DIP

AD1

~

g

5

""d

Cl

z

~

1

28

27

(!J

LL

w

~

28

0

AD2 [ 6

AD5

..J

8c(

RESET

AD3

7

23

RXCLK

8

22

RXD

ADS [ 9

21

TXD

AD6

20pCS

10

AD7 [ 11

19
13

14

15

16

~ I~

I~

Cl
Cl

~ I~

12

>

17

18

d~

SSI73K224L
Single Chip Modem
28-Pin PLCC

AdV~lnce Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Copyright Notice:
The software contained within certain components of the SSI 73D2248A12348A is copyright protected and may only be used in conjunction
with the SSI 73D2248A12348A product as supplied by Silicon Systems. No license to reproduce this software is granted or implied. This
material may not be reproduced in any form without the express written permission of Silicon Sy~tems, Inc. © Copyright 1992. All rights·
reserved.
Silicon Systems, Inc., 14351 Myford R08:d, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914

0994 - rev

4-10

RESET
ISET

AD4

CAUTION: Use handling procedures necessary
for a static sensitive component.

©1992 Silicon Systems, Inc.
Protected by the following patents: (4,777,453) (4,847,868)
(4,789,995) (4,870,370) (4,866,739)

25
24

PEXCLK

SSI73M2910/2910A
Microcontroller

November 1994

FEATURES

DESCRIPTION
The Silicon Systems 73M2910 high performance
microcontroller is based on the industry standard 8-bit
8052 implemented in Silicon Systems' advanced
submicron CMOS process. The processor has the
same attributes of the 8052 including Instruction cycle
time, UART, timers, interrupts, 256 bytes of on-chip
RAM and programmable lID. The architecture has
been optimized for low power portable modem or
communication applications by integrating unique
features with the core CPU.

8052 Compatible Instruction set
34 MHz Operation @ 4.5 - 5.5V
44 MHz Operation @ 4.75 - 5.5V (2910A)
22 MHz Operation @ 3.3 - 5.5V
HOLC Support logic (Packetizer, 16 and 32
CRC, zero 10)
24 pins for user programmable I/O ports
8 pins programmable Chip select log Ic or I/O for
memory mapped peripheral eliminating glue
logic

The main feature is a user friendly HDLC packetizer,
accessed through the special function registers. It has
a serial 110, hardware support for 16- and 32-bit CRC,
zero insert/delete control, a dedicated interrupt and a
clear channel mode for by-passing the packetizer.

3 external interrupt sources (programmable
polarity)
16 dedicated latched address pins

Other features include additional user programmable
lID with programmable bank select and chip select
logic, designed to eliminate board level glue logic. It
also includes two general purpose input ports with
programmable wakeup capability.

Multiplexed data/address bus
Instruction cycle time identical to 8052
Buffered oscillator (or OSC/2) output pin
1.8432 MHz UART clock available
Bank select circuitry to support up to 128K of
external program memory

For devices that require non-multiplexed address and
data buses, eight latched outputs forthe low byte of the
address are available.

100-Lead TQFP package available for PCMCIA
applications

(continued)

Also available in 100-Lead QFP package

BLOCK DIAGRAM

1194 - rev.

4-11

I

SSI 73M291 0/291 OA

Microcontroller

DESCRIPTION

DEVELOPER'S NOTE:

(continued)

The 73M2910 is also available in a 100-pin PGA
package for system developers. The PGA package
is more convenient and reliable for development
emulation systems than the other package styles.
Emulation systems for the 73M2910 are available
through Signum Systems, 171 E. Thousand Oaks
Blvd., #202, Thousand Oaks, CA 91360
(805) 371-4608.

The 73M2910 has two extra interrupt sources, an
external interrupt and a HDLC interrupt. The HDLC
interrupt has two registers associated with it; the HDLC
Interrupt Register which is used to determine the
source of the interrupt, and the HDLC Interr~pt Enable
Register that enables the source of the interrupt.
The state of the external interrupts can be read through
a register allowing the interrupt pins to be used as
inputs. The interrupt pins INTO and INT1 can be either
negative edge, positive edge or level triggered. The
INT2 pin is always edge triggered.

8052 REFERENCE

This Document will describe the features unique to the
73M2910. Please refer to an 8052 Programmer's
Guide, Architectural Overview and Hardware
Description for details on the instruction set, timers,
UART, interrupt control, and memory structure.

Two buffered clock outputs have been added to
support peripheral functions such as UARTs, modems
and other clocked devices. The main internal
processor clock frequency can be divided by 2 for
power conservation in functional modes that only
require half the clock speed.
Additional internal special function registers are used
for firmware control over the HDLC Packetizer, the
clocks and the programmable I/O ports.
To accommodate processor peripherals when
operating at 22 MHz the processor's timing has been
altered somewhat to allow more address setup time for
slower peripheral program ROM and memory mapped
peripherals. This can offer the system designers an
advantage when using higher (22 MHz) oscillator
frequencies.
For low power applications the 73M2910 operates
from 3 to 5 volts at 22 MHz and supports two power
conservation modes: Idle and Power-down. In the
Power-down state the total current consumption is less
than 10 J.LA at room temperature.
This device is offered in small form factor 100-lead
TQFP packages for PCMCIA applications and
100-lead QFP packages.

4-12

SSI 73M291 0/291 OA

Microcontroller

REGISTER DESCRIPTION
INTERRUPTS
The core chip provides 8 sources of interrupt; 3 external interrupts, 3 timer interrupts, a serial port interrupt, and
an HOLC interrupt. An external interrupt and an HDLC interrupt are unique to the 73M291 O. They do not exist
in a normal 8052 product. Previously unused bits in the IE and IP registers are now serving functions for these
additional interrupt sources. The interrupt vector addresses are as follows:
SOURCE

VECTOR ADDRESS

INTO (lEO)

003H

TFO

OOBH

INT1 (IE1)

013H

TF1

01BH

RI + TI

023H

TF2 + EXF2

02BH

INT2 - ADDED INTERRUPT

033H

HDLC-ADDEDINTERRUPT

03BH

The external interrupt sources, INT(2:0), come from dedicated input pins. The apparent polarity of these pins
is individually controlled by bits in a special interrupt direction register, I DIR (address A9). The interrupt pins INT1
and INTO can be either edge or level generated interrupts as indicated by bits 1 and 3 in the TCON register
(address 88). Pin INT2 is always an edge generated interrupt. A flag is set when a falling transition (riSing if IDIR
bit 2 is set) on this pin is detected. This flag is automatically cleared when the interrupt is processed.
INTERRUPT ENABLE REGISTER (IE) SFR ADDRESS A8
Bit Addressable
Reset State OOh
BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT 1

BITO

EA

EX2

ET2

ES

ET1

EX1

ETO

EXO

Note: BIT 6 differs from the 8052. This is a reserved bit in the 8052 and is used as a mask bit for external interrupt
2 in the core implementation. When BIT 6 is set to a 0, external interrupt 2 is disabled.
The mask bit for the HDLC interrupt source is BIT 0 of the HDLC control register.
INTERRUPT PRIORITY REGISTER (IP) SFR ADDRESS B8
Bit Addressable
Reset State OOh
BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT 1

BITO

PHDLC

PX2

PT2

PS

PT1

PX1

PTO

PXO

Note: BIT 6 and BIT 7 differ from the 8052. These are reserved bits in the 8052 and are used to determine the
priority of external interrupt 2 and the HDLC in the core implementation. When BIT 6 is set to a 1, the interrupt
is set to the higher priority level.

4-13

I

SSI 73M291 0/291 OA
Microcontroller

REGISTER DESCRIPTION (continued)
EXTERNAL INTERRUPT DIRECTION REGISTER (lDIR) SFR ADDRESS 92
Byte Addressable
Reset State OOh
BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT 1

BITO

0

0

INT2

INT1

INTO

INTD2

INTD1

INTDO

These bits determine the polarity of the corresponding external signals INT(2:0) which will result in an interrupt
and will also allow the user to directly read the logic level at the pads INT(2:0).
BITS(5:3) INT(2 :0)
BITS(5:3) are read only bits that reflect the logic value at the corresponding pin. The value is not affected by
BITS(2:0).
BITS(2:0) Interrupt Polarity Control

If the bit is set to a 0, a falling edge will trigger the interrupt. If the bit is set to a 1 , a rising edge will trigger the
interrupt. Also, if the bit is set to a 1, level generated interrupts will occur when the corresponding pin is high and
the internal pin signal to the timer controls will be inverted.
Bits 6 and 7 will always be read as O's.
CLOCK CONTROL REGISTER SFR ADDRESS DA
Byte Addressable
Reset State OOh
BIT7
Activity

BIT6
CLK1
CTRL1

BIT5
MCLK
CTRL

BIT4
CLK2EN

BIT3

BIT2

BIT 1

BITO

CLK2
CTRL1

CLK2
CTRLO

CLK1EN

CLK1
CTRLO

These bits determine the behavior at the CLK1 OUT and CLK20UT pins and allow the user to divide the main
internal processor clock frequency by two for power conservation.
BIT7
BIT 7 is an activity bit. It is cleared by a read of this register. If the activity bit is set it will prevent the 73M291 0
from entering Sleep mode.
BIT6
When BIT 6
BIT5

= 1, CLK10UT will be OSC/1.5 if bit 1 is a 1 and bit 0 is O.
CLOCK OUT

0

OSC

1

OSC/2

BIT 5 Master Clock Control
When BIT 5 is set to a 1 the internal processor clock is the oscillator frequency divided by 2. If this bit is a 0, the
processor clock is the same frequency as the oscillator's.

4-14

551 73M291 0/291 OA
Microcontroller

BIT 4 Clock 2 Output Enable
BIT 4 enables the clock at the CLOCK 2 output pin if it is set to a 1. The CLOCK 2 pin output is held to a 0, by
writing this bit to a O. This will reduce system power if the clock pin is not used or if a power reduction mode is
required.
BIT 3 BIT 2 Clock 2 Output Control

These bits determine the oscillator divisor for the CLOCK 2 output pin. They were designed to provide a 1.8432
MHz clock for an external UART given an oscillator frequency of 11.0592 MHz, 22.1184 MHz, 18.432 MHz, or
13.824 MHz.
BIT3

BIT2

CLK20UT

0

0

OSC/7.5

OSC FREQUENCY

13.824 MHz

0

1

11.059 MHz

1

0

OSC/6
OSC/12

22.118 MHz

1

1

OSC/10

18.432 MHz

BIT 1 CLOCK 1 Output Enable

BIT 1 enables the clock at the clock 1 output pin if it is set to a 1. The clock pin output is held to a 0, by writing
a 0 to this bit. This will reduce system power if the clock pin is not used or if a power reduction mode is required.
BIT 6 is cleared to a 0 upon a reset.
BIT 0 Clock 1 Output Control

BIT 0 controls the frequency of the clock 1 output pin. The clock output is either the oscillator's output signal
divided by two or a buffered oscillator output signal
POWER SAVING MODES
Low Power Modes

The SSI 73M291 0 supports two power conservation modes, which are controlled by the PCON.1 and PCON.O
control bits of the PCON register.
If PCON.O is set, the SSI 73M291 0 will go into a power saving mode where the oscillator is running, clocks are
supplied to the UART, timers, HDLC, and interrupt blocks, but no clocks are supplied to the CPU. Instruction
processing and activity on the address and data ports is halted. Normal operation is resumed when an unmasked
interrupt is requested or when a reset occurs.
If PCON.1 is set, the SSI 73M291 0 goes into its lowest power mode where the oscillator is halted. The total current
consumption in this state should be less than 10 IJ-a. The SSI 73M2910 will start its oscillator and begin to return
to normal operation when either a reset occurs, when a falling (rising if corresponding direction bit is set) edge of
an unmasked external interrupt from pins INT(2:0) is detected, or when the USR5(1 :0) pins change to a state
according to the USR 5 port register. Edges used in wakeup modes are not filtered in the SSI 73M291 0, so the
user must be cautious of noise or small glitches inadvertently waking up the chip. From the time the edge that
results in the wake up occurs, to the point at which an instruction is executed, depends on the oscillator start-up
time. Three good oscillator pulses must be detected before the main internal clocks are generated.
During Power Down mode, both the ALE and PSEN pins are pulled high since these signals often provide the
output enable and chip enable forthe ROM (active low). This ensures that the external components are in their
lowest power state.

4-15

I

SSI 73M291 0/291 OA
Microcontroller

REGISTER DESCRIPTION (continued)
USER PROGRAMMABLE I/O
Port Control USR1, USR2, USR3, USR4, USR5
The core chip provides 32 user I/O pins. Each pin is programmed separately as either an input or as an output
by a bit in a direction register. If the bit in the direction register is set to a 1, the I/O control will treat the
corresponding pin as an input. If it is a 0, the pin will be treated as an output whose value is determined by the
port data register. The USR1 and USR2 port registers are accessed through the internal SFR bus. The USR3
and USR4 ports are accessed through the external memory bus by a MOVX instruction. The USR4 port provides
the user with an automatic chip select function if selected by the user. If the user does not require some (or any)
of the chip select pin options, he may program the USR4 port pins to operate in the same way as USR3 port pins.
The USR DATA register contents determine pin values if chosen as an output. When reading from the DATA
register's SFR address, the pin logic values are returned as data except when the port address is the destination
address for a read-modify-write instruction. In this case, the latched register values are returned
as data. When reading data from a DATA register that is mapped in the external memory space, the pin values
are always retu rned as data.
The USR5 register allows for 2 additional input pins. In normal operation these pins can be used as general
purpose inputs. In Power Down mode, the user can program either rising or falling transitions or logical
combinations of these pins to wake up the chip.
USER 1 PORT
USR1 DATA SFR Address 90
Bit Addressable
Reset State OOh
BIT7

BITS

BIT5

BIT4

BIT3

BIT2

BIT 1

BITO

USR17

USR16

USR15

USR14

USR13

USR12

USR1 1

USR10

Bits in this register will be asserted on the USR1 (7:0) pins if the corresponding direction register bit is a O.
Reading this SFR's address will return data reflecting the values of pins USR1 (7:0) except when address 90h
is the destination address for a read-modify-write instruction. In this case, the latched register values are
returned as data.
USR1 port signals are also used as timer controls. In applications where the external signals are required for
timer count modes, the corresponding port pin should be configured as an input.
USR1
USR1
USR1
USR1

BITO
BIT1
BIT2
BIT3

TIMER
TIMER
TIMER
TIMER

0 TO PIN
1 T1 PIN
2 T2EX PIN
2 T2 PIN

USR1 Port Direction (DIR1) SFR Address 91
Byte Addressable
Reset State FFh
BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT 1

BITO

DIR17

DIR16

DIR15

DIR14

DIR13

DIR12

DIR1 1

DIR10

This register is used to designate the USR1 pins as either inputs or outputs. If the register bit is reset to a 0, the
corresponding USR1 pin is programmed as an output that will be driven by the corresponding USR1 DATA
register bit. If the register bit is a 1, the corresponding pin will be treated as an input.
4-16

SSI 73M291 0/291 OA
Microcontroller

After a reset, the USR1 pins will present a high impedance output state and the input values will not be driven
from the pin, but will be driven to a 1 internally. The pins will assume normal 1/0 operation once the processor
has written the port direction register. This feature will ensure a low current state at reset
(you don't want to drive out against external inputs, and you don't want floating inputs).

USER2 PORT
USR2 Port Data SFR Address D8
Bit Addressable
Reset State OOh
BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT 1

BITO

USR27

USR26

USR25

USR24

USR23

USR22

USR21

USR20

Bits in this register will be asserted on the USR2(7:0) pins if the corresponding direction register bit is a O.
Reading this SFR's address will return data reflecting the values of pins USR2(7:0) except when address D8h
is the destination address for a read-modify-write instruction. In this case, the latched register values are
returned as data.

•

USR2 Port Direction (DIR2) SFR Address D9
Byte Addressable
Reset State FFh
BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT 1

BITO

DIR27

DIR26

DIR25

DIR24

DIR23

DIR22

DIR21

DIR20

This register is used to designate the USR2 pins as either inputs or outputs. If the register bit is reset to a 0, the
corresponding USR2 pin is programmed as an output that will be driven by the corresponding USR2 1/0 OAT A
register bit. If the register bit is a 1 , the corresponding pin will treated as an input.
After a reset, the USR2 pins will present a high impedance output state and the input values will not be driven
from the pin, but will be driven to a 1 internally. The pins will assume normal 1/0 operation once the processor
has written the port direction register. This feature will ensure a low current state at reset (you don't want to drive
out against external inputs, and you don't want floating inputs).

USR3 Port Data External address 0000
Byte Addressable
Reset State OOh
BIT7

BIT6

BIT 5

BIT4

BIT 3

BIT2

BIT 1

BITO

USR37

USR36

USR35

USR34

USR33

USR32

USR31

USR30

Bits in this register will be asserted on the USR3(7:0) pins if the corresponding direction register bit is a
Reading this SFR's address will return data reflecting the values of pins USR3(7:0).
If the bank select feature is chosen, USR3 PIN7 acts as address bit 17 and USR3 data bit 7 is ignored.

4-17

o.

SSI 73M291 0/291 OA
Microcontroller

REGISTER DESCRIPTION (continued)
USR3 I/O Port Direction (DIR3) External Address 0001
Byte Addressable
Reset State FFh
BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT 1

DIR37

DIR36

DIR35

DIR34

DIR33

DIR32

DIR31

BIT 0
DIR3

°

This register is used to designate the USR3 pins as either inputs or outputs. If the register bit is reset to a 0, the
corresponding USR3 pin is programmed as an output that will be driven by the corresponding USR3 DATA
register bit. If the register bit is a 1, the corresponding pin will be treated as an input.
After a reset, the USR3 pins will present a high impedance output state and the input values will not be driven
from the pin, but will be driven to a 1 internally. The pins will assume normal 1/0 operation once the processor
has written the USR3 port direction register. This feature will ensure a low current state at reset (you don't want
to drive out against external inputs, and you don't want floating inputs).
If the bank select feature is chosen, USR3 PIN7 is forced to be an output.

Bank Select (BNKSEL) External Address 0002
Byte Addressable
Reset State OOh
BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT 1

BITO

B7

B6

B5

B4

B3

BSEN

BS1

BSO

This resister is used to accommodate systems where more than 64 Kbytes (up to 128 Kbytes) of program
memory are required. USR3 PIN 7 acts as an address pin, A16, if BSEN is set to a 1 and if the processor is
fetching an instruction and not data memory. If BSEN is set to a 1, A 15 is also modified during instruction fetches
as shown. If BSEN is a 0, no alterations to address bit A15 are made, and USR3 PIN 7 is a function of USER3
bit 7 and DIR3 bit 7.
Bits (7-3) are general purpose read/write register bits.
A 15 is the value of the 16th address bit as it appears at pin A 15.
A 15' is the address from port 2 internal logic, the value that will appear as the most significant address bit if
no bank select feature is chosen.
A 16 is the value of the 17th and MSB of the instruction address seen at the USR3 7 port pin, if the bank select
feature is selected. If the bank select feature is not selected, USR3 7 acts as a normal USR3 I/O port pin.

4-18

SSI 73M291 0/291 OA

Microcontroller

*

BSEN

BS1

BSO

A15'

A15

A16

ADDRESS

0
0

*

*

*

*

0
1

0
1

USR37
USR37

OK - 32K
32K - 64K

1
1

0

0

0

0

0
1

0
1

0
0

32K - 64K

1

0
0

1

0
1

0
0

0

OK - 32K

1

1

64K - 96K

1
1

1
1

0
0

0

0

0

1

1

1

OK - 32K
96K - 128K

1

1

1

0

1

1

1

0
0

0

1

1

1

OK - 32K

OK - 32K
64K - 96K

= Don't care.

Example: Bank 2 is selected
BSEN = 1, BS1 = 0, BSO = 1

BANK 3

BANK 2
Bank 2 is selected
If A15' is a 1, fetches will come from Bank 2
Bank 2 will overlay Bank 1

BANK 1

BANKO

0- 32K

That is all fetches that would normally occur
from Bank 1 will come from Bank 2

FIGURE 8: Bank Select

4-19

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Microcontroller

REGISTER DESCRIPTION (continued)
USER4 PORT
USR4 Port Data External Address 0003
Byte Addressable
Reset State OOh
BIT7

BIT6

BIT 5

BIT4

BIT3

BIT2

BIT 1

BITO

USR47

USR46

USR45

USR44

USR43

USR42

USR41

USR40

Bits in this register will be asserted on the USR4(7:0) pins if the corresponding direction register bit is a 0 and
if the corresponding bit in the chip select enable register, 0005, is set to a O. Reading this register will return data
reflecting the values of pins USR4(7:0).
USR4 1/0 Port Direction (DIR4) External Address 0004
Byte Addressable
Reset State FFh
BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT 1

BITO

DIR47

DIR46

DIR45

DIR44

DIR43

DIA42

DIR4

1 DIR40

This register is used to designate the USR4 pins as either inputs or outputs. If the register bit is reset to a 0, the
corresponding USR4 pin is programmed as an output that will be driven by the corresponding USR4 1/0 DATA
register bit if the corresponding bit in the chip select enable register, 0005, is set to a O. If the register bit is a 1,
the corresponding pin will treated as an input only if the corresponding bit in register 0005 is set to a O.
After a reset, the USR4 pins will act as chip select outputs.
USR4 Port Chip Select Enable (CSEN) External Address 0005
Byte Addressable
Reset State FFh
BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT 1

BITO

CSEN 7

CSEN6

CSEN5

CSEN4

CSEN3

CSEN2

CSEN 1

CSEN 0

This register is used to designate the USR4 pins as either user programmable II0s or as chip select (CSOB CS7B) functions on a pin by pin basis. This feature is designed to help reduce external glue logic for peripheral
memory mapped devices. The chip select function is programmed by setting the appropriate bits in the CSEN
register. When a chip select pin is enabled by setting the corresponding CSEN bit to a 1, all data and direction
information from registers 0003 and 0004 for this bit are ignored and the selected port becomes an output. If
the bit is reset to a 0, the pin will be treated as a normal programmable user 1/0 pin as defined by registers 0003
and 0004.
The chip select pins have a defined memory map. The intent is that the outputs can be wire ORed together for
a flexible selection of peripheral chip selects. All chip selects will be disabled (forced to a logic 1. It is assumed
that all chip selects are active low) after the read or write is completed, and the appropriate chip select will be
enabled as the next new external addresses is asserted. After a reset, the CSB pull-up devices are all enabled,
that is, all chip select outputs are high. Users must account for this if these pins are intended to be general
purpose I/0s.

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Microcontroller

The chip selects partition a 64K memory space as follows:

CHIP SELECT PIN

ADDRESS

# BYTES

RESERVED FOR INTERNAL USE

OOOOH - OOFFH

256

CSO (USR4.0)

0100H - 01 FFH

256

CS1

(USR4.1)

0200H - 03FFH

512

CS2 (USR 4.2)

0400H - 07FFH

1K

CS3 (USR4.3)

0800H - OFFFH

2K

CS4 (USR 4.4)

1OOOH - 1 FFFH

4K

CS5 (USR 4.5)

2000H - 3FFFH

8K

CS6 (USR 4.6)

4000H - 7FFFH

16K

CS7 (USR 4.7)

8000H - FFFFH

32K

Note: You can't read from external addresses OOOOH-OOFFH. These are reseNed for SSI 73M291 0 internally
defined registers

I

USER5PORT
USR5 Port Register External Address 0006
Byte Addressable
Reset State 60h
BIT 7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT 1

BITO

USR5EN

USR50

USR51

POL50

POL51

ACTEO

ACTE1

AND01

This register allows user programmable wakeup capability. If this is not required, this register can be used to
read external signals at the USR51 and USR50 pins.

Bit 7 USR5 Input Port Enable
Bit 7 is used to enable the USR51 and USR50 input circuitry. If this bit is a 0, the USR5 pad circuitry is driven
to a known level internally and any signal level at the chip pin is ignored. When set to a 1 the pad circuitry is
enabled and the values of these pins are reflected in BITS 6 and 7. If these pins are not connected at the board
level, this bit should remain at a 0 to keep the pad circuitry from drawing unnecessary current.
The USR5 register can be programmed such that a transition (bit 4 determines rising or falling) of USR50, a
transition (bit 3 determines rising or falling) of USR51, orthe logical combination of USR50(B) (bit 4 determines
high or low level) AND USR51 (B) (bit 3 determines high or low level) can wakeup the processor from its Power
Down mode.

BIT6 USR50
BIT 6 reflects the value of chip pin USR50 if the USR5EN bit is set to a 1.

BIT5USR50
BIT 5 reflects the value of chip pin USR51 if the USR5EN bit is set to a 1.

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551 73M291 0/291 OA
Microcontroller

REGISTER DESCRIPTION (continued)
BIT 4 USR50 Polarity
BIT 4 determines which edge or level is used in the wakeup detection circuit. A low level selects a rising transition
and the true pin value of USR50tothe wakeup combinatorial circuit. When this bit is set to a 1, a falling transition
and complemented USR50 value is presented to the wakeup combinatorial circuit.

BIT 3 USR51 Polarity
BIT 3 determines which edge or level is used in the wakeup detection circuit. A low level selects a rising transition
and the true pin value of USR51 to the wakeup combinatorial circuit. When this bit is set to a 1 , a falling transition
and complemented USR51 value is presented to the wakeup combinatorial circuit.

BIT 2 USR50 Edge Activity Enabled
When BIT 2 is set to a 1, a transition of USR50 of the appropriate level as dictated by BIT 4, will wake up the
processor. If this bit is reset to a 0, edge activity on this pin is ignored.

BIT 1 USR51 Edge Activity Enabled
When BIT 1 is set to a 1, a transition of USR50 of the appropriate level as dictated by BIT 3, will wake up the
.
processor. If this bit is reset to a 0, edge activity on this pin is ignored.

BIT 0 Combinatorial and of USR50 and USR51 Level Enabled
When BIT 0 is set to a 1, the value USR50 or its complimented value as dictated by BIT3, ANDed with the value
USR51 or its complimented value as dictated by BIT 2, will wake up the processor. If this bit is reset to a 0, the
levels of USR50 and USR5i are ignored.

USR51

BIT4

BIT3

BIT2

BIT 1

BITO

*

*

*

*

0

0

0

NO

0-1

*

0

*

1

*

*

YES

1-0

*

1

*

1

*

*

YES

*

0-1

*

0

*

1

*

YES

*

1-0

*

1

*

1

*

YES

0

0

1

1

*

*

1

YES

1

*

*

1

YES

1

YES

1

YES

1

*

WAKEUP

USR50

0

0

0

1

1

0

*

*

1

1

0

0

*

*

= Don't care.

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551 73M291 0/291 OA
Microcontroller

HOLC CONTROL REGISTER 0
HOLC Control Register 0 (HOLCO) SFR Address CO
Bit Addressable Reset State OOXX 0000 b
Bits 5 and 4 are read only bits
BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT 1

BITO

WRXD

WPTXD

TXD
R

PRXD
R

RXD
CTRL1

RXD
CTRLO

PTX
CTRL1

PTX
CTRLO

This register controls the basic set-up of the DTE and modem pins RXD, TXD, PRXD, and PTXD.

61T7WRXO
BIT 7 allows the processor to write directly to the SSI 73M291 0 RXD output pin. The value of BIT 7 will appear
at the PTXD pin only if BIT 1 is a 1 and BIT 0 is a O.

BIT6WPTXO
BIT 6 allows the processor to write directly to the SSI 73M291 0 PTXD output pin. The value of BIT 6 will appear
at the PTXD pin only if BIT 1 is a 1 and BIT 0 is a O.

BITSTXO
BIT 5 is a read only bit that reflects the value at the SSI 73M2910 TXD input pin.

BIT4PRXO
BIT 4 is a read only bit that reflects the value at the SSI 73M2910 PRXD input pin.

BIT 3 BIT 2 RXO Control
BIT 3 and BIT2 control the source of the SSI 73M291 0 RXD output pin. This output goes to the DTE's RS232
interface. The source of this signal can be the core's UART TXD output, the PRXD output from a modem
peripheral (clear channel), the DTE's TXD(echo), or the value written into bit 7 of this register.

BIT3

BIT2

0

0

RXO OUTPUT
UART TXD OUTPUT

0

1

PRXD BUFFERED (CLEAR CHANNEL)

1

0

TXD BUFFERED (ECHO)

1

1

WRXD (BIT 7)

BIT 1· BIT 0 PTXO Control
BIT 1 and BITO control the source of the SSI73M2910 PTXD output pin. This output goes to the modem's TX
data input. The source of this signal can be the core's HDLC TX output, the DTE's TXD output (clear channel),
or the value written into bit 6 of this register.

BIT1

BITO

0

0

PTXD Output
HDLC TX Output

0

1

TXD Buffered (Clear Channel)

1

0

WPTXD (BIT 6)

1

1

0
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SSI 73M291 0/291 OA
Microcontroller

REGISTER DESCRIPTION (continued)
HOLC CONTROL REGISTER 1
HOLC Control Resister 1 (HOLC1) SFR Address C1
Byte Addressable
Reset State OOh
BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT 1

BITO

HOLC
RST

CCITT

CRC
PRE

RXCRC
32

RXCRC
16

TXCRC
CTRL

ZERO

HOLC
EN

10

This register controls the basic set-up of the HOLC block. This register will be written during initialization and
not during normal message processing.

BIT 7 HOLC Software Reset
When BIT7 is a 1 ,the HOLC circuit is reset and held in a low power state and no interrupts from the HOLC circuitry
will be generated. When a 0 is written to this bit, the HOLC circuit will behave according to its control bits. BIT
7 and the power on reset Signal are OR'ed together to form a reset signal for the HOLC block.
BIT 7 is cleared to a 0 upon a power up reset.

BIT 6 CRC Type Control
BIT 6 selects the CRC algorithm used in the 16 bit CRC calculation. There are two types of 16-bit CRCs
commonly used, CRC16 and the CCITT 16-bit CRC. If this bit is set to a 1, the CCITT type is selected.
BIT 6 is cleared to a 0 upon a reset.

BIT S CRC Preset Value
BIT 5 selects the reset value for the CRC generator and receiver. If this bit is set to a 1 , the CRC generator and
receiver are initialized to ones and if this bit is reset to a 0, they are initialized to Os. This bit should be set to a
1 for most CCITT polynomials.
BIT 5 is cleared to a 0 upon a reset.

BIT 4 BIT 3 RX CRC Control
BIT 4 and BIT3 determine the type of CRC remainder that will be checked at the end of a received frame. There
is a 16-bit CRC, and a 32-bit CRC that the HOLC block can support. If both BIT 4 and BIT 3 are reset, bits 7 and
6 of the HOLC STATUS register will be held to a O. If both BIT 4 and BIT 3 are 1s, a special CRC search mode
is enabled where both bits 7 and 6 of the HOLC status register are enabled. This mode is used during a
connection to determine whicnCRC is used by the initiating modem. If the 16-bit CRC remainder is not matched
at the end of the received frame, then BIT 6 of the HOLC STATUS register is set. If the 32-bit CRC remainder
is not matched at the end of the received frame, then BIT 7 of the HOLCSTATUS register is set. Once the correct
CRC type is established during a connection, either BIT 4 or BIT 3 should be set to a 1 enabling the appropriate
INVALID CRC status bit.

BIT4

BIT3

0

0

NO CRC Check

0

1

Enable CRC16 Status

1

0

Enable CRC32 Status

1

1

Enable CRC16 Status and CRC32 Status

CRCTYPE

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SSI 73M291 0/291 OA
Microcontroller

BIT 2 TXCRC Control
BIT 2 controls the CRC type to be transmitted. If BIT 2 is reset to a 0, a 16-bit CRC will be transmitted with the
SEND CRC command. If BIT 2 is set to a 1, a 32 bit CRC will be transmitted.
BIT 1 Zero Insert/Delete Control
When BIT 1 is set to a 1, a 0 will be transmitted if either the SEND DATA or SENDCRC bits of the HDLCTX
CONTROL are set after five consecutive 1s have been transmitted. Also, when this bit is set, aO will be removed
from the received data stream if it immediately follows a pattern of a 0 followed by five consecutive ones. If BIT
1 is reset to a 0, no Os will be inserted during transmission, and no Os will be deleted during reception.
BIT 1 is cleared to a 0 upon a reset.
BIT 0 HOLC Interupt Enable
When BIT 0 is reset to a 0, the HDLC will be prevented from generating an interrupt. The status bits that indicate
the source of the interrupt
, can still be set allowing the HDLC block to be serviced in a polled mode.
BIT 0 is cleared to a 0 upon reset.
HDLC TX Control Resister (HTXC) SFR Address C2
Byte Addressable
Reset State OOh
BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT 1

BITO

0

0

0

DIV16
CLK

SEND
ABORT

SEND
CRC

SEND
DATA

SEND
FLAG

This register is used to control the source of data that appears on the PTXD pin. Bits are shifted out on every
rising edge of the PTXCLK pin input. If no control bits are set, or more than 1 TX CONTROLbit is set, the PTXD
pin will go to a binary 1.
BIT 7 • BIT 5 Always 0
BIT 4 16X Clock Select
Under normal synchronous operation, the PTXCLKand PRXCLK are used to receive and transmit data PRXD
and PTXD. The clock rate is equal to the data rate. In asynchronous modes, a clock 16 times the bit rate is
provided at PTXCLK a.nd PRXCLK.
When BIT 4 is set to a 1 for asynchronous operation, the clocks at the PTXCLK and PRXCLK pins are divided
by 16 to provide transmit and receive shift clocks. An internal clock for sampling incoming PRXD data is
synchronized by detecting any falling edge on the PRXD data pin. The rising edge of this internal clock, which
used to sample incoming data, is delayed from the falling data edge by 8 PRXCLK periods and will continue at
this phase and at a PRXCLK/16 frequency until another falling PRXD edge is detected.
If BIT 4 is reset to a 0, the rising edge of PTXCLK is used to sample the data at PRXD, and the falling edge of
PTXCLK is used to shift new data onto PTXD.
BIT 3 is cleared to a 1 upon a reset.

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Microcontroller

REGISTER DESCRIPTION (continued)
BIT 3 Abort
When BIT 3 is set to a 1, a series of consecutive ones will immediately be transmitted through the PTXO pin on
every falling edge of PTXCLK. The message will have been aborted after 2 TX ready interrupts are received.
No zeros will be inserted during the abort transmission.
BIT 3 is cleared to a 1 upon a reset.

BIT 2 Send CRC
When BIT 2 is set, the bytes in the TX CRC generatorwill be inverted and serially transmitted to the PTXO output
on the falling edge on PTXCLK as soon as the present data byte transmission is completed. If BIT 1 of the HOLC
control register is a 0, aO will be inserted into the CRC data stream after five consecutive ones are transmitted.
As soon as the last bit of the CRC is sent, a series of Flags will be automatically sent until another TX control
bit is set. No TX Ready interrupts will be generated during the transmission of the CRC bytes. A TX Ready
interrupt will be generated as the first bit of each Flag byte is transmitted indicating that the CRC transmission
has been completed. This should be cleared by a dummy write to the TX DATA register.
BIT 2 will be cleared to a 0 upon a reset.

BIT 1 Send Data
When BIT 1 is set, the data is the TX data register will be serially transmitted through the PTXO pin on every
falling edge of PTXCLK, LSB first. If BIT 1 ofthe HOLC control register is a 0, a 0 will be inserted into the data
stream after five consecutive 1s are transmitted. After all eight data register bits have been sent, the HOLC will
continue to send data by loading the parallel serial transmit register with new transmit register data, unless either
a TX underrun is detected or one of the other TX control bits has been set. This bit will be cleared by the HOLC
circuitry as soon as a TX underrun is detected. A TXROY interrupt will be generated at as the first data of each
data byte is transmitted. BIT 1 will be cleared to a 0 upon a reset.

BIT 0 Send Flag
When BIT 0 is set, a pattern of 7E will be transmitted to the PTXO output as soon as either the next data byte
or CRC has completed transmission. No Os will be inserted during the flag transmission. When BIT 0 is reset
back to a 0, the HOLC circuitry will complete the flag byte in progress and then transmit according to bits in the
TX CONTROL register. TX Ready interrupts will be generated as each byte of flag transmission is initiated.
BIT 0 will be cleared to a 0 upon a reset.

HOLC STATUS REGISTER
HOLC Status Register (HSTAT) SFR Address C3
Byte Addressable
Reset state OOh
Read only register
If any of the HOLC status bits are set, BIT 1 of the HOLC INTERRUPT register (NEW STATUS) will be set
if the corresponding bit in the HOLC INTERRUPT ENABLE register is set.

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT 1

BITO

INVAL
CRC32

INVAL
CRC16

TX
UNDRN

RX
OVRN

INVAL
FLAG

ABORT
OET

IDLE
DET

FLAG
OET

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551 73M291 0/291 OA
Microcontroller

BIT 7 Invalid CRC32
BIT 7 will be set if the CRC search mode or the 32-bit CRC is enabled by the HDLC control register and an
incorrect remainder for the 32-bit CRC is detected at the last received byte prior to receiving a flag.
BIT 7 will by cleared upon a reset and is cleared by a read of the HDLCSTAT register.

BIT 6 Invalid CRC16
BIT 6 will be set if the CRC search mode or the 16-bit CRC is enabled by the HDLC CONTROL register and an
incorrect remainder for the 16-bit CRC is detected at the last received byte prior to receiving a flag.
BIT 6 will by cleared upon a reset and is cleared by a read of the HDLC STAT register.

BIT 5 TX Underrun
When BIT 5 is set, a transmit underrun condition has been detected. This is a condition where the HDLC has
finished transmitting a message byte, but no new data has been loaded into the TX DATA register, and no other
transmit control bit has been set. This bit will be set only if the SEND DATA bit, BIT 1 ofthe TXCONTROL register
is set. The transmit data is double buffered since the TX data register is downloaded into a TX serial register
when the HDLC begins to transmit a new data byte. At the time of loading the TX serial register, a TX READY
interrupt is generated. This interrupt must be serviced by either loading a new data byte (the next data byte to
be transmitted) into the TX data register, or by setting another TX control bit, before the current data byte has
completed transmission (at which point another TX READY interrupt would be generated). If a TX UNDER RUN
is detected, the HDLC will abort the current transmission by sending continuous ones and will reset the SEND
DATA control bit in the TX CONTROL register.
BIT 5 will by cleared upon a reset and is cleared by a read of the HOLCSTAT register.

BIT 4 RX Overrun
When BIT 4 is set, a receive overrun condition has been detected. This is a condition where the HOLC has
received a new byte, but the last received data byte has not yet been read from the RX data register. As soon
as a new data byte has been received in an eight bit serial register, it is loaded into the RX data register and a
NEW RX DATA interrupt is generated. If this interrupt is not serviced by reading the RX data register during the
time another new data byte is received, the RX OVERRUN status bit will be set. The new received data will not
overwrite the older unread data.
BIT 4 will by cleared upon a reset and is cleared by a read of the HOLCSTAT register.

BIT 3 Invalid Flag
When BIT 3 is set, an invalid flag has been detected. This is a condition where a 7E pattern with no inserted Os
is detected, and this pattern did not originate on a byte boundary. Note, two consecutive flags may share a 0,
so that the second (or subsequent) flag may not appearto be on a byte boundary. This condition does not result
in an invalid flag indication.
BIT 3 will by cleared upon a reset and is cleared by a read of the HOLC STAT register.

BIT 2 Abort Detect
When BIT 2 is set, an abort condition has been detected. This is a condition where seven consecutive ones, with
no inserted zeros, are received after an active state. BIT 2 will be cleared upon a reset and is cleared by a read
of the HOLC STAT register.

4-27

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SSI 73M291 0/291 OA

Microcontroller

REGISTER DESCRIPTION (continued)
BIT 1 Idle Detect
When BIT 1 is set, the first indication of an idle state is detected. An idle state is declared when 15 consecutive
ones, with no inserted zeros, are received after an active state.
BIT 1 will be cleared upon a reset and is cleared by a read of the HOLC STAT register.
BIT 0 Flag Detect
When BIT 0 is set, the HOLC has received a 7E pattern with no inserted O's. BIT 0 will by cleared upon a reset
and is cleared by a read of the HOLCSTAT register.
HDLC INTERRUPT ENABLE REGISTER
HDLC Interrupt Enable Register (HIE) SFR Address C4
Byte Addressable
Reset state OOh
If the bit is set, the corresponding interrupt source is enabled.
BIT 7

BIT6

BIT5

BIT4

BIT3

BIT 2

BIT 1

BITO

TXROY
IE

RXROY
IE

TX ROY
EN

RX ROY
EN

INVAL
FLG IE

ABORT
IE

IDLE
IE

FLAG
IE

BIT 7 Transmitter Ready Interrupt Enable
When BIT 7 is set, an HOLC interrupt will be generated if BIT 0 ( TX ROY) of the HOLC INTERRUPT register
is also set. If BIT 7 is reset to a 0, no HOLC interrupt indication will be given as TX ROY is set. This interrupt enable
allows the TX ROY to be a polled bit. Note that BIT 5 of this register is a pre-mask to the TX ROY bit, that is, it
will prevent the TX ROY bit from ever being set.
BIT 7 will be cleared upon a reset.
BIT 6 Receiver Ready Interrupt Enable
When BIT 6 is set, an HOLC interrupt will be generated if BIT 1 ( RXROY) of the HOLC INTERRUPT register
is also set. If BIT 6 is reset to a 0, no HOLC interrupt indication will be given as RX ROY is set. This interrupt
enable allows the RX ROY to be a polled bit. Note that BIT 4 of this register is a pre-mask to the RX ROY bit,
that is, it will prevent the RX ROY bit from ever being set.
BIT 6 will be cleared upon a reset.
BIT 5 Transmit Ready Enable
BIT 5 is used to enable the TX ROY and TX UNOERRUN interrupt sources. When BIT 5 is set, the transmitter
ready indication will set BIT 0 of the HOLC interrupt register. The TX ROY indication will go active as the first
bit of a message byte is being transmitted, except during CRC transmission. Also, if this bit is set, the TX underrun
condition will result in a NEW STATUS interrupt. If IT5 is reset to a 0, BIT 0 of the HOLC INTERRUPT register
will not be set, and no corresponding HOLe interrupt will be generated. Also, a Tx underrun condition, as
indicated by BIT 5 of the HOLC STATUS register, will not result in an HOLC interrupt or in setting the NEW
STATUS interrupt bit.
BIT 5 will be cleared upon a reset.

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SSI 73M291 0/291 OA
Microcontroller

BIT 4 Receiver Ready Enable
BIT 4 is used to enable the RX RDY and RX OVERRUN interrupt sources. When BIT 4 is set, the receiver ready
indication will set BIT 1 of the HDLC INTERRUPT register. The RX RDY indication will go active when a data
byte (a byte that is not a flag, idle, or an abort pattern) is loaded into the RX DATA register. Also, if this bit is set,
the RX overrun condition will result in a NEW STATUS interrupt. If BIT 4 is reset to a 0, BIT 1 of the HDLC
INTERRUPT registerwill not be set, and no corresponding HOLC interrupt will be generated. Also, a Rx overrun
condition, as indicated by BIT 4 of the HDLC STATUS register, will not result in a HOLC interrupt or in setting
the NEW STATUS interrupt bit.
BIT 4 will be cleared upon a reset.

BIT 3 Invalid Flag Interrupt Enable
When BIT 3 is set, a HOLC interrupt will be generated if BIT 3 ( INVALI D FLAG) of the HDLC STATUS register
is also set. If BIT 3 is reset to a 0, BIT 2 ( NEW STATUS) of the HOLC INTERRUPT register will not be set as
a result of an invalid flag boundary detection and no HOLC interrupt will be generated.
BIT 3 will be cleared upon a reset.

BIT 2 Abort Detect Interrupt Enable
When BIT 2 is set, a HOLC interrupt will be generated if BIT 2 (ABORT DETECT) of the HDLC STATUS register
is also set. If BIT 2 is reset to a 0, BIT 2 ( NEW STATUS) of the HOLC INTERRUPT register will not be set as
a result of an abort pattern detection and no HDLC interrupt will be generated.
BIT 2 will be cleared upon a reset.

BIT 1 Idle Detect Interrupt Enable
When BIT 1 is set, an HDLC interrupt will be generated if BIT 1 (IDLE DETECT) of the HOLC STATUS register
is also set. If BIT 1 is reset to a 0, BIT 2 (NEW STATUS) of the HOLC INTERRUPT register will not be set as
a result of an idle pattern detection and no HDLC interrupt will be generated.
BIT 1 will be cleared upon a reset.

BIT 0 Flag Detect Interrupt Enable
When BIT 0 is set, a HDLC interrupt will be generated if BIT 0 (FLAG DETECT) of the HDLC STATUS register
is also set. If BIT 0 is reset to a 0, BIT 2 (NEW STATUS) of the HDLC INTERRUPT register will not be set as
a result of a flag pattern detection and no HOLC interrupt will be generated.
BIT 0 will be cleared upon a reset.

HDLC INTERRUPT REGISTER
HDLC Interrupt Register (HINT) SFR Address CS
Byte Addressable
Read Only register
Reset State OOh
BIT7

BIT6

BITS

BIT4

BIT 3

BIT 2

BIT 1

BITO

0

0

0

0

0

NEW
STAT

DATA
ROY

TX
RDY

This register is used to determine the source of HDLC interrupts. If one or more of these register bits are
set, the HOLC interrupt will go active if BIT 0 of the HDLC CONTROL register is set to a 1.
4-29

I

SSI 73M291 0/291 OA

Microcontroller

REGISTER DESCRIPTION (continued)
BIT 2 New Status
When BIT 2 is set, an unmasked HDLC status bit from the HDLC STATUS register is set.
BIT 2 will by cleared upon a reset and is cleared by a read of the HDLC STATUS register.
BIT 1 Data Ready
When BIT 1 is set, a new received byte has been loaded into the RX DATA register. Note, received bits that are
flag, abort, or idle patterns are not considered data, and will not be loaded into the RX DATA register. All inserted
Os have been removed from this byte. The RX DATA register must be read priorto the completed reception of
the next data byte.
BIT 1 will by cleared upon a reset and is cleared by a read of the RX DATA register.
BIT 0 TX READY
BIT 0 is set if any TX control bit is set as the first bit of data, flag or an idle byte is being transmitted. While
transmitting the current byte, the HDLC state machines are ready for commands pertaining to the next byte to
be transmitted. A new data byte must be loaded into the TX DATA register to clear the TX READY status bit.
BIT 0 will by cleared upon a reset and is cleared by writing to the TX DATA register.
RX DATA REGISTER
RX Data Register (RXD) SFR Address C6
Byte Addressable
Reset state XXh
Read Only
BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT 1

BITO

RX
DAT7

RX
DAT6

RX
DAT5

RX
DAT4

RX
DAT3

RX
DAT2

RX
OAT

RX
DATO

BIT 7 • BIT 0 Received Data Byte
BIT7through BITO isthe received data byte (LSB is received first) with all inserted Os removed. A DATA READY
interrupt will be generated when a new data byte is received. Reading this register will clear the DATA READY
interrupt.
TX DATA REGISTER
TX Data Register (TXD) SFR Address C7
Byte Addressable
Reset state XXh
Write Only
BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT 1

BITO

TX
DAT7

TX
DAT6

TX
DAT5

TX
DAT4

TX
DAT3

TX
DAT2

TX
DAT1

TX
DATO

BIT 7 • BIT 0 Transmit Data Byte
BIT 7through BIT Owi" be transmitted atthe next byte boundary (LSB first) if the TX CONTROL SEND DATA
bit is set. The HDLC will insert all necessary Os. A TX READY interrupt will be generated when a new data
byte can be loaded into the TX DATA register. Writing this register will clear the TX READY interrupt.
4-30

SSI 73M291 0/291 OA

Microcontro'ller

REGISTER

ADDRESS

BIT 7

BIT 6

BIT 5

BIT4

BIT3

BIT 2

BIT 1

BITO

HDLC
CONTROL 0

CO

WRXD

WPTXD

TXD

PRXD

RXD
CTRL1

RXD
CTRLO

HDLC
CONTROL1

C1

RESET

CCID

CRC
PRE

RXCRC32

RXCRC16

TXCRC32

PTXD
CTRL1
ZERO

PTX
CTRLO
HDLC

10

EN

TX

C2

0

0

0

SEND
DATA

SEND
FLAG

INVAL
CRC32
TX RDY
IE

TXRDY

EN

EN

ABORT
DETECT
ABORT
IE

C5

0

0

0

0

0

NEW
STATUS

IDLE
DETECT
IDLE
IE
RX
READY

FLAG
DETECT

C4

INVAL
CRC16
RXRDY
IE

SEND
ABORT
INVAL
FLAG
INVAL
FLAG IE

SEND
CRC

C3

DIV16
CLK
RX
UNDERRUN
RX RDY

C6

RXDAT7

RXDAT6

RXDAT5

RXDAT4

RXDAT3

RXDAT2

RXDAT1

RXDATO

TXDAT1

TXDATO

CONTROL
HDLC
STATUS
HDLCINT
ENABLE
HDLCINT
SOURCE
RX DATA
TX DATA

C7

TXDAT7

TXDAT6

TX
UNDERRUN

TXDAT5

TXDAT4

TXDAT3

TXDAT2

FLAG
IE

TX
READY

FIGURE 9: HOLC SFR Registers

I
CCID 16 Bit CRC X'S + X'2 + X5 + 1

FIGURE 10: CCITI Type
The CRC check field is generated by the transmitter.
The computation starts with the first transmitted bit
after the opening flag and stops at the last data bit prior
to the frame check sequence bytes, and excludes
inserted Os. The CRG generating logic is initialized to
all ones. The bits are shifted in and operated on by the
generating polynomial, X 16 + X 12 + X 5 + 1. During CRC
transmission, the bytes in the CRC generating logic are
inverted and transmitted, high order bit first.

The receiver also initializes its C RC computation logic
to all ones after the beginning flag. Its polynomial
generator (also X 16 + X12+ X 5 + 1) should see the same
value as the transmitter's polynomial generator as the
last data bit is received. Note the receiver's polynomial
generator does not process inserted Os. After the bytes
are received in the frame check sequence, a remainder
of 1111 0000 1011 1000 (Xo through X15 , respectively)
should be detected in the receiver's polynomial generator. If this is not the case, it is assumed that the
preceding frame was in error and an invalid eRe is
declared.

4-31

SSI 73M291 0/291 OA
Microcontroller

REGISTER DESCRIPTION

(continued)

RESET (option to set)
COMPUTE

DATA

FIGURE 11: CRC 16
The CRC check field is generated by the transmitter.
The computation starts with the first transmitted bit after
the opening flag and stops at the last data bit prior to the
frame check sequence bytes, and excludes inserted
as. The CRC generating logic is initialized to all as. The
bits are shifted in and operated on by the generating
polynomial, X 16 + X 12 + X5 + 1. During CRC transmission, the bytes in the CRC generating logic are transmitted, high order bit first.

4-32

The receiver also initializes its C RC computation logic
to all ones after the beginning flag. Its polynomial
generator (also X 16 + X 12 + X5 + 1) should see the same
value as the transmitter's polynomial generator as the
last data bit is received. Note the receiver's polynomial
generator does not process inserted Os.·Afterthe bytes
are received in the frame check sequence, a remainder
of 1111 0000 1011 1000 should be detected in the
receiver's polynomial generator. If this is not the case,
it is assumed that the preceding frame was in error and
an invalid CRC is declared.

SSI 73M291 0/291 OA

Microcontroller

SET
DATA

I
FIGURE 12: 32 Bit CRC
The CRC check field is generated by the transmitter.
The computation starts with the first transmitted bit
after the opening flag and stops at the last data bit prior
to the frame check sequence bytes, and excludes
inserted Os. The CRC generating logic is initialized to
all ones. The bits are shifted in and operated on by the
generating polynomial, X32 +X 26 +X23 + X22 + X16 + X12
+ X11 +X 10 +X8+X7 + X5+X4 + X2+ X+ 1. DuringCRC
transmission, the bytes in the CRC generating logic are
inverted and transmitted, high order bit first. The receiver also initializes its CRC computation logic to all

ones after the beginning flag. Its polynomial generator
should see the same value as the transmitter's polynomial generator as the last data bit is received. Note the
receiver's polynomial generator does not process inserted Os. After the bytes are received in the frame
checksequence,aremainderof1101111010111011
0010 0000 1110 0011 (Xo) through X32 , respectively)
should be detected in the receiver's polynomial generator. If this is not the case, it is assumed that the
preceding frame was in error and an invalid CRC is
declared.

4-33

SSI 73M291 0/291 OA
Microcontroller

PIN DESCRIPTION
NAME

TYPE

PSEN

0

Program store enable. This output occurs only during a fetch to external
program memory.

RESET

I

Input which is used to initialize the processor.

VND
OSCIN
OSCOUT
VPD
CLKOUn
CLKOUT2

GND
I

0
I

0
0

DESCRIPTION

Negative digital voltage ground
Crystal input for internal oscillator, also input for external source.
Crystal oscillator output.
Positive digital voltage (+5V Digital Supply)
Clock output programmable either OSC/2, OSC/1 or logic O.
Clock output 1.8432 MHz clock for an external UART given an oscillator
frequency of 11.0592 MHz, 22.1184 MHz, 18.432 MHz, or 13.824 MHz.

TXD

I

Serial input port to 73M2910 from DTE same as RXD UART input.

RXD

0

Serial output port of 73M291 0 UART to DTE.

PTXCLK

I

Input clock used to transmit data PTXD.

PTXD

0

HDLC Packetizer TX output. This pin can also be programmed to the DTE's
TXD output (clear channel) or the value written into bit 6 of the HDLC control
register. Connects to modem device TXD.

PRXCLK

I

Input clock used to receive data PRXD.

PRXD

I

Serial input port (from modem device).

INT(O)-INT(2)

I

External interrupt 0,1 and 2.

110

User programmable I/O port.

USR1 (0) -USR1 (7)
USR2(0) -USR2(7)

I/O

User programmable 110 port.

USR3(0) -USR3(7)

110

User programmable I/O port. If the bank select feature is chosen, USR (7) acts
as address bit 17and USR3databit7is ignored. Register BNKSELbit2 (BSEN)
enables bank select, bit 1 (BS1) and bit 0 (BSO) select the appropriate bank.

USR4(O) -USR4(7)
USR5(0) - USR5(1)

110
110

RD

0

Output strobe activated during a bus read. Can be used to enable data onto
the bus from an external device. Used as a read strobe to external data
memory.

WR

0

Output strobe during a bus write. Used as a write strobe to external data
memory.

ALE

0

Address Latch Enable output pulse for latching the low byte of the address
during accesses to external memory.

AD(0)-AD(7)

I/O

Data bus lines-I/O for devices that require multiplexed address and data bus.

A(O)-A(15)

0

Address bus lines-output latched address for devices that require separate
data and address bus.

NO CONNECTS

User programmable I/O port also Chip select enable.
General purpose input port, can also be used for wakeup.

No connections, leave open.

4-34

SSI 73M291 0/291 OA
Microcontroller

External RAM
(Movx data, addr)

FFh

I

Internal RAM
Indirect addressing only
(mov@Ri)

OOh

SFRs direct addressing only
(Mov data, addr)
Direct & Indirect addressing
(mov data, addr)
(mov@Ri)

OOh

FIGURE 1: Memory Map

BANK 3

ADDRESS

96K -128K

32K -64K

64K - 96K

32K -64K

BANKO

BANKO

BANKO

ADDRESS

ADDRESS

ADDRESS

O·32K

0-32K

0-32K

BANK 1

SELECTED

BANK 2

SELECTED

BANK 3

SELECTED

FIGURE 2: 128K of Bank-Selected Program Memory
4-35

0-32K

SSI 73M291 0/291 OA
Microcontro Iler

Address locations 0008 - OOFF are reserved for future use

I
I

0008
0000

USER3

DIR3

I
I
I BNKSEL I

USER4

I
I

DIR4

I
I

CSEN

I
I

I
I

OOOF
0007

FIGURE 3: Memory Mapped Registers

F8
FO

FF
F7

B

EF

E8
ACC

E7

08

"USER2

OF

DO

PSW

C8

T2CON

co

"HDLCO

B8

IP

BF

IE

AF

EO

"DIR2

CLKCTRL

07

"HDLC1

RCAP2L

RCAP2H

TL2

TH2

"TXC

"HSTAT

"HIE

"HINT

CF
"HRXD

"HTXD

80
A8

C7

B7

A7

AO

P2

98

SOON

SBUF

90

"USER1

"DIR1

"IDIR

88

TCON

TMOD

TLO

TL1

80

PO

SP

DPL

DPH

9F
97
THO

8F

TH1
PeON

87

" Unique to the SSI 73M2910. There may not be an equivalent function on an 8052.
BIT ADDRESSABLE

FIGURE 4: 73M2910 SFR Map
4-36

SSt 73M291 0/291 OA
Microcontroller

ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Recommended conditions apply unless otherwise specified.
RATING

PARAMETER
Supply Voltage

-0.5 to +7.0V

Pin Input Voltage

-0.5 to Vcc +0.5V

Storage Temperature

-55 to + 150°C

RECOMMENDED OPERATING CONDITIONS
4.5 to 5.5V

Supply Voltage
Oscillator Frequency

DC to 33 MHz

Supply Voltage

4.75 to 5.5V

Oscillator Frequency

DC to 44 MHz

Supply Voltage

3.0 to 5.5V

I

DC to 22 MHz

Oscillator Frequency
~Operating Temperature

-40 to +85°C

DC CHARACTERISTICS
MAX

UNIT

VIL
Input Low Voltage
(Except OSCIN, RESET, TEST)

-0.5

0.2 Vee - 0.1

V

Input Low Voltage
OSCIN, RESET, TEST

-0.5

0.2 Vcc

V

VIH
Input High Voltage
(Except OSCIN, RESET, TEST)

0.5 Vcc

Vee + 0.5

V

Input High Voltage
OSCIN, RESET, TEST

0.7 Vce

Vee +0.5

V

PARAMETER

MIN

CONDITION

VIL

VIH

NOM

Output Low Voltage
(Except OSCOUT)

VOL

101

= 3.2 rnA

0.45

V

Output Low Voltage
OSCOUT

VOLOSC

101

= 1.5 rnA

0.7

V

Output High Voltage
(Except OSCOUT)

VOH

Output High Voltage
OSCOUT

VOHOSC

loh

= -3.2 rnA

loh = 1.5 rnA

Vee - 0.45

V

Vee - 0.7

V

Maximum Power Supply
Normal Operation

IDD1

22MHz
30 pF/pin

40

IlA
rnA

Maximum Power Supply
Idle Mode

IDD2

22 MHz

10

rnA

Input Leakage Current

ilL

Vss < Vin < Vee

4-37

±10

SSI 73M291 0/291 OA

Microcontro Iler

ELECTRICAL SPECIFICATIONS (continued)
DC CHARACTERISTICS
PARAMETER

CONDITION

Maximum Power Supply
Power Down Mode
Pin Capacitance

MIN

1003
CIO

@1 MHz

NOM

MAX

UNIT

10

/-1A

10

pF

22.2

MHz

ACTIMING

Oscillator Frequency

FOSC

Oscillator Period

TOSC

0
45

ALE Pulse Width

TLHLL

2TOSe -10

ns

TOSC

ns

Address Valid To ALE low TAVLL

ns

Address Valid ALE low

TLLAX

TOSe -10

ns

ALE low to PSEN low

TLLPL

TOSe -10

ns

PSEN Pulse width low

TPLPH

3TOSe - 20

ns

PSEN Low to Valid Inst In

TPLIV

3TOSe - 50

ns

Address to Valid Inst In

TAVIV

STOSe -50

ns

Input Instr Hold-PSEN Hi

TPXIX

PSEN Instr Float-PSEN Hi

TPXIZ

0

PSEN Low to Address HIZ TPLAZ
RD Pulse Width

TRLRH

6TOSe - 20

WR Pulse Width

TWLWH

6TaSe - 20

RD Low to Vlaid Data In

TRLDV

Data Hold After RD

TRHDX

Data Float After RD

TRHDZ

ALE Low to Valid Data In

TLLDV

ns

20+
10

ns

0

3TOSe - 20

Data Valid to WR low

TQVWX

TOSC

Data Hold After WR Hi

TWHQX

rose -10

RD low to Address Float

TRLAZ

ns
ns

20+

ns

8TaSe -50

ns

3TOSe +20

ns
ns
ns

10

4-38

ns
ns

STaSe - 50

ALE low to RD or WR low TLLWL

ns

ns

SSI 73M291 0/291 OA
Microcontro Iler

AC TIMING

(continued)

The SSI 73M2910 timing is very similar to the 8051
except in AD(7:0), the multiplexed address data port
known as port 0 in the 8051. Its timing has been altered
somewhat to allow more address setup time for
peripheral program ROM and memory mapped
peripherals. This is important at 22 MHz operation.
The 8052 has a "dead" cycle of one oscillator period
between the time PSEN goes high, indicating that the
instruction ROM will release the AD(7:0) bus, to the
time the processor will assert address on the AD(7:0)
bus. This dead time of one whole oscillator cycle has
been shortened to approximately 15 ns afterthe PSEN
(or RD) signal is sensed to be high.
The timing specification for TPXIZ and TRHDZ of a
maximum of 20 ns can be violated at the expense of
increased operating current. The SSI 73M2910 will
begin asserting the AD(7:0) bus approximately 20 ns
after PSEN or RD go high. This should be ample time
forthe control signals in the peripheral device to turn off
their pad drivers. If the peripheral device does not
release the bus promptly, there will be a short time
where there is contention on the AD(7:0) bus between
the processor and peripheral. This should not prevent
proper operation, but it will increase operating current
slightly.

I

4-39

SSI 73M291 0/291 OA
Microcontroller

USER INTERFACE

fA

fA

MR
CD
AA
OH
HS

AA

MR
CD

..

OH

TXA -

RS

...

'- -

Ai ...

RXA ...

~~

-..,.;

.

~
~

DCD ..

~~~

TELEPHOI'IIE INTERFACE

SSI 73D2248A DEVICE SET

-

DCD
CTS
RXD

~
~

DSR ....
RXCLK ...
TXCLK

L..

AGO

It.~

DRT
RTS
TXD
L.. _
~ DSR
~ RXCLK
- TXCLK

_ ...

TXA

r- RXA

...It.

'-~ EXCLK

EXCLK ~
DTR ...
RTS ..
TXD

..,..

.. POWER
HOOK

Ia._
"" AUX

t.._
~

,--.---

RING
AUX
HOOK
POWER
AG1
AGO

FIGURE 13: Modem Block Diagram

4-40

RING

SSI 73M291 0/291 OA
Microcontroller

VCC
(

~R~

~)I)I

1R

~~

R33
-A. A
~

fA

rI

2.4K
~

D~)I)I

TD

D7
~)I)I

RD

D8
~)I)I

,..1

~

2.4K
R39
-A. A

,..1

~

2.4K
R34

...,...,

Mi:

rJ

2.4K

D9

1' 1
3

CD

as

••..1)1)1

~v

rJ

2.4K

Ali.

D10

1'~A

AA

~)I)I

OH

D11
~)I)I

HS

D12
~)I)I

~v

a:<

'"I

2.4K
.A.R;Z
~

HS

I

rI

24K

A

R38
.A.

VCC

NOTE: 1 ~F TANTALUMS
U8
C13
21
C1+

YI+If----fr-

P1

~~
O~
""'0 ~
23

~O
~O
~

~
22

+8

20

~

-0
~

+e6

0-:
-

IS
5
17
4

15
2

y~~

EXCLK

1
RI

DCD
DTR

..2
3
4

I

DSR

I
I

RXD
1XCLK
TXD

0-: ~
1

-.::::

GND

vee
v+

C1C2+

v-

C2-

GND

C14

RATE

CTS
RXCLK
RTS

~
3

I

,..1

2.4K

I

8
7
6
5

J -Ta~
41

ENfA
TAl iN

TAlOUT
TA20UT
TA30UT
TA40UT

TA2IN
TAJIN
TMIN

ENAA

RA11N
RA21N
RA31N
RA41N

RA10UT
RA20UT
RAJOUT
RMOUT

EM'
TBIIN

TBlOUT
TB20UT
TB30UT
TB40UT

TB2IN
TB3IN
TB41N

~.
~~F
26

C16

19
18
14

I

:r; I
1\

GND

15
16

17

~GND
EXCLK

11
12
13

~GND
30
29

28

ENA ~VCC

~
~

RB11N
RB21N
RB31N
~ RB41N

RBI OUT
RB20UT
RB30UT

--?-

RB40UT

~

r#--

f-#-

~

CONNECTOR DB25
MAX248

FIGURE 14: Display and User Interface

4-41

AI
5CD
CfS
RX5

1

~
COOiCI
RXCLK

TXCLK

.1
1

3:
_. en
en

(')XMOUT

~

.o.l~F
Cl.ol

Al 05

1000pF

""" ......
Ow

Rl09

Cl02

I

511

2.ok

Ss:

XMOUT

::IN

Al.o6

"CD
"""....L

+SVD
11k

2.0
--.....

+5VO

CDN

~

TXA

"""CD
....L

**

---18

AXA-rn
---2

0

l>

MOIISUM""2s'

~

-'23

Cl07
lOOP

'\ AlII
RJll

38.4 k

390pF

CUTOFF

C104
.0.1 ~F

Cl0S

Jl02

~
+5 VA

.. SVD

DGND
~

III

il~

RJl
RJ2

~I ~

Cl.o6

1:..
I\)

RJS
RJ6

R113
56k

RJll

Al0?
S.l K
RING

Rl14

AING

+svo

330

C112
Rl08
33~F

SO

112W

NOlI-POlARIZED CAPACITOR

150101
AGND

TI1119

lN914

** The tracks to the wires within the dashed lines should be as short as possible.

FIGURE 15: Telephone Interface

551 73M291 0/291 OA
Microcontro Iler

NV(;jO

>

vee

r;::~N~ve;:K=t=~ ~~

s~

e,

H

GND

jJCONTFO...lER

20pF
OSCIN

0000

DI1e!~
20pF

~r~,------------------~

ClK'oull-,:-:-,-------------PE~:~

"

,."

USR3.1
USR3.0

"

USR2.6

.~
6D

-rr-

~
.,

WR

AD

USR2.5

A14

USR2.4

'"

USR2.~

rIT---«>

,.
17

,.

USR2.2
USR2.1

A10

USA2.D

All

USR1.6

~
~

rru--s

-~

IRll~

\I

A13
A12

,.

"0
AB

12

A7

,

USA1.?

AS
AS

USA1.5

..::

GNO

~~88·;_'--_-.::_-.::_-.::_-_-_-_-.::_-_-1-+-_-_-_-_-_-_-_-_-_-_::

'0,

USR1.3

USR1.2

A3
A2

"AO

!ITA

YO

TXD

'7

INT,
INTO

lONG
'8

I

::

r-

M:i-------If+_""*~;-:_ _--.....1- ADO· AD7

PRXD
PTXD

D'

ADO r.;.,:~-----_--If+--"D"-O- - - . ....

PRXCLK

~e ~
--tr

...::::!!:
~

f=K

USR4.7

USR5.0
USR5.1

t-"!t:.-======ilj=~---r
r::"

P=

US~.O
us~.,

L-",-,=-----'
7:JM2S10

~

~

~

~
~

i'Owe!.

~

~

~
~
~
~

~
~
~
.,6
2D
22

All
A1

A2
A3

AS

..
A7

0'
0'
0,

12

D'

~~
,"

D'
D'
D'

,.,.

D'

AS

."
A14

CE

FIGURE 16A: SSI73D2248A Modem System Interconnect - Front End
4-43

I

SSI 73M291 0/291 OA
Microcontroller

I

WR--------------.-----------------~--..,
~----------~~---------------_r_,

ALE--++------t-!

~

R4

~

10K

~

~

~

l~

v

~:6
~

~

-

-

~

-

-

-

~

T

~

eLKOUT2 ----------------..,
________________________________

-

1~;~

J

U3

GNO

S2
(RESET)

DATA PUMP

'-+---~-o In

~-----":- 0.1 ).IF''

~>

R3
100K

vgo

U1

I ----1.

1 VOO

~ C4",~

:>
-l.

RXA
3 CAP
I
4 RXF
L--.§. FIL

ci"

1 ).IF

C3:;;"
0.1 ).IF
'::;".

rrl
rin<

TEST

I

1Mn

8 VSS

5GB
OSR
CTS
MR
OTR
RTS
AD
A1
A2
INTRPT

~
20

.J...C1
1:
30pF
= Typ.

1:
= 30pF
Typ.

VOO

~
~
~
24
~
22
19
18

TXA~

CLK~
OSC2~

~~D
---1L

VSS

73M1550

OSC1

13
TXO 12
RXO 11

SYN ~
SYNC

~

73M223

SSI 73M223 TYPICAL APPLICATION
4-55

00
01
02
03

D4
05
06
07
SIN
SOUT

CS2
XIN
XOUT

WR

1
2
3
4
5
6
7
8
9

~
11
~
~
14

S
T

I
N
T
E

R
F

A
C
E
"---

SSI73M223
1200 Baud FSK Modem

PACKAGE PIN DESIGNATIONS
(Top View)

VDD

TXA

RXA

2

CLK

CAP

3

OSC2

RXF

4

OSC1

FIL

5

TXD

TEST

6

TX

7

SYN

VSS

8

SYNC

11

RXD

16-Pin DIP and
16-Lead SOL

CAUTION: Use handling procedures necessary
for a static sensitive component.

ORDERING INFORMATION

PART DESCRIPTION

ORDER NO.

SSI73M223 16-Pin Plastic DIP

73M223 - CP

SSI 73M223 - CP

SSI 73M223 16-Lead SOL

73M223 - CL

SSI 73M223 - CL

PKG.MARK

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914

1293 - rev.

4-56

©1989 Silicon Systems, Inc.

Section

5

ANALOG SIGNALLING
& SWITCHING

I

5

5-0

SSI75T201
Integrated
DTMF Receiver

October 1991

DESCRIPTION

FEATURES

The 881 75T201 is a complete Dual-Tone Multifrequency (DTMF) receiver detecting a selectable group
of 12 or 16 standard digits. No front-end prefiltering is
needed. The only external components required are an
inexpensive 3.58 MHz television "colorburst" crystal
(for frequency reference) and two low-tolerance bypass capacitors. Extremely high system density is
made possible by using the clock output of a crystal
connected 881 75T201 receiver to drive the time bases
of additional receivers. The 881 75T201 is a monolithic
integrated circuit fabricated with low-power, complementary symmetry M08 (CM08) processing. It requires only a single low tolerance voltage supply and is
packaged in a standard 22-pin DIP.
(Continued)

•

Central office quality

•

NO front-end band-splitting filters required

•

Single, low-tolerance, 12-volt supply

•

Detects either 12 or 16 standard DTMF digits

•

Uses inexpensive 3.579545 MHz crystal for
reference

•

Excellent speech immunity

•

Output in either 4-bit hexadecimal code or
binary coded 2-of-8

•

22-pin DIP package for high system density

•

Synchronous or handshake interface

•

Three-state outputs

BLOCK DIAGRAM

I

BANDPASS FILTERS

i
TIMING I
CIRCUITRY I

,-------0

CLRDV

DV

,-------t-------LJ

H/B28

01
1Mz

D2

D4

08

EN
IN1633

.01mF

1091 - rev.

01mF

5-1

CAUTION: Use handling procedures necessary
for a static sensitive component.

SSI75T201
Integrated
DTMF Receiver
DESCRIPTION (Continued)

CRYSTAL OSCILLATOR

The SSI 75T201 employs state-of-the-art circuit technology to combine digital and analog functions on the
same CMOS chip using a standard digital semicondutor process. The analog input is preprocessed by
60 Hz reject and band splitting filters and then hardlimited to provide AGC. Eight bandpass filters detect
the individual tones. The digital post-processor times
the tone durations and provides the correctly coded
digital outputs. Outputs interface directly to standard
CMOS circuitry, and are three-state enabled to facilitate bus-oriented architectures.

The SSI 75T201 contains an onboard inverter with
sufficient gain to provide oscillation when connected to
a low-cost television "colorburst" crystal. The crystal
oscillator is enabled by tying XEN high. The crystal is
connected between XIN and XOUT. A 1 MQ 10%
resistor is also connected between these pins. In this
mode, ATB is a clock frequency output. Other
SSI 75T201 's may use the same frequency reference
by tying their ATB pins to the ATB of a crystal connected device. XIN and XEN of the auxiliary devices
must then be tied high and low respectively. Twentyfive devices may run off a single crystal-connected
SSI 75T201 as shown in Figure 2.

ANALOG IN
This pin accepts the analog input. It is internally biased
so that the input signal may be AC coupled. The input
may be DC coupled as long as it does not exceed the
positive supply. Proper input coupling is illustrated in
Figure 1.
vp

I
I
I
I
I

VINVP:

I
I
I
I
I

I
I
I
I

-

~~
~
Analog In I Q.
I
I
I
I
I

!

~DF

vp

I
I
I
I
I

.OlmF

I

~AA~
15

I

I
I
I
I
I

Q.

r---

f-

vp
XOUT

14
SSI75T201

ATB

-

>1~

Analog In

YYV

XIN

XEN
16-

17

XIN Connected to Vp

!

15
SSI75T201

FIGURE 1: Input Coupling

XEN
16f---

17

I

!

Up to 25 Devices

FIGURE 2: Crystal Connections

5-2

VND

551 75T201
Integrated
DTMF Receiver
H/B28
This pin selects the format of the digital output code. When H/B28 is tied high, the output is hexadecimal. When
tied low, the output is binary coded 2-of-8. The table below describes the two output codes.

Digit

1
2
3
4
5
6
7
8
9
0
*

#
A
B
C
D

Hexadecimal
08
04
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0

Binar~ Cod~d

02
0
1
1
0

0
1
1
0
0
1
1
0
0
1
1
0

01

Digit

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

1
2
3
4
5
6
7
8
9
0

08
0
0
0
0
0

*

#
A
B
C
D

0
1
1
1
1
1
1
0
0
1
1

04

2-of-8
02

0
0
0
1
1
1_~ --

0
0
0
1
1
1
0
1

0
1

0
0
1
0

0
1
0
0
1
0
0
1
1
1
1
1

01
0
1
0
0
1
0
0
1
0
1
0
0
1
1
1
1

TABLE 1: Output Codes
IN1633

OV and CLROV

When tied high, this pin inhibits detection of tone pairs
containing the 1633 Hz component. For detection of all
16 standard digits, IN1633 must be tied low.

DV signals a detection by going high after a valid tone
pair is sensed and decoded at the output pins D1, D2,
D4, and D8. DV remains high until a valid pause occurs
or the CLRDV is raised high, whichever comes first.

OUTPUTS 01, 02, 04, 08 and EN
INTERNAL BYPASS PINS, S1, S2
Outputs D1 , D2, D4, and D8 are CMOS push-pull when
enabled (EN high) and open circuited (high impedance) when disabled by pulling EN low. These digital
outputs provide the code corresponding to the detected digit in the format programmed by the H/B28 pin.
The digital outputs become valid after a tone pair has
been detected and they are then cleared when a valid
pause is timed.

Inorderforthe SSI75T201 DTMF Receivertofunction
properly, these pins must be bypassed to VNA with
0.01 /J-F ±20% capacitors.

5-3

I

SSI75T201
Integrated
DTMF Receiver
POWER SUPPLY PINS, Vp, VNA, VND
Row 0

The analog (VNA) and digital (VND) supplies are brought
out separately to enhance analog noise immunity on
the chip. VNA and VND should be connected externally
as shown in Figure 3.

Row 1

Row 2

Row 3

-==r-

12V

Coil

~

G G G

Col 2

Col 3

G G G ~
L2J G G G

D G G G

NOTE: Column 3 is for special applications
and is not normally used in telephone dialing.

6

+

ColO

FIGURE 4: DTMF Dialing Matrix

SSI75T201

=10%

13

4

DETECTION FREQUENCY
FIGURE 3: 12V System

N/C PINS
These pins have no internal connection and may be left
floating.

Low Group fo

High Group fo

Row 0 = 697 Hz

Column 0 = 1209 Hz

Row 1 = 770 Hz

Column 1 = 1336 Hz

Row 2 = 852 Hz

Column 2

Row 3

= 941

Hz

Column 3

= 1477 Hz
= 1633 Hz

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Operation above absolute maximum ratings may damage the device. All SSI75T201 unused inputs must be
connected to Vp or VND, as appropriate.
PARAMETER

RATING

DC Supply Voltage - Vp Referenced to VNA, VND

+16V

Operating Temperature

-40 to +85°C Ambient

Storage Temperature

-65 to + 150°C

Power Dissipation (25°C)

1W

--------------~

--- ----- --.--------

---

----~-------

Input Voltage (All inputs except ANALOG IN)

(VP+ 0.5V) to (VND -0.5V)

ANALOG IN Voltage

(Vp + 0.5V) to (Vp - 22V)

DC Current into any Input

±1.0 rnA

Lead Temperature - Soldering, 10 sec.

300°C

-

5-4

-----.-----~-------

--------------

551 75T201
Integrated
DTMF Receiver
ELECTRICAL CHARACTERISTICS
(-40°C ~ Ta ~ +85°C, Vp - VND = Vp - VNA
PARAMETER

= 12V ± 10%)

CONDITIONS

Frequency Detect Bandwidth

MIN

TVP

MAX

UNITS

± (1.5+2 Hz)

±2.3

±3.0

%of fo

Amplitude for Detection

each tone

-24

+6

dBm ref.
to 600n

Twist Tolerance

Twist High Tone
low Tone

-8

+4

dB

2

Vrms

a

dB*

60 Hz Tolerance
Dial Tone Tolerance

"precise" dial tone

Talk Off

M ITEl tape #CM 7290

"a" level, 750 JlA load
JlA load

Digital Outputs
(except XOUT)

"1" level, 750

2

hits

VND

VNo+0.5

V

Vp-O.5

Vp

V

Digital Inputs

"0" level

VNO

**

V

(except H/B28, XEN)

"1" level

***

Vp

V

Digital Inputs

"a" level

VNO

VNo+1

V

"1" level

Vp-1

Vp

V

25

mVp-p

50

mA

. H/B28, XEN

wide band

Power Supply Noise
Supply Current

29

Ta = 25°C
VP - VNA = VP - VND = 12V±10%

Noise Tolerance

M ITEl tape #CM 7290

Input Impedance

Vp

~

VIN

~

Vp - 22

--- - -

-12

dB*

100 kQI15 pF
--------

* dB referenced to lowest amplitude tone
** VND + 0.3(Vp - VNO)
*** Vp - 0.3(Vp - VNO)

TIMING CHARACTERISTICS
(-40°C ~ Ta ~ +85°C, Vp - VNO

= Vp

PARAMETER

- VNA

= 12V ± 10%)

CONDITIONS

MIN

TVP

MAX

UNITS

20

25

40

ms

tv

Tone Detection Time

tslh

Data Overlap of DV
Rising Edge

tp

Pause Detection Time

25

32

40

ms

tdv

Time between end of
Tone and Fall of DV

40

45

50

ms

ClRDV

= VNO,

EN = Vp

5-5

7

JlS

I

SSI75T201
Integrated
DTMF Receiver
TIMING CHARACTERISTICS (Continued)
PARAMETER
tshl

CONDITIONS

MIN

TYP

4

4.56

Data overlap of DV
Falling Edge

MAX
4.8
-~-.-

tphl

UNITS
ms
---

Prop. Delay: Rise of
CLRDV to fall of DV

CI = 300 pF
Measured at 50% points

1

IlS

Output Enable Time

CI = 300 pF, RI = 10K
Measured from 50% point
of Rising Edge of EN to
the 50% point of the data
output with RI to
opposite rail.

1

IlS

Output Disable Time

CI

= 300 pF,

RI

-_._-- - - - -

= 1K,

1

IlS

1

IlS

!:N= 1V

Measured from 50% point
of Falling Edge of EN to
time at which output has
changed 1V with RI to
opposite rail.
t-----~-~~

Output 10-90%
Transition Time

CI

--

= 300 pF

TONE BURST

ANALOG INPUT

P- tshl

...--_ _ _-+-_..:..J-+-,j.-

01 , 02, 04, 08

I

--ts'h-~~~---~~~F----~----~-

ov

tphl~ ~

---1-D_...I-.-____

CLROV _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

FIGURE 5: Timing Diagram

5-6

SSI75T201
Integrated
DTMF Receiver
6) Public phone line termination equipment must be
registered in accordance to FCC Part 68 or connected
through registered protection circuitry. Registration
typically takes about six months.

APPLICATION INFORMATION
TELEPHONE LINE INTERFACE
In applications that use the SSI 75T201 to decode
DTMF signals from a phone line, a DAA (Direct Access
Arrangement) must be implemented. Equipment intended for connection to the public telephone network
must comply with and be registered in accordance with
FCC Part 68. For PBX applications refer to EIA Standard RS-464.

Figure 6 shows a simplified phone line interface using
a 6000. 1:1 line transformer. Transformers specially
designed for phone line coupling are available from
many transformer manufacturers.
Figure 7 shows a more featured version of Figure 6.
These added options include:

Some of the basic guidelines are:

1) A 150-volt surge protector to eliminate high voltage
spikes.

1) Maximum voltage and current ratings of the
SSI75T201 must not be exceeded; this calls for protection from ringing voltage, if applicable, which ranges
from 80 to 120 volts RMS over a 20 to 80Hz frequency
range.

2) A Texas Instruments TCM1520A ring detector,
optically isolated from the supervisory circuitry.
3) Back-to-back Zener diodes to protect the DTMF
(and optional multiplexer Op-Amp) from ringer voltage.

2) The interface equipment must not breakdown with
high-voltage transient tests (including a 2500 volt peak
surge) as defined in the applicable document.

4) Audio multiplexer which allows voice or other audio
to be placed on the line (a recorded message, for
example) and not interfere with incoming DTMF tone
detection.

3) Phone line termination must be less than 2000. DC
and approximately 6000. AC (200-3200 Hz).

An integrated voice circuit may also be implemented
for line coupling, such as the Texas Instruments
TCM1705A, however, this approach is typically more
expensive than using a transformer as shown above.

4) Termination must be capable of sustaining phone
line loop current (off-hook condition) which is typically
18 to 120 rnA DC.
5) The phone line termination must be electrically
balanced with respect to ground.

TIP

:JII

,._-----l ANALOG

INPUT

SSI75T201

RING

1:1

::u::

1SOV

600z

FIGURE 6: Simplified Interface

FIGURE 7: Full Featured Interface
5-7

I

551 75T201
Integrated
DTMF Receiver
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
01

.1

22

02

H/B28

2

21

04

EN

3

20

08

VNO

4

19

CLROV

IN1633

5

18

OV

Vp

6

17

ATB

N/C

7

16

XEN

N/C

8

15

XIN
XOUT

81

9

14

82

10

13

VNA

N/C

11

12

ANALOG IN

22-Pin DIP
CAUTION: Use handling procedures necessary
for a static sensitive component.

ORDERING INFORMATION
PART DESCRIPTION
SSI75T201
22-Pin Plastic DIP

ORDER NO.

PKG.MARK

75T201 - IP

75T201 - IP

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and 'trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA ~2680-7022, (714) 573-6000, FAX: (714) 573-6914

1091 - rev.

5-8

©1989 Silicon Systems, Inc.

SSI 75T202/203
5V Low-Power
DTMF Receiver

October 1991

DESCRIPTION

FEATURES

The SSI 75T202 and 75T203 are complete Dual-Tone
Multifrequency (DTMF) receivers detecting a selectable group of 12 or 16 standard digits. No front -end
pre-filtering is needed. The only externally required
components are an inexpensive 3.58-MHz television
"colorburst" crystal (for frequency reference) and a
bias resistor. Extremely high system density is made
possible by using the clock output of a crystal-connected SSI75T202 or 75T203 receiver to drive the time
bases of additional receivers. Both are monolithic
integrated circuits fabricated with low-power, complementary symmetry MOS (CMOS) processing. They
require only a single low tolerance voltage supply and
are packaged in a standard 18-pin plastic DIP.

•
•
•
•
•

•
•
•
•
•
•

(Continued)

Central office quality
NO front-end band-splitting filters required
Single, low-tolerance, 5-volt supply
Detects either 12 or 16 standard DTMF digits
Uses inexpensive 3.579545-MHz crystal for
reference
Excellent speech immunity
Output in either 4-bit hexadecimal code or binary
coded 2-of-8
18-pin DIP package for high system density
Synchronous or handshake interface
Three-state outputs
Early detect output (551 75T203 only)

BLOCK DIAGRAM

I

BANDPASS FILTERS

ANALOG
IN
TIMING
CIRCUITRY

[ - - - - - - - - - - - - - 0 ED (75T203\

ONLY)

r - - - - - Q CLRDV

ATB

0------------,
DV

,-------+------LJ

HEXlB28

CHIP CLOCKS
01

1Mz

02

D4

08

EN
Vp

GNO

IN1633

I CAUTION: use.. h.a. ndling procedures necessary

1091 - rev.

5-9

for a static sensitive component.

551 75T202/203
5V Low-Power
DTMF Receiver
DESCRIPTION (Continued)

The 551 75T202 is deSigned to accept sinusoidal input
wave forms but will operate satisfactorily with any input
that has the correct fundamental frequency with harmonics less then -20 dB below the fundamental.

The 551 75T202 and 75T203 employ state-of-the-art
circuit technology to combine digital and analog functions on the same CM05 chip using a standard digital
semicondutor process. The analog input is pre-processed by 60-Hz reject and band splitting filters and then
hard-limited to provide AGC. Eight bandpass filters
detect the individual tones. The digital post-processor
times the tone durations and provides the correctly
coded digital outputs. Outputs interface directly to
standard CM05 circuitry, and are three-state enabled
to facilitate bus-oriented architectures.

CRYSTAL OSCILLATOR
The 551 75T202 and 75T203 contain an onboard
inverter with sufficient gain to provide oscillation when
connected to a low-cost television "colorburst" crystal.
The crystal OSCillator is enabled by tying XEN high. The
crystal is connected between XIN and XOUT. A 1 Mz
10% resistor is also connected between these pins. In
this mode, ATB is a clock frequency output. Other S51
75T202's (or 75T203's) may use the same frequency
reference by tying their ATB pins to the ATB of a crystal
connected device. XIN and XEN of the auxiliary
devices must then be tied high and low respectively.
Tendevices may run off a single crystal-connected SSI
75T202 or 75T203 as shown in Figure 2.

ANALOG IN
This pin accepts the analog input. It is internally biased
so that the input signal may be AC coupled. The input
may be DC coupled as long as it does not exceed the
positive supply. Proper input coupling is illustrated in
Figure 1.

HEX/B28
This pin selects the format ofthe digital output code. When HEX/B28 is tied high, the output is hexadecimal. When
tied low, the output is binary coded 2-of-8. The table below describes the two output codes.

Digit
1
2
3

4
5

6
7
8

9
0
*

#
A
B

C
D

Hexadecimal
08
04
0
0
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0

a
a
a

02

a
1
1
0

a
1
1
0
0
1
1

0
0
1
1

0

01
1

Digit
1
2
3

a
1
0
1
0
1
0
1
0
1
0
1
0
1
0

4
5

6
7
8

9
0
*

#
A
B
C
D

TABLE 1: Output Codes
5-10

Binary Coded_~-of-8
04
08
02
01
0
0
0 -0
-- 1
0
0
0
i--0
0
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
0
0
1
1
1
0
1
1
0
0
1 ----1
1
0
-1
1
1
0
- - - -----1
1
1
1

551 75T202/203
5V Low-Power
DTMF Receiver

Vp

Vp

VINVP

c:

.01mF

>-H-(,-1~~

>--( ~.-----I ~
Analog In

:

Q.

Analog In

I
I
I
I

-

:

-

I
I
I
I
I

I
I
I

I

GND

GND

I

FIGURE 1: Input Coupling

Vp

XOUT

XIN
12

11

XEN

SSI75T202

ATB

8

13

XIN Connected to Vp
12

XEN

SSI75T202

8

13

Up to 10 Devices

FIGURE 2: Crystal Connections
5-11

SSI 75T202/203

5V Low-Power
DTMF Receiver
IN1633

08 outputs are guaranteed to be valid when OV is high,
but are not necessarily valid when ED is high.

When tied high, this pin inhibits detection of tone pairs
containing the 1633 Hz component. Fordetectionof all
16 standard digits, IN1633 must be tied low.

N/C PINS
These pins have no internal connection and may be left
floating.

OUTPUTS 01, 02, 04, 08 and EN
Outputs 01, 02, 04, 08 are CMOS push-pull when
enabled (EN high) and open circuited (high impedance) when disabled by pulling EN low. These digital
outputs provide the code corresponding to the detected digit in the format programmed by the HEX/B28
pin. The digital outputs become valid after a tone pair
has been detected and they are then cleared when a
valid pause is timed.

DTMF DIALING MATRIX
See Figure 3. Please make note that column 3 is for
special applications and is not normally used in telephone dialing.

ColO
Row 0

DV and CLRDV
OV signals a detection by going high after a valid tone
pair is sensed and decoded at the output pins 01,02,
04, and 08. OV remains high until a valid pause occurs
or the ClROV is raised high, whichever is earlier.

Row 1

Row 2

ED (SSI 75T203 only)
Row 3

The ED output goes high as soon as the 551 75T203
begins to detect a OTM F tone pair and falls when the
75T203 begins to detect a pause. The 01,02,04, and

Col 1

Col 2

Col 3

G 0 0
G G G
~ G 0
D G G

0
0
G
0

FIGURE 3: DTMF Dialing Matrix

DETECTION FREQUENCY

Low Group fo

High Group fo

= 697 Hz

Column 0

= 1209 Hz

Row 1 = 770 Hz

Column 1

= 1336 Hz

Row 2 = 852 Hz

Column 2

= 1477 Hz

Column 3

= 1633 Hz

Row 0

Row 3

= 941

Hz

5-12

SSI 75T202/203
5V Low-Power
DTMF Receiver
ABSOLUTE MAXIMUM RATINGS
(Operation above absolute maximum ratings may damage the device. All SSI 7ST202/203 unused inputs must
be connected to Vp or GND, as appropriate.)
PARAMETER

RATING

DC Supply Voltage - Vp

+7V

Operating Temperature

-40°C to +8S o C Ambient

Storage Temperature

-65°C to + 150°C
- --_.-

Power Dissipation (25°C)

6SmW

Input Voltage (All inputs except ANALOG IN)

(Vp + .SV) to -.SV

ANALOG IN Voltage

(Vp + .SV) to (Vp - 10V)

DC Current into any Input

±1.0mA

Lead Temperature - Soldering, 10 sec.

300°C

--

--~

--

--

--

ELECTRICAL CHARACTERISTICS
(-40°C ~ TA ~ +8S o C, Vp = SV ± 10%)
PARAMETER

CONDITIONS

Frequency Detect Bandwidth
Amplitude for Detection
Twist Tolerance

each tone

Twist

High Tone
Low Tone

MIN

TYP

MAX

UNITS

±(1.S+2Hz)

±2.3

±3.S

%offo

-32

-2

dBm ref.
to 600n

-10

+10

dB

0.8

Vrms

OdB

dB*

~----

60-Hz Tolerance

_... _----

Dial Tone Tolerance

"precise" dial tone

Talk Off

MITEL tape #CM 7290

Digital Outputs

"0" level, 400flA load

0

0.5

V

(except XOUT)

"1" level, 200llA load

VP-O.S

VP

V

Digital Inputs

"0" level

0

0.3Vp

V

"1" level

0.7Vp

VP

V

10

mV p-p

16

mA

-12

dB*

------- -

2

_ _ _ _ _ 0_ _ _ _ _ . _ - -

--

hits

r----

---------

Power Supply Noise

wide band

._-

10

Supply Current

TA = 25°C

Noise Tolerance

M ITEL tape #CM 7290

Input Impedance

Vp~VIN~Vp-10

------- - - - -1 - - - - - - -

100kQI11SpF
------

* dB referenced to lowest amplitude tone

5-13

I

SSI 75T202/203
5V Low-Power
DTMF Receiver
SSI 75T202/203 TIMING

PARAMETER

CONDITIONS

tON

Tone Time

MIN

NOM

MAX

UNITS

for detection

40

-

-

ms

for rejection

-

-

20

ms

- - ------

tOFF

Pause Time

for detection

40

-

ms
-

-

-

for rejection

20

ms

to

Detect Time

25

-

46

ms

tR

Release Time

35

-

50

ms

tsu

Data Setup Time

7

-

-

Ils

tH

Data Hold Time

4.2

-

5.0

ms

c-------

tCl

-

DV Clear Time

160

250

ns

------

tpw

CLRDV Pulse Width

tED

ED Detect Time

200

-

7

-

-

ns

22

ms

f--

tER

ED Release Time

2

-

18

ms

Output Enable Time

C L = 50pF, RL

= 1kQ

-

-

200

ns

Output Disable Time

C L = 35pF, RL

= 500n

-

-

200

ns

---

Output Rise Time

CL = 50pF

-

-

200

ns

Output Fall Time

CL = 50pF

-

160

200

ns

5-14

SSI 75T202/203
5V Low-Power
DTMF Receiver
SSI 75T202/203 TIMING (Continued)

I-- ton

Analog
Input

-I-

tott---l
Pause

D1, D2,
D4,D8

~~

DV

I

CLRDV
tED

~

liER

ED

FIGURE 4: Timing Diagram

5-15

SSI 75T202/203
5V Low-Power
DTMF Receiver
PACKAGE PIN DESIGNATIONS
(TOP VIEW)

01

02

01

02

HEX/828

04

HEX/B28

04

08

EN

EN

OV

N/G

ATB

ED

XIN

N/G

N/G
11

ANALOG IN

OV

Vp

Vp

XEN

08
GlRDV

IN1633

GlRDV

IN1633

6

ATB
XIN
XOUT

XEN

XOUT

ANALOG IN

GNO

GNO

18· Pin DIP
SSI75T203

18· Pin DIP
SSI75T202

CAUTION: Use handling procedures necessary
for a static sensitive component.

ORDERING INFORMATION
ORDER NO.

PART DESCRIPTION

PKG.MARK

SSI75T202
18-pin Plastic DIP

75T202-IP

75T202-IP

SSI75T203
18-pin Plastic DIP

75T203-IP

75T203-IP

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
ofthird parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914

1091 - rev.

5-16

©1989 Silicon Systems, Inc.

551751204
5V Low-Power
Subscriber
DTMF Receiver
October 1991

DESCRIPTION

FEATURES

The SSI 75T204 is a complete Dual-Tone Multifrequency (DTMF) receiver that detects 16 standard
digits. No front-end pre-filtering is needed. The only
external components required are an inexpensive
3.58-MHz television "colorburst" crystal for frequency
reference and a bias resistor. An Alternate Time Base
(ATB) is provided to permit operation of up to 10 SSI
75T204's from a single crystal. The SSI 75T204
employs state-of-the-art "switched-capacitor" filter
technology, resulting in approximately 40 poles of
filtering, and digital circuitry on the same CMOS chip.
The analog input signal is pre-processed by 60-Hz
reject and band split filters and then zero-cross detected to provide AGC. Eight bandpass filters detect
the individual tones. Digital processing is used to

•

Intended for applications with less requirements
than the SSI 75T202

•

14-pin plastic DIP or 16-pin SO package for high
system density

•

NO front-end band-splitting filters required

•

Single low-tolerance 5-volt supply

•

Detects all 16 standard DTMF digits.

•

Uses an inexpensive 3.579545-MHz crystal

•

Excellent speech immunity

•

Output in 4-bit hexadecimal code

•

Three-state outputs for microprocessor interface

(Continued)

BLOCK DIAGRAM

I
TIMING
CIRCUITRY

L---------------Dov
DATA STROBE

01

1Mz

02

04

08

EN

vp

1091 rev.

GNO

5-17

CAUTION: Use handling procedures necessary
lor a static sensitive component.

551 75T204
5V Low-Power
Subscriber DTMF Receiver
DESCRIPTION (Continued)

DV

measure the tone and pause durations and to provide
output timing and decoding. The outputs interface
directly to standard CMOS circuitry and are three-state
enabled to facilitate bus-oriented architectures.

DV signals a detection by going high after a valid tone
pair is sensed and decoded at the output pins D1, D2,
D4, and D8: DV remains high until a valid pause
occurs.

N/C PINS
ANALOG IN
These pins have no internal connection and may be left
floating.

This pin accepts the analog input. It is internally biased
so that the input signal may be AC coupled. The input
may be DC coupled as long as it does not exceed the
positive supply. Proper input coupling is illustrated in
Figure 1.

Output Code

The SSI 75T204 is designed to accept sinusoidal input
wave forms but will operate satisfactorily with any input
that has the correct fundamental frequency with harmonics less then -20 dB below the fundamental.

Digit

08

04

1

0

0

02

01

0

1

1

0

1

1

0

0

0

1

--~-

CRYSTAL OSCILLATOR

2

0

0

3

0

0
--

4

The SSI 75T204 contains an onboard inverter with
sufficient gain to provide oscill~tion when connected to
a low-cost television "colorburst" crystal. The crystal
oscillator is enabled by tying XEN high. The crystal is
connected between XIN and XOUT. A 1 Mz 10%
resistor is also connected between these pins. In this
mode, ATB is a clock frequency output. Other SSI
75T204's (or 75T202's) may use the same frequency
reference by tying their ATB pins to the ATB of a crystal
connected device. XIN and XEN of the auxiliary
devices must then be tied high and low respectively.
Ten devices may run off a single crystal-connected SSI
75T204 (or 75T202) as shown in Figure 2.

0

1
-----

OUTPUTS 01, 02, 04, 08 and EN
Outputs D1, D2, D4, D8 are CMOS push-pull when
enabled (EN high) and open circuited (high impedance) when disabled by pulling EN low. These digital
outputs provide the hexadecimal code corresponding
to the detected digit. The digital outputs become valid
after a tone pair has been detected (DV is high) and
they are then cleared when a valid pause is timed. The
hexadecimal codes are described in Table 1.

5

0

1

6

1

1

a

7

a
a

1

1

1

8

1
1

a
a

a

9

a
a

0

1

0

1

a

*

1

0

1

1

#

1

1

a

A

1

1

a
a

B

1

1

1

a

C

1

1

1

1

D

a

a

a

a

---

TABLE 1: Output Codes

5-18

1

1

SSI75T204
5V Low-Power
Subscriber DTMF Receiver

Vp

Vp

VIN> VP

VIN < VP

a::

0.01 ~F

>--%B
Analog In

I
I

>1 t----VP

I
I
I
I

O.01I1F

XIN Connected to Vp

I

ATB

SSI75T20XX

XEN

Up to 10 Devices

GND

FIGURE 2: Crystal Connections

FIGURE 1: Input Coupling

5-26

SSI 75T2089/2090/2091
DTMF Transceivers

RECEIVER OUTPUTS AND THE DE PIN

GENERATOR

Outputs ~O, 01, 02, 03 are CMOS push-pull when
enabled (DE low) and open-circuited (high impedance)
when disabled (DE high). These digital outputs provide
the hexadecimal code corresponding to the detected
digit. Figure 3 shows that code.

The OTMF generator responds to a hexadecimal code
input with a valid tone pair. Pins 04-07 are the data
inputs for the generator. A high to low transition on
LATCH causes the hexadecimal code to be latched
internally and generation of the appropriate OTM Ftone
pairto begin. The OTM F output is disabled by a high on
RESET and will not resume until new data is latched in.

The digital outputs become valid and OV signals a
detection after a valid tone pair has been sensed. The
outputs and OV are cleared when a valid pause has
been timed.

Digit In
Out
1
2
3
4
5
6
7
8
9
0
*

#
A

B
C
0

07
03
0
0
0
0
0
0
0
1

1
1
1
1
1
1
1
0

Hexadecimal Code
06
05
02
01
0
0
1
0
1
0
1
0
1
0

1
1
0
0
0
0
1
1
1
1
0

1
1
0
0
1
1
0
0
1
1
0

04
DO

1
0
1
0
1
-0
1
0
1
0
1
0
1
0
1
0

DIGITAL INPUTS
The 04, 05, 06, 07, LATCH, RESET inputs to the
OTMF generator may be interfaced to open-collector
TTL with a pull-up resistor or standard CMOS. These
inputs follow the same hexadecimal code format as the
OTMF receiver output. Figure 4 shows the code for
each digit. The dialing matrix and detection frequency
table below list the frequencies of the digits.

ColO
Row 0

Row1

Row 2

Row 3

Col 1

Col 2

Col 3

G ~ G 0
G G G 0
D ~ G 0
D G G 0

NOTE: Column 3 is for special applications
and is not normally used in telephone dialing.

FIGURE 4: DTMF Dialing Matrix

DETECTION FREQUENCY

FIGURE 3

Low Group fo

High Group fo

ED OUTPUT (75T2091 only)

Row 0

= 697Hz

Column 0

The ED output goes high as soon as the SSI 75T2091
begins to detect a OTMF tone pair and falls when the
SSI75T2091 begins to detect a pause. The 01,02,04,
and 08 outputs are guaranteed to be valid when OV is
high, but are not necessarily valid when ED is high.

Row 1 = 770Hz

Column 1

Row 2
Row 3

5-27

= 852Hz
= 941Hz

= 1209Hz
= 1336Hz
Column 2 = 1477Hz
Column 3 = 1633Hz

I

551 75T2089/2090/2091
DTMF Transceivers

DTMF OUT
LIN INPUT (75T2090/2091)

The output amplitude characteristics listed in the
specifications are given for a supply voltage of 5.0V.
However, the output level is directly proportional to the
supply, so variations in it will affect the DTM F output. A
recommended line interface for this output is shown in
Figure 5.

This analog input accepts the call progress signal and
should be used in the same manner as the receiver
input DIN.

CALL PROGRESS DETECTION (75T2090/2091)
~(f{ f--_ _---.,1 :1

The 75T2090/2091 have a Call Progress Detector that
consists of a bandpass filter and an energy detector for
turning the on/off cadences into a microprocessor
compatible signal.

c

TIP

RING

100n

DET OUTPUT (75T2090/2091)
The output is TTL compatible and will be of a frequency
corresponding to the various candences of Call Progress signals such as: on 0.5 sec/off 0.5 sec for a busy
tone, on 0.25 sec/off 0.25 sec for a reordertone and on
0.8-1.2 sec/off 2.7-3.3 sec for an audible ring tone.

FIGURE 5: DTMF Output

ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operating above absolute maximum ratings may damage the device.
PARAM~TER

RATING

DC Supply Voltage (Vp - Vn)
Voltage at any Pin (Vn

+7V

= 0)

-0.3 to Vp + 0.3V

DIN Voltage

Vp + 0.5 to Vp - 10V

Current through any Protection Device

=20mA

Operating Temperature Range

-40 to + 85°C

Storage Temperature

-65 to 150°C

RECOMMENDED OPERATING CONDITIONS
PARAMETER

CONDITIONS

MIN

MAX

NOM

4.5

Supply Voltage

5.5

V

10

mVp-p

-40

+85

°C

-(}'01

+0.01

%

1.2

MQ

Power Supply Noise (wide band)
Ambient Temperature
Crystal Frequency
(F Nominal = 3.579545MHz)
Crystal Shunt Resistor

0.8

DTMF OUT Load Resistance

100
5-28

UNIT

--

-

Q

551 75T2089/2090/2091
DTMF Transceivers

DIGITAL AND DC REQUIREMENTS
The following electrical specifications apply to the digital input and output signals over the recommended
operating range unless otherwise noted. The specifications do not apply to the following pins: LIN, DIN, XIN,
XOUT, and DTMF OUT. Positive current is defined as entering the circuit. Vn = 0 unless otherwise stated.
PARAMETER

CONDITIONS

MIN

Supply Current*

NOM

MAX

15

30

UNIT
rnA
~

Power Dissipation
Input Voltage High

225

mW

0.3Vp

V

10

IJA

0.7Vp

V

Input Voltage Low
Input Current High
Input Current Low

-10

= -0.2mA

Output Voltage High

loh

Output Voltage Low

101 = +O.4mA

IJA

Vp-0.5

V
-~~-----

~

Vn+0.5

V

* with DTMF output disabled
DTMF RECEIVER: Electrical Characteristics
PARAMETER

CONDITIONS

Frequency Detect Bandwidth
Amplitude for Detection

MIN

NOM

MAX

UNIT

=(1.S+2Hz)

=2.3

=3.5

%Fo

-2

dBm/tone

-32

Each Tone

-10

Twist Tolerance

----------

60Hz Tolerance
--_ ..

Dial Tone Tolerance

Precise Dial Tone

Speech Immunity

MITEL Tape #CM7290

Noise Tolerance

MITEL Tape #CM7290

-

-

+10

dB

0.8

Vrms

0

dB*

-12

dB*

-----

2

hits

-~

100

Input Impedance

- -

kQ
~~~--~~- ~-~.~~--'-------~

* Referenced to lowest amplitude tone
DTMF RECEIVER: Timing Characteristics
PARAMETER
TON

Tone Time for Detect

TON

Tone Time for No Detect

MIN

CONDITIONS

NOM

40

Pause Time for Redetection

TOFF

Pause Time for Bridging
Detect Time

TR1

Release Time

20

40

.-

----

5-29

ms
ms

20

ms

25

46

ms

35

50

ms

- - - ------_ ...

------

TD1

----

UNIT
ms

- - - ------------ -- - -

TOFF

MAX

I

SSI 75T2089/2090/2091
DTMF Transceivers

DTMF RECEIVER: Timing Characteristics
PARAMETER

(Continued)

CONDITIONS

MIN

TSU1

Data Set Up Time

THD1

Data Hold Time

TED

ED Detect Time

75T2091 only

7

BER

ED Release Time

75T2091 only

2

NOM

7

MAX

UNIT

5.0

ms

22

ms

18

ms

j.Js

--_.

4.2
--.

Output Enable Time

200

ns

200

ns

-1.0

+1.0

%Fo

-9.2

-7.2

dBm

-4.6

dBm

-20

dB

2.5

!-IS
ns

-_ ..

Output Disable Time
DTMF GENERATOR: Electrical Characteristics
Frequency Accuracy
Output Amplitude

R1 = 1Don to Vn, Vp - Vn = 5.0V

Low Band

-6.6

High Band
Output Distortion

---- --_.-

DC to 50 kHz

DTMF GENERATOR: Timing Characteristics
TSTART Start-Up Time
TSU2

Data Set-Up Time

THD2

Data Hold Time

50

ns

TRP

RESET Pulse Width

100

ns

TPW

LATCH Pulse Width

100

ns

100

CALL PROGRESS DETECTOR: Electrical Characteristics (75T2090/2091 only)
Amplitude for Detection
Amplitude for No Detection

Detect Output

305 Hz-640 Hz

-40

0

dBm

305 Hz-640 Hz

-50

dBm

1>2200 Hz, <160 Hz

-25

dBm

0.5

V

Logic 0
----

Max. Voltage

Input Impedance

500 Hz

V

4.5

Logic 1
"UN" Input

VDD-10
100

5-30

VDD
_ _._...

V
kQ

551 75T2089/2090/2091
DTMF Transceivers

CALL PROGRESS DETECTOR: Electrical Characteristics
PARAMETER

(Continued)

CONDITIONS

MIN

NOM

40

MAX

UNIT

TON

Signal Time for Detect

TON

Signal Time for No Detect

TOFF

Interval Time for Detect

TOFF

Interval Time for No Detect

TD2

Detect Time

40

ms

TR2

Release Time

40

ms

TON

I

..

------

--

ms
ms

---~--

c-------

20
ms
------'-----

I

TOFF

I

_-

---

I

~
OV

10

--_ ... __ .- ---

40

~~:::'::::::'ImM
.... = =
...,
''_ _ _-------'i!!! toneburst2 t!!'-___

DIN

ms

-- _._--

L

1 - 1_ - - - - '

DIN

~::

I

tonebursl1

:l

TOFF

I

!

lonebursl2

:::1

DV

I

00,01,0203

~IED

*

~

~I-

L

1 . . . . - 1_ - - '

* 75T2091

00.01,02,03

only

FIGURE 6: DTMF Decoder

FIGURE 7: Call Progress Detector
(75T2090/2091 only)

TH02
04, 05, 06, 07

-.----------L-l-----i
TSU2

j/

~'-r-I- - -

L-----TP-----,W

TPW

I-------r~--- (SEE NOTE)

-------I

RESET

I
------------~<=---------~>~----------------I~
TSTARTI

OTMFOUT

1 - -TRP
---1

NOTE: THE INDICATED TIME MAY BE AS SMALL AS 0 SEC., MEANING THAT THE LATCH AND RESET LINES MAY BE TIED TOGETHER.

FIGURE 8: DTMF Generator

5-31

551·75T2089/2090/2091
DTMF Transceivers

PACKAGE PIN DESIGNATIONS
(Top View)
0

a
03

OV

02

03

02

07

01

OV

OE

01

06

00

07

VP

00

05

N/C

06

OE

04

OE

05

VP

LATCH

XEN

RST

OIN

OET-

XOUT

LIN-

XIN

DTMFOUT

ATB

VN
- 75T2090 only

75T2089/2090
22·Pin DIP

VP

04

ED

LATCH

4

0 aC\I aM
3

2

>
a

a

a

28

27

26

r-...

to

0

25

05

24

04

EO

23

LATCH

N/C

22

N/C

N/C

21

N/C

XEN

RST

XEN

20

RST

N/C

NlC

N/C

19

OET

N/C

N/C

DIN

DET

XOUT

LIN

XIN

DTMFOUT

ATB

VN

75T2091
28·Pin DIP

12

13

14

15

16

Z

r-

z

co
r<{

z r- z
:; ::> :::i

0

::>

0

X

17

18

0

LL
~
f-

X

a

75T2091
28·Pin PLCC
CAUTION: Use handling procedures necessary
for a static sensitive component.

ORDERING INFORMATION
ORDER NO.

PART DESCRIPTION

PKG.MARK

SSI75T2089
22-Pin Plastic DIP

75T2089 - IP

75T2089 - IP

75T2090 -IP

75T2090 - IP

28-Pin Plastic DIP

75T2091 - IP

75T2091 - IP

28-Pin PLCC

75T2091 - IH

75T2091 -IH

SSI75T2090
22-Pin DIP
SSI75T2091

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914

1191

5-32

©1991 Silicon Systems, Inc.

SSI75T980
Call Progress
Tone Detector

June 1994

DESCRIPTION

FEATURES
Detects tones throughout the telephone progress
supervision band (315 to 640 Hz)

The 551 75T980 Call Progress Tone Detector circuit
allows automatic equipment to monitor tones in dial
telephone systems that relate to the routing of calls.
5uch tones commonly include dial tones, circuits-busy
tones, station-busy tones, audible ringing tones and
others. By sensing signals in the range of 315 to
640 Hz, the SSI 75T980 does not require the use of
precision tones to function. This means that tones
which vary with location or call destination can be
detected regardless of their exact frequency.

Sensitivity to -38 dBm
Dynamic range over 36 dB
40 ms minimum detect (50 ms to output)
Single supply CMOS (lOW power)
Supply range 4.5 to 5.5 VDC
Uses 3.58 MHz crystal or external clock
8-pin DIP and 16-pin SO packages
Second source of Teltone M-980

The low powerCM05 switched capacitorfilters used in
the 5S1 75T980 derive their accuracy from a 3.58 MHz
clock, which in turn may be derived from other devices
in the system being designed. The S51 75T980 is
available in a plastic 8-pin DIP and 16-pin 50
packages.

------1
BLOCK DIAGRAM

PIN DIAGRAM

XIN

8

VDD

XOUT

2

7

VREF

ENABLE

3

6

VSS

DETECT

4

5

SIGIN

8-Pin DIP

XIN

XOUT

ENABLE

CAUTION: Use handling procedures necessary
for a static sensitive component.

0694 - rev.

5-33

551 75T980
Call Progress
Tone Detector
PIN DESCRIPTION
NAME

TYPE

SIGIN

I

Accepts analog input signal. See "Electrical Characteristics" for voltage levels,
and "Timing Characteristics" for timing.

0

Call progress detect output. Goes to logic "1" when signal in 315-640 Hz band
is sensed. See "Timing Characteristics."

ENABLE

I

Application of logic "1" on this pin enables the output; logic "0" disables output.

VREF

0

Supplies voltage at half Voo for voltage reference of on-chip op amps.

XIN, XOUT

I

Crystal connections to on-chip oscillator circuit.

Voo

-

Positive power supply connection

DETECT

Vss

DESCRIPTION

Negative power supply connection

OdBm-+==

SIGNAL
LEVEL

MUST DETECT
REGION

-38dBm

NOT
DETECT
REGION

-50dBm

190Hz

315Hz

640Hz

1025Hz

FREQUENCY

FIGURE 1: Detect and Reject Regions

5-34

SSI75T980
Call Progress
Tone Detector
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
(Operation above absolute maximum ratings may permanently damage the device.)
RATING

PARAMETER
DC Supply Voltage
Input Voltage

VOD-VSS
All inputs except SIGNAL IN

16V
(Voo + 0.5V) to (Vss - 0.5V)

SIGNAL IN Voltage

(Voo + 0.5V) to (Vss - 22V)

Storage Temperature

-65°C to 1S0°C

Operating Temperature

-30°C to 70°C

--

Lead Temperature

Soldering, 5 sec.

260°C

ELECTRICAL CHARACTERISTICS
(TA = 2SoC, Voo - Vss = 4.5V to S.SV, dBm is referenced to 6000.)
PARAMETER

CONDITIONS

MIN

NOM

MAX

Supply Current

Voo- Vss = 5V

-

4

10

UNITS
mA

Signal level for detection

31S-640 Hz

-38

0

dBm

Signal level for rejection

315-640 Hz

-

-SO

dBm

0

dBm

f
DETECT output (lout = +1mA)

ENABLE, XIN input (lin=10JlA)

>1025 Hz,

f

<190 Hz

-

0.5

V

Logic 1

4.5

-

-

V

Logic 0

Vss

-

Vss+0.2

V

Logic 1

VOD-0.2

-

Voo

V

40

-

60

%
pF

XIN, XOUT loading
Deviation
Resistance
SIGIN input

-

Logic 0

XIN duty cycle

VREF output

-

Maximum voltage
Impedance (500 Hz)

5-35

-

-

10

-2

(VDD+Vss)/~

+2

%

3.25

-

6.75

kn

VOD-10

-

Voo

V

80

-

-

kQ

I

SS175T980

Call Progress
Tone Detector
ELECTRICAL SPECIFICATIONS (continued)
TIMING CHARACTERISTICS
(TA = 25°C, VDD - Vss =4.SV TO S.SV)
PARAMETER

CONDITIONS

tMD Signal duration for detection

315-640 Hz

Interval duration for detection

MIN

NOM

40

MAX

UNITS

-

ms

f------ - - -

Signal dropping from
-38 dBm to -50 dBm (t2 )

-

40

ms

90

ms

20

ms

--------

Signal dropping from

odBm to -50 dBm (t

1

)

Tone dropout bridging

ts

If- IMD -tj

SIGIN

~ : ~:

------ll

-

~ IS

If-

f- - - - - -ilL..----.....JI----D-D~

-----------LCtF-------..:
FIGURE 2: Basic Timing

5-36

551 75T980
Call Progress
Tone Detector

SIGIN

-q
I

DETECT

~

Lu
t1

--tl

I
--.

t2

~

*-

FIGURE 3: Effect of Amplitude on Timing

881 75T980

....----_.1 SIGIN

881 75T980

DETECT

SIGIN

XIN

DETECT
XIN

PHONE LINE
AUDIO

3.58 MHz

D

3.58 MHz

D

PHONE ,----'--....,
LINE

551 75T202/3/4

DAA

DV

DIALER IC

ANALOG
IN

STROBE
DATA t - - -. .

DTMF RECEIVER

DIALER

FIGURE 4: Applications Circuits

5-37

I

SSI·75T980
Call Progress
Tone Detector
PACKAGE PIN DESIGNATIONS
(Top View)

N/C

XIN

8

VDD

XOUT

2

7

VREF

ENABLE

3

6

VSS

DETECT

4

5

SIGIN

8-Pin DIP

16

N/C

XIN

2

15

VDD

N/C

3

14

VREF

XOUT

4

13

N/C

EN

5

12

VSS

N/C

6

11

N/C

DET

7

10

SIGIN

N/C

8

9

N/C

16-Lead SO

CAUTION: Use handling procedures necessary
for a static sensitive component.

ORDERING INFORMATION
ORDER NO.

PART DESCRIPTION

PKG.MARK

SSI75T980 8-pin Plastic DIP

75T980-CP

75T980-CP

SSI 75T980 16-pin SO Package

75T980-CL

75T980C

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914

©1989 Silicon Systems, Inc.

5-38

0694 - rev.

551 78A207
MFR1 Receiver

July 1990

DESCRIPTION

FEATURES

The SSI78A207 is a single-chip, Multi-Frequency (M F)
receiver that can detect all 15 tone-pairs, including ST
and KP framing tones. This receiver is intended for use
in equal access applications and thus meets both Bell
and CCITT R1 central office register signalling specifications.

•

Meets Bell and CCITT R1 specifications

•

20-pin plastic DIP

•

Single low-tolerance 5V supply
Detects all 15 tone-pairs including ST and KP

The SSI 78A207 employs state-of-the-art switched
capacitor filters in CMOS technology. The receiver
consists of a bank of channel-separation bandpass
filters followed by zero-crossing detectors and frequency-measurement bandpass filters, an amplitude
check circuit, a timer and decoder circuit, and a clock
generator. The device does not attempt to identify
strings of digits by the KP (key pulse) and ST (stop)
tone pairs.

•

Long KP capability

•

Built-in amplitude discrimination

•

Excellent noise tolerance

•

Outputs in either "n of 6" or hexadecimal code

•

Three-state outputs, CMOS-compatible
and TTL-compatible

No anti-alias filtering is needed if the input signal is
band-limited to 26 KHz. The only external component
required is an inexpensive television "color burst" 3.58
MHz crystal.

I

The outputs interface directly with standard CMOS or
TTL circuitry and are three-state enabled to facilitate
bus-oriented architecture.

BLOCK DIAGRAM

VDD

0790 - rev.

AGN

DGND

5-39

SSI78A207
MFR1 Receiver

FUNCTIONAL DESCRIPTION

EN
The three-state enable control: When low, the 00-05
outputs are in the low impedance state. In an interrupt
oriented microprocessor interface, EN and CSTR will
often be tied together to provide automatic reset of the
strobes when the output data is enabled.

VIN
This pin accepts the analog input. It is internally biased
to half the supply and is capacitively coupled to the
channel separation filters. The input may be DC
coupled as long as it does not exceed VOO or drop
below GND. Equivalent input circuit is shown below in
Figure 1.

STROBE PINS· DV AND DE
Valid data is indicated on the OV strobe pin, and data
errors are indicated on the DE strobe pin. Whenever a
valid 2 of 6 code has been detected, the OV strobe
rises. It remains high until the code goes away, or the
CSTR line is activated. When an invalid code is
detected, e.g., 1 of 6,3 of 6, etc., the DE strobe remains
high until all errors stop, a valid tone pair is detected, or
the CSTR line is activated. Once cleared by CSTR, DE
will not reactivate until a new invalid condition is detected. The DE and OV strobes will never be high
simultaneously.

CRYSTAL OSCILLATOR
The SSI 78A207 contains an on-board inverter with
sufficient gain to provide oscillation when connected to
a low cost television "color-burst" crystal. The on-chip
clock signals are generated from the oscillator. The
crystal is connected between X1 and X2.
XOUT is a 3.58 MHz square wave capable of driving
other circuits as long as the capacitive load does not
exceed 50 pF. Other devices driven by XOUT should
use X1 as the input pin, while X2 should be left floating.

DATA OUTPUT MODES
The digital output format may be either "n of 6" or 4-bit
hexadecimal.

LKP
The KP timer control: When high, the KP detect time
is increased. When low, the KPdetecttime is the same
as for other tones.

For"hex" mode, the HEX pin is pulled high. Outputs 00
to 03 provide a 4-bit code identifying one of the 15 valid
tone combinations according to Table1.

QUAL
The outputs will be cleared to zero when no valid tone
pair is present.

Enables tone pair qualification. When low, the threshold detector outputs are passed to the data outputs
(00-05) without validation in the format selected by the
HEX pin. These outputs, plus strobes OV and DE, are
updated once per 2.3 ms frame. Note that the strobes
will cycle once per frame (even when the inputs are
stable.) As always, data changes only when both
strobes are low.

For the "n of 6" mode, the HEX pin is pulled low, and
each output represents one of the six frequencies as
shown below:
FREQUENCY OUTPUT PIN
700
00
01
900
1100
02
1300
03
1500
04
1700
05

CSTR
This input clears both the OV and DE strobes, and is
active low. After CSTR is released, the strobes will
remain low until a new detect (or error) occurs. The
output data is latched by CSTR and will not change
while CSTR is low, even in the event that a new detect
is qualified internally. (Note that improper use of CSTR
may result in missed detects.)

The outputs will be cleared to zero when no valid tone
is present.

5-40

SSI78A207
MFR1 Receiver

TABLE 1:
Channels

Tone Pair Freq.

Name

03

02

0-1

700, 900

1

0

0

0-2

700,1100

2

0

1-2

900,1100

0

0-3
1-3

700, 1300
900, 1300

3
4

a

5

0

2-3

1100,1300

6

0

0-4
1-4
2-4
3-4

700, 1500
900, 1500
1100,1500
1300, 1500

7

a

8

9
0

1
1
1

01
------ --

a
a

0
1

----.--.~-

00
----....

1
~-

a

-~~-~----.-

1
1

--.
-----

--~-

--

--_.

-- ---

a
a

0
1

--~

a

1

1
1

a
a
a
a

1

1

1
-_.-._-f------

a
--~

1
0
1

0
1
0
- - " - - - - - -f - - - - - 1
1

2-5

1100,1700

KP

1

4-5
1-5

1500,1700
900, 1700

ST
5T1

1
1

5T2
5T3

1
1

1 ----1-------- -

a

0

-~

1300, 1700
700,1700
any other signal
NOTE: In the hex mode, 04 = DE and 05
3-5
0-5

=

1
- - f----------.1 --._-

OV.

VDD

VIN

FIGURE 1: VIN Equivalent Input Circuit

5-41

a

0
---_._---

----

1
1

0
1

a

a

~-~-~-.---

----

0
1

- - - - - - -r - - - - - - -

-

-

--.~.-.--~~.---

I

SSI78A207
MFR1 Receiver

TIMING SPECIFICATIONS

Ton

PARAMETER

CONDITIONS

Tone Time, KP
(LKP = VDD)

detect

MIN

NOM

MAX

55

UNIT
ms

-~---

reject

Ton
Ton

Tone Time, KP
(LKP = DGND)

Ton
Ton

detect

30
30

ms
-

reject
Tone Time, All Others

detect

ms

--~-.-

10

- .._-

30

ms
ms

-------

Ton
Tpse

reject
Pause Time

Tbr

detect

- - --

10

---_._----

----~

20

reject

ms
-

Tsu

Data Setup Time

6

Th

Data Hold Time

7

ms

1------

10
---~----

-.---~--

-------..

-

----

__I-l_S__
I-lS

-_ ...

Tskew Tone Skew Tolerance

ms

4

ms

."._-

Tstr

Tsep

Tr

Minimum Strobe Pulse Width

--

QUAL High

20

QUAL Low

2

Minimum Strobe Separation
20

QUAL Low

2

Rise Time DV, DE, DO-OS
10-90%

CL

Tf

Fall Time DV, DE, DO-OS
10-90%

CL

Tw

CSTR Width

Ten
Tdis

Data Disable Time

Trst

Strobe Reset Time

ms

-----

----- -------- - - - - -

QUAL High

Data Enable Time

ms

.--------.

-------

ms
---~.-~

ms

----".

= 20 pF
----

100

ns

100

ns

-

= 20 pF

ns

50
CL

= 20 pF

100

------- -

CL

= 20 pF

5-42

-~---

ns
~-~-

100

ns

100

ns

SSI78A207
MFR1 Receiver

114
...- - - - - -

Tpse

----~

TONE'

TONE 2

i-T

,-s_kew
_ _ _ _ _ _ _---,

DO-D5

TSU~

==

Tstr--~~ ~

Th

,----------,
DV (QUAL -') - - - - - - - - '

DV (QUAL - 0) - - - - - '

Tstr-----1

~

-.j

~Tsep

DE ( Q U A L - O ) - - - - - - - - - - - - - - - - - - - - - - - - + - J

FIGURE 2: SSI 78A207 Timing Diagram

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
(Operating above absolute maximum ratings may damage the device.)
PARAMETER

RATING

DC Supply Voltage V DD

+ 7V

Operating Temperature

o to 70 (AmbienWC

Storage Temperature

65 to 150°C

Power Dissipation (25°C)
(Derate above TA=25°C @ 6.25 mW/°C)

650mW

Input Voltage

(VDD + 0.3V) to-9.3V

DC Current into any input

±10mA

Lead Temperature (Soldering, 10 sec.)

300°C

5-43

I

SSI·78A207
MFR1 Receiver

DC ELECTRICAL CHARACTERISTICS (O°C $ TA ~ 70°C, VDD = 5V ± 10%)
PARAMETER
Idd

Supply Current

Vol

Output Logic 0

CONDITIONS

MIN

NOM

~

MAX

UNIT

20

rnA

.. -

.--

101 = 8 rnA

-

101 = 1 rnA
Voh

Vih

0.5
0.4

.. -

-

Output Logic 1

.•_...•-_._---

-.---- •..

loh = -4 rnA

VDD-1.0

loh=-1 rnA

VDD-O.5

Input Logic 1

V

--

-.~-

- ---

~--.-

--.~-

V

f--------

1---------

V

... ---

V

--

V

2.0
.--e---..

Voh

Input logic 0

Zin

Analog Input Impedance
(Input between VDD and AGND)

100K
30pF

lin

Digital Input Current
(Input between VDD and DGND)

-50

._--_ ...

Q

50

~

MAX

UNIT

AC CHARACTERISTICS (O°C ~ TA ~ 70°, VDD = 5V ± 10%)
PARAMETER

CONDITIONS

F

Frequency for Detect
Tolerance

A

Amplitude for Detect

MIN

NOM

Hz

±(0.015
xFo + 5)
each tone

-25

0

dBm

0.123

2.191

Vpp

-35

dB

0.039

Vpp

+6

dB

---_...

AN

Amplitude for no Detect

TW

Twist Tolerance

TW= high tone
low tone

-6

T3

Third MF Tone Reject Amp

relative to highest
amplitude tone

-15

dB

N60

60 HZ Tolerance

not more than one error

81

dBrn

in 2500 1a-digit calls

Vpp

0.777
~-

N180 180 HZ Tolerance

1

Nn

Noise Tolerance

NI

Impulse Noise Tolerance 2

same as above

1---

68

dBrn

0.174

Vpp

same as above

-20

dB

same as above

+12

dB

NOTES: 1. C-message weighted. Measured with respect to highest amplitude tone.
2. With noise tape 201 per PUB 56201. Measured with respect to highest amplitude tone.
5-44

- ..

--

V
0.8
_ -1 - - - - - - -

SSI78A207
MFR1 Receiver

CAUTION: Use handling procedures necessary
______________________________________________________________~~~~~fo~ra~s~ta~ti~c~se~n~si~tiv~e~co~m~p~on~e~nt~.~~

PART DESCRIPTION
SSI 78A207 20-Pin Plastic DIP

ORDER NO.

PKG.MARK

78A207-CP

78A207-CP

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914

©1989 Silicon Systems, Inc.

5-45

0890 - rev.

I

Notes:

5-46

Section

6

PCM PRODUCTS

I

6

6-0

SSI78P300
T1/E1 Integrated Short Haul Transceiver
with Receive Jitter Attenuation

December 1993

DESCRIPTION

FEATURES

The SSI78P300 is a fully integrated transceiver for both
North American 1.544 MHz (T1), and European 2.048
MHz (E1/CEPT) applications. Transmit pulse shapes
(DSX-1 or E1/CEPT) are selectable for various line
lengths and cable types.

•

Compatible with most popular PCM framers
including the 2180A and 2181

•

Line driver, data recovery and clock recovery
functions

•

Pin and functionally compatible with Crystal
CS61574

•
•

Minimum receive signal of 500 mV

The SSI 78P300 provides receive jitter attenuation
starting at 3 Hz, and is microprocessor controllable
through a serial interface.
The SSI 78P300 offers a variety of diagnostic features
including transmit and receive monitoring. Clock inputs
may be derived from an on-chip crystal oscillator or
digttal inputs. The SSI 78P300 uses an advanced
double-poly, double-metal CMOS process and requires
only a single 5-volt power supply.

•

Selectable slicer levels (CEPT/DSX-1) Improve
SNR
Programmable transmit equalizer shapes
pulses to meet DSX-1 pulse template from 0 to
655 ft

•

Local and remote loopback functions

•

Transmit Driver Performance Monitor (DPM)
output

•
•
•
•
•

Receive monitor with Loss of Signal (LOS) output
Receiver jitter tolerance 0.4 UI from 40 kHz to
100 kHz
Microprocessor controllable
Receive jitter attenuation starting at 6 Hz
Available in 28 pin DIP or PLCC

BLOCK DIAGRAM
MODE-----------r--~~

HOST R7W
INT EC1
SOi EC2
SDo EC3
RLOOP
SCLK LLOOP
CLKE TAOS

a

CONTROL
' r -_ _ _ _ _ _+- TTIP

TPOS --+---~
TNEG __
~

EQUALIZER

TCLK --+---~

SYNCHRONIZER

+-__

TRING

t4-..-~RTIP

MCLK--+--~

j41-<..-+-- RRING

r==:Jc=l

XTALlN--L-......

XTALOUT--t-----i
RCLK __I----L_r--~

RPOS __t - - - - - i
RNEG - - t - - - - - i

MTIP
MRING

'--------'

LOS - - t - - - - - - - - - I
OPM - - + - - - - - - - - - - - - - - - - - - - '

1293 - rev.

6-1

CAUTION: Use handling procedures necessary
for a slatic sensitive component.

~

SSI78P300
T1/E1 Integrated Short
Haul Transceiver with
Receive Jitter Attenuation
FUNCTIONAL DESCRIPTION

RECEIVER

The SSI 78P300 is a fully integrated PCM transceiver
for both 1.544 MHz (DSX-1) and 2.048 MHz (CEPT)
applications. This transceiver allows transmission of
digital data over existing twisted-pair installations.

The SSI78P300 receives AM I signals from one twistedpair line on each side of a center-grounded transformer. Positive pulses are received at RTIP and
negative pulses are received at RRING. Recovered
data is output at RPOS and RNEG, and the recovered
clock is output at RCLK. Refer to Table 3 and Figure 3
for SSI 78P300 receiver timing.

The SSI78P300 transceiver interfaces with two twistedpair lines (one twisted-pair for transmit, one twistedpair for receive) through standard pulse transformers
and appropriate resistors.

The signal received at RPOS and RNEG is processed
through the peak detector and data slicers. The peak
detector samples the inputs and determines the maximum value of the received signal. A percentage of the
peak value is provided to the data slicers as a threshold
level to ensure optimum signal-to-noise ratio.

TRANSMITTER

Data received for transmission onto the line is clocked
serially into the device at TPOS and TNEG. Input
synchronization is supplied by the transmit clock (TCLK).
The transmitted pulse shape is determined by Equalizer Control signals EC 1 through EC3 as shown in
Table 1. Refer toTable 2 and Figure 1 for master and
transmit clock timing characteristics. Shaped pulses
are applied to the AM I line driver for transmission onto
the line at TTIP and TRING. Equalizer Control signals
may be hardwired in the Hardware mode, or input as
part of the serial data stream (SDI) in the Host mode.

For DSX-1 applications (determined by Equalizer Control inputs EC 1 - EC3 :;:. 000) the threshold is set to 70%
of the peak value. This threshold is maintained above
65% for up to 15 successive zeros over the range of
specified operating conditions. For CEPT applications
(EC inputs = 000) the threshold is set to 50 %.
The receiver is capable of accurately recovering signals with up to -13.6 dB of cable attenuation (from 2.4
V), corresponding to a received signal level of approximately 500 mV (1500 feet of ABAM cable.) Regardless
of received signal level, the peak detectors are held
above aminimum level of .3 Vto provide immunityfrom
impulsive noise;

Pulses can be shaped for either 1.544 or 2.048 MHz
applications. 1.544 MHz pulses for DSX-1 applications
can be programmed to match line lengths from 0 to 655
feet of ABAM cable. The SSI 78P300 also matches
FCC and ECSA specifications for CSU applications.
2.048 MHz pulses can drive coaxial or shielded twistedpair lines using appropriate resistors in line with the
output transformer.

After processing through the data slicers, the received
signal is routed to the data and clock recovery sections,
and to the receive monitor. The receive monitor generates a Loss of Signal (LOS) output upon receipt of 175
consecutive zeros (spaces). The receiver monitor loads
a digital counter at the RCLK frequency. The count is
incremented each time a zero is received, and reset to
zero each time a one (mark) is received. Upon receipt
of 175 consecutive zeros the LOS pin goes high, and
the RCLK output is replaced with the MCLK. If MCLK
is not supplied the RCLK output will be replaced with
the centered crystal clock.

DRIVER PERFORMANCE MONITOR

The transceiver incorporates a Driver Performance
Monitor (DPM) in parallel with the TTIP and TRING at
the output transformer. The DPM output level goes
high upon detection of 63 consecutive zeros. It is reset
when a one is detected on the transmit line, orwhen a
reset command is received.
LINE CODE

The LOS pin will reset as soon as a one (mark) is
detected.Recovered clock Signals are supplied to the
jitter attenuator and the data latch. The recovered data
is passed to the elastic store where it is buffered and
synchronized with the dejittered recovered clock
(RCLK).

The SSI78P300 transmits data as a 50% AM I line code
as shown in Figure 2. Power consumption is reduced
by activating the AM I line driver only to transmit a mark.
The output driver is disabled during transmission of a
space.

6-2

SSI78P300
T1/E1 Integrated Short
Haul Transceiver with
Receive Jitter Attenuation
JITTER ATTENUATION
Jitter attenuation of the SSI 78P300 clock and data
outputs is provided by a Jitter Attenuation Loop (JAL)
and an Elastic Store (ES). An external crystal oscillating at 4 times the bit rate provides clock stabilization.
Refer to Table 4 for crystal specifications. The ES is a
32 x 2-bit register. Recovered data is clocked into the
ES with the recovered clock signal, and clocked out of
the ES with the dejittered clock from the JAL. When the
bit count in the ES is within two bits of overflowing or
underflowing, the ES adjusts the output clock by 1/8 of
a bit period. The ES produces an average delay of 16
bits in the receive path.

The SSI78P300 serial port is addressed by setting bit
A4 in the Address/Command byte, corresponding to
address 16. The SSI 78P300 contains only a single
output data register so no complex chip addressing
scheme is required. The register is accessed by causing the Chip Select (CS) input to make a transition from
high to low. Bit 1 of the serial Address/Command byte
provides Read/Write control when the chip is accessed.
A logic 1 indicates a read operation, and a logic 0
indicates a write operation. Table 5 lists serial data
output bit combinations for each status. Serial data I/O
timing characteristics are shown in Table 6, and Figures 5 and 6.

OPERATING MODES

HARDWARE MODE OPERATION

The SSI78P300 transceiver can be controlled through
hard-wired pins (Hardware mode). This transceiver
can also be commanded to operate in one of several
diagnostic modes.

In Hardware mode the transceiver is accessed and
controlled through individual pins. With the exception
of the INT and CLKE functions, Hardware mode provides all the functions provided in the Host mode. In the
Hardware mode RPOS and RNEG outputs are valid on
the rising edge of RCLK. To operate in Hardware
mode, MODE must be set to O. Equalizer Control
signals (EC1 through EC3) are input on the Interrupt,
Serial Data In and Serial Data Out pins. Diagnostic
control for Remote Loopback (RLOOP), Local Loopback
(LLOOP), and Transmit All Ones (TAOS) modes is
provided through the individual pins used to control
serial interface timing in the Host mode.

The SSI 78P300 can be controlled by a microprocessorthrough a serial interface (Host mode). The mode
of operation is set by the MODE pin logic level.
HOST MODE OPERATION
To allow a host microprocessor to access and control
the SSI 78P300 through the serial interface, MODE is
set to 1. The serial interface (SDI/SDO) uses a 16-bit
word consisting of an 8-bit Command/Address byte
and an 8-bit Data byte. Figure 4 shows the serial
interface data structure and timing.

RESET OPERATION
Upon power up, the transceiver is held static until the
power supply reaches approximately 3V. Upon crossing this threshold, the device begins a 32 ms reset cycle
to calibrate the transmit and receive delay lines and
lock the Phase Lock Loop to the receive line. A reference clock is required to calibrate the delay lines. The
transmitter reference is provided by TCLK. The crystal
oscillator provides the receiver reference in the SSI
78P300.lfthe SSI78P300 crystal oscillator is grounded,
MCLK is used as the receiver reference clock.

The Host mode provides a latched Interrupt output
(INT) which is triggered by a change in the Loss of
Signal (LOS) and/or Driver Performance Monitor (DPM)
bits. The Interrupt is cleared when the interrupt condition no longer exists, and the host processor enables
the respective bit in the serial input data byte. Host
mode also allows control of the serial data and receive
data output timing. The Clock Edge (CLKE) signal
determines when these outputs are valid, relative to
the Serial Clock (SCLK) or RCLK as follows:

CLKE

OUTPUT

CLOCK

VALID EDGE

LOW

RPOS
RNEG
SDO

RCLK
RCLK
SCLK

RISING
RISING
FALLING

HIGH

RPOS
RNEG
SDO

RCLK
RCLK
SCLK

FALLING
FALLING
RISING

The transceiver can also be reset from the Host or
Hardware mode. In Host mode, reset is commanded by
simultaneously writing RLOOP and LLOOP to the
register. In Hardware mode, reset is commanded by
holding RLOOP and LLOOP high simultaneously for
200 ns. Reset is initiated 0 n the falling edge of the reset
request. In either mode, reset clears and sets all
registers to 0 and centers the oscillator, then begins
calibration.

6-3

I

SSI78P300
T1/E1 Integrated Short
Haul Transceiver with
Receive Jitter Attenuation
DIAGNOSTIC MODE OPERATION

In Local Loopback (LLOOP) mode, the receiver circu its
are inhibited. The transmit data and clock inputs (TPOS,
TNEG and TCLK) are looped back onto the receive
data and clock outputs (RPOS, RNEG and RCLK.) The
transmitter circuits are unaffected by the LLOOP command. The TPOS and TNEG inputs (or a stream of 1's
if the TAOS command is active) will be transmitted
normally. When used in this mode with a crystal, the
transceiver can be used as a stand-alone jitter attenuator.

In Transmit All Ones (TAOS) mode the TPOS and
TNEG inputs to the transceiver are ignored. The transceiver transmits a continuous stream of 1's when the
TAOS mode is activated. TAOS can be commanded
simultaneously with Local Loopback, but is inhibited
during Remote loopback.
In Remote Loopback (RLOOP) mode, the transmit
data and clock inputs (TPOS, TNEG and TCLK) are
ignored. The RPOS and RNEG outputs are looped
back through the transmit circuits and output on niP
and TRING at the RCLK frequency. Receiver circuits
are unaffected by the RLOOP command and continue
to output the RPOS, RNEG and RCLK signals received
from the twisted-pair line.

POWER REQUIREMENTS
The SSI 78P300 is a low-power CMOS device. It
operates from a single +5V power supply which can be
connected externally to both the transmitter and receiver. However, the two inputs must be within ±.3V of
each other, and decoupled to their respective grounds
separately, as shown in Figure 7. Isolation between the
transmit and receive circuits is provided internally.

PIN DESCRIPTION
NAME

TYPE

MCLK

I

Master Clock: A 1.544 or 2.048 MHz clock input used to generate internal
clocks. Upon Loss of Signal (LOS), RCLK is derived from MCLK. If MCLK not
applied, this pin should be grounded.

TCLK

I

Transmit Clock: Transmit clock input. TPOS and TNEG are sampled on the
falling edge of TCLK.

TPOS

I

Transmit Positive Data: Input for positive pulse to be transmitted on the twistedpair or coaxial cable.

TNEG

I

Transmit Negative Data: Input for negative pulse to be transmitted on the
twisted-pair or coaxial cable.

MODE

I

Mode Select: Setting MODE to logic 1 puts the SSI 78P300 in the Host mode.
In the Host mode, the serial interface is used to control the SSI 78P300 and
determined its status. Setting MODE to logic 0 puts the SSI 78P300 in the
Hardware (H/W) mode. In the Hardware mode the serial interface is disabled
and hard-wired pins are used to control configuration and report status.

RNEG/RPOS

0

Receive Negative Data/Receive Positive Data: Received data outputs. A
signal on RNEG corresponds receipt of a negative pulse on RTIP and RRING.
A signal on RPOS corresponds to receipt of a positive pulse on RTIP and
RRING. RNEG and RPOS outputs are Non-Return-to-Zero (NRZ). In the Host
Mode, CLKE determines the clock edge (RCLK) at which these outputs are
stable and valid. In the Hardware mode both outputs are stable and valid on the
rising edge or RCLK.

RCLK

0

Recovered Clock: This is the clock recovered from the signal received at RTIP
and RRING.

DESCRIPTION

6-4

SSI78P300
T1/E1 Integrated Short
Haul Transceiver with
Receive Jitter Attenuation
PIN DESCRIPTION (continued)
NAME

TYPE

DESCRIPTION

XTALIN/
XTALOUT

I/O

CrystallnputlCrystal Output: An external crystal operating at fourtimes the bit
rate (6.176 MHz for DSX-1, 8.192 MHz for CEPT applications with an 18.7 pF
load) is required to enable the jitter attenuation function of the SSI 78P300.
These pins may also be used to disable the jitter attenuator by connecting the
XTALIN pin to the positive supply through a resistor, and tying the XTALOUT
pin to ground.

DPM

0

Driver Performance Monitor: DPM goes to a logic 1 when the transmit monitor
loop (MTIP and MRING) does not detect a Signal for 63 ±2 clock periods. DPM
remains at logic 1 until a signal is detected.

LOS

0

Loss Of Signal: LOS goes to a logic 1 when 175 consecutive spaces have been
detected. LOS returns to a logic 0 when a mark is de~ected.

TTIP/TRING

0

Transmit Tip/Transmit Ring: Differential Driver Outputs. These outputs are
designed to drive a 25 n load. The transmitter will drive 100 n shielded twistedpair cable through a 2:1 step-up transformer without additional components.
To drive 75 n coaxial cable, two 2.2 n resistors are required in series with the
transformer.

TGND

-

Transmit Ground: Ground return for the transmit drivers power supply

TV+

I

Transmit Power Supply: +5 VDC power supply input for the transmit drivers.
TV+ must not vary from RV+ by more than ±0.3V.

MTIP/MRING

I

Monitor Tip/Monitor Ring: These pins are used to monitor the tip and ring
transmit outputs. The transceiver can be connected to monitor its own output
or the output of another SSI 78P300. To prevent false interrupts in the Host
mode if the monitor is not used, apply a clock signal to one of the monitor pins
and tie the other monitor pin to approximately the clock's mod-level voltage.
The monitor clock can range from 100 kHz to the TCLK frequency.

TV+_~

RTIP/RRING

I

Receive Tip/Receive Ring: The AMI signal received from the line is applied at
these pins. A center-tapped, center-grounded, 2:1 step-up transformer is
required on these pins. Data and clock from the signal applied at these pins are
recovered and output on the RPOS/RNEG, and RCLK pins.

RV+

I

Receive Power Supply: +5 VDC power supply for all circuits except the transmit
drivers. (Transmit drivers are supplied by TV+.)

RGND

-

Receive Gro_ul"I.9~_§round return for power supply RV+.

INT

0

Interrupt (Host Mode): This SSI 78P300 Host mode output goes low to flag the
host processor when LOS or DPM go active. INT is an open-drain output and
should be tied to power supply RV+ through a resistor. INT is reset by clearing
the respective register bit (LOS and/or DPM.)

EC1

I

Equalizer Control 1 (H/W Mode): The signal applied at this pin in the SSI
78P300 Hardware mode is used in conjunction with EC2 and EC3 inputs to
determine shape and amplitude of AMI output transmit pulses.

6-5

I

SSI78P300
T1/E1 Integrated Short
Haul Transceiver with
Receive Jitter Attenuation
PIN DESCRIPTION (continued)
NAME

TYPE

DESCRIPTION

SOl

I

Serial Data In (Host Mode): The serial data input stream is applied to this pin
when the SSI78P300 operates in the Host mode. SOl is sampled on the riSing
edge of SCLK.

EC2

I

Equalizer Control 2 (H/W Mode): The signal applied at this pin in the SSI
78P300 Hardware mode is used in conjunction with EC1 and EC3 inputs to
determine shape and amplitude of AMI output transmit pulses.

SOO

0

Serial Data Out (Host Mode): The serial data from the on-chip register is output
on this pin in the SSI78P300 Host mode. If CLKE is high, SOO is valid on the
rising edge of SCLK. If CL..KE is low SOO is valid on the falling edge of SCLK.
This pin goes to a high-impedance state when the serial port is being written
to and when CS is high.

EC3

I

Equalizer Control 3 (H/W Mode): The signal applied at this pin in the SSI
78P300 Hardware mode is used in conjunction with EC1 and EC2 inputs to
determine shape and amplitude of AMI output transmit pulses.

CS

I

Chip Select (Host Mode): This input is used to access the serial interface in the
SSI78P300 Host mode. For each read orwrite operation, CS must remain low
for duration of operation.

RLOOP

I

Remote Loopback (H/W Mode): This input controls loopback functions in the
SSI78P300 Hardware mode. Setting RLOOP to a logic 1 enables the Remote
Loopback mode. Se~ing both RLOOP and LLOOP caus~~_a Reset_.____

SCLK

I

Serial Clock (Host Mode): This clock is used in the SSI 78P300 Host mode to
write data to or read data from the serial interface registers.

LLOOP

I

Local Loopback (H/W Mode): This input controls loopback functions in the SSI
78P300 Hardware mode. Setting LLOOP to a logic 1 enables the Local
Loopback Mode.

CLKE

I

Clock Edge (Host Mode): Setting CLKE to logic 1 causes RPOS and RNEG to
be valid on the falling edge of RCLK, and SOO to be valid on the rising edge
of SCLK. When CLKE is a logic 0, RPOS and RNEG are valid on the rising edge
of RCLK, and SOO is valid on the falling edge of SCLK.

TAOS

I

Transmit All Ones (H/W Mode): When set to a logic 1, TAOS causes the SSI
78P300 (Hardware mode) to transmit ~ continuous stream of marks at the
TCLK frequency. Activating TAOS causes TPOS and TNEG inputs to be
ignored. TAOS is inhibited during Remote Loopback.

6-6

SSI78P300
T1/E1 Integrated Short

Haul Transceiver with
Receive Jitter Attenuation
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may damage the device.
PARAMETER

RATING

DC Supply (referenced to GND), RV+, TV+

a to 6.0V

Input Voltage, Any Pin, VIN (see note 1)

RGND -0.03 to RV+ +0.03V

---

---~~-

-10 to 10mA

Input Current, Any Pin, lin (see note 2)

---- -

Ambient Operating Temperature, TA

-40 to 85°C

Storage Temperature, T STG

-65 to 150°C

1

---~-~--------

Excluding RTIP and RRING which must stay within -6V to RV+ + 0.3V.

2

Transient currents of upto 100 rnA will not cuase SCR latch-up. TTIP, TRING, TV+ and TGND can withstand
a continuous current of 100 rnA.

RECOMMENDED OPERATING CONDITIONS
PARAMETER

CONDITIONS

DC supply, RV+, TV+ (see note 1)
Ambient Operating Temp., T A
Total Power Dissipation, PD
(see note 2)

1

MIN

NOM

MAX

4.75

5.0

5.25

V

-40

25

85

°C

620

-

mW

100% Ones Density &
Maximum Line Length
@ 5.25V

UNIT

TV+ must not exceed RV+ by more than ±0.3V.
Power dissipation while driving 250 load over operating temperature range. Includes device and load.
Digital input levels are within 10% of the supply rails and digital outputs are driving a 50pF capacitive load.

2

DIGITAL CHARACTERISTICS
TA = -40° to 85°C, V+ = 5.0 V± 5%, GND
V IH
VIL

= OV

High Level Input Voltage
(pins 1-5, 10, 23-28) (see note 1, 2)

2.0

Low Level Input Voltage
(pins 1-5, 10, 23-28) (see note 1,2)

-

-

V

-----

0.8
----"_.. -

VOH High Level Output Voltage
(pins 6-8, 11, 12, 23, 25)
(see note 1, 2)

lOUT = -400 IlA

VOL Low Level Output Voltage
(pins 6-8, 11, 12, 23, 25)
(see note 1, 2)

lOUT

ILL

Input Leakage Current

13L

Three -State Leakage Current
(pin 25) (see note 1)

1
2

2.4

-r------

-

-

a
a

V

0.4

V

±10

J..lA
J..lA

----~

±10

Functionality of pins 23 and 25 depends on mode. See Host / Hardware Mode descnptlons.
Output drivers will output CMOS logic levels into CMOS loads.
6-7

---~

---

----

= 1.6 rnA

V

I

SSI78P300
T1/E1 Integrated Short
Haul Transceiver with
Receive Jitter Attenuation
ELECTRICAL SPECIFICATIONS (continued)
ANALOG SPECIFICATIONS
TA = -40° to 85°C, V+ = 5.0 V± 5%, GND = OV
PARAMETER
AMI Output Pulse Amplitudes

TEST CONDITIONS

MIN

NOM

MAX

UNIT

DSX-1

Measured at the DSX

2.4

3.0

3.6

V

CEPT

Measured at Line Side

2.7

3.0

3.3

Load Presented to Transmitter Output

V
.Q

25

~

Jitted Added
by the Transmitter
(see note 1)

10 Hz - 8 kHz
8 kHz - 40 kHz
10 Hz - 40 kHz
Broad Band

Sensitivity Below DSX

0.01
0.025
0.025

- -----------_...•

-

..

~--

--_.

(OdB = 2.4V)

0.05

-

-

13.6

dB
mV

500
------

Loss of Signal Threshold
Data Decision Threshold

DSX-1
CEPT

~--

-

0.3

-

V

63

70

77

%peak
%peak

43

50

57

Allowable Consecutive Zeros Before LOS

160

175

190

Input Jitter Tolerance 10kHz - 100 kHz

0.4

-

1

3

-

UI

-~---

Jitter Attenuation Curve Corner Frequency
(see note 2)
2

,----

-

Hz

Input Signal to TCLK is jitter-free.
Circuit attenuates jitter at 20 dB/decade above the corner frequency.

TABLE 1: Equalizer Control Inputs
EC3

EC2

EC1

LINE LENGTH

CABLE LOSS

APPLICATION

0

1

1

0- 133 ft ABAM

0.6dB

1

0

0

133 - 266 ft ABAM

1.2 dB

1

0

1

266 - 399 ft ABAM

1.8 dB

1

1

0

399 - 533 ft ABAM

2.4 dB

1

1

1

533 - 655 ft ABAM

3.0 dB

0

0

0

cCln Recommendation G.703

CEPT

0

1

0

FCC Part 68, Option A

CSU

0

1

1

ECSA T1C1.2

FREQUENCY
t---~

DSX-1

----

1.544 MHz

2.048 MHz
---

6-8

~--

UI
UI
UI
UI

1.544 MHz

SSI78P300
T1/E1 Integrated Short
Haul Transceiver with
Receive Jitter Attenuation
TABLE 2: 78P300 Master Clock and Transmit Timing Characteristics
PARAMETER

CONDITIONS

Master clock frequency

MCLK DSX-1

MIN

NOM

-

,--

MCLK CEPT

--

MAX

UNIT

1.544

-

MHz

2.048

-

MHz

Master clock tolerance

MCLKt

-

±100

-

ppm

Master clock duty cycle

MCLKd

40

-

60

%
MHz

fc

DSX-1

-

6.176

-

fc

CEPT

-

8.192

-

MHz

Transmit clock frequency TCLK DSX-1

-

1.544
--

-

MHz

-

2.048

-

MHz

-

-

±50

ppm

Crystal frequency

TCLK CEPT
Transmit clock tolerance

TCLKt

f---

---

Transmit clock duty cycle TCLKd

10

-

90

%

tSUT

25

-

-

ns

tHT

25

-

-

ns

TPOSfTNEG to
TCLK setup time
TCLK to TPOS/TNEG
Hold time

TCLK

t,HT

TPOS
TNEG

>k=f
~

I
I-

FIGURE 1: 78P300 Transmit Clock Timing Diagram

:..

1
BIT CELL

0

.:
I

-,

+I

HIP

TRING

FIGURE 2: 50% AMI Coding Diagram

6-9

•

SSI78P300
T1/E1 Integrated Short
Haul Transceiver with
Receive Jitter Attenuation

RCLK
RPOS

RNEG
RPOS

RNEG

FIGURE 3: 78P300 Receive Clock Timing Diagram
TABLE 3: 78P300 Receive Timing Characteristics
PARAMETER
Receive clock duty cycle RCLKd
tpw
Receive clock pulse width

NOMl

MIN

CONDITIONS

40
-

DSX-1

60
324

tpw CEPT
RPOS/RNEG to RCLK

tSUR

DSX-1

MAX

-

UNIT

%
ns

244

-

ns

274

-

ns

274

-

ns

194

-

ns

.-

1--

rising setup time

-

tSUR CEPT

RCLK rising to RPOSI

tHR

RNEG hold time

tHR CEPT

194

1--

1

ns

---

DSX-1
-

Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.

TABLE 4: SSI78P300 Crystal Specifications (External)
PARAMETER

CEPT

T1

Frequency

6.176 MHz

8.192 MHz

Frequency Stability

±20 ppm @ 25°C

±20 ppm @ 25°C

±25 ppm from -40°C to + 85°C
(Ref 25°C reading)

± 25 ppm from -40°C to + 85°C
(Ref 25°C reading)

--

~---

._---------

= 11 pF to 18.7 pF,
+~F = 95 to 11 5 ppm
CL = 18.7 pF to 34 pF,
-~F = 95 to 115 ppm

Pullability

CL

= 11 pF to 18.7 pF,
+~F = 175 to 195 ppm
CL = 18.7 pF to 34 pF,
-~F = 175 to 195 ppm

CL

Effective series resistance

40 .Q Maximum

30 .Q Maximum

Crystal cut

AT

AT

Resonance

Parallel

Parallel

Maximum drive level

2.0mW

2.0mW

- --_.------

Mode of operation

Fundamental

Fundamental

Crystal holder

HC49 (R3W), 'Co = 7 pF Maximum
CM = 17 pF typical

HC49 (R3W), Co = 7 pF Maximum
C M = 17 pF typical

6-10

SSI78P300
T1/E1 Integrated Short
Haul Transceiver with
Receive Jitter Attenuation

CSI~

____________~I

SCLK

ADDRESS / COMMAND BYTE

SDI/SDO (MY

ADDRESS/
COMMAND
BYTE

DATA INPUT / OUTPUT BYTE

i

IAO I A1 I ~ "I A41 ASI
o

RiW

o

I

AS

00

o

i

I 01 I 02 103

o

04

105 106 107 J

o

X

AO

A6

Rm= 1; READ
Rm = 0 : WRITE

x = DON'T CARE

CLEAR INTERRUPTS

I-----r---+------,,-----.----f------r---+-----.
INPUT
DATA
BYTE

LOS
DO (LSB)

DPM

EC1

EC2

EC3

REMOTE LOCAL

TAOS
D7 (MSB)

L..-_ _- ' - -_ _.l...-_ _ _L . . - _ - . . L_ _- 1 -_ _--L_ _-'--_ _.......J

NOTE: Output Data
Byte same as Input
Data Byte shown at
left. except for Bits 05
through 07 shown in
Table 6.

FIGURE 4: SSI 78P300 Serial Interface Data Structure
TABLE 5: SSI78P300 Serial Data Output Bits (See Figure 4)

I

BIT 05

BIT 06

BIT 07

0

0

0

Reset has occurred, or no program input.

0

0

1

TAOS active

0

1

0

Local Loopback active

0

1

1

TAOS and Local Loopback active

1

0

0

Remote Loopback active

1

0

1

DPM has

1

1

0

LOS has changed state since last Clear LOS occurred

1

1

1

LOS and DPM have both changed state since last Clear DPM and
Clear LOS occurred

STATUS

.. -

c~anged

-------------

-

state since last Clear DPM occurred

6-11

SSI78P300
T1/E1 Integrated Short
Haul Transceiver with
Receive Jitter Attenuation

SCLK

SDI
DATA BYTE
FIGURE 5: SSI 78P300 Serial Data Input Timing Diagram

SCLK

SDO
CLKE = 1

SDO
CLKE = o~_---J

FIGURE 6: SSI 78P300 Serial Data Output Timing Diagram

6-12

SSI78P300
T1/E1 Integrated Short
Haul Transceiver with
Receive Jitter Attenuation
TABLE 6: SSI78P300 Serial 1/0 Timing Characteristics (See Figures 5 and 6)
PARAMETER

CONDITIONS

MIN

NOM'

MAX

-

-

100

ns

tDe

50

-

-

ns

SCLK to SOl hold time

teDH

50

-

-

ns

SCLK low time

tel

240

-

ns

SCLK high time

teH

240

-

ns

Rise/Fall time - any digital output

tRF

SOl to SCLK setup time

Load 1.6 rnA, 50 pF

UNIT

SCLK rise and fall time

tR, tF

50

ns

CS to SCLK setup time

tcc

50

-

-

ns

SCLK to CS hold time

teCH

50

-

-

ns

CS inactive time

teWH

250

-

-

ns

SCLK to SOO valid

tCDV

-

-

200

ns

SCLK falling edge or CS rising
edge to SOO high Z

teDZ

-

100

-

ns

-

-

, TYPical figures are at 25°C and are for deslng aid only; not guaranteed and not subject to production testing.

APPLICATION INFORMATION

SSI 78P300 2.048 MHz E1/CEPT INTERFACE
APPLICATIONS

SS178P300 1.544 MHz T1 INTERFACE
APPLICATIONS

Figure 8 is a typical 2.048 MHz E1/CEPT application.
The SSI 78P300 is shown in Hardware mode with the
2181 E1/CRC4 Framer. ReSistors are installed in line
with the transmit transformerfor loading a 75 Q coaxial
cable. The in-line resistors are not required for
transmission on 100 Q shielded twisted-pair lines. As
in the T1 application Figure 7, this configuration is
illustrated with a crystal in place to enable the SSI
78P300 Jitter Attenuation Loop, and a single power
supply bus. The hard-wired control lines for TAOS,
LLOOP and RLOOP are individually controllable, and
the LLOOP and RLOOP lines are also tied to a single
control for the Reset function.

Figure 7 is a typical 1.544 MHz T1 application. The SSI
78P300 is shown in the Host mode with the 2180A T1 /
ESF Framer providing the digital interface with the host
controller. Both devices are controlled through the
serial interface. The power supply inputs are tied to a
common bus with appropriate decoupling capaCitors
installed (1.0 ~F on the transmit side, 68 ~F and 0.1 ~F
on the receive side.)

6-13

I
•

SSI78P300
T1/E1 Integrated Short
Haul Transceiver with
Receive Jitter Attenuation

TO HOST CONTROLLER

SSI78P300
TRANSCEIVER

2180A
T1 ESF
FRAMER
TMSYNC TFSYNC

MCLK

CLKE

cs

TCLK

TCLK

SCLK

SDO

TPOS

TPOS

cs

SOl

TNEG

TNEG

SDO

SPS

MODE

SDI

RPOS

RNEG

HIT

RPOS

RGND

V+

iNT
SCLK

RNEG

RCLK

RCLK

~

RV+

XTALIN
XTALOUT

RRING
RTIP

DPM

MRING

LOS

MTiP

TTIP

TRING

TGND

TV+

OV

V+
1.011F

INOTEI11

THE SSI 78P300 IS COMPATIBLE WITH A WIDE VARIETY OF DIGITAL FRAMING AND SIGNALING DEVICES, INCLUDING THE
LXP 2180A, LXP2181, DS21sOA, MT8976, AND R8070.

INOTEI21

WHEN THE SSI 78P300 IS CONNECTED TO THE CROSS-CONNECT FRAME THROUGH A LOW LEVEL MONITOR JACK,
RECEIVE TRANSFORMER SHOULD BE 1 : 2 : 2 TO BOOST THE INPUT SIGNAL.

FIGURE 7: Typical SSI78P300 1.544 MHz T1 Application (Host Mode)

6-14

SSI78P300
T1/E1 Integrated Short
Haul Transceiver with
Receive Jitter Attenuation

2.048 MHz CLOCK
SSI78P300
TRANSCEIVER

LXP2181
E1/CRC4
FRAMER

MCLK

TAOS

TCLK

TCLK

LLOOP

TPOS

TPOS

RLOOP

TNEG

EC3

MODE

EC2

RNEG

RNEG

EC1

RPOS

RPOS

RGND

RCLK

RCLK

RV+

(NOTEI@

TNEG

XTALIN
XTALOUT

RRING
RTIP

DPM

MRING

LOS

MTIP

niP

TRING

TGND

TV+

~------~~----------------~~-+-----V+
1.011F

INOTEI11
I NOTE/21

2.2 n RESISTORS REQUIRED ONLY FOR 75 n COAXIAL CABLE.
NOT REQUIRED FOR TRANSMISSION ONTO 100 n CABLE.
THE SSI7BP300 IS COMPATIBLE WITH A WIDE VARIETY OF FRAMING AND
SIGNALING DEVICES, INCLUDING THE LXP21 B1, DS21 B1. MTB979, AND
RB070.

FIGURE 8: Typical SSI 78P300 2.048 MHz E1 Application (Hardware Mode)

6-15

I

SSI78P300
T1/E1 Integrated Short
Haul Transceiver with
Receive Jitter Attenuation
PACKAGE PIN DESIGNATIONS
(Top View)

CAUTION: Use handling procedures necessary
for a static sensitive component.

a..

en

«

(!)

SCLKlLLOOP

TCLK

ill

z

TPOS

CS/RLOOP

TNEG

SDO/EC3

MODE

SDIIEC2

RNEG

iNT/EC1

RPOS

RGND

RCLK

RV+

0
0

0

CLKEITAOS

MCLK

~

en

0

~
..J

~

~

a..

()

~

..J

()

::2

a..

..J
..J

0
0

~

..J

a:

()

en

I:::::

~

ill

()

..J

..J

I~

MODE

SDO/EC3

RNEG

24

SDI/EC2

RPOS

23

INT/EC1

RCLK

22

RGND

XTALIN

21

RV+

XTALOUT

20

RRING

19

RTIP

RRING

XTALIN

RTIP

XTALOUT

DPM
DPM

MRING

LOS

MTIP

niP

TRING

TGND

12

en

0

..J

TV+

13

a..

~

14 15 16
0

z

(!)
~

+

>
~

(!)

z

a:
~

17 18

a..
i=

::2

(!)

z

a:

::2

28·Pin PLCC

28·Pin DIP

ORDERING INFORMATION
PART DESCRIPTION
SSI 78P300 28-Pin PLCC
SSI 78P300 28-Pin DIP

ORDER NO.
78P300-IH
78P300-IP

PKG.MARK
78P300-IH
78P300-IP

No responsibility is assume<;t by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914

1293 - rev.

6-16

©1991 Silicon Systems, Inc.

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receive Jitter Attenuation

December 1993

DESCRIPTION

FEATURES

The 551 78P304A is a fully integrated low-power transceiver for both North American 1.544 MHz (T1), and
European 2.048 MHz (E1/CEPT) applications. It features a constant low output impedance transmitter allowing for high transmitter return loss in E1 applications.
Transmit pulse shapes (D5X-1 or E1/CEPT) are selectable for various line lengths and cable types.

•

•
•

The 551 78P304A provides receive jitter attenuation
starting at 3 Hz, and is microprocessor controllable
through a serial interface.

•

The 5S178P304A offers a variety of diagnostic features
including transmit and receive monitoring. The device
incorporates an on-chip crystal oscillator, and also accepts digital clock inputs. It uses an advanced doublepoly, double-metal CM05 process and requires only a
single 5-volt power supply.

•
•
•

•

APPLICATIONS
•
•
•
•
•
•
•
•

•

PCM I Voice Channel Banks
Data Channel Bank I Concentrator
T1 I E1 multiplexer
Digital Access and Cross-connect Systems (DAC5)
Computer to PBX interface (CPI & DMI)
High speed data transmission lines
Interfacing Customer Premises Equipment to a C5U
Digital Loop Carrier (DLC) terminals

Low power consumption (400 mW maximum)
40% less than the SSI 78P300
Constant low output impedance transmitter
regardless of data pattern
High transmit and receive return loss
Meets or exceeds all industry specifications
Including CCITT G.703, ANSI T1.403 and ATT
Pub 62411
Compatible with most popular PCM framers
Including the 2180A (T1) and 2181/2181A (E1)
Line driver, data recovery and clock recovery
functions
Minimum receive signal of 500 mV
Selectable slicer levels (CEPT/DSX-1) improve
SNR
Programmabletransmit equalizer shapes pulses
to meet DSX-1 pulse template from 0 to 655 ft

•

Local and remote loopback functions
Transmit I Receive perfonnance monitors with
DPM and LOS outputs

•

Receiver jitter tolerance 0.4 UI from 40 kHz to
100 kHz

•
•
•

Receive jitter attenuation starting at 6 Hz
Microprocessor controllable
Available in 28 pin DIP or PLCC

FIGURE 1: BLOCK DIAGRAM
MODE ------+-~
H ST

mw

[Nf ECl

SDI EC2
SDo EC3
CS RLOOP
SCLK LLOOP
CLKE TAOS

CONTROL
~-----~TTIP

TPOS--+-~

TNEG --+_-.1

EQUALIZER

TCLK - - + - - + - /

SYNCHRONIZER

/-------~TRING

RTIP

MCLK-f---I~

RRING

XTALlN~l--I;=::::::J===1
XTALOUT .....! - - - - !
RCLK4r---L-,,---.J

RPOS .....f - - - - i

RNEG41--L~:::'--.J
LOS

MTIP
MRING

-4-1f---------f

DPM~f----------------~

1293 - rev.

6-17

I

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

FUNCTIONAL DESCRIPTION

RECEIVER

The SSI 78P304A is a fully integrated PCM transceiver
for both 1.544 MHz (DSX-1) and 2.048 MHz (E1)
applications. It allows transmission of digital data over
existing twisted-pair installations. The SSI 78P304A
transceiver interfaces with two twisted-pair lines, one
twisted-pair for transmit, one twisted-pair for receive.

The SSI 78P304A receives the signal input from one
twisted-pair line on each side of a center-grounded
transformer. Positive pulses are received at RTIP and
negative pulses are received at RRING. Recovered
data is output at RPOS and RNEG, and the recovered
clock is output at RCLK. Refer to Table 3 and Figure 4
for SSI 78P304A receiver timing.

TRANSMITTER

The signal received at RPOS and RNEG is processed
through the peak detector and data slicers. The peak
detector samples the inputs and determines the maximum value of the received Signal. A percentage of the
peak value is provided to the data slicers as a threshold
level to ensure optimum signal-to-noise ratio. For DSX1 applications (determined by Equalizer Control inputs
EC 1 - EC3 *000) the threshold is set to 70% of the peak
value. This threshold is maintained above 65% for up to
15 successive zeros over the range of specified operating conditions. For E1 applications (EC inputs = 000 or
001) the threshold is 50%.

Data received for transmission onto the line is clocked
serially into the device at TPOS and TNEG. Input
synchronization is supplied by the transmit clock
(TCLK). The transmitted pulse shape is determined by
Equalizer Control signals EC 1 through EC3 as shown
in Table 1. Referto Table 2 and Figure 2 for master and
transmit clock timing characteristics. Shaped pulses are
applied to the AMI line driver for transmission onto the
line at niP and TRING. Equalizer Control signals may
be hardwired in the Hardware mode, or input as part of
the serial data stream (SOl) in the Host mode.

The receiver is capable of accurately recovering Signals
with up to -13.6 dB of attenuation (from 2.4V), corresponding to a received signal level of approximately 500
mV. Maximum line length is 1500 feet of ABAM cable
(approximately 6 dB of attenuation). Regardless of
received signal level , the peak detectors are held above
a minimum level of .3V to provide immunity from
impulsive noise.

Pulses can be shaped for either 1.544 or 2.048 MHz
applications. 1.544 MHz pulses for DSX-1 applications
can be programmed to match line lengths fromO to 655
feet of ABAM cable. The SSI 78P304A also matches
FCC and ECSA specifications for CSU applications. A
1:1.15 transmit transformer is used for all 1.544 MHz
systems.
2.048 MHz pulses can drive coaxial or shielded twistedpair lines. For E1 systems, a 1:2 transmit transformer
and series resistors are recommended. This design
meets or exceeds all CCIIT and European PIT specifications for transmit and receive return loss. A 1: 1 or
1:1.26 transformer may be used without series resistors.

After processing through the data slicers, the received
signal is routed to the data and clock recovery sections,
and to the receive monitor. The receive monitor generates a Loss of Signal (LOS) output upon receipt of 175
consecutive zeros (spaces). The receiver monitor loads
a digital counter at the RCLK frequency. The count is
incremented each time a zero is received, and reset to
zero each time a one (mark) is received. Upon receipt
of 175 consecutive zeros the LOS pin goes high, and a
smooth transition replaces the RCLK output with the
MCLK. (If MCLK is not supplied the RCLK output will be
replaced with the centered crystal clock.) The LOS pin
is reset immediately upon receipt of a one.

DRIVER PERFORMANCE MONITOR

The transceiver incorporates a Driver Performance
Monitor (DPM) in parallel with ITIP and TRING at the
output transformer. The DPM output goes high upon
detection of 63 consecutive zeros. It is reset when a one
is detected on the transmit line, or when a reset command is received.

Recovered clock signals are supplied to the jitter attenuator and the data latch. The recovered data is passed
to the elastic store where it is buffered and synchronized
with the dejittered recovered clock (RCLK).

LINE CODE

The SSI 78P304A transmits data as a 50% AM I line
code as shown in Figure 3. The output driver maintains
a constant low output impedance regardless of whether
it is driving marks or spaces.

6-18

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

JITTER ATTENUATION
Jitter attenuation of the SSI 78P304A clock and data
outputs is provided by a Jitter Attenuation Loop (JAL)
and an Elastic Store (ES). An external crystal oscillating
at 4 times the bit rate provides clock stabilization. Refer
to Table 4 for crystal specifications. The ES is a 32 x 2bit register. Recovered data is clocked into the ES with
the recovered clock signal, and clocked out of the ES
with the dejittered clock from the JAL. When the bit
count in the ES is within two bits of overflowing or
underflowing, the ES adjusts the output clock by 1/8 of
a bit period. The ES produces an average delay of 16 bfts
in the receive path.

The SSI78P304A serial port is addressed by setting bit
A4 in the Address/Command byte, corresponding to
address 16. The SSI 78P304A contains only a single
output data register so no complex chip addressing
scheme is required. The register is accessed by
causing the Chip Select (CS) input to make a transition
from high to low. Bit 1 of the serial Address/Command
byte provides Read/Write control when the chip is
accessed. A logic 1 indicates a read operation, and a
logic 0 indicates a write operation. Table 6 lists serial
data output bit combinations for each status. Serial
data I/O timing characteristics are shown in Table 6,
and Figures 6 and 7.

OPERATING MODES
The SSI78P304A transceiver can be controlled through
hard-wired pins (Hardware mode) or by a microprocessorthrough a serial interface (Host mode). The mode of
operation is set by the MODE pin logic level. The SSI
78P304A can also be commanded to operate in one of
several diagnostic modes.

HARDWARE MODE OPERATION
In Hardware mode the transceiver is accessed and
controlled through individual pins. With the exception of
the INT and CLKE functions, Hardware mode provides
all the functions provided in the Host mode. In the
Hardware mode RPOS and RNEG outputs are valid on
the rising edge of RCLK. To operate in Hardware mode,
MODE must be setto O. Equalizer Control signals (EC1
through EC3) are input on the Interrupt, Serial Data In
and Serial Data Out pins. Diagnostic control for Remote
Loopback (RLOOP), Local Loopback (LLOOP), and
Transmit All Ones (TAOS) modes is provided through
the individual pins used to control serial interface timing
in the Host mode.

HOST MODE OPERATION
To allow a host microprocessor to access and control
the SSI 78P304A through the serial interface, MODE is
set to 1. The serial interface (SDI/SDO) uses a 16-bit
word consisting of an 8-bit Command/Address byte and
an 8-bit Data byte. Figure 5 shows the serial interface
data structure and timing.

RESET OPERATION
Upon power up, the transceiver is held static until the
power supply reaches approximately 3V. Upon crossing this threshold, the device begins a 32 ms reset cycle
to calibrate the transmit and receive delay lines and lock
the Phase Lock Loop to the receive line. A reference
clock is required to calibrate the delay lines. The transmitter reference is provided by TCLK. The crystal oscillator provides the receiver reference. If the 78P304A
crystal oscillator is grounded, MCLK is used as the
receiver reference clock.

The Host mode provides a latched Interrupt output (INT)
which is triggered by a change in the Loss of Signal
(LOS) and/or Driver Performance Monitor (DPM) bits.
The Interrupt is cleared when the interrupt condition no
longer exists, and the host processor enables the respective bit in the serial input data byte. Host mode also
allows control of the serial data and receive data output
timing. The Clock Edge (CLKE) signal determines when
these outputs are valid, relative to the Serial Clock
(SCLK) or RCLK as follows:
CLKE

Output

LOW

RPOS
RNEG
SDO

RCLK
RCLK
SCLK

Rising
Rising
Falling

HIGH

RPOS
RNEG
SDO

RCLK
RCLK
SCLK

Falling
Falling
Rising

Clock

The transceiver can also be reset from the Host or
Hardware mode. In Host mode, reset is commanded by
simultaneously writing RLOOP and LLOOP to the register. In Hardware mode, reset is commanded by
holding RLOOP and LLOOP high simultaneously for
200 ns. Reset is initiated on the falling edge of the reset
request. In either mode, reset clears and sets all registers to 0 and centers the oscillator, then calibration
begins.

Valid Edge

6-19

I

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

DIAGNOSTIC MODE OPERATION
In Transmit All Ones (TAOS) mode the TPOS and
TNEG inputs to the transceiver are ignored. The transceiver transmits a continuous stream of 1's when the
TAOS mode is activated. TAOS can be commanded
simultaneously with Local Loopback, but is inhibited
during Remote Loopback.

TNEG and TCLK) are looped back onto the receive data
and clock outputs (RPOS, RNEG and RCLK.) The
transmitter circuits are unaffected by the LLOOP command. The TPOS and TNEG inputs (or a stream of 1's
if the TAOS command is active) will be transmitted
normally. When used in this mode with a crystal, the
transceiver can be used as a stand-alone jitter attenuator.

In Remote Loopback(RLOOP) mode, the transmit data
and clock inputs (TPOS, TNEG and TCLK) are ignored.
The RPOS and RNEG outputs are looped back through
the transmit circuits and output on TTIP and TRING at
the RCLK frequency. Receiver circuits are unaffected
by the RLOOP command and continue to output the
RPOS, RNEG and RCLK signals received from the
twisted-pair line.

POWER REQUIREMENTS
The SSI 78P304A is a low-power CMOS device. It
operates from a single +5 V power supply which can be
connected externally to both the transmitter and receiver. However, the two inputs must be within ± .3V of
each other, and decoupled to their respective grounds
separately, as shown in Figure 8. Isolation between the
transmit and receive circuits is provided internally.

In Local Loopback (LLOOP) mode, the receiver circuits
are inhibited. The transmit data and clock inputs (TPOS,

PIN DESCRIPTION
DESCRIPTION

NAME

TYPE

MCLK

I

MasterClock:A 1.544or2.048 MHzclock inputusedtogenerate internal clocks.
Upon Loss of Signal (LOS), RCLK is derived from MCLK.lf MCLK is not applied,
this pin should be 9!_~unded.

TCLK

I

Transmit Clock: Transmit clock input. TPOS and TNEG are sampled on the
falling edge of TCLK.

TPOS

I

Transmit Positive Data: Input for positive pulse to be transmitted on the twistedpair or coaxial cable.

TNEG

I

Transmit Negative Data: Input for negative pulse to be transmitted on the
twisted-pair or coaxial cable.

MODE

I

Mode Select: Setting MODE to logic 1 puts the SSI 78P304A in the Host mode.
In the Host mode, the serial interface is used to control the SSI 78Q904A and
determine its status.
Setting MODE to logic 0 puts the SSI 78P304A in the Hardware (H/W) mode. In
the Hardware mode the serial interface is disabled and hard-wired pins are used
to control configuration and report status.

RNEG/RPOS

0

Receive Negative/Positive Data: Received data outputs. A signal on RNEG
corresponds to receipt of a negative pulse on RTIP and RRING. A signal on
RPOS corresponds to receipt of a positive pulse on RTIP and RRING. RNEG
and RPOS outputs are Non-Return-to-Zero (NRZ). In the Host mode, CLKE
determines the clock edge at which these outputs are stable and valid. In the
Hardware mode both outputs are stable and valid on the rising edge of RCLK.

RCLK

0

Recovered Clock: This is the clock recovered from the signal received at RTIP
and RRING.

6-20

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

PIN DESCRIPTION
NAME

(continued)

TYPE

DESCRIPTION

XTALIN I XTALOUT

I

Crystal Input / Crystal Output: An external crystal operating at four times the bit
rate (6.176 MHz for DSX-1, 8.192 MHz for E1 applications with an 18.7pF load)
is required to enable the jitter attenuation function of the SSI 78P304A. These
pins may also be used to disable the jitter attenuator by connecting the XTALIN
pin to the positive supply through a resistor, and tying the XTALOUT pin to
ground.

DPM

0

Driver Performance Monitor: DPM goes to a logic 1 when the transmit monitor
loop (MTIP and MRING) does not detect a signal for 63 ±2 clock periods. DPM
remains at logic 1 until a signal is detected.

LOS

0

Loss of Signal: LOS goes to a logic 1 when 175 consecutive spaces have been
detected. LOS returns to a logic 0 when a mark is received.

TTIP I TTRING

0

Transmit Tip I Transmit Ring: Differential Driver Outputs. These low impedance
outputs achieve maximum power savings through a 1 :1.15 transformer (T1), or
a 1:1 or 1 :1.26 transformer (E1) without additional components. To provide
higher return loss for E1 systems, resistors may be used in series with a 1:2
transformer (use 150 resistors for 1200 terminations, and 9.30 resistors for 750
terminations. )

TGND

-

Transmit Ground: Ground return for the transmit drivers power supply TV +.

TV+

I

Transmit Power Supply: +5 VDC power supply input forthe transmit drivers. TV+
must not vary fro_~ RV+ ~y more than ±0.3V.

MTIP / MRING

I

Monitor Tip I Monitor Ring: These pins are used to monitor the tip and ring
transmit outputs. The transceiver can be connected to monitor its own output or
the output of another 78P304A on the board. To prevent false interrupts in the
host mode if the monitor is not used, apply a clock signal to one of the monitor
pins and tie the other monitor pin to approximately the clock's mid-level voltage.
The monitor c!c:>~~_~~_~ rang~ from_~ 90k~~~~_!~e TCLK frequency.

RTIP I RRING

0

Receive Tip / Receive Ring: The AMI signal received from the line is applied at
these pins. A center-tapped, center-grounded, 2:1 step-up transformer is
required on these pins. Data and clock from the signal applied at these pins are
recovered an~?~~p~! on the R~OS/~_~5G, an~~~~J~~~s.

RV+

I

Received Power Supply: +5 VDC power supply for all circuits except the
supplied
by TV+.)
transmit drivers.-._--_.
(Transmit drivers are
---- ..
.... --.- ...------.----.-

RGND

-

Receive Gr()_LJl1d:G_r()LJ_~_gJ:~turn f9wer sUf>P-'l~V±.

INT

0

Interrupt (Host Mode): This SSI 78P304A Host mode output goes low to flag the
host processor when LOS or DPM go active. INT is an open-drain output and
should be tied to power supply RV + through a resistor. INT is reset by clearing
the respectiv~_!egist~r bit (LOS_~_~d/or DPfI.,1J __

EC1

I

Equalizer Control 1 (H/W Mode): The signal applied at this pin in the SSI
78P304A Hardware mode is used in conjunction with EC2 and EC3 inputs to
determine shape and amplitude of AMI output transmit pulses.

-~-

6-21

--.~--~----.~

I

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

PIN DESCRIPTION
NAME

(continued)

TYPE

DESCRIPTION

SOl

I

Serial Data In (Host Mode): The serial data input stream is applied to this pin
when the SSI78P304A operates in the Host mode. SOl is sampled on the riSing
edge of SCLK

EC2

I

Equalizer Control 2 (H/W Mode): The signal applied at this pin in the SSI
78P304A Hardware mode is used in conjunction with EC1 and EC3 inputs to
determine shape and amplitude of AMI output transmit pulses.

SOO

0

Serial Data Out (Host Mode): The serial data from the on-chip register is output
on this pin in the SSI 78P304A Host mode. If CLKE is high, SOO is valid on the
rising edge of SCLK. If CLKE is low SOO is valid on the falling edge of SCLK.
This pin goes to a high-impedance state when the serial port is being written to
and when CS is high.

EC3

I

Equalizer Control 3 (H/W Mode): The signal applied at this pin in the SSI
78P304A Hardware mode is used in conjunction with EC1 and EC2 inputs to
determine shape and amplitude of AMI output transmit pu!~~s.

CS

I

Chip Select (Host Mode): This input is used to access the serial interface in the
SSI78P304A Host mode. For each read orwrite operation, CS must remain low
for the duration of operation.

RLOOP

I

Remote Loopback (H/W Mode): This input controls loopback functions in the
SSI78P304A Hardware mode. Setting RLOOP to a logic 1 enables the Remote
Loopback mode. ~_~!t!r:!~L~th RLOOP and LLOOP'cau~e~~ Reset.

SCLK

I

Serial Clock (Host Mode): This clock is used in the SSI78P304A Host mode
to write data to or re~d data from the serial interface regi_~!~t~.

LLOOP

I

Local Loopback (H/W Mode): This input controls loopback functions in the SSI
78P304A Hardware mode. Setting LLOOP to a logic 1 enables the Local
Loopback Mode.

CLKE

I

Clock Edge (Host Mode): Setting CLKE to logic 1 causes RPOS and RNEG to
be valid on the falling edge of RCLK, and SOO to be valid on the riSing edge of
SCLK. When CLKE is a logic 0, RPOS and RNEG are valid on the rising edge
of RCLK, and SOO is valid on the falling edge of SCLK.

TAOS

I

Transmit All Ones (H/W Mode): When set to a logic 1, TAOS causes the SSI
78P304A (Hardware mode) to transmit a continuous stream of marks at the
TCLK frequency. Activating TAOS causes TPOS and TNEG inputs to be
ignored. TAOS is inhibited during Remote Loopback.

6-22

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may damage the device. Normal operation not guaranteed at these
extremes.
PARAMETER

RATING

DC supply (referenced to GND)
Input voltage, any pin (see note 1)

RV+, TV+
VIN

UNIT

-0 to 6.0

V

RGND -0.3 to RV+ + 0.3

V
rnA

Input current, any pin (see note 2)

liN

-10 to +10

Ambient operating temperature

TA

-40 to 85

°C
-~~-

TSTG

Storage temperature
1

2

-65 to 150

°C

Excluding RTIP and RRING which must stay within -6V to RV+ + 0.3V.
Transient currents of upto 100 rnA will not cause SCR latch-up. TTIP, TRING, TV+ and TGND can withstand
a continuous current of 100 rnA.

RECOMMENDED OPERATING CONDITIONS
PARAMETER

SYMBOL

MIN

NOM

MAX

UNIT

DC supply (see note 1)

RV+, TV+

4.75

5.0

5.25

V

-40

25

85

°C

-

-

400

mW

Ambient Operating Temperature

- ---

TA

--------

Total power dissipation
(see note 2)
1
2

Po

100% ones density & max
line length @ 5.25V

TV+ must not exceed RV+ by more than ±O.3 V.
Power dissipation while driving 250 load over operating temperature range. Includes device and load.
Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load.

DIGITAL CHARACTERISTICS (TA
PARAMETER
High level input voltage
(see notes 1 & 2)

= -40° to 85°C, V+ = 5.0V ±5%, GND = OV)
CONDITIONS

MIN

VIH

NOM

2.0

MAX

UNIT

-

V

0.8

V

-~------

-

Low level input voltage
(see notes 1 & 2)

VIL

High level output voltage
(see notes 1 & 2)

VOH

lOUT = -400 jJA

Low level output voltage
(see notes 1 & 2)

VOL

lOUT = 1.6 rnA

Input leakage current
(see note 3)

ILL

---_._-

- -f - - - - -

... _--_.-

1

3

------

V
----_._---- --

-

_._--

0.4

V

±10

jJA

------_ .. _---

0
----- .. _----._--_. --------"---_.

Three-state
leakage current (see note 2) 13L

2

-

2.4

----- - - - - -

0

±10

Functionality of pins 23 and 25 depends on mode. See Host / Hardware Mode descriptions.
Output drivers will output CMOS logic levels into CMOS loads.
Except MTIP and MRING ILL = ± 50 IJ.A.
6-23

---

jJA

I

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

ELECTRICAL SPECIFICATIONS (continued)
ANALOG SPECIFICATIONS (TA = -40 to 85 oc, V+ = 5.0V ±5%, GND = OV)
TEST CONDITIONS

MIN

NOM

MAX

AMI Output

PARAMETER
DSX-1

measured at the DSX

2.4

3.0

3.6

Pulse Amplitudes

CEPT

measured__~LljmL$Jc:je

2.7

3.0____ c- ___ ~.3

UNIT

V

-~--

Load presented to transmitter out~t

-

75

Jitter added by

10 Hz - 8 kHz

-

the transmitter

8kHz-40kHz

-

-

(see note 1)

10Hz-40kHz

-

-

Broad Band

-

-

Sensitivity below DSX (0 dB

= 2.4V)

V

n

-

._--

___9J)1

UI

0.025

UI

--_.-

•.

0.025

UI

---~-.

0.05
--_..----_.

13.6

- -

5~ r----------- -----

UI

-

---------------

dB __

~.Y~
V

-

0.3

Data decision

DSX-1

63

70

77

%peak

threshold

CEPT

43

50

57

o/oQ.eak

160

175

Loss of Signal threshold

Allowable consecutive

--- -

190

zeros before LOS

---- .--_._--

10kHz - 100 kHz

Input jitter

0.4

-

-

6

----

UI

tolerance
Jitter attenuation

-

curve corner frequency (see note 2)
.--.--~--

Minimum Return Loss

Transmit

(see notes 3 & 4)
51 kHz -

1

2
3

4

102 kHz

Hz
--------

Receive

Min

Typ

Min

20

28

20

30
30

dB

25

dB

102 kHz - 2.048 MHz

20

28

20
------

2.048 MHz - 3.072 MHz

20

24

20

Typ

._---

--

dB

Input signal to TCLK is jitter-free.
Circuit attenuates jitter at 20 dB/decade above the corner frequency.
In accordance with CCITT G.703/RC6367A return loss specifications (CEPT), when wired as shown in
Figure 9.
Guaranteed by design.

6-24

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

TABLE 1: Equalizer Control Inputs for Transmitter

1
2

Line Length 1

Cable Loss2

EC3

EC2

EC1

0
1
1
1
1

1
0
0
1
1

1
0
1
0
1

0
0

0
0

0
1

0

1

0

FCC Part 68, Option A

0

1

1

ECSA T1C1.2

0- 133 ft
133 - 266 ft
266 - 399 ft
399 - 533 ft
533 - 655 ft

ABAM
ABAM
ABAM
ABAM
ABAM

O.6dB
1.2 dB
1.8 dB
2.4 dB
3.0 dB

CCITT Recommendation G.703

Application

Frequency

DSX-1

1.544 MHz

E1 - Coax (75 Q)
E1 - Twisted-pair (120 Q)

2.048 MHz

CSU

1.544 MHz

Line length from transceiver to DSX-1 cross-connect point.
Maximum cable loss at 772 kHz.

I

6-25

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

TCLK
tSUT

tHT

TPOS
TNEG

Figure 2: SSI 78P304A Transmit Clock Timing

•,

BIT CEll

,

1;"III
...I-------t.,.~,

,L-

___

I

,

TTIP

,
,

-',
-,-

..4-

-'

...L
TAING

,

,

-,-

,

.--

-

-

-

f

Figure 3: 50% AMI Coding
TABLE 2: SSI78P304A Master Clock and Transmit Timing Characteristics (See Figure 2)
Typl

Max

Units

-

1.544

-

MHz

-

2.048

-

MHz

-

±100

-

ppm

40

-

60

%

fc

-

6.176

-

MHz

Sym

Min

DSX-1

MCLK

E1

MCLK

Master clock tolerance

MCLKt

Master clock duty cycle

MCLKd

Parameter
Master clock frequency

Crystal frequency

DSX-1

fc

-

8.192

-

MHz

Transmit clock frequency

DSX-1

TCLK

-

1.544

-

MHz

E1

TCLK

-

2.048

-

MHz
ppm

E1

Transmit clock tolerance

TCLKt

-

-

±50

Transmit clock duty cycle

TCLKd

40

-

60

tSUT

25

-

-

ns

25

-

-

ns

TPOSITNEG to TCLK setup time
TCLK to TPOSITNEG Hold time
1 Typical

tHT

%

figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
6-26

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

RCLK
RPOS
RNEG
HOST MODE
'/
CLKE: 0, &
r--HIWMODE

RPOS
RNEG

FIGURE 4: SSI78P304A Receive Clock Timing
TABLE 3: SSI78P304A Receive Timing CharacteristiCS (See Figure 4)
Sym

Parameter
Receive clock duty cycle
Receive clock pulse width

DSX-1

Min

Typ1

Max

Units

60

%

RCLKd

40

-

tpw

-

324

-

ns

244

-

ns

274

-

ns

CEPT

tpw

-

RPOS / RNEG to RCLK

DSX-1

tSUR

-

rising setup time

CEPT

tsuR

-

194

-

ns

274

-

ns

194

-

ns

RCLK rising to RPOS /

DSX-1

tHR

-

RNEG hold time

CEPT

tHR

-

1Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.

TABLE 4: SSI78P304A Crystal Specifications (External)
E1

T1

Parameter
Frequency

6.176 MHz

8.192 MHz

Frequency Stability

±20 ppm @ 25° C

±20 ppm @ 25° C

±25 ppm from -40° C to + 85° C
(Ref 25° C reading)

±25 ppm from -40° C to + 85° C
(Ref 25° C reading)

Pullability

CL = 11 pF to 18.7 pF,

+~F =

175 to 195 ppm CL = 11 pF to 18.7 pF,

CL = 18.7 pF to 34 pF, -~F = 175 to 195 ppm

+~F

= 95 to 115 ppm

CL = 18.7 pF to 34 pF, -~F = 95 to 115 ppm
300 Maximum

Effective series resistance 400 Maximum
Crystal cut

AT

AT

Resonance

Parallel

Parallel

Maximum drive level

2.0mW

2.0mW

Mode of operation

Fundamental

Fundamental

Crystal holder

HC49 (R3W), Co = 7 pF maximum
CM = 17 pF typical

HC49 (R3W), Co = 7 pF maximum
CM = 17 pF typical

6-27

I

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

~~~------------------------~I
SCLK
ADDRESS I COMMAND BYTE

501/500

r

FVW 1 AO 1 A1 1 A2

i

A3 1 A4 1

ASI

DATA INPUT I OUTPUT BYTE

I

AS

DO 1 01 1 02 1 03

i

04 1 05 1 OS 1 07!

~=~IRNiI~1
FVW.1 : READ
ANi. 0 : WRITE

x = ~ON'T CARE

CLEAR INTERRUPTS

SET LOOPBACKS OR RESET

NOTE' Output Data
Byte same as Input
Data Byte shown at
left, except for Brts 05
through 07 shown in
' - - _ - - ' -_ _'---_--'---_--'--_--1._ _-'-_---'--_ _--' Table 9 above.

r----.--t----,-----,---f---,---+-----,
INPUT
DATA
BYTE

FIGURE 5: SSI78P304A Serial Interface Data Structure
TABLE 5: SSI78P304A Serial Data Output Bits (See Figure 5)
Bit 05

Bit 06 Bit 07

Status

0

0

0

Reset has occurred, or no program input.

0

0

1

TAOS active

0

1

0

Local Loopback active

0

1

1

TAOS and Local Loopback active

1

0

0

Remote Loopback active

1

0

1

DPM has changed state since last Clear DPM occurred

1

1

0

LOS has changed state since last Clear LOS occurred

1

1

1

LOS and DPM have both changed state since last Clear DPM and Clear LOS
occurred

6-28

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

SCLK

SDI

FIGURE 6: SSI78P304A Serial Data Input Timing Diagram

SCLK

I

SDO

CLKE = 1

SDO

CLKE=O_ _---J

Figure 7: SSI 78P304A Serial Data Output Timing Diagram

6-29

SSI78P304A
LQw-Power T1/E1 Integrated Shon Haul
Transceiver with Receiver Jitter Attenuation

TABLE 6: SSI78P304A Serial 1/0 Timing Characteristics (See Figures 6 and 7)
Sym

Min

Typl

Max

Units

Rise/Fall time - any digital output

tRF

-

100

ns

SOl to SCLK setup time

tDC

50

tCDH

50

-

ns

SCLK to SOl hold time
SCLK low time

tCl

240

-

ns

SCLK high time

tCH

240

SCLK rise and fall time

tR , tF

-

CS to SCLK setup time

tcc

50

SCLK to CS hold time

tCCH

50

-

CS inactive time

tcwH

250

SCLK to SOO valid

tCDv
tCDZ

Parameter

SCLK falling edge or CS rising
edge to SOO high Z
1

Test Conditions
Load 1.6 rnA, 50pF

ns

-

ns

50

ns
ns

-

-

-

-

200

ns

-

100

-

ns

ns
ns

Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.

6-30

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

APPLICATION INFORMATION

TABLE 7: E1/CEPT Output Combinations

1.544 MHz T1INTERFACE APPLICATIONS
Figure 8 is a typical 1.544 MHz T1 application. The SSI
78P304A is shown in the Host mode with the 2180A T1 /
ESF Framer providing the digital interface with the host
controller. Both devices are controlled through the serial
interface. The power supply inputs are tied to acommon
bus with appropriate decoupling capacitors installed
(1.0 JlF on the transmit side, 68 JlF and 0.1 JlF on the
receive side.)

EC

750 Coax

001
001
000
000

1:1,
1 :2,
1:1,
1 :2,

1200 TWP

Rt = 10Q
Rt = 14.3Q
Rt = OQ
Rt = 9.37Q

1:1, Rt = 00
1 :2, Rt = 150
1 :1.26, Rt = 00
1 :2, Rt = 8.70

TO HOST CONTROLLER

2180A
T1 ESF
FRAMER

78P304A
TRANSCEIVER
MCLK

CLKE

TCLK

SCLK

TPOS

Cs

TNEG

TNEG

SDO

SPS

MODE

SDI

RPOS

RNEG

TNT

RPOS

RGND

v+
SDI

jNf
SCLK

RNEG
RCLK

RCLK

1.544 MHz

~[J

RV+

XTALIN
XTALOUT

RRING
RTIP

DPM

MRING

LOS

MTIP

niP

TAING

TGND

TV+

OV

V+
1.0~F

INOTEI11

THE SSI78P304A IS COMPATIBLE WITH A WIDE VARIETY OF DIGITAL FRAMING AND SIGNALING DEVICES, INCLUDING THE
LXP2180A. LXP2181. DS2180A. MT8976, AND RB070.

FIGURE 8: Typical SSI 78P304A 1.544 MHz T1 Application (Host Mode)
6-31

I

SSI78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

2.048 MHZ E1/CEPT INTERFACE APPLICATIONS
Figure 9 is a 2.048 MHz E1/CEPT coax application
using EC code 000 and 150 Rt resistors in line with the
transmit transformer to provide high return loss. When
high return loss is not a critical factor, a 1:1 or 1:1.26
transformer without in-line resistors provides maximum
power savings. Table 7 lists transformer ratios and Rt
values with associated 2.048 MHz EC codes for both
750 coax and 1200 TWP. The SSI78P304A is shown

LXP2181A
E1/CRC4
FRAMER

2.048 MHz CLOCK

in Hardware mode with the 2181A E1/CRC4 Framer.
The hard-wired control lines for TAOS, LLOOP and
RLOOP are individually controllable, and the LLOOP
and RLOOP lines are also tied to a single control forthe
Reset function. As in the T1 application Figure 8, this
configuration is illustrated with a crystal in place to
enable the SSI 78P304A Jitter Attenuation Loop, and a
single power supply bus.

78P304A
TRANSCEIVER
TAOS

MCLK

INOTEI11

TCLK
TPOS
TNEG

V+

TCLK

LLOOP

TPOS

RLOOP

TNEG

EC3

MODE

EC2

RNEG

RNEG

EC1

RPOS

RPOS

RGND

RCLK

RCLK

RV+
RRING

XTALIN

INOTE 11 IThe 78P304A is compatible

with a wide variety of framing
and signaling devices,
including the LXP21 ~lA,
DS2181A, MT8979, AND
R8070.

INOTEI21 Various transformer

ratios and associated
Rt values are listed in
Table 8.

XTALOUT

RTIP
MRING

DPM
LOS

MTIP

TTIP

TRING

TGND

TV+

V+
1.0 IJ.F

FIGURE 9: SSI78P304A 2.048 MHz E1 Application (Hardware Mode)

6-32

551 78P304A
Low-Power T1/E1 Integrated Short Haul
Transceiver with Receiver Jitter Attenuation

PACKAGE PIN DESIGNATIONS
(Top View)

CAUTION: Use handling procedures necessary
for a static sensitive component.

c..

0
0

C/)

MCLK

CLKEITAOS

TCLK

SCLKlLLOOP

TPOS

0

CJ
UJ

TNEG

SDO/EC3

MODE

SDI/EC2

RNEG

INT/EC1

RPOS

RGND

RCLK

c..
f-

4

3

f-

CS/RLOOP

C/)

0

Z

~

«
t::
UJ

f-

:2

-I
()

2

1

28

~

-I
()

-I
()

-I
-I

~

-I
()

~

C/)

27

c..

0
0

-I

a:

I~

26

MODE

25

SDO/EC3

RNEG

24

SDI/EC2

RPOS

23

fNT/EC1

RCLK

22

RGND

XTALIN

21

RV+

XTALOUT

20

RRING

19

RTIP

RV+

XTALIN

RRING

XTALOUT

RTIP
DPM

DPM

MRING

LOS

MTIP

TTIP

TRING

12 13
C/)

TGND

0

-I

TV+

c..

~

14 15 16

17

+

CJ

f-

a:f-

c..
F

0
Z

CJ
f-

>

z

:2

18
CJ

z

a::2

28-Pin PLCC

28-Pin DIP

I

ORDERING INFORMATION
PART DESCRIPTION

ORDER NO.

PKG.MARK

SSI 78P304A 28-Pin DIP
SSI 78P304A 28-Pin PLCC

78P304A-IP
78P304A-IH

78P304A-IP
78P304A-IH

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.

Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX (714) 573-6914

1293 - rev.

6-33

©1991 Silicon Systems, Inc.

Notes:

6-34

SSI78P7200
E3/0S-3 Line Interface
with Receive Eiualizer

'4Gm,m@jE·ZiU
November 1994

DESCRIPTION

FEATURES

The SSI 78P7200 is a line interface transceiver Ie
intended for DS-3 (44.736 Mbitls) and E3 (34.368
Mbitls) applications. The receiver has a very wide
dynamic range and is designed to accept HDB3 or
B3ZS-encoded Alternate-Mark Inversion (AMI) inputs;
it provides clock, positive data, negative data, and lowlevel signal detector logical outputs. An on-chip equalizer
improves the intersymbol interference tolerance on the
receive path. The transmitter converts clock and data
input signals into AMI pulses of the appropriate shape
for transmission. A line buildout (LBO) equalizer may
be selected to shape the outgoing pulses for shorter
line lengths. The SSI 78P7200 requires a single 5 volt
supply and is available in DIP and surface mount
packages.

•

Single chip transmit and receive Interface for
E3 (34.368 Mbit/s) or 05-3 (44.736 Mbit/s)
applications

•
•

On-chip Receive Equalizer
Unique clock recovery circuit, requires no
crystals, tuned components or external clock

•

Selectable transmit line buildout (LBO) to
accommodate shorter line lengths

•

Compliant with ANSI 11.102 - 1987,
TR-TSY-000499, CCITT G.703 and G.823
Low-level input signal indication
Available in DIP or surface mount packages

•
•
•
•

The 78P7200 works in either rate of DS-3 or E3 by
simple external components modification.

-40°C to +85°C operating range
Pin-compatible with 551 78P236, 78P2361 and
78P2362

BLOCK DIAGRAM

PIN DIAGRAM

~CLF1

RCLK

OPT2

LBO

LlN+

CPD

NCR

LOWSIG

LlN-

DVCC

NCR

RPOS

RFO

RNEG

RGND

RCLK

RVCC

DGND

TGND

NCD

LOUT+

LF2

NCT

LF1

LOUT-

OPT2

LBO

TYCC

OPT1

TCLK

TPOS

TNEG

28-Pin DIP

OPT1

CAUTION: Use handling procedures necessary
for a static sensitive component.

1194 - rev.

6-35

I

SSI78P7200
E3/0S-3 Line Interface
with Receive Equalizer
FUNCTIONAL DESCRIPTION
The SSI 78P7200 is a single chip line interface IC
designed to work with a 44.736 Mbitls OS-3 or 34.368
Mbitls E3 signal. The receiver recovers clock, positive
data and negative data from an Alternate Mark Inversion
(AMI) signal. The input signal should be B3ZS or HOB3
coded.

The output of the variable gain amplifier is compared to
a threshold value which is a fixed percentage of the
signal peak. In this way, even though the input signal
amplitude may fall below the minimum value that can
be regulated by the variable gain circuit, the proper
detection threshold is maintained.

The transmitter accepts CMOS level logical clock,
positive data and negative data and converts them to
the AMI signal to drive a 750 coaxial cable.
Programmable internal Line Buildout (LBO) circuitry
eliminates the need for external LBO networks for OS3 applications. When the option pins are properly
selected, the shape of the transmitted signal through
any cable length of 0 to 450 feet complies with the
published templates of ANSI T1.1 02-1987, CCITT
G.703 and TR-TSY-000499. The SSI 78P7200 is
designed to work with a B3ZS or HOB3 coded signal.
The B3ZS or HOB3 encoding and decoding functions
are normally included in the framer ICs or can easily
be implemented in a PAL.

Outputs of the data comparators are connected to the
clock recovery circuits. The clock recovery system
employs a unique phase locked loop which has an
auxiliary frequency-sensitive acquisition loop which is
active only when cycle-slipping occurs between the
received signal rate and the internal oscillator.
This system permits the loop to independently lock to
the frequency and phase of the incoming data stream
without the need for high preciSion and/or adjustable
oscillator or tuned circuits.
The response characteristic for the phase locked loop
is established by external filter components, RLF1,
RLF2 and CLF1. The values of these components are
specified such that the bandwidth of the phase locked
loop is greater than 200 kHz.

RECEIVER

The receiver input is normally transformer-coupled to
the AMI signal. The inputs to the IC are internally
referenced to RVCC. Since the input impedance of the
SSI78P7200 is high, the AMI line must be terminated
in 750. The input signal to the SSI 78P7200 must be
limited to a maximum of three consecutive zeros using
a coding scheme such as B3ZS or HOB3.

The jitter tolerance of the SSI 78P7200 exceeds the
requirements of TR-TSY -000499 for Category II
equipment for OS-3 rate and exceeds the requirements
of cCln G.823 for E3 rate. The jitter transfer function
is maximally flat so the IC doesn't add any significant
jitter to the system.
Figure 2 shows the recovered clock (RCLK), positive
data (RPOS) and negative data (RNEG) signals timing.
The data is valid on the rising edge of the clock. The
minimum setup and hold times allow easy interface to
framer circuits. These signals are CMOS-level outputs.

The AMI signal first enters a fixed equalizer which is
designed to overcome the intersymbol interference
caused by long cable lengths and crosstalk. This fixed
equalizer is optimized for OS-3 application and its
effect should be compensated by an external filter
circuit similar to Fig. 1, for all square shaped signals
such as OS3-high or 34 Mbit/s E3. The signal is then
input to a variable gain differential amplifier whose
output is maintained at a constant voltage level
regardless of the input voltage level. The gain of this
amplifier is adjusted by detecting the peak of the signal
and comparing it to a fixed reference.

Should the input Signal fall below a minimum value,
the LOWSIG pin goes active low. A time delay is
provided before this output is active so that transient
interruptions do not cause false indications. This signal
should be used as one of many indications to the cable
disconnect; the framer device should count the number
of zeros to declare the loss of signal. The RPOS and
RNEG signals generate random data following a
silence period. The framer device should ignore RPOS
and RNEG data if the LOWSIG pin is active low.

6-36

SSI78P7200
E3/DS-3 Line Interface
with Receive Equalizer
TRANSMITIER
The transmitter accepts unipolar CMOS level logical
clock (RCLK), positive data (RPOS) and negative data
(RNEG) signals and generates high current drive pulses
on the LOUT + and LOUT- pins. When properly
connected to a center tapped transformer, an AMI
pulse is generated which can drive a 75Q coaxial
cable.
Figure 3 shows the timing for the transmitter logic
signals. The output pulse width is internally set and is
not sensitive to input clock (TCLK) pulse width.
When a recommended transformer is used and option
pins are properly set, the transmitted pulse shape at
the end of a 75Q terminated cable of 0 to 450 feet will
fit the template for OSX3 pulse published in ANSI
T1.102-1987, BELLCORE TR-TSY -000499 and
CCITT G.703 documents for RFO = 5.23 kQ.
For34 MbiVs E3 application, when RFO = 6.81 kQ, the
transmitted pulse for a short cable matches the
requirements of CCITT G.703 when both LBO and
OPT1 pins are set LOW.
The SSI 78P7200 incorporates a selectable Line
Buildout (LBO) equalizer in the transmitter path. For
OS-3 applications, the LBO pin should be set HIGH if
the cable is shorter than 225 feet and set LOW for
longer cable lengths. For E3 application, LBO pin
should be set LOW regardless of cable length.

I

The OPT1 pin is set HIGH for normal OS-3 operation.
Setting the OPT1 pin to LOW increases the transmitter
power. The OPT1 pin should be set LOW for E3
applications.
The OPT2 pin should be set HIGH for normal operation.
Setting the OPT2 pin to LOW disables the transmitter
drivers and reduces the power consumption of the
circuit by approximately 125 mW.

6-37

nt:

E3 Suggested Input circuit

O.47~H

LtJ
o

75

~.'

I OUN +

RTR

"= , ••:"'.

OS-3 Input circuit

D[[
10

LlN+

10

LlN-

RTR

I

RFO

1:1

Note: Only one of the two input circuits is needed
(J)

~

D
b>-

.+5V

b>-

en

~

RVcc

RLF2

I

I

I

1:2

OPT2

Note: NC pins should be tied to the ground pin
indicated by the trailing letter.

FIGURE 1: Functional Diagram

SSI78P7200
E3/0S-3 Line Interface
with Receive Equalizer
PIN DESCRIPTION
RECEIVER
NAME

TYPE

DESCRIPTION

LlN+, LlN-

I

Differential inputs, transformer-coupled from line.

RPOS

0

Unipolar receiver output, active as result of positive pulse at inputs.

RNEG
RCLK

0
0

Clock pulses recovered from line data.

LOWSIG

0

Low Signal logic output indicating that input signal is less than threshold
value.

TPOS

I

Unipolar transmitter data input, active high.

TNEG

I

Unipolar transmitter data input, active high.

TCLK

I

Transmitter clock input, active high.

LOUT+

0
0

Output to transformer for positive data pulses.

LOUTLBO

I

Transmitter line buildoutcontrol. Set low for E3 or OS-3 cable of 225' or longer.

OPT1

I

Transmit option 1. Selects faster output pulse transition time and higher
amplitude when low. Set high for normal DS-3 and set low for E3.

OPT2

I

Transmit option 2. Disables output driver and reduces output bias current
when 10w.Set high for normal transmit operation.

Unipolar receiver output, active as result of negative pulse at inputs.

TRANSMITTER

Output to transformer for negative data pulses.

EXTERNAL COMPONENT CONNECTION
RFO

I

Resistor connected to RGND to provide basic center frequency of receiver
phase locked loop oscillator.

LF1, LF2

-

Resistor-capacitor loop filter network to establish bandwidth of phase locked
loop.

CPO

-

Capacitor to RVcc that is connected to peak detector node to reduce signaldependent ripple on that node.

POWER
TVcc

-

5V power supply for transmit circuits.
5V power supply for receive circuits.

RVcc
DVcc

-

5V power supply for receive logic circuits.

TGND

-

Ground return for transmit circuits.

RGND

-

Ground return for receive circuits.

DGND

-

Ground return for receive logic circuits.

NCR

-

No connect, Tie to Receiver Ground (RGND).

NCT

-

No connect, Tie to Transmitter Ground (TGND).

NCO

-

No connect, Tie to Digital Ground.
6-39

I

SSI78P7200
E3/DS·3 Line Interface
with Receive Equalizer
ELECTRICAL SPECIFICATIONS
(TA = -40°C to 85°C, Vcc = 5V ±5%, unless otherwise noted.) Currents flowing into the chip are positive.
Current maximums are currents with the largest absolute value. Operation above absolute maximum
ratings may permanently damage the device.
ABSOLUTE MAXIMUM RATINGS
PARAMETER

RATING

Positive 5V supply: TVcc, RVcc, DVcc

6V

Storage Temperature

-65 to 150°C

Soldering Temperature (10 sec.)

260°C

Ambient Operating Temperature, TA

-40 to +85°C

Pin Ratings: LOUT +, LOUT-

Vcc -2 to Vcc +2V

LlN+, LlN-, TPOS, TNEG, TCLK,
LBO, RFO, LF2, LF1,
OPT1, OPT2 Pins

-0.3 to Vcc +0.3V

RPOS, RNEG, RCLK, LOWSIG Pins

-0.3 to Vcc +0.3V
or +12 mA

SUPPLY CURRENTS AND POWER
PARAMETER
Supply Current

Power Dissipation

MIN

CONDITIONS
ICC

P

Outputs Unloaded,
normal operation,
transmit and receive
all 1's pattern

NOM

MAX

UNIT

150

182

mA

0.93

W

Outputs unloaded,
TA= 85°C

EXTERNAL COMPONENTS (Common to DS3/E3, Nominal value.)
Loop filter resistor

RLF1

1% tolerance

6.04

kn

Loop filter resistor

RLF2

1%

100

kn

Loop filter capacitor

CLF1

5%

0.22

IlF

10%

0.022

IlF

Peak detector capacitor

CPO

EXTERNAL COMPONENTS (Dependent on speed, Nominal Value.)

DS-3

E3

Loop center frequency resistor RFO

1% tolerance

5.23

6.81

kO

Transmit termination capacitor CTT

5%

10

3

pF

Transmit termination resistor

RTT

1%

301

604

n

Receive termination resistor

RTR

1%

75

422

n

T1

3%

1 :1

1 :2

Receive Transformer
Turns Ratio

6-40

SSI78P7200
E3/0S-3 Line Interface
with Receive Equalizer
DIGITAL INPUTS AND OUTPUTS
(CMOS-compatible pins: LOWSIG, RPOS, RNEG, RCLK, TPOS, TNEG, TCLK, LBO, OPT1.) Currents
flowing into the chip are positive. Current maximums are currents with the largest absolute value.
PARAMETER

MAX

UNIT

Input low voltage

VIL

-0.3

1.5

V

Input high voltage

VIH

3.5

Vee +0.3

V

= 1.5V

-5

5

~

= 3.5V
IOL = 0.1 mA
IOH = -0.1 rnA

-5

5

~
V

CONDITIONS

Input low current

ilL

VIL

Input high current

IIH

VIH

Output low voltage

VOL

Output high voltage

VOH

MIN

NOM

0.4
4

V

OPT2 CHARACTERISTICS
Input low voltage

VIL

Input high voltage

VIH

ilL = 0.4 rnA

RECEIVER
All of the measurements for the receiver are made with the following conditions unless otherwise stated:
1.

The input signal is transformer coupled as shown in Figure 1.

2.

RFO = 5.23 kg for OS-3 and 6.81 kg for E3.

3.

UI (Unit Interval) defined as 22.35 ns for OS-3 and 29.1 ns for E3.

Input signal voltage

Input Resistance

VIN

RIN

Input AC-Coupled
CPO = 0.0221lF

±0.045

±1.2

CPO not used

±0.090

±1.2

V

30

kg

15

Input at device's common
mode voltage

Receive data detection
threshold

VOTH

Relative to peak
amplitude for 22.37/17.18 MHz
sinusoidal input

Receive data low signal
threshold

VLOW

Relative to peak
amplitude for 22.37/17.18 MHz
sinusoidal input

Receive data low signal
delay

TLOW

Relative to peak
amplitude for 22.37/17.18 MHz
sinusoidal input
CPO = 0.0221lF
CPO not used
VIN(max) = ±250 mV

Receive clock period

TRC

6-41

±20

±80

500
0.5

mV

IlS
3

IlS
ns

29.1

ns

OS-3

12.24

ns

E3

14.55

ns

E3
Receive clock pulse width

0/0

50

22.35

OS-3

TRCF

20

V

I

SSI78P7200
E3/0S-3 Line Interface
with Receive Equalizer
RECEIVER (continued)
PARAMETER

Receive clock positive
transition time

CONDITIONS

MIN

NOM

MAX

UNIT

TRCPT

CL = 15 pF

4.5

6

ns

Receive clock negative TRCNT
transition time

CL = 15 pF

4.5

6

ns

Positive or negative

TRDP

DS-3

Receive data pulse width TRDN

E3

Receive data set-up time

22.35

TRDPS

DS-3

5

11.18

TRDNS

E3

5

14.55

Receive data hold time TRDPH

DS-3

5

11.18

TRDNH

E3

5

14.55

Receive input jitter tolerance
high frequency (Note 3)

60 - 300 kHz
VIN (min) = ±45 mV

DS-3

10 - 800 kHz
VIN (min) = ±45 mV
10 - 800 kHz
VIN (min) = ±90 mV

UIPP

E3

0.20

UIPP
UIPP

DS-3

10

E3

10

DS-3

72

Clock Recovery Phase
Locked Oscillator Gain

KD

= 0.418/RFO

ns

0.15

100 Hz to 10 kHz

Detector Gain

13.7

E3

10 Hz to 2.3 kHz
All 1's data pattern

ns

UIPP

Receive input jitter tolerance
KD

13.7

0.3

low frequency (Note 3)
Clock Recovery Phase

ns

29.1

88

~Rad

17

Mrad/
sec. -Volt

62

E3
12

KO

UIPP
80
14.5

TRANSMITTER
All of the measurements for the transmitter are made with the following conditions unless otherwise stated:

1.

Transmit pulse characteristics are obtained using a line transformer which has the characteristics,
similar to pulse engineering PE-65969, Mini circuit T4-1, Valor PT5045.

2.

The circuit is connected as in Figure 1.

Transmit clock repetition

TICF

DS-3

Transmit clock pulse width TIC

DS-3

11.18

E3

14.55

22.35

ns

29.1

E3

ns

Transmit clock negative TICNT
transition time

4.5

6

ns

TICPT

4.5

6

ns

Transmn clock positive
transition time

Transmit data set-up timeTIPDS

DS-3

3.5

11.18

TINDS

E3

3.5

14.55

6-42

ns

SSI78P7200
E3/DS-3 Line Interface
with Receive Equalizer
TRANSMITTER (continued)
PARAMETER

MIN

NOM

Transmit data hold time TTPOH

OS-3

3.5

11.18

TTNOH

E3

3.5

14.55

10.62

11.18

10.62

11.18

CONDITIONS

Transmit positive line
pulse width

TTPL

Transmit negative line
pulse width

TTNL

Measured at
transformer,
LBO

= Low

E3

Measured at
transformer,
LBO

Transmit line pulse
waveshape

OS-3

UNIT
ns

12

ns

12

ns

14.5

DS-3

= Low

MAX

E3

14.5

ns

See Note 1 for OS-3
See Note 2 for E3

Note1:Characteristics are in accordance with ANSI T1.102 - 1987, Table 5 and Figure 8.
Note 2:Characteristics are in accordance with CCITT G.703 - 1988 Figure 17.

RECEIVEUNE
INPUT (REF)

----'
TRCF

RECCLOCK

REC POS ooT _ _ _--./

REC NEG OUT

_

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _{+TRDNS++TRDNH+)C. _ _ _ _ _ _ __
. +---TRDN----,

FIGURE 2: Receive Waveforms

TRANSMIT
CLOCK IN

TRANSMIT
POSIN
_ _ _ _.../

TRANSMIT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
NEG IN

~fTTNDS- TTNDH_}~

I_TTPLi

t

O_5~_P_=....Jj
~_

TRANSMIT
_______
LINE OUTPUT

L----------O.5-V-N=t~
VN

f

'--- - - - ' I_TTNL_I

FIGURE 3: Transmit Waveforms
6-43

_ _ _ _ _ _ _ __

I

SSI78P7200
E3/DS-3 Line Interface
with Receive Equalizer
PACKAGE PIN DESIGNATIONS

CAUTION: Use handling procedures necessary
for a static sensitive component.

(Top View)

LlN+

CPO

NCR

LOWSIG

LlN-

OVCC

NCR

RPOS

RFO

RNEG

RGNO

RCLK

RVec

DGNO

a:
<.)

z

a:
<.)

:2:

z

::J

+

0

::J

<.)

Z

I!

a...

4

<.)
<.)

>
0

26

•

RFO
RGND

25

RPOS

24

RNEG

RVCC

23

RCLK

TGND

22

DGND

TGNO

NCO

LOUT+

LF2

LOUT+

21

NCD

NeT

LF1

NCT

20

LF2

LOUT-

19

LF1

LOUT-

OPT2

LBO

TVCC

OPT1

TCLK

TPOS

TNEG

12

13

14

15

16

0

I~

(j)

CJ

::,c:

a...

(D

-1

28-Pin DIP

0

I--

W

-1
<.)

t-

I--

Z

17
<.)
<.)

>
t-

18

Ig

28-Pin PLCC

ORDERING INFORMATION
PART DESCRIPTION

ORDER NUMBER

PACKAGE MARK

SSI 78P7200, E3/DS-3 Line Interface - 28-pin
Standard Width Plastic
DIP (600 mil)

78P7200-IP

78P7200-IP

Surface Mount
28-pin PLCC

78P7200-IH

78P7200-IH

Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small q~antities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.

Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022,(714) 573-6000, FAX (714) 573-6914

©1990 Silicon Systems, Inc.

6-44

1194 - rev.

Section

7

LAN PRODUCTS

I

7

7-0

551 78Q902
Ethernet Twisted-Pair Media
Attachment Unit

December 1992

DESCRIPTION

FEATURES

The 551 78Q902 twisted-pair Media Attachment Unit
(TP-MAU) is designed to allow Ethernet connections to
use the existing twisted-pair wiring plant through an
Ethernet Attachment Unit Interface (AUI). The 551
780902 provides the electrical interface between the
AUI and the twisted-pair wire.
551 780902 functions include level-shifted data passthrough from one transmission media to another, collision detection, Signal Quality Error (SOE) testing and
automatic correction of polarity reversal on the twisted
pair input. It also includes LED drivers for transmit,
receive, jabber, collision, reversed polarity detect and
link functions.
The 551780902 is an advanced CMOS device and
requires only a single 5-volt power supply.

•

Meets or exceeds IEEE 802.3 standards for AUI
and 10Base-T interface

•
•
•
•
•

Direct interface to AUI and RJ45 connectors

Jabber function

•

Selectable link test, SeE test disable

•

Twisted-pair receive polarity reverse detection
and selectable polarity correction

•

LED driver for transmit, receive, jabber,
collision, link and reversed polarity Indicators
or for flashing status Indicator

Automatic AUIIRJ45 selection
Internal predistortion generation
Internal common mode voltage generation

APPLICATIONS

•
•

• Computer/workstation interface boards
• LAN repeater

Single +5V supply, CMOS technology
Available in 28-pin DIP or PLCC

• External 1OBase-T converter

BLOCK DIAGRAM
DO P
DO N

..

J AUITXMIT I
RECEIVER

I

1 1

ILOOPBACKI ~

1 J

WATCHDOG
TIMER

--

DRIVER

lI

MD'v
MD 1

I

-

MODE
SELECT

ICOLLISION ~
DRIVER

~

I

..

~

POLARITY
DETECT

E::-

LINK
INTEGRITY
COLLISION
DETECTOR
SQETEST

SQUELCH

-

l:=-

LED
DRIVER

OSC

TPOP
TPON
PRC

TPIP
TPIN

TP
RECEIVER --

--

I

I

PULSE
SHAPING

4

I AUI RCVR L

DIP
DIN

CIP
CIN
SQE
ClK I
ClKO

;;;

I

PIN DIAGRAM

..
..

lEDP/S
lEDJ
lEDT
lEDR
lEDC
lEDl

DON

LEDC

DOP

lEDR

lEDJ

lEDT

lEDl

lEDP/S

PRC

TPOP

ClKO

GND2

ClKI

VCC2

GND1

TPON

CIN

VCC1

CIP

RBIAS

MDO

MD1

DIN

SQE

DIP

TPIP

LI

TPIN

28-Pin DIP
CAUTION:

1292 - rev.

7-1

Use handling procedures necessary
for a static sensitive component.

I

SSI78Q902
Ethernet Twisted-Pair Media
Attachment Unit
FUNCTIONAL DESCRIPTION

RECEIVE FUNCTION

The 551 780902 Media Attachment Unit (MAU) interfaces the Attachment Unit Interface (AUI) to the
unshielded twisted pair cables, transferring data in
both directions between the two. The AUI side of the
interface comprises three circuits: Oata Output (00),
Oata Input (01) and Collision Interface (CI). The twisted
pair network side of the interface comprises two circuits: Twisted Pair Input (TPI) and Twisted Pair Output
(TPO). In addition to the five basic circuits, the 551
780902 contains an internal crystal oscillator, separate power and ground pins for analog and digital
circuits, various logic controls and six LEO drivers for
status indications.

The 551 780902 receive function transfers serial data
from the twisted pair network (the TPI circuit) to the
OTE (overthe 01 circuit of the AUI). An internal squelch
function discriminates noise from link test pulses and
valid data streams. Only valid data streams activate the
receive function. If the differential inputs at the TPI
circuit fall below 75% of the threshold level
(unsquelched) for 8 bit times (typical), the 551780902
receive function will enter the idle state. The TPI
threshold can be reduced by approximately 3 dB to
allow for longer loops in low-noise environments. The
reduced threshold is selected when M01 = 0 and
MOO = 1.

Functions are defined from the AUI side of the interface. The 551780902 Transmit function refers to data
transmitted by the Oata Terminal Equipment (OTE)
through the AUI and MAU to the twisted pair network.
The 551 780902 Receive function refers to data received by the OTE through the MAU and AUI from the
twisted pair network. In addition to basic transmit and
receive functions, the 551 780902 performs all required MAU functions defined by the IEEE 802.3
1OBase-T specification such as collision detection, link
integrity testing, 5ignal Ouality Error (50E), jabber
control and loopback.

DIFFERENTIAL INPUT MODE
In the differential input mode, the transmit interface
consists of TXP and TXN, PE, POC, and the Transmit
Enable input (TEN). Transmission starts when PE is
high and TEN is low, and ends when either PE or TEN
goes inactive. Predistortion control is provided by the
POC input.
POLARITY REVERSE FUNCTION
The 551 780902 polarity reverse function uses both
link pulses and end-of-frame data to determine polarity
of the received signal. A reversed polarity condition is
detected when eight opposite receive link pulses are
detected without receipt of a link pulse with the expected polarity. Reversed polarity is also detected if
four frames are received with a reversed start-of-idle.
Whenever polarity is reversed, these two counters are
reset to zero. If the 551780902 enters the link fail state
and no data or link pulses are received within 96 to
128 ms, the polarity is reset to the default non-flipped
condition. (If Link Integrity is disabled, polarity detection is based only on received data pulses.)

TRAN5MIT FUNCTION
The 551 780902 transfers Manchester encoded data
from the AUI port of the OTE (the 00 circuit) to the
twisted pair network (the TPO circuit). The output
signal on TPON and TPOP is pre-distorted to meet the
10 Base-T jitter template, and filtered to meet FCC
requirements. The output waveform (after the transmit
filter) is shown in Figure 1 . If the differential inputs at the
00 circuit fall below 75% of the threshold level for 8 bit
times (typical), the 551 780902 transmit function will
enter the idle state. Ouring idle periods, the 551
780902 transmits link integrity test pulses on the TPO
circuit.

n
[\
n
V UV U

~

FIGURE 1: 78Q902 TPO Output Waveform
7-2

551 78Q902
Ethernet Twisted-Pair Media
Attachment Unit
COLLISION DETECTION FUNCTION

SQE TEST FUNCTION

The collision detection function operates on the twisted
pair side of the interface. A collision is defined as the
simultaneous presence of valid signals on both the TPI
circuit and the TPO circuit. The SSI 780902 reports
collisions to the AUI by sending a 10 MHz signal over
the CI circuit. The collision report signal is output no
more than 9 bit times (BT) after the chip detects a
collision. If the TPI circuit becomes active while there is
activity on the TPO circuit, the TPI data is passed to the
OTE overthe 01 circuit, disabling the loopback. Figure
2 is a state diagram of the SSI 780902 collision
detection function (referto IEEE 802.31 OBase-T specification).

Figure 3 is a state diagram of the SOE Test function.
The SOE test function is enabled when the SOE pin is
tied high. When enabled, the SOE test sequence is
transmitted to the controller after every successful
transmission on the10Base-T network. When a successful transmission is completed, the SSI 780902
transmits the SOE signal to the AUI over the CI circuit
for 10 BT ± 5 BT. The SOE function can be disabled for
hub applications by tying the SOE pin to ground.

JABBER CONTROL FUNCTION
Figure 4 is a state diagram of the SSI 780902 Jabber
control function. The SSI 780902 on-chip watchdog
timer prevents the OTE from locking into a continous
transmit mode. When a transmission exceeds the time
limit, the Watchdog timer disables the transmit and
loopback functions, and sends the SOE signal to the
OTE over the CI circuit. Once the SSI 780902 is in the
jabber state, the DO circuit must remain idle for a period
of 491 to 525 ms before it will exit the jabber state.

LOOPBACK FUNCTION
The SSI 780902 loopback function operates in conjunction with the transmit function. Data transmitted by
the OTE is internally looped backwithinthe SSI780902
fromthe OOpinstothe 01 pins and returnedtothe OTE.
The loopback function is disabled when a data collision
occurs, clearing the 01 circuitforthe TPI data. Loopback
is also disabled during link fail and jabber states.

DO = Active·
TPI = Idle·
XMIT = Enabled

IDLE
TPI = Active

OUTPUT

INPUT

TPO = DO
DI= DO

DI = TPI
DO= Active·
TPI = Active·
XMIT = Enabled r - - - - - - - - ,

L.....-_ _ _---I~

COLLISION

DO = Active·
TPI = Active·
XMIT = Enabled

~------'

TPI = Idle

DO = Idle +
XMIT = Disabled
DO = Active·
TPI = Idle

DO = Idle

FIGURE 2: Collision Detection Function

7-3

I

SSI78Q902
Ethernet Twisted-Pair Media
Attachment Unit
LINK INTEGRITY TEST FUNCTION

TEST MODE

Figure 5 is a state diagram of the SSI 780902 link
Integrity Test Function. The link Integrity Test is used
to determine the status of the receive side twisted pair
cable. The link integrity test is enabled when the LI pin
is tied high. When enabled, the receiver recognizes link
integrity pulses which are transmitted in the absence of
receive traffic. If no serial data stream or link integrity
pulses are detected within 50 - 150 ms, the chip enters
a link fail state and disables the transmit and loopback
functions. The SSI 780902 ignores any link integrity
pulse with intervals less than 2 - 7 ms. The SSI 780902
will remain in the link fail state until it detects either a
serial data packet or two or more link integrity pulses.

The SSI 780902 Test mode is selected when a 2 to
2.5 MHz clock is input on the MOO mode select pin.
Test mode sets the internal counter chains to run at
1024 times their normal speed. The maximum transmit
time, unjab time, link Integrity timing and LED timing
are reduced by a factor of 1024. During test operation,
10 MHzand20 MHz signals areoutputonthe PRC and
SOE pins, respectively. When Test mode is selected,
the SOE function cannot be disabled. In Test mode the
PRC function can be disabled by the LI pin. Jabbercan
be disabled by setting MD1 = O.

,

Power 0 n

Power On

1

,-

•

NO OUTPUT

OUTPUT IDLE

+

,

DO = Active

DO = Active

NONJABBER OUTPUT

OUTPUT DETECTED
StarcXMIT_Max_Timer

t

,

-

.. DO = Idlel

00= Idle

DO = Active'
XMIT_Max_Timer_D one
~

JAB
XMIT = Disable
LPBK = Disable
CI = SQE

SOE WAIT TEST
Start_SOE_Test_WaieTimer

..

I
XMIT = Disable

t

.. 00= Idle
SOE Test Wait_Timer_Done·
XMIT= Enabl e

UNJAB WAIT
Start_Unjab_Timer
XMIT = Disable
LPBK = Disable
CI = SQE

SOE TEST
Start_SOE_TeseTimer
CI = SOE
SOE_Test_Timer_Done

I
Unjab Timer Done

J

I
DO = Active'
Unjab_Timer_NoCDone

FIGURE 4: Jabber Control Function

FIGURE 3: SaE Test Function
7-4

SSI78Q902
Ethernet Twisted-Pair Media
Attachment Unit

Power On

i
IDLE TEST
Start_Link_Loss_Timer
Start_Lin~Test_Min_Timer

Link_Loss_Timer_Done
• TPI = Idle
• Link_TesCRcvd = False

TPI = Active +
(Link_Test_Rcvd = True
* Link_Test_Min_Timer_Done)

I

1-._ _ _ _ _ _ _ _ _ _ _- - - '

,

LINK TEST FAIL RESET
LINK TEST FAIL WAIT

Link_Count = 0
XMIT = Disable
RCVR = Disable
LPBK = Disable
TPI

=

XMIT = Disable
RCVR = Disable
LPBK = Disable
Link_Count = Link_Count + 1

Link_Test_Rcvd = False
• TPI = Idle

Active

TPI = Active

I

Link_Test_Rcvd

=

Idle

* TPI = Idle

LINK TEST FAIL

,

,

,

TPI = Active
= LC_Max

+ Link_Count

XMIT = Disable
RCVR = Disable
LPBK = Disable

DO

(TPI = Idle * Link_Test_Max_Timer_Done) +
(Link_Test_Min_Timer_Not_Done
* Link_TesCRcvd = True)

= Idle'
=

J
Link_Test_Min_Timer_Done
* Link_Test_Rcvd = True

LINK TEST FAIL EXTEND

L..-_ _ _ _ _ _ _ _ _....I1 TPI

Start_Link_Test_Min_Timer
Start_Link_TesCMax_Timer
XMIT = Disable
RCVR = Disable
LPBK = Disable

Idle

FIGURE 5: Link Integrity Test Function

7-5

I

551 78Q902
Ethernet Twisted-Pair Media
Attachment Unit
TABLE 1: Mode Select Options
MD1

MOO

0

0

MODE
Base-T compliant MAU

0

1

Reduced squelch level

1

0

Half current AUI driver

1

1

DO, DI & CI ports disabled

1

Clock

Test mode, jabber on

0

Clock

Test mode, jabber disabled

PIN DESCRIPTION
NAME

TYPE

DESCRIPTION

I

Data Out Negative/Data Out Positive: Differential input pair connected to the
AUI transceiver DO circuit

LEDJ

I/O

Jabber LED Driver: Open drain driver for the Jabber indicator LED. Output
goes active 1 when watchdog timer begins jab, and stays active until end of the
unjab wait period (491 - 525 ms). When tied to ground, causes LEDP/S to act
as a multi-function blinking status indicator.

LEDL

0

Link LED Driver: Open drain driver for the Link indicator LED. Output is active
except during Link Failor when Link Integrity Test is disabled.

PRC

I/O

Polarity Reverse Correction: The SSI780902 automatically corrects reversed
polarity at TPI when PRC is tied high. In Test mode, this pin is a 10 MHz output.

-

Crystal Oscillator: The SSI 780902 requires either a 20 MHz crystal (or
ceramic resonator) connected across these pins, or a 20 MHz clock applied at
CLKI.
--_. . __ ..

GND1

-

Ground #1.

CIN/CIP

0

Collision Negative/Collision Positive: Differential driver output pair tied to the
collision presence pair of the Ethernet transceiver AUI cable. The collision
presence signal is a 10 MHz square wave. This output is activated when a
collision is detected on the network, during self-test by the SOE sequence, or
after the watchdog timer has expired to indicate the transmit wire pair has been
disabled.

MDO

I

Mode Select 0: Selects operating modes in conjunction with MD1. See Table
1 above for mode select options.

DIN/DIP

0

Data In Negative/Data In Positive: Differential driver pair connected to the AUI
transceiver DI circuit.

DON/DOP

----

CLKO/CLKI

1

LED drivers pull low when active.

7-6

SSI78Q902
Ethernet Twisted-Pair Media
Attachment Unit
PIN DESCRIPTION
NAME

(continued)

TYPE

DESCRIPTION

LI

I

Link Integrity Test Enable: Link integrity testing is enabled when this pin is tied
high. With link test enabled, the SSI 780902 sends the link integrity signal in
the absence of transmit traffic. It also recognizes received link test pulses,
indicating the receive wire pair is present in the absence of transmit traffic.

TPIN/TPIP

I

Twisted Pair Receive Inputs: Differential receive inputs from the twisted pair
input filter.

SOE

I/O

Signal Ouality Error Test Enable: SOE is enabled when this pin is tie high.
When enabled, the SSI 780902 sends the signal quality error test sequence
to the CI of the AUI cable after every successful transmission to the media. In
Test mode, SOE becomes a 20 MHz output.

MD1

I

Mode Select 1: Selects operating modes in conjunction with MOO, (see Table
1). MD1 clock input between 2.0 and 2'.5 MHz enables Test mode.

RBIAS

-

Resistor Bias Control: Bias control pin for the operating circuit. Bias set from
external resistor to ground. External resistor value = 12.4 kn (±1 %).

VCC1

I

Power Supply 1: +5V power supply.

TPONITPOP

0

Twisted Pair Transmit Outputs: Transmit drivers to the twisted-pair output filter.
The output is Manchester encoded and pre-distorted to meet the 1OBase-T
template.

VCC2

I

Power Supply 2: +5V power supply.

GND2

-

Ground #2.

LEDP/S

0

Polarity/Status LED Driver: Open drain LED driver. In normal mode,
LEDP/S is active when reversed polarity is detected. If LEDJ is tied to ground,
the output LEDP/S indicates multiple status conditions as shown in Figure 6.
On solid = Normal, 1 Blink = Link Down, 2 Blinks = Jabber, 5 Blinks = Polarity
Reversed

LEDT

0

Transmit LED Driver: Open drain driverforthe Transmit indicator LED. Output
is active during transmit.

LEDR

0

Receive LED Driver: Open drain driver for the Receive indicator LED. Output
is active during receive.

LEDC

0

Collision LED Driver: Open drain driverforthe Collision indicator LED. Output
is active when a collision occurs.

- -

7-7

I

SSI78Q902
Ethernet Twisted-Pair Media
Attachment Unit
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may damage the device.
PARAMETER

RATING

Supply Voltage, Vcc

-0.3 to 6

Operating Temperature, Top

a to +70

Storage Temperature, TST

UNIT
V
-----------~

°C

-65 to +150

°C

RECOMMENDED OPERATING CONDITIONS
PARAMETER

CONDITIONS

Supply Voltage 1 , Vcc
Operating Temperature, Top

MIN

NOM

MAX

4.75

5.0

5.25

UNIT
V

a

-

70

°C

NOM1

MAX

UNIT

1Maximum voltage differential between VCC1 and VCC2 must not exceed O.3V.
SWITCHING CHARACTERISTICS (Ta
PARAMETER
Jabber Timing

= a to 70°C, Vcc = 5V ±5%)
MIN

CONDITIONS

Maximum transmit time 2

98.5

Unjab time 2

491

-

a

-

Time from Jabber to
3
CSO on CIP/CIN

131

ms

525

ms

900

ns

--_ ...

_.. _-- ------------

Link Integrity Timing
Time link loss 2

65

-

Time between Link
Integrity Pulses 2

9

-

4.1

-

66
~-.--

- -

Interval for valid receive
Link Integrity Pulses 2

t-

ms

11

ms

65

ms

---

------~~-'----.----

COllision Timing

---

a

-

300

-

-

-

CSO high pulse width

40

-

60
--- _._._--

CSO low pulse width

40

-

60

ns

-

10

-

MHz

Simultaneous TPIITPO to CSO
state on CIN/CIP

00 loopback to TPI on 01

ns

900

ns

900

ns

---

3

CSO state delay after TPIIOO idle

900

3

-

-------

CSO frequency

----

ns

1 Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production
testing.
2 Switcl:ling times reduced by a factor of 1024 during Test mode.
3 Parameter is guaranteed by design; not subject to production testing.
7-8

SSI78Q902
Ethernet Twisted-Pair Media
Attachment Unit
SWITCHING CHARACTERISTICS (Ta

=0 to 70°C, Vcc = SV ±S%) (continued)
MIN

NOM1

MAX

SOE signal duration

SOO

-

1S00

ns

Delay after last positive transition
of DO

0.6

-

1.6

~s

PARAMETER

CONDITIONS

UNIT

SQE Timing

------

LED Timing
LEDC, LEDT, LEDR on time 2
LEDP/S on

time 2

100

(See Figure 6)

LEDP/S period 2 (See Figure 6)

-

-

ms

-

164

-

ms

-

328

-

ms

--

General
Receive start-up delay

0

-

500

ns

Transmit start-up delay

0

-

200

ns

Loopback start-up delay

0

-

SOO

ns

1
2

Typical figures are at 2S °C and are for design aid only; not guaranteed and not subject to production
testing.
Switching times reduced by a factor of 1024 during Test mode.

1/0 ELECTRICAL CHARACTERISTICS (Ta

CONDITIONS

PARAMETER
Input low voltage 2
Input high

voltage 2

= 0 to 70°C, Vcc = SV ±S%)

VIL
VIH

= 2 kQ

MIN

NOM1

MAX

UNIT

-

-

0.8

V

2.0

-

-

V

-

-

0.13

V

Output low voltage
(Open drain LED DriverJ)

VOL

RLOAD

Supply current

Icc

Line Idle

-

60

69.3

rnA

Line Active,
transmitting all ones

-

125

140

rnA

(Vcc1

= Vcc2 = S.2SV)

--

--

Input leakage current4
Tristate leakage
current

ILL
ITS

Input between VCC and GND

-

±1

±10

~

Output between VCC
andGND

-

±1

±10

~

Typical figures are at 2SoC and are for desing aid only; not guaranteed and not subject to production
testing.
2 MOO, MD1, SOE, PRC and LI pins. MD1 clock (test mode) must be CMOS level input.
3 LED Drivers can sink up to 10 rnA of drive current.
4 Not including TPIN, TPIP, DOP or DON.
1

7-9

I

SSI78Q902
Ethernet Twisted-Pair Media
Attachment Unit

Link Fail

Jabber

Polarity
Reverse
1.9685

NOTE: LEDP/S status indications are shown in order of priority, i.e., Link Fail indication
supersedes Jabber indication which supersedes Polarity Reverse (when PRC = 1). Reversed
polarity conditions supersede Link Fail conditions when PRC = 0 (Polarity Correction
Disabled). At the LEDL indicator, reversed polarity condition reported as Link Fail when
PRC = O. This allows the user to distinguish between actual link failure and apparent link
failure due to polarity reversal.
FIGURE 6: LEDP/S Status Indication Timing

AUI ELECTRICAL CHARACTERISTICS (Ta
PARAMETER

= 0 to 70°C, Vcc = SV ±S%)

CONDITIONS

Input low current

IlL

Input high current

IIH

MIN

NOM1

MAX

UNIT

-

-

-700
SOO

f1A
f1A

±1200

mA

-1--

Differential output voltage

VOD

±SSO

-

Differential squelch
threshold

VDS

-

220

-

20

Receive input impedance
1

Rz

Between DOP and DON

- -

-

mV
-

kn

Typical figures are at 2SoC and are for design aid only; not guaranteed and not subject to production
testing.

7-10

SSI78Q902
Ethernet Twisted-Pair Media
Attachment Unit
TRANSMIT CHARACTERISTICS (Ta = 0 to 70°C, Vee = 5V ±5%)
CONDITIONS

PARAMETER

MIN

NOM1

MAX

UNIT

-

5

-

Q

±4.5

-

±5.2

V

After Tx filter, 0 line length

-

-

±8

ns

After Tx filter, line model as
shown in IEEE 802.3
standard for 1OBase-T

-

-

±3.5

ns

-

20

-

kQ

Vos

-

420

-

mV

VOSR

-

300

-

mV

-

-

1.5

ns

Transmit output impedance

ZOUT

Peak differential output
voltage

Voo

Transmit timing jitter addition
Transmit timing jitter addition

2
2

load = 2000 at TPOP
and TPON

RECEIVE CHARACTERISTICS (Ta = 0 to 70°C, Vcc= 5V ±5%)
Receive input impedance
Differential squelch
threshold
Reduced squelch
threshold

ZIN

Between TPIP/TPIN

Receive timing jitte~

Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production
testing.
2 Parameter is guaranteed by design; not subject to production testing.
1

side of the AUI interface to prevent impedance mismatch with the drop cable. The half current drive mode
is used to maintain the same voltage levels in the
absence oftermination resistors. This application uses
capacitive coupling instead of transformer coupling.
MD1 is tied high so MDO functions as the mode control
switch.

APPLICATION INFORMATION
EXTERNAL MAU
Figure 7 shows the 551 780902 in a typical external
MAU application, interfacing between an AUI and the
RJ45 connectors of the twisted pair network. A 20 MHz
crystal (or ceramic resonator) connected across ClKI
and ClKO provides the required clock signal. Transmit and receive filters are required in the TPO and TPI
circuits. Details of the transmit and receive filters are
shown in Figures 8 and 9, respectively. (Differential
filters are also recommended.)

When MDO is low, the half current drive mode is
selected. When MDO is high, the 551 780902 is
effectively removed from the circuit. The 902 AUI ports
(DO, DI and CI) are disabled isolating the 551 780902
from the AUI. The 551 780902 DI and CI ports go to
a high impedance state and the DO port is ignored.

INTERNAL MAU
To implement an auto-select function, lEDl can be
tied to MDO. This activates the 902/AUI interface when
the TP link is active (data or link integrity pulses) and
disables it when the link is inactive.

Figure 10 shows an internal MAU application which
takes advantage of the 551 780902's unique AUII
10Base-T switching feature to select either the Dconnector (AUI) or the RJ45 connector (10Base-T).
No termination resistors are used on the 551 780902

7-11

I

SSI78Q902
Ethernet Twisted-Pair Media
Attachment Unit

~

~

C1

C2

CLKI

CLKO

AUI

TPOP

DOP
78n.

TPON
DON

To/From
Data
Terminal
Equipment

: RJ45

DIN
CIP
78n.

CIN

To/From
Network

TPIP

DIP
78n.

Twisted Pair

N
0

TPIN

0)

"
CO
I'-

LEDJ
LEDC
LEDT
LEDR
LEDL

+5~

VCC1
VCC2
PRC
SQE
LI

LEDP/S
RBIAS

12.4 kn±l%

MOO
MD1
GND1
GND2
0.1 F
1.0 FTantalum

ill Typically, resistors on the AUI side of the transformer are already present in the terminal.
If termination resistors are present in the terminal, the shaded resistors are not required .

..&. A 20 MHz (±1 %) crystal or ceramic resonator may be used at CLKI/CLKO.
£ Suitable integrated filter/transformers include TDK Corporation HIM 3000, Pulse Engineering
PE65421, FilMag 78Z1120B and Valor PT3877.

FIGURE 7: SSI 78Q902 External MAU Application Diagram

7-12

SSI78Q902
Ethernet Twisted-Pair Media
Attachment Unit

T

I

I

T

T

FIGURE 8: Transmit Filter Diagram

T

FIGURE 9: Receive Filter Diagram

D-Connector

20 MHz

D

ENCODER!
DECODER

-

t-:L
-

C1

C2

CLKI
8023
8391
7991

CLKO
TPOP

DOP

TPON
DON
RJ45
TPIP
DIP

To/From
Controller

DIN

N
0

TPIN

0

LEDJ

.......

LEDC

m
CO

CIP
CIN

I

LEDT
LEDR

PRC
LEDL

VCC1
VCC2

LEDP

LI

RBIAS

SQE
Activate
MAU

&

I

I
I
I
I

12.4kO±1%

GND1

MD1
MOO

GND2
1 f!FTantalum
0.1 f!F

!... ______________

J

& Connect LEDL to MDO to implement auto-select feature.
FIGURE 10: SSI78Q9021nternai MAU Application Diagram
7-13

Twisted Pair
To/From
Network

SSI78Q902
Ethernet Twisted-Pair Media
Attachment Unit
PACKAGE PIN DESIGNATIONS

CAUTION: Use handling procedures necessary
for a static sensitive component.

(Top View)

DON

lEDC

DOP

lEDR

lEDJ

lEDT

""")

lEDP/S

lEDl

2

....J

28

27 26

0

W

....J

GND2
VCC2

22

TPON

GND1

21

VCC1

CIN

20

RBIAS

CIP

19

MD1

ClKI

CIN

VCC1

CIP

RBIAS

TPIN

3

....J

w

23

TPON

TPIP

4

I0

....J

a::
w

24

GND1

LI

0

0

w

PRC

VCC2

DIP

0

~

a..

0

()

ClKO

GND2

ClKI

SQE

0

TPOP

ClKO

DIN

....J

z

0

25

TPOP

MD1

a..

w

LEDl

PRC

MDO

0

12 13
0

0

::!

28-Pin DIP

z
0

14

15 16 17 18

a..

::J

0

z
a: a
a: Ia..

w

(f)

l-

28-Pin PLCC

ORDERING INFORMATION
PART DESCRIPTION

ORDER NO.

PKG.MARK

881780902 28-Pin DIP
881 780902 28-Pin PLCC

780902-CP
780902-CH

780902-CP
780902-CH

No r~sponsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other
rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems.
Silicon Systems reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the data sheet is current before placing orders.

Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX (714) 573-6914

©1991 Silicon Systems, Inc.

7-14

1292 - rev.

5S178Q8373
3V, 5V PCMCIA
Ethernet Combo

January 1995

DESCRIPTION

FEATURES
Single-chip solution for 10Base-T/PCMCIA
designs
Operation at 3.3V or 5V
Pin-compatible with SSI 7808370
Integrated 10Base-T transceiver:
Programmable/automatic selection of
twisted pair (RJ45) or AUI port
Receive polarity detection/correction on
twisted-pair inputs
Manchester Encoder/Decoder circuit
AUI port for connection to 10Base2/S
transceiver or AUI cable
Integrated bus interface compliant with
PCMCIA release 2.1 specification
Bus interface can be bypassed for nonPCMCIA applications
Protocol Controller compliant with IEEE 802.3
and Ethernet 2.0
Advanced Buffer Manager architecture:
Automatic management of all pointers
Allows "simultaneous" access to data in
buffer memory by both the network and host
High-speed received packet skip
Configurable Buffer Memory for design
flexibility:
Two-bank transmit buffer in 2, 4, 8, or 16
Kbyte sizes
Ring-structure receive buffer from 4 to 62
Kbytes
Software-configurable system bus structure:
Compatible with major microprocessors
8- or 16-bit wide data path communications
with hosts
Power management options:
Intelligent power mode automatically
shuts off unused circuitry
Standby mode reduces power while not in
operation
Full shutdown mode offers maximum
power savings
Available in 100-lead QFP and TOFP packages

The SSI7808373 is a highly integrated Ethernet IC for
use in PCMCIA (Personal Computer Memory Card
International Association) applications and can
operate with a power supply of 3.3V or 5V. It contains
a Media Access Controller (MAC), a 10 Mbitls
Manchester encoder/decoder (ENDEC), a 10Base-T
transceiver, a memory-card bus interface (PCMCIA),
and an Attachment Unit Interface (AUI). This level of
integration allows the user to implement a PCMCIA
card for 10Base-T using only the SSI 7808373,
external memory, and some passive components. The
internal bus interface circuit allows connection to a
PCMCIA 2.1 bus without other external components.
The PCMCIA bus-decoding logic can be bypassed for
connection to other bus types. The SSI 7808373
connects to twisted-pair media via line transformers
through the on-chip transceiver circuit. Connection to
other media such as coaxial cable is made through the
AUI port to an external transceiver, such as the SSI
7808330 Ethernet Coax Transceiver.
The SSI 7808373 has a sophisticated power
management capability with three different operating
modes allowing the user to maximize power savings,
making it ideal for use in PCMCIA applications. During
normal operation, the IC monitors its own actions and
shuts down the circuits that are not being used,
resulting inthe lowest possible operating power. It also
has a standby mode which leaves only the oscillator
running, and a full shutdown mode which also turns off
the oscillator.
An intelligent Buffer Manager is controlled by the host
read, host write, receive and transmit pointers, and the
SSI 7808373 manages the pointers internally without
any host intervention. The device interleaves access to
the buffer memory so that accesses from the host and
from the network media seem to operate concurrently.
Big and little endian byte orderings make for simple bus
interface to all standard microprocessors.
The SSI 7808373 is available in both a 1OO-Iead OFP
and thin OFP (TOFP) packages, and can operate with
a power supply of 3.3 volts or 5 volts.

0195 - rev

7-15

7

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
FUNCTIONAL DESCRIPTION

• Buffer Manager (and SRAM Interface)

is being transmitted, the host can continue to load
packets in the second transmit bank. At this stage, the
8373 can potentially be receiving data from the mediu m
and loading it into the receive buffer (if the 8373 is in a
loop back mode or if self-reception occurs).

• Data Link Controller

DATA LINK CONTROLLER

• HosVPCMCIA Interface

The Data Link Controller (DLC) implements the ISOI
ANSI/IEEE 8802-3 CSMA/CD protocol. It consists of a
Transmitter, a Receiverand CRC logic (which is shared
by both transmit and receive operations). Automatic
generation and stripping of the 64-bit preamble and the
32-bit CRC code are provided on-chip.

The 78Q8373 consists of six major blocks as shown in
Figure 1.

• Manchester ENDEC
• Twisted Pair Transceiver
• Power Management
BUFFER MANAGER

HOST/PCMCIA INTERFACE

The Buffer Manager manages all accesses to the
buffer memory through the SRAM interface. The buffer
memory is connected directly to the Data Link Controller
(DLC), thus eliminating the need for a local
microprocessor. The Buffer Manager also keeps track
of all buffer memory pOinters automatically, simplifying
the software driver task. Together with intelligent
arbitration, this makes the 8373 a high performance
LAN controller.

The Host Interface (HIF) provides connection to the
host system. It consists of the various registers, DMA
circuits and ready logic. Both word and byte interfaces
are supported as well as big endian and little end ian
data ordering. Host access to the buffer memory is
through BMR8 (and BMR9).Reading from BMR8 will
read a byte or word from the receive buffer and writing
to BM R8 will write a byte or word to the transmit buffer.
The ready logic is capable of delaying host access to
the buffer memory with a time-out mechanism. Both
single and burst DMA transfer modes are supported.

The buffer memory is divided into two portions: transmit
memory portion and receive memory portion. The
transmit memory portion can be partitioned into 2K, 4K,
8K or 16 Kbyte buffer sizes. There is only one transmit
bank if a 2 KB transmit buffer size is selected. If the
transmit buffer size is greater than 2 KB, then the
transmit buffer is configured into two banks of equal
size. With the two bank configuration, one transmit
bank may be tied up during transmission but the host
can still continue to load data packets into the second
transmit bank to be transmitted later. The receive
buffer has a ring architecture which can be configured
from 4K to 62 KB depending on the buffer memory
configuration which has a range of 8K to 64 KB.

The PCMCIA interface circuitry builds on top of the
8373 generic host interface and is only active if the
MODE pin is left unconnected (internally pulled-up).
The 8373 can thus connect directly to a PCMCIA
release 2.1 compliant bus. It also supports decoding for
the external CIS memory (both ROM and Flash types).
The 8373 pinout has been defined to minimize crisscros~ing connections to the PCMCIA connector. This
allows for a cost effective 2-layer PCB design.
MANCHESTER ENDEC

This block implements Manchester encoding and
decoding. Serial NRZ data from the DLC is converted
to Manchester encoded data and sent to either the
twisted-pair transceiver block or to the Attachment Unit
Interface (AUI) driver, depending on which block is
active. The decoder section performs three functions:
clock recovery, carrier detection and Manchester
decoding. The recovered receive clock will be low at
the end of reception and during idle to save power.
Jitter of up to ±18 ns can be tolerated by the decoder.
This block also translates a 10 MHz collision signal to
a logic-level Signal before sending it to the DLC block
if the AUI port is selected.

A central arbitrator inside the Buffer Manager prioritizes
and services requests for access to the buffer memory
from 4 sources: the Transmitter, the Receiver, Host
Read and Host Write. If necessary, the 8373 will assert
a 'not ready' handshake to the host while servicing the
Transmitter andlor Receiver. The 8373 arbitration
mechanism provides packet management by
interleaving packet data accesses to the buffer memory
such that the operations appear to be simultaneous.
For instance, in the situation where 2 transmit banks
are configured, the host can load the first transmit bank
and initiate a transmission. Wh ile the first transmit bank
7-16

551 78Q8373
3V, 5V PCMCIA
Ethernet Combo
TWISTED PAIR TRANSCEIVER

POWER MANAGEMENT

The on-chip Twisted Pair module consists of a number
offunctions.lt has a smart squelch circuitry to determine
valid data present on the differential receive inputs
TPIP/TPIN. Its transmit and pre-distortion drivers
connect to the twisted pair network via the summing
resistors and transformer/filter. The link detector/
generator circuitry checks the integrity of the cable
connecting the two twisted pair MAUs. Collision, jabber
and SQE are also incorporated.

One very useful and important feature that the 8373
offers is intelligent power management. It supports
three different power saving modes: Intelligent, Standby,
and Full Shutdown. All modes are configurable through
registers. In the Intelligent mode, clocks are active only
when they are needed. For example, when not
transmitting, the clock supplied to the transmitter circuit
in the OLC block is not active while host read from
buffer memory may be active. In Standby mode, the
oscillator clock is disconnected from the rest of the
circuits, so that only the oscillator circuits draw power.
Full Shutdown turns off the OSCillator, resulting in
maximum power savings. Note that this mode is not
available when using an external clock source.

78Q8373

SRAM
Interface
10BaseT
Transceiver

f-----

Host!
PCMCIA
Interface

Buffer
Manager

Data Link
Controller

Manchester
ENDEC

Power
Management

AUI
Port

Transmission
Medium

PCMCIA
Bus

FIGURE 1: System Diagram

7-17

I

551 78Q8373
3V, 5V PCMCIA
Ethernet Combo
Pin Assignment Table - PCMCIA Bus Mode - 100-Pln TQFP
PIN# PIN NAME TYPE

PIN# PIN NAME TYPE

1

D1

104

26

OE

PIN# PIN NAME TYPE

PIN# PIN NAME TYPE

I

51

RA4

04

76

DON

AO

2

D8

104U

27

WE

I

52

RA5

04

77

DOP

AO

3

DO

104

28

INPACK

04

53

RA6

04

78

AGND

P
R

4

AO

I

29

REG

I

54

GND

P

79

REXT

5

A1

I

30

ROMG

04

55

VDD

P

80

AVDD

P

6

A2

I

31

FCE

04

56

RA7

04

81

TPIN

AI

04
04

57

RA12

04

82

TPIP

AI

58

RA14

04

83

MODE

TI

P

59
60

RWE
RA13

04
04

84
85

DIN
DIP

AI
AI

7

A3

I

32

XPD

8

RESET

SI

33

XRST

9
10

VDD

34

GNO

P
P

35

GND
ROO

104U

11

10WR

I

36

R01

104U

61

RA8

04

86

CIN

AI

12

lORD

I

37

RD2

104U

62

RA9

04

87

CIP

AI

13

CE2

I

38

R03

104U

63

RA11

04

88

GNO

P

14

015

104U

39

R04

104U

64

ROE

04

89

SPKRIN

SI

15

CE1

I

40

R05

104U

65

RA15

04

SPKR

08
I

16

D14

104U

41

R06

104U

OSCI

CI

17

07

104

42

R07

104U

66
67

90
91

OSCO

0

92

RRST

04

18

GND

P

43

GNO

P

68

VOO

P

93

lEOlT

0016

CCRA

19

D13

104U

44

RCSO

04

69

GND

P

94

CB

04

20

06

104

45

RCS1

04

70

GND

P

95

10lS16

04

21
22
23
24
25

D12
05
011
04
03

104U
104
104U
104
104

46
47
48
49
50

RA10
RAO
RA1
RA2
RA3

04
04
04
04
04

71
72
73
74
75

TPON
TPOP
TPON
TPOP
VOD

AO
AO
AO
AO
P

96
97
98
99
100

IREO
WAIT
010
02
09

08
04
104U
104
104U

legend:
I:
04,08:
0016:
104, 104U:
CI:
SI:
TI:
AI:
AO:
P:
R:
0:

Input (TTL level)
Output with 10l = 4 or 8 rnA
Output Open Drain with 10l = 16 rnA
Input (TTL level) and Output with 10l = 4 rnA; 104U refers to 104 with an internal pull-up resistor
CMOS level input
Schmitt trigger input
Three-state input. May be connected to low, high, or left open.
Analog input
Analog output
Power
Resistor to ground
Output
7-18

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
Pin Assignment Table - PCMCIA Bus Mode -100-Pln QFP
PIN# PIN NAME TYPE PIN#

PIN NAME TYPE PIN# PIN NAME TYPE PIN#

PIN NAME TYPE

1

D10

104U

26

D11

104U

51

RA1

04

76

TPON

AO

2

D2

104

27

D4

104

52

RA2

04

77

TPOP

AO

3

D9

104U

28

D3

104

53

RA3

04

78

VDD

P

4

D1

104

29

OE

I

54

RA4

04

79

DON

AO

5

D8

104U

30

WE

I

55

RA5

04

80

DOP

AO

6

DO

104

31

INPACK

04

56

RA6

04

81

AGND

P

R

7

AO

I

32

REG

I

57

GND

P

82

REXT

8

Ai

I

33

ROMG

04

58

VDD

P

83

AVDD

P

9

A2

I

34

FCE

04

59

RA7

04

84

TPIN

AI
AI

10

A3

I

35

XPD

04

60

RA12

04

85

TPIP

11

RESET

SI

36

XRST

04

61

RA14

04

86

MODE

TI

12

VDD

P

37

GND

P

62

RWE

04

87

DIN

AI

13

GND

P

38

RDO

104U

63

RA13

04

88

DIP

AI

14

10WR

I

39

RD1

104U

64

RA8

04

89

CIN

AI

15

lORD

I

40

RD2

104U

65

RA9

04

90

CIP

AI

16

CE2

I

41

RD3

104U

66

RA11

04

91

GND

P

17

015

104U

42

RD4

104U

67

ROE

04

92

SPKRIN

SI

18

CE1

I

43

RD5

104U

68

RA15

04

SPKR

08
I

19

D14

104U

44

RD6

104U

69

OSCI

CI

93
94

20

D7

104

45

RD7

104U

70

OSCO

0

95

RRST

04

21

GND

P

46

GND

P

71

VDD

P

96

LEDLT

OD16

22

D13

104U

47

RCSO

04

72

GND

P

97

CB

04

23

D6

104

48

RCS1

04

73

GND

P

98

101816

04

24

D12

104U

49

RA10

04

74

TPDN

AO

99

IREO

08

25

D5

104

50

RAO

04

75

TPDP

AO

100

WAIT

04

CCRA

Legend:
I:
04, 08:
OD16:
104, 104U:
CI:
SI:
TI:
AI:
AO:
P:

R:
0:

Input (TTL level)
Output with 10L = 4 or 8 mA
Output Open Drain with 10L = 16 mA
Input (TTL level) and Output with 10L = 4 mA; 104U refers to 104 with an internal pull-up resistor
CMOS level input
Schmitt trigger input
Three-state input. May be connected to low, high, or left open.
Analog input
Analog output
Power
Resistor to ground
Output
7-19

I

551 78Q8373
3V, 5V PCMCIA
Ethernet Combo
Pin Assignment Table - Generic Bus Mode -100-Pln TQFP
PIN#

PIN NAME TYPE

5
6
7

HD1
HD8
HDO
HAO
HA1
HA2
HA3

104
104U
104
I
I
I
I

1
2
3
4

PIN# PIN NAME TYPE

PIN# PIN NAME TYPE

104U
104U
104U
104U
104U
104U
104U

51
52
53
54

30
31
32

RD8
RD9
RD10
RD11
RD12
RD13
RD14

55
56
57

RA4
RA5
RA6
GND
VDD
RA7
RA12

26
27
28
29

PIN# PIN NAME TYPE

04
04
04
P
P
04
04

76
77
78
79
80
81
82

DON
DOP
AGND
REXT
AVDD
TPIN
TPIP

AO
AO
P
R
P
AI
AI

8

RESET

SI

33

RD15

104U

58

RA14

04

83

MODE

TI

9
10

VDD

34
35

GND
ROO

P
I04U

59
60

RWE
RA13

04
04

84

GND

P
P

85

DIN
DIP

AI
AI

11

WR

I

36

RD1

I04U

61

RA8

04

86

CIN

AI
AI

12

RD

I

37

RD2

104U

62

RA9

04

87

CIP

13

SHE

I

38

RD3

104U

63

RA11

04

88

GND

P

14

HD15

104U

39

RD4

104U

64

ROE

04

89

DMACK

SI

15
16
17

CS
HD14
HD7

I
104U
104

65
66
67

RA15
OSCI

04
CI

104U

68

0
P

DMREQ
EOP
RRST

P

OSCO
VDD

90
91
92

GND

RD5
RD6
RD7
GND

104U
104U
104U

18

40
41
42
"43

93

LEDLT

08
I
04
0016

19

HD13

104U

44

RCSO

P

69

GND

P

94

CS

04

20

HD6

104

45

RCS1

04

70

GND

P

95

HWORD

04

21

HD12

46

RA10

04

71

HD5
HD11

47
48

RAO
RA1

04
04

72
73

TPDN
TPDP
TPON

AO
AO
AO

96
97
98

INT

22
23

104U
104
104U

READY
HD10

24
25

HD4
HD3

104
104

49
50

RA2
RA3

04
04

74
75

TPOP
VDD

AO
P

99
100

HD2
HOg

08
04
104U
104
104U

Legend:
I:
04,08:
0016:
104, 104U:
CI:
SI:
TI:
AI:
AO:
P:
R:
0:

Input (TTL level)
Output with IOL = 4 or 8 rnA
Output Open Drain with 10L = 16 rnA
Input (TTL level) and Output with 10L = 4 rnA; 104U refers to 104 with an internal pull-up resistor
CMOS level input
Schmitt trigger input
Three-state input. May be connected to low, high, or left open.
Analog input
Analog output
Power
Resistor to ground
Output
7-20

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
Pin Assignment Table - Generic Bus Mode -100-Pin QFP

PIN# PIN NAME TYPE

PIN# PIN NAME TYPE

1
2
3
4

HD10
HD2
HD9
HD1

104U
104
104U
104

5
6
7

HD8
HDO
HAO

104U
104
I

8
9

HA1
HA2

I
I

33
34

10
11

HA3
RESET

I
SI

12
13

VDD
GND

14

HD11
HD4
HD3
RD8

PIN# PIN NAME TYPE

104U

58

104U

59

RA7

04

83
84

AVDD

RD13

TPIN

P
AI

35
36

RD14
RD15

104U
104U

60
61

RA12
RA14

04
04

85
86

TPIP
MODE

AI
TI

P
P

37
38

GND
ROO

P
104U

62

RWE
RA13

04
04

87

63

88

DIN
DIP

AI
AI

WR

I

39

RD1

104U

64

RA8

04

89

CIN

AI

15

RD

I

40

RD2

104U

65

RA9

04

90

CIP

AI

16

BHE

I

41

RD3

104U

66

RA11

04

91

GND

P

17

HD15

104U

42

RD4

104U

67

ROE

04

92

DMACK

SI

18
19
20

I

43
44
45

RD5
RD6
RD7

104U
104U
104U

GND

P

93
94
95
96

EOP
RRST
LEDLT

08
I
04

46

OSCI
OSCO
VDD

04
CI
0
P

DMREQ

P

68
69
70
71

RA15

104U
104

21

CS
HD14
HD7
GND

0016

22

HD13

104U

47

RCSO

04

72

GND

P

97

CB

04

23

HD6

104

48

RCS1

04

73

GND

P

98

HWORD

04

49

RA10

50

RAO

04
04

74

TPDN
TPDP

AO
AO

99
100

INT
READY

08
04

HD12

25

HD5

104U
104

RD9
RD10
RD11
RD12

104U
104
104
104U
104U
104U
104U

51
52
53
54
55
56
57

75

04
04
04
04
04
04
P

PIN# PIN NAME TYPE

RA1
RA2
RA3
RA4
RA5
RA6
GND
VDD

24

26
27
28
29
30
31
32

P

76
77

78
79
80
81
82

TPON
TPOP
VDD
DON
DOP
AGND
REXT

AO
AO
P
AO
AO
P
R

Legend:
I:
04, 08:
0016:
104, 104U:
CI:
SI:
TI:
AI:
AO:
P:
R:
0:

Input (TTL level)
Output with 10L = 4 or 8 rnA
Output Open Drain with 10L = 16 mA
Input (TTL level) and Output with 10L = 4 rnA; 104U refers to 104 with an internal pull-up resistor
CMOS level input
Schmitt trigger input
Three-state input. May be connected to low, high, or left open.
Analog input
Analog output
Power
Resistor to ground
Output
7-21

I

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
PIN DESCRIPTION
HOST BUS INTERFACE· PCMCIA BUS MODE
NAME

TYPE

RESET

I

HARDWARE RESET. Active high. A minimum pulse length of 800 ns is
required. This pin resets the 8373's internal pointers and registers to their
appropriate states. It also clears the CI (Configuration Index) in the CCR (Card
Configuration Register), thus placing the 8373 in an unconfigured (Memoryonly Interface) state. The 8373 remains in the unconfigured state until the CI
has been written with a non-zero value.

IOWR

I

liD WRITE. The IOWR pin is an active low input that enables a write operation
by the host to the 8373 internal registers as selected by the host address inputs
A[0:3]. The REG and at least one of CE1 or CE2 must be also active for the
liD write to take place. The 8373 will not respond to the IOWR signal until it has
been configured for liD operation by the host.

lORD

I

1/0 READ. The lORD pin is an active low input that enables a read operation
by the host from the 8373 internal registers as selected by the host address
inputs A[0:3]. The REG and at least one of CE1 or CE2 must be also active for
the liD read to take place. The 8373 will not"respond to the lORD signal until
it has been configured for liD operation by the host.

CE1, CE2

I

CH I P ENABL E. Active low input signals acting as chip select for the 8373. CE 1
enables even-numbered address bytes and CE2 enables odd-numbered
address bytes. When the 8373 is programmed to be in byte mode (DLCR6<5>
HBVTE bit is a "1"), CE2 is a don't care and only lower databus 0[0:7] is used
for data transfer. Combinations of CE1, CE2, AO and HBVTE bit (DLCR6<5»
are used to select the different modes of liD space wordlbyte transfer
according to the following table (the table assumes REG is activated):

DESCRIPTION

HBVTE

CE2

CE1

AO

0[15:8]

0[7:0]

0

1

0

0

1

0

1

X
X

even-byte

0

0
1

0

odd-byte

even-byte

X

odd-byte

X

0

0

even-byte

0

1

X
X

0

0

0
1

0

1

X
X

odd-byte

odd-byte

For Attribute Memory access, data transfer occurs only on D[7:0] with the
following valid combinations only:
HBVTE
CCRA

I

DE

I

CE2

CE1

AO

0[15:8]

0[7:0]

X
even-byte
0
0
CARD CONFIGURATION REGISTER ADDRESS. This pin connects to
PCMCIA higher address bit. A high (together with REG activation) on this bit
selects the internal CCR registers and a low selects the external CIS (Card
Information Structure) ROMIFlash memory.
X

X

OUTPUT ENABLE. An active low input signal used to read data from the
internal CCR (Card Configuration Registers) and from the external Attribute
Memory (through the activation of FCE and ROMG). This OE should also
connect to the output enable of the external Flash Memory orthe ROM.
7-22

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
HOST BUS INTERFACE· PCMCIA BUS MODE
NAME

TYPE

(continued)

DESCRIPTION

WE

I

WRITE ENABLE. An active low input signal used to write data to the internal
CCR (Card Configuration Registers) and to the external Attribute (Flash)
Memory (through the activation of FCE). This WE should also connect to the
write enable of the external Flash Memory.

REG

I

ATTRIBUTE MEMORY SELECT. When this signal is active (low), it signifies
access from or to the Attribute Memory (OE or WE active) or the I/O space
(lORD or 10WR active). Attribute Memory is generally used to record card
capacity and other configuration and attribute information. This includes the
standardized CCRs (Card Configuration Registers) which are located internally in the 8373. When Attribute Memory is accessed, only data signals 0[0 :7]
are valid and signals 0[8:15) are ignored.

A[0:3)

I

ADDRESS BUS. Selects the set of 8373 internal registers including the CCR
(Card Configuration Registers) for read or write operations.

I/O

DATA BUS. A bi-directional, tri-state bus. The combinations of CE1 , CE2 and
AO control the portion of the bus that is being utilized. A[0:3) and RBNK1,0
(DLCR7<3:2» select the set of internal registers for access.

0[0:15)

HOST BUS INTERFACE· PCMCIA BUS MODE
The following output signals are inactive (high) until the 8373 is configured for I/O mode.
WAIT

0

WAIT. An active low output that is asserted to delay completion of the current
I/O read orwrite operation. It will also be used if the device is unable to respond
to read or write requests within 2.4I1S. In these situations, the 8373 will also
assert IREO and the host read error status bit (DLCR1 <6» or host write error
status bit (DLCRO register
bit. This allows a software controlled hardware reset of the 8373 and the rest
of the devices residing on the same card.

I

SPEAKER IN. This pin is qualified with the AUDIO bit, CCR1<3> to produce
the inverted SPKR output.

SPKRIN

DESCRIPTION

7-24

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
HOST BUS INTERFACE· GENERIC BUS MODE
NAME

TYPE

RESET

I

HARDWARE RESET. Active high. A minimum pulse length of 800 ns is
required. This pin resets the 8373's internal pOinters and registers to their
appropriate states. Note: the 8373 must be reset after power on before usage.

READY

0

READY. This output is asserted to indicate to the host that the 8373 is ready
to complete the requested read or write operation. It will also be used if the
device is unable to respond to read or write requests within 2.4 IlS. In these
situations, the 8373 will also assert INT and the host read error status bit
(DLCR1 <6» or host write error status bit (DLCRO <0». The polarity of the
READY pin is determined by the MODE pin.

WR

I

WRITE. The WR pin is an active low input that enables a write operation from
the host to the 8373's internal registers as selected by the host address inputs
HA[0:3].

RD

I

READ. The RD pin is an active low input that enables a read operation by the
host from the 8373's internal registers as selected by the host address inputs
HA[0:3].

CS

I

CHIP SELECT. An active low input signal as the chip select for the 8373.

BHE

I

BYTE HIGH ENABLE. This is an active low byte/word control pin used only
when the 8373 is configured for word transfer by HBYTE bit (DLCR6 <5».
Combinations of BHE and HAO are used to select word, upper byte only or
lower byte only transfers.

DESCRIPTION

HBYTE

BHE

HAO

0

0

0

Word transfer

0

0

1

Byte transfer on high bus HD[8:15].

0

1

0

Byte transfer on low bus HD[0:7].

0

1

1

Reserved

1

X

X

Byte transfer (HD[O :7])

FUNCTION

INT

0

INTERRUPT. This active low signal is asserted when the 8373 requires the
intervention of the Host in situations as depicted in DLCRO, 1 and BMR15. The
INTsignal is masked by writing a '0' to the respective interrupt enable register.

EOP

I

END OF PROCESS. Asserted at the end of a DMA transfer by the Host DMA
controller. Further DMA requests (DMREQ) will be discontinued after EOP is
asserted. Polarity can be selected via the register bit (DLCR7 <1».

0

DMA REQUEST. The 8373 issues a DMREQ to the Host DMA controller to
initiate a write to its transmit buffer or a read from its receive buffer.

DMREQ

7-25

I

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
PIN DESCRIPTION (continued)
HOST BUS INTERFACE· GENERIC BUS MODE
NAME

TYPE

DESCRIPTION

DMACK

I

DMA ACKNOWLEDGE. An active low signal issued by the Host DMA
controller when it is ready to pe~orm data transfers between the Host and the
8373's buffer memory via BMR8.

HA[0:3]

I

HOST ADDRESS. Selects the set of internal registers to be accessible by the
8373 for read or write operations.

HD[0:15]

I/O

HOST DATA BUS. A bi-directional, tri-state bus for data, command and status
transfers between the Host and the 8373 with the direction being controlled by
RD and WR. The combinations of HBYTE, BHE and HAO control the portion
of the bus that is being utilized. HA[0:3] and RBNK <0:1> (DLCR7 <2:3»
select the set of internal registers for access.

HWORD

0

HOST WORD CONFIGURATION. This pin is the complement of the register
bit HBYTE (DLCR6<5».lf HBYTE is a '0', the Host interface is configured for
word transfers. If HBYTE is a '1', the Host interface is configured for byte
transfers on the lower bus, HD[0:7].

BUFFER MEMORY INTERFACE
RCSO, RCS1

0

RAM CHIP SELECT. RCSO and RCS1 are active low chip select lines forthe
SRAM with RCSO as the least significant byte.

ROE

0

RAM OUTPUT ENABLE. Active IQw. This is the output enable asserted by the
8373 during buffer memory read cycles for the SRAM.

RWE

0

RAM WRITE ENABLE. Active low. This is the write enable asserted by the
8373 during buffer memory write cycles for the SRAM.

RD[0:15)

I/O

RAM DATA BUS. This is the data bus between the 8373 and the buffer memory.
It can be configured for byte or word transfer depending on register bit RBYTE
(DLCR6 <4» RAM BYTE. For word transfers, the ordering of the most and
least significant byte is defined by the register bit, INTLMOT (DLCR7 <0». In
PCMCIA bus mode, this data bus is only 8 bits wide (RD[0:7]).

RA[0:15]

0

RAM ADDRESS BUS. Addresses up to 64 KByte of SRAM buffer memory.

NETWORK ATTACHMENT UNIT INTERFACE

0

TRANSMIT DATA NEGATIVE and POSITIVE. Differential outputs to external
transceiver for transmission.

DIN, DIP

I

RECEIVE DATA NEGATIVE and POSITIVE. Manchester differential inputs
from external transceiver for reception.

CIN,CIP

I

COLLISION DETECT NEGATIVE and POSITIVE. When an externally connected transceiver detects a collision on the medium, these differential inputs
are driven by a 10M Hz signal.

REXT

-

EXTERNAL R~SISTOR. External biasing resistor. Connect to 20 kn ±1 % to
AGND.

DON,DOP

7-26

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
NETWORK TWISTED-PAIR MEDIUM INTERFACE
NAME

TYPE

DESCRIPTION

TPON, TPOP

0

TWISTED-PAIR OUTPUT NEGATIVE and POSITIVE. Driver outputs to
twisted-pair medium. Must be summed together with TPDN and TPDP by
external resistors in a pre-equalization network to produce twisted-pair transmit signal.

TPDN, TPDP

0

TWISTED-PAIR DELAYED NEGATIVE and POSITIVE. Delayed (50 ns)
driver outputs to twisted-pair medium. Must be summed together with TPON
and TPOP by external resistors in a pre-equalization network to produce
twisted-pair transmit signal.

TPIN, TPIP

I

TWISTED-PAIR INPUT NEGATIVE and POSITIVE. Inputs from twisted-pair
medium.

VDD

P

POWER SUPPLY. A +5V DC (±5%) or +3.3 VDC (±0.3V) supply is required.

GND

P

SYSTEM GROUND.

AVDD

P

ANALOG VDD. The analog VDD pin required by the internal AUI and twistedpair circuits is to be connected to a different VDD path from the digital VDD.
A +5V DC (±5%) or +3.3 VDC (±0.3V) supply is required.

AGND

P

ANALOG GROUND. The analog ground required by the internal encoder/
decoder is to be connected to a separate GND path from the digital GND.

DEVICE POWER

CRYSTAL OSCILLATOR
OSCI

I

OSCILLATOR IN. Connection for one side of the 20 MHz crystal or an input
for an external 20 MHz clock source.

OSCO

0

OSCILLATOR OUT. Connection for other side of the 20 MHz crystal. Left
unconnected if an external clock is used.

CB

0

CONTROL BIT. A complement of the internal register bit, DLCR4 <2>, which
is used to activate any external hardware.

RRST

0

REMOTE RESET. This pin follows the RMTRST register bit (DLCR1 <4».
The RMTRST bit is '1' only if a packet with the pattern 0900H in the Type Field
is detected and ENA_RMTRST (DLCR5 <2» is activated. This feature can be
used by the nodes on the network to remotely-control external hardware.

MODE

I

MODE SELECT. Tied high to select Generic bus mode with active high
READY timing. Tied low to select Generic bus mode with active low READY
timing. Left open to select PCMCIA bus mode (it will be internally pulled up).

LEDLT

0

LED LINK, TRANSMIT. Connect to LED with current limiting resistor to VDD.
LED is on during link up and off during link down. During link up (when LED is
on), a transmission will blink off the LED temporarily to indicate activity. This
feature is available for both twisted pair and AUI interfaces.

MISCELLANEOUS

7-27

I

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation beyond the maximum ratings may damage the device.
PARAMETER

RATING

Supply voltage, Vdd

-0.5 to 6.0V

Input voltage, Yin

-0.5 to Vdd + 0.5V

Output voltage, Vout

-0.5 to Vdd + 0.5V

Storage temperature, Tstg

-55 to 150°C

Lead temperature (max 10 sec soldering), TI

250°C max

DC CHARACTERISTICS (Ta

= 0 to 70°C, Vdd = 5V ±5%, 5V Values)

PARAMETER
Low level input voltage

High level input voltage

CONDITIONS
Vii

Vih

MIN

NOM

MAX

UNIT

TTL inputs

0.8

V

osel pin

1.6

V

Schmitt inputs

1.1

V

TTL inputs

2.2

V

ascI pin

3.8

V

Schmitt inputs

3.5

Pull down current (RESET pin )Ipd

13

V
50

JJA

Low level output voltage

Vol

Rated 101

0

0.4

V

High level output voltage

Voh

Rated loh

2.4

Vdd

V

Low level output current
(with Vol

= OAV)

High level output current
(with Voh

101

loh

= 2AV)

Vdd

Pin type 08

Vdd = 5V

Power down supply
current

Idd

Ipwrdn

4

mA

8

mA

Pin type 0016 Vdd = 5V

16

mA

Pin types 04,
104,104U

Vdd = 5V

-4

mA

Pin type 08

Vdd

= 5V

mA

-8
-10

10

JJA

Fullyactive(1)

40

mA

Idle

30

mA

Osc. on

10

mA

Osc. off

100

JJA

Leakage current (input/output) II
Supply current

= 5V

Pin types 04,
104,104U

Note: (1) Fully active means 3 "simultaneous" operations: transmitting, receiving (through twisted-pair port)
and either host write or read.

7-28

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
DC CHARACTERISTICS (Ta

= 0 to 70°C, Vdd =3.3V ±0.3V, 3V Values)

PARAMETER
Low level input voltage

High level input voltage

CONDITIONS
Vii

Vih

MIN

MAX

UNIT

TIL inputs

0.8

V

OSCI pin

0.7

V

Schmitt inputs

0.4

V

TIL inputs

2

V

OSCI pin

2.1

V

Schmitt inputs

2.4

Pull down current (RESET pin) Ipd
Low level output voltage

Vol

High level output voltage

Voh

Low level output current
(with Vol

= O.4V)

High level output current
(with Voh

101

loh

= 2.4V)

Rated 101
Rated loh

Power down supply
current

Ipwrdn

28

0

0.4

2.4

Vdd

~
V

V

2.4

rnA

Vdd

9.8

Pin types 04,
104,104U

= 3.3V
= 3.3V
Vdd = 3.3V

4.9

Pin type 0016 Vdd

-1.5

rnA
rnA
rnA

Vdd

Pin type 08

Pin type 08
Idd

V

5

= 3.3V

Pin types 04,
104,104U

Vdd

= 3.3V

rnA

-3
10

~

Fully active(1)

28

Idle

20

rnA
rnA

Osc. on

6

rnA

Osc. off

100

~

-10

Leakage current (input/output) II
Supply current

NOM

Note: (1) Fully active means 3 "simultaneous" operations: transmitting, receiving (through twisted-pair port)
and either host write or read.

7-29

I

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
ELECTRICAL SPECIFICATIONS (continued)
AUI CHARACTERISTICS
(VDD = 5V ± 5%, 3.3 ± 0.3V, Vss

= OV, Ta = O°C to +70°C)

PARAMETER

CONDITIONS

MAX

UNIT

Low Output Voltage for DOP, DON
Vaol
RI = 780

Rext

= 20 kO

Vdd-1.5

Vdd-0.75

V

High Output Voltage for DOP, DON
Vaoh

Rext = 20 kQ
RI = 780

Vdd-0.55

Vdd

V

DOP, DON Output Current

Rext = 20 kO

8

14

mA

2.45
2.13

3.33
2.88

V

-300

-120

mV

RI = 780

-40

40

mV

Rext = 20 kO
RI = 780

620

1100

mV

75

0

MIN

NOM

lao
DIP, DIN, CIP, CIN Open Circuit
Valb
Input Voltage (bias)

Vdd = 5V ± 5%
Vdd = 3.3 ± 0.3V

DIP, DIN, CIP, CIN Diff Squelch
Threshold
Vasq
DOP, DON Diff Idle Output
Vadi
DOP, DON Diff Peak Output
Vadv
DOP, DON Output Resistance
Rao

7-30

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
TWISTED PAIR

(VDD

= 5V ± 5%, Ta = O°C to +70°C)

PARAMETER

MIN

CONDITIONS

NOM

MAX

UNIT

TPIP, TPIN Diff Input Resistance
Rti

3

TPIP, TPIN Open Circuit Input
Vtib
Voltage (bias)

2.45

3.33

V

-3.1

3.1

V

TPIP, TPIN Diff Input Voltage
Range
Vtiv

kQ

VDD = 5V

TPIP, TPIN Positive Squelched
Threshold
Vtps

Note 1

300

585

mV

TPIP, TPIN Negative Squelched
Threshold
Vtns

Note 1

-585

-300

mV

TPIP, TPIN Positive Unsquelched
Vtpu
Threshold

Note 2

180

mV

TPIP, TPIN Negative Unsquelched
Vtnu
Threshold

Note 2

-180

mV

TPIP, TPIN Positive Squelched
Threshold Long Distance Mode
Vltps

Note 1

120

300

mV

TPIP, TPIN Negative Squelched
Vltns
Threshold Long Distance Mode

Note 1

-300

-120

mV

TPIP, TPIN Positive Unsquelched
Threshold Long Distance Mode Vltpu

Note 2

100

mV

TPIP, TPIN Negative Unsquelched
Vltnu
Threshold Long Distance Mode

Note 2

-100

mV

TPOP, TPON High Output Voltage
Vtoh

1= 32 mA

TPOP, TPON Low Output Voltage
Vtol

1= 32 mA

TPDP, TPDN High Voltage
Vtdh

1= 16 mA

Vtdl

1= 16 mA

TPDP, TPDN Low Voltage
TPDP, TPDN Output Resistance

Rtd

Vddtp
-0.44

Vddtp

V

Vsstp

Vsstp
+0.44

V

Vddtp
-0.44

Vddtp

V

Vsstp

Vsstp
+0.44

V

27

n
n

13.5

TPOP, TPON Output ResistanceRto
Note 1: Sine wave at 2 MHz, 5 MHz and 7 MHz
Note 2: Sine wave: 5 MHz::; f::; 10 MHz

7-31

I

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
ELECTRICAL SPECIFICATIONS (continued)
TWISTED PAIR

(VOO

= 3.3 ± 0.3V, Ta = O°C to +70°C)

PARAMETER

CONDITIONS

MIN

NOM

MAX

UNIT

TPIP, TPIN Oiff Input Resistance
Rti

3

TPIP, TPIN Open Circuit Input
Voltage (bias)
Vtib

2.13

2.88

V

-2.2

2.2

V

TPIP, TPIN Oiff Input Voltage
Vtiv
Range

kQ

VOO = 3.3V

TPIP, TPIN Positive Squelched
Threshold
Vtps

Note 1

210

410

rnV

TPIP, TPIN Negative Squelched
Threshold
Vtns

Note 1

-410

-210

rnV

TPIP, TPIN Positive Unsquelched
Vtpu
Threshold

Note 2

130

rnV

TPIP, TPIN Negative Unsquelched
Threshold
Vtnu

Note 2

-130

rnV

TPIP, TPIN Positive Squelched
Threshold Long Distance Mode Vltps

Note 1

90

210

rnV

TPIP, TPIN Negative Squelched
Threshold Long Distance Mode Vltns

Note 1

-210

-90

mV

TPIP, TPIN Positive Unsquelched
Threshold Long Distance Mode Vltpu

Note 2

70

rnV

TPIP, TPIN Negative Unsquelched
Threshold Long Distance Mode Vltnu

Note 2

-70

rnV

TPOP, TPON High Output Voltage
Vtoh

1= 50 rnA

TPOP, TPON Low Output Voltage
Vtol

1= 50 rnA

TPOP, TPON High Voltage
Vtdh

1= 25 mA

Vtdl

1= 25 rnA

TPOP, TPON Low Voltage

VddTP
-0.3

VddTP

V

VSSTP

VSSTP
+0.3

V

VddTP
-0.3

VddTP

V

VSSTP

VSSTP
+0.3

V

TPDP, TPDN Output Resistance Rtd

12

Q

TPOP, TPON Output Resistance Rto

6

Q

Note 1: Sine wave at 2 MHz, 5 MHz and 7 MHz
Note 2: Sine wave: 5 MHz ~ f ~ 10 MHz

7-32

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
TRANSFORMER RATIO:
3.3V OPERATION

5V OPERATION

RX

TX

RX

TX

1:1

1:1

1:1.4 (step down)

1:1.4 (step down)

CCRA,
A[O:3]

OE ---t-....,

f 4 - - - - - t3 - - - - . - j

,----+-----

CCRA=O:

FCE ----+-------.

AOMG

_~_bt,

i -

1

I
1

CCRA = 1:
0[0:7] - - - - + - - - ( J
(FROM 8370)
1'--------+---'1

FIGURE 2: Attribute Memory Read Cycle (PCMCIA mode)

7-33

I

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
Unless otherwise stated, the following conditions apply to the remaining timing tables:
Ta = O°C to +70°C, Vdd = 5 ± 5%, Vdd = 3.3V ± O.3V

TABLE 1: Attribute Memory Read Cycle (PCMCIA mode) (Refer to Figure 2)
PARAMETER

CONDITIONS

MIN

NOM

MAX

UNIT

CCRA, A[O:3] Valid to OE low; t1
REG, CE1 low to OE low

0

ns

OE high to CCRA, A[O:3] invalid; t2
OE high to REG, CE1 high

0

ns

Vdd = 5V

30

ns

= 3.3V

35

ns

OE low pulse width

t3

Vdd
OE low to 0[0:7] valid

45

t4

OE high to 0[0:7] invalid
(data hold)

t5

OE low to FCE low

t6

OE high to FCE high

t7

10

ns

= 5V

25

ns

= 3.3V
= 5V
Vdd = 3.3V
Vdd = 5V
Vdd = 3.3V
Vdd = 5V
Vdd = 3.3V

35

ns

25

ns

35

ns

Vdd
Vdd

OE low to ROMG low
OE high to ROMG high

Vdd

t8
t9

ns

25

ns

35

ns

25

ns

35

ns

MAX

UNIT

TABLE 2: Attribute Memory Write Cycle (PCMCIA MODE) (Refer to Figure 3)
PARAMETER

CONDITIONS

MIN

NOM

CCRA, A[O:3] Valid to WE low; t1
REG, CE1 low to WE low

0

ns

WE high to CCRA, A[0:3] invalid; t2
WE high to REG, CE1 high

0

ns

WE low pulse width

= 5V
= 3.3V

Vdd

t3

Vdd

30

ns

35

ns

0[0:7] valid to WE high
(data setup)

t4

15

ns

WE high to 0[0:7] invalid
(data hold)

t5

10

ns

WE low to FCE low

ts

= 5V
= 3.3V
Vdd = 5V
Vdd = 3.3V
Vdd

Vdd
WE high to FCE high

t7

7-34

25

ns

35

ns

25

ns

35

ns

551 78Q8373
3V, 5V PCMCIA
Ethernet Combo

\;-------

CCRA, ~v
A[0:3] ~I\

-~ '\_----

~

/

1\

/
I'-t 2-

I'-t 1-

~

/

1\

/
t3

Ir-

\
CCRA =0:

FeE

--_.-

--

- - - - - ....-

---

J

1\

-

I--

t6

\

1\

t71I
i

(logic high)

4

t5-

CCRA= 1"

0[0:7]
(TO 8370)

FIGURE 3: Attribute Memory Write Cycle (PCMCIA mode)

I

7-35

551 78Q8373
3V, 5V PCMCIA
Ethernet Combo

\1
/\

A[0:3]

\1

/\

\

/

\

V

~t2·

.t1·

\

/

\

V

t3

1

\
\
-+-

j

-. t7 ~

f+-

t6

V

\

WAIT (a)

-

~

-T,
t4

i\

/

r-tsf4-

1

f\-/
WAIT (b)
-+-

(logic high)

t9 f+-

0[0:15]
(FROM 8370)
18-

I-t10 --

FIGURE 4: I/O Read Cycle (PCMCIA mode)

7-36

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
TABLE 3: 1/0 Read Cycle (PCMCIA mode) (Refer to Figure 4)
PARAMETER

MIN

CONDITIONS

NOM

MAX

UNIT

A[0:3] valid to lORD LOW;
t1
REG, CE1, CE2 low to lORD low

0

ns

lORD high to A[0:3] invalid;
t2
lORD high to REG, CE1, CE2 high

0

ns

= 5V

30

ns

= 3.3V
Vdd = 5V
Vdd = 3.3V

35

ns

lORD low pulse width

Vdd

t3

Vdd
lORD low to WAIT low

lORD low to WAIT high(1)
lORD low to INPACK low

t4

Port busy (a)

t5

Port busy (a)

t6

= 5V
= 3.3V
Vdd = 5V
Vdd = 3.3V
Register access (b) Vdd = 5V
Vdd = 3.3V

0

Vdd

Vdd

lORD high to INPACK high

t7

lORD low to 0[0:15] valid

t8

WAIT high to 0[0:15] valid

t9

Port busy (a)

35

ns

50

ns

350

ns

25

ns

35

ns

25

ns

35

ns

50

ns

70

ns

5

ns

10

ns

A[0:3] valid to IOWR LOW;
t1
REG, CE1, CE2 low to IOWR low

0

ns

IOWR high to A[0:3] invalid;
t2
IOWR high to REG, CE1, CE2 high

0

ns

lORD high to 0[0:15] invalid
(data hold)

t 10

TABLE 4: 1/0 Write Cycle (PCMCIA mode) (Refer to Figure 5)

IOWR low pulse width

= 5V
= 3.3V
Vdd = 5V
Vdd = 3.3V
Vdd

t3

Vdd
IOWR low to WAIT low

IOWR low to WAIT high(1)
D[0:15] valid to IOWR high
(data setup)
IOWR high to D[0:15] invalid
(data hold)

t4

t5

Port busy (a)

30

ns

35

ns

Port busy (a)

35

ns

50

ns

350

ns

ts

15

ns

t7

10

ns

Note: (1) Maximum of 350 ns may occur if system makes contiguous system read cycles at less than 100 ns
intervals, and both the transmitter and receiver are active in "Ioopback" reception (if the transmitter
and receiver are idle, the max value becomes 250 ns). 2.4 f.1s max for host read error.
(a) For Buffer Memory Port when port is busy.
(b) For register or port is not busy.
7-37

I

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo

A[0:3]

INPACK------~----------------~----------

(logic high)

WAIT (a) - - - - + -

WAIT(~ ------~----------------_+---------­

(logic high)

0[0:15] - - - - - - - I - - - - - C
(to 8370)

FIGURE 5: 1/0 Write Cycle (PCMCIA mode)

7-38

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo

HA[0:3]

---,.v

\
/

~

~t2~

cs ~ r.-t1~

I

1\

READY
(a)

•

t3

RD

/

--

ts

V

~~

~t7~

t4

READY
(b)

J

1\
~

t 6- - - . .

READY
(c)

READY
(d)

(logic high)

~
8

f4--t9~

\
J

I4-t11~

1
13

HD[0:1S]
(from 8370)

--""

Ir---

. . . - t 12 __...
t 10

FIGURE 6: Read Cycle, Generic Bus Mode (Refer to Table 9)

I

7-39

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
TABLE 5: Read Cycle, Generic Bus Mode (Refer to Figure 6)
PARAMETER

CONDITIONS

CS low to RD low;
HA[0:3] valid to RD low

t1

RD high to CS high;
RD high to HA[0:3] invalid

t2

RD low pulse width

t3

MIN

= 5V
= 3.3V
Vdd = 5V
Vdd = 3.3V
Vdd

Vdd
RD low to READY low

t4

(a)

RD low to READY high (1)

ts

(a)

RD low to READY low (1)

ts

(b)

RD high to READY high

t7

(b)

RD low to READY low

ts

(d)

Vdd
RD high to READY high

t9

RD low to HD[0:15] valid

t 10

RD high to HD[0:15] invalid
(data hold)
Note:

(1)

(a)
(b)
(c)
(d)

0

ns

30

ns

35

ns

0

35

ns

45

ns

350

ns

350

ns

0

25

ns

0

30

ns

40

ns

28

ns

0

Register access

UNIT
ns

= 3.3V

(d)

= 5V
= 3.3V

45

ns

60

ns

Port access

5

ns

Port access

5

ns

Vdd
Vdd

READY high to HD[0:15] validt 11
READY low to HD[0:15] valid t12

= 5V

MAX

0

0

Vdd

NOM

10

ns

t 13

Maximum of 350 ns may occur if system makes contiguous system read cycles at less than
100 ns intervals, and both the transmitter and receiver are active in "Ioopback" reception (if the
transmitter and receiver are idle, the max value becomes 250 ns). 2.411.5 max for host read error.
For Buffer Memory Port when port is busy and RDYSEL = 1.
For Buffer Memory Port when port is busy and RDYSEL = o.
For register or port is not busy and RDYSEL = 1.
For register or port is not busy and RDYSEL =

o.

7-40

551 78Q8373
3V, 5V PCMCIA
Ethernet Combo

HA[0:3) ~

\

----1
~t2-"

cs ~ ~t1-"
t3

WR

ts

READY
(a)

I

~

~t7~

t4

READY
(b)
f4---t6~

READY

(logic high)

(c)

READY
(d)

m'\

.

HD[0:15)

..
t10

~t9~

-

t11

..
~

(to 8370)

FIGURE 7: Write Cycle, Generic Bus Mode (Refer to Table 10)

I

7-41

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
TABLE 6: Write Cycle, Generic Bus Mode (Refer to Figure 7)
PARAMETER

CONDITIONS

CS low to WR low;
HA[O :3] valid to WR low

t,

WR high to CS high;
WR high to HA[0:3] invalid

t2

WR low pulse width

t3

MIN

= 5V
= 3.3V
Vdd = 5V
Vdd = 3.3V
Vdd

Vdd
WR low to READY low

t4

(a)

WR low to READY high (')

ts

(a)

WR low to READY low

ts

(b)

WR high to READY high

t7

(b)

WR low to READY low

ta

(d)

(1)

WR high to READY high

t9

HD[0:15] valid to WR high
(data setup)

t,o

WR high to HD[0:15] invalid
(data hold)

t"

Note:

= 5V
= 3.3V

Vdd

(d)

MAX

UNIT

0

ns

0

ns

30

ns

35
0

0

Vdd

NOM

0

0

ns
35

ns

45

ns

350

ns

350

ns

28

ns

30

ns

40

ns

25

ns

15

ns

10

ns

(1) Maximum of 350 ns may occur if system makes contiguous system read cycles at less than
100 ns intervals, and both the transmitter and receiver are active on "Ioopback" reception (if the
transmitter and receiver are idle, the max value becomes 250 ns). 2.4lls max for host write error.
(a) For Buffer Memory Port when port is busy and RDYSEL = 1.
(b) For Buffer Memory Port when port is busy and RDYSEL = O.
(c) For register or port is not busy and RDYSEL = 1.
(d) For register or port is not busy and RDYSEL = O.

7-42

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo

DMREQ

DMACK-----------.I

RD or WR

-------~

EOP--------------------~

FIGURE 8: Single-Cycle DMA Timing
TABLE 7: Single-Cycle DMA Timing (Refer to Figure 8)
PARAMETER
DMACK low to DMREO low

CONDITIONS

MIN

= 5V
= 3.3V
Vdd = 5V
Vdd = 3.3V
Vdd

t1

0

Vdd

DMACK high to DMREO high t2

0

NOM

MAX

UNIT

25

ns

30

ns

25

ns

30

ns

DMACK low to RD or WR low t3

0

ns

RD or WR high to DMACK high t4

0

ns

RD or WR low to Eap low

t5

0

ns

Eap high to DMACK high

t6

0

ns

Eap low pulse width

t7

10

ns

Note: (1) An asserted Eap terminates any further DMREO after DMACK returns high.
(2) The DMA cycle uses DMACK as the chip select. DMACK overrides CS and HA[0:3] if they are both
asserted at the same time, forcing selection of the Buffer Memory Port as in a DMA cycle.
(3) For READY timing and HD[0:15] timing, see Figure 6, t4 -t 13 , and Figure 7, t4 -t 11 .

7-43

I

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo

DMREQ ---~----------~f~----'

---.I

DMACK----~\~__________~~------+_------------~I
RDorWR--------~\~____~

FIGURE 9: Burst DMA Timing
TABLE 8: Burst DMA Timing
PARAMETER

CONDITIONS

RD or WR low to DMREQ low

SV
3.3V

MAX

UNIT

t1

30

ns

t1

40

ns

MIN

RD or WR high to DMACK high

t2

0

NOM

ns

Note: (1) DMREQ goes low during the next-to-Iast transfer of the burst. DMACK should not go high until after
the RD or WR pulse of the last transfer cycle goes high
(2) The DMA cycle uses DMACK as the chip select. DMACK overrides CS and HA[O :3] if they are both
asserted at the same time, forCing selection of the Buffer Memory Port as in a DMA cycle.
(3) For READY timing and HD[0:1S] timing, see Figure 6, t 4-t 13 , and Figure 7, t 4 -t 11 .

7-44

551 78Q8373
3V, 5V PCMCIA
Ethernet Combo

DMREO~
DMACK

~'----_ _ _ _ _ _----\

----.JI

'r--_ _ _ _

RDorWR --~

14--~

BURST INTERRUPTED

FIGURE 10: Burst DMA Interrupted by DMACK
Note: Burst can be interrupted by DMACK high-going pulse during the burst. Bu rst will resume when DMACK retu rns
low.

DMREO

RDorWR

_ ____~/~----------~0
'

-----------~\~____~

I

EOP - - - - - - - - - - - - - - - - - - - - - - - - - - ' , .--------,. J

FIGURE 11: Burst DMA Terminated by EOP
TABLE 9: Burst DMA Terminated by EOP

EOP low to DMREQ low

MIN

CONDITIONS

PARAMETER

Vdd

t1

Vdd

= 5V

4

= 3.3V

NOM

MAX

UNIT

28

ns

35

ns

EOP high to DMACK high

t2

3

ns

RD or WR low to EOP low

t3

0

ns

Note: EOP can be asserted during any transfer of the burst to terminate the process following that transfer.

7-45

SSI-78Q8373
3V, 5V PCMCIA
Ethernet Combo

RESET
CSlCE1

FIGURE 12: RESET Timing
TABLE 10: RESET Timing
PARAMETER

CONDITIONS

MIN

NOM

MAX

UNIT

t1

500

ns

RESET low to first CS/CE1 low t2

800

ns

RESET pulse width

Cs/CE1 \

WA/IOWR ~

RD/IORD

\

/

t

~~

t1

FIGURE 13: Skip Packet Timing
TABLE 11: Skip Packet Timing
PARAMETER

MIN

CONDITIONS

Writing Skip Packet high to
next Buffer Memory Port read t1

200

7-46

NOM

MAX

UNIT

ns

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo

...
RA[O:15]

J

..

t1

~

...

..

t2

t4~

~t3

RCSO,1

...

/
t5

ROE

~

J

t6

\

/
~t9

t7

RD[O:15] ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) )

/

..
«((((((((

____ t8~

»»»)

FIGURE 14: SRAM Read Timing
TABLE 12: SRAM Read Timing
PARAMETER

CONDITIONS

Read cycle

RAMSP

Address access time

Address valid to RCSO,1 low

t1
t2

MIN

=1
RAMSP = 0
RAMSP = 1
RAMSP = 0

ROE high to RCSO,1 high

t6

Output enable access time

t7

Data hold time
Address valid to ROE low

ns
ns

0

=1
RAMSP = 0
RAMSP

ns

8

ns
ns

75

ns

125

ns

8

ns

50

ns

100

ns
ns

0
30

t9

ns

125

0

=1
RAMSP = 0
RAMSP

t8

UNIT

145

t3

t5

MAX

75

RCSO,1 high to address invalid t4
Chip select access time

NOM

95

ns

Note: Use SRAM with address access time of 75 ns or less for RAMSP = 1 and 125 ns or less for RAMSP = O.
RAMSP is DLCR6 <6>.

7-47

I

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo

t1

RA[O:15]

J

'\

..

~t2

/

RCSO,1

•

t3

..

1\

~t6

t7

J

RWE

-~

---

...-.. r-ts
tg

• ~8

'10
RD[O:15]

~
5

•

t4

I

\\\\\\\

'\\'\\\\\\\\~~~~~~~~~

JIIIIII

1111111111111111111

1+-111-.J

FIGURE 15: SRAM Write Timing
TABLE 13: SRAM Write Timing
PARAMETER
Write Cycle

MIN

CONDITIONS
t1

NOM

MAX

UNIT

RAMSP = 1

95

ns

RAMSP= 0

145

ns

8

Address Valid to RCSO,1 low t2

ns

Address Valid to RWE high

t3

RAMSP = 1
RAMSP = 0

70
120

ns
ns

RCSO,1 low to RWE high

t4

RAMSP = 1
RAMSP = 0

70
120

ns
ns

0

ns

RCSO,1 high to Address Invalid ts
RCSO,1 low to RWE low

0

ns

70
120

ns
ns

ta

0

ns

tg

10

ns

RAMSP = 1

40

ns

=0

90

ns

20

ns

t6

RWE Pulse Width

t7

RWE high to RCSO,1 high
RWE high to Address Invalid
Data Setup Time

t 10

RAMSP = 1
RAMSP = 0

RAMSP
Data Hold Time

t11

Note: Use SRAM with address access time of 75 ns or less for RAMSP = 1 and 125 ns or less for RAMSP
RAMSP is DLCR6 <6>.

7-48

=

O.

551 78Q8373
3V, 5V PCMCIA
Ethernet Combo

II
SPKRIN

\

I

\L--------

\

II

\

/

\
-

t1 -

-

t2 f-----

FIGURE 16: Speaker Timing

TABLE 14: Speaker Timing (Refer to Figure 16)
PARAMETER

MIN

CONDITIONS

SPKR
high to low propagation delay t1

NOM

SPKR

UNIT

25

ns

= 3.3V
Vdd = 5V
Vdd = 3.3V

30

ns

25

ns

30

ns

Vdd

low to high propagation delay t2

MAX

= 5V

Vdd

I

J

----"-1

--t1--,r--_ __

\'---_~{.L'_,____~,
II

FIGURE 17: Interrupt Timing (Generic Bus Mode)
TABLE 15: Interrupt Timing (Generic Bus Mode)
PARAMETER
INT

MIN

CONDITIONS
Vdd

t1

signal cleaning delay

Vdd

7-49

= 5V

= 3.3V

7

NOM

MAX

UNIT

40

ns

50

ns

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo

~J

iOWA
Level Interrupt:

\

F'1l

rnEQ
II
If

Pulse Interrupt:

f-o- 12

I

lREQ

FIGURE 18: Interrupt Timing (PCMCIA Mode)
TABLE 16: Interrupt Timing (PCMCIA Mode)
PARAMETER

CONDITIONS

IREO

level interrupt

signal clearing delay
IREO low pulse width

DOP

MIN

Vdd
Vdd

t1

(VOO)

NOM

UNIT

40

ns

50

ns

750

800

ns

= 3.3V

pulse interrupt

t2

MAX

7

= 5V

o

o

~--------~~
I
I
I

r

I

DON (VOO)

I
I
I
I
~~,--------~I~

I

1~1
OOPIDON

OOPIDON

=1)

U

I
I

--·t1---1

I

~.

(Last Bit = 0)

(Last Bit

0

I
I

'--------'

o~

-U

\'-_____,

h

LJ

1}

I
I

I
I
I

{

I

I
I
I
I

!

!

LJ.-----·t1----to......I~~,~'j-

FIGURE 19: Transmit Timing (AUI)
TABLE 17: Transmit Timing (AUI)
PARAMETER

MIN

CONDITIONS

DOP/DON
end-of-packet delimiter

t1

DOP/DON
line voltage transition

t2

NOM

MAX

200

ns

8

7-50

UNIT

f..lS

551 78Q8373
3V, 5V PCMCIA
Ethernet Combo

o
TPOP

\J

Jl-n~_-

TPON

~

TPDP

TX±
= 0)

(Last bit

TX±
= 1)

o

LFt2=\~_

Jl---.JnL----

TPDN

(Last bit

°L}==114'-----_

FIGURE 20: Transmit Timing (TP)
TABLE 18: Transmit Timing (TP)
PARAMETER
TPOP/TPON
end-of-packet delimiter

CONDITIONS

MIN

NOM

MAX

UNIT

t1

250

ns

t2
TPOP to TPDP and TPON to
TPDN delay
t3

200

ns

TPDP/TPDN
end-of-packet delimiter

50

7-51

ns

I

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo

TPOP---~
~I.......----.------,/
'\--t1--1'

\'------

TPON ________~--------------------------------

::::-----~~--------------r--\--~r--\'-------

TX +1. _ _ _ _~~--------t3-------+-I-~'-----(After
Summation)

TPI PIN ___

Transmitted Link Pulse

------1

---'{rr·====~\====~t_4

\'------

Received Link Pulse

FIGURE 21: Link Test Timing
TABLE 19: Link Test Timing

TPDP/TPDN link pulse width

MIN

CONDITIONS

PARAMETER
TPOP link pulse width

MAX

UNIT

150

ns

t2

100

ns

Duration between transmitted t3
link pulses
Duration between received
link pulses

NOM

t1

t4

7-52

9

11

ms

4.1

65

ms

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo

LEDLT
Link Down

~~F'1--1-linkUp

Transmit

.

Link Up

FIGURE 22: LED Timing (TP)
TABLE 20: LED Timing
PARAMETER

MIN

CONDITIONS

Transmit blink-off timing

t1

NOM

MAX

UNIT
ms

100

TP selected

LEDLT

FIGURE 23: LED Timing (AUI)
TABLE 21: LED Timing
PARAMETER
Transmit blink-on timing

MIN

CONDITIONS
t1

NOM

MAX

100

AU I selected

UNIT
ms

I
FIGURE 24: Oscillator Duty Cycle

TABLE 22: OSCI Duty Cycle
MIN

CONDITIONS

PARAMETER
Oscillator duty cycle

40

t1

7-53

NOM
50

MAX

UNIT

60

%

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo

DOP/DON OUTPUT LOAD

DIGITAL OUTPUT, I/O LOAD

I

~OPF

DOP

l

}78Q

DON
REXT

i~~
TTL INPUT WAVEFORM
3 : T e s t Point. 1.4V

-

TTL OUTPUT WAVEFORM

k --

Vih = 2.0V
- - - - Vii = O.BV

k-

-Voh = 2AV
- - - - Vol = OAV

3:Testpoint=1.4V

-

DIP/DIN, CIP/CIN AND TPIPITPIN
INPUT WAVEFORM
Vih =4.5V
3 :Test Point = 3.5V
.- - - - Vii = 2.5V

DOP/DON OUTPUT WAVEFORM

k-_

3

E--

Test Point = 4.0V ~

- -

- -

VOh =4.3V
Vol = 3.7V

TPOPITPON OUTPUT WAVEFORM

3

.lest Point

FIGURE 25: Test Conditions

7-54

=

C--

2.5V -,

-

-

- -

VOh =4.0V
Vol = 1.0V

SSI78Q8373
3V, 5V PCMCIA
Ethernet Combo
PACKAGE PIN DESIGNATIONS

CAUTION: Use handling procedures necessary
for a static sensitive component.

(Top View)

DOP

HD10

80

HD2

79

DON

HD9

78

VDD

HD1

77

TPOP

HD8

76

TPON

HDO

75
74

TPDP

73

GND

HAD
HA1

TPDN

HA2

9
10

72
71

GND

HA3
RESET

11

70

OS CO

VDD

VDD

12

69

OSCI

GND
WR

13
14

68
67

RA15
ROE

RD

15

66

RA11

SHE

16

65

RA9

HD15

17

64

RAB

CS

18

63

RA13

HD14

19

62

RWE

HD7

20

61

RA14

GND

21

60

RA12

HD13

22

59

RA7

HD6

23
24

58
57

VDD
GND

56

RA6

HD11

25
26

55

RA5

HD4

27

54

HD3

28

53

RA4
RA3

RD8

29

52

RA2

RD9

30

51

RA1

HD12
HD5

cry

N

(")

o .....

(")

"18~C1i~~oo
80

OOP

79

DON

78
77
76

TPOP
TPON

75

TPOP

A1

74
73

TPON
GNO

f1.2.
1>:3

72
71

GNO

RESET

70
69

OSCO

68
67

RA15
ROE

iORl5

66

RA11

CE2

65
64
63
62

RA9

•

010

D2
D9

01
De
DO
AD

VOO
GNO
IOWR

015
CE1

014

VDO

VDD
OSCI

RAS
RA13
RWE

D7

61

RA14

GNO
013
D6
012

60
59
58

RA12
RA7

VDD

24

57

GND

56
54
53

RA6
RAS
RA4

D3

25
26
27
28

RA3

OE

29

52

RA2

WE

~

~

RA1

OS
011
D4

55

z;; P.I ~ C; ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t:t~ ~ fB

100-Lead QFP
PCMCIA Bus Mode

7-56

551 78Q8373
3V, 5V PCMCIA
Ethernet Combo
PACKAGE PIN DESIGNATIONS

CAUTION: Use handling procedures necessary
for a static sensitive component.

(Top View)

8813l!;;~~ VEE> -9.5V.

4.

The voltage on TXO is -4V < V(TXO) < O.OV.

5.

The AC current measurement is referenced to
the DC current level.

GND

RX+
or
eo+

7. Operating or idle state.

¢

Device measurement taken in idle state.

10. This threshold can be determined by monitoring
the CD± output with a DC level in RX/.

+
voe

510±5%

~

9.

""'?

I

t

ETHERNET
XeVR

50 f.lH±1%

VEE
RXor
eD-

t

;s:

510Q±5%

VEE

FIGURE 2: Test Load for CD± or RX±

7-64

I
r
VOS

73Q±1%

V:D -VCOM

SSI78Q8392
Ethernet Coaxial Transceiver

AC OPERATING CHARACTERISTICS
O°C < T(ambient) < +70°C, VEE

PARAMETER

= 9V ± 5%
MIN

CONDITION

Receiver startup delay
(RXI to RX±)

t RoN

NOM

MAX

UNIT

4

5

bits

50

ns

------- 1---

tRd

Receiver propagation delay
(RXI to RX±)

15

tRr

Differential outputs rise time
(RX±, CD±)

4

tRt

Differential outputs fall time
(RX±, CD±)

4

t RJ

Receiver & cable total jitter

ns
1-------.

ns
--r--

4

ns

tTST

Transmitter startup delay
(TX±to TXO)

1

2

bits

tTd

Transmitter propagation
delay (TX± to TXO)

25

50

ns

t Tr

Transmitter rise time 10% to 90% (TXO)

25

30

ns

30

ns

2
- ---

20

--

tTt

Transmitter fall time 90% to 10% (TXO)

20

25
-~

tTM
tTs

--

ns

0.5

t Tr and tTt mismatch

----~

1---.

±0.5

Transmitter skew (TXO)

ns

- - ~--- - - - - - t--------.~-

ns

t ToN

Transmit turn-on pulse
width at VTS (TX±)

20

tTOFF

Transmit turn-off pulse
width at VTS (TX±)

250

tCON

Collision turn-on delay

tCOFF

Collision turn-off delay

--~-~

--~

ns

----.~-

tCD

7

bits

'--

8.5

Collision frequency (CD±)

- -- -

20

bits

11.5

MHz

---~---.-

Collision pulse width (CD±)

35

CD Heartbeat delay
(TX± to CD±)

0.6

tHW

CD Heartbeat duration
(CD±)

0.5

tJA

Jabber activation delay
(TX± to TXO and CD±)

20

tJR

Jabber reset unjab time
(TX± to TXO and CD±)

250

tcp
tHaN

..

ns
70
__. - - - - - - t----------1.6
IJ,S

1.0

1.5

IJ,S

75

ms

750

ms

-

7-65

500

I

SSI78Q8392
Ethernet Coaxial Transceiver

ELECTRICAL SPECIFICATIONS (continued)

RECEIVE SPECIFICATIONS

TRANSMIT SPECIFICATIONS

The first bit sent from RX± may have data and phase
violations. The second through last bit reproduce the
received signal with less than or equal to specified
jitter.

The first bit transmitted from TXO may have data and
phase violations. The second through last bit reproduce
the TX± signal with less than or equal to specified jitter.

There is no logical signal inversion between the RXI
input and the RX± output. A high level at RXI produces
a positive differential voltage from RX+ to RX-.

There is no logical signal inversion between Tx± and
TXO output. A low level from TX+ to TX- results in more
current flowing from the coaxial cable into the TXO pin.
At the end oftransmission, when the transmitter changes
from the enabled state to the idle state, no spurious
pulses are generated, i.e., the transition on TXO
proceeds monotonically to zero current.

RXI - - -

r-~-l/
RX±

------.'0
1st BIT

1

FIGURE 3: Receiver Timing

TX±------------------~

~:NHI

~

TXO ------------------~--__\

-I r'Td
c::--_...J1

90%T
;=t;10%

-I~
FIGURE 4: Transmitter Timing
7-66

SSI78Q8392
Ethernet Coaxial Transceiver

INPUT STEP
FUNCTION

SS178Q8392
COLLISION
DETECTOR

RXI

co±
OUTPUT

RCNETWORK
SIMULATES WORST CASE
CABLE STEP RESPONSE

RXI
Vco (MAX)

VCO(MIN)

co± _ _ _ _ _ _ _---,

FIGURE 5: Collision Timing

T~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____

I~

·1

co± _ _ _ _ _ _ _ _ _ _- - ,

FIGURE 6: Heartbeat Timing

T~---i 111111111111111111111111---1- - - - ...

I~ ~A·I

TXO_~~~~~~

I~

________________

~

_ __

CD±-------tllllllllllllllllllllllllllllllllillr---FIGURE 7: Jabber Timing

7-67

I

SSI78Q8392

Ethernet Coaxial Transceiver

I

~~K- -

-

--,

INPUT SIGNAL WITH
1
30 NSEC RISE AND -~---'
FALL TIMES

1 RXI

fT\ C = 36 pF

1

SSI78Q8392
ET
RECEIVER

RX±
OUTPUT

1

L---.J::----l
RC NETWORK SIMULATES
WORST CASE CABLE JITIER

I. . . . I
1

1

1

Input jitter <= ±1 nsec
RX± Output jitter <= ± 7 nsec
Difference <- ± 6 nsec

FIGURE 8: Receive Jitter Timing

TRANSMIT
OUTPUT
(TXO)

RX±
25n

50 J.lH

or

CD±

510n

FIGURE 9: Test Loads

7-68

78n

551 78Q8392
Ethernet Coaxial Transceiver

PACKAGE PIN DESIGNATIONS
(Top View)

CO+

CDS

a:
4

co-

2

15

TXO

AX+

3

14

AXI

VEE

4

13

VEE

VEE

5

12

AA-

AX-

6

11

AA+

TX+

7

10

GND

TX-

9

8

+
x

16

6
<..)

+

0

<..)

rn

0

x

0

x

<..)

~

z

a:

1

28

27

26

<..)

•

25

VEE

HBE

16-Pin DIP

12

13

14

15

16

x

+
x

x

co

w

0

J:

" "

a:

~

~

z

17

18

0

a:
a:

z

VEE

24

VEE

23

VEE

22

VEE

21

VEE

20

VEE

19

RR-

+

28-Pin PLCC

CAUTION: Use handling procedures necessary
for a static sensitive component.

ORDERING INFORMATION
PART DESCRIPTION

ORDER NUMBER

PACKAGE MARK

881 78Q8392

16-Pin Plastic DIP

7808392-CP

7808392-CP

8817808392

28-Pin Plastic PLCC

7808392-28CH

7808392-28CH

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914

©1994 Silicon Systems, Inc.

7-69

1294 - rev.

I

Notes:

7-70

SSI 78Q8392L
Low Power Ethernet
Coaxial Transceiver

ttfikk1h¥ltfft,'""ji['J"

December 1994

DESCRIPTION

FEATURES

The SSI 7S0S392L Ethernet Transceiver is a low
power, BiCMOS coax line transmitter/receiver. The
device includes analog transmit and receive buffers, a
10 MHz on-board oscillator, timing logic for jabber and
heartbeat functions, output drivers and bandgap
reference, in addition to a current reference and collision
detector.

•

very low power consumption

•

Compliant with Ethernet II, IEEE S02.3
10Base5 and 10Base2 (Cheapernet)

•

Integrates all transceiver functions except
signal and power isolation
Innovative design minimizes external components count and power consumption
Jabber timer function integrated on chip
Externally selectable CEO heartbeat allows
operation with IEEE 802.3 compatible repeaters
Squelch circuitry at all inputs rejects noise

•

This transceiver provides the interface between the
single-ended coaxial cable signals and the Manchesterencoded differential logic signals. Primary functional
blocks include the receiver, transmitter, collision
detection and jabber timer. This IC may be used in
either internal or external MAU environments.

•
•
•

The SSI7S0S392L is available in 16-pin plastic, 24-pin
SOL and 2S-pin PLCC packages.

PIN DIAGRAM

SSI78Q8392L CONNECTION DIAGRAM
5100±5%

-9V

x4

U

COLLISION

SIGNAL
TODTE

co+

16

COS

VEE

co-

2

15

lXO

VEE

RX+

3

14

RXI

VEE

VEE

4

13

VEE

CDS

VEE

5

12

RR-

RX-

6

11

RR+

TX+

7

10

GNO

lX-

8

9

HBE

TXO
RXI

MTATU
DTE

GND

TX+
OATAFROMJ

HBE

16-Pin DIP
RR-

OlE

COAX

TXRR+
CAUTION: Use handling procedures necessary
for a static sensitive component.

1294

7-71

I

SSI 78Q8392L

Low Power Ethernet
Coaxial Transceiver

DATA MEDIA

VEE~VEE
5

VEE

13 VEE

SLICER

RECEIVER OUTPUT
LINE DRIVER

-lJ

>--....----------D
L---,-----J-

~ ::+

SIGNAL PRESENT

_________

I

FIGURE 1: SSI 78Q8392L General System Block Diagram

Advance Information: IndiCates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914

©1994 Silicon Systems, Inc.

7-72

1294

551 78Q8377
10BaseT Ethernet Combo
for Plug and Play

""milt·UIliiit.h'
November 1994

DESCRIPTION

FEATURES

The SSI 7808377 is a highly integrated Ethernet IC for use
in Ethemet Network Interlace Cards (NICs) in the ISA/Plug
and Play (PnP) environment. It contains a full-duplex Media
Access Controller (MAC), a 10 MbiVs Manchester encoder/
decoder (EN DEC) , a 1OBaseTtransceiver, ISA-bus interlace
and an Attachment Untt Interface (AU I). The only external
components required to build an Ethernet adapter card
with the 7808377 are buffer memory and a few passive
components. In full duplex operation, transmission line
throughput doubles to the theoretical 20 Mbit/s. In this
mode, the collision detection, SOE generation and
carrier deference are disabled.

Highly integrated Ethernet combo with Plug
and Play (PnP) interface
Compliant with plug and play ISA Specification
Version 1.0a
Includes complete Ethernet circuitry for
10BaseT: Buffer manager, MAC/OLC, ENOEC,
10BaseT transceiver, AUI, and power
management
Register-compatible with SSI 7808373
"Glueless" and "jumperless" connection to ISA
bus

The 7808377 has an integrated ISA-bus interface that
physically connects to the bus without any additional
glue logiC. The 7808377 is defined with "jumperless"
configuration in mind. The configuration information is
stored in serial EEPROM.

Supports both PnP and non-Pn P environment
Integrated 16 mA data bus buffer with
staggering for reduced noise and ground
bounce
Serial EEPROM support via microwire (4-wire)
interface

The 7808377 fully supports the PnP ISA specification.
The PnP logic can also be bypassed through a bit in
the EEPROM. When the PnP logiC is bypassed, the
7808377 will power up active after loading the
necessary configuration information from the serial
EEPROM.

Boot device (either read-only or read-write
memory) support. 8 Boot device locations with
16 or 32 Kbytes size
8 interrupt lines selection. Supports edge and
level-sensitive interrupts. Tri-state implementation allows sharing of interrupts for both
modes

The popular microwire (4-wire) interface is supported
by the 7808377 to connect to serial EEPROM, which
contains configuration information such as I/O Base
address, Boot Device address, IRO selection, MAC
address, etc. Reading of essential configuration
information like the I/O Base address and Boot Device
address is done automatically by the 7808377. The
driver software is then responsible to read the rest of
the information and program the 7808377 registers
with the appropriate values read.

Programmable full-duplex operation in twistedpair mode
Low power design
128-pin OFP with single 5V supply

The 7808377 allows for a diskless station to boot from
the installed boot device. It supports 8 memory base
addresses for the boot device with 16 Kbytes memory
size and 4 memory base addresses with 32 Kbytes
size. The boot feature can also be disabled through a
bit in the serial EEPROM. Both read-only and readwrite (e.g., flash) memory are supported by the
7808377. Furthermore, accidental write to the flash
can be prevented through a write protect register bit.
The 7808377 only provides a chip select pin to the
boot device and the address, data and control Signals
of the boot device connect directly to the appropriate
ISA bus.
1194

7-73

I

SSI78Q8377
10BaseT Ethernet Combo for
Plug and Play

BLOCK DIAGRAM

BUFFER MAC ENDEC
ISA BUS
10BASE-T
INTERFACE MANAGER (DLC)
TRANSCEIVER

FILTER,
ISOLATION
TWISTED
PAIR

rPnPl

~
AUI
POWER MANAGEMENT

ISOLATION
COAX
TRANSCEIVER

COAX

ISA BUS

Target Specification: The farget specification is intended as an initial disclosure of specification goals for the product. The specifications
are based on design goals, subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture
unless agreed to in writing.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1994 Silicon Systems, Inc.

7-74

1194

5S178Q8378
Enhanced PCMCIA
Ethernet Device

December 1994

DESCRIPTION

FEATURES

The SSI 7808378 is a highly integrated Ethernet IC
for use in PCMCIA (Personal Computer Memory Card
International Association) applications with MultiFunction card capability, especially Ethernet/Modem
combinations. It contains a full-duplex Media Access
Controller (MAC), a 10 Mbit/s Manchester encoder/
decoder (ENDEC), a 10BaseT transceiver, PCMCIA
bus interface and an Attachment Unit Interface (AUI),
and can operate from either a 5-volt or 3.3-volt supply.
The only external components required to build a
PCMCIA Ethernet adapter card with the 7808378 are
buffer memory and a few passive components. In full
duplex operation, transmission line throughput doubles
to the theoretical 20 Mbit/s. In this mode, the collision
detection, SOE generation and carrier deference are
disabled.

Highly integrated PCMCIA EtHernet and
modem port combo
PCMCIA Multifunction spec compliant. Builtin modem port interface to external UART
Includes all the functional blocks of 78Q8373:
Buffer manager, MAC/OLC, ENOEC, 10BaseT
transceiver, AUI, power management and 3.3V
or 5V operation
Register-compatible with SSI78Q8373
Interface to parallel EEPROM/Flash memory for
PCMCIA CIS (Card Information Structure)
Programmable full-duplex operation in twistedpair mode
1/0 registers are accessible through normal
1/0 cycle as well as common memory cycle

To allow multi-function operation, two sets of Function
Configuration Registers (FCR - formerly called Card
Configuration Registers or CCR) are provided so that
each function can be configured independently of the
other. The chip includes the function of mapping and
decoding the I/O range for the ethernet (7808373)
registers and the modem port. The 7808378 is also
capable of handling multiple interrupts from two
sources by saving the second interrupt and generating
it later according to the PCMCIA Multifunction spec. A
simple modem interface is provided on-chip to
eliminate the need for external glue logic when
designing an Ethernet/Modem multifunction PCMCIA
card. The 7808378 interfaces directly to a UART.

Low power design
100-Lead TQFP

I

The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.

1294

7-75

551 78Q8378
Enhanced PCMCIA
Ethernet Device

BLOCK DIAGRAM

SRAM
Interface
MultiFunction
PCMCIA
Interface

MAC ENDEC
(DLC)

10BaseT
Transceiver

FILTER,
ISOLATION
TWISTED
PAIR

Buffer
Manager

Power Management

AUI

ISOLATION
COAX
TRANSCEIVER

COAX
PCMCIA BUS MODEM INTERFACE

Target Specification: The .target specification is intended as an initial disclosure of specification goals for the product. The specifications
are based on design goals, subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture
unless agreed to in writing.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1994 Silicon Systems, Inc.

7-76

1294

SSI78Q2250
155 Mbit/s ATM
Line Transceiver

i"'~t§e·iijlit!i'[·'"

October 1994

DESCRIPTION

FEATURES

The SSI 7802250 is a high-speed line transceiver
integrated circuit intended for use in Asynchronous
Transfer Mode (ATM) applications. It is used at the
interface to Category 5 Unshielded Twisted-Pair (UTP)
cabling and is connected to the line via isolation
transformers. Interface to digital framer circuits is
accomplished via 8-bit parallel CMOS I/O running at
19.44 Mbitls.

•

The IC provides full transmit and receive line interface
functions with minimum external components required.
The receiver provides near-end crosstalk cancellation,
adaptive equalization for accurate clock and data
recovery, while the transmitter includes on-chip pulse
shaping. The 7802250 is built in a SiCMOS technology
for highest performance and low power operation.

•

•
•
•
•
•
•
•

155.52 Mbit/s interface for Category 5
Unshielded Twisted Pair (UTP) cable
Compliant with ATM PMD Interface Spec for
155.52 Mbitls over Twisted Pair Cable
Parallel CMOS logic interface at 19.44 Mbit/s
ECl interfaces for connection to fiber optic
receive and transmit modules
On-chip pulse shaping
AutomatiC gain
Adaptive equalization
Power down mode
Advanced BiCMOS processing

I
CAUTION: Use handling procedures necessary
for a static sensitive component.

The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.

1094

7-77

SSI78Q2250
155 Mbit/s ATM
Line Transceiver
FUNCTIONAL DESCRIPTION

As noted, the transmitter uses either the local crystal
oscillator or the recovered clock from the receiver.
When the circuit is in a host, the transmit clock is always
derived from the local crystal oscillator. When it is in a
hub, the transmit clock is derived from the recovered
clock when the receive PLL is locked. When it is' not,
the transmit clock PLL switches its input to the crystal
oscillator. In this way, the transmitter will still operate
at the right frequency even if the receiver is not seeing
a correct signal. The receive clock RxClk used to clock
out the data from the receive side of the chip is normally
derived from the receive PLL, when it is locked. When
the PLL is unlocked, the RxClk is switched to the crystal
oscillator so that it will be at the right frequency. The
data leaving the chip from RxDatO-7 will still be timed
by RxClk but will not be valid.

The transmit section of this IC contains all of the
necessary circuitry to convert 8-bit parallel data into a
single 155.52 MbiVs serial data signal and drive the
Category 5 UTP cable. It generates the 155.52 MHz
using a fixed PLL synthesizer locked to either a local
19.44 MHz crystal oscillator (in a hub application), or
the 155.52 MbiVs clock recovered in the receiver (when
used in a host). Data enters the chip via TxDatO-7 and
are converted to serial by a parallel-to-serial converter.
The single 155.52 Mbitls data line is then converted to
the 1 volt differential signal required at the line interface.
Connection to the UTP cable is through a transformer.
On the receive side, data signal enters the chip via the
UTP interface after it has gone through up to 100
meters of cable. The connection to the UTP cable is
through a transformer. Once on-chip, the signal goes
through both an automatic gain circuit and an adaptive
equalizer. These circuits look forthe amount dispersion
and attenuation caused by the cable and restore the
received pulses to square waves. The amount of gain
and equalization applied to the pulses varies with the
detected attenuation and dispersion and therefore with
the length of the cable. The clock signal is extracted
from the equalized data signal using a Costas loop
PLL. The recovered clock is used to retime the data
signal and finally it is converted to 8-bit parallel data at
19.44 Mbitls in a serial to parallel converter.

The 78Q2250 uses the local crystal oscillator to
generate bias voltages for setting the various time
dependent circuits on the chip. These include the
controlled rise-time for the transmit pulses and the
center frequencies of the two on-chip voltage-controlled
oscillators. This means that the narrow band PLL
circuits won't require frequency discrimination circuits
to aid acquisition. It also means the chip will not require
the use of the external resistor used in other ICs
requiring preCision timing, nor will it be necessary to
trim the part.

Target Specification: The target specification is intended as an initial disclosure of specification goal.s f~r the prod~ct. The specifications
are based on design goals, subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture
unless agreed to in writing.
No responsibility is assumed by Silicon Systems for use of this product nor for any i!1fringements of patent~ .and trademarks .~r other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of SIlicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Acco~dingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
.

Silicon Systems, Inc., 14351 Myford Road, Tustin. CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1094

7-78

©1994 Silicon Systems. Inc.

Section

8

PROGRAMMABLE
ELECTRONIC FILTERS

I
8

8-0

SSI 32F8001/8002
Low-Power Programmable
Electron ic Filter

December 1994

FEATURES

DESCRIPTION

Ideal for multi-rate systems applications

The 551 32F8001/8002 Programmable Electronic
Filter provides an electronically controlled low-pass
filter with a separate differentiated low-pass output. A
seven-pole, low-pass filter is provided along with a
single-pole, single-zero differentiator. Both outputs
have matched delays. The delay matching is
unaffected by any amou nt of programmed equalization
or bandwidth. This programability combined with low
group delay variation make the 551 32F8001/8002
idealforuse in constant density recording applications.
Pulse slimming equalization is accomplished by a twopole, low-pass with a two-pole, high-pass feed
forward section to provide complimentary real axis
zeros. A variable attenuator is used to program the
zero locations.

=

Programmable filter cutoff frequency (/c 9
to 27 MHz, 32F8001 ; Ic 6 to 18 MHz, 32F8002)
Programmable pulse slimming equalization
(0 to 13.5 dB boost at the filter cutoff
frequency)

=

Matched normal and differentiated low-pass
outputs
Differential filter inputs and outputs
±12% cutoff frequency accuracy
±2% maximum group delay variation from
0.2 Ic to Ic
Total harmonic distortion less than 1%

The 551 32F8001/8002 programmable equalization
and bandwidth characteristics can be controlled by
external DACs. Fixed characteristics are easily
accomplished with three external resistors, in addition
equalization can be switched in or out by a logic signal.
The 551 32F8001 18002 requires only a +5V supply and
are available in 16-lead SON and SOL packages.

No external filter components required
+5V only operation
16-Lead SON and SOL package
Pin compatible with SSI 32F8011

PIN DIAGRAM

BLOCK DIAGRAM
VIN+
VIN-

VO_NORM+
VO_NORM-

VO_DIFF+
VO_DIFF-

VBPLr~~~~~~~

VPTAT

IFP r1--~2f"-;:::::-::-I

N/C

VO_DIFF+

VO_NORM-

VO_DIFF-

VO_NORM+

PWRON

VCC

VPTAT

VIN-

N/C

VIN+

IFP

VBP

VFP

FBST

GND

1----'

VFP
PWRON

FBST

16-Lead SOL, SON

CAUTION: Use handling procedures necessary
for a static sensitive component.

1294 - rev.

8-1

I

SSI 32F8001/8002

Low-Power Programmable
Electronic Filter
If the 551 32F8001/8002 cutoff frequency is set using
voltage VPTATto bias upa resistor tied to pin VFP, the
cutoff frequency is related to the resistor value by the
following formulas.

FUNCTIONAL DESCRIPTION
The 551 32F8001/8002 is a high performance
programmable electronic filter. It features a 7-pole
0.05° equiripple linear phase filter with matched normal
and differentiated outputs.

Ic (ideal, in MHz)
32F8001

CUTOFF FREQUENCY PROGRAMMING

32F8002

The 551 32F8001 programmable electronic filter can
be set to a filter cutoff frequency from 9 to 27 M Hz with
no boost. The 551 32F8002 can set the cutoff frequency
from 6 to 18 MHz with no boost.

MAGNITUDE EQUALIZATION PROGRAMMING

The magnitude equalization, measured in dB, is the
amount of high frequency peaking at the cutoff frequency
relative to the original-3 dB point. For example, when
12 dB boost is applied, the magnitude response peaks
up 9 dB above the DC gain.
The amplitude of the input signal at frequencies near
the cutoff frequency can be increased using this feature.
Applying an external voltage to pin VBP which is
proportional to reference output voltage VPTAT
(provided by the VPTAT pin) will setthe amount of
boost. A fixed amount of boost can be set by an
external resistor divider network connected from pin
VBPto pins VPTATandGND. No boost is applied ifpin
FB5T, frequency boost enable, is at a low logic level.
The amount of boost FB at the cutoff frequency Fc is
related to the voltage VBP by the formula

The cutoff frequency, determined by the -3 dB point
relative to a very low frequency value « 10 kHz), is
related to the current IVFP injected into pin IFP by the
following formulas.

FB (ideal, in dB) = 20 log1o[3.73(VBP/VPTAT)+1],
where 0 < VBP < VPT A T.
POWER ON I OFF

Ic (ideal, in MHz)
=
=

45.0· IFP
30.0· IFP

= 45.0 • 1.8/(3 • Rx)

Rx in !ill

The VPTAT voltage will compensate for internal
temperature variation of the Ic and boost circuits.

32F8002

45.0· IFP

30.0· IFP = 30.0 • 1.8/(3· Rx)

If pin VFP is used to program cutoff frequency, pin IFP
should be left open.

Cutoff frequency programming can be established
using either a current source fed into pin IFP whose
output current is proportional to the 551 32F8001 18002
output reference voltage VPTAT, or by means of an
external resistor tied from the output voltage reference
pin V PTAno pin VFP. The former method is optimized
using the 551 3204661 Time Base Generator, since
the current source into pin IFP is available at the OAC
F output of the 5513204661. Furthermore, the voltage
reference input is supplied to pin VR3 of the
5513204661 by the referencevoltagefromthe VPTAT
pin of the S5132F8001/8002. This reference voltage is
internally generated by a band-gap circuit in conjunction
with a temperature varying reference to create a voltage
which is proportional to absolute temperature.

32F8001

=
=

The 551 32F8001/8002 supports a power down mode
for minimal idle mode power dissipation. When PWRON
is pulled up to logic 1, the device is in normal operation
mode. When PWRON is pulled down to logic 0, or left
open, the device is in the power down mode.

= 45.0 • IVFP • 1.8/vPTAT
= 30.0 • IVFp· 1.8/vPTAT

where IFP and IVFP are in mA, 0.2 < IFP < 0.6 rnA,
VPTAT is in volts, and Ta = 25°C.
If a current source is used to inject current into pin IFP,
pin VFP should be left -open.

8-2

SSI 32F8001/8002
Low-Power Programmable
Electronic Filter
PIN DESCRIPTION
NAME

VIN+, VIN-

TYPE

I

DESCRIPTION

Differential Signal Inputs. The input signals must be AC coupled to these pins.

VO_NORM+,
VO_NORM-

0

Differential Normal Outputs. The output signals must be Ae coupled.

VO_DIFF+,
VO_DIFF-

0

Differential Differentiated Outputs. For minimum time skew, these outputs
should be AC coupled.

IFP

I

Frequency Program Input. The filter cutoff frequency fc, is set by an external
current IFP, injected into this pin.IFP must be proportional to voltage VPTAT.
This current can be set with an external current generator such as a DAC. VFP
should be left open when using this pin.

VFP

I

Frequency Program Input. The filter cutoff frequency can be set by programming a current through a resistor from VPTAT to this pin. IFP should be left
open when using this pin.

VBP

I

Frequency Boost Program Input. The high frequency boost is set by an
external voltage applied to this pin. VBP must be proportional to voltage
VPTAT. A fixed amount of boost can be set by an external resistor divider
network connected from VBP to VPTAT and GND. No boost is applied if the
FBST pin is grounded, or at logic low.

FBST

I

Frequency Boost. A high logic level or open enables the frequency boost
circuitry. A low input disables this function.

PWRON

I

Power On. A high logic level enables the chip. A low level or open pin puts the
chip in a low power state.

VPTAT

0

PTAT Reference Voltage. This pin outputs a reference voltage which is
proportional to absolute temperature (PTAT). VBP, VFP or IFP must be
referenced to this pin for proper operation.

vee

0

+5 Volt Supply.

GND

I

Ground

I

ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may damage the device.
PARAMETER

RATINGS

Storage Temperature

-65°e to +150 o e

Junction Operating Temperature, Tj

+130 o e

Supply Voltage, vee

-O.5V to 7V

Voltage Applied to Inputs

-O.5V to vee

8-3

SSI32FS001/S002

Low-Power Programmable
Electronic Filter
ELECTRICAL SPECIFICATIONS (continued)
RECOMMENDED OPERATING CONDITIONS
PARAMETER

RATINGS

vcc

Supply voltage
Ambient Temperature

Ta

4.50V < VCC < 5.50V
O°C < Ta < 70°C

ELECTRICAL CHARACTERISTICS
Unless otherwise specified recommended operating conditions apply.

Power Supply Characteristics
PARAMETER

CONDITIONS

MIN

NOM

MAX

UNIT
rnA

Power Supply Current

ICC

PWRON~O.BV

0.1

0.5

Power Supply Current

ICC

PWRON~2V

46

60

mA

= 5V
PWRON ~ 2V, VCC = 5.5V

230

300

mW

275

330

mW

PWRON~O.BV

0.5

2.5

mW

Power Dissipation

PD

PWRON ~ 2V, VCC

DC Characteristics
High Level Input Voltage

VIH

Low Level Input Voltage

VIL

High Level Input Current

IIH

VIH

Low Level Input Current

ilL

VIL

TTL input

2

V

O.B

= 2.7V
= O.4V

20
-1.5

V

~
mA

Filter Characteristics
Filter Cutoff Frequency

*fc

32FB001

9

27

MHz

6

1B

MHz

fC

-12

+12

%

F

O.B

1.2

V/V

jc= 45 MHZ(IVFP)

*(f -3 dB)

mA
IVFP

= 0.2 to 0.6 rnA, Ta =25°C

32FB002

jc = 30 MHz (IVFP)
rnA

IVFP
Filter fc Accuracy

FCA

VO_NORM Diff Gain

AO

VO_DIFF Diff Gain

AD

Frequency Boost at fc

FB

Frequency Boost Accuracy FBA

= 0.2 to 0.6 rnA, 1a = 25°C

= max.
= 0.67 fc, FB = 0 dB
F = 0.67 fc, FB = 0 dB
VBP = VPTAT
fC = max.
fc = min.
VBP/vPTAT = 1.0 Ie = max,

8-4

O.BAO

1.2AO

V/V

12

13.5

15

dB

11.5

13

14.5

dB

+1,5

dB

-1.5

SSI 32FS001/S002
Low-Power Programmable
Electron ic Filter
FILTER CHARACTERISTICS

(continued)

PARAMETER

Group Delay Variation
Without Boost

MIN

CONDITIONS

TGDO

MAX

UNIT

8001

-500

+500

ps

F =0.2 fe to fe

8002

-750

+750

ps

= min.,

8001

-1.5

+1.5

ns

8002

-2.25

+2.25

-2

2

ns
0/0

-4

+4

0/0

jc

jc

= max.,

VBP =0
VPTAT

VBP =0
VPTAT
F = 0.2 jc to jc
Group Delay Variation
Without Boost (continued)

TGDO

F = 0.2 jc to jc

NOM

VBP =0
VPTAT
F = jc to 1.75 jc

~=O
VPTAT

Group Delay Variation
with Boost

TGDB

jc

= max, VBP = VPTAT

-500

+500

ps

F = 0.2 jc to jc

-750

+750

ps

= min., VBP = VPTAT
F = 0.2 to jc
F = 0.2 je TO fe, VBP = VPTAT
F = fe to 1.75 fe, VBP = VPTAT
THO =1% max, F =0.67 fe, VBP =OV

-1.5

+1.5

ns

-2.25

+2.25

ns

-2.5

+2.5

%

-4

+4

jc

%

1

Vp-p

THO =1.7% max, F=0.67 fe, VBP =OV,
Normal output (1000 pF across Rx)

1.5

Vp-p

Filter Input Dynamic Range VIF

THO =3.5% max, F=0.67 fe, VBP =OV,
Differentiated output
(1000 pF across Rx)

1.5

vp-p

Filter Output Dynamic RangeVOF

THD = 1% max, F = 0.67 jc
RLOAD ~ 1kQ (1000 pF across Rx)

1

Vp-p

Filter Input Dynamic Range VIF

(1000 pF across Rx)

Filter Diff Input Resistance

RIN

Filter Input Capacitance

CIN

Output Noise Voltage

EOUT
EOUT
EOUT

Differentiated Output
Output Noise Voltage
Normal Output

EOUT

kQ

4.3
3

pF

8001

3.5

5.4

mVRms

8002

3.3

5.2

mVRms

BW =100 MHz, Rs =50n

8001

2.3

3.45

mVRms

= max, VBP = OV
BW =100 MHz, Rs =50n
fe =max, VBP =VPTAT
BW =100 MHz, Rs =50n
fe =max, VBP =VPTAT

8002

2.1

3.15

mVRms

8001

7.7

10.75

mVRms

8002

4.8

7

mVRms

8001

3.8

4.75

mVRms

8002

2.6

3.3

mVRms

= max, VBP = OV

jc

Normal Output
Output Noise Voltage

BW =100 MHz, Rs =50n

jc

Differentiated Output
Output Noise Voltage

3

8-5

I

SS132F8001/S002
Low-Power Programmable
Electronic Filter
ELECTRICAL SPECIFICATIONS (continued)
FILTER CONTROL CHARACTERISTICS
PARAMETE;R

10-

Filter Output Source Current

10+

Filter Output Resistance
(Single ended)

RO

Reference Voltage

VPTAT

PTAT Voltage Input

VFP

Programming Current
Range

IVFP

Programming Voltage
Range

VVBP

Voltage at pin IFP

V1FP

Power Up Time

MIN

CONDITIONS

Filter Output Sink Current

NOM

MAX

1

rnA

2

rnA

10+ = 1.0 mA
Tj

60

= 25°C

1.8

= 25°C

IvFP = 0 mA
Ic = 9 MHz
Ic

V

0.2

0.6

mA

0

VPTAT

V
V

2/3 VPTAT

1.5

= 27 MHz

Power Down Time

8-6

Q

V

2/3 VPTAT

Ta

UNIT

f.lS

1

f.lS

1

f.lS

551 32FS001/S002
Low-Power Programmable
Electron ic Filter

,.-I..J........I.-'--'-.L..J...J..--I..--I..-~~W+-_-+~w-\-\UU-l-l

10 dB/div _

®
--@

fe = 9 MHz; 0 dB Boost

\

:\

fe = 9 MHz; 13 dB Boost

\

\
\

- ' - @ fe = 27 MHz; 0 dB Boost

--@fe=27MHz;13dBBoostl++t+----t---t---+-\++N-H

100K

1M

10M

100M

FIGURE 1: 32F8001 Normal Low Pass Response

fb

~

~

~

l.",ooI .... ~

10 dB/div.
............

~

,,"
./
./

~

~

...""

~

~;

V ~tfa"
100'"

'" ~~

..~

.,)\r~

L

,

... L.
\.

~

~ ... ~

'~

J.

til'"

r..~

V

~

~

~

\

® Ie = 9 MHz; 0 dB Boost

,
\,

'C
It"

\

~

~
\

Ie = 9 MHz; 13 dB Boost
@ Ie = 27 MHz; 0 dB Boost ~
@ Ie = 27 MHz; 13 dB Boost \
@

,
\

100K

1M

10M

FIGURE 2: 32F8001 Differentiated Low Pass Response

8-7

100M

I

SSI32FS001/S002
Low-Power Programmable
Electronic Filter

b

-~

1ns/div.

~

a

®

0 dB Boost

@

13 dB Boost

-

~

je = 27 MHz

"' \

\

,
~

\
\

o

75M
7.5 MHz/div.

FIGURE 3: 32F8001 Group Delay Response with

8-8

Ie =27 MHz

SSI32FS001/S002
Low-Power Programmable
Electron ic Filter

N/C

VO_DIFF+

VO_NORM-

VO_DIFF-

VO_NORM+
VCC (+5V)
VIN-

N/C

VIN+

IFP
VFP _ _-+----1

VBP
FBST

GND

Rsp,

RBP2

VPTAT

Rx

= 1.8V (25°C)

VVFP = 2/3 (VPT AT)
IVFP range: 0.2 mA to 0.6 mA@25°C
(9 to 27 MHz no boost 32F8001)
(6 to 18 MHz no boost 32F8002)
Fixed frequency programming is accomplished as shown in the drawing above.
In this case IVFP (programming current) is equivalent to VPTAT. ~
3
Rx
i.e.,

fc = 27 MHz then
IVFP

= 0.6 mA @25°C

Rx

= 1 kQ

Fixed boost programming is also accomplished as shown above. In this case
VVBP is set by a voltage divider, where VVBP is a fraction of VPTA T.
Le.,

boost = 9 dB then,
VBP/vPTAT

= 0.488

RBP2
1
-R-= (VPTAT
BP1

---1

9 dB

= 20 log [3.73 (0.488) + 1]

) =0.953

VBP
Cx

= 1000 pF - Cx is needed for lower THD at lower fc.
FIGURE 4: 32F8001/8002 Applications Setup

8-9

I

SSI32FS001/S002
Low-Power Programmable
Electron ic Filter

INPUT

1.31703

2.95139

5.37034

S2 + S 1.68495 + 1.31703

S2+ S 1.54203 + 2.95139

S2 + S 1.14558 + 5.37034

S2 + S 1.68495 + 1.31703

Normalized for roc = (21t) Ie = 1
AN and AD are adjusted for unity gain (0 dB) at F = 0.67 Ie
Denormalize the frequency by substituting S ~ (S/21t/e)
Eq for Ie = 27 MHz, S = S I [(21t)(27 x 106 )]

FIGURE 5: 32FS001/S002 Normalized Block Diagram
TABLE 1: 32FS001/S002 Frequency Boost Calculations, K
Assuming 13 dB boost for
VBP = VPTAT

VBP

_ (10(FB/20»)_1

VPTAT=

3.73

Boost

K

VBP
VPTAT

1 dB
2 dB
3 dB
4dB
5 dB

0.16
0.34
0.54
0.77
1.03

0.033
0.069
0.110
0.157
0.209

VBP
VPTAT

---

or,
boost in dB = 20 log [3.37 (

=1.31703 (10 BOOST (dB)/20 - 1)

V~~:T ) + 1]

0.1
0.2
0.3
0.4
0.5

Boost
2.753
4.841
6.523
7.391
9.142

8-10

dB
dB
dB
dB
dB

VBP
VPTAT

Boost

K

---

6dB
7dB
8 dB
9 dB
10 dB
11 dB
12 dB
13 dB

1.31
1.63
1.99
2.40
2.85
3.36
3.43
4.57

0.267
0.332
0.405
0.488
0.580
0.683
0.799
0.929

-VBP
-VPTAT
0.6
0.7
0.8
0.9
1.0

Boost
10.206
11.153
12.006
12.784
13.5

dB
dB
dB
dB
dB

SSI32FS001/S002
Low-Power Programmable
Electron ic Filter
TABLE 2: Calculations
Typical change in 1-3 dB point with boost
Boost (dB)

Gain@/c (dB)

Gain@ peak (dB)

Ipeak/lc

1-3dB/fc

0

-3

0.00

no peak

1.00

1

-2

0.00

no peak

1.21

2

-1

0.00

no peak

1.51

3

0

0.15

0.70

1.80

4

1

0.99

1.05

2.04

5

2

2.15

1.23

2.20

6

3

3.41

1.33

2.33

7

4

4.68

1.38

2.43

8

5

5.94

1.43

2.51

9

6

7.18

1.46

2.59

10

7

8.40

1.48

2.66

11

8

9.59

1.51

2.73

12

9

10.77

1.51

2.80

13

10

11.92

1.53

2.87

14

11

13.06

1.53

2.93

Notes: 1.

2.

Ic is the original programmed cutoff frequency with no boost
1-3 dB is the new -3 dB value with boost implemented

3. Ipeak is the frequency where the amplitude reaches its maximum
value with boost implemented
Le.,

Ic = 9 MHz when boost = 0 dB

if boost is programmed to 5 dB then

1-3 dB = 19.8 MHz
Ipeak = 11.07 MHz

I
8-11

SSI32FS001/S002
Low-Power Programmable

Electronic Filter
PACKAGE PIN DESIGNATIONS
(Top View)
THERMAL CHARACTERISTICS: Sja
16-Lead SON (150 mil)

N/C

VO_DIFF+

VO_NORM-

VO_DIFF-

16-Lead SOL (300 mil)

PWRON

VO_NORM+
VCC

VPTAT

VIN-

N/C

VIN+

IFP

VBP

VFP

FBST

GND
16-Lead SON, SOL

CAUTION: Use handling procedures necessary
for a static sensitive component.

ORDERING INFORMATION
ORDER NO.

PKG.MARK

16-Lead SOL

32F8001-CL

32F8001-CL

16-Lead SON

32F8001-CN

32F8001-CN

16-Lead SOL

32F8002-CL

32F8002-CL

16-Lead SON

32F8002-CN

32F8002-CN

PART DESCRIPTION
SSI32F8001

SSI32F8002

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1992 Silicon Systems, Inc.
Protected by the following patents:
(5,063,309) (710,512) (823,067)

1294 - rev.
8-12

SSI32F8003
Low-Power Programmable
Electronic Filter

October 1994

FEATURES

DESCRIPTION

Ideal for multi-rate systems applications
Programmable filter cutoff frequency Ic 4 to
13 MHz

The SSI 32F8003 Programmable Electronic Filter
provides an electronically controlled low-pass filter
with a separate differentiated low-pass output. A
seven-pole, low-pass filter is provided along with a
single-pole, single-zero differentiator. Both outputs
have matched delays. The delay matching is
unaffected by any amount of programmed equalization
or bandwidth. This programability combined with low
group delay variation makes the SSI32F8003 ideal for
use in constant density recording applications. Pulse
Slimming equalization is accomplished by a two-pole,
low-pass with a two-pole, high-pass feed forward
section to provide complimentary real axis zeros. A
variable attenuator is used to program the zero
locations.

=

Programmable pulse slimming equalization
(0 to 13.5 dB boost at the filter cutoff frequency)
Matched normal and differentiated low-pass
outputs
Differential filter inputs and outputs
±13% cutoff frequency accuracy
±2% maximum group delay variation from
0.2 Ic to Ic
Total harmonic distortion less than 1%
No external filter components required

The SSI 32F8003 programmable equalization and
bandwidth characteristics can be controlled by
external DACs. Fixed characteristics are easily
accomplished with three external resistors, in addition
equalization can be switched in or out by a logic Signal.
The SSI 32F8003 requires only a +5V supply and is
available in 16-lead SON and SOL packages.

+5V only operation
16-lead SON and SOL package
Pin compatible with S81 32F8011

PIN DIAGRAM

BLOCK DIAGRAM
VIN+

VO_NORM+

N/C

VO_DIFF+

VIN- u-......,~'-:--.,..,._-'

VO_NORM-

VO_NORM-

VO_DIFF-

VO_NORM+

PWRON

VO_DIFF+
VO_DIFF-

VBPUP~~~~----~

VPTAT

IFP

vcc

VPTAT

VIN-

N/C

VIN+

IFP

VBP
FBST

VFP
GND

VFP c;:r---'-'-~~=:J
PWRON

FBST

16·Lead SOL, SON

CAUTION: Use handling procedures necessary
for a static sensitive component.

1094 - rev.

8-13

I

SSI32F8003
Low-Power Programmable
Electronic Filter
FUNCTIONAL DESCRIPTION

If the SSI32FB003 cutoff frequency is set using voltage
VPTAT to bias up a resistor tied to pin VFP, the cutoff
frequency is relatedtothe resistor value by the following
formulas.

The SSI32FB003 is a high performance programmable
electronic filter. It features a 7-pole 0.05° equiripple
linear phase filterwith matched normal and differentiated
outputs.

Ic (ideal, in MHz) = 21.67 • IFP = 21.67· 1.B/(3 • Rx)
Rx in kQ

CUTOFF FREQUENCY PROGRAMMING

If pin VFP is used to program cutoff frequency, pin IFP
should be left open.

The SSI 32FB003 programmable electronic filter can
be set to a filter cutoff frequency from 4 to 13 MHz with
no boost.

MAGNITUDE EQUALIZATION PROGRAMMING

Cutoff frequency programming can be established
using either a current source fed into pin IFP whose
output current is proportional to the SSI 32FB003
output reference voltage VPTAT, or by means of an
external resistor tied from the output voltage reference
pin V PTATto pin VFP. The former method is optimized
using the SSI 3204661 Time Base Generator, since
the current source into pin IFP is available at the OAC
F output of the SS13204661. Furthermore, the voltage
reference input is supplied to pin VR3 of the
SSI 3204661 by the referencevoltagefromthe VPTAT
pin of the SSI 32FB003. This reference voltage is
internally generated by a band-gap circuit in conjunction
with a temperature varying reference to create a voltage
which is proportional to absolute temperature.

The magnitude equalization, measured in dB, is the
amount of high frequency peaking atthe cutofffrequency
relative to the original-3 dB point. For example, when
12 dB boost is applied, the magnitude resP9nse peaks
up 9 dB at Ic above the OC gain.
The amplitude of the input signal at frequencies near
the cutoff frequency can be increased using this feature.
Applying an external voltage to pin VBP which is
proportional to reference output voltage VPTAT
(provided by the VPTAT pin) will set the amount of
boost. A fixed amount of boost can be set by an
external resistor divider network connected from pin
VBPto pins VPTATandGNO. No boost is applied if pin
FBST, frequency boost enable, is at a low logic level.
The amount of boost FB at the cutoff frequency
related to the voltage VBP by the formula

The VPTAT voltage will compensate for internal
temperature variation of the Ic and boost circuits.

Ic is

FB (ideal, in dB) = 20 log1o[3.73(VBPIVPTAT)+1],
where < VBP < VPT AT.

The cutoff frequency, determined by the -3dB point
relative to a very low frequency value « 1 kHz), is
related to the current IVFP injected into pin IFP by the
following formulas.

a

a

POWER ON I OFF
The SSI 32FB003 supports a power down mode for
minimal idle mode power dissipation. When PWRON
is pulled up to TTL logic high, the device is in normal
operation mode. When PWRON is pulled down to
TTL logic low, or left open, the device is in the power
down mode.

Ic (ideal, in MHz) = 21.67 • IFP = 21.67 • IVFP • 1.B/
VPTAT
where IFP and IVFP are in mA, VPTAT is in volts, Ta
= 25°C and 0.1B5 :::; IFP :::; 0.6 mA for FB003.
If a current source is used to inject current into pin IFP,
pin VFP should be left open.

8-14

SSI32F8003
Low-Power Programmable
Electronic Filter
PIN DESCRIPTION
NAME

VIN+, VINVO_NORM+,
VO_NORMVO_DIFF+,
VO_DIFF-

TYPE

I

°
°

DESCRIPTION

Differential Signal Inputs. The input signals must be AC coupled to these pins.
Differential Normal Outputs. The output signals must be AC coupled.
Differential Differentiated Outputs. For minimum time skew, these outputs
should be AC coupled.

IFP

I

Frequency Program Input. The filter cutoff frequency fc, is set by an external
current IFP, injected into this pin. IFP must be proportional to voltage VPTAT.
This current can be set with an external current generator such as a DAC. VFP
should be left open when using this pin.

VFP

I

Frequency Program Input. The filter cutoff frequency can be set by programming a current through a resistor from VPTAT to this pin. I FP should be left
open when using this pin.

VBP

I

Frequency Boost Program Input. The high frequency boost is set by an
external voltage applied to this pin. VBP must be proportional to voltage
VPTAT. A fixed amount of boost can be set by an external resistor divider
network connected from VBP to VPTAT and GND. No boost is applied if the
FBST pin is grounded, or at logic low.

FBST

I

Frequency Boost. A high logic level or open enables the frequency boost
circuitry. A low input disables this function.

PWRON

I

Power On. A high logic level enables the chip. A low level or open pin puts the
chip in a low power state.

VPTAT

°

PTAT Reference Voltage. This pin outputs a reference voltage w~ich is
proportional to absolute temperature (PTAT). VBP, VFP or IFP must be
referenced to this pin for proper operation.

VCC

°I

+5 Volt Supply.

GND

Ground

ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may damage the device.
PARAMETER

RATINGS

Storage Temperature

-65°C to + 150°C

Junction Operating Temperature, Tj

+130°C

Supply Voltage, VCC

-O.5V to 7V

Voltage Applied to Inputs

-O.5V to VCC

8-15

I

SSI32F8003
Low-Power Programmable
Electron ic Filter
ELECTRICAL SPECIFICATIONS (continued)
RECOMMENDED OPERATING CONDITIONS
RATINGS

PARAMETER

vcc

Supply voltage
Ambient Temperature

4.50V < VCC < 5.50V

Ta

O°C < Ta < 70°C

ELECTRICAL CHARACTERISTICS
Unless otherwise specified recommended operating conditions apply.

Power Supply Characteristics
NOM

MAX

UNIT

Power Supply Current

ICC

CONDITIONS
PWRON

$;

0.8V

0.1

0.5

mA

Power Supply Current

ICC

PWRON

~

2.0V

46

60

mA

= 5.0V
PWRON ~ 2.0V, VCC = 5.5V

230

300

mW

275

330

mW

PWRON

0.5

2.5

mW

PARAMETER

Power Dissipation

PD

MIN

PWRON ~ 2.0V, VCC

$;

0.8V

DC Characteristics
High Level Input Voltage

VIH

Low Level Input Voltage

VIL

High Level Input Current

IIH

VIH = 2.7V

Low Level Input Current

ilL

VIL = OAV

V

2

TIL input

0.8

V

20

~
mA

4

13

MHz

-13

+13

0.8

1.2

V/v

0.8AO

1.2AO

V/v

-1.5

Filter Characteristics
Filter Cutoff Frequency

*fc

fc

*(f -3d8)
Filter Ie Accuracy

FCA

VO_NORM Diff Gain

AO

VO_DIFF Diff Gain

AD

Frequency Boost at fc

FB

fc

=

21.67 MHz (IVFP)
rnA

max.

= 0 dB
F = 0.67 fc, FB = 0 dB
VBP = VPTAT
fc = max.
F = 0.67 fc, FB

12

13.5

15

dB

min.

11.5

13

14.5

dB

= 1.0 le= max.

-1.5

1.5

dB

fc
Frequency Boost Accuracy FBA

VBP/vPTAT

%

8-16

=

SSI32F8003
Low-Power Programmable
Electron ic Filter
FILTER CHARACTERISTICS

(continued)

PARAMETER
Group Delay Variation
Without Boost (continued)

MIN

CONDITIONS
TGDO

NOM

MAX

UNIT

VBP =0
VPTAT

-1

+1

ns

VBP =0
VPTAT

-3

+3

ns

~=o

-2

+2

%

~=o

-3

+3

0/0

fe = max, VBP = VPTAT
F = 0.2 fc to fe
fe = min, VBP = VPTAT
F = 0.2 to fc
F = 0.2 fe TO fe, VBP = VPTAT

-1

+1

ns

-3

+3

ns

-2

+2

0/0

F = fe to 1.75 fe, VBP = VPTAT

-3

+3

THD =1% max, F =0.67 fe, VBP =OV
(1000 pF across Rx)

1

Vp-p

THD =1.5% max, F=0.67 fe, VBP =OV,
Normal output (1000 pF across Rx)

1.5

Vp-p

THD =2.0% max, F=0.67 fe, VBP =OV,

1.5

Vp-p

fc

= max,

F = 0.2 fc to

fc

fe

= min,

F = 0.2 fc to

fe
F = 0.2 fc to fe,

VPTAT

F=

fc to

1.75 fe

VPTAT

Group Delay Variation
With Boost

TGDB

Filter Input Dynamic Range VIF

Filter Input Dynamic Range VIF

%

Differentiated output
(1000 pF across Rx)
Filter Diff Input Resistance

RIN

Filter Input Capacitance

CIN

Output Noise Voltage
Differentiated Output

EOUT

3

4.3

kO
7

BW = 100 MHz, Rs = 500
fc = max, VBP = OV

3

pF
mVrms

I
8-17

SSI32F8003
Low-Power Programmable
Electronic Filter
ELECTRICAL SPECIFICATIONS (continued)
FILTER CONTROL CHARACTERISTICS
PARAMETER

MIN

CONDITIONS

Output Noise Voltage
Normal Output

EOUT

Output Noise Voltage
Differentiated Output

EOUT

Output Noise Voltage
Normal Output

EOUT

= 100 MHz, Rs = 50n
fe = max, VBP = OV
BW = 100 MHz, Rs = 50n
fe = max, VBP = VPTAT
BW = 100 MHz, Rs = 50n
fc = max, VBP = VPTAT
BW

NOM

MAX

UNIT

1.8

mVrms

4.3

mVrms

2.2

mVrms

10-

1

mA

Filter Output Source Current

10+

2

mA

Filter Output Resistance
(Single ended)

RO

Filter Output Sink Current

Reference Voltage

VPTAT

PTAT Voltage Input

VFP

Programming Current
Range

IVFP

Programming Voltage
Range

VVBP

Voltage at pin IFP

V 1FP

Power Up Time

10+ = 1.0 mA
Tj

60

= 25°C

1.8

V

2/3 VPTAT
Ta

= 25°C

,vFP = 0 mA
fC = min

V

0.185

0.6

mA

0

VPTAT

V

2/3 VPTAT

fe = max

V
1.5

I...IS

1

Ils
IlS

1

Power Down Time

8-18

n

SSI32F8003
Low-Power Programmable
Electronic Filter

N/C

VO_DIFF+

VO_NORM-

VO_DIFF-

VO_NORM+
VCC (+5V)
VIN-

N/C

VIN+

IFP

VBP

VFP-----~

FBST

R,

GND

RBP1

RBP2

VPTAT

= 1.8V (25°C)

VVFP = 2/3 (VPTAT)
IVFP range: 0.185 mA to 0.6 mA@25°C
Fixed frequency programming is accomplished as shown in the drawing above.
In this case IVFP (programming current) is equivalent tOVPTAT

1

_ _ 0-

i.e.,

3

jc = 13 MHz then
IVFP

= 0.6 mA @25°C

Rx

Rx

= 1 kQ

Fixed boost programming is also accomplished as shown above. In this case
VVBP is set by a voltage divider, where VvBP is a fraction of VPT AT.
i.e.,

boost = 9 dB then,

9 dB = 20 log [3.73 (0.488) + 1]
1
(VPTAT
)=0.953
BP1
---1
VBP
Cx = 1000 pF - Cx is needed for lower THO at lower fc.
VBP/vPTAT

= 0.488

RBP2

R

FIGURE 4: 32F8003 Applications Setup

8-19

I

SSI32F8003
Low-Power Programmable
Electronic Filter

1.31703

INPUT

2.95139

5.37034

S2+ S 1.54203 + 2.95139

S2+ S 1.14558 + 5.37034

S2+ S 1.68495 + 1.31703

Normalized for (J)c = (21t) jc = 1
AN and AD are adjusted for unity gain (0 dB) at F = 0.67 jc
Denormalize the frequency by substituting S ~ (S/21tjc)
Eq for jc = 27 MHz, S = S / [(21t)(27 x 10 6)]

FIGURE 5: 32F8003 Normalized Block Diagram
TABLE 1: 32F8003 Frequency Boost Calculations, K

Assuming 13.5 dB boost for
VBP = VPTAT
VBP
VPTAT

( 10 (FB/20)) - 1
3.73

Boost

K

VBP
-VPTAT

1 dB
2dB
3 dB
4dB
5dB

0.16
0.34
0.54
0.77
1.03

0.033
0.069
0.110
0.157
0.209

-VBP
--

Boost

VPTAT

or,

boost in dB =20 log [3.73

=1.31703 (1 oB°OST (dB)/20 - 1)

(V~~:T ) +1]

0.1
0.2
0.3
0.4
0.5

2.753
4.841
6.523
7.391
9.142

8-20

dB
dB
dB
dB
dB

VBP
VPTAT

Boost

K

---

6dB
7dB
8dB
9dB
10 dB
11 dB
12 dB
13 dB

1.31
1.63
1.99
2.40
2.85
3.36
3.43
4.57

0.267
0.332
0.405
0.488
0.580
0.683
0.799
0.929

VBP
VPTAT

--0.6
0.7
0.8
0.9
1.0

Boost

10.206
11.153
12.006
12.784
13.5

dB
dB
dB
dB
dB

SSI32F8003
Low-Power Programmable
Electronic Filter
TABLE 2: Calculations
Typical change in j-3 dB pOint with boost
Boost (dB)

Gain@fc (dB)

Gain@ peak (dB)

fpeak/fc

f-3dB/fc

0

-3

0.00

no peak

1.00

1

-2

0.00

no peak

1.21

2

-1

0.00

no peak

1.51

3

0

0.15

0.70

1.80

4

1

0.99

1.05

2.04
2.20

5

2

2.15

1.23

6

3

3.41

1.33

2.33

7

4

4.68

1.38

2.43

8

5

5.94

1.43

2.51

9

6

7.18

1.46

2.59

10

7

8.40

1.48

2.66

11

8

9.59

1.51

2.73

12

9

10.77

1.51

2.80

13

10

11.92

1.53

2.87

14

11

13.06

1.53

2.93

Notes: 1. jc is the original programmed cutoff frequency with no boost

2. j-3 dB is the new -3 dB value with boost implemented
3. jpeak is the frequency where the amplitude reaches its maximum
value with boost implemented
Le., jc = 9 MHz when boost = 0 dB
if boost is programmed to 5 dB then

j-3 dB = 19.8 MHz
jpeak

= 11.07 MHz

I
8-21

SSI32F8003
Low-Power Programmable
Electron ic Filter
PACKAGE PIN DESIGNATIONS
(Top View)
THERMAL CHARACTERISTICS: 9ja
16-lead SON (150 mil)

N/C

VO_DIFF+

VO_NORM-

VO_DIFF-

VO_NORM+

16-lead SOL (300 mil)

100°CIW

PWRON

VCC

VPTAT

VIN-

N/C

VIN+

IFP

VBP

VFP

FBST

GND

16-Lead SON, SOL

CAUTION: Use handling procedures necessary
for a static sensitive component.

ORDERING INFORMATION
PART DESCRIPTION
SSI32F8003

ORDER NUMBER

PACKAGE MARK

16-Lead SOL

32F8003-CL

32F8003-CL

16-Lead SON

32F8003-CN

32F8003-CN

Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914

©1993 Silicon Systems, Inc.
Protected by the following patents:
(5,063,309) (710,512) (823,067) (5,182,477)

8-22

1094 - rev.

SSI32F8101
Low-Power Programmable Filter

January 1995

DESCRIPTION

FEATURES

The 32F8101 is a high performance, low power,
digitally programmable low-pass filter for applications
requiring variable-frequency filtering. The device
consists ofthreefunctional blocks: [1] a 7th-order 0.05°
Equiripple Low-Pass filter, [2] two DACs for controlling
the filter cutoff frequency and high-frequency peaking
(boost), and [3] a Serial Port for programming the Ic
and Boost DACs.

•

Programmable cutoff frequency - 8.9 to 27 MHz

•

Programmable boost/equalization of 0 to
14.6 dB
Matched normal and differentiated outputs
±15% Ic accuracy
±2% maximum group delay variation

Cutoff frequency and boost are controlled by the two
on-chip 7 -bit DACs, which are programmed via the 3line serial interface. Boost is programmable from 0 to
14.6 dB nominally at maximum fc, and is implemented
using two symmetrical, real-axis zeroes. Both boost
and fc control do not affect the flat group delay
response.

•

Less than 1.5% total harmonic distortion

•

Low-Z input switch controlled by LOWZ pin

•

No external filter components required
95 mW nominal power, <5 mW idle

The 32F81 01 device is ideal for variable data rate and
variable frequency shaping applications. It requires
only a +5V supply and has an idle mode for minimal
power dissipation. The SSI 32F8101 is available in a
16-lead SON package.

PIN DIAGRAM

BLOCK DIAGRAM
VOJ'JORM.
VO_NORM

VIN-

VO_D1FF+

DGND

16

VO_DIFF+

VO_NORM-

15

VO_DIFF-

VO_NORM+

14

AX

VCA

13

SCLK

VIN-

12

VCD

VIN+

11

SDEN

SG

10

SDI

VO.OIFF
LOWZ

SG

AGND

LOWZ

16-Lead SON

veA AGNO

0195 - rev.

VCO OGNO

SOEN

SOl

CAUTION: Use handling procedures necessary
for a static sensitive component

SCLK

8-23

I

SSI32F8101
Low-Power Programmable Filter

FUNCTIONAL DESCRIPTION

FILTER OPERATION

The SSI 32F8101 programmable filter consists of an
electronically controlled low-pass filter with a separate
differentiated low-pass output. A seven-pole, low-pass
filter is provided along with a single-pole, single-zero
differentiator. Both outputs have matched delays. The
delay matching is unaffected by any amount of
programmed equalization or bandwidth. Programmable
ba~dwidth and boosVequalization is provided by internal
7-bIt control DACs. High-frequency boost equalization
is accomplished by a two-pole, low-pass with a twopole, high-pass feed forward section to provide
complimentary real axis zeros. A variabl~ attenuator is
used to program the zero locations.

Normally AC coupled differential signals are applied to
the VIN± inputs of the filter, although DC coupling can
be implemented. To improve settling time ofthe coupling
capacitors, the VIN± inputs are placed into a Low-Z
state when the [OWZ pin is brought low. The
programmable bandwidth and boost/equalization
features are controlled by internal DACs and the
registers programmed through the serial port. The
current reference for both DACs is set using a single
13.3 kQ external resistor connected from pin RX to
ground. The voltage at pin RX is proportional to absolute
temperature (PTAT), hence the current forthe DACs is
a PTAT reference current.

The filter implements a 0.05 degree equiripple linear
phase response. The normalized transfer functions
(Le., roc = 2rcfc = 1) are:

Bandwidth Control

VnormlVi

The programmable bandwidth is set by the filter cutoff
DAC. This DAC has two separate 7-bit registers that
can program the DAC value as follows:

= 13.65983· [(_KS2 + 1.31703)/D(s)] • AN

Ie =0.2133 • DACF - 0.094

and
VdiffNi

= (VnormlVi) • (s/0.86133)

Where D (5)=

The filter cutoff set by the internal DAC is the unboosted
3 dB frequency. When boost/equalization is added, the
actual 3 dB point will move out. Table 1 provides
information on boost versus 3 dB frequency.

(S2+ 1.68495s+1.31703)(S2+1.54203 s+2.95139)
(S2+ 1 .4558s+5.37034)(s+0.86133),
AN and AD are adjusted for a gain of 1 at fs=(2/3)fc.

INPUT

(MHz)

where DACF = Cutoff Frequency Control Register
value (deCimal)

• AD

1.31703

2.95139

5.37034

S2 + S 1.68495 + 1.31703

S2+ S 1.54203 + 2.95139

S2 + S 1.14558 + 5.37034

S2+ S 1.68495 + 1.31703

Normalized for roc = (2n) fc = 1
AN and AD are adjusted for unity gain (0 dB) at F = 0.67 fc
Denormalize the frequency by substituting S --+ (S/2nfc)
Eq for fc = 27 MHz, S = S / [(2n)(27 x 106 )]

FIGURE 1:

32F8~01

Normalized Block Diagram

8-24

551 32F8101
Low-Power Programmable Filter

TABLE 1: Calculations
Typical change in f-3 dB point with boost
Boost (dB)

Gain@jc (dB)

Gain@ peak (dB)

jpeak/jc

j-3 dB/jc

0

-3

no peak

no peak

1.00

0

1

-2

no peak

no peak

1.21

0.16
0.34

K

2

-1

no peak

no peak

1.50

3

0

0.15

0.70

1.80

0.54

4

1

0.99

1.05

2.04

0.77

5

2

2.15

1.23

2.20

1.03

6

3

3.41

1.33

2.33

1.31

7

4

4.68

1.38

2.43

1.63

8

5

5.94

1.43

2.51

1.97

9

6

7.18

1.46

2.59

2.40

10

7

8.40

1.48

2.66

2.85

11

8

9.59

1.51

2.73

3.36

12

9

10.77

1.51

2.80

3.93

13

10

11.92

1.53

2.87

4.57

14

11

13.06

1.53

2.93

5.28

15

12

14.18

1.56

3.0

6.09

Notes: 1. jc is the original programmed cutoff frequency with no boost

2. j-3 dB is the new -3 dB value with boost implemented
3. jpeak is the frequency where the amplitude reaches its maximum
value with boost implemented

i.e., jc

= 9 MHz when boost = 0 dB

if boost is programmed to 5 dB then

j-3 dB = 19.8 MHz
jpeak

4. K

= 1.31703 (10

BOOST (dB)

20

-

1)

8-25

= 11.07 MHz

I

SSI32F8101
Low-Power Programmable Filter

BOOST/EQUALIZATION CONTROL

Afterthe SDEN goes high, the first 16 pulses applied to
the SCLK pin will shift the data presented at the SDATA
pin into an internal shift register on the rising edge of
each clock. An internal counter prevents more than 16
bits from being shifted into the register. The data in the
shift register is latched when SDEN goes low. If less
than 16 clock pulses are provided before SDEN goes
low, the data transfer is aborted.

The programmable equalization is also controlled by
an internal DAC. The 7 -bit Filter Boost Control Register
(FBCR) determines the amount of equalization that will
be added to the 3 dB cutoff frequency, as follows:
Boost

=

20 log [(0.0239· DACB) + 7.6.10- 5 • DACB· DACF) +
1.132]
where DACB

All transfers are shifted into the serial port LSB first. The
first byte of the transfer is address and instruction
information. The LSB of this byte is the R/W bit which
determines if the transfer is a read (1) ora write (0). The
remaining seven bits determine the internal register to
be accessed. The second byte contains the
programming data. At initial power-up, the contents of
the internal registers will be in an unknown state and
they must be programmed prior to operation. During
power down modes, the serial port remains active and
register programming data is retained.

= value in FBCR register.

For example, with the DAC set for maximum output
(FBCR =7F hex or 127) atthe maximum cutofffrequency
(DACF = 7F hex or 127) there will be 14.6 dB of boost
added at the 3 dB frequency. This will result in + 11 dB
of signal boost above the 0 dB baseline.

SERIAL INTERFACE OPERATION
The serial interface is a CMOS bi-directional port for
reading and writing programming data from/to the
internal registers of the 32F8101. For data transfers
SDEN is brought high, serial data is presented at the
SDATA pin, and a serial clock is applied to the SCLK
pin.

SDE~
SDAT~
~

ADDRESS,~BIT

>-<

L

DATA8-BIT

>--

FIGURE 2: Serial Port Data Transfer Format
Load data
into Register

SDEN
SCLK

~

1.......1
1
1
1

SDATA setup
wrt SCLK rises

~DEN

setup
wrt SCLK rises

1
1

:--t-:
1

1

1

L

I

SDEN hold
;1 wrt
to SCLK rises
1 1

: - : SCLK period

SDATA hold
wrt SCLK rises

SDATA

FIGURE 3: Serial Interface Timing Diagram - Writing Control Register
8-26

TABLE 2: Serial Port Register Mapping
REGISTER NAME

ADDRESS

~

~ ~

DO

-

-

-

-

-

DAC
BIT 6

DAC
BITS

DAC
BIT4

DAC
BIT3

DAC
BIT2

DAC
BIT 1

DAC
BIT 0

1 0

.
.

FILTER
1=DISABLE
O:ENABLE

DAC
BIT6

DAC
BITS

DAC
BIT 4

DAC
BIT3

DAC
BIT2

DAC
BIT 1

DAC
BITO

0 1 0 1

1 0

-

DAC
BIT 6

DAC
BITS

DAC
BIT 4

DAC
BIT3

DAC
BIT 2

DAC
BIT 1

DAC
BIT 0

1

1 0

-

DAC
BIT 6

DAC
BITS

DAC
BIT4

DAC
BIT3

DAC
BIT2

DAC
BIT1

DAC
BITO

POWER DOWN CONTROL

o

0 0 0 0 1

DATA MODE CUTOFF

o

0

o

0 0 1

1 0

SERVO MODE CUTOFF

o

0

1

0 0 1

FILTER BOOST, DATA

0 0

FILTER BOOST, SERVO

o

0

DATA BITMAP

D7

1

0 1

o

0

-

* These bits are used only for testing. They should be programmed to 0 in actual operation.

(l)

r\,
-...j

r-

o

:e
I

-C

o

:eCD

""I

-c
""I

o
c.c
""I

Q)

3CJ)
3CJ)
1»C"w

-I\)

_

CD."

.,,(X)
.......

::::;'0

CD
......
""I

SSI32F8101
Low-Power Programmable Filter

PIN DESCRIPTION
POWER SUPPLY PINS
NAME

TYPE

DESCRIPTION

VCA

-

Filter analog power supply pin
Serial port power supply pin

VCD

-

AGND

-

Filter analog ground pin

DGND

-

Serial port digital ground pin

VIN+, VIN-

I

FILTER SIGNAL INPUTS: The AGC output signals must be AC coupled into
these pins.

SG

I

SERVO GATE: TTL input when high enables servo frequency and boost
registers to the control DACs. When low the data frequency and boost
registers are enabled.

LOWZ

I

LOW_Z CONTROL: TTL input when low reduces the filter input resistance.
When high, the input is at high impedance state.

VO_DIFF+,

0

DIFFER ENTIAL DIFFERENTIATED OUTPUTS: Filterdifferentated VO_01 FFoutputs. These outputs are normally AC coupled.

VO_NORM+,

0

DIFFERENTIAL NORMAL OUTPUTS: Filter normal low pass output signals.
VO_NORM- These outputs are normally AC coupled.

RX

-

REFERENCE RESISTOR INPUT: An external 13.3 kn, 1% resistor is connected from this pin to ground to establish a precisePT AT (proportional to
absolute temperature) reference current for the filter.

SDEN

1/0

SERIAL DATA ENABLE: Serial enable CMOS compatible input. A high level
input enables the serial port.

SOl

1/0

SERIAL DATA: Serial data CMOS compatible input. NRZ programming data
for the internal registers is applied to this input.

SCLK

1/0

SERIAL CLOCK: Serial clock CMOS compatible input. The clock applied to
this pin is synchronized with the data applied to SDATA.

INPUT PINS

OUTPUT PINS

SERIAL PORT PINS

8-28

551 32F8101
Low-Power Programmable Filter

ELECTRICAL SPECIFICATIONS
Unless otherwise specified, the recommended operating conditions are as follows: 4.5V < POSITIVE
SUPPLY VOLTAGE < 5.5V, O°C < T (ambient) < 70°C, and 25°C < T(junction) < 135°C. Currents flowing into
the chip are positive. Current maximums are currents with the highest absolute value.
Rx = 13.3 kn, Cx = 1000 pF from Rx pin to VCA. Input signals are AC-coupled into VIN±.

ABSOLUTE MAXIMUM RATINGS
Operation beyond the maximum ratings may damage the device.
PARAMETER

RATING

Storage Temperature

-65 to 150°C

Junction Operating Temperature

+130°C

Positive Supply Voltage (Vp)

-0.5 to 7V

Voltage Applied to Logic Inputs

-0.5V to Vp + 0.5V

All other Pins

-0.5V to Vp + 0.5V

POWER SUPPLY CURRENT AND POWER DISSIPATION
PARAMETER

CONDITIONS

MIN

NOM

MAX

UNITS

ICC (VCA,D)

Output pins open
DACF = 127
Boost = 0 dB

19

30

rnA

PWR Power Dissipation

Output pins open
DACF = 127
Boost = 0 dB

95

165

mW

Sleep Mode Power

PWRON = 1

5

mW

TTL COMPATIBLE INPUTS
I nput low voltage

VIL

-0.3

0.8

V

Input high voltage

VIH

2

VPD

V

+0.3
Input low current

ilL

VIL

Input high current

IIH

VIH

= O.4V
= 2.4V

rnA

-0.4
100

(JA

CMOS COMPATIBLE INPUTS
Input low voltage

Vp=5V

-0.3

1.5

V

Input high voltage

Vp= 5V

3.5

VCD
+0.3

V

8-29

I

SSI32F8101
Low-Power Programmable Filter

ELECTRICAL SPECIFICATIONS (continued)
SERIAL PORT
PARAMETER

CONDITIONS

MIN

SCLK period

Read from serial port

140

ns

Write to serial port

100

ns

SCLK low time

TCKL

SCLK high time

TCKH

NOM

MAX

UNITS

Read from serial port

60

ns

Write to serial port

40

ns

Read from serial port

60

ns

Write to serial port

40

ns

Enable to SCLK

TSENS

35

ns

SCLK to disable

TSENH

100

ns

Data set-up time

TDS

15

ns

Data hold time

TDH

15

ns

SDATA tri-state delay TSENDL
SDATA turnaround time

50

ns

TTRN

70

ns

TSL

200

ns

SDEN low time

PROGRAMMABLE FILTER CHARACTERISTICS

fc @ -3 dB point
fc = (0.2133 MHz)

Filter cutoff range

XDACF - 0.0941, Boost
42:<:; DACF:<:; 127

AN

FDP, FDN differential gain

AD

Boost accuracy
Boost

= 20

log

[(0.0239· DACB) +
(7.6·

10- 5 •

DACB • DACF)

+ 1.132]

27

MHz

= 0 dB
15

a/a

f = 0.67xfc, boost = 0 dB

0.7

1.0

1.25

V/V

f = 0.67xfc, boost = 0 dB

0.8AN

1.0 AN

DACF

Filter cutoff accuracy
FNP, FNN differential gain

8.9

= 42

and 127

6.6 dB, DACF

= 42, DACS = 37

= 127, DACS = 37
9.4 dB, DACF = 42, DACS = 67
10.6 dB, DACF = 127, DACS = 67
13.2 dB, DACF = 42, DACS = 127
14.6 dB, DACF = 127, DACS =127

7.5 dB, DACF

-15

1.2 AN

V/V

-1.0

+1.0

dB

-1.0

+1.0

dB

-1.25

+1.25

dB

-1.25

+1.25

dB

1.5

+1.5

dB

-1.5

+1.5

dB

+2

a/a

+3

%

Data mode group delay

f = 0.2 fc to fC

-2

variation, DACF = 42 to 127,
DACS = 0 to 127

f=fcto 1.75fc

-3

8-30

SSI32F8101
Low-Power Programmable Filter

PROGRAMMABLE FILTER CHARACTERSITICS (continued)
PARAMETER

CONDITIONS

MIN

MAX

UNITS

Data mode group delay

DACF = 127

-0.5

+0.5

ns

-1.25

+1.25

ns

-0.95

+0.95

ns

-1.9

+1.9

ns

variation, DACS

= 0 to 127

f

=

NOM

0.2 fc to fc

DACF

= 42

f = 0.2 fc to fc
DACF = 127

f=fcto1.75fc
DACF

= 42

f=fct01.75fc
Filter differential output
dynamic range
Filter differential input resistance

THO = 1.5%, f = 0.67fc
boost = 0 dB,
normal and differentiated outputs

1

Normal

4

Low-Z

Vp-p

kQ
200

Filter differential input capacitance
Output Noise Voltage: BW = 100 MHz, Rs

400

0

7

pF
mV Rms

= 500

differentiated output

fc

=

27 MHz, boost = 0 dB

4.4

6.6

differentiated output

fc

=

27 MHz, DACS

= 127

7.7

11.6

mV Rms

normal output

fc = 27 MHz, boost

0 dB

2.5

3.8

mV Rms

normal output

fc

3.7

5.6

mV Rms

=

=

27 MHz, DACS = 127

Filter output sink current

0.5

Filter output offset voltage

-200

Filter output source current

2.0

rnA
200

mV
rnA

Filter output resistance

single ended

Rx pin voltage

Ta

= 2rC
Ta = 127°C

600

200

mV

800

mV

Rx resistance

1% fixed value

13.3

kO

8-31

0

I

SSI32F8101
Low-Power Programmable Filter

--.J.

~------------~11~------------------------~

SDEN

SCLK

RIW

r~~~~)~

RIW

ADDRO

/

ADDRO

ADDR6

00

ADDR6

/

00

DATA?

}-

FIGURE 4: Serial Port Timing Information
THERMAL CHARACTERISTICS: 9ja

PACKAGE PIN DESIGNATIONS
(Top View)

16-lead SON
DGND

16

VO_DIFF+
VO_DIFF-

VO_NORM-

15

VO_NORM+

14

AX

VCA

13

SCLK

VIN-

12

VCD

VIN+

11

SDEN

SG

10

1000 C/W

SDI
AGND

LOWZ

CAUTION: Use handling procedures necessary
for a static sensitive component.

16·Lead SON

ORDERING INFORMATION
PART DESCRIPTION
SSI32F8101

16-Lead SON

ORDER NUMBER
32F8101-CN

PACKAGE MARK
32F8101-CN

Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or tradem'arks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914

0195 - rev.

8-32

©1993 Silicon Systems, Inc.
Protected by the following patents:
(5,063,309) (710,512) (823,067)

SSI32F8120
Low-Power Programmable
Electronic Filter
January 1994

DESCRIPTION

FEATURES

The SSI32F8120 is a continuous time, low pass filter
with programmable bandwidth and high frequency
boost. The lowpassfilterisa2zero!7pole 0.05° phase
equiripple type, featuring excellent group delay
characteristics. It features 1.5 - 8 MHz programmable
bandwidth and 0-10 dB programmable boost. Both
functions are controlled by 7-bit command words,
which are input via a 3-line serial interface.

Programmable filter cutoff frequency (fc =1.5
to 8 MHz) with no external components
Programmable pulse slimming equalization
(0 to 10 dB boost at the filter cutoff frequency)
± 10% cutoff frequency accuracy
Matched normal and differentiated low-pass
outputs
Differential filter inputs and outputs
Device Idle mode
+5V only operation
No external filter components required
Supports constant density recording

BLOCK DIAGRAM

PIN DIAGRAM
VO_NORM+

16

VO_OIFF+

VO_NORM-

2

15

VO_OIFF-

VO_NORM+

3

14

RX

VCA

4

13

SCLK

VIN-

5

12

veo

VIN+

6

11

SOEN

10

SOl

OGNO

VO_NORM·

VO_OIFF+
VO_OIFFVFP

VBP

VBP
VFP

8

9

AGNO

I

RX

VCA AGNO

VCO DGNO

SOEN

SOl

SCLK

CAUTION: Use handling procedures necessary
for a static sensitive component.

0194 - rev.

8-33

SSI32F8120
Low-Power Programmable
Electron ic Filter

jc is determined by the equation:

FUNCTIONAL DESCRIPTION

jc (MHz)

CUTOFF FREQUENCY PROGRAMMING

= 0.061321 (F_Code) + 0.212264

1.5 MHz -:;, jc -:;, 8 MHz

The SSI 32F8120 programmable electronic filter can
be set to afiltercutoff frequency from 1.5 to 8 MHz. The
cutoff frequency can be set by using the serial port
through pins SDI, SDEN, and SCLK. SDI is the serial
data input for an 8-bit control shift register, SDEN is the
control register enable, and SCLK is the control register
clock. The data packet is transmitted MSB (D7) first.
The first four bits are the register address, the last four
are the data bits. Registers largerthan four bits must be
loaded with two 8-bit data packets. See Table 1.

21 -:;, F_ Code -:;, 127

SLIMMER HIGH FREQUENCY BOOST
PROGRAMMING
The amplitude of the input signal at frequencies near
the cutoff frequency can be increased using this feature.
By controlling the V-DAC output, the boost can be
determined. The amount of boost at the cutoff frequency
is related to the V-DAC output by the following formula:
[Output of V-DAC

S Code

= VBP = VREFx~]

BOOST (dB) = 20·log [0.01703 (S_Code) +1].

TABLE 1
ADDRESS BITS

USAGE

DATA BITS

D7

D6

D5

D4

D3

D2

D1

DO

X

0

0

0

S-MSB REGISTER

X

S6

S5

S4

X

0

0

1

S-LSB REGISTER

S3

S2

S1

SO

X

0

1

0

F-MSB REGISTER

X

F6

F5

F4

X

0

1

1

F-LSB REGISTER

F3

F2

F1

FO

X

1

1

1

P REGISTER

X

X

X

PO

X = Don't Care
S = 7-bit Boost (Slimming) Control
F = 7-bit Frequency (Bandwidth) Control
P = Power Down Control; PO = 1 for power up; PO = 0 for power down
clocks data brt

I

I

~ TC--J

SCLK

n

~

I.-!

L.!..-!

SDEN setup
SDEN hold
SDEN falls
wit SCLK falls I
I
I prior to SCLK
I
I wit SCLK falls
,...--1i--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----,T2B rises

SDEN
T4

~~I~~~~ falls

load data
into register

SDI

FIGURE 1: Serial Port Timing Diagram
8-34

551 32F8120
Low-Power Programmable
Electronic Filter
PIN DESCRIPTION
NAME

TYPE

DESCRIPTION

VIN+, VIN-

I

DIFFERENTIAL FILTER INPUTS. The input signals must be AC coupled to
these pins.

VO_NORM+,
VO_NORM-

0

VO_DIFF+
VO_DIFF-

0

DIFFERENTIAL DIFFERENTIATED OUTPUTS. Forminimum pulse pairing,
these outputs should be AC coupled to the pulse detector.

SDEN

I

SERIAL DATA ENABLE. A logic HIGH level allows SERIAL CLOCK to clock
data into the control register via the SERIAL OAT A input. A logic LOW level
latches the register data and issues the information to the appropriate circuitry.

SCLK

I

SERIAL CLOCK. Negative edge triggered clock input for serial register.

SOl

I

SERIAL DATA INPUT.

RX

-

REFERENCE CURRENT SET. With an external resistor (Rx = 5 kQ±1%) to
ground, this pin gives a voltage proportional to the absolute temperature,
setting the range for VFP.

DIFFERENTIAL NORMAL OUTPUTS. The output signals must be AC
coupled to the pulse detector.

VCA

I

ANALOG +5 VOLT SUPPLY.

VCD

I

DIGITAL +5 VOLT SUPPLY.

AGND

I

ANALOG GROUND.

DGND

I

DIGITAL GROUND.

_._-

VBP

0

BOOST PROGRAMMING VOLTAGE. Output of V-DAC which programs the
boost.

VFP

0

CUTOFF FREQUENCY PROGRAMMING VOL TAGE. Output of I-DAC which
programs the cutoff frequency.*

*A minimum load resistance of 150 kQ should be used to avoid affecting the total minimum on-chip resistance
of 1.35 kQ.

I
8-35

SSI32F8120
Low-Power Programmable
Electronic Filter
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may damage the device.
PARAMETER

RATING

Storage Temperature

-65 to + 150°C

Junction Operating Temperature, Tj

+130 o e

---

Supply Voltage,

--

vee

-0.5 to 7V

Voltage Applied to Inputs*
Maximum Power Dissipation, jc

-0.5 to vee v

= 8 MHz, Vee = 5.5V

T1 Lead Temperature (1/16" from case for 10 seconds)

0.5W

--_._--

260°C

* Analog input signals of this magnitude shall not cause any change or degradation in filter performance after
sigmi'l has returned to normal operating range.
RECOMMENDED OPERATING CONDITIONS
Supply voltage, vee

4.5V < vee < 5.5V

Ambient Temperature

o°e < Ta < 70°C
o°e < Tj < 130°C

Tj Junction Temperature

ELECTRICAL CHARACTERISTICS
Unless otherwise specified recommended operating conditions apply.
NOM

MAX

55

75

rnA

9

13

rnA

Idle to Active Mode Recovery Time

50

IlS

Serial port program to output
response time

50

Ils

0.8

V

MIN

PARAMETER

CONDITIONS

Isupply

vee = 5.5V, outputs unloaded

Idle Mode Current

UNIT

DC Characteristics
VIH

High Level Input Voltage

VIL

Low Level Input Voltage

IIH

High Level Input Current

ilL

Low Level Input Current

2.0

TIL input

V
-- ---

= 2.7V
VIL = O.4V

20

VIH

-1.5

8-36

J.lA
rnA

SSI32F8120
Low-Power Programmable
Electronic Filter
Filter Characteristics
PARAMETER

CONDITIONS

MIN

Ic

21 ::; F_Code::; 127

1.5

Filter Ic Accuracy

= 127
F_Code = 21

-10
-15

Cutoff Resolution

1.5to 8 MHz

100

Ic
F = 0.67 Ic

0.7

1.1

VN

0.90 AO

1.2AO

VN

0

10

dB

-1.5

+1.5

dB

-1

+1

dB

-2%
gdm

+2%
gdm

ns

-3%
gdm

+3%
gdm

ns

-2%
gdm

+2%
gdm

ns

-3%
gdm

+3%
gdm

ns

Filter Cutoff Frequency

FCA

AO

VO_NORM Diff Gain

AD

VO_DIFF Diff Gain

FB

Frequency Boost at

Ic

F_Code

FB(dB) =20 log [0.01703 (5_Code) +1]

oto 10 dB, Ta < 22°C
oto 10 dB, Ta > 22°C

TGDO

0.2

gdm
TGDB

Group Delay Variation
Without Boost

Ic = 1.5 - 8 MHz
= group delay magnitude
Group Delay Variation
With Boost

Ic = 1.5 - 8 MHz

Ic -Ic

Ic - 1.75 Ic
0.2

..---------

MAX

UNIT

8

MHz

+10

0/0

----- ------

+15

-

-

----- ---------- - ..

0/0
---~.--

kHz
--------- - -

F = 0.67

FBA Frequency Boost Accuracy

FBA Frequency Boost Accuracy

NOM

Ic -Ic

IC-1.75/c

Boost Resolution

1.5to 8 MHz

.25

dB

VOF Filter Output Dynamic Range

THO =1.5% max, V8P =0, VO_NORM
1000 pF capacitor across Rx
F_Code = 127

1.5

Vppd

VOF Filter Output Dynamic Range

THO =3.5% max, V8P = 0, VO_OIFF
1000 pF capacitor across Rx
F_Code = 127

1.5

Vppd

VOF Filter Output Dynamic Range

THO = 1.5% max, VBP = 0, VO_NORM
1000 pF capacitor across Rx
F_Code = 21

1.0

Vppd

VOF Filter Output Dynamic Range

THO = 2.0% max, VBP = 0, VO_OIFF
1000 pF capacitor across Rx
F_Code = 21

1.0

Vppd

8-37

----

~---

- - - - - - ~----

I

SSI32F8120
Low-Power Programmable
Electronic Filter
ELECTRICAL SPECIFICATIONS
Filter Characteristics

(continued)

PARAMETER
RIN

(continued)

CONDITIONS

MIN

Filter Diff Input Resistance

NOM

MAX

3.0

kn
-

CIN

Output Noise Voltage
(VO_NORM)

BW = 100 MHz, o dB Boost
50n input
10 dB Boost
Ic = 8 MHz

EOUT

Output Noise Voltage
(VO_DIFF)

BW = 100 MHz, o dB Boost
50n input
10 dB Boost
Ic = 8 MHz

10-

-~.-

Filter Input Capacitance

EOUT

Filter Output Sink Current

7

pF

3

mVRms

4

mVRms

6

mVRms

9

mVRms

---

1.8
2.35
--- -

-~

4.2
5.85
.._-----

..-

mA

1.0

10+ Filter Output Source Current

UNIT

. _ . - _ . _ - r---~~

mA

3.0

- - - - - r---~--

RO

Filter Output Resistance
(Single ended)

Output source current, 10+ =1 rnA

TC Period, SCLK

60

ns

100

T1 SDEN Setup to SCLK Falls

Q

TC/2-10

10

ns

- - - - - -... -------

T2A SDEN Hold wrt SCLK Falls

TC/4

10
~-~--

T28 SDEN Falls prior to SCLKRises

~-----'

----.-~--

25

ns

- - - - - - t-------_ ..---- ---

T3 SDI Setup to SCLK Falls

25

T4 SDI Hold to SCLK Falls

25

ns

----

ns
--".-

Power Supply Rejection Ratio

100 rnVpp @5 MHz on VCA, VCO

=0 VOC + 100 rnVpp @5 MHz

Common Mode Rejection Ratio

Yin

Bias:

VCC

Vin+, VinVO_NORM+,VO_NORMVO_DIFF+, VO_DIFF-

= 5V
VCC = 5V
VCC = 5V

40

----- - - - _ . _ - -

70

30

50

2.5

2.9

2.8

3.2

2.8

3.2

dB
_.. -

3.3
3.6
3.6

----.---

-150

8-38

-~~-

dB

-.------~--

Output offset
Normal and Differentiated

ns

+150

V
V
f------

V
--~

mV

SSI32F8120
Low-Power Programmable
Electron ic Filter
TABLE 2: Calculations
Typical change in j-3 dB point with boost

K

Boost (dB)

Gain@fc (dB)

Gain@ peak (dB)

fpeak/fc

f-3dB/fc

0

-3

0.00

no peak

1.00

0

1

-2

0.00

no peak

1.21

0.16
0.34

2

-1

0.00

no peak

1.51

3

0

0.15

0.70

1.80

0.54

4

1

0.99

1.05

2.04

0.77

5

2

2.15

1.23

2.20

1.03
1.31

6

3

3.41

1.33

2.33

7

4

4.68

1.38

2.43

1.63

8

5

5.94

1.43

2.51

1.97

9

6

7.18

1.46

2.59

2.40

10

7

8.40

1.48

2.66

2.85

Notes: 1. jc is the original programmed cutoff frequency with no boost

2. j-3 dB is the new -3 dB value with boost implemented
3. jpeak is the frequency where the amplitude reaches its maximum value with
boost implemented
Le., jc

= 2 MHz when boost = 0 dB

if boost is programmed to 5 dB then

f-3 dB

= 4.40 MHz

jpeak = 2.46 MHz

I
8-39

SSI32F8120
Low-Power Programmable
Electronic Filter
THERMAL CHARACTERISTICS: 9ja

PACKAGE PIN DESIGNATIONS
(Top View)

N/C

16-lead SOL

100 0 C/W

20-lead SOV

125 0 C/W

20

N/C

DGND

2

19

VO_DIFF+

VO_NORM-

VO_NORM-

3

18

VO_DIFF-

VO_NORM+

3

14

RX

VO_NORM+

4

17

RX

VCA

4

13

SCLK

VCA

5

16

SCLK

VIN-

5

12

VCD

VIN-

6

15

VCD

VIN+

6

11

SDEN

VIN+

7

14

SDEN

VBP

7

10

SDI

VBP

8

13

SDI

VFP

8

9

VFP

9

12

AGND

N/C

10

11

N/C

DGND

16

VO_DIFF+

15

VO_DIFF-

AGND

16-Lead SOL

20-Lead SOY

CAUTION: Use handling procedures necessary
for a static sensitive component.

ORDERING INFORMATION
PART DESCRIPTION

SSI32F8120

ORDER NUMBER

16-Lead SOL
--------

PACKAGE MARK

32F8120-CL

32F8120-CL
--------

--

20-Lead SOY

32F8120-CV

__ •• '_0'-

---... --- ..

---~-

-----"-------

32F8120-CV

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX 714/573-6914

Patent No. 5,063,309, Patent Pending 823,067
©1993 Silicon Systems, Inc.

1294 - rev.
8-40

SSt 32F8130/8131
Low-Power Programmable
Electronic Filter

January 1995

DESCRIPTION

FEATURES

The SS132F8130/8131 Programmable Electronic Filters are digitally controlled low pass filters with a
normal low pass output and a time differentiated low
pass output. The low pass filter is of a 7-pole / 2-zero
0.05° phase equiripple type, with flat group delay
response beyond the passband.

•

Programmable filter cutoff frequency (551
32F8130: Ic 0.285 to 2.2 MHz, SSI32F8131 : Ic
= 0.15 to 1.4 MHz) with no external components,
serial data connections to minimize pin count

•

Power down mode «5 mW)

The SS132F8130/8131 bandwidth and boost are controlled by two on-chip 7-bit DACs, which are programmed via a 3-line serial interface. The SSI32F8130
filter bandwidth is programmable from 285 kHz to 2.2
MHz. The SSI32F8131 is programmable from 150 kHz
to 1.4 MHz. The boost is programmable from 0 to 10
dB. Because the boost function is implemented as two
zeros on the real axis with opposite sign, the flat group
delay characteristic is not affected by the boost programming.

•

Programmable pulse slimming equalization
(0 to 10 dB boost at the filter cutoff frequency)

•

Matched normal and differentiated low-pass
outputs

•

Differential filter inputs and outputs

•

Programming via internal 7-bit DACs

•

No external filter components required

•

+5V only operation

•

Supports constant density recording

The SS132F8130/8131 are ideal for multi-rate, equalization applications. They require only a +5V supply
and have a power down mode for minimal idle dissipation. The SSI 32F8130/8131 is available in a 16-lead
SOL package.

=

PIN DIAGRAM

BLOCK DIAGRAM
AGND

16

VO_DIFF+

VO_NORM-

15

VO_DIFF-

VO_NORM+

14

PWRON

VCA

13

SCLK
VCD

VIN+
VIN-

VO_DIFFVO_DIFF+

VIN-

12

VIN+

11

DGND2

SDEN/SDEN

10

VFP

DGND2
SDI

16-Lead SOL

PWRON

VFP

~

o

SS132F8130: Lead 7 = SDEN
SSI 32F8131: Lead 7 = SDEN

CAUTION: Use handling procedures necessary
for a static sensitive component.

Ci
z
0195 - rev.

DGND1

8-41

I

SSI 32F8130/8131
Low-Power Programmable
Electronic Filter
FUNCTIONAL DESCRIPTION

CUTOFF FREQUENCY PROGRAMMING

The SS132F8130/8131, a high performance programmable electronic filter, provides a 7-pole I 2-zero 0.05°
equiripple linear phase low pass function with matched
normal and time differentiated outputs. The device
includes multiple biquads and first-order sections to
accomplish the filter function, two 7-bit OACs for bandwidth and boost controls, a 3-line serial interface, and
complete bias reference circuits. Only one external
preciSion 8.25 kQ resistor should be connected from the
VFP pin to ground for operation. See Figure 1.

The cutoff frequency, fc, is defined as the -3 dB
bandwidth with no magnitude equalization applied,
and is programmable from 285 kHz to 2.2 MHz for SSI
32F8130, and 150 kHz to 1.4 MHz for SSI 32F8131.
While the fc is controlled by an on-chip 7-bit OAC, the
cutoff frequency resolution is better than 20-kHz step.
Let F_Code be the decimal equivalent of the 7-bit
control. The cutoff frequency can be determined by the
following equations:
SSI32F8130 fe (kHz) = 16.73· F_Code + 84

SERIAL INTERFACE

SSI32F8131 fe (kHz) = 10.81 • F_Code + 37

The SSI 32F8130/8131 allows easy digital controls of
filter bandwidth and magnitude equalization via a 3-line
serial interface. The three pins are SOl, SOEN and
SCLK. SOl is the serial data input to an internal8-bit shift
register. SDEN is the shift register enable. SCLK is the
shift register clock. Besides the 8-bit shift register which
accepts data from the SOl input, there are four 4-bit
registers which hold the filter bandwidth and boost
controls. Two 4-bit registers are assigned to each control
function, because a 7-bit binary control is required for
each function.

where 12 ~ F_Code

~

127.

MAGNITUDE EQUALIZATION PROGRAMMING

The magnitude equalization, measured in dB, is the
amount of high frequency peaking atthe cutoff frequency
relative to the original -3 dB point. For example, when
10 dB boost is applied, the magnitude response peaks
up 7 dB above the DC gain. This equalization function is
also controlled by an on-chip 7-bit OAC.
Let S_Code be the decimal equivalent of the 7-bit
control. The magnitude equalization can be determined
by the equation:

The S-MSB register, whose address code is XOOO,
holds the 3 MSBs of the boost control. The S-LSB
register, whose address code is X001 , holds the 4 LSBs
ofthe boost control. The F-MSB register, whose address
code is X01 0, holds the 4 MSBs of the cutoff frequency
control. The F-LSB register, whose address code is
X011, holds the 4 LSBs of the cutoff frequency control.

Boost (dB) = 20· log
for 32F8130

The serial interface consists of data packets, which are
structured as 4-bit address decode followed by 4-bit
data. Figure 2 shows the serial interface timing to
successfully program the SS132F8130/8131.

8-42

[0.0145· S_Code + 1]
10

[0.01703· S~Code + 1]

Boost (dB) = 20 • log
for 32F8131

1

where 0 ~ S_Code

127.

~

0

SSI 32F8130/8131

Low-Power Programmable
Electron ic Filter

2.95139
s' + S 1.54203 + 2.95139

+1.31703
s'+ S 1.68495+ 1.31703

INPUT

5.37034
S '+ S 1.14558 + 5.37034

-KS'
s' + S 1.68495 + 1.31703

Normalized for we = (21t) ic = 1
AN and AD are adjusted for unity gain (0 dB) at F = 0.67 ic
Denormalize the frequency by substituting S ~ (S/21t ic)
6
7
Eq for ic = 2.5 MHz, S = S / [(21t) (2.5 • 10 )] = S / (1.57080 • 10 )

K =1.31703(10 Boost(dB) -1)
20
FIGURE 1: Normalized Transfer Function of the SS132F8130/8131

I

clocks data bit

I

J4- TC~

SCLK

o

~

SOEN setup
SOEN hold
SOEN falls
I
I wrt SCLK falls
wrt SCLK falls I
I
I prior to SCLK
...--:.....:_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--,T2B rises

SDEN

I
SOl holds
T31 T4 wrt SCLK falls
~~Is~rlf falls 1.........1.--~

load data
into register

1.----.

SDI

FIGURE 2: Serial Port Timing Relationship
Note:
The serial data enable function of the SSI32F8130 and that of the 8S1 32F8131 are of opposite polarity.

I

TABLE 1: Data Packet Fields
ADDRESS BITS

DATA BITS

USAGE
03

02

01

DO

8 - MSB REGI8TER

X

86

85

84

1

S - L8B REGISTER

83

82

S1

80

1

0

F - MSB REGISTER

X

F6

F5

F4

1

1

F - LSB REGISTER

F3

F2

F1

FO

07

06

05

04

RO

X

0

0

0

R1

X

0

0

R2

X

0

R3

X

0

X = Don't care bit.
8-43

SSI·32F8130/8131
Low-Power Programmable
Electronic Filter
PIN DESCRIPTION
NAME

DESCRIPTION

VIN+, VIN-

DIFFERENTIAL FILTER INPUTS. The input signals must be AC coupled to these pins.

VO_NORM+,
VO_NORM-

DIFFERENTIAL NORMAL OUTPUTS. Theoutput signals must be AC coupled to the load.

VO_DIFF+
VO_DIFF-

DIFFERENTIAL DIFFERENTIATED OUTPUTS. These outputs should be AC coupled
to the load.

PWR_ON

POWER ON. A TTL high logic level enables the chip. A low level or open circuit puts the
chip into a low power state.

SDEN (8130)
SDEN (8131)

SERIAL DATA ENABLE. An active level allows SCLK to clock data into the shift register
via the SOl input. An inactive level latches the register data and issues the information to
the appropriate circuitry. Active level for SSI32F8130 is HIGH, for SSI32F8131 is LOW.

SCLK

SERIAL CLOCK. Negative edge triggered clock input for serial register.

SOl

SERIAL DATA INPUT.

VCA

ANALOG +5 VOLT SUPPLY.

VCD

DIGITAL +5 VOLT SUPPLY.

AGND

ANALOG GROUND.

DGND1
DGND2

DIGITAL GROUND.

VFP

CUTOFF FREQUENCY PROGRAMMING REFERENCE. A resistor of 8.25 kn should be
connected between this pin and AGND.

...

..

~

-

..

-~~--~--

_...

ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may permanently damage the device.
PARAMETER

RATING

Storage Temperature

-65 to + 150°C

Junction Operating Temperature, Tj

+130°C

Supply Voltage, VCC

-0.5 to 7V

Voltage Applied to Inputs·

-0.5 to VCCV

T1 Lead Temperature (1/16" from case for 10 seconds)

260°C

* Analog input signals of this magnitude shall not cause any change or degradation in filter performance after

signal has returned to normal operating range.

RECOMMENDED OPERATING CONDITIONS
PARAMETER

RATING

Supply voltage, VCC

4.50 < VCC < 5.50V

Ambient Temperature

0< Ta < 70°C

Tj Junction Temperature

0< Tj < 130°C

8-44

SSI 32F8130/8131
Low-Power Programmable
Electron ic Filter
ELECTRICAL CHARACTERISTICS
Unless otherwise specified recommended operating conditions apply. F_Code
PARAMETER

CONDITIONS

= 64, S_Code = O.

MIN

NOM

Idle Mode Current
Isupply

60
PWR_ON $ 0.8V

Power Dissipation

PWR_ON ~ 2.0V

MAX

UNIT

1

rnA

70

rnA

6

mW

385

mW

Idle to Active Mode Recovery Time

50

115

Serial port program to output
response time

50

115

303

DC Characteristics
VIH

High Level Input Voltage

VIL

Low Level Input Voltage

IIH

High Level Input Current

VIH = 2.7V

ilL

Low Level Input Current

VIL = O.4V

2

TTL input

V
0.8

V

25

IlA

-1.5

rnA

Filter Characteristics

Ic

FCA

Filter Cutoff Frequency

Filter Ic Accuracy

AD
FB

VO_NORM Diff Gain

2.2

MHz

0.15

1.4

MHz

Ic range

32F8130

-12

+12

0/0

32F8131

-10

+10

%

32F8130

17

kHz

Resolution= Maxfc
127

32F8131

Ic

32F8130

0.7

1.1

VIV

32F8131

0.8

1.2

VIV

F = 0.67

VO_DIFF Diff Gain
Frequency Boost at
(32F8130)

0.285

SSI32F8131
over

Cutoff Resolution
AO

12 < F_Code < 127
SSI32F8130

F=

0.67/c

------

"-"

11

kHz

32F8130 0.8 AO

1.15 AO

VIV

32F8131 1.0 AO

1.2AO

VIV

9

dB

10

dB

Ic

(32F8131)

FB(dB) =20 log [0.0145· S_Code + 1]
0$ S_Code $ 127

0

FB(dB) =20 log [0.0173· S_Code + 1]
0$ S_Code $ 127

0
--"

FBA

Frequency Boost Accuracy

S_Code = 127

TGDO

Group Delay Variation

0.2 Ic to Ic

Without Boost
TGDB Group Delay Variation

Ic to 1.75 Ic
0.2 Ic to Ic

With Boost

-1.5

+1.5

dB

32F8130

-2.5

+2.5

%

32F8131

-2

+2

%

-3

+3

%

32F8130

-2.5

+2.5

0/0

32F8131

-2

+2

%

-3

+3

%

Ic to 1.75 Ic
Boost Resolution
VOF_N Filter Output Dynamic Range

THD = 1% max, Normal Output
8-45

0.25

dB

1

Vp-p

I

551 32F8130/8131
Low-Power Programmable
Electronic Filter
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified recommended operating conditions apply. F_Code
PARAMETER

CONDITIONS

= 64, S_Code = O.

MIN

MAX

NOM

UNIT

Filter Characteristics (continued)
VOF_D Filter Output
Dynamic Range

TH D = 1% max, Differentiated
Output

1

Vp-p
-

RIN

Filter Diff Input Resistance

CIN

Filter Input Capacitance

EOUT Output Noise Voltage
(VO_NORM)
EOUT Output Noise Voltage
(VO_DIFF)

3.0

4.0

5.0

kQ

1.9

mVRms

3.0

pF

BW = 100 MHz,
50Q input
fC = Max fc

odB Boost

1.2

max Boost

1.4

2.0

mVRms

BW = 100 MHz,
50Q input
fc = Max fc

odB Boost

2.1

2.7

mVRms

~-

-._---- ----

- --_ .. -----

-~

max Boost

----_ ...

2.5

3.4
._""""-

10-

Filter Output Sink Current

10+

Filter Output Source Current

RO

Filter Output Resistance
(Single ended)

1.0

---

mA

- - - - - - - r---------

3.0
Output source current,
10+ = 1 mA

T1 SDEN Set-up WRT SCLK Falls

mVRms

-----

mA
70

50

Q

--- - - - - - - - - r - - - - - - -

10

---------- - - - - -

T2A SDEN Hold WRT SCLK "Falls

TC/2-10

ns

TC/4

ns

--------- - - - -

10

- - - - - -------- - - " - - - - - - - -

T2B SDEN Falls (rises for 8131)
prior to SCLK rises

25

ns
---- - - - - - - - - - - -

T3 SDI Set-up WRT SCLK Falls

25

T4 SDI Hold WRT SCLK Falls

25

SCLK Period, TC

100

ns
-

--

ns
-"-

Power Supply Rejection Ratio
VO_NORM

100 mVp-p from 10kHz to
10 MHz on VCA, VCD

Power Supply Rejection Ratio
VO_DIFF
Common Mode Rejection Ratio
VO_NORM

Yin = OVDC + 10 mVp-p from
10 kHz to 10 MHz

30

ns
dB

40
---

20

30

30

40

dB
dB
-"-

Common Mode Rejection Ratio
VO_DIFF
Bias:

= 5V

20

30

dB

2.40

2.75

3.10

V

Vin±

2.20

2.35

2.80

V

VO_DIFF±

2.40

2.75

VO_NORM±

VCC

--

3.10

------- - - -

Normal Output Offset Variation

F_Code switched from 12-127

-200

Differentiated Output Offset
Variation

F_Code switched from 12-127

-200

V
---~

200

mV

200

mV

"-

8-46

551 32F8130/8131
Low-Power Programmable
Electron ic Filter
TABLE 1: Calculations (Typical change in 1-3 dB point with boost)
Boost (dB)

Gain@fc (dB)

Galn@ peak (dB)

fpeak/fc

f-3dB/fc

0

-3

0.00

no peak

1.00

0

1

-2

0.00

no peak

1.21

0.16
0.34

K

2

-1

0.00

no peak

1.51

3

0

0.15

0.70

1.80

0.54

4

1

0.99

1.05

2.04

0.77

5

2

2.15

1.23

2.20

1.03

6

3

3.41

1.33

2.33

1.31

7

4

4.68

1.38

2.43

1.63

8

5

5.94

1.43

2.51

1.97

9

6

7.18

1.46

2.59

2.40

10

7

8.40

1.48

2.66

2.85

Notes: 1. Ic is the original programmed cutoff frequency with no boost

2.

1-3 dB is the new -3 dB value with boost implemented

3. Ipeak is the frequency where the amplitude reaches its maximum value with
boost implemented
I.e., Ic = 1 MHz when boost = 0 dB
if boost is programmed to 5 dB then

= 2.20 MHz
Ipeak = 1.23 MHz
f-3 dB

1
.........

1.8
1.6

1.2
1.0

Q)

0.8

4 fe

\

(j)

.2;
>-

3 je= 1.15MHz
= 1.6 MHz
5 je = 2.05 MHz
6 je= 2.5 MHz

\

1.4

\\

1\

0.6

I

~

ro

£:)

= 250 kHz
= 700 kHz

1 je

2 je

1\

3

0.4

"-

0.2
0.0
lOOk

,~

\.

----- -r---"'--

200k

300k

400k 500k

700k

1meg

2meg

3meg

5

4meg

Frequency (Hz)

FIGURE 3: Typical Normal/Differentiated Output Group Delay Response
8-47

6

~~
5meg

551 32F8130/8131
Low-Power Programmable
Electronic Filter
PACKAGE PIN DESIGNATIONS

THERMAL CHARACTERISTICS: ejA

(Top View)

16-Lead SOL

AGND

16

VO_DIFF+

VO_NORM-

2

15

VO_DIFF-

VO_NORM+

3

14

PWRON

VCA

4

13

SCLK

VIN-

5

12

VCD

VIN+

6

11

DGND2

SDEN/SDEN

7

10

VFP

SDI

8

9

I 100° C/W

DGND1

16-Lead SOL
SSI 32F8130: Lead 7 ::: SDEN
SSI 32F8131: Lead 7 = SO EN
CAUTION: Use handling procedures necessary
for a static sensitive component.

ORDERING INFORMATION
PART DESCRIPTION

ORDER NO.

PKG.MARK

SSI32F8130 16-Lead SOL
SSI32F8131 16-Lead SOL

32F8130-CL
32F8131-CL

32F8130-CL
32F8131-CL

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914

©1991 Silicon Systems, Inc.
Patent No. 5,063,309
Patent Pending Nos. (516717) (823067)

9195 - rev.
8-48

551 32F8144
Programmable
Electronic Filter

January 1994

DESCRIPTION

FEATURES

This custom integrated circuit incorporates a pulse
equalizer of variable equalization and variable bandwidth with a transfer function of a 2 zero/7 pole linear
phase filter, as well as variable gain stages controlled
by DACs. Equalization, gain and bandwidth changes
are user-programmable via three serial lines to a
microprocessor. The equalizer is totally contained and
calibrating. It is realized in a high speed fully differential
mode. A seven pole linear phase equiripple ± 0.05
degree filter forms the low-pass function. The cutoff
frequency of the low-pass section is programmed via a
7-bit serial shift register and can be programmed from
7 to 27 MHz. Pulse slimming equalization uses two
programmable magnitude, opposite sign zeroes on the
real axis. Pulse slimming boost is from 0 to 9.5 dB atthe
filter cutoff frequency using a 7 bit serial shift register.
Gain can be programmed from 10 VN to 100 VN for
normal outputs and from 10 VN to 50 VN for differentiated outputs.

•

Programmable filter cutoff frequency (7 MHz $;
Ic $; 27 MHz) with no external components

•

± 10% cutoff frequency accuracy

•

Programmable pulse slimming equalization
(0 to 9.5 dB boost at the filter cutoff
frequency)

•

Matched delay normal and differentiated lowpass outputs

•

Differential filter inputs and outputs

•

Device idle mode (45 mW nom.)

•

+5V only operation

•

Supports constant density recording

•

Input stage gain control with DAC

•

Relative gain between normal and differentiated outputs controlled with serial port

BLOCK DIAGRAM

PIN DIAGRAM

~+

N-

VONORM+
L-'.···.·.L

EXT CAP+

VCA

EXT CAP-

VIN+

LZ

VIN-

VONORM-

. _---.l·L_ . _ _ _"

vo

DIFF+

vo DIFF-

VONORM-

AGNO

VO NORM+

YAP

VO OIFF+

~lK.

VO OIFF-

SDEN

VBP

VCO

VFP

SOl

RX

DGNO

20-lead SOL

VCA

0194 - rev.

8-49

vco

AGNO

OGNO

CAUTION: Use handling procedures necessary
for a static sensitive component.

•

•

SSI32F8144
Programmable
Electronic Filter
FUNCTIONAL DESCRIPTION

AN/AD

F Code
jc(MHz)=27 0- - - 127

BOOST (dB) = 20

B_Code

=5

(B2

= 1,

B1

= 0,

By programming DO to "0," the SSI32F8144 is switched
into a power-down state, dissipating minimum idle
power. The filter is switched off. The serial port remains
active awaiting the next command.

A_Code

BO

log [0.01563(S_Code) +1].

POWER-DOWN CONTROL

This input gain stage is DC coupled to the filter core
through DC restore circuitry. A large capacitor (1 J..LF) is
placed between pins EXT_CAP+ and EXT_CAP- to
null the input offset to the filter. Register B ( Register 5,
R5) controls the relative gain between the normal and
differentiated outputs. There are three discrete options
which are listed as follows:

= 1, BO = 1)

o

The DO bit of the P register (register 7, R7) determies
the power up/down state of the SSI 32F8144. Upon
initial power up, the DO bit of the P register should be
initialized to "1" for normal operation. 03 - 01 are "don't
care."

Av(V/v)=100 A_Code
15
1 ~ A Code ~ 15

B1

127

The 7-bit S_Code is loaded into S1 and S2 registers
(registers 0 and 1 - RO, R1).

The input gain stage is programmed with register A
(Register 4, R4). The A_Code programs this gain as
follows:

= 0,

33~F _Code::;

The amplitude of the input signal atfrequencies near the
cutoff frequency can be increased using this feature. By
controlling the DACS output, the boost can be
determined. The amount of boost atthe cutoff frequency
is related to the OAtS output by the following formula:

GAIN PROGRAMMING

(B2

= 1, B1 = 1, BO = 0)

SLIMMER HIGH FREQUENCY BOOST
PROGRAMMING

The registers are loaded by using the serial port through
the SOl, SDEN and SCLK pins.The SOl pin is the serial
bit input. The SDEN pin is the control register enable.
The SCLK is the control register clock. The packet is
transmitted MSB (07) first.

=3

(B2

CUTOFF FREQUENCY PROGRAMMING

Data is loaded serially with MSB first. Each data packet
contains 8 bits. The first four bits (07 - D4) are designated as address bits with 07 always a "don't care."
The last four bits (03 - DO) are the data bits (see Table 1).

B_Code

=6

The filter cutoff frequency can be set from 7 to 27 MHz.
The 7 -bit F_Code programs the cutoff frequency as
follows:

The SSI32F8144 has seven control registers: A, B, S1,
S2, F1, F2 and P registers. Register A contains four
bits, B is three bits, and P is one bit. S1, S2, F1, and F2
contain seven bits. Register A controls the gain of the
input stage and register B controls the gain between
the normal and differentiated outputs. Since the F, S
registers contain 7 bits, they require two data packets
which must be loaded sequentially. S1-2 registers are
for high frequency boost. F1-2 registers are for cutoff
frequency control. The P register is for power down
command. The structure and command of each register are described as follows.

= 1.0
=1
AN/AD = 1.5

B_Code

(B3 is a "don't care")

The SS132F8144, a high performance programmable
electronic filter, provides a low pass equiripple type
seven pole filter with matched normal and differentiated outputs with variable gain using DACs.

AN/AD

= 2.0

= 1)

A_Code = 7
8-50

SSI32F8144
Programmable
Electronic Filter

clocks data bit

SCLK

Load data
into appropriate
register

CRD Hold
wrtCRC rises

SDI

FIGURE 1: Serial Port Timing Relationship

TABLE 1: Control Register Assignment
ADDRESS BITS

RO

USAGE

DATA BITS

07

06

05

04

03

02

01

DO

X

0

0

0

S1 REGISTER

X

S6

S5

S4

R1

X

0

0

1

S2 REGISTER

S3

S2

S1

SO

R2

X

0

1

0

F1 REGISTER

X

F6

F5

F4

R3

X

0

1

1

F2 REGISTER

F3

F2

F1

FO

R4

X

1

0

0

A REGISTER

A3

A2

A1

AO

R5

X

1

0

1

B REGISTER

X

B2

B1

BO

R7

X

1

1

1

P REGISTER

X

X

X

PO

X = Don't Care
S = Boost (Slimming) Control
F = Frequency (Bandwidth) Control
A = Gain Setting (0-10)
B = Gain of VO_OIFF relative to the gain of Va_NORM
P = Sleep Mode Control WO = 1, On Mode; PO = 0, Sleep Mode)
SOl is the serial data input for an 8-bit control shift register. The data packet is transmitted Most Significant B~ (07)
first. The first four bits are the register address, the last four are the data b~s. Registers larger than four bits must
be loaded w~h two 8-b~ data packets. These packets should be loaded sequentially.

8-51

I

SSI32F8144
Programmable
Electron ic Filter
PIN DESCRIPTION
NAME

DESCRIPTION

VIN+, VIN-

DIFFERENTIAL SIGNAL INPUTS

VO_NORM+,
VO_NORM-

DIFFERENTIAL NORMAL OUTPUTS

VO_DIFF+
VO_DIFF-

DIFFERENTIAL DIFFERENTIATED OUTPUTS

SO EN

CONTROL REGISTER ENABLE. A logic LOW level allows CONTROL REGISTER CLOCK
to clock data into the control registerviathe CONTROL REGISTER DATA input. A logic HIGH
level latches the register data and issues the information to the appropriate circuitry. This is
a TIL input.

SCLK

CONTROL REGISTER CLOCK. Positive edge triggered clock input for serial register. This
is a TTL input.

SOl

CONTROL REGISTER DATA. This is a TTL input (see Figure 1).

RX

CURRENT SET RESISTOR. This external resistor to groJ,Jnd provides a reference current.
(RX = 5 kQ ±1%) A 1000 pF capacitor must be connected in parallel with Rx.

VCA

ANALOG +5V SUPPLY.

VCD

DIGITAL +5V SUPPLY.

---_ ...... -

------

----

-----------

------~~----~

AGND

ANALOG GROUND.

DGND

DIGITAL GROUND.

VAP

ANALOG TO DIGITAL TEST VOLTAGE. This is an analog voltage that is proportional to the
setting on the digital output on the AID convertor. This is a test pin related to the variable gain.

--_.. -

---

--

VBP

BOOST PROGRAMMING VOLTAGE. A voltage that is related to the boost. A test pin.

VFP

CUTOFF FREQUENCY PROGRAMMING VOLTAGE. A voltage that is related to the cutoff
frequency. A test pin.

EXTCAP+
EXT CAP-

EXTERNAL CAPACITOR. These pins are available for an external capacitor which is used
in a feedback network to null the input offset. CEXT ~ 0.47/-lF, 1.0 /-IF nominal.

LZ

LOW 1M PEDANCE. This is a control signal which causes the input impedance of the filter to
be low when this pin is low. The impedance is high if the pin is open or in the high state. This
is a TIL input.

8-52

551 32F8144
Programmable
Electron ic Filter
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may damage the device.
PARAMETER

RATINGS

Storage Temperature

-65 to + 150°C

Junction Operating Temperature, Tj

+130°C

Supply Voltage, VCC

-0.5 to 7V

Voltage Applied to Inputs*

-0.5 to VCCV
-

Maximum Power Dissipation,

fc = 27 MHz,

Vcc

= 5.5V

T1 Lead Temperature (1/16" from case for 10 seconds)

.55W
260°C

* Analog input signals of this magnitude shall not cause any change or degradation in filter performance after
signal has returned to normal operating range.

RECOMMENDED OPERATING CONDITIONS
Supply voltage, VCC

4.50 < VCC < 5.50

V

Ambient Temperature

0< Ta < 70

°C

Tj Junction Temperature

0< Tj < 130

°C

--

ELECTRICAL CHARACTERISTICS
Unless otherwise specified recommended operating conditions apply.
PARAMETER

CONDITIONS

Idle Mode Current

= "0"
Vcc = 5.5V
PO = "0"
PO = "1"

Supply Current
PD

Power Dissipation

MIN

NOM

MAX

UNITS

11

15

mA

PO

85

100

rnA

45

71.5

mW

400

550

mW

50

Ils

50

Ils

0.8

V

--_.-

.-----~--

---~

--_ ...

Idle to Active Mode Recovery Time
------ - - - - - - - - "---

Serial port program to output
response time

- - _ ..• -

DC Characteristics
VIH

High Level Input Voltage

VIL

Low Level Input Voltage

- ----,------

TIL input

2.0

V
1---

IIH

High Level Input Current

VIH

ilL

Low Level Input Current

VIL

Filter Characteristics

fc

Filter Cutoff Frequency

= 2.7V
= OAV

20

!lA

-1.5

mA

27

MHz

-- - - - ----

---

--

33:E; F_Code:E; 127

8-53

7

-

I

SSI32F8144

Programmable
Electronic Filter
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise speciTIed recommende d operating conditions apply.
PARAMETER

CONDITIONS

FCA

Filter fc Accuracy

AO

Va_NORM Diff Gain (Note) F=0.67fc

AD

VO_DIFF Diff Gain (Note)

MIN

Over full fc range,
33::; F_Code::; 127

MAX

UNITS

-10

NOM

10

0/0

10

100

VIV

F = 0.67 fc, set with serial port

10

50

VIV

VO_NORM Gain Tolerance

Ao = 100

-15

15

0/0

VO_DIFF Gain Tolerance

Ao =50

-15

15

0/0

FB

Frequency Boost at fc

FS(d8) = 20 log [.01563 (S_Code) +1]

0

9.5

dB

FBA

Frequency Boost Accuracy

oto 9.5 dB

-1.25

+1.25

dB

TGDO

Group Delay Variation
Without Boost

0.2 fc - fC

-2%
gdm

+2%
gdm

ns

fc - 1.75 fc

-3%

+3%
gdm

ns

~dm

0.2 fc - fC

-2%
gdm

+2%
gdm

ns

fc - 1.75 fc

-3%
gdm

+3%
gdm

ns

gdm
TGDB

VOF

=group delay magnitude

Group Delay Variation
With Boost

Filter Output Dynamic- Range

RIN

Filter Diff Input Resistance

CIN

Filter Input Capacitance

EOUT Output Noise Voltage
(VO_NORM)
EOUT Output Noise Voltage
(VO_DIFF)

---

Vo_NORM, THO = 1.5%

1

Vpp

Vo_DIFF, THO = 2.0%

1

Vpp

Va_NORM, THO = 2.0%

1.5

Vpp

Vo_DIFF, THO = 3.0%

1.5

Vpp

3.0

o

BW = 100 MHz,
dB Boost
50Q input
fc = 27 MHz
9.5 dB Boost

o

BW = 100 MHz,
dB Boost
50n input
9.5 dB Boost
Ic = 27 MHz

4.0

kQ

7

pF

2.5

4.0

mVrms

3.7

10

mVrms

4.4

6

mVrms

7.8

14

mVrms

3.5

10-

Filter Output Sink Current

1.0

mA

10+

Filter Output Source Current

3.0

mA

RO

Filter Output Resistance
(Single ended)

30

10+ = 1 mA

50

n
ns

SCLK Period, TC

100

SDEN Set-up WRT SCLK Rising Edge

10

25

ns

SDEN Hold WRT SCLK Rising Edge

5

TC/2-10

ns

Note:

The overall gain of VO_DIFF with respect to VIN is 10 to 50 VIV. Additionally, the gain of
VO NORM with respect to VO DIFF will be adjustable and have gain values of 1.0, 1.5 and 2.0.
8-54

SSI32F8144
Programmable
Electronic Filter
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified recommended operating conditions apply.
PARAMETER

MIN

CONDITIONS

NOM

_.

MAX

UNITS

SDEN Rises Prior to SCLK Falls

15

ns

SOl Set-up WRT SCLK Rising Edge

15

ns

15

SOl Hold WRT SCLK Rising Edge

ns

Power Supply Rejection Ratio

100 mVpp in VCA, VCD from
100 kHz to 10 MHz

45

70

dB

Common Mode Rejection Ratio

VIN = 0 VDC + 100 mVpp from
100 kHz to 10 MHz

40

65

dB

2.05

2.55

2.5

3.0

DC Bias: VOJ,JORM+, VO_NORM- VCC
VO_DIFF+, VO_DIFF-

= 5V,

single ended

- -

-

Vin+, VinDelay mismatch normal and
differentiated outputs

3.05

V
... -

~.-.-

3.5

V

1

ns

TABLE 2: Calculations
Typical change in j-3 dB point with boost
Boost (dB)

Gain@fc (dB)

Gain@ peak (dB)

fpeak/fc

f-3dB/fc

K

a

-3

0.00

no peak

1.00

0

1

-2

0.00

no peak

1.21

0.16

2

-1

0.00

no peak

1.51

0.34

3

0

0.15

0.70

1.80

0.54

4

1

0.99

1.05

2.04

0.77

5

2

2.15

1.23

2.20

1.03

3

3.41

1.33

2.33

1.31

6
7

4

4.68

1.38

2.43

1.63

8

5

5.94

1.43

2.51

1.97

9

6

7.18

1.46

2.59

2.40

10

7

8.40

1.48

2.66

2.85

Notes: 1. jc is the original programmed cutoff frequency with no boost

2. j-3 dB is the new -3 dB value with boost implemented
3. jpeak is the frequency where the amplitude reaches its maximum value with
boost implemented
e.g., jc

= 9 MHz when boost = 0 dB

if boost.is programmed to 5 dB then

= 19.8 MHz
jpeak = 11.07 MHz

f-3 dB

8-55

I

551· 32F8144
Programmable
Electronic Filter

INPUT

1.31703

2.95139

S2+ S 1.68495 + 1.31703

S2+ S 1.54203+ 2.95139

S2+ S 1.68495 + 1.31703

Normalized for roc = (2n) Ic = 1
AN and AD are adjusted for unity gain (0 dB) at F = 0.67 Ic
Denormalize the frequency by substituting S ~ (S/2njc)
Eq for Ic = 27 MHz, S = S / [(2n)(27 x 106 )]

FIGURE 2: 32F8144 Normalized Block Diagram

PACKAGE PIN DESIGNATIONS

EXTCAP+

(Top View)

VIN+

[Z

VIN-

THERMAL CHARACTERISTICS: 8ja
VONORM-

20-lead SOL

VCA

EXT CAP-

VONORM+

20-Lead SOY

VBP

AGNO
YAP
SCLK

VO OIFF+

VCO

VO OIFF-

SO EN

VFP
RX

SOl
OGNO

CAUTION: Use handling procedures necessary'
for a static sensitive component.

20-lead SOL, SOY

ORDERING INFORMATION
PART DESCRIPTION

ORDERING NUMBER

PACKAGE MARK

SSI32F8144

20-Lead SOL (300 mil)

32F8144 - CL

32F8144 - CL

SSI32F8144

20-Lead SOY (220mil)

32F8144 - CV

32F8144 - CV

Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914

©1993 Silicon Systems, Inc.
Protected by the following patents: (5,182,477), (5,063,309)
Patent Pending: 710, 512

0194 - rev.
8-56

Section

9

APPLICATION NOTES
& GLOSSARY

I
9

9-0

K-Series
Application Information

January 1994
GENERAL CONSIDERATIONS

K-Series devices are available with two control interface versions: one for a parallel multiplexed address/
data interface, and one for a serial interface. The
parallel version is intended for use with 8039/48 or
8031/51 microcontrollers from Intel or many other
manufacturers. The serial interface 22-pin version can
be used with other microcontrollers or in applications
where only a limited number of port lines are available
or the application does not lend itself to a multiplexed
address/data interface. The parallel versions may also
be used in the Serial mode, as explained in the data
sheet pin description.

Figures 1 and 2 show basic circuit diagrams for
K-Series modem integrated circuits. K-Series products
are designed to be used in conjunction with a control
processor, a UART or RS-232 serial data interface
and a DAA phone line interface to function as a typical
intelligent modem. The K-Series ICs interface directly
with Intel8048 and 80C51 microprocessors for control
and status monitoring purposes. Two typical DAA
arrangements are shown: one for a split ±5 or±12 volt
design and one for a single 5 volt design. These
diagrams are for reference only and do not represent
production-ready modem designs.

In most applications the controller will monitorthe serial
data for commands from the DTE and the received
data for break signals from the far end modem. In this
way, commands to the modem are sent over the same
line as the transmitted data. In other applications the
RS-232 interface handshake lines are used for modem
control.

Cl
390 pF

RS232
LEVEL
CONVERTERS
RTS
CTS

CA
CS
CC

DSR

CD
CF

BA
SS
DA
DO
DB

DTR

WR

DCD

os

ALE

551
K-SERIES
LOW
POWER
FAMILY

C2
300 pF

TXD

RXCLK
TXCLK

US. U6
MC145406

J

+5

?

~22K
i

FIGURE 1: Basic Box Modem with Dual-Supply Hybrid
0194

9-1

VRl
MOV
V2S0L20

I

K-Series
Application Information

signals will clip if a Single-ended drive approach is
used. The bridged driver uses an extra op-amp (U1 A)
to invert the signal coming from the gain setting op-amp
(U1 B) before sending it to the other leg of the transformer. Each op-amp then supplies half the drive signal
to the transformer. The receive amplifier (U1C) picks
off its signal at the junction of the impedance matching
resistor and the transformer. Because the bottom leg of
the transformer is being driven in one direction by U1 A
and the resistor is driven in the opposite direction at the
same time by U1 B, the junction of the transformer and
resistor remains relatively constant and the receive
Signal is unaffected.

DIRECT ACCESS ARRANGEMENT (DAA)

The telephone line interfaces show two examples of
how the "hybrid" may be implemented. The split supply
design (Figure 1) is a typical two op-amp hybrid. The
receive op-amp serves two purposes. It supplies gain
to amplify the receive signal to the proper level for the
modem's detectors and demodulator, and it removes
the transmitted signal from the receive signal present
at the transformer. This is done by supplying a portion
of the transmitted signal to the non-inverting input of
the receive op-amp at the same amplitude as the signal
appearing .at the transformer, making the transmit
signal Common mode.
The single-supply hybrid is more complex than the
dual-supply version described above, but its use eliminates the need for a second power supply. This circuit
(Figure 2) uses a bridged drive to allow undistorted
Signals to
sent with a single 5 volt supply. Because
DTMF tones utilize a higher amplitude than data, these

be

C1

390pF

R4

37.4K 1%
R1

20K1%

C3

0.1 nF

@)---11-----<~

• Note: Op-amp U1
must be rated for
single 5V operation.
R10 & R11 values
depend on Op-amp
used.

R2

20K 1%

R3
4751%

.5V

R6
22.1K
C6
0.1nF

R7
2OK1%

C5
750pF

~~~~,~/~~~~-~

r:r

VOLTAGE
REFERENCE

HCXlK
RING

>---------"----

~--------------------------------~

FIGURE 2: Single 5V Hybrid Version
9-2

~~~

V250L20

K-Series
Application Information

DESIGN CONSIDERATIONS

supply and ground traces should be routed separately
to the analog and digital functions on the board, and
digital signals should not be routed near low level or
high impedance analog traces. The analog and digital
grounds should only connect at one point near the KSeries device ground pin to avoid ground loops. The KSeries modem IC's should have both high frequency
and low frequency bypassing as close to the package
as possible.

Silicon Systems 1-chip modem products include all
basic modem functions. This makes these devices
adaptable for use in a variety of applications, and as
easy to control as conventional digital bus
peripherals. Unlike digital logic circuitry, however, modem designs must properly contend with precise frequency tolerances and very low level analog signals, to
ensure acceptable performance. Using good analog
circuit design practices will generally result in a sound
design. Following are additional recommendations
which should be taken into consideration when starting
new designs.

For additional applications information consult the Silicon Systems K-Series Modem Design Manual.

CRYSTAL OSCILLATOR

The K-Series crystal oscillator requires a Parallel mode
(antiresonant) crystal which operates at 11.0592 MHz.
It is important that this frequency be maintained to
within ±0.01% accuracy.
In order for a Parallel mode crystal to operate correctly
and to specification, it must have a load capacitor
connected to the junction of each of the crystal and
internal inverter connections, terminated to ground.
The values of these capacitors depend primarily on the
crystal's characteristics, and to a lesser degree on the
internal inverter circuit. The values used affect the
accuracy and start up characteristics of the oscillator.
LAYOUT CONSIDERATIONS

Good analog/digital design rules must be used to
control system noise in orderto obtain highest performance in modem designs. The more digital circuitry
present on the PC board, the more this attention to
noise control is needed. The modem should be treated
as a high impedance analog device. A 22 mF electrolytic capacitor in parallel with a 0.1 mF ceramic capacitor between VDD and GND is recommended. Liberal
use of ground planes and larger traces on power and
ground are also highly favored. High speed digital
circuits tend to generate a significant amount of EMI
(Electro-Magnetic Interference) which must be minimized in order to meet regulatory agency limitations.
To accomplish this, high speed digital devices should
be locally bypassed, and the telephone line interface
and K-Series device should be located close to each
other near the area of the board where the phone line
connection is accessed. To avoid problems, power

I

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914

0194 - rev.
9-3

Protected by the following Patents (4,691,172) (4,777,453)
©1989 Silicon Systems, Inc.

Notes:

9-4

APPLICATION NOTE
Setting DTMF Levels for
1200 Bitls K-Series Modems
Some applications of the K-series modems without output level adjustment may require setting the DTM F transmit
level to something other than the normally transmitted level. This level is nominally about 5 dB higher than during
data transmission. If the data is transmitted at -10dBm, the DTMF levels will be at about -5 dBm, which is adequate
in most applications.
The simplest way to change the relative levels of DTM Ftones and data is to change the transmit gain during dialing.
This can be accomplished as shown below. In this example, it is assumed that the DTMF tones are to be
transmitted at a higher level than normal. Closing relay K2 will increase the gain of the transmit op-amp and allow
a higher DTMF tone level during dialing. If it is desired to decrease the DTM F level, the relay can be open for dialing
and closed for data. The value of the shunt resistor, Rdtmf, will be relatively large compared to the resistor R1,
therefore the precision of Rdtmf is not as critical as R1. This means an analog switch or similar device could be
used instead of a relay, with the on resistance of the switch not seriously affecting the tolerance of the gain setting.
+5V

TO CONTROL",

____

t

~K2
-----.
Rdtmi

750 pF

14.3 kz 1%

TXA

RXA

--..----+-*--0

r

10kz

1

HOOK~<------~------~~
RING

~--------------------------'

9-5

R

I

APPLICATION NOTE

SSI73K212A High Speed
Connect Sequence

ORIGINATING MODEM
ORIGINATING MODEM TRANSMITS SCRAMBLED MARKS IN LOW BAND

---+l

~508-626ms ~

i+==

DSR
------~I--~

,
100 - 200 ms

I

TO

I

RD

:

I

1'4

DCD

I
IGNORED

231 - 308 ms

I

.:

~:.-----

:

I

I

\

/

ANSWERING MODEM

774 ms

UNCLAMPED

CLAMPED TO MARK

I

@)

CTS

/

® 1!IIII.-f------_.
231 -308ms (©
• .;.I.-t-------

ANSWERING MODEM TRANSMITS 2225 Hz

@)

I

774 ms ----~

SCRAMBLED MARKS IN HIGH BAND

DSR ALREADY ON

BOTH DCD & CTS

TO

TRANSMIT DATA INPUT IS IGNORED WHILE CTS IS OFF

RD

RECEIVED DATA OUTPUT IS CLAMPED TO MARK WHILE DCD IS OFF

9-6

I

I

DATA

I

----~.~:W!l%tN\ihl

APPLICATION NOTE

V.22 & V.22bis

Connect Sequences
V.22
CALLING MODEM
CALLING MODEM TRANSMITS SCRAMBLED BINARY ONES IN LOW BAND
DSR

I+--I

~

456 ±10 ms

~

155±50ms

DCD

:. 270 ±40 ms

:

.1'

~

.

'~,.~----

,

765 ±10 ms ----~.;:

=":-=::O=/A=;rA=)=H=Uj

TD

IGNORED

RD

CLAMPED TO BINARY ONE

"""I

UNCLAMPLED

RECEIVED DATA

©:

0;
270±40ms

ANSWERING MODEM

,~

.....r - - - - - -

UNSCRAMBLED BINARY ONE IN HIGH BAND

765±10 ms
DATA

SCRAMBLED BINARY ONE IN HIGH BAND

BOTH DCD & CTS

TO

TRANSMIT DATA INPUT IS IGNORED WHILE CTS IS OFF

RD

RECEIVED DATA OUPUT IS CLAMPED TO BINARY ONE WHILE DCD IS OFF

I

UNCLAMPED

DATA

V.22bis
CALLING MODEM

: . - - 100 ±3 ms
~:r---~----------------------------------+'~~~~~+-------------'
DATA

SCRAMBLED BINARY ONES AT 1200 BITIS

,:111---....
600±10ms

IDATARATE

---J SEiECTOR
~ 450 ±10 ms

.'

~:
,

----.:,

I

TD

I

CTS

DCD

F~~tA@rMM$M'tt$9tl

TRANSMIT DATA INPUT IS IGNORED

---------------------------------------~-~
RD

RECEIVED DATA OUPUT IS CLAMPED TO BINARY ONE

BEGIN 16·WAY
~:
DECISIONS
IN RECEIVER

UNCLAMP

~:

I

DATA

:.-DETECT 32 CONSECUTIVE 81TS
OF BINARY ONE AT 2400 81T/S

9-7

I

APPLICATION NOTE

Remote Loop
Handshake Sequence

RESPONSE

Begin in online state
TRANSMIT UNSCRAMBLED
MARK AT BIT RATE
RxD is weak pullup (TONE bit D7)
Disable CTS
Force Transmit Mark (CRl bits D7 & D6)
Bypass Scrambler (CRl bit D4)

START
......-

.." " I

Begin in online state
Monitor Unscrambled Mark (DET bit D4)
Validate for 200 ms
Continue if detect occurs

WAIT FOR DOTTING

TRANSMIT DOTTING PATTERN

Read Receive Data (DET bit D5)
Wait for 250 ms of dotting (1/0) or timeout
of 600 ms occurs
If timeout, return to online

DISABLE TERMINAL
RxD to weak pullup (TONE bit D7)
Disable CTS, DSR and DCD; Ignore DTR

TRANSMIT SCRAMBLED MARK

. . ----------1II{l1Jll1lliif'==v1

LOOP DATA

Enable Scrambler (DET bit D4)

WAIT FOR LOOPED DATA

Select RDL (CRl bits Dl & DO)
If synchronous, select slave mode
(CRO bits D5 - D2)

Read Received Data (DET bit D5)
Wait for 250 ms of Mark

FINISH CONNECTION
Unclamp RxD (TONE bit 7)
Enable CTS

TERMINATION

TERMINATION

PULSE CARRIER
Disable Transmit (CRO bit Dl)
Wait for 80 ms
Enable Carrier (CRO bit Dl)
Return to online

DETECT CARRIER
1iii""=""i:¥1

Wait for Carrier Loss (DET bit D3)
Enable CTS and DSR
Remove Data Loop (CRl bits Dl & DO)
Wait for Carrier Return (DET bit D3)
If no carrier in 200 ms, abort call

ENABLE TERMINAL
Remove Data Loop (CRl bits Dl & DO)
Unclamp RxD (TONE bit D7)
Enable DCD; stop ignoring DTR
Return to online
9-8

APPLICATION NOTE

551 73K224L
Retrain at 2400
REQUEST

RESPONSE

STARTS WITH BAD DATA
REQUEST RETRAIN

RESPOND· RETRAIN

Deactivate CTS
Clamp RxD (TONE bit 7)

INITIALIZE

DETECT S1 REQUEST

Detect S 1 for 60 ms (DET bit 06)
Wait 50 ms and Initialize the Adaptive
Equalizer (Pulse CR2 bit DO)

Detect S1 for 60 ms (DET bit 06)
Wait 50 ms:
Deactivate CTS
Force S1 transmit at 1200 bitls for
100 ms (CRO bit 06, CR1 bits
D7 & D6, CR2 bit D4)
Clamp RxD (TONE bit D7)
Initialize the Adaptive Equalizer
(Pulse CR2 bit DO)

SCRAMBLED MARK

SCRAMBLED MARK

DETECT S1 RESPONSE

Force Scrambled Mark(CR1 bits 07 & 06)
Wait 450 ms from the end of S 1 receipt
and begin 16-way decisions (CR2 bit 03)

FINISH

FINISH

After600msofScrambiedMarkat1200 bitls
Transmit at 2400 bitls (CRO bit 06)
Detect 32bits of Mark at 2400 (DET bit D5)
Unclamp RxD after 200 ms of Mark at
2400 bitls (TONE bit D7)
Activate CTS

Detect 32 Marks at 2400 bitls (DET bit D5)
Unclamp RxD (TONE bit D7)
After600msofScrambiedMarkat 1200 bitls
Transmit Marks at 2400 bitls for 200 ms
(CRObit 06)
Unclamp TxD (CR1 bits D7 & 06)
Activate CTS

I
9-9

I

APPLICATION NOTE

SSI 73K212 & 73K222
Originate Handshake Sequence
(RXDis in tri-state mode, TONE bit D7~ 1)

DIAL
1. Go off hook
2. Bring out of power down mode (CRO bits 05-02)
3. Set OTMF tone (Tone bits 04-00)
4. Turn on transmitter (Set CRO bit 01)
5. Wait OTMF on time
6. Turn off transmitter (Clear CRO bit 01)
7. Wait OTMF off time
8. Repeat 3-7 for all digits

WAIT FOR CARRIER
1 . Start S7 (Wait for carrier) timeout
2. Set to Bell 103 originate mode
(Set CRO bits 05-00 to 110001)
3. Wait for carrier detect bit (DR bit 03) to come on
4. Start sliding window counter (Wait through
possible 2100 Hz answe r tone period)
5. Qualify RXO mark* for 150 ms (DR bit 05) to
detect answer modem (Carrier detect bit must
also be on)
6. Raise OSR

~

FSK
1. Wait 100-200 ms
2. Raise OCO, start 755-774 ms timer; wait 426-446 ms, send FSK marks
(Set CR1 bits 07 & 06to 10, set CRO bit 01)
3. At end of 755-774 ms timer period (started in #2 above); raise CTS, unclamp
RXO & TXO from marking (clear TONE bit 07; clear CR1 bits 07 & 06)

--- DPSK
1. Wait 456 (V.22) or 508-626 ms (212A), switch to OPSK
2. Send scrambled marks (Set CR1 bits 07 & 06 to 10)
3. Qualify scrambled marks from answer modem for 150 ms
4. Wait for 231-302 ms of scrambled marks, raise OCO
5. Enable RXO (Tone bit 07)
6. Wait 774ms, raise CTS, enable TXO (Clear CR1 bits 07 & 06)

*This may be either answer tone from a Bell modem or unscrambled marks from a V.22 modem
9-10

APPLICATION NOTE
SSI 73K212 & 73K222
Answer Handshake Sequence
(RXD is in tri-state mode, TONE bit D7=1)

If Answer Modem is CCITT V.22
1. Go off hook at end of ring cycle
2. Wait 2 seconds
3. Send 2100 Hz for 3.3 seconds(Set TONE
bits 05 &01, CRO bits 04-00)
4. Silence for 75 ms
(Clear CRO bit 01, TONE bits 05 &00)
5.Raise OSR
6.Send unscrambled marks at 1200 bitls
(Set CR1 bit 04, CRO bit 01)

If Answer Modem is BELL 212A/1 03
1. Go off hook at end of ring cycle
2.Raise DSR
3. Wait 2 seconds
4.Send 2225 Hz (Set TONE bit 05,
clear bit ~O, set CRO bits 04-00)

I

FSK

I
DPSK

1. When carrier is detected, start sliding window counters for FSK & DPSK.
~ 2.Monitor DR bit 05; change modes between FSK and OPSK if DR bit 05 is zero. I - 3.Continue until one window counter reaches zero. Proceed in that mode.

Wait for FSK marks for 150 ms
1.Raise CTS
2.Wait 100-200 ms or "S9" time, raise OCO
3.Enable RXO, TXO (Tone bits 07 & 05)
4.Send Data

Walt for DPSK marks for 270 ms
1.Send Scrambled Marks for 770 ms (CR1 07 & 06=10)
2.Raise CTS and OCO or wait "S9," raise OCO
3. Enable RXO (TONE bit 07)
Enable TXO (CR1 bits 06 & 07=00)
4.Send Data

9-11

I

APPLICATION NOTE
I

SSI 73K224L Originate
Handshake Sequence
Ref. CCITT Red Book V.22bis Specification

set speed to 600
DIAL
Gooffhook
Turn chip power on (CRO bits 02)
Set OTMF tone (TONE bits 04-00)
Turn on transmit (CRO bit 01)
Wait required time
Turn off transmit (clear CRO bit 01)
Wait required time
Repeat for all tones
Clear OTMF bits in tone register

Data Pump Initialization
Tristate recover data
Default to async
Default 1O-bit async
Reset equalizer (CR2 bit 0)
Turn on OSP (CR2 bit 2)
Put OSP in CAlLINIT mode
(CR2bit5)
Reset receive gain bit
Turn off guard tones
Set speed to 1200
Enable 4-way decision
Disable scrambler

FSK
Select FSK mode
(CRO bits OS, 04)
Enable OSR and DCO
Force transmit marks
(CR7 bits 07, 06)
Enable transmit (CRO bit 01)
Unclamp RXO (TONE bit 07)
Wait 765 ms
Unclamp TXO (CR1 bits 07, 06)
Activate CTS
Enable receive data

Check Carrier
For 4 sec. look for valid tone:
tone valid when 95 ms of 2225 Hz
tone valid when 133 ms of SO
then wait 450 ms

when valid 2225 or SO
put OSP in demod mode
NO

NO

2400, found S1
Wait for S1 to go away
Enable equalizer
Wait 450 ms
Set 16-way decisions
Wait 150 ms
Set speed to 2400
Wait 200 ms before enabling CTS
Qualify 8 baud times of marks
Enable optional Sync mode
Enable carrier tracking in software
Enable data mode in transmitter
Send data
Enable receive data

9-12

while waiting for 100 ms
send S1
look for S1
if receiving S1
then turn on scrambler
send marks

600/1200, found marks

Turn on scrambler
Turn on equalizer
Enable transmit
Force mark
Check receiver level
Turn on equalizer
Wait 765 ms
Enable optional sync mode
Start carrier tracking in software
Enable data mode in transmitter
Send data
Enable receive data

APPLICATION NOTE
SSI 7,3K224L Answer
Handshake Sequence
Ref. CCITT Red Book V.22bis Specification

Data Pump Initialization

Set default to marks
Check and set guard tones
Turn on transmitter
Assert DSR

Tristate receiver data
Default to async
Default 1O·bit async
Reset equalizer (CR2 bit 0)
Turn on DSP (CR2 bit 2)
Put DSP in CALUNIT mode
(CR2 bit 5) demod
Reset receive gain bit
Turn off guard tones
Set speed to 1200
Enable 4·way decision
Disable scrambler

NO

NO
set tone bit to 2100 Hz

'>-----+-------..,..

Turn on scrambler
Delay 350 ms
Turn on 16·way decisions
Begin looking for 32 consecutive marks
Wait 150ms
When 32 marks received assert DCD
Send QAM marks
Wait 200 ms
Enable receive data
Enable optional sync mode
Start carrier tracking in software
Enable data mode in transmitter
Send data
60011200, found marks
Turn off answer tone
Turn off transmitter
Set default for scrambled marks
Enable transmitter
Enable equalizer in receiver
Wait 750 ms
Enable receive data
Enable optional sync mode
Start carrier tracking in software
Enable data mode in transmitter
Send data
FSK
Disable call init mode
Set speed to 300
Equalizer should be off
Disable scrambler
Send marks
Turn on transmitter
Receive 155 ms of marks
Check receive gain level
Wait 450 ms
Assert DSR
Start carrier tracking in software
Enable data mode in transmitter
Send Data

9-13

I

APPLICATION NOTE
Troubleshooting
the Modem Design
Excerpt from the Silicon Systems K-Series Modem Design Manual

Possible Causes of a Totally Dead System

possible that the oscillator will not start or will be slow
to start if the risetime of the power supply voltage is
very long. The starting properties are helped by the
asymmetry in the load capacitor values, the capacitor
at XTL 1 should be about twice as large as that at XTL2.

It is always particularly depressing when you

power-up a new design for the first time and absol utely
nothing happens. However, this is often the easiest
type of fault to find. We will try to think of a few things
that could cause this problem (apart from the obvious,
like the plug falling out of the wall socket).

Clock to Microcontroller Isn't Getting Through

You will generally get very little cooperation from
a K-Series modem IC while it is in the power-down
state. It enters this state when a reset operation is
performed, either by writing to the Reset bit (bit 2) in
Control Register 1 or by taking the RESET input pin to
logic ONE. Make sure that your firmware is bringing
the part out of this state by writing something other
than all ZEROs to bits 5 to 2 in Control Register O. Also,
make sure that this happens after the RESET pin has
been returned to logic ZERO. A capacitor from this pin
to VDD can hold the part in the reset state for many
seconds. Attempts to program the part during this
time will not take effect. For products with a DSP,
check that the RESET DSP bit (CR2 bit D2) is also
written with ONE when appropriate.

Using the K-Series modem ICs on-chip clock
oscillator to generate timing for the entire system is
very efficient from the point of view of component
count and EMI generation. However, note that the
CLK output of the modem chip is specified only to
drive TTL compatible inputs. Many common
microcontrollers require clock inputs that rise closer to
the supply voltage for logic ONE. We have seen
applications which use the CLK pin to drive these
inputs without problem, however, the low-power (5V
supply) parts may give a lower logic ONE level than is
necessary at elevated temperature. We recommend
that you use a TTL to CMOS level converting buffer
between the CLK pin and the controller clock input in
5V systems. A pull-up resistor to the SV supply is not
effective in increasing the logic high voltage. In some
cases capacitive coupling to a CMOS input is also effective if the controller clock input is properly biased.

Crystal Oscillator Falls to Start

Connect Handshake Fails

The K-Series Modem IC is Stuck in the Reset
State

If your system seems to be working well but cannot
get into the situation of exchanging data with another
modem, it is likely that you have a problem in the
connect handshake. It is better to examine handshake
problems using a "known good" modem at the remote
end rather than another of your own systems. This
helps isolate problems if more than one are present.
Use a modem from an established and reputable
manufacturer, as discounted generic modems may not
conform fully to established specifica tions. Depending
on the modulation mode, there may be many or few
opportunities to fail so we can only offer general
pointers to problems we have encountered in the past.
It is very helpful to build extra diagnostic code into the
handshake to diagnose unexpected conditions.

If a complete crystal oscillator is used to directly

drive the K-Series modem, any starting problem should
be addressed to the manufacturer of that device. If the
internal oscillator is used with a crystal, there may be
situations in which it will not start. Check the values of
the capacitors from XTLl and XTL2 to ground. If these
are too high in value, 40 pF or above, the oscillator may
not start. Such large values are not recommended and
should not be necessary if the crystal is correctly
specified. Also ensure thatthe circuit board is designed
to minimize stray inductance and capacitance in the
area of the oscillator. The crystal and both capacitors
should be placed as close as possible to the XTL pins of
the K-Series modem IC and connected by direct traces.
The ground connection of the capacitors should be via
wide traces to the digital grounding system. It is also

9-14

If things never start, check that the initial set-up of
the chip is correct. The chip must be taken out of
power-down before it will do anything and in DSPbased chips the DSP must have been reset after any
previous call and then taken out of the reset state. (A
DSP-based part cannot be used in a non-DSP socket
without many such changes to the controller code;
watch this when upgrading a 73K222 system to use a
73K224L.) If in CALLINIT mode the answer tone is not
detected, check that you have selected the desired
answer tone frequency by programming in the Tone
Register. The selectivity of the answer tone detector is
quite high, so verify that your answering modem is
generating a frequency within the specifications of the
modulation standard. You should be able to verify the
operation of your various signal detectors with
breakpoints in the controller code. If these do not fire
at the appropriate point, the handshake is likely to
hang-up or get out of step with the other modem. Be
especially careful with the S1 detector, if this is failing
you may get connections at 1200 bit/ s which were
supposed to be at 2400 bit/ s. With DSP-based chips in
QAM or DPSK modes, make sure that you are enabling
the adaptive equalizer at the appropriate time. Enabling
it too early, when the received signal is unsuitable for
training, and too late, when there is too little time left
before the gearshift to 2400 bit/ s, can both give connect
problems. Finally, make sure the crystal oscillator
frequency is in specification as a gross error here can
cause failure of the handshake.

before the equalizer is enabled, otherwise transients
caused by changing this bit may upset the equalizer
solution.
Errors Experienced at High Receive Signal
Levels

If the error rate gets worse at high receive signal
levels, you should look for some source of clipping in
the receive path. Injecting a signal of known level at the
line coupling transformer and looking at the RXA pin
with an oscilloscope should enable you to isolate any
problem in the line interface. Look for excessive gain in
the receiver buffer amplifier or other causes of clipping
at this point such as badly chosen op-amps for single
5V supply operation. If the signal at RXA looks good
and you are using a DSP-based modem chip, it is
possible that the controller is incorrectly inserting the
12 dB receiver gain boost even if the Receive Level bit
in the Detect Register is set. Note that early data sheets
for the 73K224L gave this bit the wrong sense, i.e., ONE
for low level. Only set Receive Gain Boost if this bit is
ZERO.
Errors Experienced at Low Receive Signal Levels

There can be many causes of data errors at low
receive signal levels, almost all associated with the
presence of some level of interference or noise in the
receive path. If you are performing tests over the
telephone network, make sure that the error rate you
are experiencing is not to be expected from the
background noise level on the line. It is best to use a line
simulator or a direct connection through anattenuator
if looking for system noise problems. The capacitor
across the feedback resistor of the receiver buffer
amplifier is important to attenuate out-of-band noise
at the modem chip receiver input.
Distortion in the telephone line interface can be
located by injecting low-level signals into the line
terminals and examining the signal at the RXA pin
with a spectrum analyzer. Look for crossover distortion
in the receiver buffer amplifier. This can arise from a
poorly chosen op-amp type, such as the LM324 which
makes a transition from class A to class AB operation
at low signal levels and is not suitable for this
application. We have found LM348 and LM1458 type
op-amps to be free from this problem. It is also possible
for the line coupling transformer to introduce harmonic
distortion, particularly when a large D.C. holding
current is flowing.
In the absence of significant distortion, look for a
high noise level at the RXA pin. Another symptom of
this problem, apart from data errors, is that the Carrier
Detect bit (bit 3 in DR) comes on or blinks when no
signal is applied to the modem receiver. The system
may also fail to disconnect at the end of a call. If this is

Errors Committed Immediately After Handshake,
With Later Improvement

We have seen situations in which a K-Seriesmodem
makes many data errors during the first few seconds of
a connection, butthen shapes up and performs normally
thereafter. This is generally due to some problem in
equalizer training in a DSP-based chip. The equalizer
must be held in the initial state (bit 0 of CR2 = ZERO)
up to the point in the handshake when scrambled
DPSK binary ONES first appear at the receiver. It must
then be released promptly (bit 0 of CR2 = ONE) and
allowed to adapt so that it is fully trained before the
gear shift to 2400 bit/ s and the transition to data mode
occurs. Enabling the equalizer too early will cause it to
train on an unsuitable unscrambled signal. Because it
adapts more rapidly immediately after being enabled,
it may take a long time to recover from a bad solution
when the correct receiver signal arrives. Enabling the
equalizer too late reduces the time available for training
before the received data is relied upon to be correct. If
you have to put the equalizer back into the initialized
state after a period of training, make sure that Equalizer
Enable (bit 0 of CR2) stays at ZERO for at least 2 ms. It
is better to have the Receiver Gain Boost bit dealt with
9-15

I

your experienced on' t confine your search to the normal
carrier bandwidth because the modern chip will also
be susceptible to higher frequencies. Op-amps may be
noisy or may self-oscillate at low level due to poor
layout. If the op-amps themselves are not causing the
noise, it may be due to poor circuit layout or grounding.
If, finally, nothing suspicious is visible at the RXA pin
then the noise must be getting into the receive signal
inside the modern Ie. This can be from the power
supply and bias pins or from signals routed under the
chip. Check the connections to GND, VDD, VREF and
ISET pins for component values and placement and
routing of decouplingcomponents. You are more likely
to have problems with supply noise if you are using a
switching power supply. Look also for fast digital
signals routed under the modern IC; these should be
re-routed and a ground plane placed under the chip.
Serious interference pickup problems can be created
by two crystal oscillators producing beat frequencies
in-band to the modern. We strongly recommend using
one master crystal in the system. Check the gain in the
receive path from the line terminals and, in DSP-based
parts, the state of the Receive Gain Boost bit set by the
controller. If either of these are incorrect, then noise in
the chip will appear more significant compared to the
signal.
The transmitter of the modern can be a source of
noise in the receiver. It should not generate signals that
are in-band to the receiver, but this can happen if
either the buffer amplifier or the line transformer are
causing harmonic distortion. This will be most
noticeable in call mode, when the low band transmit
signal has harmonics in the high band filter of the
receiver. For 5V only systems, the choice of op-amps in
the buffer amplifier and their D.e. bias point is crucial
to obtaining a sufficient voltage swing without
distortion. Because of its internal operation, a small
amount of switching noise is present at the TXA pin.
The capacitor across the buffer amplifier feedback
resistor is important to prevent this signal from reaching
the recei ver. It is difficult to obtain good rejection of the
transmit signal at the receiver for all practical line
conditions, but you should check that your four-wire
to two-wire hybrid circuit is operating correctly. For
most terminations, the transmit signal at the RXA pin
minus the receive buffer gain should be 6 dB below the
level at the line.

9-16

Modem Works In Loopback but Falls to Connect
or Makes Errors in Bursts with Some Other
Modems
If anything appears "flaky" about the modern
operation it is a good idea to check the oscillator
frequency with a counter capable of resolving to at
least ten parts per million. Using an oscilloscope is of
no use whatsoever. Many systems that use crystal
oscillators are not very particular about the exact
frequency; this is not so of modems. Measure the
frequency at the eLK pin and verify that it is between
11.0581 MHz and 11.0603 MHz. Do not measure at the
XTLlorXTL2pinsastheprobecapacitancewillaiter the
frequency of oscillation. Some causes of out-ofspecification readings are: a) the wrong crystal
frequency entirely, b) a series-resonant crystal, or c) a
parallel-resonant crystal unmatched to the circuit
capacitance.
Problems Unique to FSK Modes
The SSI 73K224L does not permit answer tone
detection in FSK modes, so ensure that a mode other
than FSK is selected before a ttempti ng to detect answer
tones.

SSt 78P236/2361/2362/7200
Demo Board

November 1993

DESCRIPTION

FEATURES

The 78P236 demo board is a PC board designed to
facilitate the evaluation of the SSI 78P236 series of
single chip transceiver ICs. The demo board can be
used to test different transceiver ICs by changing various
components. The demo board includes all of the
necessary discrete components for the interface to a
coded AMI line. A DIP switch allows easy control of the
option pins on the IC. A loopback function is easily
implemented using a slide switch. The same switch
allows either an encoded signal (TPOS, TNEG, TCLK)
or composite signal (TDATA, TCLK) be input to the
transmitter. Simple test patterns can be injected into the
data stream. Several jumpers allow the change of the
transmitter and receiver clock polarity.

•

Allows easy evaluation of AMI transceiver ICs

•

Includes all necessary external components

•

Includes a digital loopback mechanical switch

•

Generates ALL ONEs and repeated ONE/ZERO
patterns

•

Accepts composite Clock/Data and converts
them to AMI pulses (No B3ZS encoding)

•

Allows the use of either the receive clock or an
external clock as the transmitter clock

•

20-pin edge connector accepts flat coax cables
and provides logical signals

I
FIGURE 1: Demo Board Block Diagram

1193- rev.

9-17

SSI78P236/2361/2362/7200
Demo Board

The demo board may be loaded with components which
form a discrete equalizer for very long cables (R11, R12,
R13, C31, L10). The AMI input signal to the IC can be
monitored using a high impedance FET probe
(TEKTRONIX P4064 or HP 1141A) connected to the
TP14, TP15 pair.

POWER SUPPLY CONNECTION

The demo board is constructed as a four layer PC board.
The outer two layers carry the signals. The internal two
layers are the segmented ground and power supply
planes. Three segments separate the receive, transmit
and logical ground and supply planes. The three ground
planes are connected together using PC board traces at
JP2 and JP8 positions. These traces can be cut to
isolate the three planes from each other. The power
supply planes are connected to a single +5V banana
jack (J4) using LC fitters of 4.7 J.lH and 0.1 J.lF. When a
separate digital +5V supply is available, L1 is removed
and the DVCC supply can be connected to J2.

The input signal is coupled through a 1:1 wideband
transformer. The following table shows some of the
suggested manufacturers of this part:

RECEIVE SIGNAL PATH

The AMI signal is connected to the BNC connector J1 O.
The maximum recommended distance of the demo
board to a DSX crosspoint is 450 feet. The IC can handle
added resistive attenuation as referenced by its minimum
input signal level specification. The IC recovers clock,
positive and negative data from the AM I signal. The
following table shows the available receiver logical
signals on the test points and edge connector J5:
J5 PIN
1
3
5
7
9
11

CODE
NAME

78P236
78P7200
78P2361
78P2362

44.736
44.736
51.840
34.368

2
2
2
3

B3ZS
B3ZS
B3ZS
HDB3

PE-65966
WB1010-PC
T1-1 .

SINGLE ENDED INPUT

It is possible to directly couple the IC to the AMI signal
without a transformer using two capacitors (C29, C30)
for isolation. In this case jumpers in locations R11, R12
should be cut and the transformerT1 should be bypassed
by connecting pins 1 to 6 and 3 to 4 at the back of the
demo board. The minimum input level should be higher
than the transformer coupled circuit. The positive effect
of the transformer in rejecting common mode noise is
not achieved in this case.

The AMI input Signal should be properly coded to
prevent a long run of zeros on the line. The proper code
should limit the number of zeros to three. The following
table shows the proper coding required:
MAX
zeros

Pulse Engineering
Coilcraft
Mini Circuit

Table 1 shows the required external components for
different ICs used for receiving AMI Signals at different
speeds. Resistor R2 sets the center frequency of the
oscillator. Capacitor C6 is used to bypass any noise on
R2. Resistors R3,R20 and capacitor C26 controls the
jitter characteristic of the IC.

LOWSIGI
U1-27
RDATA = RPOS .OR. RNEG
U1-25
RPOS
RNEG
U1-24
RCLK
U1-23
RCLKI

SPEED
Mbitls

PART NO.

The AMI line is terminated at 75 ohms using R10.

TEST POINT

IC

MANUFACTURER

9-18

SSI 78P236/2361 1236217200
Demo Board

TRANSMIT SIGNAL PATH
The IC accepts CMOS level NRZ logical inputs
(TCLK,TPOS,TNEG) and converts them to the proper
AMI signal. As shown in Table 2, the three position
switchS3andjumpersJP1,5,6allowselectionofdifferent
sources for these logical signals. In its simplest case,
placing S3 in the bottom position allows a digitalloopback.
The following table shows the test points and J5 edge
connector pins used for the transmitter.

J5 PIN
15
17
19
19

As shown in Figure 2, 450 feet of 75 ohm coaxial cable
(type RG59B) and resistive attenuation is inserted in the
receive path to exercise the IC for its lowest input level.
The following tests are performed on the receiver:

TEST POINT
TCLK
TNEG
TPOS
TDATA

clock input
negative data
positive data
composite data

BIT ERROR RATE TEST
A pseudo-random pattern is generated by the test
equipment. This pattern is created using a shift register
of N bits. Preventing an all zero pattern, a combination
of 2**N-1 patterns of N bits is created in a random
manner. This pattern is used to simulate the live traffic
on the AMI line. The following table shows the mostly
used patterns to test the IC:

The outputs of the IC, LOUT+ and LOUT -, are connected
to a 1:1:1 wide band transformer. The following table
shows some of the suggested transmitter transformers:

MANUFACTURER

PART NO.

Pulse Engineering
Minicircuit

PE-65969
T4-1

PERFORMING TESTS WITH DEMO BOARD
The general test setup using the demo board is shown
in Figure 2. When the switch S3 is placed in its bottom
poSition (Ioopback), the receiver logical output signals
(RCLK, RPOS, RNEG) from the IC are connected to the
transmitter logical input (TCLK, TPOS, TNEG). As a
result, the received AMI Signal is transmitted back to the
test equipment. Bit error rate testing will indicate the
ability of the IC to receive and transmit the AMI signal
with no errors.

The transformer center tap is connected to the +5V
supply through a filter comprised of a 4. 7 ~ inductor and
a 0.11lF capacitor. The capacitor C27, when added to the
PC board trace and the transformer input capacitances,
will effect the pulse shape. This capacitor should be
selected for individual PC boards. The objective is to
meet a pulse template at any cable length up to a
maximum of 450 feet. The generated AMI signal is
available on the BNC connector, J11, and it can be
monitored on TP12, TP13 pair using a high impedance
probe.

IC

RANDOM
PATTERN

FIXED
PATTERN

78P236
78P7200
78P2361
78P2362

2**15-1
2**15-1
2**15-1
2**23-1

100100 ...
100100 ...
100100 ...
10001000

When running these patterns, no bit errors are expected
in the absence of any noise. The test is repeated forfixed
patterns to exercise the IC for any pattern sensitivity.
JITTER TOLERANCE
Telecommunication equipments should be able to
recover clock and correct data even if the AMI Signal
includes a reasonable amount of timing jitter. For this
test, the test equipment adds jitter to the random AMI
signal. For jitter at a set frequency, the amplitude of the
jitter is slowly increased until bit errors are observed.
This process is repeated at different frequencies and a
plot of the maximum tolerated jitter vs the jitter frequency
is made as shown in Figure 3. The IC should tolerate
jitter in excess of specified requirements.

OPTION PINS CONTROL
Switch S1 changes the logic level of the option pins on
the IC which controls the transmitter. Table 3 shows the
function of this switch.

9-19

9

SSI78P236/2361/2362/7200
Demo Board

INTRINSIC JITTER

PULSE AMPLITUDE

The jitter generated by the IC in the absence of any jitter
on ns transmitter logical input (TCLK, TP08 TNEG).
should be minimal.

The pulse amplnude for a pattern of 1001 00 ... is measured
at different cable lengths by connecting the end of the
cable to the scope using a 75 ohm termination adaptor
(POMONA 4119). Except for the 78P2362, whose
transmitted pulse amplitude is needed to be fairly exact
(2 Vp-p ± 5%), other IC's transmit amplitude may fall in
a wide range of amplitudes from 0.72 to 1.7 Vp-p.

JITTER TRANSFER FUNCTION
The IC should not cause any amplification of the system
jitter, i.e., no peaking should be observed in the jitter
transfer function. This objective is achieved by selecting
the PLL filter components for an overdamped response.
The test equipment adds jitter to the AMI signal received
by the IC. Measuring the jittertransmitted by the IC in the
digitalloopback mode indicates the shape ofthe transfer
function. As shown in Figure 4, the IC adds no peaking
and higher frequency jitter is attenuated.

PULSE TEMPLATE
The shape of the signal is examined by comparing it to
the published templates. The test setup is shown in
Figure 2. The program resident in the computer reads
the transmitter waveform from the scope, scales it
vertically, and plots it togetherwith the published template
masks. The pulse shape should meet the mask for all
cable lengths from zero to 450 feet. The LBO pin as
controlled by switch 81-1 should be properly set. For
cable length of less than 225 feet this switch is open and
for longer cables this switch should be closed. A typical
pulse shapes for the 78P236 at the end of 450 feet of
cable is shown in Figure 5.

TRANSMITTER TESTS
The AMI pulse generated by the IC can be tested for its
shape, amplitude and frequency content over different
lengths of cable. The demo board is usually placed in
the loopback mode (83 in bottom position).
PULSE FREQUENCY CONTENTS

PULSE IMBALANCE

For an AMI signal with an all ones pattern, the transmnted
signal should have a frequency spectrum with the main
component at half of the bit rate. The signal power at the
harmonics including the component at the bit rate should
be at least 20 dB lower than the main component. A
spectrum analyzer is used for this purpose.

The AMI pulse generated by the Ie includes pulses of
both negative and positive polarities. The pulse imbalance
is examined by inverting the negative pulse using the
scope and overlaying tt on a typical positive pulse. No
significant imbalance is observed.

TABLE 1: External Components List for Different ICs
Data sheet ref. ->
Demo board ref. ->
Unit
->

RFO
R2
kQ

RLF1
R3
kQ

RLF2
R20
kQ

CLF1
C26
J.lF

RTR
R10
Q

RTT
R6
Q

CTT
C2
pF

78P236

44.736

5.23

20

100

0.22

75

None

10

78P7200

44.736

5.23

6.04

100

0.22

75

301

10

78P2361

51.840

4.53

20

100

0.22

75

None

10

78P2362

34.368

6.81

20

100

0.22

75

None

5

9-20

---

SSI78P236/2361/2362/7200
Demo Board

TABLE 2: Sources of the Transmitter Logical Signals
Switch

Source of:
TPOSITNEG

53

JP5
2-1

JP5
2-3

JP1
2-1

JP1
2-3

JP6
2-1

External
Converted
fromTDATA

RCLK
RCLK

EXT
EXT

Buffered
Buffered

Inverted
Inverted

JP6
2-3

Internally
generated

RCLK

EXT

Buffered

Inverted

RP05/RNEG

RCLK

RCLK

RCLK

RCLK

Top
Middle

Polarity of:
TCLK

Source of:
TCLK

Bottom

TABLE 3: Function of the DIP Switch S1
Position

ICPln

Function

Closed

Open

51-1

LBO

TX cable length

L < 225'---_ ...

51-2

OPT1

TX amplitude

Normal

51-3

OPT2

TX disable

Enable
-----_..

L> 225'
Boost 2.7 dB
~-.---

51-4

None

-

--

1010 ...

test pattern
JP6 2-3, 53 Mid.

IEEE CABLE
SCOPE
'--_ _--,75Q

II

I PRINTER I

IBM PC + SOFTWARE
+IEE488

FIGURE 2: General Test Setup
9-21

Disable
111 ...

551 78P236/2361/2362/7200
Demo Board

c:

~

10

.....

............. ............. .....

6..

2w

......

0
::J
I--

::i

'.

1.0

0..

:2

«

'"~
.'.'...

~

""

.....

a:
w

I-I--

'.

'.

=; 0.1

0.01
10

100

1K

10K

100K

1M

JITTER FREQUENCY (Hz)

FIGURE 3: Jitter Tolerance for 78P236

+20

+10

00
~

0

\

z

~

C)

a: -10
w

I-I--

::;
-20

\

-30
10

100

1K

10K

100K

JITTER FREQUENCY (Hz)

FIGURE 4: 78P236 Jitter Transfer Function
Loop Filter BW = 165 kHz
9-22

1M

SSI 78P236/2361 1236217200
Demo Board

1.0
0.9
TEMP = 25°C
en =5 pF
TRANSFORMER: PE 65664
LENGTH: 450 FT.

0.8
~
c(

w

0.7

0

0.6

w
C/)

0.5

+

0.4

a..
ff-

f::J

0
..J

0.3
0.2
0.1
0.0
-.06

-.04

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

TIME SLOTS (UI)

FIGURE 5: Transmitter Pulse Shape for 78P236

I
9-23

oen
(Den
TP30
TP

SHORT FOR
SINGLE ENDED INPUT

tJr

053_'N

REV B2

Ul

TP31
TP

TP32
TP

~~ IY

L1

0

o

<0

D53_0UT

Sl_;:=::j_

~

~i70
6

... en

I\)

N
~

_

m'"tJ
01\)

mW

W

RVCC

4

.....

Q)

I\)

RGND

-=:J
-=:J
-=:J

~~

3-

0

I\)

NCR2
RFO

~

TP35

--en
--.....o

DVCC

n~~~

TP34

a.-I\)
W
en
.....

LlN+

L 6~6~

ONL~Y

TP32
TP

0

1[5

SW DIP-4

FIGURE 6: Demo Board Schematics

551 78P236/2361 1236217200
Demo Board

N. 1- > NOT INSTALLED
CUT FOR SINGLE ENDED

1R11- 1

'~~----~--------~~OUT2

2

CUT FOR SINGLE ENDED

FIGURE 7: Pad / Equalizer

vee

1
T

C20
.01

J.

1
T 1 1
T
C21
.01

C22
.01

C23
.01

vee
JP6

U3B
12 0
11

P
R

0

C
l

Q

9

>ClK
8
74F74

}-.:..:----<~--------CTXPOS-

74F08

vee
U3A
2

0

0

5

a

6

I

>ClK

74

4

74F08
74F02

vee

TXNEG
74F08

rnlJC)----o... JP5
TClKB

FIGURE 8: Encoder
9-25

SSI78P236/2361/2362/7200

Demo Board

ORDER~G~FORMATION

DEMO BOARD PART NUMBER

AMI SPEED
Mbit/s
SSt 78P236/2361/2362/7200 Demo Board

---.-.--..

44.736

OS-3

78P236-0B

44.736

OS-3

78P7200-0B

51.840

STS-1

78P2361-0B

34.368

E-3

78P2362-0B

-.-----.--~---

---. - - - . - - - - - - - - . - -

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX (714) 573-6914
1193 - rev.

9-26

SSI78Q8373
Technical
Reference
Guide

I

DISCLAIMER
THIS MANUAL IS INTENDED TO BE USED AS A GUIDE ONLY. Silicon Systems does not warrant any of the schematics shown or code segments
provided to be qualified for production. No responsibility is assumed by Silicon Systems for use or installation of the products described herein, nor any
infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or
trademarks of Silicon Systems. Silicon Systems reserves the right to make changes in specifications at any time without notice.

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1994 Silicon Systems, Inc.

9-27

0894

9-28

OVERVIEW
INTRODUCTION
The SSI 78Q8373 is a device for Ethernet LAN applications that consists of an Ethernet protocol controller, Manchester Encoder/
Decoder, lOBaseT transceiver, AUI port, and PCMCIA Bus Interface logic on one chip. It can operate using a 5-volt or 3.3-volt
supply. This document contains detailed descriptions of key parts of the protocol controller block, namely, the Buffer Manager block
and the Data Link Controller block, along with bit descriptions of all of the control and status registers. In addition, there is
information on the power management capabilities of the SSI 78Q8373, how to configure the part for host and medium connections,
information about how a host processor would handle packet transmission and reception on a network, and descriptions of the media
interfaces (lOBaseT and AU!) and PCMCIA Bus Interface. For detailed pin descriptions, electrical and timing parameters, please
refer to the SSI 78Q8373 Data Sheet.

2

GENERAL DESCRIPTION
The SSI 78Q8373 combines the Ethernet network interface together with packet data management and consists of six major blocks:
• Buffer Manager (and SRAM Interface)
• Data Link Controller
• Host/PCMCIA Interface
• Manchester data Encoder/Decoder (EN DEC)
• Twisted-pair Transceiver
• Power Management

78Q8373

SRAM
Interface
'--

Host!
PCMCIA
Interface

-

::::x::::::::::

-

Twisted Pair Medium

10BaseT
Transceiver

Buffer
Manager

Data Link
Controller

::::x::::::::::

Manchester
ENDEC

AUI
Port

Power
Management

?

":.

PCMCIA
Bus

Figure 1-1: Block Diagram (7808373)
.2.1 Buffer Manager
The Buffer Manager manages all accesses to the buffer memory through the SRAM interface. The buffer memory is connected
directly to the Data Link Controller (DLC), thus eliminating the need for a local microprocessor. The Buffer Manager also keeps
track of all buffer memory pointers automatically; simplifying the software driver task. Together with intelligent arbitration, the
SSI 78Q8373 is a high performance LAN controller.
The buffer memory is divided into a transmit memory section and a receive memory section. The transmit memory section can be
partitioned into 2K, 4K, 8K or 16Kbyte buffer sizes. If the transmit buffer size is greater than 2KB, then the transmit buffer is
9-29

I

1.2.1 Buffer Manager (continued)
configured into two banks of equal size. There is only one transmit bank if a 2KB buffer size is selected. With the two ban
configuration, one transmit bank may be tied up during transmission but the host can still continue to load data packets into the secoOi
transmit bank to be tranmitted later. The receive buffer has a ring architecture which can be configured from 4K to 62KB dependin;
on the buffer memory configuration, which can range in size from 8K to 64KB.
A central arbitrator inside the Buffer Manager prioritizes and services requests for access to the buffer memory from four source5
the Transmitter, the Receiver, Host Read and Host Write. If necessary, the SSI 78Q8373 will assert a 'not ready' handshake to th
host while servicing the Transmitter and/or Receiver. The SSI 78Q8373 arbitration mechanism provides packet management b:
interleaving packet data accesses to the buffer memory such that the operation appears to be simultaneous.
For instance, in the situation where 2 transmit banks are configured, the host can load the first transmit bank and initiate ,
transmission. While the first transmit bank is being transmitted, the host can continue to load packets in the second transmit ban~
At this stage, the SSI 78Q8373 can potentially be receiving data from the medium and loading it into the receive buffer (if the SS
78Q8373 is in a loopback mode or if self-reception occurs).

1.2.2 Data Link Controller
The Data Link Controller (DLC) implements the ISO/ANSI/IEEE 8802-3 CSMAlCD protocol. It consists of a Transmitter and:
Receiver, each with its own independent CRC logic. Automatic generation and stripping of the 64-bit preamble and the 32-bit CR(
code are provided on-chip.

1.2.3 Host/PCMCIA Interface
The Host Interface provides connection to the host system. It consists of the various registers, DMA circuits and ready logic. Bot!
word and byte interfaces are supported as well as big endian and little endian data ordering. Host access to the buffer memory i
through BMR8 (and BMR9). Reading from BMR8 will read a byte or word from the receive buffer and writing to BMR8 will write
a byte or word to the transmit buffer. The ready logic is capable of delaying host access to the buffer memory with a time-ou
mechanism. Both single and burst DMA transfer modes are supported.
The PCMCIA interface circuitry builds on top of the SSI 78Q8373 generic host interface and is only active if the MODE pin is let
unconnected (internally pulled-up). The SSI 78Q8373 can thus connect directly to a PCMCIA release 2.1 compliant bus. It als(
supports decoding fortheextemal CIS memory (both ROM and Flash types). The SSI 78Q8373 pinout has been defined to minimiz<
criss-crossing connections to the PCMCIA connector. This allows for a cost effective 2-layer PCB design.

1.2.4 Manchester ENDEC
This block implements Manchester encoding and decoding. Serial NRZ data from the DLC is converted to Manchester encode<
data and sent to either the twisted-pair transceiver block or to the Attachment Unit Interface (AUI) driver, depending on which i:
active. The decoder section performs three functions: clock recovery, carrier detection and Manchester decoding. The recovere<
receive clock will be low atthe end of reception and during idle to save power. Jitter of up to ±l8 nsec can be tolerated by the decoder
This block also translates a lOMHz collision signal to a logic-level signal before sending it to the DLC block if the AUI port i:
selected.

1.2.5 Twisted-Pair Transceiver
The on-chip Twisted-Pair module consists of the following functions. It has a smart squelch circuitry to determine valid data presen
on the differential receive inputs (TPIPIN). Its transmit and pre-distortion drivers connect to the twisted-pair network via th<
summing resistors and transformer/filter. The liole detector/generator circuitry checks the integrity of the cable connection the tW(
twisted-pair MAUs. Collision, jabber and SQE(are also incorporated.

1.2.6 Power Management
One very useful and important feature that the SSI 78Q8373 offers is intelligent power management. It supports three differenl
power saving modes: Intelligent, Standby, and Full Shutdown. All modes are configurable through registers. In the Intelligenl
mode, clocks are active only when they are needed. For example, when not transmitting, the clock supplied to the transmittel
circuit in the DLC block is not active while host read from buffer memory may be active. In Standby mode, the oscillator clod
is disconnected from the rest of the circuits, so that only the oscillator circuits draw power. Full Shutdown turns off the oscillator
resulting in maximum power savings. Note that this mode is not available when using an external clock source.

9-30

1.2.7 Pin Assignments
Following are the pin assignments for both the QFP and TQFP versions of the SSI 78Q83 73.
TABLE 1: Pin Assignment Table - PCMCIA Bus Mode -100-Lead TQFP
PIN#

PIN NAME TYPE PIN# PIN NAME TYPE

PIN# PIN NAME TYPE

PIN#

PIN NAME TYPE

1

D1

104

26

OE

I

51

RA4

04

76

DON

AO

2

D8

104U

27

WE

I

52

RA5

04

77

DOP

AO

3

DO

104

28

INPACK

04

53

RA6

04

78

AGND

P

REXT

R

4

AO

I

29

REG

I

54

GND

P

79

5

A1

I

30

ROMG

04

55

VDD

P

80

6

A2

I

31

FCE

04

56

RA7

04

81

7

A3

I

32

XPD

04

57

RA12

04

8

RESET

SI

33

XRST

04

58

RA14

9

VDD

P

34

GND

P

59

RWE

10

GND

P

35

ROO

104U

60

11

10WR

I

36

RD1

104U

12

lORD

I

37

RD2

13

CE2

I

38

RD3

14

015

104U

39

15

CE1

I

16

014

17

--

AVDD

P

TPIN

AI

82

TPIP

AI

04

83

MODE

TI

04

84

DIN

AI

RA13

04

85

DIP

AI

61

RA8

04

86

CIN

AI

104U

62

RA~

04

87

CIP

AI

104U

63

RA11

04

88

GND

P

RD4

104U

64

ROE

04

89

SPKRIN

SI

40

RD5

104U

65

RA15

04

90

SPKR

08

104U

41

RD6

104U

66

OSCI

CI

91

CCRA

I

07

104

42

RD7

104U

67

OS CO

0

92

RRST

04

18

GND

P

43

GND

P

68

VDD

P

93

LEDLT

OD16

19

013

104U

44

RCSO

04

69

GND

P

94

CB

04

20

06

104

45

RCS1

04

70

GND

P

95

10lS16

04

21
22

D12
05

104U
104

46
47

RA10
RAO

04
04

71
72

TPDN
TPDP

AO
AO

96
97

IREO
WAIT

08
04

23
24

D11
04

104U
104

48

RA1

04

010

04

TPON
TPOP

98

RA2

73
74

AO

49

AO

99

02

104U
104

25

03

104

50

RA3

04

75

VDD

P

100

D9

104U

- --.--~-

--

- - _ ...
--_.--

-

-----~-

------ -

..

-

Legend:
I:
04, 08:
0016:
104, 104U:

Input (TTL level)
Output with 10L = 4 or 8 rnA
Output Open Drain with 10L = 16 rnA
Input (TTL level) and Output with 10L = 4 rnA; 104U refers to 104 with an internal pull-up resistor

CI:
SI:
TI:
AI:
AO:
P:
R:
0:

CMOS level input
Schmitt trigger input
Three-state input. May be connected to low, high, or left open.
Analog input
Analog output
Power
Resistor to ground
Output

9-31

I
•

TABLE 2: Pin Assignment Table - PCMCIA Bus Mode -100-Lead QFP
PIN# PIN NAME TYPE PIN# PIN NAME TYPE PIN# PIN NAME TYPE PIN# PIN NAME TYPE

1

D10

104U

26

D11

104U

51

RA1

04

76

TPON

AO

2

D2

104

27

D4

104

52

RA2

04

77

TPOP

AO

3

D9

104U

28

D3

104

53

RA3

04

4

D1

104

29

OE

I

54

RA4

04

5

D8

104U

30

WE

I

55

RA5

04

6

DO

104

31

INPACK

04

56

RA6

04

78

VDD

P

79

DON

AO

---

80

DOP

AO

AGND

P

82

REXT

R

83

AVDD

P

TPIN

AI

TPIP

AI

MODE

TI

----------

81

7

AO

I

32

REG

I

57

GND

P

8

A1

I

33

ROMG

04

58

VDD

P

9

A2

I

34

FCE

04

59

RA7

04

84

10

A3

I

35

XPD

04

60

RA12

04

85

61

RA14

----

-

_.-

---

11

RESET

SI

36

XRST

04

04

86
-------

12

VDD

P

37

GND

P

62

RWE

04

87

DIN

13

GND

P

38

RDO

104U

63

RA13

04

88

DIP

14

IOWR

I

39

RD1

104U

64

RA8

04

89

CIN

AI

65

RA9

04

90

CIP

AI

15

lORD

I

40

RD2

104U

AI
-~

------

16

CE2

I

41

RD3

104U

66

RA11

04

91

GND

P

17

D15

104U

42

RD4

104U

67

ROE

04

92

SPKRIN

SI

18

CE1

I

43

RD5

104U

68

RA15

04

93

SPKR

08

19

014

104U

44

RD6

104U

69

OSCI

CI

94

CCRA
RRST

I
-~

20

D7

104

45

RD7

104U

70

OSCO

0

95

21

GND

P

46

GND

P

71

VDD

P

96

LEDLT

OD16

22

D13

104U

47

RCSO

04

72

GND

P

97

CB

04

-----_.- - - - - -

-

----~

23

D6

104

48

RCS1

04

73

GNO

P

98

10lS16

04

24

012

I04U

49

RA10

04

74

TPON

AO

99

IREO

08

25

05

104

50

RAO

04

75

TPOP

AO

100

WAIT

04

---~-

Legend:
I:
04,08:
0016:
104,I04U:
CI:
SI:
TI:
AI:
AO:
P:
R:
0:

Input (TTL level)
Output with 10L = 4 or 8 rnA
Output Open Drain with 10L = 16 rnA
Input (TTL level) and Output with 10L = 4 rnA; 104U refers to 104 with an internal pull-up resistor
CMOS level input
Schmitt trigger input
Three-state input. May be connected to low, high, or left open.
Analog input
Analog output
Power
Resistor to ground
Output

9-32

TABLE 3: Pin Assignment Table - Generic Bus Mode -100-Lead TQFP
PIN#

PIN NAME TYPE

PIN# PIN NAME TYPE

PIN# PIN NAME TYPE PIN#

PIN NAME TYPE

1

HD1

104

26

RD8

104U

51

RA4

04

76

DON

AO

2

HD8

104U

27

RD9

104U

52

RA5

04

DOP

AO

3

HDO

104

28

RD10

104U

53

RA6

04

AGND

P

4

HAO

I

29

RD11

104U

54

GND

P

77
78
79

REXT

R

5

HA1

I

30

RD12

104U

55

VDD

P

80

AVDD

P

6

HA2

I

31

RD13

104U

56

RA7

04

81

TPIN

AI

7

HA3

I

32

RD14

104U

57

RA12

04

82

8

RESET

SI

33

RD15

104U

58

RA14

04

83

9

VDD

P

34

GND

P

59

RWE

04

84

DIN

AI

10

GND

P

35

RDO

104U

60

RA13

04

85

DIP

AI

11

WR

I

36

RD1

104U

61

RA8

04

86

~

~------.--

-_.-

TPIP

AI

MODE

TI

----------------

_.. _-

CIN

~.-----

12

RD

I

37

RD2

104U

13

BHE

I

38

RD3

104U

62

RA9

04

63

RA11

04

-

-------~-

87

AI
-----

CIP

AI

GND

P

-~-~

88
-----

14

HD15

104U

39

RD4

104U

64

ROE

04

15

CS

I

40

RD5

104U

65

RA15

04

89

DMACK

SI

DMREQ

08

~-------

16

HD14

104U

41

RD6

104U

66

OSCI

CI

90
-_..91

17

HD7

104

42

RD7

104U

67

OSCO

0

92

18

GND

P

43

GND

104U

68

VDD

P

--

EOP

I

RRST

04

LEDLT

OD16

- ---

------_ ..-

93
----

19

HD13

104U

44

RCSO

P

69

GND

P

20

HD6

104

45

RCS1

04

70

GND

P

21

HD12

104U

46

RA10

04

71

TPDN

AO

96

INT

08

22

HD5

104

47

RAO

04

72

TPDP

AO

97

READY

04

23

HD11

104U

48

RA1

04

73

TPON

AO

98

HD10

104U

24

HD4

104

49

RA2

04

74

TPOP

AO

99

HD2

104

25

HD3

104

50

RA3

04

75

VDD

P

100

HD9

104U

94

CB

04

HWORD

04

- -------

95
- ----------_.._--

Legend:
I:
04,08:
OD16:
104,104U:
CI:
SI:
TI:
AI:
AO:
P:
R:
0:

Input (TTL level)
Output with 10L = 4 or 8 rnA
Output Open Drain with 10L = 16 rnA
Input (TTL level) and Output with 10L = 4 rnA; 104U refers to 104 with an internal pull-up resistor
CMOS level input
Schmitt trigger input
Three-state input. May be connected to low, high, or left open.
Analog input
Analog output
Power
Resistor to ground
Output

9-33

9

TABLE 4: Pin Assignment Table - Generic Bus Mode -100-Lead QFP
PIN#

PIN NAME TYPE

PIN# PIN NAME TYPE

PIN# PIN NAME TYPE PIN#

HD10
HD2

104U

104U

51

RA1

04

104

26
27

HD11

2

HD4

104

52

RA2

04

3
4

HD9
HD1

104U
104

28
29

HD3
RD8

104

RA3

104U

53
54

5

HD8

104U

30

RD9

104U

6
7

HDO

104
I

31

RD10

I

32
33

1

PIN NAME TYPE

76
77

TPON

78
79

VDD

p--

RA4

04
04

DON

AO

55

RA5

04

80

DOP

AO

104U

56

RA6

04

81

RD11
RD12

104U

57

-R

58

P
P

82

104U

GND
VDD

AGND
REXT
AVDD

59
60

RA7
RA12

04

.------

AO

TPOP

AO

---~

----~-------

HAO
HA1

8

---~---

9
10

HA2

I

34

RD13

HA3

I

35

RD14

104U
104U

11

RESET

SI

36

RD15

104U

61

RA14

04

12

VDD

P

37

GND

P

62

RWE

04

13

GND

P

38

RDO

104U

63

RA13

04

14

WR

I

39

RD1

104U

64

RA8

04

15

RD

I

40

RD2

104U

65

RA9

04

16

BHE

I

41

RD3

104U

66

RA11

04

17

HD15

104U

42

RD4

104U

67

ROE

04

18

CS

I

43

RD5

104U

68

RA15

04

19
20

HD14

21

-

44

HD7

104U
104

45

RD6
RD7

GND

P

46

GND

104U
P

22

HD13

104U

47

RC80

23

HD6

104

48

RC81

24

HD12

104U

49

RA10

04

74

TPDN

25

HD5

104

50

RAO

04

75

TPDP

104U

04

OSCI

CI

71

OSCO
VDD

0
P

04

72

GND

P

04

73

GND

P

69
70

-_._--- ----

P

~----~-

83
84

--------- -

p--

- - --

85

TPIN

TPIP

---

86
MODE
r----------87
DIN
-88
DIP
89

AI

-~--

90

-----------

91

CIP

92

--_._----

GND

..

AI

r---

P

--_._----

DMACK

SI

--

DMREQ

93

-

AI

--~--

--

----_.".-.

---------_

TI
AI

CIN

---_.- ..

AI
AI

08

--

----~---

94

EOP
I
- - - - - - --,---RRST
95
04
-- _.•LEOLT
96
0016
1-------- - - - - - - - - - 97
CB
04
----_... _---

1-

-~--

98

HWORD

AO

99

INT

08

AO

100

READY

'"C54

f--------- -----

-----

04

Legend:
I:
04, 08:
OD16:
104, 104U:
CI:
81:
TI:
AI:
AO:
P:
R:
0:

Input (TTL level)
Output with 10L = 4 or 8 rnA
Output Open Drain with 10L = 16 rnA
Input (TTL level) and Output with 10L = 4 rnA; 104U refers to 104 with an internal pull-up resistor
CMOS level input
Schmitt trigger input
Three-state input. May be connected to low, high, or left open.
Analog input
Analog output
Power
Resistor to ground
Output

9-34

~

BUFFER MANAGER
The Buffer Manager manages accesses to the buffer memory through the SRAM interface. The buffer memory is connected directly
to the Data Link Controller (DLC) , thus eliminating the need for a local microprocessor. The Buffer Manager keeps track of all buffer
memory pointers automatically, simplifying the software driver task. Together with intelligent arbitration for accesses to the buffer
memory, this makes the SS! 78Q8373 a high performance LAN controller.

!.1

BUFFER MEMORY CONFIGURATION

There are 13 different ways in which to configure the transmit and receiver buffer SRAM for the SSI 78Q8373. This is done using
4 register bits, DLCR6<3:0>. DLCR6<1:0> sets the total buffer memory size and DLCR6<3:2> sets the transmit buffer size. If
the transmit buffer is greater than 2KBytes, it is divided into two transmit banks as shown in the table below.

BS1
DLCRS(1)

BSO
DLCRS(O}

TS1
DLCRS(3)

TSO
DLCRS(2)

0

0
0
0

0

0

0
1
1

1
0
1

0

0

0
1
1
0
0
1
1

1
0
1
0
1

1)

0
0
0

0
0
0
1
1
1
1
1
1

1
1

0
1
1
1
1
0
0
0

0

0

1
1
1
1

0
1
1

0
1
0
1

0
1

TOTAL
BUFFER
MEMORY
8KBYTES
8KBYTES
16KBYTES
16KBYTES
16KBYTES
32KBYTES
32KBYTES
32KBYTES
32KBYTES
64KBYTES
64KBYTES
64KBYTES
64KBYTES

TRANSMIT BUFFER MEMORY
TX BANK #1
TX BANK #2
2KBYTES
-2KBYTES
2KBYTES
IlIeaal set-uD
IlIeaal set-uD
2KBYTES
-2KBYTES
2KBYTES
4KBYTES
4KBYTES
IIleaal set-uD
2KBYTES
-2KBYTES
2KBYTES
4KBYTES
4KBYTES
8KBYTES
8KBYTES
2KBYTES
-2KBYTES
2KBYTES
4KBYTES
4KBYTES
8KBYTES
8KBYTES

RECEIVE
BUFFER
MEMORY
6KBYTES
4KBYTES
14KBYTES
12KBYTES
8KBYTES
30KBYTES
28KBYTES
24KBYTES
16KBYTES
62KBYTES
60KBYTES
56KBYTES
48KBYTES

The remaining buffer memory that is not used by the transmit memory will be used as the receive memory. Figure 2-1 shows an
example of a buffer memory configuration of 64 KBytes.

TX
BUFFER

2 KBYTES

2 KBYTES

4 KBYTES

2 KBYTES

8 KBYTES

4 KBYTES
8 KBYTES

RX
BUFFER

62 KBYTES

60 KBYTES

56 KBYTES

48 KBYTES

Figure 2·1: Maximum Buffer Size (64 KBytes) for Transmit and Receive Buffers

9-35

I

2.1

BUFFER MEMORY CONFIGURATION (continued)
The buffer memory path of the SSI 78Q8373 is 8 bits wide in PCMCIA Bus mode and can be either 8 or 16 bits wide in Generic
Bus mode (The 8-bit path in PCMCIA mode is imposed due to the lack of enough pins). In the Generic Bus mode, the buffer memory
data path width is selected through DLCR6<4>. IfDLCR6<4> is set toa 1, then the SSI 78Q8373 data path will be byte-wide. There
are eight different SRAM configurations depending on whether the data path is 8- or 16-bit (refer to Figure 2-2). The RCSO and
RCS1 are the SRAM chip select pins. In the 8 bit-data bus for 8KByte and 32KByte configurations, only RCSO is used and the
address least significant bit starts from AO. Figure 2-2 shows the configurations possible for the SRAM.

8 Bit RAM Data Bus:

DLCR6 (1:0)

DLCR6 (4)
DLCR6 (5)

RBYTE
HBYTE

=1
=°OR 1

16 Bit RAM Data Bus:
available in Generic Bus mode only
DLCR6 (4)
DLCR6 (5)

RBYTE
HBYTE

=
=

°°

RA12·RA1
RA12·RAO

8$1,0

=0,0

RO(7:0)

RA13·RA1

RA13·RA1

8$1,0

8$1,0

=0,1

RA14·RAO

RA14·RA1

RA15·RA1

RA15·RA1

=1,0

RO(7:0)

8$1,0

=1,1

Figure 2·2: SRAM Configurations
9-36

TRANSMIT OPERATION

The SSI 78Q8373 complies with the IEEE 802.3 CSMNCO specifications with a transfer rate of 1OMbit/s through the transmission
medium. It will assemble all packets from the host and append a 64-bit preamble and a 32-bit CRC to the head and tail of each packet
respectively before transmitting to the medium. As mentioned in the Buffer Memory Configuration section, one or more packets
can be written by the system within a transmit memory bank until the remaining space is insufficient for another packet. The host
can then issue a signal, called "Transmit start" which is stored in BMR 10<7> to initiate a transmission to the medium. All packets
within the same bank will thus be transmitted and followed by the status update or an interrupt if it is enabled. With the two transmit
banks configuration, one bank can be transmitting and the second bank can be loading data from the system. This concurrent
operation of transmitting and host writing will improve transmission throughput.
If the transmit packet encounter a collision in the medium, the SSI 78Q8373 will perform a truncated binary exponential backoff
routine up to 16 attempts. After the 16th attempt, the SSI 78Q8373 will either skip the current packet or re-transmit the packet again'
depending on the status of BMR 11 <2:0>.
TRANSMIT PACKET DATA FORMAT

The packet to be transmitted is first loaded into the transmit buffer together with a 2-byte header of data length in bytes. Figure
2-3 shows an example of how 3 packets are stored within a single transmit buffer:

Packet Length (LSB)
Packet Length (MSB)

Packet #1

Data1
Packet Length (LSB)
Packet Length (MSB)

Packet #2

Data2
Packet Length (LSB)
Packet Length (MSB)
Data3

Figure 2-3: Packet Format in Transmit Buffer
After the packets are loaded, the host will write the number of packets to be transmitted into BMR 10 and initiate transmission. At
this stage, if a two transmit banks configuration is chosen, any new packets can now be loaded into the second bank.
.4

RECEIVE OPERATION

The receive memory is configured as a ring structure which means the bottom of the memory is wrapped around to the top of the
receive memory. There are two pointers to handle incoming packet management and they are the receive pointer and the host read
pointer. The receive pointer will always point to the next empty location in the receive memory. The host read pointer is used by
the host to retrieve accepted packets from the receive memory.
Initially, the values of the two pointers are equal which implies that the receive buffer is empty. As soon as data is loaded into the
receive bank from the medium, the receive pointer will move away from the host read pointer. The preamble and the CRC bits are
automatically removed by the data link controller (OLC) before storing the data to the receive buffer. While accepting the data, the
size of the packet is checked. Under the IEEE specifications, the valid packet size is between 60 bytes to 1500 bytes (minus the
preamble and CRC portions). However, if set to I, the SSI 78Q8373 can accept packet sizes ranging from 6 bytes (by setting "accept
short packet" in OLCR5<3> [ENA_SRTPKT] to a 1) to 2047 bytes. When a packet is successfully stored in the receive memory,
the host can begin to read this packet. However, if there is more than one incoming packet or the packet size is too large, the receive
pointer may override the host read pointer after wrapping around the ring structure. This situation is avoided with a buffer overflow
flag,OVRFLO. When this flag is high, the receive pointer will not store any more data until the host read has cleared the memory.

9-37

9

2.4

RECEIVE OPERATION (continued)

Figure 2-4 shows the configuration of the transmit and receive buffer memory in the situation where the 2 transmit banks are selected
and explains the concept of a ring architecture of the receive buffer. The received packets are stored as they are accepted by the SSI
78Q8373. The unused buffer space in the diagram shows that the host have read packets before 'Packet P-I' hence relieving that
buffer space. Therefore the received packet' Packet P+2' can be wrapped around the end of the recei ve bufferto the start once again.
The SSI 78Q8373 also checks the incoming packet for short packet errors, alignment errors and/or CRC errors. After one successful
packet reception, the SSI 78Q8373 will perform an 8-byte re-alignment for the next packet in the receive buffer.

f-

-

Transmit Bank #1
-

-

-

-

-

-

Transmit Bank #2
f-

- - - - - -

-

t

Received Packet, P + 2
I-

-

-

-

-

-

-

-

Received Packet, P - 1
I-

-

I-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

+

-

Receive
Ring
Structure

-

I

-

Received Packet, P + 1
f-

-~

I
I
I
I
I

-

Received Packet, P
-

-

I

Unused Buffer Space
f-

--

Received Packet, P + 2

t\

(Continued at the top)

--

-

--

+

I

Figure 2-4: Transmit and Receive Buffer Organization
2.4.1 RECEIVER BUFFER DATA FORMAT

The receive packet has a 4-byte header which consists of the status of the receive packet, a reserved byte, and the 2 bytes of data
length. Regardless of the SRAM word or byte configuration, the data length is always in terms of bytes. The data packets are linked
by the internal pointers which use the data length value in the header to calculate the length of the data packet. Then the receiver
will perform an 8-byte boundary alignment and the new address is generated. Under normal operation, any packets that have errors
will be discarded. Figure 2-5 shows how accepted packets are stored in the receive buffer.
TheSSI 78Q8373 provides a means to accept erroneous packets, mainly for testing purposes. If the DLCR5<5> bit (ACPT_BADPKT)
is set to aI, short packets or packets with alignment or CRC errors will be accepted. In these circumstances, the respective bits of
the receive status registers will not be set. But the status byte to the host will still indicate that the packet has error(s).
The format of the status byte is as shown below. Note that the bit names are similar to that of the DLC register bits. However, some
of these bits are not a mirror image of the corresponding register bits and this is elaborat~d on in the Status Byte Format section.

2.5

Bit 7

Bit 6

0

0

Bit 5

PACKET
OK

Bit4

REMOTE
RESET

Bit 3

Bit2

Bit 1

SHORT
ERROR

ALIGN
ERROR

CRC
ERROR

Bit 0

OVER
FLOW

DMA OPERATION

Data transfer via Direct Memory Access is available only in the Generic Bus mode. The DMA write or DMA read operation is similar
to the I/O write or I/O read except that the handshake is done using DMREQ, DMACK and EOP signals. The DMREQ signal is
used to request for DMA transfers and the DMACK signal acts like the CS to access the BMR8 and BMR9 register pair. The WR
or RD signals accompany the DMACK to perform host write or host read operations respectively.
An EOP signal is asserted during the last data word or byte transfer to terminate the process (the DMA_EOPregister bit [DLCR 1<5>]
will be set when EOP is asserted). The SSI 78Q83T3 will not assert further DMREQs when EOP has been asserted by the host DMA.
If the DMA interrupts are enabled, the assertion of the EOP will also cause the SSI 78Q8373 to generate an interrupt to the host.

9-38

DMA OPERATION

(continued)

Single or burst DMA operations are supported for data transfer between the host and the SSI 78Q8373. In single byte or word
accesses, the SSI 78Q8373 asserts the DMREQ signal and waits for the host to respond with a DMACK acknowledge and a WR
or RD signal. Upon acknowledgment, the SSI 78Q8373 negates the DMREQ until the host completes the data transfer. The DMACK
signal is set high when the transfer is complete. To start another DMA cycle, the SS I 78Q8373 will assert the DMREQ signal again.
This continues until the host asserts the EOP signal during the last access cycle after which the SSI 78Q8373 will not make further
DMREQ requests.
In burst modes, the DMA operation can be programmed for 4,8 or 12 data transfers per DMREQ request. In these cases, the SSI
78Q8373 will negate DMREQ two cycles before the end of each burst. An EOP assertion will terminate a DMA operation anytime
during the burst data transfer.

8 Byte Alignment
Status Byte
Reserved
Length (LSB)
Length (MSB)

Packet (N-1)

DATA (N - 1)

8 Byte Alignment
Status Byte
Reserved
Length (LSB)
Packet (N)

Length (MSB)

DATA (N)

8 Byte Alignment
Status Byte
Reserved
Length (LSB)
Packet (N+ 1)

Length (MSB)

DATA (N+1)

Figure 2-5: Packet Format in Receive Buffer
9-39

I

2.5.1 DMA WRITE (TRANSMIT)
In a DMA write mode, the host performs the same function as an I/O write to load the transmit bank with one or multiple packets
of data. Typically the host has its own DMA controller which it programs to handshake with the DMA operation in the SSI 78Q8373.
The host can use a combination of I/O and DMA to write a packet into the transmit buffer.
The following depicts an example of how to perform a DMA write mode using a combination of I/O and DMA operation. First,
the host determines the size of the packet and writes the byte length into the SSI 78Q8373's transmit buffer using I/O access.
Subsequently, the host DMA is programmed with this length information. To start a DMA transfer, the host writes a 1 to the
DMA_lENA bit (BMR12) is enabled,
the SSI 78Q8373 will interrupt the host. The host will write a 0 to the DMA_RENA bit to disable the DMA read operation. It
can then initiate the next DMA transfer.

When the host interface is configured for word mode, the host DMA is programmed with the half the byte length as described in
the DMA write section. In the case of an odd packet length, the host will read an extra byte and discard it. The SSI 78Q8373 will
also manage its internal receive buffer alignment for odd size packets.

9-40

DATA LINK CONTROLLER
The Data Link Controller (DLC) implements the ISO/ANSI/lEEE 8802-3 CSMA/CD protocol. It consists of a Transmitter and a
Receiver, each with its own independent CRC logic. Automatic generation and stripping of the 64-bit preamble and the 32-bit CRC
code are provided on-chip.

IEEE PACKET FORMAT
The DLC of the SSI 78Q8373 complies with the international standards for Ethernet, ISO/ANSI/IEEE 8802-3. The IEEE 802.3
Media Access Control (MAC) frame format is shown in Figure 3-1.

-

Preamble
101010 ......... 10

7 Bytes

SFD
10101011

1 Bytes

Destination
Address

6 Bytes

Source
Address

6 Bytes

-

-

Length
I-

-

-

-

-

2 Bytes

-

Min 46 bytes. max
1500 bytes

Data
I-

-

-

-

-

Padding

As required to meet minimum
packet size

FCS

4 Bytes

Figure 3-1: IEEE 802.3 Media Access Control (MAC) Frame Format
,1.1 ELEMENTS OF THE MAC FRAME
The MAC frame size is defined to cover the Destination and Source Address fields, Length Field, Data Field, Padding (if necessary)
and Frame Check Sequence Field (CRC Code). The minimum frame size defined in the IEEE Media Access Control Protocol is
64 bytes and the maximum frame size is 1518 bytes.
Preamble Field:
This is a 7-byte field consisting of alternating l's and O's to allow synchronization of phase lock loop (PLL) circuitry in the
receiver.
Start Frame Delimiter (SFD) Field:
The SFD sequence is 10101011. This immediately follows the preamble and the double 1's signify the start of the frame.
Address Fields:
Each MAC frame consists of two address fields. The Destination Address Field specifies the destination address(es) for which
the frame is intended and the Source Address Field specify the node that is transmitting the packet. The first bit (LSB) of the
Destination Address is used to identify individual or group addressing. LSB =0 indicates an individual address and LSB =1
indicates a group address. The SSI 78Q8373 offers 3 types of group addressing called multicast group, multicast hash and
broadcast addressing. A broadcast address consists of alII's in the Destination Address field and is used to broadcast to all active
stations on the network. Please refer to Node ID and Hash Table Configuration Registers for detailed information on the other
two multicast addresses.
Length Field:
This is a 2-byte field whose value indicates the number of data bytes in the Data Field. The Length Field is transmitted with
the high order byte first. However, some protocols use this field for other purposes (Ethernet calls this a Type Field instead).
This is achieved by using values greater than the allocated values for a valid Length Field (value < 1500) to distinguish the
protocol used. The SSI 78Q8373 does not perform a consistency check on the length of the data field that follows this field.
9-41

I
•

Data and PAD Fields:
The data field may contain any data from a minimum of 46 bytes to a maximum of 1500 bytes. If necessary, the data field
is extended to meet the minimum frame size requirement. These extra bits are caUedPadding. The SSI 78Q8373 does not
perform automatic padding. Upper layer software is responsible for this task.

Frame Check Sequence Field:
A cyclic redundancy check (CRC) is used by the transmit and receive algorithms to generate a CRC value for the FCS field.
This is a 32-bit sequence that is computed as a function of the addresses, length, data (and pad) fields. The SSI 78Q8373 has
a CRC circuitry that generates the CRC for the packet to be transmitted and checks the CRC of the received packets for
transmission errors.

3.2

TRANSMITTER CIRCUITS
Circuits within the transmitter include a transmit state machine, pseudo-random number generator, preamble generator, interframe gap timer, exponential backoff generator and a time domain reflectometry counter. The CRC logic is shared by the
transmitter and the receiver. Any transmit errors will be reported via the DLCR status registers.
The CRC logic calculates the IEEE 32-bitFrame Check Sequence (FCS) for the entire data packet (from the destination address
to the end of the data field) and appends theFCS to the end of the packet. In the event of self-reception in 'accept all packets' modes
6r loop back, the CRC logic is used by the transmitter only.

3.2.1 transmit Media Access Management
The SSI 78Q8373's DLC block implements the ISO/ANSI/lEEE 8802-3 Media Access Protocol called the CSMNCD. This is
the acronym for Carrier Sense Multiple Access with Collision Detect. Abiding by this protocol requires the controller to monitor
the presence of a carrier from other nodes on the network and deferring any transmission if a carrier is 'sensed' on the network.
A collision is defined py the situation whereby two nodes transmit at nearly the same time and try to drive the network together
which results in garbled data. In the event that a collision occurs, this is detected via the collision detection mechanism. A node
that is involved in a collision will transmit a 32-bitJam Pattern to reinforce the collision such that every node on the network detects
it. It will then cease its transmission and wait a pseudo-random backoff interval before attempting to transmit the packet again.
According to the ISO/ANSI/lEEE 8802-3, there must be a 9.6 msec interval between the transmission of packets for the network
to recover. This is called the Inter-Frame Gap (lFG) and the SSI 78Q8373' s DLC utilizes the IFG timer in the transmitter to record
the interval starting from the end of the last packet on the network. The DLC will not transmit before this interval expires. If another
node happens to transmit during the first 2/3 of the IFG interval, the SSI 78Q8373 will reset its IFG counter and start again at the
end of this new transmission. However during the last 1/3 of the IFG interval, the SSI 78Q8373 will ignore any transmission on
the network that occurs during that time in accordance with the IEEE standard. This is to assure fairness and equality in accessing
the network. With two nodes transmitting at nearly the same time, a collision would occur resulting in pseudo-random backoff
intervals for each node to resolve the contention.
The SSI 78Q8373's TDR counter keeps track of the number of bits that has been transmitted. The counter maintains the count
of the actual number of bits transmitted just before a collision or loss of carrier occurs. The count can then be used to diagnose
the medium as shown.

Estimating the distance, D (m) from the transmitting node to a fault:
N = number of bits transmitted (TDR Count)
R = transfer rate, 10 Mbit/s
S =signal propagation for coaxial cable (in the region of 2 x 108 m/sec
D = (N x S)/(2 x R) meters

A pseudo-random number generator is used for collision backoffs. The range of the random num ber interval increases with each
collision with the maximum range occurring for the 10th collision through the 16th collision. Hence it is called the truncated binary
exponential backoff. The value obtained from the pseudo-random number generator is counted down every slot-time (512 bits).
When the interval expires, the SSI 78Q8373 will check the IFG timer and attempt to re-transmit.

9-42

.2 Transmit Errors
There are 4 transmit error status bits in DLCRO. These cover the loss of carrier during collision, collision on the network, 16
consecutive collisions and host write error. The loss of carrier usually indicates a fault on the network (open or shorted medium).
The 16 collisions error indic·ates that host intervention may be necessary pertaining to the next step that the SSI 78Q8373 should
take. Please refer to Buffer Memory Registers Section (BMR 11 <2:0». Host write error occurs when the host tries to write beyond
the end of the allocated transmit buffer. Interrupts can be generated for the collision, 16 collisions and host write errors.
The collision counter DLCR4<7:4> with DLCR4<7> as the most significant bit, automatically increments every time a collision
occurs. Upon the 16th collision, it will roll over to zero and set the 16COL bit (DLCRO< 1» to 1. The 16 collisions error could be
an indication of a faulty medium or an overloaded network.

.3 Encoder/Decoder
The SSI 78Q8373 includes an internal Manchester Encoder/Decoder (ENDEC) which converts the serial NRZ bit stream for
transmission to a format used on the network. This conversion is known as Manchester Encoding which uses edges at the mid-point
of a bit interval to signify a 1 or a O. A low-to-high transition at the mid-point indicates a 1 and a high-to-low transition indicates
aO.

RECEIVER CIRCUITS
Circuits within the receiver include a receive state machine, preamble and start of frame delimiter recognition, address recognition,
error detection logic, byte alignment checking, serial to parallel converter and receive FIFO. Receive errors such as short packet
error, CRC error, alignment error, and buffer overflow error are reported via the DLCR status registers and the status byte header
preceding each packet stored in the RAM.
The receive FIFO provides buffering while the Buffer Manager is servicing another resource and enables the loading of data into
the SRAM only when necessary, i.e., on the acceptance of a packet. The preamble and start of frame delimiter is stripped from the
packet before loading it into the receive buffer. The last four bytes of the packet (CRC) remain in the receive FIFO and are not
transferred to the receive buffer.
The CRC logic calculates the IEEE 32-bit Frame Check Sequence (PCS) for the entire data packet (from the destination address to
the end of the packet including the transmitted CRC) and the resultant should be a fixed constant if no errors occurred during the
transmission.

J.1 Receive Media Access Management
As a bit stream is present on the network, the PLL in the internal ENDEC of the SSI 78Q83 73 will lock -on to the stream of alternating
1's and O's (the preamble pattern). The ENDEC performs the decoding function of the Manchester encoded data on the network
for the receiver. The receiver monitors the decoded bit stream (NRZ format) for the end of the preamble pattern i.e. the start of frame
delimiter Qyte pattern which is' 10101011'. The two consecutive 1's in this pattern signifies the Start of the first bit of the first byte
of the destination address field.
The SS! 78Q8373 allows the acceptance of packets with physical or logical addressing. Physical addressing requires the exact
matching of the entire 6 bytes of destination address and the Node ID. Logical addressing comes in three forms for the SSI78Q8373:
broadcast, multicast group and multicast hash addressing. The first bit of the 48-bit destination address is a 0 if the address is a
physical address. If the address is a logical address then the first bit of destination address is a 1. Broadcast messages are messages
that are meant for all nodes on the network and the destination address of a broadcast packet consists of all l' s. A multicast group
address has the first bit of the destination address as a 1 and the receiver will only match the first 3 bytes of the incoming address
before deciding to accept or reject the packet. For multicast hash addressing, the CRC logic performs the calculation for the 48-bit
address and the least significant 6 bits are used to hash into the SSI 78Q8373' s 64 element hash table. If the hashed element has
been set to a 1 then the packet will be accepted. If the hashed element has been set to a 0, the packet will be rejected.
During initialization, appropriate bits are set in the Address Mode registers (DLCR5< 1:0» and command bits in DLCR5 for 'bad
packet' (packets with errors) acceptance and so forth. As a packet is received from the network, its destination address will be
matched following the criteria of the Address Mode and DLCR5 registers. Once the destination address matches according to that
criteria, the packet is accepted and is loaded into the receive buffer. The last 4 bytes of the received packet (32-bit CRC) are not
transferred to the receive buffer. If the destination address fails to meet the criteria, the packet is rejected and the recei ver continues
to monitor the network.

.3.2 Receive Errors
There are 5 receive status errors in DLCRl. These include the host read error, short packet error, alignment error, CRC error and
buffer overflow error. Host read error results when the host attempts to read from an empty receive buffer. RX_BUFMTY bit in
DLCR5<6> is set to 1 by the SS! 78Q8373 when the receive buffer is empty. Short packet error occurs when a packet is less than
the IEEE minimum of 60 bytes in length is received. This packet will not be accepted unless the ENA_SRTPKT bit (DLCR5<3»
9-43

I

has been activated. Packets with alignment or CRC or short packet errors are accepted only if the ACPT_BADPKT bit (DCLR5<~
is set to a 1. Alignment error indicates an incomplete byte frame at the end of a packet and CR C error indicates an error has occun
during transmission. A CRC error occurs when the received packet is checked by the CRC logic (from destination address to I
end of the packet including the appended CRC) and the resultant is not the fixed constant expected in a no-error transmission. Sh
packet error is set if the received packet is less than the minimum length of 60 bytes. Buffer overflow error signals insufficient sp~
in the receive buffer for the current packet and requires the host to read packets from the recei ve buffer to relieve more buffer spal

3.3.3 Encoder/Decoder
The internal ENDEC performs the recovery of the receive clock RXC, carrier detection and Manchester decoding of the data str~
from the network. The received data stream is transferred to the ENDEC circuit block via either the on-board twisted-pair transcei,
circuit or the AUI circuit, depending on which is active. When the ENDEC block receives a signal from the twisted-pair transceh
or the AUI circuit, it converts this carrier detection into the CRS signal for the controller. The recovered clock, RXC is achiev
through the digital phase lock loop (DPLL) in the ENDEC which tries to synchronize to the incoming 5 MHz stream. (The preamt
consists of alternating l' sand 0' s when converted to Manchester encoding produces this waveform). The data stream is then decod
to NRZ format with the recovered RXC. This is passed to the controller as the received data, RXD. During idle periods, the R~
is not active.

3.4

LOOP BACK MODES
The SSI 78Q8373 provides for 2 types of loop back testing. They are defined as follows:
i) ENDEC Loop Back

ii) Media Loop Back (Twisted-pair transceiver or AUI Port)
Loop back i is used for testing functionality of the Manchester EncoderlDecoder (ENDEC). This can be invoked by setting tI
appropriate bit in the DLCR4<1>, but is intended for diagnostic testing only, and should not be set during normal operation. TI
Media Loop Backs are basically a normal transmission with a self-addressed packet or setting the Address Modes to an "accept a
packets" mode (i.e. promiscuous mode occurs when AM = II). All of these loopbacks are illustrated in Figure 3-2.
For the ENDEC loop back, data is routed from the transmit buffer to the transmitter of the DLC, through the Manchester Encode
which loops the decoded data back to the Manchester decoder. The decoder decodes the Manchester code and passes the NR
data to the receiver of the DLC which then stores it in the receive buffer. The EDLOOP bit (DLCR4< I» is set to 0 for this loa
back mode. This permits testing of the DLC' s transmit and receive sections and the Manchester encoding and decoding section
The host software can then read and verify the received data.
For the Media loop backs, data is routed from the transmit buffer to the transmitter of the DLC through the ENDEC and the mediut
(via either the internal twisted-pair transceiver or the AUI port, depending on which interface is selected) then back to the receiv(
of the DLC. This occurs when the SSI 78Q8373 is in the 'accept all packets' mode (promiscuous) where all packets that th
transmitting node sends are accepted. Another way of achieving this effect is to send a packet with the destination address eqm
to the source address. This permits testing of the entire loop starting from the DLC to the medium and back. The host software ca
then read and verify the received data.

3.4.1 Self-Reception Criteria
In a normal operating mode, self-reception is only possible when the destination address of the transmitted packet matches th
transmitting station's Node ID (physical address match). In this case, the transmitting station will not receive its own multicas
(group or hash) or broadcast messages.

If the ENDEC Loopback mode is activated, the address recognition logic in the receiver will treat the loop back message as if it wa
coming from the medium. Thus if a match occurs (physical, multicast or broadcast), self-reception will take place.
In the 'accept all packets' mode, self-reception is guaranteed to happen for any transmission.

9-44

8M
I

TRANSMIT
MANAGER

I

RECEIVER
MANAGER

OLC

t----

ENOEC

ITRANSMITTER I

I

I f--4- I

~

I

ENCODER

I ..
CD

RECEIVER

I

------- I

DECODER

TWISTED
PAIR
TRANSCEIVER

I

~

"-'-

1(§
i--"

COAX
TRANSCEIVER

r4-

r---1
i--"

SSI78Q8370
COAX
CABLE

CD ENOEC Loopback
(§
@

Media (TP connection) Loopback
Media (AUI connection) Loopback

Figure 3-2: 78Q8373 Loop Back Modes

I
9-45

4

POWER MANAGEMENT
SSI 78Q8373 provides 3 modes of intelligent power management:
1) Auto power down mode through BMR11<6>.
This mode is the default at reset/power up. The clocks are active only when they are needed. This auto power down mode Cl
be disabled by programming a 1 which can be useful for chip debugging and maximum power consumption estimation.
2) Standby mode through DLCR7 or through CCR1<2>.
SetDLCR7<5> = 0 to enter this mode, or, if the SSI 78Q8373 is in PCMCIA mode, set CCR 1<2> = I. This de-gates the oscillat~
clock without shutting it off. All the internal clocks are not active with the oscillator still running. Using full static design, tl
SSI 78Q8373 remembers all ofthe register settings, memory pointer values and the status of the state machines prior to enterir
standby mode. It can resume normal operation again when this bit is disabled.
3) Oscillator shut off through BMRII<7>.
WARNING: This bit may only be set if using the internal oscillator. Setting this bit while using an external canned oscillat(
can damage the chip.
Due to the above danger, this bit can only be set (hardware protected) after the standby mode has been entered. Thus, accident
write can be prevented. The users need to be aware that the oscillator needs some time to stabilize. This startup time is typical]
2 msec for SSI 78Q8373.
The following programming sequence is recommended for entering this mode:
i)

Check that SSI 78Q8373 is idle (i.e. not in the middle of an operation).

ii)

Set DLCR7 to '0' to enter standby mode.

iii)

Set BMRII <7> to '1' to shut off the internal oscillator.
(SSI 78Q8373 is now in its lowest power consumption configuration).

The 'wake up' sequence is as follows:
i)

Set BMRII <7> to '0' to tum on the internal oscillator.

ii)

Allow some time for the internal oscillator to stabilize. This is typically 2 m~cc.

iii)

Set DLCR7 to '1' to go back to the normal mode.

9-46

CONTROL AND STATUS REGISTERS
The registers in the SSI 78Q8373 can be divided into six groups: 1) Data Link Control Registers (DLCRO-7); 2) Node ID registers
(IDR8-13); 3) Time Domain Reflectometry Registers (TDR14-15); 4) Hash Table Registers (HTR8-I5); 5) Buffer Memory
Registers (BMR8-15); 6) PCMCIA Registers (CCRO-I).
The Data Link Control Registers contain the transmit and receive status information, interrupt enable, SSI 78Q8373 setup and
software reset bit (DLCR6<7». They are accessed through direct register addresses xxxOH through xxx7H. The Ethernet Node
ID is stored in IDR(8-15). The TDR(14-I5) registers are used to provide the count value of the number of bits transmitted for each
packet. This value can indicate whether a packet has completed its transmission or has encountered a collision. Both the Node 10
and the Time Domain Reflectometry Registers can be accessed through direct register addresses xxx8H through xxxFH.
The Hash Table Registers (mR8-IS) provides a means for filtering incoming multicast packets. Any packet that does not match
the hash table coding will be rejected. The HTR8-I5 can be accessed by the bank-switching addresses RBNKI,O (DLCR7<3:2».
The tasks performed by the Buffer Memory Registers (BMR8-I5) include transferring of packets between the host and SSI 78Q8373
(via BMR8-9), collision control, DMA operations and activation of the transmit operation including control of the internallOBaseT
transceiver.
The final group of the registers belongs to the PCMCIA Registers (CCRO-I), which are used for controls specific to operation in
a PCMCIA card environment.
A summary table of the registers and their addresses are tabulated below:
CCRA

RBNK1 0

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

XX
XX
XX
XX
XX
XX
XX
XX

1
1

XX
XX

00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
11

HA3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

HA2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

HA1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

HAO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

ADDRESS
DLCRO
DLCR1
DLCR2
DLCR3
DLCR4
DLCR5
DLCR6
DLCR?
IDR8
IDR9
IDR10
IDR11
IDR12
IDR13
TDR14
TDR15
HTR8
HTR9
HTR10
HTR11
HTR12
HTR13
HTR14
HTR15
BMR8
BMR9
BMR10
BMR11
BMR12
BMR13
BMR14
BMR15

X

X

X

X

-

0
0

0
0

0
0

0
1

CCRO
CCR1

DESCRIPTION
Transmit ~tatus
Receive Status
Transmit Interruet Mask
Receive Interrupt Mask
Transmit Mode
Receive Mode
Configuration 0
Confiquration 1
NODE 10 0
NODE 10 1
NODE 102
NODE 103
NODE ID 4
NODE 105
TOR 0 (LS8)
TOR 1 lMSBJ select 3V
Hash Table 0
Hash Table 1
Hash Table 2
Hash Table 3
Hash Tab-le-4
Hash Table 5
Hash Table 6Hash Table?
Buffer Memory 1/0 Port
Buffer Memory 1/0 Port (word mode)
Transmit Start + Packet Count
16 Collisions Control
DMA Enable
DMA Burst & Transceiver Mode
Receiver Filter & Interrupt Enable
Transceiver Status
RESERVED
PCMCIA Configuration Option
PCMCIA Card Config. & Status

Note: All registers are both word and byte accessible. In word mode, register bytes are paired up. In the case of odd-byte packet,
the odd-address byte becomes the high byte of the word. In byte mode, only BMR8 will be used. lOR and HTR can only be accessed
when ENADLC (DLCR6<7» is a '1.' The CCRO and CCR I registers are visible only if the chip is configured in PCMCIA mode.
9-47

I

5

CONTROL AND STATUS REGISTERS (continued)
A register bit-map is also included for the Data Link Controller Registers, Buffer Manager Registers, and PCMCIA registers.
Also shown are the default values for each register. Shaded bits are non-writeable.

Rx Interrupt
Enable
DLCR3

9-48

Bit 2

Bit 1

COL

16COL

BitO

LEGEND DESCRIPTION
The legend (column L in the register tables) used to describe register initial values, readability and writeability are denoted by the
following abbreviations:
R:
W:
C:
H:
0/1:

READABLE
WRITABLE
CLEARABLE: Writing a '1' clears this bit; writing a '0' has no effect
CONDITIONALLY WRITABLE: The default values can only be changed depending on other conditions
Power-up!Reset Default value

DATA LINK CONTROLLER REGISTERS
There are 8 Data Link Controller registers that will provide the status and control signals between the SSI 78Q8373 and host. In
the following sections, each register bit will be explained.
~.1

DLCRO· Transmit Status Register
This register provides the transmit status to the host. These status bits can also produce interrupt" if DLCR2 interrupt enable signals
are set (see DLCR2 for details). The status bits can be cleared by writing a '1' to the respective bit but writing a '0' has no effect
on it. Note that more than one status bit can produce a common interrupt signal. Hence itis advisable forthe host to check this register
to find out how many of the status bits could have caused the genemtion of the interrupt signal.

BIT
7

SYMBOL
TXOK

L
R,C,O

6

NET_BSY

R,O

5

SELF_RX

R,C,O

4

TX_ERR

R,O

3

JABBER

R,O

2

COL

R,C,O

1

16COL

R,C,O

0

HWR_ERR

R,C,O

DESCRIPTION
TRANSMIT OK: When the packet is transmitted through the medium without any errors
or skipped due to excessive collisions, this bit is set high. If DLCR2<7> is enabled, then
the bit can trigger an interrupt to the host.
NET BUSY: If this bit is read as 1, it indicates that the network is busy at the receiver.
This bit reflects the status of the CRS signal.
SELF RECEPTION: The bit is used to indicate that self-reception has occurred. Writing
a 1 or power reset will clear this bit. If DLCR2<5> is enabled, it can trigger an interrupt
to the host.
TRANSMIT ERROR: When read as a 1, this bit indicates a possible COllision on the
network or a loss of carrier during transmission. Automatically cleared on the next
transmission. Writing a '1' or a '0' has no effect.
JABBER: When high, it indicates that excessive transmit length is detected by the
internal jabber timer. This is a serious error condition which only occurs when the chip
malfunctions. Can generate interrupts if enabled by the corresponding interrupt enable
bit in DLCR2. This jabber error can only be cleared by hardware or software reset
through DLCR6<7>.
COLLISION: This bit is set high when a collision occurs on the data packet during
transmission. The 7808373 performs up to 16 re-transmissions. If DLCR2<2> is
enabled, it can trigger an interrupt to the host. The number of collisions is stored in
DLCR4<7:4>.
16 COLLISIONS: If a data packet has suffered 16 unsuccessful transmission then this
bit will set high. Generates an interrupt to the host if DLCR2<1> is enabled.
HOST WRITE ERROR: When the host attempts to write data to the transmit buffer
memory and did not get the response from 7808373 after 2.4 msec, this flag is set. This
is to indicate that the transmit buffer is full. If DLCR2<0> is enabled, it can trigger an
interrupt to the host.

9-49

I

5.2.2 DLCR1 • Receive Status Register
This register provides the receive status to the host. These status bits can also produce interrupts if DLCR3 interrupt enable sign<
are set (see DLCR3 for details). The status bits can be cleared by writing a' l' to the respective bit. Writing a '0' has no effect I
the register bit. Note that more than one status bits can produce a common interrupt signal. Therefore it is best for the host to chel
this register to find out how many of the status bits could have caused the generation of the interrupt signal.
In this register, DLCR1<3:0> are status bits for the current received packet. If any of these bits are set then the packet willi
discarded. However, 'bad packets' can be accepted by the SSI 78Q8373 under the following settings:
(1). DLCR5<5>, ACPT_BADPKT set to high allows the acceptance of short packets and packets with alignment or CRC err(]
(2). DLCR5<3>, ENA_SRTPKT set to high allows the acceptance of packets with length between 6 bytes and 2047 bytes.

L

BIT
7

SYMBOL
PKT_RDY

R,C,O

6

HRD_ERR

R,C,O

5

DMA_EOP

R,O

4

RMTRST

R,C,O

3

SRT_ERR

R,C,O

2

ALG_ERR

R,C,O

1

CRC_ERR

R,C,O

0

OVRFLO

R,C,O

DESCRIPTION
PACKET READY: When a data packet is successfully loaded into the buffer memory,
this bit is set. Can generate an interrupt if DLCR3<7> is enabled.
HOST READ ERROR: If the receive buffer is empty and the host has waited for the
response from 78Q8373 for more than 2.4 msec during host read then this bit is set. Can
generate an interrupt if DLCR3<6> is set.
DMA END OF PROCESS: When a DMA process is over, the host will assert a high to
the EOP pin to indicate the end of process. Can generate an interrupt if DLCR3<5> is
set. To clear this bit, a value of OOH must be written into BMR12. Writing either a '1' or
'0' has no effect.
REMOTE RESET PACKET RECEIVED: This bit is set if a packet received contains the
pattern 0900H in its Type Field and ENA_RMTRST (DLCR5<2» is set to a 1. Can
generate an interrupt if enabled by DLCR3<4>. The value on this bit is mirrored onto the
pin RRST (pin 96).
SHORT PACKET ERROR: This bit is set when the received packet is less than 60 bytes
(excluding preamble and CRC). 60 bytes is the IEEE minimum frame size. Can
generate an interrupt if enabled by DLCR3<3>.
ALIGNMENT ERROR: Set when the receive packet has 1 to 7 extra bits at the end of
the packet. This may be due to collision or faulty transceiver. Can generate an interrupt
if enabled by DLCR3<2>.
CRC ERROR: Set when the packet has CRC errors indicating that the packet is
corrupted. Can generate an interrupt if enabled by DLCR3<1 >.
RECEIVE BUFFER OVERFLOW: Set when the receive buffer is full. Can generate an
interrupt if enabled by DLCR3<0>.

5.2.3 DLCR2· Transmit Interrupt Enable Register
This register contains the bits to enable the status bits in DLCRO to generate interrupts to the host.
BIT
7
6
5
4
3
2
1
0

SYMBOL
TXOK
INT ENABLE

0
SELF_RECP
INT ENABLE

0
JABBER
INT ENABLE
COLLISION
INT ENABLE
16COL
INT ENABLE
HWR_ERR
INT ENABLE

L

N,O
R,W,O

DESCRIPTION
TXOK INTERRUPT ENABLE: When set high, it enables transmit OK signal, TXOK to
generate an interrupt.
-RESERVED BIT.
SELF RECEPTION INTERRUPT ENABLE: Enables the transmit receive in loop back
to produce an interrupt.
-_._..RESERVED BIT.
JABBER INTERRUPT ENABLE: When high, enables JABBER to generate an interrupt.

R,W,O

COLLISION INTERRUPT ENABLE: When high, enables COL to generate an interrupt.

R,W,O

16 COLLISION INTERRUPT ENABLE: When high, enables 16COL to generate an
interrupt.
HWR_ERR INTERRUPT ENABLE: When high, enables host write error signal,
HWR_ERR to produce an interrupt.

R,W,O
N,O
R,W,O

R,W,O

9-50

:.4

DLCR3· Receive Interrupt Enable Reg ister
This register contains the bits to enable the status bits in DLCR1 to generate interrupts to the host.

31T
7

6

5
4
3
2
1

°

SYMBOL
PKT_RDY
INT ENABLE
HRD_ERR
INT ENABLE
DMA_EOP
INT ENABLE
RMTRST
INT ENABLE
SRT_ERR
INT ENABLE
ALG_ERR
INT ENABLE
CRC_ERR
INT ENABLE
OVRFLO
INT ENABLE

L
R,W,O
R,W,O
R,W,O
R,W,O
R,W,O
R,W,O
R,W,O
R,W,O

DESCRIPTION
PKT_RDY INTERRUPT ENABLE: When this bit is set high, it will enable PKT_RDY
(Packet Ready signal) to generate an interrupt.
HRD_ERR INTERRUPT ENABLE: When high, enables HRD_ERR (Host Read Error)
to generate an interrupt.
DMA_EOP INTERRUPT ENABLE: When high, enables the DMA_EOP to generate an
interrupt.
RMTRST INTERRUPT ENABLE: When high, allows the- RMTRST (Remote Reset
Packet Received) to generate an interrupt.
SRT_ERR INTERRUPT ENABLE: When high, enables SRT_ERR (Received Short
Packet) to generate an interrupt.
ALG_ERR INTERRUPT ENABLE: When high, enables ALG_ERR (Alignment Error) to
generate an interrupt.
CRC_ERR INTERRUPT ENABLE: When high, enables--CRC_ERR to generate an
interrupt.
OVRFLO INTERRUPT ENABLE: When high, enables OVRFLO (Receive Buffer Over
flow) flag to generate an interrupt.

2.5 DLCR4· Transmit Mode Register
This register contains the collision count value (up to 16 collisions). SSI 78Q8373 will attempt to fe-transmit the current packet up
to 16 times. After which, depending on the values setting in BMR 11<2:0>, the host can either skip the current packet and continue
to transmit remaining packets in the transmit buffer or re-transmit the current packet again.

BIT
7-4

SYMBOL
COL3-0

L
R,O

3

NO_BACK

R,W,O

2
1

NOT_CB
EDLOOP

R,W,1
R,W,1

°

DSC

R,W,O

DESCRIPTION
COLLISION COUNT: These 4 bits store the collision counter value. Bit 3 is the most
significant bit of the count.
NO BACKOFF ENABLE: When set to 1, it will disable the binary exponential backoff
circuitry.
NOT_CONTROL BIT: The inverse of this bit is available for general use on th CB pin.
ENDEC LOOP BACK: Active low. This bit enables the-loop back function of the
78Q8370-ENDEC. Loop back is active when this bit is set to '0'.
DISREGARD CARRIER: Program this bit to zero for normal network operation. When
set to high, the transmitter will not defer to traffic on the network.

I
9-51

5.2.6 DLCR5 - Receive Mode Register
This register controls the way that SSI 78Q8373 receives a packet DLCR5<5> set high allows SSI 78Q8373 to accept packets th
contains alignment or CRC errors. DLCR5<3> set high allows SSI 78Q8373 to accept packets with packet length that is betwet:
6 bytes and 2047 bytes (excluding preamble and CRC). Allowing the acceptance of a 6-byte packet is usually a diagnostic mod
The Receive Buffer Empty (DLCR5<6» informs the host when there is no more data in the receive buffer memory.
BIT
7
6

5
4

SYMBOL
RESERVED
RX_BUFMTY

L
0
R,1

ACPT_BADP R,W,O
KT
ADD_SIZE
R,W,O

3

ENA_SRTPK
T

R,W,O

2

ENA_RMTR
ST

R,W,O

AM1,0

R,W,O,1

1,0

DESCRIPTION
RESERVED BIT.
RECEIVE BUFFER EMPTY: When the receive bufffer has no data for the host, this is
set to a high by 7808373.
ACCEPT BAD PACKET: If this bit is set high, short packets and packets with alignment
and/or CRC errors will be accepted. Otherwise, errorneous packets are rejected.
ADDRESS SIZE: When serhigh, only the first 40 bits of the destination address are
compared to the Node ID (normal mode requires the comparison of all 48 bits).
ENABLE SHORT PACKET: When set high, allows short packets (packet length
between 6 and 2047 bytes minus the preamble and CRC) to be stored in the receive
buffer memory. When this bit is set low, any packets with less than 60 bytes in length
will be rejected.
ENABLE REMOTE RESET: When set to a 1, enables othe-r nodes on the network to
reset external peripheral(s) connected to this node. If set to a 0, a received packet with
the 0900h pattern in the Type Field will not succeed in resetting these peripherals
ADDRESSING MODE BITS: These two bits control the addre-ss filtering of the incoming
packets.
AM1

AMO

0
0

0
1

1

0

1

1

9-52

ADDRESSES ACCEPTANCE
MODES
REJECT ALL PACKETS
NODE ID, BROADCAST and
MULTICAST GROUP
NODEID,BROADCASTand---MULTICAST HASH TABLE
ACCEPT ALL PACKETS .-------

,7 DLCR5· Configuration Register 0

liT
7

SYMBOL
ENADLC

L
R,W,1

6

RAMSP

R,W,O

5

HBYTE

R,W1

4

RBYTE

R,H,1

DESCRIPTION
ENABLE DATA LINK CONTROLLER: Active low, Enables the receiver and transmitter
of 7808373. Setting this bit to high will reset all the state machines to their idle states
and allows access to Node 10 and Hash Table registers (depending on DLCR7<3:2>
settings).
RAM SPEED: When set to 1, selects 100 nsec cycle SRAM: Otherwise, the SRAM is
of 150 nsec cycle.
HOST BYTE/WORD SELECT: If set high, host system bus will-operate in byte mode.
If set to 0, it will operate in word mode.
RAM BYTE: When set high, the RAM databus will operate in b-yte mode, otherwise it will
be word mode. In PCMCIA mode, this bit will be internally hard set to 1. This is because
PCMCIA pinout makes use of the higher RAM databus. The following table is valid OOLY
for Generic Bus mode:
HBYTE
0
0
1
1

3,2

TS1,O

R,W,O,1

00
01
10
11
BS1,O

R,W,O,1

BUFFER
HOST
-word_._-.
word
word
byte
DO NOT USE
byte
byte

TRANSMIT BUFFER SIZE: Sets configuration of transmit buffer.
TS1,O

1,0

RAM BUS
0
1
0
1

TX BANKS SIZE OF
TX BANK
1
2 KB
2 KB
2
4 KB
2
2
8 KB

TOTAL TX
BUFFER
2 KB
4 KB
8 KB
16 KB

BUFFER MEMORY SIZE: Sets configuration of total Buffer Size.
BS1
0
0
1
1

BSO
0
1
0
1

SRAM SIZE
8 KB
--16 KB
32 KB
--64 KB

I
9-53

5.2.8 DLeR7 - Configuration Register 1
BIT
7,6
5

SYMBOL
CTM1,0
NOT_STBY

L
R,H,OO
R,W,1

4

RDYSEL

R,-

3,2

RBNK1,0

R,W,O,O

DESCRIPTION
CONTROLLER TEST MODES: Write 00 for normal operation.
NOT STANDBY (POWER DOWN): Active low. The power down mode is for energy
saving. If set high, it enables power to the chip for all functions.
READY SELECT: Reflects the real time image of the RDYSEL pin (pin 94). If RDYSEL
pin is high, READY interface with the host is active high. Otherwise it is active low.
REGISTER BANK SELECT: To select the upper 8 registers as shown below:
RBNK1
0
0
1
1

5.3

1

EOPSEL

R,W,O

0

INTLMOT

R,W,O

RBNKO
0
1
0
1

REGISTERS
DLCRO-7 + IDR8-13 + TDR14,15
DLCRO-7 + HTR8-15
DLCRO-7 + BMR8-15
RESERVED

END OF PROCESS PIN SIGNAL POLARITY: When high, EOP pin is active high. When
low, EIP pin is active low.
INTEL or MOTOROLA MODE: System must be in word mode. This applies to the nontransmitted buffer header and the packet data. When this bit is low (INTEL MOOE), the
least significant byte will occupy the even address. Otherwise, the most significant bytes
will occupy the even address (MOTOROLA MOOE).

NODE 10 REGISTERS

5.3.1 lOR 8:15· Node 10 Registers
lOR
8
9
10
11
12
13

BIT7
107
1015
1023
1031
1039
1047

BIT6
106
1014
1022
1030
1038
1046

BITS
105
1013
1021
1029
1037
1045

BIT4
104
1012
1020
1028
1036
1044

BIT3
103
1011
1019
1027
1035
1043

BIT2
102
1010
1018
1026
1034
1042

BIT1
101
109
1017
1025
1033
1041

BITO
100
108
1016
1024
1032
1040

The NodeID registers (IDR8-13) are located in register bank '00' (DLCR7<3:2> = 00) at address xxx8H through xxxDH. Th
unique Ethernet address is written into these registers during the initialization of the node with the first byte of the Ethernet addre~
atIDR8. The IDRregisters are readable and writeable only when ENAOLC = 1 (DLCR6<7». When ENAOLC =0, normal networ
operations resume with the DLC controller.
During the reception of a packet, the destination address of the packet is matched with the Node 10 in the lOR registers. Dependin
on the Address Mode (DLCRS< 1:0» selected for the node, either all or some of the six bytes of the incoming destination addres
are compared to the Node ID. If they match then the packet is accepted. Any mismatch in the addresses would result in the rejectio
of the packet.
5.4

TIME DOMAIN REFLECTOMETRY REGISTERS

5.4.1 TOR 14,15 - Time Domain Reflectrometry (TOR) Registers
TOR
14
15

BIT7
I BIT6
T07
I TD6
SELECT3V

BITS
T05
T013

BIT4
T04
T012

9-54

BIT3
T03
T011

BIT2
T02
T010

BIT1
T01
T09

BITO
TOO
T08

The Time Domain Reflectometry (TDR 14-15) registers provide a means of locating a fault on the network. The TDR registers are
located in the same register bank as the IDR8-13 but at address xxxEH through xxxFH. This 14-bit diagnostic counter keeps a count
of the number of bits that has been transmitted during transmission of a packet starting from the preamble and including the CRC
bits. TDR14 is the least significant byte and TDR15 is the most significant byte of the counter. Fourteen bits are sufficient for the
packet transmission of an IEEE compliant LAN. The remaining 2 bits (TDRI5<7:6» are used to select 3-volt operation of the
78Q8373.
liT
',6

SYMBOL
SELECT3V

L
R,W,O

DESCRIPTION
SELECT 3V. Programming these bits to 11 will select the 3-volt operating mode. All
other combinations will select the default 5-volt operating mode.

The TOR count is cleared on the transmission ofthe next packet. A short or open on the network would cause reflections of the signal
on the network that can be detected as a loss of carrier sense or a false collision respectively. In the event that a fault occurs on the
network, the error messages in DLCR0<2> or DLCRO<4> will be able to indicate the type of fault. The TDR count can then be used
to estimate the distance from the node to the fault location along the network cable.
HASH TABLE REGISTERS
.1 HTR 8:15 - Hash Table Registers
HTR
8
9
10
11
12
13
14
15

BIT7
HT7
HT15
HT23
HT31
HT39
HT47
HT55
HT63

BIT6
HT6
HT14
HT22
HT30
HT38
HT46
HT54
HT62

BIT5
HT5
HT13
HT21
HT29
HT37
HT45
HT53
HT61

BIT4
HT4
HT12
HT20
HT28
HT36
HT44
HT52
HT60

BIT3
HT3
HT11
HT19
HT27
HT35
HT43
HT51
HT59

BIT2
HT2
HT10
HT18
HT26
HT34
HT42
\HT50
HT58

BIT1
HT1
HT9
HT17
HT25
HT33
HT41
HT49
HT57

BITO
HTO
HT8
HT16
HT24
HT32
HT40
HT48
HT56

The Hash Table Registers (HTR8-1S) are located in register bank '01' (DLCR7<3:2> =01) at address xxx8H through xxxFH. The
Hash Table allows group addressing by filtering multicast addressed packets on the network. The 64-element table provides the host
to select which of the the node should belong to and sets the appropriate groups to a 1. If the host does not want to belong to any
groups, the entire table will be set to O.
As a packet is received, the bit stream goes through the CRC block. If the incoming address is a multicast address (least significant
bit of the destination address is a 1) then the following occurs. After the last bit of the 48-bit destination address has passed through
the CRC block, the least significant 6 bits of the CRC at that point is used to index one of the 64 elements of the Hash Table. If that
Hash Table element is set to a 1 then the packet is accepted. If it is set to a 0 the packet is rejected.
The Hash Table is readable and writeable when ENADLC = 1 and the DLCR7<3:2> =01. Selecting the Address Mode to include
multicast hash addressing would enable this filtering. For instance, AM = 10 (DLCRS< 1:0> ) allows for physical, broadcast
and multicast hash addressing but AM = 01 does not i.e. the hash filter would not be utilized in these situations. (AM
= 01 only allows for physical, broadcast and multicast group addressing).
;)

BUFFER MEMORY REGISTERS
There are 8 registers for buffer memory interface, 16 collision control and DMA control in this set of register bank. Each bit is
explained in the following sections.

6.1 BMR8, 9 - Buffer Memory Port
Reading or writing between the host and SSI 78Q8373 buffer memory is done via these two registers. The location for the buffer
memory is dependent on the address unitof SSI 78Q8373. When SSI 78Q8373 is configured as byte mode, only BMR8 is used. Both
BMR8 and BMR9 are used when the SSI 78Q8373 is set to word mode configuration.
BIT
7-0

SYMBOL
BMR8<7:0>
BMR9<7:0>

L
R,W,_

DESCRIPTION
PACKET RECEIVE and TRANSMIT REGISTERS for the host and 7808360.

9-55

I

5.6.2 BMR10 - Transmit Packet Counter
This register consists the 1RANSMIT START BIT (TXST) and the total packet count for the SSI78Q8373 to transmit. The pac
count is the number of packets that the host wants to transmit. To activate transmission, the packet count must be written the sa
time that the TXST bit is set to a 1. The user should not write into this register until the packet count has reached zero.

BIT
7

SYMBOL
TXST

l
R,W,O

6-0

PACKET
CNT<6:0>

R,W,O

DESCRIPTION
TRANSMIT START BIT: When the packet(s) in the transmit buffer is ready for transfer
to the network, this bit is set to 1 in order to activate the transmit operation. Always read
as a O.
TRANSMIT PACKET COUNT: The total number of packets to be transmitted to the
network. Each time a packet is successfully transmitted , the packet count is decremented.
The host can read this register to check how many packets have not been transmitted.

5.6.3 BMR11 -16 Collision Control
The setting of this register determines the actions of the controller to be taken after 16 consecutive attempts to transmit a pack
There are four modes (controlled by HALT, RESTART and SKIP bits in the register) to be selected:

(1) automatic re-transmission of colliding packet
(2) automatic skip of the colliding packet after 16 attempts
(3) Halt for host intervention and retry transmission of colliding packet
(4) Halt for host intervention and discontinue transmission of colliding packet.
BIT
7

6
5-3
2
1
0

SYMBOL
OSC_OFF

l
R,H,O

AUTOPD

R,W,O

RESERVED
HALT
RESTART
SKIP

R,W,O

DESCRIPTION
OSCILLATOR SHUTOFF: When enabled ('1 '), this bit shuts off the internal oscillator.
Setting this bit while using an external canned oscillator can damage the chip. For this
reason, this bit can only be set after the standby mode is entered (by setting
DLCR7 <2> = '1 ')
AUTO POWER: Upon power-up/reset, the chip is in automatic power management
mode. This mode can be disabled by writing a '1' to this bi!.
RESERVED BIT.
16 COLLISION CONTROL: These three bits control the action to be taken by 78Q8373
in the event that 16 collisions occur in the transmission of a packet. Host intervention
is possible as shown below.
HALT
1

RE-START
X

SKIP
1

1

X

0

0

X

X

9-56

DESCRIPTION OF ACTION TAKEN
Do not halt. Skip colliding packet and
continue transmitting.
Do not halt. Retry -transmission of colliding
packet.
Halt and await instruction from host for
BMR11<1 :0>. 11' : results in colliding packet
skipped and transmission resumed.10':
results in colliding packet re-transmitted.

.4 BMR12· DMA Enable
The DMA RENA and DMA TENA activates the DMA operation as follows:
~IT

L

r-2
1

SYMBOL
RESERVED
DMA_RENA

R,W,O

0

DMA_TENA

R,W,O

-

DESCRIPTION
RESERVED BIT.
RECEIVE READ DMA ENABLE: When enabled (active high), it activates receive read
DMA from the host.
TRANSMIT WRITE DMA ENABLE: When enabled (active high), it activates transmit
write DMA from the host to ICE's buffer memory.

;.5 BMR13· DMA Burst & Transceiver Mode Register
31T
7

SYMBOL
APOL

L
R,W,O

6

RTH

R,W,O

5

ENLI

R,W,O

4

PORT_SEL

R,W,O

3

ASEL

R,W,O

2

DMT

R,W,O

DMAB1,0

R,W,O

1,0

DESCRIPTION
AUTO POLARITY: When set to 0, it enables the automatic polarity correction of the
received data. The reverse polarity is identified from either the start of idle signal or link
pulses.
REDUCED THRESHOLD: When set high, twisted pair receive threshold is reduced by
3 dB (for longer than the recommended 100 meters cable).
ENABLE LINK INTEGRITY: When set low, both transmit and receive link test functions
are enabled. When high, no link test is performed and the link status is assumed to be
up and twisted pair port is selected if auto select mode is enabled. When this bit is
enabled, the transmit link pulses function is always active regardless fo the status of the
link.
PORT SELECT: This bit manually selects between Twisted Pair (when 0) or AUI (when
1) and is only applicable when ASEL bit (BMR13<3» is high (disabled).
AUTO PORT SELECT: When set to 0, automatic port selection mode is in effect. The
selection is based on the state of link integrity status. Twisted pair port is selected or a
good link and AUI port is selected for a link down condition. When set to 1, manual port
selection is in effect through POrT SEL bit (BMR13<4».
DMA DMREO DROP TIME: When set low, DMREO drops at the next-to-Iast transfer of
DMA burst (same with 7808360). When set high, DMREO drops at the last transfer of
the burst.
DMA BURST: This two bits select the burst length for DMA operation. The burst length
transfer can either be byte mode or word mode depending on the system bus setting
(SYSBUS in DLCR6<5».
DMAB1
0
0
1
1

DMABO
0
1
0
1

BURST LENGTH

1

----

------ -

4

-----

------

-~---

8
12

I
9-57

5.6.6 BMR14· Receive Filter & Interrupt Enable Register

(1)

BIT
7
6

l
SYMBOL
RESERVED
INT ENABLE R,W,O

5-3
2

RESERVED
SKP_RX

R,W,O

1

INT ENABLE

R,W,O

°

RXF

R,W,1

-

DESCRIPTION
RESERVED BIT.
LINK DOWN INTERRUPT ENABLE: When high, enables LD (BMR15<6» to generate
an interrupt. Since LD cannot be cleared, the interrupt can be deactivated by clearing this
enable bit.
RESERVED BIT.
SKIP RECEIVE PACKET: If the host is reading the received packets in the buffer and
decides to skip the current packet then this bit is set to high. The 7808373 controller will
perform a hardware skip on the internal pointer within 200 ns to the next packet start
address if there is another packet in the buffer.
SOE INTERRUPT ENABLE: When high, enables SOE (BMR15<1» to generate an
interrupt.
RECEIVE FILTER: When set to 1, disables the reception of own transmitted packet in
the ACCEPT ALL PACKETS mode. When set to 0, enables the reception of own
transmitted packet in the ACCEPT ALL PACKETS mode. (1)

Power up value for this bit is a '1' for SSI 78Q8373 and '0' for SSI 7808360. This may be used by the software driver I
differentiate between the two chips.

5.6.7 BMR15· Transceiver Status Register
BIT
7
6

SYMBOL
RESERVED
LD

l
R,O

5

OWCOL

R,C,O

4

3

RESERVED
RPI

R,O

2
1

RESERVED
SQE

R,C,O

°

RESERVED

-

DESCRIPTION
RESERVED BIT.
LINK DOWN: When high, it indicates that the twisted pair port is in link down condition.
Can generate an interrupt if enabled by BMR14<6>. The chip powers up in link up
condition. When ENLI (BMR13<5» is high (disabled), this bit is forced to a '0' (link up
condition) .
OUT OF WINDOW COLLISION: Indicates that a collision-ocCurred after the slot time
(51.2 J.IS). Transmissions terminated and rescheduled as in normal collision. Writing a
'1' will clear this bit. For software compatibility with the 7808360, writing a '1' to the COL
bit (DLCRO<2» will also clear this bit.
---_.RESERVED BIT.
REVERSE POLARITY INDICATION: When high, it indicates that inverted data is being
received over the twisted pair wire due to wiring error. This bit is only applicable when
APOL (BMR13<2» is low (enabled). When APOL is high (disables) this bit can never
be set.
--RESERVED BIT.
SIGNAL QUALITY ERROR: When high, indicates detection of SOE signal at the end of
a transmission. This bit applies to both the AUI and TP ports. Can generate interrupt if
enabled by BMR14<1>. Writing a '1' clears this bit.
------RESERVED BIT.
--~----

9-58

PCMCIA REGISTERS
There are 2 registers for the PCMCIA interface. Each bit is explained in the following sections .
.1 CCRO· Configuration Option Register
~IT

7

SYMBOL
SRESET

L
R,W,O

6

LevlREO

R,W,O

5:0

CI(5:0)

R,W,O

DESCRIPTION
SYSTEM RESET: Setting this bit high is equivalent to assertion of hardware reset
(except that this bit is not cleared). This bit is also reflected at the XRST pin to reset the
rest of the devices on the card.
LEVEL MODE INTERRUPT REOUEST: When high, levefmode interrupt is selected.
When low, pulse mode interrupt is selected.
CONFIGURATION INDEX: This field is written with the index number of the entry in the
Card's Configuration Table that corresponds to the configuration which the system
chooses forthe card. When CI(5:0) is 0, the chip does not respond to any I/O cycle, but
will use the memory cycle.

'.2 CCR1 • Card Configuration and Status Register
SYMBOL
NI
NI
IOis18

L
R,O
R,O
R,W,O

2

RESERVED
Audio
PwrDwn

R,O
R,W,O
R,W,O

1

Intr

R,O

0

RESERVED

R,O

31T
7
6
5

4
3

DESCRIPTION
NOT IMPLEMENTED
NOT IMPLEMENTED
1/0 is 8 bit: This bit set high indicates to the host that the system is only capable of 8-bit
transfer on its data bus. Since the 7808373 can support 16-bit transfer, the default value
of this bit is '0.' This bit does not affect the host byte/word mode setting of the 8373 which
is set by HBYTE (DLCR6<5> bit).
---RESERVED.
Audio Enable: This bit set to one will enable signals from SPKRIN to SPKR.
Power Down:This bit has the same function asthe NOT_STBY bit (DLCR7<5» but with
different polarity. Thechipwillbe powered down if either this bit issetto '1' or NOT_STBY
bit is set to '0.' When configured for PCMCIA interface mode and power down is
activated, the XPD pin will indicate it by going low.
Interrupt Request Status: This bit represents the internal state of the interrupt request.
This signal remains true (high) until the condition which caused the interrupt request has
been serviced.
RESERVED.

I
9-59

6

78Q8373 & HOST INTERFACE CONFIGURATION

6.1

PCMCIA INTRODUCTION
PCMCIA is an acronym for Personal Computer Memory Card International Association. Its goal is to promote interchangeabili
of PC Cards among a variety of computer and other electronic products.
PC Cards are approximately 54 by 85 millimeters, but differ in thickness. Type 1 cards are 3.3 mm thick and type 2 cards a
5.0 mm. All have a 68-pin interface at one end.

6.1.1 Memory and 1/0 Address Space
A Memory Address Space of 64 Mbytes (AO-A25) is permitted for each memory card installed in a system. The Memory Addre
Space consists of Common Memory and Attribute Memory. The Common Memory may be accessed by a host for memory reo
and write operations.
There is an additional 64 Mbytes address space for Attribute Memory which is selected by the REG signal at the interface. TI
Attribute Memory is divided into
• Card Information Structure (CIS) - contains the manufacturer's description of card capabilities and specifications.
• Card Configuration Registers (CCR) - a set of registers that allows the card to be configured by the host.
The I/O Address Space of 64 Mbytes is shared and divided among all cards installed in the system. The I/O interface requires th
the Memory-Only Interface also be implemented within the same socket, and that the Memory-Only Interface be selected in tl
socket when no card is inserted and immediately following Card reset and the application of Vcc to the card. The I/O interface al~
supports additional signals like IREO, 101S16, 10WR, lORD, SPKR, INPACK and STSCHG.
The following diagram summarizes which address space that the host is accessing depending on the logic values of REG, I/O real
write and Memory read/write signals.

OE,WE
CE1, CE2

10RD,IOWR
CE1, CE2
f

ATTRIBUTE
MEMORY

COMMON
MEMORY

CIS

CCR

~__________- - )

y

MEMORY ADDRESS SPACE

[]
"--____~

y

~-.J

1/0 ADDRESS SPACE

Figure 6-1. Host Address Space Accessing

9-60

PCMCIA INTERFACE FOR 551 78Q8373
SSI 78Q8373 complies to the PCMCIA Release 2.1 Specifications and powers up as a memory card when in PCMCIA mode. To
enter the I/O mode, the Configuration Index CI(5:0) in the CCRO register must be written with a non-zero value. Only then can the
other registers of SSI 78Q8373 be accessed by the host.
In the Attribute Memory Address Space, the CIS is located at address 0 and the CCR is located at an offset value determined by
the CCRA pin, illustrated in Figure 6-2 below.

4000000hl

«
202h

1---_ _
C_C_R_1_ _-I

200h

I--_ _
C_C_R_O_ _-f

CIS

Oh

~

_ _ _ _ _ _--'

= A8
= 512 (decimal)

CCRA
29

= 200 (hex)

Figure 6·2. Attribute Memory Address 5pace

I
9-61

CCRA pin must be connected to another address pin apart from A(3:0). For instance, if CCRA is connected to AS, then CCR(
located at address 200h, an offset of 200h from address O. An example of how to use the SSI 7SQ8373 with a Flash Memory
EEPROM is shown below.

(CCRA - A8) - 0, A(7:0)
0(7:0)
OE
WE
FCE

0(7:0)

I

FLASH
MEMORY
OR
PARALLEL
E2
512 x 8

OE
WE

SSI78Q8373

(CeRA = A8) = 1, A(3:0)
CE, I/O SIGNALS

PCMCIA BUS
Figure 6-3. SSI 7808373 Interface to Flash Memory or EEPROM
6.3

GENERIC BUS INTERFACE FOR SSI 7808373
For non-PCMCIA applications, the SSI 78Q8373 can interface with the host via a 'generic' bus interface. Transferring of dat
packet status, packet sizes and so on can be accessed easily by the host either by using programmed I/O or DMA modes. Packe
to be transferred to the network must first be stored in the buffer memory via a register called Buffer Memory Register 8 (BMR~
Similarly, packets to be read by the host is retrieved via the BMR8. Thus BMR8 acts as a window to the buffer memory.
To interface with the host, the SSI 78Q8373 has 4 host address pins (HA<3:0», 16 host data pins (HD and manual selection is in effect. In manual selection mode, the AUI or TP port may be selected by writing appropriate
value to BMR13<4>.

TWISTED PAIR TRANSCEIVER
The TP transceiver supports complete IEEE 10BASE-T functionality as well as several enhanced functions such as autopolarity
detection and correction, smart-squelch logic and long distance mode .

.1 Link Integrity
During idle periods, link pulses are generated and received by both MAUs (Medium Attachment Units) at either end of the twisted
pair to ensure that the cable has not been broken or shorted. A positive, 100 ns Link Integrity signal is generated and transmitted
by the SSI 78Q8373 every 13 ms during idle periods. The chip assumes a link-good state if it receives valid link pulses or a packet.
Ifneitherisreceivedfor 105 ms, theSSI78Q8373 enters alink-fail state. It then needs4 consecutive positive link pulses (or 8 negative
link pulses) to resume link-good state. Only link pulses spaced between 3 ms and 105 ms are considered valid.
In a link-fail state, the SSI 78Q8373 disables normal Transmit, Receive, Collision, loopback and SQE test functions. The reception
of a packet will put the device in a link-good state. However, that packet will not be relayed to the Manchester ENDEC unit.
Subsequent packets will be relayed as per normal as long as the device remains in a link-good state.
The link status is flagged by register bit BMR15<6> as well as the LEDL TR pin. The Link Integrity function can be disabled by
writing a '1' to BMRI3<5> which forces the SSI 78Q8373 into a link-good state.

:.2 Autopolarity
Because twisted pair differential signals can easily be inverted due to wiring errors, the SSI 78Q8373 incorporates autopolarity
detection and correction circuitry. Polarity circuitry monitors the polarity of the received SOl (Start Of Idle) and link pulses and
corrects the data internally if the signal is inverted. The inverted polarity is flagged by register bit BMR 15<3> and the autopolarity
function may be disabled by writing a '1' to BMRI3<7>.

1.3 Smart Squelch Logic
The twisted pair squelch logic dynamically adjusts the sensitivity and threshold of the receiver. Before signals begin to arrive at the
TPIP/TPIN pins, the SSI 78Q8373 is in a high noise rejection, squelch state and no data is passed through. A valid incoming data
needs to trip the threshold detectors with three peaks of alternating polarity occurring within a 400 ns window. Once a signal has
been qualified by the squelch circuitry, the SSI 78Q8373 assumes an unsquelch state with reduced threshold. See the datasheet for
the squelch and unsquelch threshold levels.
At the beginning of each packet there is a preamble consisting of alternating ones and zeros resulting in a 5 MHz Manchester signal
on the twisted pair. The SSI 78Q8373 uses the standard 1OBASE-T specified threshold levels to unsquelch the incoming preamble.
As data begins to arrive, the 10 MHz component of the Manchester encoded signal may have less amplitude since it is attenuated
more than the 5 MHz component. For this reason, the threshold levels are reduced in the unsquclch state. This greatly reduces the
chance of prematurely detecting the SOl by the threshold detectors.
The twisted pair smart squelch circuitry is returned to a squelch state by any of these conditions: a normal SOl signal, an inverted
SOl signal or a missing SOl signal. A missing SOl signal is assumed when no transitions crossing the threshold detectors have
occurred for 250 ns after a packet has been received. In this case, a normal SOl signal is generated and appended to the received data.

1.4 Long Mode
Writing a' l' to BMR13<6> places the SSI 78Q8373 in long mode where the thresholds of the detectors are lowered to support longer
cable length than the recommended 100 meters. Dynamic squelch circuitry is still functional in long mode. The squelch threshold
of the long mode is the same as the un squelch threshold of the normal mode and the unsquelch threshold of the long mode is another
3 dB down.

1.5 Collision Detection
A collision happens when both transmitting and receiving functions occur simultaneously in the twisted pair transceiver. The
collision signal originating from the twisted pair transceiver is multiplexed together with the collision signal from the AUI module
and is relayed to the controller. Collisions will not be reported when the device is in a link-fail state. The internal collision signal
is also activated when a jabber condition occurs or when the SQE test is being performed.

9-63

I

7.1.6 SQE Test
An internal Signal Quality Error (SQE) test is also provided on chip. After each packet transmission, an SQE signal (also referr
to as "heartbeat" signal) is sent internally to the controller. This feature is provided to match the coax transceiver functionality

7.1.7 Jabber
An independent circuit monitors the length of each transmission and inhibits it if it surpasses a 26.2 ms maximum allowed transn
time. This function keeps a damaged node from continuously transmitting on the network. When jabber occurs, the transceiver al
discontinues loopback and sends a collision signal to the controller. The jabber status is flagged by register bit DLCRO<3>.

7.1.8 Normal Loopback
The twisted pair transceiver provides the normalloopback function specified by the lOBASE-T standard. The normalloopba
function is disabled when a collision occurs during which the received data from TPIP/N is passed through instead. Link fail aJ
jabber states also disable the normalloopback.

7.1.9 LED
The LEDLT pin serves functions. A connected LED lights up during link-good state and blinks off temporarily during transmissil
activity.

7.1.10 TP Driver
The transmit driver consists of four differential signals, the true and Complement transmit data TPOP, TPON and their respecti'
50 ns delayed signals TPDP, TPDN. These drivers, when combined with the resistor network shown in Fig 7.1, provide the sign
pre-equalization required by the lOBASE-T standard.
A Manchester encoded data consists of 10 MHz (50 ns) component as well as 5 MHz (100 ns) pulses. A twisted pair cable attenuat
a 10 MHz signal more than a 5 MHz signal. Equalization is required to decrease the relative power in the 5 MHz com pone
transmitted by the SSI 78Q8373. This causes the 10 MHz and 5 MHz components of the signal to have approximately the same pow

Figure 7.1. Twisted Pair Interface Connections (5 volts)
(contact Silicon Systems for 3-volt connections)
9-64

content at the far end of the twisted pair. To achieve the power reduction of the 5 MHz component, the four transmit signals are
summed resistively as shown in Fig 7.2. The values of the five network resistors are selected to allow the twisted pair line to be
terminated in 100 ohm.
The drivers are designed to have equal rise/fall times as well as balanced low-to-high and high-to-low propagation delays to minimize
common-mode energy. It is also important to maintain equal load capacitance from the board layout for each data output so as to
maintain the equal rise/fall times and propagation delays.
The twisted pair magnetics and filters shown in Fig 7.2 isolate the SSI 78Q8373 from the twisted pair media and reduce the radiated
emissions. As a result of the well matched drivers, the common-mode choke is optional and the device still meets the lOBASE-T
standard of +/- 50 m V of common-mode energy. Various integrated modules are available with di fferent level of integration from
a few vendors listed in Table 7.1.

·able 7.1
ption
1

2

Resistor Network
Discrete

Discrete

3

EMI Filter & Isolation
1) Pulse PE65421
2) Valor PT3877
3) Bel Fuse A556-2006-DE
4) FilMag 78Z1120B
1) Pulse PE65431
2) Valor FL 1012
31 Bel Fuse 0556-2006-01 0556-3392-00
1) Pulse PE65485
2) PCA EPE6052G

Common-mode Choke
(Optional)

.11 TP Receiver
The SSI 78Q8373 twisted pair receiver uses a high-speed differential comparator designed to preserve the edge timing of the
incoming data. The comparator architecture significantly minimizes the bit jitter added by the transceiver. Dual threshold detectors
are used by the twisted pair smart squelch circuitry to qualify both positive and negative signal peaks. The threshold levels are
dynamically controlled to further enhance the immunity to noise. Refer to the smart squelch logic section.

ATTACHMENT UNIT INTERFACE (AUI)
AUI is a standard Ethernet interface that connects Data Terminal Equipment (DTE) to a Medium Attachment Unit (MAU). There
are 3 pairs of differential signals that connect to an AUI: one pair for transmission, one pair for reception and the other one pair for
collision indication. A typical AUI connection diagram is given in Fig 7.2.
~.1

AUI Driver
The SSI 78Q8373 AUI drivers have been designed to provide balanced differential voltage levels when signaling. The drivers have
equallow-to-high and high-to-Iow propagation delays to provide minimal skew.
At the end of transmission, the AUI drivers ramp to VDD slowly to avoid undershoot. An internal digital to analog converter ensures
that the driver ramp-up occurs over approximately 8 J..IS resulting in a smooth transition into an idle state.

~.2

AUI Receiver
The AUI receiver uses high-speed differential comparator to preserve the edges and duty cycle of the incoming data. A threshold
detector and squelch circuit are used to qualify valid data from noise. During idle, the AUI is in a high noise rejection squelch state.
When the first negative edge crosses the threshold of the threshold detector, the AUI enters into unsquelch state and begins receiving
data. The AUI reverts back to squelch state by a normal Start-Of-Idle (SOl) signal or a missing SOl signal. A missing SOl signal
is assumed when no transitions haveoccuredon the receiver inputs for 175 ns. In this case, an SOl signal is generated and appended
to the received data.

9-65

I
•

7.2.3 Termination and Isolation

The AUI cable is specified by the standard to have characteristic impedance of 78 ohms. For mini mal reflection, the AUI cable t
to be terminated with a 78 ohm resistance at the far end. A 0.1 J..IF' capacitor connected to the mid val ue point of the termination resis
helps to bypass common mode noise picked up by the AUI cable. This capacitor is optional for on-board transceiver because th(
will be minimum common mode noise.
The SSI 78Q8373 AUI supports both transformer coupling as well as capacitive coupling as shown in the figure. Please note tl
for capacitive coupling, the termination resistors have to reside at the inputs of the SSI 78Q8373 AU! receivers.

DOP
DON

DIP
SSI78Q8373
DIN

CIP
CIN
REXT

fRm

=20 k

·
···
- - . lop
··
··
··
·
RECEIVE
···
··
¢TN
··
··
··
COLLISION
·
··
¢TN
··
· "(AUI CABLE)
···
·
---------------,·
TRANSMIT

" if 10 BASE-5
TRANSCEIVER

··
··
··· ISOLATION
····
·
··
·· ISOLATION
·
···
··
·· ISOLATION
·
··
··
··- - - - - - - - - - -

2)

FOR ON-BOARD
TRANSCEIVER

~

RT/2

RT/2

TRANSCEIVER

~

ISOLATION

TN (TERMINATION NETWORK)
1)

QTN

1) TRANSFORMER COUPLING

39
~O.1 f.JF

,

2) CAPACITIVE COUPLING
FOR OFF-BOARD
TRANSCEIVER

Figure 7.2. Attachment Unit Interface (AUI) Connections

9-66

MEDIUM

00

USING THE SSI 78Q8373 ON THE NETWORK
This section deals with the transmission of data using the SSI 7SQ8373 from the host point of view. It will cover the interaction
of register configurations and the actual transmission executed. For more detailed information on the function of the Data Link
Controller in this respect (with regards to Inter-Frame Gap, fairness and equality of the line, Jam Pattern, Backoff Algorithm etc.),
please refer to the Transmitter Circuits Section.

INITIALIZATION
Initialization begins with a hardware reset immediately after power on. A pulse with a minimum of 200 nanosecond duration is
required to be applied to the RESET pin. This resets ICE's internal pointers and registers to their initial state. ENADLC, DLCR6<7>
= 1 acts as a software reset resetting all buffer memory pointers. The software reset does not change the contents of the status and
control registers or the DLCR 0-7, IDR8-13, TDRI4-1S, HTRS-IS and BMRI0-1S registers. Hardware reset sets the ENADLC bit
high.
The initialization of the 8373 by the host include the loading of the Ethernet Address of the node into IDRS-13 with IDR8 as the
least significant byte of the address and group addressing in the Hash Table registers (if desired). To access the Node ID registers,
(or any of the other bank of registers) the following is executed. Please note that all register values arc in hexadecimal notation unless
otherwise stated.
a) Disable the DLC by setting DLCR6<7>

=1

b) Select the register bank by setting DLCR7<3:2> as required.
DLCR7<3:2> = 00 (default setting after hardware)
DLCR7<3:2> = 01 (selects Hash Table registers)
DLCR7<3:2> = 10 (selects Buffer Memory registers)
DLCR7<3:2> = 11 (Reserved)
The host should load the Ethernet Address and Hash Table Configurations at this stage.
c) The default settings of DLCRO-7 after a hardware reset or power on are as follows:
DLCRO = 00
DLCRI = 00
DLCR2 = 00
DLCR3 = 00
DLCR4 = 06
DLCRS = 41
DLCR6 = B6
DLCR7 = 20

(Transmit Status)
(Receive Status)
(Transmit Interrupt Mask)
(Receive Interrupt Mask)
(Transmit Mode)
(Receive Mode)
(Configuration Register 1)
(Configuration Register 2)

The host can now select the type of interrupt enables that should be activated in DLCR2-3. Unless a loop back mode is required
in a testing environment, DLCR4 need not be changed.
d) The default setting ofDLCRS allows the reception of normal packets i.e. packets that meet the IEEE requirements and does
not contain any errors. The host can enable the 'remote reset' capability of SSI 78Q8373 or enable the reception of 'bad packets'
with the activation of appropriate bits in this register. The Address Mode bits can be reprogrammed for hash table acceptance
if necessary. Please refer to the Data Link Controller Registers Section for details.
e) DLCR6 configures the size of the transmit buffer and overall buffer size. This should be changed according to the host's
requirements. DLCR6<7> is reset to 0 for transmission and reception activities and set to I for access to the Node ID and Hash
Table Register Banks.

t) DLCR7 configures the access to the 3 register banks. To access the Node ID and Hash Table Register Banks, DLCR6<7>
= 1 must be set to 1. DLCR7<0> sets the big endian and little endian byte ordering depending on the host's configuration.
g) BMRII denotes the action to be taken by SSI 7SQ8373 should a 16 collision happen on the network. This should be
programmed accordingly before transmission or the default setting will be used.

PACKET TRANSMISSION USING THE SSI 78Q8373
!.1 Transmission Without Contention
Before initiating a transmission, the host wi11load in the data packet(s) into the transmit buffer via BMR8 (and BMR9 if in word
mode). Each data packet will contain a 2-byte header of the total packet length, destination and source addresses and the data to be
transmitted. The host initiates transmission by writing the number of packets into BMR 10 and setling TXST bit = 1 (BMR 10<7».
9-67

I

The 2-byte header is loaded into a counter within the transmit circuit. The counter will decrement its value as each byte is transmit
to the medium. When it reaches zero, this signifies that an entire data packet has been transmitted. At the same time, the pac
count value (pACKET CNT<6:0» in BMR 10 will decrement by 1 each time a data packet is transmitted. When packet coun
zero, this indicates that there are no more packets in the transmit buffer. SSI 78Q8373 will enter its idle state and wait for the TX
bit to be set high again and the process is repeated.
SSI 78Q8373 will wait for a 'free' medium before transmitting to the network. When the network is free, SSI 78Q8373 will gener
and append the preamble and start frame delimiter to the beginning of the packet (the 2-byte header is stripped off and not transmiw
and generate the CRC for the packet. The entire packet starting from the preamble to the CRC is encoded by the ENDEC
Manchester Encoding and output to the external transceiver via the TDN and TDP pins.
The HWR_ERR bit (DLCRO is incremented and the transmission terminated. The COL bit (DLCRO<2» will be set to indicate that at least 0
collision has occurred during the transmission of that packet. After the random interval deferment, SSI 78Q8373 will attempt
re-transmit the collided packet and all other packets in the transmit buffer until the PACKET CNT in BMRlO<6:0> reaches zel
In the event of 16 collisions, SSI 78Q8373 will take appropriate action according to the 16 collision control register set in BMRl
There are four different actions for SSI 78Q8373 to choose when a packet has attempted 16 re-transmissions. The actions and 1
settings are shown in the register section for BMR11. The 16COL bit (DLCRO bit for the INTEL or MOTOROLA format, the data order swapping only applies to the host that
configured in word format. DLCR7<0> set to 0 refers to the INTEL format and DLCR7<0> = 1 refers to the MOTOROLA form;
In the INTEL format, the least significant byte is transmitted first then followed by the most significant byte. In the MOTOROL
format, the data order is reversed. Note that all the data stored in the buffer memory is affected, including the non-transmitted
byte headers for the length of the data packet. Only BMR8 and BMR9 are affected by this control bit.
The following tables describe the ordering of the packets depending on which format the host is configured. SSI 78Q8373 defaui
to the INTEL format upon power up.
TRANSMIT PACKET:
MOTOROLA FORMAT

INTEL FORMAT
HIGH BYTE
TX MSB lenQth
Destination address 2 nd
byte
Source address 2 nd byte

LOW BYTE
TX LSB lenQth
Destination address 1st
byte
Source address 1st byte

Length field LSB
Data field 2 nd byte

Length field MSB
Data field 1st byte

HIGH BYTE
TX LSB lenQth
Destination address 1st
byte
Source address 1st byte
Lenath field MSB
Data field 1st byte

9-68

LOW BYTE
TX MSB lenQth
Destination address 2 n(
byte
Source address 2nd byte
Lenath field LSB
Data field 2nd byte

rECEIVE PACKET:
MOTOROLA FORMAT
HIGH BYTE
LOW BYTE
Packet status
Reserved
Data length low byte
Data lenath hjgh byte
Destination address 1st Destination address 2 nd
byte
byte
Source address 1st byte
Source address 2 nd byte
Lenath field MSB
Lenath field LSB
Data field 1st byte
Data field 2 nd byte

INTEL FORMAT
IGH BYTE
LOW BYTE
eserved
Packet status
ata length high byte
Data length low byte
estination address 2 nd Destination address 1st
(te
byte
Source address 1st byte
ource address 2 nd byte
Lenath field MSB
:math field LSB
Data field 1st byte
ata field 2nd byte
PACKET RECEPTION USING THE SSI 7808373

:.1

Reception Without Contention
When not transmitting, SSI 78Q8373 will consistently monitor the network. To determine if a packet on the network is for the node,
SSI 78Q8373 will check the destination address of the packet. Depending on the Address Modes (DLCRS<1:0» of the node (set
during initialization), SSI 78Q8373 will accept the packet if the destination address meeL~ the criteria.
Upon a successful reception, the received packet is stored in the receive buffer. An internal counter in SSI 78Q8373 keeps track
of the length of the packet. SSI 78Q8373 allocates 4 bytes in the receive buffer before storing the accepted packet in the receive
buffer. This is for a 4-byte header of the accepted packet to the host (refer to Receive Buffer Data Format Section). The 4-byte header
contains the packet length and the status (CRC error, alignment error etc.) of the packet. At the end of the packet reception, SSI
78Q8373 writes the status of the accepted packet in the allocated space. By default, if a packet contains any errors, it will be discarded
and the receive buffer pointers will be restored automatically.
When a packet is accepted, the PKT_RDY (DLCRl<7» bit is set and the RX_BUFMTY (DLCR5<6» bit is cleared to indicate
to the host that there is a packet in the Receive Buffer. The host will then proceed to read the packet from the buffer memory. When
all the data packets in the receive buffer are read, the RX_BUFMTY (DLCRS<6» is set to '1' again. An OVRFLO, DLCR 1<0>
error occurs when the receive buffer is full or has insufficient space for the next accepted packet. This will result in the rejection
of the packet and the host would have to read the receive buffer to free some buffer space. Due to the ring structure of the receive
buffer, once the host has read some packets, that buffer space becomes available for the future packets.
After accepting a packet, the receiver will perform an 8-byte alignment in the receive buffer. An 8-byte alignment means that the
start address of the next packet will always begin at the 8-byte boundary (for example at address locations: OOOOH, 0008H,
OOIOH....etc.). The execution of8 byte alignment must be consistent between the receiver and the host read circuit. In the host read
circuit, there is a counter that loads the packet length value from the 4-byte header of the receive packet (3rd and 4th bytes of the
4-byte header). In a byte configuration, the counter will decrement each time a byte has been read out by the host. When the counter
reaches zero, this signifies that the entire packet has been read by the host. The host can continue to read the next packet if no other
resource requires the attention of SSI 78Q8373.

t2 ColliSion and Recovery
In the event of a collision, the receiver accepts the fragmented bits of the collision and decodes it just like a valid frame. A CRC
check would inform the host that the received packet has CRC errors by setting the CRC_ERR (DLCR 1< 1» to a 1. The host will
then discard this packet and the receive buffer memory pointers will be adjusted accordingly for the reception of the next packet.

3.3 How the SS17808373.Handles Other Situations
When the host is configured as word mode, there will be a situation whereby there are packets in the receive buffer are of odd byte
length. The host should discard the excess byte of the last word. SSI 78Q8373 maintains an internal counter and re-aligns
accordingly.
SSI 78Q8373 has the capability of accepting packets with errors or perform an extra group addressing mode depending on the bits
set in the Receive Mode Register, DLCRS. The effects on packet reception with reference to each spccific bit is elaborated below.
If ACPT_BADPKT (DLCRS is set to 1. Hence, t
status byte of the RAM is not a mirror image ofDLCR 1. Similarly, this applies when ENA_SRTPKT (DLCR5<3» is set to enac
SSI 78Q8373 to accept short packets.
As for the OVRFLO bit, it will be set under the following conditions. When the receive buffer memory is too small to accommoda
any in-coming packet, then DLCRI <0> will be set (but not bitO of the status byte as the packet has already rejected). Later, il
subsequent packet is successfully loaded into the receive buffer memory then the OVRFLO bit in the status byte will be set (but n
DLCR 1<0». This is to indicate to the host that one or more packets have been reject by the receiver due to memory overflo
problems.

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights of third partie
resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems reserves the right to ma~
changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders.

Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914

0894

©1994 Silicon Systems, Inc.
9-70

Application Guide
Monolithic Dual-Tone
Multi-Frequency
(DTMF) Receivers
January 1993
indicates a single dialed digit; to generate a valid digit
sequence, each DTMF signal must be separated by a
valid pause.

INTRODUCTION
The Silicon Systems integrated DTMF Receivers and
Transceivers are complete Touch-Tone™ detection and
generation systems. Each can operate in a stand-alone
mode for the majority of telecommunications applications, thereby providing the most economical implementation of DTMF signaling systems possible. Each combines precision active filters and analog circuits with
digital control logic on a monolithic CMOS integrated
circuit. SSI DTMF chip use is straightforward and the
external component requirements are minimal. This
application guide describes device operation, performance, system requirements and typical application circuits for the SSI DTMF chips.

Table 1 gives the established Bell system standards for
a valid DTMF signal and a valid pause. The SSI DTMF
Receivers meet or exceed these standards.
Similar device architecture is used in all SSI DTMF
Receivers. Figure 1 shows the SSI 75T202 Block Diagram. This architecture is implemented in all Silicon
Systems single chip receivers, as well as SSi Transceivers. In general terms, the detection scheme is as
follows: The input signal is pre-filtered and then split into
two bands, each of which contains only one DTMF tone
group. The output of each band-split filter is amplified
and limited by a zero-crossing detector. The limited
Signals, in the form of square waves, are passed through
tone frequency bandpass filters. Digital logic is then used
to provide detector sampling and determine detection
validity, to present the digital output data in the correct
format, and to provide device timing and control.

HOW THE SILICON SYSTEMS DTMF
CIRCUITS WORK
GENERAL DESCRIPTION OF OPERATION

The task of a DTMF Receiver is to detect the presence of
a valid DTMFsignalona telephone lineorothertransmission medium. The presence of a valid DTMF signal
PARAMETER

VALUE

One Low-Group Tone, and

697, 770, 852 or 941 Hz

One High-Group Tone

1209,1336,1477 or 1633 Hz

--"-'---~~-----

Frequency Tolerance

fo

- - I--

------

_.

...

± (1.5% + 2 Hz)
-~------~~-.---

-24 dB ~ A ~ 6 dBm @ 600n (Dynamic Range 30 dB)

Amplitude Range
-~---~

---_ .. _--

--_.

~-

Relative Amplitude (Twist)

-8dB ~ High Group Tone ~ +4dB
Low Group Tone

Duration

40 ms or longer

-

Inter-tone Pauses

_ _------_._--

~

--------~-

-"-_.--

--------

--~-

..

~-~-~--.------

------~----

---

----~-~---

40 ms or longer
TABLE 1: Bell System Standards

0193 - rev.

9-71

DTMF Receiver Application Guide

I

PERFORMANCE CONSTRAINTS

2)

Zero-cross detection. Limits the acceptable level
of noise during detection of a tone pair. Important
for speech rejection.

3)

Valid tone pair/pause sampling. Samples the
detection filters and checks for consistency before
a valid tone is declared.

SPEECH IMMUNITY AND NOISE TOLERANCE
The two largest problems confronting a DTMF Receiver
are:
1)

2)

Distinguishing between valid DTMF tone pairs and
other speech or stray signals that contain DTM F
tone pairfrequencies. This is referred to as Speech
Immunity.

DETAILED DESCRIPTION OF OPERATION
AUDIO PREPROCESSOR

Detecting valid tone pairs in the presence of nOise,
which is typically found in the telephone (or other
transmission medium) environment. This is referred to as Noise Tolerance.

The Audio Preprocessor is an analog filter that band
limits the input analog signal between 500 Hz and 6 kHz.
In addition, it emphasizes the 2 kHz to 6 kHz voice region.
Band limiting suppresses power supply and dial tone
frequencies, and high frequency noise. The emphasized
voice region helps to equalize the audio response since
many phone lines tend to roll off at about 1 kHz. In
addition, preservation of the upper voice frequencies is
important in providing speech immunity.

The SSI DTMF Receivers use several techniques to
distinguish between valid tone pairs and other stray
signals. These techniques are explained in later sec.
tions. Briefly, the techniques are:
1)

Pre-filtering of audio signal. Removes supply
noise and dial tone from input audio signal and
emphasizes the voice frequency domain.

TONE BAND SPLITTING
After the analog signal is preprocessed, it is split into two
bands, each of which contains only one DTMF tone

ED

(7g~t~)

CLRDV

DV

HEXJ828

Dl

lMz
D2

D4

08

EN
VP.

IN1633

GND

FIGURE 1: SSI75T202 Block Diagram
DTMF Receiver Application Guide

9-72

group. The band-split filters are actually band-stop filters
to maintain all frequencies except the other tone group;
this is done to maintain all analog information to enhance
speech immunity but not allow the other tone group to act
as interfering noise for the band being detected. These
band-stop filters have ''floors'' that limit the amount of
tone pair twist which further enhances speech immunity.
See device data sheets for acceptable twist limits.

preCise clock for the filters and for the logic timing and
control of the chip.
CIRCUIT IMPLEMENTATION

Standard CMOS technology is used for the entire circuit.
Logic functions use standard low-power circuitry while
the analog circuits use precision switched-capacitorfilter technology.

ZERO-CROSSING DETECTORS

HOW TO USE THE SSI DTMF RECEIVERS

The output of each band-splitfilter is amplified and limited
by a zero-crossing detector (limiter). The function of the
zero-crossing detector is to produce a square wave at the
prime frequency emanating from the band-split filter. If a
pure tone is not present, as in the case of voice or other
interfering noise, a rectangular wave with a variable
period will result. Proportional to the interference, the
limiter output power is spread over a broad frequency
range as the zero crossings "dither." When a high level
of noise or speech occurs, no single bandpass filter pair
will contain significant power long enough to result in a
tone detection. On the other hand, when a pure DTMF
tone exists with acceptable noise levies, the output of the
limiter will not have any significant dither and tone detection will occur. The zero-crossing detector also acts as
AGC (Automatic Gain Control) in that the output amplitude is independent of input amplitude; this additionally
establishes an acceptable signal-to-noise ratio not dependent on tone amplitude.
BANDPASS FILTERS & AMPLITUDE DETECTORS

The bandpass filters perform tone frequency discrimination. Their responses are tailored so that if the frequency
of the limited square wave from the zero-crossing detector is within the tone frequency tolerance, the fitler output
will exceed the amplitude detector threshold. The amplitude detectors are interrogated periodically by the digital
control circuitry to acertain the presence of only one tone
in each band for the required duration. In a similar
fashion, valid pauses are measured by the absence of
valid tone pairs for the specified time.

PRECAUTIONS

Although static protection devices are provided on the
high-impedance inputs, normal handling precautions
observed for CMOS devices should be used.
All CMOS parts are prone to a destructive latch-up mode.
This behavior is inherent to these parts due to their
physical structure. The latch-up mode can best be
described as a low impedance, high current state existing
between the power supply connections on a CMOS chip.
This is also referred to as triggering of parasitic SCR
behavior.
The most common cause of a latch-up mode is operating
a CMOS part outside its rated power supply voltage. This
over-voltage need not be applied at power supply pins
only to cause latCh-up. Latch-up can occur when overvoltage is applied at any input oroutput. Forthe SSI DTMF
Receivers & Transceivers, the pin voltages should be
constrained to the range between VN - 0.5V and VP +
0.5V (except the analog input pin whose conditions are
discussed below). Clamping diodes should be utilized
wherever necessary to ensure~that voltage ratings are
not exceeded.
Another cause for latch-up is fast dv/dt transients affecting the chip. These transients are encountered in applications that require the connection/disconnection of "live"
boards. While these applications are very rare and their
implementation is best avoided, it must be mentioned
that whenever they are necessary, they present a severe
environment for CMOS parts. Care must be taken in
such instances to ensu re that grou nd planes and rails are
connected first and disconected last. This will go a long
way in eliminating voltage transients.

TIMING AND LOGIC

During the qualification process, the output decoder
gererates the proper digital code for the received DTMF
tone pair. Afterthe fidelity and duration ofthis signal have
been verified, the timing circuitry latches this code into
the output register and raises the data valid (DV) flag.

Voltage transients that exist on power lines must also be
eliminated. High voltage transients caused by switching
of high current devices can trigger latch-up. High frequency decoupling is a requirementforthe proper operation of the SSI DTMF devices. A 0.01J..lF to a 0.1J..lF
ceramic decoupling capacitor should be connected to the
power supply pin at the Chip.

The only precision external element needed for the SSI
DTMF Receivers is a 3.58 MHz parallel resonant crystal
(color-burst frequency) with a .01 % tolerance for the onboard oscillator. A 1 Mn 10% resistor should be connected in parallel with the crystal. This generates the
9-73

DTMF Receiver Application Guide

I

+V

(12V)

Vp
12 VOLT
SSI
DTMF

OPEN COLLECTOR INTERFACE

FIGURE 2: Interface Circuit for Conversion from TTL Output Levels to 12V SSI DTMF Input Levels
POWER SUPPLY

ANALOG INPUT

Excessive power supply noise should be avoided, and to
aid the user in this regard, power supply hook-up options
are provided onsome devices.

The analog input is the signal input pin for the devices,
and is specially biased to facilitate its connection to
external circuitry, as shown in Figure 3. The signal level
at the analog input pin must not exceed the positive
supply as stated on the device data sheets. If this
condition cannot be guaranteed by the external circuitry,
the signal must be AC coupled into the chip with a .01 fJ.F
± 20% capacitor.

Since the digital circuitry of the devices possess the high
noise immunity characteristics of CMOS logic, it is the
analog section that is affected most by power supply
noise. On those SSI DTM F Receivers that have separate
Analog Negative and Digital Negative supply connections (grounds), namely VNA and VND, an unfiltered
supply may be used at VND. It is necessary that VND and
VNA differ no more than 0.5V.

ANALOG INPUT NOISE
The SSI DTMF Receivers will tolerate wide-band input
noise of up to 12 dB below the lowest amplitude tone
component during detection of a valid tone pair. Any
single interference frequency (including tone harmonics)
between 1 kHz and 6 kHz should be at least 20 dB below
the lowest amplitude tone component. Adherence to
these conditions will ensure reliable detection and full
tone detection frequency bandwidth. Because of the
internal band limiting, noise with frequencies above 8 kHz
can remain unfiltered. However, noise near the 56 kHz
internal switched-capacitor-filter sampling frequency will
be aliased (folded back) into the audio spectrum; noise
above 28 kHz therefore should be low-pass filtered with
a circuit as shown in Figure 4 using a cut-off frequency
(/c) of 6.6 kHz.

The analog circuitry of the devices require low power
supply noise levels as specified on the device data sheet.
The effects of excessive power supply noise are decreased tone amplitude sensitivity and less tone detection frequency bandwidth. Power supply noise can be
significantly reduced by decoupling the chip with a 0.1 fJ.F
ceramic capacitor. Power supply noise effects will be
slightly less if the analog input is referenced to VP. This
is normally accomplished by connecting VP to ground
and utilizing a negative power supply.

DIGITAL INPUTS
The digital inputs are directly compatible with standard
CMOS logic devices powered by VP and VN (or VND).
The input logic levels should swing within 30% of VP or
VN to insure detection. Any unused input must be tied to
VN or VP. Figure 2 shows a method for interfacing TIL
outputs to 12V SSI DTMF Receivers.

DTMF Receiver Application Guide

A 1 kHz cut-off frequency filter can be used on "normal"
phone lines for special applications. When a phone line
is particularly noisy, tone pair detection may be unreliable. A 1 kHz low pass filter will remove much of the noise
energy but maintain the tone groups; however, a decreased speech immunity will result. This usage should
only be considered for applications where speech immunity is not important, such as control paths that carry no
speech.
9-74

vp
I
I
I
I
I
I
VIN < VP I
I
I
I
I
I

>-

c:

:!:
(.)

I
I
I
I
I
I

>-H- ,

f-

c

Analog in :

vp
I
I
I
I
I
I
VIN > VP I
I
I
I
I
0.01 iJ-F
I

Q.

Analog in I
I
I
I
I
I
I
GND

c:
:c
(.)

r

c

Q.

GND

FIGURE 3: Direct and AC Coupled Configurations
Some DTMF tone pair generators output distorted tones
which the SSI DTMF Receivers may not detect reliably
(inexpensive extension telephones are an example).
Most of the interfering harmonics of these may be removed by the use of a 3 kHz low-pass filter as in Figure 4.
Some speech immunity degradation will result. It should
be mentioned that when using low-pass filters, a higher
cut -off frequency will preserve more of the speech immunity advantages.
The SSI DTMF Receivers provide superior speech immunity and noise rejection. The analog signals are
subjected to stringent criteria and rigorous qualification in
order to assure that only true DTMF tone pairs are
detected and decoded properly. Stray signal and noise
with sufficient amplitude will cause a DTMF receiver to
disqualify a DTMF tone pair.
Such a condition can be occasionally encountered when
using DTMF "beepers." Beepers are normally used to
transmit DTMF signals from dial-pulse phones. It has
been obse(ved that the non-linearity in the response of
carbon microphones in telephone handsets introduces
intermodulation products, which actually produce new
frequency components. These components happen to
fall direclty into the useful bandwidths of some of the
basic tones that the receiver must detect. Because of the
presence of these components (normally referred to as
third-tone) with a valid DTMF tone, detection is disabled.
To inhibit the more common higher frequency third tones
from arriving to the receiver, the circuit shown in Figure 5
is suggested.

9-75

TELEPHONE LINE INTERFACE
In applications that use an SSI DTM F Receiverto decode
DTMF signals from a phone line, a DAA (Direct Access
Arrangement) must be implemented. Equipment intended for connection to the public telephone network
must comply with and be registered in accordance to
FCC Part 68. For PBX applications referto EIA Standard
RS-464.
Some of the basic guidelines are:
1)

Maximum voltage and current ratings of the
SSI DTMF Receivers must not be exceeded; this
calls for protection from ringing voltage, if applicable, which ranges from 80 to 120V RMS over a
20 to 80 Hz frequency range.

2)

The interface equipment must not breakdown with
high-voltage transient tests (including a 2500V
peak surge) as defined in the applicable document.

3)

Phone line termination must be less than 2000 DC
and approximately 600n AC (200-3200 Hz).

4)

Termination must be capable of sustaining phone
line lop current (off-hook condition) which is typically 18 to 120 mA DC.

5)

The phone line termination must be electrically
balanced with respect to ground.

6)

Public phone line termination equipment must be
registered in accordance to FCC Part 68 or connected through registered protection circu itry.
Registration typically takes about six months.

DTMF Receiver Application Guide

I
•

R

C

(kQ)
(=5%)

(1lF)
(=20%)

1.0

1.6

0.1

3.1

5.1

0.01

6.6

2.4

0.01

FC
(kHz)

ANALOG IN

NOISY
SIGNAL

DTMF
RCVR

I

SUGGENSTED
COMPONENT VALUES

FIGURE 4: Filter for Use in Noisy Environments
Ready made DAA devices are also available. The SSI
73M9001 is a DAA Micromodule housed in a 30-pin DIP
footprint.

audio to be placed on the line (a recorded message, for example) and not interfere with incoming DTMF tone detection.

OUTPUTS

Figure 6 shows a simplified phone line interface using a
600n 1:1 line transformer. Transformers specially designed for phone line coupling are available from many
transformer manufacturers.
Figure 7 shows a more enhanced version of Figure 6.
These added features include:
1)

A 150V su rge protector to eliminate high voltage
spikes.

2)

A Texas Instruments TCM 1520A ring detector,
optically isolated from the supervisory circuitry.

3)

Back-to-back Zener diodes to protect the DTM F
(and optional multiplexer Op-Amp) from ringer
voltage.

4)

Audio multiplexer which allows voice or other

The digital outputs of the SSI DTMF Receivers (except
XOUT) swing between VP and VN (or VND) and are fully
compatible with standard CMOS logic devices powered
from VP and VN. The 5V DTMF devices wi" also
interface directly to LSTTL. The 12V DTMF devices can
interface to TTL or low voltage MOS with the circuit in
Figure 8.
Data Outputs D8, D4, D2 and D1 are three-state enabled
to facilitate interface to a three-state bus. Figure 9 shows
the equivalent circuit for the data outputs in the high
impedance state. Care must be taken to prevent either
substrate diode in Figure 9 from becoming forward biased or damage may result.

51K
0.01 IlF
INPUT

0-1 I

0.011lF

ANALOG IN
12.9K

VCC

FIGURE 5: Filter for Use in Environments where a Third Tone Exists

DTMF Receiver Application Guide

9-76

SSI
DTMF
RCVR

TIMING
Within 40 ms of a valid tone pair appearing at the DTMF
Receiver Analog Input, the Data Outputs D8, D4, D2 and
D1 will become valid. Seven microseconds afterthe data
outputs have become valid DV will be raised. DV will
remain high and the outputs valid while the valid tone pair
remains present. Refer to individual data sheets for the
timing of signals.

_----l

TIP]

ANALOG
INPUT
SSI DTMF
RECEIVER

RING
1 :1
600n

SYSTEM INTERFACE
Provision has been made on the SSI DTMF Receivers
(with the exception of SSI 75T204) for handshake interface with an outside monitoring system. In this mode, the
DV strobe is polled by the monitoring system at least
once every 40 ms to determine whether a new valid tone
pair has been detected. If DV is high, the coded data is
stored in the monitoring system and the CLRDV is pulsed
high. With some systems operating in the handshake
mode, it may be desirable to know when a valid pause
has occurred. Ordinarily this would be indicated by the
falling edge of DV. However, inthe handshake mode, DV
is cleared by the monitoring system each ti me a new valid
tone pair is detected and, therefore, cannot be used to
determine when a valid pause is detected. The detection
of a valid pause in this case may be observed by
detecting the clearing of the Data Outputs. Since, in
hexadecimal format (the mode normally used with a
handshake interface), the all zero state represents a
commonly unused tone pair (D), the detection of a valid

FIGURE 6: Simplified Phone Line Interface
pause may be detected by connecting a four-input NOR
gate to the device outputs and sensing the all zero state.
TIME BASE
The SSI DTMF Receivers contain an on-chip oscillator
for a 3.5795 MHz parallel resonant quartz crystal or
ceramic resonator. The crystal (or resonator) is placed
between XIN and XOUT in parallel with a 1 Mn resistor,
while XEN is tied high. Since the switched-capacitorfilter time base is derived from the oscillator, the tone
detect band frequency tolerance is proportional to the
time base tolerance. The SSI DTMF Receiverfrequency
response and timing is guaranteed with a time base
accuracy of at least ± 0.01 %. To obtain this accuracy the
CTS Part No. MP036 or Workman Part No. CY1-C or

22 kn

TIP

o----;----.--------OoIIIIf--<:>--____

...fi""150V
ANALOG
INPUT
SSI DTMF
RECEIVER

ISOLATED OUTPUT
RING

0----1-----*-------------'
FIGURE 7: Full Featured Phone Line Interface
9-77

DTMF Receiver Application Guide

I

Vp

5V

vp
SSI75T201
OUTPUT PIN

12 VOLT

551DTMF

FIGURE 8: SSI 12V DTMF to TTL Level Interface

FIGURE 9:Equivalent Circuit of SSI DTMF Receiver
Data Output in High Impedance State

equivalent quartz crystal is recommended. In less critical
applications a suitable ceramic resonator may be implemented.

response that provides a minimum of 18 dB rejection at
350 Hz, and 24 dB rejection at 440 Hz so long as the
component tolerances indicated are observed. The
DTM F on-chip filter rejects 350 Hz at least 6 dB more than
440 Hz. Therefore, employing the filter of Figure 10
yields a dial tone tolerance of +24 dB.

The use of a ceramic resonator requires the addition of
tw030pF± 10% capacitors; one between XIN and VN (or
VND) and the other between XOUT and VN (or VND).
Extra caution should be used to avoid stray capacitance
on the resonant circuit when using a ceramic resonator
instead of a quartz crystal.

PRINTED CIRCUIT BOARD IMPLEMENTATION
The SSI DTMF Receivers are analog in nature and
should be treated as such; circuit noise should be kept to
a minimum. To be certain of this, all input and output lines
should be kept away from noise sources (high frequency
data or clock lines); this is especially true for the Analog
Input. Noise in the ground or power supply lines can be
avoided by running separate traces to supportive logic
circuits or by running thicker (lower resistance) busses.
Capacitance power supply bypassing should be performed at the device. Referto the Power Supply section
above.

When the oscillator is connected as above and XEN is
tied high, the ATB (Alternate Time Base) pin delivers a
square wave output at one-eighth the oscillator frequency (447.443 kHz nominal). The ATB pin can be
converted to a time base input by tying XEN low; ATB can
then be externally driven from another device such as the
AT'B output of another DTMF. No crystal is required for
the ATB input device; XIN must be tied high if unused.
Several SSI DTMF Receivers can be driven with a single
crystal (refer to device data sheet for fan-out limit).

PERFORMANCE DATA
A portion of the final SSI DTMF Receiver device characterization uses the Mitel CM7290 tone receiver test tape.
The evaluation circuit shown in Figure 11 was used to
characterize the SSI 75T201. The speed and output
level of the tape deck must be adjusted so that the
calibration tone at the beginning of the tape is at exactly
1000 Hz and 2V rms.

XOUT is designed to drive a resonant circuit only and is
not intended to drive additional devices. If a 3.58 MHz
clock is needed for more than one device and it is
desirable to use only one resonant device, an outside
inverter should be used for the time base, buffered by a
second inverter or buffer. The buffer output would then
drive XIN of the SSI DTM F Receiver as well as the other
device(s); XOUT must be left floating and XEN tied high.

The Mitel tape tests yield similar results on all of the
SSI DTMF Receivers. Test results for the SSI 75T201
are summarized in Table 2. In short, the measured
performance data demonstrates that the SSI DTMF
Receivers are monolithic realizations of a full "central
office quality" DTMF Receiver.

DIAL TONE REJECTION
The SSI DTMF Receivers incorporate enough dial tone
rejection circuitry to provide dial tone tolerance of up to
dB. Dial tone tolerance is defined as the total power of
precise dial tone (350 Hz and 440 Hz as equal amplitudes) relative to the lowest amplitude tone in a valid tone
pair. The filter of Figure 10 may be used for further dial
tone rejection. This filter exhibits an elliptic highpass

o

DTMF Receiver Application Guide

9-78

CIRCUIT IMPLEMENTATION
(SINGLE SUPPLY)

Vp
Vp

TO SSI DTMF
ANALOG IN PIN

6000

Note: All resistors 1%, all caps 5%, unless noted, op-amps: 1/2 LM1458 or equivalent

FIGURE 10: Dial Tone Reject Filter

+12V

6
H/B28

Vp

3.579545 MHz

XOUT 14

EN

XINI-'-'-~---'

SSI75T201

5 IN1633
19
12
13

0.1 ~F

08

elROV
ANALOG

04
02

IN

21
22

I

01

VNA
VNO

20

OV

-

FIGURE 11: Circuit for Receiver Evaluation

9-79

DTMF Receiver Application Guide

TEST #

RESULTS

= 5.0% of fo
= 5.0% of fo
B.W. = 5.3% of fo
B.W. = 4.9% of fo
B.W. = 5.0% of fo

2a, b

B.W.

2c, d

B.W.

-~

I--------+-------------------~.----~---~

2e, f
2g, h
2i, j
2k, I

B.W. = 5.3% of fa

2m, n

B.W. = 5.3% of fo

20,

P

B.W.

3

....-------~---------

._-------_._---

--

= 4.8% of fo

160 decodes
Acceptable Amplitude Ratio (Twist)

= -19.1

dB to +15.2 dB

-

------~~----~-~

Dynamic Range = 32.5 dB
--~-----------.~

Guard Time

= 23.3 ms
--------~---~~

100% Successful Decodes at N/S Ratio of -12 dBV
-.~-------.----

2-3 Hits Typical on Talk-Off Test
TABLE 2: Mitel #CM7290 Tape Test Results for SSI75T201 (Averaged for 10 parts)

APPLICATIONS
CREATING HEXADECIMAL "0" OUTPUT UPON
DIGIT "0" DETECTION
To be consistent with pulse-dialing systems, theSSI DTMF
Receivers provide a hexadecimal "10" output upon the
detection of a digit "0" tone pair when in the hexadecimal
code format. However, some applications may instead
require a hexadecimal "0" with a digit "0" detection. The
circuit of Figure 12 shows an easy method to recode the
hexadecimal outputs to do this using only 4 NOR gates.

DB

DB

D4
SSI
DTMF
RECEIVER

Note that this circuit will not give proper code forthe ,,* ",
"B", or "C" digits and will cause both digits "D" and "0" to
output hexadecimal "0." This circuit should therefore be
considered for numeric digits only. The output code
format is shown in Table 3.

D2

D2

D1~---------------<::
EACH NOR GATE 114 OF 4001

This circuit is useful for applications that require a display
of dialed digits; the digit display usually requires a hexadecimal "0" input for a "0" to be displayed.

01

FIGURE 12: Hex "0" Out with Digit "0" Detect
Conversion Circuit

1~CHANNELREMOTECONTROL

The 4514 raises one of its 16 outputs in response to the
4-bit output code from the DTMF. The output at the 4514
will remain high until the next button is depressed.

DTMF signaling provides a simple, reliable means of
transmitting information over a 2-wire twisted pair. The
complete schematic of a 16-channel remote control is
shown in Figure 13. When one of the key pad buttons is
depressed, a tone pair is sent over the transmission
medium to the SSI DTM F Receiver.

DTMF Receiver Application Guide

04

9-80

Hexadecimal
08
04

Digit

02

01

Digit

Hexadecimal & Figure 12 Circuit
08
04
02

01

1

0

0

0

1

1

0

0

0

1

2
3

0
0
0
0
0

0
0

1
1

0

0
0

0

1

0

1

2
3

0

1

1

1
1

0

0

4

0

1

0

0

1

5

0

0

1
1

0

6
7

0

1

0

1
0
0

1
0

0

1
1
1
0
0
0

0
1

0

0

0

1
1

1
1
1
1
0

0
0
0
0
0

4

5
6

0

7
8
9
0

1
1
1

.

1
1
0

0

0

0

1
0
1

0

1

0

0

1

1

.

1
1

0

1

1

0
1
0

#
A
B

C
D

B

1
1
1
1

C
D

1

1

1

1

0

0

0

0

#

A

8
9
0

0

0

1
1

0
0

0

1
1

0
1
0

0

1

0

0

TABLE 3: Output Code of Figure 13

Vp

3.579545 MHz

Vp

XOUT

H!B28

EN
16

XEN
XIN

SSIOTMF
RECEIVER

19
12
13
10pF

20

lN16:;.3

08

CLROV

04

ANALOG IN

02

21
22

VNA

01

VNO

OV
18

COLI

-=-

o

COL2

Vp
24
0

6VOR 9V
BATTERY

2

SO
9 SI

MK 5087

10 S2

16

14

Vdd

8 S3
7
S4

V+

v-

11

01

S5
S6
S7

13
18
17

12

lK

20
19

11

14
V-

13
16
15

S8

02
4514
03

21

S9
S10

04

22

SII
S12

STROBE

S13
SIS

ENl
23

S14
Vss
12

FIGURE 13: 16-Channel Remote Control
9-81

DTMF Receiver Application Guide

I

2-0F-8 OUTPUT DECODE

is delayed by R1-C1 so that reset and count input do not
overlap. The binary outputs of IC-1 will reflect the pulse
count and 0.2 seconds after the last pulse the 01-NOT
output will go high. C3-R3 differentiate this pulse and
clock the output latch, IC-3, holding the output pulse until
the next digit.

The circuit shown in FiQure 14 can be used to convert the
binary coded 2-of-8 to the actuaI2-of-8 code (or 2-of-7 if
detection of 1633 Hz tone is iflhibited). The output data
will be valid while DV is high. If it is desired to force the
eight outputs to zero when a valid tone is not present, DV
should be inverted and connected to both E-NOT inputs
of the 4555.

The 0.2 second timeout of IC-2A indicates the end of dial
pulsing since even a slow (8 pps) dial would input another
pulse every 0.125 seconds. The binary outputs of IC-1
are paralleled with those of the SSI DTMF Receiver
circuit through diodes to the inputs of IC-3. A pulldown
resistor is necessary on each IC-3 input pin. IC-1 must
be a binary, not BCD, counter.

DTMF TO ROTARY DIAL PULSE CONVERTER
The 2-of-8 output of Figure 14 can be modified to interface with a pulse dialer as shown in Figure 15. If a 12V
DTMF is used the 4049 will translate the 12V outputs to
the 5V swings required for the MK5099 pulse dialer.

With a 4175 for IC-3 the output data is latched until the
next valid input, whether from a rotary dial or dual tone
instrument. A unique situation exists, however, when
going on-hook. The loop detector will output a continuous level of VP which would trigger IC-2A and put a single
count into IC-1.A high level from the loop detector also
turns on 01, pulling the clock input of IC-3 to ground.
Since the loop detector output will be low at the completion of dialing, all outputs are valid even when the
telephone is placed on-hook, an important consideration
if output data is recorded.

Figure 16 shows the interface for adding pulse detection
and counting to a SSI DTMF Receiver.
The loop detector provides a digital output representing
the telephone loop circuit "make" and "break" condition
associated with rotary pulse dialing. For the circuit of
Figure 16, ground represents a "make" and VP a "break."
The loop detector feeds dial pulses to IC-1, a binary
counter, and to IC-2A, a re-triggerable "one-shot." When
a dial pulse appears the 01-NOT output of IC-2A immediately goes low, resetting IC-1. The clock input to IC-1

Vp

3.579545 MHz

Vp
XOUT
3
16

EN
XEN
XIN

5510TMF
RECEIVER

I~~
52

5
19

INPUT

12

IN 1633

DB

CLRDV

D4

ANALOG IN

02

VNA

01

13

4

8
20

03

21

A

04

8

00

4

02

697

5

770

6

852

7

941

1209
11

1336

10

1477

15

ORVIN
V NO

00

OV

A

03

Vss

FIGURE 14: Touch-Tone™ to 2-of-8 Output Converter

DTMF Receiver Application Guide

9-82

Vp

+5V
VP
H/B28

14

D

13

-

XOUT

14

EN
16

3.579545 MHz

1M
XEN

3.579545 MHZ

D

XIN

12

S1
SSI DTMF
RECEIVER

11
U1
MK 5087

52

19
COl2
TONE OUT

IN1633

D8

ClRDV

D4

VNA

D1

-I'------..---=-j
12
ANALOG IN

-

16 ~~~"-'--------+-I TRANSMISSION
COl1

MEDIUM

13

1- __

D2

20
21
22

ORVN

VND

DV
18

4556

4049

MK5099

1477
DIAL PULSES OUT

C3

18
MUTE

R4

V-

R3
R2
R1

RC1

1 MEG

1209

C1

Vp 0 - - - - - - 1 V+

QO
Q1

7

Q3

(658)

1336

C2
12

4
5

13

941

12

QO

14

852

11

Q1

15

no

10

02

16

697

9

Q3

14
(658)

15
13

RC3
NOT NEEDED IF A 5 VOLT SSI
DTMF RECEIVER IS USED
THE 4556 MUST THEN BE
REWIRED TO COMPENSATE
FOR THE MISSING INVERSION.

270K

FIGURE 15: Touch-Tone™ to Rotary Dial Pulse Converter Adding Rotary Dial Pulse Detection Capabilities

I
9-83

DTMF Receiver Application Guide

DATA OUTPUT
FROM SSI DTMF
A

8

C

D

IC-1
112-4520

IC-3
4175
A

ao

i

DO

8

01

C

02

D

03

00

D1

01

D2

02

D3

03

RESET
+12
R2

C2

100K

.1

Vp
.047

~

100K
'DV' FROM
SSI DTMF
10K
IC-2A

1/2-4538
OIS

i

.047
C3
01

2 SEC
100K

ALL DIODES - SMALL SIGNAL
SILICON -1N914, 1N4154, ETC.
01

FIGURE 16: Adding Pulse Detection and Counting to the SSI DTMF Receiver

No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights of third
parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems reserves
the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current
before placing orders.

Silicon Systems, Inc., 14351 Myford Road, Tustin, GA 92680-7022, (714) 573-6000, FAX: (714) 573-6914

DTMF Receiver Application Guide

0193 - rev.

Glossary
ANSWERBACK - A reply message from a terminal that
verifies that the correct terminal has been reached and
that it is operational.
ACK - "Acknowledge" character. A transmission control
character transmitted by a station as an affirmative
response to the station with which a connection has
been set up. An acknowledge character may also be
used as an accuracy control character.
ACOUSTIC COUPLER - A type of low-speed modem
interface frequently used with portable terminals. It
sends and receives data using a conventional telephone handset and does not require an electrical connection to the line.
ADAPTIVE DIFFERENTIAL PULSE CODE MODU·
LATION (ADPCM) - An encoding technique, standardized by the CCITT, that allows an analog voice conversation to be carried within a 32K bps digital channel.
Three or four bits are used to describe each sample,
which represents the difference between two adjacent
samples. Sampling is done 8,000 times per second.
ALGORITHM - A prescribed set of well-defined rules for
the solution of a problem in a finite numberof steps, e.g.,
A full statement of an arithmetic procedure for evaluating sine x to a stated precision.
AMPLITUDE - Magnitude or size. In waveforms or
signals occurring in a data transmission, a complete
definition of the waveform can be made if the voltage
level is known at all times. In this case, the voltage level
is called the amplitude.
AMPLITUDE MODULATION - Method of modifying the
amplitude of a sine wave signal in order to encode
information.
ANALOG LOOPBACK - A technique used for testing
transmission equipment that isolates faults to the analog signal receiving or transmitting circuitry. Basically,
where a device, such as a modem, echoes back a
received (test) signal that is then compared with the
original signal.
ANALOG SIGNAL - Signal in the form of a continuously
varying physical quantity such as voltage, which reflects
variations in some quantity.
ANSI- American National Standards Institute. A highly
active group affiliated with the International Standards
Organization (ISO) that prepares and establishes standards for transmission codes (e.g., ASCII), protocols
(e.g., ADCCP), media (tape and diskette), and high
level languages (e .g., Fortran and Cobol), among other
things.
0194 - rev.

APPLICATION LAYER- Thetopoftheseven-layerOSI
model, generally regarded as offering an interface to,
and largely defined by, the network user; in IBM's SNA,
the end-user layer.
ASCII- American Standard Code for Information Interchange. A 7 -bit binary code that defines 128 standard
characters for use in data communications.
ASYNCHRONOUS - Occurring without a regular or
predictable time relationship to a specified event, e.g.,
The transmission of characters one at a time as they are
keyed. Contrast with synchronous.
ASYNCHRONOUS TRANSMISSION - Transmission
in which each information character, or sometimes each
word or small block, is individually synchronized, usually by the use of start and stop elements. Also called
start-stop or character asynchronous transmission.
ATTENUATION - A decrease in the power of a current,
voltage, or power of a received signal in transmission
between points because of loss through lines, equipment or other transmission devices. Usually measured
in decibels.
AUI - Attachment unit interface. The electrical interface
between the traditional line electronics (transceiver)
and the DTE components (ENDEC & MAC).
AUTO-ANSWER - Automatic answering; the capability
of a terminal, modem, computer, or a similar device to
respond to an incoming call on a dial-up telephone line,
and to establish a data connection with a remote device
without operator intervention.
AUTOBAUD - The generally used term for automatically detecting the bit rate of a start/stop (character
asynchronous) communication format by measuring
the length of the start bit of the first character transmitted. Some modems extend this to additionally determine the parity in use by stipulating that the first two
characters from the DTE should be "AT." The word
autobaud comes from a popular misuse of baud rate to
mean the same as bit rate.
AUTODIAL - Automatic dialing; the capability of a
terminal, modem, computer, or a similar device to place
a call over the switched telephone network, and establish a connection without operator intervention.

9-85

I

AUTOMATIC DIALER, OR AUTODIALER - Device
which allows the user to dial preprogrammed numbers
simply by pushing a single button.

BANDPASS FILTER - A circuit designed to allow a
Single band of frequencies to pass; neither of the cut-off
frequencies can be zero or infinite.
BANDWIDTH - 1) The range· of frequencies that can
pass over a given circuit. The bandwidth dete rmines the
rate at which information can be transmitted through the
circuit. The greater the bandwidth, the more information
that can be sent through the circuit in a given amount of
time. 2) Difference, expressed in hertz (Hz), between
the highest and lowest frequencies of a transmission
channel.

BINARY SYNCHRONOUS COMMUNICATIONS - A
half-duplex, character-oriented data communications
protocol originated by IBM in 1964. It includes control
characters and procedures for controlling the establishment of a valid connection and the transfer of data. Also
called bisync and BSC. Although still enjoying widespread usage, it is being replaced by IBM's more
efficient protOCOl, SDLC.
BIPOLAR - 1) The predominant signaling method used
for digital transmission services, such as DDS and T1 ,
in which the signal carrying the binary value successfully alternates between positive and negative polarities. Zero and one values are represented by the Signal
amplitude at either polarity, while no-value "spaces" are
at zero amplitude. 2) A type of integrated circuit (IC or
semiconductor) that uses NPN, PNP, and junction
FET's as the primary active devices, as opposed to
CMOS, which uses MOS FET's. See Alternate Mark
Inversion.

10Base-T - Ethernet on unshielded twisted pair.
BISON - Broadband integrated services digital network.
10Base-2 - Ethernet on thin coax.
BIT - The smallest unit of information used in data
processing. It is a contraction of the words "binary digit."

10Base-5 - Ethernet on thick coax.
BASEBAND - Pertaining or referring to a signal in its
original form and not changed by modulation. A
baseband signal can be analog or digital.
BASEBAND SIGNALING - Transmission of adigital or
analog Signal at its original frequencies, i.e., a signal in
its original form, not changed by modulation; can be an
analog or digital signal.
B'AUD - A measure of data rate, often misused to
denote bits per second. A baud is equal to the number
of discrete conditions or signal events per second.
There is disagreement over the appropriate use of this
word, since at speeds above 2400 bitls, the baud rate
does not always equal the data rate in bits per second.
BELLCORE - Bell Communications Research; organization established by the AT&T divestiture, representing and funded by the BOCs and RBOCs, for the
purposes of establishing telephone network standards
and interfaces; includes much of former Bell Labs.
BERT - Bit Error Rate Test. A test conducted by
transmitting a known, pattern of bits (commonly 63,
511, or 2047 bits in tength), comparing the pattern
received with the pattern transmitted, and counting the
number of bits received in error. Also see bit error rate.
Contrast with BLERT.

BIT ERROR RATE (BER) - In data communications
testing, the ratio between the total number of bits
transmitted in a given message and the number of bits
in that message received in error; a measure of the
quality of a data transmission.
BITS PER SECOND (BIT/S) - Basic unit of measure for
serial data transmission capacity; Kbit/s, or kilobits, for
thousands of bits per second; Mbit/s, or megabit/s, for
millions of bits per second, etc.
BOC - Bell Operating Company. One of 22 local telephone companies spun off from AT&T as a result of
divestiture. The 22 operating companies are divided
into seven regions and are held by seven RBHCs
(Regional Bell Holding Company).
BROADBAND - Referring or pertaining to an analog
circuit that provides more bandwidth than a voice grade
telephone line, i.e., a circuit that operates at a frequency
of 20 kHz or greater. Broadband channels are used for
high-speed voice and data communications, radio and
television broadcasting, some local area data networks,
and many other services. Also called wideband.
BUFFER - A storage medium or device used for holding
one or more blocks of data to compensate for.a difference in rate of data flow, ortime of occurrence of events,
when transmitting data from one device to another.

BINARY CODE - Representation of quantities expressed
in the base-2 number system.

9-86

0194 - rev.

BUS - 1) Physical transmission path or channel. Typically an electrical connection, with one or more conductors, wherein all attached devices receive all transmissions at the same time. Local network topo logy, such as
used in Ethernet and the token bus, where all network
nodes listen to all transmissions, selecting certain ones
based on address identification. Involves some type of
contention-control mechanism for accessing the bus
transmission medium. In data communications, a network topology in which stations are arranged along a
linear medium (e.g., a length of cable). 2) In computer
architecture, a path over which information travels
internally among various components of a system.
BYTE-Groupofbits handled as a logical unit; usually 8.

CABLE - Assembly of one or more conductors within a
protective sheath; constructed to allow the use of conductors separately or in groups.
CALL PROGRESS DETECTION (CPO) - A technique
for monitoring the connection status during initiation of
a telephone call by detecting presence and/or duty
cycle of call progress signaling tones such as dial-tone
or busy signals commonly used in the telephone network.
CALL PROGRESS TONES - Audible signals returned
to the station user by the switching equipment to indicate the status of a call; dial tones and busy signals are
common examples.
CAP MODEM - Carrierless amplitude phase modem.
CCITT - Co mite Consultatif International de Telephonie
et de Telegraphie. Telegraph and Telephone Consultive Committee. An advisory committee to the International Telecommunications Union (ITU) whose recommendations covering telephony and telegraphy have
international influence among telecommunications engineers, manufacturers, and administrators.
CDPD - Cellular digital packet data 19.2 Kbitls wireless
modem.

CHANNEL SERVICE UNIT (CSU) - A component of
customer premises equipment (CPE) used to terminate
a digital circuit, such as DDS or T1 at the customer site;
performs certain line-conditioning functions, ensures
network compliance per FCC rules and responds to
loopback commands from central office; also, ensures
proper ones density in transmitted bit stream and performs bipolar violation correction.
CHANNEL, VOICE GRADE - Channel suitable for
transmission of speech, analog data, or facsimile, generally with a frequency range of about 300 to 3000 Hz.
CHARACTER - Letter, figure, number, punctuation, or
other symbol contained in the message. In data communication, common characters are defined by 7- or 8bit binary codes, such as ASCII.
CHIP - A commonly used term which refers to an
integrated ciruit.
CIRCUIT, TWO-WIRE-Acircuitformedbytwoconductors insulated from each othe r that can be used as either
a one-way or two-way transmission path.
CLOCK - In logiC or transmission, repetitive, precisely
timed signal used to control a synchronous process.
CMOS - Complementary Metal-Oxide Semiconductor.
A type of transistor, typicailly used in low-power integrated circuits.
COAXIAL CABLE - Cable conSisting of an outer
conductor surrounding an inner conductor, with a layer
of insulating material in between. Such cable can carry
a much higher bandwidth than a wire pair.
CPE - Customer Premises Equipment
CROSSPOINT - 1) Switching array element in an
exchange that can be mechanical or electronic. 2) Twostate semiconductor switching device having a low
transmission system impedance in one state and a very
high one in the other.
CROSSTALK - Interference or an unwanted signal
from one transmission circuit detected on another,
usually an adjacent circuit.

CENTRAL OFFICE (CO) - See Exchange
CHANNEL BANK - Equipment typically used in a
telephone central office that performs multiplexing of
lower speed, digital channels into a higher speed composite channel. The channel bank also detects and
transmits signaling information for each channel, and
transmits framing information so that time slots allocated to each channel can be identified by the receiver.

0194 - rev.

CYCLIC REDUNDANCY CHECK (CRC) - A powerful
error detection technique. Using a polynomial, a series
of two 8-bit block check characters are generated that
represent the entire block of data. The block check
characters are incorporated into the transmission frame,
then checked at the receiving end.

9-87

I

DIAL-UP - The process of, or the equipment or facilities
involved in, establishing a temporary connection via the
switched telephone network.

II
DATA COMMUNICATIONS EQUIPMENT (DCE) Equipment that performs the functions required to connect data terminal equipment (DTE) to the data circuit.
In a communications link, equipment that is either part
of the network, an access-point to the network, a
network node, or equipment at which a network circuit
terminates; in the case of an RS-232C connection, the
modem is usually regarded as DCE, while the user
device is DTE, or data terminal equipment; in a CCITT
X.2S connection, the network access and packetswitching node is viewed as the DCE.
DATA LINK - Any serial data communications transmission path, generally between two adjacent nodes or
devices and without any intermediate switching nodes.
DATA SET - A synonym for modem used by AT&T and
a few other vendors.
DATA SERVICE UNIT (DSU) - A device that replaces
a modem on a Digital Data Service (DDS) line. The data
service unit regenerates the digital signals fortransmission over digital facilities.
DATA TERMINAL EQUIPMENT (DTE) - Equipment
which is attached to a network to send or receive data,
generally end-user devices, such as terminals and
computers, that connect to DCE, which either generate
or receive the data carried by the network; in RS-232C
connections, designation as either DTE or DCE determines signaling role in handshaking; in a CCITT X.25
i~erface, the device or equipment that manages the
interface at the user premises; see DCE.
dB - Decibel; unit for measuring relative strength of a
signal parameter such as power, voltage, etc. The
number of decibels is twenty times the logarithm (base
10) of the ratio of the power of two signals, or ratio of the
power of one signal to a reference level.
dBm - Decibels relative to one milliwatt.
DDS - 1) Digital Data Service. A digital transmission
service supporting speeds upto 56 KbiVs. 2) Dataphone
Digital Service. An AT&T leased line service offering
digital transmission at speeds ranging from 2400 to
56 Kbitls.
DECT - Digital European cordless telephone.

DIAL TONE (DT) - Signal sent to an operator or subscriber indicating that the switch is ready to receive dial
pulses.
DIGITAL - Referring to communications procedures,
techniques, and equipment whereby information is encoded as either binary "1" or "0"; the representation of
information in discrete binary form, discontinuous in
time, as opposed to the analog representation of information in variable, but continuous, waveforms.
DIGITAL LOOPBACK - A technique for testing the
digital processing circuitry of a communications device.
It may be initiated locally, or remotely via a telecommunications circuit. The device being tested will echo back
a received test message, after first decoding and then
re-encoding it, the results of which are compared with
the original message.
DIGITAL SIGNAL - Discrete or discontinuous signal;
one whose various states are discrete intervals apart.
DIP - Dual-In-Line Package. Method of packaging electroniccomponents for mounting on printed circuit boards.
DISTORTION - The modification of the waveform or
shape of a signal caused by outside interference or by
imperfections of the transmission system. Mostforms of
distortion are the result of the characteristics of the
transmission system to the different frequency components.
DOTTING, DOUBLE DOTTING, PATTERN - The term
"dotting" was coined by Bell to describe a data pattern
consisting of alternate marks and spaces. The CCITT
uses the full description of "alternating binary ones and
zeros" on first needing this idea in a recommendation,
but then abbreviate this to "reversals." By extrapolation,
"double dotting" has come into use to refer to the data
pattern termed "S1"which is used in V.22bis to indicate
2400 biVs capability. The full description is "unscrambled
double dibit 00 and 11 at 1200 bitls for 100 ± 3 ms."
DS-1 - Digital Signal level 1 ; telephony term describing
a digital transmission format in which 24 voice channels
are multiplexed into one 1.544 Mbit/s (U.S.) T1 digital
channel.

08-3 - Digital Signal level 3; telephony term describing
the 44.736 Mbitls digital signal carried on a T3 facility.

DJCT - Digital Japanese cordless telephone.
DELAY DISTORTION - The change in a signal from the
transmitting end to the receiving end resulting from the
tendency of some frequency components within a
channel to take longer to be propagated than others.

DSP RTOS - Digital signal processing real time ope rating system.

9-88

0194 - rev.

DTMF - Dualtone Multifrequency (DTMF) - Basis for
operation of most push button telephone sets. An inband signalling technique in which a matrix combination
of two frequencies, each from a group of four, are used
to transmit numerical address information; it encodes
16 possible combinations of tone pairs using two groups
of four tones each. The two groups of four frequencies
are 697 Hz, 770 Hz, 852 Hz, and 941 Hz, and 1209 Hz,
1336 Hz, 1477 Hz, and 1633 Hz. DTMF is used primary
for call initiation in GSTN telephone applications.

II
ECHO - The distortion created when a transmitted
signal is reflected back to the originating station.
ECHO CANCELLER - A devise used to reduce or
eliminate echo. It operates by placing a signal that is
equal and opposite to the echo signal on the return
transmission path.
ECHO SUPPRESSOR - A mechanism used to suppress echoes on long-distance analog connections.
The device suppresses the transmission path opposite
in directiontothe one being used. Thisfeature, although
necessary for voice transmission, often interferes with
data transmission.
EIA - Electronic Industries Association
EIA INTERFACE, EIA232D, RS 232C - The logical,
electrical and physical characteristics of the connection
between a DTE and a modem is set out in EIA specification 232D. Previously this has been known as RS232C.
The logical characteristics are essentially similar to
those specified in CCITT recommendation V .24 and the
electrical characteristics to those in V.28.
ELECTROMAGNETIC INTERFERENCE (EMI) Radiation leakage outside a transmission medium that
results mainly from the use of high-frequency wave
energy and signal modulation. EMI can be reduced by
appropriate shielding.
EMI - See Electromagnetic Interference.
ENDEC - Encoder/Decoder. The 10 Mbitls Manchester
encoder and decoder circuit for Ethernet signalling.
ENVELOPE DELAY - An analog line impairment
ipvolving a variation of signal delay with frequency
across the data channel bandwidth.
EQUALIZATION - The introduction of components to
an analog circuit by a modem to compensate for the
attenuation (signal loss) variation and delay distortion
with frequency (attenuation equalization) and propaga0194 - rev.

tion time variations with frequency (delay equalization).
Generally, the higher the transmission rate, the greater
the need for equalization.
ERROR - In data communications, any unwanted
change in the original contents of a transmission.
ERROR BURST - A concentration
short period of time as compared
incidence of errors. Retransmission
rection procedure in the event of an

of errors within a
with the average
is the normal corerror burst.

ERROR CONTROL - A process of handling errors,
which includes the detection and in some cases, the
correction of errors.
ETHERNET - A media-access specification for local
area networks, developed by IEEE and known as the
IEEE 802.3 spec.
EXCHANGE - Assembly of equipment in a communications system that controls the connection of incoming
and outgoing lines, and includes the necessary signaling and supervisory functions. Different exchanges, or
switches, can be costed to perform different functions,
e.g., Local exchange, trunk exchange, etc. See Class of
Exchange. Also known as Central Office (U.S. Term).
EXCHANGE, PRIVATE AUTOMATIC BRANCH
(PABX) - Private automatic telephone exchange that
provides for the switching of calls internally and to and
from the public telephone network.
EXCHANGE, PRIVATE BRANCH (PBX) - Private,
manually operated telephone exchange that provides
private telephone service to an organization and that
allows calls to be transmitted to or from the public
telephone network.
EXCHANGE AREA - Area containing subscribers
served by a local exchange.

II
FILTER - Circuit designed to transmit signals of frequencies within one or more frequency bands and to
attenuate signals of other frequencies.
FIRMWARE - Permanent or semi-permanent control
coding implemented at a micro-instruction level for an
application program, instruction set, operating routine,
or similar user-oriented function.
FLOW CONTROL - The use of buffering and other
mechanisms, such as controls that turn a device on and
off, to prevent data loss during transmission.

9-89

I

FOUR-WIRE CIRCUIT OR CHANNEL - A circuit containing two pairs of wire (or their logical equivalent) for
simultaneous (Le., full-duplex) two-way transmission.
Contrast with two-wire channel.
FRAME - 1) A group of bits sent serially over a communications channel; generally a logical transmission unit
sent between data-link-layer entities that contain its
own control information for addressing and error checking. 2) A piece of equipment in a common carrier office
where physical cross connections are made between
circuits.
FRAMING - Control procedure used with multiplexed
digital channels such as T1 carriers, whereby bits are
inserted so the receiver can identify the time slots
allocated to each subchannel. Framing bits can also
carry alarm signals indicating specific alarm conditions.
FREQUENCY - Rate at which an event occurs, measured in hertz, kilohertz, megahertz, etc.
FREQUENCY BANDS - Frequency bands are defined
arbitrarily as follows:
Range (MHz)

prevent the high-band data signal from interfering with
the operation of billing apparatus in certain countries.
GSTN - General Switched Telephone Network

HALF-DUPLEX - Pertaining to the capability to send
and receive but not simultaneously.
HANDSHAKE - An eXChange of control sequences
between two locations to set up the correct parameters
for transmission.
HDLC - High-level Data Link Control. Bit-oriented communication protocol developed by the ISO (International Standards Organization).
HARMONIC DISTORTION - A waveform distortion,
usually caused by the nonlinear frequency response of
a transmission.
HERTZ (Hz) - A measure of electromagnetic frequency;
one hertz is equal to one cycle per second.

Name
HF - High Frequency.

0.03-0.3
0.3-3.0
3-30
30-300
300-3000
3000-30,000

Low frequency (LF)
Medium frequency (MF)
High frequency (HF)
Very High frequency (VHF)
Ultra high frequency (UHF)
Super high frequency (SHF) (micro
wave)
30,000-300,000 Extremely
high
frequency
(EH F) (millimeterwave)
FSK - Frequency Shift Keying. A method of modulation
that uses two different frequencies, usually phase
continous, to distinguish between a mark (digital 1) and
a space (digital 0) when transmitting on an analog line.
Used in modems operating at 1200 bit/s or slower.
FULL-DUPLEX - Pertaining to the capability to send
and receive simultaneously.

GAIN - Denotes an increase in signal power in transmission from one point to another, usually expressed in dB.
GUARD TONE -In CCITT recommendations V.22 and
V.22bis, guard tones may optionally be transmitted
along with the data signal from the answering modem.
A single frequency of either 1800 or 550 Hz is used and
the data signal power must be reduced to keep the
overall energy level the same as for transmission without guard tone. The purpose of the guard tone is to

HIGH FREQUENCY (HF) - Portion of the electromagnetic spectrum, typically used in short-wave radio applications. Frequencies in the 3 to 30 MHz range.
Hz - See Hertz.

a

IEEE -Institute of Electrical and Electronics Engineers.
IEEE 802.11 - Wireless local area network IEEE standard.
INITIALIZE - To set counters, switches, addresses, or
contents of storage to zero orother starting values at the
beginning of, or at prescribed points in, the operation of
a computer routine.
INTERFACE - A hardware and/or software link between
two devices. The interface defines all signal characteristics and other specifications for physical interconnection of the devices.
INTEROFFICE TRUNK - Direct trunk between local
central offices (Class 5 offices), or between Class 2, 3,
or 4 offices; also called intertoll trunk.

1854 - Interim standard 54 - half analog/digital, secondgeneration North American standard.

9-90

0194 - rev.

ISO - International Organization for Standardization.
ITU - International Telecommunications Union. The
parent organization of the CCIIT.

II
JITIER - Slight movement of a transmission signal in
time or phase that can introduce errors and loss of
synchronization for high-speed synchronous communications. See Phase jitter.

KEY PULSING (KP) - Manual method of sending
numerical and other signals by the operation of
nonlocking pushkeys. Also called Key Sending.
KEY SERVICE UNIT (KSU) - Main operating unit of a
key telephone system.
KEY TELEPHONE SYSTEM (KTS) - When more than
one telephone line per set is required, pushbutton or key
telephone systems offer flexibility and a wide variety of
uses, e.g., pickup of several exchange lines, PABX
station lines, private lines, and intercommunicating
lines. Features of the system include pickup and holding intercommunications, visual and audible signals,
cutoff, exclusion, and signaling.
KP - Key Pulse (signaling unlocking signal). See Key
Pulsing.
kHz - Kilohertz, kilocycles per second.

LINE HIT - A transient disturbance causing a detectable
error on a communications line.
LINE-LOADING - The process of installing loading coils
in series with each conductor on a transmission line.
Usually 88 milliHenry coils installed at 6,000 foot intervals.
LINK - 1) A physical circuit between two points. 2) A
logical circuit between two users of a packet switched
(or other) network permitting them to communicate
(although different physical paths may be used).
LINK LAYER - The logical entity in the OSI model
concerned with transmission of data between adjacent
network nodes. It is the second layer processing in the
OSI model, between the physical and the network
layers.
LOADING COILS - An inductance coil installed at
regular intervals along a transmiSSion line. Used to
improve the quality of voice grade circuits.
LOCAL EXCHANGE - Exchange in which subscribers'
lines terminate. The exchange has access to other
exchanges and to national trunk networks. Also called
local central office, end office.
LOCAL LOOP - The part of a communications circuit
between the subscriber's equipment and the equipment in the local exchange .

..

KTU - Key Telephone Unit. See Key Service Unit.

LOCAL TRUNK - Trunks between local exchanges.

LEASED LINE - A line rented exclusively to one customer for voice or data communications; dedicated
circuit, typically supplied by the telephone company or
transmission authority, that permanently connects two
or more user locations and is for the sole use of the
subscriber. Such circuits are generally voice grade in
capacity and in range of frequencies supported, are
typically analog, are usedforvoiceordata, can be pointto-point, or multipoint, and can be enhanced with line
conditioning. Also called private line, tie line, or dedicated facility.
LED - Light-Emitting Diode.
LIGHT-EMITTING DIODE (LED) - Semiconductor junction diode that emits radiant energy and is used as a
light source for fiber optic communications, particularly
for short-haul links.

0194 - rev.

LIMITED-DISTANCE MODEM - A short-haul modem
or line driver that operates over a limited distance.
Some limited-distance modems operate at higher
speeds than modems that are designed for use over
analog telephone facilities, since line conditions can be
better controlled.

LOSS (TRANSMISSION) - Decrease in energy of signal power in transmission along a circuit due to the
resistance or impedance of the circuit or equipment.

II
MAC - Media access controller - a protocol controller IC
that implements the 802.3 CSMAICO protocol.
MARK - The signal (communications channel state)
corresponding to a binary one. The marking condition
exists when current flows (current-loop channel) or
when the voltage is more negative than -3 volts (EIA
RS-232 Channel).

9-91

I

MATRIX - In switch technology, that portion of the
switch architecture where input leads and output leads
meet, any pair of which may be connected to establish
a through circuit. Also called switching matrix.
MAU - Media attachment unit - a transceiver that
connects to the AUI port on an Ethernet interface card.
Mbit/s - Megabits per second.
MEGAHERTZ (MHz) - A unit of frequency equal to one
million cycles per second.

m
NAK - "Negative acknowledge" character. A transmission control character that indicates a block of data was
received incorrectly.
NOISE - Undesirable energy in a communications path,
which interferes with the reception or processing of a
signal.
ns - Nanosecond; also nsec. One-billionth of a second.

MF - 1) Medium Frequency. 2) Multifrequency. See
Dualtone Multifrequency Signaling (DTMF).
MODEM - A contraction of modulate and demodulate;
a conversion device installed in pairs at each end of an
analog communications line. The modem at the transmitting end modulates digital signals received locally
from a computerorterminal;the modem at the receiving
end demodulates the incoming signal, converting it
back to its original (Le., digital) format, and passes it to
the destination business machine.
MODULATION - The application of information onto a
carrier signal by varying one or more of the signal's
basic characteristics (frequency, amplitude, or phase);
the conversion of a signal from its original (e.g., digital)
format to analog format.
MODULATION, PULSE CODE (PCM) - Digital transmission technique that involves sampling of an analog
information signal at regular time intervals and coding
the measured amplitude value into a series of binary
vafues, which are transmitted by modulation of a pulsed,
or intermittent, carrier. A common method of speech
digitizing using a-bit code words, or samples, and a
sampling rate of a kHz.

OFF HOOK - By analogy with the normal household
telephone, a modem is off-hook when it is using the
telephone line to make a call. This is similar to raising
the telephone handset, or taking it off the hook. Going
off-hook is also known as "seizing the line."
ON-HOOK - By analogy with the normal household
telephone, a modem is on-hoOk when it is not using the
telephone line. As with a telephone where the handset
is on the hook, the line may be used by other equipment
to make a call. Going on-hook is also known as "dropping the line."
OSI - Open Systems Interconnection. Referring to the
reference model, OSI is a logical structure for network
operations standardized within the ISO; a seven-layer
network architecture being used for the definition of
network protocol standards to enable any OSI-compatible computer or device to communicate with any other
OSI-compliant computer or device for a meaningful
exchange of information.
OVERFLOW - Excess traffic on a particular route,
which is offered to another (alternate) route.

ms - Millisecond. One-thousandth of a second.
MULTIPLEXER - Device that enables more than one
signal to be sent simultaneously over one physical
channel.
MULTIPLEXING - Division of a transmission facility into
two or more channels either by splitting the frequency
band transmitted by the channel into narrower bands,
each of which is used to constitute a distinct channel
(frequency-division multiplex), or by allotting this common channel to several different information channels,
one at a time (time-division multiplexing).

PABX - Private Automatic Branch Exchange. See
Exchange, Private Automatic Branch (PABX).
PACKET - A group of binary digits including data and
call control signals that is switched as a composite
whole. The data, call control signals, and error control
information are arranged in a specified format.
PBX - Private Branch Exchange. See Exchange,
Private Branch.

MUX - See Multiplexer.
PCMCIA - Personal Computer Memory Card International Association. Type 1: 3.3 mm thick
Type 2: 5.0 mm thick
9-92

0194 - rev.

PHASE JITTER - In telephony, the measurement, in
degrees out of phase, that an analog signal deviates
from the referenced phase of the main data-carrying
signal. Often caused by alternating current components
in a telecommunications network; or: a random distortion of signal lengths caused by the rapid fluctuation of
the frequency of the transmitted signal. Phase jitter
interferes with interpretation of information by changing
the timing.

REPEATER - 1) In analog transmission, equipment that
receives a pulse train, amplifies it and retimes it for
retransmission. 2) In digital transmission, equipment
that receives a pulse train, reconstructs it, retimes it,
and often then amplifies the signal for retransmission.
3) In fiber optics, a device that decodes a low-power
light signal, converts it to electrical energy, and then
retransmits it via an LED or laser-generating light source.
See also Regenerative Repeater.

PHASE MODULATION - One of three ways of modifying a sine wave signal to make it carry information. The
sine wave or "carrier" has its phase changed in accordance with the information to be transmitted.

REVERSE CHANNEL - A simultaneous low speed data
path in the reverse direction over a half-duplex facility.
Normally, it is used for positive/negative
acknowledgements of previously received data blocks.

PROPAGATION DELAY - The period between the time
when a signal is placed on a circuit and when it is
recognized and acknowledged at the other end. Propagation delay is of great importance in satellite channels
because of the great distances involved.

RINGER EQUIVALENCE NUMBER - This is a number
that the FCC assigns to approved telecom equipment
that measures how much load it places on the network
during ringing. In the U.S.A., you can connect telephones, modems, FAX machines etc. In parallel to the
same telephone line only as long as the sum of their
ringer equivalence numbers is less than five. Most
countries have a similar regulating system in force,
although the methods used to arrive at the numbervary
widely.

PROTOCOL - A set of procedures for establishing and
controlling communications. Examples include BSC,
SDLC, X.25, V.42, V.42bis, MNP, V.22bis handshake,
etc.
PSK - Phase Shift Keying. A method of modulation that
uses the differences in phase angle between two symbols to encode information. A reference oscillator determines the phase angle change of the incoming signal,
which in turn determines which bit or dibit is being
transmitted. DPSK (Differential Phase Shift Keying) is a
variation of PSK which changes the phase relative to
the previous phase.

RINGING SIGNAL - Any AC or DC signal transmitted
over a line or trunk for the purpose of alerting a party at
the distant end of an incoming call. The signal can
operate a visual or sound-producing device.

PULSE CODE MODULATION (PCM) - A method of
transmitting information by varying the characteristics
of a sequence of pulses, in terms of amplitude, duration,
phase, or number. Used to convert an analog signal into
a digital bit stream for transmission.

RSSI- Receive signal strength indicator (i.e., go to gain
control in AM signal).

m

REGENERATIVE REPEATER -1) Repeater utilized in
telegraph applications to retime and retransmit the
received signal impulses and restore them to their
original strength. These repeaters are speed- and codesensitive and are intended for use with standard telegraph speeds and codes. 2) Repeater used in PCM or
digital circuits which detects, retimes, and reconstructs
the bits transmitted.
REGENERATOR - Equ ipment that takes a digital signal
that has been distorted by transmission and produces
from it a new signal in which the shape, timing, and
amplitude of the pulses are that same as those of the
original before distortion.
0194 - rev.

RINGING TONE - Tone received by the calling telephone indicating that the called telephone is being rung.
Also called Ringback.

SCRAMBLER/DESCRAMBLER - A scrambler function uses a defined method for modifying a data stream,
in order to make the altered data stream appear random. A descrambler reverses the effect of the scrambler using the previously defined method to recover the
original data stream. Most often used for data encryption, or to avoid transmitting repetitive data patters that
can adversely affect data recovery in modems and
other data transmission equipment.
SDLC - Synchronous Data Link Control. IBM bit oriented protocol providing for half-duplex transmission;
associated with IBM's System Network Architecture
(SNA).
SHIELDED PAIR - Two insulated wires in a cable
wrapped with metallic braid or foil to prevent interference and provide noise-free transmission.

9-93

I

SIGNAL·TO·NOISE RATIO - The relative power of a
signal as compared to the power of noise on a line. As
the ratio decreases, it becomes more difficult to distinguish between information and interference.

and thus is faster and more efficient than asynchronous
transmission. The timing is achieved by transmitting
sync characters prior to data or by extracting timing
information from the carrier or reference.

SIMPLEX - Pertaining to the capability to move in one
direction only. Contrast with half-duplex and full-duplex.

SYNCHRONOUS NETWORK - Network in which all
the communications links are synchronized to a common clock.

SIGNALING - Process by which a caller or equipment
on the transmitting end of a line informs a particular
party or equipment at the receiving end that a message
is to be communicated.
SMART IF - Microcontroller bus interface for program
control of RF components.
SONET - Synchronous optical network.
SPACE - OppOSite signal condition to a "mark." The
signal (communications channnel state) corresponding
to a binary zero. In an EIA RS-232 channel, the spacing
condition exists when the voltage is more positive than
+3 volts.

SYNCHRONOUS TRANSMISSION - Transmission
process where the information and control characters
are sent at regular, clocked intervals so that the sending
and receiving terminals are operating continuously in
step with each other.

II
T-CARRIER - A time-division multiplexed, digital transmission facility, operating at an aggregate data rate of
1.544 Mbitls and above. T-carrier is a peM system
using 64 Kbitls for a voice channel.
T1 - A digital facility used to transmit a DS-1 formatted
digital signal at 1.544 Mbit/s; the equivalent of 24 voice
channels.

SS - Spread spectrum.
ST - Start (signal to indicate end of outpulsing).

T1 CIT2IT3/T4 - Digital carrier facilities used to transmit
signals at 3.152M, 6.312M, 44.736M, 274.176 Mbitls,
respectively.

STS1 - 51.84 Mbitls.
START·STOP (SIGNALING) - Signaling in which each
group of code elements corresponding to a character is
preceded by a start signal that serves to prepare the
receiving mechanism for the reception and registration
of character, and is followed by a stop signal that serves
to-6ring the receiving mechanism to rest in preparation
for the reception of the next character. Also known as
asynchronous transmission.

T3 - A digital carrier facility used to transmit a DS-3
formatted digital carrier signal at 44.736 Mbitls; the
equivalent of 672 voice channels.
TACS - Total access communications system. (U.K.
analog cellular standard).
TDMA - Time division multiple access.

STOP·BIT - In asynchronous transmission, the quiescent state following the transmission of a character;
usually 1-, or 2-bit times long.
STOP ELEMENT - Last bit of a character in asynchronous serial transmission, used to ensure recognition of
the next start element.
SUBSCRIBER LINE - Telephone line connecting the
exchange to the subscriber's station. Also called
(U.S. term) access line and subscriber loop.

TCVCXO - Temperature-compensated, voltage - controlled crystal oscillator.
TOUCH-TONE - An AT&T trademark fordualtone multifrequency signaling equipment. Use of tones Simplifies the switching system deSign and greatly expands
the potential for adding features to telephone systems.
It also speeds up the dialing operation for a person
making a call.

SW56 - Switched 56 Kbit/s digital transmission.

TRANSCEIVER - Device that can transmit and receive
traffic.

SYNCHRONOUS - Having a constant time interval
between successive bits, characters, or eventS. Synchronous transmission doesn't use non-information bits
(such as the start and stop bits in asynchronous transmission) to identify the beginning and end orcharacters,

TRUNK - Transmission paths that are used to interconnect exchanges in the main telephone network, two
switching centers, or a switching center and a distribution point, such as a telephone exchange line that
terminates in a PABX network.

9-94

0194 - rev.

TTL - Transistor-Transistor Logic. Digital logic family
having common electrical characteristics.
TURNAROUND TIME - The time required to reverse
the direction of transmission, e.g; to change from receive mode to transmit mode in order to acknowledge
on a half-duplex line. When individual blocks are acknowledged, as is required in certain protocols (e.g.,
IBM BSC) the turnaround time has a major effect on
throughput, particularly if the propagation delay is
lengthy, such as on a satellite channel.
TWO-WIRE CIRCUIT - Circuit formed of two conductors insulated from each other, providing a send and
return path. Signals may pass in one or both directions.

VIDEOTEX - An interactive data communications application designed to allow unsophisticated users to converse with remote databases, enter data for transactions, and retrieve textual and graphics information for
display on subscriber television sets or low-cost terminals.

V.11 - Description of a balanced physical level interchange circuit (balanced means two wires between the
transmitter and receiver with both wires' signals constant with respect to Earth).
V.1S - Description of use of acoustic couplers for data
transmission.
V.16 - Description of the transmission of ECG (electrocardiogram) signals on the telephone channel.
V.19 - Description of one-way parallel transmission
modems using push-button telephone sets.
V.20 - Description of one-way parallel transmission
modems, excluding push-button telephone sets.
V.22 - Operating at 1.2 Kbitls, encodes two consecutive
bit (dibits); the dibits are encoded as a change relative
to the previous signal element.
V.22bis - Operating at 2.4 Kbitls, encodes four consecutive bits (quadbits); the first two bits are encoded
relative to the quadrant of the previous signal element,
the last two bits are associated with the point in new
quadrant.

VSLI - Very Large Scale Integration.
V SERIES RECOMMENDATIONS(CCITT V.xx Standards)
Also see Voiceband Modem Standards chart on
page 9-12.
V.1 - Definitions of key terms for binary symbol notation,
such as binary 0 = space, binary 1 = mark.
V.2 (1) - Specification of power levels for data transmission over telephone line.
V.4 - Definition of the order of bit transmission, the use
of a parity bit, and the use of start/stop bits for asynchronous transmission.
V.S - Specification of data-signaling rates (bit/s) for
synchronous transmission in the switched telephone
network.

V.24 - Definition of the interchange circuit pins between
DTEs (data terminal equipment) and DCEs (data circuit-terminating equipment).
V.2S - (2) - Specifications for automatic-answering
equipment.
V.2Sbis - (2) - Specifications for automatic-answering
equipment.
V.28 - Description of unbalanced interchange circuits
operating below 20 Kbit/s.
V.29 - Operating at9.6 Kbitls, encodes four consecutive
bits (quadbits); the first bit determines the amplitude,
the last three bits use the encoding scheme of V.27.
V.29 - Operating at 4.8 Kbit/s, encodes two consecutive
bits (dibits); amplitude is constant and phase changes
are the same as V.26.

V.6 - Specification of data signaling rates (bit/s) for
synchronous transmission on leased telephone circuits.

V.31 - Description of low-speed interchange circuits (up
to 75 Bit/s).

V.7 - Definitions of other key terms used in the V-series
recommendations.

V.31bis - Description of low-speed interchange circuits
(up to 1.2 Kbitls).

V.10 - Description of an unbalanced physical level
interchange circuit (unbalanced means one active wire
between transmitter and receiver with ground providing
the return).

V.32 - Operating at9.6 Kbit/s, encodesfourconsecutive
bits (quadbits); the bits are mapped to a QAM signal.

0194 - rev.

9-95

I

V.32 - Operating at 9.6 KbiVs with Trellis-coded modulation (TeM), encodes four consecutive bits, two of
which are used to generate a fifth bit; the bits are
mapped to a QAM signal.
V.32 - Operating at 4.8 Kbitls, encodes two consecutive
bits (dibits), which are mapped to a QAM signal.
V.42 - Defines a method of error control.
V.42bls - Defines a method of data compression.
Note: In the United States, EIA RS-496 specifies these
measurements and RS-366 specifies these procedures.
VOICE-GRADE CHANNEL - a channel with a frequency range from 300 to 3000 Hz and suitable for the
transmission of speech, data, or facsimile.

WORD - A group of bits handled as a logical unit;
usually 16.

9-96

0194 - rev.

Voiceband Modem Standards
Data
Rate
(Bitts)

Full-or
HalfDuplex

V.21

300

Full

Frequency
Division

1080, & 1750

Frequency
Shift

V.22

1200

Full

Frequency
Division

1200, & 2400

Phase
Shift

V.22

600

Full

Frequency
Division

1200, &2400

V.22bis

2400

Full

Frequency
Division

CCITT
Standard

Channel
Separation

Carrier
Frequency
(Hz)

Modulation
Method

Bits
Encoded

Synchronous
or
Asynchronous

Back
Channel

GSTN

300

1:1

Either

ND

Yes

600

2:1

Either

ND

Yes

Phase
Shift

600

1:1

Either

ND

Yes

1200, & 2400

QuadratureAmplitude
Modulation

600

4:1

Either

ND

600

N/A

Either

1200

N/A

Either

V.23

600(1)

Half

N1A

1300, & 1700

Frequency
Modulation

V.23

1200 (1)

Half

N/A

1300, &2100

Frequency
Modulation

Modulation
Rate
(Baud)

Leased
Lines

Equalization

Scrambler

No

ND

NO

Point-to-Point
2-Wire

Fixed

Yes

Point-ta-Point
2-Wire

Fixed

Yes

Yes

Point-to-Point
2-Wire

Fixed/
Adaptive

Yes

Yes

Yes

No

ND

ND

Yes

Yes

No

ND

ND

No

Point-to-Point
MuHipoint
4-Wlre

ND

ND

Full

4-Wire

1800

Phase
Shift

2400

Half

N/A

1800

Phase
Shift

1200

2:1

Synchronous

Yes

Yes

No

Fixed

ND

V.26bls

1200

Half

N1A

1800

Phase
Shift

1200

1:1

Synchronous

Yes

Yes

No

Fixed

ND

V.26ter

2400

Either

Echo
Cancellation

1800

Phase
Shift

1200

2:1

Either

ND

Yes

Point·to·Point
2-Wire

Either

Yes

V.2S

2400

V.26bis

1200

2:1

Synchronous

Yes

V.26ter

1200

Either

Echo
Cancellation

1800

Phase
Shift

1200

1:1

Either

ND

Yes

Poinl-to-Point
2-Wire

Either

Yes

V.27

4800

Either

ND (3)

1800

Phase
Shift

1600

3:1

Synchronous

Yes

No

Yes (3)

Manual

Yes

V.27bls

4800

Either

4-Wire(4)

1800

Phase
Shift

1600

3:1

Synchronous

Yes

No

2-Wire,
4-Wire

Adaptive

Yes

V.27bis

2400

Either

4-Wire(4)

1800

Phase
Shift

1200

2:1

Synchronous

Yes

No

2-Wire,
4-Wire

Adaptive

Yes

V.27ter

4800

Half

None

1800

Phase
Shift

1800

3:1

Synchronous

Yes

Yes

No

Adaptive

Yes

V.27ter

2400

Half

None

1800

Phase
Shift

1200

2:1

Synchronous

Yes

Yes

No

Adaptive

Yes

1700

Quadrature·
Amplitude
Modulation

2400

4:1

No

Polnt·ta-Point
4-Wire

Adaptive

Yes

V.29

9600

Either

~ 4-Wire

Synchronous

No

V.29

7200

Either

4-Wire

1700

Phase
Shift (5)

2400

3:1

Synchronous

ND

No

Point·to·Point
4-Wire

Adaptive

Yes

V.29

4800

Either

4-Wire

1700

Phase
Shift (5)

2400

2:1

Synchronous

ND

No

Point-ta-Point
4-Wire

Adaptive

Yes

V.32

9600

Full

Echo
Cancellation

1800

QuadratureAmplitude
Modulation

2400

4:1

Synchronous

ND

Yes

Point·to·Point
2-Wire

Adaptive

Yes

1800

TrellisCoded
Modulation

2400

6:1

Synchronous

ND

Yes

Point·to·Point
2-Wire

Adaptive

Yes

2400

4:1

Synchronous

ND

Yes

Point-to-Point
2-Wire

Adaptive

Yes

Synchronous

ND

Yes

Point-ta-Point
2-Wire

Adaptive

Yes

V.32bls

14400

Full

Echo
Cancellation

V.32

9600

Full

Echo
Cancellation

1800

QuadratureAmplitude
Modulation

V.32

4800

Full

Echo
Cancellation

1800

auadratureAmplitude
Modulation

2400

2:1

V.33

14400

Half

Synchronous

ND

Yes

Adaptive

Yes

V.34

28600

Full

Echo
Cancellation

1800

TrellisCoded
Modulation

2400

12:1

Synchronous

ND

Yes

Point-ta-Point
2-Wire

ND

Yes

No

Filled

No

Adaptive

Yes

Bell (U.S.) Standard

103

300

Full

Frequency
DiviSion

2225&
1270(m)
2025 &
1070(6)

Frequency
Shift

300

1:1

Either

No

Yes

201

2400

Half

None

1800

Phase
Shift

1200

2:1

Synchronous

No

Yes

Point·to·Point
2-Wire

Yes

Point·la-Point
2-Wlre
Adaptive

Yes

Fixed

Yes

202

1200

Half

None

1200 & 2200

FSK

1600

600

208

4800

Half

None

1800

Quadrature·
Amplitude
Modulation

212

1200

Full

Frequency
Division

1200 & 2400

Phase
Shift

1200

1:1

Either

Yes

3:1

Synchronous

No

Yes

Point-to· Point
2-Wire

2:1

Either

No

Yes

No

1. BiVs not used in specification; rate stated in baud. Low speed 75 biVs back channel for
asymetric full·duplex

4. For half-duplex, 2-wire used

2. Half·duplex may still use a backward channel

5. Amplitude is constant on a relative basis

3. Makes no mention of 4-wire (must be assumed)

ND = Not defined (i.e., not specified in the recommendation)

9-97

No

I

Notes:

9-98

Section

10

PACKAGING/ORDERING
INFORMATION

I
10

Silicon Systems
Packaging Index

DUAL-IN-LiNE PACKAGE (DIP)

Plastic

Ceramic

PINS

PAGE NO.

8,14,16 & 18

10-4

20, 22, 24 & 24S

10-5

28,32 & 40

10-6

8,14,16& 18

10-7

22,24 & 28

10-8

20,28

10-9

SURFACE MOUNTED DEVICES (SMD)

Quad (PLCC)

32 &44
~

52 & 68

10-10

----

----

10-11

-------

Quad Flatpack (QFP)

52 & 100

10-12

128

10-13

Thin Quad Flatpack (TQFP)

32 & 48

10-14
----

64,80 & 100

10-15

120 & 128

10-16
~---.-----

10-17

144
------_ ..

Very Thin Quad Flatpack (VTQFP)

10-18

32,48 & 64

10-19

100
--_. . ._.-

10-20

120
--

Ultra Thin Quad Flatpack (UTQFP)
Small Outline (SOIC)
Pitch (mil)

64 & 100

10-21

8,14& 16S0N

10-22

16,18,20,24 & 28 SOL

10-23

Package

Width (mil)

SON

150

34 SOL

---

10-24

SOL

300

32 SOW

10-24

SOW

400

36S0M

10-24

SOM

300

44S0M

10-25

0.8

------~

Very Small Outline Package (VSOP)

...

10-25

20 & 24
--

Very Thin Small Outline Package (VTSOP)

16 & 20

10-26

Ultra Thin Small Outline Package (UTSOP)

24 &36

10-27

10-0

~~

Small form factor Package Selector Guide
Quad Flatpack Packages
BODY SIZE
(PITCH) mm

LAYOUT AREA mm 2

10.0x 10.0(0.65)

13.9x 13.9= 193.21

2.2

20.0 x 14.0 (0.65)

23.9 x 17.9 = 427.81

2.9

20.0 x 14.0 (0.5)

23.2 x 17.2 = 399.04

2.9

7.0 x 7.0 (0.8)

9.0 x 9.0 = 81

1.4

7.0 x 7.0 (0.5)

9.0x9.0=81

1.4

64GT (TQFP)

10.0 x 10.0 (0.5)

12.0 x 12.0 = 144

1.4

80GT (TQFP)

12.0x 12.0(0.5)

14.0x 14.0= 196

1.4

100 GT (TQFP)

14.0 x 14.0 (0.5)

16 x 16 = 256

1.4

PACKAGE TYPE

52 G (QFP)

1()() G (QFP)

128 G (QFP)

32 GT (TQFP)

48 GT (TQFP)

ACTUAL SIZE
(AREA)

o
D
D

•
•

= Actual Body Size

D

= Full layout Area

10-1

ACTUAL SIZE
(THICKNESS)

THI

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