1995_TI_Data_Acquisition_Circuits_Data_Book 1995 TI Data Acquisition Circuits Book
User Manual: 1995_TI_Data_Acquisition_Circuits_Data_Book
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"TEXAS
INSTRUMENTS
=============================
Data Acquisition Circuits
Data Conversion and DSP Analog Interface
1995
1995
Mixed-Signal Products
============~======
II
General Information
III
=============================111General Purpose DACs
General Purpose ADCs
DSP Analog Interface and conversion.
Special Functions
..
=========================~
Video Interface Palettes
..
~D=a=ta=M==a=nu=a=l=s================~1III
Application Reports
..
~M=e=c=h=an=i=c=al=D=a=t=a==============~1IDI
~A~p~p_e_nd_i_x____________________~1111
,
Data Acquisition Circuits
Data Book
Da~
Conversion and DSP Analog Interface
:'I1ExAs
INSTRUMENTS
PrInted on RecycIad Paper
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable atthe time of sale in accordance with Tl's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
selles office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1995, Texas Instruments Incorporated
Printed in U.S.A. by
Custom Printing Company
Owensville, Missouri
,
INTRODUCTION
Texas Instruments offers an extensive line of Industry-standard integrated circuits designed to provide highly reliable
circuits for peripheral support applications of microprocessor-based systems, DSP (digital signal processing) related
analog interfaces, video interfaces, video and high-speed converters, digitizing requirements that demand ADC and
DAC conversion, and general-purpose functions.
TI data acquisition sys'tem circuits represent technologies from traditional bipolar through LinCMOSTM, Advanced
LinCMOSTM, and LinEPICTM processes. The LinCMOSTM and Advanced LinCMOSTM technologies feature
improvements in resolution, power consumption, and temperature stability. LinEPICTM has both improved conversion
speed and reduced power consumption.
This data book provides information on the following types of products:
•
•
•
•
•
•
•
•
Dual-Slope Analog-to-Digital Converters (ADC)
Successive-Approximation Semi-Flash, and Flash ADC Converters
Current Multiplying and Video DAC Converters
High-Speed Converters for Control Applications
Color Palette Chips for Computer Graphics
Analog Interface Circuits for DSP Interface
Switched-Capacitor Filter ICs
Other General-Purpose Functions
These products cover the requirements of PC and workstation multimedia applications such as audio, graphics,
communication applications, modems and cellular phones, video capture and image processing, industrial control
and disk-drive servo-loop control, automotive,f electronic instrumentation, consumer, digital audio and any DSP or
microprocessor-based system. New surface-mount packages include both ceramic and plastic chip carriers, and the
smail-outline plastic packages that optimize board density with minimum impact on power-dissipation capability. The
equipment with handlers and test equipment. In addition, specifications and programs are continuously updated.
Quality and performance are monitored throughout all phases of manufacturing.
.
Included are those new products added to this volume as indicated by a dagger(t). The selection guide includes a
functional description of each device by providing key parametric information and packaging options. Ordering
information and mechanical data'are in the last section of the book.
Complete technical data for all TI semiconductor products are available from your nearest TI Field Sales Office, local
authorized TI distributor, or by writing directly to:
Texas Instruments Incorporated
LITERATURE RESPONSE CENTER
P.O. Box 809066
DALLAS, TEXAS 75380-9066
We sincerely believe the new 1995 Data Acquisition Circuits Data Book will be a significant addition to your technical
literature from Texas Instruments.
LinBICMOS, Advanced LinCMOS, and LinEPIC are trademarks of Texas Instruments Incorporated.
v
vi
Contents
Section 1 - General Information ••••••••••••••••• ••••••••••••••••••••••••••••••••••• 1-1
Analog-to-Digital Converter Selection Guide •..•••...•••••..•.•..••..•.•.••••....•••••.•••••••..••••••.•••• 1-3
Digltal-to-Analog Converter Selection Guide ...•.••..••••••••....•••••.•••••••..•.••...•...•••.•..••.•••••• 1-5
Cross-Reference Guide ••••••.•••••••.•••.•••••.•••••••••••.•••....•.••••••..•••••••••••••..••••••••••• 1-7
Devices Discontinued Since 1992 Data Book .•••••••••••••••••.•••..•.•.••••.•.•••••.••.•••••.••••••••••• 1-12
Glossary .•••••••••••••••••.••••.•••.•••••••••••••••••.•••.••••.•••••••••...•••••••••••••••..•••••••• 1-13
vii
Section 2 - Analog-ta-Dlgltal Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . ... . . . . . . . .. 2-1
ICL7135CfTLC7135C
4 112-Digit Precision Analog-to-Digital Converters ...............•............................••..•...• 2-3
TLC540IfTLC541I
8-Blt Analog-to-Dlgltal Converters With Serial Control and 11 Inputs .•...........•.......•.....•........ 2-13
TLC542CfTLC5421
8-Bit Analog-to-Digital Converters With Serial Control and 11 Inputs ••....•.•....•••.....• ; •.•...••..••• 2-23
TLC545CfTLC5451fTLC546CfTLC5461
8-Blt Analog-to-Dlgital Converters With Serial Control and 19 Inputs .............................•.....• 2-33
TLC548CfTLC5481fTLC549CfTLC5491
8-Bit Analog-to-Digital Converters With Serial Control ........•...................................•... 2-43
TLC0820ACfTLC0820AI
Advanced LinCMOS High-Speed 8-Bit Analog-to-Digital Converters
Using Modified Flash Techniques .................................................................. 2-53
TLC0831 ACfTLC0831 AlfTLC0831 BCfTLC0831 BI
TLC0832ACfTLC0832AlfTLC0832BCfTLC0832BI
8-Bit Analog-to-Digtt81 Converters With Serial Controlt .........••••............••..••.•••.•....•.••.• 2-63
TLC0834ACfTLC0834AlfTLC0834BCfTLC0834BI
TLC0838ACfTLC0838AlfTLC0838BCfTLC0838BI
8-Bit Analog-to-Digital Converters With Serial Controlt .........••.•.•....................•....••.••.• 2-73
TLC1540CfTLC1541C
1O-Blt Analog-to-Digltal Converters With Serial Control and 11 Inputs ...........................•.•.•.•. 2-85
TLC1542CfTLC1542IfTLC1542MfTLC1542QfTLC1543CfTLC1543IfTLC1543Q
1Q-Bit Analog-to-Dlgital Converters With Serial Control and 11 Analog Inputs ............................ 2-95
TLC1549CfTLC1549IfTLC1549M
1Q-Bit Analog-to-Digital Converters With Serial Control ...................••......•..•..........•...• 2-115
TLC15501fTLC1550MfTLC1551I
1Q-Bit Analog-to-Digital Converters With Parallel Outputs .•.....•••..•...••.•.....•.•••.•••.•••.•..• 2-129
TLC2543CfTLC25431
12-Blt Analog-to-Digital Converters With Serial Control and 11 Analog Inputs .•........................ 2-137
TLC5510
8-Bit High-Speed Analog-to-Dlgital Converter .......•....•.....•...•.•.•••••.•..•••••...••.•..••.. 2-157
TLC5540
8-Bit High-Speed Analog-to-Digital Convertert ..•••..•••.•.•..........•.•..........••..........••. 2-167
.TLC5733
20 MSPS 3-Channel Analog-to-Digital Converter With High-Precision Clamp ....••••.......•.......... 2-175
TLV1543CfTLV1543M
3.3-V 1O-Bit Analog-to-Digital Converters With Serial Control and 11 Analog Inputs. . . . . . . . . . . . . . . . • • . .• 2-191
TLVl549CfTLVl549IfTLV1549M
1Q-Blt Analog-to-Digital Converters With Serial Control •..•..........•.............•••..•••..••..•.. 2-209
TLV2543CfTLV25431
12-Bit Analog-to-Dlgltal Converters With Serial Control and 11 Analog Inputs •• . . . • . . . . . . . . . • . • . . • • . • •. 2-223
TL5501
6-Bit Analog-to-Digital Converter •....•.••...••••.....•..•......•...••.....•••..........•...••••• 2-243
tproduct P~eview
viii
,
Section 3 - Digital-fa-Analog Converters . ........................................... 3-1
TLC5602CITLC5602M
Video 8-Bit Digital-ta-Analog Converters •........................•..•.•.•..••...•.•....••••...•••.•• 3-3
TL5632C
8-Bit 3-Channei High-Speed Digital-to-Analog Converter ............................................. 3-11
TLC5620CITLC56201
Quadruple 8-Bit Digital-to-Analog Converters ...........................•..........••.....•••....••• 3-19
TLC5628CITLC56281
Octal 8-Bit Digital-ta-Analog Converters ............................................................ 3-29
TLC7226CITLC72261
Quadruple 8-Bit Digital-to-Analog Converterst ..••.....•....•.....•....••••...••...••.....•.•.•....• 3-39
TLC7524CITLC7524E1TLC75241
8-Bit Multiplying Digital-ta-Analog Converters ....................................................... 3-53
TLC7528CITLC7528E1TLC75281
Dual 8-Bit Multiplying Digital-ta-Analog Converters •...•.•....•..........•.•....••.................... 3-63
TLC7628CITLC7628E1TLC76281
Dual8-Bit Multiplying Digital-ta-Analog Converters .........................•......................... 3-77
TLV5620CITLV56201
Quadruple 8-Bit Digital-to-Analog Converterst ..•••..•.•....•........•...••....•...•..•......•...... 3-87
TLV5628CITLV56281
Octal 8-Bit Digital-ta-Analog Converterst ..............................................•••...•...•.. 3-95
TMS57014A
Dual Audio Digital-ta-Analog Converter. . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . • . . . . . . . . . . . . . .. 3-103
AD7524M
Advance LinCMOS 8-Bit Multiplying Digital-ta-Analog Converter ........................•..••...••.•.. 3-117
tproduct Preview
ix
s.ctIon 4 - Analog Interlat:e C/~ults and Codec ••••...•••.•. .;...................... 4-1
TLC32040C1TLC32040IITLC32041 crrLC320411
Analog Interface Circuits ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 4-3
TLC32044crrLC32044E1TLC32044IITLC32044M1TLC32045CfrLC320451
Voice-Band Analog Interface Circuits ............................................................. 4-35
TLC32OAD56C
Sigma-Delta Analog Interface Clrcuit't • • • • • • • • • • • . • • • • • • • • • • • • • • • • • • • • • • • • • • • • • .. • • • .. • • • • • • • • • • • •• 4-73
TLC32OAD65C
16-BIt Sigma-Delta Stereo Codect ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 4-75
tproduct Preview
x
,
SectIon 5 - Related Special Products ...........................'. . . . . . . . . . . . . . . . . . .. 5-1
TL7726CITL7726IITL7726Q
Hex Clamping Circuits ••.••••...•......•......••....•....••.•.••.....•.•.•••....•••••.•..•••••••• 5-3
TLC04IMF4A-601TLC14/MF4A-100
Butterworth Fourth-Order Low-Pass Switched-Capacitor Filters •.•.•••..••••.••••••...••.•••••••••••••• 5-7
TLC29321
High-Performance Phase-Locked Loop ..•.•.•..•••...••.••••••••••.•••..••..••..••••.••••••••.••• 5-19
TL32088
Differential Analog Buffer Ampllflert •• • • • . • • • • . • • . . • . . • • . • • • • • • • • . . • • • • . • . • • • • • • • . • • • . • • • • • • • • • • • •• 5-41
tproduct Preview
xi
SectIon B -
~~ I",."..
P.,.". ExtI'IIOtIJ .. _••• '! • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
~1
TLC34058
266 x 24 Color Palette •••••••••••••••••••••••••••••••••••••••••••••••••••• '•••••••••••••••••••• ~. 6-3
TLC34074
VIdeo Interface Dlgltal-to-Analog Converter •••••••••••••••••••••••••••••••• ~ •••••• _ • • • • • • • • • • • • • •• 8-5
TLC34075A
Video Interface palette ••••••••••••••••.•••••••.••••••••••••••••••••••••••••••••••••••••••••••••• 6-7
TLC34076
Video Interface Palette •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 6-11
TLC340n
Video Interface Palette ••••••••••••••••••••••••.•••••••••••••••••••••••••••••••••••••••••••••••• 6-15
TVP2002
Clock Driver •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 8-17
TVP301 0
Video Interface Palette •••••••••••••••••••••••••••••••••••••••• • • • • • • • • • • • • • • . • • • • • • • • • • • • • • • • •• 6-19
TVP3020
VIdeo Interface Palette •.••••.•...•. • • • • • • • • . . • • • • • • • • • . • • • • • • • • • • . . • • • • • • . • • • • • • • • • • • • • • • • • • • •• 6-23
TVP3025
Video Interface Palette .......................................................................... 6-27
TVP3026
Video Interface palette •••••••••••••••••••••••••••••••••••••••••••••••• ,........................ 6-31
TVP3027
VIdeo Interface Palettet •••••••••••••••••••••••••••••••••••••••••.•••••••••••••••••••••••••••••• 6-35
TVP3030
Video Interface Palette ••••••••••••••••••••,••••••••••••••••••••••••••••••••••••••••••••••••••••• 6-39
TVP3409
Video Interface Palette True-Color CMOS RAMDAct· • • • • • • • • • • • • • • • • • • • • • •• • • • • • • • • • • • • • • • • • • • • • • •• 6-43
TVP3703
Video Interface Palette Tru.color CMOS RAMDAct ••••••••••••••••••••••••••••••••••••••••••••••• 6-45
tproduct Preview
xII
SfJcfIon 7 - DIlts 1118nusl. .. ................................ ;, ................. ....................................................... "," .... 7-1
TLC32048C, TLC32048I, TLC32046M
Wide-Band Analog Interface Circuit •••••••••••••••••• ; • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 7-3
TLC32047C, TLC320471
WId.a&nd Analog Interface Circuit .. • .. • .. • .. • .. .. • .. .. • • • .. • .. • .. • • .. .. .. • .. .. • • • .. • . .. • • • • .. ... 7-59
TLC32OAC01C
Single-Supply Analog Interface Circuit ........................................................... 7-117
TLC32OAC02CITLC320AC021
Singie-Supply Analog Interface Circuit ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 7-191
TLC32OAD55C
Sigma-Delta Analog Interface Circuit. • • • • • • • • • • • • • • • • • • • • • ... • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 7-265
TLC32OAD57C
.
Sigma-Deita Stereo Analog-to-Digital Converter •••••••••••••••••••••••••••••••••••••••••••••••••.• 7-303
TLC32OAD58C
Sigma-Delta Stereo Analog-to-Digital Converter. • • ••• •• •• • • • •• • ••••••••• •• ••• • ••• • • • • ••• ••• ••• •• •• 7-323
xiii
SectIon 8 - Application Reports ...•..........................•........•. ~ . . . . . . . .. 8-1
TLn26
Hex ,Clamping Circuit .••••••••••••.••••••••••••••••.•••.••••••••••••••••••••••••••••••••••••••••• 8-3
Microcontroller Based Data Acquisition Using the TLC2543 12-Bit Serlal-Out ADC •••••••••••••••••••.••••.•. 8-17
Interfacing the TLC32040 Family to the TMS320 Family ••••.•••••••••••••••..••.••••••.••••••••••••••••••. 8-43
Designing With the TLC320AC01 Analog Interface for DSPs .•...••.•••.••••••••..••••••••••••••••••••.••• 8-93
Interfacing the TLV164910-Bit Serial-Out ADC to Popular 3.3-V Mlcrocontrollers •..•••••••••..••.•.•.••• ; •• 8-121
TLC2932
Phase-locked-Loop Building Block With Analog Voltage-Controlled Oscillator and
.
.
Phase Frequency Detector .••..•••••••.••••..•••.•••.•...••.•••••••••••••••• ; •••.•.•.••.•••••.• 8-137
Understanding Data Converters •••••••••••••••••••.••••.•..•••••••..•••••••.•••••••••.•••..••••••.••• 8-179
xiv
•
SectIon 9 - Mechanical Data ......•........•.......•.............•..••........•.... 9-1
08-.14-. 18-Pin Plastic Small-Outline Package ••.•...•.....•..••...•..••.•..•••.••••....•••..•••••..•••• 9-3
DB 14-. 18-.20-.24-.28-.30-. 38-Pin Plastic Small:Qutline Package ••••••••••••••••••••••••.•••••••••••••• 9-4
OW 18-. 20-. 24-. 28-Pin Plastic Small-Outline Package •••••••••••••••••••••••••••••••••••••••••••.••••••• 9-5
DWB 28-Pin Plastic Small-Outline Package .••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 9-6
FK 20-. 28-. 44-. 52-. 68-. 84-Pin leadless Ceramic Chip Carrier ...•..••..••••..••..•.••••••••••••••••••••• 9-7
FN 20-. 28-. 44-. 52-. 68-. 84-Pin Plastic J-Leaded Chip Carrier •• • • • • • • • • • • • • • . • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 9-8
FR 44-Pin Plastic Quad Flatpack •••••••••••••••••••••••••••••••••••••.•••••••••••••••••••••••••••••••••• 9-9
J 14-. 16-. 18-.20-. 22-Pin Ceramic Dual-In-Une Package •••••••••••••••••••••••••••••••••••••••••••••••• 9-10
JG 8-Pin Ceramic Dual-In-Une Package •.••••..•••.•••••••••••••..•••.•.•.••..•••••••••••••••••••••••••• 9-11
JT 24-. 28-Pin Ceramic Dual-In-L1ne Package •••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 9-12
JW 24-Pin Ceramic Dual-In-Une Package •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 9-13 .
N 14-. 18-. 18-. 20-Pin Plastic Dual-In-Une Package ••••••••••••••••••••••••••••••••••••••••••••••••••••• 9-14
N 24-. 28-. 32-. 40-. 48-. 52-Pin Plastic Dual-In-Une Package ••.••••••.••••.•.•••••••••••••••••••••••••••• 9-15
NS 14-. 16-.20-. 24-Pin Plastic Small-Outllne Package ••••••••••••••••••••••••••••••••••••••••••••••••••• 9-16
NW 24-. 28-. 40-. 48-Pin Plastic Dual-ln-Une Package ••••••••••••••••••••••••••••••••••••••••••••••••••• 9-17
P 8-Pin Plastic Dual-In-Une Package •••••••••••••••••••.•••••••••••••••••••.•••••••••••••••••••••••••• 9-18
PM 84-Pin Plastic Quad Flatpack •.•.•.••........•..•. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •. 9-19
PW 8-.14-.16-.20-.24-. 28-Pin Plastic Small-Outline Package •••••••••••••••••••••••••••••••••••••••••••• 9-20
PZ 100-Pin Plastic Quad Flatpack •••••••••••••••••••••••••••••••••••• , •••••••••••••••••••••••••••••••• 9-21
X'
Sect/on A - Appendix ................................................. A-1
Analog Interface Peripherals and Applications ................................•............. A-3
xvi
II'
General Information
1-1
C)
·CD
::s
CD
",-.
0),
.'
--
::s
a'
-.
,3 '
a-.
"
,0
, ':S
1-2
ANALOG·TO·DIGITAL CONVERTER
SELECTION GUIDE
II
16118 TLC320A057
12
10
8
48,
44.1,32
2
X
I
5
X
X
200
OW
28
Dual slgma-delta. SNR of 97 dB
TLC2543
10
66
11
5
X
X
12
OW,FN,
N
20
Low cost, high resolution
TLV2543t
10
66
11
3.3
X
X
8
DW,FN,
N
20
3 V version TLC2543
TLC122511125
12
83
1
±5
X
TLC1550/1551
6
164
1
5
X
X
85
N,FN
28
Uni or bipolar with self-calibration
40
FN,NW
24
DSP front end wHh 3-state outputs
8
Plug in upgrade for TLC549
TLCl549
21
38
1
5
X
12
0, FK,
JG,P
TLVl549
21
38
1
3.3
X
8
0, FK,
JG,P
8
3 V version TLCl549
TLCl543
21
38
11
5
X
12
OW,FN,
N
20
Plus in upgrade for TLC543
TLVl543
21
38
11
3.3
X
8
OW,FK,
J,N
20
3 V version TLCl543
TLC1541
21
32
11
5
12
OW,J,N,
FK,FN
20
± 1 LSB total error
TLC1540
21
32
11
5
12
OW,J,N,
FK,FN
20
±0.5 LSB total error
TLC5510
20,000
1
5
X
90
NS
24
Replaces Sony CXOl175
TLV5510i
20,000
1
3
X
60
NS
24
3 V version of TLC551 0
TLC5733:!:
20,000
3
5
X
375
QFP
40,000
1
5
X
120
392
1
5
X
NS
OW,F,
NFK,N
64
24
Triple AOC with clamp
TLC554tN:i
20
Replaces A07820 and ADC0820
8
5
TLC0820A
12
TLC083a*
20
X
75
High speed AOC
12
FN,N
20
Replaces AOC0638
20
Replaces AOC0811 end MC145040
TLC540
9
75
11
5
12
SW,N,
FN
TLC541
17
40
11
5
12
OW,N,
FN
20
Compatible with TLCl540 pinout
TLC542
20
25
11
5
10
FN,N,
OW
20
Replaces MC145041
TLC545
TLC546
9
76
19
5
12
FN,N
40
19
5
12
FN,N
28
28
uP compatible
17
TLC548
17
45.5
1
5
X
12
O,P
8
uP compatible
TLC549
17
40
1
5
X
12
O,P
8
uP compatible
X
uP compatible
t Budgetary pricing for O·C to 70·C
:j: Indicates product preview
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1-3
ANALOG·TQ.OIGITALCONVERTER
SELECTION GUIDE
GENERAL PURPOSE AID CONVERTERS
fa>=1 MSPS
tconv <= 1 J.IS
100 KSPS < fa < 1 MSPS
1 J.IS < tconv < 10 J.IS
TLV5510t,
20 MSPS
TL5501,
20 MSPS
TLC0820,
392 KSPS
f a <100KSPS
teonv < 10 J.IS
TLC1550,
164 KSPS
TLC5510,
20 MSPS
TLC5733t,
20 MSPS,
triple ADC, with clamp
TLC5540t,
40 MSPS
TLV1549,
38 KSPS
TLV1543,
11 Inputs,
38 KSPS
TLC0632, 2 Inputs, t
30 KSPS
TLC0634,4Inputs,t
30 KSPS
, TLC0638,8Inputs,t
30 KSPS
TLC540,11 Inputs,
75 KSPS
TLC541,11 Inputs,
40 KSPS
TLC542, 11 Inputs,
25 KSPS
TLC545,19Inputs,
76 KSPS
TLC546, 19 Inputs,
40 KSPS
TLC548, 45.5 KSPS
TLC549, 40 KSPS
TLC1549, 38 KSPS,
Internal clock
TLC1543,11 Inputs,
38 KSPS
TL(;1541,11 Inputs,
32 KSPS
TLC1540, 11 Inputs,
32 KSPS
TLC2543,11 Input,
10 J.IS, Sleep
TLC1225,63 KSPS,
aelf-callbrate
t Indicates product preview status at time of print.
~I
~ TEXAS
1-4
'
NSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLV2543t,
~61~:p~:
Sleep
TLC320AD57, stereo,
Sigma Delta
DIGITAL-TO-ANALOG CONVERTER
SELECTION GUIDE
I
I
q
16118 TMS57014A
8
I
350
OWB
28
Dual audio sigmadelta DAC with
Interpolation filter
and digital volume
control
±0.5
5
D,N,FN
16
Popular low cost
MDAC with latch for
DSP and lIP'S
5-15
±0.5
5
OW,N,
FN
20
Dual version of
TLC7524
10-15
±0.5
20
OW,N,
FN
20
Dual MDAC with
TTL-compatible
inputs
32,37.8,
44.1 and
48kHz
Serial
PWM
2
N/A
TLC7524
8,I1P
I
1
Ext,M
100 ns
5-15
TLC7528
8,I1P
I
2
Ext,M
100 ns
TLC7628
8,I1P
I
2
Ext,M
100 ns
TLC7225;
8,I1P
V
4
Ext
51J.S
±0.5
TLC7226;
8,I1P
V
8
Ext
51J.S
±0.5
195
DW,N,
FN
20
Replaces AD7226
TLC5620
Serial
V
4
Ext
101J.S
5
±1
10
N,D
14
Low power quad
DACwith
programmable x1 or
x2 output.
TLC5628
Serial
V
8
Ext
101J.S
5
±1
10
N,DW
16
Low power, octal
DACwith
programmable x1 or
x2 output.
TLV5620;
Serial
V
4
Ext
10 IJ.S
3
±1
10
N,D
14
3 V version of
TLC5620
TLV5628;
Serial
V
8
Ext
1OIJ.S
3
±1
10
N,D
16
3 V version of
TLV5628
TLC5602
8
V
1
Ext
30 ns
5
±0.5
30 MHz
80
N,DW
18
Low power video
DAC
8by3
V
3
Int
5
±0.5
60 MHz
350
FR
44
Triple video DAC
withintemal
reference.
TL5632
5
Separate reference
for each DAC
tExt, M - extemal reference, multiplYing; PWM - Pulse width modulated
; Indicates product preview
i
~TEXAS
INSTRUMENTS
POST ~FFICE BOX 655303 • DALLAS. TEXA,S 75265
1-5
DIGITAL-TO-ANALOG CONVERTER
SELECTION GUIDE
D/A CONVERTERS
Stereo Audio
DACs
General Purpose
DACs
VIdeo Graphics DACs
TMS57014A, Dual, o.emphasls Filter
TL5632, triple, 60 MHz
TLC5602, 1 output, 30 MHz
TLC5602, 1 output, 30 MHz
TL5632, 3 outpute, 60 MHz,
TLC7226, 4 outputs, 5 JISt
TLC7624, 1 output, 80 n.
TLC71528, 2 outpute, 80 n.
TLC7628, 2 outputs, 80 ne, 10-16 V Vee
TLC5620, 4 outputs, 10 JIS
TLC5628, 8outpute, 10 JIS
TLV562O, 4 outputs, 10 JISt
TLV5628, 8 outputs, 10 JISt
t Indicates product preview status at time of print.
~1ExAs
1-8
INSTRUMENTS
POST OFFICE SOX 655303 • DALlAS. TEXAS 75286
DATA ACQUISITION AND CONVERSION
CROSS-REFERENCE GUIDE
Replacements are based on similarity of electrical and mechanical characteristics shown in currently published
data. Interchangeability in particular applications is not guaranteed. Before using a device as a substitute,
compare the speCifications of the substitute device with the specifications of the original.
Texas Instruments makes no warranty as to the information fumished and the buyer assumes all risk in the use
thereof. No liability is assumed for damages resulting from the use of the information contained herein.
Manufacturers are arranged in alphabetical order.
DIRECT
TI
REPLACEMENT
ANALOG
DEVICES
AD573
"
AD7524AD
AD7524JN
AD7528BQ
AD7528KN
AD7820KlBIT
AD7524AN
AD7524JN
AD7528BN
AD7528KN
TLC0820A
SUGGESTED
TI
REPLACEMENT
TLC1550INW
TLC15501FN
TLC15511NW
TLC15511FN
TLC75241N
TLC7524CN
TLC75281N
TLC7528CN
AD7820UC/U
AD7820
AD7890
TLC0820
TLC2543IN
TLC25431DW
TLV25431N (3V)
TLV2543IDW
ADC82AG
AD82AM
AD1878
AD9048
ADC-EK12DC
TLC0820AIN
TLC320AD57
TLC5540lNS
TLC7135CN
TLC7135CFN
ICL7135CN
ICL7135CFN
TLC7135CN
TLC7135CFN
ICL7135CN
ICL7135CFN
TLC75241N, AD7524AN
TLC7524CN, AD7524JN
TLC7528, AD7528
ADG-EK12DR
PM7524FQ
PM7524FP
PM7528
BROOKTREE
DIRECT
TI
REPLACEMENT
SUGGESTED
TI
REPLACEMENT
DIRECT
TI
REPLACEMENT
SUGGESTED
TI
REPLACEMENT
Bn 01, 102, 253
CRYSTAL
TL5632CFR
5336,5339
TLC320AD57
~lExAs
INSTRUMENTS
POST OFFICE BOX _ . DALI..AS, TEXAS 75265
1-7
DATA ACQUISITION AND CONVERSION
CROSS-REFERENCE GUIDE
DIREct
TI
REPLACEMENT
FUJITSU
TL5501
TLC5502
TLC5602
MB40576
MB40578
MB40778
DIRECT
n
HARRIS
REPLACEMENT
DIRECT
TI
REPLACEMENT
LINEAR
TECHNOLOGY
SUGGESTED
TI
REPLACEMENT
LTC 1092193194
LTC1291f92193/94
DIRECT
TI
REPLACEMENT
MAXIM
SUGGESTED
n
REPLACEMENT
TLC15491N
TLC15491DW
TLC1542IN
TLC15431N
TLC15421DW
TLC1543IDN
TLC25431DW
LTC 1091
SUGGESTED
n
REPLACEMENT
TLC2543IN
TLC25431DW
TLC2543IFN
TLC2543 (3V)
TLC6620
TLC5628
MAX17x Family
MAX609
MAX629
DIRECT
n
MICRO
NETWORKS
REPLACEMENT
MN61 00/5101
MN5120/5130/5140
SUGGESTED
TI
REPLACEMENT
TLC0820ACN
TLC0820ACN
DIRECT
TI
REPLACEMENT
MP7138AN
SUGGESTED
TI
REPLACEMENT
TLC7135CN
TLC7135CFN
ICL7135CN
ICL7135CFN
~1ExAs
1-8
TLV5510 (3 V)
. TLV55101NS (3 V)
H11175
MICRO
POWER SYSTEMS
SUGGESTED
TI
REPLACEMENT
INSTRUMENTS
POST OFFICE BOX 666303 • DALLAS. TEXAS 75266
.
DATA ACQUISITION AND CONVERSION
CROSS-REFERENCE GUIDE
MOTOROLA
DIRECT
TI
REPLACEMENT
SUGGESTED
TI
REPLACEMENT
MC14433P
MC14444P
MC145040FN
MC145040L
MC145040P
MC145041P1
MC14051
NATIONAL
ADC0811BCJ
ADC0811BCN
ADC0811BJ
ADC0811CCJ
ADC0811CCN
ADC0811CCV
ADC0811CJ
ADC0820BCD
ADC0820BCN
ADC0820BD
ADC0820CCD
ADC0820CCN
ADC0820CD
ADC0830BCN
ADC0830CCN
ADC0831BCJ
ADC0831BCN
ADC0831CCJ
ADC0831CCN
ADC0832BCJ
ADC0832BCN
ADC0832CCJ
ADC0832CCN
ADC0834BCJ
ADC0834BCN
ADC0834CCJ
ADC0834CCN
ADC0838BCJ
ADC0838BCN
ADC0838CCJ
TLC7135CN
TLC7135CFN
ICL7135CN
ICL7135CFN
TLC546IN
TLC540MFN
TLC540MJ
TLC540MN
TLC541MFN
TLC541MJ
TLC541MN
TLC542IN
TLC15431N
TLC15421N
TLC15431DW
TLC15421DW
DIRECT
TI
REPLACEMENT
SUGGESTED
TI
REPLACEMENT
TLC541IN
TLC541IFN
TLC541MJ
TLC541IN
TLC541IN
TLC541IFN
TLC541MJ
TLC0820BIN
TLC0820BCN
TLC0820BMJ
TLC0820AIN
TLC0820ACN
TLC0820AMJ
TLC0831BIP
TLC0831BIP
TLC0831 AlP
TLC0831ACP
TLC0832BIP
TLC0832BCP
TLC0832AIP
TLC0832ACP
TLC540IN
TLC540lFN
TLC540MJ
TLC540lN
TLC540lN
TLC540lFN
TLC540MJ
TLC5461N
TLC5461N
TLC5491N
TLC549IN
TLC5491N
TLC5491N
TLC0834BIN
TLC0834BCN
TLC0834AIN
TLC0834ACN
TLC0838BIN
TLC0838BCN
TLC0838AIN
~
~1ExAs
INSTRUMENTs
POST OFFICE BOX 85S303 • DALLAS. TEXAS 75285 .
1-9
DATA ACQUISITION AND CONVERSION
CROSS-REFERENCE GUIDE
DIRECT
TI
REPLACEMENT
NATIONAL
(Continued)
ADC0838CCN
ADC1001CCJ
ADC1005BCJ
ADC1005CCJ
ADC1225
ADC3511CCN
TLC0838ACN
TLC15411N
TLC1541IN
TLC15411N
TLC1225
TLC7135CN
ICL7135CN
TLC7135CN
TLC7135CFN
ICL7135CN
ICL7135CFN
ADC3711CCN
MF4-50
MF4-1 00
TLC04/MF4A-50
TLC14/MF4A-100
DIRECT
TI
REPLACEMENT
PHILLIPS
NE5036FElNlD
NE5037F/N/D
TDA8703
TDA8707
SILICONIX
DIRECT
TI
REPLACEMENT
LD120CJ
LD121ACJ
TLC7135CN
ICL7135CN
DIRECT
TI
REPLACEMENT
CXD1175
SUGGESTED
TI
REPLACEMENT
TLC5510lNS
TLV5510lNC (3V)
TLC5540lNS
CXD1179
~.1ExAs
1-10
SUGGESTED
TI
REPLACEMENT
TLC7135N
ICL7135CN
TLC7135CN
ICL7135CN
TLC7135CN
ICL7135CN
TLC7135CN
ICt.7135CN
LD111ACJ
SONY
SUGGESTED
TI
REPLACEMENT
TLC549CN/CD
TLC549CN/CD
TLC55401NS
TLC57331PM
LD110CJ
Si7135CJ
SUGGESTED
TI
REPLACEMENT
INSTRUMENTS
POST OFFICE BOX 855303 • DAUAS.,TEXAS 75265
DATA ACQUISITION AND CONVERSION
CROSS-REFERENCE GUIDE
TELEDYNE
TSC7135CPI
DIRECT
TI
REPLACEMENT
SUGGESTED
TI
REPLACEMENT
TLC7135CN
ICL7135CN
TSC8701
TSC8704
TSC14433CN
TLC1541IN
TLC1541IN
TLC7135CN
ICL7135CN
~
POST OFFICE BOX 866303 • DALLAS. TEXAS 7&266
1-11
DEVICES DISCON'rINUED SINCE 1992 DATA BOOK
Analog-to-Digital Converters
ADC0803
ADC0804
ADC0805
ADC0808
ADC0809
ADC0831
t Retaining the TLC0820A
ADC0832
ADC0834
ADC0838
TLC53213
TL500
TL501
\
TL502
TL503
TL505
TL507
ADC0820t
TLC5502-2
TLC5502-5
TLC5503-2
TLC5503-5
TL5501
T1191
TL601
TL604
TL607
TL61 0
TLC4016
TLC4066
Analog Interface Circuits
TLC32071
TLC32042
Analog Switches*
TL181
TL185
TL188
:j: All analog switches and multiplexers in the data book are discontinued.
Filters
MF10A
MF10C
TLC10
TLC20
~TEXAS
1-12
INSTRUMENTS
POST OFACE eox 655303 • DALlJ\S. TEXAS 75265
GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR
ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS
INTRODUCTION
These terms, definitions, and letter symbols are in accordance with those currently approved by the JEDEC
Council ofthe Electronic Industries Association (EIA) for use in the USA and by the International Electrotechnical
Commission (IEC) for international use.
1. GENERAL TERMS
Analog-to-Dlgltal Converter (ADC)
A converter that uniquely represents all analog input values within a specified total input range by a limited
number of digital output codes, each of which exclusively represents a fractional part of the total analog input
range (see Figure 1).
NOTE:
This quantization procedure introduces inherent errors of one-half LSB (least significant bit) in the
representation since, within this fractional range, only one analog value can be represented free of
error by a single digital output code.
CONVERSION CODE
RANGE OF
ANALOG
INPUT
VALUES
4.5 0 5.5
0 ••• 101
3.5 0 4.5
0 ... 100
,,---( 2.5·3.5
'-----
Digital Output
Code
DIGITAL
OUTPUT
CODE
---~
0 ... 011 I
-----'
1.5 0 2.5
0 ... 010
0.501.5
0 ... 001
0 0 0.5
0 ... 000
Ideal Straight Line
0 ... 101
Step
0 ... 100
a!\v--( 0 ... 011
'----0 ... 010
0 ... 001
0 ... 000
I ' -........+---+--t---i---+--+ Analog Input
o
Value
2
3
4
5
Mldstap Value
of 0 ... 011
Quantization
Error
+1/2
LSB
. .-+-.....HHIH-+-.....-+-.....~f-....- .
o
Analog Input
Value
-1/2
LSB
Figure 1. Elements of Transfer Diagram for an Ideal Linear ADC
-!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
1-13
GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Analog-to-Dlgital Processor
An integrated circuit providing the anaiog part of an ADC; provision of external timing, counting, and arithmetic
operations is necessary for implementing a full analog-to-digital converter.
Companding DAC
A DAC whose transfer function complies with a compression or expansion law.
NOTE 1: The corresponding ADC normally consists of such a companding DAC and additional external
circuitry.
NOTE 2: The compression or expansion law Is usually a logarithmic function, e.g., A-law or J1"'law.
Conversion Code (of an ADC or a DAC)
The set of correlations between each of the fractional parts of the total analog input range or each of the digital
input codes, respectively, and the corresponding digital output codes or analog output values, respectively (see
Figures 1 and 2).
NOTE:
Examples of output code formats are straight binary, 2's complement,. and binary-coded decimal.
Analog Output
Value
5
4
1+--- Step Height (1 LSB)
3
2
14--- Step value
O~--~----~--~~r-~----~---'
Digital Input Code
0 ... 000 0 ... 001 0 ... 010 0 ... 011 0 ... 100 0 ... 101
l,)
Step
CONVERSION CODE
Digital Input Code
Analog Output Value
0 ... 000
0 ... 001
0 ... 010
0
1
2
r
I
,
0 ... 011
I
'L_!_J
0 ... 100
0 ... 101
4
5
Figure 2.. Elements of Transfer Diagram for an Ideal Linear DAC
Digltal-to-Analog Converter (DAC)
A converter that represents a limited number of different digital input codes by a corresponding number of
discrete analog output values (see Figure 2)
NOTE:
Examples of input code formats are straight binary, 2's complement, and binary-coded decimal.
~TEXAS
1-14
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75285
GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Full Scale (of a unipolar ADC or DAC)
A term used to refer a characteristic to that step within the transfer diagram whose nominal midstep value or
nominal step value has the highest absolute value [see Figure 3(a) for a linear unipolar ADC].
NOTE 1: The subscript for the letter symbol of a characteristic at full scale is FS.
NOTE 2: In place of a letter symbol, the abbreviation FS is in common use.
Full Scale, Negative (of a bipolar ADC or DAC) [see Figures 3(b) and 3(c)]
A term used to refer a characteristic to the negative end of the transfer diagram, that is, to the step whose nominal
midstep value or nominal step value has the most-negative value.
NOTE 1: The subscript for the letter symbol of a characteristic at negative full scale is FS- (VF5-, IF5-)'
NOTE 2: In place of a letter symbol, the abbreviation F5- is in common use.
Full Scale, Positive (of a bipolar ADC or DAC) [see Figure 3(b) and 3(c)]
A term used to refer a characteristic to the positive end of the transfer diagram, that is, to the step whose nominal
midstep value or nominal step value has the most-positive value.
NOTE 1: The subscript for the letter symbol of a characteristic at positive full scale is FS+ (VFS+, IFS+)
NOTE 2: In place of a letter symbol, the abbreviation FS+ is in common use.
Full-Scale Range, Nominal (of a linear ADC or DAC) (VFSRnom, IFSRnom) (see Figure 3)
The total range in analog values that can be coded with uniform accuracy by the total number of steps with this
number rounded to the next higher power of 2.
NOTE:
Example:
In place of the letter symbols, the abbreviation FSR(nom) can be used.
Using a straight binary n-bit code format, it follows:
- for an ADC: FSR(nom) = 2n x (nominal value of step width)
- for a DAC: FSR(nom) =2n x (nominal value of step height)
Full-Scale Value, Nominal (VFSnom, IFSnom)
A value derived from the nominal full-scale range:
- for a unipolar converter: VFSnom = VFSRnom
- for a bipolar converter: VFSnom =1/2 VFSRnom (see Figure 3)
NOTE 1: In a few data sheets, this analog value is used as a reference value for adjustment procedures or
as a rounded value for the full-scale range(s).
NOTE 2: In place of letter symbols, the abbreviation FS(nom) Is In common use.
Full·Scale Range, (Practical) (of a linear ADC or DAC) (VFSR, IFSR) (VFSRpl'l IFSRpr) (see Figure 3)
The total range of analog values that correspond to the ideal straight line.
NOTE 1: The qualifying adjective practical can usually be deleted from this term provided that, in a very few
critical cases, the term nominal full-scale range is not also shortened in the same way. This permits
use of the shorter letter symbols or abbreviations (see Note 2).
NOTE 2: In place of the letter symbols, the abbreviations FSR and FSR(pr) are in common use.
NOTE 3: The (practical) full-scale range has only a nominal value because it is defined by the end points of
the ideal straight line.
Example:
Using a straight binary n-bit code format, it follows:
- for an ADC: FSR = (2 n -1) x (nominal value of step width)
- for a DAC: FSR = (2n -1) x (nominal value of step height~
~TEXAS
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265
1-15
GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Digital Output
Code
VZS~
~ VFS(NOM)
"'--+_-+_-+_-t--'--t_--1r--t..-__
8
o
2
345
6
7
Analog Input
Value
~~---- VFSR -------.t~
(a) UNIPOLAR ADC
Digital Output
Code
---------,,
,,
,
,,,
,
,---------
,,
,,
,,
,
I
.01;4
~~+_-+_-+_~
__~t_-t_-t..-~VI
,,
,,
,
,,
,
-'4
~~----
VFSR
------.t
,
,,
,,
,
,
,,
L
VI =Analog
Input Value
(b) BIPOLAR ADC WITH TRUE ZERO
________
_ ______ _
. . . - - - - - - VFSR
-------.t
(e) BIPOLAR ADC WITH NO TRUE ZERO
Figure 3. Ideal Straight Line, Full-Scale Value and Zero-Scale Value
(Shown for Ideal Linear ADCs)
~TEXAS
1-16
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS, TEXAS 75265
GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Gain Point (of an adjustable ADC or DAC)
The pOint in the transfer diagram corresponding to the midstep value (for an ADC) or the step value (for a DAC)
of the step for which gain error is specified (usually full scale), and in reference to which the gain adjustm!'lnt
is performed (see Figures 4 and 5).
NOTE:
Gain adjustment causes only a change ofthe slope of the transfer diagram, without changing the offset
error.
Ideal Straight Line (of a linear ADC or DAC)
In the transfer diagram, a straight line between the specified points for the most-positive (least-negative) and
most-negative (least-positive) nominal midstep values or nominal step values, respectively (see Figures 1, 2,
and 3).
NOTE:
The ideal straight line passes through all the points for nominal midstep values or nominal step values,
respectively.
LlnearADC
An ADC having steps ideally of equal width excluding the steps at the two ends of the total range of analog input
values.
NOTE:
Ideally, the width of each end steps is one half of the width of any other step (see Figure 1).
LinearDAC
A DAC having steps ideally of equal height (see Figure 2).
LSB, Abbreviation
The abbreviation for Least Significant Bit, that is, for the bit that has the lowest positional weight in a natural
binary numeral.
Example:
In the natural binary numeral 1010, the rightmost bit 0 is the LSB.
LSB, Unit Symbol (for linear converters only)
The unit symbol for the magnitude of the analog resolution of a linear converter, which serves as a reference
unit to express the magnitude of other analog quantities of that same converter, especialiy of analog errors, as
multiples or submultiples of the magnitude of the analog resolution.
Example:
NOTE:
1/2 LSB means an analog quantity equal to 0.5 times the analog resolution.
The unit symbol LSB refers to the fact that, for a natural binary code, the analog resolution corresponds
to the nominal positional weight attributed to the least significant bit of the binary numeral.
In this case, the identity:
1 LSB = analog resolution
leads, for an n-bit resolution, to:
1 LSB
=
FSR
2n - 1
= FSR(nom)
2"
Midstep Value (of an ADC)
The analog value for the center of the step excluding the steps at the two ends of the total range of analog input
values.
NOTE:
For the end steps, the midstep value is defined as the analog value that results when the analog value
for the transition to the adjacent step is reduced or enlarged, as appropriate, by half the nominal value
of the step width (see Figure 1).
~TEXAS
INSTRUMENTS
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1-17
/
GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Gain Point
-------------~~
111
1/'
rI
1/
110
101
~
1
0
j
'\,.1"/
100
011
P
aI
is
r7
ldaal Straight Lln~
010
~
//1
.f-l
001
//1
2
3
4
5
Analog Input value
7
6
(a) BEFORE ADJUSTMENT
Gain Adjustment ~
------------r*r~
111
I
I
I
~-
100
.&
:I
0
J
c
I
~'5
~/'
i
~{
000
010
1//
_..1
I
~
o
I
J/
011
I/~
001
i/
I 1/
I Y
,/1
g
c
)
/(
c
1,1
100
.&
:I
0
I
1/1
Ii,
101
16/
010
I
I
1//
rl1"
011
-------------~
111
110
~-)I'
101
III
'5
.If
/
r.,.,L..1//
110
"B
I
001
000
1
2
5
3
4
Analog Input Value
~ Offset Adjustment
6
7
0
2
3
4
5
Analog Input Value
6
7
(c) AFTER OFFSET AND GAIN ADJUSTMENTS
(b) AFTER OFFSET ADJUSTMENT
NOTE A: In the above examples, the offset point is raferred to the step with the digital code 000, and the gain point is referred to the step with
.
.
the digital code 111 •
Figure 4. Adjustment In Offset Point and Gain Point for an ADC
1-18
~I
TEXAS
NSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
----------------~
7
/ ; ' ' ' Oaln Point
6
.,,;/
I
Y
1
1
.I
,./
/~/
.
•
/ /
,
1
1
1
1
/
/
/
/
/
/
1
/
/ /
/ /'
/
/
/
11
1
Ideal Straight Line
/
'
1
1
//
/
Offset Point
Digital Input Code
(a) BEFORE ADJUSTMENT
7
----------------~
7
¥
6
--------------~~;~
~
The difference between the actual midstep value or step value and the nominal midstep value or step value,
respectively, at specified zero scale.
NOTE:
Normally, this error specification is applied to converters that have no arrangement for an external
adjustment of offset error and gain error.
5. Dynamic and Sigma-Delta Definitions
Resolution
The number of different outpt:t codes possible. Expressed as N, where 2N is the number of available output
codes.
Dynamic Range
The ratio of the largest allowable input signal to the noise floor.
Total Harmonic Distortion
The ratio of the rms sum of all harmonics to the rms value of the largest allowable input signal. Units in dB's.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
1-33
....
GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Signal to Intermodulatlon Distortion
The ratio of the rmssum of two input signals. to the rms sum of all discernible intermodulation and harmonic
distortion products.
Linearity Error
a
The deviation of code from a straight line passing through the endpoints of the transfer function after zeroand full-scale errors have been accounted for. Zero-scale is a point 1/2 LSS below the first code transition and
full-scale is a point 1/2 LSS beyond the code transition to all ones. The deviation is measured from the middle
of each particular code. Units in %FS.
Differential Nonlinearity
The deviation of a code's width from the ideal width in LSS's.
Positive Full Scale Error
The deviation of the last code transition from the ideal, (Vref - 1.5 LSB).
Positive Full Scale Drift
The drift in effective, positive, full-scale input voltage with temperature.
Negative Full Scale Error
The deviation of the first code transition from the ideal, (-Vref + 0.5 LSB).
Negative Full Scale Drift
The drift in effective, negative, full-scale input voltage with temperature.
Bipolar Offset
The deviation of the midscale transition from the ideal. The ideal is defined as the middle transition lying on a
straight line between actual positive full-scale and actual negative full-scale.
Bipolar Offset Drift
The drift in the bipolar offset error with temperature.
Absolute Group Delay
The delay through the filter section of the part.
Passband Frequency
The upper -3 dB frequency.
~TEXAS
1-34
INSTRUMENTS
POST OFFICE BOX 656303 • DAUAS. TEXAS 75265
....
2-1
.
C)
(I)
::s
(I)
;
-"tJ
c...
'"C
o
en
(I)
l>
C
oen
2-2
..
ICL7135C, TLC7135C
4 1/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTERS
SLAS074A- DECEMBER 1986- REVISED MAY 1995
• Zero Reading for O-V Input
• Precision Null Detection With True Polarity
at Zero
• 1-pA Typical Input Current
• True Differential Input
• Multiplexed Binary-Coded-Declmal (BCD)
Output
• Low Rollover Error: ± 1 Count Max
• Control Signals Allow Interfacing With
UARTs or Microprocessors
• Autoranglng Capability With Over-and
Under-Range Signals
NPACKAGE
(TOP VIEW)
VCCREF
ANLGCOMMON
INTOUT
AUTO ZERO
BUFF OUT
CrelCref+
ININ+
1
4
7
8
9
10
VCC+
D5
B1
B2
• TTL-Compatible Outputs
• Direct Replacement for Teledyne TSC7135,
Intersll ICL7135, Maxim ICL7135, and
Silicon Ix SI7135
23
22
21
20
19
UNDER RANGE
OVER RANGE
STROBe
RUN/HOLD
DGTLGND
POLARITY
CLK
BUSY
D1
D2
D3
D4
B8
B4
• CMOS Technology
description
The ICL7135C and TLC7135C converters are manufactured with Texas Instruments highly efficient CMOS
technology. This 4 1/2-digit, dual-slope-integrating, analog-to-digital converter (DAC) is designed to provide
interfaces to both a microprocessor and a visual display. The digit-drive outputs 01 through 04 and multiplexed
binary-coded-decimal outputs B1, B2, B4, and B8 provide an interface for LED or LCD decoder/drivers as well
as microprocessors.
The ICL7135C and TLC7135C offer 50-ppm (one part in 20,000) resolution with a maximum linearity error of
one count. The zero error is less than 10 IJ.V and zero drift is less than 0.5IJ.V/oC. Source-impedance errors are
minimized by low input current (less than 10 pAl. Rollover error is limited to ± 1 count.
The BUSY, STROBE, RUN/HOLD, OVER RANGE, and UNDER RANGE control signals support
microprocessor-based measurement systems. The control signals also can support remote data acquisition
systems with data transfer through universal asynchronous receiver transmitters (UARTs).
The ICL7135C and TLC7135C are characterized for operation from O°C to 70°C.
AVAILABLE OPTIONS
PACKAGE
TA
O·Cto 70·C
PLASTIC DIP
(N)
ICL7135CN
TlC7135CN
Caution. These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam
during storage or handlilng to prevent electrostatic damage to the MeS gates.
-!llExAs
INSTRUMENTS
POST OFFICE BOX 856303 • OALLAS. TEXAS 75265
Copyright --""-+-----<'----I--.....--<:r O-i---t~=====r-----'
3
I
I
I
I
Section
~
AlZ
Input
low
L ___________________
IN-~
~TEXAS
2-4
I
I
I
I
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
.
~
..
-~
ICL7135C, TLC7135C
4 1/2-DIGIT PRECISION
ANALOG-TO-DIGITAL CONVERTERS
SLAS074A- DECEMBER 1986- REVISED MAY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted}t
Supply voltage (Vcc+ with respect to Vcc-) ................................................. 15 V
Analog input voltage (IN- or IN+) ................................................... VCC- to Vcc+
Reference voltage range ........................................................... VCC- to VCC+
Clock input voltage range ............................................................ a V to Vcc+
Operating free-air temperature range, TA .............................................. aoc to 7aoC
Storage temperature range, Tstg .................................................. -65°C to 15aoC
Lead temperature 1,6 mm (1/16 inch) from case for 1a seconds: N package ..................... 26aoC
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
Supply voltage. VCC+
4
5
6
UNIT
V
Supply voltage. VCC-
-3
-5
-8
V
1
Reference voltage. Vref
V
2.8
High-level input voltage, ClK, RUN/HOLD, VIH
V
low-level input voltage. ClK. RUN/HOLD. Vil
Differential input voltage, VIO
VCC-+l
1.2
Maximum operating frequency, fclock (see Note 1)
0.8
V
VCC+-0.5
V
2
MHz
0
Operating free-air temperature range, TA
·C
70
NOTE 1: Clock frequency range extends down to 0 Hz.
electrical characteristics, VCC+
otherwise noted)
=5 V, VCC- =5 V, Vref =1 V, fclock =120 kHz, TA =25°C (unless
TEST CONDITIONS
PARAMETER
VOH
High-level output voltage
MIN
TYP
MAX
101 -05,61,62,64,68
10=-1 mA
2.4
5
I Other outputs
10 =-10 pA
4.9
5
Val
low-level output voltage
10=1.6mA
VON(PP)
Peak-ta-peak output noise voltage (see Note 2)
VID = 0,
avo
IIH
UNIT
V
0.4
V
Full scale = 2 V
15
Zero-reading temperature coefficient of output voltage VID = 0,
High-level input current
VI =5V,
O·C S TA S 70·C
0.5
2
O·C S TA S 70·C
0.1
10
pA
III
low-level input current
VI=OV,
O·C S TA S 70·C
-0.02
-0.1
mA
II
Input leakage current, IN - and IN +
VIO-O
ICC+
Positive supply current
fclock = 0
ICC-
Negative supply current
fclock- 0
Cpd
Power dissipation capacitance
See Note 3
.
.
TA=25·C
1
O·C STA S 70·C
TA=25·C
ILV/·C
10
250
1
0·CSTAS70·C
TA=25·C
O·C S TA S 70·C
ILV
2
3
-0.8
-2
-3
40
pA
mA
mA
pF
NOTES: 2. ThiS IS the peak-to-peak value that IS not exceeded 95% of the time .
3. Factor-relating clock frequency to increase in supply current. At VCC+ - 5 V, ICC+ • ICC+(fclock - 0) + Cpd x 5 V x fclock
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-5
.
ICL7135C, TLC7135C
4 1/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTERS
SLAS074A':" DECEMBER 1986 - REVISED MAY 1995
ollerating characteristics, Vcc+ = 5 V, Vcc- = 5 V, Vref = 1 V, fclock = 120 kHz, TA =.25°C (unless
otherwise noted)
. .
PARAMETER
TEST CONDITIONS
aFS
Full-scale temperature coefficient (see Note 4)
EL
Unearity error
0·CSTAS70·C
VID-2V,
-2VSVIDS2V
MIN
ED
Differential linearity error (see Note 5)
-2VSVIDS2V
EFS
± Full-scale symmetry error (rollover error) (see Note 6)
VID=±2V
Display reading with O-V input
VID-O,
Display reading in ratiometric operation
TA-25·C
VID= Vref,
0·CSTAS70·C
TYP
MAX
5
0.5
count
0.01
LSB
0.5
1
0.9998
0.9999
0.9995
0.9999
1.0000
Digital
1.0005 Reading
timing diagrams
~
End of Conversion
rS_ _ _ _ _ _ _-:--_ _ _ _ _ _ _ __
I
I
.1
STROBEtl
I-
I
DS.J
.1
I-
D4
200 Counts
T T
200 Counts
I
200 Counts
201 Counts
II-
I-
I
.1
D3
200 Counts
L
.1
r
.1
I-
D2
200 Counts
I-
I
.I
I
D1
200 Counts
I-
.1
t Delay between BUSY going low and the first STROBE pulse is dependent upon the analog inpul
Figure 1
~1EXAS
2-6
INSTRUMENTS
POST OFFICE BOX 865303 • DALLAS. TEXAS 75266
count
Digital
-0.0000 ±0.0000 0.0000 Reading
0·CsTAS70·C
NOTES: 4. This pl!.rameter IS measured with an external reference haVing a temperature coefficient of less than 0.01 ppml"C.
5. The magnitude of the difference between the worst case step of adjacent counts and the ideal step.
6. Rollover error is the difference between the absolute values of the conversion for 2 V and -2 V.
BUSYt~
UNIT
pprilrC
..
ICL7135C, TLC7135C
4 1/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTERS
SLAS074A- DECEMBER 1986 - REVISED MAY 1995
timing diagrams (continued)
Digital Scan
for OVER.RANGE
M
M
,..,
D5
L..--
I L.....-...I L--...I
~D4
~D3
~D2
:--_.....II!-_---InL.-_ _ D1
1000 Counts
I..
.1
Figure 2
Intagrator Output
AUTO ZERO
10,001 Counts
Signalint
1"0,000
D.lntagrata
20,001 Counts Max
Counts
Full Measurement Cycle
40,002 Counts
BUSY
OVER RANGE ~
When Applicable
UNDER RANGE ~
When Applicable .A~-'~...:iroA
_ _ _ _ _ _ _ _ _ _ _----I
Figure 3
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75285
.
ICL7135C, TLC7135C
4 1/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTERS
SLAS074A- DECEMBER 1986 - REVISED MAY 1995
timing diagrams (continued)
STROBE
IIIII
II+- AUTO ZERO
Digit Scan
for OVER RANGE
n
Dst
~':'--------I',
n
'\-,- - - - - !
.Jl~D..;..4_ _ _ _---'I
',I
,
--I1:.;;;D,;,.3_ _ _ _-II(
-.ll~D;;;..2_ _ _---'Ir f
J;
__...nD1
~
J
Signal Integrate ~ Delntegratet
II
n
L.._ _
n rLn fln rt.
n r
t First 05 of AUTO ZERO and deintegrate is one count longer.
Figure 4
PRINCIPLES OF OPERATION
A measurement cycle for the ICL7135C and TLC7135C consists of the following four phases.
1. Auto-Zero Phase. The internal IN + and IN- inputs are disconnected from the terminals and internally
connected to ANLG COMMON. The reference capacitor is charged to the reference voltage. The
system is configured in a closed loop and the auto-zero capacitor is charged to compensate for offset
voltages in the buffer amplifier, integrator, and comparator. The auto-zero accuracy is limited only by the
system noise, and the overall offset, as referred to the input, is less than 10 !lV.
2. Signal Integrate Phase. The auto-zero loop is opened and tne internal IN+ and IN- inputs are
connected to the external terminals. The differential voltage between these inputs is integrated for a
fixed period of time. When the input signal has no return with respect to the converter power supply, INcan be tied to ANLG COMMON to establish the correct common-mode voltage. Upon completion of this
phase, the polarity of the input signal is recorded.
3. deintegrate Phase. The reference is used to perform the deintegrate task. The internal IN- is internally
connected to ANLG COMMON and IN+ is .connected across the previously charged reference
capacitor. The recorded polarity of the input signal ensures that the capacitor is connected with the
correct polarity so that the integrator output polarity returns to zero. The time required for the output to
return to zero is proportional to the amplitude of the input signal. The return time is displayed as a digital
reading and is determined by the equation 10,000 x (VUYVref). The maximum or full-scale conversion
occurs when VIO is two times Vref.
4. Zero Integrator Phase. The internal IN- is connected to ANLG COMMON. The system is configured in a
closed I.oop to cause the integrator output to return to zero. Typically, this phase requires 100 to 200
clock pulses. However, after an over-range conversion, 6200 pulses are required.
~TEXAS
2-8
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
...
-
ICL7135C, TLC7135C
4 1/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTERS
SLAS074A - DECEMBER 1986 - REVISED MAY 1995
PRINCIPLES OF OPERATION
description of analog circuits
Input signal range
The common mode range of the input amplifier extends from 1 V above the negative supply to 1 V below the
positive supply. Within this range, the common-mode rejection ratio (CMRR) is typically 86 dB. Both differential
and common-mode voltages cause the integrator output to swing. Therefore, care must be exercised to ensure
that the integrator output does not become saturated.
analog common
Analog common (ANLG COMMON) is connected to the internal IN- during the auto-zero, deintegrate, and zero
integrator phases. When IN- is connected to a voltage that is different than analog common during the signal
integrate phase, the resulting common-mode voltage is rejected by the amplifier. However, in most applications,
IN- is set at a known fixed voltage (i.e., power supply common for instance). In this application, analog common
should be tied to the same point, thus removing the common-mode voltage from the converter. Removing the
common-mode voltage in this manner slightly increases conversion accuracy.
reference
The reference voltage is positive with respect to analog common. The accuracy of the conversion result is
dependent upon the quality of the reference. Therefore, to obtain a high accuracy conversion, a high quality
reference should be used.
.
deSCription of digital circuits
RUN/HOLD Input
When RUN/HOLD is high or open, the device continuously performs measurement cycles every 40,002 clock
pulses. When this input is taken low, the integrated circuit continues to perform the ongoing measurement cycle
and then hold the conversion reading for as long as the terminal is held low. When the terminal is held low after
completion of a measurement cycle, a short positive pulse (greater than 300 ns) initiates a new measurement
cycle. When this positive pulse occurs before the completion of a measurement cycle, it will not be recognized.
The first STROBE pulse, which occurs 101 counts after the end of a measurement cycle, is an indication of the
completion of a me asurement cycle. Thus, the positive pulse could be used to trigger the start of a new
measurement after the first STROBE pulse.
"'STFoRnO-=B;";;oE Input
Negative going pulses from this input transfer the BCD conversion data to external latches, UARTs. or
microprocessors. At the end of the measurement cycle, STROBE goes high and remains high for 201 counts.
The most significant digit (MSD) BCD bits are placed on the BCD terminals. After the first 101 counts, halfway
through the duration of output D1-D5 going high, the STROBE terminal goes low for 1/2 clock pulse width. The
placement of the STROBE pulse at the midpoint of the D5 high pulse allows the information to be latched into
an external device on either a low-level or an edge. Such placement of the STROBE pulse also ensures that
the BCD bits for the second MSD are not yet competing for the BCD lines and latching of the correct bits is
ensured. The above process is repeated for the second MSD and the D4 output. Similarly, the process is
repeated through the least significant digit (LSD). Subsequently, inputs D5 through D1 and the BCD lines
continue scanning without the inclusion of STROBE pulses. This subsequent continuous scanning causes the
conversion results to be continuously displayed. Such subsequent scanning does not occur when an over-range
condition occurs.
~ThxAs
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-9
•
ICl7135C,TLC7135C
4 1/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTERS
SLAS074A- DECEMBER 1986 - REVISED MAY 1Q96
PRINCIPLES OF OPERATION
BUSY output
The BUSY output goes high at the beginning of the signal integrate phase. BUSY remains high until the first clock
pulse after zero crossing or at the'end of the measurement cycle when an over-range condition occurs. It is
possible to use the BUSY terminal to serially transmit the conversion result. Serial transmission can be
accomplished by ANDing the BUSY and CLOCK signals and transmitting the ANDed output. The transmitted
output consists of 10,001 clock pulses, which occur during the signal integrate phase, and the number of clock
pulses that occur during the deintegrate phase. The conversion result can be obtained by subtracting 10,001
from the total number of clock pulses.
OVER-RANGE output
When an over-range condition occurs, this terminal goes high after the BUSY signal goes low at the end of the
measurement cycle. As previously noted, the BUSY signal remains high until the end of the measurement cycle
when an over-range condition occurs. The OVER RANGE output goes high at the end of BUSY and goes low
at the beginning of the deintegrate phase in the next measurement cycle.
UNDER-RANGE output
At the end of the BUSY signal, this terminal goes high when the conversion result is less than or equal to 9%
(count of 1800) of the full-scale range. The UNDER RANGE output is brought low at the beginning of the signal
integrate phase of the next measurement cycle.
POLARITY output
The POLARITY output is high for a positive input signal and updates at the beginning of each deintegrate phase.
The polarity output is valid for all inputs including ±O and OVER RANGE Signals.
dlglt-drlve (01, 02, 04 and 05) outputs
Each digit-drive output (01 through 05) sequentially goes high for 200 clock pulses. This sequential process
is continuous unless an over-range occurs. When an over-range occurs, all of the digit-drive outputs are blanked
from the end of the strobe sequence until the beginning of the deintegrate phase (when the sequential digit-drive
activation begins again). The blanking activity during an over-range condition can cause the display to flash and
indicate the over-range condition.
BCD outputs
The BCD bits (B1 , B2, B4 and B8) for a given digit are sequentially activated on these outputs. Simultaneously,
the appropriate digit-drive line for the given digit is activated.
system aspects
Integrating resistor
The value of the integrating resistor (RINT) is determined by the full-scale input voltage and the output current
of the integrating amplifier. The inte,grating amplifier can supply 20 J.iA of current with negligible nonlinearity. The
equation for determining the value of this resistor is:
R
_ Full Scale Voltage
INT - l i N T
Integrating amplifier current, liNT, from 5 to 40 J.iA yields good results. However, the nominal and recommended
current is 20 J.iA.
~1ExAs
2-10
INSTRUMENTS
POST OFFICE BOX 6S5303 • DALlAS. TEXAS 75265
ICL7135C,TLC7135C
4 1/2·DIGIT PRECISION
ANALOG·TO-DIGITAL CONVERTERS
SLAS074A- DECEMBER 1986 - REVISED MAY 1996
PRINCIPLES OF OPERATION
Integrating capacitor
The product of the integrating resistor and capacitor should be s.elected to give the maximum voltage swing
without causing the integrating amplifier output to saturate and get too close to the power supply voltages. When
the amplifier output is within 0.3 V of either supply. saturation occurs. With ±5-V supplies and ANLG COMMON
connected to ground. the designer should design for a ±3.5-V to ±4-V integrating amplifier swing. A nominal
capacitor value is 0.47 jJf. The equation for determining the value of the integrating capacitor (CINT) is:
CINT
10.000 x Clock Period x liNT
Integrator Output Voltage Swing
Where:
liNT is nominally 20 !lA.
Capacitors with large tolerances and high dielectric absorption can induce conversion inaccuracies. A capacitor
that is too small could cause the integrating amplifier to saturate. High dielectric absorption causes the effective
capacitor value to be different during the signal integrate and deintegrate phases. Polypropylene capacitors
have very low dielectric absorption. Polystyrene and polycarbonate capacitors have higher dielectric
absorption. but also work well.
auto-zero and reference capacitor
Large capaCitors tend to reduce noise in the system. Dielectric absorption is unimportant except during power
up or overload recovery. Typical values are 1 jJf.
reference voltage
For high-accuracy absolute measurements. a high quality reference should be used.
rollover resistor and diode
The ICL7135C and TLC7135C have a small rollover error; however. it can be corrected. The correction is to
connect the cathode of any silicon diode to INT OUT and the anode to a resistor. The other end of the resistor
is connected to ANLG COMMON or ground. For the recommended operating conditions. the resistor value is
100 kn This value may be changed to correct any rollover error that has not been corrected. In many noncritical
applications the resistor and diode are not needed.
m~xlmum
clock frequency
For most dual-slope AID converters. the maximum conversion rate is limited by the frequency response of the
comparator. In this circuit. the comparator follows the integrator ramp with' a 3-JIS delay. Therefore, with a
160-kHz clock frequency (6-JIS period). half of the first reference integrate clock period is lost in delay. Hence,
the meter reading changes from 0 to 1 with a 5D-IlV input, .1 to 2 with a 150-IlV input, 2 to 3 with a 25D-llV input,
etc. This transition at midpoint is desirable; however. when the clock frequency is increased appreciably above
160 kHz, the instrument flashes 1 on noise peaks even when the input is shorted. The above transition pOints
assume a 2-V input range is equivalent to 20.000 clock cycles.
When the input signal is always of one polarity, comparator delay need not be a limitation. Clock rates of 1 MHz
are possible since nonlinearity and noise do not increase substantially with frequency. For a fixed clock
frequency. the extra count or counts caused by comparator delay are a constant and can be subtracted out
digitally.
~ 1ExAs ;
="1
NSlRUMENTS
POST OFFICE sox 865303 • DALLAS. TEXAS 75266
2-11
...
ICL7135C/TLC7135C
4 1/2·DIGITPRECISION
ANALOG-TO"DIGITAL CONVERTERS
SLAS074A- DECEMBER 1986 ~ REVISED MAY 1995
PRINCIPLES OF OPERATION
maximum clock frequency (continued)
For signals with both polarities, the clock frequency can be extended above 160 kHz without error .by using a
low value resistor in series with the integrating capaCitor. This resistor causes the integrator to jump slightly
towards the zero-crossing level at the beginning of the deintegrate phase, and thus compensates for the
comparator delay. This series resistor should be 10 n to 50 n. This approach allows clock frequencies up to
480 kHz.
.
minimum clock frequency
The minimum clock frequency limitations result from capaCitor leakage from the auto-zero and reference
capacitors. Measurement cycles as high as 10 ~ are not influenced by leakage error.
rejection of 50-Hz or 60-Hz pickup
To maximize the rejection of 50~Hz or 60-Hz pickup, the clock frequency should be chosen so that an integral
multiple of 50-Hz or 6D-Hz periods occur during the signal integrate phase. To achieve rejection of these signals,
some clock frequencies that can be used are:
50 Hz: 250, 166.66, 125, 100 kHz, etc.
60 Hz: 300, 200,150,120,100,40,33.33 kHz, etc.
zero-crossing flip-flop
This flip-flop interrogates the comparator's zero-crossing status. The interrogatiQn is performed ·after the
previous clock cycle and the positive half of the ongoing clock cycle has occurred, so any comparator transients
that result from the clock pulses do not affect the detection of a zero-crossing. This procedure delays the
zero-crossing detection by one clock cycle. To eliminate the inaccuracy, which is caused by this delay, the
counter is disabled for one clock cycle at the beginning of the deintegrate phase. Therefore, when the
zero-crossing is detected one clock cycle later than the zero-crossing actually occurs, the correct number of
counts is displayed.
..
nOise
The peak-ta-peak noise around zero i~ approximately 151!V (peak-to-peak value not exceeded 95% ofthe time).
Near full scale, this value increases to approximately 30 I!V. Much of the noise originates in the auto-zero loop,
and is proportional to the ratio of the input signal to the reference.
analog and digital grounds
For high-accuracy applications, ground loops must be avoided. Return currents from digital circuits must not
be sent to the analog ground line.
power supplies
The ICL7135C and TLC7135C are designed to work with ±5-V power supplies. However, 5-V operation is
possible when the input signal does not vary more than ±.1.5 V from midsupply.
~TEXAS
2-12
IN~UMENTS
POST OFACE BOX fl56303 • DALLAS. TEXAS 75266
..
---
TLC5401, TLC5411
8-BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A - OCTOBER 1983 - REVISED MARCH 1995
• B-Blt Resolution AID Converter
• Microprocessor Peripheral or Stand·Alone
Operation
• On·Chlp 12-Channel Analog Multiplexer
ow OR N PACKAGE
(TOP VIEW)
INPUT AO
INPUT Al
INPUT A2.
INPUT A3
INPUT A4
INPUT A5
INPUT A6
INPUT A7
INPUT AS
GND
•
•
•
•
Built·ln Self·Test Mode
Software-Controllable Sample and Hold
Total Unadjusted Error ..• ±O.5 LSB Max
TLC541 Is Direct Replacement for Motorola
MC145040 and National Semiconductor
ADC0811. TLC540 is Capable of Higher
Speed
• Pinout and Control Signals Compatible
with TLC1540 Family of 100Bit AID
Converters
PARAMETER
TLC540
TLC541
2 lIS
9 lIS
75 x 103
12.5mW
3.6 lIS
17 lIS
40 x 103
12.5mW
6
9
14
13
12
11
FNPACKAGE
(TOP VIEW)
• CMOS Technology
Channel Acquisition Sample TIme
Conversion TIme (Max)
Samples per Second (Max)
Power DISSipation (Max)
3
VCC
SYSTEM CLOCK
I/O CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+
REFINPUT Al0
INPUT A9
description
INPUT A3
4 3 2 1 20 1918
I/O CLOCK
The TLC540 and TLC541 are CMOS AID
17 ADDRESS INPUT
INPUTA4
5
converters
built
around
an
8-bit
16 DATAOUT
INPUTA5
6
switched-capacitor successive-approximation
15 CS
INPUT A6
7
AID converters. They are designed for serial
INPUT A7
8
14 REF+
interface to a microprocessor or peripheral via "a
9 1011 1213
3-state output with up to four control inputs,
including independent SYSTEM CLOCK, I/O
CLOCK, chip select (CS), and ADDRESS
INPUT. A 4-MHz system clock for the TLC540
and a 2. 1-MHz system clock for the TLC541 with
a design that includes simultaneous read/write
operation allow high-speed data transfers and sample rates of up to 75,180 samples per second for the TLC540
and 40,000 samples per sec6nd for the TLC541. In addition to the high-speed converter and versatile control
logic, there is an on-Chip 12-channel analog multiplexer that can be used to sample anyone of 11 inputs or an
internal self-test voltage, and a sample-and-hold that can operate automatically or under microprocessor
control. Detailed information on interfacing to most popular microprocessors is readily available from the factory.
AVAILABLE OPTIONS
PACKAGE
TA
-40·C to 85·C
SO PLASTIC OIP
(oW)
PLASTICOIP
(N)
CHIP CARRIER
(FN)
TLC5401DW
TLC541IDW
TLC540IN
TLC541IN
TLC540lFN
TLC5411FN
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-13
•
TLC5401, TLC5411
8-BITANALOG·TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A - OCTOBER 1983 - REVISED MARCH 1995
description (continued)
The converters incorporated in the TLC540 and TLC541 feature differential high-impedance reference inputs
, that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises. A
switched-capacitor design allows low-error (±O.5 LSB) conversion in 9 !is for the TLC540 and 17 !is for the
TLC541 over the full operating temperature range.
The TLC5401 and TLC541I are characterized for operation from -4boC to 85°C.
functional block diagram
REF+
REF-
f4 f3
-+
AO
A1
A2
A3 ~
A4 ~
A5 ~
A8
A7 ~
A8 9
A9
A10
-+
-+
Analog
Inputs
-+
I-+-
Sample
and
Hold
r--
12-Channel
Analog
Multiplexer
11
~
12
-=-
....
I
I
Self-Test
Reference
I
I
I
ADDRESS 17
INPUT
I
Input
Address
Register
I
I
2
Output
Data
Reglater
~
8-to-1 Date
Selector
and Driver
r-!!-
DATA
OUT
Control Logic
and 1/0
Countars
±
I/O 18
CLOCK
CS
8
4
4
Input
Multiplexer
8-81t
Analog-ta-Dlgltal
Converter
(Switched-Capacitors)
15
SYSTEM 19
CLOCK
typical equivalent Inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
INPUT
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 knTYP
AO-A10~
I
INPUT
=
01 60pFTYP
.(equivalent Input
cepacltance)
AO-A10~.
~1ExAs
2-14
INSTRUMENTS
POST OFFICE BOX e55303 • DALlAS. TEXAS 75265
. J
5 MCTYP
TLC5401, TLC541I
8·BIT ANALOG·TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A - OCTOBER 1983 - REVISED MARCH 1995
operating sequence
I/O
CLOCK
I1 I2 I3 I4 I5 I6 I7 I8
~
141
es ~
See Note A
+---------f'r
--I I
J+-
Sample
CycieC
~
1
;
1 - - - - - -.. . ,.
1
1
r0-
,\-I'
fr-';
LSB
'~
.
Access
CycleC
j+-- twH(CS) ----.j MSB
Don't care
1\
LSB
Don't Care
1
1
H_I._ZStete~~
IX>__
A7
_ _ Previous Conversion Data A --+
MSB
LSB MSB
(See Note B)
...- - - - Conversion Data B
MSB
LSB
~
MSB
NOTES: A. The conversion cycle, which requires 36 system clock periods, is initiated on the 8th falling edge of 1/0 CLOCK after CS goes low
for the channel whose address exists in memory at that time. If CS is kept low during conversion, I/O CLOCK must remain low for
at least 36 system clock cycles to allow conversion to be completed.
B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven bits
(A6-AD) will be clocked out on the first seven I/O CLOCK falling edges.
C. To minimize errors caused by noise at CS, the internal Circuitry waits for three system clock cycles (or less) after a chip select falling
edge is detected before responding to control input signals. Therefore, no attempt should be made to clock·in address data until the
minimum chip-select setup time has elapsed.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ........................................................... 6.5 V
Input voltage range, VI (any input) ...........•...........•..............•...... -0.3 V to Vee +0.3 V
Output voltage range, Vo ..................................................... -0.3 V to Vee +0.3 V
Peak input current range (any input) ....................................................... ± 10 mA
Peak total input current (all inputs) ........•................................................ ±30 mA
Operating free-air temperature range, TA: TLC540l, TLC541I .......................... -40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to 150°C
Case temperature for 10 seconds: FN package ..................................•............. 260°C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds: OW or N package ................ 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted).
~TEXAs
INSTRUMENTS
POST OFFICE BOX 655303 • OAUAS. TEXAS 75265
2-15
TLC5401, TLC5411
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A- OCTOaER 1983 - REVISED MARCH 1995
recommended operating conditions
TLC541
TLC540
MIN
Supply voltage, Vee
Positive reference voltage, Vref+ (see Note 2)
MAX
MIN
5.5
4.75
4.75
5
2.5
Vee
0
Vec+O.l
2.5
VCC
-0.1
Negative reference voltage, Vref- (see Note 2)
NOM
Differential reference voltage, Vref+ - Vref- (see Note 2)
1
Analog input voltage (see Note 2)
0
High-level control input voltage, VIH
2
Low-level control input voltage, VIL
2.5
tsu(A~
Hold time, address bits after 110 CLOCKi, th(Al
Setup time, CS low before clocking in first address bit,
tsu(CS) (see Note 3)
CS high during conversion, twH(eS)
Pulse duration, SYSTEM CLOCK frequency, fclock(SYSl
5
5.5
UNIT
V
V
-0.1
Vec+0.2
1
VCC+0.2
V
VCC
0
VCC
V
VCC
V
V
2
0.8
V
200
400
0
0
ns
3
3
System
clock
cycles
36
36
System
clock
cycles
0
110 CLOCK frequency, fclock(IIO}
MAX
VCC VCC+O.l
0
2.5
0.8
Setup time, address b~s at data inpUt before 110 CLOCKi,
NOM
2.048
4
0
fclock(IIOl
210
ns
1.1
MHz
2.1
MHz
Pulse duration, SYSTEM CLOCK high, twH(SYS)
fclocklllOl
110
Pulse duration, SYSTEM CLOCK low, twL(SYS)
100
190
Pulse duration, 110 clock high, twH(IIO)
200
404
ns
Pulse duration, I/O clock low, twL(I/Ol
200
404
ns
System
Clock transition time
(see Note 4)
110
Operating free-air
temperature, TA
MHz
MHz
30
fclock(SYSl $ 1048 kHz
30
fclock(SYS) > 1048 kHz
20
20
fclock(l/Ol $ 525 kHz
100
100
fclock(IIO) > 525 kHz
40
40
TLC5401, TLC541 I
-40
85
-40
85
ns
·C
NOTES: 2. Analog Input voltages greater than that applied to REF + convert as all "l"s (11111111), while Input voltages less than that applied
to REF- convert as all "O·s (00000000). For proper operation, REF+ voltage must be at least 1 V higher than REF- voltage. Also,
the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
3. To minimize errors caused by noise at CS, the internal circuitry wa~ for three SYSTEM CLOCK cycles (or less) after a chip select
falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in an address until
the minimum chip select setup time has elapsed.
4. This Is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2 lIS for remote data acquisition
applications where the sensor and the AID converter are placed several feet away from the controlling microprocessor.
~TEXAS
2-16
INSTRUMENTS
POST OFFICE BOX 655303 • DALl.AS. TEXAS 75265
-
TLC5401, TLC541I
8-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS066A- OCTOBER
19~
- REVISED MARCH 1995
electrical characteristics over recommended operating temperature range, Vee = Vref+ = 4.75 V to
5.5 V, fcloCk(II0) 2.048 MHz forTLC540 or fclock(I/O) 1.1 MHz for TLC541 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP't MAX UNIT
=
=
IIA
VOH
High-level output voltage, DATA OUT
VCC-4.75V,
IOH =360
VOL
Low-level output voltage
VCC-4.75 V,
IOL= 1.6mA
0.4
IOZ
Off-state (high-impedance state) output current
VO=VCC,
VO=O,
CSatVcc
10
CSatVcc
-10
IIH
High-level input current
IlL
Low-level Input current
ICC
Operating supply current
VI=VCC
VI=O
CSatOV
Selected channel at Vcc,
Unselected channel at 0 V
Selected channel leakage current
ICC + Iref
Ci
Selected channel at 0 V,
Unselected channel at VCC
Supply and reference current
Input capacitance
Vraf+-VCC,
CSatOV
I Analog inputs
I Control inputs
2.4
V
V
IIA
0.005
2.5
-0.005
-2.5
IIA
IIA
1.2
2.5
mA
0.4
1
-0.4
-1
IIA
1.3
3
7
55
5
15
mA
pF
.t All tYPiCal values are at TA = 25°C.
~1EXAS
INSTRUMENTS
POST OFFICE eox 655303 • DALLAS. TEXAS 75265
2-17
TLC5401, TLC541I
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A- OCTOBER 1983 - REVISED MARCH 1995
operating characteristics over recommended operating free-air temperature range,
Vee =Vref+ -4.75 V to 5.5 V, fclock(1I0) 2~048 MHz for TLC540 or 1.1 MHz for TLC541 ,
fclock(SYS) 4 MHz for TLC540 or 2.1 MHz for TLC541
=
PARAMETER
=
TLCS40
MIN
MAX
TEST CONDITIONS
TLC541
MIN
UNIT
MAX
EL
Linearity error
See Note 5
±0.5
±0.5
LSB
EZS
Zero-scale error
S.ee Notes 2 and 6
±0.5
±0.5
LSB
EFS
Full-scale error
See Notes 2 and 6
±0.5
±0.5
LSB
Total unadjusted error
See Note 7
±0.5
±0.5
LSB
Self-test output code
Input All address. 1011,
(see Note~)
Conversion time
See Operating Sequence
9
17
Total access and conversion tima
See Operating Sequence
13.3
25
!conv
Ie
Channel acquisition time (sample cycle)
tv
Time output data remains valid after
1/0CLOCK.1
let
Delay time, I/O CLOCK.1 to data output
valid
len
Output enable time
letis
trlbus)
Output disable lima
01111101
(125)
10000011
(131)
01111101
(125)
4
See Operating Sequence
10
See Parameter
Measurement
Information
Data bus rise lime
10000011
(131)
4
jill
jill
I/O
clock
cylces
-
10
ns
300
400
ns
150
150
ns
150
150
ns
300
300
ns
ns
300
300
tf(bus) Data bus fall lime
NOTES: 2. Analog Input voltages greater than that applied to REF+ convert to all "l"s (11111111 ) while Input voltages les8 than that applied to
REF- convert to all "O"S (00000000). For proper operation, REF+ voltage must be at least 1 V higher than REF- voltage. Also, the
total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
5. Linearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
6. Zero-scale error is the difference between 00000000 and the converted output for zero Input voltage; full-scale error is the difference
between 11111111 and the converted output for full-lICaIe input voltage.
7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic.
~1ExAs
2-18
INSTRUMENTS
POST OFFICE BOX 655303 • 0ALlAS. TEXAS 75265
TLC5401, TLC5411
.a-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A - OCTOBER 1983 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
J
VCC
1.4V
kn
Output
Under Teet
CL
(see Note Al
Output
Under Test
Teet
Point
n
CL
(see Note A)
T
kn
Teet
Point
T
Output
Under Teet
CL
(see Note A)
3kn
Test
Point
T
See NoteB
See Note B
LOAD CIRCUIT FOR
!d. t" AND tf
;
LOAD CIRCUIT FOR
tpZH AND tPHZ
LOAD CIRCUIT FOR
tPZL AND tpLZ
t
VCC
:.t.. 50%
________ OV
I
I
SYSTEM
CLOCK
tPZL
Output Waveform 1
(see Note C)
--+!
I+-
----------1......,"1
1
See Note B
50%
I!\
~
tPZH---.!
1,--_ _-
15
Output waveform 2 _ _ _ _ _ _ _ _ _ _ _..J
(see Note C)
0%
~
tpLZ
K,:l .
Vcc
10%
~t~;--OV
....1
~----
::H
VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES
110 CLOCK
~---
\ . . : . - - - - - O.BV
I
'
I
I
-+I
~Id-.l
.IX-----------------
DATA OUT_ _ _ _ _ _
2.4 V
O.BV
---
I+-
2.4V
0.4V
tf
VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES
VOLTAGE WAVEFORMS FOR DELAY TIME
NOTES: A. CL - 50 pF for TLC540 and 100 pF for TLC541.
B. ten - tpZH or tpZL. !dis - tPHZ or tpLZ'
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 Is for an output with Internal conditions such that the output Is high except when disabled by the output control.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-19
.
TLC5401, TLC541I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
Sl,AS065A- OCTOI3ER 1983 - REVISED MARCH 1995
APPLICATIONS INFORMATION
simplified analog Input analysis
Using the equivalent circuit in Figure 1, the time required to charge the analog input capacitance from 0 to Vs
within 112 LSB can be derived as follows:
The capacitance charging voltage is given by
(1 )
where
Rt=RS+rj
The final voltage to 1/2 LSB is given by
Vc (1/2 LSB) = Vs - (Vs/512)
(2)
Equating equation 1 to equation 2 and solving for time to gives
Vs - (VS/512) = Vs(1_e-tc/RtCi)
(3)
and
to (1/2 LSB) = Rt x Cj x In(512)
(4)
Therefore, with the values 'liven the time for the analog input signal to settle is
to (112 LSB) = (Rs + 1 k.a) x 60 pF x In(512)
(5)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet 4
Rs
I
I
I
I
VI
•
TLC540/1
I'J
VS~VC
I 1kOMAX
I
!
:';,.M..
VI = Input Voltage et INPUT AO-A10
VS= External Driving Source Voltage
Rs = Source Resistance
rl = Input Resistance
CI = Equivalent Input Capacitance
t Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the Input frequency.
Figure 1. Equivalent Input Circuit Including the Driving Source
~1ExAs.
2-20
>
INSTRUMENTS
POST OFRCE BOX 655303 • DALLAS, TEXAS 75265
c
..
---
TLC5401, TLC5411
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A - OCTOBER 1983 - REVISED MARCH 1995
PRINCIPLES OF OPERATION
The TLC540 and TLC541 are each complete data acquisition systems on a single chip. They include such functions
as analog multiplexer, sample and hold, a-bit AID converter, data and control registers, and cont;'ollogic. For flexibility
and access speed, there are four control inputs [two clocks, chip select (CS), and address]. These control inputs and
a TTL-compatible 3-state output are intended for serial communications with a microprocessor or microcomputer.
With judicious interface timing, with TLC540 a conversion can be completed in 9 J.IS, while complete
input-conversion-output cycles can be repeated every 13 J.IS. With TLC541 a conversion can be completed in 17 J.IS,
while complete input-conversion-output cycles are repeated every 25 J.IS. Furthermore, this fast conversion can be
executed on any of 11 inputs or its built-in self-test and in any order desired by the controlling processor.
The system and I/O clocks are normally used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the device.
Once a clock signal within the specification range is applied to SYSTEM CLOCK, the control hardware and software
need only be concerned with addressing the desired analog channel, reading the previous conversion result, and
starting the conversion by using I/O CLOCK. SYSTEM CLOCK will drive the conversion crunching circuitry so that
the control hardware and software need not be concerned with this task.
When CS is high, DATA OUT is in a 3-state condition and ADDRESS INPUT and I/O CLOCK are disabled. This feature
allows each of these terminals, with the exception of CS, to share a control logic point with their counterpart terminals
on additional AID devices when additional TLC540/541 devices are used. In this way, the above feature serves to
minimize the required control logic terminals when using multiple AID devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain
the conversion result. A normal control sequence is:
1. CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges
and then a falling edge of SYSTEM CLOCK after a low CS transition, before the low transition is recognized.
This technique is used to protect the device against noise when the device is used in a noisy environment.
The MSB of the previous conversion result automatically appears on DATA OUT.
2. A new positive-logic multiplexer address is shifted in on the first four rising edges of I/O CLOCK. The MSB
of the address is shifted in first. The negative edges of these four I/O clock pulses shift out the second, third,
fourth, and fifth most significant bits of the previous conversion result. The on-chip sample and hold begins
sampling the newly addressed analog input after the fourth falling edge. The sampling operation basically
involves the charging of internal capacitors to the level of the analog input voltage.
3. Three clock cycles are then applied to I/O CLOCK and the sixth, seventh, and eighth conversion bits are
shifted out on the negative edges of these clock cycles.
4. The final eighth clock cycle is applied to I/O CLOCK. The falling edge of this clock cycle completes the
analog sampling process and initiates the hold function. Conversion is then performed during the next 36
system clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low for
at least 36 system clock cycles to allow for the conversion function.
CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple conversion,
special care must be exercised to prevent noise glitches on I/O CLOCK. If glitches occur on I/O CLOCK, the I/O
sequence between the microprocessor/controller and the device loses synchronization. Also, if CS is taken high, it
must remain high until the end of the conversion. Otherwise, a valid falling edge of CS causes a reset condition, which
aborts the conversion in progress.
A new conversion can be started and the ongoing conversion simultaneously aborted by performing steps 1 through
4 before the 36 system clock cycles occur. Such action yields the conversion result of the previous conversion and
not the ongoing conversion.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-21
.
TLC5401, TlC541I
8~BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A- OCTOBER 1983 - REVISED MARCH 1995
PRINCIPLES OF OPERATION
It is possible to connect SYSTEM CLOCK and 1/0 clock together in special situations in which controlling circuitry
points must be minimized. In this case, the following special points must be considered in addition to the requirements
of the normal control sequence previously described.
1. The first two clocks are required for this device to recognize CS is at a valid low level when the common clock
signal is used as an 1/0 CLOCK. When CS is recognized by the device to be at a high level, the common clock
signal is u$ed for the conversion clock also.
2. A low CS must be recognized before the 1/0 CLOCK can shift in an analog channel address. The device
recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a
negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address.
Also, upon shifting in the address, CS must be raised after the eighth valid (10 total) 1/0 CLOCK. Otherwise;
additional common clock cycles are recognized as I/O CLOCKS and will shift in an erroneous address.
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.'
This device accommodates these applications. Although the on-chip sample and hold begins sampling upon the
negative edge of the fourth valid 1/0 clock cycle, the hold function is not initiated until the negative edge of the eighth
valid 1/0 clock cycle. Thus, the control circuitry can leave the I/O clock signal in its high state during the eighth valid
1/0 clock cycle until the moment at which the analog signal must be converted. The TLC540ITLC541 continues
sampling the analog input until the eighth falling edge of the 1/0 clock. The control circuitry or software then
immediately lowers the 1/0 clock signal and holds the analog signal at the desired point in time and start conversion.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.
~1ExAs
2-22
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
TLC542C, TLC5421
8-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
FEBRUARY
• 8-Blt Resolution AID Converter
• Microprocessor Peripheral or Stand-Alone
Operation
• On-Chip 12-Channel Analog Multiplexer
• Built-In Self-Test Mode
• Software-Controllable Sample and Hold
• Total Unadjusted Error. •. ±O.S LSB Max
• Direct Replacement for Motorola
MC14S041
• On-Board System Clock
• End-of-Converslon (EOC) Output
• Pinout and Control Signals Compatible
With the TLC1S42/31o-BIt AID Converters
OW OR N PACKAGE
(TOP VIEW)
INPUTAO
INPUT A1
INPUT A2.
INPUT A3
INPUTA4
INPUT A5
INPUT A6
INPUT A7
INPUT AS
GND
16 JJS
Conversion Time (Max)
20 JJS
Power Dissipation (Max)
9
14
13
12
11
CI.. CI.. CI.. ()
0
~~~::>w
25 x 103
Samples per Second (Max)
4
~<~
~~~
=> => => () ()
VALUE
Channel Acquisition/Sample Time
VCC
EOC
1/0 CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+
REFINPUT A10
INPUT A9
FNPACKAGE
(TOP VIEW)
• CMOS Technology
PARAMETER
MARCH 1995
INPUT A3
10mW
INPUT A4
INPUT A5
INPUT A6
INPUTA7
description
4 3 2 1 201918
5
17
6
16
7
15
1/0 CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+
The TLC542 is a CMOS converter built around an
8 9 1011 12,j4
B-bit switched-capacitor successive-approximation
analog-to-digital converter. The device is designed
for serial interface to a microprocessor or peripheral
via a 3-state output with three inputs [including 1/0
CLOCK, CS (chip select), and ADDRESS INPUT].
The TLC542 allows high-speed data transfers and
sample rates of up to 40,000 samples per second.
In addition to the high-speed converter and versatile control logic, an on-chip 12-channel analog multiplexer can
sample anyone of 11 inputs or an.; internal "self-tesf' voltage, and the sample and hold is started under
microprocessor control. At the end of conversion, the end-of-conversion (EOC) output pin goes high to indicate
that conversion is complete. Detailed information on interfacing to most popular microprocessors is readily
available from the factory.
AVAILABLE OPTIONS
PACKAGE
TA
CHIP CARRIER
(FN)
O·Cto 70·C
TLC542CFN
TLC542CN
TLC542CDW
-40·C to 85·C
TLC5421FN
TLC5421N
TLC5421DW
PLASTICOIP
(N)
~TEXAS
SMALL OUTLINE
(OW)
Copyright © 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
2-23
.
TLC542C, TLC5421
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A - FEBRUARY 1989 - REVISED MARCH 1995
description (continued)
The converter incorporated in the TLC542 features differential high-impedance reference inputs that facilitate
ratio metric conversion, scaling, and isolation of analog circuitry from logic and supply noises. A switchedcapacitor design allows low-error (±0.5 LSS) conversion in 20 J1S over the full operating temperature range.
The TLC542C is characterized for operation from O°C to 70°C and the TLC5421 is characterized for operation
from -40°C to 85°C.
functional block diagram
-
Analog
Inputs
--
Sample and
Hold
~
..
I--
REF+
REF-
I
I
8-Blt
Analog-ta-Dlgltal
Converter
(Switched-Capacitors)
8
12-Channel
Analog
Multiplexer
Output
Data
Reglstar
M
-
Input Address
Reglstar
.,4..
8-to-1 Data
Salector and I - DATA
OUT
Driver
~
4
Y
Self-Test
Reference
I
4
Input
Multiplexer
ADDRESS
INPUT
110 CLOCK
2
Control Logic
and I/O
Counters
tI
t
..
CS
EOC
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
1 knTYP
INPUT ----"vV'v---]
AO-A10
...L
I
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
INPUT
=
CI 60 pFTYP
(equivalent Input
capacitance)
AO-A10~
~TEXAS
.INSTRUMENTS
2-24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
;h
5 MOTYP
TLC542C, TLC5421
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A - FEBRUARY 1989 - REVISED MARCH 1995
operating sequence
110
CLOCK~
tau(A) ....1 I+-
~:::
I
I I
--I i+--
I I (s88NoteA)
taCq
I .I
tau(CS) ~I
--+1
11
. , I
I
I
CS
1 II
,
I
I
I
I I
IMSB
LSB
I,
Don'tCare
ADDRESS ~
INPUT
DATA
OUT
"Il'I
I
I
I
:
I
I
I
I
I
I
I
I
i4-- Previous Conversion Date A ~
I
I
MSB
LSB.I
1
1,
14
I
:+--- tacq ------'II
r
iI
,........- - - - - - - - - -.......
HI-Z State
I
I I
121ntemal System ClockS S 121111
I
I
I (- Note B)
EOC
I+--
I
{
A
i4" Cy,=~ --l
~I +- tconv -+I
I
I
M~B
LSB
~
Don't Care
C3 C2 C1 CO _ - - - - - - -
I
Sea Note B
114 MSB
I~(EOC-DATA)-' ~
Conversion Date B _ _~~I
LSB
I
tcI(l/~OC)-+i~r---Jr----------""'L~
1cycle
NOTES: A. To minimize errors caused by noise at the chip select input, the intemal circuitry waits for two rising edges and one falling edge of
the intemal system clock after CS.!. before responding to control input signals. The CS setup time is given by the lsu(CS) specifications.
Therefore, no attempt should be made to clock·in an address until the minimum chip select setup time has elapsed.
B. The output is 3-stated on CS going high or on the negative edge of the eighth I/O clock.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) .......................................................... 6.5 V
Input voltage range (any input) .............................................. -0.3 V to Vee + 0.3 V
Output voltage range . . . . . . .. .. .. . . .. . . . . . . .. . .. .. . . ..... .. . .. .. . . . ... ... .. -0.3 V to Vee+ 0.3 V
Peak input current range (any input) . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •. ±20 mA
Peak total input current (all inputs) .................................... . . . . . . . . . . . . . . . . . . .. ±30 mA
Operating free-air temperature range: TLC542C ........................................ O°C to 70°C
TLC5421 ...................................... -40°C to 85°C
Storage temperature range ........... . . .. .. .. . .. .. . . . . . .. .. . .. .. . . .. .. .. . . . .. ... -65°C to 150°C
Case temperature for 10 seconds: FN package .. .. .. . . . . . .. .. .. . .. . .. .. . . .. . .. . . . . . . .. .. ... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: OW or N package ...•.....•.... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at theSe or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods. may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted).
~TEXAS
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265
2-25
•
TLC542C, TLC5421
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS.
SLAS076A- FEBRUARY 1989 - REVISED MARCH 1995
recommended operating conditions, Vee = 4.75 to 5.5 V
MIN
NOM
4.75
5
Vref-0.1
VCC
0
Differential reference voltage, Vref+ - Vref- (see Note 2)
1
VCC
Analog input voltage (see Note 3)
0
High-level control Input voltage, VIH
2
Supply voltage, VCC
Positive reference voltage, Vref+ (see Note 2)
Negative reference voltage, Vref- (see Note 2)
MAX
5.5
UNIT
VCC+O.1
V
Vref+
VCC +0.2
V
VCC
V
V
V
Low-level control input voltage, VIL
0.8
Setup time. address bRs at data input before 1/0 CLocKi, isu(A)
V
V
400
ns
Hold time, address bHs after 1/0 CLocKi. thffi)
0
ns
Hold time, CS low after 8th 1/0 CLOCKt, \hICS)
0
ns
3.8
Setup time, CS low before clocking in first address bit, isu(CS) (see Note 4)
1.1
0
Input/output clock frequency, fclock{l/Ql
Input/output clock high, twHIIIO)
404
Input/output clock low, twUIIOI
404
1/0 CLOCK transition time, tt (see Note 3)
Operating free-air temperature, TA
lIS
MHz
ns
ns
fclock(I/O) s 525 kHz
100
fclocklllO) > 525 kHz
TLC542C
40
TLC5421
0
-40
ns
70
·C
85
NOTES: 2. Analog Input voltages greater than that applied to REF+ convert as all ones (11111111). while Input voltages less than that applied
to REF- convert as all zeros (00000000). For proper operation, REF+ must be at least 1 V higher than REF-. Also, the total
unadjusted error may Increase as this differential reference voltage falls below 4.75 V.
3. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2 lIS for remote data acquisRion
applications where the sensor and the AID converter are placed several feet away from the controlling microprocessor.
4. To minimize errors caused by noise at the chip select input, the internal circuitry waits for two rising edges and one falling edge of
the internal system clock after CS .1. before responding to control input signals. The CS setup time is given by the isu(CS)
speCifications. Therefore, no attempt should be made to clock-in aCldress data until the minimum chip select setup time has elapsed.
electrical characteristics over recommended operating temperature range, Vee = Vref+ = 4.75 V to
5.5 V, fClock(1I0) = 1.1 MHz (unless otherwise noted)
.
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
VOH
High-level output voltage (DATA OUn
VCC = 4.75 V,
10H = -360 JJA
VOL
Low-level output voltage
VCC-4.75V,
IOL=1.6mA
Off-state (high-impedance state)
output current
VO-VCC,
cs at VCC
0.4
10
VO=O,
CSatVcc
-10
2.4
UNIT
V
V
JJA
IIH
High-level input current
VI-VCC
0.005
2
IlL
Low-level input current
-0.005
-2.5
JJA
JJA
ICC
Operating supply current
VI-O
CSatOV
2
mA
1.2
Selected channel leakage current
Selected at VCC,
Unselected channel at 0 V
Iref
Maximum static analog reference current into
REF+
Vref+= VCC,
Ci
Input capacitance
I O·C to 70 ·C
1- 40"C to 85·C
Vref-- GND
-0.4
JJA
10
JJA
I Analog inputs
7
55
1Control inputs
5
15
t All typical values are at TA = 25·C.
~TEXAS
2-26
0.4
INSTRUMENTS
POST OFFICE BOX EI55303 • DALLAS. TEXAS 75265 ;
pF
..
--
TLC542C, TLC5421
8-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A - FEBRUARY 1989 - REVISED MARCH 1995
operating characteristics over recommended operating free-air temperature range,
Vee Vref+ 4.75 to 5.5 V, fclock(I/O) 1 MHZ
=
=
=
PARAMETER
EL
Linearity error (see Note 5)
EZS
Zero-scale error (see Note 6)
Full-scale error (see Note 6)
EFS
TEST CONDITIONS
MIN
TYPt
MAX
UNIT
±C.5
LSB
See Note 2
±C.5
LSB
See Note 2
±C.5
LSB
±C.5
LSB
Total unadjusted error (see Note 7)
01111101
(126)
10000011
(130)
Self-test oulput code
InputA11 address = 1011,
See Note 8
Iconv
Conversion time
See operating sequence
20
J.LS
tcvcIe
taca
Total access and conversion cycle time
See operating sequence
40
J.LS
Channel acquisition time (sample cycle)
See operating sequence
16
tv
Time ouput data remains valid after 1/0 CLK.!. See FigureS
!dCIQ-DATA)
Delay time, I/O CLK.!. to data output valid
See Figure 5
400
ns
!delQ-EOC)
Delay time, 8th VO CLK.!. to EOC.!.
See Figure 6
500
ns
!d(EQC-DATA)
tpZH, tpZL
Delay time, EOCi to data out (MSB)
See Figure 7
400
ns
Delay time, CS.!. to data out (MSB)
See Figure 2
3.4
J.LS
tpHZ, tpLZ
Delay time, CSi to data out (MSB)
See Figure 2
150
ns
\reEOC)
tf(EOC)
Rise time
See Figure 7
100
ns
Fall time
See Figure 6
100
ns
\rCbus)
Data bus rise time
See Figure 5
300
ns
128
10
J.LS
ns
300
ns
Data bus fall time
See Figure 5
tf(bus)
t All typical values are at TA _ 25°C
NOTES: 2. Analog input voltages greeter than that applied to REF + convert to all ones (11111111), while input voltages less than that applied
to REF- convert to all zeros (00000000). For proper operation, REF+ must be at least 1 V higher than REF-. Also, the total
unadjusted error may increase as this differential reference voltage falls below 4.75 V.
5. Unearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
6. Zaro-scale Error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted oulput for full-scale input voltage.
7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.
8. Both the input address and the oulput codes are expressed In positive logic. The A11 analog input signal is intemally generated and
is used for test purposes.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-27
TLC542C, TLC5421
8-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
S\.AS075A- FEBRUARY 1989 - REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION
J
1 4V
• 3kn
Output
Under Teat
n.
Outpu.t
Under Test
Teat
Point
CLI
(see Note A)
CL
(see Note A)
-=
Test
Point
OUtput
Under Teat
CL
3kn
\
":'
(see Note A)
":'
kn
. Test
Point
T
LOAD CIRCUIT FOR
tpZL AND tpLZ
LOAD CIRCUIT FOR
tpZH AND tPHZ
LOAD CIRCUIT FOR
td. til ANDtf
J
T
J:
V:
NOTE A: CL = 50 pF
Figure 1. Load Circuits
!.Address --+1
1Valid
1
CS
~~~
\'o.SV____J2/!f,
tPZH.tPZL
.
DATA OUT
~
I~
-i
An
~
~
I
0.4 v
110 ___________2..JV
CLOCK
10%
~
\- o.sv
tsu(CS)
Figure 3. Address Timing
110 CLOCK
(/Ii
+---j
2V
/!4 1
\. .\
Figure 4. Figure 4. CS to 110 CLOCK Timing
~TEXAS
2-28
th(CS)
;-;;-\!
yr--J Ci~~k ~
2V/\'
~
J-
/'
Figure 2. CS to Data Output Timing
CS
lit
1+ tsu(A) ~
tpHZ. tpLZ
)90%
2.4V(.
----c.
X=
=X~.~V
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS; TEXAS 75265
heAl
_._.
TLC542C, TLC5421
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A- FEBRUARY 1989 - REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION
tf(l/O)
-+I 14-- ---.:
110 CLOCK
I+-
tr(1I0)
I ~-:--~
I
,
,
~BVI
O.BV
I
~I~-- fclock(l/O) ~
td(l/()"DATA)
:..
tv~
DATA OUT
.,
,
2.4VX 2.4 V
____o~.4~V~ ~~O.~4~V_____________
I I
~
~ tr(bus). tf(bus)
Figure 5. Data Output Timing
I/O CLOCK
/
---./
Bth \
Clock
tcl(I/()"EOC)
~.B V
11:.,-. ; ; ; ; . . : . . - - - - - - -
I
-I0Il1'111----+1.,
,
2.4V
EOC
\i
!\...;;O~.4..;.V_ _
I I
tf(EOC) ~
14-
Figure 6. EOC Timing
-.I ~
EOC
tr(EOC)
Ii j'Ir-------------------2.4V
~:
-.I(
14- tcl(EOC-DATA)
______________~.~2~.4~V~----DATA OUT
~O:::;.4:.:V------
I
I+-
Valid MSB --+
Figure 7. Data Output to EOC Timing
-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-29
•
TLC542C, TLC5421
8-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A- FEBRUARY 1989 - REVISED MARCH 1995
APPLICATIONS INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 8, the time required to charge the analog inputcapacitance from 0 to Vs
within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
Vc = Vs (1-e -t c/RtCj )
(1)
where
Rt=Rs+q
The final voltage to 1/2 LSB is given by
Vc (1/2 LSB) = Vs - (Vs/S12)
(2)
Equating equation 1 to equation 2 and solving for time to gives
Vs -(Vg/S12) = Vs (1-e -t c/RtCI )
(3)
to (1/2 LSB) = Rt x Cj x In(S12)
(4)
and
Therefore, with the values given the time for the analog input signal to settle is
tc (1/2 LSB) = (Rs + 1 1<.0) x 60pF x In(S12)
'(S)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet 4
Rs
I
I . TLC542
I
I
VI
rl
VS~VC
I 1kOMAX
!
I
:::pFMAX
VI =Input Voltage at INPUT AO-A10
VS= External Driving Source Voltage
Rs = Source Resistance
I'J = Input Resistance
CI = Input capacitance
t Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.
Figure 8. Equivalent Input Circuit Including the Driving Source
~1ExAs
2~O
INSTRUMENTS
POST OFFICE BOX 665303 • DAllAS. TEXAS 75265
TLC542C, TLC5421
8-81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A - FEBRUARY 1989 - REVISED MARCH 1995
PRINCIPLES OF OPERATION
The TLC542 is a complete data acquisition system on a single chip. The device includes such functions as analog
multiplexer, sample and hold, a-bit AID converter, data and control registers, and control logic. Three control inputs
(1/0 CLOCK, CS (chip select), and ADDRESS INPUT) are included for flexibility and access speed. These control
inputs and a TTL-compatible 3-state output are intended for serial communications with a microprocessor or
microcomputer. With judicious interface timing, the TLC542 can complete a conversion in 20 ~, while complete
input-conversion-output cycles can be repeated every 40 ~. Futhermore, this fast conversion can be executed on
any of 11 inputs or its built-in self-test and in any order desired by the contrOlling processor.
When CS is high, the DATA OUT terminal is in a 3-state condition, and the ADDRESS INPUT and 1/0 CLOCK
terminals are disabled. When additional TLC542 devices are used, this feature allows each of these termminals, with
the exception of the CS terminal, to share a control logic point with their counterpart terminals on additional AID
devices. Thus, this feature minimizes the control logic terminals required when using multiple AID devices.
The control sequence is designed to minimize the time and effort required to initiate conversion and obtain the
conversion result. A normal control sequence is as follows:
1. CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for two
rising edges and then a falling edge of the internal system clock before recognizing the low CS transition.
The MSB of the result of the previous conversion automatically appears on the DATA OUT terminal.
2. On the first four rising edges of the 1/0 CLOCK, a new positive-logic multiplexer address is shifted in, with
the MSB of this address shifted first. The negative edges of these four I/O CLOCK pulses shift out the
second, third, fourth, and fifth most significant bits of the result of the previous conversion. The on-chip
sample and hold begins sampling the newly addressed analog input after the fourth falling edge of the I/O
CLOCK. The sampling operation basically involves charging the internal capacitors to the level of the analog
input voltage.
3. Three clock cycles are applied to the I/O CLOCK terminal and the sixth, seventh, and eighth conversion bits
are shifted out on the negative edges of these clock cycles.
4. The final eighth clock cycle is applied to the I/O CLOCK terminal. The falling edge of this clock cycle initiates
a 12-system clock (.. 12 ~) additional sampling period while the output is in the high-impedance state.
Conversion is then performed during the next 20 ~. After this final I/O CLOCK cycle, CS must go high or
the I/O CLOCK must remain low for at least 20 ~ to allow for the conversion function.
CS can be kept low during periods ·of multiple conversion. If CS is taken high, it must remain high until the end of
conversion. Otherwise, a valid falling edge of CS causes a reset condition, which aborts the conversion process.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through
4 before the 20-~ conversion time has elapsed, Such action yields the conversion result of the previous conversion
and not the ongoing conversion.
The end-of-conversion (EOC) output goes low on the negative edge of the eighth I/O CLOCK. The subsequent
low-to-high transition of EOC indicates the AID conversion is complete and the conversion is ready for transfer.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 656303 • DAUAS. TEXAS 75265
2-31
2-32
TLC545C, TLC5451, TLC546C, TLC5461
8-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066A- DECEMBER 1985 - REVISED MARCH 1995
• B-Blt Resolution AID Converter
• Microprocessor Peripheral or Stand-Alone
Operation
• On-Chip 2o-Channel Analog Multiplexer
•
•
•
•
N or OW PACKAGE
(TOP VIEW)
INPUTAO
INPUTA1
INPUTA2
INPUTA3
INPUTA4
INPUTA5
INPUTA6
INPUTA7
INPUTA8
INPUTA9
INPUT A10
INPUT A11
INPUT A12
GND
Built-In Self-Test Mode
Software-Controllable Sample and Hold
Total Unadjusted Error ••• ±O.5 LSB Max
Timing and Control Signals Compatible
With B-Blt TLC540 and 1o-Blt TLC1540 AID
Converter Families
• CMOS Technology
PARAMETER
Channel Acquisition TIme
Conversion TIme (Max)
Sampling Rate (Max)
Power Dissipation (Max)
TL545
TL546
1.5 !IS
2.7 !IS
17 !IS
40 x 103
15mW
9 !IS
76 x 103
15mW
1
VCC
SYSTEM CLOCK
I/O CLOCK
ADDRESS INPUT
DATA OUT
CS
7
11
REF+
REFINPUTA18
INPUT A17
INPUT A16
INPUTA15
INPUT A14
INPUTA13
description
The TLC545 and TLC546 are CMOS
analog-to-cligital converters built around an B-bit
switched capacitor' successive-approximation
analog-to-digital converter. They are designed for
serial interface to a microprocessor or peripheral
via a 3-state output with up to four control inputs
including independent SYSTEM CLOCK, 1/0
CLOCK, chip select (CS), and ADDRESS INPUT.
A 4-MHz system clock for the TLC545 and a
2.1-MHz system clock for the TLC546 with a
design that includes simultaneous read/write
operation allowing high-speed data transfers and
sample rates of up to 76,923 samples per second
for the TLC545, and 40,000 samples per second
for the TLC546.
INPUT A4
INPUTA5
INPUTA6
INPUT A7
INPUT A8
INPUT A9
INPUT A10
4321282726
5
25
6
24
7
23
8
22 REF +
9
21 ' REF10
20 INPUT A18
11
19 INPUT A17
12 1314 15 16 1718
AVAILABLE OPTIONS
PACKAGE
TA
CHIP CARRIER
(FN)
PLASTICOIP
(N)
SMALL OUTLINE
(OW)
OOCto70·C
TLC545CFN
TLC546CFN
TLC545CN
TLC546CN
TLC545CDW
TLC546CDW
-400C to 85·C
TlC545IFN
TLC548IFN
TLC545IN'
TLC546IN
TLC545IDW
TLC546IDW
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 85S303 • DAllAS. TEXAS 76285
2-33
...
TLC545C, TLC5451, TLC546C, TLC5461
8-81T ANALOG·TO;.DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066A- DECEMBER 1966 - REVISED MARCH 1995
description (continued)
In addition to the high-speed converter and versatile control logic, there is an on-chip 20-channel analog
multiplexer that can be used to sample anyone. of 19 inputs or an internal self-test voltage, and a.
sample-and-hold that can operate automatically or under microprocessor contro/."
The converters incorporated in the TLC545 and TLC546 feature differential high-impedance reference inputs
thatfacilitate ratio metric conversion, scaling, and analog circuitry isolation from logic and supply nOises. A totally
switched capacitor design allows low-error (±O.5 LSB) conversion in9 ~ for the TLC545j and 17 ~ for the
TLC546, over the full operating temperature range. Detailed information on interfacing to most popular
microprocessors is readily available from the factory.
The TLC545C and theTLC546C are characterized for operation from O°C to 70°C. The TLC5451 and the
TLC5461 are characterized for operation from -40°C to 85°C.
functional block diagram
AO .J.A1 ~
A2 ~
A3
A4 ~
4A5 -!-
INPUTS
A6 ~
A7 ~
9
A8
A9
A10
A11
A12
to
11
it"
13
15
A13 16
A14
17
A15 18
A16
A17 is
20A18 ..::...
2G-Channel
Analog
Multiplexer
ri
I
I
25
UO
26
f-+-
- 23
SYSTEM
CLOCK
27
t22
t2~
8-81t
Analog-to-Dlgltal
Converter
(Switched-capacitors)
f--
Self-Teat
Reference
Output
Data
Register
Input
Address
Reglater
I
-
5
I
I
Input
Multiplexer
I
2
Control Logic
andUO
Counters
I
!
~1ExAs
2-34
8
8-t0-1 Data
Salector and
Driver
4
CLOCK
cs
REF-
8
.....
ADDRESS
INPUT
Sample
and
Hold
REF+
INSTRUMENTS
POST OFFICE BOX e55303 • DAUAS. TEXAS 75266
DATA
.M OUT
--TLC545C, TLC5451, TLC546C, TLC5461
8-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066A- DECEMBER 1985 - REVISED MARCH 1995
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 knTYP
INPUT
INPUT~
..L
AO-A18
AO-A18~
=
. ;h
CI 60pFTYP
(equivalent Input
capacitance)
1
5MDTYP
operating sequence
I
CL~b~ --'I
1
:
'
"
I
,
14--
,
I
,
2
I
3
I
4
I
5
I
6
I
7
8
r-
,I I
Access --"*j
CycleB
(see Note C)
I
See Note A
\-\
:
,
,
DATA~
OUT~
tconv,
i+- Sample --.,
I
Cycle B
CS~ ....,'-----------11
ADDRESS...l..t
INPUT--r->
t
Don't
I
ca"l
4
LSB
I
2
I
3
I
4
I
5
I
6
I
7
8
I
I.I
,
,
,
ACCess....!
CycieC I
I
H-~\~:-----------'r
j4-- twH(CS)
MSB
1
I\
~
Don't Care
,
' MSB
LSB
Don't Care
HI-ZSlete
A7
A6 A5 A4 A3 A2 A1
AO
A7
LSB
MSB -+-- Previous Conversion Data A \
MSB
(see Note B)
..
MSB
Conversion Data B
_
•
MSB
NOTES: A. The conversion cycle, which requires 36 system clock periods, is initiated with the eighth 1/0 CLOCK.!, after CS'!' for the channel
whose address exists in mamory at that time.
B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven bits
(A6-AD) will be clocked out on the first seven I/O CLOCK falling edges.
C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three system clock cycles (or less) after a chip
select transition before responding to control Input signals. Therefore, no attempt should be made to clock-in address data until the
minimum chip-select setup time hes elapsed.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ..............•.......................•.••...•............ 6.5 V
Input voltage range, VI (any input) ...............•.........................•.. -0.3 V to Vee +0.3 V
Output voltage range, Vo ................................................... -0.3 V to Vee +0.3 V
Peak input current range (any input) ............•.............•......••................... ±10 mA
Peak total input current (all inputs) .................................... . . . . • . . . • . . . . . . . . .. ±30 mA
Operating free-air temperature range, TA: TLC545C, TLC546C .......................... O°C to 70°C
TLC5451, TLC5461 .......................... -40°C to 85°C
Storage temperature range, Tstg ............ ,..................................... -65°C to 150°C
Case temperature for 10 seconCls, Te: FN package .....................•...•................ 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N or DW package ..............• 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 665303 • DALJ.AS. TEXAS 75265
2-35
.
TLC545C, TLC5451, TLC546C, TLC5461
&;81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066A- DECEMBER 1985 - REVISED MARCH 1995
recommended operating conditions
TLC546
TLC545
MIN
Supply voltage, VCC
4.75
Positive reference voltage, Vref+ (see Note 2)
0
-0.1
Negative reference voltage, Vref- (see Note 3)
Differential reference voltage, Vref+ - Vref- (see Note 3)
0
Analog input voltage (see Note 3)
0
High-level control input voltage, VIH
2
NOM
MAX
MIN
5
5.5
4.75
Vee VCC+O.l
0
VCC
0
-0.1
VCC+0.2
0
VCC
0
VCC
V
V
VCC+O.2
V
VCC
V
VCC
V
V
V
400
0
0
ns
3
System
Clock
cycles
3
110 CLOCK frequency, fclock(I/O)
0
2.048
fclock(I/O)
Pulse duration, CS high during conversion, twH(CS)
5.5
200
Setup time, ~ low before clocking in first address bit,lsu(CS)
(see Note 2)
SYSTEM CLOCK frequency, fclock(SYS)
5
UNIT
VCC VCC+O•l
0
VCC
o.a
0.8
Address hold time, th
MAX
2
Low-level control input voltage, VIL
Setup time, address bits at data Input before 1/0 CLocKi,
tsu(A)
NOM
ns
0
1.1
4 fclock(I/O)
2.1
MHz
MHz
System
clock
cycles
36
36
Pulse duration, SYSTEM CLOCK high, twH(SYS)
110
210
ns
Pulse duration, SYSTEM CLOCK 10w,iwL(SYS)
100
190
ns
Pulse duration, 110 CLOCK high,iwH(I/O)
200
404
ns
Pulse duration, 110 CLOCK low, twL(I/O)
200
404
System
Clock transition time
(see Note 4)
1/0
Operating free-air temperature, TA
ns
fclock(SYS) S 1048 kHz
30
30
fclock~YSl > 1048 kHz
20
20
100
100
40
40
)
fclock(1/0) S 525 kHz
fclock(1I0) > 525 kHz
TLC545C,TLC546C
0
70
0
ns
ns
70
·C
-40
85
85
..
NOTES: 2. To minimize errors caused by noise at CS, the intemal circuitry waits for three system clock cycles (or less) after a chip select falling
edge or riSing edge Is detected before respcnding to control input signals. Therefore, no attempt should be made to clock-in address
data until the minimum chip select setup time has elapsed.
3. Analog input voltages greater than that applied to REF+ convert as all "l"s (11111111), while input voltages less than that applied
to REF- convert as all "O"s (00000000). As the differential reference voltage decreases below 4.75 V, the total unadjusted error tends
to Increase.
4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of norinal room temperature, the devices function with input clock transition time as slow as 2 lIS for remote data acquisition
applications where the sensor and the AID converter are placed several feet away from the controlling microprocessor. .
TLC545I, TLC5461
-40
~TEXAS
2-36
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC545C, TLC5451, TLC546C, TLC5461
8-BITANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066A- DECEMBER 1985 - REVISED MARCH 1995
electrical characteristics over recommended operating temperature range,
Vee Vref+ 4.75 V to 5.5 V, f clock(1I0) 2.048 MHz for TLC545 or f clock(1I0)
(unless otherwise noted)
=
=
=
PARAMETER
TEST CONDITIONS
=1.1 MHz for TLC546
MIN
TVPt
MAX
VOH
High-level output voltage (DATA OUT)
VCC =4.75 V,
10H = -360 J.iA
VOL
Low-level output voltage
VCC = 4.75 V,
10L= 3.2 mA
0.4
10Z
Off-state (high-impedance state) ouput current
VO-VCC,
VO-O,
CSatVcc
10
IIH
High-level Input current
IlL
Low-level input current
ICC
Operating supply current
ICC + Iref
V
J.iA
-10
CSatVcc
VI-VCC
0.005
2.5
VI=O
CSatOV
-0.005
-2.5
J.iA
J.iA
1.2
2.5
mA
0.4
1
-0.4
-1
J.iA
Selected channel at 0 V,
Unselecled channel at VCC
Supply and reference current
Input capacitance
Ci
V
Selected channel at VCC,
Unselecled channel at 0 V
Selected channel leakage current
UNIT
2.4
1.3
3
IAnalog inputs
7
55
I Control inputs
5
15
CSatOV
Vref+-VCC,
mA
pF
t All tYPical values are at TA = 25°C.
operating characteristics over recommended operating free-air temperature range,
Vee Vref+ 4.75 V to 5.5 V, fclock(I/O) 2.048 MHz for TLC545 or 1.1 MHz for TLC546,
fclock(SYS) = 4 MHz for TLC545 or 2.1 MHz for TLC546
=
=
PARAMETER
=
TLC545
TEST CONDITIONS
MIN
TYP
TLC546
MAX
MIN
TVP
MAX
UNIT
EL
Linearity error
See Note 5
±0.5
±0.5
LSB
EZS
Zero-seele error
See Note 6
±0.5
±0.5
LSB
EFS
Full-scale error
See Note 6
±0.5
±0.5
LSB
Total unadjusted error
See Note 7
±0.5
±0.5
LSB
Self-test output code
INPUT A19 address = 10011
(see NoteS)
Conversion time
See Operating Sequence
9
17
Total access and
conversion time
See Operating Sequence
13
25
lIS
3
1/0
clock
cycles
Ioonv
tacq
Channel ~UiSition time
(sample cyc e)
tv
Time output data remains
valid after 1/0 CLOCK.!.
!d
Delay time, 1/0 CLOCK to
DATA OUT valid
len
Output enable time
!dis
tr(bus)
Output disable time
01111101
(125)
See Operating Sequence
10000011 01111101
(131)
(125)
3
10
10
300
See Parameter
Measurement Information
Data bus rise time
10000011
(131)
lIS
ns
4PO
ns
150
150
ns
150
150
ns
300
300
ns
ns
300
300
tf(bus) Data bus fall time
..
..
NOTES: 5. Linearity error IS the maximum deViation from the best straight line through the AID transfer characteristics .
6. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-seele Input voltage.
7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.
S. Both the input address and the output codes are expressed in positive logic. The INPUT A19 analog input signal is intemally
generated and is used for test purposes.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-37
"'"
TLC545C, TLC5451, TLC546C, TLC5461
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066A- DECEMBER 1986 - REVISED MARCH 1995
.
PARAMETER MEASUREMENT INFORMATION
J
VCC
1.4V
n·
kn
Output
Under Test
CL
(_NoteA)
Output .
Under Test
CL
(_NoteA) I
Test
Point
T
Test
Point
3kn
":"
Point
CL
(_NoteA)I
-=SeeNoteB
SeeNoteB
LOAD CIRCUIT FOR
feI, t,., AND tf
j~est
Output
Under Test
LOAD CIRCUIT FOR
tpZL AND tpLZ
LOAD CIRCUIT FOR
tpZH AND tPHZ
i~~
I
I
______ ::c
SYSTEM
CLOCK
__________________
tPZL --+j
*- tpLZ
Vcc
f 1o:!! _ _ _ _ 0 V
j+-
~I
Output
;:.~:tr:C~
!
See Note B
tpZH --+j
Output Waveform 2
(see Note C)
}I~
~ 50%
~
~ tpHZ
I
I
____~_--------It,..500/0-----ri\:---- ::H
VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES
I/O CLOCK
ou~
\ - - - - - - O.SV
I
I+-fel-.i
I
DATA OUT
V---------------- 2.4V
A,--------
_ _ _ _ _..J
O.SV
I I
.tr -+t I+-
N;---2.4V
I - - - O.4V
I
-+t I+-
tf
VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES
VOLTAGE WAVEFORMS FOR DELAY TIME
NOTES: A. CL - 50 pF for TLC545 and 100 pF for TLC546
B. len - tpZH or IPZL.lctis - tpHZ or tpLZ
C. Waveform 1 is for an output wHh internal conditions such that the output is low except when disabled by the output control.
Waveform 2 Is for an output wHh Internal conditions such that the output is high except when disabled by the output control.
~1ExAs
2-38
.
INSTRUMENTS
POST OFACE BOX 655303 • DALlAS. TEXAS 75265
TLC545C, TLC5451, TLC546C, TLC5461
8-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066A- DECEMBER 1985- REVISED MARCH 1995
simplified analog Input analysis
Using the equivalent circuit in Figure 1, the time required to charge the analog input capacitance from 0 to Vs
within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
Vc = Vs (1-e -t c/RtCj )
(1 )
where
Rt=Rs+rj
The final voltage to 1/2 LSB is given by
(2)
Vc (1/2 LSB) = Vs - (Vs/512)
Equating equation 1 to equation 2 arid solving for time tc gives
Vs -(Vsl512) = Vs (1-e -t c/RtCj )
(3)
tc (1/2 LSB) = Rt x Cj x In(512)
(4)
and
Therefore, with the values given the time for the analog input signal to settle is
tc (1/2 LSB) = (Rs + 1 kQ) x 60 pF x In(512)
(5)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet ~
Rs
I
I
I
I
VI
~ TLC545/6
I'J
VS~VC
I 1knMAX
II
I
CI
50 pF MAX
VI = Input Voltage at INPUT AO-A18
VS= External Driving Source Voltage
Rs = Source Resistance
'1
Input Resistance
CI
Input capacitance
=
=
t
Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converler.
• Rs must be real at the input frequency.
Figure 1. Equivalent Input Circuit Including the Driving Source
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-39
•
TLC545C, TLC5451, TLC546C, TLC5481
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROLAND 19 INPUTS
SLAS066A- DECEMBER 1985 - REVISED MARCH 1995
PRINCIPLES OF OPERATION
The TLC545 and TLC546 are both complete data acquisition systems on single chips. Each includes such functions
as system clock, sample and hold, a-bit AID converter, data and control registers, and control logic. For flexibility and
access speed, there are four control inputs; CS, ADDRESS INPUT, 110 CLOCK, and SYSTEM CLOCK. These control
inputs and a TTL-compatible 3-state output facilitate serial communications with a microprocessor or microcomputer.
The TLC545 and TLC546 can complete conversions in a maximum of 9 and 17 J,1S respectively, while complete
input-conversion-output cycles can be repeated ata maximum of 13 and 25 J,1S, respectively.
The system clock and 110 clock are normally used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the device.
Once a clock signal within the specification range is applied to the SYSTEM CLOCK input, the control hardware and
software need only be concerned with addressing the desired analog channel, reading the previous conversion result,
and starting the conversion by using the 110 CLOCK. SYSTEM CLOCK will drive the "conversion crunching" circuitry
so that the control hardware and software need not be concerned with this task.
When CS is high, DATA OUT is in a high-impedance condition, and ADDRESS INPUT and 110 CLOCK are disabled.
This feature allows each of these terminals, with the exception of CS, to share a control logic point with their
counterpart terminals on additional AID devices when additional TLC545rrLC546 devices are used. Thus, the above
feature serves to minimize the required control logic terminals when using multiple AID devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain
the conversion result. A normal control sequence is:
1. CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges
and then a falling edge of the SYSTEM CLOCK after a CS transitiort before the transition is recognized. The
MSB of the previous conversion result automatically appears on DATA OUT.
2.
A new positive-logic multiplexer address is shifted in on the first five rising edges of 110 CLOCK. The MSB of
the address is shifted in first. The negative edges ofthese five 110 clocks shift outthe second, third, fourth, fifth,
and sixth most significant bits of the previous conversion result. The on-chip sample and hold begins
sampling the newly addressed analog input after the fifth falling edge. The sampling operation basically
involves the charging of internal capacitors to the level of the analog input voltage.
3. Two clock cycles are then applied to 110 CLOCK and the seventh and eighth conversion bits are shifted out on
the negative edges of these clock cycles.
4. The final eighth clock cycle is applied to 110 CLOCK. The falling edge of this clock cycle completes the analog
sampling process and initiates the hold function. Conversion is then performed during the next 36 system
clock cycles. After this final 110 clock cycle, CS must go high or the 110 CLOCK must remain low for at least 36
system clock cycles to allow for the conversion function.
CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple conversion,
special care must be exercised to prevent noise glitches on the 110 CLOCK line. If glitches occur on the 110 CLOCK
line, the 110 sequence between the microprocessor/controller and the device loses synchronization. Also, if CS is
taken high, it must remain high until the end of conversion. Otherwise, a valid falling edge of CS causes a reset
condition, which aborts the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through
4 be~ore the 36 system clock cycles occur. Such action yields the conversion result of the previous conversion and
not the ongoing conversion.
~TEXAS
2-40
.
INSTRUMENTS
POST OFFIOE BOX 656303 • DALLAS, TEXAS 76266
TLC545C, TLC5451, TLC546C, TLC5461
8-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS·
SLAS066A- DECEMBER 1985 - REVISED MARCH 1995
PRINCIPLES OF OPERATION
It is possible to connect SYSTEM CLOCK and 1/0 CLOCK together in special situations in which controlling circuitry
points must be minimized. In this case, the following special points must be considered in addition to the requirements
of the normal control sequence previously described.
1. The first two clocks are required for this device to recognize CS is at a valid low level when the common clock
signal is used as an 1/0 CLOCK. When CS is recognized by the device to be at a high level, the common clock
signal is used for the conversion clock also.
2. A low CS must be recognized before the 1/0 CLOCK can shift in an analog channel address. The device
recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a
negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address.
Also, upon shifting in the address, CS must be raised after the eighth valid (10 total) 1/0 CLOCK. Otherwise,
additional common clock cycles are recognized as 1/0 CLOCKS and shift in an erroneous address.
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.
This device accommodates these applications. Although the on-Chip sample and hold begins sampling upon the
negative edge of the fourth valid 1/0 clock cycle, the hold function is not initiated until the negative edge of the eighth
valid 1/0 clock cycle. Thus, the control circuitry can leave the 1/0 clock signal in its high state during the eighth valid
I/O clock cycle, until the moment at which the analog signal must be converted. The TLC545/546 continues sampling
the analog input until the eighth valid falling edge of the 1/0 clOCk. The control circuitry or software must then
immediately lower the 1/0 clock signal to initiate the hold function at the desired point in time and to start conversion.
Detailed information on interfacing to most popular microprocesors is readily available from the factory.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-41
...
2-42
....
TLC548C, TLC5481, TLC549C, TLC5491
8-81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067A- NOVEMBER 1983 - REVISED MARCH 1995
• Microprocessor Peripheral or Stand-Alone
Operation
• 8-Blt Resolution AID Converter
• Differential Reference Input Voltages
• Conversion Time .•• 17 IJS Max
• Total Access and Conversion Cycles Per
Second
- TLC548 ••• up to 45,500
- TLC549 .•• up to 40,000
• On-Chip Software-Controllable
Sample-and-Hold
• Total Unadjusted Error ••• ±O.5 LSB Max
• 4-MHz Typical Internal System Clock
• Wide Supply Range ••• 3 V to 6 V
• Low Power Consumption ••• 15 mW Max
• Ideal for Cost-Effective, High-Performance
Applications Including Battery-Operated
Portable Instrumentation
• Pinout and Control Signals Compatible
With the TLC540 and TLC545 8-Blt AID
Converters and with the TLC1540 100Blt
AID Converter
D OR P PACKAGE
{TOP VIEW)
REF+DS
REFas
ANALOG IN
GND
2
3
4
7
6
5
VCC
1/0 CLOCK
DATA OUT
• CMOS Technology
description
The TLC548 and TLC549 are CMOS analog-to-digital converter integrated circuits built around an 8-bit
switched-capacitor successive-approximation ADC. They are designed for serial interface with a microprocessor or peripheral through a 3-state data output and an analog input. The TLC548 and TLC549 use only
the input/output clock (1/0 CLOCK) input along with the chip select (CS) input for data control. The maximum
I/O CLOCK input frequency of the TLC548 is 2.048 MHz, and the 1/0 CLOCK input frequency of the TLC549
is specified up to 1.1 MHz. Detailed information on interfacing to most popular microprocessors is readily
available from the factory.
Operation of the TLC548 and the TLC549 is very similar to that of the more complex TLC540 and TLC541
devices; however, the TLC548 and TLC549 provide an on-chip system clock that operates typically at 4 MHz
and requires no external components. The on-chip system clock allows internal device operation to proceed
independently of serial input/output data timing and permits manipulation of the TLC548 and TLC549 as desired
for a wide range of software and hardware requirements. The 1/0 CLOCK together with the internal system clock
allow high-speed data transfer and conversion rates of 45,500 conversions per second for the TLC548, and
40,000 conversions per second for the TLC549.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
0"Cto70·C
TLC54SCD
TLC549CD
TLC54SCP
TLC549CP
-40·C to 85·C
TLC54SID
T,-C549ID
TLC54SIP
TLC549IP
~1ExAs
Copyright @ 1995. Texas Instrumen1S Incorporated
INSTRUMENTS
, POST OFFICE BOX 65Il303 • OALJ.AS. TEXAS 752156
2-43
....
TLC548C, TLC5481, TLC549C, TLC5491
8-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067A- NOVEMBER 1983 - REVISED MARCH 1995
description (Continued)
Additional TLC548 and TLC549 features include versatile control logic, an on-chip sample-and-hold circuit that
can operate automatically or under microprocessor control, and a high-speed converter with differential
high-impedance reference voltage inputs that ease ratiometric conversion, scaling, and circuit isolation from
logic and supply noises. Design of the totally switched-capacitor successive-approximation converter circuit
allows conversion with a maximum total error of ±O.5 least significant bit (LSB) in less than 17 J.1S.
The TLC548C and TLC549C are characterized for operation from O°C to 70°C. The TLC5481 and TLC5491 are
characterized for operation from -40°C to 85°C.
functional block diagram
REF+
REFANALOG IN
1
8-Blt
Analog-to
Digital
Converter
(Switchedcapacitors)
3
.L
Sample
and
Hold
-
r+-
Output
Data
Reglser
\ 1I0CLOCK
5
7
8-to-1 Data
Salector
and
Driver
-
6 DATA
OUT
t--<
--",
os
~
r--
r-
Internal
System
Clock
8
I-.Control
Loglcand.
Output Counter
typical equivalent Inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 kOTYP
ANALOGIN~
I
ANALOGIN~
CI =60pFTYP
(equivalent Input
capacltanca)
~TEXAS
2-44
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
.,t
5 MOTYP
TLC548C, TLC5481, TLC549C, TLC5491
8-81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067A- NOVEMBER 1983 - REVISED MARCH 1995
operating sequence
11 12 13 14 15 16 17 Is
1I0~
~ ~c:::; ~ j.- Sample
CLOCK
I
tau(CS) ~
~
DATA
OUT
~
Don't
t ',I
-K
I
CycieB
---.r-
;)
I
I
,- -,
r~)I---------~
II
Ien~~
I
---.j
I
HI-ZStele
II B7
II
11".--- Conversion Data B - - - .
II
I~
II
r
1.,1
HI-Z State
A7
Prevloua Conversion Date A _
MSB
LSB
MSB
(see Note B)
t-- ~::I~ -----t
\su(CS)
~---------~I
I
I
~ twH(CS)
I
Li ~:~ ~
tconv --t
(see Note A)
.---""1' ,
b 12 13 14 15 16 17 Is
II MSB
len ~
LSB
j4-
NOTES: A. The conversion cycle. which requires 36 intemal system clock periods (17 j1S maximum), is initiated with the eighth I/O clock pulse
trailing edge after OS goes low for the channel whose address exists in memory at the time.
B. The most significant bit (A7) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven bits
(A6-AO) will be clocked out on the first seven 110 clock falling edges. B7-80 will follow in the same manner.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . 6.5 V
Input voltage range at any input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to Vee + 0.3 V
Output voltage range .. . .. . .. .. .. . . .. .. .. .. .. .. .. . .. .. . .. . .. . .. . .. .. . . . . . . -0.3 V to Vee + 0.3 V
Peak input current range (any input) ...... , . .. • .. . .. .. . .. .. .. . . .. . . . . . .. . . .. .. .. . .. .. • ... ± 10 mA
Peak total input current range (all inputs) • . . . . •. . . . . . • . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .. ±30 mA
Operating free-air temperature range, TA (see Note 2):TLC548C, TLC549C . • . . . . . . . . . . O°C to 70°C
TLC5481, TLC5491 . . . . . . . . . . .. -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .............................. 260°C
NOTES:
1. All voltage values are with respect to the network ground terminal with the REF- and GND terminals connected together. unless
otherwise noted.
2. The D package is not recommended below -40·C.
~ThxAs
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75265
2-45
...
TLC548C, TLC.5481, TLC549C,. TLC5491
8-81T ANALOG..TO-OIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067A- NOVEMBER 1983 - REVISED MARCH 1995
recommended operating conditions
TLC548
MIN
Supply voltage, VCC
TLC549
NOM
MAX
5
3
MIN
6
3
2.5
-0.1
VCC VCC+O.l
2.5
0
Differential reference voltage, Vref+, Vref- (see Note 3)
1
Analog input voltage (see Note 3)
Positive reference voltage, Vref+ (see Note 3)
High-level control input voltage, VIH (for VCC - 4.75 V to 5.5 V)
Low-level control Input voltage, VIL (for VCC _ 4.75 V to 5.5 V)
Input/output clock frequency, fclock(1I0) (for VCC =4.75 V to 5.5 V)
MAX
5
6
V
V
-0.1
VCC VCC+O.l
0
2.5
VCC VCC+O·2
1
VCC VCC+0.2
V
0
2
VCC
0
VCC
0
2.048
2.5
Negative reference voltage, Vref- (see Note 3)
UNIT
NOM
2
.0.8
0
V
V
V
0.8
V
1.1
MHz
input/output clock high,iwHIIIOI(for VCC = 4.75 V to 5.5 V)
200
404
ns
Input/output clock low, twLCl/OI (for VCC = 4.75 V to 5.5 V)
Input/output clock transition lime, tt(1I0) (see Note 4)
(for VCC = 4.75 V to 5.5 V)
200
404
ns
100
Duration of CS input high state during conversion, t.wH(CS)
(for VCC = 4.75 V to 5.5 V)
17
Setup time, CS low before first 110 CLOCK,\su(CS) (for VCC = 4.75 V to
5.5 V) (see Note 5)
1.4
Operating free-air temperature, TA
ITLC548C,TLC549C
I TLC548i, TLC5491
100
ns
17
IJS
1.4
IJS
0
70
0
70
-40
85
-40
85
·C
NOTES: 3. Analog input voltages greater than that applied to REF+ convert to all ones (11111111), while input voltages less than that applied
to REF- convert to all zeros (00000000). For proper operation, the positive reference voltage Vref+, must be atleast 1 V greater than
the negative reference voltage Vref- In addition, unadjusted errors may increase as the differential reference voltage Vref+ - Vreffalls below 4.75 V.
4. This is the time required for the input/output clock Input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In
the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 IJS for remote data
acquisition applications in which the sensor and the ADC are placed severarteet away from the controlling microprocessor.
5. To minimize errors caused by noise at the CS input, the internal Circuitry waits fortwo rising edges and one falling edge of intemal
system clock after CSJ.. before responding to control input signals. This CS set-up time is given by the len and tsu(CS) speclflcetions.
~TEXAS ..
2-46
INSTRUMENTS
POST OFFICE BOX 666303 • OALlAS. TEXAS 75265
TLC548C, TLC5481, TLC549C, TLC5491
8-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067A- NOVEMBER 1983 - REVISED MARCH 1995
electrical characteristics over recommended operating free-air temperature range,
Vee Vref+ 4.75 V to 5.5 V, fclock(I/O) 2.048 MHz forTLC548 or 1.1 MHz for TLC549
(unless otherwise noted)
=
=
=
PARAMETER
TEST CONDITIONS
MIN
TYPt
MAX
VOH
High-level output voltage
Vee =4.75 V,
10H =-3S0 IIA
VOL
Low-level output voltage
Vec- 4.75V,
10L =3.2 rnA
0.4
10Z
Off-state (high-impedance state) output current
Vo=Vec,
Vo .0,
CSatVee
10
IIH
High-level input current, control Inputs
IlL
Low-level input current, control inputs
II (on)
Analog channel on-state input current during
sample cycle
lee
Operating supply current
ICC + Iref
Supply and reference current
Input capaCitance
ei
2.4
V
-10
CSatVce
VI = Vee
VI=O
Analog input at VCC
UNIT
0.005
2.5
-0.005
-2.5
V
IIA
IIA
IIA
0.4
1
-0.4
-1
eSatOV
1.S
2.5
rnA
Vref+-Vee
1.9
3
rnA
I Analog inputs
7
55
I Control inputs
5
15
Analog input at 0 V
IIA
pF
operating characteristics over recommended operating free-air temperature range,
Vec Vref+ 4.75 V to 5.5 V, fclock(I/O) 2.048 MHz for TLC548 or 1.1 MHz for TLC549
(unless otherwise noted)
=
=
=
PARAMETER
TEST CONDITIONS
TLC549
TLCS48
MIN
TYPt
MAX
MIN
TYpf
MAX
UNIT
EL
Linearity error
See NoteS
±a.5
±a.5
EZS
Zero-scaleerror
See Note 7
±a.5
±a.5
LSB
EFS
Full-scale error
See Note 7
±a.5
±a.5
LSB
Total unadjusted error
See NoteS
±a.5
LSB
Conversion time
See Operating Sequence
S
17
12
17
Total access and conversion time
See Operating Sequence
12
22
19
25
Is
ehannel acquisition time (sample cycle)
See Operating Sequence
Iv
Time output data remains
valid after I/O eLOCK,),
!conv
!d
Delay time to data output valid
±a.5
4
10
I/O CLOCK,),
Output enable time
4
10
LSB
J1S
J1S
I/O
clock
cycles
ns
2000
400
1.4
1.4
ns
len
J1S
Output disable time
150
150
ns
!dis
See Parameter
Data bus rise time
ns
300
300
trebus)
Measurement Information
Data
bus
fall
time
ns
300
300
tf(bus)
tAli typlcals are at Vce = 5 V, TA _ 25oe.
NOTES: S. Unearity error is the deviation from the best straight line through the AID transfer characteristics.
7. Zero-scale error is the difference between 00000000 and the converted output for zero Input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale Input voltage.
S. Total unedjusted error is the sum of linearity, zero-scale, and full-scale errors.
-!llExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75266
2-47
TLC548C, TLC5481, TLC549C, TLC5491
8·BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067A- NOVEMBER 1983 - REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION·
Vee
1.4V
3kn
Output
Under Test
Output
Under Test
Test
Point
D
1 '_
CL
(see Note A)
CL
(see Note A) I
3kn
Test
Point
Output }
Under Test
3kn
Teet
Point
_
CL
(see Note A ) I
SeeNoteB
LOAD CIRCUIT FOR
Id. t" AND tf
CS
~50%
I+-I
.
tpZL
Output Waveform 1
(see Note C)
See Note B
LOAD CIRCUIT FOR
tpZH AND tpHZ
:
I--
Vee
!-50%
OV
I
-+i
14- tPLZ---!
I
~50%
.
tPZH
LOAD CIRCUIT FOR
tpZL AND tpLZ
r:
!
I
---+j
I
----
OV
----
VOH
j4- tPHZ-.I
I
~
,50%
Output Waveform 2
(aee Note C)
VCC
See Note B
OV
VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES
1/0 CLOCK
0
\ - - - - - - O.8V
r
14- Id -tI
DATA
OUT------~V-_-_-_-_-_-_-_-_- ~:::
A
It
"
utPu~1
I I
tr(bus) --.t
14-
1\::--I
2.4V
- - - O.4V
I I
--.t 14- tf(bua)
VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES
VOLTAGE WAVEFORMS FOR DELAY TIME
NOTES: A. CL =50 pF for TLC548 and 100 pFfor TLC549; CL includes jig capacitance.
B. tan = tPZH or tpZL. !dis = tpHZ or tpLZ·
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
~1ExAs
2-48
INSTRUMENTS
POST OFFICE BOX e56303 • DALLAS. TEXAS 75265
TLC548C, TLC5481, TLC549C, TLC5491
8-81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067A- NOVEMBER 1983 - REVISED MARCH 1995
APPLICATIONS INFORMATION
simplified analog Input analysis
Using the equivalent circuit in Figure 1, the time required to charge the analog input capacitance from 0 to Vs within
1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
Vc = Vs (1-e -t c/RtCi)
(1 )
where
Rt=Rs+ri
The final voltage to 1/2 LSB is given by
Vc (1/2 LSB)
= Vs -
(Vs/512)
(2)
Equating equation 1 to equation 2 and solving for time to gives
-t IR-f'·)
Vs-(Vsl512) = Vs (1-e
c t"'1
(3)
to (112 LSB) = Rt x Ci x In(512)
(4)
and
Therefore, with the values given the time for the analog input signal to settle is
to (1/2 LSB) = (Rs + 1 1<.0) x 60 pF x In(512)
(5)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Soureet
.4--- 11 ---~.
Rs
1
VI
TLC548I9
rl
VS~VC
!I
1 kOMAX
I
..l
I
CI
SO pF MAX
VI = Input Voltage at ANALOG IN
VS= External Driving Source Voltage
Rs = Source Resistance
'1 = Input Resistance
CI = Input capacitance
t
Driving source requirements:
.• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.
Figure 1. Equivalent Input Circuit Including the Driving Source
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-49
TLC548C, TLC5481, TLC549C, TLC5491
8-81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067A- NOVEMBER 1983 - REVISED MARCH 1995
PRINCIPLES OF OPERATION
The TLC548 and TLC549 are each complete data acquisition systems on a single chip. Each contains an internal
system clock, sample and hold, 8-bit AID converter, data register, and control logic cirCuitry. For flexibility and access
speed, there are two control inputs: I/O CLOCK and chip select (CS). These control inputs and a TIL-compatible
3-state output facilitate serial communications with a microprocessor or minicomputer. A conversion can be
completed in 17 J.1S or less, while complete input-conversion-output cycles can,be repeated in 22 J.1S for the TLC548
and in 25 J.1S for the TLC549.
The internal system clock and I/O CLOCK are used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the device.
Due to this independence and the internal generation of the system clock, the control hardware and software need
only be concerned with reading the previous conversion result and starting the conversion by using the I/O clock. In
this manner, the internal system clock drives the "conversion crunching" circuitry so that the control hardware and
software need not be concerned with this task.
When CS is high, DATA OUT is in a high-impedance condition and I/O CLOCK is disabled. This CS control function
allows I/O CLOCK to share the same control logic point with its counterpart terminal when additional TLC548 and
TLC549 devices are used. This also serves to minimize the required control logic terminals when using multiple
TLC548 and TLC549 devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain
the conversion result. A normal control sequence is:
1.
CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges
and then a falling edge of the internal system clock after a CS! before the transition is recognized. However,
upon a CS rising edge, DATA OUT will go to a high-impedance state within the idis specification even though
the rest of the integrated circuitry will not recognize the transition until the tsu(CS) specification has elapsed.
This technique is used to protect the device against noise when used in a nOIsy environment. The most
significant bit (MSB) of the previous conversion result will initially appear on DATA OUT when CS goes low.
2. The falling edges ofthe first four I/O CLOCK cycles shift out the second, third, fourth, and fifth most significant
bits of the previous conversion result. The on-Chip sample and hold begins sampling the analog input after the
fourth high-to-Iow transition of I/O CLOCK. The sampling operation basically involves the charging of internal
capacitors to the level of the analog input voltage.
3. Three more I/O CLOCKcycies are then applied to the I/O CLOCK terminal and the sixth, seventh, and eighth
conversion bits are shifted out on the falling edges of these clock cycles.
4. The final, (the eighth), clock cycle is applied to I/O CLOCK. The on-chip sample and hold begins the hold
function upon the high-to-Iow transition of this clock cycle. The hold function will continue for the next four
internal system clock cycles, after which the holding function terminates and the conversion is performed
during the next 32 system clock cycles, giving a total of 36 cycles. After the eighth I/O CLOCK cycle, CS must
go high or the I/O clock must remain low for at least 36 internal system clock cycles to allow for the completion
of the hold and conversion functions. CS can be kept low during periods of multiple conversion. When keeping
CS low during periods of multiple conversion, special care must be exercised to prevent noise glitches on the
I/O CLOCK line. If glitches occur on I/O CLOCK, the I/O sequence between the microprocessor/controller and
the device will lose synchronization. If CS is taken high, it must remain high until the end of conversion.
Otherwise, a valid high-ta-Iow transition of CS will cause a reset condition, which will abort the conversion in
progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through
4 before the 36 internal system clock cycles occur. Such action will yield the conversion result of the previous
conversion and not the ongoing conversion.
\'
~TEXAS.
2-50
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
TLC548C, TLC5481, TLC549C, TLC5491
8-BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067A- NOVEMBER 1983 - REVISED MARCH 1995
PRINCIPLES OF OPERATION
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.
This device will accommodate these applications. Although the on-chip sample and hold begins sampling upon the
high-to-Iow transition of the fourth 1/0 CLOCK cycle, the hold function does not begin until the high-to-Iow transition
of the eighth 1/0 CLOCK cycle, which should occur at the moment when the analog signal must be converted. The
TLC548 and TLC549 will continue sampling the analog input until the high-ta-Iow transition of the 8th 1/0 CLOCK
pulse. The control circuitry or software will then immediately lower 1/0 CLOCK and start the holding function to hold
the analog signal at the desired point in time and start conversion.
.
Detailed information on interfacing to the most popular microprocessor is readily available from Texas Instruments.
-!i11ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
2-61
2-52
TLC0820AC,TLC0820AI
Advanced LinCMOSTM HIGH·SPEED 8-8IT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A - SEPTEMBER 1986 - REVISED JUNE 1994
• Advanced LlnCMOSTM Silicon-Gate
Technology
•
•
•
•
DB, OW, OR N PACKAGE
(TOP VIEW)
8-Blt Resolution
Differential Reference Inputs
Parallel Microprocessor Interface
Conversion and Access Time Over
Temperature Range
Read Mode •.• 2.5 J!S Max
ANlGIN
(lSB) DO
1
VCC
NC
OFlW
01
02
03
WRIROY
07 (MSB)
06
05
6
MODE
RO
• No External Clock or Oscillator
Components Required
INT
• On-Chip Track and Hold
04
CS
REF+
REF-
9
GNO
• Single SOV Supply
• TLC0820A Is Direct Replacement for
National Semiconductor ADC0820C/CC and
Analog Devices AD7820KlBIT
FN PACKAGE
(TOP VIEW)
description
The TLC0820AC and the TLC0820AI are
Advanced LinCMOSTM 8-blt analog-to-digltal
3 2 1 2019
02 4
converters each consisting of two 4-bit flash
18 OFlW
converters, a 4-bit digital-to-analog converter, a
03 5
17 07 (MSB)
summing (error) amplifier, control logic, and a
WR/ROY 6
16 06
result latch circuit. The modified flash technique
MODE 7
15 05
allows low-power integrated circuitry to complete
14 04
RO 8
9 10 11 12 13
an 8-bit conversion in 1.18 IlS over temperature.
The on-chip track-and-hold circuit has a 100-ns
sample window and allows these devices to
convert continuous analog signals having slew
rates of upto 100 mVlIlS without external sampling
NC-No internal connection
components. TIL-compatible 3-state output
drivers and two modes of operation allow interfacing to a variety of microprocessors. Detailed information on
interfacing to most popular microprocessors is readily available from the factory.
AVAILABLE OPTIONS
TA
TOTAL
UNADJUSTED
ERROR
PACKAGE
SSOP
(DB)
PLASTIC
SMALL OUTLINE
(DW)
PLASTIC
CHIP CARRIER
(FN)
PLASTIC DIP
(N)
O'Cto 70'C
±1 LSB
TLC0820ACDB
TLC0820ACDW
TLC0820ACFN
TLC0820ACN
-40'C to 85'C
±1 LSB
TLC0820AIDB
TLC0820AIDW
TLC0820AIFN
TLC0820AIN
Advanced linCMOS is a trademark of Texas Instruments Incorporated.
~TEXAS
COpyright © 1994. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-53
TLC0820AC, TLC0820AI
Advanced llnCMOSTM HIGH.;SPEED 8-81T ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES .
SLAS064A- SEPTEMBER 1986 - REVISED JUNE 1994
functional block diagram
REF+
REF-
12
4-BltFlash
Analog-to-Dlgltal
Converter
(4 MSBa)
11
4
4
~ OFlW
---..-.!. DO (lSB)
~ D1
4
~
Summing
Amplifier
ANlGIN
1
-
-1
~
4-Blt
f-- Dlgltal-to-Analog
Converter
'---
-
Output
latch
and
3-State
Buffers
-
4-Blt Flash
Analog-to-Dlgltal
Converter
(4 lSBs)
4
~ D2
~ D3
-..!! D4
----1! D5
---1! D6
-
17
+1
II
MODE
WRiRDY
cs
RD
7
6
Timing
and
Control
13
8
~1ExAs
2-54
.•
INSTRUMENTS
POST OFRCE BOX 665303.e DALLAS. TEXAS 75265
r---!.
D7(MSB)
Digital
Outputs
TLC0820AC,TLC0820AI
Advanced LinCMOSTM HIGH-SPEED 8-81T ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A- SEPTEMBER 1986 - REVISED JUNE 1994
Terminal Functions
TERMINAL
NAME
ANLGIN
NO.
110
DESCRIPTION
1
I
Analog input
CS
13
I
Chip select. CS must be low in order for RD or WR to be recognized by the ADC.
DO
2
3
D2
4
03
5
D4
14
05
15
D6
16
D7
17
0
0
0
0
0
0
0
0
Digital, 3-state output data, bit 1 (LSB)
D1
GND
10
INT
9
0
Interrupt. In the write-read mode, the interrupt output (I NT) going low indicates that the intemal count-down delay
time, Id(int), is complete and the data result is in the output latch. The delay time Id(int) is typically 800 ns starting
after the rising edge of WR (see operating characteristics and Figure 3). If RD goes low prior to the end of Id(int),
INT goes low at the end of Id(R!bLand the conversion results are available sooner (see Figure 2). INT is reset by
the rising edge of either RD or CS.
MODE
7
I
Mode select. MODE is intemally tied to GND through a 50-1lA current source, which acts like a pulldown resistor.
When MODE is low, the read mode is selected. When MODE is high, the write-read mode is selected.
Digital, 3-state output data, bit 2
Digital, 3-state output data, bit 3
Digital, 3-state output data, bit 4
Digital, 3-state output data, bit 5
Digital, 3-state output data, bit 6
Digital, 3-state output data, bit 7
Digital, 3-state output data, bit 8 (MSB)
Ground
NC
19
OFLW
18
0
Overflow. Normally OFLW is a logical high. However, if the analog input is higher than Vref+, OFLW will be low at
the end of conversion. It can be used to cascade two or more devices to improve resolution (9 or 10 bits).
8
I
Reed. In the write-read mode with CS low, the 3-state data outputs DO through D7 are activated when RD goes
low. RD can also be used to increase the conversion speed by reading data prior to the end of the Intemal
count-down delay time. As a result, the data transferred to the output latch is latched after the falling edge of RD.
In the read mode with CS low, the conversion starts with RD going low. RD also enables the 3-state data outputs
on completion of the conversion. RDY going into the high-Impedance state and INT going low indicate completion
of the conversion.
REF-
11
I
Reference voltage. REF- is placed on the bottom of the resistor ladder.
REF+
12
I
Reference voltage. REF + is placed on the top of the resistor ladder.
VCC
WRIRDY
20
I/O
Write ready. In the write-read mode with CS low, the conversion is started on the falling edge of the WR input signal.
The result oftha conversion is strobed into the output latch after the intemal count-down delay time, Id(ini), provided
thatthe RD input does not go low prior to this time. The delay time Id(int) is approximately 800 ns.ln the read mode,
ROY (an open-drain output) goes low after the falling edge of CS and goes into the high-impedance state when
the conversion is strobed into the output latch. It is used to simplify the interlace to a microprocessor system.
RD
6
No internal connection
Power supply voltage
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-55
TLC0820AC, TLC0820AI
Advanced LinCMOSTM HIGH-SPEED 8-81T ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A- SEPTEMBER 1986 - REVISED JUNE 1994
absolute maximum r:atings over operating free-air temperature range (unless otheiwise noted)t
Supply voltage, Vee (see Note 1) ................................•......................... 10 V
Input voltage range, all inputs (see Note 1) ..................................... -0.2 V to Vcc+0.2 V
Output voltage range, all outputs (see Note 1) .•................................ -0.2 V to Vee + 0.2 V
Operating free-air temperature range: TLC0820AC ................. . . . . . . . . • . . . . . . . . .. O°C to 70°C
TLC0820AI ................................... -40°C to 85°C
Storage temperature range ....................................................... -65°C to 150°C
Case temperature for 10 seconds: FN package .............................................. 260°C
Lead temperature 1,6 mm (1116 inch) from case fcir 10 seconds: DB, OW or N package .......•... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voitagesare with respect to network GND.
recommended operating conditions
MIN
NOM
MAX
Supply voltage, VCC
4.5
5
8
Analog input voltage
-0.1
Positive refElrence voltage, Vref +
Vref. GND
Negative reference voltage, VrefHigh-level input voltage, VIH
VCC = 4.75 V to 5.25 V
Low-level input voltage, VIL
VCC - 4.75 V to 5.25 V
CS, WRJRDY, RD
MODE
Operating free-air temperature, TA
2
.
INSTRUMENTS
POST OFFICE eox 855303 • OALLAS. TEXAS 75285
V
V
3.5
1.5
I
2-56
V
Vref+
0.8
TLC0820AI
~1EXAS
V
Vec
CS, WRJRDY, RD
ITLC0820AC
V
VCC+ O•1
MODE
Pulse duration, write in write-read mode, tw(W) (see Figures 2, 3, and 4)
UNIT
0.6
50
0
-40
70
85
V
lIS
'C
TLC0820AC, TLC0820AI
Advanced LinCMOSTM HIGH-SPEED 8-81T ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A- SEPTEMBER 1986 - REVISED JUNE 1994
=
electrical characteristics at specified operating free-air temperature, Vee 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC~4.75V,
VOH
VOL
IOH~-360pA
High-level output voltage
DO-07,INT, or
OFLW
Low-Ievel output voltage
00-07, OFLW, iNT,
orWRlROY
VCC=4.75V,
IOH=-10pA
VCC-5.25V,
IOL= 1.6 rnA
CSorRD
IIH
High-level input current
Low-Ievel input current
IOZ
Off-state (high-Impedance-state)
output current
WRIRDY
VIH-5V
CS, WRJRDY, RD,
or MODE
00-07 or WRJROY
CSat5V,
VI=5V
CSat5V,
VI-O
Analog input current
Short-cIrcuit output current
m
VO=5V
DO-D70rOFLW
VO=O
INT
Rref
Reference resistance
ICC
Supply current
Ci
Input capacitance
Co
Output capacitance
2.4
Full range
4.5
25°C
Full range
4.6
TYP
0.4
0.34
25°C
Full range
00-07
0.005
.. .
t Full range IS as specified In recommended operating conditions
V
1
25°C
Full range
0.1
25°C
50
-0.005
-1
pA
3
0.3
-3
-0.3
pA
25°C
Full range
0.1
25°C
Full range
-0.1
25°C
Full range
25°C
Full range
25°C
Full range
25°C
Full range
25°C
Full range
pA
3
25°C
Full range
Full range
ANLGIN
00-07
UNIT
3
0.3
200
170
25°C
Full range
CS, WRIROY, and
RDatOV
MAX
V
Full range
VO-5V
00-07, OFLW,
orWRJROY
lOS
Full range
Full range
VIL-O
VO=O
II
MIN
Full range
MODE
IlL
TAt
0.3
-3
pA
-0.3
7
8.4
-6
-7.2
14
mA
-12
-4.5
-5.3
1.25
-9
1.4
2.3
6
5.3
15
7.5
5
45
13
kO
rnA
pF
5
pF
~1ExAs
INSTRUMENTS
POST OFFICE BOX 656303 • DAUAS. TEXAS 75265
2-57
TLC0820AC, TLC0820AI
Advanced LinCMOSn.t HIGH-SPEED 8-81T ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A- SEPTEMBER 1986 - REVISED JUNE 1994
'operating characteristics, Vcc = 5 V, Vref... = 5 V, Vref- = 0, tr = tf =20 "s, TA = 25°C (unless otherwise
noted) .
,
PARAMETER
ksvs
Supply-voltage sensitivity
TEST CONDITIONst
MIN
TYP
.
MAX
UNIT
±1/4
LSB
Total unadjusted el1'9~
VCC=5V±5%, TA"" MINto MAX
MODEatOV,
TA = MIN to MAX
!conv(R)
Conversion time, read mode
MODEatOV,
See Figure 1
1.6
2.5
·118
ta(R)
Access time, RD,!, to data valid
MODEatOV,
See Figure 1
!conv(RJ
+2
tconv(RJ
+5
ns
190
280
Access time, RD,!, to data valid
MODEat5V,
id(WR) < id(int),
See Figure 2
CL= 15pF
ta(Rl)
CL=100pF
210
320
70
120
Access time, RD,!, to data valid
MODEat5V,
id(WR) > tdgnt),
See Figure
CL-15pF
ta(R2)
CL-l00pF
90
150
tallNn
Access time, INn to td(lnt)l
-!lJTEXAS
INSTRUMENTS
POST OFFICE BOX 656303 • DAUAS, TEXAS 75265
2-59
TLC0820AC, TLC0820AI
Advanced LinCMOSTM HIGH·SPEED 8-81T ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
.
SLAS064A- SEPTEMBER 1986 - REVISED JUNE 1994
PARAMETER MEASUREMENT INFORMATION
CSLow
RDLow
WRIRDY
50%
i r-
50%
fd(WlH)
I
~
__--+"1/50% }
fd(NC)
I
50%
14- fd(lnt) ~ !+-
--+!
DO-D7
----"") ::t
I
taPNT)
Data Valid } -
Figure 4. Write-Read-Mode Wavefol'l1!!.
(Stand-Alone Operation, MODE High, and RD Low)
VCC
CL= 10pF
1,4 I--
TLC0820 ...-_"---.,
Input
RD
Dn
CS
x:1r-::""'9O%!'"'_-_-_-_- :::
AD
Data
t---4I~-'- Output
GND
---+I
fdla
Data
Outputa
I+----
~
eO%--.VOH
- - - - - . . . ; ; : : : . GND
t r =20ns
TEST CIRCUIT
VOLTAGE WAVEFORMS
VCC
CL= 10pF
tr-+j
TLC0820
ilr-:~""'s:::!'"'_-_-_-_- ::
1 kO
Input
RD
RD
CS
GND
Dn
~
t--......- . . - - Data
Output
fdla ---.j
j+-----:--""'0:== Vee
Data
Outputa
I·~
--£...1~_ _ VOL
t r =20na
Dn=DO ... D7
-=
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 5. Test Circuit and Voltage Waveforms
~1ExAs .
2-60
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
TLC0820AC, TLC0820AI
Advanced LlnCMOSTM HIGH-SPEED 8-81T ANALOG-TO-DiGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A- SEPTEMBER 1986 - REVISED JUNE 1994
PRINCIPLES OF OPERATION
The TLC0820AC and TLC0820AI each employ a combination of sampled-data comparator techniques and flash
techniques common to many high-speed converters. Two 4-bit flash analog-to-digital conversions are used to give
a full 8-bit output.
The recommended analog input voltage range for conversion is -0.1 V to Vee + 0.1 V. Analog input signals that are
less than Vref- + 1/2 LSB or greater than Vref+ -1 /2 LSB convert to 00000000 or 11111111 , respectively. The reference
inputs are fully differential with common-mode limits defined by the supply rails. The reference input values define
the full-scale range of the analog input. This allows the gain of the ADC to be varied for ratio metric conversion by
changing the Vref+ and Vref- voltages.
The device operates in two modes, read (only) and write-read, that are selected by MODE. The converter is set to
the read (only) mode when MODE is low. In the read mode, WRIRDY is used as an output and is referred to as the
ready terminal. In this mode, a low on WR/RDY while CS is low indicates that the device is ~y. Conversion starts
on the falling edge of RD and is completed no more than 2.5 J1S later when INT falls and WRIRDY returns to the
high-i!!!E.edance state. Data outputs also change from high-impedance to active states at this time. After the data is
read, RD is taken high, INT returns high, and the data outputs return to their high-impedance states.
When MODE is high, the converter is set to the write-read mode and WRIRDY is referred to as the write terminal.
Taking CS and WRIRDY low selects the converter and initiates measurement of the input signal. Approximately
600 ns after WRIRDY returns high, the conversion is completed. Conversion starts on the rising edge of WRIRDY
in the write-read mode.
The high-order 4-bit flash ADC measures the input by means of 16 comparators operating simultaneously. A
high-precision 4-bit DAC then generates a discrete analog voltage from the result of that conversion. After a time
delay, a second bank of comparators does a low-order conversion on the analog difference between the input level
and the high-order DAC output. The results from each of these conversions enter an 8-bit latch and are output to the
3-state output buffers on the falling edge of RD.
~1ExAs
INS1RUMENTS
POST OFFICE BOX _
• DAU.AS. TEXAS 75265
2-61
TLC0820AC,TLC0820AI
Advanced LinCMOSTM HIGH-SPEED 8-81T ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A- SEPTEMBER 1986- REVISED JUNE 1994
APPLICATION INFORMATION
i"CS
ViR
f{>'
J.LP
B.us
13
Vcc ~5V
6 WRIRDY ANLG
1
IN
cs
Q-!
DO
D1
D2
03
04
OS
D6
07
08
2
3
4
5
14
15
16
17
OF[
18
RD
ANLQ
IN
TLC0820
MODE. ~5V
12
REF+
00
D1
D2
D3
D4
D5
D6
D7
REF-
OFLW
GNO
.............
1
l:
0.1~
t
0.1~
11
10
~
~
20
13
CS
Vee -5V
6 WRIRDY ANLG 1
IN
Q-!-
RD
2
3
4
5
14
15
16
17
18
DO
01
02
03
04
05
06
D7
TLC0820
0l=[W
MODE .....!SV
12
REF+
1 0.1
RE'- 11
-!I TEXAS ".
2-62
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
I
l~'~
F-I0.1~
GND
Figure 6. Configuration for 9-Bit Resolution
5V
TLC0831AC, TLC0831AI, TLC0831BC, TLC0831BI
TLC0832AC, TLC0832AI, TLC0832BC, TLC0832BI
8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
• B-Blt Resolution
• Easy Microprocessor Interface or
Stand·Alone Operation
• Operates Ratlometrlcally or With SOV
Reference
TLC0831 ••• D OR P PACKAGE
(TOP VIEW)
CS08
IN+
INGNO
• Single Channel or Multiplexed Twin
Channels With Single-Ended or Differential
Input Options
• Input Range 0 to 5 V With Single SOV Supply
• Inputs and Outputs Are Compatible With
TTL and MOS
7
6
5
VCC
ClK
DO
REF
TLC0832 ••• D OR P PACKAGE
(TOP VIEW)
csO'
• Conversion Time of 32 J.LS at
fclock 250 kHz
• Designed to Be Interchangeable With
National Semiconductor ADC0831 and
ADC0832
CHO
CH1
GNO
=
DEVICE
2
3
4
2
3
4
8
7
Vcc/REF
ClK
6
5
DO
01
TOTAL UNADJUSTED ERROR
A·SUFFIX
B·SUFFIX
TLC0831
±1 LSB
± 112 LSB
TLC0832
±1 LSB
±112 LSB
;:
W
:;
w
a::
description
These devices are 8-bit successive-approximation analog-to-digital converters. The TlC0831 has single input
channels; the TLC0832 has multiplexed twin input channels. The serial output is configured to interface with
standard shift registers or microprocessors. Detailed information on interfaCing to most popular
microprocessors is readily available from the factory.
The TlC0832 multiplexer is software configured for single-ended or differential inputs. The differential analog
voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the
voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of
resolution.
The operation of the TLC0831 and TLC0832 devices is very similar to the more complex TLC0834 and TLC0838
devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum analog input
signal value, which gives the highest possible conversion resolution. Typically, REF is set equal to VCC (done
internally on the TLC0832). For more detail on the operation of the TLC0831 and TLC0832 devices, refer to the
TLC0834rrLC0838 data sheet.
The TLC0831AC, TLC0831BC, TLC0832AC, and TLC0832BC are characterized for operation from O°C
to 70°C. The TLC0831 AI, TLC0831 BI, TLC0832AI, and TLC0832BI are characterized for operation from -40°C
to 85°C.
, AVAILABLE OPTIONS
PACKAGE
TA
e::
O·Cto 70·C
TLC0831ACP
TLC0831BCP
TLC0832ACP
TLC0832BCP
TLC0831ACP
TLC0831BCP
TLC0832ACP
TLC0832BCP
-40·C to 85·C
TLC0831AIP
TLC0831BIP
TLC0832AIP
TLC0832BIP
TLC0831 AlP
TLC0831BIP
TLC0832AIP
TLC0832BIP
PRODUCT PREVIEW _ o n ........ praduc\l1n tile_or
phIoo
C,,"_ .... _ . .ordooIangoolo. TexallllllUlIIIIIII_tllerightlo
c ngtord_••lIIoio producII _ _
-.,mont.
PLASTIC DIP
(P)
SMALL OUTLINE
(0)
~TEXAS
Ccpyrlght © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-63
a..
b
::l
C
o
a::
a..
TLC0831AC, TlC0831AI, TLC0831BC, TLC0831BI
TLC0832AC, TLC0832AI, TLC0832BC, TLC0832BI
8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107-JANUARY 1996
functional block diagram
CLK~7~~--------------------r-~
cs
......---'~....
1
r--li5~~
I
DII
Shift Register
____JD~'
D
DD EVEN
. I (TLC0832 I
L.!~!...J
SGUDIF
CHO/IN+ - - - - i Analog
CH1/IN-
Comparator
MUX
EN
"'D
:IJ
oC
CS
c:
1
EN
(')
r--5
I
REFf-:<----'-I
-I
"'D
I (TLC0831 I
L~~~.J
:a
m
<
m
-
Laddar
and
Decoder
Bits 0-7
EN R
SAR
Logic
and
Latch
Bits 0-7
Bit 1
MSB
First
EOC
9-Blt
Shift
Register
LSB
Firat
~
~TEXAS
2-64
INSTRUMENTS
POST OFACE BOX 665303 • DALLAS. "rEXAS 76265
DO
TLC0831AC, TLC0831AI, TLC0831BC, TLC0831BI
TLC0832AC, TLC0832AI, TLC0832BC, TLC0832BI
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107:" JANUARY 1995
sequence of operation
TLC0831
2
3
5
4
7
6
8
9
10
CLK
tsu1~11
cs
l r
1
MUX
Sattllng Time
DO
fconv
Ir r
1 1 I.
-.! 14-1
---,
-I j
MSB-Flrst Data
:~SB
HI-Z
IMSBI
7
6
5
4
3
j
2
HI-Z
0
TLC0832
2
3
4
5
6
•••
10
11
12
--.l
14
•••
18
19
21
;:
W
:;:
S::~ SG~S6";DB~lt
1 1
rrLC:~2 J
I
MUX
~
MSB-Flrst Data - : -
LSB
7
6
•••
2
MSB
o
::J
C
LSB-Flrst Data
-.j~
Settling Time
0..
t~I O
--+I
I r-IMS~BI~I:: I I I I I I:: I I I
I
a:
1
If!::~~::
DIF EVEN
w
~~~------~----~
!1
~I
1 1
DO
20
-I
j+-T;""";""-- tconv
~ l~---------+~----~ss
y)
13
J1J1J1fUlJ1
CLK
2
•••
6
H~Z
7
TLC0832 MUX-ADDRESS CONTROL LOGIC TABLE
MUXADDRESS
SGUDIF
ODD/EVEN
l
l
l
H
H
l
H
H
H = high level, l = low level,
- or + = polarity of selected input
CHANNEL NUMBER
1
0
+
.-
+
+
2
+
-
~1ExAs
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS. TEXAS 75265
2-65
o
a:
0..
TLC0831AC, TLC0831AI, TLC0831BC, TLC0831BI
TLC0832~C, TLC0832AI, TLC0832BC, TLC0832BI
8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107 -JANUARY 1995
absolute maximum ratings over recommended operating free-air temperature range (unless
otherwise noted)t
.
Supply voltage, Vee (see Note 1) ........•.................................................. 6.5 V
Input voltage range, VI: Logic ............................................... -0.3 V to Vee + 0.3 V
Analog .............................................• -0.3 V'to Vee + 0.3 V
Input current, II ................................................•......................... ±5 mA
Total input current ...................................................................... ±20 mA
Operating free-air temperature range, TA: C suffix .....•................................ O°C to 70°C
I suffix ..................................... -40°C to 85°C
Storage temperature range, Tst~ .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: P package .....•............... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolut&-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.
recommended operating conditions
."
:D
o
C
c:
~
."
:D
m
<
m
-
Supply voltage, Vec
High-level input voltage, VIH
MIN
NOM
MAX
4.5
5
6.3
2
Low-level Input voltage, VIL
Clock frequency, fclock
Clock duty cycle (see Note 2)
UNIT
V
V
0.8
V
10
600
kHz
40%
60%
Pulse duration, CS high, twH(CS)
220
ns
Setup time, CS low or TLC0832 data valid before CLK't, tsu
350
ns
Hold time, TLC0832 data valid after CLKi, th
90
I Csuffix
0
-40
ns
70
·C
85
II suffix
NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. If a clock frequency Is used outside the recommended
duty-cycle range, the minimum pulse duration (high or low) is 1 lIS.
Operating free-air temperature, TA
~
~TEXAS
2-e6
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75266
TLC0831AC, TLC0831AI, TLC0831BC, TLC0831BI
TLC0832AC, TLC0832AI, TLC0832BC, TLC0832BI
8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107 -JANUARY 1995
electrical characteristics over recommended range of operating free-air temperature, Vee = 5 V,
fclock 1 MHz (unless otherwise noted)
=
digital section
PARAMETER
I SUFFIX
CSUFFIX
TEST CONDITIONSt
MIN
TVA
MAX
MIN
TVA
MAX
Vee = 4.75 V,
10H = - 360 JIA
Low-level output voltage
Vee- 4.75V,
VCC-4.75V,
10H = -10 JIA
IOL-l.6rnA
High-level input current
V1H=5V
IlL
Low-level input current
VIL-O
10H
High-level output
(source) current
VOH= Vo,
TA • 25°C
-6.5
VOL-VCC,
VO=5V,
TA-25°e
8
TA-25°C
0.01
3
0.01
3
VO-O,
TA=25°C
-0.D1
-3
-0.01
-3
VOH
High-level output voltage
VOL
IIH
10L
Low-level output (Sink) current
10Z
High-impedance-state output
current (~O)
Ci
Input capacitance
. 2.8
2.4
4.6
4.5
0.34
V
0.4
V
0.005
1
0.005
1
-0.005
-1
-O.OOS
-1
-14
-6.5
16
8
UNIT
-14
mA
16
5
Output capacitance
5
Co
t All parameters are measured under open-lOOp conditions with zero common-mode input voltage.
=!: All typical values are at VCC - 5 V, TA = 25°C.
IIA
JIA
rnA
JIA.
5
pF
5
pF
analog and converter section
PARAMETER
VICR
II(stdby)
I'j(REF)
TEST CONDITIONSt
MIN
See Note 3
-0.05
to
VCC+0.05
Common-mode input voltage
Standby-input current (see Note 4)
TYP;
MAX
UNIT
V
On channel
VI=5V
Off channel
VI=O
-1
On channel
VI-O
-1
Off channel
VI=5V
IIA
1
.. With zero common-mode Input voltage.
t All parameters are measured under open-loop conditions
1.3
2.4
5.9
kQ
NOTES: 3. If channel IN- is more positive than channeIIN+, the digital output code will be 0000 0000. Connected to each analog input are two
on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC .Care must be taken during testing
at low VCC levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high temperatures, cause this input diode
to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply
voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 to 5-V input voltage range requires a minimum
VCC of 4.95 V for all variations of temperature and load.
4. Standby-input currents are currents going into or out of the on or off channels when the NO converter is not performing conversion
and the clOck is in a high or low steady-state conditions.
total device
ICC
Supply current
TYp:t
MAX
I
TLe0831
1
2.5
I
TLC0832
3
5.2
MIN
UNIT
mA
=!: All typiCal values are at VCC = 5 V, TA = 25°C.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
a:
Q.
o
c
:::»
oa:
Q.
=!: All typical values are at VCC = 5 V, TA = 25°C.
PARAMETER
>
w
I-
1
Input resistance to REF
3=
w
2-67
TLC0831AC, TLC0831AI, TLC0831BC, TLC0831BI
TLC0832AC, TLC0832AI, TLC0832BC, TLC0832BI
8-81T .ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107 - JANUARY 1995
operating characteristics vee = Vref = 5 V, fclock =1 MHz, tr = tf = 20 ns, TA = 25°0 (unless otherwise
noted)
PARAMETER
TEST CONDITIONSt
,
Supply-voltage variation error
VCC - 4.75 V to 5.25 V
Total unadjusted error (see Note 5)
Vref=5V,
TA - MIN to MAX
Common-mode error
Differential mode
Ipd
Propagation delay time,
output data after CLKi
(see Note 6)
!dis
Output disable time, DO after csi
Ioonv
Conversion time (multiplexer-addressing
time not included)
AI, AC SUFFIX
MIN
BI,BC SUFFIX
TYP
MAX
±1/16
±1/4
MIN
MAX
±1/16
±1/4
LSB
±112
LSB
LSB
±1
±1/16
±1/4
±1I16
±1/4
650
1500
650
1500
250
600
250
600
125
250
125
MSB-f1rst data
ns
CL= 100pF
LSB-first data
CL=10pF,
CL,,100pF,
UNIT
TYP
RL=10kn
RL=2kn
250
500
500
8
8
ns
clock
periods
t All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the
"tJ
:D
appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The MSB-first data is output directly from the comparator and therefore requires additional delay to allow for comparator response
time. LBS-first data applies only to TLC0832.
o
C
c:
~
"tJ
:D
m
S
m
~
~TEXAS
2-68
.
INSTRUMENTS
POsT OFFICE BOX 655303 e. DALLAS, TEXAS 75265
TLC0831AC, TLC0831AI, TLC0831BC, TLC0831BI
TLC0832AC, TLC0832AI, TLC0832BC, TLC0832BI
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107 - JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
VCC
ClK
---I
I
r- -1 ~Isu
5~r1------T-T-----1
GND
CLK~
tau
• GAV' I
I
I I4-M-I
th
I I
I I
I .....,
I
I
Vee
•
Vcc
~--GND
"-
.1
tpd
_ _- , I , __
GND
DO
~~---,
2V
\1
r
50%
Vee
.
y<
___ J .
50%
vOH
VOL
Figure 2. Data-Output Timing
GND
Figure 1. TLC0832 Data-Input Timing
3:
w
:;:
Test
Point
...
m """""
Under
Test
I !
I
~
w
a:
Q.
CL
(_NoteA)
I-
CJ
:::J
lOAD CIRCUIT
-+I I+- tr
CS
50%ij 90%
__~*f.,.l~---- GND
·~letls
DO
Output
---vcc
S'!~!!d______
o
o
50% I
_ _~'-t-10"l!.. ____ GND
Q.
tr
90%
14 .1
90%
~
S10pen
Vee
-+I~I+-
Vcc
II
GND
a:
letls
10pen
-Vee
~
10%
- - - - GND
1
DO
Output
S2closed
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTE A: CL includes probe and jig capacitance.
Figure 3. Output Disable Time Test Circuit and Voltage Waveforms
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
2-69
TLCO§31AC, TLC0831AI, TLC083tBC, TLC0831B1
TLC0832AC, TLC0832AI,TLC0832BC, TLC0832BI
8·BIT ANALOG·TO-DIGITAL CONVERTERS WITH SERIAL OONT.ROL
SLAS107-JANUARYl995
.
TYPICAL CHARACTERISTICS
LINEARITY ERROR
vs
REFERENCE VOLTAGE
UNADJUSTED OFFSET ERROR
vs
REFERENCE VOLTAGE
16
1.5
V1+- 1-~~'V
-V'
14
,
III
1.25
tn
....
12
~
w
10
!1
I
8
!
.
I
III
6
c
4
j
\
2
"'tJ
::XJ
o
o
1.0
I
0.75
~
!=
::I
VCC=5V
fclock =1 MHz
TA=25·C
0.01
m
c
::::i
'\
"
0.1
C
0.25
r-.
1.0
"
10
c:
Vref - Reference Voltage - V
"'tJ
::XJ
LINEARITY ERROR
vs
FREE·AIR TEMPERATURE
~
0.5
2
LINEARITY ERROR
vs
CLOCK FREQUENCY
0.5
:e
<
3
Vref= 5 V
fclock 1 MHz
0.45
III
!1
0.4
w
0.35
..~
I
E
'\
"-"-
III
!1
-50
-25
/
/
2
I
~
0.3
0.25
0
g
w
~~
25
50
1.5
~
'C
J
81
s:;V25~
~
........
t"
75
-40°C
0.5
100
o0
100
TA - Free-Air Tempertature _·C
200
300
400
500
fclock - Clock Frequency - kHz
Figure 6
Figure 7
~1ExAs
2-70
1
2.5
81
~
I
Vref = 5 V
VCC=5V
=
m
5
4
Figure 5
Figure 4
m
3
Vref _ Reference Voltage - V
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
600
TLC0831AC, TLC0831AI, TLC0831BC, TLC0831BI
TLC0832AC, TLC0832AI, TLC0832BC, TLC0832BI
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS1 07 - JANUARY 1995
TYPICAL CHARACTERISTICS
TLC0831
TLC0831
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
CLOCK FREQUENCY
1.6
1.6
I
fclock = 1 MHz
CS= High
VCC=5V
TA = 26·C
1I
00(
E
I
~:s
'E
~
B
~
0
>"ii.
Do
:s
~
Do
Do
:s
II)
II)
I
I
0
~
~
-
0.6
E
.;t
W
0.6 ' - - -.......-60
-26
.......-
0
.........- - ' - - - - ' - -......
26
60
76
100
0 0
100
TA - Free-Air Temperature - ·C
200
300
400
600
w
a:
fclock - Clock Frequency - kHz
Figure 8
:;
D..
Figure 9
b
OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
26,---"T"""--r--"""T'"---,.--,----,
::)
c
o
a:
VCC=5V
D..
20~=-+--~--~--_+----~~
00(
E
I
~
16
B
i
~
10
I
.9
6
t-=7.~+==F:::±~
IOL (VOL =0.4 V)
O'---~-.........---'--~-~~~
-60
-25
o
26
60
76
100
TA - Free-Air Temperature _·C
Figure 10
~TEXAS
INSTRUMENTS
POST OFFICE BOX 6S5303 • DALLAS, TEXAS 75265
2-71
2-72
TLC0834AC, TLC0834AI, TLC0834BC, TLC0834BI
TLC0838AC, TLC0838AI, TLC0838BC, TLC0838BI
8-BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
TLC0834 ••• 0 OR N PACKAGE
(TOP VIEW)
• 8-Blt Resolution
• Easy Microprocessor Interface or StandAlone Operation
• Operates Ratlometrlcally or With 5-V
Reference
• 4- or 8-Channel Multiplexer Options With
Address Logic
• Input Range 0 to 5 V With Single 5-V Supply
• Remote Operation With Serial Data Link
• Inputs and Outputs Are Compatible With
nLandMOS
• Conversion Time of 32 J.IS at felK 250 kHz
• Functionally Equivalent to the ADC0834
and ADC0838 Without the Internal Zener
Regulator Network
NC
A·SUFFIX
B·SUFFIX
±1 LSB
± 112 LSB
TLC0838
±1 LSB
± 1/2 LSB
01
CLK
SARS
DO
9 REF
6
7
8
ANLGGNO
TLC0838 ••• OW OR N PACKAGE
(TOP VIEW)
CHO
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
TOTAL UNADJUSTED ERROR
TLC0834
VCC
11
OGTLGNO
=
DEVICE
1
CS
CHO
CH1
CH2
CH3
description
1
VCC
NC
CS
01
CLK
SARS
6
OGTLGNO
These
devices
are
8-bit
successiveapproximation analog-to-digital converters, each
with
an
input-configurable
multichannel
multiplexer and serial input/output. The serial
input/output is configured to interface with
standard shift registers or microprocessors.
Detailed information on interfacing with most
popular microprocessors is readily available from
the factory.
W
==
:;
DO
SE
REF
11
w
ANLGGNO
a::
D.
TLC0838 ••• FN PACKAGE
(TOP VIEW)
~
J:
CH3
CH4
CH5
CH6
CH7
t3
~ 00
00 0
~z
3 2 1 2019
18
17
16
6
15
7
14
8
9 10 1112 13
4
5
::l
C
CS
01
CLK
SARS
00
o
a::
D.
u..IW
~ C c
OZZ~CI)
O(!)(!)
..J(!)
I-..J
(!)z
Cc(
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(D)
SMALL OUTLINE
(OW)
PLASTIC DIP
(N)
CHIP CARRIER
(FN)
O·C10 70·C
TLC0834ACD
TLC0834BCD
TLC0838ACDW
TLC0838BCDW
TLC0834ACN TLC0838ACN
TLC0834BCN TLC0838BCN
TLC0838ACFN
TLC0838BCFN
-40·C to 85·C
TLC0834AID
TLC0834BID
TLC0838AIDW
TLC0838BIDW
TLC0834AIN TLC0838AIN
TLC0834BIN TLC0838BIN
TLC0838AIFN
TLC0838BIFN
~1EXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
2-73
M31A31:1d .LOnaOl:ld
~
Cl>cp-t-t
~mr-r
functional block diagram
a_OO
Start
~H
(see Note Ai
--
Flip-Flop
pf?rr=c
\
I
I·
50Bit Shift Register
'f-tOO
I> e» e»
:II»>
os
~z~5f
5!r- 0 0
I> CLK
SARS
-0- -
!8_-t-t
"'~,
r- r-tOO
O
00
.~e»
2e»5f
G»>
r:---"
I TlC0838 I
=4:-:-
lI"-t-t
IOnIY-1
r-r-r000
...
1 --=--:----:,.---t--+---t---t------<'t
L _ _~ ;....+.
(3
~
o
~i4P
~-t
!~r
TlC0834 {
TlC0838
CHO------I
CH1------I
CH2------I
CH3------I
CH4------I
CHS------I
CH6------I
CH7------I
COM------I
S
MUX
R
EN
os
00
~E~
mmm
I>ClK
Anal~
::DOO
--t- m-t-t
::Dr-r(1)00
=e~~
;~
I
0
"
CS
~
EN
R
R
Ladder
logic
Comparator
REF
and
Decoder 1\....
, ---
Latch
::D
CS
Bits 0-7
----r-
9-Blt
Shift
Register
EOC
»
8
r-
ClK
SAR
and
=i~5f
::E:!!!!!
(I)
m
DO
~
::D
o
r-
,
NOTE A: For the TLC0834, DI is input directly to the D input of SELECT1; SELECTO is forced to a high.
TLC0834AC, TLC0834AI, TLC0834BC, TLC0834BI
TLC0838AC, TLC0838AI, TLC0838BC, TLC0838BI
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094 - MARCH 1995
description (continued)
The TLC0834 (4-channel) and TLC0838 (8-channel) multiplexer is software configured for single-ended or
differential inputs as well as pseudo-differential input assignments. The differential analog voltage input allows
for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference
input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.
The TLC0834AC, TLC0834BC and TLC0838AC, TLC0838BC are characterized for operation from O°C to 70°C.
The TLC0834AI, TLC0834BI, and TLC0838AI, TLC0838BI are characterized for operation from -40°C to 85°C.
functional description
The TLC0834 and TLC0838 use a sample-data-comparator structure that converts differential analog inputs
by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog
common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal
and is compared to ground (single ended), to an adjacent input (differential), orto a common terminal (pseudo
differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative (-)
polarity. If the signal input applied to the assigned positive terminal is less than the signal on the negative
terminal, the converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A particular input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address is shifted into the converter through the data input (01) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel
pairs. For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act
differentially with any other channel. In addition to selecting the differential mode, the polarity may also be
selected. Either channel of the channel pair may be designated as the negative or positive input.
The common input on the TLC0838 can be used for a pseudo-differential input. In this mode, the voltage on the
common input is considered to be the negative differential input for all channel inputs. This voltage can be any
reference potential common to all channel inputs. Each channel input can then be selected as the positive
differential input. This feature is useful when all analog circuits are biased to a potential other than ground.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. On each low-to-high transition ofthe clock
input, the data on 01 is clocked into the multiplexer-address shift register. The first logic high on the input is the
start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of the clock
input, the start bit and assignment word are shifted through the shift register. When the start bit is shifted into
the start location of the multiplexer register, the input channel is selected and conversion starts. The SAR status
output (SARS) goes high to indicate that a conversion is in progress, and 01 to the multiplexer shift register is
disabled the duration of the conversion.
An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. DO
comes out of the high-impedance state and provides a leading low for this one clock period of multiplexer settling
time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog
signal. The comparator output indicates whether the analog input is greater than or less than the resistive-ladder
output. As the conversion proceeds, conversion data is simultaneously output from DO, with the most significant
bit (MSB) first. After eight clock periods, the conversion is complete and SARS goes low.
-!111EXAS
INSTRUMENTS
PosT OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-75
3:
w
:;
w
a::
D..
ti::J
C
o
a::
D..
TLC0834AC,TLC0834AI, TLC0834BC, TLC0834BI
TLC0838AC, TLC0838AI, TLC0838BC, TLCPS38BI
8·BIT ANALOG"TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094-MARCH 1996
functional description (continued)
TheTLC0834 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. If BE is held high
on the TLC0838, the value of the LSB remains on the data line. When SE is forced low, ttle data is then clocked
out as LSB-first data. (To output LSB first, SE must first go low, then the data stored In the 9-blt shift register
outputs LSB first.) When CS goes high, all internal registers are cleared. At this time, the output circuits go to
the high-impedance stat~. If another conversion is desired, CS must make a hlgh-ta-Iow transition followed by
address information.
01 and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because 01 is only examined during the multiplexer-addressing interval, and DO is still in the
high-impedance state.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.
sequence of operation
2
3
4
5
7
6
TlC0834
10
11
12
14
13
18
15
'"tJ
I
I
I
:0
o
C
c:
(")
....
'"tJ
:0
m
<
-
m
~
cs 1
~
r
I
I
H
20
21
MUX Settling Time --tt
II
~~
$;;~
I
DI]III
DIF EVEN
I
HI-Z
III
SARS..,
•
'---------1 I
H
II
jf-
tau +SIgn
I
IStart
Bit SELECT I
~Blt SGlODD Blt~~
H
I
I
I
I
H
~
I
j.-
MSB-Flrat Data
1
~I::
DO-HI-Z------,L....-.L.M_SB..L.-I
7
6
'-----I..
lSB-Flrat Data
---J
HI-Z
I
2
o
8
2
TLC0834 MUX-ADDRESS CONTROL LOGIC TABLE
MUXADDRESS
CHANNEL NUMBER
ODD/EVEN
SELECT BIT 1
0
1
2
3
l
L
L
+
L
L
H
+
L
+
H
L
L
H
H
+
'L
H
L
+
+
H
L
H
H
H
L
+
+
H
H
H
H = high level, L = low level, - or + - polarity of selected Input
SGuDiF
-
-
~TExAs'
2-76
18
J1JUl1Ul-
ClK
INSTRUMENTS
POST OFFICE eox 655303 • OALLAS. TEXAS 75265
-
-
7
TLC0834AC, TLC0834AI, TLC0834BC, TLC0834BI
TLC0838AC, TLC0838AI, TLC0838BC, TLC0838BI
8-BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094-MARCH 1995
sequence of operation
TLC0838
2
3
4
5
6
7
8
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
eLK
~
H
~-- teonv
leu
cs11:
,I 14-
I I
MUX
II
Add....lng
--., iot-- feu
• SEL
I Start
Slf,n
'Bit SGL
\~\
8Jo
-J
--~
____ __________________________
~
~r-
-I'
I I
, II
BIt SEL,
a~
,I
~~III_I~OIF EVEN
~~
1
0
II
I,
I_
I
\\
' .
HI-Z
-,
HI-Z
r
--------~+---------I-----------------------I I
iEl~------------~~I------~\~\------------------------------------------------------~
II
r
=:!IIIII
~I.z-____ 1w;IMB~B!l1~I:: I I~ I
I I 14-- MSII-Flrat
LSB-Flrat
Dab!
~I
Dab!
IMBal
'Wl
1178
iE
2101
HI-Z
r-
34567
--------i'-~-----~U~~~~~F~~~----------------I '\\
MUX settling
nme
--'
I
:.-
, i4I
0 0 - -_ _:
MBII-Flrat
.
Data
______
I
Lsa
Held
--I~~I11I---
I
LSII-FII'I t
""'Y'
......
0
1234567
~TEXAS
INSTRUMENTS
POST
OFFICE
BOX 655303 •
DALLAS.
TEXAS 75265
I-
o
::l
C
a..
I
IMBal I: ::I:1::11:::.L-s-:-a::-:.I.,....I~ I~1~~I-=-I~"r""I~-~IMB:BI_---1r
7621
w
a:
a..
a:
------.I
I
:;
o
I
Dab!
~
W
2-77
TLC0834AC, TLC0834AI, TlC0834BC, TLC0834BI
TLC0838AC, TLC0838AI, TLC0838BC, TLC0838BI
8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094 - MARCH 1995
TLC0838 MUX·ADDRESS CONTROL LOGIC TABLE
MUXADDRESS
"'0
::D
o
C
c:
~
"'0
::D
m
<
m
-
:e
SGUDIF
ODD/EVEN
L
L
L
L
L
L
L
L
L
L
L
L
H
SELECTED CHANNEL NUMBER
SELECT
1
L
L
H
0
L
H
L
H
H
L
L
H
L
H
L
H
H
H
H
H
L
L
H
L
L
H
H
L
H
H
L
H
H
L
H
H
L
H
H
H
H
H
H
H =high level, L - low level, - or + •
0
+
-
0
1
3
+
-
-
+
4
2
5
+
-
1
2
-
3
7
+
-
-
+
COM
+
-
+
H
L
+
H
+
L
H
L
+
H
L
H
polarity of selected Input
6
-
+
+
-
+
+
+
,-
absolute maximum ratings over recommended operating free-air temperature range (unless
otherwise noted)t
Supply voltage, Vee (see Note 1) ...............................................•.....•..... 6.5 V
Input voltage range: Logic .................................................. -0.3 V to Vee + 0.3 V
Analog ................................................. -0.3 V to Vee+ 0.3 V
Input current, II ....•............................., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±5 mA
Total input current ...................................................................... ±20 mA
Operating free-air temperature range, TA: C suffix ...................................... O°C to 70°C,
I suffix ............................•........ -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 10 seconds, Te: FN package .............................. .. .. .. .. .... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ..................... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at'these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTEJ: All voltage values, except differential voltages, are with respect to the network ground terminal.
~TEXAS "
INSTRUMENTS
POST OFFlCE,BOX 655303 • DALLAS. TEXAS 75265
TLC0834AC, TLC0834AI, TLC0834BC, TLC0834BI
TLC0838AC, TLC0838AI, TLC0838BC, TLC0838BI
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094 - MARCH 1995
recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH
MIN
NOM
MAX
4.5
5
6.3
2
Clock duty cycle (see Note 2)
Pulse duration, CS high, twH(CS)
Setup time, Isu
Hold time, data valid after ciocki, Ih
Operating lree-air temperature, TA
I CS low, SE low, or data valid before clocki
V
V
0.8
V
10
600
kHz
40%
60%
Low-level input voltage, VIL
Clock frequency, fclock
UNIT
220
ns
350
ns
90
ns
70
0
ICsuffix
°c
-40
85
II suffix
NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequenCies. If a clock frequency IS used outside the recommended
duty-cycle range, the minimum pulse duration (high or low) is 1 lIS.
electrical characteristics over recommended range of operating free-air temperature,
fclock = 250 kHz (unless otherwise noted)
.
Vee = 5 V,
~
digital section
I SUFFIX
CSUFFIX
PARAMETER
TEST CONDITIONSt
VOH
High-level output voltage
VCC-4.75V, 10H - -360 JJA
VCC = 4.75 V, IOH =-10 JJA
VOL
IIH
Low-level output voltage
VCC-5.25V, IOH= 1.6 mA
High-level input current
VIH-5V
IlL
Low-level input current
VIL=O
IOH
High-level output (source) current
VOH =0,
TA = 25°C
-6.5
IOL
Low-level output (sink) current
8
TA = 25°C
0.01
3
0.01
3
10Z
VOL=VCC,
VO-5V,
TA = 25°C
High-impedance-state output
current (DO or SARS)
VO-O,
TA=25°C
-0.01
-3
-0.01
-3
MIN
TYP*
MAX
MIN
2.8
2.4
4.6
4.5
0.005
0.34
1
-0.005
-1
-6.5
-14
8
16
TYP*
MAX
UNIT
V
0.4
V
0.005
1
-0.005
-1
JJA
JJA
-14
mA
16
Input capaCitance
5
Ci
Output capaCitance
5
Co
.. with zero common-mode Input voltage (unless otherwise specified) .
t All parameters are measured under open-loop conditions
:J: All typical values are at VCC - 5 V, TA _ 25°C.
mA
JJA
pF
pF
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75266
2-79
w
5>
w
a::
D..
I-
o
::)
c
o
a::
D..
TLC0834AC, TLC0834AI, TLC0834BC, TLC0834BI
TLC0838AC, TLC0838AI, TLC0838BC, TLC0838BI .
8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094 - MARCH 1995
analog and converter sectIon
PARAMETER
VICR
TEST CONDITIONSt
MIN
See Note 3
-0.05
to
VCC+0.05
Common-mode input voltage
II(stdby)
Standby-input current (see Note 4)
Ii(REF)
Input resistance to REF
On channel
VI=5V
Off channel
VI=O
On channel
VI=O
VI-5V
Off channel
TY~
MAX
UNIT
V
1
-1
-1
jIA
1
1.3
2.4
5.9
kn
total device
PARAMETER
ICC
Supply current .
MIN
TYp:j:
MAX
2.5
t All parameters are measured under open-loop conditions with zero common-mode input voltage.
"'tJ
::0
o
C
c:
tAli typical values are at VCC = 5 V, TA = 25·C.
NOTES: 3. If channel IN- is more positive than channellN+, the digital output code will be 0000 0000. Connected to each analog input are
two on-chip diodes that conduct forward current for analog Input voltages one diode drop above VCC .Care must be taken during
testing at low VCC levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high temperatures, cause this input
diode to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply
voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 to 5-V input voltage range requires a minimum
VCC of 4.950 V for all variations of temperature and load.
4. Standby-input currents are currents gOing into or out of the on or off channels when the AID converter is not performing conversion
and the clock is in a high or low steady-state condition.
~
"'tJ
::0
m
m
<
-
~
~1ExAs
2-80
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
TLC0834AC, TLC0834AI, TLC0834BC, TLC0834BI
TLC0838AC, TLC0838AI, TLC0838BC, TLC0838BI
8-BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094 - MARCH 1995
operating characteristics,
noted)
Vee = 5 V, fclock = 250 kHz, tr = tf = 20 ns, TA = 25°C (unless otherwise
TEST
CONDITIONSt
PARAMETER
!pd
letis
Ioonv
Supply-voltage variation error
VCC = 4.75 Vt05.25V
Total unadjusted error (see Note 5)
Vref- 5 V,
TA - MIN to MAX
Common-mode error
Differential mode
AI, AC SUFFIX
MIN
MAX
±1/16
±1/4
±1/16
I
I
cst
MIN
±1/4
UNIT
TYP
MAX
±1116
±1/4
LSB
±1/2
LSB
±114
LSB
±1
±1/16
1500
1500
600
600
Cl= 10 pF,
Rl-10 kn
250
250
Cl= 100pF,
Rl=2kn
500
500
Propagation delay time, output MSB-first data
CL= 100pF
data after ClK.!. (see Note 6) lSB-first data
Output disable time, DO or SARS after
81, BC SUFFIX
TYP
ns
ns
Conversion time (multiplexer-addressing
time not included)
8
clock
8 periods
t All parameters are measured under open-loop conditions with zero common-mode input voltage. For cond~ions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linear~, and multiplexer errors.
6. The MSB-first data is output directly from the comparator and therefore requires additional delay to allow for comparator response
time.
PARAMETER MEASUREMENT INFORMATION
CLK
----'I
1
CO
~tsu
-1
' " - - - GND
~tsu
\Ir-----:-:------0.4 V).
i
1
~Ih
1
~---&!---,
01
I
2V
1
GND
i~
1
VCC
,_----VCC
\1
_-=~..;a.._--'_.!!,."U' ____ GND
Figure 1. Data·lnput Timing
-!!1 TEXAS
.
INSTRUMENTS
POST OFFICE BOX 655303 • DAu.AS. TEXAS 75265
2-81
,
TLC0834AC, TlC0834AI, TLC0834BC, TLC0834BI
TLC0838AC, TLC0838AI, TLC0838BC, TLC0838BI
8~BIT ANALOG·TO·DIGITAl CONVERTERS WITH SERIAL CONTROL
SI.:AS094 - MARCH 1995
PARAMETER MEASUREMENT INFORMATION
Vcc
~..-I~-
I
tpd
tpd
I
-+I
.
GND
l+1
--~\I,r------------..j.'"'\~1 Vee
DO ____ J
I~
Ii A.'--
60% GND
500/0
tau
14--
---.I
t~~---
SE - - - - - - - - - -......
VCC
.
GND
Figure 2. Data-Output Timing
Vcc
Test
Point
"U
:0
o
From Output
Under Test
C
(')
!
--tl--_~~R",LIr---~
I
c:
S1
-I
""D
CL
(see Note A)
LOAD CIRCUIT
:0
m
<
m
~
~ ~tr
!~----VCC
-
CS
:IE
6O"Il'1
i4-+ftells
1_ _ _ _
DOandSARS
50%
900/0
_ _-+11~
____ GND
90%
~
l-::--tr
GND
10pen
-Vee
~
S2 closed
-~-GND
1
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTE A: CL includes probe and jig capacitance.
Figure 3. Output Disable Time Test Circuit and Voltage Waveforms
~1ExAs .
2-82
Idls
1
DO and SARS
INSTRUMENTS
POST OFFICE BOX 65S303 • DALLAS. TEXAS 75265
VCC
GND
1
14 .1
Vcc
S10pen
S'!'~!!d______
I+-
TLC0834AC, TLC0834AI, TLC0834BC, TLC0834BI
TLC0838AC, TLC0838AI, TLC0838BC, TLC0838BI
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094-MARCH 1995
TYPICAL CHARACTERISTICS
UNADJUSTED OFFSET ERROR
va
REFERENCE VOLTAGE
16
.1
LINEARITY ERROR
va
REFERENCE VOLTAGE
1.5
I 1.111111
I- VI(+) = VI(_) = 0 V
14
1.25
VCC=5V
'clock = 250 kHz
TA = 25°C
12
III
III
~
..g
I
w
I
a-
'C
6
I
c
2
:::)
I
g
w 0.75
8
4
'ii'
II
~
10
II
c
::::i
l\.
\
1\
0.5
0.25
'~
r---
o
0.01
0.1
00
10
2
Figure 4
3
I
III
...
II)
.g
0.4
a-
0.35
I
w
'C
II
~
'"""
..g
w
0
C
Vref = 5 V
VCC=6V
J
2
25
1.5
85°C
l
II
~
-25
b
::l.
I
'" "
0.3
0.25
-50
III
II)
50
......
75
TA - Free-AIr Tempertature -
c
::::i
,
100
o0
100
°c
200
I
/
/
J
~V25:i
-400C
0.5
300
400
500
600
'clock - Clock Frequency - kHz
Figure 6
Figure 7
~TEXAs
INSTRUMENTS
POST OFFICE &eX 665303 • DALI..AS. TEXAS 75266
>
w
a::
2.5
...
W
a.
LINEARITY ERROR
va
CLOCK FREQUENCY
Vref =5 V
'clock = 250 kHz
0.45
5
Figure 5
LINEARITY ERROR
va
FREE·AIR TEMPERATURE
I
4
Vref _ Reference Voltage - V
Vref - Reference Voltage - V
0.5
3
2-83 .
o
a::
a.
....
TLC0834AC, TLC0834AI, TLC0834BC, TLC0834BI
TLC0838AC, TLC0838AI, TLC0838BC, TLC0838BI
8.BIT ANALOG·TO·DIGITALCONVERTERS WITH SERIAL CONTROL
SLAS094 - MARCH 1995
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
CLOCK FREQUENCY
vs
1.5....---r---r---.---r--"""T'"---,
fclock = 250 kHz
1.5
I
VCC=5V
TA=25·C
cs =High
cc
1
E
I
I
~
~
o
8:
iJl
>-
:I
Ul
I
I
0.5 L__.l....-_...L-._....L..._........_......L.._-..I
-50
-25
0
25
50
75
100
0
C
o
o
200
100
Figure 9
-I
OUTPUT CURRENT
"tJ
::D
vs
m
m
FREE-AIR TEMPERATURE
25,...,---r---.---,...---r"---.----.
!$
. VCC=5V
:e
20r-~+_--~--~--_+--~--~
1I
~
:I
o
O~
10~-+_-~-~-_+-~~~
-IOH (VOH =2.4 V)
I
.9
5~=±:~~H
IOL (VOL =0.4 V)
........--..I.-~--L-~
O~-~-
-50
-25
o
25
50
75
TA - Free-Air Temperature - ·C
Figure 10
~TEXAS
2-84
300
400
fclock - Clock Frequency - kHz
FigureS
(")
-
0.5
TA - Free-Air Temperature - ·C
c:
~
~
~
"tJ
::D
~
:I
:I
0
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 76266
100
500
TLC1540C,TLC1541C
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073A - DECEMBER 1985 - REVISED MARCH 1995
• 1()'Blt Resolution AID Converter
• Microprocessor Peripheral or Stand-Alone
Operation
• On-Chip 12-Channel Analog Multiplexer
• Built-In Self-Test Mode
• Software-Controllable Sample and Hold
• Total Unadjusted Error
TLC1540: ±O.5 LSB Max
TLC1541: ±1 LSB Max
• Pinout and Control Signals Compatible
With TLC540 and TLC549 Families of 8-Bit
AID Converters
OW OR N PACKAGE
(TOP VIEW)
INPUT AD
INPUT A1
INPUT A2.
INPUT A3
INPUT A4
INPUT A5
INPUT A6
INPUT A7
INPUT AS
GND
• CMOS Technology
PARAMETER
6
7
8
9
11
FNPACKAGE
(TOP VIEW)
VALUE
Channel Acquisition Sample Time
Conversion Time (Max)
Samples Per Second (Max)
Power Dissipation (Max)
4
5
VCC
SYSTEM CLOCK
I/O CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+
REFINPUT A1D
INPUT A9
5.5 fl.S
21 fl.S
32xl03
6mW
description
The TLC1540 and TLC1541 are CMOS ND
converters built around a 1D-bit, switched3 2 1 20 19
INPUT A3
4
18 I/O CLOCK
capacitor,
successive-approximation
ND
17 ADDRESS INPUT
INPUT A4
5
converter. They are designed for serial interface
INPUT A5
16 DATA OUT
6
to a microprocessor or peripheral via a 3-state
INPUT
A6
7
15 CS
output with up to four control inputs [including
8
14 REF+
INPUT A7
independent SYSTEM CLOCK, I/O CLOCK, chip
9 1011 1213
select (CS), and ADDRESS INPUTj. A 2.1-MHz
system clock for the TLC1540 and TLC1541, with
a design that includes simultaneous reacllwrite
operation, allows high-speed data transfers and
sample rates of up to 32,258 samples per second.
In addition to the high-speed converter and
versatile control logic, there is an on-chip, 12-channel analog multiplexer that can be used to sample anyone
of 11 inputs or an internal self-test voltage and a sample and hold that can operate automatically or under
microprocessor control. Detailed information on interfacing to most popular microprocessors is readily available
from the factory.
AVAILABLE OPTIONS
PACKAGE
TA
o·Cto 70·C
PLASTIC DIP
(OW)
PLASTIC CHIP
CARRIER
(FN)
PLASTIC
DIP
(N)
TLCI540CDW
TLCI541CDW
TLCI540CFN
TLCI541CFN
TLC1540CN
TLC1541CN
~TEXAS.
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS, TEXAS 75265
2-85
TLC1540C,TLC1541C
10-BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073A- DEC.EMBER 1985 - REVISED MARCH 1995
description (continued)
The converters incorporated in the TLC1540 and TLC1541 feature differential high-impedance reference inputs
that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises. A totally
switched-capacitor design allows low-error conversion (±0.5 LSB for the TLC 1540, ± 1 LSB for the TLC1541 )
in 21 J.IS over the full operating temperature range.
The TLC1540 and the TLC1541 are available in OW, FN, and N packages. The C-suffix versions are
characterized for operation from O°C to 70°C.
functional block diagram
REF+
REF-
14+
-+1
+~
~
~
..L
..!...
~
ANALOG
INPUTS
111
Sampleand
Hold
~
13+
12-Channel
Analog
Multiplexer
.......
10
Output
Data
Reglatar
~lnputAddnassJ
...1!
;.
1G-Blt
Swltched-CapacltonJ
Aria.log-to-Dlgltal
Converter
Reglater
~
t
1G-to-1 Data
DATA
Selector and f- ~
OUT
Driver
4
'-
~
4
Self-Teat
Reference
I
I
ADDRESS 17
INPUT
1/0 CLOCK
CS
SYSTEM
CLOCK
Control Logic
andl/O
Countera
\
Input
Multiplexer
I
I
2
18
15
19
typical equivalent Inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
INPUT
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 kOTYP
AO-A10~
1
INPUT
CI =60 pFTYP
(equivalent Input
cepacltance)
AO-A10~
~TEXAS
·
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
;h
5MOTYP
TLC1540C,TLC1541C
1D-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073A- DECEMBER 1985 - REVISED MARCH 1995
operating sequence
11
I I I I I I I I
2
3
4
5
8
7
8
8 1 10
11
I I I I
2
3
4
51 8
I I I
7
8
9 1 10
1/0
CLOCK~
l
r"
I
I
Access
Cycle B
-JI I~
Sample _ _
Cycle B
~
Access
CS~~)~I______________________~
I
I
INPUT
I
SaaNotaC
MSB
ADDRESS ~
LSB
I
I+- CYCleC ~
I
I
~I________________~rI
~
B3 B2 B1 BO _----------~
Don'teare
Don't Care
DATAJ
OUT~
+---- Conversion Data B ----+~
+--- Previous Conversion Data A ---+~
MSB
(_Note B)
LSB MSB
MSB
LSB MSB
NOTES: A. The conversion cycle, which requires 44 system clock periods, initiates on the tenth falling edge of the 1/0 clock after CS goes low
for the channel whose address exists in memory at that time. If CS Is kept low during conversion, the 110 clock must remain low for
at least 44 system clock cycles to allow the conversion to complete.
B. The most signlflcantbit (MSB) is automatically placed on the DATA OUT bus afterCS is brought low. The remaining nine bits (AS-AO)
clock out on the first nine I/O clock falling edges.
C. To minimize errors caused by noise at the CS input, the intemal circuitry waits for three system clock cycles (or less) after a
chip-select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in
address data until the minimum chip-select setup time elapses.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) , .................................................. :....... 6.5 V
Input voltage range, VI (any input) ............................................ -0.3 V to Vee + 0.3 V
Output voltage range, Va ................................................... -0.3 V to Vee + 0.3 V
Peak input current (any input) ........................................................... ±10 mA
Peak total input current (all inputs) ....................................................... ±30 mA
Operating free-air temperature range, TA: TLC1540C, TLC1541 C ......................... O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 10 seconCls, Te: FN package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: OW or N package ........... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other cond~ions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated cond~ions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted).
~TEXAS
INSTRUMENTS
POST OFFICE BOX 656303 • OAu.AS. TEXAS 75265
2-87
TLC1540C,TLC1541C
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073A- DECEMBER 1985 - REVISED MARCH 1995
recommended operating conditions
MIN
NOM
4.75
5
Positive reference voltage, Vref + (see Note 2)
2.5
Negative reference voltage, Vref _ (see Note 2)
-0.1
Vee
0
VCC+O.l
2.5
Differential reference voltage, Vref+ - Vref- (see Note 2)
1
VCC
VCC+0.2
Analog input voltage (see Note 2)
0
High-level control input voltage, VIH
2
Supply voltage, VCC
Low-level control input voltage, VIL
0
Input/output clock frequency, fclockCl/O)
System clock frequency, fclocklSYS)
fclockCl/O)
400
Setup time, address bits before 1/0 CLOCKi,isuIA)
MAX
5.5
VCC
UNIT
V
V
V
V
V
V
0.8
V
1.1
MHz
2.1
MHz
ns
Hold time, address bits after VO CLocKi, ih(A)
0
ns
Setup time, CS low before clocking in first address bit,isu(CS) (see Note 3)
3
System
clock
cycles
Pulse duration, CS high during conversion, twH(CS)
44
Pulse duration, SYSTEM CLOCK high, twHlSYS)
210
Pulse duration, SYSTEM CLOCK low, twLISYS)
190
ns
Pulse duration, 1/0 CLOCK high,iwHCl/O)
404
ns
System
clock
cycles
Pulse duration, 1/0 CLOCK low, twL(I/O)
ns
ns
404
System
Clock transition time (see Note 4)
1/0
fclocklSYS) S 1048kHz
30
fclocklSYS) > 1048 kHz
20
fclock(I/O) S 525 kHz
100
fclockll/O) > 525 kHz
40
Operating free-alr temperature, TA
0
70
ns
ns
·C
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied
to REF- convert as aU zeros (0000000000). For proper operation, REF + voltage must be at least 1 V higher than REF- voltage.
Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
3. To minimize errors caused by noise at the chip select input, the intemal circuitry waits for three system clock cycles (or less) after
a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in
an address until the minimum chip select setup time elapses.
.
4. The amount oftime required for the clock input Signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal rcom temperature, the devices function with input clock transition time as slow as 2 JJ.S for remote data acquisition
applications where the sensor and the AID converter are placed several feet away from the controlling microprocessor.
~1EXAs.
2-88
INSTRUMENTS
POST OFFICE eox 655303 • DALLAS. TEXAS 75265
TLC1540C,TLC1541C
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073A-DECEMBER 1985-REVISEDMARCH 1995
electrical characteristics over recommended operating temperature range, Vee
5.5 V (unless otherwise noted), fcloCk(I/O) = 1.1 MHz, fclock(SYS) = 2.1 MHz
PARAMETER
TEST CONDITIONS
MIN
=Vref+ =4.75 V to
TYpt
MAX
VOH
High-level ouIput voltage (terminal 16)
Vee =4.75 V,
IOH =360 IlA
VOL
Low-level output voltage
Vee= 4.75 V,
IOL= 3.2 rnA
Vo=Vee,
esatVee
10
VO=O,
es at Vee
-10
IOZ
High-irnpedance-state output current
IlA
IlA
CSatOV
1.2
2.5
rnA
Selected channel at Vee,
Unselected channel at 0 V
0.4
1
-0.4
-1
ICC
Operating supply current
ei
Input capacitance
IlA
2.5
VI=O
Selected channel at 0 V,
Unselected channel at Vee
I Analog inputs
V
-2.5
V,.Vee
Low-level input current
Supply and reference current
V
0.4
0.005
High-level input current
ICC + lref
UNIT
-0.005
IIH
IlL
Selected channel leakage current
2.4
Vref+ = Vee,
eSatOV
I Control inputs
IlA
1.3
3
7
55
5
15
rnA
pF
t All typical values are at Vee. 5 V and TA _ 25°C.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALlAS. TEXAS 75265
2-89
TLC1540C, TLC1541 C .
1()"BITANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073A- DECEMBER 1986- REVISED MARCH 1995
operating characteristics over recommended operating temperature range, Vee = Vref+ = 4.75 V'to.
5.5 V, fclock(1I0) = 1.1 MHz, fclock(SYS) = 2.1 MHz
PARAMETER
EL
Unearity error
EZS
Zero-scale error
EFS
Full-scale error
ET
Total unadjusted error
tconv
TEST CONDITIONS
TLC1540
TLCl541.
TLCl540
TLCl541
TLCl540
TLC1541
TLCl540
TLCl541
MIN
See Note 5
See Notes 2 and 6
MAX
±0.5
±1
±0.5
±1
±0.5
See Notes 2 and 6
±1
±0.5
See Note 7
±1
0111110100
(500)
UNIT
LSB
LSB
LSB
LSB
1000001100
(524)
Self-test output code
Input All address. 1011 (see Note 8)
Conversion time
See Operating Sequence
21
Total access and conversion time
See Operating Sequence
31
IJ.8
IJ.8
VO
tacq
Channel acquisition time (sample cycle)
See Operating Sequence
tv
Time output data remains valid after 1/0 CLOCK!
ld
Delay time, I/O CLOCK! to DATA OUT valid
tan
Output enable time
ldls
tr(bus)
Output disable time
6
10
See Parameter
Measurement Information
Data bus rise time
clock
cycles
ns
400
ns
150
ns
150
ns
300
ns
300
ns
tf(bus) Data bus fall time
NOTES: 2. Analog Input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied
to REF- convert as all zeros (0000000000). For proper operation, REF+ voltage must be at least 1 V higher than REF-voltage.
Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
5. Unearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
6. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error Is the
difference between 1111111111 and the converted output for full-scale input voltage.
7. Total unadjusted error includes linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic. The All analog input signal is internally generatad and
used for test purposes.
~TEXAS .
2-90
INSTRUMENTS
POST OFFICE BOX 655303
TEXAS 76265
, • DAllAS.
.
TLC1540C,TLC1541C
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073A- DECEMBER 1985 - REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION
J
VCC
1.4V
kn
Output
Under Test
CL
(_NoteA)
Test
Point
Output
Under Test
n
Test
Point
CL
(_NoteA) I
T
Output
Under Test
Test
POint
CL
(_NoteA)I
3kn
SeeNoteB
SeeNoteB
LOAD CIRCUIT FOR
Id. t ... AND tf .
~
kn
LOAD CIRCUIT FOR
tpZL AND tpLZ
LOAD CIRCUIT FOR
tpZH AND tpHZ
_______ ::C
i~
I
I
SYSTEM
CLOCK
tpZL ~
Output Waveform 1
(_Note C)
---See-N-ot-e-B-----I!~..,\
tpZH
Output Waveform 2
(aee Note C)
4
~ tpLZ
I+-
.
¥,;____ :~
-
I+-
~ tpHZ
I ,..--_ _---11
___________.J15~
~----
::H
VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES
110 CLOCK
\ - - - - - - 0.4 V
I
/4-Id-+l
X-- - - - - - - - : :
O~
tr(bus)
I I
-+I I+-
N"---
2.4V
I - - - 0.4V
I
-+I I+- tf(bus)
DATA OUT_ _ _ _ _ _.J
VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES
VOLTAGE WAVEFORMS FOR DELAY TIME
NOTES: A. CL = 50 pF
B. ten - tpZH or tpZL and !dis ~ tpHZ or tpLZ.
C. Wavefonn 1 is for an output with intemal conditions such that the output is low except when disabled by the output control.
Wavefonn 2 is for an output with intemal conditions such that the output is high except when disabled by the output control.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 65S303. DALLAS, TEXAS 75265
2-91
.....
TLC1540C,TLC1541C
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073A- DECEMBER 1985 - REVISED MARCH 1995
APPLICATION INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 1, the time required to charge the analog input capacitance from 0 V to
Vs within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
Vc = Vs (1-e -te/RtCi )
(1 )
where
Rt=Rs+rj
The final voltage to 1/2LSB is given by
Vc (1/2 LSB) = Vs - (Vs/2048)
(2)
Equating equation 1 to equation 2 and solving for time (te) gives
Vs -(Vs/2048) = Vs (1_e-te/RtCI )
(3)
te (1/2 LSB) = Rt x Cj x In(2048)
(4)
and
Therefore, with the values given the time for the analog input signal to settle is
te (1/2 LSB) = (Rs + 1 kn) x 60 pF x In(2048)
(5)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet ..
Rs
I
I
I
I
VI
•
TLC1540/1
.,
VS~VC
I 1 kaMAX
II
I
CI
50 pF MAX
VI = Input Voltage at INPUT AO-A10
vS= External Driving Source Voltage
Rs = Source Resistance
rl = Input Resistance
CI = Input capacitance
t
Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.
Figure 1. Equivalent Input Circuit Including the Driving Source
~TEXAs
2-92
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TLC1540C,TLC1541C
10-81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073A- DECEMBER 1985 - REVISED MARCH 1995
PRINCIPLES OF OPERATION
The TLC1540 and TLC1541 are complete data acquisition systems on single chips. Each includes such functions
as sample and hold, 10-bit AID converter, data and control registers, and control logic. For flexibility and access
speed, there are four control inputs: chip select (CS), address input, I/O clock, and system clock. These control inputs
and a TIL-compatible, 3-state output are intended for serial communications with a microprocessor or
microcomputer. The TLC1540 and TLC1541 can complete conversions in a maximum of 21 IJ.S, while complete
input-conversion-output cycles can be repeated at a maximum of 31 IJ.S.
The system and I/O clocks are normally used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the device.
Once a clock signal within the specification range is applied to the SYSTEM CLOCK input, the control hardware and
software need only be concerned with addressing the desired analog channel, reading the previous conversion result,
and starting the conversion by using I/O CLOCK. SYSTEM CLOCK will drive the conversion-crunching circuitry so
that the control hardware and software need not be concerned with this task.
When ~ is high, DATA OUT is in a 3-state condition and ADDRESS INPUT and I/O CLOCK are disabled. This feature
allows each of these terminals, with the exception of the CS terminal, to share a control logic point with its counterpart
terminals on additional AID devices when using additional TLC1540/1541 devices. In this way, the above feature
serves to minimize the required control logic terminals when using multiple AID devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain
the conversion result. A normal control sequence is:
1. CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for two
rising edges and then a falling edge of SYSTEM CLOCK after a low CS transition before recognizing the
low transition. This technique protects the device against noise when the device is used in a noisy
environment. The MSB of the previous conversion result automatically appears on DATA OUT.
2. A new positive-logic multiplexer address shifts in on the first four rising edges of I/O CLOCK. The MSB of
the address shifts in first. The negative edges ofthese four I/O clock pulses shift outthe second, third, fourth,
and fifth most-significant bits of the previous conversion result. The on-chip sample-and-hold begins
sampling the newly addressed analog input after the fourth falling edge. The sampling operation basically
involves the charging of internal capacitors to the level of the analog input voltage.
3. Five clock cycles are then applied to the I/O CLOCK, and the sixth, seventh, eighth, ninth, and tenth
conversion bits shift out on the negative edges of these clock cycles.
4. The final tenth-clock cycle is applied to the I/O CLOCK. The falling edge of this clock cycle completes the
analog sampling process and initiates the hold function. Conversion is then performed during the next 44
system clock cycles. After this final 110 clock cycle, CS must go high or the I/O CLOCK must remain low for
at least 44 system-clock cycles to allow for the conversion function.
~ can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple conversion,
special care must be exercised to prevent noise glitches on I/O CLOCK. If glitches occur on I/O CLOCK, the I/O
sequence between the microprocessor/controller and the device loses synchronization. Also, if CS goes high, it must
remain high until the end of the conversion. Otherwise, a valid falling edge of CS causes a reset condition, which
aborts the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through
4 before the 44 system-clock cycles occur. Such action yields the conversion result of the previous conversion and
not the ongoing conversion.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2413
TLC1540C,TLC1541C
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073A- DECEMBER 1986 - REVISED MARCH 1995
PRINCIPLES OF OPERATION
It is possible to connect SYSTEM CLOCK and 1/0 CLOCK together in special situations in which controlling-circuitry
pOints must be minimized. In this case, the following special pOints must be considered in addition to the requirements
of the normal control sequence previously described.
1. This device requires the first two clocks to' recognize that CS is at a valid low level when the common clock
signal is used as an I/O CLOCK. When CS is recognized by the device to be at a high level, the common clock
signal is used for the conversion clock also.
2. A low CS must be recognized before the I/O CLOCK can shift in an analog channel address. The device
recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a
negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address.
Also, upon shifting in the address, CS must be raised after the tenth valid (12 total) I/O CLOCK. Otherwise,
additional common-clock cycles are recognized as I/O CLOCK cycles and shift in an erroneous address.
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.
This device accommodates these applications. Although the on-Chip sample-and-hold begins sampiing upon the
negative edge of the fourth valid I/O CLOCK cycle, the hold function does not initiate until the negative edge of the
eighth valid I/O CLOCK cycle. Thus, the control circuitry can leave the I/O CLOCK signal in its high state during the
tenth valid I/O CLOCK cycle until the moment at which the analog signal must be converted. The TLC1540ITLC1541
continues sampling the analog input until the eighth valid falling edge of the I/O CLOCK. The control circuitry or
software then immediately lowers the I/O CLOCK signal and holds the analog signal at the desired point in time and
starts the conversion.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.
~ThXAS
2-94
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 7&265
-TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10-81T ANALOG·TO·DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
•
•
•
•
•
•
•
•
•
1()'Blt-Resolutlon AID Converter
11 Analog Input Channels
Three Built-In Self-Test Modes
Inherent Sample and Hold
Total Unadjusted Error ..• ±1 LSB Max
On-Chip System Clock
End-of-Converslon (EOC) Output
Terminal Compatible With TLC1542
CMOS Technology
DB, J, DW, OR N PACKAGE
(TOP VIEW)
20
19
EOC
110 CLOCK
ADDRESS
DATA OUT
6CS
7
REF+
8
13 REF-
A3
A4
A5
AS
A7
AS
description
9
12 A10
10
11 A9
---'
GND
The TLC1543C, TLC15431, and TLC1543Q are CMOS
1Q-bit, switched-capacitor, successive-approximation,
analog-to-digital converters. These devices have three
inputs and a 3-state output [chip select (CS) ,
input-output clock (I/O CLOCK), address input
(ADDRESS), and data output (DATA OUTl] that
provide a direct four-wire interface to the serial port of
a host processor. These devices allow high-speed data
transfers from the host.
VCC
......
FK OR FN PACKAGE
(TOP VIEW)
00
~ :( ~?@
A3
A4
A5
4 3 2 1 20 1918
1/0 CLOCK
5
17
6
16
ADDRESS
DATAOUT
CS
REF+
7
15
AS
In addition to a high-speed AID converter and versatile
A7
8
14
control capability, these devices have anon-chip
9 10 11 12 13
14-channel multiplexer that can select anyone of 11
eooenel
analog inputs or anyone of three internal self-test
'
BINARY
HEX
Vref+ - Vref-
l!
1011
B
200
Vref-
1100
C
000
1101
0
3FF
Vref+
t Vref+ is the voltage applied to the REF+ input, and Vref- is the voltage applied to the REFinput
; The output results shown are the ideal values and vary with the reference stability and with
internal offsets.
converter and analog Input
The CMOS threshold detector in the successive-approximatfon conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the Se switch and all Sr switches simultaneously.
This action charges all the capaCitors to the input voltage.
In the next phase of the conversion process, all Sr and Se switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-)
voltage. In the switching sequence, ten capaCitors are examined separately until.all ten bits are identified and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector
looks at the first capacitor (weight = 512). Node 512 of this capaCitor is switched to the REF+voltage, and the
equivalent nodes of all the other capaCitors on the ladder are switched to REF-. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half Vee), a 0 bit is placed in the
output register and the 512-weight capacitor is switched to REF-. If the voltage at the summing node is less
than the trip point of the threshold detector, a 1 bit is placed in the register and the 512-weight capacitor remains
connected to REF + through the remainder of the successive-approximation process. The process is repeated
for the 256-weight capacitor, the 128-weight capaCitor, and so forth down the line until all bits are counted.
2-100
-!lThxAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10-81T ANALOG·TO·DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052C - MARCH 1992 - REVISED MARCH 1995
converter and analog Input (continued)
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.
Be
Threshold
Detector
51J 25J 12J 18
To Output
Latches
j
I
-~t~t;:;t~t~t;:;t;;,t~f
REF-
~~SyREF-~_SyREF-~~SyREF-~!rREF-~~SyREF-~~ REF-~!rREF-~~
v,j j j\J j
T
~~
ro<
REF-
iii
j
Figure 1. Simplified Model of the Successive-Approximation System
chip-select operation
The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.
A high-to-Iow transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the contents of the output data register remain at the previous conversion result).
Exercise care to prevent CS from being taken low close to completion of conversion because the output data
can be corrupted.
reference voltage Inputs
There are two reference inputs used with the device: REF + and REF-. These voltage values establish the upper
and lower limits of the analog input to produce a full-scale and zero reading, respectively. The values of REF +,
REF-, and the analog input should not exceed the positive supply or be lower than GND consistent with the
specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher
than REF + and at zero when the input Signal is equal to or lower than REF-.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
2-101
TLCt542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10·BIT ANALOG·TO·DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052C - MARCH 1992 - REVISED MARCH 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ....•....... ~ '. . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. -0.5 V to 6.5 V
Input voltage range, VI .......................................... , ........... -0.3 V to Vee + 0.3 V
Output voltage range, Vo ................................................... -0.3 V to Vee + 0.3 V
Positive reference voltage, Vref+ .......... : ......•.................................... Vee + 0.1 V
Negative reference voltage, Vref- .......................................................... -0.1 V
Peak input current (any input) .....................................................•..... ±20 mA
Peak total input current (all inputs) ....................................................... ±30 mA
Operating free-air temperature range, TA: TLC1542C, TLC1543C ....................... DoC to 70°C
TLC15421, TLC15431 ........................ -40°C to 85°C
TLC1542Q, TLC1543Q .................... -40°C to 125°C
TLC1542M ............... ,.............. -55°C to 125°C
Storage temperature range, Tstg. .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ............................ 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF - and GND wired together (unless otherwise noted).
recommended operating conditions
Supply voltage, Vee
,
MIN
NOM
MAX
4.5
5
5.5
Positive reference voltage, Vref + (see Note 2)
2.5
Differential reference voltage, Vref + - Vref- (see Note 2)
Analog input voltage (see Note 2)
0
High-level control input voltage, VIH
I VCC -4.5 Vt05.5 V
Low-level control Input voltage, VIL
I VCC =4.5 Vt05.5 V
Setup time, address bits at data input before 1/0 CLOCKi,\su(A)
Hold time, address bits after 1/0 CLOCKt, theA)
Hold time, CS low after last 1/0 CLOCK!, thlCS)
Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3)
Clock frequency at 1/0 CLOCK (see Note 4)
V
VCC+O.2
V
VCC
V
0.8
V
2
,
V
100
ns
0
ns
0
ns
1.425
0
Pulse duration, I/O CLOCK high,iwH(t/O)
190
Pulse duration, 1/0 CLOCK low, twLIIIO)
190
Transition time, 1/0 CLOCK, tl(l/O) (see Note 5 and Figure 6)
JJS
2.1
ns
10
TLC1542C,TLC1543C
0
MHz
ns
1
Transition time, ADDRESS and CS, tt(CS)
Operating free-air temperature, TA
VCC
V
V
VCC
0
Negative reference voltage, Vref- (see Note 2)
UNIT
JJS
JJS
70
TLC15421, TLC15431
-40
85
TLCI542Q,TLCI543Q
-40
TLC1542M
-55
125
125
·C
NOTES: 2. Analog Input voltages greater than that applied to REF+ convert as all ones (1111111111), while Input voltages less than that applied
to REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref + - Vref-); however,
the electrical specifications are no longer applicable.
3. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two failing edges of the intemal system
clock after CS! before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (5 2 V) at least 1 I/O CLOCK rising edge ~ 2 V) must occur within
9.5 JJS.
5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 JJS for remote data-acquisition applications
where the sensor and the ND converter are placed several feet away from the controlling microprocessor.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10·81T ANALOG·TO·DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052C - MARCH 1992 - REVISED MARCH 1995
electrical characteristics over recommended operating free-air temperature range,
Vee = vref+ = 4.5 V to 5.5 V, 1/0 CLOCK frequency = 2.1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYpf
MIN
IOH--l.6mA
2.4
Vec = 4.5 V to 5.5 V.
IOH =-20 jlA
VCC-0.1
Vec- 4.5V•
IOL-l.6mA
0.4
Vec = 4.5 V to 5.5 V.
IOL=20 jlA
0.1
VOH
High-level output voltage
VOL
Low-level output voltage
Off-state (high-impadance-state)
output current
VO-Vcc.
CSatVcc
10
IOZ
VO·O.
cs at VCC
-10
IIH
High-level input current
VI-Vce
IlL
Low-level input current
VI-O
ICC
Oparating supply current
CSatOV
Selected channel leakage
currentTLC1542fTLC1543
C.I.orQ
Selected channel at VCC. Unselected channel at 0 V
Selected channel at 0 V.
Selected channel leakage
current TLCl542M
Selected channel at 0 V.
TAz25°C
2.5
jlA
-2.5
jlA
0.8
2.5
rnA
1
-'
jlA
-1
1
Unselected channel at VCC.
CI
Input
capacitance
Unselected channel at VCC
Vraf+=VeC.
Vref_=GND
jlA
0.005
Unselected channel at Vce
Selected channel at 0 V.
V
-0.005
-1
jlA
2.5
Selected channel at VCC. Unselected channel at 0 V
Maximum static analog reference
current into REF +
UNIT
V
Selected channel at VCC. Unselected channel at 0 V.
TA=25°C
t
MAX
Vec- 4.5V•
-2.5
10
IAnalog inputs
7
I Control inputs
5
jlA
pF
All typical values are at Vec = 5 V. TA = 25°C.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75266
2-103
TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
1()'BIT ANALOG·TO-D.IGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052C - MARCH 1992 - REVISED MARCH 1995
operating characteristics over recommended operating free-air temperature range,
Vee = Vref+ =4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)
TEST CONDITIONS
EL
EZS
EFS
Linearity error (see Note 6)
Zero-scale error (see Note 7)
Full-scale error (see Note 7)
Total unadjusted error (see Note 8)
MIN
MAX
UNIT
±0.5
LSB
TLC1543C, I, or a
±1
LSB
TLC1542M
±1
LSB
TLCl542C,I, or a
See Note 2
±0.5
LSB
TLC1543C,I, or a
See Note 2
±1
LSB
TLC1542M
See Note 2
±1
LSB
TLC1542C,I, or a
See Note 2
±0.5
LSB
TLCl543C,I, ora
See Note 2
±1
LSB
TLC1542M
See Note 2
±1
LSB
TLC1542C,I, ora
±1
LSB
TLCl543C,I, ora
±1
LSB
TLCl542M
±1
LSB
See timing diagrams
21
IJS
21
+101/0
CLOCK
periods
IJS
ADDRESS .. 1011
Self-test output code (see Table 3 and Note 9)
!conv
TYpt
TLC1542C, I, or a
Conversion time
ADDRESS~
512
1100
0
ADDRESS .. 1101
1023
!c
total cycle time (access, sample, and conversion)
See timing diagrams
and Note 10
tacq
Channel acquisition time (sample)
See timing diagrams
and Note 10
tv
Valid time, DATA OUT remains valid after 110 CLOCKJ.
See Figure 6
Id(//O-DATAI
Delay time, 110 CLOCKJ. to DATA OUT valid
See Figure 6
Id{l/O-EOCI
Delay time, tenth I/O CLOCKJ. to EOCJ.
See Figure 7
6
10
I/O
CLOCK
periods
ns
70
240
ns
240
ns
100
ns
See Figure 8
td(EOC-DATA) Delay time, EOCi to DATA OUT (MSB)
t All typical values are at TA .. 25°C.
NOTES: 2. Analog input voltages greater than that applied to REF + convert as a/l ones (1111111111), while input voltages less than that applied
to REF - convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref + - Vref-); however,
the electrical specifications are no longer applicable.
6. Linearity error Is the maximum deviation from the best straight line through the AID transfer characteristics.
7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1111111111 anc:! the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the Input address and the output codes are expressed in positive logic.
10. I/O CLOCK period = 1/(lfO CLOCK frequency) (see Figure 6)
~TEXAS
2-104
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052C - MARCH 1992 - REVISED MARCH 1995
operating characteristics over recommended operating free-air temperature range,
Vcc = Vref+ = 4.5 V to 5.5 V, 1/0 CLOCK frequency = 2.1 MHz (unless othelWise noted) (continued)
TEST CONDITIONS
MIN
TYpt
MAX
UNIT
IPZH,IPZL
Enable time, CSJ. 10 DATA OUT (MSB driven)
See Figure 3
1.3
IPHZ,lpLZ
Disable time, csT 10 DATA OUT (high impedance)
See Figure 3
150
J1S
ns
ir{EOCI
Rise lime, EOC
See FigureS
300
ns
If{EOCI
Fall time, EOC
See Figure 7
300
ns
Ir{DATAI
Rise lime, data bus
See Figure 6
300
ns
IfCDATAl
Fall lime, data bus
See Figure 6
300
ns
ic:I(I/O-CS)
Delay lime, tenth I/O CLOCK.!. 10 CS.!. 10 abort
conversion (see Note 11)
9
lIS
t All typical values are at TA • 25°C.
NOTE 11. Any lransHlons of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock
(1.425 lIS) after the transHion.
PARAMETER MEASUREMENT INFORMATION
Vee
Teat Point
Test Point
VCC
'=~8~
EOC
'=~S~
DATA OUT -
......___-4~te--..
Figure 2. Load Circuits
~
r-or-
cs
~
tpZH. tpZL
DATA
OUT
2VTI
~~~~~8~v........J/!
....l.....-.t
1I
T
2.4 V
0.4 V \
ADDRESS
""------...L
~ tpHZ, tPLZ
isu(A)
'\ 900/0
I/O CLOCK
-1100/0
Figure 3. DATA OUT Enable and Disable
Voltage Waveforms
==><~.:
I
14
Address -----.J
Valid -----.,
:X==
V
I
~ ~ th(A)
'! J.
0.8VY·
Figure 4. ADDRESS Setup and Hold Time
Voltage Waveforms
~TEXAS
INSTRUMENTS
POST OFFICE BOX 856303 • DAlLAS. TEXAS 75265
2-105
TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052C - MARCH 1992 - REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION
cs
\-0.8V
tsu(CS)
2
II
I
II
~
...
~I
14
I
1/0 CLOCK
Til
th(CS)
1
ir;;;;\.
f;:;\.i
yr--/ CIo~k ~
~ CI~~k
Figure 5. 1/0 CLOCK Setup and Hold Time Voltage Waveforms
tt(I/O)
~
~ l+I 1
tt(I/O)
1
1/0 CLOCK
0.8 V
I+--
1/0 CLOCK Period
--+I
0.8 V
14 ~I
--14-+1 I
ld(l/o-DATA)
tv
2.4
DATA OUT
0.8 V
v~ ~ 2.4 V
__~0~.4~V~)\~_~0.4~V~____________
I I
i+-
~
tr(DATA). t'(DATA)
Figure 6. 1/0 CLOCK and DATA OUT Voltage Waveforms
I/O CLOCK
/
---./
10th
Clock
\
.
...
_ ...;.0.-.8V
_ _ _ _ _ __
I
ld(l/o-EOC) ---i1~4---~~1
I
2.4 V
EOC
'N.
I
0.4 V
I
t'(EOC) ~ I + -
Figure 7. 1/0 CLOCK and EOC Voltage Waveforms
~
EOC
!+-
tr(EOC)
!1 2•4v
~i
I4-ld(EOC-DATA)
DATA OUT _ _ _ _ _ _ _
~
--C~2.4 v
\~_0....4-.;V_ _ __
I
14--
Valid MSB
--+
Figure 8. EOC and DATA OUT Voltage Waveforms
~TEXAS
2-106
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 15265
TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10·81T ANALOG·TO·DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052C - MARCH 1992 - REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION
timing diagrams
sl. . ._
CSI
(see Nota A)
1/0
r~------------------------------------------~
CLOCK_+-~
------~
1
HI·Z8tate
DATA
OUT
........~~
1
~
1
1
1
1
,-------~~
1
141.------ Previous Conversion Data -------+l~1
1 M8B
LSB
ADDRESS
B3
MSB
EOC
B2
B1
-~~
I
-~~
1
J~
Initialize
1
I
BO
LSB
1
1
_---ar'r!-(jl-
1--1
Shift In N_ Multiplexer Address;
1
Simultaneously Shift Out Previous ------~~ioII.....----~~1
Conversion Value
AID Conversion
Interval
Initialize
Figure 9. Timing for 10-Clock Transfer Using CS
NOTE A: To minimize errors caused by noise at CS, the intemal circuitry waits for a setup time plus two falling edges of the intemal system clock
aller CSJ.. before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
:JI.1ExAs
INSTRUMENTS
POST OFFICE BOX 666303 • DAUAS. TEXAS 75265
2-107
....
TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TlC15431, TLC1543Q
10;.81T ANALOG-TO-DIGITAl CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052C - MARCH 1992 - REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION
_~ Must be High on Power Up
CS
(~NomA)
I/O
CLOCK
~
----------------------------------------------------~~~
1
1
2
--M
I+-
1
DATA
----.lr A9
OUT~
14
1
3
Access Cycle B - - M - - - AS
'------~~
----+/
A7
I
I
MSB
~
ADDRESS
i~
I
~~
1((
EOC
~
Low Level
--,
Shift In New Multiplexer Addressj
I f - - - - - - Simultaneously Shift Out Previous ------*----------+1
Conversion Value
Initialize
A/D Converelon
Inmrval
Initialize
Figure 10. Timing for 1()'Clock Transfer Not Using CS
NOTE A: To minimize errors caused by noise at es, the intemal circuitry waits for a setup time plus two falling edges of the intemal system clock
aiter es.!. before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
es setup time has elapsed.
~TEXAS
2-108
INSTRUMENTS
POST OFACE BOX 655303 • DAU.AS. TEXAS 75265
TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10-81T ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052C - MARCH 1992 - REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
See NoteC
(_NOC:A~
UO
CLOCK
111111111
\11--
r1~
,
_+---!
,
Low
,
,~L~ev:e:'I..J.ZiHrl•.;;;Z;~
DATA
OUT
i 4 - = : - - - - - - Previous Conversion Data ------L:-:S~B-+I.'
B3
B2
B1
\~
I
I
ADDRESS
MSB
,
BO
LSB
EOC
Shift In New Multiplexer Addressi
I f - - - - - - - Simultaneously Shift Out Previous
Conversion Value
Initialize
.~
\~
AID Conversion
Interval
·:1'
Initialize
Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion)
It
II
~___L_o_w_L_ev_e_I__~~
,
,
~
,
ADDRESS
I--------;IJ
-1
EOC
L
Shift In New Multiplexer Address; --------.t4-- AID Conversion
~I'I----- Simultaneously Shift Out Previous
.,..
Interval
Conversion Value
Initialize
Initialize
Figure 12. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Shorter Than Conversion)
NOTES: A. To minimize errors caused by noise at CS, the internal circUitry waits for a setup time plus two falling edges of the intemal system
clock after cS".!. before responding to control input Signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. The first 1/0 CLOCK must occur after the rising edge of EOC.
C. A low·ta-high transition of CS disables ADDRESS and the 1/0 CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock.
'
-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-109
TLC1542C, TLC15421, TLCt542M, TLC1542Q, TLC1543C, .TLC15431, TLC1543Q
10-81T ANALOG·TO·DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052C - MARCH 1992 '- REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
111111111 rj~....._
CS~
(see Note A)
I/O
CLOCK
I
I
I
11
--+_-!
I
(181 ~ I r.j1
.... L.~·L
I
I
SeeNoteB
I
DATA
OUT
I
Low . HI·ZState ~
Level
I.~
I
I
I4-:M::-:S~B~---- Previous Conversion Data ------:L~S=B+I~:
~~
I
ADDRESS
B3
MSB
EOC
B2
BO
LSB
J~
.
..
Initialize
I ·11111111
Shift In New Multiplexer Address;
;
I
Simultaneously Shift O.ut Prevloua ------+~1,.4---.,~
Conversion Value
AID Conversion
Interval
II
I
Initialize
NOTES: A. To minimize errors caused by noise at es, the Internal circuitry waits for a setup time plus two falling edges of the internal system
clock after es'!' before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CSse\up time has elapsed.
B. The 11 th rising edge of the 1/0 CLOCK sequence must occur before the conversion is complete to prevent lOSing serial interface
synchronization.
Figure 13. Timing for 11· to 16-Clock Transfer Using CS (Serial Transfer Interval Longer Than Conversion)
~1ExAs
2-110
'
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052C - MARCH 1992 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
_~ Must be High on Power Up
CS
,
(see Note A)
"II
I
1
1/0 1
CLOCK-t-S
1
1
l+-
DATAJ; A9
OUT~
r
2
~~
See
1
3
Access Cycle B - - ! f - - - AS
A7
Note B
LowL~el
AS
~B~
I1
I
I1
-4\~----------------;I1
EOC
I
MSB
ADDRESS
1
1
1
MSB
I.
Shift In New MUltiplexer Address;
..
j e - - - - - Simultaneously Shift Out Previous
1
1
1
See Note C
~
I
~
C3
II
II
I
-----~~I4f---~~
Conversion value
Initialize
AID Conversion
Interval
NOTES: A. To minimize errors caused by noise at ~, the internal circuitry walts for a setup tlma plus two falling edges of the intemal.ystem
clock after CSJ. before responding to control input signals. Therefore, no attempt should be made to clock in an addres$ until the
minimum CS setup time has elapsed.
B. The 11 th rising edge of the 110 CLOCK sequence must occur before the conversion is complete to prevent losing serial interf~
synchronization.
.
C. The 110 CLOCK sequence is exactly 16 clock pulses long.
Figure 14. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Longer Than Conversion)
~TEXAS
INSTRUMENTS
POST OFFICE BOX e65303 • DAllAS. TEXAS 75265
2-111
TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC1S431, TLC1543Q
10-BIT ANALOG-TO-DIGITAL.CONVERTERS WITH
SERIAL CONTROL AND 1tANALOG INPUTS
SLAS052C - MARCH 1992 - REVI.SED MARCH 1995
APPLICATION INFORMATION
1111111111
See
NO~es A andl B
./ ~
1111111110
1111111101
t
U
lA:;
1000000001
~
'5
.&
1000000000
::J
Q
j
0111111111
/)::::
/
••
•
0000000001
0000000000
_I.
VFS
o
VFT
V
~ 0.0048 0.0096
=VFS -1/2 LSB
Ii
2
Ii
2.4576
2.4624
o
d
••
•
•••
12.
II
511
I
I
Ii
2.4528
1021
612
I
I
•••
1022
613
I
I
/'
I~ /t'/""
IIVl~V
~
l
1023
/!
./ . /
VZS
0000000010
./
~ /'
VZT =VZS + 1/2 LSB
0
~
g
~1 \
/1I
)~
/'
••
•
V
••
•
o
4.905614.9104 4.9152
ol
VI - Analog Input Voltage - V
NOTES: A. This curve is based on the assumption that Vref+ and Vref- have been adjusted so that the voltage at the transition from digital 0
to 1 (VZT) is 0.0024 V and the transition to full scale (VFT) is 4.908 V. 1 LSB - 4.8 mV.
.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (Vzsl is
the step whose nominal midstep value equals zero.
Figure 15. Ideal Conversion Characteristics
TLC1542143
1
Analog
Inputs
~
AO
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
11
A9
12
A10
1/0 CLOCK
ADDRESS
15
18
17
Processor
DATA OUT
EOC
REF+
REF-
16
19
14
r.:--+
~
5-V DC Regulator
GND
101
ToSourca
Ground
I
.1
Figure 16. Serial Interface
~TEXAS .
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS. TEXAS 75265
Control
Circuit
TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10-BITANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052C - MARCH 1992 - REVISED MARCH 1996
APPLICATION INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 17, the time required to charge the analog input capacitance from 0 to Vs
within 112 LSB can be derived as follows:
The capacitance charging voltage is given by
Vc = Vs
(1-e -t c/RtCj )
(1 )
where
Rt=Rs+rj
The final voltage to 1/2 LSB is given by
Vc (1/2 LSB) = Vs - (VsI2048)
(2)
Equating equation 1 to equation 2 and solving for time to gives
Vs -(Vsl2048) = Vs
(1-e -t c/RtCj)
(3)
and
tc (1/2 LSB) = Rt x Cj x In(2048)
(4)
Therefore, with the values given the time for the analog input signal to settle is
to (112 LSB) = (Rs + 1 kn) x 60 pF x In(2048)
(5)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet 4
Rs
I
I
I
I
•
VI
TLC154213
rl
VS~VC
!
1 kCMAX
I
I
.1
'1'
m
CI
50pFMAX
VI = Input Voltage at AO-A10
VS= External Driving Source Voltage
Rs = Source Resistance
rl = Input Resistance
CI = Equivalent Input Capacitance
t Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.
Figure 17. Equivalent Input Circuit Including the Driving Source
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-113
2-114
TLC1549C, TLC15491, TLC1549M
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH
•
•
•
•
•
1G-Blt-Resolutlon AID Converter
Inherent Sample and Hold
Total Unadjusted Error ... ± 1 LSB Max
On-Chip System Clock
Terminal Compatible With TLC549 and
TLV1549
D, JG, OR P PACKAGE
(TOP VIEW)
REF+(J8
ANALOG IN
2
7
REF3
6
GND
4
5
• CMOS Technology
VCC
I/O CLOCK
DATA OUT
~
FKPACKAGE
(TOP VIEW)
description
o~ooo
The TLC1549C, TLC15491, and TLC1549M
are 1O-bit, switched-capacitor, successiveapproximation
analog-to-digital converters.
These devices have two digital inputs and a
3-state output [chip select (CS), input-output clock
(1/0 CLOCK), and data output (DATA OUT)] that
provide a three-wire interface to the serial port of
a host processor.
za:z$'z
NC
ANALOG IN
NC
NC
The sample-and-hold function is automatic. The
converter incorporated in these devices features
differential high-impedance reference inputs that
facilitate ratiometric conversion, scaling, and
isolation of analog circuitry from logic and supply
noise. A switched-capacitor design allows lowerror conversion over the full operating free-air
temperature range.
4
5
6
3 2 1 2019
18
17
16
15
14
8
9 10 11 12 13
NC
I/O CLOCK
NC
DATA OUT
NC
ozzzoz
COl(/) 0
C!'
NC - No inlernal connection
The TLC1549C is characterized for operation from O°C to 70°C. The TLC15491 is characterized for operation
from -40°C to 85°C. The TLC1549M is characterized for operation over the full military temperature range of
-55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(D)
CHIP CARRIER
(FK)
CERAMIC D.IP
(JG)
PLASTIC DIP
(P)
O·C10 70·C
TLC1549CD
-
-
TLC1549CP
-40·C 10 85·C
TLC1549ID
-
TLC15491P
-55·C to 125·C
-
TLC1549MFK
TLC1549MJG
~TEXAS
-
CopyrIght © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 666303 • DALlAS, TEXAS 75266
2-115
TLC1549C, TLC15491, TLC1549M
1()'BIT ANALOG-TO-DIGITAL CONVERTERS
.. WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995
functional block diagram
REF+
I1
REF-
I3
1Q..Blt
Analog-to-Dlgltal
Converter
(switched capaCitors)
10
ANALOG IN
-
2
Output
Data
Reglatar
Sample and
Hold
~
1Q..to-1 Data
8
Salector and ,.-- DATA OUT
Driver
4
-
110 CLOCK
CS
Syatem Clock,
Control LogiC,
and 110
Counters
+
7
5
Terminal numbers shown are for the D. JG. and P packages only.
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 kOTYP
ANALOGIN~
I
CI=80pFTYP
(equivalent Input
capacltanca)
ANALOGIN~
~1ExAs
2-116
INSTRUMENTS
POST OFACE BOX 665303 • DALlAS. TEXAS 75266
;h
5 MOTYP
TLC1549C, TLC15491, TLC1549M
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1996
Tenninal Functions
TERMINAL
NAME
NO.
110
DESCRIPTION
ANALOG IN
2
I
Analog signal input. The driving source impedance should be s 1 kn The external driving source to ANALOG IN
should have a current capability ~ 10 mAo
CS
5
I
Chip select. A high-la-low transition on CS resets the intemal counters and controls and enables DATA OUT and
1/0 CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. A low-ta-high
transition disables 1/0 CLOCK within a setup time plus two falling edges of the internal system clock.
DATA OUT
6
0
This 3-state serial output for the AID conversion result is in the high-impedance state when CS is high and active
when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance state and is driven to
the logic level corresponding to the MSB value of the previous conversion result. The next falling edge of 1/0 CLOCK
drives DATAOUT to the logic level corresponding to the next most significant bit, and the remaining bits are shifted
out in order with the LSB appearing on the ninth falling edge of 1/0 CLOCK. On the tenth falling edge of 1/0 CLOCK,
DATA OUT is driven to a low logic level so that serial interface data transfers of more than ten clocks produce zeroes
as the unused LSBs.
The ground return for internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.
GND
4
I/O CLOCK
7
I
Input/output clock. 1/0 CLOCK receives the serial 110 CLOCK input and performs the following three functions:
1) On the third falling edge of 1/0 CLOCK, the analog input voltage begins charging the capaCitor array and
continues to do so until the tenth falling edge of 1/0 CLOCK.
2) It shifts the nine remaining' bits of the previous conversion data out on DATA OUT.
3) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.
REF+
1
I
The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range is
determined by the difference between the voltage applied to REF + and the voltage applied to REF-.
REF-
3
I
The lower reference voltage value (nominally ground) is applied to REF-.
VCC
8
Positive supply voltage
detailed description
With chip select (CS) inactive (high), I/O CLOCK is initially disabled and DATA OUT is in the highimpedance state. When the serial interface takes CS active (low), the conversion sequence begins with the
enabling of I/O CLOCK and the removal of DATA OUT from the high-impedance state. The serial interface then
provides the I/O CLOCK sequence to I/O CLOCK and receives the previous conversion result from DATA OUT.
I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface.
The first ten I/O clocks provide the control timing for sampling the analog input.
There are six basic serial interface timing modes that can be used with the TLC1549. These modes are
determined by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a
fast mode with a 1O-clock transfer and CS inactive (high) between transfers, (2) a fast mode with a 10-clock
transfer and CS active (low) continuously, (3) a fast mode with an 11- to 16-clpck transfer and CS inactive (high)
between transfers, (4) a fast mode with a 16-bit transfer and CS active (low) continuously, (5) a slow mode with
an 11-to 16-clock transfer and CS inactive (high) between transfers, and (6) a slow mode with a 16-clock transfer
and CS active (low) c~ntinuously.
The MSB of the previous conversion appears on DATA OUT on the falling edge of CS in mode 1, mode 3, and
mode 5, within 21 J.IS from the falling edge of the tenth 1/0 CLOCK in mode 2 and mode 4, and following the
sixteenth clock falling edge in mode 6. The remaining nine bits are shifted out on the next nine falling edges of
1/0 CLOCK. Ten bits of data are transmitted to the host serial interface through DATA OUT. The number of serial
clock pulses used also depends on the mode of operation, but a minimum of ten clock pulses is required for
conversion to begin. On the tenth clock falling edge, the internal logic takes DATA OUT low to ensure that the
remaining bit values are zero if the 1/0 CLOCK transfer is more than ten clocks long.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-117
TLC1549C, TLC15491, TLC1549M
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
NI'JC" DECEMBER 1992 - REVISED MARCH 1995
detailed description (continued)
. table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that
.. ·.···eanbe used, and the timing on which the MSB of the previous conversion appears at the output.
;'
Table 1. Mode Operation
cs
MODES
Fast Modes
Slow Modes
NO. OF
If0 CLOCKS
Msa AT Terminal at
TIMING
DIAGRAM
Model
High between conversion cycles
10
C§ falling edge
Figure 6
Mode 2
Low continuously
10
Within 21 lIS
Figure 7
Mode 3
High between conversion cycles
11 to 16*
C§ failing edge
Figure 8
Mode 4
Low continuously
Mode 5
High between conversion cycles
16*
11 to 16*
Within 21 lIS
C§ falling edge
Figure 10
Mode 6
Low continuously
16th clock falling edge
Figure 11
. . also .Initiates
.. senallnterfaca communication.
t this tnnmg
16*
Figure 9
*No more than 16 clocks should be used.
All the modes require a minimum period of 21 J.1S after the falling edge of the tenth I/O CLOCK before a new
.transfer sequence can bell!!:!: During a serial I/O CLOCK data transfer, CS must be active (low) so that I/O
CLOCK is enabled •. When CS is toggled between data transfers (modes 1, 3, and 5), the transitions at CS are
recognized as valid only if the level is maintained for a minimum period of 1.425 J.1S after the transition. If the
transfer is more than ten I/O clocks (modes 3, 4, 5, and 6), the rising edge of the eleventh clock must occur within
9.5J.1S after the falling ed~cif the tenth I/O CLOCK; otherwise, the device could lose synchronization with the
. host serial interface and CS has to be toggled to restore proper operation.
fast !nodes
The TLC 1549 is in a fast mode when the serial I/O CLOCK data transfer is completed within 21 J.1S from the falling
edge of the tenth I/O CLOCK. With a ten-clock serial transfer, the device can only run in a fast mode.
as
modtl1: fast mode,
Inactive (hIgh) between transfers, 1O-Clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The
faJlJ..i}g edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge
of OS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.
Also, the rising edge of CS disables I/O CLOCK within a setup time plus two falling edges of the internal system
cloek~
as
mode 2: fast mode,
active (low) continuously, 1o-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After
the initial conversion cycle, CS is held active (low) for subsequent conversions. Within 21 J.1S after the falling edge
of the tenth I/O CLOCK, the MSB of the previous conversion appears at DATA OUT.
as
mode 3: fast mode,
inactive (hIgh) between transfers, 11· to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks
long. The fallinLedge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequenc~ returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables 1/0 CLOCK within a setup time plus two falling edges of the
internal system clock.
mode 4: fast mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. Within 21 J.1S after
the falling edge of the tenth I/O CLOCK, the MSB of the previous conversion appears at DATA OUT.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 665303 • OALLAS, TEXAS 76266
TLC1549C, TLC15491, TLC1549M
1O-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995
slow modes
In a slow mode, the serial 110 CLOCK data transfer is completed after 21
110 CLOCK.
~
from the falling edge of the tenth
mode 5: slow mode, CS Inactive (hIgh) between transfers, 11· to 16-clock transfer
In this mode, CS is inactive (high) between serial 1/0 CLOCK transfers and each transfer can be 11 to 16 clocks
long. The fallin~dge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequenc~ returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables 110 CLOCK within a setup time plus two falling edges of the
internal system clock.
mode 6: slow mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial 1/0 CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of
the sixteenth 1/0 CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the
MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next-16
clock transfer initiated by the serial interface.
analog Input sampling
Sampling of the analog input starts on the falling edge of the third 1/0 CLOCK, and sampling continues for seven
1/0 CLOCK periods. The sample is held on the falling edge of the tenth 1/0 CLOCK.
converter and analog Input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capaCitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the Sc switch and all Sr switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all Sr and Sc switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified al]d
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector
looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF-. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half Vee), a bit 0 is placed in the
output register and the 512-weight capacitor is switched to REF-. If the voltage at the summing node is less
than the trip point of the threshold detector, a bit 1 is placed in the register and this 512-weight capacitor remains
connected to REF + through the remainder of the successive-approximation process. The process is repeated
for the 25?-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are determined.
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265
2-119
TLC1549C, TLC15491, TLC1549M
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995
converter and analog Input (continued)
Threshold
Detector
I
..":t~t,;:;t,;:;t~t,;:;t,;:;t,;:;f
51J
2561
128
ToOulput
Latches
'I 18
T
REF-~~S:EF-~~SrREF-~~REF-~~SrREF_~~REF-~~S:EF-~.SrREF-~~ REF-~~
ro<
. j 1 1 m1 j 1 1 1 j
Figure 1. Simplified Model of the Successive-Approximation System
chip-select operation
The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.
A high-ta-Iow transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device
.returns to the initial state (the contents of the output data register remain at the previous conversion result). Care
should be exercised to prevent CS from being taken low close to completion of conversion because the output
data may be corrupted.
reference voltage Inputs
There are two reference inputs used with the TLC1549: REF+ and REF-. These voltage values establish the
upper and lower limits of the analog input to produce a full-scale and zero reading respectively. The values of
REF.+, REF-, and the analog input should not exceed the positive supply or be lower than GND consistent with
the specified absolute maximum ratings. The digital output is at full scale when the input Signal is equal to or
higher than REF+ and at zero when the input signal is equal to or lower than REF-.
~TEXAS .
2-120
INSTRUMENTS
POST OFFICE BOX 855303 • DALlAS. T~ 75265
TLC1549C, TLC15491, TLC1549M
1O-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1): TLC1549C, TLC15491 ....................... -0.5 V to 6.5 V
TLC1549M ................................... -0.5 V to 6 V
Input voltage range, VI (any input) ............................................ -0.3 V to Vee + 0.3 V
Output voltage range, Vo ................................................... -0.3 V to Vee + 0.3 V
Positive reference voltage, Vref+ ...................................................... Vee + 0.1 V
Negative reference voltage, Vref- .......................................................... -0.1 V
Peak input current (any input) ........................................................... ±20 rnA
Peak total input current (all inputs) ....................................................... ±30 rnA
Operating free-air temperature range, TA: TLC1549C ................................... O·C to 70·C
TLC15491 ................................. -40·C to 85·C
TLC1549M .............................. -55·C to 125·C
Storage temperature range, Tstg .................................................. -65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ............................ 260·C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other cond~ions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated cond~ions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to ground with REF- and GND wired together (unless otherwise noted).
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
4.5
5
5.5
Positive reference voltage, Vref + (see Note 2)
2.5
Differential reference voltage, Vref+ - Vref- (see Note 2)
Analog input voltage (see Note 2)
High-level control Input voltage, VIH
Low-level control input voltage, VIL
0
I VCC .. 4.5 Vt05.5 V
! VCC -4.5Vt05.5 V
Clock frequency at I/O CLOCK (see Note 3)
V
VCC+O.2
V
VCC
V
2
0
Setup time, CS low before first I/O CLOCK'!', isu(CS) (see Note 4)
VCC
V
V
VCC
0
Negative reference voltage, Vref- (see Note 2)
UNIT
V
0.8
V
2.1
MHz
1.425
0
J.1S
ns
Pulse duration, I/O CLOCK high, iwH(lIO)
190
ns
Pulse duration, I/O CLOCK low, iwL(IIO)
190
Hold time, CS low after last I/O CLOCKJ., th(CS)
Transition time, I/O CLOCK, tt(I/O) (see Nota 5 and Figure 5)
Transition time, CS, ttlCS)
TLCl549C
Operating free-air temperature, TA
0
ns
1
J.1S
10
J.1S
70
TLCl5491
-40
85
TLCl549M
-55
125
·C
NOTES: 2. Analog Input voltages greater than that applied to REF + convert as all ones (1111111111), while Input voltages less than that applied
to REF -convert as all zeros (0000000000). The TLCl549 is functional with reference voltages down to 1 V (Vref + - Vref-); however,
the electrical specifications are no longer applicable.
3. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (S 2 V) at least 1 1/0 CLOCK rising edge ~ 2 V) must occur within
9.5J.1S.
4. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the intemal system
clock after CSJ. before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup
time has elapsed.
5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with Input clock transition time as slow as 1 lIS for remote data-acquisition applications
where the sensor and the AID converter are placed several feet away from the controlling microprocessor.
-!/} TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAu.AS. TEXAS 75265
2-121
TLC1549C, TLC15491, TLC1549M
10-BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1996
electrical characteristics over recommended operating free-air temperature range,
Vee Vref+ 4.5 V to 5.5 V, I/O CLOCK frequency 2. t MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP't MAX
=
=
=
VCC =4.5 V,
IOH--1.6rnA
2.4
VCC = 4.5 V to 5.5 V,
IOH=-201lA
VCC-0.1
VOH
High-level output voltage
VOL
Low-level output voltage
IOZ
Off-state (hlgh-Impedance-state) output current
VO-VCC,
VO-O,
UNIT
V
VCC-4.5V,
'OL-1.6 mA
0.4
Vee - 4.5 V to 5.5 V,
IOL-20 IlA
CSatVee
0.1
CSatVcc
-10
10
V
IlA
IIH
High-level Input current
V,-Vee
0.005
2.5
IlL
Low-level input current
-0.005
-2.5
IlA
IlA
ICC
Operating supply current
V,=O
CSatOV
0.8
2.5
rnA
1
-1
IlA
10
IlA
V,. Vee
Analog input leakage current
VI-O
Maximum static analog reference
current into REF+
Ci
Input capaCitance
Vref+= VCC,
Vref_=GND
TLC1549C,1
(Analog)
During sample cycle
30
TLC1549M
(Analog)
During sample cycle
30
TLC1549C,I
(Control)
TLC1549M
(Control)
t All typical values are at VCC" 5 V, TA _ 25°C.
~1ExAs
2-122
INSTRUMENTS
POST OFFICE BOX 6S5303 • PALLAS. TEXAS 75265
5
5
55
15
pF
TLC1549C, TLC15491, TLC1549M
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C- DECEMBER 1992 - REVISED MARCH 1995
operating characteristics over recommended operating free-air temperature range,
Vee =Vref+ =4.5 V to 5.5 V, 1/0 CLOCK frequency =2.1 MHz
PARAMETER
EL
Linearity error (see Note 6)
EZS
Zero-scale error (see Note 7)
Full-scale error (see Note 7)
EFS
TEST CONDITIONS
MIN
Conversion time
UNIT
±1
LSB
See Note 2
±1
LSB
See Note 2
±1
LSB
±1
LSB
21
jJS
Total unadjusted error (see Note 8)
!conv
MAX
See Figures 6-10
Ie
Total cycle time (access, sample, and conversion)
See Figures 6-10,
See Note 9
21
+101/0
CLOCK
periods
jJS
tv
Valid time, DATA OUT remains valid after I/O CLOCK.!.
See Figure 5
!d(I/O-DATA)
tpZH,tpZL
Delay time, I/O CLOCK.!. to DATA OUT valid
See Figure 5
240
Enable time, CS.!. to DATA OUT (MSB driven)
See Figure 3
1.3
jJS
tpHZ, tpLZ
Disable time, csi to DATA OUT (high impedance)
See Figure 3
180
ns
tr(bus)
Rise time, data bus
See Figure 5
300
ns
tf(bus)
Fall time, data bus
See Figure 5
300
ns
!d(I/O-CS)
Delay time, tenth I/O CLOCK.!. to cs.!. to abort conversion
(see Note 10)
9
jJS
10
ns
ns
NOTES: 2. Analog Input voltages greater than that applied to REF + convert as all ones (1111111111 ), while inPut voltages less than that applied
to REF -convert as all zeros (0000000000). The TLC1549 is functional with reference voltages down to 1 V (Vref + - Vref-); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
7. Zero error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero, and full-scale errors.
9. I/O CLOCK period = 1/(1/0 CLOCK frequency). Sampling begins on the falling edge of the third I/O CLOCK, continues for seven
I/O CLOCK periods, and ends on the falling edge of the 10th I/O CLOCK (see Figure 5).
10. Any transitions of CS are recognized as valid only if the level is maintained for a minimum of a setup time plus two falling edges of
the internal clock (1.425 jJS) after the transition.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-123
TLC1549C, TLC15491, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION
Test Point
Vee
DATAOUT---'-'~~__- '
"'-.'OO"T
Figure 2. Load Circuit
CS
~~;:.:...
_ _2,.,V ~II
,".0.8 V
/!
tpZH. tpZL
.
k
~
1
tPHZ. tPLZ
I
DATA _ _--.;;2..;..4V;..cl"
\ 800/000/0
OUT
0.4 V \ _ _ _ _ _
, 1
Figure 3. DATA OUT to HI-Z Voltage Waveforms
~
CS
'\
!su(CS)
I/O CLOCK
0.8 V
~
____
2r
..
S',
.
14
1;-;;:-\ .
l
~I
r.:;\.1 ..
~ CI~~ ~ry-/
Ci;k ~
Figure 4. CS to I/O CLOCK Voltage Waveforms
-.J j+I
I
I
1/0 CLOCK
0.8 V
lcI(IIo-DATA)
I+-14
tv~
DATA OUT
2.4
tt(l/O)
0.8 V
O.BV
I/O CLOCK perlod--J
~I
1
vi j. 2.4 V
____~0~.4~V~~~_0~.4~V~-----------
I I
I+-
~
tr(bus). tf(bus)
Figure 5. I/O CLOCK and DATA OUT Voltage Waveforms
~1EXAS .
2-124
!ti(CS)
INSTRUM,ENTS
POST OFFICE BOX E!55303 • DALLAS. T~ 75265
TLC1549C, TLC15491, TLC1549M
1O-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995
(,
1-------------------------..1
'f---
CSl
(see Note A)
1
1
1/0
CLOCK
1
1
~--"""T"i~
DATA
OUT
I
AID
- - - - - - - - . - Conversion ---+1
Interval
(S 21 JlS) Initialize
Figure 6. Timing for 10-Clock Transfer Using CS
_~ Must Be High on Power Up
CS
(see Note A)
I
'1-
j
------------------------------;,,----
I
1/0
J . . - -_ _
CLOCK-h
I
-----....
See Note C
DATA~ A9
Low Level
OUTN
- - - - - - - - . _ AID Conversion
lOll
I
I
---;~
MSB
Interval
(S 21 JlS)
-tI
~
I
Initialize
Initialize
Figure 7. Timing for 10-Clock Transfer Not Using CS
SeeNoteB
CSI
111111111
(see Note A)r
1/0
I
1
1
[1~
CLOCK
Low
DATA
OUT
AD
1
"1,....-
l0III10lIl------- Previous Conversion Data
Level
I
-'-------~~140111-
1 MSB
Initialize
LSB
1
1
HI.Z~
1"'7'~"""T"i~
AID
1
Conversion ...,.I
Interval
1
(S 21 JlS) Initialize
Figure 8. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed Within 21 J.IS)
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CSJ. before responding to the 1/0 CLOCK. No attempt should be made to clock out the data until the minimum ~ setup
time has elapsed.
B. A low-to-high transition of CS disables 1/0 CLOCK within a maximum of a setup time plus two falling edges of the internal system
clock.
C. The first 1/0 CLOCK must occur after the end of the previous conversion.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
2-125
TLC1549C, TLC15491, TLC1549M
1D-BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
-r.=
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995
CS
(see Note A)
(
I/O
-h
CLOCK
Must Be High on POW.er Up
"
j
I
~r---YL
See Note C
I
~
DATA
A9
OUTN
I
14
Low Level
I
Previous Conversion Oats - - - - - - L S - B.......
~ ..
f--
I MSB
Initialize
AID Conversion
Intsrval
(S 21 j1II)
ra;v
~
I
---+1
Initialize
Figure 9. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed Within 21 J.LS)
11111111 Sr--,L...~
(seeNots~ I
I
I
I
1/0
CLOCK ___--'
11
I
'.fBL~f-'1--'
pm. m
1
l-
See Note
I
I
I
DATA
OUT
AO
I
I
MSB
Low
Level
I
I . HI·ZStsts ~
~
I
I
Previous Conversion Oats - - - - - - - L S - B......
·I+ AID -.I
Conversion
Intsrval
(S 21 j1II)
Initialize
I
I
I
Initialize
Figure 10. Timing for 11· to 16-Clock Transfer. Using CS (Serial Transfer Completed After 21 J.LS)
_~ Must Be High on Power Up
CS
(see Nots A)
I/O
(
"
~r--f1II
j
I
CLOCK~
See Nots B
I
See Nots C
DATAJr A9
OUT~
14j
..- M S - B - - - - -
I
A/D Conversion Interval
(S 21 j1II)
j
Initialize
Figure 11. Timing for 16-Clock Transfer Not USing CS (Serial Transfer Completed After 21 J.LS)
NOTES: A. To minimize errors caused by noise at CS. the intemal circuitry waits for a set up time plus two falling edges of the internal system
clock after CS.!. before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup
time has elapsed.
B. A low-ta-high transition of CS disables I/O CLOCK within a maximum of a setup time plus two falling edges of the intemal system
clock.
C. The first I/O CLOCK must occur after the end of the previous ·conversion.
~TEXAS
2-126
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC1549C, TLC15491, TLC1549M
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995
APPLICATION INFORMATION
1111111111
I
I
See Nolee A and B
./
1111111110
1111111101
~
••
•
A:
1000000001
::I
/'
0111111111
/
••
•
Vzs
l
0000000010
0000000001
0000000000
~
VZT =Vzs + 1/2 LSB
0
~
~ I(J \
)~V II I
\
VFS
1 1000000000
!
t:::
V
~
/'
/!
VFT = VFS -1/2 LSB
V
I~ lLr/" "
~
I
o
0.0048 0.0096
•••
o
2.4528
2.4576
2.4624
•••
f
Ii
•••
2
I
o
I
I
IIV~V
••
•
511
I
I
/'
1021
512
Ii
c,J::::V
1022
513
I
I
V
1023
4.905614.9104 4.9152
~
VI - Analog Input Voltage - V
NOTES: A. This curve Is based on the assumption that Vref + and Vref- have been adjusted so that the voltage at the transition from digital 0
to 1 (Vzr) is 0.0024 V and the transition to full scale (VFT) is 4.908 V. 1 LSB =4.8 mV.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.
Figure 12. Ideal Conversion Characteristics
TLC1549
Analog Input
cs
ANALOG IN
I/O CLOCK
Processor
Control
Circuit
DATA OUT
5-V DC Reguletad
REF+
~ REFGND
To Source
Ground
l
Figure 13. typical Serial Interface
~TEXAS
INSTRUMENTS
POST OFFICE eox 656303 • DAllAS. TEXAS 75265
2-127
TLC1~~49C,
TLC15491, TLC1549M
1O-BIT ANALOG-TO-orGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C- DECEMBER 1992- REVISED MARCH 1995
APPLICATION INFORMATION
simplified analog Input analysis
Using the equivalent circuit in Figure 14, the time required to charge the analog input capacitance from 0 V to
Vs within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
V C == V
s( 1-e-tc/RtCi)
(1 )
. where
Rt=Rs+rj
The final voltage to 1/2 LSB is given by
Vc (1/2 LSB) = Vs - (Vs/2048)
(2)
Equating equation 1 to equation 2 and solving for time to gives
V S - (VS/2048) == V S(1-e-tc/RtCi)
(3)
to (112 LSB) = Rt x Cj x In(2048)
(4)
and
Therefore, with the values given the time for the analog input ~ignal to settle is
tc (1/2 LSB) = (Rs + 1 kO) x 60 pF x In(2048)
(5)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet •
Rs
I
I
I
I
VI
~ TLC1549
rl
VS~VC
!
1 knMAX
·1
I
.-l
I'
rh
CI
50pFMAX
=
=
=
VI Input Voltage at ANALOG IN
Vs =External Driving Source Voltage
Rs Source Resistance
I'J Input Resistance
CI =Input CapaCitance
t Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.
Figure 14. Equivalent Input Circuit Including the Driving Source
~1ExAs .
2-128
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS, TEXAS 75265
TLC15501, TLC1550M, TLC1551I
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
Jt OR NW PACKAGE
• Power Dissipation •.• 40 mW Max
• Advanced llnEPICTM Single-Poly Process
Provides Close Capacitor Matching for
Better Accuracy
(TOP VIEW)
RD
WR
CLKIN
CS
09
08
07
06
05
04
03
02
REF+
REFANLGGNO
AIN
ANLGVDD
OGTLGN01
OGTLGN02
OGTL VDDI
OGTL VDD2
EOC
• Fast Parallel Processing for DSP and !1P
Interface
• Either External or Internal Clock Can Be
Used
• Conversion Time ••• 6 IJS
• Total Unadjusted Error. •• ±1 lSB Max
• CMOS Technology
DO
description
01
The TlC1550x and TlC1551 are data acquisition
analog-to-digital converters (AOCs) using a 10-bit,
switched-capacitor,
successive-approximation
network. A high-speed, 3-state parallel port directly
interfaces to a digital signal processor (OSP) or
microprocessor (~P) system data bus. 00 through
09 are the digital output terminals with 00 being the
least significant bit (lSB). Separate power
terminals for the analog and digital portions
minimize noise pickup in the supply leads.
Additionally, the digital power is divided into two
· parts to separate the lower current logic from the
higher current bus drivers. An external clock can be
. applied to ClKIN to override the internal system
clock if desired.
The TlC15501 and TlC1551I are characterized for
operation from -40°C to 85°C. The TlC1550M is
characterized over the full military range of -55°C
to 125°C.
t Refer to the mechanical data for the JW package.
FK OR FN PACKAGE
(TOP VIEW)
C
Z
(!l
(!ll
+
~
z 0lclg; :x::
«a:a:za:;>O
...JLLLL
W W
AIN
ANLGVDD
OGTLGN01
NC
OGTLGN02
OGTLVDDI
OGTL VDD2
...J
4 3 2 1 28 2726
25
5
24
6
23
7
22
8
21
9
10
20
11
19
12 1314 15 16 1718
09
08
NC
07
06
05
0 0 ~ ON'" "-----
-+I!r~2y~_ _ _ _ __
.
TLC2543C, TLC25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079A-
• 12~Bit-Resolution AID Converter
• 1()"~ Conversion Time Over Operating
Temperature
• 11 Analog Input Channels
• 3 Built-In Self-Test Modes
• Inherent Sample and Hold
• Linearity Error ... ± 1 LSB Max
• On-Chip System Clock
• End-of-Conversion (EOC) Output
• Unipolar or Bipolar Output Operation
(Signed Binary With Respect to 1/2 the
Applied Voltage Reference)
• Programmable MSB or LSB First
• Programmable Power Down
• Programmable Output Data Length
• CMOS Technology
• Application Report Avallablet
ow OR N PACKAGE
DB,
(TOP VIEW)
AINO
VCC
EOC
1
AIN1
AIN2
I/O CLOCK
AIN3
DATA INPUT
4
AIN4
DATA OUT
AIN5
CS
AIN6
7
14
AIN7
8
13
REF+
REF-
AIN8
9
12
AIN10
GND
10
11
AIN9
FN PACKAGE
(TOP VIEW)
C\I .....
000
3 2
1 2019
18
~ ~ ~ 00
«««:::;ow
desCription
The TLC2543C and TLC25431 are 12-bit,
switched-capacitor, successive-approximation,
analog-to-digital converters. Each device has
three control inputs [chip select (CS), the
input-output clock (I/O CLOCK), and the address
input (DATA INPUT)] and is designed for
communication with the serial port of a host
processor or peripheral through a serial 3-state
output. The device allows high-speed data
transfers from the host.
AIN3
4
AIN4
5
17
I/O CLOCK
AIN5
6
16
DATA OUT
AIN6
7
15
AIN7
8
14
9 10 11 1213
CS
REF+
DATA INPUT
In addition to the high-speed converter and versatile control capability, the device has an on-Chip 14-channel
multiplexer that can select anyone of 11 inputs or anyone of three internal self-test voltages. The
sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high
to indicate that conversion is complete. The converter incorporated in the device features differential
high-impedance reference inputs that facilitate ratio metric conversion, scaling, and isolation of analog circuitry
from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating
temperature range.
The TLC2543 is available in the DB, OW, FN, and N packages. The TLC2543C is characterized for operation
from O°C to 70°C, and the TLC25431 is characterized for operation from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
O·Cto 70·C
TLC2543CDB
-40·C to 85·C
TLC25431DB
PLASTIC CHIP CARRIER
(OW)
(OB)*
I
I
(FN)
PLASTIC DIP
(N)
TLC2543CDW
TLC2543CFN
TLC2543CN
TLC25431DW
TLC25431FN
TLC2543IN
* Available in tape and reel and ordered as the TLC2543CDBR or TLC2543IDBR.
t
Microcontroller Based Data Acquisition Using the TLC2543 12-bit Serial-Out ADC (SLAA012)
Copyright © 1994. Texas Instruments Incorporated
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-137
TLC2543C, TLC25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079A- DECEMBER 1993 - REVISED DECEMBER 1994
functional block diagram
AINO
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
1 .
2
--'--
"3
"4
5
6
r8
9
11
Sample.and
Hold
-"
14-Channel
Analog
Multiplexer
12
-==-
REF+
REF-
141
131
12-Blt
Analog-to-Dlgltal
Converter
(switched capacitors)
12
~
~
Input Address
Reglstar
~
Output
Data
Reglstar
I
12-to-1 Data
SelectOr and
Driver
r-1!
DATA
OUT
4
3
~
DATA
INPUT
110 CLOCK
CS
Salf-Test
Referenca
I
-
Control Logic
and 110
Counters
,J!. EOC
17
+
18
15
~1ExAs
2-:138
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS, TEXAS 75265
I
•
TLC2543C, TLC25431
12-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079A- DECEMBER 1993 - REVISED DECEMBER 1994
Terminal Functions
TERMINAL
UO
DESCRIPTION
1-9,
11,12
I
These 11 analog-signal inputs are intemally multiplexed. The driving source impedance should be less than
or equal to 50 n for 4.1-MHz 110 CLOCK operation and capable of slewing the analog input voltage into a
capaCitance of 60 pF.
CS
15
I
Chip select. A high-ta-Iow transition on OS resets the intemal counters and controls and enables DATA OUT,
DATA INPUT, and 110 CLOCK. A low-ta-high transition disables DATA INPUT and 110 CLOCK within a setup
DATA INPUT
17
I
Seriai-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted next.
The serial data is presented with the MSB first and is shifted in on the first four rising edges of 110 CLOCK.
After the four address bits are read into the address register, 110 CLOCK clocks the remaining bits in order.
DATA OUT
16
a
The 3-state serial output for the AID conversion resull DATA OUT is in the high-impedance state when CS
is high and active when OS is low. With a valid OS, DATA OUT is removed from the high-impedance state and
is driven to the logic level corresponding to the MSB/LSB value of the previous conversion result. The next
falling edge of 110 CLOCK drives DATA OUT to the logic level corresponding to the next MSB/LSB, and the
remaining bits are shifted out in order.
EOC
19
a
End of conversion goes from a high to a low logic level after the falling edge of the last 110 CLOCK and remains
low until the conversion is complete and data are ready for transfer.
GND
10
110 CLOCK
18
I
Input/output clock. 110 CLOCK receives the serial input and perfonns the following four functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges 110 CLOCK
with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of 110 CLOCK, the analog input voitage on the selected multiplexer input
begins charging the capacitor array and continues to do so until the last falling edge of 110
CLOCK.
3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on
the falling edge of 110 CLOCK.
4. It transfers control of the conversion to the intemal state controller on the falling edge of the last
110 CLOCK.
REF+
14
I
The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range is
determined by the difference between the voltage applied to this terminal and the voltage applied to th,e REFterminal.
REF-
13
I
The lower reference voltage value (nominally ground) is applied to REF-.
VCC
20
NAME
NO.
AINO-AIN1O
time.
The ground retum terminal for the intemal circuitry. Unless otherwise noted, all voltage measurements are
with respect to GND.
ot
Positive supply voltage
detailed description
Initially, with chip select (CS) high, 1/0 CLOCK and DATA INPUT are disabled and DATA OUT is in the
high-impedance state. CS, going low, begins the conversion sequence by enabling 1/0 CLOCK ,and DATA
INPUT and removes DATA OUT from the high-impedance state.
The input data is an 8-bit data stream consisting of a 4-bit analog channel address (07 -04), a 2-bit data length
select (03-02), an output MSB or LSB first bit (01), and a unipolar or bipolar output select bit (DO) that are
applied to DATA INPUT. The 1/0 CLOCK sequence applied to the 1/0 CLOCK terminal transfers this data to the
input data register.
During this transfer, the 1/0 CLOCK sequence also shifts the previous conversion result from the output data
register to DATA OUT. 1/0 CLOCK receives the input sequence of 8, 12, or 16 clocks long depending on the
data-length selection in the input data register. Sampling of the analog input begins on the fourth falling edge
of the input 1/0 CLOCK sequence and is held after the last falling edge of the 1/0 CLOCK sequence. The last
falling edge of the 1/0 CLOCK sequence also takes EOC low and begins the conversion.
~1EXAS
INSTRUMENTS
POST OFFICE BOX B55303 • DAllAS. TEXAS 75266
2-139
-TLC2543C, TLC25431
12·81T ANALOG·TO·DIGITAL ,CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079A- DECEMBER 1993- REVISED DECEMBER 1994
converter operation
The operation of the converter is organized as a succession of two distinct cycles: 1) the 1/0 cycle and 2) the
actual conversion cycle. The 1/0 cycle is defined by the externally provided 1/0 CLOCK and lasts 8, 12, or 16
clock periods, depending on the selected output data length.
1. 1/0 cycle
During the 1/0 cycle, two operations take place simultaneously.
a. An 8-bit data stream consisting of address and control information is provided to DATA INPUT. This data
is shifted into the device on the rising edge of the first eight 1/0 CLOCKs. DATA INPUT is ignored after
the first eight clocks during 12 or 16 clock 1/0 transfers.
b. The data output, with a length of 8, 12, or 16 bits, is provided serially on DATA OUT. If CS is held low, the
first output data bit occurs on the rising edge of EOC. If CS is negated between conversions, the first
output data bit occurs on the falling edge of CS. This data is the result of the previous conversion period,
and after the first output data bit, each succeeding bit is clocked out on the falling edge of each
succeeding 1/0 CLOCK.
2. Conversion cycle
The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to
1/0 CLOCK. During the conversion period, the device performs a successive-approximation conversion on
the analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when
conversion is complete and the output data register is latched. A conversion cycle is started only after the 1/0
cycle is completed, which minimizes the influence of external digital noise on the accuracy ofthe conversion.
power up and Initialization
After power up, CS must be taken from high to low to begin an 1/0 cycle. EOC is initially high, and the input data
register is set to all zeroes. The contents of the output data register are random, and the first conversion result
should be ignored. To initialize during operation, CS is taken high and returned low to begin the next 1/0 cycle.
The first conversion after the device has returned from the power-down state may not read accurately due to
internal device settling.
operational terminology
Current (N) 1/0 cycle
The entire 1/0 CLOCK sequence that transfers address and control data into the data register and clocks
the digital result from the previous conversion from DATA OUT
Current (N) conversion cycle
The conversion cycle starts immediately after the current 1/0 cycle. The end of the current 1/0 cycle is the
last clock falling edge in the 1/0 CLOCK sequence. The current conversion result is loaded into the output
register when conversion is complete.
Current (N) conversion result
The current conversion result is serially shifted out on the next 1/0 cycle.
Previous (N -1) conversion cycle
The conversion cycle just prior to the current 1/0 cycle
Next (N + 1) 1/0 cycle
The 1/0 period that follows the current conversion cycle
Example: In the 12-bit mode, the result of the current conversion cycle is a 12-bit serial-I4I..l---------..~1
Initialize
AID Conversion
Interval
Figure 15. Timing for 16-Clock Transfer Not Using CS With MSB First
NOTE A: To minimize errors caused by noise at CS,the intemal circuitry waits fora setup time afierCSJ, before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-153
-TLC2543C, TLC25431
12-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079A- DECEMBER 1993 - REVISED DECEMBER 1994
APPLICATION INFORMATION
111111111111
sJ Notes A ~nd B
VFS
111111111110
111111111101
)~
••
•
lA;:
~ 100000000001
~
'5
!o 100000000000
!.S!'
VZT =VZS + 1/2 LSB
/
011111111111
Q
••
•
r--VZS
000000000010
000000000001
000000000000
/
/ I~ A/"
II ~V
/~
/'
0.0012 0.0024
:; ~V;
~~
,/
V
4093
VI
••
•
L~B
2049
Ii
,/
4094
FSnom
I
I
~V
4095
I.!
VFT =VFS -1/2
2047
I
I
/' . /
~V
o I
~
••
•
2
II
I
•••
2.4564
o
2.4576
2.4588
•••
VI - Analog Input Voltage - V
I
,
o
4.9128! 4.9140 4.9152
NOTES: A. This curve is based on the assumption that Vref+ and Vref- hav~ been adjusted so that the voltage at the transition from digital 0
to 1 (VZT) is 0.0006 V and the transition to full scale (VFT) is 4.9134 V. 1 LSB - 1.2 mY.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.
Figure 16. Ideal Conversion Characteristics
TLC2543
1
2
Analog
Inputs
AINO
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
3
4
5
6
7
8
9
11
AIN9
12
AIN10
15
CS
18
1/0 CLOCK
17
DATA INPUT
Proceesor
DATA OUT
EOC
16
19
14
REF+ ~ S-V DC Regulated
REF-
r14-
GND
110
To Source ,
Ground
"
I
1.
Figure 17. Serial Interface
~TEXAS
2-154
Control
Circuit
INSTRUMENTS
POST OFFICE BOX S55303 • DALLAS. TEXAS 752S5
TLC2543C, TLC25431
12-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079A- DECEMBER 1993 - REVISED DECEMBER 1994
APPLICATIONS INFORMATION
simplified analog Input analysis
Using the equivalent circuit in Figure 18, the time required to charge the analog input capacitance from 0 to Vs
within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
(1 )
where
Rt= Rs Hj
The final voltage to 1/2 LSB is given by
Vc (1/2 LSB) = Vs - (Vs/8192)
(2)
Equating equation 1 to equation 2 and solving for time tc gives
Vs - (V S /58192) = Vs(1-e-tc/RtCi)
(3)
to (1/2 LSB) = Rt x Cj x In(8192)
(4)
and
Therefore, with the values given the time for the analog input signal to settle is
tc (1/2 LSB) = (Rs + 1 kn) x 60 pF x In(8192)
(5)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet 4
Rs
I
I
I
I
VI
~ TLC2543
fJ
VS~VC
I 1 kOMAX
II
150
CI
PFMAX
VI = Input Voltage at AIN
VS= External Driving Source Voltage
Ra = Source Resistance
rl = Input Resistance
CI = Input capacitance
t Driving source requirements:
• NOise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.
Figure 18. Equivalent Input Circuit Including the Driving Source
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAu.AS. TEXAS 75265
2-155
-
2-156
TLC5510
8-81T HIGH·SPEED ANALOG·TO·DIGITAL CONVERTER
""'''T''''''A'''A 1994 - REVISED FEBRUARY 1995
NSPACKAGEt
(TOP VIEW)
• 8-Blt Resolution
• Linearity Error
±0.75 LSB Max (25°C)
±1 LSB Max (-20°C to 75°C)
OE 1
OGNO
01 (lSB)
02
03
04
05
06
07 9
08(MSB}
VOOO 11
elK
• Differential Linearity Error
±0.5 LSB (25°C)
±0.75 LSB Max (-20°C to 75°C)
• Maximum Conversion Rate
20 Mega-Samples per Second
(MSPS) Min
• SOV Single-Supply Operation
• Low Power Consumption ••• 90 mW Typ
• Interchangeable With Sony CXD1175
t Available in tape and reel only and
applications
•
•
•
•
OGNO
REFB
REFBS
AGNO
AGNO
ANALOG IN
VOOA
REFT
REFTS
VOOA
VOOA
VOOO
ordered as the TLC551 OINSLE.
Digital TV
Medical Imaging
Video Conferenclng
High-Speed Data Conversion
AVAILABLE OPTIONS
NSPACKAGE
(TAPE AND REEL ONLy)
TA
-200C to 75°C
TLC5510INSLE
• QAM Demodulators
description
The TLC5510 is a CMOS, 8-bit, 20 MSPS analog-to-digital converter (ADC) that utilizes a semiflash
architecture. The TLC551 0 operates with a single 5 V supply and consumes only 100 mW of power typically.
Also included is an internal sample and hold circuit, parallel outputs with high impedance mode, and internal
reference resistors.
The semiflash architecture reduces power consumption and die size compared to flash converters. By
implementing the conversion in a 2-step process, the number of comparators is significantly reduced. The
latency of the data upon conversion is 2.5 clocks.
The internal reference resistors can create a standard, 2-V, full-scale conversion range using VOOA. Only
external jumpers are required to implement this option. This reduces the need for external references or
reSistors. Differential linearity is 0.5 LSB at 25°C and a maximum of 0.75 LSB over the full operating temperature
range. Dynamic characteristics are specified with a differential gain of 1% and differential phase of 0.7%.
The TLC551 0 is characterized for operation from -20°C to 75°C.
~1ExAs
copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS, TEXAS 75265
2-157
TLC5510
8·BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTER
SLAS095B - SEPTEMBER 1994 - REVISED FEBRUARY 1995
functional block diagram
Resistor
R~~n~~------------------~
Divider
REFB
2700
NOM
I---I--I-..r-:--::--,
Lower Sampling
REFT
D1(LSB)
.----+--+1... Comparators
REFBS
(4-Blt)
D2
Lower Data
Latch
800
NOM
D3
AGND
D4
...--t.....
AGND
Lower Sampling
Comparators
(4-BIt)
D5
VDDA
3200
NOM
REFTS
ANALOG IN
-====~~.J-~
D6
Upper Data
Latch
Upper Sampling
Comparstors
(4-Blt)
D7
D8(MSB)
CLK
schematics of inputs and outputs
EQUIVALENT OF ANALOG INPUT
EQUIVALENT OF EACH DIGITAL INPUT
VDDA
ANALOG IN
VDDD
OE,CLK
EQUIVALENT OF EACH DIGITAL OUTPUT
VDDD
D1-D8
DGND
:lllExAs .
2-158
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC5510
8-81T HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS095B - SEPTEMBER 1994 - REVISED FEBRUARY 1995
Terminal Functions
TERMINAL
NO.
NAME
AGNO
ANALOG IN
DESCRIPTION
I/O
20,21
Analog ground
19
I
Analog Input
ClK
OGNO
12
2,24
I
Clock in
Oigital ground
01-08
3-10
0
Oigital data out. 01 :lSB, 08:MSB
I
Output enable. When OE z l, data is enabled. When OE - H, 01-08 is in high Impedance state.
OE
1
VOOA
14,15,18
VOOO
REFB
11,13
AnalogVoO
23
22
I
REFT
17
I
REFTS
16
REFBS
OigitalVOO
Reference voltage in (bottom)
Reference voltage (bottom). When using the intemal voltaga divider to generate a nominal2-V reference,
this terminal is shorted to the REFB terminal (see Figure 2).
Reference voltage in (top)
Reference voltage (top). When using the intemal voltage divider to generate a nominal2-V reference, this
terminal is shorted to the REFT terminal (see Figure 2).
absolute maximum ratlngst
Supply voltage. VOOA. Vooo ...••.•••.•...•...•.....•.•..........................•.•......•.. 7 V
Reference voltage input range. Vref(T). Vref(B). Vref(BS). Vref(TS) ....................... AGND to VOOA
Analog input voltage range. VI(ANLG) ....•............•..•..........•.............•. AGND to VOOA
Digital input voltage range. VI(DGTL) ....•.. , ...................•.................... DGND to Vooo
Digital output voltage range. VO(OGTL) •.•.•.••.....•...••..•...•...........•....... DGND to Vooo
Operating free-air temperature range. TA •..•.....•...•................•......•.....• -20°C to 75°C
Storage temperature range. Tstg .................................................. -55°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
VOOA-AGNO
VOOO-AGNO
AGNO-OGNO
Supply voltage
Reference input voltage (top), Vrefm
MIN
NOM
MAX
UNIT
4.75
4.75
5
5
5.25
5.25
V
0
100
mV
2.7
V
-100
Vref(BJ+2
0
Reference input voltaga (bottom), Vref(B)
Analog input voltage range, VI(ANlGI (see Note 1)
High-level input voltage, VIH
Vref(B)
4
low-level input voltage, Vil
VrefLat+2
0.6
Vrefm-2
V
Vretm
V
V
1
V
Pulse duration, clock high, tw(HI
25
ns
Pulse duration, clock low, tw(ll
25
ns
NOTE 1: REFT - REFS ~ 2.4 V maximum
~TEXAS
INSTRUMENTS
POST OFFICE BOX 865303 • OALlAS. TEXAS 75265
2-159
TLC5510
8-81T HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS096B - SEPTEMBER 1994 - REVISEO FEBRUARY 1995
=
=
=
=
electrical characteristics atVDD 5 V, Vref(T) 2.5 V, Vref(B)::: 0.5 V, fconv 20 MSPS, TA 25°C (unless
otherwise noted)
.
PARAMETER
El
Unearityerror
ED
linearity error, differential
TEST CONDITIONst
fconv - 20 MSPS,
VI- 0.5 Vt02.5 V
MIN
TA-25'C
TA" -20"C to 75'C
±0.3
±0.5
0.61
2.02
±0.75
0.65
2.15
2.29
2.4
5.2
7.5
10.5
190
270
16
350
-18
-43
-66
-20
0
20
TA-25'C
TA = -20'C to 75'C
Self bias (1)
Self bias (2)
Short REFB to REFBS;
Short REFT to REFTS
0.57
1.9
Self bias (3)
Short REFB to AGNO,
Short REFT to REFTS
2.18
lref
Reference voltage current
Rref
CI
Reference voltage resistor
• Analog input capacitance
Vrefm - Vref(B) .. 2 V
Between REFT and REFB terminals
EZS
EFS
Zero-scale error
Full-scale error
IIH
High-level input current
low-level input current
III
IOH
VI(ANlGl - 1.5 V + 0.07 Vnns
Vref = REFT - REFB - 2 V
VOO-MAX,
VOO=MAX,
OE-GNO,
OE .. GNO,
TYP MAX
±0.4 ±0.75
±1
VIH-VOO
5
5
VOL" 0.4 V
-1.5
IOl
High-level output current
Low-level output current
IOZH
High-level high-impedancestate output leakage current OE.VOO,
VOO"MAX
VOH-VOO
16
IOZl
Low-level high-impedancestate output leakage current C5E"Voo,
VOO-MIN
VOl"OV
16
100
Supply current
National Television System
Committee (NTSC) ramp wave Input
f s ·20MSPS,
V
rnA
n
mV
IIA
rnA
2.5
IIA
.. marked MIN or MAX are as stated In recommended operating conditions.
t Conditions
2-160
LSB
pF
Vll"OV
VOO = MIN,
VOO-MIN,
VOH .. VOO-0.5 V
UNIT
:lfThXAs
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
16
27
rnA
TLC5510
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS095B - SEPTEMBER 1994 - REVISED FEBRUARY 1995
operating characteristics at VDD
otherwise noted)
=5 V, VRT =2.5 V, VRB =0.5 V, f8 =20 MSPS, TA =25°C (unless
PARAMETER
TEST CONDITIONS
MIN
Maximum conversion rate
VICANlGl = 0.5 V - 2.5 V,
BW
Analog input bandwidth,
At-I dB
14
tctd
Digital output delay time
Cl S; 10 pF (see Note 2)
18
Differential gain
MAX
20
UNIT
MSPS
MHz
30
ns
1%
NTSC 40 Institute of Radio Engineers (IRE)
modulation wave,
fconv = 14.3 MSPS
Differential phase
tAJ
fl = I-kHz ramp wave form
TYP
fconv
Aperture jitter time
Sampling delay time
tctJ§l
NOTE 2: Cl includes probe and jig capacitance
0.7
degrees
30
ps
4
ns
ClK(Clock)
ANALOG IN
(Input Signal)
01-08
(Output Data)
I
I
~
N+l
IN
I
N-3
I
~
N-2
X~~__~J)(~~__
N-l
N __
rJ)(~~_N_+_l~__
tctd~
Figure 1.1/0 Timing Diagram
~TEXAS
INSTRUMENTS
POST OFFICE BOX 666303 • DAUAS. TEXAS 75265
2-161
TLC5510
8·BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTER
SLAS095B - SEPTEMBER 1994 - REVISED FEBRUARY 1995
APPLICATION INFORMATION
The following notes are design recommendations that shou'ld be used with the TLC5510.
•
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
•
RF breadboarding or printed-circuit-board (PCB) techniques should be used throughout the evaluation and
production process. Breadboards should be copper clad for bench evaluation.
•
Since AGNO and OGNO are not connected internally, these terminals need to be connected externally. With
breadboards, these ground lines should be connected through separate leads with correct supply
bypassing. A good method to use is separate twisted-pair cables for the supply lines to minimize noise
pickup. An analog and digital ground plane should be used on PCB layouts.
•
VOOA to AGNO and VOOO to OGNO should be decoupled with 1-¢= and O.Q1-¢= capacitors, respectively,
and placed as close as possible to the affected device.terminals. A ceramic-chip capacitor is recommended
for the O.01-~F capacitor. Care should be exercised to ensure a solid noise-free ground connection for the
analog and digital grounds.
•
VOOA, AGNO, and ANALOG IN terminals should be shielded from the higher frequency terminals, CLK and
00-07. When possible, AGNO traces should be placed on both sides ofthe ANALOG IN traces on the PCB
for shielding.
•
In testing or application of the device, the resistance of the driving source connected to the analog input
should be 10 0 or less within the analog frequency range of interest.
~1ExAs
2-162
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TLC5510
8·BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTER
SLAS095B - SEPTEMBER 1994 - REVISED FEBRUARY 1995
APPLICATION INFORMATrON
DVDD
5V
II
C11~
TLC551 0
. AVDD
5V
13
VREF
ADJ
~
FB3
b
R5 •
1
Video J.....
,
Input
?/1
---.;
-
FB7
JP1 JP2
R4
~
~C7
R2
16
17
-
~~
D3~~
•...,... ..:~~
r-
18
/I
C8
;:::r: C5
D2 .. ~
TP30
15
~
FB1
C1\1
II
C2;::: :::
~
~C8
FB2
R3
D1~~
R1
14
TP1 ;::: :::C3
Q1
1\
-
19
20
21
C4
JP3 JP4
22
I1T
C10
23
24
VDDD
CLK
VDDA
VDDD
VDDA
D8(MSB)
...- Clock
12
11
10
REFTS
D7 9
REFT
D6 8
VDDA
D5 7
ANALOG IN
D4 6
AGND
D3 5
AGND
D2 4
REFBS D1 (LSB) 3
REFB
DGND 2
DGND
OE 1
II
~~1
~
..
~
..,- Output
"
Enable
fj7
LOCATION
C1,C3-C4,
C6-C12
DESCRIPTION
0.1-1lf Capacitor
C2
1O-pF Capacitor
C5
47-Ilf CaPacitor
FB1,FB2,FB3,FB7
Q1
Ferrite Bead
2N3414 or equivalent
R1,R3
75-0 resistor
R2
500..(.1 resistor
R4
10-k0 resistor, clamp voltage adjust
R5
300..(.1 resistor, reference-voltage fine adjust
Figure 2. Application and Test Schematic
NOTE A: JP1, JP2, JP3, and JP4 allow adjustment of the reference voltage by R5 using temperature-compensating diodes 02, 03.
~TEXAS .
INSTRUMENTS
POST OFFICE SOX 656303 • DALLAS. TEXAS 75265
2-163
TLC5510
s;.BIT HIGH-SPEED ANALOG-TO~DIGITAL CONVERTER
SLAS095B - SEPTEMBER 1994 - REVISED FEBRUARY 1995
PRINCIPLES OF OPERATION
functional description
The TlC551 0 is a semiflash ADC featuring two lower comparator blocks of four bits each.
As shown in Figure 3, input voltage VI(1) is sampled with the falling edge of ClK1 to the upper comparators block
and the lower comparators block(A), 8(1). The upper comparators block finalizes the upper data UD(1) with the
rising edge of ClK2, and simultaneously, the lower reference voltage generates the voltage RV(1) .
corresponding to the upper data. The lower comparators block (A) finalizes the lower data lD(1) with the rising
edge of ClK3. UD(1) and lD(1) are combined and output as OUT(1) with the rising edge of ClK4. According
to the above internal operation described, output data is delayed 2.5 clocks from the analog input voltage
sampling point.
Input voltage VI(2) is sampled with the falling edge of ClK2. UD(2) is finalized with the rising edge of ClK3, and
lD(2) is finalized with the rising edge of ClK4 at the lower comparators block(B). OUT(2) is output with the rising
edge of ClK5.
ANALOG IN
(Sampling Points)
CLK (Clock)
Upper Comparators Block
Upper Data
=*
I
I
Lower Reference Voltage
=x
U+O)
I
Lower Data (A)
U+l)
1
1
I
I
I
U+)
RV(2)
)K
RV(3)
I
I
I
I
I
I
I
I I
8(1)
:JK
+)
C(l)
LO~-l)
8(3)
*
::::x
.OUT(-2)
)IC:
C(3)
L~(l)
I
I
I
I
X
LO(O)
~
I
I
I
I
I
I
X
I
I
I
~
+i~l~i +icool~~1
I
: LO(-2)
t:
I I I +) I I
OUT(-1)
X
OUT(O)·
X
Figure 3. Internal Functional Timing Diagram
~TEXAS
2-164
I
)K
I
01-08 (Data Output)
U+3)
RV(l)
I
Lower Data (B)
I
I
)K
I
Lower Comparators Block (B)
I
RV(O)
I
Lower Comparators Block (A)
* * *
INSTRUMENTS
POST OFFICE BOX e55303 • DALLAS, TEXAS 75265
I
I
HI~
I
,
LO(2)
I
I
OUT(1)
x::
-TLC5510
8-BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTER
SLAS095B - SEPTEMBER 1994 - REVISED FEBRUARY 1995
PRINCIPLES OF OPERATION
Internal referencing
Three internal resistors are provided so that the device can generate an internal reference voltage. These
resistors are brought out on terminals VOOA, REFTS, REFT, REFB, REFBS, and AGND.
To use the internally generated reference voltage, terminal connections should be made as shown in Figure 4.
This connection provides the standard video 2-V reference for the nominal digital output.
TLC551 0
18
VDDA
(Analog Supply)
R1
320 n NOM
RE FTS
I
16
17
REFT
REFB
23
I
22
RE FBS
AGND
Rre,
270 n NOM
~
•
R2
son NOM
21
..1
Figure 4. External Connections for Using the Internal· Reference Resistor Divider
functional operation
The TLC551 0 functions as shown in Table 1.
Table 1. Functional Operation
INPUT SIGNAL
VOLTAGE
STEP
Vref(T)
0
··•
··
·
Vref(Bl
DIGITAL OUTPUT CODE
LSB
MSB
1
1
127
1
0
128
0
1
255
0
0
·· ·· ··
·· ·· ··
1
··
··
0
1
0
1
··
··
0
1
0
1
··
··
0
1
0
1
1
1
0
·· ··
0
0
1
1
1
0
0
··
··
0
·· ··
~1EXAS
INSfRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265
2-165
-
2-166
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
• 8-Blt Resolution
• Linearity Error
- ±0.75 LSB Max (25°C)
- ±1 LSB Max (-20°C to 75°C)
• Differential Linearity Error
- ±0.5 LSB (25°(:)
- ±0.75 LSB Max (-20°C to 75°C)
• Maximum Conversion Rate of
40 Mega-Samples per Second (MSPS) Min
• Internal Sample and Hold
• 5-V Single-Supply Operation
• Low Power Consumption ... 100 mW Typ
• Analog Input Bandwidth •.• >75 MHz Typ
NSPACKAGE
(TOP VIEW)
OE
OGNO
01 (lSB)
02
03
05
06
07
08(MSB)
VOOO
elK
1
OGNO
REFB
REFBS
AGNO
AGNO
ANALOG IN
VOOA
9
11
REFT
REFTS
VOOA
VOOA
VOOO
AVAILABLE OPTIONS
applications
• Quadrature Phase Shift Keying (QPSK)
Demodulators
• Medical Imaging
• Charge-Coupled Device (CCD) Scanners
• Video Conferenclng
• Digital Set·Top Box
• Digital Down Converters
• Hlgh·Speed Signal Processing
NSPACKAGE
TLC5540INS
W
==
:;
w
a:
Il.
t)
:::l
C
description
The TLC5540 is a CMOS, 8-bit, 40 MSPS analog-to-digital converter (ADC) that utilizes a semiflash
architecture. The TLC5540 operates with a single 5 V supply and consumes only 100 mW of power typically.
Also included is an internal sample and hold circuit, parallel outputs with high impedance mode and internal
reference resistors.
The TLC5540 has a wide analog-input bandwidth typically greater than 75 MHz. This feature allows use of the
ADC in undersampling applications such as digital down converters and allows the elimination of expensive RF
components.
The semiflash architecture reduces power consumption and die size compared to flash converters. The
conversion is implemented in a 2-step process which significantly reduces the number of comparators. The
latency of the data upon conversion is 2.5 clocks.
The internal reference resistors can create a standard 2-V full-scale conversion range using VOOA. Only external
jumpers are required to implement this option, thereby reducing the need for external references or resistors.
The TLC5540 is characterized for operation from -20°C to 75°C. Differential linearity is ±0.5 LSB at 25°C and
a maximum of ±0.75 LSB over the full operating temperature range. Dynamic characteristics are specified with
a differential gain of 1% and differential phase of 0.7%.
~·TEXAS
Copyright II:> 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 6~03. DAUAS, TEXAS 75266
2-167
oa:
Il.
TLC5540
8·BIT HIGH·SPEED ANALOG·TO.;DIGITAL CONVERTER
SLAS105 - JANUARY 1995
functional block diagram
Resistor
Referance 1+-------------,
Divider
REFB
270n
NOM
REFT
I-c-l--I...r-:--.:-,
Lower sampling
r--+--+l~
REFBS
D1(LSB)
Comparatora
(4 Bit)
D2
son
D3
NOM
AGND
AGND
D4
Lower sampling
'-;--H~ Comparators
(4 Bit)
D5
VDDA
320n
NOM
REFTS
"tJ
ANALoG IN --======~--+-I~
::u
o
c
CLK
Upper sampling
Comparators
(4 Bit)
Clock
Generator
c:
~
"tJ
::u
m
<
-
m
:e
~TEXAS
2-168
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 76266
Upper Data
Latch
D8
D7
D8(MSB)
TLC5540
8-81T HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105-JANUARY 1995
schematics of Inputs and outputs
EQUIVALENT OF ANALOG INPUT
EQUIVALENT OF EACH DIGITAL INPUT
VDDA
EQUIVALENT OF EACH DIGITAL OUTPUT
VDDD
VDDD
Dl-D8
OE,CLK
ANALOG IN
AGND
DGND
Tenninal Functions
TERMINAL
NAME
AGNO
ANALOG IN
eLK
NO.
20,21
I
12
I
2,24
01-08
3-10
OE
1
Analog Input
Digital data out. 01 :LSB, 08:MSB
I
Output enable. When OE • L, data is enabled. When OE ~ H, 01-08 is high impedance.
14,15,18
AnalogVOO
11,13
OigitalVOO
REFBS
22
17
REFTS
16
:;
0
VOOO
REFB
REFT
W
Clock input
Digital ground
VOOA
23
;:
Analog ground
19
OGNO
DESCRIPTION
1/0
I
w
a::
a..
Reference voltage in (bottom)
Reference voltage (bottom). When using the internal voltage divider to generate a nominal2-V reference,
this terminal is shorted to the REFB terminal and the REFTS terminal is shorted to the REFT terminal (see
Figure 3).
I
Reference voltage in (top)
Reference voltage (top). When using the intemal voltage divider to generate a nominal 2-V reference, this
terminal is shorted to the REFT terminal and the REFBS terminal is shorted to the REFB terminal (see
Figure 3).
absolute maximum ratingst
Supply voltage, VOOA, Vooo ••••.••••••••••••••..•••.•.••••••••.•.••••••••••.••••.••.•••••••• 7 V
Reference voltage input range, Vref(T), Vref(B), Vref(BS), Vref(TS) •....•.••••••.•..••.••• AGND to VOOA
Analog input voltage range, VI(ANLG) ••.•••....•....•••.•.••••••••••••••••••••••.••• AGND to VOOA
Digital input voltage range, VI(OGTL) •••.••.•.......••.••.••••.••••••••••••••.•.••••. DGND to VOOO
Digital output voltage range, VO(OGTL) .•.••••••••.••.••.••.•.•.•••.••••••••••.••••. DGND to Vooo
Operating free-air temperature range, TA .......... ; ................................. -20°C to 75°C
Storage temperature range, Tstg .................................................. -55°C to 150°C
t Stresses beyond those listed under"absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
2-169
t>::J
C
o
a::
a..
TLC5540
\
8..BIT HIGH·SPEED ANALOG·TO..DIGITALCONVERTER
SLAS105 - JANUARY 1995
recommended operating conditions
.Supply voltage
MIN
NOM
VOOA-AGNO
4.75
5
MAX
5.25
VOOO-AGNO
AGNO-OGNO
4.75
5
5.25
0
100
-100
Reference input voltage (top), Vrefm
VreflBI+2
0
Reference input voltage (bottom), Vref(B)
Analog input voltage range, VI(ANLG) (see Note 1)
VreflBI+2
0.6
Vref(B)
4
High-level input voltage, VIH
UNIT
V
mV
2.7
V
Vrefm-2
V
Vrefm
V
V
Low-level input voltage, VIL
V
1
Pulse duration, clock high, tw(H)
25
ns
Pulse duration, clock low, twILl
25
ns
NOTE 1: REFT - REFB ~ 2.4 V maximum
electrical characteristics at Voo = 5 V, Vref(T) = 2.5 V, Vref(B) = 0.5 V, '(sampling) = 40 MSPS, TA = 25°C
(unless otherwise noted)
::D
o
EL
c:
EO
C
"lJ
m
<
-
m
=e
Unearity error
Linearity error, differential
Self bias (1)
~
::D
TEST CONDITIONSt
PARAMETER
"lJ
Self billS (2)
Self bias (3)
MIN
TYP
±1
~SamplI~) = 40 MSPS, TA" -20·C to 75°C
1=0.5 t02.5V
TA-25·C
±0.3
Short REFB to REFBS,
Short REFT to REFTS
Short REFB to AGNO,
Short REFT to REFTS
lref
Reference-voltage current
Reference-voltage resistor
Vrefm - Vref(B) .. 2 V
Between REFT and REFB terminals
Ci
Analog-input capaCitance
VI(ANLG),- 1.5 V + 0.07 Vrrns
EZS
EFS
Zero-scale error
Full-scale error
Vref" REFT - REFB = 2 V
±0.5
0.57
0.61
0.65
1.9
2.02
2.15
2.18
2.29
2.4
5.2
7.5
10.5
190
270
350
16
LSB
-18
-43
-20
0
V
mA
n
pF
-68
. 20
IIH
High-level input current
VOO-MAX,
VIH=VOO
5
IlL
Low-level Input current
VIL-O
5
IOH
High-level output current
VOO-MAX,
OE-GNO,
VOO-MIN,
VOH = VOO-0.5 V
IOL
Low-level output current
OE=GNO,
VOO-MIN,
VOL- 0.4 V
IOZH
High-level high-impedancestate output leakage current
OE .. VOO,
VOO=MAX
VOH=VOO
16
IOZL
Low-level high-impedancestate output leakage current
OE-VOOi
VOO-MIN
VOL-O
16
100
Supply current
f(sampllng) - 40 MSPS, National Television System
Committae (NTSC) ramp wave input
-1.5
mV
jIA
mA
2.5
jIA
..
.. .
t Conditions marked MIN or MAX are as stated In recommended operating conditions
~TEXAS
2-170
UNIT
±0.75
TA - -20·C to 75·C
Rref
MAX
±0.4 ±0.75
TA=25·C
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 76266
20
30
mA
TLC5540
8·BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTER
SLAS105-JANUARY 1995
=
=
=
=
=
operating characteristics atVDD 5 V, VRT 2.5 V, VRB 0.5 V, f(sampling) 40 MSPS, TA 25°C (unless
otherwise noted)
PARAMETER
Maximum conversion rate
VI(ANLGl
SW
Analog-input bandwidth
At-3dS
too
Digital-output delay time
CL s 10 pF (see Note 2)
Differential gain
Aperture jitter time
~(s)
Sampling delay time
2.5 V,
II
=I-kHz ramp wave lorm
TYP
MAX
40
UNIT
MSPS
>75
MHz
18
30
ns
1%
NTSC 40 Institute Radio Engineers (IREa
modulation wave,
'conv = 14. MSPS
Differential phase
tAJ
MIN
TEST CONDITIONS
=0.5 V -
l(samDlina)
0.7
degrees
30
ps
4
ns
NOTE 2: CL includes probe and Jig capacitance
I
Ii
I
I
I
I
I
I
I
01-08
(Output Data)
I
~y-
CLK(Clock)
ANALOG IN
(Input Signal)
I .
~
N-3
I
N+1
I
I
I
I
I N+2
I
I
I
I
~~~_N_-_2~J)(~~_N_-_1~-J)(~~
__N__
~J)(
l'--/i
I
I
I
I
I
I
W
==
:;
w
a:
a.
Io
;:)
N+1
tpd~
Figure 1. UO Timing Diagram
c
oa:
a.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-171
TLC5540
8·BIT HIGH·SPEED ANALOG·TO·DfGITAL CONVERTER
SLAS105 - JANUARY 1995
PRINCIPLES OF OPERATION
functional description
The TlC5540 is a semiflash, analog-to-cligital converter featuring two. lower comparator blocks of four bits each.
As shown in Figure 2, input voltage V,(1) is sampled with the falling edge of ClK1 to the upper comparators block
and the lower comparators block(A), 8(1). The upper comparators block finalizes the upper data UD(1) with the
rising edge of ClK2, and simultaneously, the lower reference voltage generates the voltage RV(1)
corresponding to the upper data. The lower comparators block (A) finalizes the lower data lD(1) with the rising
edge of ClK3. UD(1) and lD(1) are combined and output as OUT(1) with the rising edge of ClK4. According
to the above internal operation described, output data is delayed 2.5 clocks from the analog input voltage
sampling point.
Input voltage V,(2) is sampled with the falling edge of ClK2. UD(2) is finalized with the rising edge of ClK3, and
lD(2) is finalized with the rising edge of ClK4 at the lower comparators block(B). OUT(2) is output with the rising
edge of CLK5.
"'0
::u
ANALOQIN
(Sampling POints)
o
c
c:
5l
CLK(Clock)
"'0
::u
Upper Comparators Block
m
<
-
I I I i I I I i I
8(1)
C(l)
8(2)
C(2)
8(3)
C(3)
8(4)
C(4)
Upper Data
m
:e
Lower Reference Voltage
Lower Comparators Block (A)
Lower Data (A)
Lower Comparatore Block (8)
Lower Data (B)
:JKI
LD(-2)
:x
OUT(-2)
X
LD(O)
I
I
I
I
X
OUT(-l)
X
I
I
.
~
I
I
LD(2)
I
I
OUT(O)
X
Figure 2. Internal Functional Timing Diagram
~TEXAS
2-172
C
L~(l)
+: 'i~I~1
+" ICOOIS(~1, +
I
I
I
Dl-D8 (Data Output)
*
LD~-l)
INSTRUMENTS
POST OFACE BOX 658303 • DALlAS, TEXAS 7~
I
I
OUT(l)
x=
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105 - JANUARY 1995
PRINCIPLES OF OPERATION
internal referencing
Three internal resistors allow the device to generate an internal reference voltage. These resistors are brought
out on terminals VOOA, REFTS, REFT, REFB, REFBS, and AGND.
To use the internally-generated reference voltage, terminal connections should be made as shown in Figure 3.
This connection provides the standard video 2-V reference for the nominal digital output.
TLC5540
18
VDDA
(Analog Supply)
R1
3200NOM
RE FTS
I
16
17
REFT
Rref
2700 NOM
REFB
23
I
22
~
W
RE FBS
•
AGND
21
:;
R2
80 o NOM
w
a:
..1
D..
Figure 3. External Connections for Using the Internal Reference Resistor Divider
t;
functional operation
::l
C
Table 1 shows the TLC5540 functions.
o
a:
Table 1. Functional Operation
INPUT SIGNAL
VOLTAGE
STEP
Vref(T)
0
··
···
·
Vref(B)
D..
DIGITAL OUTPUT CODE
LSB
MSB
1
1
127
1
0
128
0
1
255
0
0
·· ·· ··
·· ·· ··
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
· ·· · ·· ·· ··
·
·
·· ·· ·· · · ·
· · ·
0
0
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75266
2-173
TLC5540
8·BIT HIGH·SPEED ANALOG·TO-DIGITAL CONVERTER
SLAS105-JANUARY 1995
APPLICATION INFORMATION
The fol/owing notes are design recommendations that should be used with the TlC5540.
•
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
•
RF breadboarding or printed-circuit-board (PCB) techniques should be used throughout the evaluation and
production process. Breadboards should be copper clad for bench evaluation.
•
Since AGNO and OGNO are not connected internally, these terminals need to be connected externally. With
breadboards, these ground lines should be connected through separate leads with correct supply
bypassing. Separate twisted-pair cables are a good method to use for the supply lines to minimize noise
pickup. An analog and digital ground plane should be used on PCB layouts.
•
VOOA to AGNO and VOOO to OGNO should be decoupled with 1-I1F and O.01-I1F capacitors, respectively,
placed as close as possible to the appropriate device terminals. A ceramic-chip capacitor is recommended
for the O.01-I1F capacitor. Care should be exercised to ensure a solid noise-free ground connection for the
analog and digital grounds.
•
VOOA, AGNO, and ANALOG IN terminals should be shielded from the higher frequency terminals, ClK and
00-07. If possible, AGNO traces should be placed on both sides of the ANALOG IN traces on the PCB for
shielding.
•
In testing or application of the device, the resistance of the driving source connected to the analog input
should be 10 nor less within the analog frequency range of interest.
"'0
::D
o
C
c
5l
"'0
::D
m
-m
<
~
~TEXAS
2-174
INSTRUMENTS
POST OFACEBOX 655303 • 'DALLAS. TEXAS 75265
TLC5733
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
•
•
•
•
•
• Analog Input Bandwidth ••. >14 MHz
• Suitable for YUV or RGB Applications
• Digital Clamp Optimized for NTSC or PAL
YUV Component
a-Channel CMOS ADC
8-Blt Resolution
Differential Linearity Error •.• ±0.5 LSB Max
Linearity Error •.• ±0.75 LSB Max
Maximum Conversion Rate
20 Mega-Samples per Second
(MSPS) Min
•
•
•
•
•
• Analog Input Voltage Range
2 V(PP) (Min)
• 64-Pln Shrink QFP Package
High Precision Clamp ... ±1 LSB
Automatic Clamp Pulse Generator
Output Data Format Multiplexer
SOV Single-Supply Operation
Low Power Consumption
description
The TLC5733 is a three-channel 8-bit semiflash analog-to-digital converter (ADC) that operates from a single
5-V power supply. It converts a wide-band analog signal (such as a video signal) to digital data at sampling rates
up to 20 MSPS minimum. The TLC5733 contains a feed-back type high-precision clamp circuit for each ADC
channel for video (YUV) applications and a clamp pulse generator that detects COMPOSITE SYNCt pulses
automatically. A clamp pulse can also be supplied externally. The output data format multiplexer selects a ratio
of Y:U:V of 4:4:4,4:1:1, or 4:2:2. For RGB applications, the 4:4:4 output format without clamp function can be
used. The TLC5733 is characterized for operation from -20°C to 75°C.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
45
44
1<:)
NT/PAL
43
42
41
40
39
38
37
36
7
8
9
10
AD1
QA DVoo
DGND
12
13
14
35
15
34
16
33
17 181920212223242526272829303132
MODED
MODE1
QC DGND
CD1
CD2
CD3
CD4
CDS
CD6
CD7
CDS
QC DVoo
OE C
RB C
ClOI"-(DLO~(,)t\I ... ClClOOOOZO
ClClClClClClClClZClI->I-OOCl
Z
ClClO..J
C(
C)
1Il1Il1Il1Il1Il1Il1Il1IlC»::>c...a::>
III
o
c... 0
d
0
t COMPOSITE SYNC refers to the extemally generated synchronizing signal that is a combination of vertical and horizontal sync information
used in display and TV systems.
~1ExAs
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 856303 • DAu.AS. TEXAS 75265
2-175
TLC5733
20 MSPS 3-CHANNEL ANALOG~TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104-JULY 1995
AVAilABLE OPTIONS
PACKAGE
TA
QUAD FlATPACK
-20·C to 75·C
TLC5733IPM
functional block diagram
r---------------,
C~A
I
AIN
RT A
II
IDJ
r
I
ClPOUTA
BIN
"-jI
ClPV B
ClPOUTB
CIN
RT C
I
I
iI
I
Clamp
Circuit
•
I
8
ADC
(Sampling
Comparators)
"-j' I
II
Clamp
CIrCuit
r--8
I
II
I
I
I
I
~
ADC
(Sampling
Comparstors)
I
-:1
I
Clamp
Circuit
~I
I
I
I
I
ClKA . -
E~ClP------~~co::nt:rc;I;.Fo:rl
ClK B ' -
INT/E~
I-Clamp Circuit
------+1.=:::.:::..:::1
ClKC . -
Multiplexer
For
Output Format
8
~....-
CD1-8
Output Data
Latch
iii
Clock
Generator
j ---r-'j
"-T-ClK
INIT
-!!1 TEXAS'
2-176
BD1-8
Output Data
latch
8
~----------- --~~
ClPEN ------.....
8
~.....-
1~81
II
•
IDJ
I
ClPV C i
NT/PAL
AD1-8
II
~
I~--------------,
ClKC
I
~C
ClPOUTC
~8
I~--------------~
ClKB
I
RT B l l i J !
~B
I
8
8
~.....ADC
t-~~~+_-----~-~
(Sampling
Output Data
Comparators)
r--8 I
latch
~A
!
ClPV A i
I
'.
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75285
Output
Format
Selector
and Teat
MODEO
.....
1 -_ _ MODE1
H----- TEST
TLC5733
20 MSPS 3·CHANNEL ANALOG·TO-DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
SLAS104-JULY 1995
Terminal Functions
TERMINAL
NAME
AAVCC
AD8-ADI
AIN
BAVCC
BD8-BDl
BIN
CAVCC
CD8-CDl
NO.
DESCRIPTION
I/O
62
I
6-13
0
Data output of ADC A (LSB: AD1, MSB:AD8)
63
I
Analog input of ADC A
Analog VCC of ADC B
Analog VCC of ADC A
51
I
17-24
0
Data output of ADC B (LSB: BD1, MSB:BD8)
50
I
Analog input of ADC B
30
I
Analog VCC of ADC C
36-43
0
Data output of ADC C (LSB:CD1, MSB: CD8)
When MODEO = L, MODEl = L, CD8 outputs MSB flag of BD8-BD5
When MODEO = L, MODEl = L, CD7 outputs MSB flag of BD8-BD5
When MODEO = L, MODEl = H, CD8 outputs B channel flag of CD8-BDl
When MODEO = L, MODEl = H, CD8 outputs B channel flag of CD8-BDl
CIN
31
I
Analog input of ADC C
CLK
56
I
Clock input. The clock frequency is normally 4 fsc for most video systems (see Table 3). The nominal clock
frequency is 14.31818 MHz for NTSC and 17.745 MHz for PAL.
CLPEN
57
I
Clamp enable. When using an internal clamp pulse, CLPEN should be high. When USing an external clamp
pulse, CLPEN should be low.
CLPOUTA
59
54
CLPOUTC
27
CLPVA
60
0
0
0
0
Clamping bias current of ADC A. A resistor-capacitor combination is used to set the clamp timing.
CLPOUTB
CLPVB
63
0
Clamping level of ADC B. A capacitor is connected to CLPV B to set the clamp timing. The clamp level at
this terminal is connected to an output code of 128 (1000000).
CLPVC
28
0
Clamping level of ADC C. A capacitor is connected to CLPV C to set the clamp timing. The clamp level at
this terminal Is connected to an output code of 128 (1000000).
Clamping bias current of ADC B. A resistor-capacitor combination is used to set the clamp timing.
Clamping bias current of ADC C. A resistor-capacitor combination is used to set the clamp timing.
Clamping level of ADC A. A capaCitor is connected to CLPV A to set the clamp timing. The clamp level at
this terminal is connected to an output code of 16 (0010000).
DGND
15
I
Digital ground
DVDD
EXTCLP
26
I
55
I
Digital VDD
Extemal clamp pulse input. When this terminal is low and CLPEN Is low, the Intemal clamp circuit cannot
be used.
GNDA
64
I
Ground of ADC A
GNDB
49
I
Ground of ADC B
GNDC
32
I
Ground of ADC C
INIT
58
I
Output initialized. The output data is synchronous when INIl: is taken high from low. This control terminal
allows the external system to initialize the TLC5733 data conversion cycle. It Is usually used upon power
up or system reset.
Output format mode selector 0
MODEO
46
I
MODEl
45
I
Output format mode selector 1
NT/PAL
3
I
NTSC/PAL control. The NTSC/PAL terminal should be: NTSC = low level, PAL = high level.
OEA
2
I
Output enable of ADC A
CEB
47
I
Output enable of ADC B
CEC
34
I
Output enable of ADC C
QADGND
5
I
Digital ground for output port of ADC A
QADVDD
QBDGND
14
I
Digital VDD for output of ADC A
25
I
Digital ground for output of ADC B
QBDVDD
16
I
Digital VDD for output of ADC B
~TEXAS
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265
2-177
TLC5733
20 MSPS a·CHANNEL ANALOG·TO·DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP .
SLAS104,,"JUI.,Y 1996
Terminal Functions (Continued)
TERMINAL
NAME
NO.
110
DESCRIPTION
aCDGND
44
I
Digital ground for output of ADC C
aCDVDD
35
I
Digital VDD for output of ADC C
RBA
1
I
Reference voltage bottom of ADC A
RBB
48
I
Reference voltage bottom of ADC B
RBC
33
I
RTA
61
I
Reference voltage bottom of ADC C
Reference voltage top of ADC A. The nominal extemaly applied DC voltage between the AT A terminal and
the RB A terminal is 2 V for video signals.
RTB
52
I
ATC
29
TEST
4
Reference voltage top of ADC B. The nominal extemaly applied DC voltage between the AT B terminal and
the RB B terminal Is 2 V for video signals.
Reference voltage top of ADC C. The nominal extemaly applied DC voltage between the RT C terminal and
the RB C terminal is 2 V for video signals.
I
Test. This terminal should be tied low when using this device.
absolute maximum ratlngst
Supply voltage, Vee, Voo .....••...•.•........•............................................. 7 V
Reference voltage input range,Vref(RT A), Vref(RT B), Vref(RT e), Vref(RB A),
Vref(RB B),.Vref(RB e) ........................................................... AGND to vee
Analog input voltage range ....•.................................................... AGND to Vee
Digital input voltage range, VI ....................................................... DGND to Voo
Digital output voltage range, Vo .................................................... DGND to Voo
Operating free~air temperature range, TA ............................................ -20 oe to 75°e
Storage temperature range, TStg •.•...............•............................... -55°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional oper;ation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Supply vQltage
MIN
NOM
MAX
VCC-AGND
4.75
5
5.25
VDD-DGND
AGND-DGND
4.75
5
5.25
-100
0
Reference input voltage, VreflRT AI, VreflRT BI, VreflAT CI
Reference Input voltage, VreflRB AI, VreflRB BI, VreflRB CI
Analog input voltage, VI
High-level input voltage, VIH
VrefIRBI+2
0
0
V
100
mV
VCC
VreflRn- 2
V
VreflRn
V
4
Low-level Input voltage, VIL
UNIT
V
V
1
V
High-level pulse duration, twlHI
25
ns
Low-level pulse duration, twIll
25
ns
Setup time for INIT input, tau1
5
-20
Operating free-air temperature range, TA
~TEXAS
2-178
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ns
75
·C
TLC5733
20 MSPS 3·CHANNEL ANALOG-TO·DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
SLAS104 - JULY 1996
=
=
=
=
=
electrical characteristics at Voo 5 V, Vref(RT) 2.5 V, Vref(BB) 0.5 V, fs 20 MSPS, TA 25°C (unless
otherwise noted)
PARAMETER
Clamp level accuracy
TEST CONDITIONS
Relerence voltage resistor
Measured between AT and RB
Analog inpu1 capacitance
VI = 1.5 V + 0.07 Vrms
IlL
IOH
High-level inpu1 current
Low-level inpu1 current
High-level Outpu1 current
VOD-MAXt,
VOO-MAXt,
VOO-MINt,
VIH-VOO
VIL-O
VOH • VOO-0.5 V
IOL
Low-level Outpu1 current
VOO-MINt,
VOL- 0.4 V
Rrel
Ci
IIH
MIN
TYP
±1
MAX
160
220
350
LSB
16
5
-1.5
=
jIA
mA
2.5
High-level outpu1leakage current
VOO=MAXt,
VOH-VOD
Low-level outpu1leakage current
VOD=MINt,
VOL-O
IOZL
NTSC ramp wave input
Supply current
Is ·20MSPS,
ICC
t Conditions marked MIN or MAX are as stated In recommended operating conditions.
=
a
pF
5
IOZH
=
UNIT
=
16
16
jIA
75
mA
=
operating characteristics atVOO 5 V, Vref(RT) 2.5 V, Vref(RB) 0.5 V, fs 20 MSPS, TA 25°C (unless
otherwise noted)
Ezs
PARAMETER
Zero-scale error
EFS
Full-scale error
TEST CONDITIONS
Vref - REFT - REFB - 2 V
Vref - REFT - REFB - 2 V
Is ·20MSPS,
Is. 20 MSPS,
TA. -20'C to 75'C
MIN
-18
TYP
-43
-20
0
20
±0.4 ±0.75
VI • 0.5 V to 2.5 V
EL
Linearity error
Is =20MSPS,
VI = 0.5 Vt02.5 V
ED
Linearity error, differential
Is -20MSPS,
TA - -20"C to 75'C
VI = 0.5 V to 2.5 V
Is
BW
Maximum conversion rate
VI_ 0.5 V -2.5 V,
II - 1-kHz ramp wave lorm
Analog input bandwidth
At-1 dB
14
tpd
O~~ou1putdelaytime
CL-10pF
18
Differential gain
Differential phase
tAJ
lips
VI • 0.5 V to 2.5 V
NTSC 40 IRE modulation wave, Is -14.3 MSPS
Aperture jitter time
Sampling delay time
MAX
-68
±0.4
±1
±0.3
±0.5
±0.3 ±0.75
20
UNIT
mV
mV
LSB
LSB
MSPS
1%
0.7
MHz
30
ns
deg
30
ps
4
ns
~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75286
2-179
TlC5733
20 MSPS 3·CHANNEl ANALOG·TO·DIGITAlCONVERTER
WITH HIGH·PRECISION CLAMP
. SLAS104 - JULY 1995
detailed description
clamp function
The clamp function is optimized for a YUV video signal and has two clamp modes. The first mode uses the
COMPOSITE SYNC signal as the input to the EXTCLP terminal to generate an internal clamp pulse and the
second mode uses an externally generated clamp pulse as the input t.o the EXTCLP terminal.
In the first mode, the device detects false pulses in the COMPOSITE SYNC signal by monitoring the rising edges
and falling edges of the COMPOSITE SYNC signal pulses. This monitoring prevents faulty operation caused
by disturbances and missing pulses of. the COMPOSITE SYNC signal input on EXTCLP and external spike
noise. When fault pulses are detected, the device internally generates a train of clamp pulses at the proper
positions (1 H) by an internal 91 O-counterfor NTSC and a 1136-counter for PAL. The device checks clamp pulses
for 1H time and generates clamp pulses at correct positions if COMPOSITE SYNC pulses are in error in time.
The internal counter continually produces a horizontal sync period (1 H) that is NTSC or PAL compatible as
selected by the condition of the NT/PAL terminal.
clamp voltages and selection
Table 1 shows the clamping level during the clamp interval. Table 2 shows the selection ofthe internal or external
clamp pulse. With either NTSC or PAL, the internal clamp pulse is always used.
Table 1. Clamp Level (Internal Connection Level)
CHANNEL OF ADC
OUTPUT CODE
APPLICATION
ADCA.VI(A)
00010000
10000000
10000000
(U, V)
ADCB.VI(Bt
ADCC.VIICI
Y
(U, V)
Table 2. Clamp Level (Internal Connection Level)
FUNCTION (EACH ADC)
CONDITION
CLPEN
L
H
CLAMP PULSE .
EXTCLP
NT/PAL
INTERNAL CLAMP
It
Don't Care
Inactive
L
Don't Care
Inactive
No clamping
L
Active
Synchronous with NTSC
H
Active
Synchronous with PAL
COMPOSITE SYNC input
External clamp pulse
The clamp circuit is shown in Figure 6. The clamp voltage is stored on capacitor C2 during the back porch of
the horizontal blanking period.
During the clamp pulse the input to channel A is clamped to
Vc(A} = (16/256) x (voltage difference from terminal RT A to RB A)
VC(B} = (128/256) x (voltage difference from terminal RT B to RB B)
Vc(C} = (128/256) x (voltage difference from terminal RT C to RB C)
COMPOSITE SYNC time monitoring
When CLPEN is high, COMPOSITE SYNC generates an internal clamp pulse on the horizontal blanking interval
back porch. The TLC5733 has atiming window into which the horizontal sync tip must occur. There is a noise
time window for the falling edge and a noise time window for the rising edge. Refer to Figure 1, Figure 2, and
Table 3.
~TEXAS
2-180
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733
20 MSPS 3·CHANNEL ANALOG·TO·DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
SLAS104-JULY 1995
correct COMPOSITE SYNC timing
The NOise Gate 1 signal provides the timing window for the COMPOSITE SYNC falling edge. After an interval
A of 867 clocks for NTSC or 1075 for PAL from the last falling edge of COMPOSITE SYNC, Noise Gate 1 goes
high for 43 clocks for NTSC or 61 clocks for PAL (interval B). The falling edge of the input signal to the EXTCLP
terminal can occur at any time within this window to be a valid COMPOSITE SYNC falling edge.
The Noise Gate 2 signal provides the timing window for the COMPOSITE SYNC rising edge. On the falling edge
of the horizontal sync tip, the internal logic generates Noise Gate 2 as a low signal for 58 clocks (interval C) for
both NTSC and PAL and then returns to a high active state. If, at this time, the input to the EXTCLP terminal
is still low, it is considered a valid COMPOSITE SYNC signal.
normal clamp pulse generation
On the rising edge of the COMPOSITE SYNC signal, the internal logic generates an internal delay (interval D)
and then generates the internal positive clamp pulse 54 clocks wide (interval F).
clamp operation with incorrect COMPOSITE SYNC timing
noise suppression
If the input to the EXTCLP terminal goes low prior to Noise Gate 1 going high (within 43 clocks for NTSC or 61
clocks for PAL of the normal 1H timing for the falling edge of COMPOSITE SYNC) then that input is not
considered a valid COMPOSITE SYNC and is ignored.
If the input to the EXTCLP terminal is high when NOise Gate 2 goes to the high state, the input signal is
considered noise and is ignored.
Therefore, the correct signal must be high a maximum of 43 clocks for NTSC or 61 clocks for PAL, before the
1H timing, to be a valid sync signal. Also, the input to the EXTCLP terminal must be at least 58 clocks wide
(interval C) to be valid.
This function of monitoring the timing eliminates spurious noise spikes from falsely synchronizing the system.
timing error of COMPOSITE SYNC
The internal counter resets to zero on the first falling edge of COMPOSITE SYNC. After that time, if there is a
missing COMPOSITE SYNC signal, then the internal logic waits an interval of 76 clocks (interval E) for NTSC
or 93 for PAL from the counter zero count and then generates an internal clamp pulse 54 cloCks wide
(interval F).
This function maintains the synchronization pattern when COMPOSITE SYNC is not present.
summary of device operation with COMPOSITE SYNC
This internal timing allows the TLC5733 to correctly position the clamp pulse when an external COMPOSITE
SYNC input occurs as follows:
•
•
•
•
Is delayed with respect to the horizontal sync period
Is early with respect to the horizontal sync period
Is nonexistent during the horizontal sync period
Has falling edge noise spikes within the horizontal sync period
The device operation is summarized as follows for these improper external clamp conditions.
•
Under all four conditions on the EXTCLP terminal, the internal clamp generation circuit generates a
clamp pulse at the proper time after the horizontal sync period as shown in Figure 1.
•
The TLC5733 internal clamp circuit generates an internal clamp pulse each 1H time for the entire time
interval that the COMPOSITE SYNC input is missing.
~ThxAs
INSTRUMENTS
POST OFFice BOX 665303 • DALLAS. TexAS 75265
2~181
TLC5733
,
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104-JULY1995
1~.----------1H------------~.~
COMPOSITE
SYNC
I
!
I
B
-lr---.-....,..r----.:..- - - A ---------~.r-I
Noise Gate 1
NolseQate2
_
II
I-_~
ct:f
i
Intemsl Clamp
Pulse
I
I
f..--.J!
.'"
_ _ _ _ _ _ _ _--'.
/
~~I'~I. .-----
1,'1
D-.j
.
Missing COMPOSITE SYNC
therefore Noise Gate Is Not
Generated
I
I
j+-
NTSCIPAL Counter at
Max Count
NTSc/PAL Counter R_t
Figure 1. COMPOSITE SYNC and Internal Clamp Timing
COMPOSITE
SYNC
~\j
/II/!
-ri________
__ __________
I
Noise Gate 1
~r-B~~I
I
I
I
I
I
I
~~
Noise Gate 2
I
Figure 2. Proper COMPOSITE SYNC Timing
Table 3. Sync and Clamp Timing for NTSC and PAL with CLK = 4 fsc
TIME
INTERVAL
PAL
NTSC
NO. OF
CLOCKS
TIME
(jJ.s)
NO. OF
CLOCKS
TIME
(jJ.s)
A
867
60.8
1075
B
43
61
3.5
C
0
58
3
4.05
58
3.27
E
76
0.42
5.3
6
93
5.25
3.77
84
4.43 MHz
F
fsc
6
54
3.58 MHz
60.7
0.34
4.74
using an external clamp pulse
When CLPEN is taken low, the EXTCLP terminal accepts an externally generated active-high clamp pulse. This
pulse must occur within the horizontal blanking interval back porch. CLPEN low inhibits the internal counters
and no internal clamp pulse is generated.
~1ExAs .
2-182
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
TLC5733
20 M$PS 3-CHANNEL ANALOG;.TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104-JULY 1995
output digital code (for each channel of ADC)
Table 4. Input Signal Versus Output Digital Code
INPUT SIGNAL
VOLTAGE
STEP
Vref(Rn
255
DIGITAL OUTPUT CODE
LSB
MSB
1
1
1
1
128
1
0
0
0
127
0
1
1
1
0
0
0
0
0
·· ·· ·· ·· ··
·· ·· ·· ·· ·
·
···
·
··
Vref1RB)
1
1
1
1
0
0
0
··
1
1
1
1
0
0
0
·· ·· ··
·· · ·
· ·
0
··
0
output data format
The TLC5733 can select three output data formats to various TVNCR (video) data processing by the
combination of MODEO and MODE1. The output is synchronous when INIT is taken high.
Table 5. Output Data Format Selection
CONDITION
OUTPUT DATA
MODEO
OUTPUT DATA
FORMAT
RATIO OF Y:U:V
L
L
Format 1
4:1:1
L
H
Format 2
4:4:4
H
L
Format 3
4:2:2
H
H
Not used
NlA
MODE1
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-183
TLC5733
20 MSPS 3-CHANNEL ANALOG·TO·DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
.
SIAS104-JULY 1996
output data format (continued)
CLK
INIT
____",
Analog
Input VI(ANLG)
Output Data A
Output Data B
BOB-B05
B04-B01:
HI·Z
Output Data C
CDS
C07
C08-C01: HI-Z
o = Input signal sampling point
Figure 3. Format 1, 4:1:1
~1ExAs
2-184
INSIRUMENTS
POST OFFICE BOX 666303. DALlAS. TEXAS 7 _
TLC5733
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104-JULY 1995
output data format (continued)
Ir---.~
Bit
A06
I L-~
L---.
Value of Sampling Data
Channel of ADC
Table 6. Format 1
CHANNEL OF
ADC
BIT
A
AD8
AD7
AD6
AD5
AD4
AD3
AD2
ADl
A08
A07
A06
A05
A04
A03
A02
AOl
A18
A17
A16
A15
A14
A13
A12
All
A28
A27
A26
A25
A24
A23
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BDl
B08
B07
C08
C07
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B06
B05
C06
C05
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CDl
H
L
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
L
L
6
7
B
C
CLK (see Note 2)
NOTES:
OUTPUT DATA
A21
A38
A37
A36
A35
A34
A33
A32
A31
A48
A47
A46
A45
A44
A43
A42
A41
A58
A57
A56
A55
A54
A53
A52
A51
A68
A67
A66
A65
A64
A63
A62
A61
A78
An
A76
A75
A74
A73
A72
A71
B04
B03
C04
C03
B02
BOl
CO2
COl
B48
B47
048
047
B46
B45
C46
C45
844
B43
C44
C43
B42
B41
C42
041
A22
.
L
L
L
H
H
L
L
L
L
L
L
H
...
~
8
9
10
11
12
13
1. HI-Z - high Impedance
2. The value of the first sampling clock at A-D conversion is CLK O.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAs. TEXAS 75265
2-185
TLC5733
20 MSPS 3-CHANNEL ANALOG·TO-DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
SLAS104-JULY1996
output data format (continued)
INIT
~-+-"I
OEA
OEB
OECAnalog
Input VI(ANLG)
Output Data A
ADS-AD1
Output Data B
BDS-BD1
Output Data C
CDS-CD1
o - Input signal sampling point
Figure 4. Format 2, 4:4:4
~TEXAS
2-1S6
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75265
TLC5733
20 MSPS 3·CHANNEL ANALOG·TO·DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
SLAS104 - JULY 1995
output data format (continued)
Ir - -••
Bit
A06
I L--. Value of Sampling Data
L-. Channel of ADC
Table 7. Format 2
CHANNEL OF
ADC
BIT
A
AD8
AD7
AD6
AD5
AD4
AD3
AD2
ADl
A08
A07
A06
A05
A04
A03
A02
AOl
A18
A17
A16
A15
A14
A13
A12
All
A28
A27
A26
A25
A24
A23
A22
A21
6D8
6D7
6D6
6D5
6D4
6D3
6D2
6Dl
608
607
606
605
618
617
616
615
614
613
612
611
62.8
627
626
625
624
623
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CDl
C08
C07
C06
C05
C28
C27
C26
C25
C24
C23
C22
C2l
C38
C37
C36
C35
C03
CO2
COl
C18
C17
C16
C15
C14
C13
C12
Cll
6
7
8
6
C
ClK (see Note 2)
OUTPUT DATA
B04
603
602
601
C04
B22
621
A38
A37
A36
A35
A34
A48
A47
A46
A45
A44
A43
A42
A41
A58
A57
A56
A55
A54
A53
A52
A51
A68
A67
A66
A65
A64
A63
A62
A61
A78
A77
A76
A75
A74
A73
A72
A71
648
647
646
645
644
643
642
641
658
657
656
655
654
653
652
651
668
667
666
665
664
663
662
661
678
677
676
675
674
673
672
671
C33
C32
C31
C48
C47
C46
C45
C44
C43
C42
C4l
C58
C57
C56
C55
C54
C53
C52
C51
C68
C67
C66
C65
C64
C63
C62
C61
C76
C75
C74
C73
C72
C71
9
10
11
12
13
A33
A32
A31
638
637
636
635
B34
633
632
631
C34
C78
cn
NOTE 2: The value of the first sampling clock at A-D conversion IS ClK O.
.
I~TEXAS
NSTRUMENTS
POST OFFICE BOX 666303 • OAUAS. TEXAS 75265
2-187
TLC5733
20 MSPS 3·CHANNEL ANALOG·TO·DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
SLAS104 - JULY 1995
output data format (continued)
CLK
INIT
-I-....,j-"I
OEA
OEB
OECAnalog
Input VI(ANLG)
Output Data A
ADS-ADl
Output Data B
BDS-BDl
Output Data C
CDS
CD7
CDS-COl: HI-Z
o - Input signal sampling point
Figure 5. Format 3, 4:2:2
~IJ TEXAS
2-188
NSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC5733
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104-JULY 1995
output data format (continued)
'I- - . . Bit
A06
I L-. Value of Sampling Data
L---. Channel of ADC
Table 8. Format 3
CHANNEL OF
ADC
A
8
C
ClK (see Note 2)
BIT
A08
A07
A06
A05
A04
A03
A02
AOl
B08
807
B06
805
804
B03
802
801
C08
C07
C06
C05
C04
C03
CO2
COl
OUTPUT DATA
AOS
A07
A06
A05
A04
A03
A02
A01
BOS
807
806
B05
A18
A17
A16
A15
A14
A13
A12
All
A28
A27
A38
A48
A58
A37
A47
A57
A26
A38
A25
A35
A48
A45
A24
A23
A34
A56
A55
A54
A68
A67
A66
A65
A64
A63
A62
A61
868
867
A44
A43
A42
A41
848
847
846
A51
048
047
046
B45
C45
844
044
B43
B42
C43
C42
861
A53
A78
A77
A76
A75
A74
A73
A72
A71
068
C67
C66
A22
A33
A32
B03
C07
C06
COO
C04
C03
A21
828
827
826
825
824
823
A31
028
027
026
025
024
023
B02
CO2
B22
C22
801
COl
821
841
H
L
Hi-Z
HI-Z
Hi-Z
HI-Z
Hi-Z
Hi-Z
L
H
H
L
021
l
H
041
l
H
C64
C63
C62
C61
l
H
l
H
l
H
6
7
8
9
10
11
12
13
B04
cos
A52
B66
865
B64
863
B62
C65
NOTES: 1. HI-Z. high Impedance
2. The value of the first sampling clock at A-O conversion is ClK O.
~1ExAs
INS1RUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265
2--189
TLC5733·
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104-JULY 1995
APPLICATION INFORMATION
I~----------~--------~-----TlC5733
I
I
Vref
(Top) RT A
(RTB,
RTC)
Video
Input
ClK
AID
2V(pp)
Output
Format
Control
Block
Video
Buffer
Amp
Vref
(Bottom)
Charge
Pump
.------.,
I
Magnitude
Comparator
ClPVA
(ClPVB,
ClPVC)
P=Q
R1
I
I
16kn I
I
I
I
C1
I ClPOUT A
I T 2200 pF I (ClP OUT B,
II.. _
rh_ _ _ _ .JI ClP OUT C)
P , .... _ _-'
1-----+-1 P > Q Q
Charge Pump
'----+---
FUNCTION FOR FEEDBACK CLAMP AND CHARGE PUMP
INPUT DATA
CONDITIONS·
PQ
OUTPUT
CHARGE PUMP
CONDITIONS
P=Q
P"'>Q
Active
H
Charge
Hold
Z
Hold
Active
L
Discharge
Figure 6. Feedback Clamp .Clrcult
~TEXAS .
2-190
P/'88etCode
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS. TEXAS 75265
Clamp Gate
TLV1543C,TLV1543M
3.3-V 10-81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
- DECEMBER 1992-
•
•
•
•
•
•
•
•
•
•
MARCH 1995
DB, DW, FK, J, OR N PACKAGE
(TOP VIEW)
3.3-V Supply Operation
10-Blt-Resolutlon AID Converter
11 Analog Input Channels
Three Built-In Self-Test Modes
Inherent Sample and Hold
Total Unadjusted Error ••• ± 1 LSB Max
On-Chip System Clock
End-of-Converslon (EOC) Output
Pin Compatible With TLC1543
CMOS Technology
Vcc
AO
EOC
1/0 CLOCK
ADDRESS
DATA OUT
CS
REF+
REF-
A3
A6
A7
AS
GND
description
FNPACKAGE
(TOP VIEW)
The TLV1543C and TLV1543M are CMOS 1Q-bit,
switched-capacitor, successive-approximation,
analog-to-digital converters. These devices have
three inputs and a 3-state output [chip select (CS),
input-output clock (I/O CLOCK), address input
(ADDRESS), and data output (DATA OUnJ that
provide a direct 4-wire interface to the serial port
of a host processor. The devices allow high-speed
data transfers from the host.
00
~<~$'@
A3
4 3 2 1 20 1918
1/0 CLOCK
A4
A5
A6
A7
5
6
ADDRESS
DATA OUT
17
16
7
15
8
14
9 10 11 12 13
as
REF+
In addition to a high-speed AID converter and
versatile control capability, these devices have an
on-chip 14-channel multiplexer that can select any
~ ~ ~ ~ .1one of 11 analog inputs or anyone ofthree internal
C!'
~
self-test voltages. The sample-and-hold function is automatic. At the end of AID conversion, the
end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated
in the devices features differential high-impedance reference inputs that facilitate ratiometric conversion,
scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows
low-error conversion over the full operating free-air temperature range.
The TLV1543C is characterized for operation from O°C to 70°C. The TLV1543M is characterized for operation
over the full military temperature range of -55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
SMALL
OUTLINE
(DB)
SMALL
OUTLINE
(DW)
0·Ct070·C
TLV1543CDB
TLVl543CDW
-55·C to 125·C
-
-
TA
CHIP CARRIER
(FK)
CERAMIC DIP_
(J)
-
-
TLVl543MFK
TLVl543MJ
I~TEXAS
NSTRUMENTS
POST OFFICE BOX 8S5303 • DAUAS. TEXAS 75266
PLASTIC DIP
(N)
PLASTIC CHIP
CARRIER
(FN)
TLVl543CN
TLVl543CFN
-
-
Copyright II:) 1995. Texas Instruments Incorporated
2-191
TLV1543C,TLV1543M
3.3-V 10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C - DECEMBER 1992 - REVISED MARCH 1995
functional block diagram
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
1
"2
t---
3"
4"
S-
a7"
8
Sample and
Hold
REF+
REF-
114
113
10-SIt
Analog-to-Dlgltal
Converter
(switched capacitors)
-
10
14-Channel
Analog
Multiplexer
~
9
11
12
-=
~ Input
Address
Register
-
Output
Data
Register
I
~
1D-to-1 Data
Selector and
Driver
r1!- DATA
OUT
~
4
3
"-
~
ADDRESS
1/0 CLOCK
CS
Self-Test
Reference
I
System Clock,
Control LogiC,
and 1/0
Counters
19
EOC
17
~
18
I
15
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
INPUT CIRCUIT IMPEDANCE DURiNG HOLD MODE
1 kOTYP
AO-A10~
I
AO-A10~·
CI= 60 pF TYP
(equivalent Input
capacitance)
~TEXAS
INSTRUMENTS .
2-192
POST OFFICE BOX 655303 • DAUAS; TEXAS 75265
~ 5 MOTYP
.
I
"
TLV1543C,TLV1543M
3.3-V 10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SE·RIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C - DECEMBER 1992 - REVISED MARCH 1995
Terminal Functions
TERMINAL
I/O
DESCRIPTION
17
I
Serial address. A 4-bit serial address selects the desired analog input or test voltage that is to be converted
next. The address data is presented with the MSB first and is shifted in on the first four rising edges of I/O
CLOCK. After the four address bits have been read into the address register, ADDRESS is ignored for the
remainder of the current conversion period.
1-9,11,
12
I
Analog signal. The 11 analog inputs are applied to AO-Al0 and are internally multiplexed. The driving
source impedance should be less than or equal to 1 kO.
CS
15
I
Chip select. A high-to-Iowtransition on CS resets the internal counters and controls and enables DATA OUT,
ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system
clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup time plus two falling edges
of the internal system clock.
DATA OUT
16
a
The 3-state serial output for the AID conversion result. DATA OUT is in the high-impedance state when CS
is high and active when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance
state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The
nextfalling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next most significant
bit, and the remaining bits are shifted out In order with the LSB appearing on the ninth falling edge of I/O
CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low logic level so that serial
interface data transfers of more than ten clocks produce zeroes as the unused LSBs.
EOC
19
a
End of conversion. EOC goes from a high- to a low-logic level on the trailing edge of the tenth I/O CLOCK
and remains low until the conversion is complete and data are ready for transfer.
GND
10
I
The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are
with respect to GND.
I/O CLOCK
18.
I
Input/output clock. I/O CLOCK receives the serial I/O CLOCK input and performs the following four
functions:
1) It clocks the four input address bits into the address register on the first four rising edges of I/O
CLOCK with the multiplex address available after the fourth rising edge.
2) On the fourth falling edge of I/O CLOCK,the analog input voltage on the selected multiplex input begins
charging the capaCitor array and continues to do so until the tenth falling edge of Ifa CLOCK.
3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.
4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.
REF+
14
I
The upper reference voltage value (nominally VCC) is applied to REF +. The maximum input voltage range
is determined by the difference between the voltage applied to REF + and the voltage applied to the REFterminal.
REF-
13
I
The lower reference voltage value (nominally ground) is applied to REF-.
VCC
20
I
POSitive supply voltage
NAME
ADDRESS
AO-Al0
NO.
detailed description
With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT
is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins
with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state.
The host then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to 1/0 CLOCK.
During this transfer, the host serial interface also receives the previous conversion result from DATA OUT. I/O
CLOCK receives an input sequence that is between 10 and 16 clocks long from the host. The first four I/O clocks
load the address register with the 4-bit address on ADDRESS selecting the desired analog channel and the next
six clocks providing the control timing for sampling the analog input.
~TEXAS
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2-193
TLV1543C,TLV1543M
3.3-V 1()'BIT ANALOG·TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C - DECEMBER 1992 - REVISED MARCH 1995
detailed description (continued)
There are six basic serial interface timing modes that can be used with the device. These modes are determined
by the speed of 1/0 CLOCK and the operation of CS as shown in Table 1. These modes are (1) a fast mode with
a 1O-Clock transfer and CS inactive (high) between conversion cycles, (2) a fast mode with a 1O-clock transfer
and CS active (low) continuously, (3) a fast mode with an 11-to 16-c10ck transfer and CS inactive (high) between
conversion cycles, (4) a fast mode with a 16-bit transfer and CS active (low) continuously, (5) a slow mode with
an 11- to 16-clock transfer andCS inactive (high) between conversion cycles, and (6) a slow mode with a
16-clock transfer and CS active (low) continuously.
The MSB of the previous conversion appears o~ DATA OUT on the falling edge of CS in mode 1, mode 3, and
mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the 16th clock falling edge in mode 6.
The remaining nine bits are shifted out on the next nine falling edges of 1/0 CLOCK. Ten bits of data are
transmitted to the host through DATA OUT. The number of serial clock pulses used also depends on the mode
of operation, but aminimum often clock pulses is required for conversion to begin. On the 10th clock falling edge,
the EOC output goes low and returns to the high logic level when conversion is complete and the result can be
read by the host. On the 10th clock falling edge, the internal logic takes DATA OUT low to ensure that the
remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks long.
Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that
can be used, and the timing edge on which the MSB of the previous conversion appears at the output.
Table 1. Mode Operation
cs
MODES
Fast Modes
Slow Modes
Mode 1
High between conversion cycles
Mode 2
.Mode 3
Low continuously
High between conversion cycles
NO. OF
110 CLOCKS
Mode 4 Low continuously
High between conversion cycles
ModeS
Mode 6 Low continuously
t These edges also initiate serlal-interfaca communication.
:I: No more than 16 clocks should be used.
MSS AT DATA ourt
TIMING
DIAGRAM
10
10
11 to 16:1:
16:1:
CS falling edge
Figure 9
EOC rising edge
CS falling edge
Figure 10
Figure 11
EOC rising edge
Figure 12
11 to 16:1:
16:1:
CS falling edge
16th clock falling edge
Figure 13
Figure 14
fast modes
The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is
completed. With a 1O-Clock serial transfer, the device can only run in a fast mode since a conversion does not
begin until the falling edge of the 10th I/O CLOCK.
mode 1: fast mode, CS Inactive (hIgh) between conversion cycles, 1o-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The
fal!!!!g edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge
of ~ ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.
Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling
edges of the internal system clock.
mode 2: fast mode, 'OS active (low) continuously, 1~/ock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After
the initial conversion cycle, CS is held active (low) for subsequent conversions; the riSing edge of EOC then
begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous
conversion to appear immediately on this output.
~TEXAS
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INSTRUMENTS
POST OFfiCE BOX 665303 e. DAUAS. TEXAS 75265
TLY1543C,TLY1543M
3.3-Y 10-BIT ANALOG-TO-DIGITAL CONYERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C - DECEMBER 1992 - REVISED MARCH 1995
mode 3: fast mode, CS Inactive (high) between conversion cycles, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time
plus two falling edges of the internal system clock.
mode 4: fast mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of
EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the
previous conversion to appear immediately on this output.
slow modes
In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow
mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must occur
before the conversion period is complete; otherwise, the device loses synchronization with the host serial
interface, and CS has to be toggled to initialize the system. The eleventh rising edge of the 1/0 CLOCK must
occur within 9.5 J.lS after the tenth I/O clock falling edge.
mode 5: slow mode, CS Inactive (high) between conversion cycles, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time
plus two falling edges of the internal system clock.
mode 6: slow mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of
the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the
MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next
16-clock transfer initiated by the serial interface.
address bits
The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal
(MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address
selects one of 14 inputs (11 analog inputs or 3 internal test inputs).
analog inputs and test modes
The 11 analog inputs and the 3 internal test inputs are selected by the 14-channel multiplexer according to the
input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce
input-to-input noise injection resulting from channel switching.
Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six
I/O CLOCK periods. The sample is held on the falling edge of the tenth 1/0 CLOCK. The three test inputs are
applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs.
~TEXAS
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POST OFFICE BOX 665303 • DALLAS. TEXAS 75265
2-195
-TLV1543C,TLV1543M
3.3·V 1()'BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C - DECEMBER 1992 - REVISED ,MARCH 1995
Table 2. Analog-Channel-Select Address
ANALOG INPUT
SELECTED
VALUE SHIFTED INTO
ADDRESS INPUT
BINARY
HEX
AO
0000
0
A1
0001
1
A2
0010
2
A3
0011
3
A4
0100
A5
0101
4
5'
A6
0110
6
A7
0111
7
A8
1000
8
A9
1001
9
A10
1010
A
Table 3. Test-Mode-Select Address
INTERNAL SELF·TEST
VOLTAGE SELECTEDt
Vref+ - Vref2
VALUE SHIFTED INTO
ADDRESS INPUT
BINARY
HEX
1011
B
OUTPUT RESULT (HExF
200
1100
C
000
Vref3FF
1101
0
Vref+
t Vref+isthevoltageappliecitothe REF + input, andVref_isthevoltageappliecftothe REFinput.
:j: The output results shown are the ideal values and vary with the reference stability and with
internal offsets.
converter and analog Input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capaCitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the Se switch and aU Sr switches simultaneously.
This action charges aU the capacitors to the input voltage.
In the next phase of the conversion process, aU Sr and Sc switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-)
voltage. In the switching sequence, ten capacitors are examined separately until aU ten bits are identified and
the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks
at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of aU the other capacitors on the ladder are switched to REF-. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half the Vee voltage), a bit 0 is
placed in the output register and the 512-weight capacitor is switched to REF-. If the voltage at the summing
node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the 512-weight
capacitor remains connected to REF + through the remainder of the successive-approximation process. The
process is repeated for the 256-weight capaCitor, the 128-weight capacitor, and so forth down the line until aU
bits are counted.
With each step of the successive-approximation process, the initial charge is redistributed among the
capaCitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.
~1ExAs
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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1543C, TLV1543M
3.3·V 10-81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C - DECEMBER 1992 - REVISED MARCH 1995
converter and analog Input (continued)
Se
Threshold
Detector
25J 1281
'-;:,t~t;:;t;;t~t~t~t~f ~T
51~
'j
18
To Output
Latches
REF-~_;EF- ~_:EF-~_;EF-~_;EF-~_s~EF-~_;EF-~_:EF-~_ REF-~_
.j j j
\J
j j j j j
Figure 1. Simplified Model of the Successive-Approximation System
chip-select operation
The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.
A high-to-Iow transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the contents of the output data register remain at the previous conversion result).
Exercise care to prevent CS from being taken low close to completion of conversion because the output data
can be corrupted.
reference voltage Inputs
There are two reference inputs used with these devices: REF + and REF-. These voltage values establish the
upper and lower limits of the analog input to produce a full-scale and zero-scale reading respectively. The values
of REF+, REF-, and the analog input should not exceed the positive supply or be lower than GND consistent
with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to
or higher than REF+ and at zero when the input Signal is equal to or lower than REF-.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1): TLV1543C ................................. -0.5 V to 6.5 V
TLV1543M ................................... -0.5 V to 6 V
Input voltage range, VI (any input) ............................................ -0.3 V to Vee + 0.3 V
Output voltage range, Vo .........................................•......... -0.3 V to Vee + 0.3 V
Positive reference voltage, Vref+ ...................................................... Vee + 0.1 V
Negative reference voltage, Vref- .......................................................... -0.1 V
Peak input current (any input) ........................................................... ±20 mA
Peak total input current (all inputs) ....................................................... ±30 mA
Operating free-air temperature range, TA: TLV1543C ................................... O°C to 70°C
TLV1543M ............................... -55°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ............................ 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF - and GND wired together (unless otherwise noted).
~TEXAS
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TLV1543C,TLV1543M
3.3-V 1()'BIT'ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C., DECEMBER 1992 - REVISED MARCH 1995
recommended operating conditions
MIN
Supply voltage, Vee
TLV1543C
3
TLV1543M
3
Positive reference voltage, Vref+ (see Note 2)
2.5
Differential reference voltage, Vref+ - Vref- (see Note 2)
Analog Input voltage (see Note 2)
Low-level control Input voltage, VIL
MAX
5.5
3.6
TLV1543C
VCC- 3 V to 5.5 V
TLV1543M
TLV1543C
VCC - 3 V to 3.6 V
VCC -3 Vto5.5V
TLV1543M
VCCa3 Vto3.6V
Setup time, address bits at data input before I/O CLOCKi,lsu(A) (see Figure 4)
0
2
VCC
UNIT
V
V
V
VCC
0
Negative reference voltage, Vref- (see Note 2)
High-level control input voltage, VIH
NOM
3.3
3.3
V
VCC+O.2
V
Vee
V
V
2
V
0.6
V
0.8
V
100
ns
Hold time, eddress bits after I/O CLOCKt, tl1{f.l(see Figure 4)
0
ns
Hold time, CS low after last I/O CLOCKJ.., th(CS)
0
ns
Setup time, CS low before clocking in first address bit,lsu(CS) (see Note 3)
Clock frequency at I/O CLOCK (see Note 4)
TLC1543C
TLC1543M
1.425
1.1
0
2.1
Pulse duration, I/O CLOCK high,!wHClIO)
190
Pulse duration, I/O CLOCK low, twL(I!O)
190
Transition time, I/O CLOCK, tt(ltO) (see Note 5)
ns
10
ITLV1543C
TLV1543M
0
-55
MHz
ns',
1
Transition time, ADDRESS and CS, tteCS)
Operating free-alr temperature" TA
JIS
0
70
125
JIS
JIS
·C
NOTES: 2. Analog Input voltages greater than that applied to REF+ convert as all ones (1111111111), while inPut voltages less than that applied
to REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref + - Vref-); however,
the electrical specifications are no longer applicable.
3. To minimize errors caused by noise at CS, the interPial circuitry waits for a setup time plus two falling edges of the intemal system
clock after CSJ.. before responding to control input signals. No attempt should be made to clock in an address until the minimum CS
setup time has elapsed.
4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (S 2 V), at least one I/O clock rising edge ~ 2 V) must occur within
9.5 JIS.
5. This Is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 JIS for remote data-acquisition applications
where the sensor and the AID converter are placed several feet away from the controlling microprocessor.
~lExAs "
2-198
INSTRUMENTS
'POST OFFICE BOX 665303 • DALLAS. TEXAS 75266
TLY1543C, TLY1543M
3.3-Y 10-81T ANALOG-TO-DIGITAL CONYERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C - DECEMBER 1992 - REVISED MARCH 1995
electrical characteristics over recommended operating free-air temperature range,
Vee = Vref+ = 3 V to 5.5 V, 1/0 CLOCK frequency = 1.1 MHz for the TLV1543C,
Vee = Vref+ = 3 V to 3.6 V, 1/0 CLOCK frequency = 2.1 MHz forthe TLV1543M (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLVl543e
VOH
High-level output
voltage
TLVl543M
TLVl543e
VOL
Low-level output
voltage
TLV1543M
IOH--l.6 mA
Vee = 3 Vto 5.5 V.
IOH =20 IIA
Vee- 3V,
IOH --1.6 mA
Vee - 3 Vt03.6 V,
IOH .20 IIA
Vee=3V.
IOL= 1.6mA
V
Vee-0.1
V
2.4
V
V
Vee-0.1
0.4
V
0.1
V
0.4
V
Vee. 3 Vt03.6 V,
IOL - 20 IIA
0.1
V
10
-10
VO=O,
CS"atVee
IIH
High-level input current
VI-Vee
IlL
Low-level input current
VI-O
ICC
Operating supply current
CSatOV
Input capacitance,
Control inputs
UNIT
IOL=1.6mA
Vo-Vee.
Ci
MAX
IOL-20 IIA
Off-state (high-impedance-state)
output current
Input capacitance,
Analog Inputs
TYPt
2.4
Vee = 3 Vt05.5 V,
IOZ
Maximum static analog reference
current Into REF+
MIN
Vce=3V.
CS"atVCe
Selected channel leakage current
t
Vce a3V•
0.005
2.5
-0.005
-2.5
(lA
0.8
2.5
mA
Selected channel at Vee. UnseJected channel at 0 V
1
Selected channel at 0 V,
UnseJected channel at Vec
-1
Vref+=VCC,
Vref_=GND
10
TLVl543C
7
TLVl543M
7
TLVl543e
5
TLVl543M
All typical values are at Vee - 5 V, TA _ 25°C.
IIA
5
55
15
(lA
(lA
(lA
pF
pF
~TEXAS
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TLV1543C, TLV1543M
3.3~V 19-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11,ANALOG INPUTS
SLAS072C - DECEMBER 1992 - REVISED MARCH 1995
operating characteristics over recommended operating free-air temperature range,
vee Vref+ 3 V to 5.5 V, 1/0 CLOCK frequency 1.1 MHz for the TLV1543C,
Vee Vref+ 3 V to 3.6 V, 110 CLOCK frequency 2.1 MHz for the TLV1543M
=
=
=
=
=
=
PARAMETER
TEST CONDITIONS
MIN
TYPt
Linearity error (see Note 6)
UNIT
±1
LSB
Zero error (see Note 7)
See Note 2
±1
LSB
Full-scale error (see Note 7)
See Note 2
±1
LSB
±1
LSB
21
IJS
Total unadjusted error (see NoteS)
ADDRESS _ 1011
Self-test output code (see Table 3 and Note 9)
!conv
MAX
Conversion time
512
ADDRESS = 1100
0
ADDRESS = 1101
1023
See Figures 9,-14
Ie
Total cycle time (access, sample, and conversion)
See Figures 9 -14
and Note 10
21
+101/0
CLOCK
periods
tacq
Channel acquisition time (sample)
See Figures 9-14
and Note 10
6
tv
Valid time, DATA OUT remains valid after 1/0 CLOCK,!,
See Figure 6
!deliO-DATA)
Delay time, 1/0 CLOCK,!, to DATA OUT valid
See Figure 6
!dn/o-EoCl
Delay time, tenth I/O CLOCK,!, to EOC'!'
See Figure 7
!d(EOC-DATA)
Delay time, EOCt to DATA OUT (MSB)
See FigureS
tPZH, tPZL
Enable time, CS,!, to DATA OUT (MSB driven)
tPHZ, tPLZ
Disable time, cst to DATA OUT (high impedance)
tr(EOC)
tf(EOC)
10
IJS
1/0
CLOCK
periods
ns
240
70
ns
240
ns
100
ns
See Figure 3
1.3
See Figure 3
150
IJS
ns
Rise time, EOC
See FigureS
300
ns
Fall time, EOC
See Figure 7
300
ns
tr(bus)
Rise time, data bus
See Figure 6
300
ns
tf(bus)
Fall time, data bus
See Figure 6,
300
ns
!d(I/O-CS)
Delay time, tenth 1/0 CLOCK,!, to CS,!, to abort conversion
(see Note 11)
9
IJS
t All typical values are at TA s 25·C.
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111,111), while input voltages less than that applied
to REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref + - Vref-); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the ND transfer characteristics.
7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1111111111 and the converted output for full-scale input voltage.
S. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input address and the output codes are expressed in positive logic.
10. 1/0 CLOCK period = 1/(1/0 CLOCK frequency) (see Figure 6).
'
11. Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock
(1.425 /IS) after the transition.
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POST OFRCE sox '656303 • DALLAS. TEXAS 75265
TLY1543C,TLY1543M
3.3-Y 1()"BIT ANALOG-TO-DIGITAL CONYERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C - DECEMBER 1992 - REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION
Vee
Test Point
Vcc
Test Point
'=~8~
,=~~~
DATA OUT-_...............-IoIII--...
EOC
Figure 2. Load Circuits
I.
Address
~ Valid
l:S
~\;~V_IL_ _ _ _
2V~1
/!
tpZH.tpZL
D~~~
~
I~
~i
ADDRESS
~
~ 'PHz. tpLZ
fau(A)
,:
~_:-«
___
~VIL
fau(CS)
110 CLOCK
I14
,
X=
~I "~
Ii1(A)
! l:
110 CLOCK
VIL¥
Figure 3. DATA OUT to HI-Z Voltage Waveforms
l:S
=X !I~
-+,
Figure 4. ADDRESS Setup Voltage Waveforms
',',
-l+1
2r
'..
,
I
~I
th(CS)
. __ i/;;\
~I __.
--!JJ,J CI~ y~ C~k ~
Figure 5. ~ and 110 CLOCK Voltage Waveforms
~1ExAs
INSTRUMENTS
POST OFFICE BOX estl303 • DAUAS. TEXAS 75265
2-201
-TLV1543C,TLV1543M
3.3-V10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C - DECEMBER 1992 - REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION
tt(I/O)
I/OCLOCK
---.I,
'+-1I I+,
I
2V'
VIL
tt(I/O)
.2V
VIL
VIL
~ I/O CLOCK perlOd--.1
!d(l/o-DATA) ~,
tv
DATA OUT
--14-+1 I
2.4 V
____
{J,,
r
2.4 V
o_.4_v~)\~-0_.4_V------------~
tr(bus). tf(bus)
Figure 6. DATA OUT and 110 CLOCK Voltage Waveforms
~Oth
I/O CLOCK- - . //
Clock \
!d(l/o-EOC)
1'0
_v_IL
___________
,
~
I
I
EOC
2.4V
!XI
I
0.4 V
I....;.;.;,.~-
-+1 I+-
tf(EOC)
Figure 7.
EOC
I/O CLOCK and EOC Voltage Waveforms
-1 I+IJe
~!
tr(EOC)
2.4V
r
.,
('
--<_
DATA OUT _ _ _ _ _ _ _ _
!d(EOc.DATA)
2.4 V
~0.4.;..;V;....------:.-- Valid MSB
---+
Figure 8. EOC and DATA OUT Voltage Waveforms
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLY1543C,TLY1543M
3.3-Y 10-BIT ANALOG-TO-DIGITAL CONYERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C - DECEMBER 1992 - REVISED MARCH 1995
(~N~~~--------------------------------------------~
110
..
I
~ ~~~4-JrlL
I
'
CLOCK_....
' .......
------~
,
I
I,
DATA
OUT
HI-ZState
ADDRESS
B3
B2
B1
BO
LSB
MSB
J~
Initialize
I
,---------~~
,
I
LSB.'
EOC
~''---
-~~
-~~
I
~i__~r~'
Shift In New Multiplexer Addreae,
,
,..r------~.I
Simultaneously Shift Out Previous - - - - -..........
Conversion Value
AID Conversion
Interval
Initialize
Figure 9. Timing for 1O-Clock Transfer Using CS
CS ~
I
't--(~NotaA) j
--------------------------------------------------------~j.____
Must be High on Po_r Up
110
CLOCK
--hI I+-
'----~~
'
~
OUTN
DATA
'I"
AI
A_Cycle B
.AB
-~---
----~
A7
Low Level
,
~
I
MSB
~
,
ADDRESS
I
EOC
Hr--
Shift In New Multiplexer Addreae,
101--..,.----- Simultaneously Shift Out Previous
--------;~------+f
Conversion value
Initialize
AID Conversion
Inlarval
Initialize
Figure 10. Timing for 10-Clock Transfer Not Using CS
NOTE A: To minimize errors caused by noise at es, the intemal circuitry waits for a setup time plus two falling edges of the internal system ciock
alter CS.J, before responding to control Input signals. No attempt shoilld ba made to clock in an address until the minimum CS setup
time has elapsed.
~TEXAS
INSlRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75266
2-203
TLV1543C,TLV1543M
.
3.3·V 10·BIT ANALOG·TO·DIGITALCONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C-DECEMBER 1992- REVISED MARCH 1995
See Note C
~'~
~~~
_________________________I~HI~IIII~~____
~
I
110
CLOCK
I
11
1"::1·· ~YA!
I
I
Low
I ,Le:V=8:..1..J.Z2::;;:H~I....Z...,~
DATA
OUT
-------------LS-B+~I
I
S~
1
ADDRESS
B3
B2
BO
1
LSB
I
B1
MSB
S~
~--------------------------------------~I
EOC
111
~18~~ 1 L..
J~
Initialize
r~
!
I
I
Shift In New Multiplexer Address,
Simuiteneously Shift Out Previous - - - - - -..~·~I..I__~--___.~I
Conversion Value
AID Conversion
Interval
Initialize
Figure 11. Timing for 11· to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Convel'$lon)
~
(S88
-r--
Must be High on Power Up
Note A) ~1-
1/0
CLOCK
I
~
r-
I
DATA {
OUT
.1..
I
ADDRESS
II
Access Cycle B - M - - - A8
A7
Low Level
A8
~I--------'l
MSB
LSBI
MSB
I
I
.~
I
I
EOC
A9
It
1
~
I
I
77Nv7.
f~'"'
I
~'l-S----------------i!,jShift In New Multiplexer Address,
I
Simultaneously Shift Out Previous ---------.~141
..-- AID Conversion
Interval
Conversion Value
Initialize
-1.
Initialize
Figure 12. Timing for 16-Clock Transfer Not UsingCS (Serial Transfer Interval Shorter Than Conversion)
NOTES: A. To minimize errors caused by noise at CS, the intemal circuitry waits for a set uptime plus two falling edges of the internal system
clock after CS.J. before responding to control Input signals. No attempt should be made to clock in an address until the minimum CS
setup time has elapsed.
.
B. The first 1/0 CLOCK must occur after the rising edge of EOC.
C. A low-te-high transition of CS disables ADDRESS and the 1/0 CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock.
~1ExAs '
2-204
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 752155
TLV1543C,TLV1543M
3.3-V 10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C - DECEMBER 1992 - REVISED MARCH 1995
CS~
111111111
(see Note A)
I
I
I
1/0
11
_+---!
CLOCK
rj~,--_
I
I
I
DATA
OUT
r;61
r?~!
L~
HI-ZState ~
~
I
I
I
B3
B2
B1
MSB
J~
o
E C
.
BO
LSB
I
I
I
~~
~~
~IIIIIIII
',';
I
Shift In New Multiplexer Address,
;
I
Simultaneously Shift Out Previous ---'-----.~i4I
..- - -...
~1
Conversion Value
AID Conversion
Initialize
L..
Level
I
ADDRESS
Ii'1
r..~~
SeeNoteB
I
I
1-1
Interval
I
I
Initialize
Figure 13. Timing for 11· to 16-Clock Transfer USing CS (Serial Transfer Interval Longer Than Conversion)
II
II
~r--f1I
See Note B
LowLe~el
I
I
II
I
I
Shift In New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Initialize
See Note C
~
I
I
~
C3
"
AID Conversion
Interval
Figure 14. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Longer Than Conversion)
NOTES: A. To minimize errors Caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system
clock after CSJ. before responding to control input signals. No attempt should be made to clock in an address until the minimum chip
CS setup time has elapsed.
B. The eleventh rising edge of the 1/0 CLOCK sequence must occur before the conversion is complete to prevent lOSing serial interface
synchronization.
C. The 1/0 CLOCK sequence is exactly 16 clock pulses long.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 6S5303 • DAUAS. TEXAS 75265
2-205
TLY1543C,TLY1543M
3.3-Y 1()"BIT ANALOG-TO-DIGITAL CONYERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C - DECEMBER 1992 - REVISED MARCH 1995
APPLICATION INFORMATION
1111111111
I
I
See Notes A and B
/
1111111110
~ rli \
II II
~
1111111101
~'S
/'1::
1000000001
.& 1000000000
:::I
VZT =Vzs + 1/2 LSB
0
7
0111111111
6
••
•
I-VZS
0000000010
0000000001
0000000000
~.
)~ V
••
•
;m
~
/
/
./
VFT =VFS -1/2 LSB
V
,/
0.0046 0.0096
2
I
I
/'
cO
•••
VI- Analog Input Voltage - V
J
4.9056
!
511
I
I
2.4624
•••
512
Ii
Ii
2.4576
1021
513
I
I
/'
V
2.4528
1022
'/!
./'L.'
•••
1023
VFS
./ ,./
1/ ~
~~
o i
.,~
/
~
~
V
,
•
••
o
~ 4.9104 4.9152
NOTES: A. This curve is based on the assumption that Vref + and Vref- have been adjusted so that the voltage at the trensition from digital 0
to 1 (VZT) is 0.0024 V and the transition to full scale (VFT) is 4.908 V. 1 LSB - 4.8 mY.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (Vzsl is
the step whose nominal midstep value equals zero.
Figure 1S.ldeal Conversion Characteristics
TLV1543
1
2
3
4
5
Analog
Inputa
6
7
8
9
11
12
~
AO
15
18
1/0 CLOCK
17
ADDRESS
A1
A2
Procesaor
A3
A4
DATA OUT
A5
EOC
16
19
A6
A7
A8
REF+
A9
A10
REF-
14
3-V DC Regulated
13
GND
110
To Source
Ground
I
.1
Figure 16. Serial Interface
~TEXAS
2-206
INSTRUMENTS
POST OFFICE BOX 1!55303 • DAllAS, TEXAS 75265
Control
Circuit
TLY154SC, TLY1543M
S.S-Y 10-81T ANALOG-TO-DIGITAL CONYERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C - DECEMBER 1992 - REVISED MARCH 1995
APPLICATION INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 17, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
Vc = Vs (l-e -t c/RtCI )
(1 )
where
Rt=Rs+rj
The final voltage to 1/2 LSB is given by
Vc (1/2 LSB)
=Vs -
(2)
(Vs/2048)
Equating equation 1 to equation 2 and solving for time to gives
Vs -(Vsl2048)
=Vs ( 1-e -t C 1RtC.)I
(3)
and
to (112 LSB) = Rt x Cj x In(2048)
(4)
Therefore, with the values given the time for the analog input signal to settle is
to (1/2 LSB) =(Rs + 1 kn) x 60 pF x In(2048)
(5)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet ..
Rs
I
I
I
I
VI
• TLV1543
I'J
VS~VC
I 1kOMAX
II
I
CI
50 pF MAX
VI = Input Voltage at AO-A 10
VS= External Driving Source Voltage
Rs = Source Reelstance
I'J = Input Reelstance
CI = Input capacitance
t Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.
Figure 17. Equivalent Input Circuit Including the Driving Source
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
2-207
2-208
TLV1549C, TLV15491, TLV1549M
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
c - JANUARY 1993 -
• 3.3-V Supply Operation
• 1o-Bit-Resolutlon Analog-ta-Digltal
Converter (ADC)
• Inherent Sample and Hold Function
• Total Unadjusted Error ••• ±1 LSB Max
• On-Chip System Clock
• Terminal Compatible With TLC1549 and
TLC1549x
• Application Report Avallablet
• CMOS Technology
REVISED MARCH 1995
D, JG, OR P PACKAGE
(TOP VIEW)
Vee
REF+D8
ANALOG IN 2
7
REF- 3
6
GND 4
5
I/O CLOCK
DATA OUT
CS
FKPACKAGE
(TOP VIEW)
+
otb080
za:z::>z
description
NC
ANALOG IN
NC
REFNC
The TLV1549C, TLV15491, and TLV1549M are
10-bit,
switched-capacitor,
successiveapproximation, analog-to-digital converters. The
devices have two digital inputs and a 3-state
output [chip select (CS), input-output clock (1/0
CLOCK), and data output (DATA OUT)] that
provide a three-wire interface to the serial port of
a host processor.
4
5
6
7
8
3
2 1 2019
18
17
16
15
14
9 1011 1213
NC
I/O CLOCK
NC
DATA OUT
NC
00 01Cf) 0
zzzoz
(!)
The sample-and-hold function is automatic. The
converter incorporated in the device features
differential high-impedance reference inputs that
facilitate ratiometric conversion, scaling, and
isolation of analog circuitry from logiC and supply
noise. A switched-capacitor design allows lowerror conversion over the full operating free-air
temperature range.
NC - No internal connection
The TLV1549C is. characterized for operation from O°C to 70°C. The TLV15491 is characterized for operation
from -40°C to 85°C. The TLV1549M is characterized for operation over the full military temperature range of
-55°C to 125°C.
TA
O·Cto 70·C
-40·C to 85·C
-55·C to 125·C
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
CHIP CARRIER
CERAMIC DIP
(D)
(FK)
(JG)
TLV1549CD
TLV15491D
TLV1549MFK
TLV1549MJG
-
PLASTIC DIP
(P)
TLV1549CP
TLV1549IP
-
t Interfacing the TLV1549 1Q-Blt Serial-Out ADC to Popular 3.3-V Microcontrollers (SLAA005)
~1ExAs
INSTRUMENTS
POST OFFICE
eox 655303 •
DAUAS. TEXAS 75255
Copyright © 1995, Texas Instruments Incorporated
2-209
TLV1549C, TLV15491, TLV1549M
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
'
SLAS071 C - JANUARY 1993 - REVISED MARCH 1995
typical equivalent inputs
INPUT CIRCUIT IMPEDAJ\ICE DURING HOLD MODE
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
1 kOTYP
ANALOGIN~
I
ANALOGIN~
J
CI=60pFTYP
(equivalent Input
capacitance)
5 MOTYP
functional block diagram
REF+
I1
REF-
I3
10-Blt
Analog-to-Dlgltal
Converter
(awltched capacitors)
4
10
ANALOG IN -
2
Output
Data
Register
Sample and
Hold
10
~
10-to-1 Data
8
SelectOr and I-- DATA OUT
Driver
4
4
"- System Clock,
Control Logic,
and 1/0
Counters
I/O CLOCK
CS
7
~
5
Terminal numbers shown are for the D, JG, and P packages only.
~TEXAS
2-210
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
TLV1549C, TLV15491, TLV1549M
10-81T ANALOG-TO-DIGITAL CONVERTERS
.
WITH SERIAL CONTROL
SLAS071 C- JANUARY 1993 - REVISED MARCH 1996
Terminal Functions
TERMINAL
I/O
DESCRIPTION
2
I
Analog Input. The driving source impedance should be S 1 kn The extemal driving source to ANALOG IN should
have a current capability;::: 10 mAo
CS
5
I
Chip select. A high-to-Iow transition on CS resets the internal counters and controls and enables DATA OUT and
110 CLOCK within a maximum of a setup time plus two falling edges of the intemal system clock. A low-to-high
transition disables 110 CLOCK within a setup time plus two falling edges of the internal system clock.
DATA OUT
6
0
This 3-state serial output for the AID conversion result is in the high-impedance state when CS is high and active
when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance state and is driven to
the logic level corresponding tothe MSB value of the previous conversion result. The next falling edge of 110 CLOCK
drives DATA OUT to the logic level corresponding to the next most significant bit, and the remaining bits are shifted
out in order with the LSB appearing on the ninth falling edge of 110 CLOCK. On the tenth falling edge of 110 CLOCK,
DATA OUT is driven to a low logic level.so that serial interface data transfers of more than ten clocks produce zeroes
as the unused LSBs.
GND
4
I
The ground return for internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.
110 CLOCK
7
I
The input/output clock receives the serial 110 CLOCK input and performs the following three functions:
1) On the third falling edge of 110 CLOCK, the analog input voltage begins charging the capacitor array and
continues to do so until the tenth falling edge of 110 CLOCK.
2) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.
3) It trensfers control of the conversion to the internal state controller on the falling edge of the tenth clock.
REF+
1
I
The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range is
determined by the difference between the voltage applied to REF+ and the voltage applied to REF-.
REF-
3
8
I
The lower reference voltage value (nominally ground) is applied to this REF-.
I
Positive supply voltage
NAME
NO.
ANALOG IN
VCC
detailed description
With chip select (CS) inactive (high), the 1/0 CLOCK input is initially disabled and DATA OUT is in the highimpedance state. When the serial interface takes CS active (low), the conversion sequence begins with the
enabling of 1/0 CLOCK and the removal of DATA OUT from the high-impedance state. The serial interface then
provides the 1/0 CLOCK sequence to 1/0 CLOCK and receives the previous conversion result from DATA OUT.
1/0 CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface.
The first ten 1/0 clocks provide the control timing for sampling the analog input.
There are six basic serial interface timing modes that can be used with the TLV1549. These modes are
determined by the speed of 1/0 CLOCK and the operation of CS as shown in Table 1. These modes are:
(1) a fast mode with a 1O-clock transfer and CS inactive (high) between transfers, (2) a fast mode with a 10-clock
transfer and CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high)
between transfers, (4) a fast mode with a 16-bit transfer and CS active (low) continuously, (5) a slow mode with
an 11-to 16-clock transfer and CS inactive (high) between transfers, and (6) a slow mode with a 16-clock transfer
and CS active (low) continuously.
The MSB of the previous conversion appears on DATA OUT on the falling edge of CS in mode 1, mode 3, and
mode 5, within 21 IlS from the falling edge of the tenth 1/0 CLOCK in mode 2 and mode 4, and following the
16th clock falling edge in mode 6. The remaining nine bits are shifted out on the next nine falling edges of the
1/0 CLOCK. Ten bits of data are transmitted to the host serial interface through DATA OUT. The number of serial
clock pulses used also depends on the mode of operation, but a minimum of ten clock pulses is required for
conversion to begin. On the tenth clock falling edge, the internal logic takes DATA OUT low to ensure that the
remaining bit values are zero if the 1/0 CLOCK transfer is more than ten clocks long.
Table 1 lists the operational modes with respect to the state of CS, the number of 1/0 serial transfer clocks that
can be used, and the timing on which the MSB of the previous conversion appears at the output.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-211
TLV1549C,'TLV15491, TLV1549M
1O-BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C- JANUARY 1993 - REVISED MARCH 1995
Table 1. Mode Operation
MODES
Fast Modes
Slow Modes
CS
NO. OF
IJOCLOCKS
MSB AT DATA OUTt
TIMING
DIAGRAM
Model
High between conversion cycles
10
CS falling edge
Figure 6
Mode 2
Low continuously
10
Within 21
Figure 7
Mode 3
High between conversion cycles
Mode 4
Low continuously
Mode 5
High between conversion cycles
11 to 16:1:
16:1:
Mode 6 Low continuously
, .
.. senal-Interface communication.
t This timing also .Initiates
:I: No more than 16 clocks should be used.
11 to 16:1:
16:1:
jJ.$
CS falling edge
Figure 8
Within21
Figure 9
jJ.$
CS falling edge
Figure 10
16th clock falling edge
Figure 11
All the modes require a minimum period of 21 ~ after the falling edge of the tenth 1/0 CLOCK before a new
transfer sequence can begin. During a serial 1/0 CLOCK data transfer, CS must be active (low) so that the I/O
CLOCK input is enabled. When CS is toggled between data transfers (modes 1,3, and 5), the transitions at CS
are recognized as valid only if the level is maintained for a minimum period of 1.425 ~ after the transition. If
the transfer is more than ten 1/0 clocks (modes 3,4,5, and 6), the rising edge of the eleventh clock must occur
within 9.5 ~ after the falling edge of the tenth I/O CLOCK; otherwise, the device could lose synchronization with
the host serial interface and CS has to be toggled to restore proper operation.
fast modes
The device is in a fast mode when the serial 110 CLOCK data transfer is completed within 21 ~ from the falling
edge of the tenth 1/0 CLOCK. With a 10-clock serial transfer, the device can only run in a fast mode.
mode 1: fast mode, CS Inactive (high) between transfers, 1O-Clock transfer
In this mode, CS is inactive (high) between seriaII/O-CLOCK transfers and each transfer is ten clocks long. The
fal!!!!g edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge
of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.
Also, the rising edge of CS disables 110 CLOCK within a setup time plus two falling edges of the internal system
clock.
mode 2: fast mode, CS active (low) continuously, 1()..clock transfer
In this mode, CS is active (low) between seriaIIlO-CLOCK transfers and each transfer is ten clocks long. After
the initial conversion cycle, CS is held active (low) for subsequent conversions. Within 21 ~ after the falling edge
of the tenth 110 CLOCK, the MSB of the previous conversion appears at DATA OUT.
mode 3: fast mode, CS inactive (high) between transfers, 11- to 16-clock transfer
In this mode, CS is inactive (high) between seriaIIlO-CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequenc~ returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables 110 CLOCK within a setup time plus two falling edges of the
internal system clock.
mode 4: fast mode, CS active (low) continuously, 16-clocktransfer
In this mode, CSis active (low) between seriaIIlO-CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. Within 21 ~ after
the falling edge of the tenth 110 CLOCK, the MSB of the previous conversion appears at DATA OUT.
slow modes
In a slow mode, the serial 110 CLOCK data transfer is completed after 21 ~ from the falling edge of the tenth
110 CLOCK.
~1EXAS
2-212
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 15265
TLV1549C, TLV15491, TLV1549M
1()'BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071C - JANUARY 1993 - REVISED MARCH 1996
mode 5: slow mode, CS Inactive (hIgh) between transfers, 11- to 16-clock transfer
In this mode, CS is inactive (high) between seriall/O-CLOCK transfers and each transfer can be 11 to 16 clocks
long. The fallln~dge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequenc~ returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables I/O CLOCK within a setup time plus two falling edges of the
internal system clock.
mode 6: slow mode, CS active (low) continuously, 16-clock transfer
In this mode,
is active (low) between seriall/D-CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of
the sixteenth 1/0 CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the
MSa of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next
16-clock transfer initiated by the serial interface.
es
analog Input sampling
Sampling of the analog input starts on the falling edge of the thircll/O CLOCK, and sampling continues for seven
I/O CLOCK periods. The sample is held on the falling edge of the tenth 1/0 CLOCK.
converter and analog Input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conve~ion process, the analog input is sampled by closing the Se switch and all ST switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and Se switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector
looks at the first capacitor (weight =512). Node 512 ofthis capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF -. If the voltage at the summing
node is greater than the trip point ofthe threshold detector (approximately one-half Vee), a bit 0 is placed in the
output register and the 512-weight capacitor is switched to REF-.lf the voltage at the summing node is less
than the trip point ofthe threshold detector, a bit 1 is placed in the register and this 512-weight capacitor remains
connected to REF + through the remainder of the successive-approximation process. The process is repeated
for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are determined..
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to determine the bits from MSa to LSa.
"!!!1EXAS
WfSTRUMENTS
POST OFFICE BOX 666303 • DAUAS. TEXAS 76265
2-213
TLV1549C, TLV15491, T~V1549M
10-81T ANALOG;.TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071C-JANUARY 1993., REVISED MARCH 1995
Threshold
Detector
51~
NODE':'
e!l I '
TO Output
Latches
j
128
18
t~t~t~t~t~t;;t;:.T ~T
REF-~_:EF-~_:EF-~~REF-~~REF-~~REF-~_SyREF-~_SyREF-~;
REF-
~~
. j 1 1 m1 1 1 j 1 j
Figure 1. Simplified Model of the Successive-Approximation System
chip-select operation
The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.
A high-to-Iow transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device
rettlrns to the initial state (the contents of the output data register remain at the previous conversion result).
Exercise care to prevent CS from being taken low close to completion of conversion because the output data
may be corrupted.
reference voltage Inputs
.
.
There are two reference inputs used with the TLVl549: REF+ and REF-. These voltage values establish the
upper and lower limits of the analog input to produce a full-scale and zero reading, respectively. The values of
REF+, REF-, and the analog input should not exceed the positive supply or be lower than GND consistent with
the specified absolute maximum ratings. The digital output .is at full scale when the input signal is equal to or
higher than REF+ and at zero when the input signal is equal to or lower than REF-.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1): TLV1549C ....................•............ -0.5 V to 6.5 V
TLV15491 ..................•............... -0.5 V to 6.5 V
TLV1549M ................................... -0.5 V to 6 V
Input voltage range, VI (any input) .........•.......................•.......... -0.3 V to Vee + 0.3 V
Output voltage range, Vo ................•.......................•.........• -0.3 V to Vee + 0.3 V
Positive reference voltage, Vref + .....•......•..............................••......... Vee + 0.1 V
Negative reference voltage, Vref- ....•..................................................... -0.1 V
Peak input current (any input) ...............•......................................•.... ±20 mA
Peak total input current (all inputs) .......•............................................... ±30 mA
Operating free-air temperature range, TA: TLV1549C ...............•.........•......... O°C to 70°C
TLVl5491 ..........................•....... -40°C to 85°C
TLVl549M ............................... -55°C to 125°C
Storage temperature range, Tstij .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds .............•.....•........ 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to ground with REF- and GND wired together (unless otherwise noted).
-!I1TEXAS
2-214
INSTRUMENTS
POST OFFICE BOX ess303 • DALlAS, TEXAS 75266
TLV1549C, TLV15491, TLV1549M
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071C - JANUARY 1993 - REVISED MARCH 1995
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
3
3.3
3.6
Positive reference voltage, Vref+ (see Note 2)
2.5
Differential reference voltage, Vref + - Vref- (see Note 2)
Analog input voltage (see Note 2)
0
High-level control input voltage, VIH
I VCC-3 V to 3.6 V
Low-level control input voltage, VIL
I VCC- 3 Vt03.6 V
Clcick frequency at 1/0 CLOCK (see Note 3)
VCC
V
VCC+O.2
V
VCC
V
0.6
V
2.1
MHz
2
0
V
V
VCC
0
Negative reference voltage, Vref- (see Note 2)
UNIT
V
1.425
).IS
0
ns
Pulse duration, 1/0 CLOCK high, IwH(I/O)
190
ns
Pulse duration, VO CLOCK 10w,IwU1/0)
190
Setup time, CS low before first 1/0 CLOCKt, tsu(CS) (see Note 4)
Hold time, ~ low after last 1/0 CLOCK'!', th(CS)
Transition time, 1/0 CLOCK, tlll/O) (see Note 5 and Figure 5)
Transition time, CS, ttlCS)
).IS
10
).IS
0
-40
70
·C
TLVI5491
85
·C
TLVI549M
-55
125
·C
TLVI549C
Operating free-air temperature, TA
ns
1
NOTES: 2. Analog Input voltages greater than that applied to REF + convert as all ones (1111111111 ), while Input voltages less than that applied
to REF -convert as all zeros (0000000000). The TLVI549 is functional with reference voltages down to 1 V (Vref + - Vref _); however,
the electrical specifICations are no longer applicable.
3. For 11- to 16-blt transfers, after the tenth 1/0 CLOCK falling edge (S 2 VJ, at least one 1/0 CLOCK rising edge f.2: 2 V) must occur
within9.5).1S.
4. To minimize errors caused by noise at ~, the internal circuitry waits for a setup time plus two falling edges of the intemal system
clock after CS.!. before responding to the 1/0 CLOCK. Therefore, no attempt should be made to clock out the data until the minimum
CS setup time has elapsed.
5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the device functions with input clock transition time as slow as 1 ).IS for remote data-acquisition applications
where the sensor and the AI D converter are placed several feat away from the controlling microprocessor.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-215
TLV1549C, TLV15491,TLV1549M
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS07.1C-JANUARY 1993'- REVISED MARCH 1995
electrical characteristics over recommended operating free-air temperature range,
Vee Vref+ 3 V to 3.6 V, I/O CLOCK frequency 2.1 MHz (unless otherwise noted)
=
=
=
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
VOL
Low-level output voltage
IOZ
Off-state (high-Impedance-state) output current
MIN
TYP't
IOH--l.6rnA
VCC =3 Vt03.6 V,
IOH --20 jIA
VCC- 3V,
IOL-l.6rnA
0.4
VCC=3 Vto3.6 V,
IOL= 20 jIA
0.1
VO-VCC,'
CSatVcc
10
VO-O,
CSatVcc
-10
IIH
High-level input current
VI-VCC
IlL
Low-level input current
VI-O
ICC
Operating supply current
CSatOV
V
Ci
Input capacitance
Vref+-VCC,
2-216
jIA
0.4
2.5
rnA
10
Vref-=GND
TLVI549C,1 (Analog)
During sample cycle
30
TLVI549M; (Analog)
During sample cycle
30
TLV1549C,I (Control)
5
TLVI549M, (Control)
5
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265
jIA
2.5
-2.5
1
~1ExAs
IiA
0.005
-1
t All tYPical values are at VCC = 3.3 V, TA = 25"C.
V
-0.005
VI-O
Maximum static analog reference current into
REF+
UNIT
VCC-O•1
VI-VCC
Analog input leakage current
MAX
2.4
VCC=3V,
jIA
jIA
55
15
pF
TLV1549C, TLV15491, TLV1549M
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1995
operating characteristics over recommended operating free-air temperature range,
Vee = vref+ = 3 V to 3.6 V, 1/0 CLOCK frequency = 2.1 MHz
PARAMETER
TEST CONDITIONS
MIN
Linearity error (see Note 6)
10
UNIT
±1
LsB
Zero error (see Note 7)
See Note 2
±1
LSB
Full-scale error (see Note 7)
See Note 2
±1
LSB
±1
LsB
21
lIS
Total unadjusted error (see Note 8)
Ioonv
MAX
Conversion time
See Figures 6-11
Total cycle time (access, sample, and conversion)
Valid time, DATA OUT remains valid after I/O CLOCK.!.
tv
1cl1ll0-DATAl Delay time, 1/0 CLOCK.!. to DATA OUT valid
Enable time, CS.!. to DATA OUT (MSB driven)
tPZH,tPZL
Disable time, CST to DATA OUT (high impedance)
tpHZ,tpLZ
Rise time, data bus
tr(busl
Fall time, data bus
21
+101/0
CLOCK
periods
See Figures 6-11
and Note 9
See Figure 5
10
lIS
ns
See Figure 5
240
ns
See Figure 3
1.3
See Figure 3
180
lIS
ns
See Figure 5
300
ns
See Figure 5
300
ns
tf(busl
Delay time, 10th 110 CLOCK.!. to CS.!. to abort conversion (see Note 10)
9
lIS
IclCl/O-CSl
NOTES: 2. Analog input voltages greater than that applied Ie REF + convert as all ones (1111111111), while Input voltages less than that applied
to REF - convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref + - Vref-); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the A I D transfer characteristics.
7. Zero error is the difference between 0000000000 and the converted output for zero input voltage; fuli-scale error is the difference
between 1111111111 and the converted output for fuli-scale input voltage.
8. Total unadjusted error comprises linearity, zero, and full-scale errors.
9. 1/0 CLOCK period = 1/(1/0 CLOCK frequency). Sampling begins on the falling edge of the third 1/0 CLOCK, continues for seven
1/0 CLOCK periods, and ends on the falling edge of the tenth 1/0 CLOCK (see Figure 5).
10. Any transitions of CS are recognized as valid only if the level is maintained for a minimum of a setup time plus two falling edges of
the intemal clock (1.425 lIS) after the transition.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-217
TLV1549C, TLV15491, TLV1549M
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Vee
Teet Point
RL= 2.18 kO
DATAOUT---'-*~~__- '
Figure 2. Load Circuit
DATA OUT
V{
)
2.4
-----<0.4 V
900/0
100/0
Figure 3. DATA OUT to HI·Z Voltage Waveforms
cs ~
2V~1
0.8 V
tsu(CS)
1/0 CLOCK
I!I
'I',
I
~
~I
14
I
1
~ ~ __ il;;\.
;::;\.\ _~ __
~ Ci;k ~~ C~k ~
Figure 4. CS to 110 CLOCK Voltage Waveforms
1/0 CLOCK
0.8 V
td(I/()'DATA)
I+-14
tv~
DATA OUT
2.4
0.8V
I/O CLOCK Period
0.8 V
----J
~I
1
V~ J:~~2.4~V~------
___~0~.4~V~~~_0~A~V~_ _ _ _ ____
I I
14-
~
tr(bus). tf(bus)
Figure 5. 110 CLOCK and DATA OUT Voltage Waveforms
~TEXAS
2-218
ttt(CS)
INSTRUMENTS
POST OFFICE BOX 65S303 • DALLAS. TEXAS 75265
TLV1549C, TLV15491, TLV1549M
1O-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION
(~
csl
(see Note A)
'r--
..- - - - - - - - - - - - - - - - - - - - - - - -....
I
I
1/0
CLOCK
I
I
r-------~~~
DATA
OUT
- - - - - - -___tI+_
AJD
Conversion -+11
Interval
(S 21 lIB) Initialize
Figure 6. Timing for 1o-Clock Transfer Using CS
_~. Must
CS
(see Note A)
/
Be High on Power Up
IL---
--------------------------------------------------~),____
j
1
I/O
-----------'lrfl
CLOCK~
------fI
1
DATA
See Note B
----.lr AS
1111
1
MSB
~
Low Level
OUTN
--------ti4-
1
AJD Conversion -tI
Interval
1
(S 21 lIB)
Initialize
Initialize
Figure 7. Timing for 1o-Clock Transfer Not Using CS
See Note C
(seeN~~,~--------------------------------~II~II~IIIII~~~--I
I pni r11
CLO~~ I
f1~~ L
1
Low
Level
DATA
OUT
I
I
J"r,."HI.-.ZT'\~
I~--AJ~D--~
I
I
4
1414----:-:-=------ Previous Conversion Data -------:-LS=:B=----'I4I11- Conversion
I MSB
IntervaI
I
Initialize
(S 21 lIB) Inltlellze
Figure 8. Timing for 11· to 16-Clock Transfer Using CS (Serial Transfer Completed Within 21 J1S)
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the Intemal system
clock after cS!. before responding to the 1/0 CLOCK. No attempt should be made to clock out the data until the minimum CS setup
time has elapsed.
B. A low-to-high transition of CS disables 1/0 CLOCK within a maximum of a setup time plus two falling edges of the intemal system
clock.
C. The first I/O CLOCK must occur after the end of the previous conversion.
-!!1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-219
-
TLV1549C, TLV15491, TLV1549M
1()'BIT ANALOG·TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
_
CS
~
(~NowA)
~
110
-HI
CLOCK
Must Be High on Power Up
.
------------------------------------------------------~\\S~-----
I
DATA
~ A9
Low Level
EBeV
'--'II'-__________
~~
OUT~
I
I
114-1II-M
--S....B- - - - - Previous Conversion Data ------:LS-==B....t!tllllII-
I
Inltlalln
AID Conversion ~
Interval
-,
~~~
~~n
Figure 9. Timing for 18-Clock Transfer Not Using l:S (Serl~1 Transfer Completed Within 21 J1S)
cs -,L __________________________________________________111111111 S~
(~NowA)
~~
I
I
CL~~
11
I
I
~
I
pm·
Low
M
I
Jill MSB
LSB
I
~
I
I
L.
I
I
HI·Z Stele
I
t-Y-::-v
~
I
II·
~14- AID -'"
Conversion
Interval
~ 21 118)
I
Initialize
-r-
I
m
SeeNote~~
I
I
I
DATA
I
I'pst
~----
I
Initialize
Figure 10. Timing for 11· to 18-Clock Transfer Using CS (Serial Transfer Completed After 21 J.IS)
cs.
(~NoteA)
110
Must Be High on Power Up
I
II
II
j
I
~~
See Note B
See Note C
CLOCK~
I
DATAJr A9
OUT~
~I
iIIIllII'--M-SB-----
I
I
AID Conversion Interval
(S 21 118)
I
Initialize
Figure 11. Timing for 18-Clock Transfer Not Using l:S (Serial Transfer Completed After 21 J.IS)
NOTES: A. To minimize errors caused by noise at CS, the intemal circuitry waits for a set up time plus two faDing edges of the internal system
clock after CS.!. before responding to the 1/0 CLOCK. No attempt should be made to c.lock out the data until the minimum CS setup
time has elapsed.
B. A Iow-to-hlgh transition of CS disables I/O CLOCK within a maximum of a setup time plus two failing edges of the internal system
clock.
C. The first 110 CLOCK must occur after the end of the previous conversion.
~TEXAS
2-220
INSTRUMENTS
POST OFFICE BOX 8155303 • DALLAS, TEXAS 76286
TLV1549C, TLV15491, TLV1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1995
APPLICATION INFORMATION
1111111111
./ ~
I
I
See Notes A and B
1111111110
~V;
1111111101
CD
8..
)~V
••
•
~:
~V
1000000001
:I
.& 1000000000
:I
0
li!9
c
VZT
0111111111
/
••
•
0000000010
0000000001
0000000000
I
0.006
513
512
/'
••
•
2
I
I
•••
1.5315
1.5345
1.5375
o
d
•••
VI - Analog Input Voltage - V
a.
~
511
I
I
~
0.003
••
•
VFS
Ii
T
o ;
1021
\
/!
Ii
1/ kr/'"
1/V~V
\
I
I
~)::::V
/'
Vzs
1022
VFT = VFS -1/2 LSB
~V
=VZS + 1/2 LSB
/
/'
II I
1023
V
3.066 ~ 3.069
o
3.072
..s
NOTES: A. This curve is based on the assumption that Vref+ and Vref- have been adjusted so thalthe voltage althe transition from digital 0
to 1 (VZT) is 0.0015 V and the transition to full scale (VFT) is 3.0675 V. 1 LSB = 3 mY.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.
Figure 12. Ideal Conversion Characteristics
TLV1549
Analog Input
2 ANALOG IN
CS
110 CLOCK
5
7
Processor
DATA OUT
5-V DC Regulated
1
Control
Circuit
6
REF+
--.!- REFGND
To Source
Ground
I4
l
Figure 13. Typical Serial Interface
~TEXAS
INSTRUMENTS
POST OFFICE BOX 665303 • OALLAS. TEXAS 75265
2-221
TLV1549C, TLV15491, TLV1549M'
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1996
APPLICATION INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 14, the time required to charge the analog input capacitance from 0 to Vs
within 1/2 LSB can be derived ,as follows:
The capacitance charging voltage is given by
(1 )
where
Rt=Rs+rj
The final voltage to 1/2 LSB is given by
Vc (1/2 LSB) = Vs - (Vs/2048)
(2)
Equating equation 1 to equation 2 and solving for time to gives
Vs - (VS/2048) = VS(1-e-tc/RtCi)
(3)
to (1/2 LSB) = Rt x Ci x In(2048)
(4)
and
Therefore, with the values given the time for the analog input signal to settle is
to (1/2 LSB) = (Rs + 1 kO) x 60 pF x In(2048)
(5)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet ,4
Rs
I
I
I
I
VI
•
TLV1549
I'J
VS~VC
I 1kOMAX
I
I
I
TCI
rh
50pFMAX
=
VI Input Voltage at ANALOG IN
VS= External Driving Source Voltage
Rs =Source Resistance
'
rl =Input Resistance
01 =Equivalent Input Capacitance
t
Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.
Figure 14. Equivalent Input Circuit Including the Driving Source
~TEXAS
2-222
'
INSTRUMENTS
POST OFAOE SOX 665303 • DALLAS. TEXAS 75266
TLV2543C, TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
• 12-Blt-Resolutlon AID Converter
• 1o-J1S Conversion Time Over Operating
Temperature
• 11 Analog Input Channels
• 3 Built-In Self-Test Modes
• Inherent Sample and Hold
• Linearity Error .•• ± 1 LSB Max
• On-Chip System Clock
• End-of-Converslon (EOC) Output
• Unipolar or Bipolar Output Operation
(Signed Binary With Respect 1/2 the
Applied Referenced Voltage)
•
•
•
•
OB,
ow, OR N PACKAGE
(TOP VIEW)
AINO
AIN1
AIN2
AIN3
VCC
EOC
110 CLOCK
4
DATA INPUT
DATA OUT
CS
AIN6
AIN7
AIN8
GND
9
REF+
REFAIN10
Programmable MSB or LSB First
Programmable Power Down
Programmable Output Data Length
CMOS Technology
description
The TLV2543C and TLV25431 are 12-bit, switched-capacitor, successive-approximation, analog-to-digital
converters (ADCs). Each device has three control inputs [chip select (CS), the input-output clock (I/O CLOCK),
and the address input (DATA INPUT)] and is designed for communication with the serial port of a host processor
or peripheral through a serial 3-state output. The device allows high-speed data transfers from the host.
In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel
multiplexer that can select anyone of 11 inputs or anyone of three internal self-test voltages. The
sample-and-hold function is automatic. Atthe end of conversion, the end-of-conversion (EOC) output goes high
to indicate that conversion is complete. The converter incorporated in the device features differential
high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry
from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating
temperature range.
The TLV2543 is available in the OW, FN, and N packages. The TLV2543C is characterized for operation from
O°C to 70°C, and the TLV25431 is characterized for operation from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
ow
OBt
O'C10 70'C
TLV2543CDW
TLV2543CDB
-40'C to 85'C
TLV2543IDW
TLV2543IDB
,
PLASTICOIP
N
TLV2543CN
TLV2543IN
t Available in tape and reel and ordered as Ihe TLV2543CDBR or TLV2543IDBR.
=-=
-,liliiii.
PRODUCT PREVIEW InIannIIIon _
~ In tile_or
III
C I I I _ dill ond _
.. lillian gooIo.1'nIo In _ _ tile rlghllO
ordllcGntlnuolhoieproduCllwlUloul noIIct.
.
~TEXAS
Copyright © 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 65S303 • DALLAS. TEXAS 75265
2-223
;:
W
:;
w
a:
D.
t-
O
S
o
a:
D.
TLV2543C, TLV25431
12-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096 - MARCH 1995
functional block diagram
.
AINO ~
AIN1 .!..AIN2 ..L
AIN3
AIN4 ~
AIN5
AIN6 ~
AIN7 ~
AIN8 9
4-!-
AIN9
AIN10
Sample and
Hold
-
........:::...
REF+
REF-
141
131
12-Blt
Analog-to-Dlgltal
Converter
(switched cepacltors)
14-Channel
Analog
Multiplexer
11
12
-=-
-
12
~
_Output
Data
Reglstar
Input Address
Register
12
~
12-t0-1 Data
Selector and
Driver
r.1!.
DATA
OUT
4
j~
3
L-
"tJ
Jl
-+1
o
DATA
INPUT
c:
1/0 CLOCK
C
(")
CS
-I
Self-Test
Reference
Control Logic
and 1/0
Countere
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~ EOC
17
+
18
15
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~TEXAS·
2-224
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
TLV2543C, TLV25431
12-81T ANALOG-T()'DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS098-MARCH 1996
Tennlnal Functions
TERMINAL
110
DESCRIPTION
1-9,
11,12
I
These 11 analog-signal inputs are internally multiplexed. The driving source impedance should be less than
or equal to 50 0 for 4.1-MHz I/O CLOCK operation and capable of slewing the analog input voltage into a
capacitance of 60 pF.
CS
15
I
Chip select. A high-to-Iow transition on CS resets the intemal counters and controls and enables DATA OUT,
DATA INPUT, and 1/0 CLOCK. A Iow-to-high transition disables DATA INPUT and 110 CLOCK within a setup
time.
DATA INPUT
17
I
Seriaklata input. A 4-bit serial address selects the desired analog input or test voltage to be converted next.
The serial data is presented with the MSB first and is shifted in on the first four rising edges of 1/0 CLOCK.
After the four address bits are read into the address register, I/O CLOCK clocks tha remaining bits in order.
DATA OUT
16
a
The 3-state serial output for tha AID conversion result. DATA OUT Is in the high-Impedance state when CS
is high and active when CS Is low. With a validCS, DATA OUT is removed from the high-impedance state and
is driven to the logic level corresponding to the MSBlLSB value of the previous conversion result. The next
falling edge of 110 CLOCK drives DATA OUT to the logic level corresponding to the next MSB/LSB, and the
remaining bits are shifted out in order.
EOC
19
a
End of conversion goes from a high to a low logic level after the falling edge of the last 110 CLOCK and remains
low until the conversion is complete and data are ready for transfer.
GND
10
I/O CLOCK
18
NAME
NO.
AINO-AIN10
The ground retum terminal for the intemal circuitry. Unless otherwise noted, all voltage measurements are
with respect to GND.
I
Inputloutput clock. 110 CLOCK receives the serial Input and perfonns the following four functions:
1. It clocks the eight Input data bits into the input data register on the first eight rising edgos of 1/0 CLOCK
with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input
begins charging the capacitor array and continues to do so until the last falling edge of I/O
CLOCK.
3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on
the falling edge of 110 CLOCK.
4. It transfers control of the conversion to the internal state controller on the falling edge of the last
I/O CLOCK.
14
I
The upper refarence voitage value (nominally VCC) is applied to REF+. The maximum input voltage range is
determined by the difference between the voltage applied to this terminal and the voltage applied to the REFterminal.
REF-
13
I
The lower reference voitage value (nominally ground) is applied to REF-.
Vee
20
REF+
a.
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Positive supply voltage
detailed description
Initially, with chip select (CS) high, 1/0 CLOCK and DATA INPUT are disabled and DATA OUT is In the
high-impedance state. CS, going low, begins the conversion sequence by enabling I/O CLOCK and DATA
INPUT and removes DATA OUT from the high-impedance state.
The input data is an 8-bit data stream consisting of a 4-bit analog channel address (07 -04), a 2-bit data length
select (03-02), an output MSB or LSB first bit (01), and a unipolar or bipolar output select bit (DO) that are
applied to DATA INPUT. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the
input data register.
During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the output data
register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clocks long depending on the
data-length selection in the input data register. Sampling of the analog input begins on the fourth falling edge
of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK sequence. The last
falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion.
:lllExAs
INS1RUMENTS
POST OFFICE BOX 1155303 • DAllAS, TEXAS 75266
3:
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2-225
TLV2543C, TLV25431
12·BITANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096 - MARCH 1995
converter operation
The operation of the converter is organized as a succession of two distinct cycles: 1) the 1/0 cycle and 2) the
actual conversion cycle. The 1/0 cycle is defined by the externally provided 1/0 CLOCK and lasts 8, 12, or 16
clock periods, depending on the selected output data length.
1. 1/0 cycle
During the 1/0 cycle, two operations take place simultaneously.
a. An8-bit data stream consisting of address and control information is provided to DATA INPUT. This data
is shifted into the device on the rising edge of the first eight I/O CLOCKs. DATA INPUT is ignored after
the first eight clocks during 12 or 16 clock I/O transfers.
b. The data output, with Ii length of 8, 12, or 16 bits, is provided serially on DATA OUT. If CS is held low, the
first output data bit occurs on the rising ed~of EOC. If CS is negated between conversions, the first
output data bit occurs on the falling edge of CS. This data is the result ofthe previous conversion period,
and after the first output data bit, each succeeding bit is clocked out on the falling edge of each
succeeding I/O CLOCK.
2. Conversion cycle
The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to
I/O CLOCK. During the conversion period, the device performs a successive-approximation conversion on
the analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when
conversion is complete and the output data register is latched. A conversion cycle is started only after the I/O
cycle is completed, which minimizes the influence of external qigital noise on the accuracy ofthe conversion.
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power up and Initialization
After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data
register is set to all zeroes. The contents of the output data register are random, and the first conversion result
should be ignored. To initialize during operation, CS is taken high and returned low to begin the next I/O cycle.
The first conversion after the device has returned from the power-down state may not read. accurately due to
internal device settling.
operational terminology
Current (N) 1/0 cycle
The entire 1/0 CLOCK sequence that transfers address and control data into the data register and clocks
the digital result from the previous conversion from DATA OUT
Current (N) conversion cycle
The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is the
last clock falling edge in the 1/0 CLOCK sequence. The current conversion result is loaded into the output
register when conversion is complete.
Current (N) conversion result
Previous (N -1) conversion cycle
The current conversion result is serially shifted out on the next I/O cycle.
The conversion cycle just prior to the current I/O cycle
Next (N + 1) I/O cycle
The I/O period that follows the current conversion cycle
Example: In the 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during
the next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even if
this corrupts the output data from the previous conversion. The current conversion begins immediately after
the twelfth falling edge of the current I/O cycle.
data Input
The data inputis internally connected to an S:-bit serial-input address and control register. The register defines
the operation of. the converter and the output data length. The host provides the data word with the MSB first.
Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 1 for the data register
format).
~TEXAS
2-226
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
TLV2543C,TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096-MARCH 1995
data Input address bits
The four MSBs (07 - 04) of the data register are used to address one of the 11 input channels, a reference-test
voltage, or the power-down mode. The address bits affect the current conversion, which is the conversion that
immediately follows the current 1/0 cycle. The reference voltage is nominally equal to Vref+ - Vrefdata output length
The next two bits (03 and 02) of the data register select the output data length. The data-length selection is valid
for the current 1/0 cycle (the cycle in which the data is read). The data-length selection, being valid for the current
VO cycle, allows device start up without losing 1/0 synchronization. A data length of 8, 12, or 16 bits can be
selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With 03 and 02 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial-data stream during the next 1/0 cycle. The current 1/0 cycle must be
exactly 12 bits long for proper synchronization, even if this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current 1/0 cycle.
With bits 03 and 02 set to 11 , the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit
serial-data stream during the next 1/0 cycle with the four LSBs always set to 0 (pad bits). The current 1/0 cycle
must be exactly 16 bits long to maintain synchronization even if this means corrupting the output data from the
previous conversion. The current conversion is immediately started after the 16th falling edge of the current 1/0
cycle.
With bits 03 and 02 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the8-bit mode, the result of the current conversion is output as an 8-blt serial-data stream
during the next VO cycle. The current 1/0 cycle must be exactly 8 bits long to maintain synchronization, even
if this means corrupting the output data from the previous conversion. The four LSBs of the conversion result
are truncated and discarded. The current conversion is immediately started after the eighth falling edge of the
current 1/0 cycle.
Since 03 and 02 take effect on the current 1/0 cycle when the data length is programmed, there can be a conflict
with the previous cycle when the data-word length is changed from one cycle to the next. This may occur when
the data format is selected to be least significant bit first, since at the time the data length change becomes
effective (6 riSing edges of 1/0 CLOCK), the previous conversion result has already started shifting out.
In actual operation, if different data lengths are required within an application and the data length is changed
between two conversions, no more than one conversion result can be corrupted and only if it is shifted out in
LSB first format.
sampling period
Ouring the sampling period, one of the analog inputs is internally connected to the capacitor array of the
converter to store the analog input signal. The converter starts sampling the selected input immediately after
the four address bits have been clocked into the input data register. Sampling starts on the fourth falling edge
of 1/0 CLOCK. The converter remains In the sampling mode until the eighth, twelfth, or Sixteenth falling edge
of the 1/0 CLOCK depending on the data-length selection. After the EOC delay time from the last 1/0 CLOCK
falling edge, the EOC output goes low indicating that the sampling period is over and the conversion period has
begun. After EOC goes low, the analog input can be changed without affecting the conversion result. Since the
delay from the falling edge of the last VO CLOCK to EOC low is fixed, time-varying analog input signals can be
digitized at a fixed rate without introdUCing systematic harmonic distortion or noise due to timing uncertainty.
After the 8-bit data stream has been clocked in, OATA INPUT should be held at a fixed digital level until EOC
goes high (indicating the conversion is complete) to maximize the sampling accuracy and minimize the influence
of external digital noise.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 666303 • DAllAS. TEXAS 7S265
2-227
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TLV2543C,TLV25431
12·91T ANAlOG-TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
0
SLAS096-MARCH 1995
data register, LSB first
01 in the input data register (LSB first) is used to control the direction of the output binary data transfer. When
01 is set to 0, the conv~rsion result is shifted out MSB first. When set to 1, the data is shifted O!,lt LSB first.
Selection of MSB first or LSBfirst always affects the next 1/0 cycle and not the current 1/0 cycle, When changing
from one data direction to another, the current 1/0 cycle is never disrupted.
data register, bipolar format
DO in the input data register is used to control the binary data format used to represent the conversion result.
When DO is set to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the
conversion result of an input voltage equal to Vref- is a code of all zeros (000 ... 0), the conversion result of
an input voltage equal to Vref+ is a code of all ones (111 ... 1), and the conversion result of (Vref + + Vref-)/2
is a code of a one followed by zeros (100 ... 0).
When DO is set to 1, the conversion result is represented as bipolar. (BIP) .(signed binary) data. Nominally,
conversion of an input voltage equal to Vref-is a code of a 1 followed by zeros (100 ... 0), conversion of an
input voltage equal to Vref+ is a code ofa 0 followed by all ones (011 ... 1), and the conversion of (Vref+ + Vref-) 12
is a code of all zeros (000 ... 0). The MSB is interpreted as the sign bit. The bipolar data formatis rE!lated to
the unipolar format in that the MSBs are always each other's complement.
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Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next 1/0 cycle. When changing between unipolar and bipolar formats, the data output during the
current 1/0 cycle is not affected.
EOC output
The EOC signal indicates the beginning and the end of conversion. In the reset state, EOC is always high. During
the sampling period (beginning after the fourth falling edge of the 1/0 CLOCK sequence), EOC remains high
until the internal sampling switch of the converter is safely opened. The opening of the sampling switch occurs
after the eighth, twelfth, or sixteenth 1/0 CLOCK falling edge, depending on the data-length selection in the input
data register. After the EOC signal goes low, the analog input signal can be changed without affecting the
conversion result.
The EOC signal goes high again afterthe conversion is completed and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new 1/0 cycle b~s.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT if CS is low. If CS is
negated between conversions, the first bit of the current conversion result occurs at DATA OUT on the falling
edge of CS.
data format and pad bits
03 and 02 of the input data register determine the number of significant bits in the digital output that represent
the conversion result. The LSB-first bit determines the direction of the data transfer while the BI P bit determines
the arithmetic conversion. The numerical data is always justified toward the MSB in any output format.
The internal conversion result is always 12 bits long. When an a-bit data transfer is selected, the four LSBs of
the internal result are discarded to provide a faster one-byte transfer. When a 12-bit transfer is used, all bits are
transferred. When a 16-bit transfer is used, four LSB pad bits are always appended to the internal conversion
result. In the LSB-first mode, four leading zeros are output. In the MSB-first mode, the last four bits output are
zeros.
When CS is held low continuously, the first data bit of the just completed conversion occurs on DATA OUT on
the rising edge of EOC. When a new conversion js started after the last falling edge of 1/0 CLOCK, EOC goes
low and)he serial output is forced to a logic zero until EOC goes high again.
"
When CS is negated between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On
each subsequent falling edge of 1/0 CLOCK after the first data bit appears, the data is changed to the next bit
in the serial conversion result until the required number of bits has been output.
~TEXAS
INSTRUMENTS
POST OFFICE. BOX 665303 • DALlAS. TEXAS 75265
-
TLV2543C, TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096-MARCH 1995
chip-select Input (CS)
The chip-select input (CS) enables and disables the device. During normal operation, CS should be low.
Although the use of CS is not necessary to synchronize a data transfer, it can be brought high between
conversions to coordinate the data transfer of several devices sharing the same bus.
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing
its output data line to other devices that may share it. After an internally generated debounce time, the I/O
CLOCK is inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low, 1/0 CLOCK must remain inactive (low)
for a minimum time before a new 1/0 cycle can start.
CS can be used to interrupt any ongoing data transfer or any ongoing conversion. If CS is debounced low long
enough before the end of the current conversion cycle, the previous conversion result is saved in the internal
output buffer and shifted out during the next 1/0 cycle.
power-down features
When a binary address of 1110 is clocked into the input data register during the first four 1/0 CLOCK cycles, the
power-down mode is selected. Power down is activated on the falling edge of the fourth 1/0 CLOCK pulse.
During power down, all internal circuitry is put in a low-current standby mode. No conversions are performed,
and the internal output buffer keeps the previous conversion cycle data results, provided that all digital inputs
are held above Vee - 0.5 V or below 0.5 V. The 1/0 logic remains active so the current 1/0 cycle must be
completed even when the power-down mode is selected. Upon power-on reset and before the first 1/0 cycle,
the converter normally begins in the power-down mode. The device remains in the power-down mode until a
valid (other than 1110) input address is clocked in. Upon completion of that 1/0 cycle, a normal conversion is
performed with the results being shifted out during the next 1/0 cycle.
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analog Input, test, and power-down mode
The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer
according to the input addresses shown in Tables 2, 3, and 4. The input multiplexer is a break-before-make type
to reduce input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on
the falling edge of. the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held
on the falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer,
sampled, and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75266
2-229
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TLV2543C, TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096 - MARCH 1996
detailed description (continued)
Table 1. Input-Register Format
FUNCTION SELECT
D7
(MSB)
Select input channel
AINO
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
Select test voltage
(Vref + - Vref-)12
VrefVref+
Software power clown
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INPUT DATA BYTE
L1
ADDRESS BITS
LO
D6
D5
D4
D3
D2
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
1
1
1
0
0
1
1
0
1
0
Output data length
8 bits
12 bits
16 bits
Output data format
MSBfirst
LSB first
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Table 2. Analog-Channel-Select Address
ANALOG INPUT
SELECTED
AINO
AINl
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
VALUE SHIFTED INTO
DATA INPUT
BINARY
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
HEX
0
1
2
3
4
5
6
7
8
9
A
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BIP
DO
(LSB)
0
1
Unipolar (binary)
Bipolar' (2s complement)
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LSBF
D1
INsTRUMENTS
POST OFFICE BOX 866303 • DALLAS, TEXAS 75266
TLV2543C,TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096 - MARCH 1995
detailed description (continued)
Table 3. Test-Mode-Select Address
INTERNAL
SELF·TEST
VOLTAGE
SELECTEDt
VALUE SHIFTED INTO
DATA INPUT
BINARY
HEX
1011
B
Vl1!f±-Vcm-
2
UNIPOLAR OUTPUT
RESULT (HEX)t
200
1100
C
000
Vref3FF
1101
0
Vref+
t Vref + is the voltage applied to REF +, and Vref- is the voltage applied to REF-.
:j: The output results shown are the ideal values and may vary with the reference stability
and with internal offsets.
Table 4. Power-Down-Select Address
INPUT COMMAND
Power down
VALUE SHIFTED INTO
DATA INPUT
BINARY
1110
I
I
HEX
E
RESULT
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converter and analog Input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the Se switch and all ST switches simultaneously.
This action charges all the capaCitors to the input voltage.
In the next phase of the conversion process, all ST and Se switches are opened and the threshold detector
begins identifying bits by identifying the cha~ge (voltage) on each capacitor relative to the reference (REF-)
voltage. In the switching sequence, 12 capacitors are examined separately until all 12 bits are identified and
the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks
at the first capaCitor (weight = 4096). Node 4096 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF-. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half Vee), a bit 0 is placed in the
output register and the 409B-weight capaCitor is switched to REF-. If the voltage at the summing node is less
than the trip point of the threshold detector, a bit 1 is placed in the register and this 4096-weight capaCitor
remains connected to REF + through the remainder of the successive-approximation process. The process is
repeated for the 2048-weight capacitor, the 1024-weight capacitor, and so forth, down the line until all bits are
determined. With each step of the successive-approximation process, the initial charge is redistributed among
the capaCitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.
reference voltage Inputs
There are two reference voltage inputs on the device: REF+ and REF-. The voltage values on these terminals
establish the upper and lower limits of the analog input to produce a full-scale and zero-scale reading
respectively. These voltages and the analog input should not exceed the positive supply or be lower than ground
consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal
is equal to or higher than REF+ terminal voltage and at zero when the input signal is equal to or lower than REFterminal voltage.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OAu.AS, TEXAS 75265
2-231
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TLV2543C, TLV25431
12-81T ANALOG-T()"DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096 - MARCH 1996
detailed description (continued)
Figure 1. Simplified Model of the Successive-Approximation System
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INSIRUMENTS
POST OFfICE BOX 886303 • DALLAS, TEXAS 76286
TLV2543C, TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096 - MARCH 1995
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ..............•............................. -0.5 V to 6.5 V
Input voltage range, VI (any input) ............................................ -0.3 V to Vee + 0.3 V
Output voltage range, Vo ................................................... -0.3 V to Vee + 0.3 V
Positive reference voltage, Vref+ ...................................................... Vee + 0.1 V
Negative reference voltage, Vref- .......................................................... -0.1 V
Peak input current, II (any input) ......................................................... ±20 mA
Peak total input current (all inputs) ....................................................... ±30 mA
Operating free-air temperature range, TA: TLV2543C ................................... O°C to 70°C
.
TLV25431 .................................. -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ............................ 260°C
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminal with REF-and GND wired together (unless otherwise noted).
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
3
3.3
3.6
Positive reference voltage, Vref+ (see Note 2)
2.5
Differential reference voltage, Vref+ - Vref- (see Note 2)
Analog input voltage (see Note 2)
VCC
0
High-level control input voltage, VIH
I VCC =3 V to 3.6 V
Low-level control input voltage, VIL
\ VCC =3 Vt03.6 V
Clock frequency at 1/0 CLOCK
V
VCC+O.1
V
VCC
V
2
V
0.8
0
V
V
VCC
0
Negative reference voltage, Vref- (see Note 2)
UNIT
3
V
MHz
100
ns
Hold time, address bits after 1/0 CLOCKi, theA) (see Figure 5)
0
ns
Hold time, CS low after last 1/0 CLOCK!, th(CS) (see Figure 6)
0
ns
1.425
lIS
ns
Setup time, address bits at DATA INPUT before 1/0 CLOCKi,\su(A) (see Figure 5)
Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3 and Figure 6)
Pulse duration, I/O CLOCK high,IwH(I/O)
190
Pulse duration, I/O CLOCK low, twL(I/O)
190
Transition time, I/O CLOCK, ttlllO} (see Note 4 and Figure 7)
Transition time, DATA INPUT and CS, tt(CS)
Operating free-air temperature, TA
\TLV2543C
0
ns
1
lIS
10
lIS
70
·C
-40
85
NOTES: 2. Analog input voltages greater than that applied to REF+convertasali ones (111111111111), while input voltages less than that applied
to REF- convert as all zeros (000000000000).
3. To minimize errors caused by noise at the CS input, the internal Circuitry waits for a setup time after CS! before responding to control
input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed.
4. This is the time required for the clock inpllt signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 lIS for remote data acquisition applications
where the sensor and the AID converter are placed several feet away from the controlling microprocessor.
I TLV25431
-!llExAs
INSTRUMENTS
POST OFFICE eox 655303 • DALLAS. TEXAS 75265
2-233
3:
:;
w
a:
w
D..
I-
o
::l
C
oa:
D..
TLV2543C, TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096 - MAROH 1995
.
electrical characteristics over recommended operating free-air temperature range,
Vee = Vref+ = 3 V to 3.6 V (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
VCC- 3V•
VCC -3 V to 3.6 V.
IOZ
Off-state (high-impedancestate) output current
VO-VCC.
VO-O.
VI-VCC
VI-O
CSalOV
IIH
High-level input current
IlL
Low-level input current
ICC
Operetil1ll s4Pply current,
ICC(PD) Power.w
W
a:
1.5
2.2
)IS
See Figure 9
See Figure 4
ns
0.7
100
1.3
Disable time, CS1' to DATA OUT (high impedance)
See Figure 4
70
150
ns
(.)
)IS
Q.
I-
Rise time, EOC.
See Figure 9
15
50
ns
:;:)
Fail time, EOC
See FigureS
15
50
ns
Rise time, data bus
See Figure 7
15
50
ns
Fall time, data bus
See Figure 7
15
50
ns
oa:
5
)IS
Delay time, last 1/0 CLOCK'/' to CS'/' to abort conversion
(see Note 11)
t All typical values are at TA • 25°C.
NOTES: 2. Anaiog input voltages greaier than that applied to REF + convert as all ones (111111111111), while input voltages less than that
applied to REF-convert as all zeros (000000000000).
6. Linearity error Is the maXimum deviation from the 'best sl\"aight line through the AID transfer characteristics.
7. Gain error is the difference between the actual midstep vaiue and the nominal midstep value in the transfer diagram at the specified
gain point aiter the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the
nominal midstep value at the offset point.
S. Total unadjusted error comprises linearity, zero-seele, and full-scale errors.
9. Both the Input addrass and the output codes are expressed in positive logic.
10. 1/0 CLOCK period. 1/(1/0 CLOCK frequency) (see Figura 7).
11. Any transitions of CS are recognized as vaiid only if the level is maintained for a satup time. CS must be taken low at S 5 )IS of the
tenth 110 CLOCK falling edge to assure a conversion is aborted. Batween 5 )IS and 10 )IS, the result is uncertain as to whether the
conversion is aborted or the conversion results are valid.
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 65S303 • DALLAS. TEXAS 75266
2-235
C
Q.
TlV2543C, TLV25431
12..811 ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096 - MARCH 1995
PARAMETER MEASUREMENT INFORMATION
15V
C1
10 IJ.f
C3
470pF
TLV2543
100
VI-~---1
>t.....-'VI/\..----t AINO-AIN10
C1
10 IJ.f
C3
470pF
-15V
LOCATION
"'tJ
:xl
DESCRIPTION
U1
C1
C2
C3
o
C
PART NUMBER
-
OP27
10-J.lF 35-V tantalum capacitor
0.1-J.LF ceramic NPO SMD capacitor
470-pF porcelain high-Q SMD capacitor
AVX 12105C104KA105 or equivalent
Johanson 201 8420471 JG4L or equivalent
c:
~
Figure 2. Analog Input Buffer to Analog Inputs AINO...:AIN10
Teat Point
"'tJ
:xl
Teat Point
m
m
-<
:e
Figure 3. Load Circuits
!.1 .
CS
~~
______2JVT.1
\.O.SV
I!
tpZH. tpZL
DATA
OUT
~
~
I"
2.4 V
0.4V\
DATA INPUT
~_
~
tPHZ.tPLZ
"\ 910%0%
1/0 CLOCK
Figure 4. DATA OUT to HI-Z Voltage Waveforms
1
.v
theA)
1 jeo. ......._ _______.:;O.;:;;s_V.JI
Figure 5. DATA INPUT and 110 CLOCK
Voltage Waveforms
~TEXAS
2-236
--.1
'=X:~~~.::-v-----X=
I
.. 1 1
14
l~
tau (A) .
,
Data
Valid
INSTRUMENTS .
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TLV2543C, TLV25431
12·BIT ANALOG·TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096-MARCH 1995
PARAMETER MEASUREMENT INFORMATION
Figure 6. CS and 110 CLOCK Voltage Waveformst
t To ensure full conversion accuracy, it Is recommended that no input signal change occurs while
a conversion is ongoing.
tt(l/O)
~ I+-- --.: I+-- It(IIO)
II
I~~~
I
I/O CLOCK
0.8 V
I
0.8 V
0.8 V
~O CLOCK Per\od--+I
~
fcI(I/OoDATA) ~I
tv~11
4A~._. .O;;;..4;.;V~
-----""I r
DATA OUT
2.4 V
0.4 V
2.4 V
~
r
w
5>
w
_ _ _ _ __
a::
a.
t,(bus). tt(bus)
I-
Figure 7. 110 CLOCK and DATA OUT Voltage Waveforms
'(,)
110 CLOCK- - - . //
"w.at \
Clock
fclCUOoEOC)
::::l
C
~..;O;;..8.;;.V_ _ _ _ __
o
a::
a.
~~f----~~I
--------,1
2.4V ,~
EOC
!\ 0.4V
tt(EOC)
--+1I II+--
Figure 8. 110 CLOCK and EOC Voltage Waveforms
--.: I+-EOC
~
0.4 V
1
I...
tr(E0C)
2.4V
~(I 2~~oc..DATA)
DATAOUT - - - - - - - - ( .
0.4V
~.;..;..----
j...- Valid MSB --+
Figure 9. EOC and DATA OUT Voltage waveforms
:illExAs
INSTRUMENTS
POST OFFICE BOX 865303 • DAUAS. TEXAS 7e265
2-237
TlV2543C, TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG. INPUTS
SLAS096 - MARCH 1995
PARAMETER MEASUREMENT INFORMATION
\1!--_
(seeNme~~~------------------------------------~SI~~------~
J1LFl W//M~
1
1
1
1/0
CLOCK_+--!
8
------~~I
1
1
DATA
OUT
1
Jr-:::-v
~
M
AO
1-ZState
1
------------L-SB~~I
DATA
INPUT
B7
B6
B5
B4
B3
B2
B1
LSB
:-~'777vv7
---~I
BO
-~~
1 C7
1
1
~----------------------------~\1\~--_n1
"'0'
::JJ
EOC
J~
o
.
c::
n
b
lconv ----.I
AID Conversion
Intarval
Initialize
Figure 10. Timing for 12-Clock Transfer Using CS With MSB First
-I
CSI
"'0
(eeNoteA)
m
CLOCK
<
-
I
r~SI----
------i~~I........----~~
Initialize
C
::JJ
Shift In Naw Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
1
:
1
MSB
~
.
1/0
I~------------------------------------~~IT~--------------~----~~S--1
--II__-!
m
=e
DATA
OUT
: _ _L_o_W_L_ev_e_1_-'I
------------LS-B~~I
BS
B7
MSB
B5
B4
B3
B2
B1
I
---~
DATA
INPUT
BO
LSB
~
1
((
EOC
Shift In New Multiplexer Address,
~
1
HS---
\1
I I.--- tconv ---~
101------- Simultaneously Shift Out Previous ------+1+--------+1
Conversion Value
Initialize
AID Conversion
Interval
Initialize
Figure 11. Timing for 12-Clock Transfer Not Using CS With MSB First
NOTE A: To minimize errors caused by noise at es, the Internal circuitry walts for a setup time afierCSJ. before responding to control input Signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
~1ExAs
2-238
INSTRUMENTS
POST OFFICE BOX 655303.• DALlAS. TEXAS 75265
TLV2543C, TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096-MARCH 1995
PARAMETER MEASUREMENT INFORMATION
s~
('-NOW~ ~~------------------------------------~
I
1/0 CLOCK
!-I--
I
-+--!
I
I
, -_____
HI_~~~
DATA OUT
I
I
--~~
DATA INPUT
I
B7
IMSS
I
EOC
Be
B5
B4
B3
B2
B1
BO
LSS
....
~-..<-~---S~
I
I C7
I
I
I
r-S L I
J~~---------------------------------nll
Initialize
I~)+----
Shift In N_ Multiplexer Address,
I j4-- tconv --+I
Simultaneously Shift Out Previous - - -....~~,,~----+t.1
Conv....lon Value
AID Conversion
Intarval
Initialize
~
W
:;:
w
Figure 12. Timing for 8-Clock Transfer Using CS With MSB First
cs
(.-NowA)
a:
0.
t)
~------------------------------------------------~~~
::l
110 CLOCK
C
0.
'--------------'I!~~
I
------~~
~
DATA INPUT
I
I
EOC
~
Low Level
DATA OUT
oa:
J..+I.----S-h-lft-ln-N-_-M-UI-tlP-le-xer-A-dd-reas-.---.....,.,1~,..J
I
---tco-nV---.::=::'";i:r
Initialize
l
r---
Simultaneously Shift Out Previous - - -........
I4---r-------:--....
Conversion Value
AID COnv....lon
Inwrval
Initialize
Figure 13. Timing for 8-Clock Transfer Not Using CS With MSB First
NOTE A: To minimize errors caused by noise atCS. the internal circuitry waits forasetuptime afterCSJ.before responding to control input signals.
Therefore. no attempt should be made to clock In an address until the minimum CS setup time has elapsed.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-239
TLV2543C, TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096 - MARCH 1995
PARAMETER MEASUREMENT INFORMATION
'1--,
, L-
(~NO~~-'~----------------------------------~\'\~------~
I
I
I
.~ rwl W///o/J73 r
----1-"'
"
~
J
~~
I
I/O
CLOCK
8
L-I
I
I
I
DATA
OUT
I
HI.ZState~
A1AO'
~
I
EOC
\WI':!
I
C7
o
C
"'D
::xJ
m
-
<
m
:IE
I
f"~,~,~I---'conv---+l
------~~I.IIII-----..
~1
AID Conversion
Interval
Initialize
c:
~
J-~------------------------------------~(()------+
"11II+-~
Shift In New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
I
\~
I
--JI
I
"'D
::xJ
~
I
------------~-B~~I
DATA
INPUT
I
I
Initialize
Figure 14. Timing for i6-Clock Transfer Using CS With MSB First
(~Note~ll-----------------------------------~r,'\jl"". --------------------~r,'\j,.----
I/O
CLOCK
I
I
I .
~
DATA
OUT
~~
Low Level
--~~------~~I
LSB
DATA
INPUT
I
87
IMSB
B6
B6
B4
B3
B2
B1
BO
LSB
)
I
I
I
l I
I
mnvv;
~I
C7
--r
--;-,!I
.
EO:Jr!I-IIII_ _ _ _ _ _ _ _ _ _ _ _--Ijf,'l-/,
Shift In New Multiplexer Address,
Simuitaneoualy Shift Out Previous
Conversion Value
'
B15
I
~''l-j--
I II1II-- 'conv --+I
~-----+l~I~.-""':·----~.1
Initialize
AID Conversion
Interval
Figure 15. Timing for i6-Clock Transfer Not Using CS With MSB First
NOTE A: To minimize errors caused by noise at CS,the internal circuitry waits forasetupijme after~J, before responding toeontrol input signals.
Therefore, no attempt should be made to clock in an address until the minimum ~ setup time has elapsed.
~lExAs .
2-240
INSTRUMENTS
POST OFFICE BOX 655303- PAllAS. TEXAS 75265
TLV2543C,TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096-MARCH 1995
APPLICATION INFORMATION
111111111111
I
I
See Notes A and B
vFS ~
111111111110
~ 1i
)~ /' /1I
111111111101
•••
A~
• 100000000001
B
~
'5
t 100000000000
o
,
Q
VZT
=Vzs + 112 LSB
I-VZS
000000000010
000000000001
oooooooooooo
/
1/
III ~
~ '/V
o
I
.,)::::
/
/'
VFT
lA'./'
V
••
•
2049
I
I
Ii
2047
I
I
/'
•••
Ii
2
I
I
/
0.0008 0.0016
4093
=VFS -112 LSB
/'
/'
•••
1.6376
o
1.6384
1.6392
4094
VFSnom
/!
~ /'
7
011111111111
•
••
~ ~l
4095
•••
VI- Analog Input Voltage - V
I
3.2752
~
~
W
:;
w
a:
o
3.2760
3.2768
Il.
I-
~
NOTES: A. This curve is based on the assumption that Vref+ and Vref- have been adjusted so that the voltage at the transition from digital 0
to 1 (VZT) is 0.0006 V and the transition to full scale (VFT) is 4.9134 V. 1 LSB = 1.2 mY.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.
Figure 16. Ideal Conversion Characteristics
o
::l
C
o
a:
Il.
TLV2643
1
2
3
4
5
6
Analog
Inputa
7
8
9
11
12
15
AINO
CS
AIN1
I/O CLOCK
AIN2
DATA INPUT
18
17
Processor
AIN3
AIN4
DATA OUT
AIN5
EOC
COntrol
Circuit
16
19
AIN6
AIN7
AIN8
REF+
AIN9
REF-
AIN10
14
r:+--
3-V DC Regulated
~
GND
.L 10
To Source
Ground
"""-
I
l
Figure 17. Serial Interface
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS, TEXAS 75265
2-241
-
2-242
TL5501
6-81T ANALOG-TO-DIGITAL CONVERTER
SLAS026-
•
•
•
•
•
•
•
•
•
6-Blt Resolution
Linearity Error. •. ±0.8%
Maximum Conversion Rate ••• 30 MHz Typ
Analog Input Voltage Range
Vee to Vee -2 V
Analog Input Dynamic Range. .• 1 V
TTL Digital 110 Level
Low Power Consumption
200mWTyp
S-V Single-Supply Operation
Interchangeable With Fujitsu MB40576
OCTOBER 1969 - REVISED APRIL 1990
NPACKAGE
(TOP VIEW)
(LSB) 00
01
02
3
GNO
DGTlVee
ANlGVee
03
REFB
04
ANlGINPUT
(MSB) 05
elK
GNO
6
7
8
REFT
ANLGVee
9 OGTL Vee
description
The TL5501 is a low-power ultra-high-speed video-band analog-to-digital converter that uses the Advanced
Low-Power Schottky (ALS) process. It utilizes the full-parallel comparison (flash method) for high-speed
conversion. It converts wide-band analog signals (such as a video signal) to a digital signal at a sampling rate
of dc to 30 MHz. Because of this high-speed capability, the TL5501 is suitable for digital video applications such
as digital TV, video processing with a computer, or radar signal processing.
The TL5501 is characterized for operation from O°C to 70°C.
functional block diagram
CLK------i
ANLG INPUT - - - . . . ,
REFT
R
EN
05 (MSB)
D4
R
03
63-\0-6
Encoder
Latch
and
Buffer
02
R
01
00 (LSB)
R
R
REFB
PAODUCTIONDATAI_II_IIorNII_ _ _
canformlOlIIICIIiCaIIOnIperllltl8mllor_ ............. _
....111\< Proclucllon pnICIIIIng _
pili......
not _rIIylncl.... llltlng 01 all
TEXAS .Jf
INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright © 1990, Texas Instruments Incorporated
2-243
TL5501
16-BIT ANALOG·TO-DIGITAL CONVERTER
SLAS026 - 03163, OCTOBER 1989 - REVISED APRIL 1990
equivalents of analog Input circuit
ANLO vee
----41~---41~
ANLOVee
v,
~
----------<..
- ......- - - - - e - - e
e,
ANLO OND
----4~......- - J
NOTE A:Cj - nonlinear emitter-follower junction capacitance
'1- linear resistance model for input current transition caused by comparator switching. VI < VrefB: Infinite; eLK high: infinite.
VrefB-voltage at REFB terminal
lbias - constant input bias current
o -base-oollector Junction diode of emitter-follower transistor
equivalent of digital Input circuit
r------------------------------------------,
DOTL Vee - -......- - -......- - - . . . . . 251<0
3.11<0
251<0
Vref =1.4 V
V,
OND---......- - -......-
......--*--
TEXAS
2-244
.Jf
INSIRUMENI'S
POST OFFICE eox 6S5303 • DAllAS, TEXAS 75266
TL5501
6-BIT ANALOG-TO-DIGITAL CONVERTER
SLAS026- 03163, OCTOBER 1989 - REVISED APRIL 1990
FUNCTION TABLE
ANALOG INPUT
DIGITAL OUTPUT CODE
VOLTAGE
0
3,992 V
L
L
L
L
L
L
1
4,008 V
L
L
L
L
L
H
I
I
I
31
4,488 V
H
H
H
H
H
L
4,508 V
L
L
L
32
H
L
L
4,520 V
33
H
L
L
L
L
H
I
I
I
4,984 V
H
H
H
H
L
62
H
5,OOQV
H
63
H
H
H
H
H
t These values are based onthe assumption that VrefB and VrefT have been
adjusted so that the voltage at the transition from digital to 1 (VZT) is
4,000 V and the transition to full scale (VFT) is 4,992 V, 1 LSB R 16 mY,
STEP
°
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, ANLG Vee (see Note 1) " ... ,., .. ,.".,." .. " ... ,.".,.""", -0.5 V to 7 V
Supply voltage range, DGTL Vee ".", .. ,., .. ,.,.,., .. ,., .. ,." .. " ... , .. ,.,"".", - 0.5 V to 7 V
Input voltage range at digital input, VI ........................... , .... , .... ' .... , .. ,.,. -0,5 V to 7 V
Input voltage range at analog input, VI ... " ... , ........ , ...... , ... , ..... -0,5 V to ANLG Vee +0,5 V
Analog reference voltage range, Vref .... , .... , .... , ... , .... '" ......... -0.5 V to ANLG Vee +0,5 V
Storage temperature range , ........ , ........ , ........ , .... ,...................... -55°e to 150°C
Operating free-air temperature range .. " .... , ... "., ... "., .. , .. , ............ ,., .... ,. O°C to 70°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ., .. ,."." ...... ,., .... , .. ,.,. 260°C
NOTE1:AII voltage values are with respect to the network ground terminal.
recommended operating conditions
MIN
4,75
4,75
2
Supply voltage, ANLG VCC
Supply voltage, DGTL VCC
High-level input voltage, VIH
Low-level input voltage, VIL
Input voltage at analog input. VI (see Note 2)
,Analog reference voltage (top side). VrefT (see Note 2)
Analog reference voltage (bottom side). VrefB (see Note 2)
High-level output current. IOH
Low-level output current. IOL
Clock pulse duration. high-level or 10w-level.1w
Operating free-air temperature. TA
4
4
3
-400
NOM
5
5
MAX
5,25
5,25
5
4
0,8
5
5,1
4,1
IIA
4
25
°
NOTE 2: VrefB
o
tn
3-2
TLC5602C,TLC5602M
VIDEO 8-81T DIGITAL-TO-ANALOG CONVERTERS
1989 - REVISED MAY 1995
•
•
•
•
• 8-Blt Resolution
• ±0.2% Linearity
• Maximum Conversion Rate
30MHzTyp
20 MHz Min
TTL Digital Input Voltage
S-V Single Power-Supply Operation
Low Power Consumption .•••.. 80 mW Typ
Interchangeable With Fujitsu MB40778
• Analog Output Voltage Range
Voo to VOD -1 V
description
The TLC5602x devices are low-power, ultra-high-speed video, digital-to-analog converters that use the
LinEPICTIl 1-J.UTl CMOS process. The TLC5602x converts digital signals to analog signals at a sampling rate
of dc to 20 MHz. Because of high-speed operation, the TLC5602x devices are suitable for digital video
applications such as digital television, video processing with a computer, and radar-signal processing.
The TLC5602C is characterized for operation from O°C to 70°C. The TLC5602M is characterized over the full
military temperature range of -55°C to 125°C.
N PACKAGE
{TOP VIEW)
OGTLGNO
OGTLVoo
COMP
DO (LSB)
01
02
REF
ANLGV001
AOUT
ANLGVOD2
OGTLVoo
ANLGGNO
DWPACKAGE
{TOP VIEW)
03
04
6
7
8
9
11
05
06
07 (MSB)
CLK
OGTLGNO
OGTLVoo
COMP
REF
02
ANLG V001
A OUT
NC
ANLG V002
OGTL VOO
ANLGGNO
03
04
JPACKAGE
{TOP VIEW)
NC
OGTLGNO
OGTL VOO
COMP
11
CLK
Cc
cz
cc~
~
~
C!:IC!:IOOo
........
...J...J
cczzc
6
03
04
9
05
06
07 (MSB)
11
9
>C!:I
01
02
REF
ANLGV001
A OUT
ANLGV002
OGTL VOO
ANLGGNO
05
06
07 (MSB)
FKPACKAGE
{TOP VIEW)
NC
00 (LSB)
3
NC
00 (LSB)
01
COMP
CLK
REF
ANLGVOO1
A OUT
ANLGVOO2
4
5
6
7
8
3 2 1 2019
18
17
16
15
14
9 10 11 12 13
01
02
03
04
05
NO-No internal connection
Un EPIC is a trademark of Texas Instruments Incorporated.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 665303 • DAUAS. TEXAS 75265
3-3
TLC5602C,TLC5602M
VIDEO 8-81" DIGITAL·TO·ANALOG CONVERTERS
SLAS023C - FEBRUARY 1989 - ReviSED MAY 1995
. AVAILABLE OPTIONS
PACKAGE
WIDE-BODY. SMALL OUTLINE
TA
(OW)
O·C to 70·e
CERAMIC CHIP CARRIER
(FK)
CERAMIC DIP
{J}
TLC5602MFK
TLC5602MJ
TLC5602CDW
PLASTIC DIP
(N)
TLC5602CN
-55·C to 125·C
functional block diagram
COMP
----~...,
REF - - - - - - - , I
CLK-------------~
07 -DO
Buffer
Driver With
Register
-...,---1 >""""--1 Decode
8
8
STEP
63
A OUT
3
t-.,-..... lx1
FUNCTION TABLE
DIGITAL INPUTS
DO
OUTPUT
VOLTAGEt
L
L
3.980 V
L
H
3.984 V
H
H
H
4.488 V
07
06
05
04
03
02
01
0
L
L
L
L
L
L
1
L
L
L
L
L
L
I
I
I
127,
L
H
H
H
H
128
H
H
L
L
L
L
L
L
L
4.492 V
L
L
L
L
L
L
H
4.496 V
H
H
H
H
H
L
4.996 V
H
5.000 V
129
I
254
255
I
H
H
H
H
H
H
H
H
I
H
tVDD = 5 V and Vre! = 4.02 V
schematics of equivalent input and output
EQUIVALENT OF EACfI DIGITAL INPUT
DGTLVDD.
DGTL "DO
d
ANLG*
GND
.....- - - ,ANLG VDD1
80n
:J----
On
EQUIVALENT OF ANALOG OUTPUT
~
DGTL*
GND
A OUT
ANLa*
GND
* ANLG GND and DGTL GND do not connect internally and should be tied together as close to the device terminals as poSSible.
3-4
"!11
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 752e6
TLC5602C,TLC5602M
VIDEO 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS023C - FEBRUARY 1989 - REVISED MAY 1995
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)t
Supply voltage range, ANLG Voo, DGTL Voo .........•...........•................... -0.5 V to 7 V
Digital input voltage range, VI •....................................................... -0.5 V to 7 V
Analog reference voltage range, Vref ..................................... VOO-1.7 V to Voo+0.5 V
Operating free-air temperature range, TA: TLC5602C ...............................•.. O°C to 70°C
TLC5602M ............................... -55°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ... . . . . . . . . • . . . . . . . . . . . . . . . . . . 260°C
t Stresses beyond those listed under "absolute maximum ratings·· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Supply voltage, VOO
MIN
NOM
MAX
4.75
5
5.25
V
3.8
4
4.2
V
Analog reference voltage, Vref
2
High-level input voltage. VIH
V
0.8
Low-level input voltage. VIL
Pulse duration, CLK high or low, tw
UNIT
V
25
ns
Setup time, data before CLK't.lsu
16.5
ns
Hold time, data after CLK'!'. th
12.5
ns
1
ILF
Phase compensation capaCitance, Ccomp (see Note 1)
g
75k
Load resistance. RL
0
70
-55
125
ITLC5602C
Operating free-air temperature.TA
JTLC5602M
NOTE 1: The phase compensation capacitor should be connected between COMP and ANLG GND.
·C
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I inputs
VI-OV
±1
lref
Input reference current
Vref=4 V
Full-scale analog output voltage
VOO
ro
Output resistance
MAX
±1
VFS
Zero-scale analog output voltage
TYP*
VI=5V
IlL
VZS
MIN
I Digital
High-level input current
LOW-level input current
IIH
=5 V. Vref -
10
UNIT
JLA
JLA
JLA
mV
TLC5602C
VOO-15
3.919
VOO = 5 V, Vr~ - 4.02 V.
TA - full range
TLC5602M
3.919
3.98
4.042
TLC5602M
3.919
3.98
4.062
TA=25·C
TLC5602C
TLC5602M
60
80
120
g
TA - full range§
25
mA
4.02 V
Input capacitance
TA=25·C
fclock - 1 MHz,
Supply current
IDO
fclock - 20 MHz, Vref = VOO-0.95 V
* All typical values are at VOO = 5 V and TA - 25·C.
.
§ Full range for the TLC5602C is O·C to 70·C, and full range for the TLC5602M is -55·C to 125·C.
Ci
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
VOO VOO+15
3.98
4.042
15
16
V
pF
TLC5602C,TLC5602M
VIDEO 8-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS023C - FEBRUARY 1989 - REVISED MAY 1995
operating characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
El(adj)
Linearity error, best-straight-line
TA-25·C
t
Linearity error, end point
ED
Linearity error, differential
Gdiff
Differential gain
TYpt
MAX
UNIT
±O.2%
±O.2%
TlC5602M
TA = full range:!:
El
MIN
TlC5602C
TA c full rangei
±O.4%
±0.15%
±0.2%
0;7%
~iff
Differential phase
NTSC 4D-IRE modulated ramp,
fclock 14.3 MHz, Zl
I
GI
i'
~
-;
•
4.496
Step 129
C
I
~
•
•
CD
~
SteP1~8 V
' - Step~27 L
-
4.488
GI
!
/'
-;
CD
I
.
g
I
~
8
8
... ... .....,..
... .
~
;:
§
y'
~:!L
), ....
3.984 ICx
r-r -
I
ELi
I
~i- Vzs
Olgltallnput Code
Olgltellnput Code
OUTPUT RESISTANCE
vs
FREE·AIR TEMPERATURE
100
~
.&
:::I
3.98
-;
0
ien
e
~
....~
4
3.99
3.97
./
I!l
VOO=5V
VOO = Vo = 0.5 V
Oata Input = FF
95
~
90
".,.
/
./
Cl
85
8c
80
I
,/
!
J-;
3.96
.&
:::I
3.95
I
>
....
......
Figure 3
VOO=5V
Vref= 4.02 V
See Note A
CD
!
Best·Flt Straight Line I--
....
4.02
CD
r
• ••
ZERO·SCALE OUTPUT VOLTAGE
vs
FREE·AIR TEMPERATURE
4.01
r
T
EL253
L EL2
~
Figure 2
>
I~-
.* .... /~
ELO ~ ~- -*
3.988
..... ......
g §
••• ..
E
~ ~
r~
•
••
c(
~P1
3.98
~--4
4.488
-ic
/'
3.984
EL127
0
Step 2 ~.
3.988
EL128
4.492
.&
:::I
//
•
EL254- ~/ F-'f.1
~.
..... -I-rEL129
•
•
•
4.496
I
~
~- r-/~'
I
4.992
>
//
IVFSI--~55 -
VOO=5V
Vref = 4.02 V
4.996
pV
Step J53
•
•
0
CD
~te ~54, L
1
4.992
4.492
.&
:::I
-ic
5
~
~
I--'"'
~
~
,...-
-
75
. 70
0
65
8
80
I
3.94
3.93
3.92
55
-55 -35 -15
5
25
45
65
85
105
125
TA - Free-Air Temperature - ·C
50
':'55 -35 -15 5
25
45
65
85 105
TA - Free-Air Temperature _·C
NOTE A: Vref is relative to ANLG GNO. VOO is the voltage between
ANLG VOD and DGTL VDD tied together and ANLG GND
and DGTL GND tied together.
125
Figure 5
Figure 4
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-7
TLC5602C,TLC5602M
VIDEO 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS023C - FEBRUARY 1989 - REVISED MAY 1995
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
21
I
V6D = 51V
Vref = 4.02 V
tel!)Ck = 20 MHz
~
20
\
-
is.
a.
:::s
18
(I)
I
Q
E
17
ZER0-5CALE OUTPUT VOLTAGE
vs
REFERENCE VOLTAGE
5
>
vD6=5~
"
4.8 _ TA=25'C
See Note A
/
I
'\
f
..
~
"'"
:::s
~
...........
..........
I
i'-- """- 100....
!
I
fa
>
/
4.4
/
4.2
/
/"
4
3.8
/
3.6
I
16
-55 -35 -15 5
25 45 65 85 105 125
TA - Free-Air Temperature -'C
FigureS
4.6
3.43•4
~
/
3.6
3.8
4
4.2
4.4
4.6
4.8
5
Vref - Reference Voltage - V
NOTE A: Vref is relative to ANLG GNO. VOO is the voltage
between ANLG VOO and OGTL VOO tied together and
ANLG GNO and OGTL GNO tied together.
Figure 7
~1ExAs
3-8
1/
INSTRUMENTS
POST OFFICE BOX 655303 • DAI.LAS, TEXAS 75265
-
TLC5602C,TLC5602M
VIDEO 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS023C - FEBRUARY 1989 - REVISED MAY 1995
APPLICATION INFORMATION
The following design recommendations benefit the TLC5602 user:
•
Physically separate and shield external analog and digital circuitry as much as possible to reduce system
noise.
•
Use RF breadboarding or RF printed-circuit-board (PCB) techniques throughout the evaluation and
production process.
•
Since ANLG GND and DGTL GND are not connected internally, these terminals need to be connected
externally. With breadboards, these ground lines should connect to the power-supply ground through
separate leads with proper supply bypassing. A good method is to use a separate twisted pair for the analog
and digital supply lines to minimize noise pickup.
Use wide ground leads or a ground plane on the PCB layouts to minimize parasitic inductance and
resistance. The ground plane is the better choice for noise reduction.
•
ANLG Voo and DGTL Voo are also separated internally, so they must connect externally. These external
PCB leads should also be made as wide as possible. Place a ferrite bead or equivalent inductance in series
with ANLG Voo and the decoupling capacitor as close to the device terminals as possible before the ANLG
Voo and DGTL Voo leads are connected together on the board.
.
•
Decouple ANLG Voo to ANLG GND and DGTL Voo to DGTL GND with a 1-J.I.F and 0.01-J.I.F capacitor,
respectively, as close as possible to the appropriate device terminals. A ceramic chip capacitor is
recommended for the 0.01-J.I.F capacitor.
•
Connect the phase compensation capacitor between CaMP and ANLG GND with as short a lead-in as
possible.
•
The no-connection (NC) terminals on the small-outline package should be connected to ANLG GND.
•
Shield ANLG VOD, ANLG GND, and A OUT from the high-frequency terminals CLK and D7-DO. Place
ANLG GND traces on both sides of the A OUT trace on the PCB.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75255
3-9
..
3-10
TL5632C
8-81T 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER
•
•
•
•
•
•
•
•
8-Blt Resolution
Linearity ... ±1/2 LSB Maximum
Differential Nonlinearity . .. ±1/2 LSB
Maximum
Conversion Rate . .. 60 MHz Min
Nominal Output Signal Operating Range
VCctoVCc-1 V
TTL Digital Input Voltage
S-V Single Power Supply Operation
Low Power Consumption . .. 350 mW Typ
description
The TL5632C is a low-power ultra-high-speed
video digital-to-analog converter that uses the
Advanced Low-Power Schottky (ALS) process.
The device has a three channel I/O; the red, the
blue, and the green channel. The red, blue, and
green signals are referred to collectively as the
RGB signal. An internally generated reference is
also provided for the standard video output
voltage range. Conversion of digital signals to
analog signals can be at a sampling rate of dc to
60 MHz. The high conversion rate makes the
TL5632C suitable for digital television, computer
digital video processing, and high-speed data
conversion.
FRPACKAGE
(TOP VIEW)
e
044 4342 4140393837363534
(MSB) R1
1
33
.R22
32
R3
3
31
R4
4
30
R5
5
29
R6
6
28
R7
7
27
(LSB) R8
8
26
(MSB) G1
9
25
G2
10
24
G3
11
23
1213 14 15161718192021 22
REF OUT
AVec
CeOMP
DVee
GND
CLKRIN
CLKGIN
CLKBIN
B8 (LSB)
B7
B6
Ne - No intemal connection
The TL5632C is characterized for operation from
DoC to 70°C.
FUNCTION TABLE
STEP
0
1
·•
·
127
128
129
I
DIGITAL INPUT
OUTPUT VOLTAGE
LLLLLLLL
LLLLLLLH
3.980 V
3.984 V
•
•
•
•
•
4.488 V
4.492 V
4.996 V
•
·•
•
·•
254
255
HHHHHHHL
HHHHHHHH
·•
·
LHHHHHHH
HLLLLLLL
HLLLLLLH
•
4.996 V
5.000 V
AVAILABLE OPTIONS
TA
o"Cto 70·e
PACKAGE
T15632CFR
~1ExAs
Copyrtght © 1994. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 66S303 • DAlLAS. TEXAS 75265
3-11
TL56~2C
"
..
' .
8.:BITa;.CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER
. sLAS091.,. DEC.EMBER 19Q4
functional block diagram
ROUT
GOUT
BOUT
~----------~__-----------4--~---------------AVCC
8
8
8
r---CCOMP
'------ REF IN
REF OUT
CLKRIN
R1-R8
CLKG IN
G1-G8
B1-B8
CLKBIN
schematics of outputs
EQUIVALENT OF REF OUT
EQUIVALENT OF ROUT. GOUT. BOUT
AVCC
-.----.AVCC
1 kO
REF OUT
. - - - - - - ROUT. GOUT. BOUT
4kO
--~---GND
.../;&
.
~TEXAS
3-12
"
INsTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL5632C
8-81T 3·CHANNEL HIGH·SPEED DIGITAL·TO·ANALOG CONVERTER
SLAS091 - DECEMBER 1994
Tennlnal Functions
TERMINAL
NAME
NO.
110
DESCRIPTION
18-25
I
~hannel
digital input (Bl= MSB)
BoUT
36
0
~hannel
analog output
CCOMP
CLKBIN
31
26
I
Phase compensation capacitance. A 1 I'f' capacitor is connected from CCOMP to GND.
~hannel clock input
CLKGIN
27
I
G-channel clock input
CLKRIN
28
I
R-channel clock input
Gl- Ga
GND
11-16
I
G-Channel digital input (Gl- MSB)
Bl- B8
29,35,37,
39,41
36
Ground. All GND terminals are connected intemally; however, all GND terminals should be connected
externally to a ground plane or equivalent low impedance ground retum.
0
GOUT
NC
17,44
Rl- Ra
1-8
I
40
0
ROUT
AVCC
DVCC
REF IN
REF OUT
G-channel analog output
No connection internally
32,42
R-channel digital input (R 1- MSB)
R-channel analog output
Analog power supply voltage
30,43
Digital power supply voltage
34
I
Reference voltage input. REF IN accepts the reference voltage on REF OUT. An extemal reference can also
be applied consistent with Note 1.
33
0
Reference voltage output. An internal voltage divider generates the voltage level (see schematics of outputs,
page 2).
NOTE 1: Vee - VrefS 1.2 V
absolute maximum ratings over operating free-air temperature range (unless otherwise noted}t
Power supply voltage range, AVec, DVee (see Note 2) ................................. -0.3 V to 7 V
Digital input voltage range,V, •.................................................... -0.3 V to DVec
Analog output voltage range, ROUT, GOUT, BOUT, eCOMP (externally applied) .... -0.3 V to AVec + 0.3 V
Reference input range, REF IN ............................................. -0.3 V to AVec + 0.3 V
Reference output range, REF OUT ......•...•...•........................... -0.3 V to AVec + 0.3 V
Operating free-air temperature range, TA ......•.•..................................... DoC to 70°C
Storage temperature range ..•....•.......•....................................... -65°C to 150°C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds ... . . . . . . . . . . . . . . . . . . . . . . . • . . .. 260°C
t Stresaes beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 2: All voltage values are with respect to GND.
~TEXAS
INSTRUMENTS
POST OFFICE eox 856303 • DAlLAS. TEXAS 75285
3-13
TL5632C
8·BIT 3·CHANNEL HIGH·SPEED DIGITAL·TO·ANALOG CONVERTER
SLAS091 - DECEMBER 1994
recommended operating conditions
I
Supply voltage, AVcc, OVCC
MIN
NOM
MAX
4.75
5
5.25
2
High-level input voltage, VIH
V
V
0.8
Low-level input voltage, VIL
3.8
Reference voltage, Vref (see Note 1)
UNIT
4
4.2
V
V
10
ns
Hold time, data after CLKi, th1
3
ns
Pulse duration at high level, tw1
8.3
ns
Pulse duration at low level, tw2
8.3
ns
Setup time, data before CLKi, tsu1
Extemal phase Compensation capacitance, CCOMP
1
Operating free-air temperatiJre, TA
0
70
I1F
·C
NOTE 1: VCC - Vref ~ 1.2 V
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYPt
MAX
Resolution
8
20
High-level input current
VCC = 5.25 V,
VIH=2.7V
IlL
Low-level input current
=
Reference input current
VCC 5.25 V,
REF IN -4 V
VIH =2.7V
Iref
Vref
Reference output voltage
VCC-5V,
With intemal reference
VFS
Full-scale analog output voltage
VIH=2V,
REF IN-4 V
VZS
Zero-scale analog output voltage
VIL=0.8V,
REF IN=4 V
IIH
-400
10
4
3.8
AVCC- 15
3.9
4.2
AVCC
3.98
AVCC+15
4.05
UNIT
Bit
I1A
I1A
I1A
V
mV
V
RGB full-scale ratio
0%
4%
8%
Zo
Output impedance
200
240
280
0
ICC
Supply current
70
90
rnA
operating characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
EL
Linearity error
Endpoint,
EO
Oifferentiallineanty error
REF IN_4 V
fc
Maximum conversion rate
TYpt
tpLH
Propagation delay time, low-to-high level
Propagation delay time, high-to-Iow level
tr
Rise time
tf
Fall time
UNIT
±0.5
LSB
CL~5pF:t:
10
5
5
t All typical values are at Vce = 5 V, TA = 25·C.
:t: CL includes probe and jig capacitances.
~1ExAs
INSTRUMENTs
POST OFACE BOX 655303 • DALLAS. TEXAS 75265
LSB
MHz
10
TA=25·C,
MAX
±0.5
60
tpHL
3-14
MIN
REF IN =4 V
ns
ns
--~
TL5632C
8·BIT 3-CHANNEL HIGH·SPEED DIGITAL·TO·ANALOG CONVERTER
SLAS091 - DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
CLKRIN,CLKGIN,CLKBIN
(Clock)
o
ROUT, GOUT, BOUT
(Analog Output)
TYPICAL CHARACTERISTICS
5--------------4.996
>
VFS
--------------
------------
I
t
~
J
f
I
~
J.
EL128~
4.496
.j.
4.492
il
1
4.488
3.988
3.9801~-'----L---I----L-.L----L-'--+
LSB---'g
MSB---.I
I I ...
~
VZS
;::
... § §
g
,..
0
0
0
8 § §
g
8
0
Digital Input Code
0
,..
,..
,..
n EL128
I
I
1
I
I
I
1
1
1
I
I
I
I
I
,..
... E ~ 8 ... E
,..
0
g
0
~
~
;::
,..
,..
,..
,..
,..
,..
,..
;::
Digital Input Code
Figure 1. Ideal Conversion Characteristics
-!!1I.
Figure 2. End-Point Linearity Error
TEXAS
NSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
3-15
TL5632C
8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER
SLAS091 - DECEMBER 1994
APPLICATION INFORMATION
The following design procedures should be used for optimum operation.
•
External analog and digital circuitry should be physically separated arid shielded as much as possible to
reduce system noise.
•
RF breadboarding or RF printed-circuit-board (PCS) techniques should be used throughout the evaluation
and production process.
•
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. A ground plane is the better choice for noise reduction.
•
AVec and DVccare also separate internally, so they must be connected externally. These external PCB
leads should also be made as wide as possible. A ferrite bead or equivalent inductance should be placed
in series with AVec and the decoupling capacitor before the AVec and DVCC leads are connected together
on the board. It is critical that the supply voltage applied to AVec be as noise free and ripple free as possible.
Ripple and noise rejection should be a minimum of 60 dB below the full-scale output range of 1 V
peak-to-peak.
.
•
AVec to GND and DVcc to GND should be decoupled with 3.3-¢= and O. hlF capacitors, respectively, as
close as possible to the appropriate device terminals. A·ceramic chip capacitor is recommended for the
0.1-¢= capacitor.
. .
•
The phase compensation capacitor should be connected between CCOMP and GND with as short a lead-in
as possible.
•
The no-connection (NC) terminals on the small-outline package should be connected to GND.
•
AV cc' DVcc' and ROUT, GOUT, and BOUT should be shielded from the high-frequency terminals CLKR IN,
CLKG IN ,and CLKs IN and the input data terminals. GND traces should be placed on both sides ofthe ROUT,
GOUT, and BOUT traces on the PCB to the following signal processing stage. These output traces should
be as short as possible.
~1ExAs
3-16
.
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75265
TL5632C
8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER
SLAS091 - DECEMBER 1994
APPLICATION INFORMATION
DVCC ,
1
AVCC :::
3.3 lifT
a
l
...L
3.3 lifT
fO.1 IlF
":" T
":"
0.111f
144 43 42 4140 39 3a 37 36 35 34
~ 88i!!5i!!5i! !5i!ii!!:
::0:00 CJOCJOCJOCJIL
cOC
a
1 R1(MSB)
2 R2
3 R3
4
~
5 R5
6 R6
7 R7
8 Ra(lSB)
r.:
a
Buffer
a
3
Buffer I
RouT
...L
±i
i~GOU T
ic
I~BOU T
a
Buffer
i~
II:
CJ
III
l
":"
TO.1IlF
":"
~
REF OUT 33
AVCC 32
CCOMP 31
DVCC 30
TL5632C
9 G1(MSB)
10 G2
11 03
CJV CJII>
iii
iii
(I)
(I)
::::!.
i§.
c! c5" CJ= ~
mIII~ :
GND
ClKRIN
ClKGIN
ClKBIN
(lSB)Ba
B7
B6
0.1
IIf
-'I111f ":"
TO.11lF -=-
~
2a
27
26
25
~
~
IIIv 11111>
3
112 13 14 15 16117 1a19 2021 22
a
I
Buffer I
NOTES: A. Buffers are SN74AS244 or equivalent.
B. 0.1 IlF capacitors should be placed as close to the device terminals as possible.
C. The coupling capacitor (CC) value is application specific and selectable by the user.
Figure 3. Typical Bypass, Buffer, and Output Configuration
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-17
-
3-18
TLC5620C, TLC56201
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
1995
NOR D PACKAGE
(TOP VIEW)
•
Four 8-Bit Voltage Output DACs
•
5-V Single-Supply Operation
•
•
•
Serial Interface
High-Impedance Reference Inputs
Programmable 1 or 2 Times Output Range
•
Simultaneous-Update Facility
•
Internal Power-On Reset
•
•
Low Power Consumption
Half-Buffered Output
GND
REFA
REFB
REFC
REFD
DATA
1
6
VDD
LDAC
DACA
DACB
DACC
9 DACD
applications
•
•
Programmable Voltage Sources
Digitally-Controlled AmplifiersJAttenuators
•
Mobile Communications
•
•
Automatic Test Equipment
Process Monitoring and Control
•
Signal Synthesis
description
The TLC5620C and TLC56201 are quadruple 8-bit voltage output digital-to-analog converters (DACs) with
buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either
one or two times the reference voltages and GND, and the DACs are monotonic. The device is simple to use,
running from a single supply of 5 V. A power-on reset function is incorporated to ensure repeatable start-up
conditions.
Digitai control ofthe TLC5620C and TLC56201 are over a simple 3-wire serial bus that is CMOS compatible and
easily interfaced to all popular microprocessor and microcontroller devices. The 11-bit command word
comprises 8 bits of data, 2 DAC select bits and a range bit, the latter allowing selection between the times 1 or
times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be written
to the device, then all DAC outputs updated simultaneously through control of the LDAC terminal. The digital
inputs feature Schmitt triggers for high noise immunity.
The 14-terminal small-outline (SO) package allows digital control of analog functions in space-critical
applications. The TLC5620C is characterized for operation from O°C to 70°C. The TLC56201 is characterized
for operation from -40°C to 85°C. The TLC5620C and TLC56201 do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
(D)
TA
PLASTIC DIP
(N)
O·Cto 70·C
TLC5620CD
TLC5620CN
-40·C to 85·C
TLC5620lD
TLC5620lN
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
3-19
TLC562OC,.TLC56201
QUADRUPLE 8-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS081A- NOVEMBER 199~ - REVISED JANUARY 1996
functional block diagram,
REFA
-----------r-,
---I~>-.....
>-..--DACA
REFB - - - f
>-.....--DACB
REFC
>-.....--DACC
REFD
---I
>-.....--DACD
ClK _ _
r---a.. . . . . ""---..,
Serial
Interface
DATA - - - - I
LOAD
---L__- - - - . J
LDAC
r;::;:l
L.:::..J
Tennlnal Functions
TERMINAL
NO.
7
NAME
ClK
DACA
DACB
12
DACC
DACD
10
11
DATA
9
6
GND
1 '
lDAC
13
lOAD
8
REFA
REFB
2
3
REFC
4
REFD
5
14
VDD
DESCRIPTION
110
I
0
0
0
0
I
I
I
I
I
I
I
I
I
Serial-interface clock, data enters on the negative edge
DAC A analog output
DAC B analog output
DAC C analog output
DAC D analog output
Serial-interface digltaklata input
Ground return and reference terminal
DAC-update latch control
Serial-interface load control
Reference voltage Input to DACA
Reference voltage input to DACB
Reference voltage input to DACC
Reference voltage Input to DACD
Positive supply voltage
detailed description
The TLC5620 is implemented using four reSistor-string digital-to-analog converters (DACs). The core of each
DAC is a single resistor with 256 taps, corresponding to the 256 possible codes listed in Table 2. One end of
each resistor string is connected to the GND terminal and the other end is fed from the output of the reference
input buffer. Monotonicity is maintained by use of the resistor strings. Linearity depends upon the matching of
the resistor elements and upon the performance of the output buffer. Because the inputs are buffered, the DACs
always presents a high-impedance load to the reference source.
~TEXAS
3-20
INSTRUMENTS
POST OFFICE BOX 8663\l3. DALlAS. TEXAS 75285
TLC5620C, TLC56201
QUADRUPLE 8-BIT DIGITAL·lO·ANALOG CONVERTERS
SLAS081 A- NOVEMBER 1994 - REVISED JANUARY 1996
detailed description (continued)
Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or
times 2 gain.
On powerup, the DACs are reset to CODE O.
Each output voltage is given by:
VO(DACAIBICID)
= REF
x C~~E x (1 + RNG bit value)
where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial-control word.
data interface
With lOAD high, data is clocked into the DATA terminal on each falling edge of ClK. Once all data bits have
been clocked in, lOAD is pulsed low to transfer the data from the serial-input register to the selected DAC as
shown in Figure 1. If lDAC is low, the selected DAC output voltage is updated and lOAD goes low. If lDAC
is high during serial programming, the new value is stored within the device and can be transferred to the DAC
output at a later time by pulsing lDAC low as shown in Figure 2. Data is entered MSB first.
CLK
--I
14-
11
tsu(DATA"CLK)
tsu(LOAD-CLK)
14-- tv(DATA-CLK)
--t---_-...~
DATA
LOAD
Figure 1. LOAD-Controlled Update (LDAC
=Low)
CLK
DATA
D1
DO
tsu(LOAD-LDAC) ---j4-+I
\....+'' ' ' '+1-
LOAD
tW(LDAC)~1
V
LDAC
I
DACUpdate
Figure 2. LDAC-Controlled Update
data interface (continued).
Table 1 lists the A1 and AO bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.
~TEXAS .
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS. TEXAS 75265
3-21
-
TLC5620C, TLC56201
QUADRUPLE 8-81T DIGITAL·TO·ANALOG CONVERTERS
SLAS081A- NOVEMBER 1994- REVISED JANUARY 1995 .
Table 1. Serial-Input Decode
OACUPOATEO
A1
AQ
0
0
DACA
0
1
DACB
1
0
DACC
1
1
DACD
Table 2. Ideal-Output Transfer
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
GND
0
0
0
0
0
0
0
1
(1/256)( REF (1+RNG)
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
·
•
•
0
·
•
•
1
(127/256)( REF (1+RNG)
1
0
0
0
0
0
0
0
(1281256)( REF (1+RNG) .
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
(2551256) )( REF (1 +RNG)
·
· · · ·
·
OUTPUT VOLTAGE
equivalent inputs and outputs
INPUT CIRCUIT
-
.......-
I
OUTPUT CIRCUIT
-
VOO
......-VOO
Input from
Oecoded OAC
Register String
V~
OAC
Voltege Olltput
Input
ToOAC
Resistor
String
- - - -.....~-GNO
601lA
....- -..... GNO
~TEXAS
3-22
ISINK
Typlcsl
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5620C, TLC56201
QUADRUPLE a-BIT DIGITAL-TO-ANALOG CONVERTERS
SLASOB1A- NOVEMBER 1994 - REVISED JANUARY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted}t
Supply voltage (Voo - GND) .•............................................................... 7 V
Digital input voltage range ............................................. GND - 0.3 V to Voo + 0.3 V
. Reference input voltage range, VID ...................................... GND - 0.3 V to Voo + 0.3 V
Operating free-air temperature range, TA: TLC5620C .................................... O°C to 70°C
TLC56201 ................................... -40°C to 85°C
Storage temperature range, Tstg .................................................. -50°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 230°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
4.75
Supply voltage, VDD
High-level digital input voltage, VIH
MAX
UNIT
5.25
V
V
0.8VDD
low-level digital input voltage, Vil
0.8
Reference voltage, Vref [AIBICIDj
V
V
VDD-1.5
load resistance, Rl
10
kn
Setup time, data input, tsu(DATA-ClK) (see Figures 1 and 2)
50
ns
Valid time, data input valid after elK!, tv(DATA-ClK) (see Figures 1 and 2)
50
ns
Setup time, ClK 11th falling edge to lOAD, tsu(ClK-lOAD) (see Figure 1)
50
ns
Setup time, LOADi to ClK!, tsu(lOAD-ClK), (see Figure 1)
50
ns
Pulse duration, lOAD,lw(lOAD) (see Figure 1)
250
ns
lDAC,lw(lD~C)
250
ns
Pulse duration,
(see Figure 1)
Setup time, LOADi to LDAC!, tsu(lOAD-lDAC) (see Figure 1)
0
ClK frequency
Operating free-air temperature, TA
ns
1
I TlC5620C
ITlC56201
MHz
0
70
·C
-40
85
·C
~TEXAS
INSTRUMENTS .
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-23
TLC5620C, TLC56201
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS081 A - NOVEMBER 1994 - REVISED JANUARY 1995
electrical characteristics-over recommended operating 'free-air temperature range; Vee = 5 V ±5%,
Vref = 2 V, x 1 gain output range (unless otherwise noted)
MAX
UNIT
IIH
High-level digital input current
PARAMETER
VI =VDD
±10
IlL
Low-level digital input current
VI =OV
±10
IO(sinkl
Output sink current
I1A
I1A
I1A
IO(sourcel
Output source current
Ci
TEST CONDITIONS
MIN
20
Each DAC output
15
- I Reference input capacitance
IDD
Supply current
VDD .. 5V
Reference input current
VDD=5V,
EL
Linearity error (end point corrected)
Vre f- 2V,
Vre f- 2V,
Differential-linearity error
EZS
EFS
PSRR
pF
15
Iref
Zero-scale error
rnA
2
I Input capacitance
ED
TYP
2
Vre f=2 V
x2 gain (see Note 1)
x 1 gain (see Note 2)
x 2 gain (see Note 3)
Zero-scale error temperature coefficient
Vref=2V,
Vre f=2V,
Full-scale error
Vref- 2 V,
x 2 gain (see Note 5)
Full-scale error temperature coefficient
x 2 gain (see Note 6)
Vref= 2 V,
See Notes 7 and S
Power-supply sensitivity
0
x 2 gain (see Note 4)
mA
±10
I1A
±1
LSB
±0.9
LSB
30
mV
I1vrc
10
±60
mV
±25
I1V/o C
0.5
mVN
NOTES: 1. Integral nonlinearity (INl) is the maximum deviation of the output from the line between zero and full scale (excluding the effects
of zero code and fuJI-scale errors).
'
2. Differential nonlinearity (DNl) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
3. Zero-scale error Is the deviation from zero voltage output when the digHal input code is zero.
4. Zero-seale error temperature coefficient is given by: ZSETC - [ZSE(Tmax) - ZSE(T min)]Nref x 106/(T max - Tmin).
5. Full-scale error is the deviation from the ideal full-scale output (Vref - 1 LSB) with an output load of 10 kn.
6. Full-scale temperature coefficient is given by: FSETC .. [FSE(T max) - FSE (T minllNref x 106/(Tmax - Tmin).
7. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the VDD voltage from 4.5 V to 5.5 V de and measuring the proportion
of this signal imposed on the zero-code output voltage.
S. Full-scale error rejection ratio (FSE-RR) is measured by varing the VDD from 4.5 V to 5.5 V dc and measuring the proportion ofthis
signal imposed on the full-scale output voltage.
=
operating characteristics over recommended operating free-air temperature range, Vee 5 V ±5%,
Vref 2 V, x 1 gain output range (unless otherwise noted)
=
TEST CONDITIONS
Output slew rate
Cl= 100pF,
Output settling time
To 0.5 lSB,
MIN
RL= 10kO
Rl= 10kO,
See Note 9
TYP
MAX
UNIT
1
V/IJ.S
10
100
IJ.S
kHz
large-signal bandwidth
Cl - 100 pF,
Measured at-3 dB point
Digital crosstalk
ClK = 1-MHz square wave measured at DACA-DACD
-50
dB
Reference feedthrough
See Note 10
-60
dB
Channel-to-channel isolation
See Note 11
-60
dB
Reference input bandwidth
See Note 12
100
kHz
..
d
NOTES: 9. Settling time IS the lime for the output signal to remain within ±0.5 LSB of the final measured value for a dlgHallnput code change
of 00 hex to FF hex or FF hex to 00 hex. For TlC5620C: VDD - 5 V, Vref = 2 V and, range = x2. For TlC56201: VDD - 3 V,
Vref - 1.25 V and range x2.
10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input _ 1 V de + 1 Vpp at 10kHz.
11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex
with Vref input = 1 V dc + 1 Vpp at 10 kHz.
12. Reference bandwidth is the -3 dB bandwidth with an input at Vref _ 1.25 V dc + 2 Vpp , with a digital input code of full-scale.
~TEXAS
3-24
INSTRUMENTS
POST OFFICE BOX 655303. DALLAS. TEXAS 75265
TLC5620C, TLC56201
QUADRUPLE 8-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS081A- NOVEMBER 1994 - REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
TLC5620
DACA
DACB
1--__.-.....,
101<0
•
•
CL=100pF
DACD
Figure 3. Slewing Settling Time and Linearity Measurements
I
L~AC
3
I
,..
VDD-eV
TAde-c
!
Code 00 to FF Hexl
Rlnge_x2
I
Vref= 2 V
I
>
I
~
I
~
!;
2
4
8
\.
'\
~
!;
= !.p
I
8
10
14
18
18
-o
-
>
I
ii
=
I
~
'>
\ ....
0
12
5
I
VDD=5V
TA=25°C
Code FF to 00 Hex
Range=x2
Vret=2 v
\
2
'>
: LI
o
I
ca.
I
T
I
>
• •
I I
.I
LDAC
3
0
I
I
I
o
5
o
2
4
t-nme-1J8
8
8
10
12
14
18
18
t-Tlme-1J8
Figure 4. Positive Rise and Setting
nmeVDD=5V
Figure 5. Negative Fall and
Setting Time VDD = 5 V
:lllExAs
INSTRUMENTS
POST OFFICE BOX 656303 • DAlLAS, TEXAS 75265
3-26
TLC5620C, TLC56201
QUADRUPLE 8-81T DIGITAL·TO·ANALOG CONVERTERS
SLAS081A- NOVEMBER 1994 - REVISED JANUARY 199&
TYPICAL CHARATERISTICS
OUTPUT SOURCE CURRENT
1
~
7
I
6
::0
0
CD
e::0
0
II)
-;
S-
dI
I
vs
OUTPUT VOLTAGE
TEMPERATURE
--.....
8
5
SUPPLY CURRENT
vs
.......
"'-'\",
1.15
1
1.1
l
1.05
G
b
8:
ci
0.95
I
\
4
1.2
VOO=5V
TA = 25DC
Vref=2V Range=x2
Input Code = 255
3
\
-
,,--
.............
VOO =5V
Vref 2V
Range=x2
Input Code = 255
.........
I
c
E
2
0.9
::0
!
0.85
.9
0
0
2
3
4
Vo - Output Voltage - V
0.8
-50
5
o
RELATIVE GAIN
-2
-4
III
-6
~
~'ii
-8
"I
a:
I
CJ
RELATIVE GAIN
vs
vs
FREQUENCY
FREQUENCY
"\
10
-10
-12
-14
~
0
\
_ VOO=5V
-16
TA=25DC
-18 _ Vref = 1.25 Vdc + 2 Vpp
Input Code = 255
I
-20
10
1
100
f - Frequency - kHz
III
-10
iii
-20
"cI
\
1
\
\
\
\
CJ
\
\
~
'Iii
;!
I
CJ
-30
VOO=5V
D
-40 I- TA = 25 C
Vrer = 2 Vdc + 0.5 Vpp
Input Code = 255
-50
\
-60
1000
\
\
\~
V
1
FigureS
10
100
1000
f - Frequency - kHz
Figure 9
~TEXAS
3-26
100
Figure 7
Figure 6
0
50
t - Temperature - DC
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10000
TLC5620C, TLC56201
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLASOS1 A- NOVEMBER 1994 - REVISED JANUARY 1995
APPLICATION INFORMATION
TLC5620
DACA 1-----4.---I+~
DACB
•
Vo
R
•
DACD
NOTE A: Resistor R ., 10 kO
Figure 10. Output Buffering Schemes
~1ExAs
INSTRUMENTS
POST OFFICE eox 655303 • DALlAS, TEXAS 75265
3-27
3-28
TLC5628C, TLC56281
OCTAL 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS089A- NOVEMBER 1994 - REVISED JANUARY 1995
•
•
•
•
•
•
•
•
•
N OR DW PACKAGE
(TOP VIEW)
Eight 8-Blt Voltage Output DACs
5-V Single-Supply Operation
Serlallnterface
High-Impedance Reference Inputs
Programmable 1 or 2 Times Output Range
Simultaneous-Update Facility
Internal Power-On Reset
Low Power Consumption
Half-Buffered Output
DACB
DACA
GND
1
DACC
DACD
REF1
LDAC
LOAD
REF2
DACH
DACG
applications
•
•
•
•
•
•
Programmable Voltage Sources
Digitally-Controlled AmpllflerslAttenuators
Mobile Communications
Automatic Test Equipment
Process Monitoring and Control
Signal Synthesis
description
The TLC5628C and TLC56281 are octal 8-bit voltage output digital-to-analog converters (DACs) with buffered
reference inputs (high impedance). The DACs produce an output voltage that ranges between either one or two
times the reference voltages and GND and are monotonic. The device is simple to use, running from a single
supply of 5 V. A power-on reset function is incorporated to ensure repeatable start-up conditions.
Digital control of the TLC5628C and TLC56281 are over a simple 3-wire serial bus that is CMOS compatible and
easily interfaced to· all popular microprocessor and microcontroller devices. The 12-bit command word
comprises 8 bits of data, 3 DAC select bits and a range bit, the latter allowing selection between the times 1 or
times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be written
to the device, then all DAC outputs updated simultaneously through control of the LDAC terminal. The digital
inputs feature Schmitt triggers for high noise immunity.
The 16-terminal small-outline (DW) package allows digital control of analog functions in space-critical
applications. The TLC5628C is characterized for operation from O·C to 70·C. The TLC56281 is characterized
for operation from -40·C to 85·C. The TLC5628C and TLC56281 do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
(OW)
PLASTIC DIP
IN)
O·C10 70·C
TLC5628CDW
TLC5628CN
-40·C 10 85·C
TLC56281DW
TLC56281N
TA
~1ExAs
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS, TEXAS 75265
3-29
TLC5628C, TLC56281
OCTAL 8-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS089A- NOVEMBER 1994 - REVISED JANUARY 1995
functional block diagram
REF1
:>-....- - DACA
••
>-....---.,.REF2
.'
DACD
--~'.... '}....+++------+------t~r-'
:>-....- - DACE
••
•
>--+--
DATA - - - - I
LOAD
Serial
Interface
LDAC
--"L....-__---1
DACH
Power-On
Reset
Terminal Functions
TERMINAL
NAME
NO.
DESCRIPTION
I/O
CLK
5
I
Serial-interface clock, data enters on the negative edge
DACA
2
DACA analog output
DACB
1
DACC
16
DACD
15
DACE
7
DACF
8
DACG
DACH
9
10
0
0
0
0
0
0
0
0
DATA
4
I
Serial-interface digital data inpui
GND
3
I
Ground retum and reference terminal
LDAC
13
I
DAC-update latch control
LOAD
12
Serial-interface load control
REF1
14
I
I
REF2
11
I
Reference voltage input to DACe
6
I
Positive supply voltage
VDD
DACB analog output
DACC analog output
DACD analog output
DACE analog output
DACF analog output
DACG analog output
DACH analog output
Reference voltage Input to DACA
detailed description
The TLC5628 is implemented using eight reSistor-string digital-to-analog converters (DACs). The core of each
DAC is a single resistor with 256 taps, corresponding to the 256 possible codes listed in Table 2. One end of
each resistor string is connected to the GND terminal and the other end is fed from the output of the reference
~TEXAS
3-30
INSTRUMENTS
POST O~FICE BOX 655303 • DALlAS. TEXAS 75265
TLC5628C, TLC56281
OCTAL 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS089A- NOVEMBER 1994 - REVISED JANUARY 1995
input buffer. Monotonicity is maintained by use of the resistor strings. Linearity depends upon the matching of
the resistor elements and upon the performance of the output buffer. Because the inputs are buffered, the DACs
always present a high-impedance load to the reference sources. There are two input reference terminals; REF1
is used for DACA through DACD and REF2 is used by DACE through DACH.
Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or
times 2 gain.
On powerup, the DACs are reset to CODE O.
Each output voltage is given by:
VO{DACAIBICIDIEIFIGIH)
= REF
x C~~E x (1
+ RNG bit value)
where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial-control word.
data interface
With lOAD high, data is clocked into the DATA terminal on each falling edge of ClK. Once ali data bits have
been clocked in, lOAD is pulsed low to transfer the data from the serial-input register to the selected DAC as
shown in Figure 1. If LDAC is low, the selected DAC output voltage is updated and lOAD goes low. If lDAC
is high during serial programming, the new value is stored within the device and can be transferred to the DAC
output at a later time by pulsing lDAC low as shown in Figure 2. Data is entered MSB first.
CLK
... r.- tsu(DATA-CLK)
l--j
I
tsu(LOAD-CLK)
I.- tY(DATA-CLK)
DATA
04
~--I;----tsu(CLK-LOAD)
rr
~LL.J....
I
[ I , tw(LOAD)
~
jJ
LOAD
r
Figure 1. lOAD-Controlled Update (lDAC
=Low)
I
DACUpdate
CLK
D4~~_______
DATA
~S
tsU(LOAD-,LDV,....~-t!_ _
LOAD
II
II
LDAC
tw(LDAC) ~
V
DACUpdate
Figure 2. LDAC·Controlied Update
data interface (continued)
Table 1 lists the A1 andAO bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-31
TLC5628C, TLC56281
OCTAL 8-81T DIGITAL·TO-ANALOG CONVERTERS
SLAS089A- NOVEMBER 1994 - REVISED JANUARY 1995
Table 1. Serial-Input Decode
A2
A1
AO
0
0
0
0
0
0
0
1
0
1
DACD
1
0
DACE
1
0
0
1
DACF
1
1
0
DACG
1
1
1
DACH
1
1
DACUPDATED
DACA
DAce
DACC
Table 2. Ideal-Output Transfer
D7
D8
05
04
D3
02
01
DO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
OUTPUT VOLTAGE
GND
(11256) x REF (1+RNG)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
1
1
1
1
1
1
1
(1271256) x REF (1+RNG)
1
0
0
0
0
0
0
0
(128/256) x REF (1+RNG)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
(2551256) x REF (1+RNG)
1•
equivalent of Inputs and outputs
INPUT CIRCUIT
-
.....-
OUTPUT CIRCUIT
-
VDO
Input from-.....I-""....
Decoded OAC
>----.r...,
Register String
Vref
Input
ToOAC
DAC
Voltage Output
ISINK
Resistor
eo"",
Sb1ng
841cQ
~--""'~~GNO
~plC8I
....--4.-..... GND
~1ExAs
3-32
.....-VDD
INS1RUMENTS
POST OFFICE BOX _
• DALLAS. TEXAS 75265
TLC5628C, TLC56281
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089A- NOVEMBER 1994 - REVISED JANUARY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (Voo - GND) ................................................................. 7 V
Digital input voltage range, VID ......................................... GND - 0.3 V to Voo + 0.3 V
Reference input voltage range .......................................... GND - 0.3 V to Voo + 0.3 V
Operating free-air temperature range, TA: TLC5628C .................................... O°C to 70°C
TLC56281 ................................... -40°C to 85°C
Storage temperature range, T5t9 .................................................. -50°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ....... . . . . . . . . . . . . . . . . . . . . . . .. 230°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
4.75
Supply voltage, VDD
High-level digital input voltage, VIH
MAX
5.25
0.8
Reference voltage, Vref [AIBICIDIEIFI(3IH]
V
V
0.8 VDD
Low-level digital input voltage, VI L
UNIT
V
load resistance, Rl
10
V
kn
VDD-1.5
Setup time, data input, tsu(DATA-ClK) (see Figures 1 and 2)
50
ns
Valid time, data input valid after ClK.!., tv(DATA-CLK) (see Figures 1 and 2)
50
ns
Setup time, CLK 11th falling edge to lOAD, !su(CLK-lOAD) (see Figure 1)
50
ns
Setup time, LOADi to ClK.!., tsu(LOAD-ClK) (see Figure 1)
50
ns
Pulse duration, LOAD, tw(LOAD) (see Figure 1)
250
ns
Pulse duration, LDAC, tw(LDAC) (see Figure 2)
250
ns
Setup time, LOADi to LDAC.!., tsu(LOAD-LDAC) (see Figure 2)
0
CLK frequency
Operating free-air temperature, TA
ITLC5628C
ITLC56281
ns'
1
MHz
0
70
·C
-40
85
·C
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-33
TLC5628C, TLC56281
OCTAL 8·BITDIGITAL·TO·ANALOG CONVERTERS
SLAS089A ~ NOVEMBER 1994 - REVISED JANUARY 1995
electrical characteristics over recommended operating free-air temperature range, Voo =5 V ± 5%,
Vref = 2 V, x 1 gain output range (unless otherwise noted)
MAX
UNIT
IIH
High-level digital input current
VI-VOO
±10
IlL
Low-level digital input current
VI-OV
±10
IO{sinkl
Output sink current
11A
11A
11A
IO{sourcel
Output source current
PARAMETER
Ci
TEST CONDITIONS
2
rnA
II nput capacitance
15
I Reference input capaCitance
15
Supply current
VOO =5V
lref
Reference input current
VOO R5V,
EL
Linearity error (end point corrected)
Vref= 2 V,
ED
Differential-linearity error
Zero-scale error
Vref= 2 V,
Vref=2V,
x 2 gain (sea Note 2)
EZS
Zero-scale error temperature coefficient
Vref= 2 V,
><2 gain (see Note 4)
Full-scale error
Vref=2V,
x 2 gain (see Note 5)
Full-scale error temperature coefficient
x 2 gain (see Note 6)
Vref= 2 V,
See Notes 7 and 8
PSRR
TYP
20
Each OAC output
100
EFS
MIN
Power-supply sensitivity
pF
4
Vref- 2 V
x 2 gain (see Note 1)
x 2 gain (see Note 3)
0
mA
±10
11A
±1
LSB
±0.9
LSB
30
mV
±60
fJ.VI"C
mV
10
±25
fJ.VI"C
mVN
0.5
NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects
of zero code and full-scale errors).
2. Differential nonlinearity (ONL) is the difference between the measured and Ideal 1 LSB amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as II change in the digital input code.
3. Zero-scale error Is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale error temperature coefficient is given by: ZSETC - [ZSE(T max) - ZSE(Tmin)]Nref x 106/(Tmax - Tmin>.
5. Full-scale error is the deviation from the ideal full-scale output (Vref - 1 LSB) with an output load of 10 kO.
6. Full-scale temperature coeffiCient Is given by: FSETC - [FSE(Tmax) - FSE (T min)]Nref xl06/(T max - Tmin).
7. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the VOO voltage from 4.5 V to 5.5 V de and measuring the proportion
of this Signal imposed on the zero-code output voltage.
8. Full-scale error rejection ratio (FSE-RR) is measured by varing the VOO from 4.5 V to 5.5 V de and measuring the proportion of this
sign~1 imposed on the full-scale output voltage.
=
operating characteristics over recommended operating free-air temperature range, Voo 5 V ± 5%,
Vref = 2 V, x 1 gain output range (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output settling time
CL =100 pF,
To 0.5 LSB,
Large-signal bandwidth
Measured at -3 dB point
100
fJ.S
kHz
Digital crosstalk
CLK - l-MHz square wave measured at OACA-OACO
-50
dB
Reference feedthrough
See Note 10
-60
dB
Channel-!o-channel isolation
See Note 11
-60
dB
Reference Input bandwidth
See Note 12
100
kHz
Output slew rate
RL= 101<0
CL = 100 pF,
RL= 10kn,
See Note 9
1
V/fJ.S
10
NOTES: 9. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured.value for a digital input code change
of 00 hex to FF hex or FF hex to 00 hex. For TLC5628C: VOO = 5 V, Vref - 2 V and range. x2. For TLC56281: VOO - 3 V,
Vref = 1.25 V and range x2.
.
10. Referencefeedthrough is measured at any OAC output with an Input code - 00 hex with a Vreflnput.l V de + 1 Vpp at 10 kHz.
11. Cilannel-to-channel isolation is measured by setting the input code of one OAC to FF hex and the code of all other DACs to 00 hex
wlthVrefinput-l Vde+ 1 Vpp atl0kHz.
.
12. Reference bandwidth Is the -3 dB bandwidth with an input at Vref _ 1.25 V de + 2 Vpp , with a digital input code of full-scale.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS. TEXAS 75265
TLC5628C, TLC56281
OCTAL 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS089A - NOVEMBER 1994 - REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
TLC5628
DACA I-_~~--,
DACB
10kO
•
DACH
Figure 3. Slewing Settling Time and Linearity Measurements
L~AC
3
>
I
j
~
I
VDD=5V
TA=25°C
I
Code 00 to FF Hexl
2 Range=x2
Vref= 2 V
I
1
c5I
/
.p
-
>
I
II
I:D
!
~
II'
'5
Go
.5
I
1/
'>
I
I =-/
o
o
2
4
6
8
10
LbAC
3
0
.I
iI
1
5
I
>
I
\
3, 2
!
.\.
'\
~
1
c5
I
I
1
12
14
16
18
o
2
4
5
0
>
I
II
I:D
!
~
:::I
Go
.5
I
0
t-Tlme-118
I
..
\
~
.!
VDD=5V
TA = 25°C
Code FF to 00 Hex
Range=x2
Vref =2V
6
>"
\
~
8
10
12
14
16
18
t-Tlme -118
Figure 4. Positive Rise and
Setting Time VDD 5 V
Figure 5. Negative Fall and
Setting Time VDD 5 V
=
=
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-35
TLC5628C, TLC56281
OCTAL 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS089A- NOVEMBER 1994 - REVISED JANUARY 1995
TYPICAL CHARATERISTICS
OUTPUT SOURCE CURRENT
SUPPLY CURRENT
vs
vs
OUTPUT VOLTAGE
-
8
CC
E
...........
7
I
~
6
:::I
0
~
5
:::I
0
1/1
4
'5
,e.
:::I
0
.......
TEMPERATURE
1.2
VOO =5V
TA = 25°C
Vref= 2 V
Range=x2
Input Code = 255
-
"" \
1.1
I
~
1.05
",.--
VOO=5V
Vref 2 V
Range=x2
Input Code = 255
.........
8
>-
\
3
- -......
1.15
8:
c7J
0.95
I
I
Gi"
e:::I
Q
E
2
!
0.9
0.85
.9
0
0
2
3
4
Vo - Output Voltage - V
0.8
-50
5
o
Figure 6
vs
FREQUENCY
FREQUENCY
10
~
-2
\
-6
I
c
ii
-8
~III
-10
a:
-12
CJ
11
ID
\
'0
~
\
a:
\
-
TA = 25°C
-18 t- Vref = 1.25 Vdc + 2 Vpp
Input Code = 255
I
-20
1
10
100
f - Frequency - kHz
-20
\
~
:;::I
III
11 ·-30
\
.:.. voo = 5V
i\
I
-14
-16
\
-10
c
I
CJ
./""..
0
\
-4
'0
RELATIVE GAIN
vs
0
I
CJ
\
\
\
-60
1000
\
VOO=5V
-40 _ TA=25°C
Vref = 2 Vdc + 0.5 Vpp
Input Code = 255
-50
1
10
100
f - Frequency - kHz
FigureS
Figure 9
~1EXAS
·3-36
100
Figure 7
RELATIVE GAIN
III
50
t - Temperatura - °C
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
\A
V
1000
10000
TLC5828C, TLC58281
OCTAL 8-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS089A- NOVEMBER 1994 - REVISED JANUARY 1995
APPLICATION INFORMATION
TLC5828
Yo
DACA
DACB
•
•
•
DACH
NOTE A: Resistor R
R
":"
~
10 kn
Figure 10. Output Buffering Schemes
~1ExAs
INSTRUMENTS
)
POST OFFICE BOX 855303 • DAllAS. TEXAS 76266
~7
3-38
TLC7226C, TLC72261
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS060 -JANUARY 1995
•
•
•
•
•
•
•
OW OR N PACKAGE
(TOP VIEW)
Four 8-Blt D/A Converters
Microprocessor Compatible
TTUCMOS Compatible
No User Trim Required
Single Supply Operation Possible
Simultaneous Update Facility
CMOS Technology
OUTB ~ 1 U 20
OUTA [ 2
19
Vss ~ 3
REF~ 4
18
17
AGND 5
16
DGND 6
15
DB? 7
14
DBS 8
13
DBS 9
12
_ _ _ _J
DB4 [10
11
applications
• Process Control
• Automatic Test Equipment
• Automatic Calibration of Large System
Parameters e.g., Gain/Offset
OUTe
OUTD
VDD
AD
A1
WR
DBD
DB1
DB2
DB3
description
The TLC7226C and TLC72261 consist of four, 8-bit, voltage-output, digital-to-analog converters with output
buffer amplifiers and interface logiC on a single monolithic chip. No external trims are required to achieve full
specified performance for the part.
Separate on-chip latches are provided for each of the four DIA converters. Data is transferred into one of these
data latches through a common, 8-bit, TTLICMOS-compatible (5 V) input port. Control inputs AO and A1
determine which D/A converter is loaded when WR goes low. The control logic is speed compatible with most
8-bit microprocessors. Since all four D/A converters are fabricated on the same chip at the same time, precise
matching and tracking between them is inherent.
~
W
:;
w
a:
Q.
t;
Each D/A converter includes an output buffer amplifier capable of sourcing up to 5 mA of output current.
;:)
The TLC7226 performance is specified for input reference voltages from 2 V to 12.5 V with dual supplies. The
voltage mode configuration of the DIA converters allow the TLC7226 to be operated from a single power supply
rail at a reference of 10 V.
o
The TLC7226 is fabricated in a LinBiCMOSTM process that has been specifically developed to allow high-speed
digital logic circuits and precision analog circuits to be integrated on the same Chip. The TLC7226 has a common
8-bit data bus with individual D/A converter latches. This provides a versatile control architecture for simple
interface to microprocessors. All latch-enable signals are level triggered.
Combining four D/A converters, four operational amplifiers, and interface logic into either a O.3-inch widEl, 2o-pin
DIP or a small 20-pin small-outline IC (SOIC) allows a dramatic reduction in board space requirements and
offers increased reliability in systems using multiple converters. The pinout is aimed at optimizing board layout
with all of the analog inputs and outputs at one end of the package and all of the digital inputs at the other.
The TLC7226C is characterized for operation from O°C to ?O°C. The TLC72261 is characterized for operation
from -25°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(DW)
PLASTICOIP
IN)
O·C to 70·C
TLC7226CDW
TLC7226CN
-25·C to 85·C
TLC72261DW
TLG7;22SIN
linBiCMOS is a trademark of Texas Instruments Incorporated.
==
PRODUC't
PREVIEW
..-..
produCIBln
Iho"""",.r
p!-.
01 _1Ion
doveIOpmont
C_
_
and OIlIer
..... d.langoals. T_I _ _ lhorightlO
..lMN produC1B wIIhouI noll...
or _
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-39
C
a:
Q.
TLC7226C, TLC72261
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS060 - JANUARY 1995
functional block diagram
REF~4________________~__~
>-*--=2,- OUTA
>-*-....:.1_ OUTB
DBO-DB7 7-14
8
>-......!!20~
OUTC
>-*_....:.1.::,..9 OUTD
"U
_
15
WR 17
:D
o
Controll-+--....J
t"...-_-___....J--,
J ....
C
5lc:
r---""
AO
IC
A1 16 LLO_9_
schematic of outputs
EQUIVALENT ANALOG OUTPUT
"U
:D
VDD - - - - - . - - - - - - - - ,
m
m
--~
<
:e
Output
Vss -----+--------'
~ThxAs
3-40
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
TLC7226C, TLC72261
QUADRUPLE 8-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS060-JANUARY 1995
Tenninal Functions
TERMINAL
NAME
NO.t
AGND
5
AO,A1
16,17
DGND
6
DBO-DB7
OUTA
I/O
DESCRIPTION
Analog ground
I
DAC select inputs
Digital ground
7-14
I
2
1
0
0
0
0
Digital DAC data inputs
DACAoutput
DACBoutput
DACCoutput
20
DACD output
OUTD
19
REF
4
I
Voltage reference input
18
Positive supply voltage
VDD
3
Negative supply voltage
VSS
I
WR
15
Write input selects DAC transparency or latch mode. The selected input latch is transparent when WR is low.
t Terminal numbers shown are for the OW and N packages.
OUTB
OUTC
detailed description
AGND bias for direct bipolar output operation
The TLC7226 can be used in bipolar operation without adding more external operational amplifiers as shown
in Figure 1 by biasing AGND to Vss. This configuration provides an excellent method for providing a direct
bipolar output with no additional components. The transfer values are shown in Table 1.
.
;=
W
:;
w
a:
D.
b
::;)
c
o
a:
Output range
(5Vto-5V)
D.
t Digital inputs omitted for clarity.
Figure 1. AGND Bias for Direct Bipolar Operation
-!111ExAs
INSTRUMENTS·
POST OFFICE BOX 656303 • DAUAS. TEXAS 75265
3-41
TLC7226C, TLC72261
QUADRUPLE 8-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS06O-JANUARY 1996
AGND bias for direct bipolar output operation (contln.ued)
Table 1. Bipolar (Offset Binary) Code
DAC LATCH CONTENTS
MSB
LSB
ANALOG OUTPUT
C27)
1111
1111
+ Vref 128
1000
0001
+ Vref
1000
0000
0111
1111
- Vref
0000
0001
- Vref (127)
128
0000
0000
-Vref (128)
128 -_
(1~8)
OV
(1~8)
- Vref
AGND bias for positive output offset
The TLC7226 AGND terminal can be biased above or below the system ground terminal, DGND, to provide an
offset zero analog output voltage level. Figure 2 shows a circuit configuration to achieve this for channel. A of
the TLC7226. The output voltage, Vo, at OUTA can be expressed as:
'"'0
::D
o
C
Vo
c:
o-I
= V BIAS + DA
(VI)
Where DA is a fractional representation of the digital input word (0 s 0 s 255/256).
Increasing AGND above system GND reduces the output range. VDD - Vref must be at least 4 V to ensure
specified operation. Because the AGND terminal is common to all four DACs, this method biases up the output
voltages of all the DACs in the TLC7226. Supply voltages VDO and Vss for the TLC7226 should be referenced
to DGND.
'"'0
::D
m
<
-
m
IY~~D
~
OUTA
-~~-{6
t Digital inputs omitted for clarity.
Figure 2. AGND Bias Circuit
~1ExAs
3-42
INSTRUMENTS
POST OFFICE BOX 655303 • DAlI..AS. TEXAS 75266
TLC7226C, TLC72261
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS060 - JANUARY 1995
bipolar output operation using external amplifier
Each of the DACs of the TLC7226 can also be individually configured to provide bipolar output operation, using
an external amplifier and two resistors per channel. Figure 3 shows a circuit used to implement offset binary
coding (bipolar operation) with DAC A of the TLC7226. In this case:
Vo = 1 +
With R1
~~
x (DA x Vref) -
~~
x (V ref)
= R2
V0
= (2D A - 1) x Vref
Where DAis a fractional representation of the digital word in latch A.
Mismatch between R1 and R2 causes gain and offset errors. Therefore, these resistors must match and track
over temperature. The TLC7226 can be operated with a single supply or from positive and negative supplies.
REF----~~----------__,
R2t
4
r--
1
1
I..--...&...-...,
1
1L _ _ _ _ _ _ _ _ _ _ .J1
tRl
W
==
:;
Vo
w
a:
=R2 =10 kO±O.l%
Q.
Figure 3. Bipolar Output Circuit
tO
staircase window comparator
In many test systems, it is important to be able to determine whether some parameter lies within defined limits.
The staircase window comparator shown in Figure 4 is a circuit that can be used, to measure the VOH and VOL
thresholds of a TIL device under test. Upper and lower limits on both VOH and VOL can be programmed using
the TLC7226. Each adjacent pair of comparators forms a window of programmable size (see Figure 5). When
the test voltage (Vtest) lines horizonal within a window, then the output for that window is higher. With a reference
of 2.56 V applied to the REF Input, the minimum window size is 10 mY.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-43
::J
C
o
a:
Q.
TLC7228C, TLC72261
.
QUADRUPLE 8-81T DIGITAL·TO-ANALOG CONVERTERS
SLAS060-JANUARY1995
staircase window comparator (continued)
SV
Vteat - - - - - - . . . . . . . , . . . ,
FromDUT
10kQ
4
Window 1
REF
BV
10kO
OUTA
2
VOH
Window 2
TLC7226
OUTB
1
VOH
"tJ
Window 3
::D
o
C
c:
~
CUTe
20 VOL
F--";;;~,*",,--I
Window 4
"tJ
::D
m
m
-=e
<
WindowS
Figure 4. Logic Level Measurement
~~ENTS
?OST OFFICE BOX 666303 • DAlLAS•.TEXAB 75266
TLC7226C, TLC72261
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS060 - JANUARY 1995
staircase window comparator (continued)
REF----------------------~--
Window 1
----------------------+--Window 2
OUTe ----------------------+--OUTA
Window 3
OUTC
----------------------+--Window 4
OUTO ----------------------....- Window 5
AGNO----------------------~--
Figure 5. Window Structure
The circuit can easily be adapted to allow for overlapping of windows as shown in Figure 6. When the three outputs
from this circuit are decoded, five different nonoverlapping programmable windows can again be defined (see
Figure 7).
5V
Vtest
From OUT
->WW
10 k.Q
4
a:
Window 1
REF
OUTA
;=
D..
I-
2
5V
0
10 k.Q
~
OUTe
C
0
Window 2
TLC7226
OUTC
OUTO
20
19
a:
D..
5V
10 k.Q
Window 3
AGNO
5
-=Figure 6. Overlapping Windows
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-45
TLC7226C, TLC72261
QUADRUPLE 8-BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS060 - JANUARY 1995
staircase window comparator (continued)
REF
WI ndow1
OUTB
OUTA
Window 2
OUTO
II-
OUTC
,
AGNO
Window 3
Figure 7. Window structure
output buffer amplifier
The unity-gain output amplifier is capable of sourcing 5 mA into a 2-k.Q load and can drive a 3300-pF capacitor.
The output can be shorted to AGND indefinitely or can be shorted to any voltage between Vss and Voo
consistent with the maximum device power dissipation;
...
v
o
:x:J
multiplying ,DAC
The TLC7226 can be used as a multiplying DAC if the reference signal is maintained between 2' V and
Voo -4 V. When this configuration is used, Voo should be 14.25 V to 15.75 V. A low output impedance buffer
should be used so thf!,t the input signal is not loaded by the resistor ladder. Figure 8 shows the general schematic. .
C
c:
~
15V
'1J
:x:J
1/4TLC7226
m
m
Vref
4
<
-
:e
OAC
AC Reference --'
Input Signal --,
5
Figure 8. AC Signal Input Scheme
~TEXAS
3-46
INSTRUMENTS
POST OFFICE BOX 856303 • DALlAS. TEXAS 75265
~H--Vo
TLC7226C, TLC72261
QUADRUPLE 8-BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS060-JANUARY 1995
Interface logic Information
Address lines AD and A1 select which D/A converter accepts data from the input port. The foliowinJl.!lnction
table shows the selection table for the four DACs. Figure 9 shows the input control logic. When the WR signal
is low, the input latches of the selected DAC are transparent and the output responds to activity on the data bus.
The data is latched into the addressed DAC latch on the rising edge of WR. While WR is high, the analog outputs
remain at the value corresponding to the data held in their respective latches.
FUNCTION TABLE
CONTROL INPUTS
WR
A1
A2
H
X
X
L
L
L
L
L
H
H
H
H
i
L
i
L
i
L
i
L - low,
H _ high,
OPERATION
No operation
Device not selected
DAC A transparent
DAC A latched
DAC B transparent
DAC B latched
DAC C transparent
DAC C latched
DAC D transparent
DAC D latched
L
L
H
H
L
L
H
H
X =irrelevant
AO
~
w
5>
w
a:
0 - - - To Latch A
0..
A1
16
~~:t:+=+=llo---
~
To Latch B
o
::J
C
o
0 - - - To Latch C
a:
0..
L.::==:t=rlo--- To Latch D
Figure 9. Input Control Logic
-!I1TEXAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-47
TLC7226C, TLC72261
QUADRUPLE 8·BIT DIGITAL·TO·ANALOGCONVERTERS
SLAS060 - JANUARY 1995
unipolar output operation
The unipolar output operation is the basic mode of operation for each channel of the TLC7226, with the output
voltages having the same positive polarity as Vref~ The TLC7226 can be operated with a single supply
(Vss = AGND) or with positive/negative supplies. The voltage at Vref must never be negative with respect to
AGND to prevent parasitic transistor turn-on. Connections for the unipolar output operation are shown in
Figure 10. Transfer values are shown in Table 2.
2 OUTA
>-i......_.::..
REF _4'---4......-.
>-4~_-,-1 OUTB
>-.--_.::;20;;.. OUTC
"tJ
:rJ
>-.--_.!.:19~ OUTO
o
C
c:
Figure 10. Unipolar Output Circuit
~
Table 2. Unipolar Code
"tJ
:rJ
OAC LATCH CONTENTS
MSB
LSB
m
m
ANALOG OUTPUT
<
1111
1111
+ Vref (255)
256
:e
1000
0001
+ Vref 256
1000
0000
0111
1111
C29)
Vref
+ Vref C28)
256 =+2
+ Vref C27)
256
0000
0001
+ Vref
0000
0000
-
(2~6)
OV
~1ExAs
3-48
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
TLC7226C, TLC72281
QUADRUPLE 8-BIT DIGITAL·TO-ANALOG CONVERTERS
SLAS06Q-JANUARY 1995
absolute maximum ratings over operating free.alr temperature range (unle.. otherwise noted)t
Supply voltage range. Voo: to AGNO or OGNO •........•........•..........•....•.... -0.3 V to 17 V
to VSS* •.....••.••••..•...•...................•.•..•.... -0.3 V to 24 V
Supply voltage range. Vss: to AGNO or OGNO •.•..............•.....••.•.•..•.•••. -17 V to + 0.3 V
Voltage range between AGNO and OGNO • • • • • • • • . . • • • . • . . . . . . . . . . . . . . . . . . . . • . . . • . .. -17 V to 17 V
Input voltage range. VI (to DGNO) ..............•...•......••.•......•..•...•. -0.3 V to Voo + 0.3 V
Reference voltage range: Vref (to AGNO) •••••.••................................. " -0.3 V to Voo
Vref (to Vss) ••••.•..•....•...•..••.........•..••....•.•.• -0.3 V to 20 V
Output voltage range. Vo (to AGNO) (see Note 1) •..•.•...••.••••.••.••.•••••••••••••••• Vss to Voo
Continuous total power dissipation at (or below) TA - 25°C (see Note 2) ...................... 500 mW
Operating free-air temperature range. TA: e suffix ....•........•..•.........•.........••. ooe to 70°C
I suffix .................................•..•• -25°C to 85°C
Storage temperature range. Tstg ..............•.............. r.................... -65°C to 150°C
Lead temperature 1.6 mm (111 Er inch) from case for 10 seconds: OW or N packages .............. 260°C
t SIr8III8I beyond those listed under"ablolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
funcIionaI operation 01 the device at Iheee or any other conditions beyond those indicated under "recommended operating conditions" is not
impled. Exposure to absoJute.maxlmum-rated condIIions for extended periods may affect device reliability.
The Vss tet'IrinIIIls connected to the substrate and must be tied to the most negativa supply voltage applied to the device.
NOTES; 1. Output YOIIageI may be shorted to AGNO provided that the power claslpatlon of the package Is not exceeded. Typically short circuit
CIAT8I'II to AGNO Is 80 rnA.
2. For operation above TA - 76"C derate linearly at the rate of 2.0 rnCI"C.
*
recommended operating conditions
MIN
MAX
UNIT
Supply voltage, VOO
4.5
16.5
V
SUpply voltage. Vss
-0.6
-5.5
V
; VOO-4.76V
High-level Input voltage, VIH
VOO-15.75V
Low-IeveIlnput voltage, VIL
2
0.8
VOO-4.75V
ReleIW1C8 voltage, Vref
0
Load resistance, RL
2
Setup time. address valid before \1m, taulAWI
0
Setup time, data valid before ~, tau(Ow)
Hold time, address veld before WI!i,itt(AW)
Hold time, data valid before \1m, itt(Ow)
PuIae duration, Ym low, tw
OperatIng frae.alr temperatura, TA
V
2
VOO - 4.75 V to 5.26 V
70
VOO - 4.75 V to 5.25 V
180
VOO - 4.76 V to 5.26 V
10
VOO - 4.75 V to 5.25 V
20
VOO - 4.75 V to 5.25 V
0
VOO - 4.75 V to 5.25 V
20
VOO-4
V
V
IcC
ns
ns
ns
ns
VOO - 4.75 V to 5.26 V
50
VOO - 4.75 V to 5.25 V
180
Csuffix
I suffix
0
70
'C
-25
85
"C
~1ExAs
INSlRUMENTS
POSTOFFIOE BOX _ . DALLAS. TEXAS 7 _
ns
;:
w
s:w
a:
a.
b
::l
C
o
a:
a.
TLC7226C, TLC72261
.
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS060 -JANUARY 1995
electrical characteristics over recommended operating free-air temperature range
dual power supply over recommended supply and reference voltage ranges, AGND
otherwise noted)
PARAMETER
TEST CONDITIONS
II
Input current, digital
VI = 0 VorVDD
IDD
Supply current
VI = VIL orVIH,
No load
ISS
Supply current
VI = VIL or VIH,
No load
rilrel)
Reference input resistance
MIN
2
Power supply sensitivity
TYP
All O's loaded
REF input
MAX
IlA
6
12
rnA
4
10
rnA
0.01
%1%
300
pF
kQ
4
65
All 1's loaded
Digital inputs
single power supply, VOO
8
= 14.25 V to 15.75 V, VSS = AGND = DGND = 0 V, Vref = 10 V
PARAMETER
"lJ
o
c
c:
o-t
TEST CONDITIONS
II
Input current, digital
VI =OVorVDD
IDD
Supply current
VI = VIL or VIH,
Power supply sensitivity
l1VDD -±5%
All O's loaded
~
REF input
Input capacitance
Ci
single or dual power supplies, Voo
Vref 1.25 V
=
~
-
IDD
Supply current
VI = VIL or VIH,
11
Input resistance
0.01
0/01%
300
pF
MIN
No load
MAX
REF input
l1VDD-±5%
All O's loaded
All 1's loaded
Digital inputs
~TEXAS . '
INSTRUMENTS
POST OFFICE BOX 655903 • DALlAS. TEXAS 75265
UNIT
±1
!IA
12
rnA
0.01
%1%
300
pF
2
Power supply sensitivity
3-50
rnA
65
TEST CONDITIONS
VI =OVorVDD
Input capacitance
!IA
13
= 4.75 V to 5.25 V, VSS = AGND = DGND = 0 V or Vss = -5 V,
PARAMETER
Ci
UNIT
±1
8
Input current, digital
:e
MAX
No load
All 1's loaded
II
m
<
m
MIN
Digital inputs
"lJ
UNIT
±1
l1VDD= ±5%
Input capacitance
Ci
=DGND =0 V (unless
kQ
65
8
TLC7226C, TLC72261
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS060-JANUARY 1995
operating characteristics over recommended operating free-air temperature range
dual power supply over recommended supply and reference voltage ranges, AGND = DGND = 0 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.5
Slew rate
I Positive full scale
Settling time to 112 LSB
I Negative full scale
VOIIS
5
Vref= 10 V
7
Resolution
VDD = 15 V ±5%.
Vref-l0V
I DifferentiaVintegral
Unearity error
±2
LSB
±1
LSB
±1.5
Full-scale error
Temperature coefficient of gain
I Full scale
±20
VDD = 14 V to 16.5 V. VrefR 10V
I Zero-code error
±30
Digital crosstalk glitch impulse area
50
Vref- OV
LSB
ppml"C
±50
Zero-code error
lIS
Bits
8
Total unadjusted error
UNIT
JJ.VI"C
mV
nVos
single power supply, VOO = 14.25 V to 15.75 V, VSS = AGND = DGND = 0 V, Vref = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Siewrate
Settling time to 112 LSB
MIN
TYP
5
Negative full scale
20
Resolution
Full-scale error
Unearity error
VDD=14Vto16.5V. Vref=10V
Zero-code error
Q.
LSB
I-
ppml"C
±50
JJ.V/oC
LSB
nVos
50
PARAMETER
MIN
MAX
UNIT
±1
LSB
Full-scale error
±4
LSB
Zero-code error
±30
mV
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
a:
±1.5
±1
I Differential
s:w
LSB
single or dual power supplies, VOO = 4.75 V to 5.25 V, VSS = AGND = DGND or Vss = -5 V, Vref = 1.25 V (unless
otherwise noted)
Unearity error
W
==
±2
±20
Differential
Digital crosstalk glitch impulse area
lIS
Bits
8
Full scale
UNIT
VOIIS
Positive full scale
Total unadjusted error
Temperature coefficient of gain
MAX
2
3-51
o
:J
C
o
a:
Q.
TLC7226C, TLC72261
QUADRUPLE 8-81T DIGITAL·TO·ANALOG CONVERTERS
SLAS060 - JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
\.
~~_--I~II-I
~============X
taulDw)
.~(<=======
--.......I0~---- :---.{< .
Oata
Address
tau(AW)
th(OW)
..
-H~tw ___If-*-
WR ----~\.
::0
VOO
OV
th(AW)
, .....-_-_-_-_- ::0
NOTES: A. tr = tf = 20 ns over VOO range.
B. The timing measurement reference level is equal to VIH + VILdivlded by 2.
C. The selected input latch is transparent while WR is low. Invalid data during this time can cause erroneous outputs.
Figure 11. Write-Cycle Voltage Waveforms
"Q
:XJ
o
TYPICAL CHARACTERISTICS
C
c:
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
(')
-I
200
m
-<
m
150
~
.100
j--
Source Current
Short-Circuit
Limiting
I
50
:E
1
0
TA = 25°C
VOO= 15V
J
600
l~
L~~=5V
<
01(
::I.
500 -
~
400
I
o~
I
VLJ5V
IT
VSS=O
0
-0.1
I
.9
700
r~
VOO=15V _
"Q
:XJ
OUTPUT CURRENT (SINK)
vs
OUTPUT VOLTAGE
300
I
TA = 25°C
VSS=-5V
OlgltallN = 0 V
-0.2
.9
100
-0.3
}
-0.4
200
I
-2
Sinking
Current Source
-1
o
Vo - Output Voltage - V
2
o
o
3
4
5
8
7
Vo - Output Voltage - V
Figure 12
Figure 13
~iExAs
3-52
2
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
8
8
10
TLC7524C, TLC7524E, TLC75241
8-81T MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061 A - SEPTEMBER 1986 - REVISED MARCH
• Easily Interfaced to Microprocessors
• On-Chip Data Latches
• Monotonic Over the Entire AID Conversion
Range
D OR N PACKAGE
crOP VIEW)
OUT1
OUT2
GND
DB?
DB6
DB5
DB4
DB3
• Segmented High-Order Bits Ensure
Low-Glitch Output
• Interchangeable With Analog Devices
AD7524. PMI PM-7524. and Micro Power
Systems MP7524
• Fast Control Signaling for Digital
Signal-Processor Applications Including
Interface With TMS320
• CMOS Technology
RFB
REF
Voo
WR
CS
4
5
DBD
DB1
DB2
6
7
8
9
FNPACKAGE
crOP VIEW)
KEY PERFORMANCE SPECIFICATIONS
Resolution
Linearity error
Power dissipation at VOO - 5 V
Setting time
Propagation delay time
~ ~
1Du..
=>=>o.!!-w
8 Bits
112 LSB Max
5mWMax
100 ns Max
80nsMax
OOZ""
a:
GND
DB?
4
5
3 2 1 20 19
18
17
NC
6
16
NC
DB6
DB5
7
15
14
CS
description
The TLC7524C, TLC7524E, and TLC75241 are
CMOS, 8-bit, digital-to-analog converters (OACs)
designed for easy interface to most popular
microprocessors.
8
9 10 11 12 13
Voo
WR
DBD
NC-No internal connection
The devices are 8-bit, multiplying OACs with input latches and load cycles similar to the write cycles of a random
access memory. Segmenting the high-order bits minimizes glitches during changes in the most significant bits,
which produce the highest glitch impulse. The devices provide accuracy to 1/2 LSB without the need for thin-film
resistors or laser trimming, while dissipating less than 5 mW typically.
Featuring operation from a 5-V to 15-V single supply, these devices interface easily to most microprocessor
buses 'or output ports. The 2- or 4-quadrant multiplying makes these devices an ideal choice for many
micr9processor-controlled gain-setting and signal-control applications.
The TLC7524C is characterized for operation from O°C to 70°C. The TLC75241 is characterized for operation
from -25°C to 85°C. The TLC7524E is characterized for operation from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA
(D)
PLASTIC CHIP
CARRIER
(FN)
SMALL OUTUNE
PLASTIC DIP
PLASTIC DIP
(N)
O·Cto 70·C
TLC7524CD
TLC7524CFN
TLC7524CN
-25·C to 85·C
TLC75241D
TLC75241FN
TLC75241N
-4O·C to 85·C
TLC7524ED
TLC7524EFN
TLC7524EN
~1ExAs
Copyright Ill> 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 65S303 • DALlAS. TEXAS 75265
3-53
TLC7524C,TLC7524E, TLC75241
.
8-81T MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061A- SEPTEMBER 1986 - REVISED MARCH 1996
functional, block diagram
REF
R
15
R
2R
2R
R
2R
r, I, r 1,1,
I,
3
2R
16
lye
,
,
,
12
13
I
2R
1
2
I
Data Latches
R
I
3
OUT1
OUT2
GND
4
5
6
11
DB7
DB6
DB5
DBO
(MSB)
(LSB)
\~--------~v~-------JI
Datalnputa
Terminal numbers shown are for the D or N package.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Voo . . . . . . . . . . . . . . . . . . . • .. . . . . . .. . .. . . . .. . .. .. . . . ... .. .. . -0.3 V to 16.5 V
Digital input voltage range, V, ................................. ; . . . . . . . . . . . . -0.3 V to Voo + 0.3 V
Reference voltage, Vref ..... , ...............................•......................... : ., ±25 V
Peak digital input current, I, ...........•................................. , ................ , 10 JJA
Operating free-air temperature range, TA: TLC7524C ................................. O°C to 70°C
TLC75241 ... . . . . . . . . . . . . . . .. . . . . . . . . . . . .. -25°C to 85°C
TLC7524E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 10 seconds, Tc: FN package ......................................... 260°C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds: D or N package ............... 260°C
~'TEXAs
'
INSTRUMENTS
POST OFFICE BOX 656303 • OALLAS. TEXAS.75266
TLC7524C,TLC7524E, TLC75241
8-81T MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061A- SEPTEMBER 1986 - REVISED MARCH 1995
recommended operating conditions
VOD=15V
VOO=5V
MIN
NOM
MAX
MIN
5
5.25
14.5
4.75
Supply voltage, VDD
High-level input voltage, VIH
MAX
15
15.5
UNIT
V
V
±10
±10
Reference voltage, Vref
NOM
2.4
V
1.5
0.8
Low-level input voltage, VIL
V
40
40
ns
0
0
ns
Data bus input setup time tsu(D)
25
25
ns
Data bus input hold time tl1(D1
10
10
ns
CS setup time, tsu(CS)
CS hold time th(CS)
40
Pulse duration, WR low, IwCWR)
TLC7524C
Operating free-air temperature, TA
40
0
ns
70
0
70
TLC75241
-25
85
-25
85
TLC7524E
-40
85
-40
85
·C
electrical characteristics over recommended operating free-air temperature range, Vref = ±10 V,
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IIH
High-level input current
VI-VDD
IlL
Low-level input current
VI-O
Ilkg
Output leakage
current
OUTl
DBO-DB7 at 0 V,
Vref-±10V
WR,~atOV,
OUT2
DBO-DB7 at VDD,
Vref-±10V
WR,CSatOV,
Quiescent
DBO-DB7 at VIHmin or VILmax
Standby
DBO-DB7 at 0 VorVDD
100
Supply current
kSVS
Supply voltage sensitivity,
dgainldVDD
dVDD",±10%
Ci
Input capacitance,
DBO-DB7, WR, CS
VI-O
Co
Output
capacitance
MAX
MIN
0.01
DBO-DB7 at 0 V,
WR,CSalOV
DBO-DB7 at VDD,
WR,~atOV
Reference input impedance
(REFtoGND)
TYP
MAX
10
10
-10
-10
±400
±200
±400
±200
UNIT
tJA
tJA
1
2
rnA
500
500
JJA
0.04
%FSR!%
0.16
0.005
5
OUTl
OUT2
TYP
nA
OUTl
OUT2
VOO = 15V
VOO=5V
MIN
5
5
30
30
120
120
120
120
30
30
20
5
20
pF
pF
kO
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
3-05
TLC7524C, TLC7524E, TLC75241
8-BITMULTIPLYING DIGITAL·TO·ANALOG CONVERTERS
SLAS061A- SEPTEMBER 1986 - REVISED MARCH 1995
o~ratlng characteristics over recommended operating free-air temperatu're range, Vref
OUT1 anit OUT2 at GND (unless otherwise noteit)
PARAMETER
TEST CONDITIONS
=±10 V,
VDO=5V
MIN
TYP MAX
VOD=15V
MIN TYfIt MAX
UNIT
Linearity error
Gain error'
±O.S
±O.S
LSB
See Note 1
±2.S
±2.S
LSB
Settling time (to 112 LSB)
See Note 2
100
100
ns
Propagation delay from digital input
to 90% Of final analog output current
See Note 2
80
80
ns
Feedthrough at oun or OUT2
Vref • ±10 V (l00-kHz slnewave)
WR and cg at 0 V, OBG-OB7 at 0 V
O.S
O.S
%FSR
Temperature coefficient of gain
TA - 2s00 to MAX
±0.004
±0.001
NOTES: 1. Gain error IS measured USing the internal feedback resistor. Nominal full scale range (FSR) - Vref -1 LSB.
2. OUTl load = 100 C, Oext = 13 pF, WR at 0 V, OS at 0 V, OBo-DB7 at 0 V to VOO or VOO to 0 V.
operating sequence
tsu(CS) ----:--~~144---*tl- fh(CS)
14
FJ;--..-..._~
CS---""" I
~-----------~I--/
.i+--Iw(WR)
WR------------~~
~
Ir-------------
---------tf
~I
----.I
ll'-"
1
tsu(O)
O~B7--------------------~(
3-56
~
~I
'TEXAS
NSTRUMENTS
POST OFFICE SOX 666303 • DALLAS. TEXAS 75266
"'(0)
~~-----------
%FSRI"O
TLC7524C, TLC7524E, TLC75241
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061A-SEPTEMBER 1966-REVISED MARCH 1995
APPLICATION INFORMATION
voltage-mode operation
It is possible to operate the current-multiplying OAC in these devices in a voltage mode. In the voltage mode,
a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the
reference voltage terminal. Figure 1 is an example of a current-multiplying OAC, which is operated in voltage
mode.
R
R
R
REF (Analog Output Voltage) ~ I--"-'VV-..---,
}2R
}
2R
2R
2R
Y
'---+----+---+-4- OUT1 (FIxed Input Voltage)
'------4---___- - - - 4....... . . - OUT2
Figure 1. Voltage Mode Operation
The relationship between the fixed-input voltage and the analog-output voltage is given by the following
equation:
Vo = VI (0/256)
where
Vo = analog output voltage
VI = fixed input voltage
o = digital input code converted to decimal
In voltage-mode operation, these devices meet the following specification:
PARAMETER
Linearity error at REF
TEST CONDITIONS
VDD =5 V,
OUTl = 2.5 V,
OUT2 at GND,
TA =25°C
~ThxAs
INSTRUMENTS
POST OFFICE BOX 650303 • DAUAS, TEXAS 75265
3-57
TLC7524C, TLC7524E, TLC75241
8·BIT MULTIPLYING DIGITAL·TO·ANALOG CONVERTERS
SLAS061 A- SEPTEMBER 1986 -REVISED MARCH 1995
.PRINCIPLES OF OPERATION
The TLC7524C, TLC7524E, and TLC7524 I are B-bit multiplying DACs consisting of an inverted R-2R ladder,
analog switches, and data input latches. Binary-weighted currents are switched between the OUT1 and OUT2
bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-order
bits are decoded. These decoded bits, through a modification in the R-2R ladder, control three equally-weighted
current sources. Most applications only require the addition of an external operational amplifier and a voltage
~~~~.
.
The equivalent circuit for all digital inputs low is seen in Figure 2. With all digital inputs low, the entire referencE!
current, Iref, is switched to OUT2. The current source 11256 represents the constant current flowing through the
termination resistor of the R-2R ladder, while the current source Ilkg represents leakage currents to the
substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all
digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2 and the on-state switch
capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown
in Figure 2. Analysis of the circuit for all digital inputs high is similar to Figure 2; however, in this case, Iref would
be switched to OUT1.
The DAC on these devices interfaces to a microprocessor through the data bus and the CS and WR control
signals. When CS and WR are both low, analog output on these devices responds to the data activity on the
DBD-DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects the
analog output. When either the CS signal or WR Signal goes high, the data on the DBD-DB7 inputs are latched
until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless of the state
of the WR signal.
These devices are capable of performing 2-quadrant or full4-quadrant multiplication. Circuit configurations for
2-quadrant or 4-quadrant multiplication are shown in Figures 3 and 4. Tables 1 and 2 summarize input coding
for unipolar and bipolar operation respectively.
R
, - - - - - - - . -......- - - - - - , . - OUT1
III(g
lref
REF
i
--+
-----"v'V\.1I-256-~.-~--I-lk9-~
.......- i - - - - f - e - - 1 2 0 - P - F - - - - OUT2
Figure 2. TLC7524 Equivalent Circuit With All Digital Inputs Low
~TEXAS
INSTRUMENTS
POST OFFICI' BOX fl55303 • DALLAS. TEXAS 75265
TLC7524C, TLC7524E, TLC75241
8·BIT MULTIPLYING· DIGITAL·TO·ANALOG CONVERTERS
SLAS061A- SEPTEMBER 1986 - REVISED MARCH 1995
PRINCIPLES OF OPERATION
Vref
VDD
RA =2 k.Q
(see Note A)
RB
DBO-DB7 '-----V
>--....--Output
CS - - - - I
WR - - - - t
Figure 3. Unipolar Operation (2-Quadrant Multiplication)
Vref
VDD
20 k.Q
RA =2 k.Q
(see Note A)
RB
20 k.Q
>-__DBO-DB7
Output
~-./
CS - - - - t
WR - - - i
GND
Figure 4. Bipolar Operation (4-Quadrant Operation)
NOTES: A. RA and RS used only if gain adjustment is required.
S. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.
Table 1. Unipolar Binary Code
DIGITAL INPUT
(see Note 3)
MSB
ANALOG OUTPUT
LSB
11111111
10000001
10000000
01111111
00000001
00000000
Table 2. Bipolar (Offset Binary) Code
DIGITAL INPUT
(see Note 4)
MSB
- Vref (255/256)
-Vref (129/256)
-Vref (128/256) = -Vre tf2
-Vref (127/256)
-Vref (11256)
0
ANALOG OUTPUT
LSB
11111111
10000001
10000000
01111111
00000001
00000000
Vref (1271128)
Vref (1/128)
0
- Vref (11128)
-Vref (127/128)
-Vref
NOTES: 3. LSS = 11256 (Vref)
4. LSS =1/128 {Vretl
-!I1TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS, TEXAS 75265
3-09
TLC7524C, TLC7524E,TLC75241
8-BITMULTIPLYING DIGITAL·TO·ANALOGCONVERTERS
SLAS061A- SEPTEMBER 1986 - REVISED MARCH 1995
PRINCIPLES OF OPERATION
microprocessor Interfa,ces
DO-D7
Data Bus
~J
Z-atlA
WR
-
DBO-DB7
~
WR
TLC7524
cs
1'1'
Ao-A15
OUT2
I
Decode
Logic
IORQ
OUT1
Address Bus
Figure 5. TLC7524 - Z-80A Interface
Data Bus
DO-D7
6800
cjl2
tJ
DBO-DB7
J~
J
ViR
TLC7524
OUT2
CS
VMA
r
Decode
Logic
r
1'1
Ao-A15
Address Bus
Figure 6. TLC7524 - 6800 Interface
~TEXAS
3-60
OUT1
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I
TLC7524C, TLC7524E, TLC75241
8·BIT MULTIPLYING DIGITAL·TO-ANALOG CONVERTERS
SLAS061A- SEPTEMBER 1986 - REVISED MARCH 1995
microprocessor Interfaces (continued)
A8-A15
AddresaBus
8051
Decode
~
r-v"
logic
8-Blt
Latch
I
)
CS
I I
ALE
WR
ADO-AD7
-
WR
TLC7524
DBO-DB7
AdresslDets Bus
OUT1
OUT2
'I
Figure 7. TLC7524 - 8051 Interface
l
~1EXAS
INSTRUMENTS
POST OFFICE BOX 856303 •
D~.
TEXAS 75266
3-61
3-62
TLC7528C, TLC7528E, TLC75281
DUAL 8-81T MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
1995
• Easily Interfaced to Microprocessors
OW OR N PACKAGE
(TOP VIEW)
• On-Chip Data Latches
• Monotonic Over the Entire AID Conversion
Range
• Interchangeable With Analog Devices
AD7528 and PMI PM-7528
• Fast Control Signaling for Digital Signal
Processor (DSP) Applications Including
Interface With TMS320
AGND
OUTA
RFBA
REFA
DGND
DACAtDACB
(MSB) DB7
DB6
DB5
DB4
• Voltage-Mode Operation
• CMOS Technology
KEY PERFORMANCE SPECIFICATIONS
Resolution
Linearity Error
Power Dissipation at VDD = 5 V
Settling lime at VDD = 5 V
Propagation Delay lime at VDD = 5 V
OUTB
RFBB
REFB
3
VDD
WR
CS
DBO (LSB)
DB1
DB2
DB3
7
8
9
11
FN PACKAGE
(TOP VIEW)
8 bits
112 LSB
20mW
100 ns
80 ns
c(~~f!:!m
fe
::> ~
:::dE
a:Oc(Oa:
REFA
DGND
DACNDACB
(MSB) DB7
DB6
description
4
5
6
7
3 2 1 20 19
18
17
REFB
VDD
16 WR
The TLC7528C, TLC7528E, and TLC75281 are
15 CS
dual, 8-bit, digital-to-analog converters designed
with separate on-chip data latches and feature
4 DBO (LSB)
8 9 1011 12
exceptionally close DAC-to-DAC matching. Data
is transferred to either of the two DAC data latches
1B
Iii gu~ iii
through a common, 8-bit, input port. C.ontrol input
00000
DACAlDACB determines whiCh DAC is to be
loaded. The load cycle of these devices is similar
to the write cycle of a random-access memory, allowing easy interface to most popular microprocessor buses
and output ports. Segmenting the high-order bits minimizes glitches during changes in the most significant bits,
where glitch impulse is typically the strongest.
d
These devices operate from a 5-V to 15-V power supply and dissipates less than 15 mW (typical). The 2- or
4-quadrant multiplying makes these devices a sound choice for many microprocessor-controlled gain-setting
and signal-control applications. It can be operated in voltage mode, which produces a voltage output rather than
a current output. Refer to the typical application information in this data sheet.
The TLC7528C is characterized for operation from O·C to 70·C. The TLC75281 is characterized for operation
from -25·C to 85·C. The TLC7528E is characterized for operation from -40·C to 85·C.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(OW)
CHIP CARRIER
(FN)
PLASTICOIP
(N)
O·Cto 70·C
TLC7528CDW
TLC7528CFN
TLC7528CN
-25·C to 85·C
TLC75281DW
TLC75281FN
TLC75281N
-40·C to 85·C
TLC7528EDW
TLC7528EFN
TLC7528EN
~lExAs
Copyright © 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 6S5303 • DALLAS. TEXAS 75265
3-63
TLC7528C,TLC7528E, TLC75281
DUAL 8-BIT MULTIPLYING,
DIGITAL-TO-ANALOG CONVERTERS
SLAS062A-JANUARY 1987 - REVISED MARCH 1995
functional block diagram
DBO 14
REFA
13
, -_ _ _3;;.. RFBA
4
12
Data
Inputs
••
•
~_ _=-2 OUTA
8
11
Input
Buffer
10
DACA
9
8
1
DB7 7
AGND
.--_ _-+~18 RFBB
r ......"',.....---+~20 OUTB
DACAlDACB 6
Logic
WR 16
CS 16
Control
REFB
operating sequence
141----;
...
1
14 4 - - - - tsu(CS) - -....
----~~------------~!--.
14---- teu(DAcl
DACAlDACB
--~I~
I'-lt!(CS)
---t.oMI4,....--.~I- It!(DAC)
I
I
I
J
~ tw(WR) ~
WR - - - - - - - - "
j.-- tsu(D)
DBO-DB7
------X
Jr~1------.1. -:
Data In Stable
,.th.;.(D.;.)_ _
X'-___
~TEXAS
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75286
TLC7528C, TLC7528E, TLC75281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062A- JANUARY 1987 - REVISED MARCH 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (to AGNO or OGNO) .................................... -0.3 V to 16.5 V
Voltage between AGNO and OGNO ........................................................ ±Voo
Input voltage range, VI (to OGNO) .............................................. -0.3 V to Vee + 0.3
Reference voltage, VrefA or VrefB (to AGNO) ................................................ ±25 V
Feedback voltage VRFBA or VRFBB (to AGNO) ..•........................................... ±25 V
Output voltage, VOA or VOB (to AGNO) ..................................................... ±25 V
Peak input current ....................................................................... 10 ~
Operating free-air temperature range, TA: TLC7528C .................................. O°C to 70°C
TLC75281 .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -25°C to 85°C
TLC7528E ................................ -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 10 seconas, Tc: FN package ....................• . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: OW or N package ............... 260°C
t Stresses beyond those listed under "absolu1e maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
voo = 4.75 V to 5.25 V
MIN
NOM
MAX
VOO = 14.5 V to 15.5 V
MIN NOM
MAX
±10
±10
Reference voltage, VrefA or VrefB
2.4
High-level input voltage, VIH
50
CS setup time, tsu(CSl
CS hold time, th(CS)
V
13.5
V
1.5
0.8
Low-level input voltage, ViL
UNIT
V
50
ns
0
0
ns
DAC select setup time, tsu(DACl
50
50
ns
DAC select hold time, th(DACl
10
10
ns
Data bus input setup time tsu(Dl
Data bus input hold time th(Dl
25
25
ns
10
10
ns
Pulse duration, WR low, twlWRl
50
50
TLC7628C
Operating free-air temperature, TA
ns
0
70
0
70
TLC76281
-25
85
-25
85
TLC7628E
-40
85
-40
85
·C
~TEXAS
INSTRUMENTS
POST OFFICE sox 655303 • DALLAS. TEXAS 75265
3-65
TLC7528C, TLC7528E, TLC75281
DUAL 8·BIT MULTIPLYING
DIGITAL·TO..ANALOG CONVERTERS
SLAS062A-JANUARY 1987 - REVISED MARCH 1995
electrical characteristics over recommended operating free-air temperature range,
VrefA VrefB 10 V, VOA and VOB at 0 V (unless otherwise noted}
=
=
PARAMETER
TEST CONOITIONS
IIH
High-level input current
VI-VOD
IlL
Low-level input current
VI-O
VOO=5V
MIN TYPt MAX
10
5
Reference input impedance
REFA or REFB to AGNO
Ilkg
100
Supply current (standby)
Ci
Co
Input capacitance
jIA
jIA
20
20
kO
12
±200
OUTB
OAC data latch loaded with
00000000, VrefB = ±10 V
±400
±200
nA
±1%
±1%
.t\VOO=±10%
All digital inputs at VIHmin or
VILmax
0.04
0.02
%1%
2
2
mA
All digital inputs at 0 V or VOO
mA
0.5
0.5
OBa-OB7
10
10
pF
WR,CS,
DACAlOACB
15
15
pF
DAC data latches loaded with
00000000
50
50
DAC data latches loaded with
11111111
120
120
Output capacitance (OUTA, OUTB)
t All typical values are at TA _ 25°C. •
~1ExAs
3-66
10
5
±400
DC supply sensitivity, .t\gainl.t\Voo
UNIT
-10
-10
DAC data latch loaded with
00000000, VrefA = ±10 V
. Input resistance match (REFA to REFB)
Supply current (quiescent)
12
OUTA
Output Leakage Current
100
VOO=15V
MIN TYpf MAX
INSTRUMENTS
POST OFFICE BOX 665303 • DALlAS. TEXAS 75265
pF
TLC7528C, TLC7528E, TLC75281
DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
SLAS062A - JANUARY 1987 - REVISED MARCH 1995
operating characteristic over recommended operating free·air temperature range,
VrefA VrefB 10 V, VOA and VOB at 0 V (unless otherwise noted)
=
=
PARAMETER
TEST CONOITIONS
VOO=5V
MIN
TYP
VOO=15V
MAX
MIN
TYP
MAX
UNIT
±1/2
±112
Settling time (to 1/2 LSB)
See Note 1
100
100
ns
Gain error
See Note 2
2.5
2.5
LSB
-65
-65
-65
-65
Linearity error
AC feedthrough
I REFA to OUTA
I REFB to OUTB
See Note 3
Temperature coefficient of gain
See Note 4
0.007
Propagation delay (from digital input to
90% of final analog output current)
See Note 5
80
Channel-to-channel
isolation
I REFA to OUTB
I REFB to OUTA
LSB
dB
0.0035 %FSRI"C
80
See Note 6
77
77
See Note 7
77
77
ns
dB
Digital-to-analog glitch Impulse area
Measured for code transition from
00000000 to 11111111, TA = 25°C
160
440
nVos
Digital crosstalk
Measured for code transition from
00000000 to 11111111, TA=25°C
30
60
nVos
Harmonic distortion
Vi=6V,
-85
-85
NOTES: 1.
2.
3.
4.
5.
6.
7.
f= 1 kHz, TA-25°C
dB
OUTA, OUTB load = 100 n, Cext = 13 pF; WR and CS at 0 V; DBa-DB7 at 0 V to VDD or VDD to 0 V.
Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = Vref - 1 LSB.
Vref = 20 V peak-to-peak, 1OO-kHz sine wave; DAC data latches loaded with 00000000.
Temperature coefficient of gain measured from O°C to 25°C or from 25°C to 70°C.
VrefA = VrefB = 10 V; OUTAlOUTB load = 100 Cl, Cext = 13 pF; WR and CS at 0 V; DBa-DB7 at 0 V to VDD or VDD to 0 V.
Both DAC latches loaded with 11111111; VrefA = 20 V peak-to-peak, 100-kHz sine wave; VrefB = 0; TA = 25°C.
Both DAC latches loaded with 11111111; VrefB = 20 V peak-Io-peak, 100-kHz sine wave; VrefA = 0; TA = 25°C.
PRINCIPLES OF OPERATION
These devices contain two identical, 8-bit-multiplying D/A converters, DACA and DACB ..Each DAC consists
of an inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched
between DAC output and AGND, thus maintaining a constant current in each ladder leg independent of the
switch state. Most applications require only the addition of an external operational amplifier and voltage
reference. A simplified D/A circuit for DACA with all digital inputs low is shown in Figure 1.
Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB. Both DACs
share the analog ground terminal 1 (AGND). With all digital inputs high, the entire reference current flows to
OUTA. A small leakage current (llkg) flows across internal junctions, and as with most semiconductor devices,
doubles every 1DoC. Co is due to the parallel combination of the NMOS switches and has a value that depends
on the number of switches connected to the output. The range of Co is 50 pF to 120 pF maximum. The equivalent
output resistance (r0) varies with the input code from 0.8R to 3R where R is the nominal value of the ladder
resistor in the R-2R network.
These devices interface to a microprocessor through the data bus, CS, WR, and DACAlDACB control signals.
When CS and WR are both low, the TLC?528 analog output, specified by the DACAlDACB control line, responds
to the activity on the DBO-DB? data bus inputs. In this mode, the input latches are transparent and input data
directly affects the analog output. When either the CS signal or WR si~1 goes high, the data on the DBO-DB?
inputs is latched until the CS and WR signals go low again. When CS is high, the data inputs are disabled
regardless of the state of the WR signal.
~TEXAS
INSTRUMENTS
POST OFFICE BOX ~3 -DAlLAS, TEXAS 75265
3-67
TLC7528C, TLC7528E, TLC75281
DUAL 8-81T MULTIPLYING
DI.GITAL·T()'ANALOG CONVERTERS
SLAS082A- JANUARY 1987 - REVISED MARCH 1896
PRINCIPLES OF OPERATION
The digital inputs of these devices provide TTL compatibility when operated from a supply voltage of 5 V. These
devices can operate with any supply voltage in the range from 5 V to 15 V; however, input logic levels are not
TTL compatible above 5 V.
REFA
R
R
R
---~".".,.......~,....-\
2R
2R
2R
2R
2R
(
:
An
y1~S8
RFBA
OUTA
I
AGND
DACA Data LatchH and Drivers
Figure 1. Simplified Functional Circuit for DACA
RFBA
R
. REFA--'V'II'v---..-----....- - - . - . . - - OUTA
I
Illeg
i5ii
t
CoUT
~----..---~-----AGND
Figure 2. RC7528 Equivalent Circuit, DACA Latch Loec:Iec:I With 11111111
MODE SELECTION TABLE
9 9m DACA DACB
L
L
Write
Hold
L
Write
H
L
L
Hold
X
H
X
Hold
Hold
X
X
H
Hold
Hold
L • low level. H • high level. X • don't care
6ACAiDACB
~1ExAs
3-68
INSIRUMENTS
POST OFFICE BOX _ . DALI.AS. TEXAS 76286
TLC7528C, TLC7528E, TLC75281
DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
SLAS062A - JANUARY 1987 - REVISED MARCH 1995
APPLICATION INFORMATION
These devices are capable of performing 2-quadrant or full4-quadrant multiplication. Circuit configurations for
2-quadrant and 4-quadrant multiplication are shown in Figures 3 and 4. Tables 1 and 2 summarize input coding
for unipolar and bipolar operation.
VI(A)
±10V
R1 (see Note A)
VDD
DBO
17r-------------------
141
: I
•
R2 (see Note A)
RFBA
REFA
......-"-.....
~~---4--~-I
Input
Buffer
DB7-+---I
7 I
I
I
I
I
I
I
DACA/DACB~6~-~
15 I
cs -'=-+-----1
WR_1~61i--1______~
DGND~
.
_ L___________________ _____
REFB
RECOMMENDED TRIM
RESISTOR VALUES
R1, R3
R2, R4
~
~
AGND
R3 (see Note AI
VI(B)
±10V
5000
1500
NOTES: A. R1, R2, R3, and R4 are uSed only if gain adjustment is required. See table for recommended values. Make gain adjustment with
digital input of 255.
B. C1 and C2 phase compensation capacitors (10 pF to 15 pF) are required when using high-speed amplifiers to prevent ringing or
oscillation.
Figure 3. Unipolar Operation (2-Quadrant Multiplication)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAs, TEXAS 75265
3-69
TLC7528C, TLC7528E, TLC75281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062A- JANUARY 1987 - REVISED MARCH 1995
APPLICATION INFORMATION
:~~~
R6
20kn
(_Note B)
RFBA
R2 (_Note A)
,..--------------
..1l..f
VDD
DBO
14
Input
Buffer
R7
10kn
8
R5
20kn
DB7
DACAl
DACB
VOA
R11
5kn
i-i--r--l.-,1-1----,
R8
20kn
CS .....1-,£5-!----1
WR 16
5
I
I
~IL ______________ _
R9
10kn
(_NoteB)
I
DGND
VOB
R11
5kn
':" AGND
R10
20kn
(aeeNote B)
VI(B)
±10~
NOTES: A. R1. R2. R3. and R4 are used only if gain adjustment is required. See table in Figure 3 for recommended values. Adjust R1 for
VOA - 0 V with code 10000000 in DACA latch. Adjust R3 for VOB - 0 V with 10000000 in DACB latch.
B. Matching and tracking are essential for resistor pairs R6. R7. R9. and R10.
C. C1 and C2 phase compensation capaCitors (10 pF to 15 pF) may be required if A1 and A3 are high-speed amplifiers.
Figure 4. Bipolar Operation (4-Quadrant Operation)
Table 2. Bipolar (Offset Binary) Code
Table 1. Unipolar Binary Code
DAC LATCH CONTENTS
MSB
LSBt
11111111
10000001
10000000
01111111
00000001
00000000
ANALOG OUTPUT
-VI (2551256)
-VI (1291256)
'-VI (1281256) - -Vj12
-VI (127/256)
-VI (1/256)
-VI (0/256) = 0
~TEXAS
3-70
DAC LATCH CONTENTS
MSB
LSB:t:
11111111
10000001
10000000
01111111
00000001
00000000
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
ANALOG OUTPUT
VI (127/128)
VI (1/128)
OV
-VI (11128)
-VI (127/128)
-VI (1281128)
TLC7528C, TLC7528E, TLC75281
DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
SLAS062A- JANUARY 1987 - REVISED MARCH 1995
APPLICATION INFORMATION
microprocessor Interface Information
A8-A15
Add ..... Bua
~____-,
....-----.....- - - - - - - f DACA/DACB
Add.....
Decode
Logic
CPU
8051
A
cs
, - - - - t - - - - - - - I WR TLC7528
DBO
••
WRI-----l
DB7
ALE
--v
ADO_AD7~__~______~____~Dam~B~u~a~____________
NOTE A: A = decoded address for TLC7528 DACA
A + 1 - decoded address for TLC7528 DACe
Figure 5. TLC7528 -Intel 8051 Interface
A8-A15
~____-,
VMA
CPU
6800
+21----1
ADO-AD7~
____~__~r-
__
~~
__________________--v
NOTE A: A. decoded address for TLC7528 DACA
A + 1 - decoded address for TLC7528 DACe
Figure 6. TLC7528 - 6800 Interface
~1ExAs
INSTRUMENTS
POST OFFICE BOX _
• DAu.AS, TEXAS 752615
3-71
TLC7528C,TLC7528E, TLC75281
DUAL 8~BIT MULTIPLYING
DIGITAL';TO·ANALOG CONVERTERS
SLAS062A-JANUARY 1987 - REVISED MARCH 1995
APPLICATION INFORMATION
8
Address Bus
A8-A15 t - - - - ,
,....-----+--:.....--1 DACA/DACB
Address
Decode
Logic
IORQ
A
CS
TLC7528
, . . . . - - -....- - - - 1 WR
CPU
zso..A
D,O
•
DB7
WRt-----L~
8
DO_D7t-_ _ _ _~~:.....-D~am~B~us:.....----------~
NOTE A: A = decoded address for TLC7fj28 DACA
A + 1 decoded address for TLC7528 DACB
K
Figure 7. TLC7528 To Z·80A Interface
programmable window detector
The programmable window comparator shown in Figure 8 determines if voltage applied to the DAC feedback
resistors are within the limits programmed into the data latches of these devices. Input signal range depends
on the reference and polarity. that is.• the test input range is 0 to -Vref. The DACA and DACB data latches are
programmed with the upper and lower test limits. A signal within the programmed limits drives the output high.
~TEXAS
3-72
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC7528C, TLC7528E, TLC75281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062A- JANUARY 1987 - REVISED MARCH 1995
APPLICATION INFORMATION
VDD
Testlnput
Oto-Vraf
VCC
-~.------...,
17
3
RFBA
1 k.Q
4
REFA
Data Inputs
~8'-'Hf-1;,;;:4....-7:.t DBO-DB7
TLC7528
_ _~~_1~5 CS
AGND--~-'~""
PASS/FAIL Output
_ _+.-1-....:1,6 WR
6 DACA/DACB
_ _+'-1---'-t
20
18 REFB
Vraf --+-4.........:..:..1-'-'"'''-=--1
5 DGND
RFBB
19
Figure 8. Digitally-Programmable Window Comparator (Upper- and Lower-Limit Tester)
digitally controlled signal attenuator
Figure 9 shows a TLC7528 configured as a two-channel programmable attenuator. Applications include stereo
audio and telephone signal level control. Table 3 shows input codes vs attenuation for a 0 to 15.5 dB range.
Attenuation dB
VDD
=-20 10910 D/256, D =digital Input code
17
VIA _ _ _ _ _ _..:.4+R~E....:FA..,
RFBA
3
OUTA
2
Output
DBO-DB7
TLC7528
8
14-7
1----.,.--Data Bus
CS
WR
DACA/DACB
REFB
AGND
DGND
15
16
6
18
1
5
19 " -_ _ _ _ _ _ _ _....
Figure 9. Digitally Controlled Dual Telephone Attenuator
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-73
TLC7528C, TLC7528E,TLC75281
DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
SLAS062A-JANUARY 1ge7-REVISED MARCH 1995
APPLICATION INFORMATION
Table 3. Attenuation vs DACA, DACB Code
ATTN (dB)
DAC INPUT CODE
0
11111111
0.5
11110010
1.0
11,100100
1.5
11010111
2.0
2.5
CODE IN
DECIMAL
ATTN (dB)
DAC INPUT CODE
CODE IN
DECIMAL
255 '
242
8.0
01100110
102
8.5
01100000
96
228
215
9.0
9.5
01011011
91
01010110
86
11001011
11000000
203
10.0
192
10.5
01010001
01001100'
81
76
3.0
3.5
10110101
10101011
181
11.0
01001000
72
4.0
4.5
10100010
10011000
171
162
11.5
12.0
01000100
01000000
00111101
68
64
61
5.0
10011111
5.5
152
12.5
13.0
13.5
00111001
97
10001000
144
136
00110110
54
6.0
6.5
10000000
01111001
128
121
14.0
51
14.5
00110011
00110000
7.0
01110010
114
15.0
00101110
46
7.5
01101100
108
15.5
00101011
43
48
programmable state-variable filter
This programmable state-variable or universal filter configuration provides low-pass, high-pass, and bandpass
outputs, and is suitable for applications requiring microprocessor control of filter parameters.
As shown in Figure 10, DACA 1 ~nd DACB1 control the gain and Q of the filter while DACA2 and DACB2 control
the cutoff frequency. Both halves of the DACA2 and DACB2 must track accurately in order for the
cutoff-frequency equation to be true. With the TLC7528, this is easy to achieve.
f 1
c - 21t R1C1
The programmable range for the cutoff or center frequency is 0 to 15 kHz with a Q ranging from 0.3 to 4.5. This
defines the limits of the component values.
:lllExAs
3-74
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC7528C, TLC7528E, TLC75281
DUAL 8-81T MULTIPLYING
DIGITAL·TO-ANALOG CONVERTERS
SLAS082A- JANUARY 1987 - REVISED MARCH 1995
APPLICATION INFORMATION
C3
47pF
4 REFA
OUTA 2
VI --+=-=::':"':;'---1
17
VDD
Data In
RFBA
8 14-7
R5
3OkO
R4
3
AGND 1
R3
15
18
CS
WR
5
-=-
OUTB 20
RFBB
DGND
8
HlghPaaa
Out
10kO
19
REFB 18
DACA/DACB
Bandpaaa Out
DACAl AND DACBl
C1
OUTA 2
4 REFA
17
Data In
VDD
814-7
15
18
RFBA
DBO-DB7
C2
AGND 1
TLC7528
1000pF
CS
OUTB 20
WR
RFBB
5
-=-
3
19
>--41..-- Low Paaa Out
REFB 18
8
DACA/DACB
DACA2 and DACB2
Circuit Equatlona:
C1 =C2, R1 = R2, R4=
Q
R3
=- -
R4
Rs
RF
• ..----"-Rfb(DACB1)
where:
Rfb la the Intarnal reslator connectad between OUTB and RFBB
G = _ RF
RS
NOTES: A. Op-amps A1, A2, AS, and A4 are TL287.
B. OS compensates for the op-amp gain-bandwidth limitations.
258 x (CAC ladder resistance)
C. CAC equivalent resistance equals
CAC digital code
Figure 10. Digitally Controlled State-Variable Filter
~ThxAs
INSTRUMENTS
POST OFFICE BOX _ . DALLAS. TEXAS 76266
3-75
'TlC7528C, TLC7528E, TLC75281
DUAL 8-81T MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
SLAS062A- JANUARY 1987 - REVISED MARCH 1995
APPLICATION INFORMATION
voltage-mode operation
It is possible to operate the current multiplying O/A converter of these devices in a voltage mode. In the voltage
mode, a fixed voltage is placed on the current output terminal. The analog output voltage is then available at
the reference voltage terminal. Figure 11 is an example of a current multiplying O/A, that operates in the voltage
mode.
R
R
R
REF--+-~~~~~~~--~~~~---.
(Analog Output Voltage)
2R
2R
2R
2R
R
......---+__4I..._---
L----+~~----+-
L-____~~------......----~~~----
Out (Fixed input Voltage)
AGND
Figure 11. Voltage-Mode Operation
The following equation shows the relationship between the fixed input voltage and ,the analog output voltage:
Vo = VI (0/256)
where
Vo = analog output voltage
VI = fixed input voltage
o = digital input code converted to decimal
In voltage-mode operation, these devices meets the following specification:
PARAMETER
LinearitY,error at REFA or REFB
3-76
TEST CONDITIONS
VDD = 5 V,
OUTA or OUTB at 2.5 V,
-!!1
TEXAS:
INSTRuMENTS
POST OFFICE apx 655303 • DALLAS. TEXAS 75265
TA = 25°C
TLC7628C, TLC7628E, TLC76281
DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
Sl.AS063A-APRIL 1989 - REVISED MAY 1995
• Easy Microprocessor Interface
• On-Chip Data Latches
• Digital Inputs Are TTL-Compatible With
10.8-V to 15.75-V Power Supply
• Monotonic Over the Entire AID Conversion
Range
• Fast Control Signaling for Digital Signal
Processor (DSP) Applications Including
Interface With TMS320
ow OR N PACKAGE
(TOP VIEW)
• CMOS Technology
DB6
DB5
DB4
KEY PERFORMANCE SPECIFICATIONS
8 bits
1/2 LSB
20mW
100 ns
80 ns
f!esolution
Linearity Error
Power Dissipation
Settling Time
Propagation Delay Time
OUTB
RFBB
REFB
AGND
OUTA
RFBA
REFA
DGND
DACNDACB
(MSB) DB?
VDD
WR
CS
DBD (LSB)
DBl
8
9
DB2
DB3
FN PACKAGE
(TOP VIEW)
description
The TLC?628C, TLC7628E, and TLC26281 are
dual, 8-bit, digital-to-analog converters (DACs)
designed with separate on-chip data latches and
feature exceptionally close DAC-to-DAC
matching. Data is transferred to either of the two
DAC data latches through a common, 8-bit input
port. Control input DACAlDACB determines which
DAC is loaded. The load cycle of these devices is
similar to the write cycle of a random-access
memory, allowing easy interface to most popular
microprocessor buses and output ports.
Segmenting the high-order bits minimizes glitches
during changes in the most significant bits, where
glitch impulse is typically the strongest.
REFA
(MSB) DB?
4
5
6
7
DB6
8
DGND
DACNDACB
3 2
1 20 19
18
REFB
17
16
VDD
WR
CS
15
14
9 1011 1213
DBD (LSB)
The TLC7628C operates from a 1O.8-V to 15.75-V power supply and is TTL-compatible over this range. 2- or
4-quadrant multiplying makes these devices a sound choice for many microprocessor-controlled gain-setting
and signal-control applications.
The TLC6728C is characterized for operation from O°C to 70°C. The TLC76281 is characterized for operation
from -25°C to 85°C. The TLC7628E is characterized for operation from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
PLASTICOIP
(OW)
PLASTIC CHIP
CARRIER
(FN)
PLASTICOIP
(N)
O·Cto 70·C
TLC7628CDW
TLC7628CFN
TLC7628CN
-25·C to 85·C
TLC7628IDW
TLC76281FN
TLC76281N
-40·C to 85·C
TLC7628EDW
TLC7628EFN
TLC7628EN
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST oFFice BOX 655303 • DALLAS. TeXAS 75265
3-n
TLC7628C, TLC7628E, TLC76281
DUAL 8-81T MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
SLAS063A-APRIL 1989 - REVISED MAY 1995
functional block diagram
14
REFA
r--~_ _ _3,,- RFBA
13
4
12
Data
Inputs
•••
11
10
Input
Buffer
~_ _.;;;..2 OUTA
8
DACA
9
8
DB7
DACAlDACB
AGND
7
....-_ _ _1---'1..;;..9
r"'--'"'\,,----t-.J20~ OUTB
6
16
WR
15
CS
RFBB
,Logic
Control
Latch B
8
REFB
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Voo (to AGND or DGND) ..........................•........... -0.3 Vto 17 V
Voltage between AGND and DGND ...•..................................•......•.••......... Voo
Input voltage range, VI (to DGND) •....•.............................•....•..• -0.3 V to VOO + 0.3 V
Reference voltage range, VrefA or VrefB (to AGND) . • . . . . . • . . . • . . . • . . . . . . . . . . • . . • . . . . . . . • . • .. ±25 V
Feedback voltage range, VRFBA or VRFBB (to AGND) ...............•.•.•.............••.... ±25 V
Output voltage range, VOA or VOB (to AGND) .••......•...................•.......•.•.•...•• ±25 V
Peak input current ...............................•. • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . .• 10 JJA
Operating free-air temperature range, TA: TLC7628C ...............................•• O°C to 70°C
TLC76281 ......••........•...•...........• -25°C to 85°C
TLC7628E ...•............................ -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 10 seconds, Tc: FN package .......................••••...•••••.•..•• 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package • . . . . . . . . . . . . 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolut.-maximum-rated conditions for extended periods may affect device reliability.
~1ExAs
3-78
INSTRUMENTS
POST OFFICE BOX 656303 ,- DALLAS. TEXAS 75265
TLC7628C, TLC7628E, TLC76281
DUAL 8-81T MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A-APRIL 1989-REVISED MAY 1995
recommended operating conditions
MIN
Supply voltage, VDD .
NOM
10.8
Reference vo~age, VrefA or VrefB
MAX
UNIT
15.75
V
±10
V
2.4
High-level input voltage, VIH
V
Low-level input voltage, VIL
0.8
CS setup time, tsu(CS)
V
50
ns
0
ns
DAC select setup time, tsuCDAC) (see Figure 1)
60
ns
DAC select hold time, th(DAC) (see Figure 1)
10
ns
Data bus input setup time tsu(Pt (see Figure 1)
25
ns
Data bus input hold time th(Dl (see Figure 1)
10
ns
Pulse duration, WR 10w,iw(WR) (see Figure 1)
50
CS hold time, thlCSI (see Figure 1)
TLC7628C
Operating free-air temperature, TA
ns
0
70
TLC76281
-25
85
TLC7628E
-40
85
°C
electrical characteristics over recommended ranges of operating free-air temperature and Voo,
VrefA =VrefB =10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IIH
High-level input current
VI ~ VDD
IlL
Low-level input current
VI =0
MIN
10
25°C
1
Full range
-10
25°C
-1
Reference input impedance REFA or REFB to
AGND
5
OUTA
Ikg
Output leakage current
OUTB
DAC data latch loaded with 00000000,
Full range
25°C
±50
Full range
±200
Vre fB=±10V
25°C
t.VDD = ±5 %
Quiescent
Ci
Input capacitance
Co
Output capacitance (OUTA, OUTB)
UNIT
IlA
I!A
kQ
±200
nA
±50
±1%
DC supply sensitivity t.gainlt.VDD
Supply current
20
VrefA - ±10 V
DAC data latch loaded with 00000000,
Input resistance match (REFA to REFB)
IDD
MAX
Full range
Full range
0.02
25°C
0.01
2
All digital inputs at VIHmin or VI Lmax
Standby
All digital inputs at 0 V or VDD
%/%
Full range
0.5
25°C
0.1
DBO-DB7
10
WR,CS,
DACAlDACB
15
DAC data latches loaded with 00000000
25
DAC data latches loaded with 11111111
60
mA
pF
pF
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-79
TLC7628C, TLC7628E, TLC7Q281
DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
SLAS063A-APRIL 1989 - REVISED MAY 1996
operating characteristics over recommended ranges of operating free-air temperature and VDD,
VrefA = VrefB = 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER
MIN
TEST CONDITIONS
TYP
Linearity error
Settling time (10 1/2 LSB)
See Note 1
Gain error
AC feedthrough
See Note 2
I REFA to OUTA
I REFB to OUTB
See Note 3
Channel-io-channel
isolation
I REFA to OUTB
I REFB to OUTA
UNIT
±112
LSB
100
ns
Full range
±S
25°C
±2
Full range
-65
25°C
-75
Temperature coefficient of gain
Propagation delay (from digital input to
90% of final analog output current)
MAX
LSB
dB
±0.0035 %FSRI"C
80
See Note 4
See Note 5
25°C
80
See Note 6
25°C
80
Digital-ta-analog glitch impulse area
Measured for code transition from 00000000 10 11111111,
TA .. 25°C
Digital crosstalk
Measured for code transition from 00000000 10 11111111,
TA=25°C
Harmonic disiorlion
Vi - 6 V, f .. 1 kHz,
,
dB
330
nVes
60
nVes
-65
TA-25°C
ns
dB
NOTES: 1. OUTA,OUTB load .1000, Cext-13pF; WRandCSatOV;DBO-OB7atOVIoVDD orVODIoOV.
2. Gain error Is measured using an Internal feedback resistor. Nominal full scale range (FSR) - Vref - 1 LSB. Both OAC latches are
loaded with 11111111.
3. Vref" 20 V peak-to-peak, 1o-kHz sine wave
4. VrefA" VrefB =10 V; OUTA/OUTB load .100 0, Cext-13 pF; WR andCS atO V; DBa-OB7 at 0 Vio VOO orVOO 10 0 V.
5. VrefA - 20 V peak-to-peak, 1o-kHz sine wave; VrefB - 0
6. VrefB" 20 V peak-to-peak, 1D-kHz sine wave; VrefA • 0
141..- -
A
J~~~_ ::::
tsu(CS) -~.1~4-~.If- tt.(CS)
j
--1.S-Y"\!
1.3Y
, ~~_ _ _ _ _ _...jI_,J. -1----
3.5 V
O.3Y
141
..- - tau(DAC) --I.~I4II---..II-tt.(DAC)
!
DACAlDACB --1.-S"Y\ •
I+-
tw(WR)
-----1.-3"Y'\
I+DBO-DB7 -----1-.S-Y""*
tau(D)
-+I
411'_"'!1"'!~"!'!~-_-_-_-_- ::::
.14.1
Data In Stable
tt.(D)
X. .
;_.3_Y
_ _ _ 3.5 Y
For all input Signals, tr .. tf .. 5 ns (10% to 90% points).
Figure 1. Setup and Hold Times
~TEXAS
3-80
INSTRUMENTS
POST OFFICE BOX 1155303 • DALLAS. TEXAS 75265
O.3Y
TLC7628C, TLC7628E, TLC76281
DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
SLAS063A-APRIL 1989-REVISED MAY 1995
APPLICATION INFORMATION
These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant and 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and bipolar
operation are summarized in Tables 2 and 3, respectively.
VI (A)
±10V
Voo ~o;;---------------REFA
,• I •
: I :
7
Input
Buffer
8
8
>---*-
VOA
IOB7
16
Ig:g:'
15
CS
16
I
WR
C2 (see Note B)
Control
Logic
>--it- VOB
"::" r-:::::CC
:-:O'"'"M'"'"M:::E""'N""OE""O:-:T""R""IM-:-"1
RE
RESISTOR VALUES
R1, R3
R2, R4
5000
1500
VI(B)
±10V
NOTES: A. R1, R2, R3. and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment w~h
dig~al input of 255.
B. C1 and C2 phase compensation capacitors (10 pF to 15 pF) are required when using high-speed amplifiers to prevent ringing or
oscillation.
Figure 2. Unipolar Operation (2·Quadrant Multiplication)
-!!11ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-81
TLC7628C, TLC7628E, TLC76281
DUAL 8-81T MULTIPLYING·
DIGITAL·TO·ANALOG CONVERTERS
SLAS063A- APRIL 1989 - REVISED MAY 1996
.
APPLICATION INFORMATION
VI(A)
±10V
R8(_t-......- -
DACA
>-.......- -
DACB
>-.......- -
DACC
>-.......- -
DACD
REFB
REFC _ _---'.I'.....
>-.......+++----~----;--~
REFD
"'tJ
::D
0
CLK
DATA
LOAD
Serial
Interface
LDAC
C
C
Power-On
Reset
Terminal Functions
(')
TERMINAL
-I
NAME
ClK
~
m
<
-
DACA
m
~
NO.
1/0
DESCRIPTION
7
I
Serial-interface clock, data enters on the negative edge
12
DAC A analog output
DACB
11
DACC
10
DACD
9
0
0
0
0
DAC B analog output
DAC C analog output
DACD analog output
DATA
6
I
Serial-interface digital-data input
GND
1
I
Ground return and reference terminal
lDAC
13
I
DAC-update .Iatch control
lOAD
8
I
Serial-interface load control
REFA
2
I
Reference I(oliage input
REFB
3
I
Reference voltage input to DACB
REFC
41
I
Reference voltage input to DACC
REFD
5
I
Reference voltage input to DACD
14
I
Positive supply voltage
VDD
to DACA
detailed description
The TLV5620 is implemented using four resistor-stringdigital-to-analog converters (DACs). The core of each
DAC is a single resistor with 256 taps, corresponding to the 256 possible codes listed in Table 2. One end of
each resistor string is connected to the GND terminal and the other end is fed from the output of the reference
input buffer. Monotonicity is maintained by use of the resistor strings. Linearity depends upon the matching of
the resistor elements and upon the performance of the output buffer. Because the inputs are buffered, the DACs
always presents a high-impedance load to the reference source.
~TEXAS
3-88
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS. TEXAS 75265
TLV5620C, TLV56201
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS110-JANUARY 1995
detailed description (continued)
Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or
times 2 gain.
On powerup, the DACs are reset to CODE O.
Each output voltage is given by:
VO{DACAIBICID) = REF x Cfs~E x (1
+ RNG bit value)
where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial-control word.
data interface
With lOAD high, data is clocked into the DATA terminal on each falling edge of ClK. Once all data bits have
been clocked in, lOAD is pulsed low to transfer the data from the serial-input register to the selected DAC as
shown in Figure 1. If lDAC is low, the selected DAC output voltage is updated and lOAD goes low. If lDAC
is high during serial programming, the new value is stored within the device and can be transferred to the DAC
output at a later time by pulsing lDAC low as shown in Figure 2. Data is entered MSB first.
"'C
--I '-- tsu(DATA.ClK)
o
1--1
C
c:
o-f
"'C
:xl
W
I
:;
tsu(LOAD.ClK) - ; - - - - I 4 - -..
~1
14- tv(DATA·ClK)
w
a:
DATA
a..
I-
o
LOAD
m
<
m
-
==
;:
ClK
:xl
Figure 1. LOAD-Controlled Update (LDAC
:J
C
=Low)
oa:
a..
ClK
DATA
DO
tsu(lOAD-lDAC) -----14'+f
\)-+1--',-
lOAD
tw(lDAC)
lDAC
---l4-tt
V
1
DAC Update
Figure 2. LDAC-Controlled Update
data interface (continued)
Table 1 lists the A1 and AO bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applieo reference voltage and GND.
'!!1TEXAS INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75265
3-89
TLV5620C, TLV56201
QUADRUPLE 8-81T DIGITAL·TO·ANALOG CONVERTERS
SLASll 0 - JANUARY 1995
Table 1. Serial-Input Decode
A1
AO
0
DACUPDATED
0
0
1
DAce
1
0
DACC
1
1
DACD
DACA
Table 2. Ideal-Output Transfer
D7
D8
D5
D4
D3
D2
D1
DO
0
0
0
0
0
0
0
0
GND
0
0
0
0
0
0
0
1
(11256) x REF (l+RNG)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
OUTPUT VOLTAGE
0
1
1
1
1
1
1
1
(1271256) x REF (l+RNG)
1
0
0
0
0
0
0
0
(1281256) x REF (l+RNG)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
.1
·•
1
•
•
(2551256) x REF (l+RNG)
equivalent inputs and outputs
INPUT CIRCUIT
-
......-
OUTPUT CIRCUIT
-
VDD
......-VDD
Input from---Decoded DAC
>----.........
Register String
Vref
Input
ToDAC
Raalator
ISINK
8011A
String
--e--.....---4~
Typical
GND
.....-4~..... GND
~1EXAS
3-90
DAC
Voltage OUtput
.
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265
TLV5620C, TLV56201
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110-JANUARY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (Voo - GND) ................................................................. 7 V
Digital input voltage range ............................................. GND - 0.3 V to Voo + 0.3 V
Reference input voltage range, VID ...................................... GND - 0.3 V toVoo + 0.3 V
Operating free-air temperature range, TA: TLV5620e .................................... ooe to 70°C
TLV56201 ................................... -40°C to 85°C
Storage temperature range, Tst~ .................................................. -50°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ... . . . . . . . . . . . . . . . . . . . . . . . . . . .. 230°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Supply voltage, VOO
High-level digital input voltage, VIH
MIN
NOM
MAX
UNIT
2.7
3.3
5.25
V
V
0.8VOO
0.8
low-level digital input voltage, Vil
Reference voltage, Vref [AIBICIO), xl gain
VOD-lo5
load resistance, Rl
10
V
V
kO
Setup time, data input, tsu(DATA-ClK} (see Figures 1 and 2)
50
ns
Valid time, data input valid atter ClK.!., tv(DATA-ClK) (see Figures 1 and 2)
50
ns
Setup time, ClK eleventh falling edge to lOAD, tsu(ClK-lOAO) (see Figure 1)
50
ns
~
W
:;
w
IX:
Q.
50
ns
Pulse duration, lOAD, tw(lOAO) (see Figure 1)
250
ns
Pulse duration, lDAC, tw(lDAC) (see Figure 2)
250
ns
(,)
ns
::l
C
Setup time, lOADi to ClK.!., tsu(lOAO-ClK) (see Figure 1)
Setup time, lOADi to lDAC.!., tsu(lOAD-lDAC) (see Figure 2)
0
ClK frequency
Operating free-air temperature, TA
I TlV5620C
I TlV56201
0
-40
1
MHz
70
·C
85
'C
~TEXAS
INSTRUMENTS
POST OFFICE eox 655303 • DALlAS, TEXAS 75265
3-91
I-
oIX:
Q.
TLV5620C, TLV56201
QUADRUPLE 8-81T DIGITAL·TO·ANALOG CONVERTERS
SLASll 0 - JANUARY 1995
electrical characteristics over recommended operating free-air temperature range,
Voo 3 V to 3.6 V, Vref 2 V, x 1 gain output range (unless otherwise noted)
=
=
TEST CONDITIONS
PARAMETER
"H
IlL
High-I,evel digital input current
IO(sink)
Output sink current
IO(source)
Output source current
Low-level digital input current
Each oAC output
c:
~
"lJ
l:J
m
-<
m
~
UNIT
j.tA
±10
j.tA
j.tA
~
Supply current
Voo-3.3V
Iref
EL
Reference input current
Voo =3.3 V, Vref=1.5V
Vref = 1.25 V, x 2 gain (see Note 1)
Linearity error (end point corrected)
ED
Differential linearity error
EZS
Zero-scale error
pF
15
2
Vref =1.25 V, x 2 gain (see Note 2)
Vref - 1.25 V, x 2 gain (see Note 3)
Zero-scale error temperature coefficient
oC
±10
15
100
Full-scale error
Full-scale error temperature coefficient
Power-supply sensitivity
PSRR
MAX
2
I Reference Input capacitance
EFS
TYP
20
I Input capacitance
Ci
"lJ
l:J
MIN
V,.Voo
V,.OV
0
rnA
±10
j.tA
±1
LSB
±0.9
LSB
30
mV
Ilvrc
Vref - 1.25 V, x 2 gain (see Note 4)
Vref = 1.25 V, x 2 gain (see Note 5)
10
Vref - 1.25 V, x 2 gain (see Note 6)
See Notes 7 and 8
±25
Ilvrc
0.5
mVN
±60
mV
NOTES: 1. Integral nonlinearity (INL) Is the maximum deviation of the output from the line b/ltween zero ancJ full scale (axcludlng the effects
of zero code ancJ full-scale errors).
2. Differential nonlinearity (oNL) is the difference between the measured ancJ ideal 1 LSB amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a change In the digital input cede.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zera-scale error temperature coefficient is given by: ZSETC = [ZSE(Tmax) - ZSE(T min)]Nref x 106/(Tmax - Tmin>.
5. Full-scale error is the deviation from the ideal full-scale output (Vref - 1 LSB) with an output load of 10 len
6. Full-scale temperature coefficient is given by: FSETC • [FSE(Tmax) - FSE (T min)]Nref x 106/(T max - Tmin).
7. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the Voo voltage from 4.5 V to 5.5 V de and measuring the proportion
of this signal Imposed on the zero-code output voltage.
8. Full-scale error rejection ratio (FSE-RR) is measured by varing the Voo from 3.0 V to 3.6 V de and measuring the proportion of this
signal imposed on the full-scale output voltage.
operating characteristics over recommended operating free-air temperature range,
Voo 3 V to 3.6 V, Vref 2 V, x\1 gain output range (unless otherwise noted)
=
=
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
Output slew rate
CL-l00pF,
RL-l0kO
Output settling time
To 0.5 LSB,
CL= 100pF,
Large-signal bandwidth
Measured at -3 dB point
100
IlS
kHz
Digital crosstalk
CLK = l-MHz square wave measured at oACA-oACo
-50
dB
Reference feedthrough
See Note 10
-60
dB
Channel-ta-channel isolation
See Note 11
-60
dB
Reference input bandwidth
See Note 12
100
NOTES: 9.
10.
11.
12.
RL= 101<0, See Note 9
VlIlS
kHz
Settling time Is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 00 hex to FF hex or FF hex to 00 hex. For TLV5620C: Voo = 5 V, Vref • 2 V ancJ range = x2. For TLV56201: VOO - 3 V.
Vref = 1.25 V and range x2.
Referencefeedthrough is measured at any OAC output with an input code = 00 hex with a Vref input- 1 V de + 1 Vppat 10 kHz.
Channel-ta-channel isolation is measured by setting the input code of one OAC to FF hex and the code of all other OACs to 00 hex
wHh Vref input. 1 V de + 1 Vpp at 10 kHz.
'
Reference bandwidth is the -3 dB bandwidth with an input at Vref _ 1.25 V de + 2 Vpp , wHh a digital input code of full-scale.
~TEXAS
3-92
10
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLV5620C, TLV56201
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
\
SLASll0-JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
TLV5620
DACA 1-----.----,
DAce
.
101<0
CL
=100 pF
DACD
Figure 3. Slewing Settling Time and Linearity Measurements
APPLICATION INFORMATION
TLV5620
DACA
DAce
.
I--~~--I..,/
Vo
3:
w
5>
w
R
DACD
r:t
NOTE A: Resistor R 2: 10 kQ
0..
Figure 4. Output Buffering Schemes
ti::J
C
o
r:t
0..
-!!I TEXAS ,
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-93
3-94
TLV5628C, TLV56281
OCTAL 8-81T DIGITAL·TO·ANALOG CONVERTERS
•
•
•
•
•
•
•
•
•
NOR 0 PACKAGE
(TOP VIEW)
Eight 8-Blt Voltage Output DACs
3-V Single-Supply Operation
Serial Interface
High-Impedance Reference Inputs
Programmable 1 or 2 Times Output Range
Simultaneous-Update Facility
Internal Power-On Reset
Low Power Consumption
Half-Buffered Output
DACB
DACA
GND
DATA 4
ClK 5
VDD
DACE
DACF
DACC
DACD
REF1
lDAC
lOAD
6
DACH
DACG
applications
•
•
•
•
•
•
Programmable Voltage Sources
Digitally-Controlled AmpliflerslAttenuators
Mobile Communications
Automatic Test Equipment
Process Monitoring and Control
Signal Synthesis
:=w
description
The TLV5628C and TLV56281 are octal 8-bit voltage output digital-to-analog converters (DACs) with buffered
reference inputs (high impedance). The DACs produce an output voltage that ranges between either one or two
times the reference voltages and GND, and the DACs are monotonic. The device is simple to use, running from
a single supply of 3 to 3.6 V. A power-on reset function is incorporated to ensure repeatable start-up conditions.
Digital control of the TLV5628C and TLV56281 is over a simple 3-wire serial bus that is CMOS compatible and
easily interfaced to all popular microprocessor and microcontroller devices. The 12-bit command word
comprises 8 bits of data, 3 DAC select bits and a range bit, the latter allowing selection between the times 1 or
times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be written
to the device, then all DAC outputs updated simultaneously through control of the LDAC terminal. The digital
. inputs feature Schmitt triggers for high noise immunity.
The 16-terminal small-outline D package allows digital control of analog functions in space-critical applications.
The TLV5628C Is characterized for operation from O°C to 70°C. The TLV56281 is characterized for operation
from -40°C to 85°C. The TLV5628C and TLV56281 do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
TA
PLASTICOIP
(0)
(N)
O·Ct070·C
TLV5628CD
TLV5628CN
-40·C to SS·C
TLV5628ID
TLV56281N
~1ExAs
Copyright © 1995. Texas Instruments Incorporated
INSTRUMENTS '
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-95
s:w
a:
D.
I-
(,)
::J
C
o
a:
D.
TLV5628C, TlV56281
OCTAL 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS1 08 - JANUARY 1995
functional block diagram
REF1
>-....--DACA
••
•
>-.....- -
DACD
>-......- -
DACE
REF2
••
•
>-.....- -
"'0
::0
o
C
c:
DATA - - - - - I
lOAD
Serial
Interface
lDAC
--"L___--1
(")
Power-On
Reset
Terminal Functions
-t
"'0
TERMINAL
NAME
::0
m
<
m
-
::e
NO.
DESCRIPTION
1/0
ClK
5
I
Serial-interface clock. data enters on the negative edge
DACA
2
DACA analog output
DACB
1
DACC
16
DACD
15
DACE
7
DACF
8
DACG
9
DACH
10
0
0
0
0
0
0
0
0
DATA
4
I
Serial-interface digital data input
GND
3
I
Ground return and reference terminal
LDAC
13
I
DAC-update latch control
LOAD
12
I
Serial-interface load control
REF1
14
I
Reference voltage input to DACA
REF2
11
I
Reference voltage input to DACB
6
I
Positive supply voltage
VDD
DACB analog output
DACC analog output
DACD analog output
DACE analog output
DACF analog output
DACG analog output
DACH analog output
~TEXAS
3-96
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DACH
TLV5628C, TLV56281
OCTAL 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS108 - JANUARY 1995
detailed description
The TlV5628 is implemented using eight resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in Table 2. One end of each resistor string is connected
to the GND terminal and the other end is fed from the output of the reference input buffer. Monotonicity is
maintained by use of the resistor strings. Unearity depends upon the matching ofthe resistor elements and upon
the performance of the output buffer. Because the inputs are buffered, the DACs always present a
high-impedance load to the reference sources. There are two input reference terminals; REF1 is used for DACA
through DACD and REF2 is used by DACE through DACH.
Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or
times 2 gain.
On powerup, the DACs are reset to CODE o.
Each output voltage is given by:
VO(DACAIBICIDIEIFIGIH) = REF x C~~E x (1 + RNG bit value)
where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial-control word.
data interface
With lOAD high, data is clocked into the DATA terminal on each falling edge of ClK. Once all data bits have
been clocked in, lOAD is pulsed low to transfer the data from the serial-input register to the selected DAC as
shown in Figure 1. If LDAC is low, the selected DAC output voltage is updated and LOAD goes low. If lDAC
is high during serial programming, the new value is stored within the device and can be transferred to the DAC
output at a later time by pulsing lDAC low as shown in Figure 2. Data is entered MSB first.
CLK
r.- tau(DATA-CLK)
1--\ k- tv(DATA.CLK)
-tI
tau(LOAD.CLK)
I
r'
D4~--~:---------
DATA
tau(CLK.LOAD) -+e-----'~
I
I I , tw(LOAD)
f/
I
DACUpdate
Figure 1. LOAD-Controlled Update (LDAC
=Low)
CLK
_________
D4~
DATA
------------------------------------~S\
LOAD
tl
IJ
LDAC
taU(LOAD-LD~C) r"'·+I1
,-"-If
tw(LDAC) ~
V
DACUpdate
Figure 2. LDAC-Controlled Update
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
W
:;:
w
a:
a..
b
:::»
c
oa:
a..
~
II
LOAD
;:
3-97
TLV5628C,TLV56281
OCT~L 8·BIT'DIGITAL·TO·ANALOG CONVERTERS
SLAS108 - JANUARY 1995
data interface (continued)
Table 1 lists the A1 and AO bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.
Table 1. Serial-Input Decode
A2
A1
AO
OACUPOATEO
0
0
0
DACA
0
0
0
1
DACB
1
0
DACC r
0
1
1
DACD'
1
0
0
DACE
1
0
1
DACF
1
1
0
DACG
1
1
1
DACH
Table 2. Ideal-Output Transfer
"tJ
:D
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
GND
1
~
•
•
•
•
•
•
•
•
•
•
·•
(1/256) x REF (l+RNG)
•
•
·•
0
0
0
C
0
0
0
1
1
1
1
1
1
1
(1271256) x REF (l+RNG)
o
c:
"tJ
:D
m
<
m
:::e
-
OUTPUT VOLTAGE
•
·
1
0
0
0
0
0
0
0
(128/256) x REF (l+RNG)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
(2551256) x REF (1 +RNG)
·
1
•
1
·
equivalent inputs and outputs
INPUT CIRCUIT
-
......-
OUTPUT CIRCUIT
-"'*--
VOO
VOO
Input from
Oecodec:lOAC
Reglstar String
Vref
Input
ToOAC
Resistor
String
__- -......---4t-- GNO
ISINK
60 !IA
Typical
.....- . - - - - GNO
~TEXA5
3-98
OAC
Voltage Output
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLV5628C, TLV56281
OCTAL 8-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS108 - JANUARY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (Voo - GND) ...................•............................................. 7 V
Digital input voltage range, VIO .........•............................... GND - 0.3 V to Voo + 0.3 V
Reference input voltage range .......................................... GND - 0.3 V to Voo + 0.3 V
Operating free-air temperature range, TA: TLV5628C .................................... O°C to 70°C
TLV56281 ................................... -40°C to 85°C
Storage temperature range, Tstg .................................................. -50°C to 150°C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds ....... . . . . . . . . . . . . . . . . . . . . . . .. 230°C
t Stresses beyond those listed under"absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Supply voltage, VDD
High-level digital input voltage, VIH
MIN
NOM
MAX
UNIT
2.7
3.3
5.25
V
0.8
V
V
0.8VDD
low-level digital input voltage, Vil
Reference voltage, Vref [AIBICIDIEIFiGIH), Xl gain
VDo-O.5
V
load resistance, Rl
10
kO
Setup time, data input, tsu(DATA-ClK) (see Figures 1 and 2)
50
ns
Valid time, data input valid after ClK.!., tv(DATA-ClK) (see Figures 1 and 2)
50
ns
Setup time, ClK eleventh falling edge to lOAD, tsU(ClK-lOAD) (see Figure 1)
50
ns
Setup time, LOADi to ClK.!., tsu(lOAD-ClK) (see Figure 1)
50
ns
Pulse duration, lOAD, tw(lOAD) (see Figure 1)
250
ns
Pulse duration, lDAC, lw(lDAC) (see Figure 2)
250
ns
0
ns
Setup time, lOADi to lDAC.!., tsu(lOAD-lDAC) (see Figure 2)
ClK frequency
Operating free-air temperature, TA
1
I TlV5628C
I TlV56281
MHz
0
70
·C
-40
85
·C
w
a.
a:
b
::l
C
o
a:
a.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3:
w
:;
3-99
TLV5628C,TLV56281
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108-JANUARY 1995
electrical characteristics over recommended operating free-air temperature range,
Voo = 3 V to 3.6 V, Vref = 2 V, x 1 gain output ra.,ge (unless otherwise, noted)
IIH
High-level digital input current
PARAMETER
VI-VDD
MAX
±10
IlL
Low-level digital input current
VI-OV
±10
IO(sink)
Output sink current
IO(source)
Output source current
Ci
TEST CONDITIONS
Each DAC output
VDD = 3.3 V
Reference input current
VDD=3.3V. Vref= 1.5 V
Vref=1.25V. x 2 gain (see Note 1)
Linearity error (end point corrected)
Differential-linearity error
EZS
Zero-scale error
Zero-scale error temperature coefficient
"'tJ
::IJ
Full-scale error
o
C
c::
o-I
"'tJ
::IJ
m
<
m
-
~
Full-scale error tempereture coefficient
PSRR
Power-supply sensitivity
4
Vref = 1.25 V. x 2 gain (see Note 2)
Vref= 1.25 V. x2 gain (see Note 3)
pA.
pF
15
Supply current
pA
rnA
15
Iref
EL
UNIT
pA
1
I Input capacitance
I Reference input capacitance
ED
TYP
20
IDD
EFS
MIN
0
rnA
±10
pA
±1
LSB
±0.9
LSB
30
mV
p.VloC
Vref = 1.25 V. x 2 gain (see Note 4)
Vref = 1.25 V. x 2 gain (see Note 5)
10
Vref = 1.25 V. x 2 gain (see Note 6)
See Notes 7 and 8
±25
p.V/oC
0.5
mVN
±60
mV
NOTES: 1. l{1tegral nonlinearity (INL) is the maximum deviation of the output from the line between zero-scele and full scale (excluding the effects
of zero code and full-scale errors).
.
2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input Code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(Tmax) - ZSE(Tmin)]Nref x 106/(Tmax - Tmin).
5. Full-scale error is the deviation from the ideal full-scale output (Vref-1 LSB) with an output load of 10 kO.
6. Full-scale temperature coefficient is given by: FSETC = [FSE(Tmaxl- FSE (T min)]IVref x 106/(Tmax - Tmin).
7. Zerli-scale error rejection ratio (ZSE-RR) is measured by varying the VDD voltage from 4.5 V to 5.5 V dc and measuring the proportion
of this signal imposed on the zero-code output voltage.
8. Full-scale error rejection ratio (FSE-RR) is measured by varing the VDD from 3.0 V to 3.6 V dc and measuring the proportion ofthis
signal imposed on the full-scale output voltage.
operating characteristics over recomm~nded operating free-air temperature range,
Voo 3 V to 3.6 V, Vref 2 V, x 1 gain output range (unless otherwise noted)'
=
=
TEST CONDITIONS
Output slew rate
CL -100 pF. RL-l01
W
DACH
CC
a.
NOTE A: Resistor R ~ 10 kO
~
Figure 4. Output Buffering Schemes
o
::J
C
o
CC
a.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-101
3-102
TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
1993- REVISED JUNE 1995
• Single S-V Power Supply
OWB PACKAGE
(TOP VIEW)
• Sample Rates (Fsl up to 48 kHz
• is-Bit Resolution
• Pulse-Wldth-Modulation (PWM) Output
INIT
TEST
An
SHIFT
LATCH
256FSO
TEST
DGND
TEST
BCK
DATA
LRCK
MUTEL
MUTER
• Deemphasis Filter for Sample Rates of
32,37.8,44.1, and 48 kHz
• Mute With Zero-Data-Detect Flags
• Digital Attenuation to -60 dB
• Total Harmonic Distortion of 0.004%
Maximum
• Total-Channel Dynamic Range of 96 dB
Minimum
• Serial-Port Interface
• Differential Architecture
• CMOS Technology
1
4
5
6
7
8
9
10
11
12
13
14
DVDD
L1
AVDDL
L2
24 AGNDL
23 XGND
22 XIN
21 XOUT
20 XVDD
19 AGNDR
18 R2
17 AVDDR
16 R1
15 DVDD
• 2s-Complement Data Format
description
The TMS57014A is a stereo, oversampled sigma-delta, digital-to-analog converter (DAC) designed for use in
systems such as compact disks, digital audio tapes, multimedia, and video cassette recorders. The device
provides high-resolution signal conversion. This device consists of two identical synchronous conversion paths
for left and right audio channels. Other overhead functions provide on-chip timing and control.
Additional features include muting, attenuation, deemphasis, and zero-data detection. Control words (16-bit)
from a host controller or processor implement these functions.
The TMS57014A is characterized for operation from O°C to 70°C.
AVAILABLE OPTIONt
PACKAGE
TA
SMALL OUTLINE
(DWB)
O·C to 70·C
TMS57014ADWBLE
t Available on tape and reel (LE) only.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields;
however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these
high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in
conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC
or ground.
~I
TEXAS
NSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright © 1995, Texas Instruments Incorporated
3-103
TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER .
SLAS077C - SEPTEMBER 1993- REVISED. JUNE 1995
functional block diagram
lNi'i'
XIN
XOUT 268FSO
ATT
SHIFT
LA'i'CH
tr1 L1
25 L2
Interpolation
Filter
Zero-Data
DATA 11
BCK 10
LRCK 12
Serial
Detect
Data
Interface I--~""'H
Zero-Data
Right Channal
Detect
Deamphasls
Interpolation
Filter
Filter
~1EXAS
3-104
INSTRUMENTS
POST OFFICE BOX 666303 • DAlLAS, TEXAS 76266
rDDAcAC;-1----1!~ R1
Modulator 1---1>.... R2
TMS57014A
DUAL AUDIO DIGITAL·TO·ANALOG CONVERTER
SLAS077C - SEPTEMBER 1993 - REVISED JUNE 1995
Terminal Functions
TERMINAL
NAME
NO.
DESCRIPTION
1/0
3
I
Serial control data. ATT is a 16-bit word configured as LSB first (see Tables 2, 3, and 4).
AVDDL
26
I
Analog power supply (left channel)
AVDDR
AGNDL
17
I
Analog power supply (right channel)
24
I
Analog ground (left channel)
AGNDR
19
I
Analog ground (right channel)
BCK
10
I
Bit clock input. The shift clock signal clocks serial audio data into the device.
DATA
11
I
Audio data input. DATA can be configured as 16 or 18 bits with MSB or LSB first. DATA is 2s complement.
DVDD
DGND
15,28
I
Digital supply
8
I
Digital ground
1
I
Reset. When INIT is brought low, the device is reset. The device is activated on the rising edge of INIT. The LRCK
signal must be applied to the device for a reset to occur.
ATT
INIT
LATCH
5
I
Serial-control data latch. Control data loads into the internal registers when LATCH is brought low.
LRCK
12
I
Leftlright clock. LRCK signifies whether the serial data is associated wHh the left-channel DAC (when high) or the
right-channel DAC (when low).
MUTEL
13
0
Left-channel mute flag active. When the left channel is mute or the data through the channel remains at zero for the
system-register selected time, MUTEL is brought low.
MUTER
14
0
Right-channel mute flag active. When the right channel is mute or the data through the channel remains at zero for
the system-register selected time, MUTER is brought low.
Ll
27
Left PWM output 1
L2
25
Rl
16
R2
18
0
0
0
0
SHIFT
4
I
Shift clock. SHIFT clocks the control data into the internal registers.
TEST
Left PWM output 2
Right PWM output 1
Right PWM output 2
2,7,9
I
All TEST inputs should be tied low.
XIN
22
I
Master clock in. XIN derives all the key logic signals of the device. XIN runs at 512Fs, where Fs is the sample rate.
XOUT
21
0
Master clock out
XVDD
XGND
20
I
Power supply for clock section
23
I
Ground for clock section
6
0
System clock out. 256FSO reflects the master clock input divided by 2. The rate is 256Fs, where Fs is the sample
rate.
256FSO
detailed description
The TMS57014A incorporates an interpolation FIR filter and oversampled modulator. The pulse-widthmodulation (PWM) digital output feeds into an external low-pass filter to recover the analog audio signal.
Two control registers configure the device, the attenuation register controls the attenuation range and the
system register controls additional functions (see register set section).
resetl initialization
When INIT is brought low, an internal reset signal becomes active approximately 120 cycles of the sampling
frequency (Fs) after the failing edge of INIT. Under this condition, ail internal circuits are initialized and the PWM
output is held at zero data (50% duty cycle). When INIT is brought high, the internal reset signal goes inactive
for a maximum of five LRCK periods after the riSing edge of INIT. At this pOint, internal clocks are synchronous
with LRCK and the PWM output is valid (see Figure 1). The LRCK signal must be applied for proper initialization.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-105
TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077C - SEPTEMBER 1993 - REVISED JUNE 1995
reset/initialization (continued)
I+- 120 Cycles of Fs -.I
J4-- 5 periods max-----.l
I ____________~I____________~I
I
INIT----~....
r-
I
Internal
I
Reset
'--------------------------~I
LRCK
Figure 1. Reset Timing Relationships
timing and control
The timing and control circuit generates and distributes necessary clocks throughout this design. XIN is the
external master clock input. The sample rate of the data paths is set as LRCK = XIN/512. With a fixed
oversampling ratio of 32x and each PWM output value requiring 16 XIN cycles, the effect of changing XIN is
shown in Table 1.
The DAC can be operated at any conversion rate between 48 kHz and 32 kHz by choosing the appropriate
master-clock frequency. Some of the functions of the converter, such as the deemphasis filter, operate only at
the frequencies in Table 1.
Table 1. Master Clock to Sample Rate Comparison
XIN
(MHz)
256FSO
(MHz)
LRCK
24.5760
12.2880
48.0
22.5792
11.2896
44.1
19.3536
9.6768
37.8
16.3840
8.1920
32.0
(kHz)
. digital audio data interface
The conversion cycle is synchronized to the rising edge of LRCK, and the data must meet the setup
requirements specified in the timing requirements table. The input data is 16 or 18 bits with the MSB or LSB first
as selected in the system register. The BCK frequency must be equal to or greater than 32 Fs for 16-bit data
or 36 Fs for 18-bit data where Fs is the sample rate. Figure 2 illustrates the input timing.
BCK
DATA
(16-blt)
LRCK
Figure 2. Audio-Data Input Timing
~1EXAS
3-106
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077C - SEPTEMBER 1993 - REVISED JUNE 1995
serial-control Interface
This device uses the most-significant-bit-first format. Therefore, for a 16-bit word, 015 is the most significant
bit and 00 is the least significant bit. Unless otherwise specified, all values are in 2s-complement format.
serial-control-data Input
The 16-bit control-data input implements the device-control functions. The TMS57014A has two registers for
this data: the system register and the attenuation register. The system register contains most of the system
configuration information, and the attenuation register controls audio output level, deemphasis, and mute.
Figure 3 illustrates the input timing for ATT, SHIFT, and LATCH. The data loads internally on the falling edge
of LATCH. The shift clock should be high for the LATCH setup time before LATCH goes low.
SHIFT
AIT ____~I~o~I~1~1~2~1~3~1_4~1~5~1~6~1_7~1~8~9~1_1_0.1_11~1_12~1_13_1~1_4~1~1~5~1
LSB
____
MSB
Figure 3. Control-Data-Input Timing
mute
When mute is activated, the output PWM becomes zero data (50% duty cycle). The two mute flags, MUTEL and
MUTER, are independently set low based on the data in the respective channel being zero. This function
becomes active under the following conditions:
1. When the zero-data detector detects that the input data has been zero for 2500 cycles of Fs or 12500
cycles of Fs (as selected in the control registers), output is 50% duty cycle.
2. When the MUTE register value is set high by means of the serial-control data.
3. When INIT is active (low), output is 50% duty cycle.
zero-data detect
After the input data remains zero for 2500 or 12500 cycles of Fs as set by the system register (04, 05), the
channel-mute flag becomes active. Zero-data detection is available for both channels independently, so the two
outputs (MUTER and MUTEL) indicate that zero data has been detected on the respective channel. The
zero-detect register value in the serial-control data selects the detection period. The mute flag returns high
immediately when nonzero input data is received.
deemphasis filter
Four sets of deemphasis-filter coefficients support four sampling rates (Fs): 32,37.8,44.1, and 48 kHz. Internal
register values select the filter coefficients. The internal register values enable or disable the filter. Figure 4
illustrates the deemphasis characteristics.
Many audio sources have been recorded with preemphasis characteristics that are the inverse of the
deemphasis characteristics shown in Figure 4. This device provides reconstruction of the original frequency
response.
~ThxAs
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265
3-107
TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077C - SEPTEMBER 1993 - REVISED JUNE 1995
deemphasls filter (continued)
10
III
'tI
I
~
Ol-----..,...~
!
-10
Deemphasls
3.18
(50 jJS)
10.6
(15 jJS)
Frequency - kHz
Figure 4. Deemphasis Characteristics
digital attenuation
A vaiue seiected in the internal attenuation register determines the attenuation of the digital-audio-data input.
The attenuation value is 11 bits long with a valid range of hex values from 400h to OOOh. A data value of 001 h
corresponds to an attenuation value of -60 dB and a data value of 400h corresponds to 0 dB. The attenuation
function is nonlinear (see equation 1). Figure 5 demonstrates the attenuation function in dB. The default
attenuation value is 400h.
Attenuation = 20 log (attenuation data)
1024
0
-10
III
'tI
(1 )
- -- -.......
~ ....
~I'\
-20
\
I
c
i
~
-30
:::I
-40
\
-50
-60
1024 896
768
640
512
364
256
128
0
Attenuation Data (decimal values)
Figure 5. Digital Attenuation Characteristics
~TEXAS
3-108
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TMS57014A
DUAL AUDIO DIGITAL·TO-ANALOG CONVERTER
SLAsonc - SEPTEMBER 1993 - REVISED JUNE 1995
register set
Table 2 contains the register-set selection. Tables 3 and 4 list the bit functions.
Table 2. Reglster-Set Selection
BITS
15
0
DESCRIPTION
14
0
1
Attenuation register
System register
0
Invalid condition t
1
x
..
t Bit 15 should always be set to 0 when writing
data for proper operation.
Table 3. Attenuation-Register Bit Functions
BITS
FUNCTION
13
12
11
10-0
0
0
-
1
-
-
0
-
Bit 11 must be low
0
Digital attenuation, mute
1
Digital attenuation, -60.2 dB
1
-
-
-
Deernphasis off
Deemphasis on
Channel mute off
Channel mute on
-
200
Digital attenuation, -6.02 dB
-
201
Digital attenuation, -6.00 dB
-
3FF
Digital attenuation, -0.01 dB
400
Digital attenuation, 0.00 dB
2
Digital attenuation, -54.2 dB
3
Digital attenuation, -50.7 dB
...
lFF
Digital attenuation, -6.04 dB
...
default 0400h
NOTE: The attenuation values shown are typical values. Refer to the digital
attenuation section for a description of the attenuation function.
~1ExAs
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
3-109
TMS57014A
'. DUAL AUDIO DIGITAL·TO·ANALOG CONVERTER
SLAS077C - SEPTEMBER 1993 - REVISED JUNE 1995
Table 4. System-Register Bit Functions
BITS
13
12
0
-
1
-
11-6
-
0
1
-
-
-
-
5
4
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
-
0
-
0
1
-
Default = OOOOh
-
FUNCTION
3-2
1
0
-
-
-
MSB first, audio data
-
-
LSB first, audio data
-
-
16-bit, audio data
.-
-
0
1
2
3
-
0
1
-
-
16-bit, audio data
-
Bits 11-6 must be low
Zero data detect period (2500 cycles of Fs)
Zero data detect period (12500 cycles of Fs)
Bit 4 must be low
Deemphasis -44.1 kHz
Deemphasis -48.0 kHz
Deemphasis -37.8 kHz
Deemphasis -32.0 kHz
LRCK and PWM are not synchronized
LRCK and PWM synchronized
Bit 0 must be low
0
Interpolation filter
The interpolation filter used prior to the DAC increases the digital data rate from the LRCK speed to the
oversampled rate by interpolating with a ratio of 1:32. The oversampling modulator receives the output of this
filter with deemphasis as an option.
DAC modulator
The DAC is a 3rd-order modulator with 32 times oversampling. The DAC provides high-resolution, low-noise
performance using a 15-value PWM output as shown in Figure 6.
,
Noise Excluded by Low-Pass Filter
Quantization Noise With Noise Shaping
I
Audio
Signal
Iz
o
~
o
__
~.c~+-
fB
0.1
Quantization Noise
Without Noise______
Shaping
________+-________
________
~
0.2
0.3
~
0.4
~
0.5
Normalized Analog-Output Frequency (fofFsn
tfo is the output frequency at the low-pass filter output (Va) shown in Figure 10.
Figure 6. Oversampllng Noise Power With and Without Noise Shaping
~TEXAS' .'
3-110
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS, TEXAS 75265
TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAsonc - SEPTEMBER 1993 - REVISED JUNE 1995
PWM output (L2-L 1 and R2-R1)
The L2- L1 and the R2-R1 output pairs are pulse-width-modulated (PWM) signals with the L2- L1 differential
pulse duration determining the left-channel analog voltage and the R2-R1 differential pulse duration
determining the right-channel analog voltage.
Each DAC left and right output consists of 15 levels of PWM and provides a differential signal as the input to
two external differential amplifiers configured as a low-pass filter to produce the left and right audio outputs (see
Figure 9).
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Analog supply voltage range, AVOOL, AVOOR (see Note 1) .......•......................• -0.3 V to 7 V
Digital supply voltage range, DVOO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 7 V
Clock supply voltage range, XVOO (see Note 3) ........................................ -0.3 V to 7 V
Output voltage range, VO:
L1, L2 ..........•............................. -0.3 V to AVOOL + 0.3 V
R1, R2 ...•.................................. -0.3 V to AVOOR + 0.3 V
Input voltage range, VI .......••.•.....•.....................•..•........... -0.3 V to DVOO + 0.3 V
Operating free-air temperature range, TA •...............................•............... O°C to 70°C
Case temperature for 10 seconds, TC .....................•.................................. 260°C
Storage temperature range, Tstg .................................................... -55°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings' may cause pennanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values for maximum ratings are with respect to AGNOL and AGNOR respectively.
2. Voltage values for maximum ratings are with respect to'DGNO.
3. Voltage values for maximum ratings are with respect to XGNO.
recommended operating conditions (see Note 4)
NOM
MAX
UNIT
5
5.25
V
Digital supply voltage. OVOO
4.75
4.75 '
MIN
5
5.25
V
Clock supply voltage. XVOO
4.75
5
5.25
V
Analog supply voltage. AVOOL. AVOOR
High-level input voltage. VIH
Low-level input voltage. VIL
XIN
0.9VOO
All other digital inputs
V
0.76 VOO
XIN
0.1 VOO
All other digital inputs
0.24 VOO
Load resistance at PWM. RL
10
Master clock frequency at XI N
Operating free-air temperature. TA
V
kQ
16.3
24.6
MHz
0
70
·C
NOTE 4: OVOO. AVOOL. XVOO and AVOOR tied together represents VOO.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 665303 • DAU.AS. TEXAS 75265
3-111
TMS57014A
DUAL AUDIO DIGITAL·T()'ANALOG CONVERTER
SLAS077C - SEPTEMBER 1993 - REVISED JUNE 1995
electrical characteristics over recommended operating free-air· temperature range (unle$s
otherwise noted)
.
digital Interface, AVOD
=DVoo =5 V ± 5% (see Note 4)
256FSO
High-level output voltage
VOH
TYpt
MIN
TEST CONDITIONS
PARAMETER
·10--0.4mA
VOO-O.5
Ll,l2, Rl, R2
10=-12mA
VOO-0.5
XOUT
10--1.2mA
VOO-0.5
MUTEL, MUTER
10=-1 mA
256FSO
Ll,l2, Rl, R2
10= 0.4mA
10- 12'mA
XOUT
10= 1.2mA
MAX
V
VOO-0.5
..
0.4
0.5
VOL
Low-level output voltage
IIH
High-level input current, any digital input
±1
±5
IlL
Low-level input current, any digital input
±1
±5
. MUTEL, MUTER
UNIT
0.5
V
0.4
10-1 mA
IlA
IlA
Ci
Input capacitance
5
pF
Co
Output capacitance
5
pF
t All typical values are at TA = 25°C.
NOTE 4: OVOO, AVOOL, XVOO and AVOOR tied together represents VOO.
supplies, AVoo
=DVoo =5 V ± 5%, no load
PARAMETER
MIN
TEST CONDITIONS
Analog power supply current
TYpt
MAX
15
AVOOL and AVOOR are shorted together
mA
15
Oigital power supply current
Total device supply current over operating temperature range
Power dissipation
UNIT
mA
60
mA
350
mW
t All typical values are lit TA = 25°C.
=
=
DACmodulator, AVOO DVOO 5 V± 5%, sample rate (Fa)
TA 25°C, bandwidth Is 20 Hz to 20 kHz
=
PARAMETER
=44.1 kHz, full-scale Input sine wave at 1 kHz,
TYpt
MIN
TEST CONDITIONS
MAX
18
Resolution
See Note 5
Signal-to-noise ratio
A-weighted,
20 Hz to 20 kHz,
See Figure 10, Table 5, and Note 5
Total harmonic distortion
20 Hz to 20 kHz, See Note 5
Oeemphasis not selected
UNIT
bits
100
96
0.003%
dB
0.004%
t All typical values are at TA - 25°C.
NOTE 5: These specifications are measured at the output (VO) of the low-pass filter shown in Figure 9.
filter characteristics, AVoo
=DVoo =5 V± 5%, deemphasls disabled
PARAMETER
Pass-band ripple
Stop-band attenuation
TEST CONDITIONS
Sample rate (Fs) - 48 kHz,
See Note 5
Pass band (-3 dB) (OAC)
Stopband
TYPt
See Note 5
NOTE 5: These specifications are measured at the output (VO) of the lOW-pass filter shown in Figure 7.
~TEXAS'
INSTRUMENTS
POST OFFICE BOX e55303 • DALLAS, TEXAS 75265
UNIT
dB
0.46 Fs
kHz
dB
kHz
0.54 Fs
29/Fs
t All typical values are at TA = 25°C.
MAX
0.002
75
0
Group delay
3-112
MIN
-0.002
s
TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077C - SEPTEMBER 1993 - REVISED JUNE 1995
timing requirements (see Figures 8 and 9 and Note 6)
MIN
twl
Pulse duration, BCK
tsul
MAX
UNIT
160
ns
Setup time, DATA before BCKi
20
ns
thl
Hold time, DATA after BCKi
20
ns
tsu2
Setup time, LRCK before BCKi
50
ns
th2
Hold time, LRCK after BCKi
50
ns
tw2
Pulse duration, SHIFT
100
ns
tsu3
Setup time, An before SHIFTi
20
ns
th3
Hold time, An after SHIFTi
20
ns
tw3
Pulse duration, LATCH
100
ns
tsu4
Setup time, LATCH before SHIFTi
100
ns
th4
Hold time, LATCH after SHIFTi
tw 2+20
ns
..
NOTE 6: All timing measurements were taken at the VDoI2 voltage level.
~TEXAS
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3-113
TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAsonc - SEPTEMBER 1993 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
22kO
4700pF
15V
L2 (R2)
-'VV''-'VV\'--''
L--_ _ _ _
L1 (R1) - ' V V ' ' - ' V V \ ' - - ' '
10kC
-----I-=----';~1 ~~~
-15V
S.6kO
AGNOL (AGNOR)
AGNOL (AGNOR)
100pF
22kO
AGNOL (AGNOR)
Figure 7. Analog Low-Pass Filter Recommended for Measuring the
Dynamic Specifications olthe TMS57014A
BCK
J
~~~
I.- Iw1 --tI
I
\
OMA __________
_-.J,,..--.. ,. . . .
Isu1 -*~----t.t.oIt-- Ih1
,,..--.. .,. . .
_101
---I
I
~~~
I---lh2 ----tI
1
,
I
I
r
~X,..-----------.....*,..~----~---~-Io*,..-~-O~~------~~
'k.\.,._____
LRCK
Figure 8. Audio-Data Serial Timing
l.--I
_Ie
I
./
I
r---tw2~1w21
I
I
SHIFT - {
i
I
ATT
~
Isu3
f
Ih3
\'-----~1
i
::J<~14:---------"* 15
I
I
:
\'-----~rI
I
>e:::::::::J<"':'o----'-:-
I
LMCH---------------~-TI--~}
I
{
I
I
I
I
I
r--- lh4 -r-Iw3 ~-'iI'r--- lsu4 ~
Figure 9. Control-Data Serial Timing
~/~·
~1ExAs
I
3-114
.
NSTRUMENTS
POST OFACE BOX 655303 • DALlAS. TEXAS 75265
TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077C - SEPTEMBER 1993 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Table 5. A-Weighted Data
FREQUENCY
A WEIGHTING (dB)
FREQUENCY
A WEIGHTING (dB)
-0.1 ±1
25
-44.6±2
SOO
31.5
-39.2±2
1000
O±O
40
-34.5±2
1250
0.6±1
50
63
-30.2±2
-26.1 ±2
1600
2000
1.0±1
1.2±1
1.2±1
SO
-22.3±2
2500
100
-19.1 ±1
3150
1.2 ±1
125
160
-16.1 ±1
4000
200
-13.2±1
-10.S±1
5000
6300
1.0±1
0.5±1
-0.1 ±1
250
-S.6±1
SOOO
-1.1 ±1
315
-6.5±1
10000
-2.4±1
400
500
630
-4.S±1
-3.2±1
12500
16000
-4.2±2
-6.5±2
-1.9±1
10
0
ED
"a
,I
-10
0
i:s
"
V
I
c
-20
c
!«
-30
-40
1/
/
-50
20
V
100
1k
10 k 20 k
Signal Frequency - Hz
Figure 10. A-Weighted Function
-!11 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-115
TMS57014A
DUAL AUDIO DIGITAL-T()"ANALOG CONVERTER
SLAS077C - SEPTEMBER 1993- REVISED JUNE 1995
APPLICATION INFORMATION
circuit and layout considerations
The designer should follow these guidelines for the best device performance.
•
Separate digital and analog ground planes should be used. All digital device functions should be over the
digital ground plane, and all analog device functions should be over the analog ground plane. The ground
planes should be connected at only one point to the direct power supply, and this is usually at the connector
edge of the board.
•
A single crystal-controlled clock should synchronously generate all digital signals
•
All power supply lines should include a 0.1-~F and a 1-~ capacitor. If clock noise is excessive, a toroidal
inductance of 10 ~H should be placed in series with XVoo before connecting to DVoo.
•
The digital input control signals should be buffered if they are generated off the card.
•
Clock jitter should be minimized, and precautions taken to prevent clock overshoot. This minimizes any
high-frequency coupling to the analog output.
PCB footprint
Figure 11 shows the printed-circuit-board (PCB) land pattern for the TMS57014A small-outline package.
~
fL
ok
Wl1 r--t-
f
+
L2
L2
fL
ok
it
f
p
DOD
ggO
DDr
ggl
L1
NOTE A: All linear dimensions are in millimeters.
Figure 11. Land Pattern for PCB Layout
~TEXAS
3-116
INSTRUMENTS
POST OFFICE BOX 665303 • DALlAS. TEXAS 75265
S
AD7524M
Advanced LinCMOSTM 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
SGLS028A - SEPTEMBER 1989 - REVISED MARCH 1995
• Advanced LinCMOSTM Silicon-Gate
Technology
• Easily interfaced to Microprocessors
• On-Chip Data Latches
• Monotonicity Over Entire AID Conversion
Range
• Segmented High-Order Bits Ensure
Low-Glitch Output
• Designed to Be interchangeable With
Analog Devices AD7524, PMI PM-7524, and
Micro Power Systems MP7524
• Fast Control Signaling for Digital Signal
Processor Applications Including Interface
With SMJ320
J PACKAGE
(TOP VIEW)
OUTl
OUT2
GND
DB?
DB6
DBS
DB4
DB3
RFB
REF
3
VDD
WR
4
CS
DBD
DBl
DB2
11
FKPACKAGE
(TOP VIEW)
C\I~
~~u
KEY PERFORMANCE SPECIFICATIONS
Resolution
8 Bits
Unearity error
1/2 LSB Max
Power dissipation at VDD = 5 V
5mWMax
Settling time
100 ns Max
Propagation delay
lEtt
00 za:: a::
GND
DB?
NC
DB6
DBS
80 ns Max
4
3 2
1 2019
18
5
6
17
7
15
8
14
9 1011 1213
description
16
VDD
WR
NC
CS
DBD
~ ~ ~~ ~
The AD7524M is an Advanced LinCMOSTM 8-bit
digital-to-analog converter (DAC) designed for
easy interface to most popular microprocessors.
NC-No intemarconnection
The AD7524M is an 8-bit multiplying DAC with input latches and with a load cycle similar to the write cycle of
a random access memory. Segmenting the high-order bits minimizes glitches during changes in the
most-significant bits, which produce the highest glitch impulse. The AD7524M provides accuracy to 1/2 LSB
without the need for thin-film resistors or laser trimming, while dissipating less than 5 mW typically.
Featuring operation from a 5-V to 15-V single supply, the AD7524M interfaces easily to most microprocessor
buses or output ports. Excellent multiplying (2 or 4 quadrant) makes the AD7524M an ideal choice for many
microprocessor-controlled gain-setting and signal-control applications.
The AD7524M is characterized for operation from -55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
CERAMIC CHIP
CARRIER
(FK)
TA
-55°C to 125°C
AD7524MFK
CERAMIC DIP
(J)
AD7524MJ
Advanced UnCMOS is a trademark of Texas Instruments Incorporated.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-117
AD7524M
Advanced LlnCMOSTM 8-81T MULTIPLYING
DIGitAL-TO-ANALOG CONVERTER
SGLS028A- SEPTEMBER 1989 -' REVISED MARCH 1995
functional block diagram
R
R
R
2R
.--_--'l~a RFB
R
L...-+-r___-t--;-_+_--+-...,....~+-_+_--
OUT1
l...-:-_......-:-_-+--:--_ _....,.--+___--=.2 OUT2
4
DB7
(MSB)
S
a
11
DBa
DBS
DBO
(LSB)
\
I
v
Data Inputa
operating sequence
11+"- - -
_ _ _ _""'\ 1
~
tsu(CS)
-------1.1..:..e----').1 th(CS)
1
l~X~____________~1~.
~ tw(WR)
..I
I
1
WR----------1~~~~____________~~~------------
~
tau (D)
1..
.1
--t!r--...;..--....."..
DBO-DB7 _ _ _ _ _ _ _ _ _
~TEXAS
3-118
INSTRUMENTS
. POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
th(D)
I ___________
AD7524M
Advanced LinCMOSTM 8-81T MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
SGLS028A-SEPTEMBER 1989- REVISED MARCH 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Voo ........•................................................ -0.3 V to 17 V
Voltage betweeh RFB and GND ............................................................ ±25 V
Digital input voltage range, VI ................................................. -0.3 V to Voo+0.3 V
Reference voltage range, Vref ............................................................. ±25 V
Peak digital input current, II .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 ~
Operating free-air temperature range, TA ................... . . . . . . . . . . . . . . . . . . . . . . .. -55°C to 125°C
Storage temperature range, Tstg ............•..................................... -65°C to 150°C
Case temperature for 60 seconas, Tc: FK package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ..................... 300°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
NOM
MAX
Voo= 15V
MIN NOM MAX
5
5.25
14.5
VOO=5V
MIN
4.75
Supply voltage, VDD
Reference voltage, Vref
High-level input voltage, VIH
2.4
Low-level input volage, VIL
15.5
40
V
V
V
13.5
0.8
CS setup time,leuccs)
15
±10
±10
UNIT
1.5
V
40
ns
0
0
ns
Data bus input setup time, tsuCD)
25
25
ns
Data bus input hold time, thCD)
10
10
ns
Pulse duration, WR low, IwCWR)
40
40
CS hold tlme,\hCCS)
Operating free-air temperature, TA
-55
125
-55
ns
125
·C
~TEXAS
INSTRUMENTS
POST OFFICE eox 656303 • OALLAS, TEXAS 75266
3-119
AD7524M"
Advanced LinCMOSTM 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG' CONVERTER
SGLS028A - SEPTEMBER 1989 - REVISED MARCH 1995
electrical characteristics over recommended operating free-air temperature range, Vref =10 V,
,OUT1 and OUT2 atGND (unless otherwise noted)
PARAMETER
High-level input current
VI = VDD
IlL
Low-level input current
VI=O
OUTl
Ipkg
OUT2
DBD-DBl at 0,
WR and CS atO V
DBD-DBl at VDD,
WRand CSatO
IDD
Supply current
Standby
Supply voltage sensitivity,
kSVS
Ll.VDD= 10%
Ll.gainlLl.VDD
Ci
Input capacitance, DBD-DBl,
WR,CS
Co
Output
capacitance
1
Full-range
-10
-10
25°C
-1
-1
Full-range
±400
±200
25°C
±50
±50
±400
±200
±50
±50
Full-range
25°C
2
2
Full-range
500
500
25°C
100
100
Full-range
0.16
0.002
25°C
0.001
0.02
DBD-DBl at 0, WR and CS at 0 V
DBD-DBl at VDD, WR and CS at 0 V
Reference input impedance
(REFtoGND)
MIN
120
120
30
30
5
20
Linearity error
Gain error
I Full range
See Note 1
I
Settling time (to 1/2 LSB)
See Note 2
Propagation delay from digital input to
90% of final analog output current
See Note 2
Feedthrough at OUTl or OUT2
Vref - ± 10 V (100 kHz sinewave),
WR and CS at 0, DBD-DBl at 0
Temperature coefficient of gain
TA = 25°C to tmin or t max
NOTES:
25°C
"
I Full range
I 25°C
MAX
oun
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pF
kn
=10 V,
UNIT
±0.2
±0.2
±1.4
±0.6
±1
±0.5
100
100
ns
80
80
ns
0.5
0.5
0.25
0.25
±0.004
±0.001
1. Gain error IS measured uSing the internal feedback resistor. Nominal Full Scale Range (FSR) - Vref - 1 LSB.
2.
load = 1000, Cext - 13 pF, WR at 0 V, CS at 0 V, DBD-DBl at 0 V to VDD or VDD to 0 V.
'~TEXAS
3-120
= 15V
MIN
J.IA
pF
30
VOO
mA
5
120
MAX
nA
pF
30
VCC=5V
TEST CONOITIONS
J.IA
%/%
operating characteristics over recommended operating free-air temperature range, Vref
OUT1 and OUT2 at GND (unless otherwise noted)
,
PARAMETER
J.IA
0.02
120
20
5
UNIT
0.04
5
VI=O
OUTl
OUT2
MAX
10
OUTl
OUT2
TYP
MIN
1
DBD-DBl at VIHmin or VILmax
DBD-DBl at 0 V or VDD
MAX
10
Vref = ±10 V
Quiescent
TYP
25°C
Vref= ±10V
Output leakage
current
MIN
Full-range
IIH
VOO=15V
VOO=5V
TEST CONOITIONS
%FSR
%FSR
%FSR
%FSR/oC
AD7524M
Advanced LinCMOSTM 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
SGLS028A- SEPTEMBER 1989 - REVISED MARCH 1995
PRINCIPLES OF OPERATION
The AD7524M is an 8-bit multiplying D/A converter consisting of an inverted R-2R ladder, analog switches, and
data input latches. Binary weighted currents are switched between the OUT1 and OUT2 bus lines, thus
maintaining a constant current in each ladder leg independent of the switch state. The high-order bits are
decoded and these decoded bits, through a modification in the R-2R ladder, control three equally weighted
current sources. Most applications only require the addition of an external operational amplifier and a voltage
reference.
The equivalent circuit for all digital inputs low is seen in Figure 1. With all digital inputs low, the entire reference
current, Iref, is switched to OUT2. The current source 1/256 represents the constant current flowing through the
termination resistor of the R-2R ladder, while the current source Ilkg represents leakage currents to the
substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all
digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2 and the on-state switch
capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown
in Figure 1. Analysis of the circuit for all digital inputs high is similar to Figure 1; however, in this case, iref would
be switched to OUT1 .
Interfacing the AD7524M D/A converter to a microprocessor is accomplished via the data bus and the CS and
WR control signals. When CS and WR are both low, the AD7524M analog output responds to the data activity
on the DBD-DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects
the analog output. When either the CS signal or WR signal goes high, the data on the DBD-DB7 inputs are
latched until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless
of the state of the WR signal.
The AD7524M is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant or 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and bipolar
operation are summarized in Tables 1 and 2, respectively.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-121
AD7524M
Advanced LlnCMOSTM 8-81T MULTIPLYING
DlGITAL·TO·ANALOG CONVERTER
SGLS028A- SEPTEMBER 1989 - REVISED MARCH 1995
PRINCIPLES OF OPERATION
ir-R----RFB
". ~.---i----f.-3·0-p-F---ouT1
REF
--
--1VV'v--!-----!
...
7 ! 11kg 7 !
-----1+------'-OUT2
1/256
T 120pF
Figure 1. AD7524M Equivalent Circuit With All Digital Inputs Low
Vref
VDD
....'" 1-
RB
(see NomA)
RFB
DBO-DB7
>-~t---Output
CS
WR
GND
Figure 2. Unipolar Operation (2-Quadrant Multiplication)
Vref
VDD
201<0
RA =21<0
(see Note A)
DBO-DB7
RB
201<0
>-2
VMA
AO-A15
~-----1-""
IO--------------i
~---<.--+---_t
Decode
Logic
AddressBu8
Figure 5. AD7524M-6800 Interface
-!llExAs
INSTRUMENTS
POST OFFICE SOX 655303 • DAUAS. TEXAS 75265
3-123
AD7524M
Advanced LinCMOSTM 8~SIT"MULTIPLYING
DIGITAL·TO·ANALOG CONVE~TER
SGLS028A- SEPTEMBER 1989 - REVISED MARCH 1995
microprocessor interfaces (continued)
,"
Address Bus"
A8"-A15
Decode
Logic
~
8-Blt
Latch
8051
CS
I
ALE
WR
AD7524M
WR
I
OUT2
DBO-DB7
4
r-ADO-AD7
Address/Data Bus
Figure 6. AD7524M-8051 Interface
~TEXAS "
3-124
INSTRUMENTs
POST OFACE BOX 655303 • DALLAS. TEXAS 75265
OUT1
I
~
4-1
c
en
'"0
J>
m
~
-
o
cc
-
....
CD
~
:::L
m
(')
CD
m
:::J
C-
O
o
:::J
<
CD
Ul
-o
:::J
4-2
TLC32040C, TLC320401, TLC32041 C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
N PACKAGE
(TOP VIEW)
• 14-Blt Dynamic Range ADC and DAC
• Variable ADC and DAC Sampling Rate Up
to 19,200 Samples per Second
• Switched-Capacitor Antlaliaslng Input Filter
and Output-Reconstruction Filter
• Serial Port for Direct Interface to TMS32011,
TMS320C17, TMS32020, and TMS320C25
Digital Signal Process
• Synchronous or Asynchronous ADC and
DAC Conversion Rate With Programmable
Incremental ADC and DAC Conversion
Timing Adjustments
• Serial Port Interface to SN74299
Serlal-to-Parallel Shift Register for Parallel
Interface to TMS32010, TMS320C15, or
Other Digital Processors
FSR
DR
MSTRCLK
AUX IN+
AUX INOUT+
OUT-
Voo
REF
DGTLGND
SHIFTCLK
EODX
OX
WORD/BYTE
FSX
• 600-Mil Wide N Package (CL to CLl
• 2s Complement Format
• CMOS Technology
9
11
VCC+
VCCANLGGND
ANLGGND
NU
NU
FNPACKAGE
(TOP VIEW)
Iffi => => =>
Icds
~I@a:zzz~
+
PART
NUMBER
DESCRIPTION
TLC32040
Analog interface circuit with intemal reference.
Also a plug-in replacement for TLC32041.
TLC32041
NU
NU
IN+
IN-
NU
RESET
EODR
Analog interface circuit without intemal
reference
description
The TLC32040 and TLC32041 are complete
analog-to-digital and digital-to-analog input!
output systems, each on a single monolithic
CMOS chip. This device integrates a bandpass
switched-capacitor antialiasing input filter, a
14-bit-resolution
AID
converter,
four
microprocessor-compatible serial port modes, a
14-bit-resolution CIA converter, and a low-pass
switched-capacitor output-reconstruction filter.
DR
MSTRCLK
Voo
REF
DGTLGND
4 3 2 1 28 2726 25
5
6
24
7
23
22
8
21
9
10
20
19
11
12 1314 15 16 17 18
INAUX IN+
AUX INOUT+
OUTVCC+
VCC-
I IX
UJ
xCl!;:~ZZZz
=> => Cl Cl
al
(!)(!)
Ci
~~
zz
a:
~
C(C(
NU - Nonusable; no extemal connection should be made to
these terminals.
AVAILABLE OPTIONS
PACKAGE
TA
O·Cto 70·C
PLASTIC CHIP
CARRIER
(FN)
PLASTIC DIP
(N)
TLC32040CFN
TLC32041 CFN
TLC32040CN
TLC32041CN
TLC32040IN
TLC32041IN
-40·C to 85·C
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
Copyright © 1995, Texas Instruments Incorporated
TLC32040C, TLC320401, TLC32041 C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E ~ SEPTEMBER 1987 - REVISED MAY 1995
description (continued)
The device offers numerous combinations of master clock input frequencies and conversion/sampling rates,
which can be changed via digital processor control.
Typical applications forthis integrated circuit include modems (7.2-,8-,9.6-, 14.4-, and 19.2-kHz sampling rate),
analog interface for digital signal processors (DSPs), speech recognition/storage systems, industrial process
control, biomedical instrumentation, acoustical signal processing, spectral analysis, data acquisition, and
instrumentation recorders. Four serial modes, which allow direct interface to the TMS32011, TMS320C17,
. TMS32020, and TMS320C25 digital signal processors, are provided. Also, when the transmit and receive
sections of the analog interface circuit (AIC) are operating synchronously, it can interface to two SN74299
serial-to-parallel shift registers. These serial-ta-parallel shift registers can then interface in parallel to the
TMS32010, TMS320C15, other digital Signal processors, or external FIFO circuitry. Output data pulses are
emitted to inform the processor that data transmission is complete or to allow the DSP to differentiate between
two transmitted bytes. A flexible control scheme is provided so that the functions of this integrated circuit can
be selected and adjusted coincidentally with signal processing via software control.
The antialiasing input filter comprises seventh-order and fourth-order CC-type (Chebyshev/elliptic transitional)
low-pass and high-pass filters, respectively and a fourth-order equalizer. The input filter is implemented in
switched-capacitor technology and is preceded by a continuous time filter to eliminate any possibility of aliasing
caused by sampled data filtering. When no filtering is desired, the entire composite filter can be switched out
of the signal path. A selectable, auxiliary, differential analog inputis provided for applications where morethan
one analog input is required.
The AID and D/A converters each have 14 bits of resolution. The AID and D/A architectures ensure no missing
codes and monotonic operation. An internal voltage reference is provided on the TLC32040 to ease the design
task and to provide complete control over the performance of this integrated circuit. The internal voltage
reference is brought out to a terminal and is available to the designer. Separate analog and digital voltage
supplies and grounds are provided to minimize noise and ensure a wide dynamic range. Also, the analog circuit
path contains only differential circuitry to keep noise to an absolute minimum. The only exception is the DAC
sample and hold, which utilizes pseudo-differential circuitry.
The output-reconstruction filter is a seventh-order CC-type (Chebyshev/elliptic transitional low-pass filter
followed by a fourth-order equalizer) and is implemented, in switched-capacitor technology. This filter is followed
by a continuous-time filter to eliminate images of the digitally encoded signal.
The TLC32040C and TLC32041 C are characterized for operation from O°C to 70°C, and the TLC320401 and
TLC32041I are characterized for operation from -40°C to 85°C.
~TEXAS
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS. TEXAS 75265
TLC32040C, TLC320401, TLC32041 C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
functional block diagram
Band-Pass Filter
Serial
Port
IN + --I...................
FSR
DR
IN - ~--tI........"
1"'--
AUX IN + --I...................
I
I
I
AUX IN - ~--tI........"
---------------------,
I
I
---,
Internal
Voltage
Reference
(TLC32040
only)
EODR
I
I
I
I
I
I
MSTRCLK
SHIFTCLK
WORD/BYTE
L _ _ _ _ _ .J
OX
Low-Pass Filter
FSX
OUT++J-----l
OUT-+J-----l
1I
EODX
Transmit Section
VCC+ VCC- ANLG
GND
DTGL
VDD
GND (DIGITAL)
Terminal Functions
TERMINAL
NAME
ANlGGND
NO.
110
17,18
DESCRIPTION
Analog ground return for all internal analog circuits. Not internally connected to DGTl GND.
AUX IN+
24
I
Noninverting auxiliary analog input state. This input can be switched into the bandpass filter and AID
converter path via software control. If the appropriate bit in the control register is a 1, the auxiliary inputs
replace the IN + and IN - inputs. lithe bit is a 0, the IN + and IN - inputs are used (see the AIC DX data word
format section).
AUXIN-
23
I
Inverting auxiliary analog input (see the above AUX IN + description)
DGTlGND
9
DR
5
0
DR is used to transmit the ADC output bits from the AIC to the TMS320 serial port. This transmission of bits
from the AIC to the TMS320 serial port is synchronized with the SHIFT ClK signal.
DX
12
I
DX is used to receive the DAC input bits and timing and control informatiol") from the TMS320. This serial
transmission from the TMS320 serial port to the AIC is synchronized with the SHIFT ClK signal.
EODR
3
0
End of data receive. See the WORD/BYTE description and the Serial Port liming diagrams. During the
word-mode timing, EODR is a low-going pulse that occurs immediately after the 16 bits of AID information
have been transmitted from the AICto the TMS320 serial port. EODR can be used to interrupt a
microprocessor upon completion of serial communications. Also, EODR can be used to strobe and enable
external serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus
communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing,
EODR goes low after the first byte has been transmitted from the AIC to the TMS320 serial port and is kept
low until the second byte has been transmitted. The TMS32011 or TMS320C17 can use this low-going
signal to differentiate between the two bytes as to which is first and which is second. EODR does not occur
after secondary communication.
Digital ground for all intemallogic circuits. Not internally connected to ANlG GND.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-5
TLC32040C, TLC320401, TLC32041C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
Terminal Functions (continued)
TERMINAL
NAME
NO.
1/0
DESCRIPTION
End of data transmn. See the WORDIBYTE description and the Serial Port Timing diagram. During the
word-mode timing, EODX is a low-golng pulse that occurs immediately after the 16 bits of D/A converter
and control or register information have been transmitted from the TMS320 serial port to the AIC. EODX
can be used to interrupt a microprocessor upon the completion of serial communications. Also, EODX can
be used to strobe and enable extemal serial-to-parallel shift registers, latches, or an external FIFO RAM,
and to facllHate parallel data-bus communications between the AIC and the serial-to-parallel shift registers.
During the byte-mode timing, EODX goes low after the first byte has been transmitted from the TMS320
serial port to the AIC and is kept low until the second byte has been transmitted. The TMS32011 or
TMS320C17 can use this low-going Signal to differentiate between the two bytes as to which is first and
which is second.
EODX
11
0
FSR
4
0
Frame sync receive. In the serial transmission modes, which are described in the WORD/BYTE description,
FSR is held low during bit transmission. When FSR goes low, the TMS320 serial port begins receiving bits
from the AIC via DR of the AIC. The most significant DR bit is present on DR before FSR goes low. (See
Serial Port Timing and Intemal Timing Configuration diagrams.) FSR does not occur after secondary
communication.
FSX
14
0
IN+
IN-
26
I
Noninverting input to analog input amplifier stage
25
I
Inverting input to analog input amplifier stage
MSTRCLK
6
I
Master clock. MSTR CLK Is used to derive ali the key logic signals of the AIC, such es the shift clock, the
switched-capacHor filter clocks, and the AID and D/A timing signals. The Intemal Timing Configuration
diagram shows how these key signals are derived. The frequencies of these key signals are synchronous
submultiples of the masterclockfrequencyto eliminate unwanted aliasing when the sampled analog signals
are transferred between the switched-capacHor filters and the AID and D/A converters (see the Internal
Timing Configuration).
OUT+
22
0
Noninverting output of analog output power amplifier. OUT + can drive transformer hybrids or
high-impedance loads directly in either a differential or a single-ended configuration.
OUT-
21
0
Inverting output of analog output power amplifier. OUT -Is functionally Identical with and complementery
to OUT +.
REF
8
110
Internal voltage reference for the TlC32040. For the TLC32040 and TLC32041 an external voltage
reference can be applied to this terminal.
RESET
2
I
Reset. A reset function is provided to initialize the TA, TA', TB, RA, RA', RB, and control registers. This reset
function initiates serial communications between the AIC and DSP. The reset function initializes ali AIC
registers including the control register. After a negative-going pulse on REm, the AIC registers are
initialized to provide an 8-kHz data conversion rate for a 5.184-MHz master clock input signal. The
conversion rate adjust registers, TN and RN, are reset to 1. The control register bits are reset as follows
(see AIC DX data word format section):
d7 = I, d6 = I, d5 = I, d4 - 0, d3 - 0, d2 _ 1
This initialization allows normal serial-port communication to occur between AIC and DSP.
SHIFTClK
10
0
Shift clock. SHIFT ClK is obtained by dividing the master clock signal frequency by four. SHIFT ClK Is used
to clock the serial data transfers of the AIC, described in the WORDtBYTE description below (see the Serial
Port Timing and Intarnal Timing Configuration diagrams).
Frame sync transmit. When FSX goes low, the TMS320 serial port begins transmitting bits to the AIC via
DX of the AIC. In ali serial transmission modes, which are described In the WORDtBYTE description,
Is held low during bit transmission (see the Serial Port Timing and Internal Timing Configuration diagrams).
m
VOD
7
VCC+
20
Digital supply voltage, 5 V ±5%
PosHive analog supply voHage, 5 V ±5%
VCC-
19
Negative analog supply voltage, -5 V ±5%
~TEXAS
INSTRUMENTS
POST OFRCE BOX 655303 • DALlAS. TEXAS 75265
TLC32040C, TLC320401, TLC32041 C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
Terminal Functions (continued)
TERMINAL
NAME
NO.
WORD~
13
1/0
DESCRIPTION
I
WORD/BYTE, in conjunction with a bit in the control register, is used to establish one of four serial modes.
These four serial modes are described below.
AIC transmit and receive sections are operated asynchronously.
The following description applies when the AIC Is configured to have asynchronous transmH and receive
sections. If the appropriate data bH in the control register is a 0 (see the AIC OX data word format section),
the transmH and receive sections are asynchronous.
L Serial port directly Interfaces with the serial port of the TMS32011 or TMS320C17 and
communicates in two 8-bit bytes. The operation sequence is as follows (see Serial Port Timing
diagrams).
1. FSX or FSR is brought low.
2. One 8-bit byte is transmitted or one 8-bit byte is received.
3. EODX or EODR is brought low.
4. FID< or FSR emits a positive frame-sync pulse that is four shift clock cycles wide.
5. One 8-bit byte is transmitted or one 8-bit byte is received.
6. EODX or EODR is brought high.
7. FSX or FSR is brought high.
H Serial port directly interfaces with the serial port of the TMS32020, TMS320C25, or TMS320C30
and communicates in one 16-bit word. The operation sequence is as follows (see Serial Port
Timing diagrams):
1. FID< or FSR is brought low.
2. One 16-b1t word is transmitted or one 16-bit word is received.
3. FSX or FSR is brought high.
4. EODX or EODR emits a low-going pulse.
AIC transmit and receive sections are operated synchronously.
If the appropriate data bit in the control register is a 1, the transmit and receive sections are configured to
be synchronous. In this case, the bandpass switched-capacitor filter and the AID conversion timing are
derived from the TX counter A, TX counter B, and TA, TI'{, and TB registers, rather than the RX counter A,
RX counter B, and RA, RI'{, and RB registers. In this case, the AICFSX and FSR timing are identical during
primary data communication; however, FSR is not asserted during secondary data communication since
there is no new AID conversion result. The synchronous operation sequences are as follows (see Serial
Port Timing diagrains).
L
Serial port directly interfaces with the serial port of the TMS32011 or TMS320C17 and
communicates in two 8-bit bytes. The operation sequence is as follows (see Serial Port Timing
diagrams):
1. FSX and FSR are brought low.
2. One 8-bit byte is transmitted and one 8-bit byte is received.
3. EODX and EODR are brought low.
4. FSX and "FSR emit positive frame-sync pulses that are four shift clock cycles wide
5. One 8-bit byte is transmitted and one 8-bit byte is received.
6. EODX and EODR are brought high.
7. FSX and FSR are brought high.
H Serial port directly interfaces with the serial port of the TMS32020, TMS320C25, or TMS320C30
and communicates in one 16-bit word. The operation sequence is as follows (see Serial Port
Timing diagrams): .
1. FSX and FSR are brought low.
2. One 16-bit word is transmitted and one 16-bit word is received.
3. FID< and FSR are brought high.
4. EODX or EODR emit low-going pulses.
Since the transmit and receive sections of the AIC are now synchronous, the AIC serial port with additional
NOR and AND gates will interface to two SN74299 serial-ta-parallel shift registers. InterfaCing the AIC to
the SN74299 shift register allows the AIC to interface to an external FIFO RAM and facilitates parallel data
bus communications between the AIC and the digital signal processor. The operation sequence is the same
as the above sequence (see Serial Port Timing diagrams).
-!I
TEXAS
INSTRUMENTS
POST OFFICE BOX 855303. OAlLAS. TEXAS 75265
4-7
TlC32040C, TLC320401, TLC32041 C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E- SEPTEMBER 1987"" REVISED MAY 1995
detailed description
analog input
Two sets of analog inputs are provided. Normally, the IN+ and IN- input set is used; however, the auxiliary input
set, AUX IN+ and AUX IN-, can be used if it second input is required. EaCh input set can.be operated in either
differential or single-ended modes, since sufficient common-mode range and rejection are provided. The gain
for the IN +, IN-, AUX IN+, and AUX IN-. inputs can be programmed to be either 1,2, or 4 (see Table 2). Either
input circuit can be selected via software control. It is important to note that a wide dynamic range is assured·
by the differential internal analog architecture and by the separate analog and digital voltage supplies and
grounds ..
AID bandpass filter, AID bandpass filter clocking, and AID conversion timing
The AID bandpass filter can be selected or bypassed via software control. The frequency response of this filter
is presented in the following pages. This response results when the switched-capacitor filter clock frequency
is 288 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter clock. When the
filter clock frequency is not 288 kHz, the filter transfer function is frequency scaled by the ratio of the actual clock
frequency to 288 kHz. The low-frequency roll-off of the high-pass section is 300 Hz.
The internal timing configuration and Ale ox data word format sections of this data sheet indicate the many
options for attaining a 288-kHz bandpass switched-capacitor filter clock. These sections indicate that the RX
counter A can be programmed to give a 288-kHz bandpass switched-capacitor filter clock for several master
clock input frequencies.
The AID conversion rate is then attained by frequency dividing the 288-kHz bandpass switched-capacitor filter
clock with the RX counter B. Thus, unwanted aliasing is prevented because the AID conversion rate is an integral
submultiple ofthe bandpass switched-capacitor filter sampling rate, and the two rates are synchronously locked.
AID converter performance specifications
Fundamental performance specifications for the AID converter circuitry are presented in the AID converter
operating characteristics section of this data sheet. The realization of the AID converter circuitry with
switched-capacitor techniques provides an inherent sample-and-hold.
analog output
The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier outputs
are brought out of this integrated circuit. This amplifier can drive transformer hybrids or low-impedance loads
directly in either a differential or single-ended configuration.
DIA low-pass filter, DIA low-pass filter clocking, and D/Aconverslon timing
The frequency response of this filter is presented in the following pages. This response results when the
low-pass switched-capacitor filter clock frequency is 288 kHz, Like the AID filter, the transfer function of this filter
is frequency scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided on the output
on the output of the D/A low-pass filter to greatly attenuate any switched-capacitor clock feedthrough.
The 01A conversion rate is then attained by frequency dividing the 288-kHz switched-capacitor filter clock with
TX counter B. Thus, unwanted aliasing is prevented because the D/A conversion rate is an integral submultiple
of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.
~TEXAS
4-8
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75?65
TLC32040C, TLC32040l, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
asynchronous versus synchronous operation
If the transmit section of the AIC (Iow-pass filter and DAC) and receive section (bandpass filter and ADC) are
operated asynchronously, the low-pass and band-pass filter clocks are independently generated from the
master clock signal. Also, the D/A and AID conversion rates are independently determined. If the transmit and
receive sections are operated synchronously, the low-pass filter clock drives both low-pass and bandpass filters.
In synchronous operation, the AID conversion timing is derived from, and is equal to, the D/A conversion timing.
(See description of WORD/BYTE in the Terminal Functions table.)
D/A converter performance specifications
Fundamental performance specifications for the D/A converter circuitry are presented in the D/A converter
operating characteristics section of the data sheet. The D/A converter has a sample-and-hold that is realized
with a switched-capacitor ladder.
system frequency response correction
The (sin x)/x correction circuitry is performed in the digital processor software. The system frequency response
can be corrected via DSP software to ±0.1-dB accuracy to band edge of 3000 Hz for all sampling rates. This
correction is accomplished with a first-order digital correction filter, which requires only seven TMS320
instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of only 1.1 %
and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (sin x)/x correction section for more detailS).
serial port
The serial port has four possible modes that are described in detail in the Terminal Functions table. These modes
are briefly described below and in the description for WORD/BYTE in the Terminal Functions Table.
•
The transmit and receive sections are operated asynchronously, and the serial port interfaces directly with
the TMS32011 and TMS320C17.
•
The transmit and receive sections are operated asynchronously, and the serial port interfaces directly with
the TMS32020 and the TMS320C25.
•
The transmit and receive sections are operated synchronously, and the serial port interfaces directly with
the TMS32011 and TMS320C17.
•
The transmit and receive sections are operated synchronously, and the serial port interfaces directly with
the TMS32020, TMS320C25, or two SN74299 serial-to-parallel shift registers, which can then interface in
parallel to the TMS320C1 0, TMS32015, to any other digital signal processor, or to external FIFO circuitry.
operation of TLC32040wlth internal voltage reference
The internal reference of the TLC32040 eliminates the need for an external voltage reference and provides
overall circuit cost reduction. Thus, the internal reference eases the design task and provides complete control
over the performance of this integrated circuit. The internal reference is brought out to a terminal and is available
to the designer. To keep the amount of noise on the reference signal to a minimum, an external capaCitor may
be connected between REF and ANLG GND.
operation of TLC32040 or TLC32041 with external voltage reference
REF can be driven from an external reference circuit if so desired. This external circuit must be capable of
supplying 250 JJA and must be adequately protected from noise such as crosstalk from the analog input.
~ThxAs
INSTRUMENTS
POST OFFICE BOX 855303 • DALlAS. TEXAS 75265
4-9
TLC32040C, TLC320401, TLC32041C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E - ,SEPTEMBER 1987 - REVISED MAY 1995
reset
A reset function is provided to initiate serial communications between the AIC and DSP and allow fast,
cost-effective testing during manufacturing. The reset function. initializes all AIC registers, including the control
register. After a negative-going pulse on RESET, the AIC is initialized. This initialization .allows normal serial port
communications activity to occur between AIC and DSP (see AIC OX data:word format section).
loopback
This feature allows the user to test the circuit remotely. In loopback, OUT + and OUT...., are internally connected
to IN+ and IN-. Thus, the DAC bits (d15 to d2), which are transmitted to OX, can be compared with the ADC
bits (d15 to d2), which are received from DR. An ideal comparison would be that the bits on DR equal the bits
on OX. However, in practice there is some difference in these bits due to the ADC and DAC output offsets.
In loopback, if IN+ and N- are enabled, the external signals on IN+ and IN- are ignored. If AUX IN+ and AUX
IN- are enabled, the external signals on these terminals are added to the OUT + and OUT-signals in loopback
operation.
The loopback feature is implemented with digital signa.l processor control by transmitting the appropriate serial
port bit to the control register (see AIC OX data word format section).
explanation of internal timing configuration
All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the master clock
input. The shift clock signal, which strobes the serial port data between the AIC and DSP, is derived by dividing
the master clock input signal frequency by four.
SCF Clock Frequency = 2 ~a~~~t~~~~ko~r~~~~~ec: A
.
Conversion Frequency
SCF Clock Frequency
of Counter B
= Contents
CI k F
Master Clock Frequency
Sh ·ft
I
oc requency =
4
TX counter A and TX counter B, which are driven by the master clock signal, determine the D/A conversion
timing. Similarly, RX counter A and RX counter B determine the AID conversion timing. In order for the
switched-capacitor low-pass and band pass filters to meet their transfer function .specifications, the frequency
of the clock inputs of the switched-capacitor filters must be 288 kHz. If the frequencies of the clock inputs are
not 288 kHz, the filter transfer function frequencies are scaled by the ratios of the clock frequencies to 288 kHz.
Thus, to obtain the specified filter responses, the combination of master clock frequency and TX counter A and
RX counter A values must yield 288-kHz switched-capacitor clock signals. These 288-kHz clock signals can
then be divided by the TX counter Band RX counter B to establish the D/A and AID conversion timings.
TX counter A and TX counter B are reloaded every D/A conversion period, while RX counter A arid RX counter
B are reloaded every AID conversion period. The TX counter Band RX counter B are loaded with the values
in the TB and RB registers, respectively. Via software control, the TX counter A can be loaded with either the
TA register, the TA register less the TN register, or the TA register plus the TN register. By selecting the TA
register less the TN register option, the upcoming conversion timing will occur earlier by an amount of time that
equals TN times the signal period of the master clock. By selecting the TA register plus the TN register option,
the upcoming conversion timing will occur later by an amount bftime that equals TN times the signal period of
the master clock. Thus, the D/A conversion timing can be advanced .or retarded. An identical ability to alter the
AID conversion timing is provided. In this case, however, the AX counter A can be programmed via software
control with the RA register, the RA register less the RN register, or the 8A register plus the RA' register.
~TEXAS
4-10
INsTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC32040C, TLC320401, TLC32041C, TLC320411
. ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
explanation of Internal timing configuration (continued)
The ability to advance or retard conversion timing is particularly useful for modem applications. This feature
allows controlled changes in the AID and D/A conversion timing. This feature can be used to enhance
signal-to-noise performance, to perform frequency-tracking functions, and to generate nonstandard modem
frequencies.
If the transmit and receive sections are configured to be synchronous (see WORD/BYTE description), then both
the low-pass and bandpass switched-capacitor filter clocks are derived from TX counter A. Also, both the D/A
and AID conversion timing are derived from the TX counter A and TX counter B. When the transmit and receive
sections are configured to be synchronous, theRX counter A, RX counter B, RA register, RA' register, and RB
registers are not used.
="1
TEXAS
NSTRUMENTS
POST OFFICE BOX _
• DALlAS. TEXAS 7S21!S
4-11
TLC32040C, TLC320401, TLC32041C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
r-----.
. .-----------,
I,
MSTR ClK
5.184 MHz
MHz (2)
(1) L
10.368
Divide by4
________________
.J
SHIFTCLK
1.296 MHz (1)
2.592 MHz (2)
-----------------------------,
TA' Register
(6 bits)
(2'scompl)
TA Register
(5 bits)
Optional External Circuitry
for Full·Duplex Modems
Dlvldeby2
- -·kHz
- - - - - - - - ,I
Ir - - - -153.6
Clock (1)
Commercial
I
I
External
I
I
Front·End
I
I
Full·Duplex
I
I
I
Spllt·Band
I
_ _ _ _ .JI
Fllterst
IL _ _ _ _ _ _ _ _ _ _ _
dO, dl = 0,1
dO, dl = 1,0*
I'""':T=X'!"'C='o..lu...n~te-r-=A....,
=
[TA 9 (1)]
[TA =18 (2)]
(6 bits)
576-kHz
Pulses
TX Counter B
[TB =40j 7.2 kHz
[TB =36j 8.0 kHz
[TB = 30j 9.6 kHz
[TB =20j 14.4 kHz
[TB = 15j 19.2 kHz
Dlvldeby2
low-Pass/
Switched
Capacitor Filter
ClK= 288-kHz
Square Wave
DIA
Conversion
Frequency
Band·Paes
Switched
Capacitor Filter
ClK= 288-kHz
Square Wave
dO, dl = 0,1
RX Counter B
dO, dl =1,0*
[RB = 40j 7.2 kHz
AID
r--R-X-C....
ou...
n-te-rA--[RS = 36j 8.0 kHz
Conversion
[RA =9 (1)]
[RB = 30j 9.6 kHz
Frequency
[RA 18 (2)]
[RB 20j 14.4 kHz
576-kHz
[RB
15j
19.2
L _ _ _ _(6
_bits)
_ _ _ _ _ _Pulses
_____
_=_
__
_kHz
_________
=
SCF Clock Frequency
=
Master Clock Frequency
= 2 x Contents of Counter A
t Split-band filtering can alternatively be performed after the analog input function via software in the TMS320.
:t: These control bits are described in the AIC OX data word format section.
NOTE A: Frequency 1 (20.736 MHz) is used to show how 153.6 kHz (for commercially available modem split·band filter clock), popular speech
and modem sampling signal frequencies, and an internal 288-kHz switched-capacitorfilter clock can ba derived synchronously and as
submultiples of the crystal oscillator frequency. Since these derived frequencies sre synchronous submultiples of the crystal frequency,
aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacltor filter stages.
Frequency 2 (41.472 MHz) is used to show that the AIC can work with high·frequency signals, which are used by high-speed digital
signal processors.
Figure 1. Internal Timing Configuration
'~TEXAS
4-12
INSTRUMENTS
POST'OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC32040C, TLC320401, TLC32041 C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
AIC OR or OX word bit pattern
AID or D/A MSB,
1st bit sent
1st bit sent of 2nd byte
AID or D/A lSB
AIC OX data word format section
I
d15 d14 1d13 1d12 1d11 1d10 1d9 1d8 1d7 1d6 1d5 1d4 1d3 1d2 1d1 1dO COMMENTS
primary DX serial communication protocol
Hl15 (MSB) through d2 go to the D/A
converter register
~ 10
0
The TX and RX counter As are loaded w~hthe TA and
RA register values. The TX and RX counter Bs are
loaded with TB and RB register values.
+--d15 (MSB) through d2 go to the D/A
converter register
~ 10
1
The TX and RX counter As are loaded with the TA +
T~ and RA + RA' register values. The TX and AX
counter Bs are loaded with TB and RB register
values. Bits d1 - 0 and dO -1 cause the next D/A and
AID conversion periods to be changed by the addition
of TA' and RA' master clock cycles, in which T~ and
RIA' can be positive or negative or zero (refer to
Table 1).
+--d15 (MSB) through d2 go to the D/A
converter register
~ 11
0
The TX and RX counter As are loaded with the TA TA' and RA - R~ register values. The TX and RX
counter Bs are loaded with TB and RB register
values.B~d1 -1 anddO.OcausethenextD/A and
AID conversion periods to be changed by the
.subtraction of T~ and R~ master clock cycles, in
which TA' and RI~ can be positive or negative or zero
(refer to Table 1).
Hl15 (MSB) through d2 go to the D/A
converter register
~ 11
1
The TX and RX counter As are loadedw~h the TA and
RA register values. The TX and RX counter Bs are
loaded with the TB and RB register values. After a
delay of four shift clock cycles, a secondary
transmission immediately follows tp program the AIC
to operate in the desired configuration.
NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (primary communications) to the AIC Initiates
secondary communications upon completion of the primary communications.
Upon completion of the primary communication, FSX remains high for four SHIFT ClK cycles and then goes low and initiates the
secondary communication. The timing specifications for the primary and secondary communications are identical. In this manner, the
secondary communication, if initiated, is interleaved between succassive primary communications. This interleaving prevents the
secondary communication from interfering with the primary communications and DAC timing, thus preventing the AIC from skipping a DAC
output. In the synchronous mode, FSR is not asserted during secondary communications.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-13
TLC32040C, TLC320401, TLC32041C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
secondary OX serial communication protocol
x x I +- to TA register -+ I x x I +- to RA register -+ I 0 0 d13 and d6 are MSBs (unsigned binary)
x I +- to TN register -+ I x I +- to RA' register -+1 0 1 d14 and d7 are 2's complement sign bits
x I +- to TB register -+ I x I +- to RB register
x x x x x x x x
1 0 d14 andd7 are MSBs (unstOned binary)
1 1
-+1
d7 d6 d5 d4 d3 d2
Control
14-
register
d2 .. 011 deletes/Inserts the bandpass filter
-+I
d3 .. 011 disables/enables the loopback function
d4 - 011 disables/enables the AUX IN + and AUX IN- terminals
d5 .. 011 esynchronous/synchronous transmit receive sections
d6 - 011 gain control bits (see gain control section)
d7 .. 011 gain control bits (see gain control section)
reset function
A reset function is provided to initiate serial communications between the Ale and OSP. The reset function
.initializes all Ale registers, including the control register. After power has been applied to the Ale, a
negative-going pulse on RESET initializes the Ale registers to provide an 8-kHz AID and O/A conversion rate
for a 5.184-MHz master clock input signal. The Ale, except the control register, is initialized as follows (see Ale
ox data word format section):
INmALIZED
REGISTER
VALUE (HEX)
REGISTER
9
TA
TA'
TB
24
RA
9
RA'
24
RB
The control register bits are reset as follows (see Ale
ox data word format section):
.d7 - 1, d6 = 1, d5 = 1, d4 = 0, d3 =0, d2 = 1
This initialization allows normal serial port communications to occur between Ale and OSP. If the transmit and
receive sections are configured to operate synchronously and the user wishes to program different conversion
rates, only the TA, TA', and TB register need to be programmed, since both transmit and receive timing are
synchronously derived from these registers (see the terminal descriptions and Ale ox word format sections).
The circuit shown below provides a reset on power up when power is applied in the sequence given under
power-up sequence. The circuit depends on the power supplies reaching their recommended values a minimum
of 800 ns before the capacitor charges to 0.8 V above OGTL GNO.
TLC320401
TLC32041
Vcc+
~
6V
200 leO
Fi!Ri' J---i ~
::::r: O.6p.F
Vcc-
-6V
~1ExAs
INSTRUMENTS
4-14
POST OFFICE BOX 666303 • DALlAS. TEXAS 75266
TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
power-up sequence
To ensure proper operation of the Ale, and as a safeguard against latch-up, it is recommended that a Schottky
diode with a forward voltage less than or equal to 0.4 V be connected from VCC- to ANLG GND (see Figure 17).
In the absence of such a diode, power should be applied in the following sequence: ANLG GND and DGTL GND,
Vcc-, then Vcc+ and Voo. Also, no input signal should be applied until atter power up.
AIC responses to improper conditions
The Ale has provisions for responding to improper conditions. These improper conditions and the response of
the Ale to these conditions are presented in Table 1 below.
AIC register constraints
The following constraints are placed on the contents of the Ale registers:
1. TA register must be ~ 4 in word mode (WORD/BYTE = high).
2. TA register must be ~ 5 in byte mode (WORD/BYTE = lOw).
3. TA' register can be either positive, negative, or zero.
4. RA register must be ~ 4 in word mode (WORD/BYTE = high).
5. RA register must be ~ 5 in byte mode (WORD/BYTE = lOw).
6. RA' register can be either positive, negative, or zero.
7. (TA register ± TA' register) must be > 1.
8. (RA register ± RA' register) must be> 1.
9. TB register must be > 1.
Table 1. AIC Responses To Improper Conditions
AIC RESPONSE
IMPROPER CONDITIONS
TA register + TA' register = 0 or 1
TA register - TA' register = 0 or 1
TA register + TA' register < 0
Reprogram TX counter A with TA register value
RA register + RA' register - 0 or 1
RA register - RA' register - 0 or 1
Reprogram RX counter A with RA register value
RA register + RA' register = 0 or 1
MODULO 64 arithmetic is used to ensure that a positive value is loaded into RX counter A, i.e., RA
register + RA' register + 40 hex is loaded into RX counter A.
TA register - 0 or 1
RA register - 0 or 1
TA register < 4 in word mode
TA register < 5 in byte mode
RA register < 4 in word mode
RA register < 5 in byte mode
The Ale is shut down.
TB register - 0 or 1
Reprogram TB register with 24 hex
MODULO 64 arithmetic is used to ensure that a positive value is loaded into the TX counter A, i.e., TA
register + TA' register + 40 hex is loaded into TX counter A.
The AIC serial port no longer operates.
RB register = 0 or 1
Reprogram RB register with 24 hex
AIC and DSP cannot communicate
Hold last DAC output
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-15
TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 -,REVISED MAY 1995
Improper operation due'to conversion times being too close together
If the difference between two successive 01A conversion frame syncs is less than 1/19.2 kHz, the AIC operates
improperly. In this situation, the second O/A conversion frame sync occurs too quickly and there.is not enough
time for the ongoing conversion to be completed. This situation can occur if the A and B registers are improperly
programmed or if the A + A' register or A - A' register result is too small. When incrementally adjusting the
conversion period via the A + A' register options, the designer should be very careful not to violate this
requirement (see following diagram).
FrameSync
FSX or FSR
-;1
~'j
~ _
j4- Ongoing Conversion
tl2
:
""'!
1-._ _
~
asynchronous operation - more than one receive frame sync occurring between two transmit
frame syncs
.
When incrementally adjusting the conversion period via the A + N or A - N register options, a specific protocol
is followe.d. The command to use the incremental conversion period adjust option is sent to the AIC during a
FSX frame sync. The ongoing conversion period is then adjusted. However, either receive conversion period
A or B may be adjusted. For both transmit and receive conversion periods, the incremental conversion period
adjustment is performed nearl the end of the conversion period. Therefore, if there is sufficient time between t1
and t2, the receive conversion period adjustment is performed during receive conversion period A. Otherwise,
the adjustment is performed during receive conversion period B. The adjustment command only adjusts one
transmit conversion period and one receive conversion period. To adjust another pair of transmit and receive
conversion periods, another command must be issued during a subsequent FSX frame (see figure below).
k-J
W
1414------ Transmit Conversion Period ------.t~
Conversion
Period A
~1ExAs
4-16
.
INSTRUMENTS
POST OFFICE BOX 665303 • DAUAS. TEXAS 75265
TLC32040C, TLC320401, TLC32041 C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
asynchronous operation - more than one receive frame sync occurring between two receive frame syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific protocol
is fOllowed. For both transmit and receive conversion periods, the incremental conversion period adjustment
is performed near the end of the conversion period. The command to use the incremental conversion period
adjust options is sent to the AIC during a FSX frame sync. The ongoing transmit conversion period is then
adjusted. However, three possibilities exist for the receive conversion period adjustment in the diagram as
shown in the following figure. If the adjustment command is issued during transmit conversion period A, receive
conversion period A is adjusted if there is sufficient time between t1 and t2' Or, if there is not sufficient time
between t1 and t2, receive conversion period B is adjusted. Or, the receive portion of an adjustment command
can be ignored if the adjustment command is sent during a receive conversion period, which is already being
or is adjusted due to a prior adjustment command. For example, if adjustment commands are issued during
transmit conversion periods A, B, and C, the first two commands can cause receive conversion periods A and
B to be adjusted, while the third receive adjustment command is ignored. The third adjustment command is
ignored since it was issued during receive conversion period B, which already is adjusted via the transmit
conversion period B adjustment command.
~
Transmit
Conversion
Period A
+
Transmit
Conversion
Period B
-+-
Transmit
Conversion
Period C
W-
l-J------,W
t2
FSR
I I.
1II
.
1-
-
-
-
Receive Conversion Period A
----!
-~+14-----
Receive Conversion Period B
--I
asynchronous operation - more than one set of primary and secondary OX serial communication occurring
between two receive frame sync (see Ale OX data word format section)
The TA, TA', TB, and control register information that is transmitted in the secondary communications is always
accepted and is applied during the ongoing transmit conversion period. If there is sufficient time between t1 and
t2, the TA, RA', and RB register information, which is sent during transmit conversion period A, is applied to
receive conversion period A. Otherwise, this information is applied during receive conversion period B. If RA,
RA', and RB register information has already been received and is being applied during an ongoing conversion
period, any subsequent RA, RA', or RB information that is received during this receive conversion period is
disregarded (see diagram below).
FSX
t1
Secondary
l n
Primary
~
Transmit
Conversion
Period A
Primary
I
Secondary
I n
~
Transmit
Conversion
Period B
I
Primary
Secondary
I n
~
I
Transmit
Conversion
PerlodC
~
~
t2
I
FSR
+- Receive Conversion ~..
Receive Conversion Period B
Period A
I
~
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
4-17
TLC3204OC, TLC32040l, TLC32041C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
Table 2. Gain Control Table Analog Input Signal Required for Full-Scale AID Conversion
CONTROL REGISTER BITS.
INPUT CONFIGURATIONS
Differential configuration
Analog input - IN + -: IN- AUX IN+ - AUX IN-
Single-ended configuration
Analog input = IN + - ANLG GND
= AUX IN+-ANLG GND
t
d6
d7.
1
1
0
0
AID CONVERSION
ANALOG INPUrt
RESULT
±6V
Full seale
1
0
±3V
Full scale
0
1
±1.5V
Full scale
1
1
0
0
±3V
Half scale
1
0
±3V
Fullscaie
0
1
±1.5V
Full scale
.. .
..
In thiS example, Vref IS assumed to be 3 V. In order to minimize distortion, It IS recommended that the analog Input not exceed 0.1 dB below full
scale.
Rfb
Rfb
I---+--}
R
IN + -J\N\,..---,
IN- -.l\/V'v-......
R
AUX IN + - J \ N \ " ' - - - .
To Multiplexer
t -........- }
AUX IN- -"VV'\r'".-t
R
To Multiplexer
R
Rfb
Rfb
Rfb = R ford6= 1, d7 = 1
d6=O,d7=O
Rfb= 2Rford6= 1, d7= 0
Rfb = 4R ford6 = 0, d7 = 1
Rfb=Rford6=1,d7=1
d6=O,d7=O
Rfb=2R ford6= 1, d7= 0
Rfb=4R ford6= 0, d7= 1
Figure 2. IN + and IN- Gain
Control Circuitry
Figure 3. AUX IN + and AUX INGalti Control Circuitry
(sin x)/x correction section
The Ale does not h~ve (sin x)/x correction circuitry after the digital-to-analog converter.The (sin x)/x correction
can be accomplished easily and efficiently in digital signal processor (DSP) software. Excellent correction
accuracy can be achieved to a band edge of 3000 Hz by using a first-order digital correction filter. The results,
which are shown below, are typical of the numerical correction accuracy that can be achieved for sample rates
of interest. The filter requires oniy seven instruction cycles per sample on the TMS320 DSPs. With a 200-ns
instruction cycle, nine instructions per sample represents an overhead factor of 1.4% and 1.7% for sampling
rates of 8000 Hz and 9600 Hz, respectively. This correction adds a slight amount of group delay at the upper
edge of the 300-300Q-Hz band.
'
(f
~TEXAS
4-18
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
TLC32040C, TLC320401, TLC32041C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
(sin x)/x roll-off for a zero-order hold function
The (sin x)/x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for the
various sampling rates is shown in the table below.
Table 3. (sin x)/x Roll-Off
20 log
sin It Ilts
It
Is (Hz)
Ills
(1= 3000 Hz)
(dB)
7200
-2.64
8000
-2.11
9600
-1.44
14400
-0.63
19200
-0.35
The actual AIC (sin x)/x roll-off is slightly less than the above figures, because the AIC has less than a 100%
duty cycle hold interval.
correction filter
To compensate for the (sin x)/x roll-off of the AIC, a first-order correction filter shown below, is recommended.
} - - - - - - - - - - 4 . - - - . Y ( 1 + 1)
U(I + 1)
p1
The difference equation for this correction filter is:
yi + 1 =p2(1 - p1) (Ui + 1) + p1 yi
where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
IH(f)12 =
p2 2 (1 - p1 )2
1 - 2p1 cos(2 11: f/f.)
+ pP
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303. DAUAS. TEXAS 75266
4-19
TLC32040C, TLC320401, TLC32041C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
correction results
Table 4below shows the optimum p values and the corresponding correction results for 8000-Hz and 9600-Hz
sampling rates.
Table 4. Correction Results
ERROR (dB)
fs =8000 Hz
p1 =-0.14813
p2 =0.9888
ERROR (dB)
fs = 9600 Hz
p1 = -0.1307
p2 = 0.9951
300
-0.099
-0.043
600
-0.089
-0.043
900
1200
-0.054
0
-0.002
0
1500
1800
0.041
0.079
0
0.043
2100
0.100
0.043
2400
0.091
0.043
2700
-0.043
3000
-0.102
0
-0.043
f (Hz)
TMS320 software requirements
The digital correction filter equation can be written in state variable form as follows:
Y = k1 x Y + k2 x U
Where
k1 = p1
k2 = (1 - p1) x p2
Y = filter state
U = next 110 sample
The coefficients k1 and k2 must be represented as 16-bit integers. The SACH instruction (with the proper shift)
will yield the correct result. With the assumption that the TMS320 processor page pointer and memory
configuration are properly initialized, the equation can be executed in seven instructions or seven cycles with
the following program:
ZAC
LTK2
MPYU
LTAK1
MPYY
APAC
SACH (dma), (shift)
4-20
"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32040C, TLC320401, TLC32041C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage range, Vcc+ (see Note 1) ............................................ -0.3 V to 15 V
Supply voltage range, Voo .....•.•............................................•.... -0.3 V to 15 V
Output voltage range, Vo .......................................................... - 0.3 V to 15 V
Input voltage range, VI ............................................................. -0.3 V to 15 V
Digital ground voltage range ........................................................ -0.3 V to 15 V
Operating free-air temperature range, TA: TLC32040C, TLC32041 C ...... . . . . . . . . . . . . . .. O°C to 70°C
TLC320401, TLC32041I ..................... -40°C to 85°C
Storage temperature range, Tstg ................................................... -40°C to 125°C
Case temperature for 10 seconas: FN package .............................................. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ..................... 260°C
t Stresses beyond those lis1ed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values for maximum ratings are with respect to VCC-.
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC + (see Note 2)
4.75
5
5.25
V
Supply voltage, vCC- (see Note 2)
-4.75
-5
.-5.25
V
4.75
5
5.25
V
Digital supply voltage, VDD (see Note 2)
Digital ground voltage with respect to ANLG GND, DGTL GND
V
0
Reference input voltage, Vref(ext) (see Note 2)
2
4
V
High-level input voltage, VIH
2
VDD+0.3
0.8
V
Low-level input voltage, VIL (see Note 3)
-0.3
Load resislance at OUT + and/or OUT -, RL
300
Load capacitance at OUT + and/or OUT -, CL
100
MSTR CLK frequency (see Note 4)
0.075
Analog input amplifier common mode input voltage (see Note 5)
Operating free-air temperature, TA
NOTES: 2.
5 10.368
±1.5
AID or 0/A conversion rate
20
ITLC32040C,TLC32041C
LTLC320401, TLC320411
V
{)
0
70
-40
85
pF
MHz
V
kHz
·C
..
Voltages at analog Inputs and outputs, REF, VCC +, and VCC-, are With respect to ANLG GND. Voltages at digital Inputs and outputs
and VDD are with respect to DGTL GND.
3. The algebraic convention, in which the leas1 positive (most negative) value is designated minimum, is used in this data sheet for
logic voltage levels and temperature only.
4. The bandpass low-pass switched-capacltor filter response specifications apply only when the switched-capacitor clock frequency
is 288 kHz. For switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted by the ratio of
sWitched-capacitor filter clock frequency to 288 kHz.
5. This range applies when (IN+-IN-) or (AUX IN+ -AUX IN-) equals ± 6 V.
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-21
TLC32040C, TLC320401, TLC32041 C, 1lC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987- RIOVISED MAY 1995
electrical characteristics over recommended operating free..alr temperature range, VCC+
VCC- = -5 V, Voo = 5 V (unless otherwise noted)
= 5 V,
total device, MSTR CLK frequency = 5.184 MHz, outputs not loaded
TEST CONDITIONS
PARAMETER
VOH
High-level output voltage
VDD-4.75V,
IOH =-300 J.LA
VOL
Low-level output voltage
VDD-4.75V,
IOL-2rnA
MIN ·TYpt
MAX
2.4
UNIT
V
0.4
TLC3204_C
35
TLC3204 I
40
V
rnA
ICC+
Supply current from VCC+
ICC-
Supply current from VCC-
IDD
Supply current from VDD
Vref
Internal reference output voltage
"'Vref
ro
Temperature coefficient of internal reference vOltage
200
ppm/"C
Output resistance at REF
100
k.O
TLC3204 C
-35
TLC3204_1
-40
7
fMSTR CLK • 5.184 MHz
3
3.3
mA
mA
V
receive amplifier Input
TYpt
MAX
AID converter offset error (fiHers bypassed)
25
65
mV
AID converter offset error (filters in)
25
65
:mV
TEST CONDITIONS
PARAMETER
CMRR
Common-mode rejection ratio at IN+, IN-, or AUX IN+,
AUXIN-
11
Input resistance at IN+, IN-, or AUX IN+,AUX IN-, REF
MIN
See Note 6
UNIT
55
dB
100
k.O
transmit filter output
PARAMETER
TEST CONDITIONS
Voo
Output offset voltage at OUT +, OUT -, (single-ended
relative to ANLG GND)
VOM
Maximum peak output voltage swing across RL at OUT +
RL ~ 300 0,
or OUT -, (single ended)
VOM
Maximum peak output voltage swing between RL at
OUT + and OUT -, (differential output)
Offset voltage = 0
RL~6000
system distortion speCifications, SCF clock frequency
PARAMETER
Attenuation of second harmonic of AID
Input signal
Attenuation of third and higher harmonics
of AID input signal
Single ended
Attenuation of second harmonic of DIA
Input signal
Single ended
Attenuation of third and higher harmoniCS
of DIA input signal
Single ended
Differential
Differential
Differential
Differential
TYpt
MAX
15
75
UNIT
mV
±3
V
±6
V
=288 kHz
TEST CONDITIONS
Single ended
MIN
MIN
TYPt
70
VI = -0.5 dB to -24 dB referred to Vref,
See Note 7
62
VI = -0.5 dB to -24 dB referred to Vref,
See Note 7
57
VI = -0 dB to -24 dB referred to Vref,
See Note 7
62
VI = -0 dB to -24 dB referred to Vref,
See Note 7
57
70
65
65
70
70
65
65
MAX
UNIT
dB
dB
dB
dB
t Ali typical values are at TA = 25°C.
NOTES: 6. The test condition is a D-dBm, 1-kHz input signal with an 8-kHz conversion rate.
7. The test condition VI is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to Vref). The load impedance for the DAC
is 600 0.
4-22
-!II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 •
DA~EXAs 75265
TLC32040C, TLC320401, TLC32041 C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
AID channel slgnal-to-dlstortlon ratio
TEST CONDITIONS
(see Note 7)
PARAMETER
AID channel signal-to-distortion ratio
Av=2t
Av= 1t
MIN
MIN
MAX
MAX
Av=4t
MIN
VI--6dBto-0.1 dB
58
>58§
>58§
VI = -12 dB to-6 dB
58
58
>58§
VI = -18 dB to-12 dB
56
58
58
VI = -24 dB to-18 dB
50
56
58
VI - -30 dB to -24 dB
44
50
56
VI = -36 dB to -30 dB
38
44
50
VI = -42 dB to -36 dB
32
38
44
VI = -48 dB to -42 dB
26
32
38
VI = -54 dB to -48 dB
20
26
32
MAX
UNIT
dB
DIA channel signal-to-distortion ratio
TEST CONDITIONS
(see Note 7)
PARAMETER
D/A channel signal-to-distortion ratio
MIN
VI--6 dB to OdB
58
VI = -12 dB to-6 dB
58
VI=-18dBto-12dB
56
VI = -24 dB to-18 dB
50
VI = -30 dB to -24 dB
44
VI = -36 dB to -30 dB
38
VI - -42 dB to -36 dB
32
VI = -48 dB to -42 dB
26
VI - -54 dB to -48 dB
20
MAX
UNIT
dB
gain and dynamic range
PARAMETER
TEST CONDITIONS
Absolute transmit gain tracking error while
transmitting into 600 0
MIN
TYP:j:
MAX
UNIT
-48-dB to O-dB signal range,
See Note 8
±0.05
±0.15
dB
±0.05
±0.15
dB
Absolute receive gain tracking error
-48-dB to O-dB signal range,
See Note 8
Absolute gain of the AID channel
Signal input is a -0.5-dB,
1-kHz sinewave
0.2
dB
Absolute gain of the D/A channel
Signal input is a o-dB,
1-kHz sinewave
-0.3
dB
power supply rejection and crosstalk attenuation
PARAMETER
TEST CONDITIONS
VCC + or VCC- supply voltage
rejection ratio, receive channel
f=Ot030kHz
VCC + or VCC- supply voltage
rejection ratio, transmit channel
(single ended)
f=Ot030kHz
f - 30 kHz to 50 kHz
f - 30 kHz to 50 kHz
Crosswalk attenuation, transmlt-to-receive (single ended)
Idle channel, supply signal at 200 mV r:rp
measured at DR (ADC output)
Idle channel, supply signal at 200 mV p-p
measured at OUT +
~
MIN
TYp:j:
30
45
MAX
UNIT
dB
30
dB
45
80
dB
t Av IS the programmable gain of the input amplifier.
:j: All typical values are at TA = 2SoC.
§ A value >58 is overrange and signal clipping occurs.
NOTES: 7. The test condition Vin is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to Vref). The load impedance for the DAC
is600n
8. Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to Vref).
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
4-23
TLC32040C, T,LC320401, TLC32041C, TLC32041I
ANALOG INTERFACE,CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
delay distortion, SCF clock frequency = 288 kHz ±2%, input (IN+ -IN;...) is±3-V sinewave
Refer to filter response graphs for delay distortion specifications.
TLC32040 and TLC32041 bandpass filter transfer function (see curves): SCF clock
frequency = 288kHz, ±2%, input (IN+ -IN-) isa ±3-V sinewave (see Note 9)
PARAMETER
TEST CONDITIONS
FREQUENCY RANGE
MIN
Input signal relerence is 0 dB
300Hz $1$3-4 kHz
PARAMETER
I~
-58
4.6 kHz
,
dB
=288 kHz ±2% (see Note 9)
FREQUENCY RANGE
1$3-4 kHz
Output signal relerence is 0 dB
0.5
-16
TEST CONDITIONS
Filter gain, (see Note 10)
-0.5
1-4 kHz
low-pass filter transfer function, SCF clock frequency
UNIT
-25
1=170Hz
Filter gain, (see Note 10)
MAX
-42
I-100Hz
MIN
MAX
-0.5
0.5
1= 3.6 kHz
-4
1=4 kHz
-30
1~4.4
-58
kHz
UNIT
dB
serial port
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH - -300 IlA
VOL
Low-level output voltage
IOL=2 mA
II
Input current
MIN
TYpt
MAX
2.4
UNIT
V
0.4
V
±10
IlA
Ci
Input capacitance
15
pF
Co
Output capacitance
15
pF
operating characteristics over recommended operating free-air temperature range, VCC+ = 5 V,
VCC_=-5V, VOO=5V
noise (measurement includes low-pass and bandpass switched-capacitor filters)
PARAMETER
TEST CONDITIONS
Single ended.
Transmit noise
Differential
TYPt
MAX
200
OX input = 00000000000000, constant input code
300
Inputs grounded, gain = 1
300
20
UNIT
I1VrmS
500
20
/
Receive noise (see Note 11)
MIN
I1Vrms
dBmcO
475
I1Vrms
dBmcO
t All tYPical values are at TA = 25°C.
NOTES: 9, The above lilter specifications are lor' a switched-capacitor filter clock range 01 288 kHz ±2%. Forswitched-capacitor filter Clocks
at Irequencies other than 288 kHz ±2%, the filter response is shifted by the ratio 01 switched-capacitor lilter clock Irequency to
288kHz.
, 0, The filter gain outside of the passband is measured with respect to the gain at 1 kHz. The filter gain within the passband is measured
with respect to the average gain within the passband, The passbands are 300 to 3400 Hz and Oto 3400 Hz lor the bandpass and
low-pass filters respectively,
11, The noise Is reffered to the input with a buffer gain 01 one, If the buffer gain is two or lour, the noise figure is correspondingly reduced.
The noise is computed by statistically evaluating the digital output 01 the AID converter,
~TEXAS'
4-24
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC32040C, TLC320401, TLC32041 C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
timing requirements
serial port recommended Input signals
MIN
MAX
UNIT
tc(MCLK)
Master clock cycle time
tr(MCLK)
Maste~ clock
rise time
10
ns
tfIMCLK)
Master clock fall time
10
ns
95
ns
Master clock duty cycle
42%
RESET pulse duration (see Note 12)
800
ns
20
ns
tc(SCLI<)/4
ns
tsulOXI
OX setup time before SCLKJ.
thlOX)
OX hold time after SCLKJ.
serial port - AIC output signals, CL';' 30 pF for SHIFT ClK output, CL
=15 pF for all other outputs
MIN
tclSCLKI
tfISCLK)
Shift clock (SCLK) cycle time
trISCLK)
Shift clock (SCLI<) rise time
58%
TYPt
MAX
3
8
ns
8
ns
380
Shift clock (SCLK) fall time
ns
3
Shift clock (SCLI<) duty cycle
UNIT
45
55
%
Id(CH-FL)
Delay from SCLKi to FSRI FSXI FSDJ.
30
IdICH-FHI
Delay from SCLKi to FSRI FSXI FSDi
35
90
ns
IdICH-DR)
DR valid after SCLKi
90
ns
Id(CH-EL)
Delay from SCLKi to EODXI EODRJ. in word mode
90
ns
IdICH-EHI
Delay from SCLKi to EODXI EODRi in word mode
90
ns
tf(EODX)
EODX fall time
2
8
ns
tf(EODR)
EODR fall time
2
8
ns
IdICH-ELl
Delay from SCLKi to EODXI EODRJ. in byte mode
90
ns
IdICH-EHI
Delay from SCLKi to EODX/EODRi in byte mode
90
ns
Id(MH-8L)
Delay from MSTR CLKi to SCLKJ.
170
ns
65
ns
65
170
ns
Id(MH-8H) Delay from MSTR CLKi to SCLKi
t Typical values are at TA = 25°C.
NOTE 12: RESET pulse duration is the amount of time that the reset terminal is held below 0.8 V after the power supplies have reached their
recommended values.
~TEXAS
INSTRUMENTS
POST OFFICE eox 655303 • OALLAS. TEXAS 75265
4-25
TLC32040C, TLC320401, TLC32041C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
serial port - Ale output signals
TEST CONDITIONS
MIN
TYpt
MAX
UNIT
IcCSCLKI
tfCSCLK)
Shift clock (SCLI<) cycle time
Shift clock (SCll<) fall time
50
ns
trCSCLK)
Shift clock (SCLK) rise time
50
ns
380
Shift clock (SCLI<) duty cycle
ns
45
%
fdCCH-FLl
Delay from SCLKi to FSRI FSX J.
CL-50pF
55
52
ns
fdCCH-FHI
Delay from SCLKi to FSR/FSxi
CL-50pF
52
ns
fdCCH-DR)
DR valid after SCLKi
90
ns
fdLCH-EL)
Delay from SCLKi to EODXI EODRJ. in word mode
90
ns
fdCCH-EH)
Delay from SCLKi to mDXt'E05Ri in word mode
90
ns
tfCEODX)
EODXfalitime
15
ns
tfCEODR)
EODR fall time
15
ns
fdCCH-El)
Delay from SClKi to EODXIEODRJ. in byte mode
100
ns
fdCCH-EH)
Delay from SCLKi to EODX/EODRi in byte mode
100
ns
fd(MH-SL)
Delay from MSTR CLKi to SCLKJ.
65
ns
fdlMH-SHl Delay from MSTR CLKi to SCLKi
t TYPical values are at TA - 25°C.
65
ns
~ThxAs
4-26
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
14---* tc(SCLK)
SHIFTCLK
I
O.BV
tcI(CH-FL)~ 14-
\I. O.B V
FSR, FSX
I I
I I
I:
O.BV
tcI(CH-FH)
I
~
r
II
I~ 14-1
I
14-
tcI(CH-FH)
II
~,r;I4-~_
O.BV)j"'--~I~';-----~rv
2V
I
I
.
~Dl~5__~~~~:____~~~______~~~_D~1_~oo~I_ __
U(DX)
DX
tcI(CH-FL) --.;
I
tcI(CH-DR)
2V
DR _ _ _
I
It
~
D15
!4-D14
~
EODR, EODX
D13
~
Don't Care
it-lh(DX)
II
I
I
~
D9
~ 14- tcI(CH-EL)
-.lie-
tcI(CH-EH)
'-'!--__
~~~O.~BV~______________~~__________-JTiV
-
I';
.
(a) BYTE-MODE TIMING
SHIFTCLK
DR
DX
D15
D2
---tt
14- th(DX)
Dl
DO
tcI(CH-EL)
II
~
:--...:
14-- tcI(CH-EH)
0.BVU';':":2V~-
(b) WORD-MODE TIMING
MSTRCLK
I
SHIFTCLK
i+-*- td(MH-SL)
~----------------\l
______________
(e) SHIFT-CLOCK TIMING
Figure 4. Serial. Port Timing
-!i1lExAs
INSTRuMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-27
TLC3204OC,TLC320401, TLC32041C, TLC320411
ANALOG INTERFACE CIRCUITS
SLASOl4E - SEPTEMBER 1987 ~ REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
ClKOUT
~.
I~I--------------------......----1....
I
I
SO,G1
00-015
-----~--C(
I
Valid
)>-----------------
(8) IN INSTRUCTION TIMING
ClKOUT~
----------------------
I~I
'---~I~·
I
I
I
SN74LS138 Y1
SN74LS299 ClK
I
00-015--------«
Valid
I)>----------------
(b) OUT INSTRUCTION TIMING
Figure 5. TMS32010·TLC32040ITLC32041 Interface Timing
~1ExAs
4-28
INSTRUMENTS
·POST OFFIOE BOX 665303 • DAllAS, TEXAS 75265
TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
TYPICAL CHARACTERISTICS
AIC TRANSMIT CHANNEL FILTER
10
0.3
Magnitude
0
0.25
\
-10
0.2
Group Delay
-20
\
III
"I
".e
-30
Ii
-50
See Note B
CD
c
:e
-40
-60
-70
1'\
J V
~
-80
-90
o
~ I
j \../
-
SeeNoteA
-
~eeNoted
\
/
0.15
~I
0.1
15
0.05
\
\,
o
0.05
i;'
Q
go
e
"
;i!!
0.1
Y
0.15
0.2
2
3
4
5
Normalized Frequency _ kHz x SCF clock frequency
NOTES: A.
B.
C.
D.
288kHz
Maximum relative delay (0 Hz to 600 Hz) = 125 ~
Maximum relative delay (600 Hz to 3000 Hz) = ± 50 ~
Absolute delay (600 Hz to 3000 Hz) = 700 ~
Test conditions are VCC+. VCC-. and VDD within recommended operating conditions. SCF clock f - 288 kHz ±2% input = ±3-V
slnewave. and TA = 25°C.
Figure 6
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS. TEXAS 75265
4-29
TLC32040C, TLC32040l, TLC32041C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
TYPICAL CHARACTERISTICS
TLC32040 AND TLC32041
RECEIVE CHANNEL FILTER
10
0.35
See Note A
Magnitude
0.3
0
0.26
-10
\
-20
\
CD
'Q
I
-30
-8
-40
:
-50
~
c
::E
\
\
\
Group Delay
l\. 7 ~I\
V V'\ I V
-50
-70
LSeeNoteB
-80
\
See NoteC -
-90
0
2
,
\
3
4
Normalized Frequency _ kHz x SCF clock frequency
288kHz
NOTES: A. Maximum relative delay (200 Hz to 600 Hz) .. 3350 lIS
B. Maximum relative delay (600 Hz to 3000 Hz) .. ± 50 lIS
C. Absolute delay (600 Hz to 3000 Hz) - 1230 lIS
D. Test conditions are VCC+. VCC-. and VOO within recommended operating conditions. SCF clock f - 288 kHz ±2%. input - ±3-V
sinewave. and TA = 25°C.
Figure 7
~lEXAS
INSTRUMENTS
POST OFFICE BOX 656303 • DALlAS, TEXAS 75286
TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
TYPICAL CHARACTERISTICS
AID SIGNAL-T()'DISTORTION RATIO
AID GAIN TRACKING
(GAIN RELATIVE TO GAIN
AT O-dB INPUT SIGNAL)
va
INPUT SIGNAL
0.5
80
70
l-kHz Input Signal With an
8-kHz Converalon Rate
I
Galn=4X
!BI
80
j
50
I
40
.V / '
V
0.4
..... -~
Galn=lX
0.3
!B
I
~
~
30
0.1
0
-0.1
~
-0.2
,..
-0.3
10
o
0.2
~c
20
-50
l-kHz Input Signal
8-kHz Converalon Rate
-0.4
-0.5
-40
-30
-20
-10
o
10
-50
-40
Input Signal Relative to Vraf - dB
-30
-20
o
-10
10
Input Signal Relative to Vraf - dB
Figure 9
FigureS
D/A GIAN TRACKING
D/A CONVERTER SIGNAL-T().DISTORTION RATIO
vs
va
(GAIN RELATIVE TO GAIN
AT 0 OdB INPUT SIGNAL)
INPUT SIGNAL
100
90
1.--r.I---rI----r---,...----,
1.0 ,......-~
l-kHz Input Signal Into 600 a +-_+_-1
0.8 8-kHz Converalon Rate
I.
.1
I
l-kHz Input Signal Into 600 a
8-kHz Conversion Rate
0.6t---+---t--+---t---I1---i
80
70
""..,.
60
50
/.
.
-
!BI
I:D
i
~
./
40
~
30
0.4 t - - - + - - - t - - + - - + - - I I - - - i
0.21----+---+--+---1---11----1
Or---+---~---r--~----r-__;
-0.2 t---+---t--+---t---II---i
-0.4 t - - - + - - - t - - + - - + - - I I - - - i
20
-0.6 t - - - + - - - t - - + - - + - - I I - - - i
10
-0.8 t - - - + - - - t - - + - - + - - I f - - - i
__ __ ____ __ __
__
o
-50
-1~
-10
o
Input Signal Relative to Vraf - dB
-40
-30
-20
10
-50
~
-40
Figure 10
~
-30
~
-20
~
-10
~~
o
~
10
Input Signal Relative to Vraf - dB
FlgLlre 11
NOTE: Test conditions are VCC+. VCC-. VOO and within recommended operating conditions set clock f = 288 kHz ±2%. and TA _ 25°C.
-!I
TEXAS
INSTRUMENTS
POST OFFICE BOX 66S303 • DALLAS. TEXAS 75265
4-31
TLC32040C, TLC320401, TLC32041C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
TYPICAL CHARACTERISTICS
ATTENUATION OF THIRD HARMONIC OF AID INPUT
vs
INPUT SIGNAL
ATTENUATION OF SECOND HARMONIC OF AID INPUT
va
INPUT SIGNAL
100
90
III
"I
80
.2
c
0
70
:J:
60
Ii
,~
100
1\
I "II
-
1·kHz Input Signal
90 ~ B-kHz Conversion Rate '
./
III
~
.S!
5
80
I
60
50
1:
50
"0
40
"0
40
i
30
i
30
!
20
"c
J
c
f3.
c
!
::I
1·kHz Input Signal
B-kHz Conversion Rate
J
I
I
10
o
-50
-40
-30
~
70
/
r"/
~
20
10
-20
o
-10
o
10
-50
-40
. Input Signal Relative toVref - dB
-30
III
"I
.S!
c
i
j
80
80
--
... /
va
INPUT SIGNAL
".....
90
-
.S!
c
i
80
70
50
40
"0
40
30
i
f3.
5
!
20
10
-40
-30
-~O
-10
o
./
60
1:
o
I.
.1
1
1·kHz Input 81gnallnto 600 0
B-kHz Conversion Rate
III
"I
50
-50
....."
"
30
20
10
o
10
-50
Input 81gnal Relative to Vref - dB
-40
-30
-20
-10
o
10
Input Signal Relative to Vref - dB
Figure 14
Figure 15
NOTE: Testconditlons are VCC+. VCC-. and VDD within recommended operating conditions set clock f a 288 kHz ±2%. and TA
~1ExAs
4-32
10
ATTENUATION OF THIRD HARMONIC OF DIA INPUT
100
I.
I
1
1·kHz Input Signal Into 800 0
B-kHz Conversion Rate
70
o
-10
Figure 13
ATTENUATION OF SECOND HARMONIC OF DIA INPUT
vs
INPUT SIGNAL
90
-20
Input Signal Relative to Vref - dB
Figure 12
100
""'
INSTRUMENTS
POST OFFICE BOX 656303- DALLAS. TEXAS 75265
=25°C.
TLC32040C, TLC320401, TLC32041C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995
APPLICATION INFORMATION
cr
TMS32010
SN74LS299
I - S1
QH
I
DEN
L
01
A
A1/PA1
B
'to
D~15
\
A·H SR
N74LS299
S1
QH
' - - - 02
on
!D
01
00-015
WE
CLKOUT
INT
~
8
CLK
DO-D7
\
TLC320401
TLC32041
SO CLK< I-01
Y1 I--
C
SN74LS138
DO-D15
DX
G2
AOIPAO
A2JPA2
Ffi
\
A·H
~
---
SHIFTCLK
.r-
~~
SR
C1
Q 1D
DR
-~
-
~
J
1 -
MSTRCLK
EOl5i
Figure 16. TMS32010·TLC32040ITLC32041 Interface Circuit
~1ExAs
INSTRUMENTS
POST OFFICE BOX 6S6303 • DAllAS. TEXAS 75266
4-33
TLC32040C, TLC320401, TLC32041C, TLC320411
ANALOG INTERFACE CIRCUITS
SLAS014E -SEPTEMBER 1987 - REVISED MAY 1995
APPLICATION INFORMATION
TMS32020/C25
TLC32040ITLC32041
, CLKOUT
MSTRCLK
FS~
DX
DX
CLKX
ANLGGND
FSFi"'
FSR
DR
, CLKR
VCC,+
REF
FSX
DR
VCC-
SHIFTCLK
..J"
*
If
1\ C
5V
;:: :;::C
1
BAT42t+ C
-5 V,
VDD
5V
;::
DGTLGND
r: 0.1 jIJ'
~
~,
C =0.2 jIJ', Ceramic
Figure 17. AIC Interface to the TMS32020/C25 Showing Decoupllng Capacitors and Schottky Diodet
t
Thomson Semiconductors
VCC
___-----4.---......
---~~
3 V Output
5000
0.01 jIJ'
TL431
0.1 jIJ' Ceramlnc
25000
For:
VCC
VCC
=12 V, R =7200 0
=10 V, R =5600 0
VCC=5 V, R = 15000
Figure 18. External Reference Circuit For TLC32045
~1ExAs
4-34
INSTRUMENTS
POST OFFICE BOX 655:!03 .' DALLAS. TEXAS 75265
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
Jt OR N PACKAGE
• 14-Blt Dynamic Range ADC and DAC
(TOP VIEW)
• 2's Complement Format
• Variable ADC and DAC Sampling Rate Up
to 19,200 Samples per Second
• Switched-Capacitor Antialiasing Input Filter
and Output-Reconstruction Filter
NU
RESET
EODR
FSR
OR
MSTRCLK
• Serial Port for Direct Interface to
TMS(SMJ)320C17, TMS(SMJ)32020,
TMS(SMJ)32OC25,
and TMS320C30 Digital Signal Processors
• Synchronous or Asynchronous ADC and
DAC Conversion Rates With Programmable
Incremental ADC and DAC Conversion
Timing Adjustments
• Serial Port Interface to SN74(54)299
Serlal-to-Parallel Shift Register for Parallel
Interface to TMS(SMJ)32010,
TMS(SMJ)320C15, or Other Digital
Processors
• Internal Reference for Normal Operation
and External Purposes, or Can Be
Overridden by External Reference
4
NU
NU
IN+
INAUX IN+
AUXINOUT+
OUT-
VDD
REF
DGTLGND
SHIFTCLK
EODX
OX
WORD/BYTE
9
11
FSX
VCC+
VCCANLGGND
ANLGGNO
NU
NU
t Refer to the mechanical data for the JT package.
FK OR FN PACKAGE
(TOP VIEW)
• CMOS Technology
DR
MSTRCLK
description
The TLC32044 and TLC32045 are complete
analog-to-digital and digital-to-analog input and
output systems on single monolithic CMOS chips.
The TLC32044 and TLC32045 integrate a
bandpass switched-capacitor antialiasing input
filter, a 14-bit-resolution AJDconverter, four
microprocessor-compatible serial port modes, a
14-bit-resolution D/A converter, and a low-pass
switched-capacitor output-reconstruction filter.
The devices offer numerous combinations of
master clock input frequencies and conversionl
sampling rates, which can be changed via digital
processor control.
VOO
REF
5
6
7
8
4 3 2
1 28 2726
25
24
INAUXIN+
AUXINOUT+
OUT-
9
10
11
19
12 1314 15 16 17 18
VCC+
VCC-
IXC~CI)ZZZZ
IW IXu.. ::> ::> (!)(!)
C c
!!!
(!)(!)
~
zz
«
C
II:
...J...J
NU - Nonusable; no extemal connection should be made to
these terminals (see Table 2).
AVAILABLE OPTIONS
PACKAGE
TA
O·C to 70·C
-20·C to 85·C
-40·C to 85·C
-55·C to 125·C
PLASTIC CHIP
CARRIER
(FNI
PLASTIC DIP
(N)
TLC32044CFN
TLC32044CN
TLC32045CFN
TLC32045CN
CERAMIC DIP
(J)
CHIP CARRIER
(FK)
TLC32044MJ
TLC32044MFK
TLC32044EFN
TLC32044IN
TLC32045IN
-!I
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75266
Copyright © 1995. Texas Instruments Incorporated
4-35
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C,TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
description (continued)
Typical applications for the TLC32044 and TLC32045 include speech encryption for digital transmission,.
speech recognition! storage systems, speech synthesis, modems (7.2-, 8-, 9.6-, 14.4-, and 19.2-kHz sampling
rate), analog interface for digital signal processors (DSPs), industrial process control, biomedical
instrumentation, acoustical signal processing, spectral analysis, data acquisition, and instrumentation
recorders. Four serial modes, which allow direct interface to the TMS(SMJ)320C17, TMS(SMJ)32020,
TMS(SMJ)320C25, and TMS(SMJ)320C30 digital signal processors, are provided. Also, when the transmit and
receive sections of the analog interface circuit (AIC) are operating synchronously, it will interface to two
SN74(54)299 serial-to-parallel shift registers. These serial-to-parallel shift registers can then interface in parallel
to the TMS(SMJ)32010, TMS(SMJ)320C15, and other digital signal processors, or external FIFO circuitry.
Output data pulses are emitted to inform the processor that data transmission is complete or to allow the DSP
to differentiate between two transmitted bytes. A flexible control scheme is provided so that the functions of the
TLC32044 or TL.C32045 can be selected and adjusted coincidentally with signal processing via software
control.
The antialiasing input filter comprises eighth-order and fourth-order CC-type (Chebyshev/elliptic transitional)
low-pass and high-pass filters, respectively. The input filter is implemented in switched-capacitor technology
and is preceded by a continuous time filter to eliminate any possibility of aliasing qaused by sampled data
filtering. When only low-pass filtering is desired, the high-pass filter can be switched out of the signal path. A
selectable, auxiliary, differential analog input is provided for applications where more than one analog input is
required.
The AID and D/A architectures ensure no missing codes and monotonic operation. An internal voltage reference
is provided to ease the design task and to provide complete control over the performance of the TLC32044 or
TLC32045. The internal voltage reference is brought out to a terminal and is available to the designer. Separate
analog and digital voltage supplies and grounds are provided to minimize noise and ensure a wide dynamic
range. Also, the analog circuit path contains only differential circuitry to keep noise to an absolute minimum. The
only exception is the DAC sample and hold, which utilizes pseudo-differential circuitry.
The output-reconstruction filter is an eighth-order CC-type (Chebyshev/elliptic transitional low-pass filter)
followed by a second-order (sin x)/x correction filter and is implemented in switched-capacitortechnology. This
filter is followed by a continuous-time filter to eliminate images of the digitally encoded signal. The on-board
(sin x) Ix correction filter can be switched out of the signal path using digital signal processor control, if desired.
The TLC32044C and TLC32045C are characterized for operation from O°C to 70°C. The TLC32044E is
characterized for operation from -20°C to 85°C. The TLC320441 and TLC320451 are characterized for operation
from -40°C to 85°C. The TLC32044M is characterized for operation from -55°C to 125°C.
~TEXAS
4-36
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
functional block diagram
Filter
IN+-4-a............
IN- _ _'"1...<'"
A/D
AUXIN +-4-a............
AUXIN- _ _'"1...<'"
SERIAL
PORT
DR
Receive Section
r-I
---------------------1
EODR
--..,
I
Internal
I
Voltage
I
Reference
_ _ ...JI
IL __
Filter
MSTERCLK
SHIFTCLK
WORD/BYTE
OX
FSX
OUT + ~-_'l-""/
OUT -
FSR
D/A
"--""""'-Ir--1
EODX
Transmit Section
VCC+ VCC- ANLG DTGL VDD
GND GND (Digital)
REF
Terminal Functions
TERMINAL
NAME
NO.
ANLGGND
DESCRIPTION
UO
17,18
Analog ground return for all internal analog circuits. Not internally connected to DGTL GND.
AUX IN+
24
I
Noninvertlng auxiliary analog Input stage. AUX IN + can be switched into the bandpass filter and NO
converter path via software control. If the appropriate bit in the control register is aI, the auxiliary inputs
will replace the IN + and IN- inputs. If the bit is a 0, the IN + and IN- inputs will be used (see the AIC OX
data word format section).
AUXIN-
23
I
Inverting auxiliary analog input (see the above AUX IN + description).
DGTLGND
9
DR
5
0
Data receive. DR is used to transmit the ADC output bits from the AIC to the TMS320 (SMJ320) serial port.
This transmission of bits from the AIC to the TMS320 (SMJ320) serial port is synchronized with the SHIFT
CLKsignal.
OX
12
I
Data transmit. OX is used to receive the DAC input bits and timing and control information from the TMS320
(SMJ320). This serial transmission from the TMS320 (SMJ320) serial port to the AIC is synchronized with
the SHIFT ClK signal.
EODR
3
0
End of data receive. (See the WORD/BYTE description and Serial Port Timing diagram.) During the
word-mode timing, EODR is a low-going pulse that occurs immediately after the 16 bits of NO information
have been transmitted from the AIC to the TMS320 (SMJ320) serial port. EODR can be used to interrupt
a microprocessor upon completion of serial communications. Also, EODR can be used to strobe and enable
external serial-ta-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus
communications between the AIC and the serial-ta-parallel shift registers. During the byte-mode timing,
EODR goes low after the first byte has been transmitted from the AIC to the TMS320 (SMJ320) serial port
and is kept low until the second byte has been transmitted. The DSP can use this low-going signal to
differentiate between the two bytes as to which is first and which is second. EODR does not occur after
secondary communication.
Digital ground for all internal logic circuits. Not internally connected to ANLG GND.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75255
4-37
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REViseD MAY 1995
Terminal Functions (continued)
TERMINAL
NAME
NO.
11
EODX
1/0
DESCRIPTION
0
End of data transmit. (See the WORD/BYTE description and Serial Port Timing diagram.) During the
word-mode timing, EODX is a low-going pulse that occurs immediately after the 16 bits of D/A converter
and control or register information have been transmitted from the TMS320 (SMJ320) serial port to the AIC.
EODX .can be used to interrupt a microprocessor upon the completion of serial communications. Also,
EODX can be used to strobe and enable extemal serial-ta-parallel shift registers, latches, or an extemal
FIFO RAM, and to facilitate parallel data-bus communications between the AIC and the serial-ta-parallel
shift registers. During the byte-mode timing, EODX goes low after the first byte has been transmitted from
the TMS320 (SMJ320) serial port to the AIC and is kept low until the second byte has been transmitted. The
DSP can use this low-going signal to differentil\te between the two bytes as to which is first and which is
second.
Frame sync receive. In the serial transmission modes, which are described in the WORD/BYTE description,
FSR is held low during bit transmission. When FSR goes low, the TMS320 (SMJ320) serial port begins
receiving bits from the AIC via DR of the AIC. The most Significant DR bit is present on DR before FSR goes
low. (See Serial Port Timing and Internal Timing Configuration dil\Qrams.) FSR does not occur after
secondary communications.
Frame sync transmit. When FSX goes low, the TMS320 (SMJ320) serial port begins transmitting bits to the
AIC via OX ofthe AIC.ln all serial transmission modes, which are described inthe WORD/BYTE description,
FSX is held low during bit transmission (see Serial Port Timing and Internal Timing Configuration diagrams).
FSR
4
0
FSX
14
0
IN+
IN-
26
I
25
I
Inverting input to analog input amplifier stage
MSTRClK
6
I
Master clock. MSTR ClK is used to derive all the key logic signals of the AIC, such as the shift clock, the
switched-capacitor filter clocks, and the AID and D/A timing signals. The Internal Timing Configuration
diagram shows how these key signals are derived. The frequencies of these key signals are synchronous
submultiples of the master clock frequency to eliminate unwanted aliasing when the sampled analog signals
are transferred between the switched-capacitor filters and the AID and D/A converters (see the Internal
Timing Configuration diagram).
OUT+
22
0
Noninverting output of analog output power amplifier. OUT+ can drive transformer hybrids or
high-impedance loads directly in either a differential or a single-ended configuration.
OUT-
21
0
Inverting output of analog output power amplifier. OUT-is functionally identical with and complementary
to OUT +.
REF
8
1/0
Internal voltage reference. An intemal reference voltage is brought out on REF. An external voltage
reference can also be applied to REF.
RESET
2
I
Reset lunction. RESET Is provided to initialize the TA, TA', TB, RA, RA', RB, and control registers. A reset
initiates serial communications between the AIC and DSP. A reset initializes all AIC registers including the
control register. After a negative-going pulse on RESET, the AIC registers are initialized to provide an 8-khz
d;;Ita conversion rate for a 5.184-MHz master clock input signal. The conversion rate adjust registers, TfI:
and RfI:, are reset to 1. The control register bits are reset as follows (see AIC OX data word format section):
d9 =1, d7 =1, d6 = 1, d5 =1, d4 - 0, d3 = 0, d2 = 1.
This Initialization allows normal serial-port communication to occur between the AIC and DSP.
SHIFTClK
10
0
Shift clock. SHIFT ClK is obtained by dividing the master clock signal frequency by four. SHIFT ClK is used
to clock the serial data transfers of the AIC, described in the WORD/BYTE desCription below (seethe Serial
Port Timing and Internal Timing Configuration diagrams).
Noninverting input to analog input amplifier stl\Qe
VDD
7
Digital supply voltage, 5 V ±50/0
VCC+
20
Positive analog supply voltage, 5 V ±50/0
Vec-
19
Negative analog supply voltage, -5 V ±50/0
~TEXAS
4-,38
INSTRUMENTs
POST OFFICE eox 655303'. DALLAS. TEXAS 75265
TlC32044C, TlC32044E, TlC320441, TlC32044M, TlC32045C, TlC320451
VOICE~BAND ANALOG INTERFACE CIRCUITS
SLAS017F-MARCH 1988- REVISED MAY 1995
Terminal Functions (continued)
TERMINAL
NAME
NO.
WORD/BYTE
13
110
DESCRIPTION
I
Used in conjunction wHh a bit in the control register, WORDIBYTE is used to establish one of four serial
modes. These four serial modes are described below.
Ale transmit and raceive sections ara operated asynchronously.
The following description applies when the AIC is configured to have asynchronous transmit and receive
sections. If the appropriate data bit in the control register is a 0 (see the AIC DX data word format section),
the transmit and receive sections are asynchronous.
L Serial port directly interfaces with the serial port of the DSP and communicates in two
8-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams).
1. FSX or FSR is brought low.
2. One 8-bit byte is transmitted or one 8-bit byte is received.
3. EODX or EODR is brought low.
4. FSX or FSR emits a positive frame-sync pulse that is four shift clock cycles wide.
5. One 8-bit byte is transmitted or one 8-bit byte is received.
6. EODX or EODR is brought high.
7. FSX or FSR is brought high.
H Serial port directly interfaces wHh the serial ports of the TMS(SMJ)32020, TMS(SMJ)320C25, or
TMS(SMJ)320C3Q, and communicates in one 16-bit word. The operation sequence Is as follows
(see Serial Port Timing diagrams):
1. FSX or FSR is brought low.
2. One 16-bit word is transmitted or one 16-bit word is received.
3. FSX or FSR is brought high.
4. EODX or EODR emits a low-going pulse.
Ale transmit and raceive sections are operated synchronously.
If the appropriate data bH in the control register is 1, the transmit and receive sections are configured to be
synchronous. In this case, the bandpass switched-capacHorfilter and the ND conversion timing are derived
from the TX counter A, TX counter B, and TA, T~, and TB registers, rather than the RX counter A, RX counter
B, and RA, R~, and RB registers. In this case, the AIC FSX and FSR timing are identical during primary
data communication; however, FSR is not asserted during secondary data communication since there is
no new ND conversion result. The synchronous operation sequences are as follows (see Serial Port Timing
diagrams).
L
Serial port directly interfaces with the serial port of the DSP and communicates in two 8-bH
bytes. The operation sequence is as follows (see Serial Port Timing diagrams):
1. FSX and FSR are brought low.
2. One 8-bit byte is transmitted and one 8-bit byte is receiVed.
3. EODX and EODR are brought low.
4. FSX and FSR emit positive frame-sync pulses that are four shift clock cycles wide.
5. One 8-bit byte is transmHted and one 8-bH byte is received.
6. EODX and EODR are brought high.
7. FSX and FSR are brought high.
H Serial port directly interfaces wHh the serial port of the TMS(SJM)32020, TMS(SMJ)320C25, or
TMS320C30, and communicates in one 16-bit word. The operation sequence is as follows (see
Serial Port Timing diagrams):
1. FSX and FSR are brought low.
2. One 16-bit word is transmHted and one 16-bit word is received.
3. FSX and FSR are brought high.
4. EODX or EODR emit low-going pulses.
Since the transmit and receive sections of the AIC are now synchronous, the AIC serial port with additional
NOR and AND gates interface to two SN74(54)299 serial-to-parallel shift registers. InterfaCing the AIC to
the SN74(54)299 shift register allows the AIC to interface to an extemal FIFO RAM and facilitates parallel,
data bus communications between the AIC and the digital signal processor. The operation sequence is the
same as the above sequence (see Serial Port Timing diagrams).
~TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS, TEXAS 75265
4-39
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
PRINCIPLES OF OPERATION
analog input
Two sets of analog inputs are provided. Normally, the IN + and IN- input set is used; however, the auxiliary input
set, AUX IN + and AUX IN-, can be used if a second input is required. Each input set can be operated in either
differential or single-ended modes, since sufficient common-mode range and rejection are provided. The gain
for the IN +, IN-, AUX IN +, and AUX IN- inputs can be programmed to be either 1,2, or 4 (see Table 2). Either
input circuit can be selected via software control. It is important to note that a wide dynamic range is assured
by the differential internal analog architecture and by the separate analog and digital voltage supplies and
grounds.
AID bandpass filter, AID bandpass filter clocking, and AID conversion timing
The AID high-pass filter can be selected or bypassed via software control. The frequency response of this filter
is presented in the following pages. This response results when the switched-capacitor filter clock frequency
is 288 kHz and the AID sample rate is 8 kHz. Several possible options can be used to attain a 288-kHz
switched-capacitor filter clock. When the filter clock frequency is not 288 kHz, the low-pass filter transfer function
is frequency scaled by the ratio of the actual clock frequency to 288 kHz. The ripple bandwidth and 3-dB
low-frequency roll-off points of the high-pass section are 150 Hz and 100 Hz, respectively. However, the
high-pass section low-frequency roll-off is frequency scaled by the ratio of the AID sample rate to 8 kHz.
The internal timing configuration and Ale DX data word format sections of this data sheet indicate the many
options for attaining a 288-kHz bandpass switched-capacitor filter clock. These sections indicate that the RX
counter A can be programmed to give a 288-kHz bandpass switched-capacitor filter clock for several master
clock input frequencies.
The AID conversion rate is then attained by frequency dividing the 288-kHz bandpass switched-capacitor filter
clock with the RX counter B. Unwanted aliasing is prevented because the AID conversion rate is an integral
submultiple of the bandpass switched-capacitor filter sampling rate, and the two rates are synchronously locked.
AID converter performance specifications
Fundamental performance specifications for the AID converter circuitry are presented in the AID converter
operating characteristics section of this data sheet. The realization of the AID converter circuitry with
switched-capacitor techniques provides an inherent sample-and-hold.
analog output
The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier outputs
are brought out. This amplifier can drive transformer hybrids or low-impedance loads directly in either a
differential or single-ended configuration.
DIA low-pass filter, D/A low-pass filter clocking, and DIA conversion timing
The frequency response of this filter is presented in the following pages. This response results when the
low-pass switched-capacitor filter clock frequency is 288 kHz. Like the AID filter, the transfer function of this filter
is frequency scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided on the output
of the (sin x) Ix correction filter to eliminate tITe periodic sample data signal information, which occurs at multiples
of the 288-kHz switched-capacitor filter clock. The continuous time filter also greatly attenuates any
switched-capacitor clock feedthrough.
~ThXAS
4-40
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
PRINCIPLES OF OPERATION
D/A low-pass filter, D/A low-pass filter clocking, and D/A conversion timing (continued)
The D/A conversion rate is attained by frequency dividing the 288-kHz switched-capacitor filter clock with TX
Counter B. Unwanted aliasing is prevented because the D/A conversion rate is an integral submultiple of the
switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.
asynchronous versus synchronous operation
If the transmit section of the AIC (low-pass filter and DAC) and receive section (bandpass filter and ADC) are
operated asynchronously, the low-pass and bandpass filter clocks are independently generated from the master
clock signal. Also, the D/A and AID conversion rates are independently determined. If the transmit and receive
sections are operated synchronously, the low-pass filter clock drives both low-pass and bandpass filters. In
synchronous operation, the AID conversion timing is derived from, and is equal to, the D/A conversion timing
(see description of the WORD/BYTE in the Terminal Functions table.)
D/A converter performance specifications
Fundamental performance specifications for the D/A converter circuitry are presented in the D/A converter
operating characteristics section of the data sheet. The D/A converter has a sample-and-hold that is realized
with a switched-capacitor ladder.
system frequency response correction
The (sin x)/x correction for the D/A converter zero-order sample-and-hold output can be provided by an
on-board second-order (sin x)/x correction filter. This (sin x)/x correction filter can be inserted into or deleted
from the signal path by digital signal processor control. When inserted, the (sin x)/x correction filter follows the
switched-capacitor low-pass filter. When the TB register (see Internal Timing Configuration section) equals 36,
the correction results of Figures 11 and 12 can be obtained.
The (sin x)/x correction can also be accomplished by deleting the on-board second-order correction filter and
performing the (Sin x)/x correction in digital signal processor software. The system frequency response can be
corrected via DSP software to ±0.1-dB accuracy to a band edge of 3000 Hz for all sampling rates. This correction
is accomplished with a first-order digital correction filter, which requires only seven TMS320 (SMJ320)
instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of only 1.1 %
and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (sin x)/x correction section for more details).
serial port
The serial port has four possible modes that are described in detail in the Terminal Functions table. These modes
are briefly described below and in the functional description for WORD/BYTE.
•
The transmit and receive sections are operated asynchronously, and the serial port interfaces directly
with the DSP.
•
The transmit and receive sections are operated asynchronously, and the serial port interfaces directly
with the TMS(SMJ)32020, TMS(SMJ)320C25, and the TMS(SMJ)320C30.
•
The transmit and receive sections are operated synchronously, and the serial port interfaces directly
with the DSP.
•
The transmit and receive sections are operated synchronously, and the serial port interfaces directly
with the TMS(SMJ)32020, TMS(SMJ)320C25, TMS(SMJ)320C30, or two SN74(54)299 serial-toparallel shift registers, which can then interface in parallel to the TMS(SMJ)3201 0, TMS(SMJ)320C15,
and SMJ320E15 to any other digital signal processor or to external FIFO circuitry.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-41
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE ,CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
PRINCIPLES OF OPERATION
operation of TLC32044 or TLC32045 with Internal voltage reference
The internal reference eliminates the need for an external voltage reference and provides. overall circuit cost
reduction. Thus, the internal reference eases the design task and provides complete control over device
performance. The internal reference is brought out to a terminal and is available to the designer. To keep the
amount of noise on the reference signal to a minimum, an external capaCitor can be connected between REF
and ANLG GND.
operation of TLC32044 or TLC32045 with external voltage reference
REF can be driven from an external reference circuit. This external circuit must be capable of supplying 250 IlA
and must be adequately protected from noise such as crosstalk from the analog input.
reset
A reset function is provided to initiate serial communications between the Ale and DSP and to allow fast,
cost-effective testing during manufacturing. The reset function initializes all Ale registers, including the control
register. After a negative-going pulse on RESET, the Ale is initialized. This initialization allows normal serial port
communications activity to occur between Ale and DSP (see Ale DX data word format section).
loopback
This feature allows the user to test the circuit remotely. In loopback, OUT + and OUT- are internally connected
to the IN + and IN-. Thus, the DAe bits (d15 to d2), which are transmitted to DX, can be compared with the ADe
bits (d15 to d2), which are received from DR. An ideal comparison would be that the bits on DR equal the bits
on DX. However, there are some difference in these bits due to the ADe and DAe output offsets. The loopback
feature is implemented with digital signal processor control by transmitting the appropriate serial port bit to the
control register (see Ale DX data word format section).
~1ExAs
4-42
INSTRUMENTS
POST OFFICE BOX 656303 ~ OALU\S. TEXAS 75265
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
INTERNAL TIMING CONFIGURATION
MSTR ClK , . . - - - - - - - - - - - - - - - - - ,
5.184 MHz (1)
Divide by 4
I
10.368 MHz (2) L
----------------~
-----------------------------.,
TA' Register
(6 bits)
(2'scompl)
TA Register
(5 bits)
Optional External Circuitry
for Full Duplex Modems
Dlvldeby2
--------------.,II
153.60kHz
r""'D-lv-ld-e"CIOCk (1)
by 135
Commercial
External
Front-End
Full-Duplex
Split-Band
L ___________
____ ~
Fllterst
I
I
I
I
I
I
SHIFTClK
1.296 MHz (1)
2.592 MHz (2)
low-Passi
(sin xix
Correction
Switched
CapaCitor Filter
ClK 2660kHz
Square Wave
=
dO, d1
dO, d1
r-:T~X:-:C:-o.l.u-:nt:-er..;A~
=0,1
=1,0*
=
=
[TA 9 (1)]
[TA =18 (2)]
(6 bits)
TXCounterB
[TB =4Oj. 7.2 kHz]
[TB 36j 8.0 kHz]
[TB =30j 9.6 kHz]
[TB =20j 14.4 kHz]
[TB 15j 19.2 kHz]
5760kHz
Pulses
D/A
Conversion
Frequency
=
low-Pass
Switched
capacitor Filter
ClK 2660kHz
Square Wave
=
dO, d1
dO, d1
=0,1
RX Counter B
AID
Conversion
Frequencyl
[RB 40j 7.2 kHz]
RX Counter A
[RB =36j 8.0 kHz]
High-Pass
[RA 9 (1)]
[RB 30j 9.6 kHz]
SwItched
[RA =18 (2)]
5760kHz
[RB =20j 14.4 kHz]
capaCitor
[RB
15j
19.2
L _ _ _ _(6
_bits)
_ _ _ _ _ _Pulses
_____
_=
_
__
_kHz]
_ _ _ _Filter
_ _ClK
___J
=1,0*
=
=
=
t Split-band filtering can altematively be perfonned after the analog input function via software in the TMS(SMJ)320.
:I: These oontrol bits are described in the AIC OX data word format section.
NOTE: Frequency 1 (20.736 MHz) is used to show how 153.6 kHz (for a commercially available modem split-band filter clock), popular speech
and modem sampling signal frequencies, and an intemal 2660kHz switched-capacltor filter clock can be derived synchronously and as
submultiples of the crystal oscillator frequency. Since these derived frequencies are synchronous submultiples of the crystal frequency,
aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter stages.
Frequency 2 (41.472 MHz) is used to show thatthe AIC can work with high-frequency signals, which are used by high-speed digital signal
processors.
-!II TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
4-43
TlC32044C, TlC32044E, TlC320441, TlC32044M,·TlC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
explanation of internal timing configuration .
All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the master clock
input. The shift clock signal, which strobes the serial port data between the AIC and DSP, is derived by dividing
the master clock input signal frequency by four.
Low-pass:
Master Clock Frequency
SCF Clock Frequency (D/A or AID path) = 2 x Contents of Counter A
C
. F
_ SCF Clock Frequency (D/A or AID path)
onverslon requency Contents of Counter B
High-pass:
SCF Clock Frequency (AID Path) = AID Conversion Frequency
Shift Clock Frequency
= Master
CIOC: Frequency
TX counter A and TX counter B, which are driven by the master clock, determine the D/A conversion timing.
Similarly, RX counter A and RX counter B determine the AID conversion timing. In order for the low-pass
switched-capacitor filter in the D/A path to meet its transfer function specifications, the frequency of its clock
input must be 288 kHz. If the clock frequency is not 288 kHz, the filter transfer function. frequencies are
frequency-scaled by the ratios of the clock frequency to 288 kHz. Thus, to obtain the specified filter response,
the combination of master clock frequency and TX counter A and RX counter A values must yield a 288-kHz
switched-capacitor clock signal. This 288-kHz clock signal can then be divided by the TX counter B to establish
the D/A conversion timing.
.
The transfer function of the bandpass switched-capacitor filter in the AID path is a composite of its high-pass
and low~pass section transfer functions. The high-frequency roll-off ofthe low-pass section meets the bandpass
filter transfer fUAction specification when the low-pass section SCF is 288 kHz. Otherwise, the high-frequency
roll-off will be frequency-scaled by the ratio of the high-pass section's SCF clock to 288 kHz. The low-frequency
roll-off ofthe high-pass section meets the bandpass filter transfer function specification when the AID conversion
rate is 8 kHz. Otherwise,. the low-frequency roll-off of the high-pass section is frequency-scaled by the ratio of
the AID conversion rate to 8 kHz.
TX counter A and TX counter B are reloaded every D/A conversion period, while RX counter A and RX counter
B are reloaded every AID conversion period. The TX counter Band RX counter B are loaded with the values
in the TB and RB registers, respectively. Via software control, the TX counter A can be loaded with either the
TA register, the TA register less the TA' register, or the TA register plus the TA' register. By selecting the TA
register less the TA' register option, the upcoming conversion timing occurs earlier by an amount of time that
equals TA' times the signal period of the master clock. By selecting the TA register plus the TA' register option,
the upcoming conversion timing occurs later by an amount of time that equals TA' times the signal period of the
master clock. The D/A conversion timing can be advanced or retarded. An identical ability to alter the AID
conversion timing is provided. In this case, however, the RX counter A can be programmed via software control
with the RA register, the RA register less the RA' register, or the RA register plus the RA' register.
The ability to advance or retard conversion timing is particularly useful for modem applications. This feature
allows controlled changes in the AID and D/A conversion timing. This feature can be used to enhance
signal-to-noise performance, to perform frequency-tracking functions, and to generate nonstandard modem
frequencies.
~TEXAS
4-44
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75266
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
explanation of internal timing configuration (continued)
If the transmit and receive sections are configured to be synchronous (see WORD/BYTE description), then both
the low-pass and bandpass switched-capacitor filter clocks are derived from TX counter A. Also, both the D/A
and AID conversion timing are derived from the TX counter A and TX counter B. When the transmit and receive
sections are configured to be synchronous, the RX counter A, RX counter B, RA register, RA' register, and RB
registers are not used.
AIC DR or OX word bit pattern
AID or D/A MSB,
1st bit sent
1st bit sent of 2nd byte
AID or D/A LSB
AIC OX data word format section
I
I
I
I
d15 d14 d13 d12 d11
I dID I de I d8 I d7 I dB I d5 I d4 I d3 I d2 I dl I dO
Comments
primary OX serial communication protocol
Hl15 (MSB) through d2 go to the D/A converter register
~
I
0
0 The TX and RX counter As are loaded with the TA and
RA register values. The TX and RX counter Bs are
loaded with TB and RB register values.
Hl15 (MSB) through d2 go to the D/A converter register
~
I
0
1 The TX and RX counter As are loaded with the TA +
TPt and RA + RA' register values. The TX and RX
counter Bs are loaded with the TB and RB register
values. LSBs dl = 0 and dO =1 cause the next D/A
and AID conversion periods to be changed by the
addition of TA' and RA' master clock cycles, in which
TA' and RPt can be positive or negative or zero (refer
toTable 1).
Hl15 (MSB) through d2 go to the D/A converter register
~ 11
0 The TX and RX counter As are loaded with the TATPt and RA - RA' register values. The TX and RX
counter Bs are loaded with the TB and RB register
values. LSBs d1 a 1 and dO = 0 cause the next D/A
and AID conversion periods to be changed by the
subtraction of TPt and RPt master clock cycles, in
which TA' and RA' can be positive or negative or zero
(refer to Table 1).
Hl15 (MSB) through d2 go to the D/A converter register
~ 11
1 The TX and RX counter As are loaded with the TA and
RA register converter register values. The TX and RX
counter Bs are loaded with the TB and RB register
values. After a delay of four shift clock cycles, a
secondary transmission immediately follows to
program the AIC to operate in the desired
configuration.
NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (primary communications) to the AIC initiates
secondary communications upon completion of the primary communications. Upon completion of the primary communication, FSX
remains high for four shift clock cycles and then goes low and initiates the secondary communication. The timing specifications for the
primary and secondary communications are identical. In this manner, the secondary communication, if initiated, is interleaved between
successive primary communications. This interleaving prevents the secondary communication from interfering with the primary
communications and DAC timing, thus preventing the AIC from skipping a DAC output. In the synchronous mode, FSR is not asserted
during secondary communications.
~lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-45
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
secondary OX serial communication protocol
x x I f- to TA register ~ I x x I f- to RA register ~ I
0 0 d13 and d6 are MSBs (unsigned binary)
x I f- to TA' register -l I x I f- to RA' register ~ I
0 1 d14 and rIl are 2's complement sign bits
x I f- to TB register -l I x I f- to RB register -ll
.1
x x x x x x d9
1 1
xd7d6d5d4 d3 d2
Control
I+-
Register
---+I
0 d14 and rIl are MSBs (unsigned binary)
d2 = 011
deletes/inserts the ND high-pass filter
d3 - 011
d4 = 011
disables/enables the loopback function
disables/enables the AUX IN + and AUX IN-
d5 - 011
asynchronous/synchronous transmit and receive sections
d6 - 011
gain control bits (see gain control section)
d7 =0/1 gain control bits (see gain control section)
d9 - 011
delete/insert on-board second-order (sin x)/x correction filter
reset function
A reset function is provided to initiate serial communications between the Ale and DSP. The reset function
initializes all Ale registers, including the control register. After power has been applied to the Ale, a
negative-going pulse on RESET initializes the Ale registers to provide an 8-kHz AID and D/A conversion rate
for a 5.184 MHz master clock input signal. The Ale, except the control register, is initialized as follows (see Ale
DX data word format section):
REGISTER
TA
TA'
TB
RA
RA'
RB
INITIALIZED REGISTER
VALUE (HEX)
9
1
24
9
24
The control register bits are reset as follows (see Ale DX data word format section):
d9 = 1, d7 = 1, d6 = 1,. d5 = 1, d4 = 0, d3 = 0, d2 = 1
This initialization allows normal serial port communications to occur between Ale and DSP. If the transmit and
receive sections are configured to operate synchronously and the user wishes to program different conversion
rates, only the TA, TA', and TB register neec:l to be programmed, since both transmit and receive timing are
synchronously derived from these registers (see the terminal functions table and Ale DX word format sections).
The circuit shown in Figure 1 provides a reset on power up when power is applied in the sequence given under
power-up sequence. The circuit depends on the power supplies reaching their recommended values a minimum
of 800 ns before the capacitor charges to 0.8 V above DGTL GND.
TLC320441TLC32045
5V
200kO
O.51J.F
L"':v~cc~-:.J-~- -5 v
Figure 1. Power-Up Reset
~1ExAs .
4-46
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
power-up sequence
To ensure proper operation of the Ale and as a safeguard against latch-up, it is recommended that Schottky
diodes with forward voltages less than or equal to 0.4 V be connected from VCC- to ANLG GND and from VCCto DGTL GND (see Figure 21). In the absence of such diodes, power should be applied in the following
sequence:ANLG GND and DGTLGND, Vcc-, then Vcc+ and Voo. Also, no input signal should be applied until
after power up.
'
AIC responses to improper conditions
The Ale has provisions for responding to improper conditions. These improper conditions and the response of
the Ale to these conditions are presented in Table 1 below.
AIC register constraints
The following constraints are placed on the contents of the Ale registers:
1.
2.
3.
4.
5.
6.
7.
8.
9.
TA register must be ~ 4 in word mode (WORD/BYTE = high).
TA register must be ;:: 5 in byte mode (WORD/BYTE = lOW).
TA' register can be either positive, negative, or zero.
RA register must be ;:: 4 in word mode (WORD/BYTE = high).
RA register must be;:: 5 in byte mode (WORD/BYTE =low).
RA' register can be either positive, negative, or zero.
(TA register ± TA' register) must be > 1.
(RA register ± RA' register) must be > 1.
TB register must be > 1.
Table 1. AIC Responses to Improper Conditions
IMPROPER CONDITION
Ale RESPONSE
TA register + TA' register - 0 or 1
TA register - Til: register = 0 or 1
Reprogram TX counter A with TA register value
TA register + TA' register < 0
MODULO 64 arithmetic is used to ensure that ,a positive value is loaded into the TX counter A, i.e., TA
register + Til: register + 40 hex is loaded into TX counter A.
RA register + RA' register = 0 or 1
RA register - RII: register = 0 or 1
Reprogram RX counter A with RA register value
RA register + RA' register. 0 or 1
MODULO 64 arithmetic is used to ensure that a positive value is loaded Into RX counter A, i.e., RA
register + RA' register + 40 hex is loaded into RX counter A.
TA register - 0 or 1
RA register - 0 or 1
AIC is shut down.
TA register < 4 in word mode
TA register < 5 In byte mode
RA register < 4 in word mode
RA register < 5 in byte mode
TB register = 0 or 1
RB register _ 0 or 1
The AIC serial port no longer operates.
AIC and DSP cannot communicate
Hold last DAC output
Reprogram TB register with 24 hex
Reprogram RS register with 24 hex
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-47
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
..
SLAS017F - MARCH 1988- REVISED MAY 1995
........------------------------------....----..--~
------------------------
improper operation due to conversion times being too close together
Ifthe difference between two successive D/A conversion frame syncs is less than 1/19.2 kHz, the Ale operates
improperly. In this situation, the second D/A conversion frame sync occurs too quickly and there is not enough
time for the ongoing conversion to be completed. This situation can occur if the A and B registers are improperly
programmed or if the A + A' register or A - A' register result is too small. When incrementally adjusting the
conversion period via the A + A' register options, the designer should be careful not to violate this requirement
(see following diagram).
asynchronous operation - more than one receive frame sync occurring between two transmit
frame syncs
When incrementally adjusting the conversion period via the A + N or A - N register options, a specific protocol
is followed. The command to use the incremental conversion period adjust option is sent to the Ale during a
FSX frame sync. The ongoing conversion period is then adjusted. However, either r~ceive conversion period
A or B can be adjusted. For both transmit and receive conversion periods, the incremental conversion period
adjustment is performed near the end of the conversion period. Therefore, if there is sufficient time between t1
and t2, the receive conversion period adjustment is performed during receive conversion period A. Otherwise,
the adjustment is performed during receive conversion period B. The adjustment command only adjusts one
transmit conversion period and one receive conversion period. To adjust another pair of transmit and receive
conversion periods, another command must be issued during a subsequent FSX frame (see figure below).
U
FSX
i4~------
l.-
Receive Conv.
Period A
--...l..-
Transmit Conversion Period
Receive Conv.
Period B
W
-----~~
--J
Figure 2. Adjusted Transmit and Receive Conversion Periods
asynchronous operation - more than one transmit frame sync occurring between two receive
frame syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific protocol
is followed. For both transmit and receive conversion periods, the incremental conversion period adjustment
is performed near the end of the conversion period. The command to use the incremental conversion period
adjust options is sent to the Ale during a FSX frame sync. The ongoing transmit conversion period is then
adjusted. However, three possibilities exist for the receive conversion period adjustment in the diagram as
shown in the following figure. If the adjustment command is issued during transmit conversion period A, receive
conversion period A is adjusted if there is sufficient time between t1 and t2. If there is not sufficient time between
t1 and t2, receive conversion period B is adjusted. The receive portion of an adjustment command can be ignored
if the adjustment command is sent during a receive conversion period, which is already being or will be adjusted
~1ExAs
4-48
INSTRUMENTS
POST OFFICE BOX e65303 • DALlAS. TEXAS 75265
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
due to a prior adjustment command. For example, if adjustment commands are issued during transmit
conversion periods A, B, and C, the first two commands can cause receive conversion periods A and B to be
adjusted, while the third receive adjustment command is Ignored. The third adjustment command is ignored
since it was issued during receive conversion period B, which already is adjusted via the transmit conversion
period B adjustment command.
I
j4--
Receive Conversion Period A
Transmit
Converalon
Period A
I
Transmit
I
I
Transmit
-¥- Conversion --I~""'- Conversion ~
Period B
LJ
+
PerIod C
Receive Conversion Period B
~
----.!
Figure 3. Receive and Transmit Conversion Period Adjustments
asynchronous operation - more than one set of primary and secondary DX serial communication
occurring between two receive frame sync (see Ale DX data word format section)
The TA, TA', TB, and control register information that is transmitted in the secondary communications is always
accepted and is applied during the ongoing transmit conversion period. If there is sufficient time between t1 and
t2, the TA, RA', and RB register information, which is sent during transmit conversion period A, is applied to
receive conversion period A. Otherwise, this information is applied during receive conversion period B. If RA,
RA', and RB register information has already been received and is being applied during an ongoing conversion
period, any subsequent RA, RA', or RB information that is received during this receive conversion period is
disregarded (see Figure 4).
l-.n-;.I--...,I .......n-~--.,I ......n--;.I--...,~
t1
FSX
Trsnsmlt
..
~--- Conversion
Period A
~
Transmit
Conversion
Period B
Period A
-t+.----
Period C
I
F S R I,,__-'
+- R_lve Conversion
Transmit
----1~
...
'I---- Converalon -----...~
R_lve Conversion Period B ----~~
Figure 4. Receive and Transmit Periods for Primary and Secondary Data
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75265
4-49
TLC32044C, TLC.32044E,· TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
'
SLAS017F - MARCH 1988 ~ REVISED MAY 1995
test modest
.
I
.
The TLC32044 or TLC32045 can be operated in special test modes. These test modes are used by Texas
Instruments to facilitate testing of the device during manufacturing. They are not intended to be used in real
applications, however, they allow the filters in the AID and D/A paths to be used without using the AID and D/A
converters.
.
In normal operation, the nonusable (NU) terminals are left unconnected. These NU terminals are used by the
factory to speed up testing of the TLC32044 or TLC32045 analog interface circuits (AIC). When the device is
used in normal (non-test mode) operation, the NU terminal (terminal 1) has an internal pulldown to.-5 V.
Externally connecting 0 V or 5 V to terminal 1 puts the device in test-mode operation. Selecting one of the
possible test modes is accomplished by placing a particular voltage on certain terminals. A description of these
modes is provided in Table 2 and Figures 5 and 6.
Table 2. List of Test Modes
TEST
TERMINALS
D/A PATH TEST (TERMINAL 1 to 5 V)
AID PATH TEST (TERMINAL 1 to 0)
TEST FUNCTION
TEST FUNCTION
5
The low-pass switched-capacitor fiiler clock is brought out to The bandpass switched-capacitor filter clock is brought oUt to
DR. This clock signal is normally intemal.
DR. Tliis clock signal is normally intemal.
11
No change from normal operation. The EODX signal is The pulse that initiates the AID conversion Is bro~ght out here.
This signal is normally intemal.
brought out to EODX.
3
The pulse that initiates the D/A conversion is brought out here. No change from normal operation. The EODR signal Is
brought out.
27 and 28
There are no test output Signals provided on these terminals. The outputs of the AID path low-pass or bandpass filter
(depending upon control bit d2 -see AIC OX data word format
section) are brought out to these terminals. If the high-pass
section is inserted, the output will heve a (sin xlIx droop. The
slope of the droop is determined by the ADC sampling
frequency, which is the high-pass section clock frequency (see
diagram of bandpass or low-pass filter test for receive section).
These outputs drive small (3O-pF) loads.
15 and 16
D/A PATH LOW·PASS FILTER TEST; (WORD/BYTE) to -5 V
TEST FUNCTION
The inputs of the 0/A path low-pass filter are brought outto terminals 15 and 16. The 0/A input to this filter is removed. If (sin x) / x
correction filter is inserted, the OUT + and OUT -signals have a flat response (see Figure2). The common-mode renge of these
inputs must not exceed ±0.5 V.
t In the test mode, the AIC responds to the setting of WORD/BYTE to -5 V, as If WORD/BYTE were set to 0 V. Thus, the byte mode IS selected
for communicating between DSP and AIC. Either olthe path teSts (D/A or AID) can be performed simultaneously with the 0/A low-pass filter test.
In this situation, WORD/BYTE must be connected to -5 V, which initiates byte-mode communications.
~1ExAs .
4-50
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988- REVISED MAY 1995
Terminal 27 (positive)
Terminal 28 (negatlve)t
Test Control
(terminal 1 at 0 V)
Filter
1--+---1 M
........- t _ - I
AID
Ul-~
X
Figure 5. Bandpass or Low-Pass Filter Test for Receiver Section
Filter
H .....- - I
t--L
M
1-. .-4--1 U 1-+--1
•
X
DIA
~i-- Test Control
(terminal 13 at -5 V)
Terminal 16 (positive)
Terminal 15 (negatlve)t
Figure 6. Low-Pass Filter Test for Transmit Section
t All analog signal paths have differential architecture and hence have positive and negative components.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-61
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vcc+ (see Note 1) ............................................ -0.3 V to 15 V
Supply voltage range, Voo ......................................................... -0.3 V to 15 V
Output voltage range, Va ..........................................•............... -0.3 V to 15 V
Input voltage range, VI .................•..................................•........ -0.3 V to 15 V
Digital ground voltage range ............................................ ;........... -0.3 V to 15 V
Operating free-air temperature range: TLC32044C, TLC32045C .......•.•............... O°C to 70°C
TLC32044E ................................... -20°C to 85°C
TLC320441, TLC320451 ......................... -40°C to 85°C
TLC32044M ............•.................... -55°C to 125°C
Storage te,mperature range: TLC32044C, I, TLC32045C, I' ..............••...•....•. -40°C to 125°C
TLC32044M ......................................... -65°C to 150°C
Case temperature for 10 seconds: FN or FK package ......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ...•................. 260°C
J package ......•.............. 300°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
,implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values for maximum ratings are with respect to VCC-.
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC+ (see Note 2)
4.75
5
5.25
V
Supply voltage, VCC- (see Note 2)
-4.75
-5
-5,25
Digital supply voltage, VDD (see Note 2)
4.75
Digital ground voltage with respect!o ANLG GND, DGTL GND
High-level input voltage, VIH
V
V
300
0
Load capacitance at OUT + and/or OUT -, CL
100
MSTR CLK frequency (see Note 4)
0.075
Analog input amplifier common mode Input voltage (see Note 5)
5
pF
10.368
MHz
±1.5
AID or D/A conversion rate
V
20
TLC32044C,TLC32045C
Operating free-air temperature, TA
V
VOD+0.3
0.8
-0.3
Load resistance at OUT + and/or OUT -, RL
V
4
2
Low-level input voltage, VIL (see Note 3)
V
0
2
Reference input voHage, Vref(ext) (see Note 2)
V
5.25
5
0
-20
70
TLC32044E
TLC32044I, TLC320451
-40
85
TLC32044M
-55
125
kHz
85
·C
,
.
NOTES: 2. Voltages at analog Inputs and outputs, REF, VCC +, and VCC- are With respect to the ANLG GND terminal. Voltages atdlgitallnputs
and outputs and VDD are with respect to the DGTL GND terminal.
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for
logic voHage levels and temperatura only.
4. The bandpass swltched-capacitor filter (SCF) specifications apply only when the low-pass section SCF clock is 288 kHz and the
high-pass section SCF clock is 8 kHz. If the low-pass SCF clock is shifted from 288 kHz, the lOW-pass roIl-off frequency will shift by
the ratio of the low-pass SCF clock to 288 kHz. If the high-pass SCF is shifted from 8 kHZ, the high-pass roll-off frequency will shift
by the ratio olthe high-pass SCF clock to 8 kHz. Similarly, the low-pass switched-capacitorfilter (SCF) specifications apply only when
the SCF clock is 288 kHz. If the SCF clock Is shifted from 288 kHz, the low-pass roIl-off frequency will shift by the ratio of the SCF
clock 10 288 kHz.
5. This range applies when (IN + -IN-) or (AUX IN +.:.. AUX IN-) equals ± 6 V.
~1ExAs
4-52
INSTRUMENTS'
POST OFFICE BOX 665303 • !>ALIAS. TEXAS 75265
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
electrical characteristics over recommended operating free-air temperature range, Vcc+
Vcc- -5 V, Vee 5 V (unless otherwise noted)
=
=
= 5 V,
total device, MSTR ClK frequency = 5.184 MHz, outputs not loaded
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
Voo = 4.75 V.
IOH = -300 IlA
VOL
Low-level output voltage
VOO =4.75V.
IOL=2mA
ICC+
Supply current from VCC+
ICC-
Supply current from VCC-
100
Supply current from VOO
Vref
Internal reference output voltage
MIN
TYpt
MAX
2.4
V
0.4
TLC32044C.TLC32045C
35
TLC320441. TLC320451,
TLC32044E.TLC32044M
40
TLC32044C.TLC32045C
-35
TLC320441, TLC320451,
TLC32044E.TLC32044M
-40
TLC3204xC. E. I
TLC32044M
TLC32044M
mA
7
fMSTR CLK = 5.184 MHz
TLC3204xC. E, I
UNIT
8
3
3.3
2.9
3.3
V
~Vref
Temperature coefficient of internal reference voltage
200
ppmfOC
ro
Output resistance at REF
100
kO
receive amplifier input
PARAMETER
TEST CONDITIONS
AID converter offset error (filters in)
TYPt
MAX
TLC32044C. E. I
10
70
TLC32044M
10
85
TLC32045C, I
10
75
TLC3204xC. E. I
CMRR
Common-mode rejection ratio at IN+.IN-. or
AUX IN+. AUX IN-
'i
Input resistance at IN+.IN-. or AUX IN+. AUX IN-. REF
See Note 6
TLC32044M
MIN
55
35
UNIT
mV
dB
55
100
kn
transmit filter output
PARAMETER
TYPt
MAX
/ TLC3204xC. E. I
TEST CONDITIONS
15
80
/TLC32044M
15
75
VOO
Output offset voltage at OUT + OUT (single-ended relative to ANLG GNO)
YOM
Maximum peak output voltage swing across RL at OUT + or OUT (single ended)
YOM
Maximum peak output voltage swing between OUT + and OUT (differential output)
RL~300n.
Offset voltage = 0
RL~600n
MIN
UNIT
mV
±3
V
±6
t All tYPical values are at TA = 25°C.
NOTE 6: The test condition is a O-W
>58:1:
VI_ -12 dB to-6 dB
58
>58:1:
VI--18dBto-12dB
58
56
58
58
VI_ -24 dB to -18 dB
50
56
VI - -30 dB to -24 dB
44
50
58
56
VI - -36 dB to -30 dB
38
44
VI- -42 dB to-36 dB
32
38
50
44
38
VI - -48 dB to -42 dB
26
32
VI - -54 dB to -48 dB
VI = -6 dB to -0.5 dB
20
26
32
58
>58:1:
>58:1:
VI--12dBto-6dB
VI_-18 dBto-12 dB
58
56
58
>58:1:
58
58
VI_ -24 dB to -18 dB
50
56
58
VI - -30 dB to -24 dB
44
50
56
VI - -36 dB to -30 dB
VI - -42 dB to -36 dB
44
38
32
50
44
VI - -48 dB to -42 dB
38
32
26
VI - -54 dB to -48 dB
20
26
VI--6dBto-0.1 dB
55
>55i
38
32
>55:1:
VI--12 dB to-6 dB
55
55
>55:1:
VI--18 dBto-12 dB
VI_ -24 dB to-18 dB
53
47
55
55
53
55
VI • -30 dB to -24 dB
41
47
53
VI - -36 dB to -30 dB
41
47
VI - -42 dB to -36 dB
.35
29
35
41
VI • -48 dB to -42 dB
23
29
35
VI - -54 dB to -48 dB
17
23
29
t ""' is the programmable gain of the input amplifier.
UNIT
dB
:I: A value >60 is over range and signal clipping occurs.
NOTE 7: The test condition VIiS a 1-kHz Input signal with an 8-kHz conversion rate (0 dB relative to Vref). The load impedance for the DAe is
600 Q (300 Q for TLC32044M).
~1ExAs
INSTRUMENTS
POST OFACE BOX 865303 • DAUAS. TEXAS 75265
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
D/A channel slgnal-to-distortion ratio (see Note 7)
TEST CONDITIONS
PARAMETER
DfA channel signal-to-distortion ratio, TLC32044C, TLC32044E, TLC320441,
TLC32044M
\
DfA channelsignal-to-distortion ratio, TLC32045C: TLC320451
58
VI = -12 dB to-6 dB
58
VI =-18dBto-12dB
56
VI =-24dBto-18dB
50
VI = -30 dB to -24 dB
44
VI = -36 dB to -30 dB
38
VI = -42 dB to -36 dB
32
VI = -48 dB to -42 dB
26
VI = -54 dB to -48 dB
20
VI = -6 dB to 0 dB
55
VI =-12dBto-6dB
55
VI =-18dBto-12dB
53
VI = -24 dB to -18 dB
47
VI =-30 dBto-24dB
41
=-36 dB to -30 dB
35
VI - -42 dB to -36 dB
29
VI= -48 dB to -42 dB
23
VI = -54 dB to -48 dB
17
VI
..
MIN
VI = -6 dB to 0 dB
MAX
UNIT
dB
NOTE 7: The test condition VIIS a 1-kHz Input signal with an 8-kHz conversion rate (0 dB relative to Vretl. The load Impedance for the DAC IS
6000 (3000 for TLC32044M).
gain and dynamic range
PARAMETER
TYPt
MAX
UNIT
-48-dB to O-dB signal range, See Note 8
±0.05
±0.15
dB
Absolute transmit gain tracking error while transmitting
Into 300
TLC32044M
-48-dB to O-dB signal range, TA = 25°C,
See Note 8
±0.05
±0.25
dB
Absolute transmit gain tnicking error while transmitting
into 300
TLC32044M
-48-dB to O-dB signal range,
TA = -55°C to 125°C; "
See Note 8
±0.4
dB
Absolute receive gain tracking error
-48-dB to O-dB signal range, See Note 8
±0.05
±0.15
dB
Absolute receive gain tracking error, TLC32044M
-48-dB to O-dB signal range, TA = 25°C,
See Note 8
±0.05
±0.25
dB
Absolute receive gain tracking error, TLC32044M
-48-dB to O-dB signal range,
TA = -55°C to 125°C,
See Note 8
±0.4
dB
Absolute gain of the AID channel
Signal input is a -O.5-dB,
1-kHz sinewave
0.2
Absolute gain of the DfA channel
Signal input is a O-dB,
1-kHz sinewave
-0.3
n.
n.
t All typical values are at TA = 25°C.
NOTE 8: Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to Vref).
~TEXAS
INSTRUMENTS
4-56
MIN
TEST CONDITIONS
Absolute transmit gain tracking error while transmitting
into 600 0
POST,OFFICE"BOX 655303 • DALLAS, TEXAS 75265
.'
dB
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
power supply rejection and crosstalk attenuation
PARAMETER
TEST CONDITIONS
VCC + or VCC- supply voltage rejection f-Oto30kHz
ratio, receive channel
f - 30 kHz to 50 kHz
Vee + or VCC- supply voltage rejection f_Ot030kHz
ratio, transmit channel (single ended)
f - 30 kHz to 50 kHz
Crosstalk attenuation,
transmit-to-receive (single ended)
MIN
MAX
UNIT
45
30
Idle channel, supply signal at 200 mV
p-p measured at OUT +
45
TLC3204xC, E, I
dB
80
TLC32044M
Crosstalk attenuation, receive-to-transmit, TLC32044M
TYPt
30
Idle channel, supply signal at 200 mV
p-p measured at DR (ADC output)
65
Inputs grounded,
Gain-l,2,4
80
65
t All typical values are at TA - 25°C.
-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75266
4-57
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988- REVISED MAY 1995
delay distortion
bandpass filter transfer function, SCF fclock
PARAMETER
Filter gain,
TlC32044C,
TlC32044E,
TlC320441
Filter gain,
TlC32044M
Filter gain,
TlC32045C,
TlC320451
TEST CONDITIONS
Input signal reference to 0 dB
Input signal relerence to 0 dB
Input signal relerence to 0 dB
=288 kHz IN + - IN -Is a ±3 V slnewavet (see Note 9)
FREQUENCY RANGE
ADJUSTMENT ADDEND:!:
1:550 Hz
Kl xOdB
MIN
TYP§
MAX
-33
-29
-25
1=100Hz
Kl x-0.26dB
-4
-2
-1
1.150 Hz to 3100 Hz
Kl xOdB
-0.25
0
0.25
1= 3100 Hz to 3300 Hz
Kl xOdB
-0.3
0
0.3
I = 3300 Hz to 3650 Hz
Kl xOdB
-0.5
0
0.5
1-3800 Hz
Kl x2.3dB
-3
-1
1= 4000 Hz
Kl x2.7dB
-17
-16
1~4400Hz
Kl x 3.2 dB
f~5000
Kl xOdB
Hz
-40
-65
-33
-29
-4
-2
-1
-0.25
0
0.25
-0.3
0
0.3
-0.5
0
0.5
Kl x2.3dB
-3
-0.5
1=4000 Hz
Kl x2.7dB
-17
-16
1~4400
Hz
Kl x3.2dB
1~5000
Hz
Kl xOdB
1:550 Hz
Kl xOdB
1=100Hz
Kl x-0.26dB
1= 150 Hz to 3100 Hz
Kl xOdB
1- 3100 Hz to 3300 Hz
Kl xOdB
1= 3300 Hz to 3500 Hz
Kl xOdB
1= 3800 Hz
-25
dB
-40
-65
1:550 Hz
Kl xOdB
I-100Hz
Kl x-0.26dB
1= 150 Hz to 3100 Hz
Kl xOdB
1= 3100 Hz to 3300 Hz
Kl xOdB
-0.3
0
0.3
I = 3300 Hz to 3650 Hz
Kl xOdB
-0.5
0
0.5
-33
-29
-4
-2
-1
-0.25
0
0.25
-25
f= 3800 Hz
Kl x2.3dB
-3
-1
1= 4000 Hz
Kl x2.7 dB
-17
-16
1~4400
Hz
Kl x3.2dB
-40
1~5000
Hz
Kl xOdB
-65
t See filter curves in typical characteristics
:I: The MIN, TYP, and MAX specifications are given
UNIT
.
lor a 288-kHz SCF clock Irequency. A slight error in the 288-kHz SCF may result Irom
inaccuracies in the MSTR ClK Irequency, resulting Irom crystal Irequency tolerances. II this Irequency error is less than 0.25%, the
ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications, where Kl = 100 '[(SCF frequency - 288 kHz) 1288 kHzl.
For errors greater than 0.25%, see Note 8.
§ All typical values are at TA = 25°C.
NOTE 9: The Iilter gain outside of the passband is measured with respect to the gain at 1 kHz. The filter gain within the passband is measured
with respect to the average gain within the passband. The passbands are 150to 3600 Hz and 0 to 3600 Hz lor the bandpass and low-pass
filters respectively. For switched-capacitor Ii Iter clocks at Irequencies other than 288 kHz, the Iilter response is shifted by the ratio 01
switched-capacitor filter clock frequency to 288 kHz.
~TEXAS
4-58
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
low-pass filter transfer functlont, SCF fclock
PARAMETER
Filter gain,
TLC32044C,
TLC32044E,
TLC320441
Filter gain,
TLC32044M
Filter gain,
TLC32045C,
TLC320451
Input signal reference is 0 dB
MIN
TYP§
MAX
Kl xOdB
-0.25
0
0.25
FREQUENCY RANGE
Input signal reference is 0 dB
ADJUSTMENT ADDEND*
f z 3100 Hz to 3300 Hz
Kl xOdB
-0.3
0
0.3
f ~ 3300 Hz to 3650 Hz
Kl xOdB
-0.5
0
0.5
f-3800 Hz
Kl x2.3dB
-3
-1
=4000 Hz
Kl x2.7dB
-17
-16
f
Input signal reference is 0 dB
=288 kHz (see Note 9)
f~OHzto3100Hz
TEST CONDITIONS
f~4400 Hz
Kl x3.2 dB
f:::5000 Hz
Kl xOdB
f~OHzto3100Hz
Kl xOdB
-0.25
0
0.25
f = 3100 Hz to 3300 Hz
Kl xOdB
-0.3
0
0.3
f _ 3300 Hz to 3500 Hz
Kl xOdB
-0.5
0
0.5
f=3800 Hz
Kl x2.3dB
-3
-0.5
f=4oo0 Hz
Kl x ,2.7 dB
-17
-16
-40
-65
f~4400
Hz
Kl x 3.2 dB
f~5000
Hz
Kl xOdB
f~OHzt03100Hz
Kl xOdB
-0.25
0
0.25
f
z
3100 Hz to 3300 Hz
Kl xOdB
-0.3
0
0.3
f
z
3300 Hz to 3650 Hz
K1 xOdB
-0.5
0
0.5
dB
-40
-65
f= 3800 Hz
K1 x2.3dB
-3
-1
f. 4000 Hz
K1 x2.7dB
-17
-16
f~4400Hz
K1 x 3.2 dB
-40
f~50oo
K1 xOdB
-65
Hz
UNIT
t
See filter curves in typical characteristics
:j:The MIN, TYP, and MAX specifications are given for a 288-kHz SCF clock frequency. A slight error in the 288-kHz SCF may result from
inaccuracies in the MSTR CLK frequency, resulting from crystal frequency tolerances. If this frequency error is less than 0.25%, the
ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications, where Kl = 100 ·[(SCF frequency - 288 kHz) /288 kHz).
For errors greater than 0.25%, see Note 8.
§ All typical values are at TA = 25°C.
NOTE 9: The filter gain outside of the passband is measured with respect to the gain at 1 kHz. The filter gain within the passband is measured
with respect to the average gain within the passband. The passbands are 150to 3600 Hz and Ot03600 Hz forthe bandpass and low-pass
filters respectively. For switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted by the ratio of
switched-capacitor filter clock frequency to 288 kHz.
serial port
PARAMETER
t
TEST CONDITIONS
VOH
High-level output voltage
IOH - -300
VOL
Low-level output voltage
IOL-2mA
II
Input current
IJA
MIN
TYpt
MAX
2.4
UNIT
V
0.4
V
±10
IJA
Ci
Input capacitance
15
pF
Co
Output capacitance
15
pF
All typical values are at TA = 25°C.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
4-59
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988- REVISED MAY 1995
operating characteristiCs over recommended operating free-air temperature range, Vcc+ = 5 V,
Vcc-= -5 V, VDD = 5 V
noise (measurement Includes low-pass and bandpass switched-capacitor filters)
PARAMETER
TEST CONDITIONS
MIN
TYpt
TLC32044C, E, I
TLC32044M
Transmit noise
With sin xIx correction
OX input ~ 00000000000000,
constant Input code
TLC32044M '
TLC32045C, I
600
..,.Vrms
325
425
..,.Vrms
325
450
..,.Vrms
Without sin xIx correction
450
TLC32044C, E, I
18
TLC32045C, I
Receive noise
(see Note 10)
300
Inputs grounded, gain. 1
TLC32044C, E, I, M
TLC32045C, I
..,.Vrms
dBmcO
24
TLC32044C, E, I, M
TLC32045C, I
UNIT
550 ..,.Vrms
575 ..,.Vrms
TLC32045C, I
TLC32044C, E, I
MAX
dBmcO
500
530
..,.Vrms
..,.Vrms
18
dBmcO
24
dBmcO
t All typical values are at TA _ 25°C.
NOTE 10: The noise is computed by statistically evaluating the digital output of the AID converter.
timing requirements
serial port recommended Input signals
Ie(MCLK)
LMaster clock cycle time
I Master clock cycle time, TLC32044M
tr(MCLK)
Mastar clock rise time
tf(MCLK)
Master clock fall time
tsu(DX)
MIN
MAX
95
100
192
10
ns
ns
ns
10
ns
Master clock duty cycle
25%
75%
Master clock duty cycle, TLC32044M
42%
58%
RESET pulse duration (see Note 11)
800
.\ OX setup time before SCLKJ.
I OX setup time before SCLKJ., TLC32044M
UNIT
ns
20
ns
28
ns
OX hold time after SCLKJ.
ns
th(DX)
Ie(SCLKl/4
..
NOTE 11: RESET pulse duration IS the amount of time that the reset pin IS held below 0.8 V after the power supplies have reached their
recommended values.
.
.
~1ExAs
4-60
INSTRUMENTS
POST OFFICE BOX 6S6303 • DAlLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
serial port - AIC output signals
. TEST CONDITIONS
MIN
TYPt
MAX
380
UNIT
Ic(SCLK)
Shift clock (SCLK) cycle time
tf(SCLKI
Shift clock (SCll<) fall time
50
ns
tr(SClK)
Shift clock (SCLI<) rise time
50
ns
Shift clock (SCLK) duty cycle
ns
45
55
%
52
ns
Id(CH-FLI
Delay from SCLKt to FSR/FSXJ.
CL=50pF
Id(CH-FHI
Delay from SCLKt to FSRI FSX t
Cl = 50 pF
52
ns
Id(CH-DR)
DR valid after SCLKt
90
ns
ldiCH-ELl
Delay from SCLKt to EODXI EODRJ. in word mode
90
ns
Id(CH-EHI
Delay from SCLKt to EODXI EODRt in word mode
90
ns
tf(EODXI
EODX fall time
15
ns
tf(EODR)
EODR fall time
15
ns
Id(CH-ELI
Delay from SClKt to EODXI EODRJ. in byte mode
100
ns
Id(CH-EHI
Delay from SCLKt to EODXI EODRt in byte mode
100
Id(MH-SL)
Delay from MSTR ClKt to SCLKJ.
65
ns
Id(MH-SH)
Delay from MSTR CLKt to SClKt
65
ns
ns
serial port - AIC output signals, TLC32044M
MIN
TYpt
MAX
UNIT
Ic(SCLKI
Shift clock (SCLK) cycle time
tf(SCLK)
Shift clock (SCLK) fall time
50
ns
tr(SCLI<)
Shift clock (SCLK) rise time
50
ns
Shift clock (SCLK) duty cycle
50
Id(CH-FLI
Delay from SCLKt to FSRI FSX J.
400
ns
%
260
ns
Id(CH-FH)
Delay from SCLKt to FSRI FSX t
260
ns
IdCCH-DRl
DR valid afterSCLKt
316
ns
Id{CH-Ell
Delay from SCLKt to EODX/EODRJ. in word mode
280
ns
Id(CH-EHI
Delay from SCLKt to EODXI EODRt in word mode
280
ns
tf(EODX)
EODX fall time
15
ns
tf{EODRI
EODR fall time
15
ns
Id(CH-ELI
Delay from SCLKt to EODXI EODRJ. in byte mode
100
ns
Id(CH-EH)
Delay from SCLKt to EODXI EODRt in byte mode
100
ns
Id(MH-8Ll
Delay from MSTR CLKt to SCLKJ.
65
ns
Delay from MSTR CLKt to SCLKt
Id(MH-SHI
t Typical values are at TA = 25°C.
65
ns
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-61
TLC32044C, TLC32044E j TLC320441, TLC32044M,TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
Table 3. Gain Control Table (Analog Input Signal Required for Full-Scale AID Conversion)
INPUT CONFIGURATIONS
Differential con!iguratlon
Analog input -IN+ -IN_AUX IN+-AUX IN-
Single-ended configuration
Analog input =IN + - ANLG GND
- AUX IN+ - ANLG GND
CONTROL REGISTER B.ITS
d6.
1
d7
0
0
ANALOGINPUT*
AID CONVERSION
RESULT
±6V
FUll-scale
1
1
0
±3V
Full-scale
0
1
±1.5V
Full-scale
1
1
0
1
0
±.3V
Half-scale
0
±3V
Full-sale
0
1
±1.5 V
Full-scale
:j: In this example, Vref IS assumed to be 3 V. In order to minimize distortion, it is recommended that the analog Input not exceed 0.1 dB below full
scale.
Rfb
Rfb
I--.--}
R
IN + -'III/'Ir"""""4t--1
IN - -'III/'Ir"""""4t--1
R
I--.--}
R
AUX IN + -'III/'Ir"""""4t--1
To Multiplexer
AUX IN- -'VV'.......-t-.!
To Multiplexer
R
Rfb
Rfb
Rfb=Rford6=1,d7=1
d6=0,d7=0
Rfb = 2R for de = 1, d7 = 0
Rfb= 4R ford6 =0, d7 = 1
Rfb = R for d6 = 1, d7 =-1
d6=O,d7=0
Rfb =2R ford6= l,d7 = 0
Rfb =4Rford6= 0, d7= 1
Figure 7.IN+ and IN-Gain Control Circuitry
FigureS. AUX IN+ and AUX INGain Control Circuitry
(sin x)/x correction
The Ale does not have (sin x)/x correction circuitry after the digital-to-analog converter. (Sin x)/x correction can
b~ accomplished easily and efficiently in digital signal processor (DSP) software. Excellent correction accuracy
can be achieved to a band edge of 3000 Hz by using a first-order digital correction filter. The results, which are
shown in Table 4, are typical of the numerical correction accuracy that can be achieved for sample rates of
interest. The filter requires only seven instruction cycles per sample on the TMS(SMJ)320 DSPs. With a 200-ns
instruction cycle, nine instructions per sample represents an overhead factor of 1.4% and 1.7% for sampling
rates of 8000 Hz and 9600 Hz, respectively. This correction adds a slight amount of group delay at the upper
edge of the 300-3000-Hz band.
~1ExAs
INSTRUMENTS
4-62
POST OFACE BOX 656303 • DALLAS. TEXAS 75265
/
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995
(sin x)/x roll-off for a zero-order hold function
The (sin x)/x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for the
various sampling rates is shown in the table below.
I
Table 4. (sin x)/x Roll-Off
sin n fits
n tIts
3000 Hz)
(dB)
20 log
fs (Hz)
(f
=
7200
-2.64
8000
-2.11
-1.44
9600
14400
-0.63
19200
-0.35
The actual AIC (sin x)/x roll-off will be slightly less than the above figures because the AIC has less than a 100%
duty cycle hold interval.
correction filter
To compensate for the (sin x)/x roll-off of the AIC, a first-order correction filter (shown below) is recommended.
J - - - - - - - - - - r - - - . Y ( I + 1)
U(I + 1)
pi
The difference equation for this correction filter is:
yi + 1 = p2(1 -p1) (UI + 1) + p1 yi
where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
IH(f)12
p22 (1-p1)2
1 - 2p1 cos(2 :It f/fs)
+ p1 2
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-63
TLC32044C,TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988- REVISED MAY 1995
correction results
Table 5 shows the optimum p values and the corresponding correction results for 8000-Hz and 9600-Hz
sampling rates.
Table 5. Optimum P Values
1 (Hz)
ERROR (dB)
18=8000 Hz
p1 =-0.14813
p2 = 0.9888
300
-0.099
-0.043
600
900
-0.089
-0.043
-0.054
0
1200
-0.002
0
1500
0.041
0.079
1800
ERROR (dB)
18= 9600 Hz
p1 = -0.1307
p2 =0.9951
0
0.043
2100
0.100
0.043
2400
0.091
0.043
2700
-0.043
-0.102
0
-0.043
3000
.TMS(SMJ)320 software requirements
The digital correction filter equation can be written in state variable form as. follows:
Y=k1 xY+k2xU
Where
k1 = p1
k2 = (1 - p1) x p2
Y =filter state
U = next 1/0 sample
The coefficients k1 and k2 must be represented as 16-bit integers. The SACH instruction (with the proper shift)
yields the correct result. With thfl assumption that the TMS(SMJ)320 processor page pointer and memory
configuration are properly initialized, the equation can be executed in seven instructions or seven cycles with
the following program:
ZAC
LTK2
MPYU
LTAK1
MPYY
APAC
SACH (dma), (shift)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVIS EO MAY 1995
PARAMETER MEASUREMENT INFORMATION
I4---*- te(SCLK)
SHIFTCLK
I O.8V
tcI(CH-FL)~ 14-
\t
FSR, FSX
0.8 V
1 I
1 I
I I
o.av
1
\1
DR ___
1
I
I
tcI(CH-DR)
~D~15~_~~~~:--~D~8-----~~
tsu(DX)
DX
.
I
tcI(CH-FL) ~ 14tcI(CH-FH) ~ 140.8 V\t~___~'/\oj_ _ _ _ _-!"-'=':2v~-
14Jt2V
1 I
I~ ~
I
tcI(CH-FH) ~
~ lot-
01
00
i
i
I
I
__~
Don't Care
~
~OC]0!!:9:X:~>---.!=.!.!:!::':::"---------~--,-- MON OUT
I}--+-.....,~ DOUT (2.
complement)
AUXP
-------1
AUXM
-------1
OUTP
OUTM
"'tJ
Interpolation FII~r
Buflert-H~- FLAG
:D
0
C
c:'
n-I
1-+"''''''' complement)
DIN (2.
ALT DATA
1-+-<"--
FC
FLAG 1
MCLK
SCLK
"'tJ
:D
m
m
<
-
:e
~TEXAS
4-74
INSTRUMENTS
POST OFFICE BOX 655303, • DALLAS. TEXAS 75265
0
1-+-1-+..--
TLC320AD65C
16-81T SIGMA·DELTA STEREO CODEC
XLAS099 - MAY 1995
• Single S-V Power Supply
• Stereo 16-Blt Sigma-Delta Audio Converter
• General Purpose 16-Blt Signal Processing
• Sample Rates from 4 kHz to 48 kHz
• High Current Capacity Output Drivers For
Driving Line Outputs or 32 n Stereo
Headphones
• On-Chip Support Real Time Data
Compression/Decompression For A-Law,
I1-Law, and Adaptive Differential Pulse
Code Modulation-International Multimedia
Association (ADPCM-IMA)
• Differential Architecture
• Register Compatible Functional Upgrade
From AD1848, CS4248, and CS4231
• Fully Independent Analog Input Capture
and Playback Mixing Capability
• Mono Channel Input
• Mono Speaker Driver With 32 n Drive
Capability
• Internal Reference Voltage (Vred
• Supports Little and Big Endlan Formats
• Byte Wide Parallel Port Interface For ISA,
EISA Bus Support
• Full Duplex Transfers With Host PC Using
On-Chip Dual DMA Count Registers
• 8-Blt DMA Data Transfers WIth Host
Utilizing On·Chip Dual 64 Byte FIFOs With
Independent Capture and Playback
Programmable Interrupt Flag Depth
• Stereo Microphone Preampllfier-Unlquely
Mixable In Capture A/D Path
:=w
description
The TLC320AD65C sigma-delta technology audio stereo codec provides 16-bit audio for computer multimedia
applications.
The TLC320AD65C provides upgraded functionality, flexibility, and performance from the 16-bit AD1848,
C54248, and the C54231. Flexible analog mixing for both record and playback paths, provide capability for
either the normal ADC with DAC playback paths or an all analog input to output mixing path without any digital
conversions. This device consists of four synchronous conversion paths. Four stereo inputs and one mono input
are provided. The stereo line outputs are capable of driving 32-0 stereo headphones. The mono channel output
driver is capable of driving a 32-0 speaker. Gain and mixing control and sample rate selections are provided
for maximum flexibility. Additional functions provide digital filtering and on-chip timing and control. The
TLC320AD65C is characterized for operation from O·C to 70·C.
AVAILABLE OPTIONS
O·Cto70·C
PRODUCT PREVIEW Information _ _ prodUCIIIIn tilt _ve or
de81gn ~ 01 dovtIopment. Cha_~III. data and other
apaclllcatlo.. aradellan gools. T_lnstru............ tilt right 10
-at or dI........lIIeie products without notico.
PLASTIC CHIP
CARRIER
(FN)
TLC320AD65CFN
QUAD FLATPACK
(PZ)
TLC320AD65CPZ
~TEXAS
Copyright © 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75265
w
a:
D..
t-
O
::l
C
o
a:
D..
PACKAGE
TA
:;
4-75
TLC320AD65C
16-81T SIGMA-DELTA STEREO CODEC
XLAS099 - MAY 1995
functional block diagram
PWRDWN
XTAL11
XTAL10
XTAL21
XTAL20
Linear, A-Law,
JI.-Law, ADPCM-IMA
"'0
::D
0
C
c:
L_LlNE
L_AU~1
(')
L_MIC
Microphone
Preamp
-I
"'0
::D
m
S
m
L_OUT
=e
L_AUX2
Left
Channel
Mono Channel
M_IN
..
/:-
~1EXAS
4-76
M_OUT
.
.
INSTRUMENTS
POST OFFICE BOX 865303 • DALLAS. TEXAS 75265
5-1
en
"C
CD
_.
()
Q)
."
C
:::s
...o_.
()
:::s
en
5-2
TL7726C, TL77261, TL7726Q
HEX CLAMPING CIRCUITS
SLAS078-
•
•
•
•
•
•
Protects Against Latch-Up
25-mA Current Sink In Active State
Less Than 1-mW Dissipation In Standby
Condition
Ideal for Applications In Environments
Where Large Transient Spikes Occur
Stable Operation for All Values of
Capacitive Load
No Output Overshoot
SEPTEMBER 1993
D OR P PACKAGE
(TOP VIEW)
GN0Da
CLAMP
CLAMP
CLAMP
2
3
4
7
6
5
REF
CLAMP
CLAMP
CLAMP
description
The TL7726C, TL77261, and TL7726Q each consist of six identical clamping circuits that monitor an input
voltage with respect to a reference value, REF. For an input voHage (VI) in the range of GND to < REF, the
clamping circuits present a very high impedance to ground, drawing current of less than 10 J,1A. The clamping
circuits are active for VI < GND or VI > REF when they have a very low impedance and can sink up to 25 mAo
These characteristics make the TL7726C, TL77261, and TL7726Q ideal as protection devices for CMOS
semiconductor devices in environments where there are large positive or negative transients to protect
analog-to-digital converters in automotive or industrial systems. The use of clamping circuits provides a
safeguard against potential latch-up.
The TL7726C is characterized for operation over the temperature range of O°C to 70°C. The TL77261 is
characterized for operation over the temperature range of -25°C to 85°C. The TL7726Q is characterized for
operation over the temperature range of -40°C to 125°C.
AVAILABLE OPTIONS
OPERATING
TEMPERATURE
RANGE
DEVICE
PACKAGE
0·C-700C
TLn26CD
8-plnSO
0·C-70·C
TL7726CP
8-pin DIP
-25·C-85·C
TLn261D
8-pinSO
-25·C-85·C
TL7726IP
8-pin DIP
-400C -12500
TL77260D
8-pinSO
-400C -12500
TL77260P
8-pln DIP
====-..-._nat_.,_
PRODUcmoN
......
__ ..........-,.,l1li_01,...._
DATA _ _ . . . . . . . . 01
~
_
:'IlExAs
INSTRUMENTS
POST OFFICE BOX 666303 • DAlLAS. TEXAS 75286
Copy~ght
© 1993. Texas Instruments Incorporated
TL7726C, TL77261, TL7726Q
HEX CLAMPING CIRCUITS
SLAS078 - 04102, SEPTEMBER 1993
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Reference voltage, Vref ....................................................................... 6 V
Clamping current, 11K ................................................................... ±50 mA
Junction temperature, TJ .................................................................. 150°C
Continuous total dissipation .......................................\. . .. See Dissipation Rating Table
Operating free-air temperature range, TA: TL7726C ............ ; .•....................... O°C to 70°C
TL77261 ................................... -40°C to 85°C
TL7726Q ................................ _40°C to 125°C
Storage temperature range ....................................................... -65°C to 150P C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ..... . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
DISSIPATION RATING TABLE
TA =70°C
POWER RATING
TA =85°C
POWER RATING
5.8mW'oC
460rtlW
374mW
144mW
9.5mW'OC
757mW
615mW
237mW
PACKAGE
TA s; 25°C
POWER RATING
DERATING FACTOR
ABOVE TA s; 25°C
o
728mW
P
924mW
TA =125°C
POWER RATING
recommended operating conditions
MIN
MAX
4.5
5.5
Reference voltage, Vref
Input clamping current, 11K
I VI ~ Vref
25
-25
)VIS;GND
UNIT
V
mA
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIK+
Positive clamp voltage
11=20 mA
Vref
VIK-
Negative clamp voltage
II =20mA
-200
IZ
Reference current
Vref= 5 V
TYPt
MAX
UNIT
Vref+ 2OO
mV
25
Input current
GND S; VI S; 50 mV
50 mVs; VI S; Vref-50 mV
t
mV
60
1
!lA
!lA
!lA
!lA
MAX
UNIT
10
Vref - 50 mV S; VI S; Vref
II
0
-10
-1
All typical values are at TA = 25°C.
switching characteristics specified at TA
PARAMETER
ts
Settling time
=25°C
TEST CONDITIONS
VI (system) = ±13 V,
RI = 600 0,
Measured at 10% to 90%, See Figure 1
~1ExAs
5-4
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MIN
tt< 1 lIS,
30
lIS
TL7726C, TL77261, TLn26Q
HEX CLAMPING CIRCUITS
SLAS078 - 04102. SEPTEMBER 1993
PARAMETER MEASUREMENT INFORMATION
VCC=5V
I
REF
SL-""'
lV'Ir
n- " CLAMP TL7726
600
VI(aystem)
GND
1
TEST CIRCUIT
~----....,----- VIK+
--------
13V - -
---90%
--------
VI (system) OV - -
--------
I
---
I
-r--------T
II
~j+--
95%
--10%
II
~j+-
INPUT WAVEFORM
CLAMP WAVEFORM
Figure 1. Switching Characteristics
IIi
I
VIK_
...: I:=-...: I:=--
II
1
-1 ).IA
-10).IA -100).IA -1 mA-10mA -100mA -
25mA - 100mA
-10mA
-1 mA
- 100).IA
- 10).IA
1).IA
Vref-50mV
50mV
-'
...:: I::"-
J
VIK+
-25mA
GND
Figure 2. Tolerance Band for Clamping Circuit
~TEXAS
INSTRUMENTS
POST OFFICE BOX 656303 • DAllAS. TEXAS 7~
5-5
TL7726C, TL77261, TL7726Q
HEX CLAMPING CIRCUITS
SLAS078 - 04102. SEPTEMBER 1993
APPLICATION INFORMATION
VCC=5V
1
10kn
VI(system)
(Input sIgnal)
11(~m)
-+
VI
..A
T
DevIce to Be
Protected, e.g.,
AID Converter,
MIcroprocessor, etc.
III
1/6
TLn26
-if.1
IZ'
4Vref
Example: If II » II(system), I.e., VI (system) > Vret + 200 mV
where:
II (system) = Input current to the devIce beIng protected
VI (system) = Input voltage to the devIce being protected
then the maximum Input voltage
VI(system)max= Vref + Ilmax(10kC)
= 5 V + 25 mA(10kn)
=5V+250V
=255V
Figure 3. Typical Application
~1ExAs
INSTRUMENTS
,POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TLC04/MF4A-50, TLC14/MF4A-100
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
SLAS021A - NOVEMBER 1986 - REVISED MARCH 1995
• Low Clock-to-Cutoff-Frequency Ratio Error
TLC04/MF4A-SO ... ±0.8%
TLC141MF4A-100 •.• ±1%
• Filter Cutoff Frequency Dependent Only on
External-Clock Frequency Stability
• Minimum Filter Response Deviation Due to
External Component Variations Over Time
and Temperature
• Cutoff Frequency Range From 0.1 Hz
to 30 kHz, VCC± ±2.S V
• 5-V to 12-V Operation
• Self Clocking or TTL-Compatible and
CMOS-Compatible Clock Inputs
• Low Supply-Voltage Sensitivity
• Designed to be Interchangeable With
National MF4-S0 and MF4-100
Ds
o OR P PACKAGE
(TOP VIEW)
ClKIN
ClKR
lS
VCC-
2
3
4
7
6
5
FilTER IN
VCC+
AGND
FilTER OUT
=
description
The TLC04/MF4A-50 and TLC14/MF4A-100 are monolithic Butterworth low-pass switched-capacitor fiiters.
'Each is deSigned as a low-cost, easy-to-use device providing accurate fourth-order low-pass filter functions in
circuit design configurations.
Each fiiter features cutoff frequency stability that is dependent only on the external-clock frequency stability.
The cutoff frequency is clock tunable and has a clock-to-cutoff frequency ratio of 50: 1 with less than ±O. 8% error
for the TLC04/MF4A-50 and a clock-to-cutoff frequency ratio of 100:1 with less than ± 1% error for the
TLC14/MF4A-100. The input clock features self-clocking or TTL- or CMOS-compatible options in conjunction
with the level shift (LS) terminal.
The TLC04C/MF4A-50C and TLC14C/MF4A-100C are characterized for operation from O°C to 70°C. The
TLC0411MF4A-501 and TLC1411MF4A-1001 are characterized for operation from -40°C to 85°C. The
TLC04M1MF4A-50M and TLC14M1MF4A-100M are characterized over the full military temperature range of
-55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
CLOCK-TO-CUTOFF
FREQUENCY RATIO
SMALL OUTLINE
O°Cto 70°C
50:1
100:1
TLC04COIMF4A-50CO
TLC14CO/MF4A-100CO
TLC04CP/MF4A-50CP
TLCl4CP/MF4A-100CP
-40°C to 85°C
50:1
100:1
TLC0410IMF4A-5010
TLC14101MF4A-10010
TLC04IP/MF4A-501P
TLC14IP/MF4A-100IP
-55°C to 125°C
50:1
100:1
TA
(0)
PLASTICOIP
(P)
TLC04MP/MF4A-50MP
TLC14MP/MF4A-100MP
The 0 package IS available taped and reeled. Add the suffiX R to the device type (e.g., TLC04COR/MF4A-5OCOR).
~TEXAS
Copyright © 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-7
TLC04/MF4A-50, TLC14/MF4A-100
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
SLAS021 A- NOVEMBER 1986 - REVISED MARCH 1995
functional block diagram
lS
ClKIN
ClKR
~
_ _ _ _ _ _..J
FilTER IN
Butt.worth
6
Fourth-Order
AQND - " - - - - - - - - - - - 1 low-Pass Filter
t---,5... FilTER OUT
Terminal Functions
TERMINAL
NAME
AGND
NO.
110
DESCRIPTION
6
I
Analog ground. The noninverting input to the operational amplifiers of the Butterworth fourth-order low-pass filter.
ClKIN
1
I
Clock in. ClKIN is the clock input terminal for CM05-compatible clock or self-clocking options. For either option,
lS is at VCC-. For self-clocking, a resistor is connected between ClKIN and ClKR and a capacitor is connected
from ClKIN to ground.
ClKR
2
I
Clock R. ClKR is the clock input for a TTl-compatible clock. For a TTL clock, lS is connected to mldsupply and
ClKIN can be left open, but it Is recommended that it be connected to either VCC+ or VCC-.
FilTER IN
8
I
Filter input
FilTER OUT
lS
5
3
0
I
Butterworth fourth-order low-pass filter output
level shift. lS accommodates the various input clocking options. For CMOS-compatible clocks or self-clocking,
lS is at VCC- and for TTl-compatible clocks, lS is at midsupply.
VCC+
VCC-
7
I
Positive supply voltage terminal
4
I
Negative supply voltage terminal
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TLC04/MF4A·50, TLC14/MF4A·100
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
SLAS021 A- NOVEMBER 1986 - REVISED MARCH 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vcc± (see Note 1) .................................................... ±7 V
Operating free-air temperature range, TA: TLC04C/MF4A-50C, TLC14C/MF4A-1 OOC . . . . .. O°C to 70°C
TLC041/MF4A-501, TLC141/MF4A-100l ........ -40°C to 85°C
TLC04M/MF4A-50M, TLC14M/MF4A-100M .. -55°C to 125°C
Storage temperature range, Tst9 .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds ... . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause pennanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the AGND terminal.
recommended operating conditions
TLC04lMF4A-50
Positive supply voltage, VCC+
Negative supply voltage, VCe-
2.25
6
2.25
6
-6
-2.25
-6
2
0.8
0.8
VCC±-±2.5V
5 1.5 x 106
5 1.5xl06
VCC±- ±5 V
5
2xl06
5
2xl06
0.1
40xl03
0.05
20xl03
70
85
0
-40
70
TLC04I1MF4A-50I, TLC141IMF4A-1001
0
-40
TLC04M/MF4A-50M, TLC14M1MF4A-l00M
-55
125
-55
125
Cutoff frequency, fco (see Note 3)
TLC04C1MF4A-50C, TLC14C/MF4A-l00C
..
UNIT
V
V
V
2
Low-level input voltage, VIL
Operating free-air temperature, TA
MAX
MIN
-2.25
High-level Input voltage, VIH
Clock frequency, fclock (see Note 2)
TLC14/MF4A-100
MAX
MIN
85
V
Hz
Hz
·C
NOTES: 2. Above 250 kHz, the Input clock duty cycle should be 50% to allow the operational amplifiers the maximum time to settle while
processing analog samples.
3. The cutoff frequency is defined as the frequency where the response is 3.01 dB less than the dc gain of the filter.
electrical characteristics over recommended operating free-air temperature range, Vcc+
VCC- -2.5 V, fclock S; 250 kHz (unless otherwise noted)
=
= 2.5 V,
filter section
PARAMETER
Voo
TEST CONDITIONS
TLC04lMF4A-50
MIN
TYP*
Output offset voltage
VOM
Peak output voltage
lOS
Short-circuit oUtput current
MAX
TLC141MF4A-100
MIN
25
VOM+
VOMSource
Sink
RL-l0kn
TA=25·C,
TYP*
50
1.8
2
1.8
2
-1.25
-1.7
-1.25
-1.7
See Note 4
-0.5
-0.5
4
4
MAX
UNIT
mV
V
mA
Supply current
1.2
1.2
2.25
rnA
2.25
ICC
fclock - 250 kHz
* All typical values are at TA = 25·C.
NOTE 4: 10S(source) is measured by forcing the output to its maximum positive voltage and then shorting the output to the VCC- terminal.
10S(sink) is measured by forcing the output to its maximum negative voltage and then shorting the output to the VCC+ terminal.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-9
TLC04/MF4A-SO, TLC14/MF4A-100
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
SLAS021A-NOVEMBER 1986-REVISED MARCH 1995
electrical characteristics over recommended operating free-air temperature range, VCC+ = 5 V,
VCC- = -5 V, fclock :S 250 kHz (unless otherwise noted)
filter section
PARAMETER
Voo
TEST CONDITIONS
TLC04lMF4A·50
TYPt MAX
MIN
output offset voltage
YOM
Peak output voltage
lOS
Short-circuit output current
ICC
Supply current
TLC141MF4A·100
MIN
150
VOM+
RL-l0 len
VOMSource
4.3
3.75
4.5
-3.75
-4.1
-3.75
-4.1
-2
-2
5
5
1.8
fclock .. 250 kHz
kSVS Supply voltage sensitivity (see Figures 1 and 2)
MAX
200
3.75
TA=25°C.
See Note 4
Sink
TYpt
3
1.8
-30
UNIT
mV
V
mA
3
-30
mA
dB
t
All tyPical values are at TA _ 25°C.
NOTE 4: 10S(source) is measuredbyforcingtheoutputtoits maximumpositivevoltageandthenshortingtheoutputtothe Vcc_terminaI.IOS(sink)
is measured by forCing the output to its maximum negative voltage and then shorting the output to theVCC+ terminal.
clocking section
MIN
TYpt
MAX
VCC+=10V.
VCC-= 0
6.1
7
8.9
VCC+=5V.
VCC-=O
3.1
3.5
4.4
VCC+= 10V.
VCC-- 0
1.3
3
3.8
VCC+-5 V.
VCC-=O
0.6
1.5
1.9
VCC+_ 1OV•
VCC-= 0
2.3
4
7.6
VCC+=5V.
VCC- .. O
1.2
2
3.8
PARAMETER
VIT+
Positive-going Input threshold voltage
VIT-
Negative-going input threshold voltage
Vhys
Hysteresis voltage (VIT+ - VIT-)
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
CLKIN
VCC= 10V
VCC -5V
VCC-l0V
VCC =5V
Input leakage current
ClKR
VCC-l0V
VCC=5V
VCC-l0V
10
Output current
VCC-5V
VCC=10V
VCC=5V
10 = -10
IIA
1
0.5
2
LS at mldsupply.
TA-25°C
2
ClKR and ClKIN
shortened to VCC-
-3
-7
-0.75
-2
ClKR and ClKIN
shortened to VCC+
3
7
0.75
2
~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • OALLAS. TEXAS 75265
V
V
V
V
4.5
10-1011A
t All typical values are at TA = 25°C.
5-10
9
UNIT
V
IIA
mA
mA
TLC04/MF4A-50, TLC14/MF4A-100
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
SLAS021A- NOVEMBER 1986 - REVISED MARCH 1995
operating characteristics over recommended operating free-air temperature range, Vcc+ = 2.5 V,
Vcc- = -2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Maximum clock frequency, fmax
See Note 2
Clock-to-cutoff-frequency ratio (fclockifco)
fclock S 250 kHz,
Temperature coefficient of clock-to-cutoff
frequency ratio
fclock S 250 kHz
Frequency response above and below
cutoff frequency (see Note 5)
TA=25°C
TLC04lMF4A·50
MIN
TYPt
1.5
3
49.27
50.07
MAX
50.87
TLC141MF4A·100
MIN
TYPt
1.5
3
99
100
MAX
MHz
101
±25
±25
f-6kHz
-7.9
-7.57
-7.1
TA=25°C
f- 4.5 kHz
-1.7
-1.46
-1.3
fco - 5 kHz,
fclock = 250 kHz,
f=3kHz
-7.9
-7.42
-7.1
TA = 25°C
f- 2.25 kHz
-1.7
-1.51
-1.3
24
25
-0.15
0
Dynamic range (see Note 6)
TA=25°C
fclock S 250 kHz
Voltage amplification, dc
fclock S 250 kHz,
Peak-ta-peak clock feedthrough voltage
TA = 25°C
dB
dB
80
RSS2 kn
Hz/Hz
ppm"'C
fco = 5 kHz,
fclock = 250 kHz,
Stop-band frequency attentuation at 2 fco
UNIT
24
25
-0.15
0
78
0.15
dB
dB
0.15
5
5
dB
mV
t All typical values are at TA = 25°C.
NOTES: 2. Above 250 kHz, the input clock duty cycle should be 50% to allow the operational amplifiers the maximum time to settle while
processing analog samples.
5. The frequency responses at f are referenced to a de gain of 0 dB.
6. The dynamic range is referenced to 1.06 V rms (1.5 V peak) where the wideband noise over a 3O-kHz bandwidth is typically
10611V rms for the TLC04/MF4A-50 and 13511V rms for the TLC14/MF4A-l00.
operating characteristics over recommended operating free-air temperature range, VCC+
VCC- -5 V (unless otherwise noted)
=
PARAMETER
TLC04lMF4A-50
TEST CONDITIONS
Maximum clock frequency, fmax
See Note 2
Clock-to-cutoff-frequency ratio (fclock/fco)
fclock S 250 kHz,
Temperature coefficient of clock-ta-cutoff
frequency ratio
fclock S 250 kHz
Frequency response above and below
cutoff frequency (see Note 5)
TA
m
25°C
MIN
TYPt
2
4
49.58
49.98
TLC141MF4A·100
TYPt
MAX
MIN
2
4
50.38
99
100
±15
MAX
-7.9
-7.57
-7.1
f=4.5 kHz
-1.7
-1.44
-1.3
fco = 5 kHz,
fclock = 250 kHz,
TA=25°C
f - 3 kHz
-7.9
-7.42
-7.1
f - 2.25 kHz
-1.7
-1.51
-1.3
TA=25°C
fclock S 250 kHz
Voltage amplification, dc
fclock S 250 kHz,
Peak-to-peak clock feedthrough voltage
TA-25°C
Hz/Hz
ppm/DC
±15
f-6 kHz
Stop-band frequency attentuation at 2 fco
UNIT
MHz
101
feo = 5 kHz,
fclllck = 250 kHz,
TA = 25°C
Dynamic range (see Note 6)
=5 V,
dB
dB
84
86
RSs2kn
24
25
-0.15
0
7
0.15
24
25
-0.15
0
7
dB
dB
0.15
dB
mV
tAli tYPical values are at TA = 25°C.
NOTES: 2. Above 250 kHz, the input clock duty cycle should be 50% to allow the operational amplifiers the maximum time to settle while
processing analog samples.
5. The frequency responses at f are referenced to a dc gain of 0 dB.
6. The dynamic range is referenced to 2.82 V rms (4 V peak) where the wideband noise over a3Q-kHz bandwidth is typically 14211V rms
for the TLC04/MF4A-50 and 17811V rms for the TLC14/MF4A-l00.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-11
TLC04/MF4A-50, TLC14/MF4A-100,
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
SLAS021A- NOVEMBER 1986 - REVISED MARCH 1996
TYPICAL CHARACTERISTICS
FILTER OUTPUT
vs
SUPPLY VOLTAGE VCe. RIPPLE FREQUENCY
o
1
-10
III
'a
_I
1_
1
VCC+ = 5 V + 5O-mV Sine Wave
(0 to 40 kHz)
VCC_=-5V
Filter In at 0 V
'cloCk = 250 kHz
-20
1
1:s-30
o
Iu::
-40
1\
I ,
if
-50
-60 o
5
10
15
20
25
30
35
40
Supply Voltage VCe. Ripple Frequency - kHz
Figure 1
FILTER OUTPUT
vs
SUPPLY VOLTAGE VCC- RIPPLE FREQUENCY
o
VC~+=5~
I
I
I
VCC-= -5 V + 5O-mV Sine Wave
(0 to 40 kHz)
-10 f- Filter In at 0 V ~::"':'::';:;:';:'::L--+_+-_+---I
'clock = 250 kHz
-20r-~--+~~-~-+--+-~r--;
III
'a
1
'5
.& - 30
~
u::
_
1--~"~-+--+----1f---+---+---+----1
1/ l~v--L--I-+--r---r-1
-40 1-~--+--+-~-+--+--I----1
-50r-~--+-~--+-+--+--r--;
-60~~--~--~--~--~--~--~~
o
5
10
15
20
25
30
35
40
Supply Voltege VCC- Ripple Frequency - kHz
Figure 2
~TEXAS
5-12
INSTRUMENTS
POST OFFICE BOX e65303 • DALlAS. TEXAS 75266
TLC04/MF4A-50, TLC14/MF4A-100
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
SLAS021 A- NOVEMBER 1986 - REVISED MARCH 1995
APPLICATION INFORMATION
5V
-----r----------------------,lL-----------,
3
QIT-
CMOS
~~
5V
~V
I
I
I
VCC+
LS
Level Shift
1
CLKIN
--+--4----~
2
8
CLKR
I
I
I
I
I
I
I
I FILTER IN
6
Butterworth
Fourth-Order
Low-Pass Filter
AGND
I
IL _________
VCC_
1---;..........::.5 FILTER
OUT
I
I
_ _ _ _ _ _ _ _ _ _ _ _ .J
4
-5V-~----------~
Figure 3. CMOS-Clock-Driven Dual-Supply Operation
5V - -....- - - - - - - - - - - ,
7
------------,
TTL
CLKR
m-
-5 V _ _ _--=-+-=:..:::..:c:..:....._ _ _ _ _ _...l
OV
6
I
I
Butterworth
Fourth-Order
Low-Pass Filter
AGND
VCC-
5 FILTER
1-----1-.......::.
OUT
I
L----------T4-----------~
-5V
Figure 4. TTL-Clock-Driven Dual-Supply Operation
~lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-13
TLC04/MF4A-50, TLC14/MF4A-100
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED-CAPACITOR FILTERS
SLAS021A-NOVEMBER 1986-REVISEDMARCH 1995
APPLICATION INFORMATION
5V--------------------------~
R
Filter
Input
_+-______..,.-<..:.:=C!..!!.:.____________....,
FILTER
Butterworth
1---"0.:,.UTo---;-'--=-5 Filter
Fourth-Order
Output
r-'~It-""=<--------------__t Low-Pass Filter
6
AGND
L__________ ____________
I
VCC-
.
~
,
4
-5V~~----------------------~
ForVcc= 10V
f I
k1
-l.69RC
COC
Figure 5. Self-Clocking Through Schmitt-Trigger Oscillator Dual-Supply Operation
·~I·~ ThxAs
5-14
NSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75266
TLC04/MF4A·SO, TLC14/MF4A·100
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
SLAS021A- NOVEMBER 1986 - REVISED MARCH 1995
APPLICATION INFORMATION
10V----------.-----------------~
-------------.,
7
g~.g~
lJI-lJI--
1_0_V+-______+--"-+-==='--I
0 V --t--------i-.::....jf--:!='------------....J
See Note A
TTL
CLKR
-5 V
10kO
OV
FILTER IN
(_Note B)
0.
'V
5VOC
6
0.1 j1f
I
Butterworth
Fourth-Order
Low-Paas Filter
AGND
I
VCC-
FILTER
OUT
5
I
I
~---------- 4-------------~
10kO
See NoteC
NOTES: A. The external clock used must be of CMOS level because the clock is input to a CMOS Schmitt trigger.
B. The filter input signal should be dc-biased to midsupply or ac-coupled to the terminal.
C. AGND must be biased to midsupply.
Figure 6. External·Clock·Driven Single-Supply Operation
~TEXAS
INSTRUMENTS
POST OFFICE BOX 856303 • DALLAS. TEXAS 75266
5-15
TLC04/MF4A-50, TLC14/MF4A-100
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR· FILTERS
SLAS021A- NOVEMBER 1986 - REVISED MARCH 1996
APPLICATION INFORMATION
10V
7
r-----~--------------------~
.
Vee..·
R
2
CLKR
'JC
Nonoverlapplng
Clock Generator
10ke
cp1
8
FILTER IN
II
AGND
cp2
Butterworth
Fourth-Order
Low-Peas Filter
FILTER
OUT
~-----~--~-~~-------~--------~
4
10ke
O.1j1f
See Note A
ForVCC=10V
1
fclock =1.68 ftC
NOTE A: AGND must be biased to midsupply.
Figure 7. Self Clocking Through Schmitt-TrIgger Oscillator Single-Supply Operation
~1ExAs
5-16
INS1RUMENTS
POST OFFICE BOX 856303- DALLAS, TEXAS 75266
5
TLC04JMF4A-50, TLC14/MF4A-100
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
SLAS021 A- NOVEMBER 1986 - REVISED MARCH 1995
APPLICATION INFORMATION
5V
r-----------
I
3
Clock Input
VCC+
--------------.,
7
Level Shift
LS
I
I CLKIN
-+-+--=-+-==:=.-ur><>--I
I
1
2
CLKR
I
I
I
I
8
6
10kO
I
I
I
I
FILTERIN
Butterworth
Fourth-Order
Low-Pass Filter
AQND
FILTER
OUT
L___________ ______________
I
I
VCC-
O.11Jf'
5
~
4
-SV ~~~----------------~
Figure 8. DC Offset Adjustment
~1EXAS
INSTRUMENTS
POST OFFICE BOX 656303 • DAUAS. TEXAS 75265
5-17
5-18
TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
1995
SLAS097B
• Voltage-Controlled Oscillator (VCO)
Section:
Complete Oscillator Using Only One
External Bias Resistor (RBIAS)
Lock Frequency:
22 MHz to 50 MHz (Voo = 5 V ±5%,
TA -20°C to 75°C, xi Output)
11 MHz to 25 MHz (Voo 5 V ±5%,
TA -20°C to 75°C, x1/2 Output)
Output Frequency ... xi and xi/2
Selectable
=
=
PWPACKAGEt
(TOP VIEW)
veo Voo
LOGIC Voo
SELECT
VCO OUT
FIN-A
FIN-B
PFD OUT
LOGICGND
=
12
11
BIAS
VCO IN
veo GND
VCO INHIBIT
PFD INHIBIT
NC
---------~Available in tape and reel only and ordered as the
TLC2932IPWLE.
NC - No internal connection
t
• Phase-Frequency Detector (PFD) Section:
High Speed, Edge-Triggered Detector
With Internal Charge Pump
• Independent VCO, PFD Power-Down Mode
• Thin Small-Outline Package (14 terminal)
• CMOS Technology
• Typical Applications:
Frequency Synthesis
Modulation/Demodulation
Fractional Frequency Division
• Application Report Avallablet
• CMOS Input Logic Level
description
The TLC29321 is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlled
oscillator (VCO) and an edge-triggered type phase frequency detector (PFD). The oscillation frequency range
of the VCO is set by an external bhis resistor (RBIAS)' The VCO has a 1/2 frequency divider at the output stage.
The high speed PFD with internal charge pump detects the phase difference between the reference frequency
input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions,
which can be used as a power-down mode. Due to the TLC29321 high speed and stable oscillation capability,
the TLC29321 is suitable for use as a high-performance PLL.
functional block diagram
VCOIN
FIN-A
FIN-B
PFD INHIBIT
4
5
9
Phase
Frequency
Detector
6
BIAS
PFD OUT VCO INHIBIT
12
13
10
2
VoltageControlled
Oscillator
3
VCOOUT
SELECT
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(PW)
-20·C to 75·C
TLC2932IPWLE
t TLC2932 Phase-locked-Loop Building Block With Analog Voltage-Controlled Oscillator and Phase Frequency Detector (SLAA011).
~lEXAS
Copyright © 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 665303 • OALLAS. TEXAS 75265
5-19
TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097B - SEPTEMBER 1994 - REVISED MARCH 1995
Terminal Functions
TERMINAL
NAME
FIN-A
NO.
4
FIN-B
5
LOGICGNO
7
1
LOGICVOO
DESORIPTION
UO
I
Input reference frequency f(REF IN) is applied to FIN-A.
I
Input for VCO extemal counter output frequency f(FIN-B). FIN-B is nominally provided from the external
counter, see functional block diagram.
GNO for the internal logic.
Power supply for the intemal logic. This power supply should be separate from VCO VOO to reduce
cross-coupling between supplies.
NC
PFO INHIBIT
8
9
I
PFD inhibit control. When PFD INHIBIT is high, PFD output Is in the high-Impedance state, see Table 3.
PFDOUT
6
0
PFD output. When the PFO INHIBIT is high, PFO output Is in the high-impedance state.
13
I
Bias supply. An external resistor (RBIAS) between VCO VDD and BIAS supplies bias for adjusting the
oscillation frequency range.
SELECT
2
I
VCO output frequency select. When SELECT is high, the VCO output frequency is x 112 and when low, the
output frequency is x 1, see Table 1.
VCOIN
12
I
VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency.
VCO INHIBIT
10
11
I
VCO inhibit control. When VCO INHIBIT is high, VCO OUT is low (see Table 2).
GNDforVCO.
3
14
0
VCO output. When the VCO INHIBIT is high, VCO output is low.
BIAS
VCOGNO
VCOOUT
VCOVDD
No Intemal connection.
Power supply for VCO. This power supply should be separated from LOGIC VDD to reduce cross-coupIing
between supplies.
detailed description
veo oscillation frequency
The veo oscillation frequency is determined by an external resistor (RBIAS) connected between the veo Voo
aM the BIAS terminals. The OSCillation frequency and range depends on this resistor value. The bias resistor
value for the minimum temperature coefficient is nominally 3.3 kn with 3-V Voo and nominally 2.2 kn with
5-V Voo. For the lock frequency range refer to the recommended operating conditions. Figure 1 shows the
typical frequency variation and veo control voltage.
veo Oscillation Frequency Range
1/2VDD
veo Oontrol Voltage (yCO IN)
Figure 1. veo Oscillation Frequency
~ThxAs
5-20
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SlAS0978 - SEPTEMBER 1994 - REVISED MARCH 1995
veo OUtput frequency 1/2 divider
The TLC29321 SELECT terminal can select between the f080 and 1/2 f08c VCO output frequencies as shown in
Table 1. The 1/2 f080 output should be used for minimum VCO output jitter.
Table 1. VCO Output 1/2 Divider Function
SELECT
VCOOUTPUT
Low
fosc
112f08O
High
VCO Inhibit function
The veo has an externally controlled inhibit function which inhibits the VCO output. A high level on the veo
INHIBIT terminal stops the VCO oscillation and powers down the veo. The output maintains a low level during
the power-clown mode, refer to Table 2.
Table 2. VCO Inhibit Function
VCOINHIBIT
VCO OSCILLATOR
VCOOUTPUT
Low
Active
Active
IDDNCO)
Nonna!
High
Stopped
Low level
Power Down
PFD operation
The PFD is a high-speed, edge-triggered detector with an intemal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN-A and FIN-B as shown in Rgure 2. Nominally the
reference is supplied to FIN-A, and the frequency from the external counter output is fed to FIN-B. For clock
recovery PLL systems, other types of phase detectors should be used.
FIN-A
FIN-B
PFDOUT
Jt--_
I
I
L -_- 4 .l._-I
I I
It---
I
HI-Z
VOL
Figure 2. PFD Function Timing Chart
PFD output control
A high level on the PFD INHIBIT terminal places the PFD output in the high-impedance state and the PFD stops
phase detection as shown in Table 3. A high level on the PFD INHIBIT terminal also can be used as the
power-clown mode for the PFD.
Table 3. VCO Output Control Function
PFDINHIBIT
DETECTION
PFDOUTPUT
Low
Active
Active
IDDIPFDl
Nonna!
High
Stop
Hi-Z
Power Down
~1EXAS
INSTRUMENTS
POST OFFICE BOX _ . DAlLAS, TEXAS 75281i
5-21
TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS097B - SEPTEMBER 1994 - REVISED MARCH 1995
schematics
veo block schematic
BIAS
VCOIN
Bias
Control
VCOOUT
VCOINHIBIT
PFD block schematic
r-charg;~;P-l
I
I
VDD
FIN-A
I
I
I
I
PFDOUT
FIN-B
I
I
I
IL _ _ _ _ _ ___ .JI
PFDINHIBIT
absolute maximum ratingst
Supply voltage (each supply), Voo (see Note 1) •............................................... 7 V
Input voltage range (each input), VI (see Note 1) ............................... -0.5 V to Voo + 0.5 V
Input current (each input), II •............................................................ ±20 rnA
Output current (each output), 10 ...•.•.•........•.•......••.......•........•............. ±20 rnA
Continuous total dissipation, at (or below) TA = 25°C ....................................... 700 mW
Operating free-air temperature range, TA ........................................ .,... -20°C to 75°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ....... . . . . . . . . . . . . . . . . . . . . . . .. 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the devica. These are stress ratings only, and
functional operation of the devica at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network GND.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 5.6 mW/oC.
~TEXAS
5-22
'
INSTRuMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097B - SEPTEMBER 1994 - REVISED MARCH 1995
recommended operating conditions
PARAMETER
Supply voltage, VDD (each supply, see Note 3)
MIN
NOM
MAX
VDD=3 V
2.85
3
3.15
VDD=5V
4.75
5
5.25
Input voltage, VI (inputs except VCO IN)
0
VDD
Output current, 10 (each output)
0
±2
VCO control voltage at VCO IN
Lock frequency (x1 output)
Lock frequency (x1/2 output)
Bias resistor, RBIAS
0.9
VDD
VDD-3V
14
21
VDD=5V
22
50
VDD=3 V
7
10.5
VDD-5V
11
25
VDD=3V
2.2
3.3
4.3
VDD-5V
1.5
2.2
3.3
UNIT
V
V
mA
V
MHz
MHz
kn
NOTE 3: It is recommended thalthe logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) should be althe same voltage
and separated from each other.
electrical characteristics over recommended operating free-air temperature range, Voo
(unless otherwise noted)
=3 V
veo section
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
10H =-2 mA
VOL
Low-level output voltage
IOL=2rnA
VIT
Input threshold voltage at SELECT,
II
Input current at SELECT, VCO INHIBIT
VI = VDD or GND
ZilVCOINI
Input impedance
VCO IN - 1/2 VDD
IDDlINHI
VCO supply current (inhibit)
See Note 4
0.01
1
IlA
IDD(VCO)
VCO supply current
See Note 5
5
15
mA
veo INHIBIT
2.4
V
0.3
0.9
1.5
V
2.1
V
±1
IlA
Mn
10
NOTES: 4. Current into VCO VDD, when VCO INHIBIT = VDD, PFD is inhibited.
5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kn, VCO INHIBIT = GND, and PFD is inhibited.
PFO section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
IOH=-2mA
VOL
Low-level output voltage
IOL=2mA
0.2
V
10Z
High-impedance-state output current
PFD INHIBIT = high,
VI = VDD or GND
±1
IlA
VIH
High-level input voltage at FIN-A, FIN-B
VIL
Low-level input voltage at FIN-A, FIN-B
VIT
Input threshold voltage at PFD INHIBIT
2.7
V
2.7
0.9
V
1.5
0.5
V
2.1
V
Ci
Input capacitance at FIN-A, FIN-B
5
pF
Zi
Input impedance at FIN-A, FIN-B
10
Mn
IDD(Z)
High-impedance-state PFD supply current
See Note 6
0.01
1
IIA
IDD(PFD)
PFD supply current
See Note 7
0.1
1.5
rnA
,NOTES: 6. Current Into LOGIC VDD, when FIN-A, FIN-B = GND, PFD INHIBIT - VDD, no load, and VCO OUT is inhibited.
7. Current into LOGIC VDD, when FIN-A, FIN-B = 1 MHz (VI(PP) _ 3 V, rectangular wave), NC = GND, no load, and VCO OUT is
inhibited.
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-23
TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097B - ,SEPTEMBER 1994 - REVISED MARCH 1995
operating characteristics over recommended operating free.alr temperature range, VDD = 3 V
(unless otherwise noted)
,
VCOsection
fosc
PARAMETER
Operating oscillation frequency
ts(fosc)
Time to stable oscillation (see Note 8)
tr
Rise time
tf
Fall time
TEST CONDITIONS
RBIAS - 3.3 kC, VCO IN - 112 VDD
Measured from VCO INHIBIT.!.
MIN
TYP
MAX
UNIT
15
19
23
MHz
10
jill
CL-15pF,
See Agure3
7
CL=50pF,
CL-15pF,
CL-50pF,
See Figure 3
See Figure 3
14
See Figure 3
10
6
45%
14
12
ns
ns
Duty cycle at VCO OUT
RBIAS • 3.3 kC, VCO IN - 112 VDD,
a(fose)
Temperature coeffIcient of oscillation frequency
RBIAS - 3.3 kC, VCO IN - 112 VDD,
TA .. -2o-C to 75·C
0.04
%/"C
kSVS(fosc)
Supply voltage coefficient of oscillation frequency
RBIAS - 3.3 kC, VCO IN - 1.5 V,
VDD -2.85 Vto 3.15 V
0.02
%lmV
50%
55%
Jitter absolute (see Note 9)
100
ps
RBIAS - 3.3 kO
NOTES: 8. The time period to the stable VCO oscillation frequency after the VCO INHIBIT tennlnai is changed to a low level.
9. The LPF circuit is shown in Figure 28 with calculated values listed In Table 7. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter Specification was made with a carefully designed PCB with no device socket.
PFDsectlon
PARAMETER
fmax
tpLZ
tpHZ
tpZL
tpZH
tr
tf
.,.,..
:lOIaximum opereting frequenCy
PFD output disable. time from low level
PFD output disable time from high level
,PFD output enable time to low level
PFD output enable time to high level
Rise time
Fall time
TEST CONDITIONS
"
-
MIN
,
See Figures 4 and 5 and Table 4
CL-15pF,
See Figure 4
~TEXAS
5-24
,
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75285
TYP
MAX
21
23
50
50
30
UNIT
MHz
20
11
10
2.3
2.1
30
10
10
ns
ns
ns
ns
TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS097B - SEPTEMBER 1994 - REVISED MARCH 1995
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V
(unless otherwise noted)
veo section
TEST CONDITIONS
PARAMETER
VOH
High-level output voltage
IOH=-2mA
VOL
Low-Ievel output voltage
IOL-2rnA
VIT
II
Input threshold voltage at SELECT, VCO INHIBIT
MIN
VI - VOO or GNO
Zi(VCOIN)
Input impedance
IOOIlNHI
VCO supply current (inhibit)
VCOIN - 112 VOO
See Note 4
MAX
UNIT
V
0.5
1.5
Input current at SELECT, VCO INHIBIT
TYP
4
2.5
3.5
V
±1
IJA
10
0.01
VCO supply current
See Note 5
15
IOOIVCOI
NOTES: 4. Current into VCO VOO, when VCO INHIBIT - VOO, and PFO is inhibited.
.
5. Current into VCO VOO. when VCO IN - 1/2 VOO, RBIAS - 3.3 kO, VCO iNHIBIT - GNO, and PFO is inhibited.
V
MO
1
IJA
35
rnA
PFD section
TEST CONDITIONS
PARAMETER
MIN
4.5
TYP
MAX
UNIT
VOH
High-level output voltage
IOH-2rnA
VOL
Low-level output voltage
10Z
Hlgh-impedance-s!ate output current
IOL-2rnA
PFO INHIBIT - high,
VI - VOO or GNO
VIH
High-level Input voltage at FIN-A, FIN-B
VIL
Low-level input voltage at FIN-A, FIN-B
VIT
Ci
Input threshold voltage at PFO INHIBIT
Input capacitance at FIN-A, FIN-B
5
pF
ZI
Input impedance at FIN-A, FIN-B
10
MO
IOO(Z)
High-Impedence-state PFO supply current
V
0.2
V
±1
IJA
4.5
1.5
See Note 6
V
2.5
0.01
1
V
3.5
V
1
IJA
See Note 7
0.15
rnA
3
IOO(PFO) PFO supply current
NOTES: 6. Current Into LOGIC VOO, when FIN-A, FIN-B • GNO, PFO INHI!3IT = VOO, no load, and VCO OUT IS Inhibited.
7. Current into LOGIC VOO, when FIN-A, FIN-B -1 MHz (VI(PP) - 5 V, rectangular wave), PFO INHIBIT. GNO, no load, and
VCO OUT Is inhibited.
.
~1ExAs
INSTRUMENTS
POST OFFICE BOX &55303 • DAlLAS. TEXAS 76266
5-25
TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS097B-SEPTEMBER 1$94- REVISED MARCH 1995
operating characteristics ~ver recommended operating free-air temperature range, VOO
(unless otherwise noted)
=5 V
veo section
PARAMETER
TEST CONDITIONS
fosc
Operating oscillation frequency
tslfosc)
Time to stable oscillation (see Note 8)
tr
Rise time
tf
Fall time
RBIAS =22 leO, VCO IN = 112 VOO
Measured from VCO INHIBIT.J.
MIN
TYP
MAX
UNIT
30
41
52
MHz
10
lIS
CL-15pF,
See Figure 3
5.5
CL=50pF,
CL-15pF,
See Figure 3
See Figure 3
8
5
CL = 50 pF,
See Figure 3
6
Duty cycle at veo OUT
RBIAS - 22 leO, VCO IN .112 VOO,
a(fosc)
Temperature coefficient of oscillation frequency
RBIAS • 22 leO, VCO IN = 1/2 VOO,
TA. -20·C to 75·C
ksVS(fosc)
Supply voltage coefficient of oscillation frequency
RBIAS • 2.2 leO, VCO IN = 2.5 V,
VOO = 4.75 V to 5.25 V
45%
50%
10
10
ns
ns
55%
0.06
%rC
0.006
%/mV
Jitter absolute (see Note 9)
100
ps
RBIAS - 2.2 k.O
NOTES: 8: The time penod to the stable veo oscillation frequency after the VCO INHIBIT terminal IS changed to a low level.
9. The LPF circuit is shown in Figure 28 with calculated values listed In Table 7. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.
PFO section
PARAMETER
TEST CONDITIONS
fmax
Maximum operaling frequency
tpLZ
PFO output disable time from low level
tpHZ
PFO output disable time from high level
tpZL
PFO output enable time to low level
tpZH
PFO output enable time to high level
tr
Rise time
tf
Fall time
TYP
MAX
21
40
20
40
7.3
20
6.5
20
2.3
10
ns
1.7
10
ns
40
See Figures 4 and 5 and Table 4
CL= 15 pF,
See Figure 4
~.ThxAs
INSTRUMENTS .
5-26
MIN
POST OFFICE SOX 855303 • DAlLAS. TEXAS 75265
UNIT
MHz
ns
ns
TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS097B - SEPTEMBER 1994 - REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION
VCOOUT
Figure 3. veo Output Voltage Waveform
j
FIN-At
"
1
1
1
1
1
1
1
1
1
1--1
FIN-Bt
PFDINHIBIT
100/0
I
tPZH
VOD
aND
\..=
I
i4- tr
-----------------
Voo
-------
VDD
aND
50%j
! ~90%
500/0
PFDOUT
- - - - - - voo
aND
~I
500/0J
1
aND
i
~tPHZ
500/0\
aND
\..=
1
1--' /4- tf
J4-*-
'
500/0!_ _ _ _ _
90~ ~O%
------; VOH
I
"
I
I
VDD
aND
1
100/0
I
(a) OUTPUT PULLDOWN
(see Figure 5 and Table 4)
aND
tpLZ
1
VDD
tpZL~
-H
VDD
vOL
(b) OUTPUT PULLUP
(see Figure 5 and Table 4)
t FIN-A and FIN-B are for reference phase only. notfortiming.
Figure 4. PFD Output Voltage Waveform
~lEXAS
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
5-27
TLC29321
HIGH·PERFORMANCE PHASE·LOCKEO'LOOP
SLAS097B-SEPTEMBER 1994-REVISED MARCH 1995
.
PARAMETER MEASUREMENT INFORMATION
Table 4. PFD Output Test Conditions
PARAMETER
RL
eL
T\ b
Teet Point
S1
S2
Open
Close
\
tpZH
tpHZ
tr
tpZL
1 kn
OUT
Close
tpLZ
S1
9
RL
15pF
VOO
I-~PF~O~O~UIT-:--~~~
Open
tf
Figure 5. PFD Output Test Conditions
TYPICAL CHARACTERISTICS
veo OSCILLATION FREQUENCY
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
vs
veo CONTROL VOLTAGE
__
40~---~------~------~
VOO=3V
-200c
RBIAS = 2.2 kn
30r--------r------~~~~~
2Or--------r~~"'--___t---------I
10~=~l---_'_--J
100~--~----~----~---r--~
i
I
VOO=&V
RBIAS = 1.& kn
+----+-----!-----I
80~---+----~----~---+~~
iI
s
~
j
40r----+---7.~~~r----+----4
I
20~~~---+------+----~---~
O~------~------~------~
o
2
3
veo IN - veo Control Voltege -
o
V
FigureS
Figure 7
~1ExAs
5-28
2
INSTRUMENTS
POST OFFICE BOX 665303 • DAllAS. TEXAS 75285
3
6
4
veo IN - veo Control Voltage -
V
· TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097B - SEPTEMBER 1994 - REVISED MARCH 1995
TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
VCO OSCILLATION FREQUENCY
va
va
VCO CONTROL VOLTAGE
VCO CONTROL VOLTAGE
~~--------~----~--~----~
VDD=5V
40
VDD=3V
RBIAS = 3.3 leO
!:E
:E
I
P)-
I
I
-20"C
30
P)-
i::I
r
r
IL
u.
c:
c:
0
i
20
0
I
~
~I
RBIAS = 2.2 leO
!
4O~---+----;-~~~---+----,
~
~I
10
...I
2O~~~----;-----~---+----,
...§
0
0
2
veo IN - VCO Control Voltage - V
O~--~----~----~--~----~
02345
3
veo IN - veo Control Voltage -
Figure 8
Figure 9
VCO OSCILLATION FREQUENCY
VCO OSCILLATION FREQUENCY
va
va
VCO CONTROL VOLTAGE
VCO CONTROL VOLTAGE
80
40
VDD=3V
RBIAS = 4.3 leO
!
:E
i
I
30
P)-
r
~I
60
i::I
~
r
u.
c:
I
I,
VDD=5V
f- RBIAS = 3.3 leO
!:E
I
P)-
V
/. ~
u.
c:
20
0
I
~
~I
10
J
25·C
75·c1
...a
~
P
./~
~
-20·C
0
0
0
2
3
veo IN - veo Control Voltage -
V
Figure 10
2
3
4
veo IN - veo Control Voltage -
5
V
Figure 11
~I
1EXAS
NSIRUMENTS
POST OFFICE BOX 6553ix! • DAlLAS. TEXAS 75266
5-29
TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097B- SEPTEMBER 1994 - REVISED MARCH 1995
TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
vs
BIAS RESISTOR
VCO OSCILLATION FREQUENCY
vs
BIAS RESISTOR
60
30
VOO=3V
veo IN = 1/2 Voo
TA=25·e
N
iI
~
Ii:::I
r
Ii
ag=
I
:IE
I
~
..............
c
0
:z:
25
IL
20
............
VOO=5V
veo IN = 1/2 Voo
TA=25·e
N
Ii:::I
~
IL
50
'"
c
-~
~
15
i'5
40
S
g
i'-...
I
~
J
III
~
10
2
2.5
3
3.5
4
RBIAS - Bias Resistor - kQ
4.5
20
1.5
2.5
3
RBIAS - Bias Resistor - kQ
3.5
Figure 13
TEMPERATURE COEFFICIENT OF
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
0.4
"
2
Figure 12
TEMPERATURE COEFFICIENT OF
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
0.4
VOO=3V
veo IN = 1/2 Voo
TA;; -20·e to 75·e
""- ........
VOO=5V
veo IN = 1/2 Voo
TA = -20·e to 75·e
\.
" 'II. . Y
~
/
2.5
3
3.33.5
4
RBIAS - Bias Resistor - kQ
4.5
Figure 14 .
i'....L ./V
"
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
/
/
/
I
2 2.2
2.5
3
RBIAS - Bias Resistor - kQ
Figure 15
~TEXAS
5-30
~'"
30
3.5
TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS097B - SEPTEMBER 1994 - REVISED MARCH 1995
TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
VCO OSCILLATION FREQUENCY
vs
vs
VCO SUPPLY VOLTAGE
VCO SUPPLY VOLTAGE
48
24
RBIAS = 3.3 kr.l
VCOIN=1.5V
TA = 25°C
N
J:
:I:
I
~
5i
~
IL
:I:
I
22
~
c
:::I
~
IL
C
C
E
I
20
~
8
>
I
44
CD
::I
0
RBIAS = 2.2 kr.l
VCO IN = 1/2 Vee
TA = 25°C
N
J:
40
~
0
~
18
38
I
1;1
1;1
.2
.2
32~----~------~----~------~
16~----~------~----~------~
3.05
3
3.15
Vee - VCO Supply Voltage - V
4.75
Figure 16
Figure 17
SUPPLY VOLTAGE COEFFICIENT OF VCO
OSCILLATION FREQUENCY
0.05
SUPPLY VOLTAGE COEFFICIENT OF VCO
OSCILLATION FREQUENCY
vs
vs
BIAS RESISTOR
BIAS RESISTOR
j
Vee = 2.85 Vto 3.15 V
VCO IN = 1/2 Vee
TA = 25°C
~
g
0.04
Vee = 4.75 V to 5.25 V
VCO IN = 1/2 Vee
TA = 25°C
0.01
'0
..
>
c_
0.03
-.......
0.02
~
.!!~
.!!I
~ I--.....
0.01
o
2
2.5
5.25
5
Vee - veo Supply Voltage - V
3
1~
..........
'"
o 5i
tt
,
IlL
0.005
~
I'---
>-
-
I
I
3.5
4
RBIAS - Bias Resistor - kr.l
4.5
io
;r
0
1.5
Figure 18
2
2.5
3
RBIAS - Bias Resistor - kr.l
3.5
Figure 19
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
5-31
TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097B - SEPTEMBER 19114 - REVISED MARCH 1995
. APPLICATION INFORMATION
RECOMMENDED LOCK FREQUENCY
(x10UTPUT)
va
BIAS RESISTOR
RECOMMENDED LOCK FREQUENCY
(x10UTPUT)
,va
BIAS RESISTOR
30
8O..---.......
---r----r-----.
VDD = 4.75 V to 5.25 V
vDD =2.85 V to 3.15 V
TA = -2O"C to 75°C
TA =-200c to 75°C
I
I
I
I
I
25
I
]
20
]
I
I
151---I---~
10~
2
__
~
__
2.5
~
____
~_~
__
10~
~
3
3.5
4
RIIAS - lias R.lstor - leO
____
1.5
~
____
~
___
~
Figure 21
RECOMMENDED LOCK FREQUENCY
(x1/2 OUTPUT)
RECOMMENDED LOCK FREQUENCY
(x1/2 OUTPUT)
V8
V8
BIAS RESISTOR
BIAS RESISTQR
VDD .4.75 V to 5.25 V
TA = -2OOC to 75°C
SELECT.VDD
VDD=2.85Vto3.15V
TA =-2OOC to 7&OC
SELECT =VDD
I
~
3
2.5
RBIAS - Bias Resistor - leO
Figure 20
15
____
2
I
I
12.&
1
..I
I
10
7.51----+--~
5~
&~--~---~---~-~---..I
2
3
4
RBIAS - BI88 R.Jator - leO
4.5
____
1.5
Figure 22
~
___
~
____
~,TEXAS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75266
____
2
2.5
3
RBIAS - Blaa Resistor - leO
Figure 23
INSTRUMENTS
~
~
3.5
TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097B - SEPTEMBER 1994 - REVISED MARCH 1996
APPLICATION INFORMATION
gain of VCO and PFD
Figure 24 is a block diagaram of the PLL. The
countdown N value depends on the input
frequency and the desired veo output frequency
according to the system application requirements.
The ~ and Kv values are obtained from the
operating characteristics of the device as shown
in Figure 24. Kp is defined from the phase detector
VOL and VOH specifications and the equation
shown in Figure 24(c). Kv is defined from
Figures 8, 9, 10, and 11 as shown in Figure 24(c).
The parameters for the block diagram with the
units are as follows:
Kv : veo gain (radls/V)
Ko: PFD gain (V/rad)
Kf: LPF gain (VN)
i2(S)
Kp • KV
11>1 (s) = N • (Tl + T2)
I
1
+s . T2
'I
I
and the transfer function for frequency is
FOUT(s) _ Kp' KV
. FREF(s) - (Tl + T2)
I
1 + s • T2
2
[
Kp' Kv' T2]
Kp' KV
s + s· 1 + N • (T1+ T2) + N • (T1+ T2)
(1 )
(2)
The standard two pole denominator is 0 =s2 + 2 ~ ron s + ron2 and comparing the coefficients of the denominator
ofequation (1) and (2) with the standard two pole denominator gives the following results.
ron =
Kp' Kv
N • (Tl + T2)
Solving for Tl + T2
Tl
Kp' KV
N· ro n2
+ T2 = -'---;:;
(3)
and by using this value for Tl + T2 in equation (3) the damping factor is
t = ron • (T2 +
N )
Kp' KV
2
solving for T2
T2=2t
N
ro Kp' Kv
then by substituting for T2 in equation (3)
KV·Kp 2t . N
Tl =
--+~~~
N • ro n2 ron Kp' KV
:lllEXAs
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097B - SEPTEMBER 1994 - REVISED MARCH 1995
APPLICATION INFORMATION
From the circuit constants and the initial design parameters then
~
R2 -- [2(On - Kp N
• KV] C1f
~
R1 = [K p • Kv _
+ N ] 1..
(On 2 • N (On Kp. KV Cf
The capacitor, C" is usually chosen between 1 ~F and 0.1 ~ to allow for reasonable resistor values and physical
capacitor size. In this example, C, is chosen to be 1 ~ and the corresponding R1 and R2 calculated values are
listed in Table 7.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 8S6303 • DALLAS. TEXAS 75266
5-37
TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097B - SEPTEMBER 1994 - REVISED MARCH 1995
APPLICATION INFORMATION
1.9
1.8
/ \ 1/
/ ..l\ r
I~
1.7
1.6
1.5
1.4
t 0.6
I'\.
1.3
t=O., -\:
1.2
t='·
IIc
0
I
t=1
I
t= I
/
1\
\
~
-
~
0.8
0.7
0.6
I
I
I
0.4
0.3
I
0.2 r----.
0.1
o
rl V /t \i\ J
V
/ vr
,1//
,
r!J
V
!
0.5
J
"
o
,i
2
3
4
I
5
Cllnts=4.5
6
7
8
9
10
~t
Figure 26. Type 1 Second Order Step Response
~TEXAS
5-38
Jr\
~
0.9
EN
0&-
I
t= _I.
~
I
1z
I
t=
/ ~
~K ~,
~
~
~~
it' r\
'II ~ ~ \'\. ..........~ -~
-~
I I ~~
11111/ ~=1.01
\~
F-'
II/IV/ / t : { i ~ /
"
1.1
0
J
/1 \; rr
/1 ~ ~ ;'11 K~
t= I
-
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
11
12
13
TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097B - SEPTEMBER 1994 - REVISED MARCH 1995
APPLICATION INFORMATION
1.9
1.8
/
1.7
V
\ Vfr (Jt V- I
1.6
,~
1.4
1.2
0
0.8
...::
C-
o
0.7
0.6
0.5
0.4
I
I
I
jr,
~ =0.4
~ ~=0.5
___
~ =~.6
~ ~ ~/
~ =0.7
I
~~
'/,
0.9
1 IVIII
..
I
~ =0.2
/ !\
IL , \
~
~ ..... ~ ~.
1.1
'5
S::J
z
:v
~ ~\
1.3
1
=1
~ =0.3
1.5
ir
Iii::J
...~
Y
~
V-
'-
1/110
'1118
~ =
-;;;...-
~
VII
\'-- / VI
/ /
= 0.8
I
'-
~
~
~
"
= 1.0
I
-
'\.....I
\ J
\\.... './/
VB
0.3
rJ
0.2
0.1
o
r
o
234
5
6
7
8
9
10
11
12
13
IIlnt
Figure 27. Type 2 Second Order Step Response
~TEXAS
INSTRUMENTS
POST OFACE BOX 656303 • DAllAS. TEXAS 75265
5-39
TLC29321
HIGH~PERFORMANCE
.
PHASE·LOCKEDLOOP
SLAS091B - SEPTEMBER 1994 -REVISED MARCH 1995
APPLICATION INFORMATION
VDD'
veo
I
1 LOGIC VDD (Digital)
VCOVDD
Inhibit
2
BIAS
-& DGND
14
AVDD
R1t
..
13
;;: ::::: 0.22 jtF'
3
REFIN
VCOOUT8
r-. 1/2
4~A
r-..
veo
R3
12
'.
IN
VCOGND
11
C2 ;;:
~
r:
R2 ~
C1
\1
On/Off
D! D
II
rh
10
56
AGND
6
Phase
I Inhibit
I Comparator I
I
7 LOGIC GND (Digital)
Divide
By
N
9
NC
~
DtD
R4
R5
~~
R6
DGND
DVDD
t RSIAS resistor
Figure 28. Evaluation and Operation Schematic
PCB layout considerations
The TLC29321 contains a high frequency analog oscillator; therefore. very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC29321 user:
•
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
•
RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.
•
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
•
LOGIC Voo and VCO Voo should be separate PCB traces and connected to the best filtered supply pOint
available in the system to minimize supply cross-coupling.
•
VCO Voo to GND and LOGIC Voo to GND should be decoupled with a O.1-¢= capacitor placed as close
as possible to the appropriate device terminals.
•
The no-connection (NC) terminal on the package should be connected to GND.
~1ExAs
5-40
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265
TL32088
DIFFERENTIAL ANALOG BUFFER AMPLIFIER
MARCH 1995
• Analog Front-End Integrated Circuit for the
18-Blt Stereo Audio Sigma-Delta Analog-toDigital Converter TLC320AD58C and
Equivalent Analog-to-Dlgltal Converters
• Single-Ended to Differential Signal
Conversion
NSPACKAGE
(TOP VIEW)
AVss
IN L+
INLOUTL
REFL
FLTL 1
FLTL2
AOUTLAOUTL+
• Low Distortion, Low Noise
- THD+N ••. -10o-dB Typ
- SIN ••• 108-dB Typ
•
•
•
•
1
REFL1
Adjustable Signal Gain
5-V Single Supply Operation
Internal Voltage Reference
Operating Temperature ••• -20°C to 70°C
6
7
8
9
10
15
14
13
12
11
REF R1
INR+
INROUTR
REFR
FLTR 1
FLTR2
AOUTRAOUTR+
AVoo
AVAILABLE OPTIONS
description
PACKAGE
The TL32088 is an analog signal conditioning
TA
SMALL OUTLINE
integrated circuit built using a proprietary Texas
(NS)
Instruments bipolar process. This device is used for
-20·C to 70·C
TL32088INS
the analog signal input stage of the 18-bit, stereo
audio, sigma-delta, analog-to-digital converter (ADC)
TLC320AD58C or equivalent converters. The TL32088 converts a single-ended audio signal to a differential
· signal with externally controlled gain for the input of a sigma-delta ADC, differential-analog Signal input. The
differential output can be connected to the TLC320AD58C directly. The TLC32088 is composed of high
performance amplifiers that offer wide output swing with low distortion and low noise. The reference voltage for
the internal amplifiers circuit is provided from an internal voltage reference circuit.
The TL32088 operates in a single 5-V supply high end audio system providing wide output swing while
maintaining -1 OD-dB THD+N and 108-dB SNR.
3:
w
:;
w
IX
a..
b
:::l
C
o
functional block diagram
OUTR
REFR
FLTR1
IX
FLTR2
a..
5kn
INRINR+
ROUT
AOUTRROUT
AOUTR+
REF
LOUT
AOUTL+
LOUT
AOUTL-
":'
INL+
INL-
5kn
OUTL
REFL
FLTL1
~1ExAs
FLTL2
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
5-41
TL32088
DIFFERENTIAL ANALOG BUFFER AMPLIFIER
SLAS123- MARCH 1995
absolute maximum rating over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) .........................................................•... 7 V
Differential input voltage, VIO (see Note 2) ................................................. , ... 7 V
Input voltage range, VI (any input) (see Notes 1 and 3) .................................. -0.3 to Vee
Output voltage, Vo .................................................................. -0.3 to Vee
Output current, 10 ...................................•.................................... 20 mA
Duration of short-circuit current at or below 25°C (output shorted to GND) ..................... unlimited
Continuous total dissipation, Po (TA:S; 25°C) (see Note 4) ................................... 625 mW
Operating free-air temperature range, TA ............................................ -20°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ......... • . . . . . . . . . . . . . . . . . . . .. 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other condHions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliabilHy.
NOTES: 1. All voltage valUes, except differential voltage, are with respect to GND.
2. Differential voltage is at the noninverting input with respect to the inverting input.
3. All input voltage values must not exceed VCC.
4. Derating factor above TA = 25·C is 10 mW'·C.
"0 recommended operating conditions
::D
o
MIN
NOM
MAX
5
UNIT
V
C
Supply voltage, VCC
Input voltage range, VI (see Note 5)
1.1
3.9
V
o
Operating free-air temperature, TA
-20
70
·C
c:
....
NOTE 5: The output voltage is undetermined when the input voltage exceeds recommended input voltage range.
~
electrical characteristics over recommended operating free-air temperature range, Vee
(unless otherwise noted)
~
m
m
<
-
:e
PARAMETER
TEST CONDITIONS
VO-2.5V
VIO
Input offset voltage
VIC=2.5V,
(AMPL1,R1)
110
Input offset current
VIC-2.5V, Vo = 2.5 V
(AMPL1,R1)
TA=25·C
liB
Input bias current
VIC=2.5V, Vo = 2.5 V
(AMP L1, R1)
TA=25·C
VIC
Common-mode input voltage
VOS7.5 mV (AMP L1, R1)
VOM+
VOM-
MAX
5
nA
150
TA - -20·C to 70·C
20
nA
TA = -20·C to 70·C
0.9
4.1
TA = -20·C to 70·C
1.1
3.9
Maximum positive-peak output voltage
TA - -20·C to 70·C
4.4
Maximum negative-peak output voltage
TA = -20·C to 70·C
Differential voltage amplification
CMRR
Common-mode rejection ratio
Vo = 2.5 V±5 V
(AMPL1,R1)
Vref
Reference voltage
EG
Gain error
ro
Output resistance
Supply current (both channels)
V
0.6
dB
TA=25·C
85
dB
2.45
2.5
TA - -20·C to 70·C
No load
V
60
TA=25·C
VO. 2.5 V,
V
TA=25·C
TA - -20·C to 70·C
See Note 6
UNIT
mV
7.5
TA=25·C
Avd
TA=25·C
TA - -20·C to 70·C
NOTE 6: Gam error Is between OUT Land FLTL 1, OUT Rand FLTR 1.
~TEXAS
5-42
TYP
1
TA = -20·C to 70·C
VO=2.5V±1 V
(AMP L1, R1)
ICC
MIN
TA-25·C
=5 V
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS, TEXAS 75265
2.55
V
±3%
50
Q
15
18
mA
TL32088
DIFFERENTIAL ANALOG BUFFER AMPLIFIER
SLAS123-MARCH 1995
operating characteri~tics over recommended operating free-air temperature range, VCC
(unless otherwise noted)
PARAMETER
Slew rate
Bl
SNR
Unity-gain bandwidth
AV·l,
AMPL1, Rl
Signal-to-noise ratio (EIAJ)
A-Weight test circuit
Total harmonic distortion plus noise
VO(PP) =3.2 V,
f =1 kHz,
BW _ 10Hz to 20 kHz test circuit
THD+N
MIN
TEST CONDITIONS
SR
VI-2.5 V + 0.5V (AMP L1, Rl)
TYP
MAX
=5 V
UNIT
3
V/)JJ5
7
MHz
108
dB
-100
dB
APPLICATION INFORMATION
AVOD
;:
->W
T
w
a:
a.
t)
::l
C
1°""T
o
IX:
a.
I
AOUT R-113
OUT~4-------~+---~~~--J
ONLM)t
L---4~I/\r-----.._:..=-----------+
50 n AOUT R+ 112
10 AOUT L+ 50 n
ouTL+4-------~~~~~------~
OUT RONRM)t
~------~r_--_+------------_.OUTR+
(INRP)t
ONLP)t
t TLC320AD58C input terminals.
Figure 1. TL32088 to TLC320AD58C Connections
~ThXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
5-43
6-1
II
_.
<
CCD
o
::J
.....
CD
~
Q)
(")
CD
"'tJ
-.....
.....
Q)
CD
CD
tn
6-2
TLC34058
256 x 24 COLOR·PALETTE
1995
•
•
•
•
•
•
•
•
• Direct Interface to TMS340XX Graphics
Processors
• Standard Microprocessor Unit (MPU)
Palette Interface
• Multiplexed-TTL Pixel Ports
• Triple Dlgital-to-Analog Converters (DACs)
• Dual-Port Overlay Registers •.• 4 x 24 Bits
• 5-V Power Supply
• Data Sheet Avallablet
CMOS Technology
135-MHz Plpelined Architecture
Available Clock Rate .•. 80,110,135 MHz
Dual-Port Color RAM
256 Words x 24 Bits
Bit-Plane Read and Blink Masks
EIA R8-343-A Compatible Outputs
Functionally Interchangeable With
Brooktree® Bt458
Direct Interface to SMJ340xx Graphics
Processors (110M)
description
The TlC34058 color-palette integrated circuit is specifically developed for high-resolution color graphics in such
applications as CAE/CAD/CAM, image processing, and video reconstruction. The architecture provides for the
display of 1280 x 1024 bit-mapped color graphics (up to eight bits per pixel resolution) with two bits of overlay
information. The TlC34058 has a 256-word x 24-bit RAM used as a lookup table with three 8-bit, video, D/A
converters.
On-chip features such as high-speed pixel clock logic minimize costly ECl interface. Multiple pixel ports and
internal multiplexing provide TTl-compatible interface (up to 32 MHz) to the frame buffer while maintaining
sophisticated color graphic data rates (up to 135 MHz). Programmable blink rates, bit plane masking and
blinking, color overlay capability, and a dual-port palette RAM are other key features. The TlC34058 generates
red, green, and blue signals compatible with EIA RS-343-A and can drive 75-0 coaxial cables terminated at
each end without external buffering.
AVAILABLE OPTIONS
PACKAGE
TA
SPEED
DAC
RESOLUTION
80 MHz
8 Bits
O·Cto 70·C
110MHz
8 Bits
135 MHz
8 Bits
-
-55·Cto 125·C
110 MHz
8 Bits
TLC34058-110MGA
PLASTIC CHIP
CARRIER
(FNI
CERAMIC GRID ARRAY
(GAl
-
TLC34058-80FN
TLC34058-110FN
TLC34058-135FN
-
QUAD FLATPACK
(HFGI
TLC34058-110MHFG
t For the complete data sheet. refer to the Graphics and Imaging Data Book (SLAD002).
Brooktree is a registered trademark of Brooktree Corporation.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-3
TLC34058 .
256 x 24 COLOR PALETTE
XLAS05O-APRIL 1995
functional block diagram
REF
FSADJ
a:K
CLK
load
Control
Multiplex
Control
1 - 4 1 - - - - - - COMP
Blink
Control
lD
P(7-0) 40
(A-E)
lOR
OlO-Ol1
(A-E)
lOG
4x24
Overlay
SYNC
Palette
Registers
BlK
CE
RJW
Bus
Control
co
To
I - - Control
Functions
C1
To
D(7-0)
8
8
Add.....
Control
Functions
8
Rad
Value
Green
;'Value
Blue
Value
"
,
,r
~1ExAs
INSTRUMENTS
'
POST OFFIcE BOX 665303 • DAWIS. TEXAS 75265
lOB
TLC34074
VIDEO INTERFACE
DIGITAL-TO-ANALOG CONVERTER
•
•
•
•
•
•
•
•
•
•
•
• Versatile Multiplexing Interface Allows
Lower Pixel Bus Rate
• High Level of Integration Provides Lower
System Cost and Complexity
• Versatile Pixel Bus Interface Supports
Little- and Blg-Endlan Data Formats
• Directly Interfaces to TMS340101TMS34020
and Other Graphics Processors
• Single 8-Blt D/A Converters
• Low Cost Monochrome and Gray-Scale
System
• Pin Compatible With TLC34075 and
TLC34076
135-, 170-, and 2QO-MHz Versions
On-Chip Voltage Reference
R8-343A-Compatlble Outputs
TTL-Compatible Inputs
Standard MPU Interface
On-Chip Clock Selection
Directly Interfaces to Video RAM
Supports Split Shift-Register Transfers
TIGATII Software-Standard Compatible
CMOS Technology
Data Manual Avallablet
description
The TLC34074 video interface DAC (VID) is designed for monochrome and gray-scale graphics systems,
providing lower system cost with a higher level of integration by incorporating all the high-speed timing,
synchronizing, and multiplexing logic usually associated with graphics systems into one device, thus greatly
reducing chip count. Since all high-speed signals (excluding the clock source) are contained on-chip, RF noise
considerations are simplified. Maxitnum flexibility Is provided through the pixel multiplexing scheme, which
allows for 32-, 16-, 8-, and 4-bit pixel buses to be accommodated without any circuit modification. This enables
the system to be easily reconfigured for varying amounts of available video RAM. Additionally, data can be split
into 1, 2, 4. or 8-bit gray-scale.
The TLC34074 is also designed to be terminal compatible with the TLC34075 and TLC34076 video interface
palettes. Therefore, a single graphics design can be configur9d into a color or black-and-white system by using
either the TLC34075/076 Or the TLC34074 to reduce the system cost and increase the resolution. Like the
TLC34076, the TLC34074 can be programmed for little or big-endian data format for the pixel bus frame buffer
interface.
The TLC34074 has an &-bit video digital-to-analog converter (DAC) capable of directly driving a doubly
terminated 75-0 line. Sync generation can be incorporated onto the output channel when so enabled. Hsync
and Vsync are fed through the device and optionally inverted to indicate screen resolution to the monitor. Bit
stuffing logic repeats the intended gray-scale pattern to the least significant bits when the gray-scale is not 8 bits
wide. This allows the 8-bit DAC to achieve full R8-343A output levels while maintaining uniform linearity for all
codes.
AVAILABLE OPTIONS
PACKAGE
TA
SPEED
0·Cto70·C
170 MHz
135 MHz
200 MHz
DAC
RESOLUTION
SBits
SBits
SBits
PLASTIC CHIP
CARRIER
(FN)
TLC34074-135FN
TLC34074-170FN
TLC34074-200FN
t For the complete data manual; refer to the Graphics and Imaging Data Book (SLAD002).
TIGA is a trademark of Texas Instruments Incorporated.
CopyrIght@ 1995, Texas Instruments Incorporated
:'II·
.1ExAs
NSTRUMENTS
POST OFFICE eox 656303 • DALLAS. TEXAS 75265
TLC34074
VIDEO COLOR PALETTE
XLAS056 - MAY 1995
description (continued)
Clocking is provided through one of four inputs (3 TTL- and 1 EClJTTL-compatible) and is software selectable.
The video and shift-clock outputs provide a software-selected divide ratio of the chosen clock input.
The TLC34074 can be connected directly to the serial port of VRAM devices, eliminating the need for any
discret~ logic. Support for split shift-register transfers is also provided.
functional block diagram
:>----.+-IOG
lOB
S}ata.
0(7-0)
Test
a
Register
RS(3-0)
RO
WR
Qock
Control
~
i
or-
k
:IIi:
01r:IIi:
W
pp
:IIi::IIi:
;!!
lo'
g
Figure 1. Functional Block Diagram
:b
Output
MUX
6-10
TLC34076
VIDEO INTERFACE PALETTE
XLAS076 - MAY 1995
• CMOS Technology
• Versatile Multiplexing Interface Allows
Lower Pixel Bus Rate
• High Level of Integration Provides Lower
System Cost and Complexity
• Direct VGA Pass-Through Capability
• Versatile Pixel Bus Interface Supports
Little- and Big-Endlan Data Formats
• True-Color (Direct Addressing) Modes
Support Various 24- and 16-Bit Formats
• XGATM-Format Compatible (5-6-5)
• TARGATM-Format Compatible (5-5-5)
• Directly Interfaces to TMS34010ITMS34020
and Other Graphics Processors
• Triple B-Blt D/A Converters
• 85-,110-,135-, and 170- MHz Versions
•
•
•
•
•
•
•
•
•
•
•
256-Word Color Palette RAM
Palette Page Register
On-Chip Voltage Reference
RS-343A-Compatlble Outputs
TTL-Compatible Inputs
Standard MPU Interface
Pixel Word Mask
On-Chip Clock Selection
Directly Interfaces to Video RAM
Supports Split Shift-Register Transfers
Software Downward-Compatible With
INMOS IMSG17618 and Brooktree™ BT47618
Color Palettes
• TIGATM Software-Standard Compatible
• Data Manual Avallablet
description
The TLC34076 video interface palette (VIP) is designed to provide lower system cost with a higher level of integration.
The device incorporates all of the high-speed timing, synchronization, and multiplexing logic usually associated with
graphics systems into one device, thus greatly reducing chip count. Since all high-speed signals (excluding the clock
source) are contained on-chip, RF noise considerations are simplified. Maximum flexibility is provided through the
pixel multiplexing scheme, which allows for 32-, 16-,8-, and 4-bit pixel buses to be accommodated without any circuit
modification. This enables the system to be easily reconfigured for varying amounts of available video RAM. Data
can be split into 1-, 2-, 4-, or 8-bit planes. The TLC34076 is software-compatible with the IMSG176/8 and Brooktree
BT476/8 color palettes.
The TLC34076 VIP is terminal-for-terminal compatible with the TLC34075 VI P but contains additional 24- and 16-bit
true-color modes as well as the ability to select little- or big-endian data formats for the pixel bus frame-buffer interface.
The TLC34076 features a separate video graphics adapter (VGA) bus that allows data from the feature connector
of most VGA-supported personal computers to be fed directly into the palette without the need for external data
multiplexing. This allows a replacement graphics board to remain downward compatible by utilizing the existing
graphics circuitry often located on the motherboard.
The 24- and 16-bit true-color modes that are provided allow bits of color information to be transferred directly from
the pixel port to the digital-to-analog converters (DACs). Depending on which true-color mode is selected, an ovetray
function is provided using the remaining bits of the pixel bus. The 24-bit modes allow overlay with the eight remaining
bits of the pixel bus, while the TARGA (5-5-5) 16-bit mode allows overlay with the one remaining bit of the divided
pixel bus.
The TLC34076 has a 256-by-24 color-lookup table with triple, B-bit video, D/A converters capable of directly driving
a doubly terminated, 75-0 line. Synchronization generation is incorporated on the green output channel. HSYNC and
VSYNC are fed through the device and optionally inverted to indicate screen resolution to the monitor. A palette page
register provides the additional bits of palette address when 1-, 2-, or 4-bit planes are used. This allows the screen
colors to be changed with only one MPU write cycle.
t For the complete data manual, refer to the Graphics and Imaging Data Book (SLAD002).
XGA is a trademark of Intemational Business Machines Corporation.
TARGA is a trademark of Truevision incorporated.
Brooktree is a trademark of Brooktree Corporation.
TIGA is a trademark of Texas Instruments incorporated.
~ThXAS
copyright © 1995,·Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • O",LLAS, TEXAS 75265
6-11
TLC34076
VIDEO INTERFACE PALETTE
XLAS076-MAY 1995
description (continued)
Clocking is provided through one of four or five inputs (three TIL- and either one ECL- or two .TIL-compatlble) and
is software selectable. The video and shift-clock outputs provide a software-selected dMde ratio of the chosen clock
input.
The TLC34076 can be connected directly to the serial port of VRAM devices, eliminating the need for any discrete
logic. Support for split shift-register transfers is also provided.
AVAILABLE OPTIONS
PACKAGE
TA
O·Cto 70·C
-55·C to 125·C
SPEED
DAC
RESOLUTION
PLASTIC CHIP
CARRIEFi
(FN)
a5MHz
110 MHz
a Bits
a Bits
TLC34076-85FN
TLC34076-110FN
135 MHz
170 MHz
a Bits
TLC34076-135FN
a Bits
TLC34076-170FN
135 MHz
a Bits
-
~ThxAs
6-12
INSTRUMENTS
POST OFFICE BOX 865303 • DALLAS. TEXAS 75265
GRID ARRAY
(GA)
-
-
TLC34076-135MGA
function block diagram
,.
11
24
v...
111. I
True-CoIor
PIpeline DeIIIr
>.
•
COIF
FS ADJUST
~
lOR
Color
PaIelIe
1"
2
Ilr
I
RAM
•
OUtput
lOB
D(7~)
RS~)
iii)
WR
r
MPU
.'.1
1124<
,.
I
· II~MUX~=
I
and Control
Clock
Control
SFLAGINFLAG CLK3 CLK3 SCLK VCLK
Figure 1. Functional Block Diagram
Co>
_ _~
MUXOUT
sc
oi-.J~ ..........
iiSYNC
!
lOG
IlUX
~
BLANK
~
VSYNC
i
I
~
i
::u
~
g
~;:!
~~
=I~
me»
6-14
TLC34077
VIDEO INTERFACE PALETTE
XLAS045-APRIL 1995
• Versatile Multiplexing Interface Allows
Lower Pixel Bus Rate
• High Level of Integration Provides Lower
System Cost and Complexity
• Direct VGA Pass-Through Capability
• True-Color (Direct Addressing) Modes
Support Various 24- and 16-Bit Formats
• XGATM-Format Compatible (5-6-5)
• TARGATM-Format Compatible (5-5-5)
• Directly Interfaces to Most Graphics
Processors
•
•
•
•
•
•
•
•
256-Word Color Palette RAM
On-Chip Voltage Reference
RS-343A-Compatlble Outputs
TTL-Compatible Inputs
Standard MPU Interface
Pixel Word Mask
On-Chip Clock Selection
Software Downward-Compatible With
INMOS IMSG176/8 and BrookTree™ Bt476/8
Color Palettes
• TIGATM Software-Standard Compatible
• Triple 8-Blt D/A Converters
• 11D- and 135-MHz Versions
• CMOS Technology
• Data Manual Avai/ablet
description
The TLC34077 video interface palette (VIP) is designed to provide lower system cost with a higher level of integration
by incorporating all the high-speed timing, synchronization, and multiplexing logic usually associated with graphics
systems into one device, thus greatly reducing chip count. Since all high-speed signals (excluding the clock source)
are contained on-chip, RF noise considerations are simplified. Maximum flexibility is provided through the pixel
multiplexing scheme, which allows for 32-, 16-, and 8-bit pixel buses to be accommodated without any circuit
modification. The TLC34077 is software compatible with the IMSG176/8 and Brooktree Bt476/8 color palettes.
The TLC34077 VIP is terminal-for-terminal compatible with the TLC34076 VIP, but with a reduced feature set
optimized for cost-sensitive, high-performance, PC graphics applications. The TLC34077 is compatible with a variety
of graphics processors, including the ATI 68800 mach 32 series of graphics accelerators.
The TLC34077 features a separate VGA bus that allows data from the feature connector of most VGA-supported
personal computers to be fed directly into the palette without the need for external data multiplexing. This allows a
replacement graphics board to remain downward compatible by utilizing the existing graphics circuitry often located
on the motherboard.
The 24- and 16-bit true-color modes that are provided allow bits of color information to be transferred directly from
the pixel port to the DACs.
The TLC34077 has a 256-by-24 color-lookup table with triple, 8-bit video, D/A converters capable of directly driving
a doubly terminated, 75-0 line. Synchronization generation is incorporated on the green output channel.
Clocking is provided through one of two TIL-compatible inputs and is software selectable. The video clock output
provides a software-selected divide ratio of the chosen clock input.
AVAILABLE OPTIONS
PACKAGE
TA
O·Cto 70·C
SPEED
DAC
RESOLUTION
110MHz
8 Bits
TLC34077-110FN
135 MHz
8 Bits
TLC34077-135FN
PLASTIC CHIP
CARRIER
IFN)
t For the complete data manual, refer to the Graphics and Imaging Data Book (SLAD002).
XGAis a trademark of International Business Machines Corporation.
TARGA is a trademark of Truevision Incorporated.
Brooktree is a trademark of Brooktree Corporation.
TIGA is a trademark of Texas Instruments Incorporated.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75266
6-15
e-
!
=
SO'
=
!!.
Q)
24
CT
32
16.
8
16.
Tru.color
15.' Pipeline Delay
COMP
0'
~
a.
Dr
co
x
~
I
>
"U
:u
r=
i
~
o
Color
~~Z-.4r
!;~r
I
Palette
RAM
I
,
lit; - I MUX
Output
lOG
lOB
LCLK
Test
D(7-o)
RS(3-0)
AD
WR
Register
II ~<
_I
-
Clock
II C:~:01
\I1deo MUX
Control
p
~
e
Figure 1. Functional Block Diagram
~,
an;
~i
0
-::t
0
!i
m
:2J
~
m
(')
a3
lOR
<~
_I""'"
I
~
I""'"
m
~
m
TVP2002
CLOCK DRIVER
•
•
•
•
•
•
•
•
•
•
135-MHz Operation
Differential ECl Clock Generation
Divide by 3, 4, 5, or 8 of the Clock
Divide by 2 and 4 of the load
Resets Pipeline Delay of the TlC34058
1.235-V Voltage Reference Output
5-V Single Power-Supply Operation
28-Pin PlCC (FN) Package
low Power Consumption ••• 400 mW Max
Designed to Be Interchangeable With
Brooktree™ Bt438
• Data Sheet Availablet
FNPACKAGE
{TOP VIEW)
~g
~
~ ~
I Cl)tt»o«
~a:ooz~~
W
0
5 432 :
IXlIXl
282726 25
9
10
24
23
22
21
20
11
19
6
7
LOA
LOB
NC
GND
GND
NC
NC
12 1314 15 16 17 18
description
~
010
~ ~
I OCl)CI)CCCC
The TVP2002 is a clock driver for the Texas
Instruments
TLC34058
and
functionally
equivalent color palettes. It interfaces to a 10
KH-ECL oscillator operating from a single 5-V
supply I to the TLC34058, generating the
necessary clock and control signals.
co
OOO..J..J..J..J
..J
o
NC - No internal connection
The clock output may be divided by 3, 4, 5, or 8 to generate the load signal. The load signal is also divided by
2 and 4 for clocking video timing logic. for example. A second load signal may be synchronously or
asynchronously controlled to enable starting and stopping of the VRAM Clock.
The TVP2002 also optionally configures the pipeline delay ofthe TLC34058 to a fixed-pipeline delay. An on-chip
1.235-V reference is provided and may be used to provide the reference voltage for the color palette.
AVAILABLE OPTIONS
PACKAGE
TA
O·CIo 70"C
PLASTIC CHIP
CARRIER
(FN)
TVP2002FN
t For the complete data sheet. refer to the Graphics and Imaging Data Book (SLAD002).
Brooktree Is a trademark of Brooktree Corporation.
-!llExAs
Copyright @ 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 865303 • DALLAS, TEXAS 75265
6-17
TVP2002
.CLOCK DRIVER
XLAS083-MAY 1995
functional block diagram
REF
VCC
GND
CLOCK
CLOCK
esc
OSC
r~=:~~~~~~~~~~f=LDA'LDB
LD/2.
'---r-......
LD/4
LDC, LDD
DIVO, DIV1
ENABLE(S) ENABLE(A)
~TEXAS
6-1!l
INSTRUMENTS
POST OFFICE BOX 865303 • DALLAS. TEXAS 75265
TVP3010
VIDEO INTERFACE PALETTE
• Second-Generation Video Interface Palette
• Supports System Resolutions of:
- 1600 x 1280 x 1, 2, 4, 8, 16 BitS/Pixel at
60-Hz Refresh Rate
- 1280 x 1024 x 1, 2, 4, 8, 16 BIts/Pixel at
60-Hz and 72-Hz Refresh Rates
- 1024 x 768 x 1, 2, 4, 8, 16,24 BIts/Pixel at
60-Hz and 72-Hz Refresh Rates
- Lower Resolutions
• Direct-Color Modes:
- 24-Blt/Plxel with 8-Blt Overlay
..,. 16-Blt/Plxel (5, 6, 5) XGATM Configuration
- 16-Blt/Plxel (6, 6, 4) Configuration
- 15-Blt/Pixel With 1-Bit Overlay (5, 5,5,1)
TARGATM Configuration
- 12-Blt/Pixel With 4-Bit Overlay (4, 4, 4, 4)
• True-Color Modes:
- 24-Blt/Plxel With Gamma Correction
- 16-Blt/Plxel (5, 6, 5) XGA Configuration
With Gamma Correction
- 16-Blt/Plxel (6, 6, 4) Configuration with
Gamma Correction
- 15-Blt/Plxel (5, 5, 5) TARGA
Configuration With Gamma Correction
, - 12-Blt/Plxel (4, 4, 4) With Gamma
Correction
• On-Chip Hardware Cursor:
- 64 x 64 x 2 Cursor (XGA Functionally
Compatible)
- Full-Window Crosshair
- Dual-Cursor Mode
• 85-,110-,135- and 170-MHz Versions
• Supports Overscan For Creation of Custom
Screen Borders
• Versatile Pixel Bus Interface Supports
Little- and Blg-Endlan Data Formats
• Windowed Overlay, VGA Capability
• Color-Keyed Switching of Direct Color and
Overlay
•
•
•
•
•
•
•
•
•
•
On-Chip Clock Selection
Internal Frequency Doubler
Triple 8-Blt D/A Converters
Analog Output Comparators
Triple 256 x 8 Color Palette RAMs
R8-343A-Compatlble Outputs
Direct VGA Pass-Through Capability
Palette-page Register
Horizontal Zooming Capability
Software Downward Compatible With
IMSG17618 and Bt47618
• RCLKlSCLKlLCLK Data Latching Allows
Flexible Control of VRAM Timing
• Directly Interfaces to Graphics Processors
• Direct Interfacing to Video RAM
• Supports Split Shift-Register Transfers
• CMOS Technology
• Data Manual Avallablet
• 64-Bit Wide Pixel Bus
description
The lVP301 0 palette is an advanced video interface palette (VIP) from Texas Instruments implemented in the EPICTM
O.8-micron CMOS process. Maximum flexibility is provided by the pixel multiplexing scheme. The scheme
accommodates 64-, 32-, 16-, 8-, and 4-bit pixel buses without any circuit modification. This enables the system to
be easily reconfigured for varying amounts of available video RAM. The device supports selection of little- or
big-endian data format for the pixel-bus/frame-buffer interface. Data can be split into 1-, 2-, 4-, or 8-bit planes for
pseudo-color mode or split into 12-,16- or 24-bit true-color and direct-color modes. For the 24-bit direct color modes,
an 8-bit overlay plane is available. The 16-bit direct- and true-color modes can be configured to IBMTM XGA (5, 6, 5),
TARGA (5, 5, 5,1), or (6, 6, 4) as another existing format. An additional 12-bit mode (4, 4, 4, 4) is supported with 4
bits for each color and overlay. An on-chip, IBM XGA-compatible hardware cursor is incorporated so that further
increases in graphics system performance are possible. The device is also software compatible with the IMSG176/8
and Bt476/8 color palettes.
t Forthe complete data manual, refertotheGraphics and Imaging Data Book (SLAD002).
XGA is a trademark of International Business Machines Corporation.
TARGA is a trademark of Truevision Incorporated.
EPIC is a trademark of Texas Instruments Incorporated.
IBM is a trademark of Intemational Business Machines Corporation.
~1EXAS
Copyright @ 1995. Texas lns1rUmen1s Incorporated
INSTRUMENTS
POST OFFICE BOX e65303 • OAu.AS. TEXAS 75265
6-19
TVP3010
VIDEO INTERFACE PALETTE
XLAS082 - MAY 1.995
description (continued)
An internal frequency doubler is incorporated, allowing convenient and cost-effective clock source alternatives to be
utilized. An auxiliary windowing function and a pixel-port-select function are provided so that overlay or VGA graphics
can be displayed on top of direct color inside or outside a specified auxiliary window. Color-keyed switching of direct
color and overlay is also supported.
Clocking is provided through one of five TIL inputs, CLKO-CLK4, and is software selectable. Additionally,
CLK1/CLK2 and CLK3/CLK4 can be selected as differential ECL clock sources. The video, shift clock, and reference
clock outputs provide a software-selected divide ratio of the chosen clock input. The reference clock can optionally
be provided as an output on CLK3, and a data latch clock can optionally be input on CLK4.
The TVP3010 has three 256-by-8 color lookup tables with triple, 8-bit video, digital-to-analog converters (DACs)
capable of directly driving a doubly terminated 75-0 line. The lookup tables are designed with a dual-ported RAM
architecture that enables ultra-high speed operation. Sync generation is incorporated on the green output channel.
Horizontal sync and vertical sync are fed through the device and optionally inverted to indicate screen resolution to
the monitor. A palette-page register provides the additional bits of palette address when 1-,2-, or 4-bit planes are
used. This allows the screen colors to be changed with only one microprocessor interface unit (MPU)write cycle.
The device features a separate VGA bus that allows data from the feature connector of most VGA-supported personal
computers to be fed directly into the palette without the need for external data multiplexing. This allows a replacement
graphics board to remain downward compatible by utilizing the existing graphics circuitry often located on the
motherboard.
The TVP301 0 VIP is highly system integrated. It can be connected to the serial port of VRAM devices without external
buffer logic and connected to many graphics engines directly. The split shift-register transfer function, which is
supported by VRAM, is also supported by the TVP301 o.
The system-integration concept is carried to manufacturing test and field diagnosis. To support these, several highly
integrated test functions have been designed to enable simplified testing of the palette, the graphics board, and the
graphics system.
The 32-bit TVP301 0 is terminal compatible with the TLC3407X VIP, allowing convenient performance upgrades when
using devices in the TI Video Interface Palette family.
AVAILABLE OPTIONS
PACKAGE
TA
SPEED
DAC
RESOLUTION
PLASTIC CHIP
C~RRIER
(FN)
0·Cto70·C
-55·C to 125·C
85 MHz
SBIts
TVP301 Q-85FN
110 MHz
S Bits
TVP301D-110FN
135 MHz
170 MHz
S Bits
TVP3010-135FN
S Bits
TVP3010-170FN
135 MHz
SBIts
-
~TEXAS
S-:-20
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
GRID ARRAY
(GA)
TVP301D-135MGA
TVP3010
VIDEO INTERFACE PALETTE
XLAS082 - MAY 1995
functional block diagram
P(31-j)
>"--+COMP
lOR
VGA(7-0)
lOG
lOB
0(7 -0)
RS(2-0)
MUXOUT (SENSE]
HSYNCOUT
VSYNCOUT
I~I~I!II
Figure 1. Functional Block Diagram
~ThxAs
INSTRUMENTS
POST OFFICE BOX 655303 • OAUAS. TEXAS 75265
6-21
6-22
TVP3020
VIDEO INTERFACE PALETTE
XLAS080A - MAY 1995
• Second-Generation Video Interface Palette
• Supports System Resolutions of:
- 1600 x 1280 x 1, 2, 4, 8, 16, 24 BitS/Pixel
at 60-Hz and 72-Hz Refresh Rate
- 1280 x 1024 x 1, 2, 4, 8,16, 24 BitS/Pixel
at 60-Hz and 72-Hz Refresh Rate
- 1024 x 768 x 1, 2, 4, 8, 16,24 BIts/Pixel at
60-Hz and 72-Hz Refresh Rate
- And lower resolutions
• Direct-Color Modes:
- 24-Blt/Plxel With 8-Blt Overlay
- 16-Blt/Plxel (5, 8,5) XGA® Configuration
- 16-Blt/Plxel (6, 6, 4) Configuration
- 15-Blt/Plxel With 1-Blt Overlay (5, 5, 5,1)
TARGA Configuration
- 12-Bit/Pixel With 4-Bit Overlay (4, 4, 4, 4)
• True-Color Modes:
- 24-Blt/Pixel With Gamma Correction
- 16-Bit/Pixel (5, 6, 5) XGA Configuration
With Gamma Correction
- 16-Blt/Plxel (6, 6, 4) Configuration With
Gamma Correction
- 15-Blt/Plxel (5, 5, 5) TARGA®
Configuration With Gamma Correction
- 12-Blt/Plxel (4, 4, 4) With Gamma
Correction
• RCLKlSCLKlLCLK Data Latching Allows
Flexible Control of VRAM Timing
• Direct Interfacing to Video RAM
• Supports Split Shift-Register Transfers
• 64-Blt-Wide Pixel Bus
• On-Chip Hardware Cursor:
- 64 x 64 x 2 Cursor (XGA Functionally
Compatible)
- Full-Window Crosshalr
- Dual-Cursor Mode
• 135-,170-, and 200-MHz Versions
• Supports Overscan for Creation of Custom
Screen Borders
• Versatile Pixel Bus Interface Supports
Little- and Blg-Endlan Data Formats
• Windowed Overlay, VGA Capability
• Color-Keyed Switching of Direct Color and
Overlay
• On-Chip Clock Selection
• Internal Frequency Doubler
• Triple 8-Blt D/A Converters
• Analog-Output Comparators
• Triple 256 x 8 Color Palette RAMs
• R8-343A-Compatlble Outputs
• Direct VGA Pass-Through Capability
• Palette-Page Register
• Horizontal Zooming Capability
• Software Downward Compatible With
IMSG17618 and Bt47618
• Directly Interfaces to Graphics Processors
• CMOS Technology
• Data Manual Avallablet
description
The TVP3020 viewpoint palette is an advanced video interface palette (VIP) from Texas Instruments implemented
in EPICTM O.B-micron CMOS process. Maximum flexibility is provided by the pixel multiplexing scheme. The scheme
accommodates 64-, 32-, 16-, 8-, and 4-bit pixel buses without any circuit modification. This enables the system to
be easily reconfigured for varying amounts of available video RAM. The device supports selection of little- or
big-endian data format for the pixel-bus-frame buffer interface. Data can be split into 1-,2-, 4-, or 8-bit planes for
pseudo-color mode or split into 12-, 16- or 24-bit true-color and direct-color modes. For the 24-bit direct color modes,
an 8-bit overlay plane is available. The 16-bit direct- and true-color modes can be configured to IBM XGA® (5, 6, 5),
TARGA® (5, 5, 5,1), or (6, 6, 4) as another existing format. An additional 12-bit mode (4, 4, 4, 4) is supported with
4 bits for each color and overlay. An on-Chip, IBM XGA-compatlble hardware cursor Is Incorporated so that further
increases in graphics system performance are possible. The device is also software compatible with the IMSG176/8
and Bt476/8 color palettes.
t Forthecomplete data manual, refertotheGraphics and Imaging Data Book (SLAD002).
EPIC is a trademark of Texas Instruments Incorporated.
XGA Is a trademark of Intemational Business Machines Corporation.
TARGA is a trademark of Truevision Incorporated.
~1ExAs
Copyrlght@ 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 76266
6-23
TVP3020.
VIDEO INTERFACE PALETTE
XLAS080A- MAY 1995
description (continued)
An' internal frequency doubler is incorporated, allowing convenient and cost-effective clock source alternatives to be
utilized.
.
An auxiliary windowing function and a pixel-port-select function are provided so that overlay or VGA graphics can be
displayed on top of direct color inside or outside a specified auxiliary window. Color-keyed switching of direct color
and overlay is also supported.
Clocking is provided through one ofthree inputs (two TTL- and one ECL/TTL-compatible) and is software selectable.
The video clock, shift clock, lind reference clock outputs provide a software-selected divide ratio of the chosen clock
input.
.
The TVP3020 has three 256-by-8 color lookup tables with triple, 8-bit video, digital-to-analog converters (DACs)
capable of directly driving a doubly terminated, 75-0 line. The lookup tables are designed with a dual-ported RAM
architecture that enables ultra-high speed operation. Sync generation is incorporated on the green output channel. .
Horizontal sync (HSYNC) and vertical sync (VSYNC) are fed through the device and optionally inverted to indicate
screen resolution to the monitor. A palette-page register provides the additional bits of the palette address when 1-,
2-, or 4-bit planes are used. This allows the screen colors to be changed with only one microprocessor interface unit
(MPU) write cycle.
The device features a. sepa~ate VGA bus that allows data from the feature connector of most VGA-supported personal
computers to be fed directly info the palette without the need for external data multiplexing. This allows a replacement
graphics board to remain downward compatible by utilizing the existing graphics circuitry often located on the
motherboard.
The viewpoint VIP is highly system integrated. It can be connected to the serial port of VRAM devices without external
buffer logic and connected to many graphics engines directly. The split shift-register transfer function, which is
supported by VRArlt1, is also supported by the TVP3020.
The system-integration concept is carried to manufacturing test and field diagnosis. To support these, several highly
integrated test funCtions have been 'designed to enable simplified testing of the palette, the graphics board, and the
graphics system.
AVAILABLE OPTIONS
TA
0·0 to 70·0
SPEED
DAC
RESOLUTION
135 MHz
8 Bits
170 MHz
200 MHz
PACKAGE
FLAT PACK
(MDN)
FLAT PACK
(PCE)
-
TVP3020-135POE
8 Bits
8 Bits
TVP3020-200MDN
-
~ThxAs
6-24
INSTRUMENTS
POST OFFICE BOX 6S5303 • DALlAS. TEXAS 75265
TVP3020-170POE
'TVP3020
VIDEO INTERFACE PALETTE
XLAS080A- MAY 1995
functional block diagram
>"_-COMP
lOR
lOG
lOB
0(7-0)
SENSE
HSYNCOUT
VSYNCOUT
Figure 1. Functional Block Diagram
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
6-25
6-26
TVP3025
VIDEO INTERFACE PALETTE
MAY 1995
• 64-Blt Wide Pixel Bus
• Compatible With the S3 Vislon964™ and
86C928
• Brooldree BT485 Register Map Emulation
• RCLKlSCLKlLCLK Data Latching Allows
Flexible Control of VRAM Timing
• Supports System Resolutions of:
- 1600 x 1280 x 1-, 2-, 4-, 8-, 16-,
24-BitslPlxel at 60-Hz, 72, and 76-Hz
Refresh Rate
- 1536.x 1152 x 1-, 2-, 4-, 8-, 16-,
24-BltsJPlxel at 6O-Hz and 72-Hz and
Higher Refresh Rates
- 1280 x 1024 x 1-, 2-, 4-, 8-, 16-,
24-BltsJPixel at 60-Hz and 72-Hz and
Higher Refresh Rates
- 1024 x 768 x 1-, 2-, 4-, 8-, 16-,
24-BltsJPlxel at 60-Hz and 72-Hz and
Higher Refresh Rates
- And lower resolutions
• 135-,170-, and 200-MHz Versions
• Integrated Pixel Clock and Memory Clocks
Phase-Locked Loops (PLL)
• Direct-Color Modes:
- 24-Blt/Pixel with 8-Bit Overlay
- 16-Bit/Pixel(5, 6,5) XGATII Configuration
- 16-Blt/Plxel (6, 6, 4) Configuration
- 15-Blt/Plxel With 1.-Blt Overlay (5, 5, 5, 1)
TARGATII Configuration
- 12-Bit/Plxel With 4-Blt Overlay (4, 4, 4, 4)
• Windowed Overlay, VGA Capability
• Color-Keyed Switching of Direct Color and
Overlay
• True-Color Modes:
- 24-Bit/Plxel With Gamma Correction
- 16-Bit/Plxel (5, 6, 5) XGA Configuration
With Gamma Correction
- 16~Blt/Plxel (6, 6, 4) Configuration with
Gamma Correction
- 15-Blt/Plxel (5,5, 5) TARGA
Configuration With Gamma Correction
- 12-Blt/Plxel (4, 4, 4) With Gamma
Correction
• Direct InterfaCing to Video RAM
• Supports Split Shift-Register Transfers
• On-Chip Hardware Cursor:
- 64 x 64 x 2 Cursor (XGA Functionally
Compatible)
- Full-Window Crosshalr
- Dual-Cursor Mode
• On-Chip Clock Selection
• Supports Overscan For Creation of Custom
Screen Borders
• Versatile Pixel Bus Interface Supports
Little- and Blg-Endlan Data Formats
• Horizontal Zooming Capability
• Triple 8-Blt D/A Converters
• Analog-Output Comparators
• Triple 256 x 8 Color Palette RAMs
• R5-343A-Compatlble Outputs
• Direct VGA Pass-Through Capability
• Palette-Page Register
• Software Downward Compatible With
IMSG17618 and Bt47618
• CMOS Technology
• Data Manual Availablet
description
The TVP3025 is an advanced video interface palette (VIP) from Texas Instruments implemented in EPICTII O.8-micron
CMOS process. The TVP3025 is a superset of the 64-bit TVP3020 VI P with the addition of Brooktree Bt485 register
map emulation and frequency synthesis phase-locked loops (PLLs). The BT485 register emulation mode allows the
device to be software compatible with many graphics controllers, including the S3 Vision964™ and 86C928
VRAM-based graphics accelerators. This new 64-bit device provides an effective migration path from lower
performance graphics systems which utilize previous generation 32-bit color palettes.
t For the complete data manual, refer to the Graphics and Imaging Data Book (5LAD002).
EPIC Is a trademark of Texas Instruments Incorporated.
XGA is a trademark of Intemational Business Machines Corporation.
TARGA is a trademark of Truevision Incorporated.
Vision964 is a trademark of 53 Corporation.
~1ExAs
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS, TEXAS 75265
6-27
TVP3025
VIDEO INTERFACE PALETTE
XLAS090 - MAY 1995
description (continued)
The TVP3025 is a functional superset of the TVP3020 and features the same 64-1>it programmable pixel bus interface.
Data can be split into 1-, 2-, 4-, or 8-1>it planes for pseudo-color mode or split into 12-, 16- or 24-bit true-color and
direct-color modes. For the 24-bit direct color modes, an 8-bit overlay plane is available. The 16-bit direct- and
true-color modes can be configured to IBM XGA (5, 6, 5), TARGA (5, 5, 5, 1), or (6, 6, 4) as another existing format.
An additional 12~bit mode (4, 4, 4, 4) is supported with 4 bits for each color and overlay. All color modes support
selection of little or big endian data format for the pixel bus. Additionally, the device is also software compatible with
the IMSG176/8 and Bt476/8 color palettes.
Clocking is provided through one of four inputs (two TIL- and one ECLITIL-compatible) or two crystal oscillator
inputs, and is software selectable. The video, shift clock, and reference clock outputs provide a software-selected
divide ratio of the chosen clock input. Two fully programmable PLLs for pixel clock and memory clock functions are
provided, as well as a simple frequency doubler for dramatic improvements in graphics system cost and integration.
A third loop clock PLL is incorporated making pixel data latch timing much simpler than with other existing color
palettes.
Like the TVP3020, the TVP3025 also integrates a complete, IBM XGA-compatible hardware cursor on chip, making
significant graphics performance enhancements possible. Additionally, auxiliary windowing, port-select and
color-keyed switching functions are provided, giving the user several efficient means of producing graphical overlays
on direct-color backgrounds.
The TVP3025 has three 256-by-8 color lookup tables with triple, 8-bit video, digital-to-analog converters (DACs)
capable of directly driving a doubly terminated, 75-0 line. The lookup tables are designed with a dual-ported RAM
architecture that enables ultra-high speed operation. Sync generation is incorporated on the green output channel.
Horizontal sync (HSYNC) and vertical sync (VSYNC) are fed through the device and optionally inverted to indicate
screen resolution to the monitor. A palette-page register is available to provide the additional bits of palette address
when 1-, 2-, or 4-bit planes are used. This allows the screen colors to be changed with only one microprocessor
interface unit (MPU) write cycle.
The device features a separate VGA bus that allows data from the feature connector of most VGA-supported personal
computers to be fed directly into the palette without the need for external data multiplexing. The separate bus also
is useful in graphics accelerator applications, allowing efficient VGA and text mode support.
The TVP3025 is highly system integrated. It can be connected to the serial port of VRAM devices without external
buffer logic and connected to many graphics engines directly. It also supports the split shift-register transfer function,
which is common to many industry standard VRAM devices.
The system-integration concept is carried to manufacturing test and field diagnosis. To support these, several highly
integrated test functions have been designed to enable simplified testing of the palette and the entire graphics system.
AVAILABLE OPTIONS
TA
0·Cto70·C
PACKAGE
SPEED
DAC
RESOLUTION
135 MHz
8 Bits
170 MHz
8 Bits
-
200 MHz
8 Bits
TVP3025-200MDN
FLAT PACK
(MDN)
~TEXAS
6-28
INSTRUMENTS
POST OFFICE BOX 8s5303 • DALlAS. TEXAS 75265'
FLAT PACK
(PCE)
TVP3025-135PCE
TVP3025-170PCE
-
TVP3025
VIDEO INTERFACE PALETTE
XLAS090 - MAY 1995
functional block diagram
r----
COMP2
>..--- COMP1
P(63-0)
lOR
VGA(7-0)
lOG
0(7-0)
lOB
RS(4-0)
Clock Selecl
and
Conlrol
3
SENSE
r-~~--:-'_~ HSYNCOUT
2
Ii ~
g
VSYNCOUT
~ ~
g g ~ ~ g~ a~~~
!i8 0~ 0
~ .,... ~a:g>
::::;
I~
~
'i
~
&:'
Figure 1. Functional Block Diagram
~TEXAS
INSTRUMENTS
POST OFFICE BOX 656303 • OAUAS. TEXAS 75265
6-29
TVP3026
VIDEO INTERFACE PALETTE
XLAS098A - MAY 1
• SUppOrts System Resolutions up to
1600 x 1280 at 76-Hz Refresh Rate
• Supports Color Depths of 4·, 8-, 16-, 24-,
and 32·BltlPlxel
• Versatile Dlrect·Color Modes:
- 24-Blt/Plxel with 8-Blt Overlay
(0, R, G, B)
- 24-Blt/Plxel (R, G, B)
- 16-Blt/Plxel (5, 6, 5) XGATM Configuration
- 16·Blt/Plxel (6, 6, 4) Configuration
- 15-Blt/Plxel With 1·Blt Overlay (1, 5, 5, 5)
TARGATM Configuration
- 12·Blt/Plxel With 4-Blt Overlay (4, 4, 4, 4)
• True-Color Gamma Correction
• Supports Packed Pixel Formats for
24-BltlPlxel Using a 32· or 64-BltlPlxel Bus
• 50% Duty Cycle Reference Clock for Higher
Screen Refresh Rates In Packed·24 Modes
• Programmable Frequency Synthesis
Phase-Locked Loops (PLL) for Dot Clock
and Memory Clock
• Loop Clock PLL Compensates for System
Delay and Ensures Reliable Data Latching
• Versatile Pixel Bus Interface Supports
Little- and Blg.Endlan Data Formats
• 135-,175-, and 22D-MHz Versions
• On·Chlp Hardware Cursor, 64 x 64 x 2
Cursor (XGA and X·Wlndow™ Functionally
Compatible)
• Direct Interfacing to Video RAM
• Supports Overscan For Creation of Custom
Screen Borders
• Color· Keyed Switching of Direct Color and
and True Color or Overlay
• Hardware Port Select Switching Between
Direct Color and True Color or Overlay
• Triple 8-Blt D/A Converters
• Analog~Output Comparators for Monitor
Detection
• R8-343A·Compatlble Outputs
• Direct VGA Pass-Through Capability
• Palette-Page Register
• Horizontal Zooming Capability
• CMOS Technology
• Data Manual Avallablet
description
The TVP3026 is an advanced video interface palette (VIP) from Texas Instruments implemented in EPICTM O.8-micron
CMOS process. The TVP3026 is a 54-bit VIP that supports packed-24 modes enabling 24-bit true color and high
resolution at the same time without excessive amounts of frame buffer memory. For example, a 24-bit true color
display with 1280 x 1024 resolution may be packed into 4 megabytes of VRAM. A PLL-generated, 50% duty cycle
reference clock is output in the packed-24 modes, maximizing VRAM cycle time and screen refresh rate.
The TVP3026 supports all of the pixel formats of the TVP3020 VIP. Data can be split into 4- or 8-bit planes for
pseudo-color mode or split into 12-, 16- or 24-bit true-color and direct-color modes. For the 24-bit direct color modes,
an 8-bit overlay plane is available. The 16-bit direct- and true-color modes can be configured to IBMTM XGA (5, 6, 5),
TARGA (1, 5, 5, 5), or (6, 6, 4) as: ariother existing format. An additional 12-bit mode (4, 4, 4, 4) is supported with 4
bits for each color and overlay. All color modes support selection of little- or big-endian data format for the pixel bus.
Additionally, the device is also software compatible with the IMSG176/8 and Bt476/8 color palettes.
Two fully programmable PLLs for pixel clOCk and memory clock functions are provided, as well as a simple frequency
doubler for dramatic improvements in graphics system cost and integration. A third loop clock PLL is incorporated,
making pixel data latch timing much Simpler than with other existing color palettes. In addition, four digital clock inputs
(two TTL- and two ECLlTTL-compatible) can be used and are software selectable. The video clock provides a
software-selected divide ratio of the chosen pixel clock. The shift clock output can be used directly as the VRAM shift
clock. The reference clock output is driven by the loop clock PLL and provides a timing reference to the graphics
accelerator.
t For the complete data manual. refer to the Graphics and Imaging Data Book (SLAD002).
IBM is a trademark of Intemational Business Machines Corporation.
EPIC is a trademark of Texas Instrumenta Incorporated.
XGA is a trademark of IBM.
TARGA is a trademark of Truevision incorporat8d.
X-Window is a trademark of the Massachusetts Institute of Technology
~1ExAs
Copyright II:> 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 656303 • DAllAS. TEXAS 75265
6-31
TVP3026
VIDEO INTERFACE PALETTE
XLAS098A- MAY 1995
description (continued)
Like the TVP3020, the TVP3026 also integrates a complete, IBM XGA-compatible hardware cursor on chip, making
significant graphics performance enhancements possible. Additionally; hardware port select and color-keyed
switching functions allow the user several options for producing graphical overlays on direct-color backgrounds.
The TVP3026 has three 256-by-8 color lookup tables with triple, 8-bit video, digital-to-analog converters (DACs)
capable of directly driving a doubly terminated, 75-:0 line. The lookup tables are designed with a dual~port RAM
architecture that enables ultra-high speed operation. Sync generation is incorporated on the green output channel.
Horizontal sync (HSYNC) and vertical sync (VSYNC) are pipeline delayed through the device and optionally inverted
to indicate screen resolution to the monitor. A palette-page register is available to select from multiple color maps in
RAM when 4 bit planes are used. This allows the screen colOrs to be changed with only one microprocessor write
cycle.
The device features a separate VGA bus that supports the integrated VGA modes in graphics accelerator
applications, allowing efficient support for VGA graphics and text modes. The separate bus also is useful for accepting
data from the feature connector of most VGA-supported personal computers, without the need for external data
multiplexing.
The TVP3026 is highly system integrated. It can be connected to the serial port of VRAM devices without external
buffer logic and connected to many graphics engines directly. It also supports the ,split shift-register transfer function,
which is common to many industry standard VRAM devices.
The system-integration concept is even carried further to manufacturing test and field diagnosis. To support these,
several highly integrated test functions have been designed to enable simplified testing of. the palette and the entire
graphics system.
AVAILABLE OPTIONS
TA
0·Cto70·C
DAC
RESOLUTION
135 MHz
8 Bits
TVP3026-135PCE
175 MHz
8 Bits
TVP3026-175PCE
220 MHz
8 Bits
TVP3026-220PCE
~TEXAS'
6-32
PACKAGE
FLAT PACK
(peE)
SPEED
.
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75285
TVP3026
VIDEO INTERFACE PALETTE
XLASQ98A- MAY 1995
functional block diagram
REF
FSADJUST
~~---COMP2
1+-4.~-t--- COMP1
lOR
lOG
lOB
SENSE
VIdao-Slgnai
Control
Figure 1. FUnctional Block Diagram
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
HSYNCOUT
VSYNCOUT
6-34
TVP3027
VIDEO INTERFACE PALETTE
XLAS106-MAY 1995
• Supports System Resolutions up to
1600 x 1280 at 76-Hz Refresh Rate
• Supports Color Depths of 4-,8-,16-,24-,
and 32-BltlPlxel
• 64-Blt-Wlde Pixel Bus
• Versatile Direct-Color Modes:
- 24-Blt/Plxel with 8-Blt Overlay
(0, R, G, B)
-
24-Blt/Plxel (R, G, B)
16-Blt/Plxel (5,6, 5) XGA® Configuration
16-Blt/Plxel (6, 6, 4) Configuration
is-Bit/Pixel With i-Bit Overlay (1, 5, 5, 5)
TARGA® Configuration
- 12-Blt/Plxel With 4-Blt Overlay (4, 4, 4, 4)
• True-Color Gamma Correction
• Supports Packed Pixel Formats for
24-BltlPlxel Using a 32- or 64-BltlPlxel Bus
• 50% Duty Cycle Reference Clock for Higher
Screen Refresh Rates In Packed~24 Modes
• Programmable Frequency SynthesiS
Phase-Locked Loops (PLLs) for Dot Clock
and Memory Clock
• Loop Clock PLL Compensates for System
Delay and Ensures Reliable Data latching
• Versatile Pixel Bus Interface Supports
Little- and Blg-EndlanData Formats
• 135-,175-, and 22D-MHz Versions
• On-Chip Hardware Cursor, 64 x 64 x 2
Cursor (XGA and X-Windows Functionally
Compatible)
• Direct Interfacing to Video RAM
• Supports Overscan For Creation of Custom
Screen Borders
• Color-Keyed Switching of Direct Color and
and True Color or Overlay
• Hardware Port Select Switching Between
Direct Color and True Color or Overlay
• Triple 8-Blt D/A Converters
• Analog-Output Comparators for Monitor
Detection
•
•
•
•
RS-343A-Compatlble Outputs
Direct VGA Pass-Through Capability
Palette-Page Register
Horizontal Zooming Capability
• CMOS Technology
• DOS OM-1 Compatible for 16-Blt Video with
Graphics
• Additional VGA Clock Frequencies Pullups
Added to Pixel Port Terminals
;=
• Dot Clock Added to RCLK Output
Multiplexor
• VESA Advancad-Feature Connector (VAFC)
Baseline Connector Compatible
a:
• Pixel Port Bank Switching
• Data Manual Avallablet
W
s:w
Il.
....
o
:::l
C
o
a:
Il.
description
The TVP3027 is an advanced video interface palette (VIP) from Texas Instruments implemented in EPICTM O.B-micron
CMOS process. The TVP3027 is an enhanced TVP3026. As such, it supports all modes and pixel formats of the
TVP3026 VIP, including packed 24-bit true color with the phase-locked loop (PLL) generated, 50% duty cycle
reference clock. In addition, the TVP3027 supports 16-bit video switching with graphics and VAFC baseline
compatibility.
Like previous VIPs, data can be split into 4- or B-bit planes for pseudo-color mode or split into 12-, 16- or 24-bit
true-color and direct-color modes. For the 24-bit direct color modes, an 8-bit overlay plane is available. The 16-bit
direct- and true-color modes can be configured to IBM XGA® (5, 6, 5), TARGA® (1, 5, 5, 5), or (6, 6, 4) as another
existing format. An additional 12-bit mode (4, 4, 4, 4) is supported with 4 bits for each color and overlay. All color modes
support selection of little or big end ian data format for the pixel bus. Additionally, the device is also software compatible
with the IMSG176/8 and 8t476/8 color palettes.
Two fully programmable PLLs for pixel clock and memory clock functions are provided for dramatic improvements
in graphics system cost and integration. A third loop clock PLL is incorporated making pixel data latch timing much
t For the complete data manual. refer to the Grephics and Imaging Data Book (SLAD002).
EPIC is a tredemark of Texas Instruments Incorporeted.
XGA is a trademark of International Business Machines Corporation.
TARGA is a trademark of Truevision Incorporeted.
-!11 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAU.AS, TEXAS 75265
Copyright@ 1995. Texas Instruments Incorporated
TVP3027
VIDEO INTERFACE PALETTE
XLAS1 06 -
MAY 1995
description (continued)
\I
:a
o
C
c:
(')
-I
\I
simpler than with other eXisting color palettes. In addition, four digital clock inputs (two TTL- and two
ECLlTTL-compatible) may be utilized and are software selectable. The video clock provides a software. selected
divide ratio of the chosen pixel clock. The shift clock output may be used directly as the VRAM shift clock. The
reference clock output is driven by the loop clock PLL and provides a timing reference to the graphics accelerator.
Like the TVP3026, theTVP3027 integrates a complete, 64 x 64 x 2 hardware cursor on chip, making significant
graphics performance enhancements possible. Additionally, hardware port select and color keyed switching functions
are provided, giving the user $everal efficient means of producing graphical overlays on direct-color backgrounds.
The TVP3027 has three 256-by-8 color lookup tables with triple, 8-bit video, digital-te-analog converters (DACs)
capable of directly driving a doubly-terminated, 75-0 line. The lookup tables are designed with a dual-potted RAM
architecture that enables ultra-high speed operation. Sync generation is incorporated on the green output channel.
Horizontal sync (HSYNC) and vertical sync (VSYNC) are pipeline delayed through the device and optionally inverted
to indicate screen resolution to the monitor. A palette-page register Is available to select from multiple color maps in
RAM when 4-bit planes are usecl. This allows the screen colors to be changed with only one microprocessor write
cycle.
The device features a separate VGA bus which supports the integrated VGA modes in graphics accelerator
applications, allowing efficient support for VGA graphics and text modes. The separate bus is also useful.for accepting
data from the feature connector of most VGA-supported personal computers, without the need for external data
multiplexing.
.
The TVP3027 is highly system integrated. It can be connected to the serial port of video RAM (VRAM) devices without
external buffer logic and connected to many graphics engines directly. It also supports the split shift-register transfer
function, which is common to many industry standard VRAM devices.
.
The system-integration concept is even carried further to manufacturing test and field diagnosiS. To support these,
several highly integrated test functions have been designed to enable simplified testing of the palette and the entire
graphics system.
.
AVAILABLE OPTIONS
:a
m
<
-
TA
m
SPEED
135 MHz
:e
O·Cto 70·C
175 MHz
220 MHz
DAC
RESOLUTION
a Bits
a Bits
a Bits
PACKAGE
FLAT PACK
(PeE)
TVP3027":1 ~5PCE
TVP3027-175PCE
TVP3027-220PCE
~ThxAs
6-36
INSTRUMENTS
POST OFFICE BOX 855303 • DALlAS. TEXAS 7~
TVP3027
VIDEO INTERFACE PALETTE
XLAS106-MAY1995
functional block diagram
REF
FSADJUST
......."""',....-- COMP2
...""....,.",..,.~~~~~-\.~l-- COOPt
P(63-0)
LCU<
lOR
EVIDEO
------h
GRDY----,
lOG
VGA(7-0)
;=
lOB
W
:;:
w
a:
SENSE
I
0..
~V~ld~eo-S~lg-n-:al-~r- HSYNCOUT
Control
I-- VSYNCOUT
b
::)
c
o
a::
0..
Figure 1. Functional Block Diagram
~TExAs
. INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-37
H8
TVP3030
VIDEO INTERFACE PALETTE
XLAS111-MAY 1995
• Supports System Resolutions up to
1600 x 1280 at 86-Hz Refresh Rate
• Supports Color Depths of 4-, 8-, 16-, 24-,
and 32-BltlPlxel, All at Maximum Resolution
• 128-Blt-Wlde Pixel Bus
• Versatile Direct-Color Modes:
- 24-Blt/Pixel With 8-Blt Overlay
(0, R,G, B)
- 24-Blt/Plxel (R, G, B)
- 16-Blt/Plxel (5, 6, 5) XGA® Configuration
- 16-Bit/PIxel (6, 6, 4) Configuration
- 15-Bit/Plxel With 1-Blt Overlay (1, 5, 5, 5)
TARGA® Configuration
- 12-Blt/Plxel With 4-Blt Overlay (4, 4, 4, 4)
• True-Color Gamma Correction
• Supports Packed Pixel Formats for
24-BitlPlxel Using a 32-,64-, or 128-BltlPlxel
Bus
• 50% Duty Cycle Reference Clock for Higher
Screen Refresh Rates In Packed-24 Modes
• Programmable Frequency Synthesis PLLs
for Dot Clock and Memory Clock
• Loop Clock PLL Compensates for System
Delay and Ensures Reliable Data Latching
• Versatile Pixel Bus Interface Supports
LIttle- and Blg-Endlan Data Formats
• 175-,220-, and 250-MHz Versions
• On-Chip Hardware Cursor, 64 x 64 x 2
Cursor (XGA and X-Windows Functionally
Compatible)
• Byte Router Allows Use of R,G, or B
Direct-Color Channels Individually
• Direct Interfacing to Video RAM
• Supports Overscan for Creation of Custom
Screen Borders
• Color-Keyed Switching of Direct Color and
and True Color or Overlay
• Triple 8-Bit D/A Converters
• Analog Output Comparators for Monitor
Detection
•
•
•
•
•
•
RS-343A-Compatlble Outputs
Direct VGA Pass-Through Capability
Palette-Page Register
Horizontal Zooming Capability
CMOS Technology
Data Manual Avallablet
description
The TVP3030 is an advanced video interface palette (VIP) from Texas Instruments implemented in EPICTM O.8-micron
CMOS process. The TVP3030 is a 128-bit VI P that provides virtually all features of the 64-bit TVP3026. The TVP3030
doubles the pixel bus bandwidth; enabling 24-bit/pixel displays at resolutions up to 1600 x 1280 at a 76-Hz refresh
rate. Also, 24-bitlpixel graphics at 1280 x 1024 resolution may be implemented at higher refresh rates with or without
the use of pixel packing.
With the wider pixel bus comes additional 24-bitlpixel multiplexing modes: 4: 1 [128-bit bus width for overlay, red,
green, and blue (RGB)] and 5:1 (12Q-bit bus width for RGB). The byte router function allows pseudo-color or
monochrome image data to be taken from the red, green, or blue color channels. This enables high performance
24-bitlpixel architectures organized as red, green, and blue memory banks to provide 8-bitlpixel modes as well.
The TVP3030 extends the packed-24 modes to include 16:3 (pixels:load clocks) using a 128-bit pixel bus width. This
enables, for example, 24-bitlpixel graphics at 220 MHz pixel rate with only a 40 MHz VRAM serial output. With the
8:3 packed-24 mode (64-bit pixel bus width), a 24-bitlpixel display with 1280 x 1024 resolution may be packed into
4 megabytes of VRAM. A phase-locked loop (PLL) generated, 50 % duty cycle reference clock is output in the
packed-24 modes, maximizing VRAM cycle time.
The TVP3030 supports all of the pixel formats of the TVP3026 VIP. Data can be split into 4- or 8-bit planes for
pseudo-color mode or split into 12-, 16- or 24-bit true-color and direct-color modes. For the 24-bit direct color modes,
an 8-bit overlay plane is available. The 16-bit direct- and true-color modes can be configured to IBM XGA® (5, 6, 5),
TARGA® (5, 5, 5,1), or (6,6,4) as another existing format. An additional 12-bit mode (4, 4, 4, 4) is supported with
4 bits for each color and overlay. All color modes support selection of little or big end ian data format for the pixel bus.
Additionally, the device is also software compatible with the IMSG176/8 and Bt476/8 color palettes.
t For the complete data manual, refer to the Graphics and Imaging Data Book (SLAD002).
EPIC Is a trademark of Texas Instruments Incorporated.
XGA is a registered trademark of Intemational Business Machines Corporation.
TARGA is a registered trademark of Truevision Incorporated.
~ThxAs
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 752e5
6-39
TVP3030
VI.DEO INTERFACE PALETTE
XLASlll - MAY 1995.
description (continued)
Two fully programmable PLls for pixel clock and memory clock functions are provided for dramatic improvements
in graphics system cost and integration. A third loop clock PLL is incorporated making pixel data latch timing much
simpler than with other existing color palettes. In addition, an external digital clock input is provided for VGA modes.
The reference clock output is driven by the loop clock PLL and provides a timing reference to the graphics accelerator.
The shift clock output may be .used directly as the VRAM shift clock.
Like the TVP3026, the TVP3030 also integrates a complete, IBM XGA-compatible hardware cursor on chip, making
significant graphics performance enhancements possible. Additionally, color-keyed switching is provided, giving the
user an efficient means of combining graphic overlays and direct-color images on-screen.
The TVP3030 has three 256-by-8 color lookup tables with triple, 8-bit video, digital-to-analog converters (DACs)
capable of directly driving a doubly-terminated, 75-0 line. The lookup tables are designed with a dual-ported RAM
architecture that enables ultra-high speed operation.
The device features a separate VGA bus which supports the integrated VGA modes in graphics accelerator
applications, allowing efficient support for VGA graphics and text modes. The separate bus is also useful for accepting
data from the feature connector of most VGA-supported personal computers, without the need for external data
multiplexing.
The TVP3030 is highly system integrated. It can be connected to the serial port of VRAM devices without external
buffering and connected to many graphics engines directly. It also supports the split shift-register transfer operation,
which is common to many industry standard VRAM devices. To aid in manufacturing test and field diagnosis, several
highly integrated test functions have been designed to enable simplified testing of the palette and the entire graphics
subsystem.
AVAILABLE OPTIONS
TA
SPEED
DAC
RESOLUTION
175 MHz
O'Cto 70'C
220 MHz
250 MHz
PACKAGE
FLAT PACK
(PPA)
FLAT PACK
(MEP)
8 Bits
TVP303Q-175PPA
8 Bits
TVP303Q-220PPA
8 Bits
-
-
~TEXAS
6-40
INSTRUMENTS
POST OFFICE BOX 665303 • DALlAS. TEXAS 75266
TVP303Q-250MEP
TVP3030
VIDEO INTERFACE PALETTE
XLASll'l - MAY 1995
functional block diagram
True-
Pixel
Bus
P (127-0) -.....,"""~ Latch
128
LCLK
.....,._ _ _...,24
Byte
8
ROU1ar
VGA
VGA (7-0) -"""'....-t Latch
8
8
1--+----'+1
8
8
D (7-0)
8
RS (3-0)
4
RD
MPU
Registers
and
Control
Logic
Pixel
Clock
PLL
Memory
Clock
PLL
WR
II
~
....I
~
....I
()
()
II:
CIJ
~
d
CI
:5
III
l-
:)
~
s.:
c
....I
W
~ ::ICIJ
II.
. e e
....I
....I
~
....I
!j
Figure 1. Functional Block Diagram
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAu.AS. TEXAS 75265
6-41
TVP3030
VIDEO INTERFACE PALETTE
XLASlll.- MAY 1995
functional block diagram (continued)
REF
FSADJUST
1 - - - - - - - - - COMP2
1 - - -.....- - - - -
24
Direct
Color
Pipeline
Delay
COMP1
24
HlI----IOR
24
a
H ...._--IOG
>--If-+....- - I O B
Tast Function
and
Sense Comparator
2
64x64x2
Cursor RAM
and Conlrol
2
Video Signal
Control
!e
o
Figure 2. Functional Block Diagram
~TEXAS
6-42
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS, TEXAS 75265
I--- HSYNCOUT
r-- VSYNCOUT
TVP3409
VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC
XLAS092 - MAY 1995
res
• On-Chip Pll Clock Doubler
- 85 MHz Input
- 170 MHz Pixel Output
• Functionally Interchangeable With
ATT20C409
• 170/135 MHz
- 170 MHz 2:1 Multiplexer Rate for 8-Blt
Pseudocolor Operation
- 73 MHz True-Color Operation
• 16-Blt Pixel Port, Usable as 8-Blt Port
- Compatible With ATT20C490 Using P(7-0)
- Compatible With ATT20C498 Using
P(t5-0)
• 9 Software-Selectable Color Modes
- 24-Blt Packed Pixels
- 24-Blt 16-Blt True Color
- 8-Blt Pseudocolor
• 2:1 and 1:1 Pixel Multiplexing
• Power Dissipation of 1.19 W at 135 MHz Typ
• Dual Programmable-Clock Synthesizers
- Pixel Clock
- Memory Clock
- Reset to 28.322 MHz and 25.175 MHz
VGA Frequencies
- Strobe Input latches Frequency Select
lines
• 256 x 24 Color RAM
• Software Compatible With the AT&T
ATT20C4981499/409
• 68-Terminal Plastic leaded Chip Carrier
(PlCC) Package
• Data Manual Avallablet
applications
• Screen Resolutions (nonlnterlaced)
- 1600 x 1280, 8-BltlPixel, 60 Hz
- 1280 x 1024, 16-BitlPixel, 60 Hz
- 1024 x 768, 16-BitlPlxel, 85 Hz
- 1024 x 768, 24-BltlPixel, Pack,ed, 70 Hz
- 800 x 600, 24-BitlPlxel, Unpacked, 72 Hz
• True-Color Desktop, PC Add-in Card
3:
w
• X-Windows Terminals
s:w
• Green PCs
a:
D.
b=»
description
The TVP3409 is functionally interchangable with the ATT20C409 RAMDAC.
The TVP3409 RAMDAC supports 8-bit multiplexed operation that can be input on 16-pixel terminals. The TVP3409
retains register compatiblity with the ATT21 C498 and ATT20C499 parts.
The TVP3409 features 24obit, packed pixel modes that provide 24-bit graphics in a 3-Mbyte frame buffer at 1024 x
768 screen resolution. bual clock synthesizers offer two programmable and two fixed frequencies in phase-locked
loop (PLL) (A), and one programmable and three fixed frequencies in PLL (8). After reset the frequencies are:
PLL (A): 25.175, 28.322, 50, and 75 MHz
PLL (8): 30, 40, 50, and 60 MHz
AVAILABLE OPTIONS
TA
ODC to lODC
PACKAGE
SPEED
DAC
RESOLUTION
135 MHz
8 Bits
TVP3409-135CFN
170 MHz
8 Bits
TVP3409-170CFN
CHIP CARRIER
(FN)
t For the complete data manual, refer to the Graphics and Imaging Data Book (SLAD002).
¥
PRODUCT PREVIEW
l""'mIIIIon ....... produc\Iln tile _
or
01 _pmont. CharaCIe _ _ MIl o1h..
no ... deoIan gooII. T.... lnlllUmonIII ........ tile dgillto
or dlocontlnutlhaie produc\IwftIIout.-.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
6-43
o
o
a:
D.
TVP3409
VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC
XLAS092 - MAY 1995
functional block diagram
REF R$ET
~>---...
COMP
2411618
RED
256 x 24118
Color RAM
PCLK ---i.~1
•
2x,O.67
FS(1-0) --I.r~=;';;;;;;:;=-l
"'tJ
STROBE
:rJ
24
---I~
o
C
c:
OTCLKB
o-I
Figure 1. Functional Block Diagram
"'tJ
:rJ
m
-
<
m
:IE
~.lEXAs
6-44
GREEN
Multiplier
INSTRUMENTS
POST OFRCE BOX 665303 • DALLAS. TEXAS 75266
BLUE
TVP3703
VIDEO INTERFACE PALETTE
TRUE·COLOR CMOS RAMDAC
XLAS100 - FEBRUARY 1995
• Fully Integrated Dual Clock Synthesizer and
16-81t Pixel Port True-Color RAMDAC
• Two Phase-locked-Loop (PLL) Synthesizers
Provide Independently Controlled Video and
Memory Clock Outputs
• Functionally Interchangeable with STG1703
• On-Chip PLL Clock Reference Requires
Single External Crystal
• 16-81t Pixel Port Supports VGA High-Color
and True-Color Standards Up to 170 MHz
• Programmable Power-Down Features
• On-Chip Cyclic Redundancy Check (CRC)
Test
• Data Sheet Availablet
applications
• Screen resolutions (non Interlaced)
- 1600 x 1280, 8 bit/pixel, 6d Hz
- 1280 x 1024,16 bit/pixel, 60 Hz
- 1024 x 768,16 bit/pixel, 85 Hz
- 1024 x 768,24 bit/pixel, packed, 70 Hz
- 800 x 600, 24 bit/pixel, unpacked, 72 Hz
• Tru8-Color desktop, PC add-In cards
3=
w
description
The TVP3703 is a super VGA (SVGA) compatible, true-color CMOS RAMDAC with integrated clock
synthesizers that can provide the memory and pixel clock signals for a PC graphics subsystem. The video clock
can be one of two VGA base frequencies or 14 VESA standard frequencies that can also be reprogrammed
through the standard microport interface.
:;
w
a..
a:
The memory clock output is also user programmable at frequencies up to 80 MHz. The pixel modes supported
by the TVP3703 include:
b
•
Serializing 16-bit pixel port providing 170 MHz 8-bit and 73 MHz 24-bit packed pixel modes using an internal
PLL
•
16-bit pixel port providing faster high-color/true-color operation up to the 11 O-MHz sampling rate
c
o
a:
•
8-bit pixel port giving standard SVGA and high-color/true-color modes up to the 11 O-MHz sampling rate
The 68-terminal plastic leaded chip carrier (PLCC) package is designed to be interchangeable with the
STG1703.
AVAILABLE OPTIONS
TA
0·Cto70·C
SPEED
DAC
RESOLUTION
PACKAGE
CHIP CARRIER
(FN)
135 MHz
SBits
TVP3703-135CFN
170 MHz
S Bits
TVP3703-170CFN
t For the complete data sheet, refer to the Graphics and Imaging Data book (SLAD002).
PRODUCT PREVIEW
I _ n .......
praducIa In 1110 _
Dr
oI'-,..nt
C_ _ Ind _
...
~ _1notrumInIII_1IIo rIgIIIlD
ngo or dlscon1l=rJ: prod_ wIthouI..ace.
~
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 656303 • DAUAS. TEXAS 75266
6-45
:::)
a..
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
XLAS100-' FEBRUAFIY 1995
functional block diagram
MCLK
XIN
XOUT
VCLK
D{7-0)
RD
WR
RS()'RS2
Micro Port
VS(3-O)
STROBE
24
258x8Blt
Color Palette
PIXMIX
P(15-0)
Pixel
Latchea
Multiplexor
Mask
>------4t---- RED
258xB Bit
Color Palette
258x8Blt
Color Palette
__--GREEN
r-""1-__ BLUE
3
"'tJ
::D
PCLK
o
tJ
c:
~
Figure 1. Functional Block Diagram
"'tJ
::D
m
<
m
-
:e
~1ExAs
6-46
INSTRUMENTS
POST OFFICE SOX 855303 • DALlAS. TEXAS 75266
7-1
cQ)
...
Q)
s:
Q)
::J
t:
-
Q)
en
7-2
TLC32046C, TLC32046I, TLC32046M
Data Manual
Wid~Band Analog Interface
Circuit
~I
1D'As
NSTIWMENTS
7-3
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to. make changesto its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with Tl's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICE~
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
~es~~
.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1995, Texas Instruments Incorporated
7-4
Contents
Section
Title
Page
1
Introduction ............................................................... 7-9
1.1 Features ......................................................... ; ... 7-10
1.2 Functional Block Diagrams ............................................. 7-11
1.3 Terminal Assignments ................................................. 7-14
1.4 Ordering Information .................................................. 7-14
1.5 Terminal Functions .................................................... 7-15
2
Detailed Description ......................................................
2.1 Internal Timing Configuration ...........................................
2.2 Analog Input .........................................................
2.3 AID Band-Pass Filter, Clocking, and Conversion
Timing ................................................................
2.4 AID Converter ........................................................
2.5 Analog Output ........................................................
2.6 D/A Low-Pass Filter, Clocking, and Conversion
Timing ...............................................................
2.7 D/A Converter ........................................................
2.8 Serial Port ...........................................................
2.9 Synchronous Operation ................................................
2.9.1
One 16-Bit Word (Dual-Word [Telephone Interface] or Word Mode) ..
2.9.2 Two 8-Bit Bytes (Byte Mode) ....................................
2.9.3 Synchronous Operating Frequencies .............................
2.10 Asynchronous Operation .........................•.....................
2.10.1 One 16-Bit Word (Word Mode) ..................................
2.10.2 Two 8-Bit Bytes (Byte Mode) ....................................
2.10.3 Asynchronous Operating Frequencies ............................
2.11 Operation of TLC32046 With Internal Voltage Reference ...................
2.12 Operation of TLC32046 With External Voltage Reference ..................
2.13 Reset ...............................................................
2.14 Loopback ................................................. ; ..........
2.15 Communications Word Sequence .......................................
2.15.1 DR Word Bit Pattern ...........................................
2.15.2 Primary DX Word Bit Pattern ....................................
2.15.3 Secondary DX Word Bit Pattern .................................
2.16 Reset Function .......................................................
~17 Power-Up Sequence ..................................................
2.18 AIC Register Constraints ...............................................
2.19 AIC Responses to Improper Conditions ..................................
2.20 Operation With Conversion Times Too Close Together .....................
\
7-17
7-18
7-20
7-20
7-20
7-20
7-20
7-20
7-21
7-21
7-21
7-21
7-22
7-22
7-22
7-22
7-22
7-23
7-23
7-23
7-23
7-24
7-24
7-25
7-26
7-26
7-27
7-27
7-27
7-28
7-5
Contents (Continued)
Section
Title
2.21 More Than One Receive Frame Sync Occurring Between Two Transmit
Frame Syncs - Asynchronous Operation ................................•
2.22 More Than One Transmit Frame Sync Occurring Between Two Receive
Frame Syncs - Asynchronous Operation .................................
2.23 More than One Set of Primary and Secondary DX Serial Communications
Occurring Between Two Receive Frame Syncs (See DX Serial Data Word
Format section) - Asynchronous Operation ..............................
2.24 System Frequency Response Correction ...........................•.....
2.25 (Sin x)/x Correction ..................................................•.
2.26 (Sin x)/x Roll-Off for a Zero-Order Hold Function ..........................
2.27 Correction Filter ......................................................
2.28 Correction Results ...•................................................
2.29 TMS320 Software Requirements ........................................
3
7-6
Specifications . ................. '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range ....
3.2 Recommended Operating Conditions ....................................
3.3 Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, Vcc+ =5 V, Vcc- =-5 V, Voo =5 V ................
3.3.1
Total Device, MSTR ClK Frequency = 5.184 MHz,
'
Outputs Not Loaded ...........................................
3.3.2 Power Supply Rejection and Crosstalk Attenuation . . . . . . . . . . . . . . . ..
3.3.3 Serial Port ..................................•.................
3.3.4 Receive Amplifier Input . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.3.5 Transmit Filter Output ..........................................
3.3.6 Receive and Transmit Channel System Distortion, SCF Clock
Frequency =288 kHz ..........................................
3.3.7 Receive Channel Signal-to-Distortion Ratio .......................
3.3.8 Transmit Channel Signal-to-Distortion Ratio ......................
3.3.9 Receive and Transmit Gain and Dynamic Range ..................
3.3.10 Receive Channel Band-Pass Filter Transfer Function,
SCF fclock =288 kHz, Input (IN+ -IN-) Is A +3-V Sine Wave .......
3.3.11 Receive and Transmit Channel low-Pass Filter Transfer Function,
SCF fclock = 288 kHz ..........................................
3.4 Operating Characteristics Over Recommended Operating Free-Air
Temperature Range, Vcc+ =5 V, Vcc- =-5 V, Voo =5 V ................
3.4.1
Receive and Transmit Noise (measurement includes low-pass and
band-pass switched-capacitor filters) .............................
3.5 Timing Requirements ..................................................
3.5.1
Serial Port Recommended Input Signals,
TlC32046C and TlC320461 ....................................
3.5.2 Serial Port Recommended Input Signals, TlC32046M .......... ~ •..
3.5.3 Serial Port - AIC Output Signals, CL = 30 pF for SHIFT ClK Output,
CL = 15 pF, For All Other Outputs, TlC32046C and TlC320461 ...•.
Page
7-28
7-29
7-29
7-30
7-30
7-30
7-31
7-31
7-32
7-33
7-33
7-33
7-34 ,
7-34
7-34
7-34
7-35
7-35
7-35
7-36
7-36
7-36
7-37
7-37
7-38
7-38
7-38
7-38
7-38
7-39
Contents (Continued)
Section
Title
3.5.4
Page
Serial Port - AIC Output Signals, CL = 30 pF for SHIFT ClK Output,
CL = 15 pF, For All Other Outputs, TlC32046M .................... 7-39
4
Parameter Measurement Information ....................................... 7-41
4.1 TMS3201 0ITMS320C15 - TlC32046 Interface Circuit ..................... 7-44
5
Typical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-47
6
Application Information ................................................... 7-67
7-7
List of Illustrations
Figure
1-1.
1-2.
1-3.
2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
6-1.
6-2.
Title
Page
7-12
Dual-Word (Telephone Interface) Mode ............................. ..
Word Mode ...................................................... .
7-13
Byte Mode ....................................................... .
7-13
Asynchronous Internal Timing Configuration .......................... .
7-19
7-24
Primary and Secondary Communications Word Sequence ............. .
7-27
Reset on Power-Up Circuit ......................................... .
7-28
Conversion Times Too Close Together ............................... .
More Than One Receive Frame Sync Between Two
Transmit Frame Syncs ............................................. .
7-29
More Than One Transmit Frame Sync Between
7-29
Two Receive Frame Syncs ......................................... .
More Than One Set of Primary and Secondary OX
Serial Communications Between Two Receive Frame Syncs ........... .
7-30
First-Order Correction Filter ........................................ .
7-31
7-41
IN + and IN - Gain Control Circuitry .................................. .
Dual-Word (Telephone Interface) Mode Timing ....................... : .
7-42
Word Timing ......•...............................................
7-42
Byte-Mode Timing ................................................ .
7-43
Shift-Clock Timing .................................. ; ............. .
7-44
TMS3201 OrrMS320C15-TLC32046 Interface Timing ................. .
7-44
TMS32010rrMS320C15 - TLC32046 Interface Circuit ................. .
7-45
AIC Interface To The TMS32020/C25 Showing Decoupling Capacitors
and Schottky Diode ................................................... 7-57
External Reference Circuit for TLC32046 ................................ 7-57
List of Tables
Table
2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
4-1.
7-8
Title
Page
ModErSelection Function Table ..................................... .
Primary OX Serial Communication Protocol .......................... .
Secondary OX Serial Communication Protocol ........................ .
AIC Responses to Improper Conditions .............................. .
(Sin x)/x Roll-Off Error ............................................. .
(Sin x)/x Correction Table for f8 =8000 Hz and f8 =9600 Hz ............ .
Gain Control Table ............................................... .
7-17
7-25
7-26
7-28
7-31
7-32
7-41
1 Introduction
The TLC32046C, TLC320461, and TLC32046M wide-band analog interface circuits (AI C) are a complete
analog-ta-digital and digital-to-analog interface system for advanced digital signal processors (DSPs)
similar to the TMS32020, TMS320C25, and TMS320C30. The TLC32046C and TLC320461 offer a powerful
combination of options under DSP control: three operating modes (dual-word [telephone interface], word,
and byte) combined with two word formats (8 bits and 16 bits) and synchronous or asynchronous operation.
It provides a high level of flexibility in that conversion and sampling rates, filter bandwidths, input circuitry,
receive and transmit gains, and multiplexed analog inputs are under processor control.
This AIC features a
•
band-pass switched-capacitor antialiasing input filter
•
14-bit-resolution AID converter
•
14-bit-resolution D/A converter
•
low-pass switched-capacitor output-reconstruction filter.
The antialiasing input filter comprises eighth-order and fourth-order CC-type (Chebyshev/elliptic
transitional) low-pass and high-pass filters, respectively. The input filter is implemented in switchedcapacitor technology and is preceded by a continuous time filter to eliminate any possibility of aliasing
caused by sampled data filtering. When low-pass filtering is desired, the high-pass filter can be switched
out of the signal path. A selectable auxiliary differential analog input is provided for applications where more
than one an~log input is required.
The output-reconstruction filter is an eighth-order CC-type (Chebyshev/elliptic transitional low-pass filter)
followed by a second-order (sin x)/x correction filter and is implemented in switched-capacitor technology.
This filter is followed by a continuous-time filter to eliminate images of the sample data signal. The on'"board
(sin x)/x correction filter can be switched out of the signal path using digital signal processor control.
The AID and D/A architectures ensure no missing codes and monotonic operation. An internal voltage
reference is provided to ease the design task and to provide complete control over the performance of the
IC. The internal voltage reference is brought out to REF. Separate analog and digital voltage supplies and
ground are provided to minimize noise and ensure a wide dynamic range. The analog circuit path contains
only differential circuitry to keep noise to a minimum. The exception is the DAC sample-and-hold, which
utilizes pseudo-clifferential circuitry.
The TLC32046C is characterized for operation from O°C to 70°C. the TLC320461 is characterized for
operation from -40°C to 85°C, and the TLC32046M is characterized for operation from -55°C to 125°C.
7-9
1.1
Features
•
14-Blt Dynamic Range ADC and DAC
•
•
16-Blt Dynamic Range Input With Programmable Gain
Synchronous or Asynchronous ADC and DAC Sampling Rates Up to 25,000 Samples Per
Second
'
.
•
Programmable Incremental ADC and DAC Conversion Timing Adjustments
•
Typical Applications
- Speech Encryption for Digital Transmission
- Speech Recognition and Storage Systems
- Speech Synthesis
- Modems at 8-kHz, 9.6-kHz, and 16-kHz Sampling Rates
- Industrial Process Control
- Blomedlcallnstrumentatlon
- Acoustical Signal Processing
•
- Spectral Analysis
- Instrumentation Recorders
- Data Acquisition
Swltched·Capacltor Antiallaslng Input Filter and Output-Reconstruction Filter
•
Three Fundamental Modes of Operation: Dual-Word (Telephone Interface), Word, and Byte
•
•
60o-mil Wide N Package
Digital Output in Twos Complement Format
•
CMOS Technology
FUNCTION TABLE
SYNCHRONOUS
DATA
(CONTROL
COMMUNICATIONS
REGISTER
FORMAT
BIT D5 = 1)
ASYNCHRONOUS
(CONTROL
REGISTER
BIT D5=0)
16-bit format
Dual-word
(telephone
interface) mode
Dual-word
Terminal 13 = 0 to5 V
(telephone interface) Terminal 1 - 0 to 5 V
mode
16-bit format
Word mode
Word mode
Terminal 13 .. VCe- (-5 V nom) TMS32020,
TMS320C25,
Terminal 1 - VCC+ (5 V nom)
TMS320C30,
indirect
interface to
TMS320C10.
(see Figure 7).
8-bit format
(2 bytes required)
Byte mode
Byte mode
Terminal 13- VCC-(-5 V nom) TMS320C17
Terminal 1 .. VCC- (-5 V nom)
7-10
FORCING CONDITION
DIRECT
INTERFACE
TMS32020,
TMS320C25,
TMS320C30
1.2
Functional Block Diagrams
WORD OR BYTE MODE
IN + 2;;.;;,8t--to.....
IN_2~5t-........~
AUX IN + 24~_........
AUX IN _ 23
........_ .........
Low-Pass
Filter
Serial
Port
AID
5 DR
4 FSR
3
Receive Section
High-Pass
Filter
r,:-- -:::1
I
------------------~I
10 SHIFTCLK
I
I
I
-~
Internal
Voltage
Reference
L.::_
EODR
II MSTRCLK
1 WORD.
BYTE
13 CONTROL
12 DX
14 FSX
Low·Pass
Filter
11 EODX
o
20
VCC+
8
REF
DGTl
VDD
GND (DIGITAL)
DUAL·WORD (TELEPHONE INTERFACE) MODE
...,;.1I..-_...
IN+ 2
IN _ 25,ut-_.........
AUX IN + 2;;.;.4..---1".....
AUX IN _ 2_3..---t.o~
Low-Pass
Filter
AID
Serial
Port
5
4
3
Receive Section
High-Pass
Filter
II
r,:-
I
------------------~I
~~~
Reference
Low-Pass
Filter
VCC+
D110UT
MSTRCLK
10
Internal
L.::_
20
DR
FSR
SHIFTCLK
1_
FSD
13
DATA DR
12
DX
14_
FSX
11
D100UT
8
VCC-
DGTL
VDD
GND (DIGITAL)
REF
7-11
FRAME SYNCHRONIZATION FUNCTIONS
I
,',
c
Function
Frame Sync Output
Receiving serial data on OX from processor to internal DAC
FSXlow
Transmitting serial data on DR from internal ADC to processor, primary communications
FSRlow
Transmitting serial data on DR from Data-DR to processor, secondary communications In
dual-word (telephone interface) mode only
FSD low
5V
201
26,
Analog In
25
VCC+
IN+
IN-
-5V
191
Serial Data Out
VCC5
DR
TLC32046
4
FSR
3
D110UT
...
~
Analog Out
22
21
OUT+
DX
12 Serial Data In
TMS32020,
TMS320C25,
TMS320C30, or
Equivalent 16-Blt DSP
OUTFSX
14
TTL or CMOS
Logic Levels
11
D100UT
~
""
1
FSD
Secondary Commu nlcatlon (S88 Table above) .
13 Serial Data Input
DATA-DR ,
16-Blt Format TTL
orCMOSLolc
g Levels
Figure 1-1. Dual·Word (Telephone Interface) Mode
When the DATA-DR/CONTROL input is tied to a logic signal source varying between 0 and 5 V, the
TLC32046 is in the dual-word (telephone interface) mode.This logic signal is routed to the DR line for input
to the DSP only when data frame synchronization (FSD) outputs a low level. The FSD pulse duration is 16
shift clock pulses. Also, in this mode, the control register data bits 010 and 011 appear on 01 OOUT and
D110UT, respectively, as outputs.
7-12
5V
.. 26
Analog In
.. 25
-5V
201
191
vcc+
vccDR
IN+
IN-
TLC32046
~
22
:""
21
OUT+
3
Serfal Data In
12
DX
TMS32020,
TMS32OC25,
TMS320C30,
or Equivalent
16-BltDSP
OUT14
FSX
TTL or CMOS
Logic Levels
~
11
EODX
VCC+
(5 V nom)
.
4
FSR
EODR
Analog Out
Serfal Data Out
5
---.
VCC-
1
WORD-BYTE
(-5Vnom)
13
CONTROL
,
Figure 1-2. Word Mode
5V
26
~
Analog In
25
~
-5V
201
191
VCC+
VCCDR
IN+
IN-
TLC32046
FSR
EODR
...
22
AnalogOut
...
21
OUT+
DX
EODX
...
1
Serfal Data Out
~
4
~
.
3
12
Serial Data In
TMS320C17 or
Equivalent
8-Blt Serfallnterface
(2 bytes required)
OUTFSX
VCC(-5 V nom) •
5
WORD-BYTE
CONTROL
14
r
11
TTL or CMOS
Logic Levels
~
r
13
...
VCC(-5 V nom)
Figure 1-3. Byte Mode
The word or byte mode is selected by first connecting the DATA-DR/CONTROL input to Vee-.
FSDIWORD-BYTE becomes an input and can then be used to select either word or byte transmission
formats. The end-of-data transmit (EODX) and the end-of-data receive (EODR) signals respectively, are
used to signal the end of word or byte communication (see the Terminal Functions section).
7-13
1.3
Terminal Assignments
FK OR FN PACKAGE
(TOP VIEW)
Jt OR N PACKAGE*
(TOP VIEW)
FSOIWORO-BYTE§
RESET
011OUT/EOOR§
FSR
DR
MSTR CJ.K
VOO
REF
OGTLGNO
SHIFTCLK
0100UT/EOOX§
OX
:OATA-ORICONTROL§
FSX
NU
NU
IN+
INAUXIN+
AUXINOUT+
OUTVCC+
VCCANLGGNO
ANLGGNO
NU
NU
54 3 2 1 28272\5
DR
MSTRCLK
VOO
REF
OGTLGNO
SHIFTCLK
0100UTtmm(§
IN24 AUXIN+
23 AUXIN22 OUT+
21 OUT20 Vcc+
19 Vcc-
6
7
8
9
10
NU - Nonusable; no extemal connection should be made to these tenninals.
t Refer to the mechanical data for the JT package.
*
600-mil wide
.
§ The portion of th$ tenninal name to the left of the slash is used for the duaJ.word (telephone interface) mode.
The portion of the tennlnal name to the right of the slash Is used for word-byte mode.
1.4
Ordering Information
AVAILABLE OPTIONS
PACKAGE
TA
O°C to 70°C
-40°C to 85°C
-55°C to 125°C
7-14
PLASTIC CHIP
CARRIER
(FN)
PLASTIC DIP
(N)
TLC32046CFN
TLC32046CN
TLC32046IFN
TLC32046IN
CERAMIC DIP
CHIP CARRIER
(J)
(FK)
TLC32046MJ
TLC32046MFK
--1.5
Terminal Functions
TERMINAL
NAME
ANLGGND
NO.
1/0
DESCRIPTION
Analog ground return for all internal analog circuits. Not internally connected to DGTL
GND.
17,18
AUX IN+
24
I
Noninverting auxiliary analog input stage. AUX IN+ can be switched into the band-pass
filter and ADC path via software control. If the appropriate bit in the control register is
a 1, the auxiliary inputs replace the IN+and IN-inputs.lfthebitisaO, the IN+and INinputs are used (see the DX Serial Data Word Format).
AUX IN-
23
I
Inverting auxiliary analog input (see the above AUX IN + description).
DATA-DR
13
I
The dual-word (telephone interface) mode, selected by applying an input logic level
between 0 and 5 V to DATA-DR, allows this terminaltofunction as a data input. The data
[s then framed by the FSD signal and transmitted as an output to the DR line during
secondary communication. The functions FSD, D11 OUT, and D1 OOUT are valid with
this mode selection (see Table 2-1).
When CONTROL is tied to V~he device is in the word or byte mode. The functions
WORD-BYTE, EODR, and EODX are valid in this mode. CONTROL is then used to
select either the word or byte mode (see Function Table).
CONTROL
DR
5
0
DR is used to transmit the ADC output bits from the Ale to the TMS320 serial port. This
transmission of bits from the AIC to the TMS320 serial port is synchronized with
SHIFTCLK.
DX
12
I
DX is used to receive the DAC input bits and timing and control information from the
TMS320. This serial transmission from the TMS320 serial port is synchronized with
SHIFTCLK.
D100UT
11
0
In the dual-word (telephone interface) mode, bit D1 0 ofthe control register is output to
D1 OOUT. When the device is reset, bit D1 0 is initialized to 0 (see DX Serial Data Word
Format). The output update is immediate upon changing bit D10.
EODX
D110UT
EODR
End-of-data transmit. During the word-mode timing, a low-going pulse occurs on EODX
imrnediately after the 16 bits of DAC and control or register information have transmitted
from the TMS320 serial port to the AIC.This signal can be used to interrupt a
microprocessor upon completion of serial communications. Also, this signal can be
used to strobe and enable external serial-to-parallel shift registers, latches, or external
FI FO RAM and to facilitate parallel data bus communications between the DSP and the
serial-to-parallel shift registers. During the byte-mode timing, this signal goes low after
the first byte has been transmitted from the TMS320 serial port to the AIC and is kept
low until the second byte has been transmitted. The TMS320C17can use this low-going
signal to differentiate first and second bytes.
3
0
In the dual-word (telephone interface) mode, bit D11 of the control register is output to
D110UT. When the device is reset, bit D11 is initialized to 0 (see DX Serial Data Word
Format). The output update is immediate upon changing bit D11.
End-of-data receive. During the word-mode timing, a low-going pulse occurs on EODR
immediately after the 16 bits of AID information have been transmitted from the AIC to
the TMS320 serial port. This signal can be used to interrupt a microprocessor upon
completion of serial communications. Also, this signal can be used to strobe and enable
external serial-to-parallel shift registers,latches, or external FIFO RAM, and to facilitate
parallel data bus communications between the DSP and the serial-to-parallel shift
registers. During the byte-mode timing, this signal goes low after the first byte has been
transmitted from the AIC to the TMS320 serial port and is kept low until the second byte
has been transmitted. The TMS320C17 can use this low-going signal to differentiate
between first and second bytes.
7-15
1.5
Terminal Functions (continued)
TERMINAL
NAME
NO.
DGTL
9
FSD
1
WORD-BYTE
1/0
,DESCRIPTION
0
Frame sync data. The FSD output remains high during primary communication. In the
dual-word (telephone interface) mode, FSD is identical to FSX during secondary
communication.
I
WORD-BYTE allows differentiation between' the word and byte data format (see
DATA-DR/CONTROL and Table 2-1 for details).
Digital ground for all internal logic circuits. Not internally connected to ANLG GND.
FSR
4
0
Frame sync receive. FSR is held low during bit transmission. When FSR goes low, the
TMS320 serial port begins receiving bits from the AIC via DR of the AIC. The most
significant DR bit is present on DR before FSR goesJow (see Serial Port Sections and
Internal Timing Configuration Diagrams).
FSX
14
0
Frame sync transmit. When FSX goes low, the TMS320 serial port begins transmitting
bits to the AIC via DX of the AIC. FSX is held low during bit transmission (see Serial Port
Sections and Internal Timing Configuration Diagrams).
IN+
26
I
Noninverting input to analog input amplifier stage
IN-
25
I
Inverting input to analog input amplifier stage
MSTRCLK
6
I
The master clock signal is used to derive all the key logic signals of the AIC, such as
the shift clock, the switched-capacitor filter clocks, and the AID and DIA timing signals.
The Internal Timing Configuration diagram shows how these key signals are derived.
The frequencies of these signals are synchronous submultiples of the master, clock
frequency to eliminate unwanted aliasing when the sampled analog signals are
transferred between the switched-capacitor filters and the ADC and DAC converters
(see the Internal Tir:ning Configuration).
OUT+
22
0
Noninverting output of analog output power amplifier. OUT+ drives transformer hybrids
or high-impedance loads directly in a differential or a single-ended configuration.
OUT-
21
0
Inverting output of analog output power amplifier. OUT-is functionally identical with and
complementary to OUT+.
REF
8
1/0
The internal voltage reference is brought out on REF. An extemal voltage reference can
be applied to REF to override the internal voltage reference.
RESET
2
I
A reset function is provided to initialize TA, TA', TB, RA, RA', RB (see Figure 2-1), and
the control registers. This reset function initiates serial communications between the
AIC and DSP. The reset function initializes all AIC registers, including the control
register. After a negative-going pulse on RESET, the AIC registers are initialized to
provide a 16-kHz data conversion rate for a 10.368-MHz master clock input Signal. The
conversion rate adjust registers, TA' and RA', are resetto 1. The CONTROL register bits
are reset as follows (see AIC DX Data Word Format section):
D11 .. 0, D10 .. 0, D9 .. 1, D7 - 1, D6 = 1, D5 = 1, D4 = 0, D3 .. 0, D2 = 1
The shift clock (SCLK) is held high during RESET.
This initialization allows normal serial-port communication to occur between the AIC
and the DSP.
SHIFTCLK
10
0
The shift clock signal is obtained by dividing the master clock signal frequency by four.
SHIFT CLK is used to clock toe serial data transfers of the AIC.
VDD
7
Digital supply voltage, 5 V ±5%
VCC+
20
Positive analog supply voltage, 5 V ±5%
VCC-
19
Negative analog supply voltage, -5 V ±5%
7-16
2
Detailed Description
Table 2-1. Mode-Selection Function Table
DATA-DR!
CONTROL
(Terminal 13)
FSDI
WORD-BYTE
(Terminal 1)
CONTROL
OPERATING
SERIAL
REGISTER
MODE
CONFIGURATION
BIT (05)
DESCRIPTION
Terminal functions DATA-DRT,
FSDt, D110UT, and D100UT
are applicable in this
Dual Word
configuration. FSD is asserted
Synchronous,
Data in
FSD out
(Telephone
during secondary
1
(0 Vto 5 V)
(OVt05V)
One 16-Bit Word
Interface)
communication, but FSR is not
asserted. However, FSD
remains high during primary
communication.
Terminal functions DATA-DR T,
FSDt, D11 OUT, and D100UT
are applicable in this
configuration. FSD is asserted
during secondary
communication, but FSR is not
Dual Word
asserted. However, FSD
Data in
FSDout
Synchronous,
(Telephone
0
(0 V to 5 V)
(OVt05V)
One 16-Bit Word remains high during primary
Interface)
communication. If secondary
communications occur while
the ND conversion is being
transmitted from DR, FSD
cannot go low, and data from
DATA-DR cannot go onto DR.
Terminal functions
Synchronous,
CONTROLt, WORD-BYTEt,
1
One 16-Bit Word EODR:and EODX are
applicable in this configuration.
WORD
VCC+
Terminal functions
CONTROLt, WORD-BYTEt,
Asynchronous,
0
One 16-bit Word EODR, and EODX are
applicable in this configuration.
VCCTerminal functions
Synchronous,
CONTROLt, WORD-BYTEt,
1
Two a-Bit Bytes
EODR, and EODX are
applicable in this configuration.
BYTE
VCCTerminal functions
CONTROLt, WORD-BYTEt,
Asynchronous,
0
Two a-Bit Bytes
EODR, and EODX are
applicable in this configuration.
t DATA-DR/CONTROL has an internal pulldown resistor to -5 V, and FSDIWORD-BYTE has an internal pullup resistor
t05 V.
.
7-17
2.1
Internal Timing Configuration (see Figure 2-1)
All the internal timing of the AIC is derived from the highLfrequency clock signal that drives the master clock
input. The shift clock signal, which strobes the serial port data between the AIC and DSP, Is derived by
dividing the master clock input signal frequency by four.
The TX(A) counter and the TX(B) counter, which are driven by the master clock signal, determine the D/A
conversion timing. Similarly, the RX(A) counter and the RX(B) counter determine the AID conversion timing.
In order for the low-pass switched:-eapacitor filter in the D/A path (see Functional Block Diagram) to meet
its transfer function specifications, the frequency of its clock input must be 288 kHz. If the clock frequency
is not 288 kHz, the filter transfer function frequencies are frequency-scaled by the ratios of the clock
frequency to 288 kHz:
Absolute Frequency (kHz)
Normalized Frequency x SCF fclock (kHz)
288
(1 )
For Low-Pass SCF fclock > 288 kHz, please call the factory.
To obtain the specified filter response, the combination of master clock frequency and the TX(A) counter
and the RX(A) counter values must yield a 288-kHz switched:-eapacitor clock signal. This 288-kHz clock
signal can then be divided by the TX(B) counter to establish the D/A conversion timing.
The transfer function of the band-pass switched:-eapacitor filter in the AID path (see Functional Block
Diagram) is a composite of its high-pass and low-pass transfer functions. When the shift:-elock frequency
(SCF) is 288 kHz, the high-frequency roll-off of the low-pass section will meet the band-pass filter transfer
function specification. Otherwise, the high-frequency roll-off is frequency-scaled by the ratio of the
high-pass section SCF clock to 288 kHz (see Figure 5-5). The low-frequency roll-off of the high-pass section
meets the band-pass filter transfer function specification when the AID conversion rate is 16 kHz. If not, the
low-frequency roll-off of the high-pass section is frequency-scaled by the ratio of the AID conversion rate
to 16 kHz.
The TX(A) counter and the TX(B) counter are reloaded each D/A conversion period, while the RX(A) counter
and the RX(B) counter are reloaded every AID conversion period. The TX(B) counter and the RX(B) counter
are loaded with the values in the TB and RB registers, respectively. Via software control, the TX(A) counter
can be loaded with the TA register, the TA register less the TA' register, or the TA register plus the TA' register.
By selecting the TA register less the TA' register option, the upcoming conversion timing occurs earlier by
an amount of time that equals TA' times the signal period of the master clock. If the TA register plus the TA'
register option is executed, the upcoming conversion timing occurs later by an amount of time that equals
TA' times the signal period of the master clock. Thus, the D/A conversion timing can be advanced or
retarded. An identical ability to alter the AID conversion timing is provided. However, the RX(A) counter can
be programmed via software control with the RA register, the RA register less the RA' register, or the RA
register plus the RA' register.
The ability to advance or retard conversion timing is particularly useful for modem applications. This feature
allows controlled changes in the AID and D/A conversion timing and can be used to enhance signal-to-noise
performance, to perform frequency-tracking functions, and to generate nonstandard modem frequencies.
If the transmit and receive sections are configured to be synchronous, then the low-pass and band-pass
switched:-eapacitor filter clocks are derived from the TX(A) counter. Also, both the D/A and AID conversion
timings are derived from the TX(A) counter and the TX(B) counter. When the transmit and receive sections
are configured to be synchronous, the RX(A) counter, RX(B) counter, RA registe2 RN register, and RB
registers are not used.
7-18
TMS320DSP
MASTER CLOCK
5.184 MHz
10.368 MHz
SHIFT CLOCK
1.296 MHz
2.592 MHz
SCFCLOCK
Low-Pass Filter,
(sin x)/x Filter
Transmit Section
D/A Conversion
Timing
D1t DO SELECT
o 0 TA
o 1 TA+TA'
1 0 TA-TA'
1 1 TA
TX(A) Counter
(6 Bits)
IJ~~~[)=~~
TX (B) Counter
288 kHz ....._ _ _ _'"
576kHz
7.20 kHz for TB ., 40
8.00 kHz for TB .. 36
9.60 kHz for TB '"' 30
14.4 kHz for TB = 20
16.0 kHz for TB = 18
19.2 kHz for TB = 15
D/A Conversion
Frequency
Low-Pass Filter
Receive Section
AID Conversion
Timing
9
D1t DO
o 0
o 1
1 0
1 1
SELECT
RA
RA+ RA'
RA-RA'
RA
18
RX (A) UOllnIBlri
(6 Bits)
7.20 kHz for RB ., 40
8.00 kHz for RB .. 36
9.60 kHz for RB = 30
14.4 kHz for RB .. 20
16.0 kHz for RB .. 18
19.2 kHz for RB .. 15
High-Pass Filter,
AID Conversion
Frequency
t These control bits are described in the DX Serial Data Word Format section.
NOTES: A. Tables 2-2 and 2-3 are primary and secondary communication protocols, respectively.
B. In synchronous operation, RA, RA', RB, RX(A), and RX(B) are not used. TA, TA', TB, TX(A), and TX(B) are
used instead.
C. Items in italics refer only to frequencies and register contents, which are variable. A crystal oscillator driving
20.736 MHz into the TMS320-series DSP provides a master clock frequency of 5.184 MHz. The TLC32046
produces a shift clock frequency of 1.296 MHz. If the TX(A) register contents equal 9, the SCF clock
frequency is 288 kHz,. and the D/A convel'$ion frequency is 288 kHz + T(B).
Figure 2-1. Asynchronous Internal Timing Configuration
7-19
2.2
Analog Input
Two pairs of analog inputs are provided. Normally, the IN+ and IN- input pair is used; however, the auxiliary
input pair, AUX IN+ and AUX IN-, can be used if a second input is required. Since sufficient common-mode
range and rejection are provided, each input set can be operated in differential or single-ended modes. The
gain for the IN+, IN-,AUX IN+,andAUX IN-inputs can be programmed to 1,2,or4 (see Table 4-1). Either
input circuit can be selected via software control. Multiplexing is controlled with the D4 bit (enable/disable
AUX IN+ and AUX IN-) of the secondary DX word (see Table 2-3). The multiplexing requires a 2-ms wait
at SCF = 288 kHz (see Figure 5-3) for a valid output signal. A wide dynamic range is ensured by the
differential internal analog architecture and the separate analog and digital voltage supplies and grounds.
2.3
AID Band-Pass Filter, Clocking, and Conversion Timing
The receive-channel AID high-pass filter can be selected or bypassed via software control (see Functional
Block Diagram). The frequency response of this filter is found in the electrical characteristic section. This
response results when the switched-capacitor filter clock frequency is 288 kHz and the AID sample rate is
16 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter clock. When the
filter clock frequency is not 288 kHz, the low-pass filter transfer function is frequency-scaled by the ratio of
the actual clock frequency to 288 kHz (see Typical Characteristics section); The ripple bandwidth and 3-dB
low-frequency roll-off points of the high-pass section are 300 Hz and 200 Hz, respectively. However, the
high-pass section low-frequency roll-off is frequency-scaled by the ratio of the AID sample rate to 16 kHz.
Figure 2-1 and the DX serial data word format sections of this data manual indicate the many options for
attaining a 288-kHz band-pass switched-capacitor filter clock. These sections indicate that the RX(A)
counter can be programmed to give a 288-kHz band-pass switched-capacitor filter clock for, several master
clock input frequencies.
The AID conversion rate is attained by frequency-dividing the band-pass switched-capacitor filter clock with
the RX(B) counter. Unwanted aliasing is prevented because the AID conversion rate is an integer
submultiple of the band-pass switched-capacitor filter sampling rate, and the two rates are synchronously
locked.
2.4
AID Converter
Fundamental performance specifications for the receive channel ADC circuitry are in the electrical
characteristic section of this data manual. The ADC circuitry, using switched-capacitor techniques, provides
an inherent sample-and-hold function.
2.5
Analog Output
The analog output circuitry is an analog output power amplifier. Both non inverting and inverting amplifier
outputs are brought out of the IC. This amplifier can drive transformer hybrids or low-impedance loads
directly in either a differential or single-ended configuration.
2.6
DIA Low-Pass Filter, Clocking, and Conversion Timing
The frequency response results when the low-pass switched-capacitor filter clock frequency is 288 kHz (see
equation 1). Like the AID filter, the transfer function of this filter is frequency-scaled when the clock frequency
,is not 288 kHz (see Typical Characteristics section). A continuous-time filter is provided on the output of the
. low-pass filter to eliminate the periodic sample data signal information, which occurs at multiples of the
288-kHz switched-capacitor clock feedthrough.'
The D/A conversion rate is attained by frequency-dividing the 288-kHz switched-capacitor filter clock with
the T(B) counter. Unwanted aliasing is prevented because the DIA conversion rate is an integer submultiple
of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.
2.7
01A Converter
Fundamental performance specifications for the transmit channel DAC circuitry are in the electrical
characteristic section. The DAC has a sample-and-hold function that is realized with a switched-capacitor
ladder.
'
7-20
2.8
Serial Port
The serial port has four possible configurations summarized in the function table on page 1-2. These
configurations are briefly described below.
2.9
•
The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS320C17. The communications protocol is two a-bit bytes.
•
The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS32020, TMS320C25, and TMS320C30. The communications protocol is
one 16-bit word.
•
The transmit and receive sections are operated synchronously, and the serial port interfaces
directly with the TMS320C17. The communications protocol is two a-bit bytes.
•
The transmit and receive sections are operated synchronously, and the serial port interfaces
directly with the TMS32020, TMS320C25, TMS320C30, or two SN74299 serial-to-parallel shift
registers, which can interface in parallel to the TMS32010, TMS320C15, to any other digital
signal processor, or to external FIFO circuitry. The communications protocol is one 16-bit word.
Synchronous Operation
When the transmit and receive sections are operated synchronously, the low-pass filter clock drives both
low-pass and band-pass filters (see Functional Block Diagram). The AID conversion timing is derived from
and equal to the D/A conversion timing. When data bit 05 in the control register is a logic 1, transmit and
receive sections are synchronous. The band-pass switched-capacitor filter and the AID converter timing are
derived from the TX(A) counter, the TX(B) counter, and the TA and TA' registers. In synchronous operation,
both the AID and the D/A channels operate from the same frequencies. The FSX and the FSR timing is
identical during primary communication, but FSR is not asserted during secondary communication because
there is no new AID conversion result.
One 16-Blt Word (Dual-Word [Telephone Interface] or Word Mode)
2.9.1
The serial port interfaces directly with the serial ports of the TMS32020, TMS320C25, and the TMS320C30,
and communicates in one 16-bit word. The operation sequence is as follows:
1.
2.
3.
4.
The FSX and FSR pins are brought low by the TLC32046 AIC.
One 16-bit word is transmitted and one 16-bit word is received.
FSX and FSR are brought high.
EODX and EODR emit low-going pulses one shift clock wide. EODX and EODR are valid in the
word or byte mode only.
If the device is in the dual-word (telephone interface) mode, FSD goes low during the secondary
communication period and enables the data word received at the DATA-DR/CONTROL input to be routed
to the DR line. The secondary communication period occurs four shift clocks after completion of primary
communications.
Two 8-Bit Bytes (Byte Mode)
2.9.2
The serial port interfaces directly with the serial port of the TMS320C17 and communicates in two a-bit
bytes. The operation sequence is as follows:
1.
2.
3.
4.
5.
6.
7.
FSX and FSR are brought low.
One 8-bit word is transmitted and one a-bit word is received.
EODX and EODR are brought low.
FSX and FSR emit positive frame-sync pulses that are four shift clock cycles wide.
One 8-bit byte is transmitted and one 8-bit byte is received.
FSX and FSR are brought high.
EO OX and EODR are brought high.
7-21
2.9.3
Synchronous Operating Frequencies
The synchronous operating frequencies are determined by the following equations.
Switched capacitor filter (SCF) frequencies (see Figure 2-1):
Low-pass SCF clock frequency
(D/A and AID channels)
master clock frequency
T(A) x 2
High-pass SCF clock frequency (AID channel) = AID conversion frequency
Conversion frequency (AID and 01A channels)
low-pass SCF clock. frequency
= -...:...----=T:"::(B=-)----'--...:...
master clock frequency
T(A) x 2 x T(B)
NOTE: T(A), T(B), R(A), and R(B) are the contents of the TA, TB, RA, and RB registers, respectively.
2.10 Asynchronous Operation
When the transmit and the receive sections are operated asynchronously, the low-pass and band-pass filter
clocks are independently generated from the master clock. The D/A and the AID conversion timing is also
determined independently.
D/A timing is set by the counters and registers described in synchronous operation, but the RA and RS
registers are substituted for the TA and TB registers to determine the AID channel sample rate and the AID
path switched-capacitor filter frequencies. Asynchronous operation is selected by control register bit OS
being zero.
2.10.1
One 16-BltWord (Word Mode)
The serial port interfaces directly with the serial ports of the TMS32020, TMS320C2S, and TMS320C30 and
communicates with 16-bit word formats. The operation sequence is as follows:
1.·
2.
3.
4.
FSX orFSR are brought low by the TLC32046 AIC.
One 16-bit word is transmitted or one 16-bit word is received.
FSX or FSR are brought high.
EO OX or EODR emit low-going pulses one shift clock wide. EO OX and ~ODR are valid in either
the word or byte mode only.
2.10.2 Two 8-Blt Bytes (Byte Mode)
The serial port interfaces directly with the serial port of the TMS320C17 and communicates in two 8-tlit
bytes. The operating sequence is as follows:
1..
2.
3.
4.
S.
6.
7.
FSX or FSR are brought low by the TLC32046 AIC.
One byte is transmitted or received.
EODX or EODR are brought low.
FSX or FSR are brought high for four shift clock periods and then brought low.
The second byte is transmitted or received.
FSX or FSR are brought high.
EO OX or EODR are brought high.
2.10.3 Asynchronous Operating Frequencies
The asynchronous operating frequencies are determined by the following equations.
Switched-capacitor filter frequencies (see Figure 2-1 ):
Low-pass DIA SCF clock frequency =
7-22
master clock frequency
T(A) x 2
Low-pass AID SCF clock frequency =
master clock frequency
R(A) x 2
(2)
High-pass SCF clock frequency (AID channel) = AID conversion frequency
Conversion frequency:
01A
conversion frequency
low-pass
01A
SCF clock frequency
T(B)
. f
low-pass AID SCF clock frequency (for low pass receive filter)
AID conversion
requency =
R(B)
(3)
NOTE: T(A), T(B), R(A), and R(B) are the contents of the TA, TB, RA, and RB registers, respectively.
2.11 Operation of TLC32046 With Internal Voltage Reference
The internal reference of the TLC32046 eliminates the need for an external voltage reference and provides
overall circuit cost reduction. The internal reference eases the design task and provides complete control
of the IC performance. The internal reference is brought out to REF. To keep the amount of noise on the
reference signal to a minimum, an external capacitor can be connected between REF and ANLG GNO.
2.12 Operation of TLC32046 With External Voltage Reference
REF can be driven from an external reference circuit. This external circuit must be capable of supplying
250 I!A and must be protected adequately from noise and crosstalk from the analog input.
2.13 Reset
A reset function is provided to initiate serial communications between the AIC and OSP and to allow fast,
cost-effective testing during manufacturing. The reset function initializes all AIC registers, including the
control register. After a negative-going pulse on RESET, the AIC is initialized. This initialization allows
normal serial port communications activity to occur between AIC and OSP (see AIC OX Data Word Format
section). After RESET, TA=TB=RA=RB=18 (or 12 hexadecimal), TA'=RA'=01 (hexadecimal), the AID
high-pass filter is inserted, the loop-back function is deleted, AUX IN+ and AUX IN- are disabled, transmit
and receive sections are in synchronous operation, programmable gain is set to 1, the on-board (sin x)/x
correction filter is not selected, 0100UT is set to 0, and 0110UT is set to O.
2.14 Loopback
This feature allows the circuit to be tested remotely. In loopback, OUT+ and OUT-are internally connected
tolN+ and IN-. The DAC bits (015 to 02), which are transmitted to OX, can be compared with the AOC bits
(015 to 02), received from DR. The bits on DR equal the bits on OX. However, there is some difference in
these bits due to the AOC and OAC output offsets.
The loopback feature is implemented with digital signal processor control by transmitting a logic 1 for data
bit 03 in the OX secondary communication to the control register (see Table 2-3).
7-23
2.15 Communications Word Sequence
In the dual-word (telephone interface) mode, there are two data words that are presented to the DSP or ~P
from the DR terminal. The first data word is the ADC conversion result occurring during the FSR time, and
the second is the serial data applied to DATA-DR during the FSD time. FSR is not asserted during secondary
communications and FSD is not asserted during primary communications.
Primary
Communications
1
4 Shift
Clocks
14
,
Secondary
Communications
1
.1
DX-14 Bits Digital 11
From DSP to DAC
TLC32046
DX-14 Bits Digital XX
From DSP
Input for D/A
Conversion
Input for Register
Program
TLC32046
1
I
1
I
TLC32046
Dual-Word
(telephone Interface)
Mode Only
2s Complement Output
From ADC to the DSP
TLC32046
Dual-WOrd
(telephone Interface)
Mode Only
16 bits Digital From
.
1 DATA-DR to DR
Data From DATA-DR
to the DSP
28 Complement Output
From ADC to the DSP
DR
1
14----
1
I
16 bits -~~
..
1
1
14----
16 bits ---.-t~
1
1
TLC32046
Dual-Word
(telephone Interface)
Mode Only
1
Figure 2-2. Primary and Secondary Communications Word Sequence
2.15.1
DR Word Bit Pattern
The data word is the 14-bit conversion result of the receive channel to the processor in 28 complement
format. With 16-bit processors, the data is 16 bits long with the two LSB8 at zero.
AID MSB
AID LSB
1st bit sent
J.
015 1,014
7-24
J.
I 013 I 012 I 011 I 010 I
09
I
08
I
07
I
06
I
05
I
04
I
03
I
02
I D1 I DO
2.15.2 Primary OX Word Bit Pattern
Using 8-bit processors, the data word is transmitted in the same order as one 16-bit word, but as two bytes
with the two LSBs of the second byte set to zero.
AlO OR O/A MSB
1st bit sent
J.
015
AlO or 01A LSB
1st bit sent of 2nd byte
J.
J.
I 014 I 013 I 012 I 011 I 010 I
09
I
08
I
07
I
06
I
05
I
04
I
03
I
02
I
01
I
00
Table 2-2. Primary OX Serial Communication Protocol
FUNCTIONS
D1
DO
015 (MSB)-02 ~ OAC Register.
TA ~ TX(A), RA ~ RX(A) (see Figure 2-1).
TB ~ TX(B), RB ~ RX(B) (see Figure 2-1).
0
0
015 (MSB)-02 ~ OAC Register.
TA+TA' ~ TX(A), RA+RA' ~ RX(A) (see Figure 2-1).
TB ~ TX(B), RB ~ RX(B) (see Figure 2-1).
The next O/A and AlO conversion period is changed by the addition of TA' and RA' master clock cycles,
in which TA' and RA' can be positive, negative, or zero (refer to Table 2-4).
0
1
015 (MSB)-02 ~ OAC Register.
TA-TA' ~ TX(A), RA-RA' ~ RX(A) (see Figure 2-1).
TB ~ TX(B), RB ~ RX(B) (see Figure 2-1).
The next 01A and AlO conversion period is changed by the subtraction ofTA' and RA' master clock cycles,
in which TA' and RA' can be positive, negative, or zero (refer to Table 2-4).
1
0
015 (MSB)-02 ~ OAC Register.
TA ~ TX(A), RA ~ RX(A) (see Figure 2-1).
TB ~ TX(B), RB ~ RX(B) (see Figure 2-1).
After a delay of four shift cycles, a secondary transmission follows to program the AIC to operate in the
desired configuration. In the telephone interface mode, data on OATA OR is routed to OR during
secondary transmission.
1
1
NOTE: Setting the two least significant bits to 1 in the normal transmission of OAC information (primary communications)
to the AIC initiates secondary communications upon completion of the primary communications. When the
primary communication is complete, FSX remains high for four SHIFT CLOCK cycles and then goes low and
initiates the secondary communication. The timing speCifications for the primary and secondary communications
are identical. In this manner, the secondary communication, if initiated, is interleaved between successive
primary communications. This interleaving prevents the secondary communication from interfering with the
primary communications and OAC timing. This prevents the AIC from skipping a OAC output. FSR is not asserted
during secondary communications activity. However, in the dual-word (telephone interface) mode, FSO is
asserted during secondary communications but not during primary communications.
7-25
2.15.3 Secondary OX Word Bit Pattern
O/A MSB
1st bit sent
1st bit sent of 2nd byte
,J.
015
O/A LSB
,J.
,J.
I 014 I 013 I 012 I 011 I 010 I
09
I
08
I
07
I
06
I
05
I
04
I
03
I
02
I
01
I DO
Table 2-3. Secondary OX Serial Communication Protocol
D1
DO
013 (MSB)-09 -+ TA, 5 bits unsigned binary (see Figure 2-1).
06 (MSB)-02 -+ RA, 5 bits unsigned binary (see Figure 2-1).
015,014,08, and 07 are unassigned.
FUNCTIONS
0
0
014 (sign bit)-09 -+ TN, 6 bits 2s complement (see Figure 2-1).
07 (sign bit)-02 -+ RN, 6 bits 2s complement (see Figure 2-1).
015 and 08 are unassigned.
0
1
014 (MSB)-09 -+ TB, 6 bits unsigned binary (see Figure 2-1).
07 (MSB)-02 -+ RB, 6 bits unsigned binary (see Figure 2-1 ).
015 and 08 are unassigned.
1
0
02 .. 0/1 deleteslinserts the AID high-pass filter.
03 ... 0/1 deletes/inserts the loopback function.
04 ... 011 disables/enables AUX IN+ and AUX IN-.
05 .. 0/1 asynchronous/synchronous transmit and receive sections.
06 ... 0/1 gain control bits (see Table 4-1).
07 ... 0/1 gain control bits (see Table 4-1).
09 .. 0/1 deletelinsert on-board second-order (sinx)/x correction filter
010 = 0/1 output to 01 OOUT (dual-word (telephone interface) mode)
011 = 0/1 output to 011 OUT (dual-word (telephone interface) mode)
08,012-015 are unassigned.
1
1
2.16 Reset Function
A reset function is provided to initiate serial communications between the AIC and OSP. The reset function
initializes all AIC registers, including the control register. After power has been applif;ld to the AIC, a
negative-going pulse on RESET initializes the AIC registers to provide a 16-kHz AID and O/A conversion
rate for a 10.368-MHz master clock input signal. Also, the pass-bands of the AID and O/A filters are 300
Hz to 7200 Hz and a Hz to 7200 Hz, respectively; therefore, the filter bandwidths are half those shown in
the filter transfer function specification section. The AIC, except the CONTROL register, is initialized as
follows (see AIC OX Data Word Format section):
REGISTER
INITIALIZED VALUE (HEX)
TA
12
TA'
01
TB
12
RA
12
RA'
01
RB
12
The CONTROL register bits are reset as follows (see Table 2-3):
011 = 0,010 = 0,09 = 1, 07 = 1, 06 = 1, 05 = 1, 04 = 0, 03 = 0,02 = 1
This initialization allows normal serial port communications to occur between the AIC and the OSP. If the
transmit and receive sections are configured to operate synchronously and the user wishes to program
different conversion rates, only the TA, TA', and TB register need to be programmed. Both transmit and
receive timing are synchronously derived from these registers (see the Terminal Functions and OX Serial
Data Word Format sections).
Figure 2-3 shows a circuit that provides a reset on power-up when power is applied in the sequence given
in the power-up sequence section. The circuit depends on the power supplies reaching their recommended
values a minimum of 800 ns before the capacitor charges to 0.8 V above OGTL GNO.
7-26
TLC32046
VCC+
O.5I1F
VCC-
-5V
Figure 2-3. Reset on Power-Up Circuit
2.17 Power-Up Sequence
To ensure proper operation of the Ale and as a safeguard against latch-up, it is recommended that Schottky
diodes with forward voltages less than or equal to 0.4 V be connected from Vcc- to ANLG GND and from
Vcc- to DGTL GND.ln the absence of such diodes, power is applied in the following sequence: ANLG GND
and DGTL GND, Vcc-, then Vcc+ and Vee. Also, no input signal is applied until after power-up.
2.18 AIC Register Constraints
The following constraints are placed on the contents of the Ale registers:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
TA register must be ~ 4 in word mode (WORD/BYTE= high).
TA register must be ~ 5 in byte mode (WORDIBYTE= low).
TA' register can be either positive, negative, or zero.
RA register must be ~ 4 in word mode (WORD/BYTE = high).
RA register must be ~ 5 in byte mode (WORD/BYTE = low).
RA' register can be either positive, negative, or zero.
(TA register ± TA' register) must be > 1.
(RA register ± RA' register) must be > 1.
TB register must be ~ 15.
RB register must be ~ 15.
2.19 AIC Responses to Improper Conditions
The Ale has provisions for responding to improper conditions. These improper conditions and the response
of the Ale to these conditions are presented in Table 2-4.
7-27
Table 2-4. AIC Responses to Improper Conditions
IMPROPER CONDITION
AIC RESPONSE
TA register + TA' register .. 0 or 1
TA register - TA' register .. 0 or 1
Reprogram TX(A) counter with TA register value
TA register + TA' register < 0
MODULO 64 arithmetio is used to ensure that a positive value is loaded into
TX(A) counter, i.e., TA register + TA' register + 40 HEX is loaded into TX(A)
counter.
RA register + RA' register .. 0 or 1
RA register - RA' register - 0 or 1
Reprogram RX(A) counter with RA register value
RA register + RA' register = 0 or 1
MODULO 64 arithmetic is used to ensure that,s positive value is loaded into
RX(A) counter, i.e., RA register + RA' register + 40 HEX is loaded into RX(A)
counter.
TA register = 0 or 1
RA register .. 0 or 1
AIC is shut down. Reprogram TA or RA registers after a reset.
TA register < 4 in word mode
TA register < 5 in byte mode
RA register < 4 in word mode
RA register < 5 in byte mode
The AIC serial port no longer operates. Reprogram TA or RA registers after
a reset.
TB register < 15
Reprogram TB register with 12'HEX
RB register < 15
Reprogram RS register with 12 HEX
AIC and DSP cannot communicate
Hold last DAC output
2.20 Operation With Conversion Times Too Close Together
If the difference between two successive D/A conversion frame syncs is less than 1/25 kHz, the AIC
operates improperly. In this situation, the second D/A conversion frame sync occurs too quickly, and there
is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B
registers are improperly programmed or if the A + A' register result is too small. When incrementally
adjusting the conversion period via the A + A' register options, the designer should not violate this
requirement (see Figure2-4).
t1
Frame Sync- ,
(FSX or FSR)
1
...__....
t2
'I')
j.-- Ongoing Conversion
I...__....r1
-+l
t2 - t1 :s; 1/25 kHz
Figure 2-4. Conversion Times Too Close Together
2.21 More Than One Receive Frame Sync Occurring Between Two Transmit
Frame Syncs - Asynchronous Operation
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the AIC
during an FSX frame sync. The ongoing conversion period is then adjusted; however, either receive
conversion period A or conversion period B can be adjusted. For both transmit and receive conversion
periods, the incremental conversion period adjustment is performed near the end of the conversion period.
If there is sufficient time between t1 and t2, the receive conversion period adjustment is performed during
receive conversion period A. Otherwise, the adjustment is performed during receive conversion period B.
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see Figure 2-5).
7-28
u
U
14-14---- Transmit Conversion Period ---~~I
I~
~ I
Receive Conversion
Period A
Receive Conversion
Period B
Figure 2-5. More Than One Receive Frame Sync Between Two Transmit Frame Syncs
2.22 More Than One Transmit Frame Sync Occurring Between Two Receive
Frame Syncs - Asynchronous Operation
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol must be followed. For both transmit and receive conversion periods, the incremental conversion
period adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the AIC during an FSX frame sync. The ongoing transmit
conversion period is then adjusted. However, three possibilities exist for the receive conversion period
adjustment as shown in Figure 2-6. When the adjustment command is issued during transmit conversion
period A, receive conversion period A is adjusted if there is sufficient time between t1 and t2' If there is not
sufficient time between t1 and t2' receive conversion period B is adjusted. The third option is that the receive
portion of an adjustment command can be ignored if the adjustment command is sent during a receive
conversion period, which is adjusted due to a prior adjustment command. For example, if adjustment
commands are issued during transmit conversion periods A, B, and C, the first two commands may cause
receive conversion periods A and B to be adjusted, while the third receive adjustment command is ignored.
The third adjustment command is ignored since it was issued during receive conversion period B, which
already is adjusted via the transmit conversion period B adjustment command.
t1
1!4- Conversion
Transmit
1 Transmit 1 Transmit 1
-¥- Conversion ....... converslon-+I
I
FSRU
Period A
j.---- Receive Conversion Period A
I
Period B
I
Period C
L.J
U
_14
Receive Conversion Period B
-1
Figure 2-6. More Than One Transmit Frame Sync Between Two Receive Frame Syncs
2.23 More than One Set of Primary and Secondary DX Serial Communications
Occurring Between Two Receive Frame Syncs (See DX Serial Data Word
Format section) - Asynchronous Operation
The TA, TA', TB, and control register information that is transmitted in the secondary communication is
accepted and applied during the ongoing transmit conversion period. If there is sufficient time between t1
and t2, the TA, RA', and RB register information, sent during transmit conversion period A, is applied to
receive conversion period A; otherwise, this information is applied during receive conversion period B. If RA,
RA', and RB register information has been received and is being applied during an ongoing conversion
period, any subsequent RA, RA', or RB information received during this receive conversion period is
disregarded (see Figure 2-7),
7-29
Primary
SecQndaryt 1
Fsxln
I
1'1
Primary
I
II
Transmit
Conversion
Preload A
~
Secondary
n
I
Transmit
Conversion
Preload B
Primary
I'I
~~
t2
I
FSR
+--
Receive
Conversion
Period A
I
~
Receive
Conversion
Period B
Secondary
I
n
Transmit
Conversion
Preload C
L
I
-t
I I
I
~I
Figure 2-7~ More Than One Set of Primary and Secondary DX
Serial Communications Between Two Receive Frame Syncs
2.24 System Frequency Response Correction
The (sin x)/x correction for the DAC zero-order sample-and-hold output can be provided by an on-board
second-order (sin x)/x correction filter (see Functional Block Diagram). This (sin x)/x correction filter can be
.inserted into or omitted from the signal path by digital-slgnal-processor control (data bit 09 In the OX
secondary communications). When inserted, the (sin x)/x correction filter precedes the switched-capacitor
low-pass filter. When the TB register (see Figure 2-1) equals 15, the correction results of Figures 5-5, 5-6,
and 5-7 can be obtained.
The (sin x)/x correction [see section (sin x)/x] can also be accomplished by disabling the on-board
second-order correction filter and performing the (sin x)/x correction in digital signal processor software. The
system frequency response can be corrected via DSP software to ± 0.1 dB accuracy to a band edge of
3000 Hz for all sampling rates. This correction is accomplished with a first-order digital correction filter, that
requires seven TMS320 Instruction cycles. With a 200-ns instruction cycle, seven instructions represent an
overhead factor of 1.1 % and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (Sin x)/x
Correction Section for more details).
2.25 (Sin x)/x Correction
If the designer does not wish to use the on-board second-order (sin x)/x correction filter, correction can be
accomplished in digital signal processor (DSP) software. (Sin x)/x correction can be accomplished easily
and efficiently in digital signal processor software. Excellent correction accuracy can be achieved to a band
edge of 3000 Hz by using a first-order digital correction filter. The results shown are typical of the numerical
correction accuracy that can be achieved for sample rates of interest. The filter requires seven instruction
cycles per sample on the TMS320 OS. With a 200-ns instruction cycle, nine instructions per sample
represents an overhead factor of 1.4% and 1.7% for sampling rates of 8000 Hz and 9600 Hz, respectively.
This correction adds a slight amount of group delay at the upper edge of the 300-:Hz to 3000-Hz band.
2.26 (Sin x)/x Roll-Off for a Zero-Order Hold Function
The (sin x)/x roll-off error for the AIC DAC zero-order holcj function at a band-edge frequency of 3000 Hz
for the various sampling rates is shown in Table 2-5 (see Figure 5-7).
7,-30
Table 2-5. (sin x)/x Roll-Off Error
fs (Hz)
sin 1t f1f.
Error = 20 log 1t flfs
1=3000 Hz
(dB)
7200
-2.64
8000
-2.11
9600
-1.44
14400
-0.63
16000
-0.50
19200
-0.35
25000
-0.21
The actual AIC (sin x)/x roll-off is slightly less than the figures in Table 2-5 because the AIC has less than
100% duty cycle hold interval.
2.27 Correction Filter
To externally compensate for the (sin x)/x roll-off of the AIC, a first-order correction filter can be implemented
as shown in Figure 2-8.
Y(I + 1)
p1
Figure 2-8. First-Order Correction Filter
The difference equation for this correction filter is: ,
Y(i+1)=p2.(1-p1).U(i+1)+p1·Y(i)
(4)
where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
1H
12 _
(f)
(p2)2
V (1-p1)2
- 1-2 V p1 V cos (2P f/fs) + (p1 )2
(5)
2.28 Correction Results
Table 2-6 shows the optimum p values and the corresponding correction results for 8000-Hz and 960C-Hz
sampling rates (see Figures 5-8,5-9, and 5-10).
7-31
Table 2-6. (Sin x)/x Correction Table for fs
f (Hz)
ROLL·OFF ERROR (dB)
fs= 8000Hz
pi = -0.14813
p2= 0.9888
300
-0.099
600
-0.089
-0.054
900
1200
1500
1800
-0.002
0.041
0.079
2100
2400
2700
0.100
0.091
-0.043
3000
-0.102
=8000 Hz and fs =9600 Hz
ROLL·OFF ERROR (dB)
f s = 9600Hz
pi =-0.1~07
p2= 0.9951
-0.043
-0.043
0
0
0
0.043
0.043
0.043
0
-0.043
2.29 TMS320 Software Requirements
The digital correction filter equation can be written in state variable form as follows:
Y(i+1) = Y(i) . k1 + u(i+1) . k2
Where
k1 = p1
k2 = (1 - p1) p2
y(i) = filter state
u(i+ 1) = next I/O sample
The coefficients k1 and k2 must be represented as 16·bit integers. The SACH instruction (with the proper
shift) yields the correct result. With the assumption that the TMS320 processor page pointer and memory
configuration are properly initialized, the equation can be executed in seven instructions or seven cycles
with the following program:
ZAC
LT K2
MPY U
LTA Kl
MPY Y
APAC
SACH (dma) , (shift)
7-32
3
3.1
Specifications
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)
Supply voltage range, VCC+ (see Note 1) .......................... -0.3 V to 15 V
Supply voltage range, Voo ....................................... -0.3 V to 15 V
Output voltage range, Va ........................................ -0.3 V to 15 V
Input voltage range, VI ........................................... -0.3 V to 15 V
Digital ground voltage range ...................................... -0.3 V to 15 V
Operating free-air temperature range: TLC32046C ................... O°C to 70°C
TLC320461 .................. -40°C to 85°C
TLC32046M ................ -55°C to 125°C
Storage temperature range: TLC32046C, TLC320461 ............. -40°C to 125°C
TLC32046M ........................ -65°C to 150°C
Case temperature for 10 seconds: FN or FK package ....................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds:
N or J package .................................................... 260°C
NOTE 1: Voltage values for maximum ratings are with respect to VCC-.
3.2
Recommended Operating Conditions
Supply voltage, VCC+ (see Note 2)
MIN
4.75
Supply voltage, VCC- (see Note 2)
-4.75
Digital supply voltage, VDD (see Note 2)
Digital ground voltage with respect to ANLG GND, DGTL GND
Reference input voltage,.VrefCext) (see Note 2)
High-level input voltage, VIH
Low-level input voltage, VIL (see Note 3)
4.75
2
2
-0.3
NOM
5
-5
MAX
5.25
-5.25
5
0
5.25
4
VDD+0.3
0.8
UNIT
V
V
V
V
V
V
V
a
Load resistance at OUT+ and/or OUT-, RL
300
Load capacitance at OUT+ and/or OUT-, CL
100
pF
MSTR CLK frequency (see Note 4)
5 10.368
MHz
Analog input amplifier common mode input voltage (see Note 5)
±1.5
V
NO or D/A conversion rate
25
kHz
TLC32046C
0
70
-40
TLC320461
85
Operating free-air temperature range, TA
°C
-55
TLC32046M
125
NOTES: 2. Voltages at analog Inputs and outputs, REF, VCC+, and VCC- are With respect to ANLG GND. Voltages at
digital inputs and outputs and VDD are with respect to DGTL GND.
3. The algebraic convention, in which the least positive (most negative) value is deSignated minimum, is used
in this data manual for logic voltage levels only.
4.. The band-pass switched-capacitor filter (SCF) specifications apply only when the low-pass section SCF
clock is 288 kHz and the high-pass section SCF clock is 16 kHz. If the low-pass SCF clock is shifted from
288 kHz, the lOW-pass roll-off frequency shifts by the ratio of the low-pass SCF clock to 288 kHz. If the
high-pass SCF clock is shifted. from 16 kHz, the high-pass roll-off frequency shifts by the ratio of the
high-pass SCF clock to 16 kHz. Similarly, the low-pass switched-capacitor filter (SCF) specifications apply
only when the SCF clock is 288 kHz. If the SCF clock is shifted from 288 kHz, the low-pass roll-off frequency
shifts by the ratio of the SCF clock to 288 kHz.
5. This range applies when (IN+ -IN-) or (AUX IN+ - AUX IN-) equals ± 6 V.
7-33
3.3
3.3.1
Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, Vcc+ 5 V, Vcc- -5 V, VDD 5 V (Unless
Otherwise Noted)
=
=
Total Device, MSTR ClK Frequency
PARAMETER
=
=5.184 MHz, Outputs Not loaded
TEST CONDITIONS
VOH
High-level output voltage
VOO = 4.75 V,
IOH .. -300 I1A
VOL
Low-level output voltage
VOO .4.75 V,
IOL=2mA
MIN
TYPt
ICC-
Supply current from
VCC+
Supply current from
VCC-
0.4
V
TLC320461
35
40
rnA
TLC32046M
45
TLC32046C
-35
TLC320461
TLC32046M
100
Supply current from VOO
Vref
Internal reference
output voltage
10000 Hz
UNIT
dB
t All typical values are at TA .. 25°C.
:j: The MIN, TYP, and MAX specifications are given for a 288-kHz SCF clock frequency. A slight error in the 288-kHz SCF
may result from inaccuracies in the MSTR CLK frequency, resulting from crystal frequency tolerances. Jf this frequency
error is less than 0.25%, the ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications,
where K1 .. 100 • [(SCF frequency - 288 kHz)/288kHzj. For errors greater than 0.25%, see Note 9.
NOTE 9: The filter gain outside of the pass band is measured with respect to the gain at 1 kHz (2 kHz for M version).
The filter gain within the pass band is measured with respect to the average gain within the pass band. The
pass bands are 300 Hz to 7200 Hz and 0 to 7200 Hz for the band-pass and low-pass filters, respectively. For
switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted by the ratio of
switched-capacitor filter clock frequency to 288 kHz.
7-37
3.4
Operating Characteristics Over Recommended Operating Free-Air
Temperature Range, VCC+ = 5 V, VCC- = -5 V, Vee = 5 V
3.4.1
Receive and Transmit Noise (measurement Includes low-pass and band-pass
switched-capacitor filters)
Transmit
noise
PARAMETER
Broadband with (sin xlIx
Broadband without (sin xlIx
oto 30 kHz with (sin xlIx
oto 30 kHz without (sin xlIx
oto 3.4 kHz with (sin xlIx
oto 3.4 kHz without (sin xlIx
oto 6.8 kHz with (sin xlIx
(wide-band operation with 7.2 kHz
rOil-Off)
oto 6.8 kHz without (sin xlIx
(wide-band operation with 7.2 kHz
roll-off)
Receive noise (see Note 10)
MIN
TEST CONDITIONS
OX input - 00000000000000,
Constant input code
Inputs grounded,
Gain: 1 .
TYPT
250
200
200
200
180
160
MAX
500
450
400
400
300
300
180
350
160
350
300
18
500
ILVrms
dBrncO
MAX
UNIT
UNIT
ILVrms
t All typical values are at TA • 25°C.
NOTE 10: The noise is computed by statistically evaluating the digital output of the AID converter.
3.5
Timing Requirements
3.5.1
Serial Port Recommended Input Signals, TLC32046C and TLC320461
PARAMETER
tc(MCLK)
Master clock cycle time
tr(MCLK)
Master clock rise time
tf(MCLK)
MIN
95
Master clock fall time
Master clock duty cycle
25%
RESET pulse duration (see Note 11 1
tsu(DX)
ns
OX setup time before SCLKJ..
10
ns
10
ns
75%
800
ns
20
ns
OX hold time after SCLKJ..
ns
th(DX)
tc(SCLK)/4
NOTE 11: RESET pulse duration is the amount of time that the RESET is held below 0.8 V after the power supplies have
reached their recommended values.
3.5.2
Serial Port Recommended Input Signals, TLC32046M
PARAMETER
MIN
TYpt
MAX
UNIT
tc(MCLK)
Master clock cycle time
tr(MCLK)
Master clock rise time
10
ns
tf(MCLK)
Master clock fall time
10
ns
95
Master clock duty cycle
RESET pulse duration ($ee Note 11)
tsuCDX)
OX setup time before SCLKJ..
ns
50%
SOO
ns
28
ns
OX hold time after SCLKJ..
ns
th(DXl
tc(SCLK)/4
NOTE 11: RESET pulse duration is the amount of time thatthe RESET is held below 0.8 V after the power supplies have
reached their recommended values.
7-38
3.5.3
=
Serial Port - AIC Output Signals, CL 30 pF for SHIFT ClK Output, CL
For All Other Outputs, TlC32046C and TlC320461
PARAMETER
MIN
TYpt
=15 pF
MAX
UNIT
tcCSClK)
Shift clock (SCll<) cycle time
tfCSClK)
Shift clock (SClK) fall time
3
8
ns
trCSClK)
Shift clock (SClK) rise time
3
8
ns
Shift clock (SCll<) duty cycle
ns
380
45%
55%
idlCH-Flt
Delay from SClKi to FSRlFSXlFSDJ.
30
idlCH-FHl
Delay from sClKi to FSR/FSXlFSDi
35
ns
90
ns
id(CH-DR)
DR valid after SClKi
90
ns
id(CH-El)
Delay from sClKi to EODXlEODRJ. in word mode
90
ns
idCCH-EH)
Delay from SClKi to EODXlEODRi in word mode
90
ns
tfCEODX)
EODX fall time
2
8
ns
tfCEODR)
EODR fall time
2
8
ns
id(CH-El)
Delay from SClKi to EODXlEODRJ. in byte mode
90
ns
id(CH-EH)
Delay from SClKi to EODXlEODRi in byte mode
90
ns
id(MH-Sl)
Delay from MSTR clKi to SClKJ.
65
170
ns
id(MH-SH)
Delay from MSTR ClKi to SClKi
65
170
ns
t Typical values are at TA = 25°C.
3.5.4
Serial Port - AIC Output Signals, CL = 30 pF for SHIFT ClK Output, CL = 15 pF
For All Other Outputs, TlC32046M
PARAMETER
tcCSClK)
Shift clock (SClK) cycle time
tf(SClK)
Shift clock (SClK) fall time
tr(SClK)
MIN
TYPt
400
UNIT
ns
ns
3
Shift clock (SClK) rise time
Shift clock (SCll<) duty cycle
MAX
ns
3
55%
45%
id(CH-Fl)
Delay from SClKi to FSRlFSXlFSDJ.
30
250
ns
id(CH-FH)
Delay from sClKi to FSRlFSXlFSDi
35
250
ns
id(CH-DR)
DR valid after SClKi
250
ns
id(CH-El)
Delay from SClKi to EODXlEODRJ. in word mode
250
ns
id(CH-EH)
Delay from SClKi to EODXlEODRi in word mode
250
ns
tf(EODX)
EODX fall time
-
2
ns
tf(EODR)
EODR fall time
id(CH-EU
Delay from SClKi to EODXlEODRJ. in byte mode
250
ns
id(CH-EH)
Delay from SClKi to EODXlEODRi in byte mode
250
ns
id(MH-Sl)
ns
2
Delay from MSTR ClKi to SClKJ.
65
170
ns
Delay from MSTR clKi to sClKi
65
170
ns
idCMH-SH)
t Typical values are at TA = 25°C.
7-39
7-40
4 Parameter Measurement Information
Rfb
IN+
or
AUXIN+
R
INor
AUX IN-
R
I--_-}
To Mu""""
Rfb
Rfb
=R for D6 =1 and D7 =1
06 = 0 and 07 = 0
Rfb = 2R for 06 = 1 and D7 = 0
Rfb= 4RforD6= 0, and 07= 1
Figure 4-1. IN + and IN - Gain Control Circuitry
Table 4-1. Gain Control Table {Analog Input Signal Required for
Full-Scale Bipolar AID Conversion Twos Complement)t
INPUT
CONFIGURATIONS
Differential configuration
Analog input = IN+ -IN= AUX IN+-AUX IN-
Single-ended configuration
Analog input = IN + - ANLG GND
= AUX IN + -ANLG GND
CONTROL REGISTER BITS
ANALOG
INPUrt§
AID CONVERSION
RESULT
D6
D7
1
0
1
0
VID =±6 V
±full scale
1
0
VID =±3 V
±full scale
0
1
VID-±1.5V
±full scale
1
0
1
0
V, =±3V
±halfscale
1
0
V, =±3V
±full scale
0
1
V,=±1.5V
±full scale
t VCC+ = 5 V, VCC- = -5 V, VDD = 5 V
:j: V,D = Differential Input Voltage, V, = Input voltage referenced to ground with IN- or AUX IN- connected to GND.
§ In this example, Vref is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input not
exceed 0.1 dB below full scale.
7-41
~tc(SClK)
SHIFT
ClK
2Y
___-'I.,:
FSX, FSR,FSD
r-
8Y
1
let (CH-Fl)
let (CH-FH)
1 I
8Y\
~
-+I
DR--""D-1"5-- ,D14
'D13
D1
JL
D1
DO
tsU(DX) ~
1
-.r1/2Y
I!::~~t----
'let(CH_DRH
D12
2Y
1
I,
1
1
1
I I
DO
-~-~:]~~]i~CE~K:~)(~~CJ~)c~~:J!C)-~Di~~'t~ca:N!--
~
1
DATA-DR
~~_D1__.D.0-rI_~~_ ___
i
D15
Figure 4-2. Dual-Word (Telephone Interface) Mode Timing
SHIFT
ClK
.____-'1.,:
FSX, FSRt
DR
2
r
r-
8Y
let (CH-Fl)
8Y\
--""D~1"5--
1 I',
1 I
let (CH-FH)
-.r
rl!::~I""'---
1/2Y
'A
-+I
let (CH-DR
~
D14
D13
D12
D 1 J?2 ~_D1__
, .D.o-+,I_--I~_ ___
1
I
I
DX---~~LX~~~~D(~~(J~)(~L)[J~X:J!c>_~D~~~n~'t~ca=N~-.
I
tau (DX)~
r
-
r-
~
let (CH-El) -+I It- -.I
let (CH-EH)
EOD~EODR*--------------~M-------~8~y~2Y
Figure 4-3. Word Timing
t The time between falling edges of FSR is the NO conversion period and the time between falling edges of FSX is the
O/A conversion period.
::j: In the word format, EOOX and EOOR go low to signal the end of a 16-bit data word to the processor. The worcl-cycle
is 20 shift-clocks wide, giving a four-clock period setup time between data words.
7-42
-+I
SHIFT
ClK
2 V,
lei (CH-Fl~
F:S~
r
I
8V'
I
I
r-
tr (SCll<)
I
~
I
I
d
tsu (OX)
015
lei (CH-FH)
f2V
K
.~~H~.
I
OR--"'0-15---~
OX
t
V
08
2 V,
I
~ 14- lei (CH-Fl)
8~
I
td (CH-FH) -, t~~_
K
(2V
I
~_01_ _0_0..1_ _ __
-1 I-
I
08
Don't Care
EOOR, --------------------~i~I~------~~,
8V'"
EOOX
K
,
Figure 4-4. Byte-Mode Timing
tThe time between falling edges of FSR is the NO conversion period, and the time between fallling edges of FSX is the O/A conversion period.
low, the second byte is
transmitted or received. Each byte-cycle is 12 shift-clocks long, allowing for a four-shift-clock setup time between byte transmissions.
:t: In the byte mode, when EOOX or EOOR is high, the first byte is transmitted or received, and when these signals are
r
(,)
MSTRClK
SHIFTClK
I
I
~
1
~- tel (MH-SH)
--+I
14- tel (MH-Sl)
'X.~.. .____
---/
Figure 4-5. Shift-Clock Timing
4.1
TMS3201 OITMS320C15 - 'TLC32046 Interface Circuit
ClKOUT
---1
L
I
I
......---il...·
DEN
r - I- - - - - - -
I
SO,G1
r-I- - - - - - - - - - - - - -
.....---;1--'
DO-D15
-------«
)>-----------
Valid
IN INSTRUCTION TIMING
CLKOUT
---1
I
L
_____________
II
WE
SN74lS138 Y1
~
~--~I~-I----~--------I
SN74lS299 ClK'
DO-D15
-------«
Valid
»)----------
OUT INSTRUCTION TIMING
Figure 4-6. TMS320101TMS320C15-TLC32046 Interface Timing
7-44
SN74lS74
Q
...
SN74lS299
C2<
~
S1
G2
SO
G1
~
OEN
'--
AO/PAO
A1/PA1
A2IPA2
G1
A
B
Y1
YO
~
08-015
"-
\,
C
SN74lS138
A-H
...
---
OX
-
~
-
SR
----
S1
G.2
""-
TlC32048
QH
SO
ClK:
,.r-
SN74lS7~
G1
C1<
A
()
WE
elK
OUT
~
\,
SHIFT
ClK
I .•
00-015
00-015
FSX
SN74lS299
pD
TMS32010
QH
ClK<
20
\
A-H
SR
Q
10
-.-
DR
00-07'
-
'1
-
J
f"'
MSTR
ClK
EOOX
INT
Figure 4-7. TMS32010ITMS320C15 - TLC32046 Interface Circuit
7-45
7-46
5 Typical Characteristics
D/A AND AID LOW-PASS FILTER
RESPONSE SIMULATION
0.4
I
I
I
I
I
TA =25°C
Input =± 3 V SIne Wave
0.2
ID
'0
I
CD
'0
j
I
'0
c
III
./
"
o
2
-0.2
ID
I
l.
- 1\
~ ~
1\
0
c
V
-0.4
-0.6
3
4
5
6
7
Normalized Frequency
8
10
9
Figure 5-1
o
-10
D/A AND AID LOW-PASS FILTER RESPONSE
See FIgure 2-1
for Pass Band
Detail
~
T~=250C
I
I
I
f- Input = ± 3 V SIne Wave
-20
ID
-30
'0
I
CD
'0
-40
c
-50
j
If
:&
-60
r\
-70
-so
-90
o
2
4
u
I"
~I
6
8 10 12 14
Normalized Frequency
16
18
20
Figure 5-2
NOTE: Absolute Frequency (kHz)
Normalized Frequency x SCF fclock (kHz)
288
For Low-Pass SCF fclock > 288 kHz, please call the factory.
7-47
DIA AND AID LOW-PASS GROUP DELAY
I
0.9
I
I
I
I
TA =25°C
Input =± 3 V Sine Wave
I-
0.8
~
I
i:'
8
e
CJ
Q.
::::II
0.7
0.6
0.5
0.4
J
0.3
0.2
......"..
0.1
V
V
~
~
°°
2
3
4
5
6
7
Normalized Frequency
8
9
10
9
10
Figure 5-3
AID BAND-PASS RESPONSE
0.4
I
I
I
I
I
=
I
I
High-Pass SCF fclock 16 kHz
TA 25°C
Input ±3 V Sine Wave
=
0.2
=
III
'a
I
CD
'a
:ec
I
'a
Ii
III
:.=
°~
~
1\
"
r..,.I
-0.2
V \}
-0.4
,
-0.6
°
1
2
3
4
5
6
7
Normalized Frequency
8
Figure 5-4
Normalized Frequency x SCF fclock (kHz)
NOTE : Absolute Frequency (kHz)
288
For Low-Pass SCF fclock > 288 kHz, please calL the factory.
7-48
AID BAND-PASS FILTER RESPONSE SIMULATION
0
\
-10
-20
m
Hlgh·Pass SCF
fclock = 16 kHz
TA =25°C
Input =± 3 V Sine Wave
-
-30
"CJ
I
G)
"CJ
:Ec
i
::::&
-40
-50
-60
-70
(
-SO
-100
o
2
4
\
-
I "'"
~I
6
8 10 12 14
Normalized Frequency
16
18
20
Flgure5~
AID BAND-PASS FILTER GROUP DELAY
2
I
I
I
I
I
I
I
Hlgh·Pass SCF fclock = 16 kHz
TA =25°C
Input =±3 V Sine Wave
1.8
1.6
II
JCD
Q
a.
::J
e
CJ
-
1.4
1.2
1.1
11\
0.8
\
/ \
.-"'" ,
0.6
0.4
\
0.2
o
o
0.8 1.6 2.4 3.2 4.0 4.8 5.6 6.4 7.2 8.0
Normalized Frequency
Figure 5-8
NOTE: Absolute Frequency (kHz)
Normalized Frequency x SCF fclock (kHz)
= ------------~2~8~8------~~----
For Low-Pass SCFfclock > 288 kHz, please call the factory.
7-49
AID CHANNEL HIGH-PASS FILTER
20
TA=25°C
Input = ± 3 V Sine Wave
10
0
lit
,
-10
~
j
-20
i
-30
~
I~
c
:::&
r
I
-40
-50
-80
o
100 200 300 400 500 800 700 800 800 1000
Normalized Frequency
Figure 5-7
DIA (sin x)/x CORRECTION FILTER RESPONSE
4
,........
~
2
,
V
lit
~
0
V
/
v \,
1\
\
~
j
i\
C
at
:I
-2
-4
-8
~
o
\\
TA=25°C
Input = ± 3 V Sine Wave
\
I I I I I
2
4
8
8
10
12
14
18
18
20
Normalized Frequency
Figure 5-8
NOTE: Absolute Frequency (kHz) =
Normalized Frequency x SCF fclock (kHz)
288
For L~w-Pass SCF fclock > 288 kHz, please call the factory.
7-50
D/A (81n x)/x CORRECTION FILTER RESPONSE
500
TA=25°C
Input = ± 3 V Sine wave
400
( !\
•
::L
1300
i
I
I \
200
100
l/
V
,
1\
"'
I-"'
o
o
2
4
8
8 10 12 14 18
Normalized Frequency
18
20
Figure 5-8
D/A (81n x)/x CORRECTION ERROR
2
I
TA=2SOC
Input = ± 3 V Sine Wave
1.8
1.2
/
"V
(eln x) Ix Correction
/
0.8
I1
I
0.4
V
V
Error
-....r--.....
-'
0
1- 0•4
~
-0.8
-1.6
'"'"
~
"'
-1.2
-2
,.... ~
18.2 kHz (81n x) IX\
Distortion
,
'" '"
\
o
1
2
3
4
5
8
7
Normalized Frequency
8
8
10
Figure 5-10
NOTE: Absolute Frequency (kHz)
=
Normalized Frequency x SCF fclock (kHz)
288
For Low-Pass SCF fclock > 288 kHz, please call the factory.
7-51
AID BAND-PASSQROUP DELAY
760
720 I-III
T
680
"i
840
I
Low-pass SCF fclock = 144 kHz
High-pass SCF 'clock = 8 kHz
TA=25°C
Input = ± 3 V Sine Wave
~
i;'
Q
a.
e:s
600
I
c:J
-aIc
III
560
\
520
\,
II)
~
480
~
440
./
r-
/
/
I
/
J
/
400
o
0.4
0.8
1.2 1.6 2.0 2.4
, ..., Frequency - Hz
2.8
3.2 3.6
Figure 5-11
,
D/A LOW-PASS GROUP DELAY
560
I
520 _
480
1i
440
! .I
I
I,
~:~-:~ SCF 'clock = 144 kHz
Input = ± 3 V Sine Wave
III
T
I
i;'
Q
I
a.
:s
e
c:J
•
-a
!
Ii
II)
Q
~
400
360
320
280
240
200
V
o
0.4
0.8
V
/
)'
V
1.2 1.6 2.0 2.4
• - Frequency - Hz
Figure 5-12
7~2
I
2.8
3.2 3.6
AID SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL
100
90
ID
80
I
0
:;::;
70
"
t}.
c
1-kHz Input Signal
16-kHz Conversion Rate
TA 25°C
~
=
Gain
60
, /'
0
:e
.eIII
a
~
50
/'
40
'iiic
30
us
20
Gain
=4
=1
".,.-~
/'
Q
10
o
-50
-40
-30
-20
-10
0
10
Input Signal Relative to Vref - dB
Figure 5-13
AID GAIN TRACKING
(GAIN RELATIVE TO GAIN AT O-dB INPUT SIGNAL)
0.5
1-kHz Input Signal
0.4 I- 16-kHz Conversion Rate
TA
0.3
ID
0.2
I
0.1
"
Q
c
:s2
()
~
c
"iii
"
=25°C
,""
-
-0.1
-0.2
-0.3
-0.4
-0.5
-50
-40
-30
-20
-10
0
10
Input Signal Relative to Vref - dB
Figure 5-14
7-53
D/!t ~NVERT~R SIGNAL-To-DISTORTION RATIO,
vs
INPUT SIGNAL
,
100
,
Into 600 a
90 r- 180kHz Conversion Rate
'~1-kHz Input Signal
CD
'a
I
0
Ir:
70
80
~
50
i5
40
!
30
i
~
r
TA=25°C
80
,~
/
/
~
./
~
"""
20
10
o
~
-40
-30
-20
-10
0
Input Signal Relative to Vref- dB
10
Figure 5-15
D/A GAIN IRACKING (GAIN RELATIVE TO GAIN
AT G-dB INPUT SIGNAL)
0.5
0.4
i-kHz Input Slgnallnto'800 a
180kHz Conversion Rate
TA=~oC
0.3
CD
'a
I
aI
0.2
0.1
r:
:s
0
r:
-0.1
~
~
.......
,
/'
-0.2
-0.3
-0.4
-0.5
~
-40
-30
-20
-10
0
Input Signal Relative to Vref - dB
Figure 5-16
7-54
10
AID SECOND HARMONIC DISTORTION
va
INPUT SIGNAL
-100
-80
i-kHz Input Signal
ie-kHz Conversion Rate
-80
'1:1
I
c::
0
-70
!
-80
.S!
-50
I§
-40
i!
-V
is
8
:!
'1:1
-30
J
-20
c::
~~
TA = 25°C
III
V
-10
o
-50
-40
-30
-20
-10
0
10
Input Signal Relative to Vref - dB
Figure 5-17
D/A SECOND HARMONIC DISTORTION
va
INPUT SIGNAL
-100
-80
III
'1:1
I
c::
0
i!
~
.S!
c::
-80
i-kHz Input SIgn811nto $00 a
ie-kHz Conversion Rate
TA=25°C
-70
-80
V
~
----... , --
.......
-50
0
I§
:!
-40
'1:1
-30
J
-20
c::
-10
o
-50
-40
-30
-20
-10
0
10
Input Signal Relative to Vref - dB
Figure 5-18
7-55
AID THIRD HARMONIC DISTORTION
vs
INPUT SIGNAL
-100
i-Hz Input Signal
-90 roo 16-kHz Conversion Rate
TA 25°C
-80
=
ED
~
I
c
0
;:
I
C
()
'c0
~",,-
-70
-60
...
-50
~
-40
::z::
-30
./
",
,
"
III
l!
:c
I-
-20
-10
o
-50
-40
..,.30
-20
-10
0
10
Input Signal Relative to Vref - dB
Figure 5-19
D/A THIRD HARMONIC DISTORTION
vs
INPUT SIGNAL
-100
ED
~
I
c
-70
I
C
-60
f
I
I
I
_ i-kHz Input SIgn811nto 600 0
-90 16-kHz Conversion Rate
TA = 25°C
-80
~
i~
-50
::z::
-30
,
~
./
./
-40
III
l!
:c
I-
-20
-10
o
-50
-40
-30
-20
-10
o
Input Signal Relative to Vref - dB
Figure 5-20
7-56
10
6 Application Information
TMS320201C25
TLC32046
MSTRCLK
CLKOUT
FSX
FSX
DX
DX
FSR
FSR
DR
C
ANLGGND
DR
CLKR
+5V
VCC+
REF
SHIFTCLK
VCC-
-5V
VDD
+5V
CLKX
DGTLGND
A
C =0.2 ~, Ceramic
Figure 6-1. AIC Interface to the TMS32020/C25 Showing Decoupllng Capacitors
and Schottky Dlodet
t Thomson Semiconductors
VCC
3 V Output
TL431
0.01 J.LF
FOR: VCC =12 V, R =7200 n
VCC = 10 V, R =5600 n
VCC = 5 V, R = 1600 n
Figure 6-2. External Reference Circuit for TLC32046
7-57
7-58
TLC32047C, TLC320471
Data Manual
Wide-Band Analog Interface Circuit
•
TEXAS
INSTRUMENTS
7-69
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1995, Texas Instruments Incorporated
7-60
Contents
Section
1
2
Title
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.1 Features .............................................................
1.2 Functional Block Diagrams .............................................
1.3 Terminal Assignments .................................................
·1.4 Ordering Information ..................................................
1.5 Terminal Functions ....................................................
Page
7--65
7-66
7-67
7-70
7-70
7-71
Detailed Description ...................................................... 7-75
2.1
2.2
2.3
2.4
2.5
2.6
2.7
·2.8
2.9
. 2.10
2.11
2~ 12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
Internal Timing Configuration ...........................................
Analog Input ......... '.' ...............................................
AID Band-Pass Filter, AID Band-Pass Filter Clocking, and AID Conversion
Timing ................... , ...........................................
AID Converter ........................................................
Analog Output ........................................................
D/A Low-Pass Filter, D/A Low-Pass Filter Clocking, and D/A Conversion
Timing .................. ; ............................................
D/A Converter ........................................................
Serial Port ...........................................................
Synchronous Operation ................................................
2.9.1 One 16-Bit Word [Dual-Word (Telephone Interface) or Word Mode] ....
2.9.2 Two 8-Bit Bytes (Byte Mode) .....................................
2.9.3 Synchronous Operating Frequencies ..............................
Asynchronous Operation ...............................................
2.10.1 One 16-Bit Word (Word Mode) ................................. '"
2.10.2 Two 8-Bit Bytes (Byte Mode) .....................................
2.10.3 Asynchronous Operating Frequencies .............................
Operation of TLC32047 With Internal Voltage Reference ...................
Operation of TLC32047 With External Voltage Reference ..................
Reset ...............................................................
Loopback ............................................................
Communications Word Sequence .......................................
2.15.1 DR Word Bit Pattern .............................................
2.15.2 Primary OX Word Bit Pattern .....................................
2.15.3 Secondary OX Word Bit Pattern ...................................
Reset Function .......................................................
Power-Up Sequence ..................................................
AIC Register Constraints ............................................ : ..
AIC Responses to Improper Conditions ..................................
Operation With Conversion Times Too Close Together .....................
7-76
7-78
7-78
7-78
7-78
7-78
7-79
7-79
7-79
7-79
7-80
7-80
7-80
7-80
7-80
7-81
7-81
7-81
7-81
7-81
7-82
7-82
7-83
7-84
7-84
7-85
7-85
7-85
7-86
7-61
Contents (Continued)
Sec#on
rme
2.21 More Than One Receive Frame Sync Occurring Between Two Transmit
Frame Syncs - Asynchronous Operation. . . . . . . . . • • . • . • • • • . . . . . • • . . • . . . •.
2.22 More Than One Transmit Frame Sync Occurring Between Two Receive
Frame Syncs - Asynchronous Operation .•.........•••..••.•••.•.•••••..•
2.23 More than One Set of Primary and Secondary OX Serial Communications
Occurring Between Two Receive Frame Syncs (See OX Serial Data Word
Format section) - Asynchronous Operation .........•...•...••...•.....•.
2.24 System Frequency Response Correction. . . . . . . . . . . . . . . . . . . • • • . . . . • • . • . •.
2.25 (Sin x)/x Correction ....•....•..•......•..•...........••...•..••.••..••
2.26 (Sin x)/x Roll-Off for a Zero-Order Hold Function ..........•..•....•••..•..
2.27 Correction Filter .........................................•............
2.28 Correction Results ....•••.....••............. ; ...•.....••..........•..
2.29 TMS320 Software Requirements .......••.......•..•...•..••..•.•.•.•.••
3
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range •...
3.2 Recommended Operating Conditions ..•.•.•.......••.....•••••..•...•••.
3.3 Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, Vcc+ =5 V, Vcc- =-5 V, Voo =5 V ................
3.3.1 Total Device, MSTR ClK Frequency. 5.184 MHz,
Outputs Not loaded .....••.••...•....•....•.•.•..•..•..••.••....
3.3.2 Power Supply Rejection and Crosstalk Attenuation •..•..•••.••......
3.3.3 Serial Port ......•....•.••••....•.•....•......•...•...•....••••.
3.3.4 Receive Amplifier Input .•..••••.•...••.•••......••...•.••••••....
3.3.5 Transmit Filter Output ...•....•.•....•....••......•....••....•..•
3.3.6 Receive and Transmit Channel System Distortion, SCF Clock
Frequel1cy =432kHz ...•......••...•.....•........••..•.••......
3.3.7 Receive Channel Signal-to-Distortion Ratio ...•.......•••••.•...•.•.
3.3.8 Transmit Channel Signal-to-Distortion Ratio •........•.......•••...•
3.3.9 Receive and Transmit Gain and Dynamic Range .•.•••••••...•••••.
3.3.10 Receive Channel Band-Pass Filter Transfer Function,
SCF fclock =432 kHz, Input (IN+ -IN-) is a +3-V Sine Wave. • . . • • • ..
3.3.11 Receive and Transmit Channel low-Pass Filter Transfer Function,
SCF fclock =432 kHz .........•..........•.......' •..........•....
3.4 Operating Characteristics Over Recommended Operating Free-Air
Temperature Range, VCC+ =5 V, VCC- - -5 V, VOO. 5 V ................
3.4.1 Receive and Transmit Noise (Measurement Includes low-Pass and
Band-Pass Switched-Capacitor Filters) ••••..•..••..•••••••••••....
3.5 Timing Requirements ...••..•...•.•.••••••••••.•.•.••••.•..•.•.•..••..•
3.5.1 Serial Port Recommended Input Signals ..••...•••••••.•.••••.•••..
7-62
Page
7-86
7-87
7-87
7-88
7-88
7-88
7-89
7-89
7-90
7-81
7-91
7-92
7-92
7-92
7-93
7-93 \
7-93
7-93
7-94
7-94
7-95
7-95
7-95
7-96
7-96
7-96
7-97
7-97
Contents (Continued)
Section
Title
Page
=
3.5.2 Serial Port - AIC Output Signals, CL 30 pF for SHIFT ClK Output,
CL = 15 pF, For All Other Outputs ....•......•.......................... 7-97
4
Parameter Measurement Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-89
4.1 TMS32047 - Processor Interface ...................................... 7-102
5
Typical Characteristics . .................................................. 7-105
6
Application Information .. ................................................ 7-115
7-63
List of Illustrations
Figure
1-1.
1-2.
1-3.
2-1.
2-2.
2-3:
2-4.
2-5.
2-6.
2-7.
2-8.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
6-1.
6-2.
Title
Dual-Word (Telephone Interface) Mode ................................ .
Word Mode .........................................................
Byte Mode ......................................................... .
Asynchronous Internal Timing Configuration ............................ .
Primary and Seconda~ C.ommunications Word Sequenc~ ......... \ ...... .
Reset on Power-Up CircUit ........................................... .
Conversion Times Too Close Together ................................. .
More Than One Receive Frame Sync Between Two Transmit Frame Syncs .
More Than One Transmit Frame Sync Between Two Receive Frame Syncs .
More Than One Set of Primary and Secondary OX Serial Communications
Between Two Receive Frame Syncs ................................... .
First-Order Correction Filter .......................................... .
IN+ and IN- Gain Control Circuitry ............... '..................... .
Dual-Word (Telephone Interface) Mode Timing .............•.............
Word Timing ................... : .................................... .
Byte-Mode Timing ................................................... .
Shift-Clock Timing ................................................... .
TMS32010rrMS320C15-TLC32047 Interface Circuit .................... .
TMS3201 OrrMS320C15-TLC32047 Interface Timing ................... .
AIC Interface to the TMS32020/C25 Showing Decoupling
Capacitors and Schottky Diode ....................................... .
External Reference Circuit for TLC32047 ............................... .
Page
7-68
' 7-69
7-69
7-77
7-82
7-85
7-86
7-87
7-87
7-88
7-89
7-99
7-100
7-100
7-101
7-102
7-102
7-103
7-115
7-115
List of Tables
Table
2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
4-1.
7-64
Title
Mode-Selection Function Table ................ , ...................... .
Primary OX Serial Communication Protocol ............................. .
Secondary OX Serial Communication Protocol .......................... .
AIC Responses to Improper Conditions ................................ .
(Sin x)/x Roll-Off Error ............................................... .
(Sin x)/x Correction Table for f8 = 8000 Hz and f8 = 9600 Hz .............. .
Gain Control Table (Analog Input Signal Required for Full-Scale Bipolar AID
Conversion Twos Complement) ....................................... .
Page
7-75
7-83
7-84
7-86
7-89
7-90
7-99
1 Introduction
The TLC32047 wide-band analog interface circuit (AIC) is a complete analog-to-digital and digital-to-analog
interface system for advanced digital signal processors (DSPs) similar to the TMS32020, TMS320C25, and
TMS320C30. The TLC32047 offers a powerful combination of options under DSP control: three operating
modes [dual-word (telephone interface), word, and byte] combined with two word formats (8 bits and 16 bits)
and synchronous or asynchronous operation. It provides a high level of flexibility in that conversion and
sampling rates, filter bandwidths, input circuitry, receive and transmit gains, and multiplexed analog inputs
are under processor control.
This AIC features a
•
•
•
•
band-pass switched-capacitor antialiasing input filter
14-bit-resolution AID converter
14-bit-resolution D/A converter
low-pass switched-capacitor output-reconstruction filter
The antialiasing input filter comprises eighth-order and fourth-order CC-type (Chebyshev/elliptic
transitional) low-pass and high-pass filters, respectively. The input filter is implemented in switchedcapacitor technology and is preceded by a continuous time filter to .eliminate any possibility of aliasing
caused by sampled data filtering. When low-pass filtering is desired, the high-pass filter can be switched
out of the signal path. A selectable auxiliary differential analog input is provided for applications where more
than one analog input is required.
The output-reconstruction filter is an eighth-order CC-type (Chebyshev/elliptic transitional low-pass filter)
followed by a second-order (sin x)/x correction filter and is implemented in switched-capacitor technology.
This filter is followed by a continuous-time filter to eliminate images of the sample data signal. The on-board
(sin xlIx correction filter can be switched out of the signal path using digital signal processor control.
The AID and D/A architectures ensure no missing codes and monotonic operation. An internal voltage
reference is provided to ease the design task and to provide complete control over the performance of the
IC. The internal voltage reference is brought out to REF. Separate analog and digital voltage supplies and
ground are provided to minimize noise and ensure a wide dynamic range. The analog circuit path contains
only differential circuitry to keep noise to a minimum. The exception is the DAC sample-and-hold, which
utilizes pseudo-differential circuitry.
The TLC32047C is characterized for operation from O°C to 70°C, and the TLC320471 is characterized for
operation from -40°C to 85°C.
7-65
1.1
•
•
•
•
•
Features
14-Blt Dynamic Range ADC and DAC
16-Blt Dynamic Range Input With Programmable Gain
Synchronous or Asynchronous ADC and DAC Sampling Rates Up to 25,000 Samples Per
Second
Programmable Incremental ADC and DAC Conversion Timing Adjustments
Typical Applications
- Speech Encryption for Digital Transmission
- Speech Recognition and Storage Systems
- Speech Synthesis
- Modems at 8-kHz, 9.6-kHz, and 16-kHz Sampling Rates
- Industrial Process Control
- Blomedlcallnstrumentatlon
•
•
- Acoustical Signal Processing
- Spectral Analysis
- Instrumentation Recorders
- Data Acquisition
Switched-Capacitor Antlallaslng Input Filter and Output-Reconstruction Filter
Three Fundamental Modes of Operation: Dual-Word (Telephone Interface), Word, and Byte
•
•
6Oo-mll Wide N Package
Digital Output in Twos Complement Format
•
CMOS Technology
FUNCTION TABLE !
DATA
FORMAT
SYNCHRONOUS ASYNCHRONOUS
(CONTROL
(CONTROL
REGISTER
REGISTER
BIT 05= 1)
BIT 05= 0)
FORCING CONDITION
DIRECT
INTERFACE
16-bit format
Dual-word
(telephone
interface) mode
Dual-word
(telephone
interface) mode
DATA-DR/CONTROL .. 0 to 5 V
FSDIWORD-BYTE - 0 to 5 V
16-bit format
Word mode
Word mode
DATA-DR/CONTROL .. VCC-(-5 V nom) TMS32020.
TMS320C25.
FSDIWORD-BYTE - VCC+ (5 V nom)
TMS320C30.
indirect
interface to .
TMS320C10
(see Figure 7)
8-bit format
(2 bytes
required)
Byte mode
Byte mode
DATA-DR/CONTROL .. VCC-(-5 V nom) TMS320C17
FSDIWORD-BYTE .. VCC- (-5 V nom)
7-66
TMS32020.
TMS320C25.
TMS320C30
1.2
Functional Block Diagrams
WORD OR BYTE MODE
IN+ 2:;;;,1It-............
IN - 25:-:-t-_-VAUX IN + 2:..:.41----1".....
AUX IN _ 23
......._ .........
Racalva Section
Low-Pass
Flltar
Sarlal
Port
AID
High-Pass
Filter
r,:-- -;,
5
DR
4
3
FSR
II
MSTRCLK
10 SHIFTCLK
I
Internal
I
Voltage
I
I Reference I
L!:_
_::.J
1 WORD-
------------------~
BYTE
13 CONTROL
12 DX
14 _
FSX
Low-Pass
Filter
20
VCC+
9
EODR
EODX
7
8
REF
DGTL
VDD
GND (Digital)
DUAL-WORD (TELEPHONE INTERFACE) MODE
IN+ 2:;;;,8t-............
25
IN -2~4t---t.o~
AUXIN+~-.......
AUX IN _ 23
......._ .........
Low-Pass
Filter
Serial
Port
AID
II
4
3
Racalva Section
High-Pass
Flltar
r,:-
-;,
I Intarnal I
Voltage
I
I Raference I
L!:_ __::.J
---------------------1
Low-Pass
Filter
20
VCC+
7
DGTL . VDD
GND (Digital)
II
DR
FSR
D110UT
MSTRCLK
10
SHIFTCLK
1_
FSD
13
DATA-DR
12
DX
14_
FSX
11
D100UT
8
REF
7-67
FRAME SYNCHRONIZATION FUNCTIONS
TLC32047 Function
Frame Sync Output
Receiving serial data on DX from processor to internal DAC
FSXlow
Transmitting serial data on DR from internal ADC to PI'QC~sor, piimary communications
FSRlow
Transmitting serial data on DR from DATA-DR to processor, secondary communications in
dual-word (telephone interface) mode only
FSD'low
5V
201
26
Analog In
25
VCC+
-5V
191
VCCDR
IN+
IN-
TLC32047
FSR
Serial Data Out
5
4
3
D110UT
Analog Out
....
....
22
21
OUT+
OX
12 Serial Data In
TMS32020,
. TMS320C25,
TMS320C30,
or Equivalent
16-BltDSP
OUTFSX
14
TTL or CMOS
Logic Levels
11
D100UT
.....
1
FSD
SeCondary Commu nl~tlon (see Table above)
Serial Data Input
13
DATA·DR .....
16-Blt Format TTL
orCMOSLog Ic. Levels
Figure 1-1. Dual·Word (Telephone Interface) Mode
When the DATA·DR/CONTROL input is tied to a logic signal source varying between 0 and 5 V, the
TLC32047 is in the dual-word (telephone interface) mode. This logic signal is routed to the DR line for input
to the DSP only when terminal 1, data frame synchronization (FSD), outputs a low level. The FSD pulse
duration i~ 16 shift clock pulses. Also, in this mode, the control register data bits 010 and 011 appear on
D100UT and D110UT, respectively, as outputs.
7-68
5V
-5V
191
201
..
..
... 26
Analog In
VCC-
VCC+
... 25
DR
IN+
IN-
TLC32047
FSR
EODR
22
Analog Out
21
OUT+
OX
EODX
1
~
..
4
3
12
Serial Data In
,
TMS32020,
TMS320C25,
TMS320C30,
or Equivalent
16-Blt DSP
OUTFSX
VCC+
(5 V nom)
Serial Data Out
5
WORD-BYTE
CONTROL
14
11
~
TTL or CMOS
Logic Levels
..
VCC(- 5Vnom)
13
Figure 1-2.Word Mode
5V
-5V
201
191
VCC-
VCC+
26
Analog In
25
DR
IN+
IN-
TLC32047
FSR
EODR
22
~
AnalogOut
21
,
OUT+
OX
EO OX
1
~
..
Serial Data Out
4
~
..
3
~
12
WORD-BYTE
CONTROL
TMS320C17
or Equivalent
8-Blt Serial
Interface
(2 Bytes Required)
..Serial Data In
.,
OUTFSX
VCC(-5 V nom)
5
..
14
TTL or CMOS
Logic Levels
11
13
,
VCC(-5 V nom)
Figure 1~. Byte Mode
The word or byte mode is selected by first connecting the DATA-DR/CONTROL input to Vee-.
FSDIWORD-BYTE becomes an input and can then be used to select either word or byte transmission
formats. The end-of~ata transmit (EODX) and the end-of-data receive (EODR) signals on terminals 11 and
3, respectively, are used to signal the end of word or byte communication (see the Terminal Functions
section).
7-69
1.3
Terminal Assignments
FNPACKAGE
{TOP VIEW)
N PACKAGEt
{TOP VIEW)
FSDIWORD-BYTE;
RESET
D110UT/EODR;
FSR
DR
MSTRCLK
VDD
REF
DGTLGND
SHIFTCLK
NU
NU
IN+
INAUX IN+
AUXINOUT+
OUTVCC+
VCCANLGGND
ANLGGND
NU
NU
D100UT/EODX;
OX
DATA-DR/CONTROL;
FSX
t..
I~ow
~
C
0
a:
~
J z+
I ~ gIia: I~:J :z_
LL.C
LL.Z
54 3 2 1 28272625
SHIFTCLK
6
7
8
9
10
24
23
22
21
INAUXIN+
AUXIN-
D100UT/EODX;
IX
xco~zzzz
"'!J
::J ::J C C
a:
I-
Z
o
~
C)C)
C)C)
...J...J
ZZ
«
C
~
~
NU - Nonusable; no external connection should be made to these pins.
t 600-mil wide
; The portion of the terminal name to the left of the slash is used for the dual-word (telephone interface) mode.
The portion of the terminal name to the right of the slash is used for word-byte mode.
1.4
Ordering Information
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
PLASTIC CHIP CARRIER
(FN)
PLASTIC DIP
(N)
O°C to 70°C
TLC32047CFN
TLC32047CN
-40°C to 85°C
TLC320471FN
TLC32047IN
>
7-70
1.5 Terminal Functions
TERMINAL
NAME
ANLGGND
NO.
I/O
DESCRIPTION
Analog ground retum for all internal analog circuits. ANlG GND is intemally connected
toDGTlGND.
17,18
AUXIN+
24
I
Noninverting auxiliary analog input stage. AUX IN + can be switched into the band-pass
filter and ADC path via software control. If the appropriate bit in the control register is
a 1, the auxiliary inputs replace the IN + and IN- inputs.lfthe bit is a 0, the IN + and INinputs are used (see the OX Serial Data Word Format).
AUXIN-
23
I
Inverting auxiliary analog input (see the above AUX IN + description).
DATA-DR
13
I
The dual-word (telephone interface) mode, selected by applying an input logic level
between 0 and 5 V to DATA-DR, allows DATA-DR to function as a data input. The data
is then framed by the FSD signal and transmitted as an output to DR during secondary
communication. The functions FSD, D110UT, and D100UT are valid with this mode
selection (see Table 2-1).
When CONTROL is tied to V~he device is in the word or byte mode. The functions
WORD-BYTE, EODR, and E OX are valid in this mode. FSDIWORD-BYTE is then
used to select either the word or byte mode (see Function Table).
CONTROL
DR
5
0
DR is used to transmit the ADC output bits from the AIC to the TMS320 serial port. This
transmission of bits from the AIC to the TMS320 serial port is synchronized with the
SHIFT ClK Signal.
OX
12
I
OX is used to receive the DAC input bits and timing and control information from the
TMS320. This serial transmission from the TMS320 serial port is synchronized with the
SHIFT ClK signal.
D100UT
11
0
In the dual-word (telephone interface) mode, bit 010 of the control register is output to
01 OOUT. When the device is reset, bit 010 is initialized to 0 (see OX Serial Data Word
Fonnat). The output update is immediate upon changing bit 010.
EODX
End of data transmit. During the word-mode timing, a low-going pulse occurs on EODX
immediately after the 16 bits of DAC and control or register infonnation have been
transmitted from the TMS320 serial port to the AIC. EODX can be used to interrupt a
microprocessor upon completion of serial communications. Also, EODX can be used
to strobe and enable extemal serial-to-parallel shift registers, latches, or external FIFO
RAM and to facilitate parallel data bus communications between the DSP and the
serial-to-parallel shift registers. During the byte-mode timing, EODX goes low after the
first byte has been transmitted from the TMS320 serial port to the AIC and is kept low
until the second byte has been transmitted. The TMS320C17 can use this low-going
signal to differentiate first and second bytes.
7-71
1.5
Terminal Functions (continued)
TERMINAL
NAME
NO.
D110UT
3
I/O
DESCRIPTION
0
In the dual-word (telephone interface) mode, bit 011 of the control register is output to'
011 OUT. When the device is reset, bit D11 is initialized to 0 (see OX Serial Data Word
Format)~ The output update is immediate upon changing bit D11.
End of data receive. During the word-mode timing, a low-going pulse occurs on EODR
immediately after the 16 bits of AID information have been transmitted from the AIC to
the TMS320 se.rial port. EODR can be used to interrupt a microprocessor upon
completion of serial communications. Also, EODR can be used to strobe and enable
external serial-to-parallel shift registers, latches, or external FI FO RAM, and to facilitate
parallel data bus communications between the DSP and the serial-to-parallel shift
registers. During the bytErmode timing, EODR goes low after the first byte has been
transmitted from the AIC to the TMS320 serial port and is kept low until the second byte
has been transmitted. The TMS320C17 can use this low-going signal to differentiate
between first and second bytes.
EODR
DGTLGND
FSD
9
1
WORD-BYTE
Digital ground for all internal logic circuits. Not internally connected to ANLG GND.
0
Frame sync data. The FSD output remains high during primary communication. In the
dual-word (telephone interface) mode, the FSD output is identical to the FSX output
during secondary communication.
I
WORD-BYTE allows differentiation between the word and byte data format (see
DATA-DR/CONTROL and Table 2-1 for details).
FSR
4
0
Frame sync receive. FSR is held low during bit transmission. When FSR goes low, the
TMS320 serial port begins receiving bits from the AIC via DR of the AIC. The most
significant DR bit is present on DR before FSR goes low (see Serial Port Sections and
Internal Timing Configuration Diagrams).,
FSX
14
0
Frame sync transmit. When FSX goes low, the TMS320 serial port begins transmitting
bits to the AIC via DX of the AIC. FSX is held low during bit transmission (see Serial Port
Sections and Internal Timing Configuration Diagrams).
IN+
IN-
26
I
Noninverting input to analog input amplifier stage
25
I
Inverting input to analog input amplifier stage
MSTRCLK
6
I
Master clock. MSTR CLK is used to derive all the key logic signals of the AIC, such as
the shift clock, the switched-capacitor filter clocks, and the AID and D/A timing signals.
The intemal timing configuration diagram shows how these key signals are derived. The
frequencies of these signals are synchronous submultiples of the master clock
frequency to eliminate unwanted aliasing when the sampled analog signals are
transferred between the switched-capacitor filters and the ADC and DAC converters
(see the Internal Timing Configuration).
OUT+
22
0
Noninverting output of analog output power amplifier. OUT+ drives transformer hybrids
or high-impedance loads directly in a differential or a singlErended configuration.
OUT-
21
0
Inverting output of analog output power amplifier. OUT-is functionally identical with and
complementary to OUT+.
REF
8
1/0
Internal voltage reference is brought out on REF. An external voltage reference can be
applied to REF to override the internal voltage reference.
7-72
1.5
Terminal Functions (continued)
TERMINAL
NAME
NO.
110
DESCRIPTION
RESET
2
I
Reset. A resetfunction is provided to initialize TA,TA', TB, RA, RA', RB (see Figure 2-1),
and the control registers. This reset function initiates serial communications between
the AIC and DSP. The reset function initializes all AIC registers, including the control
register. After a negative-going pulse on RESET, the AIC registers are initialized to
provide a 16-kHz data conversion rate for a 1O.368-MHz master clock input signal. The
conversion rate adjust registers, TA' and RA', are resetto 1. The CONTROL register bits
are reset as follows (see AIC DX Data Word Format section):
011 .. 0, D10 - 0, 09 .. 1, D7 - 1, D6 .. 1, 05 = 1, 04 - 0, 03 = 0, D2 - 1
The shift clock (SCll<) is held high during RESET.
This initialization allows normal serial-port communication to occur between the AIC
and the DSP.
SHIFTClK
10
0
Shift clock. SHI FT ClK is obtained by dividing the master clock signal frequency by four.
SHIFT ClK is used to clock the serial data transfers of the AIC.
VDD
7
Digital supply voltage, 5 V ±50/0
VCC+
20
Positive analog supply voltage, 5 V ±50/0
VCC-
19
Negative analog supply voltage, -5 V ±50/0
7-73
7-74
2
Detailed Description
Table 2-1. Mode-Selection Function Table
DATA-DR!
CONTROL
Data in
(Ot05V)
Data in
(Oto5V)
FSDI
WORD-BYTE
FSDout
(Ot05V)
FSD out
(0 to 5 V)
CONTROL
OPERATING
SERIAL
REGISTER
CONFIGURATION
MODE
BIT (05)
Synchronous,
One 16-Bit Word
Terminal functions DATA-DRt,
FSDt, D110UT, and D100UTare
applicable in this configuration.
FSD is asserted during
secondary communication, but
the FSR is not asserted.
However, FSD remains high
during primary communication.
Asynchronous,
One 16-bit Word
Terminal functions DATA-DRt,
FSDt, D110UT, and D100UT are
applicable in this configuration.
FSD is asserted during
secondary communication, but
the FSR is not asserted.
However, FSD remains high
during primary communication. If
secondary communications occur
while the NO conversion is being
transmitted from DR, FSD cannot
go low, and data from DATA-DR
cannot go onto DR.
Synchronous,
One 16-Bit Word
Terminal functions CONTROLt,
WORD-BYTEt, EODR, and
EODX are applicable in this
configuration.
0
Asynchronous,
One 16-bit Word
Terminal functions CONTROLt,
WORD-BYTEt, EODR, and
EODX are applicable in this
configuration.
1
. Synchronous,
Two 8-Bit Bytes
Terminal functions CONTROLt,
WORD-BYTEt, EODR, and
EODX are applicable in this
configuration.
1
0
Dual-Word
(Telephone
Interface)
Dual-Word
(Telephone
Interface)
1
WORD
VCC+
VCe-
VCe-
DESCRIPTION
BYTE
Terminal functions CONTROLt,
WORD-BYTEt, EODR, and
0
EODX are applicable in this
configuration.
t DATA-DR/CONTROL has an intemal pulJdown resistor to -5 V, and FSDIWORD-BYTE has an intemal pulJup resistor
t05 V.
Asynchronous,
Two 8-Bit Bytes
7-75
2.1
Internal Timing Configuration (see Figure 2-1)
All the internal timing of the AIC is derived from the high-frequency clock signal that drives the master clock
input. The shift clock signal, which strobes the serial port data between the Ale and DSP, is derived by
dividing the master clock input signal frequency by four.
The TX(A) counter and the TX(B) counter, which are drivenby the master clock signal, determine the D/A
conversion timing. Similarly, the RX(A) counter and the RX(B) counter determine the AID conversion timing.
In order for the low-pass switched-capacitor filter in the D/A path (see Functional Block Diagram) to meet
its transfer function specifications, the frequency of its clock input must be 432 kHz. If the clock frequency
is not 432 kHz, the filter transfer function frequencies are frequency-scaled by the ratios of the clock
frequency to 432 kHz:
'
.
Normalized Frequency x SCF fclock (kHz)
(1 )
432
To obtain the specified filter response, the combination of master clock frequency and the TX(A) counter
and the RX(A) counter values must yield a 432-kHz switched-capacitor clock signal. This 432-kHz clock
signal can then be divided by the TX(B) counter to establish the D/A conversion timing.
Absolute Frequency (kHz)
The transfer function of the band-pass switched-capacitor filter in the AID path (see Functional Block
Diagram) is a composite of its high-pass and low-pass transfer functions. When the shift clock frequency
(SCF) is 432 kHz, the high-frequency roll-off of the low-pass section meets the band-pass filter transfer
function specification. Otherwise, the high-frequency roll-off is frequency-scaled by the ratio of the
high-pass section's SCF clock to 432 kHz (see Figure 5-5). The low-frequency roll-off of the high-pass
section meets the band-pass filter transfer function specification when the AID conversion rate is 24 kHz.
If not, the low-frequency roll-off of the high-pass section is frequency-scaled by the ratio of the AID
conversion rate to 24 kHz.
The TX(A) counter and the TX(B) counter are reloaded each D/A conversion period, while the RX(A) counter
and the RX(B) counter are reloaded every AID conversion period. The TX(B) counter and the RX(B) counter
are loaded with the values in the TB and RB registers, respectively. Via software control, the TX(A) counter
can be loaded with the TA register, the TA register less the TA' register, orthe TA register plus the TN register.
By selecting the TA register less the TA' register option, the upcoming conversion timing occurs earlier by
an amount of time that equals TA' times the signal period of the master clock. If the TA register plus the TA'
register option is executed, the upcoming conversion timing occurs later by an amount of time that equals
TA' times the signal period of the master clock. Thus, the D/A conversion timing can be advanced or
retarded. An identical ability to alter the AID conversion timing is provided. However, the RX(A) counter can
be programmed via software control with the RA register, the RA register less the RN register, or the RA
register plus the RA' register.
The ability to advance or retard conversion timing is particularly useful for modem applications. This feature
allows controlled changes in the AID and 01A conversion timing and can be used to enhance signal-to-noise
performance, to perform frequency-tracking functions, and to generate nonstandard modem frequencies.
If the transmit and receive sections are configured to be synchronous, then the low-pass and band-pass
switched-capacitor filter clocks are derived from the TX(A) counter. Also, both the D/A and AID conversion
timings are derived from the TX(A) counter and the TX(B) counter. When the transmit and receive sections
are configured to be synchronous, the RX(A) counter, RX(S) counter, RA register, RA' register, and RB
registers are not used.
7-76
r----, 20.736 MHZ _ - - - - - ,
41.472 MHZ
TMS320DSP
5.1B4MHz
MASTER CLOCK 10.368 MHz
SHIFT CLOCK
1.296 MHz
2.592 MHz
SCFCLOCK
Low-Pass Filter,
(sin x)/x Filter
Transmit Section
D/A Conversion
Timing
7.20 kHz for TB .. 60
8.00 kHz for TB ... 54
9.60 kHz for TB '" 45
14.4 kHz for TB .. 3D
16.0 kHz for TB .. 27
24.0 kHz for TB .. 18
TX (A) Counter
(6 Bits)
~~!!!~J:::-:::-=1 TX (B) Counter
432 kHz _ _ _ _ __
D/A Conversion
Frequency
SCFCLOCK
Low·Pass Filter
Receive Section
AID Conversion
Timing
7.20 kHz for RB = 60
8.00 kHz for RB .. 54
9.60 kHz for RB 45
14.4 kHz for RB 3D
16.0 kHz for RB '" 27
24.0kHzforRB= 18
=
=
RX (A) Counter
(6 Bits)
Hlgh·Pass Filter,
AID Conversion
Frequency
t These control bits are described in the OX Serial Data Word Format section.
NOTES: D. Tables 2-2 and 2-3 (pages 2-9 and 2-10) are primary and secondary communication protocols,
respectively.
E. In synchronous operation, RA, RA', RB, RX(A), and RX(B) are not used. TA, TA'. TB. TX(A). and TX(B) are
used instead.
F. Items in italics refer only to frequencies and register contents. which are variable. A crystal oscillator driving
20.736 MHz into the TMS320-series OSP provides a master clock frequency of 5.184 MHz. The TLC32047
produces a shift clock frequency of 1.296 MHz. If the TX(A) register contents equal 6, the SCF clock
frequency is then 432 kHz. and the OIA conversion frequency is 432 kHz + T(B).
Figure 2-1. Asynchronous Internal Timing Configuration
7-77
2.2
Analog Input
Two pairs of analog inputs are provided. Normally, the IN + and IN - input pair is used; however, the auxiliary .
input pair, AUX IN + and AUX IN-, can be used if a second input is required. Since sufficient common-mode
range and rejection ar~ provided, each input set can be operated in differential or single-ended modes. The
gain for the IN+,IN-,A,uX IN+,andAUX IN-inputs can be programmed to 1,2, or4 (see Table 4-1). Either
input circuit can be selected via software control. Multiplexing Is controlled with the D4 bit (enable/disable
AUX IN + and AUX IN-) of the secondary DX word (see Table 2-3). The multiplexing requires a 2-ms wait
at SCF = 432 kHz (see Figure 5-3) for a valid output signal. A wide dynamic range is ensured by the
differential internal analog architecture and the separate analog and digital voltage supplies and grounds.
2.3
AID Band-Pass Filter, AID Band-Pass Filter Clocking, and AID Conversion
Timing
The receive-channel AID high-pass filter can be selected or bypassed via software control (see Functional
Block Diagram). Th~ frequency response of this filter is on page 3-5. This response results when the
switched-capacitor filter clock frequency is 432 kHz and the AID sample rate is 24 kHz. Several possible
options can be used to attain a 432-kHz switched-capacltor filter clock. When the filter clock frequency is
not 432 kHz, the low-pass filter transfer. function is frequency-scaled by the ratio of the actual clock
frequency to 432 kHz (see Typical CharaCteristics section). The ripple bandwidth and 3-dB low-frequency
roll-off points of the high-pass section are 450 Hz and 300 Hz, respectively. However, the high-pass section
low-frequency roll-off is frequency~scaled by the ratio of the AID sample rate to 24 kHz.
Figure 2-1 and the DX Serial Data Word Format sections of this data manual indicate the many options for
attaining a 432-kHz band-pass switched-capacitor filter clock. These sections indicate that the RX(A)
counter can be programmed to give a 432-kHz band-pass switched-capacitor filter clock for several master
clock input frequencies.
The AID conversion rate is attained by frequency-dividing the band-pass switched-capacitor filter clock with
the RX(B) counter. Unwanted aliasing is prevented because the AID conversion rate is an integer
submultiple of the band-pass switched-capacitor filter sampling rate, and the two rates are synchronously
locked.
2.4
AID Converter
Fundamental performance specifications for the receive channel ADC circuitry are on pages 3-2 and 3-3
of this data manual. The ADC circuitry, using switched-capacitor techniques, provides an inherent
sample-and-hold function.
2.5
Analog Output
The analog output Circuitry is an analog output power amplifier. Both non inverting and inverting amplifier
outputs are brought out of the IC. This amplifier can drive transformer hybrids or low-impedance loads
directly in either a differential or single-ended configuration.
2.6
D/A Low-Pass Filter, D/A Low-Pass Filter Clocking, and D/A Conversion
Timing
The frequency response of these filters is on page 3-5. This response results when the low-pass
switched-capacltor filter clock frequency is 432 kHz (see Equation 1). Like the AID filter, the transfer function
of this filter is frequency-scaled when the clock frequency .is not 432 kHz (see TYPical Characteristics
section). A continuous-time filter is provided on the output of the low-pass filter to eliminate the periodic
sample data signal information, which occurs at multiples of the 432-kHz switched-capacitor clock
feedthrough.
The D/A conversion rate is attained by frequency-dividing the 432-kHz switched-capacitor filter clock with
the T(B) counter. Unwanted aliasing is prevented because the D/A conversion rate is an integer submultiple
of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.
7-78
01A Converter
2.7
Fundamental performance specifications for the transmit channel DAC circuitry are on pages 3-3 and 3-4.
The DAC has a sample-and-hold function that is realized with a sWitched-capacitor ladder.
2.8
Serial Port
The serial port has four possible configurations summarized in the function table on page 1-2. These
configurations are briefly described below.
2.9
•
The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS320C17. The communications protocol is two 8-bit bytes.
•
The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS32020, TMS320C25, and TMS320C30. The communications protocol is
one 16-bit word.
•
The transmit and receive sections are operated synchronously, and the serial port interfaces
directly with the TMS320C17. The communications protocol is two 8-bit bytes.
•
The transmit and receive sections are operated synchronously, and the serial port interfaces
directly with the TMS32020, TMS320C25, TMS320C30, or two SN74299 serial-to-parallel shift
registers, which can interface in parallel to the TMS32010, TMS320C15, to any other digital
signal processor, or to external FIFO circuitry. The communications protocol is one 16-bit word.
Synchronous Operation
When the transmit and receive sections are operated synchronously, the low-pass filter clock drives both
low-pass and band-pass filters (see Functional Block Diagram). The AID conversion timing is derived from
and equal to the D/A conversion timing. When data bit 05 in the control register is a logic 1, transmit and
receive sections are synchronous. The band-pass switched-capacitor filter and the AID converter timing are
derived from the TX(A) counter, the TX(8) counter, and the TA and Tfl: registers. In synchronous operation,
both the AID and the D/A channels operate from the same frequencies. The FSX and the FSR timing is
identical during primary communication, but FSR is not asserted during secondary communication because
there is no new AID conversion result.
2.9.1
One 16-Blt Word [Dual-Word (Telephone Interface) or Word Mode]
The serial port interfaces directly with the serial ports of the TMS32020, TMS320C25, and the TMS320C30,
and communicates in one 16-bit word. The operation sequence is as follows:
1.
2.
3.
4.
FSX and FSR are brought low by the TLC32047 AIC.
One 16-bit word is transmitted and one 16-bit word is received.
FSX and FSR are brought high.
EODX and EODR emit low-going pulses one shift clock wide. EODX and EODR are valid in the
word or byte mode only.
If the device is in the dual-word (telephone interface) mode, FSD goes low during the secondary
communication period and enables the data word received at the DATA-DR/CONTROL input to be routed
to the DR line. The secondary communication period ocpurs four shift clocks after completion of primary
communications.
.
7-79
2.9.2
Two 8-Blt Bytes (Byte Mode)
The serial port interfaces directly with the serial port of the TMS320C17 and communicates in two 8-bit
bytes. The operation sequence is as follows: .
1.
2.
3.
4.
5.
6.
7.
2.9.3
FSX and ~ are brought low.
One 8-bit word is transmitted and one 8-bit word is received.
EODX and EODR are brought low.
FSX and FSR emit positive frame-sync pulses that are four shift clock cycles wide.
One 8-bit byte is transmitted and one 8-blt byte is received. ;
FSX and FSR are brought high.
.
EC5i5X and EODR are brought high.
Synchronous Operating Frequencies
The synchronous operating frequencies are determined by the following equations.
Switched capacitor filter (SCF) frequencies (see Figure 2-1):
Low- pass SCF clock frequency
(DjA and AjD channels)
master clock frequency
T(A) x 2
High-pass SCF clock frequency (AjD channel) = AjD conversion frequency
Conversion frequency (AjD and DjA channels)
Low pass SCF clock frequency
T(B)
master clock frequency
T(A) x 2 x T(B)
NOTE: T(A) , T(B), R(A), and R(B) are the contents of the TA, TB, RA, and RB registers,
respectively~
2.10 Asynchronous Operation
When the transmit and the receive sections are operated asynchronously, the low-pass and band-pass filter
clocks are independently generated from the master clock. The D/A and the AID conversion timing is also
determined independently.
D/A timing is set by the counters and registers described in synchronous operation, but the RA and RB
registers are substituted for the TA and TB registers to determine the AID channel sample rate and the AID
path switched-capacitor filter frequencies. Asynchronous operation Is selected by control register bit D5
being·zero.
2.10.1
One 16-BltWord (Word Mode)
The serial port interfaces directly with the serial ports of the TMS32020, TMS320C25, and TMS320C30 and
communicates with 16-bit word formats. The operation sequence is as follows:
1.
2.
3.
4.
FSXor FSR are brought low by the TLC32047 AIC.
One 16-bit word is transmitted or one 16-bit word is received.
FSX or FSR are brought high.
EODX or EODR emit low-going pulses one shift clock wide. EODX and EODR are valid in either
the word or byte mode only.
2.10.2 Two 8-Blt Bytes (Byte Mode)
The serial port interfaces directly with the serial port of the TMS320C17 and communicates in two 8-bit
bytes. The operating sequence is as follows:
1.
2.
7-80
FSX or FSR are brought low by the TLC32047 AIC.
One byte is transmitted or received.
3.
4.
5.
6.
7.
EODX or EODR are brought low.
FSX or FSR are brought high for four shift clock periods and then brought low.
The second byte is transmitted or received.
FSX or FSR are brought high.
EODX or EODR are brought high.
2.10.3 Asynchronous Operating Frequencies
The asynchronous operating frequencies are determined by the following equations.
Switched-capacitor filter frequencies (see Figure 2-1 ):
Low pass D/A SCF clock frequency =
master clock frequency
T(A) x 2
Low pass AID SCF clock frequency =
master clock frequency
R(A) x 2
High pass SCF clock frequency (AID channel) = AID conversion frequency
(2)
Conversion frequency:
01A conversion
frequency
Low f)ass
01A SCF
clock frequency
T(B)
. f
Low pass AID SCF clock frequency (for low pass receive filter)
AID conversion
requency =
R(B)
'.
(3)
NOTE: T(A), T(B), R(A), and R(B) are the contents of the TA, TB, RA, and RB registers, respectively.
2.11 Operation of TLC32047 With Internal Voltage Reference
The internal reference of the TLC32047 eliminates the need for an external voltage reference and provides
overall circuit cost reduction. The internal reference eases the design task and provides complete control
of the IC performance. The internal reference is brought out to REF. To keep the amount of noise on the
, reference signal to a mininium, an external capacitor can be connected between REF and ANLG GND.
2.12 Operation of TLC32047 With External Voltage Reference
REF can be driven from an external reference circuit. This external circuit must be capable of supplying
250 JJA and must be protected adequately from noise and crosstalk from the analog input.
2.13 Reset
A reset function is provided to initiate serial communications between the AIC and DSP and to allow fast,
cost-effective testing during manufacturing. The reset function initializes all AIC registers, including the
control register. After a negative-going pulse on RESET, the AIC is initialized. This initialization allows
normal serial port communications activity to occur between AIC and DSP (see AIC OX Data Word Format
section). After a reset, TA=TB=RA=RB=18 (or 12 hexadecimal), TA'=RA'=01 (hexadecimal), the AID
high-pass filter is inserted, the loop-back function is deleted, AUX IN+ and AUX IN- are disabled, the
transmit and receive sections are in synchronous operation, programmable gain is set to 1, the on-board
(sin x)/x correction filter is not selected, 010 OUT is set to 0, and 011 OUT is set to O.
2.14 Loopback
This feature allows the circuit to be tested remotely. In loopback, OUT+ and OUT-are internally connected
to IN+ and IN-. The DAC bits (015 to 02), which are transmitted to OX, can be compared with the ADC bits
(015 to 02) received from DR. The bits on DR equal the bits on OX. However, there is some difference in
these bits due to the ADC and DAC output offsets.
The loopback feature is implemented with digital signal processor control by transmitting a logic 1 for data
bit 03 in the OX secondary communication to the control register (see Table 2-3).
7-81
2.15 Communications Word Sequence
In the dual-word (telephone interface) mode, there are two data words that are presented to t.he DSP or J.1P
from DR. The first data word is the ADC conversion result occurring during the FSR time, and the second
is the serial data applied to DATA-DR during the FSD time. FSR is not asserted during secondary
communications and FSD is not asserted during primary communications.
Primary
Communications
1
4 Shift
Clocks
14
Secondary
Communications
1
.1
DX·14 Bits Digital 11
From DSP to DAC
Input for D/A
Conversion
Input for Register
Program
2s Complement Output
From ADC to the DSP
FSR
1
I
I
1
1
1
1
1
1
1
1
I
FSD
1
28 Complement Output
From ADC to the DSP
1
14---
16 bits
1
TLC32047
1
16 bits Digital From
DATA·DR to DR
DR
TLC32047
DX·14 Bits Digital XX
FromDSP
TLC32047
Dual·Word
(Telephone Interface)
Mode Only
I
TLC32047
Dual·Word
(Telephone Interface)
Mode Only
1
TLC32047
Dual·Word
(Telephone Interface)
Mode Only
Data From DATA·DR
totheDSP
1
1
1
1
I+-
~
16 bits ---.~
1
Figure 2-2. Primary and Secondary Communications Word Sequence
2.15.1
DR Word Bit Pattern
AlOMSB
1st bit sent
,J.
015
I 014 I 013 J 012 J 011 I 010 I
, AID LSB
,J.
09
I 08 I 07 I 06 I 05 L 04
J
03
I
02
I
01
I
DO
The data word is the 14·bit conversion result of the receive channel to the processor in 2s complement
format. With 16-bit processors, the data is 16 bits long with the two LSBs at zero. Using 8-bit processors,
the data word is transmitted in the same order as one 16-bit word, but as two bytes with the two LSBs of
the second byte set to zero.
7-82
2.15.2 Primary OX Word Bit Pattern
NOORO/AMSB
1st bit sent
NOorO/A LSB
1st bit sent of 2nd byte
J.
J.
J.
01
I DO
D1
DO
0
0
015 (MSB)-D2 ~ OAC Register.
TA+TA' ~ TX(A), RA+RA' ~ RX(A) (see Figure 2-1).
TB ~ TX(B), RB ~ AX(B) (see Figure 2-1).
The next O/A and ND conversion period is changed by the addition of TA' and RA' master clock cycles,
in which TA' and RA' can be positive, negative, or zero (refer to Table 2-4, AIC Responses to Improper
Conditions).
0
1
015 (MSB)-02 ~ OAC Register.
TA-TA' ~ TX(A), RA-RA' ~ RX(A) (see Figure 2-1).
TB ~ TX(B), RB ~ RX(B) (see Figure 2-1).
The next O/A and NO conversion period is changed by the subtraction ofTA' and RA' master clock cycles,
in which TA' and RA' can be positive, negative, or zero (refer to Table 2-4, AIC Responses to Improper
Conditions).
1
0
015 (MSB)-02 ~ OAC Register.
TA ~ TX(A), RA ~ RX(A) (see Figure 2-1).
TB ~ TX(B), RB ~ RX(B) (see Figure 2-1).
After a delay of four shift cycles, a secondary transmission follows to program the AIC to operate in the
desired configuration. In the telephone interface mode, data on DATA-DR is routed to DR (Serial Data
Output) during secondary transmission.
1
1
015
I 014 I 013 I 012 I 011 I 010 I
09
I
08
I
07
I
D6
I
05
I
04
I
03
I
02
I
Table 2-2. Primary OX Serial Communication Protocol
FUNCTIONS
D15 (MSB)-D2 ~ OAC Register.
TA ~ TX(A), RA ~ RX(A) (see Figure 2-1).
TB ~ TX(B), RB ~ RX(B) (see Figure 2-1).
NOTE: Setting the two least significant bits to 1 in the normal transmission of OAC information (primary communications)
to the AIC initiates secondary communications upon completion of the primary communications. When the
primary communication is complete, FSX remains high for four shift clock cycles and then goes low and initiates"
the secondary communication. The timing specifications for the primary and secondary communications are
identical. In this manner, the secondary communication, if initiated, is interleaved between successive primary
communications. This interleaving prevents the secondary communication from interfering with the primary
communications and DAC timing. This prevents the AIC from skipping a DAC output. FSR is not asserted during
secondary communications activity. However, in the dual-word (telephone interface) mode, FSO is asserted
during secondary communications but not during primary communications.
7-83
2.15.3 Secondary OX Word Bit Pattern
O/AMSB
1st bit sent
1st bit sent of 2nd byte
O/A LSB
,J.
,J.
,J.
015
I 014 I 013 I 012 I
011
I 010 I
09
I
08
L 07 I
06
I
05
I
04
I
03
I
02
I
01
I
00
Table 2-3. Secondary OX Serial Communication Protocol
D1
DO
013 (MSB)-09 -+ TA ,5 bits unsigned binary (see Figure 2-1).
06 (MSB)-02 -+ RA, 5 bits unsigned binary (see Figure 2-1).
015,014,08, and 07 are unassigned.
0
0
014 (sign bit)-09 -+ TN, 6 bits 2s complement (see Figure 2-1).
07 (sign bit)-02 -+ RA', 6 bits 2s complement (see Figure 2-1).
015 and 08 are unassigned.
0
.1
014 (MSB)-09 -+ TB, 6 bits unsigned binary (see Figure 2-1).
07 (MSB)-02 -+ RB, 6 bits unsigned binary (see Figure 2-1).
015 and 08 are unassigned.
1
0
02 ... 0/1 deletes/inserts the AlO high-pass filter.
03 - 0/1 deleteslinserts the loopback function.
04 = 0/1 disables/enables AUX IN+ and AUX IN-.
05 = 0/1 asynchronous/synchronous transmit and receive sections.
06 = 0/1 gain control bits (see Table 4-1).
07 ... 0/1 gain control bits (see Table 4-1).
09 = 0/1 delete/insert on-board second-order (sin x)/x correction filter
010 - 011 output to 0100UT [dual-word (telephone interface) mode]
011 - 0/1 output to 0110UT [dual-word (telephone interface) mode]
08,012-015 are unassigned.
1
1
FUNCTIONS
2.16 Reset Function
A reset function is provided to initiate serial communications between the AIC and OSP. The reset function
initializes all AIC registers, including the control register. After power has been applied to the AIC, a
negative-going pulse on RESET initializes the AIC registers to provide a 16-kHz AID and O/A conversion
rate for a 10.368-MHz master clock input signal. Also, the pass-bands of the AID and O/A filters are 300 Hz
to 7200 Hz and a Hz to 7200 Hz, respectively. Therefore, the filter bandwidths are 66% of those shown in
the filter transfer function specification section. The AIC, excepting the control register, is initialized as
follows (see AIC OX Data Word Format section):
REGISTER
INITIALIZED VALUE (HEX)
TA
12
TA'
01
TB
12
RA
12
RA'
01
RB
12
The control register bits are reset as follows (see Table 2-3):
011 = 0, 010 = 0, 09 = 1, 07
= 1, 06 = 1, 05 = 1, 04 = 0, 03 = 0, 02 = 1
This initialization allows normal serial port communications to occur between the AIC and the OSP. If the
transmit and receive sections are configured to operate synchronously and the user wishes to program
different conversion rates, only the TA, TA', and T8 register need to be programmed. 80th transmit and
receive timing are synchronously derived from these registers (see theTerminal Functions and OX Serial
Data Word Format sections).
Figure 2-3 shows a circuit that provides a reset on power-up when power is applied in the sequence given
in the Power-Up Sequence section. The circuit depends on the power supplies reaching their recommended
values a minimum of 800 ns before the capacitor charges to 0.8 V above OGTL GNO.
7-84
TLC32047
VCC+
5V
VCC-
-5V
Figure 2-3. Reset on Power-Up Circuit
2.17 Power-Up Sequence
To ensure proper operation of the AIC and as a safeguard against latch-up, it is recommended that Schottky
diodes with forward voltages less than or equal to 0.4 V be connected from Vcc- to ANLG GND and from
Vcc- to DGTL GND.ln the absence of such diodes, power is applied in the following sequence: ANLG GND
and DGTL GND, VCC-, then Vcc+ and Voo. Also, no input signal is applied until after power-up.
2.18 AIC Register Constraints
The following constraints are placed on the contents of the AIC registers:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
TA register must be ~ 4 in word mode (WORD/BYTE: High).
TA register must be ~ 5 in byte mode (WORD/BYTE: Low).
TA' register can be either positive, negative, or zero.
RA register must be ~ 4 in word mode (WORD/BYTE: High).
RA register must be ~ 5 in byte mode (WORD/BYTE: Low).
RA' register can be either positive. negative. or zero.
(TA register ± TA' register) must be > 1.
(RA register ± RA' register) must be> 1.
TB register must be ~ 15.
RS register must be ~ 1.5.
2.19 AIC Responses to Improper Conditions
The AIC has provisions for responding to improper conditions. These improper conditions and the response
of the AIC to these conditions are presented in Table 2-4. The general procedure for correcting any improper
operation is to apply a reset and reprogram the registers to the proper value.
7-85
Table 2-4. AIC Responses to Improper Conditions
IMPROPER CONDITION
TA register + TN register = 0 or 1
TA register - TA' register - 0 or 1
AIC RESPONSE
Reprogram TX(A) counter with TA register value
TA register + TA' register < 0
MODULO 64 arithmetic is used to ensure that a positivevalue is loaded
into TX(A) counter, i.e., TA register + TA' register + 40 hex is loaded into
TX(A) counter.
Reprogram RX(A) counter with RA register value
RA register + RA' register .. 0 or 1
RA register - RA' register .. 0 or 1
RA register + RA' register", 0 or 1
MODULO 64 arithmetic is used to ensure that a positive value is loaded
into RX(A) counter, i.e., RA register + RA' register + 40 hex is loaded
into RX(A) counter.
AIC is shut down. Reprogram TA or RA registers after a reset.
TA register .. 0 or 1
RA register .. 0 or 1
TA register < 4 in word mode
TA register < 5 in byte mode
RA register < 4 in word mode
RA register < 5 in byte mode
TB register < 15
RB register < 15
AIC and DSP cannot communicate
The AIC serial port no longer operates. Reprogram TA or RA registers
after a reset.
ADC no longer operates
DAC no longer operates
Hold last DAC output
2.20 Operation With Conversion Times Too Close Together
If the difference between two successive D/A conversion frame syncs Is less than 1/25 kHz, the AIC
operates improperly. In this situation, the second DIA conversion frame sync .occurs too quickly, and there
is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B
registers are improperly programmed or if the A + A' register result is too small. When incrementally
adjusting the conversion period via the A + A' register options, the designer should not violate this
requirement. See Figure2-4.
Frame Sync
(FSXor FSR)
l
t1
,....--~'/'I'"j- - - ; t2
~-----~
1
I
~--~
j.-- Ongoing Conversion --+I.
t2 - t1
S;
1/25 kHz
Figure 2-4. Conversion Times Too Close Together
2.21 More Than One Receive Frame Sync Occurring Between Two Transmit
Frame Syncs - Asynchronous Operation
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the AIC
during an FSX frame sync. The ongoing conversion period is then adjusted; however, either receive
conversion period A or conversion period B may be adjusted. For both transmit and receive conversion
periods, the incremental conversion period adjustment is performed near the end of the conversion period.
If there is sufficient time between t1 and t2, the receive conversion period adjustment is performed during
receive conversion period A. Otherwise, the adjustment is performed during receive conversion period B.
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another Command must be issued during
.
a subsequent FSX frame (see Figure 2-5).
7-86
u
U
14~---- Transmit Conversion Period ---~~
.....--"'1
~
IJ'I
I
Receive Conversion
Period B
Receive Conversion
Period A
Figure 2-5. More Than One Receive Frame Sync Between Two Transmit Frame Syncs
2.22 More Than One Transmit Frame Sync Occurring Between Two Receive
Frame Syncs - Asynchronous Operation
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol must be followed. For both transmit and receive conversion periods, the incremental conversion
period adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the AIC during an FSX frame sync. The ongoing transmit
conversion period is then adjusted. However, three possibilities exist for the receive conversion period
adjustment as shown in Figure 2-6. When the adjustment command is issued during transmit conversion
period A, receive conversion period A is adjusted if there is sufficient time between t1 and t2' If there is not
sufficient time between t1 and t2, receive conversion period B is adjusted. The third option is that the receive
portion of an adjustment command can be ignored if the adjustment command is sent during a receive
conversion period, which is adjusted due to a prior adjustment command. For example, if adjustment
commands are issued during transmit conversion periods A, B, and C, the first two commands may cause
receive conversion periods A and B to be adjusted, while thethird receive adjustment command is ignored.
The third adjustment command is ignored since it was issued during receive conversion period B, which
already is adjusted via the transmit conversion period B adjustment command.
1
1
1
I
Conversion I
Period B
14- Transmit ____ Transmit ___ Transmit
I
Conversion
Period A
t2
FSFiU
I.--- Receive Conversion Period A
Conversion
Period C
U
~I..
-+11
.
LS
Receive Conversion Period B
----.I
Figure 2-6. More Than One Transmit Frame Sync Between Two Receive Frame Syncs
2.23 More than One Set of Primary and Secondary DX Serial Communications
Occurring Between Two ,Receive Frame Syncs (See DX Serial Data Word
Format section) --Asynchronous Operation
The TA, TA', TB, and control register information that is transmitted in the secondary communication is
accepted and applied during the ongoing transmit conversion period. If there is sufficient time between t1
and t2' the TA, RA/, and RB register information, sent during transmit conversion period A, is applied to
receive conversion period A. Otherwise, this information is applied during receive conversion period B. If
RA, RA/, and RB register information has been received and is being applied during an ongoing conversion
period, any subsequent RA, RA/, or RB information received during this receive conversion period is
disregarded. See Figure 2-7.
7-87
n
PrimarySecorJdaryt1
Fsxl. '.
1
Primary
r--I---:';1
Transmit
1
n
Secondary
'r--I---:.;,
Transmit
14-1.-- Conversion --"'~oI4-l.-- Conversion
Preload A
+--
Receive
Conversion Period A.
1
~!-I
Preload B
II
....
~j'IIf------
.·n
Primary
.Secondary
---'L
r--I
Transmit
Conversion
Preload C
1
~
!-----oIlI
Receive
I
Conversion - - - - - - - ,..
~
Period B
Figure 2-7. More Than One Set of Primary and Secondary OX Serial Communications
Between Two Receive Frame Syncs
2.24 System Frequency Response Correction
The (sin x)/x correction for the DAC zero-order sample-and-hold output can be provided by an on-board
second-order (sin x)/x correction filter (see Functional Block Diagram). This (sin x)/x correction filter can be
inserted into or omitted from the signal path by digital-signal-processor control (data bit 09 in the OX
secondary communications). When inserted, the (sin x)/x correction filter precedes the switched-capacitor
low-pass filter. When the TB register (see Figure 2-1) equals 15, the correction results of Figures 5-8, 5-9,
and 5-10 can be obtained.
The (sin x)/x correction can also be accomplished by disabling the on-board second-order correction filter
and performing the (sin x)/x correction in digital signal processor software. The system frequency response
can be corrected via DSP software to ± 0.1· dB accuracy to a band edge of 3000 Hz for all sampling rates.
This correction is accomplished with a first-order digital correction filter, that requires seven TMS320
instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of 1.1 %
and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (sin x)/x Correction Section for more
details).
2.25 (sin x)/x Correction
If the designer does not wish to use the on-board second-order (sin x)/x correction filter, correction can be
accomplished in digital signal processor (DSP) software. (sin x)/x correction can be accomplished easily
and efficiently in digital signal processor software. Excellent correction accuracy can be achieved to a band
edge of 3000 Hz by using a first-order digital correction filter. The results shown below are typical of the
numerical correction accuracy that can be achieved for sample rates of interest. The filter requires seven
instruction cycles per sample on the TMS320 DSP. With a 200-ns instruction cycle, nine instructions per
sample represents an overhead factor of 1.4% and 1.7% for sampling rates of 8000 Hz and 9600 Hz,
respectively. This correction adds a slight amount of group delay at the upper edge of the 300-Hz to 3000-Hz
band.
.
2.20 (sin x)/x RolI·Off for a Zero-Order Hold Function
The (sin x)/x roll-off error for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz
for the various sampling rates is shown in Table 2-5 (see Figure 5-10).
7-88
Table 2-6. (sin x)/x Roll-Off Error
sin 1t flf.
1t flfs
f= 3000 Hz
=
Error 20 log
fs (Hz)
(dB)
7200
8000
9600
14400
16000
19200
25000
-2.64
-2.11
-1.44
-0.63
-0.50
-0.35
-0.21
The actual Ale (sin x)/x roll-off is slightly less than the figures above because the Ale has less than 100%
duty cycle hold interval.
2.27 Correction Filter
To externally compensate for the (sin x)/x roll-off of the Ale, a first-order correction filter can be implemented
as shown in Figure 2-S.
Y(I + 1)
p1
Figure 2-8. First-Order Correction Filter
The difference equation for this correction filter is:
Y(i+ 1) = p2. (1-p1) .u(i+1) + p1 . YCi)
(4)
where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
1H f 12 =
(p2)2. (1-p1)2
()
1-2 . p1 . cos (21t flfs) + (p1)2
(5)
2.28 Correction Results
Table 2-6 shows the optimum p values and the corresponding correction results for SOOO-Hz and 9600-Hz
sampling rates (see Figures 5-S, 5-9, and 5-10).
7-89
Table 2-6. (sin x)/x Correction Table for f8 = 8000 Hz and f8 = 9800 Hz
f (Hz)
300
600
900
1200
1500
1800
2100
2400
ROLL-OFF ERROR (dB)
f8=8000 Hz
pi = -0.14813
p2 =0.9888
-0.099
-0.089
-0.054
-0.002
0.041
0.079
0.100
2700
0.091
-0.043
3000
-0.102
ROLL-OFF ERROR (dB)
f8= 9600 Hz
pi =-0.1307
p2= 0.9951
-0.043
-0.043
0
0
0
0.043
0.043
0.043
0
-0.043
2.29 TMS320 Software Requirements
The digital correction filter equation can be written in state variable form as follows:
Y(i+1) = Y(i) xk1 + U(i+1) xk2
where
k1 = p1
k2 = (1 - p1)p2
y(i) is the filter state
u(i+1)
The coefficients k1 and k2 must be represented as 16-bit integers. The SACH instruction (with the proper
shift) yields the correct result. With the assumption that the TMS320 processor page pointer and memory
configuration are properly initialized, the equation can be executed In seven Instructions or seven cycles
with the following program:
ZAC
LT K2
MPY IT
LTA Kl
MPY Y
APAC
SACH (dma) , (shift)
7-90
3
Specifications
3.1
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)t
Supply voltage range, Vcc+ (see Note 1) .......................... -0.3 Vto 15 V
Supply voltage range, Vcc- (see Note 1) .......................... -0.3 V to 15 V
Supply voltage range, Voo ....................................... -0.3 V to 15 V
Output voltage range, Vo ........................................ -0.3 V to 15 V
Input voltage range, VI .............................•............. -0.3 V to 15 V
Digital ground voltage range ...................................... -0.3 V to 15 V
Operating free-air temperature range: TLC32047C ................... O°C to 70°C
TLC320471 .................. -40°C to 85°C
Storage temperature range ...................................... -40°C to 125°C
Case temperature for 10 seconds: FN package ............................ 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress'ratings only and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for
extended periods may affect device reliability.
NOTE 1: Voltage values for maximum ratings are with respect to VCC-
7-91
3.2
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
V
Supply voltage, VCC+ (see Note 2)
4.75
5
5.25
Supply voltage, VCC- (see Note 2)
-4.75
-5
-5.25
V
4.75
5
5.25
V
Digital supply voltage, VDD (see Note 2)
Digital ground voltage with respect to ANLG GND, DGTL GND
0
V
2
4
V
High-level input voltage, VIH
2
0
VDD
0.8
V
Low-level input voltage, VIL (see Note 3)
Reference input voltage, VrefCextl (see Note 2)
Load resistance at OUT+ and/or OUT-, RL
300
Load capacitance at OUT+ and/or OUT-, CL
100
MSTR CLK frequency (see Note 4)
5 10.368
Analog input amplifier common mode input voltage (see Note 5)
±1.5
ND or D/A conversion rate
25
.
ITLC32047C
Operating free-air temperature range, TAl
TLC320471
V
0
0
70
-40
85
pF
MHz
V
kHz
°C
NOTES: 2. Voltages at analog inputs and outputs, REF, VCC+, and VCC- are with respect to ANLG GND. Voltages at
digital inputs and outputs and VDD are with respect to DGTL GND.
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used
in this data manual for logic voltage levels only.
4. The band-pass switched-capacitor filter (SCF) specifications apply only when the lOW-pass section SCF
clock is 432 kHz and the high-pass section SCF clock is 24 kHz. If the low-pass SCF clock is shifted from
432 kHz, the low-pass roll-off frequency shifts by the ratio of the lOW-pass SCF clock to 432 kHz. If the
high-pass SCF clock is shifted from 24 kHz, the high-pass roll-off frequency shifts by the ratio of the
high-pass SCF clock to 24 kHz. Similarly, the low-pass switched-capacitor filter (SCF) specifications apply
only when the SCF clock is 432 kHz. If the SCF clock is shifted from 432 kHz, the low-pass roll-off frequency
shifts by the ratio of the SCF clock to 432 kHz.
5. This range applies when (IN+ -IN-) or (AUX IN+ - AUX IN-) equals ± 6 V.
3.3
Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, VCC+ = 5 V, VCC- = -5 V, VDD = 5 V (Unless
Otherwise Noted)
3.3.1 Total Device, MSTR ClK Frequency =5.184 MHz, Outputs Not loaded
IDD
Vref
PARAMETER
High-level output voHage
Low-level output voltage
TLC32047C
Supply current from
VCC+
TLC320471
TLC32047C
Supply current from
VCCTLC320471
Supply current from VDD
Intemal reference output voltage
aVref
Temperature coefficient of
internal reference voltage
260
ppmfOC
ro
Output resistance at REF
100
kO
VOH
VOL
ICC+
ICC-
t All typical values are at TA = 25°C.
TEST CONDITIONS
VDD=4.75V, IOH - -300!lA
VDD=4.75V, IOL-2mA
MIN
2.4
TYPt
MAX
0.4
35
40
-35
-40
7
3
3.3
UNIT
V
V
mA
mA
mA
V
3.3.2
Power Supply Rejection and Crosstalk Attenuation
PARAMETER
VCC+ or VCC- supply voltage
rejection ratio, receive channel
VCC+ or VCC- supply voltage
rejection ratio, transmit channel
(Single-ended)
f .. Ot030 kHz
f .. 30 kHz to 50 kHz
f=Ot030kHz
f = 30 kHz to 50 kHz
TEST CONDITIONS
MIN
Idle channel, supply
signal at 200 mV p-p
measured at DR (ADC
output)
TYPt
MAX
UNIT
30
dB
45
Idle channel, supply
signal at 200 mV p-p
measured at OUT+
30
dB
45
Crosstalk attenuation, transmit-to-receive
(Single-ended)
80
dB
t All typical values are at TA =25°C.
3.3.3
Serial Port
PARAMETER
TEST CONDITIONS
High-level output voltage
IOH .. -300 J.IA
VOL
Low-level output voltage
IOL=2mA
II
Input current
II
Input current, DATA-DR/CONTROL
Ci
Input capacitance
VOH
MIN
TEST CONDITIONS
MIN
AID converter offset error (filters in)
Common-mode rejection ratio at IN+, IN-, or
AUX IN+, AUX IN-
See Note 6
Input resistance at IN+, IN- or AUX IN+,
AUX IN-, REF
t All typical values are at TA .. 25°C.
NOTE 6: The test condition is a O-dBm, 1-kHz input signal with a 24-kHz conversion rate.
Ij
3.3.5
V
0.4
V
±10
J.IA
J.IA
15
pF
15
pF
TYPt
MAX
10
70
UNIT
mV
55
dB
100
kn
Transmit Filter Output
PARAMETER
VOO
UNIT
Receive Amplifier Input
PARAMETER
CMRR
MAX
±100
Output capacitance
Co
t All typical values are at TA = 25°C.
3.3.4
TYPt
2.4
TEST CONDITIONS
MIN
Output offset voltage at OUT+ or OUT(single-ended relative to ANlG GND)
Maximum peak output voltage swing across
RL at OUT+ or OUT- (single-ended)
RL~300n.
Offset voltage .. 0
TYPt
MAX
15
80
UNIT
mV
±3
V
±6
V
VOM
Maximum peak output voltage swing between
OUT+ and OUT- (differential output)
t All typical values are at TA =25°C.
RL~600n.
7-93
3.3.6
Receive and Transmit Channel System Distortion, SCF Clock
Frequency 432 kHz (see Note 7)
=
PARAMETER
Attenuation of second harmonic of
NO input signal
TEST CONDITIONS
single-ended
differential
single-ended
Attenuation of third and higher
harmonics of NO input signal
MIN
VI
=-0.1 dB to-24 dB
Attenuation of third and higher
harmonics of O/A input signal
single-ended
differential
70
65
57
single.ended
differential
MAX
70
62
differential
Attenuation of second harmonic of
O/A input signal
TVPt
65
70
62
VI .. -OdBto-24dB
70
65
57
65
UNIT
dB
dB
dB
dB
t All typical values are at TA =25°C.
3.3.7
Receive Channel Slgnal-to-Dlstortlon Ratio (see Note 7)
PARAMETER
NO channel signal-todistortion ratio
TEST CONDITIONS
Av = 1 VM
MIN MAX
Av = 2 VM
MIN MAX
§
Av =4 V/V*
MIN MAX
§
VI =-6dBto-0.1 dB
56
VI ",-12 dBto-6dB
56
56
VI" -18 dB to-12 dB
53
66
56
VI"' -24 dB to-18 dB
47
53
47
56
41
47
35
§
VI .. -30 dB to -24 dB
41
VI .. -36 dB to -30 dB
35
VI .. -42 dB to -36 dB
29
VI - -:48 dB to -42 dB
VI .. -54 dB to -48 dB
23
29
·41
35
17
23
29
\
UNIT
53
dB
:j: Av is the programmable gain of the input amplifier.
§ Measurements under these conditions are unreliable due to overrange and signal clipping.
NOTE 7: The test condition is a 1-kHz input Signal with a 24-kHz conversion rate. The load impedance for the OAC is
600 o. Input and output voltages are referred to Vref.
7-94
3.3.8
Transmit Channel Slgnal-to-Dlstortlon Ratio (see Note 7)
PARAMETER
01A channel signal-to-distortion ratio
TEST CONDITIONS
MIN
V,,, -6 dB to -0.1 dB
58
V,--12dBto...;.6dB
58
V,--18dBto-12dB
56
V,,,, -24 dB to -18 dB
50
V, .. -30 dB to -24 dB
44
V, .. -36 dB to -30 dB
38
V, .. -42 dB to -36 dB
32
V, .. -48 dB to -42 dB
26
V, .. -54 dB to -48 dB
20
MAX
UNIT
dB
NOTE 7: The test condition is a 1-kHz input signal with a 24-kHz conversion rate. The load impedance for the DAC is
600 n Input and output voltages are referred to Vref.
3.3.9
Receive and Transmit Gain and Dynamic Range (see Note 8)
PARAMETER
TEST CONDITIONS
MIN
TYpf
MAX
UNIT
Transmit gain tracking error
Vo .. -48 dB to 0 dB Signal range
±0.05 ±0.25
dB
Receive gain tracking error
V, - -48 dB to 0 dB signal range
±0.05 ±0.25
dB
NOTE 8: Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to Vref).
3.3.10 Receive Channel Band-Pass Filter Transfer Function, SCF fclock
Input (IN+ -IN-) Is a ±3-V Sine Wave* (see Note 9)
PARAMETER
Filter gain
TEST
CONDITION
FREQUENCY
=432 kHz,
ADJUSTMENT
MIN
TYPt
MAX
fS150Hz
K1 xOdB
-33
-29
-25
f ... 300Hz
K1 x-0.26dB
-4
-2
-1
f .. 450 Hz to 9300 Hz
K1 xOdB
-0.25
0
0.25
f =9300 Hz to 9900 Hz
K1 xOdB
-0.3
0
0.3
K1 xOdB
-0.5
0
0.5
-0.5
Input Signal
f .. 9900 Hz to 10950 Hz
reference is 0 dB
f .. 11.4kHz
K1 x2.3dB
-2
f =12 kHz
K1 x2.7dB
-16
f~
K1 x 3.2 dB
-40
K1 xOdB
-60
13.2 kHz
f~15kHz
UNIT
dB
-14
t All typical values are at TA .. 25°C.
:j: The MIN, TYP, and MAX specifications are given for a 432-kHz SCF clock frequency. A slight error in the 432-kHz SCF
can result from inaccuracies in the MSTR ClK frequency, resulting from crystal frequency tolerances. If this frequency
error is less than 0.25%, the ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications, where
K1 .. 100 x [(SCF frequency - 432 kHz)/432 kHz]. For errors greater than 025%, see Note 9.
NOTE 9: The filter gain outside of the pass band is measured with respect to the gain at 1 kHz. The filter gain within the
pass band is measured with respect to the average gain within the pass band. The pass bands are 450 Hz
to 10.95 kHz and 0 to 10.95 kHz for the band-pass and low-Pass filters, respectively. For switched-capacitor
filter clocks at frequencies other than 432 kHz, the filter response is shifted by the ratio of switched-capacitor
filter clock frequency to 432 kHz.
7~5
3.3.11
Receive and/ Transmit Channel Low-Pass Filter Transfer Function,
SCF fclock ~ 432 kHz (see Note 9)
PARAMETER
Filter gain
TEST
CONDITION
Input signal
reference is 0 dB
FREQUENCY
RANGE
ADJUSTMENT
ADDEND*
MIN
TYpt
MAX
0.25
f .. OHz to 9300 Hz
K1 xOdB
-0.25
0
f = 9300 Hz to 9900 Hz
K1 xOdB
-0.3
0
0.3
f • 9900 Hz to 10950 Hz
K1 xOdB
-0.5
0
0.5
f-11.4kHz
K1 x2.3dB
-2
-0.5
f .. 12kHz
K1 x2.7dB
-16
-14
f~
K1 x3.2dB
-40
K1 xOdB
-60
13.2 kHz
f~15kHz
-5
UNIT
dB
t All typical values are at TA = 25°C.
.
:j: The MIN, TYP, and MAX specifications are given for a 432-kHz SCF clock frequency. A slight error in the 432-kHz SCF
may result from inaccuracies in the MSTR ClK frequency, resulting from crystal frequency tolerances. If this frequency
error is less than 0.25%, the ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications, where
K1 .. 100 x [(SCF frequency - 432 kHz)/432 kHz]. For errors greater than 0.25%, see Note 9.
NOTE 9: The filter gain outside of the pass band is measuJed with respect to the gain at 1 kHz. The filter gain within the
pass band is measured with respect to the average gain within the pass band. The pass bands are 450 Hz
to 10.95 kHz and 0 to 10.95 kHz for the band-pass and lOW-pass filters, respectively. For switched-capacitor
filter clocks at frequencies other than 432 kHz, the filter response is shifted by the ratio of switched-capacitor
filter clock frequency to 432 kHz.
3.4
Operating Characteristics Over Recommended Operating Free-Air
Temperature Range, VCC+ 5 V, VCC- -5 V, Voo 5 V
3.4.1
=
=
Receive and Transmit Noise (Measurement Includes Low-Pass and Band-Pass
Switched-Capacitor Filters)
PARAMETER
Transmit
noise
=
TYPt
MAX
broadband with (sin x)/x
280
5eO
broadband without (sin x)/x
250
450
250
400
oto 12 kHz with (sin x)/x
oto 12 kHz without (sin x)/x
Receive noise (see Note 10)
TEST CONDITIONS
DX = input = 00000000000000,
constant input code
Inputs grounded, gain = 1
MIN
240
400
300
500
18
t All typical values are at TA .. 25°C.
NOTE 10: The noise is computed by statistically evaluating the digital output of the AID converter.
7-96
UNIT
IJ.Vrms
IJ.Vrms
dBrncO
3.5
Timing Requirements
3.5.1
Serial Port Recommended Input Signals
MIN
PARAMETER
MAX
UNIT
ns
tcCMCLKI
Master clock cycle time
95
tr(MCLK)
Master clock rise time
10
ns
tf(MCLK)
Master clock fall time
10
ns
Master clock duty cycle
25%
RESET pulse duration (see Note 11)
OX setup time before SCLKJ.
tsuCDX)
75%
800
ns
20
ns
OX hold time after SCLKJ.
ns
th(DX)
tc(SCLKl/4
NOTE 11: RESET pulse duration is the amount oftime thatthe reset pin is held below 0.8 V after the power supplies have
reached their recommended values.
3.5.2
Serial Port - AIC Output Signals, CL
For All Other Outputs
=30 pF for SHIFT CLK Output, CL =15 pF
PARAMETER
MIN
TYPt
MAX
UNIT
tc(SCLK)
Shift clock (SCLK) cycle time
tf(SCLK)
Shift clock (SCLK) fall time
3
8
ns
tr(SCLK)
Shift clock (SCLK) rise time
3
8
55
ns
Shift clock (SCLK) duty cycle
ns
380
45
ldCCH-FU
Delay from SCLKi to FSRlFSXlFSDJ.
30
ldCCH-FHI
Delay from SCLKito FSRlFSXlFSDi
35
%
ns
90
ns
ldCCH-DRI
DR valid after SCLKi
90
ns
ld(CH-EL)
Delay from SCLKi to EODXlEODRJ. ih word mode
90
ns
ld(CH-EH)
Delay from SCLKi to EODXlEODRi in word mode
90
ns
tf(EODX}
EODX fall time
2
ns
tf(EODR)
EODR fall time
2
8
8
ns
ldCCH-ELI
Delay from SCLKi to EODXlEODRJ. in byte mode
90
ns
ldCCH-EHI
Delay from SCLKi to EODXlEODRi in byte mode
90
ns
ldCMH-SLl
Delay from MSTR CLKi to SCLKJ.
65
170
ns
ld(MH-SH) Delay from MSTR CLKi to SCLKi
t Typical values are at TA _ 25°C.
65
170
ns
7-97
7-98
4
Parameter Measurement Information
Alb
IN+
or
AUX IN+
R
INor
AUXIN-
R
Rfb
Rfb=RforD8= 1andD7= 1
D8=OandD7= 0
Rfb = 2R for D8 = 1 and Dt'= 0
Rfb=4RforD8=O,andD7= 1
Figure 4-1. IN+ and IN- Gain Control Circuitry
Table 4-1. Gain Control Table (Analog Input Signal Required for
Full-Scale Bipolar AID Conversion Twos Complement)t
INPUT
CONFIGURATIONS
Oifferential configuration
Analog Input - IN+ -IN• AUX IN+ - AUX IN-
Single-ended configuration
Analog Input • IN+ - ANLG GNO
• AUX IN+ - ANLG GNO
'CONTROL REGISTER BITS
ANALOG
INPU"rt:§
AID CONVERSION
RESULT
D8
D7
1
0
1
0
VIO-±6V
±full scale
1
0
VIO-±3V
±full scale
0
1
VIO-±1.5V
±full scale
1
0
1
0
VI-±3V
±haHscale
1
0
VI-±3V
±full scale
0
1
VI-±1.5V
±fullscale
*
tvcc+-S v. VCC---SV. VOO-S V
VIO - Oifferentiallnput Voltage. VI_ Input voltage referenced to ground with IN-or AUX IN- connected to ground.
§ In this example. Vref is assumed to be 3 V.ln order to minimize distortion. it is recommended thatthe analog input not
exceed 0.1 dB below fuH scale.
7-99
SHIFT
CLK
8V
FSX, FSR,
FSD
2\l
I
I I
I I
I -+l
IS
r- .let (CM-DR)
DR----~D~16~--~~--D-1----~-----------
tau (DX) -+J k_
____~~~~~~~~KJU!)(~~CJ~)(JU:x:J~>_~D~O~n~'t~Ca=N!--00
I
D15
~__D_1__~D_O~I~__~_______
DATA-DR
~
I
Figure 4-2. Dual-Word (Telephone Interface) Mode Timing
SHIFT
CLK
2\l
. I
I I
I I
IS
I -+l
let (CH-DR)
DR _____D_15_____~--D-1----~--~-------BV
r-
tau (DX) -+J ~
.
DX--~--(]~)C~~~~(]~(]~)C][J(~CX:JOO!:>_~Don~'t~Ca~N~--
I
I
let (CH-EL) .... j4let (CH-EH)
EODX,EODR*----------------------------·"-------------8~V~2V
-.1:--
Figure 4-3. Word Timing
t The time between falling edges of FSR is the NO conversion period and the time between falling edges of FSX is the
O/A conversion period.
:\: In the word format, EOOX and EOOR go low to signal the end of a 16-bit data word to the proCessor. The word-cycle
is 20 shift-clocks wide, giving a four-clock period setup time between data words.
7-100
EODX
Figure 4-4. Byte-Mode Timing
tThe time between falling edges of FSR is the NO conversion period, and the time between tallling edges of"FSX is the O/A conversion period.
tin the byte mode, when EOOXor'EOOR is high, the first byte is transmitted or received, and when these signals are low, the second byte is
transmitted or received. Each byte-cycle is 12 shift-clocks long, allowing for a four-shift-clock setup time between byte transmissions.
!
~
MSTRCLK
I
I
.~
SHIFTCLK
--
~
.
I
--+I
~- lei (MH-8H)
14- tel (MH-SL)
'iw;..l_ _ __
/
Figure 4-6. Shift-Clock Timing
4.1
TMS32047 - Processor Interface
SN74lS74
.--
'"
-
TMS32010
G1
A
B
Y1
YO
-
C
SN74l$138
Do-D15
\.,
WE
ClK
OUT
INT
if
SO ClK<
G1
D8-D15
\.
A·H
-
SN74lS299
S1
QH
G2
so
Cl~
G1
Do-D7
\.
r-
DX
-
K - t::..
SR
'\
Dn
Do-D15
L:3-
G2
DEN
AOIPAO
A1/PA1
A2IPA2
SN74lS299
S1
QH
FSX
C2
A·H
SR
,
-
S~~
C1<
1D
-
TlC32047
1-+ DR
=>=n
1 -
Figure 4-8. TMS320101TMS320C15-TLC32047 Interface Circuit
7-102
SHIFT
ClK
MSTR
ClK
EODX
ClKOUT
.-J
L
I
~~I~I----------------
DEN
I I
SO,G1
00-015
-----~(
)~-----:------
Valid
(a) IN INSTRUCTION TIMING
ClKOUT
WE
.-J
L
I
--~I~I----------------
I I
SN74lS138 Y1
SN74lS299 ClK
I
00-015
-------c(
II
Valid
)>----------
(b) OUT INSTRUCTION TIMING
Figure 4-7. TMS32010ITMS320C15-TLC32047 Interface Timing
7-103
7-104
5
Typical Characteristics
D/A AND AID LOW·PASS FILTER
RESPONSE SIMULATION
0.4
I
TA=25°C
Input = ± 3 V Sine Wave
0.2
lEI
,
1:1
I
oS
i!c
1:1
c
1\1
0
-
1\
V 'vV\ ~\
-0.2
lEI
i
-0.4
-0.6
o
3
6
9
12
Normalized Frequency
15
Figure 5-1
D/A AND AID LOW·PASS FILTER
RESPONSE SIMULATION
0
See Figure 2-1
for Pass Band
Detail
-10
~
T~=250C
I
I
_ Input = ± 3 V Sine Wave
-20
lEI
-30
1:1
I
G)
1:1
i!c
aI
-40
-50
1\1
:::E
-60
I--
-70
(
-so
-90
o
3
6
9
12
15
\ I
18
II
21
Ii""'"
24
27
30
Figure 5-2
NOTE : Absolute Frequency (kHz)
Normalized Frequency x SCF f clock (kHz)
432
7-105
D/A AND AID LOW-PASS GROUP DELAY
0.6
=
_I
I
TA 25°C
Input ±3 V Sine Wave
=
0.5
~
I
0.4
f
Q
a.
:::t
e
CJ
0.3
./
0.2
o
o
3
6
I
J
~
"12
9
15
, - Frequency - kHz
FlgureS-3
AID BAND-PASS RESPONSE
0.4
I
I
=
I
High-Pass SCF 'clock 24 kHz
TA 25°C
Input ±3 V Sine Wave
=
0.2
=
III
'a
I
CD
'a
j
/
0
t
:.
'a
c
II
....
"v ~ I"
V
-0.2
III
J
-0.4
-0.6
o
3
6
9
12
15
, - Frequency - kHz
FlgureS-4
Normalized Frequency x SCF fclock (kHz)
NOTE: Absolute Frequency (kHz) = ------------~~----~~~--432
7-106
AID BAND-PASS FILTER RESPONSE SIMULATION
0
\
-10
Hlgh·Pass SCF
fclock = 24 kH.z
TA=25°C
Input = ± 3 V Sine Wave
-20
III
-
-30
'a
I
CD
'a
-40
:::I
:t:
C
I
-SO
-60
-70
(
-SO
-90
o
3
6
\ I
~I
u
9 12 15 18 21
f - Frequency - kHz
-
".
24
27
30
FigureS-6
AID BAND-PASS FILTER GROUP DELAY
1.0
I
I
I
I
I
I
I
Hlgh·Pass SCF fclock = 24 kHz
TA = 25°C
Input = ±3 V Sine Wave
0.9
0.8
~
I
>1\1
11
Q
ICI.
:::I
e
0.6
It
0.5
0.4
CJ
0.2
0.1
o
o
-"
'""
,
"
:/ \
'. '
1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
f - Frequency - kHz
FigureS-6
NOTE: Absolute Frequency (kHz) =
Normalized Frequency x SCF 'clock (kHz)
--------------4~3~2------~~----
7-107
AID CHANNEL HlGH-PASS FILTER
20
TA = 25°C
Input =± 3 V SIne Wave
10
,""
0
ED
'til
-10
I
-8::::II
=:
c
a
III
:I
-20
r
I
-30
-40
-50
-60
o
150 300 450 600 750 9001050120013501500
Normalized Frequency
Figure 5-7
D/A (sin x)/x CORRECTION FILTER RESPONSE
4
,-...,
~
2
/
ED
'til
I
/'
0 r--
V
v 1\,
~
\
CD
'til
:Ec
i
:I
\
-2
-4
TA
\\
\
=25°C
=± 3 V SIne Wave
Input
-6
o
I
I
I
3
6
9
I
I
12 15 18 21
f - Frequency - kHz
24
27
30
Figure5~
NOTE: Absolute Frequency (kHz)
7-108
Normalized Frequency x SCF f clock (kHz)
432
. D/A (sin x)/x CORRECTION FILTER RESPONSE
325
=
TA 25°C
Input ± 3 V Sine Wave
=
260
V\
III
::I.
I
i:
195
/ \
'1ii
Q
a.
::I
e
e"
130
65
/
l../
-
o
o
3
6
1\
"
9
12 15 18 21
f - Frequency - kHz
24
27
30
Figure 5-9
D/A (sin x)/x CORRECTION ERROR
2
TA = 25°C
Inp.ut =± 3 V Sine Wave
1.6
1.2
V (sin x) Ix Correction
0.8
V
a:I
"C
I
CD
"C
::I
c
==aI
III
::&
0.4
.-/
,../
Error
--- .........
0
...........
-0.4
~
"
-0.8
-1.2
-1.6
-2
/
/
~
'\
~
'"
I\..
28.8 kHz (sin x) Ix
Distortion
_
'\.
\
o
1.5
3
4.5 6 7.5 9 10.5 12 13.5 15
f - Frequency - kHz
Figure 5-10
NOTE : Absolute Frequency (kHz)
Normalized Frequency x SCF 'clock (kHz)
432
7-109
AID BAND-PASS GROUP DELAY
760
•
I
720 I--
::I.
I
680 I"-
8=-CL
640
2
600
I.,
560
-D
c
520
:::I
I
I
I
I
I
r-
Cl
I
~
\,
460
440
400
J
If
CL
Q
~.
/
CJ
81
J
Low-pass SCF fclock = 144 kHz
High-pass SCF fclock = 8 kHz
TA=25°C
Input = ± 3 V Sin. Wave
o
0.4
"
0.8
-
./
V
/
~
1.2
1.6 2.0 2.4
f - Frequency - Hz
2.8
3.2 3.6
Figure 5-11
D/A LOW-PASS GROUP DELAY
560
.1
•
::I.
I
'"
1
1
1
I.
1
520 I-- Low-pass SCF fclock = 144 kHz
TA=25°C
I-- Input = ± 3 V Sin. wave
480
1\1
15
Q
440
CL
e
CJ
I
-D
c
1\1
400
/
360
I(
)
320
ID
Q
Cl
280
240
200
V
o
0.4
0.8
V
V
1.2 1.6 2.0 2.4
f - Frequency - Hz
Figure 5-12
7-110
/
V
2.8
3.2 3.6
AID SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL
100
90
III
'a
I
0
;:;
~
80
_ 1-kHz Input Signal
16-kHz Conversion Rate
TA=25"C
c
60
t!
50
Q
40
..I.
III
C
30
0
j
,
~
Gain = 1
70
.,.,--
Gain 1= 4
,V
.. / '
V
20
10
,
o
-50
-40
-30
-20
-10
0
10
Input Signal Relative to Vref - dB
Figure 5-13
AID GAIN TRACKING
(GAIN RELATIVE TO GAIN AT O-dB INPUT SIGNAL)
0.5
1-kHz Input Signal
0.4 I- 16-kHz Conversion Rate
0.3
III
'a
I
aI
TA=25°C
0.2
0.1
c
i
0.0
c
-0.1
~
~
,~
-
-0.2
-0.3
-0.4
-0.5
-50
-40
-30
-20
-10
0
10
Input Signal Relative to Vref - dB
Figure 5-14
7-111
DlACONVERTER SIGNAL.TQ..OISTORTION RATIO
vs
INPUT SIGNAL
100
III
'a
I
0
~
I
1·kHz Input Signal Into 600 0
90 i- 16-kHz Conversion Rate
TA =25°C
80
70
i
c
60
:e
50
0
i
is
/!.
.J.
II
30
en
20
c
.f!.'
,
40
~
V
L
~
./
'f'"
~
10
o
-50
-40
-30
-20
-10
0
Input Signal Relative to Vref - dB
10
Figure 5-15
O/A GAIN TRACKING (GAIN RELATIVE TO GAIN
AT G-dB INPUT SIGNAL)
0.5
I
1·kHz Input Signal Into 600 0
0.4 16-kHz Conversion Rate
TA =25°C
0.3
III
0.2
'a
I
CD
c
:s2
~c
~
0.1
0.0
-0.1
-0.2
-...
"""
,
-0.3
-0.4
-0.5
-50
-40
-30
-20
-10
0
Input Signal Relative to Vref - dB
Figure 5-16
7-112
10
AID SECOND HARMONIC DISTORTION
vs
INPUT SIGNAL
-100
-90
III
"g
1·kHz Input Signal
16-kHz Conversion Rate
TA 25°C
=
-SO
/'
I
c
0
-70
S
1/1
C
-60
1:
(,)
·S
-/
~ ...........
-50
0
E
111
J:
..... 40
c
-30
tn
-20
"g
§
-10
o
-50
-40
-30
-20
-10
0
10
Input Signal Relative to Vref - dB
Figure 5-17
D/A SECOND HARMONIC DISTORTION
vs
INPUT SIGNAL
-100
-90
III
"g
I
c
~
-SO
1·kHz Input Signal Into 600 n
16-kHz Conversion Rate
TA = 25°C
-70
S1/1
-60
.S=!
c
-50
/'
V-
.-
~~
.....
C
..~
111
-40
J:
"g
-30
J
-20
c
-10
o
-50
-40
-30
-20
-10
0
10
Input Signal Relative to Vref - dB
Figure 5-18
7-113
AID THIRD HARMONIC DISTORTION
vs
INPUT SIGNAL
-1000
ID
"CI
I
c
0
t!
-SO
f-
TA = 25°C
-70
-60
u
-50
...
-40
:J:
-30
C
0
E
.
f- 160kHz Conversion Rate
i
is
1·Hz Input Signal
-90
.- i-"""
V
L
.... ~ r'\
I'll
'E
:c
I-
-20
-10
o
-50
-40
-30
-20
-10
0
10
Input Signal Relative to Vref - dB
Figure 5-19
DIA THIRD HARMONIC DISTORTION
vs
INPUT SIGNAL
-100
-90
ID
"CI
I
c
~
j
-SO
1·kHz Input Signal Into 600 a
160kHz Conversion Rate
TA 25°C
=
-60
.S!
-50
...~
-40
:J:
-30
,
~
-70
- .....
./'
c
I'll
'E
:c
I-
-20
-10
o
-50
-40
-30
-20
-10
0
Input Signal Relative to Vref - dB
FIgure 5-20
7-114
10
6
Application Information
TMS32020/C25
TLC32047
VCC + 1 - - - - - - - - - - - > - - 5V
CLKOUT t---"I--f MSTR CLK
REF 1---111-::--,
FSX t---"I--f FSX
DX
DX
FSR
FSR
DR
DR
CLKR
ANLG GND
I-e--~e_-_---_
VCC - t - _....- - -.....-
SHIFT CLK
C
VDD
-5 v
5V
CLKX
DGTL GND 1 - -....- - - _
~--------------~
C
A
=0.2 Itf, Ceramic
Figure 6-1. AIC Interface to the TMS32020/C25 Showing Decoupling
Capacitors and Schottky Dlodet
t Thomson Semiconductors
VCC
R
3VOutput
5000
0.011lF
TL431
25000
=
=
FOR: VCC 12 V, R 7200 0
VCC =10V, R = 56000
VCC = 0 V, R = 16000
Figure 6-2. External Reference Circuit for TLC32047
7-115
7-116
TLC320AC01C
Data Manual
Single-Supply Analog Interface Circuit
•
TEXAS
INSTRUMENTS
7-117
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to
discontinue any semiconductor product or service without notice, and advises its
customers to obtain the latest version of relevant information to verify, before placing
orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the
specifications applicable at the time of sale in accordance with TI's standard warranty.
Testing and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not
necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications'1.
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT
APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the
customer. Use of TI products in such applications requires the written approval of an
appropriate TI officer. Questions concerning potential risk applications should be
directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design
and operating safeguards should be provided by the customer to minimize inherent or
procedural hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI
warrant or represent that any license, either express or implied, is granted under any
patent right, copyright, mask work right, or other intellectual property right of TI covering
or relating to any combination, machine, or process in which such semiconductor
products or services might be or are used.
Copyright © 1995, Texas Instruments Incorporated
7"":118
Contents
Section
Title
Page
1
Introduction . ............................................................
1.1 Features ............................................................
1.2 Functional Block Diagram .............................................
1.3 Terminal Assignments ................................................
1.4 Terminal Functions ...................................................
1.5 Register Functional Summary .........................................
7-125
7-126
7-127
7-127
7-129
7-132
2
Detailed Description ..................................................... 7-133
2.1 Definitions and Terminology ..........•................................ 7-133
2.2 Reset and Power-Down Functions ..........................•.......... 7-134
2.2.1 Reset ........................................................ 7-134
2.2.2 Conditions of Reset ............................................ 7-134
2.2.3 Software and Hardware Power-Down ............................. 7-134
2.2.4 Register Default Values After POR, Software Reset, or
RESET Is Applied .............................................. 7-134
2.3 Master-Slave Terminal Function ....................................... 7-136
2.4 ADC Signal Channel ................................................. 7-136
2.5 DAC Signal Channel ................................................. 7-136
2.6 Serial Interface ...................................................... 7-136
2.7 Number of Slaves .................................................... 7-137
2.8 Operating Frequencies ............................................... 7-138
2.8.1 Master and Stand-Alone Operating Frequencies ................... 7-138
2.8.2 Slave and Codec Operating Frequencies ......................... 7-138
2.9 Switched-Capacitor Filter Frequency (FCll<) ............................ 7-138
2.10 Filter Bandwidths .................................................... 7-138
2.11 Required Minimum Number of MClK Periods ...........' ................ 7-138
2.12 Master and Stand-Alone Modes ....................................... 7-138
2.12.1 Register Programming .......................................... 7-139
2.12.2 Master and Stand-Alone Functional Sequence ..................... 7-139
2.13 Slave and Codec Modes .............................................. 7-139
2.13.1 Slave and Codec Functional Sequence ........................... 7-140
2.13.2 Slave Register Programming •.•................................. 7-140
2.14 Terminal Functions ................................................... 7-140
2.14.1 Frame-Sync Function .......................................... 7-140
2.14.2 Data Out (DOUT) .............................................. 7-141
2.14.3 Data In (DIN) ........... ; ...................................... 7-141
2.14.4 Hardware Program Terminals (FC1 and FCO) ....................... 7-141
2.14.5 Midpoint Voltages (ADC VMIO and DAC VMIO) ..................... 7-142
7-119
Contents (Continued)
Section
Title
Page
2.15 Device Functions .................................................... 7-142
2.15.1 Phase Adjustment .... ; ........................................ 7-142
2.15.2 Analog Loopback .............................................. 7-143
2.15.316-Bit Mode ................................................... 7-143
2.15.4 Free-Run Mode ........................................... ~ .... 7-143
2.15.5 Force Secondary Communication ................................ 7":"143
2.15.6 Enable Analog Input Summing ..................................• 7-144
2.15.7 DAC Channel (sin x)lx Error Correction ........................... 7-144
2.16 Serial Communications .............. ; ................................ 7-144
2.16.1 Stand-Alone and Master-Mode Word Sequence and Information
Content During Primary and Secondary Communications ........... 7-144
2.16.2 Siave- and Codec-Mode Word Sequence and Information Content
During Primary and Secondary Communications ................... 7-145
2.17 Request for Secondary Serial Communication and Phase Shift ..........•. 7-146
2.17.1 Initiating a Request ............................................ 7-146
2.17.2 Normal Combinations of Control ................................. 7-146
2.17.3 Additional Control Options ...................................... 7-146
2.18 Primary Serial Communications ........................................ 7-147
2.18.1 Primary Serial Communications Data Format ...................... 7-148
2.18.2 Data Format From DOUT During PrimarY Serial Communications .... 7-148
2.19 Secondary Serial Communications ..................................... 7-148
2.19.1 Data Format to DIN During Secondary Serial Communications ....... 7-148
2.19.2 Control Data-Bit Function in Secondary Serial Communication ....... 7-148
2.20 Internal Register Format .............................................. 7-149
2.20.1 Pseudo-Register 0 (No-Op Address) ............................. 7-149
2.20.2 Register 1 (A Register) ......................................... 7-149
2.20.3 Register 2 (B Register) ......................................... 7-150
2.20.4 Register 3 (A' Register) ............•............................ 7-150
2.20.5 Register 4 (Amplifier Gain-Select Register) ........................ 7-151
2.20.6 Register 5 (Analog Configuration Register) ........................ 7-151
2.20.7 Register 6 (Digital Configuration Register) ......................... 7-152
2.20.8 Register 7 (Frame-Sync Delay Register) ........................... 7-152
2.20.9 Register 8 (Frame-Sync Number Register) ........................ 7-153
3
Specifications ............................................. , ............. 7-155
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range .. 7-155
3;2 Recommended Operating Conditions ................................... 7-155
3.3 Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, MCLK = 5.184 MHz, Voo = 5 V, Outputs
Unloaded, Total Device ............................................... 7-156
3.4 Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, Voo = 5 V, Digital 1/0 Terminals (DIN, DOUT, EOC,
FCO, FC1, FS, FSD, MCLK, MIS, SCLK) ....................... ; ........ 7-156
3.5 Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, Voo =5 V, ADC and DAC Channels ..•............ 7-156
7-120
Contents (Continued)
Title
Page
ADC Channel Filter Transfer Function, FCLK = 144 kHz, f8 = 8 kHz
ADC Channel Input, VOO = 5 V, Input Amplifier Gain = 0 dB ...... .
ADC Channel Signal-to-Distortion Ratio, Voo = 5 V, f8 = 8 kHz ... .
DAC Channel Filter Transfer Function, FCLK = 144 kHz,
f8 = 9.6 kHz, VDO = 5 V ...................................... .
3.5.5 DAC Channel Signal-to-Distortion Ratio, Voo = 5 V, f8 = 8 kHz ... .
3.5.6 System Distortion, VOO = 5 V, f8 = 8 kHz, FCLK = 144 kHz ...... .
3.5.7 Noise, Low-Pass and Band-Pass Switched-Capacitor Filters Included,
7-156
7-157
7-157
Voo=5V ..................................................
3.5.8 Absolute Gain Error, VOO = 5 V, f8 = 8 kHz .....................
3.5.9 Relative Gain and Dynamic Range, Voo = 5 V, f8 = 8 kHz. . . . . . . . .
3.5.10 Power-Supply Rejection, Voo = 5 V ............................
3.5.11 Crosstalk Attenuation, Voo = 5 V ..............................
3.5.12 Monitor Output Characteristics, Voo = 5 V ......................
7-159
7-159
7-159
7-160
7-160
7-161
7-162
Section
3.5.1
3.5.2
3.5.3
3.5.4
3.6 liming Requirements and Specifications in Master Mode ...............
3.6.1 Recommended Input liming Requirements for Master Mode,
Voo=5V ..................................................
3.6.2 Operating Characteristics Over Recommended Range of
Operating Free-Air Temperature, Voo = 5 V .....................
3.7 liming Requirements and Specifications in Slave Mode and:Codec
Emulation Mode...................................................
3.7.1 Recommended Input liming Requirements for Slave Mode,
Voo = 5 V ..................................................
3.7.2 Operating Characteristics Over Recommended Range of
Operating Free-Air Temperature, Voo = 5 V .....................
7-157
7-158
7-158
7-162
7-162
7-163
7-163
7-163
4
Parameter Measurement Information ............•.••••..••••..•.•...
7-165
5
Typical Characteristics ....•.••••......•...•...............••....•..
7-171
6
Application Information............................................
7-179
Appendix A Primary Control Bits ......•....••...•.••.......•.••...•..•••.•.•. 7-183
Appendix B Secondary Communications ..•.••...•...•.•••......••••.•.....•. 7-185
Appendix C TLC320AC01CITLC320AC02C Specification Comparisons ..•....... 7-187
7-121
List of Illustrations
TiOe
Page
Figure
1-1.
Control Flow Diagram ................................................ 7-131
2-1.
Functional Sequence for Primary and Secondary Communication.......... 7-137
2-2.
Master and Stand-Alone Functional Sequence........................... 7-145
2-3. Slave and Codec Functional Sequence................................. 7-145
4-1. IN+ and IN- Gain-Control Circuitry..................................... 7-165
4-2. AIC Stand-Alone and Master-Mode Timing.............................. 7-166
4-3. AIC Slave and Codec Emulation Mode .................................. 7-166
4-4. Master or Stand-Alone FS and FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-167
4-5. Slave FS to FSD Timing .............................................. 7-167
4-6. Slave SCLK to FSD Timing............................................ 7-167
4-7. DOUT Enable Timing From Hi-Z ....................................... 7-168
4-8. DOUT Delay Timing to Hi-Z ........................................... 7-168
4-9. EOC Frame Timing ................................................... 7-168
4-10. Master-Slave Frame-Sync Timing After a Delay Has Been Programmed
Into the FSD Registers............................................... 7-169
4-11 . Master and Slave Frame-Sync Sequence with One Slave ............. ,... 7-169
5-1
ADC Low-Pass Response ............................................. 7-171
5-2
ADC Low-Pass Response.. . . .. . . . . .. .. .. .. . .. .. . . . . . .. . .. .. .. . .. .. ... 7-171
5-~,_
ADC Group Delay ................................................ , ... 7-172
5-4
ADC Band-Pass Response ............................................. 7-172
5-5
ADC Band-Pass Response ............................................. 7-173
5-6
ADC High-Pass Response ............................................. 7-173
5-7
ADC Band-Pass Group Delay .......................................... 7-174
5-8
DAC Low-Pass Response ............................................. 7-174
5-9
DAC Low-Pass Response ............................................. 7-175
5-10 DAC Low-Pass Group Delay . ~ ........................................ 7-175
5-11 DAC (sin x)/x Correction Filter Response................................ 7-176
5-12 DAC (sin x)/x Correction Filter Response ..... ,.......................... 7-176
5-13 DAC (Sin x)/x Correction Error......................................... 7-177
6-1
Stand-Alone Mode (to DSP Interface) .................................... 7-179
6-2
Codec Mode (to DSP Interface) ......................................... 7-179
6-3
Master With Slave (to DSP Interface) ... , ... , ............................ 7-180
7-122
List of Illustrations (Continued)
Figure
Title
Page
6-4
Single-Ended Input (Ground Referenced) ................................ 7-180
6-5
Single-Ended to Differential Input (Ground Referenced) .................... 7-181
6-6
Differential Load ...................................................... 7-181
6-7
Differential Output Drive (Ground Referenced) ............................ 7-181
6-8
Low-Impedance Output Drive ................ : .......................... 7-182
6-9
Single-Ended Output Drive (Ground Referenced) ......................... 7-182
List of Tables
Table
Title
Page
1-1.
Operating Frequencies
7-131
2-1.
Master-Slave Selection
7-136
2-2.
Sampling Variation With A' ............................................ 7-142
2-3.
Software and Hardware Requests for
Secondary Serial-Communication and Phase-Shift Truth Table............. 7-147
Gain Control (Analog Input Signal Required for
Full-Scale Bipolar AID-Conversion 2s Complement) ...................... 7-165
4-1.
7-123
7-124
1
Introduction
The TLC320AC01 t analog interface circuit (AIC) is an audio-band processor that provides an
analog-to-digital and digital-to-analog input/output interface system on a single monolithic CMOS chip. This
device integrates a band-pass switched-capacitor antialiasing input filter, a 14-bit-resolution
analog-to-digital converter (ADC), a 14-bit-resolution digital-to-analog converter (DAC) , a low-pass
switched-capacitor output-reconstruction filter, (sin x)/x compensation, and a serial port for data and control
transfers.
The internal circuit configuration and performance parameters are determined by reading control
information into the eight available data registers. The register data sets up the device for a given mode of
operation and application.
The major functions of the TLC320AC01 are:
1.
To convert aUdio-signal data to digital format by the ADC channel
2.
To provide the interface and control logic to transfer data between its serial input and output
terminals and a digital signal processor (DSP) or microprocessor
3.
To convert received digital data back to an audio signal through the DAC channel
The antialiasing input low-pass filter is a switched-capacitor filter with a sixth-order elliptic characteristic. The
high-pass filter is a single-pole filter to preserve low-frequency response as the low-pass filter cutoff is
adjusted. There is a three-pole continuous-time filter that precedes this filter to eliminate any aliasing caused
by the filter clock signal.
The output-reconstruction switched-capacitor filter is a sixth-order elliptic transitional low-pass filter followed
by a second-order (sin x)/x correction filter. This filter is followed by a three-pole continuous-time filter to
eliminate images of the filter clock signal.
The TLC320AC01 consists of two signal-processing channels, an ADC channel and a DAC channel, and
the associated digital control. The two channels operate synchronously; data reception at the DAC channel
and data transmission from the ADC channel occur during the same time interval. The data transfer is in
2s-complement format.
There are three basic modes of operation available: the stand-alone analog-interface mode, the
master-slave mode, and the linear-codec mode. In the stand-alone mode, the TLC320AC01 generates the
shift clock and frame synchronization forthe data transfers and is the onlyAIC used. The master-slave mode
has one TLC320AC01 as the master that generates the master-shift clock and frame synchronization; the
remaining AICs are slaves to these signals. In the linear-codec mode, the shift clock and the framesynchronization signals are externally generated and the timing can be any of the standard codec-timing
patterns.
Typical applications for this device include modems, speech processing, analog interface for DSPs,
industrial-process control, acoustical-signal processing, spectral analysis, data acquisition, and
instrumentation recorders.
The TLC320AC01 C is characterized for operation from ODC to 70DC.
t The TLC320AC01 is functionally equivalent to the TLC320AC02 and differs in the electrical specifications as shown
in Appendix C.
7-125
1.1
Features
•
General-Purpose Signal-Processing Analog Front End (AFE)
•
Single 5-V Power Supply
•
Power Dissipation ... 100 mW Typ
•
Signal-ta-Distortion Ratio ... 70 dB Typ
•
Programmable Filter Bandwidths (Up to 10.8 kHz) and Synchronous ADO and DAO Sampling
•
Serial-Port Interface
•
Monitor Output With Programmable Gains of 0 dB, -8 dB, -18 dB, and Squelch
•
Two Sets of Differential Inputs With Programmable Gains of 0 dB, 6 dB, 12 dB, and Squelch
•
Differential or Single-Ended Analog Output' With Programmable Gains of 0 dB, -6 dB, -12 dB,
and Squelch
•
Differential Outputs Drive 3-V Peak into a 600-0 Differential Load
•
Differential Architecture Throughout
•
1-J.IITl Advanced LinEPIOTM Process
•
14-Bit Dynamic-Range ADO and DAO
•
2s-00mplement Data Format
•
Application Report Availablet
t Designing with the TLC320AC01 Analog Interface for DSPs (SLAA006)
LinEPIC is a trademark of Texas Instruments Incorporated.
7-126
1.2
Functional Block Diagram
IN+
INAUXIN+
AUXIN-
11 DOUT
12 FS
MON OUT --=--+-I--------C
MIS
14 MCLK
13 SCLK
....J1""--~
FCO --=-+-1
FC1
10 DIN
17 FSD
19 EOC
OUT+
OUT - --'---+-t
0
~
>
0
c'
«
NC
NC
OUTNC
NC
OUT+
'j5ijijR' OWN
NC
MONOUT
NC
AUXIN+
AUXININ+
INNC
NC
1.4
Terminal Functions
TERMINAL
NAME
NO.t NO.*
DESCRIPTION
I/O
ADCVDD
24
32
I
Analog supply voltage for the ADC channel
ADCVMID
23
30
0
Midsupplyforthe ADC channel (requires a bypass capacitor). ADC VMID must be
buffered when used as an external reference.
ADCGND
22
27
I
Analog ground for the ADC channel
AUX IN+
28
38
I
Noninverting input to auxiliary analog input amplifier
AUXIN-
27
37
I
Inverting input to auxiliary analog input amplifier
DACVDD
5
49
I
Digital supply voltage for the DAC channel
DACVMID
6
51
0
Midsupplyforthe DAC channel (requires a bypass capacitor). DAC VMID must be
buffered when used as an external reference.
DACGND
7
54
I
Analog ground for the DAC channel
DIN
10
1
I
Data input. DIN receives the DAC input data and command information and is
synchronized with SCLK.
DOUT
11
3
0
Data output. DOUT outputs the ADC data results and register read contents.
DOUT is synchronized with SCLK.
DGTLVDD
9
59
I
Digital supply voltage for control logic
DGTLGND
20
22
I
Digital ground for control logic
EOC
19
17
0
End-of-conversion output. EOC goes high at the start of the ADC conversion
Period and low when conversion is complete. EOC remains low until the next ADC
conversion period begins and indicates the internal device conversion period.
FCO
15
11
I
Hardware control input. FCO is used in conjunction with FC1 to request secondary
communication and phase adjustments. FCO should be tied low if it is not used.
FC1
16
12
I
Hardware control input. FC1 is used in conjunction with FCO to request secondary
communication and phase adjustments. FC1 should be tied low if it is not used.
FS
12
4
I/O
Frame synchronization. When FS goes low, DIN begins receiving data bits and
DOUT begins transmitting data bits. In master mode, FS is low during the
simultaneous 16-bit transmission to DI N and from DOUT. In slave mode, FS is
externally generated and must be low for one shift-clock period minimum to initiate
the data transfer.
FSD
17
14
0
Frame-synchronization delayed output. This active-low output synchronizes a
slave device to the frame synchronization timing of the master device. FSD is
applied to the slave FS input and is the same duration as the master FS signal but
delayed in time by the number of shift clocks programmed in the FSD register.
IN+
26
36
I
Noninverting input to analog input amplifier
IN-
25
35
I
Inverting input to analog input amplifier
MCLK
14
10
I
The master-clock input drives all the key logic signals of the AIC.
1
40
0
The monitor output allows monitoring of analog input and is a high-impedance
output.
18
16
I
MONOUT
MIS
Masterlslave select input. When MIS is high, the device is the master and when
low, it is a slave.
Terminal numbers shown are for the FN package.
1: Terminal numbers shown are for the PM package.
7-129
\
1.4
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
43
0
Noninverting output of analog output power amplifier. OUT+ can drive transformer
hybrids or high-impedance loads directly in a differential connection or a
single-ended configuration with a buffered VMID.
4
46
0
Inveiting output of analog output power amplifier. OUT-is functionally identical
with and complementary to OUT+.
PWR OWN
2
42
I
Power-down input. When PWR OWN is taken low, the device is powered down
such that the existing intemally programmed state is niaintained. When PWR
OWN is brought high, full operation resumes.
RESET
8
57
I
Reset input that initializes the internal counters and control registers. RESET
initiates the serial data communications, initializes all of the registers to their
default values, and puts the device in a preprogrammed state. After a low-going
pulse on RESET, the device registers are initialized to provide a 16-kHz
data-conversion rate and 7.2-kHz filter bandwidth for a 10.368-MHz master clock
input signal.
SCLK
13
8
I/O
Shift clock. SCLK clocks the digital data into DIN and out of DOUT during the
frame-synchronization interval. When configured as an output (MIS high), SCLK
is generated intemally by dividing the master clock signal frequency by four. When
configured as an input (MIS low), SCLK is generated extemally and
synchronously to the master clock. This signal clocks the serial data into and out
of the device.
SUBS
21
24
I
NAME.
NO.t
NO.*
OUT+
3
OUT-
Substrate connection. SUBS should be tied to ADC GND.
t Terminal numbers shown are for the FN package.
*
Terminal numbers shown are for the PM package.
7-130
I
Processor
I-
-----------
5.184 MHz
10.368 MHz
~--------
MCLK
I
..
SCLK
1.296MHz ...
2.592 MHz
A Register + A' Register
(8 bits)
2s Complement
A Register
(8 bits)
I
Dlvldeby4
FCLK [lOW-pass filter and
(sin x)/x filter clock] ..
I
r
Control
+-
Normal
Phase Shift
(
-- ~
Single, A·Counter
Period
One-Shot
)
B Register
(8 bits)
Program Divide
A Counter
(8 bits)
I
I
Divide by 2
576kHz
L
B Counter
Conversion
Rate
.
288kHz
Figure 1-1. Control Flow Diagram
Table 1-1. Operating Frequencies
FCLK
(kHz)
LOW·PASS FILTER
BANDWIDTH
(kHz)
144
3.6
B REGISTER CONTENTS
(Program No. of Filter Clocks)
(Decimal)
20 (see Note 1)
18
15
10 (see Note 2)
CONVERSION
RATE
(kHz)
HIGH-PASS
POLE FREQUENCY
(Hz)
7.2
8
9.6
14.4
14.4
16
19.2
28.8
36
40
48
72
72
80
96
144
20 (see Note 1)
18
15
10 (see Notes 2 and 3)
432
10.8
20 (see Note 1)
21.6
108
18
24
120
144
28.8
15 (see Note 3)
216
10 (see Notes 2 and 3)
43.2
NOTES: 1. The 8 register can be programmed for values greater than 20; however, since the sample rate IS lower than
7.2 kHz and the internal filter remains at 3.6 kHz, an external antialiasing filter is required.
2. When the B register is programmed for a value less than 10, the ADe and the CAe conversions are not
completed before the next frame-sync signal and the results are in error.
3. The maximum sampling rate for the ACe channel is 43.2 kHz. The maximum rate for the CAe channel is
25kHz.·
288
7.2
7-131
1.5
Register Functional Summary
There are nine data registers that are used as follows:
Register 0
The No-op register. The 0 address allows phase adjustments to be made without
reprogramming a data register.
Register 1
The A register controls the count of the A counter.
Register 2
The B register controls the count of the B counter.
Register 3
The A' register controls the phase adjustment of the sampling period. The adjustment is
equal to the register value multiplied by the input master period.
Register 4
The amplifier gain register controls the gains of the input, output, and monitor amplifiers.
Register 5
The analog configuration register controls:
Register 6
•
The addition/deletion of the high-pass filter to the ADC signal path
•
The enable/disable of the analog loopback
•
The selection of the regular inputs or auxiliary inputs
•
The function that allows processing of signals that are the sum of the regular inputs and
the auxiliary inputs (VIN + VAUX IN)
The digital configuration register controls:
•
Selection of the free-run function
•
FSD [frame-synchronization (sync) delay] output enable/disable
•
Selection of 16-bit function
•
Forcing secondary communications
•
Software reset
•
Software power down
Register 7.
The frame-sync delay register controls the time delay between the master-device frame
sync and slave-device frame sync. Register 7 must be the last register programmed when
using slave devices since all register data is latched and valid on the sixteenth falling edge
of SCLK. On the sixteenth falling edge of SCLK, all delayed frame-sync intervals are shifted
by this programmed amount.
RegisterS
The frame-sync number register informs the master device of the number of slaves that are
connected in the chain. The frame-sync number is equal to the number of slaves plus one.
7-132
2
2.1
Detailed Description
Definitions and Terminology
ADC Channel
All signal processing circuits between the analog input and the digital conversion
results at DOUT
The operating mode under which the device receives shift clock and frame-sync
Codec Mode
signals from a host processor. The device has no slaves.
d
The d represents valid programmed or default data in the control register format
(see Section 2.19, Secondary Serial Communications) when discussing other
data-bit portions of the register.
Dxx
Bit position in the primary data word (xx is the bit number)
DAC Channel
All signal processing circuits between the digital data word applied to DIN and the
differential output analog signal available at OUT+ and OUTData Transfer Interval The time during which data is transferred from DOUT and to DIN. This interval is 16
shift clocks regardless of whether the shift clock is internally or externally generated.
The data transfer is initiated by the falling edge of the frame-sync signal.
DSxx
Bit position in the secondary data word (xx is the bit number)
FCLK
An internal clock frequency that is a division of MCLK that controls the low-pass filter
and (sinx)/x filter clock (see Figure 1-1 and Table 1-1).
The analog input frequency of interest
fi
Frame Sync
The falling edge of the signal that initiates the data-transfer interval. The primary
frame sync starts the primary communications, and the secondary frame sync starts
the secondary communications.
Frame Sync and
The time between falling edges of successive primary frame-sync signals
Sampling Period
Frame-Sync Interval The time period occupied by 16 shift clocks. Regardless of the mode of operation,
there is always an internal frame-sync interval signal that goes low on the rising
edge of SCLK and remains low for 16 shift clocks. It is used for synchronization of
the serial-port internal signals. It goes high on the seventeenth rising edge of SCLK.
The sampling frequency that is the reciprocal of the sampling period.
fs
Host
Any processing system that interfaces to DIN, DOUT, SCLK, or FS.
Master Mode
The operating mode under which the device generates and uses its own shift clock
and frame~sync signal and generates all delayed frame-sync signals necessary to
support slave devices.
Phase Adjustment
The programmed time variation from the falling edge of one frame-sync signal to the
falling edge of the next frame sync signal. The time variation is determined by the
contents of the A' register. Since the time between falling edges of successive
frame-sync signals is the the sampling period, the sampling period is adjusted.
Primary (Serial)
The digital data-transfer interval. Since the device is synchronous, the signal data
Communications
words from the ADC channel and to the DAC channel occur simultaneously.
Secondary (Serial)
The digital control and configuration data-transfer interval into DIN and the register
Communications
read-data cycle from DOUT. The data-transfer interval occurs when requested by
hardware or software.
Signal Data
The input signal and all of the converted representations through the ADC channel
and return through the DAC channel to the analog output. This is contrasted with
the purely digital software-control data.
Slave Mode
The operating mode under which the device receives shift clock and frame-sync
signals from a master device.
7-133
Stand-Alone Mode
X
The operating mode under which the device generates and uses its own shift clock
and frame-sync signal. The device has no slave devices.
The X represents a don't-care bit position within the control register format.
Reset and Power-Down Functions
2.'2
2.2.1
Reset
The TLC320AC01 resets both the internal counters and registers, including the programmed registers, by
any of the following:
.
•
•
•
Applying power to the device, causing a power-on reset (POR)
Applying a low reset pulse to RESET
Reading in the programmable software reset bit (OS01 in register 6)
PWR OWN resets the counters only and preserves the programmed register contents.
2.2.2
Conditions of Reset
The two internal reset signals used for the reset and synchronization functions are as follows:
1.
Counter reset: This signal resets all flip-flops and latches that are not externally programmed with
the exception of those generating the reset pulse itself. In addition, this signal resets the software
power-down bit.
Counter reset = power-on reset + RESET + RESET bit + PWR OWN
2.
Register reset: This signal resets all flip-flops and latches that are not reset by the counter reset
except those generating the reset pulse itself.
Register reset = power-on reset + RESET + RESET bit
Both reset signals are at least one master-clock period long and release on the falling edge of the master
clock.
2.2.3
Software and Hardware Power-Down
Given the definitions and conditions of RESET, the software-programmed power-down condition is cleared
by resetting the software bit (OSOO in register 6) to zero. It is also cleared by either cycling the power to the
device, bringing PWR OWN low, or bringing RESET low.
PWR OWN powers down the entire chip « 1 mA). The software-programmable power-down bit only
powers down the analog section of the chip ( < 3 mA ), which allows a software power-up function. Cycling
PWR OWN high to low and back to high resets all flip-flops and latches that are not externally programmed,
thereby preserving the register contents.
When PWR OWN is not used, it should be tied high.
2.2.4
Register Default Values After POR, Software Reset, or RESET Is Applied
Register 1 -
T~e
A Register
The default value of the A-register data is decimal 18 as shown below.
7-134
Register 2 - The B Register
The default value of the B-register data is decimal 18 as shown below.
Register 3 - The A' Register
The default value of the A'-register data is decimal 0 as shown below.
Register 4 - The Amplifier Gain-Select Register
The default value of the amplifier gain-select register data is shown below.
Register 5 - The Analog Control Configuration Register
The power-up and reset conditions are as shown below. In the read mode, eight bits are read but the four
LSBs are repeated as the four MSBs.
Register 6 - The Oigital Configuration Register
The default value of OS07 - OSOO is 0 as shown below.
Register 7 - The Frame-Sync Oelay Register
.The default value of OS07 - OSOO is 0 as shown below.
Register 8 - The Frame-Sync Number Register
The default value of OS07 - OSOO is 1 as shown below.
7-135
2.3
Master-Slave Terminal Function
Table 2-1 describes the function of the master/slave (M/S) input. The only difference between master and
slave operations in the TLC320AC01 is that SCLK and FS are outputs when Mis is high and inputs when
Mis is low.
Table 2-1. Master-Slave Selection
MIst
MODE
FS
SCLK
Output
Output
Input.
Slave and Codec Emulation
L
Input
t When the stand-alone mode is desired or when the device is
permanently in the master mode, MIS must be high.
Master and Stand Alone
2.4
H
ADC Signal Channel
To produce excellent common-mode rejection of unwanted signals, the analog signal is processed
differentially until it is converted to digital data. The signal is amplified by the irput amplifier at one of three
software selectable gains (typically 0 dB, 6 dB, or 12 dB). A squelch mode can also be programmed for the
input amplifier.
The amplifier output is filtered and applied to the ADC input. The ADC converts the signal into discrete digital
words in 2s-complement format corresponding to the analog-signal value at the sampling time. These 16-bit
digital words, representing sampled values of the analog input signal, are clocked out of the serial port
(DOUn, one word for each primary communication interval. During secondary communications, the data
previously programmed into the registers can be read out with the appropriate register address and with the
read bit set to 1. When a register read is not requested, all 16 bits are O.
2.5
DAC Signal Channel
QIN receives the 16-bit serial data word (2s complement) from the host during the primary communications
interval and latches the data on the seventeenth rising edge of SCLK. The data are converted to an analog
voltage by the DAC with a sample and hold and then through a (sin x)/x correction circuit and a smoothing
filter. An output buffer with three software-programmable gains (0 dB, -6 dB, and -12 dB), as shown in
register 4, drives the differential outputs OUT + and OUT -. A squelch mode can also be programmed for
the output buffer. During secondary communications, the configuration program data are read into the
device control registers.
'
2.6
Serial Interface
The digital serial interface consists of the shift clock, the frame-synchronization signal, the ADC-channel
data output, and the DAC-channel data input. During the primary 16-bit frame-synchronization interval, the
SCLK transfers the ADC channel results from DOUT and transfers 16-bit DAC data into DIN.
During the secondary frame-synchronization interval, the SCLK transfers the register read data from DOUT
when the read bit is set to a 1. In addition, the SCLK transfers control and device parameter information into
DIN. The functional sequence is shown in Figure 2-1.
7':"136
j+- Sampling Period and Frame-Sync Period -+j
1
1
j+- Frame-Sync Interval-+!
~ Frame-Sync Interval ~
J1fUi:~~k
SCLK
1
1
1
1
I+-- 16 SCLKs.1
1
1
14
1
1
1
1
I,
1
1
1
1
FS
\', I '/, I
1
1
-!( ..c,_* >
1
DIN
"~
K"'---1C>---
: AOCc-a_r-." ~
DOUT
1
1
16 SCLKs --+1
"
~- ... =~~
Figure 2-1. Functional Sequence for Primary and Secondary Communication
2.7
Number of Slaves
The number of slaves is determined by the sum of the individual device delays from the frame-sync (~)
input low to the frame-sync delayed (FSD) low for all slaves as follows:
(n) x tp(FS-FSD) < 1/2 shift-clock period
Where:
n is the number of slave devices.
Example:
From the above equation, the number of slaves is given by:
(n) s
~
x (SCLK period) x tp(FS
~
FSD)
assuming the shift clock is 2.4 MHz and tp(FS - FSD) is 40 ns, then the number of slaves is:
n
1
1
1
s 2.4 MHz x 2 x 40 ns
=
1000
192 = 5.2
The maximum number of slaves under these conditions is five. As the SCLK increases in frequency, the
number of slaves that can be used decreases.
7-137
2.8 Operating Frequencies
2.8.1
Master and Stand-Alone Operating Frequencies
The -sampling (conversion) frequency is derived from the master-clock (MClK) input by the following
equation:
fs
= Sampling
(conversion) frequency
= (A
register value)
~~~~egister value)
x 2
The inverse is the time between the falling edges of two successive primary frame-synchronization signals.
The input and output data clock (SClK) is given by:
SClK frequency = MCLK frequency
4
2.8.2
Slave and Codec Operating Frequencies
The slave and codec conversion and the data frequencies are determined by the externally applied SCLK
and FS signals.
2.9
Switched-Capacitor Filter Frequency (FCll<)
The filter clock (FCLK) is an internal clock signal that determines the filter band-pass frequency and is the
B counter clock. The frequency of the filter clock is derived by the following equation:
FClK
=
. MClK
(A register value) x 2
2.10 Filter Bandwidths
The low-pass (LP) filter -3 dB corner is derived by:
f (LP) = FClK =
MClK
40
40 x (A register value) x 2
The high-pass (HP) filter -3 dB corner is derived by:
f (HP)
= Sampling frequency =
200
MClK
200 x 2 x (A register value) x (B register value)
2.11 Required Minimum Number of MClK Periods
The number of MClKs necessary for proper operation when only the primary communications are used is:
Total number of MClKs =(16 + 2) SClKs x 4 MClKs per SClK
= 72 MClKs minimum
The number of MClKs necessary for proper operation if both the primary and secondary communications
are used is:
Total number of MClKs = (16 + 2) SClKs x 2 x 4 MClKs per SClK
= 144 MClKs mihimum
Even though the TlC320AC01 can perform with this number of MClKs, the host may need more time to
execute the required software instructions between primary and secondary communication Intervals.
2.12 Master and Stand-Alone Modes
The difference between the master and stand-alone modes is that in the stand-alone mode there are no
slave devices. Functionally these two modes are the same. In both, the AIC internally generates the shift
clock and frame-sync signal for the serial communications. These signals and the filter clock (FClK) are
derived from tlie input master clock. The master clock applied at the MClK input determines the internal
device timing. The shift clock frequency is a divide-by-four of the master clock frequency and shifts both the
7-138
input and output data at DIN and DOUT, respectively, during the frame-sync interval (16 shift clocks long).
To begin the communication sequence, the device is reset (see Section 2.2.1, Reset), and the first frame
sync occurs approximately 648 master clocks after the reset condition disappears.
2.12.1
Register Programming
All register programming occurs during secondary communications, and data is latched and valid on the
sixteenth falling edge of SClK. After a reset condition, eight primary and secondary communications cycles
are required to set up the eight programmable registers. Registers 1 through 8 are programmed in
secondary communications intervals 1 through 8, respectively. If the default value for a particular register
is desired, that register does not need to be addressed during the secondary communications. The no-op
command addresses the pseudo-register (register 0), and no register programming takes place during this
communications. The no-op command allows phase shifts of the sampling period without reprogramming
any register.
During the eight register programming cycles, DOUT is in the high-impedance state. DOUT is released on
the rising edge of the eighth primary internal frame-sync interval. In addition, each register can be read back
during DOUT secondary communications by setting the read bit to 1 in the appropriate register. Since the
register is in the read mode, no data can be written to the register during this cycle. To return this register
to the write mode requires a subsequent secondary communication (see Section 2.19, Secondary Serial
Communications for detailed register description).
2..12.2 Master and Stand-Alone Functional Sequence
The A counter counts according to the contents of the A register, and the A counter frequency is divided by
two to produce the filter clock (FClK). The 8 counter is clocked by FClK with the following functional
sequence:
1.
The 8 counter starts counting down from the 8 register value minus one. Each count remains in
the counter for one FClK period including the zero count. This total counter time is referred to
as the 8 cycle. The end of,the zero count is called the end of B cycle.
2.
When the 8 counter gets to a count of nine, the analog-to-digital (A-to-D) conversion starts.
3.
The A-to-D conversion is complete ten FClK periods later.
4.
FS goes low on a rising edge of SClK after the A-to-D conversion is complete. That rising edge
of SClK must be preceded by a falling edge of SClK, which is the first falling edge to occur after
the end of B cycle.
5.
The D-to-A COhversion cycle begins on the rising edge of the internal frame-sync interval and is
complete ten FClK periods later.
.
2.13 Slave and Codec Modes
The only difference between the slave and codec modes is that the codec mode is controlled directly by the
host and does not use a delayed frame-sync signal. In both modes, the shift clock and the frame sync are
both externally generated and must be synchronous with MClK. The conversion frequency is set by the time
interval of externally applied frame-sync falling edges except when the free-run function is selected by bit 5
of register 6 (see Section 2.15.4, Free-Run Mode). The slave device or devices share the shift clock
generated by the master device but receive the frame sync from the previous slave in the chain. The Nth
slave FS receives the (N-1 )st slave FSD output and so on. The first slave device in the chain receives FSD
from the master.
7-139
2.13.1
Slave and Codec Functional Sequence
The A counter counts according to the contents of the A register, and the A counter frequency is divided by
two to produce the FCLK. The device function in the slave or codec mode is the same as steps 1 through
3 of the B cycle description in the master mode but differs as follows:
1.
Same as master
2.
Same as master
3.
Same as master
4.
All internal clocks stop 1/2 FCLK before the end of count 0 in the B counter cycle.
5.
All internal clocks are restarted on the first rising edge of MCLK after the external FS input goes
low. This operation provides the synchronization necessary when using an external FS signal.
6.
The D-to-A conversion starts on the rising edge of the internally generated frame-sync interval
at the end of the 16-shift clock data transfer.
In the slave mode, the master controls the phase adjustments for itself and all slaves since all devices are
programmed in the same frame-sync interval. In the. codec mode, the shift clock and frame sync are
externally generated and provide the timing for the ADC and DAC if the free-run function has not been
selected (see Section 2.15.4, Free-Run Mode). In the codec mode, there is usually no need for phase
adjustments; however, any required phase adjustments must be made by adjusting the external frame-sync
timing (sampling time).
2.13.2 Slave Register Programming
When slave devices are used on power-up or reset, all slave frame-sync signals occur at the same time as
the master frame-sync signal and all slave devices are programmed during the master secondary framesync interval with the same data as the master. The last register programmed must be the frame-sync delay
(FSD) register because the delay starts immediately on the rising edge of the seventeenth shift clock of that
frame- sync interval. After the FSD register programming is completed for the master and slave, the slave
primary frame interval is shifted in time (time slot allocated) according to the data contained in the slave FSD
registers. The master then generates frame-:sync intervals for itself and each slave to synchronize the host
serial. port for data transfers for itself and all slave devices.
The 'number of slaves is specified in the FSN register (register 8); therefore, the number of frame-sync
intervals generated by the master is equal to the number of slaves plus one (see Section 2.7, Number of
Slaves). These master frame-sync intervals are separated in time by the delay time specified by the FSD
register (register 7). These master-generated intervals are the only frame-sync interval signals applied to
the host serial port to provide the data-transfer time slot for the slave devices.
2.14 Terminal Functions
2.14.1
Frame-Sync Function
The frame-sync Signal indicates that the device is ready to send and receive data for both master and slave
modes. The data transfer begins on the falling edge of the frame-sync signal.
2.14.1.1 Frame Sync (FS), Master Mode
The frame sync Is generated internally. FS goes low on the rising edge of SCLK and remains low for the
16-bit data transfer. In addition to generating its own frame-sync interval, the master also outputs a frame
sync for each slave that is being used.
7-140
2.14.1.2 Frame-Sync Delayed (FSD), Master Mode
For the master, the frame-sync delayed output occurs 1/2 shift-clock period ahead of FS to compensate for
the time delay through the master and slave devices. The timing relationships are as follows:
1.
When the FSD register data is 0. then FSD goes low on the falling edge of SClK prior to the rising
edge of SClK when FS goes low (see Figure 4-4).
2.
When the FSD register data is greater than 16, then FSD goes low on a rising edge of SClK that
is the FSD register number of SClKs after the falling edge of FS.
Register data values from 1 to 16 result in the default register value of zero.
2.14.1.3 Frame Sync (FS), Slave Mode
The frame-sync timing is generated externally, applied to FS, and controls tile ADC and DAC timing (see
Section 2.15.4, Free-Run Mode). The external frame-sync width must be a minimum of one shift clock to
be recognized and can remain low until the next data frame is required.
2.14.1.4 Frame-Sync Delayed (FSD), Slave Mode
This output is fed from the master to the first slave and the first slave FSD output to the second and so on
down the chain. The FSD timing sequence in the slave mode is as follows:
1.
When the FSD register data is 0. then FSD goes low after FS goes low (see Figure 4-5).
2.
When the FSD register data is greater than 16, FSD goes low on a rising edge of SClK that is
the FSD register number of SClKs after the falling edge of FS.
Data values from 1 to 16 are constrained because the data transfer requires 16 clock periods.
2.14.2 Data Out (DOUT)
DOUT is placed in the high-impedance state on the seventeenth rising edge of SClK (internal or external)
after the falling edge of frame sync. In the primary communication, the data word is the ADC conversion
result. In the secondary communication, the data is the register read results when requested by the
readlwrite (R/W) bit with the eight MSBs set to a(see"Section 2.16, Serial Communications). If no register
read is requested, the secondary word is all zeroes.
2.14.2.1 Data Out, Master Mode
In the master mode, DOUT is taken from the high-impedance state by the falling edge of frame sync. The
most significant data bit then appears on DOUT.
2.14.2.2 Data Out, Slave Mode
In the slave mode, DOUT is taken from the high-impedance state by the falling edge of the external frame
sync or the rising edge of the external SClK, whichever occurs first (see Figure 4-7). The falling edge of
frame sync can occur ±1/4 SClK period around the SClK rising edge (see Figure 4-3). The most
significant data bit then appears on DOUT.
2.14.3 Data In (DIN)
In the primary communication, the data word is the digital input signal to the DAC channel. In the secondary
communication, the data is the control and configuration data to set up the device for a particular function
(see Section 2.16, Serial Communications).
"2.14.4 Hardware Program Terminals (FC1 and FCO)
These inputs provide for hardware programming requests for secondary communication or phase
adjustment. These inputs work in conjunction with the control bits 001 and 000 of the primary data word
or control bits DS15 and DS14 of the secondary data word. The data on FC1 and FCO are latched on the
rising edge of the next internally generated primary or secondary frame-sync interval. These inputs should
be tied low if not used (see Section 2.17, Request for Secondary Serial Communication and Table 2-3).
7-141
2.14.5
Midpoint Voltages (ADC VMIO and DAC VMIO)
8incethe device operates at a single-supply voltage, two midpoint voltages are generated for internal signal
processing. AOC VMID is used for.the AOC channel reference, and OAC VMID is used for the OAC channel
reference. Two referepces minimize channel-to-channel noise and crosstalk. AOC VMID and OAC VMID
must be buffered when used as a reference for external signal processing.
2..15 Device Functions
2.15.1
Phase Adjustment
In some applications, such as modems, the device sampling period may require an adjustment to
synchronize with the incoming bit stream to improve the signal-to-noise ratio. The TLC320AC01 can adjust
the sampling period through the use of the A' register and the control bits.
2.15.1.1 Phase-Adjustment Control
A phase adjustment is a programmed variation in the sampling period. A sampling period is adjusted
according to the data value in the A' register, and the phase adjustment is that number of master clocks
(MCLK). An adjustment is made during device operation with data bits 001 and 000 in the primary
communication, with data bits 0815 and 0814 in the secondary word or in combination with the hardware
terminals FC1 and FCO (see Table 2-3). This adjustment request is latched on the rising edge of the next
internal frame-sync interval and is only valid for the next sampling period. To repeat the phase adjustment,
another phase request must be initiated.
2.15.1.2 Use of the A' Register for Phase Adjustment
The A' register value makes slight timing adjustments to the sampling period. The sampling period
increases or decreases according to the sign of the programmed A' register value and the state of data bits
001 and 000 in the primary data word.
The general equation for the conversion frequency is given as:
f = conversion frequency =
MCLK
.
s
(2 x A register value x B register value) ± (A' register value)
Therefore, if A'
= 0, the device conversion (sampling) frequency and period is constant.
If a nonzero A' value is programmed, the sampling frequency and period responds as shown in Table 2-2.
Table 2-2. Sampling Variation With A'
SIGN OF THE A' REGISTER VALUE
001
000
PLUS VALUE
(+)
NEGATIVE VALUE
(-)
0
1
(increase command)
Frequency decreases,
period increases
Frequency increases,
period decreases .
1
0
(decrease command)
Frequency increases,
period decreases
Frequency decreases,
period increases
An adjustment to the sampling period, which must be requested through 001 and 000 of the primary data
word to OIN, is valid for the following sampling period only. When th~ adjustment is required for the
subsequent sampling period, it must be requested again through 001 and 000 of the primary data word.
For each request, only the sampling period occurring immediately after the primary data word request is
affected.
7-142
The amount of time shift in the entire sampling period (1/fsl is as follows:
When the sampling period is set to 125 p.s (8 kHz), the A' register is loaded with decimal 10 and the
TLC320AC01 master clock frequency is 10.386 MHz. The amount of time each sampling period is increased
or decreased, when requested, is:
Time shift = (A' register value) x (MCLK period)
The device changes the entire sampling period by only the MCLK period times the A' register value.
Change in sampling period = contents of A' register x master clock period
= 10 x 96.45 ns = 964 ns (less than 1% of the sampling period)
The sampling period changes by 964.5 ns each time the phase adjustment is requested by the primary data
word (Le., once per sampling period).
It is evident then that the change in sampling period is very small compared to the sampling period. To
observe this effect over a long period of time (> sampling period), this change must be continuously
requested by the primary data word. If the adjustment is not requested again, the sampling period changes
only once and it may appearthatthere was no execution of the command. This is especially true when bench
testing the device. Automatic test equipment can test for results within a single sampling period.
Internally, the A' register value only affects one cycle (period) of the A counter. The A and A' values are
additive, but only for one A-counter period. The A counter begins the first count atthe default or programmed
A-register value and counts down to the A'-register value. As the A' value increases or decreases, the first
clock cycle from the A counter is lengthened or shortened. The initial A-counter period is the only counter
period affected by the A' register such that only this single period is increased or decreased.
2.15.2
Analog Loopback
This function allows the circuit to be tested remotely. In loopback, OUT+ and OUT-are internally connected
to IN + and IN-. The OAC data bits 015 to 002 that are applied to DIN can be compared with the AOC output
data bits 015 to 002 at OOUT. There are some differences due to the AOC and OAC channel offset. The
loopback function is implemented by setting 0501 and 0500 to zero in control register 5 (see Section 2.19,
Secondary Serial Communications).
2.15.3
16-Blt Mode
In the 16-bit mode, the device ignores the last two control bits (001 and 000) of the primary word and
requests continual secondary communications to occur. By ignoring the last two primary communication
bits, compatibility with existing 16-bit software can be maintained. This function is implemented by setting
bit 0503 to 1 in register 6. To return to normal operation, 0503 must be reprogrammed to o.
2.15.4
Free-Run Mode
With the free-run bit set in register 6, the external shift clock and frame sync control only the data transfer.
The AOC and OAC timing are controlled by the A and B register values, and the phase-shift adjustment must
be done as if the device Is in stand-alone mode (by the software or the state of FC1 and FCO).
Phase adjustment cannot be made by adjustment of the frame-sync timing. The external frame sync must
occur within 1/2 FCLK period of the internal frame sync (FCLK as determined by the values of the A and
B registers).
When the external frame sync occurs simultaneously with the internal load, the data-transfer request by the
external frame sync takes precedence over an internal load command. The latching of the AOC conversion
data in the output register is inhibited until the current 16 bits are shifted out of the register by the shift clock.
2.15.5
Force Secondary Communication
With bit 2 in register 6 set to 1, secondary communication is requested continuously. It overrides all software
and hardware requests concerning secondary communication. Phase shifting, however, can still be
performed with the software and hardware.
,
7-143
2.15.6
Enable Analog Input Summing
By setting bits OS01 and OSOO to 11 in register 5, the normal analog input voltage is summed with the
auxiliary input voltage. The gain for the analog input amplifier is set by data bits OS03 and OS02 in register 4.
2.15.7
DAC Channel (sin x)/x Error Correction
The (sin x)/x compensation filter is designed for zero (sin x)/x error using a B-register value of 15. Since the
filter cannot be removed from the signal path, operation using another B-register value results in an error
in the reconstructed analog output. .The error is given by the following equation. Any error compensation
needed by a given application can be performed in the software.
sin
OAC channel frequency response error = 20 x 10910
(2~XAXB
x f)
f MCLK
_--'-~_ _ _~
sin
(303tXA x f)
f MCLK
x 15
B
where:
f
fMCLK
A
B
= the frequency of interest
= the TLC320AC01 master-clock frequency
= the A-register value
= the B-register value
and the arguments of the sin functions are in radians.
2.16 Serial Communications
2.16.1 Stand·Alone and Master-Mode Word Sequence and Information Content During
Primary and Secondary Communications
.
For the stand-alone and master modes, the sequence in Figure 2-2 shows the relationship between the
primary and secondary communications interval, the data content into DIN, and the data content from
OOUT.
The TLC320AC01 can provide a phase-shift command or the next secondary communications interval by
decoding 1) the programmed state of the FC1 and FCO inputs and the 001 and 000 data bits in the primary
data word, or 2) the state of the FC1 and FCO i'!e,uts and the OS15 and I)S14 data bits in the secondary
data word (see Table 2-3). When OS13 (the R/W bit) is the default value of 0, all 16 bits from OOUT are
oduring secondary communication. However, when the R/W bit is set to 1 in the secondary communication
control word, the secondary transmission from OOUT still contains Os in the eight MSBs. The lower order
eight bits contain the data of the register currently being addressed. This function provides register status
information for the host.
7-144
:...
[ (B reglster)l2] FClK Perlodst ---~
I
Primary Frame Sync
(16 SClKslong)
Secondary Frame Sync
(16 SClKs long)
2s-Complement ADC Output
(14 bits plus 00 for the two lSBs)
16 Bits All Os, Except When In
Read Mode (then least significant
8 bits are register data)
2s-Complement Input for the DAC
Channel (14 bits plus two
function bits). If the 2 lSBs Are
Set to 1, Secondary Frame Sync Is
Generated by the TlC320AC01
1
Input Data for the Internal Registers
(16 bits containing control,
address, and data Information)
1..1- - - - . . . .
t The time between the primary and secondary frame sync is the time equal to filter clock (FCLK) period multiplied by the
B-register contents divided by two. The time interval is rounded to the nearest shift clock. The secondary frame-sync
signal goes from high to low on the next shift clock low-te-high transition after (8 register/2) filter clock periods.
Figure 2-2. Master and Stand-Alone Functional Sequence
2.16.2 Slave- and Codec-Mode Word Sequence and Information Content During
Primary and Secondary Communications
For the slave and codec modes, the sequence is basically the same as the stand-alone and master modes
with the exception that the frame sync and the shift clock are generated and controlled externally as shown
in Figure 2-3. For the codec mode, the frame-sync pulse width needs to be a minimum of one shift clock
long. The timing relationship between the frame sync and shift clock is shown in the timing diagrams. Phase
shifting is usually not required in the slave or codec mode because the frame-sync timing can be adjusted
externally if required.
-+I
~ 1 SClK Minimum
Fill _f_f_i_t_J_J
Primary Frame Sync
2s-Complement ADC Output
16 BIts, All Os, Except When In
(14 bits plus 00 for the 2 lSBsln ...._ _ _...... Read Mode (then least significant
master and stand-alone mode and
8 bits are register data)
01 In slave mode)
DOUT
Input Data for the Internal
2s-Complement Input for the DAC
...._ _ _...... Registers (16 bits containing
Channel (14 bits plus two
1 control, address, and data
1 function bits)
1 Information).
1
NOTE: The time between the primary and secondary frame syncs is determined by the application; however, enough
time must be provided so that the host can execute the required number of software instructions in the time
between the end of the primary data transfer (rising edge of the primary frame-sync interval) and the falling edge
of the secondary frame sync (start of secondary communications).
Figure 2-3. Slave and Codec Functional Sequence
7-145
2.17 Request for Secondary Serial Communication and Phase Shift
The following paragraphs describe a request for secondary serial communication and phase shift using
hardware control inputs FC1 and FCO, primary data bits 001 and 000, and secondary data bits OS15 and
OS14.
2.17.1
Initiating a Request
Combinations of FC1 and FCO input conditions, bits 001 and 000 in the primary serial data word, FC1 and
FCO, and bits OS15 and OS14 in the secondary serial data word can initiate a secondary serial
communication or request a phase shift according to the following rules (see Table 2-3).
1.
Primary word phase shifts can be requested by either the hardware or software when the other
set of signals are 11 or 00. If both hardware and software request phase shifts, the software
request is performed.
2.
Secondary words can be requested by either the software or hardware at the same time that the
other set of signals is requesting a phase shift.
3.
Hardware inputs FC1 and FCO are ignored during the secondary word unless OS15 and OS14
are 11. When OS15 and OS14 are 01 or 10, the corresponding phase shift is performed. When
OS15 and OS14 are 00, no phase shift is performed even when the hardware requests a phase
shift.
2.17.2
Normal Combinations of Control
The normal combinations of control are as follows:
. 1.
Use 001 and 000 and OS15 and OS14 to request phase shifts and secondary words by holding
FC1 and FCO to 00.
2.
Use FC1 and FCO exclusively to request phase shifts and secondary words by holding D01 and
000 to 00 and OS15 and OS14 to 11.
3.
Use 001 and 000 only to request secondary words and FC1 and FCO to perform phase shifts
once per period by holding OS15 and DS14 to 00.
2.17.3 Additional Control Options
Additional control options are unusual and are rarely needed or used; however, they are as follows:
7-146
1.
Use 001 and 000 only to request secondary words and FC1 and FCO to perform phase shifts
twice per period by holding OS15 and OS14 to 11.
2.
Use FC1 and FCO exclusively to request secondary words and 001 and 000 and OS 15 an~ OS 14
to perform phase shifts twice per period.
3.
Use FC1 and FCO to perform the phase shift after the primary word and OS15 and OS14 to
perform a phase shift after the secondary word by holding 001 and 000 to 11.
Table 2-3. Software and Hardware Requests for
Secondary Serlal·Communlcatlon and Phase-Shift Truth Table
WITHIN PRIMARY
OR SECONDARY
DATA WORD
Primary
Secondary
CONTROL
BITS
HARDWARE
TERMINALS
PHASE-SHIFT
ADJUSTMENT
(see Section 2.15.1)
D01
DOO
FC1
FCO
EARLIER
LATER
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
1
0
0
1
0
0
1
1
1
1
DS15
DS14
FC1
FCO
EARLIER
LATER
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
1
SECONDARY
REQUEST
(see Note 1)
No request can be made for
secondary communication
within the secondary word.
1
0
0
0
0
0
0
1
1
0
1
0
0
1
0
0
1
1
1
0
1
1
0
0
0
0
1
1
0
1
0
1
1
1
1
0
1
0
1
1
1
1
0
0
NOTE 1: The 0 state indicates that a secondary communication is not being requested. The 1 state indicates that a
secondary communication is being requested.
1
1
1
1
2.18 Primary Serial Communications
Primary serial communications transfer the 14-bit DAC input plus two control bits (001 and 000) to DIN of
the TLC320AC01. They simultaneously transfer the 14-bit ADC conversion result from DOUT to the
processor. The two LSBs are set to 0 in the ADC result.
7-147
2.18.1
Primary Serial Communications Data Format
~------------------------~vr--------~--------------~
14~bit
OAC Conversion Result
2s-Complement Formatt
Control Bits
t 8ince the supply voltage is single ended, the reference for 2s-complement format is AOC VMI O. Voltages above
this reference have a 0 as the M8B, and voltages below this reference have a 1 as the M8B.
During primary serial communications. when 001 and 000 are both high in the DAC data word to DIN, a
subsequent 16 bits of control information is received by the device at DIN during a secondary
serial-communication interval. This seeondaryserial-communication interval begins at 112 the programmed
conversion time when the B register data value is even or 1/2 the programmed value minus one FCLK when
the B register data value is odd. The time between primary and secondary serial communication is
measured from the falling edge of the primary frame sync to the falling edge of the secondary frame sync
(see Section 2.19, Secondary Serial Communications for function and format of control words).
2.18.2 Data Format From DOUT During Primary Serial Communications
~------------------------~vr------------------------~
14-Bit AOC Conversion Result
2s-Complement Format
015 is the 8ign Bit
2.19 Secondary Serial Communications
2.19.1
Data Format to DIN During Secondary Serial Communications
There are nine 16-bit configuration and control registers numbered from zero to eight. All register data
contents are represented in 2s-complement format. The general format of the commands during secondary
serial communications is as follows.
Control Bits
2 bits
RIW
Bit
Register Address
5 bits
Register Data Value
8 bits
All control register words are latched in the register and valid on the sixteenth falling edge of SCLK.
2.19.2 Control Data-Bit Function In Secondary Serial Communication
2.19.2.1 0515 and 0514
In the secondary data word. bits DS15 and DS14 perform the same control function as the primary control
bits 001 and 000 do in the primary data word.
081510814 0813 081210811108101080910808 08071 08061 08051 08041 08031 08021 08011 0800
Control Bits
RIW
Register Address
Register Data
Hardware terminals FC1 and FCO are valid inputs when DS15 and OS 14 are both high. and they are ignored
for all other conditions.
7-148
2.19.2.2
0813 (RIW Bit)
Reset and power-up procedures set this bit to a 0, placing the device in the write mode. When this bit is set
to 1, however, the previous data content of the register being addressed is read out to the host from DOUT
as the least significant eight bits of the 16-bit secondary word. The first eight bits remain set to o. Reading
the data out is nondestructive, and the contents of the register remain unchanged.
A. Write Mode (OS 13 = 0)
Data In. The data word to DIN has the following general format in the write mode.
081510814 0813 081210811108101080910808 0807108061 08051 08041 08031 08021 080110800
Control Bits
Register Oata
Register Address
0
Data Out. The shift clock shifts out all Os as the pattern to the host from DOUT.
0815 0814 0813 0812 0811 0810 0809 0808 0807 0806 0805 0804 0803 0802 0801 0800
0
0
0
0
0
0
0
0
0
0
0
0
0
0
a
0
B. Read Mode (DS13 = 1)
Data In. The data word to DIN has the following format to allow a register read. Phase shifts can
also be done in the read mode.
081510814 0813 081210811108101080910808 08071 08061 08051 08041 08031 08021 08011 0800
Control Bits
Register Address
1
Ignored
Data Out. The shift clock clocks out the data of the register addressed from DOUT in the read mode in
the eight LSBs.
0815 0814 0813 0812 0811 0810 0809 0808 08071 08061 08051 08041 D803\ 08021 0801J 0800
0
0
0
0
0
0
0
Register Oata
0
2.20 Internal Register Format
2.20.1
Pseudo-Register 0 (No-Op Address)
This address represents a no-operation command. No register 1/0 operation takes place, so the device can
receive secondary commands fOr phase adjustment without reprogramming any register. A read of the
no-op is o. The format of the command word is as follows.
081510814 0813 0812 0811 0810 0809 0808 0807 0806 0805 0804 0803 0802 0801 0800
Control Bits
2.20.2
X
0
0
a
0
0
X
X
X
X
X
X
X
X
Register 1 (A Register)
The following command loads DS07 (MSB) - 0500 into the A register.
081510814 0813 0812 0811 0810 0809 0808 08071 08061 08051 08041 08031 08021 08011 0800
Control Bits R/W
0
0
0
0
1
Register Oata
The data in DS07 - DSOO determines the division of the master clock to produce the internal FCLK.
FCLK frequency = MCLKI(A register contents x 2)
7-149
The default value of the A-register data is decimal 18 as shown below.
0807 OS06 0805 0804 0803 0802 0801 0800
0
0
0
1
0
0
1
0
1/
2.20.3
Register 2 (8 Register)
The following command loads OS07 (MSB) - OSOO into the B register.
081510814 0813 0812 0811 0810 0809 0808 080710806108051080410803108021 0801j 0800
Control Bits
RIW
0
0
0
1
Register Oata
0
The data in OS07 - OSOO controls the division of FCLK to generate the conversion clock.
Conversion frequency
= FCLK/(B register contents)
MCLK
2 x A register contents x B register contents
The default value of the B-register data is decimal 18 as shown below.
0807 0806 0805 0804 0803 0802 0801 0800
0
2.20.4
0
0
1
0
0
1
0
Register 3 (A' Register)
The following command contains the A'-register address and loads OS07(MSB) - OSOO into the A' register.
081510814 0813 0812 0811 0810 0809 0808 080710806108051080410803108021080110800
Control Bits
RIW
0
0
0
1
1
Register Oata
The data in OS07 - OSOO is in 2s-complement format and controls the number of master-clock periods that
the sampling time is shifted.
The default value of the k-register data is 0 as shown below.
0807 0806 0805 0804 0803 0802 0801 0800
0
7-150
0
0
0
0
0
0
0
2.20.5
Register 4 (Amplifier Gain-Select Register)
The following command contains the amplifier gain-select register address with selection code for the
monitor output (0505-0504), analog input (0503-0502), and analog output (0501-0500)
programmable gains.
051510514 0513 0512 0511 0510 0509 0508 0507 0506 0505 DS04 0503 0502 0501 0500
Control Bits
R/W
0
0
1
0
0
X
X
•••
•
Monitor output gain - squelch
Monitor output gain .. 0 dB
Monitor output gain .. -8 dB
Monitor output gain .. -18 dB
Analog input gain .. squelch
Analog input gain = 0 dB
Analog input gain .. 6 dB
Analog input gain =12 dB
*
*
0
0
1
1
0
1
0
1
*
••
••
Analog output gain .. squelch
Analog output gain. 0 dB
Analog output gain .. -6 dB
Analog output gain. -12 dB
*
0
0
1
1
*
0
1
0
1
••
••
0
0
1
1
*
0
1
0
1
The default value of the monitor output gain is squelch, which corresponds to data bits 0505 and 0504 equal
to 00 (binary).
.
The default value of the analog input gain is 0 dB, which corresponds to data bits 0503 and 0502 equal
to 01 (binary).
The default value of the analog output gain is 0 dB, which corresponds to data bits 0501 and 0500 equal
to 01 (binary).
The default data value is shown below.
0507 0506 0505 0504 0503 0502 0501 0500
0
2.20.6
0
0
0
0
1
0
1
Register 5 (Analog Configuration Register)
The following command loads the analog configuration register with the individual bit functions described
below.
051510514 0513 0512 0511 0510 0509 0508 0507 0506 0505 0504 0503 0502 0501 0500
Control Bits
R/W
0
0
1
0
1
Must be set to 0
High-pass filter disabled
High-pass filter enabled
Analog loopback enabled
Enables IN+ and IN- (disables AUXIN+ and AUXIN-)
Enables AUXIN + and AUXIN- (disables IN + and IN-)
Enable analog input summing
X
X
X
X
•
*
*
*
*
0
0
0
1
1
0
1
1
0
••
1
0
••
•
•
The default value of the high-pass-filter enable bit is 0, which places the high-pass filter in the signal path.
The default values of 0501 and 0500 are 0 and 1 which enables IN+ and IN-.
7-151
The power-up and reset conditions are as shown below.
OS03 OS02 OS01 OSOO
0
0
1
0
In the read mode, eight bits are read but the four LSBs are repeated as the four MSBs.
2.20.7
Register 6 (Digital Configuration Register)
The following command loads the digital configuration register with the individual bit functions described
below.
OS1510S14 OS13 OS12 OS11 OS10
Control Bits
R/W
0
0
1
OS09 OS08 OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO
1
X
0
X
*
~
~
AOC and OAC conversion free run
Inactive
*
*
*
*
*
1
0
~
~
FSO output disable
Enable
1
0
16-Bit mode, ignore primary LSBs
Normal operation
Force secondary communications
Normal operation
1
0
~
~
~
~
(
Software reset
(upon reset, this bit is automatically reset to 0)
Inactive reset
Software power-down active (automatically reset to 0
after PWR OWN is cycled high to low and back to high)
Power-down function extemal
(uses PWR OWN)
1
0
~
1
~
0
~
1
~
0
The default value of OS07-0S00 is 0 as shown below.
OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO
0
2.20.8
0
0
0
0
0
0
0
Register 7 (Frame-Sync Delay Register)
The following command contains the frame-sync delay (FSD) register address and loads OS07
(MSB)-OSOO into the FSO register. The data byte (OS01-0S00) determines the number of SCLKs
between FS and the delayed frame-sync signal, FSD. The minimum data value for this register is
decimal 18.
OS1510S14 OS13 OS12 OS11 OS10 OS09 OS08 OS071 OS061 OS051 OS041 OS031 OS021 OS011 OSOO
Control Bits RiW
0
0
1
1
1
Register Oata
The default value of OS07 - OSOO is 0 as shown below.
OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO
0
0
0
0
0
0
0
0
When using a slave device, register 7 must be the last register programmed.
7-152
2.20.9
Register 8 (Frame-Sync Number Register)
The following command contains the frame-sync number (FSN) register address and loads OS07
(MSS) - OSOO into the FSN register. The data byte determines the number of frame-sync signals generated
by the TLC320AC01. This number is equal to the number of slaves plus one.
051510514 0513 0512 0511 0510 0509 0508 05071 05061 05051 05041 05031 05021 0501 10500
Control Bits RIW
0
1
0
0
Register Data
0
The default value of OS07 - OSOO is 1 as shown below.
0507 0506 0505 0504 0503 0502 0501 0500
0
0
0
0
0
0
0
1
7-153
7-154
3
Specifications
3.1
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)t
Supply voltage range, DGTL VDD (see Notes 1 and 2) ............... -0.3 V to 6.5 V
Supply voltage range, DAC VDD (see Notes 1 and 2) ................ -0.3 V to 6.5 V
Supply voltage range, ADC VDD (see Notes 1 and 2) ................ -0.3 V to 6.5 V
Differential supply voltage range, DGTL VDD to DAC VDD ............ -0.3 V to 6.5 V
Differential supply voltage range, all positive supply voltages to
ADC GND, DAC GND, DGTL GND, SUBS .................... -0.3 V to 6.5 V
Output voltage range, DOUT ......................... -0.3 V to DGTL VDD + 0.3 V
Input voltage range, DIN ............................. -0.3 V to DGTL VDD + 0.3 V
Ground voltage range, ADC GND, DAC GND,
DGTL GND, SUBS ............................ -0.3 V to DGTL VDD + 0.3 V
Operating free-air temperature range, TA ................. . . . . . . . . . .. O°C to 70°C
Storage temperature range, Tstg ................................. -40°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .............. 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
3.2
Recommended Operating Conditions (see Note 2)
VOO
Positive supply voltage
MIN
NOM
MAX
4.5
5
5.5
V
0.1
V
Steady-state differential voltage between any two supplies
VIH
High-level digital input voltage
VIL
Low-level digital input voltage
10
fMCLK
VIO(PP)
RL
V
2.2
Load output current from AOC VMIO and OAC
Conversion time for the AOC and OAC channels
0.8
V
100
IJA
15
MHz
10 FCLK periods
Master-clock frequency
10.368
Analog input voltage (differential, peak to peak)
I Differential output load resistance
I Single-ended to buffered OAC VMIO voltage load resistance
UNIT
6
600
300
V
Q
·C
70
Operating free-air temperature
0
TA
NOTES: 1. Voltage values for OGTL VOO are with respect to OGTL GNO, voltage values for OAC VOO are with respect
toDACGND,andvoltagevaluesforAOCVOOarewithrespecttoAOCGND. For the subsequent electrical,
operating, and timing specifications, the symbol VOO denotes all positive supplies. OAC GNO, AOC GNO,
OGTL GNO,and SUBS are at 0 V unless otherwise specified.
2. To avoid possible damage to these CMOS devices and associated operating parameters, the sequence
below should be followed when applying power:
(1) Connect SUBS, OGTL GNO, AOC GNO, and OAC GNO to ground.
(2) Connect voltages AOC VOO,and OAC VOO.
(3) Connect voltage OGTL VOO.
(4) Connect the input signals.
When removing power, follow the steps above in reverse order.
7-155
3.3
Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, MClK 5.184 MHz, Voo 5 V, Outputs
Unloaded, Total Device
=
TEST CONDITIONS
PARAMETER
MIN
PWR OWN = 1 and clock signals
present
Supply
current
100
=
20
PWR OWN = 0 after 500 lIS and
clock signals present
Power
dissipation
UNIT
25
mA
2
mA
100
mW
PWR OWN .. 0 after 500 lIS and
clock signals present
5
mW
Software power down, (bit 000,
register 6 set to 1)
15
20
mW
AOCVMIO
Midpoint
voltage
No load
AOCVOoJ2
-0.1
AOCVOO/2
+0.1
V
OACVMIO
Midpoint
voltage
No load
OACVOoJ2
-0.1
OACVOO/2
+0.1
V
3.4
Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, Voo = 5 V, Digital 1/0 Terminals (DIN, DOUT, EOC,
FCO, FC1, FS, FSD, MClK, MIS, SCll<)
PARAMETER
t
MAX
1
PWR OWN = 1 and clock signals
present
Po
TYPt
TEST CONDITIONS
MIN
TYpt
MAX
UNIT
V
VOH
High-level output voltage
IOH--1.6mA
VOL
Low-level output voltage
IOL= 1.6 rnA
2.4
IIH
High-level input current, any digital input
IlL
Low-level input current, any digital input
Ci
Input capacitance
5
pF
Co
Output capacitance
5
pF
0.4
V
VI .. 2.2 V to OGTL VOO
10
VI = 0 V to 0.8 V
10
J.1A
J.1A
All typical values are at VOO = 5 V and TA = 25°C.
3.5
3.5.1
Electrical Characteristics Over Recommended Range of Operating
Free-Air Temp,erature, Voo = 5 V, ADC and DAC Channels
AOC Channel Filter Transfer Function, FCLK
PARAMETER
=144 kHz, fs =8 kHz
TEST CONDITIONS
MIN
-1.8
-0.15
fi .. 300 Hz to 3 kHz
-0.15
0.15
fi" 3.3 kHz
-0.35
0.03
fi" 3.4 kHz
-1
-0.1
fi" 200 Hz
Gain relative to gain at fi .. 1020 Hz (see Note 3)
MAX
UNIT
-2
fi=50Hz
fi=4kHz
-14
fi ~4.6 kHz
-32
dB
NOTE 3: The differential analog input signals are sine waves at 6 V peak to peak. The reference gain is at 1020 Hz.
7-156
ADC Channel Input, Voo
Noted)
3.5.2
=5 V, Input Amplifier Gain =0 dB (Unless Otherwise
PARAMETER
VI(PP)
Peak-to-peak input voltage (see Note 4)
CMRR
Common-mode rejection ratio at IN+, IN-,
AUX IN+, AUX IN- (see Note 5)
ri
Input resistance at IN+, IN-, AUX IN+,
AUXIN-
ADC converter offset error
TEST CONDITIONS
MIN
MAX
UNIT
Single-ended
3
V
Differential
6
V
Band-pass filter selected
DS03, DS02 - 0 in
register 4
Squelch
TYPt
10
30
mV
55
dB
100
kO
60
dB
t All typical values are at VDD -
5 V and TA" 25°C.
NOTES: 4. The differential range corresponds to the full-scale digital output.
5. Common-mode rejection ratio is the ratio of the ADC converter offset error with no signal and the ADC
converter offset error with a common-mode nonzero signal applied to either IN+ and IN- together or
AUX IN+ and AUX IN-together.
3.5.3
ADC Channel Slgnal-to-Dlstortlon Ratio, Voo
Otherwise Noted)
PARAMETER
TEST CONDITIONS
Av=OdB
MIN MAX
Av=6dB
MIN MAX
AV=12dB
MIN MAX
68
-
VI" -12 dB to -6 dB
63
68
VI = -18 dB to -12 dB
56
63
68
VI = -24 dB to-18 dB
51
57
63
VI .. -30 dB to -24 dB
43
51
57
VI = -36 dB to -30 dB
39
45
51
VI .. -42 dB to -36 dB
33
39
45
VI .. -48 dB to -42 dB
27
32
39
VI
ADC channel signal-todistortion ratio
(see Note 6)
=-6 dB to -1 dB
=5 V, fs =8 kHz (Unless
UNIT
dB
NOTE 6: The analog-input test signal is a 102Q-Hz sine wave with 0 dB .. 6 V peak to peak as the reference level for
the analog-input signal.
3.5.4
DAC Channel Filter Transfer Function, FCLK
PARAMETER
=144 kHz, fs =9.6 kHz, Voo =5 V
TEST CONDITIONS
MIN
UNIT
0.15
fi<200 Hz
-0.5
0.15
fi" 300 Hz to 3 kHz
-0.15
0.15
fl" 3.3 kHz
-0.35
0.03
fi" 3.4 kHz
-1
-0.1
fi - 200 Hz
Gain relative to gain at fi - 1020 Hz (see Note 7)
MAX
fi- 4kHz
-14
fi ~ 4.6 kHz
-32
dB
NOTE 7: The input signal is the digital equivalent of a 102Q-Hz sine wave (digital full scale .. 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak.
7-157
DAC Channel Slgnal-to-Dlstortlon Ratio, VDO
Otherwise Noted)
3.5.5
PARAMETER
TEST CONDITIONS
DAC channel signal-todistortion ratio
(see Note 8)
=5 V, fs =8 kHz (Unless
Av=OdB
MIN
MAX
AV=-6dB
MIN MAX
AV=-12dB
MIN
Vo =-6 dB to 0 dB
68
-
Vo =-12 dB to-6 dB
63
68
-
Vo = -18 dB to-12 dB
57
63
68
Vo =-24 dB to-18 dB
51
57
63
Vo • -30 dB to -24 dB
45
51
57
Vo - -36 dB to -30 dB
39
45
51
Vo =-42 dB to -36 dB
33
39
48
Vo =-48 dB to -42 dB
27
33
39
MAX
UNIT
dB
..
NOTE 8: The input signal. VI. IS the digital equivalent of a 1020-Hz sine wave (full-scale analog output at full-scale digital
input =0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The
load impedance for the DAC output buffer is 600 n from OUT + to OUT -.
'
3.5.6
System Distortion, VOO = 5 V, fs = 8 kHz, FCLK = 144 kHz (Unless Otherwise
Noted)
TEST CONDITIONS
MIN TYpt MAX UNIT
PARAMETER
Second harmonic
ADCchannel
attenuation
Third harmonic and
higher harmonics
Second harmonic
DAC channel
attenuation
Single-ended input (see Note 9)
Differential input (see Note 9)
70
Single-ended input (see Note 9)
Differential input (see Note 9)
70
77
82
70
Single-ended output
(see Note 10),
Differential output (see Note 10)
82
77
Single-ended output
(buffered DAC VMID)
(see Note 10)
Differential output (see Note 10)
Third harmonic and
higher harmonics
82
dB
82
77
70
77
t All typical values are at VDD - 5 V and TA _ 25°C.
NOTES: 9. The input signal is a 102Q-Hz sine wave for the ADC channel. Harmonic distortion is defined for an input
level of -1 dB.
10. The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the
DAC output buffer is 600 n from OUT + to OUT -. Harmonic distortion is specified for a signal input level
of 0 dB.
7-158
3.5.7
Noise, Low-Pass and Band-Pass Switched-Capacitor Filters Included,
5 V (Unless Otherwise Noted)
Voo
=
PARAMETER
TEST CONDITIONS
Inputs tied to ADC VMID,
fs .. 8 kHz, FCLK = 144 kHz,
(see Note 11)
ADC idle-channel noise
DAC idle-channel
noise
MIN
Broad-band noise
DIN INPUT .. 00000000000000,
fs .. 8 kHz, FCLK .. 144 kHz,
(see Note 12)
Noise (0 to 7.2 kHz)
Noise (0 to 3.6 kHz)
TYPt
MAX
180
300
180
300
180
300
180
300
UNIT
Jl.Vrms
t All typical values are at VDD = 5 V and TA = 25·C.
NOTES: 11. The ADC channel noise is calculated by taking the RMS value of the digital output codes of the ADC
channel and converting to microvolts.
12. The DAC channel noise is measured differentially from OUT + to OUT-across 600 O.
3.5.8
Absolute Gain Error, VOO
=5 V, fs =8 kHz (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
ADC channel absolute gain error (see Note 13)
-1-dB input signal
DAC channel absolute gain error (see Note 14)
Q-dB input signal,
RL = 6000
MIN
MAX
UNIT
±0.5
TA = 25·C
±1
TA=0-70·C
dB
±0.5
TA" 25·C
±1
TA=0-70·C
NOTES: 13. ADC absolute gain error is the variation in gain from the ideal gain over the specified input signal levels.
The gain is measured with a -1-dB, 102Q-Hz sine wave. The -1-dB input signal allows for any positive gain
or offset error that may affect gain measurements at or close to O-dB input signal levels.
14. The DAC input signal is the digital equivalent of a 1020-Hz sine wave (full-scale analog output at digital fullscale input .. 0 dB). The nominal differential DAC channel output voltage with this input condition is 6 V peak
to peak. The load impedance for the DAC output buffer is 600 0 from OUT + to OUT -.
3.5.9
Relative Gain and Dynamic Range, Voo = 5 V, fs = 8 kHz (Unless Otherwise
Noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
ADC channel relative gain tracking error
(see Note 15)
-48-dB to -1-dB input signal range
±0.15
DAC channel relative gain tracking error
(see Note 16)
-48-dB to Q-dB input signal range
RL(diff) = 600 0
±0.15
UNIT
dB
NOTES: 15. ADC gain tracking is the ratio of the measured gain at one ADC channel input level to the gain measured
at any other input level. The ADC channel input is a -1-dB 1020-Hz sine wave input signal. A -1-dB input
signal allows for any positive gain or offset error that may affect gain measurements at or close to O-dB ADC
input signal levels.
16. DAC gain tracking is the ratio of the measured gain at one DAC channel digital input level to the gain
measured at any other input level. The DAC-channel input signal is the digital equivalent of a 102Q-Hz sine
wave (digital full scale = 0 dB). The nominal differential DAC channel output voltage with this input condition
is 6 V peak to peak. The load impedance for the DAC output buffer is 600 0 from OUT + to OUT -.
7-159
3.5.10
Power-Supply ReJection, VDD
=5 V (Unless Otherwise Noted) (see Note 17)
PARAMETER
ADCVDD
DACVDD
T.EST CONDITIONS
Supply-voltage rejection ratio, ADC channel
Supply-voltage rejection ratio, DAC channel
DGTLVDD Supply-voltage rejection ratio, ADC channel
DGTLVDD Supply-voltage rejection ratio, DAC channel
MIN
TYPt
fi=Ot030kHz
50
~.30t050kHz
55
fi-Ot030kHz
40
~.30t050kHz
45
~=Ot030kHz
50
fi • 30 to 50 kHz
Single ended,
fi=Ot030kHz
55
fi .. 30 to 50 kHz
45
Differential,
~ .. Ot030 kHz
40
fi = 30 to 50 kHz
45
MAX
UNIT
dB
40
t All typical values are at VDD = 5 V and TA" 25°C.
NOTE 17: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 20o-mV
peak-to-peak signal applied to the appropriate supply.
3.5.11
Crosstalk Attenuation, VDD
=5 V (Unless Otherwise Noted)
PARAMETER
ADC channel crosstalk attenuation
DAC channel crosstalk attenuation
TEST CONDITIONS
MIN
TYPt
DAC channel idle with
DIN .. 00000000000000,
ADC input .. 0 dB,
1020-Hz sine wave,
Gain .. 0 dB (see Note 18)
80
ADC channel idle with INP, INM,
AUX IN +, and AUX IN - at ADC VMID
80
DAC channel input. digital equivalent
of a 102o-Hz sine wave (see Note 19)
80
MAX
UNIT
dB
dB
t All typical values are at VDD .. 5 V and TA" 25°C.
NOTES: 18. The test signal is a 1020-Hz sine wave with a 0 dB .. 6-V peak-to-peak reference level for the analog input
signal.
. 19. The input signal is the digital equivalent of a 102o-Hz sine wave (digital full scale .. 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the
DAC output buffer is 600 n from OUT + to OUT -.
7-160
3.5.12 Monitor Output Characteristics, VDD
(see Note 20)
=5 V (Unless Otherwise Noted)
TEST CONDITIONS
MIN
TYpt
VO(PP)
Peak-to-peak ac output
voltage
Quiescent level- ADC VMID
ZL-10kaand60pF
1.3
1.5
VOO
Output offset voltage
No load, single ended
relative to ADC VMID
VOC
Output common-mode voltage
No load
ro
DC output resistance
PARAMETER
AV
Voltage gain (see Note 21)
5
0.4ADC
VDD
MAX
V
10
0.5ADC 0.6ADC
VDD
VDD
50
Gain .. OdB
-0.2
0
0.2
Gain 2 --8dB
-8.2
-8
-7.8
Gain 3 .. -18 dB
-18.4
-18
-17.6
Squelch (see Note 22)
UNIT
mV
V
Q
dB
-60
t All typical values are at VDD - 5 V and TA" 25°C.
NOTES: 20. All monitor output tests are performed with a 10-ka load resistance.
21. Monitor gains are measured with a 102O-Hz, 6-V peak-to-peak sine wave applied differentially between
IN + and IN -. The monitor output gains are nominally 0 dB, -8 dB, and -18 dB relative to its input; however,
the output gains are -6 dB relative to IN+ and IN- or AUX IN+ and AUX IN-.
22. Squelch is measured differentially with respect to ADC VMID.
7-161
3.6
Timing Requirements and Specifications In Master Mode
3.6.1
Recommended Input Timing Requirements for Master Mode, Voo
=5 V
NOM
MAX
MIN
UNIT
tr(MCLK)
Master clock rise time
5
ns
tf(MCLK)
Master clock fall time
5
ns
Master clock duty cycle
40%
tw(RESETI
RESET pulse duration
1 MCLK
tsutDlNl
DIN setup time before SCLK low (see Figure 4-2)
th(DIN)
DIN hold time after SCLK low (see Figure 4-2)
3.6.2
60%
ns
25
20
ns
Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, Voo = 5 V (Unless Otherwise Noted) (see Note 23)
PARAMETER
tf(SCLKl
tr(SCLK)
MIN
Shift clock fall time (see Figure 4-2)
Shift clock rise time (see Figure 4-2)
Shift clock duty cycle
TYpt
MAX . UNIT
13
18
ns
13
18
ns
45%
55%
ld(CH-FL)
Delay time from SCLK high to FSD low
(see Figures 4-2 and 4-4 and Note 24)
5
20
ns
ld(CH-FH)
Delay time from SCLK high to FS high (see Figure 4-2)
5
20
ns
ld(CH-DOUn
Delay time from SCLK high to DOUT valid
(see Figures 4-2 and 4-7)
20
ns
ld(CH-DOUTZ)
Delay time from SCLKi to DOUT in high-impedance state
(see Figure 4-8)
20
ns
ld(ML-EL)
Delay time from MCLK low to EOC low (see Figure 4-9)
40
ns
ld(ML-EHl
tf(ELl
Delay time from MCLK low to EOC high (see Figure 4-9)
40
ns
EOC fall time (see Figure 4-9)
13
ns
tr(EH)
EOC rise time (see Figure 4-9)
13
ns
ld(MH-CH)
Delay time from MCLKhigh to SCLK high
50
ns
Delay time from MCLK high to SCLK low
50
ns
ld(MH-CL)
t All typical values are at VDD - 5 V and TA _ 25°C.
NOTES: 23. All timing specifications are valid with CL .. 20 pF.
24. FSD occurs 1/2 shift-clock cycle ahead of FS when the device is operating in the master mode.
)
7-162
3.7
Timing Requirements and Specifications in Slave Mode and Codec
Emulation Mode
3.7.1
Recommended Input Timing Requirements for Slave Mode, Vee = 5 V
MIN
NOM
tr{MCLK}
Master clock rise time
5
tf(MCLK)
Master clock fall time
5
Master clock duty cycle
40%
tw(RESEn
RESET pulse duration
1 MCLK
tsu(DIN)
DIN setup time before SCLK low (see Figure 4-3)
th(DIN)
DIN hold time after SCLK high (see Figure 4-3)
tsu(FL-CH)
Setup time from FS low to SCLK high
3.7.2
MAX
UNIT
ns
ns
60%
ns
20
20
ns
±SCLK/4
ns
Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, Vee = 5 V (Unless Otherwise Noted) (see Note 23)
PARAMETER
MIN
TYPt
MAX
UNIT
ns
tcCSCLK)
Shift clock cycle time (see Figure 4-3)
tfCSCLI()
Shift clock fall time (see Figure 4-3)
18
ns
trCSCLI()
Shift clock rise time (see Figure 4-3)
18
ns
Shift clock duty cycle
125
45%
55%
ld(CH-FDL)
Delay time from SCLK high to FSD low (see Figure 4-6)
50
ns
ld(CH-FDH)
Delay time from SCLK high to FSD high
40
ns
td(FL-FDL)
Delay time from FS low to FSD low (slave to slave)
(see Figure 4-5)
40
ns
ld(CH-DOUT)
Delay time from SCLK high to DOUT valid
(see Figures 4-3 and 4-7)
40
ns
ld(CH-DOUTZ)
Delay time from SCLKi to DOUT in high-impedance state
(see Figure 4-8)
20
ns
ldCML-EL)
Delay time from MCLK low to EOC low (see Figure 4-9)
40
ns
ld(ML-EH)
Delay time from MCLK low to EOC high (see Figure 4-9)
40
ns
tf(EL)
EOC fall time (see Figure 4-9)
13
ns
tr(EH)
EOC rise time (see Figure 4-9)
13
ld(MH-CH)
Delay time from MCLK high to SCLK high
50
ns
td(MH-CL)
Delay time from MCLK high to SCLK low
50
ns
ns
t All typical values are at VDD" 5 V and TA = 25°C.
NOTE 23: All timing specifications are valid with CL .. 20 pF.
7-163
7-164
4
Parameter Measurement Information
Rfb
R
IN+ or AUX IN+---JVV\r-_e_--t
R
IN- or AUX IN---...JV'II'v--....--t
+
Rfb
=
=
=
=
=
=
=
=
=
Rfb R for DS03 0 and DS02 1
Rfb 2R for DS03 1 and DS02 0
Rfb 4R for DS03 1 and DS02 1
R = 100 leO nominal
Figure 4-1. IN+ and IN- Gain-Control Circuitry
Table 4-1. Gain Control (Analog Input Signal Required for
Full-Scale Bipolar AID-Conversion 28 Complement)t
INPUT CONFIGURATION
Differential configuration
Analog input .. IN + - IN'"' AUX IN+ - AUX IN-
Single-ended configuration§
Analog input .. IN + - VMID
=AUXIN+':"'VMID
CONTROL REGISTER 4
ANALOG INPUTt:
AID CONVERSION
RESULT
DS03
DS02
0
0
1
VID a±3 V
Squelch
±Full scale
0
VID -±1.5V
±Fullscale
0
1
All
1
1
0
VID ,,!,±0.75 V
All
±Full scale
0
·0
1
VI=±1.5V
±Halfscale
1
0
1
VI-±1.5V
VI = ±0.75 V
±Fullscale
1
Squelch
±Full scale
*
tVDD =5V
VID '" differential input voltage, VI .. input voltage referenced to ADe VMID with IN- or AUX IN- connected to
ADe VMI D. In order to minimize distortion, it is recommended that the analog input not exceed 0.1 dB below full scale.
§ For single-ended inputs, the analog input voltage should not exceed the supply rails. All single-ended inputs should be
referenced to the internal reference voltage, ADe VMID, for best common-mode performance.
7-165
-1 I+-
-.I 14---
tf(SCLK)
I
SCLK 2V
I
--+ll--
tr(SCLK)
1
0.8 V
tcI(CH-FL)
I
I
tcI(CH-FH}
~~
>-->---
FSt~~_____.______~I~I~____________________~________- J
I~
I
.
I ---.j ' - tcI(CH-DOUT)
DOU,"*
--(D1!)(
DIN
~"D-1-5'""·
D14
X ~1'. ~ D12 X D11
--l+-I
Y
tau(DIN)
D14
J
J
"""X
D13 X-D-1-2
. 1"
I .. I
th(DIN)
14 .,
D11
.
>CO<
D2
X
D1
X
DO
~'r-v.
1\......J,y../\
D2
X
D1
X
DO
t The time between falling edges of two primary FS signals is the conversion period.
:I: The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling
edge of the shift clock.
.
Figure 4-2. AIC Stand-Alone and Master-Mode Timing
I+-
tf(SCLK)
I
SCLK 2V
I
14 I~I
-h.!
§
r:st \l.
I
I
DOm
.
DIN
~ ~. tcI(CH-DOUT)
t
~ .,4 X 'S ~. D12 XD11
.
tau (DIN)
--@)(
--1+1
D14
1
~.t13 .~"-D1-2'""X D11
th(DIN)
14
r
I
>CO<
>CO<
D2
X
D1
X
DO
.D2
X
D1
X
DO
~
>-->---
t The time between falling edges of two primary FS signals is the conversion period.
:I: The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling
edge of the shift clock.
§ The high-to-Iow transition of FS must must occur within ±1/4 of a shift-clock period around the 2-V level of the shift clock.
Figure 4-3. AIC Slave and Cod,c Emulation Mode
7-166
I
SCLK
\
I
I
I
I
I
I
14
FSD
0.8>J..
I'll
r
\
2.4/1
~
SCLK Per\odl2
1
I
~I
1
tct(CH-FL)
0.8~
Fa
NOTE: Timing shown is for the TLC320AC01 operating as the master or as a stand-alone device.
Figure 4-4. Master or Stand-Alone FI and
m
Timing
0.8~"__________
I
~
tct(FL-FDL)
------------0-.8-~..
1 _________________
NOTE: Timing shown is for the TLC320AC01 operating in the slave mode (i=! and SCLK signals are generated
externally). The programmed data value in the FSD register is O.
Figure 4-5. Slave FI to FSD TIming
SCLK
2.4Vj2
___
II
-+I
\
'r..
/
0.8 V'",.___.
\'-___r
tct(CH-FDL)
------~-8~1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
NOTE: Timing shown is. for the TLC320AC01 operating in the slave mode (~ and SCLK signals are generated
extemally). There is a data value in the FSD register greater than 18 decimal.
Figure 4 - 8. Slave SCLK to ]!II) Timing
7-167
SCLK
•.8~~_..J/
_....;;Ij21
,
1++
DOUT
HI-Z
\ ____
.
Id(CH-DOUT)
~2.4V
X 2.4V
\~
__0.~4_V______________-,. ~._0._4_V______
Figure 4-7. DOUT Enable Timing From H.I-Z
SCLK
0.8~
2V;f
/
.,
~
Id(CH-DOUTZ)
HI-Z
I
0.8/
DOUT
Figure 4-8. DOUT Delay Timing to Hi-Z
!4-14~.1-1I
1
MCLK
____
Id(ML-EH)
-J;r~----0.8~)l~_+i-----~~~0.-8-V-----------I
I
-+I II.-~
.1
tr(EH)
EOC
!~~2-.4~V~----~~I~j------2-.4~vN~·
________....;0.;.;..4..;.V~¥
I
I
14
.
I _0.4 V
1
Internal ADC
Conversion Time
Figure 4-9. EOC Frame Timing
7-168
Id(ML-EL)
--I I+1
.,
tf(EL)
~
.1
1
Master
FS
Master FSD,
Slave Device 1 FS
Delay Is m Shift Clockst
1
I
I
I
I
LJ
14114f----.....-
Delay Is m Shift Clockst
I------i
1-1
JI
I
1
~
Delay Is m Shift Clockst
I
I
I
Slave Device 1 FSD,
Slave Device 2 FS I
1
I
I
I
I
I
I
-- !-I----------------------~U
I
iI
Slave Device 2 FSD,
Slave Device 3 FS
Slave Device
(n -1) FSD,
Slave Device n FS
I
LJr------
I
t The delay time from any FS signals to the corresponding FSD signals is m shift clocks with the value of m being the
numerical value of the data programmed into the FSD register. In the master mode with slaves, the same data word
programs the master and all slave devices; therefore, master to slave 1, slave 1 to slave 2, slave 2 to slave 3, etc., have
the same delay time.
Figure 4-10. Master-Slave Frame-Sync Timing After a Delay Has Been
Programmed Into the FSD Registers
t=o
t=1
Sampling ~
Period
.
I
r
r-i
MasterAIC
Only Primary
Frame Sync
FS
MasterAIC
Only Primary
and Secondary
Frame Sync
~\
'\-oj
1=2
I
I
H
~'
'~'
tMP1
Ie
~
1M.!
I.~
~FSD~
1M.!
1
I
I
IMPI
I
IMPI
1/2 Period I
I
I
I'
I
r-i ~~~ ~, r - i ~'
FS
iiiil
1M.!
II
I
I
IMP!
'
I
-~\II
IW~hrl\
I i
i i
U U
Master and Slave
FS
AICPrimary
Frame Sync
Master and Slave
AIC Primary and
Secondary
Frame Sync
I
ISP
I
ISPI
Fs---U-U1.J-viJiJUu-UiJLru
MP = Master Primary
MS Master Secondary
=
ISP
MP
SP
MS
SS
MP
SP
MS
SS
MP
SP
MS
SS
=
SP Slave Primary
SS =Slave Secondary
Figure 4-11. Master and Slave Frame-Sync Sequence with One Slave
7-169
7-170
5
,
Typical Characteristics
ADC LOW-PASS RESPONSE
0
=
TA 25°C
FCLK 144 kHz
=
-10
III
-20
'tJ
I
6
!
-30
i
=-
CC
-40
r~
II
-50
:--
~
~I
-60
o
1
2
3
4
5
6
7
8
fl -Input Frequency - kHz
9
10
Figure 5-1
ADC LOW-PASS RESPONSE
o.5
o.4
I.
.'
I
TA =25°C
FCLK = 144 kHz
O. 3
0.2
III
'tJ
I
I!
c
cc
o.1
0
~
.....
-0.1
-0.2
r-.....
-
~
,/
r'\
-0.3
-0.4
-0.5
0
0.5
1
1.5
2
2.5
3
fl -Input Frequency - kHz
3.5
4
Figure 5-2
NOTE: Absolute Frequency (kHz)
Normalized Frequency x FCLK (kHz)
144
7-171
ADC GROUP DELAY
1
TA = 25°C
FCLK = 144 kHz
O. 9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
~
-'
0.1
o
o
1
2
J
J
\. .........
-
"
3
4
5
6
7
8
fl -Input Frequency - kHz
9
10
Figure 5-3 '
ADC BAND·PASS RESPONSE
°lr
'\
-1 0
TA=25°C
fs = 8 kHz
FCLK = 144 kHz
-20
-30
-40
I
-50
-60
o
1/
~
II
1
23456
fl-Input Frequency - kHz
7
8
Figure 5-4
NOTE : Absolute Frequency (kHz)
7-172
Normalized Frequency x FCLK (kHz)
144
ADC BAND·PASS RESPONSE
o.5
TA = 25°C
o.4 fs =8 kHz
FCLK = 144 kHz
0.3
0.2
III
'a
I
c
I
:::s
!
0.1
o
I
-0.1
.....
V
/' \
~~
\
I
-0.2
I
-0.3
-0.4
-0.5
o
0.5
1
1.5
2
2.5
3
fl -Input Frequency - kHz
3.5
4
Figure 5-5
ADC HIGH·PASS RESPONSE
0
/
-5
III
/
-10
/
/
'a
I
g
:;::I
!!
!
~
-15
-20
-25
TA = 25°C
fs 8 kHz
FCLK =144 kHz
=
-30
o
50
100
150
200
fl -Input Frequency - kHz
250
FigureS-6
NOTE: Absolute Frequency (kHz)
Normalized Frequency x FCLK (kHz)
144
7-173
ADC BAND-PASS GROUP DELAY
1
I
I
I
TA = 25°C
f.= 8 kHz
FCLK = 144 kHz
0.9
0.8
0.7
I
0.8
I
0.5
II
0.4
0.3
0.2
'-
0.1
o
o
~
/
2
1
"3
4
"""
5
It -Input Frequency -
io-....
8
kHz
r-
J
7
8
Figure 5-7
DAC LOW-PASS RESPONSE
0
"
-10
ID
'0
-20
TA = 25°C
f.= 9.8 kHz
FCLK = 144 kHz
I
c
i
-30
!
-40
~
I~
-50
-80
/
r-...
!I
\
lJ
o
1
2
3
4
5
8
7
8
9
10
fl-Input Frequenoy - kHz
Figure 5-8
NOTE : Absolute Frequency (kHz) = Normalized Frequency x FCLK (kHz)
144
7-174
DAC LOW-PASS RESPONSE
o.5
o.4
T
J
TA =SoC
f. =9.6 kHz
FCLK = 144 kHz
0.3
0.2
CD
"c
I
0.1
t
!
0
--
-
~
'"'-h
-0.1
-0.2
-0.3
-0.4
-0.5
o
0.5
1
1.5
2
2.5
3
3.5
4
fl -Input Frequency - kHz
Figure 5-9
DAC LOW-PASS GROUP DELAY
1
TA~25ob
I
o.9 f- f. =9.6 kHz
FCLK:: 144 kHz
0.8
0.7
I
0.6
I
0.5
j::
0.4
~
f
0.3
0.2
0.1
o
o
,
\
/
"-
""""'"
1
2
3
4
5
6
7
nr
8
9
10
fl -Input Frequency - kHz
Figure 5-10
NOTE: Absolute Frequency (kHz)
Normalized Frequency x FCLK (kHz)
144
7-175
DAC (slnx)lx CORRECTION FILTER RESPONSE
4
~
2
'8I
/
.........
V
V
1\,
~
\
./
o r-
!
i
\
-2
\
-4
\
TA=25°C
Input = ± Joy Sine Wave
-6
o
I
I
I
I
I
2
4
6
8
10
~
12
14
16
18
20
Normalized Frequency
Figure 5-11
DAC (sin x)lx CORRECTION FILTER RESPONSE
500
TA=25OC
Input = ± SOY Sine Wave
400
Vr\
~
I
f
I
300
I i\
200
100
l./
\
V
"
~
o
o
2
4
6
8
10
12
14
16
18
20
Normalized Frequency
Figure 5-12
NOTE: Absolute Frequency (kHz)
7-176
=
Normalized Frequency x FCLK (kHz)
288,
DAC (sin x)/x CORRECTION ERROR
2
TA=25°C
Input = ± 3-V Sine Wave
1.8
V (81n x) Ix Correction
0.8
III
I
-
0.4
.........
0
~
~
V
I"
V
I
Error
~
04
'- •
-0.8
~
"" "'"
~
-1.2
19;2-kHz (81n x)
i\..
Distortion
,~
"\
t\.
-1.8
-2
If
~
1.2
"i'
V
/
o
1
2
3
4
5
8
7
8
9
10
Normalized Frequency
Figure 5-13
NOTE: Absolute Frequency (kHz)
=
Normalized Frequency x FCLK (kHz)
288
7-177
7-178
6
Application Information .
TMS320C2x13x
TLC320AC01
DACVDD
14
CLKOUT
10
DX
DR
FSX
.FSR
CLKX
CLKR
.... 11
-
--:r
--:r
12
MCLK
DACVMID
DIN
DACGND
DOUT
8
7
5V
t
;::: :::: 0.1
0.1
24
FS
5V
23
;::: :::: 0.1 J.Lf
2 2 + 0.1
ADCGND
SCLK
9
-
J.Lf
5V
DGTLVDD
DGTLGND
J.Lf
J.Lf
ADCVDD
ADCVMID
13
5
20
:::::1:
-:....
DGND
0.1
J.Lf
_
....
AGND
Figure 6-1. Stand-Alone Mode (to DSP Interface)
TMS320C2x13x
TLC320AC01
.
.
CLKOUT
DX
FSR
CLKX
CLKR
10
r
-
.... 11
DR
FSX
14
....
h-1
h-1
12
13
MCLK
DIN
DOUT
FS
SCLK
Figure 6-2. Codec Mode (to DSP Interface)
Terminal numbers shown are for the FN package.
7-179
TMS320C2xJ3x
TLC320AC01
.,14
...
10
...
CLKOUT
DX
DR
FSX
FSR
CLKX
..
.. -
11
....
12
W
..
-
MCLK
DIN
DOUT
Master Mode
FS
FSD
13
SCLK
CLKR· ~
TLC320AC01
.,14
.,10
11
MCLK
DIN
DOUT
~ FS
,
4
~
FSD
.,13
SlaveMod~
SCLK
~
Terminal numbers shown are for the FN package.
_
Figure 6-3. Master With Slave (to DSP Interface)
10kn
10kn
IN+
10kn
10kn
ADCVMID
IN. TLE2022
t The VI source must be capable of sinking a current equal to [ADe VMID + IVII(max)]/10 1<0.
Figure 6-4. Single-Ended Input (Ground Referenced)
7-180
IN+
10kn
10kn
10kn
Vlt -..JV\/'v--.....- - I
10kn
IN-
10kn
1 - - - - - - - - ADC VMID
10kn
tThe VI source must be capable of sinking a current equal to [(ADe VMloI2) + IVII(max)]f10 kO.
Figure 6-5. Single-Ended to Differential Input (Ground Referenced)
OUT-
600-0
Load
OUT+
Figure 6-6. Differential Load
10kn
10kn
OUT- 1---'VV'v----tlI------t
OUT+ 1--..JV1/'v----tlI------I
10kn
-::-
600-0
Load
-::-
NOTE: When a signal changes from a single supply with a nonzero reference system to a grounded
load. the operational amplifier must be powered from plus and minus supplies or the load
must be capacitively coupled.
Figure 6-7. Differential Output Drive (Ground Referenced)
7-181
OUT+~--------~
6O()"C
Load
OUT-t------I
Figure 6-8. Low-Impedance Output Drive
100kC
100kC
OUT+ 1--"v".At----...---I
DAC VMID I--..J\/\/'v--.....- - I
100kC
6O()"C
Load
TLE2062
NOTE: When a signal changes from a single supply with a nonzero reference system to a grounded
load, the operational amplifier must be powered from plus and minus supplies or the load
must be capacitively coupled.
Figure 6-9. Single-Ended Output Drive (Ground Referenced)
7-182
Appendix A
Primary Control Bits
The function of the primary-word control bits 001 and 000 and the hardware terminals FCO and FC1 are
shown below. Any combinational state of 001, 000, FC1, and FCO not shown is ignored.
CONTROL FUNCTION OF CONTROL BITS
BITS
TERMINALS
D01
DOO
FC1
FCO
0
0
0
0
On the next falling edge of FS, the AIC receives OAC data 015-002 to OIN and
transmits the AOC data 015- 000 from OOUT.
0
0
0
1
On the next falling edge of FS, the AIC receives OAC data 015-002 to OIN and
transmits the AOC data 015- 000 from OOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of the next internal FS, the next AOC/OAC sampling time occurs later
by the number of MCLK periods equal to the value contained in the A' register. When
the A' register value is negative, the internal falling edge of FS occurs earlier.
0
0
1
0
On the next falling edge of FS, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
rising edge of the next intemal FS, the next AOC/OAC sample time occurs earlier by
the number of MCLK periods determined by the value contained in the A' register.
When the A' register value is negative, the internal falling edge of FS occurs later.
0
0
1
1
On the next falling edge of the primary FS, the AIC receives OAC data 015- 002 at
OIN and transmits the AOC data 015-000 from OOUT.
When FCO and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at OIN. The secondary frame sync~urs at 1/2 the
sampling time as measl,lred from the falling edge of the primary FS.
0
1
0
0
On the next falling edge of FS, the AIC receives OAC data 015-002 to OIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustm.!!!t is determined by the state of 001 and 000 such that on the
next rising edge of FS, the next AOC/OAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, the falling edge of FS occurs earlier.
1
0
0
0
On the next falling edge of FS, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015- 000 from OOUT.
The phase adjustment is determined by the state of 001 and 000. On the next rising
edge of FS, the next AOC/OAC sampling time occurs earlier by the number of MCLK
periods determined by the value contained in the A' register. When the A' register
value is negative, the internal falling edge of FS occurs later.
1
1
0
0
On the next falling edge ofFS, the AIC receives OAC data 015-002 to OIN and
transmits the AOC data 015-000 from OOUT.
When 000 and 001 are both high, the AIC initiates a secondary FS to receive a
secondary control word at OIN. The secondary frame sync occurs at 1/2 the sampling
time as measured from the falling edge of the primary FS.
7-183
CONTROL FUNCTION OF CONTROL BITS (Continued)
BITS
TERMINALS
D01
DOO
FC1
FCO
0
1
1
1
On the next falling edge of FS, the Aid receives OAC data 015-002 to DIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of 001 and 000 such that on the
next rising edge of FS, the next AOC/OAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs earlier.
When FCO and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 1/2 the
sampling time as measured from the falling edge of the primary FS.
1
0
,1
1
On the next falling edge of FS, the AIC receives OAC data 015-002 at DIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of 001 and 000. On the next rising
edge of FS, the next AOC/OAC sample time occurs earlier by the number of MCLK
periods determined by the value contained in the A' register. When the A' register
value is negative, FS occurs later.
When FCO and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 1/2 the
, sampling time as measured from the falling edge of the primary FS.
1
1
1
1
On the next falling edge of the primary FS, 'the AIC receives OAC data 015-002 at
DIN and transmits the AOC data 015-000 from OOUT.
When FC1 and FCO are both high or 001 and 000 are both high, the AIC initiates a
secondary FS to receive a secondary control word at DIN. The secondaryfS occurs
at 1/2 the sampling time measured from the falling edge of the primary FS.
1
1
0
1
On the next failing edge of FS, the AIC receives OAC data 015-002 to DIN and
transmits the AOC data 015-000 from OOUT.
When 000 and 001 are high, the AIC initiates a secondary FS to receive a secondary
control word atOIN. The secondary frame sync occurs at 1/2 the sampling time as
measured from the falling edge of the primary FS.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of FS, the next AOC/OAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs earlier.
1
1
1
0
On the next falling edge of FS, the AIC receives OAC data 015-002 to DIN and
transmits the AOC data 015-000 from OOUT.
When 000 and 001 are high, the AIC initiates a secondary FS to receive a secondary
control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as
measured from the falling edge of the primary FS.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of FS, the next AOC/OAC samF?ling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs earlier.
1
1
1
1
On the next falling edge of FS, the AIC receives OAC data 015-002 at DIN and
transmits the AOC data 015-000 from OOUT.
When FC1 and FCO are both high or 001 and 000 are both high, the AIC Initiates a
secondary FS to receive a secondary control word at DIN. The seconda~s occurs
at 1/2 the sampling time measured from the falling edge of the primary F .
7-184
Appendix B
Secondary Communications
The function of the control bits 0515 and 0514 and the hardware terminals FCO and FC1 are shown below.
Any combinational state of 0515, 0514, FC1, and FCO not shown is ignored.
CONTROL FUNCTION OF SECONDARY COMMUNICATION
BITS
OS15 0$14
TERMINALS
FC1
FCO
0
0
Ignored
On the next falling edge of FS, the AIC receives OAC data 015-002 at DIN and
transmits the AOC data 015-000 from OOUT.
0
1
Ignored
On the next falling edge of the FS, the AIC receives OAC data 015- 002 at OIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of OS 15 and OS14 such that on the
next rising edge of FS, the next AOC/OAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs earlier.
1
0
Ignored
On the next falling edge of FS, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of 001 and 000. On the next rising
edge of FS, the next AOC/OAC sampling time occurs earlier by the number of MCLK
periods determined by the value contained in the A' register. When the A' register
value is negative, FS occurs later.
1
1
0
0
On the next falling edge of FS, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.
1
1
0
1
On the next falling edge of the FS, the AIC receives OAC data 015- 002 at OIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of FS, the next AOC/OAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs earlier.
1
1
1
0
On the next falling edge of FS, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of FS, the next AOC/OAC sampling time occurs earlier by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs later.
1
1
1
1
On the next falling edge of FS, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.
7-185
7-186
Appendix C
TLC320AC01 CITLC320AC02C Specification Comparisons
Texas Instruments manufactures the TLC320AC01 C and the TLC320AC02C specified for the O°C to 70°C
commercial temperature range and the TLC320AC021 specified for the -40°C to 85°C temperature range.
The TLC320AC02C and TLC320AC021 operate at a relaxed TLC320AC01 C specification. The differences
are listed in the following tables.
ADC Channel Slgnal-to-Dlstortion Ratio, Voo
Otherwise Noted) (see Note 1)
PARAMETER
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
_TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TEST CONDITIONS
VI=-6dBto-1 dB
VI- -12 dB to-6 dB
VI
VI
=-18 dB to -12 dB
=-24 dB to-18 dB
VI - -30 dB to -24 dB
VI - -36 dB to -30 dB
VI = -42 dB to -36 dB
VI • -48 dB to -42 dB
=5 V, f8 =8 kHz (Unless
AV=OdB
AV=6dB
MIN
MIN
68
MAX
-
MAX
AV= 12dB
MIN
MAX
UNIT
-
64
-
63
68
59
64
-
57
63
68
-
56
59
64
51
57
63
50
56
59
45
51
57
44
50
56
39
45
51
38
44
50
33
39
45
32
38
44
27
33
39
26
32
38
dB
NOTE 1: The analog-input test signal is a 1020-Hz sine wave with 0 dB - 6 V peak to peak as the reference level for
the analog input signal.
7-187
DAt Channel Signal-ta-Distortion Ratio, Voo = 5 V, fs :: 8 kHz (Unless
Otherwise Noted) (see Note 2)
PARAMETER
TLC320AC01
TLC320AC02
TLC~OAC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC3~OAC02
JLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320ACO~
TEST CONDITIONS
Vo. -6 dB to 0 dB
VO--12dBto-6dB
Vo" -18 dB to-12 dB
Vo" -24 dB to -18 dB
Vo • -30 dB to -24 dB
Vo. -36 dB to -30 dB
Vo '" -42 dB to -36 dB
Vo • -48 dB to -42 dB
Ay=OdB
MIN
MAX
Ay=-6dB
MIN' ~AX
64
-
63
68
59
64
68
Ay=-12dB
MIN
-
",AX
UNIT
-
57
63
68
56
59
64
51
57
63
50
56
59
45
51
57
44
50
56
39
45
51
38
44
50
33
39
45
32
38
44
27
33
39
26
32
38
dB
NOTE 2: The input signal, VI, is the digital equivalent of a 102()"Hz sine wave (full-scale analog output at full-scale digital
input = 0 dB). The nominal differential CAC channel output with this input condition is 6 V peak to peak. The
load impedance for the CAC output buffer is 600 a from OUT + to OUT -.
7-188
System Distortion, ADC Channel Attenuation, Voo
FCLK 144 kHz (Unless Otherwise Noted)
=
PARAMETER
TLC320AC01
TLC320AC02
TLC320AC01
=5 V, fs =8 kHz,
TEST CONDITIONS
Second harmonic
Differential input
(see Note 3)
Third harmonic and higher harmonics
MIN
MAX
UNIT
70
dB
64
dB
70
dB
TLC320AC02
64
dB
NOTE 3: The input signal is a 1020 Hz-sine wave for the ADC channel. Harmonic distortion is defined for an input level
of-1 dB.
System Distortion, DAC Channel Attenuation, Voo
FCLK 144 kHz (Unless Otherwise Noted)
=
PARAMETER
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
Second harmonic
Third harmonic and higher harmonics
=5 V, fs =8 kHz,
TEST CONDITIONS
Differential output
(see Note 4)
MIN
MAX
UNIT
70
dB
64
dB
70
dB
64
dB
NOTE 4: The input signal is the digital equivalent of a 102O-Hz sine wave (digital full scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the DAC
output buffer is 600 n from OUT + to OUT -. Harmonic distortion is specified for a signal input level of 0 dB.
7-189
7-190
TLC320AC02C, TLC320AC021
Data Manual
Single-Supply Analog Interface Circuit
.1ExAs
INSTRUMENTS
7-191
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to
discontinue any semiconductor product or service witho\Jt notiqe, and advises its
customers to obtain the latest version of relevant information to verify, before placing
orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the
specifications applicable at the time of sale in accordance with Tl's standard warranty.
Testing and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not
necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications'~.
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT
APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the
customer. Use of TI products in such applications requires the written approval of an
appropriate TI officer. Questions concerning potential risk applications should be
directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design
and operating safeguards should be provided by the customer to minimize inherent or
procedural hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI
warrant or represent that any license, either express or implied, is granted under any
patent right, copyright, mask work right, or other intellectual property right of TI covering
or relating to any combination, machine, or process in which such semiconductor
products or services might be or are used.
Copyright © 1995, Texas Instruments Incorporated
7-192
Contents
Section
1
Title
Introduction . ............................................................ 7-199
1.1 Features ............................................................
1.2 Functional Block Diagram .............................................
1.3 Terminal Assignments ................................................
1.4 Terminal Functions ...................................................
1.5 Register Functional Summary .........................................
2
Page
7-200
7-201
7-201
7-203
7-206
Detailed Description ..................................................... 7-207
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
Definitions and Terminology ...........................................
Reset and Power-Down Functions .....................................
2.2.1 Reset .............................................•..........
2.2.2 Conditions of Reset ............................................
2.2.3 Software and Hardware Power Down .............................
2.2.4 Register Default Values After POR, Software Reset,
or RESET Is Applied ...........................................
Master-Slave Terminal Function .......................................
ADC Signal Channel .................................................
DAC Signal Channel .................................................
Serial Interface ......................................................
Number of Slaves ............................... '......................
Operating Frequencies ...............................................
2.8.1 Master and Stand-Alone Operating Frequencies .............•.....
2.8.2 Slave and Codec Operating Frequencies .........................
Switched-Capacitor Filter Frequency (FCLK) ............................
Filter Bandwidths ....................................................
Required Minimum Number of MCLK Periods ...........................
Master and Stand-Alone Modes :......................................
2.12.1 Register Programming ..........................................
2.12.2 Master and Stand-Alone Functional Sequence .....................
Slave and Codec Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
2.13.1 Slave and Codec Functional Sequence ...........................
2.13.2 Slave Register Programming ....................................
Terminal Functions ...................................................
2.14.1 Frame-Sync Function ..........................................
2.14.2 Data Out (DOUT) ..............................................
2.14.3 Data In (DIN) ..................................................
2.14.4 Hardware Program Terminals (FC1 and FCO) ......................
2.14.5 Midpoint Voltages (ADC VMID and DAC VMID) .....................
Device Functions ....................................................
7-207
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7-208
7-208
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7-212
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7-214
7-214
7-214
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7-215
7-215
7-216
7-216
7-193
Contents (Continued)
Section
Page
7-216
7-217
7-217
7-217
7-217
7-218
7-218
7-218
Specifications ••••.•..•..••••••••••••••••••••••••.•••••••••.•.•••••••••.•
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range ...
3.2 Recommended Operating Conditions ...................................
3.3 Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature. MCLK = 5.184 MHz, Voo =5 V, Outputs Unloaded,
Total Device .........................................................
3.4 Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, Voo = 5 V, Digital 1/0 Terminals (DIN, DOUT, EOC,
FCO, FC1, FS, FSD, MCLK, Mis, SCLK) .•..............................
3.5 Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, Voo = 5 V, ADC and DAC Channels ...............
3.5.1 ADC Channel Filter Transfer Function, FCLK = 144kHz, f8 = 8 kHz ..
7-229
7-229
7-229
2.16
2.17
2.18
2.19
2.20
3
Title.
2.15; 1 Phase Adjustment .............................................
2.15.2 Analog Loopback ................ ; .............................
2.15.316-Bit Mode ...................................................
2.15.4 Free-Run Mode ................................................
2.15.5 Force Secondary Communication ................................
2.15.6 Enable Analog Input Summing ...................................
2.15.7 DAC Channel (sin x)/x Error Correction ...........................
Serial Communications ......................................•........
2.16.1 Stand-Alone and Master-Mode Word Sequence and Information
Content During Primary and Secondary Communications ...........
2.16.2 Siave- and Codec-Mode Word Sequence and Information Content
During Primary and Secondary Communications ...................
Request for Secondary Serial Communication and Phase Shift ...... ; .....
2.17.1 Initiating a Request ............................................
2.17.2 Normal Combinations of Control .................................
2.17.3 Additional Control Options ......................................
Primary Serial Communications ........................................
2.18.1 Primary Serial Communications Data Format ., ....................
2.18.2 Data Format From DOUT During Primary Serial Communications ....
Secondary Serial Communications ...........•.........................
2.19.1 Data Format to DIN During Secondary Serial Communications .......
2.19.2 Control Data-Bit Function in Secondary Serial Communication .......
Internal Register Format ..............................................
2.20.1 Pseudo-Register 0 (No-Op Address) .............................
2.20.2 Register 1 (A Register) .........................................
2.20.3 Register 2 (B Register) .........................................
2.20.4 Register 3 (A' Register) .................... , ....................
2.20.5 Register 4 (Amplifier Gain-Select Register) ........................
2.20.6 Register 5 (Analog Configuration Register) ........................
2.20.7 Register 6 (Digital Configuration Register) .........................
2.20.8 Register 7 (Frame-Sync Delay Register) ..........................
2.20.9 Register 8 (Frame-Sync Number Register) ........................
7-194
7-218
7-219
7-220
7-220
7-220
7-220
7-221
7-222
7-222
7-222
7-222
7-222
7-223
7-223
7-223
7-224
7-224
7-225
7-225
7-226
7-226
7-227
7-230
7-230
7-230
7-230
Contents (Continued)
Section
Title
3.5.2 ADC Channel Input, Voo = 5 V, Input Amplifier Gain = 0 dB .........
3.5.3 ADC Channel Signal-to-Distortion Ratio, Voo = 5 V, fs = 8 kHz ......
3.5.4 DAC Channel Filter Transfer Function, FCLK = 144 kHz,
fs = 9.6 kHz, Voo = 5 V .........................................
3.5.5 DAC Channel Signal-to-Distortion Ratio, Voo = 5 V, fs = 8 kHz ......
3.5.6 System Distortion, VOO =5 V, fs =8 kHz, FCLK = 144 kHz .........
3.5.7 Noise, Low-Pass and Band-Pass Switched-Capacitor Filters Included,
Voo = 5 V ....................................................
3.5.8 Absolute Gain Error, VOO = 5 V, fs = 8 kHz ................•.......
3.5.9 Relative Gain and Dynamic Range, Voo = 5 V, fs = 8 kHz ...........
3.5.10 Power-Supply Rejection, Voo =5 V ..............................
3.5.11 Crosstalk Attenuation, Voo =5 V ................................
3.5.12 Monitor Output Characteristics, Voo =5 V ........................
3.6 Timing Requirements and Specifications in Master Mode .................
3.6.1 Recommended Input Timing Requirements for Master Mode,
Voo = 5 V ....................................................
3.6.2 Operating Characteristics Over Recommended Range of
Operating Free-Air Temperature, Voo = 5 V .......................
3.7 Timing Requirements and Specifications in Slave Mode and Codec
Emulation Mode .....................................................
3.7.1 Recommended Input Timing Requirements for Slave Mode,
Voo = 5 V ....................................................
3.7.2 Operating Characteristics Over Recommended Range of
Operating Free-Air Temperature, Voo =5 V .......................
4
Page
7-231
7-231
7-231
7-232
7-232
7-233
7-233
7-233
7-234
7-234
7-235
7-236
7-236
7-236
7-237
7-237
7-237
Parameter Measurement Information ...........•.........•................ 7-239
5· Typical Characteristics .........•.••.••.•..••.••....•..•..•..•....•.••..•. 7-245
6
Application Information .•............•.................••.•.•............ 7-253
Appendix A Primary Control Bits •. . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .. 7-257
Appendix B Secondary Communications ...............................•..... 7-259
Appendix C TLC320AC01CITLC320AC02C Specification Comparisons ....•..... 7-261
7-195
List of Illustrations
Figure
Title
1-1 Control Flow Diagram ........................... -. ....................
2-1 Functional Sequence for Primary and Secondary Communication ..........
2-2 Master and Stand-Alone Functional Sequence .................•.........
2-3 Slave and Codec Functional Sequence .................................
4-1 IN+ and IN- Gain-Control Circuitry .....................................
4-2 AIC Stand-Alone and Master-Mode liming ......................•.......
4-3 AIC Slave and Codec Emulation Mode ........................... ; .....
4-4 Master or Stand-Alone FS and FSD liming ...............................
4-5 Slave FS to FSD liming •.............................................
4-6 Slave SCLK to FSD liming ............................................
4-7 DOUT .Enable liming from Hi-Z ........................................
4-8 DOUT Delay liming to Hi-Z ...........................................
4-9 EOC Frame liming ..................................................
4-1 oMaster-Slave Frame-Sync liming After a Delay Has Been
Programmed into the FSD Registers ...............•...................
4-11 Master and Slave Frame-Sync Sequence with One Slave .................
5-1 ADC Low-Pass Response ............................................
5-2 ADC Low-Pass Response ............................................
5-3 ADC Group Delay ....................................................
5-4 ADC Band-Pass Response ...........................................
5-5 ADC Band-Pass Response ...........................................
5-6 ADC High-Pass Response ............................................
5-7 ADC Band-Pass Group Delay .........................................
5-8 DAC Low-Pass Response ............................................
5-9 DAC Low-Pass Response ............................................
5-10DAC Low-Pass Group Delay ..........................................
5-11 DAC (sin x)/x Correction Filter Response ...................•...........•
5-12DAC (sin x)/x Correction Filter Response ...............................
5-13 DAC (sin x)/x Correction Error .........................................
6-1 Stand-Alone Mode (to DSP Interface) .... :1 ..........•..................
6-2 Codec Mode (to DSP Interface) ........................................
6-3 Master With Slave (to DSP Interface) ...................................
6-4 Single-Ended Input (Ground Referenced) .... '...........................
6-5 Single-Ended to Differential Input (Ground Referenced) ...................
6-6 Differential Load .....................................................
6-7 Differential Output Drive (Ground Referenced) ...........................
6-8 Low-Impedance Output Drive ..........................................
6-9 Single-Ended Output Drive (Ground Referenced) ........................
7-196
Page
7-205
7-211
7-219
7-219
7-239
7-240
7-240
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7-255
7-255
7-255
7-256
7-256
List of Tables
Table
1-1
2-1
2-2
2-3
Title
Operating Frequencies ...............................................
Master-Slave Selection ...............................................
Sampling Variation With A' ............................................
Software and Hardware Requests for Secondary Serial-Communication and
Phase-Shift Truth Table ...............................................
4-1 Gain Control {Analog Input Signal Required for Full-Scale Bipolar
AID Conversion 2s Complement} ......................................
Page
7-205
7-210
7-216
7-221
7-239
7-197
7-198
1
Introduction
The TLC320AC02t analog interface circuit (AIC) is an audio-band processor that provides an
analog-to-digital and digital-to-analog input/output interface system on a single monolithic CMOS chip. This
device integrates a band-pass switched-capacitor antiallasing input filter, a 14-bit-resolution
analog-to-digital converter (ADC), a 14-bit-resolution digital-to-analog converter (DAC) , a low-pass
switched-capacitor output-reconstruction filter, (sin x)/x compensation, and a serial port for data and control
transfers.
The internal circuit configuration and performance parameters are determined by reading control
information into the eight available data registers. The register data are used to set up the device for a given
mode of operation and application.
The major functions of the TLC320AC02 are:
1.
To convert audio-signal data to digital format by the ADC channel
2.
To provide the interface and control logic to transfer data between its serial input and output
terminals and a digital signal processor (DSP) or microprocessor
3.
To convert received digital data back to an audio signal through the DAC channel
The antialiasing input low-pass filter is a switched-capacitor filter with a sixth-order elliptic characteristic. The
high-pass filter is a single-pole filter to preserve low-frequency response as the low-pass filter cutoff is
adjusted. There is a three-pole continuous-time filter that precedes this filter to eliminate any aliasing caused
by the filter clock signal.
The output-reconstruction switched-capacitor filter is a sixth-order elliptic transitional low-pass filter followed
by a second-order (sin x)/x correction filter. This filter is followed by a three-pole continuous-time filter to
eliminate images of the filter clock signal.
The TLC320AC02 consists of two signal-processing channels, an ADC channel and a DAC channel, and
the associated digital control. The two channels operate synchronously; data reception at the DAC channel
and data transmission from the ADC channel occur during the same time interval. The data transfer is in
2s-complement format.
There are three basic modes of operation available: the stand-alone analog-interface mode, the
master-slave mode, and the linear-codec mode. In the stand-alone mode, the TLC320AC02 generates the
shift clock and frame synchronization for the data transfers and isthe only AIC used. The master-slave mode
has one TLC320AC02 as the master that generates the master-shift clock and frame synchronization; the
remaining AICs are slaves to these signals. In the linear-codec mode, the shift clock and the framesynchronization signals are externally generated and the timing can be any of the standard codec-timing
patterns.
Typical applications for this device include modems, speech processing, analog interface for DSPs,
industrial-process control, acoustical-signal processing, spectral analysis, data acquisition, and
instrumentation recorders.
The TLC320AC021 is characterized for operation from -40·C to 85·C, and the TLC320AC02C is
characterized for operation from O·C to 70·C.
t The TLC320AC02 is functionally equivalent to the TLC320AC01
and differs only in the electrical specifications as
shown in Appendix C.
7-199
1.1
Features
•
General-Purpose Signal-Processing Analog Front End (AFE)
•
Single 5-V Power Supply
•
Power Dissipation ... 100 mW Typ
•
Signal-to-Distortion Ratio .•• 70 dB Typ
•
Programmable Filter Bandwidths (up to 10.8 kHz) and Synchronous ADC and DAC Sampling
•
Serial-Port Interface
•
Monitor Output With Programmable Gains of 0 dB, -8 dB, -18 dB, and Squelch
•
Two Sets of Differential Inputs With Programmable Gains of 0 dB, 6 dB, 12 dB, and Squelch
•
Differential or Single-Ended Analog Output With Programmable Gains of 0 dB, -6 dB, -12 dB,
and Squelch
•
Differential Outputs Drive 3-V Peak into a 600-0 Differential Load
•
Differential Architecture Throughout
•
1-jJIT1 Advanced LinEPICTM Process
•
14-Bit Dynamic-Range ADC and DAC
•
2s-Complement Data Format
LinEPIC is a trademark of Texas Instruments Incorporated.
7-200
1.2
Functional Block Diagram
IN + :,2~-t---........-.r:~
IN- 25=-~I--""""
AUX IN+ ~"""'I--""""
AUX IN- 2~7:"""'+-Lr---..;~
1--I---..,~1:...:1 DOUT
1--I....,~1:.=2 FS
MONOUT~1~+-I--------~
1--I+-....;1~4 MCLK
1--I....,~1!!:3 SCLK
MlS-,1~.....
FCO -,1~5-"-I
FC1 -,1~8-"-I
1--1+--,1..,0 DIN
t-t--+...;.;17 FSD
OUT + ..;:3:'--+iH."
OUT __4___++0
1--I---..,~1~9 EOC
9
DOTL
VDD
ADC
VMID
24
ADC
VDD
DAC
VMID
Terminal numbers shown are for the FN package.
1.3 Terminal Assignments
FNPACKAGE
(TOP VIEW)
I
~~+l
+lEio~~
........
~oZxx
+
::l ::J
:::) ::l Z
00
DACVOO
DACVMIO
DACGND
~
DGTLVOO
DIN
DOUT
5
::tcCcC-
4 3 2
282726
0
6
7
8
9
10
11
12 13 1415 16 1718
25
24
23
22
21
20
19
INADCVOO
ADCVMIO
ADCGND
SUBS
DGTLGND
EOC
Ife:S
:s 8 0 I~ I~
()()IJ..IJ..IJ..
Cf)::t
7-201
1.3 Terminal Assignments (Continued)
PM PACKAGE
(TOP VIEW)
8
>
0
I-
~
e
1
0
~
()()()()()g()ffi()()~()()~()~
zzzzzoza:zzozzozo
64 63 62 61 60 5958 57 56 55 5453 5251 50 49
10
~
2
Q
3
46
4
5
OUT-
6
OO~
7
PWR OWN
NC
NC
8
NC
9
MONOUT
10
11
12
13
14
15
34
16
33
17 18 1920 21 22 23 242526 27 28 29 30 31 32
NC - No internal connection
7-202
NC
NC
NC.
AUXIN+
AUXININ+
IN-
NC
NC
1.4 Terminal Functions
TERMINAL
NAME
NO.t
I/O
DESCRIPTION
ADCVDD
24
NO.*
32
I
Analog supply voltage for the ADC channel
ADCVMID
23
30
0
Midsupply for the ADC channel (requires a bypass capacitor). ADC VMID must be
buffered when used as an extemal reference.
ADCGND
22
27
I
Analog ground for the ADC channel
AUXIN+
28
38
I
Noninverting input to auxiliary analog input amplifier
AUXIN-
27
37
I
Inverting input to auxiliary analog input amplifier
DACVDD
5
49
I
Digital supply voltage for the DAC channel
DACVMID
6
51
0
Midsupply for the DAC channel (requires a bypass capacitor). DAC VMID must be
buffered when used as an extemal reference.
7
54
I
Analog ground for the DAC channel
DIN
DACGND
10
1
I
Data input. DIN is used to receive the DAC input data and command information and
is synchronized with SCLK.
DOUT
11
3
0
Data output. This terminal outputs the ADC data results and register read contents.
DOUT is synchronized with SCLK.
Digital supply voltage.for control logic
DGTLVDD
DGTLGND
9
59
I
20
Digital ground for control logic
19
22
17
I
EOC
0
End-of-conversion output. EOC goes high at the start of the ADC conversion period
and low when conversion is complete. EOC remains low until the next ADC
conversion period begins and indicates the intemal device conversion period.
FCO
15
11
I
Hardware control input. FCO is used in conjunction with FC1 to request secondary
communication and phase adjustments. FCOshould be tied low if it is not used.
FC1
16
12
I
Harqware control input. FC1 is used in conjunction with FCO to request secondary
communication and phase adjustments. FC1 should be tied low if it is not used.
FS
12
4
I/O
Frame synchronization. When FS goes low, DIN begins receiving data bits and DOUT
begins transmitting data bits. In master mode, FS is low during the simultaneous
16-bit transmission to DIN and from DOUT. In slave mode, FS is externally generated
and must be low for one shift-clock period minimum to initiate the data transfer.
FSD
17
14
0
Frame synchronization delayed output. This active-low output is used to synchronize
a slave device to the frame synchronization timing of the master device. FSD is
applied to the slave FS input and is the same duration as the master FS signal but
delayed in time by the number of shift clocks programmed in the FSD register.
Noninverting input to analog input amplifier
IN+
26
36
I
IN-
25
35
I
Inverting input to analog input amplifier
MCLK
14
10
I
The master clock input is used to drive all the key logic signals of the AIC.
1
40
0
The monitor output allows monitoring of analog input and is a high-impedance output.
18
16
I
MONOUT
MIS
Master/slave select input. When M/S is high, the device is the master and when low,
it is a slave.
t Terminal numbers shown are for the FN package.
:I: Terminal numbers shown are for the PM package.
7-203
1.4
Terminal Functions (Continued)
TERMINAL
NAME
NO.t
1/0
DESCRIPTION
0
Noninverting output of analog output power amplifier. OUT+ can drive transformer
hybrids or high-impedance loads directly In a differential connection or a single-ended
configuration with a buffered VMID.
OUT+
3
NO.*
43
OUT-
4
46
0
Inverting output of analog output power amplifier. OUT-is functionally identical with
and complementary to OUT+.
PWRDWN
2
42
I
Power-down input. When PWR DWN is taken low, the device is powered down such
that the existing intemally programmed state is maintained. When PWR DWN is
brought high, full operation resumes.
RESET
8
57
I
Reset inputthat initializes the intemal counters and control registers. RESET initiates
the serial data communications, initializes all of the registers to their default values,
and puts the device in a preprogrammed state. After a low-going pulse on RESET,
the device registers are initialized to provide a 16-kHz data-conversion rate and
7.2-kHz filter bandwidth for a 10.368-MHz master clock input signal.
SClK
13
8
I/O
Shift clock. SClK clocks the digital data into DIN and out of DOUT during the
frame-synchronization interval. When configured as an output (MIS high), SClK is
generated intemally by dividing the master clock signal frequency by four. When
configured as an input (MIS low), SClK is generated extemally and synchronously
to the master clock. This signal is used to clock the serial data into and out of the
device.
SUBS
21
24
'I
Substrate connection. SUBS should be tied to ADC GND.
t Terminal numbers shown are for the FN package.
=1=
Terminal numbers shown are. for the PM package.
7-204
I
Processor
~
5.1B4MHz
10.368 MHz
- - - - - - - - - - -- - - - - - - - MCLt<;
Divide by 4
I
.
SCLK
1.296MHz
2.592 MHz
p
A Register + A' Register
(8 bits)
2s Complement
A Register
(8 bits)
I
I
FCLK [low-pass filter, and
(sin x)/x filter clock]
I
...
Control
t
Normal
Phase Shift
(
--
'Single, A Counter
Period
One Shot
B Register
(8 bits)
~
Program Divide
A Counter
(8 bits)
I
Dlvldeby2
576kHz
B Counter
Conversion
Rate
..
288kHz
Figure 1-1. Control Flow Diagram
Table 1-1. Operating Frequencies
FCLK
(kHz)
LOW-PASS1=ILTER
BANDWIDTH
(kHz)
144
3.6
288
7.2
B REGISTER CONTENTS
(program No. of Filter Clocks)
(Decimal)
CONVERSION
RATE
(kHz)
HIGH-PASS
POLE FREQUENCY
(Hz)
20 (see Note 1)
18
15
10 (see Note 2)
7.2
8
9.6
14.4
36
40
48
72
20 (see Note 1)
18
15
10 (see Notes 2 and 3)
14.4
16
19.2
28.8
72
80
96
144
20 (see Note 1)
108
21.6
18
24
120
144
15 (see Note 3)
28.8
10 (see Notes 2 and 3)
43.2
216
NOTES: 1. The B register can be programmed for values greater than 20; however, since the sample rate is lower than
7.2 kHz and the intemal filter remains at 3.6 kHz, an extemal antialiasing filter is required.
2. If the B register is programmed for a value less than 10, the ADC and the DAC conversions are not
completed before the next frame-sync signal and the results are in error.
3. The maximum sampling rate for the ADC channel is 43.2 kHz. The maximum rate for the DAC channel is
25 kHz.
432
10.8
7-205
1.5
Register Functional Summary
There are nine data registers that are used as follows:
Register 0
The No-op register. The 0 register allows phase adjustments to be made without
reprogramming a data register.
Register 1
The A register controls the count of the A counter.
Register 2
The B register controls the count of the B counter.
Register 3
The A' register controls the phase adjustment of the sampling period. The adjustment is
equal to the register value multiplied by the input master period.
Register 4
The amplifier gain-select register controls the gains of the input, output, and monitor
amplifiers.
Register 5
The analog control configuration register controls:
Register 6
•
The addition/deletion of the high-pass filter to the ADC signal path
•
The enable/disable of the analog loopback
•
The selection of the regular inputs or auxiliary inputs
•
The function that allows processing of signals that are the sum of the regular inputs and
the auxiliary inputs (VIN + VAUX IN)·
The digital configuration register controls:
•
Selection of the free-run function
•
FSD [frame-synchronization (sync) delay] output enable/disable
•
Selection of 16-bit function
•
Forcing secondary communications
•
Software reset
•
Software power down
Register 7
The frame-sync delay register controls the time delay between the master-clevice frame
sync and slave-device frame sync. Register 7 must be the last register programmed when
using slave devices since all register data is latched and valid on the 16th falling edge of
SCLK. On the 16th falling edge of SCLK, all delayed frame-sync intervals are shifted by this
programmed amount.
RegisterS
The frame-sync number register informs the master device of the number of slaves that are
connected in the chain.
7-206
2
2.1
Detailed Description
Definitions and Terminology
All signal processing circuits between the analog input and the digital conversion
results at DOUT
The operating mode under which the device receives shift clock and frame-sync
Codec Mode
signals from a host processor. The device has no slaves.
The d represents valid programmed or default data in the control register format
d
(see Section 2.19, Secondary Serial Communications) when discussing other
data-bit portions of the register.
Bit position in the primary data word (xx is the bit number)
Dxx
DAC Channel
All signal processing circuits between the digital data word applied to DIN and the
differential output analog signal available at OUT+ and OUTData Transfer Interval The time during which data is transferred from DOUT and to DIN. This interval is
16 shift clocks regardless of whether the shift clock is internally or externally
generated. The data transfer is initiated by the falling edge of the frame-sync signal.
DSxx
Bit position in the secondary data word (xx is the bit number)
FCLK
An internal clock frequency that is a division of MCLK that controls the low-pass filter
and (sinx)/x filter clock (see Figure 1-1 and Table 1-1).
The analog input frequency of interest
fj
Frame Sync
The falling edge of the signal that initiates the data-transfer interval. The primary
frame sync starts the primary communications, and the secondary frame sync starts
the secondary serial communications.
Frame Sync and
The time between falling edges of successive primary frame-sync signals
Sampling Period
Frame-Sync Interval The time period occupied by 16 shift clocks. Regardless of the mode of operation,
there is always an internal frame-sync interval signal that goes low on the rising
edge of SCLK and remains low for 16 shift clocks. It is used for synchronization of
the serial-port internal signals. It goes high on the 17th rising edge of SCLK.
The sampling frequency that is the reciprocal of the sampling period
fs
Host
Any processing system that interfaces to DIN, DOUT, SCLK, or FS
Master Mode
The operating mode under which the device generates and uses its own shift clock
and frame-sync signal and generates all delayed frame-sync signals necessary to
support slave devices
Phase Adjustment
The programmed time variation from the falling edge of one frame-sync signal to the
falling edge of the next frame sync signal. The time variation is determined by the
contents of the A' register. Since the time between falling edges of successive frame
sync signals is the tlie sampling period, the sampling period is adjusted.
Primary (Serial)
The digital data-transfer interval. Since the device is synchronous, the signal
Communications
data words from the ADC channel and to the DAC channel occur simultaneously.
Secondary (Serial)
The digital control and configuration data-transfer interval into DIN and the register
Communications
read-data cycle from DOUT. The data-transfer interval occurs when requested by
hardware or software.
'
Signal Data
The input signal and all of the converted representations through the ADC channel
and return through the DAC channel to the analog output. This is contrasted with
the purely digital software control data.
ADC Channel
7-207
Slave Mode
Stand-Alone Mode
X
2.2
The operating mode under which the device receives. shift clock and frame-sync
signals from a master device
The operating mode under which the device generates and uses its own shift clock
and frame-sync signal. The device has no slave devices.
The X represents a don't care bit position within the control register format
Reset and Power-Down Functions·
2.2.1
Reset
The TLC320AC02 resets both the internal counters and registers, includiog the programmed registers, by
any of the following:
•
•
•
Applying power to the device, causing a power-on reset (POR)
Applying a low reset pulse to RESET
Reading in the programmable software reset bit (OS01 in register 6)
PWR OWN resets the counters only and preserves the programmed register contents.
2.2.2
Conditions of Reset
The two internal reset signals used for the reset and synchronization functions are as follows:
1.
Counter reset: this signal resets all flip-flops and latches that are not externally programmed with
the exception of those generating the reset pulse itself. In addition, this signal resets the software
power-down bit.
Counter reset = power-on reset + RESET + RESET bit + PWR OWN
2.
Register reset: this signal resets all flip-flops and latches that are not reset by the counter reset
except those generating the reset pulse itself.
Register reset = power-on reset + RESET + RESET bit
Both reset signals are at least one master clock period long and release on the falling edge of the master
clock.
2.2.3
Software and Hardware Power Down
Given the definitions and conditions of RESET, the software-programmed power-down condition is cleared
by resetting the software bit (OSOO in register 6) to zero. It is also cleared by either cycling the power to the
device, bringing PWR OWN low, or bringing RESET low.
PWR OWN powers down the entire chip ( < 1 mA ). The software-programmable power-down bit only
powers down the analog section of the chip ( < 3 mA ), which allows a software power-up function. Cycling
PWR OWN high to low and back to high resets all flip-flops and latches that are not externally programmed,
thereby preserving the register contents.
If PWR OWN is not used, it should be tied high.
2.2.4
Register Default Values After POR, .Software Reset, or RESET Is Applied
Register 1 - The A Register
7-208
Register 2 - The B Register
The default value of the B-register data is decimal 18 as shown below.
Register 3 - The A' Register
The default value of the A'-register data is decimal 0 as shown below.
Register 4 - The Amplifier Gain-Select Register
The default value of the amplifier gain-select register data is shown below.
Register 5 - The Analog Control Configuration Register
The power-up and reset conditions are as shown below. In the read mode, eight bits are read but the four
LSBs are repeated as the four MSBs.
~--~---r--~---'
0803
Register 6 - The Oigital Configuration Register
The default value of OS07 - OSOO is 0 as shown below.
Register 7 - The Frame-Sync Oelay Register
The default value of OS07 - OSOO is 0 as shown below.
Register 8 - The Frame-Sync Number Register
The default value of OS07 - OSOO is 1 as shown below.
7-209
2.3
Master-Slave Terminal Function
Table 2-1 describes the function of themasterlslave (Mis) input. The only difference between master and
slave operations in the TLC320AC02 is that SCLK and FS are outputs when MIS is high and inputs when
~~~
.
Table 2-1. Master-Slave Selection
MODE
Mist
FS
SCLK
Master and Stand-Alone
Output
H
Output
Slave and Codec Emulation
L
Input
Input
t If the stand-alone mode is desired or if the device is permanently in the
master mode, MiS must be high.
2.4
ADC Signal
Ch~nnel
To produce excellent common-mode rejection of unwanted signals, the analog signal is processed
differentially until it is converted to digital data. The signal is amplified by the input amplifier at one of three
software-selectable gains (typically 0 dB, 6 dB, or 12 dB). A squelch mode can also be programmed for the
input amplifier.
The amplifier output is filtered and applied to the ADC input. The ADC converts the signal into discrete digital
words in 2s-complement format corresponding to the analog-signal value at the sampling time. These 16-bit
digital words, representing sampled values of the analog input signal, are clocked out of the serial port,
(DOUn, one word for each primary communication interval. During secondary communications, the data
previously programmed into the registers can be read out with the appropriate register address and with the
read bit set to 1. If no register read is requested, all 16 bits are o.
2.5
DAC Signal Channel
DIN receives the 16-bit serial data word (2s complement) from the host during the primary communications
interval and latches the data on the 17th rising edge of SCLK. The data are converted to an analog voltage
by the DAC with a sample and hold and then through a (sin x)/x correction circuit and a smoothing filter. An
output buffer with three software-programmable gains (0 dB, -6 dB; and -12 dB), as shown in Section
2.20.5, Register 4 (Amplifier Gain-8elect Register), drives the differential outputs OUT + and OUT-. A
squelch mode can also be programmed for the output buffer. During secondary communications, the
configuration program data are read into the device control registers.
2.6
Serial Interface
The digital serial interface consists of the shift clock, the frame-synchronization signal, the ADC-Channel
data output, and the DAC-Channel data input. During the primary 16-bit frame-synchronization interval, the
SCLK transfers the ADC channel results from DOUT and transfers t6-bit DAC data into DIN.
During the secondary frame-synchronization interval, the SCLK transfers the register read data from DOUT
if the read bit is set to a one. In addition, the SCLK transfers control and device parameter information into
DIN. The functional sequence is shown in Figure 2-1.
7-210
t+- Sampling Period and Fram.Sync Period -+!
1
j4:- Fram.sync Interval-+!
SClK
1
I+- Fram.sync Intervat-+I
JlfUi:3ik~JirL
1
I
I
",.r1
1
1
1
1
I+-- 18 SClK8.1
n
II
1
1
1
18 SClK8 --+ 1
',I
1
1
1
1
1
1
1
1
ADCc-.~~ >
K"'---1C>-
~ DAC'_* >
~- ... =-~
1
DOUT
{
1
DIN
1
14
I
Figure 2-1. Functional Sequence for Primary and Secondary Communication
2.7
Number of Slaves
The number of slaves is determined by the sum of the Individual device delays from the frame-sync (FS)
input low to the frame-sync delayed (FSD) IQw for all slaves as follows:
(n) x tp(FS-FSD) < 112 shift-clock period
Where:
n is the number of slave devices.
Example:
From the above equation, the number of slaves is given by:
(n) :s
'21
1
x (SCLK period) x tp(FS _ FSD)
and assuming the shift clock is 2.4 MHz and tp(FS - FSD) is 40 ns, then the number of slaves is:
n "'"""
1
2;4 MHz
x1 x
'2
1
- 1000 - 52
40 ns - 192 .
The maximum number of slaves under these conditions is five. As the SCLK increases In frequency, the
number of slaves that can be used decreases.
7-211
2.8
Operating Frequencies
2.8.1
Master and Stand-Alone Operating Frequencies. '
The sampling (conversion) frequency is derived from the master clock (MClK) input by the following
equation:
fs = Sampling (conversion) frequency = (A register value)
~~~~egister'vaIUe)
x 2
The inverse is the time between the falling edges of two successive primary frame synchronization signals.
The input and output data clock (SClK) 'is given by:
SClK frequency = .MClK frequency
4
2.8.2
Slave and Codec Operating Frequencies
The slave and codec conversion and the data frequencies are determined by the externally applied SClK
and FS signals.
2.9
Switched-Capacitor Filter Frequency (FCLK)
The filter clock (FClK) is an internal clock signal that is used to determine the filter band-pass frequency
and is the B counter clock. The frequency of the filter clock is derived by the following equation:
FClK =
MClK '
(A register value) x 2
2.10 Filter Bandwidths
The low-pass (lP) filter -3 dB corner is derived by:
f (lP) = FClK =
MClK
40
40 x (A register value) x 2
The hlgh-pass (HP) filter -3 dB corner Is derived by:
f (HP)
=
Sampling frequency
200
=
MClK
200 x 2 x (A register value) x (B register value)
2.11 Required Minimum Number
of MCLK Periods
The number of MClKs necessary for proper operation if only the primary communications are used is:
Total number of MClKs = (16 + 2) SClKs x 4 MClKs per SClK
= 72 MClKs minimum
The number of MClKs necessary for proper operation if both the primary and secondary communications
are used is:
Total number of MClKs = (16 + 2) SClKs x 2 x 4 MClKs per SClK
= 144 MClKs minimum
Even though the TlC320AC02 can perform with this number of MClKs, the host may need more time to
execute the required software instructions between primary and secondary communication intervals.
2.12 Master and Stand-Alone Modes
The difference between the master and stand-alone modes is that in the stand-alone mode there are no
slave devices. Functionally these two modes are the same. In Qoth, the AIC internally generates the shift
clock and frame-sync signal for the serial communications. These signals and the filter clock (FCLK) are'
derived from the input master clock.The master clock applied at the MClK input determines the Internal
device timing. The shift clock frequency is a divide-by-four of the master clock frequency and shifts both the
7-212
input and output data at DIN and DOUT, respectively, during the frame-sync interval (16 shift clocks long).
To begin the communication sequence, the device is reset (see Section 2.2.1, Reset), and the first frame
sync occurs approximately 648 master clocks after the reset condition disappears.
2.12.1
Register Programming
All register programming occurs during secondary communications, and data is latched and valid on the
16th falling edge of SClK. After a reset condition, eight primary and secondary communications cycles are
required to set up the eight programmable registers. Registers 1 through 8 are programmed in secondary
communications intervals 1 through 8, respectively. If the default value for a particular register is desired,
that register does not need to be addressed during the secondary communications. The no-op command
addresses the pseudo-register (register 0), and no register programming takes place during this
communication. The no-op command allows phase shifts of the sampling period without reprogramming any
register.
During the eight register programming cycles, DOUT is in the high-impedance state. DOUT is released on
the rising edge of the eighth primary internal frame-sync interval. In addition, each register can be read back
during DOUT secondary communications by setting the read bit to 1 in the appropriate register. Since the
register is in the read mode, no data can be written to the register during this cycle. To return this register
to the write mode requires a subsequent secondary communication (see Section 2.19, Secondary Serial
Communications for detailed register description).
2.12.2
Master and Stand-Alone Functional Sequence
The A counter counts according to the contents of the A register, and the A counter frequency is divided by
two .to produce the filter clock (FClK). The B counter is clocked by FClK with the following functional
sequence:
1.
The B counter starts counting down from the B register value minus one. Each count remains in
the counter for one FClK period including the zero count. This total counter time is referred to
as the B cycle. The end of the zero count is called the end of B cycle.
2.
When the B counter gets to a count of nine, the A-to-D conversion starts.
3.
The A-to-D conversibn is complete ten FClK periods later.
4.
FS goes low on a rising edge of SClK after the A-to-D conversion is complete. That rising edge
of SClK must be preceded by a falling edge of SClK, which is the first falling edge to occur after
the end of B cycle.
5.
The D-to-A conversion cycle begins on the rising edge of the internal frame-sync interval and is
complete ten FClK periods later.
2.13 Slave and Codec Modes
The only difference between the slave and codec modes is that the codec mode is controlled directly by the
host and dpes not use a delayed frame-sync signal. In these modes, the shift clock and the frame sync are
both externally generated and must be synchronous with MClK. The conversion frequency is set by the time
interval of externally applied frame sync falling edges except when the free-run function is selected by
bit 5 of register 6 (see Section 2.15.4, Free-Run Mode). The slave device or devices share the shift clock
generated by the master device but receive the frame sync from the previous slave in the chain. The Nth
slave FS receives the (N-1 )st slave FSD output and so on. The first slave device in the chain receives FSD
from the master.
7-213
2.13.1
Slave and Codec Functional Sequence
The A counter counts according to the contents of the A register, and the A counter frequency is divided by
two to produce the filter clock (FClK). The device function in the slave or codec mode is the same as steps
1 through 3 of the B cycle description in the master mode but differs as follows:
1.
Same as master
2.
Same as master
3.
Same as master
4.
All internal clocks stop 1/2 FClK before the end of count 0 in the B counter cycle.
5.
All internal clocks are restarted on the first rising edge of MClK after the external ~ input goes
low. This operation provides the synchronization necessary when using an external FS signal.
6.
The D-to-A conversion starts on the rising edge of the internally generated frame-sync interval
at the end of the 16-shift clock data transfer.
In the slave mode, the master controls the phase adjustments for itself and all slaves since all devices are
programmed in the same frame-sync interval. In the codec mode, the shift clock and frame sync are
externally generated and provide the timing for the ADC and DAC If the free-run function has not been
selected (see Section 2.15.4, Free-Run Mode). In the codec mode, there is usually no need for phase
adjustments; however, any required phase adjustments must be made by adjusting the external frame-sync
timing (sampling time).
,
2.13.2 Slave Register Programming
When slave devices are used on power up or reset, all slave frame-sync signals occur at the same time as
the master frame-sync signal and all slave devices are programmed during the master secondary framesync Interval with the same data as the master. The last register programmed must be the frame-sync delay
(FSD) register because the delay starts immediately on the rising edge of the 17th shift clock of that framesync interval. After the FSD register programming is completed for the master and slave, the slave primary
frame interval is shifted in time (time slot allocated) according to the data contained in the slave FSD
registers. The master then generates frame-sync intervals for itself and each slave to synchronize the host
serial port for data transfers for itself and all slave devices.
The number of slaves is specified in the frame-sync number (FSN) register (register 8); therefore, the
number of frame-sync intervals generated by the master is equal to the number 9f slaves plus one (see
Section 2.7, Number of Slaves). These master frame-sync intervals are separated In time by the delay time
specified by the FSD register (register 7). These master-generated intervals are the only frame-sync interval
signals applied to the host serial port to provide the data transfer time slot for the slave devices.
2.14 Terminal Functions
2.14.1
Frame-Sync Function
The frame-sync signal is used to indicate that the device is ready to send and receive data for both master
and slave modes. The data transfer begins on the falling edge of the frame-sync signal.
2.14.1.1 Frame Sync (FS), Master Mode
The frame sync is generated internally. FS goes low on the rising edge of SClK and remains low for the
16-bit data transfer. In addition to generating its own frame-sync interval, the master also outputs a frame
sync for each slave that is being used.
7-214
2.14.1.2 Frame-Sync Delayed (FSD), Master Mode
For the master, the frame-sync delayed output occurs 1/2 shift-clock period ahead of FS to compensate for
the time delay through the master and slave devices. The timing relationships are as follows:
1.
If the FSD register data is 0, then FSD goes low on the falling edge of SCLK and prior to the rising
edge of SCLK when FS goes low (see Figure 4-4).
2.
If the FSD register data is greater than 16, then FSD goes low on a rising edge of SCLK that is
the FSD register number of SCLKs after the falling edge of FS.
Register data values from 1 to 16 result in the default register value of zero.
2.14.1.~
Frame Sync (FS), Slave Mode
The frame-sync timing is generated externally, applied to FS, and controls the ADC and DAC timing (see
Section 2.15.4, Free-Run Mode). The external frame-sync width must be a minimum of one shift clock to
be recognized and can be as long as 16 shift clocks.
2.14.1.4 Frame-Sync Delayed (FSD), Slave Mode
This output is fed from the master to the first slave and the first slave FSD output to the second and so on
down the chain. The FSD timing sequence in the slave mode is as follows:
1.
If the FSD register data is 0, then FSD goes low after FS goes low (see Figure 4-5).
2.
When the FSD register data is greater than 16, FSD goes low on a rising edge of SCLK that is
the FSD register number of SCLKs after the falling edge of FS.
Data values from 1 to 16 are constrained because the data transfer requires 16 clock periods.
2.14.2 Data Out (DOUT)
DOUT is placed in the high-impedance state on the 17th rising edge of SCLK (internal or external) after the
falling edge of frame sync. In the primary communication, the data word is the ADC conversion result. In
the secondary communication, the data is the register-read results when requested by the read/write (RIW)
bit with the eight MSBs setto zero (see the Serial Communications section). If no register read is requested,
the secondary word is all zeroes.
2.14.2.1 Data Out, Master Mode
In the master mode, DOUT is taken from the high-impedance state by the falling edge of frame sync. The
most significant data bit then appears on DOUT.
2.14.2.2 Data Out, Slave Mode
In the slave mode, DOUT is taken from the high-impedance state by the falling edge of the external frame
sync or the rising edge of the external SCLK, whichever occurs first (see Figure 4-7). The falling edge of
frame sync can occur ±1/4 SCLK period around the SCLK rising edge (see Figure 4-3). The most
significant data bit then appears on DOUT.
2.14.3 Data In (DIN)
In the primary communication, the data word is the digital input signal to the DAC channel. In the secondary
comrrwnication, the data is the control and configuration data to set up the device for a particular function
(see Section 2.16, Serial Communications).
2.14.4 Hardware Program Terminals (FC1 and FCO)
These inputs provide for hardware programming requests for secondary communication or phase
adjustment. These inputs work in conjunction with the control bits D01 and DOO of the primary data word
or control bits DS15 and DS14 of the secondary data word. The data on FC1 and FCO are latched on the
rising edge of the next internally generated primary or secondary frame-sync interval. These inputs should
be tied low if not used (see Section 2.17, Request for Secondary Serial Communication and Table 2-3).
7-215
2.14.5
Midpoint Voltages (ACC VMIO and CAC VMIO)
Since the device operates at a single-supply voltage, two midpoint voltages are generated for internal signal
processing. AOC VMID is used for the AOC channel reference, and OAC VMID is used for the OAC channel
reference. Two references are used to minimize channel-to-channel noise and crosstalk. AOC VMID and
OAC VMID must be buffered if used as a reference for external signal processing.
2.15 Device Functions
2.15.1
Phase Adjustment
In some applications, such as modems, the device sampling period may require an adjustment to
synchronize with the incoming bit stream to improve the signal-to-noise ratio. The TLC320AC02 can adjust
the sampling period through the use of the A' register and the control bits.
2.15.1.1 Phase-Adjustment Control
A phase adjustment is a programmed variation in the sampling period .. A sampiing period is adjusted
according to the data value in the A' register, and the phase adjustment is that number of master clocks
(MCLK). An adjustment is made during device operation with data bits 001 and 000 in the primary
communication, with data bits OS15 and OS14 in the secondary word or in combination with the hardware
pins FC1 and FCO (see Table 2-3). This adjustment request is latched on the rising edge ofthe next internal
frame-sync interval and is only valid for the next sampling period. To repeat the phase adjustment, another
phase request must be initiated.
2.15.1.2 Use of the A' Register for Phase Adjustment
The A' register value is used to make slight timing adjustments to the sampling period. The sampling period
increases or decreases according to the sign of the programmed A' register value and the state of data bits
001 and 000 in the primary data word.
The general equation for the conversion frequency is given as:
f = conversion frequency =
MCLK
s
(2 x A register value x B register value) ± (A' register value)
Therefore, if A' =0, the device conversion (sampling) frequency and period is constant.
If a nonzero A' value is programmed, the sampling frequency and period responds as shown in Table 2-2.
Table 2-2. Sampling Variation With A'
SIGN OF THE A' REGISTER VALUE
D01
DOO
PLUS VALUE
(+)
NEGATIVE VALUE
(-)
0
1
(increase command)
Frequency decreases,
period increases
Frequency increases,
period decreases
1
0
(decrease command)
Frequency increases,
period decreases
Frequency decreases,
period increases
An adjustment to the sampling period, which must be requested through 001 and 000 of the primar~ data
word to DIN, is valid for the following sampling period only. If the adjustment is required for the subsequent
sampling period, it must be requested again through 001 and 000 of the primary data word. For each
request, only the sampling period occurring immediately after the primary data word request is affected.
7-216
The amount of time shift in the entire sampling period (1/f8 ) is as follows:
If the sampling period is set to 125 J.LS (8 kHz), the. A' register is loaded with decimal 10 and the TLC320AC02
master clock frequency is 10.386 MHz. The amount of time each sampling period is increased or decreased,
when requested, is:
Time shift = (A' register value) x (MCLK period)
The device changes the entire sampling period by only the MCLK period times the A' register value.
Change in sampling period = contents of A' register x master clock period
= lOx 96.45 ns = 964 ns (less than 1% of the sampling period)
The sampling period changes by 964.5 ns each time the phase adjustment is requested by the primary data
word (i.e., once per sampling period).
It is evident then that the change in sampling period is very small compared to the sampling period. To
observe this effect over a long period of time (> sampling period), this change must be continuously
requested by the primary data word. If the adjustment is not requested again, the sampling period changes
only once and it may appear that there was no execution of the command. This is especially true when bench
testing the device. Automatic test equipment can test for results within a single sampling period.
Internally, the A' register value only affects one cycle (period) of the A counter. The A and A' values are
additive, but only for one A-counter period. The A counter begins the first count at the default or programmed
A-register value and counts down to the A'-register value. As the A' value increases or decreases, the first
clock cycle from the A counter is lengthened or shortened. The initial A-counter period is the only counter
period affected by the A' register such that only this single period is increased or decreased.
2;15.2
Analog Loopback
This function allows the circuit to be tested remotely. In loopback, OUT+ and OUT-are internally connected
to IN + and IN-. The OAC data bits 015 to 002 that are applied to OIN can be compared with the AOC output
data bits 015 to 002 at OOUT. There are some differences due to the AOC ,and OAC channel offset. The
loopback function is implemented by setting OSOl and OSOO to zero in control register 5 (see Section 2.19,
Secondary Serial Communications).
2.15.3
16-Bit Mode
In the 16-bit mode, the device ignores the last two control bits (001 and 000) of the primary word and
requests continual secondary communications to occur. By ignoring the last two primary communication
bits, compatibility with existing 16-bit software can be maintained. This function is implemented by setting
bit OS03 to one in register 6. To return to normal operation, OS03 must be reprogrammed to zero.
2.15.4
Free-Run Mode
With the free-run bit set In register 6, the external shift clock and frame sync control only the data transfer.
The AOC and OAC timing are controlled by the A and B register values, and the phase-shift adjustment must
be done as if the device is in stand-alone mode (by the software or state of FC1 and FCO).
Phase adjustment cannot be made by adjustment of the frame-sync timing. The external frame sync must
occur within 1/2 FCLK period of the internal frame sync (FCLK as determined by the values of the A and
B registers).
If the external frame sync occurs simultaneously with the internal load, the data-transfer request by the
external frame sync takes precedence over the internal load command. The latching of the AOC conversion
data in the output register is inhibited until the current 16 bits are shifted out of the register by the shift clock.
2.15.5
Force Secondary Communication
With bit 2 in register 6 set to 1, secondary communication is requested continuously. It overrides all software
and hardware requests concerning secondary communication. Phase shifting, however, can still be
performed with the software and hardware.
7-217
2.15.6
Enable Analog Input Summing
By setting bits 0501 and 0500 to 11 in register 5, the normal analog input voltage is summed with the
auxiliary input voltage. The gain for the analog input amplifier is set by data bits 0503 and 0502 in register 4.
2.15.7
DAC Channel (slo x)/x Error Correction
The (sin x)/x compensation filter is designed for zero (sin x)/x error using a B-register value of 15. 5ince the
filter cannot be removed from the signal path, operation using another B-register value results in an error
in the reconstructed analog output. The error is given by the following equation. Any error compensation
needed by a given application can be performed in the software.
sin (2nXAXB x f)
f MCLK
OAC channel frequency response error = 20 x 10910
--------X~
sin
(7~~~: x f)
where:
f
fMCLK
A
B
=
=
=
=
the frequency of interest
the TLC320AC02 master clock frequency
the A-register value
the B-register value
and the arguments of the sin functions are in radians.
2.16 Serial Communications
2.16.1 Stand-Alone and Master-Mode Word Sequence and Information Content During
Primary and Secondary Communications
For the stand-alone and master modes, the sequ~f.lce in Figure 2-2 shows the relationship between the
primary and secondary communications interval, the data content into DIN, and the data content from
OOUT.
The TLC320AC02 can provide a phase-shift command or the next secondary communications interval by
decoding 1) the programmed state of the FC1 and FCO inputs and the 001 and 000 data bits in the primary
data word or2) the state ofthe FC1 and FCO inputs and the 0515 and OS14 data bits in the secondary data
word (see Table 2-3). If OS13 (the RIW bit) is the default value of zero, all 16 bits from OOUT are 0 during
secondary communication. However, when the R/W bit is setto one in the secondary communication control
word, the secondary transmission from OOUT still contains Os in the eight M5Bs. The lower order eight bits
contain the data of the register currently being addressed. This function provides register status information
for the host.
7-218
\..
[ (B register)l2] FCLK periodst - - - .
I
Primary Frame Sync
(16 SCLKs long)
Secondary Frame Sync
(16 SCLKs long)
2s-Complement ADC Output
(14 bits plus 00 for the two LSBs)
16 Bits All Os, Except When In
Read Mode (then least significant
8 bits are register data)
2s-Complement Input for the DAC
Channel (14 bits plus two
function bits). If the 2 LSBs Are
Set to 1, Secondary Frame Sync Is
Generated by the TLC320AC02
Input Data for the Internal Registers
(16 bits containing control,
address, and data Information)
I
I
t The time between the primary and secondary frame sync is the time equal to FCLK period multiplied by the B-register
contents. The time interval is rounded to the nearest shift clock. The secondary frame-sync signal goes from high to
low on the next shift clock low-to-high transition after (B register/2) filter clock periods.
Figure 2-2. Master and Stand-Alone Functional Sequence
2.16.2 Slave- and Codec-Mode Word Sequence and Information Content During
Primary and Secondary Communications
For the slave and codec modes, the sequence is basically the same as the stand-alone and master modes
with the exception that the frame sync and the shift clock are generated and controlled externally as shown
in Figure 2-3. For the codec mode, the frame-sync pulse width needs to be a minimum of one shift clock
long. The timing relationship between the frame sync and shift clock is shown in the timing diagrams. Phase
shifting is usually not required in the slave or codec mode because the frame-sync timing can be adjusted
externally if required.
-+I
1.-
1 SCLK Minimum
FilJ _i_i_t_t_J_J
--+I
L1_f_J_J_J_J_J
Primary Frame Sync
DOUT
2s-Complement ADC Output
(14 bits plus 00 for the 2 LSBs)
2s-Complement Input for the DAC
Channel (14 bits plus two
I function bits)
I
j+-:-1 SClK Minimum
Secondary Frame Sync
....._ - _ . . . . . 1
16 Bits, All Os, Except When In
Read Mode (then least significant
8 blts.are register data)
Input Data for the Internal
Registers (16 bits containing
I control, address, and data
I Information)
....._ _ _.....1
NOTE: The time between the primary and secondary frame syncs is determined by the application; however, enough
time must be provided so that the host can execute the required number of software instructions in the time
between the end of the primary data transfer (rising edge of the primary frame-sync interval) and the falling edge
of the secondary frame sync (start of secondary communications).
,
Figure 2-3. Slave and Codec Functional Sequence
7-219
2.17 Request for Secondary Serial Communication and Phase Shift
The following paragraphs describe a request for secondary serial communication and phase shift using
hardware control inputs FC1 and FCO, primary data bits 001 and 000, and secondary data bits OS15 and
OS14.
2.17.1
Initiating a Request
Combinations of FC1 and FCO input conditions, bits 001 and 000 in the primary serial data word, FC1 and
FCO, and bits OS 15 and OS 14 in the secondary serial data word can be used to initiate a secondary serial
communication or request a phase shift according to the following rules (see Table 2-3).
1.
Primary word phase shifts can be requested by either the hardware or software if the other set
of signals are 11 or 00. If both hardware and software request phase shifts, the software request
is performed.
2.
Secondary words can be requested by either the software or hardware at the same time that the
other set of signals is requesting a phase ·shift.
3.
Hardware inputs FC1 and FCO are ignored during the secondary word unless OS15 and OS14
are 11. If OS15 and OS14 are 01 or 10, the corresponding phase shift is performed. If OS15 and
OS14 are 00, no phase shift is performed even if the hardware requests a phase shift.
2.17.2 Normal Combinations of Control
The normal combinations of control are as follows:
1.
Use 001 and 000 and OS15 and OS14 to request phase shifts and secondary words by holding
FC1 and FCO to 00
2.
Use FC1 and FCO exclusively to request phase shifts and secondary words by holding 001 and
000 to 00 and OS15 and OS14 to 11
3.
Use 001 and 000 only to request secondary words and FC1 and FCO to perform phase shifts
once per period by holding OS1.5 and OS14 to 00
2.17.3 Additional Control Options
Additional control options are unusual and rarely needed or used; however, they are as follows:
1.
Use 001 and 000 only to request secondary words and FC1 and FCO to perform phase shifts
.
twice per period by holding OS15 and OS14 to 11
2.
Use FC1 and FCO exclusively to request secondary words and 001 and 000 and OS 15 and OS14
to perform phase shifts twice per period
3.
Use FC1 and FCO to perform the phase shift after the primary word and OS15 and OS14 to
perform a phase shift after the secondary word by holding 001 and 000 to 11
7-220
Table 2-3. Software and Hardware Requests for
Secondary Serial-Communication and Phase-Shift Truth Table
WITHIN PRIMARY
OR SECONDARY
DATA WORD
Primary
Secondary
CONTROL
BITS
HARDWARE
TERMINALS
PHASE-SHIFT
ADJUSTMENT
(S88 Section 2.15.1)
D01
DOO
FC1
FCO
EARLIER
LATER
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
0
1
1
1
1
DS15
DS14
FC1
FCO
0
0
1
0
EARLIER
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
0
0
0
SECONDARY
REQUEST
(see Note 1)
0
0
0
1
LATER
0
0
0
0
1
1
1
1
No request can be made for
secondary communication
within the secondary word.
0
0
0
1
0
1
1
0
0
0
0
1
0
1
0
0
1
1
1
0
1
1
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0,
1
1
1
1
0
NOTE 1: The 0 state indicates that a secondary communication is not being requested. The 1 state indicates that a
secondary communication is being requested.
1
1
1
1
2.18 Primary Serial Communications
Primary serial communications transfer the 14-bit DAC input plus two control bits (001 and 000) to DIN of
the TLC320AC02.They simultaneously transfer the 14-bit ADC conversion result from DOUT to the
processor. The two LSBs are set to zero in the ADC result.
7-221
2.18.1
Primary Serial Communications Data Format
~----------------~------~.v~----------------------~
14-bit OAC Conversion Result
CQntrol Bits
2s-Complement Fotmatt
t Since the supply voltage is single ended, the reference for 2s-complement format is AOC VMIO. Voltages above·
this reference have a 0 as the MSB, and voltages below this reference have a 1 as the MSB.
During primary serial communications, if 001 and 000 are both high in the OAC data word to DIN, a
subsequent 16 bits of control information is r~eived by the device at DIN during a secondary serialcommunication interval. This secondary serial-communication interval begins at 1/2 the programmed
conversion time if the B register data value is even or 1/2 the programmed value minus one FCLK if the B
register data value is odd. The time between primary and secondary serial communication is measured from
the falling edge of the primary frame sync to the falling edge of the secondary frame sync (see Section 2.19,
Secondary Serial Communications for function and format of control words).
2.18.2 Data Format From DOUT During Primary Serial Communications
~------------------------~v~----------------------~
14-Bit AOC Conversion Result
2s-Complement Format
015 is the Sign Bit
001 - 0
000=0
2.19 Secondary Serial Communications
2.19.1 Data Format to DIN During Secondary Serial Communications
There are nine 16-bit configuration and control registers numbered from zero to eight. All register data
contents are represented in 2s-complement format. The general format of the commands during secondary
serial communications is as follows.
Register Address
5 bits
Register Data Value
8 bits
All control register words are latched in the register and valid on the 16th falling edge of SCLK.
2.19.2 Control Data-Bit Function in Secondary Serial Communication
2.19.2.1 OS15 and 0814
In the secondary data word, bits OS15 and OS14 perform the same control function as the primary control
bits 001 and 000 do in the primary data word.
OS1510S14 OS13 OS12 1 OS11 1 OS10 1OS091 OS08 OS071 osoel OS051 OS041 OSP~ 1OS021 OS011 OSOO
Control Bits
RfW
Register Address
Register Data
Hardware terminals FC1 and FCO are valid inputs when OS 15 and OS14 are both high, and they are ignored
for all other conditions.
7....222
2.19.2.2
0813 (R/W Bit)
Reset and power-up procedures set this bit to a zero, placing the device in the write mode. When this bit
is set to one, however, the previous data content of the register being addressed is read out to the host from
OOUT as the least significant eight bits of the 16-bit secondary word. The first eight bits remain set to zero.
Reading the data out is nondestructive, and the contents of the register remain unchanged.
A. Write Mode (OS 13 = 0)
. Data In. The data word to DIN has the following general format in the write mode.
081510814 0813 081210811108101080910808 08071 08061 08051 08041 08031 08021 08011 0800
Control Bits
Register Address
0
Register Oata
Data Out. The shift-clock shifts out all zeros as the pattern to the host from OOUT.
0815 0814 0813 0812 0811 0810 0809 0808 0807 0806 0805 0804 0803 0802 0801 0800
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B. Read Mode (OS13 = 1)
Data In. The data word to DIN has the following format to allow a register read. Phase shifts can
also be done in the read mode.
081510814 0813 081210811108101080910808 08071080e10805(0804i0803108021080110800
Control Bits
Register Address
1
Ignored
Data Out. The shift-clock clocks out the data of the register addressed from OOUT in the read mode in
the eight L S B s . ·
.
0815 0814 0813 0812 0811 0810 0809 0808 08071080el 08051 0804108031 08021 080110800
0
0
0
0
0
0
0
Register Oata
0
2.20 Internal Register Format
2.20.1
Pseudo-Register 0 (No-Op Address)
This address represents a no-operation command. No register I/O operation takes place, so the device can
receive secondary commands for phase adjustment without reprogramming any register. A read of the
no-op is zero. The format of the command word is as follows.
081510814 0813 0812 0811 0810 0809 0808 0807 080e 0805 0804 0803 0802 0801 0800
Control Bits
2.20.2
X
0
0
0
0
0
X
X
X
X
X
X
X
X
Register 1 (A Register)
The following command loads OS07 (MSB) - OSOO into the A register.
081510814 0813 0812 0811 0810 0809 0808 08071 080el 08051 08041 08031 08021 08011 0800
Control Bits R/W
0
0
0
0
1
Register Oata
The data in OS07 - OSOO determines the division of the master clock to produce the internal FCLK.
FCLK frequency = MCLKI(A register contents x 2)
7-223
The default value of the A-register data is decimal 18 as shown below.
0807 0806 0805 0804 0803 0802 0801 0800
0
2.20.3
0
0
1
0
0
1
0
Register 2 (8 Register)
The following command loads 0507 (M5B) - 0500 into the B register.
081510814 0813 0812 0811 0810 0809 0808 08071 08061 08051 08041 08031 08021 08011 0800
Control Bits
R/W
0
0
'0
1
Register Oata
0
The data in 0507 - 0500 controls the division of FCLK to generate the conversion clock.
Conversion frequency
= FCLK/(B register contents)
MCLK
2 x A register contents x B register contents
The default value of the B-register data is decimal 18 as shown below.
0807 0806 0805 0804 0803 0802 0801 0800
0
2.20.4
0
0
1
0
0
1
0
Register 3 (A' Register)
The following command contains the A'-register address and loads 0507(M5B) - 0500 into the A' register.
081510814 0813 0812 0811 0810 0809 0808 08071 0806 10805108041 0803 10802 10801 1OSOO
Control Bits
R/W
0
0
0
1
Register Oata
1
The data in 0507 - 0500 is in 2s-complement format and controls the number of master clock periods that
the sampling time is shifted.
The default value of the A'-register data is 0 as shown below.
0807 0806 0805 0804 0803 0802 0801 0800
0
7-224
0
0
0
0
0
0
0
2.20.5
Register 4 (Amplifier Gain-Select Register)
The following command contains the amplifier gain-select register address with selection code for the
monitor output (0805-0804), analog input (0803-0802), and analog output (0801-0800)
programmable gains.
081510814 0813 0812 0811 0810 0809 0808 0807 0806 0805 0804 0803 0802 0801 0800
Control Bits
RIW
0
0
1
0
0
X
X
....
....
Monitor output gain = squelch
Monitor output gain =0 dB
Monitor output gain = -8 dB
Monitor output gain .. -18 dB
Analog
Analog
Analog
Analog
*
*
0
0
1
1
0
1
0
1
...
....
input gain .. squelch
input gain - 0 dB
input gain .. 6 dB
input gain =12 dB
Analog output gain =squelch
Analog output gain .. 0 dB
Analog output gain .. - 6 dB
Analog output gain =-12 dB
*
*
0
0
1
1
0
1
0
1
...
....
*
*
0
0
1
1
0
1
0
1
The default value ofthe monitor output gain is squelch, which corresponds to data bits 0805 and 0804 equal
to 00 (binary).
The default value of the analog input gain is 0 dB, which corresponds to data bits 0803 and 0802 equal
to 01 (binary).
The default value of the analog output gain is 0 dB, which corre~ponds to data bits 0801 and 0800 equal
to 01 (binary).
The default data value is shown below.
0807 0806 0805 0804 0803 0802 0801 0800
0
2.20.6
0
0
0
0
1
0
1
Register 5 (Analog Configuration Register)
The following command is used to load the analog configuration register with the individual bit functions
described below.
081510814 0813 0812 0811 0810 0809 0808 0807 0806 0805 OS04 0803 0802 0801 OSOO
Control Bits
RIW
0
0
1
0
1
Must be set to 0
High-pass filter disabled
High-pass filter enabled
Analog loopback enabled
Enables IN+ and IN- (disables AUXIN+ and AUXIN-)
Enables AUXIN+ and AUXIN- (disables IN+ and IN-)
Enable analog input summing
X
X
X
X
..
*
*
*
*
0
0
0
.
• ..
..
1
0
..
..
0
1
1
0
1
1
The default value of the high-pass-filter enable bit is zero, which places the high-pass filter in the signal path.
The default values of 0801 and 0800 are zero and one, which enables IN + and IN-.
7-225
The power-up and reset conditions areas shown below.
0503
0
0502 0501 0500
0
0
1
In the read mode, eight bits are read but the four LSBs are repeated as the four MSBs.
2.20.7
Register 6 (Digital Configuration Register)
The following command is used to load the digital configuration register with the individual bit functions
described below.
051510814 0513 0512 0511 0510
Control Bits
RIW
0
0
1
0509 0508 0507 0506 0505 0504 0503 0502. 0501 0500
1
0
X
X
*
••
AOC and OAC conversion free run
Inactive
F50 output disable
Enable
*
*
*
*
*
1
0
••
••
••
1
0
16-Bit mode, ignore primary L8Bs
Normal operation
1
0
Force secondary communications
Normal operation
50ftware reset
(upon reset, this bit is automatically reset to 0)
Inactive reset
1
0
•
• •
•
1
0
5oftw~wer-down
active (automatically reset to 0
after PWR OWN is cycled high to low and back to high)
Power-down function external
(uses PWR OWN)
1
0
The default value of OS07 - OSOO is zero, as shown below.
0507 0506 0505 0504 0503 0502 0501 0500
0
2.20.8
0
0
0
0
0
0
0
Register 7 (Frame-Sync Delay Register)
The following command contains the frame-sync delay (FSO) register. address and loads OS07
(MSB)-OSOO into the FSO register. The data byte (OS01-0S00) determines the number of SCLKs
between FS and the delayed frame-sync signal, FSO. The minimum data value for this register is
decimal 18.
'
051510514 0513 0512 0511 0510 0509 0808 05071 05061 05051 05041 05031 05021 05011 0500
Control Bits RIW
0
0
1
1
1
Register Oata
The default value of OS07 - OSOO is zero, as shown below.
0807 0506 0505 0504 0503 0502 0501 0500
0
0
0
0
0
0
0
0
When using a slave device, register 7 must be the last register programmed.
7-226
2.20.9 Register 8 (Frame-Sync Number Register)
The following command contains the frame-sync number (F8N) register address and loads 0807
(M8B) - 0800 into the F8N register. The data byte determines the number of frame-sync signals generated
by the TLC320AC02.
081510814 0813 0812 0811 0810 0809 0808 08071 08061 08051 08041 08031 08021 08011 0800
Control Bits R/W
0
1
0
0
Register Data
0
The default value of 0807-0800 is one, as shown below.
0807 0806 0805 0804 0803 0802 0801 0800
0
0
0
0
0
0
0
1
7-227
7-228
3
3.1
Specifications
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)t
Supply voltage range, DGTL Voo (see Notes 1 and 2) ............... -0.3 V to 6.5 V
Supply voltage range, DAC Voo (see Notes 1 and 2) ................ -0.3 V to 6.5 V
Supply voltage range, ADC Voo (see Notes 1 and 2) ................ -0.3 V to 6.5 V
Differential supply voltage range, DGTL Voo to DAC Voo ............ -0.3 V to 6.5 V
Differential supply voltage range, all positive supply voltages to
ADC GND, DAC GND, DGTL GND, SUBS .................... -0.3 V to 6.5 V
Output voltage range, DOUT ......................... -0.3 V to DGTL Voo + 0.3 V
Input voltage range, DIN ............................. -0.3 V to DGTL Voo + 0.3 V
Ground voltage range, ADC GND, DAC GND,
DGTL GND, SUBS ............................ -0.3 V to DGTL Voo + 0.3 V
Operating free-air temperature range: TLC320AC02C ................ O°C to 70°C
TLC320AC021 ............... -40°C to 85°C
Storage temperature range ...................................... -40°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .............. 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for
extended periods may affect device reliability.
3.2
Recommended Operating Conditions (see Note 2)
VDD
Positive supply voltage
MIN
NOM
MAX
4.5
5
5.5
V
0.1
V
Steady-state differential voltage between any two supplies
UNIT
VIH
High-level digital input voltage
VIL
Low-level digital input voltage
0.8
V
Load current from ADC VMID and DAC
100
jJA
15
MHz
10
Conversion time for the ADC and DAC channels
fMCLK
VID(PP)
RL
10 FCLK. periods
Master clock frequency
10.368
Analog input voltage (differential, peak to peak)
I Differential output load resistance
I Single-ended to buffered DAC VMID voltage load resistance
Operating free-air temperature
V
2.2
TLC320AC02C
V
6
600
n
300
0
70
°C
TLC320AC021
-40
85
NOTES: 1. Voltage values for DGTL VDD are With respect to DGTL GND, voltage values for DAC VDD are With respect
toDACGND,andvoltagevaluesforADCVDDarewithrespecttoADCGND.For the subsequent electrical,
operating, and timing specifications, the symbol VDD is used to denote all positive supplies. DAC GND,
ADC GND, DGTL GND, and SUBS are at 0 V unless otherwise specified.
2. To avoid possible damage to these CMOS devices and associated operating parameters, the sequence
below should be followed when applying power:
(1) Connect SUBS, DGTL GND, ADC GND, and DAC GND to ground.
(2) Connect voltages ADC VDD, and DAC VDD.
(3) Connect voltage DGTL VDD.
(4) Connect the input signals.
When removing power, follow the steps above in reverse order.
TA
7-229
3.3
Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, MCLK = 5.184 MHz, VOO = 5 V, Outputs Unloaded,
Total Device
PARAMETER
TEST CON.DITIONS
Supply
current
100
MIN
PWR OWN = 1 and clock signals
present
UNIT
20
22
mA
1
2
mA
Power
dissipation
100
mW
PWR OWN = 0 after 500 j1S and
clock signals present
5
mW
Software power down, (bit 000,
register 6 sat to 1)
15
20
mW
AOCVMIO
No load
AOCVOO/2
-0.1
AOC V 00/2 ,
+0.1
V
OACVMIO
No load
OACVOO/2
-0.1
OACVOO/2
+0.1
V
3.4
Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, VOO= 5 V, Digital 110 Terminals (DIN, DOUT, EOC,
FCO, FC1, FS, FSD, MCLK, MIS, SCLK)
PARAMETER
VOH
t
MAX
PWR OWN = 0 after 500 j1S and
clock signals present
PWR OWN = 1 and clock signals
present
Po
TYPt
High-level output voltage
TEST CONDITIONS
IOH =-1.6 mA
MIN
TYPt
MAX
2.4
UNIT
V
VOL
Low-level output voltage
IOL= 1.6mA
0.4
V
IIH
High-level input current, any digital input
VI ... 2.2 V to OGTL VOO
10
IlL
Low-level input current, any digital input
VI ... 0 V to 0.8 V
10
!!A
!!A
Ci
.Input capacitance
5
pF
Co
Output capacitance
5
pF
All typical values are at VOO = 5 V and TA = 25°C ..
3.5
3.5.1
Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, Voo = 5 V, ADC and DAC Channels
AOC Channel Filter Transfer Function, FCLK
PARAMETER
=144 kHz, fs =8 kHz
TEST CONDITIONS
MIN
Gain relative to gain at fi ... 1020 Hz (see Note 3)
MAX
UNIT
-~
fi =50 Hz
fi = 200 Hz
-1.8
fi ... 300 Hz to 3 kHz
-0.2
-0.2
0.2
fi'" 3.3 kHz
-0.35
0.03
fi = 3.4 kHz
-1
-0.1
fi=4kHz
-14
fi ~4.6 kHz
-32
dB
NOTE 3: The differential analog input signals are sine waves at 6 V peak to peak. The reference gain is at 1020 Hz.
7-230
3.5.2
ADC Channel Input, Voo
Noted)
=5 V, Input Amplifier Gain =0 dB (Unless Otherwise
PARAMETER
TEST CONDITIONS
VI(PP)
Peak-to-peak input voltage (see Note 4)
CMRR
Common-mode rejection ratio at IN+. IN-.
AUX IN+. AUX IN- (see Note 5)
ri
Input resistance at IN+. IN-. AUX IN+.
AUXIN-
ADC converter offset error
MIN
MAX
UNIT
3
V
Differential
6
V
Band-pass filter selected
10
DS03. DS02 = 0 in
register 4
Squelch
TYPt
Single ended
30
mV
55
dB
100
kg
60
dB
t
All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 4. The differential range corresponds to the full-scale digital output.
5. Common-mode rejection ratio is the ratio of the ADC converter offset error with no signal and the ADC
converter offset error with a common-mode nonzero signal applied to either IN + and IN - together or AUX
IN + and AUX IN- together.
3.5.3
ADC Channel Signal-to-Distortion Ratio, Voo = 5 V, fs
Otherwise Noted)
PARAMETER
TEST CONDITIONS
ADC channel signal-todistortion ratio (see Note 6)
= 8 kHz (Unless
Ay= OdB
Ay=6dB
Ay = 12dB
MIN
MIN
MIN
MAX
VI = -6 dB to -1 dB
64
-
VI =-12 dB to-6 dB
59
64
MAX
MAX
UNIT
-
VI'" -18 dB to -12 dB
56
59
64
VI" -24 dB to -18 dB
50
56
59
VI .. -30 dB to -24 dB
44
50
56
VI = -36 dB to -30 dB
38
44
50
VI = -42 dB to -36 dB
32
38
44
VI = -48 dB to -42 dB
26
32
38
dB
NOTE 6: The analog input test signal is a 102D-Hz sine wave with 0 dB ,.; 6 V peak to peak as the reference level for
the analog input signal.
3.5.4
DAC Channel Filter Transfer Function, FCLK
PARAMETER
=144 kHz, fs =9.6 kHz, VDD =5 V
TEST CONDITIONS
MIN
fi = 200 Hz
..
-0.5
UNIT
0.2
-0.2
0.2
fi'" 3.3 kHz
-0.35
0.03
fi = 3.4 kHz
-1
-0.1
fi = 300 Hz to 3 kHz
Gain relative to gain at fi = 1020 Hz (see Note 7)
MAX
0.15
fi<200 Hz
fi = 4 kHz
-14
fi ~ 4.6 kHz
-32
dB
NOTE 7: The Input signal IS the digital equivalent of a 1020-Hz slOe wave (digital full scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak.
7-231
3.5.5
,
CAC Channel Slgnal-to-Dlstortlon Ratio, Voo
Otherwise Noted)
PARAMETER
DAC channel signal-to
distortion ratio (see Note 8)
TEST CONDITIONS
=5 V, fs =8 kHz (Unless'
Av=OdB
MIN
MAX
Av=-6dB
MIN
MAX
AV=-12dB
MIN
MAX
UNIT
-
VO--6dBtoOdB
64
-
VO=-12dBto-6dB
59
64
VO--18dBto-12dB
56
59
64
Vo --24 dB to-18 dB
50
56
59
Vo - -30 dB to -24 dB
44
50
56
Vo .. -36 dB to -30 dB
38
44
50
VO- -42 dB to -36 dB
32
38
44
Vo .. -48 dB to -42 dB
26
32
38
' dB
NOTE 8: The input signal. VI. is the digital equivalent of a 1020-Hz sine wave (full-scale analog output atfull-scale digital
input = 0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The
load impedance for the DAC output buffer is 600 a from OUT + to OUT -.
3.5.6
System Distortion, VOD
Noted)
PARAMETER
Second harmonic
.ADC channel
attenuation
DACchannel
attenuation
Third harmonic and
higher harmonics
Second harmonic
=5 V, fs =8 kHz, FCLK =144 kHz (Unless Otherwise
.
TEST CONDITIONS
Differential input (see Note 9)
64
64
Single-ended output
(buffered DAC VMID) (see Note 10)
UNIT
82
77
82
64
82
77
64
77
Single-ended output (see Note 10)
Differential output (see Note 10)
MAX
77
Single-ended input (see Note 9)
Differential input (see Note 9)
TYPt
82
Single-ended input (see Note 9)
Differential output (see Note 10)
Third harmonic and
higher harmonics
MIN
dB
t All typical values are at VDD" 5 V and TA" 25°C.
NOTES: 9. The inpl.lt signal is a 1020-Hz sine wave for the ADC channel. Harmonic distortion is defined for an input
level of -1 dB.
10. The input Signal is the digital equivalent of a 102O-Hz sine wave (digital full scale .. 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the
DAC output buffer is 600 a from OUT + to OUT -. Harmonic distortion is specified tor a signal input level
otO dB.
3.5.7
Noise, Low-Pass and Band-Pass Switched-Capacitor Filters Included,
Voo =5 V (Unless Otherwise Noted)
PARAMETER
MIN
Inputs tied to ADC VMID
fs =8 kHz, FCLK = 144 kHz,
(see Note 11)
ADC idle channel noise
DAC idle channel
noise
TEST CONDITIONS
Broad-band noise
Noise (0 to 7.2 kHz)
Noise (0 to 3.6 kHz)
DIN INPUT =00000000000000
fs .. 8 kHz, FCLK .. 144 kHz,
(see Note 12)
TYPt
MAX
180
300
180
300
180
300
180
300
UNIT
I1Vrms
t All typical values are at VDD" 5 V and TA" 25°C.
NOTES: 11. The ADC channel noise is calculated by taking the RMS value of the digital output codes of the ADC
channel and converting to microvolts.
12. The DAC channel noise is measured differentially from OUT + to OUT-across 600 C.
3.5.8
Absolute Gain Error, VDO = 5 V, fs = 8 kHz (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
ADC channel absolute gain error
(see Note 13)
-1-dB input signal
TA = -40 to 85°C
±1
DAC channel absolute gain error
(see Note 14)
O-dB input signal,
RL=600C
TA = -40 to 65"C
±1
UNIT
dB
NOTES: 13. ADC absolute gain error is the variation in gain from the ideal gain over the specified input signal levels.
The gain is measured with a -1-dB, 1020-Hz sine wave. The -1-dB input signal allows for any positive gain
or offset error that may affect gain measurements at or close to O-dB input signal levels.
14. The DAC input Signal is the digital equivalent of a 1020-Hz sine wave (full-scale analog output at digital
full-scale input = 0 dB). The nominal differential DAC channel output voltage with this input condition is 6
V peak to peak. The load impedance for the DAC output buffer is 600 C from OUT + to OUT -.
3.5.9
Relative Gain and Dynamic Range, Voo
Noted)
PARAMETER
=5 V, fs =8 kHz (Unless Otherwise
TEST CONDITIONS
MIN
MAX
ADC channel relative gain tracking error
(see Note 15)
-48-dB to -1-dB input signal range
±0.2
DAC channel relative gain tracking error
(see Note 16)
-48-dB to O-dB input Signal range
RL(diff) = 600 C
±0.2
UNIT
dB
NOTES: 15. ADC gain tracking is the ratio of the measured gain at one ADC channel input level to the gain measured
at any other input level. The ADC channel input is a -1-dB 1020-Hz sine wave input signal. A -1-dB input
signal allows for any positive gain or offset error that may affect gain measurements at or close to O-dB ADC
input signal levels.
16. DAC gain tracking is the ratio of the measured gain at one DAC channel digital input level to the gain
measured at any other input level. The DAC channel input signal is the digital equivalent of a 1020-Hz sine
wave (digital full scale =0 dB). The nominal differential DAC channel output voltage with this input condition
is 6 V peak to peak. The load impedance for the DAC output buffer is 600 C from OUT + to OUT -.
7-233
3.5.10
Power-Supply Rejection, Voo
=5 V (Unless Otherwise Noted)(see Note 17),
PARAMETER
TEST CONDITIONS
ADCVDD
Supply-voltage rejection ratio, ADC channel
DACVDD
Supply-voltage rejection ratio, DAC channel
DGTL VDD Supply-voltage rejection ratio, ADC channel
DGTL VDD Supply-voltage rejection ratio, DAC channel
MIN
TYPt
fi=Ot030kHz
50
fi .. 30 to 50 kHz
,55
fi-Ot030kHz
40
fi .. 30 to 50 kHz
45
fi~Ot030kHz
50
fi .. 30 to 50 kHz
Single ended,
fi-Ot030kHz
55
MAX
UNIT
dB
40
fi = 30 to 50 kHz
45
Differential,
fi""Ot030kHz
40
fi = 30 to 50 kHz
45
tAli typical values are at VDD = 5 V and TA" 25°C.
NOTE 17: Power-supply rejection measurements are made with both the ADC and the DAC channels idle and a 200-mV
peak-ta-peak signal applied to the appropriate supply.
3.5.11
Crosstalk Attenuation, Voo
PARAMETER
ADC channel crosstalk attenuation
DAC channel crosstalk attenuation
=5 V (Unless Otherwise Noted)
TEST CONDITIONS
MIN
TYpt
PAC channel idle with
DIN .. 00000000000000,
ADC input .. 0 dB,
1020-Hz sine wave,
Gain .. 0 dB (see Note 18)
80
ADC channel idle with INP, INM,
AUX IN +, and AUX IN- at ADC VMID
80
DAC channel input = digital equivalent of
a 1020-Hz sine wave (see Note 19)
80
MAX
UNIT
dB
dB
t All typical values are at VDD =5 V and TAos 25°C.
NOTES: 18. The test Signal is a 1020-Hz sine wave with a 0 dB .. 6-V peak-ta-peak reference level for the analog input
signal.
19. The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale - 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the
DAe output buffer is 600 Q from OUT + to OUT -.
7-234
3.5.12
Monitor Output Characteristics, VDD
(see Note 20)
PARAMETER
=5 V (Unless Otherwise Noted)
TEST CONDITIONS
VO(PP)
Peak-to-peak ac output
voltage
Quiescent level .. ADC VMID
ZL .. 10 kO and 60 pF
VOO
Output offset voltage
No load, single ended
relative to ADC VMID
ro
DC output resistance
Voe
Output common-mode voltage
AV
Voltage gain (see Note 21)
MIN
1.3
Typf
MAX
1.5
5
V
10
O.4ADC
VDD
0.5ADC
VDD
0.6ADC
VDD
Gain .. OdB
-0.2
0
0.2
Gain2 .. -8dB
-8.2
-8
-7.8
Gain 3 =~18dB
-18.4
-18
-17.6
Squelch (see Note 22)
mV
C
50
No load
UNIT
V
dB
-60
t
All typical values are at VDD .. 5 V and TA" 25°C.
NOTES: 20. All monitor output tests are performed with a 10-kO load resistance.
21. Monitor gains are measured with a 1020-Hz, 6-V peak-ta-peak sine wave applied differentially between
IN + and IN -.The monitor output gains are nominally 0 dB, ~8 dB, and -18 dB relative to its input; however,
the output gains are -6 dB relative to IN+ and IN- or AUX IN+ and AUX IN-.
22. Squelch is measured differentially with respect to ADC VMID.
7-235
3.6
Timing Requirements and Specifications in Master Mode
3.6.1
Recommended Input Timing Requirements for Master Mode,
MIN
Voo =5'"
. NOM
MAX
UNIT
tr(MCLK)
Master clock rise time
5
ns
tf(MCLK)
Master clock fall time
5
ns
Master clock duty cycle
twCRESET>
(
RESET pulse duratio{l
tsuCDlN)
DIN setup time before SCLK low (see Figure 4-2)
th(DIN)
DIN hold time after SCLK high (see Figure 4-2)
3.6.2
40% . ...
60%
1 MCLK
25
ns
20
ns
Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, Voo 5 V (Unless Otherwise Noted) (see Note 23)
=
PARAMETER
tfCSCLK)
Shift clock fall time (see Figure 4-2)
trCSCLK)
Shift clock rise time (see Figure 4-2)
Shift clock duty cycle
MIN
TYPt
MAX
13
18
ns
18
ns
13
45%
UNIT
55%
Delay time from SCLK high to FSD low
(see Figures 4-2 and 4-4 and Note 24)
5
id(CH-FH)
Delay time from SCLK high to FS high (see Figure 4-2)
5
id(CH-DOUT)
Delay time from SCLK high to DOUT valid
(see Figures 4-2 and 4-7)
id(CH-DOUTZ)
Delay time from SCLKi to DOUT in high-impedance state
(see Figure 4-8)
20
ns
idCML-EL)
Delay time from MCLK low to EOC low (see Figure 4-9)
40
ns
idCML-EH)
Delay time froll) MCLK low to EOC high (see Figure 4-9) .
40
ns
tfCEU
EOC fall time (see Figure 4-9)
13
ns
tr(EH)
EOC rise time (see Figure 4-9)
13
ns
id(MH-CH)
Delay time from MCLK high to SCLK high
50
ns
idCMH-CL)
Delay time from MCLK high to SCLK low
50
ns
td(CH-FL)
20
ns
20
ns
20
ns
t All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 23. All timing specifications are valid with CL = 20 pF.
24. FSD occurs 1/2 shift-clock cycle ahead of FS when the device is operating in the master mode.
7-236
3.7
Timing Requirements and Specifications in Slave Mode and Codec
Emulation Mode
3.7.1
Recommended Input Timing Requirements for Slave Mode, Voo
=5 V
NOM
MIN
MAX
UNIT
tr(MCLK)
Master clock rise time
5
ns
tf(MCLK)
Master clock fall time
5
ns
Master clock duty cycle
40%
tw(RESETI
RESET pulse duration
1 MCLK
tsuCDIN)
DIN setup time before SCLK low (see Figure 4-3)
th(DIN)
DIN hold time after SCLK high (see Figure 4-3)
tsu(FL-CH)
Setup time from FS low to SCLK high
3.7.2
60%
20
ns
20
±SCLKl4
ns
ns
Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, Voo 5 V (Unless Otherwise Noted) (see Note 23)
=
PARAMETER
tc(SCLK)
Shift clock cycle time (see Figure 4-3)
tf(SCLK)
Shift clock fall time (see Figure 4-3)
tr(SCLK)
Shift clock rise time (see Figure 4-3)
Shift clock duty cycle
MIN
TYPt
MAX
125
UNIT
ns
45%
18
ns
18
ns
55%
~(CH-FDU
Delay time from SCLK high to FSD low (see Figure 4-6)
50
~(CH-FDH)
Delay time from SCLK high to FSD high
40
ns
ns
~(FL-FDL)
Delay time from FS low to FSD low (slave to slave)
(see Figure 4-5)
40
ns
~(CH-DOUT)
Delay time from SCLK high to DOUT valid
(see Figures 4-:-3 and 4-7)
40
ns
~(CH-DOUTZ)
Delay time from SCLKi to DOUT in high-impedance state
(see Figure 4-8)
20
ns
~(ML-EL)
Delay time from MCLK low to EOC low (see Figure 4-9)
40
ns
~(ML-EH)
Delay time from MCLK low to EOC high (see Figure 4-9)
40
ns
tf(EU
tr(EH) .
EOC fall time (see Figure 4-9)
13
ns
EOC rise time (see Figure 4-9)
13
ns
~(MH-CH)
Delay time from MCLK high to SCLK high
50
ns
~(MH-CL)
Delay time from MCLK high to SCLK low
50
ns
t All typical values are at VDD • 5 V and TA = 25°C.
NOTE 23: All timing specifications are valid with CL .. 20 pF.
7-237
7-238
4
Parameter Measurement Information
Rfb
R
IN+orAUXIN+----~~--~--~
R
IN-orAUXIN-----~~--~--~
+
Rfb
=
=
=
=
=
=
=
=
=
Rfb R for OS03 0 and OS02 1
Rfb 2R for OS03 1 and OS02 0
Rfb 4R for OS03 1 and OS02 1
R = 100 kn nominal
Figure 4-1. IN+ and IN- Gain-Control Circuitry
Table 4-1. Gain Control (Analog Input Signal Required for
Full-Scale Bipolar AID Conversion 28 Complement)t
INPUT CONFIGURATION
Oifferential configuration
Analog input .. IN + - IN= AUX IN+ - AUX IN-
Single-ended configuration§
Analog input = IN + - VMIO
=AUXIN+-VMIO
CONTROL REGISTER 4
OS03
OS02
0
0
1
0
1
1
0
1
ANALOG INPun
All
A/O CONVERSION
RESULT
Squelch
VIO =±3 V
±Full scale
VID=±1.5V
±Fullscale
VIO = ±O.75 V
±Full scale
Squelch
0
0
All
0
1
VI=±1.5V
±Halfscale
1
0
VI=±1.5V
±Full scale
1
±Full scale
VI =±0.75 V
1
tVOO '" 5 V
:j: VID = differential input voltage, VI .. input voltage referenced to AOC VMIO with IN - or AUX IN - connected to
AOC VMIO. In order to minimize distortion, it is recommended that the analog input not exceed 0.1 dB below full scale.
§ For single-ended inputs, the analog input voltage should not exceed the supply rails. All single-ended inputs should be
referenced to the internal reference voltage, AOC VMI[), for best common-mode performance.
7-239
---:
~
I+-
tf(SCLK}
tr(SCLK}
I
SCLK 2V
I
O.BV
- . : : - "'(CH-FL)
1
"'(CI>FH) - :v
:
L
Fst~~i____________I~~I________________________________-J~
O.BV~
1
1
X
-+--I
~ X
~ .014
oou11
tsu(OIN)
OIN~
!~. ~ tct(CH-OOUT)
X
014
~13
013
th(OIN)
1
14
012
X
011
~O<
02
X
012
X
011
~O<
02
X X
Master-M~de
Timing
.01
00
}-
~
tf(SCLK)
1
SCLK 2V
I
14 I~I
F~
X"--OO_·",,,}-
1
Figure 4-2. AIC Stand-Alone and
-1 ~
01
1
1
§
~!
~_~________~~~I__________________________-J·;-1
1
OOUT*
~
I: --+I
014
X
013
I!= tct(CH-OOUT)
X
012
X
1
OIN
tsU(OIN)~
1
014 ~ ~131
---®<
th(OIN)
14
011
~O<
02
X
01
X
00
}-
'
012
X
011
}-
~
Figure 4-3. AIC Slave and Codec Emulation Mode
t The time between falling edges of two primary FS signals is the conversion period.
:j: The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling
edge of the shift clock.
§ The high-to-Iow transition of FS must must occur within ±1/4 of a shift-clock period around the 2-Vlevel of the shift clock.
7-240
/
SCLK
\
1
1
1
1
1
1
'..
FSD
0.8>J.
14
r
\
2.4/1
.,,
SCLK perlodl2
1
,
.1
tct(CH-FL)
0.8~
FS
NOTE: Timing shown is for the TLC320AC02 operating as the master or as a stand-alone device.
Figure 4 ...4. Master or Stand-Alone FS and FSD Timing
0.8 \V _ _ _ _ _ _ _ _ __
FS
\:~
I
FSD
.1
~
tct(FL-FDL)
----------0-.8-~~1_ _ _ _ _ _ ___
NOTE: Timing shown is for the TLC320AC02 operating in the slave mode (FS and SCLK signals generated extemally).
The programmed data value in the FSD register is O.
Figure 4-5. Slave FS to FSD Timing
SCLK
__
2'...,4/1
---./ I+-
I
0.8 ~_ _ _
tct(CH-FDL)
------0-.8~~~1_____________________________________
NOTE: Timing shown is for the TLC320AC02 operating in the slave mode (FS and SCLK signals generated extemally).
There is a data value in the FSD register greater than 18 decimal.
Figure 4 - 6. Slave SCLK to FSD Timing
7-241
SCLK
:.+
DOUT
U~1'-_---'/
----011( .
\"--
tci(CH-DOUT) ,
J
X
2•4V
2.4V
....
O4...V
_ _ _ _ _ _ _ _. \"'
. .;,;O.~4.;;.V_ __
HI-Z
\;j&;.,_
Figure 4-7. DOUT Enable Timing from HI-Z
SCLK
2V
if
O.8~
~
/
.1
1
tci(CH-DOUTZ)
HI-Z
0.81
DOUT
Figure 4-8. DOUT Delay Timing to HI-Z
L.
_I
I"~
MCLK
____~;r~----~8~)l~~i----J~~~0.~8V-----------~
EOC
....
-u(ML-EH)
1
I
: . - tr(EH)
1
~
td(ML-EL)
!;rr~2.~4~V---~~(~j--~2~.4~V~1
I _0.4 V
_ _ _ _ _ _.....O,;, ; .4....V.....¥
I
~
1 (
1
14
Internal ADC
Conversion ,Time
Figure 4-9. EOC Frame Timing
7-242
.1
I+-1
.1
tf(EL)
~
.1
1
Delay Is m Shift Clockst
1
Master I
FS I
111111141-------I~ Delay Is m Shift Clockst
LJ
I
I
Master FSD,
Ir
tI
1-1- - - - - - ;
Slave Device 1 FS :
I
1
Delay Is m Shift Clockst
I
Slave Device 1 FSD, :
Slave Device 2 FS I
I
I
1
I
I
I
I
----------------------~U
Slave Device 2 --1FSD, I1
Slave Device 3 FS I
i
I
I
LJ
Slave Device I
(n -1) FSD,
Slave Device n FS
,.------
t The delay time from any FS signals to the corresponding FSD signals is m shift clocks with the value of m being the
numerical value of the data programmed into the FSD register. In the master mode with slaves, the same data word is
used to program the master and all slave devices; therefore, master to slave 1, slave 1 to slave 2, slave 2 to slave 3,
etc., have the same delay time.
Figure 4-10. Master-Slave Frame-Sync Timing After a Delay Has Been
Programmed Into the FSD Registers
t=O
t=1
Sampling ~
I
r ~~
t--; ~s
MasterAIC
Only Primary
FramSync
FS
I
I
~
fMP1
\'1 ~s
~
I I
II
r9
"
I
I 1
,
FsT~~~'~j----II :
h II
Ie
MasterAIC
Only Primary
and Secondary
Frame Sync
t=2
I
-'
r'j
h-FSD:'!
Master and Slave FS---'
AICPrimary
Frame Sync
.'
~ tSPt
I
1/2 Period I
1
1
"Wrr---u-v'j
:
1
IMPI
I
ISP
I
I
IMP!
ISPI
Master and Slave
AIC Primary and F S - - L J - U i J - L r t H J t i 1 J i J i J u u
MP
SP
MS
SS
MP
SP
MS
SS
MP
SP
MS
SS
Secondary
Frame Sync
MP = Master Primary
MS = Master Secondary
SP = Slave Primary
SS = Slave Secondary
Figure 4-11. Master and Slave Frame-Sync Sequence with One Slave
7-243
7-244
5
Typical Characteristics
ADC LOW·PASS RESPONSE
0
-10
III
=
'\
TA 25°C
FCLK 144 kHz
=
-20
"CI
I
c
0
i::::II
!
-30
-50
-60
-
r~ II """
-40
o
~I
1
2
3
4
5
6
7
8
11 -Input Frequency - kHz
9
10
Figure 5-1
ADO LOW·PASS RESPONSE
0.5
=
ITA 250C I
FCLK 144 kHz
0.4
=
0.3
0.2
III
"CI
I
0.1
0
i::::II
0
!ct
-0.1
c
c
-
"",
i'... r-- ~
,/
'\
\
-0.2
-0.3
-0.4
-0.5
o
0.5
1
1.5
2
2.5
3
3.5
4
'1 -Input Frequency - kHz
Figure 5-2
NOTE : Absolute Frequency (kHz)
Normalized Frequency x FCLK (kHz)
144
7-245
AI)C ~ROUP DELAY
1
TA=25°C
FCLK = 144 kHz
o.9
0.8
0.7
0.6
!
0.5
0.4
J
0.3
0
[.....00"
If;
\.
..........
'\
-1 0
ID
J
TA = 25°C
f8 = 8 kHz
FCLK =144 kHz
-20
"
!8
-30
!
-40
I
I
-50
-60
o
1\ 1/
~
II
1
23456
fl -Input Frequency - kHz
7
8
Figure 5-4
NOTE : Absolute Frequency (kHz)
7-246
=
Normalized Frequency x FCLK (kHz)
144
ADC BAND-PASS RESPONSE
o.5
o.4
TA=25°C
f S =8kHz
FCLK =144 kHz
o.3
CD
"c
i:::s
I
0.2
0.1
o
c
:!
I
-0.1
-
........
!;!"
I
4(
-0.2
,
/ 1\
~
I
-0.3
-0.4
-0.5
II
o
0.5
1
1.5
2
2.5
3
fl -Input Frequency - kHz
3.5
4
Figure 5-5
ADC HIGH-PASS RESPONSE
0
/
-5
CD
"g
/
-10
/
I
!=
10--
-15
I
-20
-25
-30
TA = 25°C
fs = 8 kHz
FCLK =144 kHz
o
50
100
150
200
fl -Input Frequency - kHz
250
Figure 5-6
NOTE: Absolute Frequency (kHz)
Normalized Frequency x FCLK (kHz)
144
7-247
ADC BAND-PASS GROUP DELAY
;
1
I
I
..!.
TA = 25°C
f s =8 kHz
FCLK =144 kHz
o.9
0.8
0.7
I
0.6
I
0.5
7
0.4
J
0.3
0.2
0.1
o
/
"- I--"""'"'
o
1
2
1\
"3
4
...............
5
j
7
6
8
fl - Input Frequency - kHz
Figure 5-7
DAC LOW-PASS RESPONSE
0
"
-10
ED
-20
TA = 25°C
fs = 9.6 kHz
FCLK =144 kHz
"a
I
C
i
-30
::I
!
-40
I~
-50
-60
/
r-..
If
~J
o
1
2
3
4
5
6
7
8
fl - Input Frequency - kHz
\
9
10
Figure 5-8
NOTE : Absolute Frequency (kHz)
7-248
Normalized Frequency x FCLK (kHz)
144
DAC LOW-PASS RESPONSE
o. 5
I
I
TA = 25°C
O. 4 fs = 9.6 kHz
FCLK =144 kHz
0.3
m
'tI
I
c
0.2
0.1
i
0
:!
-0.1
c
-
~
V
'"'-
h
C
-0.2
-0.3
-0.4
-0.5
o
0.5
1
1.5
2
2.5
3
3.5
4
fl - Input Frequency - kHz
Figure 5-9
DAC LOW-PASS GROUP DELAY
TAL25~ I
O. 9 I- fs = 9.6 kHz
FCLK =144 kHz
0.8
1
0.7
I
0.6
I
0.5
~
fl
II
0.4
0.3
0.2
0.1
o
j
V
o
1
2
1\
3
4
"'" 5
6
to--
7
8
lr
9
10
fl -Input Frequency - kHz
Figure 5-10
NOTE: Absolute Frequency (kHz)
Normalized Frequency x FCLK (kHz)
144
7-249
DAC (sin x)/x CORRECTION FILTER RESPONSE
4
~
2
V
o
/
V
.IV
\,
~
\
\
-2
\
-4 l- TA =25°C
=
~
\
Input ± 3-V Sine Wave
-6
o
I I II I
24
6
8 10 12 14 16
Normalized Frequency
18
20
Figure 5-11
DAC (sin x)/x CORRECTION FILTER RESPONSE
500
=
TA 25°C
Input ± 3-V Sine Wave
=
400
•I
Vf\
:I.
J
c!Go
~
300
J ~
200
~
100
y
l/
If
1\
"
I"'--
o
o
2
4
6
8 10 12 14 16
Normalized Frequency
18
20
Figure 5-12
NOTE: Absolute Frequency (kHz) = _N_or_m_a_"z_e_d_F...;,req---:...u:;:o:en:::;c;-:.y_x_F_C_L_K....;<:....kH_z..:.,>
288
7-250
DAC (sin x)/x CORRECTION ,ERROR
2
~
1.2
all
i•
-
0.4
~
.."
.........
0
:-0.4
:2
-0.8
I
Error
~
"
-1.8
o
V
~
...........
-1.2
-2
V
V (sin x) Ix Correction
0.8
"i'
/V'
TA=25°C
Input = ± 3-V Sine Wave
1.8
~
"'
19.2-kHz (sin x)
Distortion
I\..
,~
"- t\.
\
1
2
3
4
5
8
7
Normalized Frequency
8
9
'10
Figure 5-13
NOTE: Absolute Frequency (kHz)
=
Normalized Frequency x FCLK (kHz)
288
7-251
7-252
6
Application Information
TLC320AC02
TMS320C2x1C3x
.
.
CLKOUT
CLKX
CLKR
10
.... 11
DR
FSR
14
r
DX
FSX
DACVDD
DACVMID
DIN
DACGND
DOUT
~
12
....
MCLK
~
~
6
7
24
ADCVDD
FS
ADCVMID
13
5
23
22
ADCGND
SCLK
5V
+
+
0.1
0.1
;::: ::: 0.1
!iF
5V
;:::
F:
0.1
!iF
;:::
r:
0.1
!iF
!iF
9
DGTLVDD
DGTLGND
20
!iF
-==
-
DGND
5V
AOND
Figure 6-1. Stand-Alone Mode (to DSP Interface)
TMS320C2x13x
TLC320AC02
..
..
CLKOUT
DX
FSR
CLKX
CLKR
10
.... 11
-
DR
FSX
14
....
-
12
....
-
13
~
~
MCLK
DIN
DOUT
FS
SCLK
Figure 6-2. Codec Mode (to DSP Interface)
Terminal numbers shown are for the FN package.
7-253
TMS320C2x13x
TLC320AC02
.,14
CLKOUT
DX
..
DR
FSX
FSR
..
.,10
11
-
12
~
CLKX
..
CLKR
~.
-
MCLK
DIN
DOUT
Master Mode
FS
FSD
13
SCLK
TLC320AC02
-
.,14
.,10
-
11
~r
,
DIN
DOUT
~
FS
-
FSD
-
.,13
" .
MCLK
Slave Mode
SCLK
r
Terminal numbers shown are for the FN package.
Figure 6-3. Master With Slave (to DSP Interface)
10kn
IN+
10kn
INADCVMID
t The VI source must be capable of sinking a current equal to
[ADC VMID + IVII(max)]/10 kn.
Figure 6-4. Single-Ended Input (Ground Referenced)
7-254
IN+
10kn
10kn
10kn
Vlt --'V\f'v--......- - t
10kn
IN-
10kn
t------- ADC VMID
10kn
tThe VI source must be capable of sinking a current equal to [(ADC VMlo/2) + IVII(max)]/10 1<0.
Figure 6-5. Single-Ended to Differential Input (Ground Referenced)
OUT-
eoo-a
Load
OUT+
Figure 6-6. Differential Load
10kn
10kn
OUT- 1-..JV1/'v---4..---1
OUT+I-..JVI/'v---4..---1
10kn
eoo-a
TLE2062
Load
NOTE: When a signal is changed from a single supply with a nonzero reference
system to a grounded load, the operational amplifier must be powered from
plus and minus supplies or the load must be capacitively coupled.
Figure 6-7. Differential Output Drlve (Ground Referenced)
7-255
OUT+~--------~
TLE2062
6Oo-n
Load
OUT-I------f
Figure 6-8. Low-Impedance Output Drive
100kn
100kn
OUT+ I--'V'VV----_---t
DAC VMID t--..JV\/'v--.....- - I
100kn
600-0
Load
TLE2062
NOTE: When a signal is changed from a single supply with a nonzero reference
system to a grounded load, the operational amplifier must be powered from
plus and minus supplies or the load must be capacitively coupled.
Figure 6-9. Single--Ended Output Drive (Ground Referenced)
7-256
Appendix A
Primary Control Bits
The function of the primary-word control bits 001 and 000 and the hardware terminals FCO and FC1 are
shown below. Any combinational state of 001, 000, FC1, and FCO not shown is ignored.
CONTROL FUNCTION OF CONTROL BITS
BITS
D01
DOO
TERMINALS
FC1
FCO
DESCRIPTION
0
0
0
0
On the next falling edge of FS, the AIC receives DAC data D15-D02 to DIN and
transmits the ADC data D15-DOO from DOUT.
0
0
0
1
On the next falling edge of FS, the AIC receives DAC data D15-D02 to DIN and
transmits the ADC data D15-DOO from DOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of the next internal FS, the next ADC/DAC sampling time occurs later
by the number of MCLK periods equal to the value contained in the A' register. If the
A' register value is negative, the internal falling edge of FS occurs earlier.
0
0
1
0
On the next falling edge of FS, the AIC receives DAC data D15-D02 at DIN and
transmits the ADC data D15-DOO from DOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge ofthe next internal FS, the next ADC/DAC sample time occurs earlier
by the number of MCLK periods determined by the value contained in the A' register.
If the A' register value is negative, the intemal falling edge of FS occurs later.
0
0
1
1
On the next falling edge of the primary FS, the AIC receives DAC data D15-D02 at
DIN and transmits the ADC data D15- DOO from DOUT.
When FCO and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync~urs at 1/2 the
sampling time as measured from the falling edge of the primary FS.
0
1
0
0
On the next falling edge of FS, the AIC receives DAC data D15-D02 to DIN and
transmits the ADC data D15-DOO from DOUT.
The phase adjustment is determined by the state of D01 and DOO such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. If the A' register
value is negative, the falling edge of FS occurs earlier.
1
0
0
0
On the next falling edge of FS, the AIC receives DAC data D15-D02 at DIN and
transmits the ADC data D15-DOO from DOUT.
The phase adjustment is determined by the state of D01 and DOO. On the next rising
edge of FS, the next ADC/DAC sampling time occurs earlier by the number of MCLK
periods determined by the value contained in the A' register. If the A' register value
is negative, the internal falling edge of FS occurs later.
1
1
0
0
On the next falling edge of FS, the AIC receives DAC data D15-D02 to DIN and
transmits the ADC data D15-DOO from DOUT.
When DOO and D01 are both high, the AIC initiates a secondary FS to receive a
secondary control word at DIN. The secondary frame sync occurs at 1/2 the sampling
time as measured from the falling edge of the primary FS.
7-257
CONTROL FUNCTION OF CONTROL BITS (CONTINUED)
BITS
001
000
0
1
TERMINALS
FC1
FCO
1
1
DESCRIPTION
On the next falling edge of FS, the AICreceives OAC data 015-002 to DIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of 001 and 000 such that on the
next rising edge of FS, the next AOC/OAC sampling time occurs later by the number
of MCLK periOds determined by the value contained in the A' register. If the A' register
value is negative, FS occurs earlier.
When FCO and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 112 the
sampling time as measured from the falling edge of the primary FS.
1
0
1
1
On the next falling edge of FS, the AIC receives OAC data 015-002 at DIN and
transmits the AOC data 015-000 frqm OOUT.
The phase adjustment is determined by the state of 001 and OOO.On the next rising
edge of FS, the next AOC/OAC sample time occurs earlier by the number of MCLK
periods determined by the value contained in the A' register. If the A' register value
is negative, FS occurs later.
When FCO and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync~rs at 112 the
sampling time as measured from the falling edge of the primary FS.
1
1
1
1
On the next falling edge ofthe primary FS, the AIC receives OAC data 015-002 at
DIN and transmits the AOC data 015":'000 from OOUT.
When FC1 and FCO are both high or 001 and 000 are both high, the AIC initiates a
secondary FS to receive a secondary control word at DIN. The secondaryfS occurs
at 1/2 the sampling time measured from the falling edge of the primary FS.
1
1
0
1
On the next falling edge of FS, the AIC receives OAC data 015-002, to DIN and
transmits the AOC data 015- 000 from OOUT.
When 000 and 001 are high, the AIC initiates a secondary FS to receive a secondary
. control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as
measured from the falling edge of the primary FS.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of FS, the next AOC/OAC sampling time occurs later by the number
of MCLK periOds determined by the value contained in the A' register. If the A' register
value is negative, FS occurs earlier.
1
1
1
0
On the next falling edge of FS, the AIC receives OAC data 015-002 to DIN and
transmits the AOC data 015~000 from OOUT.
When 000 and 001 are high, the AIC initiates a secondary FS to receive a secondary
control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as
measured from the falling edge of the primary FS.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of FS, the nextAOC/OAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. If the A' register
value is negative, FS occurs earlier.
1
1
1
1
On the next falling edge of FS,the AIC receives OAC data 015"':002 at DIN and
transmits the AOC data 015-000 from OOUT.
When FC1 and FCO are both high or 001 and 000 are both high, the AIC initiates a
.secondary FS to receive a secondary control word at DIN. The secondaryfS occurs
at 112 the sampling time measured from the falling edge of the primary FS.
7-258
Appendix B
Secondary Communications
The function of the control bits OS15 and OS 14 and the hardware terminals FCO and FC1 are shown below.
Any combinational state of OS15, 0814, FC1, and FCO not shown is ignored.
CONTROL FUNCTION OF SECONDARY COMMUNICATION
BITS
DS15 DS14
TERMINALS
FC1
FCO
0
0
Ignored
On the next falling edge of~, the AIC receives DAC data D15-D02 at DIN and
transmits the ADC data D15-000 from DOUT.
0
1
Ignored
On the next falling edge of the FS, the AIC receives DAC data 015- 002 at DIN and
transmits the ADC data 015-000 from DOUT.
The phase adjustment is determined by the state of DS 15 and OS 14 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained"in the A' register. If the A' register
value is negative, FS occurs earlier.
1
0
Ignored
On the next falling edge of FS, the AIC receives DAC data 015-D02 at DIN and
transmits the ADC data 015-DOO from DOUT.
The phase adjustment is determined by the state of D01 and 000. On the next rising
edge of FS, the next AOC/DAC sampling time occurs earlier by the number of MCLK
periods determined by the value contained in the A' register. If the A' register value
is negative, FS occurs later.
"
1
1
0
0
On the next falling edge of ~, the AIC receives DAC data 015-002 at DIN and
transmits the AOC data 015-Doo from OOUT.
1
1
0
1
On the next falling edge of the FS, the AIC receives DAC data 015-'-002 at DIN and
transmits the AOC data D15- DOO from OOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. If the A' register
value is negative, FS occurs earlier.
1
1
1
0
On the next falling edge of FS, the AIC receives OAC data 015-002 at DIN and
transmits the ADC data 015-DOO from DOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of FS, the next AOC/DAC sampling time occurs earlier by the number
of MCLK periods determined by the value contained in the A' register. If the A' register
value is negative, FS occurs later.
1
1
1
1
On the next falling edge of FS, the AIC receives DAC dataD15-D02 at DIN and
transmits the AOC data D15- 000 from DOUT.
7-259
7-260
Appendix C
TLC320AC01 CITLC320AC02C Specification Comparisons
Texas Instruments manufactures the TLC320AC01 C and the TLC320AC02C specified for the O°C to 70°C
commercial temperature range and the TLC320AC021 specified for the -40°C to 85°C temperature range.
The TLC320AC02C and TLC320AC021 operate at a relaxed TLC320AC01 C specification. The differences
are listed in the following tables.
ADC Channel Signal-to-Distortion Ratio, Voo
Otherwise Noted) (see Note 1)
PARAMETER
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TEST CONDITIONS
VI=-6dBto-1 dB
VI=-12dBto-6dB
VI- -18 dB to -12 dB
VI = -24 dB to -18 dB
VI = -30 dB to -24 dB
VI =-36dBto-30dB
VI = -42 dB to -36 dB
VI
=-48 dB to -42 dB
AV=OdB
MIN MAX
=5 V, f8 =8 kHz (Unless
AV=6dB
MIN MAX
AV= 12dB
MIN
64
-
-
63
68
59
64
-
68
57
63
68
56
59
64
51
57
63
50
56
59
45
51
57
56
44
50
39
45
51
38
44
50
33
39
45
32
38
44
27
33
39
26
32
38
MAX
UNIT
dB
NOTE 1: The analog input test signal is a 1020-Hz sine wave with 0 dB = 6 V peak to peak as the reference level for
the analog input signal.
7-261·
DAC Channel Signal-to-Distortion Ratio, Voo
Otherwise Noted) (see Note 2)
PARAMETER
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TEST CONDITIONS
Vo .. -6 dB to OdB
Vo =-12 dB to-6 dB
Vo =-18 dB to -12 dB
Vo = -24 dB to -18 dB
Vo = -30 dB to -24 dB
Vo =-36 dB to -30 dB
Vo - -42 dB to -36 dB
Vo =-48 dB to -42 dB
Ay=OdB
MIN
68
MAX
=5 V, fs =8 kHz (Unless
Ay=-6dB
MIN
-
64
-
63
68
MAX
Ay=-12dB
MIN
MAx
UNIT
-
59
64
-
57
63
68
56
59
64
51
57
63
50
56
59
45
51
57
44
50
56
39
45
51
38
44
50
33
39
45
32
38
44
27
33
39
26
32
38
dB
NOTE 2: The input signal, V" is the digital equivalent of a 1020-Hz sine wave (full-scale analog output atfull-scale digital
input =0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The
load impedance for the DAC output buffer is 600 n from OUT + to OUT -.
7-262
System Distortion, ADC Channel Attenuation,
FCLK = 144 kHz (Unless Otherwise Noted)
PARAMETER
TLC320AC01
Voo = 5 V, fs = 8 kHz,
TEST CONDITIONS
MIN
MAX
70
Second harmonic
UNIT
dB
64
dB
TLC320AC02
Differential input
(see Note 3)
70
dB
TLC320AC01
Third hannonic and higher hannonics
TLC320AC02
dB
64
NOTE 3: The input signal is a 1020 Hz-sine wave for the ADC channel. Harmonic distortion is defined for an input level
of-1 dB.
System Distortion, DAC Channel Attenuation,
FCLK = 144 kHz (Unless Otherwise Noted)
PARAMETER
TLC320AC01
TLC320AC02
Second hannonic
TLC320AC01
Third hannonic and higher hannonics
TLC320AC02
Voo = 5 V, fs =8 kHz,
TEST CONDITIONS
Differential output
(see Note 4)
MIN
MAX
UNIT
70
dB
64
dB
70
dB
dB
64
NOTE 4: The input signal is the digital equivalent of a 102Q-Hz sine wave (digital full scale • 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the DAC
output buffer is 600 n from OUT + to OUT -. Harmonic distortion is specified for a signal input level of 0 dB.
7-263
7-264
TLC320AD55C
Data Manual
Sigma-Delta Analog Interface Circuit
.1ExAs
. INSTRUMENTS
7-266
IMPORTANT NOTICE
i
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injl,Jry, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
representthat any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1995, Texas Instruments Incorporated
7-266
Contents
Section
Title
Page
1
Introduction .............................................................
1.1 Features ............................................................
1.2 Functional Block Diagram .............................................
1.3 Terminal Assignments ................................................
1.4 Ordering Information .................................................
1.5 Terminal Functions ...................................................
1.6 Definitions and Terminology ...........................................
1.7 Register Functional Summary .........................................
7-271
7-271
7-272
7-273
7-273
7-274
7-275
7-276
2
Functional Description ....................................... .............
2.1 Device Functions ....................................................
2.1.1 Opera:ting Frequencies .........................................
2.1.2 ADC Signal Channel ...........................................
2.1.3 DAC Signal Channel ...........................................
2.1.4 Serial Interface ................................................
2.1.5 Register Programming ..........................................
2.1.6 Sigma-Delta ADC ..............................................
2.1.7 Decimation Filter ...............................................
2.1.8 Sigma-Delta DAC ..............................................
2.1.9 Interpolation Filter ..............................................
2.1.10 Switched-Capacitor Filter (SCF) .................................
2.1 .11 Analog/Digital Loopback ........................................
2.1.12 DAC Voltage Reference Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.1.13 FIR Overflow Flag .............................................
2.2 Terminal Descriptions ................................................
2.2.1 Reset and Power-Down ........................................
2.2.2 Master Clock Circuit ............................................
2.2.3 Data Out (DOUT) ..........•...................................
2.2.4 Data In (DIN) ..................................................
2.2.5 Hardware Program Terminal (FC) .......... , .....................
2.2.6 Frame-Sync ...................................................
2.2.7 Multiplexed Analog Input ........................................
2.2.8 Analog Input ..................................................
7-277
7-277
7-277
7-277
7-277
7-277
7-277
7-278
7-278
7-278
7-278
7-278
7-278
7-278
7-279
7-279
7-279
7-280
7-280
7-280
7-281
7-281
7-281
7-281
3
Serial Communications ..................................................
3;1 Primary Serial Communication ................. : .......................
3.2 Secondary Serial Communication ......................................
3.3 Conversion Rate Versus Serial Port ....................................
3.4 FIR Bypass Mode ....................................................
3.5 Phone Mode Control .................................................
7-283
7-283
7-285
7-287
7-288
7-289
7-267
Contents (Continued)
Section
4
Page
Title
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-291
4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range ...
4.2 Recommended Operating Conditions ..•................................
4.3 Recommended Operating Conditions, DVoo 5 V .................•.....
4.4 Electrical Characteristics, TA = 25°C, Voo(ADC) = Voo(DAC) = DVoo = 5 V,
MCLK = 16.384 MHz, Fk= 8 ..........................................
4.4.1 Digital Inputs and Outputs, Outputs Not Loaded .....•....•.........
4.4.2 ADC Path Filter ................................................
4.4.3 ADC Dynamic Performance ........................•............
4.4.4 ADC Channel .................................................
4.4.5 DAC Path Filter .....•..................•.......................
4.4.6 DAC Dynamic Performance .....................................
4.4.7 DAC Channel .................................................
4.4.8 Power Supplies, Voo(ADC) = Voo(DAC) = DVoo == 5 V, No Load ...
4.4.9 Timing Requirements ...........................................
=
5
7-291
7-291
7-291
7-292
7-292
7-292
7-292
7-293
7-293
7-294
7-294
7-295
7-295
Application Information .. ................. ~ .............................. 7-297
Appendix A Register Set . .................................................... 7-299
7-268
List of Illustrations
Figure
Title
Page
1-1 Functional Block Diagram .............................................. 7-272
1-2 Terminal Assignments ...............•................................. 7-273
2-1 Reset Function .......................................................
2-2 Internal Power-Down Logic .............................................
2-3 Differential Analog Input Configuration ...................................
3-1 Primary Serial Communication Timing ...................................
3-2 DAC and ADC Word Lengths ........................................•..
7-279
7-280
7-281
7-284
7-284
3-3 Hardware and Software Methods to Initiate a Secondary Request ........... 7-285
3-4 Secondary DIN Format ................................................ 7-285
3-5 Hardware FC Secondary Request ....................................... 7-286
3-6 Software FC Secondary Request ........................................ 7-287
3-7 FIR Bypass Timing .................................................... 7-288
3-8 Phone Mode Timing ............................. ~ ..................... 7-289
5-1 TLC320AD55C Application Schematic ................................... 7-297
5-2 TLC320AD55C 1/0 Buffer and VMID Generator Schematic .................. 7-298
List of Tables
Table
Title
Page
3-1 Least-Significant-Bit Control Function .................................... 7-286
3-2 Secondary Communication Data Format ................................. 7-287
7-269
7-270
1 Introduction
The TLC320AD55C provides high resolution low-speed signal conversion from digital-to-analog (D/A) and
from analog-to-digital (AID) using oversampling sigma-delta technology. This device consists of two. serial.
synchronous conversion paths (one for each data direction) and includes an interpolation filter before the
digital-to-analog converter (DAC) and a decimation filter after the analog-to-digital converter (ADC) (see
Figure 1-1). Other overhead functions provide analog filtering and on-chip timing and control. The
sigma-delta architecture produces high resolution. analog-to-digital and digital-to-analog conversion at low
system speeds and low cost.
The options and the circuit configurations of this device can be programmed through the serial interface.
The options include reset. power-down. communications protocol. serial clock rate. signal sampling rate.
and test mode as outlined in Appendix A. The circuit configurations could include a selection of input ports
to the ADC. analog loopback. digital loopback. decimator sinc filter output. decimator finite-duration
impulse-response (FIR) filter output. interpolator sinc filter output. and interpolator FIR filter output. The
TLC320AD55C is characterized for operation from
to 70°C.
aoc
1.1
Features
•
•
Single 5-V power supply
Power dissipation (Po) of 150 mW maximum in the operating mode
•
•
•
•
•
•
•
•
•
•
•
•
Power-down mode to 1 mW
General-purpose 16-bit signal processing
2s-complement format
Serial port ihterface
Minimum 80-d8 harmonic distortion plus noise
Differential architecture
Internal reference voltage (Vref)
Internal 64 x oversampling
Analog output with programmable gain of 1. 1/2. 1/4. and (squelch)
Phone-mode output control
Variable conversion rate selected as MCLK/(Fk x 256). Fk = 1.2.3 •...•256
System test mode:
a
Digital loopback test
Analog loopback test
7-271
1.2
Functional Block Diagram
INP ---.--~
INM ---.--~
AUXP ---.--~ MUX
AUXM ---.--~
t-+-.....~
DOUT (28
complement)
Analog
Loopback
OUTP
SCF
OUTM
Filter
H-~""""I- DIN (28
complement)
MCLK
SCLK
t See control 3 register in Appendix A.
Figure 1-1. Functional Block Diagram
7-272
1.3 Terminal Assignments
DWPACKAGE
(TOP VIEW)
NU
PWRDWN
OUTP
OUTM
VOO(DAC)
REFCAPOAC
VSS(DAC)
RESET
DVOO
DIN
DOUT
FS
SCLK
MCLK
3
4
7
11
AUXP
AUXM
INP
INM
VOO(ADC)
REFCAPAOC
VA(SUB)
VSS(ADC)
DVSS
VO(SUB)
ALTDATA
FLAG 0
FLAG 1
FC
NU-Make no external connection
Figure 1-2. Terminal Assignments
1.4
Ordering Information
TA
PACKAGE
SMALL OUTLINE
(DW)
O°Cte 70°C
TLC320A055COW
7-273
- 1.5
Terminal Functions
TERMINALS
NAME
NO.
DESCRIPTION
1/0
AUXM
27
I
AUXP
28
I
Noninverting input to auxiliary anl!.log input
ALTDATA
18
I
Signals on ALT DATA are roUted to DOUT during secondary communiction when phone
mode is enabled.
DIN
10
I
cData input. DIN r~ives the DAC input data and command information from the DSP
and is synchronized to SCLK.
DOUT
11
0
Data output. DOUT transmits the ADC output bits and is synchronized to SCLK. DOUT
is at Hi-Z when FS is not activated.
DVDD
9
I
Digital power supply
DVSS
20
I
Digi~1
FC
15
I
Function control. FC is sampled and latched on the rising edge of FS for the primary serial
communication. Refer to Section 3 Serial Communications for more details.
FLAG 0
17
0
During phone mode, FLAG 0 contains the value set in control 2 register.
FLAG 1
16
0
During phone mode, FLAG 1 contains the value set in control 2 register.
FS
12
0
Frame sync. When FS goes low, the serial communication port is activated. In all serial
transmission modes, FS is held low during bit transmission: Refer to Section 3 Serial
Communications for a detailed description.
INM
25
I
Inverting input to analog input
INP
26
I
Noninverting input to analog input
MCLK
14
I
Master clock. MCLK derives the intemal clocks of the sigma-delta analog interface
circuit.
OUTM
4
0
Inverting output of the DAC analog power amplifier. Functionally identical with and
complementary to OUTP. OUTM and OUTP can drive 600 a differentially. OUTM should
not be used alone for single-ended operation.
OUTP
3
0
Noninverting output of the DAC analog power amplifier. OUTM and OUTP can drive
600 a differentially. OUTP should not be used alone for single-ended operation.
PWRDWN
2
I
Power down. When PWRDWN is pulled low, the device goes into a power-down mode;
the serial interface is disabled and most of the high-speed clocks are disabled. However,
all of the registers' values are sustained and the device resumes full power operation
without reinitialization when PWRDWN is pulled high again. PWRDWN resets the
counters only and preserves the programmed register contents. Refer to Section 2.2.1.3
Software and Hardware Power-Down.
REFCAPADC
23
0
Analog-reference voltage connection for external capacitor for the ADC. The nominal
voltage on REFCAPADC is 3.4 V. A buffer must be used when this voltage is used
externally. REFCAPADC is not to be used as the mid-supply voltage reference for
single-ended operation.
REFCAPDAC
6
0
Analog-reference voltage connection for external capacitor for the DAC. The nominal
voltage on REFCAPDAC is 3.4 V. A buffer must be used when this voltage is used
externally.
RESET
8
I
Reset. The reset function initializes all of the internal registers to their default values. The
serial port can be configured to the defauHstate accordingly. Refer to Appendix A Table
A-2 Control 1 Register and Section 2.2.1 Reset and Power-Down for more detailed
descriptions.
13
0
Shift clock. SCLK is derived from MCLK and clocks serial data into DIN and out of DOUT.
SCLK
Inverting input to auxiliary analog input
ground
NOTE 1: All digital inputs and outputs are TTL compatible unless otherwise noted.
7-274
1.5
Terminal Functions (Continued)
TERMINALS
NAME
NO.
110
DESCRIPTION
VA(SUB)
22
I
Analog substrate. VA(SUB) must be grounded.
VD(SUB)
19
I
Digital substrate. VD(SUB) must be grounded.
VDD(ADO)
24
I
Analog ADO path supply
VDD(DAO)
5
I
Analog DAO path supply
VSS(ADO)
21
I
Analog ADO path ground
I
7
Analog DAO path ground
VSS(DAO)
..
NOTE 1: All digital Inputs and outputs are TTL compatible unless otherwise noted.
1.6
Definitions and Terminology
Data Transfer Interval The time during which data is transferred from DOUT and to DIN. The interval is
16 shift clocks and this data transfer is initiated by the falling edge ofthe frame-sync
signal.
Signal Data
The input signal and all of the converted representations through the ADC channel
and retum through the DAC channel to the analog output. This is contrasted with
the purely digital software control data.
Primary
Communications
The digital data transfer interval. Since the device is synchronous, the signal data
words from the ADC channel and to the DAC channel occur simultaneously.
Secondary
Communications
The digital control and configuration data transfer interval into DIN and the register
read data cycle from DOUr. The data transfer interval occurs when requested by
hardware or software.
Frame Sync
The falling edge of the signal that initiates the data transfer interval. The primary
frame sync starts the primary communications, and the secondary frame sync
starts the secondary communications.
Frame Sync and
Sampling Period
The time between falling edges of successive primary frame-sync signals.
The sampling frequency that is the reciprocal of the sampling period.
fs
Frame-Sync Interval The time period occupied by 16 shift clocks. It goes high on the sixteenth rising
edge of SCLK after the falling edge of the frame sync.
ADC Channel
All signal processing circuits between the analog input and the digital conversion
results at DOUT.
DACChannel
All signal processing circuits between the digital data word applied to DIN and the
differential output analog signal available at OUTP and OUTM.
Host
Any processing system that interfaces to DIN, DOUT, SCLK, or FS.
Dxx
A bit position in the primary data word (xx is the bit number).
DSxx
A bit position in the secondary data word (xx is the bit number).
d
The alpha character d is used to represent valid programmed or default data in the
control register format (see secondary serial communications) when discussing
other data bit portions of the register.
x
The alpha character Xrepresents a don't-care bit position within the control register
format.
FIR
Finite-duration impulse response.
7-275
1.7
Register Functional Summary
There are six data and control registers that are used as follows:
Register 0
The No-op register. The 0 register allows secondary requests without altering any other
register..
Register 1
The control 1 register. The data in this register controls:
•
The software reset
•
The software power-down
•
Selection of the normal or auxiliary analog inputs
•
The output amplifier gain (1, 1/2, 1/4, or squelch)
•. Selection of the analog loopback
Register 2
Register 3
Register 4
RegisterS
7-276
•
Selection of the digltalloopback
•
16-bit or 15-bit mode of operation
The control 2 register. The data in this register:
•
Contains. the output flag indicating a decimator FIR filter overflow
•
Contains Flag 0 and Flag 1 output values for use in the phone mode
•
Selects the phone mode
•
Selects or bypasses the decimation FIR filter
• Selects or bypasses the interpolater FIR filter
The Fk divide register. This register controls the filter clock rate and the sample period.
The Fsclk divide register. This register controls the shift (data) clock rate.
The control 3 register. This register enables and disables the DAC reference.
2
Functional Description
2.1
Device Functions
The following sections describe the functions of the device.
2.1.1
Operating Frequencies
The sampling (conversion) frequency is derived from the master clock (MCll<) input by the following
equation:
. .
MClK frequency
fs = Sampling (conversion) frequency = (Fk register value) x 256
The inverse is the time between the falling edges of two successive primary frame-synchronization Signals
and it is the conversion period.
The input and output data clock (SClK) is given by:
SClK frequency =
2.1.2
MCl~ frequency
(Fsclk register value) x 2
ADC Signal Channel
To produce excellent common-mode rejection of unwanted Signals, the analog signal is processed
differentially until it is converted to digital data.
The ADC converts the signal into discrete output digital words in 2s-complement format, corresponding to
the analog-signal value at the sampling time. These 16-bit digital words, representing sampled values of
the analog input signal, are clocked out of the serial port, DOUT, during the frame-sync interval (one word
for each primary communication interval). During secondary communications, the data previously
programmed into the registers can be read out with the appropriate register address, and the read bit set
to 1. When a register read is not requested, al\ 16 bits are 0 in the secondary word.
2.1.3
DAC Signal Channel
DIN receives the 16-bit serial data word (2s complement) from the host during the primary communications
interval and latches the data on the seventeenth rising edge of SClK. The data are converted to an analog
voltage by the DAC and then passed through a (sin x)/x correction circuit and a smoothing filter. An output
buffer with three software-programmable gains (0 dB, -6 dB, and -12 dB) drives the differential outputs
OUTP and OUTM. A squelch mode can also be programmed for the output buffer. During secondary
communications, the configuration program data are read into the device control registers.
2.1.4
Serial Interface
The digital serial interface consists of the shift clock, the frame synchronization signal, the ADC-channel
data output, and the DAC-channel data input. During the primary 16-bit frame synchronization interval,
SClK transfers the ADC c,hannel results from DOUT and transfers 16-bit DAC data into DIN.
During the secondary frame-synchronization interval, the SClK transfers the register read data from DOUT
when the read bit is set to a one. In addition, SClK transfers control and device parameter information into
DIN. The functional sequence is shown in Figure 3-1.
2.1.5
Register Programming
All regi~ter programming occurs during secondary communications, and data are latched and valid on the
rising edge of the frame-sync signal. When the default value for a particular register is desired, that register
does not need to be addressed during secondary communications. The no-op command addresses the
no-op register (register 0), and register programming does not take place during this communication.
7-2n
OOUT is released from the high-impedance state on the falling edge of the primary or secondary frame-sync
interval. In addition, each register can be read back during OOUT secondary communications by setting the
read bit 013 to 1 in the addressed register (refer to Appendix A). When the register is in the read mode, no
data can be written to the register during this cycle. To return this register to the write mode requires a
subsequent secondary communication.
.
2.1.6
Sigma-Delta ADC
The sigma-delta AoC is a fourth-order, sigma-delta modulator with 64-times oversampling: The AOC
provid~s high-resolution, low-:noise performance using oversampling techniques.
2.1.7
Decimation Filter
The decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating
with a ratio of 1:64. The output of this filter is a sixteen-bit, 2s-complement data word clocking at the sample
rate.
NOTE
The sample rate is determined through a programmable relationship of
MCLK/(Fk x 256), Fk = 1,2,3, ... ,256
2.1.8
Sigma-Delta DAC
The sigma-delta OAC is a fourth-order, sigma-delta modulator with 64-times oversampling. The OAC
provides high-resolution, low-noise performance from a one-bit converter using oversampling techniques.
2.1.9
Interpolation Filter
The interpolation filter resamples the digital data at a rate of 64 times the incoming sample rate. The
high-speed data: output from this filter is then used in the sigma-delta OAC.
2.1.10 Switched-Capacitor Filter (SCF)
A switched-capacitor filter network is implemented on the analog output to provide low-pass operation with
high rejection in the stop band.
2.1.11 •Analog/Digital Loopback
The loopbacks provide a means of testing the AOC/OAC channels and can be used for in~ircuit,
system-level tests. The loopbacks feed the appropriate output to the corresponding input on the device.
a
The test capabilities include an analog loopback between the two analog paths and digital loopback
between the two digital paths; Each loopback is enabled by setting the 01 or 02 bit in control 1 register (see
Appendix. A).
2.1.12 DAC Voltage Reference Enable
The OAC voltage reference can be disabled through the control 3 register. This allows the use of an external
voltage reference applied to the OAC channel modulator. By supplying an external reference, the user can
scale the output voltage range of this channel. The internal reference value is 3.6 V which provides a 6-V,
peak-to-peak, differential output. The ratio of an external reference to the internal reference determines the
output voltage range of the OAC channel as shown in the following equation:
VO(PP)
= V( EXi.6REF)
x6V
NOTE
The distortion and noise specifications listed in Section 4 Specifications apply only
under the following condition:
V(EXT REF)
1
3.6
s
7-278
2.1.13 FIR Overflow Flag
The decimator FIR filter provides an overflow flag to the control 2 register to indicate that the input to the
filter has exceeded the range of the internal filter calculations. When this bit is set in the register, it remains
set until the register is read by the user. Reading this value always resets the overflow flag.
2.2
Terminal Descriptions
The following sections describe the terminal functions.
2.2.1
Reset and Power-Down
2.2.1.1
Reset
As shown in Figure 2-1, the TLC320AD55C resets both the internal counters and registers, including the
programmed registers, in two ways:
•
By appling a low-going reset pulse to the RESET terminal
•
By writing to the programmable software reset bit (007 in control 1 register)
PWRDWN resets the counters only and preserves the programmed register contents. The DAC resets to
the 15-bit mode.
~-------~-------------------------,
14 .1
I
ru
I
TRESET
I
D RESETt-----.---1. To Circuitry
I
I
MCLK
I
I Software RESET Control
I
Register 1, Bit 7
I
IL _______________
________________
I Internal TLC320AD55C
~-
~
NOTE A: RESET to circuitry is at least 6 MCLK periods long and releases on the positive edge of MCLK.
Figure 2-1. Reset Function
2.2.1.2
Conditions of Reset
The two internal reset signals used for the reset and synchronization functions are:
•
•
Counter reset
- This signal resets all flip-flops and latches that are not externally programmed,
with the exception of those generating the reset pulse itself. Additionally, this
signal resets the software power-down bit.
Counter reset
=RESET terminal or reset bit or PWRDWN terminal
Register reset - This signal resets all flip-flops and latches that are not reset by the counter
reset, except those generating the reset pulse itself.
Register reset
=RESET terminal or reset bit
Both reset signals are at least six MCLK periods long (T RESET) and release on the trailing edge of MCLK
7-279
2.2.:1.3 Software and Hardware Power-Down
Given the definitions above, the software-programmed power-down condition is cleared by programming
the software bit (control 1 ~stETbit 6) to a 0 or is cleared by cycling the power to the device, bringing
PWRDWN low, or bringing R S low (see Figure 2-2).
.
PWRDWN removes power to the entire chip. The software-programmable, power-down bit only removes
power from the analog section of the chip, which allows a software power-up function. Cycling the
power-down terminal from high to low and back to high resets all flip-flops and latches that are not externally
programmed, thereby preserving the register contents with the exception that the software power-clown bit
is cleared.
When
PWRDWN Is not being used, it should be tied high [Voo(ADC) is preferred].
r~---------~--------------,
I
I
Digital Circuitry
~Down
Analog Circuitry
Power-Down
PWADWN
I
I
I
Bit 818 Programmed
I
Through a Secondary
I
Write OperatIon
I
I
IL_________________________ ~
I Internal TLC320AD55C
Figure 2-2. Internal Power-Down Logic
2.2.2
Master Clock Circuit
The clock circuit generates and distributes necessary clocks throughout the device. MCLK is the external
master clock input. SCLK is derived from MCLK [SCLK • MCLKI(Fsclk x 2), Fsclk =1,2,3,...,256] in order
to provide clocking of the serial communications between the device and a digital signal processor (DSP).
The sample rate of the data paths is set as MCLKI(Fk x 256). Fk and Fsclk are programmable register values
used as divisors of MCLK. The default value for the Fk and Fsclk register is 8 (decimal) ..
2.2.3
Data Out (DOUT)
DOUT is taken from the high-impedance state by the falling edge of the frame-sync signal. The most
significant data bit then appears on DOUT.
DOUT is placed in a high-impedance state on the sixteenth rising edge of SCLK (internal or external) after
the falling edge of the frame-sync Signal. In the primary communication, the data word is the ADC conversion
result. In the secondary communication, the data is the register read results when requested by the
read/write (R/W) bit with the eight MSSs set to zero (see the serial communications section). When a
register read is not requested, the secondary word is all zeroes.
.
2.2.4
Data In (DIN)
In the primary communication, the data word is the input digital signal to the DAC channel. In the secondary
communication, the data is the control and configuration data to set up the device for a particular function
(see Section 3 Serial Communications).
7-280
2.2.5
Hardware Program Terminal (FC)
This input provides for hardware programming requests for secondary communication. It works in
conjunction with the control bit 000 of the secondary data word. The signal on FC is latched 112 shift clock
after the rising edge of the next internally generated primary frame-sync interval. FC should be tied low when
not being used (see Section 3.2 Secondary Serial Communication).
2.2.6
Frame-Sync
The frame-sync signal indicates that the device is ready to send and receive data. The data transfer from
DOUT and into DIN begins on the falling edge of the frame-sync signal.
The frame sync is generated internally and goes low on the rising edge of SCLK and remains low during
the 16-bit data transfer.
2.2.7
Multiplexed Analog Input
The two differential analog inputs (INP and INM or AUXP and AUXM) are multiplexed into the slgma-delta
modulator. The performance of the AUX channel is similar to the normal input channel.
2.2.8
Analog Input
The signal applied to the terminals INM and INP should be differential to preserve the device specifications
(see Figure 2-3). A single-ended input signal should always be converted to a differential input signal prior
to being used by the TLC320AD55C. The signal source driving the analog inputs (INM. INP. AUXM. AUXP)
should have a low source-impedance for lowest noise performance and accuracy.
TLC320AD55C
~: -r-~-7L-~
~: -?\:-JL-~-~
IN.
,---INM
_ __
Figure 2-3. Differential Analog Input Configuration
7-281
7-282
3 Serial Communications
DOUT, DIN, SCLK, FS, and FC are the serial communication signals. The digital output data from the ADC
is taken from DOUT. The digital input data for the DAC is applied to DIN. The synchronizing clock for the
serial communication data and the frame sync is taken from SCLK. The frame-synchronization pulse that
encloses the ADC/DAC data transfer interval is taken from FS. For signal (audio) data transmitted from the
ADC or to the DAC, primary serial communication is used. To read or write words that control both the
options and the circuit configurations of the device, secondary communication is used.
The purpose of the primary and secondary communications is to allow conversion data and control data to
be transferred across the same serial port. A primary transfer is always dedicated to conversion data. A
secondary transfer sets up and reads the register values described in Appendix A. A primary transfer occurs
for every conversion period. A secondary transfer occurs only when requested. Two methods exist for
requesting a secondary command. Terminal FC can request a secondary communication when it is
asserted, or the LSB of the DAC data within a primary transfer can request a secondary communication.
The selection of which method is enabled is provided in control 1 register (bit 0) as shown in Appendix A.
For all serial communications, the most significant bit is transferred first. For a 16-bit ADC word and a 16-bit
DAC word, 015 is the most significant bit and DO is the least significant bit. For a 15-bit DAC data word in
the 16-bit primary communication, 015 is the most significant bit, 01 is the least significant bit, and DO is
used for the embedded function control. All digital data values are in 2s-complement format.
These logic signals are compatible with TIL-voltage levels and CMOS current levels.
3.1
Primary Serial Communication
Primary serial communication is used both to transmit and receive conversion signal data. The ADC word
length is always 16 bits. The DAC word length depends on the status of DO in the control 1 register. After
power-up or reset, the device defaults to the 15-bit mode (not 16-bit mode). The DAC word length is 15 bits
and the last bit of the primary 16-bit serial communication word is a function-control bit used to request
secondary serial communications. In the 16-bit mode, all 16 bits of the primary communications word are
used as data for the DAC and the hardware terminal Fe must be used to request secondary
communications.
7-283
Figure 3-1 shows the timing relationship for SCLK, FS, OOUT and DIN in a primary communication. The
timing sequence for this operation is as follows:
1.
The TLC320A055C takes FS low.
2.
One 16-bitword is transmitted from the AOC (OOUT) and one 16-bit word is received for the OAC
(DIN).
-VIH
VIL
......:.--- VOH
_ _ _ _ VOL
1...- - - Ir--------"""trt- ----,letls -.j
VOH
VOL
j4-
01
--Xc~-DOOO",,~~1
!
01
X
01
X
_---I
00
LSB·
Fe
~A
>V//7/ffi
LSB
Figure 3-1. Primary Serial Communication Timing
When a secondary request is made through the LSB of the OAC data word (16-bit mode), the format shown
in Figure 3-2 is used:
015
014
013
012 011 010 09 08 07 06 05 04 03 02 01
DO
15-bit OAC _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.......
~
2s-complement format
control
16-bit AOC --------------------I~~
2s-complement format
Figure 3-2. DAC and ADC Word Lengths
7-284
3.2
Secondary Serial Communication
Secondary serial communication reads or writes 16-bit words that program both the options and the circuit
configurations of the device. All register programming occurs during secondary communications. Four
primary and secondary communication cycles are required to program the four registers. When the default
value for a particular register is desired, the user can omit addressing it during secondary communication.
A no-op command addresses the no-op register (register 0), and no register programming takes place
during this secondary communication.
There are two methods for initiating secondary communications (see Figure 3-3):
1) by asserting a high level on FC, or 2) by asserting the LSB of DIN 16-bit serial communication high while
not in 16-bit mode (see control 1 register bit 0).
~-----------------------,
FC _ _-+-__________
I
(Hardware)
---l'~-- Secondary
~~
I
I
(LSB Of DIN)
I
I
1HnM~
(Control 1 Register,
Bit 0)
I
Iinternal TLC320AD55C
I
I
I
I
I
I
~----------------------~~
Figure 3-3. Hardware and Software Methods to Initate a Secondary Request
1.
Figures 3-5 and 3-6 show the two different methods by which FC requests secondary
communication words as well as the timing for FS, DOUT, DIN, and SCLK. The examples span
two primary communication frames. Figure 3-5 shows the use of hardware function control.
During a secondary communication, a register can be written to or read from. When writing a
value to a register, DIN contains the value to be written (see Figure 3-7). The data returned on
DOUT is OO(hex). When performing a read function, DIN can still provide data to be written to an
addressed register; however, DOUT contains the most recent value contained in the register
addressed by DIN.
Don'tC8re
.,~_....JA,--_---.,
~]
rj
R/W
I
v,-----t
8 Bits
Register Address
I IAI
I I
8 Bits
W?00
''-----.v~--...I1
Data to the
Register
Figure 3-4. Secondary DIN Format
In Figure 3-5, FC clocks in and latches on the rising edge of frame sync (FS). This causes the
start of the secondary update 32 FCLKs (see Fk divide register, Appendix A) after the start of the
primary communication frame. Read and write examples are shown for DIN and DOUT.
2.
Figure 3-6 shows the use of software function control.
The software request for function control is typically used when the required resolution of the DAC
channel is less than 16 bits. Then the least significant bit (DO) can be used for the secondary
requests as shown in Table 3-1.
7-285
Table 3-1. Least-Slgnlflcant-Blt Control Function
CONTROL BIT DO
0
1
CONTROL BIT FUNCTION
No operation (no-op)
Secondaryeommunlcatlon request
On the falling edge of the next FS, D15 through D1 is input to DIN or D15 through DO is output to DOUT.
When a secondary communication request is made, FS go~s low for 32 FCLKs (see Fk divide register,
Appendix A) after the beginning of the primary frame.
Communication Frame 2 (CF2) I
Primary
FC
DOUT I
(Secondary :/ ADC Data
Read)
1\
~
Out
1
I
.
DOUT
(Secondary
Write)
(secon~~k
., ADO Data
Out
I
1
L<-..l
DAC Data In
I
1
1
Register
Data
L\
,
1
·.1
~ ~=ry ~
1
1
~
~~lKS
64 FClKst
(128 SClKs when Fk = Fsclk)t
I
/I'
1
1
1
1
ADO Data
OUt·
~
14
1
lot
.1
1
:j: For a selected MCLK, Fk and Fsclk: SCLK .. 2 FklFsclk x FCLK
Figure 3-5. Hardware .FC Secondary Request
(Phone Mode Disabled)
I
I
-----t
~'r-\
~,
11--';
.
t See Fk divide register In Appendix A.
7-286
~-
K
!:W$R'DACDataln
14
.,
14
1
I
14-- 32 FClKst ~
~
1\
ADC Data
All Bits 0
Out
~,---~---,
1
Read or Write) 1
16 SClKs
:
K
.
I
I
~
~\
No Secondary
1
1
.
I
. .1
~/ffM0
~
~
.1
16 SClKs
64 FClKst
1
1
,
1
1
In Figure ~, FC hardware terminal 15 is left in its nonasserted state (0). FC is asserted through software
by embedding an asserted high level (1) in the LSB of the 16-bit primary word. This is possible when not
in 16-bit mode (control 1 register bit 2 = 0) because the user is using only 15 bits of OAC information.
r ~' i
I
CommunlcaUon Frame 1 (CF1)
I
" II ...... "
I
I
FC
OI
I
I
D15-D1
DO=1
~
\
j
I
II
I
I
I
I
Secondary
Communication Frame 2 (CF2)
~\
II
Prlma~ ;1.
No Secondary I
Request I
4
I
I "
I"
',\
I
II
~D15-01 DO.O
~
(Secon~':, KDACDataln~,=:.ry~DACDataln(?'$;00
I
Read or Write)
DOUr I
(Secondary
Read)
(Seco~~a~
Write)
18SCLKs
I
j4----+!-
Software Fe Bit
I
I
V ADC Data '--'\
I
8 SCLKs
K
ADC Data L~'
I. Out ~
1\
j
I
I
I
Register
I
I
I
I Data
K Aog~ ~~\
I
I
I
14
.1 16 SCLKs
I
I
I
I
14
.1
I
I
j4- 32 FCLKst ---.j
I
L.
Out
I
I
r
KADg~ata ~\
I
I
~
I
.116 SCLKs
I
I
I
14
I
I
I
I
I
I
I
I
I
I
I
I
.1
64 FCLKst
I
I
.1
64 FCLKst
I
I
I
t See Fk divide register in Appendix A.
NOTE A: For a read cycle, the last 8 bits are don't care.
Figure 3-6. Software FC Secondary Request (Phone Mode Disabled)
Table 3-2 shows the secondary communications format. 013 is the R/W bit, the read/not-write bit.
012 through 08 are address bits. The register map is specified in the register set section in Appendix A.
07 through DO are data bits. The data bits are values for the specified register addressed by data bits 012
through 08.
.
Table 3-2. Secondary Communication Data Format
D16
D14
D13
D12
D11
D10
De
D8
X
X
R/W
A
A
A
A
ADD
3.3
D7
D8
D6
D4
D3
D2
D1
DO
0
0
0
0
0
0
Conversion Rate Versus Serial Port
The SCLK frequency can be programmed independently from the FCLK frequency. This can create a
problem with the interpretation of the serial port data. The serial port is designed to initiate a primary
communication every 64 SCLKs. There must be an integer number of SCLKs ~ 40 per sample period. Two
examples follow to demonstrate the possible output of the serial port. SCLK must be fast enough to collect
all data from each frame.
Example 1: MCLK = 4.096 MHz, sample rate = 8 kHz, 8 kHz = MCLKI (Fk x 256), set Fk = 2,
SCLK = MCLKI(Fsclk x 2), set Fsclk =2, SCLK = 1.024 MHz. With this configuration,
SCLK =sample rate x 128. Therefore, each primary communication is a valid sample. .
7-287
Example 2: All variables above remain the same except Fsclk ... 1, SCLK = 2.048· MHz = sample
rate x 256. In this configuration, two consecutive primary communications represent the
same data sample.
3.4
FIR Bypass Mode
An option is provided to bypass the FIR sections of the decimation filter and the Interpolation filter. This is
selected through the control 2 register. The sinc filters of the two paths cannot be bypassed.
The timing requirements for this mode of operation are shown in Figure 3-7.
FS
Primary
l
Secondary.
Primary
1
1
1
DOUT
-4cAD&u~)
1
DIN
1
1
-K
1
I'"
I'"
Secondary
__----w
K~A~Dg~~~tm~'~
"------WI
Primary
r
__________________~(A~~~
1
18-4
W~//A
'I""' 16 FCLKS
~
See Note A
I
3-0
I
~
NOTE A: The number of clocks between primary cycles is a function of FCLK. When either FIR is bypassed, this period
is 16 FCLKs. See Fk divide register in Appendix A.
Figure 3-7. FIR Bypass Timing
7-288
3.5
Phone Mode Control
This function is provided for applications that need hardware control and monitor of external events. By
allowing the device to drive two FLAG terminals (set through the control 2 register). the host digital signal
processor (DSP) is capable of system control through the same serial port connection to the device. Along
with this control is the capability for monitoring the value of the ALT DATA terminal during a secondary
communication cycle. One application for this function is in monitoring ring detect or offhook detect from a
phone answering system. The two FLAG terminals allow response to these incoming control signals. Figure
3-8 shows the timing associated with this operating mode.
FS
l
Primary
Secondary
,.....---,
---
Primary
Secondary
,.....---,
---
Primary
r
Register
ALT DATA .
"m.d Data
(Secono:'~-<,-_.J»)o---~
Read)
8 SCLK8~
ALTDATA
~~~t~it-,.I
IHN
1 SCLK MAX
-< WM W4
W/~
Set FLAG 0 • FLAG 1 • 1
I,
';L~~Oi
W?0'ff00ZI
Figure 3-8. Phone Mode Timing
7-289
7-290
4 Specifications
4.1
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(unless otherwise noted)t
Supply voltage range, DVoo Voo(ADC, DAC)(see Note 1) .......... -0.3 V to 6.5 V
Output voltage range, DOUT: FS, SCLK, FLAG 0, FLAG 1 . .. -0.3 V to DVoo + 0.3 V
Output voltage range, OUTP, OUTM ........................ -0.3 V to Voo + 0.3 V
Input voltage range, DIN, PWRDWN, RESET, ALT DATA,
MCLK, FC ........................................... -0.3 V to DVoo + 0.3 V
Input voltage range, INP, INM, AUXP, AUXM ................ -0.3 V to Voo + 0.3 V
Case temperature for 10 seconds, Tc: DW package ......................... 260°C
Operating free-air temperature range, TA ............................ DoC to 70°C
Storage temperature range, Tstg ................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS(DAC) for DAC channel measurements and VSS(ADC) for ADC
channel measurements.
4.2
Recommended Op.rating Conditions
MIN
Supply voltage, VDD(ADC, DAC)
Analog signal input voltage, VI
I
NOM
4.5
Differential, (INP-INM) peak,
for full scale operation
,
Load resistance for OUTP and .oUTM, RL
0.3
Recommended Operating Conditions, DVoo
High-level input voltage, VIH
6
V
kO
100
pF
kHz
70
0
·C
=5 V
MIN
Supply voltage, DVDD
V
8
Operating free-air temperature, TA
UNIT
5.5
10
Load capacitance for OUTP and OUTM, CL
ADC or DAC conversion rate (Nyquist)
4.3
MAX
NOM
4.5
MAX
V
0.8
V
V
2
Low-level input voltage, VIL
MCLK frequency (see Note 2), duty cycle = 50 ±10%
16.384
NOTE 2: The default state for an 8 kHz conversion rate requires a 16.384 MHz MCLK frequency.
UNIT
5.5
MHz
7-291
=
4.4
=
=DVDD =5 V,
Electrical Characteristics, TA 25°C, VDD(ADC) VDD(DAC)
MCLK = 16.384 MHz, Fk = 8 (unless otherwise noted)
4.4.1
Digital Inputs and Outputs, Outputs Not Loaded
PARAMETER
TEST CONDITIONS
MIN
TYP
2.4
4.6
VOL
Low-level output voltage, oOUT
'0- 360 J,JA
10-2mA
I'H
IlL
Ci
High-level input current, any digital input
Low-level input current, any digital input
Input capacitance
5
pF
Co
Output cilpacitance
5
pF
VOH
High-level output voltage, oOUT
4.4.2
0.2
MAX
UNIT
V
0.4
V
V,H .. 5V
10
V'L= O.SV
10
J,JA
J,JA
ADC Path Filter (see Note 3)
PARAMETER
TEST CONDITIONS
20Hz
200Hz
Filter gain relative to gain at 1020 Hz
TYP
MIN
-0.5 -0.15
MAX
0.2
0.03
0.15
-0.5
300 Hz to 3 kHz
-0.15
0
0.15
3.3 kHz
-0.35
-0.5
0.3
3.4 kHz
-1
-0.6
..,.20
-0.1
4kHz
UNIT
dB
-14
~4.6kHz
-40
NOTE 3: The filter gain outside of the passband IS measured With respect to the gain at 1020 Hz. The analog input test
signal is a sine wave with 0 dB .. 6 V'(PP) as the reference level for the analog input signal. The passband is
Oto3400 Hz.
.
4.4.3
4.4.3.1
ADC Dynamic Performance
ADC Signal-to-Noise (see Note 4)
PARAMETER
Signal-to-noise ratio (SNR)
TEST CONDITIONS
TYP
V,--1 dB
MIN
80
v,--9dB
72
n
V,--40dB
40
45
21
V,.-65dB
14
MAX
UNIT
85
dB
72
7S
V'(AUXM, AUXP) = -9 dB
..
NOTE 4: The test conadion IS the digital equivalent of a 1020 Hz inPut Signal with an S kHz conversion rate. The load
impedance is 600 o. Input and output voltages are referred to Voo/2.
4.4.3.2
ADC Signal-to-Distortion (see Note 4)
PARAMETER
Signal-to-total harmonic distortion (THO)
TEST CONDITIONS
MIN
TVP
V,--1 dB
SO
92
V,--9dB
SO
94
VI--40dB
V,--65dB
40
60
15
40
M¥
UNIT
dB
SO
92
'v'(AUXM, AUXP) .. -9 dB
..
NOTE 4: The test condition is the digital eqUivalent of a 1020 Hz Input Signal with an S kHz conversion rate. The load
impeda~ is 600 O.lnput and output voltages are referred to Voo/2.
7-292
4.4.3.3
ADC Signal-to-Distortion+Noise (see Note 5)
PARAMETER
Total harmonic distortion+noise (THD+N)
TEST CONDITIONS
MIN
TYP
VI =-9dB
80
83
VI =-1 dB
72
76
VI =-40dB
40
45
VI--65dB
14
20
MAX
UNIT
dB
72
77
VI(AUXM; AUXP) =-9 dB
NOTE 5: The test condition is a 1020 Hz input signal with an 8 kHz conversion rate. Input and output voltages are
referred to VDD/2.
4.4.4
ACC Channel
PARAMETER
TEST CONDITIONS
MIN
Dynamic range
Interchannel isolation
Gain error, dc
INP = 3 V, INM =2 V
VI = 0 dB at 1020 kHz
dB
±0.5
4.4.5
Input resistance
dB
8
mV
80
dB
50
70
100
MIN
TYP
MAX
20 Hz
-0.5
0.08
0.15
200Hz
-0.5
0.08
0.15
300 Hz to 3 kHz
-0.15
0.08
0.15
3.3 kHz
-0.35
0.11
0.3
3.4 kHz
-1
-.48
-0.1
-20
-14
TA" 25°C
dB
±0.6
Idle channel noise (on-chip reference)
Ri
UNIT
dB
80
VI- -1 dB at 1020 Hz
Off-set error, ADC converter
CMRR
MAX
86
Gain error
Common-mode rejection ratio INM, INP or
AUXM,AUXP
TYP
J.I.Vrms
kn
CAC Path Filter (see Note 6)
PARAMETER
Filter gain relative to gain at 1020 Hz
TEST CONDITIONS
4kHz
UNIT
dB
kHz
-40
NOTE 6: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The input signal is the
digital equivalent of a sine wave (digital full scale .. 0 dB). ,The nominal differential DAC channel peak-to-peak
output voltage with this input condition is 6 V. The pass band is 0 to 3600 Hz.
~4.6
7-293
4.4.6
4.4.6.1
DAC Dynamic Performance
DAC Signal-to-Noise (see Note 4)
PARAMETER
TEST CONDITIONS
Signal-to-noise ratio (SNR)
MIN
TYP
VO .. OdB
VO .. -9dB
74
80
70
74
VO=-40dB
38
44
MAX
UNIT
dB
14
18
VO=-65dB
NOTE 4: The test condition is the digital equivalent of a 1020 Hz input Signal with an 8 kHz conversion rate. The load
impedance is 600 a. Input and output voltages are referred to Voo/2.
4.4.6.2
DAC Signal-to-Distortion (see Note 4)
PARAMETER
TEST CONDITIONS
VO-OdB
VO=-9dB
Signal-ta-total harmonic distortion (THO)
VO--40dB
VO=-65dB
MIN
TYP
74
74
84
84
40
58
18
30
MAX
UNIT
dB
NOTE 4: The test condition is the digital equivalent of a 1020 Hz input signal with an 8 kHz conversion rate. The load
impedance is 600 a. Input and output voltages are referred to VOo/2.
4.4.6.3
DAC Signal-to-Distortion+Noise (see Note 4)
PARAMETER
TEST CONDITIONS
VO-OdB
VO=-9dB
Total harmonic distortion+noise (THD+N)
VO .. -40dB
VO=-65dB
MIN
TYP
72
78
68
74
38
14
44
20
MIN
TYP
MAX
UNIT
dB
,
NOTE 4: The test condition is the digital equivalent of a 1020 Hz input Signal with an 8 kHz conversion rate. The load
impedance is 600 a.lnput and output voltages are referred to Voo/2.
4.4.7
DAC Channel
PARAMETER
TEST CONDITIONS
Oynamic range
80
Interchannel isolation
Gain error, 0 dB
Voo
Vo
dB
±0.5
VO" 0 dB at 1020 Hz
Oigital input offset = 1 V dc
Idle channel broad-band noise
See Note 7
Idle channel narrow-band noise 0-4 kHz,
Output offset voltage at OUT
OIN=AIIOs
(differential)
±0.2
dB
dB
100 IlVrms
See Note 7
RL",600,
With internal reference and full-scale
digital input, (see Note 8)
40 IlVrms
8
mV
6
NOTES: 7. The conversion rate is 8 kHz; the out-of-band measurement is made from 4800 Hz to FMCLK/2.
8. The digital input to the OAC channel atOIN is in 2s complement.
7-294
UNIT
dB
80
Gain error, dc
Analog output voltage,
peak-ta-peak, OUTP-OUTM
(differential)
MAX
V
4.4.8
Power Supplies, Voo(ADC)
otherewise noted)
PARAMETER
100 (ADC)
100 (DAC)
100 (Digital)
Po
4.4.9
Power supply current, ADC
Power supply current, DAC
Power supply current, digital
Power dissipation
lcJ2
TEST CONDITIONS
MIN
Operating
Power-down
TYP
MAX
12
20
mA
24
mA
400
Operating
16
Power-down
2.5
Operating
2
!lA
mA
6
Power-down
300
Operating
150
250
16
30
TYP
MAX
Power-down
UNIT
rnA
!lA
mW
Timing Requirements (see Notes 9 and 10)
PARAMETER
id1
=Voo(DAC) =DVoo =5 V, No Load (unless
TEST CONDITIONS
MIN
Delay time, SCLKt to FSJ.
Delay time, SCLKi to DOUT
10
15
6
20
tsu
th
Setup time, DIN before SCLKJ.
ten
Enable time, FSJ. to DOUT
10
idis
Disable time, Fsi to DOUT Hi-Z
Delay time MCLKJ. to SCLKt
20
Hold time, DIN after SCLKJ.
UNIT
20
20
CL-20pF
id3
NOTES: 9. Refer to Figure 3-1 for timing diagram.
10. When FS occurs after SCLK, it shortens the MSB (015) duration.
25
ns
25
50
7-295
7-296
5 Application Information
3.9kO
fc = 10.5 kHz
fc= 14.5 kHz
4.99kO
OUT(+)
220pF
15kO
2210
fc = 19.56 kHz
10kO
37kO
3900
fc= 40.8 kHz
IN747B
Telephone
Line
IN747B
220pF
0.033 JLF
fc = 19.56 kHz
3900
VMID
3900pF
2210
fc= 10.5 kHz
3.9kO
fc
=40.8 kHz
TO.01 JLF
-=- AGND
fc= 14.5 kHz
4.99kO
OUT(-)
VMID
-=-
5VA(ADC)
AGND
20kO
+
10 JLF
VMID
0.1
JLF
-=- AGND
Figure 5-1. TLC320AD55C Application Schematic
7-297
- 5VA(ADC)
20
5 V ....IV\I\r-...-
--<.
....
22j.iFP·1 j.iF
5VA(DAC)
5VA(ADC)
-=-AGND
20
5 VA(DAC) .
0.1 j.iF AGND
IN(+)
28
25
28
24
21
VDD
(ADC)
VSS
(ADC)
0.1 j.iF
1 kO
7
5
22
VA
Vss
VDD
(SUB) (DAC) (DAC)
INP
PWRDWN 2
INM
OUTP
AUXP
OUTM
AUXM
ALTDATA
TLC320AD55C
23
+
P
22 j.iF
AGND -=-
REFCAPADC
0.1j.iF
FS
0.1 j.iF
22j.iF'f-T
AGND -=-
--
-'~~:':":"""'I RESET
4
18
DR
DX
CLKX
CLKR
FSX
FSR
12
17}
8-14 RESET
FLAG 0
FLAG 1 18
t----~MCLK
OUT(-)
NC
11
DOUT
10
DIN
13
SCLK
8 REFCAPDAC
+
OUT(+)
3
Phone Mode
Programmable Bits (Latched)
15 FC
DVSS
VD(SUB)
VDD
20
19
9
NU
NC
0.1 j.iF
-=- DGND
+
10 j.iF
3V
Figure 5-2. TLC320AD55C 1/0 Buffer and VMID Generator Schematic
7-298
TMS320C5X
DSP
Serial Port
Appendix A
Register Set
Data bits 012 through 08 in the secondary serial communication contain the address of the register, and
data bits 07 through DO contain the data that is to be written to the register. Data bit 013 determines a read
or write cycle to the addressed register. When data bit 013 is low, a write cycle is selected.
The following table shows the register map:
Table A-1. Register Map
REGISTER NO.
015
014
013
0
0
0
1
0
0
REGISTER NAME
012
011
010
09
08
0
0
0
0
0
0
No operation
0
0
0
0
0
1
Control 1
2
0
0
0
0
0
0
1
0
Control 2
3
0
0
0
0
0
0
1
1
Fkdivide
4
0
0
0
0
0
1
0
0
Fsclk divide
5
0
0
0
0
0
1
0
1
Control 3
Table A-2. Control 1 Register
OESCRIPTION
07
1
0
06
05
04
03
02
01
00
-
Software reset
-
Software reset not asserted
Software power down (analog and filters)
-
Software power down (not asserted)
-
Select AUXP and AUXM
0
-
-
0
-
-
-
-
-
1
-
-
-
-
Analog output gain = 1
-
-
-
Analog output gain = 1/2
Analog output gain = 1/4
1
-
0
-
Digitalloopback not asserted
1
16-bit mode (hardware secondary requests)
0
Not 16-bit mode (software secondary requests)
-
0
-
1
0
-
- -
-
-
-
-
0
1
1
0
-
-
1
1
-
-
-
-
-
-
0
-
-
-
-
-
- -
-
-
-
-
-
-
-
-
-
- -
1
-
-
Select INP and INM
Analog output gain = 0 (squelch)
Analog loopback asserted
Analog loopback not asserted
Digitalloopback asserted
Default register value: 00000000
The software reset is a one-shot operation and this bit is cleared to zero after reset. It is not necessary to
write a zero to end the master reset operation.
7-299
Table A-3. Control 2 Register
D7
D6
X
X
-
-
-
-
-
-
-
D5 . D4
-
D3
D2
D1
DO
-
-
-
-
-
-
0
1
-
-
X
-
X
-
-
X
-
-
-
-
1
0
-
-
-
-
-
-
-
-
-
-
-
'
-
-
0
1
DESCRIPTION
Reserved
Decimator FIR overflowflag (valid only during read cycle)
FLAG 1 output value
FLAG 0 output value
Phone mode enabled
Phone mode disabled
Normal operation with decimator FIR filter
Bypass decimator FIR filter
Normal operation with interpolator filter
Bypass interpolator FIR filter
Default register value: 00000000
Writing zeros to the reserved bits is suggested.
Table A-4. Fk Divide Register
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
••
•
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default register value: 00001000
0
0
•
DO
1
255
DIVIDE VALUE
0
0
128
0
0
32
0
0
1
0
1
256
•••
0
••
•
••
D1
1
•
••
••
•
The oversampling clock (FClK) is set as MClK/(Fk x 4). MClK/(Fk x 256) is the sample frequency
(conversion rate) for the converter. When Fk is programmed to zero, its value is interpreted as 256.
7-300
Table A-S. Fsclk Divide Register
DIVIDE VALUE
D7
D6
D5
D4
D3
D2
D1
DO
1
1
1
1
1
1
1
1
255
0
0
128
0
0
32
1
0
0
0
0
1
0
0
0
0
0
0
••
•
••
•
••
•
0
0
0
0
0
0
••
•
••
•
•••
0
0
0
0
1
1
0
0
0
0
0
256
Default register value: 00001000
SCLK is set by MCLKI(2 x Fsclk). SCLK is for the serial transfer of data to and from the TLC320AD55C.
When Fsclk is programmed to zero, its value is interpreted as 256.
Table A-6. Control 3 Register
D7
D6
D5
D4
D3
D2
D1
DO
0
0
0
0
0
0
DESCRIPTION
0
1
0
0
0
DAC reference disabled
0
0
0
0
0
DAC reference enabled
7-301
7-302
TLC320AD57C
Data Manual·
Sigma-Delta Stereo Analog-ta-Digital Converter
.1ExAs
INSTRUMENTS
7-303
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to m~e changes to Its products or to discontinue any
semiconductor product or service without notice, and acJvises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the spebifications
applicable atthe time of sale in accordance with Tl's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each ~evice is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications,,).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications aSSistance, customer product design, software
performance, or Infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
Copyright @ 1995, Texas Instruments Incorporated
7-304
Contents
Section
Title
Page
1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
"1.1 Features ............................................................
1.2 Functional Block Diagram .............................................
1.3 Terminal Assignments ................................................
1.4 Ordering Information .................................................
1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
7-307
7-307
7-307
7-308
7-308
7-308
2
Detailed Description .....................................................
2.1 Power-Down and Reset Functions .....................................
2.1.1 Power Down ..................................................
2.1.2 Reset Function ................................................
2.2 Differential Input .....................................................
2.3 Sigma-Delta Modulator ...............................................
2.4 Decimation Filter .....................................................
2.5 High-Pass Filter .....................................................
2.6 Master-Clock Circuit ..................................................
2.7 Test ................................................................
2.8 Serial Interface ......................................................
2.8.1 Master Mode ..................................................
2.8.2 Slave Mode ...................................................
7-311
7-311
7-311
7-312
7-313
7-313
7-313
7-313
7-313
7-314
7-314
7-314
7-316
3
Specifications ...........................................................
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range ...
3.2 Recommended Operating Conditions ...................................
3.3 Electrical Characteristics ..............................................
3.3.1 Digital Interface, TA =25°C, AVoo = DVoo = 5 V ..................
3.3.2 Analog Interface ...............................................
3.3.3 Channel Characteristics, TA =25°C, AVoo = DVoo = 5 V,
fs = 48 kHz, HPByp = 1 .........................................
3.4 Switching Characteristics .............................................
7-317
7-317
7-317
7-318
7-318
7-318
4
7-319
7-319
Parameter Measurement Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-321
7-305
List of Illustrations
Figure
Title
2-1 Power-Down liming Relationships ......................................
2-2 Differential Analog Input Configuration ...................•...............
2-3 Serial Master Transfer Modes ..........................................
2-4 Serial Slave Transfer Modes ...........................................
4-1 SClK to Fsync and DOUT - Master Mode 3 ..............................
4-2 SClK to Fsync, DOUT, and lRClk - Master Modes 4 and 6 ................
4-3 SClK to Fsync, DOUT, and lRClk - Master Mode 5 .......................
4-4 SClK to Fsync, DOUT, and lRClk - Master Mode 7 .......................
4-5 SClK to lRClk and DOUT - Slave Mode 0, Fsync High ....................
4-6 SClKto Fsync, lRClk, and DOUT - Slave Mode 2, Fsync Controlled ........
Page
7-312
7-313
7-315
7-316
7-321
7-321
7-321
7-322
7-322
7-322
List of Tables
Table
Title
Page
2-1 Master-Clock to Sample-Rate Comparison ..............................• 7-314
7-306
1 Introduction
The TLC320AD57C provides high-resolution signal conversion from analog to digital using oversampling
sigma-delta technology. This device consists of two synchronous conversion paths. Also included is a
decimation filter after the modulator as shown in the functional block diagram. Other functions provide
analog filtering and on-chip timing and control.
A functional block diagram of the TLC320AD57C is included in section 1.2. Each block is described in the
Detailed Description section.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
1.2
Single 5-V Power Supply
Sample Rates (fs) up to 48 kHz
18-Bit Resolution
Signal-ta-Noise (EIAJ) of 97 dB
Dynamic Range of 95 dB
Total Signal-ta-Noise+Distortion of 91 dB
Internal Reference Voltage (Vref)
Serial Port Interface
Differential Architecture
Power Dissipation of 200 mW. Power-Down Mode for Low-Power Applications
One Micron Advanced LinEPIC1zrM Process
Functional Block Diagram
INLP
INLM
REFO
REFI
s
•r
~
I
a
I
I
n
t
•r
f
a
DOUT
Fayne
LRClk
e
8
INRP
OSFR
OSFL
INRM
MCLK
CMODE
MODEO-MODE2
Control
L-____
J-------------------.-.-~~---------~LK
LinEPIC1 Z is a trademark of Texas Instruments Incorporated.
7-307
1.3
Terminal Assignments
OW PACKAGE
(TOP VIEW)
INLP
INLM
REF I
INRP
INRM
REFO
LGND
Vlogic
NC
MODE1
OSFR
MCLK
AVDD
AVSS
AnaPD
HPByp
MODE2
OSFL
DigPD
TEST
CMODE
MODED
LRClk
. DVSS
DVDD
13
14
17
16
15
Fsync
DOUT
SCLK
NC - No internal connection
1.4
Ordering Information
PACKAGE
1.5
TA
SMALL OUTLINE
(OW)
O°Cto 70·C
TlC320AD57CDW
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AnaPD
6
I
Analog power-down mode. The analog power-down mode disables the analog
modulators. The single-bit modulator outputs become invalid, which renders the
outputs of the digital filters invalid. When AnaPD is pulled low, normal operation of the
device resumes.
AVDD
4
I
Analog supply voltage
AVSS
CMODE
5
I
Analog ground
12
I
Clock mode. CMODE selects between two methods of determining the master clock
frequency. When CMODE is high, the master clock input is 384x the conversion
frequency. When CMODE is low, the master clock input is 256x the conversion
frequency.
DOUr
16
0
Data output. DOUT transmits the sigma-delta audio analog-to-digital converter (ADC)
output data to a digital signal processor (DSP) serial port or other compatible serial
interface and is synchronized to SClK. DOUT is low when DigPD is high.
DVDD
18
I
Digital supply voltage
7-308
1.5
Terminal Functions (Continued)
TERMINAL
NAME
NO.
DESCRIPTION
1/0
DVSS
19
I
Digital ground
DigPD
10
I
Digital power-down mode. The digital power-down mode shuts down the digital
filters and clock generators. All digital outputs are brought to unasserted levels.
When DigPD is pulled low, normal operation of the device resumes.
Fsync
17
1/0
HPByp
7
I
High-pass filter bypass. When HPByp is high, the high-pass filter is bypassed. This
allows dc analog signal conversion.
INLM
2
I
Inverting input to left analog input amplifier
INLP
1
I
Noninverting input to left analog input amplifier
INRM
27
I
Inverting input to right analog input amplifier
INRP
28
I
Noninverting input to right analog input amplifier
LGND
25
I
Logic-power-supply ground for analog modulator
LRClk
14
1/0
Left/right clock. LRClk signifies whether the serial data is associated with the left
channel ADC (when high) or the right channel ADC (when low). LRClk is low when
DigPD is high.
MCLK
20
I
Master clock. MCLK derives all of the key logic signals of the sigma-delta audio
ADC. The nominal input frequency rang.e is 18.432 MHz to 256 kHz.
MODEO-MODE2
8,13,
22
I
Serial modes. MODEO-MODE2 configure this device for many different modes of
operation. The different configurations are:
Master versus slave
16 bit versus 18 bit
MSB first versus LSB first
Slave: Fsync controlled versus Fsync high
Each of these modes is described in the Serial Interface section with timing
diagrams.
MODE MASTER!
MSB/LSB
012
SLAVE
BITS
FIRST
slave
up to 18
MSB
000
001
slave
18
LSB
010
slave
up to 18
MSB
o 1 1 master
16
MSB
100
master
18
MSB
1 0 1
master
18
LSB
1 10
master
16
MSB
1 1 1
master
16
LSB
OSFL,OSFR
9,21
0
Over scale flag left/right. If the leftlright channel analog input exceeds the full scale
input range for two consecutive conversions, OSFL and OSFR are set high for 4096
LRClk periods. OSFL and OSFR are low when DigPD is high.
SCLK
15
1/0
Shift clock. If SCLK is confirgured as an input, SCLK clocks serial data out of the
sigma-delta audio ADC. If SCLK is configured as an output, SCLK stops clocking
when DigPD is high.
TEST
11
I
Test mode. TEST should be low for normal operation.
Frame synchronization. Fsync deSignates valid data from the ADC.
REFI
3
I
Input voltage for modulator reference (normally connected to REFO, terminal 26).
REFO
26
I
Internal voltage reference
Vlogic
24
I
Logic power supply (5 V) for analog modulator
7-309
7-310
2 Detailed Description
The following sections contain a detailed description of the TLC320AD57C.
2.1
Power-Down and Reset Functions
The following sections contain descriptions of the power-down and reset functions of the TLC320AD57C.
2.1.1
Power Down
The power-down state is comprised of a separate digital and analog power down. The power consumption
of each is detailed in Section 3.3, Electrical Characteristics.
The digital power-down mode shuts down the digital filters and clock generators. All digital outputs are set
to an unasserted level. When the digital power-down terminal (DigPD) is pulled low, normal operation of the
device is initiated.
In slave mode, the conversion process must synchronize to an input on the LRClk terminal and the SCLK
terminal. Therefore, the conversion process is not initiated until the first rising edges on both SCLK and
LRClk are detected after DigPD is pulled low. This synchronizes the conversion cycle. All conversions are
performed at a fixed LRClk rate [MCLKI256 (CMODE low) or MCLK/384 (CMODE high)) after the initial
synchronization. After the digital power-down terminal is brought low, the output of the digital filters remains
invalid for 50 LRClk cycles [see Figures 2-1 (a) and 2-1 (b)).
In master mode, LRClk is an output; therefore, the conversion process initiates based on internal timing.
The first valid data out occurs as shown in Figure 2-1 (c).
The analog power-down mode disables the analog modulators. The single-bit modulator outputs become
invalid, which renders the outputs of the digital filters invalid. When the analog power-down terminal is
brought low, the modulators are brought back online; however, the outputs of the digital filters require 50
LRClk cycles for valid results.
7-311
2.1.2
Reset Function
The conversion process is not initiated until the first rising edges on both·SCLK and LRClk are detected after
DlgPD is pulled low. This ~ynchronizes the conversion cycle. All conversions are performed at a fixed LRClk
rate [MCLK/256 (CMODE low) or MCLK/384 (CMODE high)) after the initial synchronization.
---"!II,
~
DlgPD
LRClk
.1
tau 1
Slave Mode Digital Power Down
i
1
\ __---1
I
---.....,/
DOUT'
Data Valid
(a)
~
I
1-DlgPD
\
tau2
Master Mode Digital Power Down
1
/
LRClk
I
\,--_,.....,1
I
DOUT
Data Valid
(b)
~
AnaPD
---~,
~1
.:
Analog Power Down
:
1
DOUT~
_ _ _ _ _ _ _ _ _ _ _ _ ___
(e)
Figure 2-1. Power-Down Timing Relationships
7-312
2.2
Differential Input
The input is differential in order to provide common-mode noise rejection and increase the input dynamic
range. Figure 2-2 shows the analog input signals used in a differential configuration to achieve
6.4-V peak-ta-peak differential swing with a 3.2-V peak-ta-peak swing per input line.
TLC320AD57
4.1 V
INLP,INRP
2.5 V
0.9 V
4.1 V
2.5 V
INLM,INRM
0.9 V
Figure 2-2. Differential Analog Input Configuration
2.3
Sigma-Delta Modulator
The modulator is a fourth order sigma-delta modulator with 64 times oversampling. The ADC provides
high-resolution, low-noise performance from a one-bit converter using oversampling techniques.
2.4
Decimation Filter
The decimation filter used after the sigma-delta modulator reduces the digital data rate to the sampling rate
of LRCIk. This is accomplished by decimating with a ratio of 1:64. The output of this filter is a 2s complement
data word of up to 18 bits serially clocked out.
If the input value exceeds the full range of the converter, the output of the decimator is held at the appropriate
extreme until the input returns to within the dynamic range of the device.
2.5
High-Pass Filter
The high-pass filter removes dc from the input. With this filtering, offset calibration is not needed. The
high-pass filter can be circumvented by asserting the HPByp terminal to pass dc signals through the
converter. However, an offset due to the converter can be present when bypassing the high-pass filter.
2.6
Master-Clock Circuit
The master-clock circuit generates and distributes necessary clocks throughout the device. MCLK is the
external master-clock input. CMODE selects the relationship of MCLK to the sample rate, LRClk. When
CMODE is low, the sample rate of the data paths is set to LRClk = MCLK/256. When CMODE is high, the
sample rate is set to LRClk = MCLK/384. With a fixed oversampling ratio of 64x, the effect of changing MCLK
is shown in Table 2-1.
When the device is in master mode, SCLK is derived from MCLK in order to provide clocking of the serial
communications between the sigma-delta audio ADC and a digital signal processor (DSP) or control logic.
This is equivalent to a clock running at 64 x LRClk.
When the device is in slave mode, SCLK is externally derived.
7-313
Table 2-1. Master-Clock to Sample-Rate Comparison
(modes 1, 3, 4, 5)
_ MCLK
(MHz)
12.2880
18.4320
2.7
CMOOE
Low
High
11.2896
Low
16.9344
High
8.1920
Low
12.2880
High
0.2560
0.3840
Low
High
SCLK
(MHz)
LRClk
(kHz)
3.0720
48
2.8224
44.1
2.0480
32
0.0640
1
Test
When the TEST input is high, the test mode is selected, which routes the high speed one-bit modulator result
to the serial port output. When in the test mode, the SCLK output frequency is equal to the data output rate.
LRClk is an input when the test mode is selected. This all9ws for the selection of the left or right modulator
output to be routed to the serial port (high = left and low = right).
2.8
Serial Interface
Although the serial data is shifted out in two seperate time packets that represent the left and right channels,
the inputs are sampled and converted simultaneously.
The serial interface protocol has master and slave modes each with different read-out modes. The master
mode sources the control signals for conversion synchronization while the slave mode allows an external
controller to provide conversion synchronization signals.
The five master modes are shown in Figures 2-3(a} through 2-3(e} and the three slave modes are shown
in Figures 2-4(a} through 2-4(c}. For a 16-bit word, D15 is the most significant bit and DO is the least
significant bit. Unless otherwise specified, all values are in 2s complement format.
In the master mode, SCLK is generated internally and is sourced as an output. The relationship of SCLK
to LRClk is 64x (modes 1,3,4, 5) or 32x (modes 6, 7). In the slave mode, SCLK is an input. SCLK timing
must meet the timing specifications listed in the Recommended Operating Conditions section.
2.8.1
Master Mode
As the master, the TLC320AD57C generates LRClk, Fsync, and SCLK from MCLK. These signals are
provided for synchronizing the serial port of a DSP or other control devices.
Fsync deSignates valid data from the ADC, and accomplishes this in the master modes by one of two
methods. The first method is to place a single pulse on Fsync prior to valid data. This indicates the starting
point for the data. The second method of frame synchronization is to hold Fsync high during the entire valid
data cycle which provides boundaries for the data.
LRClk is generated internally from MCLK. The frequ~ncy of this signal is fixed at the sampling frequency
fs [MCLK/256 (CMODE low) or MCLK/384 (CMODE high)). During the high period of this signal, the left
channel data is serially shifted to the output; during the low period, the right channel data is shifted to the
output. The conversion cycle synchronizes with the rising edge of LRClk.
Five modes are available when the device is configured as a master. Two modes are for 18-bit
communications. These modes differ f~om each other in that the MSB is transferred first in one mode while
I the LSB is transferred first in the second mode [see Figures 2-3(b} and 2-3(c)). When the LSB is transferred
first, the data is right justified to the LRClk [see Figures 2-3(a} through 2-3(e)). The three other modes
7-314
available as a master are 16-bit modes. Two of the modes differ as MSB first versus LSB first. These two
modes set SCLK =LRClk x 32. This is one half the frequency used in the other transfer modes [see Figures
2-3(d) and 2-3(e)]. The third 16-bit mode provides the data MSB first with one clock delay after LRClk [see
Figure 2-3(a)].
Mode 011
(a) MASTER MODE (Fayne bound)
SCLK
(\.../)../\...{
\----+_--!J~---.,.I----tl~\
Fsyne --+-o--!--...;
OOUT_~_ _~~
I
1
I
'I
'~~J\-~~~_~~~~~~~~~~~~
1I---+---t'---t----1r- 64 SCLKs Il
I
LRClk _---.l_ _1..J
\1o....I.._R..:lg_ht-J..._-lII\ol-\I_ _
I
·-"-1_--..1.1_--...1
FSyne'_--ii-'
Mode 101
SCLK
I
F~ne ___~__~__~J~~_~I~~I_ _~_~_~I~_~~~TI_~I_
1-
I
II
I
I
II
I
I.
___t1
I
OOUT_--,~~~_~_~..:0~1~i~~1~8~~___~__;~0~~~1~~W~~~.~
LRClk
===+===+1I ==:+1I ~=+I
=..!64!.,!SCLKs
I
1
1
J
I
.r
II
I
i Right
I
I-,V---l
--t---1 Left
I
I
I
r""';:""""-1It---t-1---t----il'i--j---'J
, I
!O-L
(d) DSP CONTINUOUS MODE
DOUT_~'--__~~~~~~-"'~~~I~~~~~~~~__~~~-L~~~
I
I
I
I 1\
I , Right
f~~==~+=~==~'32~S~C~L~
LRClk _ _-+-_.... Ir Left
I
Mode 111
I
II
H~
.
I""'--'--t----+-II--+--+--
I
(e) DSP CONTINUOUS MODE
SCLK
F~ne~I~__~_~_~_ _+-_~1
DOUT
LRClk
1
--"1'---'1
Left
132SCLKS
' Right
I
I
I
\I
Figure 2-3. Serial Master Transfer Modes
7-315
2.8.2
Slave Mode
As a slave, the TLC320AD57C receives LRClk, Fsync, and SCLK as inputs. The conversion pycle
synchronizes to the rising edge of LRClk, and the data synchronizes to the falling edge of SCLK. SCLK must
meet the setup time requirements specified in Section 3.2, Recommended Operating Conditions.
Synchronization of the slave modes is accomplished with the digital power-clown control.
In slave mode, Fsync is an input. Three modes are provided as shown in Figures 2-4(a) through 2-4(c).
SCLK and LRClk are externally generated and sourced. The first rising edges of SCLK and LRClk after a
power-clown cycle Initiate the conversion cycle. Refer to Section 2.8.1, Master Mode for signal functions.
Several modes are available when the TLC320AD57C is configured as a slave. Using the ModeO, Mode1,
and Mode2 terminals, the TLC320AD57C can be set to shift out the MSB first or the LSB first [see Figures
2-4(a) and 2-4(b)]. The number of bits shifted out can be controlled by the number of valid SCLK cycles
provided within the left or right channel period. If only enough clocks are provided to shift out 16 data bits
before LRClk changes state, this is equivalent to a 16-bit mode.
Mode 000
(8) SLAVE MODE (Fsyne high)
SCLK~·
Fsyne
DOUT
LRClk
Input
Input
I
I
0'jtputl
put 1
1
I
I
1111
III~
11
I
~t1~~7:E1~~'g"1~~f~~E:t~~~1~r=F
c:
32-128 SCLKs -+----ir--+--+-+--+---ti
1
Left 1
l...;R..:lgT-rt~-+-+--t--+-~-t-...oIf
114 1
Mode 001
SCLK
(b) SLAVE MODE (Fsyne high)
hyne ~--r-~~--T--r~--~~--~~-T--rl~~~-TI--~I~I--~I~I
::t:~=-:::l1:=~::t:;4}oO::::j""=-=~01~84;!sc-il-LK-I~----t.;----i-- ~~I~·-·!~r:IE--+q--tj~
DOUT -+--;-+--1-=-::t+-=-=t-=
....
LRClk
~-+--+--If Left 1
.....
- -+""!
~R&ihF-t-+__+--+--1!---4I,"1+__...1~~
Mode 010
SCLK
Fsyne(1)
-+__+--+--+--,y--y-II
LRClk
I
\1..--+--+--+1--,
+ ~~
.,. -+---+--,~I
I I I
....
liI-_"""..J.,'rr-:--_
DOUT(1)
~I
Fsyne(2)
DOUT(2)
1
f
I
I
-+---+--tl--f Leftl
I
[
--
~i f*9=::~=:---"'"" ....,.JX,...I,.._-:,~~-:::
II
I
I
I
-i---1t---t--;.--r--;---4j
I
Figure 2-4. Serial Slave Transfer Modes
7-316
3. Specifications
3.1
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)t
Analog supply voltage range, AVoo (see Note 1) ................... -0.3 V to 6.5 V
Digital supply voltage range, DVoo (see Note 2) ................... -0.3 V to 6.5 V
Digital output voltage range, (externally applied) ........... -0.3 V to DVoo + 0.3 V
Digital input voltage range, MODEO - MODE2 . ~ .......... -0.3 V to DVoo + 0.3 V
Analog input voltage range, INLP, INLM, INRP, INRM ...... -0.3 V to AVoo + 0.3 V
Operating free-air temperature range, TA ............................. O°C to 70°C
Storage temperature range, Tstg ...••••••..•••••••••....•••.•... -65°C to 150°C
Case temperature for 10 seconas, TC ..................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .............. 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
NOTES: 1. Voltage values for maximum ratings are with respect to AVSS.
2. Voltage ~alues for maximum ratings are with respect to OVSS.
3.2
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Analog supply voltage, AVoo (see Note 3)
4.75
5
5.25
V
Digital supply voltage, OVOO
4.75
5
5.25
V
Analog logic supply voltage, at Vlogic
4.75
5
5.25
V
Reference voltage, Vref
3.2
V
Setup time, OigPOJ. to LRClki, slave mode, tsu1 (see Figure 2-1 (a»
30
ns
Setup time, OigPOJ. to LRClki, master mode, tsu2 (see Figure 2-1 (b»
30
ns
Setup time, SCLKi to LRClk, slave mode, tsu3 (see Figures 4-5 and 4-6)
30
ns
Setup time, LRClk to SCLKi, slave mode, tsu4 (see Figure 4-5)
30
ns
Setup time, SCLKi to Fsync, slave mode, tsu5 (see Figure 4-6)
30
ns
Setup time, Fsync to SCLKi, slave mode, tsu6 (see Figure 4-6)
30
Load resistance at OOUT, RL
Operating free-air temperature, TA
ns
10
0
kO
70
°C
NOTE 3: Voltages at analog inputs and outputs and AVOO are with respect to the AVSS terminal.
7-317
3.3
Electrical Characteristics
3.3.1
Digital Interface, TA = 25°C, AVoo = DVoo =5 V
PARAMETER
TEST CONDITIONS
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage, DOUT
IOH-2mA
VOL
Low-level output voltage, DOUT
IOL=2mA
IIH
High-level input current, any digital input
MIN
2
TYP
4.6
0.2
2.4
MAX
V
0.8
4.6
0.2
UNIT
V
V
0.4
V
1
pA
IlL
Low-level input current, any digital input
1
pA
OJ
Input capacitance
5
pF
00
Output capaCitance
5
pF
3.3.2
Analog Interface
3.3.2.1
ADC Modulator, TA =25°C, AVoo = DVoo =5 V, f8
HPByp = 1, CMODE =0, MODEO - 2 = 101
PARAMETER
=48 kHz, Bandwidth =24 kHz,
TEST CONDITIONS
MIN
Resolution
TYP
MAX
UNIT
18
Bits
DYNAMIC PERFORMANCE
Signal to noise (EIAJ)
Dynamic range
Signal to noise + distortion (THO + N)
Total harmonic distortion (THO)
Interchannel isolation
INLP • INRP .. 2.5 V de
INLM • INRM - 2.5 V dc
93
97
dB
-1 dB down from
6-V differential input between
INRP (INLP) and INRM (INLM)
91
95
91
dB
dB
0.001%
108
dB
Gain error
±0.2
dB
Interchannel gain mismatch
±0.2
dB
±5
mV
DC ACCURACY
Offset error (18-bit resolution)
Offset drift
7-318
±0.17
LSerO
3.3.2.2
Inputs/Supplies, TA = 25°C, AVoo = DVoo = 5 V, fs = 48 kHz, Bandwidth = 24 kHz,
HPByp = 1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Input voltage
Differential input
6.4
Single-ended input
3.2
Input impedance
.V
kn
50
POWER SUPPLIES
Power-supply current
IDD (analog), operating
22
30
mA
IDD (digital), operating
24
32
mA
IDD (analog), power down
100
IDD (digital), power down
40
IJA
IJA
230
mW
Power dissipation
3.3.3
Channel Characteristics, TA = 25°C, AVoo=DVoo = 5 V, fs = 48 kHz, HPByp = 1
PARAMETER
TEST CONDITIONS
Passband (-3 dB)
HPByp=O
Passband ripple
30 Hz -21.8 kHz
Stopband attenuation
26.2 kHz - 3046 kHz
MIN
TYP
0.001
UNIT
24
kHz
±0.01
dB
dB
80
Group delay
3.4
MAX
25/Fs
s
Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
ld1
Delay time, AnaPD.L to DOUT valid (see Figure 2-1 (c»
ld(MFSD)
Delay time, SCLK.L to Fsync, master mode
(see Figures 4-1,4-2,4-3, and 4-4)
-20
20
ns
ld(MDD)
Delay time, SCLK.L to DOUT, master mode
(see Figures 4-1, 4-2, 4-3, and 4-4)
0
50
ns
ld(MIRD)
Delay time, SCLK.L to LRClk, master mode
(see Figures 4-2 and 4-4)
-20
20
ns
ldCSDD1)
Delay time, LRClk to DOUT, slave mode (see Figure 4-5)
50
ns
ld(SDD2)
Delay time, SCLK.L to DOUT, slave mode
(see Figures 4-5 and 4-6)
50
ns
30
ns
7-319
7-320
4 Parameter Measurement Information
SCLK
tci(MFSD)
Fsyne
tci(MDD)
14
1
1
1
~
I
~I
j'II
DOUT
/MSB
LRClk ____________J)(~
X
MSB-1
X
________________________________________
Figure 4-1. SCLK to Fsync and DOUT - Master Mode 3
SCLK
"'(MFSD)
Fayne
~j
I
1\
tci(MDD)
~
I
I
DOUT
td(MIRD)
j'II
LRClk
~I
/MSB
~I
X
MSB-1
X
X
Figure 4-2. SCI.K to Fsync, DOUT, and LRClk - Master Modes 4 and 6
SCLK ' - - . / '
"'(M:::;
'sync
tci(MDD)
DOUT~
I
~j
1\~.------------------------1
14
~I
"P-LS-B--)(~__L_SB_-_1__)(~_______
LRClk~S
Figure 4-3. SCLK to Fsync, DOUT, and LRClk - Master Mode 5
7-321
SCLK
Fayne
:\
"(MFSD)~
I
tcI(MDD) l1li
DOUT
tcI(MIRD)
~
I
I
I
I
,--
LSB
X
LSB-1
~
X
I
LRClk
Figure 4-4. SCLK to Fsyne, DOUT, and LRClk - Master Mode 7
I
SCLK
LRClk
I
. . .i------.
-----~*~---------
tcI(SDD1)~
.l-I~_-1_7:=====X
DOUT _ _ _ _ _ _ _
Flgure~.
tau3
I
tcI(SDD2)~
Xr-;----)~
16
SCLK to LRClk and DOUT - Slave Mode 0, Fsyne High
~I
I
taus
~~
I
tau6
SCLK
I
I
I
tcI(SDD2)~
Fayne
I
I
V
DOUT
LRClk
)
I
17
X
Figure 4-6. SCLK to Fsyne, LRClk, and DOUT - Slave Mode 2, Fsyne Controlled
7-322
>C
TLC320AD58C
Data Manual
Sigma-Delta Stereo Analog-ta-Digital Converter
•
TEXAS
INSTRUMENTS
7~
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant Information to verify, before placing orders. that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal Injury, or severe property or environmental damage (''Critical Applic~tions".
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1995, Texas Instruments Incorporated
7-.'324
Contents
Section
Title
Page
1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.1 Features ............................................................
1.2 Functional Block Diagram .............................................
1.3 Terminal Assignments ................................................
1.4 Ordering Information .................................................
1.5 Terminal Functions ...................................................
7-327
7-327
7-327
7-328
7-328
7-328
2
Detailed Description .....................................................
2.1 Power-Down and Reset Functions .....................................
2.1.1 Power Down ..................................................
2.1.2 ResetFunction ................................................
2.2 Differential Input .....................................................
2.3 Sigma-Delta Modulator ...............................................
2.4 Decimation Filter ..................................................•..
2.5 High..:Pass .Filter .....................................................
2.6 Master-Clock Circuit ..................................................
2.7 Test ................................................................
2.8 Serial Interface ......................................................
2.8.1 Master Mode ..................................................
2.8.2 Slave Mode ............................................... ; ...
7-331
7-331
7-331
7-331
7-332
7-333
7-333
7-333
7-333
7-333
7-333
7-334
7-335
3
Specifications .. .........................................................
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range ...
3.2 Recommended Operating Conditions ...................................
3.3 Electrical Characteristics ..............................................
3.3.1 Digital Interface, TA = 25°C, AVoo = DVoo = 5 V ..................
3.3.2 Analog Interface ................................... ; ...........
3.3.3 Channel Characteristics, TA = 25°C, AVoo = DVoo = 5 V,
fs =48 kHz .......•............................................
3.4 Switching Characteristics .............................................
7-337
7-337
7-337
7-338
7-338
7-338
7-339
7-339
4
Parameter Measurement Information ...................................... 7-341
5
Application Information .................................................. 7-343
7-325
List of Illustrations
Figure
Title
Page
2-1
2-2
2-3
Power-Down Timing Relationships .... "..................................
Differential Analog Input Configuration ...................................
Serial MasterTransfer Modes ................................ : .........
Serial Slave Transfer Modes ............................................
SCLKto Fsync and DOUT - Master Mode 3 ..............................
SCLK to Fsync, DOUT, and LRClk - Master Modes 4 and 6 ................
SCLK to Fsync, DOUT, and LRClk - Master Mode 5 .......................
SCLK to Fsync, DOUT, and LRClk - Master Mode 7 .......................
SCLK to LRClk and DOUT - Slave Mode 0, Fsync High ....................
SCLK to Fsync, LRClk, and DOUT - Slave Mode 2," Fsync Controlled ........
TLC320AD58C Configuration Schematic ........................•........
TLC320AD58C External Digital Timing and Control-Signal
Generation Schematic ......................•..........................
TLC320AD58C External Analog Input Buffer Schematic ....................
7-332
7-332
7-335
.7-336
7-341
7-341
7-341
7-342
7-342
7-342
7-344
2-4
4-1
4-2
4-3
4-4
4-5
4-6
5-1
5-2
5-3
7-345
7-346
List of Tables
Table
2-1
7-326
Title
Page
Master-Clock to Sample-Rate Comparison (Modes 1,3,4,5) ............... 7-333
1 Introduction
The TLC320AD58C provides high-resolution signal conversion from analog to digital using oversampling
sigma-delta technology. This device consists of two synchronous conversion paths. Also included is a
decimation filter after the modulator as shown in the functional block diagram. Other functions provide
analog filtering and on-chip timing and control.
A functional block diagram of the TLC320AD58C is included in Section 1.2. Each block is described in the
detailed description section.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
1.2
Single 5-V Power Supply
Sample Rates up to 48 kHz
18-Bit Resolution
Signal-te-Noise Ratio (EIAJ) of 97 dB
Dynamic Range of 95 dB
Total Signal-te-Noise+Distortion of 95 dB
Internal Reference Voltage (Vref)
Serial-Port Interface
Differential Architecture
Power Dissipation of 200 mW. Power-Down Mode for Low-Power Applications
One-Micron Advanced LinEPIC1 zrM Process
Functional Block Diagram
INLP -----~ISj;;;;::j5;H,;'1
DOUT
INLM -------L.=;~~
F8yne
REFO~
REFI
INRP
--------e
-----~rs.;;;;:~;W
INRM -------L~~~
serial
Interface
LRClk
OSFR
OSF!:.
MCLK
CMODE
CONTROL
MODE(O-2)
SCLK
LinEPIC1 Z is a trademark of Texas Instruments Incorporated.
7-327
Terminal Assignments
1.3
OW PACKAGE
(rOPVIEW)
INLP
INLM
REFI
AVDD
AVSS
AnaPD
TEST1
MODE2
OSFL
DigPD
TEST2
CMODE
MODEO
LRClk
INRP
INRM
REFO
LGND
Vlogic
NC
MODE1
OSFR
MCLK
DVss
DVDD
Fsyne
DOUT
SCLK
NC - No internal connection
Ordering Information
1.4
PACKAGE
1.5
TA
SMALL OUTLINE
(OW)
O°Cto 70°C
TlC320AD58CDW
Terminal Functions
TERMINAL
NAME
NO.
UO
DESCRIPTION
AnaPD
6
I
Analog power-down mode. The analog power-down mode disables the analog
modulators. The single-bit modulator outputs become invalid, rendering the outputs of the
digital filters invalid. When AnaPD is pulled high, normal operation of the device is
resumed.
AVDD
4
I
Analog supply voltage
AVSS
CMODE
5
I
Analog ground
12
I
Clock mode. CMODE is used to select between two methods of determining the master
clock frequency. When CMODE is high, the master clock input is 384x the conversion
frequency. When CMODE is low, the master clock input is 256x the conversion frequency.
DOUT
16
0
Data output. DOUT is used to transmit the sigma-delta audio ADC output data to a DSP
serial port or other compatible serial interface and is synchronized to SClK. This output
is low when DigPD is high.
DVDD
18
I
Digital supply voltage
DVSS
DigPD
19
I
Digital ground
10
I
Digital power-down mode. The digital power-down mode shuts down the digital filters and
clock generators. All digital outputs are brought to unasserted states. When DigPD· is
pulled high, normal operation of the device is resumed.
Fsync
17
I/O
7-328
Frame sync. Frame sync is used to designate the valid data from the ADC.
1.5 Terminal Functions (Continued)
TERMINAL
NAME
NO.
DESCRIPTION
I/O
INLM
2
I
Inverting input to left analog input amplifier
INLP
1
I
Noninverting input to left analog input amplifier
INRM
27
I
Inverting input to right analog input amplifier
INRP
28
I
Noninverting input to rigtrt analog input amplifier
LGND
25
I
Logic power supply ground for analog modulator
LRClk
14
I/O
Left/rightclock. LRClk signifies whether the serial data is associated with the left channel
ADC (when LRClk is high) or the right channel ADC (when LRClk is low). LRClk is low
when DigPD is low.
MCLK
20
I
Master clock. MCLK is used to derive all the key logic signals of the sigma-clelta audio
ADC. The nominal input frequency range is 18.432 MHz to 256 kHz.
13,22,
8
I
Serial modes. MODE(0-2) configure this device for many different modes of operation.
The different configurations are:
Master versus slave
16 bit versus 18 bit
MSB first versus LSB first
Slave: Fsyne controlled versus Fsync high
Each of these modes is described in the serial interface section along with timing
diagrams.
MODE MASTER!
MSB/LSB
012
SLAVE
BITS
FIRST
slave
up to 18
MSB
000
001
slave
18
LSB
010
slave
up to 18
MSB
011
master
16
MSB
10 0
master
18
MSB
10 1
18
master
LSB
1 10
master
16
MSB
1 1 1
master
16
LSB
OSFL,
OSFR
9,21
0
Over scale flag left/right. If the left/right channel digital output exceeds full scale output
range for two consecutive conversions, this flag is set high for 4096 LRClk periods.
OSFL and OSFR are low when DigPD is low.
SCLK
15
I/O
Shift clock. If SCLK is configured as an Input, SCLK is used to clock serial data out of
the sigma-delta audio ADC. If SCLK is configured as an output, SCLK stops clocking
when DigPD is low.
TEST1
7
I
Test mode 1. TEST1 should be low for normal operation.
TEST2
MODE(0-2)
11
I
Test mode 2. TEST2 should be low for normal operation.
REFI
3
I
Input voltage for modulator reference (normally connected to REFO, terminal 26).
REFO
26
I
Internal voltage reference
Vlogic
24
I
Logic power supply voltage (5 V) for analog modulator
7-329
7-330
2 Detailed Description
The sigma-delta converter allows for simple antialias external filtering. Typically, a first order RC filter is
sufficient.
2.1 Power-Down and Reset Functions
2.1.1
Power Down
The power-down state is comprised of a separate digital and analog power down. The power consumption
of each is detailed in the electrical characteristics section.
The digital power-down mode shuts down the digital filters and clock generators. All digital outputs are set
to an unasserted level. When the digital power-down terminal is pulled high, normal operation of the device
is initiated. In slave mode, the conversion process must synchronize to an input on the LRClk terminal as
well as the SCLK terminal. Therefore, the conversion process is not initiated until the first rising edges of
both SCLK and LRClk are detected after DigPD is pulled high. This synchronizes the conversion cycle; all
conversions are performed at a fixed LRClk rate [MCLKl256 (CMODE low) or MCLKl384 (CMODE high)]
after the initial synchronization. After the digital power-down terminal is brought high, the output of the digital
filters remains invalid for 50 LRClk cycles [see Figures 2-1 (a) and 2-1 (b)].
In master mode, LRClk is an output; therefore, the conversion process initiates based on internal timing.
The first valid data out occurs as shown in Figure 2-1 (c).
The analog power-down mode disables the analog modulators. The single-bit modulator outputs become
invalid which renders the outputs of the digital filters invalid. When the analog power-down terminal is
brought high, the modulators are brought back online; however, the outputs of the digital filters require 50
LRClk cycles for valid results.
2.1.2
Reset Function
The conversion process is not initiated until the first rising edges of both SCLK and LRClk are detected after
DigPD is pulled high. This synchronizes the conversion cycle; all conversions are performed at a fixed LRClk
rate [MCLKl256 (CMODE low) or MCLKl384 (CMODE high)] after the initial synchronization.
7-331 .
r-
DlgPD
Y
tsus
-.I--
I
LRClk
Slave-Mode Digital Power Down
II
\ __---J/
DOUT
/
Data Valid
(a)
l+-tSU6~
DlgPD
Y
I
LRClk
Master-Mode Digital Power Down
II
\ __---J/
DOUT
/
Data Valid
(b)
I'..
AnaPD
DOUT
---Y
1d1
~I1
Analog Power Down
I
..
1-----------
~~-----------------------(e)
Figure 2-1. Power-Down Timing Relationships
2.2
Differential Input
The input is differential in order to provide common-mode noise rejection and increase the input dynamic
range. Figure 2-2 shows the analog input signals used in a differential configuration to achieve a
6.4 V,(PP) differential swing with a 3.2 V'(PP) swing per input line. Both a differential and a single-ended
configuration are shown in the application information section.
TLC320ADS8
4.1 V
INLP,INRP
2.SV
0.9 V
4.1 V
2.SV
0.9 V
-~-~-7
INLM,INRM
Figure 2-2. Differential Analog Input Configuration
7-'332
2.3
Sigma-Delta Modulator
The modulator is a fourth-order sigma-delta modulator with 64 times oversampling. The ADC provides
high-resolution, low-noise performance from a one-bit converter using oversampling techniques.
2.4
Decimation Filter
The decimation filter used after the sigma-delta modulator reduces the digital data rate to the sampling rate
of LRClk. This is accomplished by decimating with a ratio of 1:64. The output of this filter is a 2s complement
data word of up to 18 bits serially clocked out.
If the input value exceeds the full range of the converter, the output of the decimator is held at the appropriate
extreme until the input returns to the dynamic range of this device.
2.5
High-Pass Filter
The high-pass filter removes dc from the input.
2.6
Master-Clock Circuit
The master-clock circuit is used to generate and distribute necessary clocks throughout the device. MCLK
is the external master clock input. CMODE is used to select the relationship of MCLK to the sample rate of
LRCIk. When CMODE is low, the sample rate of the data paths is set as LRClk = MCLKl256. When CMODE
is high, the sample rate is set as LRClk = MCLKl384. With a fixed oversampling ratio of 64><, the effect of
changing MCLK is shown in Table 2-1.
When the TLC320AD58C is in master mode, SCLK is derived from MCLK in order to provide clocking of
the serial communications between the sigma-delta audio ADC and a digital signal processor (DSP) or
control logic. This is equivalent to a clock running at 64 x LRCIk.
When the TLC320AD58C is in slave mode, SCLK is externally derived.
Table 2-1. Master-Clock to Sample-Rate Comparison
(Modes 1, 3, 4, 5)
2.7
MCLK
(MHz)
CMODE
12.2880
18.4320
High
Low
11.2896
Low
16.9344
High
8.1920
Low
12.2880
High
0.2560
Low
0.3840
High
SCLK
(MHz)
LRClk
(kHz)
3.0720
48
2.8224
44.1
2.0480
32
0.0640
1
Test
TEST1 and TEST2 are reserved for factory test and should be tied to digital ground (DVss).
2.8
Serial Interface
Although the serial data is shifted out in two seperate time packets that represent the left and right channels,
the inputs are sampled and converted simultaneously.
The serial interface protocol has master and slave modes each with different read out modes. The master
mode is used to source the control signals for conversion synchronization, while the slave mode allows an
external controller to provide conversion synchronization signals.
The five master modes are shown in Figures 2-3(a) through 2-3(e), and the three slave modes are shown
in Figures 2-4(a) through 2-4(c). For a 16-bit word, D15 is the most significant bit and DO is the least
significant bit. Unless otherwise specified, all values are in 2s complement format.
7-333
In master mode, SCLK is generated internally and is sourced as an output. The relationship of SCLK to
LRClk is 64x (modes 1,3, 4, 5) or 32x (modes 6, 7). In slave mode, SCLK is an input. SCLK timing must
meet the timing specifications shown in the recommended operating conditions section.
2.8.1
Master Mode
As the master, the TLC320AD58C generates LRClk, Fsync, and SCLK from MCLK. These signals are
provided for synchronizing the serial port of a digital signal processor (DSP) or other control devices.
Fsync is used to designate the valid data from the ADC, and this is accomplished in the master modes by
one of two methods. The first is a single pulse on Fsync prior to valid data. This indicates the starting point
for the data. The second method of frame synchronization is to hold Fsync high during the entire valid data
cycle, which provides boundaries for the data.
LRClk is generated internally from MCLK. The frequency of this signal is fixed at the sampling frequency
fs [MCLKl256 (CMODE low) or MCLKl384 (CMODE high)). During the high period of this signal, the left
channel data is serially shifted to the output; during the low period, the right channel data is shifted to the
output. The conversion cycle is synchronized with the rising edge of LRCIk.
Five modes are available when the device is configured as a master. Two modes are for 18-bit
communications. These modes differ from each other in that the MSB is transferred first in one mode while
the LSB is transferred first in the second mode [see Figures 2-3 (b) and 2-3(c)). When the LSB is transferred
first, the data is right justified to the LRClk [see Figures .2-3 (a) through 2-3(e)]. The three other master
modes are 16-bit modes. Once again, two of the modes differ as MSB first versus LSB first. These two
modes set SCLK = LRClk x 32. This is half the frequency used in the other transfer modes (see
Figures 2-3(d) and 2-3(e)). The third 16-bit mode provides the data MSB first with one clock delay after
LRClk [see Figure 2-3(a)].
7-334
Mode 011
(a) 16-BIT MASTER MODE (Fayne bound)
SCLK
Fayne ----if---+--
Dour----r---:~~t=~~~=t==~~e;;;x;i=~1=5t=1=4~~==~==:c==~
MSCLKe
LRClk
II--+---t---\I-+----+--.....,~,
-~--~~
I Right
~·+I~~-~~~-r--+_~
Mode 100
(b) 18-BIT MASTER MODE
I
SCLK./\/\.f\./lJ\.A
1
Fayne
nil
III
°1
---i-.J ~ ... I
I ~
I ' 1---'
DOur
~~~'''""_!'_---!---.....~;:;,~Z;-·''"' '4·"''\·,'~_ _ _I!--_lfi'CJ.
LRClk ___
~
I---'~
Lett
...
II Ii
l
MSCLKa
Right
f/,
Mode 101
I
II II I
II .H I I
(e) 18-BIT MASTER MODE
SCLK
Fayne
---1-----i---...,...-0 .I
II
I
I
DOUT_-J~~~__~__-A~O~1~~._
..~1~6~17~_~_.....~O~~1~,
LRClk
~
---1'---'1
II iI II
Lett
II
Mode 110
MSCLKa!
!
~. .,;R:.;.; lgl,; h;.; . tt-I---tl----t-II'\-I- - - 1 - -
(d) 16-BIT DSP CONTINUOUS MODE
SCLK~
Fayne ~\-I--+----+----+----+----H
Dour~~..~·~~~I~--~I~--~~~'
LRClk
I
I
f
Lett
I
I
I II
I
32 SCLKa
t
--;----;--i--;---tf
Right
r-
Mode 111
(8) 16-BIT DSP CONTINUOUS MODE
SCLK~
Fayne ~\-I-t-----+---+---+---~
DOUT~~"~'~~~~__~__~~-J~
LRClk
I
~ L tt
--i----r---+---i-----.j
I
,.. e I
I
I
III
Figure 2-3. Serial Master Transfer Modes
2.8.2
Slave Mode
As a slave, the TLC320AD58C receives LRClk, Fsync, and SCLK as inputs. The conversion cycle is
synchronized to the rising edge of LRClk, and the data is synchronized to the falling edge of SCLK. SCLK
must meet the setup requirements specified in the recommended operating conditions section.
Synchronization of the slave modes is accomplished with the digital power-down control.
In slave mode, Fsync is an input. Three modes are provided as shown in Figures 2-4(a) through 2-4(c).
SCLK and LRClk are externally generated and sourced. The first rising edges of SCLK and LRClk after a
power-down cycle initiate the conversion cycle. Refer to the master-mode section for signal functions.
7-335
Several modes are available when the TlC320AD58C is configured as a slave. Using the ModeO, Mode1,
and Mode2 terminals, the TlC320AP58C can be set to shift out the MSB first or the lSB first [see Figures
2-4(a) and 2-4(b)]. The number of bits shifted out, however, can be control/ed by the number of valid SClK
cycles provided within the left or right channel. period. If only enough clocks are provided to shift out 16 data
bits before lRClk changes state, then this is equivalent to a 16-bit mode. Modes 1 and 2 both require 64
SClK periods per lRClk period.
(8) 18-81T SLAVE MODE (Fsyne high)
(b) 18-81T SLAVE MODE (Fsyne high)
Mode 001
~LK
~
h~c -+--~~~--~-r~--~~~~~-T--~~-+--~~~I--+I~I
DOUT
~__+-~~__+--r~~~~~~~~~__+-~~~~~~~~1~7
LRClk
-+--1_+--'1
LRClk
I
.....
--+---~-+-
Figure 2-4. Serial Slave Transfer Modes
7-336
I
I
3 Specifications
3.1
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(unless otherwise noted)t
Supply voltage range, AVoo (see Note 1) ......................... -0.3 V to 6.5 V
Supply voltage range, DVoo (see Note 2) ......................... -0.3 V to 6.5 V
Analog input voltage range, INLP, INLM, INRP, INRM ............... -0.3 V to 6.5 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . .. -O°C to 70°C
Storage temperature range, Tstg ................................ -65°C to 150°C
Case temperature for 10 seconds ........................................ 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .....•........ 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
NOTES: 1. Voltage values for maximum ratings are with respect to AVSS.
2. Voltage values for maximum ratings are with respect to DVSS.
3.2
Recommended Operating Conditions
Analog supply voltage, AVDD (see Note 3)
4.75
MIN
NOM
5
MAX
5.25
Digital supply voltage, DVDD
4.75
5
5.25
V
Analog logic supply voltage, Vlogic
4.75
5
5.25
V
3.2
Reference voltage, Vref
UNIT
V
V
Setup time, SCLKi to LRClk, slave mode, tsu1
30
ns
Setup time, LRClk to SCLKi, slave mode, tsu2
Setup time, SCLKi to Fsync, slave mode, tsu3
30
ns
30
ns
Setup time, Fsync to SCLKi, slave mode, tsu4
30
ns
Setup time, DigPD to LRClki, slave mode, tsu5
30
ns
Setup time, DigPD to LRClki, master mode, tsus
30
10
kn
Load resistance at DOUT, RL
Input de offset range
Operating free-air temperature, TA
-50
0
0
ns
50
mV
70
·C
NOTE 3: Voltages at analog inputs and outputs and AVDD are with respect to the AVSS terminal.
7-337
3.3
Electrical Characteristics
3.3.1
Digital Interface, TA
=25°C, AVDD =DVDD =5 V
PARAMETER
TEST CONDITIONS
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage at OOUT
IOH-2rnA
VOL
Low-level output voltage at OOUT.
IOL-2rnA
IIH
High-level input current, any digital input
MIN
TYP
2
4.6
0,2
2.4
MAX
V
0.8
4.6
0.2
UNIT
V
V
0.4
V
1
pA
IlL
Low-level input current, any digital input
1
pA
Ci
Input capacitance
5
pF
Co
Output capacitance
5
pF
3.3;2
Analog Interface
3.3.2.1 ADC Modulator, TA =25°C, AVoo = DVoo =5 V, fs =48 kHz, Bandwidth =24 kHz,
CMODE = 0, MODE(0-2) = 000
PARAMETER
TEST CONDITIONS
MIN
TYP
DYNAMIC PERFORMANCE
ANSI A-weighting filter
Signal to noise (EIAJ)
INLP = INRP = 2.5 V de
INLM = INRM = 2.5 V de
Dynamic range
Signal to noise + distortion (THO + N)
-1 dB clown from
6-V differential input
Total harmonic distortion (THO)
MAX
UNIT
18
Bits
96
100
dB
90
95
dB
88
93
dB
Resolution
0.0015%
Interchannel isolation
120
dB
Absolute gain error
±0.6
dB
Interchannel gain mismatch
±0.2
dB
DC ACCURACY
Offset error (18-bit resolution)
Offset drift
3.3.2.2
120±5
mV
±0.17
LSB/oC
Inputs/Supplies, TA = 25°C,AVoo = DVoo = 5 V, fs = 48 kHz, Bandwidth =24 kHz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Input voltage range
(differential)
6.2
(0 to peak)
3.1
Input impedance
V
kn
200
POWER SUPPLIES
24
32
rnA
100 (digital), normal mode
26
32
rnA
100 (analog), power down
250
100 (digital), power down
150
pA
250
mW
100 (analog), normal mode
Power-supply current
Power dissipation
7-338
pA
3.3
Electrical Characteristics (Continued)
3.3.3
Channel Characteristics, TA
=25°C, AVoo =DVoo =5 V, fs =48 kHz
PARAMETER
TEST CONDITIONS
Passband (-3 dB)
MIN
0.001
Passband ripple
30 Hz - 21.8 kHz
Stopband attenuation
26.2 kHz - 3046 kHz
MAX
24
±0.01
UNIT
kHz
dB
80
Group delay
3.4
TYP
dB
25lfs
s
Switching Characteristics
PARAMETER
~1
Delay time, AnaPD to DOUr valid
~(MFSD)
Delay time, SCLKJ. to Fsync, master mode
MIN
TYP
MAX
30
UNIT
ns
-20
20
ns
~(MDD)
Delay time, SCLKJ. to DOUr, master mode
0
50
ns
~(MIRD)
Delay time, SCLKJ. to LRClk, master mode
-20
20
ns
~(SDD1)
Delay time, LRClk to DOur, slave mode
50
ns
~(SDD2)
Delay time, SCLKJ. to DOUr, slave mode
50
ns
7-339
7-340
4 Parameter Measurement Information
SClK
tci(MFSD)
Fsyne
tci(MDD)
I..
1
1
1
~I
I
~I
14
DOUT
/MSB
X
MSB-1
X
X"'-____________________
lRClk _ _ _ _ _ _ _
Figure 4-1. SCLK to Fsyne and DOUT - Master Mode 3
SClK
"'IMFSD)
~j
1
Fsyne
tci(MDD)
DOUT
1\
I..
I
I
/MSB
1
td(MIRD)
I"
lRClk
~I
~I
X
MSB-1
X
X
Figure 4-2. SCLK to Fsyne, DOUT, and LRClk - Master Modes 4 and 6
SClK~
Fsync
DOUT
i\'-_____________
"'IMF,::;
~
tci(MDD)
I
~I~_,",
14
/
lSB
X"'--______ X"'-_______
~~j--------'----J
lSB-1
~
lRClk~lj
Figure 4-3. SCLK to Fsyne, DOUT, and LRClk - Master Mode 5
7-341
SCLK
tcI(MFSD)
Fsyne
+--lJ~--"",,1
.~
tcI(MDD)
DOUT
!\~-------------------~
14
I
~~LS-B~)(~__L_SB_-_1-J)(_______
~I
_________________I~/p-----------------tcI(MIRD) ',.
LRClk
.
Figure 4-4. SCLK to Fsync, DOUT, and LRClk - Master Mode 7
I
I
I
SCLK
LRClk
-------~X~I~---------------..
tcI(SDD1)~
tcI(SDD2)4
I_il:-_-17~~~~~.:X
DOUT _ _ _ _ _ _ _ _ _ _ _
Xil:--------~
16
Figure 4-5. SCLK to LRClk and DOUT ;... Slave Mode 0, Fsync High
tsu1
~,
I
, tsu3
~I,.
I
tsu4
SCLK
I
I
I
Fsyne
I
I
DOUT
~
I
LRClk
td(SDD2)-l+--+l
17
X
J
Figure 4-6. SCLK to Fsyne, LRClk, and DOUT - Slave Mode 2, Fsyne Controlled
7-342
>C
5 Application Information
7-343
.....
l,
RM
t
n
I!,o
RP
n
I!,o
LM
IL
LP
n
IL
D-
.....
.....
n
EXFS f----« l--
I
>
•
I
I
t
4
~
a.
E
.!!
4
~ 3
a.
3
E
.!!
0
'S
a.
0
'Sa. 2
2
.5
I
.5
~
I
!iii:
:>
:>
0
0
-1~~--~~--~~--~~--~~~
-50 -40 -30 -20 -10 0 10 20 30
11K -Input Clamp Current - mA
40
Figure 8. Characteristics of the TL7726
(Vref 5 V)
=
50
-1~~~~~~--~~--~~--~~
-10 -8
-6 -4 -2 0
2
4
6
11K -Input Clamp Current - mA
8
10
Figure 9. Characteristics of the TL7726
at Low Current (Vref 5 V)
=
A complementary circuit has the effect that if the input sees a voltage that is more negative than GND, the resulting
current (flowing outward) also increases very rapidly. In this voltage range, the circuit behaves like a very low resistance
diode having a forward voltage of only some tenths of a millivolt.
The characteristics of the 1L7726 cannot be properly represented using linear axes. Therefore, mixed log/linear axes
are used (see Figure 10) so the voltage limits over a very wide range can be shown in detail.
Overvoltages at device pinS are often of very short duration but of high amplitude. The hex clamping circuit must be
able to provide reliable protection under these conditions, so the device has been designed such that a continuous current
of 50 rnA is permissible at the clamp input. However, the maximum power dissipation of the package must be taken into
account in case such currents flow simultaneously into several inputs.
Extremely rapid operation of the hex clamping circuit has been achieved with the capacitor CI (see Figure 6), which
essentially consists of the collector-base (Miller) capacitance of Q5. This ensures that Q5 is immediately switched on
if there are rapid voltage changes. Figure 11 shows that voltage limiting is achieved with virtually no delay. Figure 12
shows the circuit used to make these measurements. Since this circuit reacts to practically any voltage change, it must
be noted that several microseconds elapse from a change of amplitude until a new stable value is reached (see
Figure 13).
8-12
II
I
OND-200mV
...:: ~
...::
/.
F:--
II
-1 f,IA
-10 f,IA -100 f,IA -1 mA-10mA -100mA -
1
5OmV":
J
-25mA
iI
-100mA
25mA -10mA
-lmA
- 100 f,IA
- 10 f,IA
If,IA
I
Vref- 50mV 4
-{-Vref + 200mv
I
I
I
I
I
I
I
GND
Figure 10. Current and Voltage Limits of TL7726
8
Generator Output,
VA
8
>
4
J§!
2
I
o
~.
2
TL7728
Clamp Input,
Va
o
o
50 100 150 200 250 300 350 400 450 500
Tlme-ns
Figure 11. Behavior of TL7726 With Rapid Voltage Changes
r-----+--
5V
Pulse Generator
500
500
OND
Figure 12. Measurement Circuit
8-13
/
6
,....,
VA
4
V"
/
2
/'
VB
o
o
2
3
4
5
6
Time-lUI
7
8
9
10
Figure 13; Settling Time at the Input of the Hex Clamping Circuit
Application Examples Using the TL7726
The TL7726 was developed to protect the inputs of linear (analog) ICs against overvoltage and to ensure the reliable
operation of these components both in demanding applications and in harsh environments. A typical application of the
TL7726 is extremely simple, as shown in Figure 14.
T
RV (typically 10 len)
AO
A1
A2
·,V,
~~
.v.
A5
·V
....=:
'---
'---
REF
TL7726
GND
Vcc= 5V
TLC1543
11-lnput ADC
(6 of 11 Inputs shown)
GND
-=1Circuit to be
Protected
..L
Figure 14. Typical Application of the Hex Clamping-Circuit TL7726
The TL7726 is ideal for protecting the inputs of the TI range of multiple input analog-to-digital converters. The TL7726
can reliably handle currents up to 50 rnA. The series current-limit resistor (RV) is chosen to limit the current to this level.
The clamp voltage level is set to be within 200 mV of Vref and GND.
The reference voltage pin (REF) of the hex clamping circuit is connected to the supply voltage (Vcd of the circuit to
be protected whose inputs are connected to the CLAMP inputs (see Figure 14). The requirement for series resistors
depends on the particular application. If the input signal to be limited is supplied by a comparatively high-impedance
source, and if only undefined currents must be prevented from flowing into the substrate of the circuit to be protected,
such resistors are not needed. However, in most cases, voltages of considerable amplitude can be expected. These are
coupled into the signal inputs and cause significant interference. In such cases, the TL7726 should also be protected
against damage; this can only be ensured if the current that flows can be limited to an acceptable amount with a series
resistor. The TL7726 reliably diverts currents up to ±50 rnA where the'flifference of the voltage between the input
voltage (VIK) and the reference voltage (depending on whether current is flowing to REF orGND) is only a few hundred
millivolts. The RV series resistor can be chosen over a wide range depending on the requirements of the circuit to be
protected. Resistors from a few tens of ohms up to several tens of kilohms ·(Le., 20 n to 40 ill) can be used.
8-14
When choosing series resistors used to limit current flowing into the 11..7726, consideration should be given to the
maximum power dissipation [PD(max)l that the 11..7726 can withstand. The limiting factors are the maximum
permissible device temperature of lS0°C and the thermal resistance (RaJA) between the device and ambient temperature.
The following expression applies (see the 11..7726 data sheet):
PD(max) - lSOoC - TA
RaJA
where:
TA - ambient temperature
RaJA (D package) - l72°C/W
RaJA (P package) - lOS°c/W
given the following derating factors
Derating factor (D package) - lIRaJA - S.8 mW/oC
Derating factor (P package) - l/RaJA - 9.5 mW/oC
Current Flow
Consideration should be given to the path taken by the current that flows into the 11..7726. A positive current flowing
into a CLAMP terminal is channeled to GND (see Figure 6 and Figure 15); similarly, a negative current flows to REF.
Since REF is normally connected to the Vee rail supplying other circuits, this voltage source must be able to withstand
the current flow. In most cases, only short duration voltages need to be limited; this usually means that the filter capacitor
in the power supply must be of sufficiently large capacitance and the ground return of sufficiently large size to prevent
excessive ground bounce.
Vee
REF
Figure 15. Current Flow Paths
Summary
Until recently, the protection of analog circuits in harsh environments where the inputs could be subjected to undefined
overvoltages was only possible with considerable extra circuitry. Although this circuitry gave protection against
destruction, it often limited the performance of the protected device. The availability of the 11..7726 hex clamping circuit
now provides bo!h reliable and transparent protection operation for up to six analog inputs in a single package.
8-15
8-16
Microcontro//er Based Data
Acquisition Using the TLC2543
12-Bit Seriaf-Out ADC
•
I
-
TEXAS
INSTRUMENTS
8-17
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its'products or
to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to
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TI warrants peiformance of its semiconductor products and related software
to the specifications applicable at the time of sale in accordance with TI's
standard warranty. Testing and other quality control techniques are utilized to
the extent TI deems necessary to support this warranty. Specific testing of all
parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential
risks of death, personal injury, or severe property or environmental damage
(''Critical Applications'1.
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN
LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion ofTI products in such applications is understood to be fully atthe risk
of the customer. Use of TI products in such applications requires the written
approval of an appropriate TI officer. Questions concerning potential risk
applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications,
adequate design and operating safeguards should be provided by the
customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design,
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Copyright © 1995, Texas Instruments Incorporated
8-18
Contents
Title
Page
Introduction ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 8-21
Scope of this Application Report .......................................................... 8-21
The 11.C2543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-21
Interface Timing ................................................................. 8-21
Minimum Number of Data Transfers per Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-22
Serial Peripheral Interface (SPI) ......................................................... 8-23
11.C2543 to SPI Interface Timing ................................................... 8-23
Software Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-24
TLC2543 TO TMS370 Microcontroller Interface •••••••••••••••••••••••••••••••••••••••••••••• 8-26
Microcontroller Features ............................................................... 8-26
Interface Circuit .........................................•............................ 8-26
Software .... , .. , ........•......•......•.............•..•............................ 8-26
List 1 ................................................................................... 8-27
Opto-Isolated 12-Bit Data Acquisition System .............................................. 8-29
TLC2543 to H81325 Microcontroller Interface ••.••••••••••••••••••••••••••••••••••••••••••••.• 8-31
Microcontroller Features ............................................................... 8-31
Interface Circuit ................................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-31
Software ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-31
List2 ••••••••••••••••••••••••••••••••••••••••••••••••••.•••••••••.••••••••••••••••••••••• 8-32
TLC2543 to MC68HCll Microcontroller Interface. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • . • • • •• 8-35
Microcontroller Features ............................................................... 8-35
Interface Circuit .....•.............................•.................. . . . . . . . . . . . . . . .. 8-35
Software ..................... '.' . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-35
List3 ............................................................................. , ••••• 8-36
TLC2543 to SOC51 Microcontroller Interface ••••••••••••••••••••••••••••••••••••••••••••••••• 8-38
Microcontroller Features ...........................•................................... 8-38
Interface Circuit ........................................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-38
Software ............................................................................ 8-38
List4 •••••••••••••••••••••••••••••••••.•••••••••••••••••••••••••••••••••••••••••••••••••• 8-39
Analog Considerations •••••••••••••••••••••••••••••••••••••••••••••.•••••••••••••••••••••• 8-41
Power Supply Decoupling ...................................... ',' . . . . . . . . . . . . . . . . . . . . .. 8-41
Grounding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-41
Board Layout'. . .. .... . . . . . . . . .. . . . . . . . .. . . . .. . . . . . .. . . . .. . . . . . . . . . .. . . . . . . . . . . .. . . . .. 8-41
Appendix A •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••.•• 8-42
References .......................................................................... 8-42
Acknowledgement ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-42
8-19
List of mustratioDS
Figure
Page
1.
2.
3.
4.
5.
6.
7.
S.
9.
10.
11.
12.
13.
14.
8-21
8-22
8-22
8-23
8-24
8-24
8-25
8-25
8-26
8-30
8-31
8-35
8-3S
8-41
~20
7itle
1LC2543 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . .•
TIming for 16-Clock Transfer Using CS With MSB First .....•................................
TIming for 16-Clock Transfer Not Using CS With MSB First ...............................•..
Serial Peripheral Interface - Internal Structure and Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . ..
1LC2543 to SPI Interface TIming .•.••....•.........•..............•...••..•.•..••......•
Flowchart for Main Program of 1LC2543 to 1MS37OCOIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . • ..
Flowcharts of Subroutine DATAIN and STORE for 1LC2543 to 1MS37OCOIO Intelface Software ....
Flowcharts of Subroutine ADC for 1LC2543 to 1MS37OCOI0 Interface Software .....•............
1LC2543 to 1MS370COIO Interface Circuit ...........•...............................•....
Opto-lsolated 12-Bit Data Acquisition System ............•.........................•.......
1LC2543 to HS/300 Microcontroller Interface Circuit .................•......................
1LC2543 to MC6SHCS11E2 Microcontroller Interface .•........................... ; .........
1LC2543 to SOC51 Microcontroller Interface ...............................................
1LC2543 to Microcontroller Interface: Grounding and Decoupling Scheme . . . . . . . . . . . . . . . . . . . . . ..
Introduction
Scope of this Application Report
This application report describes how to construct 12-bit data acquisition systems using the TI..C2543 serial-out
analog-to-digital converter (ADC) in conjunction with a range of four popular microcontrollers.
The four microcontrollers used are the TMS370, H8/300, 68HCli and 80C51.
TheTLC2543
The TLC2543 is a 12-bit ADC which uses the switched capacitor successive approximation technique to perform the
conversion process and provides a maximum sampling rate of 66k samples per second (KSPS) while using only 1 rnA
(typical) of supply current.
The block diagram of the TLC2543 is shown in Figure 1. Anyone of eleven analog input channels can be selected by
programming the four mOst significant bits (MSBs) of the eight bit channel/mode control byte applied serially to the
DATA INPUT terminal of the device. In addition three internal test voltages [Vref':' Vref+ and (Vref+ - Vref_)/2] can
be applied to the converter for calibration or other purposes by applying the appropriate code to the same four MSBs.
The four least significant bits (LSBs) of the channel/mode control byte are used to select the output data length (8, 12
or 16 bits), the output data order (MSB first or LSB first) and whether unipolar (binary) or bipolar (2's complement
around (Vref+ - Vref-)/2) format is required.
Input
Address
Register
AI NO
Analog
Inputs
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
Data
Input
UOClock
14-Channel
Analog Input
MUX
Sample
and
Hold
Serial
Data Out
EOC
•
•
•
12·Blt Resolution ADC
66-KSPS Sampling Rate
11 Analog Input Channels
•
•
•
Low Supply Current -1 mA (Typ)
Power-Down Mode -4 !iA (Typ)
SPI Compatible Serial Interface
Figure 1. TLC2543 Block Diagram
Interface Timing
Four transfer methods are available for obtaining the full 12 bits of resolution from the TLC2543. Either 12 or 16 clock
cycles can be used for each conversion and data transfer.
A chip select (CS) pulse can be inserted at the start of each conversion or only once at the beginning of each sequence
of conversions with CS remaining low until the sequence is completed.
8-21
FigUre 2 shows the timing for the method which uses 16 clock cycles for each conversion and data transfer cycle and
which inserts CS between each of these transfer cycles. Figure 3 shows the timing for the method which uses 16 clock
cycles for each conversion and data transfer cycle but ~erts CS only once at the start of each sequence of conversions.
This application report describes various microcontroller interfaces, each of which uses 16 clock cycles for each
conversion data transfer. CS is applied at the start of each conversion and data transfer. This method allows for the
general case where one or mOre conversions may be required. It 8Iso simplifies the required software.
~-,~----------------~,,~--~
H- tau
> 1.425118
CLO~~ _-+1.......
\~
1
jJ
f1.-f1
~ ........ "
1
~~
. I
1
DATA
OUT
------------~~
1
____L
I
DATA
INPUT
EOC
r-
~t=1
I
:~
1
:
\\I----h,I .
J
r,~r-+-:-
If- tconv
16-Clock Transfer Using CS (MSe Firat)
C7
1
<10118
---JI
Figure 2. Timing for 16-Clock Transfer Using CS With MSB First
~-'~------------------------------------~(/\~------------~"\~----~--H- tau 1.42~
I
CLO~~--II_...
~"
f1
>
118
II
jJ
8
1
~~
DATA
OUT
------------~~:
DATA
lei (EOC.DATA)~
<10,..
__,___ +-1'
INPUT
1
EOC
:
1
'
16-Clock Transfer Not Using CS (MSe Firat)
I_
1-
14-1
1
: ~
1
Jrlll------------------------------------------~\(~;--;"1
I1
1
1
C7
I
',H
ogonv _ 1
L.
<10118
-I
Figure 3. Timing for 16-Clock Transfer Not Using CS With MSB First
Minimum Number
0'
Data Transfers per Channel
It should be noted that in any single data transfer cycle between the 'ILC2543 and the chosen microcontroller the data
output from the ADC is the result of the previous conversion. The software listings included in this application report
have been written for the general case where the conversion results may be required for any .individual channel or
sequence of channels. In this case the program included for each microcontroller interface nlust be run at least twice per
channel so that valid data corresponding to the required analogue input channel and ADC mode is delivered.
Software can be written to implement the consecutive channel scanning mOde of operation of the 'ILC2543. In this case
the result from the fIrst analog-to-digital conversion should be ignored or overwritten.
8-22
Serial Peripheral Interface (SPI)
The fastest and most efficient method of implementing a data transfer between the 'ILC2543 and a microcontroller is
to use the serial peripheral interface (SPI) of the microcontroller, if this is available.
The TMS370 (Texas Instruments), HS/300 (Hitachi) and MC6SHC II (Motorola) all offer SPls (or the equivalent) in
a subset of each of these families of microcontrollers. The HS/300 offers a serial communications interface (SCI) which
can be configured to operate in a similar way to that of the standard SPI's offered by the TMS370 and MC6SHCIl.
The principle features of the SPI are:
•
•
•
•
Simultaneous serial data input and output
Synchronous operation
Provision of frequency programmable serial clock
Data transfer complete flag
Figure 4 shows the structure of the SPI. In this case the TMS37OCOlO is used to illustrate the main elements of the
interface.
TLC2543
TMS370C010
SPI Master (Master/Slave
DATA OUT
SOMI
I
DATA INPUT
SOMO
SerIal Input Buffer
(SPIBUF)
I
I
MSB
110 CLOCK
=1)
i''r
Shift Register
(SPIDAT)
I
r-
LSB
SPICLK
Figure 4. Serial Peripheral Interface -Internal Structure and Data Flow
The microcontroller can be configured by software to perform as the SPI master or slave. When operating as the master,
data is input to the SPI shift register (SPIDAT) via the slave out master in (SOMI) terminal. At the same time data is
output from the SPIDAT via the slave in master out (SIMO) terminal.
The SPI functions as follows. The SPIDAT should be loaded with the flrst byte of data to be sent. This automatically
initiates the transmission of this byte. During this transmission time data is received at the other end of the SPIDAT shift
register. The SPI !NT FLAG is regularly checked. As soon as the last bit of the input data byte is received the SPI !NT
FLAG is set to 1. This then signals that the received byte can be read from the serial input buffer (SpmUF) and that the
SPIDAT is ready to accept the next byte of data to be transmitted.
Additional SPI features which apply to the speciflc microcontrollers are described in their respective sections which
follow.
TLC2543 to SPllnterfaee Timing
The timing digram for the 16 clock transfer 'ILC2543 to SPI interface is shown in Figure 5. The channel select/mode
data is read into the 'ILC2543 on the positive going edges of the I/O clock and analog-to-digital conversion results are
read into the microcontroller on the negative going edges of the I/O clock.
8-23
cs l!--------I'i.,.j~--~rj~
I/O
CLOCK
DATA
IN
DATA
OUT
EOC
Figure 5. TLC2543 to SPllnterface Timing
Software Flowcharts
Figures 6, 7, and 8 show the flow charts for the main program and subroutines used in the TLC2543 to TMS370COIO
interface software shown in this application report. The same program structure also applies to the other three interfaces
included in this report.
rl
1
..
START
2
CALL
SUBROUTINE
DATAIN
+
3
CALL
SUBROUTINE
ADC
+
4
CALL
SUBROUTINE
STORE
+
5
~
JUMP TO
START
}
}
}
}
Reads channellmode data for TLC2543 into microcontroller via parallel I/O port.
(reformats channellmode data if serial data is sent LSB first).
Puts channellmode data into accessible register.
Derives destination address for STORE from channel data.
Provides CS high to low transition prior to conversion.
Provides serial 110 CLOCK to TLC2543.
Sends channel/mode data to TLC2543.
Receives MSbyte then LSbyte of previous NO conversion.
Stores MSbyte In even address of selected RAM space.
Stores LSbyte in odd address of selected RAM space
(all addresses mapped to corresponding channel number).
Jump to start for next conversion
Figure 6. Flowchart for Main Program of TLC2543 to TMS370C010
8-24
+
Read ChanneUM.oda
Data Into Choaan
Register
+
t
Store MSBYTE In Evan Address
Of RAM
(Channel # Dapandant)
Map Channal Numbers
t
To Registers
Or RAM
+
Store LSBYTE In Odd Address
Of RAM
(Channel' Dependant)
Put Daatlnatlon
Address Into Choaan
Register
+
STORE
+
Return
~
DATAIN
Figure 7. Flowcharts of Subroutine DATAIN and STORE for TLC2543
to TMS37OC010 Interface Software
Racalva LS Byte Of Prevloua
Convaralon Raault and
Store In LS BYTE
NO
Recelva MS Byte Of Prevloua
Convaralon Raault and
Store In MS BYTE
Figure 8. Flowcharts of Subroutine ADC for TLC2543 to TMS370C010 Interface Software
8-25
TLC2543 TO TMS370 Microcontroller Interface
Microcontroller Features
Within the family of TMS370 microcontrollers there are several versions which contain a serial peripheral interface
(SPI) facility. One of these versions should be chosen to implement the interface method described below. One such
version is the TMS37OCOIO which is used to illustrate the method.
Interface Circuit
Figure 9 shows the circuit interconnections for the lLC2543 to TMS37oCOIO miCrocontroller interface. Note that no
extra logic is required to implement this interface.
5V
5V
VCC
VCC
1/0 CLOCK i+--ISPICLK
DATA INPUT
SPISIMO
DATA OUT
SPISOMI
CS
D7
Analog
Inputs
TMS370
8x10kC
VSS
Figure 9. TLC2543 to TMS370C010 Interface Circuit
Depending upon the layout of the particular printed circuit board used it may be necessary to insert a small value
capacitor of between 50 and 100 pF between the JlO CLOCK input of the lLC2543 and ground. This has the effect of
ensuring that data applied to the DATA INPUT terminal of the lLC2543 is valid before the positive going transition
of the JlO CLOCK.
The positive reference, REF+, to the 1LC2543 is provided directly from the VCC+ supply.
The four digital interface terminals, JlO CLOCK, DATA INPUT, DATA OUT, and CS, of the 1LC2543 connect directly
to the SPICLK, SPISIMO, SPISOMI and D7 terminals respectively of the TMS370COIO.
The operation mode and channel number of the lLC2543 is determined by the serial data which is sent to its DATA
INPUT terminal.
Software
List I contains the software listing for the program which controls the interface illustrated in Figure 5. The software
consists of the main program and three subroutines called DATA IN, ADC and STORE. DATAIN reads in the channel
select and mode control data into a holding register and maps the channel select number to a corresponding pair of
registers between R64 and R91. The mapping vector is held in register RIO. ADC provides the chip select pulse, controls
the SPI operation, and puts the MSByte and LSByte of each conversion result into registers R20 and R21 respectively.
STORE puts the MSByte into the even number register .and the LSByte into the odd number register mapped by the
contents of register RIO.
8-26
The user can put channel select and ADC mode control data into the holding register within the microcontroller, via the
8-bit wide port A bidirectional JlO port, using a bank of eight toggle switches as shown in Figure 9. Alternatively, the
mode and channel data can be sent to the microcontroller holding register via the asynchronous serial communications
interface (SCI). This option is available only on those versions of the TMS370, such as the TMS370C020, which include
both SPI and SCI interfaces. Additional software to control the SCI must be appended to the software shown in List 1
to provide this method of control.
List 1
LINE
LOC
OBJ
1
SOURCE
;*
2
i
*
*
*
*
*
*
*
*
*
*
*
*
*
*
3
;* TLC2543 to TMS 370Cx10 Interface Program
4
;*
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
0030
0031
0037
0039
003d
003e
003f
0021
0022
0023
002c
002d
002e
002f
7ffe
2e
4000
4000
4002
4003
4007
400a
400b
400d
400f
4012
4014
4016
4018
40la
40lc
40le
4020
5260
fd
* 88400000
8b7ffe
b5
2121
2123
f7802f
2280
2130
2207
2130
2203
213d
2222
213e
31
Ob
4022 '8e402d
4025
'8e403e
4028 '8e409d
*
*
*
*
*
;* This program reads channel select and mode *
;* control data (provided by toggle switches) *
;* into the microcontroller, using subroutine *
; * DATAIN.
*
;* It then provides the control signals to
*
;* the TLC2543 to perform a 12 bit analog to *
;* conversion, using subroutine ADC. It
*
;* finally stores the MSByte and LSByte of
*
;* each conversion in consecutive even and
*
;* odd number registers respectively starting *
;* at R64 corresponding to channel 0, using
*
;* subroutine STORE.
*
;* * * * * * * * * * * * * * * *
SPICCR .EQU P030
;* * * * * * * *
SPICTL .EQU P03l
;*
*
SPIBUF .EQU P037
;*
*
SPIDAT .EQU P039
i*
*
SPIPC1
.EQU PO 3D
;*
*
SPIPC2
.EQU P03E
;* Name Peripheral
*
SPIPRI
.EQU P03F
;* Registers
*
APORT 2 .EQU P02l
;*
*
ADATA
.EQU P022
;*
*
.EQU P023
ADIR
;*
*
DPORTI
.EQU P02C
j*
*
.EQU P02D
DPORT2
j*
*
.EQU P02E
DDATA
i*
*
DDIR
.EQU P02F
;* * * ~ * * * *
RESET
.EQU 7FFEH
;Reset vector named
.DBIT 7,DDATA
CSBIT
;TLC2543 Chip Select bit
;named CSBIT
.TEXT 4000H
;Main Program
START
MOV ~60H,B
LDSP
MOVW ~4000H,A
MOV A,RESET
CLR A
MOV A,APORT2
MOV A,ADIR
MOV #080H,DDIR
MOV #80H,A
MOV A,SPICCR
MOV #07,A
MOV A,SPICCR
MOV #03,A
MOV A,SPIPCl
MOV #22H,A
MOV A,SPIPC2
SPIF
.DBIT 6,SPICTL
MSLSB. DBIT 1, R11
CALL DATAIN
CALL ADC
CALL STORE
;Start program at 4000H
,
;Set SP to address 60H
;Set reset vector
Configure SPI for 8-bit
character length.
Configure SPICLK
function and direction.
Configure SPISOMI and
SPISIMO pin functions.
SPI INTFLAG named SPINTF
Bit 1 of R11 named MSLSB
8-27
List 1 (Contl,nued)
LINE
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
~28
LOC
402b
SOURCE
OBJ
'00d3
JMP START
,
; Subroutine :- DATAIN
,
402d
402f
9122
d10b
DATAIN
4031
4033
4034
4035
4036
4037
4039
403b
53fO
cc
cc
cc
cc
5c02
5840
d10a
AND tOFOH,B
RR B
RR B
RR B
RR B
MPY t002,B
ADD t40H,B
MOV B,R10
403d
f9
RTS
,
MOV ADATA,B
MOV B,Rll
Read ADC mode/channel
Put ADCmode/channel
in R11
Retain channel number
• • • • '* • • •
•* Map
channel numbers
•
• to registers R64-R91 *
• R10 contains storage *
* address
*
• Even numbers - MS Byte·
.. Odd numbers - LS Byte *
•
..
* * * * *
..
*
; Subroutine :- ADC
,
403e
4040
4043
4044
4046
4047
4049
404b
404d
4051
4053
2203
a4802e
b2
'06fd
c5
5l2e
2207
2131
'76020b19
120b
2139
ADC
4055
4059
'a74031fc
a21437
FLAG1
405c
LOOP 1
71390b
405f
4063
'a7403lfc
a21537
4066
'77020b32
406a
406c
406e
4072
120b
2139
'a74031fc
a21537
4075
4077
4079
407d
120b
2139
'a74031fc
a21437
4080
4082
4084
4086
4088
4089
408b
408e
4090
4092
4094
4096
4097
4099
2208
d516
dd14
dfl6
b2
'06f9
421614
2208
d517
dd15
dfl7
b2
'06f9
421715
FLAG2
LS1ST
FLAG3
FLAG4
MOV t003H,A
;Set ADC Chip Select high.
SBIT1 CSBIT
;Chip Select stays high
DEC A
;whi1e A is not o.
JNE LOOP1
CLR B
MOV B,DDATA
;CS goes low
MOV .7,A
MOV A,SPICTL
; Enable SPI transmission
JBIT1 MSLSB,LS1ST
MOV R11,A
MOV A,SPIDAT
MOV Rll, SPIDAT ;Send mode/channel data
ito TLC2543
JBITO SPIF,FLAG1;If SPIF-O, repeat check.
MOV SPIBUF,R20 ;Put received MS Byte
;in R20
MOV Rll, SPIDAT ;Send mode/channel data
;to TLC2543
JBITO SPIF,FLAG2;If SPIF=O, repeat check.
MOV SPIBUF,R21 ;Put received LS Byte
; in R21
JBI~O MSLSB,RETURN ;If MSLSB-O, go
ito RETURN
MOV R11,A
MOV A,SPIDA";l'
JBITO SPIF,-FLAG3 If SPIF-O, repeat check.
MOV SPIBUF, R21
Put received LS Byte
in R21
MOV R11,A
MOV A,SPIDAT
JBITO SPIF,FLAG4 If SPIF-O, repeat check.
MOV SPIBUF,R20
Put received MS Byte
in R20
MOV 1I08,A
* * *
* * *
CLR R22
* Reformat MS Byte *
RRC R20
*
*
RLC R22
* Put result in R20 **
DEC A
JNZ LOOP2
•
*
MOV R22, R20
* * * * • •* •* *
MOV t08,A
CLR R23
•* * * * *
RRC R21
• Reformats LS Byte •
,RLC R23
•
DEC A
Put result in R21 •
JNZ LooP3
MOV R23,R21
• * • * * * * **
.. ..
LOOP2
LOOP 3
..
...
..
•
•
List 1 (Continued)
LINE
LOC
129 409c
OBJ
f9
SOURCE
RETURN RTS
130
131
;Subroutine :- STORE
132
133
134
135
136
137
138
139
409d
409f
40al
40a3
40a5
40a7
1214
9bOa
d30a
1215
9bOa
f9
STORE
HOV R20,A
HOV A,@Rl0
INC Rl0
HOV R21,A
HOV A,@Rl0
RTS
. END
;Put HS Byte into even
;address contained in Rl0
; (R10)+1
;Put LS Byte into odd
;address contained in Rl0
Opto-l80lated 12·81t Data Acquisition System
The serial nature of the data flow between the 'ILC2S43 analog-to-digital converter and the accompanying
microcontroller makes this ADC an ideal choice for isolated 12-bit data acquisition. Figure 10 shows an opto-isolated
system which uses four optocouplers to provide a 3-kV isolation barrier.
Note that the optocouplerwhich routes conversion result data from the TLC2S43 to the microcontrolleris a single device
and does not share the same piece of silicon with any of the other optocouplers used. This ensures that the full 3 kV of
isolation is maintained between the ADC andmicrocontroller.
The choice ofVP0610 P-channel enhancement MOSFETs avoids the use of an extra inverter stage for each optocoupler
driver. In addition, the relatively low input capacitance of the VP061 0 (typically IS pF) allows data rates up to 100kHz
to be achieved without the need for external buffers to be added at the outputs of the 'ILC2S43 and TMS370.
8-29
VCC1
-----~
VCC~'--""
'1
( r - - + - - 4 H VCC
.-----+-1 SPICLK
470R
110 CLOCK
H---"
TLC2543
TMS370
VP0610
470R
DATA INPUT
H---"
470R
DATA OUT
AINO
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
SPISOMI
-=D7
470R
VPOS10
CS
VSSI---"
AO
A1
A2
A3
}
ADCMode
A4
A5
AS
A7
}
ADC Channel
Number
...- - - - - 1 VSS
-=- /,-=-
3kV
. Isolation Barrier
Figure 10. Opto-Isolated 12-Blt Data Acquisition System
8-30
TLC2543 to H8J325 Mlcrocontroller Interface
Microcontroller Features
The individual members of the H8 family of microcontrollers can be differentiated by various criteria, for example the
inclusion or otherwise of an on-board 8-bitresolution analog-to-digital converter (ADC). Those members which include
an ADC generally cost between 10 and 20 percent more than their counterparts which do not.
System requirements such as ADC resolution, remote location of ADC, flexibility, and total cost all influence the final
choice of microcontroller architecture. The HS/325, used for this application report, does not include an on-board ADC
but provides IK of RAM, 32K of ROM, and two serial I/O ports. It is therefore well suited to interfacing with the
1LC2543 serial output ADC.
Interface Circuit
Figure II illustrates a typicall2-bit data acquisition system which uses the HS/325 microcontroller to coordinate the
operation of the 1LC2543 ADC via one of its serial (SCI) ports. The circuit uses the HS's S-bit parallel I/O port 4 to
route ADC channel and mode information into the microcontroller. This information could be provided by a host system
data bus or, as in Figure 6, by a bank of eight manually operated toggle switches situated on the same printed circuit board
as the microcontroller.
5V
H8I325
TLC2543
VCC
AINO
Analog
Inputs
SCKOIP5.2
1/0 CLOCK
AIN1 DATA INPUT 1 + - - - 1 TxDO/P5.0
AIN2 DATA OUT J - - - + i RxDO/P5.1
AIN3
CS 1+---1 P6.0
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
GND
VCC
MDO
MD1
XTAL
EXTAL
=
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Vss
20 MHz
(max)
}
ADCMode
}
ChM,O
Number
':'
NOTE: Single Chip Mode (MOO = M01 = 1)
Figure 11. TLC2543 to H8I300 Mlcrocontroller Interface Circuit
Software
List 2 shows the program which was written to coordinate the interface. It uses three subroutines to implement the overall
interface to the 1LC2543. The first of these is called DATAIN which reads ADC channel and mode information into
the microcontroller. It also maps converter channel numbers to corresponding addresses in RAM where conversion
results can be stored. In this case the addresses from 0040H to 0067H were chosen to store the results. The most
significant byte of each result is placed in an even address and the least significant byte of each result is placed in the
corresponding adjacent odd address.
The conversion result of each channel is stored in left justified format and therefore occupies the upper 12 bits of the
16-bit words which occupy even addresses from 0040H up to 0066H.
The second subroutine to be used is ADC. This begins by producing a chip-select high pulse. The trailing negative edge
of this pulse is rapidly followed by the transmission of channel and mode information to the converter.
8-31
List 2
LINE
LOC
OBJ
1
;*
3
4
5
6
i*
;*
11
12
13
;*
14
i*
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
FFDD
FFDB
FFD8
FFDA
FFDC
FFD9
FFB8
FFBA
FFB5
FFB7
FFB9
FFBB
31
32
1000
~
*
* * * * * * * * * * * * * * * *
This program contains subroutines DATAIN, ADe,
FORMAT and STORE.
DATAIN reads channel number and mode data into the
microcontroller via Port4. "ADC" controls A to D
conversion. "FORMAT" changes conversion results from
LSB first format to MSB first format. ·Store" places
results in memory addresses 40 to 5B (MS Bytes in even
addresses, LS Bytes in odd addresses) according to
channel number.
* * * * * * * * * * * * * * * • * * *
;*
;*
;*
;*
10
*
TLC2543 to H8 Microcontroller Interface Program.
;*
;*
;*
7
8
9
*
*
*
*
*
•
•
•
•
*
*
*
*
Define special function register names •
, *
;
RDR
TDR
SMR
SCR
SSR
BRR
P5DDR
P5DR
P4DDR
P4DR
P6DDR
P6DR
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
H'FFDD
H'FFDB
H'FFD8
H'FFDA
H'FFDC
H'FFD9
H'FFB8
H'FFBA
H'FFB5
H'FFB7
H'FFB9
H'FFB,B
ORG H'lOOO
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
, 59
60
61
62
63
64
65
66
67
*
;*
;*
2
30
SOURCE
;Receive Data Register - RDR
;Transmit Data Register - TDR
;Serial Mode Register - SMR
;Serial Control Register - SCR
;Serial Status Register - SSR
;Bit Rate Register - BRR
;Port5 Data Direction Register
;Port5 Data Register - P5DR
;Port4 Data Direction Register
;Port4 Data register - P4DR
;Port6 Data Direction register
;Port6 Data Register
;Sets start of program
* Main Program *
1000 79001000
1004
1008
100A
100C
100E
1010
1012
1014
1016
lOlA
101E
1022
1026
102A
7907FDOO
F984
39D8
F93l
39DA
F90l
39D9
F901
6A89FFB9
5EOOI082
5EOOI02C
5EOOlOB4
5EOOIOAC
40DC
102C
102E
1032
1034
1036
103A
103E
1040
1042
1046
1048
104A
104E
FA05
7FBB7000
lAOA
46FC
7FBB7200
6AOCFFB7
731C
461E
7EDC7370
47FA
34DB
7FDC7270
7EDC7360
START
,
MOV.W tH'lOOO, RO
MOV.W RO, @H'OOOO
MOV.W IIH'FDOO, SP
MOV.B #H'84, RIL
MOV.B RlL, @SMR:8
MOV.B jH'31,RIL
MOV.B RlL, @SCR:8
MOV.B tH'Ol,RIL
MOV.B RlL, @BRR:8
MOV.B tH'Ol, RIL
MOV.B RIL, @P6DDR
JSR @DATAIN:16
JSR @ADC:16
JSR @FORMAT:16
JSR @STORE:16
BRA START
;Sets reset vector to START
;Sets contents of Stack Pointer
;* •
* * * * * * * * * * * * *
;* Sets up serial port
*
;* registers for simultaneous.
;* transmit and receive
*
;*
;*
*
* * * * * * * • * * * * * *
;Sets Rl(Low Byte) to OlH
;Set BitO of Port6 as Output
;Read in ADC channel/mode data
;Do AID conversion
;Reformat AID conversion result
;Store A/D conversion result
;Repeat above routine.
* Subroutine ADC which controls the conversion process •
ADC
MOV.B IIH'05, R2L
BSET #0, @P6DR:8
CSHIGH DEC R2L
BNE CSHIGH
BCLR #0, @P6DR:8
MOV.B @P4DR, R4L
BTST il, R4L
BNE LSBYTE
MSBYTE BTST #7, @SSR:8
BEQ MSBYTE
MOV.B R4H, @TDR:8
BCLR #7, @SSR:8
TESTB61 BTST 116, @SSR:8
Put 05 in R2L
TLC2543 chip select goes high
(R2L) - 1
If not zero, CS stays high
TLC2543 chip select goes low
Puts channel/mode data in R4L
Is LSBF of channel/mode data
If not, do LSBYTE first
Is TDR empty ?
If not empty, repeat check.
Put channel/mode data in TDR
Reset TDRE bit of SSR to 0
Is receive shift reg. empty?
List 2 (Continued)
LINE
LOC
OBJ
SOURCE
68
69
70
1052 47FA
1054 23DD
BEQ TESTB61
MOV.B @RDR:8, R3H
71
1056 7FDC7260
105A 68D3
BCLR #6, @SSR: 8
MOV.B R3H, @R5
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
105C
lOSE
1060
1064
1066
1068
106C
1070
1072
1074
731C
4620
7EDC7370
47FA
34DB
7FDC7270
7EDC7360
47FA
OAOD
2BDD
BTST #1, R4L
BNE RETURN
LSBYTE BTST #7, @SSR:8
BEQ LSBYTE
MOV.B R4H, @TDR:8
BCLR #7, @SSR: 8
TESTB62 BTST #6, @SSR:8
BEQ TESTB62
INC R5L
MOV.B @RDR:8, R3L
1076 7FDC7260
107A 68DB
BCLR #6, @SSR:8
MOV.B R3L, @R5
107C 731C
107E 46C2
1080 5470
BTST #1, R4L
BNE MSBYTE
RTS
RETURN
;If not empty, repeat check
;Put MS Byte of conversion
;resu1t in R3H
;Reset RDRF bit of SSR to 0
;Put MS Byte in even address
;mapped by channel number.
;Is LSBF of channel/mode data 0
;If not, return from subroutine
;Is TDR empty?
;If not empty, repeat check
;Put channel/mode data in TDR
;Reset TDRE bit of SSR to 0
;Is receive shift reg. empty?
;If not empty, repeat check
; (R5L) + 1·
;Put LS Byte of conversion
;resu1t in R3L
;Reset RDRF bit of SSR to 0
;Put LS Byte in odd address
;mapped by channel number.
;Is LSBF of channel/mode data 0
;If not, go to MSBYTE
;Return from subroutine
,
; * Subroutine "DATAIN" which reads in ADC channel/mode data *
,
1082
1086
108A
108E
1090
1092
1094
1096
1098
109C
109E
79040000
79050000
6AOCFFB7
OCCD
110D
110D
110D
110D
79060002
50E5
8D40
DATAIN
10AO
10A2
10A4
10A6
10A8
10AA
F008
110C
1204
1AOO
46F8
5470
MOV.B #H'08, ROH
NEXTBIT SHLR R4L
ROTXL R4H
DEC ROH
BNE NEXTBIT
RTS
,
10AC 68D3
MOV.W #H'OOOO, R4
MOV.W #H'OOOO, R5
MOV.B @P4DR, R4L
MOV.B R4L, R5L
SHLR R5L
SHLR R5L
SHLR R5L
SHLR R5L
MCiv.W #0002, R6
MULXU R6L, R5
ADD.B #H'40, R5L
STORE
MOV.B R3H, @R5
INC R5L
MOV.B R3L, @R5
10B2 5470
RTS
,
F008
1103
1207
1AOO
46F8
OC73
F008
110B
i*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
;*
*
*
*
*
*
*
*
*
*
;*
*
*
*
*
*
*
*
*
* *
i*
*
*
*
*
*
*
*
*
* *
;*
;* Maps channel numbers to
*
;* even addresses 40H to 5AH*
;* Put address in R5L
*
;Put 08 in ROH
;* Reformats channel/mode data*
;* from MSB first to LSB first*
* Subroutine "STORE" stores A/D conversion results in RAM *
10AE OAOD
lOBO 68DB
10B4
10B6
10B8
10BA
10BC
lOBE
lOCO
10C2
;Puts channel/mode data in R4L
;Puts (R4L) in R5L
i*
* * * * * * * * *
;* Retain only channel
*
;* number in R5L
*
;Store MS Byte in even address
;corresponding to channel
; number
; (R5) + 1
;Store LS Byte in odd address
;corresponding to channel
; number
;Return from subroutine
* Subroutine "FORMAT" changes received data format
* ( LSB first ) into MSB first format
FORMAT
LOOP1
LOOP2
MOV.B #H'08, ROH
SHLR R3H
ROTXL R7H
DEC ROH
BNE LOOP1
MOV.B R7H, R3H
MOV.B IIH'08, ROH
SHLR R3L
*
*
Put 08 in ROH
* * * * *
*
*
* * * *
Reformats MSBYTE
*
*
*
* * * * * *
* * * * * * * * *
*
*
*
*
Put 08 in ROH
List 2 (Continued)
LINE
136
137
13B
139
.140
141
8-34
10C4
10C6
10CB
10CA
10CC
10CE
LOC
120F
1AOO
46FB
OCFB
5470
OBJ
SOURCE
ROTXL R7L
DEC ROH
BNE LOOP2
MOV.B R7L, R3L
RTS
END
*
*
*
Reformats LSBYTE
* * * * * * * *
Return from subroutine
*
*
*
"
TLC2543 to MC68HC11 Microcontroller Interface
Microcontroller Features
All members of the MC68HCli family of microcontrollers contain an SP!. As is the case for the TMS370, the user is
able to set the idle level of the serial clock of the 68HCll. This eliminates the need for an external inverter to be used
to invert the microcontroller's serial clock output prior to its arrival at the TI.C2543's serial clock input.
The 68HC 11 DO, 68HCIID3 and 68HC71ID3 versions do not contain an on-boardADC. One of these three devices may
prove to be the most cost effective choice when used with the TI.C2543. All other versions contain either an 8- or lO-bit
resolution ADC.
Interface Circuit
Figure 12 shows the circuit diagram of the interface between the 68HC 11 and the TI.C2543. The microcontroller device
type used to illustrate this interface is the 48-pin dual-in-line version of the MC68HC811E2.
The master in slave out (MISO), master out slave in (MOSI) and serial clock (SCK) terminals of the SPI are available
as the alternative, user selectable, functions of port D pins PD2, PD3, and PD4 respectively. When the SPI is configured
to operate as a master, the SSIPD5 terminal can be used as an output to drive the chip select (CS) terminal of the
'lLC2543. This leaves all other bidirectional I/O ports of the microcontroller uncommitted and available for other uses.
Note that no extra glue logic is required to implement the interface.
5V
TLC2543
MC68HC811E2
vee
vee
1/0 CLOCK
SCKO/PD4
DATA INPUT
MISOIPD2
DATA OUT
MOSUPD3
es
ss/PD5
5V
GND
MODe
VSS
10M
PCO
PC1
PC2
PC3
}A~C_
PC4
PCS
PC6
}-'"
Number
PC7
VSS
-:
-:
NOTES: A. Configured for single chip mode of operation
B; Maximum SPI data rate = crystal frequency/S
Figure 12. TLC2543 to MC68HC811E2 Mlcrocontroller Interface
Software
The listing of the program which was written to coordinate and control the interface between the TI.C2543 and the
68HC811E2 is shown in List 3. The software consists of the main program and two subroutines named TI.C2543 and
STORE. TI.C2543 begins by providing the ADC's chip select pulse. It then reads in channel/mode data via the port C
parallel I/O port and subsequently sends this data to the TI.C2543 via the MOSI terminal of the SPI. At the same time,
the first byte of the result from the previous analog-to-digital conversion is received at the MISO terminal of the SPI.
List 3
LINE
LOC
OBJ
2
3
4
5
6
A
A
A
A
A
*
*
*
8 A
9 A
8-36
Interface Program
** This program contains subroutines "TLC2543" and "STORE".
7 A
10 A
llA
12 A
13A
14 A
15 A
16 A
17 A
18 A
19 A
20 A
21 A
22 A
23 A
24 A
25 A
26 A
27 A
28 A
29 A
30 A
31 A
32 A
33 A
34 A
35 A
36 A
37 A
38 A
39 A
40 A
41 A
42 A
43 A
44 A
45 A
46 A
47 A
4B A
49 A
50 A
51 A
52 A
53 A
54 A
55 A
56 A
57 A
5B A
59 A
60 A
61 A
62 A
63 A
64 A
65 A
66 A
67 A
6B A
SOURCE
* * * * * * * * * * * * * * * * * * * * *
** TLC2543 l2-bit Serial Out AOC to MC68HCll Micr9controller **
1 A
*
*
*
*
"TLC2543" reads in AOC mode control and channel select
* data via Port C. It then sends this data to the TLC2543
* and at the same time receives the result of the previous
* conversion.
* "STORE" puts the results into addresses $30 to $4B with
* MSBytes in even addresses and LSBytes in odd addresses.
* Channel 0 result in addresses $30 and $31
*
* Channell result in addresses $32 and $33 etc.
*
*
*
*
*
*
*
* * * * * * * * * * * * * * * * * * * * *
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
1000
0000
0003
0007
0008
0009
0028
0029
002A
OOFO
OOFI
00F2
BASEADO
PORTA
PORTC
OORC
PORTD
OORD
SPCR
SPSR
SPOR
MSBYTE
LSBYTE
TEMP
$1000
$00
$03
$07
$OB
$09
$2B
$29
$2A
$FO
$Fl
$F2
F800
ORG
$FBOO
LOS #$0070 Set Stack Pointer
START
LOAA
i$3E
OORD,X
STAA
LOAA
i$50
SPCR,X
STAA
LOAA
#$00
STAA
OORC,X
PORTO,X#$20
BSET
JSR
TLC2543
STORE
JSR
BRA
START
Register block start
Port A Data Register
Port C Data Register
Port C Data Oir Reg
Port 0 Data Register
Port 0 Data Oir Reg
SPI Control Register
SPI Status Register
SPI Data Register
MSBYTE address
LSBYTE address
TEMP address
0000
F800
F802
F804
F806
F808
F80A
F80C
F80F
FB12
F8l5
863E
A709
8650
An8
8600
A707
lC0820
BOF8l7
BOF84A
20E9
F8l7 CElOOO
F8lA B602
F8lC lC0820
F8lF
F820
F822
F825
4A
26FA
100820
lE0302l0
F829 AG03
F82B A72A
FB20 lF29BOFC
F83l A62A
F833 97FO
F835lE0302l0
FB39 A603
FB3B A72A
FB30
FB4l
FB43
FB45
lF29BOFC
A62A
97Fl
lE0302EO
*
#BASEADO
LOX
#02
LOAA
PORTO,X#$20
CSHIGH
BSET
* Set Port A bit 6 (TLC2543 CS) high
OECA
BNE
CSHIGH
PORTO,X#$20
BCLR
PORTC,X#$02 LSB
BRSET
i f LSBF set.
*
MSB
PORTC, X
LOAA
SPOR,X
STAA
*
and receive MSByte
LOOPI
BRCLR
SPSR,X#$BO LOOPI
*
repeat check
LDAA
SPOR,X
STAA
MSBYTE
BRSET
PORTC,X#$02 RETURN
* If MSB/LSB-first bit = 1, return
LSB
LOAA
PORTC, X
STAA
SPOR,X
and
receive
LSByte
*
LOOP2
BRCLR
SPSR,X#$BO LOOP2
LOAA
SPOR,X
LSBYTE
STAA
PORTC,X#$02 MSB
BRSET
Start @ $FBOO
Load 3EH in AA
Store 3EH in OORD
Load SOH into AA
Set SPI as master
Load 00 into AA
Set PORTC ~ all I/Ps
;ADC CS high
Do A/D conversion
Store results
Repeat above
TLC2543
AOC CS low
Do LSB first
Load Chan/mode data
Send the data to ADC
If SPIF=O,
Store MSByte
Load chan/mode data
Send the data to ADC
If SPIF-O,
repeat "heck
Store LSByte
-List 3 (Continued)
LINE
LOC
OBJ
SOURCE
* If MSB/LSB-first bit - 1 go to MSB
69 A
70 A F849 39
RETURN
71A
72A
*
* S'routine stores MSByte in even address
73 A
74 A
75 A
76 A
77A
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
95
96
97
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
•
•
•
•
F84A
F84C
F84F
F851
F853
F855
F856
F857
F858
F859
F85A
F85C
F850
F85F
F861
F863
F864
F866
F866
F868
A603
CE0030
97F2
86FO
94F2
46
46
46
46
16
8602
3D
OOF2
96FO
A7F2
08
96F1
A7F2
A7F2
39
RTS
LSByte in odd address
Channel 0 result in $30 and $31
Channell result in $32 and $33 etc.
(Reserve addresses $30-$4B for results
* of all channels)
STORE
LDAA
PORTC,X
LOX
'$30
STAA
TEMP
LDAA
'$FO
ANnA
TEMP
RORA
RORA
RORA
RORA
TAB
LOAA
'$02
NUL
STD'
TEMP
LDAA
MSBYTE
TEMP, X
STAA
INX
LDAA
LSBYTE
TEMP, X
STAA
TEMP,X
STAA
RTS
END
TLC2543 to 80C51·Mlctocontrolier Interface
Microcontroller Features
The 80CSI microcontroller family does not provide an SPI or equivalent facility. In order to implement the interface
with the TI..C2543 analog-to-digital converter, it is necessry to use software to synthesize the operation of an SPI. This
results in a slower data transfer rate which is governed by the microcontroller's instruction cycle times. These are, in
turn, influenced by the clock frequency of the microcontroller. The highest clock frequency possible should therefore
be selected for the microcontroller to minimize instruction cycle times and thus optimize the data transfer rate of the
interface.
Interface Circuit
Figure 13 shows the circuit for the interface of the TI..C2S43 to the 80CSI microcontroller. The YO CLOCK, DATA
INPUT and CS inputs to the 1LC2543 are provided via the bidirectional parallel port 1 terminals Pl.O, Pl.1, and Pl.3
respectively. Conversion result data from the 1LC2S43 is received by the 8OCS1 through the PI.2 terminal of port 1.
The channel select/mode data is input to the microcontroller via port 3.
SV
80C51
TLC2543
Vee
VCC
I/O CLOCK H-----1 P1.O
DATA INPUT H-----1 P1.1
DATA OUT 1 - - -..... P1.2
CSH-----1 P1.3
P3.0
P3.1
P3.2
P3.3
}
}-..
P3.4
P3.S
P3.8
P3.7
Vss
GND
AOCU...
Number
-::-
Figure 13. TLC2543 to 80C51 Mlcrocontroller Interface
Software
The listing for the program used to control the interface circuit mentioned above is shown in List 4. As for the other
microcontroller interface programs, it consists of a m8in program and two subroutines - TI..C2543 and STORE.
The main program initializes the directions of the port 1 YO terminals. P1.2 is configured as an input. P1.0, P1.l, and
Pl.3 are all programmed to perform as outputs. The chip select terminal of the TI..C2543 is set high by setting P1.3.
TI..C2S43 is then called. This subroutine contains the instructions which synthesize the SPI function and controls the
exchange of data between the microcontroller and the TI..C2543. The least significant bit first (LSBF) flag which is bit
1 of the channel select/mode data byte is checked to determine which byte (most significant - MSByte,least significant
- LSByte) of the conversion result is to be expected first.
The SPI function is synthesIzed by using the accumulator in conjunction with the rotate left through carry (RLC)
instruction to act as the SPI shift register. The following sequence provides a slow motion version of the SPI function.
The first bit of the first byte of the conversion result is read into the carry (C) bit. The contents of the accumulator are
rotated left through carry and the first bit of the channel select/mode data is then output from PI.I. The first pulse of
the serial clock is then provided by toggling the PI.O bit of port 1 first high and then low. This sequence is repeated seven
more times to complete the transfer of the first byte of data.
8-38
-The second byte of data is tranferred between the TLC2543 and the SOC51 by repeating the entire sequence of eight sets
of data transfer and clock pulse. The MSByte is placed in register 2 (R2) and the LSByte is placed in register 3 (R3).
The subroutine SIDRE is used to map the MSByte and LSByte conversion results into even and odd number RAM
addresses corresponding to the particular channel number which has been selected.
List 4
LINE
LaC
OBJ
SOURCE
1
2
3
4
5
6
7
8
9
10
11
0100
0100
0103
0106
0108
010A
010C
010E
0110
758150
759004
C290
D293
74FF
3112
313F
80EE
0112
0114
0115
0117
ACBO
EC
C293
20E112
011A
011C
011E
011F
0121
0123
0125
0127
0128
0129
012C
012E
0130
0131
0133
0135
0137
0139
013A
013B
7D08
A292
33
929:!D290
C290
DDF5
FA
EC
20E112
7D08
A292
33
9291
D290
C290
DDF5
FB
EC
20E1DC
013E 22
013F
0140
0142
0143
EC
54FO
C4
75F002
. 12
13
14
15
16
17
18
19
20
j*
;*
*
56
57
*
*
*
*
*
*
*
*
*
*
*
*
*
*
i*
* * * * * * * * * * * * * * *
;This program reads mode/channel select data into the
;80C51 via Port 4 and transmits this data to the
;TLC2543 at the same time as reading the result from
;the previous conversion and storing the result in an
;adjacent pair of memory locations from 30H to 4CH .
;MsByte - Even Address LSByte - Odd Address
;MSByte Channel 0 in 30H, MSByte Channell in 32H etc.
START:
ORG 100H
MOV SP,#50H
MOV P1,#04H
CLR Plo 0
SETB Plo 3
MOV A,#OOFFH
ACALL TLC2543
ACALL STORE
JMP START
TLC2543:MOV R4,P3
MOV A,R4
CLR Plo 3
JB ACC.1,LSB
MSB:
LOOP1:
LSB:
LOOP2:
44
55
*
TLC2543 12-bit Serial Out ADC to BOC51
33
45
46
47
48
49
50
51
52
53
54
*
Microcontro11er Interface Program
34
35
36
37
,38
39
40
41
*
*
;*
i
22
42
43
*
;*
;*
21
23
24
25
26
27
28
29
30
31
32
*
MOV R5,#OB
MOV C,P1.2
RLC A
MOV Plo1,C
SETB P1.0
CLR Plo 0
DJNZ R5,LOOP1
MOV R2,A
MOV A,R4
JB ACC.1,RETURN
MOV R5,#OB
MOV C,P1.2
RLC A
MOV Plo1,C
SETB P1.0
CLR Plo 0
DJNZ R5,LOOP2
MOV R3,A
MOV A,R4
JB ACC.1,MSB
;Initialise Stack Pointer
;Initialize port 1 I/O Pins
;Set I/O clock low
;Set chip select high
; Read mode/channel data into R4
;and A
;Set chip select low
;If bit 1 of A is 1,
;do LSByte first
;Load MS bit counter
;Read data bit into carry
;Rotate into accumulator
;Output mode/channel bit
;Set I/O clock high
;Set I/O clock low
;Get/send another bit
;Put MSByte in R2
;Put mode/channel data in A
;
;Load LS bit counter
;Read data bit into carry
;Rotate into accumulator
;Output mode/channel bit
;Set I/O clock high
;Set I/O clock low
;Get/send another bit
;Put LSByte in R3
;Put mode/channel data in A
;If bit 1 of R4 is 1,
;do MSbyte next
RETURN: RET
STORE:
MOV A, R4
ANL A,#OFOH
SWAP A
MOV B,#02
Put mode/channel data in A
Retain only channel number
Swap high and low nibble of A
8-39
List 4 (Continued)
0146
0147
0149
014A
014B
LINE
A4
2430
F9
LOC
OBJ
r
SOURCE
58
59
60
F7
61
62
63
64
014C 09
014D EB
014E F7
66
67
EA
MOL AS
ADD
MOV
MOV
MOV
A, to"30H
R1,A
A,R2
@R1,A
65
68
INC R1
MOV A,R3
MOV @R1,A
69
70
014F 22
71
72
73
RET
END
;Add 30H to aooumulator
Put MSByte in oorresponding,
even number address :Channel 0 in address 30H,
Channell in address 32H eto.
Put LSByte in oorresponding
odd' number address :Channel 0 in address 31H,
Channell in address 33H eto.
-Analog Considerations
Power Supply Decoupling
Care should be taken with the design of the printed circuit board when using 12-bit devices such as the TI..C2543. The
power supply tenninal of each analog integrated circuit should be separately decoupled to the analog ground using a
0.1 J,IF ceramic capacitor. The inclusion of a 10 J,IF tantalum capacitor in parallel with the ceramic capacitor at each
device supply terminal is also recommended, particularly in noisy environments.
Grounding
Separate ground return paths for analog and digital components back to the power supply should be used to prevent any
noise currents induced by digital components from passing through the analog ground return path. These noise currents
can induce noise voltages to occur in the analog ground return and thus corrupt the analog signal. Remember that, for
a 5-V full scale signal, only 600 microvolts represents approximately half an LSB for a 12-bit ADC.
The important point to remember is that all ground return paths have a fmite impedance. This impedance should be kept
to a minimum by the use of wide printed circuit board tracks or ground planes where possible. A separate star.connected
ground topology is recommended for the analog components. This involves connecting each analog component's
ground terminal to a central star point, which can then be connected via a wide printed circuit track to the power supply
ground connection.
Board Layout
Digital devices and power switching elements should be kept as far away physically from analog components, such as
the TI..C2543, as possible. Particular attention should be paid to the use of switching power supplies. The high frequency
switching currents which flow in the ground return paths of these space saving power blocks can introduce several LSBs
of noise into 12-bit analog circuits. Linear regulated power supplies should be used or, if essential, switching regulators
should be as far as possible from the analog circuitry with their outputs decouple.
Judicious use of ground planes can help to reduce analog ground impedances.
Figure 14 illlustrates a typical bypassing scheme for the TI..C2543-to-TMS370 microcontroller interface.
DIrection Of
Current Flow
T
-=-
0.1 Ilf
Creamlc
101lf T
Tantalum
T
-=-
-=-
VCC
VCC
TLC2543
TMS37OC010
0.11lf
Creamlc
External
>-'---4AINO 110 CLOCK ....-~ SPICLK
AIN1
AIN2 DATA INPUT
SPISIMO
10llfT
Tantalum
Connection to
output of
Po_r Supply-
-=-
T
-=-
AIN3
AIN4
AIN5
O.11lf
AIN6
Creamlc AIN7
AIN8
AIN9
AIN10
DATA OUT
CS
GND
Connection To Output
Of Power Supply +
Data/Address
BU8(If Usad)
SPISOMI
D7
GND
DIrection Of
Ground Return
To Po_r Supply
Current Flow
Figure 14. TLC2543 to Mlcrocontroller Interface: Grounding and Decoupllng Scheme
8-41
Appendix A
References
HS/325 Hardware User's Manual
HS/300 Series Programming Manual
Embedded Microcontrollers and Processors Vol 1
M6SHCll Reference Manual (1991)
TMS370 Family Data Manual (1993)
TLC2543 Data Sheet (Dec. '93)
Hitachi
Hitachi
Intel Corporation
Motorola Inc.
, Texas Instruments Incorporated
Texas Instruments Incorporated
Acknowledgement
I wish to express my thanks to Mike Williams (Microcontroller Field Applications Engineer - Northern European
Industrial Segment) for his useful comments on the TMS370 interface.
8-42
--
Interfacing the TLC32040
Family to the TMS320 Family
~1ExAs
INSTRUMENTS
8-43
IMPORTANT NonCE
Texas Instruments (TI) reserves the right to make changes to its products or
to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to
verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software
to the specifications applicable at the time of sale in accordance with TI's
standard warranty. Testing and other quality control techniques are utilized to
the extent TI deems necessary to support this warranty. Specific testing of all
parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential
risks of death; personal injury, or severe property or environmental damage
("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN
LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion ofTI products in such applications is understood to be fully atthe risk
of the customer. Use of TI products in such applications requires the written
approval of an appropriate TI officer. Questions concerning potential risk
applications should be directed to TI through a local SC seles office.
In order to minimize risks associated with the customer's applications,
adequate design and operating safeguards should be provided by the
customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described
herein. Nor does TI warrant or represent that any license, either express or
implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might
be or are used.
Copyright © 1994, Texas Instruments Incorporated
Contents
Title
Page
1 Introduction
8-47
2 TLC32040 Interface to the TMS320101E15 ••••.••••••••••••.•••..•.•.••••••••.••.•.•••••.•..
2.1 Hardware.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.1.1 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.1.2 Hardware Description .......................................................
2.2
Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.2.1 Initializing the Digital Signal Processor .........................................
2.2.2 Communicating with the TLC32040 ...........................................
2.2.3 TLC32040 Secondary Communication .........................................
8-49
8-49
8-49
8-50
8-50
8-50
8-50
8-51
3 TLC32040 Interface to the TMS32020/C25 ••••••••••••••••••••••••••••••••••••••••••••••••••
3.1 Hardware Description .............................................................
3.2
Software ......................................................................
3.2.1 Initializing the TMS32020/C25 ....................................................
3.2.2 Communicating with the TLC32040 ................................................
3.2.3 Secondary Communicating - Special Considerations ...................................
8-53
8-53
8-53
8-54
8-54
8-54
4 TMS32040 Interface to the TMS320C17 ••.••••..•••..••••.••...••••••.••••• ;...............
4.1 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.2 Software.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.2.1 Initializing the TMS32OC17 .......................................................
4.2.2 AIC Communications and Interrupt Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.2.3 Secondary Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8-57
8-57
8-58
8-58
8-58
8-59
5 Summary •••••.•••••.••••.••.••••.•••••••••••.••••.••••••••••••••••.••••••••••••••••••• 8-61
Appendices
Title
Page
A TLC32040 and TMS32010 Flowcharts and Communication Program •...••••.••.••.•••••••••••• 8-63
A.1 Flowcharts...................................................................... 8-63
A.2 Communication Program List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-64
B TLC32040 and TMS32020 Flowcharts and Communication Program •••.••.•••••••.•••••••••.•. 8-69
B.1 Flowcharts ...................................................................... 8-69
B.2 Communication Program List. ...................................................... 8-72
C TLC32040 and TMS320C17 Flowcharts and Communication Program •..•..••.•...••.••.•••..•. 8-81
C.1 Flowcharts ...................................................................... 8-81
C.2 Communication Program List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-84
8-45
Dlustrations
Figure
1.
2.
3.
4.
5.
6.
8-46
TItle
AlCInterfacetoTMS320101E15 ......•.......•....... , ................•...........•
AIC Interface to TMS32020/C25 ...........•...... '" .............•....•......•......
Operating Sequence for AlC-TMC320201C25 Interface ..................................
Asynchronous Communication AIC- TMS32020/C25 Interface •...........................
AlC Interface to TMS3:2.OC17 .............•....................•....•..•....•......
Operating Sequence for AIC-TMS32OC17 ............................................
Page
8-49
8-53
8-53
8-54
8-57
8-58
1
Introduction
The TLC32040 and TLC32041 analog interface circuits are designed to provide a high level of system
integration and perfonnance. The analog interface circuits combine high resolution AID and DIA converters,
programmable filters, digital control and timing circuits as well as programmable input amplifiers and
multiplexers. Emphasis is placed on making the interface to digital signal processors (the TMS320 family) and
most microprocessors as simple as possible. This application report describes the software and circuits
necessary to interface to numerous members of the TMS320 family. It presents three circuits for interfacing
the TLC32040 Analog Interface Circuit to the TMS320 family of digital signal processors. Details of the
hardware and software necessary for these interfaces are provided.
To facilitate the discussion of the software the following definitions and naming conventions are used:
1. >nnnn - a number represented in hexadecimal.
2. Interrupt service routine - a subroutine called in direct response to a processor interrupt·
3. Interrupt subroutine - any routine called by the interrupt service routine.
4. Application program (application routine) - the user's application dependent software (e.g., digital
filtering routines, signal generation routines, etc.)
8-47
.....
6-48
2
TLC32040 Interface to the TMS32010/E15
2.1
Hardware
Because the n..C32040 (Analog Interface Circuit) is a serial-I/O device, the interface to the TMS3201O, which
has no serial port, requires a small amount of glue-logic. The circuit shown in Figure 1 accomplishes the
serial-to-parallel conversion for the AlC operating in synchronous mode.
Parts List
2.1.1
The interface circuit for the TMS32010 uses the following standard logic circuits:
1. One SN74LS138 3-to-8-line address decoder
2. One SN74LS02 Quad NOR-Gate
3. One SN74LSOO Quad NAND-Gate
4. One SN74LS04 Hex Inverter
5. One SN74LS74 Dual D-Flip-Flop
6. Two SN74LS299 8-bit Shift Registers
TLC32040
74LS299
...-- S1
TMS320101C15
DIN
L......-
YO
Y1 I - -
G1
U1
AOIPAO
A1IPA1
A21PA2
S1
'Ci2
QH'
Ci2
S1 U2
< f'Ci2
1
8
h
••
a•
f
A
SR f-
Ul~
-
B
C
SHIFT
CLK
74LS299
~
D18
••
•
DO
WE
CLKOUT
iN'f
18
(
/
~
--..-.
-
8,
S1
QH' ICi2
S1 U3
Ci2
./
h
••
a•
~
SR
Ir-
Q D
U3
f.4-
DR
~
~
74LS74
MSTRCLK
E'ODX
Figure 1. Ale Interface to TMS320101E15
8-49
2.1 ~2
Hardware Description
The SN74LS138 is used to decode the addresses of the ports to which the lLC32040 and the interface logic
have been mapped. If no other ports are needed in the develo~nt system, this device may be eliminated and
the address lines of the 1MS32010 used directly in place of Yl and YO (see Figure 1).
'
Since the interface circuits are only addressed when the 1MS3201 0 executes an IN or an OUT instruction, gates
Ll, L2, L3, L4, and L5 are required to enable reading and writing to the shift registers only on these instructions.
The TBLW instruction is prohibited because it has the same timing as the OUT instruction. Flip-flop U4 ensures
that the setup and hold times of SN7 4LS299 shift registers are met.
Although not shown in the circuit diagram, it is recommended that the CLR pins of the SN74LS299 shift
registers as well as the RESET pin of the AlC be tied to the power-up reset circuit shown in the AIC data sheet.
This ensures that the registers are clear when the AIC begins to transfer data and decrease the possibility that
the AIC will shift in bad data which could cause the AIC to shut down or behave in an unexpected manner.
2.2
Software
The flowcharts for the communication program along with the 1MS32010 program listing are presented in
Appendix A. If this software is to be used, and application program that moves data into and out of the transmit
and receive registers must be supplied.
2.2.1
Initializing the Digital Signal Processor
As shown in the flowcharts in Appendix A, the program begins with an initialization routine which clears both
the transmit/receive-end flag and the secondary communication flag, and stores the addresses of the interrupt
subroutines. The program uses the MPYK...PAC instruction sequence to load data memory locations with the
12-bit address of the subroutines. This sequence is only necessary if the subroutines are to reside in program
memory locations larger than >OOFF. Otherwise, the instructions LACK and SACL may be used to initialize
the subroutine-address storage locations. '
.
2.2.2
Communicating with the TLC32040
After the storage registers and status register have been initialized, the interrupt is enabled and control is passed
to the user's application routine (i.e., the system-dependent software that processes received data and prepares
data for transmission). The program ignores the first interrupt that occurs after interrupts are enabled (page 22,
line 207, IOINT routine), allowing the AlC to stabilize after a reset. The application routine should not write
to the shift registers while data is moving into (and out of) them. In addition, it should ensure that no primary
data is written to the shift registers between a primary and secondary data-communication pair. The first
objecive can be accomplished by writing to the SN74LS299 shift registers as quickly as possible after the
receive interrupt. The number of instruction cycles between the data transfers can be calculated from the
conversion frequency. By counting instruction cycles in the application program, it is possible to determine
whether the data transfer will conflict with the OUT instruction to the shift register. The second objective can
be accomplished by monitoring SNDFLO in the appl,ication program. If SNDFLO is true (>DOFF), secondary
communication has not been completed.
When the processors receives an interrupt, the program counter is pushed onto the hardware stack and then the
program counter is set to >0002, the location of the interrupt service routine, INTSVC (page 19, line 46). The
interrupt service routine then saves the contents of the accumulator and the status register and calls the interrupt
subroutine to which XVECT points. If secondary communication is to follow the upcoming primary
communication, XVECT, is set by the application program to refer to SINT1, otherwise, XVECT defaults to
NINT (i.e., the normal interrupt routine).
8-50
Because the interrupt subroutine makes one subroutine call and uses two levels of the hardware stack, the
application program can only use two levels of nesting (i.e., if stack extension is not used). This means that any
subroutine called by the application program can only call subroutines containing no instructions that use the
hardware stack (e.g., TBLW) and that make no other subroutine calls. In addition, if the application program
and communication program are being implemented on an XDS series emulator, the emulator consumes one
level of the hardware stack and allows the application program only one level of nesting (i.e., one level of
subroutine calls).
As shown in the flowcharts in Appendix A, the normal interrupt routine reads the AID data from the shift
registers and then sets the receive/transmit end-flag (RXEFLG). The application program must write the
outgoing D/A data word to the shift registers at a time convenient to the application routine. It should have the
restriction that the data be written before the next data transfer.
2.2.3
TLC32040 Secondary Communication
If it is necessary to write to the control register of the AlC or configure any of the AlC internal counters, the
application program must initiate a primary/secondary communication pair. This can be accomplished by
placing a data word in which bits 0 and 1 are both high into DXMT, placing the secondary control word (see
program listing page 19) in D2ND, and placing the address of the secondary communication subroutine,
SINTl, in XVECT. When the next interrupt occurs, the interrupt subroutine will call routine SINT1. SINTl
reads the AID information from the shift registers and writes the secondary communication word to the shift
registers.
8-51
8-52
3
TLC32040 Interface to the TMS32020/C25
3.1
Hardware Description
Because the TI.C32040 is designed specifically to interface with the serial port of the TMS320201C25, the
interface requires no external hardware. Except for CLKR and CLKX, there is a one-to-one correspondence
between the serial port control and data pins ofTMS32020 and lLC32040. CLKR and CLKX are tied together
since both the transmit and the receive operations are synchronized with SHIFT CLK of the lLC32040. The
interface circuit, along with the communication program (page 26), allows the AlC to communicate with the
TMS320201C2S in both synchronous and asynchronous modes. See Figures 2, 3, and 4.
3.2
Software
The program listed in Appendix B allows the AlC to communicate with the TMS32020 in synchronous or
asynchronous mode. Although originally written for the TMS32020, it will work just as well for the
TMS320C2S.
6V
TLC3202OIC25
L
CLKOUT
FSX
DX
FSR
DR
CLKX
CLKR
TLC32040
WORDiBYft
MSTRCLK
FIX
DX
FM
DR
SHIFTCLK
---1
Figure 2. AIC Interface to TMS320201C25
SHIFTCLK
-J/
FM.FIX~~__+-__+-__+-____~~______
-
DR
D15
SS·
D1~....._D_1_ _ _D_O_ _ _ __
DX
The S8Q!!!!lC8 .2!BPeration Is:
1. The J=SX or FSR pin Is brought low.
2. One 16-blt word Is transmitted or one 16-b1t byte Is received.
3. The FSX or ~pln is brought high.
4. The ~ or E DR pin emits a Iow-going pulse as shown.
Figure 3. Operating Sequence for AIC-TMC32020/C25 Interface
I
FSX
FSR
Figure 4. Asynchronous Communication AIC-TMS32020/C25 Interface
3.2.1
Initializing the TMS32020/C25
This program starts by calling the initialization routine. The working storage registers for the communication
program and the transmit and receive registers of the OSP are cleared, and the status registers and interrupt
mask register of the TMS32020/C25 are set (see program flow charts in Appendix B). The addresses of the
transmit and receive interrupt subroutines are placed in their storage locations, and the addresses of the routines
which ignore the first transmit and receive interrupts are placed in the transmit and receive subroutine pointers
(XVECT and RVECT). The TMS32020/C25 serial port is configured to allow transmission of 16-bit data
words (FO), the serial port format bit of the TMS32020/C25 must be set to zero) with an externally generated
frame synchronization (FSX and FXR are inputs, TXM bit is set to 0).
3.2.2
Communicating with the TLC32040
After the TMS32020/C25 has been initialized, interrupts are enabled and the program calls subroutine IGR.
The processor is instructed to wait for the first transmit and receive interrupts (XINT and RINT) and ignore
them. After the TMS32020 has received both a receive and a transmit interrupt, the IGR routine will transfer
control back to the main program and lOR will not be called again.
If the transmit interrupt is enabled, the processor branches to location 28 in program memory at the end of a
serial transmission. This is the location of the transmit interrupt service routine. The program context is saved
by storing the status registers and. the contents of the accumulator. Then the interrupt service routine calls the
interrupt subroutine whose address is stored in the transmit interrupt pointer (XVECT).
A similar procedure occurs on completion of a serial receive. If the receive interrupt is enabled, the processor
branches to location 26 in program memory. As with the transmit interrupt service routine (XINT, page 30, line
226), the receive interrupt service routine (page 30, line 194) saves context and then calls the interrupt
subroutine whose address is stored in the receive interrupt pointer (RVECT). It is important that during the
execution of either the receive or transmit interrupt service routines, all interrupts are disabled and must be
re-enabled when the interrupt service routine ends.
The main program is the application program. Procedures such as digital filtering, tone-generation and
detection, and secondary communication judgment can be placed in the application program. In the program
listing shown in Appendix B, a subroutine (C2ND) is provided which will prepare for secondary
communication. If secondary communication is required, the user must first write the data with the secondary
code to the OXMTregister. This data word should have the two least significant bits set high (e.g., >00(3). The
first 14 bits transmitted will go to the 01A converter and the last two bits indicate to the AlC that secondaly
communication will follow. After writing to the SXMT register, the secondary communication word should
be written to the 02ND register.
This data may be used to program the AlC internal counters or to reconfigure the AlC (e.g., to change from
synchronous to asynchronous mode or to bypass the bandpass filter). After both data words are stored in their
respective registerS, the application program can then call the subroutine C2ND which will prepare the
TMS32020 to transmit the secondary communication word immediately after primary communication..
3.2.3
Secondary Communicating - Special Considerations
This communication program disables the receive interrupt (RINT) when secondary communication is
requested. Because of the critical timing between the primary and secondary communication words and
because RINT carries a higher priority than the transmit interrupt, the receive interrupt cannot be allowed to
interrupt the processor before the secondary data word can be written to the data-transmit register. If this
situation were to occur, the AlC would not receive the coirect secondary control word and the AlC could be
shutdown.
8-54
In many applications, the AlC internal registers need only be set at the beginning of operation, (i.e., just after
initialization). Thereafter, the DSP only communicates with the AlC using primary communication. In cases
such as these, the communication program can be greatly simplified.
......
4
TMS32040 Interface to the TMS320C17
4.1
Hardware Description
As shown in Figure 5, the 1MS32OC17 interfaces directly with the TI..C32040. However, because the
1MS32OC17 responds more slowly to interrupts than the 1MS32010lE15 or the 1MS32020/C25, additional
circuit connections are necessary to ensure that the 1MS32OC17 can respond to the interrupt, accomplish the
context-switching that is required when an interrupt is serviced, and proceed with the interrupt vector. This
must all be accomplished within the strict timing requirements imposed by the TI..C32040. To meet these
requirements, FSX of the TI..C32040 is connected to the EXINT pin of the 1MS32OC17. This allows the
1MS320C17 to recognize the transmit interrupt before the transmission is complete. This allows the interrupt
service routine to complete its context-switching while the data is being transferred. The interrupt service
routine branches to the interrupt subroutines only after the FSX flag bit has been set. This signals the end of
data transmission.
The other hardware modification involves connecting the EODX pin of the TI..C32040 to the BIO pin of the
1MS32OC17. Because the 1MS32OC17 serial port accepts data in 8-bit bytes (see Figure 6) and the TI..C32040
controls the byte sequence (i.e., which byte is transmitted first, the high-order byte or the low-order byte) it is
important that the 1MS32OC17 be able to distinguish between the two transmitted bytes. The EODX signal
is asserted only once during each transmission pair, making it useful for marking the end of a transmission pair
and~chronizing the 1MS32OC17 with the AlC byte sequence. After synchronization has been established,
the BIO line is no longer needed by the interface program and may be used elsewhere.
Because the 1MS320C17 serial port operates only in byte mode, 16-bit transmit data should be separated into
two 8-bit bytes and stored in separate registers before a transmit interrupt is acknowledged. Alternatively, the
data can be prepared inside the interrupt service routine before the interrupt subroutine is called. From the time
that the interrupt is recognized to the end of the data transmission is equivalent to 28 1MS32OC17 instruction
cycles.
TLC32OC17
EXIMT
FSX
CLKOUT
DXO
FSR
DRO
SCLK
TLC32040
~
*
WORD/BYTE
FSX
MSTRCLK
DX
FSR
DR
SHIFTCLK
Figure 5. AIC Interface to TMS320C17
8-57
II
~'~I------~\~I------~;---
The s~ce .Qf..Qperation is:
1. The FSX or FSR pin is brought low.
2. One 8-bit word is transmitted or one 8-bit byte is received.
3. The EODX or EODR pins are brought low.
4. The FSX or FSR emit a positive frame-sync pulse that is four shift clock cycles wide.
5. One 8-bit byte is transmitted and one 8-bit byte is received.
6. The EODX and EODR pins are brought high.
7. The FSX arid FSR pins are brought high.
Figure 6. Operating $equence for Ale-TMS320C17
4.2
Software
The software listed in Appendix C only allows the AIC to communicate with the 1MS32OC17 in synchronous
mode. This communication program is supplied with an application routine, DLB (Appendix C, program
listing line 253), which returns the most recently received data word back to the AlC (digitalloopback).
4.2.1
Initializing the TMS320C17
The program begins with an initialization routine (!NIT, page 4O,line 120). Interrupts are disabled and all the
working storage registers used by the communication program are cleared. Both transmit registers are cleared,
the constants used by the program are initialized and the addresses of the subroutines called by the program
are placed in data memory. This enables the interrupt service routine to call subroutines located in
program-memory addresses higher than 255. After the initialization is complete, the 1MS32OC17 monitors
the FSX interrupt flag in the control register to establish synchronization with the AlC.
4.2.2
AIC Communications and Interrupt Management
Because the AIC FSX pin is tied to the EXINT line of the 1MS32OC17 and the delay through the interrupt
multiplexer, the interrupt service routine is called four instruction cycles after the falling edge of FSX. The
interrupt service routine (INTSVC, Appendix C, program listing, line 90) completes its context switching and
then monitors the lower control register, polling the FSX flag bit that indicates the end of the 8-bit serial data
transfer. If the FSX flag bit is set, the transfer is complete. After this bit is set, control is transferred to the
interrupt subroutine whose address is stored in VECT. The serial communication must be complete before data
is read from the data receive register.
When no secondary communication is to follow, the interrupt subroutines, NINTI and NINT2, are called. If
data has been stored in DXMT2 (the low-order eight bits of the transmit data word), which does not indicate
that secondary communication is to follow, the interrupt service routine calls NINTI when the first 8-bit serial
transfer is complete. NINTl immediately writes the second byte of transmit data, (Le., the contents ofDXMT2)
to transmit data register 0 (1R0). It then moves the first byte of the received data (Le.,the high-order byte of
the NO conversion reSUlt) into DRCVl. NINTI then stores in VECT the address ofNINT2. NINT2 is called
at the end of the next 8-bit data transfer and resets the FSX interrupt flag bit by writing a logic high to it. The
next interrupt (a falling edge ofEXINT) occurs before the interrupt service routine returns control to the main
8-58
program. This is an acceptable situation since the TMS32OC17, on leaving the interrupt service routine,
recognizes that an interrupt has occurred and immediately responds by servicing the interrupt
The interrupt subroutine NINT2 is similar in operation to NINTl. It stores the low-order byte of receive data
(bits 7 through 0 of the AID conversion result) and stores the address of the next interrupt subroutine in VECT.
NINT2 does not write to the transmit data register, TRO. This task has been left to the application program. After
the transmit data has been prepared by the main program and the data has been stored in DXMTI and DXMTI,
the main program stores the fIrst byte of the transmit data in transmit data register 0 (TRO).
4.2.3
Secondary Communications
The interrupt subroutines SINTI through SINT4 are called when secondary communication is required. For
secondary communication, DXMTI and DXMTI will hold the primary communication word. DXMTI and
DXMT4 will hold the secondary communication word. VECT, the subroutine pointer should then be initialized
to the address of SINTI. As with the normal (primary communication only) interrupt subroutines (i.e., NINTl
and NINT2), the secondary communication routines will change VECT to point to the succeeding routine (e.g.,
SINTI will point to SINT2, SINT2 will point to SINT3, etc.).
8-59
--
8-60
5
Summary
The n..C32040 is an excellent choice for many digital signal processing applications such as speech
recognition/storage systems and industrial process control. The different serial modes of the AIC
(synchronous, asynchronous, 8- and 16-bit) allow it to interface easily with all of the serial port members of
the TMS320 family as well as other processors.
8-En
8-62
A
A.1
TLC32040 and TMS32010 Flowcharts and
Communication Program
Flowcharts
Yes
c. SECONDARY DATA COMMUNICATIONS 1
...
a.MAIN
d. SECONDARY DATA COMMUNICATIONS 2
b. PRIMARY INTERRUPT ROUTINE
• Set, If need secondary•
.. Modify to call SINT2 •
... Modify to call NINT•
•••• Must execute bsfore transfer beginning.
A.2
Communication Program List
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029 0000
0030 0000
0001
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
8-64
***********.~**********~*~****~**********~*********~** ****
*
*
*
*
*
*
When using ,this program, the c,ircuit in the T.LC32040
*
data sheet or its equivalent circuit must be fused
*
port 1 are reserved for data receiving and data
*
transmitting. The TBLW command is prohibited because
*
it has the same timing as the OUT command. TLC32040 is*
used only in synchronous mode.
*
****************************************************** **~
0002
0003
0004
0005
0006
0007
0008
0009
OOOA
OOOC
OOOD
OOOE
OOOF
OOFF
0001
*
RXEFLG
SNDFLG
DRCV
DXMT
D2ND
XVECT
ACHSTK
ACLSTK
SSTSTK
ANINT
ASINT1
ASINT2
TMPO
*
SET
ONE
*
*
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
>02
>03
>04
>05
>06
>07
>08
>09
>OA
>OC
>OD
>OE
OF
EQU
EQU
>FF
>01
Reset vector.
AORG
B
F900
OOOD
receive and xmit end flag.
secondary communication flag.
receive data storage.
xmit data storage.
secondary data storage.
interrupt address storage.
ACCH stack.
ACCL stack.
Status stack.
interrupt addres$ 1
interrupt address 2
interrupt address 3
temporary register.
>0000 program start address.
EPIL jump to initialization.
*********************************************************
* =================
*
* Interrupt vector.
*
*
=====-==-=-==---=
*
* When secondary communication, modify the content of
*
* XVECT to the address of secondary communication and
*
* store secondary data in D2ND.
*
* ex.
*
LAC
ASINT1,0 modify XVECT
*
*
SACL XVECT,O
*
*
*u
I
*
D2ND,0
store secondary data.
LAC
*
*
*********************************************************
.....
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091
0092
0093
0094
0095
0096
0097
0002
0002
0002
0003
0004
0005
0006
0007
0008
0009
OOOA
OOOB
OOOC
AORG
7COA
6EOI
5808
5009
2007
7F8C
6508
7A09
7BOA
7F82
7F8D
>0002
interrupt vector.
INTSVC
SST
SSTSTK
push status register.
LDPK ONE
set data pointer one.
SACH ACHSTK
push ACCH.
SACL ACLSTK
push ACCL.
XVECT,O
load interruput address.
LAC
CALA
branch to interruupt routine.
ZALH ACHSTK
pop ACCH
ACLSTK
pop ACCL.
OR
pop stack register.
LST
SSTSTK
enable interrupt.
EINT
RET
return from interrupt routine.
*********************************************************
*
*
*
*
*
*
*
*
*
============================
Initialization after reset.
===========================
*
*
*
*
*
*
*
*
*
Data RAM locations 82H(130) through 8FH(143),
12 words of page 1, are reserved for this
program. The user must set the status register
by adding the SST command at the end of the
the initialization routine.
*********************************************************
OOOD
OOOD
OOOD
OOOE
OOOE
OOOF
0010
0011
0012
0013
0014
0014
0015
0016
0017
0017
0018
0019
OOIA
OOIA
OOIB
OOIC
OOID
OOID
OOIE
OOIF
OOIF
*
*
*
AORG
$
initial program.
LDPK
ONE
set data page pointer one.
7EOI
500F
6AOF
802C
7F8E
500C
LACK
SACL
LT
MPYK
PAC
SAC 1
ONE
TMPO
TMPO
NINT
save normal communication
address to its storage.
8030
7F8E
500D
MPYK
PAC
SACL
8037
7F8E
500E
MPYK
PAC
SACL
803A
7F8E
5007
MPYK
PAC
SACL
XVECT
7F89
5002
ZAC
SACL
RXFLG,O
5003
SACL
SNDFLG,O
6EOI
EPIL
ANINT
SINTI
save secondary communication
addressl to its storage.
ASINTI
SINT2
save secondary communication
address2 to its storage.
ASINT2
IGINT
ignore interrupt once after
master reset.
clear flags.
8-65
0098
0099
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0020
0020
0020
0020
7F82
enable interrupt.
EINT
*
*********************************************************
*
Main program.
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0021
0021
0022
0023
0024
0024
0025
0026
0027
0027
0028
0028
0029
002A
002A
002B
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144 002C
0145 002C
0146 002D
2002
FFOO
0021
This program allows the user two levels of nesting
since one level is used as stack for the interrupt. *
When the RXEFLG flag is false then no data transfer *
has ocurred, if it is true then data transfer has
*
finished. User rountines such as digital filter,
*
secondary-data-communication judgement etc., must be *
placed in this location. Depending on the sampling
*
rate (conversion rate), these user routines must
*
write the xmit data to the shift registers within
*
approximately 500 instruction cycles. If the user
*
requires secondary communication, it will be
*
necessary to delay the OUT instruction until the
*
* secondary data transfer has finished.
*
*********************************************************
MAIN LAC
RXEFLG, 0 wait for interrupt.
BZ
MAIN
2003
FEOO
0028
LAC
BNZ
SNDFLG, 0
MAIN1
skip OUT instruction during
secondary communication.
4905
OUT
DXMT,PA1
write xmit data to shift register.
7F89
5002
*
*
MAIN1 ZAC
SACL
F900
0021
B
clear flags.
RXEFLG
MAIN
loop.
*
*********************************************************
*
*
Normal interrupt rountine.
-=--------=------=-------destroy ACC, DP.
*
*
*
*
*
Write the contents of DXMT to the 'LS299s, receive
DAC data in DRCV, and set RXEFLG flag.
*
*
*
*
*
*
*
*****************************~******************.***** ***
4004
NINT
IN
DRCV,PAO receive data from shift register.
.....
014 7
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165
0166
0167
0168
0169
0170
0171
0172
0173
0174
0175
0176
0177
0178
0179
0180
0181
0182
0183
0184
0185
0186
0187
0188
0189
0190
0191
0192
0193
0194
0195
002D
002E
002F
002F
7EFF
5002
LACK
SACL
7F8D
RET
SET
RXEFLG
set receive and xmit ended flag.
return.
*
*********************************************************
*
Secondary communication interrupt routine 1.
*
*
destroy ACC,DP
*
*
*
*
*
*
*
*
*
*
*
Write the contents of D2ND to the 'LS299s, receive
data in DRCV, and modify XVECT for secondary
*
communication interrupt.
*
*********************************************************
0030
0030
0031
0031
0032
0033
0034
0034
0035
0036
0036
0037
4004
SINT1 IN
4906
LAC
SACL
D2ND,PA1 write secondary data to shift
register.
ASINT2,O modify interrupt location.
XVECT
secondary communication 2
7EFF
5003
LACK
SACL
SET
SNDFLG,O
7F8D
RET
200E
5007
OUT
DRCV,PAO receive data from shift register.
*
set secondary communication flag.
return.
**********************************~******************* ***
*
Secondary communication interrupt routine 2.
*
*
*
*
*
*
destroy ACC,DP
Modify XVECT for normal communication, and set
RXEFLG flag.
*
*
*
*
*
*
*
*********************************************************
0037
0037
0038
0039
0039
003A
003B
003B
003C
003D
003D
003E·
200C
5007
SINT2 LAC
SACL
ANINT
XVECT
modify interrupt location
normal communication.
7EFF
SACL
RXEFLG
LACK
SET
set receive and xmit ended flag.
7F89
5003
ZAC
SACL
SNDFLG,O
7F8D
RET
clear secondary communication flag.
return.
8-67
0196
0197
0198
0199
0200
0201
0202
0203
0204
0205
0206 003E
0207 003E
0208 003F
0209 0040
0210 0040
0211 0041
0212
NO ERRORS,
8-88
******************************************~*********** ***
*
------------------------=-------~--=-~---.Ignoring the first interrupt after reset.
*
*
*
*
*
*
destroy ACC,DP.
Ignore the first interrupt after reset. the TLC32040
receives zero as DAC data but no ADC data in DRCV.
*
*
*
*
*
*
*
*
*
*********************************************************
200C
5007
IGINT LAC
SACL
7F8D
RET
END
NO WARNINGS
ANINT
XVECT
modify interrupt location
normal communication.
return.
-
B
B.1
TLC32040 and TMS32020 Flowcharts and
Communication Program
Flowcharts
2
6
3
4
5
a. INITIALIZATION
C.
RECEIVE SUBROUTINE
b. RECEIVED INTERRUPT SERVICE ROUTINE
d. IGNORE INTERRUPT
1 - Alterable AR pOinter and OVM.
2 - Alterable CNF. SXM and XF.
3 - Must clear at least 108 through 127. 19 of internal RAM.
4 - if IMR is changed by user program. INST must be changed.
5 - Their contents will be changed by their routine locations.
6 -IGNRR is executed only once after raseL
8-69
-
7
f. PRIMARY TRANSMISSION ROUTINE
e. TRANSMIT INTERRUPT SERVICE ROUTINE
8
g. PRIMARY·SECONDARY COMMUNICATIONS 1
7 - IGNRX Is executed only once after reset.
S - Modify to 52 address.
9 - Modify to NRM address.
8-70
Modify IMR Interrupt Masklng.Reglster
h. PRIMARY-SECONDARY COMMUNICATIONS 2
9
No
10
11
I. IGNORE TRANSMIT INTERRUPT
10- Modify to NRM address.
11 - Modify to S1 address.
J. SECONDARY COMMUNICATION JUDGEMENT
No
No
k. IGNORE FIRST INTERRUPTS
8-71
· B.2
Communication Program List
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
8-72
************************************************************
*
*
==-=-=--==-======~=~================-==--==
TLC32040 & TMS32020 communication program.
*
===========================================
*
*
*
by H.Okubo & W.Rowand
version 1.1
7/22/88.
*
*
*
*
*
*
*
*
*
*
*
This is a TMS32020 - TLC32040 communication program
that can be used in many systems. To use this program
the TMS32020 and the TLC32040 (AIC) must be connected
as shown in the publication: Linear and Interface
Circuit Applications, Volume 3. The program reserves
TMS32020 internal data memory 108 through 127 (B2) as
flags and storage. When secondary communication is
needed, every maskable interrupt except XINT is
disabled until that communication finishes.
If you have any questions, please let us know.
************************************************************
*
**
*
0000
0001
0004
*
DRR
DXR
IMR
*
*
*
*
*
006C
006D
006F
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
007A
007B
007C
007D
007E
007F
-==-==-===-============
Memory mapped register.
*
EQUO
EQU
EQU
*
*
*
data receive register address.
data xmit register address.
interrupt mask register address.
=================-============================
Reserved on chip RAM as flags and storages.
(block B2 108 through 127.)
-============~======-=====--=---==-==-===-==-=
FXE EQU
FRE EQU
TMPO EQU
ACCHST EQU
CCLST EQU
SSTST EQU
INTST EQU
RVECT EQU
XVECT EQU
VRCV EQU
VNRM EQU
VS1 EQU
VS2 EQU
DRCV EQU
DXMT EQU
D2ND EQU
FRCV EQU
FXMT EQU
F2ND EQU
*
1
4
108
109
111
12
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
ignore first XINT flag.
ignore first RINT flag.
temporary register.
stack for ACCH.
stack for ACCL.
stack for STO register.
stack for IMR register.
vector for RINT.
vector for XINT.
RINT vector storage.
XINT vector storage.
secondary vector storagel.
secondary vector storage2.
receive data storage.
xmit data storage.
secondary data storage.
* receive flag.
* xmit flag.
* secondary communication flag.
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0055
0056
0057
0058 0000
0059 0000
0001
0060
0061
0062
0063
0064
0065 001A
0066 001A
OOIB
0067
0068
0069
0070
0071
0072 ODIC
0073 001C
0010
0074
0075
0076 0020
0077
0078
0079
0080
0081
0082
0083 0020
0021
0084 0022
0085 0023
0024
0086
*******************************************************
*
*
FF80
0020
Processor starts at this address after reset.
AORG
B
0
STRT
*
*
program start address.
jump to initialization routine.
*
**
*
*******************************************************
*
*
*******************************************************
*
Receive interrupt location.
AORG
B
FF80
004A
26
RINT
*
*
*
Rint vector.
jump to receive interrupt
routine.
*
*
*
*
*
*******************************************************
*
*******************************************************
* Transmit interrupt location.
*
FF80
005A
AORG
B
28
XINT
*
*
* Xint vector.
*
* jump to xmit interrupt routine. *
*******************************************************
*
AORG
32
* start initial program.
*
*******************************************************
*
User must initialize DSP with the routine INIT.
* The user may modify this routine to suit his
* requirements as he likes.
*
*
*
*******************************************************
FE80 STRT
CALL INIT
0025
CEOO
EINT
* enable interrupt.
FE80
CALL IGR
0080
8-73
0087
**********************************~******************* **********
0088
*
*
0089
User area
*
*
0090
*
*
0091
*
*
0092
* This pr'ogram allows the user two levels of nesting,
*
0093
* since two levels are used as stack for the interrupt.
*
0094
* When the FXMT flag is false no data has occurred
*
* When the' FRCV flag is false, no data has been
0095
*
* received. As those flags are not reset by any
0096
*
0097
* routine in this program, the user must reset the
*
0098
* flags if he chooses to use them and note that >OOff
*
0099
* means 'true, >0000 means false. User routines such as
*
0100
* digital filtering, FFTs etc. must be placed in this
*
0101
* location. Depending on the sampling rate (conver*
0102
* sion rate), these user routines must write,the xmit
*
0103
* data to the DXMT registers within approximately 500
*
0104
* instruction cycles. If the user,requires secondary
*
0105
* communication, data with the secondary code (XXX
*
* xxxx xxxx xx11) should first be written to DXMT and
0106
*
0107
* then secondary data should be written to D2ND. Next,
*
0108
* a call should be made to C2ND to set up SVECT and the
*
0109
* F2ND flag to perform the secondary communication.
*
0110
* Note that all maskab1e interrupts except XINT are
*
0111
* disabled until secondary communication has completed.
*
0112
****************************************************************
0113
*
0114
****************************************************************
0115
*
*
0116
Initialization routine.
*
*
0117
*
*
0118
* This routine initializes the status registers, flags,
*
0119
* vector storage contents and internal data locations
*
0120
* 96 through 107. Note that the user can modify these
*
0121
* registers (i.e., STO ST1 IMR), as long as the contents
*
0122
*do not conflict with the operation of the AlC.
*
0123
***********************************************************
0124 0025 C800 INIT LDPK 0
* set statusO register.
0125 0026 DOOI LALK >OEOO,O
* 0000 1110 0000 DOOOB
0027 OEOO
0126 0028 606F SACL TMPO, 0
* ARP=O AR pointer 0
0127 0029 506F LST
TMPO
* OV =0 (Overflow reg-clear)
0128
* OVM=l (Overflow mode set to 1)
*
0129
* ? -1 Not affected.
*
0130
* INTM=l Not affected
*
0131
* DP 000000000 page 0
*
0132
*
0133
* set status1 register.
*
0134
*
0135 002A DOOI LALK >03FO
* 0000 0011 1111 OOOOB
002B 03FO
0136 002C 606F SACL TMPO, 0
* APB=O
0137 002D 516F LSTI TMPO
* CNF=O (Set BO data memory)
0138 002E
8-74
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0,152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165
002E
002F
0030
0031
0032
0033
CAOO
6001
6000
C060
CBIF
60AO
0034 CA30
0035 6004
0036 6073
*
*
*
*
*
*
*
*
*
*
*
*
ZAC
SACL DXR,O
SACL DRR,O
LARK ARO,96
RPTK 31
SACL +,0
0166
,0167
0168 003A
003B
0169 003C
0170
0171 003D
003E
0172 003F
0173
0174 0040
0041
0175 0042
0176
0177 0043
0044
0178 0045
0179
0180 0046
0047
0181 0048
0182 0049
0183 004A
*
DOOl
006C
6078
D001
0071
6079
D001
0055
6076
D001
0094
6074
D001
0099
6075
CE26
*
*
*
*
TC =0
SXM=l (enable sign extend mode.)
D9-D5=111111 not affected.
F=l (XF pin status.)
FO=O (16-bit data transfer mode. )
TXM=O (FSX input)
*
*
*
*
*
*
clear registers
clear Block B2.
Interrupt masking
LACK
SACL
SACL
>30
IMR,O
INTST,O
*
*
*
*
*
*
*
0000 0000 0011 OOOOB
INT
II IIII
RINT
I IIII
TINT
IIII
INT2
III
INT1
II
INTO
I
LALK
NRM,O
*
normal xint routine address.
SACL
VNRM,O
LALK
Sl,O
*
*
secondary xint routine address 1.
SACL
VS1,0
LALK
S2,0
*
*
secondary xint routine address 2.
SACL
VS2,0
LALK
RCV,O
*
*
rint routine address.
SACL
VRCV,O
LALK
IGNRR,O
*
set ignore first rint address.
SACL
RVECT,O
LALK
IGNRX,O
*
set ignore first xint address.
SACL
RET
XVECT,O
*
return.
*
*
0037 D001
0038 0067
0039 6077
*
*
*
*
*
*
8-75
0184
0185
0186
0187
0188
0189
0190
0191
0192
0193
0194
0195
0196
0197
0198
0199
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0213
0214
0215
0216
0217
0218
0219
0220
0221
0222
0223
0224
0225
0226
0227
0228
0229
0230
0231
0232
0233
0234
0235
0236
0237
0238
8-76
*
***********************************************************
*
Receive interrupt ro.utine.
*
=--------=-==-=-============
*
*
*
*
* This ro.utine sto.res receive data in its sto.rage DRCV *
* (112 pageO) and sets the receive flag FRCV (125 pageO)*
* As two. levels o.f nesting are used, this routine
*
* al1o.ws the user two. levels, witho.ut stack extensio.n . *
***********************************************************
RINT SST
* push STO register.
SSTST
LDPK 0
* data Po.inter page O.
SACL ACCLST, 0
* push ACCL.
* push ACCH.
SACH ACCHST,O
RVECT,O
* lo.ad ACC vecto.r address.
LAC
CALA
ZALS ACCLST
* Po.P ACC
ADDH ACCHST
LST
SSTST
* Po.P ST register.
EINT
* enable interrupts.
RET
* return.
004A
004B
004C
004D
004E
004F
0050
0051
0052
0053
0054
7872
C800
6071
6870
2074
CE24
4171
4870
5072
CEOO
CE26
0055
0056
0057
0058
0059
2000 RCV
607A
CAFF
607D
CE26
*
LAC
SACL
LACK
SACL
RET
DRR,O
DRCV,O
>FF
FRCV
* lo.ad data fro.m DRR.
* save it to. its sto.rage.
* set receive flag.
**
return.
*
***********************************************************
*
*
*
005A
005B
005C
005D
005E
005F
0060
0061
0062
.0063
0064
0065
0066
7872
C800
6071
6870
207C
6001
2075
CE24
4171
4870
5072
CEOO
CE26
xmit interrupt ro.utine.
*
*
*
* This ro.utine writes xmit data C%the co.ntents o.f DXMT *
* (123 pageO» to. the DXR register acco.rding to. the type*
* o.f co.mmunicatio.n, i.e. no.rmal co.mmunicatio.n o.r seco.ndary*
* co.mmunicatio.n. Fo.r no.rmal co.mmunicatio.n, call the no.rmal *
* co.mmunicatio.n ro.utine (NRM). Fo.r seco.ndary, call the *
* seco.ndary co.mmunicatio.n ro.utines (Sl and S2). Because *
* these ro.utines use two. levels o.f nesting, the user is *
*
* allo.wed two. levels o.f nesting if stack extensio.n is
* no.t used.
*
***********************************************************
XINT SST
SSTST
* push ST register.
LDPK 0
* data Po.inter page O.
SACL ACCLST, 0
* push ACCL.
SACH ACCHST,O
* push ACCH.
LAC
D2ND,O
* prelo.ad dxr with seco.ndary
SACL DXR,O
* co.mmunicatio.n data.
LAC
XVECT, 0
* lo.ad vecto.r address .•
CALA
* call xmit ro.utine.
ZALS ACCLST
* POP ACC
ADDH ACCHST
LST
SSTST
* Po.P ST register.
EINT
* enable interrupt.
RET
* return.
0239
0240
0241
0242
0243
0244
0245
0246
0247
0248
0249
0250
0251
0252
0253
0254
0255
0256
0257
0258
0259
0260
0261
0262
0263
0264
0265
0266
0267
0268
0269
0270
0271
0272
0273
0274
0275
0276
0277
0278
0279
0280
0281
0282
0283
0284
0285
0286
0287
0288
***********************************************************
*
*
*
0067
0068
0069
006A
006B
207B
6001
CAFF
607E
CE26
Normal data write routine.
*
Secondary data write routine 1.
*
207
6001
2079
6075
CE26
*
*
*
CAOO
6001
607F
CAFF
607E
2077
6075
2073
6004
CE26
*
*
*
* This routine is called when secondary communication
*
* occurs. It writes secondary data to DXR, and modifies *
* the content of XVECT(117 pageO) for continuing secondary*
* communication.
*
***********************************************************
Sl
LAC D2ND,0
* write DXR 2nd data.
SACL DXR, 0
LAC VS2,0
* modify for next XINT.
SACL XVECT, 0
RET
* return.
*
***********************************************************
*
0071
0072
0073
0074
0075
0076
0077
0078
0079
007A
*
* This routine is called when normal communication occurs.*
* This routine writes xmit data to DXR, and sets the
*
* transmit flag (126 pageO).
*
***********************************************************
*
NRM
LAC DXMT,O
* write DXR data.
SACL DXR, 0
LACK >FF
* set flag.
SACL FXMT
RET
* return.
***********************************************************
*
006C
006D
006E
006F
0070
*
Secondary data writing routine 2.
*
*
*
* This routine is called when secondary communication
*
* occurs. It writes dummy data to DXR to ensure that
*
* secondary communication is not inadvertently
*
* initiated on the next XINT. It also modifies the
*
* content of XVECT for normal communication.
*
***********************************************************
S2
ZAC
* clear data for protection;
SACL DXR, 0
* of double secondary communication.
SACL F2ND
* clear secondary flag.
LACK >FF
* set xmit end flag.
SACL FXMT,O
LAC VNRM,O
* set normal communication vector.
SACL XVECT, 0
LAC INTST,O
* enable all interrupts.
SACL IMR,O
RET
* return.
8-77
0289
0290
0291
0292
0293
0294
0295
0296
0297
0298
0299
0300
0301
0302
0303
0304
0305
0306
0307
0308
0309
0310
0311
0312
0313
0314
0315
0316
0317
0318
0319
0320
0321
0322
0323
0324
0325
0326
0327
0328
0329
0330
0331
0332
0333
0334
0335
0336
8-78
*
***********************************************************
*
*
*
Check secondary code.
==_= __ =_=c=_=_====_===
*
007B
007C
007D
007E
007F
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
OOBA
008B
OOBC
C800
CA03
606F
207B
4E6F
106F
F680
0084
CE26
destroy DP pointer. *
Ace.
*
*
* This routine checks whether the data in DXMT (123 pageo)*
* has secondary code or not. If secondary code exists, *
* then disable maskable interrupts except XINT, modify the*
* contents of XVECT(117 pageO) for secondary communi*
* cation, and set secondary flag. Note that we recommend*
* calling this routine to send control words to the AIC.*
***********************************************************
C2ND
LDPK 0
* data page pointer o.
LACK 03
SACL TMPO
LAC DXMT,O
* is this data secondary code
AND TMPO
SUB TMPO,O
BZ
C2ND1
* if yes, then next.
RET
* else return.
*
CAFF C2NDI
LACK >FF
* set secondary flag.
607F
SACL F2ND, 0
CA20
LACK >20
* enable only XINT.
6004
SACL IMR, 0
2078
LAC VSI,O
* modify vector address for secondary
6075
SACL XVECT, 0
* communication.
207B
LAC DXMT,O
* write primary data to DXR.
6001
SACL DXR,O
CE26
RET
* return.
*
***********************************************************
*
*
*
*
*
Check first interrupt
*
*
*
*
*
* This routine checks if both first interrupts have
*
*
* occurred. If this routine is called after reset, it
* waits for both interrupts then returns.
*
***********************************************************
008D 206D IGR
LAC FRE,O
* check first interrupt after
008E F680
BZ
IGR
* master reset.
008F 008D
0090 206C
LAC FXE,O
0091 F680
BZ
IGR
0092 008D
0093 CE26
RET
0094
0337
0338
0339
0340
0341
0342
0343
0344
0345
0346
0347
0348
0349 0094
0350 0095
0351 0096
0352 0097
0353 0098
0354
0355 0099
0356 009A
0357 009B
0358 009C
0359 0090
0360
0361
NO ERRORS,
*
***********************************************************
*
*
*
Ignore interrupt routine.
*
*
*
* These routines are used so that the first RINT and
*
*
* XINT after the %OSP reset can be ignored. They set
*
* flags and modify each vector address to the normal
* interrupt address but do not read or write to the
*
* serial ports. Note that the first data that the AIC wi11*
* receive after the OSP reset is >0000.
*
***********************************************************
CAFF IGNRR
LACK >FF
6060
SACL FRE, 0
2076
LAC VRCV, 0
* set normal receive address.
6074
SACL RVECT, 0
*
CE26
RET
* return.
*
LACK >FF
CAFF IGNRX
606C
SACL FXE, 0
2077
LAC VNRM,O
* set normal xmit address.
6075
SACL XVECT, 0
*
CE26
RET
* return.
*
ENO
NO WARNINGS
8-79
C
C.1
TLC32040 and TMS320C17 Flowcharts and
Communication Program
Flowcharts
Walt for First fOD)( Pulse
Enable Interrupt
Write Secondary Communication
Modify Interrupt Location. ·SINT1
Yes
b.INTERRUPT SERVICE ROUTINE
.. MAIN
8-81
Write Transmit Low Byte
Get Receive Low Byte
Get Receive High Byte
Modify Interrupt Locetlon. "NINT1
Modify Interrupt Location. "NINT2
Clear Transfer End Flag
Clear Transfer End Flag
d. PRIMARY COMMUNICATION 2
c. PRIMARY COMMUNICATION 1
Write Transmit Low Byte
Get Receive High Byte
Modify, Interrupt Location. "SINT2
Write SecOndary Date High Byte
Get Receive Low Byte
Modify Interrupt Location. "SINT3
Clear Transfer End Flag
f. PRIMARY-8ECONDARY COMMUNICATION 2
e. PRIMARY-8ECONDARY COMMUNICATION 1
Write Secondary Data Low Byte
Modify Interrupt Location. *NINT1
Modify Interrupt Location. *SINT4
Clear Transmit Low Byte Storage Location
Clear Transfer End Flag
Clear Transfer End Flag
g. PRIMARY·SECONDARY COMMUNICATION 3
h. PRIMARY·SECONDARY COMMUNICATION 4
No
Move Recalve High-Byte to
Transmit Hlgh·Byte
Move Receive Low-Byte to
Transmit Low-Byte
Write Transmit Hlgh·Byte to
Transmit Register Buffer
I. DIGITAL LOOPBACK
8-83
C.2
Communication program List
***********************************************************
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
*
*
*
*
*
*
*
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
8-84
TLC32040 to TMS320C17 Communication program
version 1.2
revised 7/22/88
by Hironori Okubo and woody Rowand
Texas Instruments
(214 ) 997-3460
*
*
*
*
*
*
*
*================================-=~-=-==-==-==--=-==- ---=*
*
*
* This program uses the circuit published in the Volume *
*
* 3 of the Linear and Interface Circuit Applications
*
* book with the following modification:
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
*
*
*=============================================-===========*
*
*
*
*
*
*
*
*
*
*
*
*
*
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
DOOA
OOOB
OOOC
OOOD
OOOE
OOOF
*
1. INT- of the TMS320C17 must be connected to
EODX- of the TLC32040.
*
*
*
*
In this configuration, the program will allow the
*
TLC32040 to communicate with the TLC320C17 with the
*
restriction that all interrupts except INT- are
*
prohibited and only synchronous communication can
*
occur. The program allows the user two levels of
*
nesting in the main program; the remaining two levels *
are reserved for the interrupt vector and subroutines.*
*
*
*
*
*
*
*
*
*
If desired, this program may be used with the TMS32011*
digital signal processor with the following change.
*
Since the TMS32011 has only sixteen words of data RAM *
on data page 1, all of the registers used by this
*
program should be moved to data page 0, except for
*
SSTSTK (the tempo~ary storage location for the status *
register) which must remain on page %1 (since the
*
SST instruction always addresses page 1).
*
*
*
***********************************************************
SSTSTK EQU >00
stack for status (SST) register.
ACHSTK EQU >01
stack for accumulator high (ACCH).
ACLSTK EQU >02
stack for accumulator low (ACCL).
RXEFLG EQU >03
xmit/receive in progress.
DRCV1
EQU >04
storage for high byte receive data.
DRCV2
storage for low byte receive data.
EQU >05
DXMT1
EQU >06
storage for high byte xmit data.
DXMT2
EQU >07
storage for low byte xmit data.
EQU . >08
DXMT3
storage for high byte secndry data.
DXMT4
EQU >09
storage for low byte secndry data.
VECT
EQU >OA
storage for interrupt vector addr.
AN1NT1 EQU >013
storage for normal xmit/rcv vect 1.
AN1NT2 EQU >OC
storage for normal xmit/rcv vect 2.
AS1NT1 EQU >OD
storage for secndry xmit/rcv vect 1.
AS1NT2 EQU >OE
storage for secndry xmit/rcv vect 2.
AS1NT3 EQU >OF
storage for secndry xmit/rcv vect 3.
0055 0000
0010
0056
0057
0011
0058
0012
0059
0013
0060
0014
0061
0015
0062
OOFF
0063
0064
0065
0066 0000
0067 0000 F900
0001 0013
0068
00020069
0070
0071
0072
0073
0074
*
AORG
B
INIT
>0000
branch to initialization routine.
*********************************************************************
*
--------------=-------=-
*
*
Interrupt service routine.
* -----------------------*
* To initiate secondary communication, change the
* contents of VECT to the address of the secondary
* communication subroutine and store the
in DXMT3 and DXMT4.
*
*
*
* e.g.
*
modify VECT.
* LAC ASINTI
VECT
* SACL
0075
0076
0077
0078
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091
0092
0093
0094
0095
0096
0097
0098
*
*
*
*
*
*
I
LAC HI
SACL
LAC H2
SACL
DXMT3
store high-byte of
secondary information in
DXMT4 store low-byte in DXMT4.
DXMT4
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*********************************************************
0002
0002
0003
0004
0005
0006
0007
0008
0009
OOOA
OOOB
0099 OOOC
0100
0101 OOOC
0102 0000
0103
0104
0105
0106
0107
storage for secndry xmit/rcv vect 4.
ASINT4 EQU
>10
CNTREG EQU
>11
storage for control register.
MXINT
EQU
>12
storage for xmit interrupt mask.
storage for xmit interrupt clear
EQU
CLRX
>13
CLRX1
>14
storage for xmit intrpt clear/mask.
EQU
temporary register.
TEMP
EQU
>15
EQU
flag set.
FLAG
>FF
*
=========================
Branch to initialization routine.
*
OOOE
OOOF
0010
0011
0012
6EOI
7COO
5801
5002
4813
4011
2011
7912
FFOO
0007
200A
7F8C
6501
7M2
7BOO
7F82
7F8D
INTSVC
WAITI
*
AORG
LDPK
SST
SACH
SACL
OUT
IN
LAC
AND
BZ
>02
I
SSTSTK
ACHSTK
ACLSTK
CLRXPAO
CNTREG,PAO
CNTREG, 0
MXINT
WAIT1
LAC
CALA
VECT
ZALH
OR
LST
EINT
RET
ACHSTK
ACLSTK
SSTSTK
push status register.
push accumulator high.
push accumulator low.
make sure FSX-flag is clear.
read control register.
load accumulator with control
reg mask-off xmit interrupt
flag loop until xmit interrupt
flag is recognized.
load acc with interrupt vector.
call appropriate xmit/rcv
routines
pop accumulator high.
pop accumulator low.
pop status register.
enable interrupts.
return to main program.
!HIS
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
8-86
0013
0013
0014
0015
0016
0017
0018
0019
001A
001B
001C
0010
001E
001F
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
002A
002B
OOIC
0020
002E
002F
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
003A
003B
003C
0030
003E
003F
7F81
6E01
7F89
6880
7083
50A8
50A8
50A8
50A8
50A8
50A8
50A8
5088
4906
4906
7E04
5012
7EOl
5015
6A15
80A1
7F8E
6713
80A2
7F8E
6714
8090
7F8E
500A
8077
7F8E
500B
8070
7F8E
500C
8084
7F8E
5000
808A
7F8E
500E
8090
7FBE
600F
A095
***********************************************************
===-=-=======================*
*
Initialization after reset.
*
*
=====-=====~==================
*
*
*
*
Oata RAM locations >80 through >92 are reserved
*
*
by this program. The user must set the status
*
*
register at the end of this program with the SST
*
*
command or a combination of SOVM, LOPK etc.
*
*
*
*
***********************************************************
disable" interrupts.
INIT OINT
set data page pointer one.
LOPK
1
"clear registers.
ZAC
LARP
0
0, RXEFLG+>80
LARK
SACL
*+
SACL
*+
SACL
*+
SACL
*+
SACL
*+
SACL
*+
SACL
*+
SACL
*
OUT
OXMT1,PAl
clear transmit registers.
OUT
OXMT1,PAI
LACK
?00000100
SACL
initialize xmit-int mask.prepare
MXINT
LACK
1
for serial port initialization
SACL
TEMP
and initialization of registers
containing 16-bit constants.
TEMP
LT
MPYK
initialize interrupt flag clear.
CLX1
PAC
TBLR
CLRX
,
MPYK
CLX2
initialize interrupt flag clear
PAC
with interrupts disabled.
TBLR
CLRX1
MPYK
IGN
PAC
SACL
VECT
initialize interrupt vector.
MPYK
NINT1
save normal communication
PAC
address to its storage.
SACL
ANINT1
MPYK
NINT2
save normal communication
PAC
address 2 to its storage.
SACL
ANINT2
MPYK
SINTI
save secondary communication
PAC
address 1 to its storage.
SACL
ASINT1
MPYK
SINT2
save secondary communication
PAC
address 2 to its storage.
SACL
ASINT2
MPYK
SINT3
save secondary communication
PAC
address 3 to its storage.
SACL
ASINT3
MPYK
SINT4
save secondary communication
0165
0166
0167
0168
0169
0170
0171
0172
0173
0174
0175
0176
0177
0178
0179
0180
0181
0182
0183
0184
0189
0190
0191
0192
0193
0194
0195
0196
0197
0198
0199
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0213
0214
0215
0216
0217
address 4 to its storage.
ASINT4
***********************************************************
*
*
*
*
*
*
*
*
*
=====-=---==-==========================-=-
Synchronize high/low byte transmission.
The time between FSX- interrupts is approximately
ten microseconds (50 cycles). Wait for first if
FSX-, this is the first interrupt, delay 60 cycles
(past the second interrupt). If it is the second
interrupt, no harm done.
*
*
*
*
*
*
*
*
*
*
***********************************************************
0042
0043
0044
0045
0046
0047
0185 0048
0186 0048
0187 0049
0188
PAC
SACL
0040 CE14
0041 6010
0042
004A
004B
004C
004C
004D
004D
E014
8011 IGNOR
2011
4E12
F680
0043
OUT
IN
LAC
AND
BZ
CLRX1, PAO clear interrupt flags,disableint.
CNTREG,PAO read control register.
CNTREG
wait
MXINT
for
IGNOR
FSX- flag.
C014
5500 IGNORl
LARK
NOP
0,20
FB90
0049
BANZ
IGNORl
E013
OUT CLRX,PAO
CEDO
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
CAOO
6006
CA03
5007
7E24
anyway.
enable interrupt.
EINT
***********************************************************
*
*
004E
004F
0050
0051
0052
wait 60 cycles (20 x 3 cycles) in
case FSX- into is first of the
pair.
if FSXI- int was the second, delay
Main program (user area)
This program allows the user two levels of nesting,
since one level is used as stack for the interrupt and
the interrupt service routine makes one subroutine
call. User routines such as digital filtering, FFTS,
and secondary communication judgement may be placed
here. The number of instruction cycles between
interrupts varies with the sampling rate. In the
power-up condition this is approximately 500 cycles.
In the example below, the first two transmissions send
secondary information to the AIC. The first configures
the TB and RB registers. The second configures the
control register.
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
***********************************************************
MAIN
ZAC
prepare first control word.
SACL DXMTI
LACK >03
SACL
DXMT2
should be xxxx xxll.
LACK
>24
8-87
0218
0219
0220
0221
0222
0223
0224
0225
0226
0227
0228
0229
0230
0231
0232
0233
0234
0235
0236
0237
0238
0239
0240
0241
0242
0243
0244
0245
0246
0247
0248
0249
0250
0251
0252
0253
0254
0255
0256
0257
0258
0259
0260
0261
0262
0263
0264
0076
0265
8-88
0053
0054
0055
0056
0057
0057
0058
5008
7E92
5009
200D
SACL
LACK
SACL
LAC
DXMT3
>92
DXMT4
ASINT1
500A
4906
SACL
OUT
VECT
communications.
DXMTI,PAI
store first transmit byte in
transmit buffer.
0059
005A
005B
005C
005D
005E
005E
005F
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069
006A
7F89
5003
2003
FFOO
005B
*
set VECT for secondary
ZAC
clear xmit/rcv end flag.
SACL RXEFLG
MAIN1 LAC
RXEFLG
BZ
MAINI
wait for data transfer to
complete.
ZAC
SACL
LACK
SACL
LACK
SACL
LACK
SACL
LAC
SACL
OUT
ZAC
SACL
7F89
5006
7E03
5007
7EOO
5008
7E67
5009
200D
500A
4906
7F89
5003
prepare second, control word.
DXMT1
>03
DXMT2
>00
DXMT3
>67
DXMT4
ASINTI
VECT
DXMTI,PAL
RXEFLG
clear xmit/rcv end flag.
*****'****~******************************************* *****
*
*
========================= *
Digital loop-back program
*
*
*
*
*
*
*
*
This program serves as an example of what can
be done in the user area. *
*
*
***********************************************************
006B
006C
006D
006E
006E
, 006F
0070
0071
0072
2003
FFOO
006B
0073
0074
0075
006B
0077
7F89
5003
F900
2004
5006
2005
5007
4906
*
DLB
LAC
RXEFLG
wait for data transfer to complete.
BZ
DLB
LAC
SACL
LAC
SACL
OUT
DRCV1
move receive data to transmit
registers.
DXMT1
DRCV2
DXMT2
DXMTI, PAL
write first transmit byte to
transmit buffer.
ZAC
SACL
B
RXEFLG
DLB
clear rcv/xmit-end flag.
0266
0267
0268
0269
0270
0271
0272
0273
0274
0275
0276
0277
0278
0279
0280
0281
0282
0283
0284
0285
0286
***********************************************************
*
Normal interrupt routines.
*
*
*
*
*
*
*
*
*
*
These routines destroy the contents of the
*
accumulator and the data page pointer, making it *
necessary to save these before the routines begin *
*
*
*
Write the contents of DXMT2 to the transmit buffer*
and read the receive buffer into DRCV1.
*
*
*
***********************************************************
0077
0077
0078
0079
007A
007B
007C
007D
4907
4104
200C
500A
4813
7F8D
4105
DXMT2,PAI
NINT10UT
DRCVI,PAI
IN
LAC
ANINT2
SACL VECT
OUT
CLRX, PAO
RET
DRCV2,PAI
NINT2 IN
007E
007F
0080
0081
0082
0083
200B
500A
4813
7EFF
5003
7F8D
LAC
SACL
OUT
LACK
SACL
RET
0287
0288
0289
0290
0291
0292
0293
0294
0295
0296
0297
0298
0299
0300
0301
0302
0303
0304
0305
0306
ANINTI
VECT
CLRX, PAO
FLAG
RXEFLG
0084 4907 SINT10UT
0085 4104
IN
DXMT2, PAl
DRCVI,PAl
0307
0308
0309
0310
0311
0086
0087
0088
0089
008A
200E
500A
4813
7F8D
4908 SINT2
ASINT2
VECT
CLRX,PAO
0312
0313
0314
0315
0316
0317
0318
008B
008C
008D
008E
008F
0090
0091
4105
IN
200F
LAC
500A
SACL
4813
OUT
7F8D
RET
4909 SINT3 OUT
2010
LAC
write xmit-low to xmit register.
read rcv-data-high from rcv reg.
prepare next interrupt vector.
clear xmit interrupt flag.
read receive-data-low from rcv
reg.
prepare next interrupt vector.
clear xmit interrupt flag.
set xmi%t/rcv end flag.
***********************************************************
*
*
Secondary interrupt routines
*
These routines destroy the contents of the
accumulator and the data page pointer.
*
*
The following routines write the low byte of
*
the primary data word and the high and low byte *
of the secondary data word. They also read the *
A/D information in the receive registers.
*
*
*
*
*
*
*
*
*
*
*
***********************************************************
LAC
SACL
OUT
RET
OUT
DXMT3,PAI
DRCV2, PAl
ASINT3
VECT
CLRX,PAO
DXMT4,PAI
ASINT4
write xmit-data-low to xmit reg.
read receive-data-high from rcv
reg
prepare next interrupt vector.
clear xmit interrupt flag.
write secondary-data-high to
xmit.
read receive-data-low from rcv.
prepare next interrupt vector.
clear xmit interrupt flag.
write secondary-data-low to xmit
prepare next interrupt vector.
8-89
-"-
0319 0092 500A
0320 0093 4813
0321 0094 7F8D
0322 0095 200B
0323 0096 500A
0324 0097 4813
0325 0098 7F89
0326 0099 5007
eliminate
0327 009A 7EFF
communications
0328 009B 5003
0329 009C 7FBD
0330
0331
0332
0333
0334
0335
0336
0337
0338 009D 200B
0339 009E 500A
0340 009F 4813
0341 OOAO ---7F8D
-e-ru--
SACL VECT
OUT
RET
SINT4 LAC
SACL
OUT
ZAC
SACL
CLRX,PAO
clear xmit interrupt flag.
ANINT1
VECT
CLRX,PAO
prepare next interrupt vector.
DXMT2
clear DXMT2 immediately to
LACK
FLAG
unnexpected secondary
SACL
RET
RXEFLG
set xmit/rcv end flag.
clear xmit interrupt flag.
***********************************************************
* ===========================-=======
*
*
*
Ignore first interrupt.
===================================
*
*
*
This routine is used to ignore t~irst data
transmission and also to s~hionize the AIC
with the processor.
*
*
*
*
* * * * * * * * * * * * * * * * * * * * * "*ft* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
IGN
LAC
AN1NT1
SAeL
VECT
OUT
CLRX,O
RET
***********************************************************
0343
*
*
0344
CONTROL REGISTER INFORMATION
*
*
0345
*
*
0346
SERIAL-PORT CONFIG.
INT. MASK INT. FLAG
*
*
0347
110 0 0 1 1 1 0 1
1 0 0 0 1 0 100 1
*
*
0348
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
*
*
0349
1 1 1 I_INT
1
*
*
1 1 1_ _ FSR
0350
I_XF status
*
*
0351
1
FSX
*
*
I
_____
FR
0352
*
*
0353
*
*
0354
(write
l's
to
clear)
*
*
0355
***********************************************************
0356 OOAl 8E1F CLXI DATA
>8EIF
0357 00A2 8EOF CLX2 DATA
>8EOF
0358
ENDNO ERRORS, NO WARNINGS
8-90
0317 009D
0318 009E
0319 009F
0320 OOAO
0321
0322
0323
0324
0325
0326
0327
0328
0329
0330
0331
0332
0333
0334
0335 OOAl
0336 00A2
0337
NO ERRORS,
200B IGN
500A
4813
7F8D
LAC
SACL
OUT
RET
ANINT1
VECT
CLRX,O
***********************************************************
*
*
*
*
*
*
*
*
CONTROL REGISTER INFORMATION
INT. MASK INT. FLAG
SERIAL-PORT CONFIG.
I 100 0 1 1 1 0 I
I 0 0 0 1 0 1 0 0 I
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I
*
*
*
*
I_XF status
*
*
*
*
*
*
I I I I ____ INT
I I I _ _ FSR
I
FSX
I
FR
*
(write l's to clear)
*
*
*
*
*
***********************************************************
8ElF CLXI DATA
8EOF CLX2 DATA
END
NO WARNINGS
>8EIF
>8EOF
8-91
8-92
--
Designing with the TLC320AC01
Analog Interface for DSPs
~1ExAs
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or
to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to
verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software
to the specifications applicable at the time of sale in accordance with Tl's
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the extent TI deems necessary to support this warranty. Specific testing of all
parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may Involve potential
risks of death, personal injury, or severe property or environmental damage
(''Critical Applications',).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN
LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATION.S.
Inclusion ofTl products in such applications is understood to be fully atthe risk
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approval of an appropriate TI officer. Questions concerning potential risk
applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications,
adequate design and operating safeguards should be provided by the
customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design,
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herein. Nor does TI warrant or represent that any license, either express or
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machine, or process in which such semiconductor products 'Or services might
be or are used.
Copyright © 1995, Texas Instruments Incorporated
Contents
Title
Page
1 INTRODUCTION ...................................................................... 8-97
1.1 Overview of Device .............................................................. 8-97
2 ANALOG INPUT . ...................................................................... 8-99
2.1 Signal-to-Noise and Signal-to-Distortion Measurements ................................ " 8-99
2.2 Input Preamp Design ............................................................. 8-99
2.2.1 Noise Considerations ....................................................... 8-99
2.2.2 VMID Referenced Input Circuit Configuration .................................. 8-100
2.2.3 0-V Referenced Input Circuit Configuration .................................... 8-100
2.2.4 Gain Control ............................................................. 8-101
2.3 Layout and Grounding ........................................................... 8-102
2.4 Power Supply .................................................................. 8-102
2.5 Sampling Rate and Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-102
2.5.1 High-Pass Filter . ',' ....................................................... 8-103
,3 ANALOG OUTPUT ................................................................... 8-104
3.1
3.2
3.3
Signal-to-Noise and Signal-to-Distortion Ratio ........................................ 8-104
Voltage Swing andPSRR ......................................................... 8-104
(Sin x)/x Correction ............................................................. 8-105
4 DIGITAL DESIGN CONSIDERATIONS . .................................................
4.1 DSP Serial Interface ......................................................... ,. ...
4.1.1 Maximum Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.1.2 Synchronization of Negative Rail Generator ....................................
4.1.3 Edge Timing .............................................................
4.2 Hardware Design ofTMS320C50 Based DSP System ..................................
4.3 Battery Operation ...............................................................
4.3.1 Reset Considerations ......................................................
4.3.2 Interfacing to a 3-V DSP Processor ...........................................
4.3.3 Calculation of Interface Component Values ......................................
4.4 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.4.1 Initialization ..............................................................
4.5 Register Descriptions .............................................................
4.5.1 Pseudo Register 0 (no-op) ...................................................
4.5.2 Register 1 (A Register) ......................................................
4.5.3 Register 2 (B Register) ' ......................................... , ...... '......
4,5.4 Register 3 (A4 Register) .....................................................
4.5.5 Register 4 (Amplifier Gain Select Register) ......................................
4.5.6 Register 5 (Analog Configuration Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.5.7 Register 6 (Digital Configuration Register) ......................................
4.5.8 Register 7 (Frame-Sync Delay Register) ........................................
4.5.9 Register 8 (Frame-Sync Number Register) ......................................
4.6 TLC320AC01/TMS320C50 Demonstration Program ....................................
4.7 TMS32OC50 Assembler Listing .....................................................
4.8 Linker Command File: ACOlDEMO.CMD Listing ......................................
4.9 Measuring the DAC Filter Response with a White Noise Generator .........................
4.10 Example Noise Generator Code Listing ..............................................
8-106
8-106
8-106
8-106
8-106
8-107
8-107
8-107
8-107
8-109
8-11 0
8-110
8-11 0
8-110
8-110
8-110
8-110
8-111
8-111
8-111
8-111
8-111
8-111
8-112
8-115
8-115
8-116
5 SAMPLING AND QUANTIZATION - TUTORIAL . ........................................ 8-117
5.1 Sampling .................................................................. 8-117
8-95
.....
Contents (Continued)
Title
5.1.1 IdealSampling ............................................................
5.1.2 Real Sampling .............................................................
5.1.3 Aliasing Effects and Considerations ............................................
5.2 Theoretical SNR for a 14-BitDevice .................................................
5.3 References ............................................•.........................
Page
8-117
8-118
8-118
8-119
8-120
List of D1ustrations
Figure
Title
Page
1.
2.
3.
TI..C320ACOI Analog Interface for DSP ................................................ 8-98
ADC Noise and Distortion Measurement ........................ . . . . . . . . . . . . . . . . . . . . . . .. 8-99
VMID Referenced Input Circuit ...................................................... 8-100
4.
5.
6.
0- V Referenced Input Circuit ........................................................ 8-101
7.
8.
9.
10.
11.
12.
Differentialto Single Ended Output Circuit .............................................
(Sin x)/x Error ........................................... ; .........................
TI..C320ACOI to TMS320C50 Hardware Schematic ......................................
Interfacingto3-VDSP .............................................................
Interfacing to 3-V DSP - Component Values ............................................
DAC Channel Frequency Response ...................................................
13.
14.
Ideal Sampling .................................................................... 8-117
Real Sampling .................................................................... 8-118
8-96
Input Circuit for 6 SIW Selectable Gain Settings ......................................... 8-102
DAC Noise and Distortion Measurements .............................................. 8-104
8-105
8-105
8-108
8-109
8-11 0
8-116
1 INTRODUCTION
This application report was prepared by John Walliker and Julian Daley of University College London. It is based on
their experience of using the device as part of a specialized signal processing hearing aid. However the techniques
described, for both the analbg and digital interfaces, are appropriate for a wide variety of applications.
Measurements of performance quoted in this application note are those achieved with the particular samples and test
set-up. For the full device specification see the 1LC320ACOI data manual, reference SLASOS7 A.
Some features of the 1LC320ACOI were not used in this design and therefore have not been covered here. They are
phase adjustment and the use of multiple devices.
1.1 Overview of Device
The lLC320ACOI is a 14-bit resolution, audio frequency (approximately 12-kHz bandwidth) analog interface for DSP
with integral anti-aliasing and reconstruction filters. It has a synchronous, serial, digital interface designed for ease of
connection to many DSP chips.
The internal circuit configuration and the performance parameters, such as input source, sampling rate, filter bandwidths
and gain, are determined by writing in control information to eight data registers. These registers are used to set-up the
device for a given mode of operation and given application. The ADC channel and the DAC channel operate
synchronously and data is transfe1Ted in 2's complement format.
The anti-aliasing filter is a switched-capacitor low-pass filter with a sixth-order elliptic characteristic. The high-pass is
a single-pole filter, which can be switched out if required. There is a 3-pole continuous-time filter that precedes the
switched-capacitor filter to eliminate aliasing caused by sampling in the switched-capacitor filter.
The output-reconstruction fllter is also a switched-capacitor low-pass filter with a sixth-orderelliptic characteristic and
it is followed by a second-order (sin x)lx correction filter. This is followed by a three-pole continuous-time filter to
eliminate images caused by sampling in the switched-capacitor filter.
There are three basic modes of operation available:
• Stand-alone analog-interface mode, where the 1LC320ACOI generates the shift clock and the frame sync for
the data transfers and is the only AlC used.
• Master-slave mode, where the master lLC320ACOI generates the shift clock and the frame sync and the rest
are slaves to these signals.
.
• Linear-codec mode, wilere the shift clock and the frame sync are generated externally and the timing can be
any of the standard codec timing patterns.
The lLC320ACOI is available in a standard 28-pin plastic J-lead chip carrier (FN suffix) and a 64-pin
plastic-quad-flat-pack (PM suffix) which is only l,s mm thick, making it suitable for use in portable systems.
The device has a maximum power dissipation of 110mW in the active mode and 10 mW in the power down mode. It
runs from a single 5-V supply, both for digital and analog circuitry. This is particularly useful for portable equipment,
but does require extra care in the design of the analog input and output stages.
8-Q7
--
AUX IN + ....i----1
AUX IN--++---I
IN+ ....t----1
IN--+---I
I
I
I
I
L _______________________~
I
MON OUT "'+-"""-iC
OUT+
OUT-
•
•
•
•
•
•
14-bit AID converter
14-bit 01A converter
Antialiasing filter
Anti-imaging filter
(sin xlix correction
Input and output amplifiers
.DSP
TLC320AC01
Programmable bandwidth, sampling rate, gain, liP source
Single 5 V supply
70 dB typical signal to nolse+distortion ratio
•
100 mW typical power consumption
•
Analog bandwidth up to 10.8 kHz
Figure 1. TLC320AC01 Analog Interface for DSP
8-98
D
2 ANALOG INPUT
2.1 Signal-to-Noise and Signal-to-Dlstortion Measurements
With the internal gain of the 'ILC320ACOI set to 0 dB, a full scale signal corresponds to 6 V peak-peak at the analog
input (equivalent to 6/(2...fi) - 2.12 V RMS).
The input signal-to-noise ratio of the 'ILC320ACOI can be expressed in terms of the number of least significant bits
(LSB) of noise present in the digital signal, when both its inputs are connected to VMID. The RMS value of the noise
was measured on the test boards at 0.5 LSB. This corresponds to a noise voltage of approximately 180 I1V RMS at the
input (Le., a signal-to-noise ratio of 81 dB). The intermodulation measurements are shown in Figure 2. The stimulus
was the sum of a 1 kHz signal at -6 dB referred to full scale plus a 1.2 kHz signal at -12 dB referred to full scale.
Distortion products are approximately 80 dB down throughout the pass band. The low frequency peaks that can be seen
are multiples of 50 Hz interference.
o
GI
'a
I
-20
'5
Q.
.5
~
rn
-40
'3
-60
'"~
!l!
i
~
-SO
-100
-120
0
1000
500
1500
2000
2500
3000
3500
4000
Frequency - Hz
Figure 2. ADC Noise and Distortion Measurement
In the test circuit, the de accuracy on the samples measured was 14 LSB, equivalent to 5 mV of dc offset.
2.2 Input Preamp Design
2.2.1 Noise Considerations
In order that the input preamp does not significantly affect the noise performance of the system, it should produce a noise
level at least 6 dB below the 'ILC320ACOl, (Le., less than 90 I1V RMS) at the 'ILC320ACOl input.
Consider the case of a microphone producing 20 mV peak-to-peak at the maximum sound level, a preamp is needed with
a gain of 6 V.20 mV - 300 to get a full scale input at the ADC. So the input noise produced by the preamp must be less
than 90 I1V/3oo - 300 nV RMS.
For a preamp with a bandwidth of 10 kHz the input noise voltage should be less than
300 nV = 3 nV/!Hz
/10 kHz
This noise is made up of the operational amplifier's noise voltage combined with the thermal noise of the equivalent
series resistance of the input source. Resistor values need to be carefully chosen, since a 10 k.Q resistor produces thermal
noise of 14 nV/-fHZ at room temperature. (spectral noise voltage density for a resistor is given by ..J4K1R, where K is
Boltzman's constant, T is the absolute temperature and R the resistance). In this case, a 100-0 resistor was chosen
8-99
..
(producing a thermal noise of 1.4 nVlvH'Z at room te~rature). A MAX410 operational amplifier was chosen for the
first gain stage as this has a noise voltage of 2.4 nV/VHz. Noise voltages combine as the root of the sum of the squares,
so the total noise is given by:
\ j(2.4 nV2 + 1.4 nv2) = 2.8 nV/.fHz
The gain is split between two operational amplifiers. The fIrst, low noise, operational amplifier confIgured as a
noninverting amplifier with a gain of 100, followed by a second noninverting stage with a gain of three. This second
operational amplifIer does not need such a low noise voltage specification since its input noise is only being amplifIed
by three. The TLC2272 dual operational amplifIer, which has a noise voltage of 9 nVIVHz, is chosen for its low power
consumption, low input offset and well behaved performance under overload. (These operational amplifiers do not
exhibit the behavior of BiFETs which can produce phase reversal of the output when the inputs go out of negative
common mode range).
47pF
10 k!l
Analog
Input 10 k!l
4 V ~IN
2.5V
1V
Gain Of TLC320AC01 Set To 6 dB
>-<'_----1 IN-
>-+-.____>-1 IN +
TMS320C5x
DSP
VMID ---t====~--.JADCVMID
(2.5 V Normal)
To Rest Of Input Analog
100nF
Signal Conditioning
T
Figure 3. VMID Referenced Input Circuit
2.2.2 VMID Referenced Input Circuit Configuration
The confIguration of the input circuitry requires extra care since all internal signals are referenced to VMID rather than
ground, to allow single supply operation. The PSRR at the internally generated VMID point is low, so it is important that
both the differential inputs are referenced to VMID with any noise on VMID appearing equally on both inputs. There are
two ways of fulfilling this criterion. The first is to reference the whole input circuit to VMID (using this as a virtual
ground) as shown in Figure 3.
This configuration has the advantage of simplicity although there are some drawbacks. The buffered VMID point has
to be capable of driving the virtual ground and since many operational amplifiers are unhappy driving large capacitive
loads this problem must not be overlooked. The TLC2272 is a good choice for this application. The input needs to be
referenced to VMID, which may canse a problem if interfacing to an externally powered, ground referenced signal. In .
this case the input needs to be ac coupled.
2.2.3 O-V Referenced Input Circuit Configuration
The second method is to level shift the signal just before the ADC inputs as shown in Figure 4. In this circuit, the preamp
input is referenced to 0 V. This circuit allows a full range input swing (VMID ± 1.5 Von each input) for an input signal
of ± 1.5 V. Any noise on VMID appears equally on both differential inputs and is therefore cancelled. The common mode
range of the inputs does not exceed the supply rails, so VMID noise must not take the input signal outside the.supply rails.
The eight resistors can conveniently be in one thin film resistor package, giving good matching of resistor values and
hence good power supply rejection ratio (PSRR) and de accuracy. Amplifier Al must have ±5 V or greater power rails
but A2 to A4 only need a single 5-V rail.
8-100
.".
VMID
+ +}
VIN
IN
2VIN
>-""':-:---:-:---1 IN -
'"'v
VIN
± 1.5 V
VMID
-20.1111=
L - - - - - - - -.....__
---~_4~--
__
~~~OV
Figure 4. o-V Referenced Input Circuit
2.2.4 Gain Control
The internal preamp of the TLC320ACOI has software selectable internal gain of 0 dB, 6 dB or 12 dB plus a squelch
mode (-60 dB). With 0 dB gain, plus or minus full scale result is given for a differential input of ±3 V. With a single
ended input configuration (one input tied to VMID), this would not allow plus or minus full scale before the operational
amplifiers run out of headroom, so the gain must be set to 6 dB or 12 dB which would give plus or minus full scale with
±I.5 V and±0.75 V, respectively, at the TLC320ACOl input.
Most of the input noise is associated with the converter itself, rather than the input amplifiers or multiplexers. Therefore,
the signal-to-poise ratio is hardly affected by the chosen input gain. However, it is easier to ensure good rejection of
power supply noise coupled through VMID at low gains.
The TLC320ACOI has two sets of differential inputs, IN and AUX IN which can be individually selected (or both
selected simultaneously for mixing).
If more gain settings are required, a combination of software switching of input source and input gain coupled with an
extra hardware gain stage (see Figure 5) allows six software selectable gain steps as shown in the following table.
EXTERNAL GAIN 3 dB
NORM/AUX
INPUT
INTERNAL GAIN
(dB)
EXTERNAL GAIN 18 dB
TOTAL GAIN
(dB)
NORM/AUX
INPUT
INTERNAL GAIN
(dB)
6
6
12
0
NORM
0
0
AUX
0
3
NORM
6
6
NORM
NORM
NORM
0
TOTAL GAIN
(dB)
0
AUX
6
9
AUX
NORM
12
12
12
15
AUX
6
12
18
24
AUX
12
30
AUX
8-101
-G=OdB
I---;IN+
1-----iIN-
TLC320AC01
1 - - - ; AUX+
t-----IAUXG=+3dBor+18dB
Internal Gain Settings 0 dB, 6 dB, 12 dB
Figure 5. Input Circuit for 6 SJW Selectable Gain Settings
2.3 Layout and Grounding
Although earthing and PCB layout do not seem to be too critical for this device, it is good practice to ensure that the
ground current from sensitive devices such as the ADC does not flow in the same copper as currents from other devices.
This means having a central ground point near the device or using power planes with splits where necessary to isolate
return current from other devices.
The substrate (SUBS) should be connected to ADC ground. Failure to do so can result in noisy and unstable operation.
The circuit should be well decoupled for low and high frequencies to minimize noise injection from the supplies.
2.4 Power Supply
With a master clock frequency of 10 MHz, the TI..C320AC01 samples typically drew lOrnA at 5 V with default register
values. The supply current depends principally on the filter clock frequency. If a negative supply is needed for
operational amplifiers, etc., it may be convenient to generate it using a negative voltage converter. Since the negative
supply generally draws little current this is a feasible solution and avoids the need for a second battery in portable
systems. The ICL7660 needs no external inductors and is available in an 8-pin small outline package. As the internal
oscillator of the ICL7660 free runs at about 10kHz, noise generated from this oscillator can find its way into the ADC
input, often beating with the sampling clock creating a whirring type noise. It is however,possible to lock this oscillator
. to the ADC clock by linking the conversion complete signal to the oscillator input on tlleICL7660. Coupling viaa 100-pF
capacitor allows the converter to free-run if the ADC is not operative (e.g., during start-up). Any noise that now gets
coupled into the ADC will be the same for each sample, creating a dc result that is much easier to deal with. Alternatively
the TLE2682 provides a negative rail generator supplying up to 100 rnA (which can be phase locked) plus a dual
operational amplifier in one 16-pin wide body SO package).
2.5 Sampling Rate and Filters
Within limits, the sampling rate of the device (both ADC and DAC are inherently synchronous) can be set under software
control. If the DAC is not used then the ADC can run at up to 43.2k samples/sec. However, if the DAC is to be used the
sampling rate must be limited to 15k samples/sec.
The anti-aliasing filters (switched capacitor type) track the sampling rate by setting the corner frequency of the filter
to some fraction of the sampling rate. This allows for the possibility of sub-Nyquist sampling, which should be avoided
in most cases. The ratio of sampling rate to anti-aliasing filter comer frequency is set by the B register value (RE~).
The anti-aliasing comer frequency is set by the A register value (REGA) within the TI..C320ACOl.
Conversion rate is given by:
f
8-102
-,
sample - (
f
MCLK
2 x RegA x Reg B
)
.....
The anti-aliasing comer frequency is given by:
f
f MCLK
lp - 80 x Reg A
40
fsample
-yz;;- = RegB
To satisfy Nyquist's sampling theorem:
fsample
---~
2
lip
:.RegB s 20
The default of 18 for the B register gives fsamplelflp - 2.2. This ensures that energy above the Nyquist frequency is well
into the filter's stop band.
The product of the A and B registers must be greater than 65 to allow for 17 serial clock cycles between conversions
(16 data bits plus one extra cycle for frame sync in master or standalone mode). The B register must not be less than 10,
since the ADC conversion takes lOB register counts to complete. The A and B registers have a maximum value of255.
2.5.1 High-Pass Filter
The TLC320AC01 also has a high-pass filter which can be used to attenuate subsonic noise and remove dc offsets. The
importance of subsonic noise filtering should not be underestimated. For example: air conditioning systems are a
notorious source of low frequency noise and a slamming door can produce extremely high levels of subsonic energy.
The filter in the TLC320AC01 has a comer frequency of fg/200 and a slope of 6 dB per octave. The corner frequency
cannot be changed independently of the sampling frequency.
8-103
-3 ANALOG OUTPUT
As previously mentioned, the maximum sample rate for the DAC, at 25 kHz, is lower than for the ADC. This limits the
bandwidth of the output signal to less than 12.5 kHz.
3.1 Signal-to-Noise and Slgnal-to-Dlstortlon Ratio
Figure 6 shows the result of intermodulation distortion measurements for the DAC made on the teSt boards. The noise
floor can be seen at approximately -90 dB in the pass band, falling to approximately -108 dB at frequencies above f,f2.
There are some distortion products in the pass band at approximately -85 dB. The double peaks at approximately 7 kHz
and 9 kHz are images of the signal that have been only partially attenuated by the reconstruction filter. Images are the
digital to analog equivalents of aliases in analog to digital conversion. They occur at frequencies given by:
fimage = N fs ± fin
N = 1,2,3 ...
fs = sampling frequency
0
GI
"a
I
-20
15
a.
.5
j
...'S
{!.
i=
-40
-60
-80
~
1.....
-100
iJJ) \.1....J.AJ..~
j
j,
-
-120
o
1000
2000
3000
I.
I.
'''v
4000
5000
6000
Frequency - Hz
'
•
,lft""
.... -' -U·
IAIlRA
lllnA" .JUlA
7000
8000
9000
MJ\
10000
Figure 6. DAe Noise and Distortion Measurements
If the images are to large for a given application they can be removed by continuous-time low-pass filtering at the output
of the DAC. The size of the images reflects the 45 dB stop-band attenuation of the reconstruction filter.
3.2 Voltage Swing and PSRR
The voltage swing at the differential output is ±6 V for a full scale output. There are software selectable attenuators
giving outputs of 0 dB, -12 dB and a squelch mode of -60 dB. Although there is not a large improvement in SNR ratio
by using a differential output stage, it has the added advantage of increasing the PSRR and allowing level shifting to
a ground referenced output without having to ac couple the signal. Using a thin film resistor pack for the differential
amplifier gives the well matched resistors needed for good common mode rejection and accurate gain. Using a
differential amplifier in this way the PSRR was improved from 49 dB to 53 dB (see Figure 7).
8-104
101<0
TLC320ACOl
5V
101<0
OUT + t-"'V\!'v-....-t
OUT-~4AAr-.-r~
>-+----+4J- OUTPUT
101<0
100 nF
101<0
Figure 7. Differential to Single Ended Output Circuit
3.3 (Sin x)/x Correction
(Sin x)/x error arises because the output from a digital-to-analog converter is held constant between samples rather than
smoothly joining them up. The 1LC320ACOI has a (sin x)/x correction filter. It gives a correct response for a B register
value of 15, which gives a ratio of sample rate to ADC anti-iiliasing filter of 2.67. But as it does not track the B register,
other values for the B register will produce an error in the magnitude of a given output frequency. Figure 8 shows a graph
of calculated error versus frequency for various values of B register with a master clock of 10 MHz and sample rate of
approximately 8 kHz. Other values can be calculated using the equation given in section 2.15.7 of the 1LC320ACOI
data manual.
0.5
0
III
'V
I
I
w
-0.5
-1
-1.50
-2
0
500
1000
1500
2000
2500
3000
3500
4000
Frequency - Hz
Figure 8. (Sin x)/x Error
8-105
4 DIGITAL DESIGN CONSIDERATIONS
4.1 DSP Serial Interface
The TLC320ACOl can be connected directly to the synchronous serial port of a TMS32OC25 as shown in Figures 6-1
and 6-3 of the TLC320AC01 data manual. Interfacing the TMS32OC50 family requires some caution because the
CLKOUT signal will usually exceed the maximum 15 MHz MCLK frequency of the TLC320ACOl. So a divider is
required. Most makes of DSP chip support the synchronous serial interface and should connect directly to the
TLC320AC01.
4.1.1 Maximum Clock Rate
It is highly desirable that the DSP chip and TLC320AC01 are clocked from a common master oscillator. This ensures
that the digital noise which is often coupled into the ADC and DAC of the TLC320AC01 in miniature systems is aliased
to a stable frequency, preferably dc. Texas Instruments has found that the signal-to-noise ratio can be degraded by as
much as 6 dB in a breadboard system when independent clocks are used compared with a fully synchronous system.
A convenient way of phase locking the TLC320AC01 to the processor is to drive the MCLK input of the TLC320AC01
from the CLKOUT of a TMS32OC25 or TMS32OC50orfromtheHl or H3 output of a TMS320C30. However, because
of the higher speed of the TMS32OC50 an external one or two stage divider must be used to lower the CLKOUT
frequency (which can be between20 MHz and 40 MHz depending on which speed grade of processor is used) to 15 MHz
or less. A SN74ACT74 was chosen for its high maximum clock frequency, relatively low power consumption and
availability in surface mount package. The divider power supply current was measured at 6.5 rnA at 5 V and 3.17 rnA
at 3 V when dividing by 2 at 20 MHz; and 20.3 rnA at 5 V and 9.6 rnA at 3 V when dividing by 4 at 40 MHz.
4.1.2 Synchronization of Negative Rail Generator
If switching power supplies are used in the system, for example to generate a negative supply rail, it is advantageous
to phase lock the switcliing frequency to the sampling frequency. The EOC output from the TLC320AC01 is close to
a square wave for reasonable sampling frequencies and can be connected to the OSC pin of a ICL7660 negative supply
generator through a small (100 pF) capacitor to force the normally free running oscillator. The small capacitor allows
the ICL7660 to free run in the absence of anEOC signal. The ICL7660 divides this signal by tWo internally, so that power
supply ripple is at exactly the Nyquist frequency and hence appears as a small dc offset rather than as an unstable whistle.
4.1.3 EdgeTiming
It is important to ensure that the rise and fall times of the serial clock sigt"-Ill between the codec and DSP chip are within
specification, particularly if level shifting circuits are used for mixed 5 V and 3 V operation. Failure to do so can result
in data or frame sync signals being sampled on the wrong clock edge, causing erratic errors. The shift clock output rise
and fall times for the TLC320ACOl in master mode are specified at 19 ns maximum and 13 ns typical in the data manual.
The maximum serial clock input rise and fall times for the TMS32OC25 are 25 ns, and for the TMS32OC30 and
TMS32OC50 are 8 ns. While it might seem from these specifications that the TLC320ACOl cannot satisfactorily drive
the TMS320C30 or TMS320C50 without buffering, these devices do work reliably together as long as very short
connections are used.
In order to discover whether the system was operating with a reasonable safety margin, the rise and fall times of SCLK
were measured. The measurements were made using a LeCroy oscilloscope sampling at 1 GHz and a FET probe with
SCLK from the TLC320AC01 driving the parallel inputs CLKX and CLKR on the TMS32OC50. The PCB track length
was approximately 10 cm and the width 0.25 mm. The results (shown below) were well within the requirements of the
TLC32OC50.
8-106
Rise time (0.8 V to 2 V)
VDD=5V
2.3 ns
VDD=4V
4.1 ns
Fall time (2 V to 0.8 V)
4.4 ns
5.6ns
..
4.2 Hardware Design of TMS320C50 Based DSP System
A relatively simple yet powerful DSP system can be built using a TMS320C50 family digital signal processor and a
1LC320ACOl AlC, as shown in Figure 9. The circuit shown is a simplified version of one that we have used extensively.
It can readily be expanded to include parallel input and output ports. The TMS320C50 has 10K words of on-chip RAM,
allowing complex algorithms to be implemented without the need to use external RAM. Some means of program storage
is needed. A pair of 8-bit wide I-Mbit flash EPROMs (N28FOOIBX-B 120 from Intel) were used which completely fill
the program and data address spaces, allowing the use of very large data tables. They have the advantages of reasonably
low power consumption, especially when idle, the ability to be reprogrammed in-circuit or in a standard programmer
(if socketed) and have a hardware protected boot block. The boot block is an 8K byte segment starting at address zero
which can be protected against erasure by opening a switch. This allows the EPROM programming algorithm to be
safely stored within the EPROM itself, downloaded to on-chip memory and executed from there to reprogram the rest
of the flash EPROM with data transmitted through one of the serial ports. This is very convenient when portable
equipment is to be reprogrammed in the field, especially when surface mounted devices are permanently soldered into
the circuit. The initial bootstrap code can either be loaded using a standard programmer before assembly, or afterwards
using the XDS5 lOin-circuit emulator interface which is brought out to a 14-pin header. These flash EPROMs have an
internal state machine to control the erasure and programming algorithms. This is very important, not only because it
simplifies programming, but it ensures that the essential precharge step before erasure is applied to all locations. This
cannot easily be done with earlier generations of flash memory because those addresses that overlap internal registers
and memory cannot easily be accessed. 100 kn pull-up resistor packs were used on the data bus and serial port signals
to minimize power consumption when the bus is in a high impedance condition, which is the normal condition when
executing from on-chip RAM.
A standard, 40 MHz, third overtone crystal oscillator was used to clock the TMS32OC50. Exactly 8 kHz or 16 kHz
sampling frequencies cannot be obtained with a 40 MHz MCLK. If this is a requirement, an MCLK of 41.475 MHz
should be used. A 2.2 ¢:I surface mount inductor blocks oscillation at the fundamental frequency of the crystal. The
330 kn resistor biases the on-chip oscillator inverter. Some care is needed in the choice of this value to ensure stable
operation and reliable start-up. With the component values shown, the oscillator starts at a supply voltage of
approximately 2 V and is stable up to the absolute maximum of 7 V. Alternatively, CLKMD2 of the TMS320C50 can
be grounded and an extemal20 MHz clock fed into CLKIN2. This provides a divide by 1 option whereby the CPU clock
operates at the same 20-MHz frequency. The 20 MHz, CLKOUTI signal from the TMS320C50 is divided by two using
half a SN74ACT74 D-type flip-flop to provide a 10 MHz MCLK to the TLC320ACOl.
4.3 Battery Operation
4.3.1 Reset Considerations
The 1LC320ACOI undergoes a power-on reset when VDD falls below 4 V with the samples tested. In battery powered
systems it is important to ensure that the supply never dips this low, otherwise all the programmed registers will return
to their default values. To guard against undetected resetting, the system supply should be monitored, using a comparator
as shown in Figure 9 or a supply voltage supervisor such as the 1L7702B. Also, one of the registers that has been changed
from its default should periodically be read back and checked.
4.3.2 Interfacing to a 3-V DSP Processor
There is a strong incentive to operate DSPs at 3 V or 3.3 V to save power. As the 1LC320ACOl resets at a VDD of about
4 V, separate power supplies and level shifting circuits must be used. The signals from a true CMOS DSP such as the
TMS32OC50 swing from 0 to VDD, that is from 0 V to 3 V. As this is greater than the 2.2-V logic high threshold of the
1LC320AC01, all signals from the DSP to the 1LC320ACOI can be directly connected, provided that the 5-V supply
rises and falls faster than the logic supply at switch on and off, respectively. If the power sequence cannot be guaranteed,
the 1LC320ACOl inputs should be protected with a series resistor of about 3.3 kQ compensated with a parallel capacitor
of about 1 nF. There will be a small increase in IDD of the 1LC320ACOI compared with driving from 0 V to 5 V due
to simultaneous conduction by both FETs in the input circuits. Signals from the 1LC320ACOI to the DSP cannot be
directly connected, however. The simplest interface circuit is a series resistor, to limit the current flowing through the
upper protection diode, with parallel compensating capacitor to preserve the rise and fall times, as shown in Figure 10.
8-107
100
!
IcO PULL-lJP to +5 V on 0(151
12 V Only Required
~
For Programming
Rash EPROM
015
014 015
013
5V
OV
I
•
"OOnF
•
,
•
I
,
••
•
SYNC To
-5 V Inverter
.OV
l00pF
.1
SV
ACT74
PWRDWN
RESETI
MiS
SUBS
FCO
FCI
OS
D4
4 Xi'
01
DO
A2
DR
-{
i
:
5V
COM
OV
OX
FSR
FSX
AIS
AIS
A14
A14
A13
A13
A12
All
Al0
/IS
Nl
A7
AS
AS
A4
AS
D7
D6
OS
0
'"
i'ii
>c
II
igr
D4
D3
D2
01
DO
Z
WE
CE
OE
A2
A2
PWO
V(PP)
Al
AO
OS
Pi
IS
READY
t-
A16
07
D6
OS
0
'"
i'ii
~.
i
D4
D3
D2
01
DO
III
'"Z
WE
CE
OEhll
PWO
V(PP)
III
PWO
VPP
,5V
R.W
smB
WE
MSC
HOLD
fK)lD~r.
ACT04
rIcO
~XF
IAQ
lACK
1NT4
INT3
INT2
INTI
NMI
MPIMC
l00nF
A16
liD
TCLKR
TCLKX
lOR
lOX
1FSR/TADO
TFSXITFRM
RS
O·V
A15
A14
A13
A12
AU
Al0
/IS
Nl
A7
AS
AS
A4
AS
Al
Al
AO
AO
TMS32OC50
DOUr
L-
llcO
D6
CLKR
CLKX
OV
- - ApproJdmately 4.1 V
07
SCLK
DIN
Serial PorIa
D9
D6
D2
EOC
MCLK
A12
All
Al0
/IS
Nl
D3
TLC320AC01
Low VoIIaga DeIecInr
g~:
012
011
010
• +5V
1 PERIC
AIS
A14
A13
A12
All
Al0
/IS
Nl
A7
AS
AS
A4
AS
A15
CLKOUT1
CtJ 100 ns for MCLK = 10 MHz
c1rc
xf
serial interface and 'AC01 are now in a stable state
setup codec - only need to reprogram those registers that need to be changed from
their defaults
reg 0 = no op
reg 1
A register (18 = default)
. i f FSAMP = B
progreg 0000000101000101b
36 -> B kHz @10.368 MHz clockin
;endif
35 -> 7.937 kHz @10 MHz
.if FSAMP = 16
progreg 0000000100100010b
.endif
18 -> 16 kHz @10.368 MHz c10ckin
17 -> 16.34 kHz @10 MHz
8-113
--
progreg
progreg
progreg
0000001000010010b
1111 " III " 11111
I I I I I I I 1++++++++----I I 1+++++------------11+-----------------++------------------0000010000011001b
1111111111111111
I I I I I I I I I I I I I I ++----I I I I I I I I I I I 1++------I I I I I I I I I 1++--------I II I I I I I ++----------I I 1+++++------------11+-----------------++------------------000001010000010lb
11111111111111++----1111111111111+------I I I I I I I I I I I 1+-------I I I I I I I 1++++--------I I 1+++++------------11+-----------------++-------------------
; reg 2 - B register (18 - default)
data
address
0 = write
Phase shift
reg 3 - A' register
reg 4 = amplifier gain select
O=sq, 1=0 dB, 2=-6 dB,
output
O=sq, 1-0 dB, 2=+6 dB,
input
O=sq, 1=0 dB, 2=-8 dB,
monitor
no used
address
o = write
Phase shift
; reg 5 = analog configuration
O-loopback, 1=norm ilp, 2-aux ilp,
O=hp filter on, 1=hp filter off
O-echo off, 1=echo on
not used
address
O-write
Phase shift
reg 6
reg 7
reg 8
=
3=-12 dB
3=+12 dB
3--18 dB
3-both
digital configuratjon
frame sync delay
frame sync number
b passthrough
; branch to real-time code in on-chip ram
This section is relocated to on-chip single access ram block for faster operation
.sect 'ocram"
.label ocramstart
this label referes to the address where the following
code is stored in eprom, not the address from which it
is executed
this label refers to the execution address in on-chip ram
passsthrough
Main signal processing loop
clrc
nop
idle
setc
lacc
bz
clrc
splk
intm
Wait for any interrupt, determine whether
it is caused by serial data input and branch
back to idle if not.
intm
WARNING - The manipulation of INTM and the
gotdataflag
nop, idle sequence are necessary to prevent
passthrough , serial interrupts from being missed if they
intm
occur just after another interrupt!
#0, gotdataflag
clear the data received flag
outoutputbuffer, dxr
write the data derived from the previous input sample
to the serial port data transmit register
lacc drr
; read a codec input s'ample from the serial port data receive
; register. Data is in low accumulator
do the signal processing here, leaving result in accumulator
and
#11111111111l1100b
sacl outputbuffer
mask out bottom two bits to ensure that secondary
communications are not accidentally requested
save the result of the prcessing until the next
interrupt, and only then write it to the serial
port. This maximizes the processing time available.
b
passthrough
Interrupt handlers
because the transmit and receive operations of the 'AC01 are synchronous,
only one serial port interrupt handler is needed
8-114
getdata
splk
rete
#1, gotdataflag ; set a flag to indicate data available
; return from interrupt, restoring context and re-enabling interrupts
.label ocramend
; end of block transferred to on-chip ram
.end
4.8 Linker Command File: AC01 DEMO.CMD Listing
MEMORY
/* memory map for CSO */
{
page 0 :/* program memory */
reset
: origin = 0,
length
onchipp :origin = BOOh, length
flashp
param2
BOOh /* booth block up to start of on chip ram +/
2400h /* on chip program memory*/
origin
BOOOh, length = 7200h /* top half flash prog except bO */
origin - 3000h, length = 1000h /* second parameter block in eprom */
/* par. block is overlaid by on-chip ram */
page 1
/* data memory */
origin = 60 h, length = 20h
b3
bObl
:origin = BOOh, length = 240h /* ocram is on-chip data if OVLY=l */
/* external flash eprom if OVLY=O */
SECTIONS
{
vectors
. text
param2
ocram
be
.bss
: load = reset page 0
load
flashp page 0
load
param2 page 0
load - flashp page 0 run = onchipp page 0
load
load
b2 page 1 /* data page 0 on-chip ram */
bObl page 1
4.9 Measuring the DAC Filter Response with a White Noise Generator
A convenient way of measuring the frequency response of a linear system is to excite it with white noise and measure
the response with a spectrum analyzer. This example shows how white noise can be generated by a very short random
bit generator program and used to measure the response of the 1LC320AC01's DAC reconstruction filter.
The random bit generator implements a recurrence relation in a primitive polynomial modulo 2 of order 31
(reference I). This gives a maximal length sequence of pseudo-random bits which only repeats after 231 -1 iterations.
The polynomial used is x31 +' x3 +xO, although there are many others to choose from. A 32-bit variable, noise_sr, which
is initially seeded with any non zero value, stores the state between iterations. On each iteration, the accumulator is
loaded from noise_sr and shifted left one bit. The most significant bit (now in the carry bit) is then exclusive ORed (XOR)
with the remaining non zero terms. Each bit that has been XORed is stored back into the same location in the accumulator
and the result is saved. This is implemented by testing the carry bit after the shift with the execute conditional (XC)
instruction. If C was 0, do nothing because anything XORed with 0 is 0 and bit zero of the accumulator is filled with
a 0 after a shift. IfC was I, XOR the low accumulator with the constant l00lOb which achieves the desired result.
There are three main limitations to this technique. Because the XOR is only carried out on the 16 least significant bits
there must not be any nonzero tenns in the polynomial above x15 apart from x31. The contents of the accumulator should
not be used directly as a random number because successive values are correlated as the bits work their way to the left.
This is overcome in the example by iterating the code 14 times for each sample. Although the noise has a white long-tenn
spectrum (that is equal power per unit frequency), it is nongaussian. This does not matter for frequency response
measurements.
Figure 12 shows the response of the 1LC320AC01 reconstruction filter measured at a sampling rate of 7.937 kHz. 'The
A register value is 42, the B register value is 15 and the MCLK frequency is 10 MHz.
\
,
8-115
..
0
M~SUred JSlng A Jhlte NOIJe GeneJung
-10
Algorithm Runnln In The TMS320CSO
\
-20
l1li
'1:1
-30
\
\
I
iii
.....
Gi
-40
iii
c
-50
r
\
-60
~
Y
-70
--
./
\
1/
y
-80
-90
-
o
1000
2000
3000
MCLK 10 MHz, A register
=
4000
5000
6000
"\
7000
/
V
6000
9000
10000
=42, B register =15 Sampling Frequency =7.937 kHz
Figure 12. DAC Channel Frequency Response
4.10 Example Noise Generator Code listing
.usect "b2" , 2
larp
1rlk
lac
sac1
zac
sac1
*+
*
execute this section once
1arp AR1
lr1k AR1, noise_sr
1acl
*+
add
*, 16
splk
#13, brcr
rptb
end_noise - 1
sfl
nop
xc
1, C
xor n0010b
end_noise
sach
sac1
; allocate 32 bits of data memory
AR1
; seed random bit generator with .2
AR1, noise_sr
#2
*-
*
per dac output sample
load low accumulator from data memory
load high accumulator
repeat block 14 times to decorrelate sequential bits
need a 1 cycle gap between sf1 and xc to
allow for pipeline delay
execute next instruction if carry set
xor bit 3 with bit 31, copy bit 31 to bit 0
save high accumulator to data memory
save low accumulator
Write low accumulator to transmit data register (after masking out bottom 2 bits)
8-116
5 SAMPLING AND QUANTIZATION - TUTORIAL
5.1 Sampling
5.1.1 Ideal Sampling
In converting a continuous time signal into a discrete digital representation, the process of sampling is a fundamental
requirement. In an ideal case, the sampling signal is a train of impulses (infinitesimally narrow with unit area). The
frequency of these impulses is the sampling rate (fs). The input signal can also be idealized by considering it to be truly
band limited, containing no components in its spectrum above a certain frequency.
Input Waveform
Sampling FuncUon
."~,,,:h
~
In Time Domain
(1) (1) (1) (1)
h(t)
4
4
=
Unit
Impulses
x
t1t2t3t4t
J,
~T
Fourier Analysla
J,
J,
F(f)L @"tu
Sampling Spectra
Input Spectra
Convolution In
Frequency Domain
f1
NYQUIST'S THEOREM: fa -f1 > f1
Sampled Output
f
~ fa
fa = 11T
2fa
Sampled Spectra
=
f
> 211
Figure 13. Ideal Sampling
The ideal sampling condition is shown in Figure 13, represented in both the frequency and time domains. The effect of
sampling in the time domain is to produce an amplitude modulated train of impulses representing the value of the input
signal at the instant of sampling. In the frequency domain, the spectrum of the pulse train is a series of discrete
frequencies at multiples of the sampling rate. Sampling convolves the spectrum of the input signal with that of the pulse
train to produce the combined spectrum shown, with double sidebands around each discrete frequency which are
produced by the amplitude modulation. In effect, some of the higher frequencies are folded back so that they produce
interference at lower ones. This interference causes distortion which is called aliasing. Aliases cannot be removed by
subsequent processing.
As shown in the diagram, if the input signal is band limited to a frequency f 1 and is sampled at frequency fs' the overlap
(and hence aliasing) cannot occur if
Therefore, if sampling is performed at a frequency at least twice as great as the maximum frequency of the input signal,
no aliasing occurs and all of the signal information can be extracted. This is Nyquist's Sampling Theorem, and it provides
a basic criterion for the selection of the sampling rate required by the converter to process an input signal of a given
bandwidth.
8-117
®b:
Input Waveform
JI
hIt)
t
14* T
JI
JI
Output Spectra
Sampling Spectre
FroL
(1)
x
I
r,;--p:;I:;;:;:---l
=
x
Input Spectre
r--------,
I Square Wave ~ (sin x)1
I
Fourier Analysis
f1
Sampled Output
Sampling Function
J-\J\
J~
II
FroJK i
-Tl2 +Tl2
I
I
E-~ (~'t) I
- ..;.
T _ _ lth
'- __
_ _ _ JI
.-111; 0 111;
(1)
Envelope has the form
=
's =11T 1/'t 2's
f
Input signals are not truly
band limited
I(s) 211
*
Sampling cannot be done with
impulses, so the amplitude of
the signal Is modulated by
f1
fs
Because 01 input spectra and
sampling there is aliasing and
distortion
(Si: x) envelope
Figure 14. Real Sampling
5.1.2 Real Sampling
The concept of an impulse is a useful one to simplify the analysis of sampling. However, it is a theoretical ideal which
can be approached but never reached in practice. Instead the real sigpal is a series of pulses with a period equalling the
reciprocal of the sampling frequency. The result of sampling with this pulse train is a series of amplitude modulated
pulses.
Examining the spectrum of a square wave pulse train shows a series of discrete frequencies, as with the impulse train,
but the amplitude of these frequencies is modified by an envelope which is defmed by (sin x)/x (sometimes written
sinc(x» where x in this case is ltfs' For a square wave of amplitude A, the envelope of the spectrum is defined as
Envelope = A(;})[Sin(3tfst)]/3tfst
The error resulting from this can be controlled with a filter which compensates for the sinc envelope. This can be
implemented as a digital filter, in a DSP, or using conventional analog techniques. (The n.C320ACOl analog interface
circuit has an on-chip (sin x)/x correction filter after its DAC output for this purpose.)
5.1.3 Aliasing Effects and Considerations
In practice, any real signal has infinite bandwidth. However, the energy of the higher frequency components become
increasingly smaller so that at a certain value they can be considered to be irrelevant. This value is a choice that must
be made by the system designer.
r
.
As shown, the amount of aliasing is affected by the sampling frequency and by the relevant bandwidth of the input signal,
filtered as required. The factor that determines how much aliaSing can be tolerated is ultimately the resolution of the
system. If the system has low resolution, the noise floor is already relatively high and aliasing can have an insignificant
effect. However, with a high resolution system, aliasing can increase the noise floor considerably and therefore needs
to be controlled.
As shown, increasing the sampling rate is one way to prevent aliasing. However, there is a limit on what frequency this
can be, determined by the type of converter used and also by the maximum clock rate of the digital processor receiving
and transmitting the data. 1)ierefore, to reduce the effects of aliasing to within acceptable levels, analog filters must be
used to alter the input signal spectrum.
8-118
5.2 Theoretical SNR for a 14·Blt Device
The analog input to an ADC is a continuous signal with an infinite number of possible states, whereas the digital output
is by its nature a discrete function with a number of different states determined by the resolution of the device. It follows
from this therefore, that in converting from one form to the other, certain parts of the analog signal that were represented
by a different voltage on the input, are represented by the same digital code at the output. Some information has been
lost and distortion has been introduced into the signal. This is quantization noise.
For an ideal staircase transfer function of an ADC, the error between the actual input and its digital form has a uniform
probability density function if the input signal is assumed to be random. It can vary in the range of ±1I2least significant
bit (LSB) or ±q/2 where q is the width of one step.
p(e) = lIq for -q/2 Se S +q/2
p(e) - 0 otherwise
The average noise power (mean square) of the error over a step is given by
+q/2
f
=!
E2(e)
e 2dE
q/2
which gives E2(e) - q2/12
The total mean square error, N2, over the whole conversion area is the sum of each quantization level's mean square
multiplied by its associated probability. Assuming the converter is ideal, the width of each code step is identical and
therefore has an equal probability. Hence for the ideal case
N2
2
=L
12
Considering a sine wave input F(t) of amplitude A so that
F(t) - A sin rot
which has a mean square value of F2(t), where
23t
F2(t) =
in f A2sin2(rot)dt
o
which is the signal power. Therefore the signal-to-noise ratio (SNR) is given by
But q - 1 LSB - 2A12n _ Al2n-l
Substituting for q gives
SNR = 10 LOg[
~
(~2tC :~2n)] = 10 LOg(3 x222n)
6.02n + 1.76 dB
This gives the ideal value for a perfect n-bitconverter and shows that each extra bit of resolution provides approximately
6 dB improvement in the SNR. In practice, errors in the ADC introduce non-linearities that lead to a reduction of this
value.
8-119
For a perfect 14-bit converter, the. SNR is:
6.02 x 14 + 1.76 .. 86 dB
5.3 References
8-120
1.
William H. Press, Brian P. Flannery, Saul A. Teukolsky and William T. Vetterling, 1988, Numerical Recipies
in C - The Art of Scientific Computing, (Cambridge: Cambridge University Press) pp 224-228.
2.
1LC320ACOI Analog Interface Circuit Data Manual; SLAS057A
3.
TMS320C2x User's Guide; SPRUOI4C
4.
TMS320C5x User's Guide; SPRU056B
5.
TMS320 Fixed-Point DSP Assembly Language Tools; SPRU018C
-
Interfacing the TLV1549
10-Bit Serial-Out ADC to
Popular 3.3- V Microcontrollers
~ThxAs
INSTRUMENTS
8-121
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or
to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to
verify, before placing orders, tliat the information being relied on is current.
TI warrants performance of its semiconductor products and related software
to the specifications applicable at the time of sale in accordance with Tl's
standard warranty. Testing and other quality control techniques are utilized to
the extent TI deems necessary to support this warranty. Specific testing of all
parameters of each device Is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential
risks of death, personal injury, or severe property or environmental damage
(''Critical Applications'?
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN
LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications Is understood to be fully atthe risk
of the customer. Use of TI products in such applications requires the written
approval of an appropriate TI officer. Questions concerning potential risk
applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications,
adequate design and operating safeguards should be provided by the
customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design,
software performance; or infringement of patents or services described
herein. Nor does TI warrant or represent that any license, either express or
implied, is granted under any patent right, copyright, mask work right, or other
Intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might
be or are used.
Copyright © 1994, Texas Instruments Incorporated
8-122
Contents
TItle
Page
INTRODUCTION ..........................................•............................ 8-125
Interface TIming ...............................•................... " ...... " ........ 8-125
Use of Software Subroutines ....................................................... ; ... 8-125
Data Format •.........................................•............................. 8-125
TLV1S49-TO-68HCOS INTERFACE . ....................................................... 8-126
Microcontroller Features ..............................................................
Interface Circuit ................•........•...........................................
Software Considerations ..............................................................
Serial Peripheral Control Register (SPCR) ...........................................
Serial Peripheral Status Register (SPSR) .............................................
Serial Peripheral Data I/O Register (SPDR) ...........................................
Program Listing .....................................................................
Program Listing for the 1LVI549-to-MC68HC705 Interface ......................•..... ,
8-126
8-126
8-127
8-127
8-127
8-127
8-127
8-128
TLV1S49-TO-TMS7000 INTERFACE .............................................•........ 8-129
Microcontroller Features .................,.............................................
Interface Circuit ........•.....................•....... " ...... '" .•..•...............
Serial I/O Mode .....................................................................
Provision of1LV1549 Chip Select (CS) ...............................•........•.........
Data Reformatting and Storage ......................•..............•...................
Other Software Considerations .........................................................
Software Listing . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . ..
Program Listing for 1LVI549-to-TMS70C02 Microcontroller Interface ....................
8-129
'8-129
8-129
8-130
8-130
8-130
8-130
8-131
TLV1S49-TO-SOCS1-L INTERFACE ........... ,............................................ 8-133
MicrocontrollerFeatures ..............................................................
Serial I/O Mode 0 ....... , ...................................... " .•...•..............
Interface Circuit ......................................................................
Software Listing .....................................................................
Program Listing for the 1LVI549-to-8OC51-L Interface ................................ ~
8-133
8-133
8-133
8-133
8-134
ANALOG CONSIDERATIONS . ........................................................... 8-135
Analog Reference for the 1LV1549 ...................................................... 8-135
PCB Layout ..............................................•......................... 8-135
Grounding and Decoupling ........•................................................... 8-135
APPENDIX A ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 8-136
8-123
List of IDustrations
Figure
TItle
Page
~)
1.
Tuning for the 11- to 16"clock Transfer Using CS (Serial Transfer Completed After 21
2.
TLV1549 100Bit Serial Out ADC-to-MC68HC705C8 Microcontroller mterface ..•........•.... 8-126
•...... 8-125
3.
Shift Register Operation of the Serial Peripheral mterface (SPI) ..................... '.. .. . . .. 8-127
4.
TLV1549 lO-Bit Serial Out ADC-to-TMS70C02 Microcontroller mterface .................... 8-129
5.
TLV1549 lO-Bit Serial Out ADC-to-80C51-L Microcontroller mterface ...................... 8-133
6.
User Adjustable 2.5-V Reference Circuit ............................................ '"
8-124
8-135
INTRODUCTION
The n.V1549 is a lO-bit serial out analog-to-digital converter that operates from a 3.3-V (±O.3 V) single supply. It uses
a switched-capacitor successive-approximation method to perform the conversion in a maximum of 21 J.IS.
This application report describes how to interface the n.V1549 to three popular microcontrollers which operate from
a single 3.3-V supply rail. These are the 68HC05, the TMS70C02, and the 8OC51-L.
Interface Timing
The timing for each of the interfaces described in this application report is illustrated in Figure 1. One chip-select (CS)
pulse is used for each lO-bit conversion and 16 CLOCK 110 pulses are between each CS.
~l~--------------~lrnr~1--
CLOg~
I~~
:
I
I
~.C:II HI'ZSl8te~
DATA
OUT
I
I
I ~~:~~r;slon I
------;~~i+_--I.~I AID
('; 21
pal
Initialize
Figure 1. Timing for the 11· to 16-Clock Transfer Using CS
(Serial Transfer Completed After 21 1lS)
Use of Software Subroutines
The subroutines included in this application report have been developed as much as possible as relocatable pieces of
software. They include a provision for setting the number of consecutive conversions to be performed. This is either set
in the main program as in the TMS7000 and 80C51-L examples or inside the subroutine as used in the 68HC05 example,
by programming the number of conversions into COUNT. It is recommended that at least two conversions are performed
either after a power-up reset or after a protracted interval between the last conversion. This enables the TI..V1549
on-board sample-and-hold to acquire the most recent signal level during the first conversion cycle before converting
it into digital form during the second cycle.
Data Format
In whatever format the data arrives at the microcontroller, it is important to ensure that any reformatting, if required,
puts the data into a convenient final format. This application report places the most significant byte of the conversion
result in one byte of random access memory (RAM) and the least significant byte in an adjacent byte of RAM. The two
least significant bits of the lO-bit result are placed in the least significant bit locations of their RAM location.
This format gives the user the flexibility to use only 8-bit precision data, if so required, to add the MS and LS pytes
together for use in 16 bit wide architectures, to view the two least significant bits of the resultfor fine tuning applications,
or to reformat into another more convenient format.
8-125
TLV1549-To-68HC05 INTERFACE
Microcontroller Features
The M68HC05 family of microcontrollers consists of several different product variants of the basic architecture. It is
important that the correct product type is specified to ensure that it contains all the features and attributes necessary to
fulfill all its eventual system requirements.
In the case of its suitability for interfacing to the 1LV1549 serial out ADC, the M68HC05 product type should contain
a serial peripheral interface (SPI). Several types contain this feature including the MC68HC705C8, which was chosen
as the target for this ADC interface.
Vcc+ (3.3 V ± 0.3 Y)
VCC
Vcc
PD4ISCK
UOCLOCK
1/2 TLV2262A
REF+
PD2IMISO
DATA OUT
ANALOQIN
Analog Input
(OV-VCcJ2)
XTAL1
PC7
CS
2 MHz (max)
IRQ
TLV1548
10 ItO
=
XTAL2
REF10 ito
SS
Interrupt
(optional)
VCC_(OY)
MC68HC705C8
VSS
OV
NOTE: For 68HC05 operating off 3.3 V de supply:
Maximum I/O clock frequency = maximum crystal clock frequency/4 - 0.5 MHz
Figure 2. TLV15491O-BIt Serial Out ADC·to-MC68HC705C8 Mlcrocontroller Interface
Interface Circuit
Figure 2 shows the circuit interconnections for the 1LV1549 - MC68HC705C8 microcontroller interface. No glue logic
is required. The positive reference to the 1LV1549 is provided directly from the Vcc+ supply. The analog signal is scaled
by an appropriate factor (a gain of two in this case) and buffered by one half of a 1LV2262A dual operational amplifier.
The three digital interface terminals, YO CLOCK, DATA OUT, and CS of the 1LV1549 connect directly to the
PD4ISCK, PD2IMISO, and PC7 terminals respective}y of the microcontroller. When the SPI is enabled, PD4 becomes
SCK, which is the serial clock output, and PD2 becomes the master in slave out (MISO) terminal. When programmed
to be a master device, the microcontroller receives serial data at its MISO terminal.
Figure 3 shows the shift register operation of the SPI when connected to Ii serial output peripheral component such as
the 1LV1549. The MC68HC705C8 operates as the master device and the 1LV1549 acts as the slave.
&-126
1/0 CLOCK
SCK
DATA OUT
MISO
SPI Shift Register
TLV1549
MC68HC705C8
Figure 3. Shift Register Operation of the Serial Peripheral Interface (SPI)
Software Considerations
The three registers which are used for SPI communications are:
Serial peripheral control register (SPCR)
Serial peripheral status register (SPSR)
Serial peripheral data 110 register (SPDR)
Serial Peripheral Control Register (SPCR)
Bits 0 and 1 of the SPCR program the SPI master bit rate. With bits 0 and 1 set to 0, SCK runs at the internal processor
clock/2. This means that SCK operates at one quarter of the microcontroller XTAL frequency.
Bit 2 determines the phase relationship between the clock transmitted at SCK and the data appearing on the MISO
terminal. If a 0 is placed in bit 3, SCK idles low. This is the correct condition for the TLV1549. A 1 in bit 6 of the SPCR
enables the SPI. A 0 in bit 6 disables the SP!. A 1 in bit 4 (MSTR) confers the status of master to the microcontroller.
Serial Peripheral Status Register (SPSR)
The most important bit of the SPSR is bit 7 (SPIF). When set to 1, it indicates that a data transfer between the TLVl549
and the microcontroller has been completed. The SPIF bit is automatically cleared when the SPSR is read and the SPI
data register is accessed.
Serial Peripheral Data 1/0 Register (SPDR)
When the SPIF bit of the SPSR is 1, the SPDR contains the received byte of information from the converter. The contents
of SPDR can then be read into a suitable register or location.
Program Listing
The program listing for the TLVI549-to-MC68HC705 interface shown in Figure 2 is included in the following section.
COUNT has been set to 2; this ensures that two conversions are performed each time the ADC subroutine is used. The
fIrst conversion flushes out potentially erroneous data from the converter output registers. For test purposes, the main
program simply performs continuous repeat jumps to the ADC subroutine.
The SPI expects the most significant bit of each received byte to arrive fIrst which is compatible with the order of the
TLV1549 output bit stream. This means that no reformatting of the most signifIcant bit of the lO-bit conversion result
is required. However, the least significant byte does need to be shifted right by 6 bits.
8-127
Program Listing for the TLV1549-to-MC68HC705Interface
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
*
TLV1549 - MC68HC705C8 Interface Program
*
** This program contains a subroutine ADC which reads
**
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
**
*
*
*
*
*
*
OOOA
OOOB
OOOC
0002
0006
0011
OOOE
OOOF
0010
0050
0051
1FFE
1FFF
0052
0160
0160
0162
0165
0167
016A
016D
016F
0171
0173
0175
0177
0179
017A
017C
017E
0180
0182
0184
0186
0189
018B
018D
018F
0191
0194
0196
0198
019A
019C
019E
01AO
01A1
01A3
01A4
01A6
01A7
8-128
the serial data from two conversions of the TLV1549
and places the MSByte in address 50H and the LSByte
in address 51H.
The data from the first conversion(potentia11y
erroneous) is overwritten by the result from the
second conversion.
*
* * * * * * * * * * * *
SPCR
SPSR
SPOR
PORTC
DDRC
SCDAT
SCCR1
SCCR2
SCSR
MSBYTE
LSBYTE
RESETH
RESETL
COUNT
A601
C71FFE
A660
C71FFF
CD016F
20FB
1E06
A602
B752
A610
1E02
4A
26FB
1F02
A650
B70A
A600
B70C
OFOBFD
B60C
B750
A600
B70C
OFOOFD
B60C
B751
3A52
B652
2607
A606
98
3651
4A
26FA
81
START
ADC
CONVERT
CSHIGH
HBYTE
LBYTE
FORMAT
*
*
*
*
*
*
*
** * * * * * * * * * * * * * * * * *
EQU OAH
* * * * * * * * * * * * * * * * * *
EQU OBH
*
*
EQU OCH
*
EQU 02H
** Names, Peripheral, and
*
EQU 06H
* Control Registers
*
EQU 11H
*
*
EQU OEH
*
*
EQU OFH
*
*
EQU 10H
* * * * * * * * * * * * * * * * * *
EQU 50H
* * * * * * * * * * * * * * * * * *
EQU 51H
* Names working RAM addresses
*
EQU 1FFEH
*
*
EQU 1FFFH
*
*
EQU 52H
* * * * * * * * * * * * * * * * * *
ORG 160H
Start Program at 160H
LOA #OlH
STA RESETH
Load Reset Vector High Byte
LDA #6.0H
STA RESETL
Load Reset Vector Low Byte
JSR ADC
BRA START
BSET 7, DDRC
LOA #02H
STA COUNT
LOA nOH
BSET 7, PORTC
Set Port C bit 7 (TLV1549 CS) high
DECA
BNE CSHIGH
BCLR 7, PORTC
Reset TLV1549 CS (Low)
LOA #50H
Load accumulator with 50H
STA SPCR
Load SPI control register
LDA lIOOH
Load dummy data into accumulator
STA SPDR
Receive SPI data
BRCLR 7, SPSR, HBYTE
LDA SPDR
STA MSBYTE
Put MSBYTE in Location 50
LDA #OOH
Load dummy data into accumulator
STA SPDR
Receive SPI data
BRCLR 7, OB, LBYTE
LOA SPOR
STA LSBYTE
Put LSBYTE in Location 51
DEC COUNT
LOA COUNT
BNE CONVERT
If COUNT - 1, do another conversion
LOA #06H
*
* * * * * * * * * * * * * * * * *
CLC
*
*
ROR LSBYTE
Reformats LSBYTE
*
*
DECA
*
*
BNE FORMAT
* * * * * * * * * * * * * * * * * *
RTS
END
TLV1549-TO-TMS7000 INTERFACE
Microcontroller Features
The entire range of TMS7000 microcontrollers can be operated with a 3-V supply. However, the maximum crystal
frequency they will tolerate at this supply voltage (over the full temperature range) is 3 MHz. The inherently longer
instruction cycle times that this yields should be taken into account when deciding how many software delay loops are
necessary to produce the required delay.
Within the family of TMS7000 microcontrollers, three types are available that have a serial port: TMS70Cx2,
TMS77C82, and TMS7OCx8. This application report refers to the TMS7OCx2, but anyone of these three types could
be chosen to efficiently implement a serial interface to the TLV1549.
Three modes of serial communication are available for the serial port: asynchronous mode, isosynchronous mode, and
the serial I/O mode. The most suitable of these for interfacing the TMS7OCx2 to the TLV1549 is the serial I/O mode.
Interface Circuit
The TLV1549-to-TMS7OC02 interface circuit is shown in Figure 4. The chip select (CS) of the TLV1549 is controlled
by the output from AO (bit 0 of peripheral port A).
Vcc+ (3.3 V ± 0.3 y)
Vec+
Vcc
Vee
A4ISCLK
110 CLOCK
1/2 TLV2262A
Analog Input
(OV-Vcct2)
REF +
DATA OUT
ANALOG IN
A5IRXD
XTAL1
AO
CS
XTAL2
REF10 leO
=
3 MHz (max)
INn
TLV1549
10 leO
ss
Interrupt
(opUonal)
Vcc-(OY)
TMS70C02
VSS
ov
NOTE: Maximum 1/0 clock frequency ~ microcontroller crystal frequency!8
Figure 4. TLV15491()...Blt Serial Out ADC-to-TMS70C02 Mlcrocontroller Interface
Serial 1/0 Mode
Four peripheral registers are used to set up and control the serial I/O mode of the microcontroller:
Serial mode register (SMODE)
Serial control register 0 (SCTLO)
Serial control register 1 (SCTL1)
Serial port status register (SSTAT)
The contents of the SMODE register determine the data format and type of communication mode (serial I/O for
example). In the serial I/O mode, the frame format of each characteris five to eight data bits followed by a stop bit. Setting
the number of bits to eight can simplify the software necessary to implement the interface.
SCTLO enables either transmit or receive communication. SCTLl determines the source of SCLK and programs the
frequency of SCLK.
8-129
SSTAT is a read-only register that is used for checking the status of the serial port. Bit 1 (RXRDY) of SSTAT is 0 when
the receive buffer (RXBUF) is empty and 1 when RXBUF is full.
Provision of TLV1549 Chip Select (~)
On power-up and/or system reset, the lLV1549 chip-select terminal (CS) should be initialized to a high level. To provide
this, one of the bidirectional peripheral port bits can be programmed as an output and set to a 1 for a period of at least
21 ~. This period is provided by a delay loop at the beginning of the ADC subroutine. The number of times the loop
is excuted in order to achieve at least 21 ~ is dependent on the clock frequency of the microcontroller and the number
of instruction cycles contained within the delay loop. The example program listing shown in the section program listing
for lLVI549-to-TMS7OC02 microcontroller interface executes the loop 16 times, but the loop can be executed less
times to optimize the conversion throughput rate.
'
On completion of this delay loop, the particular peripheral port bit is reset to 0, and the converter is now ready to send
out data from the previously performed conversion.
Data Reformatting and Storage
After RXBUF is checked to verify it is full, its contents can be read to a suitable register for subsequent access and
processing. In the case of the lO-bit conversion result from the lLV1549, two successive bytes of data are received and
each are placed in RXBUF to be read consecutively into two convenient memory locations.
The lLV1549 sends the digital result of each conversion with the most significant bit first and the least significant bit
last. This is the reverse of the order that the TMS7OC02 expects. A few software instructions are therefore inserted near
the end of the conversion subroutine that reformat the data into the correct order for interpretation by the microcontroller.
Other Software Considerations
The subroutine that services the lLV1549 conversion should be located in a convenient area of memory that is
compatible with the rest of the system. For example, all serial port versions of the TMS7000 family have 8K bytes of
EPROM. This EPROM is located between addresses EOOOH (hex) and FFFFH. A converter subroutine start address at
the midpoint of this EPROM memory space may be convenient in that it leaves the first half of this space for the location
of the main program. The example program listing in the section Program Listing for lLVI549-to-TMS70C02
Microcontroller Interface uses a start location of FOO6 which is convenient for the emulation system it was developed
'on.
On system reset, the stack pointer is at location OOOlH. In programs that include nested subroutines where the number
of RAM locations taken up by the stack becomes large, the stack can interfere with other useful or even critical RAM
locations. It is therefore prudent to reposition the stack pointer, immediately after reset, at a higher address in RAM such
as 0060H. This allows the stack plenty of room to grow and avoids interference with lower address RAM locations.
Software Listing
The following program listing reads in the results of two lO-bit converSions from the lLV1549. The software routine
ADC actually reads in the results from N conversions, where N is the contents of the register COUNT. The first
conversion in a sequence of conversions may be erroneous because the data received is derived from a previous
(probably invalid) sample of the analog signal. It is often useful to flush out this first spurious reading before receiving
a second valid conversion result. The setting of the contents of COUNT is performed within the main program and
should normally be set to a minimum of two.
8-130
Program Listing for TLV1549-to-TMS70C02 Mlcrocontroller Interface
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
* * * * * * *TLV1549
* * * * * * * * * * * * * * * * * * * * * * * * *
- TMS70C02 Interface Program
*
*
*
*
*
*
*
*
0004
0005
0014
0015
0016
0018
0019
001A
0009
0010
0011
F006
F006
52
F007
60
F008
OD
F009
A2
FOOA
11
FOOB
05
FOOC
A2
FOOD
OC
FOOE
14
FOOF
72
F010
02
FOll
09
F012
8E
F013 F017
F015
EO
F016
EF
F017
22
F018
03
F019
A2
F01A
01
F01B
04
F01C
B2
FOlD
E6
F01E
FA
F01F
11:2
F020
00
04
F021
F022
A2
16
F023
F024
15
F025
A2
CO
F026
18
F027
80
F028
F029
16
F02A
26
F02B
02
02
F02C
F02D
EO
F02E
F9
F02F
80
F030
19
F031
DO
F032
OA
F033
A2
F034
16
F035
15
*
This program contains a subroutine ADC which reads in
the serial data from two conversions of the TLV1549. The
data (potentially erroneous) from the first conversion
is overwritten by the data from the second conversion.
The most significant byte is placed in register 16. The
least significant byte is placed in register 17.
*
*
*
*
*
*
*
* * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * *
*
*
*
*
* Name Peripheral Registers
*
*
*
*
*
*
*
*
*
Name
Count
and
Result
Registers
*
*
*
*
* * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * *
APORT
ADDR
SMODE
SCTLO
SSTAT
SCTL1
RXBUF
TXBUF
COUNT
MSBYTE
LSBYTE
START
EQU P4
EQU P5
EQU P20
EQU P21
EQU P22
EQU P24
EQU P25
EQU P26
EQU R9
EQU R16
EQU R17
AORG >F006
MOV %>60,B
LDSP
MOVP %>ll,ADDR
Set start address of program
Set stack register
Set up Port A Data Direction Register
MOVP %>OC, SMODE Set up Serial Mode Register
MOV %> 02, COUNT
Set COUNT = 2
CALL @ADC
Call Subroutine ADC
JMP START
On return from Subroutine ADC, jump to START
ADC
MOV %>03,A
Put 03 in register A
CSHIGH
MOVP %>Ol,APORT TLV1549 Chip Select goes high
DEC A
JNZ CSHIGH
Decrement the contents of Register A by 1
and jump to CSHIGH if result is not zero
MOVP %>OO,APORT TLV1549 Chip Select goes low
MOVP %>16,SCTLO Set up Serial Control Register 0
MOVP %>CO,SCTLl Set up Serial Control Register 1
LABELl
MOVP SSTAT,A
Put contents of Serial Status Register in A
BTJO %>2,A,LABEL2 If bit 1 of A is 1, jump to LABEL2
LABEL2
JMP LABELl
and if not, jump to LABELl
MOVP RXBUF,A
Put contents of RXBUF (MSByte) in A
MOV A,R10
Put contents of A into Register 10
MOVP %>16,SCTLO Set up Serial Control Register 0
8-131
0043 F036
A2
F037
CO
F038
18
0044 F039
80
F03A 16
0045 F03B
26
F03C
02
F03D
02
0046 F03E
EO
F03F
F9
0047 F040
80
F041
19
0048 F042
00
F043
Os
0049 F044
02
F045
09
0050 F046
E6
F047
CF
0051 F048
BO
0052 F049
DD
F04A
OB
0053 F04B
E7
F04C
03
0054 F04D
74
F04E
02
F04F
OB
0055 F050
42
F051
OB
F052
11
0056 F053
05
F054
OC
0057 F055
05
F056
OE
0058 F057
22
FOS8
08
0059 F059
42
FOSA
OA
F05B
OC
0060 F05C
BO
0061 F05D
OD
F05E
OC
0062 FQ5F
DF
F060
OE
0063 F061
B2
0064 F062
E6
F063
F8
0065 F064
42
F065
OE
F066
10
0066 F067
OA
0067 FFFE
0068 FFFE F006
0069
8-132
MOVP '>CO,SCTL1 Set up Serial Control Register 1
LABEL3
MOVP SSTAT,A
Put contents of Serial Status Register in A
BTJO '>2,A,LABEL4
LABEL4
If bit 1 of A is 1, jump to LABELl
JMP LABEL3
and if not, jump to LABEL3
MOVP RXBUF,A
Put contents of RXBUF (LSByte) in A
MOV A,Rll
Put contents of A in Register 11
OEC COUNT
(COUNT) - 1
JNZ ADC
If COUNT is not zero do another conversion
CLRC
RRC Rll
clear carry bit
* * * * *.* * * *
JNC LSBITO
OR '>2,R11
LSBITO MOV R11,LSBYTE
* * * * * * * * * * *
* Reformats Least Significant Byte *
*
*
*
*
* * * * * * * * * * * * * * * * * * * *
Put reformatted LSByte in LSBYTE
CLR R12
clear register 12
CLR R14
and register 14
MOV '>8,A
Set contents of A to 8
MOV R10,R12
Put contents of register 10 in register 12
DEC A
JNZ FORMAT
* * * * * * * * * * * * '* * * * * * * *
*
*
* Reformats Most Significant Byte
*
*
*
*
*
*
*
* * * * * * * * ****** * • * * * *
MOV R14,MS8YTE
Put reformatted MSByte into MSBYTE
RETS
AORG >FFFE
DATA START
END
Return from subroutine AOC
Configure Reset vector
to point to START
FORMAT CLRC
RRC R12
RLCR14
TLV1549-TQ-SOC51-L INTERFACE
Mlcrocontroller Features
The 80C51-L is the 3.3-V supply version of the 8OC5l family of microcontrollers. Various 3.3-V supply versions of the
8OC51 architecture are available from different manufacturers. Individual data sheets should be consulted to establish
at which maximum crystal frequency each specific device type can operate.
As indicated for the previously described interfaces, the most suitable method of receiving the serial output from the
1LV1549 is to configure the serial port of the microcontroller to perform like an 8-bit shift register. The same is true
for the 80C51-L.
Serial 1/0 Mode 0
The type of serial communication to and from the 80C51-L is determined by the data inserted into the serial port control
register (SCON). The contents of the most significant bits of SCON (bits 7 and 6) determine the operating mode (modes
0, I, 2, and 3) of the serial port.
Mode 0 is the shift register mode and is programmed by placing a 0 in each of bits 7 and 6 of the SCON. Bit 4 (REN)
of the SCON is the receive enable bit. This bit is set to I, while bit I (RI) of the SCON is 0, to receive serial data. In this
configuration, data is received at bit 0 of port 3 (P3.0). The synchronizing signal for clocking in this data is output at
TXD, which is bit I of port 3 (P3.I).
When configured for mode 0, eight bits are received with no trailing stop bit for each enabling of serial reception. The
data is received with the least significant bit expected first, the reverse of the order in which the 1LV1549 serial data
arrives. Reformatting of the received data is therefore necessary.
Interface Circuit
Figure 5 shows the interconnections necessary to implement the interface of the 1LV1549 to the 80C51-L
microcontroller. CS of the 1LV1549 is driven by bit 4 of port 3 (P3.4) of the 8OC51-L.
Vcc+ (3.3 V ± 0.3 V)
Vee
Vcc
1/2 TLV2262A
Analog Input
(OV-VCcJ2)
P3.1ITXD
UOCLOCK
REF +
DATA OUT
ANALOG IN
P3.0/RXD
XTAL1
P3.4
CS
XTAL2
REF10ke
P3.31INT1
TLV1549
10ke
Interrupt
(optional)
VCC-(OY)
BOC51·L
VSS
=
See Data Sheet
for Maximum
Frequency
OV
NOTE: 1/0 clock frequency = microcontroller clock frequency/12
Figure 5. TLV154910-Blt Serial Out ADC-to-80C51-L Mlcrocontroller Interlace
Software Listing
Similar to the previously described program listings, the following listing contains the subroutine ADC that reads into
the 80C51-L ten bits of serial data resulting from a single conversion of the 1LVI549. The number of consecutive
conversions performed for each jump to subroutine ADC is equal to the number placed in COUNT. The result of each
conversion is overwritten by that of the next conversion in the sequence.
8-133
Program Listing for the TLV1549-to-8OC51-L Interface
LOC
OBJ
LINE
1
2
3
4
5
0049
004B
004D
004E
004F
0050
0051
0052
0053
0054
0055
0056
0058
0059
005B
005C
005D
005F
0061
0063
8-134
7B02
020029
80F9
D2B4
7410
14
;*
;*
7
8
9
;*
;*
;*
11
0022
0022
0024
0027
0029
002B
002D
002E
0030
0032
0035
0038
003A
003C
003F
0041
0043
0045
0046
0047
;*
6
10
0020
0021
REG
SOURCE
i* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;*
*
TLV1549 - 80C51-L Interface Program
;*
*
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
70FD
C2B4
759810
3098FD
C298
A899
3098FD
C29C
C298
A999
33
1B
EB
34
70EO
35
36
37
7C08
38
AAOO
C3
39
E8
40
13
41
42
F8
EA
43
33
44
FA
45
46
1C
47
EC
48
70F5
EA
49
F520
50
E9
51
13
52
F521
53
9209
54
55
C20F
22
56
57
This program contain,s a subroutine ADC which reads
in the serial data from the TLV1549 10-bit ADC
and places the most significant byte in address 20H
and least significant byte in address 21H
*
*
*
*
*
*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
EQU 20H
MSBYTE
j* * * * * * * * * * * * * * * * * * *
;* *
LSBYTE
COUNT
START:
ADC:
DELAY:
LABELl:
LABEL2:
LOOP:
Name data destinations
*
and COUNT register
*
j* * * * * * * * * * * * * * * * * * *
ORG 22H
;Set start address
MOV COUNT, #02H ;Set COUNT=2 (Do 2 conversion,s)
JMP ADC
;Jump to subroutine ADC
JMP START
;Repeat above again
SETB P3.4
j* * * * * * * * * * * * * * * * * *
MOV A, nOH
;* Set Port3 (bit 4) high
*
DEC A
;* (Sets CS of TLV1549 high)
*
JNZ DELAY
:* * * * * * * * * * * * * * * * * * *
CLR P3.4
MOV SCON, nOH
JNB SCON.O, LABELl
;Read in
;most significant
CLR SCON.O
MOV RO,SBUF
; byte, place in RO
JNB SCON.O, LABEL2
;Read in
CLR SCON.4
;least significant
CLR SCON.O
;byte,
MOV R1, SBUF
;p1ace in R1
;COUNT-1
DEC COUNT
,
MOV A, COUNT
JNZ ADC
;If COUNT not - 0,
;do another conversion
MOV R4, #08H
;Put 08H in R4
MOV R2, OOH
CLR C
:* * * * * * * * * * * * * * * * * * *
MOV A, RO
;*
*
RRC A
;*
*
MOV RO, A
Reformats MSByte
;*
*
MOV A, R2
;. *
*
RLC A
;*
*
MOV R2, A
;*
*
DEC R4
;*
*
MOV A, R4
;*
*
JNZ LOOP
j* * * * * * * * * * * * * * * * * * *
MOV A, R2
,
MOV 20H, A
MOV A, R1
;* * * * * * * * * * * * * * * * * * *
RRC A
;*
*
MOV 21H, A
Reformats LSByte
;*
*
MOV 21H.1, C
i*
*
CLR 21H.7
;* * * * * * * * * * *'* * * * * * * *
RET
;Return from subroutine
END
EQU 21H
EQU R3
;*
;*
*
ANALOG CONSIDERATIONS
Analog Reference for the TLV1549
The REF + terminal of the n,v1549 can be directly connected to the vee rail of the device. This produces accurate
results for analog input signals right up to the supply rail. However, if the operational amplifier driving the input is
supplied from the same single supply as the ADC, the output of the operational amplifier could possibly be nonlinear
up to the rail voltage. Ifthis is a concern, a lower reference voltage as shown in Figure 6 can be applied to REF +providing
more headroom for the amplifier.
The output of the TL2262A 3-V single-supply operational amplifier can swing to within 10 mV of its positive supply
rail. This effectively loses only two least significant bits (LSBs) off the top of the digital output range of the TLV1549
when both the amplifier andADC are powered from the same 3-V supply. The circuit shown in Figure 6 provides a 2.5-V
reference to the converter, which restores those bits to the digital output of the TLVlS49 while the maximum analog
input swing is reduced to 2.5 V.
--~.------------- Vee (3 V)
20kO
1/2TL2262A
> - - - - - - . . - . V r e f (2.5 V)
~-4-""
AD589
(1.235-V reference)
10kO
10kO
------__----__-------------------GND
Figure 8. User Adjustable 2.5-V Reference Circuit
PCB Layout
As with all precision analog components, care should be taken in laying out the printed-circuit board (PCB) on which
the TLV1549 and chosen microcontroller are placed. The interaction between digital and analog signal paths should be
minimized by keeping them as far apart as is physically possible within the constraints of the dimensions of the PCB.
Grounding and Decoupllng
Each supply terminal to both the TLV1549 and the microcontroller should be decoupled by a ceramic capacitor of
approximately 100 nF in value, situated close to the terminal of the device. Digital and analog groundretum paths should
be kept separate to prevent any digitally generated currents from corrupting the analog signal.
8-135
APPENDIX A
References
MC68HC705C8 Technical Data Mantial (1990)
M68HC05 Applications Guide
1LV1549 Data Sheet
TMS7000 Family Data Manual (1991)
Embedded Microcontrollers and Processors Vol. 1
8-136
Motorola
Motorola
Texas Instruments Incorporated
Texas Instruments Incorporated
Intel Corporation .
TLC2932
Phase-Locked-Loop Building Block With Analog
Voltage-Controlled Oscillator and
Phase Frequency Detector
.1ExAs
INSTRUMENTS
Printed on Recycled Plpel
8-137
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or
to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to
verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software
to the specifications applicable at the time of sale in accordance with TI's
standard warranty. Testing and other quality control techniques are utilized to
the extent TI deems necessary to support this warranty. Specific testing of all
parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may invoive potential
risks of death, personal injury, or severe property or environmental damage
("Criticai Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN
LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS;
Inclusion ofTI products in such applications is understood to be fully atthe risk
of the customer. Use of TI products in such applications requires the written
approval of an appropriate TI officer. Questions concerning potential risk
applications should be directed to TI through a local SC sales office.
In order to minimize risks. associated with the customer's applications,
adequate design and operating safeguards should be provided by the
customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described
herein. Nor does TI warrant or represent that any license, either express or
implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might
be or are used.
Copyright © 1995, Texas Instruments Incorporated
~138
Contents
Section
Title
Page
1 INTRODUCTION ..................................................................... 8-143
2 THEORY OF AN ANALOG PHASE-LOCKED LOOP (PLL) ................................
2.1 Overview .......................................................................
2.2 General Operation of a PLL ........................................................
2.2.1 Analysis of a PLL as a Feedback Control System .................................
2.2.2 Defmitions ...............................................................
2.3 PLL Functional Blocks ............................................................
2.3.1 Voltage-Controlled Oscillator (VCO) ...........................................
2.3.2 Phase Detector Operation and Types ...........................................
2.4 Loop Filter ......................................................................
2.5 Transfer Function Using a Lag-Lead Filter .............................................
2.6 Transfer Function Using an Active Filter ........................................... : ..
2.7 General Design Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . ..
2.8 Frequency Division ................................................................
2.8.1 Prescaler Method ..........................................................
2.8.2 Pulse Swallow Method (2s Modulus Prescaler Method) ............................
8-144
8-144
8-144
8-144
8-146
8-146
8-146
8-147
8-150
8-150
8--152
8-154
8--157
8-157
8-158
3 TLC2932IPW .........................................................................
3.1 Overview .......................................................................
3.2 Voltage-Controlled Oscillator (yCO) .................................................
3.3 Phase Frequency Detector (PFD) ....................................................
3.4 Loop Filter ......................................................................
3.5 Setting System Parameters ..........................................................
3.5.1 Setting the Phase Reference Frequency and Output Frequency from a Reference Signal
Source ..................................................................
3.5.2 Setting the Frequency Division Ratios of the Programmable Counter and Prescaler ......
3.5.3 Setting the Lock-Up Time ...................................................
3.5.4 Determining the Damping factor,/;; ............................................
3.5.5 Calculating the PLL Natural Angular Frequency, Wn ..............................
3.5.6 Calculating VCO Gain, KV ..................................................
3.5.7 Calculating PFD Gain, Ka ...................................................
3.5.8 Lag-Lead Filter Case .......................................................
3.5.9 Active Filter Case ..........................................................
3.6 Layout Considerations .............................................................
3.7 Input-Output Protection Circuits .....................................................
8-160
8-160
8-160
8-160
8-161
8-161
4 APPLICATION EXAMPLE . ............................................................
4.1 Introduction .....................................................................
4.2 National Television System Committee (NTSC) Method 4 Frequency Sub-Carrier (fsc),
8 fsc Output Signal Evaluation .....................................................
4.3 Evaluation Results (phase Reference Frequency - fsc, Output Frequency - 4 fsc) . . . . . . . . . . . . ..
4.3.1 Programmable Counter and Prescaler Frequency Division Ratio Settings ..............
4.3.2 Loop Filter Parameter Settings ................................................
4.3.3 Passive Lag-Lead Filter Used as a Loop Filter. . . . . . . . . .. .. . . . . . . . . .. . . . . . .. . . . . ..
4.3.4 Active Filter Used as a Loop Filter. . . . . . . . . . . . . . . . . . .. .. . .. . . . . . .. . . . . . .. . . . . ..
4.4 Evaluation Results (Phase Reference Frequency - 4 fsc/910,
Output Frequency - 4 fsc) ........................................................
4.4.1 Programmable Counter and Prescaler Frequency Division Ratio Settings ..............
4.4.2 Loop Filter Settings ........................................................
8-168
8--168
8-161
8-161
8--162
8--162
8--162
8-162
8-162
8-163
8-164
8-166
8--166
8--168
8-169
8-169
8-170
8-170
8-170
8--171
8--171
8--171
8-139
Contents (Continued)
Section
ntle
4.4.3 Passive Lag-Lead Filter Used as a Loop Filter ....................................
4.4.4 Active Filter Used as a Loop Filter .............................................
4.5 Evaluation Results (phase Reference Frequency - fscl91O, Output Frequency - 8 fsc) ..........
4.5.1 Programmable Counter and Prescaler Frequency Division Ratio Settings ..............
4.5.2 Loop Filter Settings ........................................................
4.5.3 Passive Lag-Lead Filter Used as a Loop Filter ....................................
4.5.4 Active Filter Used as a Loop Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.6 Summary .......................................................................
4.7 ExatnplesofaPLLApplication .....................................................
4.7.1 Generating a 4fsc NTSC Signal from aNTSC Signal ..............................
4.7.2 Generating a 4 fsc PAL Signal from a PAL Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8-140
Page
8-172
8-172
8-173
8-173
8-174
8-174
8-174
8-175
8-175
8-175
8-176
List of Illustrations
Figure
Title
Page
2-1.
Basic PLL Block Diagram ........................................................... 8-144
2-2.
Linearized PLL Block Diagram ...................................................... 8-144
2-3.
PLL Frequency Synthesizer Block Diagram ............................................. 8-145
2-4.
Linearized PLL Frequency Synthesizer Block Diagram .................................... 8-145
2-5.
Concept Behind Hold-In Range and Lock-In Range ...................................... 8-146
2-6.
OR Gate 'IYpe Phase Detector ........................................................ 8-147
2-7.
ExOR Gate 'IYpe Phase Detector ...................................................... 8-148
2-8 .
3-State Buffer 'JYpe Phase Detector .................................................... 8-148
2-9.
RS Flip-Flop 'IYpe Phase Detector .................................................... 8-149
2-10.
3-State Phase Frequency Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-150
2-11.
Lag-Lead Filter ................................................................... 8-150
2-12.
Active Filter ...................................................................... 8-152
2-13.
PLL Step Response Using the Active Filter in 2-17 ....................................... 8-154
2-14.
YCO Oscillating Frequency Characteristic .............................................. 8-155
2-15.
Phase Frequency Detector Output Characteristic ......................................... 8-156
2-16.
Lag-Lead Filter (With Additional Capacitor) ........................................ ~ ... 8-156
2-17.
Active Filter (With Additional Capacitor) ............................................... 8-157
2-18.
Programmable Counter ............................................................. 8-157
2-19.
Prescaler Method .................................................................. 8-157
2-20.
PLL Synthesizer Using Prescaler ..................................................... 8-158
2-21.
Pulse Swallow Method (2s Modulus Prescaler Method) ................................... 8-158
2-22.
PLL Frequency Synthesizer Based on Pulse Swallow Method ............................... 8-159
3-1.
Setting the YCO Oscillating Frequency ................................................ 8-160
3-2.
TIming ofPFD Operation ........................................................... 8-161
3-3.
Block Diagram ofPLL Synthesizer Using the Prescaler Method ..... : ....................... 8-161
3-4.
YCO Oscillating Frequency Characteristic .............................................. 8-162
3-5.
PLL Transfer Function Gain Characteristics and Phase Characteristics
(Lag-Lead Filter used as Loop Filter) .................................................. 8-164
3-6 .
PLL Step Response Characteristic
(Lag-Lead Filter used as Loop Filter) .................................................. 8-164
3-7 .
PLL Transfer Function Gain Characteristics and Phase Characteristics
(Active Filter used as Loop Filter) .................................................... 8-165
3-8.
PLL Step Response Characteristic
(Active Filter used as Loop Filter) .................................................... 8-165
4-1.
4 fsc Output Evaluation Block Diagram ................................................ 8-168
4-2.
Evaluation Circuit (Based on Number 2 of Table 4-1)
(Lag-Lead Filter Used as Loop Filter) .................................................. 8-169
4-3.
Wavefonns Using Passive Lag-Lead Filter
(IOOnsldivonhorizontalaxis) ....................................................... 8-170
4-4.
Spectrum of the YCO Output Signal When Using a
Passive Lag-Lead Filter (100 kH:zJdiv on horizontal axis) .................................. 8-170
8-141
List of DIustrations (Continued)
Figure
Title
4-5
Wavefonns Using Active Filter (100 nS/div on horizontal axis) ..............................
4-6.
Spectrum of the VCO Output Signal When Using an Active Filter
l(l00kHzldiv on horizontal axis) ......................................................
4-7.
Wavefonns Using Passive Lag-Lead Filter
(100 ns/div on horizontal axis) ............................................. ; .........
4-8.
Spectrum of the VCO Output Signal When
Using a Passive Lag-Lead Filter (100 kHzldiv on horizontal axis) ...........................
4-9.
Wavefonns Using Active Filter
(IOOnS/divonho!izontalaxis) .......................................................
4-10. Spectrum of the VCO Output Signal When Using an Active Filter
(IOOkHzldiv on horizontal axis) ......................................................
4-11. Wavefonns Using Passive Lag-Lead Filter
(100 ns/div on horizontal axis) .......................................................
4-12. Spectrum of the VCO Output Signal When Using a Passive Lag-Lead Filter
(IOOkHzldiv on horizontal axis) ......................................................
4-13. Waveforms Using an Active Filter
(100 ns/div on horizontal axis) .......................................................
4-14. Spectrum of the VCO Output Signal When Using an Active Filter
(100 kHzldiv on horizontal axis) ......................................................
4-15. Generating a 4 fsc (NTSC) Signal by Multiplying the Horizontal Synchronization Frequency .....
4-16. Generating a 4 fsc (PAL) Signal by Multiplying the Horizontal
Synchronization Frequency,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-17. Multiplying the Horizontal Synchronization Frequency of a NTSC Signal or
PAL Signal to Generate a 13.5 MHz Output ............ ; . .. . . .. . . . .. . . .. . . . . . . .. .. .. . ...
Page
8-171
8-171
8-172
8-172
8-173
8-173
8-174
8-174
8-175
8-175
8-176
8-176
8-177
List of Tables
Table
3-1.
Title
Page
Frequency Settings ................................................................ 8-161
3-2.
Settings for Frequency Divide Ratios of the Programmable Counters and Prescaler .............. 8-162
3-3.
PLL Design Specifications .......................................................... 8-163
3-4.
3-5.
PLL Circuit Specifications (SELECT Tenninal- H Level) ................................. 8-163
Calculation Example of Lag-Lead Filter Parameters ...................................... 8-163
3-6.
Calculation Example of Active Filter Parameters . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . . .. .. . . . ... 8-165
3-7.
Input-Output Protection Circuits ...................................................... 8-166
4-1.
4-2.
Evaluation Conditions (VDD - 5 V, TA - 25°C, RBIAS - 3.3 Jill) .........•................. 8-168
Frequency Division Ratio Settings .................................................... 8-169
4-3.
4-4.
4-5.
4-6.
4-7.
Loop Filter Parameter Settings' ..........................................' ............. 8-170
8-142
Frequency Division Ratio Settings .................................................... 8-171
Loop Filter Parameter Settings ....................................................... 8-172
Frequency Division Ratio Settings .................................................... 8-173
Loop Filter Parameter Settings ....................................................... 8-174
1 INTRODUCTION
The 1LC2932IPW integrated circuit (IC) contains a voltage-controlled oscillator (YCO) and a phase frequency detector
(PFD) for use in phase-locked-loop (PLL) circuit blocks. A standalone PLL circuit can be designed with the addition
of an external frequency divider and a loop filter.
Because the on-chip analog YCO has a wide usable lock frequency range and can cover a wide range of frequencies
(11 MHz-50 MHz) previously unavailable, many new applications are now possible. A stable clock output can be
achieved with only one external resistor required for the oscillator. The on-chip PFD uses a widely accepted
edge-triggered charge pump circuit. The 1LC2932IPW is designed for use as clock frequency generator blocks in digital
signal processor (DSP) applications involving video where many video signal frequency bands are possible. Refer to
the 1LC2932 data sheet (SLAS097) for other features.
For the proper usage of the 1LC2932IPW, basic concepts relating to conventional PLL blocks and examples based on
experimental results are described in this application report. In the design of a high perfonnance PLL circuit, the
parameters of the peripheral circuits such as the counter frequency division setting and the loop filter parameters are
determined by the application. The fundamentals needed to produce a high perfonnance PLL are discussed, and the
YCO, PFD, frequency divider, and loop filter are examined individually and then as a group.
11-143
2 THEORY OF AN ANALOG PHASE·LOCKED LOOP (PLL)
2.1 Overview
A phase-locked loop is a feedback controlled circuit that maintains a constant phase difference between a reference
signal and an oscillator output signal.
2.2 General Operation of a PLL
Figure 2-1 shows a basic block diagram of a PLL. A phase frequency detector compares the phase of the yeO output
frequency, fose, with the phase of a reference signal frequency, fref' A phase detector output pulse is generated in
proportion to that phase difference. This pulse is smoothed by passing it through a loop filter. The resulting dc component
is used as the input voltage for controlling the yeo. The output of the yeO, fos e• is fed back to the phase frequency
detector input for comparison which in tum controls the yeO oscillating frequency to minimize the phase difference.
Therefore, both frequency and phase are made the same, i.e., fose - frefand eose - eref, such that the phase and frequency
of the yeo and the reference signal source are in a locked state.
Reference
Signal
Source
fREF
eREF
Phase
Frequency
Detector
KA
...,.....
•
Oscillator
Outputs:
fosc,90sc
Loop
Filter
KF(S)
f--
Voltage
Controlled
Oscillator
KV(s)
-+-
Figure 2-1. Basic PLL Block Diagram
Therefore, the PLL is a negative feedback circuit which compares the current value to a reference value to make the
difference as close to zero as possible.
2.2.1 Analysis of a PLL as a Feedback Control System
An analysis can be performed using the linearized block diagram in Figure 2-2.
Reference
Signel
Source
eREF(s)
+
-
Ke
...,.....
Control
Level (Vel
KF(S)
KV(s)
!--< .... eosc (s)
~
Figure 2-2. Linearized PLL Block Diagram
The parameters in Figure 2-2 are defined as follows:
Ka - gain of the phase frequency detector (V/rad)
Kp - transfer function of the loop filter (YN)
y c - yeO control level
Ye - yeo control level
s - Laplace variable
Using a Laplace transform, the closed-loop transfer function can be expressed as:
eosc(s)
eREp(s)
Ke X Kp(s) x Ky(s)
= 1 + Ke x KF(s) x Ky(s) = W(s)
(2.1)
The yeO transform gain, Kv, is a function of time. Since phase is the time integral of frequeJ?cy, the gain can be
expressed as follows:
Ky
Ky(s) = -sThe phase frequency detector gain is assumed to not to be a function of frequency.
8-144
(2.2)
From equation 2.1 and equation 2.2
W (s)
Ke x KF(s) x Ky
= ---.,....:::--""="-:-:-----:==_
s + Ke x KF(s) x Ky
(2.3)
This equation is the general linear transfer function for a PLL.
The PLL has become widely used as a frequency synthesizer by generating frequencies from a single reference signal
source such as a crystal oscillator.
Consider the operation of the PLL frequency synthesizer in Figure 2-3.
Reference
Signal
Source
fREFIN,
eRE FIN
Frequency
Divider
(Ratio: M)
fREF
eREF
~
Phase
Frequency
Detector
-....
Loop
Filter
•
f+-
Oscillator
Yoltage
Controlled ~~ Outputs:
foac,eosc
Oacillator
Frequency
Divider
(Ratio: N)
Figure 2-3. PLL Frequency Synthesizer Block Diagram
Since the signal from the reference signal source is used to generate the desired frequency in a frequency synthesizer,
only frequencies at multiples of the reference frequency can be obtained.
The phase frequency detector compares the signal from the lIN frequency divider which divides the output signal of
the YCO, and the signal from the 11M frequency divider which divides the output signal of the referer..ce signal source,
and controls the YCO frequency in such a way so that both frequency and phase are the same.
f f'
f
Therefore ...!!L!!! = osc
(2.4)
and the oscillating frequency, fosc = frefm x ~
(2.5)
M
N
The closed-loop transfer function of the PLL in equation 2.1 can now be considered. If 11M and liN frequency dividers
are inserted into the block diagram of Figure 2-3, then Figure 2-2 becomes Figure 2-4.
Control
Level (Ve>
eREF(s)
Reference
Signal
Source
~
11M
+'J......+-
-
Ke
eosc(s)lN
--+-
I
Ky(s)
KF(s)
1/N
--4 .....
eoac(s)
I
Figure 2-4. Linearized PLL Frequency Synthesizer Block Diagram
Thus, the closed-loop transfer function can be expressed by the following equation:
W(s) =
Ke x Kp(s) x Ky
Ke x Kp(s) x Ky
s +
N
(2.6)
If the multiplication parameter N is set to 1 in equation 2.6, it becomes equation 2.3.
In this application report, equation 2.6 is used as the closed-loop transfer function for the PLL.
From equations 2.3 and 2.6, the closed-loop transfer function of the PLL is heavily dependent on the characteristics of
the loop filter which is discussed later in this application report.
8-145
2.2.2 Definitions
2.2.2.1 Free Running Frequency
The free oscillating frequency of the YCO whim it is in an unlocked state is called the free running frequency.
2.2.2.2 Hold-In Range (Lock Range) and Lock-In Range (Capture Range)
When the PLL is in the phase-locked state, the frequency range in which the frequency of the input reference signal,
fREF can slowly be pulled away from the free running frequency of the YCO but still maintain the phase-locked
condition is called the hold-in range or lock range. When the PLL is not in the phase-locked state, if the frequency of
the input signal, fREF' slowly approaches the free running frequency of the YCO, the frequency range in which the input
signal becomes phase-locked is called the lock-in range or capture range.
~--.....- - Frequency
\--+--4---
Frequency
fO : PLL Free Running Frequency
t.fL : Lock-In Frequency Range
t.fH : Hold-In Frequency Range
I
~
Figure 2-5. Concept Behind Hold-In Range and Lock-In Range
Referring to the conceptual diagram in Figure 2-5, if the input signal frequeny is increased slowly from a very low
frequency not phase-locked to the YCO free running frequency, phase-lock occurs at frequency fl. If the input signal
frequency continually increases, it will pass through the free running frequency and then become unlocked at frequency
f2' Conversely, if the input signal frequency is decreased slowly from a very high frequency not phase-locked to the YCO
free running frequency, phase lock occurs at frequency f3' If the input signal frequency continually increases, it will pass
through the free running frequency and the PLL becomes unlocked at frequency f4' The hold-in range, MH, and lock-in
range, ML, can be expressed as the following equations:
MH = (f2 - f4)
(2.7)
ML = (f3 - f 1)
(2.8)
Normally, the relationship of t.fH > t.fL exists.
2.2.2.3 Lock-Up Time (Acquisition Time)
The amount of time required for the loop to phase lock is called lock-up time or acquisition time.
2.3 PLL Functional Blocks
2.3.1 Voltage-Controlled Oscillator (VCO)
The YCO is an oScillator circuit with the following characteristics whose output frequency is controlled by a voltage.
• Kv - YCO gain (rad/Y/sec) from Section 2.2.1
• Stable with respect to external disturbances (change in voltage, temperature, etc.)
• Control voltage versus oscillating frequency should ideally be linear
• Frequency adjustment should be simple
8-146
Because it is extremely difficult to satisfy all these conditions at the same time, a suitable oscillator should be chosen
based on the application.
Oscillators that are typically used include the following:
•
•
•
Crystal oscillator
LC oscillator
CR oscillator
For a VCO utilizing any of the above oscillation techniques, many excellent technical books and articles on VCO circuit
design should be used.
2.3.2 Phase Detector Operation and Types
A phase detector detects phase differences between two input signals and produces a voltage based on this phase
difference.
Phase detectors can be either analog or digital. For analog, representative devices are ring modulators and multipliers
which are also called double balanced mixers. For digital, representative devices are OR-gates, ExOR-gates, RS
flip-flops, 3-state buffers, and phase frequency detectors.
Only the digital phase detectors are discussed in this application report.
2.3.2.1 OR-Gate Type Phase Detector
The simplest form of digital type phase detectors is the OR-gate type shown in Figure 2--6(a).
For an OR-gate type phase detector, the output signal duty cycle varies depending on the phase difference, as shown in
Figure 2--6(b). Then this output signal is smoothed by an integrator. The resulting output voltage in relation to the phase
difference is shown in Figure 2--6(c).
Input Signal 1
=D--
Input Signal 2
Output Signal
Input Signal 1
(a) OR GATE
Input Signal 2
Output
o
Phase Difference
ruL
~
J
u
L
(b) INPUT AND OUTPUT SIGNALS OF OR GATE
(el OR GATE TYPE PHASE DETECTOR OUTPUT CHARACTERISTIC
(OUTPUT SIGNAL SMOOTHED BY AN INTEGRATOR)
Figure 2-6. OR Gate Type Phase Detector
8-147
2.3.2.2 ExOR-Gate Type Phase Detector
An ExOR gate phase detector is shown in Figure 2-7(a).
InplltSIgnal1
=D-
Inpllt Signal 2
OlltPllt Signal
. (a) ExOR GATE
o
InplltSIgnal1
~
Input Signal 2
~
Output
lJ1JUlf
Phase Difference
(e) ExOR GATE TYPE PHASE DETECTOR OUTPUT CHARACTERISTIC
(OUTPUT SIGNAL SMOOTHED BY AN INTEGRATOR)
(b) ExOR GATE INPUT AND OUTPUT SIGNALS
Figure 2-7. ExOR Gate Type Phase Detector
For this type of phase detector, the duty cycle of the output signal varies depending on the phase difference, as shown
in Figure 2-7(b). This output signal is also smoothed by an integrator. The resulting output voltage in relation to the phase
difference is shown in Figure 2-7(c).
For this ExOR-gate type of phase detector, as compared to an OR-gate type of phase detector, the integrator output signal
swings from 0 V to the supply voltage, VOO. Moreover, because the ExOR-gate output frequency is twice that of the
OR-gate, the high frequency components are more easily filtered out by the integrator.
However, when using an ExOR-gate as a phase detector, if each input signal duty cycle is not 50%, the output voltage
generated from the phase difference does not have acceptable linear characteristics. Therefore, care must be exercised
when using this type of phase detector.
2.3.2.3 3-State Buffer Type Phase Detector
A 3-state buffer phase detector is shown in Figure 2-8(a).
The 3-state buffer phase detector output characteristic, as shown in Figure 2-8(c), is basically the same as ExORgate
phase detector. However, when input signal 2 is high, the output is in a high impedance state as shown in Figure 2-8(b).
Inpllt Signal 1
InputSIgnel2
-----f':>o.-~
Output Signal
Input Signal 1
~
InplltSIgnal2
~
.
(a) 3-STATE BUFFER
Output
o
na..___
(b) 3-STATE BUFFER INPUT AND OUTPUT
SIGNALS (OUTPUT HIGH IMPEDANCE
WHEN INPUT SIGNAL 2 IS HIGH)
Phase Difference
(e) 3-STATE BUFFER TYPE PHASE DETECTOR OUTPUT CHARACTERISTIC
(OUTPUT SIGNAL SMOOTHED BY AN INTEGRATOR)
.
Figure 2-8. 3-State Buffer Type Phase Detector
8-148
-.Il
2.3.2.4 R-S Flip-Flop Type Phase Detector
A R-S flip-flop phase detector is shown in Figure 2-9, and the input and output signals are shown in Figure 2-9(b).
As shown inFigure 2-9(c), a RS flip-flop type phase detector has twice the comparison range of an ExOR gate type phase
detector.
The R-S flip-flop type phase detector can be constructed using only an R-S flip flop. The pulse width of the input signal
pulses is small, so a SET-RESET error difference do not cause a significant error. This condition can be solved by
inserting AND-gates as shown in Figure 2-9(a).
Input Signal 1
Output Signal
--""1.._
Input Signal 2
Input Signal 1
Input Signal 2
Jl__. . .n. ___
n
nL
-----' ",,----I
outPut~
(a) R-S FLIP-FLOP
~l .-S 'UP-FLOP INPUT AND OUTl'UT ..GNALS
o
Phaaa Difference
(e) R-S FLIP-FLOP TYPE PHASE DETECTOR OUTPUT CHARACTERISTIC
(OUTPUT SIGNAL SMOOTHED BY.AN INTEGRATOR)
Figure 2--9. RS Flip-Flop Type Phase Detector
2.3.2.5 Phase Frequency Detector (PFD)
Of the phase detectors currently available, the most commonly used in a PLL is a circuit called a phase frequency
detector. Figure 2-10(a) show~ an example of a phase frequency detector.
In Figure 2-1 O(b), when the input signal 2 phase lags that of input signal 1, phase detector output D goes high starting
from the rising edge of input signal 1 to the rising edge of input signal 2, that is, during the period of time corresponding
to a phase difference between inputs 1 and 2, output D goes high. During this same period, output U stays low. When
the phase of input 2 leads that of input 1, output D stays low from the rising edge of input 2 to the rising edge of input
1. During that time, U goes high.
When both inputs 1and 2 have the same phase, both outputs D and U stay low. Depending on the phase detector outputs
D and U, the charge pump MOS transistors are turned on and off resulting in output levels of VOH, VOL, or high
impedance. So when D is high and U is low, the MOS transistor Ql is on and Q2 is off, therefore, the outputlevelis VOH.
When U is high and D is low, Q2 is on and Ql is off, resulting in the output level of VOL' When both D and U are low,
Ql and Q2 are both off and the output becomes high impedance.
In this way, the output level is proportional to the phase difference. The output signal characteristic is shown in
Figure 2-10(c).
8-149
VDD
Input
Signal 1
D
Input
Signal 1
n
n
n
.J L-J. L-J L
Input
Signal 2
U
[---------~- VOH
Input
Signal 2
Output
~--~v
Phase Detector
~--VOL
V~------JI
Charge Pump
(a) 3-STATE PHASE FREQUENCY DETECTOR
VOH
outpu[
Voltage
Level
(b) PHASE FREQUENCY DETECTOR
~_
_ ._ _..!NPUT AND OUTPUT SIGNALS
-
VOL
-
-
-:-2n; -
0 -
-
2n;--
Phase Difference
(c) PHASE FREQUENCY DETECTOR OUTPUT CHARACTERISTIC
Figure 2-10. 3-8tate Phase Frequency Detector
2.4 Loop Filter
The loop filter smooths the output pulses of the phase detector and the resulting dc component is the VCO input. From
the closed-loop transfer function (equation 2.6) obviously the loop filter is very important in determining the
characteristics of the PLL response.
Some examples of a loop filter are a lag filter, a lag-lead filter, and an active filter. Among these, the most commonly
used are the lag-lead filter and the active filter. For these two filters, the PLL closed loop transfer functions are derived,
and design examples for the filter parameters are shown.
2.5 Transfer Function Using a Lag-Lead Filter
First, the lag-lead filter transfer function is derived from Figure 2-11. If a Laplace transform is taken, then
V0
K () _
I + sCI x R2
VD = F s - I + sCI(RI + R2)
Where
't l
= CI
x RI, 't2
= CI
I + S't 2
(
)
I + s 't l + 'tr
(2.9)
x R2
VD----:r
(2.10)
R1
vo
C1J;
Figure 2-11. Lag-Lead Filter
8-150
By substituting equation 2.9 into equation 2.6 and rearranging the tenns, the PLL closed-loop transfer function is
W(s) =
1 + st2
..,..-----,--------,----""-------~---
{h + t2)/K}
(2.11)
x s2 + {(N + K x t2)/(N x K)} x s + 1/N
Where
x KV
Ke
(2.12)
= K
If this equation is further expanded, it becomes
W(s)
= W l(s) +
W 2(s)
={
h + t 2)/K} x s2 + {(N I+ K x t2)/(N x K)} x s + l/N
+
(2.13)
st2
{h + t 2)/K} x s2 + {(N + K x t 2)/(N x K)} x s + l/N
The general transfer function for a second order system is shown below
G(s) =
1
(2.14)
(I/Wn2) x s2 + (2S/wn) x s + 1
Where Wn is the natural angular frequency and ~ is the damping factor.
If, in equation 2.15 the right hand side first tenn is designated as Wl(s) and the second tenn as W2(s), then Wl(s) is a
second order system as in equation 2.14 and W2(s) is a second order lag with gain of t2 multiplied by s.
If W 1(s) is equated to equation 2.14 and the coefficients compared
WI (s) =
1 + st2
{h + t 2)/K} x s2 + {(N + K x t2)/(N x K)} x s + 1/N
(2.15)
1
(1/wn2) x s2 + (2S/wn) x s + 1
the following are derived
(2.16)
S
=
1 + Kt2
2jN(tl+t2)XK
= Wn(t2 +.t:!)
2
(2.17)
K
Similarly for W2(S)
W 2(s) =
st2
{(tl + t 2 )/K} x s2 + {(N + K x t2)/(N x K)} x
(2.18)
S
+ l/N
(2~/wn - N/K) x s
8-151
Thus, using a lag-lead filter, the PLL closed-loop transfer function becomes
W(s) ,= W (s)
1
+W
1 + (2~/oon - N/K) x s
(1/00J) x s2 + (2~/oon> x s + 1
(s) =
2
(2.19)
From the above result, design equations fot lag-lead filter parameters are derived.
1ft} - C1 x R1 and t2 - C2 x R2 are substituted into equations 2.16 and 2.17 respectively and solved for R1 and R2,
the following equations are derived:
R1 =
(....lL
x 1.. - ~
+ N) x .l...
oon 2, N
oon K
C1
R2 =
(2~
_
oon
(2.20)
N) x .l...
K
(2.21)
C1
2.6 Transfer Function Using an Active Filter
When using an active filter, the PLL closed-loop transfer function and design equation for filter parameters are derived
in the same fashion as in Section 2.5.
First, the Laplace transform is taken and the transfer function of an active filteris derived. Figure 2-12 shows an example
of an active filter.
t Voltage used for single ended power supply systems.
Figure 2-12. Active Filter
The transfer function for the active filter is
1 + sCI
KF(s)
x R2
1
+ st2
= sCl(Rl + R2) = ~
(2.22)
Where
t}
= C1
x R1 and t2
= C1
x R2
(2.23)
From the PLL closed-loop transfer function, if Kp(s) is substituted into equation 2.6 and equation 2.6 is simplified, it
becomes
(2.24)
Where
Ke x KV
=K
(2.25)
as before.
1f this equation is expanded further, it becomes
W(s) = W 1(s)
+ W 2(s)
1
=
h/K) x s2
+ (t2/N)
h/K) x s2
+ (t2/N)
+
(2.26)
x s
+
l/N
x
+
l/N
st2
S
As shown before, second order lag resonators can be expressed as equation 2.14.
8-152
Following the procedure in Section 2.5.
IfWl(S) is equated to equation 2.14
WOO1
h/
K) x s2
1
+ ('t2/N)
_
x s
+
I/N
1
+ (2~/wn)
(I/Wn 2) x s2
x S+ 1
(2.27)
the following are derived
wn -
jNZ;1
s - ;~ -
(2.28)
j'tl/(N/K) -
~n
(2.29)
't2
Similarly for W2(S)
W (s) _
2
S't2
(2~/wo) x s
_
h/K) x s2 + ('t2/N) x S + I/N
(I/Wn2) x s2
+ (2~wrJ
x s
+1
(2.30)
Thus for the active filter, the PLL closed-loop transfer function becomes
W(8) _ W (8)
1
+W
(s) _
2
1
+ (~/wn> x s
(I/W;) x s2 + (2~/wn> x s + 1
(2.31)
From the above result, the design equation for active filter parameters can be derived.
If'tl - Cl x Rl and't2 -Cl x R2 are substituted into equations 2.28 and 2.29 respectively, and solved for Rl and R2,
the following two equations are derived:
Rl -
..JL x .1 x .L
wn 2
N
R2-~X.L
wn
Cl
Cl
(2.32)
(2.33)
8-153
2.7 General Design Procedures
Based on a PLL step response, the damping factor can be chosen, the natural angular frequency can be evaluated,and
the characteristics of response time and relative stability can be examined. For the PLL transfer function in equation 2.31,
the step responses of several cases are shown in Figure 2-13. As shown, the smaller the 1; value the larger the ringing,
and a large 1; value results in little or no ringing. Also, a larger Clln results in a faster response time.
The step response for a PLL using an active filter as a loop filteris shown in Figure 2-13. When a passive lag-lead filter
is used, if the condition Clln «KIN is met for equation 2.19, the step response is similar to the step response shown.
1.9
1.8
I Y
1.7
\
1.6
1.5
1.4
~
1.3
l)'
Ii::s
f
"i-lr--..,
1.1
I&.
-;
/
~
0.9
1z
0.8
0
.
e:
0
/
/
\V
,
~
~
I
/
/
r--~=0.7
~
~~
~
r/~
rJ /j
-,
I
-' \
/
/
\
'V
II
1\
0.6
\
VI
~
r-~=2.0
~
,-
\
' - ~ = 1.0
~
I
~
I I
0.7
~=0.4
1\
\
I "
1.2
)
1
~ =0.1
V-
J
\\.... l.//
0.5
0.4
0.3
0.2
0.1
o
I
o
2
3
4
5
6
7
8
9
10
11
Figure 2-13. PLL Step Response Using the Active Filter in Figure 2-17
8-154
12
13
To design a PLL system, ~ is selected first. Then from the step response characteristic, the value of CIlnt, at which the
response is decayed to within 5% of the fmal value, is found. Then CIlnt is divided by the desired lock-up time, ts' to
detennine CIln. The following steps should be followed.
I.
~
2.
Assume ~ is selected to be 0.7.
is a measure of stability. and usually ~ is selected to be between 0.6 to 0.8.
3.
The value of CIlnt from the step response characteristic is determined to be 4.5 for response settling within 5%.
4.
Lock-up time, la, is detennined by system requirements.
5. The PLL natural angular frequency, CIln, is
W
n
= wn'!: = 4.5 (rad/sec)
ts
ts
(2.34)
This criterion varies depending on the system application. It is app1"9priate to pick the natural frequency
(fn - ~2rr.) to be one tenth to one hundredth of the reference frequency of the phase frequency detector.
6. The frequency division ratio is detennined from the reference frequency and the desired frequency according
to equation 2.5.
7. Determine the veo gain parameter, KV. An example of a veo oscillating frequency characteristic is shown
in Figure 2-14.
I
fMAX
J
I
1MIN
I
~
Yeo - Control Voltage - Y
Figure 2~14. YCO Oscillating Frequency Characteristic
From the oscillating frequency characteristic of Figure 2-14, the veo gain can be determined using the
following equation:
K
V
=
f
MAX
- f
MIN x 2n [rad/sec/Vl
VMAX - VMIN
(2.35)
Where
fMAX - maximum frequency at which the linearity of the oscillating frequency versus the veo control
voltage can be maintained.
fMIN - minimum frequency at which the linearity of the oscillating frequency versus the veo control
voltage can be maintaitted.
VMAX - control voltage at which the veo oscillating frequency is fMAX
vMIN - control voltage at which the veo oscillating freq~y is fMIN
8-155
I
\
VOH - - -
--
Output Voltage
Range
VOL - - - - - - - - - - -2lt
0
2lt
~ Detectlon~
Phase
Range
Figure 2-15.. Phase Frequency Detector Output Characteristic
8. Detennine the phase detector gain parameter, Ko
Based on the phase frequency detector output characteristic in Figure 2-15, the phase detector gain can be
determined from equation 2.36.
Ke
=
VOH - VOL
41t
(2.36)
[V jrad]
Where
VOH - maximum output voltage
VOL - minimum output voltage
9.
For other types of phase detectors, the phase detector gain can be detennined in the same fashion.
Filter parameters can be determined by substituting each of the values detennined in steps 1 through 8 into
the corresponding equations.
For the lag-lead filter. substituting the desired values of ron. ~. N. and K into equations 2.20 and 2.21. the filter
parameters can be determined by choosing an appropriate value for Cl.
For a practical loop filter, a second order lag-lead filter with an additional capacitor C2. as shown in
Figure 2-16. to minimize spurious noise at the VCO input should be used.
R1
---'\IV'v--+-~~1C~2f
Figure 2-16. Lag-Lead Filter (With Additional Capacitor)
The value of C2 should be less than or equal to ClIlO to keep C2 from affecting the low-pass filter response while
providing adequate noise filtering.
Similarly for the case of an active filter. substituting the desired values of ron. ~. N. and K into equations 2.32 and 2.33.
the filter parameters can be determined by choosing an appropriate value for Cl.
Also when using an active filter as the loop filter. as shown in Figure 2-17. a second order active filter with one additional
capacitor should be used. .
.
.
The additional capacitor C2 is used for compensating the R2 high frequency response. The cutoff frequency. roc. of C2
and R2 should be chosen to be 10 times that of the natural frequency. ron. of the PLL.
roc = (C2
8-156
~
R2)
5!!
lOron
(2.37)
C2
R1
VCC
-2-
= VREF
-----I
Figure 2-17. Active Filter (With Additional Capacitor)
2.8 Frequency Division
When given an input signal with frequency f, a circuit that generates a fiN (N an integer) signal synchronized to the input
signal is called a frequency divider. Usually frequency dividers use programmable counters like the one shown in Figure
2-18 (programmable meaning that the frequency divide ratio N can be changed and controlled externally).
1-_ _ _ Output Signal
Frequency: fI N
Input Signal - - - - t
Frequency: f
Control Signal for Setting Frequency Divide Ratio (Ratio: N)
Figure 2-18. Programmable Counter
The construction of a PLL frequency divider using a programmable counter, and the prescaler and pulse swallow
methods (2s modulus prescaler method) are discussed in the following sections.
2.8.1 Prescaler Method
If the frequency, f, of an input signal is too high, a divide can be added using an additional programmable counter in
the feedback path. As shown in Figure 2-19, the frequency can be divided before the programmable counter using a
fixed frequency divider (prescaler) operating at high speed, this lowers the input frequency to the programmable counter.
This method is called the prescaler method.
Input Signal to Progremmable
Counter Frequency: flPI
Input Signal
Frequency: f
Output Signal
Frequency: fI (p x N)
Frequency Divide Ratio: P
(FIxed)
Control Signal for Setting
Frequency Divide Ratio (RatiO: N)
Figure 2-19. Prescaler Method
The pre scaler frequency dividing ratio is fixed. As shown in Figure 2-19, if the prescaler frequency divide ratio is P and
the programmable counter frequency dividing ratio is N, then the total frequency divide ratio becomes P x N. As shown
in Figure 2-20, if the frequency dividing ratios M and N of the programmable counters are changed, the veo oscillating
frequency is changed in steps ofP/M times the phase-reference frequency. Thus the channel space (frequency resolution)
becomes fREF x PIM. The PLL fREF should be chosen to be MIP of the channel space. Thus, iffREF is low, the loop-filter
time parameters must be designed to be large with respect to fREF; however, the lock-up time can become too large for
the application. Noise effects must be considered as well.
8-157
Reference
Signal
Source
REF,
9REF
Frequency
Divide
(Ratio: M)
Phase
Frequency
Detector
-+-
-
~
Frequency
Divide
(Ratio: N)
Loop
Filter
f-+-
-+-
Voltage
Controlled
Oseillator
Pre_ler
(Frequency Divide
Ratio: P)
--1 .......
Oselllator
Outputa:
fose,90se
--+-
Figure 2-20. PLL Synthesizer Using Prescaler
2.8.2 Pulse Swallow Method (2s Modulus Prescaler Method)
When the channel space is equal to 11M of the reference frequency, fREF' the technique is called the pulse swallow
method. This method uses a prescalerwhose frequency divide ratio can be changed by a control signal as shown in Figure
2-21.
I
Input Signal - . Frequency: f
Prescaler
(Frequency Divide
Ratio: P, P + 1)
Modu Ius Signal
II
..
Programmable
Counter
(Frequency Divide
Ratio: N)
Output Signal
Frequency: fO
=f/(P x N + S)
Where N > S, S > P
t
Control Signal for Setting
Frequency Divide Ratio
Swallow Counter
(Frequency
Divide
Ratio: S)
.
r--
t
Control Signal for Setting
Frequency Divide Ratio
Figure 2-21. Pulse Swallow Method (2s Modulus Prescaler Method)
The prescaler frequency divide ratio is P or P+ 1. The counter consists of a programmable counter and a swallow counter
which is used to control the prescaler. The frequency divide ratios are N and S respectively.
When the swallow counter is operating, the prescaler frequency divide ratio is P+ 1. The programmable counter and the
swallow counter operate in parallel with the condition N > S. The swallow counter counts up to S and then generates
a modulus signal to switch the prescaler. Then the prescaler's frequency divide ratio becomes P.
Thus, during the time period in which the swallow counter is dividing the frequency while counting up to S (time period
SIN), the total frequency divide ratio is (P+ 1) x N. During the remaining time period, N-8, in which the programmable
counter divides the frequency [time period (N-S)/Nl, the total frequency divide ratio is P x N. Now the output signal
frequency can be expressed by the following equation:
fo = f/(P x N
+ S)
(2.38)
By examining the actual operation of the PLL shown in Figure 2-22 and equation 2.38, P is the coefficient for N but
not for S. Thus, each time the value of S changes, the frequency only changes by fREPM. By using the pulse swallow
method and a prescaler, a channel space of fREp'M can be obtained.
8-158
,
Reference
Signal
Source
9REF
Programmable
Counter
(Ratio: M)
-+-
Phase
Frequency
Detector
-+-
-
Frequency
Divider
(Ratio: N)
~
Swallow
Counter
r+-
Programmable Counter
Used for SwallOW Counter
I
(1/S)
Loop
Filter
f-+-
i
Oscillator
Voltage
Controlled ~~ Outputs:
fosc,90sc
Oscillator
Prasceler
(1/p, 1/p + 1)
Figure 2-22. PLL Frequency Synthesizer Based on Pulse Swallow Method
Many variations exist by combining frequency dividers. A specific frequency divider technique can be adopted
according to the application.
8-159
3 TLC2932IPW
3.1 Overview
The TI..C2932IPW can be used for designing high perfonnance PLLs and consists of a voltage controlled oscillator
(VCO) operating at up to 50 MHz and an edge detection type phase frequency detector (PFD).
In the design of a PLL, the VCO lock range is detennined by the value of a single external bias resistor. In addition, by
using the inhibit fuTIction, the VCO can be turned off to reduce power dissipation. By switching the VCO output select
tenninal extemally, the output frequency can be divided in half. Thus, lower frequencies can be produced and a 50%
duty cycle can be achieved.
With the on-chip charge pump, the PFD detects the phase difference between the rising edges of an external input signal
and a phase-reference signal from a reference signal source. Also the PFD output can be controlled externally by the
input state to a high impedance output.
The design of a TI..C2932IPW system, calculations of loop filters, layout considerations, and input-output protection
circuits are explained in the following sections.
3.2 Voltage-Controlled Oscillator (VCO)
The TI..C2932IPW VCO has the following special features:
• The VCO only requires one external bias resistor for oscillation and for setting the VCO variable oscillating
frequency range. As shown in Figure 3-1, the possible lock frequency range is from 22 MHz to 50 MHz. The
range of possible settings for bias resistance is 1.5 kO to 3.3 kO.
Possible Range of
Veo Oscillating Frequency
:I!I
f
I
Ig
Value of Bias Resistance Settings
1.6 k.Q 3.3 k.Q
N
o
veo - Control Voltage -
V
Figure 3-1. Setting the veo Oscillating Frequency
•
•
By switching the VCO select terminal externally, the output frequency can be divided in half'to produce a
lower frequency; moreover, a duty cycle of 50% is possible. By using this function, the possible frequency
range is extended to 11 MHz. Video applications at 14.31818 MHz are possible.
TI..C2932IPW VCO has an inhibit function that is controlled externally
the output waveform can be initialized
power dissipation during power down can be reduced
For detailed specifications, refer to the TI..C2932 data sheet.
3.3 Phase Frequency Detector (PFD)
TI..C2932IPW PFD has the following special features:
• The PFD is a high speed edge triggered type with charge pump. As shown in Figure 3-2, the difference
between the rising edges of two input signal frequencies can be detected.
• Depending on the external controller, the PFD output
can be placed in a high impedance state
is static when put in the power down mode
8-160
FIN-A
FIN-B
PFD Out
Jl------------------------------lLf~~=
VOH
High Impedance
VOL
FIN-A: Phase-reference frequency Input from reference signal source
FIN-B: Externallnputfrequency
Figure 3-2. Timing of PFD Operation
3.4 Loop Filter
The loop filter design shown is based on the design equations for loop filter parameters derived in Sections 2.5. and 2.6.
Figure 3.3 shows a design based on the block diagram of a PLL synthesizer using the prescaler method.
r---------~--------~
Reference
Signal
Source
fREF,
9REF
Programmable
Counter
(Frequency
Division
Ratio: M)
I
I
4I
r--- - - I
Phase
Frequency
Detactor
I
I
-T+l
I
Loop
Flltar
L __ __ .J~
I
VCO
(Voltage
Controlled
OSCillator)
~
L _____
I
I
I
Oscillator
~~ Outputs:
fose,90se
I
-.JI
TLC29321PW
--+-
Programmsble
Countar
(Frequency
Division
Ratio: N)
......
Prascaler
(Frequency
Division
Ratio: P)
-
Figure 3-3. Block Diagram of PLL Synthesizer Using the Prescaler Method
3.5 Setting System Parameters
3.5.1 Setting the Phase Reference Frequency and Output Frequency from a Reference Signal
Source
Each frequency is set to the values shown in Table 3-1. A 14.31818 MHz crystal is used as the reference signal source.
This frequency is divided by 910 so that it can be used as the phase reference frequency. Then, the yeO output signal
is 14.31818 MHz.
Table 3-1. Frequency Settings
SYMBOL
VALUE
UNIT
Oscillating frequency
REFERENCE SIGNAL SOURCE
fREF
14.31818
MHz
Phase reference frequency
freflM
14.318181910
MHz
fose
14.31818
MHz
Output frequency
3.5.2 Setting the Frequency Division Ratios of t,he Programmable Counter and Prescaler
Using the settings in '{able 3-1, the frequency division ratios of the programmable counter and prescaler can be
determined. However, this time the design proceeds based on the settings in Table 3-2. In practice, the frequency
division ratio for the prescaler is based on the frequency operating range of the programmable counter input signal.
8-161
Table 3-2. Settings for Frequency Division Ratios of the Programmable Counters and Prescaler
PARAMETER
VALUE
Programmable counter
(Phase reference frequency side)
NAME
M
910
Programmable counter
N
455
Presceler
P
2
Therefore, the total frequency division ratio becomes P x N - 910.
3.5.3 Setting the Lock.Up Time
The required lock-up time is 2 ms which is the time it takes for the phase to lock and is dependent on system requirements.
3.5.4 Determining the Damping factor,
The damping factor,
s
S, is chosen to be 0.7.
3.5.5 Calculating the PLL Natural Angular Frequency, Cl>n
For S= 0.7 and from equation 2.34, ron is calculated to be
CI>
n
= Cl>nt =
t
= 2250 (rad/sec)
4.5
2 x 10-3
3.5.6 Calculating YCO Gain, Ky
Figure 3-4 shows an example of the oscillating frequency characteristic of the 1LC2932 internal VCO. The VCO gain
is calculated from a characteristic curve in the data sheet. By switching the SELECT terminal, the output frequency is
divided in half and the resulting characteristic curve is shown in Figure 3-4.
40
TA=25°e
N
35 I- VDD =5V
:::I!
RSIAS = 3.3 kn
30 I- SELECT = H
:c
I
r;o
c
CD
:::I
25
II.
aI
20
~
15
r
C
~
10
I
0
5
~fMAX
""
/
V
I
1/
fMIN
/ /
~"
VMIN
VMAX
V
V
2
3.
4
5
Veo - Control Voltage - V
Figure 3-4. YCO Oscillating Frequency Characteristic
The VCO gain, KY,from equation 2.35 is
K
V
=
fMAX - fMIN
VMAX - VMIN
x 23t = (27.5 ;
2) t
106
x 23t !: 41 x
106 [rad/sec/V]
(3.1)
3.5.7 Calculating PFD Gain, Ke
The PFD output characteristic is shown in Figure 2-15. By substituting the values obtained from the data sheet into
equation 2.36, the PFD gain is calculated to. be
Ke
8-162
!:
0.34 [Y /rad]
(3.2)
The design and circuit specifications mentioned above are listed in Tables 3-3 and 3-4.
Table 3-3. PLL Design Specifications
DESIGN SPECIFICATIONS
SYMBOL
NAME
Radian value to selected lock-up time
UNIT
VALUE
t;
PLL damping factor
0.7
4.5
ront
t
0.002
Desired output frequency
fosc
14.318180
Phase reference frequency
fREF
15734.26374
Lock-up time
rad
s
MHz
Hz
Table 3-4. PLL Circuit Specifications (SELECT Terminal
CIRCUIT SPECIFICATIONS (VDD
=H Level)
=5 v, RBIAS =3.3 ItO, TA =25°C)
NAME
SYMBOL
VALUE
veo frequency range
fMAX
27
fMIN
7.5
veo control voltage range
VMAX
4
VMIN
1
VOH
4.5
VOL
0.2
Phase detector output level
12.56
Phase detector range of detection
Frequency divide ratio
N
910
PLL natural angular frequency
ron
2250
UNIT
MHz
V
V
rad
radlsec
3.5.8 Lag-Lead Filter Case
From the design and circuit specifications above and using the lag-lead filter of Figure 2-16, C2 is selected to be 1110
of the Cl value.
The calculations are shown in Table 3-5. The transfer function gain characteristics and phase characteristics are shown
in Figure 3-5 and the step response is shown in Figure 3-6.
Table 3-5. Calculation Example of Lag-Lead Filter Parameters
LAG-LEAD FILTER
PARAMETER
VALUE
C1
1.00E-{).6
F
R1
2476
R2
557
n
n
1.00E-{)7
C2
Where C2 - C1 x 1/10
UNIT
F
8-163
20
""
0
'"
-20
0
-40
I·
I
\
Gain .Characterlstlc
~
-80
""
.c
Go
4S
-80
c
-100
'a
1
~
f'.
-120
./ '\
-140
~
' \ Phaae Characteristic
-180
.~
-180
10
1k
100
10k
100k
1M
10M
f - Frequency - Hz
Figure 3-5. PLL Transfer Function Gain Characteristics and Phase Characteristics
(Lag-Lead Filter used as Loop Filter)
1.2
I
!
(
I
o.
'"
1'-0..
(
.'
0.6
1
I
0.4
z
0.2
o
o
0.001
0.002
0.003
0.004
0.005
Tlme-s
Figure 3-6. PLL Step Response Characteristic (Lag-Lead Filter used as Loop Filter)
3.5.9 Active Filter Case
The active filter is shown in Figure 2-17. Each parameter can be calculated using equations 2.32 and 2.33. C2 is
calculated from equation 2.37 in Section 2.7.
Table 3-6 shows an example of these calculations. Figure 3-7 shows the transfer function gain characteristics and phase
characteristics of aPLL using the filter parameters in Table 3-6. Figure 3-8 shows the step response of utilizing the filter
parameters in Table 3-6.
8-164
Table 3-6. Calculation Example of Active Filter Parameters
ACTIVE FILTER
PARAMETER
VALUE
C1
1.00E-Q.6
UNIT
F
R1
3033
R2
622
n
n
7.14E-Q7
C2
Where C2 = R2I10 ron
20
~
0
"or--....
-20
"
-40
0
I
I
-60
IS
-80
"tI
I
-100
CJ
-120
c
'iii
Gain Characteristic
"
'\
.c
Do.
F
'"
'\
/ '\
-140
-180
10
"
~ Phase CharacterlsUc
lL
-160
f'....
100
1k
10 k
100 k i M
10 M
f - Frequency - Hz
Figure 3-7. PLL Transfer Function Gain Characteristics and Phase Characteristics
(Active Filter used as Loop Filter)
1.4
1.2
IIc
i
!
)
~
z
(
I
"-'"
0.8
0.6
0.4
0.2
o
o
0.001
0.002
0.003
0.004
0.005
Tlme-s
Figure 3-8. PLL Step Response Characteristic (Active Filter used as Loop Filter)
A basic design example for a PLL loop filter is somewhat of an ideal case. In practice, the PLL characteristics greatly
depend on the evaluation boilrd used and the layout of components in the system. Consequently, it is necessary to plan
the evaluation boilrd and system carefully.
8-165
Section 4, contains the evaluation results of the loop filters.
3.6 Layout Considerations
When designing an evaluation or production board, the following precautions, based on techniques used with high
frequency analog circuits must be ~xercised.
• Depending on the IC socket used, increased circuit resistance, inductance, and capacitance can degrade the
performance in some cases. Ifpossible, do not use IC sockets. Direct connection to the board is recommended.
• Extreme care should be exercised with wiring and connections. Casual wiring should be avoided.
• Power supplied to the VDD terminal of the VCO should be separated from the digital portion. Moreover, by
inserting high pass capacitors, noise coupling can be avoided as much as possible.
• It is necessary to consider the VCO ground terminal. The analog portion and digital portion must be separated.
The analog portion should be connected to a ground plane. The design should avoid the coupling of switching
noise from the digital portion.
• The loop filter ground should be connected to analog ground..
• External components (such as the loop filter and high pass capacitors) should be placed as close as possible
totheIC.
Layouts and bread boards must be carefully designed to realize the full potential of the TI..C2932. These techniques must
be used to ensure proper operation of the PLL design.
3.7 Input-Output Protection Circuits
The input and output protection circuits are shown in Table 3-7.
Table 3-7. Input-output Protection Circuits
TERMINAL
NAME
NO.
CIRCUIT
FUNCTION
VoltagE! supply terminal for internal logic. It Is
desirable to separatE! complE!tE!ly from the vee
voltagE! supply terminal.
.
LOGICVDD
SELECT
2
VCO output freqUE!ncy 112 dividl!r SE!lect terminal.
By controlling this tl!rmlnal using E!xtE!rnal logic,
the vee output frequency can bE! dividl!d in half.
VCOOUT
3
VCO output tE!rmlnal. During Inhibit, this tE!rminal
is takE!n low.
3
FIN-A,B
8-166
4,5
ThE! two input terminals usl!d for dlltecting thE!
edgE! difference of rererence frequl!nCY, fretlN,
and external countE!r's frequE!ncy. UsuallyfretlN is
connected to the FiN-A terminal and the E!xtE!rnal
countE!r output frequency is connactE!d to thE!
FIN-B tE!rminal.
Table 3-7. Input-Output Protection Circuits (Continued)
TERMINAL
NAME
PFOOUT
NO.
CIRCUIT
FUNCTION
The PFO output terminal can be put in high
impedance state.
6
LOGICGNO
7
'ntema"ogic ground terminal.
NC
8
Not connecled internally.
PFO INHIBIT
9
The PFO inhibit function control terminal.
VCOINHIBIT
10
VCOGNO
VCOIN
11
12
RBIAS
13
VCOVOO
14
The VCO inhibit function control pin
vco ground terminal
The VCO control voltage input terminal usually
connecled to VCO control voltage from the
extemalloop filter of PLL.
The terminal for connecting the bias resistor for
setting the VCO oscillating frequency. To provide
a bias for the operation of intemal VCO and for
frequency setting and tuning. a bias resistor is
connecled between this terminal and the power
supply line.
-l+---G
This terminal supplies the supply voltage to the
VCO. It is desirable to completely separate this
from the logic power terminal.
8-167
4 APPLICATION EXAMPLE
4.1 Introduction
An evaluation example using the 1LC2932IPW in a PLL application is described in the following sections.
4.2 National Television System Committee (NTSC) Method 4 Frequency Sub-Carrier (fsc),
8 fsc Output Signal Evaluation
Table 4-1 shows that by combining a phase reference frequency and loop ftlter, the NTSC method of 4 fsc and 8 fsc
output signals can be generated.
The block diagram is shown in Figure 4-1. Figure 4-2 shows the circuit for evaluation, using a passive lag-lead ftlter
as the loop ftlter. This evaluation circuit is based on the conditions stated in number 2 of Table 4-1.
When an active ftlter is used, because of additional inversion added to the loop, the phase frequency detector input signal
is reversed from that in the passive lag-lead filter case.
Table 4-1. Evaluation Conditions (Voo
NO.
PHASE
REFERENCE FREQUENCY
=5 V, TA =25°C, RBIAS =3.3 kO)
OUTPUT FREQUENCY
1
Iso (NTSC) = 3.579545 MHz
4 Iso (NTSC) - 14.31818 MHz
2
HD (NTSC). 4 IscJ91 0 ~ 15.7 kHz
4 Iso (NTSC) - 14.31818 MHz
3
HD (NTSC) - 4 IscJ91 0 .. 15.7 kHz
8 Iso ~ 28.63636 MHz
LOOP FILTER
EVALUATION RESULT
Section 4.3
Lag-lead and
active
Section 4.6
Section 4.9
,---- -,
,----------------~
Programmable
fREFIN
Xtal
Counter
Oscillator
(Phase
(14.31818 MHz)
Division
Ratio: M)
FIN·A
I
I
I
!
H
__ -1"
I
Phase
Frequency
Detector
I
IL __•
I
Loop
Filter
I
~
I
VCO
(Voltage
Controlled
Oscillator)
I
I
I
-1
'i
L _____ I
TLC2932IPW
FIN·B
Programmable
Counter
'--(Phase
Division
Ratio: N)
-+
Prascaler
(Phase
Division
Ratio: P)
Figure 4-1. 4 fsc Output Evaluation Block Diagram
8-168
-+
VCO
OUT
Oscillator
Output:
lose
DVDD
Oscilloscope
AVDD
1
-
LOGIC VDD
VCO VDD
10lJl't t o . 22 1J1'
0.221J1't 10l1Ft
DGND
....---
SELECT
3.3kn
VCOOUT
Xtal
Oscillator
Prasceler
(1/2)
J-~
BIAS
r-----'
I
R2
I
c..t :I I~
VCOIN
TLC2932IPW
Programmable
Counter
FIN-A
R1
VCOGND
~
(1/910)
Programmable
Counter
FIN-B
VCO
i---INHIBIT
PFDOUT
PFD
INHIBIT
(1/455)
Spectrum
Analyzer
~
~ LOGICGND
NC
I
I
I
I
I
I
L.r-----.J
Loop Filter
(Lag-Lead FIIter)
c--
r-
DONO
S1,S2 : On
: Off
S3
~~
S2
Programmable Counter : TC9122 (Counter)
Prasceler
: 74AC11074 (D-FF) X 2
S3
DVDD
I
.
~
47kn
DGND
Figure 4-2. Evaluation Circuit (Based on Number 2 of Table 4-1)
(Lag-Lead Filter Used as Loop Filter)
4.3 Evaluation Results (Phase Reference Frequency
=fsc, Output Frequency =4 fsc)
In this evaluation, the fsc (3.579545 MHz) shown as number 1 in Table 4-1, is used as the phase reference frequency
to generate a 4 fsc (14.31818 MHz) output frequency. The details and results for the cases of using a lag-lead filter and
an active filter as the loop filter are described in the following sections.
4.3.1 Programmable Counter and Prescaler Frequency Division Ratio Settings
Based on the evaluation block diagram of Figure 4-1, the frequency division ratio settings for the programmable
counters and prescaler are listed in Table 4-2.
Table 4-2. Frequency Division Ratio Settings
FREQUENCY DIVISION RATIO
Frequency divide value
8-169
4.3.2 Loop Filter Parameter Settings
From the loop filter design procedures of Sections 2.5 and 2.6, the setting of each parameter is listed in Table 4-3.
Table 4-3. Loop Filter Parameter Settings
LOOP FILTER TYPE
Ct
Rt
R2
C2
CIRCUIT
CONSTRUCTION
Lag-lead filter
Figure 2-16
1.6kO
360
1ILF
0.1 !LF
Active filter
1.6kO
360
Figure 2-17
1ILF
0.11LF
NOTE: The numencal values In Table 4-3 are the capacitance and resistance closest to the calculated values.
4.3.3 Passive Lag-Lead Filter Used as a Loop Filter
The evaluation results of using a lag-lead filter as the loop filter are illustrated in Figure 4-3 and Figure~. Figure 4-3
shows the individual waveforms as observed from an oscilloscope. Figure 4-4 shows the output signal measured by a
spectrum analyzer.
FIN-A Signal
FIN·B Signal
VCO OUT Signal
Figure 4-3. Waveforms Using Passive Lag-Lead Filter
(100 ns/dlv on horizontal axis)
Flgure~.
Spectrum of the veo Output Signal When Using a Passive Lag-Lead Filter
(100 kHz/dlv on horizontal axis)
4.3.4 Active Filter Used as a Loop Filter
The evaluation results of using an active filter as the loop filter are illustrated in Figure 4-5 and Figure 4-6. Figure 4-5
shows the individual waveforms as observed from an oscilloscope. Figure 4-6 shows the output signal measured by a
.
spectrum analyzer.
8-170
FIN-B Signal
FIN-A Signal
veo OUT Signal
Figure 4-5 Waveforms Using Active Filter
(100 ns/dlv on horizontal axis)
Figure 4-6. Spectrum of the VCO Output Signal When Using an Active Filter
(100 kHzldlv on horizontal axis)
4.4 Evaluation Results (Phase Reference Frequency = 4 fscl91 0,
Output Frequency = 4 fsc)
In this evaluation of number 2 in Table 4-1, fsc/910 (15.7 kHz) is used as the phase reference frequency to generate a
4 fsc (14.31818 MHz) output frequency. The details ,and results for the cases of using a lag-lead filter and an active filter
as the loop filter are described in the following sections.
4.4.1 Programmable Counter and Prescaler F!"8quency Divis/on Ratio Settings
Based on the evaluation block diagram of Figure 4-1, the frequency division ratio settings for the programmable counter
and prescaler are listed in Table 4-4.
Table 4-4. Frequency Division Ratio Settings
FREQUENCY DIVISION RATIO
Frequency divide value
4.4.2 Loop Filter Settings
Following the loop filter design procedures of Sections 2.5 and 2.6, the setting of each parameter is listed in Table 4-5.
8-171
Table 4-5. Loop Filter Parameter Settings
C2
CIRCUIT
CONSTRUCTION
5600
0.1 j1F
Figure 2-16
6200
0.111F
Figure 2-17
C1
R1
R2
Lag-lead filter
111F
2.41<0
Active filter
1j1F
31<0
LOOP FILTER
NOTE: Numerical values in Table 4-5 are the capacitan~ and resistance closest to the calculated values.
4.4.3 Passive Lag-Lead Filter Used as a Loop Filter
Using lag-lead filter as the loop filter, the evaluation results are illustrated in Figure 4---7 and Figure 4-8. Figure 4---7
shows the individual waveforms as observed from an oscilloscope. Figure 4---8 shows the output signal measured by a
spectrum analyzer.
FIN-A Signal
FIN·B Signal
VCO OUT Signal
Figure 4-7. Waveforms Using Passive Lag-Lead Filter
(100 nsJdlv on horizontal axis)
Figure 4-8. Spectrum of the veo Output Signal When Using a Passive Lag-Lead Filter
(100 kHzldiv on horizontal axis)
4.4.4 Active Filter Used as a Loop Filter
Using an active filter as the loop filter, the evaluation results are illustrated in Figure 4---9 and Figure 4---10. Figure 4---9
shows the individual waveforms as observed from an oscilloscope. Figure 4---10 shows the output sigruiI measured by
a spectrum analyzer.
8-172
FIN·B Signal
FIN·A Signal
VCO OUT Signal
Figure 4-9. Waveforms Using Active Filter
(100 nsJdiv on horizontal axis)
Figure 4-10. Spectrum of the VCO Output Signal When Using an Active Filter
(100 kHzldiv on horizontal axis)
4.5 Evaluation Results (Phase Reference Frequency
=fsc/910, Output Frequency =8 fsc)
In this evaluation of number 1 in Table 4-1, fsc (3.579545 kHz) is used as the phase reference frequency to generate
a 8 fsc (2 x 14.31818 MHz) output frequency. The details and results for the cases of using a lag-lead filter and an active
filter as the loop filter are described in the following sections.
4.5.1 Programmable Counter and Prescaler Frequency Division Ratio Settings
Based on the evaluation block diagram of Figure 4-1, the frequency division settings for programmable counters and
prescaler are listed in Table 4-6.
Table 4-6. FreCJuency Division Ratio Settings
FREQUENCY DIVIDE RATIO
Frequency dividing value
8-173
4.5.2 Loop Filter Settings
Following the loop filter design procedures of Sections 2.5 and 2.6, the setting of each parameter is listed in Table 4-7.
,Table 4-7. Loop Filter Parameter Settings
LOOP FILTER
C1
R1
R2
C2
CIRCUIT
CONSTRUCTION
Lag-lead filter
Figure 2-16
2.41<0
5600
0.11J.1'
11J.1'
Figure 2-17
Active Filter
31<0
6200
0.11J.1'
1IJ.F
NOTE: Numerical values in Table 4-6 are the capacitance and resistance closest to the calculated values.
4.5.3 Passive Lag-Lead Filter Used as a Loop Filter
The evaluation results of using a lag-lead filter as the loop filter are illustrated in Figure 4-11 and Figure 4-12. Figure
4-11 shows the individual 'wavefonns as observed from an oscilloscope. Figure 4-12 shows the output signal measured
by a spectrum analyzer.
FIN-S Signal
FIN-A Signal
VCO OUT Signal
Figure 4-11. Waveforms Using Passive Lag-Lead Filter
(100 nsldiv on horizontal axis)
Figure 4-12. Spectrum of the veo Output Signal When Using a Passive Lag-Lead Filter
(100 kHzJdlv on horizontal axis)
4.5.4 Active Filter Used as a Loop Filter
The evaluation results of using an active fllter as the loop filter are illustrated in Figure 4-13 and Figure 4-14. Figure
4-13 shows the individual wavefonns as observed from an oscilloscope. Figure 4-14 shows the output signal measured
by a spectrum analyzer.
8-174
FIN-B Signal
FIN-A Signal
veo OUT Signal
Figure 4-13. Waveforms Using an Active Filter
(100 ns/dlv on horizontal axis)
Figure 4-14. Spectrum of the veo Output Signal When Using an Active Filter
(100 kHz/div on horizontal axis)
4.6 Summary
The evaluation results shown were with the practical resistance and practical capacitance values closest to the calculated
values used for the loop filter. The evaluations were carried out with a lLC2932IPW placed in the IC socket on an
evaluation board with power supplies, and the BIAS terminal was bypassed directly on the bottom of the socket.
Better results can be achieved however by placing the lLC2932IPW directly on the evaluation board.
4.7 Examples of a PLL Application
The following sections contain PLL application examples.
4.7.1 Generating a 4 fsc NTSe Signal from a NTSe Signal
A NTSC signal horizontal synchronization frequency (fH) is multiplied by 910 to generate a 4 fsc NTSC signal. Figure
4-15 shows a block diagram of the PLL.
8-175
r-----~----------~
Horizontal Synchronization
Frequency =fH (NTSC)
I
I
I
r--:----,
I
I
I I.
veo
(Voltage
Controlled
Oscillator)
I
I
hl....- .
4 fac
(NTSC)
.TLC2932IPW
Programmable
Counter
(Frequency Divide
Ratio: 910)
Figure 4-15. Generating a 4 fsc (NTSC) Signal by Multiplying the Horizontal Synchronization
Frequency,
4.7.2 Generating a 4 fsc PAL Signal from a PAL Signal
A phase alteration line (PAL) signal horizontal synchronization frequency (fH) is multiplied by 910 to generate a 4 fsc
PAL signal. Figure 4-16 shows a block diagram of the PLL.
veo
Horizontal Synchronization
Frequency fH (PAL)
(Voltage
4 fsc
COntrol.led t-ii--4.-. (PAL)
OSCillator)
=
TLC2932IPW
Programmeble
COunter
(Frequency Divide
Ratio: 1135)
Programmable
COunter
(Frequency Divide
Ratio: 625)
Figure 4-16. Generating Ii 4 fsc (PAL) Signal by Multiplying the Horizontal Synchronization
.
Frequency
.
8-176
4.7.3 Generating a 13.5 MHz Output from a NTSC or PAL Signal
Figure 4-17 shows the derivative of a 4 fsc signal from a PAL or NTSC horzontial synchronization frequency.
VCO
(Voltage
Controlled
Oscillator)
Horizontal Synchronization
Frequency fH (NTSC or PAL)
=
13.5 MHz
TLC2932IPW
Programmable Counter
Counter Frequency
Divide
Ratio: 2
NTSC (Frequency Divide
Ratio: 429)
PAL (Frequency Divide
Ratio: 432)
Figure 4-17. Multiplying the Horizontal Synchronization Frequency of a NTSC Signal or \
PAL Signal to Generate a 13.5 MHz Output
8-177
8-178
Understanding Data Converters
.1ExAs
INSTRUMENTS
8-179 .
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or
to discontinue any semiconductor product or service without notice, and
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8-180
Contents
Section
Title
Page
1 INTRODUCTION ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 8-183
2 THE IDEAL TRANSFER FUNCTION •••••••••••••••••••••••••••••••••••••••••••••••••••• 8-183
2.1 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-183
2.2 Digital-to-Analog Converter (DAC) ...................................... " .......... 8-185
3 SOURCES OF STATIC ERROR •••••••••••••••••••••••••••••••••••••••••••••••••••••••••
3.1 Offset Error .....................................................................
3.2 GainError ......................................................................
3.3 Differential Nonlinearity (DNL) Error ................................................
3.4 Integral Nonlinearity (INL) Error ....................................................
3.5 Absolute Accuracy (Total) Error .....................................................
8-186
8-186
8-187
8-188
8-189
8-190
4 APERTURE ERROR •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 8-191
5 QUANTIZATION EFFECTS •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 8-192
6 IDEAL SAMPLING ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 8-194
7 REAL SAMPLING •••••••••••••••••••••••••••••••••••••••••••••••••,••••••••••••••••••• 8-195
8 ALIASING EFFECTS AND CONSIDERATIONS ••••••••••••••••••••••••••••••••••••••••••
8.1 Choice of Filter ..................................................................
8.2 'JYpesofFilter ...................................................................
8.2.1 Butterworth Filter ..........................................................
8.2.2 Chebyshev Filter ...........•...............................................
8.2.3 Inverse Chebyshev Filter ....•...............................................
8.2.4 CauerFilter ...............•.......................•.......................
8.2.5 Bessel-ThomsonFilter ...•..•..•..•.........................................
8.3 1LC04 Anti-Aliasing Butterworth Filter ..............................................
8-196
8-196
8-196
8-197
8-197
8-197
8-197
8-197
8-198
8-181
List of Illustrations
Figure
I.
2.
3.
4.
5.
6.
7.
8.
9.
10.
II.
Title
Page
The Ideal Transfer Function (ADC) ••...•....•....•.....•............................. 8-184
The Ideal Transfer Function (DAC) •........•.....•............•...................... 8-185
Offset Error ...................................................................... 8-186
Gairi Error .....•..•...........•.........•....
o'. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ••
8-187
Differential Nonlinearity (DNL) ...................................................... 8-188
Integral Nonlinearity (INL) Error ..•...........................•...................... 8-189
Absolute Accuracy (Total) Error ...................................................... 8-190
Aperture Error . • . . • • . • . . . . . . . • • • • . . . . . • . . . . . . . • . . . . . . . . . . . • • . . . • . . . . . . . • . . . . . . . . .. 8-191
Quantization Effects ......................................•.•...................... 8-192
Ideal Sampling ..................................................................... 8-194
Real Sampling .....................•.•.•......•...•............................... 8-195
12.
Aliasing Effects and Considerations .....•...................................•......... 8-196
13.
TLC04 Anti-aliasing Butterworth Filter .•..........•... . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. 8-198
8-182
1 INTRODUCTION
This application report discusses the way the specifications for a data converter are defined on a manufacturers data sheet
and considers some of the aspects of designing with data conversion products. It covers the sources of error that change
the characteristics of the device from an ideal function to reality.
2 THE IDEAL TRANSFER FUNCTION
The theoretical ideal transfer function for an ADC is a straight line, however, the practical ideal transfer function is a
uniform staircase characteristic shown in Figure 1. The DAC theoretical ideal transfer function would also be a straight
line with an infmite number of steps but practically it IS a server of points that fallon the ideal straight line as shown
in Figure 2.
2.1 Analog-to-Digital Converter (ADC)
An ideal ADC uniquely represents all analog inputs within a certain range by a limited number of digital output codes.
The diagram in Figure 1 shows that each digital code represents a fraction of the total analog input range. Since the analog
scale is continuous, w:bile the digital codes are discrete, there is a quantization process that introduces an error. As the
number of discrete codes increases, the corresponding step width gets smaller and the transfer function approaches an
ideal straight line. The steps are designed to have transitions such that the midpoint of each step corresponds to the point
on this ideal line.
The width of one step is defined as 1 LSB (one least significant bit) and this is often used as the reference unit for other
quantities in the specification. It is also a measure of the resolution of the converter since it defmes the number of
divisions or units of the full analog range. Hence, 112 LSB represents an analog quantity equal to one half of the analog
resolution.
The resolution of an ADC is usually expressed as the number of bits in its digital output code. For example, an ADC
with an n-bit resolution has 2n possible digital codes which define 2n step levels. However, since the first (zero) step
and the last step are only one half of a full width, the full-scale range (FSR) is divided into 2n - 1 step widths.
Hence
1 LSB = FSR/(2n - 1) for an n-bit converter
8-183
CONVERSION CODE
RANGE OF
ANALOG
INPUT
VALUES
DIGITAL
OUTPUT
CODE
4.5·5.5
0 ... 101
3.5' 4.5
0 ... 100
;--
( 2.5' 3.5
'----
----
0 ... 011
Digital Output
Code
0 ... 101
Step 0 ... 100
)
-----'
1.5·2.5
0 ... 010
0.5 '1.5
0 ... 001
0'0.5
0 ... 000
Ideal Straight Line
/~-( 0 ... 011
'---0 ... 010
0 ... 001
I'----+--+---+--+----t--.
0 ... 000
023
4
Analog Input
Value
5
Mldstep Value
of 0 ... 011
Quantization
Error
+1/2
LSB
. .--+-4t-+-.....H--4It-+....---1f--. .--+
o
-1/2
LSB
Elements of Transfer Diagram for an Ideal Linear ADC
Figure 1. The Ideal Transfer Function (ADe)
8-184
Analog Input
Value
2.2 Digltal-to-Analog Converter (DAC)
A DAC represents a limited number of discrete digital input codes by a corresponding number of discrete analog output
values. Therefore, the transfer function of a DAC is a series of discrete points as shown in Figure 2. For a DAC, 1 LSB
corresponds to the height of a step between successive analog outputs, with the value defined in the same way as for
the ADC. A DAC can be thought of as a digitally controlled potentiometer whose output is a fraction of the full scale
analog voltage determined by the digital input code.
Analog Output
Value
5
4
3
2
o.----;I---+---i--+-..;-....L..+-----1--..
9... 01~ 0 ... 100 0 ... 101
Digital Input Code
0 ... 000 0 ... 001 0 ... 010
l. .
CONVERSION CODE
Digital Input Code
Analog Output Value
0 ... 000
0 ... 001
0 ... 010
0
1
2
....J)
r
I
0 ... 011
Step
,
I
IL_.!_J
0 ... 100
0 ... 101
4
5
Elements of Transfer Diagram for an Ideal Linear DAC
Figure 2. The Ideal Transfer Function (DAC)
8-185
3 SOURCES OF STATIC ERROR
Static errors, that is those errors that affect the accuracy of the converter when it is'converting static (de) signals, can
be completely described by just four terms. These are offset error, gain error, integral nonlinearity and differential
nonlinearity. Each can be expressed in LSB units or sometimes as a percentage of the FSR. For example, an error of 112
LSB for an 8-bit converter corresponds to 0.2% FSR.
3.1 Offset Error
The offset error as shown in Figure 3 is defmed as the difference between the nominal and actual offset points. For an
ADC, the offset point is the midstep value when the digital output is zero, and for a DAC it is the step value when the
digital input is zero. This error affects all codes by the same amount and can usually be compensated for by a trimming
process. If trimming is not possible, this error is referred to as the zero-scale error.
/
/
/
/
/
r-r-r-
011
1 /
II)
"U
..'"
1
1
1
1
J/
<3
/1
Ideal~_r-""'~.J
.& 010
'"
!
g
0
1//
Diagram
//1
001
i~
1 "-- Actual
I
Diagram
i
r-+-.J
1//
Offsat Error
(+11/4 LSB)
14--+1--- +1/2 LSB
/V
/1
000 ....-1'----+___---+----1---....
Nominal
Offset Point
I
[ I Anal~
Actual
Offset Point
Offset Error
(+11/4 LSB)
Output
v~ue
Nominal
Offset Point
Digital Input Code
.1
(b) DAC
(a)ADC
Offset error of a Linear SoBIt Natural Binary Code Converter
(SpecHIed at Stap 000)
Figure 3. Offset Error
8-186
3.2 Gain Error
The gain error shown in Figure 4 is defined as the difference between the nominal and actual gain points on the transfer
function after the offset error has been corrected to zero. For an ADC, the gain point is the midstep value when the digital
output is full scale, and for a DAC it is the step value when the digital input is full scale. This error represents a difference
in the slope of the actual and ideal transfer functions and as such corresponds to the same percentage error in each step.
This error can also usually be adjusted to zero by trimming.
Nominal Gain
Point
---------...,..--+-r-J
111
~
110
6
;g
101
/.(
~'rj-----t--------~------~
o
5
6
Analog Input Value (LSB)
//
Gain Error
(-11/4 LSB)
/
/1
I
/
I
I
/ ""71
""
Idaal Diagram"""'\.._ / /
I
,,"
""".
/
/
.",,""
/ ..""
Actual Gain
Point
/.'l/
/.'/
~{I'
4
T // I
000
-------- ------.~
7
I / I
(1/2 LSB) --1~'---'1
;/ I
/ I
I
Actual Diagram I
\
I /'1+-+2--1
r--_3r~..,--II....,L -.J
I /
1/
)/
Gain Error
/1
(-3/4 LSB)
I
/ I
I _,/ _.J
-""""I.1-/ ~I/
L Idaal Diagram
1
g
Nominal Gain pOlnt~_
/
O~'jl
000
100
101
110
I
I
I
I
I
I
I
I
111
Digital Input Code
(a) ADC
(b) DAC
Gain Error of a Llnaar 3-Blt Natural Binary Code Convertar
(Specified at Step 111), Attar Correction of the Offset Error
Figure 4. Gain Error
8-187
3.3 Differential Ncmlinearity (DNL) Error
The differential ilonlinearityerror shown in Figure 5 (sometimes seen as simply differential linearity) is the difference
between an actual step width (for an ADC) or step height (for a DAC) and the ideal value of 1 LSB. Therefore if the
step width or height is exactly 1 LSB, then the differential nonlinearity error is zero. If the DNL exceeds 1 LSB, there
is a possibility that the converter can become nonmonotonic. This means that the magnitude of the output gets smaller
for an increase in the magnitude of the input. In an ADC there is also a possibility that there can be missing codes i.e.,
one or more of the possible 2n binary codes are never output.
0 ... 110
0 ••• 101
011
I
"0:1
0 ... 100
i
0 ... 011
8
::I
I
..-_...J1
!.S!!
~
0 ••• 010
c
!
~
~
0 ••• 001
I-
.
i
-1-\1J.-
11 L S B U
0
Dlfferentlel
Linearity Error (1/2 LSB)
Differential Linearity
Error (-1/2 LSB)
0 ••• 000
0
2
4
3
Analog Input Value (LSB)
5
(a)ADC
6
iii
::!
011
.:
5
4
:l:
"S 3
So
8CII
.2
2
1\1
C
C(
Digital Input Code
(b)DAC
Differential Linearity Error of a Linear ADC or DAC
Figure 5. Differential Nonlinearity (DNL)
8-188
3.4 Integral Nonlinearity (INL) Error
The integral nonlinearity error shown in Figure 6 (sometimes seen as simply linearity error) is the deviation of the values
on the actual transfer function from a straight line. This straight line can be either a best straight line which is drawn so
as to minimize these deviations or it can be a line drawn between the end points of the transfer function once the gain
and offset errors have been nullified. The second method is called end-point linearity and is the usual definition adopted
since it can be verified more directly.
I
For an ADC the deviations are measured at the transitions from one step to the next, and for the DAC they are measured
at each step. The name integral nonlinearity derives from the fact that the summation of the differential nonlinearities
from the bottom up to a particular step, determines the value of the integral nonlinearity at that step.
--------------~
111
---------------~
7
,(?
/r'
010
G)
;3
:;
t
101
Actual
Transition
100
o
011
c
010
!!lI
Ideal
Transition
~
6
"/
.//
I)
-r
~~
~ J)/
~~
"P..
/~
At Transition
/ fI-a /
011/100
dj~ ~ (-1/2 LSB)
1
r'
End-poln~
,///
At Transition
)
001/010 (-1/4 LSB)
000 . .
o
4
2
3
5
Analog Input Value (LSB)
/f
Error
"
~
~
,.j..j..+--+--+---+---+---+---I
001
//?
/fi//
6
7
~t--r.-
At Step
011 (1/2 LSB)
V
End-poln~
Error
At step"
IV
001 (1/4 LSB)
o __-+--+--r--r---Ir-~---I
000
001
010 011
100 101
Dlgltellnput Code
(a)ADC
110
111
(b) DAC
End·Polnt Linearity Error of a Linear 3-Blt Natural Blnary·Coded ADC or DAC
(Offset Error and Gain Error ara Adjusted to the Value Zero)
Figure 6. Integral Nonlinearity (INL) Error
8-189
3.5 Absolute Accuracy (Total) Error
The absolute accuracy or total error of an ADC as shown in Figure 7 is the maximum value of the difference between
an analog value and the ideal midstep value. It includes offset, gain, and integral linearity errors and also the quantization
error in the case of an ADC.
r
/
I /
0 ... 111
~/
0 ... 110
iii 6
I //
~ 0 ... 101
I
~
•
r.0
:::I
I / /
r;ItI
j§ 0 ... 011
.r
~
g
c 0 ... 010
14
3
Ic
Total Error
At Step 0 ... 101
(-11/4 LSB)
/
/JI'
2
/~
~
/
0 ... 000
/
/
/
0
o
2
4
3
5
Analog Input Value (LSB)
(e)ADC
6
7
Digital Input Code
(b)DAC
Abaolute Accuracy or Total Error of a Linear ADC or DAC
Figure 7. Absolute Accuracy (Total) Error
8-190
/
Total Error
At Step 0 ... 011
(11/4 LSB)
,1/
//./
d T o t a l Error
At Step
/
0 ... 001 (1/2 LSB)
0 ... 001
//
:::I
0
oC
, ;£:{
//
5
J!
~.
0 ... 100
./
.
~/"
//
" /.
7
4 APERTURE ERROR
Sampling Pulse
v = Voaln27lft
dV
Cit
= 27IfVocoa27lft
dVI
Cit
max =2n fVO
dV
t
2VO
2n+1
EA=TA -d =1/2LSB=--
2VO
- - 1 =2ltfVOTA ~
2n+
Figure 8. Aperture Error
Aperture error is caused by the uncertainty in the time at which the samplelhold goes from sample mode to hold mode
as shown in Figure 8. This variation is caused by noise on the clock or the input signal. The effect of the aperture error
is to set another limitation on the maximum frequency of the input sine wave because it defines the maximum slew rate
of that signal. For a sine wave input as shown, the value of the input V is defIned as:
V = V 0 sin2nft
The maximum slew rate occurs at the zero crossing point and is given by:
~Ylmax =
2nfVO
If the aperture error is not to affect the accuracy of the converter, it must be less than 112 LSB at the point of maximum
slew rate. For an n bit converter therefore:
2V
EA = TA dV = 1/2 LSB =--..Q
dt
2n+ 1
Substituting into this gives
2 Vo
- - = 2nfVOTA
2n + 1
So that the maximum frequency is given by
8-191
5 QUANTIZATION EFFECTS
The real world analog input to an ADC is a continuous signal with an infinite number of possible states, whereas the
digital output is by its nature a discrete function with a number of different states determined by the resolution of the
device. It follows from this therefore, that in converting from one form to the other, certain parts of the analog signal
that were represented by a different voltage on the input are represented by the same digital code at the output. Some
information has been lost and distortion has been introduced into the signal. This is quantization noise.
For the ideal staircase transfer function of an ADC, the error between the actuaI input and its digital form has a uniform
probability density function if the input signal is assumed to be random. It can vary in the range ±1I2 LSB or ±ql2 where
q is the width of one step as shown in Figure 9.
Error at the Jth step
Digital
Code
EJ
=(VJ -VI)
The mean square error over the step
f
J Ef
+q/2
E = ~1
-q/2
dE = q 2
12
Assuming equal steps, the total error Is
N2 =q2/12 (Mean square quantization noise)
For an Input sine wave F(t)
powar
Jo
=A slnrot, the signal
21t
F2(t)
= i.rr.
A2sln2rotdrot:
~2
andq = 2A=~
2n
+112
QuantlzaUon
Error
LSB
-+.....f---.
Error E ir-...
2n- 1
SNR = 10 Log (F22) = 10 Log ( 2;"2/2 )
n
A /3 x 2n
SNR = 6.02n
+ 1.76 dB
-1/2
LSB
Figure 9. Quantization Effects
Where
peE)
=
! for (-~
:S
E :S
+~)
Otherwise
peE) = 0
The average noise power (mean square) of the error over a step is given by
q/2
N2
f
=!
E2dE
-q/2
which gives
2
q2
N=12
8-192
The total mean square error, N2, over the whole conversion area is the sum of each quantization levels mean square
multiplied by its associated probability. Assuming the converter is ideal, the width of each code step is identical and
therefore has an equal probability. Hence for the ideal case
N2
2
=.9...
12
Considering a sine wave input F(t) of amplitude A so that
F(t) = Asinoot
which has a mean square value of F2(t), where
f
23t
p2(t)
= ire
A2sin2(oot)dt
o
which is the signal power. Therefore the signal to noise ratio SNR is given by
SNR(dB) =
1O~ (",2)/ (i~) ]
[
But
q
= I .LSB = 2A
=~
2 n 2n-1
Substituting for q gives
SNR(dB)
= 10Log
[(~2)/(3 :~2n)] = 10 Log (3 X222n)
=
+ 1.76dB
6.02n
This gives the ideal value for an n bit converter and shows that each extra I bit of resolution provides approximately
6 dB improvement in the SNR.
In practice, the errors mentioned in section 3 introduce nonlinearities that lead to a reduction of this value. The limit of
a112 LSB differential linearity error is a missing code condition which is equivalent to a reduction of I bit of resolution
and hence a reduction of 6 dB in the SNR. This then gives a worst case value of SNR for an n-bit converter with 112 LSB
linearity error.
SNR (worst case)
= 6.02n + 1.76 -
6
= 6.02n -
4.24 dB
Hence we have established the boundary conditions for the choice of the resolution of the converter based upon a desired
level of SNR.
8-193
6 IDEAL SAMPLING
In converting a continuous time signal into a discrete digital representation, the process of sampling is a fundamental
requirement. In an ideal case, sampling takes the form of a pulse train of impulses which are infmitesimally narrow yet
have unit area. The reciprocal of the time between each impulse is called the sampling rate. The input signal is also
idealized by being truly bandlimited, containing no components in its spectrum above a certain value (see Figure 10).
Input Waveform
Sampling Function
~~
(1) (1) (1) (1)
=
Unit
Impulses
X
t1t2t3t4t
Input Spectra
J(,
It)
Frequency Domain
f
1)
""'lu
(1)
fs = 11T
t
J(,
Sampling Spectra
eo'WI"'~
}' .
NYQUIST'S THEOREM: fs -f1 > f1
t1 t2 t3 t4
~T
Fourier Analysis
f1
g(t)
h(t)
Multiplication
In Time Domain
J('
Sampled Output
2fs
Sampled Spectra
=
f
=* fs > 2f1
Figure 10. Ideal Sampling
The ideal sampling condition shown is represented in both the frequency and time domains. The effect of sampling in
the time domain is to produce an amplitude modulated train of impulses representing the value of the input signal at the
instant of sampling. In the frequency domain, the spectrum of the pulse train is a series of discrete frequencies at
multiples of the sampling rate. Sampling convolves the spectra of the input signal with that of the pulse train to produce
the combined spectrum shown, with double sidebands around each discrete frequency which are produced by the
amplitude modulation. In effect some of the higher frequencies are folded back so that they produce interference at lower
frequencies. This interference causes distortion which is called aliasing.
If the input signal is bandlimited to a frequency f1 and is sampled at frequency fs' as shown in the figure, overlap (and
hence aliasing) does not occur if
f1 < f s,,- f1
i.e., 2f1 < fs
Therefore if sampling is performed at a frequency at least twice as great as the maximum frequency of the input signal,
no aliasing occurs and all of the signal information can be extracted. This is Nyquist's Sampling Theorem, and it provides
the basic criteria for the selection of the sampling rate required by the converter to process an input signal of a given
bandwidth.
8-194
7 REAL SAMPLING
The concept of an impulse is a useful one to simplify the analysis of sampling. However, it is a theoretical ideal which
can be approached but never reached in practice. Instead the real signal" is a series of pulses with the period equalling
the reciprocal of the sampling frequency. The result of sampling with this pulse train is a series of amplitude modulated
pulses (see Figure 11).
Input Waveform
~b:
r--------,
I
Square Wave ~ SI: x
FmL
f1
f(l)
~T
Ji
Fourier Analysis
Input Spectra
Ji
Sampling Spectra
(1)
Output Spectra
Period T
J-VL
FmJK
-tf2 +tf2 J~
-1/'f 0 1/'f
(1)
Envelope has the form
E=~ (~'t)
=
f
Input signals are not truly
band limited
f(s) ~ 2f1
I
r---------,
x
t
Ji
Sampled Output
Sampling Function
T
f1
Sampling cannot ba done with
impulses so, amplitude of
signal is modulated by
Sinx
-x- envelope
7th
L. _ _ _ _ _ _ _ _ ..I
fs
Because of input spectra and
sampling there is aliasing and
distortion
Figure 11. Real Sampling
Examining the spectrum of the square wave pulse train shows a series of discrete frequencies, as with the impulse train,
but the amplitude of these frequencies is modified by an envelope which is defmed by (sin x)/x [sometimes written
sinc(x)] where x in this case is 'ltfs. For a square wave of amplitude A, the envelope of the spectrum is defined as
Envelope = A(t)[Sin(nfs't)] /1tfs't
The error resulting from this can be controlled with a filter which compensates for the sinc envelope. This can be
implemented as a digital filter, in a DSP, or using conventional analog techniques.
8-195
8 ALIASING EFFECTS AND CONSIDERATIONS
No signal is truly deterministic and therefore in practice has inftnite bandwidth. However, the energy of higher frequency
components becomes increasingly smaller so that at a certain value it can be considered to be irrelevant. This value is
a choice that must be made by the system designer.
As shown, the amount of aliasing is affected by the sampling frequency and by the relevant bandwidth of the input signal,
ftltered as required. The factor that determines how much aliasing can be tolerated is ultimately the resolution of the
system. If the system has low resolution, then the noise floor is already relatively high and aliasing does not have a
signiftcant effect. However, with a high resolution system, aliasing can increase the noise floor considerably and
therefore needs to be controlled more completely.
One way to prevent aliasing is to increase the sampling rate, as shown. However, the frequency is limited by the type
of converter used and also by the maximum clock rate of the digital processor receiving and transmitting the data.
Therefore, to reduce the effects of aliasing to within acceptable levels, analog ftlters must be used to alter the input signal
spectrum (see Figure 12).
-8
!
s
.c
Ci.
E
.-....
c(
iii
C
c
~
CL
Signal Allased
Into Frequencies
of Interest
-;
CL
.5 QN
+ - flnt - + fs12
.5
fs
CD
+-flnt-+
fs
+-flnt-+
fs
31
"g
:I
."
:t:
.-....
Ci.
E
c(
iii
c
Anti-aliasing Filter
II)
Resultant
.~
CL
iii
-;
01
1i)
-;
A-
QN
.c
A-
iii
c
~
-;
CL
.5
.5
+ - flnt - + fs12
fs
Figure 12. Aliasing Effects and Considerations
8.1 Choice of Filter
As shown with sampling, there is an ideal solution to the choice of a ftlter and a practical realization that compromises
must be made. The ideal ftlter is a so-called brickwall filter which introduces no attenuation in the passband, and then
cuts down instantly to infmite attenuation in the stopband. In practice, this is approximated by a ftlter that introduces
some attenuation in the passband, has a fmite rolloff, and passes some frequencies in the stopband. It can also introduce
phase distortion as well as amplitude distortion. The choice of the ftlter order and type must be decided upon so as to
best meet the requirements of the system.
8.2 Types of Filter
The basic types of ftlters available to the designer are briefly presented for comparison purposes. This is not intended
to be a full analysis of the subject; therefore, other texts should be referenced for more details.
8-196
8.2.1 Butterworth Filter
A Butterworth (maximally flat) filter is the most commonly used general purpose filter. It has a monotonic passband
with the attenuation increasing up to its 3-dB point which is known as the natural frequency. This frequency is the same
regardless of the order of the filter. However, by increasing the order of the filter, the roll-off in the passband moves closer
to its natural frequency and the roll-off in the transition region between the natural frequency and the stopband becomes
sharper.
8.2.2 Chebyshev Filter
The Chebyshev equal ripple filter distributes the roll-off across the whole passband. It introduces more ripple in the
passband but provides a sharper roll-off in the transition region. This type of filter has poorer transient and step responses
due to its higher Q values in the stages of the filter.
8.2.3 Inverse Chebyshev Filter
Both the Butterworth and Chebyshev filters are monotonic in the transition region and stopband. Since ripple is allowed
in the stopband, it is possible to make the roll-off sharper. This is the principle of the Inverse Chebyshev, based on the
reciprocal of the angular frequency in the Chebyshev filter response. This filter is monotonic in the passband and can
be flatter than the Butterworth filter while providing a greater initial roll-off than the Chebyshev filter.
8.2.4 Cauer Filter
The Cauer or (Elliptic) filter is nonmonotonic in both the pass and stop bands, but provides the greatest roll-off in any
of the standard filter configuratigns.
8.2.5 Bessel-Thomson Filter
All of the types mentioned above introduce nonlinearities into the phase relationship of the component frequencies of
the input spectrum. This can be a problem in some applications when the signal is reconstructed. The Bessel-Thomson
or linear delay filter is designed to introduce no phase distortion but this is achieved at the expense of a poorer amplitude
response.
In general, the performance of all of these types can be improved by increasing the number of stages, i.e., the order of
the filter. The penalty for this of course is the increased cost of components and board space required. For this reason,
an integrated solution using switched capacitor filter building blocks which provide comparable performance with a
discrete solution over a range of frequencies from about 1 kHz to 100kHz might be appropriate. They also provide the
designer with a compact and cost effective solution.
8-197
8.3 TLC04 Anti-Aliasing Butterworth Filter
.The TLC04 fourth order Butterworth filter features include the following:
• Low clock to cutoff frequency error ... 0.8%
• Cutoff depends only on stability of external clock
• Cutoff range of 0.1 Hz to 30 kHz
• 5-V to 12-V operation
• Self clocking or both TIL and COS compatible
As detailed previously the Butterworth filter generally provides the best compromise in filter configurations and is by
far the easiest to design. The Butterworth filter's characteristic is based on a circle which means that when designing
filters, all stages to the filter have the same natural frequency enabling simpler filter design. Most modem designs which
use operational amplifiers are based on building the whole transfer function by a series of second order numerator and
denominator stages (a Biquad stage). The Butterworth design is simplified, when using these stages, because each stage
has the same natural frequency. This can easily be converted to a switched capacitor filter (SCF) which has very good
capacitor matching and accurately synthesized RC time constants.
The switched capacitor technique is demonstrated in Figure 13. Two clocks operating at the same frequency but in
complete antiphase, alternately connect the capacitor C2 to the input and the inverting input of an operational amplifier.
During CI> 1, charge Q flows onto the capacitor equal to VIC2' The switch is considered to be ideal so that there is no series
resistance and the capacitor charges instantaneously. During Cl>2, the switches change so that C2 is now connected to the
virtual earth at the operational amplifIer input. It discharges instantaneously delivering the stored charge Q.
VoC+--._-------------------.-7 VOC+
Filter In
Fourth Order
Butterworth
Low-Pass Filter
8
TLC04
TLC14
4
VOe-
VocSwitched Capacitor Equivalent to Integrator
1<1111 =1<1121
=FC~L
--o--"C
<
A-2
Appendix A
Analog Interface Peripherals and
Applications
til
Texas Instruments offers many products for total system solutions, including
memory options, data acquisition, and analog input/output devices. This
appendix describes a variety of devices that interface directly to the TMS320
DSPs in rapidly expanding applications.
Section
Page
A.1 Multimedia Applications ......................................... A-4
A.2 Telecommunications Applications ............................ A-7
A.3 Dedicated Speech Synthesis Applications . . . . . . . . . . . . . . . . . . .. A-12
A.4 Servo Control/Disk Drive Applications ....................... A-14
A.5 Modem Analog Front-End Applications ...................... A-15
A.6 Advanced Digital Electronics Applications for Consumers ...... A-17
A-3
Multimedia Applications
A.1
Multimedia Applications
Multimedia integrates different media through a centralized computer. These
media can be visual or audio and can be input to or output from the central
computer via a number of technologies. The technologies can be digital based
or analog based (such as audio or video tape recorders). The integration and
interaction of media enhances the transfer of information and can
accommodate both analysis of problems and synthesis of solutions.
Figure A-1. System Block Diagram
Figure A-1 shows both the central role of the multimedia computer and the
multimedia system's ability to integrate the various media to optimize
information flow and processing.
CD ROM
Video Input
Image Sensor
Microphone
,
Operator Input
........
-ll~
---.J l ---",
Multimedia·
Computer
---.I
~,
Music Input
(MIDI)
A.1.1
Modem
:::JJ
=ill
--y
.....
Video Monitor
Facsimile/Modem
,
Speakers
Slides and Printing
System Design Considerations
Multimedia systems can include various grades of audio and video quality. The
most popular video standard currently used (VGA) covers 640 x 480 pixels
with 1, 2, 4, and 8-bit memory-mapped color. Also, 24-bit true color is
supported, and 1024 x 768 (beyond VGA) resolution has emerged. There are
two grades of audio. The lower grade accommodates 11.25-kHz sampling for
8-bit monaural systems, while the higher grade accommodates 44.1-kHz
sampling fori 16-bit stereo.
Audio specifications include a musical instrument digital interface (MIDI) with
compression capability, which is based on keystroke encoding, and an
input/output port with a 3-disc voice synthesizer. In the media control area,
video disc, CD audio, and CD ROM player interfaces are included. Figure A-2
shows a multimedia subsystem.
A-4
Analog Interface Peripherals and Applications
Multimedia Applications
The TLC320AC01 wide-band analog interface circuit (AIC) is well suited for
multimedia applications because it features wide-band audio and up to 25-kHz
sampling rates. The TLC320AC01 is a complete analog-to-digital and
digital-to-analog interface system for the TMS320 DSPs. The nominal
bandwidths of the filters accommodate 11.4 kHz, and this bandwidth is
programmable. The application circuit shown in Figure A-2 handles both
speech encoding and modem communication functions, which are associated
with multimedia applications.
Figure A-2. Multimedia Speech Encoding and Modem Communication
VOCODER (Speech Analysis)
9600-bps Modem (V.32 bis)
r----------,
'i
(
I
TLC320AC01
TMS320
r----------,
I
TMS320
I TMS320
TLC320AC01
I r---~-.,
DAA
~I
I
L._______
HYB
Phone
Line
I
_.J
TMS320DSPI
TLC320AC01
Interface
Figure A-3 shows the interfacing ofthe TMS320C25 DSP to the TLC320AC01
AIC that constitutes the building blocks of the 9600-bps V.32 bis modem
shown in Figure A-2.
FigureA-3. TMS320C25 to TLC32047 Interface
TMS320C25
CUG:X
BitS
Receive
TIming
LSB
BitS Transmit
TIming
LSB
Telecommunications-Related Devices. Data sheets for the devices in
Table A-3 are contained in the 1993 Telecommunications Circuits Databook,
(literature number SCTD001). To request your copy, contact your nearest
Texas Instruments field sales office or call the Customer Response Center at
(800) 336-5236.
A-9
Tel8e'omfJIunications Applications
Table A-3. Telecom Devices
Device Number
Coding
Law
TCM29C23
TCM29C26
TCM320AC36
Aand JL
Aand JL
JL and Linear
TCM320AC~7
A and Linear
TCM320AC38
JL and Linear
A and Linear
Clock Rates
MHzt
CodeclFliter
1.544, 1.536, 2.048
1.544, 1.536, 2.048
2.048
2.048
2.048
1.536
Up to 4.096
Up to 4.096
Up to 4.096
Up to 4.096
Up to 4.096
Up to 4.096
TCM29C13
TCM29C14
Aand JL
TP3054/64
JL
1.544, 1.536, 2.048
8
TP3054/67
A
1.544, 1.536, 2.048
8
TLC32040/1
Linear
Linear
25kHz
Up to 19.2-kHz sampling
14
14
TLC32044/5
Linear
Up to 19.2-kHz sampling
14
TLC32046
TLC32047
Linear
Up to 25-kHz sampling
14
For high-dynamic linearity
For high-dynamic linearity
Linear
Up to 25-kHz sampling
14
For high-dynamic linearity
A and JL
TCM29C16
TCM29C17
A
TCM29C18
JL
JL
TCM29C19
JL
TCM320AC39
TLC320AC01/02
#of Bits
8
C.O. and PBX line cards
8
8
Includes 8th-bit signal
8
16-pin package
16-pin package
8
Low-cost DSP interface
8
Low-cost DSP interface
8
8
8 and 13
Extended frequency range
Low-power TCM29C23
Single voltage (+5) VBAP
8 and 13
8 and 13
8 and 13
Single voltage (+5) VBAP
Single voltage (+5) GSM
Single voltage (+5) GSM
National Semiconductor
second source
National Semiconductor
second source
5-volt-only analog interface
For high-dynamic linearity
Transient Suppressor
Transient suppressor for SUC-based line card
Transient suppressor for SUC-based line card
TCM1030
TCM1060
Comments
(30 A max)
(60 A max)
t Unless otherwise noted
Table A-4. Switched-Capacitor Filter ICs
Device
TLC2470
TLC2471
Function
Differential audio filter amplifier
TLC04/14
Low pass, Butterworth filter
Differential audio filter amplifier
Order
4
4
Roll-Off
5 kHz
3.5 kHz
Power Out
500mW
500mW
Power Down
Yes
Yes
4
CLK+50
CLK + 100
N/A
No
For further information on these telecommunications products, please call
(214) 997-3772.
A-10
Analog Interface Peripherals and Applications
Telecommunications Applications
Figure A-6. General Telecom Applications
~
~
Analog
Phones
I
Neighborhood
Concentrator
TCM5087 Tone
TCM5089 Encoder
TCM5092
TCM5094
TCM153x Ringer
~
I
Cell Base
Station
Cellular
Phone
TCM29C23 Combo
TMS320xx DSP
TGAP90x
TCM320AC3X VBAP Combo
TGAP901
Answering
~hl".
Central Office ...- - - - -..
Toll Office
TCM29C13 Combo
TP3054 Combo
TCM1 060/30 Transient Suppressors
TCM9050/51 HVLI/HCombo
DSP/Memory/Logic
DSP
Modem
Phones
TMS320xx DSP
TCM291 x Combo
Phones
TCM29Cxx Combo
Figure A-l. Generic Telecom Application
TLC320AC01
+
ADCand DAC
Fine Tune
Echo-Cancel
TMS320C25
:1
o
A
A
Telephone
Line
Echo Canceler
Transmitter
RS-232
I/F
Serial
I/O
Control
TMS320C25
Receiver
A-11
Dedicated Speech Synthesis Applications
A.3 Dedicated Speech Synthesis Applications
For dedicated speech synthesis applications, Texas Instruments offers a
family of dedicated speech synthesizer chips. This speech technology has
been used in a wide range of products including games, toys, burglar alarms,
fire alarms, automobiles, airplanes, answering machines, voice mail, industrial
control machines, office machines, advertisements, novelty items, exercise
machines, and learning aids.
Dedicated speech synthesis chips are a good alternative for low-cost
applications. The speech synthesis technology provided by the dedicated
chips is either LPC (linear-predictive coding) or CVSD (continuously variable
slope delta modulation). Table A-5 shows the characteristics of the TI voice
synthesizers.
Table A-5. Voice Synthesizers
TI Voice Synthesizers:
Device
Microprocessor
Synthesis
Method
I/O Pins
On-Chip
Memory (Bits)
External
Memory
Data Rate
(BIts/Sec)
TSP50C4x
8-bit
LPC-10
20/32
64K/128K
VROM
1200-2400
TSP50C1x
8-bit
LPC-12
10
64K/128K
VROM
1200-2400
TSP53C30
8-bit
LPC-10
20
N/A
Fromhost~
1200-2400
TSP50C20
8-bit
LPC-10
32
N/A
EPROM
1200-2400
TMS3477
NlA
CVSD
2
None
DRAM
16K-32K
In addition to the speech synthesizers, TI has low-cost memories that are ideal
for use with these chips. Texas Instruments can also be of assistance in
developing and processing the speech data that is used in these speech
synthesis systems. Table A-6 shows speech memory devices of different
capabilities. Additionally, audio filters are outlined in Table A-7.
Table A-6. Speech Memories
TSP60Cxx Family of Speech ROMs
Size
No. of Pins
Interface
For use with:
TSP60C18
TSP60C19
TSP60C20
TSP60C80
TSP60C81
256K
256K
256K
1M
1M
16
16
28
28
28
Parallel 4-bit
Serial
ParalleVserial 8-bit
Serial
Parallel 4-bit
TSP50C1x
TSP50C4x
TSP50C4x
TSP50C4x
TSP50C1x
Table A-7. Switched-Capacitor Filter ICs
Device
TLC2470
Function
Differential audio filter amplifier
Order
4
Roll-Off
5 kHz
Power Out
500mW
Power Down
Yes
TLC2471
Differential audio filter amplifier
4
3.5 kHz
500mW
Yes
TLC04/14
Low pass, Butterworth filter
4
CLK+50
CLK+ 100
N/A
No
A-12
Analog Interface Peripherals and Applications
Speech Synthesis Development Tools
Software:
EVM
Speech:
SAB
S085000
Code development tool
Speech audition board
PC-based speech analysis
system
System:
SEB
SEB60Cxx
System emulator board
System emulator boards for speech
memories
For further information on these speech synthesis products, please call TI Linear Applications at
(214) 997-3772.
r
A-13
Servo Control/Disk Drive Applications
A.4 Servo Control/Disk Drive Applications
Several years ago, most servo control systems used only analog circuitry.
However, the growth of digital signal processing has made digital control
theory a reality. Figure A-8 shows a block diagram of a generic digital control
system using a DSP, along with an ADC and DAC.
Figure A-B. Generic Servo Control Loop
TMS320-Based
Digital Controller
In a DSP-based control system, the control algorithm is implemented via
software. No component aging or temperature drift is associated with digital
control systems. Additionally, sophisticated algorithms can be implemented
and easily modified to upgrade system performance.
System Design Considerations. TMS320 DSPs have facilitated the
development of high-speed digital servo control for disk drive and industrial
control applications. Disk drives have increased storage capacity from 5
megabytes to over 1 gigabyte in the past decade, which equates to a 23,900
percent growth in capacity. To accommodate these increasingly higher
densities, the data on the servo platters, whether servo-positioning or actual
storage information, must be converted to digital electronic signals at
increasingly closer points in relation to the platter "pick-off' pOint. The ADC
must have increasingly higher conversion rates and greater resolution to
accommodate the increasing bandwidth requirements of higher storage
densities. In addition, the ADC conversion rates must increase to
accommodate the shorter data retrieval access time.
Table A-B. Control Related Devices
Function
ADC
~-
A-14
DAC
Device
Bits
Speed
TLC1550
TLC1551
TLC0820
TLC1225
TLC1543
TLC1549
TLV1543
TLV1549
TLC2543
TLC7524
TLC7628
10
10
8
13
10
10
10
10
12
8
8
3-5 lIS
TLC5602
8
30 MHz
3-5~
1.5 lIS
12 lIS
21 lIS
21 lIS
21 lIS
21 lIS
10 lIS
9MHz
9MHz
Channels
1
1
1
1 (Diff.)
11
1
11
1
11
1
(Dual)
Interface
Parallel
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Parallel
1
Parallel
Analog Interface Peripherals and Applications
Multimedia Applications
A.5 Modem Applications
High-speed modems (9,600 bps and above) require a great deal of analog
signal processing in addition to digital signal processing. Designing both
high-speed capabilities and slower fall-back modes poses significant
engineering challenges. TI offers a number of analog front-end (AFE) circuits
to support various high-speed modem standards.
The TLC32040, TLC32044, TLC32046, TLC32047, and TLC320AC01/02
analog interface circuits (AIC) are especially suited for modem applications by
the integration of an input multiplexer, switched capacitor filters, high
resolution 14-bit ADC and DAC, a four-mode serial port, and control and timing
logic. These converters feature adjustable parameters, such as filtering
characteristics, sampling rates, gain selection, (sin x)/x correction (TLC32044,
TLC32046, TLC32047 and TLC320AC01 102 only), and phase adjustment. All
these parameters are software programmable, making the AIC suitable for a
variety of applications. Table A-9 has the description and characteristics of
these devices.
Table A-9. Modem AFE Data Converters
Device
Description
110
Resolution
(Bits)
Conversion
Rate
TLC32040
Analog interface chip (AIC)
Serial
14
19.2 kHz
TLC32041
AIC without on-board VREF
Serial
14
19.2 kHz
TLC32044
Telephone speed/modem AIC
Serial
14
19.2 kHz
TLC32045
Low-cost version of the
TLC32044
Serial
14
19.2 kHz
TLC32046
Wide-band AIC
Serial
14
25 kHz
TLC32047
AIC with 11.4-kHz BW
Serial
14
25kHz
TLC320AC01/02
5-volt-only AIC
Serial
14
25 kHz
TCM29C18
Companding codec/filter
PCM
8
8kHz
TCM29C23
Companding codec/filter
PCM
8
16 kHz
TCM29C26
Low-power codeC/filter
PCM
8
16 kHz
Single-supply codec/filter
PCM
and
Linear
8
25kHz
TCM320AC36
The AIC interfaces directly with serial-input TMS320 DSPs, which execute the
modem's high-speed encoding and decoding algorithms. The TLC3204x
family performs level-shifting, filtering, and AID and D/A data conversion. The
DSP's many software-programmable features provide the flexibility required
for modem operations and make it possible to modify and upgrade systems
easily. Under DSP control, the AIC's sampling rates permit designers to
include fall-back modes without additional analog hardware in most cases.
Phase adjustments can be made in real time so that the AID and D/A
conversions can be synchronized with the upcoming signal. In addition, the
chip has a built-in loopback feature to support modem self-test requirements.
A-15
Multimedia Applications
For further information or application assistance, please call TI Linear
Applications at (214) 997-3772.
FigureA-9. High-Speed V.32 Bis and Multistandard Modem With the TLC320AC01 AIC
TLC320AC01
+
ADCand DAC
Fine Tune
Echo-Cancel
:1
D
A
A
Telephone
Line
Echo Canceler
Transmitter
RS-232
/IF
Serial
I/O
Control
TMS320C25/C5X
Receiver
Figure A-9 shows a V.32 bis modem implementation using the TMS320C25
and a TLC320AC01. The upper TMS320C25 performs echo cancellation and
transmit data functions, while the lower TMS320C25 performs receive data
and timing recovery functions. The echo canceler simulates the telephone
channel and generates an estimated echo of the transmit data signal. The
TLC320AC01 performs the following functions:
Upper TLC320AC01 O/A Path: Converts the estimated echo, as computed by
the upper TMS320C25, into an analog signal,
which is subtracted from the receive signal.
Upper TLC320AC01 A/O Path: Converts the residual echo to a digital signal for
purposes of monitoring the residual echo and
continuously training the echo canceler for
optimum performance. The converted signal is
sent to the upper TMS320C25.
Lower TLC320AC01 01A Path: Converts the upper. TMS320C25 transmit
output to an analog signal, performs a
smoothing filter function, and drives the DAC.
Lower TLC320AC01 O/A Path: Converts the echo-free receive signal to a
digital signal, which is sent to the lower
TMS320C25 to be decoded.
Note: About the Above Example
The example above is for illustration only. In reality, one single TMS320C5x
DSP can implement high-speed modem functions.
A-16
Analog Interface Peripherals and Applications
Advanced Digital Consumer Electronics Applications
A.S Advanced Digital Electronics Applications for Consumers
With the extensive use of the TMS320 DSPs in consumer electronics, much
electromechanical control and signal processing can be done in the digital
domain. Digital systems generally require some form of analog interface,
usually in the form of high-performance ADCs and DACs. Figure A-1 0 shows
the general performance requirements for a variety of applications.
Figure A-1 O. Applications Performance Requirements
MSPS
300
Instrumentation
S
a
m 100
p
I
i
n
g
F
30
n
c
y
Broadcasting
ADTV
e
q
u
e
HDTV
DVTR
10
Fax/PC
4
5
6
7
8
9
10
Bits
PerformancelApplication
Advanced Television System Design Considerations. Advanced
Digital Television (ADTV) is a technology that uses digital signal processing to
enhance video and audio presentations and to reduce noise and ghosting .
.Because of these DSP techniques, a variety of features can be implemented,
including frame store, picture-in-picture, improved sound quality, and zoom.
The bandwidth requirements remain at the existing 6-MHz television
allocation. From the IF(intermediate frequency) output, t~e video signal is
converted by an a-bit video ADC. The digital output can be processed in the
digital domain to provide noise reduction, interpolation or averaging for
digitally increased sharpness, and higher quality audio. The DSP digital output
is converted back to analog by a video DAC, as shown in Figure A-11.
A-17
Figure A-11. Video Signal Processing Basic System·
TMS320
.DSP
TV IF
Amplifier
Field
Memory
Buffer
System
Controller
Clock
Generator
VCRs, compact disc and OAT players, and PCs are a few of the products that
have taken a major position in the marketplace in the last ten years. The audio
channels for compact disc and OAT require 16-bit AlO resolution to meet the
distortion and noise standards. See NO TAG for a block diagram of a typical
digital audio system.
The audio processing becomes more demanding as higher fidelity is required.
Better fidelity translates into lower noise and distortion in.the output signal.
The TMS570140W 1-bit digital-to-analog converters (OAC) include an 8 times
over sampling digital filter designed for digital audio systems, such as COPs,
OATs, CO Is, LOPs, digital amplifiers, car stereos, and BS tuners. They are also
suitable for all systems that include digital sound processing like TVs, VCRs,
musical instruments, NICAM systems, multimedia, etc.
The converters have dual channels so that the right and left stereo signals can
be transformed into analog signals with only one chip. There are some
functions that allow the customers to select the conditions according to their
applications, such as muting, attenuation, de-emphasis, and zero data
detection. These functions are controlled by external 16-bit serial data from a
controller like a microcomputer.
The TMS570140W has a 129-tap FIR filter and third-order Ill: modulation to
get -75-dB stop band attenuation and 96-dB SNR. The output is PWM wave,
which facilitates analog signal through a low-pass filter.
Table A-1 0 lists TI products for analog interfacing to digital systems.
A-18
Analog Interface Peripherals and Applications
Advanced Digital Consumer Electronics Applications
Table A-1 O. AudioNideo AnalogJDigitallnterface Devices
Function
Device
Bits
Dual audio DAC+ digital filter
TMS57013
16/18
Speed
Channels
Interface
32,37.8,
44.1,48 kHz
2
Serial
12 J.LS
1
Parallel
6J.LS
1
Parallel
AID
TLC1225
12
AID
TLC1550
10
Video D/A
TLC5602
8
50 ns
1
Parallel
Triple video D/A
TL5632
8
16 ns
3
Parallel
Triple flash AID
TLC5733
8
70 ns
3
Parallel
Pipelined AID
TLC5510
8
50 ns
1
Parallel
Semiflash AID
TLC5540
8
25 ns
1
Parallel
For further information or application assistance, please call TI Linear
Applications at (214) 997-3772.
A-19
Analog Interface Peripherals and Applications
Notes
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A04038&
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TI assum.. no r..pon.lbUIty lor customa..• applications or product designs.
@ 1995 Taxas Instruments Incorporated
Printed in the USA
TEXAS
INSTRUMENTS
~lExAs
INSIRUMENTS
Printed in U.S.A.
7-95
SLAD001
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