1995_TI_MOS_Memory_Data_Book 1995 TI MOS Memory Data Book
User Manual: 1995_TI_MOS_Memory_Data_Book
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~TEXAS
INSTRUMENTS
MOSMemory
Commercial and Military Specifications
1995
1995
MOSMemory
Data Book
Commercial and Military
Specifications
•
TEXAS
INSTRUMENTS
Printed on Recyded Peper
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice,and advises its customers to obtain the latest
version of relevant information to verify,· before placing orders, that the Information being relied
on is cum;nt,
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with Tl's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to· support this warranty.
Specific testing of aI/ parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal Injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN L1FE·SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
representthat any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other Intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
Copyright@ 1995, Texas Instruments Incorporated
General Information
ISelection Guide
IDefinition of Terms
I DRAMs
SDRAM/VRAMs
SIMMS
EPROMs/OTP PROMs/Flash EEPROMS.
Military Products
•
Mechanical Data
..
Logic Symbols
Quality and Reliability
Electrostatic Discharge Guidelines
!
INTRODUCTION
The 1995 MOS Memory Data Bookfrom Texas Instruments Includes complete detailed specifications on the
expanding MOS Memory product line Including Dynamic Random Access Memories (DRAMs), Singie-in-Una
Memory Modules (SIMMs), Erasable Programmable Read-Only Memories (EPROMs), One-11me
Programmable Read-Only Memories (OTP PROMs), Electrically Erasable Programmable Read~Only
Memories (Flash Memories), and Video RAMs (VRAMs). Also Included are military specifications for DRAMs,
EPROMs, and VRAMs.
The data book is divided Into 12 chapters. Below you will find a brief description of each chapter.
Chapter 1. General Information -Includes an alphanumeric Index for quickly finding device numbers and a part
number guide with ordering Information.
Chapter 2. Selection Guide - An easy-to-use reference guide that Includes specific device Information. Page
numbers are also shown for easy access to the detailed specifications.
Chapter 3. Glossaryrnmlng ConventlonS/Data Sheet Structure throughout the data book.
Chapter~.
Defines terms and standards used
Product specifications for more than 100 devices can be found In these sections.
Chapter 9. Mechanical Data - Detailed package drawings and specifications are shown in this section.
Chapter 10. Logic Symbols -Includes an explanation and examples of the IEEE standard.
Chapter 11. Quality and Reliability - Details selected processes and the philosophies of Texas Instruments that
are used to ensure high quality standards.
Chapter 12. Electrostatic Discharge Guidelines handling guidelines are Included.
Because all MOS Memory devices are ESD-sensltlve,
For ordering Information or further assistance, please contact your nearest Texas Instruments Sales Office or
Distributor as listed In the back of this book.
v
PRODUCT STAGE STATEMENTS
Product stage statements are used on Texas Instruments data .sheetsto Indicate the development stage(s) of the
product(s) specified in the data sheets.
If all products specified in a data sheet are at the same development stage. the appropriate statement from the
following list is placed In the lower left comer of the first page of the data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the
terms of Texas Instruments standard warranty.· Production processing does not necessarily include testing of
all parameters.
ADVANCE INFORMATION concems new products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change without notice.
PRODUCT PREVIEW Information conCems products in the formative or design phase of development.
Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
.
If not all products specified in a data sheet are at the PRODUCTION DATA stage. then the first statement below is
placed in the lower left comer of the first page of the data sheet. Subsequent pages of the data sheet containing
PRODUCT PREVIEW information or ADVANCE INFORMATION are then marked in the lower left-hand comer with
the appropriate statement given below:
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of
publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
ADVANCE INFORMATION concems new products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change without notice.
PRODUCT PREVIEW information concems products in the formative or design phase of development.
Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
vi
Contents
CHAPTER 1.
GENERAL INFORMATION
Alphanumeric Index ...•.........•.....................•..................•............•..•.••.•.•
Ordering Information .............................•...................•.....•. '.' • • . . . . . . • . . . • . . • . ••
DRAM/SDRAM .•....................•...............•...•.•.........••••••...•..•....•..•..•
DRAM ....................................................•...•...•......•......•.•.•..•.•.
Standard DRAM Module. . . . . . . . . . . . . . . • . . . . . . . . . . . • . • . . . . . . . • . . . . . • . . . . . . • . • . . . . . . • • . . • • • . . ..
Differentiated DRAM Module ..................................................................
EPROMs/FLASH/OTP .................•.•..•..•..•..........•....•.......••........•..••.••.
VRAM ...............................•..•....•............•...•......•...•......•.•....•.••
CHAPTER 2.
1-3
1-4
1-4
1-5
1-6
1-7
1-8
1-9
SELECTION GUIDE
Dynamic Random-Access Memory (DRAM) ......................................•.......•........•. 2-3
Synchronous DRAM ... . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . • . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . • . . • . • • . . .• 2-9
Video Random-Accesss Memory (VRAM) .......................................................... 2-10
Single-In-Une Memory Modules (SIMMS) ......................... 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11.
Rash Memory ....................•..•.....•.•..•.....•..•.................•..•••..•..•..•..••.• 2-15
Erasable Programmable Read-Only Memory (EPROM) ....•...................••.•••...•..•..•.••••• 2-16
One-lime Programmable (OTP) ....•..•................•........•....•.....•.•..•....•..•....••.•• 2-17
CHAPTER 3.
DEFINITION OF TERMS/TIMING CONVENTIONS
General Concepts and "TYPes of Memories ...............•.•................•..•.......•.••.•..••... 3-3
Operating Conditions and Characteristics ...•............•.•................••..•...•....•..•.•..... 3-7
liming Diagram Conventions .......•...................•.••.......•.............•......•..•.••.•. 3-13
CHAPTER 4.
TMS44460
TMS44460P
TMS46460
TMS46460P
TMS44100
TMS44100P
TMS46100
TMS46100P
TMS44400
TMS44400P
TMS46400
TMS46400P
TMS44165
TMS44165P
TMS45160
TMS45160P
DYNAMIC RANDOM-ACCESS MEMORY (DRAM)
4194304-bit
4194304-bit
4194304-bit
4194304-bit
4194304-blt
4194304-blt
4194304-bit
4194304-blt
4194304-bit
4194304-bit
4194304-bit
4194304-bit
4194304-bit
4194304-bit
4194304-bit
4194304-bit
(1 024K x 4) Enhanced Page Mode, Quad CAS . . . . . . • . • . • . . • . . . . . .. 4-5
(1 024K x 4) Enhanced Page Mode, Quad CAS, Low Power . . • . . . • . .. 4-5
(1 024K x 4) Low Voltage, Quad CAS. . . . . . . . . . . . . • . . . . . • . . • . . . . . •. 4-5
(1 024K x 4) Low Voltage, Quad CAS, Low Power. • . . . • . . . . . • . . • . . .. 4-5
(4096Kx 1) Enhanced Page Mode •....•....•.....•...•.•....... 4-27
(4096Kx 1) Low Power ........................................ 4-27
(4096Kx 1) Low Voltage ....................................... 4-27
(4096K x 1) Extended Refresh .................................. 4-27
(1 024K x 4) Enhanced Page mode .............................. 4-51
(1 024K x 4) Low Power •..•...............•...••.....•......•.• 4-51
. (1 024K )( 4) Low Voltage ............•..•..•..........•.•••..••• 4-51
(1 024K x 4) Extended Refresh .................................. 4-51
(256K x 16) Enhanced Page Mode •...............•.... " . • . . • • .• 4-73
(256K x 16) Low Power. . . . . . . . . . . . . . • . . . • . . . • . . . . . . . . • . . • . • . • .• 4-73
(256K x 16) Enhanced Page Mode. . . . . . . . . . . . . . . . . • . • . • . . . . . . . .. 4-93
(256K x 16) Low Power. . .. . . . . . • . . . . . • . . . . . . . . . . • • . • . • . . • . .. . •• 4-93
vii
TMS45165
TMS45165P
TMS416400
TMS416400P
TMS417400
TMS417400P
TMS426400
TMS426400P
TMS427400
TMS427400P
TMS416160
TMS416160P
TMS426160
TMS426160P
TMS418160
TMS418160P
TMS428160
TMS428160P
TMS464400
TMS464400P
TMS464800
TMS464800P
TMS464160
TMS464160P
TMS416169
TMS416169P
TMS418169
TMS418169P
TMS4261!39
TMS426169P
TMS428169
TMS428169P
CHAPTERS.
TMS626402
TMS626802
TMS55160
TMS55165
TMS55161
TMS55166
viii
4194304-blt
4194304-bIt
16777216-bIt
16777216-bit
16777216-blt
16777216-bit
16777216-blt
16777216-bit
16777216-blt
16777216-blt
16777216-bit
16777216-blt
16777216-bIt
16777216-bit
16777216-blt
16777216-blt
16777216-blt
16777216-bit
67108864-bit
.67108864-bit
67108864-bit
67108864-bit
67108864-blt
67108864-bit
16777 216-bit
16777216-bit
16777216-bit
16777216.-bit
16777216-bit
16777216-bjt
16777216-blt
16777216-blt
(256K )C 16) Enhanced Page Mode •.•••..••••.••.....•..• ',' .••. ,
(256K)C 16) Low Power. .. . .. . .. . .. .. • • . • .. .. .. • .. . . . . . . .. . ....
(4096K)C 4) Enhanced Page Moc;Ie .............................
(4096K)C 4) Enhanced Page Mode .............................
(4096K)C 4) Enhanced Page Mode .............................
(4096K)C 4) Enhanced Page Mode .•..•......•..••••••.•••••.••
(4096K)C 4) Low Voltage ......................................
(4096K)C 4) Low Voltage, Low Power ••.•••.••.•..•...••••.•••.•
(4096K)C 4) Low Voltage ••••........•..•.....•.....••..••.•.• ~
(4096K)C 4) Low Voltage, Low Power ...........................
(1 024K)C 16) Enhanced Page Mode ............................
(1 024K)C 16) Low Power ..................... ~ ................
(1024K)C 16) Low Voltage .....................................
(1 024K)C .16) Low Voltage, Low Power ..........................
(1 024K)C 16) Enhanced Page Mode ............................
(1 024K)C 16) Low Power ......................................
(1 024K )C 16) Low Voltage .....................................
(1 024K )C 16) Low Voltage, Low Power ..........................
(16384K)C 4) Enhanced Page Mode ...••.•.....•••.....•.......•
(16384K)C 4) Enhanced Page Mode, Low Power ••..••..•.•..••.•
(8 192K )C 8) Enhanced Page Mode ••••••.•..•.•.••..••........•
(8192K)C 8) Enhanced Page Mode, Low PoWer .•.•..•.••••..••.•
(4096K)C 16) Enhanced page Mode ............................
(4096K)C 16) Enhanced Page Mode, Low Power .•••............•
(1 024K)C 16) Extended Data Out Mode .........................
(1 024K)C 16) Extended Data Out Mode, Low Power ..•.••••.•••.•
(1 024K)C 16) Extended Data Out Mode ..•.....•.•..•.•••..•••.•
(1 024K)C 16) Extended Data Out Mode, Low Power .•...•.•.••••.
(1 024K)C 16) Extended Data Out Mode, Low Voltage ••.••.•..•••.
(1 024K )C 16) Extended Data Out Mode, Low Voltage, Low Power ••
(1 024K)C 16) Extended Data Out Mode, Low Voltage •••.•••.•...•
(1 024K )C 16) Extended Data Out Mode, Low Voltage, Low Power ..
4-115
4-115
4-135
4-135
4-135
4-135
4-135
4-135
4-135
4-135
4-1~
4-163
4-163
4-163
4-163
4-163
4-163
4-163
4-187.
4-187
4-187
4-187
4-187
4-187
4-191
4-191
4-191
4-191
4-191
4-191
4-191
4-191
'SYNCHRONOUS DRAM (SDRAM)
VIDEO RANDOM-ACCESS MEMORY (VRAM)
16777216-bit
16777216-bit
4194304-bit
4194304-bit
4194304-bit
4194304-blt
(4096K)C 4) Synchronous DRAM
(2048K)C 8) Synchronous DRAM
(256K )C 16) Multiport Video RAM
(256K )C 16) Multlport Video RAM
(256K)C 16) Multiport Video RAM
(256K)C 16) Multlport Video RAM
•••.•.••••..•.••....•......•..••• 5-3
................................ 5-41
.•.........•.•.•..•...•.•....... 5-79
......•.••.•..'................. 5-135
............................... 5-191
............................... 5-251
CHAPTER 6.
SINGLE-IN-LiNE MEMORY MODULES (SIMMS)
4
4
4
4
4
4
Mbyte
Mbyte
Mbyte
Mbyte
Mbyte
Mbyte'
TM4100GAD8
TM497GU8
TM4100EAD9
TM497EU9
TM124BBK32
TM124BBK32S
TM248CBK32
TM248CBK32S
TM124BBK32F
TM124BBK32U
TM248CBK32F
TM248BK32U
TM497BBK32
TM497BBK32S
TM893CBK32
TM893CBK32S
TM124MBK36B
TM124MBK36R
TM248NBK36B
TM248NBK36R
TM124MBK36F
TM124MBK36U
TM248NBK36F
TM248NBK36U
8 Mbyte
8 Mbyte
4 Mbyte
4 Mbyte
8 Mbyte
8 Mbyte
16 Mbyte
16 Mbyte
32 Mbyte
32 Mbyte
4 Mbyte
4 Mbyte
8 Mbyte
8 Mbyte
4 Mbyte
4 Mbyte
8 Mbyte
8 Mbyte
TM124MBK36C
TM124MBK36S
TM248NBK36C
TM248NBK36S
4 Mbyte
4 Mbyte
8 Mbyte
8 Mbyte
TM124MBK36G
TM124MBK36V
TM248NBK36G
TM248NBK36V
TM497MBK36A
TM497MBK36Q
4 Mbyte
4 Mbyte
8 Mbyte
8 Mbyte
16 Mbyte
16 Mbyte
16 Mbyte
16 Mbyte
32 Mbyte
32 Mbyte
TM497MBM36A
TM497MBM36Q
TM893NBM36A
TM893NBM36Q
(4096K x 8) Single-Sided (Solder-tabbed) ......................... 6-3
(4096K-x 8) Single-Sided (Solder-tabbed) ...................•..... 6-9
(4096K x 9) Single-Sided (Solder-tabbed) ....................•... 6-15
(4096K x 9) Single-Sided (Solder-tabbed) ...........•.•.....•.... 6-23
(1 024K x 32) Single-Sided (Gold-tabbed) ..... . . . . . . . . . . . . . . . . . . .. 6-29
(1 024K x 32) Single-Sided (Solder-tabbed) ...................•... 6-29
(2048K x 32) Double-Sided (Gold-tabbed) ........•......•....•.•. 6-29
(2048K x 32) Double-Sided (Solder-tabbed) ...................... 6-29
(1 024K x 32) Single-Sided (Gold-tabbed) .........•••....•.•...••. 6-39
(1 024K x 32) Single-Sided (Solder-tabbed) ....................... 6-39
(2048K x 32) Double-Sided (Gold-tabbed) .....................•.. 6-39
(2048K x 32) Double-Sided (Solder-tabbed) ...................... 6-39
(4096K x 32) Single-Sided (Gold-tabbed) .....................•... 6-47
(4096K x 32) Single-Sided (Solder-tabbed) ....................... 6-47
(8192K x 32) Double-Sided (Gold-tabbed) ........................ 6-55
(8192K x 32) Double-Sided (Solder-tabbed) ...................... 6-55
(1 024K x 36) Single-Sided (Gold-tabbed) ......... . . . . . . . . . . . . . . .. 6-63
(1 024K x 36) Single-Sided (Solder-tabbed) ....................... 6-63
(2048K x 36) Double-Sided (Gold-tabbed) ....................•... 6-63
(2048K x 36) Double-Sided (Solder-tabbed) ...................... 6-63
(1 024K x 36) Single-Sided (Gold-tabbed) ......................... 6-73
(1 024K x 36) Single-Sided (Solder-tabbed) ...................•... 6-73
(2048K x 36) Double-Sided (Gold-tabbed) ............•........•.. 6-73
(2048K x 36) Double-Sided (Solder-tabbed) ...•.................. 6-73
(1 024K x 36) Single-Sided (Gold-tabbed) ......•..........••..••.• 6-81
(1 024K x 36) Single-Sided (Solder-tabbed) .......•......•........ 6-81
(2048K x 36) Double-Sided (Gold-tabbed) •.•...•.•..•••....•..•.• 6-81
(2048K x 36)
(1 024K x 36)
(1 024K x 36)
(2048K x 36)
(2048K x 36)
(4096K x 36)
(4096K x 36)
(4096K x 36)
(4096K x 36)
(8192K x 36)
(8192K x 36)
Double-Sided (Solder-tabbed) .•................•... 6-81
Single-Sided (Gold-tabbed) ., •.•. ,', •.• , , , .• , , , , , . .. 6-91
Single-Sided (Solder-tabbed) . . . . . . . . . . . . • . . . . • . . • . .• 6-91
Double-Sided (Gold-tabbed) ........................ 6-91
Double-Sided (Solder-tabbed). . . . . . . . . . . . . . . . . . . . .. 6-91
Double-Sided (Gold-tabbed) .....•..•.•......•...••• 6-99
Double-Sided (Solder-tabbed) ...................... 6-99
Single-Sided (Gold-tabbed) ..........•............. 6-107
Single-Sided (Solder-tabbed) ...................... 6-107
Double-Sided (Gold-tabbed) ....................... 6-107
Double-Sided (Solder-tabbed) .......•.••....••.... 6-107
Ix
CHAPTER 7.
TMS28F512A
TMS28F010B
TMS28F210
TMS28F020
TMS28F200BZT
TMS28F200BZB
TMS28F400BZT
TMS28F400BZB
TMS27C256
TMS27PC256
TMS27C510
TMS27PC510
TMS27C512
TMS27PC512
TMS27C010A
TMS27PC010A
TMS27C210A
TMS27PC210A
TMS27C020
TMS27PC020
TMS27C040
TMS27PC040
TMS27C240
TMS27PC240
FLASH MEMORY
.
ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EPROM)
ONE-TIME PROGRAMMABLE MEMORY (OTP)
524288-bit
1048576-bit
1048576·bit
2097152·bit
2097152·bit
2097152·bit
4194304-bit
4194304·bit
262144-bit
262144-bit
524288·bit
524288·bit
524288·bit
524288-bit
1048576·bit
1048576·bit
1048576·bit
1048576·bit
2097152·bit
2097152·bit
4194304·bit
4194304·bit
4194304·bit
4194304·bit
CHAPTERS.
(64K x 8) 12·V Flash Memory .................................... 7·3
(128K x 8) 12·V Flash Memory .................................. 7·25
(64K x 16) 12·V Rash Memory .................................. 7-47
(256Kx 8) Flash Memory ....................................... 7-67
(256K x 81512K x 16) Flash Memory ............................. 7·87
(256K x 8/512K x 16) Flash Memory .•........................... 7·87
(256K x 8/512K x 16) Rash Memory ............................ 7·115
(256K x 8/512K x 16) Rash Memory ............................ 7·115
(32K x 8) CMOS EPROM ...............•...................... 7·143
(32K x 8) CMOS OTP PROM .................................. 7·143
(64K x 8) CMOS EPROM ..•................................... 7·155
(64K x 8) CMOS OTP PROM .............................. ; ... 7·155
(64K x 8) CMOS EPROM ...................................... 7·167
(64Kx 8) CMOS OTP PROM .................................!. 7·167
(128K x 8) CMOS EPROM ..................................... 7·179
(128K x 8) CMOS OTP PROM ................................. 7·179
(64Kx 16) CMOS EPROM ..................................... 7·191
(64K x16) CMOS OTP PROM ................................. 7·191
(256K x 8) CMOS EPROM ..................................... 7·201
(256K x 8) CMOS OTP PROM ................................. 7·201
(512K x 8) CMOS EPROM ..................................... 7·211
(512K x 8) CMOS OTP PROM ................................. 7·211
(256K x 16) CMOS EPROM .................................... 7·221
(256K x 16) CMOS OTP PROM ................................ 7·221
MILITARY PRODUCTS
Military Introduction .•..................................•.: ........................................ 8·3
DYNAMIC RAMS
SMJ44C256
SMJ4Cl024
SMJ441 00
SMJ44400
SMJ416100
SMJ416400
SMJ416160
SMJ418160
1048576-bit ,
1048576·bit
4194304-bit
4197304-bit
16777216·bit
16777216-bit
. 16777216·bit
16777216·bit
(256K x 4) Enhanced Page Mode.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ... 8·5
(1 024K x 1) Enhanced Page Mode .............................. 8·25
(4096K x 1) Enhanced Page Mode .•....'\. ....................... 8·45
(1 024K x 4) Enhanced Page Mode .............................. 8·65
(16385K xl) Enhanced Page Mode •............................ 8·85
(4096K x 4) Enhanced Page Mode ............................. 8·105
(1 024K x 16) Enhanced Page Mode ............................ 8~123
(1 024K x 16) Enhanced Page Mode ............................ 8·123
VIDEO RAMS
SMJ44C251B
SMJ55161
SMJ55166
x
1048 576·bit
4194304·bit
4194304-bit
(256K x 4) Multiport Video RAM ................................ 8·145
(256K x 16) Multiport Video RAM ............................... 8-197
(256K x 16) Multiport Video RAM ............................... 8-259
EPROMS
SMJ27C128
SMJ27C040
CHAPTER 9.
131072-bit
4194304-bit
(16K )( 8) UV Erasable Programmable Read-Only Memory • • . • • . • •. 8-319
(512K)( 8) UV Erasable Programmable Read-Only Memory ..•.•.•• 8-331
MECHANICAL DATA
MOS Memory Products - Commercial ...................................••.•....•.•.•.•..•••.••.•.. 9-5
MOS Memory Products - Military. . . . . • . • . • . . . • . . . . . • . . • . • . • . . . • . • . • . . . . . . . . . . . . . • • . . • • . • . . . • • • • • .• 9-31
CHAPTER 10.
LOGIC SYMBOLS
Explanation of IEEE/lEC Logic Symbols for Memories ••.•••.•.•.•.•...•..........•.....•..••.•.••••• 10-3
CHAPTER 11.
QUALITY AND RELIABILITY
MOS Memory Products Division Quality and Reliability Information .•..•••••.•.•.•................•.••. 11-3
CHAPTER 12.
ELECTROSTATIC DISCHARGE GUIDELINES
Guidelines for Handling Electrostatic-Discharge Sensitive Devices and Assemblies •...•.........•....... 12-3
xl
xii
General Information
1·1
:IIThxAs
INSTRUMENTS
1·2
POST OFFICE BOX 1448 •
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Alphanumeric Index
SMJ27C040 ............. 8-331
SMJ27C128 ............. 8-319
SMJ4C1024 ............... 8-25
SMJ416100 ............... 8-85
SMJ416160 ............. 8-123
SMJ416400 ............. 8-105
SMJ418160 ............. 8-123
SMJ44C251B .••..•.••... 8-145
TM497BBK32 .............. 6-47
TM497BBK32S ............ 6-47
TM497EU9 ................ 6-23
TM497GU8 ................. 6-9
TM497MBK36A ............ 6-99
TM497MBK36Q ............ 6-99
TM497MBM36A .......... 6-107
TM497MBM36Q .•....•.. 6-107
TMS416400P ............
TMS418160P ............
TMS418169 .............
TMS418169P ............
TMS426160 .............
TMS426160P ............
TMS426169 .............
TMS426169P .....•.•..•.
SMJ44C256 ................ 8-5
TM893CBK32 ............. 6-55
TMS426400 ............. 4-133
TM893CBK32S ............ 6-55
TMS426400P ............ 4-133
TMS427400 ............. 4-133
SMJ44100 ................ 8-45
SMJ44400 ................ 8-65
SMJ55161 .............. 8-197
SMJ55166 .............. 8-259
TM124BBK32 .•.•.•...••.•. 6-29
TM124BBK32F ..•••.•....• 6-39
TM124BBK32S ............ 6-29
TM124BBK32U ............ 6-39
TM124MBK36B ............ 6-63
TM124MBK36C •.•.....••.. 6-81
/ , TM124MBK36F ............ 6-73
TM124MBK36G .......••..• 6-91
TM124MBK36R ............ 6-63
TM124MBK36S •......•.... 6-81
TM124MBK36U ............ 6-73
TM893NBM36A .......... 6-107
TM893NBM36Q •......... 6-107
TMS27C010A ........... 7-181
TMS27C020 .............
TMS27C040 .............
TMS27C210A ...........
TMS27C240 ........... ; •
7-203
7-213
7-193
7-223
TMS27C256 ............. 7-145
TMS27C510 ............. 7-157
TMS27C512 ............. 7-169
TMS27PC010A .......... 7-181
TMS27PC020 ........... 7-203
TMS27PC040 ........... 7-213
TMS427400P ............
TMS428160 .............
TMS428160P ............
TMS428169 .............
TMS428169P ............
4-133
4-161
4-189
4-189
4-161
4-161
4-189
4-189
4-133
4-161
4-161
4-189
4-189
TMS44100 ...••.•........• 4-25
TMS44100P ............... 4-25
TMS44165 ................ 4-71
TMS44165P ............... 4-71
TMS44400 •.••.....•..••.• 4-49
TMS44400P ...•••..•••..•. 4-49
TMS27PC210A .......... 7-193
TMS45160 ................ 4-71
TMS45160P ............... 4-71
TM248CBK32 •.•••.••.•••• 6-29
TMS27PC256
TMS27PC240 ........... 7-223
........... 7-145
TMS45165P ••••.••••••.•• 4-113
TM248CBK32F ...•..•..... 6-39
TM248CBK32S ............ 6-29
TMS27PC510 ........... 7-157
TMS27PC512 ........... 7-169
TMS46100 ••.•...•••.•.••. 4-25
TMS46100P ............... 4-25
TM248CBK32U ............ 6-39
TMS28F010B .............. 7-25
TMS46400 ................ 4-49
TM248NBK36B •......••... 6-63
TMS28F020 ......•.•••.... 7-67
TMS46400P .••...•.......• 4-49
TM248NBK36C ....•....... 6-81
TMS28F200 ..•.....•...... 7-89
TMS464160 •.•...•...... 4-185
TM248NBK36F ............ 6-73
TMS28F210 ............... 7-47
TMS464400 ............. 4-185
TM248NBK36G ............ 6-91
TM248NBK36R .••••...•.•• 6-63
TMS28F400 .............. 7-117
TMS28F512A •••.•....••.••• 7-3
TMS464800 ............. 4-185
TMS55160 •••••...•..•.••• 5-79
TM124MBK36V ............ 6-91
TMS45165 ............... 4-113
TM248NBK36S ............ 6-81
TMS416160 ............. 4-161
TMS55161 .............. 5-191
TM248NBK36U ............ 6-73
TM248NBK36V ............ 6-91
TM4100EAD9 ............. 6-15
TMS416160P ............ 4-161
TMS416169 ............. 4-189
TMS416169P ............ 4-189
TMS55165 .............. 5-135
TMS55166 .............. 5-251
TMS626402 ................ 5-3
TM4100GAD8 .............. 6-3
TMS416400 ............. 4-133
TMS626802 ............... 5-41
~1ExAs
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1-3
General Information
DRAMNRAM/FMEM Ordering Information
Orders for DRAMs and VRAMs described in this book should Include an eight-part number as explained in the
following example:
.
TMS
1. Prefix: _ _ _ _ _ _ _ _ _ _ _---'1
TMS
SMJ
I
4
4
C
258
-10
OJ
Commercial MOS
Military MOS
2. Produ91 Family: - - - - , - - - - - - - - - - - - '
4
3. Word Width:
Blank
Blank
4
8
DRAM/VRAM
)( 1
)( 4
)(4
)(8
18
)( 18
4. Technology: - - - - - - - - - - - - - - - - - - - - '
·C
CMOS
6. Density: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'--0.1
6. Speed Designator: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1
DRAMsNRAMB
80ns
-70 70ns
-60 80ns
-10
100ns
-12 120 ns
-15 150ns
-20 200ns
-60
7. Package: - - - - - - - - - - - - - - - - - - - - - - - - - : - -.....
Commercial (Plastic)
Military (Ceramic)
OJ
Small-Outline J-Lead (SOJ)
FQ
Smail-Outline Leadleas Chip Carrier (SOlCC)
ON
Thin Small-Outline J-Lead (ThlnSOJ)
FV
Leadless Chip Carrier (ClCC)
HJ
Small-Outllne J-Lead (SOJ)
DZ
Small-Outllne J-Lesd (SOJ)
SO
Zig-Zag In-Une (ZIP)
HK
Ratpack
N
Dual-In-Une (DIP)
Hl
Low Profile Lesdless Surface Mount
DGA Thin Small-Outllne Package
JD
Dual-In-Une (DIP)
SV
Zig-Zag In-Une (ZIP)
--------------------------1
8. Temperature Range:
Commercial
l
O°C to 70°C (\'RAMs)
Blank OOC to 70°C (DRAMs)
Military
M
- 55°C to 125°C
~1ExAs
1-4
INSTRUMENTS
POST OFFICE &OX 1443 •
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General Information
DRAM Ordering Information
I
Orders for the 4 Meg and 16 Meg and 64 Meg DRAMs described In this book should include an eight-part
number as explained in the following example:
00
-so
OM
1. Prefix:
T~S 1
TMS Commercial MOS
SMJ Military MOS
2. Product Family:
4 DRAM
3. Denslty- Refresh: _ _ _ _ _ _ _ _ _ _ _....J
2 2 Meg 1K Refresh
4 4 Meg 1K Refrssh
5 4 Meg 512 Cycle Refresh
6 4 Meg 1K Refresh 3.3 V
7 4 Meg 512 Cycle Refresh 3.3 V
16 16 Meg 4KRefresh5V
17 16 Meg 2KRefrssh5V
18 18 Meg 1KRefresh5V
28 16 Meg 4K Refresh 3.3 V
27 16 Meg 2K Refresh 3.3 V
28 16 Meg 1K Refresh 3.3 V
84 64 Meg 8K Refrssh 3.3 V
4. Organization-I/O: - - - - - - - - - - - - - - - - '
10 x 1
Std
90 x9
Sid
26 x 2
Quad-CAS
91 x9
WPB
40 x4
SId
18 x 18 Sid
41 x4
WPB
17 x 18 WPB
18 x 18 SId
46 x 4
Quad-CAS
SO x8
Std
19 x 18 WPB
81 x8
WPB
5. Functional Mode/Options:
o Enhanced Page Mode
5 En!:l1!nced Page Mode
o Enhanced Page Mode
2 WE(xI8 and x18 Devices)
2 CAS (x16 and x18 Devices)
9 Extendad Data Out
Enhanced Page Mode
Extended Data Out
9 2 CAS (x18 and x18 Devices)
4 CAS (Quad-CAS Devices)
o
6. Speed D e s l g n a t o r : - - - - - - - - - - - - - - - - - - - - . . . J
-60 SOns
-SO SOns
-70 70ns
7. P a c k a g e : - - - - - - - - - - - - - - - - - - - - - - - - - . . . . J
Commercial (Plastic)
DGA 3OQ-mil Thin Small Outline (TSOP)
DGB 30Q-mll Reverse l:ead Thin Small Outline
(TSOP)
DGC 400-mll Thin Small Outline (TSOP)
(SO-mll-pltch)
DGD 400-mll Reverse Lead Thin Small Outline
(TSOP) (50-mil-pitch)
OGE 4OO-mil Thin Small Outline (TSOP)
(31-mll-pltch)
DGF 4OO-mil Reverse Lead Thin Small Outline
(TSOP) (31-mIl-pltch)
OJ 300-mil Small Outline J-Lead (SOJ)
(26/24-lead)
ON Thin Small Outline J-Lead (SOJ)
DZ 4OQ-mil Small Oulline J-Lead (SOJ)
8. Tempereture Range:
Commercial
Blank O·C to 70·C
Military (Ceramic)
HM Small-Outline Leadlsaa Chip Carrier
(SOLCC)
HJ Small-Outline J-Lead (SOJ)
HR Fialpack
JD Side-Brazed Dual-in-Une
Military
M - 55·C to 125·C
~.TEXAS
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1-5
General Information
Standard DRAM Module Ordering Information
Orders forthe standard DRAM Modules described in this book should include a seven-part number as explained
in the fOllowing example:
TM
1. Prefix: _ _ _- - - - - - - - - - ' ,
TM
Commercial TI MOS Module
2. Memory
024
E
NJ
9
-10
I
Device:-------------'
024
4100
18100
1 Meg DRAM. Enhanc8d Pege Mode
4 Meg DRAM. Enhanced Pege Mode
18 Meg DRAM. Enhanced Pege Mode
3. Pinout Configuratlon: - - - - - - - - - - - - - - '
E
G
4. Boerd Dimensions: - - - - - - - - - - - . . . ; . . . . . - - - - - '
NJ
BD
5. Word Width Output
8
.. 8
.9
.. 9
Oeslgnator:------------------------'
8. Speed
-SO SOns
-70 70ns
-SO SOns
-10 100 ns
7. Temperature Range: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----J
Blank o·e to 70·e
l.
O·C to 70·C (1 Meg only)
~ThxAs
1-8
.
INSTRUMENTS
POST OFFICE BOX 1443 •. HOUSTON. TEXAS 77001
General Information
Differentiated DRAM Module Ordering Information
Orders for the mixed DRAM Modules described in this book should include an eight-part number as explained
in the following example:
TM
1. Prefix: _ _ _ _ _ _ _ _ _ _...J1
124
E
AO
9
B
Commercial TI MOS Module
TM
2. Density: - - - - - - - - - - - -....
4 Meg
256 256K
496
512K
512
497
4 Meg - 2K Refresh
892
124
1 Meg
8 Meg
2 Meg
893
8 Meg - 2K Refresh
248
3. Pinout Configurelion: - - - - - - - - - - - - - '
B
G
M
C
K
T
E
l
V
4. Board Dimensions: _ _ _ _ _ _ _ _ _ _ _ _ _ _...J
U
AD
BK
BM
5. Word Width O u t p u t : - - - - - - - - - - - - - - - - - - '
8
.. 8
9
.. 9
32
.. 32
36
.. 36
40
.. 40
6. Devices U s e d : - - - - - - - - - - - - - - - - - - - - - - - I
Blenk 8 - '44400s ('124BBK32)
Blank 9-('4100EAD9)
A
2 - '444OOs ('124GU8A)
B
2 - '44400s + 1 '401024 ('124EAU9B)
8 - '44400s + 1 '44480 ('124MBK36B)
B
B
16 - '444008 + 2 '444608 ('248NBK36B)
C
8 - '44400s + 2 '444608 ('124MBK36C)
C
16 - '44400s + 4 '444808 (,124NBK36C)
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1-7
General Information
EPROM, FLASH,OTP Ordering Information.
Orders for EPROMs, OTPs, and Flash Memories described In this book should Include a nine-part number as
explained In the following example:
TMS
1. Prefbc
TMS
SMJ
I
Commercial MOS
Military MOS
27
I
P
C
512
-10
FM
L
4
2 .. Product Family: - - - - - - - - - - - ' - - - - '
27
EPROM/OTP
28
12-V Flash Memory
29
5-V Flash Memory
P
Blank
Non-erasable (One-Time Programmable)
Erasable
3. Erasabillty: _ _ _ _ _ _ _ _ _ _-'-_ _ _- - l
4. Technology;
C
F
LV
-_----------------1
CMOS
CMOS Flash Mamory
LowVoitage
5. Density: - - - - - - - - - - - ' - - - - - - - - - - - - '
816
16K
010A 1 Meg
128K
210A 1 Meg
128
020
2Meg
256K
256
256K
040
4Meg
257
200
2Meg
512K
510
240
4 Meg
512
400
4Meg
512K
8. Speed Designator: - - - - - - - - - - - - - - - - - - - - - - - - - '
80na
-8,-80
170ns
-'1,-17,-170
100 ns
120 na
150ns
-10, -100
- 12, -120
-1,-15,-150
200ns
250ns
300ns
-2, -20, -200
Blank, - 25, - 250
-30,-300
'
7.P~kag~ ---------------------------~
DO
DU
FM
FN
N
Plastic Thin Small-Outline (TSOP)
Plastic Thin Smail-Outline (TSOP, Reverse Form)
Plastic Chip Carrier (32-Pln) Rectangular
Plastic Chip CarrIer (44-Pin) Square
Ceramic Dual-In-Una (DIP)
Plastic Dual-in-Una (DIP)
PM
Square Quad Flat Package (SQFP)
J
8. Temperature Range:
----------------------------1
Commercial
Military
L
O·Cto 70·C
M
- SS·C to 125·C
E
- 4O"C to 8S·C
Q
-40·Cto 125·C
T
-40·Cto110·C
9. 168 Hour Bum-in Op1ion: - - - - - - - - - - - - - - - - - - - - - - - - - - - '
Commercial
Military
4
168 Hour Bum-In
Blank
5004 Processing
Blank No Bum-in
~1ExAs
1-8
INSTRUMENTS
POST OFFICE lOX 1443 •
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General Information
VRAM Ordering Information
Orders for 4 Meg VRAMs described in this book should include an eight-part number as explained in the
following example:
TMS
1. Prefix: - - - - - - - - - ' 1
TMS
Commercial MOS
SMJ
Military MOS
5
5
16
5
-80
DGH
I
2. Product Family: - - - - - - - - - - '
5
VRAM
3. Density
Refresh: _ _ _ _ _ _ _ _ _ _..J
4
4 Meg
1KRefresh
5
4 Meg
512 Cycle Refresh
16
16 Meg
4KRefresh
17
16 Meg
2KRefresh
4. Organization
Features:
40
" 4
Standard
41
" 4
Enhanced Page Mode
80
" 8
Standard
81
" 8
Enhanced Page Mode
16
,,16
Standard
17
,,16
Enhanced Page Mode
5. Functional Mode Options: - - - - - - - - - - - - - - - - '
o
Enhanced Page Mode
1
Hyper Page Mode
5
Enhanced Page Mode
6
Hyper Page Mode
6. Speed Designator: - - - - - - - - - - - - - - - - - - - - - - - '
-60
60 ns
·70
70 ns
-60
80 ns
·10
100 ns
7. Package: - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
DGH
Super Small·Outline (SSOP)
8. Temperature Range: - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
. Military
Commercial
Blank
O·C to 70·C
M
- 55·C to 125·C
~TEXAS
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1·9
General Information
~TEXAS
INSTRUMENTS
1-10
POST OFFICE BOX 1443 •
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2-1
~1ExAs
:2-2
INSlRUMENTS
POST OFFICE BOX 1448 •
HOUSTON, TEXAS 71001
Selection Guide
DRAM
DENSITY
ORGANlZAnON
(WORDS" BITS)
nilE
MAX POWER
DISSIPATION
POWER
SUPPLY
PACKAoEi'
NOTES
PAOE
18,20,
20/28
HJ,FQ,
HL,JD,
HK,SV
MUltary
8-25
20/28
HJ,FQ,
Hl,JD,
HK,SV
MIlitary
8-5
11
24/26
OJ, DGA
CMOS
Enhanced
Page Mode
Quad CAS
4-5
11
24/26
OJ,DGA
CMOS
Enhanced
Page Mode
Quad CAS
4-5
OJ, DGA
CMOS
Enhanced
Page Mode
Low Voltage
Quad CAS
4-5
24/26
OJ, OGA
CMOS
Enhanced
Page Mode
Low Voltage
Quad CAS
4-5
11
20/28
DGADJ
CMOS
Enhanced
Page Mode
4-27
523
468
413
11
20/26
DGA, OJ
CMOS
Enhanced
Page Mode
Low Power
4-27
5:1:10%
468
440
385
22
18,20, HR,JD,
JDB,HL
28
Military
CMOS
Enhanced
Page Mode
8-45
5:1:10%
495 .
440
385
50
Military
CMOS
Enhanced
Page Mode
8-123
AC11VE
STANDBY
(118)
M
1024KlC 1
SMJ4Cl024-80
SMJ4Cl 024-1 00
SMJ4Cl024-12O
SMJ4Cl024-150
80
100
120
150
5:1:10%
256KlC4
SMJ44C256-80
SMJ44C258-1oo
SMJ44C256-12O
SMJ4Cl 024-150
80
100
120
150
5:1:10%
TMS44480-ao*
TMS44480-ro*
TMS44480-ao*
80
70
80
5:1:10%
578
495
440
TMS44460P-ao*
TMS44460P-7O*
TMS44460P-So*
80
70
80
5:1:10%
578
495
440
TMS46480-80*
TMS46480-70*
TMS46480-ao*
80
70
80
5:1:10%
385
330
275
TMS46480P-ao*
TMS46480P-7o*
TMS46480P-So*
80
70
80
5:1:10%
385
330
275
3.6
TMS441 00-80*
TMS441 00-70*
TMS441oo-80*
80
70
80
5:1:10%
523
468
413
TMS441ooP-SO*
TMS44100P-70*
TMS441OOP-80*
80
70
80
5:1:10%
SMJ441oo-80
SMJ441 00-1 0
SMJ441 00-12
80
100
120
SMJ4161ao*
SMJ41816o*
80
70
80
1024K
1024KlC4
4096K
4096Kx 1
16384K
DEVICE NUIIBER
MAX
ACCESS
1024)( 16
(mW)
PINS
(mW)
22
3.6
11
24/26
HKD
tOGA Plastic Thin Small-Outlina-Package (TSOP)
OJ Plastic Small-Outllne J-Lead (SOJ)
FQ Leadless Ceramic Chip Cerrier (Military) (COCC)
HJ CeramiC Smail-Outline J-Lead (Military) (80J)
HK Flatpack (Military)
HKD FIa1pack (Military)
HL Small-Outllne Leadless Ceramic Chip Carrier (Military) (SOlCC)
HR Flatpack (Military)
JD 4OO-MII Ceramic Sidebrazed Dualln-Une Package (Military) (DIP)
JOB 300-m1l Ceramic Side-Brazed Dual In-Una Package (Military) (DIP)
SV Ceramic ZIg-Zag Package (ZIP) (Military)
* Advance Information for product under development by TI
~TEXAS
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2-3
Selection Guide
DRAM (Continued)
DENSITY
ORGANIZATION
(WORDS)( 8IT8)
MAX POWER
DISSIPATION
MAX
ACCESS
TIME
'(ne)
POWER
SUPPLY
(Y)
ACTIVE
STANDBY
(mW)
(mW)
TMS48100-ro*
TMS48100-so*
TMS48100-10*
70
60
100
3.3:0 10%
216
160
144
3.6
TMS48100P-7O*
TMS48100P-ao*
TMS48100P-10*
70
60
100
3.3:010%
216
160
144
TMS44400-60*
TMS44400-70*
TMS44400-80*
60
70
5:010%
495
TMS444OOP-80*
TMS444OOP-70*
TMS44400P-80*
60
70
60
5:010%
SMJ44400-80
SMJ44400-10
SMJ44400-12
60
1'00
120
5:010%
TMS46400-7o*
TMS484OO-6O*
TMS4840Q-1o*
70
60
100
3.3:0 10%
252
218
160
TMS48400P-7o*
TMS484OOP-ao*
TMS484OOP-1o*
70
60
100
3.3:010%
252
218
160
DEVICE NUMBER
PINS
20/26
PACKAGEi'
NOTES
PAGE
DGA, OJ
CMOS
Enhanced
PagE! Mode
Low Voltage
4-27
4-27
3.6
20/26
DGA, OJ
CMOS ,
Enhanced
Page Mode
Low Voltage
Extended
Refresh
} 11
20/26
OJ,DGA
CMOS
Enhanced
Page Mode
4-51
11
20/26
OJ, DGA
CMOS
Enhanced
Page Mode
Low Power
4-51
22
20
HR,JDB,
HL,SV
Military
CMOS
Enhanced
Page Mode
8-65
7.2
20/28
DGA, OJ
CMOS
Enhanced
Page Mode
Low Voltage
4-51
4-51
4096I(x1
1024Kx4
4096K
258Kx 16
550
440
60
550
495
440
466
440
358
70
20/26
DGA, OJ
11
40,
40/44
DGE, DZ
CMOS
Enhanced
Page Mode
4-73
11
40,
40/44
DGE, DZ
CMOS
Enhanced
Page Mode
Low Power
4-73
11
40,
40/44
DGE,DZ
CMOS
Enhanced
Page Mode
"4-93
11
40,
40/44
DGE, DZ
CMOS
Enhanced
Page Mode
Low Power
4-93
860
TMS441 as.:70
TMS44165-80
TMS44165-10
100
TMS44165P-70
TMS44165P-60
TMS44165P-10
70
60
100
5:1:10%
TMS4S160-70
TMS4S1s0-60
TMS4S160-10
70
60
100
5:1: 10%
TMS4S160P-70
TMS4S160P-80
TMS4S160P-10
70
60
100
5:010%
80
7.2
CMOS
Enhanced
Page Mode
Low Voltage
Extended
Refresh
5:010%
578
523
860
578
523
860
770
860
860
770
660
t DGA Plastic Thin Small-Outllne-Package (TSOP)
, ,
DGE Plastic Surface Mount Thin Small-Outllne Package (TSOP)
OJ Plastic Small-Outllne J-Lead (SOJ)
DZ Plastic Small-Outline J-Lead (SOJ)
HL Small-Outline Leadless Ceramic Chip Carrier (Military) (SOLCC)
HR FJatpack (Military)
JDB 300-mil Ceramic Side-Brazed Dualln-Une Package (Military) (DIP)
SV Ceramic ZIg-zag Package (ZIP) (Military)
* ,Advance Information for product under development by TI
~TEXAS '
2-4
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Selection Guld~
DRAM (Continued)
DENSITY
4096K
ORGANIZATION
(WORDS ..
BITS)
256K .. 16
183841< .. 1
16384K
4096K .. 4
DEVICE NUMBER
MAX
ACCESS
TIME
POWER
SUPPLY
MAX POWER
DISSIPATION
PINS
PACKAoEt
NOTES
PAOE
(na)
M
ACTIVE
(mW)
STANDBY
(mW)
TMS45165-7o*
TMS45165-80*
TMS45165-10*
70
80
100
5:1:10"-
880
770
660
11
40,
40/44
DGE,DZ
CMOS
Enhanced
Page Mode
4·115
TMS45165P.7o*
TMS45165P·80*
TMS45165P·10*
70
80
100
5:1:10"-
11
40,
40/44
DGE, DZ
CMOS
Enhanced
Page Mode
Low Power
4-115
SMJ4161(l()..70
SMJ4181(l()..80
70
80
5,010"-
440
385
11
24/28
FNC,HKB
Military
Enhanced
PsgeMode
8-85
TMS418400·60
TMS418400·70
TMS418400-80
60
70
80
5:1:10"-
440
385
330
11
24/26
DGA,OJ
CMOS
Enhanced
Page Mode
4-135
TMS416400P-60
TMS418400p·70
TMS418400P-60
60
70
80
5:1:10"-
11
24/26
DGA, OJ
CMOS
Enhanced
Page Mode
4-135
SMJ418400-60
SMJ418400·70
SMJ418400-60
SMJ4184(l()..10
60
70
80
100
5,010"-
495
440
385
330
11
24/28
FNC,
HKB,SV
Military
Enhanced
PsgeMode
8·105
TMS417400-60
TMS417400·70
TMS417400-60
80
70
80
5:1:10"-
605
550
495
11
24/26
DGA, OJ
CMOS
Enhanced
Page Mode
'4·135
TMS417400P-60
TMS417400P·70
TMS417400p·80
60
70
80
5,010"-
605
550
495
11
24/26
DGA,OJ
CMOS
Enhanced
Page Mode
4-135
TMS42840Q..60§
TMS4284oo-70§
TMS428400-80§
60
70
80
3.3,0 10"-
252
216
180
3.6
24/26
DGA, OJ
CMOS
Enhanced
Page Mode
Low Voltage
4·135
TMS426400P-60§
TMS428400P·70§
TMS426400P-ao§
60
70
80,
3.3,010"-
252
216
180
DGA, OJ
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4·135
880
no
660
440
365
330
3.6
24/26
t DGA Plastic Thin Small-OuUine-Package (TSOP)
DGE
OJ
DZ
FNC
HKB
SV
Plastic Surface Mount Thin Small·Outiine Package (TSOP)
Plastic Small-Outline J·Lead (SOJ)
Plastic Small-Outllne J·Lead (SOJ)
Small-Outllne Leadless Chip Carrier (Military) (SOLCC)
Flatpack (Military)
Ceramic Zig-Zag Package (ZIP) (MII~ry)
* Advance Information for product under deVelopment by TI
§ Product preview documents contain information on products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
2·5
Selection Guide
DRAM (Continued)
MAX
DENSrrv
ORGANlZAnoN
(WORDS" BITS)
MAX POWER
DISSIPATION
POWER
ACCESS
SUPPLY
(M)
M
ACTIVE
STANDBY
(mW)
(mW)
TMS427400-60*
TMS427400-70*
TMS427400-60*
60
70
60
3.3:010%
360
324
288
3.8
TMS427400P-SO*
TMS427400P-70*
TMS427400P-SO*
80
70
60
3.3:0 10%
380
324
288
TMS418160-60*
TMS418180-70*
TMS418160-60*
60
70
60
5:010%
TMS418180P-SO*
TMS418160P-70*
TMS418180P-SO*
60
70
80
5:010%
TMS418160-60*
TMS418180-70*
TMS418180-60*
60
70
80
5:010%
1045
990
935
11
TMS418160P-SO*
TMS418160P-70*
TMS418180P-SO*
60
70
80
5:0 10%
1045
990
935
11
TMS428160-60*
TMS428180-70*
TMS428160-60*
60
70
60
3.3:0 10%
TMS428180P-SO*
TMS428180P-70*
TMS428160P-SO*
80
70
DEV\CENUMBER
TIME
PINS
NOTES
PAGE
OGA,OJ
CMOS
Enhanced
Page Mode
Low Voltage
4-135
DGA, OJ
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4-135
CMOS
Enhanced
PegeMode
4-183
DGE,OZ
CMOS
Enhanced
Page Mode
Low Power
4-183
DGE,OZ
CMOS
Enhanced
Page Mode
4-183
DGE, DZ
CMOS
Enhanced
Page Mode
Low Power
4-183
3.6
42,
DGE,DZ
44/50
CMOS
Enhanced
Page Mode
Low Voltage
4-183
3.8
42,
DGE,OZ
44/50
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4-183
3.8
42,
DGE,OZ
44/50
CMOS
Enhanced
Page Mode
Low Voltage
4-183
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4-183
24/28
PACKAGet
4098K,,4
18384K
1024K,,16
60
70
60
TMS428160P-so*
TMS428160P-7o:1:
TMS428180P-SO*
60
70
80
11
385
495
440
11
385
324
288
252
3.3:0 10%
-80
TMS42818O-6O*
TMS428180-7o:1:
TMS42818O-6O*
495
440
3.8
3.3:010%
324
288
252
864
848
812
3.3:0 10%
884
848
812
3.6
24/28
42,
44/50 DGE,DZ
42,
44/50
42,
44/50
42,
44/50
42,
44/50 DGE, DZ
tOGA Plastic Thin Small-Outbne-Package(TSOP)
DGE Plastic Surface Mount Thin Small-Outllne Package (TSOP)
DJ Plastic Small-Outline J-Lead (SOJ)
OZ Plastic Smail-OuUine J-Lead (SOJ)
.
* Product preview documents contain Information on products In the formative or design phase of development. Characteristic data and other
speclficaUons are design goals. Texas Instruments reserves the right to change or discontinue these products without nob.
~1ExAs
INSTRUMENTS
!'OST OFFICE BOX 1443 • HOUSTON. TEXAS noel
Selection Guide
DRAM (Continued)
MAX
ORGANIZATION
DENSITY (WORDS
x BITS)
18384K
65536K
1024Kx 18
81.92Kx8
ACCESS
nME
(na)
DEVICE NUMBER
MAX POWER
DISSIPATION
POWER
SUPPLY
ACTIVE
M
STANDBY
(mW)
PINS
PACKAOEt
NOTES
PAGE
(mW)
11
42,
44/50
OGE,DZ
CMOS
Enhanced
Page Mode
4-191
495
440
385
11
42,
44/50
DGE,OZ
CMOS
Enhanced
Page Mode
Low Power
4-191
5:1:10%
1045
990
935
11
42,
44/50
DGE,OZ
CMOS
Enhanced
Page Mode
4-191
60
70
80
5:1: 10%
1045
990
935
11
42,
44/50
DGE,DZ
CMOS
Enhanced
Page Mode
Low Power
4-191
TMS426169-80*
TMS426189-70*
TMS426169-80*
80
70
80
3.3:1:10%
288
3.6
42,
44/50
OGE,OZ
TMS426169P-SO*
TMS426169P-70*
TMS426169P-SO*
80
70
80
3.3:1: 10%
324
288
252
3.6
42,
44/50
DGE,DZ
TMS426189-8O:1:
TMS428189-7o:t:
TMS428169-8o:t:
80
70
80
3.3:1:10%
884
848
812
3.6
42,
44/50
OGE,OZ
CMOS
Enhanced
Page Mode
Low Voltage
4-191
TMS428169P-80*
TMS428169P-7o:t:
TMS428169P-ao:t:
80
70
80
3.3:1: 10%
884
848
612
3.6
42,
44/50
DGE,DZ
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4-191
TMS464800-5o:t:
TMS484800-8o:t:
TMS484800-7o:t:
TMS484800-8o:t:
50
80
70
80
3.3:1:10%
504
432
396
380
7.2
32
OZ,
OGC
CMOS
Enhanced
Page Mode
Low Voltage
4-187
TMS464800P-So:t:
TMS464800P-ao:t:
TMS464800P-7o:t:
TMS464800P-ao:t:
50
80
70
80
3.3:1:10%
504
432
396
380
32
DGC,
DZ
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4-187
TMS418169-80*
TMS418169-70*
TMS416169-80*
80
70
80
5:1:10%
495
TMS416169P-80*
TMS418169P-70*
TMS418169P-80*
80
70
80
5:1:10%
TMS418169-80*
TMS418189-70*
TMS418169-80*
80
70
80
TMS418169P-SO*
TMS418169P-70*
TMS418169P-80*
440
385
324
252
7.2
CMOS
Enhanced
Page Mode
Low Voltage
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4-191
4-191
t DGCPlastic ThIn Smail-Outline Package (TSOP) 4OO-mll (SO-mll pitch)
OGE Plastic Surface Mount Thin Small-Outline Package (TSOP)
DZ Plastic Small-Outllne J-Lead (SOJ)
* Product preview documents contain information on products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue thase products without notice.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
2-7
Selection Guide
DRAM (ContInued)
DENSITY
ORGANlZAnoN
(WORDS" BITS)
4096K .. 18
65536K
183S4K .. 4
DEVICE NUMBEA
MAX
ACCESS
TIME
(na)
POWER
SUPPLY
ACTIVE
STANDBY
(mW)
(mW)
M
PINS
PACKAGEt
504
TMS4641ro-so*
TMS4641~
TMS464180-7o*
TMS484180-60*
50
60
70
60
3.3:t 10%
TMS484180P-so*
TMS484160P-6o*
TMS484160P-70*
TMS484160P-SO*
50
60
70
60
3.3:t 10%
TMS464400-50*
TMS464400-60*
TMS464400-70* '
TMS464400-80*
50
60
70
60
3.3:t 10%
504
432
398
360
TMS464400P-so*
TMS464400P-6o*
TMS464400P-ro*
TMS464400P-6o*
50
60
70
60
3.3:t10%
504
432
396
360
432
396
360
PAGE
7.2
50.
TBD
DGE.
DZ
CMOS
Enhanced
Page Mode
Low Voltage
4-187
7.2
50.
TBD
DGE.
DZ
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4-187
7.2
32
DGC.
DZ
CMOS
Enhanced
Page Mode
Low Voltage
4-187
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4-187
504
432
396
360
NOTES
7.2
32
DGC.
DZ
t DGC Plastic Thin Small-ouUine Package (TSOP) 4OO-mil (SO-mil pitch)
DGE Plastic Surface Mount Thin Small-Outline PllCkage (rSOP)
DZ Plastic Small-Outline J-Lead (SOJ)
* Product preview documenta contain information on products in the formative or design phase of development. Characteristic data and other
sp8clficatlons are design goals. Texas Instrumenta reserves the right to change or discontinue these products without notice.
~TEXAS
2-8
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS nOOl
Selection Guide
SDRAMa
DENSITY
OROANlZA1l0N
(WORDS" BITS)
DEVICE NUMBER
MAX
ACCESS
llME
(na)
(V)
ACTIVE
STANDBY
(mW)
(mW)
3.3~10%
504
466
3.3 ~ 10%
504
466
9
4Mx4
TMS828402-10
TMS828402-12
TMS626402-15
10
12
2Mx8
TMS826802-10
TMS826802-12
TMS826802-15
10
12
16M
MAX POWER
DISSlPAll0N
POWER
SUPPLY
PINS
PACKAoEt
NOTES
PAOE
612
9
3.6
44
DGE
5-3
3.8
44
DGE
5-41
612
t DGE Plastic Surface Mount Thin Smail-OuUlne Package (TSOP)
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
2-9
Selection .Gutde
V1deoRAMa
MAX
DENSITY
10241< .
4098K
ORGANIZATION
(WORDS Ie BITS)
256KIC4
258KIC 18
DEVICE NUMBER
ACCESS
TIME
(na)
POWER
SUPPLY
MAX POWER
DISSIPATION
M
ACTIVE
(mW)
STANDBY
PACKAGEt
NOTES
PAGE
SMJ44C2518-10
SMJ44C2518-12
100
120
5:1:10%
550
495
83
28
HJ,HM,
JD,SV
Military
CMOS
Multlport
VIdeo RAM
8-145
SMJ55161-70
SMJ55161-80
70
80
5:1: 10%
1050
975
825
800
64,68
GB,
HKC
Military
CMOS
Multlport
Video RAM
8-197
SMJ55168-70
SMJ55168-80
70
80
5:1: 10%
1050
975
825
800
64,68
GB,
HKC
Military
CMOS
Multlport
Video RAM
8-259
TMS55180-80
TMS55180-70
TMS55180-80
80
70
80
5:1: 10%
908
880
28
64
DGH
CMOS
Multlport
Video RAM
5-79
TMS55161-80
TMS55161-70
TMS55161-80
80
70
80
5:1:10%
908
880
28
64
DGH
CMOS
Multlport
VIdeo RAM
5-191
TMS56165-80
TMS55165-70
TMS55165-80
80
70
80
6:1: 10%
908
880
28
64
DGH
CMOS
Multiport
VIdeo RAM
5-135
908
880
28
64
DGH
CMOS
Multlport
Video RAM
5-251
TMS56168-80
60
TMS55168-70
70
5:1: 10%
80
TMS55168-80
t DGH Plastic Super Smail-Outline Package (SSOP)
GB Ceramic Pin Grid Array
HJ Ceramic Small-OuIJlne J-Lead (Military) (SOJ)
HKC 0.5 mm Pitch CeramiC FIatpack (Non-conductive tie bar) (Military)
HM Small-Outllne Leadless Ceramic Chip Carrier (Military) (SOLCC)
JD Ceramic Sidebrazed Dual In-Line Package (MIII1ary) (DIP)
SV Ceramic Zig-Zag Package (ZIP) (Military)
~1ExAs
2-10
PINS
(mW)
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS noo1
Selection Guide
DRAM Module
DENSlTY
ORGANIZATION
(WORDS x BITS)
4M)(S
4M)(9
lM)( 32
4MByte
lM)(36
DEVICE NUMBER
MAX
ACCESS
TIME
POWER
SUPPLY
DIMENSION
LENGHT)( HEIGHT
INCHES
(MILLIMETERS)
PINS
PACKAGE
PAGE
3.5")( O.S"
(88,90 )( 20,32)
30
Single-Sided
Socketable
Solder-Tabbed
S-3
5:1:10%
3.5")( 0.65"
(88,90)( 16,65)
30
Single-Sided
Socketable
Solder-Tabbed
6-9
60
70
80
5:1:10%
3.5")( O.S",
(8S,90 )( 20,32)
30
Single-Sided
Socketable
Solder-Tabbed
8-15
TM497EU9-60
TM497EU9-70
TM497EU9-80
60
70
80
5:1:10%
3.5")( 0.8"
(8S,90 )( 20,32)
30
Single-Sided
Socketable
Solder-Tabbed
S-23
TM124BBK32-60
TM124BBK32-70
TM124BBK32-80
60
70
80
5:1:10%
3.5")( 0.65"
(88,90 )( 16,65)
72
Single-Sided,
Socketable
Gold-Tabbed
8-29
TM124BBK32S-60
TM124BBK32S-70
TM124BBK32S-80
60
70
80
5,.10%
4.25" )( 1.00"
(107,95)( 25,40)
72
Single-Sided
Socketable
Solder-Tabbed
6-29
TM124BBK32F-60
TM124BBK32F-70
TM124BBK32F-80
60
70
80
5,.10%
4.25" )( 1.00"
(107,95)( 25,40)
72
Single-Sided
Socketable
Gold-Tabbed
8-39
TM124BBK32U-60
TM124BBK32U-70
TM124BBK32U-80
60
70
80
5:1:10%
4.25" )( 1.00"
(107,95 )( 25,40)
72
Single-Sided
Socketable
Solder-Tabbed
6-39
TM124MBK36B-60
,TM124MBK36B-70
TM124MBK36B-80
70
5,.10%
4.25" )( 1.00"
(107,95)( 25,40)
72
Single-Sided
Socketable
Gold-Tabbed
6-63
TM124MBK36R-60
TM124MBK36R-70
TM124MBK36R-80
60
70
80
5:1:10%
4.25" )( 1.00"
(107,95)( 25,40)
72
Single-Sided
Socketable
Solder-Tabbed
8-63
TM124MBK36C-60
TM124MBK36C-70
TM124MBK36C-80
60
70
80
5,.10%
4.25" )( 1.00"
(107,95)( 25,40)
72
Single-Sided
Socketable
Gold-Tabbed
6-81
TM124MBK36S-60
TM124MBK36S-70
TM124MBK36S-60
60
70
80
5,.10%
4.25" )( 1.00"
(107,95)( 25,40)
72
Single-Sided
Socketable
Solder-Tabbed
8-S1
TM124MBK36F-60
TM124MBK36F-70
TM124MBK36F-60
80
70
80
5,.10%
4.25" )( 1.00"
(107,95 )( 25,40)
72
Single-Sided
Socketable
Gold-Tabbed
6-73
TM124MBK36U-60
TM124MBK36U-70
TM124MBK36U-80
60
70
80
5,.10%
4.25" )( 1.00"
(107,95)( 25,40)
72
Single-Sided
Socketable
Solder-Tabbed
6-73
TM124MBK36G-60
TM124MBK36G-70
TM124MBK36G-80
60
70
80
5,.10%
4.25" )( 1.00"
(107,95)( 25,40)
72
Single-Sided
Socketable
Gold-Tabbed
6-91
TM124MBK36V-60
TMl24MBK36V-70
TM124MBK36V-80
60
70
80
5:1:10%
4.25" )( 1.00"
(107,95)( 25,40)
72
Single-Sided
Socketable
Solder-Tabbed
8-91
(n.)
M
TM4100GAD8-60
TM4100GAOS-70
TM4100GAOS-80
60
70
80
5:1:10%
TM497GUS-60
TM497GU8-70
TM497GU8-60
60
70
80
TM4100EAD9-60
TM4100EAD9-70
TM4100EAD9-80
80
80
~1ExAs
INSTRUMENTS
POST OFFICE SOX 1443 •
HOUSTON, TEXAS 77001
2-11
Selection Guide
DRAM Module (continued)
DENSIlY
ORGANIZATION
(WORDS .. BITS)
MAX
ACCESS
DEVICE NUMBER
TIME
(lIS)
TM248CBK32-60
2M .. 36
PACKAGE
PAGE
4.25" .. 1.00(107,95 .. 25,40)
72
Double-Slded
Socketable
Gold-Tabbed
8-29
TM248CBK32S-60
TM248CBK32S-70
TM248CBK32S-60
60
70
80
5:1:10%
4.25" .. 1.00"
(107,95 x 25,40)
72
Double-Sided
Socketable
Solder-Tabbed
6-29
TM248CBK32F-60
TM248CBK32F-70
TM248CBK32F-80
60
70
60
5:1:10%
4.25" x 1.00(107,95 .. 25,40)
72
Double-Sided
Socketable
Gold-Tabbed
8-39
TM248CBK32U-60
TM248CBK32U-70
TM248CBK32U-80
60
70
60
5:1:10%
4.25" x 1.00(107,95 .. 25,40)
72
Double-Slded
Socketable
Solder-Tabbed
8-39
TM248NBK36B-60
TM248NBK36B-70
TM248NBK36B-60
60
70
80
5:1:10%
4.25" .. 1.00·
(107,95 x 25,40)
72
Double-Slded
Socketable
Gold-Tabbed
8-63
TM248NBK36R-80
TM248NBK36R-70
TM248NBK36R-80
60
70
80
5:1:10%
4.25" .. 1.00(107,95 x 25,40)
72
Double-Sided
Socketable
Solder-Tabbed
8-63
TM248NBK36C-60
TM248NBK36C-70
TM248NBK36C-80
80
70
80
5:1:10%
4.25" .. 1.00·
(107,95 x 25,40)
72
Double-Slded
Socketable
Gold-Tabbed
6-81
TM248NBK36S-60
TM248NBK36S-70
TM248NBK36S-60
80
70
80
5:1:10%
4.25" .. 1.00(107,95 x 25,40)
72
Double-Sided
Socketable
Solder-Tabbed
6-81
TM248NBK36F-60
TM248NBK36F-70
TM248NBK36F-80
80
70
80
5:1:10%
4.25" .. 1.00(107,95 .. 25,40)
72
Double-Slded
Socketable
Solder-Tabbed
6-73
TM248NBK36U-60
TM248NBK36U-70
TM248NBK36U-80
70
80
5:1:10%
4.25" x 1.00(107,95 x 25,40)
72
Double-Sided
Socketable
Solder-Tabbed
6-73
TM248NBK36G-80
TM248NBK36G-70
TM248NBK36G"()
70
80
5:1:10%
4.25" x 1.00·
(107,95 x 25,40)
72
Double-Sided
Socketable
Solder-Tabbed
8-91
5:1:10%
4.25" x 1.00"
(107,95 .. 25,40)
72
Double-Sided
Socketable
Solder-Tabbed
8-91
I
60
60
TM248NBK36V-60
TM248NBK36V-70
TM248NBK36V-80
60
70
80
~1ExAs
2-12
PINS
5:1:10%
TM248CBK32-80
8MByte
(Y)
DIMENSION
LENGHT .. HEIGHT
INCHES
(MIWMETERS)
60
70
60
TM2~BK32-70
2M .. 32
POWER
SUPPLY
INSTRUMENTS
POST OFFICE
sox 1443
•
HOUSTON. TEXAS 77001
Selection Guide
DRAM Module (Concluded)
DENSITY
ORGANIZATION
(WORDS x BITS)
4Mx32
16 MByie
4Mx36
SMx32
32MByie
SMx36
DEVICE NUMBEA
MAX
ACCESS
TIME
POWER
SUPPLY
DIMENSION
LENQHTx HEIGHT
INCHES
(MIWMETERS)
PACKAGE
PAGE
72
Single-Sided
Socketable
Gold-Tabbed
8-47
4.25" x 1.00(107,95 x 25,40)
72
Single-Sided
Socketable
Solder-Tabbed
8-47
5 .. 10%
4.25" x 1.00(107,95 x 25,40)
72
Double-Sided
Socketable
Gold-Tabbed
6-99
80
70
80
5 .. 10%
4.25" x 1.00"
(107,95 x 25,40)
72
Double-Sided
Socketable
Solder-Tabbed
6-99
TM497MBM36A-60
TM497MBM36A-70
TM497MBM36A-60
80
70
80
5 .. 10%
4.25" x 1.25"
(107,95 x 31,75)
72
Single-SIded
Socketable
Gold-Tabbed
6-107
TM497MBM360-60
TM497MBM36Q-70
TM497MBM36Q-80
80
70
80
5 .. 10%
4.25" x 1.25"
(107,95 x 31,75)
72
Single-Sided
Socketable
Solder-Tabbed
8-107
TM893CBK32-60
TMS93CBK32-70
TMS93CBK32-60
60
70
SO
5 .. 10%
4.25" x 1.25"
(107,95 x 31,75)
72
Double-Sided
Socketable
Gold-Tabbed
6-55
TMS93CBK32S-80
TMS93CBK32S-70
TMS93CBK32S-60
80
70
80
5 .. 10%
4.25" x 1.25"
(107,95x 31,75)
72
Double-Slded
Socketable
Solder-Tabbed
6-55
TMS93NBM36A-60
TMS93NBM36A-70
TMS93NBM36A-80
60
70
80
5 .. 10%
4.25" x 1.25" '
(107,95 x 31,75)
72
Double-Sided
Socketable
Gold-Tabbed
8-107
TMS93NBM36Q-80
TMS93NBM36Q-70
TMS93NBM36Q-SO
60
70
80
5 .. 10%
4.25" x 1.25"
(107,95 x 31,75)
72
Double-Sided
Socketable
Solder-Tabbed
6-107
(na)
M
TM497BBK32-60
TM497BBK32-70
TM497BBK32-60
80
70
80
5 .. 10%
4.25" x 1.00"
(107,95 x 25,40)
TM497BBK32S-60
TM497BBK32S-70
TM497BBK32S-60
80
70
80
5 .. 10%
TM497MBK36A-80
TM497MBK36A-70
TM497MBK36A-60
60
70
80
TM497MBK36Q-60
TM497MBK36Q-70
TM497MBK36Q-80
PINS
,:lllExAs
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
2-13
Selection Guide
EPROM
MAX
DENSITY
ORGANIZATION
(WORDS" ami)
DEVICE NUMBER
ACCESS
nME
(/Ie)
16Kxe
256K
512K
I;IJSSIPATIOH
(V)
ACTIVE
STANDBY
(mW)
(mW)
5:1:10%
138
1.7
28
PACKAoet
J
NOTES .
Military
PAGE
8-319
I
250
5:1:10%
165
1.4
2e
J
CMOS
7·143
TMS27C510-12
TMS27C510-15
'TMS27C510-17
TMS27C51 0·20
TMS27C510-25
120
150
170
200
250
5:1:10%
165
1.4
32
J
CMOS
7·155
TMS27C512·10
TMS27C512·12
TMS27C512·15
TMS27C512·2O
TMS27C512·25
100
120
150
200
250
5:1: 10%
165
1.4
2e
J
CMOS
7-167
128Kxe
TMS27C010A-10
TMS27C010A·12
TMS27C010A·15
TMS27C010A·2O
100
120
150
200
5:1: 10%
165
0.65
32
J
CMOS
7·179
64Kx 16
TMS27C210A·10
TMS27C210A·12
TMS27C210A·15
TMS27C210A·2O
TMS27C210A·25
100
120
150
200
250
5:1:10%
165
0.55
40
J
CMOS
7·191
120
150
200
250
5:1:10%
165
0.55
32
J
CMOS
7-201
32Kxe
64Kxe
256Kxe
~TEXAS
2·14
PINS
100
120
150
170
200
250
TMS27C020·12
TMS27C020-15
TMS27C020-2O
TMS27C020-25
Ceramic Dual In·L1ne Package (DIP)
2048K
120
150
170
200
MAX POWER
TMS27C256-10
TMS27C256-12
TMS27C256-15
TMS27C256-17
TMS27C256-2O
TMS27C256-25
1024K
tJ
SMJ27C128-12
SMJ27C128-15
SMJ27C128-17
SMJ27C128-2O
SMJ27C128-25
POWER
SUPPLY
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
Selection Guide
Flash
DENSITY
512K
ORGANIZATION
(WORDS )( BITS)
MAX POWER
DISSIPATION
MAX
ACCESS
TIME
(na)
POWER
SUPPLY
M
ACTIVE
(mW)
STANDBY
(mW)
PINS
PACKAGEt
NOTES
PAGE
64Kx8
TMS28F512A-10
TMS28F512A-12
TMS28F512A-15
TMS28F512A-17
100
120
150
170
5:1:10%
185
.55
32
FM,N,
DD,DU
CMOS
Flash
Memory
7-3
128Kx8
TMS28F010B-90
TMS28F010B-10
TMS28F010B-12
TMS28F010B-15
100
120
150
170
5:1:10%
185
.55
32
DD,DU,
FM
CMOS
Flash
Memory
7-25
64Kx 16
TMS28F210-10
TMS28F21 0-12
TMS28F210-15
TMS28F21 0-17
100
120
150
170
5:1: 10%
275
.55
40,44
FN,J
CMOS
Flash
Memory
7-47
256Kx8
TMS28F02O-10
TMS28F02O-12
TMS28F02O-15
TMS28F020-17
100
120
150
170
5:1:10%
275
.55
32
FM,DD
CMOS
Flash
Memory
7-67
1024K
2048K
4096K
DEVICE NUMBER
256Kx 80r
128Kx 16
TMS28F200x-so*
TMS28F2OOx-70*
TMS28F200x-80*
TMS28F200x-90*
60
70
80
90
5:1:5%
5:1: 10%
5:1: 10%
5:1:10%
358
.55
44,56
DBJ,DBR
CMOS
Boot-Block
Flash
Memory
7-87
517Kx8or
256Kx 16
TMS28F4OOx-SO*
TMS28F4OOx-70*
TMS28F4OOx-80*
TMS28F4OOx-90*
80
70
80
90
5:1:5%
5:1:10%
5:1:10%
5:1:10%
358
.55
44,56
DBJ,DBR
CMOSBoot-Block
Flash
Memory
7-115 .
t DBJ Plastic Small-Outline Package
DBR Plastic Small-Outline Package
DO Plastic Thin Small-OuUlne Package
DU Plastic Thin Smail-Outline Reverse Form Package
FM Plastic Lsaded Chip Carrier
FN Plastic Lsaded Chip carrier
J
Ceramic Dualln-Une Package (DIP)
N
Plastic Dualln-Une Package (DIP)
* Advance Information for product under development by TI
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 10M3 •
HOUSTON. TEXAS ncol
2-15
Selection Guide
EPROM
DENSITY
ORGANIZATION
(WORDS" BITS)
512K"S
4096K
256Kx 16
tJ
D£VICENUMBER
MAX
ACCESS
TIME
(ne)
POWER
SUPPLY
M
ACTIVE STANDBY
(mW)
(mW)
PINS
PACKAoEt
NOTES
PAOE
TMS27C040-10
TMS27C040-12
TMs27C040-15
100
120
150
5:010%
275
0.55
32
J
CMOS
7-211
SMJ27C04O-10
SMJ27C04O-12
SMJ27C040-15
100
120
150
5:010%
275
0.55
32
J
Military
S-331
TMS27C240-10
TMS27C240-12
TMS27C240-15
100
120
150
5:010%
275
0.55
40
J
CMOS
7-221
Ceramic Dualln-Une Package (DIP)
~1ExAs.
2-16
MAX POWER
DISSIPATION
.
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
Selection Guide
One-TIme Programmable (OTP) PROM
DENSITY
256K
512K
ORGANIZATION
(WORDS x BITS)
DU
FM
FN
N
POWER
SUPPLY
MAX POWER
DISSIPATION
PINS
PACKAGEt
NOTES
PAGE
M
ACTIVE
STANDBY
(mW)
(mW)
TMS27PC256-10
TMS27PC256-15
TMS27PC256-17
TMS27PC256-2O
TMS27PC256-25
100
150
170
200
250
5:t:l0%
185
1.4
28,32
FM,N
CMOS
7-143
TMS27PC51 0-15
TMS27PC51 0-17
TMS27PC51 0-20
TMS27PC510-25
150
170
200
250
5:t:10%
165
1.4
32
FM,N
CMOS
7-155
TMS27PC512-10
TMS27PC512-12
TMS27PC512-15
TMS27PC512-2O
TMS27PC512-25
100
120
150
200
250
5:t:l0%
165
1.4
28,32
DD,DU,
FM,N
CMOS
7-167
128Kx8
TMS27PC010A-12
TMS27PC010A-15
TMS27PC010A-2O
120
150
200
5:t:l0%
165
0.55
32
DD,DU,
FM,N
CMOS
7-179
64Kx16
TMS27PC210A-12
TMS27PC210A-15
TMS27PC210A-2O
TMS27PC210A-25
120
150
200
250
5:t:10%
165
0.55
44
FN
CMOS
7-191
256Kx8
TMS27PC020-12
TMS27PC020-15
TMS27PC02O-2O
TMS27PC020-25
120
150
200
250
5:t:l0%
165
0.55
32
FM
CMOS
7-201
512Kx8
TMS27PC040-10
TMS27PC040-12
TMS27PC04G-15
100
120
150
5:t:10%
275
0.55
32
FM
CMOS
7-211
256Kx 16
TMS27PC240-10
TMS27PC240-12
TMS27PC240-15
100
120
150
5:t:l0%
275
0.55
44
FN
CMOS
7-221
32Kx8
64Kx8
4098K
t DO
MAX
ACCESS
TIME
(ns)
1024K
2048K
DEVICE NUMBER
Plastic Thin Smail-Outline Package
Plastic Thin Small-Outline Reverse Form Package
Plastic Leaded Chip Carrier
Plastic Leaded Chip Carrier
Plastic Dualln-Une Package (DIP)
~TEXAS
.
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS· noo1
2-17
Selection Guide
c
2-18
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
IDefinition of Terms
3-1
~1ExAs
3-2
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
Definition of Terms/Tlmlng Conventions
GENERAL CONCEPTS AND TYPES OF MEMORIES
Address - Any given memory location in which data can be stored or from which it can be retrieved.
Automatic Chlp·Select/Power Down - see Chip Enable Input.
Blt-Contraction of binary digit i.e., a 1 or a O. In electrical terms, the value of a bit can be represented by the presence
or absence of charge, voltage, or current.
Byte -A word of eight bits (see Word).
C of C - Certification of Conformance.
CQIP - Ceramic Dual In-Une Package.
CERPAC - CERamic flat PACk (hermetic).
CMOS - A complementary MOS technology that uses transistors with electron (N-channel) and hole (P-channel)
conduction.
Chip Enable Input - A control input to an integrated circuit that, when active, permits operation of the integrated
circuit for input, internal transfer, manipulation, refreshing, and/or output of data and, when inactive, causes the
integrated circuit to be in a reduced-power standby mode.
Chip Select Input - Chip select inputs are gating inputs that control the input to, and output from, the memory. They
may be of two kinds:
1. Synchronous - Clocked/latched with the memory clock. Affects the inputs and outputs for the duration
of that memory cycle.
2. Asynchronous - Has direct asynchronous control of inputs and outputs. In the read mode, an
asynchronous chip select functions like an output enable.
'
Column Address Strobe (CAS) - A clock used in dynamiC RAMs to control the input of column addresses. It can
be active high (CAS) or active low (CAS).
Data - Any information stored or retrieved from a memory device.
Ole - Unpackaged semiconductor.
DIP - Dual In-line Package.
DESC - Defense Electronics Supply Center.
Dynamic (Read/Wrlte) Memory (DRAM) - A read/Write memory in which the cells require the repetitive application
of control signals in order to retain the stored data.
NOTES:
1. The words "read/Write· can be omitted from the term when no misunderstanding will result.
2. Such repetitive application of the control signals is normally called a refresh operation.
3. A dynamic memory might use static addressing or sensing circuits.
4. This definition applies whether the control signals are generated inside or outside the integrated circuit.
EPIC'" - Enhanced Performance Implanted CMOS.
Erasable and Programmable Read-Only Memory (EPROM) - A field-programmable read-only memory that can
have the data content of each memory cell altered more than once.
EPIC Is a trademark of Texas Instruments InCOrporated.
-!!11ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
3-3
Definition of TermS/Timing Conventions
Erase - Typically associated with .EPROMs and Flash' Memories. The procedure whereby programmed data Is
removed and the device returns to its unprogrammed state.
ESD - Electrostatic Discharge.
Extended Data Output - Extended data out allows for data output rates of up to 40 MHz for 60 ns devices. When
keeping the same row address while selecting random column addresses; the time for row-address setup and
hold and address multiplex Is eliminated. The maximum number of columns that can be accessed is determined
by tRASP, the maximum RAS low time.
.
Extended data out does not enter the DQs into the h~h-impedancie state with the rising edge of CAS. The ~
remains valid for the system to latch the data. After AS goes high, the DRAM is decoding the next address. OE
and WE can be used to control the output impedance. Descriptions of OE and WE further explains EDO operation
benefit.
Field Memory (FMEM) - A serial-access memory that performs high-speed, asynchronous read/Wrlte operations.
(Used mainly for fields of digital 1VNTR that require higher speed operation,lower power consumption, and larger
capacity.)
Field-Programmable Read-Only Memory - See One-Time Programmable Read-Only Memory.
FIFO - First-In, First-Out.
Fit - A failure rate of one failure in one billion hours.
Fixed Memory-A common term for ROMs, EPROMs, EEPROMs, etc., Containing data that Is not normally changed.
A more precise term for EPROMs and EEPROMs is nonvolatile since their data can be easily changed.
Flash Memory - A nonvolatile memory that can be field1rogrammed like an OTP PROM or EPROM but that can
be electrically erased by a combination of electrical signals at its inputs.
FRAM - First-in first-out pseudo-static RAM or Field RAM.
Fully Static RAM -In a fully static RAM, the periphery as well.as the memory array is fully static. The periphery is
thus always active and ready to respond to input changes without the need of clocks. There is no precharge
required for static periphery.
GENERIC DATA - Group A,
e, C, &D Quality Conformance Data.
JAN - Joint Army Navy. Specifically, a JM3851 0 qualified device.
JANB - Class e screened JAN device.
JANS - Class S screened JAN device.
JEE?EC - Joint Electronic Device Engineering Council.
JTAG - Joint Test Action Group.
K - When used In the context of specifying a given number of bits of information, 1K
64K =64 )( 1024 =65 536 bits.
=210 =1024 bits. Thus,
Mask-Programmed Read-Only Memory- A read-only memory in which the data content of each cell Is determined
during manufacture by the use of a mask, the data content thereafter being unalterable.
Memory - A medium capable of storing information that can be retrieved.
Memory Card - A pocket-size memory storage system.
~TEXAS
INSTRUMENTS
. POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
Definition of TermsJTlmlng Conventions
Memory Cell- The smallest subdivision of a memory into which a unit of data has been or can be entered, in which
it is or can be stored, and from which it can be retrieved.
Metal-Oxide Semiconductor (MOS) - The technology involving photolithographic layering of metal and oxide to
produce a semiconductor device.
MIL-M-38510 - A military controlling specification pertaining mainly to JAN-qualified devices (microcircuits).
MIL-STD-883 - A military controlling speCification containing detailed descriptions of the screening processes
pertaining to Class B and Class S devices (microcircuits).
NMOS - A type of MOS technology In which the basic conduction mechanism is govemed by electrons. (Short for
N-channel MOS.)
Nonvolatile Memory - A memory in which the data content is maintained whether the power supply is connected
or not.
OTP - One-lime Programmable.
One-Time Programmable (OTP) Read-Only Memory - A read-only memory that, after being manufactured, can
have the data content of each memory cell altered once. Also referred to as OTP.
Output Enable - A control input that, when true, permits data to appear at the memory output, and when false, causes
the output to assume a high-impedance state. (See also chip select.)
PCMCIA - Personal Computer Memory Card Intemational Association.
PDIP - Plastic Dual-Inline Package.
PLCC - Plastic Leaded Chip Carrier.
PMOS - A type of MOS technology in which the basic conduction mechanism is govemed by holes. (Short for
P-channel MOS.)
Parallel Access - A feature of a memory by which all the bits of a byte or word are entered simultaneously at several
inputs or retrieved simultaneously from several outputs.
Power Down - A mode of a memory during which the device Is operating in a low-power or standby mode. Normally
read or write operations of the memory are not possible under this condition.
Program - Typically associated with EPROM and OTP memories, the procedure whereby logical OS (or 18) are stored
into various desired locations in a previously erased device.
Program Enable - An input signal that, when true, puts a programmable memory device into the program mode.
Programmable Read-Only Memory (pROM) - See One-lime Programmable (OTP) Read-Only Memory.
Printed Wiring Board (PWB) - A substrate of epoxy glass, clad material, or other material upon which a pattem of
conductive traces is formed to Interconnect the components that are mounted upon it.
Read - A memory operation whereby data Is output from a desired address location.
Read-Only Memory (ROM) - A memory in which the contents are not Intended to be altered during normal operation.
NOTE: Unless otherwise qualified, the term ·read-only memory" Implies that the contents are determined by its
structure and are unalterable.
ReadlWrlte Memory - A memory in which each cell may be selected by applying appropriate electrical input signals
and the stored data may be either (a) sensed at appropriate output terminals, or (b) changed in response to other
similar electrical input signals.
Row Addr••• Strobe (RAS) - A clock used In dynamic RAMs to control the Input of the row addresses. It can be
active high (RAS) or active low (RAS).
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
3-5
Definition of Termsmmlng Conventions
SCD - Source Control Drawings.
Scaled-MOS (SMOS) - MOS technology under which the device is scaled down in size in three dimensions and in
operating voltages allowing for improved performance.
SDRAM - Synchronous Dynamic Random Access Memory. SDRAM synchronizes all address, data and control
signals with the system clock. This makes the data transfer rates much higher than can be attained with
asynchronous data. System design will be mada easier with timing relationships now similar to other system
operations.'
.
Seml-8tatlc (Quasl-8tat1c, Pseudo-Static) RAM - In a semi-static RAM, the periphery is clock-activated (i.e.,
dYnamic). Thus the periphery is inactive until clocked, and only one memory cycle is permitted per clock. The
peripheral circuitry must be allowed to reset after each active memory cycle for a minimum precharge time. No
refresh is required.
Serial Access - A feature of a memory by which all the bits. are entered sequentially at a single input or retrieved
sequentially from a single output.
SIMM - Single In-Une Memory Module.
Small Outline Integrated Circuit (SOIC) - A package in which an integrated circuit chip can be mounted to form
a surface-mounted component. .It is made of a plastic material that can withstand high temperatures and has leads
formed In a gull-wing shape along its two longer sides for connection to a PWB footprint.
SMD - Standard Military Drawing.
SOlCC - Small Outline Leadless Ceramic Chip Carrier.
SOJ - Small Outline J-Iead package.
SOP - Small Outline Package.
SQFP"- Small Quad Flat Pack.
Static RAM (SRAM) - A read/Write random-access ,device within which information is stored as latched voltage
levels. The memory cell Is a static latch that retains data as long as power Is applied to the memory array. No
refresh is required. The type of periphery circuitry sub-categorizes static RAMs.
.
ThlnSOJ - (TSOJ) Thin Small-Outline J-Lead package.
ThlnSOP - (TSOP) Thin Small-Outline package .
.Very-Larg.Scale Integration (VLSI) - The description of an IC technology that is much more complex than largescale integration (LSI) and involves a much higher equivalent gate count. At this time an exact definition Including
a minimum gate count has not been standardized by JEDEC or the IEEE.
Video RAM (VRAM) - A dual-port dynamic random-access memory with an on-chip serial data register.
Volatile Memory - A memory in which the data content Is lost when the power supply is disconnected.
Word - A series of one or more bits that occupy a given address location and then can be stored and retrieved in
parallel.
Write - A memory operation whereby data is written into a desired address location.
Write Enable - A control signal that when true causes the memory to assume the write mode, and when false causes
it to assume the read mode.
ZIP - Zig-zag In-line Package.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lSCAS 77261-1443
Definition of Terms/Tlmlng Conventions
OPERATING CONDITIONS AND CHARACTERISTICS (INCLUDING LETTER SYMBOLS)
CapaCitance
The inherent capacitance on every pin, which can vary with various inputs and outputs.
Example symbology:
C,
Co
CI(D)
Input capacitance
Output capacitance
Input capacitance, data input
Current
High-level Input current, IIH
The current into an input when a high-level voltage is applied to that input.
High-level output current, 10H
The current into· an output with input conditions applied that, according to the product specification, establishes
a high level at the output.
Low-level Input current, IlL
The current into an input when a low-level voltage is applied to that input.
Low-level output current, 10L
The current into· an output with input conditions applied that, according to the product specification, establishes
a low level at the output.
Off-state (hIgh-Impedance state) output current (of a three-state output,) loz
The current into· an output having three-state capability with input conditions applied that according to the product
specification establishes the high~impedance state at the output.
Short-cIrcuit output current, los
The current into· an output when the output is short-circuited to ground (or other specified potential) with Input
conditions applied to establish the output logic level farthest from ground potential (or other specified potential).
Supply current, IBB, ICC, 100, Ipp
The current into, respectively, the VBB, Vee, VDD, Vpp supply terminals.
*Current out of a terminal is given as a negative value.
Operating Free-Air Temperature
The temperature (TA> range over which the device operates and the range which meets the specified electrical
characteristics.
Voltage
High-level Input voltage, VIH
An input voltage within the more positive (less negative) of the two ranges of values used to represent the binary
variables.
NOTE:
A minimum is specified that is the least positive value of high-level input voltage for which
of the logiC element within specification limits is guaranteed.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
3-7
Definition qf, Termsmming Conventions
High-level output voltage, VOH '
The voltage at an output terminal with input conditions applied that, according to the product specification,
establishes a high level at the output.
Low-level Input voltage, VIL
An Input voltage level within the less positive (more negative) of the two ranges ofvalues Is used to represent
the binary variables.
NOTE:
The most positive value of low-level input voltage Is speCified for which operation of the logic element
within specification limits is guaranteed.
Low-level output voltage. VOL
The voltage at an output terminal with input conditions applied that, according to the product specification,
establishes a low level at the output.
Supply voltages. Vee. Vee. voo. Vpp
The voltages supplied to the corresponding voltage pins that are required for the device to function. From one
to four of these supplies may be necessary, along with ground (VSS).
TIme Intervals
New or revised data sheets in this book use letter symbols in accordance with standards recentiy adopted by
JEDEC, the IEEE, and the IEC. Two basic forms are used. The first form is usually used when intervals can be
easily classified as access, cycle, disable, enable, hold, refresh, setup, transition, or valid times and for pulse
durations. The second form can be used generally, but in this book primarily, for time Intervals not' easily
classifiable. The second (unclassified) form is described first. Since some manufacturers use this form for all time
intervals, symbols in the unclassified form are given with the examples for most of the classified time intervals.
Unclassified time Intervals
Generalized letter symbols can be used to identify almost any time interval without classifying it using traditional
or contrived definitions. Symbols for unclassified time intervals identify two signal events listed in from-to
sequence using the format:
tAB-CD
Subscripts A and C indicate the names of the signals for which changes of state or level or establishment of state
or level constitute signal events assumed to occur first and last, respectively, that is, at the beginning and end
of the time interval. EY!!leffort is made tq keep the A and C subscript length down to one letter, if possible (e.g.,
R for RAS and C for CAS).
Subscripts Band 0 Indicate the direction of the transitions and/or the final states or levels of the signals
represented by A and C, reSpectively. One or two of the following is used:
.
H = high or transition to high
L = low or transition to low
V = a valid steady-state level
X = unknown, changing, or "don't care" level
Z = high-impedance (off) state
The hyphen between the B and C subscripts is omitted when no confusion is likely to occur.
~1ExAs
INSTRUMENTS
3-8
POST OFFlCE BOX 1443 • HOUSTON. TEXAS 77251-1443
Definition of Termsrrlming Conventions
Classified time Intervals (general comments, specific times follow)
Because of the information contained inthe definitions, frequently the identification of one or both of the two signal
events that begin and end the intervals can be significantly shortened compared to the unclassified forms. For
example, it is not necessary to indicate in the symbol that an access time ends with valid data at the output.
However, if both signals are named (e.g., in a hold time), the from-to sequence is maintained.
Access time
The time interval between the application of a specific input pulse and the availability of valid signals at an output.
Example symbology:
Classified
ta(A)
ta(S), ta(CS)
Cycle time
Unclassified
tAVQV
tSLQV
Description
Access time from address
Access time from chip select (low)
The time interval between the start and end of a cycle.
NOTE:
The cycle time is the actual time interval between two signal events and is determined by the system
in which the digital circuit operates. A minimum value is specified that is the shortest interval that must
be allowed for the digital circuit to perform a speCified function (e.g., read, write, etc.) correctly.
Example symbology:
Classified
tc(R), tc(rd)
tc(W)
Unclassified
tAVAV(R)
tAVAV(W)
Description
Read cycle time
Write cycle time
NOTE: R is usually used as the abbreviation for "read"; however, in the case of dynamic memories, "rd" is used
to permit R to stand for RAS.
Disable time (of a three-state output)
The time interval between the specified reference pOints on the input and output voltage waveforms, with the
three-state output changing from either of the defined active levels (high or low) to a high-impedance (off) state.
Example symbology:
Classified
tcJls(S)
tcJls(W)
Unclassified
tSHQZ
twLQZ
Description
Output disable time after chip select (high)
Output disable time after write enable (low)
These symbols supersede the older forms tpvz or tpxz.
Enable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms, with the
three-state output changing from a high-impedance (off) state to either of the defined active levels (high or lOW).
NOTE:
For memories these intervals are often classified as access times.
Example symbology:
Classified
Unclassified
ten(SL)
tSLQV
These symbols supersede the older from tpzv.
Description
Output enable time after chip select low
~TEXAS
.
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
3-9
Definition of Terrnsmmlng Conventions
Hold time
The time Interval during which a signal Is retained at a specified input terminal after an active transition occurs
at another specified input terminal.
NOTES: 1. The hold time Is the actual time interval between two signal events and is determined by the system
In which the digital Circuit operates. A minimum value is specified that is the shortest interval for which
correct operation of the digital circuit Is guaranteed.
2. The hold time can have a negative value In which case the minimum limit defines the longest Interval
(between the release of the signal and the active transition) for which correct operation Of the digital
circuit is guaranteed.
.
Example symbology:
Classified
th(D)
th(RHrd)
th(CHrd)
th(CLCA)
~(RLCA)
th(RA)
Unclassified
twHDX
tRHWH
tcHWH
tcL-CAX
tRL-CAX
tRL-RAX
Description
Data hold time (after write high)
Read (write enable high) hold time after RAS high·
Read (write enable high) hold time after CAS high
Column address hold time after CAS low
Column address hold time after RAS low
Row address hold time (after RAS low)
These last three symbols supersede the older forms:
NEW FORM
~(CLCA)
th(RLCA) .
NOTE:
OLD FORM
th(AC)
th(ARL)
~(AR)
th(RA)
The from-to sequence in the order of subscripts In the unclassified form is maintained in the classified
form. In the case of hold times, this causes the order to seem reversed from what would be suggested
by the terms.
Pulse duration (width)
The time interval between the specified reference points on the leading and trailing edges of the pulse waveform.
Example symbology:
Classified
tw(W)
tw(RL)
Unclassified
twLWH
tRLRH
DescriPtion
Write pulse duration
Pulse duration, RAS low
Refresh tlm,lnterval
The time Interval between the beginnings of successive signals that are intended to restore the level in a dynamic
memory cell to its original level.
NOTE:
The refresh time Interval Is the actual time Interval between two refresh operations and Is determined
by the system In which the digital circuit operates. A maximum value is specified that is the longest
Interval for which correct operation of the digital circuit is guaranteed.
Example symbology:
Classified
trf
Unclassified
DeSCription
Refresh time interval
~TEXAS
3-10
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. leXAB 77281-1443
Definition of TermslTlming Conventions
Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent active
transition at another specified input terminal.
NOTES: 1. The setup time is the actual time interval between two signal events and is determined by the system
in which the diQitaI circuit operates. A minimum value is specified that is the shortest interVal for which
correct operation of the digital circuit is guaranteed.
2. The setup time can have a negative value in which case the minimum limit defines the longest interval
(between the active transition and the application of the other signal) for which correct operation of
the digital circuit is guaranteed.
Example symbolOgy:
Classified
Unclassified
tsu(O)
tOVWH
tsu(CA)
tsu(RA)
tcAV-CL
tRAV-RL
Description
Data setup time (before write high)
Column address setup time (before CAS low)
Row address setup time (before RAS low)
Transition times (also called rise and fall times)
The time interval between two reference points (10% and 90% unless otherwise specified) on the same waveform
that is changing from the defined low level to the defined high level (rise time) or from the defined high level to
the defined low level (fall time).
Example symbology:
Classified
tt
tt(CH)
tr(C)
tf(C)
Unclassified
tCHCH
tcHCH
tcLCL
Description
Transition time (general)
Low-to-high transition time of ~
CAS rise time
CAS fall time
Valid time
(a) General
The time interval during which a signal is (or should be) valid.
(b) Output data-valid time
The time interval in which output data continues to be valid following a change of input conditions that could
cause the output data to change at the end of the interval.
Example symbology:
Classified
ty(A)
Unclassified
tAXQX
Description
Output data valid time after change of address
This supersedes the older form tpvx.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 772li1-1443
3-11
Definition of Termsffiming Conventions
~
- TIMING DIAGRAMS CONVENTIONS
Meaning
Input Forcing Functlona
Output Reaponae Function.
Must be steady high or low
Will be steady high or low
~~
High-to,low changes permitted
Will be changing from high to low sometime
during designated intervals
/////
Low-to-high changes permitted
Will be changing from low to high sometime
during designated intervals
Don't care
Stste unknown or changing
(Does not apply)
Centerline represents high-Impedance
(off) state.
nmlng Diagram Symbol
~TEXAS
INSTRUMENTS .
3-12
POST OFFICE sox 1443 • HOUSTON, TEXAS 77251-1443
Definition of Termsmmlng Conventions
~.1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
3-13
Definition of TermsJTiming Conventions
~1ExAs
3-14
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lEXAS 77251-1443
4-1
--'--~--"-"-'
.......... _.•.
Contents
CHAPTER 4.
TMS44460
TMS44460P
TMS46460
TMS46460P
TMS44100
TMS44100P
TMS46100
TMS46100P
TMS44400
TMS44400P
TMS46400
TMS46400P
TMS44165
TMS44165P
TMS45160
TMS45160P
TMS45165
TMS45165P
TMS416400
TMS416400P
TMS417400
TMS417400P
TMS426400
TMS426400P
TMS427400
TMS427400P
TMS416160
TMS416160P
TMS426160
TMS426160P
TMS418160
TMS418160P
TMS428160
. TMS428160P
TMS464400
TMS464400P
TMS464800
TMS464800P
TMS464160
TMS464160P
DYNAMIC RANDOM-ACCESS MEMORY (DRAM)
4194304-bit
4194304-bit
4194304-bit
4194304-bit
4194304-blt
4194304-bit
4194304-blt
4194304-bit
4194304-blt
4194304-bit
4194304-blt
4194304-bit
4194304-bit
4194304-bit
4194304-bit
4194~blt
4194304-bit
4194304-blt
16777216-bit
16777216-bit
16777216-bit
16777216-bit
16777216-bit
16777216-bit
16777216-bit
16777216-bit
16777216-blt
16777216-bit
16777216-bit
16777216-bit
16777216-bit
16777216-bit
16777216-bit
16777216-bit
67108864-blt
67108864-blt
67108864-bit
67108864-blt
67108864-bit
67108864-bit
(1 024K x 4) Enhanced Page Mode, Quad 'OA§ • . • . . . . . . . . . • . . . • • . .• 4-5
(1 024K x 4) Enhanced Page Mode, Quad 'OA§, Low Power ..•.•..•.• 4-5
(1 024K x 4) low Voltage, Quad ~ . . . . • . . • . . • . . . . . . • . . . . . . . . . . .. 4-5
(1 024K x 4) Low Voltage, Quad 'OA§, Low Power. . . . . . . . . . . . . • . . • •. 4-5
(4096Kx 1) Enhanced Page Mode .....•...•........•......•..•. 4-27
(4096Kx 1) Low Power ........................................ 4-27
(4096Kx 1) Low Voltage ....••..•......•.....••...•..•......... 4-27
(4096Kx 1) Extended Refresh ...•........•....•..............•• 4-27
(1 024K x 4) Enhanced Page mode ......•....................•.• 4-51
(1 024K x 4) Low Power ........................................ 4-51
(1 024K x 4) Low Voltage ...••....•..•..•......•...........•...• 4-51
(1 024K x 4) Extended Refresh .•..••....•••...•................• 4-51
(256K x 16) Enhanced Page Mode .......•....................... 4-73
(256K x 16) Low Power ......................................... 4-73
(256K x 16) Enhanced Page Mode. . . . . . . • . . . . . . . . . . . . . . . . . . . . • .• 4-93
(256K x 16) Low Power ....•.•.•.....•..•.....•......••......... 4-93
(256K x 16) Enhanced Page Mode ....• ; .••...........•......••. 4-115
(256Kx 16) Low Power ........................................ 4-115
(4096K x 4) Enhanced Page Mode ...•......................... 4-135
(4096K x 4) Enhanced Page Mode ............................. 4-135
(4096K x 4) Enhanced Page Mode ............................. 4-135
(4096Kx 4) Enhanced Page Mode ..••......................... 4-135
(4096Kx4) Low Voltage ...................................... 4-135
(4096Kx 4) Low Voltage, Low Power ..•......................•. 4-135
(4096Kx4) Low Voltage ......•....................•.......... 4-135
(4096Kx 4) LowVoltagejLow Power ....•...................... 4-135
(1 024Kx 16) Enhanced Page Mode ............................ 4-163
(1 024Kx 16) Low Power ...................................... 4-163
(1024Kx 16) Low Voltage ..................................... 4-163
(1 024K x 16) Low Voltage, Low Power .......................... 4-163
(1 024K x 16) Enhanced Page Mode ............................ 4-163
(1 024K x 16) Low Power ...................................... 4-163
(1024Kx 16) Low Voltage ..................................... 4-163
(1 024K x 16) Low Voltage, Low Power .........•................ 4-163
(16384K x 4) Enhanced Page Mode ..•......................... 4-187
(16384K)( 4) Enhanced Page Mode, Low Power .............•... 4-187
(8192K x 8) Enhanced Page Mode ............................. 4-187
. (8192K x 8) Enhanced Page Mode, Low Power .••............... 4-187
(4096Kx 16) Enhanced Page Mode ........................ ·...• 4-187
(4096K x 16) Enhanced Page Mode, Low Power ..............•.. 4-187
~1ExAs
INSTRUMENTS
P08T OFFICE BOX 1443 • HOUSTON. 'IEXA8 77211-1443
TMS416169P
TMS418169
TMS418169P
TMS426169
TMS426169P
TMS428169
TMS428169P
16777216·bit
16777216·bit
16777216·bit
16777216·bit
16777216·bit
16777216·bit
16777216·bit
(1 024K x
(1 024K x
(1 024K x
(1 024K x
(1 024K x
(1 024K x
(1 024K x
16)
16)
16)
16)
16)
16)
16)
Extended
Extended
Extended
Extended
Extended
Extended
Extended
Data Out Mode,
Data Out Mode
Data Out Mode,
Data Out Mode,
Data Out Mode,
Data Out Mode,
Data Out Mode,
~TEXAS
INSTRUMENTS
POSTOFFICEB6XI~· HOUSTON. TEXAS77251-1~
Low Power .............•
.........................
Low Power ....•.........
Low Voltage ............•
Low Voltage, Low Power •.
Low Voltage ..........•..
Low Voltage, Low Power ..
4·191
4·191
4·191
4·191
4·191
4·191
4·191
4-4
:lflExAs
INSTRUMENTS
POST OFFICE BOX 1448 • HOUSTON, TEXAS 772S1-1448
TMS44460, TMS44460P, TMS46460, TMS46460P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM·ACCESS MEMORIES
• Organization ••• 1048576 x 4
• Single S-V Power Supply for TMS44460/P
(:t10% Tolerance)
• Single 3.3·V Power Supply for TMS46460/P
(:t10% Tolerance)
• Low Power Dissipation (for TMS46460P)
- 200-JAA CMOS Standby
- 200-JAA Self Refresh
- 300-JAA Extended·Refresh Battery
Backup
• Performance Ranges:
ACCESS ACCESS ACCESS
READ
TIME
TIME
TIME
OR WRITE
(tRAc)
(tAA)
CYCLE
(MAX)
(leAc)
(MAX)
(MAX)
(MIN)
'4x4SO/P-60
SOns
15 ns
30ns
110
'4x460/P-70
'4x460/P-SO
70ns
18 ns
35ns
130ns
80 ns
20 ns
40 ns
150 ns
DQAPACKAGE
(TOPYlEW)
DJPACKAGE
(TOPYlEW)
DQ1 F 1 U
DQ2 1= 2
W1= 3
RAS F 4
CAS 1 5
CAS2 1=6
A9 1=
AO
A1 F
A2 F
AS 1=
Vee F
DQ1 F
DQ2 i=
iN 1=
241= D03
23 F CAS4 RAS F
DE 'CA§1 i=
22
211= CAS3 m2
Vss
28 F
DQ4
251=
NC
191=
18 F
8
9
10
11
12
13
A7
16 F=
15;=
14
AS
AS
A4
261= Vss
25 OQ4
24=
23=
3
4
5
6
DQ3
22=
CAS4
DE
21 =
CAS3
8
9
10
= 11
19=
NC
18=
M
12
15=
14
A9 i=
AO
A1 F
M
17;=
10
2
A2
AS =
VCC =
13
17= A7
16= A6
AS
A4
ns
z
PIN NOMENCLATURE
• Four Separate CASx Pins Provide for
Separate I/O Operation
AO-AS
• Parlty·Mode OperaUon
• Enhanced Page-Mode Operation for Faster
Memory Access
OE
CAS1.,.CAS4
001-004
RAS
Vee
Vss
• CAS·Before·RAS (CBR) Refresh
• Long Refresh Period
- 1024-Cycle Refresh In 16 ms
- 128 ms (Max) Low·Power, Self·Refresh
Version (TMS4x460P)
W
Address Inputs
Column-Address Strobe
Data In/Data Out
Output Enable
Row-Address Strobe
S-V or 3.3-V Supply
Ground
Write Enable
~
is measured from each individual CASx to its corresponding
DOxpin.
To latch in a new column address. all four CASx pins must be brought high. The column precharge time (see
parameter tep) is measured from the last CASx rising edge to the first CASx falling edge of the new cycle. In
order for a column address to remain valid while toggling CASx. there exists a minimum setup time (tcLCH)
where at least one CASx must be brought low before all other CASx pins are taken high.
For early-write~s. the data is latched on the first CASx falling edge. Only the DOs that have the
corresponding CAS)( low are written into. Each CASX has to meet teAS minimum in order to ensure writing into
the storage cell. To latch a new address and new data. all CASx pins must come high and meet tCp.
This DO independence allows the TMS4x460/P to provide four parity bits in memory designs that normally
require the use of four 1-megabit x 1 DRAMs.
~TEXAS
INSTRUMENTS
POSTOFFlCE BOX 1443· HOUSTON, '!eXAS 77251-1443
TMS44460, TMS44460P, TMS46460, TMS46460P
1048576-WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS564A- MARCH 1995 - REVISED JUNE 1995
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by the maximum RAS low time and the CASx
page-cycle time used. With minimum CASx page-cycle time, all 1024 columns specified by column addresses
AO through A9 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CASx is high. The falling edge of
CASx latches the column addresses. This feature allows the TMS4x400 to operate at a higher data bandwidth
than conventional page-mode parts because data retrieval begins as soon as the column address Is valid rather
than when CASx transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after row-address hold time has been satisfied, usually well in
advance of the falling edge of CASx. In this case, data is obtained after tCAC max (access time from CASx low)
if tAA max (access time from Column address) has been satisfied. If column addresses for the next cycle are
valid at the time CASx goes high, access time for the next cycle is determined by the later occurrence of teAC
or tePA (access time from rising edge of CASx).
address (AO-A9)
Twenty address bits are required to decode 1 of 1 048576 storage-cell locations. Ten row-address bits are set
up on inputs AO through A9 and latched onto the chip by the row-address strobe (RAS). The ten column-address
bits are set up on AO through A9 and latched onto the chip by the column-address strobe (CASx). Ail addresses
must be stable on or before the falling edges of RAS and CASx. RAS is similar to a chip enable in that it activates
the sense amplifiers as well as the row decoder. CASx is used as a chip select, activating the output buffer as
well as latching the address bits into the column-address buffer.
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on W selects'the read mode
arid a logic low selects the write mode. W can be driven from standard TTL circuits (TMS44460/P) or low-voltage
TTL circuits (TMS46460/P) without a pullup resistor. The data input is disabled when the read mode is selected.
When W goes low prior to CASx (early write), data out remain in the high-impedance state for the entire cycle,
permitting a write operation independent of the state of OE. This permits early-write operation to be completed
with OE grounded.
data In/out (DQ1-DQ4)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CASx and OE
are brought low. In a read cycle, the output becomes valid after all access times are satisfied. The output remains
valid while CASx and OE are low. CASx or OE going high returns it to a high-impedance state. This is
accomplished by bringing OE high prior to applying data, satisfying tOED,
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and CASx to be brought low for the output buffers to go into the
low-impedance state. They remain in the low-impedance state until either OE or CASx is brought high.
refresh
A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x400P) to retain data. This
can be achieved by strobing each of the 1024 rows (AO-A9). A normal read or write cycle refreshes all bits in
each row that is, selected. A RAS-only operation can be used by holding CASx at the high (inactive) level,
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443 .
4-7
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TMS44480, TMS44460P,·TMS46460, TMS46460P
1048576-WORDBY 4-BIT
DYNAMIC RANDOM~ACCESS MEMORIES
SMHS584A.., MARCH 1986 - REVISED JUNE 1995
refresh (continued)
conserVIng power as the output buffer remains in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh. Hidden refresh can be performed while maintaining valid data at the
output. This Is accomplished by holding CASx at Vil after a read operation and cycling RAS after a specified
precharge period, similar to a RAS-only refresh cycle. The external address Is Ignored during the hidden-refresh
cycle.
CASx·befora~fiAS' refresh (CBR)
CBR refresh is utilized by bringing CASx low earlier than RAS (see parameter leSFU and holding it low after RAS
falls (see parameter tcHFU' For successive CBR refresh cycles, CASx can remain low while cycling RAS. The
external address is ignored and the refresh address is generated internally.
A low-power battery-backup refresh mode that requires less than 300-j.IA (TMS46460P) or 500-j.IA
(TMS44460P) refresh current is available on the low-power devices. Data integrity is maintained using CBR
refresh with a period of 125 !AS while holding RAS low for leSs than 1 !AS. To minimize current consumption, all
Input levels need to be at CMOS levels (Vll S 0.2 V, VIH :2 Vee - 0.2 V).
l>
C
=:;
~
Z
n
m
-Z
"TI
o
s:
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self refresh
The self-refresh mode Is entered by dropping CASx low prior to RAS going low. CASx and RAS are both held
low for a minimum of 100 !AS. The chip is then refreshed by an on-board oscillator. No external address is
required because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and ~ are brought high to satisfy tcHS' Upon exiting the self-refresh mode, a burst refresh (refresh a full set
of row addresses) must be executed before continuing with normal operation. This ensures the DRAM is fully
refreshed.
power up
To achieve proper device operation, an initial pause of 200 !AS followed by a minimum of eight initialization cycles
i~uired after full Vee level is achieved. These eight initialization cycles must include at least one refresh
(RAS-onlyor CBR) cycle.
~
(5
Z
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lEXAS 77261-1443
TMS44460, TMS44460P, TMS46460, TMS46460P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS584A-MARCH 1996-REVISEDJUNE 1896
absolute maximum ratings over operating tree..lr temperature range (unless otherwise noted)t .
Supply voltage range, Vee:
TMS4446Q, TMS44460P ...................•..... -1 V to 7 V
TMS46460, TMS46460P ...................•.. - 0.5 V to 4.6 V
Voltage range on any pin (see Note 1): TMS44460, TMS44460P .........•............•. -1 V to 7 V
TMS46460, TMS46460P ...................... - 0.5 V to 4.6 V
Short-circuit output current .......•.............•.......................•.................. 50 mA
Power dissipation .. ;....................................................................... 1 W
Operating free-air temperature range, TA .............................................. O.DC to 70·C
Storage temperature range, Tsttg ..........................•......••...........•... - 55·C to 150·C
t Stresses beyond those listed under "absolute maximum ratings" may C8U88 permanent damage to the device. These are 8Ir88s ratings only, and
funcUonel operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" Is not
implied. Exposure to absolute-maxlmuin·rated conditions for extended perIocIs may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
'44460/P
'46460/P
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
3.0
3.3
3.8
Vee
Supply voltage
VIH
VIL
Hlgh..Jevallnput voltage
2.4
8.5
2.0
L.ow-IevaIlnput voltage (see Note 2)
-1
0.8
-0.3
TA
Operetlng free..alr temperature
0
70
0
Vcc + 0.3
0.8
70
UNIT
V
V
z
o
~
V
"C
NOTE 2: The algebrelc convention. where the more nagativa (less positive) limit is designated 88 minimum, Is used for logic-voltage levals only.
:&
a:
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~1ExAs
INSTRUMENTS
POST OFFICE sox 1443 • HOUSlON. TEXAS 772S1-1443
4-9
TMS44460, TMS44460P, TMS46460, TMS46460P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
.SMHS584A-' MARCH 1995 - REVISED JUNE 1995
.I.ctrlcal charact.rlstlcs ov.r r.comm.nd.d rang.s of supply voltag. and op.ratlng fr....lr
t.mp.ratur. (unl.ss oth.rwls. not.d)
TMS44460/P
PARAMETER
VOH
High-level
output voltage
IOH=-5mA·
VOL
Low-level output
voltage
IOL=4.2mA
II
Input current
(leakage)
10
ICCl
l>
c
z~
TEST CONDITIONS
o
ICC2
(5
Z
MIN
MIN
MIN
MAX
2.4
2.4
UNIT
MAX
2.4
V
0.4
V
VCC=5.5V,
VI "OVt06.5V,
All others = 0 V to VCC
:1:10
:1:10
:1:10
i.IA
Output current
(leakage)
VCC=5.5V,
C5ASihigh
Vo = 0 Vto VCC,
:1:10
:1:10
:1:10
i.IA
Read- or writecycle Qurrent
(see Note)
VCC =5.5 V,
Minimum cycle
105
90
80
niA
2
·2
2
mA
1
1
1
mA
500
500
500
i.IA
105
90
80
mA
90
80
70
mA
500
500
500
i.IA
5
5
5
mA
500
500
500
i.IA
Standby current
After 1 memory cycle,
RAS and CASx high,
VIH .. VCC - 0.2 V
(CMOS)
'44460
'44460P
ICC3
Minimum cycle,
VCC=5.5V,
RAS cycling,
C5ASi high (RAS only);
RAS low after CASx low (CBR)
ICC4
Average page
current
(see Notes 4
and 5)
VCC=5.5V,
RASlow,
tpc .. minimum,
C5ASi cycling
ICC6 t
Self-refresh
current
(see Note 4)
C5ASi< 0.2 V,
RAS<0.2V,
ICC7
Standby current,
outputs enabled
(see Note 4)
(with CBR)
,
IRAS and teAS> 1000 ms
Battery-backup
ICC10t current
,
RAS"VIH,
CASx =VIL
Data out enabled
IRc =1251'11,
tRAS" 11'11,
Vcc - 0.2 V "VIH ,,6.5 V,
oV" VIL" 0.2 V, iii and OE = VIH,
Address and data stable
t For TMS44460P only
NOTES: 3. ICC max Is specified with no load connected.
4. Measured with a maximum of one address change while RAS .. VIL
5. .Measured with a maximum of one address change while CASx .. VIH
~1ExAs
4-10
MAX
0.4
Average refresh
current
(RASonlyor
CBR)
(see Note 4)
::D
s:
~
'44460·60
'44460P·60
After 1 memory cycle,
RAS and CASx high,
VIH • 2.4 V (TTL)
m
."
'44460·70
'4446OP·70
0.4
o
-z
'44460·60
'44460P·60
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS44460, TMS44460P, TMS46460, TMS46460P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS584A- MARCH 1996 - REVISED JUNE 1995
.I.ctrlcal charact.rlstlcs ov.r recomm.nd.d rang.s of supply voltag. and op.ratlng fr....lr
t.mp.rature (unl.ss oth.rwls. not.d)
TMS46460/P
PARAMETER
TEST CONDInONS
'46480-60
'4648OP-60
'46480-70
'48480P-70
'48480-60
'48480P-60
MIN
MIN
MIN
MAX
2.4
MAX
2.4
UNIT
MAX
2.4
VOH
High-level
output voltage
10H .. - 2 mA (LVTTL)
Low-level output
voltage
10L" 2 mA (LVTTL)
0.4
0.4
0.4
VOL
10L .. 100!iA (LVCMOS)
0.2
0.2
0.2
II
Input current
Oeakage}
VI'" OVto3.9V,
VCC·3.6V,
All others .. 0 V to VCC
:tl0
:tl0
:tl0
!iA
10
Output current
Oeakage)
Vcc = 3.6 V,
CASXhlgh
VO=OVtoVcc,
:tl0
:tl0
:tl0
!iA
ICCl
Read-orwritecycle current
(see-Note)
Vcc = 3.6 V,
Minimum cycle
70
60
50
mA
2
2
2
mA
'46480
300
300
300
!iA
'46480P
200
200
200
!iA
10H .. -100!iA (LVCMOS)
VCC-0.2
After 1 memory cycle,
RAS and CASx high,
VIH .. 2 V (LVTTL)
IC02
Standby current
After 1 memory cycle,
RAS and CASXhlgh,
VIH- VCC- 0•2 V
(LVCMOS)
V
VCC-0.2
VCC-0•2
V
Ices
Average refresh
current
(RASonlyor
CBR)
(see Note 4)
Minimum cycle,
VCC- 3•6 Y,
RAScycling,
CASX high (RAS only);
RAS low after CASX low (CBR)
70
1CC4
Average page
current
(see Notes 4
and 5)
VCC-3.8V,
RASlow.
tpc .. minimum.
CASxcycling
60
50
40
mA
Iccet
Self-refresh
current
CseeNote4)
CASX<0.2V.
-RAS<0.2V.
200
200
200
!iA
1CC7
Standby current.
outputs anabled
(see Note 4)
5
5
5
mA
ICC10t
Battery-backup
current
(with CBR)
300
300
300
!iA
1RAs and teAs > 1000 ma
-RAS.VIH.
CASi"VII
Data out enabled
tRAS" 1148.
tRC" 125 148.
VCC - 0.2 V " VIH " 3.9 V.
OV"VIL,,0.2Y, WandOE =VIH.
Address and data stable
60
50
mA
t For TMS46460P only _
NOTES: 4. ICC max is specified with no load connecled.
4. Measured with a maximum of one address change while RAS - VIL
5. Measured with a maximum of one address change while CASx .. VIH
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
4-11
z
o
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a:
f2
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-w
o
z
c~
ca:
TMS44460, TMS44460P, TMS46460, TMS46460P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS564A- MARCH 1995 - REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-alr temperature,
' . '
f = 1 MHz (see Note 6)
MIN
PARAMETER
MAX
UNIT
CICA)
Input capacitance, NJ-AS
5
pF
CURet
Input capacitance, ~ and RAS"
7
pF
CilOEl
CI(W)
Input capacitance, OE
7
pF
Input capacitance, W
7
pF
Output capacitance
pF
7
Co
NOTE 8: VCC. 5 V ...6 V for the TMS44480/P devices, VCC =3.3 V .. 0.3 V for the TMS48460/P devices, and the bias on Pins under test Is
OV.
switching characteristics over recommended ranges of supply voltage and operating free-air
.
temperature
'4x400·60
'4x400p·60
PARAMETER
»
c
MIN
MAX
'4x400·70
'4x400P·70
MIN
'4x400·60
'4x400p·60
MAX
tM
Access time from column address
z~
teAC
Access time from CASx low
tePA
tRAC
Access time from column precharge
30
15
35
Access time from RAS" low
toEA
Access time from OE low
'-z
teLZ
CASx to output in Iow·impedance state
0
Output dissble time after CASx high (see Note 7)
0
15
0
18
0
15
0
18
n
m
."
o
toFF
toez Output disable time after OE high (see Note 7)
NOTE 7: toFF and toez are specified when the output Is no longer driven.
UNIT
MAX
35
40
18
20
ns
45
ns
80
40
70
80
ns.
15
18
20
ns
0
20
ns·
ns
0
20
ns
0
::D
s::
!io
z
~TEXAS
4-12
MIN
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77261-1443
0
ns
TMS44460, TMS44460P, TMS46460, TMS46460P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS564A-MARCH 1995-REVISEDJUNE 1995
tImIng requIrements over recommended ranges of supply voltage and operatIng free-aIr
temperature
'4x400-60
'4x4OOP-60
'4x400-70
'4x4OOP-70
'4x4oo-80
'4X400P-80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tRC
Cycle time, random read or write (see Note 8)
110
130
150
ns
tRWC
tpc
Cycle time, read-write (see Note 8)
155
181
205
ns
Cycle time, page-mode read or write (see Notes 8 and 9)
40
45
50
ns
tpRWC
Cycle time, page-mode read-write (see Note 8)
85
96
105
ns
tRASP
Pulse duretlon, RAS low, page mode (see Note 10)
60 100000
tRAS
Pulse duration, RAS low, nonpage mode (see Note 10)
60
tRASS
tCAS
Pulse duration, RAS low, self refresh
lOp
Pulse duration, ~ precharge time
10
10
10
ns
40
50
80
ns
110
130
150
ns
10
10
10
ns
10000
70 100000
70
100
Pulse duration, CASx low (see Note 11)
10
10000
10000
80 100000
ns
10000
ns
80
100
18
10000
20
100
j.IS
10000
ns
tRP
Pulse duration, RAS high (precharge)
tRPS
Precharge time after self refresh using RAS
twP
Pulse duretlon, write
tASC
Setup time, column eddress before CASx low
0
0
0
ns
tASR
Setup time, row eddress before RAS low
0
0
0
ns
tos
Setup time, date (see' Note 12)
0
0
0
ns
tRCS
Setup time, W high before CASx low
0
0
ns
tcwL
Setup time, W low before CASx high
15
0
18
20
ns
tRWL
Setup time, Vii low before RAS high
Setup time, Vii low before CASx low
(early-write operation only)
15
18
20
ns
0
0
0
ns
twcs
twsR
Setup time, W high (CBR refresh only)
10
10
10
ns
lOAH
Hold time, column eddress after CASx low
10
15
15
ns
tOHR
Hold time, data after RAS low (see Note 13)
50
55
60
ns
tOH
Hold time, date (see Note 12)
10
15
15
ns
50
55
60
ns
5
5
5
ns
tAR
Hold time, column eddrass after RAS low (see Note 13)
lOLCH
Hold time, CASx low to CASx high
tRAH
Hold time,
row eddress after RAS low
10
10
10
ns
tRCH
Hold time, W high after CASx high (see Note 14)
0
0
0
ns
tRRH
Hold time, W high after RAS high (see Note 14)
0
0
0
ns
twcH
Hold time, W low after CASx low (early-write operation only)
10
15
15
ns
twCR
Hold time, W low after RAS low (see Note 13)
50
55
60
ns
twHR
Hold time, W high (CBR refresh only)
10
10
10
ns
lOHS
Hold time, CASx low after RAS high (self refresh)
-50
-50
-50
ns
18
20
ns
Hold time, OE command
15
toEH
NOTES: 8. All cycle times assume tr .. 5 ns.
9. To assure tpC min, tAsc should, be :t lop.
10. In a read-write cycle, tRWO and tRWL must be observed.
11. In a read-write cycle, lewD and tcwL must be observed.
12. Referenced to the later of CASx or Vii In write operations
13. The minimum value is measured when tRCO is set to tRCO min as a reference.
14. Either tRRH or tRCH must be satisfied for a read cycle.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS n251-1443
4-13
z
o
~
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a::
olL
-w
Z
o
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c~
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______________
1
L-
...
twcsl4
--------~'~ I
VI
II
_
I
I
~
I
I.!II
.
f
D01_"'W.m~
I
pi
I
I
\I
I teAH
I
I
tAR ~ I
~
I
I
I
~j~--~I
I Iof--twCH;r
II
II
_
II
I
I tCWL
I I
IRwL
~
I I
I
twCR I
~
I
twP~
-Hm ~m*~
I
I
tcHR
~tcs-.i
I
~
tcH
NOTES: A. To hold the address latched by the first CASx going low, the parameter tcLCH must be met.
B. CA§ order Is arbitrary.
Figure 3. Early-Wrlte-Cycle Timing (s.. Note B)
~1ExAs
INSTRUMENTS
4-16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
'
TMS44460, TMS44460P, TMS46460, TMS46460P
1048576-WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS584A- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
z
-~
o
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a:
~
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z
~
~
• NOTES: A. To hold the address latched by the first ~ going low. the parameter tcLCH must be met.
B. Referenced to the later of either the first CASx or Vii in write operations.
C. ~ order 18 arbitrary.
Figure 4. Wrlte-cycle Timing (s.. Note C)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOU81ON. n:xAS 77251-1443
4-17
TMS44460, TMS44460P,TMS46460, TMS46460P
1048576-WORD BY4-BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS564A- MARCH 1995 - REVISED J!JNE 1995
PARAMETER MEASUREMENT INFORMATION
NOTES: A. To hold the address latched by the first ~ going low. the parameter tcLCH must be met.
B. tcAC Is measured from ~ to Its corresponding DOx.
C. ~ order Is arbitrary.
Figure 5. Read-Write/Read-Modify-Write-Cycle Timing (see Note C)
~TEXAs
INSTRUMENTS
4-18
POST OF.FICE BOX 1443 • HOUSlON.lEXAs 77261-1443
TMS44460, TMS44460P, TMS46460, TMS46460P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS564A- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
i4
iRP
~
~~-------------iRMP--------------;~
l4-iRCD~
I
I
\l~1___I
I
1
I
I
1,
______~~I----~I
I
I
- - - - -........- - - - , i
~Ii
II
N
I
___-+-+-"'
!
:::=;
I F
i * t~SR Nt-
AO-AS
teM
~
~I
I -I
I I
1
,
1 II
Vi
z
I
III
o
I
I
I
_I
j4-- teAL ~
!i
::E
;~~::~~iRA~L~I~~~~~~~~~
Column
Don't Care
a:
teAH
'V\J'VV'VVVV
~~;t
I
1"1
t..
t
-RCH
I
W1I
I
I
I'I
S.. NotaB I
1
I' j4-- teAC -tt
14---'- tAA ~
I
I
1f-14-----'tRAc ~
I
,.! lAA4
________~I_.--
I
'
--..!!.l!
II
~
iRRH
~~~~~
I
I
I
~ ~.----+I--,._~~I-~~F~F---------
,
DQ3
I I
I
~~
\l
S~----';1~..1~eJr-::iRA=D
DQ1
I 1
I
I..
14
I ~
I ~PC
~¥l4I L~ tep ~
oJ II
, ,
tRC....
Vi
I!
I
;T
-
I
j4--tARM
i I I
I iRAH ~
I
I ~ j4j tMC
I
I
'----""'!I
~A'I teLCH (..a Note A)
I I
teSH
I
I
~
rl_,____~I~I--------II
I
I I
\
~
r'
II
I I
if--teRP
-
I
I
tePA
,
~
(a.. Note
C)
-+I
j.- ~EZ
lpoo-__~I~I
----------+l--~!~ ~~ }~--------------------~0--~1
~,"d ----+1-------teLZI4
~~
I
__
(a.. Nota D)
DQ4
_ _ _ _ _~
(J!l)X '~~ ~ ~~:: »)-_________
~~EA~
\l
I
NOTES: A.
B.
C.
D.
E.
To hold the address latched by the first CASx going low, the parameter tcLCH must be met.
teAC Is measured from CASx to Its corresponding DQx.
'
Access time is tePA or tM dependent.
Output can go from high-impedance to an invalid-clata stete prior to the specified aocess time.
A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the Write and read-modify-write timing
specifications are not violatad.
F. CASx order Is arbitrary.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing (see Notes E and F)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON, TEXAS 77251-1443
4-19
oLL
-ow
Z
z
c~
c
.~
z
o
w~g~n~g~~~
DQ1-DQ4 - - - - - - - - - - - - HI.z - - - - - - - - - - -
m
-z .
cg
Figure 9. RAS-Only Refresh-Cycle nmlng
:lJ
i:
~
(5
z
~1ExAs
4-22
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS44460, TMS44460P, TMS46460, TMS46460P
1048576-WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS~-MARCH1995-R~SEDJUNE1~
PARAMETER MEASUREMENT INFORMATION
~I~---------------~C--------------~~I
*-1 fAp --.I I
I 1
~----~I ~I_________ ~----------~~ I~-----
If
JiAI
1
tAPC
--.I
CiSit
Y
~tcSR~\j
I I
I
I ..14 - - I+- tr
I I
'4-
"' ~
~
.,
twsR
~
tcHR
~I
yl, - - - - - - - _.
~ ~I"---I~~I twHR
M-A8 ~:*~1:¥-.E:~
~:ef¥,1:*';:~
OE
DQ1-DQ4
-----------HI-Z----------t
CASi
Any
can be used.
JiAI
}:
---/1 ~rtRPC
-+j
\J.
twsR
-\
tcSR
141--------- ~s
.j
~ '}
Jel~~
YI
I I
tcHS
~ ~tr
~. J ..I~ ---I~~I
~l
I~ ~I
tRPS
"-
V-
twHR
M-A8~::~K¥-~;:~
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DQ1-DQ4------------HI-Z------------------Figure 11. Self.Refresh-Cycle TIming
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
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Figure 10. Automatic CBR Refresh-Cycle TIming
~~P~
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3331D
A,32D
34 EN
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25
Q
tThlssymbol1s In accordance wHh ANSVIEEE Std 91·1984 and lEe Publication 8t7·12.
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!i(5
AO
A1
z
Column Decode
•
•
A10
•
•
•
•
ColumnAdd....
Buffera
Sen.. Ampllflera
128KArray
128KAmy
128KArray
•••
Row·
R
0
128KArray
D
e
Q
c
Addra..
Buffera
0
d
e
128KArray
128KArray
~lExAs
4-28
D
•
••
w
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304·WORD BY 1·BIT
DYNAMIC RANDOM.ACCESS MEMORIES
SMHS581A- MARCH 1995-REVISEDJUNE 1995
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by the maximum RAS low time and the CAS
page cycle time used.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS4x1 00 to operate at a higher data bandwidth than
conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than
when CAS transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after row-address hold time has been satisfied, usu~lv;ell in
advance of the falling edge of CAS. In this case, data is obtained after tcAC max (access time from A low),
if tM max (access time from column address) has been satisfied. If column addresses for the next cycle are
valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of tcAC
or tePA (access time from rising edge of CAS).
address (AO-A10)
Twenty-two address bits are required to decode 1 of 4194304 storage cell locations. Eleven row-address bits
are set up on inputs AO through A10 and latched onto the chip by the row-address strobe (RAS). The eleven
column-address bits are set up on AO through A10 and latched onto the chip be the column-address strobe
(CAS). All addresses must be stable on or before the falling edges of RAS and AS. RAS is similar to a chip
enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating
the output buffer, as well as latching the address bits into the column-address buffer.
.
Z
o
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a:
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Z
write enable (W)
The read or write mode is selected through the write-enable ~ input. A logic high on W selects the read mode
and a logic low selects the write mode. W can be driven from standard TTL circuits (TMS44100/P) or
low-voltage TTL circuits (TMS461 00/ P) Wi~out a pullup resistor. The data input is disabled when the read mode
is selected. When Wgoes low prior to CA (early write), data out remains in the high-impedance state for the
emire cycle, permitting common I/O operation.
data In (D)
Data is written during a write or read-write cycle. Depending on the mode of operation, the falling edge of CAS
or W strobes data into the on-Chip data latch. In an early-write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-write cycle,
CAS is already low and the data is strobed in by W with setup and hold times referenced to this signal.
data out (a)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS is brought
low. In a read cycle, the output becomes valid after the access time interval teAC (which begins with the negative
transition of CAS) as long as tRAC and tM are satisfied. The output becomes valid after the access time has
elapsed and remains valid while CAS is low; CAS going high returns it to the high-impedance state. In a
delayed-write or read-write cycle, the output follows the sequence for the read Cycle.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
4-29
o
Z
c~
and holding it low after RAS
falls (see parameter tcHR>. For successive CBR refresh cycl~, CAS can remain low while cycling RAS. The
external address Is ignored and the refresh address is generated internally.
l>
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A low-power battery-backup refresh mode, that requires less than 300-JAA (TMS46100P) or 500-JAA
(TMS44100P) refresh current is available on the low-power devices. Data integrity is maintained using CBR
refresh with a period of 125 j.t.S while holding RAS low for less than 1 j.t.S. To minimize current consumption, all
input levels need to be at CMOS levels (Vll S 0.2 V, VIH ~ Vee - 0.2 V).
.e"refre.h
The self-refresh mode is entered by dropping CAS low priortoRAS going low. CAS and RAS are both held low
for a minimum of 100 j.t.S. The chip is then refreshed by an on-board oscillator. No external address is required
because the CBR counter Is used tei keep track of the address. To exit the self-refresh mode, both RAS and CAS
are brought high to satisfy tcHS' Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row
addresses) must be executed before continuing with normal operation. This ensures the DRAM is fully
refreshed.
.
power up
To achieve proper deVice operation, an initial pause of 200 j.t.S followed by a minimum of eight initialization cycl~s
~s re~uired after full Vee level is achieved. These eight initialization cycles must include at least one refresh
RA "only or CBR) cycle.
.
test mode
An industry-standard design-for-test (OFT) mode is incorporated in the TMS4x100 and TMS4x100P. A CBR
cycle with ijJ low (WCBR) cycle is used to enter the test mode. In the test mode, data is written into and read
from eight sections of the array in parallel. Data is compared upon reading and if all bits are equal, the data-out
terminal goes high. If anyone bit is different, the data-out terminal goes low. Any combination of read, write,
read-write, or page-mode cycles can be used in the test mode.,The test-mode function reduces test times by
enabling the 4-Mbit DRAM to be tested as if it were a 512K DRAM, where row address 10, column address 10,
and column address 0 are not used. A RAS-only or CBR refresh cycle is used to exit the OFT mode.
~I
~ ThxAs
NSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lCXAS n251-1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A- MARCH 1985- REVISED JUNE 1985
test mode (continued)
-ioI14t----.,.1
i+-----+.t-I Entry Cycle
ExIt Cycle
1oI141-------THt-MocIe Cycle _ _ _ _ _-1.....,
I
~ Normal
Mode
, I
I
,
w~! /
t The states ot W. data In. and address are defined by the type of cycle used during test mode.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)*
Supply voltage range, Vee:
TMS44100, TMS44100P ......................... - 1 V to 7 V
TMS46100, TMS46100P ...................... -0.5Vt04.6V
Voltage range on any pin (see Note 1): TMS441 00, TMS44100P ........................ - 1 V to 7 V
TMS461 00, TMS46100P .........••.......•.•. - 0.5 V to 4.6 V
Short-circuit output current ......................•......•.•.....•.•.......•••....•.•...•••. 50 rnA
Power dissipation ....•.......•.•••.....•..•......•.•.....••....•••.•....••.••.....••.•..... 1 W
Operating free-air temperature range, TA .............................................. O·C to 70·C
Storage temperature range, Tstg .................................................. - 55·C to 150·C
:I: Stressee beyond thoee listed unc!er"absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· Is not
Implied. Exposure to absolu\e-maxlmum-rated conditions for extended periods may affect device reliability.
NOTE 1: All wltage values are with. respect to VSS.
recommended operating conditions
z
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W
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TMS46100/P
TMS44100/P
MIN
NOM
4.5
5
MAX
5.5
MIN
NOM
MAX
3
3.3
3.6
Vee
Supply wltage
VIH
High-level input wltage
2.4
6.5
2
Low-level input wltage (see Note 2)
-1
0.8
-0.3
Vee +0.3
0.8
UNIT
V
V
VIL
Operating free-air temperature
0
0
70
·e
70
TA
NOTE 2: The algebraic convention, whare the more negative Oess positive) limit Is designated as minimum, Is used for Jogic-voltage levels only.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
c~
«
V
4-31
TMS44100, TMS44100Pr TMS46100, TMS46100P
4194304-WORD BY 1·BIT
.
DYNAMICRANDOM·ACCESS MEMORIES
SMHS661A- MARCH 1895.,. REVISED JUNE 1895
.Iectrlcal charact.rlstlcs ov.r recomm.nd.d rang.s of supply voltag. and op.ratlng fr....lr
t.mperatur. (unl... otherwise noted)
.
~
VOH
High-level output voHage
10H ,,-5mA
VOL
Low-level output voltage
IOL-4.2mA
II
Input current Oeakage)
VCC=5.5V,
VI-OVto6.5V,
All otherS .. 0 V to VCC
10
Output current Oeakage)
ICC1
Read- or wrlte-cycle current
(see Note 3)
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~
(5
VCC = 5.5 V,
MIN
2.4
Vo =OVtoVcc,
~hlgh
VCC = 5.5 V,
ICC2
Standby current
m
MIN
MAX
2.4
'44100-60
'441OOP-80
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
:1:10
:1:10
:1:10
J.iA
:1:10
:1:10
:1:10
J.iA
105
90
sO
mA
2
2
2
mA
1
1
1
mA
500
500
500
J.iA
105
90
80
mA
90
80
70
mA
500
500
500
J.iA
5
5
5
mA
500
500
500
J.iA
Minimum cycle
After 1 memory cycle,
RAS and
high,
VIH Vcc - 0.2 V
(CMOS)
=
'44100-70
'441OOP-70
MAX
After 1 memOlY cycle,
RAS and CAS high,
VIH .. 2.4 V (TTL)
C
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'44100-60
'441OOP-60
TEST
CONDITIONS
PARAMETER
'44100
'44100P
=
Vcc 5.5 V, Minimum cycle,
RAS cycling,
~ high ~ only);
RAS low after
low (CBR)
1CC3
Average refresh current
~ only or CBR)
(see Note 4)
ICC4
Average page current
(see Notea 3 and 5)
VCC=5.5V,
tpc
RMIow,
~cycling
ICC6t
Self-refresh current
(see Note 3)
CAS:c 0.2 V, RAS<0.2V,
tRAS and teAs > 1000 ms
ICC7
Standby current, outputs
enabled (see Note 3)
RAS=VIH,
CAS = VIL,
Data out - enabled
ICC10t
Battery-backup current
(with CBR)
fRc 125 JIll, tRAS:c1 ms,
VCC - 0.2 V :C VIH :C 6.5 V,
OV:cVIL:c0.2V,
iN and OE .. VIH,
Address and data stable
m
=minimum,
=
Z
t For TMS441 OOP only
NOTES: 3. ICC max is specified with no load connected.
4. Measured with a maximum of one address change while RAS = VIL
5. Measured with a maximum of one address change while
= VIH
m
~1ExAs
4-32
'
INSTRUMENTS
POST OFFICE BOX 1443 • HOU$TON, lEXAS 77251-1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304·WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS581A- MARCH 1995- REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)
PARAMETER
TEST
CONDmONS
'46100·60
'46100P·80
'46100·70
'46100P·70
MIN
MIN
MAX
2.4
IOH = - 2 mA (LVTTL)
'46100·80
'46100P·80
MAX
2.4
MIN
UNIT
MAX
2.4
VOH
High-level
output voltage
Low-laval
IOL .. 2 mA (LVTTL)
0.4
0.4
0.4
VOL
outputvoltaga
IOL" 100 iAA (LVCMOS)
0.2
0.2
0.2
II
Input currant
(leakage)
VI "OVto3.9V, VCC-3.aV,
All others = 0 V to Vcc
:tl0
:tl0
:t 10
JJA
10
Output currant
(leakage)
Vo =OVtoVCC, VCC" 3.6 V,
CAS high
:tl0
:tl0
:tl0
JJA
ICCI
Read- or
writa-cycle
current
(saa Note 3)
Minimum cycle,
70
60
50
mA
2
2
2
mA
300
300
300
iAA
1CC2
Standby
currant
IOH .. - 100 iAA (LVCMOS)
VCC-0.2
VCC-0.2
VCC=3.av
V
z
After 1 memory cycle,
RAS and CAS high,
VIH = 2.0 V (LVTTL)
After 1 memory cycle,
RAS and CAS high,
VIH =VCC- 0.2V
(LVCMOS)
V
VCC-0.2
'46100
'46100P
ICes
Average
refresh currant
(RASonlyor
CBR)
(sea Note 4)
Minimum cycle, VCC = 3.6 V,
RAS cycling,
~ high (RAS only);
RAS low after CAS low (CBR)
1CC4
Average page
currant
(sea Notaa3
andS)
tpc .. minimum,
RASlow,
Iccet
Salf-rsfresh
current
(saa Note 3)
~,,0.2V,
RAS < 0.2 V,
tRAS and teAS > 1000 ms
1CC7
Standby
current,
outputs
enabled
(saa Note 3)
CAS.VIL,
RAS=VIH,
Data out .. enabled
200
=
Vcc 3.aV,
~cycling
-
200
200
o
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iAA
70
60
SO
mA
80
50
40
mA
200
200
200
iAA
oLL
-w
Z
o
z
~
Q
'4x100-60
'4x100P-60
18
60
toFF
NOTE 7: toFF is specified whan the output is no longer driven.
m
-z
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~
oz
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
0
15
0
40
20
ns
45
ns
80
ns
0
18
0
UNIT
MAX
ns
ns
20
ns
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304·WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS561A- MARCH 19115-REVlSEDJUNE 19115
tImIng requIrements over recommended ranges of supply voltage and operatIng free-aIr
temperature
lAc
!Awc
!PC
'PRwC
lRASp
lRAS
lRASs
teAs
tcp
tRP
tRPS
Cycle time, random read or write (see Note 8)
Cycle time, read-wrlte (see Note 8)
Cycle time, page-mode read or write (see Notee 8 and 9)
Cycle time, page-mode read-wrlte (see Note 8)
Pulse duration, RAS /OW, page mode (see Note 10)
Puise duration, RAS low, nonpage mode (see Note 10)
Pulse duration, RAS low, self refresh
Puise duration, ~ low, (see Note 11)
Pulse duration, CAS high
Pulse duration, RAS high (precharge)
twP
Precharge time after self refresh using RAS
Pulse duration, write
tASC
tASR
tos
Setup time, column addrees before CAS low
Setup time, row addrass before RAS /ow
Setup time, date (see Note 12)
tRCS
Setup time, W high before CAS low
Setl,lp time, W low before ~ high
Setup time, W /ow before RAS high
Setup time, W /ow before CAS /ow (early-write operation only)
tcwl
lAWl
twos
twSR
Setup time, W high (CBR refresh only)
Setup time, W low (test mode only)
Hold time, column addrees after CAS /ow
'4x1oo-80
'4x1ooP-80
'4x1oo-70
'4x1OOP-70
'4x1OO-80
'4x1ooP-80
MIN
MAX
110
130
40
80
80 100000
80 10000
100
15 10000
10
40
140
10
0
0
0
0
15
15
0
10
10
10
MIN
MAX
130
153
45
68
70 100000
70 10000
100
18 10000
10
MIN
150
175
50
75
80 100000
80 10000
100
20 10000
10
80
150
10
0
0
0
0
20
20
0
10
10
15
80
15
80
10
0
ns
ns
ns
ns
n8
n8
lUI
na
ns
ns
na
ns
ns
10
0
130
10
0
0
0
0
18
18
0
10
10
15
55
15
55
10
0
0
0
0
10
15
50
55
10
10
15
80
10
10
30
35
40
ns
10
0
80
10
0
70
10
0
80
ns
ns
twrs
tcAH
tOHR
tOH
tAR
tRAH
Hold time, date after RAS /ow (8ee Note 13)
Hold time, date (see Note 12)
50
Hold time, column addrees after RAS low (see Note 13)
Hold time, row addrees after RAS /ow
50
tRCH
Hold time, W high after ~ high (see Note 14)
tRRH
Hold time, Whigh after
twoH
twCR
Hold time, W /ow after ~ low (early-write operation only)
Hold time, W low after RAS /ow (see Note 13)
twHR
twrH
Hold time, W high (CBR refresh only)
Hold time, W low (test mode only)
10
10
tAWD
Delay time, column addrass to W /ow
(read-write operation only)
tcHR
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS high to RAS low
10
m high (see Note 14)
50·
UNIT
MAX
tcRP
Delay time, RAS /ow to CAS high
leSH
NOTES: 8. All cycle timee assume tT .. 5 na.
9. To assure tpc min, tASC should be a 5 ns.
10. In a read-write cycle, tRWO and lAWl must be observed.
11. In a read-wrHe cycle, tcwo and tcWL must be observed.
12. Referenced to the later of CAS or iN in write operations
13. The minimum value is meesured when tRCO is set to lAco min as a reference.
14. Either tRRH or lACH must be satisfied for a read cycle.
na
ns
ns
ns
na
na
na
na
ns
ns
ns
ns
ns
ns
ns
ns
ns
na
ns
ns
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
4-35
z
o
~
:E
a:
oI.L
-ow
Z
z
c~
c(
"TMS44100, TMS44100P, TMS46100, TMS46100P
4194304·WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS561A- MARCH 1995-REVISEDJUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (continued)
'4x100·60
'4x100P·60
MIN
teSR
Delay time! CAS low to .RAS low (CBR refresh only)
teHS
Hold time, CAS low after RAS high, self refresh
. tcwo
l>
c
~
z
n
m
-
'4x100·70
'4x100P·70
MAX
MIN
MAX
'4x100·80
'4x100P·80
MIN
5
5
5
ns
-so
-SO
-so
ns
Delay time, CAS low. to W low (read-write operation only)
15
tRAD
Delay time, RAS low to oolumn address (see Note 15)
15
tRAl
Delay time, oolumn address to RAS high
30
35
40
teAL
Delay time, oolumn address to CAS high
30
35
40
tRCD
Delay time, RAS low to CAS low (see Note 15)
20
tRPC
Delay time, RAS high to CAS low
18
30
45
0
15
20
ns
20
35
52
15
20
0
40
ns
ns
60
ns.
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
ns
Delay time, RAS low to W low (read-wrHe operation only)
80
70
80
ns
ITAA
Access time from
35
40
45
ns
ITCPA
Access time from oolumn precharge (test mode)
40
45
SO
ns
ITRAC
Access time from RAS (test mode)
tREF
addr~
(test mode)
75
85
16
1'4x100
Refresh time Interval
1'4xl00P
Transttlon time
IT
NOTE 15: The maximum value is specified only to assure access time.
/
2
128
128
SO
85
16
2
50
2
ns
16
ms
128
ms
50
ns
Z
o
PARAMETER MEASUREMENT INFORMATION
:xJ
1.31 V
i:
-z
ns
tRWD
."
~
o
UNIT
MAX
.
Output Under Teet
~
VCC=SV
R1 =828C
RLd18C
-iI
Output Under Test ~-.--~
Cl-100pF
Cl=100pF
(8) lOAD CIRCUIT·
R2=295C
(b) ALTERNATE lOAD CIRCUIT
Figure 1. Load Circuits for Timing Parameters
~TEXAS
INSTRUMENTS
. POST OFFICE SOX 1443· HOUSTON.lEXAS 772!51-1443
TMS441 00, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS561A- MARCH 1995-REVISEDJUNE 1995
PARAMETER MEASUREMENT INFORMATION
-1J
1.4V
Output Under Teet
VCC .. 3.3V
RL,,500D
R1 =117SD
Output Under Teet -~~-...
CL-100pF
CL:0100pF
(b) ALTERNATE LOAD CIRCUIT
(a) LOAD CIRCUIT
Figure 2. Low-Voltage Load Circuits for Timing Parameters
z
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NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 3. Read-Cycle Timing
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS'772151-1443
4-37
TMS44100; TMS44100P, TMS46100, T-MS46100P
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS581A- MARCH 189S-REVJSEOJUNE 1886
PARAMETER MEASUREMENT INFORMATION
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-z"T1
o:II
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Q------------HI.z-----------FIgure 4. Early-Wrlte-Cycle Timing
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 'IEXAS 772151-1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS581A- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
z
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(.)
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c~
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Q------------------------~-------------------NOTE A: A10 is a don't care.
Figure 10. RAS·Only Refresh·Cycle nmlng
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~1ExAs
,.
INS1RUMENTS
POeT OFFICE BOX 1443 • HOUSTON. 'I&XA8 77211-1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS561A- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
AO-A10~:*:r*~:~
z
o
~
D~!;?~*E~
:::E
a:
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Q------------HI"z-----------Figure 11. Automatic CBR-Refresh-Cycle Timing
w
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-!!11ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
4-45
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-8IT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS561A- MARCH 1886 - REVISED JUNE 1986
PARAMETER MEASUREMENT INFORMATION
-IR ,~
P
I
~ ____AI
t
58
.1
RPC--"
.
-,
tcHS
~ ~
.
IT
i
1
I I
~~I
----~------------.¥f1
I I
~tcSR~
!~I
I II
\l
1+1"---t~.....
1 tRPS
~I I
-----1RAss
i41
..
II
I"
~I
~
yr--
~R~~I--~~IHI~
--~----------~----------"~I twHR
Q-----------------------H~----------------------Figure 12. Self-Refresh-Cycle Timing
~1ExAs
, INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS581A- MARCH 1895 - REVISED JUNE 1895
PARAMETER MEASUREMENT INFORMATION
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a:
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-ow
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c~
«
Figure 13. Hldden-Refresh-cycle (Read) 11mlng
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. lEXAS 77251-1443
4·47
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORDBY 1-81T
DYNAMIC·RANDOM·ACCESS MEMORIES
SMHS581A- MARCH 1995- REVISED JUNE 1985
PARAMETER MEASUREMENT INFORMATION
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-z
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:rJ
i:
l:I!-
-oz
~
Q
------------HI.z_----~'j'rS------
Figure 14. Hldden-Refresh-Cycle (Write) Timing
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS561A- MARCH 1895-REVISEDJUNE 1895
PARAMETER MEASUREMENT INFORMATION
AO-A10~:*~r;!::~
z
o
-!:i
D~:~;?::*E:~
:E
a:
Q--------------HI-Z---------------
oLL
Figure 15. Test-Mode Entry Cycle
Z
W
device symbolization (TMS44100 Illustrated)
o
T~
)
TMS44100
W B
Y
1#
M
Z
Speed ( -eo, - 70, -eof
~
Low-Power/Self·Refreah DIIlgnator (blank or p)
C
c(
Package Code
T+
Aaambly Site Code
Lot Tracllbillty Code
Month Code
VearCode
Die Revlalon Code
Wafer Fab Code
~1ExAs
INSTRUMENTS
4-49
POST OfFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
--~."--
--
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS581A- MARCH 1986-REVJSEDJUNE 1986
~ThxAs
INSTRUMENTS
4-50
POST OFFICE BOX 1443 • HOUSTON, lCXAS 772S1-1443
TMS44400, TMS44400P, TMS46400, TMS46400P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
• Organization ••• 1048576 x 4
• Single 5-V Power Supply for TMS44400/P
(:t10% Tolerance)
• Single 3.3-V Power Supply for TMS46400/P
(:t10% Tolerance)
• Low Power Dissipation (TMS46400P only)
- 200-JAA CMOS Standby
- 2DO-JAA Self Refresh
- 3OQ.JAA Extended-Refresh Battery
Backup
ACCESS ACCESS ACCESS
READ
TIME
TIME OR WRITE
TIME
'4x400/P-70
'4x4OO/P-80
(tRAc)
(tcAc)
(tAJU
(MAX)
(MAX)
(MAX)
60 ns
70 ns
60 ns
15 ns
18 ns
20 ns
30 ns
35 ns
40 ns
CYCLE
(MIN)
110 ns
130 ns
150 ns
• Enhanced Page-Mode Operation for Faster
Memory Acces.
• CAS-Before-RAS (CBR) Refresh
• Long Refresh Period
1024-Cycle Refresh In 16 ms
128 ms (Max) for Low-Power,
Self-Refresh Version (TMS4x400P)
•
•
•
DJPACKAGE
(TOP VIEW)
001
002
Vss
OQ4
003
CAS
W
RAS
A9
OE
AO
A1
AS
A7
AS
A2.
• Performance Ranges:
'4x4OO/P-60
DGAPACKAGE
(TOP VIEW)
A5
A4
A3
Vee
001
002
W
RAS
A9
AO
A1
A2.
Vss
004
003
CAS
OE
AS
A7
AS
A3
A5
Vee
A4
PIN NOMENCLATURE
AO-AS
CAS
DQ1-DQ4
OE
AM
Vee
VSS
iN
z
o
Address Inputs
Column-Address Strobe
Data In
Output Enable
Row-Address Strobe
frV or 3.3-V Supply
Ground
Write Enable
!i:E
a::
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-w
Z
3-State Unlatched Output
Texas Instruments EPIC" CMOS Process
Operating Free-Air Temperature Range
0°Ct070°C
(.)
Z
. description
The TMS4x400 series is a set of high-speed,
AVAILABLE OPTIONS
4194304-bit dynamic random-access memories
SELF-REFRESH
(DRAMs), organized as 1048576 words of four
POWER
REFRESH
BATTERY
DEVICE
bits each. The TMS4x400P series is a set of
SUPPLY
CYCLES
BACKUP
high-speed,
low-power,
self-refresh
with
1024 In 16 ms
5V
TMS44400
extended-refresh,
4194304-bit
DRAMs,
5V
Yes
1024 In 128 rna
TMS44400P
organized as 1048576 words of four bits each.
TMS46400
3.3 V
1024 In 16 rna
Both series employ state-of-the-art enhanced
implanted
CMOS
(EPIC™)
performance
TMS46400P
3.3V
Yes
1024 In 128 rna
technology for high performance, reliability, and
low power.
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines
are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS4x400 and TMS4x400P are offered in a20/26-lead plastic small-outline (TSOP) package (DGAsuffix)
and a 30D-mil20/26-lead plastic surface-mount SOJ package (OJ suffix). Both packages are characterized for
operation from O°C to 70°C.
EPIC is a trademark of Texas Instruments Incormated.
Copyright C 1995, Texas Instrumen1s Incorporated
4-51
c~
«
TMS44400, TMS44400P, TMS46400, TMS46400P
4194304-WORD BY 1-.BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS582A- MAY 1995 - REVISED JUNE 1995
logic symbol t
DJPackage
RAM1024Kx4
AD
A1
A2
A3
A4
AS
AS
A7
AS
At
9
10
11
12
14
15
18
17
18
5
20D10/21oo
>A1~575
2OD19/2109
"-
4
"
~
z~
om
23
3
22
-z
DQ1
."
DQ2
DQ3
:II
DQ4
o
:s::
!i-
t--;:
~
r-..
1
2
24
25
C20IROW)
G23I[REFRESH ROW)
~ 241PWRDWN]
L.,
C21ICOLUMNI
G24
"
> 23C22
2321D
G25
24,25 EN
-,
r
A,22D
V28
A,Z26-
..
tThis symbol Is In accordance with ANSI/IEEE Std 91-1984 and lEO Publication 617-12.
functional block diagram
o
z
AD
Column Decode
A1
•
•
At
•
•
ColumnAddress
Buffara
Sense Ampllflera
128KArray
128KArray
128KArray R 128KArray
••
•
0
••
•
w.
Row• Address
Buffara
•
128KArray
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 772&1-1443
DQ1-DQ4
TMS44400, TMS44400P, TMS46400, TMS46400P
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS562A- MAY 1895 - REVISED JUNE 1895
operation
enhanced page IT!ode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex Is eliminated. The
maximum number of columns that can be accessed is determined by the maximum RAS low time and the CAS
page cycle time used. With minimum C\S page cycle time, all 1024 columns specified by column addresses
AO through A9 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device activate on the falling edge
of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS latches
the column addresses. This feature allows the TMS4x400 to operate at a higher data bandwidth than
conventional page-mode parts because data retrieval begins as soon as the column address Is valid rather than
when CAS transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after row-address hold time has been satisfied, usually well in
advance of the falling edge of CAS. In this case~ data is obtained after tCAC maximum (access time from CAS
low) iftAA maximum (access time from column address) has been satisfied. In the event that column addresses
for the next cycle are valid at the time C\S goes high, access time for the next cycle Is determined by the later
occurrence of teAC or tePA (access time from rising edge of CAS).
address (AD-AS)
Twenty address bits are required to decode anyone of the 1048576 storage-cell locations. Ten row-address
bits are set up on inputs AO through A9 and latched onto the chip by RAS. The ten column-address bits are set
up on AO through A9 and latched onto the chip by CAS. All addresses must be stable on or before the falling
edges of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the
row decoder. CAS Is used as a chip select, activating the output buffer, as well as latching the address bits into
the column-address buffer.
write enable (W)
The read or write mode is selected through W Input. A logic high on W selects the read mode and a logic low
selects the write mode. W can be driven from standard TTL circuits (TMS44400/P) or low voltage TTL circuits
(TMS46400/P) without a pullup resistor. The data input is disabled when the read mode is selected. When W
goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitt~
a write operation independent of ~e state of CE. This permits early-write operation to complete with OE
grounded.
data In/out (DQ1-DQ4)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE
are brought low. In a read cycle, theoutput becomes valid Illfter all access times are satisfied. The output remains
valid while CAS and OE are low. AS or OE going high returns the output to a high-impedance state. This is
accomplished by bringing CE high prior to applying data, satisfying toED,
output enable (OE)
OE controls the impedance of the output buffers. When OE Is high, the buffers remain in the high-impedance
state. Bringing OE low durini!..!!0rm~cle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance
state. They remain In the low-impedance state until either CE or CAS is brought high.
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. l1!XAS 77251-1443
4·53
z
o
!i:E
£t
oLL
-Zw
o
z
c~
«
TMS44400, TMS44400P, TMS46400, TMS46400P
4194304-WORD BY1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS582A- MAY 1896 - REVISED JUNE 1995
refresh
A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x400P) to retain data. This
can be achieved by strobing each of the 1024 rows (AO-A9). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS-only operation can be used by holding ~ at the high Onactive) level,
conserving power as the output buffer remains in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh. Hidden refresh can be performed while maintaining valid data at the
output. This is accomplished~olding CAS at Vil after a read operation and cycling RAS after a specified
precharge period, similar to a RAS-only refresh cycle. The external address is ignored during the hidden-refresh
cycle.
CAS~before-RAS (CBR) refresh
CBR refresh is utilized by bringing ~ low earlier than RAS (see ~metertcSFV and holding it low after RAS
falls (see parameter tcHFV. For successive CBR refresh cycles, ~ can remain low while cycling RAS. The
external address is ignored and the refresh address is generated internally.
l>
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m
z
-
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(5
Z
A low-power battery-backup refresh mode that requires less than 300-JAA (TMS46400P) or 5OO-JAA
(TMS44400P) refresh current is available on the low-power devices. Data integrity is maintained using CBR
refresh with a period of 125 !AS while holding RAS low for less than 1 !AS. To minimize current consumption, all
input levels need to be at CMOS levels (Vll" 0.2 V, VIH :II: Vee - 0.2 V).
self refresh
The self-refresh mode is entered by dropping CAS low prior to RAS going low. CAS and RAS are both held low
for a minimum of 100 !AS. The chip is then refreshed by an on-board oscillator. No external address is required
since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS
are brought high to satisfy tcHS. Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row
addresses) must execute before continuing with normal operation. This ensures the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 !AS followed by a minimum of eight initialization cycles
is required after full Vee level is achieved. These eight initialization cycles must include at least one refresh
(RAS-only or CBR) cycle.
test mode
The test mode is initiated with a CBR refresh cycle while simultaneously holding W low (WCBR). The entry cycle
performs an intemal refresh cycle while internally setting the device to perform parallel read or write on
subsequent cycles. While in test mode, any desired data sequence can be performed on the device. The device
exits test mode if a CBR refresh cycle with W held high or a RAS-only refresh (ROR) cycle is performed.
The TMS4x400/P is configured as a 512K x 8 bit device in test mode, where each DQ pin has a separate 2-bit
parallel read- and write-data bus. During a read cycle, the two internal bits are compared for each DQ pin
separately. If the two bits agree, the DQ pin goes high; if not, the DQ pin goes low. The two bits are written to
reflect the state of their respective DQ pins during a parallel write operation. Each DQ pin is independent of the
others, and any data pattern desired can be written on each DQ pin. Test time is reduced by a factor of 4 for
this series.
~ThxAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lCXAS 77251-1443
TMS44400, TMS44400P, TMS46400, TMS46400P
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS562A- MAY 1995 - REVISED JUNE 1995
te.t mode (continued)
14-----~+-1 Entry Cycle
Exit Cycle -I4141-----+l~1
141------...
Tnt Mode Cycle ------~~I
1
1
I+-- Normal
M~
1
1
7!\___~__
/
Figure 1. Te.t·Mode Cycle TImingt
t The states of W, data in, and address are defined by the type of cycle used during test mode.
absolute maximum ratings over operating free-alr temperature range (unless otherwise noted)*
Supply voltage range, Vee:
*
TMS44400. TMS44400P .................•....• -1.0 V to 7.0 V
TMS46400. TMS46400P •....•...•....•.•...... - 0.5 V to 4.6 V
Voltage range on any pin (see Note 1) TMS44400. TMS44400P .•...•.•....•.•.•.••••• - 1.0 V to 7.0 V
TMS46400. TMS46400P ...•.....•....•........ - 0.5 V to 4.6 V
Short-circuit output current •.••....•...•.....••.•.••...•••...••...••....•.••..•..•..•.•.•.• 50 mA
Power dissipation •................•.....•....••..................................•.......... 1 W
Operating free-air temperature range, TA .............................................. O·C to 70·C
Storage temperature range, Tstg •...•.••..••.•.••........•........................ - 55·C to 150·C
Stresses beyond thoae listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operetlon of the device at these or any other conditions beyond those indicated under "recommended operating conditions· Is not
Implied. Exposure ~ abeolute-maxlmum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
TMS44400/P
Supply voltage
TMS46400/P
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
3.3
3.6
UNrr
V
VIH
High-level Input voltage
2.4
6.5
3
2
VIL
Low-level Input voltage (see Note 2)
-1
0.6
-0.3
0.6
V
TA
Operating free-air temperature
0
70
0
70
·C
VCC
..
..
VCC+ 0.3
V
NOTE 2: The algebraic convention, where the more negative ~ess positive) limit Is designated as minimUm, IS used for logIC-voltage levels only.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
4-55
z
o
fi
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a:
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Z
W
o
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c~
ICC2
Standby current
VIH .. VCC- 0.2 V
(CMOS)
~=5.5V,
:0:10
:0:10
tlA
:0:10
:0:10
:0:10
tlA
105
90
ao
mA
2
2
2
mA
'44400.
1
1
1
mA
'44400P
500
500
500
tlA
105
90
ao
mA
90
80
70
mA
500
500
500
tlA
5
5
5
iliA
500
500
500
tlA
Minimum cycle,
-
Average refresh current
(RAS only or CBR)
(see Note 4)
ICC4
Average page
current
(see Notes 3 and 5)
VCC = 5.5 V,
RASIOW,
Iccat
Self-refresh current
(see Note 3)
CAS,,0.2V, RAS<0.2V,
tRAS and teAS > 1000 ma
ICC7
Standby current, outpute
enabled (see Note 3)
FiAS .. VIH,
ICC10t
Battery-backup current
(wilhCBR)
o
s:
::D
~
0'
Z
RAS cycling,
~ high
(RAS only);
RAS low after ~ low (CBR)
tpc .. minimum,
CAS cycling
~.VIL..
Data out .. enabled
tRC" 125 j.IS, lRAS,,1 ma,
VCC - 0.2 V " VIH " 6.5 V,
OV "VIL" 0.2 V,
iN ."d OE • VIH,
Address end data stable
t For TMS44400P only
NOTES: 3. ICC max Is spacl1led with no load connected.
4. Measured with a maximum of one address change while FiAS .. VIL
5. Measured wilh a maximum of one address change while CAS .. VIH
~TEXAs
4-56
V
:0:10
1CC3
."
2.4
V
(')
m
z
UNIT
MAX
0.4
Minimum cycle
After 1 memory cycle,
MIN
0.4
VO=OVtoVCC,
FiAS end ~ high,
'44400-60
'44400P-80
0.4
After 1 memory cycle,
RAS end ~ high,
VIH = 2.4 V (TTL)
c
z~
MIN· MAX
2.4
2.4
CAS high
VCC .. 5.5V,
'44400-70
'44400P-70
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON. lEXAS 77251-1443.
TMS44400, TMS44400P, TMS46400, TMS46400P
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS562A- MAY 1995 - REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VOH
High-level
output voltage
VOL
Low-level
output voltage
II
Input current
Oeakage)
10
Output current
(leakage)
ICCl
Reed-or
wrlta-cycle
current
(see Note 3)
'46400-60
'46400P-60
'46400-70
'46400P-70
MIN
MIN
MAX
ICes
Standby
current
Average
refresh current
(FiAS DIlly or
CBR)
(see NoIiI4)
MIN
UNIT
MAX
2.4
VCC-O•2
VCC-O.2
V
VCC-0•2
IOL = 2 mA (LVTTL)
0.4
0.4
0.4
IOL = 100 lolA (LVCMOS)
VI =OVto3.9V, Vcc = 3.8 V,
All others • 0 V to Vcc
0.2
0.2
0.2
:1:10
:1:10
:1:10
lolA
:1:10
:1:10
:1:10
lolA
70
80
50
mA
2
2
2
mA
300
300
300
lolA
Vo =OVtoVCC, Vcc = 3.8 V,
~hlgh
Minimum cycle,
VCC=3.8V
V
z
After 1 memory cycle,
RA! and ~ high,
ICC2
MAX
2.4
2.4
10H .. - 2 mA (LVITL)
IOH .. - 100 lolA (LVCMOS)
'46400-80
'46400P-80
VIH·2V(L~
After 1 memory cycle,
RA! and ~ high,
VIH .VCC- O•2V
(LVCMOS)
'46400
'464OOP
200
200
200
lolA
Iccet
current
tpc • minimum,
VCC· 3•8V,
(aeeN«*li3
RAlIow,
~cycllng
and 5)
SeIf-"""",
current
(_NoIiI3j
au. 0.2 V,
RA!<0.2V,
70
80
50
rnA
80
50
40
rnA
IAAS and teAs > 1000 me
200
200
200
lolA
current,
outpuI8
enabled
(_NoIiI3j
a:
u.
z
w
o
z
c~
tAA
Accees time from column eddress
30
35
40
n.
teAC
Accees time from CAS low
15
18
na
.~
tePA
tRAC
Accees time from column precharge
35
40
20
45
Accees time from RAS low
80
70
80
c
z
o
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-Z
~
toEA
Accees time from OE low
teu
CAS to output In low Impedance
Output-dislible time after CM high (see Note 7)
toFF
15
toEZ Output-d~1e time after Of high (see Note 7)
NOTE 7: toFF Is specified when the output Is no longer driven.
0
15
0
18
0
1$
0
18
!:
-o~
Z
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lEXAS 77251-1443
20
ns
0
0
:lJ
4-58
18
0
0
0
os
os
os
20
ns
20
ns
TMS44400, TMS44400P, TMS46400, TMS46400P
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS582A- MAY 1895 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
tRC
tRWC
tpc
'4X400-60
'4X4OOP-60
'4X4OO-70
'4X4OOP-70
'4x8400-60
'4X400P-60
MIN
MIN
MIN
MAX
MAX
Cycle time, random read or write (see Note 8)
110
130
150
ns
CYCle time, read-write
155
181
205
50
105
ns
80 100000
80 10000
100
20 10000
10
60
150
10
ns
Cycle time, page-mode read or write (see Note 9)
Cycle time, page-mode raed-write
40
45
85
98
Pules duration, RAS low, page mode (see Note 10)
Pulse duration, RAS low, nonpage mode (see Note 10)
60
100000
1RAS
60
10000
10000
tRASS
Pulse duration, AAS low, self refresh
70
100
teAs
10000
18
10
10000
tcp
tAp
Pules duration, ~ low (see Note 11)
Pules duration, ~ high
Pules duration, RAS high (precharge)
tAps
Precherge time after self refresh using RAS
twP
Pulse duration, write
tASe
Setup time, column addreea before ~ low
Setup time, row addreea before RAS low
tPRWC
tRASP
tAsR
tos
100
10
10
70 100000
40
50
110
10
130
10
0
0
0
0
Setup time, data (see Note 12)
0
tRCS
Setup time, W high before ~ low
0
tcwL
1RwL
Setup time, Wlow before ~ high
Setup time, Wlow before fiA! high
twcs
Setup time, Wlow before 'CAS low (early-write operation only)
Setup time, Whigh ~ refresh only)
15
15
0
10
twsR
twTs
UNIT
MAX
\
ns
ns
ns
I&S
ns
ns
ns
ns
ns
0
0
ns
ns
0
0
ns
0
0
ns
18
20
18
0
10
20
0
10
n8
n8
ns
ns
10
15
ns
ns
Setup time, Wlow (teat mode only)
Hold time, column addreea after CAS low
10
10
10
15
toHR
tOH
Hold time, data after RAS low (see Note 13)
Hold time, data (see Note 12)
50
10
55
15
80
15
ns
ns
tcAH
tAR
Hold time, column addreea after RAS low (see Note 13)
50
55
Hold time, row addreea after AAS low
10
10
80
10
n8
lRAH
tRCH
Hold time, Whigh after eA! high (see Note 14)
0
0
0
ns
tRRH
Hold time, Vi high after FiAS high (see Note 14)
twcH
Hold time, W low after ~ low (early-write operation only)
0
10
0
15
0
16
ns
ns
twcR
Hold time, W low after fiA! low (see Note 13)
Hold time, W high (CBFi refresh only)
50
10
55
10
10
-50
18
18
60
10
10
n8
ns
twHR
twTH
tcHS
toEH
Hold time, Wlow (teat mode only)
Hold time, CAS low after RAS high (self refresh)
Hold time,~ command
10.
-50
15
Hold time, ~ to data delay
16
toED
NOTES: 8. All cycle times assume tr 5 ns.
9. To ensure tpc min, tASC should be II tcP.
10. In a read-write cycle, tRWO and 1RwL must be observed.
11. In a read-wrlte cycle, tcwo and tcwL must be obsllrved.
12. Referenced to the later of eM' or WIn write operations
13. The minimum value Is measured when tAco Is set to tRCO min as a reference.
14. Either tRRH or tACH must be satisfied for a read cycle.
n8
ns
20
ns
ns
20
ns
-50
=
~1ExAs
INSTRUMENTS
POSTOFFICE BOX 1443· HOUSTON, TEXAS 77251-1443
4-59
z
o
~
::IE
a:
f2z
-w
CJ
Z
~
Q
c(
TMS44400, TMS44400P,TMS46400,TMS46400P
4194304-WORD BY 1·B1T
DYNAMICRANDOM.ACCESS MEMORIES
SMHS582A-MAY1895-REVlSEDJUNE1995
..
timing requirements over recommended ranges of supply voltage and operating free..lr
temperature (continued)
'4x4OO-70
'4x4OOP-70
'4x400-80
'4x4OOP-80
MIN
MAX
MIN
MAX
'4x400-80
'4x4OOP-80
MIN
UNIT
MAX
tROH
Hold time, RAS referenced to OE
10
10
10
ns
tAWD
Delay time, column address to W low (read-write operation only)
55
63
70
teHR
Delay time, J!iA'§ low to CAS high (CBR refresh only)
10
10
10
ns
ns
teRP
Delay time, CAS high to RAS low
0
0
0
ns
tcsH
Delay time, J!iA'§ low to CAS high
80
70
80
ns
tcsR
Delay time, CAS low to J!iA'§ low (CBR refrlish only)
5
5
5
ns
tewo
tRAO
Delay time, CAS low to Wlow (read-write operetlon only)
40
46
50
Delay time, J!iA'§ low to column address (see Note 15)
15
tAAL
Delay time, column address to J!iA'§ high
30
35
40
ns
teAL
tRCD
Delay time, column address to CAS high
30
35
40
ns
Delay time, J!iA§ low to CAS low (see Note 15)
20
tRPC
Delay time, J!iA'§ /'Iigh to CAS low
0
0
0
ns
~
tRSH
tRWD
Delay time, CAS low to J!iA'§ high
15
18
20
ns
Delay time, J!iA'§ low to Wlow (read-write operation only)
85
98
110
ns
trAA
35
40
45
ns
trCPA
Acoess time from address (test mode)
Access time from column precharge (test mode)
40
45
50
ns
-
trRAc
Acoess time from RAS (test mode)
85
75
85
l>
c
o
m
z
cg
2J
tREF
I '4x4OO
Refresh lime interval
a:
~
45
15
20
18
128
I '4x400P
Transition time
tr
NOTE 15: The maximum value is specified only to ensure access time.
30
2
30
35
52
15
20
18
128
2
30
2
ns
40
80
1.31 V
~
ns
Output Under Test
--1I
ms
ns
R1-828Q
Output Under Test
-----~
CL-100pF
(_NoteA)
CL-100pF
(eesNoteA)
R2-295Q
(b) ALTERNATE LOAD CIRCuIT
(a) LOAD CIRCUIT
NOTE A: CL Includes probe and fixture capacltanoe.
Figure 2. Load Circuits for Timing Parameter.
~TEXAS
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON. TEXAS 77211-1443
ms,
30
VCC-IV
RL-Z18Q
ns
18
128
PARAMETER MEASUREMENT INFORMATION
oz
ns
TMS44400, TMS44400P, TMS46400, TMS46400P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS582A- MAY 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
UV
~
Output Under TNt
VCC·3.3V
Rl.117SD
RL-500D
---i .
CL-l00pF
Output Under Tnt
I
----4...--....
CL-l00pF
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
Figure 3. Low-Voltage Load Circuits for Timing Parameters
z
o
~
:E
a:
o
u.
z
-ow
z
c~
c
z~
n
AD-AI
m
-z
cg
::D
!ia:
-oz
DQ1-DQ4
Figure 5. Early-Wrlte-Cycle Timing
~TEXAS
INSTRUMENTS
POeT OFFICE BOX 1443 • HOUSTON, 'IEXA8 772S1-1443
TMS44400, TMS44400P, TMS46400, TMS46400P
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS582A- MAY 1895 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
z
o
~
:&
a:
~
z
-w
(J
Z
~
~
Figure .. Wrfte.Cycle nmlng
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 772151-1443
4-63
TMS44400, TMS44400P, TMS46400, TMS46400P
4194304-WORD BY 1·BIT
DYNAMIC·RANDOM·ACCESS MEMORIES
SMHS562A-MAY 1995 -REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
l>
c
~
z
(')
m
-z
cg
:II
I:
-oz~
NOTE A: Output can go from the high-Impedance state to an Invaild-data state prior to the specified access time.
Figure 7. Read-Wrlte-Cycle TIming
4-64
-!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS44400, TMS44400P, TMS46400, TMS46400P
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS582A- MAY 1995 - REVISED JUNE 1995
rr
PARAMETER MEASUREMENT INFORMATION
I
IRASP
L
~
I 1"tACD ~
I
, I..
teSH
~ ~tr
..., :, I
I+r iASR
I!41_----+l.I-
'i
.1
.I I
I
I
-+-I
II4-f-I-
}
IASC
1
teAH'
"
P
.,'
II
I I
'
.~
_
14'_---
AO-A9
'I
I+- teRP ~
I ""I'
1
.ii
...SH.Je"',
11'4
,
- ,
·1
tpc
te
~,..
teAS
1
.1
1
-----------tjf-L
NI+- -+111
,j4-IRAH-.I
, I
I
tAp II I
tRAL
teAL
/iI
I
I
I,
I
,
z
Column
o
ti
:E
a:
o
u.
Z
w
o
z
c~
DQ1-DQ4
«
time
NOTES: A Acces8
Is tePA or fAA dependent.
B. Output can go from the high-Impedanoe state to an InvaJld-data state prior to the specified acceSs time.
Figure 8. Enhanced·Page-Mode Read-<:ycle TIming
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
4-65
TMS44400, TMS44400P, TMS46400, TMS46400P
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESSMEMORIES
SMHS582A;" MAY 1995 - REVISED JUNE 1895
PARAMETER MEASUREMENT INFORMATION
AO-A9
l>
c
z~
w
o
m
-z
cg
:u
OQ1-DQ4
I:
!i(5
z
NOTES: A. Referenced to C5AS or IN, whicheVer occurs last
B. A read cycle or a read-wrlte cycle can be Intermlxad with write cycles as long as read and read-write timing specifications are not
violated.
Figure 9. Enhanced-Page-Mode Wrlte-Cycle Timing
~1ExAs
4-68
INSTRUMENTS
POST OFFICE-BOX 1443 • HOUSTON. 1CXAS 77251-1443
TMS44400, TMS44400P, TMS46400, TMS46400P
4194304·WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS562A- MAY 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
z
o
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a:
oLL
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W
o
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.~
I
I
II
I
I .14+j- twHR
I
I
_r •
~ twSR
twSR
I
I .
toFF-+j
:l1li
; .-1 teAC
~
I
_...::~
DQ1-DQ4 _ _ _
I
114-l1li--i~~1 toEA
~~~I
~~
tt
"
Figure 14. Hldden-Refresh-cycle (Read) nmlng
~ThxAs
4-70
I
I
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I
I
~.
f""1
I
I
I
I
I
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lE(A8 77251-1443
TMS44400, TMS44400P, TMS46400, TMS46400P
. 4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS582A- MAY 1985 - REVISED JUNE 1985
PARAMETER MEASUREMENT INFORMATION
z
o
fi:E
a:
oLL
-w
Z
U
Z
c~
«
FIgure 15. Hldden-Refresh-Cycle (Write) Timing
~1ExAs
INSTRUMENTS
POST OFFICe BOX 1443 • HOUSTON. TEXAS 772&1-1443
4-71
TMS44400; ·TMS44400P, TMS464bo~ TMS46400P
4194304-WORD BY1 ~BIT
DYNAMIC'RANDOM-ACCESS·MEMORIES
SMHS582A- MAY 19116.-REViSED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
~
z~
om
z
."
-
o
:D
s::
DQ1-DQ4 ----------~---
HI.z--------------
Figure 16. Test·Mode Entry·Cycle Timing
device symbolization (TMS44400 Illustrated)
TT
~s
~
P
(5
Z
TMS44400
W
B
Y
Speed ( ·60, ·70, ·80)
Low-Power/SeIf·R.f....h D••lgnator (Blank or P)
~.
M
T+
Packag. Cod.
Asaambly Site Cod.
Lot Trac.abillty Cod.
Month Cod.
V.arCod.
01. R.vlslon Cod.
Waf.r Fab Cod.
~ThxAs
4-72
INSTRUMENTS
POST OFFICE sox 14<13 • HOUsTON, TEXAS 772111-14<13
TMS44165, TMS44165P
262144-WORD BY 16-BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
1995
This data sheet is applicable to all TMS44165/Ps
symbolized with Revision -D- and subsequent
revisions as described on page 4-92.
• Organization ••• 262 144 )( 16
• SOV Supply (:t:10% Tolerance)
• Performance Ranges:
'44165/P-60
'44165/P-70
'44165/P-60
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
WRITE
'RAC
'cAC
tAA
CYCLE
MAX
MAX
MAX
MIN
60 n8
15 n8
30 n8
110 ns
70 n8
20 n8
35 n8
130 n8
60 n8
20 n8
40 n8
150 n8
• Enhanced-Page-Mode Operation With
CASO-Before-RAS (CBR) Refresh
• Long Refresh Period
1024-Cycle Refresh In 16 ms (Max)
128 ms Max for Low-Power With
Self-Refresh Version (TMS44165P)
•
•
•
•
3-State Unlatched Output
Low Power Dissipation
Texas Instruments EPIC™ CMOS Process
All Inputs, Outputs, and Clocks Are TTL
Compatible
DZPACKAGE
(TOP VIEW)
Vee
1
2
3
4
5
( 6
004 ( 7
DOS 8
006 9
007 10
NC 11
LW 12
UW 13
AAS 14
AS 15
AO 16
Al 17
A2 18
A3 19
20
000
001
002
003
Vcc
Vee
• High-Reliability, 4O-Lead, 4OO-MII-Wlde
Plastic Surface-Mount (SOJ) Package and
4O/44-Lead Thin Smail-Outline Package
(TSOP)
Vss
0015
0014
0013
0012
Vss
34 0011
33 0010
32 009
31 DOS
30 NC
Vee
D07
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
13
32
31
30
29
28
27
26
25
24
23
000
001
002
D03
Vee
D04
D05
DOS
29
NC
28
27
26
25
24
23
CAS
NC
OE
LW 14
UW
AAS
A9
AS
A7
AS
A5
22 A4
21
Al
A2
A3
15
16
17
18
19
20
21
Vee
22
AO
Vss
Vss
0015
0014
D013
D012
Vss
0011
0010
D09
DOS
NC
NC
CAS
OE
AS
A7
AS
AS
A4
Vss
PIN NOMENCLATURE
AO-A9
DOO-DQ15
CAS
LW
NC
OE
RAS
UW
• Operating Free-Air Temperature Range
O°C to 70°C
• Low-Power With Self-Refresh Version
• Upper and Lower Byte Control During Write
Operations
40
39
38
37
36
35
DGEPACKAGE
(TOP VIEW)
Vcc
Vss
Address Inputs
Data In/Data Out
Column-Addrass Strobe
Lower Write Enable
No Internal Connection
Output Enable
Row-Address Strobe
Upper Write Enable
5-VSupply
Ground
description
The TMS44165 series are high-speed, 4194 304-bit dynamic random-access memories organized as 262144
words of 16 bits each. The TMS44165P series are high-speed, low-power, self-refresh 4194304-bit dynamic
random-access memories organized as 262144 words of 16 bits each. They employ state-of-the-art EPIC™
(Enhanced Performance Implanted CMOS) technology for high performance, reliability, and low power.
The~e devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. Maximum power dissipation
Is as low as 580 mW operating and 11 mW standby on 8O-ns devices. All inputs and outputs, including clocks,
are compatible with Series 74 TTL. All addresses and data-in lines are latched on chip to simplify system design.
Data out is unlatched to allow greater system flexibility.
The TMS44165 and TMS44165P are eaqh offered in a 40-lead plastiC surface-mount SOJ package (DZ suffix)
and a 4O/44-lead plastic surface-mount TSOP package (DGE suffix). These packages are characterized for
operation from O°C to 70°C.
EPIC is a trademark of Texas Instruments InCOrporated.
~TEXAS
INSTRUMENTS
POST OFFICE &OX 1443 • HOUSTON, TEXAS 77251-1443
Copyright C 1995, Texas Instruments Incorporated
4-73
TMS44165, TMS44165P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHSl88C- AUGUST 18112- REViseD JUNE 1995
operation
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex Is eliminated. The maximum
number of columns that can be accessed Is determlred by the maximum RAS low time and the ~ page-mode
cycle time used. With minimum CAS page~e time, all 256 columns specified by column addresses
AO-A7 can be accessed without intervening RAS cycles.
Unlike conventional page-mQde DRAMs, the column-address buffers In this device are activated on the falling
ed~ew RAS, The buffers act as transparent or flow-through latches while CAS is high. The first falling edge
of A latches the column addresses. This feature allows the devices to operate at a higher data bandwidth
than conventional page-mode parts because data retrieval begins as soon as column address Is valid rather
than when ~ transitions low. This performance improvement Is referred to as enhanced page mode. A valid
column address can be presented immediately after tRAH (row-address hold time) has been satisfied, usually
well in advance of the falling edge of CAS. In this case, data is obtained after tCAC max (access time from CAS
low) If tAA max (access time from column address) .has been satisfied. In the event that column addresses for
the next page cycle are valid at the time CAS goes high, minimum access time for the next cycle Is determined
by tePA (access time from rising edge of the last CAS).
addre. . (AO-Aa)
Eighteen address bits are required to decode 1 of 262144 storage cell locations. Ten row-address bits are set
up on AO-AS and latched onto the chip by RAS. Then, eight column-address bits are set up on AO through
and latched onto the chip by~. All addresses must be stable .on or before the falling edge of RAS and CA •
RAS is similar to a chip enable In that it activates the sense amplifiers as well as the row decoder. ~ Is used
as a chip select activating the output buffers and latching the address bits into the column-address buffers.
W
write enable (UW, LW)
The read or write mode is selected through the upper or lower write-enable (UW, LW) Input. [W controls
OQO-OQ7, and UW controls OQ8-0Q15. A logic high on the UW and UN input selects the read mode and a
logic low selects the write mode. The write-enable terminal Can be driven from the standard TTL circuits without
a pullup resistor. The data input is disabled when the read mode is selected. When UWor UN goes low prior
to CAS (early write), data out remains in the high-impedance state for the entire cycle permitting a write
operation with OE grounded.
Either UW or LW can be brought low, and the user can write into eight OQ locations; UWand LW can be brought
low at the same time and all 16 OQ are written Into.
data In (OQO-OQ15)
Data Is written during a write or read-modify-write cycle. Depending on the mode of o~ation, the falling edge
of CAS, UW, or LW strobes data into the on-cg'p data latch. In an early-write cycle, UW or LW is brought low
prior to CAS, and the data is strobed in by AS with setup and hold times referenced to this signal. In a
delayed-write or read-modify-write cycle, CAS is already low, and data is strobed In ~OW or LW with setup
and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring
the output buffers to the high-Impedance state prior to impres~ing data on the I/O lines. The [Wterminal controls
OQO-OQ7. The OW pin controls OQ8-0Q15.
data out (OQO-DQ15)
The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output Is In the high-impedance (fioating) state
until CAS and OE are brought low. In a read cycle, the output becomes valid after the access time interval tcAC
(which begins with the negative transition of CAS) as long as tRAC and tAA are satisfied.
~ThxAs
4-74
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 712&1-1443
TMS44165, TMS44165P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS166C- AUGUST 1992 - REVISED JUNE 1995
output enable (O!)
OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go Into the low-Impedance
state. Once in the low-impedance state, they remain in the low-Impedance state until either OE or CAS is
brought high.
RAS-only refreeh
A refresh operation must be performed at least once every 16 ms (128 ms for TMS44165P) to retain data. This
can be achieved by strobing each of the 1024 rows (AO-A9). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high Onactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
hidden refre.h
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding
CAS' at Vil after a read operation and cycling RAS after a specified precharge period, similar to a RA'S-only
refresh cycle. The external address is ignored, and the refresh address is generated internally.
. ~·befor..RAS (CBR) refre.h
CBR refresh Is utilized by bringing CAS low earlier than RAS (see parameter tesR> and holding it low after RAS
falls (see parameter tcHR)' For successive CBR refresh cycles, CAS remains low while cycling RAS. The
external address is ignored and the refresh address is· generated internally.
A low-power battery-backup refresh mode that requires less than 500 !AA refresh current Is available on the
TMS44165P. Data integrity is maintained using CBR refresh with a period of 125 jl.S while holding RAS low for
less than 1 jl.S. To minimize current consumption, all input levels must be at CMOS levels
(Vll ~ 0.2 V, VIH :II: Vee - 0.2 V) •
• elf refre.h (TMS44165P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS' and RA'S are both
held low for a minimum of 100 jl.S. The chip is then refreshed internally by an on-board oscillator. No external
address is required because the CBR counter is used to keep track of the address. To exit the self-refresh mode,
both RA§' and CAS are brought high to satisfy tcHS' Upon exiting the self-refresh mode, a bUrst refresh (refresh
a full set of row addresses) must be executed before continuing with normal operation. This ensures the DRAM
Is fully refreshed.
power up
To achieve proper device operation, an Initial pause of 200 jl.S followed by a minimum of eight RAS cycles is
~ed
after power up to the full Vee level.These eight initialization cycles must include at least one refresh
(RAS-only or CBR) cycle.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1_ • HOUSTON. TEXAS 772111-1_
4-75
TMS44165, TMS44165P
262144-WORDBY 16-BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHSI68C- AUGUST,I892 - REVISED JUNE 1996
logic aymbol t
~256K"11
2OD8/21DO
11
AD
17
AI
A2
11
19
A3
22
A4
0
>A 282143
23
AS
24
AS
25
A7
~
AS
15
2OD18/21D7
20017
20018
AS
-t::. >C20[ROw]
,..1::=:. 023/(REFRESH ROW)
.1L >--
24[PWRDWN]
--""
&:
-t::.
+
029
,..1::=:. Z31
,..1::=:. >C21 [COL]
,..1::=:. 024
58
28
LVI
12
r
r
)
uw
OE
DQO
13
27
:l
DQ4
DOS
DQ6
DQ7
DQ8
23,21D
23C22
+
31&:
2321D
29,25EN28
23C32
+
29,25EN27
.... 025
2
001
DQ2 4
DQ3 5
.
....
,-
r
A,22D
L.....
-
V21
A,Z21
-
7
8
9
10
31 -
A.32D
4- V27
32 ....
A,Z27
DQ9
33 .: ..
0010
34DQ11
OO1~
38
37
0013
38 ....
0014
39DQ15
t This symbol Is In accordance with ANSVIEEE Sid 91-1984 and lEe Publication 617-12.
The pin numbers shown correspond to the DZ package.
-!11 TEXAS
4-76
INSTRUMENTS
POST OFFICE BOX 14<13 • HOVsroN. 1S(A8 77251-14<13
TMS44165, TMS44165P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHSl86C -AUGUST 1992 - REVISED JUNE 1995
functional block diagram
AO
A1
Column Decode
•
•
AI
•
•
•
•
Sen.. Ampllflel1l
CoIumnAdd .....
Buffera
128KArray
128KArray
•••
128KArray
R
0
128KArray
w
•
••
D
e
e
RowAdd .....
Buffera
0
d
e
128KArray
128KArray
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee ........................................................... -1 Vt07V
Input voltage range (see Note 1) ...................................................... -1 V to 7 V
Short-circuit output current .................................................. ,............. 50 rnA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range, TA ..............' ........................... "... o·e to 70·e
Storage temperature range, Tstg , ............................ ,., .............. ,.... - 55·e to 150·e
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-raied conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
vee
Supply voltage
Vss
Supply voltage
VIH
High-level input voltage
2.4
6.5
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-alr temperature
0
70
·C
..
. ..
..
V
V
0
V
NOTE 2: The algebraIC convention, where the more negatiVe '0- pcsltlVe) limit IS designated es minimUm, IS used for logic-voltage levels only.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEl 1 I
400
400
400
t4A
~=5.5V.
RASIow,
t Measured with outputs open
* Measured with a maximum of one address change while ~ .. VIL
§ Measured with a maximum of one address change while CAS = VIH
, For TMS44185P only
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f 1 MHz' (see Note 3)
=
PARAMETER
CI(A}
Input cepacitance. AO-AS
CilOE)
Input capacitance, OE
CIlRC)
Input cepacitance. CAS and RAS
Ci(W)
Input cspacItance, )I!.N
MIN
\;,
Output cepacltance
Co
it capacitance measurements are made on a sample basIS only.
NOTE 3: VCC" 5 V :t 0.5 V. and the bias on pins under test Is 0 V.
~1ExAs
4-78
INSTRUMENTS
POST OFFICE SOX 1443 -HOUSTON. lEXAS 77261-1443
MAX
UNIT
5
pF
7
pF
7
7
7
pF
pF
pF
TMS44165, TMS44165P
262144-WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS186C -AUGUST 1992 - REVISED JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'44165-60
'44165P-60
PARAMETER
MIN
'44165-70
'44165P-7O
'44166-80
'44166P-80
MIN
MIN
MAX
MAX
UNIT
MAX
teAC
Access time from CAS low
15
20
20
ns
tM
Access time from column address
30
35
40
ns
tRAC
Access time from RAS low
60
70
80
ns
toEA
Access time from OE low
15
20
20
ns
tePA
Access time from column precharge
35
40
45
toFF
Output disable time after CAS high (see Note 4)
0
15
0
20
0
20
ns
ns
ns
toEZ
Output disable time after OE high (see Note 4)
0
15
0
20
0
20
ns
.teLZ
Delay time, CAS low to output In the low-Impedance state
0
0
0
NOTE 4: toFF and toEZ are specified when the output Is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
'44165-60
'44165P-60
'44165-70
'44165P-70
'44165-80
'44165P-80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tRWC
Cycle time, read-write/read-modify-wrlte
155
165
205
ns
ns
ns
tpc
Cycle time, page-mode read or write (see Note 7)
40
50
ns
tPRWC
Cycle time, page-mode read-modify-write
85
45
90
105
ns
tRASP
Pulse duration, RAS low, page mode (see Note 8)
70
100000
tRAS
Pulse duration, RAS low, nonpage mode (see Note 8)
60 100000
60 10000
70
teAS
Pulse duration, CAS low (see Note 9)
15
20
tep
Pulse duration, CAS high
10
10
10
tRP
Pulse duration, RAS high (precharge)
40
50
twP
Pulse duration, write
15
15
.tASC
Setup time, column address before CAS low
0
0
tASR
Setup time,
0
0
tRC
Cycle time, read (see Note 6)
110
130
150
twc
Cycle time, write
110
130
150
row address before RAS low
10000
80 100000
ns
10000
80
10000
ns
10000
20
10000
80
ns
ns
ns
15
ns
0
0
ns
ns
tos
Setup time, dele before xW low (see Note 10)
0
0
0
ns
tRCS
Setup time, read before CAS low
0
0
0
tCWL
Setup time, xW low before CAS high
15
20
20
ns
ns
tRWl
Setup tlme,llW low before RAS high
15
20
20
ns
twcs
Setup time, xW low before CAS low (see Note 11)
0
0
0
ns
NOTES: 5.
6.
7.
8.
9.
10.
11.
,
Timing measurements are referenced to VIL max and VIH min.
All cycle times assume IT 5 ns.
To assure !pc min, IAsc should be 1It tep.
Ina read-modify-write cycle, tRWO and tRWL must be observed.
In a read-modlfy-write cycle, lewD and teWl must be observed.
Referenced to the later of CAS or iii In write operations
Early-write operation only
=
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 772111-1443
4-79
TMS44165, TMS44165P
2621*WORDBY 16-BITHIGH·SPEED
DYNAMIC RANDOM·ACCESS.MEMORIES
SMHS188C -AUGUST 1882 - REVISIOD JUNIO 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued) (see Note 5)
'44185·80
'44185P·80
MIN
MAX
'44185·70
'44185p·70
MIN
MAX
'44185·80
'44185P·80
MIN
UNIT
MAX
tcAH
tDHR
Hold time, column address after eAS low (see Note 10)
10
15
15
Hold time, data after RAS low (see Note 13)
30
35
ns
toH
Hold time, data after ~ low (see Note 10)
10
35
15
15
ns·
ns
tAR
Hold time, column address alter RAS low (see Note 13)
30
1RAH
Hold time, row address after RAS low
10
35
10
35
10
tRCH
Hold time, reed alter ~ high (see Note 14)
0
0
0
tRRH
Hold time, reed after RAS high (see Note 14)
0
0
0
ns
ns
ns
twCH
Hold time, write after ~ low (see Note 14)
Hold time, write after RAS low (see Note 12)
10
15
15
ns
30
35
35
ns
5
5
5
twCR
ns·
tcLCH
tAWD
Hold time, eAS low to eAS high
Delay time, column address to xW low (see Note 15)
55
85
70
ns
·ns
tcHR
Delay time, RAS low to ~ high (see Note 11)
15
15
20
ns
tcRP
Delay time, ~ high to RAS low
0
0
0
ns
tcSH
Delay time, RAS low to ~ high
60
70
80
ns
tcSR
Delay time, CAS low to RAS low (see Note 11)
10
10
10
ns
tcwo
Delay time, ~ low to xW low (see Note 15)
40
50
50
ns
toEH
Hold time, OE command
15
20
20
ns
toED
tROH
Delay time, OE high before data at DQ
20
20
Deley time, OE low to J!iAS high
15
10
ns
ns
tRAO
Deley time, RAS low to column address (see NOIe 16)
15
tRAL
Deley time, column address to RAS high
30
teAL
Delay time, column address to eAS high
30
tRCD
Delay time, J!iAS low to ~ low (see Note 16)
20
tRPC
Delay time, RAS high to ~ low (see Note 11)
0
0
0
IRSH
tRWO
Delay time, eAS low to J!iAS high
15
2ci
20
ns
Delay time, RAS low to xW low (see Note 15)
65
100
110
ns·
ns
10
30
15
.10
35
35
35
45
20
15
40
50
20
ns
ns
40
40
ns
60
ns
ns
tePR
Pulse duration, ~ precharge before self refresh
0
0
0
tRPS
Pulse duration, RAS precharge alter self refresh
110
130
150
ns
tRASS
Pulse duration, self refresh entry from RAS low
100
100
100
(.IS
teHS
.HoId time, ~ low after RAS high (for self refresh)
tREF
Refresh time Interval
IT
Transition time
NOTES: 5.
10.
11.
12.
13.
14.
15.
16.
-50
-50
1'44165P
2
16
16
128
50·
128
128
llmlrlg measurements are referenced to VIL max and VIH min.
Referenced In the later of ~ or xW in write operations
EarIy-write operation only
CBR refresh only
The minimum value is measurad when IRCD is set to IRCD min as a reference.
Either tRRH or tRCH must be setisfied for a read eyele.
Read-modify-write operation only
Maximum value specified only to assure acceas time
~.1ExAs
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON, TEXA11772I1-1443
ns
-50
16
1'44165
2
50
2
50
ms
ns
TMS44165, TMS44165P
262144-WORD BY 16-BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHSl68C-AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INf:ORMATION
1.31 V
VCC-SV
Output Under Teet -
Output Under Teet
CL-100pF
(e.. NoteA)
.......----i
CL-100pF
(..eNoteA)
1_
(e) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL Incluctee probe and fixture capacitance.
Figure 1. Load Circuits for Timing Parameter.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
4-81
,
TMS44165, TMS44165P
2621440WORDBY 16-BIT HIGH-SPEED
DVNAMICRANDOM-ACCESS MEMORIES
SMHSl66C - AUGUST 1992 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
NOTE B: Output can go from the high-Impedance state to an Invalid data state prior to the specified access time.
Figure 2. Read-Cycle Timing
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 772lI1-1443
TMS44165, TMS44165P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS186C-AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~~!~~~C~;~
t Either UW or [Vi can be brought low, and the user can write Into eight OQ locations; UWend UN can be brought low at the same time and all
18 OQ locations are written Into.
All DQ pins remain In the hlgh-impedanca state for an early write cycle.
*
Figure 3. Early-Write-Cycle Timing
'!IlEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
4-83
TMS44165, TMS44165P
262144-WORD BY 16-81T HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHSl66C- AUGUST 1992 - REVISED JUNE 1895
PARAMETER MEASUREMENT INFORMATION
14
twc
_ _"",' 14
j\i
Y: .
.
tr...j ~.
lol
~
tRSH
I ~ tRCO ~
I jill
.teSH
~I
IltASCI4
I loll
I tAR
tRAH~ I+-
~.~R
14 I
teRP----.I
,
I
~ ;..'...,jl......_ _ _ _ _ _""'"
teAS
~
0:
III
I .14......1~-- tep
.1
I
,I
i'--
---.~
I.!
lRAL
'IteAL
14
1\
----I . . . ._--
"1
N
I
14-- tRP
,
N
jill
I
~
~
tRAS
.!
I.
"-A8~ CoMo.: ~QQQ§fe'f;;~.----lRAo
. uW,LWt
I
jill
~
I
14
14
tos~ l.+
1
1 toHR
ItwCR
j4
14
I
~ii~~*~:§w(
1
j4-toED-+I
,.
~
~
~
I
,
.r
AOOOOOOO(~~~~~~~:~
See Not. A
!.-- tOH
, (s•• Not. A)
_I'
.
teWL
tRWL
Q0§§:;~'r~*:~
,
OQO-OQ1S*
14-
teAH-.I
~
I
I
~
~twP~
VaIf80n
~:Diz'r;Y::~
14-- toEH ~
.
~;~t*;~
OEW
t Either OW or IW can be brought low, and the user can write Into eight DQ locations; UW and LW can be brought low at the same time and all
18 DO locations are written into.
All DQ pins remain in the high-impedance atate for an early write cycle.
NOTE A: Later of CAS or xW in write operations.
*
.
Figure 4. Write·Cycle Timing
~1ExAs
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON. TEXAS 77251-1443
.
TMS44165, TMS44165P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHSl66C - AUGUST 1892 - REVISED JUNE 1895
PARAM~TER MEASUREMENT INFORMATION
~
~
: 14
RAS-----:!lN
-1 i4-
I j4-
I~
If
tRCD
~I:
tRAS
.
tr
~
~
1~
tRSH
teAS
-.Ij4
I
~ l4-+~~I
teSH
I:'---~H
N
W
I !+-+
I ~ASR~ I4-i
j4- IRAH I I
I
~i
tRP
-.I
1'1:
~
I +tcp~
I
-i-.!
teRP
I
j4--- teWL ~
teAH
I
I
_. ~ . . :,«~'m.~=~
~
i4
tASC I
IRcs
~
-.I I4-t
I
14
~!
,
teAC
I
DQO-DQ15*~~*~~~~:~
tRWD
-'
-.:
Valid Out
I
14-
~
~--_/
I
Ii-
teWD
14-- tRAC ~
toEA ~
----.I
I j4- twp ~
~
uw.LWt§{En~:e:;:w ~
tRWL
~
I
~I
~ toH
~*~'r*~:m
14- los I
valldln
~~~~~C~~~
toED
t Either I.JW or LW can be brought low, and the user can write Into eight DO locations; I.JW and LW can be brought low at the same time and all
*
18 DO locations are written into.
All DO pins remain In the hlgh-Impedanca state for an early write cycle.
Figure 5. Read-Modlfy-Wrlte-Cycle Timing
~1ExAs
INSTRUMENTS
. POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
4-85
TMS44165, TMS44165P
262144-WORD BY1&-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS188C-AUGUST 1882- REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
NOTES: A. Output can go from the high-impedance state to an invalid dsta state prior to the specified access time.
B. A write cycle or read-modify-write cycle can be mixed wHh the read cycles es long es the write and read-modify-wrlte timing
specifications are not violated.
C. Access time is tePA or 1M dependent.
Figure 6. Enhanced-Page-Mode Read-cycle TIming
~ThxAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 772111-1443
TMS44165, TMS44165P
262144-WORD BY 16-BI1 HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS168C-AUGUST 1992 - REVISED JUNE 1995
NOTES: A. Later of CAS or )IM/ In write operations.
B. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read and read-modlfy-wrlte timing
specifications are not violated.
Figure 7. Enhanced-Page-Mode Write-Cycle TIming
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON.1'EXAS77251-1443
4-87
TMS44165, TMS44165P
262144-WORD BY 16-BIT HIGH·SPEED
DYNAMIC RAN DOM·ACCESS MEMORIES
SMHS186C-AUGU.ST 1992- REVISED JUNE 1996·
PARAMETER MEASUREMENT INFORMATION
DQO-DQ16 ------~I(XX
01__r-
-.I
teu
toEA
valid
lOut
I
~l.-toEZ .~I..---tt+-totoEEHH ~~
I
I
I
I
"--/.......---...,.~~~~~
NOTES: A. Output can go from the hlgh·lmpedance state to an Invalid data state prior to the specilled access time.
B. Aocess time Is tePA or tM dependent.
C. A reed or write cycle can be intermixed with read·modily·wrlle cycles IS long IS the read and write cycle timing specifications are
.
~~~
Figure 8. Enhanced-Page-Mode Read-Modlfy-Wrlte-Cycle Timing
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS44165, TMS44165P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS188C-AUGUST 1992 - REVISED JUNE 1895
CAl
§@§§C~*~:~e~~::w'
.: I
iAsR~ ~tRAH
I
I
AIJ-AIa
~m~:~;~~i:~~::~:~~~·
W
,«~:~~~;:t~te;~~;:X
Row
Row
UW.LW~::~:~X~~:~
DQO-DQ15~::~;f.X¥'~e:~
OE~:e:~x~e:~
Figure 9. RAS·Only Refresh TIming
j
~ThxAs
.INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 772t51-1443
4-89
TMS44165, TMS44165P
.
262144-WORDBY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHSl68C- AUGUST 1982 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Figure 10. Hldden-Refresh-Cycle Timing
~ThxAs
4-90
INSTRUMENTS
POST OFFlCE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS44165, TMS44165P
262144-WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS166C-AUGUST1992-REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~~-----------------~c----------------~~
~ ~p ---.! 14
I
RAS
Ii~
---I
I
CAS
I~~I·===~~~~_-_-_-__~_~_-_-_-_-_-_-_-_-_-_-_-~:I~
N.
Y I~-----I
l-
-ti ..-tr
~pc --.I ~
: 1~!4----tcHR _ _ _ _.~
ytcSR~
Y
~-~15-------------------------H~------------------------Figure 11. Automatic CBR-Refresh-Cycle Timing
~1ExAs
INSTRUMENTS
POST OFFicE BOX 1443 • HOUSlON. TEXAS 77251-1443
4-91
TMS44165, TMS44165P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS188C - AUGUST 1992 -REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
AO-AS
xW
~}i2t~a!::~
OE
~:e:?'1:¥-*:~
OOO-DQ15
~--------HI.z-------------Figure 12. Self-Refresh-Cycle Timing·
device symbolization (TMS44165 Illustrated)
T-!,!
)
Speed ( -60, - 70, -SO)
Low-Power/Self·Refreah Dolgnator (Blank or p)
TMS44185 ~
W
B
Y
M
T+
Package Code
Aaembly Site Code
Lot Tracaability Code
Month Code
YaarCode
Ole Revision Code
Wafer Fab Code
~TEXAS .
4-92
INSTRUMENTS
POST OFFICE BOX'_ • HOUSTON, TEXAS 7725'-'_
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
1995
This data sheet is applicable to all TMS45160/Ps
symbolized with Revision "D" and subsequent
revisions as described on page 4-113~
• Organization ••• 262144 x 16
• S-V Supply (:t:10% Tolerance)
• Performance Ranges:
ACCESS ACCESS ACCESS READ OR
~ME
~ME
~ME
WRnE
tRAC
'45160/P-60
'4516O/P-70
'4516O/P-60
tcAC
tAA
CYCLE
MAX
MAX
MAX
MIN
80 n8
70 ns
80 ns
15 n8
20 ns
20 ns
30 ns
35 n8
40 n8
110 ns
130 ns
150 nil
• Enhanced-Page-Mode Operation With
xCAS-Before-RAS (xCBR) Refresh
• Long Refresh Period
512-Cycle Refresh In 8 ms (Max)
64 ms Max for Low Power With
Self-Refresh Version (TMS45160P)
•
•
•
•
3-State Unlatched Output
Low Power Dissipation
Texas Instruments EPIC'" CMOS Process
All Inputs, Outputs, and Clocks Are TTL
Compatible
• High-Reliability, 4O-Lead, 4OO-MII-Wlde
Plastic Surface-Mount (SOJ) Package and
4O/44-Lead Thin Small-Outllne Package
(TSOP)
• Operating Free-Air Temperature Range
O·Cto70·C
DGEPACKAGE
(TOP VIEW)
DZPACKAGE
(TOP VIEW)
Vee
000
001
002
003
Vee
004
005
006
007
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
Iii 13
RAS 14
NC 15
AO 16
A1 17
A2 18
A3 [ 19
Vee [20
• Low Power With Self-Refresh Version
• Upper and Lower Byte Control During Read
and Write Operations
4O~
Vss
0015
0014
37 0013
36~ 0012
39~
38~
Vss
35
34
33
32
31
30
29
28
27
26
25
24
23
0011
0010
DQ9
Dae
NC
LCAS
UCAS
OE
Vee
000
001
002
000
Vee
DQ4
005
Dae
007
NC
NC
W
AS
A7
RAS
A6
NC
A5
AO
22 A4
A1
Vss
21
A2
A3
Vee
1
2
3
4
5
8
7
8
9
10
13
14
15
18
17
18
19
20
21
22
44
Vss
43
0015
0014
0013
0012
42
41
40
39
38
37
36
35
Vss
0011
0010
009
DOS
32
31
30
29
28
27
28
25
24
_NC
LCAS
23
Vss
UCAS
OE
AS
A7
A6
A5
A4
PIN NOMENCLATURE
AO-AS
DQO-DQI5
I£AS
Ne
~
RAS
UCAS
Vee
Vss
iii
Address InpU18
Data In/Data Qui
Lower Column-Address Strobe
No ln1emal Connection
Ou1pul Enable
Row-Address Strobe
Upper Column-Address Strobe
S-VSupply
Ground
Writs Enable
description
The TMS45160 series are high-speed. 4194304-bit dynamic random-access memories organized as 262144
words of 16 bits each. The TMS45160P series are high-speed. low-power. self-refresh 4194304-bit dynamic
random-access memories organized as 262144 words of 16 bits each. They employ state-of-the-art EPIC ™
(Enhanced Performance Implanted CMOS) technology for high performance. reliability. and low power at low
, cost.
These devices feature maximum RAS access times of 60 ns. 70 ns. and 80 ns. Maximum power dissipation
is as low as 770 mW operating and 11 mW standby on 80-ns devices. All inputs and outputs. Including clocks.
are compatible with Series 74 TTL. All addresses and data-in lines are latched on chip to simplify system design •
. Data out is unlatched to allow greater system flexibility.
'
The TMS45160 and TMS45160P are each offered in a 4O-Iead plastiC surface-mount SOJ package (DZ suffix)
and a 4O/44-lead plastic surface-mount small-outline (TSOP) package (DGE suffix). These packages are
characterized for operation from O·C to 70·C.
EPle Is a trademark of Texas Instruments IncOrporated.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
Copyright C 1885. Texas Instruments Incorporated
4-93
TMS45160j TMS45160P
262144-WORD BY 16-BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS180D -AUGUST 1892 - REVISED JUNE 1986
operation
dual CAS
Two Cts{'ns (lCAS-UCAS) are provided to give independent control of the 16 data I/O pins (OQO-OQ15)
with ~ A corresponding to OQO-OQ7 and UCAS corresponding ts OQ8-0Q15. For read or write cycles, the
column address is latched on the first xCAS falling edge. Each xCA going low enables its corresponding OQx
pins with data associated with the column address latched on the first falling ~ edge.:1 address setup and
hold parameters are referenced to the first falling xeAS a:8e'J"e delay time from xCA low to valid data out
(see parameter tcAC) is measured from each individual A to its corresponding OQx pins.
In order to latch in a new column address, both xCAS pins must be brought high. The column precharge time
(see parameter lop) is measured from the last xCAS rising edge to the first falling xCAS edge of the new cycle.
Keeping a column address valid while toggling xeAS requires a minimum setup time, loLCH' During tCLCH, at
least one xeAS must be brought low before the other ~ is taken high.
For early-write~es, the data is latched on the first falling edge of xCAS. Only the OQs that have the
corresponding iCAS low are written into. Each xCAS must meet loA~inimum in order to ensure writing into
the storage cell. .In order to latch a new address and new data, both AS pins must go high and meet lop.
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum
number of columns that can be accessed is determined by the maximum RAS low time and the xCAS
page-mode cycle time used. Wrth minimum xCAS page cycle time, all 512 columns specified by column
addresses AO through AS can be accessed without intervening RAS cycles.
Unlike conventional page~mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches whilEi xCAS is high. The first falling edge
of xCAS latches the column addresses. This feature allows the devices to operate at a higher data bandwidth
than conventional page-mode parts because data retrieval begins as soon as column address is valid rather
than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after tRAH (row-address hold time) has been satisfied, usually
well in advance of the falling edge of~.ln this case, data is obtained afterloAC max (access time from xCAS
low) if tAA max (access time from column address) has been satisfied. In the event that column addresses for
the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle is determined
by tePA (access time from riSing edge of the last xCAS).
address (AD-AS)
Eighteen address bits are required to decode 1 of 262144 storage cell locations. Nine row-address bits are set
up on AO through AS and latched onto the ch! by RAS. Then, nine column-address bits are set up on AO through
AS and latched onto the chip by the first x AS. All addresses must be stable on or before the falling edge of
RAS and xeAS. RAS is similarto a chip enable in that it activates the sense amplifiers as well as the row decoder.
xCAS is used as a chip select, activating its corresponding output buffer and latching the address bits into the
column-address buffers.
write enable (W)
,The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects
the write mode. W can be driven from the standard TTL circuits without X&u~up resistor. The data input lines
are di1.abled when the read mode is selected. When W goes low prior to A (e~ write) '. data out remains
in the high-impedance state for the entire cycle, permitting a write operation with OE grounded.
~TEXAS
4-94
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D..., AUGUST 1992 - REVISED JUNE 1995
data In (DQO-DQ15)
Data Is written during a write or read-modIfy-write cycle. Depending on the mode of operation, the failing edge
of XCAS or W strobes data Into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data Is strobed in by the first occurring xCAS with setup and hold times referenced to data in. In a
delayed-write or read-modify-write cycle, XCAS is already low and the data is strobed in by W with setup and
hold times referenced to data in. In a delayed-write or read-modify-write cycle, DE must be high to bring the
output buffers to the high-impedance state prior to impressing data on the 1/0 lines.
data out (DQO-DQ15)
The 3-state output buffer provides direct TIL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating)
state until xCAS and DE are brought low. In a read cycle, the output becomes valid after the access-time interval
tcAC (which begins with the negative transition of xCAS) as long as tRAC and tAA are satisfied.
output enable (OE)
DE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing DE low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into the
low-impedance state. They remain In the low-impedance state until either OE or xCAS is brought high.
RAS-only refresh
A refresh operation must be performed at least once every 8 ms (64 ms forTMS45160P) to retain data. This
can be achieved by strobing each of the 512 rows (AO-AS). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS-only operation can be used by holding all xCAS at the high (inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This Is accomplished by hs'ding
xCAS at V,l after a read operation and cycling RAS after a specified precharge period, similar to a RA -only
refresh cycle. The external address is ignored and the refresh address is generated internally.
xCAS-before-RAS (xCBR) refresh
xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter tcSR) and holding
it,low after RAS falls (see parameter tcHR). For successive xCBR refresh cycles, xCAS can remain low while
cycling RAS. The external address is ignored and the refresh address is generated internally.
A low-power battery-backup refresh mode that requires less than 5OO-!lA refresh current is available on the
TMS45160P. Data integrity is maintained using xCBR refresh with a period of 125 JAS holding
RAS low for less than 1 JAS. To minimize current consumption, all input levels must be at CMOS levels
(V'l $ 0.2 V, V,H :It VCC - 0.2 V).
self refresh (TMS45160P)
The self-refresh mode is entered by dropping xCAS low prior to RAS going low. Then xCAS and RAS are both
held low for a minimum of 100 JAS. The chip is refreshed internally by an on-board oscillator. No external address
is reqtgt since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and x A are brought high to satisfy tcHS. Upon exiting the self-refresh mode, a burst refresh (refresh a full set
of row addresses) must be executed before conth1uing with normal operation. This ensures that the DRAM is
fully refreshed.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON, TEXAS mSI-I443
4-95
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS1800-AUGUST 11192 - REVISED JUNE 1995
power up
To achieve proper device operation. an initial pause of 200 jA.8 followed by a minimum of eight RAS cycles is
~red after~r up to the full Vee level.These eight initialization cycles must include at least one refresh
(RAS-only or xCBR)cycJe. .
~1ExAs
4-98
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 772S1~1443
TMS45160, TMS45160P
262144-WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS180D-AUGUST 11182 - REVISED JUNE 1895
logic symbol t
RAM258K1C18
AD
A1
18
2OD8/21DO ...
17
18
A2
18
Ita
A4
22
> A2820143
23
M
24
M
A7
AS
28
28
14
28
2OD17121D8
~
~ •
23C22
~ •
23032
>C20[ROW(
Q231[REFRESH ROW]
24[PWRDWN]
> C21
024
31
28
> 021
034
r .,
31
Z31
13
27
DQO
2
DQ1 3
4
23,21D
....
4-
t
24,25EN27
34,25EN37
025
A,22D
V 28,27
r
A,D8
t-
DOZ
DQ3 5
DQ4 7
005 8
DQ8 8
10
DQ7
31
DQI
DQ8 32
DQ10
DQ11
DQ12
0013
0014
0015
A,32D
4- V 38,37
A,Z38
33
34
38
37
38
38
tThIa symbolla in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 817-12.
The pin numbers shown are for the DZ package.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOU8TCN. TEXAS 77251-1443
4-97
TMS45160, TMS45160P
262144-WORDBY 16-BJTHIGH~SPEED
DYNAMIC RANDOM~ACCESS MEMORIES
SMHS160D -AUGUST 1992 - REVISED JUNE 1996
functIonal block dIagram
AO
A1
AS
Column Decod.
•
•
•
•
•
•
Sen.. Ampllfl...
ColumnAcId....
Bulte..
128KArray
128KArray
18
••
•
RowAcId....
Bulte..
128KArray
R
0
w
D
•c
128KArray
••
•
0
d
•
128KArray
128KArray
absolute maxImum ratIngs over operatIng free-aIr temperature range (unless otherwIse notec:l)t
Supply voltage range, Vee ........................................................... -1 V to 7 V
VoHage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Short-circuit output current .•....••.•••••••••••••...••.•••••.••••••••.•.••••.••• ;.......... 50 mA
Power dissipation ••.........•....•..•.•..•••.••••...•......••...•....•..•.•.•..•••..•••.••• 1 W
Operating free-air temperature range, TA .•••...•••.••..••••••••••.•.•••.•..•..•.•....• O°C to 70°C
Storage temperature range, Tstg .................................................. - 55°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" Is not
Implied. Exposure to absolute-maximum-rated conditions for axtended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operatIng condItIons
MIN
NOM
MAX
4.5
5
5.5
vee
Supply voltage
VSS
VIH
Supply voltage
High-level input voltage
2.4
6.5
VIL
Low-level Input voltage (888 Note. 2)
-1
0.8
UNIT
V
V
0
V
V
·e
Operating fres-air temperature
0
70
TA
..
NOTE 2: The algebraiC convention. where.the more negatIVe (less positive) limit· .IS designated es mlmmum. is used for logic-voltage levels only.
~TEXAS .
4-98
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS45160, TMS45160P
262144-WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHSl60D - AUGUST 1992 - REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating fre..alr
temperature (unless otherwise noted)
PARAMETER
TEST CONDmONS
'45180-80
'45180P-80
'46180-70
'45180P-70
'45180-80
'45180P-80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
VOH
High-level output
voltage
VOL
voltage
10L= 4.2 mA
0.4
0.4
0.4
V
Input current
(leakage)
V, =OVto8.5V.
Vce 5.5 V,
All others. 0 V to Vce
=
:t10
:t10
:t10
IIA
10
Output current
(leakage)
CAS high
:t10
:tl0
:tl0
IIA
lcel t •
Reed- or wrIIe-cycIe
current
VCC .. 5.5V.
180
160
140
mA
2
2
2
mA
1
1
1
mA
"
1CC2
Low-level output
Standby current
2.4
IOHa-5mA
Vce= 5.5V.
VO .. OVtoVce.
Minimum cycle
2.4
V,H .. 2.4 V (TTl).
After 1 memory cycle,
RAS and iCAS high
V,H .. VCC - 0.2 V (CMOS),
After 1 memory cycle.
RAS and xCAS high
'45160
'45160P
2.4
V
350
350
350
IIA
180
180
140
mA
160
140
120
mA
Icca*
Average refresh
current (FiAS-on1y
refresh or CBR)
Minimum cycle,
VCC = 5.5 V,
(RASonly),
RAScycling,
iiCAS high (CBR only),
RAS low after iCAS low
1CC4t1
Average page current
Vce .. 5.5V,
RASIow.
Ices'
Battery-backup
operating current
(equivalent refresh
time is 84 ma):
CBRonly
tRC .. 125 j.s,
1RAS"1 ....
VCC - 0.2 V " V'K.! 6.5 V,
o V" V'L" 0.2 V,· W and Of. V'H,
Address and data atable
500
500
500
IIA
Iccet,
Self-refresh current
iiCAS < 0.2 V, RAS<0.2V,
fRAs and teAs > 1000 ma
400
400
400
~
tpC·MIN.
iiCAS cycling
t Measured with outputs open
Meaaured with a maximum of one address change while RAS .. V,L
• Measured with a maximum of one address change while iCAS .. V,H
*
, For TMS45180P only
capacitance over recommended ranges of supply voltage and operating free·alr temperature,
f = 1 MHz' (see Note 3)
PARAMETER
MIN
MAX
UNIT
CiOO
Input capacitance, AO-AS
5
pF
Ci(OE)
Input capacitance, OE
7
pF
CIIRC}
Input capacItanca, xCAS and RAS
pF
CIIWl
Input capacitance. W
7
7
Co
Outputcapacltanca
7
pF
pF
II CapacItanca measurements are made on a sample basis only.
NOTE 3: Vce. 5 V ::t 0.5 V, and the bias on pins under test ia 0 V.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. leCAS 77251-1443
4-99
TMS4S160, TMS4S160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS18OD-AUGUST 1882-REVlSED JUNE 1996
switching characteristics over recommended ranges of supply voltage and operating fre...lr
temperature
.
PARAMETER
tcAc
Access time from ~ low
1M
Access time from column address
Access time from RA! low
'46160-60
'4616OP-60
'46160-70
'4616OP-70
MIN
MIN
MAX
15
30
60
15
35
'46160-60
'4616OP-80
MAX
MIN . MAX
20
20
35
70
40
60
20
20
UNIT
ns
ns
ns
ns
ns
!RAc
toEA
tePA
Access time from l>E low
Access time from column precharge
teLZ
Delay time, iCAS low to output In low Impedance
0
toFF
Output disable time after iiCAS high (see Note 4)
0
15
0
20
0
20
ns
0
15
0
20
0
20
ns
toEZ Output disable time after l>E high (see Note 4)
NOTE 4: toFF and toEZ are specified when the output Ie no longer driven.
40
46
0
ns
0
timing requirements over recommended ranges of supply voltage and operating fre...lr
temperature (see Note 5)
'46180-60
'46160P-60
tRC
twc
tRWC
tpC
tPRWC
MIN
110
Cycle time, read (see Note S)
Cycle time, write
Cycle time, read-write/read-modlfy-wrlte
~
'46160-70
'46160P-70
'46160-80
'4616OP-80
MIN
130
110
130
MIN
150
150
155
185
206
40
85
45
90
50
105
60 100000
70 100000
60
70
20
Cycle time, page-mode read or write (see Note 7)
Cycle time, pege-mode read-modify-wrlte
tRASP Pulse duration, RAS low, page mode (see Note 8)
tRAS . Pulse duration, RAS low, nonpege mode (see Note 8)
Pulse duration, ~ low (see Note 9)
teAs
15
10
40
15
10000
10000
MAX
UNIT
MAX
ns
ns
ns
ns
ns
80 100000
ns
10000
80
10000
20
ns
n.
10000
10000
twP
Pulse duration, iCAS high
Pulse duration, RAS high (precharge)
Pulse duration, write
lAsc
tASR
tos
Setup time, column address before xCAS low
0
0
0
Setup time, row address before RA! low
Setup time, data before Wlow (see Note 10)
0
0
0
0
ns
0
0
n.
tep
lAp
ns
15
10
80
15
ns
10
50
ns
ns
tRCS
Setup time, read before ~ low
0
0
0
tcWL.
Setup time, W low before iiCAS high
15
20
20
ns
tRWL.
Setup time, Wlow before RA! high
15
20
20
ns
0
0
0
ns
twcs Setup time, W low before xCAS low (see Note 11)
NOTES: 5. Timing measurements are referenced to VIL max and VIH min.
6. All cycle times assume tr =5 ns.
7. To assure tpc min, tASC should be :0 teP.
.
6. In a read-modlfy-wrlte cycf" tRWO and tRWL must be obse!ved.
9. In a read-modlfy-wrlte cycle, tcwo and tcwL must be observed.
10. Referenced to the later of iiCAS or Win write operations
11. EarIy-wrlte operation only
~TEXAS .
4-100
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
ns
TMS45160, TMS45160P
262144-WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS180D -AUGUST 1992 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued) (see Note 5)
'45160·60
'45160P·60
'45160·70
'45160P·70
'45160·60
'45160P·60
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tcAH
Hold time, column address efter xCAS low (see Nole 10)
10
15
15
na
IDHR
Hold time, date after RAS low (aee Note 12)
30
35
35
ns
toH
Hold time, date after iiCAS low (see Note 10)
10
15
15
na
iAR
Hold time, column address after RAS low (see Note 12)
30
35
35
ns
iRAH
Hold time, row address after RAS low
10
10
10
ns
tRCH
Hold time, read after xCAS high (see Note 13)
0
0
0
ns
iRRH
Hold lime, reed after RAS high (see Note 13)
0
0
0
na
twCH
Hold time, write after XCAS low (see Note 13)
10
15
15
ns
twCR
Hold time, write after RAS low (see Note 14)
30
35
35
ns
teLCH
Hold time, xCAS low to xCAS high
5
5
5
ns
IAwe
Delay time, column address to W low (see Note 15)
55
65
70
ns
teHR
Delay time, RAS low to xCAS high (see Note 11)
15
15
20
ns
teRP
Delay time, XCAS high to RAS low
0
0
0
ns
tcsH
Delay time, RAS low to xCAS high
60
70
80
ns
teSR
Delay time, xCAS low to RAS low (see Note 11)
10
10
10
ns
teWD
Delay lime, xCAS low 10 W low (see Note 15)
40
50
50
ns
toEH
HQld time, OE command
15
20
20
ns
toED
tROH
Delay time, OE high before date at DO
15
20
20
ns
Delay time, OE low to RAS high
10
10
10
iRAD
tRAL
Delay time, RAS low to column address (see Note 16)
15
Delay time, column address to RAS high
30
15
35
35
15
ns
40
ns
na
teAL
Delay lime, column address to iiCAS high
30
30
iRCD
tRPC
Delay time, RAS low to xCAS low (see Note 18)
20
Delay time, RAS high to XCAS low (see Note 11)
0
0
0
ns
tRSH
Delay time, xCAS low to RAS high
15
20
20
ns
tRWD
Delay time, RAS low to W low (see Note 15)
85
100
110
na
tePR
tRPS
Pulae duration, iiCAS precharge before self refresh
0
0
0
ns
Pulse duration, RAS precharge after self refresh
110
130
150
ns
tRASS
Pulse duration, self refresh entry from RAS low
100
100
100
j.tS
tcHS
Hold time, xCAS low after RAS high (for aelf refresh)
-50
-50
-50
ns
iREF
Refresh time Interval
ty
Transition time
NOTES; 5.
10.
11.
12.
13.
14.
15.
18.
40
35
45
20
ns
40
50
20
60
1'45180
8
8
8
l'45160P
64
64
64
2
50
2
50
2
50
ns
ms
ns
TIming measurements are referenced to VIL max and VIH min.
Referenced in the later of iiCAS or iii In write operations.
Ear1y-write operation only
The minimum value Is measured when tRCD Is set to tRCD min as a reference.
Either tRRH or iRCH must be satisfied for a read cycle.
xCBR refresh only
Read-modlfy-write operation only
Maximum value apecified only to assure access time
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOU81ON. TEXAS n2S1-1443
4-101
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS1800 - AUGUST 1992 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
1.31 V
VCC=5V
R1 =828Q
Output Under Tnt -
Output Uncler Teet
CL-100pF
(_NoteA)
......----1
T
(b) ALTERNATE LOAD CIRCUIT
(a) LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
Figure 1. Load Circuits for Timing Parameters
~1ExAs .
4-102
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 772111-1443
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS180D-AUGUST 11192-REVISED JUNE 1l1li5
PARAMETER MEASUREMENT INFORMATION
w
DQO-DQ15
~~:M
I
14
I
leLZ
L
Li!
k- ~
i!
I lAA ~
~
14-- 'oFF ~
See ~ote B
~.,'
'RAe
~
jf-'oEA~
\[
valid Date
ou~
~.
I
,IROH
:'
I
"«:¥o:cEd§
I
)>------~'oEZ
---)"1;!!!I-------
NOTES: A. In order to hold the add.... latched by the first XCAS going low, the parameter tcLCH must be met
B. Output can go from the high-impedance state to an invalid-date state prior to the specified access time.
C. tcAc Is measured from XCAS to Its corresponding DQx.
D. XCAS order Is arbitrary.
Figure 2. Read-Cycle 11mlng
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77281-1443
4-103
TMS45t60, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM..ACCESSMEMORIES
SMHS180D - AUGUST 1992::- REVISED JUNE 1985
PARAMETER MEASUREMENT INFORMATION
j4
RAS
~
~
IT - , I4--IRCD ~
II
l\~teAS---y
!~
I I
II
I
I I
/4+tASR
/4
I
LCAS
-1I
I
I
I
I
AO-AS
T\"""----
(He Note A)
jill
-II"
~ j4
I
~
I
I
I
I
I
IRSH
.I
I
I
I
I
I
~
tAR
~
teRP
~
~'I
~.~
I
--.I
-~
I I
~
I
~
tRWL
~~~~~*~~r*~~re:~~~
~
1!4II
twP~
I /4
~ tDH (8" Note B)
""'"
toED
I
j4-- teWL -----.I
twCR
r--.-I
I
I
I
~~~r~·~~
~
I
14- teAH
~
DQO-DQ1S - -.......
~~ ~
I I
j
~
....
~.~
~
I los
1f/1111--..;..toEH ---..,.~~\
'-._________
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tcLCH must be met.
B. Leter of XCAS or iN In write operations
•
C. xCAS order Is arbitrary. .
Figure 3. Write-Cycle TIming
~TEXAS
4-104
~I
I
I
I
tep -;-1-~
1
I
=>< ~ ~-~~4rE.~_~
I
I
I
.
I
H-teLCH
I
\.,
I I
'k
I teSH
!.-.LI /4
I I IRAH
I I
I I IASc -l++I I
II
/l1li
I
teAL
I
I
I.-IRAD --..l
OE
I
~
I 14- tRP-.I
I
IIII
I
W
rr·
twc
INSTRUMENTS
·POST OFFIC~ BOX 1443 • HOUSTON. lEXAS 77251-1443
TMS45160, TMS45160P
262144-WORD BY 16-BI1 HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHSl80D - AUGUST 1982 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
AO-AIJ
DQO-DQ15
NOTES: A. In order to hold the addr.a latched by the first xeAS going low, the parameter felCH must be met.
B. xeAS order Is arbitrary.
Figure 4. Early-Wrlte-Cycle nmlng
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 772111-1443
4-105
TMS45160, TMS45160P
262144-WORD BY 16-BI1 HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS1800~AUGUST1982-REVISED;lUNE1995
PARAMETER ME:ASUREMENT INFORMATION
AO-Aa
DQ8-DQ15
DQO-DQ7
NOTES: A. In order to hold the address latched by the first xeAS going low, the parameter tcLCH must b8 met.
B. Output can go from the high-Impedance state to an invalld-dsta state prior to the specified access time.
C. xeAS order Is arbitrary.
.
Figure 5. Read-Modlfy-Write-Cycle nmlng
4-106
-!i11ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 772111-1443
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS180D-AUGUST 1992-REVlSED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
I'll
lAp
~
~1'-~t-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-:.lRAS
__P::::::::::::::::::_-_-_-_-t_rfl\14-- teRP I:
I j4-IACD -.!
::
~ll ·/
II
I I
~
N
,I,
-----+I·,--Vi
J4--*-lAsR
I ' : teAS ~
I
I I
teAH
teAC ---.,
I
14+-+-1-lAA
~
tRCS -loI1--1---'" I
J
~
1
I I
I :
tRAL . ; . - - - - - -
A/\.1V\.fV\J'V\/V'
Don't Care
I
Out
8M Note B
tePA
~toFF
.,
-.I!.:I 1-
iI
~tAA~
DQO-DQ7
I'
II
I
I
~Id
.
DQ8-DQ15 - - - - - - - - - _
,{ !
I
I
I
(8n Note A)
teLZIiI
I I
"
T.-----~I+:------
l1li
Column
"---,lRAc
I
r--- teAL ~
AO-AS
Vi
~
tpc
~
~~H·
IlRAH f-t'-r-t 14 lA~C
I
!
:I
ItRSH~1
jill
l1li
I I
~f4-teP~1
I
teSH
114
~
----------_~ ~~~
to
EZ
)>---------
I
IL-- toEA
~I
~
. )
.
NOTES: A.. tcAc Is measured from ~ to Its corresponding 00x.
B. Access time Is tePA or fAA dependent.
C. A write cycle or reed-modlfy-wrlte cycle can be mixed with the reed cycles as long as the write and read-modify-write timing
specifications are not violated.
D. ~ order Is arbitrary.
E. Output can go from the hlgh-lmpedance state to an Invalid-data state prior to the specified access time.
Figure 8. Enhanced-Page-Mode Read-Cycle TImIng
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOIJSTON, TEXAS 77261-1443
4-107
TMS45160, TMS45160P
262144-WORD BY 16-BIT HI.GH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
8MH81800 -AUGUST 1l1li2 - REVISED JUNE 1885
PARAMETER MEASUREMENT INFORMATION
DQI-DQ18
---<'
:
"-
T
~
DQO-DQ7
valid In
,>----------"""'---------"-
--: If-toED
~J
NOTES: A. In order to hold the addresa latched by the first ~ going low, the parameter tcLCH must be met.
B. Referenced to ~ or Vi, whichever occul'8last
C. ~ order Is arbitrary.
D. A read cycle or reed-modlfy-write cycle can be mixed with the write cycles as long as the reed and reed-modlfy-write timing
apecIfIcatIons _
not violated.
Figure 7. Enhanced·Page-Mode Write-Cycle llmlng
~1ExAs
4-108
INSTRUMENTS
POST OffICE BOX 1+43· HOUSTON.lE(A8 77251-1443
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS180D-AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
lAp ~ j4tRASP ---------~~II I
ril
RAlN~
~1=1;te;;s;;H-=====i~:r1---;:II4I11=--=-=-=-=-:::lA:S::-H::':':':'~~ I ' - - - II ~!.:::t=~CD:::=
UCAS
1"'" -~
Iii
I~
:I
J. ~
~
II
I
tpRWC
teAS
It-_
hi
11 :
~I
1
I
I~ --te-P-----:!II
teLCH
~I·I
I
I
II
114
(sHNoteA)
LI tASR
-+lr-.
I tASe -+I~
1RAD~114
,AO-AS
0
~I
I
I
I
I
I
.~I teAH
~ Co&mn ~
lRAH ~ :... UFteWD -+I
I (8M Note B)
~I
-.I~
l4--~cH
teLZ -+j
DQO-DQ15
1+1.
Valid Out
NOTES: A.
B.
C.
D.
E.
~II'"
I.- tePA -.rI
See No.. C
~~
I
1411111--~- toEH
I
I
--------c:xx:'"
!+- toEA ---+j
I
-til
Of
II
I
los
DJ.
I
I
I
I
I
. -
I+- tcAc I ~I-~~~
lA6s -.: I I4t
I IAA ~ I
I
I
~
teWL l1li
~I I
I
~
teRP
Colum€
. r-rIAWD--.j
Qoj-~~ I I~
~
~
14 ~I jtwP
llltRWD~1
W~III
N~II
_
I
I:
~ toEH
I
I
1......___. . -
toED
II
I
1JL----.j,\___/io-----~~~~~
I
In order to hold the address latched by the first iiCA! going low, the parameter tcLCH must be met.
tcAe Is measured from il5AS to Its corresponding 00x.
Output can go from the high-lmpedance state to an invalid data state prior to the specified access time.
iCAS order is arbitrsry.
A read or wrHe cycle can be intermixed with read-modify-wrHe cycles as long as the reed and write cycle timing specifications are
not violated.
Figure 8. Enhanced·Page·Mode Read·Modlfy·Wrlte-Cycle Timing
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77261-1443
4-109
TMS45160, TMS45160P
262144-WORDBY 16-81T HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS180D- AUGUST 1892 - REVISED JUNE 1895
DQO-DQ1S
- - - - - - - - - HI"z - - - - - - - - - - -
NOTE A: All XCAS must be high,
Figure 9. RAS-Only Refresh Timing
~1EXAS
4-110
INSTRUMENTS
POST OFFICE BOX 1+43 • HOUSTON,11OOIS 77251-1+43
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS1 6OD- AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 .
4-111
TMS45160, TMS45160P
2621*WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS ·MEMORIES
. SMHS180D- AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~I~---------------~C--------------~~I
~ lAP ----+j ~I~_________ lRAS __________
+1.1 I
III
RAS
-----J!f
1
~I______
N
y
~ ~ tr
Y,--------
~pc~ ~tcsAi !4-1~---tcHA---~.1
\L
w
AD-All
~J,f~::¥,.E:~
~::~::*'~:~
~-~11------------------H~---------------------
NOTE A: Any iCAS can be used.
Figure 11. Automatlc-CBR- Refresh-Cycle Timing
(
~1ExAs .
4-112
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77211-1443
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHSl800 -AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
114
..------iRASS - - - - - - -..
~I
j
I
_---IX
I
tcSR
I
l.--iRpc
N---------....J/i*-
~
+l II
II
-+1 J4- tcHS
J~tcPR~\l
AlJ-AB
1\
tRPS-+I
~
~:~:,~X~~Fo~
W~::**!~e:~
DQO-DQ15
~--------HI.z---------------
NOTE A: Ally iQ\S can be used.
Figure 12. Self-Refresh-Cycle Timing
device symbolization (TMS45160 Illustrated)
TI
)
T~
Sp..d ( -60, - 70, -60)
Low-Power ISelf-Refraah Dealgnator (Blank or P)
TMS45160 ~
W
B
:t..
M
Package Code
T+
Aaambly SIts Code
Lot TraceabilIty Code
Month Code
Year Code
Ole RevisIon Code
Wafer Feb Code
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
4-113
TMS45160, TMS45160P
262144-0WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS1600 -AUGUST 1892 - REVISED JUNE 1995
~TEXAS
4-114
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS45165, TMS45165P
262144-WORD BY 16·BI1 HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS185C - OCTOBER 1992 - REVISED JUNE 1995
This data sheet is applicable to all
TMS45165/Ps symbolized with Revision -Band subsequent revisions as described on
page 4-134.
• Organization ••• 262144 x 16
• Single SoV Supply (:1:10% Tolerance)
• Performance Ranges:
'45165/P·70
'45165/P-80
'45165/P-l0
ACCESS ACCESS ACCESS READ OR
nME
TIME
TIME
WRITE
tRAC
teAC
tAA
CYCLE
MAX
MAX
MAX
MIN
70 ns
20 ns
35 ns
130 ns
60 ns
20 ns
40 ns
150 ns
100 ns
25 ns
45 ns
160 ns
• Enhanced Page Mode Operation With
CAS-Before-RAS (CBR) Refresh
• Long Refresh Period
512-Cycle Refresh In 8ms (Max)
64 ms for Low Power With Self-Refresh
Version (TMS45165P)
•
•
•
•
3-State Unlatched Output
Lower Power Dissipation
Texas Instruments EPICTM CMOS Process
All Inputs, Outputs and Clocks are TTL
Compatible
• High-Reliability Plastic 4O-Lead
4OO-MII-Wlde Surface Mount (SOJ)
Package, and40/44-Lead Thin Small
Outline Package (TSOP)
DGEPACKAGE
{TOP VIEW)
DZPACKAGE
{TOP VIEW)
VcC
DO0
DO 1
DO2
DO3
Vee
DO 4
DO5
DO6
DO7
NC
LW
UW
RAS
NC
A0
A1
A2
39
36
37
36
35
34
33
32
31
30
29
26
27
26
25
24
230
22
21
A3
Vc0'20
Vcc
Vss
40
1
2
3
4
5
6
7
6
9
10
11
12
13
14
15
16
17
16
19
D015
D014
D013
D012
Vss
DOll
DOlO
D09
DOS
NC
NC
CAS
OE
DOO
D01
D02
D03
Vcc
D04
D05
D06
D07
NC
LW
AS
OW
A7
RAS
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
16
19
A5
NC
AO
A4
A1
Vss
A2 20
A6
A3 21
22
Vcc
44
43
42
41
Vss
39
38
37
36
35
Vss
32
31
30
NC
NC
CAS
29
OE
D015
D014
D013
40 D012
D011
D010
D09
DOS
28 AS
27 A7
26 A6
25p A5
24p A4
23p
Vss
CAS
OQO-OQ15
LW
NC
OE
• Operating Free-Air Temperature Range
O·Cto 70·C
RAS
• Low-Power With Self-Refresh
• Upper and Lower Byte Control During Write
Operations
Vcc
Vss
UW
:E
a:
oLL
PIN NOMENCLATURE
AO-AS
z
o
~
Address Inputs
Column Addrsss Strobe
Data In/Data 0u1
Lower Write Enable
No Intemal Connection
Output Enable
Row Address Strobe
Upper Write Enable
5-VSupply
Ground
Z
W
o
Z
~
c
«
description
The TMS45165 series are high-speed, 4194304-bit dynamic random access memories organized as 262144
words of sixteen bits each.
The TMS45165P series are high-speed, low-power with self-refresh, 4194304-bit dynamic random-access
memories organized as 262144 words by sixteen bits each.
They employ state-of-ths-art enhanced performance implanted CMOS (EPIC™) technology for high
performance, reliability, and low power at low cost. These devices feature maximum RAS access times of 70
ns, 80 ns, and 100 ns. Maximum power dissipation is as low as 660 mW operating and 11 mW standby on
100 ns devices.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
EPIC Is a trademark of Texas Instruments Incorporated.
Copyright C 1995, Texas Instruments Incorporated
4-115
TMS45165, TMS45165P
2621WWORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM:'ACCESS MEMORIES
SMHS185C- OCTOBER 1992 - REVISED JUNE 1995
description (continued)
The TMS45165 and TMS45165P are each offered in a 40-lead plastic surface mount SOJ (OZ ~uffix) package,
and a 4O/44-lead plastic surface mount TSOP (OGE suffix). These packages are characterized for operation
from O·C to 70·C.
operation
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is thus eliminated. The
maximum number of columns that can be accessed is determined by the maximum RAS low time and the CAS
page-mode cycle time used. With minimum CAS page cycle time, all 512 columns specified by column
addresses AO through AS can be accessed without intervening RAS cycles.
Unlike conventional page-mode ORAMs, the column-address buffers in these devices are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge
of CAS latches the column addresses. This feature allows the TMS45165 and TMS45165P to operate at a
higher data bandwidth than conventional page-mode parts, since data retrieval begins as soon as column
address is valid rather than when CAS transitions low. This performance improvement is. referred to as
enhanced page mode. Valid column address can be presented immediately after tRAH (row address hold time)
has been satisfied, USU~IY well in advance of the falling edge of CAS. In this case. ' data is obtained after teAC
max (access time from AS low) iftAA max (access time from column address) has been satisfied. In the event
that column addresses for the next page cycle are valid at the time CAS goes hlgl;l, access time for the next cycle
is determined by the later occurrence of teAC or tePA (access time from rising edge of the last CAS).
»
c
~
o
z
m
Z
C9
address (AO-AS)
Eighteen address bits are required to decode 1 of 262144 storage cell locations. Nine row-address bits are set
up on pins AO through AS and latched onto the chip by the row-address strobe (RAS). Then nine
column-address bits are set up on pins AO through AS and latched onto the chip gy the column-address strobe
(CAS). All addresses must be stable on or before the falling edge of RAS and AS: RAS is similar to a chip
enable in that it activates the sense amplifiers as well as the row decoder. In the TMS45165 and TMS45165P
CAS Is used as a chip select activating the output buffer, as well as latching the address bits Into the
column-address buffers.
XI
s:
~
oz
write enable (UW, LW)
The read or write mode is selected through the upper or lower write-enable 0§jJ, [W) input. [W controls
OQO-OQ7, and UW controls OQ8-0Q15. A logic high on the UW and LW input selects the read mode and a
logic low selects the write mode. The write-enable terminal can be driven from the standard TIL circuits without
a pullup resistor. The data input is disabled when the read mode is selected. When UW or LW goes low prior
to CAS (early write), data out remains in the high-impedance state for the entire cycle permitting a write
operation with OEgrounded.
NOTE: Either UW or LW can be brought low in a given write cycle and only eight data bits are written Into. The
user can bring both UW and [W low at the same time and all 16 data bits are written into.
data In (DQO-DQ15)
Oata is written during a write or read-modify-write cycle. Oepending on the mode of o.E!!,ation; the falling edge
of CAS, UW, or LW strobes data into the on-Chip data latch. In an early write cycle, UW or LW is brought low
prior to CAS and the data Is strobed in by CAS with setup and hold times referenced to this signal. In a delayed
write or read-modify-write cycle, CAS is already low, the data is strobed in ~ UW or UN with setup and hold
times referenced to this signal. In a delayed write or read-modify-write cycle, OE must be high to bring the out~
buffers to high-impedance prior to impressing data on the I/O lines. The LW pin controls OQO-OQ7. The UW
pin controls OQS-OQ15.
~1ExAs
4-116
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
TMS45165, TMS45165P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS1esc - OCTOBER 1882- REVISED JUNE 1985
data out (DQO-DQ15)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data In. The output is In the high-impedance (floating) state
until CAS and DE are brought low. In a re~le the output becomes valid after the access time Interval tcAC
that begins with the negative transition of CASas long as tRAC and tAA are satisfied.
output enable (OE)
DE controls the impedance of the output buffers. When DE is high, the buffers remain in the high-impedance
state. Bringing DE low durin~orm~cle activates the output buffers, putting them In the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance
state, they remain in the low-impedance state until either OE or CAS is brought high.
'RAI-only refreah
A refresh operation must be performed at least once every eight milliseconds (64 ms for TMS45165P) to retain
data. This can be achieved by strobing· each of the 512 rows (AO-AS). A normal read or write cycle refreshes
all bits in each row that Is selected. A RAS-only operation can be used by holding CAS at the high Onactive)
level, thus conserving power as the output buffer remains In the high-Impedance state. Externally generated
addresses must be used for a RAS-only refresh.
z
o
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by hslding
-only
refresh cycle.
CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RA
CA§-befor.RAS refresh (CBR)
CBR refresh is utilized by bringing CAS low earlier than RAS (see gaseter tcSFU and holding it low after RAS
falls (see parameter tcHIV. For successive CBR refresh cycles, A can remain low while cycling RAS. The
external address is ignored and the refresh address is generated internally.
ti
:&
a::
f2
-
·Z
A low-power battery-backup refresh mode that requires less than 300 J.cA refresh current Is available on the W
TMS45165P. Data Integrity Is maintained using CBR refresh with a period of 125 1'8 holding RAS low for less (,)
than 1 1'8. To minimize current consumption, all input levels must be at CMOS levels ML" 0.2 V, VIH 2: Z
Vcc-0.2V).
~
self-refresh (TMS45165P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100 1'8. The chip Is then refreshed internally by an on-board oscillator. No external
address is required since the CBR counter Is used to keep track of the address. To exit the self-refresh mode,
both RAS and CAS are brought high to satisfy tcHS'
power up
To achieve proper device operation, an Initial pause of 20Q 1'8 followed by a minimum of eight RAS cycles is
required after power-up to the full VCC level.
~1EXAS
INSTRUMENTS
POST OFFICE 80X 1443 • HOUSTON, TEXAS 77251-1443
4-117
Q
c(
TMS45165, TMS4S165P
262144-WORD BY 16-BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
.St.ilHS1S5(: ~ cicToSER 1892 - REVISED JUNE 1895
logic symbol t
RAM256KlC18
18
AO
17
A1
18
A2
19
2009/2100
A3
22
A4
23
AS
AS
A7
AS
> A 2820143
24
25
28
,20017/2101t-
...b >C20(ROW]
RAS J.L..:
-
.,...l::> 023/[REFRESH ROW]
~
l>
+
24(PWRDWN]
"
029
.,...l::> Z31
.,...l::> >C21 [COL)
.,...l::> 024
~
~
CAS
Z
0
LW
m
-."z
0
28
12
UW 13
:a
OE
!:
27
.....
r
r
!f-
DQ1 3
DQ2 4
0
Z
23,210
23C22
+
31 "
23210
.,
29,25EN28
23C32
+
29,25EN27
..... 025
2
DQO
"
A,220
4- V28
r
A,Z28
.
r
DQ3 5
DQ4 7
8 .....
DQ5
,r
9
DQ8
10
DQ7
31
DQ8
..
DQ9
DQ10
OQ11
OQ12
DQ13
32
33
34
38
37
38
DQ14
39
DQ.15
A,320
4- V27
A,Z27
..
..
t this symbol Is In accordance with ANSVlEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown correspond to the DZ package.
~TEXAS
4-116
INSTRUMENTS
POeT OFFICE sox 1443 • HOUSTON. TEXAS 77251-1443
TMS45165, TMS45165P
262144-WORD BY 16-BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS185C - OCTOBER 1992 - REVISED JUNE 1995
functional block diagram
•• •
I
,
Il
I
AD
A1
•
•
•
L
•
R
128KArray
•
••
•
'It
~
128KArray
128KArray
18<
R_
Add.....
Buffe...
1!.
Column Decod.
S.n.. Ampllft....
Column
Add.....
Bu"'...
l-
•
l 1
TIming .nd Control
0
128KArrsy
•
w
••
D
e
r---
L±
r>18
16VO
r+-
0
128KArray
'---
~
~
18
~
Out
Reg.
I....-
d
e
'--
In
Reg.
1....-
Bu"'...
c
I
18
D.ta
f+1
128KAr...y
z
000- 0015
~
I
abs91ute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) • • • • . • • . . . • • • . . . . • . . . . . . . . . . . • • . • • . • • • • • •• - 1 V to 7 V
Supply voltage range on Vee .•.••.•••••..•..•....•.................•.••..•.•••••.•••. - 1 V to 7 V
Short-circuit output current ....•.....•..•....••.••.••.•••••.••••••.•.•........••.•..•..••' .• 50 mA
Power dissipation ••.....•••...•.•..•..•..•••••••.••.•••••.••••.•.•.•••.....••...•.•.•••.•.• 1 W
Operating free-air temperature range ••••.••.•........•..•...•....•....•.•••••••••••••• O°C to 70°C
Storage temperature range, Tstg .••.••••.••..•..•.••.••.••....•..•.•.•..••••.••.•• - 55°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" is not
Implied. Exposure to abaolute-maxlmum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
Supply voltage
VSS
V,H
Supply voltage
MIN
NOM
MAX
4.5
5
0
5.6
UNIT
V
V
Hlgh-Jevellnput voltage
2.4
6.5
Low-level input voltage (see Note 2)
-1
0.8
70
V
V
·C
Operating free..airtemperature
0
TA
NOTE 2: The algebraic convention, where the more negative pess positive) limit Is desIgnated as mlnlmum,ls used for loglc·voltage levels only.
VII.
-
-zw
'0
Z
c~
tep min + teAS min + 2tf.
In a read-modify-writecycle, tewo and teWl must be observed. Depending on the user's transition times, this can require additional
CAS low time (teAS>.
11. In a read-modify-write cycle, tRWO and tRWl must be observed. Depending on the user's transition times, this can require additional
RAS low time (~.
12. Later of ~ or xW in write operations
NOTES: 7.
8.
9.
10.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77251-1443
4-121
z
o
~
:E
a:
oLL
-wZ
o
z
c~
c
z~
n
m
'45185-70
'45185P·70
'45165-80
'45185P4O
'45165-10
'45185P·10
MIN
MIN
MIN
MAX
MAX
teAH
tOHR
Hold time, column address after CAS low (see Note 12)
15
15
20
Hold time, date after RAS low (see Note 13)
35
35
45
n.
tDH
Hold time, date after CAS low (see Note 12)
15
15
ns
tAR
Hold time, column address after RAS low (see Note 13)
35
35
20
45
n.
tRAH
Hold lime, row address after RAS low
10
10
15
n.
tRCH
Hold lime, read after CAS high (see Note 14)
0
0
0
ns
tRRH
Hold time, read after RAS high (see Note 14)
0
0
0
n.
n.
twCH
Hold time, write after eAS low (early-write operation only)
15
15
20
Hold time, write after RAS low (see Note 13)
35
35
45
ns
toEH
tAWD
Hold time, ~ command
20
20
25
n.
Delay time, column address to xW low (see Note 15)
85
70
80
ns
teHR
Delay time, RAS low to CAS high (CBR refresh. only)
15
20
0
100
n.
0
70
20
0
80
n.
leRP
Delay time, CAS high to RAS low
tcsH
Delay time, RAS low to eAS high
teSR
Delay time, CAS low to RAS low (CBR refresh only)
10
10
10
tcwo
Delay time, CAS low to xW low (see Note 16)
ns
Delay lime, CSE high before date at DQ
50
20
80
toED
50
20
25
ns
tROH
Delay lime, CSE low to RAS high
10
tRAD
tRAl
Delay time, RAS low to column address (see Note 16)
Delay time, column address to RAS high
15
35
40
45
:rJ
teAL
tRCO
Delay time, column address to eAS high
35
40
45
Delay time; RAS low to eAS low (see Note 16)
~
6
z
tRPC
Delay time, RAS high to CAS low (CBR refresh only)
tRSH
tRWO
Delay time, CAS low toRAS high
20
0
20
tePR
eAS precharge before self refresh
i:
n.
twCR
z-n
-0
UNIT
MAX
lAps
tRASS
tREF
20
10
40
80
20
25
65
ns
n.
ns
ns
75
ns
0
ns
20
25
ns
100
110
135
ns
m precharge after self refresh
0
0
0
ns
130
150
180
n8
Self-refresh entry from RAS low
100
100
100
Delay time, RAS low to xW low (see Note 15)
Refresh time Interval (TMS45185 only)
8
8
Refresh time Interval,low power (TMS45165P only)
teHS
CAS low hold time after RAS high
IT
Transition time
4-122
50
15
0
tREF
NOTES: 7.
12.
13.
14.
15.
16.
10
35
ns
ns
64
64
-50
2
·Tlming measurements are referenced to Vil max and VIH min.
Later of CAS or xW in write operations
The minimum value Is measured when IRCD Is set to IRco min as a reference.
Either lARH or tRCH must be satisfied for a read cycle.
Read-modlfy-wrlte operation only
MaxImum value specified only to assure access time.
:lllExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
50
-50
2
50
-50
2
8
!IS
ms
64
ma
n8
50
na
TMS45165, TMS45165P
262144-WORD BY 16-81T HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS185C - OCTOBER 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
1.31 V
VCC-SV
Output Under Tnt -
Output Under Tnt
CL-100pF
(_NoteA)
I
......---1
CL-100pF
(.nNoaA)
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL Includes probe and fixture capacitance.
Figure 1. Load Circuits for Timing Parameters
z
o
-ti
:&
a:
~
z
w
o
z
c~
<
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAIi 77251-1443
4-123
TMS45165, TMS45165P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS1860- OClOBER 1992- REVISED Jl)NE 1995
PARAMETER MEASUREMENT INFORMATION
~
~
~
I~
_ _..,.11
~
~1
IfIAS
N
11
0
~
I I
I
I '-----I
14
tRSH
~ 14-- tAp ~
I I..
tRCD ---.I
14
I
tcRP
~
1'4
tcsH
~I
I
!.tcAS ---.II 11r-+-+1_ _ _ _ _ _ __
----;-..
~
_ _ _ _ _ 14-I
tr....,
I
!.'RAD-ti
'RAH'-.l- ~
I,
~
~
0
N
I
~I
I
I I
I
1 14 I I
ASC
I
tcAL---ti
1 i i r... I
~-
I
1\1
~
tcp
I I
\-.- -
I ~~
~ ..- ~ ~ ~ -7 ~~~============
=:s
,
Zn
m
I
I·
ow, tw
~
I
l:J
14
i:
9.....
Z
j4- tRC,H
I
I+-- tcAC --tI
.
j
tAA
tcLZ~
~
~
I
-------~
SMNmeA
\l
tAOH
NOTE A: Output can go from the high-impedance state to
--tI
I
I
I
II
141
~'ldData.
I
I
~
toFF
~
Out
}>----1
~ toEZ
I
Ir----~-
an Inva/Id-data state prior to the epeelfled access time.
Figure 2: Read-Cycle TIming
~1ExAs
4-124
tARH
~---~i------~l
'RAc
~
14--- toEA ~
III
OE
14- tcAH
I
DQO-DQ15 _ _ _;-1
()
()
+-I
I
_
~
I
14'-tAcs-tI
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 772&1-1443
TMS45165, TMS45165P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS165C-OCTOBER 1992-REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
z
o
-ti
:E
~
LL
Z
W
o
Z
c~
·~~~~~r~;~ and holding it low after RAS
falls (see parameter tCHR>. For successive CSR refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored, and the refresh address is generated internally•
.battery-backup refresh
TMS4x6400P
A low-power battery-backup refresh mode that requires less than 500 ,..A (5 V) or 350 ,..A (3.3 V) refresh current
is available on the TMS4x6400P. Data integrity is maintained using CSR refresh with a period of 31.25 !-IS while
holding RAS low for less than 1 JA.S. To minimize current consumption, all input levels must be at CMOS levels
(Vll < 0.2 V, VIH > VCC - 0.2 V).
TMS4x7400P
A low':power battery-backup refresh mode that requires less than 500 ,..A (5 V) or 350 ,..A (3.3 V) refresh current
is available on the TMS4x7400P. Data integrity is maintained using CSR refresh with a period of 62.5 J.LS while
holding RAS low for less than 1 J.LS. To minimize current consumption, all input levels must be at CMOS levels
(Vll < 0.2 V, VIH > Vcc - 0.2 V).
self refresh (TMS4xx400P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100 J.LS. The chip is then refreshed internally by an on-board oscillator. No external
address is required because the CSR counter is used to keep track of the address. To exit the self-refresh mode,
both RAS and CAS are brought high to satisfy tCHS. Upon exiting self-refresh mode, a burst refresh (refresh a
full set of row addresses) must be executed before continuing with normal operation. The burst refresh ensures
the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 J.LS followed by a minimum of eight initialization cycles
is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh
(RAS-only or CSR) cycle.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1~ • HOUSTON. TEXAS 77251-1443
4-137
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400p·
4194304-WORDBY 4-BIT HIGH·SPEED DRAMS
SMKS881A- MAY 1995 - REVISEOJUNE1995
test mode
The test mode is initiated with a CBR-refresh cycle while simultaneously holding the W input low. The entry cycle
performs an internal refresh cycle while internally setting the device to perform parallel read or write on
subsequent cycles. While in the test mode, any data sequence can be performed. The device exits test mode
if a CBR refresh cycle with W held high or a RAS-only refresh cycle is performed.
In the test mode, the device is configured as 1024K bits x 4 bits for each DO. Each DO pin has a separate 4-bit
parallel read and write data bus that ignores column addresses AO and A1. During a read cycle, the four internal
bits are compared for each DO pin separately. If the four bits agree, DO goes high; Hnot, DO goes low. During
a write cycle, the data states of all four DOs must be the same to ensure proper function of the test mode. Test
time Is reduced by a factor of four for this series.
Exit Cycle -+II14f-----+l.1
1
...
..-----Te.tModeCycle _ _ _ _ _.~I
~ Normal
I
I
I
Mode
~--""~of- Entry Cycle
I
I
7:\________
iN~! I
NOTE A: The states of W, data In, and address are defined by the type of cycle used during lest mode.
Figure 1. Test-Mode Cycle
~TEXAS
4-138
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. ~ 77251-1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH·SPEED DRAMS
SMKS881A- MAY 1995 - REVISEDJUNEl995
logic symbol t
AO
Al
A2
A3
A4
AS
A8
A7
A8
AS
Al0
All*
RAS
RAM4096K,,4
9
2001012100
10
11
12
15
18
0
;> A 4194303
17
18
19
21
8
8
20019/2109
20020
"-
5
~
"-
CAS
Vi
OE
OQl
0Q2
OQ3
0Q4
25
!---;:
20021
C20[ROW]
G23/[REFRESH ROW)
24 [PWR OWN]
C21 [COLUMN]
G24
•
4
22
~ 23210
...,
24,26 EN
"- G25
2
3
24
25
> 23022
4-
A,220
'i726
r
A,Z28 -
~~
t This symbol Ie In accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
All Ie NC for TMS4x7400 and TMS4x7400P.
*
~1ExAs
INSTRUMENTS
POSTOFFICE8OXl443· HOUSlON, TEXAS 77251-1443
4-139
TMS41.6400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
41943~WORD BY4-BIT HIGH-SPEED DRAMS
SMKSB81A- MAY 111116- REVISEDJUNE1995
functional block diagram
TMS4x8400/P
AO
Al
Column Decode
Sen.e Amplifiers
• Column• Add::t
Buffers
All
256KArrsy
•
R
256KArray
0
•
••
w
•
D
e
•
0
Row• Addraee
Buffers
c
d
e
256KArray
DQ1-DQ4
t Column addresses Al0 and All are not used.
TMS4x7400/P
~==i=~r-~--~IIIIII~r===c~o~lu~m~n~D~~~o~d~.===t__
• Column• Addrna
• Buffers
Sen" Amplifiers
256K Arrsy
256K Arrsy
256K Array :
A10-+-~
•
••
•
256K Array
w
•••
Row• Addraea • • •
• Buffers Jill
DQ1-DQ4
~1ExAs
4-140
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881A- MAY 1995 - REVISEDJUNE1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee:
TMS41x400. TMS41x400P .................. -1 Vt07V
TMS42x400, TMS42x400P ........•...... - 0.5 V to 4.6 V
Voltage range on any pin (see Note 1):
TMS41x400, TMS41x400P .................. -1 V to 7 V
TMS42x400, TMS42x400P ............... - 0.5 V to 4.6 V
Short-circuit output current ................................................................. 50 rnA
Power dissipation ...................•. ;..................................................... 1 W
Operating free-air temperature range, TA ............................................... O°C to 70°C
Storage temperature range, Tstg .................................................. -55°C to 125°C
t Streesee beyorid those listed under "absolute maximum ratings" may causa permanent damage to the device. These are stress ratings only, and
functional operation of the device at thasa or any other conditions beyond those Indicated under "recommended operating conditions" 18 not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
TMS41x400
VOO
VSS
VIH
VIL
MIN
4.5
Supply voltage
Supply voltage
High-level input voltage
NOM
5
TMS42x400
MAX
5.5
MIN
3
0
2.4
-1
1.ow-laValinput voltage (sae Note 2)
NOM
3.3
MAX
3.6
0
6.5
0.8
2
-0.3
Voo + 0.3
0.8
UNIT
V
V
V
V
70
Operating fra&.alr temperature
0
0
70
·0
TA
NOTE 2: The algebraic convention, where the more negative (leas positive) limit 18 designated 88 minimum, 18 used for logic-voltage lavals only.
~1ExAs
INSTRUMENTS
POST OFFICE lOX 1443 • HOUSTON, TEXAS 77261-1443
4-141
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881A- MAY 1885- REVlSEDJUNEl885
electrical characteristics over recommended ranges of supply voltage and operating free..lr
temperature (unle.. otherwise noted)
TMS416400/P
PARAMETER
'416400-60
'4164OOP-60
TEST CONDITIONSt
MIN
High-level output
MAX
2.4
IOH--5mA
VOH
voltage
VOL
.Low-level output
voltage
IoL-4.2mA
II
Input current
Qeakage)
VI" 0 V to 8.5 V,
VCC- 5•5V,
All others - 0 V to Vcc
10
Output current
(leekage)
~.5.5V,
Read- or wrlte-cycle
ICC1*§ current
Vo .0VtoVCC,
high
Standby current
Average refresh
1CC3*§ current (RA§-only
refresh or CBR)
ICC4*" Average page current
Ices'
Self-refresh current
~ .. 5.5V,
~
2.4
V
V
.. 10
.. 10
.. 10
j.iA
.. 10
.. 10
.. 10
j.iA
60
70
80
mA
2
2
2
mA
1
1
1
mA
500
500
500
j.iA
60
70
80
mA
70
80
50
mA
500
500
500
j.iA
500
500
j.iA
"
Minimum cycle,
cycling,
~ high (RA§ only),
RAS low after CAS low (CBR)
~ .. 5.5V.
low.
!fQ.... MIN.
CAS cycling
~<0.2V.
RAS<0.2V.
Measured after tRASS min
Battery back-up
IRC" 31.251'8.
tRAS" 11'8.
operaUng current
Vcc -0.2 V" VIH" 8.5 V.
(equivalent
refresh
500
ICC10'
o V" VIL" 0.2 V. iN and OE = VIH.
time Is 128 ms): CBR
Address and data stable
only
t For conditions shown as MINIMAX. use the appropriate value specified In the Umlng requirements.
* Measured with outputs open
,
§ Measured with a maximum of one address change while AAS .. VIL
, Measured with a maximum of ona address change while CAS - VIH
'For TMS416400P only
~1ExAs
4-142
UNIT
MAX
0.4
'416400
'418400P
MIN
0.4
mand~hlgh
VIH .. VCC - 0.2 V (CMOS),
After 1 memory cycle,
AAS and CAS high
MAX
'416400-60
'416400P-80
0.4
Minimum cycle
Vcc = 5.5 V,
MIN
2.4
VIH .. 2.4 V (TTL),
After 1 memory cycle,
ICC2
'416400-70
'416400P-70
INSTRUMENTS
POST 0FF1CE sox 14013 • HOUSTON. lEXA8 77261-14013
,.
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4.;BIT HIGH-SPEED DRAMS
SMKS881A- MAY 188S-REVISEDJUNE1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS417400/P
PARAMETER
'417400-80
'4174OOP-80
TEST CONDmoNst
MIN
VOH
High-level output
voltage
VOL
L.ow-Ievel output
voltage
IOL=4.2mA
II
Input currant
Oeakage)
VCC .. S.SV,
VI =OVtoS.SV,
All others .. 0 V to VCC
10
Output currant
Oeakage)
~ .. s.SV,
Reed-or
ICC1*' write-cycle current
2.4
IOH=-SmA
VO·OVtoVcc,
S high
=S.Sv,
VIH =2.4 V (TTL),
VCC
MAX
Minimum cycle
Standby current
1CC4*'
Average refresh
current (FiAS-only
refresh or CBR)
Average page
current
Icee'
Self-refresh currant
1CC3*'
Minimum cycle,
Y.QQ-S.SV,
RAS cycling,
~ high (RAS only).
RAS low after CAS low (CBR)
~-S.5V.
low,
UNIT
MAX
2.4
V
0.4
V
:0:10
:0:10
:0:10
!IA
:0:10
:1:10
:1:10
!IA
110
100
90
mA
2
2
2
mA
1
1
1
mA
500
500
500
!IA
110
100
90
mA
70
60
SO
mA
500
500
500
!IA
500
500
!IA
~.MIN,
cycling
CASeO.2V,
RASe 0.2 V;
Measured after tRASS min
MIN
0.4
'417400
'417400P
MAX
'417400-80
'4174OOP-80
0.4
RAS and ~ high
VIH .. Vcc - 0.2 V (CMOS),
After 1 memory cycle,
RAS and ~ high
MIN
2.4
After 1 memory cycle,
ICC2
'417400-70
'4174OOP-70
Battery back-up
tRC-S2.Sj.I8.
tRAS .. 1 j.I8.
operating current
VCC-0.2 V .. VIH .. S.Sv,
(equivalent refresh
500
oV .. VIL." 0.2 V, Vii and OE .. VIH!
time Is 128 ms);
Address end data stable
CBRonly
For condltiona shown as MINIMAX, use the appropriate velue specified In the liming requirements.
Measured with outputs open
Measured with a maximum of one address change while RAS .. VIL.
Measured with e maximum of one address change while ~ - VIH
For TMS417400P only
ICC10'
t
*
,
,
,
~1EXAS
INSTRUMENTS
POST OFFICE BOX 14013 • HOUSTON, 1E
25
AS
28
A7
27
AS
28
AS
18
A10*
15
A11*
A 1 CW:S7S
2OD15/21D7
2OD18
20017
20018
.2OD18
~
po
~
~C20[ROW)
RAS
"'D
LCAS
::0
0231[REFRESH ROW)
14
24[pWRDWNI
C21
024
31
&
31
0
C
c:
~
UCAS 30
0
-I
>C21
034
&
31
"'D
23C22
23C32
r +
Z31
~
m
<
m
VI 13
-
OE 28
23,21D
....
DQO 2
~
D01
DQ2
D03
DQ4
DOS
Doe
D07
DQ8
3
4
.,25
r
4-
A,22D
V28,27
A,Z28
L....
A,32D
V36,37
A,Z38
5
7
8
8
10
33
DQ8 34
0010
D011
D012
D013
0014
D01S
,
24,2SEN27
34,25EN37
36
36
36
38
40
41
...,
t This symbol is In accordance with ANSI/IEEE Std 91-1984 and lEe Publlcetion 617~12.
*The pin numbers shown oorrespond to the DZ package.
A10 and A11 are NC for TMS4x8160 and TMS4x8160P.
~1ExAs
4-164
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lEXAS 77251-1443
~~~~m~~~m~~~m~~~
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS18OA- MAY 1995 - REVISED JUNE 1996
functional block diagrams (TMS4x6160/P)
RAS UCAS LCAS
AD
Al
OE
Column~.
•
•
•
A7
•
•
•
AB-
W
Sen.. AmpIHl...
ColumnAdd....
Butfera
256KArray
,.•
•
Row-
Add....
Butte..
R
0
w
D
256KArray
•
••
•e
0
d
•
4
256KArray
~
~
a:
All
(a) TMS4x8l60, TMS4x8l6OP
a.
functional block diagram (TMS4x8160/P)
liAS UCAi LCD
Vi
DE
b
:::l
C
o
a:
~::i=t=~~~)lIIIIIIII~::~co~lu~m~n~D~R~~~.~::~_
•
Column-
•
Add....
Butte..
•
•
•
•
a.
Sen.. Ampllfle..
256K Array
256K Array :
•••
RowAdd....
Butte. . . . .
1
256K Array
w
•
••
D
•c
o
d
•
DQO-DQ1S
266KArray
(b) TMS4x8l60, TMS4x&l6OP
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
4-165
m~~~mw~~mw~~mw~~
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH·SPEED DRAMS '
SMKS18OA- MAY 1995 - REVISED JUNE 1995
operation
dual CAS
Two CAS pins ([CAS and tmAS) are provided to give independent control of the 16 data-I/O pins
(OQO-OQ15), with LCAS corresponding to OQO-OQ7 and UCAS corresponding to OQ8-0Q15. For read or
write cycles, the column address is latched on the first xCAS falling edge. Each xCAS going low enables its
corresponding OQx pin with data associated with the column address latched on the first falling ~ edge,
All address setup and hold parameters are referenced to the first falling XCA~ edge. The delay time from xCAS
low to valid data out (see parametertCAC) is measured from each individuallt AS to its corresponding OQx pin.
In order to latch In a new column address, both xCAS pins must be brought high. The column-precharge time
(see parameter tep) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle.
Keeping a column address valid while toggling xCAS rereuir; aminimum setup time, tClCH' During telCH, at
least one xCAS must be brought low before the other x:A. is taken high.
For early-write ~s, the data is latched on the first XCAS falling edge. Only the OQs that have the
corresponding XCAS low are written into. Each xCAS must meet...!QAs minimum in order to ensure writing
into the storage cell. To latch a new address and new data, all ,xCAS pins must be high and meet tcp.
enhanced page mode
"0
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum
number of columns that can be accessed is determined by the maximum RAS low time and the XCAS'
page-mode ~e time used. With minimum xCAS page-cycle time, all columns can be accessed without
intervening RAS cycles.
"
:D
o
C
c:
£l
Uniike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while ~ is high. The falling edge of the
first xCAS latches the column addresses. This feature allows the devices to operate at a higher data bandwidth
than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather
than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address may be presented immediately after tRAH (row-address hold time) has been satisfied, usually
well in advance of the falling edge of xCAS. In this case, data is obtained after tcAC maximum (access time from
~ low) if tAA maximum (access time from column address) has been satisfied. In the event that column
addresses for the next page cycle are valid at the time XCAS goes,£i9h, minimum access time for the next cycle
is determined by tePA (access time from rising edge of the last AS).
"0
:D
-~~
address: AO-A11 (TMS4x6160, TMS4x6160P) and AO-A9 (TMS4x8160, TMS4x8160P)
Twenty address bits are required to decode 1 of 1048576 storage cell locations. For the TMS4x6160 and
TMS4lt6160P, 12 row-address bits are set up on AO through A11 and latched onto the chip by RAS. Eight
column-address bits are set up on AO through A7 and latched onto the chip by the first xCAS. For the
TMS4x8160 and TMS4x8160P, 10 row-address bits are set up on AO-AS and latched onto the chip by RAS.
Ten column-address bits are set up on AO-:-AS and latched onto the chip by the first xCAS. All addresses must
be stable on or before the falling edge of RAS and xCAS. RAS is similar to a chip enable in that it activates the
sense amplifiers as well as the row decoder. XCAS' is used as a chip Select, activating its corresponding output
buffer and latching the address bits into the column-address buffers.
write enable (W)
The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects
, the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to xCAS
~rly write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded.
~1ExAs
4·166
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
mw~~mw~~m~~~m~~~
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS1BOA- MAY 1985 - REVISED JUNE 1995
data In (000-0015)
Data Is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of ~ or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data is strobed In by the first occurring XCAS with setup and hold times referenced to this signal. In a
delayed-write or read-modify-write cycle, XCAS is already low and the data is strobed In by iN with setup and
hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must. be high to bring the
output buffers to the high-impedance state prior to impressing data on the I/O lines.
data out (000-0015)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until iCAS and OE
are brought low. In a read cycle, the output becomes valid after the access time Interval tcAC (which begins with
the negative transition of XCAS) as long as tRAC and tM are satisfied.
output enable (OE)
C5E controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing C5E low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into the
low-impedance state, and they remain in the low-impedance state until either OE or xCAS is brought high.
RAS-only refresh
TAfS4x6160, TAfS4x6160P
A refresh operation must be performed at least once every 64 ms (256 ms for TMS4x61 6OP) to retain data. This
can be achieved by strobing each of the 4096 rows (AO-A11). A normal read or write cycle refreshes all bits
In each row that is selected. A RAS-only operation can be used by holding both xCAS at the high Onactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
.
TMS4xB160, TMS4xB160P
A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x81 6OP) to retain data. This
can be achieved by strobing each of the 1024 rows (AO-A9). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS-only operation can be used by holding both XCAS at the high (Inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding
xCAS at Vil after a read operation and cycling RAS after a specified precharge period, similar to a RAS-oniy
refresh cycle. The external address is ignored and the refresh address is generated internally.
XCAS-before-RAS (xCBR) refresh
xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter tcsR> and holding
it low after RAS falls (see parameter tcHR>. For successive xCBR refresh cycles, iCAS' can remain low while
cycling RAS'. The external address is ignored and the refresh address is generated internally.
battery-backup refresh
TAfS4x6160P
A low-power battery-backup refresh mode that requires less than 600 !AA (5 V) or 350 !AA (3.3 V) refresh current
is available on the TMS4x6160P. Data integrity is maintained using xCBR refresh with a period of 62.5 !.IS while
holding RAS low for less than 300 ns. To minimize current consumption, all input levels must be at CMOS levels
(Vll < 0.2 V, VIH > Vee - 0.2 V).
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 7721i1-1443
4-167
3:
!:!:!
iiia:
t:ia.
::::»
C
0
a:
a.
TMS416160,.TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 1&-BIT HIGH-SPEED DRAMS
SMKS16OA-MAY 1995-REVISED JUNE 1995
TMS4xB160P
A low-power battery-backup refresh mode that requires less than 600 !AA (5 V) or 350 !AA (3.3 V) refresh current
is available on the TMS4x8160P. Data integrity Is maintained using xCBR refresh with a period of 125 lAS while
holding ~ low for less than 300 ns. To minimize current consumption, all input levels must be at CMOS levels
(Vll < 0.2 V, VIH > Vee - 0.2 V).
self refresh (TMS4xx160P)
The self-refresh mode Is entered by dropping xCAS low prior to RAS going low. Then XCAS and RAS are both
held low for a minimum of 100 lAS. The chip is then refreshed internally by an on-board oscillator. No external
address is required because the CBR counter is used to keep track of the address. To exit the self-refresh mode,
both RAS and xCAS are brought high to satisfy tcHS' Upon exiting self-refresh mode, a burst refresh (refresh
a full set of row addresses) must be executed before continuing with normal operation. The burst refresh
ensures the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 lAS followed by a minimum of eight initialization cycles
is required after power up to the full Vee level. These eight initialization cycles must include at least one refresh
(RAS-only or xCBR) cycle.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee:
TMS41x160, TMS41x160P .•.•..•..•.•.•.•..•.••• - 1 V to 7 V
TMS42x160, TMS42x160P .................... - 0.5 V to 4.6 V
Voltage range lln any pin (see Note 1): TMS41x160, TMS41x160P ....................... -1 Vto 7V
TMS42x160, TMS42x160P .................... - 0.5 V to 4.6 V
Short-circuit output current ..••..•.•••••...•..•..•..•.........•......•...•.....••.•••.••.••• 50 mA
Power dissipation ........•.••..•..•..•..••.•...•.....•.....•..••.....••.........••..••.••.. 1·W
Operating free-air temperature range, TA .............................................. O·C to 70·C
Storage temperature range, Tstg .................................................. - 55·C to 1.25·C
t stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These ara strass ratings only, and
functional operallon of the device at these or any other conditions· beyond those indicated under "recommended operating conditions" Is not
implied. Exposure to absolute-maxlmum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values ara with respect to VSS.
recommended operating conditions
TMS41x160
TMS42x160
MIN
NOM
MAX
MIN
NOM
4.5
5
0
5.5
3
3.3
0
Vee
Supply voltage
VSS
Supply voltage
VIH
High-level Input voltage
2.4
VIL
Low-level Input voltage (see Note 2)
-1
8.5
0.8
2
-0.3
MAX
3.8
UNIT
V
V
VCC+ 0.3
0.8
V
V
Operating free-air temperature
70
0
70
0
·C
TA
..
NOTE 2: The algebraic convention, where the more negative (less positive) limit IS designated as minimUm, IS used for logic-voltage levels only.
~TEXAS'
4-188
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON. leXA8 77251-1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS18OA- MA.Y 1995 - REVISED JUNE 1995
TMS416160/P
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
'416160·60
'416160P·60
TEST CONDITIONSt
MIN
VOH
Hlgh·level output
voltage
10H =-5mA
VOL
Low-level output
voltage
IOL=4.2mA
II
Input current
Oeakage)
VI = OVto 6.5 V,
VCC = 5.5 V,
All others = 0 V to Vcc
10
Output current
Oeekage)
VCC 5.5 V,
xCAS high
Vo .. OVtoVcc,
ICC1*§
Read-orwrite-cycle
current
VCC = 5.5 V,
Minimum cycle
1CC2
ICC3§
Standby current
Average refresh
current (RAS-only
refresh or CBR)
1CC4*'1 Average page current
Icca'
Self-refresh current
MAX
2.4
'416160·70
'41616OP·70
MIN
MAX
2.4
'416160·60
'41616OP·60
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
:t10
:010
:t10
iAA
:010
:010
:t10
iAA
go
60
70
rnA
2
2
2
rnA
1
1
1
rnA
500
500
500
iAA
Minimum cycle,
VCC=5.5V,
RAS cycling,
XCAS high (RAS only),
RAS low after xCAS low (CBR)
:>
w
90
60
70
rnA
a.
VCC = 5.5 V,
RASlow,
!PC" MIN,
xCAScycling
go
60
70
rnA
xCAS < 0.2 V,
RAS < 0.2 V,
Measured after tRASS min
500
500
500
iAA
600
600
iAA
=
VIH = 2.4 V (TTL),
After 1 memory cycle,
RAS and xCAS high
VIH = VCC - 0.2 V (CMOS),
After 1 memory cycle,
RAS and xCAS high
'416160
'416160P
Battery back-Up
tRC=62.5j.U1,
tRAS " 300 ns,
operating current
VCC - 0.2 V "VIH "J!.5 V,_
600
ICC10' (equivalent refresh
OV"VIL,,0.2V, Wand OE VIH,
lime Is 256 ms); CBR
Address and dB18 8leble
only
t For conditions shown as MIN/MAX, use the appropnate value specified In the liming requirements.
* Measured with outputs open
§ Measured with a maximum of one address change while RAS .. VIL
'I Measured with a maximum of one address change while xCAS VIH
'For TMS416160P only
=
=
~TEXAS
INSTRUMENTS
POST OFFICE BOX 14013 • HOUSlON. TEXAS 77251-14013
4-169
~
w
a:
lJ
::)
c
oa:
a.
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH·SPEED .DRAMS
SMKS18OA-: MAY 1895 - REVISED JUNE 1996
TMS418160/P
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unle.. otherwise noted) (continued)
PARAMETER
'418180-80
'41818OP-80
TEST CONDlTlONst
MIN
VOH
High-level output
voltage
VOL
voltage
lOLa 4.2 rnA
II
Input current
(leakage)
10
Output current
(leakage)
ICC1*1
wrIte-cyc1e current
ICC2
Low-level output
Read-or
Standby current
Average refreeh
1CC3§
current~ly
refresh or CBR)
Average page
1CC4*' current
Ieee'
Self-refresh current
Battery back-up
operating current
ICC10' (equivalent refresh
time Is 128 ms);
CBRonly
MAx
MAX
'418180-80
'41818OP-80
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
VCC .. S.Sv,
VI" 0 Vto 8.S V.
All othere .. 0 V to VCC
:1:10
:1:10
:1:10
(IA
VCC=S.SV.
iCAShlgh
Vo =OVtoVCC.
:1:10
:1:10
:1:10
(IA
Vcc= S.SV.
Minimum cycle
190
180
170
rnA
2
2
2
rnA
1
1
1
rnA
VIH" 2.4 V (TILl.
After 1 mX'Cll cycle.
~and
high
VIH = Vcc - 0.2 V (CMOS).
After 1 memory cycle.
~ and iCAS high
'418180
'418180P
500
500
500
(IA
Minimum cycle.
VCC= S.SV.
~ high (AA'S' only).
m-cycling.
~ low after iCAS low (CBR)
190
180
170
rnA
VCC- 5•5V•
~Iow.
100
90
80
rnA
XCAS<0.2V.
~<0.2V.
Measured aftertRASS min
500
500
500
(IA
lRAs • 300 nsf
Vcc - 0.2 V • VIH " 8.5 V.
OV"VIL,,0.2V, Wand OE = VIH.
Addreee and data stable
800
800
800
(IA
tpC-MIN.
~cycllng
.
lAc " 125 J4!1.
t For conditions shown as MIN/MAX. use the appropriate value specified In the timing requirements.
* Measured with outputs open
§ Measured with a maximum of one address change while ~ - VIL
, Measured with a maximum of one address change while XCAS .. VIH
'For TMS418180P only
~1ExAs
4-170
MIN
2.4
2.4
10Hz-SmA
'418180-70
'418180P-70
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 1£XAS 772&1-1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS18OA-MAY 1996- REVISED JUNE 1995
TMS426160/P
electrical characteristics over recommended ranges of supply voltage and operating free-air
condition. (unle•• otherwise noted) (continued)
PARAMETER
TEST CONDITIONst
'426160-60
'426160P-60
MIN
VOH
High-level
output
voltage
IOH =-2mA
LVITL
10H=-lOOI1A
LVCMOS
2.4
",10
",10
",10
IIA
",10
",10
",10
IIA
90
80
70
mA
1
1
1
mA
'426160
500
500
500
IIA
'426160P
200
200
200
IIA
VCC=3.6V,
xc;AShlgh
Vo =OVtoVcc,
ICC1*'
Read- or writecycle current
Vee = 3.6 V,
Minimum cycle
VIH = 2 V (LV1TL),
After 1 memory cycle,
RAS and xCAS high
VIH =VCC-0.2V
(LVCMOS),
After 1 memory cycle,
RAS and xc;AS high
Minimum cycle,
VCC-3.6V,
RAScycling,
XCAS high (RAS-only refresh)
~ low after xc;AS low (CBR)
VCC=3.6V,
~Iow,
VCC-0.2
VCC-0.2
0.2
Output current
(leakage)
Average page
ICC4*' current
Vee-0•2
0.4
10
(~-only
UNIT
MAX
0.2
Input current
(leakage)
refresh
orCBR)
2.4
MIN
0.4
II
1CC3§
2.4
MAX
0.2
LV1TL
IoL=2mA
LVCMOS
10L -100 IIA
VI =OVto3.9V,
VCC = 3.6 V,
All others = 0 V to VCC
Average
refresh current
MIN
0.4
Low-level
output voltage
Standby
current
MAX
'426160-60
'426160P-80
V
VOL
1CC2
'426160-70
'426160P-70
tpC = MIN,
xc;AS cycling
V
90
80
70
mA
90
80
70
mA
250
250
IIA
350
350
IIA
Self-refresh
xCAS<0.2V,
RAS<0.2V,
250
current
Measured after tRASS min
Battery ,
back-up
tRC = 62.5118,
operating
lRAS '" 300 ns,
current
Vee - 0.2 V '" VIH '" 3.9 V,
350
leel0' (equivalent
OVo:VILo:O.2V, Wand OE =VIH,
refresh time Is
Address and data stable
256ms),
CBRonly
t For conditions shown as MINIMAX, use the appropriate value specified In the timing requirements.
Measured with outputs open
.
§ Measured with a maximum of one address change while RAS = VIL
• Measured with a maximum of one address change while XCAS = VIH
'For TMS426160P only
Ieee'
*
~TEXAS
INSTRUMENTS
POST OFFICE SOX 14043 • HOUSTON, TEXAS 77261-14043
4-171
3=
w
~
a:
0.
l3::l
C
oa:
0.
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS4261GQ, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS18OA- MAY 1886- REVISED JUNE 1886
TMS428160JP
.Iectrlcal charact.rlstlcs ov.r r.comm.nd.d ranges of supply voltag. and operating fr....lr
conditions (unl.ss oth.rwls. not.d) (continued)
PARAMETER
TEST CONDITIONst
MIN
High-lavel
VOH
IOH--2mA
LVTTL
voltage
10H" -100 JAA
LVCMOS
output
'428160·70
'428160P·70
'428160·60
'42816OP·60
MAX
MIN
'428160·80
'42816OP·80
MAX
2.4
11.4
VCC-O.2
MIN
UNIT
MAX
2.4
VCC-0•2
v
VCC-0•2
Low·1eveI
IOL-2mA
LVTTL
0.4
0.4
0.4
VOL
output voltage
10L .. 100 JAA
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
VI-OVto3.9V,
VCC-3.6V,
All others .. 0 V to Vcc
:1:10
:1:10
:1:10
JAA
10
Output current
(leakage)
VCC. 3.6 V,
XCAShlgh
VO= OVtoVCC,
:1:10
:1:10
:1:10
JAA
Read· or writeICC1*' cycle current
VCC =3.6 V,
Minimum cyc:1e
190
180
170
mA
1
1
1
mA
'428160
500
500
500
j&A
'428160P
200
200
200
JAA
190
160
170
mA
100
90
80
mA
250
250
250
JAA
350
350
JAA
Icc2
Standby
current
VIH .. 2 V (LVTTl),
After 1 m~ cycle,
RMand
high
VIH =VCC- 0.2V
(LVCMOS),
After 1 memory cycle,
RAS and XCAS high
Average
refresh current
(RAS-only
refresh
orCBR)
JiM low after ~ low (CBR)
1CC4*'
Average page
current
VCC- 3•6V,
RASIow,
Icca'
SeIf·refreeh
current
XCAS<0.2V,
RAS<0.2V,
Measured after tRASS min
Ices'
VCC-3.6V,
Minimum cycle,
~cycllng,
XCAS high (RAS·only refresh)
tpC·MIN,
~cycling
Battery
back·up
tRAS 0; 300 ns,
operating
lAc =125 lIS,
current
Vee - 0.2 V 0; VIH 0; 3.9 V,
350
ICC10' (equivalent
oV 0; VIL 0; 0.2 V, Wand OE .. VIH,
refresh time 18 Addrees and data stable
128ms),
CBRonly
For conditions shown as MIN/MAX, usa the appropriatavalue specified In the timing requirements.
Measured with outputs opan
• Measured with a maximum of one addrees change while RAS .. VIL
• Measured with a maximum of one addrees change while ~ =VIH
, For TMS428160P only
*
.~1ExAs
4-172
V
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, 'I1!XAB 772151-1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS18OA- MAY 11195 - REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-alr temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
CieA)
Input capacitance, AO-A11
5
pF
CI(OE)
Input capacitance, OE
7
pF
CURC}
Input capacitance, xCAS and RAS
7
pF
Input capacitance, W
7
pF
7
pF
Ci/Wl
Output capacitance
Co
NOTE 3: Vee '" 5 V % 0.5 V or 3.3 V + 0.3 V (see Table, 1), and the bias on pinl under teat Ie 0 V.
switching characteristics over recommended ranges ot supply voltage and operating tree-air
temperature
'4xx160·60
'4xx16OP·60
PARAMETER
MIN
MAX
'4xx160·70
'4xx16OP·70
MIN
MAX
'4xx160·80
'4xx16OP·80
MIN
UNIT
MAX
tAA
Access time from column address (see Note 4)
30
35
40
nl
teAC
Aocess time from xCAS low (see Note 4)
15
18
20
nl
tePA
tRAC
Access time from column precharge (see Note 4)
35
40
45
nl
Access time from RAS low (see Note 4)
60
70
80
ns
toEA
Accesl time from OE low (see Note 4)
15
18
20
ns
teLZ
Delay time, XCAS low to output In low.impedance state
0
0
0
ns
toH
Output data hold time (from xCAS)
3
3
3
ns
toHO
Output data hold time (from OE)
toFF
Output disable time after XCAS high (see Note 5)
3
0
15
3
0
0
15
0
toEZ Output disable time after OE high (see Note 5)
NOTES: 4. Access times for TMS42x160 are measured with output reference levels of VOH =2 V and VOl
5. toFF and toEZ are specified whan the output is no Ioilger driven.
ns
3
18
0
20
ns
18
0
20
ns
=0.8 V.
3:
w
~
a:
a.
b
::l
C
o
a:
a.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, 1aAS 77251-1443
4-173
m~~.m~~~m~~.m~~~
.TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS1BOA-MAY 1985-REVISED JUNE 1985
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
,
'4xx160·60
'4xx160·70
'4xx160·60
'4xx160P·60
'4xx18OP·70
'4XX18OP·60
MIN
110
110
MIN
130
130
150
ns
ns
155
40
181
205
ns
45
ns
Cycle time, page-mode read-write (see Note 6)
85
96
50
105
tRASP
Pulse duration, RAS low, page mode (see Note 8)
60. 100000
70 100000
60 100000
IMs
Pulse duration, RAS low, nonpage mode (see Note 8)
60
70
80
10000
ns
ns
teAS
Pulse duration, ~ low (see Note 9)
15
20
10000
ns
tRP
twp
Pulse duration, RAS high (prechsrge)
40
Pulse duration, W low
10
0
tRC
Cycle time, read (see Note 6)
twc
Cycle time, write (see Note 6)
tRWC
tpc
Cycle time, read-write (see Note 6)
tPRWC
Cycle time, page-mode read or write (see Notes 6 and 7)
10000
10000
18
50
10
tASC
Setup time, column address before XCAS low
tASR
Setup time, row address before RAS low
0
0
0
MAX
UNIT
MIN
150
MAX
10000
10000
MAX
ns
80
ns
10
0
ns
0
ns
ns
tos
Setup time, deta (see Note 9)
Setup time, W high before xCAS low
0
0
0
0
0
0
ns
tRCS
tcwL
Setup lime, W low before ~ high
15
20
ns
tRWL
Setup lime, Wlow before RAS high
15
18
18
20
twcs
Setup time, W low before ~ low (early-write operation only)
0
0
0
teAH
tOH
Hold time, column address after ~ low
10
10
15
15
tRAH
Hold time, row address after RAS low
15
15
10
ns
ns
ns
Hold lime, data (see Note 10)
tRCH
Hold time, Whigh after XCAS high (see Note 11)
10
0
tRRH
Hold lime, W high after RAS high (see Note 11)
0
ns
0
ns
15
5
ns
6
40
45
ns
18
20
ns
10
-50
ns
0
0
15
twCH
Hold time, W low after ~ low (early-write operation only)
Hold time, ~ low to XCAS high
teEH
Hold time, OE command
35
15
tROH
Hold time, RAS referenced to OE
10
10
-50
-50
Hold time, RAS high from ~ precharge
Hold time, XCAS low after RAS high (self refresh)
teHS
NOTES: 6. All cycle times assume IT 5 ns.
7. To assure tPC min, tASc should be It to tep.
8. In a read-write cycle, tRWO and tRWL must be observed.
9. In a read-write cycle, tcwo and tcWL must be observed.
10. Referenced to the later of xCAS or Win write operations
11. Either tRRH or tRCH must be satisfiad for a read cycle.
=
~1ExAs
4-174
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
ns
10
0
teLCH
tRHCP
10
5
ns
ns
ns
ns
m~~~m~~~m~~~m~~~
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS18OA- MAY 1118S - REVISED JUNE 1995
timing requirements oyer recommended ranges of supply Yoltage and operating free-air
temperature (continued)
'4xx160·60
'CXX18OP·80
MIN
'CXX160·70
'4xx18OP·70
MAX
MIN
'CXX180·80
'CXX180p·80
MAX
MIN
UNIT
MAX
tcp
Delay time, XCAS high (precharge)
10
10
10
ns
tAWD
Delay time, column address to W low (read-write operation only)
55
63
70
ns
tcHR
Delay time, RAS low to XCAS high (xCBR refresh only)
10
10
10
ns
tcRP
Delay time, xCAS high to RAS low
5
5
5
ns
tcsH
Delay time, RAS low to xCAS high
60
70
80
ns
tcSR
Delay time, xCAS low to RAS low (xCBR refresh only)
5
5
5
ns
ns
lewD
Delay time, xCAS low to W low (read-wrlte operation only)
40
46
50
toED
Delay time, OE to data
15
18
20
tRAO
Delay time, RAS low to column address (see Note 12)
15
tRAL.
teAL.
Delay time, column address to RAS high
30
35
40
ns
Delay time, column address to xCAS high
30
35
40
ns
tRCD
Delay time, RAS low to xCAS low (see Note 12)
20
tRPC
Delay time, RAS high to xCAS low
0
0
0
ns
tRSH
Delay time, XCAS low to RAS high
15
18
20
ns
tRWO
Delay time, RAS low to W low (resd-wrlte operation only)
85
98
110
ns
tcPW
Delay time, W low after XCAS precharge (read-write operation only)
60
68
75
ns
tRASS
Pulse duration, self-refresh entry from RAS low
100
100
100
i'S
tRPS
Pulse duration, RAS precharge after self refresh
110
130
150
ns
30
45
'4x6160
tREF
IT
20
35
15
52
20
ns
40
60
64
64
64
256
256
256
'4x8160 ,
16
16
16
'4x8160P
126
128
126
'4x6160P
Refresh time Interval
15
Transition time
3
30
3
30
3
30
ns
ns
ms
ms
ns
NOTE 12: The maximum value IS specified only to assure access time.
~
-Gi
W
a:
a.
t;
~
C
oa:
a.
PARAMETER MEASUREMENT INFORMATION
VTH
VCC
Rl
\
Output Under T. .t - - - . . . . - -..
Output Under Teet
CL,,100pF
(see Note A)
I
R2
CL"l00pF
(s•• Note A)
(b) ALTERNATE LOAD CIRCUIT
(8) LOAD CIRCUIT
NOTE A: CL Includes probe and fixture capecitance.
YCC (V)
Rl (g)
M(g)
VrH (V)
41xl60/P
5
828
295
1.31
218
42xl60/P
3.3
1178
868
1.4
500
DEVICE
RL(g)
Figura 1. Load Circuits for Timing Paramatars
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSlON, TEXAS 77261-1443
4-175
m~~~m~~~m~~~mw~~
TMS426160, TMS426160P, TMS428160,TMS4281~
1048576-WORD BY 16·BIT HIGH·SPEED'DRAMS
SMKS18OA- MAY 1995- REVISED JUNE 1896
.
PARAMETER MEASUREMENT INFORMATION
"tJ
:a
o
c
c
Q
":a~
-
m
I
I
I 14toFF -1
leAC ---'
1(- Note B)
Me
I
I
DQO-DQ1S
:e
leLZ
I
1 tAA ~
-l9I
14-- toH ---....I
- I _ _ _ _ _ _ _-----.,~
~,.-
I See Note D
---+t-----~
I
j4
$HNoteC
lRAc
~.~
~
I.
?
Valid Date Out
toHO
. ItAOH
§§§:¥o1*~:~toEA~
14
)-------
I
1141
~toEZ
~
~:~~~~~:a
NOTES: A. To hold the addl'888latched by the first iCAS going low, the parameter !cLCt-! muat be met.
B. !cAc js·meaaured from iCAS to its corresponding DQx.
C. Output can go from the high-Impedance stete to an Invalld-dat8 stete prior to the specified access time.
D. xCAS order Is arbitrary.
Figure 2. Read-Cycle TIming
~1ExAs
INSTRUMENTS
4-178
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
m~~~m~~~m~~~m~~~
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16·BIT HIGH·SPEED DRAMS
SMKSI8OA- MAY 11195 - REVISED JUNE 11195
PARAMETER MEASUREMENT INFORMATION
Add....
W
==
~
a:
a.
t3
w
::l
C
oa:
DQO-DQ15
"'-J'VVVV'VV'",V'
I
I
I4--toED~
I
Don't Care
a.
./V'IJV\JV\/V\.
!4--.r-"-, IDs (s.. Note B)
14
toEH--"~
NOTES: A. To hold the address latched by the first iCAS going low, the parameter tcLCH must be met.
B. Referenced to the first xCAS or Vii, whichever occurs last
,
C. iCAS order Is arbitrary.
Figure 3, Write-Cycle Timing
~ThxAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lECAS 77261-1443
4-177
m~~~m~~~mw~~m~~~
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH·SPEED DRAMS
SMKS1BOA- MAY 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
"o
:D
Add .....
C
c:
~
":D~
m
-
DQO-DQ1S
:e
NOTES: A. To hold the address latched by the flrst~ going low, the parameter tcLCH must be met.
B. iCAS order Is arbitrary.
Figure 4. Early-Write-Cycle Timing
~TEXAS
INSTRUMENTS
4-178
POST OFFICE BOX 1443 • HOUSTON, 'IEXAS 77251-1443
~~~~~~~~~~~~N~~~
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16·BIT HIGH·SPEED DRAMS
SMKS18OA-MAY 1895-REVlSEDJUNE 1895
PARAMETER MEASUREMENT INFORMATION
Add.....
w
DQ8-DQ15
000-007
NOTES: A.
B.
C.
O.
To hold the address latched by the first ~ going low, the parameter tcLCH must be met.
Output can go from a the high-impedance state to an invalid-data atete prior to the specified access time.
tcAC Is measured from ~ to Its corresponding OOX.
~ order Is arbitrary.
Figure 5. Read-Modlfy-Wrlte-Cycle TIming
~TEXAS
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON. TEXAS 7721i1-1443
4-179
TMS416160, TMS41616QP, TMS418160, TMS418160P
TMS426160, TMS42616()P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH·SPEED DRAMS
•
SMKS18OA- MAV1995- REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
IRP~
'RAsP ----------1~
N
"---
I~~~
_ _ _-+I....I~-_ I
UCAS
I
I
I I
II I
I ~
I 1I I
..jI II
N
14-- teRP
I.~
.
I
teLCH ~!..
(8H NOleA) I
I
i
jtcsH ~
I
"'D
o
C
c:
~
I IRAH ~
I I
I
~ t.l- tASC
I
I I I I ~teAH
jill
I
I
I
I
rL.
I
Vi
"'D
::D
~
~
tRCS
I
I
I
I
I~
I'
I I .
I
I
I
I
I
IIII
~
E*~
em __• •
(S88tePA
Note C)
I
I
I
I
I
tRAL
I
I
-~
I
/(
I
te
tRAC
I-.
I
j4
I I r - - AC
I
I I I
(He Nota B)
14 I I tAA
~
I I
II
141
-JI I
teLZ -1j4
__---.!~
I
i4-- teAL - . (
I
-- w( -: X
*')«:~1tR»(
~
~~;t~ I I L
-1Wi
IRAD
I
I
I
I
I
I
I _ _ _ -!--_ _ __
~
~
r;tASRII\LJ1
::D
~I
tpC
I
I
~ I
I
II -tep--.j
II
I'
IteAS I.i!
II
II I
~ I
I I
IRSH
-'I
I
~i
I
IRHCP
14
I
I
I
t==:!'
008-0015 _ _
SH_Nota_D
_ _ _ _ _ _~
~
I
II
I
I
I
I4--IRCH~
IRRH
'~~~;'i~
141 .tl toH
I I
I I
I I
I 'I
I I
~ toFF
I
FtoEZ
~
I -+I
j4-tAA4
I I
~ ~~:
DQO-DQ7 _ _
Se_8_N_ota_D
......_ _ _ _ _ _
I
I
toEA 14
I
~ ~,toHO
I
~ *:~?K~.E:~~toEA~ ~
I
~
)>-________
I I
~to
~
I
HO
'~~~~~~~~g.~££'l'I"7'rm~
To hold the address latched by the first iCAS going low, the parameter teLCH must be met.
teAC is measured from xCAS to ita corresponding DQx.
Access time Is tePA or tM dependent.
Output can go from the high-impedance stete to an iiwalid-data state prior to the specified access time.
A write cycle or read-modify-write cycle can be mixed with the read cycles ae long ae the wrlte- and read-modlfy-wrIte-t1mlng
specifications are not violated.
F. iCAS order Is arbitrary.
NOTES: A.
B.
C.
D.
E.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1-143 • HOUSTON. 'TeXAS 77251-1-143
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16·BIT HIGH·SPEED DRAMS
SMKSl80A- MAY 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Add .....
Column
14
See Note B
: . - - twP
tos1-1 i
w
=.
DQO-7
DQ
I
~
XX)OO(X)O()( Don't Care
~tcWL~
tcWL
---.!
~
twCH
~
I
'AWL
VV\.fV\/'\.A/V
:>
[U
I
~
a:
J
[;-Fo;~;~
1w:ES;:W ~fn~E~ ~
~ :,"I~m~E(¥o:~
~
W-
i4-Valld ItnDH
=1.~
0;:::"
8
II:
valid In
)@OOS::€~:~e;*::~ 0-
NOTES: A. To hold the address latchad by the first xCAS going low, the parameter tcLCH must be met.
B. Referenced to the first xCAS or W. whichever occurs last
C. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-wrlte-tim Ing
specifications are not violated.
D. xCAS order Is arbitrary.
Figure 7. Enhanced·Page-Mode Write-Cycle TIming
~TEXAS
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON, TEXAS 77261-1443
4-181
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH;,SPEED DRAMS
SMKS18OA-MAY1996-REVlSEDJUNE 1996
.
PARAMETER MEASUREMENT INFORMATION
---------.-.-...~
i 1;
/ 1+ IRCD --.I
teSH
./
j+--IRSH -
--- ~!
/ I~
II
:+-I
II X (..
Ii
'X/ I
I I
/I
I:
./
~
0
Vi
C
c:
~!
II 1
~ I
14
i+--lRAc H
1 tAA .
."
:rJ'
-:e
teWD
.~
__
1 I
I~
teWL
!~
~,~I
111M 1 I~
II4t-I~ .1
twP
i1: tRwD~ I
IRes
-I
m
m
I
i4-T--
II
teLZ
DQO-DQ15
~
I
~I
-.114-
..,
tDH
------~
-
valldO~
j+-- toEA - - . , I
I
I
1
falldln
10lIl
..,;1.14-_
)
10lIl
tos
~
.11
1
~
tePA
/
14
~
.1
I
(... Note B)
~
toEH
,.
Valldln
/
)>-11-----
1
1
01
toEH
I
(se. Not. ~)Lr: ~11d Out
L
./
14
I
il4-~--...·t-1-IRWL
h-teAC"N-
(')
<
1
~it_~
I+- I F
~ .1
'AWD --+I
I
Ifwt -.,
:rJ
,---
1
tASR
tASC ..., ~
."
II
teLCH ---.,
II
.
111II ~-
tCP
NoteA)
1~
..
1 '----
_I
/
~
!/ !/
Add,..
j+-
tRP ~
~/~
/
1
-
\}
I
~
NOTES: A. To hold the address latched by the first ~ going low, the parameter teLCH must be met.
B. Access time is tePA or 1M dependent.
C. Output can go from the high-ImpedanCe stete to an Invalld-clata state prior to the specified access time.
D. xCAS order 18 arbitrary.
E. A read or write cycle can be Intermixed with read-modify-write cycles as long as the read- and write-cycle timing speclflcations are
not violated.
.
F. tcAc Is measured from ~ to its corrasponding 00x.
Figure 8. Enhanced-Page-Mode Read-Modlfy-Wrlte-Cycle Timing
~1ExAs
4-182
INSTRUMENTS
POST OFFICE sox 1...:1 • HOUSTON. TEXAS 772111-1...:1
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576·WORD BY 16-BIT HIGH·SPEED DRAMS
SMKS18OA- MAY 1996 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
xCAS
~::~:~x¥-~e:~
lASR
~
:I
~ ~
See NoleA
~
~
lRAH
Addre.. §@§::~s~x~e:~ Row )@2:¥-*~g~~:W<~_R_OW__
Vi
~::&:n~g:~:~
DQO-DQ15 - - - - - - - - - HI-2 - - - - - - - - - - -
NOTE A: All XCAS must be high.
Figure 9. RAS-Only Refresh-Cycle Timing
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
4-183
TMS416160,TMS416160P, TMS418160, TMS418160P
TMS426160, TMS42616C)P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS18OA-MAY1995-REVlSEDJUNE 1995
PARAMETER MEASUREMENT INFORMATION
'1J
:u
oc
c
~
'1J
:u
~
Figure 10. Hidden-Refresh-Cycle nmlng
-~
4-184
:'IlExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lEXAS 77251-1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS18OA- MAY 1996 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
~I~---------------~C--------------~~
I+-- tRP ~I14-~---'------- tRAS _ _ _ _ _ _ _ _ _..,., I
1'1
, ~I____~_
_ _ _ _J
N
,
IfI
~PC --.I ~ tcSR - ,
\l.
t
Y-------
~I- - - - - - - - - - - - - - - - - - - - - -
-., j4-
!.
+.
o j-
-
-
-
tcHR -------.t.1
IT
Vi
~:efi::;,'€~
Add,...
~:e'f~1:¥.f,:~
OE
~:efiK¥.f,:~
DQO-DQ15
- - - - - - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - - - - - - NOTE A: Any ~ can be used.
Figure 11. Automatlc-CBR-Refresh-Cycle Timing
~
~
a:
a.
ti
:::)
c
o
a:
a.
~1ExAs
INSTRUMENTS
POST. OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
4-185
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS16OA- MAY 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
144----lRAss ----~~
I
I
I _ _ _ _ _ _ _ _ _ _....J I
fi
--- 1
~I
tRPC 14
-.-A
teSR
11
N
N
~
I
~
tRPS ----1'14f---+l~1
I
14-
-.: !+- teHS
:~~~~
!+-teP--.!
Add .....
~5E~
"~=E~
'1J
OE~=;:~
:xJ
oC
~
c:
o-t
000...,DQ15
r-
toFF
~_-----_ _ _ HI.z_....;._ _ _ _ _ _ _ __
'1J
Figure 12. Self-Refresh-Cycle nmlng
:xJ
-=em~
device symbolization (TMS416160P Illustrated)
t~
TI
P
Speed ( -60, - 70, -60)
Low.power/SeIf·Refruh Oulgnator (Blank or p)
.TMS418160 ~
W
By
M
I +
Package Code
Aeeembly Site Code
Lot Traceability Code
Month Code
VearCode
Ole Revlalon Code
Wafer Fab Code
~1ExAs
4-186
INSTRUMENTS
POST OFFICE BOX 14013 • HOUSTON, lEXAS 77251-14013
TMS4644001P 167n216-WORD BY 4-BIT
TMS4648001P 8388608-WORD BY 8-BIT
TMS4641601P 4194304-WORD BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORIES
This data sheet is applicable to aI/
TMS464400/P,
TMS464800/P,
and
TMS464160/P devices symbolized with
Revision "An and subsequent revisions as
described on page 4-189.
• All Inputs, Outputs, and Clocka Are LVTTL
Compatible
• Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR) Refresh
• Long Refresh Period
- 4096-Cycle CBR Refresh In 64 ms (max)
- 8192-Cycle RAS-Only Refresh In 64 ms
(max)
• Organization
16777216 x 4 TMS464400, TMS464400P
8388608 x 8 TMS464800, TMS464800P
4194304 x 16 TMS464160, TMS464160P
• Low-Power, Self-Refresh Version
(TMS464400P, TMS464800P, TMS464160P)
• TMS464400/P and TMS464800/P In
High-Reliability Plastic 32-Lead
400-MII-Wlde Surface-Mount (DZ) Package
and 32-Lead Surface-Mount Thin
Smail-Outline Package (DGC)
• Single 3.3-V Power Supply
(:1:0.3 V Tolerance)
• Operating Free-Air Temperature Range
O·Cto 70·C
• Low Power Dissipation
- CMOS Standby
- Extended Refresh
- Battery Backup
• Fully Compatible With 840Megabit DRAM
Specification From Hitachi
• Texas Instruments EPIC™ CMOS Process
3=
w
• 3-8tate Unlatched Outputs
• Performance Ranges:
ACCESS
TIME
fRAC
(MAX)
ACCESS
TIME
teAC
(MAX)
ACCESS
TIME
tAA
(MAX)
READ
OR WRITE
CYCLE
(MIN)
TMS464400/P-60
TMS464400/P-70
TMS484400/P-80
60ns
70ns
SOns
15ns
18ns
20ns
30ns
35ns
40ns
110 ns
130 ns
150 ns
TBOmA
TBOmA
TBOmA
TBOmA
TBOmA
TBOmA
TMS464800/P-80
TMS4848OOIP-70
TMS464800/P-SO
60ns
70ns
SOns
15ns
18ns
20ns
30ns
35ns
40ns
110 ns
130ns
150 ns
120mA
110mA
l00mA
120mA
110mA
l00mA
TMS48416O/P-60
TMS464160/P-70
TMS464160/P-SO
SOns
70ns
SOns
15n8
18ns'
20n8
3On8
35ns
4On8
110 ns
130 n8
150ns
TBOmA
TBOmA
TBOmA
TBOmA
TBOmA
TBOmA
ICCl
OPERATING
CURRENT
(MIN)
~
Icca
REFRESH
CURRENT
(MIN)
a:
a.
b
:::l
C
o
a:
a.
description
The TMS464400, TMS464800, TMS464160 series are high-speed, 67108864-bit dynamic random-access
memories (DRAMS), organized as either 16 777 216 words of four bits each (TMS464400), 8388608 words
of eight bits each (TMS464800), or 4194304 words of 16 bits each (TMS464160).
The TMS464400P, TMS464800P, and TMS464160P series are high-speed, low-voltage, low-power,
self-refresh and extended-refresh, 671 08864-bit DRAMS, organized as either 16 777 216 words of four bits
each (TMS464400P), 8388608 words of eight bits each (TMS464800P), or 4194304 words of 16 bits each
(TMS464160P).
The TMS464400/P and TMS464800/P are offered in a 400-mil32-lead plastic surface-mount SOJ package
(DZ suffix) and a 32-lead plastic surface-mount thin small-outline TSOP package (DGC suffix). The
TMS464160/P packages are still being discussed by JEDEC. All packages are characterized for operation from
0·Cto70·C.
=_--.. . - . . . -
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PRIMEW_ -.mi povducIIln 111 _ _ ..
•
..
.......---...,..
OIII . . dooIlIII'- ToxuInolru _ _ IIIoIghtID
~TEXAS
Copyright 01995, Texas Instrumen1B Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
4-187
TMS464400/P 16777216-WORDBY 4-BIT
TMS464800/P 8388608-WORD BY B-BIT
TMS464160/P4194304-WORD BY 16-BITDYNAMIC RANDOM-ACCESS MEMORIES
SMWSOO3A- MARCH 1995 - REVISED JUNE 1995
TMS484400
DZ, DOC PACKAGES
(TOP VIEW)
Vee
1'
D01 = 2
DQ2 = 3
NC = 4
NC = 5
NC =8
NC =7
W=8
RAS =9
AO = 10
A1 = 11
A2. F= 12
A3 F= 13
A4 F 14
AS F= 15
Vee
18
32
31 F
30 F
29F=
28 F
27F=
281=
25=
24=
23=
22=
21 =
20=
19 =
18=
17=
Vss
DQ4
D03
PIN NOMENCLATURE
NC
NC
NC
AO-A12
~
001-004
CAS
NC
OE
l5E
RAS
A12
A11
A10
A9
AS
Addreaa Inputs
CoJumn-Addreaa Strobe
Data In/Data Out
No Intemal Connection
Output Enable
Row-Addreaa Strobe
WrIte Enable
Vee
3.3-V Supply
VSS
Ground
A7
AS
Vss
TMS484800
DZ, DGC PACKAGES
(TOP VIEW)
Vee =
1
DOO = 2
D01 =3
D02 =4
D03 = 5
NC =
8,
Vgg, = 7
W= 8
RAS
AO =
A1 =
9
10
11
A2. = 12
A3 = 13
A4 14
AS = 15
Vee = 18
32 Vss
31 F D07
30 F D06
29F= DOS
28F= D04
27 F VSS
28 F CAS
25F= OE
24F= A12
23 F A11
22F= A10
21 F A9
2OF= AS
PIN NOMENCLATURE'
AO-A12
CAS
OQO-OQ7
NC
l5E
RAS
Vi
Vee
Vss
19 A7
18= AS
17= VSS
~1ExAs
4-188
INS1RUMENTS
POST OFFICE BOX 1441- HOUSTON. '!eXA8 77251-1441
Addreaa Inputs
Column-Addreaa Strobe
Data In/Data OUt
No Internal Connection
Output Enable
Row-Addreaa Strobe
WrIte Enable
3.3-V Supply
Ground
TMS464400/P 16m216-WORD BY 4-BIT
TMS464800/P 8388608-WORD BY 8-BIT
TMS464160/P 4194304-WORD BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMWSOOSA- MARCH 1I11III- REVISED JUNE 1995
TMS48418ODZ, DGC PACKAGE
(TOP VIEW)
Vss
DQ15
DQ14
DQ13
DQ12
AO-A12t
VOO
VSS
'OAS or LeE, UCE
DQ4
005
DQ6
DQ7
DQ11
DQ10
DQ9
Das
NO
OE
RAS
Iii
VSS
Vec
VCC
Vii
RE
NO
NO
NO
NO
AO
A1
A2
9
PIN NOMENCLATURE
000-0015
NC
RE
roe
VSS
UOE
OE
NO
NO
A12/NOt
A11
A10
Address Inputs
Column-Address Strobe
Data In/Data OUt
No Intemal Connection
Output Enable
Row-Addrees Strobe
Read Enable
Write Enable
3.3-V Supply
Ground
;:
Table 1. TMS464160 Refresh Configuration
4KREFRESHt
W
IKREFRESHt
Row/refresh addresses
AO-A11
AO-A12
Column addresses
AO-A9
AO-AS
~
a:
A3
AS
AS
a.
A4
AS
A7
A6
b
::l
Vce
VSS
C
o
a:
t Pin 33 is A 12 for 8K refresh and NC for 4K refresh. CBR refresh is strongly recommended for this device.
a.
device symbolization (TMS464400P Illustrated)
t~
TI
P
TMS484400 ~
W
B
Y..
M
T+
SpHd ( -60, -70, .80)
Po_r/Self-Refreah Code
Peckage Code
Assembly SHe Code
Lot TraceabURy Code
Month Code
YnrCode
Die Revlalon Code
Wafer Fab Code
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 772111-1443
4-189
TMS464400/P 16m216-WORD BY 4-BIT
TMS464800/P 8388608-WORD BY &;BIT
.
TMS464160/P4194304-WORD BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMWSOO3A- MARCH 1996- REVISED JUNE 1996
4-190
-!llExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
TMS416169, TMS416169P, TMS418169, TMS418169P
TMS426169, TMS426169P, TMS428169, TMS428169P
'1 048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH.;SPEED DRAMS
SMKS888A- APRIL 1995 - REVISED JUNE 1896
• Organization ••• 1 048576 x 16
• Single Power Supply (5 V or 3.3 V)
• Performance Ranges:
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
EDO
CYCLE
'RAc
'cAC
1M
MIN
MAX
MAX
MAX
15n. 30ne
25ne
'4xX188/P-60 8On.
18n. 35ne
30ne
'4xX188fP.70 lOne
35ne
'4xx188/P-60 8On. 2On. 40ne
• Extended Data Out (EDO) Operation
• iCAI·Before·FiAS (xCBR) Refresh
• Long Refresh Period and Self·Refresh
Option (TMS4xx169P)
• 3-State Unlatched Output
• Low Power DiSSipation
• Hlgh·Rellablllty Plastic 42·Lead (DZ Suffix)
4OO·MII·Wlde Surface·Mount (SOJ) Package
and 44/50·Lead (DGE Suffix) Surface·Mount
Thin Small·Outllne Package (TSOP)
• Operating Free·Alr Temperature Range
G·Cto 7G·C
• Texas Instrument Enhanced Performance
Implanted CMOS (EPIC™) Process
DEVICE
TMS4161S9
TMS4161S9P
TMS418169
TMS418169P
TMS42S169
TMS426169P
TMS4261S9
TMS428169P
DGEPACKAGE
(TOP VIEW)
DZPACKAGE
(TOP VIEW)
Vcc
DOO
D01
D02
D03
VCC
D04
D05
D06
D07
NC
NC
1
2
3
40
39
3S
8
37
38
35
9
34
33
11
32
W
RAS
A11t
A10t
AO
A1
Vcc
-
2
3
6
DQ6
9
D07
NC
10
11
VSS
D015
D014
D013
D012
VSS
44 D011
43 D010
42 D09
41 D08
40 NC
NC
NC
W
RAS
A11t
A10t
AO
A1
A2
A3
VCC
NC
LCAS
UCAS
~
A9
AS
A7
A6
AS
A4
VSS
AO-A11
000-0015
LeAS
~
RAS
PIN NOMENCLATURE
Address Inputs
Data In/Data Out
Lower Column-Address Strobe
Upper Column-Address Strobe
No Intemal Connection
output Enable
Row-Address Strobe
5-V or 3.3-V Supply*
Ground
Write Enable
The TMS4xx169 and TMS4xx169P are offered in a 44/50-lead plastiC surface-mount TSOP (DGE suffix) and
a 42-lead plastic surface-mount SOJ (DZ suffix) package. These packages are characterized for operation from
O·Cto 70·C.
EPIC is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
D.
U
::::»
D.
These devices feature maximum RAS access times of 60 ns, 7D-ns, and 80 ns. All addresses and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system fleXibility.
~ThxAs
~
a:
oa:
The TMS4xx169 series is a set of high-speed,
Vcc
16777216-bit dynamic random-access memo~S
ries (DRAMs) organized as 1 048576 words of
W
16 bits each. The TMS4xx169P series is a similar
* See Available Options Table.
set of high-speed, low-power, self-refresh,
16777216-bit DRAMs organized as 1048576
words of 16 bits each. Both sets employ state-of-the-art EPIC™ technology for high performance, reliability, and
low power at low cost.
INSTRUMENTS
3:
w
c
t A10 and A11 are NC for TMS4x8169 and TMS4x81S9P.
NC
OE
description
VCC
DOO
001
D02
D03
Vcc
D04
D05
OE
A9
AS
A7
A6
AS
A4
Vss
A2
A3
AVAILABLE OPTIONS
SELF
POWER REFRESH,
REFRESH
SUPPLY BATTERY
CYCLES
BACKUP
5V
4096 In 64 ms
5V
Yes
4096 In 128 ms
1024 In 16ms
5V
1024 In 128 ms
5V
Yes
3.3V
4096 in 64ms
3.3 V
Yes
4096 In 128 ms
3.3V
1024 in 16 ms
3.3V
Yes
1024 In 128 ms
Vss
0015
D014
D013
D012
VSS
D011
D010
D09
D08
NC
LCAS
UCAS
CopyrIght 411 1995, Texas Instrument8 Incorporated
4-191
TMS416169, TMS416169P, TMS418169,TMS418169P
TMS426169, TMS426169P, TMS428169, TMS428169P
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS888A-APRIL 1995- REVISED JUNE 1995
logic 8y~bolt
RAM1Mx18
17
AO
18
A1
18
A2
20
A3
23
A4
2008/2100 ...
24
AS
25
AS
H
A7
>
20015/2107
20018
20017
20018
20018
27
Aa
28
AI
18
A10*
15
A11*
14
"
31
:u
o
c
c
~
:u
~
~
~
.~
"
23C22
>C21
G34
31
"
'"
>C20(ROW]
G231(REFRESH ROW]
24(PWROWNJ
> C21
G24
31
30
A1~575
"
23C32
r +
Z31
13
-~
29
OQO 2
23,210
..... H
,
~
OQ1 3
""'~
4
0Q2
S
0Q3
00. 7
8
OQS
9
0Q6
10
OQ7
"'"
OQl 33
L.
008 34
38
0010
38
OQ11
OQ12 38
39
0013
40
OQ14
41
OO1S
24,25EN27
34,25EN37
A,220
V28,27
A,320
V38.37
r
A,Z26
A,Z38
.:"'"
.:
.:
~
tThis symbol is in accordance with ANSVIEEE Std 91-1984 and lEe Publication 617-12.
The pin numbenl shown correspond to the DZ package.
A10 and A11 are Ne for TMS4x8169 and TMS4x8189P.
*
~TEXAS
4-192
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lEXAS 77251-1443
m~~~m~~~m~~~m~~~
TMS426169, TMS426169P, TMS428169, TMS428169P
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS888A-APRIL 1895-REVISEDJUNE 1895
functional block diagram (TMS4x6169/P)
AO
A1
.Column D.codl
•
•
•
A7
•
•
•
S.n.. Ampllfl....
Column-
AcId.....
Buffe...
258K Array
258K Array
•••
2581( Arrey
:
258K Array
w
•••
Row-
Add.....
Buffe...
DQO-DQ1S
Aa-
4
~
258KArray
A11
W
:;
w
a::
a.
(a) TMS4x6189, TMS4x6189P
functional block diagram (TMS4x8169/P)
RAS UCAS LCAS
Vi
b
:::»
OE
Q
AO
A1
A9
o
a::
a.
Column Decod.
•
•
•
•
•
•
CoIumnAdd .....
Buffe...
S.n.. Ampllfl....
258KArray
258KArray
••
•
Row-
Add .....
Buffera
268KArray
R
0
w
D
•c
258KArray
•••
0
d
I
258KArray
. DQO-DQ15
258KArray
(b) TMS4x8189, TMS4x6189P
-!llExAs
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON. TEXAS 77251-1443
4-193
TMS416169, TMS416169P, TMS418169, TMS418169P
TMS426169 j TMS426169P, TMS428169, l'MS428169P
1048576-W,ORD BY 16-BIT EXTENDED DATA OUT HIGH·SPEED DRAMS
SMKS886A- APRIL 1995 - REVISED JUNE 11195
operation
dual CAS
Two CAS pins (LCAS and UCAS) are provided to give independent control of the 16 data-I/O pins
(DQO-DQ15),wlth LCAS corresponding to DQO-DQ7 and UCAS corresponding to DQ8-DQ15. For read or
write cycles, the column address is latched on the first xCAS failing edge. Each xCAS going low enables Its
corresponding DQx pin with data associated with the column addrElsslatched on the first falling XCAS xggS
All address setup and hold parameters are referenced to the first falling iCAS' edge. The delay time from A
low to valid data out (see parametertcAc) is measured from each indMduai XCAS to its corresponding DQx pin.
In order to latch in a new column address, both XCAS pins must be brought high. The column-precharge time
(see parameter tcp) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle.
Keeping a column address valid while toggling xCAS requires a minimum setup time, tcLCH' During tCLCH, at
least one XCAS must be brought low before the other xCAS is taken high.
For early-write ~s, the data Is latched on the first XCAS failing edge. Only the DQs that have the
corresponding xCAS low are written into. Each XCAS must meet..!cAs minimum in order to ensure writing
into the storage cell. To latch a new address and new data, ail xCAS pins must be high and meet tcp.
extended data out
"tJ
Extended data out (EDO) ailows for data output rates of up to.4O MHz for 60-ns devices. When keeping the same
row address while selecting random column addresses, the time for row-address setup and hold and address
multiplex Is eliminated. The maximum number of columns that can be accessed is determined by tRASP, the
maximum RAS low time.
::D
00
oc:
....
EDO does not enter the DQs Into the high-Impedance state with the rising edge of XCAS. The output remains
valid for the system to latch the data. After xCAS goes high, the DRAM Is decoding the next address. OE and .
W can be used to control the output impedance. Descriptions of OE and W further explain EDO operation
benefit.
.
"tJ
::D
address: AO-A11 (TMS4x6169, TMS4x6169P) and AO-A9 (TMS4x8169, TMS4x8169P)
~
m
Twenty address bits are required to decode a single one of the 1048576 storage cell locations. For the
TMS4x6169 and TMS4x6169P, 12 row-address bits are set up on AO through A11 and latched onto the chip
by RAS.Eight column-address bits are set up on AO through A7 and latched on the chip by the first iCAS'. For
the TMS4x8169 and TMS4x8169P, 10 row-address bits are set up on AO-A9 and latched on the chip by RAS.
Ten column-address bits are set up on AO-A9 and latched on the chip by the first xCAS. All addresses must
be stable on or before the falling edge of RAS and XCAS. RAS is similar to a chip-enable In that it activates the
sense amplifiers as well as the row decoder. XCAS is used as a chip-select, activating its corresponding output
buffer and latching the address bits into the column-address buffers.
~
write enable (W)
The read or write mode Is selected through W. A logic high on W selects the read mode and a logic low selects
the write mode. The data input is disabled when the read mode Is selected. When W goes low prior to XCAS
(early write), data out remains in the high-Impedance state for the entire cycle, permitting a write operation
independent of the state of OE. This permits early-write operation to be completed with OE grounded. If W goes
. low in an extended-data-out read cycle, the DQs go into the high-impedance state as long as xCAS Is high.
data In (DQO-DQ15)
Data is written during awrite or read-modify-write cycle. Depending on the mode of operation, the failing edge
of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data is strobed in by the first occurring xCAS with setup and hold times referenced to this signal. In a
~TEXAS
4-194
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 1E and holding
it low after RAS falls (see parameter tcHR)' For successive xCBR refresh cycles, XCAS' can remain low while
cycling RAS. The external address is ignored and the refresh address is generated internally.
battery-backup refresh
TMS4x6169P
.A low-power battery-backup refresh mode that requires less than 600 JAA (5 V) or 350 JAA (3.3 V) refresh current
is available on the TMS4x6169P. Data integrity is maintained using xCBR refresh with a period of 31.25 tJS while
holding RAS low for less than 300 ns. To minimize current consumption, all input levels must be at CMOS levels
(V'l < 0.2 V, V,H > VCC - 0.2 V).
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 772151-1443
4-195
3:
w
[ij
a:
a.
b
:::l
C
oa:
D..
TMS416189, TMS416169P, TMS418169, TMS418169P
TMS426169, TMS426169P, TMS428169, TM$428169P
,
104857&-WORDBY 16-BIT EXTENDED DATA OUT HIGH·SPEED DRAMS
SMKS88eA-APRIL 1895 - REVISED JUNE 1996
TMS4xB169P
A low-power battery-backup refresh mode that requires less than 600 tAA (5 V) or 350 tAA (3.3 V) refresh current
Is available on the TMS4x8169P. Using xCBR refresh with a period of 125 JAB while holding
low for less
than 300 ns maintains data Integrity. To minimize current consumption, all input lE!,¥els must be at CMOS levels
(VIL < 0.2 V, VIH > Vee - 0.2 V) •
m
• elf-refre.h (TMS4xx169P)
The self-refresh mode is entered by dropping xCAS low prior to RAS going low. Then iCAS and RAS are both
held low for a minimum of 100 JAB. The chip Is then refreshed Internally by an on-board oscillator. No external
address Is required because the CBR counter is used to keep track of the address. To exitthe self-refresh mode,
both RAS and xCAS are brought high to satisfy tcHS' Upon exiting self-refresh mode, a burst refresh (refresh
a full set of row addresses) must be executed before continuing with normal operation. The burst refresh
ensures the DRAM is fully refreshed.
power-up
To achieve proper device operation, an Initial pause of 200 JAB followed by a minimum of eight initialization cycles
is required after power-up to the full Vee level. These eight Initialization cycles must include at least one refresh
(RAS-only or xCBR) cycle.
'
,
"1J
:D
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)t
oC
Supply voltage range, Vee:
TMS41x169,TMS41x169P ....................... -1Vto7V
TMS42x169, TMS42x169P •••••.•.•....•••.••• - 0.5 V to 4.6 V
Voltage range on ,any pin (see Note 1): TMS41x169, TMS41x169P ....................... -1 Vto 7V
TMS42x169, TMS42x169P ••••••••••••••.•••.• - 0.5 V to 4.6 V
Short-circuit output current •••••.•.•.• " •••••••.•....' •••..•••.••.•. ; • • • . . • . . . . • • •• . • • . • • • • •• 50 mA
Power dissipation •.......•.......•.•..•...•••....•..•.•...•......•.......•.....••.. ;....... 1 W
Operating free-air temperature range, TA .................... ,......................... O°C to 70°C
Storage temperature range, Tstg .................................................. - 55°C to 125°C
c:
o
....
"1J
:D
~
-~
t stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. Tliese are streSs ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" Is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
'42x189
'41x189
MIN
NOM
MAX
MIN
NOM
4.5
5
0
5.5
'3
3.3
0
8.5
0.8
2
-0.3
Vee
Supply voltage
VSS
Supply voltage
VIH
High-level Input voltage
2.4
VIL
Low-level input voltage (see Note 2)
-1
MAX
3.8 '
UNIT
V
V
Vee + 0.3
0.8
V
V
0
7~
"C
NOTE 2: The algebraic convantion, where the more negative (less positlV8) limit'.18 designated es minimum, Is used for logic-voltage levels only.
TA
Operating free-alr temperature
0
~1ExAs
4-198
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77261-1443
70
TMS416169, TMS416169P, TMS418169, TMS418169P
TMS426169, TMS426169P, TMS428169, TMS428169P
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS888A- APRIL 11185 - REVISED JUNE 11185
TMS416169/P
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
'418189·80
'418189P·80
TEST CONDITIONst
MIN
MIN
MAX
'418189·80
'41818tP·80
MIN
UNIT
MAX
VOH
High-level output
voltage
'0Hz-SmA
VOL
Low-level output
voltage
IOL= 4.2 mA
0.4
0.4
0.4
V
II
Input current
(leakage)
VI- OVto6.S V,
VCC 5.5 V,
All others = 0 V to VCC
=
:0:10
:0:10
:0:10
IIA
Output current
VCC=S.Sv,
XCAShlgh
Vo =OVtoVCC,
:0:10
:0: 10
:0:10
IIA
Vcc = 5.5 V,
Minimum cycle
90
60
70
rnA
2
2
2
mA
1
1
1
rnA
500
500
500
IIA
90
60
70
mA
tHpC-MIN,
XCAScycling
100
90
60
mA
xCAS<0.2V.
RAS<0.2V.
Measured after tRASS min
500
500
500
IIA
tRAS oS 300 ns.
tRC" 31.25l1li.
VCC-0.2 V .. VIH oS 6.5 V,
o V .. V,L" 0.2 V. iN and OE - VIH.
Addl'8ll and data stable
eoo
eoo
eoo
IIA
10
ICC1*§
ICC2
1CC3§
~eakage)
Read· or write-cycle
current
Standby current
Average refresh
current (RAS-only
refresh or CBR)
1CC4*'1 Average EDO current
Ieee'
Self·refresh current
Battery back-up
operating current
ICC10* (equivalent refresh
time Is 126 ms): CBR
only
\
MAX
'418189·70
'418189p·70
2.4
2.4
VIH = 2.4 V (TTL.),
After 1 memory cycle.
RAS and XCAS high
VIH .. Vcc - 0.2 V (CMOS).
After 1 memory cycle.
RAS and xCAS high
'416169
'416169P
2.4
V
Minimum cycle.
VCC-S.SV.
RASCYCling.
xCAS high (RAS only).
RAS low after xCAS low (CBR)
VCC-S.SV,
RASIow.
t For conditions shown as MIN/MAX. uas the appropriate value specified In the timing requirements.
* Measured with outputs open
§ Measured with a maximum of one address change while RAS "' VIL
11 Measured with a maximum of one address change while xCAS = V,H
* ForTMS416169P only
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
4-197
~
~
a:
D.
b
:::l
C
o
a:
D.
TMS416169, TMS416169P, TMS418169, TMS418169P
TMS426169, TMS426169P, TMS428169, TMS428169P
1048576-WORD BY 16~BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS888A-APRIL 1995-REVISEDJUNE 1995
TMS4181.69/P
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
,
PARAMETER
'418169·80
'4181891'·80
TEST CONDITIONSt
MIN
VOH
High-level output
voltage
IOH"-5mA
VOL
Low-level output
voltage
10L =4.2 mA
II
Input current
(leakage)
10
Output current
(leakage)
Read-or
ICC1*' wrlte-cycle current
"o
:xl
ICC2
Standby current
C
"~
:xl
-~
MAX
MIN
MAX
MIN
V
0.4
0.4
VCC=5.5V,
VI =OVto8.5V,
All others .. 0 V to VCC
:1:10
:1:10
:I:
VCC=5.5V,
XCAShlgh
VO=OVtoVCC,
:1:10
VCC = 5.5 V,
Minimum cycle
VIH .. 2.4 V (TTL),
After 1 micC0ry cycle,
RAS and AS high
VIH = VCC - 0.2 V (CMOS),
After 1 memory cycle,
RAS and xCAS high
1'418189
UNIT
MAX
2.4
2.4
2.4
'418169·80
'418169P·80
0.4
V
10'
t1A
.. 10
.. 10
t1A
190
180
170
mA
2
2
2
mA
1
1
1
mA
500
t1A
170
mA
1'418189P
500
500
ICC3'
Average refresh
current (RAS-only
refresh or CBR)
Minimum cycle,
VCC = 5.5 V,
RAScycling,
xCAS high (RAS only),
RAS low after xCAS low (CBR)
190,
180
IC04*'
AverageEDO
current
VCC",,5.5V,
RASIow,
tHPC" MiN,
XCAScycling
100
90
80
mA
ICca'
Self-refresh current
xCAS<0.2V,
RAS < 0.2 V,
Measured after tRASS min
500
500
500
t1A
tRAS s 300 ns,
tRC"' 125 J.&S,
VCC - 0.2 V s VIH s 8.5 V,
OVsVILsO.2V, Wand(5E=VIH,
Address and data stable
800
800
800
t1A
C
~
'418169·70
'418169P·70
Battery back-Up
operating current
ICC10' (equivalent refresh
time is 128 ms);
,CBRonly
--
--
t For conditions shown as MINIMAX, use the approprlata value specified in the timing requirements.
* Measured with outputs open
'
§ Measured with a maximum of one address change while RAS = VIL
, Measured with a maximum of one address change while XCAS = VIH
'For TMS418169P only
~TEXAS
4-198
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON,1CXAS 77251-1443
r
TMS416169, TMS416169P, TMS418169, TMS418169P
TMS426169, TMS426169P, TMS428169, TMS428169P
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886A- APRIL 1995 - REVISED JUNE 1995
TMS426169/P
electrical characteristics over recommended ranges of supply voltage and operating free-alr
conditions (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONst
'426168-60
'426168P-60
MIN
High-level
output
voltage
10H =-2mA
LVTTL
IOH--1001lA
LVCMOS
VOL
Low-level
output voltage
II
Input current
Oeakage)
LVTTL
IOL=2mA
LVCMOS
10L= 1001lA
VI -OVto3.9V,
VCC=3.6V,
All others = 0 V to VCC
VOH
10
Output current
Oeakage)
Read- or writeICC1*' cycle current
ICC2
1CC3§
Standby
current
Average
refresh current
(RAS-only
refresh
orCBR)
AveregeEDO
1CC4*'1 current
ICes*
Self.refresh
current
'426168-70
'426168P-70
MIN
MAX
2.4
'426168-80
'426168P-80
MAX
2.4
MIN
UNIT
MAX
2.4
V
VCC-O.2
0.4
0.4
0.2
0.2
0.2
2: 10
2:10
2:10
IlA
2:10
2:10
2:10
IlA
90
60
70
mA
1
1
1
mA
'426168
500
500
500
IlA
'426169P
200
200
200
IlA
Vo = 0 Vto VCC,
VCC=3.6V,
Minimum cycle
VIH = 2 V (LVTTL),
After 1 memory cycle,
RAS and xCAS high
, Minimum cycle,
VCC- 3•6V,
RAS cycling,
~ high (RAS-only refresh)
RAS low after ~ low (CBR)
VCC=3.BV,
RASlow,
VCC-0.2
0.4
VCC=3.6V,
XCAShlgh
VIH =VCC-0.2V
(LVCMOS),
After 1 memory cycle,
RAS and xCAS high
VCC-0•2
tHPC = MIN/
~cycllng
xCAS < 0.2 V,
RAS < 0.2 V,
Measured after tRASS min
90
60
70
V
mA
~
~
a::
Il.
ti
::::)
100
90
60
mA
250
250
250
IlA
350
350
IlA
Battery
back-up
operating
tRC = 31.25 JUI, tRAS " 300 ns,
current
Vcc -0.2 V" VI~ 3.9 ~
350
ICC10* (equivalent
OV"VIL " 0.2 V, Wand OE =VIH,
refresh time Is
Address and data stable
126ms),
CBRonly
t For conditions shown as MINIMAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
'I Measured with a maximum of one address change while ~ = VIH
* ForTMS426168P only
*
-!!I TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. Ti:xAs 77251-1443
4-198
c
oa::
Il.
TMS416169,TMS416169P,TMS418169, TMS418169P
TMS426169, TMS426169P, TMS428169, TMS428169P
1048576-WORD BY 16'1'BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886A-APRIL 1995 - REVISED JUNE 1996
TMS428169/P
electrical characteristics over recommended ranges· of. supply voltage and operating free..lr
conditions (unle.. otherwise noted) (continued)
, '
PARAMETER
TEST CONDlTlONSt
MIN
MAX
MIN
UNIT
MAX
LVTTL
IOH,,-1oojAA
LVCMOS
Low-level
output voltage
IOL-2mA
LVTTL
0.4
0.4
0.4
VOL
IOL .. 1oojAA
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
Voo=3.8V,
VI "OVto3.9V,
All others = 0 Vto Voo
:0:10
:0:10
:0:10
JAA
10
Output current
(leakage)
VCC-3.6V,
XCAShlgh
Vo -OVtoVoo,
:0:10
:0:10
:Z10
JAA
Raad-orwritaloo1*' cycle currant
VCC=3.8V,
Minimum cycle
190
180
170
rnA
1
1
1
rnA
'428189
500
500
500
JAA
'428169P
200
200
200
JAA
1002 ,
Standby
current
c:
-~
MIN
IOH,,-2rnA
"'0
~
"'0
:a
~
MAX
'4281611-80
'4281611P-80 ,
High-level
output
voltage
VOH
:a
oc
'4281611-70
'428189P-70
'4281611-80
'4281611P-80
2.4
2.4
2.4
'V
VIH .. 2 V (LVTTL),
After 1 memory cycle,
RAS and XCAS high
VIH .. Voo - 0.2 V
(LVCMOS),
After 1 memory cycle,
AAS and XCAS high
Voo-0•2
VCC-O.2
Voo-0•2
V
1CC3§
Average
refresh currant
(AAS-only
refresh
orCBR)
Minimum cycle,
VCC-3.8V,
RAScycllng,
XCAS high (RAS-only refresh)
AAS low after XCAS low (CBR)
190
180
170
rnA
ICC4*'
AverageEDO
current
Voo=3.6V,
AASIow,
100
90
60
rnA
Icee'
Self-refresh
current
XCAScO.2V,
AAScO.2V,
Measured after tRASS min
250
250
250
JAA
350
350
JAA
tHPCooMIN;
~cycling
Battery
beck-up
operating
tRAS s 300 ns,
tRC 125 \18,
currant
VCC - 0.2 V S VII-\.! 3.9 V,
350
10010' (equivalent
OVsVILsO.2V, Wand~"VIH'
refresh Ulne Is Address and data stable
128ms),
CBRonly
t For conditions shown as MIN/MAX. use the appropriate value specified In the timing requirements.
Measured with outputs open
§ Measured with a maximum of one address change while AAS .. VIL
'I( Measured with a maximum of one address change while XCAS = VIH
'ForTMS428169Ponly
.
=
*
~1ExAs
4-200
INSTRUMENTS
POST OFFICE BOX 1_ • HOU8TON, 'IECAS 77251-1_
TMS416169, TMS416169P, TMS418169, TMS418169P
TMS426169, TMS426169P, TMS428169, TMS428169P
1048576-WORD BY 16·BIT EXTENDED DATA OUT HIGH·SPEED DRAMS
SMKS888A-APRIL 1895 - REVISED JUNE 1895
capacitance over recommended ranges of supply voltage and operating f ......lr temperature,
.
f = 1 MHz (see Note 3)
PARAMETER
MAX
MIN
UNIT
CI(A)
Input capacitance, AO-A11
5
Ci(OE)
Input capacitance, ~
7
pF
CitRC)
7
pF
Ci(W)
Input capacitance, ~ and ~
Input capacitance, W
7
pF
Co
Output capacitance
7
pF
pF
NOTE 3: Vee" 5 V z 0.5 V or 3.3 V z 0.3 V, and the bias on plna under teat Is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'4XX168-80
'4XX168P-80
PARAMETER
MIN
MAX
'4Xx168-70
'4Xx168P-70
'4XX168-80
'4XX168P-80
MAX
MIN
MIN
UNIT
MAX
tAA
Access time from column addreee (eee Note 4)
30
35
40
ns
tcAc
Access time from ~ low (eee Note 4)
15
18
20
ns
tePA
tRAG
Access time from column precharge (eee Note 4)
Access time from ~ low (eee Note 4)
35
40
45
ns
60
70
na
toEA
Access time from ~ low (eee Note 4)
15
18
80
20
teLZ
Delay time, ~ low to output In low-impedance state
toEZ
tREZ
Output disable time after ~ high (eee Note 5)
3
15
3
18
3
Output disable time after JQ! high (eee Note 5)
3
15
3
18
3
teEZ
Output disable time after ~ high (eee Note 5)
3
15
3
18
3
twEz
Output disable time after Wlow (eee Note 5)
3
15
3
18
3
0
0
0
na
na
20
20
20
20
ns
na
na
na
NOTES: 4. Access times for TMS42X168 are measured with output reference levels of VOH .. 2 V and VOL = 0.8 V.
5. Maximum tREZ, teEZ, twEZ and toEZ are specified when the output Is no longer driven.
EDO timing requirements over recommended ranges of supply voltage and operating fre..alr
temperature
'4Xx189-80
MIN
lHpc
MAX
'4Xx189-70
MIN
MAX
'4xx189-80
MIN
.MAX
UNIT
25
30
35
na
80
90
100
na
tcsH
Cycle time, EDO page-mode read or write
Cycle time, EDO read-write
Hold time, ieA! from JQ!
50
55
80
na
teHO
Hold time, ~ from iCM
10
10
10
na
tpRWC
tooH
Hold time, output from ~
teAs
Pulse dul'lltlon, iCM
3
10
3
10000
12
3
10000
15
ns
10000
ns
twPE
Pulse duration, W (output disable only)
tacH
toP
Setup time, ~ befora iCM
Precharge time, iCM
5
5
5
na
toEP
Precharge time, OE
5
5
5
na
5
5
ns
10
5
10
10
ns
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lEXAS 772&1-1443
4-201
m~~~m~~~m~~~m~~~
TMS426169, TMS426169P, TMS428169, TMS428169P
1048576-WORD BY 16..BIT EXTENDED DATA OUT HIGH..SPEED .DRAMS
SMKS888A-APRIL 1996-REVISEDJUNE 1995
tlmlngrequlrementsovei recommended ranges of supply voltage and operating fre. .lr
temperature
'4xx169-60
'4XX169P-60
MIN
tAc
Cycle time, read (see Note 6)
twc
tRWC
tRASP
tRAS
tRP
Cycle time. write (see Note 6)
twP
tASC
tASR
tDS
tcwL
Setup time, W low before iCAS high
Setup time, W low before RAS high
Setup time, W low before xCASIow (ear1y-wrlte operation only)
tRWL
o
c
twcs
c:
teAH
tDH
tRAH
:::u
~
-~
Pulse duration. W low
Setup time. column ac.dress before ~ low
Setup time, row address before RAS low
Setup time, data (see Note 8)
Setup time, W high before xCAS low
"'U
"'U
Pulse duration. RAS high (precharge)
tRCS
:::u
~
Cycle time. read-write (see Note 6)
Pulse duration, RAS low, page mode (see Note 7)
Pulse duration, RAS low, non page mode (see Note 7)
tRCH
tRRH
twCH
teLCH
tRHCP
Hold time, column address after ~ low
Hold time. data (see Note 8)
Hold time. row address after RAS low
Hold time, W high after ~ high (see Note 9)
Hold time, W high after RAS high (see Note 9)
Hold time. W low after iCAS low (ear1y-wrlte operation only)
Hold time, xCAS low to xCAS high
Hold time, RAS high from ~ precharge
MAX
110
110
150
60 100000
80 10000
40
10
0
0
0
0
10
10
0
10
10
. 10
'4xx169-70
'4xx169P-70
MIN
MAX
130
130
175
70 100000
70 10000
50
10
0
0
0
0
12
'4xx169-60
'4XX169P-80
MIN
UNrr
MAX
150
150
200
80 100000
80 10000
80
10
0
0
0
0
15
15
0
15
na
ns
na
na
ns
na
ns
na
na
ne
ne
ne
ne
0
0
10
5
35
15
10
12
0
15
15
10
0
0
15
5
40
18
10
-50
-50
-50
ne
ne
na
na
na
n8.
ne \
15
10
0
0
15
5
45
ns
ne
na
ne
ne
toEH
tROH
Hold time, C5E command
teHS
Hold time, ~ low after RAS high (self refresh)
tAwo
Delay time. column address to W low
(read-Wrlta operation only)
65
83
70
na
Delay time. RAS low to ~ high (xCBR refresh only)
Delay time, XCAS high to RAS low
10
5
10
5
lit
Delay time. RAS low to iCAS high
50
80
Delay time. xCAS Iow.to RAS low (xCBR refresh only)
Delay time. iCAS low to W low (read-write operation only)
os
os
40
10
5
65
5
48
18
15
tCHR
teRP
teSH
teSR
tcwD
toED
tRAD
tRAL
HOld time, RAS referencad to C5E
Delay time. C5E to data
Delay time,
m
low to column address (see Note 10)
Delay time, column address to RA! high
Delay time, column address to xCAS high
teAL
Delay time. RAS low to xCAS low (see Note 10)
tRCD
NOTES: 6. All cycle times essume tr = 5 ns.
7. In a read-write cycle, tRWD and 1RWL must be observed.
8. Referencad to the later of XCA! or Win write operations
9. EIther tARH or tACH must be satisfied for a read cycle.
10. The maximum value Is specified only to aesure accese time.
5
15
15
30
30
45
~1ExAs
INSTRUMENTS
4-202
10
35
35
25
20
20
20
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
20
52
5
50
20
15
40
30
20
ne
40
80
na
ne
ne
ns
ns
ns
m~~~m~~~m~~~m~~~
TMS426169, TMS426169P, TMS428169, TMS428169P
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS888A- APRIL 1995 - REVISED JUNE 1996
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (continued)
'4xx169-60
'4xx169P-60
MIN
MAX
'4xx169-70
'4xxl69P -70
MIN
'4xxI69-60
'4xx169P -80
MAX
MIN
UNrr
MAX
tAPC
Delay time, RAS high to ~ low
0
0
0
lASH
Delay time, ~ low to ~ high
10
12
15
tRWD
Delay time, ~ low to W low (read-write operation only)
85
98
110
tcPW
lRASs
Delay time, W low after id5AS precharge (read-write operation only)
60
68
75
n8
100
100
100
I'll
tAPS
Pulse duration, RAS precharge after
Pulse duration, se"-refresh entry from RAS low
18"
110
refresh
130
'4x6169P
Aefresh time Interval
tr
Transition time
64
128
128
128
16
16
16
128
128
128
2
2
30
30
2
PARAMETER MEASUREMENT INFORMATION
Vee
VTH
Al
Output Under T e . t - . . - - - - -
Oiltflut Under Tnt
CL=I00pF
(_NoteA)
T
A2
CL"I00pF
(see Note A)
(b) ALTERNATE LOAD CIRCUIT
(a) LOAD CIACUrr
VCC(V)
Rt (Q)
R2(Q)
VTH (V)
41x169/P
5
828
295
1.31
218
42x169/P
3.3
1178
868
1.4
500
DEVICE
n8
64
'4x6169
'4x6169P
150
64
'4x6169
tAEF
na
na
na
AL(Q)
NOTE A: CL includes probe and fixture capacitance.
Figure 1. Load Circuits for TIming Parameters
-!I1TEXAS
INSTRUMENTS·
POST OFFICE BOX 1443 • HOUS'roN. TEXAS 77251-1443
30
m8
m8
n8
TMS416169, TMS416169P, TMS418169, TMS418169P
TMS426169, TMS426169P, TMS428169, TMS428169P
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS888A-APRIL 11195- REVISED JUNE 1l1li5
PARAMETER MEASUREMENT INFORMATION
"U
:a
o
c
c
~
Add .....
"U
:a
-:em~:
DQO-DQ15
NOTES: B. To hold the address latched by the first xCAS go/ng /ow, the parameter tcLCH must be met.
C. tcAc 18 measured from ~ to its corresponding 00x.
D. Output can go from the hlgh·lmpedance state to an Invalid-data stale prior to the specified access time.
E. XCM order Is arbitrary.
Figure 2. Read-Cycle Timing
~ThxAs
4-204
INSTRUMENTS
POST OFFICE BOX 10143 • HOUSTON. TEXAS 77251-10143
TMS416169, TMS416169P, TMS418169, TMS418169P
TMS426169, TMS426169P, TMS428169, TMS428169P
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS888A-APRIL 1995-REV!SEDJUNE 1995
PARAMETER MEASUREMENT INFORMATION
Add .....
VI
DQO-DQ111
NOTES: A. To hold the addreea latched by the first iCAS going low, the parameter tcLCH must be met.
B. Referenced to the first xCAS or W. whichever occurs last
C. XCAS order is arbitraly.
Figure 3. Write-Cycle Timing
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
4-205
TMS416169, TMS416t69P, TMS418169, TMS418169P
TMS426169, TMS426169P, TMS428169, TMS428169P
1048576-WORD.BY 16-81T EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886A- APRIL 1995- REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
I
NOTES: A. To hold the addreaa latched by the first ~ going
B. ~ order Is arbitrary.
row, the parameter tcLCH must be met.
Figure 4. Early-Wrlte·Cycle Timing
~1ExAs
4-206
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 1EXAS 77261-1443
TMS416169, TMS416169P, TMS418169, TMS418169P
TMS426169, TMS426169P, TMS428169, TMS428169P
1048576·WORD BY 16-BIT EXTENDED DATA OUT HIGH·SPEED DRAMS
SMt 2.
Rgure 3. Read Burst Interrupted by Read Command
nCCD .. 4 (even)
C~
1 +nDOD
InterruPtIng
WRTCommand
for Column Addrase Cl
(see Note A)
DOO-DQ3
DQM
___I
SaeNoteB
\_-------------------
NOTES: A. For the purposes of this example, read latency. 2 and burst length> 2.
B. OOM Is held high for2 C~cycles (2 rising edges). OOM Is held high fornDOD+ 1to mask out bit prior to Interrupting WRT command.
DaM Is held high for nDOD as specified spec.
Figure 4. Read Burst Interrupted by Write Command
~1ExAs
INSTRUMENTs
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
5-13
TMS626402
2Q97152-WORD BY.4-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS642A- FEBRUARY 1994- REVISED JUNE·1995
Interrupted bursts (continued)
14-- nCCD. 2 (even) - - + I
I
I
CLK
1 4 - - - nBSD. 2 - - - + !
READ Command
for Column AcId,... co
DO
(He
Note
...............
Interrupting
STOP Command
~
A)
CO
New Command
X CO+ )>--------------1
=
NOTE A: For this example, read latency 2 and burst length > 2-
Rgure 5. Read Burst Interrupted by STOP Command
14-- nCCD. 2 (even) - - + I
I
I
CLK
I
I
~1.-----n~.3------+I
ln18rruptlng
DEACIDCAB
Command
READ Command
for Column AcId,... CO
(... NoteA)
DQ
~
---------------------·~(~--C-O--)(~._C_O_+1__)~------------=
NOTE A: For this ex8rnple, read latency 3 and burst length> 2.
Figure 6. Read Burst Interrupted by DEAC Command
~TEXAS
5-14
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS626402
2097152-WORD BY 4-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS842A- FEBRUARY 1994 - REVISED JUNE 1995
Interrupted bursts (continued)
Table 8. Write-Burst Interruption
INTERRUPTING
COMMAND
EFFECT OR NOTE ON USE DURING WRITE BURST
OEAC,OCAB
The OEACIDCAB command immediately supersedes the write burst in progress. OQM must be used to mask the OQ
bus such that the write-recovery specification· (tRWLl is not violated by the Interrupt (see Figure 10).
WRT,WRT-P
The new WRT (WRT-P) command and data In Immediately supersede the write burst In progress (see Figure 8).
REAO, REAO-P
Oata In on previous cycle Is written. No further data input Is accepted (see Figure 7).
STOP
The data on the Input pins at the time of the burst STOP command Is not written, and no further data Is accepted. The
bank remalns active. A new read or write command cannot be entered for at least two cycles after the STOP command
(see Figure 9).
nCCD .2 (even)
CLK
I
I
I
I
I
I
WRTCommand
(sHNoteA)
READ Command
(see Note A)
I
I
<
DQO-DQ3
I
00-D3
X
DO-D3
<
>
I
QO-Q3
I
I
I
I
I
X
I
QO-Q3
NOTE A: For this example, read latancy • 2 and burst length > 2.
Figure 7. Write Burst Interrupted by Read Command
14-- nCCD. 2 (even) - - - - . ,
I
I
CLK
Interrupting
WRT-P Command
WRTCommsnd
for Column Address CO
(see Note A)
DQ
__CO__ X CO 1 X,,-__C1_--,X C1 1 X C1 2 X C1 3 »0------J
+
+
+
+
NOTE A: For this example, burst length> 2.
Figure 8. Write Burst Interrupted by Write Command
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • fIOUSTON, TEXAS 77261-1443
6-15
TMS626402
2097152·WORD BY 4-BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS842A- FEBRUARY 1884 - REVISED JUNE 1996
Interrupted bursts (continued)
I+-- nCeo. 2 (even) - - + I
I
I
CLK
WRTCommand
for Column AcId ..... CO
(aeeNottA)
~-----nBSD.2------~
InterruptIng
STOP Command
DQ
JX
__
CO
__
CO
New Write Command
X ~norecI X ~nored
+1
___
X~_--JX~_--JX
NOTE A: For tthls example, burst length> 2.
Figure 9. Write Burst Interrupted by STOP Command
nCCD.2(even)
CLK
I
WRTCommand
(aeeNottA)
I
DQO-DQ3
---c(
I
DO-D3
I
I
I
I
I
X ~7D3 X.--~ )>----........- - - - j4-
DQM
I
DEAC or DCAB Command
(_.. NottA)
tAWL
--tj
------------~/~,--.~~~~~~~~
=
=
NOTE A: For this example, read latency 2, burst length> 2, and tcK !AWL.
Figure 10. Write Burst Interrupted by DEAC/DCAB Command
power up
Device initialization should be performed after a power up to the full Vee level. After power is established, ,a
200-f.I.S interval Is required (with nD inputs other than ClK). After this Interval, both banks of the device must be
deactivated. Eight REFR commands must be performed, and the mode register must be set to complete the
device Initialization.
5-18
~I
TEXAS.
NSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS626402
2097152·WORD BY 4·BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS642A - FEBRUARY 1994 - REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)t
Supply voltage range, Vcc •..•.....••.••..••...••••.•....•.••.•.••.•.••..•.••••••• - 0.5 V to 4.6 V
Supply voltage range for output drivers, VCCQ ....................................... - 0.5 V to 4.6 V
Voltage range on any pin (see Note 1) .............................................. - 0.5 V to 4.6 V
Short-circuit output current ..••..•.•.......•.•..•..•......•.•.••.••.•.•..•..••••••.•••••••• 50 mA
Power dissipation ...••••.••••••.•..•••..•..•.•••.••••••••.•.•••.•••••.•••••..•••••••••••••• 1 W
Operating free-air temperature range, TA , ................... ,......................... O·C to 70·C
Storage temperature range, Tstg •.••••.••.•.•••.••.•..••,•..•••.••.••.•.••.••...•.• - 55·C to 150·C
t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These ere stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" Is not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values ere with· respect to VSS.
recommended operating conditions
Vee
Supply voltage
Veea
VSS
Supply voltage for output drivers
Supply voltage
Vssa
V,H
Supply voltage for output drivers
High-level Input voltage
VIL
TA
Low-levellnput voltage
MIN
3
NOM
3.3
MAX
3.8
3
3.3
3.8
0
0
2
-0.3
Operating free-alr temperature
0
Vee+ 0.3
0.8
70
UNIT
V
V
V
V
V
V
·C
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. 'TEXAS 77251-1443
5-17
'!'
to
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted)
(see Note 2)
PARAMETER
~t
~l'l1
~~
~1.
t
MIN
'626402-15
MAX
2.4
MIN
MAX
UNIT
VOL
Low-Ievel output voltage
IOL=2mA
0.4
0.4
0.4
V
II
Input current (leakage)
o V" VI" Vcc + 0.3 V,
All other pins = 0 V to Vcc
:10
:10
:10
10
Output current Oeakage)
o V" VO" VCC + 0.3 V,
Output disabled
:10
:10
:10
fAA
fAA
70
Average read or write current
2.4
IOH=-2mA
90
80
110
100
90
Burst length = 1 or 2
150
120
100
Burst length = 4 or 8
170
140
130
16
16
16
ICC2
Standby current
CKE=VIL
2
2
2
CKE = 0 V (CMOS)
1
1
1
One or both
banks
CKE=VIL
6
6
6
90
80
70
2 banks active
interleaving
See N0Ie3
Consecutive CBR commands
tRC=MIN
~
1CC4
Ieee
Burst current, gapless burst
SeIf-refresh current
A~ not allowed,
tcK=MIN,
2-bank interleaved
Read latency = 1
70
80
50
Read latency = 2
100
90
80
Read latency = 3
140
120
100
CKE=VIL
2
2
2
CKE = 0 V (CMOS)
1
1
1
i°..;..~
1%01 0)
... :UNoI=Io
>O:u
:!!C::C
iien m
"'C-<
~-<
~Z~
(j»>m
mS:::o_~
mA
eOm
iIi:u-< '
o;»N
ll:Z •
C~
Oz
lilA
i:"
~
o
active
Icca
o-<~i:
o
mo:e
~ZON
V
Burst length = 1 or 2
IRC=MIN,
tcK=MIN,
Read latency = 3
Both banks
deactivated
2.4
Burst length = 4 or 8
CKE=VIH,
~
~~i"'-
'626402-12
MAX
VOH
ICC1
:rt::
MIN
High-level output vottage
1 bank active
~-~
'626402-10
TEST cONomONS
~enN ~
cnZ ..... en
m
en
mA
(/)
i:
m
i:
mA
o
~
mA
NOTES: 2. All specifications apply to the device alter power-up initialization.
3. AD control and address inputs must be stable and valid.
"
TMS626402
2097152·WORD BY 4·BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS842A- FEBRUARY 1994 - REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 4)
MIN
CI{AC)
Input capacitance, CLK
Inputcepacitance, AO-A11 , 08, OOM, RAS, CAS, W
CI/E}
Input cepacitance, CKE
Co
Output cepacitance
CI{S)
MAX
7
5
5
8
UNT
pF
pF
pF
pF
NOTE 4: Vee. 3.3 :I: 0.3 V and biaa on plna under test la 0 V.
ac timing recnllrements over recommended ranges of supply voltage and operating free·alr
temperature tl
'626402-10
MIN
MAX
Read latency .. 1
teK
=
Cycle time, CLK (system clock)
Read latency 2
Read latency .. 3
10
'626402-15
MIN
MIN
i
,
Pulse duration, CLK (system clock) high
3
3.5
teKL
Pulse duration, ClK (system clock) low
3
3.5
tAC
toH
U
tHZ
tos
tAS
tes
Access time, ClK t to data out
(see Note 5)
=
Read latency 2
Read latency. 3
Hold time, CLK t to data out
Delay time, CLK to DO In the low-Impedance state
(see NoteS)
MAX
40
20
15
4
4
12
teKH
Read latency = 1
MAX
3S
18
30
15
'626402-12
29
33
14
9
15
10
UNIT
ns
na
na
38
18
12
ns
3
3
3
ns
0
0
0
na
Read latency .. 1
Delay time, ClK to DO in the
Read latency. 2
high-Impedance atate (aee Note 7)
Read latency. 3
20
12
9
20
13
20
14
10
11
na
Satup time, data In
2
2
2
Setup time, addreaa
2
2
2
lIS
Setup time, control Input CCS, RAS, CAS, W, OOM)
2
2
2
na
Setup time, CKE (suspend entry/exit, power-down entry)
teES
teESP Satuptlme, CKE (power-down/aeH-refresh exit) (see Note 8)
Hold time, data In
tDH
Hold time, addreaa
tAH
Hold time, control input (08, RAS, CAS, W, DOM)
teH
na
2
2
2
na
8
10
12
ns
2
3
4
lIS
2
3
3
4
4
ns
2
lIS
Hold time, CKE
2
3
4
ns
REFR command to ACTV, MRS, REFR or SLFR command;
ACTV command to ACTV, MRS, REFR or SLFR command;
100
110
125
lIS
tRC
SeH-refresh exit to ACTV, MRS, REFR or SlFR command
t See Paramater Meaaurement Information for load circUits
All referencaa era made to the rising transition of CLK, unleaa otherwise noted.
NOTES: 5. lAc Is referenced from the rising transition of CLK that la previous to the data-out cycle. For example, the first data-out lAC la
referenced from the rising transition of CLK that Is read latency -1 cycles after the READ command. An acceaa time Is meaaured
at output reference level 1.4 V.
6. U Is measured from the rising transition of ClK that Is read latency - 1 cycles after the READ command.
7. 1Hz (max) defines the time at which the outputs era no longer driven and Is not referenced to output voltage levels.
8. HteESP > teK, NOOP or DESl commands must be entered until teESP Is mat. CLK must be active and stable (H CLK waa turned
ofl for power down) before CKE Is retumed high.
teEH
*
~1EXAS
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON, lEXAS 77251-1443
5-19
TMS626402
2097152..WORD BY 4-BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS842A- FEBRUARY 1994 - REVISED JUNE 1995
ac timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (contlnued)t:a:
'826402-10
'826402-12
'826402-18
MIN
MIN
MAX
MIN
MAX
70
100000
100000
MAX
100000
tRAS
Ar::rv command to DEAC or DCAB command
60
tAco
Ar::rv command to READ or WRT command
30
-, 35
80
40
tRP
DEAC or DCAB command to Ar::rv, MRS, SL.FR,
or REFR command
40
40
45
tAPR
Final data out of READ·P operation to Ar::rv,
MRS, SL.FR, or REFR command
Final data In of WRT·P Burst length. 1
operation to Ar::rv, MRS,
SL.FR, or REFR command
Burst length> 1
(see Note 10)
1 clock+60
tAPW
Final data In to DEAC or Burst length =1
DCAB command
Burst length> 1
(see Note 11)
1 clock+20
tRWL
tRRD
Ar::rv command forons bank to Ar::rv command
for the other bank
nl
ns
1 clock+75
ns
60
75
60
1 clock+20
1 clock+30
ns
20
20
30
20
25
30
Transition time, all Inputs (see Note 9)
5
1
1
Refresh Interval
64
tREF
t See Parameter Measurament Information for load circuits
All references are made to the rising tranlltlon of CLK, unleSl otherwise noted.
NOTES: 9. Transition time, tr, 18 measured between VIH and VIL.
10. for BL-10nly
SPEED
-10, -12. tAPW is 60 na from first unsuspended clock adge after last data In
-15 • tAPW is 80 ns from first unsuspended clock edge after last data In
11. forBL .. 10nly
SPEED
-10, -12. tAwL 18 20 ns from first unsuspended clock edge after last data In
-15 • tRWL is 30 ns from first unsuspended clock edge after last data In
tr
*
~1ExAs
5-20
nl
nl
tAp + (nEP Ie teK>
1 clock+60
UNIT
.
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON~ lEXAS 77251-1443
5
64
1
ns
5
64
ns
ml
TMS626402
2097152·WORD BY 4-BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS842A- FEBRUARY 1894 - REVISED JUNE 1885
clock timing requirements over recommended ranges of supply voltage and operating fr....lr
temperature t
'628402·10
'626402·12
'628402·16
MIN
MIN
MIN
=
Burst length 1, Read latency =1
Burst length. 1, Read latency. 2
nEP
nHZP
1
0
Final dete out to OEAC or Burst length .. 1. Read latency .. 3
OCAB command
Burst length> 1. Read latency. 1
-1
Burst length> 1. Read latency =2
-1
-2
Burst length> 1. Read latency .. 3
OEAC or OCAB Interrupt of Read latency .. 1
dete out burst to 00 In the
Read latency .. 2
high-impedance etete
Read latency .. 3
(see Note 12)
MAX
0
MAX
MAX
UNrrt
1
1
0
-1
-1
0
-1
-2
-1
-2
cycIee
0
0
1
1
1
2
2
2
3
3
3
cycles
cycles
nCCD
READ or WRT command to Interrupting STOP, READ. WRT. DEAC. or
OCAB command Q=1. 2. 3•... ) (see Note 13)
21
21
21
cycles
nOWL
Final dete In to READ or WRT Burst length. 1
command In either bank
Burst length> 1
2
1
2
1
2
1
cycIee
nWCO
WRT command to first dete In
0
0
0
0
0
0
nOlO
ENBL or MASK command to dete In
0
0
0
0
0
0
cycles
nOOO
ENBL or MASK command to data out
2
2
2
2
2
2
cycIee
nCLE
HOLD command to suspendad CLK edge;
HOLD operation exit to entry of any command
1
1
1
1
1
1
cycles
nRSA
MRS command to ACTV, REFR. SLFR. or MRS commend
2
neoo
OESL command to control input Inhibit
0
0
0
0
0
0
cycIee
nBSD
STOP command to READ or WRT command
2
.. of CLK. unless otherwISe noted.
t All references are made to the rlalng transition
2
2
cycles
cycles
2
2
cycIee
cyc/ee
*
.
A CLK cycle can be considered as contributing to a timing requirement for thoseparamaters defined In cycle units only when not gated by CKE
(those CLK cycles occurring during the time when CKE Is asserted low).
NOTES: 12. A data-out burst 'can be Interrupted only on an even number of clock cyclee after the Initial READ command Is entered (refer to
nCCD).
13. A read or writs burst can be Interrupted only at an even number of clock cyclee after entry of the Initial READ or WRT command.
The nceO paramater Is only required In the case of a burst Interruption.
~ThxAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS Tl2l51-1443
5-21
TMS626402·10
tcK
Operating frequency
100
Cycle time, CLK (system clock)
10
80
1 12
33
80
15
20
30
12
I~
~c
2
3
2
2
cycles
4
3
6
4
3
cycIee
3
2
2
4
3
2
cycles
10
8
6
4
9
7
5
cycles
2
3
3
2
2
3
3
2
cycles
1
1
2
2
1
1
2
2
1
cycles
1
1
3
2
2
1
2
2
1
cycles
-
3
-
-
-
-
-
cycles
2
-
-
2
3
2
cycles
1
3
2
1
cycles
3
3
2
ACTV command to DEAC or DCAB command
6
5
4
lAp
DEAC or DCAB command to ACTV, MRS, SLFR, or REFR command
4
4
lAC
REFR command to ACTV, MRS, SLFR, or REFR command; self-refresh exit
to ACTV, MRS, SLFR, or REFR command
10
Rnal data in to DEAC or DCAB Burst length =1
Burst length > 1
ACTV command for one bank to ACTV command for the other bank
Burst length .. 1, Read latency
Burst length .. 1, Read latency
Flnal data in of WRT-P operation to
ACTV, MRS, SLFR, or Rem
command
lIS
2
ACTV command to READ or WRT command
tRAS
IAPW
30
cycles
lAeo
~f~
MHz
2
2
Final data out of READ-P operation to
ACTV, MRS, SLFR, or REFR
command
UNrr
33
2
2
tAPR
t~~
30
66150
15 1 20
3
3
!-~
TMS626402-15
33
2
3
lARD
66 50
15 1 20
Burst length
=1
=2
=1, Read latency .. 3
=1
Burst length > 1, Read latency
Burst length > 1, Read latency
=2
Burst length > 1, Read latency
=3
Burst length
=1
Burst length > 1
------ ----
--
1
3
3
2
2
1
3
3
3
2
6
5
3
2
2
4
9
7
5
4
3
3
3
2
2
2
2
2
2
2
-
-
-
- 3 2
2
1
3
3
- - - -
2
1
- 3
2
1
-
-
- - - 2 1
cycles
O::!c:n
::c en I\)
iII':U1\)
"'O~
::uZ
oc:;
~O.O
~C:U
-en C
!C9!
1~ ..
!l!» •
ffl3l:!!!
0_-1
~Om
~:u-<
-»1\)
Iz·
C~
Oz
i:~
oj:.
o
o
m
-
-
2
1
1
-
1
1
2
2
1
0
0
2
1
0
0
2
1
0
i:ycIes
m
7
6
5
4
3
6
5
4
3
6
5
4
cycles
o
6
5
4
3
2
5
4
3
2
5
4
3
cycles
2
-
-
-I
i:
; zCDen
0-<0
NUMBER OF CYCLES REQUIRED
Read latency, minimum programmed value
IRwL command
TMS6264CJ2.12
66 50
KEY PARAMETER
~
~cnl\)
Table 9. Number of Cycles Required to Meet Minimum Specification for Key nmlng Parameters
~
cycles
en
en
i:
i:
~
§
TMS626402
2097152·WORD BY 4·BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS642A- FEBRUARY 1994 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
general Information for ae timing measurements
The ac timing measurements are based on signal rise and fall times equal to 1 ns (tT = 1 ns) and a midpoint
reference level of 1.4 V for LVTTL For signal rise and fall times greater than 1 ns, the reference level should
be changed to VIH min and VIL max instead ofthe midpoint level. All specifications referring to READ commands
are also valid for READ-P commands unless otherwise noted. All specifications referring to WRT commands
are also valid for WRT-P commands unless otherwise noted. All specifications referring to consecutive
commands are specified as consecutive commands for the same bank unless otherwise noted.
-1
1.4V
output
Under Teat
I
_
3.3 V
RL-SOOQ
Output
Under Teat
R2=B68Q
CL=SOpF
(..eNoleA)
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL Includ.. probe and fixture capacitance.
Figure 11. Load Circuits
nEP
eLK
II
DEAC/DCAB
Command
1Hz
DQO-DQ3
I
I
I
I
14
~
X ~_)>---
___x__---'x''__---JX
FInal Output of Buret : /
=
NOTE A: For this example...sume read latency 3 and burst length> 1.
Figure 12. nEP, Final Data Output to DEAC or DCAB Command
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
5-23
TMS626402
2097152;.WORD BY 4-BIT BY2-BANK .
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SM0S842A- FEBRUARY 1994;' REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
J4
R.ad Latency
~
I
CLK
I
.h
. L\..h
.r-\
~H ~~ .. '-'i .'-iH ' ACw
READ
lAc i4
~ I
I
I
I I
~
i
i
4 Il...t-toH
I
Command
Command
tHZ
ILZ
DQO-DQ3_~~!
}-
Figure 13. Output Parameters
ACTV
14
tRAS
~ DEAC, DCAB
ACTV
~
IRCD
~
READ, WRT
14
lAp
~ ACTV, MRS, REFR, SLFR
REFR
14
tRC
~ ACTV, MRS, REFR, SLFR
ACTV
~
lAc
~
~
tRC
~ ACTV, MRS, REFR, SLFR
DEAC, DCAB
I
SeIf-Rafre8h ExIt
I
ACTV
14
MRS
~
"'RD
...
See Note A
nRSA
READ, WRT
~
nCCD
I
--¥- nCDD
DESL
Command
Dissble
I
I
I
.
ACTY, MRS, REFR, SLFR
I
~ ACTV (of a dlfferenl bank)
~
ACTV,
R~FR, SLFR, MRS
~ STOP, READ, WRT, DEAC, DCAB
I
I
I
I
CLK~~
NOTE A: lARD Is specified for command execution in one bankto command execution In the other bank.
Figure 14. Command-to-Command Parameters
~1ExAs
5-24
INSTRUMENTS
POST OFFICE ~ 14<13 • HOUSTON. TEXAS 77251-14<13
TMS626402
2097152-WORD BY 4-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS842A- FEBRUARY 1994 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
teKH
J4- teK--.j
~
,
,
,,
I"
CLK
I
I
I
~
IiIII
toS. tAS. teS. teES
I
,
.~-ItlIM-,, ,
,
IiIII
~,
J!..JI.,.......- - - -....
teS. teES. teESP
\L
---r-!
....!
,
toH. tAH. teH. teEH
I
1
tos. tAS.
IT~ 14-
~
i4
,
'-.I
II
IteKL~
~-~Q3.AO-A11.CS,RAS.
.
CAS. W. DQM. CKE
toH.
tNt. teH. teEH
DQO-DQ3, AD-A11. CS. RAS.
'\ 'CAl. W. DQM. CKE
'
14- IT
Figure 15. Input-Attribute Parameters
14-,
Read Latency • 2
(..eNotaA)
!.-ICLK
,
DQO-DQ3
,
nDOD
(tor MASK)
,,
,
II
,
,
(
I
I
ENBL~ommand ~
,
14- tRWL
I
I
~
I
I
,
1
DQM
,
nDOD
(for ENBL)
I '!.-
READ Command
---.I
:
QO-Q3
'I'
--J"'
,
,tDS
) ',
WRTCommand
,
IiIII
~
I
l
"--:""-X
('
00-D3
.
I -:/
1
I,
1
!/I~
toH'
I
I
,
. Igno1red)
.)-.-
1-
....,
,
1
MASK Command
I
I
I
DEAC/DCAB
Command
"
}4.1
~
,
/
~
=
NOTE A: For this example, assume read latency =2 and burst length 2.
Figure 16. OQ Masking
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. l1!XAS 77261-1443
6-25
TMS626402
2097152·WORD BY 4·BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RAND.OM·ACCESS MEMORY
SMOS642A- FEBRUARY 1994- REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
14-ClK
Read Latency. 2
(a88 Note
A)
I
I
I
----'I
I
I
READ-P Command
DQO-DQ3
I
I
I
I
I
I
<
I
I
I
I
I
I
QO-Q3
~
tAPR
~
ACTV Command
X
QO-Q3·
I
I
I
)
I
I
NOTE A: For this example, -assume read latency = 2 and burst length .. 2.
Figure 17. Read·Automatlc Deactivate (Autoprecharge)
14------
tAPW -------tl~
--'J~
ClK
ACTV Command
WRT·P Command
DQO-DQ3
--<
I
I
I
I
DO-D3
I
I
I
I
I
X(':,;o':A) )>-------------+-I---:--
NOTE A: For this example, the burst length .. 2.
Figure 18. Wrlte·Automatlc Deactivate (Autoprecharge)
-!!1
5-26
TEXAS .
I NSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77261-1443
TMS626402
2097152·WORD BY 4·BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS642A- FEBRUARY 1994 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
14- nCLE-ti
14- nCLE-ti
I
I
I
I
CLK
DOO-DQS
--< ~QO X
r--*"I
QO-Q3_!~-_~"NO
I
~
teES
C~
~
~~
-
)>-----teES
II~--------
__________________~I~-------J
',S
Figure 19. eLK-Suspend Operation
CLK Is Don't care for This Interval --I4------.t
No READ (READ·p) or
WRT(WRT-P)
In Progr••• ' ) .
CLK
1411111-,"*- teES
I
C~
CLK Must Be Actlv. and Stabl.
Before Returning C~ High
teESP
,,'-__________________~~I~~--------J
Figure 20. Power-Down Operation
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
5-27
TMS626402
2097152·WORD BY 4-BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SM.OS842A- F.EBRUARY 1884 - REVISED JUNE 1.895
PARAMETER MEASUREMENT INFORMATION
14- IRc
I
CLK Ia Don't Care - - I f - - - - - - a I
for Thlalntarval
teEH
CLK Must Be ActIve and
Stable Before Retumlnll
-r41--+l~1
I
~
ACTV, MRS, or
REFR
Command
I
CKE High
te9P
J
II
~~~~-I
r
I
I
------~~________~;,~\-------------------'){r.----~;~~----~!---PJ-
CKE
I
I'-T.
I
CLK
SLFR Command
-.j
teES
NOTE A: Assume both banks are previously deectlvated.
Figure 21. Self-Refresh Entry/EXlt
nCCD • 4 (even)
nHZP...--otl!
j4- nCWL--I
CLK~:
FInal Input 01
WrJta Buret
' I
-
DQO-D03
I
I
DEAC/DCAB
Command
I
READ
Command
I
1--------«
~,,,,,\...
00-03
X
00-03
X,....I:..-~X
00-03
NOTE A: Assume read latency. 2 and burst length • 8.
Figure 22. Write Burst Followed by DEAC/DCAB-Interrupted Read
~TEXAS
6-28
INSTRUMENTS
POST 0FF1CE BOX 1443 • HOUSTON. TEXAS 77251-1443
QO-03
»-~--
Ac:rYT
READT
DEACT
CLK
DQO-DQ3
DaM
RAS
~
~-
...
I
I
jf~
·
t~d
~~
i.!.
I
~
'
'
\...J
\.i../
,
~
w
I
~ ~"if
--------------------------------------------~~~------
A10
Al1
,
\...J
~-'~-
~~.-~
Aa-A9
cs
I
t
CKE
BURST
~~~
W
-
I
~
::u
en
»tn
Z
0
::u
0
Z
0
a:
m
c:
m
a:
m
Z
~
Z
-<
:::c
::u
ct/)
C
~
-0"
0 m
1,m-
BURST CYCLE
ROW
(D/O)
(BIT)
ADDR
a
b
c
d
Q
T
RO
cot
CO+1
CO+2
CO+3
t CoIumlHlddress sequence depends on programmed burst type and CO (seeTabIe 5).
NOTE A: This example Hlustrates minimum IRCD and nEP for the '626402-10 at 100 MHz, the '626402-12 at 80 MHz. and the '626402-15 at 66 MHz.
Figure 23_ Read Burst (read latency
~
~
jlIe::u
OIoe
BANK
TYPE
-
,
\..J
_~
=3, burst length =4)
lit/)
-t
~t/)m
-t
ens:: -< s::
I!JmN t/)
~s::m~
~o»~
-:UZCS
I-<~N
Ar:rvT
,
~
men I'» """
DEACT
,
WRTT
,
3I:-<~:s::::
iz
. . . en
CLK
~Cl ... ~
I
IDO:e O
DQ3
DQM
,
~j.
o
RAS
',
\if
,
',,
\..U
~
'I
CAS
I
W
~~. . I
A10
t~d
~ ~~
~mG;
I
A11
~~
lAO-At
~
I
!!l
V·
-
-CS
.!.
t
CKE
BURST
\JJ
~
&
~~:.~
~~
&
W
~C;!!
a;en-
~a~
~-<: .110.
!1;!Z.
(j);>m
~
i
ROW
(DfQ)
(BIT)
ADDR
0
T
RO
BURST CYCLE
•
cot
b
c
d
CO+1
CO+2
CO+3
•
CO+4
f
9
h
CO+5
CO+6
CO+7
-
t ColumlHlddl9Sll sequence depends on programmed burst type and CO (see Table 6).
NOTE A; This example IIustiates minimum lRwL for the '626402-10 at 100 MHz, the '626402-12 at 80 MHz, and the '626402-15 at 66 MHz.
Figure 24. Write Burst (burst length
=8)
2l!;=i
EClm
iil::u-<
a;» I'»
IIIZm
C»
~:II Oz
:s::::'"
i:
~
Cl
ic:
::u
m
m
m
en
en
z
-I
:s::::
m
:s::::
Z
~
i:
(g
::u
i:
oz~
BANK
TYPE
JlZOI'»
Co
~
.
I
Xcn en
jR::Q ~ oIlo
000-
o
WRTB
Ac:rvB
READB
DEACB
CLK
DQO-DQ3
DaM
~
HAS
-----~
~
\..J'
CAS
~
~
Vi
z...,
0 _....
~
ilr
A10
A11
~
)'l
\i./
mm~
~mm~mm~
AO-A9
CS~
~
~
~
CKEW
1.
£
BURST
TYPE
(DfQ)
0
mm
.~
BANK
ROW
(BIT)
B
B
ADDR
RO
RO
BURST CYCLE
•
cot
b
c
d
CO+1
Cft:
*
Figure 25. Write-Read Burst (read latency = 3, burst length = 2)
~
~
::D
i:
~
C
::D
~
o
X
:u
i:
m
oZ
oc:
-t
_
C
m
z
Z
"TI
o::D
en
-
g
~
c:
:D
;m i==
.
CSBB.:~
BURST
TYPE
i:
m
~:z:!:S
~O""'I\)
I$~i!
WRT-PT
DQO-
-I
=3, burst length =8)
:!:i
Z
21:D
==
!i
(5
z
~
o
~
Ac:rvB
READ-PB
Ac:rvT
READ-PT
Ac:rvB
READ-PB
Ac:rvT
CLK
DQODQ3
I
•
DOlI
-
~
-
..
w------~------------------------~~--------~--------------~--------~
J
i~
~
....
~~~
i~i
~-
~~
~
.!.
C
rn
CKEy---:-
::u
a::
~------------~--------------------------------------------------------------------------------------~~~
::u
p
q
!2
BURST BANK
ROW
(D/Q)
(BIT)
ADDR
•
Q
Q
Q
B
T
B
RO
R1
R2
oot
~E
BURST CYCLE
bed
•
f
I
h
k
m
n
r.
0
00+1 00+2 00+1 00+4 00+5 00+& 00+7
C1*
Ch1 Ch2 ChI C1+4 C1+5 C1+& Ch7
C2I C2+1 C2+2 ... ...
:!irn_
~~----------~------------------------------------------------------------------------~
Z
t CoIumn-addrass sequence depends on programmed burst type and CO (see Table 6).
"11
*
=
:x:
:u
oz
o
c:
en
~
z!\)
g
>~
a:: fI)!&'"
CoIumn-addrass sequence depends on programmed burst type and C1 ( _ Table 6).
I CoIumn-adclrass sequence depends on programmed burst type and C2 ( - Table 6).
NOTE A:. lbis example illustrates minimum fReD for the '626402-10 at 100 MHz, the '626402-12 at 80 MHz, and the '626402-15 at 66 MHz.
Figure 'D. lWo-Bank Row-lnterleavlng Read Bursts With Automatic DeactIvate (read latency 3, burst length
~
(')
:J:II!
=8)
~(')fa
6 ~~=e
""t
~ZO
z :lC:U
mOC
~a::::
...
~:i><
-(')f"
I(')m
Im~
~=m-l
fl)a::::-:
i~~2
~
ACT'B
R~B
ACT'T
R~B
READT
DQM_
R~T
rhenN -I
~Z!S en
R~B
;;:eC)m
~ ~~~
a:
m Iz'
cm
iii::a O~
a::~
a: oJ>
!:en
em
::a en
m en
a: a::
m m
z
-t
BURST
z
BANK
ROW
(DfQ)
(BIT)
ADDR
Q
T
B
RO
Rl
TYPE
D
BURST CYCLE
•
cot
b
c:
d
CO+l
CO+2
CO+3
•
f
Cl*
Cl + 1
9
h
C1 +2- Cl +3
2J
::a
a:
!t
6
z
t CoIumn-addreSs sequence depends on programmed burst type and CO (see Table 5).
*NOTE
CoIumn-address sequence depends on programmed burst type and C1 (see Table 5).
A: Thlsexample Hlustrates minimum lRCD for the '626402-10 at 100 MHz, the '626402-12 at 80 MHz, and the '626402-15 at 66 MHz.
Rgure 34. Use of CKE for Clock Gating (Hold) and Standby Mode (read-burst bank T with hold, wrlte-burst bank B, standby mode)
(read latency = 2, burst length 4)
=
C)
C)
a::
0
~
TMS626802
1048576-WORD BY 8·BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
• Organization ••• 1M x 8 x 2 Banks
• 3.3N Power Supply (~10% Tolerance)
DGEPACKAGE
(TOP VIEW)
• lWo Banks for On-Chip Interleaving
(Gapless Accesses)
• High Bandwidth - Up to 100-MHz Data
Rates
• Burst Length Programmable to 1, 2, 4, or 8
• Programmable Output Sequence - Serial or
Interleave
• Chip Select and Clock Enable for
Enhanced-System Interfacing
• Cycle-by-Cycle DQ-Bus Mask Capability
• Programmable Read Latency From Column
Addre..
•
•
•
•
•
•
VCC
oa7
VSSQ
Oa1
DaB
VCCQ
VCCQ
oa2 8
oa4
VCCQ
NC
NC
'828802-10
'828802-12
'828802-15
10 na
12.5 ns
15 ns
30 na
35 na
40na
IREF
(MAl<)
84 ms
84 ms
84 ms
description
The TMS626802 series are high-speed
16777216-bit synchronous dynamiC randomaccess memories (DRAMs) organized as two
banks of 1 048576 words with eight bits per word.
All inputs and outputs of the TMS626802 series
are compatible with the low-voltage TIL (lVTTL)
interface.
The synchronous DRAM employs state-of-the-art
enhanced performance implanted CMOS
(EPIC"') technology for high performance,
reliability, and low power. All inputs and outputs
are synchronized with the ClK Input to sImplify
system design and enhance use with high-speed
microprocessors and caches.
W
oaM
cAs
CLK
RAS
SYNCHRONOUS COMMAND 10 REFRESH
CLOCK CYCLE READ OR WRITE
nME
nME
COMMAND
INTERVAL
IRCD
(MIN)
oa5
Vssa
• Performance Ranges:
tcK
VSS
VSSQ
Self-Refresh Cap-ability
High-Speed, low-Noise LVITL Interface
Power-Down Mode
Compatible With JEDEC Standards
4K Refresh (Total for Both Banks)
2-Blt Prefetch Architecture for High Speed
Performance
(MIN)
1
oao
CKE
~
NC
A11
A10
AS
AS
AO
A7
A1
AS
A2
A5
AS
A4
VCC
VSS
PIN NOMENCLATURE
AO-A10
Address Inputs
AO-A10 Row Addresses
AO-A8 Column Addresses
A10 Automatlc-Precharge Select
A11
Bank Select
CAS
Column-Address Strobe
CKE
Clock Enable
ClK
System Clock
Chip Select
OOO-DQ7 SDRAM Data Input/Data Output
Data/Output Mask Enable
DQM
No Extemal Connect
NC
Row-Address Strobe
RAS
Power Supply (3.3 V Typ)
Power Supply for Output Drivers (3.3 V Typ)
VCCQ
Ground
Ground for Output Drivers
~Q
W
Write Enable
cs
Vee
Vss
The TMS626802 synchronous DRAM is available in a 40Q-mil, 44-pin surface-mount TSOP (II) package (DGE
suffix).
EPIC Is a trademark of Texas Instruments InCOrporated.
-!/} 1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
Copyright 0 1995. Texas InatrumenIB Incorporated
5-41
TMS626802
1048576-WORD BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS182A- FEBRUARY 1994"- REVISED JUNE 1996
operation
All inputs of the '626802 synchronous DRAM are latched on the rising edge of the system (synchronous) clock.
The outputs, DQO-DQ7, are also referenced to the rising edge of CLK The '626802 has two banks that are
accessed independently. A bank must be activated before it can be accessed (read from or written to). Refresh
cycles refresh both banks alternately.
Five basic commands or functions control most operations of the '626802:
•
•
•
•
•
•
Bank activate/row-address entry
Column-address entry/write operation
Column-address entry/read operation
Bank deactivate
CAS-before-RAS (CBR)
Self-refresh entry ,
Additionally, operation can be controlled by three methods: using chip select (CS) to select/deselect the
devices, using DQM to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or
gate) the eLK input. The device contains a mode register that must be programmed for proper operation.
Tables 1 through 3 show the various operations that are available on the '626802. These truth tables identify
the command and/or operations and their respective mnemonics. Each truth table is followed by a legend that
explains the abbreviated symbols. An access operation refers to' any READ (READ-P) or WRT (WRT-P)
command in progress at cycle n. Access operations include the cycle upon which the READ (READ-P) orWRT
(WRT-P) command is entered and ail subsequent cycles through the completion of the access burst.
functional block diagram
CLK
Array BankT
CKE
cs----"'--+-t
DQM-----------.~
DQ
-----------11. .
RAS
CAS -----------.....
Buffar
ijj--"'----+-t
AD-A11--..,..----t-t
Array Bank B
12
~1ExAs
INSTRUMENTS
POST'OFFIOE BOX 1443 • HOUSlON, TEXAS 77251-1443
DQO-DQ7
8
TMS626802
1048576-WORD BY 8·BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS182A- FEBRUARY 1994 - REVISED JUNE 1895
operation (continued)
Table 1. Basic-Command Truth Tablet
COMMAND
STATE OF
CS
RAS
CAS
Vi
A11
A10
L
L
L
L
X
X
L
L
L
H
H
L
BS
L
L
H
L
BS
BS
H
V
L
X
X
DEAC
H
H
L
X
V
V
Ar:rv
SB =actv
.L
L
L
L
BANK(S)
AI-AO
MNEMONIC
AI-X
Mode register set
Bank deactivate (precharge)
Deactivate all banks
T=deac
B-deac
X
X
AS.O
A7.0
AS-NJ.V
MRS
DCAB
Bank actIvete/row-address entry
Column-address entry/write operation
Column-address entry/write operation
with automatic deactivate
SB-deac
SB .. actv
L
Ii
L
L
BS
H
V
WRT-P
Column-address entry tread operation
SB. actv
L
H
L
H
BS
L
V
READ
CoIumn-address entry/read operation
with automatic deactivate
SB. actv
L
H
L
H
BS
H
V
READ-P
SB .. actv
L
H
H
L
X
X
L
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
NOOP
DESL
Burst stop
No operation
Control-Input Inhibit / no operation
WRT
STOP
T=B.
H
REFR
L
X
X
CBR refresh*
L
L
X
deac
t For execution of these commands on cycle n. CKE (n) must be high and satisfy teESP from power-down exit (POE). teES and nCLE from
clock-suspend (HOLD) exit, and tcESP and lAc from self-refresh (SLFR) exit. DaM (n) Is a don't care.
* CBR or aeIf-refrash entry requires that all banks be deactivated or In an idle state prior to the command entry.
Legend:
L
.. logic low
H
• logic high
X
• Don'tcare
V
T
.. Valid
.. BankT
B
-
BankB
actv .. ActIvated
deac .. Deactivated
BS
• logic high to select bank 1: logic low to select bank B
SB
.. Bank selected by A11 at cycle n
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS626802
1048576-WORD BY 8·BIT BY.2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS182A- FEBRUARY 1994- REVISED JUNE 1995
operation (continued)
Table 2. CKE·Use Command Truth Tablet
COMMAND
Self-refresh 8ntry
Power-down entry at n + 1
STATE OF BANK(S)
CKE
(n-1)
CKE
(n)
T-B-deac
H
T-B-no
access operatlon*
H
H
L
L
L
L·
H
L
L
H
Self-refresh exit
T • B • self refresh
Power-down exH
T .. B .. power down
eLK suspend at n+1
Tor B .. access
operatlon*
cs
CAS
VI
(n)
(n)
(n)
RAS
(n)
L
L
L
L
H
H
H
H
H
X
X
X
H
H
H
H
L
H
X
X
X
H
X
X
X
X
-
L
X
X
X
X
HOLD
=
MNEMONIC
SLFR
POE
POE
-
-
Tor B access
H
X
X
X
X
L
operatlon*
t For execution of these commands, AO-A11 (n) and DaM (n) are don't cares.
* An access operation refers to any READ (READ-P) orWRT (WRT-p) command In progress at cycle n. Access operations Include the cycle upon
which the READ (READ-P) or WRT (WRT-P) command Is entered and all subsequent cycles through the completion of the acceis burst.
Legend:
n
.. eLK cycle number
L
• Logic low
H
• logic high
X
• Don'tcare
T
• BankT
B
.. BankB
deac • Deactivated
eLK suspend exit at n +1
~1ExAs
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON. TEXAS 77261-1443
-
TMS626802
1048576-WORDBY 8-BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOSl82A- FEBRUARY 1994- REVISED JUNE 1995
operation (continued)
Table 3. DQM·Use Command Truth Tablet .
COMMAND
-
Data-ln enable
STATE OF
BANK{S)
T-deac
and
B=deac
T-actv
and
B=actv
(no access operation)*
T -write
or
DOM
(n)
DATA IN
(n)
DATA OUT
(n+2)
MNEMONIC
·X
N/A
HI-Z
-
X
N/A
HI-Z
-
L
V
N/A
ENBL
H
M
N/A
MASK
L
N/A
V
ENBL
B .. write
T.write
Data-lnmask
or
B. write
T .. read
Data-out enable
or
B. read
T. read
HI-Z
MASK
or
H
N/A
B-read
t For execution of these commanda, CKE (n) must be high and satisfy te~from power-down exit (POE), teES and nCLE from cIock-auspend
(HOLD) exit, and teESP and tRC from self-refreSh (SLFR) exit. ~ (n), RAS (n), ~ (n), VI (n), and AO-All (n) are don't cares.
* An access operation refers to any READ (READ-P) orWRT (WRT-P) command In progress at cycle n. Acoase operations Include the cycle upon
which the READ (READ-P) or WRT (WRT-P) command Is entered and all subsequent cycles through the completion of the access burst
Legend:
n
.. CLK cycle number
L
.. Loglclow
H
.. logic high
X
.. Don'tcare
V
.. Valid
M
.. Masked Input data
N IA .. Not applicable
T
.. BankT
B
.. BankB
actv .. Activated
deac .. Deactivated
write .. Activated and accepting data In on cycle n
read • ActIvated and delivering data out on cycle n + 2
Data-out mask
~ThxAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS621802
1048576-WORD BY 8-BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOSl82A- FEBRUARY 1994- REVISED JUNE 1896
burst sequence
All data for the '626802 is written or read in a burst fashion; that is, a single starting address is entered into the
device and the '626802 internally accesses a sequence of locations based on that starting address. Some of
the subsequent accesses after the first can be at preceding as well as succeeding column' addresses,
depending on the starting address entered. This sequence can be programmed to follow either a serial burst
or an interleave burst (see Tables 4 through 6). The length of the burst sequence can be user programmed to
be either 1, 2, 4, or 8 accesses. After a read burst is completed (as determined by the programmed·burst length),
the outputs are in the high-impedance stete until the next read access is initiated.
Table 4. 2-Blt Burst Sequences
INTERNAL COLUMN ADDRESS AO
DECIMAL
BINARY
START
2ND
START
2ND
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
SerJaJ
Interleave
Table 5. 4-Blt Burst Sequences
INTERNAL COLUMN ADDRESS A1-AO
DECIMAL
Serial
Interleave
BINARY
START
2ND
3RD
4TH
START
2ND
3RD
0
1
2
3
0
1
2
3
1
2
3
0
1
0
3
2
2
3
0
1
2
3
2
1
0
00
01
10
10
11
00
01
10
11
00
01
3
0
1
2
3
0
1
01
10
11
00
01
10
11
11
00
01
00
11
10
4TH
11
00
01
10
11
10
01
00
Subiequent Read or WrIte CMD tOr BL • 1
CLK
CAS,
II
I
I
I,
\
/
II
\
/
Minimum of1Wo Cyel..
\
I
I
,I
\
/
\\--..,/
'-
NOTE: For burst sequence ofona. subaequent reed or write commands must be done at ISasttWo clock cycles from initial read or write command
(_ timing diagram above).
~1ExAs~
INSTRUMENTS
POST OFFICE BOX 144$ • HOUSlON. 'IE 2.
Figure 2. Read Burst Interrupted by Read Command
nCCD
=4 (even)
CLK
1 4 - - - - nDOD - - -...
1+nDOD
,
Interrupting
WRTCommand
for Column Addreaa C1
(..eNoteA)
DQO-DQ3
DQM
__--'I
See Note e
\~------------------
NOTES: A. For this example, read latency =2 and burst length> 2.
B. DaM is held high for2 CLKcycJes (2 rising edges). DaM is held high for nOOO+ 110 mesk out bitpriorlo interrupting WRT command.
DaM is held high for nOOO as specified.
Figure 3. Read Burst Interrupted by Write Command
-!!11EXAS
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON. TEXAS 77251-1443
5-51
TMS626802
1048576-WORD BY 8-BIT BY 2·BANK .
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS182A- FEBRUARY 1994 - REVISED JUNE 1995
Interrupted bursts (continued)
14--- nCCD •
I
I
2 (even) - - - . t
CLK
~-----nnD.2------~
READ Command
fot Column Acldre..
DQ
CO --.. . .
~.
(see Note A)
New Command·
Interrupting
STOP Command
CO X
CO+1
)>-_____________
NOTE A: For this example, read latency. 2 and burst length> 2.
Figure 4. Read Burst Interrupted by STOP Command
I4---nCCD.2 (even)
--~
I
I
CLK
I
I
~14~---------N~.3----------~
READ Command
for Column AcId,...
(see NOIeA)
DQ
CO
Interrupting
DEAC/DCAB
Command
----......
-------------------~~<~--CO--~X~__ )~----------CO_+1_ _
NOTE A: For this example, read latency .. 3 and burst length> 2.
Figure 5. Read Burst Interrupted by DEAC Command
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS626802
1048576·WORD BY 8-BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS182A- FEBRUARY 1894 - REVISED JUNE 1996
Interrupted bursts (continued)
Table 8. Wrlte·Burst Interruption
INTERRUPTING COMMAND
EFFECT OR NOTE ON USE DURING WRITE BURST
DEAC,DCAB
The DEAC/DCABcommand Immediately supersedes the write burst In progress. DQM must be used to mask
the DQ bus such that the write recovery specification ~RWL) Is not violated by the
Interrupt (see Figure 10).
WRT, WRT·P
The new WRT (WRT·P) command and data In Immediately supersede the write burst In progress
(see FIgure 8).
READ, READ-P
Data In on previous cycle Is written. No further data In Is accepted (see FIgure 7).
STOP
The data on the Input pins at the time of the burst STOP command Is not written, and no further data Is
acospted. The bank remains active. A new read or write command cannot be entered for at least two cycles
after the STOP command (see Figure 9).
nCCD • 2 (even)
CLK
I
WRT Command
(see Note AI
I
I
DQO-DQ7
I
-----«
X
00-07
READ Command
(SH Note AI
00-07
)>------------«
QO-Q7
X
QO-Q7
=
NOTE A: For this example, read latency 2 and burst length> 2.
Figure 6. Write Burst Interrupted by Read Command
I+-- nCCD • 2 (even) - - - . !
I
I
CLK
Interrupting
WRT-P Command
WRTCommand
for Column Addresa CO
(see Note AI
DQ
X
__CO
_ _. . J
CM
X,-__ X
Cl_--J
Cl+l
X
Cl+2
X
NOTE A: For this example, burst length> 2.
Figure 7. Write Burst Interrupted by Write Command
~ThxAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 'TeXAS 77251-1443
C1+3
)>-----
TMS6268Q2
.
1048576-WORD BY 8-BIT BY ~-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOSl82A- FEBRUARY 1994 - REVISED JUNE 1995
Interrupted bursts (continued)
14-- nCCD. 2 (avan) - - + I
I
I
CLK
WRTCommand
for Column AcId..... CO
14-----nBSD. 2 ---~
(8HNoteA)
New Write Command
Interrupting
STDP Command
DQ
-,X
__
CO
__
X
CO+1
X
Ignored
Ignored
X"--_----'X"--_----'X'-__
NOTE A: For this example. burst length> 2.
Figure 8. Write Burst Interrupted by STOP Command
nCCD • 2 (avan)
CLK
I
WRTCommand
(He Nota A)
I
I
DQO-DQ7
I
I
I
I
~D7
I
DEAC or DCAB Command
(_HNotaA)
I
X ..~ )>-----....------
j4-lRWL ~
DQM
--------------~/---~~~~~~~·~~
NOTE A: For this example. reed latency. 2. burst length> 2. and tcK" tRWl.
Figure 9. Write Burst Interrupted by DEAC/DCAB Command
power up
Device Initialization should be performed after a power up to the full Vee level. After power Is established. a
20Q-tJS interval is required (with no inputs other than ClK). After this interval. both banks of the device must be
deactivated. Eight REFR commands must be performed. and the mode register must be set to complete the
device initialization.
~1ExAs
INSTRUMENTS
P08TOFFICE BOX 1443· HOUSTON. TEXAS Tn51-1443
TMS626802
1048576·WORD BY B-BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOSI82A- FEBRUARY 1984 - REVISED JUNE 1996
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)t
Supply voltage range, Vcc ........................................................ - 0.5 V to 4.6 V
Supply voltage range for output drivers, VCCQ ••••••••••••••••••••••••••••••••••••••• - 0.5 V to 4.6 V
Voltage range on any pin (see Note 1) •••••.•••••••.••.••••••••••••••.••••.••.•••••• - 0.5 V to 4.6 V
Short-circuit output current .•••..•..••.•....•..•••..•••••••.•....•..•.•....•.••.•..•.••.•.. 50 rnA
Power dissipation ••.••.•••••••.•••••••••••••••••.•.••••••••••••••••••••.••••••••••••••••••• 1 W
Operating free-air temperature range, TA .............................................. O"C to 70"C
Storage temperature range, Tstg •..••••.••.•.•..•.••.••••••••••••••.••.••••.•••••. - SS"C to 150"C
t Stresses beyond those listed under "absolute maximum ratings" may causa permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" Is not
Implied. Exposure to absolute·maxlmum·rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
3
3.3
3.8
Vcca
Supply voltage for output drivers
3
3.3
3.8
VSS
Supply voltage
Vssa
VIH
Hlgh·level input voltage
2
VIL
Low·levellnput voltage
-0.3
TA
Operating free-alr temperature
0
0
~/~
~1ExAs·
I
NSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
V
V
V
0
Supply voltage for output drivers
UNrr
V
Vcc + 0.3
0.8
70
V
V
·C
~
PARAMETER
VOH
High-level output voltage
TEST CONDmONS
L.CJw.IeveI output voltage
IOL=2rnA
II
Input current (leakage)
10
Output current (leakage)
o V ",VI "'VCC + 0.3 V,
oV "'Vo '" Vcc·+ O.S V,
All other pins
=0 V to Vcc
Output disabled
1 bank active
...
f~"If
Average read or write current
II!
~
s
MIN
MAX
Burst length = 1 or 2
'626802-15
~
2.4
MIN
MAX
2.4
UNIT
ii!O=e
~ZON
V
0.4
0.4
0.4
V
tl0
:1;10
tl0
pA
tl0
tl0
tl0
pA
90
80
70
~g::D
-en C
!C~
~~cp
~»m
m3:-
Burst length " 4 or 8
110
100
90
Burst length " 1 or 2
150
120
100
interleaving
Burst length
=4 or 8
170
140
130
~::D-<
16
16
16
CKE"VIL
2
2
2
Iz ·
CKE = 0 V (CMOS)
1
1
1
CKE=VIL
6
6
6
90
80
70
Read latency = 1
70
80
50
Read latency = 2
100
90
80
Read latency = S
140
120
100
CKE=VIL
2
2
2
CKE = 0 V (CMOS)
1
1
1
Both banks
cIeacIIvated
IcQ
'626802-12
MIN
~-<2 a::
2 banks active
tcK-MIN,
tRC=MIN,
Read latency .. 3
CKE=VIH.
~
'626802-10
2.4
IoH=-2mA
VOL
ICC1
~
~-
men .... -«
~ZCD en
~ncn ~
I::z:
..... ~
::DO)
electrical characteristics over recommended ranges of supply voltage and free-alr temperature (unless otherwise noted)
(see Note 2)
Slandby current
Oneorbolh
banks
SeeNoteS
0_-«
rnA
Enm
-»N
8;
3:,.;:
mA
~m
active
Ices
Consecutive CBR commands
tRC=MIN
Icc.
Burst current, gapless burst
ACfV not allowed,
2 bank interl8lMld
Ices
Self-lefresh current
tcK"MIN,
NOTES: 2. All specifications apply to the device after Power-up initialization.
S. All control and address inputs must be stable and vaBd.
mA
en
en
mA
m
3:
a::
o
mA
-
I
~
TMS626802
1048576-WORD BY 8·BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS182A- FEBRUARY 1994 - REVISED JUNE 1995
capacltanc. ov.r recomm.nd.d rang.s of supply voltag. and op.ratlng fr....lr t.mp.ratur.,
= 1 MHz (s•• Not. 4)
f
MIN
MAX
UNT
Cies)
Input capacitance, CLK
7
pF
CI(AC)
Input capacitance, AO-A11 , CS, DQM, RAS, CAS, W
pF
CitEl
Input capacitance, CKE
Output capecltance
5
5
8
Co
pF
pF
NOTE 4: Vee. 3.3 * 0.3 V end bias on pins under test Is 0 V.
BC timing requlr.ments ov.r r.comm.nd.d ranges of supply voltage and operating free·alr
t.mp.rature U
Read latency. 1
teK
Cycle time, CLK (system clock)
Reed latency .. 2
Reed latency .. 3
'626802-10
MIN
MAX
30
15
10
teKH
Pulse duration, CLK (system clock) high
3
teKL
Pulse duration, CLK (system clock) low
3
tAo
Access time, CLK t to data out
(_NoteS)
Read latency .. 1
Read latency. 2
Read latency .. 3
tLZ
Delay time, CLK to DQ In the low-Impedance state
(_Note6j
1HZ
Reed latency. 1
Delay time, CLK to DQ In the
Read latency .. 2
high-Impedance state (see Note 7)
Read latency = 3
'626802-12
MIN
MAX
'626802-15
MIN
MAX
38
40
18
20
12
15
4
3.5
3.5
ns
ns
ns
4
29
14
33
15
38
18
9
10
12
0
ns
ns
0
0
UNIT
20
20
20
12
13
14
9
10
11
ns
Setup time, data input
2
2
2
tcs
Setup time, address
Setup time, control input (CS, RAS, CAS, W, DQM)
2
2
2
2
teES
Setup time, CKE (suspend entry I exit, power-down entry)
2
2
2
2
2
ns
ns
teESP
Setup time, CKE (power down lself-refresh exit) (see Note 8)
8
10
12
ns
Hold time, CLK t to data out
3
2
2
3
4
ns
ns
teH
Hold time, data Input
Hold time, AO-Al0
Hold time, control Input (CS, RAS, CAS, W, DQM)
teEH
Hold time, CKE
2
3
3
3
3
3
tDS
tAS
toH
tDH.
tAH
2
ns
ns
.
ns
,4
ns
4
ns
REFR command to ACTV, MRS, REFR or SLFR command;
ACTV command to ACTV, MRS, REFR or SLFR commend;
100
110
125
ns
IRc
Self-refresh exit to ACTV, MRS, REFR or SlFR command
t See Parameter Measurement Information for load circuits.
All re1erences are made to the rising transition of CLK, unless otherwise noted.
NOTES: 5. lAc Is re1erenced from the rising transition of CLK thet Is previous to the data-out cycle. For example, the first data out tAo is
re1eranced from the rising transition of CLK that is reed latency -1 cycles after the READ command. An access time is measured
at output re1erence level 1.4 V.
8. ILZ is meesured from the rising transition of CLK that is read lataney - 1 cycles after the READ command.
7. 1HZ (max) defines the time at which the outputs are no longer driven and is not re1erenced to output voltage levels.
8. If teESP > teK, NOOP or DESl commands must be entered until teESP Is meL ClK must be active end stable (If CLKwas tumed
off for power down) before CKE is retumed high.
*
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON, TEXAS 772t51-1443
5-57
TMS626802
1048576-WORD BY 8-BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS1B2A- FEBRUARY 1994 - REVISED JUNE 1995
ac tIming requirements over recommended ranges of supply voltage and operating fre....lr
temperatureU
'626802-10
'626802-12
MIN
MAX
MIN
MAX
100000
70
100000
'626802-15
MIN
MAX
tRAS
ACTV command to DEAQ or DCAB command
60
tRCD
ACTV oommand to READ or WRT oommand
30
35
40
ns
tRP
DEAC or DCAB command toACTV, MRS, SLFR,
or REFR command
40
40
45
nl
W>R
Final data out of READ-P operation to ACTV,
MRS, SLFR, or REFR command
tAPW
Final data in of WRT-P
operation to ACTV, MRS,
SLFR, or REFR command
(see Note 10)
Burst length =1
60
100000
UNIT
tAp + (nEP .. teKl
1 clock+BO
ns
ns
1 clock+60
1 clock+75
ns
Burst length> 1
tRWL
Final data in to DEAC or Burst length. 1
DCAB command
Burst length> 1
(lee Note 11)
tRRD
ACTV command for one banktoACTV oommand
for the other bank
60
1 clock+2O
60
75
1 clock+30
1 cIock+2O
nl
20
20
30
20
25
30
1
Transition time, all Inputs (see Note 9)
1
5
Refresh Interval
64
tREF
t See Parameter Measurement Information for load circuits.
AU referances are made to the rising transition of CLK, unless otherwise noted.
NOTES: 9. Transition time, IT, Is measured between VIH and VIL.
10. for BL-10nly
SPEED
-10, -12 .. tAPW Is 60 ns from first unsuspended clock edge after last data In
-15 -1APw Is 60 nstrom first unsuspended clock edge after last data In
11. for BL = 1 only
SPEED
-10, -12 .. tRWL Is 20 ns trom first unsuspended clock edge after last data In
-15 • tRwL Is 30 ns trom first unsuspended clock edge after last data In
IT
*
~1ExAs
INSTRUMENTS
P(lIT OFFICE lOX 1443 • HOUSTON. TEXAS 712&1-1443
5
64
1
nl
5
64
ns
ml
TMS626802
1048576·WORD BY 8·BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOSI 82A- FEBRUARY 1994 - REVISED JUNE 1995
clock timing requirements over recommended ranges of supply voltage and operating free-air
temperature t
nHZP
nCCD
'826802·12
'826802·15
MIN
MIN
MIN
MAX
MAX
=1, Read latency .. 1
1
1
1
Burst length = 1, Read latency =2
0
-1
0
0
-1
-1
Burst length
nEP
'826802·10
Final data out to DEAC or Burst length =1, Read latency .. 3
DCAB command
Burst length> 1, Read latency. 1
0
0
Burst length> 1, Read latency =2
-1
-1
0
-1
Burst length> 1, Read latency. 3
-2
-2
-2
DEAC or DCAB interrupt of Read latency. 1
data-out burst to 00 in the
Read latency =2
high-impedance state
Read latency. 3
(see Note 10)
READ or WRT command to interrupting STOP, READ, WRT, DEAC, or
DCAB command 0" 1,2,3, ••• ) (see Note 11)
MAX
UNIrt
cycles
cycles
1
1
1
2
2
2
3
3
3
2i
2i
2i
cycles
2
cycles
1
cycles
nCWL
Final data in to READ or WRT Burst length =1
command in either bank
Burst length> 1
2
2
1
1
nWCD
WRT command to first data in
0
0
0
0
0
0
nOlO
ENBL or MASK command to data in
0
0'
0
0
0
0
cycles
nOOD
ENBL or MASK command to data out
2
2
2
2
2
2
cycles
nCLE
HOLD command to suspended CLK edge;
HOLD operation exit to entry of any command
1
1
1
1
1
1
cycles
0
0
0
0
nRSA
MRS command to ACTV, REFR, SLFR, or MRS command
2
nCDD
DESL comman~ to control input inhibit
0
2
cycles
cycles
cycles
2
cycles
nBSD STOP command to READ or WRT command
cycles
2
2
2
t All references are made to the rising transition of CLK, unless otherwise noted.
A CLK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gatad by CKE
(those CLK cycles occurring during the time when CKE is asserted low).
NOTES: 12. A data-out burst can be interrupted only on an even number of clock cycles after the Initial READ command Is entered (refer to
nCCD).
.
13. A read or write burst can be Interrupted only at an even number of clock cycles after entry of the Initial READ or WRT command.
The nCCD parameter is only required in the case of a burst interruption.
*
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
0
Table 9. Number of Cycles Required to Meet Minimum Specification for Key Timing Parameters
~
TMS626802·10
Operating frequency
tcK
~ time,
100
10
CLK (system clock)
I
I
80
12
I 66 I 50 I 33
15
20 1 30
KEY PARAMETER
~
.
'~
i~t
2~~
;~
~
TMS626802-12
80
12
TMS626802-15
66150133
15 120 I 30
NUMBER OF CYCLES REQUIRED
2'
1
3
3
2
3
Read latency; minimum programmed value
3
3
2
2
tAco
ACJrV command to READ or WRT command
3
3
2
2
1
3
3
1RAs
ACJrV command to OEAC or DCAB command
8
5
4
3
2
tAp
OEAC or DCAB command to ACJrV, MRS, SLFR, or REFR command
4
4
3
2
2
8
4
tAc
REFRcommandtoACJrV,MRS,orREFRcommand;self-refreshexittoACJrV,
MRS, SLFR, or REFR command
10
9
7
5
4
3
3
3
2
1RWL
FIII8I data it to OEAC
or DCAB command
2
2
2
1
tARO
ACJrV command for one bank to ACJrV command for the other bank
2
2
2
1
1
3
2
2
-
-
- -
3
-
-
-
2
2
-
-
2
2
3
3
1
1
3
2
1
1
-
- - -
2
-
-
-
-
Burst length
=1
Burst length >_1
=1, Read latency =1
Burst length =1, ~ead latency =2
Burst length =1, Read latency =3
Burst length > 1, Read latency =1
Burst length > 1, Read latency =2
Burst length > 1, Read latency =3
Burst length =1
Burst length
W>R
fAPW
FIIl8I data out of READ-P operation to
Ac::fV, MRS, SLFR, or REFR
command
Fmal data in of WRT-P operation to
ACJrV, MRS, SLFR, or REFR
Burst length > 1
command
,
!1l
.!.
!
-
-
r-
66150
15
20
UNRS
33
MHz
30
lIS
l~i5
f~~~
':":U9» G)
IIlO:E2
~ZO
2
2
- cycles
2
2
cycles
~g:u
"en C
!C~
2
2
3
5
4
.3
8
4
3
cycles
3
2
2
3
3
2
cycles
10
8
8
4
9
7
5
cycles
1Y!5=i
2
3
3
2
2
3
3
2
cycles
ifi:u-<
~»
1
2
2
1
1
2
2
1
cycles
IZ •
1
2
2
1
cycles
~- 1•.
Figure 11. nEP, Final Data Output to DEAC or DCAB Command
~.1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
5-81
TMS626802
1048576-WORD BY 8-BIT BY 2·BANK
SYNCHRONOUS DYNAMIC .RANDOM·ACCESS MEMORY
SMOS182A- FEBRUARY 1994 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
fill .
~
Read Latency
I
I
I
I
.
CLK~~~~
ACw .
Command
READ
Command
I
lAC
u-IHI
I
I
.
.~ I
14.
I
I
I
I
I I
·1Hz ~
II
I
I
I ~toH
DQO-DQ7~~~~
)-
FIgure 12. Output Parameter.
ACTV
~14----
IRAS -----.t~ DEAC, DCAB
ACTV
~~----
IRCD
---~~
READ, WRT
IRP
---~~ ACTV, MRS, REFR, SLFR
REFR
I4lRc
---~~ ·ACTY, MRS, REFR, SLFR
ACTV
~
IRc
---~~
ACTY, MRS, REFR, SLFR
Self-Refnlsh ExIt
-----J!~
ACTY, MRS, REFR, SLFR
l1li
DEAC, DCAB
I
~
tRC
ACTV
~he____
'-RD
MRS
.~.......,.----
1"'1
READ, WRT
-.I.i---I
-¥nCDD
DESL
Command
Disable
CLK
...
I
SseNoteA
N ACTV (of a different bank)
...
nRSA
-----...~
nCCD
-----..~ STOP, READ, WRT, DEAC, DCAB
I
I
ACTY, REFR, SLFR, MRS
I
I
I
I
~r------T\-
NOTE A: tARO Iaspecified forcommand execution In one bank to command execution In the other bank.
Figure 13. Command-to-Command Parameters
i
-!I1TEXAS
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON, ~ 77251-1443
TMS626802
1048576-WORD BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS182A- FEBRUARY 1994 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
If-teK~
teKH~
II
II
I
CLK
I
I
I 1-.1
IteKL-Hi
J
14
los. lAs. tes. teES
--..to1\
I
tr ~
~
I
,.
I
,
I,
~-~.AO-A11.a.RAi.
"r--l"'",",,
tDs.lAs. teS. teES. teESP 14
IoH. Wt. teH. teEH
.
,
j.-
II
.tr -tI ~
CAS. W. DaM. CKE
IoH. lAH. teH. teEH
I
~,
Jt-i',,.....---~\.' DOG-DQ7. AO-A". a. JIiAI.
J!
"CAl. W. DaM. CKE
,
....!
14- tr
Figure 14. Input-Attribute Parameters
' - - Rnd Latency. 2
CLK
I
(... NoteA)
!.--I-
nOOD
(for ENBL)
I
I
DaM
I
!.-I"
I
II
I
I
I
I
I
I
I
I
I
I
I
\4-1RwL
~
I
READ Command
oaO-DQ7
--tI
I
(for~~
<
ENBL~ommand ~
I
I
I
I
I
I los -II1II141---"1
~ IoHI
:
I
I
X
Y II
00-a7)
I
~~~
I
I I
(DO-07
I,
!/I~
NOTE A: For this example. assume read latency • 2 and burst length oj 2.
Figure 15. DQ Masking
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUS'ICN. TEXAS 772&1-1443
/
I
I
I
I
WRT Co~mand
nOOD
~
I
I
Ignored
DEAC/DCAB
Command
'I
)"'---1I
,
I,
~
TMS626802
1048576-WORD BY ~BIT BY 2..BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS182A- FEBRUARY 1994 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
IfCLK
I
I
I
~..d Latency. 2
(..a Note A)
~
I
I
I
I
I
I
I
I
~EAD-P Command
I
DQO-DQ7
-~------«
QO-Q7
+------
~p~
~
~~
ACTV Command
x
)~------------~--------
QO-Q7
NO~ A: For this example, assume read latencY • 2 end burst length. 2.
Figura 18. Raad-AutomatlcDaactlvata (Autopracharga)
~----- tAPW
~
--~~
CLK
ACTV Command
WRT·P Command
NOTE A: For this example, the burst length • 2.
Figura 17. Wrlta-AutomaUc DeacUvata (Autoprecharge)
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lECAB 77251-1443
TMS626802
1048576·WORD BY 8·BIT BY 2·BANK
SYNCHRONOUS DYNAMIC RANDOM·ACCESS MEMORY
SMOS182A- FEBRUARY 1994 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
*- nCLE-to!
*- nCLE-to!
I
I
I
I
I
I
I
I
I
I
CLK
DOO-DQ7
-< "~Q7 X,__Q_O_-_Q7__
~,~,. fln_._1
(a_
••_u_m...
I
~
d_ata_ou_tp_u_t_of_b_Urat)....,:_..J)>------
I
~
teES
teES
C~ ~'__ _ _ _ _ _ _ _ _~~I,..j----J)tr-------Figure 18. CLK--Suspend Operation
ClK .. MDon't care" for This Interval --liIII4f------ti
I
I
I
I
No READ (REAO-p) or
WRT (WRT-P)
In Progrees ~
CLK
I11114'----MI
C~
teES
CLK Must Be Active and Stable
Before Returning C~ High
~'--.------
~,',. j
_ _ _...
teESP
~
____
Figure 19. Power-Down Operation
-!!11EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
5-85
TMS626802
104857~WORD BY 8-B11 BY 2,-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS182A- FEBRUARY 1994 _ .REVlSED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
14I
IRC -.j
I
I~
CLK
I
CLK Must.Se Active and
Stabla Before Returning
CKEHlgh
SLFR Commanil
teEH
CKE
I
I
-I4-tot~1
.
~~- - -....~Ij-
teESP
ACTV, MRS, or
REFR \
Command
I
I
I
I
~~_~~
I
teES
1
----~~~______~~,~j----------------~){~--~S'S~---+!--
NOTE A: Assume both banks are previously deactlvated.
Figure 20. Self-Refresh Entry/ExIt
j4-
~.~--nHzp - -...
nCCD • 4 (Evan)
nCWL--I
CLK~:
Flnallnpulof
Wrlta Sum """\.
~
I
I
I
READ
Command
I
I
.
-11------«
DQO-DQ7-8S--s~'j
00-07
X
DEACIDCAB
Command
I
__
I _'"\
00-07
X
00-07
X
NOTE'A: Assume read latency. 2 and burst length. 8.
Figure 21. Write Burst Followed by DEAC/DCAB-Interrupted Read
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
QO-07
>......-'--
ACTVT
READT
DEACT
CLK
DQO-DQ7
DaM
----------------------------------------------~~-------.
~
I
~
~
o_~
~~ ~
t
d
i~~
i~
i
.!.
A10
A11
I
I
.
..
w
I
\....J
\..i..I
CAS
I
.~
\J...J
RAS
\J../
:--
~-------==~~~~~~~~
~
~.:-~:.-:
. . .
. . .
.
CS
t
CKE
i
~
::u
;:
~
Z
ic: :0
::u o
n
:c
m
Z
oc
;:
zm
_
AO-A9
I
J
en
c
-t
~~-~
rtf
z
~ .....
~
»2
::u
".. CD
;:
cn:=
CII
.... !l:n
......
-:0::
-- g
::!
en
oz e»o
IZ
"c:o
BURST
BANK
ROW
(DfQ)
(BIT)
ADDR
Q
T
RO
TYPE
BURST CYCLE
•
cot
b
c
d
CO+1
CO+2
CO+3
t CoIumn-address sequence depends on programmed burst type and CO (seeTabIe 5).
NOTE A:. This example Ulustrates minimum lRco and nEP for fie '626802-10 at 100 MHz. the '626802-12 at 80 MHz. and the '626802-15 at 66 MHz.
=
=
Rgure 22. Read Burst (read latency 3, burst length 4)
~
llIoc
:us:
§;i.~
-nfP
!nm
Im:uen""
~enm -t
cn"..< s:
l!l::llo N en
.. m. en
c3:mN
ifio»
en
-:uz~
I<"N
;
fl>en..a. -f
~~ii:
~nCII !
CLK
(
0
RAS
...
i~r
!-~
~~
;~
iJ.
l
~
\if
V
CAS
\i/-----------------~
w
~
&
A10~
. . _ _.:~
A11~··~:
AO-AS
&
~.
CKEW
~
!: Enm
l> ifi:u-<
a: ii»~
rn IliZm
....0»
rn
Oz
:D
a:
~
tn
c
:D
m
a:
m
....
z
~
:D
a:
!i(5
BANK
ROW
(0/0)
(BIT)
ADDR
0
T
RO
TYPE
z
BURST CYCLE
•
cot
b
c
d
CO+1
CO+2
CO+3
•
CO+4
f
9
h
I,
CO+5
CO+6
CO+7
I
t CoIumn-address sequence depends on programmed burst type and CO (seeTabIe 5).
NOTE A: This example illustrates minimum 1RwL. for the '626802-10 at 100 MHz. the '626802-12 at 60 MHz. and the '626802-15 at 66 MHz.
Figure 23. Write Burst (burst length
=8)
~g:D
-en
!_m
1::(-<
:DZI!III
!2_
•.
Cii-m
I!l!!:=i
°
z
cs2§§a
BURST
1
m0=e
i!!ZO
1% 0»
......
jlJ:xJ
.
DQM~~
DQO-DQ7
i::;:II\
•
l=;
n
m
en
en
i:
m
i:
0
~
Ar:rvB
. WRTB
READB
DEACB
CLK
DQO-DQ7
(
\....J
RAS
,
\j./
W
~-~
A10~
I~:r~~~
J
~
CAS
~
\...J
,
\j./
~~
A11~~~~~
;~
cs~~~~~
.!.
&
eKE
BURST
TYPE
(DIQ)
W
BANK
ROW
(BIT)
ADDR
BURST CYCLE
~
c:
:D
z
z
""
o
•
c
b
~o
:r:
~
2
oc:
_
-I
en
C
I
22
»5
en!;cn
-< ....
~
3:0 .....
(5
Z
il>o~
,2
~:D~
iIIC:D
mOC
d
.-
*
Figure 24. Wrlte-Read Burst (read latency
;
!!!:
....
cot CO+1
B
RO
Q
B
RO
C1+1
C1*
-------t CoIumn-address sequence depends on programmed burst type and CO (see Table 4).
CoIumn-address sequence depends on programmed burst type and C1 (see Table 4).
NOTE A: ThIs example Ilustrates minimum IRCI) for Ihe '626802-10 at 100 MHz, Ihe '626802-12 at 80 MHz, and Ihe '626802-15 at 68 MHz.
0
~:D
!im2
AD-AS
i
I
=3, burst length =2)
~!!:m
~:i>-<
-om
0 m
1,m-
iIIenooot
:senm ooot
en!!: -< i!!:
I!Jm~
(I)
Ei:m~
iiOl>1
i~~~
READT
ACTVT
~
CLK
a
DQO-DQ7
DQII~
~,
~~~
CAS
-en
!_m
0
AO-A9
CS~
~m~
~~
i
.!.
£
iihnhnihi"ihi".
_ _ '~
I
Jinniinnninnn""""""""""""""
iU
TYPE
BANK
ROW
~
i:
(BIT)
ADDR
a
b
c
d
Q
T
T
RO
RO
cot
CO+1
CO+2
CO+3
•
CO+4
f
9
h
CO+5
CO+6
CO+7
I
C1*
k
I
C1+1
I
C1+2 C1+3
m
C1+4
n
C1+5
t CoIumn-address sequence depends on programmed burst type and CO (seeTable 6).
*
CoIumn-address sequence depends 01\ programmed burst type and C1 (see Table 6).
NOTE A: This example Ulustrates minimum tRco for the '826802-10 at 100 MHz. the '826802-12 at 80 MHz, and the '626802-15 at 88 MHz.
Figure 25. Read-Write Burst With Automatic Deactivate (read latency
=3, burst length =8)
0
p
C1+8
,
C1+7
!l!» •
fii~!!
0 _ ....
E(')m
~::a<
iD»~
~
IIlZ •
i:
l;
~
C
BURST CYCLE
(D/O)
0
J
:II
CKE ~
BURST
'::«
:Uze»
~r-----------------
A11~:~:~··~
~
~zo
~g:ll
A10~:~,~
s
mO=:2
Am
~
W
!I:
men ...... ....
~-
\.:.....J
Vi
Al0
~
All
~
AO-A9
g
~z~
~CJ)~
~·~mJ
~~~
~mr;;
~~
~.!.
S
~
rI
m
BURST
BANK
ROW
s::
(D/Q)
(BIT)
ADDR
RO
Rl
R2
CKE
TYPE
Q
Q
Q
B
T
B
:xJ
I
BURST CYCLE
8
cot
b
c
d
e
g
h
k
m
n
o
p
q
8
~
c:
:xJ
CO+l CO+2 CO+3 CO+4 CO+5 CO+6 CO+7
Cft Cl + 1 C1+2 Cl +3 C1 +4 C1+5 C1 +6 C1+ 7
C2§ C2+1 C2+2 .
t Column-address sequence depends on programmed burst type and CO (see Table 6).
t Column-address sequence depends on programmed burst type and C1
(see Table 6).
§ Column-address sequence depends on programmed burst type and C2 (see Table 6).
NOTE A:. This example illustrates minimum tRCD for the '626802-10 at 100 MHz, the '626802-12 at 80 MHz, and the '626802-15 at 66 MHz.
Figure 26. Two-Bank Row-Interleaving Read Bursts With Automatic Deactivate (read latency
=3, burst length =8)
m
s::
m
z
-t
Z
~
:xJ
~o
:c
::0
o
Z
o
c:
en
o
-<
....
Zo
l>~
(/):5: g:
s::
;::0 ......
oz
tz,o
!4
~::o CD
C;;l>:e
"0::0
III 0 0
i!!:5: m
Si:i>
-<
~OC»
"'0
•
fmm
I
JJen-t
~enm
1b :5:
-t
-< :5:
(gm N en
2:5:
mfa
~Ol>CD
~
-::ozc»
~-<~2
~
R~B
AC'!VT
AC1VB
R~B
READT
R~T
0fn ..... -I
R~B
~-<2 a:::
!!!Zo; fn
CLK
~nUl~
l:x ...... 0)
DQO-DQ7
DQM
HAS
"II::D tp
-
~0::D
_~c
'-.U
!c~
'-U
~-< qc»
~~m
ma:::-
0_-1
~ Enm
CAS
w
~
1:1-.,.
~~~
A10~~~~~~
~
~ ~r;;I
g~~
A11
Il#lltl#ltI
~
/#lltI
.~
~
/#lltI
~
~
AO-A9
~l'I1Gi
i~
cs
i
CKE
~:~: ~~. ~: ~: ~: ~: B»
W'
-,-- ---
--,
~
Iz'
i:
a::: "
1>
~
:u
BANK
(D/Q)
(BIT)
ADDR
Q
Q
Q
B
RO
R1
RO
T
B
...
...
•
cot
b
c
d
C1*
C1 + 1
CO+1
•
f
C2§
C2+1
...
...
z
-t
i:
Z
...
. ..
z
-
*t
CoIumn-eddress sequence depends on programmed burst type and CO (see Table 4).
CoIumn-eddress seql.KlllC§ depends on programmed burst type and C1 (see Table 4).
§ CoIumn-address sequence depends on programmed burst type and C2 (see Table 4).
Rgure 27. lWo-Bank Column·lnterleavlng Read Bursts (read latency
=3, burst length =2)
c~
Oz
g
c:
:u
m
i:
m
~
6
BURST CYCLE
~::D<
-»~
5
i:
ROW
TYPE
~
2J
:u
1.
BURST
!!!
m0=ei\S
jgZO
m
en
fn
!!!:
m
o
~
ACfVT
READB
ACfVB
DEACB
WRTT
DEACT
CLK
DQU_'
DQO-
DQ7
,
\..J
HAS
t
I
~
i~~~-g~
~"'
~~
i
a
.!.
Vi
I
'-J
\..U
I
I
~
i_
A10~
A11
\....:...J
'-J:
CAS
~
'~'
"
:' \....:...J
~
\.i.J
:
I
~
I
J>
~
~~
~'~'~'~!3
.
~
i
~'~/~:~~~ ~
c:
I
AOA;
:u
m
~
~~~~ zm
cs~~
CKE
W-- -;---
BURST
,
BANK
ROW
(BIT)
ADDR
a
b
c
d
Q
B
CO+1
CO+2
CO+3
T
RO
R1
cot
0
TYPE
(DIQ)
~
-4
Z
21:u
BURST CYCLE
~
•
f
9
h
C1*
C1 + 1
C1+2
C1+3
oZ
oc:
en
~ .....
Zg
»m
cn~UI
5:0 ......
~ ~~~
(5
~Z~
z "1IC:O
lIloc
t CoIumn-address sequence depends on programmed burst type and CO. (see Table 5).
CoIumn-address sequence depends on programmed burst type and C1. (see Table 5).
*
NOTE A: This example Ulustrates a minimum fRCOand nEP read bUIst, and a minimum IRwL. write burst for the '626802-10 at 100 MHz, the '626802-12 at 80 MHz, and the
'626802-15 at 66 MHz.
Figure 28. Read-Burst Bank B, Write-Burst Bank T (read latency
~
X
:0
=3, burst length =4)
~S:m
~l>-<
-om
10m
1m ....
:uen-
~enm -I
ms:-<
s:
0m N en
~
Es:m~
~O»G)
-:u Z 51!!
1-<~iG
en
ACfVT
....:..
ACfVB
WRT·PT
Olen ..... -I
READ-PB
CLK
~-:
... CIIN
DQO-DQ7
ilj:J:JCP co
1 .......... 0)
!llg:.e2
~OO
:::!c:: ::a
DQM_:
RAS
~
\.U
V
CAS
~
A10
o_~
~z~
~~g
~m~
A11
V
V
'Ii
~
-en e
lem
1-<-<
:Dzco
!l!» •
iiis::::!!!
0_-1
~ Enm
~
iii:
~-~
w
~
1ll#lI_~
AO-A9
cs~'~'t&,.'_'~
~~
~
..!.
t
CKE
BURST
W
ROW
(DfQ)
(BIT)
ADDR
0
T
Q
B
RO
R1
•
cot
b
c
d
CO+1
CO+2
CO+3
.
~
C1*
f
9
h
I
C1 +1
C1 +2
C1 +3
!
*t
CoIumn-address sequence depends on programmed burst type and CO (see Table 5).
CoIumn-address sequence depends on programmed burst type and C1 (see Table 5).
NOTE A: This example illustrates minimum nCWL for the '626802·10 at 100 MHz, the '626802·12 at 80 MHz, and the '626802·15 at 66 MHz.
Figure 29. Write-Burst Bank T, Read-Burst Bank B With Automatic Deactivate (read latency
=3, burst length =4)
e~
Oz
:s::::"
:D
n
m
en
~
c:
~
m
iii:
m
en
3:
m
-t
o
z
Z
a:
~
oz
BURST CYCLE
3lZ •
iii:
2J:D
BANK
TYPE
~
:D
~::a<
;;;»N
:s::::
~
ACTVB
WRTB
READT
ACTVT
DCAB
CLK
~-~
(
DQM~h
0
w
I
~~~
'"
~~gd
:'
\
_ _
~
~:II
!:
~
m
m
_
~
!:
cs~~
CKE
~
.!.
_~Am
w--_.
cgz
:II
BURST
TYPE
BANK
ROW
(DfQ)
(BIT)
ADDR
Q
T
B
RO
0
!:
~
BURST CYCLE
•
cot
b
c
d
CO+1
CO+2
CO+3
•
R1
C1*
f
C1+1
g
C1+2
h
C1+3
*t
CoIumn-address sequence depends on programmed burst type and CO (see Table 5).
CoIumn-address sequence depends on programmed burst type and C1 (see Table 5).
NOTE A: This example iHustrates a minimum tAco read burst and minimum tRwL write burst for the '626802-10 at 100 MHz, the '626802-12 at 80 MHz,
and the '626802-15 at 66 MHz.
Figure 30. Use of DQM for Output and Data-In Cycle Masking (read-burst bank T, write-burst bank B, deactivate all banks)
(read latency 2, burst length 4)
=
~
VI
J
C
:II
AO-AS
;~
!
'0J
~
A10~ 1~1_ ~'~
~
~~
\i./
'0J
CAS
~m:z:
V
\i.I
HAS
~~~-~
=
...
oz
~
°o
::c
:D
Z
oc
en
C
-< .....
Zo
>&
cn~UI
150 .....
!!l:D~
~>::e
,ZO
illC:D
mOC
~S::m
~:i>-<
-oco
~o .
fm!!!
:uen-f
!1;!enm-f
0i:-< i:
!!1 m !\) en
Ei:mla
~O>G)
-:uz co
1<,,2
~
REFR
,
REFR
,
A~T
,
READT
DEACT
,
REFR
,
~(I)"'" .....
!!~15
CLK
~nUl~
1% ..... _
ilI:D~
IIIO==:
j!!ZO
~g:D
HAl
-tn C
I·
~
Vi
...
/D'1>1II
A10.,~,'-II
IIft'I,,"I!ft!'"
A1.1
~
~
r.l-"
...
~z
~i~
~~
;~
~
!!
1.
5
: ... :
:
'WEBD J
~
esl&. ~: ~:.-.'
CKE VI
'WBBBf'
: 'WBBBf'
I
•
.-.'
m
BURST
TYPE
BANK
~
•
::u
•
b
c
d
f
h
9
CO+1
CO+2
CO+3
CO+4
CO+5
CO+8
CO+7
fColumn-address sequence depends on programmed burst type and CO (see Table 8).
NOTE A: This example Ulustrates minimum lAc. lReo, nEP, and IRp for Ihe '828802-10 at 100 MHz, Ihe '826802-12 at 80 MHz, and Ihe '828802-15 at 88 MHz.
(D/Q)
Q •
(BIT)
ADDR
T
RO
cot
Figure 31. Refresh Cycles (refreshes followed by read burst followed by refresh) (read latency
~
::u
c
BURST CYCLE
ROW
I
iii:
I
=2, burst length =8)
III
I~<
~ZCP
m
iii:
m
....z
:IE
g
iii:
~
-0
Z
mi:c_ .....
EnID.
ifi:D~'
-'1> I\)
IZ m
0'1>
Oz
!!!:"
~
n
m
tn
tn
i:
m
!!!:
o
~
DCAB
Af:rVB
MRS
WRT-PB
CLK
------------------------------------------------------------~
DQODQ7
DaM
\..::J
HAS
\..::J
~
if~
I~r
I~
~
-
V
\.i.J
J
~
VI
~
§§§§§W
A10
-
A11
All-AS
cs~~_~_
~
~
n
i!:
~
en
::E:
:rJ
C
0
Z
0
C
tn
2J
m
m
i!:
Z
:!Z
c
-< ....
Zg
g » co
i!: cn!;cn
W
CKE
:J:I!
""t
BURST
BANK
ROW
(C/O)
(BIT)
ADDR
0
B
RO
TYPE
BURST CYCLE
•
cot
~n"'"
g:rJ~
o
Z i»o=E
,Z
"1IC:rJ
b
c
d
CO+1
CO+2
CO+3
t Column-acidress sequence depends on programmed burst type and CO (see Table 5).
NOTES: A. This example Ulustrates minimum tAco for the '626802-10 al100 MHz, the '626802-12 alSO MHz, and the '626802-15 al66 MHz.
B. Refer to FlQure 1
Figure 32. Mode Register Programming (deactivate all, mode program, write burst with automatic deactivate)
(read latency = 2, burst length = 4)
~
tn
2J
"n
!
C
-~
,
CAS
~
~
:
llIoc
~S::::m
~J:..-<
-nco
In6J
,rn-
::utn-l
;;t
cn_-<=tn
~tnm
~=-N
c..
rn • en
cS::::mN
iiio»o»
-;0 Z S!!!
1<~i\5
~
Acrrv T
READ-P T
AcrrvB
HOLD
WRT-PB
~(I)-'
CLK
Iii!~~~
000DQ7
DQM~:
HAS
~
CAS
VI
A10
~
s
il4r
~fg
~m~
i~
f
c
A11
:
_
\J
o
~
mw','@§W
v
0:a
c:
~(I) 0
-
\J
"'0<
~----
.1
(~u~p~~r~B~yte~)~---
\
Output
.
I
Figure 1. Example of a Byte-Read Cycle
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
6-88
TMS55160
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVSl80D-AUGUST 1992 - REVISED JUNE 11196
byte operation (continued)
In byte-write operation,·~ enables data to be written to the lower byte (OQO-OQ7) and CASU enables data
to be written to the upper byte (DQ8~OQ15). In an early-write cycle, WE Is brought low prior to both ~
signals. Data setup and hold times for OQO~OQ15 are referenced to the first falling edge of ~
(see Figure 2).
~~------------~I
\ _______________1
.j\""-_____-----II
I I
H
\ ______1
I I
leU(CA)i
..-~ ...
.
~ -I
"(cLCAI
~~I-·~
leu(DClJ
DQO-DQ15
I I
I~
~I I
II I!+1
.. ---l~~I-
~
Valid Input
. . tCLD)
\
~
Figure 2. Example of an Early-Write Cycle
-!I1TEXAS
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TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS160D- AUGUST 1992 - REVISED JUNE 1895
byte operation (continued)
For late-write or read-modify-write cycles, WE is brought low after either or both ~ and ~ fall. The data
is strobed in with data setup and hold times for 000-0015 referenced to WE (see Figure 3).
~----------------I
\'--_ _ _ _~I
~\\\\\\\\\\
I
j\,...._---I
teu(DWlJ --11+4-~~i I
I
I
DQO-DQ15
1144--"~1- tt.(WLD)
Yalldlnput
~~~~~~~~
Figure 3. Example of a Late·WrHe Cycle
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 772151-1443
5-81
TMS55160
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS1800-AUGUST 1992- REVISED JUNE 1895
write-per-bit
The write-per-bit feature allows masking any combination of the 16 OQs on any write cycle. The write-par-bit
operation is invoked when WE is held low on the falling edge of RAS. If WE is held high on the falling edge of
RAS, the write operation Is performed without any masking. The TMS55160 offers two write-per-bit modes: the
nonpersistent write-per-bit and the parsistent write-per-bit.
nonpersistent write-per-bit
When WE is lowon the falling edge of RAS, the write mask is reloaded. A 16-bit binary code (the write-par-bit
mask) Is input to.the device via the OQ pins and latched on the falling edge of RAS. The write-per-bit mask
selects which of the 161/0s are to be written and which are not. After RAS has latched the on-chip write-par-bit
mask, in.£!:!! data is driven onto the OQ pins and is latched on either the first falling edge of CASx or the falling
edge of WE, whichever occurs later. CAS[ ",nables the lower byte (OQO-OQ7) to be written through the mask,
and CASU enables the upper byte (OQ8-0Q15) to be written through the mask. If a data low (write mask = 0)
Is strobed Into a particular I/O pin on the falling edge of RAS, data Is not written to that I/O. If a data high
(write mask 1) Is strobed into a particular I/O pin on the falling edge of RAS, data Is written to that I/O
(see Figure 4).
=
~~--------------~/
I I
I I
I I
I I
\'-----------'/
I I
I
I
I
I
I
I
I
I
I
I
\'---------'/
\,--~I
!--J/
I I
~~
I I
leu{DQR} --I1·1III-~.1 I
I
I 1l1li
.1
I
14-11III-~.If- th(RDQ)
I
I
I
I I~111-...I~leu(DW411
I
I
I
DQO-DQ15~
WriteMaak
~
Valid Input
th(WLD)
~
Figure 4. Example of a Nonpersistent Wrlte-Per-Blt (late-Write) Operation
-!I1TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 772t51-1443
TMS55160
262144 BY 16-81T
MULTIPORT VIDEO RAM
SMVS180D- AUGUST 19112 - REVISED JUNE 1l1li6
perll'stent wrlte-per-blt
The persistent write-per-bit mode Is initiated only by performing a load-write-mask-reglster (LMR) cycle first.
In the persistent write-per-bit mode, the write~per-bit mask Is not overwritten but remains valid over an arbitrary
number of write cycles until another LMR cycle is performed or power is removed.
The load-write-mask-register cycle is performed using DRAM write-cycle timing except DSF Is held high on the
falling edge of RAS and held low on the first failing edge of CASx. A blC~code Is Input to the write-mask register
via the random I/O pins and latched on either the first falling edge of Ax or the failing edge of WE, whichever
occurs later. Byte-write control can be applied to the write mask during the 10ad-write-mask-register cycle. The
persistent write-per-bit mode can then be used in exactly the same way as the nonpersistent write-per-bit mode
except that the Input data on the falling edge of RAS is ignored. When the device Is set to the persistent
write-per-blt mode, it remains In this mode and Is reset only by a CBR refresh with option reset cycle
(see Figure 5).
RAIn
I
Load-Wrlte-Maak Register
I
I
~
\
I
Pe,.latent Wrlte-Per-Blt
CBR Refreeh (option "III)
I
I-~-\'- _ _ _--JI--~---\
j--i
I
/1
I
---I
I
I
\
I .
/
I
1\
I
I
AO-AS
I
I
'W*..em+
WiP 'W*. ~
AcId....
DSFP
I
&
~ ~
~ ~
Am.
~~5~
~
I
Write-Milk Data
I
I
Valid
~
I
Input
Ma.k Data • 1: Write to I/O enabled
• 0: Write to 110 dillbl,d
Figure 5. Example of a Persistent Wrlte-Per·Blt Operation
~TEXAS
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POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS180D -AUGUST 1992 - WSED JUNE 1995
block write
The block-write feature allows up to 64 bits of data to be written simultaneously to one row of the memory array.
This function is implemented as (4 columns )( 4 DQs) repeated in four quadrants. In this manner, each of the
four one-megabit quadrants can have up to four consecutive columns written at a time with up to four DQs per
column (see Figure 6).
DQ1SIJII]
DQ14 [ [ I ]
DQ13 [ [ I ]
DQ1Z[[I]
DQ11[[I]
DQ10[[I]
DQ9[[I]
DQalJII]
One Row of 0-&11
DQ71JII]
DQ6[[I]
DQS[[I]
DQ41JII]
DQ3[[I]
DOZ[[I]
DQ1[[I]
-~
4 ConeecuUve Columna of 0-&11
Figure 6. Block-Write Operation
Each one-megabit quadrant has a 4-bit column mask to mask off any or all of the four columns from being written
with data. Nonpersistent write-per-bit or persistent write-per-bit functions can be applied to the block-write
operation to provide write masking options. The DQ data is provided by four bits from the on-chlp color register.
Bits 0-3 from the 16-bit write-mask register, bits 0 -3 from the 16-bit column-mask register, and bits 0 -3 from
the 16-blt color-data register configure the block write for the first quadrant, while bits 4 -7, 8 -11, and 12 -15
of the corresponding registers control the other quadrants In a similar fashion (see Figure 7).
~1ExAs
INSTRUMENTS
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SMVSl60D-AUGUST 1992- REVISED JUNE 1896
block write (continued)
DQ15[I]J]
DQ14[I]J]
DQ13[I]J]
DQ12
l
r--
,..J,..J
-,
DQ11[I]J]
, , ; DQ10[I]J]
Jt
DQ8[]
One Row of 0-511
I
~:::II
8
I
I
I I
I I II
I ~ .J
~
.J
.J
r--,
:...1_, I
~
rI.
12 f,j~
13
fi
14
~>
15
DQ9[I]J]
,
..1_, I
DQ7[I]J]
DQ5[I]J]
ITT1l
DQ5WJj
8
9
~>
1,/
_, I I
I I I
I
I I
10
~
11 ++-I-+.~
l,.J
t.J
.J
0
1
2
3+++-H~L
I~~
I~ >
I~ >
~>
\ 0 1 2 3
4 5 8 7
8 9 10 11
12 13 14 15 I
~------------------------------~v~--------------------------------~
Color Register
Figure 7. Block Write With Masks
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
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TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS160D -AUGUST 1992 - REVISED JUNE 1995
block wrIte (contInued)
Every four columns make a block, which makes 128 blocks along one row. Block 0 comprises columns 0 -3,
block 1 comprises columns 4 -7, block 2 comprises columns 8 -11, etc., as shown In Figure 8.
Block 0
Block 1 ...................... Block 127
\
I
" ....- - " ' 1 \
,,-----"'---.....v'---'''
On. Row 010-511
I
I
o
2
3
4
5
I
8
I
I
7 ••••••••••••••••••••••••••• 511
'. . -----------.....vr-----------.J'
Columna
Flgur. 8. Block Columns OrganIzatIon
During bIOCk-w@e cycles, only the seven most significant column addresses (A2-AS) are latched on the first
falling edge of ASx to decode one of the 128 blocks. Address bits AO-A1 are Ignored. Each one-megabit
quadrant has the same block selected.
A block-write cycle is entered in a manner similar to a DRAM write cycle except OSF is held high on the first
falling edge.ofCASx. As in a DRAM write operation, CASLand CASU enable the corresponding lower and upper
DRAM DO bytes to be written, respectively. The column-mask data is input via the DOs and is latched on either
the first falling edge of CASx or the falling edge of WE, whichever occurs later. The 16-bit color-data register
must be loaded prior to performing a block write as described below. Refer to the write-per-bit section for details
on use of the write-mask capability, allowing additional performance options.
Example of block write:
block-write column address
color-data register
write-mask register
column-mask register
= 110000000 (AO-A8 from left to right)
bit 0
= 1011
= 1110
= 1111
1st
Ouad
1011
1111
0000
2nd
Ouad
1100
1111
0111
3rd
Ouad
bit 15
0111
1011
1010
4th
Ouad
Column-address bits AO and A1 are ignored. Block 0 (columns 0 -3) Is selected for each one-megabit quadrant.
The first quadrant has POO-002 written with bits 0-2 from the color-data register (101) to all four columns of
block O. 003 Is not written and retains Its previous data due to the write-mask register bit 3 being a O.
The second quadrant (004-007) has all four columns masked off due to the column mask bits 4-7 being 0,
so that no data Is written.
The third quadrant (008-0011) has its four ~Os written with bits 8-11 from the color-dataregister (1100) to
columns 1-3 of its block O. Column 0 is not written and retains its previous data on all four ~Os due to the column
m~k-register bit 8 being O.
The fourth quadrant (0012-0015) has 0012,0014, and 0015 written with bits 12, 14, and 15 from the
color-data register to column 0 and column 2 of its block O. 0013 retains its previous data on all columns due
to the write mask. Columns 1 and 3 retain their previous data on all ~Os due to the column mask. If the previous
data for the quadrant was all Os, the fourth quadrant would contain the data pattern shown in Figure 9 after the
block-write operation shown in the previous example.
~ThxAs
5-96
INSTRUMENTS
POST OFFICE BOX 14.43· HOUSTON. TEXAS 77251-14.43
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVSl80D- AUGUST 1992 - REVISED JUNE 1995
block write (continued)
I II
I II
IIII
001511
001411
00131 0
0
0
0 11
0 11
0
0
0
DQ"~
Columns 0
1
2
3
Figure 9. Example of Fourth Quadrant After a Block-Write Operation
load color register
The load-color-register~e~ormed using normal DRAM write-cycle timing except that OSF is held high
on the falling edges of RAS, CASL, and CASU. The color register is loaded from pins 000 -0015, which are
latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later. If only one CASi
is low, only the corresponding byte of the color register is loaded. When the color register is loaded, it retains
data until power is lost or until another load-color-register cycle is performed (see Figure 10 and Figure 11).
I
I
I
load-Color-Register Cyels
iI '
\
7
I
I
I
I
I
Block-Write Cycle
(no write mask)
Block-WrIte Cyels
(load and u. . write ~k)
I
I
/P
\
2
3
I
I
I
/I
/-1
\
2
3
OSF
DaO-Da15
6
Legend:
,1.
2.
3..
4.
5.
8.
Refresh address
Row address
Block address (A2-AB) Is lalched on the first failing edge of CASx.
Color-register data
Write-mssk data: OQO-DQ15 are latched on the failing edge of~.
Column-mask data: OQI-OQI+3 ~ "' O. 4. 8. 12) are latched on either the first falling edge of ~ or the failing edge of WE. whichever
occurs latar.
• don't care
Figure 10. Example of Block Writes
~1ExAs
INSTRUMENTS
POeT OFFICE BOX 1443 • HOUSTON, TEXAS 77281-1443
5-97
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVSl60D-AUGUST 1992-REVlSED JUNE 1995
load color r.gl8ler (continued)
I
I
I
Load.WrHe-Maak-Regl8ter Cycle
I
I
I
I
I
I
Load-Color.Reglster Cycle
I
I
I
Persistent Block·WrHe Cycle
(u.e loaded write mask)
~i'~==~--~~~-=.==~--~~~~==~----/I
''-___I I
' ____I I
,'-___/-1
I
AO-AS
2
WE
TRG
DSF
DQD-DQ15
6
Legend:
1. Refresh eddress
2. Row eddress
3. Blockaddrees (A2-AS) Is latched on the first falling edge of CASx.
4. Color-reglster data
5. Wrlte-mask data: OQO -0015 are latched on the falling edge of CASx.
6. Column·mask data: 001-001+3 Q 0, 4, 8, 12) are latched on either the first falling edge of CASx or the falling edge of~, whichever
occurs later.
=
«:ac::::cc::ccnccc~
;;I
don' care
Figure 11. Example of a Persistent Block Write
DRAM·to·SAM transfer operation
During the DRAM·ta-SAM transfer operation, one half of a row (256 columns) in the DRAM arr~selected
to be transferred to the 256-bit serial-data register. The transfer operation is invoked by bringing TRG low and
holding WE high on the falling edge of RAS. The state of DSF, which is latched on the falling edge of RAS,
determines whether the full·register·transfer read operation or the split-register-transfer read operation is
performed.
Table 4. SAM Function Table
CASx
FALL
RAS'FALL
FUNcnON
ADDRESS
DQD-DQ15
MNE
CODE
CASxt
TRG
WE
DSF
DSF
RAS'
CASx
RAS'
CASx
WE
Full-reglster-transfar reed
H
L
H
L
X
Row
Addr
Tap
Point
X
X
AT
Spllt-register-transfar read
H
L
H
H
X
Row
Addr
Tap
Point
X
X
SAT
t logic L Is selected when either or both CAS[ and CASU are low.
X = don'tcare
~ThxAs
5-98
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, 'I1:XAS 77251-1443
TMS55160
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS160D-AUGUST 1992-REVISEDJUNE 1995
full-register-transfer read
A full-reglster-transfer read operation loads data from a selected half of a row in the DRAM into thEi-s.~M. TRG
is brought low and latched at the falling edge of RAS. Nine row-address bits (AO-AS) are also latched at the
falling edge of RAS to select one of the 512 rows available for the transfer. The nine column-address bits
(AO-AS) are latched at the first falling edge of CASx, where address bit AS selects which half of the row is
transferred. Address bits AO-A7 select one of the SAM's 256 available tap points from which the serial data
is read out (see Figure 12).
AS.O
o
255258
AS.1
511
512" 512
MemoryArny
2!58-BIt
Data Reglatar
o
255
Figure 12. Full-Reglster-Transfer Read
A full-register-transfer read can be performed in three ways: early load, real-time load (or midline load), or late
load. Each of these offers the flexibility of controlling the TRG trailing edge In the full-reglster-transfer read cycle
(see Figure 13).
,
RAS
Early Load
'T'
i'
I
CASX:
\
I
AO-AS,
Row
TROr\....l
Tap
Point
I
Real-Time Load
I
I.
I
I
Row·
,
i
,
I
I
I
\
Lata Load
'T'
I
\
Tap
Point
I
I
I
'---/
Row
I
,
I
i\
Tap
Point
I
,
I
:
I
I
/I
I
WfP'~~~
I
I
I
I
SC
I
I
Figure 13. Example of Full-Reglster-Transfer Read Operations
="lExAs .
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77261-1443
5-99
TMS55160
262144 BY 16·BIT
MULTIPORT VIDEO RAM
. SMVS1800-AUGUST 1892 - REVISEO JUNE 1895
spllt-reglster.:transfer read
In the spllt-reglster-transfer read operation, the serial data register is split into halves. The low half contains bits
0-127, and the high half contains bits 128-255. While one half Is being read out of the SAM port, the other
half can be loaded from the memory array.
o
511
512 .. 512
Memory Alray
256-B1t
Data Reglatar
o
255
Figure 14. Spllt-Reglster-Transfer Read
To Invoke a SPlit-regist:r-transfer read cycle, DSF Is brought high, TRG is brought low, and both are latched at
the falling edge of RA . Nine row-address bits (AO-AS) are also latched at the falling edge of RAS to select
one of the 512 rows available for the transfer. Eight of the nine column-address bits (AD-AS and AS) are latched
at the first falling edge of CASx. Column-address bit AS selects which half of the row Is to be transferred.
Column-address bits AD-AS select one of the 127 tap points in the specified half of the SAM. Column-address
bit A7 Is Ignored, and the split-register-transfer is intemally controlled to select the Inactive register half.
Aa.1
,-A-..
0...-,......,,.....,,......511
A B
DRAM
SAM
SQ
o
A7_0t 511
m
°ltli~
SQ
t A7 shown Is Internally controlled.
Figure 15. Example of a Split-Register-transfer Read Operation
A full-register-transfer read must precede the first split-register-transfer read to ensure proper operation. After
the full-register-transfer read cycle, the first split-register-transfer read can follow Immediately without any
minimum SC clock requirement.
~TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
TMS55160
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS180D - AUGUST 1992 - REVISED JUNE 1985
spllt-reglster-transfer read (contInued)
QSF indicates which half of the register is being accessed during serial access operation. When QSF is low,
the serial-address pOinter is accessing the lower (least significant) 128 bits of the SAM. When QSF is high, the
pointer is accessing the higher (most significant) 128 bits of the SAM. QSF changes state upon completing a
full-register-transfer read cycle. The tap point loaded during the current transfer cycle determines the state of
QSF. QSF also changes state when a boundary between two register halves is reached.
Full-Reglater-Transfer Read
WIth Tap Point N
I
I
\
RAS
\1
CASx
1
I
1
1
\
'fAG
DSF
I
1
1
~
SC
QSF
Spllt-Reglater
Transfer Read
I
I
\
\
II1
I
\
1
I
1
1
1\
id(CLQSF)
I~
4
~
PolntN
~
id(GHQSF)
Figure 16. Example of a Spllt-Reglster-Transfer Read After a Full-Register-Transfer Read
Spln-Reglster
Tranefer Read
With Tap Point N
Ii1
\
RAJ
'fAG~
)\
1
1
1
1
\1
~
\
CASx
Spln-Reglater
Tranafer Raad
I
1
I
1
1
1
I
DSF~
id(RHMS)
\
I
I
h.I
14
I
I
id(MSRL)
SC
14-----.,~*I- id(SCQSF)
QSF
------------------------------~~~I
____________________
Figure 17. Example of Successive Split-Register-Transfer Read Operations
~TEXAS
INSTRUMENTS
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5-101
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS160D-AUGUST 1992 - REVISED JUNE 1996
serial-read operation
The serial-read operation can be performed through the SAM port simultaneously and asynchronously with
DRAM operations except during transfer operations. Serial data can be read from the SAM by clocking SC
starting at the tap point loaded by the preceding transfer cycle, proceeding sequentially to the most significant
bit (bit 255), and then wrapping around to the least significant bit (bit 0), as shown In Figure 18.
r'
0
1 1 1 2 1 . . . . . 1 Tap 1-+ . . • 1 2541 255
,
I
I
Figure 18. Serial Pointer Direction for Serial Read
For split-register-transfer read operation, serial data can be read out from the active haH of the SAM by clocking
SC starting at the tap point loaded by the preceding split-register-transfer cycle. The serial pointer proceeds
sequentially to the most significant bit of the half, bit 127 or bit 255. If there Is a split-register-transfer read to
the inactive half during this period, the serial pointer points next to the tap point location loaded by that
split-reglster-transfer (see Figure 19).
Figure 19. Serial Pointer for Split-Register Read - Case I
If there is no split-register-transfer read to the Inactive half during this period, the serial pOinter points next to
the least significant bit of the inactive half, bit 128 or bit 0 (see Figure 20).
Figure 20. Serial Pointer for Split-Register Read - Case II
split-register programmable stop point
The TMS55160 offers programmable stop-point mode for split-register-transfer read operation. This mode can
be used to improve 2-D drawing performance In a nonscanline data format.
In split-register-transfer read operation, the stop point Is defined as a register location at which the serial output
stops coming from one haH of the SAM and switches to the opposite haH of the SAM. While in stop-point mode,
the SAM is divided Into partitions whose length Is programmed via row addresses A4-A7 in a CBR set (CBRS)
cycle. The last serial-address location of each partition is the stop point (see Figure 21).
127
0
PartHlon
Length
I
~
I
{
I· · ·1
1. ..
128
I
I
255
I
I I. ..
Figure 21. Example of the SAM With Partitions
~1ExAs
5-102
I· · -I
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 772S1-1443
I
I
Stop
Pointe
TMS55160
262144 BY 16-BI1
MULTIPORT VIDEO RAM
SMVS160D - AUGUST 1992 - REVISED JUNE 1995
split-register programmable stop point (continued)
Stop-point mode is not active until the CBRS cycle is initiated. The CBRS operation is performed by holding
CASx and WE low and DSF high on the falling edge of RAS. The falling edge of RAS latches row addresses
A4-A7, which are used to define the SAM's partition length. The other row-address inputs are don't care.
Stop-point mode should be initiated after the initialization cycles have been performed (see Table 5).
Table 5. Programming Code for Stop-Point Mode
ADDRESS AT RAS IN CBRS CYCLE
MAXIMUM
PARTITION
LENGTH
AS
A7
AS
AS
A4
AO-A3
16
X
L
L
L
L
X
16
NUMBER OF
PARTITIONS
STOP-POINT LOCATIONS
15.31,47.63.79.95.111.127.143.159.175.
191.207.223.239.255
32
X
L
L
L
8
31.83.95.127.159.191.223.255
X
L
L
H
H
H
X
84
X
4
83.127.191.255
128
(default)
X
L
H
H
H
X
2
127.255
In stop-point mode, the tap point loaded during the split-register-transfer read cycle determines in which SAM
partition the serial output begins and at which stop point the serial output stops coming from one half of the SAM
and switches to the opposite half of the SAM (see Figure 22).
RAS
\..
Y
~ReadXFER
Split
Full .. /
\"ead XFEr
Tap .. H1
y
~
Tap .. L1
Split
Tap.H2
H1
L1
t
SAM Low Half
83
1
l1li
L2
127
L1
Tap.L2
255 L2
SC ________________~ ••• ~ ••• ~ • • • • • • ~
0
191
Y
~8adXFER
Split
R8adXFER
83
128
t:
l1li
H1
H2
SAM HIgh Half
191
:
l1li
H2
255
f
1 1
•
l1li
Figure 22. Example of Split-Register Operation With Programmable Stop Points
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
5-103
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVSl60D -AUGUST 1992 - REVISED JUNE 1995
256-/512-blt compatibility of split-register progrsmmable stop point
The stop-point mode Is designed to be compatible both for 256-blt SAM and 512-blt SAM devices. After the
CBRS cycle is initiated, the stop-point mode becomes active. In the stop-point mode, and only In the stop-point
mode, the column-address bits AY7 and Aya are internally swapped to assure the compatibility (see Figure 23).
This address-bit swap applies to the column address, and It Is effective for all DRAM and transfer cycles. For
example, during the split-reglster-transfer cycle with stop point, column-address bit Aya is a don't care and AY7
decodes the DRAM row half for the spllt-register-transfer. During stop-point mode, a CBR option reset cycle Is
not recommended because It ends the stop-point mode and restores address bits AY7 and Aya to their normal
function. Consistent use of CBR cycles ensures that the TMS55160 remains in normal mode.
NON STOP.pOINT MODE
STOP.pOINT MODE
812x512
812 x 512
Memory Array
Memory Array
25&-BIt
Data Raglatar
25&-BIt
Data Reglatar
FIgure 23. DRAM-to-SAM Mapping, Non Stop-Point Versus Stop Point
IMPORTANT: For proper device operation in a split-register stop-point mode, a CBRS cycle should be Initiated
right after the power-up initialization cycles have been performed.
power up
To achieve proper device operation, an initial pause of 200 !AS is required after power up followed by a minimum
of eight RAS cycles or eight CBR cycles to initialize the DRAM port. A full-register-transfer read cycle and two
SC cycles are needed to Initialize the SAM port.
After initialization, the Internal state of the TMS55160 is as follows:
STATE AFTER INITIALIZATION
aSF
Write mode
Write-mask register
Color register
Serial-register tap point
SAM port
Defined by the transfer cycle during Initialization
Nonpersistent mode
Undefined
Undefined
Defined by the transfer cycle during Initialization
Output mode
~I~ TEXAS
5-104
NSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS180D- AUGUST 1992 - REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise notec:l)t
Supply voltage range, Vee (see Note 1) ............................... . . . . . . . . . . .. . . .. -1 V to 7 V
Voltage range on any pin • • • • • • • • • • • • • • • . • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • . • • • •• -1 V to 7 V
Short-circuit output current •••••••••••••••••••••••••••.•.••••••••••••••••.•.••••••••••••••• 50 rnA
Power dissipation •.••••••..••••..•••.•••••..•••..••....••.•.•••...••••.•••..•••..•••••.•• 1.1 W
. Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Streaaea beyond thOl8llsted under "absolute maximum ratings" may causa permanent damage to the device. Thasa are stress ratings only, and
functional operation of the device !It thasa or any other conditions beyond those Indicated under "recommended operating conditions" Is not
Implied. Exposure to absoluta-maxlmum-ratacl conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
Vee
MIN
4.5
Supply voltage
NOM
5
MAX
5.5
UNIT
V
Supply voltage
0
V
Hlgh-lavellnput voltage
2.4
6.5
V
VIH
Low-lavallnput voltage (sea Nota 2)
-1
0.8
V
VIL
Operating frea..alr temperature
0
70
OC
TA
.. . .
NOTE 2: The algebraic convention. where the more negative ~ass positIVe) limit Is dasJgnatad as minimum. Is used for loglc-voltage lavals only•
VSS
~1EXAS
INSTRUMENTS
POST OFFJCE BOX 14<13 • HOUSTON. TeXAS 77251-14<13
5-105
TMS55160
262144 BY 16..BIT
MULTIPaRT VIDEO RAM
SMVSl60D- AUGUST 1992 - REVISED JUNE 1985
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS*
VOH
High-level output
voltage
IOH--1mA
VOL
Low-level output
voltage
IOL-2mA
II
Input current (leakage)
Voo=S.SV,
VI- OVtoS.8V,
All other pins at 0 V to VCC
SAM
PORT
'55160-60
MIN MAX
'55160-70
MIN MAX
2.4
2.4
'55180-80
MIN MAX
2.4
UNIT
V
0.4
0.4
0.4
V
:1:10
:t10
:1:10
I4A
:1:10
:1:10
:1:10
I4A
180
225
185
205
150
185
S
70
S
8S
6
mA
mA
80
mA
ICC1
Output current
Oeakage)
Operating current §
ICC1A
1002
Operating current'
Standby current
loISCI-MIN
All clocks. Voo
ICC2A
lo(SC) .. MIN
ICC3
Standby current
RAS-only refresh
current
Stsndby
ActIve
Standby
Active
See Note 4
Stsndby
180
18S
150
mA
1CC3A
RAS-only refresh
current
lo(SC) =MIN.
See NoteS
Active
226
20S
185
mA
1CC4
Page-mode current §
loIP)- MIN.
SeeNoteS
mA
See Notss
CBR current
CBRcurrent
lo(SC) - MIN.
See Note 4
See NoteS
1SS
18S
20S
140
150
185
mA
Ioos
lolSCI =MIN,
See Note 4
135
17S
105
Page-mode current §
Stsndby
ActIve
Standby
ActIve
Standby
Active
11S
loo4A
mA
mA
180
180
mA
22S
200
mA
10
ICCSA
VCC- 5.5 V, Vo .. OVtoVoo
'See Note 3
See Note 4
180
.226
200
250
Oats-transfer current
ICC8
loISCI-MIN
ICCM Oats-transfer current
* For conditions shown as MIN/MAX. use the appropriate value specified In the timing requirements.
§ Measured with outputs open
NOTES: 3. SE Is disabled for SQ output leakage tssts.
4. Measured with one eddress change while RAS - VIL. lo(rd). lo(W). tc(TRO). - MIN.
S. Measured with one addreas change while ~ - VIH
mA
capacitance over recommended ranges of supply voltage and operating free-air temperature.
f = 1 MHz (see Note 6)
PARAMETER
MIN
MAX
UNIT
CIIA)
Input capacitance. address Inputs
8
pF
Ci(RC)
Input capacitance. address strobe inputs
7
pF
Ci(W)
Input capacitance. writs enable input
7
pF
CI(SC)
Input capacitance. serial clock
7
pF
CIISEl
Input capacitance. serial enable
Input capacitance. special function
7
pF
7
pF
Input capacitance. transfer register Input
7
7
pF
pF
9
pF
CIIDSA
Ci(TRG)
Co(Ol
Output capacitance. SQ and DQ
ColQSA Output capacitance. QSF
NOTE 8: VCC 6 V :I: 0.6 V. and the bias on pins under tsst Is 0 V.
=
~1ExAs
INSTRUMENTS
5-108
POST OFFICE BOX 1 _ · HOUSTON, TEXAS 77251-1_
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS1600-AUGUST 1992-REVISEO JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 7)
'55160-60
'55160-70
'55180-80
MIN
MIN
MIN
PARAMETER
TEST
CONDITIONSt
ALT.
SYMBOL
ta(C)
Access time from CASx
fcI(RLCL) .. MAX
teAC
17
20
20
III
ta(CA)
Access time from column address
fcI(RLCL)
tAA
30
35
40
ns
ta(CP)
Access time from CASx high
fcI(RLCL) • MAX
tePA
35
40
45
III
ta(R)
Access time from RAS
fcI(RLCL) .. MAX
tRAC
60
70
60
III
ta(G)
Access time of DQ from TRG low
toEA
t5
20
20
ns
=MAX
MAX
MAX
MAX
UNIT
ta(SQ)
Access time of SQ from SC high
CL=30pF
tsCA
t5
20
25
ns
ta(SE)
Access time of SQ from SE low
CL,,30pF
tsEA
12
15
20
ns
fcIls(CH)
Disable time, random output from
CASx high (saa Note 8)
CL"'50pF
toFF
0
15
0
20
0
20
ns
fcIls(G)
"i'RG high (sea Nota 8)
CL,,50pF
toEZ
0
15
0
20
0
20
ns
fcIis(SE)
SE high (see Note 8)
CL,,30pF
tsEZ
0
10
0
15
0
20
III
Disable time, random output from
Disable time, sarial output from
t Measured with outputs open. For conditions shown as MIN/MAX. usa the appropriate value specified under timing requirements.
NOTES: 7. Switching times for RAM port output are measured with a load equivalent to 1 TIL load and 50 pF. Data out reference laval:
VOH /VOL 2 V/O.8 V. Switching times for SAM port output are measured with a load equivalent to 1 TTL load and 30 pF. Serial data
out reference lavel: VOH / VOL" 2 V/O.8 V.
8. fcIis(CH). fcIis(G). and fcIis(SE) are specified when the output is no longer driven.
=
·~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
5-107
TMS55160
.262144 BY 16-BI1
MULTIPORT VIDEO RAM
SMVSl80D- AUGUST 1892 - REVISED JUNE 1895
timing requirements over recommended ranges of supply. voltage and operating free-alr
temperaturet
ALT.
'&S160-60
SYMBOL
MIN
MAX
'55160-70
MIN
MAX
'&5160-60
MIN
MAX
UNIT
teCreIl
telWl
te(rdWl
Cycle time, read
tRC
110
130
150
ns
Cycle time, write
twc
110
150
nl
150
200
tc:(P)
Cycle time, page-mode reed, write
tAMW
tpC
130
175 .
35
40
ns
ns
teIROWPI
Cycle time, page-mode reed-modify-write
tpRMW
80
90
45
100
terrRO)
Cycle time, transfer reed
tRC
110
130
150
nl
te(SC)
Cycle time, serial clock (see Note 9)
tscc
18
22
3b
ns
tw(CH)
Pulse duretlon, CASx high
tePN
10
tw(CU
Pulse duration, CASx low (see Note 10)
17
tw(RH)
Pulse duration, AAS high
teAS
tAp
lo,rtRLl
Pulse duration, AAS low (see Note 11)
tRAS
twlWLl
tw(TRG)
Pulse duration, WE low
lWP
tw{SCHl
tw(SCLI
Pulse duration, SC high (see Note 9)
tw(GH)
Pulse duration, 'fAG high
tw(RL)P
Pulse duration, RAS low (page mode)
tRASP
tsu(CAI
Setup time, column address before CASx low
tASC
Cycle tline, read-modify-write
Pulse duration, 'i"RG low
tsc
tscp
Pulse duration, SC low (see Note 9)
trp
10
10000
20
40
50
80 10000
10
15 .
70
nl
10
10000
20
10000
80
80
nl
10000
nl
nl
10
15
ns
ns
nl
10000
20
20
5
8
10
ns
5
8
10
n.
n.
20
20
20
60 100000
70 100000
80 100000
0
ns
0
0
nl
n.
tsu(SFC)
Setup time, OSF before CASx low
tFSC
0
0
0
tau(RA)
Setup time, row address before RAS low
tASR
0
0
0
n.
tsulWMRI
Setup time, WE before RAS low
0
0
nl
taulOORI
Setup time, OQ before RAS low
twsR
tMS
0
0
0
0
ns
tsurrRGI
tsulSFRI
tau(OCU
Setup time, 'i'RG high before RAS low
Setup time, OSF low before AAS low
trHS
0
tFSR
tosc
0
0
0
0
0
0
n.
nl
0
0
n.
tsu(DWL)
Setup time, data valid before WE low
tosw
0
0
0
nl
tau(rd)
Setup time, read command, WE high before
~Iow
tAos
0
0
0
ns
tau(WCL)
Setup time, early write command,
WE low before CASx low
twcs
0
0
0
nl
tsu(WOH)
Setup time, WE low before CASx high, write
tcwL
15
15
20
ns
tsu(WRH)
Setup lime, WE low before RAS high, write
tAWL
15
15
20
n.
Setup time, data valid before CASx low
Hold time, column address after CASx low
15
10
10
nl
teAH
Hold lime, OSF after CASx low
10
10
15
nl
Itt{SFQt
teFH
10
Hold lime, row address after AAS low
10
ns
10
th(RAI
tRAH
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 9. Cycle time assumes tt 3 na.
10. In a read-modify-write cycle,Id(CLWL) and tau (WCH) must be obs8lV8d. Depending on the user's transition times, this can require
additional CASx low time !tw(CL))'
11. In a read-modify-write cycle,Id(RLWL) and tau(WRH) must be observed. Depending on the uler's transition times, this can require
additional RAS low time !tw(RL))' .
th(CLCA)
=
~1ExAs1
5-108
INSTRUMENTS
PosT OFFICE lOX 1443 •
HOUSTON. lEXAS 77251-1443
TMS55160
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS180D - AUGUST 1992·- REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued) t
ALT.
SYMBOL
thrrRG)·
Hold time, 'i'RG after RAS low
!h1RWM1
th(RDQ)
Hold time, write mask after RAS low
th(SFR)
th(RLCA)
Hold time, DQ after RAS low (write-mask operation)
Hold time, DSF after RAS low
Hold time, column addrase valid after RAS low
(see Note 12)
th(CLD)
Hold time, data valid after CASx low
!h(RLD)
Hold time, data valid after RAS low (see Note 12)
1t!(WLD)
!h(CHrd)
Hold time, data valid after WE low
Hold time, read, WE high after CASx high
(see Note 13)
th(RHrd)
Hold time, read, WE high after RAS high
(see Note 13)
'55160-80
'55160-70
'55160-80
MIN
MIN
MIN
MAX
MAX
MAX
UNrr
trHH
tRWH
10
10
10
ns
10
10
tMH
tRFH
10
10
10
10
ns
ns
tAR
30
10
10
10
ns
30
35
ns
tDH
15
15
35
tDH
15
35
15
15
35
15
ns
tDHR
tACH
0
0
0
ns
tARH
0
0
0
ns
15
35
15
35
10
ns
ns
ns
ns
ns
th(CLWl
tIJ(RL..W)
thlWLG)
Hold time, write, WE low after CASx low
Hold time, write, WE low after RAS low (see Note 12)
Hold time, 'i'RG high after WE low (see Note 14)
twCH
twCR
toEH
10
30
10
th(SHSQ)
th(RSF)
Hold time, SQ valid after SC high
tsOH
Hold time, DSF after RAS low
tFHR
tcSH
4
30
10
ns
ns
teHR
10
0
1d(CLRH)
Delay time, CASx low to RAS high
teRP
tRSH
5
30
70
10
0
17
20
5
35
SO
15
0
20
1d(CLWL)
Delay time, CASX low to WE low
(see Notes 15 and 17)
tcwo
37
45
45
1dlRLCLl
1d(CARH)
Delay time, RAS low to CASx low (see Note)
Delay time, column address valid to RAS high
tRCD
tRAL
30
35
teAL
tRWD
30
35
40
SO
95
105
ns
ns
tAWD
50
60
65
ns
teSR
tRPC
0
0
0
0
0
0
ns
ns
17
20
20
ns
15
ns
1d(RLCH)
Delay time, RAS low to CASX high
1d(CHRL)
Delay time, CASx high to RAS low
I
I See Note 15
1d{CACHl Delay time, column addrase valid to CASx high
1dlRLWL) Delay time, RAS low to WE low (see Note 16)
Delay time, column addreas valid to WE low
1d(CAWL) (see Note 16)
1d(CLRL)
Delay time, CASx low to RAS low (see Note 15)
1d(RHCL)
Delay time, RAS high to CASx low (see Note 15)
1d(CLGH)
Delay time, CASX low to TRG high for DRAM read cycles
60
20
43
20
Delay time, TRG high before data applied at DQ
10
15
1d(GHD)
toED
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 12. The minimum value is measured when 1d(RLCL) is set to 1d(RLCL) min as a reference.
13. Either !h(RHrd) or th(CHrd) muat be setisfied for a read cycle.
14. Output-enable-controlled write. Output remains in the high-Impedance atate for the entire cycle.
15. CBRrefresh operation only
16. Read-modify-write operation only
17. 'i'RG must disable the output buffers prior to applying data to the DO pins.
18. The maximum value is speciflad only to easure AAS access time.
50
20
40
ns
ns
ns
ns
60
ns
ns
~ThxAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
5-109
TMS5516J)
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS160D -AUGUST 1992 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (contlnued)t
ALT.
SYMBOL
'55160-60
MIN
MAX
'55180-70
'55160-80
MIN
MIN
MAX
MAX
UNIT
idlRLTHl
Delay time, RAS low to TAG high (see Note 19)
lATH
50
55
60
na
id(RLSH)
Delay'time, RAS low to first SC high after TRG high
(aee Note 20)
!ASD
55
70
60
ns
id(RLCA)
Delay time,
tRAD
15
idlGLRHI
Delay time, ffiG low to RAS high
tROH
10
15
15
na
id(CLSH)
Delay time, ~ low to first SC high after ffiG high
(see Note 20)
leSD
20
20
25
na
id(SCTR)
Delay time, SC high to TRG high
(see Notea 19 and 20)
!TSL
5
5
5
na
idlTHRHI
id(THRLI
Delay time, TRG high to RAS high (see Note 19)
!TRD
-10
-10
-10
na
Delay time, ffiG high to FiAS low (see Note 21)
!TRP
40
50
60
na
idITHSC)
Delay time, TRG high to SC high (see Note 19)
!TSD
10
10
15
ns
id(RHMS)
Delay time, RAS high to last (most significant) rising
edge of SC before boundary switch during aplltregister-transfer read cycles
15
20
20
ns
id(CLTH)
Delay time, CASx low to ffiG high In real-time transfer
read cycles
tcTH
15
15
15
ns
id(CASH)
Delay time, column address to first SC In ear!y-loed
transfer read cycles
tASD
25
25
30
ns
id(CAGH)
Delay time, column address to ffiG high In real-time
transfer read cycles
tATH
20
20
20
na
m
low to column address valid
30
15
35
15
40
ns
tq(DCLt
Delay time, data to ~ low
tDZC
0
0
0
na
idlDGLl
Delay time, data to TRG low
tDZO
0
0
0
ns
id(MSRL)
Delay time, last (most slgnlfipant) rising edge of SC to
RAS low before boundary switch during split-reglstertransfer read cycles
15
20
20
ns
id(scasF)
Delay time, last (127 or 255) rlalng edge of SC to aSF
awltchlng at the boundary during aplit-register-transfer
read cycles (see Note 22)
taaD
20
25
30
na
id(CLaSF)
Delay time, CASx low to aSF awltchlng In transfer
read cycles (see Note 2222)
teaD
25
30
35
na
id(GHaSF)
Delay time, ffiGhlgh to aSF switching In transfer read
cycles (see Note 2222)
!TaD
20
25
30
ns
id(RLaSF)
Delay time, RAS low to aSF switching in transfer read
cycles (see Note 2222)
tROD
65
70
75
ns
trflMAI
tt
R~htimelme~,memory
tREF
8
ms
Transition time
50
ns
!T
8
3
50
8
3
50
3
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 19.
20.
21.
22.
Real-time load transfer read or late-load transfer read cycle only
EarIy-loed transfer read cycle only
Full-register (read) transfer cycles only
Switching times for aSF output are measured with a load equlvalem to 1 TTL load and 30 pF, and output reference level 18
VOH /VOL = 2V/O.8 V.
~ThxAs
5"110
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON. TEXAS 77261..,1443
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS160D- AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
1
RAS
~
1
14
"
r
~~
~~
~(RLCtQ
--~N
" ~(RtQ -.l\'-__
' _
V~
!+-
I
1 , ,
I+- ~(CLRtQ --.I I I
~ ~(RLCL) -+I
1I
Ii4t- ~(CHRL) 14
CASx w# I t
~~
'll1 I,
I i ~
~
~(RLCA)
!'III
th(RA) ~
M-A>
I
1 .,
tt -+I 1
lsu(RA)
~
~
-+I
!+-
, ,.. I
, ,'" 1
~ I
I'
.,
,4, ,
--t-MI
II I, IIXj+- ~(ctQ --..I)~'\.......- -
1 ,
C
k
~(CL)
, , , ,
~(CARtQ
~
--+j , , ,
, , , ,
, , , ,
"fl(RL, A) ---rJ
~
'lsu(CA)
I I
-.! ~
~,(CACtQ
.,
"."
I' ,
"'(CLCA)
~ :+~ ~"'~71!'.~'""""
~~~'"'""'"'~~~
lsu(SFR)
-+!~
tau(!,RO)
+I
r-
"'(SFR)
,
I
"
... ~:i_
II
i4t
I,
_ wwJ~
~G .~
I
,.
,
I 1 ~ IcI(CLGtQ---+i,
I I I
I~
I I ,
.11'," ~(OLRtQ
~14:::'1w(nI0).!,I ~
1
~,
I,
,
I
I
I
I
!
, Isu(~
~:
WEI
~(DGL)
DQO-DQ15
,4
Data In}
I~
I
,1
I
,4
,
"
j+
I I
I" ~
'"
~
lh(RHrd)
~la(CtQ
tacO)
+I
~
,I
I~
I~
! 14
.,
I
~
.......
~
11+ ~la(O) -+i1
Data Out
)>-----
ta(e)--+l
,4
ta(CA)
ta(R)
~
.,
Figure 24. Read-Cycle nmlng
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
5-111
TMSSS160
262144 BY 16-BI1
MULTIPORT VIDEO RAM
SMVS18OD-AuGUST 1892 - REVISED JUNE 1_
PARAMETER MEASUREMENT INFORMATION
Figure 25. Early-Wrlte-Cycle TIming
Table 6. Early-Wrlte-Cycle State Table
STATE
CYCLE
1
2
WrIte operation (nonmasked)
H
WrIte operation with nonpersistent wrHe-per-blt
WrIte"operatIon with persistent wrHe-per-b1l
L
L
Don' care
Write mask
care
~1ExAs,
5-112
.
INSTRUMENTS
POeT OFFICE BOX 1443 • HOUSTON. TEXASn2s1-1443
eon,
3
Valid data
Valid data
valid data
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVSI80D-AUGUST 1992-REVlSEDJUNE 1995
TRO
~ 11
I I1 104104
104
1
h
I
1 1
1
111
i.t-+i.r
tcI(OHD)
-+! 1 1 teu(WMR) 1
WE
=~nxxJ
~._
teU(DQR)
DQO-DQIS
1
teU(WCH)
It!(CLW)
--+I
~I
U
teu(DWL) ~
+jill 1
1 -+i
It!(RDQ) 1 I
1 1041
11
I+-
~
:mm
1
1
1
~I
th(RLW)
104
It!(WLG)
L, N~r4___
1
I ~I
teu(WRH)
-+i 14+ teu(TRG) I
1
i4-~
I
1
1
~I
..J~
~.r::_~~~~~~~~~
tw_(W_L)_ _ _
It!(WLD)
.
--+I
It!(RLD)
1
~I
3
Figure 26.· Late-Wrlte-Cycle Timing (Output-En able-Controlled Write)
Table 7. Late-Wrlte-Cycle State Table
STATE
CYCLE
1
H
2
3
Don't care
Valid data
Write operation with nonpersistent write-per-bit
L
Write mask
Valid data
Write operation with persistent wrlte-per-blt
L
Don't care
Valid data
Write operation (nonmasked)
~1EXAS
INSTRUMENTS
POST. OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
5-113
TMS55160
262144 BY 16~BIT
MULTIPORT VIDEO RAM
SMVS180D- AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
~
~
'N '
- -.......'
~II
AO-AS
tct(CHRL)
~
tct(CLRH)
I
.
~
~/L!
tw(CL).
II
-{.I I+-
1t!(RA)
leu(RA)
•
.r.t-.
I j4 I
Rlfrellh Row
~:1
.
I I
-+I ~ leu(SFC)
144 leu(SFR)
I I
I I r..-:-- It!(RSF) ----;+I
_I
~
-H
It!(SFR)
DSF
r.-
I
I
I
I
I
I
I
I
tw(CH)
I II" ~I1 ~
~II~'I
~
It!(TRG) I·
---i
1+
Ii.
~II
--.r W
I ~I
leu(WMR)
I
1t!(RWM)
1
I"
t-+l
I+1 1I
~
I
. "
I~I[
I
I
I
I..
. .
I
I
~I
I
~I
I
I"I.. 1II III
I I I
I
IJ..
~ rt
leu(WCH)
leu(WRH)
~I
It!(RLW)
.
I
~l
th(CLW)
1
leu(WCL)
tw(WL)
_
.
I I
. -.r I4f- leu(DCL)
I
I..
lh(CLD) -..r
I
"ICI"~~~~~~(
It!(RLD)
~I
WrlteM..kt
~
t Load-wrlte-m..k-reglster CYQIe puts the device Into the persistent write-per-bit mode.
Figure 27. Load-Wrlte-Mask-Reglster-Cycle Timing (Early-Write Load)
~1ExAs
5-114
~
---+j
~II~II
leu(TRG)
DQO-DQ15
...j~
~I
I I
I
I. ~I I
I
I -+I I+- tt
I
I ~ tct(CHRL) --.r
tct(RLCH)
r.- tct(RLCL) -+I
--:!l ~
,
V/.-'w(RH)
-.-...I 141
tt -., t+
I
~
~
tw(RL)
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 11!XAS 77251-1443
•
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVSl80D - AUGUST 1892 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
104
_ _--.il 104
N
1 104
It -+I j4-
~ Io4t
~I
~I
tcf(RLCH)
tcf(CLRH)
101IIII
I
I
tcf(CHRL)
I
i I+-+I
vww9 I
104
'ttlU i l l -~ I+11
1
CASx
~I
tc(W)
tw(RLJ
tw(CL).
1'+1
fAG
-+I
1
;+-- "'(RSF) ,--.j
--+I
I
1
.
"'mII '@N'IQoQ,Q.:lr,I-+,_....lII_~~~~~~~~~~~~~
I r
i ~_=
wr
104-
~!
I
~II
I
104
1
I"'"
104
I
teu(WMR)
i
~
MNW'
~
1
1
~I
1
~I
th(RLW)
I:'
th(WLG)
NI !--_ _ _ _ _
I
tw(WLJ
1
teu(DWLJ
~I
teu(WCH)
"'(CLW)
I
1
~b"'(RWM)~
r--1
i
I1 ~I
teu(WRH)
II..
~ tcf(GHD) - - . ,
DQO-DQ15
1
I
-+' 14+ teu(SFC)
j4f
-+j ~ teu{1'RG)
I
I,
WE
1
tcf(CHRLJ
~~
teu(SFR)
DSF
j;f-i
tw(CH)
"'IRA)
AD-AS
-+I :
~
-+\
tw(RH)
I ~. I+- It
JytJr-+i- - - -....~
-,I ~ 1I
~I ~
tcf(RLCL)
1
01 ~
1
-r.:I ~
1
1
~
1
I
I
1
1
'~!
~
~
--01~~~~~~~~~
~ 1h(WLD) --+I
~~""
~
I
WritaMaakt
.:~
t Load-wrJte.mask-reglster cycle puts the device Into the parslstent write-par-bit mode.
Figure 28. Load-Wrlte-Mask-Reglster-Cycle Timing (late-Write Load)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON, l1!XAS 77251-1443
5-115
TMS55160
262,144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS160D -AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
10lIl
_---iF
~~
~
CASx
I
1111
~
td(CLRH)
lw(cL)
~ ~ Ici(CHRL)
~lI lh(RA~~ I'~C
Iw
~'II
I
!.--L
11-
·ih
+1,~~~
.:=0
Ici(CHRL)
, I+--Ici(RLCL)
W 'I
I!OI I
.1
tc(rdW)
C
14tfeU(CA)
I ~
to.
I
(H)
_IOiII-lh(CLCA)
II
II
'fI(RLC~~
~~~~~~_~!~i ~
AO-AIJ
~ .~ ~ ~olumn
I ~lh(RSF)
-+I jIIIt feu(SFR)
th(SFR)I
~I
"III
-+I
,I .1
I I+-+I--ltJ(SFC)
,0lIl 1 . I !-u{SFC}
"
.
.
II
~11~1111~
bSF~11
IL
~
. . - th(TRG)
I I
I I
I
I
-+II
th(RWM)
WO
DOG-DQ"
*'- feu(WRH) -+I
I
I
lh(WLG)
I
th(CLW)
I II
I
I 'th(RLW)
110lIl 1
feu(TRG)
I 10lIl
I ,
II
'~I'.~~~~~~
~I
~l
~ feu(WMR) IIJ
hiI '0lIl I
Ici(CLWL) ---+I '
I
I..... , 1Ici(DCL) I
'
I
~l II I
!I
~I I ~(CLGH) ll'w(WL) -J~
. I I
I jOlll
MW!:.
iii ~1CA1
,= ~iIi
~I
-+I
~ feu(WCH)
.
~I
I 10lIl I I' Ici(CAWL)
~I
I I
10l
I
l
~I
_tw~(TI,;,;R~G
..
) _+I-+-_--:II~~~~~~~
I
I #"
, I I
, I I
-J I.t.
I
~I
I feu(rd)
r:::-
liOlllI
i'{
1
l1li+ feu(DQR)
10lIl
Ici(RLWL)
~!
Ici(DGL)
-+j 1+
:0lIl
~I
,
lh(WLD)
~
I
Ici(GHD)
~ ~~ ~;: ~ ~~~ ~
fe(G)
'I
+II+-
~
1ci1.(G)
Figure 29. Read-Wrlte-/Read-Modlfy-Wrlte-Cycle Timing
Table 8. Read-Wrlte-/Read-Modlfy-Wrlte-Cycle State Table
STATE
CYCLE
1
2
3
Write operation (nonmssked)
H
Oon'tcare
Valid data
Write operation with nonpersistent wrlts-per-blt
L
Wrltemssk
Valid data
Write operation with persistent wrlte-per-blt
L
Don't care
Valid data
~1ExA.s
5-116
INSTRUMENTS
POST OFFI(lE BOX 1443 • HOUSTON, TEXAS 772&1-1443
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS18OD-AUGUST 1992-REVISED JUNE 1895
PARAMETER MEASUREMENT INFORMATION
14I I
tw(RH)~
""~r----------tw(RL)P ----------~~
IX~
.......
I
feU{RA)~
I
:+-
tct(CHRL)tct(RLCL)
~ tct(RLCA) ---J
I~
tct(RLCH)
~1+ It!{RA) ij(CA) I~
I
I I
I~
I
I
I
It!(RLCA)
It!(CLCA)
I
I
It
I
I
I
I
U==~ 114-~--- tc(P)'
·1
rf'-l.-
~
tct(CLRH)
I~
I
I+- tct(CACH) --+j
I tct(CARH) ---+!
L1'I:1~~~~
AO-Aa
Column
I
I I~
.1
It!(SFR)
.1
I~
I I
I
I
II
I
I
II
II
tct(CLOH) I
-+' ~feU(sFR)_1
DSF
~II
I
-II
II~
TAO
-" 14
W
I I
I I
.......
I~
WE
j4ffeU(WMRl
rtf
tct(DOL)
I
I
I
I
I
I
feU(rd)
II
I
I
II
I
I
----~
Data In
I
I
I
I
I I~ .1
I~
DQODQ15
.,It!(TR0)
feUCTRO)t\'
I
I
I
I
I
II
I
I
I
.1
I
I
I
I
I
I
~
I
I
I
~ta(C)
I+-ta(CA)~
I+- ta(O)
t---+1
ta(R)*
1 .1
I
I}-------t---{
I
I
I
I
I
I
I
I~
!¥Iif
I
It!(RHrd)
I
II
I+- ta(CA) t ~
ta(CP)t
Data Out
I
I
I
I
I
I
I
-.I
I
I
I
I
I
1 ' - tctIS(O)
Data Out
I
~ tct(DCL) ---.I
*t
Access time Is ta(CP) or ta(CA) dependent.
Output can go from the high-Impedance stata to an Invalid data state prior to the specified access time.
NOTE A: A write cycle or a read-modify-wrlte cycle can be mixed with the read cycles as jong as the write and read-modify-write timing
specifications are not violated and the proper polarity of OSF Is selected on the failing edge ofAAS and CASi to select the desired write
mode (normal, block write, etc.).
Figure 30. Enhanced-Page-Mode Read-cycle nmlng
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
5-117
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS160D -AUGUST 1992 - REVISED JUNE 1995
RAS
-.I
CASx
teu(RA)
if
PARAMETER MEASUREMENT INFORMATION
'I
~(RLCH)
IcI(RLC~
I:
!+t IcI(CHR~
I
14-,.. 1h(RA)
I I :"
AOM~ I
-+I
I
.
i=-1h(SFR)
~ I I teu{TRG)
IcI(RSF)
1
~~~5~
I :~
1
I
I
I
I
I
I
.1
.1
. I
~ ~II~
~
.1
"'....
teU
2
=
I
I
.:
Ih~FC)
~I
~
(SFC)
,
A
teu(WCH)
I+tw~ -+!
".¥i~~,QQQ
I
I~
11
. _
I
I I
I
th(SFC)
14- teu(WCH) -+I
~
; :(CARH)
~OIUmn
1
:::
.
I
:
-+: _14-
,
~ tsU(WR~H)~~~~~,",
~II~~
3
~
teU(DC~t I~
i+-1h(RDQ)
,,~.
I
I I
-+j
I I
I
:
~U(WMR)
I : :~ 1h(RWM) ~
Ih(CLCA)
~!. ~
I:
tei.;-;-CI
't
,
'~14- Ie(G)t,
1
teI(~GL) -+I I+- I teI(GHD) -1+-+1
i+- ta(R) t --+I
'I valid Out
" -+I ~ tells(O)
-+II+-
Ie(e) t
t Output can go from high-impedance to an invalid data state prior to the specified access lime.
NOTE A: Aread or a write cycle can be Intermixed with read-modify-wrlte cycles as long as the read and write timing speciflcatlonure not violated.
Figure 32. Enhanced Page-Mode Read-Modlfy-Wrlte-Cycle TIming
Table 10. Enhanced Page-Mode Read-Modlfy-Wrlte-Cycle State Table
STATE
CYCLE
1
Write operation (nonmasked)
L
Write operetion with nonpersistent write-per-bit
2
L
L
L
3
H
4
Don't care
5
valid data
L
L
Write mask
Valid data
Write operation with persistent write-per-blt
L
Don't care
valid data
L
Load-write-mask register on either the first falling edge of
H
L
H
Don't care
Write mask
CASx or the failing edge of WE. whichever occurs later.*
Load-wrlte-mask-register cycle sets the device to the persistent write-per-blt mode. Column address at the falling edge of OAS'"x Is a don't care
during this cycle.
~TEXAS
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON. TEXAS 772a1-1443
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TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVSl60D -AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
~
_ _ _......1 104
~~(
Icf(CHRL)
CASx
;L..
I 1
-HI 1 1:+-
1
1ti(RA)
1
~II
I
lcf(cLRH)
IN""
~II
~I -+If I+I.-
Icf(RLCH)
'4
.....
I .~
I+-Icf(RLCL) -+I
-+I ~
'4
iiitti
1
~
iA
I ~104
It ~
~
~I
tw(RL)
"---(CL)
J
ow
..,
!+t""",
vt
1
I
I
1
I~
1
1
-+I
1
I
Icf(CHRL) --.I
1
I fl... I
1
tw(RH)
It
tw(CH)
1\-
.I
AD-A>
lau(SFR}
OSF
+I
1 104
~
Iti(RSF)
-+t!4+ lau(SFC)
1
1
~t4" .._ I I ·
~
~·IIJroo
"'~iiVi_
~ M-,,"(IRG)
'i'RQ
X)\)Q\J7. I I
i
I~
~: II
IIIIII+-t- tcI(QHD) - + 1
I
I~
-+t I4t t.u(WMR)
I
... W
I
!
I
I
14
I
I
I
'4
'
I~
t.u(WRH)·1
t.u(WCH)
.1
.1
lh(RLW)
1
1
I~
! i't
~
.11 'I
th(CLW)
t.t
lh(WLG)
1
i~
.1
1
I
I
.1
~~
Iw(Wll
t.u(DWL)
I I ~lh(WLD) ~
I 1lh(RLD)
~ii ~
.1
valid Color Input
~
FIgure 34. Load·Color·Reglster·Cycle nmlng (Late-WrIte Load)
-!!11ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
5-121
TMS55160
262144 BY 16-BIT
MULTIPORTVIDEO RAM
SMVSl60D -AUGUST 1992 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
I~
tc(W)
_ _.....1 14
tw(RL.)
.t
:~r
i 1;
tii' ~
teI(RLCA)
.i'4
teI(RLCA),
fau(RA)
...,
teI(CHRL.)
f'II
,
1
;vt;: tw(RH) ~'--
tt..t"4
I+teI(RLCL.)
CA§i
.1
teI(RLCH)
., ...,
0I
(CLAH)
N~
,
tw(CL.)
.1 1 ,
,
,4 . ."""
~'
,
,
,
teI(CHRL.)
-.I,
J\...
j+t- tw(CH) -+j
I I
~ li1(RLCA) ~
~
~ tt
tel'.'
t++-,~I
teI(CARH)
~"
'teI(CACH)
~~~
~
~ ~\Q_,Q,Q,IIoQQoo~,Q,Q,IIoQQoo~~IoQQoo~,Q,Q,IIoQQoo~~
AD-AS
I'"'T
-.! I t+-- teI(RSF). -+I
,f4T
1 I ,
I
li1(SFR) ,
14- ~
faU(SfC)
1111
fau(SFR)
1.:
rr
'II+-i_
m,i IllIIIlI,1
DSF
-+I
Block Address
A2-AS
,
I
I
I
I I
m~
'i'RG1W,,~
, I
fau('1'.BG
fa
u
-!.! w..
t
h(RWM)II'~
(ViM -+I ~ I
I
R),
'II
'4
I ,
II'
-.1I4 It+,
I I
,4
i4}
I
-+I
,4
lh(RDQ) I~
DQO-DQ15
~
14-
I
~
I
th(CLW)
~I
--~~I
Ilh(RLD)
t..t
1
fau(WRH)
faU(WCL.)
WE~II~~
faU(DQR)
.1
fau(WCH)
fau(DCL.)
I4--lh(CLD)
~
.,
i
3
I
_
Figure 35. Block-Wrlte-Cycle TIming (Early Write)
Table 11. Block-Wrlte-Cycle State Table
STATE
CYCLE
, 1
Block-wrlte operation (nonmasked)
Block-write operation with nonpersistent write-per-bit
Block-wrlte operation with persistent wrlte-per-blt
Write-mask data
0: 110 write disable
1: 110 write enable
Column-mask data OQI- OQI+3
0: column write disable
(I • 0, 4, 8, 12)
1: column write enable
H
L
L
-!I11ExAs
5-122
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77251-1443
2
3
Oon'tcera
Write mask
Column mask
Oon'tcare
Column mask
Example:
OQO - column 0 (addreas A1
001 - column 1 (addreas A1
002 - column 2 (addreas A1
003 - column 3 (addreas A1
Column mask
• 0, AD • 0)
.0, AD. 1)
• 1, AD • 0)
• 1, AD • 1)
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVSl80D -AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
~~
_ _-oil 1l1li
N,~
It'" ; :
CASx
! ~IIIII
I I+--
lltU
N
th(RA)
tw(CL)
I I
tta(RLCA) --.j
"j+I II1II-
111
1l1li
~
L.!
f"1
1
1
I I .-
1
tct(RLCA) 1 1l1li
AO-AS
tct(CLRH)
II1II
~~ tct(RLCL) -+j
t4
tcI(C~ i
---.J
1
tcI(CACH)
I
lIT
1 j4-
~I
tct(RLCH)
j4-
~
~I
iw(RL)
~
tw(RH) ,
14- It
L
I
~ tcI(CHRL) -.I
JI
,
J'--
-f iI_!I
~
----.I
1 iiw(CH)
1 ~I
1 1
tct(CARH)
leu(CA)
leU~IIIIII_:::
~~tta(RSF) ~
BlockAddress
I
I
I_I
i"i
leu(SFR) ~
-+I
I4t
leu(SFC)
I
A2-AS
I
-rI W
!IIII---t'!- ~
~II~I11
I
~ i4" leu{TRG)
1
1
1
tta(SFR)
DSF
ill
illll
~ tct(GHD) -+I
1 1l1li
1
I
-.I
I.}leU(WMR)
'-+j 14- It!(RWM) 1
I
11
~
ih(RLW)
1l1li
1l1li
.,
leu(WRH)
ih(WLG)
~
1
,
.1
,
11
I I
1l1li1
I~I----------~~~~~~~~~
leU(DWL)
t' 1+
,
~ II1II- ih(RDQ)
I
I1 I1
1 Ni+--tw(WL)-----+j.~~-~--~
-, iIIIIt leU(DQR)
I
I~
.'1
It!(CLW)
~ leu(WCH)-r
I.- ih(WLD) -.I
ih(RLD)
~I
~3_
DQO-DQ1S
Figure 36. Block-Wrlte-Cycle Timing (Late Write)
Table 12. Block-Wrlte-Cycle State Table
STATE
CYCLE
1
2
3
Block-write operation (oonmasked)
H
Don't care
Column mask
Block-write operetion with nonpersistent wrIte-per-bit
L
Write mask
Column mask
Block-write operation with persistent write-per-bit
L
Don't care
Column mask
Write-mask date
0:
va write disable
1: I/O write enable
Column-mask data 001- 001+3
0: column write disable
= 0, 4, 8, 12)
1: column write enable
o
Example:
DQO - column 0 (address A1 .0, AD •
001 - column 1 (address A1 0, AD
002 - column 2 (address Al • 1, AD •
003 - column 3 (address A1 • 1, AD •
=
0)
=1)
0)
1)
~ThXAS
INSTRUMENTS
POST OFFICE BOX 14043 • HOUSTON. TEXAS 77251-1443
5-123
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS180D-AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
14
AU
CASx
tw(RL)P
~
I 14
a
i-t ""'H.~
II 1
II: 14i4I
".,
~
1/
~I
~ ~
I
I 14
~I
, -
I:'"
1
I+-
1 ~I
I ~II
.
Ih(CLCA)
1
14
/
II
II
1
1 I
~
,
I
--I
Id(CACH)
~tw(RH)
I
--.:
,.
j\.1
f
1~
I
....
(R
I
"II LCA)
Id(C~H)
tw(CH) --.j , . -
1 tw(Cll
i1
~ 1
~I
tc(p)
14
I I+-
NI
I4-Id(RLCA)-.J
tau(CA)
Ih(RA)
.1
Id(RLCH)
Id(RLCL) - - . :
~I
I
Id(CARH) - - . j
_AI ~,' ~~ ~ ~~~~ ~ :7-~
~
I+-Ih(SFR)
-+t
~!
DSF
1.+,
1
tau(SFC)
X"x"l& I I
1ItT
II t t+i ....-- Ih(TRG)
- if rr\~
_II)
-.: *I
Ih(RWM)
IIII14
WE~::1
oJ
1 1
....., I+t
~~5
II
~
I j+- Ih(SFC) -.I
Vi
I I
I I
I I
'.;::,I .,: "'_A
II 1
,141
I
~I
:
:
I+- _
1
~I
I..
tw(WL)
tau(WRH)
I
th(CLD) t
I4t- Ih(WLD)t --.I
~ tau(DCL)t
1+ "'(RDQ) -.:
~ Ih(RLD)
2
~
~!I
~~
-toI14f 14----+I
tau(DWL) t
tau(DQR)
14
I
I
~I
I
.
1 I
I
I
I
tau(SFC)
I
I
I
"'(Well)
~
Ih(SF~ --.I
I
j+-.i-1 1I 1 -I+-M-
II·
tau(SFR)
,~
3
I
~
~
3
~
t Referenced to the first failing edge of -aASx or the failing edge of WE, whichever occurs later
NOTE A: To assure page-mode cycle time, fRG must remain high throughout the entire page-mode operation If the Iate-wrIte feature 18 used.
If the early-write cycle timing 18 used, the state offRG 18 a don't care after the minimum period lti(TRG) from the failing edge ofFiAS'.
Figure 37. Enhanced-Page-Mode Block-Wrlte-Cycle Timing
Table 13. Enhanced-Page-Mode Block-Wrlte-Cycle State Table
STATE
CYCLE
1
2
3
Block-wrlte operation (nonmasked)
Block-write operation with nonpersistent wrlte-par-bit
H
L
Don't care
Write mask
Column mask
Block-wrlte oparation with persistent wrlte-per-bit
L
Oon'tcare
0: I/O write disable
1: I/O write enable
Column-maak date 001 - OQI+3
0: column write disable
Q• 0, 4, 8, 12)
1: column write enabla
Wrlte-maak dsta
~TEXAS
5-124
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
Column mask
Column mask
Example:
OQO - column 0 (addraaa A1 •
001 - column 1 (addreaa A 1 •
002 - column 2 (addraaa A1 •
003 - column 3 (addraaa A1 •
0, AD •
0, AD •
1, AD •
1, AD •
0)
1)
0)
1)
TMS55160
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVSl60D- AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
K
lcI(CHRL)
11
1 tc(rd)
10IIII
~~
-+l 1I+- tt
1
I
-+I~~~.i 1
lcI(RHCL)
~"
.1
L
/+-1w(RH) ~
1 1
1 I~.I
~I 1
...... j4- lcI(CHRL)
.~~~
=====;:=;:
11
teu(T'RQ)
I~.
I
DQODQ15
Figure 38. RAS-Only Refresh-Cycle Timing
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 772&1-1443
6-125
TMS55160
262144 BY16-BIT
MULTIPORT VIDEO RAM
SMVS180D-AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT. INFORMATION
I~
AI+--
---'
.
tc(rd) -------~~I
~\l.~
tw(RL) ---~~U
IcI(RHCL) I ,Il...-_______-+-'!I I+-lt
tw(RH)
!~~I
IcI(CLRL)
CASx~I
I~
~I ~ IcI(RLCH) -+I
\1.
I4--IcI(CHRL)
I~
""~~""""~"""'"""~
tau(RA)
AO-AS
V
II
I ,
--+I, ,
,
~I !oIIII1~1---t~"-1-
t!i(RA)
.
i i
tau(SFR) -+1~
__-.r~1
141~1---t~*"1-
Iti(SFR)
DSF~:':~
DQO-DQ15
'
Figure 39. CBR-Refresh-Cycle Timing
Table 14. CBR-Cycle State Table
STATE
CYCLE
CBR refresh with option reset
CBR refresh with no reset
CBR refresh with stop point set and no reset
1
2
3
Don'lcare
H
Don'lcare
L
H
Stop address
H
L
~1ExAs
5-126
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
H
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS160D- AUGUST 1992 - REVISED JUNE 1995
+
PARAMETER MEASUREMENT INFORMATION
!+" Memory Read Cycle
: . - fc(rd)
I
lw(R1:I)
.:II1II
Refreeh Cycle
t
,II1II
I
I
~
tw(RH)
-;",IIIIIt----.!.1
I
I I
I
I
I
I
:I 1.,...'
~i
I II II
I I _ i~
: tcI(RLCA)
I
I I~ ~taU(CA)
-y.j ~th(RA) -+I
-+f ~
I
AO-AS
:
I
I ~ th(RA)
'I I
tau(SFR)
I I
I ,II1II
I I
tcI(RLCH)
I:
II
I
~ tau(RA)
!~
I I
-.: I"-It
I
-+I
I
I
I I
tau(RA) II
JX-I:~
i
S'j
I~II tau(RA)
.1
I I
I
___!.!..
._1
I:
I ~ th(RA)
I I
I
I I
I
I
i-L::A)I
I
I
I
I
I
~ ItI(RA)
I I
I
I
I
I
I
~:': ~',' ~~~~Ido~~
I -+! ~
~ f ~~(SFR) -+: If
'I
DSF
tw(CL)
I
IIIIIII-ItI(CLCA)
I
·1
fc(rd)
~
tct(CARH)
I
---+j
.~ f c ( r d ) . 1 . - -
,II1II
~T }t ~N ~V
.It
-+!
tct(CHR~
'fj
_. I iN'1 ! !i
:)
!lllll+1
Refresh Cycle
tau(SFR)
~IC_I~ ~~I;.
~th(RHrd)
-+I ~ tau(TRG)
I
I I
y-~ ~I\.~I4T ~
I
I
IiF
tau(rd) ~ I
~
I I
tclIT(CH)
I :I
t,h(TRG)
tcI(GLR~
I
I
I'
~ jIIIIIf- tau(WMR)
I~
II
-+I ~
I
I *+I
II
,,11:
i,
11111'
tclIS(G)
___
I
~ tau(WMR)
-+! ~ tau(WMR) I
W *'r~} ~""••~",J ~-
I
WE~I~~~~~. ~ • ~~ ~~
I
~~~
DQODQ15
--------~{~i__________________D_am__
Ou_t____
I
~~:~----------}--
Figure 40. Hldden-Refresh-Cycle Timing
Table 15. Hldden-Refresh-Cycle State Table
STATE
CYCLE
1
2
3
Don't care
Don't care
L
H
H
H
Stoll address
H
L
CBR refresh with option reset
CBR refresh with no reset
CBR refresh with stop point set and no option reset
~1ExAs
INS{RUMENTS
POST OFFICE BOX 1_'- HOUSTON. TEXAS 77251-1_
5·127
TMS55160
262144 BY 16-BIT
MULTIPaRT VIDEO RAM
SMVSI60D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
,.
-----..ir:
I 14
tw(RL)
IcI(RLCL).
~I ~I-
te(TRD)
~I
.,
I
~I
~tw(RH) - - - - . \
I
i
----1 N--
~I
""'-"--
IcI{RLCH)
-I
IcI(CHRL) -+14f----.!1 I
. I4-l-IcI(CARH) ~
I
II
II
~ IcI{RL~A)
tw(CL) ~
wvwJ,
~1ExAs
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON. TEXAS 77251-1443
5-131
TMS55160
262144 BY 16-BIT
MULTIPORTVIDEO RAM
Sr.iVS180D -AUGUST 1992 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
~~---tc(SC).
lw(scH)
SC
_I~_ _~~
~
..
~
.l
/f
- - - - - ' j4
--.!~I
~
(SHSQ)
'\l
~
I
I
--------~)
'---
r-1a(SE)
i4~-'I-I-- ....(SHSQ)
J p - - - - - - - - - . i . Jp-_ _ __
Valid Out
~ tells(SE)
I
.j.
~L..-"'-Ia(SQ)
r
Ia(SQ)
Valid Out
I
I
I
Vl't-I--...c.\
~I ~
~
I I
~14----I~M-Iw(ScH)
.l. rI4-Iw(SCL) ~
Ia(SQ):
I
I++..
I
~~--~~If-Iw(SCH)
\L~ Iw(SCL) ~0
~
~
tc(SC)
I
10
_ _ _ _ _, I
SQ·
I'll,
.1
Valid Out
I "'----------' "'-----I
I
I
~~:----------------
NOTE A: While the data Is being read through the 88r!aklata register, ~ Is a don't care except'mG must be held high when RA! goes low.
This is to avoid the initiation of a reglstar-data transfer operation.
Figure 45. Serial-Read Timing (SE-Controlled Read)
~1ExAs
INSTRUMENTS
5-132
POSTOFFlCE BOX 1443 ·,HOUSTON. TEXAS 772&1-1443
TMS55160
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVSl80D- AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
, '--_--'-r-""""\.\-_--Jr,',
I
~~~
::x::::x:::J<---I-.. .
RowTap1
(low)
'i'RG
DSF
n~T--
\.
~~T__
CASx
ADDR
I
I
(hIgh)
I
(low)
' - '----I'~\.J--~'j~~T-I
I
-----if----JI\\--~,,~~T__
I
I
I
I
CASE I
Ta P1 1
(low) I
I
I
I
I
'II \
I
I
I
I.
(low)
127
S".....r
I
I
I
(low)
1271 (high)
"
---..Jo\--t---------'l'<-.J
I
I
I
CASElli
se
255
------..I---~~~~
I
1
aSF
S'
127 (hIgh)
--~\-__TI----~SHt
CASE II
SC
I
I
I
I
~II
Tap1
~II
Bit
Tap2
~
SC
QSF
\t==
(hIgh)
255
j~
" II
I
I
I
I
I
I
(low)
127
,.,r---r
\
-------;.I----.
. . Q-s~~~
I
I
(low)
1271 (hIgh)
255
--+I-----~sH'
',S
QSF - - - - \.....
Full·R.gl.te....Transfer Re.d
I
I
I
Spilt R.glat.r to the
High H.lf of the
Data Regl.t.r
I
I
1
Split Reglat.r to the
Low Half of the
Data R.gl.t.r
II \
I
I
(low)
127
',,,.....r
Spilt R.gl.ter to the
High Half of the
D.ta Reglater
NOTES: A. In order to achieve proper spllt·reglster operation, a full·reglster-transfer read should be performed before the first
split-register-transfer cycle. This Is necessary to Initialize the data register and the starting tap location. First serial access can then
begIn either after the full.reglster-transfer-read cycle (CASE I), during the first split-reglster-transfer cycle (CASE II), or even after
the first spllt-reglster-transfer cycle (CASE III). There Is no mInimum requirement of SC clock between the full-regIBter-tranafer-read
cycle and the first spllt.reglster cycle.
B. Asplit-reglster-trensferintotheinactlve halflsnotallowed untilldIMSRL) is met.IdIMSRL) Istheminlmum de/aytimebetweentherlslng
edge of the serial clock of the last bit (bit 127 or 255) and the falling edge of RAS of the spllt-reglster-trensfer cycle into the inactive
half. After the Id(MSRL) requirement Is met, the split-register-transfer into the InactJve half must alae satisfy the minimum IdCRHMS)
requlrement.Id(RHMS) is the minimum delay time between the rising edge of RAS of the split-reglster-transfer cycle Into the lnactlv8
half and the rising edge of the sarlal clock of the last bit (bit 127 or 255).
Figure 46. Spllt·Reglster Operating Sequence
~ThXAS
.
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
5-133
TMS55160
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVSl80D - AUGUST 1992 - REVISED JUNE 1995
device symbolization
"¥
Speed (-80, -70,-80)
TMS55180~
F
R
PackagsCode
A!X.!T
I
LotTraceablilly Code
Date Code
AlssmblySlteCode
DlsRevlslon Code
Wa"rFabCods
~1ExAs
5-134
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 'IEXAS 772t51-1443
TMS55165
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS165D - AUGUST 1992 - REVISED JUNE 1995
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
This data sheet is applicable to all TMS55165s
symbolized with Revision "C" and subsequent
revisions as described on page 5-189.
Organization:
- DRAM: 262144 Words x 16 Bits
- SAM: 256 Words x 16 Bits
Dual-Port Accessibility - Simultaneous and
Asynchronous Access From the DRAM and
SAM Ports
Data Transfer Function From the DRAM to
the Serial Data Register
(4 x 4) x 4 Block-Write Feature for Fast Area
Fill Operations; As Many as Four Memory
Address locations Written Per Cycle From
the 16-Blt On-Chip Color Register
Wrlte-Per-Blt Feature for Selective Write to
Each RAM I/O; Two Wrlte-Per-Blt Modes to
Simplify System Design
Byte Write Control (WEL, WEU) Provides
Flexibility
Enhanced Page-Mode Operation for Faster
Access
CAS-Before-RAS (CBR) and Hidden
Refresh Modes
Long Refresh Period
Every 8 ms (Max)
Up to 55-MHz Uninterrupted Serial Data
Streams
256 Selectable Serial-Register Starting
locations
iE-Controlled Reglster-Btatus QSF
Split-Register Transfer Read for Simplified
Real-Time Register Load
Programmable Split-Register Stop Point
3-State Serial Outputs Allow Easy
MultipleXing of Video Data Streams
All Inputs/Outputs and Clocks TTL
.Compatible
Compatible With JEDEC Standards
Texas Instruments EPIC'" CMOS Process
Designed to Work With the
Industry-Leading Texas Instruments
Graphics Family
Performance Ranges:
ACCESS TIME
ROW ENABLE
t..(R)
(MAX)
ACCESS TIME
SERIAL DATA
t..(Sa)
(MAX)
DGHPACKAGE
(TOP VIEW)
BE
vaa
Vss
salS
DOIS
sal4
DOI4
Vee
saIl
DOli
sao
coo
SQI
DOl
Vee
Baa
DQ2
saa
BQ11
ila3
DOlI
Vss
SQII
DOlI
salO
DOlO
Vee
Vss
SQ4
DQ4
SQB
DOS
Vee
SQ8
DQ8
sa7
DQ7
18
11
20
21
22
VSS
23
WEL
WEii
RAi
as
AS
A7
AS
M
A4
Vee
24
28
4B
47
4B
4B
44
·43
42
41
40
38
27
28
211
88
3D
II
315
34
32
33
SQ8
DQ8
SQ8
DQ8
VSS
DSF
NC/GND
CAS
Q8F
37
AO
AI
AI
as
AI
Vss
PIN NOMENCLATURE
AD-AS
~
000-0015
OSF
NOONO
OSF
RAS
SC
SE
SOO-S015
TRG
Vee
~
WEL,WEU
DRAM
CYCLE TIME
DRAM
PAGE MODE
SERIAL
CYCLE TIME
tc(W)
tc(p)
(MIN)
(MIN)
35ns
40ns
45ns
TMS55165-60
60 ns
15 ns
110 ns
TMS55165-70
70 ns
20 ns
130 ns
TMS55165-80
80 ns
25 ns
150 nB
EPIC Is a trademark of Texas Instruments Incorporated.
8C
vee
'iiiG
Address Inputs
Column-Address Strobe
DRAM Data VO, Write Mask Data
Special Function Select
No Connect/Ground (Important: Not
connected Internally to Vas)
Special Function Output
Row-Address Strobe
Serial Clock
Serial Enable
Serial Data Output
Output Enable, Transfer Select
5-V Supply (TVP)
Ground
DRAM Byte-Write Enable Selects
OPERATING CURRENT
SERIAL PORT STANDBY
OPERATING CURRENT
SERIAL PORT ACTIVE
tc(SC)
1cc1
1cc1A
(MIN)
(MAX)
(MAXI
18ns
22ns
30ns
180mA
165mA
150mA
225mA
205mA
165mA
~TEXAS
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON. TEXAS 772&1-1443
Copyright 0 1995. 'IlIxas lnatrumenlllincorporatad
5-135
TMS55165
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS185D - AUGUST 1892 - REVISED JUNE 1885
description
The TMS55165 multiport video RAM is a high-speed dual-ported memory device. It consists of a dynamic
random-access memory (DRAM) organized as 262144 words of 16 bits each interfaced to a serial data register
[serial-access memory (SAM)] organized as 256 words of 16 bits each. The TMS55165 supports three basic
types of operation: random access to and from the DRAM, serial access from the serial register. and transfer
of data from any row in the DRAM to the serial register. Except during transfer operations, the TMS55165 can
be accessed simultaneously and asynchronously from the DRAM and SAM ports.
The TMS55165Is equipped with several features designed to provide higher system-level bandwidth and to
simplify design Integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates can
be achieved by the device's (4)( 4) )( 4 block-write feature. The block-write mode allows 16 bits of data (present
In an on-chip color data register) to be writteh to any combination of four adjacent column address locations.
As many as 64 bits of data can be written to memory during each CAS cycle time. Also on the DRAM port, a
write mask or a write-per-bit feature allows masking of any combination of the 16 Inputs/outputs on any write
cycle. The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent
write cycles without reloading. The TMS55165 also offers byte control. Byte control can be applied In write
cycles, block-write cycles, load-write-mask-register cycles, and load-color-reglster cycles.
The TMS55165 offers a split-register-transfer read (DRAM to SAM) feature for the serial register (SAM port).
This feature enables real-time register load implementation for truly continuous serial data streams without
critical timing requirements. The register is divided into a high haH and a low haH. While one haH Is being read
out of the SAM port, the other haH can be loaded from the memory array. For applications not requiring real-time
register load (for example, loads done during CRT retrace periods), the full-register mode of operation Is
retained to simplify system design.
The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up
to 55 MHz. During the split-register-transfer read operations, intemal circuitry detects when the last bit position
is accessed from the active haH of the register and immediately transfers control to the opposite half. A separate
output, aSF, Is Included to indicate which haH of the serial register Is active.
All inputs, outputs, and clock signals on the TMS55165 are compatible with Series 74 TTL All address lines
and data-In lines are latched on chip to simplify system design. All data-outs are unlatched to allow greater
system flexibility.
The TMS55165. employs state-of-the-art Texas Instruments EPIC'" scaled-CMOS, double-level
polysilicon/polycide gate technology for very high performance combined with low cost and improved reliability.
The TMS55165 Is offered In a 64-pln smail-outline gull-wlng-Ieaded package (DGH suffix) for direct surface
mounting.
The TMS55165 and other TI multlport video RAMs are supported by a broad line of graphics processors and
control devices from Texas Instruments.
~1ExAs
5-138
INSTRUMENTS
POST OFFICE BOX 1_ • HOUSTON. lEXAS 77251-1_
TMS55165
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS165D - AUGUST 1992 - REVISED JUNE 1995
functional block diagram
r--------..,
......~',
,m---Ij'
If!
I_l'BIiiQl
1 of 4 Sub·Blocks
(.ee next page)
OSF
,,
.JI
I'-________
.
,r--------..,,
-.~
,
1 of 4 Sub·Blocks
(.11 naxt page)
OQOOQ15
Column
~.II."-mw~ Buffar
,
,,
,r--------..,,,
,,
,,
,
,
.---..,
9
AD-AS
'-________ .J
1 of 4 Sub-Blocks
(.11 next page)
'- _ _ _ _ _ _ _ _ .JI
SQO-SQ15
16
Serial·
Output
Buffer
r--------..,I
CAS
TRG
Timing
Genarator
Spilt.
Raglster
Status
QSF
IE
AAS
,
I
Refresh
Counter
1 of 4 Sub·Blocks
(saa naxt page)
,
,,
'-_ _ _ _ _ _ _ _ .J
WEx
~1ExAs
INSTRUMENTS
POST OFFICE BOX 14043 • HOUSTON, 1CXAS 77261-14043
5-137
TMS55165
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVSl6SD- AUGUST 1992 - REVISED JUNE 19915
functional block diagram (continued)
OQI
OQI+1
OQI+2
OQI+3
512,,512
Memory
Array
Row
Decoder
sc
SQI ---~~~~23~~~:J8L:~~~~~C:~~<:!:~~~~~
Legend:
1. Refresh address
2. Row address
3. Block address (A2-A8) Is latched on the falling edge of
4. Color-register data
.
5. . Write-mask data: OQO-OQ15 are latched on the falling edge of RAS.
8. Column-mask data: OQI-OQI+3 0 .0, 4, 8, 12) are latched on either the first failing edge ofWEx or the falling edge of CAS, whichever
occurs later.
I
m.
-unuu::uaucu" =don't care
Figure 9. Example of Block Writes
~1ExAs
60152
INSTRUMENTS
POST OFFICE BOX 1443 • HOU8TONi TEXAS 77251-1443
/
TMS55165
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS165D - AUGUST 1992 - REV1SED JUNE 1995
load color register (continued)
I
Load-Wrlte-Maak-Regleter Cycle
I
I
I
I
Load-Color-Reglater Cycle
I
I
I
Peralatent Block-Write Cycle
(u.. loaded write ma.k)
I
I
I
I
~-~
~I'~==~----~~t-~==~----~~t-~==~----/I
CAS I
' ...._ _,.,1
' ...._ _,.,1
,"'--_-..J/-1
DQO-DQ15
DSF
B
~:;;;;:~~:J~::::::~:;;;;:~~;;~::::::~~~~~~;:::::::~
6
Legend:
1. Refresh address
2. Row address
'3. Block address (A2-AS) Is latched on the falling edge of CAS.
4. Color-register data
6. Write-mask data: OQO -OQ15 are latched on the failing edge of CAS.
8. Column-mask data: OQI-OQI+3 (I .0, 4, 8, 12) are latched on either the first falling edge of WElt or the falling edge of CAS, whichever
Occurs later.
• don't care
t'Ulcc!cUlcc!Uc!::CIU!cUt-
Figure 10. Example of a Persistent Block Write
DRAM·to.sAM transfer operation
During the DRAM-to-SAM transfer operation, one half of a row (256 columns) In the DRAM arr~selected
to be transferred to the 256-bit serial-data register. The transfer operation is invoked by bringing 'i'RG low and
holding WEx high on the falling edge of RAS. The state of DSF, which is latched on the failing edge of RAS,
determines whether the full-register-transfer read operation or the split-register-transfer read operation Is
performed.
Table 4. SAM Function Table
CAS
FALL
~FALL
FUNCTION
Full-register-transfer read
Split-register-transfar read
ADDRESS
DQO-DQ15
MNE
CODE
CA§
TRG
WExt
DSF
DSF
~
CAS
RAS
CAS
WEx
H
L
H
L
X
Row
Addr
Tap
Point
X
X
RT
X
Row
Addr
Tap
Point
X
X
SRT
H
L
H
H
t logIC L Is selected when either or both WE[ and WEU are low.
X •
don'tcare
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSlON. TEXAS 77251-.1443
5-153
TMS55165
(
262144 BY 1$-BIT
.
MULTIPORT VIDEO RAM
SMVSl65D- AUGUST 1992 - REVISED JUNE 1995
full-reglster-transfer read
A full-register-transfer read operation loads data from a selected half of a row in the DRAM into the SAM. TFm
is brought I.ow and latched at the falling edge of RAS. Nine row-address bits (AO -AS) are also latched at the
falling edge of RAS to select one of the 512 rows avaiiable for the transfer. The nine COlumn-address bits
(AO -AS) are latched at the failing edge of CAS, where address bit AS selects which half of the row is transferred.
Address bits AO-A7 select one of the SAM's 256 available tap points from which the serial data is read out
(see Figure 11).
512 II 512·
Memory Array
256-BII
Data Regleter
o
255
Figure 11. Full-Reglster-Transfer Read
A full-register-transfer read can be performed in three ways: early load, real-time load (or midline load), or late
load. Each of these offers the flexibility of controlling the TRG trailing edge in the full-register-transfer read cycle
(see Figure 12).
I
fiAt
Earty Load
II
AO-AB,·
TRG
Real-nme Load
r-"\
rr-\.
I . ,
I
CAS
,
\
Row
r\..I
I
Tap
Point
,
I ,
.
~
Row
,
I
Tap
Point
\
I
I
rr-\.
' '-----'.
,
\
,
Late Load
,
'-I
. I ,
,
Row
,
I
Ta~
Point
I \
I
I
II
,
r-1,
WExFv~~~
I
I
+,____
~~IJ
~__
Figure 12. Example of Full-Reglster-Transfer Read Operations
~1ExAs
5-154
INSTRUMENTS
POST OFFICE BOX 1443 •
HOIJS'TON. TEXAS 77251-1443
TMS55165
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVSI65D-AUGUST 1992-REVISEDJUNE 1895
spllt-reglster-transfer read
In the split-register-transfer read operation, the serial data register is split into halves. The low half contains bits
0-127, and the high half contains bits 128 - 255. While one half is being read out of the SAM port, the other
half can be loaded from the memory array.
o
511
512 x512
Memory Array
256-BII
Data Reglater
o
255
Figure 13. Spllt-Reglster-Transfer Read
To invoke a split-register-transfer read cycle, DSF Is brought high, TRG is brought low, and both are latched at
the falling edge of RAS. Nine row-address bits (AO -AS) are also latched at the falling edge of RAS to select
one of the 512 rows available for the transfer. Eight of the nine column-address bits (AO -AS and AS) are latched
at the falling edge of CAS. Column-address bit A8 selects which half of the row is to be transferred.
Column-address bits AO-A6 select one of the 127 tap points in the specified half of the SAM. Column-address
bit A7 is ignored, and the split-register-transfer is internally controlled to select the inactive register half.
RlJi\FUIIXFERj
\SPIItXFERj
AS.O
DRAM
SAM
r-A-..
511
•
'[i~r
g
m m
or@:
0
A7.0t
511
0
C B
SQ
t A7 ahown Ie Intemally controlled.
AS.O
r-A-..
r-A-..
o~
A B
\&PIHXFERr
AS.1
AS.1
r-A-..
0
\SPIIIXFERj
A7 .. 1t 511
o A7=Ot
o~
C D
SQ
511
E D
SQ
SQ
Figure 14. Example of a Spllt-Reglster-Transfer Read Operation·
A full-register-transfer read must precede the first split-register-transfer read to ensure proper operation. After
the full-register-transfer read cycle, the first split-register-transfer read can follow immediately without any
minimum SC clock requirement.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. lEXAS 77251-1443
5-155
TMS55165
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS186D-AUGUST 1892 - REVISED JUNE 1996
apllt-reglat.r-tranafer read (continued)
OSF Indicates which half of the register is being accessed during serial acCess operation. When OSF Is low,
the serial-address pointer Is accessing the lower Qeast significant) 128 bits of the SAM. When OSF is high, the
pOinter Is accessing the higher (most significant) 128 bits of the SAM. OSF changes state upon completing a
full-register-transfer read cycle. The tap point loaded during the current transfer cycle determines the state of
OSF. OSF also changes state when a boundary between two register halves is reached.
Spllt-Reglater
Tranmr Re.d
Full-Reglater-TraII"'r Read
With Tap Point N
\
IW"
/
\1
~
I
Ii1
I
I
1
1
DSF
1
1
/
/
rr:;;"-.
I. II.
Ici(CLQSF)
\
\
/\
1
1
1
SC
/
/
1
\
'fRO
\
PointN
~
~ Ici(GHOSF)
OSF
Figure 15. Example of a Split-Register-Transfer Read After a Fuil-Reglster·Transfer Read
Spllt·Reglatar
Transfer Read
WIth Tap Point N,
III
\
IW"
Spllt-Reglster
Transfer Re.d
mi~
1
1
1
/
I
I
I
DSF~
Ici(RHMS)
,.
/
I
1
1
1
~
\
CAl
~
/
\
\'
I
1
h
~I
Ici(MSRL)
SC
14----....
1-
QSF
lci(ScOSF)
----------------------------~>t;,-------------------Figure 16. Example of Successive Spllt·Reglster.Transfer Read Operations
~1ExAs)
5-158
INSTRUMENTS
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TMS55165
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS185D -AUGUST 1992 - REVISED JUNE 1995
.erlal-read operation
The serial-read operation can be performed through the SAM port simultaneously and asynchronollisly with
DRAM operations except during transfer operations. Serial data can be read from the SAM by clocking SC
starting at the tap point loaded by the preceding transfer cycle. proceeding sequentially to the most significant
bit (bit 255). and then wrapping around to the least significant bit (bit 0). as shown in Figure 17.
r-+I
L
01
11
21
. . • . . 1 Tap
I.........
125412551
I
Figure 17. Serial Pointer Direction for Serial Read
For split-register operation. serial data can be read out from the active half ofthe SAM by clocking SC starting
at the tap point loaded by the preceding split-register-transfer cycle. The serial pointer proceeds sequentially
to the most significant bit of the half. bit 127 or bit 255. If there is a split-register-transfer read to the Inactive half
during this period. the serial pointer points next to the tap point location loaded by that split-register-transfer
(see Figure 18).
Figure 18. Serial Pointer for Split-Register Read - Case I
If there is no split-register-transfer read to the Inactive half during this period. the serial pointer points next to
the least significant bit ofthe inactive haif. bit 128 or bit 0 (see Figure 19).
Figure 19. Serial Pointer for Split-Register Read - Case"
split-register programmable stop pOint
The TMS55165 offers programmable stop-point mode for split-register-transfer read operation. This mode can
be used to improve 2-D drawing performance in a nonscanline data format.
In split-register-transfer read operation. the stop point is defined as a register location at which the serial output
stops coming from one haif of the SAM and switches to the opposite half of the SAM. While in stop-point mode.
the SAM is divided Into partitions whose length is programmed via row addresses A4-A7 In a CBR set (CBRS)
cycle. The last serial-address location of each partition Is the stop point (see Figure 20).
0
I
Partition
Langth
~
,
I
127
I· •·1
1. ..
128
I
1
255
I
I- •·1
1 L..
I
1
Stop
Points
Figure 20. Example of the SAM With Partitions
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TMS55165
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS165D- AUGUST 1992 - REVISED JUNE 1996
split-register programmable stop point (continued)
StOp~t mode Is not active until the CBRS cycle Is Initiated. The CBRS operation is performed by holding CAS
and WEx low and DSF high on the falling edge of RAS. The falling edge of RAS also latches row addresses
A4-A7, which are used to define the SAM's partition length. The other row address inputs are don't care.
Stop-point mode should be initiated after the Initialization cycles have been performed (see Table 5).
Table 5. Programming Code for Stop-Point Mode
MAXIMUM
PARTITION
LENGTH
AS
A7
AS
AS
A4
16
X
.L
L
L
L
X
16
32
84
128
X
X
L
L
L
L
L
H
X
H
H
X
8
4
15,31.47.63.79.95.111.127.143.159.175.
191.207.223.239.255
31.63.95.127.159.191.223.255
63.127.191.255
X
L
H
H
H
X
2
127.255
ADDRESS AT RAS IN CBRS CYCLE
(default)
NUMBER OF
AO-Aa PARTITIONS
STOP-POINT LOCATIONS
In stop-point mode, the tap point loaded during the split-register-transfer read cycle determines in which SAM
partition the serial output begins and at which stop point the serial output stops coming from one half of the SAM
and switches to the opposite half of the SAM (see Figure 21).
RAS
'- _
Full
..
J
\.
",sad XFE.,
Tap_L1·
Tap=H1
H1
X'sad XFE'Y
Tap.H2
191
Spilt _ ~
Spilt , , / , . . - - - , . , .
X'sad XFE'Y
Tap .. L2
63
L1
H2
255
L2
SC ________________~ ••• ~ ••• ~ •••••• ~
SAM LOw Half
0
L1
63
L2
t
1..
f:
127
128
H1
SAM High Half
191
:.
l
..
H2
f
266
.
•
Figure 21. Example of,Split-Reglster Operation with Programmable Stop Points
~1ExAs
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INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
1
TMS55165
262144 BY 16-BIT
MULTIPaRT VIDEO RAM
SMVS165D-AUGUST 1992 - REVISED JUNE 1995
256-/512-blt compatibility o.f split-register programmable stop point
The stop-point mode is designed to be compatible both for 256-bit SAM and 512-blt SAM devices. After the
CBRS cycle is initiated, the stop-point mode becomes active. In the stop-point mode, and only in the stop-point
mode, the column-address bits AY7 and AY8 are internally swapped to assure the compatibility (see Figure 22).
This address-bit swap applies to the column address, and It Is effective for all DRAM and transfer cycles. For
example, during the spllt-register-transfer cycle with stop point, column-address bit AY81s a don't care and AY7
decodes the DRAM row half for the split-register-transfer. During stop-point mode, a CBR option reset (CBR)
cycle is not recommended because this ends the stop-point mode and restores address bits AY7 and AY8 to
their normal function. Consistent use of CBR cycles ensures that the TMS55165 remains in normal mode.
NON STOP-POINT MODE
AV8.0
AV8.1
AY7.0 AY7.1 AY7_0 AY7.1
STOP-POINT MODE
AY8.0
AV8.1
AY7-0 AY7.1 AY7.0 AY7.1
Memory Array
512 )(512
512)(512
Memory AIray
256-BII
258-BIt
Data Reglater
Data Reglatar
Figure 22. DRAM-to-SAM Mapping, Non Stop-Point Versus Stop Point
IMPORTANT: For proper device operation in a spilt-register stop-point mode, a CBRS cycle should be initiated
right after the power-up initialization cycles have been performed.
power up
To achieve proper device operation, an initial pause of 200 !AS is required after power up followed by a minimum
of eight RAS cycles or eight CBR cycles to Initialize the DRAM port. A full-register-transfer read cycle and two
SC cycles are needed to initialize the SAM port.
After initialization, the Internal state of the TMS55165 is as follows:
STATE AFTER INITIAUZATION
aSF
Write mode
Wrlte·mask register
Color register
Serial·reglster tap point
SAM part
Defined by the transfer cycle during Initialization
Nonpersistent mode
Undefined
Undefined
Defined by the transfer cycle during initialization
Output mode
~1ExAs
INSTRUMENTS
POST OFFICE BOX , _ • HOUSlON. TEXAS 772111-1_
6·159
TMS55165
262144 BY 16-BtT
MULTIPORT VIDEO RAM
SMVSl86D-AUGUST 1992 - REVISED JUNE 1996
absolute maximum ratings over operating fre. .lr temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) •...•..• • . . • . . . . . • . • . • . . . • . . • • . . • . • . . . . . • . • . . •• -1 V to 7 V
Voltage range on any pin .•.•.•.•...•••..••.......••...•.......•.••• , . • . . • . . . • • . • . . .• -1 V to 7 V
Short-circuit output current ••..•........•..•..••...•.........•......•..•.•.•.•.•.•......•.. 50 mA
Power dissipation .•......••••...•.•....•..••....•.•......•.•••..•.•.•.•...•.....••...•.•• 1.1 W
Operating free-air temperature range, TA .•..•.....•........••.• • • . • . . . • . • . • . • . . . . . • • .. ooe to 70°C
Storage temperature range, Tstg ...........•......•.•.•....•..•.•.•.•.....•....... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
funcUonai operation 01 the device at these or any other conditions beyond those Indicated under "recommended operating conditions· Is not
Implied. Exposure to absoIute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
Vee
Vss
Supply voltage
V,H
High-level Input voltage
2.4
8.5
V
V,L
Low-level Input voltage (see Note 2)
-1
0.8
V
Supply voltage
0
V
V
Operating free-alr temperature
0
70
OC
TA
NOTE 2: The algebraic convention, where the more negative Oess positive) limit Is designated es minimum, is used for logic-voltage levels only.
~TEXAS
5-160
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS55165
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVSl85D- AUGUST 1992 - REVISED JUNE 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
SAM
PORT
TEST CONDITIONS*
VOH
Hlgh·level output
voltage
10H=-1 mA
VOL
Low·level output
voltage
IOL=2mA
II
Input current (leakage)
VCC- 5•5V,
VI-OVto5.8V,
All other pins at 0 V to VCC
10
Output currant
Oeakage)
VCC = 5.5V. Vo =OVtoVcc
See Note 3
ICCl
Operating currant §
See Note 4
Standby
IC01A
Operating current §
Standby current
!cISC)- MIN
All clocks = VCC
ActIve
ICC2
ICC2A
Standby current
!c(SC) = MIN
Act~
Ices
RAS-only refrash
currant
See Note 4
ICC3A
RAS-only refresh
current
!c(SC) - MIN.
See Note 4
ICC4
Page-mode current §
!c(Pl = MIN,
ICC4A
Page-mode currant §
ICC5
CBRcurrent
!c(SC) =MIN.
See Note 4
ICCSA
CBRcurrent
!cISC) .. MIN.
See Note 4
See Note 4
'55165-60
MIN MAX
2.4
'55165·70
MIN MAX
2.4
'55165-80
MIN MAX
2.4
UNIT
V
0.4
0.4
0.4
V
:1:10
:1:10
:1:10,
IIA
:1:10
:1:10
:1:10
IIA
180
165
150
mA
225
205
185
mA
5
5
5
mA
70
65
60
mA
Standby
180
165
150
mA
Active
225
205
'185
mA
See Note 5
Standby
135
115
105
mA
See Note 5
Active
175
155
140
mA
Siandby
160
165
150
mA
Active
225
205
185
mA
180
180
200
mA
l
Standby
Data-transfer currant
Standby
200
Icca
Active
250
ICCM Data-transfer current
!cISC) " MIN
* For conditions shown as MINIMAX. use the appropriate value speclfled In timing requirements.
§ Measured with outputs open
•
NOTES: 3. ~ Is disabled for sa output leakage tasts.
4. Measured with one addreas change while RAS "VIL'!c(rd). !c(W). !cITRO) -MIN.
5. Measured with one address change while CAS .. VIH
225
mA
~ThxAs
INSTRUMENTS
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5-181
TMS55165
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVSl65D -AUGUST 1992 - REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-alr temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
MAX
8
CjlA)
Input capacitance, address Inputs
CI(RC)
CI{W)
Input capacltanca, address strobe Inputs
7
Input capacltanca, write enable Input
Input capaCltanca, serial clock
7
7
7
7
7
CllSC)
CI(SE)
CjlDSA'
Ci(TRG)
CoCO)
Input capacltanca, serial enable
Input capacltanca, special function
Input capacitance, transfer register input
Output capacltanca, SQ and DQ
Co(QSA Output capacitance, QSF
NOTE 8:. Vee. 5 V :I: 0.5 V, and the bias on pins under test Is 0 V.
UNIT
pF
pF
pF
pF
7
pF
pF
pF
pF
9
pF
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature (see Note 7)
PARAMETER
TEST
CONDlTlONSt
ALT.
SYMBOL
'65165-80
MIN MAX
17
'65185-70
MIN MAX
'65185-80
MIN MAX
UNIT
Ia(C)
Accass time from CAS
IcI(RLCL) .. MAX
!CAC
20
20
ns
Ia(CA)
Access time from column address
IcI(RLCL) .. MAX
tM
30
35
40
ns
!a(CP)
Access time from CAS high
IcI(RLCL) = MAX
tePA
35
40
45
ns
Ia(R)
Access time from RAS
tRAC
80
70
80
ns
Ia(G)
Access time of DQ from TRG low
toEA
15
20
20
ns
!a(SQ)
Access time of SQ from SC high
CL=30pF
!sCA
15
20
25
ns
!a(SE)
Access time of SQ from SE low
CL=30pF
!sEA
12
15
20
ns
lcIis(CH)
Disable time, random output from
CAS high (see Note 8)
CL.= 50 pF
toFF
0
15
0
20
0
20
ns
IcIls(G)
ffiG high (see Note 8)
CL=50pF
toEZ
0
15
0
20
0
20
ns
lcIis(SE)
SE high (see Note 8)
CL.-30pF
!sEZ
0
10
0
15
0
20
ns
Disable time, random output from
Disable time, serial output from
IcI(RLCL) .. MAX
t Measured with outputs open. For conditions shown as MIN/MAX, use the appropriate value specified In the timing requirements.
NOTES: 7. Switching times for RAM port output ara measurad with a load equivalent to 1 TTL. load and 50 pF. Data out referenca level:
VOH /VOL = 2V/O.8 V. Switching times for SAM port output are messured with a load equivalent to 1 TTLloed and 30 pF. Serial data
out referenca level: VOH / VOL" 2 V/O.8 V. '
8. IcIls(CH), lcIis(G), and IcIls(SE) ara specified when the output Is no longer drlv$n.
-!/} TEXAS
5-182
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. 'T1:XAS 77251-1443
TMS55165
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS185D - AUGUST 1992 - REVISED JUNE 1995
tImIng requIrements over recommended ranges of supply voltage and operatIng free-alr
temperaturet
ALT.
telrel)
Cycle time, read
te!W'l
Cycle time, write
'55155-60
MAX
'55155-70
MIN
'55155-80
MIN
lAc
110
130
150
118
twc
tRMW
110
130
150
n8
150
175
tpC
35
40
118
MAX
MIN
telrdWl
Cycle time, read-modify~wrlte
telPl
te(RDWP)
Cycle time, page-mode read, write
tPRMW
80
90
200
45
100
~!IRDl
telSCI
tw(CH)
Cycle time, trensfer read
lAc
110
130
150
Cycle time, serial clock (see Note 9)
tscc
18
22
30
Pulse duration, CAS high
tePN
10
10
twlCU
Pulee duration, CAS low (see Note 10)
teAS
17
twIRH)
Pulse duration, RAS high
tRP
40
twIRL)
Pulse duration, RAS low (see Note 11)
tRAS
80
twcwu
tw{TRG)
Pulse duration, WEx low
twP
10
10
15
tw(SCH)
Pulse duration, SC high (see Note 9)
tw(SCL)
twIGHI/
Pulse duration, SC low (see Note 9)
Cycle time, page-mode read-modify-write
Pulse duration, 'i'RG low
Pulse duration, TRG high
UNIT
SYMBOL
10000
20
70
n8
na
na
na
10
10000
50
10000
MAX
20
nB
10000
80
10000
80
10000
na
na
118
n8
15
20
20
na
tsc
tscP
5
8
10
118
5
8
10
118
trp
20
20
20
ns
60 100000
70 100000
80 100000
twIRL)P
Pulee duration, RAS low (page mode)
tRASP
tsu(CA)
Setup time, column address before CAS low
lAsc
0
0
tsu(SFCI
tsu(RA)
Setup time, DSF before CAS low
tFSC
Setup time, row address before RAS low
tASR
0
0
tsu{WMR)
Setup time, WEx before RAS low
twSR
0
0
tsu(DQRI
Setup time, DQ before RAS low
0
0
Setup time, 'i'RG high before RAS low
1Ms
trHs
0
tsuITRG)
0
0
0
tsu(SFR)
Setup time, OSF low before RAS low
tFSR
0
0
tsYIDCI..l
Setup time, deta valid before CAS low
lOSC
0
0
tsulDWLI
Setup time, deta valid before WEx low
tosw
0
0
0
nB
tsu(rd)
Setup time, read command,
CAS low
tRCS
0
0
0
118
tsu(WCL)
Setup time, early write command,
WEx low before CAS low
twcs
0
0
0
na
tsu(WCH)
Setup time, WEx low before CAS high, write
tcWL
15
15
20
n8
tsu(WRH)
Setup time, WEi low before RAS high, write
tRWL
15
15
20
thlCLCAl
Hold time, column address after CAS low
teAH
10
10
15
WEi
high before
na
0
nB
0
0
ns
0
0
0
0
na
na
na
na
na
0
ns
,
ns
na
Hold time, OSF after CAS low
10
15
na
10
th(SFC)
teFH
t liming measurements are referenced to VIL max and VIH min.
NOTES: 9. Cycle time assumes tt .. 3 ns.
10. In a read-modify-write cycle,ld(CLWL) and tsu(WCH) must be observed. Depending on the user's transition times, this may require
additional CAS low time ltw(CL)l.
11. In a read-modify-write cycle,ld(RLWL) and tsu(WRH) must be observed. Depandlng on the user's trensltion times, this may require
additional RAS low time ltw(RL)l.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
5-163
TMS55165
262144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVSl65D - AUGUST 1992 - REVISED JUNE 1995
tImIng requIrements over recommended ranges of supply voltage and operatIng free-aIr
temperature (contlnued)t
ALT.
SYMBOL
'55165-60
'5!l165-70
'55165-80
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
thlRAI
Hold time, row address after RAS low
tRAH
10
10
10
na
thITRGI
Hold time, ~ after RAS low
trHH
tRWH
10
10
10
ns
I'll
lh(RWM)
Hold time, WrIte mask after RAS low
10
10
10
lh(RDQ)
Hold time, OQ after RAS low (write-mask operation)
tNiH
10
10
10
ns
lh(SFR).
Hold time, OSF after RAS low
tRFH
10
10
10
I'll
lh(RlCA)
Hold time, column address valid after RAS low
(see Note 12)
tAR
30
30
35
I'll
th(CLOI
Hold time, data valid after CAS low
tOH
16
15
15
lh(RLO).
Hold time, data valid after RAS low (see Note 12)
tOHR
35
35
lhCWLOI
Hold time, data valid after WEi low
tOH
15
15
35
15
ns
ns
ns
th(CHrd)
Hold time, read, WEx low after CAS high
(see Note 13)
tRCH
0
0
0
ns
lh(RHrd)
Hold time, read, WEx high after RAS high
(see Note 13)
tRRH
0
0
0
ns
lh(CLW)
Hold time, write, WEx low after CAS low
twCH
10
15
15
na
lhlRlWl
thCWLGI
Hold time, write, WEx low after RAS low (aee Note 12)
twCR
tOEH
30
36
36
na
10
10
10
na
th(SHSQ)
Hold time, SQ after SC high
tSOH
4
5
5
na
lh(RSF)
Hold time, OSF after RAS low
tFHR
30
30
35
ns
Delay time, RAS low to CAS high
teSH
teHR
60
70
10
60
ld(RLCH)
ldICHRl\
Delay time, CAS high to RAS low
0
0
ldICLRH)
teRP
tRSH
0
Delay time, CAS low to RAS high
17
20
20
ns
ns
ld(CLWL)
Delay time, CAS low to WEx low
(see Notes 18 and 17)
tewo
37
45
45
ns
ldlRLCll
Delay time, RAS low to CAS low (see Note)
tRCO
20
ldlCARHI
Delay time, column address valid to RAS high
tRAl
30
36
ldlCACHI
Delay time, column address valid to CAS high
ldIRLWL\
Delay time, RAS low to WEx low (see Note 18)
Hold time, 'i'RG high after WEx low (see Note 14)
I
ISee Note 16
10
na
15
teAL
30
36
40.
ns
ns
ns
• tRWO
80
96
106
na
ld(CAWL)
Delay time, column address valid to WEx low
(see Note 18)
'Awo
50
80
65
ns
ldlCLRLl
Delay time, CAS low to RAS low (see Note 15)
tc!'lR
0
0
0
ns
ld(RHCL)
Delay time, RAS high to CAS low (see Note 16)
tApc
0
0
0
na
17
20
20
na
10
15
15
na
ld(CLGHl Delay time, CAS low to TRG high for DRAM read cycles
Delay time, 'i'RG high before data applied at DQ
ldlGHOI
tOED
43
20
t Timing measurements are referenced to Vil max and VIH min.
NOTES: 12.
13.
14.
16.
18.
17.
18.
The minimum value Is measured when ld(RlCl) Is set to ld(RLCL) min as a referance.
Eltherth(RHrd) orlh(CHrd) must be satisfied for a read cycle.
Output-enable-controlled WrIte. Output remains In the high-impedance state for the entire cycle.
CBR refresh operation only
Read-modify-write operation only
~ must disable the output buffers prior to applying data to the OQ pins.
The maximum value Is apeclfied only to assure RAS accass time.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 7'7251-1443
&0
20
40
60
TMS55165
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS185D - AUGUST 1992 - REVISED JUNE 1996
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (contlnued)t
ALT.
SYMBOL
'55185-80
MAX
'55185-70
MAX
'65185-80
MIN
MIN
MIN
MAX
UNIT
tcllRLTHI
Delay time, AAS low to fAG high (sea Note 19)
lATH
50
55
60
ns
tcl(RLSH)
Delay time, AAS low to first SC high after TRG high
(sea Note 19)
IRSD
85
70
60
ns
tcl(RLCA)
Delay time, RAS low to column address valid
IRAD
tcl(GLRH)
Delay time, fAG low to RAS high
tROH
15
10
tcl(CLSH)
Delay time, CAS low to first SC high after fAG high
(sea Note 20)
tcsD
20
tcl(SCTR)
Delay time, SC high to TRG high
(sea Notes 19 and 20)
trSL
5
5
5
ns
tcl(THRH)
Delay time, TRG high to RAS high (sea Note 19)
trRD
-10
-10
ns
tclrrHRLl
Delay time, TRG high to RAS low (sea Note 21)
trAp
40
50
-10
60
tclrrHsCl
Delay time, TRG high to SC high (sea Note 19)
trSD
10
10
15
ns
tcl(RHMS)
Delay time, RAS high to last (most significant) rising
edge of SC before boundary switch during splitregister-transfer read cycles
15
20
20
ns
tcl(CLTH)
Delay time, CAS low to fAG high in real-time transfer
read cycles
tcTH
15
15
15
ns
tcl(CASH)
Delay time, column address to first SC in early-load
transfer read cycles
tAsD
25
25
30
ns
tcl(CAGH)
Delay time, column address to fAG high In real-time
trensfer read cycles
lATH
20
20
20
ns
tclIDCL)
Delay time, data to CAS low
tozc
0
tcl(DGL)
Delay time, data to fRG low
tDZO
0
0
0
0
0
ns
ns
tcl(MSRL)
RAS low before boundary switch during split-trensfer
115
20
20
ns
tcl(scaSF)
Delay time, last (127 or 255) rising edge of SC to aSF
switching at the boundary during split-reglster-trensfer
read cycles (see Note 2222)
!sao
20
25
30
ns
tcl(CLaSF)
Delay time, CAS low to aSF switching In transfer read
cycles (sea Note 2222)
teaD
25
30
35
ns
tcl(GHaSF)
Delay time, fAGhigh toaSF switching in transfer read
cycles (sea Note 2222)
traD
20
25
30
ns
tcl(RLaSF)
Delay time, AAS low to aSF switching In transfer read
cycles (sea Note 2222)
tRaD
S5
70
75
ns
trf(MA)
Refresh time Interval, memory
tREF
8
ms
It
Transition time
50
ns
15
30
15
35
15
15
20
25
40
ns
ns
ns
ns
Delay time, last (most significant) rising edge of SC to
read cycles
tr
.
8
3
50
8
3
50
3
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 19.
20.
21.
22.
Real-time load transfer read or late-load trensfer read cycle only
Early-load transfer read cycle only
Full-register (read) transfer cycles only
SwItching times for aSF output are measured with a load equivalent to 1 TTL load and 30 pF and output reference level Is
VOH /VOL· 2 VIO.8 V.
~ThxAs
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262144 BY 16·BIT
MULTIPORT VIDEO· RAM
SMVS185D -AUGUST 1992- REVIsED JUNE 1986
WEx
_
1
telCDGL) ---;014
.........i--.r~1
DQO-DQ15
Data In }
I1
1
I
I'"
.11
1
1
I1
1
11 telIBCCH)
1
j+ taCG) +!
I1 I1
~
I ~taCC)-+I
14
taCCA)
ta(R)
I1
.~
1~1oIooWIoI~~~
1
1
1+ telIBCG) -+j
Data Out
~I
~I
Figure 23. Read-Cycle Timing
~TEXAS
5-186
114.
INSTRUMENTS
POaTOFF1CE BOX 1443· tIOIJBTON. TeXAS 77251-1443
}>-----
TMS55165
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS186D - AUGUST 1992 - REVISED JUNE 1895
PARAMETER MEASUREMENT INFORMATION
~
~~
_ _.......jl 14
N
AD
It
! II1II
-+I
I
14
~
II14I
~ ~
th(RA)
tct(RLCA)
Ih(RLCA)
I~
Row
I
I
tct(CACH)
!4;
I
I
II
I
Column
I
L
.vT
I L
J
I tw(RH) I
t
~I
I
I
I
I
I
I
"'(CHAI.l-+i
VI+tI I
"I~ I -+I!'tt
lsu(CA)
~ I I4--+I-Ih(CLCA)
IsU~)
~ III
AO-Aa
~
""""
N_--+I
I
I ~I
I ~ I4-lt
tct(CLRH)
~ tct(RLCL) +I
~ ~ "'(CHR~ • ~
CAS
~I
fci(RLCH)
1+
~
~I
tw(RL)
tw(CH)
~'-
I
tct(CARH)~
~~~~~~~~~~~~~
lsu(SFR)
~ I I lsu(SFC)
I 14-- Ih(RSF) ~
-.I J4t
!
Ih(SFR)
~ ~
I"~
TRG
Ih(TRG)
~
I
I
I
tau(WCH) ~
tau(WRH)
~I
lsu(TRG)~ J4t~1
. ~
.
~II
' _
I I
lsu(WMR)
I
M
I I I~
I~ I
-+j
I
r.
~ ~
"'(RWM)
~
I I I
I I
I+-
~:R
WEx
Is
u(DQR)
-+!~
I
I
"'(RDQ)
~I
th(RLW)
I
~I
th(CLW)
I ~~~~~~~
lsu(WCL)
~
tw(WL)
II
-+I
-+J II1II-
~ ~ fl1'I?\. !
DQO-DQ15
I
I
~I ~
DSF~II~III
I I
~ 14-
I
I
~
I 14-- th(CLO) ----.!
~ lsu(DCL)
"'(RLD)
I
~I ~moeo~moeo~mooeoo~mooeoo~~
3
~
Rgure 24. Early-Write-Cycle TIming
Table 6. Early-Write-Cycle State Tabie
STATE
CYCLE
1
2
3
Write operation (nonmasked)
H
Write operation with nonpersistent wrIte-per-blt
L
L
Oon'tcare
Write mask
valid data
valid data
Oon'tcare
valid data
Write operation with persistent write-per-bit
~1EXAS
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262144 BY 16-BIT
MULTIPaRT VIDEO RAM
SMVS165D -AUGUST 1992 - REVISED JUNE 1995
TRG
~II
-+j 14"
teu(TRG)
~
I I
~...
WEi
IcI(GHD)
I
I
I
(R ~ ~::;. Il':
~
*
I
1
~ ~
I~
I
I .., ~
teu(WRH).
teu(WCH)
--+I
..I
th(CLW)
I
.. I
th(RLW)
ih(WLG)
I
I
I
I
I
~I
~
.
~~
1w(WL)
!~I 1 ~----~~~:liQ,Qj:liQ,Qj~~~
I
1.1
teu(DQR)
DQO-D01S
I I I'"
II II... II...
r-+I I
teu(DWL)
j4- Ih(RDO)
1... 1
~
I I
I I
I I
~
i4i"
!+- th(WLD) -+I
I
.. I
ih(RLD)
3
Figure 25. Late-Wrlte-Cycle Timing (Output-Enable-Controlled Write)
Table 7. Late-Wrlte-Cycle State Table
STATE
CYCLE
Write operation (nonmasked)
Write operation with nonpersistent write-per-bit
Write operation wlthpeiSlstent write-per-bit
1
2
H
L
L
Don1care
3
Valid data
Write mask
Valid data
Don't care
Valid data
~1ExAs
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INSTRUMENTS
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TMS55165
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS185D-AUGUST 1992 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
~
----i.'
~
'4
JN~
ft -, 1+
~
I ~ tcI(RLCL) -+I
~
tcI(CHRL)
1
~
...
... (RA)
K
. I
I
I
I
~ tcI(CHRL) ~
itt
~
1
I j4-t-- tw(CH) ~
I
1
tw(CL)
"'1RAI~14l- ~.
~:~
AO-AIJ
-.r ~ teu(SFC)
I 1
I I r.-- ih(RSF) ---.I
~I I 1
-?I
I4t
-H
teu{rRO)
-+j
I
teu(SFR)
I II"
Ih(SFR)
j+~jl~11
~li~'1
DSF
~ ~ lhcrRG)
r-t I
I
~II
I
I
W II.. ', I
j
j4i i
1 ,4
I I I
41 I+- 1l J..
~I
t_
..u(WMR) -...
th(RWM)
I
I
I 1
~ !~
===
1
I
I
-.t
1
~I
tJ,(RLW)
I
1 ~~~~~:7'I7'eoeom:"""
~
tw(WL)
I
~ teu(DCL)
.
lh(CLD)
tJ,(RLD)
.,
·1
tJ,(CLW)
'14
~
I
I
teu(WRH)
teu(WCL)
~ I~!I
,
I
~I'
teu(WCH)
j
-I
I
I
I
·1I ~
~II
DQO-DQ15
-+1'--'
tw(RH)
1 .1 I
1 -+I I+- ft
tcI(CLRH)
1
1I
1- I
Vj.I,
~I
tcI(RLCH)
N~
I 1
J.!!.I
~
~I
tw(RL)
---.r
~I
Write Maakt
~
t Load-write-mask....glster cycle puta the device Into the persistent write-per-blt mode.
Figure 26. Load-Wrlte-Mask-Reglster-Cycle Timing (Early-Write Load)
~1EXAS
INSTRUMENTS
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TMS55165
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS185D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
_ _--oil
~~
I~
~
I
~I
tw(RL)
N
0
I ;~
~I
It ~
I
~ I!
I
I~
J+-
-+I I4t
i4-1cf(RLCL)
I I
1h(RA);+i
lcf(cLRH)
I
+I
~~
t+tiI
...!
I
Icf(CHRL)
-+I
I ~ I+- It
~0Je-+I-";'"----1'-.
I I+f---+l
I
I
tw(CL)
il
!+-
I
I
Icf(CHRL)
L
I 14- tw(RH) --.:
Icf(RLCH)
tw(CH)
I I
AlJ-AS
I j+-tau(SFR) -.:
OSF
j4t
~m
Ih(RSF) 1---+1
tau(SFC)
I
I
I ii~ ~_~,
1+-,
FC
I4f. tau{TRQ)
! _I!
tau(WMR)
i
xxm
--4 ~
I
I
A2-AS
I
I I
"u(SFC)
II~
~
BlIIWII,1
DSF
1
VI
teI(CARH)
1
teI(CACH) --+I
I
I+- -+t ~ "U(CA)
-.I I j4-"U(SFR)
I
"1411
14
~
AD-AS
...
..I .1
It!(CLCA)
1 ~ It!(RLCA) -.I
teI(RLCA) ,
"u(RA) ~ I4t
It!(RA) w.I
+1'---
I
1 ..I
I
1 !++- teI(CHRL) ....,I
(CLRH)
tw(CL)
N
~
"I
tw(RL)
14- I+-
fiiGB"ll~
I I
It!
~ I+14 I I
"U(WCH)
.. I
1
(WM~1 :.:.III
....
I
'1'4
~
~ I:!
I
....(DQR) ~
tt.(RDQ)
DOG-DQ1'
1
I
I ~
i4!-
'--.l14-
"I
"u(WRH)
","U(WCL)
I
WIi
:=-----=
-.14 W
,
I
tw(WL)----+~
~
.. I
tt.(RLD)
~ I4f "u(DCL)
I
"I
tt.(CLW)
tt.(RLW)
J4- tt.(CLD)
i
3
I
_
Figure 34. Block-WrHe-Cycle nmlng (Early Write)
Table 11. Block-Wrlte-Cycle State Table
CYCLE
1
Block-write operation (non masked)
H
Block-wrlte operation with nonpe~lstent wrlte-per-blt
Block-write operation with persistent wrlte-per-blt
Write-mask data
0: I/O write disable
1: I/O write enable
Column-mask data OQI- OQI+3
0: column write disable
0, 4, 8, 12) 1: column write enable
L
L
o•
STATE
2
Don'lcare
Write mask
Don'lcare
3
Column mask
Column mask
Column mask
Example:
DQO - column 0 (address A1 • 0, AD • 0)
001 - column 1 (address A1 .0, AD • 1)
DQ2 - column 2 (address A1 • 1, AD • 0)
DQ3 - column 3 (address A1 • 1, AD • 1)
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 11:XAS 772lI1-1443
15-177
TMS55165
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS185D -AUGUST 1892 - REVISED JUNE 1995 '
PARAMETER MEASUREMENT INFORMATION
~
_ _"",,' 14
tw(R~
N
I ~
~I 14It ~
fcI(RLCH}
~
,
~
~I
.~Ir+I
tw(RH)
I "tl
fcI{CLRH) --+~
... j4- It
L
-.r"
1
tw{C~
~ + fcI{CHR~
'tllU!!I L ~ NrH=tw{cH)~'~I I
fcI{C~ ~ fcI{R~
W
~~
fcI(RLCA)
1tI{RA)
14
-+I
""4 I ,
I r:--1tI(RLCA)..--+I
~ I+14 ' I
I
~ ~teU{CA)
I II
fcI{CACH)
I
I
I
I
I
I
I
I
I ~I
fcI{CARH)
'D-IA"'~I~_
~SF)
~
-+r
-.I I4t teu{SFC)
teu{SFR)
I I
ItI{SFR)
OSF
-ri W
Block Addre..
A2-Aa
~::
.
~II~I~ ~teU(TRG) I
I I
~N
14
ItI{CLW)
~II I ~
OQO-OQ15
Figure 35. Block-Wrlte-cycle 'riming (Late Write)
Table 12. Block-Wrlte-cycle State Table
1
STATE
2
Block-wrlte operation (nonmasked)
H
Oon'lcare
Column mask
Block-wrlte operation with nonpersistent write-per-bit
L
L
Write mask
Column mask
Oon'tcare
Column mask
CYCLE
Block-write operation with persistent write-per-blt
0:
I/O write disable
1:
I/O write enable
Column-mask data OQl- OOi+3
0: column write disable
(I • 0, 4, 8, 12)
1: column write enable
Write-mask data
~1ExA.s
5-178
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON.lEXAS 77251-1443
3
Example:
DQO - column 0 (add_ A1 .0, /II) • 0)
001 - column 1 (add_ A1 .0, /11). 1)
002 - column 2 (add_ A1 • 1, /11).0)
003-column3 (add_A1 1,/11)= 1)
=
TMS55165
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS185D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
14
~
!
"_HI
_l4
tcs(RLCL)
~ ~
~
tcs(CHRL)
14
W#lllj14- tcs(RLCA) --.I
ZlI
"'(RA)
~
AIJ-AS
teu(CA)
~I
teu(RA)
I
~ ~II teu(SFR)
-m.!
I
I'll
j
MF
I
I~I I~
01
.....
r-1w(CH)
Iw(CL)
r
~~I
I I
I
Iti(RLCA)1
I
"'(CLCA)
I
~I
01
-+j j+-- tcs(CLRH)
I
tcs(CHRL)
IiI /
I
I
14
I I
I
I
I
~I
II
I
j+- tcs(CACH)
14
--oI~"""
I
I
-.j
---+t
tcs(CARH)
t~ll.- o~ ~k~ ~ ~~~ ~
h(SFR)
OSF
I I
I 14
l.t
~I
1w(RL)p
I I
X"x"xX "
H
j4i-t
I
I
I j4- th(SF~ --.J
I
Wi
'Jl;f
j4- "'(TRG)
-.I
I j4- "'(SFC) ~
~I Iteu(SFC)
I
14-+1- teu(SFC) I ~I
I
·
11 -
teu(TRQ)
I I
I I
I I
I
I
I
I
I
I
I
OQO-OQ15
t Referenced to the first WEx falling edge or the falling edge of CAS, whichever occurs later
NOTE A: To assure page-mode cycle lime, TAG must remain high throughout the entire page-mode operation Hthe late write feature is used.
Hthe early-write-cycle timing is used, the state of TAG is a don't care after the minimum period "'(TRG) from the failing edge of RAS.
Figure 38. Enhanced-Page-Mode Block-Wrlte-Cycle TIming
Table 13. Enhanced-Page-Mode Block-Wrlte-Cycle State Table
STATE
CYCLE
1
2
Block-wrile operation (nonmasked)
H
Oon'tcare
3
Column mask
Block-write operation with nonpersistent write-per-bit
L
Write mask
Column mask
Block-write operation with persistent write-per-bit
L
Don't care
Column mask
Write-mask date 0:
va write disable
1:
va write enable
Column-mask data 001 - OOi+3
0: column write disable
0, 4, 8, 12)
1: column write enable
o•
Example:
000 - column 0 (eddress A1 0, All .. 0)
OO1-column 1 (eddressA1 .0, All. 1)
002 - column 2 (eddress A1 • 1, All • 0)
003-column 3 (eddress A1 .1, All .. 1)
=
:lllExAs .
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77251-1443
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TMS55165
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MULTIPORT VIDEO RAM
SMVSI65D- AUGUST 1992 - REVISED JUNE 1886
PARAMETER MEASUREMENT INFORMATION
1I
I I
I I~
.1
IJ,(RA)
"_M~-I!I4-~-~~~"-"'~+-:
.
I I
D
a o - .
D Q 1 S .
Figure 37. RA§'-Only Refresh-Cycle Timing
)~ThxAs
5-180
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77261-1443
TMS55165
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MULTIPaRT VIDEO RAM
SMVS185D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
~~
1+--1w(RH) ~ 141111111----Iw(RL) ---~.I
RAS
fi
_ _oJ!1IIII
.,
~!'7e'I:~tci.(C_L_RL)"",
N
tci(RHCL)
1II1II
CAi~1 \J.
II
•
~
1
___- - - - - -
1:
I
-.1
14- It
I+- tci(RLCH) ---+I
V
II
I I
I11III-- tci(CHRL) ~ I
I I
--+oI11IIII1---i.~1 !oIII11IIII1---I.*"1""~~!'7e'I:~~","""",,~
11 I
teu(RA)
AO-AS
fh(RA)
I I
teu(SFR) -;'11IIIIe--.~1 "'1II1II1---1.*1- fh(SFR)
DOF~:':~
DQO-DQ1S
Figure 38. CBR-Refresh-Cycle nmlng
Table 14. CBR-Cycle State Table
CYCLE
CBR refresh with option reset
CBR refresh with no reset
CBR refresh with stop point set and no reset
STATE
1
Don't care
Don't care
Stop address
2
L
H
3
H
H
H
L
-!!1
ThxAs
INSTRUMENTS
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SMVSl85D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
!+" Memory Read Cycle -+!.- Refresh Cycle
~IIIIII
, I
~I+-- tc(rcI)
14-- tc(rcI)
RAS
,
tw(RH)
I
I
_
(R~ illll :·H
'.4~ I; tw(R~N.~
~
~_
----"0.1 I -
CAl
~
,l1li
I
1l1li
I
;#rr ~(~~~
W I I!
! :l1li .1 1 I'
I
I~
I
Vi
1
I I
IcI(CARH)
I~
i
I~I
IcI(RLCA)
1-+1 ~ ..U(CA)
~
"1+--
';"1111
__-.~1
--+t
I
,
tc(rcI)
.,
1 !\!'-___.I~I'!\..--/rI
y
I
I
tw(C~
I
II
Ift(CLCA)
~ ~I Ift(RA) -+I
-+I ~ "u(RA) II
I
tw(RH)
Refresh Cycle
I I
I I
1+1t
,I I
~
~I
-+I
I
I
I
I
I
1
I
I I
~I
I
1I
!!lilt "u(RA) I
1 ~Ift(RA)
-+t
:
I
I
rl
~!
"u(RA)
~Ift(RA)
1
:.t"U(RA)
~Ift(RA)
S~
I
I I
I
1l1li
'I
IcI(RLCH)
I
I
I I
I I
,
,
I'
_ .. ~ :,: ~ ',' ~){ ~ ~"""''ft7'!'7'
,=
-+: ~
~ If
~, ~ ~th(SFR) I '!
2S-~1
::
~ ~~
~~'-:-"'l""_---J//~~
.I I
II1II--*I I
~
-+I ~ ~(TRG) I I I
rvJ -+j rT I ~(TRG) I I I
I I
~
W II \~~ ~ IcI(QLR~
II
!
"
I
~ w:..
SS
I
"
'"
I
-+l
j4r.
~(SFR)
';FFR)
,
DSF
2)
I
I I
"u(SFR)
I;
Ift(RHrd)
I I
I
I
__
L ..
IcIlr(CH) -
11cI18(G)
fAG.
I
~ I
~ I
"u(rcI)
~
tJ
I,
I
~~ ~
iIIIIt "u(WMR)
: 1
I
t_
I ~ I ..u(WMR)
/
-+! I4i- "u(WMR)
~Ift. ~
!+frlft(RWM)
-~I~l~~i' ~ · ~w{ ~~
~~~
000DQ15 ,
----<{
I
~~
D8t80ut
}-
Figure 39. Hldden-Refresh-Cycle Timing
Table 15. Hldden-Refresh-Cycle State Table
STATE
CYCLE
Don' care
2
L
Don' care
Stop address
H
H
1
CBR refresh with option reset
CBR refresh with no reset
CBR refresh with stop point set and no option reset
~1ExAs
5-182
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
3
H
H
L
TMS55165
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVSl85D- AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
14
tc(TRO)
------.it!
J. "t
I ~
Ici(CHRL) -iO.141----...,
vwwJ.
t;i--------------------
FIgure 20. Example of Successive Spllt-Reglster-Transfer Read Operations
-!111ExAs
INSTRUMENTS
P08TOFFICE BOX 1443 • HOUS1ON. TEXAS 771151-1443
5-216
TMS55161
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS181 B - OCTOBER 1 . - REVISED JUNE 1995
serial-read operation
The serial-read operation can be performed through the SAM port simultaneously and asynchronously with
DRAM operations except during transfer operations. Serial data can be read from the SAM by clocking SC
starting at the tap point loaded by the preceding transfer cycle, proceeding sequentially to the most significant
bit (bit 255), and then wrapping around to the least significant bit (bit 0), as shown In Figure 21.
r'
0
1 1 1 2 1 ..... 1Tap 1-+··· 12541 2ss1
I
Figure 21. Serial Pointer Direction for Serial Read
For split-register-transfer read operation, serial data can be read out from the active half of the SAM by clocking
SC starting at the tap point loaded by the preceding split-register-transfer cycle. The serial pointer then proceeds
sequentially to the most-significant bit of the half, bit 127 or bit 255. If there is a split-register-transfer read to
the inactive half during this period, the serial pointer points next to the tap point location loaded by that
split-register-transfer (see Figure 22).
Figure 22. Serial Pointer for Split-Register Read - Case I
If there is no split-register-transfer read to the inactive half during this period, the serial pointer points next to
the le,ast significant bit of the inactive half (bit 128 or bit 0) (see Figure 23).
FIgure 23. Serial Pointer for Split-Register Read - Case II
split-register programmable stop pOint
The TMS55161 offers programmable stop-point mode for split-register-transfer read operation. This mode can
be used to Improve 2-D drawing performance In a nonscanline data format.
In split-register-transfer read operation, the stop point is defined as a register location at which the serial output
..'stops coming from one half of the SAM and switches to the opposite half of the SAM. While in stop-point mode,
the SAM is divided Into partitions whose length is programmed via roW addresses A4-A7 In a CBR set (CBRS)
cycle. The last serial-address location of each partition is the stop point (see Figure 24).
127
0
Partition
Length
I
~
I
{
I· · ·1
1. ..
128
I
I
255
I
I I. ..
Figure 24. Example of the SAM With Partitions
~TEXAS'
5-216
I· · ·1
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
I
I
Stop
Polnta
TMS55161
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVSI81B-OCTOBER 1993-REVISEDJUNE 1895
split-register programmable stop point (continued)
~int
mode is not active until the CBRS cycle is initiated. The CBRS operation is performed by holding
CASxand WE low and DSF high on the falling edge of RAS. The falling edge of RAS also latches row addresses
A4-A7, which are used to define the SAM's partition length. The other row-address inputs are don't care.
Stop-point mode should be initiated after the initialization cycles have been performed (see Table 5).
Table 5. Programming Code for Stop-Point Mode
MAXIMUM
PARTITION
LENGTH
AS
A7
AS
AS
A4
AO-A3
16
X
L
L
L
L
X
16
15.31.47,63.79.95.111.127,143.158.175.
191,207,223,239,255
32
X
L
L
L
H
X
8
31. 63. 95. 127. 159. 191. 223. 255
64
X
L
L
H
H
x
4
83.127.191.255
128
(default)
X
L
H
H
H
X
2
127.255
ADDRESS AT jQS IN CBRS CYCLE
NUMBER OF
PARTITIONS
STOP-POINT LOCATIONS
In stop-point mode, the tap point loaded during the split-register-transfer read cycle determines in which SAM
partition the serial output begins and at which stop point the serial output stops coming from one half of the SAM
and switches to the opposite half of the SAM (see Figure 25).
RAS
rf
~ReadXFE
Full
.
Y
Y
~ReadXFER
Spilt
~ReadXFER
Spilt
Tap=H1
Tap.L1
Tap=H2
Tap=L2
H1
191 L1
63 H2
255 L2
SC ________________~ ••• ~ ••• ~ •••••• ~
0
L1
t
SAM Low Half
63
L2
127
128
1 t:
.
4
H1
SAM High Half
191
:
4
~
~
H2
255
f
4
1
Figure 25. Example of Split-Register Operation With Programmable Stop Points
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5-217
TMS55161
262144 BY 16-81T
MULTIPORT VIDEO RAM
SMVS181 B - OCTOBER 1893- REVISED JUNE 1895
258-/512·blt compatibility of spln·reglster programmable stop point
The stop-point mode Is designed to be compatible both for 256-bit SAM and 512-blt SAM devices. After the
CBRS cycle Is Initiated, the stop-point mode becomes active. In the stop-point mode, and only In the stop-point
mode, the column-address bits AY7 and Aya are internally swapped to assure the compatibility (see Figure 26).
this address-bit swap applies to the column address, and it Is effective for all DRAM and transfer cycles. For
example, during the split-register-transfer cycle with stop point, column-address bit Ayals a don't care and AY7
decodes the DRAM row haH for the spllt-reglster-transfer. During stop-point mode, a CBR option reset (CBR)
cycle Is not recommended because It ends the stop-point mode and restores address bits AY7 and Aya to their
normal function. Consistent use of CBR cycles ensures that the TMS55161 remains in normal mode.
NON STOP-POINT MODE
STOP.pOINT MODE
AY8.0
AY8.1
AY7.0 AY7.1 AY7.0 AY7.1
o
AY8.0
AY8.1
AY7.0 AY7.1 AY7.0 AY7.1
5121(512
Memory Array
5121(512
Memory Array
258-8ft
Data Reglatar
258-Bft .
Data Reglatar
o
2155
2515
Figure 26. DRAM·to-SAM Mapping, Non Stop Point Versus Stop Point
IMPORTANT: For proper device operation in a split-register stop-point mode, a CBRS cycle should be initiated
right after the power-up initialization cycles have been performed.
power up
To achiRjJroper device operation, an initial pause of 200 !lS Is required after power up followed by a minimum
of eight
cycles or eight CBR cycles to Initialize the DRAM port. A full-register-transfer read cycle and two
SC cycles are needed to initialize the SAM port.
After Initialization, the Internal state of the TMS55161 Is as follows:
STATE AFTER INITIAUZATION
OSF
WrIte mode
WrIte mask register
Color register
Serial-register tap point
SAM port
Oeflned by the transfer cycle during Initialization
Nonpersistent mode
Undefined
\
Undefined
Oeflned by the transfer cycle during initialization
Output mode
~1ExAs
5-218
INSTRUMENTS
POST OFFICE lOX 1443 • HOUSTON. lE------
ta(C)--+I
ta(CA)
ta(R)
.1
I
.1
Figure 28. Read·Cycle Timing With RAS·Controlled Output
~TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lCXAS 77251-1443
'
TMS55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS181B-OCTOBER 1993-REVlSEDJUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
~
- - - . il 14
'N
RAI
I 14
It
--lI ~~
~
CASx
rt
y~:V(RH)
~ ....!
tcJ(RLCH)
14
tcJ(RLCL) -.I
tcJ(CHRL)
~ II Ij4--
OL
I ~
I ~
tcJ(CLRH)
~
IsU~~nv\.~ I~I
ih(SFR)
r: r-
If ----.t
ih(RSF)
ih{I'RG}
tcJ(CHRL)--tI
I
I
I
I
1
tw C
~ H)
-....1"-I
lsu=n~l~
'llll111 •
I I
1
~ I
-.I H
t.. I I
Ili-I
III
~
ih(RWM)~. 1 I ~
~
lsu(WCH)
1su(WRH)
.,
ih(RLW)
Ih(CLW)
~ ~lsu(WCL)
~ ti
J
IeU(DQR}~ I
ih(ROQ)~ 14-
1
i4--ih(CLD)
I
~
I ~mm:mm:~_ __
~
.tw(WL)
~!if lsu~L)
~ ~y
OQO-OQ15
I
I
I I ~.
IsU(WMR}
WE
I
~II~II
+-I 14-
fRO
I
~COiumn_
lsu(SFR} -.I itt
-.j
lsu(SFC}
I
I
II ~
DSF
--1'---
I
I r
I I
I 1
~I
I
Ih(RLCA)
ih(RA)~ ~ -.I !4+
I I I
I lsu(CA)
tcJ(RLCA) I 141
.,14 I I
tcJ(CACH)
~I
~ Ih(CLCA)
I I 1
AO-AS
j.- It
I
V!...Li
~
tw(CL)
~ ---.j
~
~
tw(RL)
-..!
I
~
ih(RLD)
3
_t1f.~~~~~~~~"
Figure 29. Early-Wrlte-Cycle TIming
Table 6. Early-Wrlte-Cycle State Table
STATE
CYCLE
1
2
3
Don't care
Valid data
Write operation with nonpersistent write-per-blt
H
L
Write mask
Valid data
Write operation with persistent wrlte-per-blt
L
Don't care
Valid data
Write operation (nonmasked)
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAB 77251-1443
5-227
TMS55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS161 B- OCTOBER 1993 - REVISED JUNE 1995
TRG
~ 11
-+j ~ tau(TRG)
111
i.4t-
tcI(GHO)
I I1
{
h
~-:hI\U~(wMR)1
Lilli
14
14
1
1
I
lhIRLW)
t.I
~
i
'taU(WRH)
tau(WCH)
th(CLW)
~
~I
~
I
~I
1
1
1
~~
.
WE~!rE·~~~
1_I
tau(DOR)..,
~
I -+j
I
000-0015
tau(OWL)
I+-
th(ROO)
1... 1
I 1
J+--lh(WLD)
I 1
11
~
th(RLD)
~
1
~I
3
Figure 30. Late-Wrlte-Cycle Timing (Output-Enable-Controlled Write)
Table 7. Late-Wrlte-Cycle State Table
STATE
CYCLE
1
2
3
H
Don'lcare
Valid data
Write operation with nonpersistent write-per-bit
L
Write mask
Valid data
Write operation with persistent wrlte-per-bit
L
Don'lcare
Valid data
Write operation (nonmasked)
~TEXAS
INSTRUMENTS
5-228
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS55161
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVSI61B-OCTOBER 1993-REVISEO JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tc(W)
I..
_ _-.jl II1II
twIRL)
N
I I..
tcI(RLCH}
It -+j i+
~
~
I 14K
I..
tcI(RLCL)
I I
I I
I~
~
y~
1
tw(RH)
I I
I ~I I
I -+I I+- tt
-+I
I
--.l"--I
I
I
~ i++- tcI(CHRL) -+I
~.vt :
1~ i
tw(CL)
1
I _
th(RA)~
~I
tcI(CLRH}
N"
tcI(CHRL)
~I
~I
II
I
I
I
I
I
I
I
I
I
I
!\..-
tw(CH) - - - . :
.......,~141-~
AO-AS
~:=y
I I
-+I
-+I r.t- tsu(SFR)
I I I..
th(RSF)
tsu(SFC)
--.I
-H
I I I"
MN0T11~1,
j+-
Ih(SFR)
OSF
~
I I
~II~II
~
th(TRG) I
tsu{TRG) -+I ~ I
I I
~:~
I
1+
MN0T11
~I,
~I
W
I
:
I
I"
tsu(WMR) -...
Ih(RWM)
I..
I
I"
I
I I
I I
I I
I I
M
*- I I.. :"
I I I
:+i I I
~
OQO-OQ15
'-I
I~I:
I
I
I
I..
tsu(WRH)
I
'e'~~~~~~~(
~I
Ih{RLW)
I·
I
~I
~:I
th(CLW)
tsu(WCL)
~
tw(WL)
I
-+I
I
~I
tsu(WCH)
14+ tsu(DCL)
1~
..- - - t h ( C L O ) - . r
th(RLD)
-----+i~1
Write Maskt
~
t Load-write-mask-register cycle will·put the device into the persistent write-per-bit mode.
Figure 31. Load-Write-Mask-Register-Cycle Timing (Early-Write Load)
-!I1TEXAS
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MULTIPORT VIDEO RAM
SMVS181 B'- OCTOBER 1993 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
DQO-DQ15
t Load-write-mask-reglster cycle win put the device Into the persistent wrfte-per-bitmode,
Figure 32. Load-Wrlte-Mask-Reglster-Cycle nmlng '(Late-Write Load)
~1ExAs
5-230
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77251-1443
TMS55161
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVSI61B-OCTOBER 1993- REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
RAS
~~
ld;~~~)
--{I~I: '
~ ~
Iet(CHRL)
i+-ld(RLCL)
CASx
114
I I
I I
I I
~
~4
ld(cLRH)
tw(CL)
14
~It
II
I h(RA! I I
I
-pi
I
I ~
/4t
~i~~1
II
I 1
~ll
(RH)
Iet(CHRL)
II
I
11+ tw(CH)
II
'
II
+l
tsu(CA)
j+-th(CLCA)
tsU(RA)~ qL;~ fS:
AO-AS
~
~: ~ ~OIUmn
~th(RSF)
-+I ~ tsu(SFR)
lh(SFR)
I 114 ~I
I ~
I I++i-
-+I 141
11
th(SFC).
~
I
mJll~llll~
~
I
DSF~II
'I L
~ tsu(rd).
-lh(TRG)
I I
II
~
~
I 14 i II Iet(CAWL)
II
14
~tw
I+- tsu(WRH) -+t
~I I
I
I ~:::;l=~=~~~1I ~£§~88~~~
I II I
(I
I 1
I
I
i4----+-4-+-+i-!-1- lh(RLW)
I I
I 14 1
I th(CLW) I 1
I
I I
I
I
-+I ~ tsu(WMR) I I I 14 1
ld(CLWL)
1
I I I
114 ~I II ld(DCL) 1
I
lh(R;J, i i4,
I 14
,1
01 i"lOLOHl
TRG
~I
~I
I
-1
WE
~ 1 14
1 14
~w.
M 14 ii t~I
ts(R)
~ 14+ tsu(DQR)
DQO-DQ15
tsu(WCH)
1
14
II
~~
I
I
.J
~l
ts(CA) 1
ld(RLWL)
I: ld(DGL) [4
-J'i
~I
~
tw(WL)
I 1+ th(WLD) +t
I ld(GHD)
I
~ ~~ ~~;: ~ ~~ ~
II
I+-
ts(G) . ,
!~~I
~ Ietla(G)
Figure 33. Read-Wrlte/Read-Modlfy-Wrlte-Cycle Timing
Table 8. Read-Wrlte/Read-Modlfy.Wrlte-Cycle State Table
STATE
CYCLE
1
2
3
H
Don't care
Valid data
Write operation with nonpersistent write-per-bit
L
Write mask
Valid dati.
Write operation with persistent write-per-bit
L
Don't care
Vsliddati.
Write operation (nonmaskedl
~1ExAs
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POST OFFICE BOX 1443 • HOUSTCN, TEXAS 772151-1443
5-231
TMS55161
262144 BY 16-BIT .
MULTIPORTVIDEO RAM
SMVS181B - OCTOBER 1993 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
u~
II-ltat(TRO)
~ rrtaU(TRO) t\1' I
fRGW111
-+I
~taU(WMR'
II
. tauCrd)
l~ I
W
_-I
WE
I
I
I
teI(DOL)
I
II
I I
II
II 11-1I II
I I~
I~ :
ta(R)*
t---+l
I
11-1
I
000- ----~
Data In 1 ) - - - - - - - 1 - - - (
DQ15
---~
.
I
II
I
II
I
I
I I
I
I I
~ -+II+- tacc)
I I
taCCA)
I
II-! t+- tacO)
I.-
I
I
I
II
I
I
I
'I
I
tatCCLQ)
I
I
I
II
I
I
--!+-+j
I
I
j4- ta(C4)t ~
I
I~
taccp)t
Data Out
I
I
I
I
V!
I
I
tat(RHrd)
I
I
I
I
I p!+-
-+j
1I
tel
18(WL)
II
~IS(RH) ~
,..- telISCO)
Data Out
I
14- teI(DCL) ---.I
Access time Is taCCP) or ta(~ dependent.
I
Output can go train the hlgh.Jnipedance state to an Invalld-dsta state prior to the specified access time.
NOTE A: A write cycle or a read-modify-wrlte cycle can be mixed with the read cycles aa long aa the write and read-modify-wrlte timing
specifications 81'8 not vlolatedad the proper polarity of DSF Is selected on the failing edge ofRAS and -eASx to select the desired write
mode (normal, block write, etc.).
*t
Figure 34. Enhanced-Page-Mode Read-Cycle Timing
~TEXAS
5-232
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS55161
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS181 B - OCTOBER 1993 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
r
!)
l\,1
RAS
,
1
tcI(RLCH)
tcI(RLCL)
1<111
, 4
-+I ~
CASx
taU(RA)
•
tcI(RLCA) ~
tsU(CA)
th(RA) ~
I
,
, 1
-+i ,
TRGW!
~
~
~I
r-lh(SFR) ~
,
.
,
tcI(CHRL)
---.,l
tcI(CLRH)
,
,
,
I
-+i
,
!~_~ ~
~ ~:-
, ' . '
tcI(RSF) , I
,
'I
',1
II .1
4
th(SFC)j
~ 2~'-
,
"fI~SFC)
tL
_
'"
\
II
tw(R~1 14 .,
I:+-
~~~
~+~
.,
,
:::
l<1li- t8u(WCH)
See Note A
+I
:
l<1li-
taU(WCH)"+I.
,
14-~~
~'ii~~-==
3
I
-+I
,tsu(DCL)t
1<111
1
4
_,
I4f tau(DWL) t
1
.:
~ th(CLO) t --.!
1
~ th(WLD)t
1 th(RLO)
14- th(RDQ) -+i
,,-------
I+-- tcI(DCL) --+t
*t
Access time Is ta(CA) dependent.
Omput can go from the high-impedance state to
an invalid-data state prior to the spectlied access time.
Figure 37. Enhanced-Page-Mode Read/Write-Cycle Timing
-!11
ThxAs
INSTRUMENTS
'PoST OFFICE BOX 1443· HOUSlON. TEXAS 77261-1443
5-235
TMS55161
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS161B - OCTOBER 1993 - REVISED JUNE 1995
PARAMETER MEASUREME'NT INFORMATION
~
_ _--,j,1 14
~
~I
I t4
tt -.I !.-
14
tct(CHRL)
~
!-4t
iiiV tl" :+-
-. ~
,
lau(SFR) +'1
I 14
~
.11
...1 !+t-I tct(CHRL)
ow
po,
vt
lh(RsF) I~
~ lau(SFC)
,-+!
I
,I
1
1
1
I
I
~
I
I
I
-.JI
-+I
I
I f : ' "I
1I
1
(RA)
tw(RH)
tt
L(CL)
1
lh(RA)
I II
-.I i4+ Ia
I
tct(CLRH)
14
~II
CASx
tct(RLCH)
..
N"
~
I+- tct(RLCL) ~
~
ill
r i+I -+I ~
.1
I I~
~
I ,
.1
tw(RL)
tw(CH)
./ .
~ ... th(sFR),I,1
_ I I
~IIVII~
=~l!_
~ :.t
I
I
lh(RWM)
WE
lau(WMR) 14
14
14
I
I
T+!
~
!!
1+ ~
1 I
-?j
rr
tsu(WCH)
tau(WRH)
lh(RLW)
th(CLW)
teu(WCL)
.1
I~II
I
I
14
14:
I
1
1
~
-+I
,
t.t
I
.1
.1
.1
1
~
1'\Xlx?hl I 1
I
DQO'DQiS
I I
I I
I I
~ !4
.1~
tw(WL)
lau(DCL)
th(CLD) --"".~I
lh(RLD) - - - - - - . . . '
,
-M
-+t i4t
IaU(SFR}
"'(SFA)
1
W'YsN1-
1.1.!.iwv#
DSF~II~
-+I 14-
TRG
~I'
'&;&;Y I , ,
lauCTRG}
"I
1II1II
-H+I j+- -+t I4T
th(SFC)
lau{SFC}
,
:
:4
1
I
I
..
lau(WRH)! I
lau(WCH)
.,
-+! I4t
! N"
i+t
1
~
,
':
'II1II
, 1lt!(RLD)
,I
th(CLW)
I4t-t-
!
1
1
_
'II1II
tct(GHD) - . ,
'II1II
,
"'(RLW)
1 ,II1II
lau(WMR}
,
1
,
,
"II1II
~ ~
1
1
"'(WLG)
I~
i~
..,
"II '
1
1
1
~
~~
'-tWll
lau{DWL)
~ Jh(WLD)-.I
~~~5 ~
Valid Color Input
.1
~
Figure 39. Load·Color·Register·Cycie nmlng (late-Write Load)
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
5-237
TMS55161
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS181 B - OCTOBER 1993 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
I"
RAS
I"
..
CASx
I I"
~r
.1
"t..
r
'Q
1 ~ '~(CHRL) ~
tcI(CLRH)
YfT
tw(CL)
11
Ih(RLCA)
I"
AO-AB
~
teu(SFR)
I
_I
Ih(SFR)'
DSF
'Q
I11 i4t1
.1
-+i.
tcI(RLCA) I I"
. .1.. I I
I
tcI(CARH)
teu(RA) ~ I4t
II
I tel (CACH)
fh(RA) I 4.1 I+- -+i ~
~f!'(CLCA)
1
I
,0
L
.1 I ~ tw(RH) ~
1 =:i ,. .-- II
I
'~(RLCH)
.1"
tcI(CHRL)
tcI(RLCA)
.1
Iw(RL)
tt -+I I+-
tcI(RLCL)
.1
tc(W)
N
'1liJ' rr
_ _-,;1
.1
I.
I
I
I
I
I
I
I
I
"--
Iw(CH)
-+I
.
M" ....
-+l
I j+"- th(RSF)
jolt
-.! 1 1 1
14- 1 1+ teu(SFC)
-H
Block Address
A2-AB
1111 11r-t_
~IIJII!jIII
teu(TRG)
-+I
14- I+-
'i'RGWII~
I I
th(RWM)
. teu(Wfo'IR)""
1
1
I I
-ri
i+-
I4t
I
II
II
I" 1 1
tsu(WCH)
•
~
I 11
I I I"
-.I
!
~i'
I I"
II
teu(WRH)
tsu(WCL)
Ih(CLW)
~~
WE
teu(DQR)
-+I
Ih(RDQ)
DQO-DQ15
i4!-
1-+114-
1
.1
I.. I 1
-+j ~
1
='1.,;
..:':..f-. ~
~
1
·1
Ih(RLW)-----+l-:=-----=
tw(WL)
fh(RLD)
tsu(DCL)
_
.1
I
j 4 - - Ih(CLD) ----+j
3
1
_tlf..~'!7e'!~'!7e'!moeo~mooeoo~_
Figure 40. Block-Wrlte-Cycle Timing (Early Write)
Table 11. Block-Wrlte-CycleState Table
STATE
CYCLE
1
2
3
Block-write operation (nonmasked)
H
Don't cere
Column mask
Block-write operation with nonpersistent write-per-bit
L
Write mask
Column mask
Block-wrlte operation with persistent write-per-bit
L
Don't care
Column mask
Write-mask data
va write dIsable
1: va write enable
0:
Column-mask data 001- 001+ 3
(i a 0, 4. 8. 12)
0: column write disable
1: column write enable
~1ExAs
5-238
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
Example:
000 - column 0
001 - column 1
002 - column 2
003-column 3
=
(address AI = 0, M 0)
(address A1 ., 0, M .1)
(addrass AI .. 1, M .. 0)
(address AI .1. M = 1)
TMS55161
262144 BY 16-BIT
MULTIPaRT VIDEO RAM
SMVS181B - OCTOBER 18113- REVISED JUNE 1885
PARAMETER MEASUREMENT INFORMATION
DSF
i~
ill
I4{-i--
tcr(GHD)
r
I
~
tr.(CLW)
I I~
14..
I
1-+1 :W:~ I . I~
"u(WCH)
~II
--tI
tr.(RLW)
-+I
14
R
~;7
I
t.u(WRH)
tr.(WLG)
DQO-DQ15
III I
I~I
~I
I I
I
-i--+I
I ~I
~AI_:::::::t:.I."(!f.:~'{!fJ>I:I>I."(!f.'IIA~t:.I."1A
N~~~__tw_(W_I.)_ _
~
III
-+t i4t "u(DQR) ~ 1+ "u(DWI.)
I~ ~ tr.(RDQ) i+-1h(WLD) ~
1
I~
II
th(RLD)
~I
~.~~~
I~~~~~
~3_
Figure 41. Block-Wrlte-Cycle Timing (Late Write)
Table 12. Block-Wrlte-Cycle State Table
CYCLE
1
H
L
L
Block-wrHe operation (nonmasked)
Block-write operation with nonpersistent wrtte-per-blt
Block-write operation with persistent wrlte-per-bit
0: vO write disable
1: I/O write enable
Column-mask data 001- OQI+3
0: column write disable
0.0,4,8,12)
1: column wrHe enable
Wrlte-mask data
STATE
2
3
Oon'tcare
Column mask
Write mask
Column mask
Don't care
Column mask
Example:
000 - column 0 (address A1 .0, NJ .. 0)
DQ1 - column 1 (address A1 =0, NJ =1)
DQ2 - column 2 (address A1 • 1, NJ = 0)
DQ3 - column 3 (address A1 = 1, NJ 1)
=
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON.lliXAS 772111-1443
5-239
TMS55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS181B- OCTOBeR 1893- REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
AO-M
DSF
DQOD011
t Referenced to the first falling edge of CASx or the falling edge of WE, whichever occurs later.
NOTE A: To assure page-mode cycle time, 'fAG must remain high throughout the entire page-mode oparstlon If the late-write feature 18 used.
If the early-write cycle timing is used, the state of 'fAG is a don't cars after the minimum period 1i1(TRG) from the falling edge of!!iA!.
Figure 42. Enhanced-Page-Mode Block-Wrlte-Cycle Timing
Table 13. Enhanced~Page-Mode Block-Wrlte-Cycle State Table
STATE
CYCLE
2
3
BIock-write oparstlon (nonmasked)
1
H
Don't cars
Column mask
Block-wrlte operation with nonpersistent write-par-bit
L
Write mask
Column mask
Block-write ojl8ration with parsistent write-par-bit
L
Don't care
Column mask
0: I/O write disable
1: I/O. write enable
Column-mask data 001- 001+3
0: column write disable
O. 4, 8, 12)
1: column write enable
Write-mask data
o=
~1ExAs
5-240
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON, TEXAS 7721i1-1443
Example:
DQO - column 0 (address A1 •
DQ1 - column 1 (address A1
DQ2 - column 2 (address A1
003 - column 3 (address A1 •
0, AD • 0)
=0, AD =1)
=1, AD =0)
" AD. 1)
TMS55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS161B-OCTOBER 1993-REVISEDJUNE 1986
PARAMETER MEASUREMENT INFORMATION
14'.1----- tc(rd)
~,
--------------------~~:r~~----~-~-~----~Jlt1
~
-+l1+-1t
~ ~~H) -+/
tcI(CHR~ -jol.__--t>!~: :
tcI(RHC~ M
-+' I+- tcI(CHR~
~Il
I~
,,
OQOOQ1S
Figure 43. RAS·Only Refresh-Cycle TIming
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lexAS 77251-1443
5-241
TMS55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMV$161 B- OCTOBER 1883- REVISED JUNE 1986
PARAMETER MEASUREMENT INFORMATION
I~
tc(rd) ----------'~t>l1
114~--- tw(RL) ------'~t>l1
I+-- tw(RH) ---+I
AD
fi
__oJ!~
i
~I
tcI(RHCL)
~~~tcI,.(_CLR~L) I~
CAli
mwt '4
'I!--______
I
~I ~ tcI(RLCH) ~
-+1 t+-lt
V
II
1
VI
N
I
, I
14-- tcI(CHRL) --+t I
I r
teu(RA) -fooII1~1---l~
..1
AO-Aa
""'~~'""'~-'"""~
!OIIII'~f--"'~"""1-
"'(RA)
II
1 1
teu(SFR) -Io1~
___--..t~I""
1OIIIIf--"'~*",-
"'(SPA)
DOF~:':~
-~
WE~
3
DQO-DQ16
Figure 44. CBR-Refresh-Cycle nmlng
Table 14. CBR-Cycle State Table
STATE
CYCLE
1
CBR refresh with option reset
CBR refresh with no reset
3
H
Don't care
2
L
H
Stop address
H
L
Don't care
eBR refresh with stop point set and no reset
~1ExAs
5-242
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
H
TMS55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS181 B - OCTOBER 1883 - REVISED JUNE 1985
'.
I~
I
II
PARAMETER MEASUREMENT INFORMATION
,~
,I
AIJ-AS
DSF
DQODQ15
Figure 45. Hldden-Refresh-Cycle Timing
Table 15. Hidden-Refresh-Cycle State Table
CYCLE
1
CBR refre8h with option reset
Don't care
Don'lcare
CBR refre8h )NIth no reset
CBR refresh with stop point set and no option reset
Stop addl988
STATE
2
L
H
H
3
H
H
L
~1ExAs
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON, TEXAS 77251-1443
5-243
TMS55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS161 B - OCTOBER 1993 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
14
tc(TRD)
-----..;,Tf
I 14
ld(RLCL)
J ~I
4
ld(RLCtQ
~
~
U
'w(RL)
I
~
'w(RtQ
--It..:~
---
~14t---~'
14-+ ld(CARtQ
I
II
II.
I
~
I j4-ld(RLCA) --tI ~ 'w(CL)--tV
ld(CHRL)
vvvvvJ.
I r~. ~
-.I!.i=
t~~!I.14 ~~
=114
~:7~~~~
AD-AS
th(RA) --:
_-i04rt--~1i
DSF
~
taU(TRG) 14
tau(CA)
I
~r-----:-
lh(TRG)
I
I
I
.
.
~ i ~ w{:e4##~"lO~~~
~.!!-~
I
I
DQO-
0016
1414
I
'w(SCH)
,I.
---'/1re-
SC
ItI(SHSO)
so
14
Old Data
OSF
H
ld(SCTR)
~I
I
I
I
14
Ih
HI..z+I---"-I----------
~I ld(6LStQ 4
~
ld(RLStQ
.
~
I
l1li
..
~
I
I
~
'w(SCL)
l~~\\\\\\}1\\\\~~~'w(sctQ ~\
*
I
.
.:
_
ta(SO) ~
~1.1
14
I
I
I:!
Old
Da~
~
14
J]
~
tc(sC)
~- :--~ir-I_ _ _ __
I4---.,-ld(GHOSF).
~
-.!~I
___
New Data
Tap Point Bit A7
ld(CLOSF)
.t
ld(RLOSF) - - - - -......
L -------------------------------NOTES: A. DO outputs remain In the high-Impedance state for the entire memory-to-data-reglster-transfer cycle. The
memory-to-data-reglster-transfercycle Is used to load the data registers In parallel from the memory array. The 258 Iocatlona In each
data register ere written Into from the 258 corresponding columna of the aelected row.
B. Once data Is transferred Into the data registers. the SAM Is In the aerial read mode Q.e•• SO Is enabled). allowing data to be shifted
out of the registers. Also. the first bit to read from the data register after fFiG has gone high must be activated by a positive tranaltlori
,
of~
C. NJ - A7: register tap point: All: ident,,*, the half of the transferred row
O. Early-load operation Is defined as Ih(TRG> min < Ih(TRG) < id(RLTH) min.
Figure 46. Full-Reglster-Transfer Read Timing, Early-Load Operations
~1ExAs
5-244
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77261-1443
TMS55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS181 B- OCTOBER 1l1li3 - REVISED JUNE 1985
PARAMETER MEASUREMENT INFORMATION
I.!
*-~~~~
----tt,
I /4
I
IcJ(CHRL) --!;.....
~
IcJ(RLCH)
I
i j..-1cJ(RLCA) --., ~ tw(CL)
:
~ tt.(RA) -+I
I
m§§*
I
I
I
I+t 1eu(CA)
L ~
~
~~ ~'-__
U
LJ
1
~
I
Y
1
I
I
:
I
:
I ,
I
~tt.(CLCA)
:+- ~~~~~
~
teu(SFR) -J+-----+I 14
~IIII
~II
DSF
~
I.-- th~LCA)
teu(RA) ~
II
AO-AI
Ic{TRD)
tt.(SFR) I
I
I
I
I I
MWI~
DQO-D015
I"
tw(SCH)
SC
/!I
~I
I,
I•. ~
j4-te(SO) ~ I"
1wI I
tt.(SHSQ) ~
91 I
_--J
so
I
I
Old Data
*
I
QSF
j4
~ IcJ{THSC)
II III HI-Z-+I---...
I----------I
I
):
\:I
YTI
\'--_-JI!I
I'
I
-
~ tw(SCL)
~14--Ic(sC)
I
14- te(SQ) ~
: : tt.(SHSO) I0Il
,
Old Data
I
X.
~
liro------
Old Data
~
N_ Data
~-----
H------~;------~~~==~~~IcJ;~;L~~;.:;H=Q=S=~~~~:~;--~_p_~_I_nt_B_R_~_7
__
I..
IcJ(RLQ~
~I
L---------------~-~-------------A. DO outputs remaln in the high-impedance state for the entire memory-to-data-reglster-tran8fer cycle. The
SE
NOTES:
memory-to-data-reglstar-tran8fer cycle is used to load the data registers In parallel from the memory array. The 256 locations
In each data register are writtan Into from the 256 corrssponding columns of the selected row.
B. Once data Is transferred into the data registers, the SAM Is In the serial read mode (I.e., sa is enabled), allowing data to be shifted
out of the registars. Also, the first bit to read from the data register after 'i'RG has gone high must be activated by a positive
transition of SC.
.
C. AO-A7: reglstar tap point; AS: idantifles the half of the transferred row
D. Late load operation is defined as !d{THRH) < 0 ns.
'
Figure 47. Full-Register-Transfer Read nmlng, Real-nme Load OperatlonJLate-Load Operatlo"
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
5-245
TMS55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS181 B- OCTOBER 1893 -REVISED JUNE 189S
PARAMETER MEASUREMENT INFORMATION
14
tc{TRO)
, I~
.,
.1
tw(RL)
! J.:
, I+- tci(RLCL) -+I
---"'!iN
tci(CHRL)
-l++! I
'I~
1
y(
1
- . I
...-,
\
\-.- - - - -
r-14
_l',rIw(ClJY i
:+- I
I
~
~ I~ I
tci(RLCH)
tt.~~~
AD-AS
!+- tw(RH) ~
~
==
II
I'~
.1
tw(CH)
.
..
. _ 1
~ R~.~TaPPolntAD-AS_~_
teu(RA), : '
teu{TRQ)
-+!
I
~
~
I+-~
I
S.. Note A
.
~III
~II
teu(SFR)-+j
OSF
-t+I !+- tt.(SFR)
I
1
~
4 1 - _ 1
§ ~§
§WI!.
!+
tt.(RWM)
teu(WMR)+j
1
~
+ - _ 1
WErnwl.
I
I
I
OQO0015
tci(MSRL)
HI-Z--....
I -----------
I
-l4--·~1
tc(SC)
tci(RHMS)
-.j :+-
: I+-- tc(SC) --+l
I
sc
Bit 127 or
Bit 255
so
TapPolntM
,
,
., tci(SCQSF)
,
X
QSF
,----,
tci(SCQSF)
MSB
,~
Old~~
Bit 127 or
Bit 255
I
Tap
PolntN
I++t- te(SO)
~
X
NawMSB
H
IE L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~~--------------
S'j
NOTE A:. AD-AS: tap point of the given half; A7: don't care; AS: Identifies the DRAM row half
Figure 48. Split-Register-Transfer Read Timing
~1ExAs
5-248
INSTRUMENTS
POST OFFICE BOX 1~· HOUSTON, lEXAS 77251-1~
TMS55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS181 B - ocroBER 1883 - REVISED JUNE 11196
~
14
I
SQ
SE
i: ~
·~----"'I~ Iw(SCH)
Iw(SCH)
I
I
I
:\. r-1w(SC~ -.,
----I,1\!.~ lw(Sc~ --.1.0
~
-----I_
~
14-
~I
~I
tc(SC)
I
j4
I
-.I
'h(fRO)
14-14--- tc(SC)
~
SC
~~:--------------------------------I"III~----I~M-
I
~
ta(SQ)
I4t th(SHSQ)
'h(SHSQ)
valid Out
r
--MI"I--~~I
I
~
~
I
I
I
I
I
.\.\. ,__
l-
i"
ta(SQ)
M
th(SHSQ)
valid Out
1w(SCH)
.L
JIf
~
~
14 .-I
~
I
ta(SQ)
X
valid Out
ta(SE)
----~~~!____________________________________~----------------
NOTE A: While the data is being read through the seriai-data registar, 'i'RG" Ie a don't care, except '1'Rtt must be held high when RAS goes low.
This Ie to avoid the Initiation of a registar-data transfer operation.
Figure 49. Serlal-Read-Cycle Timing (SE = VIL>
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
J
I
PARAMETER MEASUREMENT INFORMATION
teu(TRG) ---:
!
5-247
TMS55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS181B-OCTOBER 1983-REVlSeDJUNE 1985
PARAMETER MEASUREMENT INFORMATION
-~~
liAS
.
~
TRG
.1
1
1
~ Iw(SCH)
l1li
1
\t14-1w(SCL) --.I 1
l1li
II1II
I
Iw(SCH)
SC
~
~
SE
YalldOut
~
14
~
SQ
Itt(TRG)
-
~.
~
te(SC)
\
~
i4-1w(SCL)
-.10
1
j4+Itt(SHSQ)
*
YalidOut
1
)
fell.(SE)
1
1w(SCH)
\
1
I~
te(SQ)
-+I I+-
~
te(SE)
!~
1
~
I
1
I4--*-
~
.,
vr
1
~
te(SQ)
I 1
1
te(SC)
YalldOut
~
I
~I
te(SQ)
Itt(SHSQ)
M
YaiidOut
I
I
~
NOTE A: While the data Is being read through the serlai-data regiSter. TRG Is a don't care except TRG must be held high when RAS goes low.
This is to avoid the initiation of a reglster-data treoster operation.
Figure 50. Serlal-Read-Cycle Timing (SE-Controlled Read)
~1ExAs
5-248
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS55161
262144 BY 16-BIT
MULTIPaRT VIDEO RAM
SMVS161 B - OCTOBER 1993 - REVISED JUNE 1996
RAS
PARAMETER MEASUREMENT INFORMATION
,
,
I
ril,
~~r--
aSx
ADDR
::x:::::x:::::x. . . --l--~~~
RowTap1
(low)
'i'RG
DSF
r,~r--
I'
(hIgh)
1
' - I.....----+----,.\......1
(low)
1
----,...........,1\
1
1
1
1
Ij~~r-1
I
I
CASE I
I
1
~II ~II
Bit
~
SC
Tap1
127 (hIgh)
\
/I
!J
255
It
jJ
--------~----~--------------~j~
I
I
I
I
CASE II
SC
n-
Ij~~r--
1
QSF
(hIgh)
I
I
I
I
1
1
Tap2
(low)
\
127
I'
r
j~
-------j.---~~~~
(low)
1271 (high)
I 255 (low)
127
IL-..!/)~ I \
r
I
QSF
\
-------i-----~~~~~
(low)
QSF
j~
I
1
1
1
1
1
1
CASElli
SC
I'
--------~----~--------------~j~
1271 (high)
------..J\----III--------~/jH'
1
Full-Reglater -Tranafer Read 1
I
Spilt Reglater to the
High Half of the
Data Reglater
I
1
I
1
1/,
Spilt Register to the
Low Half of the
Data Reglater
255
(low)
II \'
1
I
127
\r---F
Spilt Register to the
High Half of the
Data Reglater
NOTES: A. In order to achieve proper spilt-register operation. a full-register-transfer read shouid be performed before the first
spilt-register-transfer cycle. This is necessary to Initialize the data register and the starting tap location. First aerial access can then
begin either after the fuii-register-transfer read cycle (CASE I). during the first split-register-transter cycle (CASE II). or even after
the first split-register-transfer cycle (CASE III). There Is no minimum requirement of SC clock between the fuil-register-transfer reed
cycle and the first spllt-register cycle.
B. A spHt-register-transfer into the inactive half is not allowed until fd(MSRL) is met. fdCMS...RL) is the minimum delaytlme between the
rising edge of the serial clock of the last bit (bit 127 or 255) and the falling edge of RAS of the split-register-trensfer cycle into the
inactive half. After the fd(MSRL) requirement Is met. the split-register-transfer into the inactive half mllst also satisfy the minimum
fd(RHMS) requirement. fd(RHMS)is the minimum delaytlme between the rising edge of RAS of the spllt-reglster-transfer cycle into
the inactive half and the rising eOge of the serial clock of the last bit (bit 127 or 255).
Figure 51. Split-Register Operating Sequence
~ThxAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
5-249
TMS55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS181 B - OCTOBER 1993 - REVISED JUNE 1995
device symbolization
"¥
Speed(- 80, -70, ~80)
TMS56161~
PaekagaCode
F
R
A~T
I
Lot Traceability Code
Date Code
AaaambIy Site Code
DleRIlVllIon Code
WarerFabCode
~1ExAs
5-250
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS55166
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVSl88B-OCTOBER 1993-REVISEDJUNE 1895
DGHPACKAGE
(TOPVJEW)
• Organization:
- DRAM: 262144 Words)( 16 Bits
- SAM: 256 Words)( 16 Bits
• Dual-Port Accessibility - Simultaneous and
Asynchronous Access From the DRAM and
SAM Ports
• Data Transfer Function From the DRAM to
the Serial Data Register
• (4)( 4) )( 4 Block-Write Feature for Fast Area
Fill Operations. As Many as Four Memory
Address Locations Written Per Cycle From
the 16-BIt On-Chip Color Register
• Write-Per-Bit Feature for Selective Write to
Each RAM I/O. Two Write-Per-Bit Modes to
Slmp"fy System Design
• Byte Write Control (WEL, WEU) Provides
Flexibility
• Extended Data Output for Faster System
Cycle Time
• Enhanced Page-Mode Operation for Faster
Access
• CAS-Before-RAS (CBR) and Hidden
Refresh Modes
• Long Refresh Period
Every 8 ms (Max)
• Up to 55-MHz Uninterrupted Serial Data
Streams
• 256 Selectable Serial Register Starting
Locations
• §E-Controlled Register Status QSF
• SplIt Register-Transfer Read for Slmp"fled
Real-Time Register Load
• Programmable Spilt-Register Stop Point
• 3-State Serial Outputs A"ow Easy
Multiplexing of Video Data Streams
• All Inputs/Outputs and Clocks TTL
Compatible
• Compatible With JEDEC Standards
• Texas Instruments EPIC'" CMOS Process
• Designed to Work With the
Industry-Leading Texas Instruments
Graphics Fam"y
• Performance Ranges:
ACCESS TIME
ROW ENABLE
TMS55168-60
TMS55188-70
TMS55188-60
ACCESS TIME
SERIAL DATA
fa(R)
t.(SQ)
DRAM
CYCLE TIME
(MAX)
(MAX)
SOns
70ns
SOns
15na
20ns
25ns
(MIN)
110 ns
130ns
150ns
tc(W)
Vee
10
2
ea
Vss
3
4
12
sao
55
SQ15
DQ15
8014
D014
57
Vee
10
55
55
SQ13
DQ13
SQl1
DOli
5
eo
SQl
DOl
8
7
8
58
SQ2
,
D02
11
54
SQ5
II
13
14
15
18
17
18
18
&2
51
50
48
48
47
48
DOS
20
45
SQ7
21
44
DQ7
22
Vss
23
24
25
28
43
42
41
40
SQ3
DQ3
Vss
SQ4
DQ4
SQ5
DOS
Vee
WEi:
WEU
RA8
Nl
A7
Nl
AS
M
Vee
BE
Vsa
81
DQO
Vee
SO
84
TRG
27
28
2t
30
31
32
ea
Vss
8011
DOlI
8010
DOlO
Vee
SQ8
DQ8
SQ8
DQ8
Vss
DSF
NC/GND
38
CAS
38
37
38
QSF
AO
AI
AI
35
34
AS
33
vaa
PIN NOMENCLATURE
AO-AS
CAS
OQO-OQ15
DSF
NC/GND
QSF
RAS
SC
SE
SQO-SQ15
TRG
Vec
~WEL,WEU
Address Inputs
Column-Address Strobe
DRAM Data I/O, Write Mssk Data
Special Function Select
No Connect/Ground
(Important not connected Internally to VSS>
Special Function Output
Row-Address Strobe
Serial Clock
Serial Enable
Serial Data Output
Output Enable, Transfer Select
5-V Supply (TYP)
Ground
DRAM Byte Writs Enable Select8
DRAM
SERIAL
OPERATING CURRENT
PAGE MODE CYCLE TIME SERIALPORT STANDBY
tc(p)
tc(SC)
1cc1
(MIN)
(MIN)
(MAX)
30ns
18ns
180mA
30ns
22na
165mA
35na
150mA
30ns
OPERATING CURRENT
SERIAL PORT ACTIVE
1cc1A
(MAX)
225mA
205mA
185mA
EPIC Is a trademark of Texas Instruments Incorporated.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON, TEXAS 77251-1443
Copyright 0 1995, Texas Inalrumen18 Inc:orporated
5-251
TMS55166
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS188B- OCTOBER 1993 - REVISED JUNE 1995
description
The TMS55166 multiport video RAM is a high-speed dual-ported memory device. It consists of a dynamic
random-access memory (DRAM) organized as 262 144 words of 16 bits each interfaced to a serial data register
[serial-access memory (SAM)] organized as 256 words of 16 bits each. The TMS55166 supports three basic
types of operation: random access to and from the DRAM, serial access frOin the serial register, and transfer
of data from any row in the DRAM to the serial register. Except during transfer operations, the TMS55166 can
be accessed simultaneously and asynchronously from the DRAM and SAM ports.
The TMS55166 Is equipped with several features designed to provide higher system-level bandwidth and to
simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates can
be achieved by the device's (4 x 4) x 4 block-write feature. The block-write mode allows 16 bits of data (present
in an on-chip color data register) to be written to any combination of f()ur adjacent column address locations.
As many as 64 bits of data can be written to memory during each CAS cycle time. Also on the DRAM port, a
write mask or a wrlte-per-bit feature allows masking of any combination of the 16 inputs/outputs on any write
cycle. The persistent write-per-bit feature uses a mask register which, once loaded, can be used on subsequent
write cycles without reloading. The TMS55166 also offers byte control. Byte control can be applied in write
cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. The TMS55166 also
offers extended output mode. The extended output mode is effective in both the page-mode and standard
DRAM cycles.
The TMS55166 offers a split-register-transfer read (DRAM to SAM) feature for the serial register (SAM port).
This feature enables real-time register load implementation for truly continuous serial data streams without
critical timing requirements. The register is divided into a high half and a low half. While one half is being read
out of the SAM port, the other half can be loaded from the memory array. For applications not requiring real~time
register load (for example, loads done during CRT retrace periods), the full-register mode of operation is
retained to simplify system design.
The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up
to 55 MHz. During the split-register-transfer read operations, internal circuitry detects when the last bit position
is accessed from the active half of the register and immediately transfers control to the opposite half. A separate
output, QSF, is included to indicate which half of the serial register is active.
All inputs, outputs, and clock signals on the TMS55166 are compatible with Series 74 TIL. All address lines
and data-in lines are latched on chip to simplify system design. All data outs are unlatched to allow greater
system flexibility.
The TMS55166 employs state-of-the-art Texas Instruments EPIC'" scaled-CMOS, double-level
polysilicon/polycide gate technology for very high performance combined with low cost and improved reliability.
The TMS55166 is offered in a 64-pin small-outline gull-wing-Ieaded package (DGH suffIX) for direct surface
mounting.
The TMS55166 and other TI multiport video RAMs are supported by a broad line of graphics processors and
control devices from Texas Instruments.
~1EXAS
5-252
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS55166
262144 BY 16-BIT
MULTIPORTVIDEO RAM
SMVS188B- OCTOBER 1993 - REVISED JUNE 1995
functional block diagram
_-iii)
r--------.,
. ._ _ 1
1
1
~
1
• ,.___1
1
1 of 4 Sub-Blocks
(see next page)
1
OSF
1L _ _ _ _ _ _ _ _ .J1
r--------.,1
1
-~
.mt..._.~column
114
r<
Buffer
1 of 4 Sub-Blocks
9
(see next page)
OQOOQ15
,..---.
AO-AS
1
1
L ________ .J1
r--------.,
_ . .1
1
11
1 of 4 Sub-Blocks
(see next page)
1
I
1
L _ _ _ _ _ _ _ _ .J
SQO-SQ15
16
Serlal-
Output ~_.11
Buffer ("j
r--------.,
1
I
1
1 of 4 Sub-Blocks
(see next page)
Timing
Generator
1
1L _ _ _ _ _ _ _ _ .J1
-!I11EXAS
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON, TEXAS 77251-1443
5-253
TMS55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS188B- OCTOBER 1,,"-REvIsED JUNE 1995
functional block diagram· (continued)
sc
SQI --4-r--:----:-~
SQI + 1 -"';ci';b;:;t~1Il
SQI+2 --4-1
SQI + 3 --4-L_..J
1 of 4 Sub-Blocks
~1ExAs
5-254
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, ~ 77251-1443
TMS55166
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS166B- OCTOBER 1993 - REVISED JUNE 1995
Table 1. Function Table
CAS
FALL
RASFALL
ADDRESS
DQO-DQ15t
FUNCTION
Reserved (do not use)
CBR refresh (no reset) and stop point
MNE
CODE
RAS
CASt
RAS
WEL
WEU
CAS
X
X
X
X
X
-
H
X
Stop
Point'
X
X
X
CBRS
CAS
TRG
WEx*
DSF
DSF
L
L
L
L
set' .
L
X
L
CBR refresh (option reset)1I
L
L
L
X
X
H
CBR refresh (no reset)*
H
H
X
X
X
X
X
X
X
X
X
X
CBRN
Full-reglster-transfer read
H
L
H
L
X
Row
Addr
Tap
Point
X
X
RT
Spllt-reglster-transfer read
H
L
H
H
X
Row
Addr
Tap
Point
X
X
SRT
DRAM write (nonmasked)
H
H
H
L
L
Row
Addr
Col
Addr
X
Valid
Data
RW
DRAM write (nonpersistent write-per-blt)
H
H
L
L
L
Row
Addr
Col
Addr
Write
Mask
Valid
Data
RWM'
DRAM write (persistent write-par-bit)
H
H
L
L
L
Row
Addr
Addr
X
Valid
Data
RWM
DRAM block write (nonmasked)
H
H
H
L
H
Row
Addr
Block
Addr
A2-AB
X
Col
Mask
BW
DRAM block write
(nonpersistent wrlte-per-bit)
H
H
L
L
H
Row
Addr
Block
Addr
A2-AB
Write
Mask
Col
Mask
BWM
DRAM block write
(persistent write-per-bit)
H
H
L
L
H
Row
Addr
Block
Addr
A2-AS
X
Col
Mask
BWM
Load write mask register c
H
H
H
H
L
Refresh
Addr
X
X
Write
Mask
LMR
Load color register
H
H
H
H
H
Refresh
Addr
X
X
Color
Data
LCR
Col
CBR
Legend:
X
.. Don'tcare
Col Mask
= H: Write to address/column enabled
Write Mask = H: Write to I/O enabled
t 000-0015 are latched on either the first falling edge ofWEx or the falling edge of CAS, whichever occurs later.
* Logic L is selected when either or both WEL and WEU are low.
§ The column address and block address are latched on the falling edge of CAS.
, CBRS cycle should be performed Immediately altar the power-up initialization cycle.
/I AO-A3, AS: don't care; A4-A7: stop-point code
II CBR refresh (option reset) mode ends persistent wrlte-per-blt mode and stop-point mode.
*CBR refresh (no reset) mode will not end persistent write-per-bit mode or stop-point mode.
c Load-write-mask-register cycle sets the persistent writs-per-blt mode. The persistent write-per-bit mode is reset only by the CBR (option reset)
cycle.
-!!1ThXAS
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON, TEXAS 77251-1443
5-255
TMS55166
262144 BY 16-BI1
MULTIPORT VIDEO RAM
SMVS186B - OCTOBER 1993 - REVISED JUNE 1995
Table 2. Pin Description Versus Operational Mode
PIN
AO-AS
DRAM
TRANSFER
Row, column address
Row address, tap point
~
Column-address strobe, DQ output enable
Tap-address strobe
DQ
DRAM data I/O, Write mask
DSF
Block-write enable
Write-mask-reglster-Ioad enable
Color-reglster-load enable
CBR (option reset)
Split-register-transfer enable
m
Row-address strobe
Row-address strobe
SAM
~
SQ output enable,
QSF output enable
se
SQ
Serial clock
Serial data output
'i"Im:
WEe
WED'
OQ output enable
Transfer enable
WrIte enable, Wrlte-per-bit enable
Serlal-reglster statuI
QSF
NClGND
VCCt
Make no extemal connection or tie to system GND
5-V8UPPIy
Ground
vsst
t For proper devlos operation, all Vee pins must be connected to a 5-V 8UPPly and all VSS pins must be tied to ground.
pin definitions
address. (AO-A8)
Eighteen address bits are required to decode one of 262 144 storage cell locations. Nine row-address bits are
set up on pins AO-A8 and latched onto the chip on the falling edge of RAS. Nine column-address bits are set
up on pins AO-A8 and latched onto the chip on the falling edge of CAS. All addresses must be stable on or before
the falling edge of RAS and the falling edge of CAS.
During the full-register-transfer read operation, the states of AO-M are latched on the falling edge of RAS to
select one of the 512 rows where the transfer occurs. At the falling edge of CAS, the column-address bits AO-A8
are latched. The most Significant column-address bit (A8) selects which half of the row Is transferred to the SAM.
The appropriate 8-blt column address (AO-A7) selects one of 256 tap points (starting positions) for the serial
data output.
During the split-register-transfer read operation, address bit A7is ignored at the falling edge of CAS. An internal
counter selects which half of the register is used. If the high half of the SAM is currently in use, the low half of
the SAM Is loaded with the low half of the DRAM half row, and vice versa. Column address (M) selects the
DRAM half row. The remaining seven address bits' (AO-A6) are used to select 1 of 127 possible starting
locations within the SAM. locations 127 and 255 are not valid tap polnts~
row-address strobe (RAS)
RAS Is similar to a chip enable, so that all DRAM cycles and transfer cycles are initiated by the falling edge of
RAS. RAS is a control Input that latches the states of the row address, WEL, WEU, TRG, CAS, and DSF onto
the chip to Invoke DRAM and transfer functions of the TMS55166.
-!11 TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAl77251-1443
TMS55166
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS166B - OCTOBER 1993 - REVISED JUNE 1996
column-address strobe (CAS)
CAS is a control input that latches the states of the column address and DSF to control DRAM and transfer
functions of the TMS55166. CAS also acts as output enable for the DRAM output pins, DOO-D015.
In transfer operations, address bits AO-AS are latched at the falling edge of CAS as the start position (tap) for
the serial data output (SOO-S015).
output enable/transfer select (TRG)
The TRG pin selects either DRAM or transfer operation as RAS falls. For DRAM operation, TRG must be held
high as RAS falls. During DRAM operation, TRG functions as an output enable for the DRAM output pins,
DOO-D015. For transfer operation, TRG must be brought low before RAS falls.
write mask select, write enable (WEL, WEU)
In DRAM operation, WEL enables data to be written to the lower byte (DOO-D07) and WEU enables data to
be written to the upper byte (DOS-D015) of the DRAM. Both WEL and WEU have to be held high together to
select the read mode. Bringing either or both WEL and WEU low selects the write mode.
WEL and WEU are also used to select the DRAM write-per-bit mode of operation. If either or both WEL and WEU
are brought low on the falling edge of RAS, the write-per-bit operation is invoked. The TMS55166 supports both
the nonpersistent write-per-bit mode and the persistent write-per-bit mode.
special function select (OSF)
The DSF input is latched on the falling edge of RAS or CAS similar to an address. DSF determines which of
the following functions are invoked on a particular cycle:
•
•
•
•
•
•
CBR refresh with no reset (CBRN)
CBR refresh with no reset and stop-point set (CBRS)
Block write (BW, BWM)
Loading write-mask register for the persistent write-per-bit mode (LMR)
Loading write-color register for the block-write mode (LCR)
Split-register-transfer read (SRT)
ORAM data I/O, write mask data (OQO-OQ15)
DRAM data is written or read through the common 1/0 DO pins. The 3-state DO output buffers provide direct
TIL compatibility (no pullup resistors) with a fanout of one Series 74 TIL load. Data out Is the same polarity
as data il1. The outputs are in the high-impedance (floating) state as long as either TRG or CAS is held high.
Data does not appear at the outputs until after both CAS and TRG have been brought low. The write mask is
latched into the device via the random DO pins by the falling edge of RAS and is used on all write-per-bit cycles.
In a transfer operation, the DO outputs remain in the high-Impedance state for the entire cycle.
serial data outputs (SQO-SQ15)
Serial data is read from the SO pins. The SO output buffers provide direct TIL compatibility (no puilup resistors)
with a fanout of one Series 74 TIL load. The serial outputs are in the high-impedance (floating) state as long
as the serial enable pin, SE, is high. The serial outputs are enabled when SE is brought low.
serial clock (SC)
Serial data is accessed out of the data register from the rising edge of SC. The TMS55166 is designed to work
with a wide range of clock duty cycles to simplify system design. There Is no refresh requirement because the
data registers that comprise the SAM are static. There is also no minimum SC operating frequency.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS55166
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVSl68B- OCTOBER 1993 - REVISED JUNE 1895
serial enable (SE)
During serial-access operations, SE Is used as an enable/disable for the SO outputs. SE low enables the serial
data output. SE high disables the serial data output. SE is also used as an enable/disable for output pin OSF.
IMPORTANT: While SE is held high, the serial clock is not disabled. External SC pulses Increment the internal
serial-address counter regardless of the state of SE. This ungated serial clock scheme minimizes access time
of serial output from SE low because the serial clock Input buffer andtbe serial-address counter are not disabled
~~
.
special function output (OSF)
OSF is an output pin that indicates which half of the SAM is being accessed. When OSF Is low, the serial-address
pointer is accessing the lower Oeast significant) 128 bits of the serial register (SAM). When OSF is high, the
pointer is accessing the higher (most significant) 128 bits of the SAM. OSF changes state upon crossing a
boundary between the two SAM halves.
During full-register-transfer operations,· OSF can change state upon completing the cycle. This state is
determined by the tap point loaded during the transfer cycle. The OSF output is enabled by SE. If SE is high,
the OSF output Is In the high-Impedance state.
no connect/ground (NC/GND)
The NC/GND pin should be tied to system ground or left floating for proper device operation.
~1ExAs
5-258
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lEXAS 77261-1443
"',
TMS55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS166B - OCTOBER 1993 - REVISED JUNE 1995
functIonal operatIon descrIptIon
random access operation
Table 3. DRAM Function Table
CAS
FALL
RASFALL
ADDRESS
OQO-OQ15t
FUNCTION
CAS
Reserved (do not use)
CBR refresh (no reset) and stop point
set'
CBR refresh (option reset)1I
L
TAG WEi*
L
L
MNE
CODE"
RAS
CASt
RAS
WEL
WEU
CAS
X
X
X
X
X
-
X
X
X
CBRS
CBRN
DSF
OSF
L
L
X
L
H
X
Stop
Point'
L
L
X
X
H
CBR refreSh (no reset)*
H
L
H
X
X
X
X
X
X
X
X
X
X
DRAM write (nonmasked)
H
H
H
L
L
Row
Addr
Col
Addr
X
Valid
Data
RW
DRAM write (nonparsistent write-per-bit)
H
H
L
L
L
Row
Addr
Col
Addr
Write
Mask
Valid
Data
RWM
DRAM write (persistent write-par-bit)
H
H
L
L
L
Row
Addr
Col
Addr
X
Valid
Data
RWM
DRAM block write (nonmasked)
H
H
H
L
H
Row
Addr
Block
Addr
A2-AS
X
Col
Mask
BW
DRAM block write
(nonparsistent write-per-bit)
H
H
L
L
H
Row
Addr
Block
Addr
A2-AS
Write
Mask
Col
Mask
BWM
DRAM block write
(persistent write-par-bit)
H
H
L
L
H
Row
Addr
Block
Addr
A2-A8
X
Col
Mask
BWM
Load write-mask register c
H
H
H
H
L
Refresh
Addr
X
X
Write
Mask
LMR
Load color register
H
H
H
H
H
Refresh
Addr
X
X
Color
Data
LCR
CBR
Lagend:
X
• Don'tcare
Col Mask
• H: Write to address/column enabled
Write Mask
H: Write to I/O enabled
t 000-DQ15 are latched on either the first falling edge of ~ or the falling edge of CAS, whichever occurs later.
Logic L is selected when either or both WE[ and WEiJ are low.
SThe column address and block address are latched on the failing ecige of CAS.
t CBRS cycle should be performed immediately after the power-up initializaiion cycle.
, AfJ-A3. AS: don't care; AA-A7: stop-point code
II CBR rafresh(optlon reset) mode ends perslstentwrite-per-bit mode and stop-point mode.
*CBR rafresh (no reset) mode will not end persistent write-par-bit mode or stop-point mode •
.CLoad-write-mask-reglster cycle sets the persistent write-per-bit mode. The persistent write-per-blt mode Is reset only by the CBR (option reset)
cycle.
=
*
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
5-259
TMS55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS186B -OCTOBER 1993 - REVISED JUNE 1995
enhanced page mode
Enhanced-page-mode operation allows faster memory access by keeping the same row address while
selecting random column addresses. This mode eliminates the time required for row-address setup,
row-address hold, and address multiplex. The maximum RA8.low time and minimum CAS page cycle time are
used to determine the number of columns that can be accessed.
Unlike conventional page-mode operations, the enhanced page mode allows the TMS55166 to operate at a
higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CAS
transitions low. A valid column address can be presented immediately after the row-address hold time has been
satisfied, usually well in advance ofthe falling edge of CAS. In this'case, data is obtained after taCO) max ( access
time from CAS low) If ta(OA) max (access time from column address) has been satisfled.
refresh
CAS-before-RAS (CBR) ",',.,sh
CBR refreshes are accomplished by bringing CAS low earlier than RAB. The external row address is Ignored,
and the refresh row address is generated intern~lIy. Three types of CBR refresh cycles are available. The CBR
refresh (option reset) ends the perSistent write-per-bit mode and the stop-point mode. The CBRN and CBRS
refreshes (no reset) do not end the persistent write-per-bit mode or the stop-point mode. The 512 rows of the
DRAM do not necessarily need to be refreshed consecutively as long as the entire refresh is completed within
the required time period, trf(MA)' The output buffers remain In the high-impedance state during the CBR refresh
cycles regardless of the state of TRG.
hidden ",',.,sh
A hidden refresh is accomplished by holding CAS low in the DRAM read cycle and cycling RAS. The output data
of the DRAM read cycle remains valid while the refresh is being carried out. Like the CBR refresh, the refreshed
row addresses are generated internally during the hidden refresh.
RAS-on/y refresh
A RAS-only refresh is accomplished by cycling RAS at every row address. Unless CAS and TRG are low, the
output buffers remain In the high-impedance state to conserve power. Externall~erated addresses must be
supplied during RAS-only refresh. Strobing each ofthe 512 row addresses with RAS causes all bits In each row
to be refreshed.
extended data output
The TMS55166 features extended data output during DRAM accesses. While RAS and TRG are low, the DRAM
output remains valid even when CAS returns high. The output remaIns valid until WEx Is low, 'fRG' Is high, or
both CAS and RAS are high. The extended-data-output mode functions In all read cycles including DRAM-read,
page-mode-read, and read-modify-write cycles.
MS
,,~__________________~
"
I
I
\
DQO-DQ1S
TRG
/
_ _ _ _.-J
<
!4
valid Output
14
"I
I
}
~I
\_-----I
FIgure 1. DRAM·Read Cycle With RAS·Cont,rolled Output
~1ExAs
5-260
INSTRUMENTS
POST OFFICE BOX 14043 • HOUSTON.11:XAS 77251-14043
ldla(RH)
ldla(G)
TMS55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS188B-OCTOBER 1993-REVlSEDJUNE 1985
extended data output (continued)
\~------'/
\'-_________JA~~-_t~.,-.
DQO-DQ15
tell.(CH)
I
------------«'-___
va_lId_O_U_tp_ut_ _
~})------
~14---.t~1- tell.(O)
\\..---_--11
TAG
Figure 2. DRAM-Read Cycle With CAS-Controlled Output
\~----------------------~I
\
A
\ ____1
. -. ~+-~~.. ~
I
I
I
1a(C)
I
I
14
I
I
I
.. ,
Ia(CP)
1"'4-111-----I..
~,- Ia(CA)
14
",'
I
Ia(CA) .........
141---+1.,4
I
Ih(CLQ) --Io14__-~"1
DQO-DQ15
-----------C~
valid Output
..I'
1a(C)
,
M/IP,--va-lid-O-ut-P-ut-~)-
\_--------------------_1
Figure 3. DRAM-Page-Read Cycle With Extended Output
-!11
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byte-write operation
Byte-write operations can be applied in DRAM-write cycles, block-write cycles,load-write-mask-register cycles,
and load-color-register cycles. Holding either or both WEL and WEU low selects the write mode. In normal write
cycles, WEL enables data to be written to the lower byte (OQO-OQ7) and WEU enables data to be written to
the upper byte (OQ8-0Q15). For earltwte cycles, one WEx is brought low before CAS falls. The other WEx
can be brought low' before or after A falls. The data is strobed in with data setup and hold times for
OQO-OQ15 referenced to CAS (see Figure 4).
\'--________1
~~i____________~J'
wELt
I1
\ __________~I~I--------------__J'
1 1
~~~~
~u~~---1~14----------~·1 1
I
1
DQD-DQ1S
-----1.*1-- ItI(CLD)
I
4
14
1
~
Yalldlnput
~
t Either WEi can be brought low prior to ~ to Initiate an early-write cycle.
Figure 4_ Example of an Early-Write Cycle
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byte.wrHe operation (continued)
For late-write ~d-modify-wrlte cycles, WEL and WEU are both held high before ~ falls. After ~ falls,
either or both WEL and WEU are brought low to select the corresponding byte or bytes to be written. Data Is
strobed in by WEt and/or WEU with data setup and hold times for OQO-OQ15 referenced to whichever WEx
falls earlier (see Figure 5).
\~--------~------~I
\~
_______..JI
!\____ 1
\
I
I
...J
I I
I 1
I 1
1
"u(D~ --ll~"-----~.I 1
1
1
1
DQO-DQ15~
11+,.-----...1-Yalldlnput
ih(WLD)
~
Figure 5. Example of a Late·Wrlte Cycle
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lE
write-per-blt.
nonpersistent wrlte-per-blt
when either or both WEL and WEU are low on the falling edge of RAS, the write mask is reloaded. A 16-bit binary
code (the write-per-bit mask) Is Input to the device via the random OQ pins and latched on the falling edge of
RAS. The write-per-bit mask selects which ofthe 16 random lIDs are to be written and which are not. After RAS
has latched the on-chip write-per-bit mask, input data is driven onto the OQ pins and is latched on either the
first falling edge of WEx or the falling edge of CAS, whichever occurs later. WEL enables the lower byte
(OQO-OQ7) to be written through the mask and WEU enables the upper byte (OQ8-0Q15) to be written
through the mask. If a data low (write mask = 0) is strobed into a particular 110 pin on the falling edge of RAS,
data is not written to that I/O. If a data high (write mask = 1) is strobed Into a particular I/O pin on the falling edge
of RAS, data is written to that I/O (see Figure 6).
~~------------~I
I I
1
: I
I I
I I
\ ' - -_ _ _ _ _ _ _ _ _ _- J
I I
I I
\ :: I
r----------~,
!\."..._ _ _~~~~
I I
I I
I
I I
\ !.: I
lsu(DQR)
I...
I
I
I
I
DQO-DQ15
N,.,..'_ _ _
II II
~I I
1tIII1tIII_-t~o!-ll-
I
I
th(RDQ)
-'~~~~
I I
I
1tIII1"'--+~11- lh(WLD)
lsu(DWL)-!4:"'-~~1
I
~jI!--w-rlte-M-aa-k--oj~jI!--w-r-H.-I-np-u-t--oj~
Figure 6. Example of a Nonpersistent Write-Per-Sit (late-Write) Operation
~1ExAs .
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persistent wrlte-per-blt
The persistent write-per-bit mode is initiated only by performing a load-write-mask-register cycle first. In the
persistent write-per-bit mode, the write-per-bit mask is not overwritten but remains valid over an arbitrary
number of write cycles until another LMR cycle is performed or power is removed.
The load-write-mask-register cycle Is performed using DRAM write-cycle timing except DSF is held high on the
falling edge of RAS and held low on the falling edge of CAS. A bin~de is input to the write-mask register
via the random I/O pins and latched on either the first falling edge of WEx or the falling edge of CAS, whichever
occurs later. Byte-write control can be applied to the write mask during the load-write-mask-register cycle. The
persistent write-per-bit mode can then be used in exactly the same way as the nonpersistent write-per-bit mode
except that the input data on the falling edge of RAS is ignored. When the device is set to the persistent
write-per-bit mode, it remains in this mode and is reset only by a CBR 'refresh with option reset cycle
(see Figure 7).
L
RAS
eAS
Load Write-Mask Register
I~
I
I
\
I
Persistent Write-Per-Bit
,
AO-AS
I
CBR Refreah (option reaet)
1-.........- \
I,----!----\
'--------'
I
I
/1
\
/
1\
I
I
Refreah
Addre..
I
DSFP~~
WExP ~
Row
Column
A
Data
---J
1
I
I
~
I
I
~ ~
~.ft\
~~~5~
~
I
Wrlte-Maak
I
I
rlI
~~
valid
Input
,~
I
M..k Data • 1: Write to I/O enabled
• 0: Write to I/O dlaabled
Figure 7. Example of a Persistent Write-Per-Bit Operation
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block write
The block-write feature allows up to 64 bits of data to be written simultaneously to one row of the. memory array.
this function Is Implemented as (4 columns )C 4 DOs) repeated In four quadrants. In this manner, each of the
four one-megabit quadrants can have up to four consecutive columns written at a time with up to four DOs per
column (see Figure 8).
DQ15[]]]
DQ14[]]]
DQ13[]]]
DQ12[]]]
DQ11[]]]
DQ10[]]]
DQ9[]]]
One Row of 0-511
DQ8[]]]
DQ7[]]]
DQ6[]]]
DQ&[]]]
DQ4[]]]
DQ3[]]]
DQ2[]]]
-w
DQ1[]]]
4 Conaecutl". Columna of 0-511
Figure 8. Block·Wrlte Operaton
Each one-megabit quadrant has a 4-blt column mask to mask off any or all of the four columns from being written
with data. Nonpersistent write-par-bit or persistent write-per-bit functions can be applied to the block-write
operation to provide write-masking options. The DO data Is provided by four bits from the on-chlp color register.
Bits 0 -3 from the 16-bit write-mask register, bits 0 -3 from the 16-bit column-mask register, and bits 0 -'3 from
the 16-blt color-data register configure the block write for the first quadrant, while bits 4 -7, 8 -11 , and 12 -15
of the corresponding registers control the other quadrants in a similar fashion (see Figure 9).
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block write (continued)
OQ1S[[]
OQ14[[]
OQ13[[]
OQ12
~
[[]
OQ11
1'';
~
,f
One Row of 0-511
OQS[
DQ7[[]
r--'
....1_, I
I I
III
I I I
~~
~: ~
l
15 +++-hQ
~r-J.J
.J
J r--,
....1_, I
_, I I
~ OOS[[]
,
12
OQ9[[]
~
_,
[[]
OQ10
~J
II I
~
OQS[[]
10
11 ++-t-hj:l. LJ
j
J
r--,
....1_, I
;-
OQ3[[]
....
-,
I
I
I
r++++t
'/OQ2[[]
4
OQ1[[]
:
7
I
I
I I
I J
.J
J
000
7
\ 0 1 2 3
4 S & 7
S 9 10 11
12 13 14 15 I
~--------------------~vr----------------------~
Color Reglater
Figure 9. Block Write With Masks
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block write (continued)
Every four columns make a block, which makes 128 blocks along one row. Block 0 comprises columns 0-3,
block 1 comprises columns 4-7, block 2 comprises columns 8-11, etc., es shown .in Figure 10.
Block 0
Block 1
,r-____
A'-_ _....V,-_ _ A
•••••••••••••••••••••• Block 127
,
I
AI.-_ _....,
...I
One Row 01.0-611
I
I
o
2
3
I
4
6
6
I
I
7 ••••••••••••••••••••••••••• 611
\~----------'v,..-----------J'
Columns
Figure 10. Block Columns Organization
During block-write cycles, only the seven most significant column addresses (A2 -AS) are latched on the falling
edge of CAS to decode one of the 128 blocks. Address bits AO -A1 are Ignored. Each one-megabit quadrant
has the. same block selected.
A block-write ~ Is entered In a manner similar to a DRAM write cycle except OSF is held high on the first
falling edge of CAS. As In a DRAM write operation, WEe and WEU enable the corresponding lower and upper
DRAM OQ bytes to be written, respectively. The column-mask data is Input via the OQs and is hatched on either
the first falling edge of WEx or the falling edge of CAS, whichever occurs later. The 16-bit color-data register
must be loaded prior to performing a block write as described below. Refer to the wrlte-per-blt section for details
on use of the write-mask capability allowing additional performance options.
Example of block write:
block-write column address
color-data register
write-mask register
column-mask register
= 110000000 (AO -A8 from left to right)
bit 0
= 1011
= 1110
1111
1st
Quad
=
1011
1111
0000
2nd
Quad
1100
1111
0111
3rd
Quad
bit 15
0111
1011
1010
4th
Quad
Column-address bits AO and A1 are Ignored. Block 0 (columns 0 -3) Is selected for each one-megabit quadrant.
The first quadrant has OQO-OQ2 written with bits 0-2 from the color-data register (101) to all four columns
of block O. OQ3 Is not written and retains its previous data due to the write-mask register bit 3 being a O.
The second quadrant (OQ4-0Q7) has all four columns masked off due to the column mask bits 4 -7 being 0,
so that no data is written.
The third quadrant (OQ8-0Q11 ) has Its four OQs written with bits 8 -11 from the color-data register (1100) to
columns 1-3 of its block O. Column 0 is not written and retains Its previous data on all four OQs due to the
column-mask-reglster bit 8 being O.
The fourth quadrant (OQ12-0Q15) has OQ12, OQ14, and OQ15 written with bits 12, 14, and 15 from the
color-data register to column 0 and column 2 of Its Block O. OQ13 retains its previous data on all columns due
to the write mask. Columns 1 and 3 retain their previous data on all OQsdue to the column mask. If the previous
data for the quadrant was aliOs, the fourth quadrant would contain the data pattern shown In Figure 15 after
the block-write operation shown in the previous example.
~1ExAs
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block write (continued)
D01S11 1 0 11 1 0
D0141,1 0 11 1 0
I
I
IIII
-.~
DQ131 0
Columna 0
1
2
0
0
0
3
Figure 11. Example of Fourth Quadrant After Block-Write Operation
load color register
The load-color-register ~ is performed using normal DRAM write-cycle timing except that OSF is held high
on the falling edges of RAS and CAS. The color register is loaded from pins 000-0015, which are latched
on either the first falling edge of WEx or the falling edge of CAS, whichever occurs later. If only one WEx is low,
only the corresponding byte of the color register is loaded. When the color register is loaded, it retains data until
power is lost or until another load-color-register cycle is performed (see Figure 12 and Figure 13).
I
I
Load-Color-Reglster Cycle
I
I
I
Block-Write Cycle
(no write mask)
I
I
I
Block-Write Cycle
(load and US8 write mssk)
I
I
I
I
~S~I'~====~___~I~--------~~I~==~----/I
CAS I
WEx
AD-AS
TRG
DOO-DQ1S
DSF
''-_ _..J1
''-_ _..J1 I
,
/-i
!~~=:~~~::::::~~~~~~~~~~~~~~~~~~~~~~~~
E
~:;;;;:~~~~~~~~3§~~~~~~~~~~C:~~~~;:~~~~
Legend:
1. Refresh address
2. Row address
3. Block address (A2-AS) is latched on the failing edge of CAS.
4. Color-register data
5. Write-mask data: DaO-001S are latched on the falling edge AA§.
8. Column-mask data: OQI...;DaI+3 Q-0, 4, 8,12) are latched on either the first failing edge ofWEx or the failing edge of CAS, whichever
occurs later.
• don't care
a
tcccl!cclcUlcccI!UlcUln!Bc:ct
Figure 12. Example of Block Writes
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load color register (continued)
I
I
Load·Maak·Reglater Cycle
Load·Color-RegJater Cycle
Perslatent Block·WrIte Cycle
(uaeloaded wrlt.maak)
Legend:
1. Refresh address
2. Row address
3. Block address (A2-AB) Is latched on the failing edge of CAS.
4. Color·register data
5. Write-mask data: 000-0015 are latched on the falling edge RAS.
8. Column-maskdata: OQi-OQi+3 (i .. 0, 4, 8,12) are latched on either the first falling edge of wei or the falling edge of 'CAS, whichever
OOCUI'$ later.
«ccccc:cijC:Ucc:ccMt • don't care
Figure 13. Example of a PerSistent Block Write
DRAM·to·SAM transfer operation
During the DRAM·to·SAM transfer operation, one half of a row (256 columns) In the DRAM arr~selected
to be transferred to the 256·blt serial-data register. The transfer operation is Invoked by bringing "I'RG low and
holding WEx high on the falling edge of RAS. The state of DSF, which Is latched on the falling edge of RAS,
determines whether .the tull-reglster-transfer read operation or the split-register-transfer read operation is
performed.
Table 4. SAM Function Table
CAS
AASFALL
FALL
FUNCTION
CAS
'i'RG WEit
ADDRESS
DQO-DQ15
DSF
DSF
RAS
CAS
RAS
CAS
MNE
CODE
WEx
Full-register-lransfer read
H
I.
H
I.
X
Row
Addr
Tap
Point
X
X
AT
Split-register-transfar read
H
I.
H
H
X
Row
Addr
Tap
Point
X
X
SAT
t l.oglC I. is selected when either or both WEI. and WEU are low.
X
= don'lcare
~1ExAS
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MULTIPORT VIDEO RAM
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full-register-transfer read
A full-register-transfer read operation loads data from a selected half of a row in the DRAM Into the SAM. 'fAG
is brought low and latched at the falling edge of RAS. Nine row-address bits (AO -AS) are also latched at the
falling edge of RAS to select one of the 512 rows available for the transfer. The nine column-address bits
(AO -AS) are latched atthe falling edge of CAS, where address bit AS selects which half ofthe row is transferred.
Address bits AO -A7 select one of the SAM's 256 available tap points from which the serial data is read out
(see Figure 14).
o
AS-O
255 256
AS=1
511
512 x512
Memory Arrey
256-BIt
Data Reglstar
o
25~
Figure 14. Full-Reglster-Transfer Read
A full-register-transfer read can be performed In three ways: early load, real-time load (or midline load), or late
load. Each of these offers the flexibility of controlling the TRG trailing edge in the full-register-transfer read cycle
(see Figure 15).
I
Early Load
RAS 1'\
I
.
I
I
AO-AS,
Row
fRGrv'
I
I
Real-Tlma Load
Tap
Point
I
I
I I
I
I
I
Row
\
Tap
Point
I
I
I
II
'--I
I I
\
I
I
Lata Load
/""I\.
I '-_ _--J.I
/""I\.
I
\
~I
I
Row
I \
I
Tap
Point
,
n
I
wEx~~~~
,
se I
I
I
I
I
___
~_J
Figure 15. Example of Full-Register-Transfer Read Operations
-!I
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spllt-reglst.,-transftl, fflad
In the split-register-transfer read operation, the serial-data register is split into halves. The low half contains bits
D-127, and the high half contains bits 128 - 255. While one half Is being read out of the SAM port, the other
half can be loaded from the memory array.
o
511
612 ><512
Memory Array
256-BIt
Data Register
Figure 16. Spllt-Reglster-Transfer Read
To invoke a split-register-transfer read cycie, DSF is brought high, TRG Is brought low, and both are latched at
the falling edge of RAS. Nine row-address bits (AD -A8) are also latched at the falling edge of RAS' to select
one of the 512 rows available for the transfer. Eight of the nine column-address bits (AD -A6 and AS) are latched
at the falling edge of CAS. Column-address bit AS selects which half of the row is to be transferred.
Column-address bits AD-A6 select one ofthe 127 taP points in the specified half ofthe SAM. Column-address
bit A7 is ignored, and the split-register-transfer is internally controlled to select the Inactive register half.
AS.O
, AS-1
~
O~~1"""""Ir-i511
A B
DRAM
o
AS.O
AS-1
~
A7_0t 611
o
~
A7_1t 511
o
~
A7_0t
611
m
m
m
·1,lt~
·Itli~
O~255
SAM
.
SQ
sa
sa
~sa
t A7 shown is internally controlled.
Figure 17. Example of a Split-Reglster-Transfer Read Operation
A full-register-transfer read must precede the first split-register-transfer read to ensure proper operation. After
the full-register-transfer read cycle, the first split-register-transfer read can follow Immediately without any
minimum SC clock requirement.
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spllt-IYIglster-trans"r raad (continued)
aSF indicates which half of the register is being accessed during serial-access operation. When aSF is low,
the serial-address pointer is accessing the lower Qeast significant) 128 bits of the SAM. When aSF is high, the
pointer is accessing the higher (most significant) 128 bits of the SAM. aSF changes state upon completing a
tull-register-transfer read cycle. The tap pOint loaded during the current transfer cycle determines the state of
aSF. aSF also changes state when a boundary between two register halves is reached.
Full-R.glate....Tranlfer R..d
With Tap Point N
I
I
\
iiAi
\I
~
I
\
i'FRi
I
IIf
I
I
f
f
DSF
f
f
tcJ(CLQSF)
I
I
\
\
I
\
/\
f
f
f
I. I
SC
Spllt-R.glet.r
Tranlf.r R..d
r;:;\..
X
PolntN
~I
f_
tcJ(QHQSF)
QSF
Figure 18. Example of a Split-Register-Transfer Read After a Full-Register-Transfer Read
Spllt-Reglater
Tran.r R..d
WIth Tap Point N
iiAi
Spllt-Reglater
Tranlfer R.ad
hri------~~
\
,
~
\
TRQ~
DSF
~
,I \
A,
~
I!
I
tcJ(RHMS) ,_
I
f
I
I
D _______
~I I.
II
~f
tcJ(MSRL)
SC
14----I~*'1-
QSF
tcJ(SCQSF)
----------------------------~>t'i-------------------Figure 19. Example of Successive Split-Register-Transfer Read Operations
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serial-read operation
The serial-read operation can be performed through the SAM ,port simultaneously and asynchronously with
DRAM operations except during transfer operations. Serial data can be read from the SAM by clocking SO
starting at the tap point loaded by the preceding transfer cycle, proceeding sequentially to the most significant
bit (bit 255), and then wrapping around to the least significant bit (bit 0), as shown In Figure 20.
r'
0
1 1 1 2 1 ...... 1 Tap 1-+ ...• 12641 2551
I
Figure 20. Serial Pointer Direction for Serial Read
For split-register operation, serial data can be read out from the active half of the SAM by clocking SO starting
at the tap point loaded by the preceding split-register-transfer cycle. The serial pointer then proceeds
sequentially to the most significant bit of the half, bit 127 or bit 255. If there is a split-register-transfer read to
the Inactive half during this period, the serial pointer points next to the tap point location loaded by that
split-register-transfer (see Figure 21).
Figure 21. Serial Pointer for Split-Register Read - Case I
If there is no split-register-transfer read to the inactive half during this period, the serial pOinter points next to
the least Significant bit of the Inactive half (bit 128 or bit 0) (see Figure 22).
Figure 22. Serial Pointer for Spilt-Register Read - Case"
split-register programmable stop point
The TMS55166 offers programmable stop-point mode for split-register-transfer read operation. This mode can
be used to Improve 2-D drawing performance in a nonscanline data format.
In split-register-transfer read operation, the stop point is defined as a register location at which the serial output
stops coming from one half of the SAM and switches to the opposite half of the SAM. While In stop-point mode,
the SAM is divided into partitions whose length Is programmed via row addresses A4-A7 In a CBR set (CBRS)
cycle. The last serial-address location of each partition is the stop point (see Figure 23).
0
I
Partition
Length
~
I
i
I· · -I
L..
127 128
I
255
I
1 1
Figure 23. Example of the SAM With Partitions
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1. ..
I
1
Stop
Pointe
TMS55166
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MULTIPORT VIDEO RAM
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spllt....eglster programmable stop point (continued)
Stop-point mode is not active until the CBRS cycle Is initiated. The CBRS operation Is performed by holding ~
and WEx low and OSF high on the falling edge of RAS. The falling edge of RAS also latches row addresses
A4-A7, which are used to define the SAM's partition length. The other row address inputs are don't care.
Stop-point mode should be initiated after the initialization cycles have been performed (see Table 5).
Table 5. Programming Code for Stop-Point Mode
ADDRESS AT fiAi IN CBRS CYCLE
MAXIMUM
PAFmTION
LENGTH
AS
A7
AI
AS
A4
18
X
L
L
L
L
X
18
32
84
X
X
L
L
L
L
H
H
L
H
X
X
8
4
15,31,47,83,79,95,111,127,143,159,175,
191.207.223,239.255
31.83.95.127.159.191.223,255
83.127.191.255
128
X
L
H
H
H
X
2
127.255
.. (default)
NUMBER OF
AO-A3 PARTITIONS
STOP-POINT LOCATIONS
In stop-point mode, the tap point loaded during the split-register-transfer read cycle determines in which SAM
partition the serial output begins and at which stop point the serial output stops coming from one half of the SAM
and switches to the opposite half of the SAM (see Figure 24).
AM \R":~r
\ . Split .. /,..--""",'\.. Spilt _
~.ad XFE'Y
~.ad
r-
XFE'Y
Tap.H1
Tap. L1
H1
Tap. H2
191
Tap. L2
L1
83
H2
2511
L2
SC ______________~~ ••• ~ ••• ~ •••••• ~
SAM Low Half
0
SAM High Half
L1
83
t
1 t:
L2
127
128
4
4
H1
:
4
H2
191
2S1S
f
} 1
~
4
Figure 24. Example of Spllt·Reglster Operation With Programmable Stop Points
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUS'TCN, TEXAS 77251-1443
5-275
TMS55166
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS166B-OCTOSER 1993 - REVISED JUNE 1996
256-/512-blt compatibility of split-register programmable stop point
The stop-point mode Is designed to be compatible both for 256-bit SAM and 512-bit SAM devices. After the
CBRS cycle is initiated, the stop-point mode becomes active. In the stop-point mode, and only in the stop-point
mode, the column-address bits AY7 and AYa are internally swapped to assure the compatibility (see Figure 25).
This address-bit swap applies to the column address, and it is effective for all DRAM and transfer cycles. For
example, during the split-register-transfer cycle with stop point, column-address bit Aya is a don't care and AY7
decodes the DRAM row half for the split-register-transfer. During stop-point mode, a CBR option reset (CBR)
cycle is not recommended because this ends the stop-point mode and restores address bits AY7 and Aya to
their normal functions. Consistent use of CBR cycles ensures that the TMS55166 remains in nomal mode.
NON STOP-POINT MODE
STOP-POINT MODE
1512 x 1512
Memory Array
512 x 512
Memory Array
256081t .
Date Reglater
25608lt
Date Reglater
Figure 25. DRAM-to-SAM Mapping, Non Stop Point Versus Stop Point
IMPORTANT: For proper device operation in the split-register stop-point mode, a CBRS cycle should be initiated
right after the power-up initialization cycles have been performed.
power up
To achieve proper device operation, an initial pause of 200 J.tS is required after power up followed by a minimum
of eight RAS cycles or eight CBR cycles to initialize the DRAM port. A full-register-transfer read cycle and two
SC cycles are needed to initialize the SAM port.
After initialization, the internal state Of the TMS!55166 is as follows:
STATE AFTER INITIALIzATION
QSF
Write mode
Write mask register
Color register
Serial-register tep point
SAM port
Deflned by the transfer cyCle during initialization
Nonpersistent mode
Undeflned
Undefined
DefIned by the transfer cycle during initialization
Output mode
~TEXAS·
INSTRUMENTS .
5-276
POST OFFlCEBOX 1443 • HOUSTON, lEXAS 77251-1443
TMS55166
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS166B-OCTOBER 1993-REVISEDJUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................... -1 V to 7 V
Voltage range on any pin • • • • . • • • • • • • . . . . . . •• • . . . • . . . . • . . . • • • • • • • . . . . • • • . • • . • • • . • • • •• -1 V to 7 V
Short-circuit output current ••••••••.•••.•••••••.••.•.••....•.•.•..•.....••.•.•.•.••..•...•• 50 rnA
Power dissipation .••..•••.••••.••••••••.••.••..•.•••••••••••••••••.•.••.•..••...•••..•••• 1.1 W
Operating free-air temperature range, TA .••..••...••••..•...••••••••.••••.••••••••••.• O·C to 70·C
Storage temperature range, Tstg ••••••••••••..••.• ;............................... -65·C to 150·C
.t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at thaae or any other conditions beyond those Indicated under "recommended operating conditions" Is not
Implied. Exposure to absolute-maxlmum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
Supply voltage
Supply voltage
4.5
5
5.5
V
V
VIH
High-level Input voltage
2.4
8.5
V
VIL
Low-levellnput voltage (see Note 2)
-1
0.8
70
V
Vee
VSS
0
UNrr
Operating frae-alr temperature
0
"C
TA
NOTE 2: The algebraiC convention, where the more negative (less positive) limit Is designated as minimum. Is used for logic-voltage levels only•
.. . .
~TEXAS
INSTRUMENTS
POST OFFICE eox 1443 • HOUSTON. TEXAS 77251-1443
5-277
TMS55166
262144 BY1&-BIT
MULTIPORT VIDEO RAM
SMVS186B- OCTOBER 1993 - REVISED JUNE 1996
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)
PARAMETER
TEST cONDmoNst
VOH
High-level output
voltage
IOH--1 mA
VOL
Low-level output
voltage
IOL .. 2mA
II
Input current
~eakage)
SAM
PORT
'I5S1_
MIN MAX
2.4
'515188-70
MIN MAX
2.4
'15151_
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
VCC .. S.SV,
VI-OVtoS.8V.
All other pins at 0 V to Vcc
:1:10
:1:10
:1:10
\IA
VCC"S.SV, VO·OVtoVCC
See Note 3
:1:.10
*'0
*'0
\IA
180
225
165
20S
150
185
15
70
S
85
S
mA
mA
mA
teISC) -MIN
Standby
Actlve
Stendby
Actlve
80
mA
Stendby
180
165
150
mA
10
Output current
(leakage)
ICC1
Operating current *
See Note 4
ICC1A
ICC2
teISC) • MIN
All clocka • VCC
ICC2A
Operattng current *
Stendby current
.Stendby current
ICC3
RAS-only refresh
current
See Note 4
ICCSA
RAS-only refresh
current
te(SC) • MIN.
See Note 4
Active
225
205
185
mA
See Note S
See NoteS
Stendby
140
140
120
mA
ActIve
185
165
165
mA
Stendby
180
165
150
mA
205
180
225
185
180
mA
mA
200
mA
1CC4
Page-mode current*
ICC4A
ICCS
Page-mode current'
CBR current
telP) -MIN.
teISC) .. MIN,
See Note 4
CBRcurrent
Date-transfer current
te(SC) • MIN.
See Note 4
See Note 4
Active
Stendby
225
200
ActIve
250
ICCIIA Date-transfer current te(SC) • MIN
t For conditions shown as MIN/MAX. use the appropriate value specified In the ttmlng requlremente.
Measured with outpule open
NOTES: 3. R Is disabled for SQ output leakage tests.
4. Measured with one address change while i!iAS .. VIL. tc(rd). tc(W). tc(TRD) • MIN.
S. Measured with one address change while ~ • VIH
ICCIIA
ICC6
*
capaCitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
CI(A)
Input capacitance. address Inpule
6
UNIT
pF
CI(RC)
CIIWI
Input capacitance. address strobe Inpule
7
pF
Input capacitance. write enable Input
7
pF
7
pF
CI(SEl
Input capecltance. serial clock
Input capacitance. serial enable,
7
pF
CI(OSF)
Input capacitance. special functton
7
pF
7
7
pF
pF
pF
CI(SC)
CI(TRGI Input capacitance. transfer register Input
Output capacitance. SQ and DQ
CoCO)
Co(QSF) Output capacitance. QSF
NOTE 8: VCC" 5 V * 0.5 V. and the bias on pins under test Is 0 V.
9
~1ExAs
5-278
INSTRUMENTS
POST OFFICE BOX 1443 •
MAX
HOUSTON. lEXA8 77251-1443
TMS55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS188B - OCTOBER 1993 - REVISED JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature (see Note 7)
ta(C)
Access time from ~
tcl(RLCL) - MAX
teAC
'55186-60
MIN MAX
17
ta(CA)
Access time from column address
tcl(RLCL) .. MAX
1M
30
ta(CP)
Access time from ~ high
tcl(RLCL) .. MAX
tePA
35
40
45
na
ta(R)
Access time from RAS
tcl(RLCL) .. MAX
tRAC
60
70
60
na
ta(G)
Access time of Da from TRG low
toEA
15
20
20
na
ta(Sa)
Access time of sa from SC high
CL=30pF
tsCA
15
20
25
na
ta(SE)
Acceaa time of sa from SE low
CL-30pF
tsEA
12
15
20
na
tclis(CH)
Disable time, random output from
CAS high (sea Note 6)
CL" 50 pF
toFF
tclis(RH)
RAS high (sea Note 6)
CL-50pF
tclis(G)
Disable time, random output from
TRG high (see Note 8)
CL-50pF
tclis(WL)
Disable time, random output from
WE low (see Note 8)
tclis(SE)
SE high (see Note 8)
PARAMETER
Disable time, random output from
Disable time, serial output from
TEST
CONDITIONSt
ALT.
SYMBOL
'55186-70
MIN MAX
20
'55186-60
MIN MAX
20
35
40
UNIT
na
n8
0
15
0
20
0
20
na
0
15
0
20
0
20
na
toEZ
0
15
0
20
0
20
na
CL-30pF
twEZ
0
15
0
20
0
20
na
CL-30pF
tSEZ
0
10
0
15
0
20
na
t Measured with outputs open. For conditions shown as MIN/MAX. use the appropriate value specified In the timing requlraments.
NOTES: 7. Switching times for RAM port output ara measured with a load equivalent to 1 TTL load and 50 pF. Data out referenoe level:
VOH /VOL - 2 VIO.8 V. Switching times for SAM port output ara measured with a load equivalent to 1 TTL load and 30 pF. Serial data
out reference level: VOH / VOL - 2 VIO.8 V.
8. tclis(CH), tclls(RH), tclls(G), tclis(WL)' and tclis(SE) ara specified when the output is no longer driven.
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
5-279
TMS55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS188B- OCTOBER 1993 - REVISED JUNE ~119&
timing requirements over recommended ranges. of supply voltage and operating fre...lr
temperature t
,"
ALT.
SYMBOL
te(rd)
Cycle time, read
IRc
telWl
Cycle time, write
telrdWI
tecp)
Cycle time, read-modlfy-write
two
tRMW
teIROWP)
teCTRO)
te(SC)
Cycle time, page-mode read-modlfy-wrlte
Cycle time, transfer read
Cycle time, aerial clock (aee Note 9)
twlCH)
Pulse duration, CAS high
Pulse duration, CAS low (see Note 10)
tw(CU
Cycle time, page-mode read, write
twIRU
tw(WL)
Pulle duration, RAS high
Pulse duration, RAS low (see Note 11)
Pulse duration, WEi low
twCTRG\
Pulse duration, 'i'RG low
twCSCH)
Pulse duretlon, SC high (see Note 9)
twcscu
tw(GH)
Pulse duration, SC low (see Note 9)
twfFtHl
tpC
Setup time, column address before CAS low
Setup time, OSF before CAS low
taulRAl
taulWMR)
Setup time, row address before RAS low
Setup time, WEi before RAS low
taulDORI
tauCTRG)
tau(SFR)
Setup tlll:le, DO before RAS low
Setup time, 'i'RG high before RAS low
Setup time, DSF low before RAS low
taucocu
'55168-70
MIN
MAX
'116188-80
MIN
175
30
80
130
22
10
10
50
70
10
200
ns
35
100
150
30
10
nl
ns
nl
nl
80
10000
40
10000
20
10000
10000
ns
ns
trp
20
20
20
80 100000
0
70 100000
0
0
0
0
0
0
0
0
80 100000
0
0
0
0
0
IFsc
tASR
0
twsR
tMS
0
0
0
80
15
ns
20
20
ns
8
8
10
10
ns
ns
nl
ns
Setup time, data valid before CAS low
taulDWU
Setup time, data valid before WEx low
tosw
0
0
0
teu(rd)
Setup time, read command,
~Iow
IRcs
0
0
0
twos
0
0
0
Setup time, WEi low before CAS high, write
tcwL
IRWL
teAH
teFH
15
15
10
10
15
15
10
10
20
Setup time, ~ low before RAS high, write
Hold time, column address after CAS low
taulWCH)
tau(WRH)
nl
18c
!sCP
10000
0
0
low before CAS low
nl
10000
80
10
15
5
5
0
~ time, early write command,
nl
80
trHS
tau(WCL)
ns
150
30
110
18
10
10
tRASP
tASC
UNIT
150
150
!FSR
tosc
WEi high before
MAX
130
130
IRc
!sec
tePN
twP
twlRUP
taulCA)
tau(SFC)
MAX
110
110
tpRMW
teAS
tRP
tRAS
Pulse duration, 'i'RG high
Pulse duration, RAS low (page mode)
'551_
MIN
0
0
0
20
ns
ns
ns
ns
ns
ns
ns
ns
..
....
....
ns
15
thlCLCAI
Hold time, OSF after CAS low
15
ns
thlSFC)
Tlmlng measurements are referencad to VIL max and VIH min.
NOTES: 9. Cycle time assumes It • 3 ns.
10. In a read-modlfy-write cycle, fcI(CLWL) and tau(WCH) must be obeerved. Depending on the user'1 transition times, this may require
additional CAS low time ltw(CL))'
11. In a read-modlfy-wrlte cycle, fcI(RLWL) and tau(WRH) must be obeerved. Depending on the uler's transition times, this may require
additional RAS low time ltw(RL))'
~TEXAS
5-280
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251_1443
TMS55166
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVSl86B - OCTOBER 1993 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (contlnued)t
ALT.
SYMBOL
Hold time, row address after RAS low
Hold time, TRG after RAS low
'55166-60
'55168-70
'55166-80
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
10
10
10
10
10
10
10
10
10
10
ns
ns
ns
ns
ns
Hold time, write mask after RAS low
lTHH
tRWH
Hold time, DO after RAS low (write-mask operation)
Hold time, oSF after RAS low
tMH
tRFH
10
10
10
10
10
tAR
30
30
35
ns
toH
toHR
toH
15
35
15
15
35
15
15
35
15
n8
trl(CHrd)
Hold time, read, WEx high after CAS high
(see Note 13)
tACH
0
0
0
n8
Ih(RHrd)
Hold time, read, WEx high after RAS high
(see Note 13)
tRRH
0
0
0
ns
twCH
twCR
10
30
10
4
15
ns
ns
ns
n8
trl/RAI
trlrrRGI
trl(RWMI
trllRoOI
thlSFRI
tRAH
lh(RLCA)
Hold time, column address valid after RAS low
(see Note 12)
trl(CLDI
Hold time, data valid after CAS low
lh/RLo)
th(WLDI
Hold time, data valid after RAS low (see Note 12)
trllCLWl
th(RLWl
lhIWLGi
th(SHSOI
th(RSF)
Hold time, data valid after WEx low
Hold time, write, WEx low after CAS low
Hold time, write, WEx low after RAS low (see Note 12)
Hold time, 'i'RG high after WEx low (see Note 14)
toEH
!sOH
!FHR
toHC
tCSH
30
30
4
5
60
10
0
20
20
n8
45
45
n8
th(CLOI
tel(RLCH)
Delay time, RAS low to -aAS high
tellCHRLI
tel(CLRHl
Delay time, -aAS high to RAS low
teHR
tCRP
Delay time, CAS low to RAS high
tRSH
10
0
17
tel(CLWL)
Delay time, CAS low to wei low
.(see Notes 16 and 17)
lewD
37
tel/RLCLI
telICARH!
Delay time, column address valid to RAS high
telICACH!
tel/RLWLI
Delay time, column address valid to CAS high
Delay time, RAS low to WEx low (see Note 16)
tel(CAWL)
09lay time, column address valid to WEx low
(see Note 1.8)
telCCLRL)
tel(RHCL)
Delay time, CAS low to RAS low (see Note 15)
Delay time, RAS high to -aAS low (see Note 15)
telCCLGHl
Delay time, -aAS low to 'i'RG high for DRAM read cycles
Delay time, RAS low to -aAS low (see Note 18)
tAco
tRAL
n8
15
35
10
5
35
5
80
15
0
Hold time, SO after SC high
Hold time, oSF after RAS low
Hold .tlme, output valid after CAS low
I
1See Note 15
ns
35
10
5
53
20
43
20
50
20
n8
ns
ns
ns
60
n8
35
40
ns
35
95
40
105
ns
tRWo
30
30
80
tAWo
50
60
85
ns
teSR
tRPC
0
0
17
10
0
0
0
0
20
15
ns
ns
ns
ns
tCAL
20
Delay time, TRG high before data applied at DO
15
telCGHo)
toED
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 12. The minimum value Is measurad when tel(RLCL) Is set to tel(RLCL) min as a reference.
13. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
14. Output-enable-controlled write. Output remains In the high-Impedance state for the entire cycle.
15. -aAS-before-RAS refresh operation only
18. Read-modify-write operation only
17. 'i'RG must disable the output buffers prior to applying data to the DO pins.
18. The maximum value Is specified only to assure RAS access time.
ns
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77251-1443
5-281
TMS55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS166B - OCTOBER 1993 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature {contlnued)t
ALT.
SYMSOL
'55166-60
'65186-70
MIN
MIN
MAX
MAX
'55166-60
MAX
MIN
UNIT
~{RLTH)
Delay time, RAS low to TRG high (sea Note 19)
lATH
50
55
60
na
tcI(RLSH)
Delay time, AAS low to first SC high after TRG high
(see Note 19)
tRSD
65
70
60
na
tclCRLCA)
Delay time, AAS low to column address valid
tRAD
tclCGLRH)
tAOH
15
10
tcI(CLSH)
Delay time,i'RG low to AAS high
Delay time, CAS low to first SC high after i'RG high
(sse Note 20)
loso
20
20
25
na
tcI(SCTR)
Delay time, SC high to TRG high
(see Notes 19 end 20)
lTsL
5
5
5
ns
lTRO
lTRP
lTso
-10
40
10
-10
50
10
-10
60
15
na
ns
15
20
20
na
tcI(THRH)
tcllTHRLI
tcllTHSC)
tcI(RHMS)
Delay time, i'RG high to RAS high (see Note 19)
Delay time, 'fAG high to RAS low (sea Note 21)
Delay time, 'fAG high to SC high (see Note 19)
Delay time, RAS high to last (most significant) rising
edge of SC before boundary switch during
spllt-reglster-transfer read cycles
·30
15
15
35
15
15
40
na
. na
na
tcI(CLTH)
Delay time, CAS low to i'RG high In real~time transfer
reed cycles
lOTH
15
15
15
ns
tcI(CASH)
Delay time, column address to first SC In eariy-load
transfer read cycles
tASD
25
25
30
na
tcI(CAGH)
Delay time, column address to 'fAG high In real-time
transfer read cycles
tATH
20
20
20
na
Delay time, data to CAS low
Delay time, data to TRG low
tozc
tozo
0
0
0
0
0
na
~
na
15
20
20
na
tclCOCL)
tcI(DGL)
tcI(MSRL)
Delay time, last (most significant) rising edge of SC to
RAS low before boundary awitch during spilt-transfer
read cycles
tcI(SCOSF)
Delay time, last (127 or 255) rising edge of SC to OSF
awitching althe boundary during spllt-register-~rensfer
read cycles (see Note 2222)
!sOD
20
25
30
na
tcI(CLOSF)
Delay time, CAS low to OSF awitchlng In transfer read
cycles (see Note 2222)
loOo
25
30
35
na
Delay time, TRG high to OSF switching in transfer read
tcI(GHOSF) cyclea (sea Note 2222)
lToo
20
25
30
na
Delay time, AAS low to OSF switching In transfer read
cycles (see Note 2222)
tROD
65
70
75
tcI(RLOSF)
Refresh time interval, memory
ns
ma
8
8
8
trf{M~.
tAEF
Trensition time
na
3
50
3
50
3
50
tt
IT
t liming measurements are referencad to VIL max and VIH min.
NOTES: 19. Real-time load transfer read or late-load transfer read cycle only
20. Early-load transfer reed cycla only
.
21. Full-register (read) transfer cyclea only
22. Switching times for OSF output are measured with a load equivalent to 1 TTL load end 30 pF end output reference level Is
VOH I VOL a 2 VIO.8 V.
~ThxAs
5-282
INSTRUMENTS
POST OFFICE sox 14043 • HOUSTON, lEXAS 772111-14043
TMS55166
262144 BY 16-BIT
MULTIPaRT VIDEO RAM
SMVS1888 - OCTOBER 1993 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
I~
Io(rd)
twIRL)
IcI(RLCH)
1 I~
1 I~
--"'"\II~~
I
CAS
I+-IcI(CLRH)
I+-IcI(RLCL)
II
I I
W#
------
1
1+ IcIla(G) -+j
Data Out
ta(C)--+1
ta(CA)
I~
ta(R)
.:
.1
Figure 26. Read·Cycle TIming With CAS.Controlied Output
~1ExAs
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MULTIPORT VIDEO RAM·
SMVS.186B ~ OCTOBER 1993 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
~~
I I~
I I~
tw(R!..)
Ici(RLCH)
---'!I!~~
~
~I
I
I
I
~I
I
I
I\(
II VI
i''---I
I 14- tw(RH) ~
It ~ I+~ Ici(CLRH) '-+I I
I ~ Ici(RLCL} -.I
-+t i4+-1ci(CHRL}
I+- tw(CL} -+II II II
II
I·
I
CiS
I r.
j\~.!
'L I i
..
I
i~
¥~ I Itw(CH)
Ici(RLCA) ~
~I~ I I Ici(CARH) ~ I
Itt(RA)~ I+- I I I ·
I I~ I
th(RLCA) ---.I
II II II I
lau(RA) -+I 14 I
I ~ I I· . I ~I Ici(CACH)
AU
r-i-,-----_
wi
J\,
po
'-.--
~~~
AO-"~:7-~
-.. *
*"Itt(SFR)
I
I
II'
laU(SFR)""1~_I~
DSF~II I
.
~II
I
lau(TRG) +I
-+-+II
I j.- Ici(CLGH)
. I~
~I II
I
I I
I
I
I!}
I
~~ ~.I:+1w(TRG)-':1
fRQ~'I~
I -*+I
I
I
laU(rd)
~
I
.
I
Itt(CHrd)
Ici(GLRH)
II·~
-+j II+IIIIII~I
Itt(RHrd)
-IIII~
Figure 27. Read·CycleTlmlng With RAS·Controlled Output
5-284
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, ~ 77251-1443
TMS55166
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MULTIPORT VIDEO RAM
SMVSI88B-OCTOBER 1993-REVJSEDJUNE 1895
PARAMETER MEASUREMENT INFORMATION
RAt
'4
----.iN..
1c(W)
, ,.
I
14
I
1+ tcI(RLCL) -..!
tcI(RLCH)
14
M
~
tcI(CHRL)
~ ~ 114-I I·
N
lh(RLCA) ~
lh(RA)
1+! I+-
tcI(RLCA)
14;
~!4t tau(CA)
~
tau(RA)
AO-AB
I I
tcI(CACH)
.,1
I I
.,1
I
I+- tw(RH) -1
t
~ I4-It
I
tcI(CHRL) -+I
lJ~tw(CH)--..I\...
1 I
I
I
1
"L ~'114-+I-~tt.(CLCA)
I I
141
~4::::
~_ COlumn ~
• Row.
. -to!
tau(SFR) ......, I4t
I 1 I+--- lh(RSF) -+I
r- I 114 "1
m,t11~111
11
;.t
_
;; taU(SFC)\QoQj~~IooIloQj~~I~~,~~0QQI;jQQ~-
lh(SFR)i1
DSF
tw(CL)
"1
I
I
.'
tcI(CLRH)
~
L'
'yT
ow
It ~ I+-
~
"I
L(RL)
I+" lh(I'RO) I
I
I
~
~
I
I
tau~(TRQr+!
14t~
-II
Table 6. Early-Wrlte-Cycle State Table
STATE
CYCLE
1
H
L
L
Write operation (nonmasked)
WrIte operation with nonpersistent wrIte-per-b1t
Write operation with persistent wrlte-per-blt
2
3
Don't care
Write mask
Don't care
Valid data
Valid data
Valid data
~TEXAS
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MULTIPORT VIDEO RAM
SMVS16BB - OCTOBER 1993 - REVISED JUNE 1895
'i'RG
~I
I
-+j ~ teu(TRG)
!_I
1
~W tcI(QHD)
-+! l~
~
I I I~·
I I I~
~~
II
1"""1
I
teu(WMR) I
I
I
I~
~I
wei
I
I I
~
I -+j
~I
fh(WLQ)
~
teu(DQR)
DQO-DQ1S
th(CLW)
th(RDQ)
th(WLD)
I I
l-!l ~!
~
.
~
I
I
I
I
I
~I
I I .
~~
tw(Wl)
teu(DWL)
I+-
--+I
~I
th(RLW)
I it
~
t.I ~
+ j i l l I !+--
I ~I
teu(WRH)
teu(WCH)
--.I
I
~I
fh(RLD)
3
~
FIgure 29. Late-Wrlte-Cycle Timing (Output-Enable-Controlled Write)
Table 7. Late-Wrlte-Cycle State Table
STATE
CYCLE
1
H
L
L
Write operation (nonmasked)
Write opera1ion with nonpersistent write-per-bit
Write operation with persiatent write-per-blt
~TEXAS
5-286
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
2
3
Don't care
Valid data
Write mask
Vsliddata
Don't care
Vsliddata
TMS55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS1888- OCTOBER 1993 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
I...
_ _--.jl I'"
tw(R~
N
1 I...
Id(RLCH)
It
-.j
~
t+
I...
I I+-Id(RLC~ -+I
~
lit(RA)
N
I---
~I
~I
~I
IdCCLRH)
MId(CHR~ L
~ :I
tc(W)
j
tw(C~
VI--11
tw(RH)
1 ..I 1
I -+I t4-lt
-.j"--1
1
1
~ Id(CHR~-+I
V~ I
I I
I
1
tw(CH)
~'-
I
....... -+:141-~
~>r~·~~~~~
-+I
AO-Aa
~ fau(SFC)
1I
-.I I4t
I 1
fau(SFR)
I 1 I...
lit(RSF)
I
I
1
---.t
I
I
1
i.: J4- I ,:'" ~I1 ~
XNQQf.T11~11
~li~11
-!+i 1+
-+I ~ 1
1
I I
~I!
-.t W.
~I
,'-I,
I. . 'II,
1
~I
-+--+I 1+ I! I'" .
~I
, ,I
::-'-i !:.r fau(Wc~
I '
"'(SFR)
DSF
1
"'(TAG)
fau{I'RG)
fa
I
I... 1 ,
.
u(WMR)
:
,...
'"
lit(RWM)
.. I
lit(CLW)
~I~~I
===
1
I
1
DQO-DQlIS
1
fau(WCH)
fa (WRH)
u
th(RLW)
tw(WL)
,
-.t
~ fau(DC~
'14
1,
~
_
th(eLO) - . I
"'(RLO)
WrIte Mukt
~I_ _""'~""'~~~~~~
t Load-write-mask-reglster cycle will put the device Into the perSistent write-per-blt mode.
Rgure 30. Load-Wrlte·Mask-Reglster-Cycle TIming (Early-Write Load)
~1EXAS
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MULTIPORT VIDEO RAM
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PARAMETER MEASUREMEN;r INFORMATION
14
_ _...,jl 14
Ii
I 14
It -.I j+-
-+i ~
I
~I
14
I
tct(CHRL)
I 14-
tct(RLCL)
0I I+- -+lLI -...! :
I
I I+"H
-+I
I ~ I+- It
tct(CLRH)
th(RA)~~
tw(RH)
tct(CHRL)
-+I
l-.
~.vtJ,-+I-----~
tw(CL)
1'+1
I 14I·
I -II
I 1
I
~I
tct(RLCH)
wwWll.
'ttltI
~
tc(W) .
tw(RL)
-
tw(CH)
---+I '-
AO-AS
I ~
teu(SFR)
DSF
-+! j4t
1
I
..
~n,~ lii4~_=
*
teu(1'RG)
W4
teU(WMR)i
NW-------
*t
Access time Is laICAl dependent.
Output can go from the high-impedance state to an invaJid-data state prior to the specified access time.
Figure 36. Enhanced-Page-Mode Read/Write-Cycle Timing
~.1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
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TMS55166
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MULTIPORT VIDEO RAM
SMVsl66B-OCTOBER 1993-REVlSEDJUNE 1895
PARAMETER MEASUREMENT INFORMATION
~
~
_ _......1 I~
}~,
I~
I I~
i+-1cI(RLCL) --+I
ttt(RA)
I I ,
I
I
I
~ tau(RA)
taU(SFR)
+I
I
0i~ I
1
1
1
'
I I~
., th(SFC)
ttt(RSF) I
.,
-+I!4t tau(SFC)
I~
~
~tlj4-ttt(SFR)11
I
tw(CH)
1'--'
.J
I
I
~ ~
~
I
mr I
tau(TRG)
. I
I
I
T ' _ l + - t h ,( T R
, G)
1
.
11
-+I
I
I
th(RWM)
I
1
II
,
I
_~
,',
DSF'tlll1.IIWII
WEx
I
I
•..1 !+t-I IcI(CHRL) --+I
"I!
..
I ,
.11
~'--
~,~l",'~,'"
I 1
TRG
1
'---(CL)
14
tI :+-
.,
IcI(CLRH)
N'"
~I
CAS~II
AO-AS
fi+- tw(RH)
, ~ I+-tt
IcI(RLCH)
!.i=
~II
-+'
I
iA
I T~
tt-+l ~
IcI(CHRL) ~
~
.1
twIRL)
~~~~~~~~~~~~~~~~~~~~~~
/.tI teu(WMR) I~I~ I1 11
I~
-t--+!
~
I+-
1 I
I
I
I
~
\Yx?Ohl
teu(WCH)
tau(WRH)
1 1
Ih(RLW)
1 I~
th(CLW)
teU(WCL)
1*
I '
I~II
1
I
1
I~
'~I
'I~
I
I
~
.,
1
.1
1
~
r----
1
-+: I4t
.1
tw(WL)
.1
teu(DCL)
Ih(CLD)--~.1
Ih(RLD) _ _ _ _~.I
I
~~~5 ~~l"rft"l~~l"rft"l~~1"--__Va_I_ld_CO_IO_r_lnp_ut_ _~~
Figure 37. Load-Color-Reglster-Cycle Timing (Early-Write Load)
~1ExAs
5-294
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, -rexAS 77251-1443
TMS55166
262144 BY 16·BIT
MULTIPORT VIDEO RAM
\~
SMVS18SB- OCTOBER 1993 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
1 1l1li
RAS
--....,jN
,
It -+!
_I
IcI(C~
CAS
~~
5&1
twIRL)
L..
I~
'l1li
~
II
,, ,I+--
..,
.. ,
,
~I
tw(CL)
, , .1
tw(RH)
-+I
,
.,
,
!+t--1cI(CHRL)--.t
,
N~
r i...-
-+I 14- It
I
JJ'
lcI(cLRH)
! !.-1cI(RLCL) -.I
L
l/j
IcI(RLCH)
~
~
I
.1
i"-
I
" ,l1li "
th(RSF)"
tw(CH)
.,
M-AO
+J iIIIIt
leu(SFR)
. th(SFR)
fRO
-H+I !+- -+I
rNQQ-
~~
Figure 44. Hldden-Refresh-Cycle Timing
Table 15. Hldden-Refresh-Cycle State Table
STATE
CYCLE
1
CBR refresh with option reset
CBR refresh with no reset
CBR refresh with stop point set and no option reset
2
L
3
Don't care
Don't care
H
H
H
Stop address
H
L
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
5-301
TMS55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS186B- OCTOB.ER 1993 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMAnON
14
I 14
tc(TAD)
--------X
-il141-----~.,
I r-
teU(RA)~ ~
teU(SFR)
14
~
SC
~
14
---J~
Old Data
t
I
.
1 HI-Z+I--.....Ili..-----------
\"--':1
tcs(dLSH)
tcs(RLSH)
*
.
:
~
~II
1
QSF
1
I
-:II
14
I
..
~
tw(SCL)
i~\\~)\\\~ ~~tw(SCH)~,'---_~
j4- "(SQ)
SQ
"'(SFR)
I
!
14
tw(CL)-Y
teu(CA)
--../
11~"O"O"I:mc~~~~~"O"O"I~~~~~~~
I
14- tcs(S~) -tt
14
~
I..
li1(SHSQ)
~I
--t~~_ __
~T~~:_
.
I
-
tw(SCH)
I
tw(RH)
:======
r-+=
":"l.CAj II i~
"'(RA) --:
~ :R~
~
I
I
N-
~
14-1- tcs(CARH) ~
I I
I
I j4- tcs(RLCA) --.I
~
0000015
~
--------to!~
~
1
tcs(RLCH)
I I
vvvvvJ,
DSF
tcs(RLCL)
I
tcs(CHRL)
AO-AS
tw(RL)
I:!Da~
I·
=--
1
"'i8H8Oi
Old
~
.
f4- tcs(GHQSF)
0
tc(SC)
~
..1SOl
2 "------"'~~"A1
JX.
New Data
;;
NOTES: A. DQ outputs remain In the high-impedance state for the entire memory-to-data-reglster-transfar cycle. The
memory-to-data-raglster-transfar cycle is used to load the data registers in parallel from the memory array. The 258 IocatIone
In each data register are written into from the 258 corraspondlngcolumns of the selactad row.
B. Once data Is tranafarrad Into the data registers. the SAM is In the aerial-read mode O.e •• SQ is enabled). aHowlng data to be
shifted out of the registers. Also. the first bit to read from the data register after'i'FiG has gone high must be activated by a positive
transition of SO.
O. AO-A7: register tap point; AS: which half of the tranafarrad row
D. EarIy-load operation is defined as th(TRG) min < "'(TAG> < Id(RLTH) min.
FIgure 45. Full-Reglster-Transfer Read nmlng, Early-Load Operations
~ThxAs
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INSTRUMENTS
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TMS55166
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MULTIPORT VIDEO RAM
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PARAMETER MEASUREMENT INFORMATION
~
~~~
~
0.
~lcI(RLCL)i
lcI(CHR~
H
I
I
I
I I
(RA)
~~ow
I
I
I I
~ ~ teu(CA)
I L
~ lfI(RLCA)
: I
teu(SFR) ~ l1li
DSF
tw~H)
~'__ _
U~
i I--lcI~LCA) ~ ~tw(~ Y
~lfI
-.I
~
teu(RA)
lcI~LCH)
14
I
I
I"
~
AO-AS
1I
tc(TRD)
________~I ~
~
1
I
I
I
I
I
I
I
I
!
I
I
I
~T~~:t
I
I
~
lfI(SFR) I
IIII~
~II
.J
teu(TRG) I..
~I
~
I
lcI(CLTH)
I I
II"
I
-+14e--...~ r
lcI(CAGH)
14
lcI(RLTH)
~ 14
I
~
L
teu(WMR)
I
lcI(THR~
~.
~ ~ lcI(THRH)
Y~tw(GH)----I~
I I
m§Wi~
I
I
DQO-DQ15
I
~(SCH) --jIII~f---~~
SC
_--..II!I
I,
1-0 ~
~ te(SQ);.I I..
1_
SQ
It!(SHSQ)''
Old Data
*
II
91 I
)
" tw(SC~
:
Old Data
.
:
;
I
lITI~
X.
\~
Ij
j4
I
I
::
.,
I
-OSF
I
I"
~lcI(THsC)
I HI.z-l-I---IoI---------I
I
I
_
II \1I
I
tc(SC)
14- ta(SO) ~
~
*iP------
~
~
It!(8HSQ) 14
Old Data
I+- tcI(GHQSF) -+!
~
New Data
... ~~ ...,
NOTES: A. DQ outputs remain In the high-Impedance state for the entire memory-to-data-reglster-transfer cycle. The memory to data
register-transfer cycle Is used to load the date registers In parallel from the memory array. The 258 locations in each data register
are written Into from the 258 corresponding columns of the selected row.
B. Once data Is transferred Into the data registers, the SAM Is In the serial-read mode Q.e., sa Is enabled), allowing data to be shifted
out of the registers. Also, the first bit to read from the dsta register after TRG has gone high must be activated by a positive transition
ofSC.
C. AIJ-A7: register tap point; M: identifies the DRAM half of the row
D. Late load operation Is defined as Id(THRHl < 0 ns.
Figure 46. Full-Reglster-Transfer Read Timing, Real-Time Load Operation/late-load Operation
~lExAs
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MULTIPORT VIDEO RAM
St,1VS1 fIIIB - !JCTOBER1993 - REVISED JUNE 1995
PARAMETER MEAS'UREMENT INFORMATION
~
I I: ,
-----liN
tcI(CHRL)
~~~
lA
I
I
~I I
I
~
~L) ---~.I I+- tw(RH) -+I
tcI(RLCL)
tcI(RLCH)
l
,
~ '4
'
\
'----~--
tw(CH) -'--~.I
I
Ii4- tw(CL) -+jI " -1r-------9~~~
tcI(RLCA)
fV'..'V'.J'V'
AD-AS
I
Tap Point AD-AS
I I
INo./V'V'VV'
I II
,
'
I'
~ t4- "'(SFR)
1
teU(SFR)-+j
XJOOC;<.XT I I~
'>OOOOIY I I
I
DSF
'
~~
DQODQ16
i -.II+II
tcI(MSRL) -!4--~·1
~(SC)
H~----~I
I ----------------
tcI(RHMS)
I '+- ~(SC) --+I
I
se
SQ
QSF
NOTE A:. AO-M: tap point of the given half; A7: don't care: M: Identifies the DRAM half of the row
Figure 47. Split-Register-Transfer Read nmlng
~1ExAs, '
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON; TEXAS 77251-1443
~--~
TMS55166
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SMVS188B -OCTOBER 1993 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
'-u(TRG)
'-III
SC
___~
i4
1
-.J
SQ
.
.-II
I4f
----.
~
14-
~~~-----~----~--------------~-------14---- tc(SC)
~
tc(sC)
I14
I
---:
~
i4
~
01.
lw(ScH)
~I
~
I
~
I
~\!.~ lw(ScL) ~.vf
th(SHSQ)
~(SHSQ) ~14--.!~
valid Out
!
"\,...__
I
·r--I~~'-(SQ)4
I
:M
~(SHSQ) ~ ~
valid Out
lw(ScH)
I
I
.lt1
.~
l..
Ia(SQ)
~
I
I
I
ol ~1w(SCL)~ I
lw(ScH)
~
I
'-(SQ)
M
valid Out
1a(SE)
~~I----------------------------------
NOTE A: While reading data through the serial-data register, 'i'RG Is a don't care, except'i'RG must be held high when ~ goes low. This Is
to avoid the Inlliatlon of a reglster-data transfer operation.
Figure 48. Serial-Read Timing (SE
=VIL)
~TEXAS
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MULTIPORT VIDEO RAM
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PARAMETER MEASUREMENT INFORMATION
RAi
.
..
teu(I'RG)
~ ~:IIII-=--:"-----IlI;:-ItI-(l'R-G-)----------
TRG
1III/41-----Ic(Sc) ---~.,
14
tw(SCH)
sc
.LI4r---"'~-
1c(SC)
I
-------.11~
14
;t
Ij4
l
I I
_ _ _ _ _""" I
SQ
~
~I
I
I
14-/4---IIlIt+- 'wISCH)
1 j4-fw(SCll-.. I
I
\l . Yr-;- -....,\-__
I
14- tw(SCL) -111,0
~ ~I ta(SQ)
~ l+1- ItI(SHSQ)
'wISCH)
I
14-1..--101-
ta(SQ)
r
L..-
li4Ij4~I-I-- It!(SHSQ)
r- ta(SE)
Jo---------.i. , _____
valid Out
valid Out
valid Out
I
I
II1I--+I-
SE ____________
~~
tclls(SE)
I - - - - - - - - - ------I
I
I
.\J~I__________________________
NOTE A: While reading data through the serlal-data register, 'fAG Is a don't care except 'fAG must be held high when
is to avoid the Initiation of a register-data transfer operation.
Figure 49. Serial-Read Timing (SE-ControUed Read)
~1ExAs
6-308
te(Sa)
INSTRUMENTS
POBTOFFICE BOX 1+13· HOUSTON. TEXAS 77261-1+13
m
goes low. this
TMS55166
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MULTIPaRT VIDEO RAM
SMVS166B - OCTOBER 1993 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
,
,-t,S
CAS
ADDR
x:::x::::x~=~~~
RowTap1
RowTap1
I RowTap2
I RowTap2
(low)
TRG
DSF
I'
~~'r-S- ~~'r-S-
,
I
I
(hIgh)
I
(low)
~~~S--
-----;--"
'j~~S--
CASE I
Tap1 1
(low) I
I
I
I
I
OSF
II
255
I'
(low)
127
~r,---r
I
I
I
~I
Bltl Tap1
1271 (hIgh)
(low)
-----\--~I--------~~~
I
I
I
CASElli
1/
I
I
I
-------+-I---~
I
SC
127 (hIgh)
---...l\~--il---------\'Is--V
CASE II
OSF
I
I
I
I
~~sQ-
SC
SC
~~
r---
'-'
'--'
I
I
I
I
OSF
(high)
~sQ-
~S
I
I
I
I
255
I'
(low)
127
~r,---r
I
I
I
------..,.I----~~QKyVY~sQI
I
(low)
.
1271 (hIgh)
II
----\~--...I------~'jH
Full.Reglster-Tranater Read
I
I
I
Split Raglater to the
High Half of the
Data Register
I
I
I
II
II
Spilt Register to the
Low Half of the
Data Reglater
I
I
II
I
I
255
(low)
127
'~r---r
Spilt Register to the
High Half of the
Data Regleter
NOTES: A. In order to achieve proper spilt-register operation, a full-reglster-transfer read should be performed before the tlrat
spllt-reglster-transfer cycle. This Is necessary to Initialize the data register and the starting tap location. Firat serial access can then
begin either after the fun-reglstar·transfer read cycle (CASE I), during the tlrat spllt-reglster·transfer cycle (CASE II), or even after
the flrat spllt-reglster-transfer cycle (CASE III). There Is no minimum requirement of se clock between the full-reglster-transfer read
cycle and the first spilt-register cycle.
B. A spllt-reglster-transfer Into the Inactive half Is not allowed until ld(MSRL) Is met. ldCMSflL) Is the minimum delay time between the
rising edge of the ~rlal clock of the last bit (bit 127 or 255) and the failing edge of RAS of the spllt-reglstar-transfer cycle Into the
inactive half. After the ld(MSRL) is met, the split-reglster-transfer Into the Inactive half must also satisfy the minimum ld(RHMS)
requirement.ld(RHMS) is the minimum delay time between the rising edge ofRAS of the spllt-reglster-transfer cycle Into the Jnactive
half and the rising edge of the serial clock of the last bit (bit 127 or 255).
Figure SO. Spllt·Reglster Operating Sequence
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUS'TON. TEXAS 77251-1443
5-307
TMS55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS168B - OCTOBER 1993 - REVISED JUNE 1995
device symbolization
~
Speed(-
TMS55168~
PackageCode
F
R
A~T
I
Lot Traceability Code
Date Code
AseemblySIteCoda
DleRevlalonCoda
Wafe rFabCoda
~1ExAs
5·308
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON,1EXAS 77251-1443
6-1
Contents
CHAPTER 6.
.TM41 OOGAD8
TM497GU8
TM4100EAD9
TM497EU9
TM124BBK32
TM124BBK32S
TM248CBK32
TM248CBK32S
TM124BBK32F
TM124BBK32U
TM248CBK32F
TM248CBK32U
TM497BBK32
TM497BBK32S
TM893CBK32
TM893CBK32S
TM124MBK36B
TM124MBK36R
TM248NBK36B
TM248NBK36R
TM124MBK36F
TM124MBK36U
TM248NBK36F
TM248NBK36U
TM124MBK36C
TM124MBK36S
TM248NBK36C
TM248NBK36S
TM124MBK36G
TM124MBK36V
TM248NBK36G
TM248NBK36V
TM497MBK36A
TM497MBK36Q
TM497MBM36A
TM497MBM36Q
TM893NBM36A
TM893NBM36Q
SINGLE-IN-LiNE MEMORY MODULES (SIMMS)
4 Mbyte
4 Mbyte
4 Mbyte
4 Mbyte
4 Mbyte
4 Mbyte
8 Mbyte
8 Mbyte
4 Mbyte
4 Mbyte
8 Mbyte
8 Mbyte
16 Mbyte
16 Mbyte
32 Mbyte
32 Mbyte
4 Mbyte
4 Mbyte
8 Mbyte
8 Mbyte
4 Mbyte
4 Mbyte
8 Mbyte
8 Mbyte
4 Mbyte
4 Mbyte
8 Mbyte
8 Mbyte
4 Mbyte
4 Mbyte
8 Mbyte
8 Mbyte
16 Mbyte
16 Mbyte
16 Mbyte
16 Mbyte
32 Mbyte
32 Mbyte
(4096K lC 8) Single-Sided (Solder-tabbed) ••••.•.••.•.•••••.••••••• 6-3
(4096K lC 8) Single-Sided (Solder-tabbed) •••••••••••.•••••.•.••.•• 6-9
(4096K lC 9) Single-Sided (Solder-tabbed) ••••••.•••••.•••••.••••• 6-15
(4096K lC 9) Single-Sided (Solder-tabbed) •••••••••••••••.•••..••• 6-23
(1 024K lC 32) Single-Sided (Gold-tabbed) .••.....•.•.••••••••••••. 6-29
(1 024K lC 32) Single-Sided (Solder-tabbed) .•.•.....•••..•••••...• 6-29
(2048K lC 32) Double-Sided (Gold-tabbed) ..•••....•.•.....••••... 6-29
(2048K lC 32) Double-Sided (Solder-tabbed) ••••...........•..•..• 6-29
(1 024K x 32) Single-Sided (Gold-tabbed) •..•.•..•.•.•.•.•.•.••.•. 6-39
(1 024K l(32) Single-Sided (Solder-tabbed) ••..••.••••.••••••••••• 6-39
(2048K lC 32) Double-Sided (Gold-tabbed) ...••......•.•......•... 6-39
(2048KlC 32) Double-Sided (Solder-tabbed) .•••.•..•••••.•.•••••• 6-39
(4096K ic 32) Single-Sided (Gold-tabbed) ••.••••.....•••.......•.. 6-47
(4096K lC 32) Single-Sided (Solder-tabbed) •.•...•.....••••••••••• 6-47
(8192K lC 32) Double-Sided (Gold-tabbed) ........................ 6-55
(8192K lC 32) Double-Sided (Solder-tabbed) .......•••.•.•.••••••• 6-55
(1 024K lC 36) Single-Sided (Gold-tabbed) ••.••••..........•....•.. 6-63
(1 024K lC 36) Single-Sided (Solder~tabbed) .•.•.•....•............ 6-63
(2048K lC 36) Double-Sided (Gold-tabbed) .•••.•••.....•.•....•••. 6-63
(2048K lC 36) Double-Sided (Solder-tabbed) ••..•.••••....••..•••• 6-63
(1 024K lC 3e) Single-Sided (Gold-tabbed) •.••••••....•.•......•••. 6-73
(1 024K lC 36) Single-Sided (Solder-tabbed) .•••......•..•......•.. 6-73
(2048K lC 36) Double-Sided (Gold-tabbed) •.••••••...•••.......... 6-73
(2048K lC 36) Double-Sided (Solder-tabbed) •........•....••..•.•. 6-73
(1 024K lC 36) Single-Sided (Gold-tabbed) .•.•••......••........... 6-81
(1 024K lC 36) Single-Sided (SOlder-tabbed) .•...••••.•.•.•.••.•••. 6-81
(2048K x 36) Double-Sided (Gold-tabbed) •••••••••••••••••••••••• 6-81
(2048K lC 36) Double-Sided (Solder-tabbed) •••......•.........•.. 6-81
(1 024K lC 36) Single-Sided (Gold-tabbed) •..•••••. . • . • . • . . • . • . . . •. 6-91
(1 024K lC 36) Single-Sided (Solder-tabbed) .•.•......•.....•.•.•.. 6-91
(2048K lC 36) Double-Sided (Gold-tabbed) ••••••••...••.•••...••.. 6-91
(2048K lC 36) Double-Sided (Solder-tabbed) •.•...••.•.•.......... 6-91
(4096K lC 36) Double-Sided (Gold-tabbed) .....•.• ~ ••.....•.•..•.• 6-99
(4096K lC 36) Double-Sided (Solder-tabbed) ..•........•....•..... 6-99
(4096K lC 36) Single-Sided (Gold-tabbed) .•.•.....••••..•.•...••• 6-107
(4096K lC 36) Single-Sided (Solder-tabbed) ••..•....•...•••••.•.. 6-107
(8192K lC 36) Double-Sided (Gold-tabbed) •••...••••••..•.•..••.• 6-107
(8192K lC 36) Double-Sided (Solder-tabbed) ............•.•••.•.. 6-107
~1ExAs
6·2
INSTRUMENTS
POST OFFICE BOX 1_ • HOUSTON. TEXAS n251-1_
TM4100GAD8
4194304 BY 8·BIT DRAM MODULE
• Organization ••• 4194304 x 8
• Single 5-V Power Supply (~10% Tolerance)
• 3O-Pln Single In-Line Memory Module
(SIMM) for Use With Sockets
• Utilizes Eight 4-Megablt DRAMs In Plastic
Smail-Outline J-Lead Packages (SOJs)
SINGLE IN-UNE MODULE
(TOP VIEW)
Vee
CAS 2
001
AD
A1
002
A2
A3
• Long Refresh Period
16 ms (1024 Cycles)
• All Inputs, Outputs, Clocks Fully TTL
Compatible
3
4
5
8
7
8
Vss 9
• 3-State Output
• Performance Ranges:
ACCESS ACCESS ACCESS
TIME
TIME
TIME
'4100GAD8-60
'4100GAD8-70
'4100GAD8-60
1
'RAc
tAA
tcAC
(MAX)
60 ns
70 n8
60 ns
(MAX)
30 ns
35 ns
(MAX)
15 ns
18 ns
20 ns
003 10
A4 11
AS 12
004 13
All 14
A7 15
005 18
All 17
AS 18
A10 19
D08 20
W 21
READ
OR
WRITE
CYCLE
(MIN)
110 ns
130 ns
150 ns
40 ns
• Common CAS Control for Eight Common
Data·ln and Data-Out Lines
Vss 22
007
NC
008
NC
• Low Power Dissipation
• Operating Free-Air Temperature Range
O·Cto 70·C
23
24
25
28
27
28
29
30
RAS
NC
NC
Vee
o
D
D
D
D
D
D
D
D
0'
description
The TM4100GAD8 is a dynamic random-access
memory (DRAM) module organized as 4194304
x 8 bits in a 30-pin leadless single in-line memory
module (SIMM).
The SIMM is composed of eight TMS44100DJ
4194304 x 1-bit DRAMs in 20/26-lead plastic
smail-outline J-Iead packages (SOJ) mounted on
a substrate with decoupling capacitors.
The TM4100GAD8 is available in the AD
single-sided, leadless module for use with
sockets.
PIN NOMENCLATURE
AD-A10
CAS
001-008
NO
RAS
Vee
VSS
W
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Connection
Row-Address Strobe
5-VSupply
Ground
Write Enable
The TM41 OOGAD8 Is characterized for operation
from o·e to 70·e.
-
operation
The TM41 OOGAD8 operates as eight TMS441 OODJs connected as shown in the functional block diagram. Refer
to the TMS441 00 data sheet for details of its operation. The common I/O feature of the TM41 OOGAD8 dictates
the use of early-write cycles to prevent contention on 0 and C.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
Copyright C 1996. Texas Instruments Incofporatad
6-3
TM4100GAD8
4194304 BY 8-BIT DRAM MODULE
SMMS508C- MARCH 1982 - REVISED JUNE 1986
Single In-line m~mory module and components
PC substrate: 1,27 mm (0.05 Inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: NiCkel plate and solder plate over copper
functional block diagram
AO-A10
iUtI
~
Vi
4098)( 1
, 1 \ AO-A10
DQ1
""
...
I
DQ2
iUtI
~
Vi
DQ1
Vee Vss Qn
.RAj
"
~
1
~
DOS
4098)( 1
AO-A10
~
"
4098)(1
11\. AO-A10
Vi
DQ2
Vee Vss
003
1
~
.""
DQ4
I
01
"
DQ6
;;:
~
Vi
DQS
Vee Vss Q l
"
1
RAS
"
Vi
DQ3
vee Vss Qn
IQI
~
Vi
DQ6
Vee Vss Q l
40118" 1
1 11,,,, AO-A10
4098" 1
AO-A10
DQ7
4098" 1
AO-A10
"
1
~
RAS
~
iUtI
cAS
Vi
DQ7
vee Vss Q l
40118)( 1
AO-A10.
HAl
"- ~
Vi
DQ4
Vee Vss Qn
DQ8
1
Vee
I
iUtI
4098)(1
1 11,,, AO-A10
" cAS
"
""
r:: e ....e ;;: r::
Vss
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. 'TeXAS 77251-1443
"
I
Vi
DQ6
Vee Vss Qn
I
TM4100GAD8
4194304 BY 8-BIT DRAM MODULE
SMM~C-MARCH1~-R~SEDJUNE1~
absolute maximum ratings over operating free-air ~emperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) • . . . . . . • . . . . • . • • • . . . . • . . . . • . . . . • • • . • • • • • •• -1 V to 7 V
Supply voltage range on Vee ........................................................ -1 V to 7 V
Short-circuit output current •••••••••••••••.•.•.•..........••••••••••..••••••••..••••••••••• 50 rnA
Power dissipation •••••••••••••••••. ~ • . . . • • . . . • • • • . . • . . . . . . . • . . • • . • • • • . • . • • • • • • • • . . • • • • . • . .• 8 W
Operating free-air temperature range, TA ..........•.....•.................•••••••••••• O°C to 70°C
Storage temperature range ••.•..•.....•...••••.•••••••••••••••••.•••..•••..•••••• - 55°C to 125°C
t Stresses beyondthoae listed under "absolute maximum ratings" maycauaepermanent damage to the device. Th_ are stress ratlnge only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" Ie not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage va/uo are wHh ropect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level Input voltage
2.4
8.5
V
UNrr
<
Low-levellnput voltage (see Note 2)
-1
0.8
V
VIL
Operating free-air temperature
70
0
"C
TA
.
NOTe 2: The algebrBlc convention. where tha more negative (los positive) limit Is dOlgnated as minimum. Is used for logic voltage levels only•
..
.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
VOH
Hlgh-lavel output voltage
VOL
Low-lavel output voltage
II
Input current (leakage)
10
ICCl
'4100GAD8-60
TEST CONDInONS
MIN
MAX
2.4
10H--SmA
IOL",4.2mA
'4100GAD8-70
MIN
MAX
2.4
'4100GAD8-60
MIN
MAX
2.4
UNrr
V
V
0.4
0.4
0.4
VCC .. S•5V• Vi" 0 V to 8.S V.
All other pins 0 V to Vcc
:0:10
:0:10
:0:10
Output current ~okage)
VO" OVtoVCC.
CAS high
VCC .. S.5V.
:0:10
:0:10
:0:10
Reed- or wrlte-cycle current
(see Note 3)
VCC- S.5V•
840
720
840
rnA
18
16
18
mA
8
8
8
rnA
840
720
840
mA
720
840
560
rnA
1CC2 Standby current
Average refresh current
1CC3, (RAS only or CBR*)
(see Note 3)
Average page current
1CC4 (see Note 4)
=
Minimum cycle
VIH =2.4 V (TTL).
After 1 memory cycle,
RAS and CAS high.
VIH" VCC-0.2 V (CMOS).
After 1 memory cycle.
RAS and CAS high
Minimum cycle.
VCC=5.SV.
RAScycling.
CAS high (RAS only);
RAS low after CAS low (CBR*>
tpc .. minimum.
VCC-S.5V,
RASlow.
CAS cycling
""
""
* CAS-before-RAS (CBR) refroh
NOTES: 3. Measured wHh a maximum of one address change while RAS .. VIL
4. Measured wHh a maximum of one address change while CAS VIH
=
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77251-1443
8-5
TM4100GAD8
4194304 BY 8-BIT DRAM MODULE
SMMS508C- MARCH 18112 - REVISED JUNE 189S
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f= 1 MHz.
PARAMETER
MIN
MAX
40
UNIT
CllA)
Input capacitance, AO-Al0
CI(RC)
Input capacitance, CAS and RAS
56
pF
CI/WI
Input capacitance, W
56
pF
Co
Output capacitance (pIns OCl-DOS)
12
pF
NOTE 5: Vee
=5 V
:t
pF
0.5 V and the bias on the pin under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature
'4100GAD&80
PARAMETER
MIN
MAX
'4100GAD8-70
MIN
MAX
lAA
Aocess time from column address
30
35
teAc
Aocess time from CAS low
Aocess time from column precharge
Acoess time from ~ low
CAS to output In low Impedance
15
18
35
40
70
tePA
tRAC
teu
60
toFF Output disable time after CAS high (see Note 6)
NOTE 8: toFF is spaclfled when the output Is no longer driven.
0
0
0
15
0
'4100GAD&80
MIN
MAX
40
20
45
60
0
lS
0
20
UNIT
ns
ns
ns
ns
ns
ns
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature
'4100GAD8-60
MIN
tRC
Cycle time, random read or write (see Note 7)
tpc
Cycle time, page-mode read or write (see Note 8)
teHR
Delay time, RAS low to CAS high (CBR refresh only)
teRP
MAX
'4100GADS-70
MIN
MAX
'4100GAD&80
MIN
MAX
UNIT
110
130
150
ns
40
15
45
. 15
50
ns
20
ns
Delay time, CAS high to ~ low
0
0
0
ns
tcsH
Delay time, ~ low to CAS high
60
70
ns
teSR
tRAO
Delay time, CAS low to RAS low (CBR refresh only)
10
10
80
10
Delay time, ~ low to column address (see Note 10)
15
tRAL
Delay time, column address to RAS high
30
35
teAL
tRCD
Delay tillie, column address to CAS high
30
Delay time, RAS low to CAS low (see Note 10)
20
35
20
tRPC
Delay time, RAS high to CAS low
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
ns
teAH
Hold time, column address after CAS low
10
15
15
ns
tDHR
Hold time, date. after RAS low (see Note 9)
50
55
60
ns
tDH
Hold time, date
10
15
15
ns
55
60
ns
30
45
Hold time, column address after RAS low (see Note 9)
50
tAR
NOTES: 7. All cycle times assume IT • 5 ns.
8. To assure tpc min, tASC should be It tep.
9. The minimum value Is measured when IRCD is set to tRCD minas a reterence.
10. The maximum value is specified only to assure access time.
~1ExAs
INSTRUMENTS
8·8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
15
35
15
ns
40
52
20
ns
ns
40
40
ns
60
ns
TM4100GAD8
4194304 BY 8-BIT DRAM MODULE
SMMS508C - MARCH 1992 - REVISED JUNE 1895
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
'4100GAD8-60
MIN
tRAH
Hold time, row address after RAS low
tACH
Hold time, W high after CAS high (see Note 11)
'41OOGAD8-70
MAX
MIN
MAX
'4100GAD8-80
MIN
MAX
UINT
10
10
10
ns
0
0
0
ns
tARH
Hold time, W high after AAS high (see Note 11)
0
0
0
ns
twcH
Hold time, write after CAS low
15
15
15
ns
twcR
Hold time, W low after RAS low (see Note 9)
50
55
ns
twRH
Hold time, Vii high after AAS low (CBR refresh only)
Hold time, Vii low (test mode only)
Pulse duration, page mode, RAS low
Pulse duration, nonpage mode, AAS low
Pulse duration, CAS low
Pulse duration, CAS high
Pulse duration, RAS high (precharge)
Pulse duration, write
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data before CAS low
Setup time, W high before CAS low
Setup time, W low before CAS high
Setup time, W low before RAS high
Setup time, W low before CAS low
Setup time, W high before RAS low (CBR refresh only)
Setup time, W low (test mode only)
Access time from address (test mode)
Access time from colu.mn precharge (test mode)
Access time from FiAS (test mode)
Refresh time interval
Trensitlon time
10
10
60
10
10
10
10
twrH
tRASP
tRAS
teAS
tep
tRP
twP
tASC
tASR
tos
tRCS
teWL
tAWL
twcs
twRP
twrs
trAA
trCPA
trRAc
tREF
ns
ns
60
100000
70
100000
80
100000
ns
60
10000
70
10000
60
10000
ns
15
10000
18
10000
10000
ns
10
10
20
10
40
50
60
15
15
15
ns
0
0
0
ns
0
0
0
ns
0
0
0
ns
0
0
ns
15
0
18
20
ns
15
18
20
ns
0
0
0
ns
10
10
10
ns
10
10
10
ns
35
40
40
45
45
ns
50
ns
65
75
85
16
2
50
tr
NOTES: 9: The minimum value Is measured when tRCO Is set to tRCO min as a reference.
11. Either tRRH or tACH must be satisfied for a read cycle.
16
2
2
50
ns
ns
ns
16
ms
50
ns
device symbolization
I
o
TM4100GAD8
~
nDDODDDDDDDD~~DD:DODDDDDDDnn ("
YV
MM
T
-SS
=Year Code
=Month Code
=Assembly Site Code
=Speed
NOTE A: The location of symbOlization may vary.
~1ExAs
INSTRUMENTS
POST OFFICE aoXI443· HOUSTON. TEXAS 77251-1443
6·7
TM410OGAD8
4194304 BY 8-BIT DRAM MODULE
SMMSsoaC- MARCH 1982 - REVISED JUNE 1995
~1ExAs
INSTRUMENTS
. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TM497GU8
4194304·WORD BY 8-BIT
DYNAMIC RAM MODULE
• Organization ••• 4194304 x 8
• Single S-V Power Supply (:t:10% Tolerance)
• 3O-Pln Single-in-Une Memory Module
(SIMM) for Use With Sockets
• Utilizes Two 16-Megablt Dynamic RAMs In
Plastic Smail-Outline J-Lead (SOJ)
Packages
• Long Refresh Period
32 ms (2048 Cycles)
U SINGLE-IN-UNE PACKAGE
(TOP VIEW)
o
VCC
CAS
DQ1
AIJ
A1
DQ2
A2
• All Inputs, Outputs, Clocks Fully nL
Compatible
• 3-State Output
• Performance Ranges:
ACCESS
TIME
\RAc
(MAX)
'497GU8-60
'497GU8-70
'497GU8-60
60 n8
70 ns
80 n8
A3
VSS
DQ3
A4
ACCESS ACCESS READ OR
TIME
TIME
WRITE
tAA
teAC
CYCLE
(MAX)
(MAX)
(MIN)
30 n8
15 ns
110 ns
35 n8
18 ns
130 ns
40 n8
20 ns
150 ns
• Common CAS Control for Eight Common
Data-In and Data-Out Unes
• Low Power Dissipation
• Operating Free·Alr Temperature Range
O°C to 70°C
• Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR), "RAS.Only, and
Hidden Refresh
AS
DQ4
AS
A7
DQ5
AS
A9
A10 19
DQ6 20
W 21
VSS 22
DQ7 23
NC 24
DQ8 25
NC 26
RAS 27
NC 28
NC 29
VCC 30
o
description
The TM497GU8 is a 4M-byte dynamic
random-access memory module organized as
4194304 x 8 bits in a 30-pin leadless single-in-line
memory module (SIMM).
The SIMM is composed of two TMS417400DJ,
4194304 x 4-bit dynamic RAMs in 24/26-lead
plastic small-outline J-Iead (SOJ) packages
mounted on a substrate with decoupling capacitors.
PIN NOMENCLATURE
AIJ-A10
Address Inputs
CAS
DQ1-DQ8
Column-Address Strobe
NC
RAS
VCC
VSS
W
Data In/Data Out
No Internal Connection
Row-Address Strobe
5-VSupply
Ground
Write Enable
The TM497GU8 is available in the U single-sided,
leadless module for use with sockets and is
characterized for operation from O°C to 70°C.
~1ExAs
Copyright C 1995, Texas Instrumenlllincorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS n251-1443
6-9
TM497GU8
4194304-WORD BY 8-BIT
DYNAMIC RAM MODULE·
SMMS498A-APRIL 1994-REVISED JUNE 1995
operation
The TM497GU8 operates as two TMS417400DJs connected as shown In tMfunctional block diagram. Refer
to the TMS417400 data sheet for details of its operation. The commonlfQ feature of the TM497GU8 dictates
the use of early-write cycles to prevent contention on D and Q.
power up
To achieve proper operation, an initial pause of 200 !AS followed bya minimum of eight initialization cycles is
r~ed after full Vee level is achieved. These eight initialization cycles need to include at least one refresh
(RAS"-only orCBR) cycle.
singie-in-line memory module and components
PC substrate: 1,27 mm (0.05 Inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and solder plate over copper
functional block diagram
11.
AO-A10
RAS
,....
,....
,....
CAS
Vi
OE
.b
4
.b
4MlC4
AO-A10 DQ1
RAS
DQ2
CAS
DQ3
Vi
DQ4
4MlC4
AO-A10 DQ1
RAS
DQ2
"- CAS
DQ3
"- Vi
DQ4
OE
~TEXAS
INSTRUMENTS
6-10
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
DQ1
DQ2
DQ3
DQ4
DQS
DQS
DQ7
DQS
TM497GU8
4194304-WORD BY 8-BIT
DYNAMIC RAM MODULE
SMMS498A-APRIL 1994 - REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -1 V to 7 V
Voltage range on any pin (see Note 1) ................................................. -1 V to 7 V
Short-circuit output current ............................................•.••••..•.•.••.•..•• 50 rnA
Power dissipation •••.•..........................•.......••........•..•..•..••.•..••..•.•••• 2 W
Operating free-air temperature range, TA .............................................. o·e to 70·e
Storage temperature range, Tstg ... ; •.,............................................ - 55°e to 125°e
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those Indicaled under "recommended operating conditions" Is not
Implied. Exposure to abaolute-maxlmum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
VCC
Supply voltage
VIH
High-level Input voltage
MIN
NOM
MAX
4.5
2.4
5
5.5
8.5
UNrr
V
V
low-level Input voltage (see Note 2)
-1
O.B
V
VIL
·C
OPerating free-air temperature
0
70
TA
.. . .
NOTE 2: The algebreic convention. where the more negative Oess posillVe)lImills deSignated as minimum. Is used for loglc-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
'497GU8-60
MIN
MAX
'497GUB-70
MIN
MAX
'497GUB-80
MIN
MAX
UNrr
VOH
High-level output voltage
10H =-5mA
VOL
Low-level output voltage
IOL=4.2mA
0.4
0.4
0.4
V
II
Input current (leakage)
VI = OVt06.5V.
VCC=5V.
All other pins = 0 V to VCC
:1:10
:1:10
:1:10
IIA
10
Output current Oeakage)
:1:10
:1:10
:1:10
IIA
ICC1
Read- or wrlte-cycle current
(see Note 3)
220
200
180
mA
4
4
4
mA
2
2
2
mA
~=5.5V.
2.4
VO=OVtoVCC.
CAS high
VCC=5.5V.
Minimum cycle
2.4
2.4
V
=
ICC2 Standby current
VIH 2.4 V (TTL).
After 1 memory cycle.
RAS and CAS high
=
VIH VCC - 0.2 V (CMOS).
After 1 memory cycle.
RAS and CAS high
Average refresh current (RASICC3 only or CBR) (see Note 3)
VCC .. 5.5V.
RAScycling.
Minimum cycle,
CAS high
220
200
1BO
rnA
Average pege current
ICC4 (see Note 4)
~=5.5V,
K-MIN,
CAS cycling
140
120
100
rnA
RASlow.
NQTES: 3. Measured With a maximum of one address change while RAS =VIL
4. Measured with a maximum of one address change while CAS .. VIH
~lExAs
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON. TEXAS 77251-1443
8-11
TM497GU8
4194304-WORD Bya-BIT
DYNAMIC RAM MODULE
SMMS498A-APRIL1994 - REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-alr temperature,
f = 1 MHz (see Note 5)
MIN
PARAMETER
MAX
UNIT
CIIA)
CI(RC)
Input capacitance, AO-A10
10
pF
Input capacitance, ~ and RAS
14
pF
CI(W)
Inputcapacitance,VV
14
pF
7
pF
Output cepacltance, OQ1-0Q8
Co
NOTE 5: VCC. 5 V :& 0.5 V, and the bias on the pin under teSt Is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'497GU8-60
PARAMETER
MIN
MAX
'497GU8-70
MIN
MAX
'497GUS-80
MIN
MAX
UNIT
tM
Access time from column address
30
35
40
ns
tCAC
Access time from ~ low
15
18
20
ns
tCPA
Access time from column precharge
35
40
45
tRAC
Access time from RAS low
60
.70
80
ns
ns
20
teLZ CAS to output In low-Impedance state
toH
Output disable time from start of CAS high
toFF Output disable time after CAS high (see Note 6)
NOTE 8: toFF Is specified when the output Is no longer driven.
6-12
0
0
0
ns
3
3
3
ns
ns
0
I~TEXAS
NSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON, TEXAS 77251-1443
15
0
18
0
TM497GU8
4194304-WORD BY 8-BIT
DYNAMIC RAM MODULE
SMMS498A-APRIL 1994-REVISEDJUNE 1995
timing requirements over recommended ranges of supply voltage and operating fre...lr
temperature
'497GU8-60
'497GU8-70
'497GU8-60
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tRC
tpc
Cycle time, random raad or write (see Note 7)
110
130
150
ns
Cycle time, page-mode read or write (see Notes 7 and 8)
40
45
50
ns
tRASP
Pulse duration, RAS low, page mode
60 100000
70
100000
tRAS
teAs
Pulse duration, RAS low, nonpage mode
60
10000
70
Pu~du~,CASlow
15
10000
18
tep
Pu~ duration, CAS high
10
10
10
tAp
Pulse duration, RAS high (pracharge)
40
50
80
twP
10
10
10
0
0
0
0
0
0
ns
0
0
0
ns
tRCS
Pulse duration, W low
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data before CAS low
Setup time, iN high befora CAS low
0
0
0
tcwt.
Setup time, W low befora CAS high
15
18
20
ns
ns
tRWL
Setup time, W low befora RAS high
Setup time, W low before CAS low
15
18
20
ns
0
0
0
ns
Setup time, W high before RAS low (CBR refresh only)
10
10
10
ns
Hold time, column address after CAS low
10
15
15
ns
Hold time, data after CAS low
10
15
15
10
10
10
ns
ns
0
0
0
ns
tRRH
Hold time, row address after RAS low
Hold time, W high after CAS high (see Note 9)
Hold time, iN high after RAS high (see Note 9)
0
0
0
twoH
Hold time, W low after CAS low
10
15
15
ns
ns
twRH
tRHCP
Hold time, iN high after RAS low (CBR refresh only)
10
10
10
ns
35
40
45
teHR
Hold time, RAS high from CAS pracharge
Deley time, RAS low to CAS high (CBR refresh only)
10
10
10
ns
ns
teRP
Delay time, CAS high to RAS low
5
5
5
ns
teSH
Delay time, RAS low to CAS high
60
70
80
ns
teSR
tRAO
Delay time, CAS low to RAS low (CBR refresh only)
5
5
5
ns
ns
tASC
tASR
tDS
twos
twRP
teAH
tDH
tRAH
tRCH
60 100000
ns
10000
80
10000
10000
20
10000
ns
n8
tRAL
Delay time, RAS low to column address (see Note 10)
Delay time, column address to RAS high
30
35
40
teAL
Delay time, column address to CAS high
30
35
40
tAco
tRPC
Delay time, RAS low to CAS low (see Note 10)
belay time, RAS high to CAS low
Delay time, CAS low to RAS high
Refresh time interval
20
tASH
tAEF
Transition time
NOTES: 7. All cycle times assume tr =5 os.
B. To essure tpC min,lASC should be '" tep
9. Either tARH or tACH must be satisfied for a read cycle.
10. The maximum value is specified only to assure access lime
Itr
15
30
45
15
20
35
52
15
20
0
0
0
15
18
20
32
3
30
32
3
30
ns
ns
ns
ns
40
ns
80
32
3
30
ns
ns
ns
ns
ms
ns
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
8-13
TM497GU8
4194304-WORD BY 8-BIT
DYNAMIC RAM MODULE
SMMS498A-APRIL 1994 - REVISED JUNE 1895
device symbolization
I
TM497GU8
)
~I
o 000000000000:00:00000000000 (=
YY
Ve.r Code
MM .. Month Code
T • Aaaembly Site Code
-SS • Speed
NOTE: The location of the part number may vary.
~TEXAS
6-14
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77261-1443
TM4100EAD9
4194304 BY 9-BIT
DYNAMIC RAM MODULE
• Organization ••• 4194304 x 9
• Single 5-V Power Supply (:t10% Tolerance)
• 30-Pln Single In-Une Memory Module
(SIMM) for U.e With Sockets
• Utilize. Nine 4-Megablt Dynamic RAM. In
PlasUc Smail-Outline J-Lead Package.
(SOJs)
SINGLE IN-LINE MODULE
(TOP VIEW)
o
DQ1
2
3
AO
A1
5
4
DQ2
6
A3
7
8
A2
ti8~ 1~
• 3-State Output.
• Performance Ranges:
A4 11
ACCESS ACCESS ACCESS
TIME
TIME
TIME
WRITE
(MAX)
(MAX)
(MAX)
CYCLE
(MIN)
'4100EA09·60 60 n8
'4100EAD9-70 70 ns
'4100EAD9-80 80 n8
15ns
18 ns
20 ns
30n8
35ns
40 ns
110 n8
130 ns
150 ns
AS
A9
17
18
·A10 19
DQ§ 20
W 21
Vss 22
DQ7 23
• Common CAS Control for Eight Common
Data-In and Data-Out Une.
• Separate CAS Control for One Separate
Pair of Data-In and Data-Out Unes
NC 24
DQS 25
Q9 26
27
Fi7iS
CAS9 28
09 29
• Low Power Dissipation
• Operating Free-Air Temperature Range
O°C to 70°C
VCC 30
D
D
D
D
D
D
D
D
D
o
description
The TM4100EA09 i$·a dynamic random-access
memory module organized as 4194304 x 9 [bit
nine (09, 09) is generally used for parity and is
controlled by CAS9] in a 3D-pin leadless Single
in-line memory module (SIMM).
This module is composed of nine TMS441000J,
4194304 x 1-bit dynamic RAMs (DRAMs) each in
a 20/26-lead plastiC small-outline J-Iead package
(SOJ) mounted on a substrate with decoupling
capacitors.
The TM4100EA09 is characterized for operation
from O°C to 70°C and is available in the AD
single-sided, leadless module for use with
sockets.
PIN NOMENCLATURE
AO-A10
~,CA$
DQ1-DQ8
09
NC
Q9
RAS
Vee
VSS
W
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
Address Inputs
Column·Address Strobe
Data In/Data Out
Data In
No Internal Connection
Data Out
Row·Address Strobe
5·VSupply
Ground
Write Enable
Copyright C 1995. Texas Instruments lncOlporalad
6-15
TM4100EAD9
4194304 BY 9-BIT
DYNAMIC RAM MODULE
SMMS419C- NOVEMBER 1991'- REVISED JUNE 1995
functional block diagram
AO-A1D
AM
58
W
I
4
.",
'"
'"
D01
I
'"
"
4
D03
'II
D
I
Vss
CAS
Vi
D
~:'
Dvce
"
'"
I
°l'
Vss
Vss
4096Kx1
AO-A10
RAS
eAS
W
D
Vee
Vss
DOS .
°l
on
°l
DOS
I
D07
D08
"
Vss
~ThxAs
INSTRUMENTS
POST OFF\CEBOX 1443" HOUSTON. l1:XAS 77251-1443
4096Kx1
AO-A1D
RAS
58
Vi
D
Vcc
"
I
~
."
'"
I
~
""
Vss
aD
4096Kx1
AO-AiD
AM
CAS
Vi
D
Vcc
'"
Vee
8-18
"
~
Q9
c ••••c:;::
I
'"
D9
"
'"
~
CAS9
:;::
~r-.
"
AM
4096Kx1
" AO-A1D
'" RAS
~
.
4096Kx1
AO-A1D
Vee
I
D04
58
Vcc
~
DQ2
4096Kxi
AD-AiD
RAS
Vss
an
409SKx1
AO-A1D
RAS
58
Vi
D
Vce
Vss
4096Kx1
AO-A10
RAS
CAS
Vi
D
Vce
Vss
4096Kx1
AO-AiD
RAS
CAS
Vi
D
Vcc
I
Vss
°l
°l
an
TM4100EAD9
4194304 BY 9·BIT
DYNAMIC RAM MODULE
SMMS419C-NOVEMBER 1991-REVlSEDJUNE 1996
operation
The TM41 00EAD9 operates as nine TMS441 OODJs connected as shown in the functional block diagram. Refer
to the TMS441 00 data sheet for details of its operation. The common I/O feature of the TM41 OOEAD9 dictates
the use of early-write cycles to prevent contention on D and a.
single In·llne memory module and components
PC substrate: 1.27 mm (0.05 inch) nominal thickness; 0.005 incMnch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and solder plate over copper
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-17
TM4100EAD9
4194304 BY9-BIT
DYNAMIC RAM MODULE
SMMS419C- NOVEMBER 1991 - REVISED JUNE 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) .................................................. -1 V to 7 V
Voltage range on Vee (see Note 1) ................. '. . • . . . . . . . . . . . . . . . . . • . . . . . . • • • . . •. - 1 V to 7 V
Short-circuit output current .•.•....•..•.....•...•.•......•..•.........•. '.' . • • • • • . . . . . . . . . •. 50 mA
Power dissipation .•.......•. '. • • . . . . . • . . . . . . . . . • • . . . . . . . . . . . . • . • . • • . • . . . . . . . • . • . . . . . . . . . . • .• 9 W
Operating free-air temperature range, TA .. . .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . .. .. .. .. .. ooe to 700 e
Storage temperature range, Tstg ......•••••.............•.....•. : ........•.• ~ •.•.. - 55°e to 125°e
t Stresses beyond th08811sted under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect, device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
Vcc
Supply voltage
High-level Input voltage
MIN
NOM
MAX
4.&
&
&.&
UNIT
V
2.4
8.&
V
VIH
Low-level Input voltage (see Note 2)
-1
0.8
V
VIL
·C
Operating free-air temperature
70
0
TA
NOTE 2: The algebraic convantion, where the more negatIVe (less positive) limit Is deSignated as minlmum,'ls used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
'4100EADNO
MIN
MAX
2.4
0.4
'4100EAD9-70
0.4
0.4
V
V
MIN
2.4
MAX
'4100EAD9-80
MAX
MIN
2.4
UNIT
VOH
VOL
High-level output voltage
Low-ievel output voltage
10H--&mA
IOLoo4.2mA
II
Input current (leakage)
Vcc"&.&V,
VI'" 0 Vto 8.& V,
All others .. 0 V to VCC
:t10
:t10
:t10
I!A
10
Output current (leakage)
VCC .. 5.5V,
eAShlgh
VO" OVto VCC,
:t10
:t10
:t10
I!A
ICC1
Reed- or writa-cycIe current
(see Note 3)
VCCoo5.&V,
Minimum cycle
945
810
720
mA
18
18
18
mA
9
9
9
mA
945
810
720
mA
810
720
830
mA
After 1 memory cycle,
RAS and eAS high,
VIH .. 2.4 V (lTL)
After 1 memory cycle,
J!iA! and eAS high,
VIH .. VCC - 0.2 V (CMOS)
Minimum cycle,
VCC=5.5V,
Average refresh current
RAS cycling,
ICC3 (RAS only or CBR)
eAS high (RAS only), '
(see Note 3)
RAS low after eAS low (CBR)
tpc .. minimum,
Average page current
VCC .. 5.5V,
ICC4 (see Note 4)
RASlow,
eAScycling
NOTES: 3. Measured with a maximum of one eddress change while RAS .. VIL
4. Measured with a maximum of one eddress change while CAS =VIH
ICC2 Standby current
8-18
-!i11ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. l1!XAS rnSI-I443
TM4100EAD9
4194304 BY 9·BIT
DYNAMIC RAM MODULE
SMMS419C-NOVEMBER 1991-REVISEOJUNE 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f 1 MHz (see Note 5)
=
MIN
PARAMETER
CleA)
Input capacitance, AO-A10
otCOl
Input capacitance, data Input (pin 09)
oteRCl
CI(W)
Co(OQl
Output capacitance, 001-08
Co
Output capacitance, Q9
MAX
UNIT
45
pF
5
pF
Input capacitance, CAS and RAS
83
pF
Input capacitance, W
83
12
pF
7
pF
NOTE 5: VCC
pF
=5 V '" 0.5 V and the bias on pins under test IS 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature
'4100EAD9-60 '4100EAD8-70 '4100EAD9-80
MIN
MAX
MIN
MAX
MIN
MAX
PARAMETER
lRAc
Access time from column address
Access time from CAS low
Access time from column pracharge
Access time from RAS low
teLZ
CAS to output In low-Impedance
tAA
teAC
tePA
30
35
40
ns
15
18
20
ns
ns
35
40
45
80
70
80
ns
ns
20
ns
0
toFF Output disable time after CAS high (see Note 6)
NOTE 6: toFF Is specified when the output IS no longer dnven.
0
UNIT
0
15
-!!11ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
0
0
18
0
6-19
TM4100EAD9
4194304 BY 9-BIT
DYNAMIC RAM MODULE
SMMS418C- NOVEMBER 1991 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free..lr
temperature
'4100EAD8-tIQ
MIN
110
MAX
'4100EAD8-70
MIN
130
'4100EAD8-80
MIN
150
50
ns
80 100000
80
10000
20
10000
10
80
ns
ns
ne
ns
ne
tRC
tpc
Cycle time, random read or write (see Note 7)
Cycle time, page-mode read or write (see Note 8)
40
tRASP
tRAS
Pulse duration, page mode ~ low (see Note 9)
teAS
tep
Pulse duration, nonpage mode, ~ low (see Note 9)
Pulse duration, CAS low (see Note 10)
Pulse duration, CAS high
80 100000
80 10000
15 10000
10
45
70 100000
70 10000
18 10000
10
IRp
Pul8e duration, ~ high (precharge)
40
50
twP
Pulse duration, write
15
15
tASe
Setup time, column add..... before CAS low
0
0
15
0
tASR
10s
Setup time, row add,..s before ~ low
Setup time, data (see Note 11)
0
0
0
0
0
0
IRCs
Setup time, read before CAS low
Setup time, iN low before CAS hrgh
Setup time, iN low before RAS' high
0
18
18
0
tcwL
0
15
15
20
Setup time, W low before CAS low (earty-wrlte operation only)
Setup time, W high (CBR refresh only)
Setup time, iN low (test mode only)
0
10
10
0
10
10
0
10
10
Hold time, column address after CAS low
Hold time, data after RAS' low (see Note 12)
10
50
15
55
15
80
tDH
tAR
tRAH
Hold time, data (see Note 10)
Hold time, column add..... after RAS low (see Note .12)
10
50
15
55
15
Hold time, row address after ~ low
10
10
tRCH
tRRH
Hold time, read after CAS high (see Note 13)
0
0
15
0
tRWL
twcs
IWsR
twTs
teAH
tDHR
UNIT
MAX
20
60
10
0
0
15
80
10
10
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ne
twCH
!wCR
twHR
Hold time, read after ~ high (see Note 13)
Hold time, write after CAS low (early-wrlte operation only)
Hold time, write after RAS low (see Note 12)
Hold time, iN high (CBR refresh only)
50
10
0
15
55
10
twTH
Hold time, W low (test mode only)
10
10
teHR
teRP
Delay time, RAS' low to CAS high (CBR refresh only)
15
0
15
0
70
0
80
ns
ns
ns
ns
ns
ns
ns
10
10
ns
teSH
Deley time, CAS high to ~ low
Delay time, RAS low to CAS high
60
Delay time, CAS low to ~ low (CBR refresh only)
10
teSR
NOTES: 7. All cycle times assume tr = 5 ns.
8. To assure tpc min, tASC should be ill: 5 ns.
9. In a read-write cycle, tRWD and tRWL must be observed.
10. In a read-write cycle, tcwQ..!!!.d fQwL must be observed.
11. Referenced to the later of CAS or W In write operations
12. The minimum value Is measured when tRCD Is set to tRCD min as a reference.
13. Either IRRH or tRCH must be satisfied for a read liVcle.
~1ExAs
INSTRUMENTS
8-20
POST OFFICE ~ 1443 • HOUSTON. TEXAS 77251-1443
20
TM4100EAD9
41943048Y9-81T
DYNAMIC RAM MODULE
SMMS419C-NOVEMBER 1991-REVISEDJUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (continued)
'4100EAD9-80
'4100EAD9-80
'4100EAD9-70
MIN
MAX
MIN
MAX
15
30
15
35
MIN
MAX
15
40
UNIT
tRAI)
Delay time, RAS low to column address (see Note 14)
tRAL
Delay time, column address to RAS high
30
35
40
teAL
Delay time, column address to CAS high
30
35
40
tRCD
Delay time, RAS low to CAS low (see Note 14)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
n8
ns
ns
45
20
52
20
trAA
Access time from address (test mode)
35
40
45
trCPA
Access time from column precharge (test mode)
40
45
50
trRAC
tREF
Access time from RAS (test mode)
65
Refresh time interval
Transition time
tr
NOTE 14: The maximum value is specified only to assure access time.
2
50
16
2
ns
ns
80
50
2
ns
n8
65
75
16
n8
16
me
50
n8
device symbolization
I
o
TM4100EAD9
~
DDDDDDDDDDDD~;DD:;DDDDDDDDDDD (
YY .. Year Code
MM • Month Code
T • Assembly Site Code
-SS .. Speed
NOTE: The location of symbolization may vary.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77251-1443
8-21
TM4100EAD9
4194304 8Y9-81T
DYNAMIC RAM MODULE
SMMS419C-NOVEMBER 1991-REVlSEDJUNE 1995
~1ExAs
6-22
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TeXAS 772&1-1_
TM497EU9
4194304-WORD BY 9-BIT
DYNAMIC RAM MODULE
SMMS499A- FEBRUARY 1894 - REVISED JUNE 1895
• Organization ••• 4194304 x 9
• Single S-V Power Supply (:1:10% Tolerance)
• 3O-Pln Single-in-Une Memory Module
(SIMM) for Use With Sockets
U SINGLE-IN-LINE PACKAGE
(TOP VIEW)
• Utilizes One 4-Megablt and Two 16-Megabit
Dynamic RAMs In Plastic Smail-Outline
J-Lead (SOJ) Packages
• Long Refresh Period
32 mst (2048 Cycles)
• All Inputs, Outputs, and Clocks Fully TTL
Compatible
'497EU9-60
'497EU9-70
'497EU9-60
1
CAS
OQ1
AO
A1
OQ2
A2
A3
2
3
o
4
5
6
7
8
Vss 9
OQ3 10
A4 11
AS 12
• 3-State Outputs
• Performance Ranges:
ACCESS ACCESS
TIME
TIME
(tRAc)
I(M)
(MAX)
(MAX)
60 ns
30 ns
70 ns
35 ns
80 ns
40 ns
Vee
DQ4 13
AS
A7
OQ5
AS
14
15
16
17
AS 18
A10 19
ACCESS READ OR
'TIME
WRITE
(tcAc)
CYCLE
(MAX)
(MIN)
15 ns
110 ns
18 ns
130 ns
20 ns
150 ns
oa6 20
'iN
21
Vss 22
• Common CAS Control for Eight Common
Data-In and Data-Out Unes
OQ7 23
Ne 24
008 25
as 26
RAS 27
CAS9 28
• Separate CAS Control for One Separate
Pair of Data-In and Data-Out Unes
• Low Power Dissipation
• Operating Free-Air Temperature Range
O·Cto 70·C
0929
Vee 30
o
• Enhanced Page Mode Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
description
The TM497EU9 is a 4M-byte dynamic
random-access memory (RAM) organized as
4194304 x 9 bits [bit nine (09, 09) ~ generally
used for parity and is controlled by AS9] in a
3D-pin leadless single-in-Iine memory module
(SIMM). The ,_ SIMM is composed of two
TMS4174000J, 4194304 x 4-bit dynamic RAMs,
each in a 24/26-lead plastic small-outline J-Iead
(SOJ) package, and one TMS441 OOOJ, 4194304
x 1-bit dynamic RAM in a 2O/26-lead plastic SOJ
package, mounted on a substrate with decoupling
capacitors.
PIN NOMENCLATURE
AO-A10
CAS,CAS9
oo1-0Q8
09
NC
Q9
RAS
VCC
VSS
'iN
Address Inputs
Column-Address Strobe
Data In/Oats Out
oats In
No Connection
Oats Out
Row-Address Strobe
s-V Supply
Ground
Write Enable
The TM497EU9 is available in the U single-sided, lead less module for use with sockets and is characterized
for operation from O·C to 70·C.
tAO-AS address lines must be refreshed every 16 ms.
~1ExAs
Copyright C 1995. Texas Instrumenta Incorporated
INSTRUMENTSPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
6-23
TM497EU9
.
4194304-WORDBY 9-BIT
DYNAMIC RAM MODULE
SMMS489A- FEBRUARY 1994 - REVISED JUNE 1995
operation
The TM497EU9 operates as two TMS417400DJs and one TMS441 OODJ connected as shown in the functional
block diagram (refer to the TMS417400 and TMS441 00 data sheets for details of their operation). The common
I/O feature of the TM497EU9 dictates the use of early write cycles to prevent contention on 0 and Q.
refresh
The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with
RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power. In addition,
the ten least Significant row addresses (AO-A9) must be refreshed every 16 ms as required by the TMS441 00.
power up
To achieve proper operation, an initial pause of 200 JA.S followed by a minimum of eight initialization cycles is
required after full Vee level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CBR) cycle.
singie-in-llne memory module and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and solder plate over copper
functional block diagram
11
AO-A10
JiA§
CAS
Vi
~
4MlC4
AO-A10 D01
RAS
D02
_.....
D03
... CAS
Vi
DQ4
...
..ll-...
...
~
8
--W
~
--1.L
DQ2
D03
DQ4
OE
4MlC4
AO-A10 D01 ~
RAS
D02 ~
CAS
D03 ~
Vi
D04 ~
D05
D08
DQ7
D08
OE
1
..!L
,.,
4MlC.1
AO-A10
RAS
CAS
D~
os
o~ 09
Vi
~TEXAS
6-24
D01
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TM497EU9
4194304-WORD BY9-BIT
DYNAMIC RAM MODULE
SMMS499A- FEBRUARY 1994 - REVISED JUNE 1985
absolute maximum ratings over operatlr1g free..lr temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................... -1 V to 7 V
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Short-circuit output current ..............•.......•...•...........•......•..•••..•.•••.•••.• 50 mA
Power dissipation .••••••••...••..•.•..•.......•..............••...••.••••.••.•......•••.•.• 3 W
Operating free-air temperature range, TA .•.........................................••. O°C to 70°C
Storage temperature range, Tstg .................................................. - 55°C to 150°C
t Stresses beyond those listed under "absolute maxlmum ratings" may cause permanent damage to the device. These are stress ratings only, and
. functlonaJ operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" Is not
Implied. Exposure to absolute-maxlmum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
Vcc
Supply voltage
4.5
5
VIH
High-level Input voltage
2.4
5.5
B.5
UNIT
V
V
-1
0.8
Low-Ievellnput voltage (see Note 2)
V
VIL
·C
Operating free-air temperature
70
0
TA
.. . ..
NOTE 2: .The algebraic convention, where the more negatIVe Oess positIVe) limit IS desIgnated as mlnlmum,ls used for Iogic-voltage levels only•
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
ICC1
Read- or wrlte-cycle current
(see Note 3)
1CC2 Standby current
Average refresh current
ICC3 (m-only or CBR)
(see Note 3)
Average page current
1CC4 (see Note 4)
TEST CONDITIONS
'497EU9-60
MIN
MAX
2.4
IOH=-5mA
IOL=4.2mA
'497EU9-70
MIN
MAX
2.4
'497EU9-80
MIN
MAX
UNIT
V
2.4
0.4
0.4
0.4
V
:10
:10
:10
IIA
VO=OVtoVCC.
:10
:10
:10
IIA
Minimum cycle
325
290
260
rnA
VIH = 2.4 V (TIL),
After 1 memory cycle,
RAS and CAS high
6
6
6
VIH =VCC - 0.2 V (CMOS),
After 1 memory cycle.
RAS and ~ high
3
3
3
325
290
260
rnA
210
1S0
150
rnA
VI- OVto 6.5 V,
VCC-5V,
All other pins = 0 V to VCC
~=5.5V,
CAS high
VCC=5.5V,
Minimum cycle,
VCC .. 5•5V,
RAScycllng,
~ high (RAS-only):
RAS low after CAS low (CBR)
VCC .. 5•5V,
tpC-MIN,
RASIow,
CAS cycling
rnA
NOTES: 3. Measured with a maximum of one address change while RAS .. VIL
4. Measured with a maxlmum of one address change while CAS .. VIH
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
6-25
TM497EU9
4194304-WORD BY 9·BIT
DYNAMIC RAM MODULE
SMMS499A- FEBRUARY 1994- REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating fre...lr temperature,
= 1 MHz (see Note 5)
f
PARAMETER
Ci(A)
Input capacltance, AO-A10
CI{DI
Input capacitance, data Input (09)
CIIRI
Input capacitance, strobe Input (AAS)
CI(C)
Input ~nce, strobe Inputs
CIIWl
Co/DQ1
Output cepacltance (OQ1-0Q8)
MAX
MIN
15
I CAS
pF
21
pF
7
Input capacitance, W
21
7
7
Output cepacltance (Q9)
CoCCI
NOTE 5: Vee. 5 V :t 0.5 V, and the bias on pin under test Is 0 V.
pF
5
14
1CAS§
UNIT
pF
pF
pF
pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'497EU9-80
PARAMETER
'497EU9-80
Access time from column address
30
teAC
Access time from CAS low
15
18
2D
n.
tePA
tRAC
Access time from column precharge
Access time from RAS low
35
60
40
45
60
ns
70
teLZ
CAS to output In low-Impedance state
0
toH
Output disable time, start of CAS high
3
2D
ns
0
~1ExAs
6-26
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
MIN
0
0
3
15
0
MIN
MAX
40
UNIT
1M
Output disable time after CAS high (see Note 6)
toFF
NOTE 8: toFF Is specified when the output Is no longer driven.
MAX
'497EU9-70
MAX
35
MIN
3
18
0
os
os
os
os
TM497EU9
4194304-WORD BY9-BIT
DYNAMIC RAM MODULE
SMMS499A- FEBRUARY 1994 - REVISED JUNE 1886
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature
PARAMETER
'497EU9-60
'497EU9-70
MIN
MIN
MAX
MAX
'497EU9-80
MIN
MAX
UNIT
os
os
110
130
150
Cycle time, page mode raac:I or write (see Notas 7 and 8)
40
45
50
lRASp
Pulse duration, page mode, RAS low
100000
60
100000
lRAS
60 100000
60 10000
70
Pulse duration, nonpage mode, RAS low
70
10000
80
10000
na
teAS
tep
Pulse duration, eAS low
15
18
10000
20
10000
nl
Pulse duration, eAS high
10
10
10
lAp
Pulse duration, RAS high (precharge)
40
50
80
nl
twP
Pulse duration, W low
10
10
10
na
IASc
1ASR
tDS
Setup time, column address before CAS low
0
0
0
na
Setup time, row address before RAS low
0
0
os
Setup time, data before CAS low
0
0
0
0
tRCS
Setup time, W high before eAS low
0
0
0
na
na
lAc
tpC
Cycle time, random read or write (saa Nota 7)
10000
ns
nl
na
tcwL
Setup time, W low before CAS high
15
18
20
tRWl
Setup time, W low before RAS high
15
18
20
na
twos
Setup time, W low before CAS low
0
0
0
nl
twRP
Setup time, W high before RAS low (CBR refresh only)
10
10
10
nl
teAH
tDH
tRAH
Hold time, column address after eAS low
10
15
15
nl
Hold time, data after CAS low
10
15
15
nl
Hold time, row address after RAS low
10
10
10
nl
tRCH
Hold time, Vi high after eAS high (see Note 9)
0
0
nl
tRRH
Hold time, W high after RAS high (see Note 9)
0
0
0
0
twoH
Hold time, W low after CAS low
10
15
15
nl
twRH
tRHCP
Hold time, W high after RAS low (CBR refresh only)
Hold time, RAS high from eAS pracharga
10
10
35
40
10
45
nl
nl
teHR
Delay time, RAS low to eAS high (CBR refresh only)
10
10
10
na
teRP
Delay time, CAS high to RAS low
5
5
5
na
teSH
Delay time, RAS low to CAS high
60
70
80
nl
teSR
tRAO
Delay time, CAS low to RAS low (CBR refresh only)
Delay time, RAS low to column address (see Note 10)
15
lfw.
Delay time, column address to RAS high
30
35
40
teAL
Delay time, column address to CAS high
30
35
40
lACD
tRPC
Delay time, RAS low to CAS low (sea Note 10)
20
Delay time, RAS high to CAS low
0
0
0
tRSH
Delay time, CAS low to RAS high
15
18
20
tREF
Refresh time interval
5
5
30
45
15
20
32
Transition time
tr
NOTES. 7. All cycle tlmel essume tr .. 5 na.
8. To assure tpc min, IASc should be :. tep.
9. Either tRRH or tRCH must be satisfied for a read cycle.
10. The maximum value is spaclflad only to assure access time.
3
30
nl
5
35
52
15
20
32
3
nl
30
3
40
nl
nl
ns
60
nl
nl
nl
32
ms
30
ns
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-27
TM497EU9
'4194~WORD
BY 9-BIT
DYNAMIC RAM MODULE
SMMS498A- FEBRUARY 1.994-REVISED JUNE 1995
device symbolization
1 DDDDDDDDDDDDDDDDDDonOOOOooooon
~
o
-sa . VYMMT
YV • VearCod.
MM • Month Cod.
T • AaHmbly Site Cod.
Speed
.
-sa •
NOTE: The location of the part number may vary.
-!llExAs
INSTRUMENTS .
8-28
POST OFFICE BOX 1443 • HOUSTON. leXAS 77251-1443
0'
TM124BBK32, TM124BBK32S 1048576 BY 32·BIT
TM248CBK32, TM248CBK32S 2097152 BY 32·BIT
DYNAMIC RAM MODULE
• Performance Ranges:
• Organization
TM124BBK32 ••• 1 048 576 x 32
TM248CBK32 ••• 2 097 152 x 32
• Single
Power Supply (:tiD % Tolerance)
• 72-pln Single In-Une Memory Module
(SIMM) for Use With Sockets
s-v
ACCESS
nME
ACCESS
nME
tRAC
tcAC
READ
OR
WRITE
CYCLE
TM124BBK32-60
TM124BBK32-70
TM124BBK32-60
TM248CBK32-60
TM248CBK32-70
TM248CBK32-60
• TM124BBK32-Utlllzes Eight 4-Megablt
DRAMs In Plastic Smail-Outline J-Lead
(SOJ) Packages
• TM248CBK32-Utlllzes Sixteen 4-Megablt
DRAMs In Plastic Smail-Outline J-Lead
(SOJ) Packages
• Distributed Refresh Period
16 ms (1024 Cycles)
• All Inputs, Outputs, Clocka Fully TTL
Compatible
(MAX)
(MAX)
(MIN)
60ns
70ns
60ns
60ns
70ns
60 ns
15 ns
18ns
20ns
15ns
18 ns
20 ns
110ns
130ns
150ns
110 ns
130 ns
150 ns
• Low Power Dissipation
• Operating Free-Air-Temperature Range
O°C to 70°C
• Gold-Tabbed VerSions Avallable: t
- TM124BBK32
- TM248CBK32
• Tin-Lead (Solder) Tabbed Versions
Available:
- TM124BBK32S
- TM248CBK32S
• 3-State Output
• Common cAs Control for Eight Common
Data-In and Data-Out Lines, In Four Blocks
• Presence Detect
description
TM124BBK32
The TM124BBK32 is a dynamic random-access memory (DRAM) organized as four times 1048576 x 8 in a
72-pln leadless single in-line memory module (SIMM). The SIMM is composed of eight TMS44400, 1048576
x 4-bit DRAMs, each in 20/26-lead plastic SOJ packages, mounted on a substrate together with decoupling
capacitors. Each TMS44400 is described in the TMS44400 data sheet.
The TM124BBK32 is available In the single-sided BK leadless module for use with sockets.
The TM124BBK32 features RAS access times of 60 (lS, 70 ns and 80 ns. This device is rated for operation from
0°Ct070°C
TM248CBK32
The TM248CBK32 is a dynamic random-access memory organized as four tilt;les 2097152 x 8 in a 72-pin
leadless SIMM. The SIMM is composed of sixteen TMS44400, 1048576 x 4-bit dynamiC RAMs, each in
20/26-lead plastic SOJ packages SOJs, mounted on a substrate together with decoupling capacitors. Each
TMS44400 is described in the TMS44400 data sheet.
The TM248CBK32 is available in the double-sided BK leadless module for use with sockets.
The TM248CBK32 features RAS access times of 60 ns, 70 ns and 80 ns. This device is rated for operation from
0°Ct070°C
operation
TM124BBK32
The TM124BBK32 operates as eight TMS44400DJs connected as shown in the functional block diagram. Refer
to the TMS44400 data sheet for details of operation. The common I/O feature of the TM124BBK32 dictates the
use of early write cycles to prevent contention on D and Q.
_on
t Part numbers In this data sheet are for the gold-tabbed version; the Information applies to both gold-tabbed and solder-tabbed versions.
___ ......cIII_,., ......... oI,..... .............,
PIIOOUCTION DATA
II ournnI • 0I1I\IIIIIcIIIoft _
.. ,
,; "
~'lExAs'
II
Copy~ght 11:11995, TeX88lnstrumenIB Incorporated
=~ProM1Ian....-..._not-.u,lnaIudo
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lEXAS 77251-1443
8-29
TM124BBK32, TM124BBK32S 1048576 BY 32..BIT
TM248CBK32, TM248CBK32S 2097152 BY 32..BIT
DYNAMIC RAM MODULE
SMMS1320-JANUARY 1991 - REVISED JUNE 1995
TM248CBK32
The TM248CBK32 operates as sixteen TMS44400DJs connected as shown In the functional block diagram.
Refer to the TMS44400 data sheet for details of operation. The common I/O feature of the TM248CBK32
dictates the use of early write cycles to prevent contention on D and Q.
refresh
Refresh period Is extended to 16 ms and, during this period, each of the 1024 rows must be strobed with RAS
In order to retain data. AO-MJ address lines must be refreshed every 16 ms as required by the TMS44400 DRAM.
~ can remain high during the refresh sequence to conserve power.
Single In-line memory module and components
PC substrate: 1,27 :t 0,1 mm (0;05 inch) nominal thickness; 0.005 Inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124BBK32 AND TM248CBK32: Nickel plate and gold plate over copper.
Contact area for TM124BBK32S AND TM248CBK32S: Nickel plate and tin-lead over copper.
-!111ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, l1!XAS 77251-1443
TM124BBK32, TM124BBK32S 1048576 BY 32·BIT
TM248CBK32, TM248CBK32S 2097152 BY 32·BIT
DYNAMIC RAM MODULE
SMMS1320-~UAFrf
1881-REVlSEDJUNE 1885
BK SINGLE IN-UNE MEMORY MODULE
TM124BBK32T
TM248CBK32T
(TOP VIEW)
(SIDE VIEW)
(SIDE VIEW)
e
~
D018
DOl
0017
DQ2
D018
DQ8
0018
V28
NJ
Al
A2
A2
A4
AS
All
NO
DQ4
DQ20
DOS
DQ21
DQ8
DQ22
DQ7
DQ28
A7
NO
Vee
All
D
D
D
D
d
NO
NO
NO
~
I
RASl
~
W
NC
DQ8
DQ24
DQ9
IlQ2Ii
DOlO
IlQ2Ii
DOll
DQ27
D012
DQ28
Vee
DQ28
D018
DQ80
D014
DQ81
D015
NO
POl
POI
POS
PD4
NO
Vss
PIN NOMENCLATURE
Address Inputs
Column-Address Strobe
Data InJData Out
AD-A9
D
CASO-CAS3
DQO-OQ31
D
NO
No Connection
PD1-PD4
Presence Detects
RAS0-RAS3
Row-Address Strobe
VSS
Ground
W
Write Enable
Vee
D
D
e
S-VSupply
PRESENCE DETECT
PD1
(67)
PD2
PD3
(69)
PD4
(66)
8On8
Vss
Vss
NO
Vss
70n8
Vss
Vss
VSS
8On8
Vss
Vss
NO
NO
8On8
NO
NO
NO
NO
NO
NO
NO
NO
SIGNAL
(PIN)
TM124BBK32
TM248CBK32
70n8
6On8
VSS
NO
(70)
Vss
NO
NO
t The packages shown here are not drawn to scale.
~1ExAs
INSTRUMENTS
POST OFFICE sox 1448 • HOUSlON. TEXAS 77251-1448
6-31
~
I
i~i!i!
functional block diagram (for TM124BBK32 and TM248CBK32, Side 1)
I\)
!!lZ~""
~l>&~
I
AO-.- - 10
RASO
CASO
!!!i:i:S:
.,.
CAS11Mx4
~ Vi
-;;: CAS
OE
DQ1OQ4
~
0 _. . .
~~...~~.g~
2f
~tI1
~~
i.!.
t
~DQO-
-!-
DQ3
1Mx4
~
....
J.
OE
001- . . . DQ4DQ7
..I
-=
...... CAS
OE
001- . . . 0012
~ ViRAJ
RAS
OE
OQ1DQ4 "'DQ16-
*
DQ4
0015
-
-=
.......
DQ4
iii
~
a;
CAS
...... OE
DQ1DQ4
!K
DQ24DQ27
.J:.
OQ20- DQ23
OE
DQ1DQ4
~!
.... c,n
~ot
~~
mm
Vi
~ CAS
......
~N
0.0
~ ....
~~
1Mx4
CAS
OE
DQ1- . . .
E ~.~
AO-AS
~ RAJ
~Vi
J.
2Ilnmm
1Mx4
~ 1Mx4
AO-AS
RAJ
RAS
:Dcft~
.!l!c:
~
c;;.
m
AO-AS
DQ19
~Vi
CAS
DQ4
OE
DQ1- . . .
OQ4
006.
DQ11
l.....:b AO-AS
~ Vi
1Mx4
AO-AS
Vi
~ CAS
~ 1Mx4
~ AO-AS
RAS
....
RAS
Vi
~ CAS
...
-~
~.
~
1Mx4
AO-AS
IO~""
CAS3-
CAS2-
~
AO-AS
RAS
~
~~~~
_i::":"
RAS2
-
i:nm
~nmm
=i=i
DQ28DQ31
functional block diagram (for TM248CBK32, Side 2)
AO_--10
RAS3
RAS
CAS1-
CASO1 1Mx4
AO-AS
~
~
~~
;
CAS
CAS
~
1~4r~~g~
~m
~ RAS
~
...
OE
D01004
D03
~ RAS
~
OE
~
-b
RAS
~
... Vi
....
.
001- .... 004_
0Q4
007
-:!:-
OE
CAS
.... OE
OQ1OQ4 .... OQ160019
-'"
-b
001- .... D012- ':"
004
0015
~
"-
001- .... 0020004
DQ23
D01- ~
0Q4
0024DQ27
i!:
~ Vi
..... CAS
OE
OE
-:!:-
1Mx4
AO-AS
1Mx4
CAS
Vi
~ RAS
~ AO-AS
Vi
CAS
OE
1Mx4
~ AO-AS
RAS
~... ViCAS
~ RAS
Vi
OQ1004 ~DQ80011
!4+-ooo- -:!:-
1Mx4
AO-AS
c:::;:...
1Mx4
AO-AS
1Mx4
AO-AS
~ ViRAS
~
...
CAS3-
CAS2-
-:!:-.
1Mx4
AO-AS
-f-f
s:s:
RAS
Vi
I\) ....
~~
CAS
OE
001- ..
0Q4
D0280031
om
mm
I
~~
j\)j\)
-f-f
1.
t
s:s:
(1J
1\) ....
.::
" " I\)
.::
~
~
OCt ""
om
mm
I~~~
~z I\) I\)
C:» (I) (I)
~S:I\)
....
io~2
_~ ...... a;
I
:II
.... 01
01 ......
~S:I\)
en
Ms:2i!
2i!
<-oww
...t
!fa I\) I\)
me:'
•
-r mm
~rn=t =t
TM124BBK32, TM124BBK32S 1048576 BY 32·BIT
TM248CBK32, TM248CBK32S 2097152·BY32·BIT
DYNAMIC RAM MODULE
SMMS132D - JANUARY 1991 .;,. REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ..••..•....•...•..•..•.•.••••..•.•.••..••.....••• - 1 V to 7 V
Voltage range on Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . -1 V to 7 V
Short-circuit output current .•..••....•..•...••..••..••.••...••..................•••...•••.•• 50 rnA
Power dissipation ••••••••••.•••...•......... ;.............................................. 8 W
Operating free-air temperature range, TA ............................................... O·C to 70·C
Storage temperature range, Tstg .•.•••.••.•••. ~ . • . • • • • . • • • • . • . • . . • . . • . . . . . . . . . . • .• - 55·C to 125·C
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the d~ice. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' Is not
Implied. Exposure to absolute-maxlmum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
VCC
VIH
Supply voltage
High-level Input voltage
UNIT
MIN
NOM
MAX
4.5
5
5.5
V
6.5
V
2.4
Low-level Input voltage (see Note 2)
-1
0.8
V
VIL
Operating free-air temperature
70
0
TA
NOTE 2: The algebraic convention, where the more negative (less positive) hmlt Is deSignated as mlnimum,ls used for logic-voltage levels only.
·c
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDmONS
'124BBK32-60 '124BBK32-70
MIN
MAX
MAX
MIN
MAX
10H--SmA
Low-level output voltage
10L = 4.2 mA
0.4
0.4
0.4
V
II
Input current ~eakage)
VI = OVt06.S V,
VCC=5V,
All other pins = 0 V to VCC
:1:10
:1:10
:1:10
lolA
10
Output current (leakage)
:1:10
:1:10
:1:10
lolA
ICC1
Read- or write-cycle current
(see Note 3)
640
720
640
mA
16
16
16
6
8
8
840
720
640
mA
720
640
S60
mA
Vo =OVtoVCC,
Minimum cycle
Vcc = 5.5 V,
2.4
UNIT
High-level output voltage
AS high
2.4
'124BBK32-80
VOH
VOL
~=5.SV,
2.4
MIN
V
After 1 memory cycle,
RAS and CAS high,
ICC2 Standby current
VIH=2.4 V (TTL)
rnA
After 1 memory cycle,
RAS and CAS high,
VIH = VCC-0.2V (CMOS)
Average refresh current
ICC3 (RAS only or CBR)
(see Note 3)
Average page current
1CC4 (see Note 4)
Minimum cycle,
YQQ-5.5V,
RAScycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
~
.. S.SV,
RASlow,
!fQ: minimum,
CAS cycling
NOTES: 3. Measured with a m8XImum of one address change while RAS = VIL
4. Measured with a maximum of one address change while CAS = VIH
-!I11ExAs
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON. TEXAS n251-1443
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT
TM248CBK32, TM248CBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULE
SMMS132D - JANUARY 1991 - REVISED JUNE 1895
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
'248CBK32-60 '248CBK32-70
MIN
MAX
MIN
MAX
'248CBK32-80
MIN
MAX
UNIT
VOH
High-level output voltage
IOH=-5mA
VOL
low-level output voltage
10L= 4.2 mA
0.4
0.4
0.4
V
II
Input current (leakage)
VCC=5V,
VI " 0 V to 6.5 V,
All other pins .. 0 V to VCC
:0:20
:0:20
:0:20
)IA
10
Output current Oeakage}
VCC = 5.5 V,
CAS high
VO=OVtoVCC,
:020
:0:20
:0:20
)IA
ICC1
Read- or write-cycle current
(see Note 3)
VCC=5.5V,
Minimum cycle
mA
,
ICC2 Standby current
2.4
2.4
2.4
V
856
736
656
After 1 memory cycle,
RAS and CAS high,
VIH=2.4 V (TTL)
32
32
32
After 1 memory cycle,
RAS and CAS high,
VIH = VCC - 0.2 V (CMOS)
16
16
16
mA
Average refresh current
ICes (RAS only or CBR)
(see Note3)
Minimum cycle,
VCC=5.5V,
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
1680
1440
1280
rnA
Average page current
ICC4 (see Note 4)
VCC = 5.5 V,
RASlow,
tpc = minimum,
CAS cycling
736
656
576
mA
NOTES: 3. Measured With a maximum of one address change while RAS • VIL
4. Measured with a maximum of one address change while CAS =VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature
f = 1 MHz (see Note 5)
'124BBK32
'248CBK32
MIN
MIN
MAX
MAX
UNIT
CilA)
Input capacitance, address inputs
40
80
pF
CIIRI
Input capecltance, RAS
28
28
pF
CI(C)
Input capacitance, CA§
14
28
pF
CI(W)
Input capecltance, W
58
112
pF
Co(OQ)
Output capecitance on OQ pins
7
14
pF
NOTE 5: VCC = 5 V :t 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature
'124BBK32-60
'248CBK32-60
PARAMETER
MIN
MAX
'124BBK32-70
'248CBK32-70
MIN
MAX
'124BBK32-80
'248CBK32-80
MIN
UNIT
MAX
tM
Access time from column-address
30
35
40
os
!cAe
Access time from CAS low
15
18
20
ns
!cPA
Access time from column precharge
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
!cLZ
CA§ to output In low Z
os
os
os
0
Output disable time after CAS high (see Note 6)
toFF
..
NOTE 8: toFF IS specified when the output Is no longer dnven .
0
0
15
0
0
18
0
20
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS n251-1443
8-35
TM124BBK32, TM124BBK32S 1048576 BY 32·BIT
TM248CBK32, TM248CBK32S 2097152 BY 32·BIT
DYNAMIC RAM MODULE
SMMS132D- JANUARY 1981 - REVISED JUNE 1895
timing requirements over recommended range of supply voltage and operating fre...lr
temperature
'124BBK32-80
'248CBK32-60
MIN
110
MAX
'124BBK32·70
'248CBK32·70
MIN
130
MAX
tRC
tpc
Cycle time, random read or write (see Note 7)
Cycle time, page-mode read or write (see Note 8)
40
45
lep
Pulse duretion, CAS high
teAS
tRP
Pulse duretion, CAS low
10
15
10
18 10000
50
70 100000
70 10000
15
0
0
0
0
0
10
18
tRASP
tRAS
twp
tASC
Pulse duretion, RAS high (precharge)
Pulse duration, page mode, RAS low
Pulse duretion, nonpage mode, RAS low
Pulse duretion, write
Setup time, column address before CAS low
los
Setup time, row address before RAS low
Setup time, data
tRCS
Setup time, reed before CAS low
twcs
twSR
tASR
tcwL
Setup time, W low before CAS low
Setup time, W high (CBR refresh only)
Setup time, W low before CAS high
tRWL
·Setup time, W low before RAS high
twrs
Setup time, W low (test mode only)
leAH
lRAH
tAR
Hold time, column address after CAS low
Hold time, row address after ~ low
10000
40
80 100000
80 10000
15
0
0
0
0
0
10
15
15
10
'124BBK32-80
'248CBK32-80
MIN
150
50
10
UNIT
MAX
ns
ns
ns
20
10000
80
80 100000
80 10000
15
0
0
0
ns
ns
0
0
10
ns
ns
ns
ns
ns
ns
ns
20
ns
ns
ns
20
ns
ns
0
0
15
10
15
10
80
80
15
0
0
15
18
10
15
10
55
55
15
ns
ns
tRCH
tRRH
Hold time, reed after CAS high (see Note 10)
Hold time, .read after RAS high (see Note 10)
twCH
Hold time, write after CAS low
10
10
50
50
10
0
0
15
twHR
Hold time, W high (CBR refresh only)
10
10
10
ns
twCR
Hold time, write after RAS low
teSH
Hold time, VI low (test mode only)
Delay time, RAS low to CAS high
teRP
tRCO
tCHR
Delay time, CAS high to RAS low
Delay time, RAS low to CAS low (see Note 11)
Delay time, RAS low to CAS high (CBR refresh only)
55
10
70
0
60
10
80
0
ns
twrH
50
10
teSR
tRAO
Delay time, CAS low to FiAS low (CBR refresh only)
Delay time, RAS low to column address (see Note 11)
tOHR
tOH
Hold time, column address after RAS low (see Note 9)
Hold time, data after RAS low (see Note 9)
Hold time, data
60
0
20
15
10
15
45
30
Delay time, column address to RAS high
30
tRAL
NOTES: 7. All cycle times assume IT. 5 ns.
8. To assure lpLmln,lASc should be 11 5 ns.
9. The minimum value Is measured when IRco Is set to IRco min as a reference.
10. Either tRRH or tRCH must be satisfied for a read cycle.
11. Maximum value specified only to assure access time.
~TEXAS
INSTRUMENTS
6·36
POST OFFICE BoX 1443 • HOUSTON. TEXAS 77251-1443
20
15
10
15
35
52
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
60
20
35
10
15
40
40
ns
ns
ns
ns
ns
TM124BBK32, TM124BBK32S 1048576 BY 32·BIT
TM248CBK32, TM248CBK32S 2097152 BY 32·BIT
DYNAMIC RAM MODULE
SMMS132D - JANUARY 1981 - REVISED JUNE 1985
timing requirements over recommended range of supply voltage and operating free-air
temperature (concluded)
'124BBK32-80 '124BBK32-70 '124BBK32-80
'248CBK32-80 '248CBK32-70 '248CBK32-80
MIN
teAL
Delay time, column address to CAS high
tRPC
Delay time, RAS high to CAS low (CBR refresh only)
tRSH
trAA
trRAC
trCPA
tREF
tr
MAX
MIN
MAX
MIN
UNIT
MAX
ns
30
35
40
0
0
0
ns
Delay time. CAS low to RAS high
15
18
20
ns
Acca88 time from address (test mode)
Acca88 time from RAS (test mode)
Acoa88 time from column precharge (test mode)
35
40
45
ns
65
75
65
ns
45
40
Refresh time IntlllVBl
Transition time
2
50
2
ns
50
16
16
50
2
18
ms
50
ns
device symbolization {TM124BBK32 Illustrated)
oDDDD DDDDo
TM124BBK36B
-SS
VYMMT
VY .. Year Code
MM = Month Code
T
Assembly Site Code
=
-SS
=
Speed Code
NOTE: location of symbolization may vary.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 14<13 • HOUSToN. TEXAS 77261-14<13
8-37
TM124BBK32, TM124BBK32S 1048576 BY 32·BIT
TM248CBK32, TM248CBK32S 2097152 BY 32·BIT
DYNAMIC RAM MODULE
SMMS132D-JANUARY 1991- REVISED JUNE 1995
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TM124BBK32F, TM124BBK32U 1048576 BY 32·BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32·BIT DYNAMIC RAM MODULE
• Organization
TM124BBK32F ••• 1 048 576 x 32
TM248CBK32F ••• 2 097152 x 32
• Single Sav Power Supply (:t10% Tolerance)
• 72-Pln Single-in-Une Memory Module
(SIMM) for Use With Socket
• Presence Detect
• Performance Ranges:
ACCESS
TIME
• TM124BBK32F - Utilizes Two 16-Megablt
DRAMs In Plastic Smail-Outline J-Lead
(SOJ) Packages
• TM248CBK32F - Utilizes Four 16-Megablt
DRAMs In Plastic Smail-Outline J-Lead
(SOJ) Packages
ACCESS ACCESS READ
TIME
TIME
OR
IRAc
IAA
tcAc
WRITE
CYCLE
(MIN)
(MAX)
(MAX)
(MAX)
'124BBK32F-60
eo ns
30 ns
15 ns
110 ns
'124BBK32F-70
70 ns
35ns
18 ns
130 ns
'124BBK32F-eo
80 ns
80 ns
40 ns
30ns
20ns
150 ns
'248CBK32F-80
15 ns
110 ns
'248CBK32F-70
70 ns
35 ns
18 ns
130 ns
'248CBK32F-80
80 ns
40 ns
20 ns
150 ns
• Low Power Dissipation
• Operating Free-Air Temperature Range
O·Cto 70·C
• Long Refresh Period
16 ms (1024 Cycles)
• All Inputs, Outputs, Clocka Fully TTL
Compatible
• 3-State Output
• Common CAS Control for Eight Common
Data-In and Data-Out Lines In Four Blocks
• Enhanced Page-Mode Operation With
CA8-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
• Gold-Tabbed Versions Avallable: t
- TM124BBK32F
- TM248CBK32F
• Tin-lead (Solder) Tabbed Versions
Available:
- TM124BBK32U
- TM248CBK32U
description
TM124BBK32F
The TM124BBK32F Is a 32-megabit dynamic random-access memory (DRAM) organized as four times
1048576 x 8 in a 72-pin SIMM. The SIMM is composed of two TMS418160DZ, 1 048 576 x 16-bit DRAMs, each
In a 42-lead plastiC SOJ package mounted on a substrate with decoupllng capacitors. The TMS418160DZ Is
described in the TMS418160 data sheet. The TM124BBK32F SIMM is available in the single-sided BK-Ieadless
module for use with sockets.
TM248CBK32F
The TM248CBK32F is a 64-megabit DRAM organized as four times 2 097 152 x 8 in a 72-pin SIMM. The SIMM
is composed of four TMS418160DZ, 1 048 576 x 16-bit DRAMs, each in a 42-lead plastic SOJ package
mounted on a substrate with decoupUng capacitors. The TMS418160DZ is described in the TMS418160 data
sheet. The TM248CBK32F SIMM is available in the double-sided BK-Ieadless module for use with sockets.
operation
The TM124BBK32F operates as two TMS418160DZs connected as shown in the functional block diagram and
Table 1. The TM248CBK32F operates as four TMS418160DZs connected as shown in the functional block
diagram and Table 1. The common 1/0 feature dictates the use of early-write cycles to prevent contention on
Dand Q.
t Part numbers In this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed varslons.
PRODUC1\OH DATA ........... 10 ..I1'1III • 01 pUblI_ _
_ _ loepoclll_pIIlht ...... oITIXII_
=~~proCIIIIng_noI--a,lncIucIo
..lIs
~
Copyright C 1995. Texas Instruments Incorporated
1ExAs
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSlON, TEXAS 77251-1443
TM124BBK32F, TM124BBK32U 104$576 BY 32·BITDYNAMIC RAM MODULE
TM248CBK32F, TM24.8CBK32U 2097152 BY 32·BIT DYNAMIC RAM MODULE
SMMS849A- DECEMBER 1994- REVISED JUNE 1995
BK SINOLE·IN·UNE MEMORY MODULE
(TOP VIEW)
Vss
DQO
0018
001
0017
DQ2
0018
DQ3
0011
c:>
1
8:
c:>
c:>
c:>
c:>
c:>
c:>
VCC c:>
He c:>
NJ c:>
AI c:>
AI c:>
A3 c:>
M c:>
1.5 c:>
AI c:>
NC c:>
DQ4 c:>
DQ20 c:>
DQ6 c:>
DQ21 c:>
DQ8 c:>
DQ22 c:>
007 c:>
DQ23 c:::::>
1.7 c:>
NC c:>
Vee c:>
AI c:>
AI c:>
'RAS3 c:>
RASa c:>
NC c:>
He c:>
TM124BBK32F
TM248CBK32F
(SIDE VIEW)
(SIDE VIEW)
e
4
5
8
7
8
I
10
11
12
13
14
15
18
17
18
18
20
21
22
23
1M
25
28
U
28
28
30
31
32
33
34
36
38
c:> 37
c:> 38
c:> 38
. CASO c:> 40
CAS2 c:> 41
CAS3 c:> 42
CASI c:::::> 43
RASO c:> 44
AASI c:> 45
NC c:> 48
iN c:> 47
NC c:> 48
DQ8 c:> 48
DQ24 c:> 110
008 c:> 51
DQ25 c:::::> 52
0010 c:> 13
DQ28 c:> 54
0011 c:> 158
DQ27 c:> 158
0012 c:> 117
DQ28 c:> 158
VCC c:> 158
DQ28 c:> 80
0013 c:> 81
DQ30 c:> sa
0014 c:> 13
DQ31 c:> 54
0015 c:> 85
NC c:> 85
POI c:> 117
PD2 c:> 88
PD3 c:> 88
Po. c:> 70
NC c:> 71
Vss c:> 72
NC
NC
Vss
PIN NOMENCLATURE
AO-AS
CASO-CAS3
000-0031
NC
PD1- PD4
RASO-RAS3
VCC
VSS
W
Address Inputs
Column-Address Strobe
Data InJData OU1
No Connection
Presence Detects
Row-Address Strobe
5-VSupply
Ground
Write Enable
PRESENCE DETECT
SIGNAL
(PIN)
TM124BBK32F
e
TM24BCBK32F
PD1
(67)
PD2
(66)
PD3
(69)
PD4
(70)
&Ons
VSS
VSS
NC
Vss
70ns
Vss
Vss
Vss
NC
&Ons
VSS
VSS
NC
NC
BOns
NC
NC
NC
Vss
70ns
NC
NC
VSS
NC
&Ons
NC
NC
NC
NC
~ThxAs
INSTRUMENTS
POST OFFICE sex 1443 • HOUSTCN. TEXAS 77251-1443
TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS849A- DECEMBER 181M - REVISED JUNE 1885
Table 1. Connection Table
DATA BLOCK
JiASx
SIDE 1
000-007
RASO
008-0015
RASO
0018-0023
RAS2
0024-0031
RAS2
t Side 2 applies to the TM248CBK32F only.
~
SIDEzt
RASf
CASO
·RMf
RAS3
~
RAS§
~
~
singie-in-line memory module and components
PC substrate: 1,27 :t 0,1 mm (0.05 inch) nominal thickness; 0.005 Inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124BBK32F and TM248CBK32F: Nickel plate and gold plate over copper
Contact arEia for TM124BBK32U and TM248CBK32U: Nickel plate and tin/lead over copper
functional block diagram (TM124BBK32F and TM248CBK32F, side 1)
M-M----.-~------------------------------------------------~
1QIii
W~+---------------------------~
00-07
018-023
08-015
024-031
functional block diagram (TM248CBK32F, side 2)
M_M ....
4-~1~O
__________________________________________________
~
RD1
w~+---------------------~----~
08-015
024-031
00-07
018-023
-!111ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-41
TM124BBK32F, TM124BBK32U 1048576 BY 32·BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32·BIT DYNAMIC RAM MODULE
SMMS848A- DECEMBER 1894 - REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. - 1 V to 7 V
Voltage range on any pin (see Note 1) ................................................. -1 V to 7 V
Short-circuit output current ..............•.....•..••....•.......•....................•..... 50 rnA
Power dissipation: TM124BBK32F, TM124BBK32U ••••••••••••••••••••••••••..••.•.••.••••• 2 W
TM248CBK32F, TM248CBK32U •••••••.•••••••.••••••••••••••.•••••••••• 4 W
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg •••.••.•••••••••••••••••••.••••.•• ~ •.•••••••••••• , - 55°C to 125°C
stresses beyond thoae listed under "absolute maximum ratings" may cause permanent damage 10 the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" Is not
implied. Exposura 10 absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage ,values are with respect to VSS.
t
recommended operating conditions
MIN
NOM
MAX
Vcc
Supply voltage
4.S
S
S.S
V
VIH
High-laval input voltage
2.4
V
VIL
TA
Low-level Input voltage (see Note 2)
-1
8.S·
0.8
70
"C
Operating frae-alr temperature
0
UNIT
V
NOTE 2: The algebraic convention. where the more negative Oass positiva) limit is designated as minimum. is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH,,-SmA
VOL
Low-laval output voltage
IOL =4.2 mA
II
'124BBK32F-60
MIN
MAX
'124BBK32F-70 '124BBK32F-80
MIN . MAX
MIN
MAX
2.4
2.4
2.4
UNIT
V
0.4
0.4
0.4
V
Input current Oeakage)
VCC -S.SV. VI "OVto8.SV.
All other pins .. 0 V to Vcc
:1:10
:1:10
:1:10
!AA
10
Output current (leakage)
VCC .. S.SV.
VO .. OVtoVCC.
CAS high
:1:10
:1:10
:1:10
!AA
ICC1
Read- or wrlte-cycle
current
VCC-S.SV. Minimum cycle
180
160
140
mA
VIH .. 2.4 V (TTL).
After 1 memory cycle.
RAS and CAS high
4
4
4
rnA
VIH" VCC-0.2 v (CMOS).
After 1 memory cycle.
RAS and CAS high
2
2
2
rnA
ICC2 Standby current
Avarage refresh current
ICC3 (RAS only or CBR)
VCC= S.SV. Minimum cycle.
RAScycling.
CAS high (RAS only):
RAS low after CAS low (CBR)
180
180
140
rnA
ICC4 Average page current
VCC=S.SV. tpC=MIN.
RASlow.
CAS cycling
180
160
140
rnA
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, 1CXAB 77251-1443
TM124BBK32F, TM124BBK32U 1048576 BY 32·BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32·BIT DYNAMIC RAM MODULE
SMMS649A- DECEMBER 1994 - REVISED JUNE 1985
electrical characteristic. over recommended range. of .upply voltage and operating free-alr
temperature (unle•• otherwl.e noted)t
PARAMETER
TEST CONDITIONS
VOH
High-level output
voltage
IOH--6mA
VOL
Low-level output
voltage
10l " 4.2 mA
II
Input current ~eakage)
VCC .. 6•6V,
VI" OVtoe.6V,
All other pins .. 0 V to VCC
Output current
Vcc 6.6 V,
VO-OVtoVcc, ~high
10
ICCl
~akage)
Read- or wrlte-cycle
current (see Note 3)
1CC2 Standby current
'248CBK32F-60
MIN
'248CBK32F -70
MAX
2.4
MIN
'248CBK32F-80
MAX
MIN
2.4
MAX
UNIT
V
2.4
0.4
0.4
0.4
V
.. 10
.. 10
.. 10
f&A
.. 20
.. 20
.. 20
f&A
184
164
144
mA
VIH .. 2.4 V (TTL),
After 1 memory cycle,
RAS and ~ high
8
8
8
mA
VIH .. Vcc - 0.2 V (CMOS),
After 1 memory cycle,
RAS and CAS high
4
4
4
mA
380
320
280
mA
184
164
144
mA
=
VCC- S•6V,
Minimum cycle
Average refresh
1CC3 current (RAS only or
CBR) (see Note 3)
Minimum cycle,
Vcc = 5.5 V,
RAScycllng,
CAS high (RAS only);
RAS low after CAS low (CBR)
Average page current
ICC4 (see Note 4)
VCC 6.5 V,
RASlow,
=
tpC=MIN,
CAS cycling
..
t For test conditions shown as MINIMAX, use the appropriate value specified under recommended operating conditions•
NOTES: 3. Measured with a maximum of one address change while RAS = Vil
4. Measured with a maximum of one address change while ~ = VIH
capacitance over recommended range. of supply voltage and operating free-alr temperature,
f = 1 MHz (.ee Note 5)
'124BBK32F
PARAMETER
MIN
MAX
'248CBK32F
MIN
MAX
UNIT
CI(A)
Input capacitance, AO-A9
10
20
pF
CILR)
Input capacitance, RAS Inputs
7
7
pF
CICCI
CI(W)
Input capacitance, ~ Inputs
7
14
pF
14
28
pF
7
14
pF
Input capacitance, W
C~(OQl Output capacitance on OOD-DQ31
NOTE 6: VCC" 6 V .. 0.5 V, and the bias on pins under test IS 0 V.
~.1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
TM124BBK32F, TM124BBK32U 1048576 BY 32·BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32·BIT DYNAMIC RAM MODULE
SMMS849A- DECEMBER 1884 - REVISED JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating fr....lr
temperature
'124BBK32F-60
'24BCBK32F-60
PARAMETER
MIN
MAX
'124BBK32F-70
'24BCBK32F-70
MIN
MAX
'124BBK32F-60
'24BCBK32F-80
MIN
UNIT
MAX
tM
Access time from column address
30
35
40
ns
\cAc
Access time from CAS low
1~
1B
20
ns
tRAc
Access time from RAS low
80
70
80
ns
tePA
Access time from column precharge
35
40
45
ns
teLZ
~ to output In low-lmp8clance state
0
0
0
toH
Output disable time from start of ~ high
3
3
3
toFF Output disable time after ~ high (see Note 8)
NOTE 8: toFF Is lpeclfled when the output Is no longer driven.
0
15
0
18
0
ns
ns
20
ns
timing requirements over recommended ranges of supply voltage and operating fre...lr
temperature
'124BBK32F-60
'24BCBK32F-60
MIN
MAX
'124BBK32F-70 '124BBK32F-80
'24BCBK32F-70 '24BCBK32F-SO
MIN
MAX
MIN
UNIT
MAX
lAc
Cycle time, random reed or write (see Note 7)
110
130
150
lRWc
tpc
Cycie time, raad-wrlte
155
181
205
Cycle time, pege-mode read or write (see Notes 7 and 8)
40
45
50
tRASP
Pulse duration, page mode, RAS low
60 100000
70 100000
60 100000
tRAS
Pulse duration, nonpege mode, RAS low
80
10000
70
10000
60
10000
teAS
tep
Pulse duration, ~ low
15
10000
10000
10 .
20
10
10000
Pulse duretion, CAS high
18
10
tRP
Pulse duration, RAS high (prscharge)
40
50
80
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
ns
twP
Pulse duration, W low
lAsc
tASR
Setup time, column address before ~ low
0
0
0
ns
Setup time, row addrass before RAS low
0
0
0
ns
tos
Setup time, data befora CAS low
0
0
0
ns
lACs
Setup time, W high before ~ low
0
0
0
ns
tcwL
lRWL
Setup time, Wlow before ~ high
15
18
20
ns
Setup time, W low before RAS high
15
18
20
ns
twcs
Setup time, W low batoreCAS low
0
0
0
ns
twRP
Setup time, W high before RAS low (CBR refresh only)
10
10
10
nl
teAH
Hold time, column address after CAS low
10
15
15
nl
tRHCP
Hold time, RAS high from CAS prscharge
35
40
45
nl
tOH
tAAH
Hold time, data after CAS low
10
15
15
Hold time, row address after RAS low
10
10
10
ns
ns
tRCH
Hold time, W high after ~ high (see Note 9)
0
0
0
nl
Hold time, W high after RAS high (see Note 9)
tRRH
NOTES: 7. All cycles assume tr 5 ns.
8. To assure tpc min, tASC should be :.. teP.
9. Either tRRH or tRCH must be satisfied for a read cycle.
0
0
0
ns
=
~1ExAs
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON, lEXAS 77251-1443
TM124BBK32F, TM124BBK32U 1048576 BY 32·BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32·BIT DYNAMIC RAM MODULE
SMMS649A- DECEMBER 1994 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
'124BBK32F-60 '124BBK32F-70 '124BBK32F-80
'248CBK32F-60 '248CBK32F-70 '248CBK32F-80
MIN
MIN
MAX
MIN
MAX
MAX
UNIT
twCH
Hold time, Wlow after ~ low
10
15
15
twRH
Hold time, W high after RAS low (CBR refresh only)
10
10
10
118
teHR
Delay time, RAS low to ~ high (CBR refresh only)
10
10
10
ns
teRP
Delay time, ~ high 10 RAS low
5
5
5
na
teSH
Delay time, RAS low to CAS high
60
70
80
na
teSR
tRAO
Delay time, CAS low to RAS low (CBR refresh only)
5
5
5
118
Delay time, RAS low to column address (see Note 10)
15
tRAL
Delay time, column address to RAS high
30
teAL
tRCD
Delay time, column address 10 CAS high
30
Delay time, RAS low to CAS low (see Note 10)
20
tApc
Delay time, RAS high to ~ low (CBR only)
tASH
tREF
Delay time, CAS low to RAS high
tr
Trall8lt1on time
30
15
35
35
20
52
118
15
18
20
118
30
18
3
30
NOTE 10: The maximum value la specified only to essure access time.
device symbolization (TM124BBK32F Illustrated)
[~:::::::~]
-SS
T
-SS
118
0
18
YY
MM
118
60
0
3
[:~:::::~~:]
20
na
118
0
Refresh time Interval
(,)
40
40
40
35
45
15
118
= Year Code
= Month Code
= Assembly Site Code
= Speed Code
NOTE: Location of symbolization may vary.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
(,)
3
18
ma
30
na
TM124BBK32F.:TM124BBK32U1048576 BY 32-BIT DYNAMIC RAM MODULE '
TM248CBK32F, TM248CBK32U 2097152 BY.32-BIT DYNAMIC RAM MODULE
SMMS649A- DECEMBER 1994.-.REVlSED JUNE 1995
Ii
~1ExAs
.
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON; lCXAS .?7251-1443
TM497BBK32, TM497BBK32S
4194304 BY 32-BIT
DYNAMIC RAM MODULE
SMMS433B-JANUARY 1993-
• Organization", 4194304 x 32
• Single S-Y Power Supply (=10% Tolerance)
• 72-Pln Slngle-ln-Llne Memory Module
(SIMM) for Use With Sockets
• Utilize. Eight 16-Megablt DRAMs In Plastic
Smail-Outline J-Lead (SOJ) Packages
• Presence Detect
• Performance Ranges:
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
WRITE
'RAC
tAA
teAC
CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
'49788K32-60
60 ns
30 ns
15 ns
110 ns
'49788K32-70
70 ns
35 ns
18 ns
130 ns
'49788K32-60
80 ns
40 ns
20 ns
150 ns
• Long Refresh Period
32 ms (2048 Cycles)
• All Inputs, Outputs, Clocks Fully TTL
Compatible
• 30State Output
• Common CAS Control for Eight Common
Data-In and Data-Out Lines In Four Blocks
• Enhanced Page Mode Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
• Low Power Dissipation
• Operating Free-Alr-Temperature Range
O°C to 70°C
• Gold-Tabbed Version Avallable: t
TM497BBK32
• nn-Lead (Solder) Tabbed VerSion
Available: TM497BBK32S
description
The TM497BBK32 is a 16M-byte dynamic random-access memory (DRAM) organized as four times 4194304
x 8 in a 72-pin leadless single-in-line memory module (SIMM). The SIMM is composed of eight TMS417400DJ,
4194304 x 4-bit DRAMs, each in 24/26-lead plastic small-outline J-Iead (SOJ) packages mounted on a
substrate with decoupling capacitors. The TMS417400DJ is described in the TMS417400 data sheet.
The TM497BBK32 SIMM is available in the single-sided BK leadless module for use with sockets. The
TM497BBK32 SIMM features RAS access times of 60 ns, 70 ns, and 80 ns. This device Is characterized for
operation from O°C to 70°C.
operation
The TM497BBK32 operates as eight TMS417400DJs connected as shown in the functional block diagram and
Table 1. The common 1/0 feature dictates the use of early write cycles to prevent contention on D and Q.
refresh
The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with
RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power,
power up
To achieve proper operation, an initial pause of 200 !.IS followed by a minimum of eight initialization cycles is
required after full Vee level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CBR) cycle.
___
t Part numbers In this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
--_10
I'ROOUC11ON DATA InIo_ /0
oumn/ •
opoo/tIoaI/onI flll'tht -
=T'~
of _
011_ -
dolo.
noI--'1nc/udO
-lIs
~ 1ExAs
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77261-1443
Copyright C 1995, Texas Instruments Incorporated
6-47
TM497BBK32, tM497BBK32S
4194304 BY 32-8IT
DYNAMIC RAM MODULE
SMMS433B..., JANUARY 1993 - REVISED JUNE 1995
BK SINGLE-IN-UNE PACKAGE
(TOP VIEW)
Ves
DQO
D018
DOl
D017
CO2
D018
DQ3
D018
Vee
NC
AD
Al
AI
AI
A4
AS
AS
Al0
DQ4
D020
DQ5
C021
DQ5
DQ22
DQ7
'co:
NC
VCC
AS
AS
NC
AAS2
NC
NC
NC
NC
Vss
CABO
CJl
CJ 2
CJ 3
CJ 4
CJ 5
CJ 8
CJ 7
CJ 8
CJ 8
C J 10
C J 11
C J 12
C J 13
C J 14
C J 15
C J 18
C J 17
C J 18
C J 18
C J 20
C J 21
C J 22
CJ 23
C J 24
C J 25
C J 28
CJ 27
C J 28
C J 28
C J 30
C J 31
C J 32
C J 33
C J 34
C J 35
C J 38
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
37
38
38
40
41
42
43
44
46
46
47
48
48
50
51
82
(SIDE VIEW)
e
D
D
D
D
= D
CASl
RASO
NC
NC
Vi
NC
DOS
DQ24
DQ8
DQ25
DOlO
DQ25
0011
C027
0012
DQ25
Vee
DQ25
0013
DQ30
0014
DQ31
0015
NC
POl
POI
POI
PD4
NC
Vss
&3
64
&5
&8
57
&8
&8
eo
81
82
83
84
86
86
87
86
88
70
71
72
PIN NOMENCLATURE
D
D
D
AO-A10
CASO-~
DQO-DQ31
NC
PD1-P04
RASO,RAS2
VCC
Y§s
W
PRESENCE DETECT
SIGNAL
(PIN)
SOns
TM497BBK32
PD1
PD2
PD3
(67)
(68)
(89)
(70)
VSS
NC
NC
NC
NC
VSS
VSS
NC
NC
7.0ns
VSS
SOns
VSS
~1ExAs
INSTRUMENTS
6-48
Address Inputs
Column-Address Strobe
Data In/Data Out
No Connection
Presenoe Detects
Row-Address Strobe
5-V Supply
Ground
Write Enable
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
NC
PD4
TM497BBK32,TM497BBK32S
4194304 BY 32·BIT
DYNAMIC RAM MODULE
SMMS433B- JANUARY 1893 - REVISED JUNE 1885
Table 1.• Connection Table
DATA BLOCK
000-007
008-0015
0018-0023
0024-0031
JiASi
AASO
CASx
eA§O
RASO
CAS1
RAS2
~
RAS2
CAS3
singie-in-line memory module and components
PC substrate: 1,27 :to 0,1 mm (0.05 Inch) nominal thickness; 0.005 Inch/lnch maximum warpage
Bypass capacitors: Multilayer ceramic
.
Contact area for TM497BBK32: Nickel plate and gold plate over copper
Contact area for TM497BBK32S: Nickel plate and tin-lead over copper
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 772tS1-1443
~
I
mc.oo .....
functional block diagram
AO-A10
a:: :
~<-"
~ZCD .00
,
RASO
Vi
CASO
RAS2
-
4Mx4
4Mx4
~
~
~.!.
&
'"
OE
~ Vi
~
CAS
001DQ4
~DQODQ3
-b-
~ AO-A10
~ ViRAS
~
'"
'"
CAS
OE
'"
DQ4
~
CAS
OE
001- . . . 008DQ4
D011
-!-
~
~Do.DQ7
-!--
CAS
'" OE001DQ4
OE
001- . . . DQ12D015
-!--
4Mx4
Ia:::::~a:::::
AO-A10
~ ViRAS
Vi
... 0019
~'6- -!-
Vi
~
... CAS
OE
001- . . . DQ20DQ23
DO.
'"
'"
IO ..... ~
~c
-C
CAS
OE
001DQ4
DQ24DQ27
~ AO-A10
~ ViRAS
-!--
'" CAS
'" OE001DO.
DQ28-
0031
.....
m
m
rR.
em
Co.
"
W
m
(I)
~
i
4Mx4
~ AO-A10
RAS
CAS
DO.
~
4Mx4
~ AO-A10
~ ViRAS
~
DQ1-
RAS
4Mx4
4Mx4
s
;~
~
Vi
4Mx4
~ AO-A10
RAS
AO-A10
~nm~
!::D<
I'd
~»W _
_a:::::~ .....
CASa-
CAS2-
CAS1AO-A10
~ RAS
il"!~
2~
i»t~
IIIa:::::Om
1_.00 m
11
~
TM497BBK32, TM497BBK32S
4194304 BY 32·BIT
DYNAMIC RAM MODULE
SMMS433B - JANUARY 18113 - REVISED JUNE 1885
absolute maximum ratings over operating free..lr temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) •• • • • • • . • • • • • • • • • . • • . . • • • . • • • . • • • • • • • • • • • • • • • • - 1 V to 7 V
Voltage range on any pin (see Note 1) ................................................. -1 V to 7 V
.Short-cIrcuit output current •••••••••...••.•.•..................••••••.••••..•.•••••.•••••.• 50 rnA
Power dissipation ••••.••••••.••.•...••••••..•...••••.••.••.•••••••.••••••••••••••••••••.•.• 8 W
Operating free-air temperature range, TA ....... ~ . .. .. . .. . . .. . .. .. . . . .. .. .. • .. .. .. • .... O°C to 700 e
Storage temperature range, Tstg .................................................. - SsoC to 125°C
t Streaaea beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are straa ratings only. and
functional operation of the device at thasa or any other conditions beyond those Indicated under "recommended operating condlllona" II not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
Vcc
VIH
Supply voltage
High-level Input voltage
MIN
NOM
MAX
4.S
2.4
S
S.S
8.S
UNIT
V
V
-1
Low-levellnput voltage (see Note 2)
0.8
V
VIL
·C
Operating free..alr temperature
0
70
TA
NOTE 2: The algebraic convention. where the more negative Oess positive) limit Is designated as minimum. Is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free..lr
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS;
VOH
High-level output voltage
10H .. -SmA
VOL
Low-level output voltage
II
Input currant Oeakage)
IOL-4.2mA
VCC=5.SV.
VI-OVto8.5V.
All others = 0 V to VCC
10
Output currant Oeakege)
ICC1
Read· or write-cycle current
(see Note 3)
~=5.5V.
'497BBK32-80 ·497BBK32·70 . '497BBK32-80
MIN MAX
MIN MAX
MIN MAX
2.4
2.4
2.4
0.4
0.4
0.4
:080
:080
lolA
VO" 0 Vto VCC.
:010
:1:10
:010
lolA
Minimum cycle
880
800
720
mA
16
16
18
mA
8
8
8
mA
880
800
720
mA
400
mA
=
1002 Standby currant
Average refresh current
ICC3 ~ only or CBR)
(sae Note 3)
V
V
:080
CAS high
Vcc= 5.5V.
UNIT
VIH 2.4 V (TTL).
After 1 memory cycle.
~ and eAS high
VIH .. Vcc - 0.2 V (CMOS).
After 1 mamory cycle.
~ and eAS high
Minimum cycle.
YQQ=S.5V.
RAS cycling.
eAShlgh
(RAS only);
RAS low after
eAS low (CBR)
Average page currant
~.S.5V.
~.. MIN,
580
480
ICC4 (see Note 4)
CA cycling
RASIow.
For tast conditions shown as MIN /MAX. use the appropnate value specified under recommended operating conditions.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL
4. Measured with a maximum of one address change while CAS .. VIH
*
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-61
TM497BBK32,TM497BBK32S
4194304 BY 32·BIT
DYNAMIC RAM MODULE
SMMS433B - JANUARY 1893 - REVISED JUNE 1995 ,
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
MIN
PARAMETER
MAX
UNIT
CleA)
Input capacitance, address inputs
40
pF
ClLRl
CICC)
Input capacitance, RAS Inputs
pF
Input capacitance, CAS Inputs
28
14
CI(W)
Input capacitance, wrlte-enable input
56
pF
7
pF
Co(OO) Output capacitance on DO pins
NOTE 5: VCC = 5 V :I: 0.5 V, end the bias on pins under test is 0 V.
pF
switching characteristics over recommended ranges of supply voltage and operating free-air
, temperature
'497BBK32.eG
PARAMETER
MIN
MAX
30
15
'497BBK32·70
MIN MAX
'497BBK32-80
MIN
MAX
UNIT
tAA
Access time from column address
teAC
Access time from CAS low
tePA
Access time from column precharge
lRAc
Access time from RAS low
teL2
CAS to output In low-impedance state
0
0
0
ns
toH
Output disable time from start of CAS high
3
3
3
ns
-toFF Output disable til1)e after CAS high (see Note 6)
NOTE 6: toFF Is spl!Cifl811 when the output is no longer driven.
0
35
40
ns
18
20
ns
35
40
ns
60
70
45
60
15
0
18
0
20
ns
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
"
'497BBK32-80
MIN
MAX
'497BBK32·70
MIN
MAX
'497BBK32-80
MIN
MAX
UNIT
tRC
tpc
Cycle time, random read or write ($88 ,Note 7)
110
130
Cycle time, pags-mode read or wrile (see Notes 7 and 8)
40
45
tRASP
Pulse duratldn, page-mode, RAS low
60 100000
70 100,000
50
80 100000
tRAS
Pulse duration, non·pags-mode, RAS low
60
10000
70
10000
80
10000
ns
teAS
tep
Pulse duration, CAS low
15
10000
18
10000
20
10000
ns
Pulse duretion, CI'S hIgh
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
50
60
ns
twp
Pulse duration, W low
40
10
10
10
ns
tASe',,;,
Seiup time, column address before CAS low
0
0
0
ns
tASR
Setup time, row address before RAS low
0
0
0
ns
tos
Setup time, data before CAS low
0
0
0
ns
tRCS
Setup time, W high before CAS low
0
0
ns
tcwL
Setup time, IN-low before CAS high
0
15
18
20
ns
tRWL
Setup time, W,low,before RAS high
15
18
20
ns
twcs
Setup time, W-Iow before CAS low
0
0
0
10
10
10
'ns
ns
Setup time, IN-high before RAS low (CBR refresh only)
twRP
. NOTES: 7. All cycles assume ty =5 ns.
8. To assure tpc min, tASC should be :0: tCp.
.1ExAS
6-52
INSTRUMENTS
POST OFFICE SOX 1443· HOUSTON. TEXAS'77251-1443
ns
160
ns
ns
TM497BBK32, TM497BBK32S
4194304 BY 32-BIT
DYNAMIC RAM MODULE
SMMS433B- JANUARY 1993 - REVISED JUNE 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'497BBK32-60
MIN
MAX
10
'497BBK32·70
MIN
MAX
15
'49788K32-60
MIN
MAX
15
UNIT
teAH
tRHCP
Hold time, column address after CAS low
Hold time, RAS high from CAS precharge
35
40
45
ns
tDH
tRAH
Hold time, data after ~ low
tACH
tRRH
twCH
Hold time, Wlow after ~ low
twRH
Hold time, W high after RAS low (CBR refresh only)
teHR
Delay time, RAS low to ~ high (CBR refresh only)
teRP
Delay tlme,~ high to RAS low
15
10
0
0
15
10
10
5
teSH
Delay time, RAS low to CAS high
60
teSR
tRAe
Delay time, CAS low to RAS low (CBR refresh only)
Delay time, RAS low to column address (see Note 10)
tRAL
Delay time, column address to RAS high
5
15
30
15
10
0
0
15
10
10
5
70
5
15
35
n8
Hold time, W high after CAS high (see Note 9)
10
10
0
0
10
10
10
5
teAL
Delay time, column address to CAS high
30
tRCD
tRPC
Delay time, RAS low to CAS low (see Note 10)
20
Delay time, RAS high to CAS low (CBR only)
tASH
tREF
Delay time, CAS low to RAS high
0
15
LlL
Hold time, row address after RAS low
Hold time, W high after RAS high (see Note 9)
Refresh time interval
Trensltlon time
9. Either tRRH or tRCH must be satlsfiad for a read cycle.
10. The maximum value is specified only to essure access time.
3
30
35
32
30
20
0
18
3
n8
n8
ns
ns
n8
ns
ns
40
52
20
ns
60
0
3
ns
ns
ns
20
32
30
ns
ns
40
40
35
45
n8
ns
80
5
15
ns
32
ms
30
n8
device symbolization
00000 00000
TM497BBK32
YV
MM
T
-SS
= Vear Code
= Month Code
= Assembly Site Code
= Speed Code
NOTE: The location of the part number may vary.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-53
TM497BBK32, TM497BBK32S
4194304 BY 32·81T
DYNAMIC RAM MODULE
SMMS433B-JANUARY 1993 - REVISED JUNE 1995
~1ExAs
INSTRUMENTS
POST OFFICE. BOX 1443 • HOUSTON, TEXAS 77251-1443
TM893CBK32, TM893CBK32S
8388608 BY 32·BIT
DYNAMIC RAM MODULE
SMMS652A - FEBRUARY 1
• Organization
TM893CBK32 ••• 8388608 )( 32 Bit
• Single S-V Power Supply (z10% Tolerance)
• 72-Pln, Leadless Single In-Line Memory
Module (SIMM) for Use With Sockets
• TM893CBK32 - Utilizes Sixteen 16-Megablt
Dynamic RAMs In Plastic Smail-Outline
J-Lead (SOJ) Packages
• Long Refresh Period
32 ms (2048 Cycles)
• All Inputs, Outputs, Clocks Fully TTL
Compatible
• 3-State Output
• Common CAS Control for Eight Common
Data-In and Data-Out Lines In Four Blocks
• Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
• Presence Detect
• Performance Ranges:
ACCESS
TIME
lRAC
ACCESS ACCESS READ
TIME
TIME
OR
1M
tcAC
WRITE
CYCLE
'893CBK32-60
'893CBK32-70
'893CBK32-60
(MAX)
60 ns
70 ns
60 ns
(MAX)
(MAX)
30ns
35 ns
40 ns
15 ns
18 ns
20 ns
(MIN)
110 ns
130 ns
150 ns
• Low Power Dissipation
• Operating Free-Alr-Temperature Range
O°C to 70°C
• Gold-Tabbed Versions Avallable: t
TM893CBK32
• Tin-lead (Solder) Tabbed Versions
Available:
TM893CBK32S
descrIptIon
The TM893CBK32 is a 32-megabyte, dynamic random-access memory organized as four times 8388608 )( 8
bits in a 72-pin, leadless single in-line memory module (SIMM). The SIMM is composed of 16 TMS417400DJ,
4194304)( 4-bit dynamic RAMs, each in 24/26-lead plastic small-outline J-Iead (SOJ) packages mounted on
a substrate with decoupling capacitors. The TMS417400DJ is described in the TMS417400 data sheet. The
TM893CBK32 SIMM is available in the double-sided BK leadless module for use with sockets.
operatIon
The TM893CBK32 operates as sixteen TMS417400DJs connected as shown in the functional block diagram
and Table 1. The common I/O feature dictates the use of early-write cycles to prevent contention on D and Q.
refresh
The refresh period is extended to 32 ms, and during this period each of the 2048 rows must be strobed with AAS
to retain data. To conserve power, CAS can remain high during the refresh sequence.
power up
To achieve proper operation, an initial pause of 200 JA.S followed by a minimum of eight initialization cycles is
required after full Vee level is achieved. These eight initialization cycles must include at least one refresh
(RAS-only or CBR) cycle.
t Part numbers In this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
~TEXAS
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON. TEXAS 77251-1443
Copyright C 1995, Texas lnatrumente II1COIJ)CIfIIIed
8-55
TM893CBK32, TM893CBK32S
8388608 BY 32·BIT
DYNAMIC RAM MODULE
SMMS862A- FEBRUARY 1986 - REVISED JUNE 1995
BK SINGLE-IN-LINE PACKAGE
(TOP VIEW)
~
DQI.
DaI
DQI7
DQ2
DQI.
DQ3
Dale
V28
NJ
AI
A2
M
A4
AI
AI
1010
DQ4
DQ20
DQII
DQ21
DQ8
D022
DQ7
DQ23
A7
NC
Vee
AI
d
NC
NC
TM893CBK32
(SIDE VIEW)
D
D
D
D
i D
RAIl
~
NC
DQ8
DQ24
DQI
DQ25
DalO
DQ28
DQII
DQ27
Dal2
DQ28
o'DaIS
c':ii
DQ30
Dal4
DQ31
DQIS
NC
POI
POI
PD3
P04
NC
Vss
D
D
D
PIN NOMENCLATURE
RASO-RAS3
Address Inpu1S
Column-Address Strobe
Data InJData Out
No Connection
Presence Detects
Row-Address Strobe
Vee
5-VSupply
VSS
VI
Ground
Write Enable
AO-A10
CASO-CAS3
000-OQ31
NC
P01-PD4
PRESENCE DETECT
SIGNAL (PIN)
TM8930BK32
80ne
70ne
SOne
~ThxAs
8-58
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. l1!lCAS 77251-1443
PD1
PD2
PD3
(67)
(68)
(68)
(70)
NO
NC
NO
VSS
Vss
VSS
NO
VSS
VSS
NO
NO
NO
PD4
TM893CBK32, TM893CBK32S
8388608 BY 32·BIT
DYNAMIC RAM MODULE
SMMS652A- FEBRUARY 1895 - REVISED JUNE 1895
Table 1. Connection Table
DATA BLOCK
DQO-DQ7
0Q8-oo15
0018-0023
DQ24-DQ31
JiASi
~
SIDE 1
SIDE 2
RASO
RASO
RAS1
CA§O
~
CAST
JiAS2
JiAS2
RAS3
~
AAS3
CAS3
single In-llne memory module and components
PC substrate: 1,27 ~ 0,1 mm (0;05 Inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
COntact area for TM893CBK32: Nickel plate and gold plate over copper
COntact area for TM893CBK32S: Nickel plate and tin-lead over copper
~1EXAS
INSTRUMENTS
POITOFFlCE 80X 1443 • HOUSTON. TEXAS 772&1-1443
~
functional block diagram (side 1)
f!!CC» -f
s:: c::)
AS c::)
NO c::)
DQ4 c::)
DQ22 c::)
DQ5 c::)
DQ23 c::)
DQ5 c::)
0024 c::)
007 c::)
0025 c::)
A7 c::)
NC c::)
VCC c::)
AS c::)
AI c::)
RAS3 c::)
RASi c::)
DQ28 c::)
DQ8 c::)
DQO
0018
001
0019
002
1
2
3
4
5
8
7
8
8
10
11
12
13
14
15
18
17
18
18
20
21
22
23
24
25
28
27
28
28
30
31
32
33
34
35
38
0017
DQ35
c::) 37
c::) 38
CASo
CAS2
CAS3
CASI
RASa
RASI
c::)
c::)
c::)
c::)
c::)
c::)
c::)
c::)
c::)
c::)
C::)'
c::)
e
D
D
D
D
D
Vss c::) 38
NC
W
NC
DQ8
DQ27
0010
./
/
--
DQ28
0011
DQ29
0012
DQ30
0013
DQ31
c::::>
c::)
c::)
c::)
c::)
c::)
c::::>
Vee c::)
DQ32
0014
DQ33
0015
DQ34
D018
NO
POI
PD2
PD3
PD4
NC
Vss
c::)
c::)
c::)
c::)
c::)
c::)
c::)
c::)
c::)
c::)
c::::>
40
41
42
43
44
45
45
47
48
48
50
51
52
53
54
65
68
67
68
5&
80
81
82
83
54
88
88
67
88
88
70
c::) 71
c::) 72
TM248NBK36B
(SIDE VIEW)
TM124MBK36B
(SIDE VIEW)
PIN NOMENCLATURE
D
D
D
D
e
AO-A9
CASO-CAS3
000-0035
NC
P01- P04
RASO-RAS3
VCC
VSS
W
Address Inputs
Column-Address Strobe
Data InJData Out
No Connection
Presence Detects
Row-Address Strobe
5-VSupply
Ground
Write Enable
PRESENCE DETECT
SIGNAL
(PIN)
TM124MBK36B
TM248NBK36B
P01
PD2
P03
(67)
(68)
(69)
P04
(70)
BOns
VSS
VSS
NC
VSS
70ns
VSS
VSS
VSS
NC
BOns
VSS
VSS
NC
NC
BOns
NC
NC
NC
VSS
70ns
NC
NC
VSS
NC
80ns
NC
NC
NO
NC
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS n251-1443
6-65
TM1'24MBK36B,TM124MBK36R 1048576 BY 36-BIT
TM248NBK36B~ TM248NBK36R 2097152 BY 36-BIT
DYNAMIC RAM MODULE
.
SMMSl37E-JANUARY 1881-REVlSEDJUNE 1885
Table 1. Connection Table
)Wi
DATA BLOCK
SIDE 1
SIDEzt
CASi
~
DQ8
RAS2
~
~
eA§O
eA§O
DQ9-OO18
0017
~
FiA§2.
~
~
CAST
CAST
oo18-DQ25
RAS2
~.
as2
as2
000-007
FiA§2
RAS3
DQ27-DQ34
RAS2
DQ35
RAS2
~
~
0028
eM!
~
t Side 2 applies to the TM248NBK38B only.
singie-in-line memory module and components
PC substrate: 1,27:1: 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: MuHilayer ceramic
Contact area for TM124MBK36B and TM248NBK36B: Nickel plate and gold plate over copper
Contact area for TM124MBK36R and TM248NBK36R: Nickel plate and tin-lead over copper
~1ExAs
8-88
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, 'TEXAS 77251-1443
functional block diagram (TM124MBK36B and TM248NBK36B, side 1)
10
--
ADRASO
RAS2
CAS1-
CASO1 -
10
§
~-~
~
~
~
"
-:!:-
AD-AS
OE
0 : ; .... 004007
J-=-
~Vi
..... CAS
OE
001- "'-0013D04
0016
~ ViCAS
RAS
~
CAS
"
OE
001DQ4
0012
~0018- ~
"
"
OE
DQ1D04
0021
1Mx4
.J:-=-
~ Vi
CD
OE
001OeM
DQ27DQ30
~ AD-AS
RAS
~ ViCAS
"-
...
1Mx4
~ AD-AS
RAS
L.:t:.. :SAS
~:s
~-
~DQ9-
.J:-
~ 1Mx4
~ 1Mx4
..... CAS
DQ4
~ AD-AS
RAS
AD-AS
AD-AS
HAS
CAS
OE
001-
1Mx4
~ Vi
~ Vi
.... OE
0:;...-000003
1Mx4
1Mx4
~~
.... CAS
I~r"'~i!
;~
1Mx4
CAS3-
CAS2-
"'-0022_
.f
"
OQ25
~
t
OE
001D04
-=-
mm
is1is1
1DQ34
JDJD
-f-f
1Mx4
en
!:::
3:
RAS
~ CAS3
.....
1.
...
~~
zill:
AD-AS
~ Vi
CAS4
"
"
-fi!
i: ....
CAS2
CAS1
OE
OeM
OQ3
OQ2
OQ1
OQ35
0Q26
0017
DQ8
i:
ill:
1\) ....
en
~ I\)
CD ~
~
mm
-
zill:
i~is1~
c:~:u ~
~ill:1\) ....
!n~1
~~~~
~iII: I\) 0)
~iII:~~
E0c.,) c.,)
~a~O)
~
_C:m •
zr-_m
... m-f=i
;
I
~~~i!
functional block diagram (TM248NBK36B, aide 2)
EZI\) -
-~C~
~.:z.:
'-mm
AD-M 10
RAfi
511-
CAli1 ~
~
~-.
~~
...
!Ir
i
.!.
OE
OO1- .... DOO
DQ4
~
DQ3
-
DQ4
L.:b
.... CAS
OEDQ1_ .... 004DQ4
DQ1- ....
008DQ12
~
DQ7
*
001-
DQ4 f4+-DQ18DQ21
ftAj'
... 58
'*"
DQ4
AD-M
iAI
!:
ifi
CAS
I
OE
001DQ4
-
~ DQ27DQ30
.... DQ22-
~
DQ4
~
:1DQ34
-
10
111,,4
AD-M
~ HAl
&
~
...
...
....
~~
':"
W
5§4
c:Afi
~
.... CASf
OE
SI
-01
m~
OE
DQ25
I\)~
~~
w
~ CAS
DQ1-
:D:D
,W
111,,4
....
mm
~~
0)0)
~aI
~ AD-M
HAS
w
~ CAl
..... OE
DQ1-
"
~
111,,4
~w
OEOO1_ .... 0013DQ4
001.
~
...... OE
~ AD-AB
HAS
~ 111,,4
AD-At
111,,4
L.:b ~At
~w
~
.b-
I!JJnz .:
~w
~~
..... 58
OE
'0':':
~C:C~
iI.ICI\) 111,,4
~w
~w
... ~
~
111,,4
AD-M
liD
AD-M
iAI
!.: ........
513-
CAS2111,,4
111,,4
AD-M
liD
~w
~
IiiJ
RAS3
DQ4~
DQ3 ~
DQ2~
001 ~
DQ35
DQ26
0017
DQ8
=i!l
TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT
TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT
DYNAMIC RAM MODULE
SMMS137E- JANUARY 1991 - REVISEDJUNE 1995
absolute maximum ratings over operating free..lr temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) .•....••....•...........•••....••...••••••.•••••• -1"V to 7 V
Voltage range on Vee (see Note 1) .... . .. .. .. .. . . .. . . . . • . .. . . . • . . . . .. .. . . .. ... .. .. . . -1 V to 7 V
Short-circuit output current •..•.•.........•.....•............•......•.....••.•.••••.•• ;.... 50 rnA
Power dissipation •••...••...•....••••....•.•.••...•.•....•.•.....•......•.....••....•.....• 9 W
Operating free-air temperature range, TA .............................................. ooe to 700 e
Storage temperature range, Tstg .................................................. - 55°e to 125°e
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" is not .
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to Vss.
recommended operating conditions
MIN
NOM
MAX
Vcc
Supply voltage
4.5
5
5.5
UNIT
V
VIH
High-level Input voltage
2.4
6.5
V
Low-level Input voltage (see Note 2)
-1
0.8
V
·c
Operating free..alr temperature
70
0
TA
.. . ..
NOTe 2: The algebraic convention, where the more negative Vess positIVe) limit IS designated as minimum, is used for logic-voltage levels only•
VIL
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TeST CONomONS
VOH
High-level output
voltage
IOH=-5mA
VOL
Low-level output
voltage
10L" 4.2 mA
II
Input current (leakage)
'124MBK36B-60 '124MBK38B-70 '124MBK36B-80
MIN
MAX
2.4
MIN
MAX
MIN
MAX
2.4
2.4
UNIT
V
0.4
0.4
0.4
V
VI = OVtoS.5V,
VCC=5.5V,
All other pins .. 0 V to VCC
:010
:010
:010
I4A
10
Output current
Oeakage)
VCC=5.5V,
Whlgh
VO .. OVtoVCC,
,0:10
:010
:010
I4A
ICCl
Read or write cycle
current (see Note 3)
VCC': 5•5V,
Minimum cycle
945
810
720
mA
18
18
18
rnA
9
9
9
mA
945
810
720
mA
810
720
830
rnA
1002
Standby current
After 1 memory cycle,
RAS and CAS high,
VIH .. 2.4 V (TTL)
After 1 memory cycle,
high,
VIH .. VCC - 0.2 V (CMOS)
RAS and W
ICC3
Average refresh current
(RAS only or CBR)
(see Note 3)
1CC4
Average page current
(see Note4)
Vcc =5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
VCC=5.5V,
RASIow,
tpc = minimum,
CAS cycling
NOTES: 3. Measured with a maximum of one address change while RAS .. VIL
4. Measured with a maximum of one address change while W =VIH
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
8-69
T,..124MBK36B, TM124MBK36R 1048576 BY 36·BIT
TM248NBK36B,TM248NBK36R 2097152 BY 36·BIT
DYNAMIC RAM MODULE
SMMSl37E - JANUARY 1991 - REVlSEDJUNE 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
tempe'llture (unless otherwise noted)
PARAMETER
TEST CONDmONS
VOH
High-level output
voltage
IOHa-5mA
VOL
Low-level output
voltage '
10J,.=4.2mA
II
Input current Oeakage)
10
Output current
(leakage)
ICC1
Read or write cycle
current (SBB Note 3)
ICC2
Standby current
VCC, .. 5.5V,
'248NBK36B-«I
MIN
2.4
VI "OVt06.5V,
All other pins .. 0 V to VCC
VCC=5.5V,
CAS high
Va .0VtoVcc,
VCC- 5•5V,
Minimum cycle
'After 1 memory cycle,
RAS and CAS high,
VIH .. 2.4 V (tTL)
VIH
ICC3
ICC4
Average page current
(see Note 4)
em
'248NBK36B-70 '248NBK36B-«)
MIN
MIN
MAX
MAX
2.4'
2.4
--
UNIT
V
0.4
0.4
0.4
V
.. 20
.. 20
.. 20
tIA
.. 20
.. 20
.. 20
tIA
963
828
738
mA
36
38
38
mA
18
18
18
mA
1890
1620
1440
mA
828
738
848
mA
After 1 memory cycle,
RAS and CAS high,
Average refresh current
only or CBR)
(see Note 3)
MAX
=VCC - 0.2 V (CMOS)
Vcc
=5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
VCC- 5•5V,
tpc .. minimum,
RAS low, ~ cycling
NOTES: 3. Measured with a maximum of one address change while RAS .. VIL
4. Measured with a max/mum of one address change while CAS .. VIH
capacitance over recommended ranges of supply voltage and operating free...r temperature,
f = 1 MHz (see Note 5)
PARAMETER
'124MBK36B
MIN
MAX
'248NBK36B
MIN
MAX
UNIT
CleA)
Input capacitance, AO-AS
45
90
pF
CIIR)
Input capacitance, RAS
35
35
pF
CI(cl
Input capacitance, CAS
21
42
pF
CI/Wl
Input capacitance, W
63
128
pF
Co(DQ)
Output capacitance on DQ pins
7
14
pF
NOTE 5: VCC
=5 V .. 0.5 V and the bias on pins under test is 0 V.
~1ExAs
8-70
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. leXA8 77251-1443
TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT
TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT
DYNAMIC RAM MODULE
SMMS137E-JANUARY 1991-REVISEDJUNE 1895
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature
'124MBK388e
'248NBK368e
PARAMETER
'124MBK38B·70
'248NBK38B-70
MAX
MIN
MIN
MAX
'124MBK38B-IIO
'248NBK388e
MIN
teAC
Access time from CAS low
15
18
20
tAA
30
35
40
60
70
80
tePA
Access time from column address.
Access time from RAS low
Access time from column precharge
35
40
teLZ
CAS to output In low Impedance
!RAc
0
toFF Output disable time after CAS high (see Note 8)
NOTE 6: toFF Is speclflad when the output Is no longer dnven.
45
0
0
15
0
0
18
0
UNIT
MAX
20
ns
ns
ns
ns
ns
ns
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature
'124MBK388e
'248NBK38B-60
MIN
'124MBK36B-70
'248NBK36B·70
MAX
MIN
MAX
'124MBK38B-80
'246NBK38B-IIO
MIN
UNIT
MAX
tpc
Cycle time, page-mode read or write (see Note 8)
40
tRASP
Pulse duration, page mode, RAS low
80
100000
70
100000
80
100000
tRAS
Pulse duration, nonpage mode, RAS low
80
10000
70
10000
80
10000
teAS
Pulse duration, CAS low
15
10000
18
10000
20
10000
tep
Pulse duration, CAS high
10
10
10
ns
ns
ns
ns
ns
ns
ns
tRC
Cycle time, random read or write (see Note 7)
110
130
150
tAWC
Cycle time, read write
130
153
175
45
50
tRP
Pulse duration, RAS high (precharge)
40
50
80
ns
twP
Pulse duration, write
15
15
15
tASC
Setup time, column address before CAS low
0
0
0
tASR
Setup time,
0
0
0
ns
ns
ns
tos
Satup time, date
0
0
0
ns
tRCS
S~p time, read before CAS low
0
0
0
ns
tcwL
Satup time, W low before CAS high
15
18
20
ns
tAWL
Setup time, W low before RAS high
15
18
20
ns
twcs
Satup time, W low before CAS low
0
0
0
twSR
Satup time,
10
10
10
ns
ns
.
row address before RAS low
Whigh (see Note 9)
=
NOTES: 7. All cycles essume IT 5 ns.
8. To essure tpc min, tASC should be :t 5 ns.
9. CBR refresh only
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
6-71
TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT
TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT
DVNAMIC RAM MODULE
SMMS137E- JANUARY 1991 - REvISEDJUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
'124MBK36B-60 '124MBK36B-70 '124MBK36B-60
'248NBK36B-60 '248NBK36B-70 '24SNBK38B-60
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
tcAH
tOHR
tOH
Hold time, column address after ~ low
10
15
15
na
Hold time, data after AAS low (see Nota 10)
50
55
60
na
Hold time, data
10
15
15
na
tAR
Hold time, column address after RAS low (see Note 10)
Hold time, (5AS low to CAS high
50
5
55
5
na
Hold time, row address after RAS low
10
10
60
5
10
0
0
15
60
10
20
0
80
10
15
tclCH
tRAH
tRCH
Hold time, read after CAS high (see Note 11)
0
0
tARH
Hold time, read after AAS high (see Nota 11)
Hold time. write after CAS low
Hold time. write after RAS low (see Nota 10)
Hold time, Whigh (see Note 9)
0
15
50
10
0
15
55
Delay time. RAS low to CAS high (see Note 9)
15
twCH
twcR
twHR
tcHR
tcRP
teaH
teaR
tRAO
tRAL
teAL
tRCO
tApc
tRSH
tREF
tr
Delay time. CAS high to RAS low
Delay time. RAS low to (5AS high
0
Delay time. CAS low to RAS low (see Nota 9)
Delay time, RAS low to column address (see Note 12)
Delay time, column addresa to RAS high
Delay time. column addresa to CAS high
Delay time. RAS low to (5AS low (see Note 12)
Delay time. RAS high to CAS low (see Note 9)
Delay time. ~ low to RAS high
Refresh time Interval
Tranaltlontlme
NOTES: 9.
10.
11.
12.
10
15
60
10
15
30
30
20
0
15
0
70
10
30
45
15
35
40
35
20
40
52
50
50
device symbolization (TM124MBK36B Illustrated)
000000 00000
YY .. Yaar Code
MM .. Month Code
T .. Assembly Site Code
-SS " Spead Code
NOTE: location of symbolization may vary.
-!111ExAs
6-72
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, 'TEXAS 77251-1443
na
na
na
40
2
ns
ns
na
ns
80
na
ns
na
18
16
2
CBRrefresh only
The minimum value la meesured when tAco Is aet to tRCO min as a reference.
Either tRRH or tACH must be satisfied for a read cycle.
The maximum value Is apecified only to assure access time.
TM124MBK36B
20
na
na
0
20
0
18
16
2
35
ns
ns
ns
ns
ns
50
ma
na
TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE
TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE
• Organization
TM124MBK36F ••• 1 048 576 x 36
TM248NBK36F ••• 2 097152 x 36
• Presence Detect
• Performance Ranges:
ACCESS
TIME
• Single 5-V Power Supply (:t10% Tolerance)
• 72-Pln Single-in-Une Memory Module
(SIMM) for Use With Socket
'RAc
(MAX)
60 ne
70 ne
60 ns
60 ne
'124MBK38F-60
'124MBK36F-70
'124MBK36F-60
'248NBK36F-60
'248NBK36F-70 70 na
'248NBK36F-60 60 ns
• TM124MBK36F - Utilizes "IWo 16-Megablt
and One 4-Megablt DRAMs In Plastic
Small-outllne J-Lead (SOJ) Packages
• TM248NBK36F - Utilizes Four 16-Megablt
and Two 4-Megablt DRAMs In Plastic
Small-outllne J-Lead (SOJ) Packages
• Long Refresh Period ••• 16 ms
(1024 Cycles)
• All Inputs, Outputs, Clocks Fully TTL
Compatible
• 3-State Output
• Common ~ Control for Nine Common
Data-In and Data-Out Unes In Four Blocka
• Enhanced pagsMode Operation With
CAS-Before-RA (CBR), RAS-Only, and
Hidden Refresh
ACCESS ACCESS READ
nME
nME
OR
lAA
teAC WRITE
CYCLE
(MAX)
30 ns
35 ns
40 ns
30 ns
35 ns
40 ns
(MIN)
(MAX)
15 na
110 ns
18 ns
130 na
20 na
15 na
150 na
110 na
18 ns
130 na
150 ns
20 ns
• Low Power DiSSipation
• Operating Free-Air Temperature Range:
O°Cto 70°C
• Gold-Tabbed Versions Avallable: t
- TM124MBK36F
- TM248NBK36F
• Tin-lead (Solder) Tabbed Versions
Available:
- TM124MBK36U
- TM248NBK36U
description
TM124MBK36F
The TM124MBK36F is a 4-MByte dynamic random-access memory (DRAM) organized as four times
1048576 x 9 In a 72-pin singie-in-line memory module (SIMM). The SIMM is composed of two TMS418160DZ,
1 048 576 x 16-blt dynamic RAMs, each in a 42-lead plastic smail-outline J-Iead (SOJ) package and one
TMS44460DJ, 1048576 x 4-bit DRAM In a 24/26-lead plastic small-outline J-lead (SOJ) package mounted on
a substrate with decoupllng capacitors. The TMS418160DZ and TMS44460DJ are described in the
TMS418160 and TMS44460 data sheets, respectively. The TM124MBK36F SIMM is available in the
single-sided BK leadless module for use with sockets.
TM248NBK36F
The TM248NBK36F is an 8-MByte DRAM organized as four times 2097152 x 9 In a 72-pin single-In-line
memory module (SIMM). The SIMM is composed of four TMS418160DZ, 1 048 576 x 16-bit dynamic RAMs,
each in a 42-lead plastic smail-outline J-Iead (SOJ) package and two TMS44460DJ, 1048576 x 4-bit DRAMs,
each in a 24/26-lead plastic small-outline (SOJ) package mounted on a substrate with decoupling capacitors.
The TMS418160DZ and TMS44460DJ ~e described in the TMS418160 and TMS44460 data sheets,
respectively. The TM248NBK36F SIMM Is available In the double-sided BK leadless module for use with
sockets,
operation
The TM124MBK36F operates as two TMS418160DZs and one TMS44460DJ connected as shown in the
functional block diagram and Table 1. The TM248NBK36F operates as four TMS418160DZs and two
TMS44460DJs connected as shown in the functional block diagram and Table 1. The common I/O feature
dictates the use of early write cycles to prevent contention on D and Q.
t Part numbers in this data sheel are for the pold-tabbed version; the information appnes to both pold-tabbed and solder-tabbed versions.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. 'IEXAS 7721i1-1443
Copyright 0 1895, Texas IlIIIIrUmenta IncoIporated
TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE
TM248NBK36F, TM248NBK36U .2097152.BY 36·BIT DRAM MODULE
SMMS85OA-APRIL 1995 - REVISED JUNE 1995
BK SINGLE-IN-LiNE MEMORY MODULE
TM124MBK38F
TM248NBK38F
croP VIEW)
(SIDE VIEW)
(SIDE VIEW)
Vas
DQO
DOl.
DOl
DOl.
DOl
DOlO
DC»
DOlI
Vee
He
AD
AI
AI
AS
M
AS
AS
NC
~
DQ22
DQ5
DQ2S
DOe
DQ24
DQ7
DQ25
A7
He
Vee
AS
AI
::
DOlI
DOe
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
CASO c:::>
CAS2 c:::>
CASi c:::>
as;
RASii c:::>
AASI c:::>
He c:::>
Vi c:::>
NC c:::>
DOe c:::>
DQ27 c:::>
DOlO c:::>
DOlI c:::>
DOlI c:::>
DQ28 c:::>
DQ12 c:::>
DC»o c:::>
DOla c:::>
. DC»1 c:::>
Vee c:::>
DC»2 c:::>
DOl. c:::>
DC»3 c:::>
DOIS c:::>
D034 c:::>
DOl. c:::>
Ne c:::>
POI c:::>
POI c:::>
P03 c:::>
P04 c:::>
He c:::>
Vss c:::>
D017
DC»5
VSS
1
2
S
~
o
5
•
7
8
•
10
11
12
13
1~
UI
1.
17
1.
I'
20
21
22
IS
24
25
28
27
28
28
so
31
S2
sa
M
S5
,..------,
D __
__ .JI
~
(TM248NBK36
~!n
sa
37
sa
38
PIN NOMENCLATURE
~
~1
AIJ-NJ
42
43
44
CASO-CAS3
000-0035
NC
P01- P04
~
~
~7
~
•
RASO-RAS3
50
51
Vee
52
53
W
VSS
54
Presence Oetecta
Row-Address Strobe
5-VSupply
Ground
Write Enable
55
51
57
PRESENCE DETECT
51
511
eo
01
12
13
54
55
55
57
55
..
70
SIGNAL
(PIN)
TM124MBK36F
TM246NBK36F
71
72
PD1
PD2
PD3
(67)
(68)
(69)
SOn.
VSS
VSS
NC
70ns
VSS
SOns
VSS
NC
VSS
NC
SOns
VSS
VSS
NC
70ne
SOns
NC
NC
NC
NC
VSS
NC
~1ExAs
6-74
Address Inpu1s
Column-Address Strobe
Data In/Data Out
No Connection
INSTRUMENTS
POST OFFICE BOX 1~ • HOUSTON, TEXAS 77251-1~
NC
P04
(70)
VSS
NC
NC
VSS
NC
NC
TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE
TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE
SMMS85OA- APRIL 11195 - REVISED JUNE 11195
Table 1. Connection Table
DATA BLOCK
JiASx
SIDE 1
SIDE2t
5Sx
CASO
oas
RASO
RAS1
FiAS2
RAS3
CMO
DQ9-DQ18
OQ17
AASO
RAS2
RASl
RAS3
CASl
CASl
OQ18-0Q25
OQ26
RAS2
RAS2
RAS3
RAS3
CAS2
0027-0034
0Q35
AAS2
FiAS2
RAS3
RAS3
CAS3
CAS3
OQO-OQ7
CAS2
t Side 2 applies to the TM248NBK38F only.
single In-line memory module and components
PC substrate: 1,27 ~ 0,1 mm (0.05 Inch) nominal thickness; 0.005 Inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124MBK36F and TM248NBK36F: Nickel plate and gold plate over copper
Contact area for TM124MBK36U and TM248NBK36U: Nickel plate and tin/lead over copper
:lllExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 'ICXAS 77251-1443
8-75
TM124MBK36F, TM124MBK36U1 048576 BY 36·BIT DRAM MODULE
TM248NBK36F, TM248NBK36U 2097152 BY 36·BIT DRAM MODULE
SMMS85OA-APRIL 1995-REVISED JUNE 1119G
functIonal block dIagram [TM124MBK36F and TM248NBK36F, sIde 1]
M-M--1-~------------------------~~
RASO
RAS2
W~~------------------~--------.
011025
DO07
09-
016
027-
CAS2
CAS3
034
OQI
OQ17
0Q26
OQ35
functIonal block dIagram [TM248NBK36F, sIde 2]
M_M __
~_1~0~
________________________
~
RAS1
w~+---------------------------~
10
09016
027035
DO-
011-
07
025
OQI
OQ17
0Q26
0Q35
:Ila TExAs
6·76
.
INSTRUMENTS
POST OFFICE BOX 1443 • HOUStoN, TEXAS 77251-1443
TM124MBK36F, TM124MBK36U 1048576 BY 36·BIT DRAM MODULE
TM248NBK36F, TM248NBK36U 2097152 BY 36·BIT DRAM MODULE
SMMS650A- APRIL 1995 - REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .....•....•........••...••••••.•.•.•••••••.... - 1 V to 7 V
Voltage range on any pin (see Note 1) ••.....••..•••................••••.•.•...•.•..••• -1 V to 7 V
Short-circuit output current ••.•.••.•...•....••..........•..........••.....••.•..•••••.•.•.• 50 rnA
Power dissipation
TM124MBK36F, TM124MBK36U ......•..••••.••••.••.••••.••.•••••••.•. 3W
TM248NBK36F, TM248NBK36U ......•••.•••••..••.••.••...••........... 6 W
Operating free-air temperature range, TA ....•••...•...•..•••••••.••.•.....•..•....••.. DoC to 70°C
Storage temperature range, Tstg .•....•...•••..••••....••............•.•..••••..•• - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings· may causa permanent damage to the device. These are strese ratings only, and
functional operation of the device at thesa or any other conditions beyond those indicated under "recommended operating conditions· is not
Implied. Exposura to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level Input voltage
2.4
8.5
V
Low-level input voltage (see Note 2)
-1
UNIT
V
·C
Operatlng free-air temperature
70
TA
NOTE 2: The algebraic convention, where the more negative Qess positive) limit is designated as minimum, is used for logic·voltage levels only.
VIL
0.8
°
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-laval output voltage
IOH=-5mA
VOL
Low-level output voltage
10L= 4.2 mA
'124MBK36F-60 '124MBK36F-70 '124MBK36F·80
MIN
MAX
2.4
MIN
MAX
2.4
MIN
2.4
MAX
UNIT
V
0.4
,0.4
0.4
V
Input current Oeakage)
Vcc =5.5 V, VI =OVto 8.5 V,
All other pins = V to VCC
°
:1:10
:1:10
:1:10
fAA
10
Output current Oeakage)
VCC=5.5V,
Vo = OVtoVCC,
CAS high
:1:10
:1:10
:1:10
fAA
ICC1
Read- or wrlte-cycle
current
VCC- 5.5V, Minimum cycle
285
250
220
mA
VIH .. 2.4 V (TTL),
After 1 memory cycle,
RAS and CAS high
8
8
8
mA
VIH .. VCC - 0.2 V (CMOS),
After 1 memory cycle,
RAS and CAS high
3
3
3
mA
285
250
220
mA
250
220
190
mA
II
ICC2 Standby current
~
Average refresh current
ICC3 (RAS only or CBR)
1CC4 Average pege current
.. 5.5V, Minimum cycle,
RASCYClin~
CAS high (RAS only);
RAS low after CAS low (CSR)
VCC = 5.5 V, tpC=MIN,
CAS cycling
RASlow,
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
6-77
TM124MBK36F, TM124MBK36U 1048576 BY 36·BIT DRAM MODULE
TM248NBK36F, TM248NBK36U 2097152 BY 36·BIT DRAM MODULE
SMMS65OA-APRIL ~995 - REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)t·
.
PARAMETER
TEST cONDmONS
VOH
High-level output
voltage
10H=-SrnA
VOL
Low-level output
voltage
10L = 4.2 rnA
II
Input current
Oeekage)
10
ICC1
'248NBK36F-60 '248NBK36F-70 '248NBK36F-60
MIN
MAX
MIN
MAX
MIN
MAX
2.4
2.4
2.4
UNIT
V
0.4,
0.4
0.4
V
VCC· S•SV,
VI'" 0 V to 6.S V,
AU other pine. 0 V to VCC
.. 10
.. 10
.. 10
(.IA
Output current
Oeakage)
VCC· S•SV,
VO .. OVtoVCC, ~high
.. 20
.. 20
.. 20
(.IA
Read- or write-cycle
current (see Note 3)
VCC- S•SV,
391
256
226
rnA
12
12
12
mA
6
6
6
rnA
500
440
mA
196
rnA
ICC2 Standby current
Averege refresh
ICC3 current (RAS only or,
CBR) (see Note 3)
Minimum cycle
VIH .. 2.4 V (TTL),
After 1 memory cycle,
RAS and CAS high
VIH • VCC - 0.2 V (CMOS),
After 1 memory cycle,
RAS and CAS high
VCC-S.SV,
,
Minimum cycle,
RAS cycling,
~ high
570
(RAS only);
RAS low after ~ low (CBR)
=
Average page current
ICC4 (see Note 4)
VCC .. S.SV,
tpc MIN,
256
226
RASlow,
eAScyciing
t For test conditions shown as MINIMAX, use the appropriate value specified under recommended operating conditione.
NOTES: 3. Measured with a maximum of one addrees change while RA§' .. VIL .
4. Measured with a maximum of one address change while eAS .. VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
'124MBK36F
PARAMETER
CiCA>
Ci(R)
CI(C)
MIN
Input capacitance, address inputs
Input capacitance, RAS inputs
MAX
'248NBK36F
MIN
MAX
UNIT
15
30
IRAS2,RAS3
14
14
IRASO, RAS1
7
pF
pF
Input capacitance, CAS inputs
14
Input capacitance, write-enable input
21
7
26
42
7
14
Ci/Wl
Co(OO) Output capacitance on DO pins
NOTE S: Bias on pine under test is 0 V.
~TEXAS
INSTRUMENTS
POSTOFFtCE BOX 1443· HOUSTON, 'reXAS 77251-1443
pF
pF
pF
TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE
TM248NBK36F, TM248NBK36U 2097152 BY 36·BIT DRAM MODULE
SMMS66OA- APRIL 1\195 - REVISED JUNE 1885
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature
'124MBK36F-60 '124MBK36F-70 '124MBK36F-60
'248NBK36F-60 '248NBK36F-70 '248NBK36F-60
PARAMETER
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
tM
Access time from column address
30
35
40
118
tcAe
Access time from CAS low
15
18
20
118
tRAe
Access time from RAS low
60
70
60
118
tePA
Access time from column precharge
3S
40
45
118
teLZ
CAS to output In low-Impedance state
Output disable time from start of CAS high
toH
toFF Output disable time after CAS high (see Note 8)
NOTE 8: toFF is 8pecffied when the output is no longer driven.
0
0
0
3
3
3
0
15
0
18
0
ne
n8
20
ns
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature
'124MBK36F-60 '124MBK36F-70 '124MBK36F-60
'248NBK36F-60 '248NBK36F-70 '248NBK36F-60
MIN
MIN
MAX
MIN
MAX
MAX
150
110
130
UNIT
tRe
Cycle time, random read or write (see Note 7)
tpC
Cycle time, page-mode read or write (see Notes 7 and 8)
40
45
tRASP
Pulse duration, page mode, RAS low
70
100000
60
100000
tRAS
Pulse duration, nonpage mode, RAS low
60 100000
60 10000
70
10000
60
10000
nB
teAS
tep
Pulse duration, CAS low
15
18
10000
20
10000
ne
Pulse duration, CAS high (precharge)
10
10
10
tRP
Pulse duration, RAS high (pracharge)
40
50
80
ne
twP
Pulse duration, W low
10
10
10
118
tAse
Setup time, column address before CAS low
0
0
0
ne
tASR
Setup time, row address before RAS low
0
0
0
nB
tos
Setup time, data before CAS low
0
0
0
118
tRCS
Setup time, W high before CAS low
0
0
0
118
tcwL
Setup time, Wlow before CAS high
15
18
20
118
10000
50
118
118
118
n8
tRWL
Setup time, W low befora RAS high
15
18
20
ne
twos
Setup time, W low befora CAS low
0
0
0
118
twRP
Setup time, W high before RAS low (CBR refresh only)
10
10
10
118
tcAH
Hold time, column address after CAS low
10
15
15
118
tAHCP
Hold time, RAS high from CAS precharge
35
40
45
ne
toH
Hold time, data after CAS low
10
15
15
118
tRAH
Hold time, row address after RAS low
10
10
10
118
tACH
tRRH
Hold time, Whigh after CAS high (Bee Note 9)
0
0
0
ns
Hold time, Whigh after RAS high (see Note 9)
0
0
0
ns
twoH
Hold time, Wlow after CAS low
10
15
15
n8
10
10
10
118
Hold time, W high after RAS low (CBR refresh only)
twRH
NOTES: 7. All cycleB essume IT "' 5 ne.
8. To assure tpc min, tASC should be • tep.
9. Either tRRH or tRCH must be satisfied for a read cycle.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-79
TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE
TM248NBK36F, TM248NBK36U ·2097152 BY 36-BIT DRAM MODULE
SMMS85OA- APRIL 1995_ REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (continued)
'124MBK36F·60
'248NBK36F·60
MIN
MAX
'124MBK36F· 70
'248NBK38F·70
MIN
MAX
'124MBK36F·60
'248NBK38F·8iI
MIN
UNIT
MAX
tcHR
Delay time, RAS IQw to CAS high (CBR refresh only)
10
10
10
na
tcRP
Delay time, CAS high to RAS low
5
5
5
nl
tcSH
Delay time, RAS IQw to CAS high
60
70
80
tcsR
tRAD
tRAJ.
Delay time, CAS IQw to RAS low (CBR refresh only)
Delay time, RAS low to column address (sea Note 10)
Delay time, column address to RAS high
Delay time, column address to CAS high
5
5
5
nl
na
teAL
tAco
tApc
tRSH
15
30
20
Delay time, RAS IQw to CAS IQw (188 Note 10)
Delay time, AAS high to CAS low (CBR only)
Delay time, CAS IQw to AAS high
tREF
Refresh time Interval
tr
Transition time
30
30
15
15
40
52
40
40
20
60
nl
nl
35
45
20
0
0
0
os
15
18
20
18
na
ml
30
os
18
18
3
30
3
30
NOTE 10: The maximum value II lpeciflad only to assure access time.
device symbolization (TM124MBK36F Illustrated)
[::~:::::~:]
VV
MM
T
-SS
•
•
..
•
na
nl
35
35
Year Code
Month Code
Assembly Site Code
Speed Code
NOTE: LocatIon of symbolization may vary.
-!/}1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
0
3
TM124MBK36C, TM124MBK36S 1048576 BY 36-BIT
TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT
DYNAMIC RAM MODULE
SMMS138B- MARCH
• Organization
TM124MBK36C ••• 1048576 x 36
TM248NBK36C ••• 2097152 x 36
• Enhanced Page Mode Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
• Single SoV Power Supply (:t10% Tolerance)
• Presence Detect
• Performance Ranges:
• 72-pln Leadless Single In-Une Memory
Module (SIMM)
ACCESS ACCESS ACCESS READ
• TM124MBK36C - Utilizes Eight 4-Megablt
DRAMs In Plastic SmalloOutline J-Lead
(SOJ) Package. and 'TWo 4-Megablt
Quad-CAS DRAM. In PlastiC SOJ Packages
• TM248NBK36C - Utilizes Sixteen 4-Megablt
DRAMs In Plastic SOJ Packages and Four
4-Megablt Quad-CAS DRAMs In PlastiC SOJ
Packages
• Long Refresh Period
16 ms (1024 Cycles)
'124MBK36c-60
'124MBK36C-70
'124MBK36C-SO
'248NBK36C-SO
'248NBK38C-70
'248NBK3&c-60
TIME
nME
nME
lRAc
lAA
tcAC
(MAX)
60 ns
70 ns
60 ns
60 ns
70 ns
60 ns
(MAX)
30 ns
35 ns
40 ns
30 ns
35 ns
40 ns
(MAX)
15 ns
18 ns
20ns
15 ns
18 ns
20 ns
OR
WRITE
CYCLE
(MIN)
110 ns
130 ns
150 ns
110 ns
130 ns
150 ns
• Allinputa, Outputs, Clocks Fully TTL
Compatible
• Low Power Dissipation
• Operating Free-Alr-Temperature Range
O°C to 70°C
• 3-State Output
• Common CAS Control for Nine Common
Data-In and Data-Out Unes, In Four Blocks
• Gold-Tabbed Versions Avallable: t
- TM124MBK36C
- TM248NBK36C
• Tin-Lead (Solder) Tabbed Versions
- TM124MBK36S
- TM248NBK36S
description
TM124MBK36C
The TM124MBK36C is a dynamic random-access memory (DRAM) organized as four times 1 048576 x 9 (bit
9 is generally used for parity) in a 72-pin leadless single in-line memory module (SIMM). The SIMM is composed
of eight TMS44400DJ, 1 048 576 x 4-bit DRAMs, each in 20/26-lead plastic small-outline J-Iead packages
(SOJs), and two TMS44460DJ, 1048576 x 4-bit Quad-CAS DRAMs, in 24/26-lead plastic SOJs mounted on
a substrate with decoupling capacitors. Each TMS44400DJ and TMS44460DJ is described in the TMS44400
and TMS44460 data sheets, respectively.
The TM124MBK36C is available in the single-sided BK leadless module for use with sockets.
The TM124MBK36C features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for
operation from O°C to 70°C.
t Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS n251-1443
Copyright C 1995. Texas Instrumen1llII1COlJIOI1lI8d
8-81
TM124MBK36C,TM124MBK36S 1048576 BY 36-BIT
TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT
DYNAMIC RAM MODULE
SMMS138S- MARCH 1892 - REVISED JUNE 1996
TM248NBK36C
The TM248NBK36C is a DRAM organized as four times 2 097 152 )( 9 (bit 9 is generally used for parity) in a
72-pln leadless SIMM) The SIMM is composed of sixteen TMS44400DJ,.1 048576)( 4-bit DRAMs, each In
20/26-lead plastic SOJs, and four TMS44460DJ, 1 048 576 )( 4-bit Quad-~ DRAMs, In 24/26-lead plastic
SOJs mounted on a substrate with decoupling capacitors. Each TMS44400DJ and TMS44460DJ is described
in the TMS44400 or TMS44460 data sheet, respectively.
The TM248NBK36C is available in the double-sided BK leadless module for use with sockets.
The TM248NBK36C features RAS access times of 60 ns, 70 ns, and 80 ns. This device is rated for operation
from O°C to 70°C.
operation
TM124MBK36C
The TM124MBK36C operates as eight TMS44400DJs and two TMS44460DJs connected as shown In the
functional block diagram and Table 1. The common I/O feature dictates the use of early write cycles to prevent
contention on D and Q.
TM248NBK36C
The TM248NBK36C operates as sixteen TMS44400DJs and four TMS44460DJs connected as shown In the
functional block diagram and Table 1. The common I/O feature dictates the use of early write cycles to prevent
contention on D and Q.
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lE
DQO
DOl.
DOl
0018
DQ2
DQ20
DQ3
DQ21
c::::::>
c::::::>
c::::::>
c::::::>
1
2
3
4
5
8~
c::::::> •
c::::::> 8
Vee c::::::> 10
NO c::::::> 11
NJ c::::::> 12
AI c::::::> 13
AI c::::::> 14
AI c::::::> 15
A4 c::::::> 18
AS c::::::> 17
All c::::::> 18
NO c::::::> 18
DQ4 c::::::> 20
D022 c::::::> 21
DQ5 c::::::> 22
D023 c::::::> 23
DQ8 c::::::> 114
DQII4 c::::::> 25
DQ7 c::::::> 28
DQ25 c::::::> V
A7 c::::::> 28
NO c::::::>_
Vee c::::::> 30
All c::::::> 31
All c::::::> 32
RAS3 c::::::> 33
RAS2 c::::::> 34
DQ28 c::::> 35
DQ8 c::::::> 38
c::::::>
c::::::>
aso c::::::>
CAS2 c::::::>
CAiii c::::::>
CASi c::::::>
RASO c::::::>
RASI
c::::>
NO c::::::>
IN c::::::>
NC c::::::>
D017
37
DQ35
38
38
40
Vss G::>
DOl
DQV
DOlO
DQ28
D011
DQ28
D012
DQ30
D013
DQ31
c::::>
c::::>
c::::>
c::::::>
c::::::>
c::::::>
c::::::>
c::::::>
c::::::>
c::::>
Vee c::::>
DQ32 c::::>
D014
DQ33
Da15
DQ34
Da18
NC
POI
POI
POI
c::::::>
c::::::>
c::::::>
c::::>
c::::::>
c::::::>
c::::>
c::::>
c::::::>
c::::::>
c::::::>
Vss c::::::>
P04
NO
41
42
43
44
45
048
47
048
048
50
51
52
63
54
155
58
57
58
58
50
81
82
83
54
88
88
87
88
88
70
71
72
TM124MBKa6C
(SIDE VIEW)
TM248NBKa6C
(SIDE VIEW)
e
D
D
D
D
D
D
D
D
D
D
e
PIN NOMENCLATURE
AO-AS
CASO-CAS3
000-0035
NC
P01- PD4
RASO-RAS3
VCC
VSS
iN
Address Inputs
Column-Address Strobe
Data In/Data Out
No Connection
Presence Detects
Row-Address Strobe
S-V Supply
Ground
Write Enable
PRESENCE DETECT
SIGNAL
(PIN)
PD1
(67)
PD2
60ns
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
80ns
NC
NC
NC
VSS
70ns
NC
NC
VSS
NC
80ns
NC
NC
NC
NC
80ns
TM124MBKa6C
TM248NBK36C
70ns
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON,'TEXAS 77251-1443
(68)
PD3
(69)
PD4
NC
VSS
VSS
NC
(70)
TM124MBK36C, TM124MBK36S 1048576 BY 36-BIT
TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT
DYNAMIC RAM MODULE
SMMS138B- MARCH 1992 - REVISED JUNE 1995
Table 1. ConnectIon Table
DATA BLOCK
RASX
CiSX
SIDE 1
SIDE2t
000-007
008
RASO
RASO
RASl
RASl
CASO
009-0016
0017
RASO
RASO
RAS1
f\AS1
CAS1
CAS1
0018-0025
0026
RAS2
RAS2
OQ27-oo34
RAS2
OQ35
RAS2
t Side 2 applies to the TM248NBK36C only.
CASO
RAS3
CAS2
AAS3
AAS3
CAS2
RAS3
CAS3
CAS3
singie-in-llne memory module and components
PC substrate: 1,27:t 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124MBK36C and TM248NBK36C: Nickel plate and gold plate over copper
Contact area for TM124MBK36S and TM248NBK36S: Nickel plate and tin-lead over copper
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lEXAS 77261-1443
functional block diagram (for TM124MBK36C and TM248NBK36C, Side 1)
AO_AS 10 <
~
RASO'T
T
Tn
~
o AO-AS
1Mx4
~
~-
~
~~
10
Ttl
CAS3-
1Mx4
AO-AS
RAS
Vi
CAS
OE
OE
001-_
DQ4
DQ9- DQ12
000- -::
003
o
~
1M .. 4
AO-AS
RAS
Vi
~
RAS
Vi
I oo~ ~ =--=.1
OE
i
OE
OO1-l4..a.- 0013!!9!J - - 0016
DQ18DQ21
o
1Mx4
AO-AS
CAS
..... CAS
1.
CAS2-
CAS
DQ4
I
Til
Vi.
001-
o
~~g
2rt1~
RAS
-=
~~~
L
CAS1-
,I
RAS2
1Mx4
RAS
Vi
-=
OE
.1
_
-=
OO1~DQ8
~OO17
RAS
Vi
.a=o.~
~i:
CAS
~-.
mm
~~
DQ34
CJ)C»
10
~
Vi
~----........ OE
i!i!
1\:» ....
AO-AS
51$)
RAS
L-----------------------~CAS1
DQ30
OE
D~!:-:: . . . 0031-
~DQ25
AO-AS
CAS2
1
DQ1-L_ DQ22- _
1M .. 4
.!.
S
DQ27-
01MX4
AO-AS
CAS
1.
-=
i!i!
1\:» ....
1M .. 4
AO-AS
RAS
CI.I
Vi
!!:
~
CAS2
L-------------------------~~CAS1
.1
OE~
DQ1
DQ26
DQ2
DQ35
.a=o. I\:»
.a=o.
zi:
C»
i mm
1119"
"
WW
~s;mm
I .......
2i:1\:»
__ ....
o~
I~!S C»
~»C;; CI'I
~i:1\:» ~
~!:~~
20WW
;
ific~~
-~mm
Im=i=i
x:
I
!Ci!i!
~~I\)
functional block diagram (for TM248NBK36C, Side 2)
CD
--.
i»~~
Uli!!!:Zi!!!:
1c;mm
AD-A9 10
~i;4
~ VI
.... CAS
Iz~
~
~ii
10
d.......
~3:
~.~
RAS
OE
ooO:;~DQ9-
J:-
OE
001- . . . D04DQ4
DQ7
..... CAS
OE
001- ~0013DQ4
~~
10
d"
"
-!-
DQ4
"
~ 0018- J.-
0016
J-=
~ AD-AS
~ VIRAS
" CAS
" OE001DeM
"'D022- f
""
DQ4
D025
i!:
~
CAS2
~~
0031D034
1Mx4
AO-AS
RAS
VI
..... CAS2
..... CAS1
-!-
~~
--'--.
~~
OE
001-
::;:R;:;;a:;
1\)--.
0027-
~ CAS
VI
CAS1
1..-008
DQ2 ~0017
DQ4
1Mx4
1Mx4
001
001-
~ AD-AS
RAS
AD-AS
RAS
VI
OE
...... OE
D030
1Mx4
1Mx4
AD-AS
~VI
J-=
...
iii
i... (1)81
~w
CAS
DQ21
RAS
RAS
VI
CAS
J-
CAS
OE
001-
~r-Zi!!!:
cmm
m
AD-AS
~ iiAS
~
...... VI
VI
0012
~
1Mx4
AD-AS
~
CAS
003
:z:C
~rn
~ . . . DQO- -!-
~
....
Ci5C~~
mC m oI::a
1Mx4
~ AD-AS
RAS
AD-AS
~VI
OE
1Mx4
1Mx4
I
~Oi!!!: ill:
CAS3-
CAS2-
CAS1-
CASO1 -
§
I~~·~p
ii:ilI:-I-I
iiASi
RAfi
OE
001
D026
DQ2
DQ36
Ww
en en
• •
mm
=i=i
· TM124MBK36C, TM124MBK36S 1048576 BY 36-BIT
TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT
DYNAMIC RAM MODULE
SMMS138B - MARCH 1992 - REVISED JUNE 1895
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on Vee (see Note 1) .•................•..........••••.•.•••••••. - 1 V to 7 V
Supply voltage range on any pin (see Note 1) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -1 V to 7 V
Short~circult output current ......•.•....•.....•.......................•....•.••..••..••••.. 50 mA
Power dissipation •••.•.•.•.••.•.•.•......................•........•••.•.••..•..•.•...••.•. 10 W
Operating free-air temperature range, TA •.•.•....................••...• • • • • • . . •• • • . • .• ooe to 700 e
Storage temperature range, Tstg ......•.•.....•.......•...............•.•....••.•. - 55°e to 125°e
stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those .indicated under "recommended operating conditions" Is not
Implied. Exposure to absolute-maxlmum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
t
recommended operating conditions
MIN
NOM
Vee
Supply voltage
4.5
5
VIH
High-level Input voltage
2.4
MAX
5.5
6.5
UNrr
V
V
Low-level Input voltage (see Note 2)
-1
0.8
V
VIL
·C
Operating free-air temperature
0
70
TA
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated es minimum. Is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free..lr
temperature (unless otherwise noted)
PARAMETER
TEST CONomONS
VOH
High-level output voltage
10H =-SmA
VOL
Low-level output voltage
10L 4.2 rilA
II
Input current (leakage)
VI = 0 Vlo 6.5 V.
VCC= S.5V.
All other pins .. 0 V to VCC
10
Output current Oeakage)
ICC1
Read- or wrIta-cycle
current (see Note 3)
IC02 Standby current
Average refresh current
Icca (RA'S only or CBR)
(see Note 3)
'124MBK36C-60 '124MBK36C-70 '124MBK36C-80
MAX
MIN
MAX
MIN
MAX
MIN
2.4
=
2.4
V
0.4
0.4
0.4
V
:1:10
:1:10
:1:10
I&A
:1:10
:1:10
:1:10
I&A
1050
900
800
mA
VIH .. 2.4 V (TTL).
after 1 memory cycle.
~ and CAS high
20
20
20
mA
VIH .. VCC - 0.2 V (CMOS).
after 1 me~ cycle.
~ and CAS high
10
10
10
rnA
1050
900
600
rnA
900
600
700
mA
VCC .. S.5V. '
Vo .. OVIOVCC.
~hlgh
VCC .. S•5V•
Minimum cycle
VCC .. 5.5V.
Minimum cycle.
RAS cycling.
~ high (RAS only).
~ low after ~ low (CBR)
IPC .. Minimum.
CAS cycling
NOTES: 3. Measured with a maximum of one address change while ~ = VIL
4. Measured with a maximum of one address change while ~ =VIH
Average page current
1CC4 (see Note 4)
2.4
UNIT
VCC-S.SV.
~Iow.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
6-67
TM124MB.K36C, TM124MBK36S 1048576 BY 36-BIT
TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT
DYNAMIC RAM MODULE
SMMS138B-MARCH 1992-REVlSEDJUNE 1885
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
10Ha-SmA
VOL
Low-Ievel output voltage
10L 4.2 mA
II
Input current (leakage)
VCC- S•SV• VI "OVto6.SV.
All other pins .. 0 V to VCC
10
Output current (Ieekage)
ICC1
Read or write cYcle
current (see Note 3)
ICC2 Standby current
Average refresh current
ICC3 (RAS only or CBR)
(see Note 3)
·2_BK36C.eo
MIN
MAX
2.4
=
·248NBK38C.eG
'248NBK36C-70
MIN
MIN
MAX
2.4
MAX
UNIT
V
2.4
0.4
0.4
0.4
V
:I:~
:1:20
:1:20
tIA
:1:20
:1:20
:1:20
tIA
1070
920
820
mA
VIH .. 2.4 V (TTL).
after 1 memory cycle.
RAS and CAS high
40
40
40
mA
VIH .. Vcc - 0.2 V (CMOS).
after 1 memory cycle.
AAS and CAS high
20
20
20
mA
2100
1600
1600
mA
920
820
720
mA
VCC .. 5.SV•
Vo -OVtoVCC.
CAS high
VCC- S•SV•
Minimum cycle
Minimum cycle.
VCC-S.Sv,
RAS cycling.
CAS high (RAS only).
AAS low after CAS low (CBR)
Average page current
ICC4 (see Note 4)
VCC .. S.5V,
tpc .. Minimum.
RASlow.
CAS cycling
NOTES: 3. Measured with a maximum of one address change while RAS .. VIL
4. Measured with a maximum of one addre88 change while CAS = VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
.
PARAMETER
I
'124MBK36C
MIN
MAX
'248NBK38C
MIN
MAX
UNIT
eieA)
ClIR)
Input capacitance. AD-AS
50
100
pF
Input capacitance. RAS Inputs
35
CI(C)
Input capacitance. CAS Inputs
21
35
42
pF
CI(Wj
Co(DO)
Input capacitance. W
70
140
Output capacitance on DO pins
7
14
NOTE S: VCC equal to 5 V :I: 0.5 V and the bias on pins under test IS 0 V.
~1ExAs
INSTRUMENTS
~ OFFICE BOX 1443 • HOUSTON. lEXAS 77261-1443
pF
pF
pF
TM124MBK36C, TM124MBK36S 1048576 BY 36-BIT
TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT
DYNAMIC RAM MODULE
SMMS138B - MARCH 1992 - REVISED JUNE 1995
awltchlng characteristics over recommended ranges of supply voltage and operating free-alr
temperature
'124MBK38c-ao '124MBK38C-70 '124MBK38C-80
'248NBK38c-ao '248NBK38C-70 '248NBK38C-80
PARAMETER
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
tcAC
tAA
Access time from CAS low
15
18
20
ns
AccBSB time from column-address
30
35
ns
tRAC
Access time from RAS low
tePA
Access time from column precharge
CAS to output In low Z
Output disable time after CAS high (see Note 6)
60
35
70
40
40
80
45
ns
ns
20
ns
teLZ
0
0
0
0
toFF
NOTE 6: toFF Is specified when the output Is no longer driven.
15
0
18
0
ns
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature
'124MBK38C-60
'248NBK36C-60
MIN
'124MBK38C-70
'248NBK38C-70
MAX
MIN
MAX
'124MBK38C-80
'248NBK38C-80
UNIT
tRC
Cycle time, random reed or write (see Note 7)
110
130
MIN
150
tRWC
tpc
Cycle time, read·write
130
153
175
Cycle time, page-mode read or write (see Nota 8)
40
tRASP
Pulse duration, page mode, RAS low
60
100000
70
tRAS
Pulse duration, nonpage mode, RAS low
60
10000
tCAS
ICp
Pulse duration, CAS low
15
10000
Pulse duration, CAS high
10
10
10
ns
IRP
Pulse duration, RAS high (precharge)
50
Pulse duration, write
15
60
15
ns
twP
40
15
IASC
Setup time, column address before CAS low
0
0
0
ns
ns
45
MAX
ns
ns
ns
50
100000
ns
60
10000
20
10000
ns
ns
100000
80
70
10000
18
10000
ns
tASR
Setup time, row address before RAS low
0
0
0
tos
Setup time, date
0
0
0
ns
tRCS
Setup time, read before CAS low
0
0
0
ns
tcwL
Satup time, W time before CAS high
15
18
tRWL
Setup time, W low before RAS high
15
18
20
20
.ns
twcs
Setup time, W low before CAS low
twSR
Satup time, W high (CBR refresh only)
ns
teAH
Hold time, column address after CAS low
10
15
15
ns
ns
ns
tOHR
Hold time, data after RAS low (see Note 9)
50
55
60
ns
tOH
tAR
Hold time, data
10
15
15
ns
Hold time, column address after RAS low (see Note 99)
50
55
60
5
5
5
ns
ns
10
10
10
ns
0
0
0
ns
0
0
ns
teLCH
Hold time, CAS low to CAS high
IRAH
Hold ·time, row address after RAS low
tRCH
Hold time, read after CAS high (see Nota 10)
0
0
0
10
10
10
Hold time, raad after RAS high (see Note 10)
0
tRRH
NOTES: 7. All cycles assume IT 5 ns.
8. To assure tpc min, tASC should be lI: 5 ns.
9. The minimum value is measured when tRCO is set to tRCO min as a reference.
10. Either tRRH or IRCH must be satisfied for a read cycle.
=
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-89
TM124MBK36C,TM124MBK36S 1048576 BY 36·BIT
TM248NBK36C, TM248NBK36S 2097152 BY 36·BIT
DYNAMIC RAM MODULE
SMMS138B-.MARCH 1992,.. REVISED JUNE '896
timing requirements over recommended ranges of supply voltage and operating fre....lr
temperature (continued)
'124MBK38C-80 '124MBK38C-70 '124MBK38c.ao
'248NBK36C-eo '248NBK38C-70 '248NBK38c.ao
MIN
MAX
MIN
MAX
MIN
twcH
Hold time, write after CAS low
15
15
15
twcR
Hold 1Ime, write after RAS low (see Note 9)
50
55
60
twHR
Hold 1Ime, Whigh (CBR refresh only)
tcHR
10
15
0
10
15
0
20
tcRP
Delay time, RAS low to 15M high (CBR refresh only)
Delay time, 15M high to RAS low
teaH
Delay time, RASIow to 15M high
60
70
60
teaR
IRA[)
Delay time, ~ low to RAS low (CBR refresh only)
Delay time, RAS low to column address (see Note 11)
10
15
tRAL
teAL'
Delay time, column address to RAS high
30
Delay time, column address to 15M high
30
10
15
35
35
IRCD
IRpc
Delay time, RAS low to ~ low (see Note 11)
20
Delay time, RAS high to c:AS low (CBR refresh only)
IRSH
tREF
Delay time, c:AS low to RAS high
0
15
IT
Transition 1Ime
30
20
45
2.
0
52
2
50
50
device symbolization (TM124MBK36C Illustrated)
00 00000000Do
-SS
YY • Year Code
MM
= Month Code
T •
Aasambly Site Code
-SS • Speed Code
NOTE: Location of symbolization may vary.
~1ExAs
6-90
INSTRUMENTS
POST OFFICE BOX 1443 • I;IOUSTON. lEXAS 77251-1443
20
0
20
18
NOTES: 9. The minimum value Is measured when IRCD 18 set to IRCD min as a reference.
10. Either IRRH or tRCH must be sa1lsfled for a read cycla.
11. The maximum value Is speclfled only to assure access 1Ime.
TM124MBK36C
10
15
40
YYMMT
2
"'
"'
"'
"'n8
na
40
40
0
18
18
Refresh time Interval
"'
"'
"'
10
35
UNIT
MAX
60
"'na
n8
n8
16
me
50
n8
TM124MBK36G, TM124MBK36V 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36G, TM248NBK36V 2097152 BY 36-BIT DYNAMIC RAM MODULE
• Presence Detect
• Performance Ranges:
• Organization
TM124MBK36G ••• 1 048 576 )( 36
TM248NBK36G ••• 2 097 152 )( 36
ACCESS ACCESS ACCESS READ
• Single 5-V Power Supply (~1 0% Tolerance)
• 72-Pln Slngl.ln-Une Memory Module
(SIMM) for Use With Socket
• Long Refresh Period
16 ms (1024 Cycles)
• All Inputs, Outputs, Clocks Fully TTL
Compatible
• 3-State Output
• Common CAS Control for Nine Common
Data-In and Data-Out Lines In Four Blocks
• Enhanced Page-Mode Operation With
CASx-Befor.RAS (CBR), RASx-Only, and
Hidden Refresh
TIME
TIME
OR
fAA
tcAc
WRrTE
(MAX)
30 n8
(MAX)
15 na
18 na
(MAX)
'124MBK36G-60 60 na
'124MBK36G-70 70 na
'124MBK36G-60 80 ns
'248NBK36G-60 60 n8
'248NBK38G-70 70 na
'248NBK38G-80 80 ns
• TM124MBK36G - Utilizes Two 16-Megablt
and Two 4-Megablt DRAMs In Plastic
Small-outllne J-Lead (SOJ) Packages
• TM248NBK36G - Utilizes Four 16-Megablt
and.Four 4-Megablt Dynamic RAMs In
Plastic Smail-Outline J-Lead (SOJ)
Packages
TIME
'RAC
35 n8
40 n8
30 n8
35 n8
40 na
20 na
15 na
18 na
20 na
CYCLE
(MIN)
110 na
130 na
150 ns
110 na
130 ns
150 ns
• Low Power Dissipation
• Operating Free-Air Temperature Range
O°C to 70°C
• Gold-Tabbed Versions Avallable: t
TM124MBK36G
TM248NBK36G
• lln-Lead (Solder) Tabbed Versions
Available:
TM124MBK36V
TM248NBK36V
description
TM124MBK36~
The TM124MBK36G is a 4M-byte dynamic random-access memory (DRAM) organized as four times
1048576)( 9 in a 72-pin SIMM. The SIMM is composed of two TMS418160DZ, 1 048 576)( 16-blt DRAMs, each
in a 42-lead plastic SOJ package and two TMS44460DJ, 1 048576)( 4-bit DRAMs, in a 24/26-lead plastic SOJ
package mounted on a substrate with decoupling capacitors. The TMS418160DZ and TMS44460DJ are
described in the TMS418160 and TMS44460 data sheets respectively. The TM124MBK36G SIMM is available
in the single-sided BK leadless module for use with sockets.
TM248NBK36G
The TM248NBK36G Is an 8M-byte DRAM organized as four times 2097152 x 9 In a 72-pln SIMM. The SIMM
Is composed of four TMS418160DZ, 1 048 576 x 16-bit DRAMs, each in a 42-lead plastiC SOJ package and
four TMS44460DJ, 1048576)( 4-blt DRAMs, each in a 24/26-lead plastiC SOJ package mounted on a substrate
with decoupling capacitors. The TMS418160DZ and TMS44460DJ are described in the TMS418160 and
TMS44460 data sheets, respectively. The TM248NBK36G SIMM is available in the double-sided BK leadless
module for use with sockets.
operation
The TM124MBK36G operates as two TMS418160DZs and two TMS44460DJs connected as shown in the
functional block diagram and Table 1. The TM248NBK36G operates as four TMS418160DZs and four
TMS44460DJs connected as shown in the functional block diagram and Table 1. The common I/O feature
dictates the use of early-write cycles to prevent contention on D and Q.
t Part numbers In this data sheet are for the gold-tabbed version; the Information applies to both gold-tabbed and solder-tabbed versions.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUStON. TEXAS 77251-1443
Copyright C 1995, Texas InslrUmenllllncorporated
8-91
TM124MBK38G, TM124MBK36V 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36G, TM248NBK36V 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS851A- MAY 1895 - REVISED JUNE 1895
BK SINGLE-IN-LINE MEMORY MODULEt
(TOP VIEW)
Vss c::::>
c::::>
c::::>
c::::>
c::::>
c::::>
c::::>
c::::>
DQ21 c::::>
Vee c::::>
NC c::::>
NJ c::::>
AI c::::>
AI c::::>
AI c::::>
A4 c::::>
AI c::::>
AI c::::>
NC c::::>
DQ4 c::::>
DQ22 c::::>
DQI c::::>
DQ28 c::::>
DQI c::::>
DQ24 c::::>
DQ7 c::::>
DQ2I c::::>
A7 c::::>
NC c::::>
Vee c::::>
AS c::::>
AS c::::>
iWi c::::>
RAS2 c::::>
DQ28 c::::>
DQI c::::>
2
8
4
DQ8I
Vss
CASO
CASi
CAii
~
FlABI
NC
W
NC
DQII
DQ27
DQl0
DQ28
DQl1
DQ28
DQ12
DQ80
DQ1S
DQ81
Vee
DQ32
DQ14
DQ88
DQ15
DQ34
DQ18
NC
POI
POI
P03
P04
NC
Vss
o
•
•
7
•
•
10
11
II
18
14
11
18
17
18
18
ao
21
22
28
24
21
28
27
28
28
so
31
32
aa
34
81
81
c::::> 37
c::::> 81
c::::> ..
c::::> 40
c::::> 41
c::::> 42
c::::> 48
c::::> 44
c::::> 41
c::::> 48
c::::> 47
c::::> 48
c::::> 48
c::::> 10
c::::> 51
c::::> 12
c::::> 18
c::::> 54
c::::> 15
c::::> 18
c::::> 17
c::::> 18
c::::> ..
c::::> 10
c::::> 81
c::::> 112
c::::> 83
c::::> 84
c::::> 85
c::::> 88
c::::> 17
c::::> 18
c::::> II
c::::> 70
c::::> 71
c::::> 72
,-------,
D
.!'!!!>__ I
,-------,
D
I
(TM248NBK38
l.. __
..J
(TM248NBK38
l.. __
P
.!".!>__ .J
PIN NOMENCLATURE
·1
NJ-AS
~-~
000-0035
NC
PD1- PD4
RASO-RAS3
VCC
VSS
iii
Address Inputs
Column-Address Strobe
Data InJData Out
No Connection
Presence Detects
Row-Address Strobe
5-VSupply
Ground
Write Enable
PRESENCE DETECT
SIGNAL
(PIN)
TM124MBK36G
PD2
(66)
P03
(69)
PD4
(70)
Vss
NC
80ns
VSS
Vss
NC
VSS
VSS
80ns
VSS
NC
VSS
NC
VSS
NC
70ne
NC
NC
80ne
NC
NC
80ns
TM248NBK36G
P01
(67)
70ns
tThe packages shown here ere not drawn to scale.
~1ExAs.
8-92
(SIDE VIEW)
1
DQO
DQ18
DQ1
DQll1
DQ2
DQ20
DQ8
DQ17
TM248NBK38G
TM124MBK38G
(SIDE VIEW)
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 'IEXA8 77251-1443
NC
VSS
NC
NC
VSS
NC
NC
TM124MBK36G, TM124MBK36V 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36G, TM248NBK36V 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS8S1A- MAY 1995 - REVISED JUNE 1995
Table 1. Connection Table
OATABLOCK
RASx
CASx
SIDE 1
SIDE2t
000-OQ7
008
RASO
RASO
RAS1
RAS1
CASO
OQ9-0Q18
0017
RASO
AASO
RAS1
RAS1
CAS1
CAS1
OQ18-0Q25
OQ28
RAS2
RAS3
RAS2
RAS3
~
CAS2
0027-0034
0035
RAS2
RAS2
RAS3
RAS3
CASO
CAS3
CAS3
t Side 2 applies to the TM248NBK36G only.
single In-line memory module and components
PC substrate: 1,27 :I:: 0,1 mm (0.05 inch) nominal thickness; 0.005 incMnch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124MBK36G and TM248NBK36G: Nickel plate and gold plate over copper
Contact area for TM124MBK36V and TM248NBK36V: Nickel plate and tin/lead over copper
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77251-1443
6-93
TM124MBK36G, TM124MBK36V 1048576 BY 36·BIT DYNAMIC RAM MODULE
TM248NBK36G,TM248NBK36V 2097152 BY 36·BIT DYNAMIC RAM MODULE
SMMS851A-MAY 1896-REVlSEDJUNE 1995
functional block diagram [TM124MBK36G and TM248NBK36G. side 1]
10
AD-AS
RASO
RAS2
W
018-025
00-07
CASO
~
09-016
CAS2
CAS3
027-034
0Q28
OQ35
OQ8
OQ17
CASO
NIC
NIC
CAS2
CAS3
NlC
NlC
~
NIC
NlC
functional block diagram [TM248NBK36G. side 2]
AD-AS
RAS1
10
RAS3
W
10
027-035
09-016
~
CASO
00-07
CAS3
CAS2
OQ8
OQ17
CASO
CAS1
NlC
NlC
CASO
CAS1
N/C
NlC
~1ExAs
6-94
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, 'TEXAS 77251-1443
018-025
1M .. 4
OQ1
AO-AS
OQ2
RAS
OQ3
W
0Q4
CAS1
CAS2
CAS3
CAS4
0Q26
OQ35
NlC
NlC
TM124MBK36G, TM124MBK36V 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36G, TM248NBK36V 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS8S1A- MAY 1995 - REVISED JUNE 1995
absolute maximum ratings over operating free-alr temperature range (unless otherwIse noted)t
Supply voltage range, Vee (see Note 1) .............................................. - 1 V to 7 V
Voltage range on any pin (see Note 1) •...•.•.•.•.•.•.•............•....•••.•.•.•.•.•.• - 1 V to 7 V
Short-circuit output current •..•.•••..•.•••••.•.••.......................•••••••••••••••..•• 50 mA
Power dissipation
TM124MBK36G, TM124MBK36V .••.••••.•.•••.•••••.••.•...•••.•.•••••• 4 W
TM248NBK36G, TM248NBK36V •.....•.....•..•.••..•.•.•.•.••.•••••••• 8 W
Operating free-air temperature range, TA .............................................. ooe to 70°C
Storage temperature range, Tstg .................................................. - 55°C to 125°C
t Streases beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These ere stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" Is not
Implied. Exposura to absolute-maximum-rated conditions for extended periods may affect device raiIabUIty.
NOTE 1: All voltage values ere with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
UNIT
VIH
High-level Input voltage
2.4
6.5
V
VIL
Low-level input voltage (888 Note 2)
-1
0.6
V
·C
V
Operating free-air temperatura
0
70
TA
..
NOTE 2: The algebraic convention. where the mora negative 0- positive) limit Is designated as minimum. Is used for logic-voltage levels only•
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output
voltage
IOH=-5mA
VOL
Low-level output
voltage
IOL-4.2mA
II
Input current Oeakage)
10
ICC1
·124MBK38G·60 '124MBK36G· 70 '124MBK38G·80
MIN
MAX
2.4
MIN
MAX
MIN
MAX
V
2.4
2.4
UNIT
0.4
0.4
0.4
V
VCC= 5.5V. VI =OVto6.5V.
All other pins ., 0 V to VCC
:1:10
:1:10
:1:10
pA
Output current
Osakage)
VCC=5.5V.
Vo -OVtoVCC.
CASxhlgh
:1:10
:1:10
:1:10
pA
Read- or wrIte-cycle
current
VCC=5.5V. Minimum cycle
390
340
300
rnA
VIH = 2.4 V (TTL).
After 1 mem cycle.
RASx and
x high
8
8
8
rnA
VIH .. Vee - 0.2 V (CMOS).
After 1 memory cycle.
RASx and CASx high
4
4
4
mA
ICC2 Standby current
refresh current
Icca f = e
only or CBR)
VCC = 5.5 V. .Minimum cycle.
RASx cycling.
CASx high (RASx only).
RASx low after CASx low (CBR)
390
340
300
mA
ICC4 Average page current
VCC=5.5V. tpC .. MIN.
CASxcycling
RASxlow.
320
280
240
mA
~1ExAs
.
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS·77251-1443
TM124MBK36G, TM124MBK36V 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36G, TM248NBK36V 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS651A-MAY 1895 - REVISED JUNE 1895
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)t
PARAMETER
TEST cONDmONS
High-level output
VOH voltage
10H--SrnA
Low-level output
voltage
IOL .. 4.2mA
VOL
Input current
'248NBK36G-60 '248NBK36G-70 '248NBK360-60
MIN
MAX
MIN
MAX
MIN
MAX
2.4
2.4
2.4
UNIT
V
0.4
0.4
0.4
V
~eakage)
VI-OV106.SV,
VCC- S•SV,
All other pins =0 V 10 VCC
.. 10
.. 10
.. 10
lolA
10
Output current
6eakage)
VCC- S•SV,
Vo-OVlOVcC, ~hlgh
.. 20
.. 20
:1:20
lolA
ICC1
Read- orwrlte-cycle
current (see Note 3)
VCC- S•SV,
398
348
308
rnA
16
16
16
mA
6
6
6
mA
780
680
800
mA
248
rnA
II
ICC2 Standby current
Averege refresh
Ices current (AM only or
CBR) (see Note 3)
Minimum cycle
VIH .. 2.4 V (TTL),
After 1 memory cycle.
RAS and CAS high
VIH - VCC -0.2 V (CMOS),
After 1 memory cycle.
RAS and CAS high
Minimum cycle,
VCC-S.SV,
RAS cycling,
CAS high (AAS only),
RAS low after CAS low (CBR)
Averege page
tpC-MIN,
VCC" S,SV,
268
326
1CC4 current
~cycling
RASlow.
(see Note 4)
t For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions.
NOTES: 3. Measured with a maximum of one address change whlls RAS .. VIL
4. Measured with a maximum of one address change while ~ .. VIH
capacitance over recommended ranges of supply voltage and. operating free-alr temperature,
f = 1 MHz (see Note 5)
PARAMETER
'124MBK36G
MIN MAX
'248NBK36G
MIN MAX
40
14
26
56
14
CI(A)
Input capacltancs, address Inputs
20
CI(R)
Input capacltanos, RAS Inputs
14
CI(C)
Input capacltancs, CAS Inputs
14
Inputcapacltanos,VV
CUWI
COIDOI Output capacltanos on DO pins
NOTE S: VCC S V :I: O.S V, and the bias on pins undsr tsst 18 0 V.
28
7
=
~1ExAs
.
INSTRUMENTS
6-96
POST OFFICE BOX 1443 • HOUSTON. TEXAS T12111-1443
UNIT
pF
pF
pF
pF
pF
TM124MBK36G, TM124MBK36V 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36G, TM248NBK36V 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS851A-MAY 1895-REV!SEDJUNE 1886
switching charact.rlstlcs ov.r recomm.nded rang.s of supply voltag. and op.ratlng fr....lr
t.mperature
'124MBK36G-80 '124MBK36G-70
'248NBK36G-80 '248NBK36G-70
PARAMETER
MIN
tM
leAc
lRAc
tePA
teLZ
toH
toFF
Accesa time from column address
Accesa time from CAS low
Accesa time from RAS low
Accesa time from column precharge
CAS to output In Jow-Impedence state
Output disable time from start of CAS high
Output dl8able time after CAS high (see Note 6)
MAX
MIN
MAX
MIN
35
15
18
40
20
60
70
80
35
40
0
3
0
45
0
3
15
3
18
0
UNIT
MAX
30
0
0
'124MBK38G-80
'248NBK36G-80
20
na
na
na
na
na
na
118
NOTE 8: toFF is apecllied when the output 18 no longer driven.
timing requlrem.nts ov.r recomm.nd.d rang.s of supply voltag. and operating tree-alr
t.mperature
'124MBK36G-80 '124MBK36G-70
'248NBK36G-60 '248NBK36G-70
MAX
MIN
MIN
MAX
'124MBK38G-80
'24INBK38G-80
MIN
UNIT
MAX
tRC
tpc
Cycle time, random read or write (see Note 7)
Cycle time, page-mode read or write (888 Notes 7 end 8)
lRASp
Pulse duration, page mode, AAS low
Pulse duretion, nonpage mode, AAS low
60
100000
70
100000
80
100000
80
10000
70
10000
80
10000
na
na
na
na
Pulse duretion, CAS low
15
10000
18
10000
20
10000
118
Pulse duration, CAS high (precharge)
10
10
10
118
lAp
Pulse duration, AAS high (precharge)
40
50
60
118
twP
Pulse duration, IN low
Setup time, column address before CAS low
10
10
10
118
0
0
0
118
0
0
0
na
0
0
0
118
lRAS
teAS
tep
tASC
tASR
tos
110
130
150
40
45
50
Setup time, row address before RAS low
Setup time, dele before CAS low
Setup time, 'iii high before CAS low
Setup time, W low before CAS high
0
0
0
118
15
18
Setup time, W low before RAS high
Setup time, W low before CAS low
Setup time, W high before RAS low (CeR refresh only)
15
18
20
20
118
0
0
0
118
10
10
10
118
Hold time, column address after CAS low
10
15
15
Hold time, AAS high from CAS precharge
Hold time, dele after CAS low
35
40
45
na
na
10
15
15
118
10
10
10
n8
tRCH
Hold time, row address after RAS low
Hold time, IN high after CAS high (see Note 9)
0
0
0
tRRH
Hold time, W high after RAS high (see Note 9)
0
0
0
na
na
lAcs
tcwL
lRWL
twcs
twRP
leAH
lAHCP
toH
tRAH
118
twcH
Hold time, 'iii low after OM low
10
15
15
118
twRH
Hold time, IN high after AAS low (CeR refresh only)
10
10
10
118
NOTES: 7. All cycles assume tr • 6 118.
8. To assure lPC mln,lAsc should be a tep.
9. Either tRRH or lACH must be satisfied for a read cycle.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
6-97
TM124MBK36G, TM124MBK36V 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36G, TM248NBK36V 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMSS51A- MAY 1996 - REVISED JUNE 1895
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'124MBI<36G·80 '124MBK36G·70 '124MBI<36G·80
'248NBK36G·80 '248NBK36G·70 '248NBI<36G·80
MIN
MAX
MIN
MAX
MIN
MAX
!CHR
!CRP
teSH
!CSR
tRAD
tRAl
teAL
tRCD
tRPC
m
low to CAS high (CBR refresh only)
low
Delay time,
low to CAS high
Delay time, CAS low to
low (CBR refresh only)
Delay time,
low to column address (see Note 10)
Delay time,
Delay time, CAS high to
m
m
m
m
m
10
10
10
5
5
60.
5
70
80
5
15
5
15
5
15
Delay tim~, column address to
high
Delay time, column address to CAS high
30
30
Delay time, RAS low to CAS low (see Note 10)
20
Delay time, FiAS high to CAS low (CBR only)
Delay time, CAS low to FiAS high
Refresh time Interval
0
15
lASH
lAEF
Transition time
1,NOTE 10: The maximum value Is specified only to aaaura acceaa time.
30
35
35
20
3
o[:::::~::::]
YY • Year Code
MM .. Month Code
T
Assembly Site Code
-ss .. Speed Code
=
NOTE: Location of symbolization may vary.
~TEXAS
INSTRUMENTS
8-98
POST OFFICE lOX 1_ • HOUSTON. TEXAS 77251-1_
40
60
ns
ns
18
ms
30
ns
na
20
30
0
3
ns
ns
ns
0
device symbolization (TM124MBK36G lilustrated)
-SS
20
18
3
ns
ns
40
52
0
18
18
30
ns
ns
40
35
45
UNIT
TM497MBK36A, TM497MBK36Q
4194304 BY 36-BIT
DYNAMIC RAM MODULE
SMMS446C-
• Organization ••• 4 194 304 x 36
• Single SOV Power Supply (:t10% Tolerance)
• 72-Pln Slngle-ln-Llne Memory Module
(SIMM) for Use With Sockets
• Utilizes Eight 16-Megablt DRAMs In Plastic
Smail-Outline J-Lead (SOJ) Packages and
Four 4-Megablt DRAMs In Plastic
Smail-Outline J-Lead (SOJ) Packages
• Long Refresh Period
32 ms (2048 Cycles)t
• All Inputs, Outputs, Clocks Fully TTL
Compatible
• Common CAS Control for Nine Common
Data-In and Data-Out Unes In Four Blocks
• Separate RAS Control for Eighteen Data-In
and Data-Out Lines In l\No Blocks
•
• Performance Ranges:
ACCESS
'497MBK36A-60
'497MBK36A-70
'497MBK36A-60
ACCESS ACCESS READ
TIME
TIME
TIME
OR
'RAc
tcAC
lAA
(MAX)
60 ns
70 ns
80 ns
(MAX)
15 ns
1,8 ns
20 ns
(MAX)
30 ns
35 ns
40 ns
WRITE
CYCLE
(MIN)
110 ns
130 ns
150 ns
• Low Power Dissipation
• Operating Free-Air Temperature Range
O·Cto 70·C
• Presence Detect
• Gold-Tabbed Version Avallable:*
TM497MBK36A
• Tin-lead (Solder) Tabbed Version
Available: TM497MBK36Q
3-State Output
description
The TM497MBK36A is a 16M-byte dynamic random-access memory (DRAM) organized as four times
4194304 x 9 (bit 9 is generally used for parity) in a 72-pin leadless single-in-line memory module (SIMM). The
SIMM is composed of eightTMS417400DJ, 4194304 x 4-bit DRAMs, each in 24/26-lead plastic SOJ packages,
and four TMS441 OODJ, 4194304 x 1-bit DRAMs, each in 20/26-lead plastic SOJ packages mounted on a
substrate with decoupling capacitors. Each TMS417400DJ and TMS441 OODJ is described In the TMS417400
and TMS441 00 data sheets (respectively).
The TM497MBK36A is available in a double.sided BK lead less module for use with sockets. The
TM497MBK36A features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for operation
from O·C to 70·C.
operation
The TM497MBK36A operates as eight TMS417400DJs and four TMS44100DJs connected as shown in the
functional block diagram and Table 1. Refer to the TMS417400 and TMS44100 data sheets for details of
operation. The common I/O feature dictates the use of early write cycles to prevent contention on 0 and Q.
refresh
The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with
, RAS in order to retain, data. Address line A10 must be used as most significant refresh address line (lowest
frequency) to assure correct refresh for both TMS417400 and TMS44100. AO-A9 address lines must be
refreshed every 16 ms as required by the TMS441 00 DRAM. CAS can remain high during the refresh sequence
to conserve power.
power up
To achieve proper operation, an initial pause of 200 J4S followed by a minimum of eight initialization cycles is
required after full Vee level Is achieved. These eight initialization cycles need to include at least one refresh
[RAS-only or CAS-before-RAS (CBR» cycle.
t AD-AS address lines must be refreshed every 16 ms.
t Part numbers In this data sheet refer only to the gold-tabbed version; the Information applies to both gold-tabbed and solder-tabbed versions.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
Copyright C1995. llIxas Instruments InCOlPoreted
6-99
TM497MBK36A, TM497MBK36Q
4194304 BY 36-BIT .
DYNAMIC RANI MODULE
SMMS448C- DECEMBER 1882- REVISED JUNE 18911
BK SINGLE-IN-LlNI! PACKAGE
(TOP VIEW)
Vss
DQO
DQ18
DQ1
DQl.
DQ2
D020
DQ8
DQ21
Vee
NO
NJ
Al
AI
AI
A4
AI
AI
Al0
DQ4
DQ22
DOl
DCI23
DOl
DQ24
DQ7
DQ2I
A7
NO
Vee
AI
AI
NO
RA82
DQ2I
DOl
c:::> 1
c:::> 2
c:::> a
c:::> 4
c:::> I
c:::> 8
C:::>' 7
c:::> 8
c:::> •
c:::> 10
c:::> 11
c:::> 12
c:::> 13
c:::> 14
c:::> 11
c:::> 1.
c:::> 17
c:::> 18
c:::> 1.
c:::> 20
c:::> 21
c:::> 22
c:::> 23
c:::> 24
c:::> 21
c:::> 21
c:::> 27
c:::> 21
c:::> 21
c:::> 3D
c:::> 11
c:::> 32
c:::> 33
c:::> 34
c:::> 31
c:::> 31
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
CASl c:::>
AASO c:::>
NO c:::>
NO c:::>
W c:::>
NO c:::>
DQI c:::>
DQ27 c:::>
DQl0 c:::>
DQ2I c:::>
DQll c:::>
DQ2I c:::>
DQ12 c:::>
DQ80 c:::>
DQl1 c:::>
DQ81 c:::>
Vee c:::>
DQ32 c:::>
DQ14 c:::>
DQ33 c:::>
DQll c:::>
DQ34 c:::>
DQ1. c:::>
NO c:::>
POl c:::>
POI c:::>
POI c:::>
PD4 c:::>
NO c:::>
Vss c:::>
DQ17
DQ8I
Vss
5
37
31
31
40
41
42
43
44
41
48
47
48
48
10
11
12
13
14
18
II
17
18
III
80
81
12
13
14
II
II
17
II
II
70
71
72
(SIDE VIEW)
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
)
PIN NOMENCLATURE
Address Inputs
CASO-C5AS3'
Column-Address Strobe
000-007, DQ9-0Q18,
Oata InJOata Out
0018-0025,0027-0034
OQB, 0017, 0026, OQ35
Parity
No Connection
NC
P01-P04
Pressnce Oetacls
RASO,RAS2
Row-Address Strobe
5-VSupply
VCC
Ground
Vss
Write Enable
iii
AO-A10
PRESENCE DETECT
SIGNAL
(PIN)
TM497MBK36A
PD1
(87)
PD2
PD3
(88)
(88)
(70)
80ns
Vss
NC
NC
70ns
Vss
Vss
NC
NC
Vss
Vss
NC
NC
80ns
~1ExAs
~100
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON, 'T1!XAS 77211-1443
NC
PD4
TM497MBK36A, TM497MBK36Q
4194304 BY 36-BIT
DYNAMIC RAM MODULE
SMMS448C- DECEMBER 1892 - REVISED JUNE 1985
Table 1. Connection Table
RASx
CASi
DQO-D07
008
~
~
Oae-D01S
0017
~
eAS1
0018-0025
0026
m2
~
DQ27-0034
0035
RAS2
CAS3
DATA BLOCK
singie-in-line memory module and components
PC substrate: 1,27:1: 0,1 mm (0.05 inch) nominal thickness; 0.005 InchJlnch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM497MBK36A: Nickel plate and gold plate over copper
Contact area for TM497MBK36Q: Nickel plate and tin-lead over copper
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77261-1443
6-101 -
!
I
is!~i!
functional block diagram
fa
fZ~oIiIi
?Eg~
lite") m
AO-A10 11
RASO
f;l::ll~~
3:» w
lI!i:fd~
JJ
.• _ .
ii:!! -4
10-4
i:
C
.,.
~c: !I
fijr'"
i:
21 m m
RAS2
W
CASO
4Mx4
AO-A10
RAS
~
CAS
....
~W
~
~
...
~~~
"
!.
001- . . . OQO-
0Q4
~
~-
lir
g~
003
.J:.
OE
.001-
0Q4
~.!.
±".....
.... DQ7
~- .J:.
r..-
0013OQ16
.J:.
I
1
0
DQ21
J-
I
0017
~
-:;:::: W
0Q1- . . . DQ22DQ25
DQ4
Q
...
zm
E
DQ27DQ30
4Mx4
~ AO-A10
RAS
..... CAS
OE
ID
OE
OQ1,...
DQ4
4Mx4
AO-A10
RAS
~W
CAS
Q
~0018-
"
..r-
CAS
OE
001-
-
0Q4
4Mx1
AO-A10
~ RAS
DQ8
DQ4
...
~ RAS
~W
CAS
Q
001-
~
CAS
OE
~W
CAS
.... OE
~W
4Mx1
AO-A10
~ RAS
I
-b
W
0Q4
~W
CAS
0
OE
001-
4Mx1
AO-A10
C
~ CAS
AO-A10
~ RAS
~..... CAS
W
4Mx4
~ AO-A10
RAS
~ WRAS
4Mx4
4Mx4
~
4Mx4
AO-A10
001- ~DQ9DQ4
0012
~ AO-A10
RAS
.....
4Mx4
AO-A10
RAS
~ W
CAS
OE
CAS3-
CAS2-
CAS1-
...
'0311034
'4Mx1
~ AO..,.A10
RAS
~..... W
I
0Q26
CAS
I
0
0Q35
Qr
i
W
"0)
0
TM497MBK36A, TM497MBK36Q
4194304 BY 36-BIT
DYNAMIC RAM MODULE
SMMS446C - DECEMBER 1892 - REVISED JUNE 1986
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. - 1 V to 7 V
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Short-circuit output current ....................•......................••...•............... 50 rnA
Power dissipation .....•.......••..•......•....•..•......•.......•...•.•..•................ 12 W
Operating free-air temperature range, TA .............................................. O·C to 70·C
Storage temperature range, Tstg .................................................. - SS·C to 12S·C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are strese ratings only. and
functional operation of the device at these or any other conditione beyond those indicated under "recommended operating conditione" Is not
implied. Expoeure to absolute-maximum-rsted conditione for extended periods may affect device reliability.
NOTE 1: All voltage valuae are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
Vee
Supply voltage
4.5
5
5.5
UNIT
V
VIH
High-level input voltage
8.5
V
VIL
Low-level input voltage (see Note 2)
2.4
-1
0.8
V
Operating frea-air temperalure
"C
0
70
TA
NOTE 2: The algebraic convention. where the more negative Oess positive) limit is designated es minimum. Is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise· noted)
.
PARAMETER
TEST CONDrTlONS
VOH
High-level output
voltage
IOH=-5mA
VOL
Low-level output
voltage
10L= 4.2 mA
II
Input current
(leakage)
Vee = 5.5V.
VI = OVto 8.5 V.
All other pins .. 0 V to Vee
10
Output current
(leakage)
~=5.5V,
ICCl
Reed- or wrlte-cycle
current (see Note 3)
IC02 Standby current
'497MBK36A-60
MIN
'497MBK36A-70
MAX
2.4
MIN
MAX
2.4
'497MBK36A-80
MIN
MAX
2.4
UNIT·
V
0.4
V
120
jU\
:1:10
:1:10
jU\
1300
1180
1040
mA
VIH = 2.4 V (TTL).
After 1 memory cycle.
RAS and CAS high
24
24
24
mA
VIH .. VCC - 0.2 V (CMOS).
After 1 memory cycle.
RAS and CAS high
12
12
12
mA
1300
1180
1040
mA
920
800
880
mA
. Vo =OVtoVCC.
CAS high
VCC=5.5V•. Minimum cycle
Average refresh
current (RAS only
ICC3 orCBR)
(see Note 3)
Minimum cycle.
VCC= 5.5V.
RAScycling,
CAS high (RAS only);
RAS low after CAS low (CBR)
Average page
ICC4 current (see Note 4)
YQQ-5.5V.
RASlow,
0.4
0.4
:1:120
:1:120
:1:10
~=MIN
AS cycling
:I:
NOTES: 3. Measured with a m8Xlmum of one. address change while RAS = VIL
4. Measured with a maximum of one address change while CAS =VIH
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8,103
TM497MBK36A, TM497MBK36Q
4194304 BY 36-BIT
DYNAMIC, RAM MODULE
SMMS448C,.. DECEMBER 1992-REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature,
.
f 1 MHz (s.. Note 5)
=
MIN
PARAMETER
MAX
UNIT
CIIAl
CI(C)
Input capacitance, address Inputs
80
pF
Input capacitance, ~ Inputs
21
pF
CIIAI
Input capacitance, AAS Inputs
42
pF
CUW)
Inp\lt capacitance, writtHlnable input
84
pF
Co
I DQplns
Output capacitance
7
I Parity pins
12
pF
NOTE 5: Vee. 5 V :I: 0.5 V, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature
PARAMETER
'497MBK38A-80
MAX
MIN
'497MBK38A-70
MIN
MAX
'497MBK38A-80
MIN
MAX
UNIT
tM
Access time from column address
30
35
40
ns
teAC
Access time from CAS low
15
1B
20
ns
tePA
tRAC
Access time from column precharge
Access time from AAS low
35
40
45
80
70
80
ns
ns
tcLz
~ to output In Iow-Impadance state
0
0
0
toH
Output disable time, start of CAS high
3
3
3
toFF Output disable time after ~ high (see Note 6)
NOTE 6: toFF is specified when the output Is no longer driven.
0
15
0
18
0
ns
ns
20
ns
timing requirements over 'recommended ranges of supply voltage and operating free-air
temperature
'497MBK38A-80
Cycle time, random read or write (see Note 7)
MIN
110
MAX
'497MBK36A-70
MIN
MAX
'497MBK38A-80
MIN
MAX
UNIT
tRc
tpc
130
150
ns
Cycle time, page-mode read or write (see Notes 7 and 8)
40
45
50
ns
'RASP
Pulse duration, page-mode, RAS low
60 100000
70 100000
80 100000
ns
IRAS
Pulse duration, nonpage-mode, RAS low
80
10000
70
10000
80
10000
ns
toAS
top
Pulse duration, CAS low
15
10000
18
10000
20
10000
ns
Pulse dUration, CAS high
10
10
10
ns
tRp
Pulse duration, RAS high (precharge)
40
50
80
ns
twP
Pulse duration, Wlow
10
10
10
ns
tASC
Setup time, column address before CAS low
0
0
0
ns
tASR
Setup time, row address before RAS low
0
0
0
ns
tos
Setup time, data before CAS low
0
0
0
ns
tACS
Setup time, Whigh before CAS low
0
0
0
ns
ns
tcwL
Setup time, W low before CAS high
15
18
20
tAWL
Setup time, Wlow before AAS high
15
1B
20
ns
twos
Setup time, W low before CAS low
0
0
0
ns
10
10
10
ns
Setup time, W high before RAS low (CBA refresh only)
twRP
NOTES: 7. All cycles assume IT 5 ns.
B. To assure tpC min, tASC should be .. top.
=
6-104
~I
Z TEXAS "
NSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lCXAS 77251-1443
TM497MBK36A, TM497MBK36Q
4194304 BY 36-BIT
DYNAMIC RAM MODULE
SMMS448C - DECEMBER 1992 - REVISED JUNE 1896
timing requirements over recommended ranges of supply voltage and operating tree-alr
temperature (continued)
'497MBK38A-60 '497MBK38A-70 '497MBK38A-60
MIN
MIN
MAX
MIN
MAX
MAX
UNrr
teAH
tRHCP
tDH
Hold time, column address after CAS low
15
15
15
na
Hold time, RAS high from CAS precharge
35
15
45
15
n8
Hold time, data after CAS low
40
15
tRAH
Hold time, row address after RAS low
10
10
10
tRCH
Hold time, W high after CAS high (see Note 9)
0
0
0
n8
tRRH
Hold time, W high after RAS high (see Note 9)
0
0
0
twCH
Hold time, W low after CAS low
10
15
15
na
na
na
na
twRH
Hold time, W high after RAS low (CBR refresh only)
10
10
10
n8
teHR
Delay time, RAS low to CAS high (CBR refresh only)
10
10
10
n8
teRP
Delay time, CAS high to RAS low
5
5
5
ns
teSH
Delay time, RAS low to CAS high
60
70
60
tcsR
tRAO
Delay time, CAS low to RAS low (CBR refresh only)
5
15
5
Delay time, RAS low to column address (see Note 10)
5
15
tRAL
Delay time, column address to RAS high
30
teAl
tRCD
tRPC
Delay time, column address to CAS high
30
Delay time, RAS low to CAS low (see Note 10)
20
Delay time, RAS high to CAS low
0
lASH
tREF
Delay time, CAS low to RAS high
15
na
na
na
ns
na
na
na
ns
tr
Transition time
Refresh time interval
30
15
40
52
20
35
45
20
20
32
3
60
0
18
30
40
40
0
32
3
35
35
30
3
32
m8
30
na
NOTES: 9. Either tRRH or lACH must be satisfied for a read cycle.
10. The maximum value is specified only to assure access time.
device symbolization
00000 00000
YV = Year Code
MM .. Month Code
T = Assembly Site Code
-SS
Speed Code
=
NOTE: location of symbolization may vary.
-!I1TEXAS
INSTRUMENTS
POST OFFICE sox 1443· HOUSTON. TEXAS 77251-1443
8-105
TM497MBK36A, TM497MBK36Q
4194304 BY 36-BIT
DYNAMIC RAM MODULE
SMMS446C- DECEMBER 1982- REVISED JUNE 1985
~1ExAs
8-106
INSTRUMENTS
POST OFFICE BOX 1~ • HOUSTON, 'IeXAS 77251-1~
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT
TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
• OrganIzatIon
TM497MBM36A ••• 4194304 x 36
TM893NBM36A ••• 8388608 x 36
• Present Detect
• Operating Free-A1r-Temperature Range
O°C to 70°C
• Single 5-V Power Supply (:t:10% Tolerance)
• Performance Ranges:
ACCESS
nUE
iRAC
• 72-Pln Leadless Single-in-Une Memory
Module (SIMM) for Use With Sockets
• TM497MBM36A- Utilizes Eight 16-Megablt
and Four 4-Megablt DRAMs In Plastic
Smail-Outline J-Lead (SOJ) Packages
• TM893NBM36A - Utilizes Sixteen
16-Megablt and Eight 4-Megablt DRAMs In
Plastic Smail-Outline J-Lead (SOJ)
Packages
• Long Refresh Period
32 ms (2048 Cycles)
• All Inputs, Outputs, Clocks Fully TTL
Compatible
• 308tate Output
• Common CAS Control for Nine Common
Data-In and Data-Out Unesln Four Blocks
'497MBM36A-eo
'497MBM36A-70
'497MBM36A-eo
'893NBM36A-eo
'893NBM36A-70
'893NBM36A-eo
(MAX)
60 n8
70 n8
60 ns
60 ns
70 ns
60 ns
ACCESS ACCESS READ
nUE
nME
OR
1M
!cAC WRITE
CYCLE
(MAX)
(MAX)
(MIN)
30 n8
15 ns 110 ns
35 n8
18 ns 130 n8
40 n8
20 n8 150 n8
30 ns
15 ns
110 ns
35 nS
18 ns 130 ns
40 n8
20 ns 150 ns
• Gold-Tabbed VersIons Avallable: t
TM497MBM36A
TM893NBM36A
• nn-Lead (Solder) Tabbed Versions
Available:
TM497MBM36Q
TM893NBM36Q
• Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
description
TM497MBM36A
The TM497MBM36A Is a 16-megabyte dynamic random-access memory (DRAM) organized as four times
4194304 x 9 (bit 9 is generally used for parity) in a 72-pln. leadless single-In-line memory module (SIMM). The
SIMM is composed of eight TMS417400DJ. 4194304 x 4-bit DRAMs. each in 24/26-lead plastic small-outilne
J-Iead (SOJ) packages and four TMS44100DJ. 4194304 x 1-bit DRAMs. each in 20/26-lead plastic
small-outline J-Iead (SOJ) packages mounted on a substrate with decoupling capacitors. The TMS417400DJ
and TMS44100DJ are described in the TMS417400 and TMS44100 data sheets. respectively. The
TM497MBM36A SIMM is available in the Single-sided. BM leadless module for use with sockets.
TM893NBM36A
The TM893NBM36A is a 32-megabyte DRAM organized as four times 8388608 x 9 (bit 9 is generally used for
parity) in a 72-pin. leadless single-in-line memory module (SIMM). The SIMM is composed of sixteen
TMS417400DJ. 4194304 x 4-bit DRAMs. each in 24/26-lead plastic small-outline J-Iead (SOJ) packages and
eight TMS441 OODJ. 4194304 x 1-bit DRAMs. each in 2O/26-lead plastic small-outline J-Iead (SOJ) packages
mounted on a substrate with decoupling capacitors. The TMS417400DJ and TMS441 OODJ are described in the
TMS417400 and TMS44100 data sheets. respectively. The TM893NBM36A SIMM is available in the
double-sided. BM leadless module for use with sockets.
operation
TM497MBM36A
The TM497MBM36A operates as eight TMS417400DJs and four TMS44100DJs connected as shown in the
functional block diagram and Table 1. The common I/O feature dictates the use of early-write cycles to prevent
contention on D and Q.
t Part numbers In this data sheet refer only to the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
PROIlUCI1OII DATA _ _ .......... 01 DUIIIIcdGn _
_ _ .. _ _ _ ",,1ho_0I1'IxI.__
_Wlll'llllJ._"'-ng_noI--ay1naludo
fllllngold
__
'I liEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
Copyright 0 1995. T8lCII8 Instruments Incorporeted
6-107
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT
TM893NBM36A,TM893NBM36Q 8388.608 BY 36-BIT
DYNAMIC RANDOM·ACCESSMEMORY MODULES
SMMS853A- MAY 1996 - REVlSEDJUNE 1996
TM893NBM36A
The TM893NBM36A operates as sixteen TMS417400DJs and eight TMS441 OODJs connected as shown in the
functional block diagram and Table 1. The common I/O feature dictates the use of early-write cycles to prevent
contention on D and Q.
refresh
The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with
RAS in order to retain data. Address line A10 must be used as ~e most significant refresh address line (lowest
frequency) to ensure correct refresh for both TMS417400and TMS44100. Address lines AO-A9 must be
refreshed every 16 ms as required by the TMS441 00 DRAM. To conserve power, CAS can remain high during
the refresh sequence.
power up
To achieve proper operation, an initial pause of 200 !AS followed by a minimum of eight initialization cycles is
required after full Vee level is achieved. These eight initialization cycles must include at least one refresh
(RAS-only or CBR-refresh) Cycle.
Table 1. Connection Table
DATA BLOCK
RASX
CASX
SIDE 1
SIDE2t
DaO-OQ7
Da8
RASO
RAS1
CASO
OQ9-0Q18
OQ17
RASO
RAS1
CAS1
OQ18-0Q25
OQ26
RAS2
RAS3
~
OQ27-0Q34
OQ35
RAS2
RAS3
CAS3
t Side 2 applies to the TM893NBM38A.
singie-in-line-memory module and components
PC substrate: 1, 27 :t 0,1 mm (0.05 inch) nominal thickness; inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM497MBM36A and TM893NBM36A: Nickel plate and gold plate over copper
Contact area for TM497MBM36Q and TM893NBM36Q: Nickel plate and tin/lead over copper
-!!11ExAs
INSTRUMENTS
6-108
POST OFFICE sox 1443· HOUSTON. TEXAS n2S1-1443
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT
TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653A- MAY 1995 - REVISED JUNE 1995
TM497MBM36A
(SIDE VIEW)
BM SINGLE-IN-UNE PACKAGE
(TOP VIEW)
Vas c:::>
c:::>
c:::>
c:::>
c:::>
DQ2 c:::>
DQ20 c:::>
DQ3 c:::>
DQ21 c:::>
vee c:::>
NO
N) c:::>
c:::>
Al c:::>
I« c:::>
loIS c:::>
A4 c:::>
NIl c:::>
AI c:::>
Al0 c:::>
DQ4 c:::>
D022 c:::>
DQti c:::>
DQ23 c:::>
DQti c:::>
DQ24 c:::>
DC7 c:::>
DQ25 c:::>
A7 c:::>
Ne c:::>
vee c:::>
AI c:::>
AI c:::>
RAS3 c:::>
FIAS2 c:::>
DQ27 c:::>
cae c:::>
)
DC17 c:::>
DQ38 c:::>
c:::>
...YH
CABO c:::>
CASi c:::>
CASi c:::>
CAii c:::>
AASO c:::>
AAS1 c:::>
He c:::>
Vi c:::>
NO c:::>
DQI c:::>
DQ27 c:::>
DC10 c:::>
DQ28
DQO
DCl.
DCl
DCl'
DC11
DQ2I
1
2
1
4
5
•
7
•
•
10
"
12
13
14
l'
1.
17
18
18
20
21
22
23
24
25
28
27
28
21
30
31
32
33
34
38
38
17
18
38
40
41
42
43
44
45
45
47
45
48
80
'1
S=
c:::>
14
c:::> 15
c:::> 18
c:::> 17
DQ31 c:::> 18
Vee c:::> 18
DQ32 c:::> 80
DC14 c:::> '1
DQ33 c:::> 82
DCUI c:::> 83
DQ34 c:::> 84
DCl' c:::> as
He c:::> 88
P01 c:::> 17
POI c:::> 88
POI c:::> 88
P04 c:::> 70
He c:::> 71
Vas c:::> 72
DC12
DQ30
DCl1
TM883NBM38A
(SIDE VIEW)
<±)
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
<±)'
o
o
o
o
PIN NOMENCLATURE
DQO-DQ35
NC
PD1-PD5
AASO-RAS3
Address Inputs
Column-Address Strobe
Data In/Data Out
No Connection
Presence Detects
Row-Address Strobe
Y$s
5-VSupply
Ground
AO-Al0
~-CAS3
Vee
Write Enable
W
PRESENCE DETECT
SIGNAL
(PIN)
TM497MBM36A
TM893NBM36A
PD3
(89)
PD4
(70)
NC
NC
NC
Vss
NC
NC
Vss
NC
Vss
NC
PD1
(67)
PD2
(88)
SOns
VSS
70ns
VSS
SOns
80ns
VSS
NC
70ns
NC
Vss
SOns
NC
Vss
Vss
NC
NC
Vss
NC
NC
~ThxAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8·109
!
o
I
~~i!i!
functional block diagram (TM497MBM36A and TM893NBM36A, side 1)
Z f8cB
i~»w
....
1
AO-A10 11
:!!~i:i:
,...
Ww
RAS2
RASO
efteft
Iz»»
10-.. -'
Vi
CASO
-
CAS14M,,4
AO-A10
~ Vi
CAS
.... OE
l:-
D01DQ4
~
il~~~
gf
~m
~~
~DQO- ~
D03
CAS
......
~~Q4~
D07
~ Vi
CAS
l
D
_._--
0
DQ1- ..... DQ13DQ4
0016
~
-=±.....
~~
DQ6
I
0
T
0017
I
D
o
"'CI) eft eft
OE
D01DQ4
~
-;:- Vi
...
J--
CAS
OE
D01DQ4
.....
DQ27-
'030
~ RAS
I
~ Vi
CAS
.DQ26
I
D
i:w ...
om~
~eftw
i:ClDiI:Io
...
82!2!
C:~w
r-.~
!31;D034
.
0
i:Oo
mCl)iI:Io
-00
411,,1
AO-A10
~ RAS
CAS
- i:i:
:gCl)w
w
4M,,4
AO-A10
RAS
DQ1- ..... DQ22DQ25
DQ4
~ Vi
CAS
Vi
D
-!--
411,,1
AO-A10
~ AO-A10
RAS
~ RAS
C
0021
Vi
~ CAS
.... OE
4M,,1
411 x1
AO-A10
~DQ18-
....
~ RAS
OE
•
~ RAS
4M,,4
AO-A10
Vi
~ ·CAS
Vi
D01DQ4
~.!.
DQ1DQ4
~ RAS
~:i>~~
ZOm
mm m
EOZi:
-;:- ViCAS
~ Vi
.... CAS
OE
-!-
CIli:CI) iI:Io
4M,,4
AO-A10
~ RAS
4M,,4
AO-A10
411,,4
AO-A10
..... OE
~
4M,,4
AO-A10
DQ1- ..... 009DQ4
D012
~ RAS
±.....
411,,4
AO-A10
RAS
~ Vi
CAS
.... OE
lIo
..........
~. i:i:
CAS3-
CAS2-
~
~ RAS
~
i:z i:
~nmm
I
D035
mmm
CI)=i=i
functional block diagram (TM893NBM36A, side 2)
AO-A10 11
HAS1
RAS3
Vi
CASO
-
~
4M .. 4
AO-A10
HAS
~
~ Vi
CAS
~
0_.,.
...
~
"
~
zrl1
~~
OE
001DQ4
~z
~ir
!~
as2-
CAfi-
~
~
"
~OQO"*"
D03
4M .. 4
AO-A10
HAS
~
DQ4
~
t
"
f4+- DQ4
D07 -
'*"
~ Vi
CAS
l
D
Q
001- . . . 009DQ4
0012
"
J
:~
0Q8
I
001- . . . 0018DQ21
DQ4
.... OE
J.-
D01DQ4
4M .. 4
4y .. 4
AO-A10
HAS
001- . . . 0013DQ4
D016
'*"
OE
001- . . . 0022DQ25
DQ4
It!-
J~
.~
0017
1
"
J.-
CAS
D
Q
zmct
»~ . . .
OE
D01DQ4
!31-
~ DQ34
4y .. 1
4M .. 1
AO-A10
HAS
~ AO-A10
HAS
~ Vi
...
-1-1
~!!5:!!5:
~ CAS
~ Vi
CAS
J-.,
DQ27-
~ DQ30
~ Vi
~ AO-A10
HAS
OE
~ AO-A10
~ ViHAS
" CAS
Q
D
~ CAS
OE
"*"
4y .. 1
4M .. 1
4y .. 4
AO-A10
HAS
~ Vi
~ Vi
CAS
Vi
CAS
OE
~ Vi
CAS
~ AO-A10
HAS
1.
4M .. 4
~ AO-A10
HAS
~ RAS
OE
001-
4M .. 4
AO-A10
HAS
4y .. 4
AO-A10
~ Vi
CAS
...
CAS3-
J
...
~ Vi
CAS
DQ26
D
1
o
!!5: z !!5:
-mm
O!!5:!!5:
:a wW
»~~
z- -
0-1-1
O!!5:!!5:
i:m.&:lo
• , - CD
I
DQ35
(/»>w
...
~oz !!5:
~omm
'" m!!5: !!5:
~(I)W W
I (l)G) G)
:ts:""
~mm.&:lo
-s:w ....
loll~
~~g~
~s:m.&:lo
~o~~
EOWW
~
AiC:~ ~
-r-mm
Im=i =i
TM497MBM38A, TM497MBM36Q4194304 BY 36-BIT
TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS8Il3A- MAY 1995- REVISED JUNE 1995
absolute maximum ratings over operating free.alr temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .......................•...................... -1 Vto 7V
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Short-circuit output current ................................................................. 50 rnA
Power dissipation: TM497MBM36A, TM497MBM36Q •••• • • • • • • • • • • • . • . • • . • • • • • • • • • . • • • • • • • •• 12 W
TM893NBM36A, TM893NBM36Q ••••..••• ,............................... 24 W
Operating free-air temperature range, TA ............................... ~ • • • • • • • • • • . • •• ooe to 700 e
Storage temperature range, Tstg ••••••••.••••.•.••.••.•••••••••••••••••••••••••••• - 55°e to 125°0
t Streases beyond thole Iistad under "abaoIute maximum ratings" may cause permanent damage to the device. These are IIIr888 ratings only, and
functional operation of the device at these or any other conditions beyond Ihoae indicated under "recommended operating conditions" Is not
implied. Exposure to absolute-maxlmum-rated conditions for extended periods may affec:t device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
Vcc
Supply voltage
4.5
5
5.5
VIH
Hlgh.Jevellnput voltage
2.4
8.5
V
VIL
Low-level Input voltage (see Note 2)
-1
0.8
V
TA
Operating free-alr temperature
0
70
'0
UNrr
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit 18 designated as mlnlmum,ls used for logic-voltage IeveIa only.
electrical characteristics over recommended ranges of supply voltage and operating fre...lr
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS*
VOH
High-level output
voltage
IOH"'-5mA
VOL
Low-level output
voltage
IOL-4.2mA
II
Input current
Oeakage)
VI-OVto8.5V,
VCC- 5•5V,
All other pins .. 0 V to Vcc
Output current
VCC-5.5V,
(I~e)
~hlgh
Read- or writa-cycle
current
VCC=5.5V,
10
ICC1
Icc2
Standby current
'497MBM38A-80
MIN
2.4
VO·OVtoVCC,
Minimum cycle
Average page
MIN
MAX
2.4
MAX
UNrr
V
0.4
0.4
0.4
V
:I:
10
:1:10
:1:10
JIA
:I:
10
:1:10
:1:10
JIA
1300
1180
1040
mA
24
24
24
mA
VIH • Vcc - 0.2 V (CMOS),
After 1 memory cycle,
12
12
12
mA
1300
1180
1040
mA
880
mA
mand~high
Minimum cycle,
VCC· 5•5V,
RAScycllng,
CA! high (RAS-only refresh);
JiAS low after ~ low (CBR)
VCC· 5.5V,
JiASIow,
~1ExAs
6-112
MIN
2.4
tpC·MIN,
920
800
~CYCling
* For test conditions shown as MIN/MAX, use the appropriate value specified In the timing requirements.
1CC4 current
'487MBM38A-80
VIH = 2.4 V (TTL),
After 1 memory cycle,
RASand~hlgh
Average refresh
current
1CC3 ~nly refresh
orCBR)
'497MBM38A· 70
MAX
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON. 1EXAS 77251-1443
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT
TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT
DYNAMIC RANDOM·ACCESS MEMORY MODULES
SMMS853A- MAY 1996 - REVISED JUNE 1996
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted) (continued)
PARAMETER
TEST CONDmoNSt
VOH
High-level output
voltage
IOH--5mA
VOL
Low-Ievel output
voltage
IOL-4.2mA
II
Input current
(leakage)
VCC- 5•5V,
VI-OVtoS.5V,
All other pins .. 0 V to Vcc
10
Output current
(leakage)
CAS high
ICC1
Read-or~e
current (one
active. see Note 3)
1CC2 Standby current
Average refresh
current
Ices (RASonly or CBR.
see Note 3)
'893NBM38A-80
MIN
'893NBM38A-70
MAX
2.4
MIN
'893NBM38A-80
MIN
MAX
2.4
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
:1:20
:1:20
:1:20
:1:20
:1:20
:1:20
""
1324
1184
1084
mA
VIH - 2.4 V (TTL),
After 1 memory cycfe.
JiA! end ~ high
48
48
48
mA
VIH - VCC - 0.2 V (CMOS).
After 1 memory cycfe.
RAS end CAS high
24
24
24
mA
1324
1184
1084
mA
704
niA
VCC- 5•5V•
Vo .. OVtoVCC.
Minimum cycfe
VCC- 5•5V,
Minimum cycle,
VCC .. S.5V.
RAS cycling.
~ high (AA!.only refresh);
RAS low after CAS low (CBR)
Average page
tpc .. MIN.
VCC- S•5 v,
current
944
824
1CC4 (one RAS actfve,
CAS cycling
RASfow.
see Note 4)
..
t For test conditions shown as MIN IMAX. use the appropnate value specfffed In the tuning reqUIrements •
NOTES: 3. Measured with a maximum of one address change while RAS - VIL
4. Measured with a maximum of one addreSs change while CAS .. VIH
""
capacitance over recommended supply voltage range and operating free-alr temperature range,
f 1 MHz (see Note 5)
=
'487MBM38A
PARAMETER
MIN
MAX
'893NMB38A
MIN
MAX
UNIT
CllA)
CI(R)
Input capacitance. AO-A10
80
120
pF
Input capacftance. RAS Inputs
42
pF
CIICl
Input capacitance. CAS Inputs
21
42
42
CI/WI
Input capacitance, write-enable Input
84
188
pF
7
14
pF
12
24
pF
Co(DQ)
I DQpins
Output caPacItance
I Parity pins
pF
NOTE 5: Vcc - 5 V :I: 0.5 V. end the bIBS on pins under test IS 0 V..
-!II
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. T\!XAS 77251-1443
8-113
TM497MBM36A, TM497MBM36Q 4194304 BY 36·BIT
TM893NBM36A, TM893NBM36Q8388608 BY 36-BIT
DYNAMIC RANDOM·ACCESS MEMORY MODULES
SMMS86SA-MAY 1995-REVlSEDJUNE1995
'
switching' characteristics over recommended ranges of, supply voltage and operating free-alr
temperature
'497MBM36A-60
'893NBM36A-60
PARAMETER
'497MBM36A-70 '497MBM3fA-60
'893NBM3fA-70, '893NBM36A.80
MAX
tM
Access time from column address
30
35
MAX
40
teAC
tRAC
15
18
20
60
70
80
teLZ
Access time from ~ low
Access time from RAS low
Access time from column precharge
~ low to output in Iow-impedance state
toFF
Output disable time after ~ high (see Note 6)
MIN
tePA
MIN
35
0
15
3
MIN
45
40
0
0
Output dlBSbIe time, start of CAS high
toH
NOTE 6: toFF Is speolfled when the output Is no longer driven.
MAX
0
0
18
0
20
3
3
UNIT
ns
ns
ns
ns
ns
ns
ns
timing requirements over recommended ranges of supply voltage and operating free..lr
temperature
'497MBM36A-60 '497MBM3fA.70 '497MBM36A-80
'893NBM36A-60 '893NBM3fA-70 '893NBM36A-80
MAX
MIN
MIN
MAX
MIN
UNIT
MAX
tRP
Pulse duration, RAS high (precharge)
40
50
60
twp
PulSe duration, iN low
10
10
10
tASC
Setup time, column address before ~ low
0
0
0
tASR
Setup time, row address before RAS low
0
0
0
tos
Setup time, data before CAS low
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRCS'
Setup time, Whigh before ~ low
0
0
0
ns
tcwL
lRWL
Setup time, W low before CAS high
15
18
20
ns
Setup time, iN low before RAS high
15
18
20
ns
twcs
Setup time, W low before ~ low
0
0
ns
twRP
Setup time, W high before RAS low (CBR refresh only)
10
10
'0
10
'teAH
Hold time, column address after .CAS low
10
15
15
ns
lAHCP
Hold time, RAS high from ~ precharge
35
40
45
ns
lAc
tpc
Cycle time, random read or write (see Note 7)
110
130
150
40
45
50
Cycle time, page-mode read or write (see Notes 7 and 8)
tRASP
Pulse duration, page mode, RAS low,
60
100000
70
100000
80
100000
!RAs
Pulse duration, nonpage mode, RAS low
60
10000
70
10000
80
10000
teAS
tep
Pulse duration, CAS low
15 ' 10000
18
10000
20
10000
Pulse duration, ~ high
10
1'0
10
ns
toH
Hold time, data after CAS low
10
15
15
ns
lRAH
Hold time, row address after RAS low
10
10
10
ns
tRCH
Hold time, iN high after CAS high (see Note'9)
,0
0
0
ns
tRRH
Hold time, iN high after RAS high (see Note 9)
0
0
0
twCH
Hold time, W low after CAS low
10
15
15
ns
ns
10
10
10
n8
Hold time, iN high after RAS low (CBR refresh only)
twRH
NOTES: 7. All cycle times assume IT .. 5 ns.
8. To assura tpc min, tASC should be 11: teP.
9. Either tRRH or tRCH must be satisfied for a read cycle.
~ThxAs
6-114
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 'TEXAS 77251-1443
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT
TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS853A-MAY 1995-REVlSEDJUNE 11196
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (continued)
'487MBM36A·80
'893NBM36A·80
MIN
'4I17MBM36A·70
'893NBM36A·70
MAX
MIN
'4I17MBM36A·80
'893NBM36A·80
MAX
MIN
teHR
Delay time, RAS low to CAS high (CBR refresh only)
10
10
10
teRP
tcsH
Delay time, CAS high to RAS low
5
5
5
Delay time, AAS low to CAS high
80
70
80
tcsR
tRAe
Delay time, CAS low to AAS low (CBR refresh only)
Delay time, RAS low to column address (see Note 10)
Delay time, column address to RAS high
Delay time, column address to CAS high
5
5
tRAL
teAL
tRCD
tRPe
15
30
20
tRSH
tREF
Delay time, CAS low to AAS high
Refresh time Interval
15
tr
Trensltlon time
20
20
3
n.
ns
ns
ns
32
ms
30
ns
20
32
30
3
ns
ns
ns
ns
ns
ns
80
0
18
30
40
40
52
0
32
15
40
35
4S
0
3
5
35
35
30
30
Delay time, RAS low to CAS low (see Note 10)
Delay time, RAS high to CAS low (CBR refresh only)
15
UNrr
MAX
NOTE 10: The maximum value IS specified only to assure access time.
device symbolization (TM497MBM36A Illustrated)
o
·0
0
0
@DDDDDDDD@
-SS
TM497MBM36A
11111111' I111111111
I11111111111111
YYMMT
'111111111111111111111111111111111111
YY • Year Code
Month Code
T • Asaembly Site Code
-SS • Speed Code
MM •
NOTE: Location of symbolization may vary.
~lEXAS
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSlON. 'TeXAS 77261-1443
6-115
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT
TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS853A-MAY 1895-REVlSEDJUNE 1895
.~1ExAs
6-118
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 1EXAS 77251-1443
•
7·1
Contents
CHAPTER 7.
TMS28F512A
TMS28F010B
TMS28F210
TMS28F020
TMS28F200
TMS28F400
TMS27C256
TMS27PC256
TMS27C510
TMS27PC510
TMS27C512
TMS27PC512
TMS27C010A
TMS27PC010A
TMS27C210A
TMS27PC210A
TMS27C02O
TMS27PC020
, TMS27C04O
TMS27PC040
TMS27C240
TMS27PC240
FLASH MEMORY
.
. ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EPROM)
ONE-TIME PROGRAMMABLE MEMORY (OTP)
524288-bit
1048576-bit
1048576-bit
2097152-bit
2097152-bit
4194304-bit
262144-bit
262144-bit
524288-blt
524288-bit
524288-blt
524288-bit
1048576-bit
1048576-bit
1048576-bit
1048576-bit
2097152-bit
2097152-bit
4194304-blt
4194304-bit
4194304-bit
4194304-bit
(64K)( 8) 12-VAashMemory .; .................................. 7-3
(128K)( 8) 12-V Flash Memory .................................. 7-25
(64K)( 16) 12-V Flash Memory .................................. 7-47
(256K x 8)FISsh Memory ....••••••••• '•••.•••.••.....•..•..••..• 7-67
(256K)( 8/512K)( 16) Flash Memory ............................. 7-87
(256K)( 8/512K)( 16) Flash Memory •.•••..•••.••.•.•..•••.••.•. 7-115
(32K)( 8) CMOS EPROM. ; •••••••••.••••.••..•....•..•...••..• 7-143
(32Kx 8) CMOSOTP PROM •••••••..•••••.•...•.••.•••.•.•••• 7-143
(64Kx 8) CMOS EPROM ...................................... 7-155
(64K)( 8) CMOS OTP PROM .................................. 7-155
(64K)( 8) CMOS EPROM •••.•••••.••••..••.•..•..•...••....•.• 7-167
(64K)( 8) CMOS OTP PROM .................................. 7-167
(128K)( 8) CMOS EPROM •..•..•....•.......•...•..••..•.•.••• 7-179
(128K)( 8) CMOS OTP PROM •..•...... ~ ....•...•..•••.•.•.••. 7-179
(64Kx 16) CMOS EPROM ••...••..•••..•..•...•..•••...•.•.•.. 7-191
(64K x 16) CMOS OTP PROM ••••••••••••••••••..••..•.•..•••• 7-191
(256K)( 8) CMOS EPROM ..................................... 7-201
(256K)( 8) CMOS OTP PROM ................................. 7-201
(512K)( 8) CMOS EPROM •....•...•.••••••••••••..••.•.••••••• 7-211
(512K)( 8) CMOS OTP PROM ••••••.••..•.......•.•..•.••..••• 7-211
(256K)( 16) CMOS EPROM .................................... 7-221
(256K)( 16) CMOS OTP PROM ................................ 7-221
~TEXAS
7·2
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
TMS28F512A
524288·BIT FLASH MEMORY
•
•
•
•
•
•
•
•
•
•
NPACKAGE
(TOP VIEW)
Organization ••• 14K )( 8-Blt Flash Memory
Allinputs/Outputa TTL Compatible
Vee Tolerance :t10%
Maximum Access/ Minimum Cycle TIme
'28F512A·10
100 ns
'28F512A·12
120 ns
'28F512A·15
150 ns
'28F512A·17
170 ns
Industry-8tandard Programming Algorithm
PEP4 Version Available With 168·Hour
Bum·ln and Choice of Operating
Temperature Ranges
Chip Erase Before Reprogramming
10000 and 1000 Program/Erase Cycles
Low Power Dissipation (Vee 5.5 V)
- Active Write ••• 55 mW
- Active Read ••• 165 mW
- Electrical Erase ••• 82.5 mW
- Standby ••• 0.55 mW
(CMOS·lnput Levels)
Automotive Temperature Range
- 40°C to 125°C
Vpp
NC
A15
A12
A7
AS
AS
A4
AS
A2
A1
AD
ooa
=
001
002
Vss
1
Vee
2
3
4
5
iii
6
NC
A14
A13
AS
7
AS
6
A11
9
10
11
12
13
14
15
18
G
22
21
20
19
18
17
A10
~
007
D06
005
004
003
FMPACKAGE
(TOP VIEW)
NI/)OQ.O
0
;(;( z ~~I~ z
description
The TMS28F512A Flash memory is a 524 288-bit,
programmable read-only memory that can be
electrically bulk-erased and reprogrammed. It is
available in 10000 and 1000 program/erase
endurance cycle versions.
The TMS28F512A is offered in a dual-in-line
plastiC package (N suffix) designed for insertion in
mounting-hole rows on 15,2-mm (600-mil)
centers, a 32-lead plastic leaded chip-carrier
package with 1,25-mm (SO-mil) lead spacing
(FM suffix), a 32-lead thin small-outline package
(DD suffix), and a reverse~pinoutTSOP package
(DU suffix).
The TMS28F512A is characterized for operation
in temperature ranges of ooe to 70 0 e (NL, FML,
DDL, and DUL suffixes), -40oe to 85°e (NE,
FME, DDE, and DUE suffixes), and -40oe to
125°e (NQ, FMQ, DDQ, and DUQ suffixes). All
package types are offered with 168-hour burn-in
(4 SuffIX).
A7
A6
0
5
A14
A13
AS
AS
A4
AS
A2
AS
A11
G
A1
A10
AD
'E
21
000
007
1415 18 171819 20
"'N~C')81/)8
gg;:>g
go
PIN NOMENCLATURE
AO-A15
DQO-OQ7
E
G
NC
VCC
Vpp
vSS
W
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, lEXAS 77251-1443
Address Inputs
Inputs (programming)/Outputs
Chip Enable
Output Enable
No Internal Connection
5-V Power Supply
12·V Power Supply
Ground
Write Enable
Copyright 10 1995. Texas Instrumen1S Incorporated
7·3
1MS28F512A
524288-811
FLASH MEMORY
I
.....
>
SMJS514A.,. FEBRUARY 1994 - REVISED JUNE 1995
DDPACKAGE
(TOP VIEW)
A11
A9
A9
A13
A14
NC
iii
Vee
Vpp
NC
A15
A12
A7
AS
AS
A4
1
2
3
4
5
8
7
8
9
10
11
12
13
14
15
18
0
32
A10
31
30
E
29
007
28
DO~
27
005
004
003
VSS
002
001
COO
AO
A1
28
25
24
23
22
21
20
19
18
17
A2
A3
DUPACKAGE
REVERSE PINOUT
(TOP VIEW)
G
A10
E
007
DOS
005
004
003
Vss
002
001
000
AO
A1
A2
A3
1
2
3
4
5
8
7
8
9
10
11
12
13
14
15
18
V
32
AS
29
A13
A14
27
NC
28
iii
25
Vee
Vpp
24
23
NC
22
A15
A12
A7
AS
21
20
19
18
17
~1ExAs
7-4
A9
30
28
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON,TEXAS 77251-1443
All
31
AS
A4
TMS28F512A
524288-81T FLASH MEMORY
SMJS514A- FEBRUARY 1894- REVISED JUNE 1996
device symbol nomenclature
TMS28F512A
·12
C4
FM
L
L
4
PEP4Bum-ln
4 • 188-Hour Bum-ln
(blank If no bum-ln)
Temperatura Range Daalgnator
L.
O"C to 700C
E • - 4O"C to a"C
Q • -WC to1ZS"C
' - - - - - - - - - - Packaga Dealgnator
N. Plutlc Dual-ln-Une Package
FM. PlaatIc Leaded Chip Cerrler
DD. Thin Small-Outllna Package
DU. Thin Small-Outllne Package,
Ravaraa Pinout
' - - - - - - - - - - - - Program/Era.. Endurance
C4 • 10000 eye...
C3 • 1000 Cycl..
L - - - - - - - - - - - - S p e a d Dnlgnator
·10 • 100na
·12 • 120na
·15 • 160na
.17 • 170na
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUS1ON, TEXAS 77251-1443
7-6
TMS28F512A
524288-8IT FLASH MEMORY
SMJS514A- FEBRUARY 1994 - REVISED JUNE 1995
logic symbol t
AO
A1
A2
A3
A4
AS
AS
A7
AS
AS
A10
A11
A12
A13
A14
A15
fLASH
o ...
12
11
10
8
8
EEPROM
85538><'
7
8
5
>A85~
27
28
23
25
4
28
28
3
22
15 ...
"
Q1
[PWRDWN]
24~ G2
G
Vi
31
DQO
13
DQ1
14
15
L....!:::.
1,2 EN (READ)
1C3(WRITE)
r
DQ2
DQ3.
DQ4
DQ5
DQ8
DQ7
A, 3D
L.+V4
A,Z4- -
17
18
18
20
21
tThls symbol Is In accordance with ANSI/IEEE Std 91-1984 and lEO Publication 617-12.
Pin numbars shown are for the N package.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1_ • HOUSTON. ~ 77281-1_
TMS28F512A
524288-81T FLASH MEMORY
SMJS514A- FEBRUARY 1994- REVISED JUNE 11195
functional block diagram
DQO-DQ7
Vpp
------e-----4~...,
W---t~
STB
E
Chlp-Enable and
Output-Enable
logic
G
8TB
AO-A15
18
A
d
d
r
e
a
e
L
a
t
c
h
Column Decoder
Row Decoder
Column aaUng
524288-BIt
Array Matrix
,~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7-7
TM.S28F512A
524288-8IT FLASH MEMORY
SMJSSt4A- FEBRUARY 1994 - REVISED JUNE 1995
Table 1. Operation Mod.s
FUNCTIONt
MODE
Read I
WrIte
E
G
AI)
At
W
(22)
(24)
(12)
(26)
(31)
DQO-DQ7
(13-15,17-21)
VPPL
VPPL
VIL
VIL
X
X
VIH
Data Out
Output Disable
VIL
VIH
X
X
VIH
Hi-Z
Standby and WrIte Inhibit
VPPL
VIH
X
X
X
X
Read
Read
Vpp*
(1)
Algorithm-8eleC:tion Mode
VPPL
VIL
ViL
Read
Output Disable
VPPH
VPPH
VIL
VIL
VIL
Standby and WrIte Inhibit
VPPH
WrIte
VPPH
ViL
Hi-Z
Mfr Equivalent Code 89h
VID
VIH
X
X
VIH
Data Out
VIH
X
X
VIH
Hi-Z
VIH
X
X
X
X
Hi-Z
VIL
VIH
X
X
VIL
Data In
VIH
t X can be VIL or VIH.
* VPPL "Vee + 2 V; VPPH Is the programming voltage 8pec1fied for the device. For more detail., _
Device Equivalent Code Bah
recommended operating conditions.
operation
read/output disable
When the outputs of two or more TMS28F512As are connected in parallel on the same bus, the output of any
particular device In the circuit can be read with no interference from the competi.!]) outputs of other devices. To
.read the output of the TMS28F512A, a low-level signal is applied to the 'E and G pins. All other devices in the
circuit should have their outputs disabled by applying a high-level signal to one of these pins.
standby and write Inhibit
Active ICC current can be reduced from 30 mA to 1 mA by applying a high TTL level on 'E or to 100 JIA with a
high CMOS level on 'E. In this mode, all outputs are in the high-impedance state. The TMS28F512A draws active
current when It is deselected during programming, erasure, or program/erase verification. It continues to draw
active current until the operation Is terminated.
algorlthm-aelectlon mode
The algorithm-selection mode provides access to a binary code identifying the correct programming and erase
algorithms. This mode is activated when A9 Is forced to VID. Two Identifier bytes are accessed by toggling AO.
All other addresses must be held low. AO low selects the manufacturer equivalent code 89h, and AO high selects
the device equivalent code B8h, as shown In the algorithm-selection mode table below:
IDENTIFIERI
PINS
D07
DQ6
DQ6
DQ4
DQ3
DQ2
DQ1
DOO
VIL
1
0
0
0
1
0
0
1
89
1
0
1
VIH
ij .. VII.. A1-AS"VIL,A9=VID,A10-A15-VI1o VPP .VpPL.
1
1
0
0
0
88
Manufacturer Equivalent Code
Device Equivalent Code
Se ..
HEX
AI)
programming and erasure
In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to
a logiC O. Afterwards, the entire chip Is erased. At this point, the bits, now logic 1s, can be programmed
accordingly. Refer to the Fastwrite and Fasterase algorithms for further detail.
~1ExAs
7-8
INSTRUMENTS
POST OFFICE BOX 1443 • HOUStON. TEXAS 77251-1443
TMS28F512A
524288-81T FLASH MEMORY
SMJS514A- FEBRUARY 1814 - REVlBED JUNE 18111
command register
The command register controls the program and erase functions of the TMS28F512A. The algorlthm-aelection
mode can be activated using the command register in addition to the previously described method. When Vpp
is high, the contents of the~mmand re.,iister and the function being performed can be changed. The command
register is written to when E is low and W is pulsed low. The address Is latched on the leading edge of the pulse,
while the data Is latched on the trailing edge. Accidental programming or erasure is minimized because two
commands must be executed to invoke either operation.
power supply considerations
Each device should have a O.1-"F ceramic capacitor connected between Vee and Vss to suppress circuit noise.
Changes in current drain on Vpp requires It to have a bypass capacitor as well. Printed circuit traces for both
power supplies should be appropriate to handle the current demand.
Table 2. Command Definitions
COMMAND
REQUIRED
BUS
CYCLES
OPERATlONt
ADDRESS
DATA
OPERAnoNt
ADDRESS
1
Write
X
00h
Read
RA
RD
0000
0001
89h
Read
SECOND BUS CYCLE
FIRST BUS CYCLE
DATA
AIgoritI1m-8election Mode
3
Write
X
SOh
Read
Set-Up-Erase/Erase
2
2
2
2
2
Write
Write
Write
X
20h
X
20h
EA
AOh
Write
Read
X
EVe
X
40h
PD
X
COh
Write
Read
PA
Write
X
PVD
Write
X
FFh
Write
X
FFh
Erase Verify
Set-Up-Program/Program
Program Verify
Reset
t Modes of operation are defined In Table 1.
Legend:
EA
RA
PA
RD
Address of memory location to be read during erase verify
Address of memory Jocation to be read
Address of memory location to be programmed. Address Is latched on the falling edge of W.
Data read from location RA during the read operation
EVe Data read from location EA during erase verify
PD Data to be programmed at location PA. Data is latched on the rising edge of W.
PVD Data read from location PA during program verify
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
B8h
TtJlS28F512A
524288.,Brr FLASH MEMORY
SMJSS14A- FEBRUARY 1994 - REVISED JUNE 1895
command definitions
read command
Memory contents can be accessed while Vpp is high or low. WhenVpp is high, writing OOh into the command
register invokes the read operation. When the device is powered up, the default contents of the cOmmand
register are oob and the read operation is enabled. The read operation remains enabled until a different valid
command is written to the command register.
algorithm-selection-mode command
The algorithm-selection mode is activated by writing. 90h into the command register. The manufacturer
equivalent code (89h) is Identified by the value read from address location OOOOh, and the device equivalent
code (B8h) is identified by the value read from address location 0001 h.
set-up-erase/erase commands
The erase algorithm inltiateswithE=VIL,W=VIL,G=VIH,VPP =VpPH,and Vee=5V.Toentertheerasemode,
write the set-up-erase command, 20h, into the command register. After the TMS28F512A is in the erase mode,
writing a second erase command, 20h, Into the command register invokes the erase operation. The erase
operation begins on the rising edge of W and ends on the rising edge of the next W. The erase operation requires
10 ms to complete before the erase-verify command, AOh, can be loaded.
Maximum erase timing is controlled by the internal stop timer. When the stop timer terminates the erase
operation, the device enters an inactive state and remains inactive until a valid erase-verify, read, or reset
command is received.
erase-verify command
All bytes must be verified following an erase operation. After the erase operation is complete, an erased byte
can be verified by writing the erase-verify command, Mh, into the command register. This command causes
the device to exit the erase mode on the rising edge of W. The address of the byte to be verified is latched on
the falling edge of W. The erase-verify operation remains enabled until a valid command is written to the
command register.
To determine whether or not all the bytes have been erased, the TMS28F512A applies a margin voltage to each
byte. If FFh Is read from the byte, all bits in the designated byte have been erased. The erase-verify operation
continues until all of the bytes have been verified. If FFh is not read from a byte, an additional arase operation
needs to be executed. Figure 2 shows the combination of commands and bus operations for electrically erasing
the TMS28F512A.
set-up-program/program commands
The programming algorithm initiates with E = VIL' W = VIL, G = VIH, Vpp = VpPH, and Vee = 5 V. To enter the
programming mode, write the set-up-program command, 40h, Into the command register. The programmi.!!9
operation is invoked by the n",xt write-enable pulse. Addresses are latched internally on the falling edge of W,
an~data is latched internally on the rising edQ! of W. The programming operation begins on the riSing edge
of Wand ends on the rising edge of the next W pulse. The program operation requires 10 f1S for completion
before the program-verify command, COh, can be loaded.
Maximum program timing is controlled by the internal stop timer. When the stop timer terminates the program
operation, the device enters an inactive state and remains inactive until a valid program-verify, read, or reset
command is received.
~ThxAs
7-10
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lEXAS 77251-1443
1MS28F512A
524288-811 FLASH MEMORY
SMJS514A- FEBRUARY 1984 - REVISED JUNE 1895
program-verify command
The TMS28F512A can be programmed sequentially or randomly because it is programmed one byte at a time.
Each byte must be verified after it is programmed. The program-verify operation prepares the device to verify
the most recently programmed byte. To Invoke the program-verify operation, COh must be written into the
command register. The program-verify operation ends on the rising edge of W.
'
While verifying a byte, the TMS28F512A applies an internal margin voltage to the designated byte. If the true
data and programmed data match, programming continues to the next designated byte location; otherwise, the
byte must be reprogrammed. Figure 1 shows how commands and bus operations are combined for byte
programming.
reset command
To reset the TMS28F512A after set-up-erase command or set-up-program command operations without
changing the contents in memory, write FFh into the command register two consecutive timas. After executing
the reset command, a valid command must be written into the command register to change to a new state.
Fastwrlte algorithm
The TMS28F512A is programmed using the Texas Instruments Fastwrite algorithm shown in Figure 1. This
algorithm programs in a nominal time of two seconds.
Fasterase algorithm
The TMS28F512A is erased using the Texas Instruments Fasterase algorithm shown in Figure 2. The memory
array needs to be completely programmed (using the Fastwrite algorithm) before erasure begins. Erasure
typically occurs in one second.
parallel erasure
To reduce total erase time, several devices can be erased in parallel. Since each Flash EEPROM can erase
at a different rate, every device must be verified separately after each erase pulse. After a given device has been
successfully erased, the erase command should not be issued to this device again. All devices that complete
erasure should be masked until the parallel erasure process is finished (see Figure 3).
Examples of how to mask a device during parallel erase include driving the Epin high, writing the read command
(OOh) to the device when the others receive a set-up-erase or erase command, or disconnecting it fr'om all
electrical signals with relays or other types of switches.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7-11
TMS28F512A
524288-81T FLASH MEMORY
SMJS514A- FEBRUARY 1994 - REVISED JUNE. 1995
-T
SetUp
Bue
Operation
Commind
Comments
Initialize
Add,....
Walt for Vpp to ramp to
VpPH (aea Nota A)
Standby
Initialize pulae count
WrIte
SeWpProgram
Data-40h
WrIte
Wru.Data
valid addraaa/data
Standby
Write
Walt. 101'8
Programvartfy
Data • COh; enda
program operation
Standby
Walt. 8 1'8
Read
Read byte to vertfy
programming; compara
output to expected output
Interactive
Mode
Power
Down
L
Write
Read
Standby
NOTES: A. Refer to the rac:ommended operating conditions for the value of VPPH.
B. Refer to the racommended opereting conditions for the value of VPPL.
Figure 1. Programming Flowchart: Fastwrlte Algorithm
7-12
.
I~TEXAS
NSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 'Il:XAS 77251-1443
Data _ 00h; reaata raglatar
for raad operatlona
Walt for Vpp to ramp to
VPPL (eae Note B)
TMS28F512A
524288-81T FLASH MEMORY
SMJS514A- FEBRUARY 1994 - REVISED JUNE 1995
Bus
Operation
Command
Commenta
Entlra memory must .. DOh
befora eraaure
Uae Faetwrlta
programming algorithm
Initialize addreaan
walt for Vpp to ramp to
Standby
VpPH ( - Nota A)
Initialize pulae count
Setup
WrIte
Set..IJp-
Oata.ZDh
Eraaa
Write
Eraae
Walt .. 10 ma
Standby
Interactive
Mode
WrIte
EraaaVerify
Addr. Byte to verlfyj
Data .. AOhj ende the erne
operation
Standby
Walt. 6 j1II
Raad
Read byte to verify eruuraj
compare output to FFh
Write
Rnd
Power
Down
Oata.ZOh
Standby
Data .. DOhj ranta raglater
for raad operatlona
Walt for Vpp to ramp to
VPPL (eaa Note B)
NOTES: A. Refer to the recommended operating conditions for the value of VPPH.
B. Refer to the recommended operating conditions for the value of VpPL.
Figure 2. Flash·Erase Flowchart: Fasterase Algorithm
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7-13
TMS28F512A
524288·81T FLASH MEMORY
SMJS51-4A,.. FEBRUARY 1894- REVISED JUNE 1995
GlveEraaa
Command to
All Unmasked
Davleaa
No
GlveR.ad
Command to
AlID.vleaa
GlveR.ad
Command To
All Devleaa
t n =number of devices being erased.
Figure 3. Parallel·Erase Flow Diagram
~1ExAs
7-14
.
INSTRUMENTS
POST OFFICE BOX 14<43 • HOUSTON. TEXAS 77251-14<43
TMS28F512A
524288-81T FLASH MEMORY
SMJS514A- FEBRUARY 1994 - REVISED JUNE 1995
absolute maximum ratings over operating free-alr temperature range (unless otherwise noted)t
SUj:)ply voltage range, Vee (see Note 1) ............................................. - 0.6 V to 7 V
Supply voltage range, Vpp ........................................................ - 0.6 V to 14 V
Input voltage range (see Note 2): All inputs except A9 •.•...•.............•.•••.. - 0.6 V to Vee + 1 V
A9 •••....•...•...•••.•••••.••...•..•••...••.•••.. -0.6Vto 13.5V
Output voltage range (see Note 3) ............................................ - 0.6 V to Vee + 1 V
Operating free-air temperature range during read/erase/program, TA
NL, FML, DOL, DUL ................................... ooe to 700 e
NE, FME, DOE, DUE ............................... - 40 0 e to 85°e
NQ, FMQ, DDQ, DUQ •........•...••..•..••••.••• -40° eto 125°e
Storage temperature range, Tstg .................................................. - 65°e to 1500 e
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" 18 not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to VSS.
2. The voltage on any Input pin can undershoot to - 2.0 V for periods less than 20 ns.
3. The voltage on any output pin cen overshoot to 7.0 V for periods less than 20 ns.
recommended operating conditions
MIN
VCC
Supply voltage
During write/read/flash erase
VID
During read only (VPPL)
Supply voltage
During write/read/flash erase (VppH)
Voltage level on AS for algorlthm-selectlon mode
vlH
High-level de input voltage
VIL
Low-level de Input voltage
TA
Operating free-air temperature
Vpp
TTL
CMOS
TTL
CMOS
NL. FML. DOL, DUL suffix
NE, FME. DOE. DUE suffix
NQ. FMQ. DDQ. DUQ suffix
4.5
0
11.4
11.5
2
VCC-0.5
-!l.5
GND-0.2
0
-40
-40
TYP
MAX
UNIT
5
5.5
V
V
12
VCC+2
12.6
13
VCC+ 0•5
VCC+ 0•5
0.8
GND+0.2
V
V
V
V
70
65
·C
125
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7·15
TMS28F512A
524288-81T FLASH MEMORY
SMJSSl4A- FEBRUARY 1994- REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-alr
(unless otherwise noted)
.
tempe~ature
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
VOL
Low-level output voltage
110
AS algorllhm-eelectlon-mode current
II
Input current (leakage)
10
Output current (leakage)
IAll axcept AS
lAS
10H =-2.5mA
MIN
2.4
10H .. -100 !.&A
VCC- 0.4
TYP
MAX
UNIT
V
IOL=5.8mA
0.45
10L • 100 !.&A
0.1
AS.Vlomax
V
200
!.&A
VI =OVI05.5V
VI=OVI013V
zl
z200
!.&A
VO .. OVIOVCC
z10
Vpp .. VPPH. Read mode
200
IpPl
Vpp supply current (read/standby)
VPP"VPPL
z10
!.&A
!.&A
!.&A
IpP2
Vpp supply current (during progrem pulse)
(888 Nota 4)
VPP=VPPH
30
mA
IpP3
Vpp supply current (during flash erase)
(see Nota 4)
VPP=VPPH
30
mA
IpP4
Vpp supply current (during program/eraseverify) (see Note 4)
VPP=VPPH
5.0
mA
ICCS
Vcc supply current
(standby)
VCC=5.5V. E=VIH
VCC .. 5.5V. E .. 'v'cc.
1
mA
100
!.&A
ICCl
Vcc supply current (active read)
VCC-5.5V. E"VILo f.8MHz.
Outputs open
30
mA
ICC2
Vcc average supply current (active write)
(888 Nota 4)
VCC=5.5V. E=VIL. Programming In
progress
10
mA
ICC3
VCC average supply current (flash erase)
(see Note 4)
VCC=5.5V. E.VIL. Erasure In
progress
15
mA
ICC4
VCC average supply current·
(program/el'BS8"verlfy) (see Note 4)
VCC-5.5V. E = VILo Vpp .. VpPH.
Program / erase-verify In progress
15
mA
I TTL-input level
I CMOS-Input level
NOTE 4. Not 100% tested; characterization data available
~1ExAs.
7-18
INSTRUMENTS
POST O~FICE BOX 1443 • HOUlTON, TEXAS 77251-1443
TMS28F512A
524288-81T FLASH MEMORY
SMJS514A- FEBRUARY 1984 - REVISED JUNE 1885
capacitance over recommended ranges of supply voltage and operating free-alr temperature,
f = 1 MHzt
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
CI
Input capacitance
VI-OV, 1-1 MHz
8
pF
Co
Output capacitance
Vo
=0 V, f =1 MHz
12
pF
t Capacitance measurements are made on sample basis only.
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature
TEST
CONDITIONS
ta{A)
Access time from
address, A
ta(E)
E
ALTERNATE
SYMBOL
'28F512A-10
MIN
MAX
'28F512A-12
'28F512A-15
'28F512A-17
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
IAVQV
100
120
150
170
ns
lELQV
100
120
150
170
ns
~
fGLQV
45
50
55
80
0$
tc(R)
Cycle time, read
tAVAV
100
120
150
170
0$
ld(E)
Delay time, E low
to Iow-Z output
tELQX
0
0
0
0
0$
ld(G)
Delay time, ~ low
to Iow-Z output
fGLQX
0
0
0
0
ns
ldls{E)
Chip disable time
to HI-Z output
tEHQZ
0
55
0
55
0
55
0
55
0$
ldls(G)
Output disable
time to Hi-Z
output
fGHQZ
0
30
0
30
0
35
0
35
0$
lh(D)
Hold time, data
valid from
address, E, or G*
tAXQX
0
0
0
0
ns
twHGL
8
8
6
8
f'8
ten(G)
Access time from
Acc~ time from
Write recovery
trac(W) time before resd
*
CL-'00pF,
1 Series 74
TTL Load,
Input tr ~ 20 0$,
Input tf ~ 20 ns
Whichever occurs first
-!!11ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7-17
TMS28F512A
524288-81T FLASH MEMORY
SMJS514A- FEBRUARY 1994- REVISED JUNE 1995
timing requlrements-wrlte/erase/program operations
PARAMETER
'28F612A-10
ALTERNATE
SYMBOL
MIN
NOM
MAX
'Z8F612A-1Z
MIN
NOM
MAX
UNIT
tc(w)
Cycle time, write using VI
tAVAV
100
120
n8
tcfWlPR
Cycle time, programming operation
twHWH1
10
10
1'8
tc(w)ER
Cycle time, erase operation
Hold time, addras
twHwHz
twl.Ax
9.5
lh(A)
thlEI
th(WHO)
Hold time, E
10
9.5
10
m8
55
60
n8
twHEH
0
0
n8
Hold time, date valid after VI high
twHox
10
10
n8
taulA)
Setup time, address
lAVlNL
0
0
ns
tau(O)
Setup time, date
toVWH
50
50
ns
talJ{EEt
tauIEHVPP)
Setup time, E before W
tcLWL .
20
20
ns
Setup time, E high to VPP ramp
tEHVP
100
100
n8
tauevPPEL)
tree(\'\/)
Setup time, VPP to E low
tvPEL
1.0
1.0
Recovery time, VI before read
twHGL
8
8
treclRl
Recovery time, read before W
lGHWL
0
0
1'8
1'8
1'8
tw(W)
Pulse duration, W (see Note 5)
twLWH
60
60
ns
twlWHI
Pulse duration, W high
lWHwL
20
20
ns
trIVPPI
tfIVPP)
Rise time, VPP
tvPPR
1
1
Fall time, VPP
tvPPF
1
1
1'8
1'8
PARAMETER
'Z8F612A-16
ALTERNATE
SYMBOL
MIN
NOM
MAX
'Z8F61ZA-17
MIN
NOM
MAX
UNIT
tc(W)
Cycle time, write using W
lAVAV
150
170
tcfWlPR
Cycle time, programming operation
twHWH1
10
10
tclWlER
lh(A)
Cycle time, erase operation
twHWH2
9.5
Hold time, addras
twl.Ax
80
70
ns
lhlEl
Hold time, E
twHEH
0
0
ns
lh(WHOl
Hold time, data valid after W high
twHox
10
10
ns
tau (A)
Setup time, address
tAVWL
0
0
ns
tauCO)
Setup time, data
tOVINH
50
50
ns
tau/El
tau(EHVPP)
Setup time, E before VI
tELWL
20
20
Setup time, E high to VPP ramp
tEHVP
100
100
ns
ns
tvPEL
1.0
1.0
twHGL
8
8
10
9.5
ns
1'8
10
ms
tauMPEL). Setup time, VPP to E low
Recovery time, VI before read
treefWl
Recovery time, read before W
tree(R)
lGHWL
0
0
1'8
1'8
1'8
tw(W)
Pulse duration, W (see Nota 5)
twLWH
60
80
ns
twlWHl
Pulse duration, W high
lWHwL
20
20
ns
trIVPPI
Rise time, VPP
tvPPR
1
1
tvPPF
1
1
1'8
1'8
Fall time, VPP
tfIVPP)
NOTE 5: Rise/fail time :s 10 ns
~1ExAs
7-18
.
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lEXAS 77251-1443
TMS28F512A
524288-8IT FLASH ·MEMORY
SMJS514A- FEBRUARY 1994 - REVISED JUNE 1895
.. timing requirements - alternative E-controlled writes
ALTERNATE
SYMBOL
PARAMETER
'28F512A·10
MIN
'28F512A·12
MAX
MIN
MAX
'28F512A·15
MIN
MAX
'28F512A·17
MIN
MAX
UNIT
tclWl
Cycle lime, write using E
IAVAV
100
120
150
170
ns
tc(E)PR
Cycle time, programming
operation
tEHEH
10
10
10
10
I'll
ih(EA)
th(ED}
Hold time, addrass
Hold time, data
tELAX
75
80
80
10
10
10
90
10
ns
tEHDX
ihlWl
tau (A)
tau(O}
Hold time, W
tEHWH
0
0
0
0
ns
IAVEL
tOVEH
0
0
0
0
ns
50
50
50
50
ns
twLEL
0
0
0
0
ns
tvPEL
1.0
1.0
1.0
1.0
I'll
IEHGL
6
6
6
6
I'll
tGHEL
0
0
0
0
I'll
70
70
80
ns
20
20
20
ns
Setup time, addrass
Setup time, data
Setup time, W before E
tauNPPEL} . Setup time, Vpp to E low
Recovery time, write using E
trec(E)R
before read
tau(W)
trec(E)W
Recovery ti!!!e, read before
write using E
tw(E)
Pulse duration, write using E
tELEH
70
tw(EH}
Pulse duration, write, E high
tEHEL
20
ns
PARAMETER MEASUREMENT INFORMATION
-4
2.08 V
Output
Under Test
T
RL =aooQ
CL-100pF
(sHNoteA)
LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
2.4V
OASV
=X
2V
O.BV
O.!~ X"'___
VOLTAGE WAVEFORMS
Figure 4. Load Circuit and Voltage Waveforms
AC testing inputs are driven at 2.4 V for logic high and 0.45 V for logic low. liming measurements are made at
2 V for logic high and 0.8 V for logic low on both Inputs and outputs. Each device should have a 0.1·"F ceramic
capacitor connected between Vee and Vss as close as possible to the device pins.
:111ExAs .
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON, TEXAS 77261-1443
7·19
TMS28F512A
524288-BIT FLASH MEMORY
8MJSS14A- FEBRUARY 18114- REVISED JUNE 1896
PARAMETER MEASUREMENT INFORMATION
lol
1c(R) -----~~I
AO-A1S-----X
I
I
X,;.-------
Add ..... VaIIcl
'"
ta(A)
~
I
E------'~~--~.-I~I----~~~i-------
.: I+-- ta(E) ~
0' - - - - - - + - 1-'It
I
1'\
"I
I
ftrec(W) M
W---/I'
I
teI(E)
DQO-DQ7
HI-Z
,"
I 14-- tell.(E) ---+t
I
I
?IIf.·
I I
,I
II
II
I
~ tanco)"':
-+J
I
«<<<<<<:
Ollput Valid
Figure 5. Read-Cycle Timing
~1ExAs
7·20
II
I M-- tell.CO) ~
III- tt.(D) ~
I
14- telCO) ,
~I
I
I
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
}»»»}- HI..z -
TMS28F512A
524288-81T FLASH MEMORY
SMJS514A-FEBRUARY 1884-REVlSEDJUNE 1885
PARAMETER MEASUREMENT INFORMATION
Power Up
and
Program-
set-UpProgram
Program
verification
Standbyl .
AO-A15
v~~~~ !~. _--*_
1
1
I I
,.1_--.I.
\'j
'..t
'. t
\\
'i'r--
~ ~tr(VPP)
Figure 6. Wrlte-Cycle Timing
-!i11ExAs
INSTRUMENTS
POST OFFICE. BOX 1443 • HOUSlCN, TEXAS 77251-1443
7-21
TMS28F512A
524288-BITFLASH MEMORY
)
SMJS514A- FEBRUARY 1994 - REVISED JUNE 1985
PARAMETER MEASUREMENTINFOR.",ATION
Program
Command
Latch
Prog.......,
Add.....
Verify
and Data. Programmln,g Comm!ind
Po_r Up Set-Upand
Program
Standby .Command
AO-A15
.~
,---."..
1h(EA)
.
__
1eu(W) ~(4th(W)
/
XI
-"---~. I I
I
--I J+-
I
I
I.
th(ED)
1'vI(E) ...j
DQO-DQ7
..
I
trec(E)W
rrI
f+I
I
~ k- 1h(W)
5V
OV
VPPH
VPP
.VpPL
..
-*I J4" 1h(W)
.I
.\\.
I
.. I
+--I
I
I
I 1
...t
r-
I
~
I
. .1\.I III
H--i I.- 'b(ED)
'vI(E)
'vI(E) ..:
I.-
I
K
I II
It.--.j-
I
.11
~
- I
pr- ~
II
-+! j4-I-lh(D)
Ien(G)
leI(G)
I
It ~
-'lH~
II ~ _~taln'~~(~~! ~i.r ~Data~ut
I
I
...AI
I
I
~
1e(E) 1111
Data In .. COh
\\
II
\\
\...
leu(vpPEL}
\\
--V!
t4
~
II
II I
1+ tr(vpP)
-.I
~1+-tt(VPP)
j4- leu(EHVPP}
Figure 7. Write-Cycle (Alternative 'E-Controlled Writes) TIming
~1ExAs
7·22
leI18(G)
y""I-"""\.
I II I I I
Ih(ED)
\...
-HI III-
\£~"-~
r-""1"" N:
IeU~~
I
I
II
I
1h(EA)
~ j+ ·leu(W) I
·1
\\
. I~ tc(w)B
Data In • 40h
Vce
I+-
I
--l ~ leu(W)
I
I
I
~
I
. ~ tc(R) ~
tc(W)4
.~I.
.
I leu(A)"
-.tI I+-
e..Jf ~. ·MrI
I
r
I
Standbyl
P _ Down
~
..
~
-k----.J I
leu{A)
VI
~~~ ~~'
...
-I--- tc(W)
tc(W) 1111
Program
VerHIcaUon
i.
INSTRtJM:ENTS
POST OFF!CE BOX 1443 • HOUSTON, 'TEXAS 77251-1443
TMS28F512A
524288·8IT FLASH MEMORY
SMJS614A- FEBRUARY 1994 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Power Up
and
AO-A15
Set-UpEraaa
Eras..
Eraaa
Eraas
Verify
Standbyl
~-~--~
1c(W)
I..
J
14-
I---,..,.j ..
i..-f-
I
1c(W) ---.(
"'(A)
1c(W) ~
14-- 1c(R)
I
tau(A)
I
j4""
I
i+" tau(E)
I ->i i<-
I
-t*f
I
~~
-tI ,.. tau(E) I
, ,
I I
: ...., .,1<...., I I -.. ~...., I I
-Ioi i'" ....1El
)
~I!'t\
"t~
/11
I.
~, 1w(WH)
" . , "
I'
II
I,
,
r+- trec(W) ~ ,
I'
trac(R) ,~ j+"
I
I--- Ic(E)B ~
.' " I
!dla(G)
,
I
,
,
I
OOO-DQ7
-*
1w(W)..i!--
,
Vee
BV
OV
11-.114-",
I, I (WHO)
I
...r ,..... 7'(W)
~
,~
--k1
JI
, , I+-
1w(W)
I
...I I.-
' I~
I
t\
,
'\..
VI
~ ~ "'(D)
III
""
I t.I 14- "'(WHO)' " ,.-..r tan (G)
Data
I'
,
fi""
"II
, " I
-tI~ tau(D) ~\ I,
In • 2~h
,JI--' ~(E):"
!
Oats In: AOh
ta(E) ,.
H':;(D)"
I
~~j
t Ik
!dIG)
~ I It&!
~I
Oats.()ut
\...
\l
.
,... tau(vpPEL)
'l;
If(vpp)
tr(VPP)
~
, I
--r ;--
..., ,... tau(EHVPP)
Figure 8. F'ash-Erase-Cycle Timing
-!111ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
7-23
TMS28F512A
524288-BIT FLASH MEMORY .
SMJS514A- FEBRUARY 18114- F\EV1SED.JUNE 1895
7·24
:illExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77211-1443
TMS28F010B
1048576-BIT FLASH MEMORY
FMPACKAGE
CTOPVlEW)
• Organization ••• 128K x 8-Blt Flash Memory
• Pin Compatible With Existing 1-Megablt
EPROMs
• Vee Tolerance ~10%
• All Inputs/Outputs TTL Compatible
• Maximum Access/Minimum Cycle Time
'28F010B-9O
90 ns
'28F01OB-10
100 ns
'28F010B-12
120 ns
'28F010B-15
150 ns
• Industry-Standard Programming Algorithm
• PEP4 Version Available With 168-Hour
Burn-In, and Choice of Operating
Temperature Ranges
(lllI)coa.g
0
28
2:1
28
25
24
A3
A2
A1
AO
DQO
A14
A13
AS
A9
A11
~
23
A10
22
IE
21
DQ7
1415 18 1718 19 20
• 100000 and 10000 Program/Erase-Cycle
Versions Available
• Latchup Immunity of 250 mA on All Input
and Output Unes
• Low Power Plsslpatlon (Vee = 5.5 V)
-Active Write ••• 55 mW
-Active Read ••• 165 mW
-Electrical Erase ••• 82.5 mW
-Standby ••• O.SS mW
(CMOS-Input Levels)
• Automotive Temperature Range
- 40°C to 125°C
0
::(::( ::( ~ ::>1:= z
_(II
o
0
cc
g 8C
(f)C')(§1I)
~g
c
PIN NOMENCLATURE
AO-A18
DQO-OQ7
E
G
NC
VCC
Vpp
VSS
Vi
Address Inputs
Inputs (programmlng)/Outputs
Chip Enable
Output Enable
No Internal Connection
5-V Power Supply
12·V Power Supply
Ground
Write Enable
NOTE: Refer to page 2 for the DO and DU pinouts.
description
The TMS28F01 OB is a 1048 576-bit. programmable read-only memory that can be electrically bulk-erased and
reprogrammed. It is available in 100000 and 10000 program/erase-endurance-cycle versions.
The TMS28F01 OB Flash Memory is offered in a 32-lead plastiC leaded chip-carrier package using 1.25-mm
(50-mil) lead spacing (FM suffix). a 32-lead thin small-outline package (DD suffix). and a reverse pinout TSOP
package (DU suffix).
~1ExAs
INSTRUMENTS
POST OFFICE BOX 14043 • HOUSTON. TEXAS 77251-14043
Copyright C 1995, Texas Insirumenla Incorporated
7·25
TMS28F010B
1048576·BIT FLASH MEMORY
SMJSB24A- MAY 1995 - REVISED JUNE 1995
DDPACKAGE
(TOP VIEW)
A11
A9
AS
A13
A14
NC
Vi
Vee
Vpp
A1S
A15
A12
A7
AS
AS
A4
1
2
3
4
5
8
7
8
9
10
11
12
13
14
15
16
0
32
31
30
G
A10
29
21
D07
DOS
D05
DQ4
DQ3
VSS
D02
D01
DOO
20
AO
19
18
17
A1
A3
32
A11
31
A9
AS
28
'Z1
28
25
24
23
22
~
A2
DUPACKAGE
REVERSE PINOUT
(TOP VIEW)
G
A10
~
D07
DOS
D05
004
D03
VSS
D02
D01
DOO
AO
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
\l
30
29
28
'Z1
28
25
24
23
22
21
20
19
18
17
~ThxAs
7·28
..
INSTRUMENTS
POST OFFICE BOX 1443.- HOUSTON, 'T15XAS 77251-1443
A13
A14
NC
Vi
Vee
Vpp
A1S
A15
A12
A7
AS
AS
A4
TMS28F010B
1048576-BIT FLASH MEMORY
SMJS824A- MAY 1886 - REVISED JUNE 1886
device symbol nomenclature
TMS28F010B
·12
C5
FM
L
L
PEP4 Burn-ln
4 • 168-Hour Bum"n
(blank If no bum..n)
' - - - - - - - - Temperatura Range D..lgnetor
L.
O°C to 70°C
E • - 40°C to asoc
Q
• - 40°C to 1250C
' - - - - - - - - - - Package Deelgnator
FM. Plaallc ....ded Chip Carrier
DD. Thin Small-Outllne Peckage
DU. Thin Small-OlI1Ilne Package,
Reverae Pinout
' - - - - - - - - - - - - Program/Era.. Endurance
C5 • 1OO000Cyclea
C4 • 10000 Cycle.
' - - - - - - - - - - - - - - S p e a d Deelgnator
-eo • 80
·10 • 1OOn.
·12 .. 120n.
·15 .. 150n.
n.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS TI2I1-1443
TMS28F010B
1048576-BIT FLASH MEMORY
SMJS824A- MAY 1995 -REVISED JUNE 1995
logic symbolt
,
AD
A1
A2.
A3
A4
AS
AS
A7
AS
AS
A10
A11
A12
A13
A14
A15
A18
27
28
23
25
4
28
28
3
2
E
G
24
31
DQO
D01
DQ2
D03
DQ4
D05
DQ8
D07
MEMORY
131072 .. 8
o'
5
22
Vi
.FLASH
12
11
10
8
8
7
8
0
> A 131 071
18 ...
....
Lb.
1,2 EN (READ)
1C3 (WRITE)
r
13
4
14
15
17
18
18
20
21
G1
[PWRDWNI
~ G2
A, 3D
V4
A,Z4-1-
.....
tThls symbol Is In accordance with ANSI/IEEE Std 91-1984 and lEe Publication 817-12.
Pin numbers shown are for the FM package.
~1ExAs
7-28
INSTRUMENTS
POST OFFICE BOX 1_ • HOUSTON. 'IeXA8 77251-1_
TMS28F010B
1048576-BIT FLASH MEMORY
SMJS824A- MAY 1886- REVISED JUNE 1886
functional block diagram
DQO-DQ7
-----_.....
Vpp ------4II----_~
W--+-I
ST8
!
Chlp-Enabll and
Output-Enlbll
G
Logic
STa
A
d·
d
r
Column DIcocI...
CoIumnGlllng
I
AO-A18
••
L
R_Decodlr
I
1 048178-B1t
Array Matrix
t
c
h
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7-29
TMS28F010B
1048576-81T FLASH MEMORY
SMJS824A- MAY 1995 - REVISED JUNE 1985
Table 1. Operation Modes
FUNcnONt
MODE
Read
Readl
Write
Vpp*
E
G
(1)
(22)
Read
VpPL
Output Disable
VpPL
Standby lind Write Inhibit
VpPL
AJgorithm.setectlon Mode
Read
At
DQO-DQ7
17-21)
W
(24)
AO
(12)
(28)
(31)
V,L
V,L
X
X
V,H
OataOut
V,L
X
X
V,H
V,H
X
X
X
V,H
X
Hi·Z
VPPL
V,L
V,L
V,D
V,H
Mfr Equivalent Code 89h
DevIce Equivalent Code B4h
VPPH
VpPH
V,L
Output Disable
Standby and Write Inhibit
VPPH
V,L
V,H
X
V,L
V,H
V,L
V,H
X
(13~15,
HI·Z
X
V,H
OataOut
X
X
X
X
V,H
X
HI-Z
HI-Z
Write
Data In
X
X
V,L
V,H
VPPH
V,L
t X can be V,L or V,H.
* VPPL" Vee + 2 V; VPPH Is the programming voltage specified for the device. For more datalls, refer to the recommended operating oonditlons.
operation
read/output disable
Wh.en the outputs of two or more TMS28F01 OBs are connected In parallel on the same bus, the output of any
particular device in the circuit can be read with rio interference from the competing outputs of other devices. To
read the output of the TMS28F010B, a low-level signal is applied to the E and G pins. All other devices in ht
circuit should have their outputs disabled by applying a high-level Signal to one of these pins.
standby and write Inhibit
Active IcC current can be reduced from 30 mA to 1 rnA by applying a high TTL level on E or to 100 t.tA with a
high CMOS level on E.ln this mode, all outputs are in the high-impedance state. The TMS28F01 OB draws active
current when it is deselected during programming, erasure, or program/erase verification. It continues to draw
active current until the operation is terminated.
algorlthm..electlon,mode
The algorithm-selection mode provides access to a binary code identifying the correct programming and erase
algorithms. This mode is activated when A9 (pin 26) is forced to VIC. Two identifier bytes are accessed by
toggling AO. All other addresses must be held low. AO low selects the manufacturer equivalent code 89h, and
AO high selects the device equivalent code B4h, as shown in the algorithm-selection mode table below:
IDENTIFIERS
PINS
AO
DQ7
DQ8
DQ5
DQ4
DQ3
DQ2
DQ1
DQO
Manufacturer Equivalent Code
V,L
1
0
0
0
1
0
0
1
89
Device Equivalent Code
V,H
1
0
1
1
0
1
0
0
64
HEX
IE =(3 =V,L, A1-AB-V,L,A9 -VID,A10-A16 =V,L, VPP "VpPl.
programming and erasure
In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to
a logic O. Afterwards, the entire chip Is erased. N. this point, the bits, now logic 1s, can be programmed
accordingly. Refer to the Fastwrite and Fasterase algorithms for further detail.
~1ExAs
7-30
INSTRUMENTS
POST OFFICE BOl('f443· HOUSTON. 'II!lCAS 77251-1443
1MS28F010B
1048576-BI1 FLASH MEMORY
SMJS824A - MAY 1l18li- REVISED JUNE 1l18li
command register
The command register controls the program and erase functions of the TMS28F01 OB. The algorithm-selection
mode can be activated using the command register In addition to the previously described method. When Vpp
.Is high. the contents of the~mmand re~ster and the function being performed can be changed. The command
register Is written to when E Is low and W Is pulsed low. The address is latched on the leading edge of the pulse.
while the data Is latched on the trailing edge. Accidental programming or erasure is minimized because two
commands must be executed to Invoke either operation. The command register is inhibited when Vee is below
the erase/write lockout voltage. VLKO.
power supply considerations
Each device should have a 0.1-"F ceramic capacitor connected between Vee and Vss to suppress circuit noise.
Changes in current drain on Vpp require it to have a bypass capacitor as well. Printed-circuit traces.for both
power supplies should be appropriate to handle the current demand.
Table 2. Command Definitions
COMMAND
Read
AIgorIIhm-Se1ectlon Mode
Set·Up-Eraee/Eraee
EraeeVerify
Set·Up-Program/Program
Program Verify
REQUIRED
BUS
CYCLES
1
SECOND BUS CYCLE
FIRST BUS CYCLE
OPERATIONt
Write
ADDRESS
X
DATA
00h
OPERATIONt
Read
3
Write
X
90h
Read
2
2
2
2
.2
Write
X
EA
X
X
X
20h
Write
AOh
40h
COh
Write
Write
Write
POST OFFICE 80X 1443 • HOUSTON. TEXAS 772S1-1443
RA
0000
DATA
. RD
89h
0001
B4h
Read
X
X
20h
EVD
Write
PA
PO
Read
X
X
PVD
Reset
FFh
Write
Write
t Mod.. of operation are defined in Table 1.
Legend:
EA
Addl'888 of memory location to be reed during eraee verify
RA
Addl'888 of memory location to be reed
PA
Addl'888 of memory location to be programmed. Addl'888 Is latched on the falling edge of Vii
RD
Data read from location RA during the read operation
EVD
Data reed from location EA during eraee verify
PO
Data to be programmed at location PA. Data is latched .on the rising edge of Vii
PVD
Data read from location PA during program verify
-!l1ExAs
INSTRUMENTS
ADDRESS
FFh
7-31
TMS28F010B
1048576-8IT FLASH MEMORY
SMJSB24A- MAY 1996 - REVISED JUNE 1996
command definitions
read command
Memory contents cen be accessed while Vpp is high or low. When Vpp Is high, writing OOh Into the command
register invokes the read operation. When the device is powered up, the default contents of the command
register are OOh and the read operation is enabled. The read operation remains enabled until a different valid
command Is written to the command register.
algorithm-selection mode command
The algorithm-selection mode is activated by writing 90h into the command register. The
manufacturer-equlvalent code (89h) is identified by the value read from address location OOOOh, and the
device-equivalent code (B4h) Is identified by the value read from address location 0001 h.
.
set-up-erase/erase commands
Theerase-aigorlthminitiateswithE=VIL,W=VIL,G=VIH,VPP=VpPH,andVee =5V. To enter the erase mode,
write the set-up-erase command, 20h, into the command register. After the TMS28F01 OB is'in the erase mode,
writing a second erase command, 20h, into the command register Invokes the erase operation. The erase
operation begins on the rising edge ofW and ends on the rising edge of the next W. The erase operation requires
at least 9.5 ms to complete before the erase-verify command, AOh, cen be loaded.
Maximum erase timing is controlled by the Internal stop timer. When the stop timer terminates the erase
operation, the device enters an inactive state and remains Inactive until a command Is received.
program-verify command
The TMS28F01 OB can be programmed sequentially or randomly because It Is programmed one byte at a time.
Each byte must be verified after It is programmed. The program-verify operation prepares the device to verify
the most recently programmed byte. To Invoke the program-verify operation, COh must be written into the
command register. The program-verify operation ends on the rising edge of W.
While verifying a byte, the TMS28F01 OB applies an internal margin voltage to the designated bYte. If the true
data and programmed data match, programming continues to the next designated byte location; otherwise, the
byte must be reprogrammed. Figure 1 shows how commands and bus operations are combined for byte
programming.
'
erase-verify command
All bytes must be verified following an erase operation. After the erase operation is complete, an erased byte
can be verified by writing the erase-verify command, AOh, into the command register. This command causes
the device to exit the erase mode on the rising edge of W. The address of the byte to be verified is latched on
the failing edge of W. The erase-verify operation remains enabled until a command is written to the command
register.
To determine whether or not all the bytes have been erased, the TMS28F01 OB applies a margin voltage to each
byte. If FFh is read from the byte, all bits In the designated byte have been erased. The erase-verify operation
continues until all of the bytes have been verified. If FFh Is not read from a byte, an additional erase operation
needs to be executed. Figure 2 shows the combination of commands and bus operations for electrically erasing
the TMS28F010B.
set-up-program/program commands
The programming algorithm initiates with E = VIL, W = VIL, G = VIH, Vpp = VPPH, and Vee = 5 V. To enter the
programming mode, write the set-up-program command, 4Oh, Into the command register. The programml~
operation Is Invoked by the next write-enable pulse. Addresses are latched internally on the falling edge of ViI,
an~data is latched Internally on the rising edQ! of W. The programming operation begins on the rising edge
of Wand ends on the rising edge of the next W pulse. The program operation requires 10 !AS for completion
before the program-verify command, COh, can be loaded.
~TEXAS
INSTRUMENTS
7-32
POST OFFICE BOX 1443 • HOUSTON, lEXA8 77251-1443
TMS28F010B
1048576-BIT FLASH MEMORY
SMJS824A- MAY 1995 - REVISED JUNE 1996
set-up-program/program commands (continued)
Maximum program timing Is controlled by the internal stop timer. When the stop timer terminates the program
operation, the device enters an inactive state and remains inactive until a command is received.
reset command
To reset the TMS28F010B after set-up-erase command or set-up-program command operations without
changing the conten~ in memory, write FFh into the command register two consecutive times. After executing
the reset command, the device defaults to the read mode.
Fastwrlte algorithm
The TMS28F010B Is programmed using the Texas Instruments Fastwrite algorithm shown in Figure 1. This
algorithm programs in a nominal time of two seconds.
Fasterase algorithm
The TMS28F01 OB is erased using the Texas Instruments Fasterase algorithm shown In Figure 2. The memory
array needs to be completely programmed (using the Fastwrite algorithm) before erasure begins. Erasure
typically occurs in one second.
parallel erasure
To reduce total erase time, several devices can be erased In parallel. Since each Flash Memory can erase. at
a different rate, every device must be verified separately after each erase pulse. After a given device has been
successfully erased, the erase command should not be issued to this device again. All devices that complete
erasure should be masked until the parallel erasure process is finished (see Figure 3).
Examples of how to mask a device during parallel erase include driving the E pin high, writing the read command
(OOh) to the device when the others receive a set-up-erase or erase command, or disconnecting it from all
electrical signals with.relays or other types of switches.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 772151-1443
7-33
TMS28F010B
1048576-BIT FLASH MEMORY
SMJS824A- MAY 111e6 - REVISED JUNE 111e6
-T
Bue
OperaUon
Command
Commen..
In/tllllize
Add,...
walt tor VPP to ramp to
VPPH (e.. Note A)
Standby
Setup
Initialize pul. . count
WrItII
SetoUp-
D.... 40h
Program
Write
WrItII
WrIte Data
Standby
WrItII
Interactive
Mode
Power
Down
L
Walt-1°tlll
Programvarlfy
Data _ COh; ende
Program operation
Standby
Wait-Still
Read
R..d byte to verify
Programming; compere
output to expected outPut
-
-
-
WrIte
Read
Data. OOh; raaeta regleter
for read operetlone
Standby
NOTES: A. Refer to the recommended operating conditions for the value of VPPH.
B. Refer to the recommended operating conditions for the value of VPPL.
Figure 1. Programming Flowchart: Fastwrlta Algorithm
~TEXAS
INSTRUMENTS
7-34
valid add,.../data
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
Walt tor VPP to remp to
VPPL (e. . Note B)
TMS28F010B
1048576-BIT FLASH MEMORY
SMJS824A - MAY 1995 - REVISED JUNE 1995
Bua
OperaUon
Command
Commenta
Entire memory muat • DOh
before eraaure
Uae Faetwrlte
prollremmlnll aillorithm
Initialize add.......
Setup
walt for Vpp to ramp to
VPPH (aee Note A)
Standby
Initialize pulae count
Interactive
Mode
Write
Set-UpEre..
Data.20h
WrIt.
Era..
Data .. 20h
Standby
WrIte
P~r
Walt.10ma
Eraae
Verify
=6j18
Standby
walt
R(HId
Read byte to verify eraaure;
compare output to FFh
Write
Read
Down
l
Addr .. Byte to verify;
Data • AOh; enda the eraae
operaUon
Standby
Data .. DOh; reeate relilatar
for read operatlona
Walt for Vpp to ramp to
VpPL (aee Note B)
NOTES: A. Refer to the recommended operating conditiOns for the value of VpPH.
B. Refer to the recommended operating conditions for the value of VpPL.
Figure 2. Flash-Erase_Flowchart: Fasterase Algorithm
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
7-35
TMS28F010B
1048576-BIT FLASH ME~ORY
SMJS824A - MAY 111115 - REVISED JUNE 111115
GIveE,...
Command to
AnUnmeaked
DavIe..
No
GIveR.ad
Command to
GlveR..d
Command to
A1IDev1c..
All Devle..
tn. number of devices being erased.
FIgure 3. P~rall.I-Era.. Flow Diagram
~1ExAs
7-38
INSlRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS28F010B
1048576-BIT FLASH MEMORY
SMJS824A- MAY 1995 - REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .:............................................ -0.6 V to 7 V
Supply voltage range, Vpp ..........•....................................•......... -0;6 V to 14 V
Input voltage range (see Note 2): All inputs except A9 ........................... -0.6 V to Vee + 1 V
A9 ............•..•............................... -0.6 V to 13.5 V
Output voltage range (see Note 3) .............•..•.......•................... -0.6 V to Vee + 1 V
Operating free-air temperature range during read/erase/program, TA
L ................•................................... DoC to 70°C
E .......•..............................•.•.•...... - 40°C to 85°C
Q .....................•......................... -40°Cto 125°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
t Stresses beyond thosellstad under "absolute maximum ratings" may cause permanent damage to the device. Thasa are stress ratings only, and
functlonal operation of the devica at thasa or any other conditions beyond those Indicated under "recommended operating conditions" is not
Implied. Exposure to absolute-maxlmum-ratad conditions for extended periods may affect davica reliability.
NOTES: 1. All wltage values are with raspactto VSS •.
2. The wltage on any Input pin can undershoot to -2 V for periods lass than 20 ns.
3. The wltage on any output pin can overshoot to 7 V for periods lass than 20 ns.
recommended operating conditions
Vee
Supply wltage
Vpp
Supply wltage
VIH
High-laval de Input wltage
VjL
Low-Ieval de Input wltage
VID
Voltage laval on AS for algorlthm-selactlon mode
MIN
4.5
0
11.4
During write/read/flash erase
During read only (VppL,)
During write/read/flash erase (VppH>
TTL
eMOS
TTL
eMOS
-!111ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUlTON. TEXAS 772151-1443
2
Vee- 0•5
-0.5
GND-0.2
11.5
TYP
MAX
5
5.5
12
Vee+ 2
12.6
Vee+ 0•5
Vee +0.5
0.8
GND+0.2
13
UNIT
V
V
V
V
V
V
7-37
TMS28F010B
1048576-BIT FLASH.MEMORY
SMJS824A- MAY 1986 - REVISED JUNE 1986
electrical characteristics over recommended ranges of supply voltage and operating free..lr
temperature
TEST CONDITIONS
PARAMETER
VOH
High-level output voltage
VOL
Low-ievel output voltage
110
A9 algorithm-aelection-mode current
MAX
IOl-S.8rnA
0.45
10l .. 100 JAA
0.1
A9=VIDmax
VI'" OVto5.5V
VI-OVto13V
UNIT
V
VCC- 0•4
IoH=-100jAA
I All except A9
MIN
2.4
10H = - 2.5 rnA
V
200
:t1
:t2OO
JAA
:t10
JAA
JAA
JAA
II
Input current (leakage)
10
Output current (leakage)
VO .. OVtoVCC
IpPf
VPP supply current (read/standby)
VPP=VPPH.
VPP=VPPl·
IPP2
VPP supply current (during progrsm pulse) (see Note 4)
VPP-VpPH
30
IPP3
VPP supply current (during flash erase) (see Note 4)
VpP-VpPH
30
rnA
mA
IpP4
VPP supply current (during progrsm / erase-verify)
(see Note 4)
VPP=VPPH
5.0
mA
ICCS
Vcc supply current (standby)
1
mA
ICC1
1CC2
1A9
I TTL-Input level
I CMOS-Input level
VCC .. 5.5V•
Read mode
VCC=5.5V.
E=VIH
E=VCC
VCC supply current (active read)
VCC=5.5V
h6MHz.
E=Vll.
10UT=OmA
VCC aversge supply current (active write) (see Note 4)
1CC3 . VCC aversge supply currsnt (flash erase) (see Note 4)
ICC4
Vcc aversge supply current (progrsm/erase-verlfy)
(see Note 4)
VLKO Vcc erase/write-lockout voltage
NOTE 4: Not 100% tested; characterization data avedable.
200
:t10
JAA
100
JAA
30
mA
Vcc= 5.5V.
E-Vll.
.Progrsmmlng In progress
10
mA
Vcc= 5.5V.
E.Vll.
Erasure In progress
15
rnA
VCC- 5•5V•
E =Vllo
VPP=VpPH.
Progrsm / erase-verify In prograss
15
rnA
V
2.5
VpP=VPPH
capacitance over recommended ranges of supply voltage and operating free..lr temperature,
f 1 MHzt
=
TEST CONDITIONS
PARAMETER
Input capscitance
CI
Output capscltance
Co
t capacitance measurements are made on sample basis only.
VI=OV. 1=1 MHz
Vo .. 0 V. f .. 1 MHz
~1ExAs
INSTRUMENTS .
7-38
POST OFFICE
sox 1443· HOUSTON. TEXAS n2S1-1443
MIN
MAX
6
12
UNIT
pF
pF
TMS28F010B
1048576·81T FLASH MEMORY
SMJSB24A-MAV 1995-REVlSEDJUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature
PARAMETER
TEST
CONDITIONS
ALTERNATE
SYMBOL
'28F010B-90
MIN
MAX
'28F01OB-10
MIN
MAX
'28F01OB-12
MIN
MAX
'28F010B-15
MIN
MAX
UNIT
ta(A)
Access time from
address,
AO-A16
lAVQV
90
100
120
150
ns
ta(E)
Access time from
chip enable, E
tELQV
90
100
120
150
ns
1en(G)
Access time from
output enable, (I
tGLQV
35
45
50
55
ns
1c(R)
Cycle time, read
lAVAV
90
100
120
150
ns
1d(E)
Delay time, E low
to low-Z output
tELQX
0
0
0
0
ns
Id(G)
Delaytlme,G
Iowtolow-Z
output
tGLQX
0
0
0
0
ns
1d1s(E)
Chip disable time
to Hi-Z output
tEHQZ
0
45
0
55
0
55
0
55
ns
ldis(G)
Output disable
time to Hi-Z
output
tGHOZ
0
30
0
30
0
30
0
35
ns
1h(D)
Hold time, data
valid from
address, E or (It
IAXQX
0
0
0
0
ns
twHGL
6
6
8
6
I'll
Write recovery
time before read
t Whichever occurs first
trec(W)
CL= 1OOpF,
1 Series 74
TTL load,
Input tr "' 20 ns,
Input tf "' 20 ns
~TEXAS
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON, TEXAS 77251-1443
7-39
TMS28F010B
104857&-BIT FLASH MEMORY
SMJSB24A- MAY 11195 - REVISED JUNE 1996
timing requlrements-wrlte/erase/program operations
'28F010B-80
MIN NOM MAX
ALTERNATE
SYMBOL
PARAMETER
'28F010B-10
MIN
100
NOM
MAX
UNIT
tclWl
Cycle time, write using W
tclWlPR
tc(W)ER
lilIAI'
Cycle time, programming operation
twHWH1
90
10
Cycle time, erase operation'
twHWH2
9.5
9.5
twI..Ax
40
55
lillEl
th{WtlO).
Holdtlme,~
lWHEH
twHox
0
10
lAVWL
tOVWH
0
0
10
,0
40
50
na
teLWl
tvPEL
15
20
na
1
lWHGL
6
0
1
6
J4II
J4II
J4II
taulAI
taueO)
taueE)
tauNPPELI
trac(W)
lAVAV
Hold time, address
Hold time, date valid afl8r W high
Setup time, address
Setup time, data
Setup time,,! before W
Setup time, Vpp to ! gOing low
Recovery time, Wbefore read
trac(R)
Recovery time, read before W
IGHWl
twlWl
tw(WH)
Pulse duration, W(see Nots 5)
Pulse duration, W high
twLWH
twHWl
trcvpP)
Rise time, Vpp
Fall time, Vpp
tvPPR
tvPPF
ttNPPI
J4II
10
m.
n.
na
n.
na
0
40
eo
20
1
20
na
ns
1
1
J4II
J4II
1
'28F010B-12
ALTERNATE
SYMBOL
PARAMETER
n.
10
MIN
NOM
MAX
'28F010B-15
MIN
NOM
MAX
UNIT
tclWl
tc(W)PR
Cycle time, write using W
Cycle time, programming operation
lWHWH1
120
10
tclWlER
lillAI
lileE)
lil(WHO)
Cycle time, erase operation
twHWH2
9.5
twI..Ax
60
eo
ns
twHEH
0
10
0
10
ns
ns
taueAI
taueD)
tau(E)
Setup time, address
Setup time, data
tauNPPELl
trac(W)
trac(R)
twlWl
tw(WH)
Hold time, address
Hold time, E
Hold time, data valid afl8r W high
tAVAV
lWHox
tAVWL
10
9.5
ns
J4II
10
me
0
0
tOVWH
50
50
Setup time, E before W
tELWl
20
Setup time, Vpp to E low
tvPEL
twHGL
20
1
ns
ns
ns
1
6
0
J4II
J4II
J4II
Recovery time, Wbefore read
Recovery time, read before W
IGHWL
6
0
Pulse duration, W(sea Nots 5)
twLWH
eo
eo
ns
twHWl
20
20
ns
tvPPR
1
1
tvPPF
1
1
J4II
J4II
Pulse duration, W high
Rise time, Vpp
trNPP)
Fall time, Vpp
ttNPP)
NOTE 5: RISe/fail time" 10 na
,/
~TEXAS
7-40
150
10
.
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS28F010B
1048576·BIT FLASH MEMORY
SMJS824A- MAY , . - REVISED JUNE , .
timing requirements - alternative !-controlled writes
ALTERNATE
PARAMETER
SYMBOL
Cycle time, write using l
Cycle time, programming
operation
'28F01011-10
'28F010B-80
MIN
MAX
MIN
'28F01011-12
MAX
MIN
MAX
'28F01OB-15
MIN
MAX
UNIT
lAVAV
90
100
120
150
118
tEHEH
10
10
10
10
....
Hold time, addrass
tELAX
45
76
80
80
118
Hold time, data
Holdtlme,W
tEHDX
10
10
10
10
118
tEHWH
0
0
0
0
118
lAVEL
tDVEH
0
0
0
0
118
tsuCO)
Setup time, addrass
Setup time, data
35
50
50
50
118
tsulWl
Setup time, W before E
0
0
0
0
tsuCVPPEU
1
1
1
1
trec(E)R
Setup time, Vpp to E low
Recovery time, write using l
before read
twLEL
tvPEL
tEHGL
8
8
8
8
trec(E)W
Reooverytlme, read before
write uaIng !
IGHEL
0
0
0
0
....
....
....
1w(E)
Pulae duration, write ua/ng !
tELEH
45
70
70
70
118
Iw(EH)
Pulae duration, write, l high
tEHEL
20
20
20
20
118
tc(W)
tc(E)PR
IhIEAI
Ih(ED)
IhIWl
tsuCAl
118
PARAMETER MEASUREMENT INFORMATION
-4
2.08 V
Output
UnderT_
.
RL • 8000
T
CL·'00pF
(..eNoteA)
NOTE A: CL Includ. probe and fixture capacitance.
Figure 4. AC Test Output Load Circuit
AC testing Input/output waveforms
a::=x!.:v
O.!~ X'--__
AC testing inputs are driven at 2.4 V for logic high and 0.45 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low on both inputs and outputs. Each device should have a O.1-"F ceramic
capacitor connected between Vee and VSS as clOSE! as possible to the device pins.
~1ExAs
INSTRUMENTS
POITOFFICE BOX 1443· HOUS'TCN. TEXAS 772&1-1448
7....,
TMS28F010B
1048576-BIT FLASH MEMORY
SMJS824A- MAY 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tc(R) ------+l~1
I"
I
I
AO-AI.-----.....,.X
X.,-------
Add..... Valid
I"
E-------~~~
~I
ta(A)
I
________~I-----~~11~i------------I I4-ldla(E) ~
I
I+- ta(E) ---l
I
Q-----------~I~f\
14-1
I
rec(W)
wJ
~
I -j
~ tan(G) ~I
I
I
I
II
I +i
1d(E) . I"
DQO-DQ7
HI.z
l~
I+- Id(G)
~I
II
em
II
I I
I
II·
I
I i4--1d18(G) ~
I+- "'(0) ~
I
I
Ouput Valid
Figure 5. Read-Cycle Timing
7-42
",
I I
-!111ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, 1EXAS 77251-1443
}»»»r
HI.z -
TMS28F010B
1048576-BIT FLASH MEMORY
SMJS824A- MAY 11195 - REVISED JUNE 1986
PARAMETER MEASUREMENT INFORMATION
Program
Command
Latch
Program
Add.....
Verify
and Data Programmlnll Command
Power Up SetoUpand
Program
Standby Command
~I:~~~~
4
I
I ~ I+-1 I+'--+
AO-A18
~~ 1c(W) --tI
1c(W)-
"u(E)
/
r~
~IfI(E)I
_J.~_~ I
trec(R) I ~
I-
I
1
IfI(WHD~ t.t
1w(W)
DQO-DQ7
r-
~ I+- IfI(E)
I
I
I
I
1+--Ic(W)PR
~I 1w~H)
r1
I
I
II
II r-
r-
-L-....I
I
I+-lrac~
I
I/""'I-'""'\..
l' I
J
-ttl I
I II
Of.i I+- IcIla(G)
~jllil
I
-.I
I
~ I+- IfI(E) I I
I
II
I 11\
th(WHD)
!i.ll.I
IfI(WHD)111
1w(W) -.I I.-
1w(W)
I I
II\..
~ C~~(D)
M---.t- lcI(o)
I
"U(D)~I.-~(D) ~(D)
I.II!! ((
l.J. I ~
---r- HI-Z
\
~ »1---\..
J
ov
II
Vcc llV
VPP
-tI
I
~~
-.I j4- "u(E) I
i~~
I+-
I
I
I
I
"u(A)
-+I j4" "u(E)
-.j,..
~
IfI(A)
th(A)
Standbyl
Power Down
~ 1c(R) ---+-t
,1c(W)
"u(A) -k---,.j
G
Program
VerltlcaUon
--I:I
Data In
Data In .. 40h
I
I
I
I+-
Data In .. COh
I-II_ JiS8Ud
1cI(E)
"(E)
II
'II
II
'/;
~I
Data-Out
"u(vpPEL)
VPPL
-+I 1+ 1r(VPP)
Rgure 6. Write-Cycle Timing
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lCXAS 77251-1443
7-43
TMS28F010B
1048576-BIT FLASH MEMORY
SMJS824A- MAY 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Program
Command
Latch
Program
Add,...
Verify
and Data Programming Command
Power Up Set.lJpand
Program
Standby Command
AO-A18
~I-14-; ~~~~~
4
..-1c(W} -+I
I
1c(W}-
I
I
-k--+I
...
...(EA) ...tLo....
I ,..-
tau(A)
.
,----,. ...._~
tau(W)
-.j~
It!(W}
/
I
It!(ED)
I
--t t4'"
-.j
tw(E)
r-
..j
I
r- I
j4-
tau(W)
I
~ 14- It!(W}
I
I
BV
ov
-..
I
I I
tI r-
...t
r-
I
~
tw(E)
I
r-- It!(W}
I
1\.
\\
,I -
III
I It!(ED)
\....
IelIa(G)
I II
Y"'I--\
-
I
'-
pr-~
III
,II'
II
~j4+It!(D)
I
H.! t.- It!(ED) I II K tan(O)
tw(E) -.l I.- I I I t.--.j- IeIIG) 1
tau~~II1t~
-r-H~ II ~. _ u~taln'~~(E) t! ~_I ~dData'()ut
..I
I
Data In • COh
ta(E) I_
\\
fl.
fl;
'I;
I
I
~ tau(vpPEL)
--"
I I
~
\....
~
I I
~1+-tr(VPP)
1+tr(VPP)
Figure 7. Write-Cycle (Alternative !·Controlled Writes) Timing
~TEXAS
7-44
~
-t+I
II
-H
r ~~N:
~
1+
StandbyI
Power Down
I
j+ tau(W) I
I
I
\\
1+-Ic(E)PR
Data In • 40h
Vce
It!(EA)
I
r......
1
I
~
~ ~
1c(R)
~
I tau(A)
\
M \£:
EJ~--I..
1c(W}
I
XI I
1
:.- trac(E)W
--'--~~
DQO-D07
Program
VerHlcaUon
INSTRUMENTS
POST OFFICE BOX 1443 eHOUS'TON; 'T1!XAS 77251-1443
TMS28F010B
1048576-BIT FLASH MEMORY
SMJS824A- MAY 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Power Up Set-u,..
and
Era..
Standby Command
AO-A1.
Eraaa
Command
Era_
Verify
Command
Eraalnll
~mx _~
I.
..I
I
I-~
I------I
I
tc(W)
tc(W)
-.j
tc(W)
I
!
~--t.......
1
I
'It
I
I
I
III
Ita(WHD~ +.l
~
IwIW) -101
rI
tau(D)'"
VCC
sv
ov
-r- HI~
I
J
--!
~
......- tc(R) ,...
I
... 1ta(A)
I
~t.u(A)
~~
-101 j+I I
I I
j4" t.u(E)
DQO-DQ7
Era..
Standbyl
VerltlcaUon Po_ Down
~,..
t.u(E) I
"""I :.- 1ta(E) I I
-+-I 14- tella(E)
11\II'j~
Ita(E)
I
I
I
I
I
!4~
I II
II
~ I
II
: - - - tc(W)ER
I II I
I+- tells(G)
~~;
I1II
,-1
\
I
VI
I II I
~ ~ th(D) ' 11-.it.-Ita(WHD)
III
III1
I
II I
I t..! t.- Ita(WHD) I II I i ten(G)
.....! ~ t;w(W)
1w(W) .....I I.I :
teI(G)
-+II.- tau(D)
: I
1w(WH)
I
'-"H
~,;
>--A85~
34
2
DQ7
FLASH
EEPROM
85536 .. 16
35
E
DQ1
DQ2
DQ3
DQ4
- DQ5
DQ6
o ..
21
22
23
24
25
26
27
26
28
31
32
33
15 ....
"
~
L-t:.
L-+
18
17
16
15
14
13
12
10
8
8
7
6
5
4
3
G1
(PWRDWN]
;:
G2
1. 2 EN (READ)
1C3 (WRITE)
W
,
~
r
A, 3D
V4
A,Z4--
a:
Il.
~r
....
b
::l
....
o
,r
C
a:
Il.
.r
tThIs symbol Is In accordance with ANSI/IEEE Std 91-1884 and lEe Publication 617-12.
Pin numbelS shown are for the N package.
-!!1TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7-49
TMS28F210
1048576-BIT FLASH MEMORY
SMJS210B - DECEMBER 1992 - REVISED JUNE 1995
functional block diagram
vpp __________~~----~~
\V---t......
STa
E
Chlp-Enabll and
Output-Enabll
logic
Q
-a
XI
0
C
c:
Column Decodlr
Column Gating
RowDlCOcIlr
1 048578-8lt
ArnyMatrlx
0
-I
-a
XI
m
<
m
AO-A15
18
L
a
t
c
-
h
:e
~1EXAs
7-50
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 'ICXAS 77251-1443
TMS28F210
1048576-81T FLASH MEMORY
SMJS210B - DECEMBER 1992 - REVISED JUNE 1995
Table 1. Operation Modes
FUNCTIONt
NPACKAGE
MODE
FNPACKAGE
Read
Vpp*
E
Q
AD
AI
W
DQO-DQ15
1
2
20
21
31
39
3-10,12-19
2
3
22
24
35
43
21-14,11-4
Read
VPPL
VIL
VIL
Data Out
VPPL
VIL
VIH
VIH
Hi-Z
Standby and Write Inhibit
VpPL
VIH
X
X
X
X
VIH
Output Disable
X
X
X
AlgorithmoSelection Mode
VIL
VPPL
VIL
Read
VpPH
VIL
VIL
Readl
Output Disable
VPPH
VIL
VIH
Write
Standby and Write Inhibit
VPPH
VIH
X
Write
VPPH
VIL
VIH
X
HI-Z
Mfr Equivalent Code 0097h
VIL
VIH
X
X
X
X
VIO
VIH
X
X
X
X
VIH
Data Out
VIH
HI-Z
Device Equivalent Code OOESh
X
HI-Z
VIL
Data In
*
t X can be VIL or VIH.
VPPL s: VCC + 2 V; VpPH Is the programming voltage specified for the device. For more details, see the recommended operating conditions.
operation
read/output disable
When the outputs of two or more TMS28F21 Os are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from the competing outputs of other devices. To
read the output ofthe TMS28F21 0, a low-level signal is applied to the E and Gpins. All other devices In the circuit
should have their outputs disabled by applying a high-level Signal to one of these pins.
standby and write Inhibit
Active ICC current can be reduced from 50 rnA to 1 mA by applying a high TTL level on E or to 100 J.IA with a
high CMOS level on E. In this mode, all outputs are in the high-impedance state. The TMS28F21 0 draws active
current when it is deselected during programming, erasure, or program/erase verification. It continues to draw
active current until the operation is terminated.
algorlthm-selectlon mode
The algorithm-selection mode provides access to a binary code identifying the correct programming and erase
algorithms. This mode is activated when A9 is forced to VID. Two identifier bytes are accessed by toggling AO.
All other addresses must be held low. AO low selects the manufacturer-equivalent code oo97h, and AO high
selects the device-equivalent code 00E5h,as shown in the algorithm-selection mode table below:
IDENTIFIER'
Manufacturer-Equivalent Code
PINS§
AD
DQ7
DQS
DQ5
DQ4
DQ3
DQ2
DQl
DQO
HEX
VIL
1
0
0
1
0
1
1
1
0097
0
0
1
0
1
OOES
Device-Equivalent Code
1
1
1
VIH
OB-015 are not shown In the table because the upper8d ata b'its read O.
''E G .. Al-AS.= Al0-A15 .. VIL, As" VIO, VPP = VpPL
=
programming and erasure
In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to
a logic O. Afterwards, the entire chip is erased. At this pOint, the bits, now logic 1s, can be programmed
accordingly. Refer to the Fastwrite and Fasterase algorithms for further detail.
~1ExAs
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON. TEXAS 77251-1443
7-51
TMS28F210
1048576-8IT FLASH MEMORY
SMJS210B - DECEMBER 1992 - REVISED JUNE 1996
command regIster
The command register controls the program and erase functions of the TMS28F21 O. The algorithm-sEilection
mode can be activated using the command register in addition to the previously described method. When Vpp
Is high, the contents of the~mmand r~ister and the function being performed can be changed. The command
register is written to when E is low and W is pulsed low. The address is latched on the leading edge of the pulse,
while the data is latched on the trailing edge. Accidental programming or erasure is minimized because .two
commands must be executed to invoke either operation.
power supply consIderations
Each device should have a O.1·"F ceramic capacitor connected between Vee and Vss to suppress circuit noise.
Changes in current drain on Vpp require it to have a bypass capacitor as Well. Printed circuit traces for both
power supplies should be appropriate to handle the current demand.
Table 2. Command DefinItIons
COMMAND
REQUIRED
BUS
CycU:S
OPERATIONt
ADDRESS
DATA
OPERATIONt
ADDRESS
1
Write
X
ooooh
Read
RA
RD
0000
0097h
OOESh·
Read
SECOND BUS CYCU:
FIRST BUS CYCU:
DATA
."
Algorithm-SelecUon Mode
3
Write
X
OO9Oh
Read
0001
o
Set-Up-Erase/Erase
Write
X
0020h
Write
X
20h
Write
EA
00A0h
Read
x
EVD
c:
Set-Up-Program/Program
2
2
2
2
2
Write
X
X
0040h
Write
PA
PO
Write
00C0h
Read
X
PVO
Write
X
OOFFh
Write
X
OOFFh
:D
C
£t
."
:D
-~
~
Erase Verify
Program Verify
Reset
t Modes of operation are defined in Tabla 1•
Legend:
EA
RA
PA
RD
evD
PO
PVO
.
Address of memory location to be read during erase verify
Address of memory location to be read
Address of memory location to be programmed. Address is latched on the falling edge of iN.
Data read frory'llocation RA during the read operation
Data read from location eA during erase verify
Data to be programmed at location PA. Data is latched on the riSing edge of W.
Data read from location PA during program verify
~1ExAs
7-52
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS28F210
1048576-8IT FLASH MEMORY
SMJS210B - DECEMBER 1992 - REVISED JUNE 1995
command definitions
read command
Memory contents can be accessed while Vpp is high or low. When Vpp Is high, writing OOOOh into the command
register invokes the read operation. When the device is powered up, the default contents of the command
register are OOOOh and the read operation is enabled. The read operation remains enabled until a different valid
command is written to the command register.
algorithm-selection-mode command
The algorithm-selection mode is activated by writing 0090h into the command register. The manufacturer
equivalent code (0097h) is identified by the value read from address location ooOOh, and the device equivalent
code (00E5h) is identified by the value read from address location 0001 h.
set-up-program/program commands
The programming algorithm initiates with E = VIL, W = VIL, G" = VIH, Vpp = VpPH, and Vee = 5 V. To enter the
programming mode, write the set-up-program command, 0040h, Into the command register. The programmi!!J
operation is invoked by the next write-enable pulse. Addresses are latched internally on the falling edge of W,
and data is latched internally on the rising edQ! of W. The programming operation begins on the rising edge
of W and ends on the rising edge of the next W pulse. The program operation requires 10 J.t.S for completion
before the program-verify command, OOCOh, can be loaded.
Maximum program timing is controlled by the internal stop timer. When the stop timer terminates the program
operation, the device enters an inactive state and remains inactive until a valid program-verify, read, or reset
command Is received.
program-verify command
;:
W
~
a:
a.
The TMS28F21 0 can be programmed sequentially or randomly because it is programmed one word at a time.
Each word must be verified after It Is programmed. The program-verify operation prepares the device to verify
the most recently programmed word. To invoke the program-verify operation, OOCOh must be written into the
command register. The program-verify operation. ends on the rising edge of W.
t;
While verifying a word, the TM$28F21 0 applies an internal margin voltage to the designated word. If the true
data and programmed data match, programming continues to the next designated word location; otherwise, the
word must be reprogrammed. Figure 1 shows how commands and bus operations are combined for word
programming.
oa:
set-up-erase/erase commands
TheerasealgorithminitiateswithE=VIL,W=VIL,G"=VIH,VPP=VpPH,andVee=5V.Toentertheerasemode,
write the set-up-erase command, 0020h, into the command register. After the TMS28F21 0 is in the erase mode,
writing a second erase command, 0020h, Into the command register invokes the erase operation. The erase
operation begins on the rising edge of Wand ends on the rising edge of the next W. The erase operation requires
10 ms to complete before the erase-verify command, OOAOh, can be loaded.
Maximum erase timing is controlled by the internal stop timer. When the stop timer terminates the erase
operation, the device enters an inactive state and remains Inactive until a valid erase-verify, read, or reset
command is received.
erase-verify command
All words must be verified following an erase operation. After the erase operation is complete, an erased word
can be verified by writing the erase-verify command, ooAOh, into the command register. This command causes
the device to exit the erase mode on the rising edge of W. The address of the word to be verified is latched on
the falling edge of W. The erase-verify operation remains enabled until a valid command is written to the
command register.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7-53
;:)
C
a.
TMS28F210
1048576-8IT FLASH MEMORY
SMJS210B- DECEMBER 1992 - REV1SED JUNE 1995
erase-verify command (continued)
To determine whether or not all the words have been erased, the TMS28F21 0 applies a margin voltage to each
word. If FFFFh Is read from the word, all bits in the designated word have been erased. The erase-verify
operation continues until all of the words have been verified. If FFFFh is not.read from a word, an additional erase
operation needs to be executed. Figure 2 shows the combination of commands and bus operations for
electrically erasing the TMS28F21 O.
reset command
To reset the TMS28F210 after set-up-erase command or set-up-program command operations without
changing the contents In memory, write OOFFh into the command register two consecutive times. After
executing the reset command, a valid command must be written into the command register to change to a new
state.
Fastwrlte algorithm
The TMS28F210 is programmed using the Texas Instruments Fastwrite algorithm shown In Rgure 1. This
algorithm programs in a nominal time of two seconds.
"o
Fasterase algorithm
::D
The TMS28F21 0 is erased using the Texas Instruments Fasterase algorithm shown in Figure 2. The memory
array needs to be completely programmed (using the Fastwrite algorithm) before erasure begins. Erasure
typically occurs in one second.
C
c:
~
parallel erasure
To reduce total erase time, several devices can be erased In parallel. Since each Flash EEPROM can erase
at a different rate, every device must be verified separately after each erase pulse. After a given device has been
successfully erased, the erase command should not be Issued to this device again. All devices that complete
erasure should be masked until the parallel erasure p/'0Cess Is finished (see Rgure 3).
"::Dm
-<~
Examples of how to mask a device during parallel erase include driving the Epin high, writing the read command
(OOOOh) to the device when the others receive a set-up-erase or erase command, or disconnecting it from all
electrical signals with relays or other types of switches.
~1ExAs ..
7·54
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
·
TMS28F210
1048576-8IT FLASH MEMORY
SMJS210B - DECEMBER 1992 - REVISED JUNE 1995
Bua
VCC. BV :t10%. VPP .12V:tS%
-T
Operation
Commmd
Commen18
Initialize
Add,...
Walt for VPP to ramp to
VPPH (He Note A)
StIIndtIy
Setup
Initialize pulaa count
WrIte
Sat..up-
oata.OO4Oh
Program
WrIte
Writa Data
Walt. 10 118
Standby
WrIte
valid add,..., data
Programvarlfy
Data. OOCOh; ende
program operation
Standby
Walt. 8 118
Read
R. .d word to verify
programming: compera
output to expected output
Interactive
Mode
~
~
a:
a.
b
::l
C
oa:
a.
Power
Down
1
Write
Read
Standby
Data. OOOOh; ranta
reglater for raad operations
Walt for VPP to ramp to
VPPL (a.. Note B)
NOTES: A. Refer to the recommended operating conditions for the value of VPPH.
B. Refer to the recommended operating conditions for the value of VPPL.
Figure 1. Programming Flowchart: Fastwrlte Algorithm
-!111ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lECAS 77251-1443
7-55
TMS28F210
1048576-811 FLASH MEMORY
SMJS210B- DECEMBER 1992 - REVISED JUNE 1995
Sue
Operation
Comm.nd'
Commenle
EnUra.m.mory muet _ 0000h
befo........u...
U.. F..twrlle
programmlng.lgorlthm
InW.llze.dd.......
Willi for Vpp to ramp to
VPPH (... Note A)
Standby
Setup
InIU.11a puIH count
W'r1te
Set-Up-
Dete_OO2Oh
E.....
'1J
Write
:u
oc
EraH
St.ndby
InteracUv.
Mode
c:
Q
W'r1te
om_OO2Oh
W.It-10me
E.....
verify
Addr - Word to verify;
d.1e _ 00A0h; .ndelh.......
op.ratlon
'1J
St.ndby
W.lt-8J&8
~
RNd
R••d word to verify .....u...;
com,.... output to FFFFh
:u
m
:e
W'r1te
Power
Down
RNd
Standby
l
NOTES: A. Refer to the recommended operating conditions for the value of VPPH.
B. Refer to the recommended operating conditions for the value of VPPL.
Figure 2. Flash-Erase Flowchart: Fasterase Algorithm
7·56
:il1ExAs
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 772151-1443
=
D.1e OOOOh; raHte ragl8ter
for ....d operaUone
W.1t for Vpp to ramp to
VPPL (... Note B)
TMS28F210
1048576·8IT FLASH MEMORY
SMJS21 os - DECEMBER 1892 - REVISED JUNE 18811
GIveE....e
Command To
All Unm..kecI
Devl_
No
Give Read
Command To
All Devlc..
GlveR..d
Command To
AlIDIVICH
t n =number of devices being erased
Figure 3. Parallel-Erase Flow Diagram
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7-57
TMS28F210
104857&-BIT FLASH MEMORY
SMJS210B - DECEMBER 1992 - REVISED JUNE 1995
absolute maximum ratings over operating free-alr temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) •......•..•. . . . . . • • . . • . • . • . . . . . . . . . . . . . . . • • • .• -0.6 V to 7 V
Programming supply voltage range, Vpp ............................................. -0.6 V to 14 V
Input voltage range (see Note 2): All inputs exceptA9 .....•••....•.•...•........ -0.6 V to Vee + 1 V
A9 •.•..•..• ;..................................... -0.6 V to 13.5 V
Output voltage range (see Note 3) •......•......•........•........•......•.... -"0.6 V to Vee + 1 V
Operating free-air temperature range during read/erase/program, TA
NL, FNL ..........•.....••....•.•...........•.••..•..• ooe to 70°C
NE, FNE .•...•..•..........•.....•..••.....•...... - 40°C to 85°C
Na, FNa ..•..••......•...•..•...•...•.•.......•• - 40° e to 125°C
Storage temperature range, Tstg ........•................•...•...•...•.•.......•.. -65°C to 150°C
t Stresses beyond those IIstsd under "absolute maximum ratings" may cause permanent damage to the device. These are strass ratings only. and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" Is not
Implied. Exposure to absolute-maximum·rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to VSS.
2. The voltage on any input can undershoot to -2 V for periods less than 20 ns.
3. The voltage on any output can overshoot to 7 V for periods less than 20 ns.
recommended operating conditions
Vee
Supply voltage
During wrlta/read/flash erase
During read only (VppL)
Vpp
Programming supply voltage
VID
Voltage level on AS for algorithm-selaction mode
VIH
Hlgh·1eve1 de Input voltage
VIL
Low·level de Input voltage
TA
Operating free-alr tempersture
TYP
MAX
4.5
5
5.5
V
V
12
Vee +2
12.6
11.5
13
V
2
Vee +0.5
0
During wrIta/readlflash erase (VPPH)
TTL
CMOS
11.4
UNIT
TTL
Vee- 0•5
-0.5
vee+ 0•6
0.8
CMOS
GND-0.2
GND+0.2
NL, FNL suffix
NE, FNE suffix
NQ, FNQ suffix
~1ExAs
7-68
MIN
INSTRUMENTS
POST OFFICE BOX 1443 • -HOUSTON. TEXAS 77251-1443
0
-40
-40
V
V
V
70
86
125
"C
TMS28F210
1048576-8IT FLASH MEMORY
SMJS210B - DECEMBER 1882- REVISED JUNE 18811
.Iectrlcal charact.rlstlcs ov.r recomm.nd.d rang.s of supply voltag. and operating fr....lr
t.mperature
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
TTL
CMOS
TTL
CMOS
All except AS
AS
TEST cONDmONS
IOH--2.5mA
10H .. -100 !.&A
MIN
2.4
MAX
V
VCC-0.4
0.45
IOL-5.8rnA
IOL - 100 !.&A
VI-OVto5.5V
VI"OVto13V
UNIT
V
0.1
.1
.200
.10
!.&A
TBD
rnA
200
.10
!.&A
!.&A
50
50
rnA
rnA
5.0
rnA
1
100
rnA
50
rnA
10
Output current Oeakage)
VO-OVtoVcc
110
AS algorlthm-selectlon-mode current
AS=VIOmax
IpP1
VPP supply current (read/standby)
IpP2
IpP3
VPP supply current (during progrem pulse) (see Note 4)
VPP supply current (during flash erase) (see Note 4)
VPP·VPPL
VPP-VpPH
VPP-VpPH
IpP4
VPP supply current (during program / erase verify)
(see Note 4)
VPP-VPPH
Ices
Vcc supply current (standby)
ICC1
Vcc supply current (active read)
ICC2
Vcc average supply current (active write) (see Note 4)
VCC- 5•5V•
e.VIIo
Programming In progress
10
mA
ICC3
Vcc average supply current (flash erase) (see Note 4)
E-VIL.
VCC· 5•5V•
Erasure In progress
15
rnA
1CC4
Vcc averege supply current (program / erase verify)
(see Note 4)
E.VIIo
VCC· 5•5V•
VPP-VpPH.
Progrem / arese verify In progress
15 . rnA
VPP-VPPH.
TTL-Input level
CMOS-Input level
Vcc= 5.5V.
VCC_ 5•5V•
VCC- 5•5V•
f=8MHz.
Read mode
E-VIH
e-VCC
E .Vllo
Outputs open
!.&A
!.&A
capacltanc. over recommended ranges of supply voltage and operating free-air temperature,
f= 1 MHzt
PARAMETER
VI-OV.
h1MHz
MAX
8
VO-OV.
f-1 MHz
12
TEST CONDITIONS
Input capacitance
Output capacitance
Co
t Capacitance measurements are made on sample basis only.
MIN
UNIT
pF
pF
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
a.
ti
~
Q
NOTE 4: Not 100% tested; charecterizatlon data available
CI
~
~
a:
7-59
oa:
a.
TMS28F210
1048576-BITFLASH MEMORY
SMJS2108- DECEMBER 1892- REVISED JUNE 1885
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature
.
TEST
CONDITIONS
ta(A)
100
120
150
170
118
100
120
150
170
118
ta(G)
IGLQV
45
50
55
80
118
1c{R)
Cycle time,
read
tAVAV
100
120
150
170
118
tELQX
0
0
0
0
118
IGLQX
0
0
0
0
na
tEHCZ .
0
55
0
55
0
55
0
55
118
IGHQZ
0
30
0
30
0
35
0
35
118
. tAXQX
0
0
0
0
na
twHGL
6
6
6
6
lIS
o"
C
~
th(D)
-~
tAVQV
UNIT
teLQV
:xl
~
'28F21CJ.17
IIIN MAX
Access time
fromG
Iclls(E)
"
'28F21o-1a
IIIN MAX
fromE
Icl{G)
:xl
Access time
'28F21o-12
MIN MAX
ta(E)
1cl(E)
c:
Access time
from address
'28F21CJ.10
IIIN MAX
ALTERNATE
SYIIBOL
lclis{G)
Delay time, chip
enable low to
low-Z output
CL= l00pF,
1 Series 74
Oelaytlme,G
TTL load,
low to Iow-Z
Inputlr " 20 ne,
output
Input tf " 20. ne
Chip disable to
HI-Zoutput
Hold time,
output enable to
HI-Zoutput
Hold time, data
valid from
address, E, or
lit
Write recovery
time before
read
t Whichever occurs first
1rec(W)
~1ExAs
7-80
INSTRUMENTS
PO$T OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS28F210
1048576·81T FLASH MEMORY
SMJS210B - DECEMBER 1992 - REVISED JUNE 1996
timing requlrements-wrlte/erase/program operations
'28F210·10
ALTERNATE
SYMBOL
MIN
NOM
'28F210·12
MAX
MIN
NOM
MAX
UNIT
tc(W)
Cycle time, write using W
tAVAV
100
120
na
tc(W)PR
Cycle time, programming operation
twHwHI
10
10
l1li
twHwH2
9.5
twt..Ax
55
80
0
10
tclWlER
Cycle time, erase operation
IhCAl
Hold time, address
Ihca
thlWHDl
Hold time, E
twHEH
0
Hold time, date valid after W high
10
!suCAl
Satup time, address
twHDX
tAVWL
0
0
!suCD)
Setup time, data
toVWH
50
50
!sulE)
Setup time, E before W
!sulEHVPPl Setup time, E high to Vpp ramp
!su(VPPEL) Setup time, Vpp to E low
10
9.5
teLWL
20
20
teHVP
100
100
tvPEL
1
1
twHGL
8
8
treclWl
Recovery time, W before read
tracCR)
Recovery time, read before W
IGHWL
0
0
tw(W)
Pulse duration, W (see Note 5)
twLWH
80
IwIWHl
tr(VpP)
Pulse duration, W high
twHWL
Rise time, Vpp
tvPPR
80
20
1
tf(vpP)
Fall time, Vpp
tvPPF
1
1
MIN
na
na
na
na
na
na
na
1411
l1li
1411
na
na
20
1
'28F210·15
ALTERNATE
SYMBOL
rna
10
NOM
l1li
1411
'28F210·17
MAX
MIN
NOM
MAX
~
5>
w
a:
UNIT
a.
tclWl
Cycle time, write using W
tAVAV
150
170
na
Cycle time, programming operation
twHwHl
10
10
t)
tc(w)PR
1411
tc(W)ER
thlAl
Cycle time, erase operation
twHWH2
9.5
:l
Hold time, address
twt..Ax
10
9.5
70
10
ms
thCE)
Holdtime,E
twHEH
80
0
thIWHD)
Hold time, date valid after W high
twHDX
10
10
na
na
na
!suCA)
Setup time, address
tAVWL
0
0
ns
!sulDl
Satup time, data
50
na
Setup time, E before W
toVWH
tELWL
50
!sulEl
!suIEHVPP)
20
20
n8
Setup time, E high to Vpp ramp
tEHVP
100
100
na
!su(VPPEL)
Setup time, Vpp to E low
tvPEL
1
1
treclWl
Recovery time, W before read
twHGL
8
8
tracCR)
Recovery time, read before W
IGHWL
0
1w(W)
Pulse duration, W (see Note 5)
twLWH
IwIWHl
Ir(VPP)
Pulse duration, W high
twHWL
20
Rise time, Vpp
tvPPR
80
20
1
0
80
1411
1411
1411
tvPPF
1
1
Fall time, Vpp
tf(vPPI
NOTE 5: Rise/fall time", 10 n8.
0
1
na
na
1411
1411
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77251-1443
7-81
C
oa:
a.
TMS28F210
1048576-8IT FLASH MEMORY
SMJS210B- DECEMBER 1992 - REVISED JUNE 1995
•
timing requirements-alternative E-controlled writes
ALTERNATE
SYMBOL
Cycle time, write using E
tc(W)
MIN
'28F210·12
MIN
MAX
'28F210·15
MAX
MIN
MAX
'28F210·17
MIN
MAX
UNrr
ns·
tAVAV
100
120
150
170
10
10
10
i.I8
80
90
ns
10
o.
10
0
nl
nl
tc(E)PR
operation
teHEH
10
1tilEA)
thlED)
th(W)
Hold time, addi'ess
tELAX
75
Hold time, date
Hold time, ViI
teHDX
10
0
taulA)
Setup time, address
teHWH
tAVEL
80
10
0
taulD)
Setup time, date
toVEH
0
50
0
50
0
50
0
50
nl
nl
tau(W)
twLEL
tyPEL
0
1
0
1
0
1
0
1
nl
trec(E)R
Setup time, ViI before E
Setup time, Vpp to E low
R8CO'I8I)' time, write using E
before read
tEHGL
8
8
8
8
i.I8
trec(E)W
Recovery time, raad before
write using E
tGHEL
0
0
0
0
i.I8
Pulse duration, write using E
teLEH
70
70
70
80
nl
Pulse duration, write, E high
teHEL
20
20
20
20
ns
taulVPPELl
"o::IJ
Cycle time, programming
'28F210·10
twlEl
twlEHl
i.I8
C
c:
o
PARAMETER MEASUREMENT INFORMATION
-I
-I
2.08 V
"~
::IJ
-
Output
Under Telt
~
I
RL • aooQ
CL-100pF
(IHNoteA)
LOAD CIRCUIT
NOTE A: CL includes probe and fixtura capacitance.
=X
2.4V
0.45 V
2V
0.8 V
o.~~ X'-__-
VOLTAGE WAVEFORMS
FIgure 4. Load Circuit and Voltage Waveforms
AC testing inputs are driven at 2.4 V for logic high and 0.45 V for logic low. llming measurements are made at
2 V for logic high and 0.8 V for logic low on both inputs and outputs. Each device should have a 0.1·",F ceramic
capacitor connected between Vee and VSS as close as possible to the device pins.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 11'!XAS 77261-1443
TMS28F210
1048576·8IT FLASH MEMORY
SMJS210S - DECEMBER 19112 - REVISED JUNE 1885
PARAMETER MEASUREMENT INFORMATION
tc(A) -----~.~I
I..
I
1
AO-A1S---.....,.X
X,;-------
Addre.. Yalid
""
E------'~
I
I
I
~I
ta(A)
I
~'i,------- - - - + 1----....of'
"""I
;+-- talE) ~
1 14--1cI1a(E) ~
U
I
G-------tl-..~
.
1cI(E)
DOG-D015
HI-Z
I"
~I
I
I
I I
I
1 14--1c118(G)--.I
I..-
I
@<<«{
I
'11' iI
14-- tnc(W)....J.--..I I
1
1
I
I j4-tan(G)~
j'
I
1
1
W --.J
I
I
I
I ~ I+- IcI(G) I
OuputYalid
tt.(D)
~
I
I
}»»»}- HI.z-
Figure 5. Read-Cycle nmlng
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
7-83
TMS28F210
1048576-8IT FLASH MEMORY
SMJS210B:" DECEMBER 1892 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Power Up
and
Program-
S.t-UpProgram
Program
VeJitlcation
AO-A15
Io
c
c:
o-I
DQODQ1&
"'tJ
::xJ
~
m
=e
Vee ."
w,
-
II
II
II
II
"
"-
OV
Vpp
VPPH
VPPL
·f
i'r-
It(VPP) --.,
Figure 6. Write-Cycle TIming
~TEXAS
7-64
INSTRUMENTS
POST OFFICE ~x 1443 • HOUSTON. lEXAS 77251.,..1443
I+-
TMS28F210
1048576·8IT FLASH MEMORY
SMJS210B- DECEMBER 1992 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
Power Up
Prollram-
Program
Verification
and
Standby!
AO-A15
VI
I
I
I lsu(W)~~
I
"'(W) -.j l+I
XI
I/
i
E
y
I
I
I
"'(D)
tw(E)
I
DQO-
DQ15
I
;I){!r---"'-
~ 14-
~
lsu(D)
trac(E)W
t+I l+-
r-I
I.-
lsu(D)
---V-H1.z
I
I
I
Vee
5V
OV
Vpp
12V
VPPL
--Y
I
I
\..
I
I---*- lsu(VPPEL}
IJ;"
II
II
II ~I I1+
-tI
J4-
'LI
tf(VPP)
Ir(VPP}
lsu(EHVPP}
-+I
I
I+-
Rgure 7. Write-Cycle (Alternative E-Controlled Writes) Timing
~TEXAS
.
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
7-65
TMS28F210
1048576-81T FLASH MEMORY
SMJS210B- DECEMBER 1892 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
AO-A15
G
W
."
:D
0
C
C
DQODQ15
n
-t
."
:::a
m
<
m
-:e
Vee
Vpp
IV
OV
l2V
VPPL
--Y I
II ....
- I I+-
'I;
teu(VPPEL)
Iii
I I I
11
~
.
fl,
~
. I I
tf(VPP) ~
j4- tr(VPP)
~ teu(EHVPp)
Figure 8. Flash·Erase-Cycle TIming
~1ExAs
7-66
\...
',\
INSTRUMENTS
POST OFFICE BOX 1443 • HOUS'ION, TEXAS 77251-1443
j4-
TMS28F020
2097152·81T FLASH MEMORY
• Organization ••• 256K )( 8-Blta
.• Pin Compatible With ExIsting 2-Megablt
EPROM.
• Vee Tolerance :t:10%
• Allinputa/Outputa TTL Compatible
• Maximum Acce88/Mlnlmum Cycle Time
'28F02O-10
100 ns
'28F020-12
120 n.
'28F020-15
150 n.
'28F02D-17
170 ns
• Industry-Standard Programming Algorithm
• PEP4 Version Available With 168-Hour
Burn-In and Choice of Operating
Temperature Ranges
• 100000 and 10000 Program/Erase-Cycle
Version. Available
• Latchup Immunity of 250 mA on All Input
and Output Line.
• Low Power Dissipation (Vee = 5.5 V)
- Active Write ••• 55 mW
- Active Read ••• 165 mW
- Electrical Erase ••• 82.S mW
- Standby ••• 0.55 mW
(CMOS-Input Levels)
• Automotive Temperature Range
- 40°C to 125°C
FMPACKAGE
(TOP VIEW)
o
A14
A13
M
A9
A11
G
A1
11
A10
E
AO
000
DQ7
14 15 16 17 18 19 20
PIN NOMENCLATURE
AIJ-A17
COO-CQ7
~
G
Vee
VPP
Vss
Vii
AddrasslnpU18
InpUIs (programmlng)/OutpU18
Chip Enable
Output Enable
SoV Power Supply
12-V Power Supply
Ground
Write Enable
description
The TMS28F020 flash memory is a 2097152-bit, programmable read-only memory that can be electrically
bulk-erased and reprogrammed. It is available in 100 000 and 10000 program/erase-endurance-cycle versions.
The TMS28F020 is offered in a 32-lead plastic leaded chip-carrier package using 1,25-mm (50-mil) lead spacing
(FM suffix) and a 32-lead thin small-outline package (DO SuffIX).
-!I
TEXAS
INSTRUMENTS
POST OFFICE BOX 144ll- HOUS'TON. TEXAS 77251-1443
CopyrIght 0 1995. Texas Instruments Incorporated
7-4l7
TMS28F020
2097152-BIT FLASH MEMORY
SMJS020B- OCTOBER 1894 - REVISED JUNE 1996
DDPACKAGE
(TOP VIEW)
A11
10
AS
AS
A13
A14
A17
W
Vee
Vpp
A16
A15
A12
A7
A6
AS
A4
4
5
8
7
32
31
(I
30
29
28
E
'l:1
28
25
24
23
8
9
10
22
DQ7
Dae
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
Doo
11
12
21
13
14
20
19
AO
15
18
18
17
A2
A3
device symbol nomen"lature
TMS28F020
·12
C5
FM
L
L
PEP4Bum"n
4 .. 188 Hour Bum..n
(blank If no bum..n)
'--------Temperature Range Deelgnator
L.
O°C to 70°C
E
• - 4O"C to UOC
Q
.. -4O"C to 125"C
L....-_ _ _ _ _ _ _ _
L....-_ _ _ _ _ _ _ _ _
Package De.lgnator
FM.. Plaatlc Leaded Chlp-Carrler
DD. Thin Small-Outllne Package
Program/Era.. Endurance
C& .. 100000 Cycl..
C4 .. 10000CyclH
L . . . - - - - - - - - - - - - s p e e d D..lgnator
·10 • 100 na
·12 • 120 na
·15 • 150 na
·17 • 170na .
~1ExAs
7-88
A10
INSTRUMENTS
POeT OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
A1
TMS28F02O
2097152·BIT FLASH MEMORY
SMJS020B - OCTOBER 1994 - REVISED JUNE 1995
logic symbol t
AO
A1
A2
A3
A4
AS
AS
A7
Ita
AI
A10
A11
A12
A13
A14
A15
A18
A17
o ...
12
11
10
8
8
7
8
5
27
> A282~43
28
23
25
4
28
28
3
2
30
17 '"
....
22
24
31
~
l..b
DQO
DQ1
DQ2
DQ3
D04
DQ5
DQ8
DQ7
01
[PWRDWN)
G2
1.2 EN (READ)
1C3(WR1TE)
r
13
4
14
15
17
18
18
20
21
FLASH
MEMORY
282144".
A, 3D
V4
A,Z4- -
.....
...
_r
/
tThIs symbol Is In acc:ordance with ANSIJIEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the FM package.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
NI9
TMS28FOZO
2097152·81T FLASH MEMORY
SMJS02OB- OCTOBER 1994 - REVISED JUNE 1995
functional block diagram
DQO-DQ7
8
vpp------~--~~----~~ E.......VOltaa. Switch
'--.,..---~
........
w----....
State Control
Program/E.....
Stop 11m.,
Command Reglate, t---~
STB
E --.---------t------------------+--f....
Chlp-Enabl. and
Output-Enabl.
G
logic
STS
A
d
d
AD-A17
18
,
••
•
Column Decod.,
Column aaona
Row Decoder
2087152-8lt
Array Matrix
L
a
t
c
h
~1ExAs
7·70
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXA!l77251-1443
TMS28F020
2097152·81T FLASH MEMORY
SMJS020B - OCTOBER 1994- REVISED JUNE 1995
operatIon
The operation of the TMS28F020 Is fully summarized In Table 1 with required signal levels shown for each
operation. The sections following the table describe operations in detail.
Table 1. Operation Modes
FUNCTlONt
MODE
Read
Read
Output Disable
VpPL
VpPL
Standby and WrIte Inhibit
VPPL
A1gorlthm-8electlon Mode
Read!
Write
G
(24)
AD
(12)
AS
(28)
W
(31)
DOO-DQ7
(13-15,17-21)
VIL
VIL
X
X
X
Data Out
VIH
X
X
X
VIH
VIL
VIH
VIH
HI-Z
X
HI-Z
Mfr-Equlvalent Code 89h
VIO
VIH
X
X
X
X
VIH
Data Out
VIH
HI-Z
E
Vpp*
(1)
(22)
X
VPPL
VIL
VIL
Read
VpPH
VIL
VIL
Output Disable
VpPH
VPPH!
VIL
VIH
VIH
X
Standby and Write Inhibit
Write
VPPH
VIL
VIL
VIH
X
X
X
X
VIH
Device-Equivalent Code BOh
X
Hi-Z
VIL
Data In
t X can be VIL or VIH.
* VPPL '" Vee + 2 V; VpPH is the programming voltage specified forthe device. For more details, refer to the recommended operating conditions.
read/output disable
When the outputs of two or more TMS28F020s are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from the competing outputs of other devices. To
read the output of the TMS28F020, a low-level signal is applied to Eand G. All other devices in the circuit should
have their outputs disabled by applying a high-level signal to one of thEtse terminals.
standby and write Inhibit
Active IcC current can be reduced from 30 mA to 1 mA by applying a high TTL level on E or to 100 !AA with a
high CMOS level on E. In this mode, all outputs are In the high-impedance state. The TMS28F020 draws active
current when it is deselected during programming, erasure, or program/erase verification. It continues to draw
active current until the operation Is terminated.
algorithm-selection mode
The algorithm-selection mode provides access to a binary code Identifying the correct programming and erase
algorithms. This mode is activated when A9 is forced to VID. Two identifier bytes are accessed by toggling AO.
All other addresses must be held low. AO low selects the manufacturer-equivalent code 89h, and AO high selects
the device-equivalent code BOh, as shown in the algorithm-selection mode table below:
IDENTIFIER§
Manufacturer-Equivalent Code
DevIce-Equivalent COde
§E
TERMINALS
AD
DQ7
DQ6
DQ5
DQ4
DQ3
002
DQ1
000
VIL
1
0
0
0
0
0
1
HEX
89
VIH
1
0
1
1
1
1
1
0
1
BO
=G = Vllo AI-AS. VIL, AS. VIO, AtO-AI7 =Vllo Vpp. VPPL.
programming and erasure
In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to
a logic O. Afterward, the entire chip is erased. At this point, the bits, now logic 1s, can be programmed accordingly
(refer to the Fastwrite and Fasterase algorithms for further detail).
:lllExAs
'
INsTRUMENTS
POST OFFICE SOX 1443 • HOUSTON, ll:XAS 77251-1443
7-71
TMS28F020.
2097152·BIT FLASH MEMORY
SMJS020B- OCTOBER 1994- REVISED JUNE 1995
command register
The CQmmand register controls the program and erase functions of the TMS28F020. The algorlthm-selectlon
mode can be activated using the command register in addition to the method described in the
algorithm-selection mode section. When Vpp Is high, the contents of the command register and the function
being performed can be changed. The command register is written to when E is low and WIs pulsed low. The
address is latched on the leading edge of the pulse and the data Is latched on the trailing edge; AccIdental
programming or erasure is minimized because two commands must be executed to invoke either operation.
The command register is Inhibited when Vee Is below the erase/write lockout voltage, VLKO.
power supply considerations
Each device should have a O.1-"F ceramic capacitor connected between Vee and Vss to suppress circuit noise.
Changes in current drain on Vpp require it to have a bypass capacitor to Vss as well. Printed-circuit traces for
both power supplies should be appropriate to handle the current demand.
Table 2. Command Definitions
COMMAND
REQUIRED
BUS
CYCLES
OPERAnoNt
ADDRESS
DATA
OPERAnoNt
ADDRESS
1
Write
X
OOh
Read
RA
RD
00000
89h
00001
BDh
X
X
EVD
Read
SECOND BUS CYCLE
FIRST BUS CYCLE
A1gorHhm-Selectlon Mode
3
WrIte
X
SOh
Read
Set-Up-Erase/Erase
2
2
Write
X
Write
Write
EA
2
2
2
Write
X
20h
AOh
40h
WrIte
X
COh
Write
Read
Write
X
FFh
Write
Erase Verify
Set-Up-ProgremJProgram
Program Verify
Reset
t Modes of operation are defined In Table 1.
Legend:
EA
RA
PA
RD
Address of memory location to be read during erase verify
Address of memory location to be read
Address of memory location to be programmed. Address is latched on the felling edge of VIi.
Dele read from location RA.during the reed operation
EVD Dete read from location EA during erase verify
PO Dele to be programmed at location PA. Dele Is latched on the rising edge of W.
PVD Dele read from location PA during program verify
:IlalExAs .
INSTRUMENTS
7-72
POST OFFICE 8OX1443 • HOUSTON, 1EXAS 77251-1443
Read
PA
X
X
DATA
20h
PO
PVD
FFh
TMS28F020
2097152·8IT FLASH MEMORY
SMJS020B - OCTOBER 1994- REVISED JUNE 1996
command definitions
read command
Memory contents can be accessed while Vpp Is high or low. When Vpp is high, writing OOh into the command
register Invokes the read operation. When the device is powered up, the default contents of the command
register are OOh and the read operation is enabled. The read operation remains enabled until a different valid
command Is written to the command register.
algorithm-selection-mod. command
The algorithm-selection mode is activated by writing 90h Into the command register. The
manufacturer-equivalent code (89h) Is Identified by the value read from address location OOOOOh, and the
device-equivalent code (BOh) is identified by the value read from address location 00001 h.
aet-up..ras./eraa. commanda
The erase algorithm begins with E =VIL, W =VIL, G=VIH, Vpp =VpPH, and Vee =5 V. To enter the erase mode,
write the set-up-erase command, 2Oh, into the command register. Writing a second erase command, 20h, into
the command register invokes the erase operation. The erase operation begins on the rising edge ofW and ends
on the rising edge of the next W. The erase operation requires 10 ms to complete before the erase-verify
command, AOh, can be loaded.
Maximum erase timing is controlled by the internal stop timer. When the stop timer terminates the erase
operation, the device enters an inactive state and remains inactive until a command is received.
eraae-verlfy command
All bytes must be verified following an erase operation. After the erase operation is complete, an erased byte
can be verified by writing the erase-verify command, AOh, into the command register. This command causes
the device to exit the erase mode on the rising edge of W. The address of the byte to be verified is latched on
the falling edge of W. The erase-verify operation remains enabled until a command is wntten to the command
register.
To determine whether or not all the bytes have been erased, the TMS28F020 applies a margin voltage to each
byte. IfFFh is read from the byte, all bits in the designated byte have been erased. The erase-verify operation
continues until all of the bytes have been verified. If FFh is not read from a byte, an additional erase operation
must be executed. Figure 1 shows the combination of commands and bus operations for electrically erasing
the TMS28F020.
set-up-program/program commands
The programming algorithm begins with E =VIL, W =VIL, G =VIH, Vpp =VpPH, and Vee =5 V. To enter the
programming mode, write the set-up-program command, 4Oh, into the command register. The programmi!!9
operation is invoked by the next write-enable pulse. Addresses are latched internally on the falling edge of W,
an~data is latched internally on the rising edQ! of W. The programming operation begins on the rising edge
of Wand ends on the rising edge of the next W pulse. The program operation requires 10 IJS for completion
before the program-verify command, COh, can be loaded.
Maximum program timing is controlled by the internal stop timer. When the stop timer terminates the program
operation, the device enters an inactive state and remains inactive until a command is received.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7·73
TMS28F020
2097152·81T FLASH MEMORY
SMJS020B.,. OCTOBER 1994 - REVISED JUNE 1995
program-verify command
The TMS28F020 can be programmed sequentially or randomly because it is programmed one byte at a time.
Each byte must be verified after it Is programmed. The program-verify operation prepares the device to verify
the most recently programmed byte. To Invoke the program-verify operation, COh must be written into the
command register. The program-verify operation ends on the rising edge of W.
While verifying a byte, the TMS28F020 applies an internal margin voltage to the designated byte. If the true data
and programmed data match, programming continues to the next deSignated byte location; otherwise, the byte
must be reprogrammed. Figure 2 shows how commands and bus operations are combine(j for byte
programming.
reBet command
To reset the TMS28F020 after set-up-erase command or set-up-program command operations without
changing the contents in memory, write FFh into the command register two consecutive times. After executing
the reset command, the device will default to the read mode.
Fastwrlte algorithm
The TMS28F020 is programmed using the Texas Instruments Fastwrite algorithm shown in Figure 2.· This
.
algorithm programs in a nominal time of four seconds.
Fasterase algorithm
The TMS28F020 is erased using the Texas Instruments Fasterase algOrithm shown in Figure 1. The memory
array needs to be completely programmed (using the Fastwrite algorithm) before erasure begins. Erasure
typically occurs in two seconds.
parallel erasure
To reduce total erase time, several devices can be erased in parallel. Since each Flash memory can erase at
a different rate, every device must be verified separately after each erase pulse. After a given device has been
successfully erased, the erase command should not be Issued to this device again for this erase cycle. All
devices that complete erasure should be masked until the parallel erasure process is finished (see Figure 3).
Examples of how to mask a device during parallel erase Include drMng E high, writing the read command (OOh)
to the device when the others receive a set-up-eraljle or erase command, or disconnecting it from all electrical
signals with relays or other types of switches.
~
~TEXAS
7-74
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
TMS28F020
2097152·81T FLASH MEMORY
SMJS020B - OCTOBER 1994 - REVISED JUNE 1895
Bua
Operation
Command
Commenta
Entlra memory muet .. OOh
befora eraaure
U.. Faatwrlte
programming algorithm
Initialize add_
Walt for Vpp to ramp to
VPPH (a.. Note A)
Standby
Initialize pul.. count
InteractlVII
Mode
WrIte
Set-UpEra..
Dateoo20h
Write
Eraae
Date .. 20h
Walt .. 10ma
Standby
Write
Power
Era..
.Verffy
Addr • Byte to VIIlfty;
Data .. AOh; enda the eraae
operation
Standby
Walt .. 6 jdI
Read
R..d byte to velfty eraaure;
compare output to FFh
Write
Read
Down
Standby
Data .. OOh; raaete reglater
for read operatlona
Walt for Vpp to ramp to
VPPL (aee Note B)
NOTES: A. Refer to the recommended operating conditions for the value of VPPH.
B. Refer to the recommended operating conditions for the value of VpPL.
Figure 1. Flash·Erase Flowchart: Fasterase Algorithm
~TEXAS
INSTRUMENTS
POST OFFICE BOX 14013 • HOUSTON. TEXAS 77261-14013
7-75
TMS28F020
2097152·8IT FLASH MEMORY
SMJS020B - OCTOBER 11194- REVISED JUNE 1895
Bua
Operation
-T
Command
Commenta
Initialize
Add,...
walt for Vpp to ramp to
Stllndby
VpPH (see Note A)
Setup
Initialize pulse count
Write
Set·UpProgram
Write
Data-40h
Write
Write Data
valid addra88/data
Walt. 101&8
StIIndbY
Write
Interactive
Mode
Power
Down
Walt. S 1&8
Resd
Read byte to verify
Programmlngi compare
output to expectad output
Read
Stllndby
NOTES: A. Refer to the recommended operating conditions for the value of VpPH.
B. Refer to the recommended operating conditions for the value of VpPL.
Figure 2. Programming Flowchart: Fastwrlte Algorithm
~ThxAs
7·78
Data - COhi ends
Program operation
StIIndby
Write
1
Program
Verify
.
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
Data • 00h; meta register
for read operations
Walt for Vpp to ramp to
VpPL (sse Note B)
TMS28F020
2097152·8IT FLASH MEMORY
SMJS020B - OCTOBER 1994- REVISED JUNE 1995
Give Era..
Command to
All Unmeaked
Devlcee
No
Give Read
Command to
A110.vlc..
GIveR..d
Command to
All Devlcee
t n =number of devices being erased.
FIgure 3. Parallel-Erase Flow DIagram
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7-n
TMS28F020
2097152·81T FLASH MEMORY
SMJS020B- OCTOBER1984- REVISED JUNE 1996
absolute maximum ratings over operating free·alr temperature range (Unless otherwise notecl)t
Supply voltage range, Vee (see Note 1) .............................................. -0.6 V to 7 V
Supply vO.ltage range, Vpp .•..•.......•.••.............•....•...•.................. -0.6 V to 14 V
Input voltage range (see Note 2): All inputs except A9 ...............•........... -0.6 V to Vee + 1 V
A9 ...•...•....•.............•••.•.•••.•.•.•.••..• -0.6 V to 13.5 V
Output voltage range (see Note 3) ............................................ -0.6 V to Vee + 1 V
Operating free-air temperature range during read/erase/program, TA:
L ................................................................... ooe to 700 e .
E ... , .•.••••.•......•.••...................•........'............. - 40 0 e to 85°e
Q ••.••••••••••••••••••••.•••••••••••••••••••••.••••••...••.•.••• - 40 0 e to 125°e
Storage temperature range, Tatg .................................................. -65°e to 1500 e
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the davlce. These are stress ratings only. and
functional operation of the device at these or any other oonditlons beyond those Indicated under "reoommended operating oonditlons' Is not
implied. Exposure to absolute-maxlmum-rated oonditlons for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to VSS.
2. The voltage on any input can undershoot to -2 V for periods less than 20 ns.
3. The voltage on any output can overshoot to 7 V for periods less than 20 ns;
recommended operating conditions
Vee
Vpp
Supply voltage
Supply voltage
During wrIte/read/1Iash erase
During read only (VPPL)
During wrlta/read/llash erase (VPPH)
TTL Inputs
VIH
High-level de Input voltage
VIL
Low·level de Input voltage
VID
Voltage level on AS for algorlthm-selectlon mode
CMOS Inputs
TTL Inputs
CMOS Inputs
~1ExAs
7·78
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
MIN
TVP
MAX
4.5
5
5.5
V
V
12
VCC+ 2
12.6
0
11.4
2
VCC-0.5
-0.5
GND-0.2
11.5
VCC + 0.5
VCC + 0.5
0.8
GND+0.2
13
UNIT
V
V
V
V
TMS28F020
2097152·8IT FLASH MEMORY
SMJS020B - OCTOBER 1994- REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
110
M algorithm-selection-mode current
II
Input current (Ieakagej
10
Output current Oeakage)
IpP1
VPP supply current (read/standby)
IpP2
TEST CONDITIONS
MIN
IOH=-2.5mA
2.4
10H = -100 joIA
VCC- 0.4
MAX
V
IOL=5.8mA
0.45
10L" 100 joIA
0.1
M"VIOmax
200
LAll except M
VI "OVto5.5V
:01
1M
VI"OVto13V
:0200
VO=OVtoVCC
Read mode
Vpp.VpPH,
UNrr
V
joIA
joIA
:010
joIA
200
joIA
VPP=VPPL
:010
joIA
VPP supply current (during program pulse) (see Note 4)
VpP-VpPH
30
mA
IPP3
VPP supply current (during flash erase) (see Note 4)
VPP"VPPH
30
mA
IpP4
VPP supply current (during program/erese verify)
(see Note 4)
VPP= VpPH
5
mA
ICCS
V CC supply current (standby)
ITTL-Input level
VCC=5.5V,
E=VIH
I CMOS-Input level
VCC=5.5V,
E=VCC
E=VIL,
10UT=OmA
1
mA
100
joIA'
30
mA
ICC1'
VCC supply current (active read)
VCC = 5.5 V,
f.6MHz,
ICC2
VCC averege supply current (active write) (see Note 4)
VCC·5.5V,
E"VIL,
Programming In prograss
10
mA
1CC3
Vcc average supply current (flash erase) (sea Note 4)
VCC = 5.5 V,
E=VII_,
Erasure In progress
15
mA
1CC4
Vcc average supply current (progrem/erese verify)
(see Note 4)
VCC- 5.5V,
E .Vllo
Vp'p=VpPH,
Program/erase verify In progress
15
rnA
VLKO
VCC erase/write lockout voltage
VPP= VPPH
2.5
V
NOTE 4: Not 100% tested; characterization data available.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHzt
PARAMETER
TEST CONDrrlONS
MIN
MAX
UNrr
CI
Input capacitance
VI=OV
6
pF
Co
Output cepacltance
VO·OV
12
pF
t capacitance measurements are made on sample basis only.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77261-1443
7-79
TMS28F020
2097152·8IT FLASH MEMORY
SMJS020B - OCTOBER 1994 - AEVISEDJUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature
PARAMETER
TEST
CONomONS
ALTERNATE
SYMBOL
'28F020·10
MIN
'28F02O·12
MAX
MIN
MAX
'28F02O·15
MIN
MAX
'28F020·17
MIN
MAX
UNrr
talA)
Access time from
address, AO-A17
tAVQV
100
120
150
170
n8
talE)
Access time from
chip enable, E
tELQV
100
120
150
170
n8
ten(G)
Access time from
output enable, G
tGLQV
45
50
55
50
ns
tc(R)
Cycle time, read
tAVAV
100
120
150
170
ns
ld(E)
Delay time, E
going low to
low-Impedance
output
teLQX
0
0
0
0
ns
ld(G)
Delay time, G
going low to
low-impedance
output
tGLax
0
0
0
0
n8
teHQZ
0
55
0
55
0
55
0
55
n8
30
0
30
0
35
0
35
ns
CL= 100pF,
1 Series 74
TTL load,
Input
20 n8,
Input tt " 20 n8
tr "
ldls(E)
Chip dlssble time
to high-Impedance
output
ldls(G)
Output dlssble
time to
high-Impedance
output
tGHQZ
0
th(D)
Hold time, data
valid from
address, E or Gt
lAxax
0
0
0
0
n8
trec(W)
Writs recovery
time before read
twHGL
8
8
8
8
I'll
t Whichever oocurs first
-!111ExAs
INSTRUMENTS
7-80
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS28F020
2097152·81T FLASH MEMORY
SMJS020B - OCTOBER 1994 - REVISED JUNE 1995
timing requlrements-wrlte/erase/program operations
'28F020·12
'28F020·10
ALTERNATE
SYMBOL
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
tc(W)
Cycle time, write using W
tAVAV
100
120
ns
tc(W)PR
Cycle time, programming operation
twHWHl
10
10
I'll
~ER
Cycle time, erase operation
twHWH2
9.5
1hIA}
Hold time, address
twLAx
55
80
thee)
Hold time, E
twHEH
0
0
ns
tl1M'!'iD)
Hold time, data valid after W high
twHOX
10
10
ns
taulA}
Setup time, address
tAVWl.
0
0
na
tsu(O)
Setup time, data
tOVWH
50
50
na
tau IE}
Setup time, E before W
tELWL
20
20
nl
tauNPPELl
Setup time, Vpp to E going low
tvPEL
1
1
I'll
trec(W)
Recovery time, W before read
twHGL
8
8
traclR}
Recovery time, read before W
tGHWL
0
0
I'll
I'll
tw(W)
Pulse duration, W (see Note 5)
twLWH
80
80
na
tw(WH)
Pulse duration, W high
twHWL
20
20
na
trNPP}
Rise time, Vpp
tvPPR
1
1
I'll
tf(VPP)
Fall time, Vpp
tvPPF
1
1
I'll
10
9.5
MIN
NOM
ma
ns
'28F020·17
'28F02O·15
ALTERNATE
SYMBOL
10
MAX
MIN
NOM
MAX
UNIT
tc(W)
Cycle time, write ullng W
tAVAV
150
170
ns
tclWlPR
Cycle time, programming operation
twHWHl
10
10
I'll
twHWH2
9.5
twLAx
80
70
ns
0
nl
tc(w)ER
Cycle time, erase operation
1h(A)
Hold time, address
1h~
Hold time, E
twHEH
0
thIWHD}
Hold time, data valid after W high
twHox
10
10
nl
tau(A}
Setup time, address
tAVWl.
0
0
nl
tau(D)
Setup time, data
toVWH
50
50
ns
tau(E)
Setup time, E before W
tELWL
20
20
na
tauNPPELl
Setup time, Vpp to E gOing low
tvPEL
1
1
trac(W)
Racovery time, W before read
twHGL
6
6
I'll
I'll
trac(R)
Recovery time, read before W
tGHWL
0
0
I'll
twlWl
Pulse duration, W (see Note 5)
twLWH
80
80
na
twIWH)
Pulse duration, W high
twHWL
20
20
ns
tr(VPP)
Rise time, Vpp
tvPPR
1
1
tfNPP}
Fall time, Vpp
tvPPF
1
1
I'll
I'll
10
9.5
10
ma
NOTE 5: RIse/fail time s 10 ns
~ThxAs
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON, TEXAS 77251-1443
7-81
TMS28F020
2097152·8IT FLASH MEMORY
SMJS020B - OCTOBER 1994 - REVISED JUNE 1995
timing requirements-alternative E-controlled writes
ALTERNATE
SYMBOL
'28F020-10
MIN
'281'020-12
MAX
MIN
'28F02O-16
MAX
MIN
MAX
'28F020-17
MIN
MAX
UNIT
tc(W)
Cycle time, write using E
tAVAV
100
120
150
170
ns
tc(E)PR
Cycle time, programming
operatlcn
teHEH
10
10
10
10
!.IS
th(EA)
Hold time; address
tELAX
75
80
80
80
ns
th(ED)
th(w)
Hold time, data
teHDX
10
10
10
10
ns
Hold time, W
0
0
0
ns
Setup time, address
teHWH
tAVEL
0
tau(A)
0
0
0
0
ns
tau (D)
Setup time, data
tDVEH
50
50
50
50
ns
tau(W)
Setup time, W before E
0
0
0
0
ns
tauIVPPEL)
Setup time, Vpp to E low
twLEL
tyPEL
1
1
1
1
!.IS
trac(E)R
Recovery time, write using E
before read
tEHGL
6
6
6
6
!.IS
trec(E)W
Recovery time, read before
write using E
tGHEL
0
0
0
0
!.IS
tw(E)
Pulse duration, write using E
tELEH
70
70
70
80
' ns
tw(EH)
Pulse duration, write, E high
tEHEL·
20
20
20
20
ns
PARAMETER MEASUREMENT INFORMATION
-1
2.08 V
Output
Under Test
I
RL =600Q
CL-100pF
(_NoteA)
NOTE A: CL Includes probe and fixture capacitanca.
LOAD CIRCUIT
2.4V
O.4SV
=X
2V
0.8 V
O.!~ X'--__
VOLTAGE WAVEFORMS
The ac testing inputs are driven at 2.4 V for logic high and 0.45 V for logic low. Timing measurements are made
at 2 V for logic high and 0.8 V for logic Iowan both inputs and outputs. Each device should have a 0.1-I4F ceramic
capacitor connected between Vee and VSS as close as possible to the device terminals.
Figure 4. Load Circuit and Voltage Waveforms
~1ExAs
INSTRUMENTS
7-62
POST OFFICE BOX 1.443 • HOUSTON. 'reXAS 772S1-1443
TMS28F020
2097152·81T FLASH MEMORY
SMJS020B - OCTOBER 1994 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~~-----------~~----------~·I
1
I
AD-A17
----""'X"-_____
.....,.X.,-------
Ad_d_f8_..
_Ya_lId_ _ _ _
I..
,
,,------------~~,______~,--------~~I
, I+-- -----t
,+--- ~,
ta(A)
------------~
e
.,
'
ta(E)
-----T--i"
G
:!'to'
i
J'
w--./
trac(W)
-H
:.i ,
tan(G) -.:
,
, ,
,
,-+,
14.1,
HI-Z
,"
(«««{
tclla(E)
''
,
I,
"
,
i 14-- tcJla(G) ~
I+-- th(D) ~
,
tcJ(G) ,
tcl(E)
DQD-DQ7
Ii.'
{I
I
, ,
Ouput Valid
}»»»}- HI-Z -
Figure 5. Read-Cycle Timing
~TEXAS
,INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
7-83
TMS28F020
2097152·81T FLASH MEMORY'
SMJS020B - OCTOBER 1994- REvIsED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Power Up
and
Standby
ProgramCommand
Latch
ProgramAdd....
Verify
and Data Programming Command
Set-UpProgram
Command
Program
VerHlcation
~I;~~~~
r-- 4
AO-A17
~I+--
tc(W)"
feu(A)
~ I
I
1tI(A)
I..
I
teu(E)
~ !+"
I
~I
/
.
th(E)
tracCR)
tiIIIII+-
-.t
tclW)
I
1
~
feu(A)
-+I j+" feu(E) I
I
I
I
I!II-"--I~*"I-
,
1·\
I,......-tc(W)PR
tw(WH)
I
I
Vi
I
1-rJ
I,.I I I
-.J
14-
ItI(WHD)
feu(D)
~
. II
I I
\S
tw(W) ....
I..-
I
'.S
.
VCC
5V--.I
OV
-+:
VPP:::: ____
>-----C
Data In '" Cbh
fl;
~
I
tcllaCO)
Ii
I III
~ 14I I i+1-
'1tI(D)
fenCO)
14-+ tclCO)
I
'LI'
tcI(E) 1,.1
feCE) I..
I
«( =
»~
Jf
\l8I~
~I
Data-Out
\'j
~ feU(vpPEL)
#f1~i------------------~%~------------~~~S------------~~
-.I 1+
Ir(vPP)
If(vpp)
Figure 6. Wrlte-cyclenmlng
:ilTEXAS
7-84
II~
IIII
II
I
\
Data In
I
.+.I
I"
ItI(WHD) I
~U(D)
14-
I ..,.._'"
II
I I l+I
{f""j!--""'\\
I (\
I
-'
I I !\
I ! . - - trac(W) I :..1 I
I
I
iT'll
I
DQO-DQ7 ~ HI-Z
I
I
I
I
I
I
tclla(E)
14- ItICE)
'A'
"if
If.!i I,.-
\
j4'""" tw(W)
I
I
I
1+-1tI(A)'
I~
-.114- feu(E)
I -+J 14- 1tI~
~..-
~I
~
14----:' tc(R) -1+1
tc(W)
~
StandbyI
Power Down
INSTRUMENTS
POST OFFICE BOX 1443 • HO\JSTON. 'IEXAS 77251-1443
-+! 14-
TMS28F020
2097152·81T FLASH MEMORY
SMJS020B - OCTOBER 1894 - REVISED JUNE 1985
PARAMETER MEASUREMENT INFORMATION
Program·
Command
Latch
ProgramAcId.....
Verify
and Data Programming Command
Power Up SetoUpand
Program
Standby Command
AO-A17
Program
VerlftcaUon
~~~~~
I"
-I.-r- 4 ~
~
1e(W}
1e(W) ---.I
I
teu(A)
th(EA)
.
r---,. _ _
-.II
I
~
1e(W}
I
-.j
1e(R)
:.- 1h(EA)
~"I " (A)
U',
I
Standbyl
Power Down
~
J+I
I
III
\....
-HI IIrL XI I
I
\\
I
1\ y""I-""'\
""""""----!.~ ~
~
l- - I ~
~I
~~N:
E J'--""I
"r~
III
I I
I
I
rtJ
!.I I I
I I I . ~ ~1h(D)
~
1"- I
H.! ~
I II ~
~ r- I ..I ~
~ L.- I
l I~
teu~(DL.L.- I ~U(D)
~
I I 11
.-rit!
{« ~ »~
lI
~ I J"T
=
=
I"
_I
IV...I II
\....
1h(W}
--II
I
1
I
trac(E)W
I
--I ~
teu(W)
M
~ ~ 1h(W}
~ j+ teu(W) I
I
I
'Ii
1+--Ie(E)PR
I
Ih(ED)
....
Ih(ED)
tw(E)
tw(E)
lella(O)
~ 1h(W}
-.j
Ih(ED)
tw(E)
yi,-
ten(G)
IeI(O)
teu(D)
DQO-DQ7
HI-Z
Data In
Ditta In
.
40h
Data In COb
.
1eI(E)
te(E)
1;d Data.()ut
\'J
VCC
oV
VppVpPH
VPPL
r--+
~
teu(vpPEL)
,
S'
fl;
I
I I
~ (+tr(vpp)
'LII
--./ I+- tf(VPP)
Figure 7" Wrlte.Cycle (Alternative E.Controlled Writes) nmlng
~1ExAs
INSTRUMENTS
POST OFFICE BOX , _ • HOUSTON. TEXAS 71211-1_
7.f16
TMS28F020
2097152·81T FLASH MEMORY
SMJS020B - OCTOBER 1894- REVISED JUNE 1885
PARAMETER MEASUREMENT INFORMATION
Power Up Set-Upand
Era..
standby Command
Eraae
Command
Erulng
AO-A17
tc(W)
14
.1
~ tc(W)
I
-'-"I
14"
tau(E)
!
1w(WH)
I
14----1......
1
Era_
Verify
Command
Erase
Standbyl '
VerHlcatlon Powar Down
~~~~
I
I
-.l
I+-:- tc(R)
tc(W)
14- th(A)
~
--t-I
I
I
~tau(A)
~~
J+'
I
I I
I I
"
...,
tau(E)
-+J~ 1h(E)
I I
~ ~ th(E) I I
~ J4- Idla(E)
111111~1
U!
I "I
II '
I
J4- trac(W) r;"1 I
II
~ tc(E)EB ~
I II I
-ri 14- Idla(Q)
~'''--'I
1111
TI
\...
,I
I,
VI
I II I
-+J I"- th(D)
I
!I I
I I-.! 14- Ih(WHD)
II I
I II I
ta
th(WHD) ...j..j 14I I I
I t.! 14- Ih(WHD) I II l.--.r n(O)
,
twlW) -.i I.-+I j+" ~(W)
tw(W) -.I I.1 ~ Id(Q)
taU(D,~1.--il.-tau, (D)~,
u(D) ~I.I I
I
I
I
DQO-DQ7
~
HI-Z ,
.
5V
VCC
OV
J
I
.
II'
I
,
Data In
I
~
I14-
=20h
Data In • 20h .
. Data In =AOh
I
'j
1d(E)
ta(E)
II
II
II
II
tau(vpPEL)
Figure 8. Flash-Erase-Cycle TIming
~TEXAS ,,'
7-88
INSTRUMENTS
POST OFFICE BOX t_ • HOUSTON,TEXAS mIIl-l_
!!141,
14
lJ.
{« !t~
J1.1
~lld Data..()ut
\..
TMS28F200BZT, TMS28F200BZB
2097152·BIT BOOT·BLOCK FLASH MEMORY
• Organization
- 'TWo BK-Byte Parameter Blocks
- One 96K-Byte Main Block
- One 12BK-Byte Main Block
- One 16K-Byte Protected Boot Block
- Top or Bottom Boot Locations
• All Inputs/Outputs TTL Compatible
• Maximum Access/Minimum Cycle Time
Vee :t 5%
Vee:t 10%
60 ns
'2BF2ooBZ-6-x
'2BF200BZ-7D-x 70 ns
'2BF2ooBZ-SO-x 80 ns
'2BF200BZ-90-x 90 ns
• 100000 and 10000 Program/Erase Cycle
Versions
• Three Temperature Ranges
- Commercial ••• O·C to 70°C
- Extended ••• - 40°C to 85°C
- Automotive ••• - 4O·C to 125·C
• Low Power Dissipation (Vee 5.5 V)
- Active Write ••• 330 mW (Byte Write)
- Active Read ••• 330 mW (Byte Read)
- Active Write ••• 358 mW (Word Write)
- Active Read ••• 330 mW (Word Read)
- Block Erase ••• 165 mW
- Standby ••• 0.55 mW (CMOS-Input
Levels)
- Deep Power-Down Mode ••• 0.0066 mW
• Fully Automated On-Chip Erase and
Word/Byte Program Operations.
• Write Protection for Boot Block
• Command State Machine (CSM)
- Erase SuspendlResume
- Algorithm-Selection Identifier
DBJ PACKAGIa
(TOP VIEW)
Vpp
NC
NC
A7
A6
AS
A4
A3
A2.
A1
AO
'E
Vss
~
OQO
OQS
OQ1
OQ9
OQ2
OQ10
OQ3
OQ11 22
=
44
43
RP
'Ii
42
AS
41
AS
40
A10
A11
A12
A13
A14
A15
A16
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
BYfE
Vss
OQ15/A_1
OQ7
OQ14
OQ6
OQ13
OQ5
OQ12
0Q4
z
-tc(
o
Vee
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a:
PIN NOMENCLATURE
AO-A16
Address Inputs
BYTE
Byte Enable
ou.
-zw
DQO-DQ14 Data In/Out
DQ15/A_1 Data In/Out (word-wlde mode).
,
Low'()rder Address (byte-wlde mode)
DU
Do Not Use
E
G
NC
Chip Enable
Output Enable
No Internal Connection
RP
Vee
VPP
VSS
Reset/Deep Power-Down
S-V Power Supply
12-V Power Supply for Program/EIU8
Ground
.Vii
description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
o
z
c~
c
~
AcId .....
R.ng.
1FFFFh
1EOOOh
1DFFFh
1DOOOh
1CFFFh
1COOOh
1BFFFh
10000h
OFFFFh
OOOOOh
All Is LSB AcId,...
Figure 1. TMS28F200BZf (Top Boot Block) Memory Map
z
Acldra..
R.ng.
n
m
-z
3FFFFh
20000h
1FFFFh
."
o
s:
~
O8OOOh
07FFFh
:IJ
O6OOOh
05FFFh
04000h
03FFFh
(5
Z
OOOOOh
..8 Configuration
..18 Conflgur.tlon
M.lnBlock
128KAdd.......
M.lnBlock
14K AcId,.....
M.lnBlock
96KAcldra....
M.lnBlock
48K AcId,.....
P.r.metar Block
IKAdd.......
P.rameter Block
4KAcld_
P.r.m.tar Block
8K AcId,.....
P.rameter Block
4KAcld_
Boot Block
18K Acldra....
Boot Block
8KAcldreeeee
DQ15/A_1 Is LSB AcId,...
AcId,...
R.ng.
1FFFFh
10000h
OFFFFh
04000h
03FFFh
03000h
O2FFFh
02000II
01FFFh
00000h
All Is LSB AcId .....
Figure 2. TMS28F200BZB (Bottom Boot Block) Memory Map
boot-block data protection
The 16K-byte boot block is used to store key system data that is seldom changed in normal operation. To protect
data within this memory sector, the RP terminal can be used to provide a lockout to eliminate accidental erase
or program operations. When RP is operated with normal TTL/CMOS logic levels, the contents of the boot block
cannot be erased or reprogrammed. Changes to the contents of the boot block can be made only when RP is
at VHH (nominally 12 V) during normal write/erase operations.
parameter block·
Two parameter blocks of 8K bytes each can be used like a scratch pad to store frequently updated data.
Alternately, the parameter blocks can be used for additional boot- or main-block data. If a parameter block is
used to store additional boot-block data, caution should be exercised because the parameter block does not
have the boot-block data-protection safety feature.
~TEXAS
7·90
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lEXAS 77251-1443
TMS28F200BZT, TMS28F200BZB
2097152·BIT BOOT·BLOCK FLASH MEMORY
SMJS200B - JUNE 1994 - REVISED JUNE 1995
main block
Primary memory on the TMS28F2008ZX is located in two main blocks. One of the blocks has storage capacity
of 128K bytes and the other block has storage capacity of 96K bytes.
command state machine (CSM)
The CSM is the interface between an external microprocessor and the write state machine and status register
on the memory chip. When the WSM has completed a task, the WSM status (WSMS) bit (S87) is set to a logic
high (1), allowing the CSM to respond to the full command set.
status register (SR)
The status register provides a means of determining whether the state of a program/erase operation is pending
or complete. The status register is read by writing a read-status command to the CSM and reading the resulting
status code on I/O terminals 000-007. This is valid for operation in either the byte- or word-wide mode. When
the device is operating in the word-wide mode, the high order I/Os (008-0015) are set to OOh when performing
a read-status operation.
After a read-status command has been given, the data appearing on 000-007 remains as the status register
data until a new command is issued to the CSM. To return the device to other modes of operation, a new
command must be issued to the CSM.
Register data is updated on the falling edge of G or E. The latest falling edge of either of these two signals
updates the latch within a given read cycle. Latching data prevents errors from occurring should the register
input change during a status-register read. To assure that the status-register output contains updated status
data, E or G must be toggled for each subsequent status read.
The status register provides the internal state of the WSM to the external microprocessor. During periods when
the WSM is active, the status register can be polled to determine the WSMS. Table 1 defines the status register
bits and their functions.
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:E
a:
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c~
«
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7-91
TMS28F200BZT, TMS28F200BZB
2097152.;.BIT BOOT-BLOCK FLASH MEMORY
SMJS200B - JUNE 1994 - REVISED JUNE 1995
status register (SR) (continued)
Table 1. Status Register Bit Definitions and Functions
STATUS
BIT
FUNCTION
COMMENTS
c,
DATA
Write-state-machlne status
(WSMS)
1 .. Ready
0= Busy
If SB7 .. 0, the WSM has not completed an erase or programming
operation. If SB7 = 1 (ready),other polling operations can be
performed. SB7 does not automatically update WSM status atthe
completion of a WSM task. If the WSM status bit shows busy (0),
the user must periodically toggle IE or G to determine when the
WSM hes completed an operetlon (SB7 = 1).
SB8
Erase-suspend status
(ESS)
1 = Erase suspended
o= Erase in progress or
completed
When an erase-suspend command Is Issued, the WSM halts
execution and sets the ESS bit high (SB8 .. 1) Indicating that the
erase operation has been suspended. The WSMS bit is also set
high (SB7 = 1) Indicating that the erase-suspend operation has
been successfully completed. The ESS bit remains at a high level
until an erase-resume command Is Input to the CSM (code DOh).
»
~
l>
SBS
Erase status
(ES)
1.. Block erase error
0 .. Block erase good
SBS .. 0 indicates that a successful block erasure has occurred.
SBS .. 1 indicates that an erase error has occurred. In this case,
the WSM has completed the maximum allowed erase pulses
determined by the internal algorithm, but this was insufficient to
completely erase the device.
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o
SB4
Program status
(PS)
1 .. Byte/Word progrem error
0= Byte/Word program good
SB4 = 0 indicates successful progremmlng has occurred at the
addreased block location. SB4 .. 1 indicates that the WSM was
unable to correctly program the addreased block location.
SB3
Vppstatus
(Vpps)
1 "' Program abort:
Vpptoolow
0= Vppgood
SB3 provides information on the status of Vpp during
programmlng.lfVpp is too Iowafter a program orerasecommand
has been issued, SB31ssettoa 11ndlcatingthattheprogrammlng
operation is aborted. The Vpp status bit is not assured to give
accurate feedback between VpPH and VPPL.
SB2SBO
Reserved
SB7
-
:D
I:
~
oz
The.. bits should be masked out when reading the statUs
register.
operation
Oevice operations are selected by entering standard JEOEC 8-bit command codes with conventional
microprocessor timing into an on-chip command state machine (CSM) through I/O terminals OQO-OQ7. When
the device is powered up, internal reset .circuitry Initializes the chip to a read-array mode of operation. Changing
the mode of operation requires a command code to be entered into the CSM. Table 2 lists the CSM codes for
all modes of operation.
The on-Chip status register allows the progress of various operations to be monitored. The status register is
interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data
on I/O terminals OQO-OQ7 (cycle 2). Status-register bits SBO through SB7 correspond to OQO through OQ7.
~TEXAS
7-92
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 7721i1-1443
TMS28F200BZT, TMS28F200BZB
2097152·BIT BOOT·BLOCK FLASH MEMORY
SMJS200B - JUNE 1994 - REVISED JUNE 1895
operation (continued)
Table 2. Command State Machine Codes for Device Mode Selection
COMMAND
CODE ON
DQO-DQ7 t
DEVICE MODE
OOh
Invalid/Reserved
Alternate Program Setup
10h
Block-Erase Setup
20h
Program Setup
40h
SOh
Cleer-status Register
70h
Read-status Register
Algorithm SelectIon
90h
BOh
Erase Suspend
DOh
Erase Resume/Block-Erase Confirm
Read Array
FFh
t DQO 18 the least significant bit. OQa-OQ15 era any valid 2-state level.
command definition
z
Once a specific command code has been entered, the WSM executes an internal algorithm generating the
necessary timing signals to program, erase, and verify data. See Table 3 for the CSM command definitions and
data for each of the bus cycles.
o
Following the read-a1gorithm-selection-code command, two read cycies are required to access the
manufacturer-equivalent code and the device-equivalent code as shown in Table 4 and Table S.
:E
Table 3. Command Definitions
FIRST BUS CYCLE
BUS
CYCLES
REQUIRED
OPERAnoN
Reed Array
1
Write
Reed AlgorIthm-Selection Code
3
Read-Status Register
Clear-Status Register
COMMAND
SECOND BUS CYCLE
CSM
INPUT
OPERATION
ADDRESS
DATA
IN/OUT
X
FFh
Read
X
Date Out
WrIte
X
90h
Reed
AO
MID
2
Write
X
70h
Read
X
SRB
1
Write
X
50h
ADDRESS
Read Operations
2
Write
PA
2
Write
BEA
(,)
Z
CC
40h or 10h
Write
PA
PD
20h
Write
BEA
DOh
Write
X
DOh
Erase Suspend!
Write
X
BOh
2
Erase Resume.
Legend:
BEA
BIock_ address. Any addresa selected within a block selects that block for erase.
M/D Manufacturer-equlvalent/devioe-equlvalent code
PA
Address to be programmed
PO
Data to be programmed at PA
SRB
Status-register data byte that can be found on DQO-DQ7
~1EXAs
INSTRUMENTS
-zw
~
Erne OperaUons
Block-Erase Setup!
Block-Erase Confirm
a:
~
C
Program Mode
Program Setup/Program
(byte/word)
ti
POST OFFICE sox 1443 • HOUSlON. ll!XAS 77251-1443
7-93
TMS28F200BZT, TMS28F200BZB
2097152·BIT BOOT·BLOCK FLASH MEMORY
SMJS200B - JUNE 1994 - REVISED JUNE 1995
byte-wide or word-wide mode selection
The memory array is divided into two parts: an upper half byte that outputs data through I/Os oo8-0Q15, and
a lower half byte that oUtputs data through OQO-OQ7. Device operation in either byte-wide or word-wide mode
is user-selectable and is determined by the logic state of BYTE. When BYTE is at a logic high level, the device
is in the word-wide mode and data is written to or read from 110s OQO-OQ15. When BYTE Is at a logic low, the
device Is In the byte-wide mode and data is written to or read from I/Os OQO-OQ7.In the byte-wide mode, I/Os
OQ8-0Q14 are placed in the high-impedance state and OQ15/A_1 becomes the low-order address terminal
and selects either the upper or lower half of the array. Array data from the upper half (OQ8-0Q15) and the lower
half (OQO-OQ7) are multiplexed and appear on OQO-OQ7. Table 4 and Table 5 summarize operations for
word-wide mode and byte-wide mode.
Table 4. Operation Modes for Word·Wlde Mode (BYTE .. VIti>
E
G
RP
W
At
AO
Vpp
DQO-OO16
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
X
X
X
VIO
VIL
x
VIL
VIL
VIH
VIH
VIO
VIH
X
Oataout
Manufacturer-equlvalent code 0089h
Devlce-equlvalent code 2274h
(top boot block)
VIL
VIH
X
VIH
VIH
VIH
VIH
X
X
X
X
X
VIL
VIHor
VHH
X
X
X
X
X
X
MODE
Read
l>
Algorlthm-selection mode
.
C
.~
Z
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~
(5
Z
Output disable
Standby
Reset/deep power down
Write (see Note 1)
VIL
X
X
VIH
X
VIL
Devlce-equlvalent code 2275h
(bottom boot block)
High Impedance
High Impedance
High Impedance
VpPLor Detain
VPPH
X
Table 5. Operation Modes for Byte-Wide Mode (BYTE .. VIL>
MODE
Read lower byte
Read upper byte
E
Q
RP
W
At
AO
Vpp
DQ16/A_1
008..;0014
VIL
VIL
VIL
VIH
VIH
X
VIL
VIH
VIH
X
X
X
X
X
VIL
VIH
HI-Z
HI-Z
VIL
VIL
VIH
VIH
VIO
VIL
X
X
HI-Z
Algorlthm-salection
mode
Output disable
Standby
Reset/deep power
down
DQO-OO7
Data out
Data out
Manufacturer-equlvalent
code89h
Devlce-equlvalant code
74h (top boot block)
VIL
VIL
VIH
VIH
VIO
VIH
X
X
HI-Z
VIL
VIH
VIH
VIH
VIH
VIH
X
X
X
X
X
X
High Impedance
X
X
X
HI-Z
X
HI-Z
High Impedance
X
X
VIL
X
X
X
X
X
HI-Z
High Impedance
Devlce-equlvalant code
75h (bottom boot block)
VpPL
or
X
HI·Z
Data In
I
VpPH
..
NOTE 1: When writing commands to the '28F200BZx, Vpp must be VPPH for block-erase or program commands to be executed and J'US must
be held et VHH for the entire boot block program or erase operation.
Write (see Note 1)
VIL
VIH
VIHor
VHH
VIL
X
X
~1ExAs
INSTRUMENTS
7-94
POST OFFICE BOX 1443 • HOUSTON, 'IEXAB 77251-1443
TMS28F200BZT, TMS28F200BZB
2097152·BIT BOOT·BLOCK FLASH MEMORY
SMJS200B - JUNE 1l1li4 - REVISED JUNE 1895
command sta~ machine (CSM) operations
The CSM decodes instructions for read, read algorithm-selection code, read status reglstar, clear status
register, program, erase, erase suspend, and erase resume. The B-bit command code is input to the device on
000-007 (see Table 2 for CSM codes). During a program or erase cycle, the CSM Informs the WSM that a
program or erase cycle has been requested. During a program cycle, the WSM controls the program sequences
and the CSM responds only to status reads.
During an erase cycle, the CSM responds to status reads and erase suspend. When the WSM has completed
its task, the WSM status bit (S87) is set to a logic high and the CSM responds to the full command set. The CSM
stays in the current command state until the microprocessor issues another command.
The WSM successfully initiates an erase or program operation only when Vpp is within its correct voltage range
(VpPH). For data protection, it Is recommended that'RP be held at a logic low during a CPU reset.
read operations
There are three read operations available: read array, read algorithm-selection code, and read status register.
read array
The array is read by entering the command code FFh on 000-007. Control terminals ~ and ~ must be at a
logic low (Vld and Wand RP must be at a logic high (VIH) to read data from the array. Data Is available on
000-0015 (word-wide mode) or 000-007 (byte-wide mode). Any valid address within any of the blocks
selects that block and allows data to be read from the block.
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0
'""4,
read algorlth",...,flCtlon cod.
~
Algorithm-selection codes are read by entering command code 90hon DOO-D07. 'TWo bus cycles are required
for this operation: the first to enter the command code and a second to read the device-equivalent code. Control
terminals E and ~ must be at a logic low (Vld and Wand RP must be at a logic high (VIH>. Two Identifierbytes
are accessed by toggling AO. The manufacturar-equivalent code is obtained on DOO-D07 with AO at a logic Z
low (Vld. The device-equivalent code is obtained when AO Is set to a logic high (VIH>. Alternately, the
manufacturer- and device-equivalent codes can be read by applying VIO (nominally 12 V) to AS and selecting W
the desired code by toggling AO high or low. All other addresses are don't care (see Table 3, Table 4, and (J
TableS).
Z
a::
~
-
read status reglst.r
The status register is read by entering the command code 70h on 000-007. Control terminals ~ and ~ must
be at a logic low (Vld and Wand 'RP must be at a logic high (VIH). Two bus cycles are required forthis operation:
one to enter the command code and a second to read the status register. In a given read cycle, status register
contents are updated on the failing edge of E or G, whichever occurs last within the cycle.
clear status register
The internal circuitry can set only the Vpp status (S83), the program status (S84), and the erase status (S85)
bits of the status register. The clear-status-register command (SOh) allows the external microprocessor to clear
these status bits and synchronize to internal operations. When the status bits are cleared, the device returns
to the read array mode.
boot·block progremmlng/e,.slng
Shouldchangestothebootbiockberequired,RJ5mustbesettoVHH(12V)andVpptothep~ammlngvoltage
level (VpPH). If an attempt Is made to write, erase, or erase suspend the boot block without RP at VHH, an error .
Signal Is generated on SB4 (program-status bit) or S85 (erase-status bit).
A program-setup command can be aborted by writing FFh Qn byte-wide mode) or FFFFh Qn word-wide mode)
during the second cycle. After writing FFh or FFFFh during the second cycle, the CSM responds only to status
reads. When the WSM &tatus bit (S87) is set to a logic high, signifying termination of the non program operation
is terminated, all commands to the CSM become valid again.
-!I
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7-95
~
~
TMS28F200B~, TMS28F200BZB
2097152..BIT BOOT·BLOCK FLASH MEMORY
SMJS2OO6-'JUNE 1884- REVISED JUNE 1896
normal programming
There are two CSM commands for programming: program setup and alternate program setup
(see Table 2 ()fl page 7). After the desired command code is entered, the WSM takes over and correctly
sequences the device to complete the program operation. During this time, the CSM responds only to status
reads until the program operation has been completed, after which a" commands to the CSM become valid
again. Once a program command has been Issued, the WSM cannot normally be Interrupted until the program
algorithm Is completed (see Figure 4 and Figure 4). Taking RJ5 to VIL during programming aborts the program
operation. During programming, Vpp must remain at VpPH' Only OS are written .and compared during a program
operation. If 1s are programmed, the memory cell contents do not change and no error occurs.
A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)
during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status reads.
When the WSM status bit (SB7) is set to a logic high, signifying the nonprogram operation Is terminated, a"
commands to the CSM become valid again.
eraae operatlona
There are two erase operations that can be performed by the TMS28F200BZX devices: block erase and erase
suspend/erase resume. An erase operation must be used to initialize all bits In an array block to 1s. After
block-erase confirm is issued, the CSM responds only to status reads or erase-suspend commands until the
WSM completes its task.
~
~
z
bIocIc erasura
Block erasure Inside the memory array sets all bits within the addressed block to logic 1s. Erasure la
accomplished only by blocks; data at single address locations within the array cannot be IndMduaily erased.
Any.va"d address within the parameter or main blocks acts as a block selector and allows that block to be
erased. RP must be·at VHH for changing the data content of the boot block. Block erasure lalnltlated by a
command sequence to the CSM: block-erase setup (20h) followed by block-erase confirm (DOh). A
two-command erase sequence protects against accidental erasure of memory contents.
(')
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II
Erase setup and confirm commands are latched on the rising edge of E' or W, whichever ocCurs first. Block
addresses are latched during the block-erase-confirm command on the rising edge ofE orW (see Figure 5).
When the block-erase-confirm command is complete, the WSM automatically executes a sequence of events
to complete the block erasure. During this sequence, the block is programmed with logic OS, data Is verified,
all bits In the block are erased, and finally, verification Is performed to assure that all bits are correctly erased.
Monitoring of the erase operation Is possible through the status register (see read status register).
.,.." su."."dI.,.." rasums
During the execution of an erase operation, the erase-suspend command (BOh) can be entered to direct the
WSM to suspend the erase operation. Once the WSM has reached the suspend state, It allows the CSM to
respond only to the read-array, read-status-reglster, and erase-resume commands. During the erase-suspend
operation, array data should b$ read from a block other than the one being erased. To resume the erase
operation, an erase-resume command (DOh) must be issued to cause the CSM to clear the suspend state
previously set (see Figure 5 and Figure 10).
automatic powe.....vlng mode
Substantial power savings can be realized during periods when the array Is not being read. During this time,
the device switches to the automatic power-saving mode. When the device switches to this mode,lcc is typically
reduced from 40 mA to 1 rnA (lOUT = OmA). The low level of power Is maintained until another read operation
is initiated. In this mode, the I/O terminals retain the data from the last memory address read until a new address
is read. this mode Is entered automatically if no address or control pins toggle within a 200-ns time-out period.
At least one transition on E must occur after power up to activate this mode.
~1ExAs
7-98
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS28F200BZT, TMS28F200BZB
2097152-BIT BOOT-BLOCK FLASH MEMORY
SMJS200B - JUNE 1994 - REVISED JUNE 1896
reset/deep power-down mode
Very low levels of power consumption can be attained by using a special terminal, RP, that disables internal
device circuitry. When RP is at a CMOS logic low of 0.0 V z 0.2 V, an Icc value on the orde~ of 0.2 JAA (or 1 jJ.W
of power) is achievable. This is important in portable applications where extended battery life is of major
concern.
A recovery time is required when exiting from deep power-down mode. For a read-array operation, a minimum
of 300 ns is required before data is valid, and a minimum of 215 ns in deep power-down mode is required before
data input to the CSM can be recognized. With RP at ground, the WSM is reset and the status register is cleared,
effectively eliminating accidental programming to the arra~uring system reset. After restoration of power, the
device does not recognize any operation command until RP is returned to a VIH or VHH level.
Should RP become low during a program or erase operation, the device becomes nonfunctional Qs in a
power-down state) and data being written or erased is invalid or indeterminate, requiring that the operation be
performed again after power restoration.
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Z
(.)
Z
c~
--.....,NVpp Range Error
i:
~
6
z
Standby
Stand~y
COMMENTS
CheckSB3
1 .. Detect Vpp low
(see Nota B)
CheckSB4
1 .. Byta program error
(see Note C)
NOTES: A. Full atatua-reglatar check cen be done after each word or after a sequence of words.
B. SB3 must be cleared before attampting additional program I erase operations.
C.. SB41a cleared only by the clear-atalus-regiBter commend, but it does not prevent additional program operation attempts. ,
Figure 3. Automated Byte·Programmlng Flowchart
~TEXAS
7-98
INSTRUMENTS
POST OFFICE BOX 1~ • HOUSTON. TEXAS 77251-1~
TMS28F200BZT, TMS28F200BZB
2097152·BIT BOOT·BLOCK FLASH MEMORY
SMJS200B- JUNE 1994 - REVISED JUNE 1996
BUS
COMMAND
OPERATION
Start
COMMENTS
Writ.
Write
program
setup
Data .. 40h or 10h
Addr " Addresaof
word to be
programmed
Write
Write data
Data .. Wordtobe
programmed
Addr .. Addresaof
word to be
programmed
Write Progrllm-8etup
Command, Word
Add .....
R..d
Status register data.
Toggle GorE to update
status register.
Standby
CheckSB7
1 .. Ready, 0 • Busy
Repeat for subsequent words.
Write FFh after the last word-programming operation to
reset the device 10 read-array mode.
S.. NoteA
z
o
~
:E
a:
o
LL
Word Program
Completed
-w
FULL STATUs-REGISTER-C:HECK FLOW
Z
BUS
COMMAND
OPERATION
COMMENTS
Stendby
CheckSB3
1 .. Detect Vpp low
(see Note B)
Standby
CheckSB4
1 .. Word program
failed
(see Note C)
c~
c
z~
o
Erase
Data .. DOh
BlockAddr .. Add,...
within
block to
be
erased
RNd
Status register data.
Toggle G or E to updste
status register
Standby
CheckSB7
1 .. Ready. 0 .. Busy
Repeat for subsequent blocks.
WrIte FFh after the last block-erase operation to resetthe
device to read-array mode.
m
-z
FULL STATU8-AEGISTER-CHECK FLOW
."
o
BUS
COMMAND
OPERATION
:XI
I:
hndby
CheckSB3
1 .. DetectVpp low
(see Note B)
Command Sequence
Error
Standby
Check SB4 and SB5
1 .. Block-erase
command error
Block Era.. Failed
Standby
CheckSB5
1 .. BIock-erase failed
(see Note C)
Vpp Range Error
.~
oz
COMMENTS
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program/erase operations.
C. SBSIs cleared only by the cIear-status-reglster oommand In cases where multiple blocks are erased before full status Is checked.
Figure 5. Automated Block·Erase Flowchart
~TEXAS
7-100
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS28F200BZT, TMS28F200BZB
2097152·BIT BOOT·BLOCK FLASH MEMORY
SMJS200B - JUNE 1984- REVISED JUNE 11195
BUS
OPERATION
Wrlte
COMMAND
Erase
suspend
COMMENTS
Data-BOh
R«Jd
Status register data.
Toggle (lorE to update
status reglatar.
Standby
CheckSB7
1 .. Ready
Standby
ChackSB6
1 .. Suspended
No
z
Wrlte
Read
o
Ii
Data=FFh
memory
:E
Read data from block
other than that being
Read
E_ConUnued
Erase
resume
Data = DOh
o
z
c~
SMNoteA
NOTE A: Refer to bIock-erase flowchert for oompJate erasure procedure.
VCC
IpP2
VPP supply current (active byte write)
VPP=VPPH,
Programming In progress
30
mA
IpP3
VPP supply current (ective word write)
VpP=VPPH,
Programming In progress
40
mA
IpP4
VPP supply current (block erase)
VpP=VpPH,
Block erase In progress
30
mA
IpP5
VPP supply current (erase suspend)
VPP=VPPH,
Block erase suspended
200
t&A
Ices
Vee supply current
(standby)
ICeL
down mode)
ICC1
500
500
:1:10
VO=OV toVcc
10
5
TTL·lnput level
VCC-6,5V,
E .. RP=VIH
1.6
rnA
CMOS·lnput level
VCC .. 5.5V,
E .. RP=VIH
100
t&A
1.2
t&A
8
t&A
0·Ct070·{:
- 4O·C to 86·0
Vee supply current (reset/deep power·
RP .. VSS :l:0.2V
- 4O·C to 125·C
Vee supply current
(active reed)
VCC .. 5.5V,
TTL·lnput level
CMOS·lnput level
1= 10 MHz,
E.Vllo
10UT-OmA
60
mA
VCC=6.6V,
f=10MHz,
E .VSS :I: 0.2 V,
10UT=OmA
55
rnA
ICC2
Vee supply current (active byte write) (see Notes 10 and 11)
VCC=6.5V,
Programming In progress
60
rnA
1CC3
Vee supply current (active word write) (see Notes 10 and 11)
VCC=5.6V,
Programming in progress
66
mA
ICC4
Vee supply current (block erase) (see Notes_'0 and 11)
VCC .. 6•6V,
Block erase in progress
30
rnA
Ices
Vee supply current (erase suspend) (see Notes 10 and 11)
Vcc = 5.5 V,
E=VIH,
Block erase suspended
10
mA
NOTES: 6. Not 100% tested; charactenzaHon data 8VBllable
7. All ac current values are RMS unless otherwise noted.
Table 6. AC Test Conditions
SPEED DESIGNATOR
10L
(mA)
10H
(mA)
vzt
(V)
VOL
(V)
VOH
(V)
VIL
(V)
VIH
(V)
CLOAD
(pF)
(ns)
If
tr
(ns)
TEMPERATURE
·6
6.6
-2.6
1.5
1.5
1.6
0
3.0
30
<10
<10
0·Cto70·C
·70, ·60,'SO
5.6
-2.6
1.5
0.8
2.0
0.45
2.4
100
<10
<10
- 40·C to 125·C
t Vz Is the measured value used to detect high Impedance.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS n251-1443
7·103
z
o
ti::E
D!
oLL
-ow
Z
z
~
c
«
TMS28F200BZT, TMS28F200BZB
2097152-BI1 BOOT-BLOCK FLASH MEMORY
SMJS200B-JUNE 1984- REVISED JUNE 1986
capacitance over recommended ranges of supply voltage and operating free-air temperature.
f = 1 MHz. VI = 0 V
TEST CONomONS .
PARAMETER
CI
Co
MIN
Input~
Output capacitance
MAX
8
12
Vo=OV
UNIT
pF
pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
ALT.
SYMBOL
'28F200BZX.8
MIN
MAX
'28F200BZX·70
MIN
MAX
'28F200BZX·80
MIN
MAX
'28F200BZX·90
MIN
MAX
UNIT
tarAI
Access time from AO-A18
lAVQV
80
70
80
90
nl
tarE)
ta(G)
teLQV
tGLQV
lAVAV
80
70
35
80
90
80
70
80
90
nl
nl
nl
feI(E)
Access time from E
Access time from G
Cycle time, read
Delay time, E low'to
Iow-impedance output
teLQX
0
0
0
0
ns
feI(G)
Delay time, G low to
low-impedance output
tGLQX
0
0
0
0
ns
fells(E)
Disable time, E to
high·lmpedance output
teHQZ
20
25
30
35
nl
felis(G)
Disable time, G to
high-Impedance output
tGHQZ
20
25
30
35
nl
!h(0)
Hold time, OQ valid from
AO-A18, E, or G, whichever
occurs first
IAxQX
lsu(EB)
Setup time, BYTE from E low
tELFL
teLFH
5
5
5
5
nl
feI(RP)
Output delay time from RP
high
tPHQV
300
300
300
300
ns
~
felil(BL)
~Isable time, BYTE low to
008-0015 In
hlgh-impedsnce state
tFLQV
20
25
30
35
ns
Z
ta(BH)
Access time from BYTE
switching high
tFHQV
80
70
80
90
nl
terRI
l>
c
z~
o
m
-z
~
:xl
!:
(5
30
0
0
0
~TEXAS
7-104
INSTRUMENTS
POST OFFICE BOX 14<13 • HOUSTON, TEXAS 77251-14<13
45
40
nl
0
TMS28F200BZT, TMS28F200BZB
2097152-BIT BOOT-BLOCK FLASH MEMORY
SMJS200B - JUNE 1994 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
wrltelerase operations - W-controlled writes
ALT.
SYMBOL
'28F200BZX·6
MIN
'28F200BZX· 70
MAX
MIN
MAX
'28F200BZX·80
MIN
MAX
'28F200BZX·90
MIN
MAX
UNIT
60
70
80
90
ns
twHOVI
6
6
6
7
J1S
Cycle time, erase
operation (boot block)
twHOV2
0.3
0.3
0.3
0.4
s
fc(W)ERP
Cycle time, erase
operation (parameter
block)
twHOV3
0.3
0.3
0.3
0.4
s
fc(W)ERM
Cycle time, erase
operation (main block)
!wHOV4
0.6
0.6
0.6
0.7
s
IcI(RPR)
Delay time, boot·block
relock
tpHBR
Hold time, AO-AI6
twHAX
Hold time, DO valid
twHDX
0
0
Hold time, E
twHEH
10
10
th(VPP)
Hold time, Vpp from valid
status register bit
IQWL
0
0
th(RP)
Hold time, RP at VHH
from valid status register
bit
IQVPH
0
!su(A)
Setup time, AO-A16
tAVWH
!sueD)
Setup time, DQ
!su(E)
Setup time, E before write
operation
fcCW)
Cycle time, write
fc(W)Op
Cycle time, duration of
programming operation
fc(W)ERB
tAVAV
100
100
100
100
ns
10
ns
0
0
ns
10
10
ns
0
0
ns
0
0
0
ns
50
50
50
50
ns
tDVWH
50
50
50
50
ns
tELWL
0
0
0
0
ns
tpHHWH
100
100
100
100
ns
Setup time, Vpp to W
going high
tvPWH
100
100
100
100
ns '
twCW)
Pulse duration, W low
twLWH
50
50
50
50
tw(WH)
Pulse duration, W high
twLWL
10
20
30
30
ns
ns
IpHWL
215
215
215
215
ns
!h1A)
!hCO)
!hIE)
!su(RP)
!su(VPP)
Irec(RPHW)
~tup time, RP at VHH to
Wgoing high
R~ery time,
to W going low
RP high
10
10
10
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
7·105
z
o
ti
:E
a:
o
u.
-w
Z
CJ
Z
c~
c
~
MIN
MAX
'28F200BZX·70
MIN
MAX
'28f200BZx·80
MIN
MAX
'28F200BZX·90
MIN
MAX
UNIT
tclW)
Cycle time, write using E
tAVAV
60
70
80
90
ns
tc(E)OP
Cycle time, duration of
programming operation
usingE
tEHQV1
8
8
8
7
I4S
tc(E)ERB
Cycle time, erase operatlon using E (boot block)
teHQV2
0.3
0.3
0.3
0.4
s
tc(E)ERP
Cycle time, erase
operation using E
(peramater block)
teHQV3
0.3
0.3
0.3
0.4
s
tc(E)ERM
Cycle time, erase operation using E (main block)
tEHQV4
0.8
0.8
0.8
0.7
s
Id(RPR)
Delay time, boot-blOCk
relock
100
tpHBR
100
100
100
ns
thlA)
Hold time, AO-A18
tEHAX
10
10
10
10
ns
!h(D)
Hold time, DQ valid
tEHDX
0
0
0
0
ns
th(W)
Hold time, W
teHWH
10
10
10
10
ns
!h(VPP)
Hold time, Vpp from valid
status-register bit
taWL
0
0
0
0
ns
!h(RP)
Hold time, RP at VHH from
valid status-register bit
taVPH
0
0
0
0
ns
o:a
tsulA)
Setup time, AO-A18
tAVEH
50
50
50
Setup time, DQ valid
toVEH
50
50
tsu(WI
Setup time, W befora E
twLEL
0
0
50
0
50
50
ns
tsu(D)
0
ns
oz~
tsu(RP)
Setup time, RP at VHH to E
going high
tpHHEH
100
100
100
100
ns
tsu(VPP)
Setup time, Vpp to E going
high
tvPEH
100
100
100
100
ns
tw(E)
Pulse duration, E low, write
uslngE
tELEH
50
50
50
50
ns
tw(EH)
Pulse duration, E high,
write using E
teHEL
10
20
30
30
ns
tpHEL
215
215
215
215
ns
z
o
z
'TI
m
!:
Recovery time, RP high to
trec(RPHE) Egoinglow
~1ExAs
7-108
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
ns
TMS28F200BZT, TMS28F200BZB
2097152·BIT BOOT·BLOCK FLASH MEMORY
SMJS200B - JUNE 1994 - REVISED JUNE 1895
PARAMETER MEASUREMENT INFORMATION
1~4------~~------~·1
.JX,..___
AO-A18 _ _ _ _ _ _ _
.JX.....-----
Ad_d_re_
.._Ya_II_d_ _
j4-ta(A)
.1
E----------------~\
-
, *:.
T.
I
~ta~--+j
Q---------......j.!""\\
I
I
I
----"'*I :.-
,..---+1
14
.1
T.
ta(O)
tcl18(E)
-+i
I
I
tcl18(O) -.:
I
z
o
ri
::E
a:
o
LL
-Zw
Figure 7. Read·Cycle TIming
(J
Z
~
Q
«
-!11 TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
7-107
TMS28F200BZT, TMS28F200BZB
2097152-BIT BOOT-BLOCK FLASH MEMORY
SMJS200B -JUNE 1884 - REVISED JUNE 1895
PARAMETER MEASUREMENT INFORMATION
Power Up
Write
Program-8etup
Command
InCI
Standby
AO-A18
Data
X.,...--
~
14-- tc(W)
"u(E)-+l1+1
1
if
Write Valid
AcId,... or
1
~I+- tt.(E)
1
1
1
v
1 4 - - - tc(W)OP --~"I
1
tw(WH) -+l1"1-----.!
c,
n
-cgz
v
1
I
~
z
m
Read-Array
Command
II+
.. ---+..t-I-+1
I
1
l>
WrIte
Read Statu..
Regletar Blta
---.I
I
-/1
/
Automated
Byte/Word
Programming
1
1
Data
DQO-DQ7
(bytawlde)
DQO_ DQ15 -
>---
H~
(wordwlda)
:a
~
I
I
: \
.
~tt.(RP)
1
1
1+--+1- "u(VPP)
(5
Z
ValldSR
H~ --<({ ~
I
I
s::
I
I,
I
!+-.t- tt.(VPP)
1
1
VPP
Figure 8. Wrlte-Cycle TIming (W-Controlled Write)
~1ExAs
7-108
INSTRUMENTS'
POST OFFICE BOX 10M3 • HOUSTON, TEXAS 77251-10M3
C>::I,z-
TMS28F200BZT, TMS28F200BZB
2097152·BIT BOOT·BLOCK FLASH MEMORY
SMJS200B - JUNE 1994 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Power Up
and
Stendby
Write
Program-8etup
Command
:;~
X...___. . "
--+I
Automated
Byte/Word
Programming
Write
Read-Array
Command
R..d Stetu.
Raglater Bite
1
14-1.----+1---+1
14- Ic(w)
Vi-./\.
Write Valid
Addraaa
And Date
tau(A)
1+*-tt.(A)
/\
II
!
j
I
j
j
j
j.
\'I...--JI
--~I
~-+~j
taU(W)-.i1+j
j
-+ji+-tt.(W)
I
oJ
I I
II
I.
~j
z
o
1c(E)OP - - - - + I
1
~------------~
000_
DQ7
Date
(byte
=~- HI-Z
DQ15
(Word
wide)
>---- HI-z
j
j
j
j
j
j
Sl
i
d
r£
----<<<{ ;»...r--\...:r
SR
ti
:E
FFh
HI-Z-
I
-zw
j
14-!.-~c-tau(RP)
~1
_)ri4---I~*"j trac(RPHE)/~!
...I.-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....
~....tt.(RP)
____
RP
j
j
j
!..!- tt.(VPP)
i+---+I- tau(VPP)
I
U
Z
c~
1
1
«
Vpp
Figure 9. Write-Cycle Timing (E'-Controlled Write)
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS n261-1443
£E:
o
u.
7-109
TMS28F200BZT, TMS28F200BZB
2097152,BIT BOOT.;BLOCKFLASH MEMORY
SMJS200B -JUNE 1894- REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Power Up
and
Standby
Write
E.....eetup
Command
~; ~
Write E _
Conffrm
Command
Eraee
X. . ___.·.
---.I
14-- tc(W)
Automated
Write
Read-Array
Command
1
~I
14
R d Stat
ea
u..
Regleter Bite
1 teu(A)
I I4*-ltt(A)
I I
~
z~
J_........V
cg
::rJ
s::
DQ7
(byte
DQ15·
(word
wide)
I
1
I
I
tc(W)ERB
11"'-"_...tc(W)ERP --+l~1
!
\jI.r--...;...;....--:i----V
~I
.
tw(W)
teu(D)
.... . - th(D)
I
i
I
tc(W)ERM
DOh
I
I
I
!;
1
I
C. Valid SR
>---- HI-Z ---<({ ~»)
I
14-........
..
1 trac(RPHW)
11+4---+\- teu(RP)
i
i
t-t
th(RP)
J
I
I
1+--...1- teu(VPP)
1
~
I
th(VPP)
1
1
Vpp
Figure 10. Erase-Cycle TIming (W-Controlled Write)
'\
~1ExAs
.
7-110
r£ FFh
c;- HI-Z -
)-~--.....,)-......'----.,....---------,rr--~-------- VIH
RP
~
(5
Z
14
II -.IlUi!~
DQO-
n ;:!.-HI-Z
m
-z
I
I
I
tw(WH)
Vi
v
i
I
I
I
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS28F200BZT, TMS28F200BZB
2097152·BIT BOOT·BLOCK FLASH MEMORY
SMJS200B-JUNE 1994-REVISEDJUNE 1894
PARAMETER MEASUREMENT INFORMATION
Power Up
and
Standby
. AO-A18
WrlteE,....
Conftrm
Command
Writ.
Program-8etup
Command
X.,.,.--
~
14--- Ic(W) --.I
Automat.d
Ern.
"u(A)
III-*- 'ti(A)
:1
¥If'\.--"-11\
"------!--'!,
~ 101- 'ti(W)
,
,,
,'Ic(E)ERB
"
,
I
"
"
Ic(E)ERP --~
'Ic(E)ERM
,
101----
,..
DOh
DQO- P07
::'::1·l(word wid.)
>---- HI-Z~«
1
14-1
.. - ........
1 trec(RPHE)
I
II
HPJ
Vpp
I
,
HI-Z
Wrlta
Reed-Array
Command
1
14-1
.. -___.I-----+-I
"U(W)...II+,
RHdStatuaR.glat.r Blta
11+4-~-"u(RP)
1
Z
o
C. Valid SR
i»> .
!i
r£ FFh
c.r
:::::IE
HI-Z -
I
0u-
t:t.IIJ1(RP)
Zw·
I~---~------------------~~~.
I
I
r---r
0
Z
~
~th(VPP)
I
"u(VPP)
.air
I
."WaI ~
Figure 11. Erase-Cycle TIming (!-ControIJed Write)
~TEXAS
INSTRUMENTS
POSTOFFlCE BOX 1443 • HOUSTON. TEXAS 77251-1443
a:
7·111
TMS28F200BZT, TMS28F200BZB
2097152-BIT BOOT-BLOCK FLASH MEMORY
SMJS200B- JUNE 1994 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
M-M8~~---------M-d-~--~-II-d--__------~~
I
I
....
- - - - - - Ie(R) ---,.----~
..I
I1OIII"---la(A) ---+1"1 ".
I
\~--------~!-------I:
,
,
,
"1"-,
1a(E)
,
.,
O
I
"
,
'I'
I '
I
"I'
~
Z
o
m
I"
---------------+1--,.
-cgz
BYTE
..I
14
telI8(E)
I
DQO-DQ7 - - - HI-Z
DQ8-DQ14 - - - - - HI-Z
I
..I
I
,,
,,
!
1....
.. -+1
..11- feu(EB)
,
I
I
' .
I
I'
I I
telI8(G)
/::
let- lJ1(D)
I
I
,
--+i_+-1! it'--\?)}}-J..(G)
I
I,
I
14-1
.. --;-1 teI(E) --+1"1
,
I
,
z
Ia(G)
:
I"
,
1 \1
,
,
:D
!:i(5
I
I
G--------------~i----\~------~!__________;1~,----~!------
:t-
s::
--+1
..1
I
I
,
--------t-------<
,
,,
I
I
_
DC»-DQ1
Word DQO-DQ7
I
I
I
>-----+-----------
HI-Z -
,
I
14-- tcl18(BL) ~
I
I
Word DQ8-DQ14
I
DQ15/A_1 ----- HI-Z --------------C.~,.,«.,.-;.C~--A--1-ln-pu1--""')-.
HI-Z Word DQ15
FIgure 12.1Wi'E TIming, Changing From Word-Wide to Byte-Wide Mode
-!I
TEXAS
INSTRUMENTS
7-112
POST OFFICE BOX 1443 • HOUSTON, TEXAS n2S1-1443
TMS28F200BZT, TMS28F200BZB
2097152·BIT BOOT·BLOCK FLASH MEMORY
SMJS200B-JUNE 1994-REVISEDJUNE 1995
PARAMETER MEASUREMENT INFORMATION
A
1
1
1
1
14
~I
A
1
1
14
1
1
1
1
1
14
\
DQO-DQ7
~I
1
1
1
1
~I
I
I
-~
tctle(O)
:IE
a:
olL
-w
Z
1
1
1
1
1
o
z
~
cc(
HI-Z_
I
I
~
I
14
~I
tct(G)
I
~I
1
1cI(E)
---~,,~~
HI-Z
DQ1~A~ ~
z
o
II
HI-Z
1
1
DQI-DQ14
tctle(E)
1
1
1
1
1
A_1lnput
--'«i
>HI-Z
\l
»)}-HI-Z-
»)}-HI-Z-
Figure 13. BYTE Timing, Changing From Byte-Wide to Word-Wide Mode
~1ExAs
INSTRUMENTS
POBTOFFICE BOX 1443· HOUSTON, TEXAS 772&1-1443
7-113
TMS28F200BZT, TMS28F200BZB
2097152·BIT BOOT·BLOCK FLASH MEMORY
SMJS200B-JUNE 1994 - REVISED JUNE 1995
~1ExAs
INSTRUMENTS
7-114
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS28F400BZT, TMS28F400BZB
4194304·BIT BOOT·BLOCK FLASH MEMORY
SMJS400B - JUNE 1994 - REVISED JUNE 1996
•
•
•
•
DBJPACKAGE
Organization
- Two 8K-Byte Parameter Blocks
- One 96K-Byte Main Block
- Three 128K-Byte Main Blocks
- One 16K-Byte Protected Boot Block
- Top or Bottom Boot locations
Allinputs/Outputa TTL Compatible
Maximum Access/Mlnlmum Cycle Time
Vee :t: 5%
Vee :t: 10%
'28F400BZ-6-x
60 ns
'28F400BZ-7D-x 70 ns
'28F400BZ-SD-x 80 ns
'28F400BZ-90-x 90 ns
VSS
100000 and 10000 Program/Erase Cycle
Versions
000
Three Temperature Ranges
- Commercial ••• O°C to 70°C
- Extended ••• - 40°C to 85°C
- Automotive ••• - 40°C to 125°C
• Low Power Dissipation (Vee 5.5 V)
. - Active Write •.• 330 mW (Byte Write)
- Active Read ••• 330 mW (Byte Read)
- Active Write .•• 358 mW (Word Write)
- Active Read ••• 330 mW (Word Read)
- Block Erase ••• 165 mW
- Standby ••• 0.55 mW (CMOS-Input
Levels)
- Deep Power-Down Mode ••• 0.0066 mW
(TOP VIEW)
•
•
39
A4
A3
A2.
A1
38
37
36
35
34
33
32
31
30
AO
E
G
OOS
001
009
002
0010
003
0011
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
42
41
40
29
28
27
26
25
24
23
RP
IN
AS
A9
A10
A11
A12
A13
A14
A15
A1S
BYTE
Vss
0015/A_1
007
0014
OOS
z
0013
005
0012
004
o
ti
VCC
:IE
a:
~
z
PIN NOMENCLATURE
AD-A17
BYTE
000-0014
DOl5/A_1
Address Inputs
Byte Enable
Data In/Out
Data InlOut (word-wide mode).
Low-Order Address (byte-wide mode)
DU
Do Not Use
E
Chip Enable
Output Enable
No Internal Connection
Reset/Deep Power Down
5-V Power Supply
12-V Power Supply for Program/Erase
Ground
Write Enable
G
NC
. RP
Vee
vPP
Vss
Vii
description
AS 6
AS
=
Fully Automated On-Chip Erase and
Word/Byte Program Operations
Write Protection for Boot Block
Command State Machine (CSM)
- Erase Suspend/Resume
- Algorithm-Selection Identifier
44
43
NC
A17
A7
•
•
1
2
3
4
5
Vpp
-w
(J
Z
c~
20000h
c
z~
1FFFFh
OOOOOh
>c8 Configuration
,,18 Configuration
Boot Block
18K Add.......
Boot Block
8KAdd.......
Param.ter Block
8KAdd.......
Param.tar Block
4KAdd.......
Pa...meter Block
eKAdd.......
Parameter Block
4KAdd,.....
Main Block
98KAdd.......
Main Block
48KAdd.......
Main Block
128KAdd.......
Main Block
84KAdd.......
MalnBiock
128KAdd.......
Main Block
84KAdd.....n
Main Block
128KAdd.......
Main Block
84KAdd....n.
DQ15/A_1 .. LSB Addran
o
m
z
Add....
Rang.
3FFFFh
3EOOOh
3DFFFh
3DOOOh
3CFFFh
3COOOh
3BFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
OFFFFh
OOOOOh
AD Ie LSB Addrn.
Figure 1. TMS28F400BZT (Top Boot Block) Memory Map
cg
Add.n.
Rang.
:a
7FFFFh
:s:
~
8000Gh
SFFFFh
40000h
(5
3FFFFh
Z
20000h
1FFFFh
08000h
07FFFh
06000h
06FFFh
O4OOOh
03FFFh
OOOOOh
,,8 Configuration
,,16 C.onflguraUon
Main Block
12eKAddrann
Main Block
84KAdd...nn
Main Block
12eKAdd.......
Main Block
84KAdd...nn
Main Block
12eKAddrann
Main Block
84KAdd.....e.
Main Block
98KAdd.......
Main Block
48KAdd...a•••
Parameter Block
eKAdd.......
Parametar Block
4KAddrann
Parameter Block
eKAdd.......
Parameter Block
4KAddrann
Boot Block
Boot Block
eKAddrann
18K Add.......
DQ15/A_1 I. LSB Add .....
Add ••s.
Range
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
OFFFFh
O4OOOh
03FFFh
O3OOOh
02FFFh
02000h
01FFFh
OOOOOh
AD I. LSB Addrn.
Figure 2. TMS28F400BZB (Bottom Boot Block) Memory Map
~1ExAs
7-118
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTO!'I. 11:XAS 77251-1443
TMS28F400BZT, TMS28F400BZB
4194304-BIT BOOT-BLOCK FLASH MEMORY
SMJS400B - JUNE 1894 - REVISED JUNE 1885
boot-block data protection
The 16K-byte boot block Is used to store key system data that is seldom changed in normal operation. To protect
data within this memory sector, the RP terminal can be used to provide a lockout to eliminate accidental erase
or program operations. When RP is operated with normal TTL/CMOS logic levels, the contents of the boot block
cannot be erased or reprogrammed. Changes to the contents of the boot block can be made only when RP is
at VHH (nominally 12 V) during normal write/erase operations.
parameter block
Two parameter blocks of 8K bytes each can be used like a scratch pad to store frequently updated data.
Alternately, the parameter blocks can be used for additional boot- or main-block data. If a parameter block is
used to store additional boot-block data, caution should be exercised because the parameter block does not
have the boot-block data-protection safety feature.
main block
Primary memory on the TMS28F400BZX is located in four main blocks. Three of the blocks have storage
capacity of 128K bytes and the fourth block has storage capacity of 96K bytes.
command atate machine (CSM)
The CSM is the interface between an external microprocessor and the write state machine and &tatus register
on the memory chip. When the WSM has completed a task, the WSMS bit (SB7) is setto a logic high (1 ), allowing
the CSM to respond to the full command set.
z
o
~
::E
status register (SR)
The status register provides a means of determining whether the state of a program/erase operation Is pending
or complete. The status register is read by writing a read-status command to the CSM and reading the resulting
status code on I/O terminals OQO-OQ7. This is valid for operation in either the byte- or word-wide mode. When
the device is operating In the word-wide mode, the high order I/Os (OQ8-0Q15) are setto OOh when performing
a read-status operation.
OD:
After a read-status command has been given, the data appearing on OQO-OQ7 remains as the status register
data until a new command is issued to the CSM. To return the device to other modes of operation, a new
command must be issuect to the CSM.
o
z
c~
Register data is updated on the falling edge of G or E. The latest falling edge of either of these two signals
updates the latch within a given read cycle. Latching data prevents errors from occurring should the register
input ~an.!le during a status-register react To ensure that the status-register output contains updated status
data, E or G must be toggled for each subsequent status read.
The status register provides the internal state of the WSM to the external microprocessor. During periods when
the WSM is active, the status register can be polled to determine the WSM status (WSMS). Table 1 defines the
status register bits and their functions.
~1ExAs
INSTRUMENTS
PO$T OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7-119
u'
z
_
w
c(
TMS28F400BZT, TMS28F400UB
4194304-BIT BOOT·BLOCK-F!,.ASH MEMORY
SMJS400B -JUNE 1884- REVISED JUNE 1986
status register (SR) (continued)
Table 1. Status Register Bit Definitions and Funcijons
STATUS
BIT
SB7
see
»
c
~
z
FUNCTION
Wtlte-state-machlne status
(WSMS)
1-Resdy
O-Busy
~P8mtstatus
1.. Erase suspended
0- Erase In prograss or
complated
When an erese-suspend command Is issued, the WSM halts
execution and Bats the ESS bit high (See .1) Indicating that the
er888 operation has been suspended. The WSMS bit Is also sat
high (S87 - 1) indicating that the erase-suspend operation has
been successfully completed. The ESS bit remains at a high level
"nIIl an erase-rasume command Is Input to the CSM (code DOh).
1.. Block er888 error
0= Block erase good
SBS .. 0 Indicates that a successful block eresure has occurred.
SBS .. 1 indicates that an erase error hes occurred. In this case,
the WSM hes completed the maximum allowed erase pulses
datermlned by the Intemal algorithm, but this was Insufllclent to
completely er888 the device•
Erase status
(ES)
.
-
SB4
Program atatus
(PS)
-z
SB3
Vppstatus
(Vpps)
::D
SB2SBO
R888IV8d
n
1 = Byte/word program error
Byte/word program good
SB4 .. 0 Indicates successful programming hes occurred at the
addressed block location. SB4 .. 1 Indicates that the WSM was
unable to correctly program the addressed block location.
1.. Program abort:
Vpptoolow
0 .. Vppgood
SB3 provides Information on the status of Vpp during
programmlng.IfVpp Istoc Iowalleraprogram orerasecommand
hes bean 1ssu8d, SB31s sat to a 1 Indicating that the programming ,
operation Is aborted. The Vpp status bit is not essured to give
accurate feedbeck between VPPH and VPPL.
q,-
m
cg
I:
!t(5
COMMENTS
If SB7 = 0, the WSM has not completed ail erase or programming
operation. If SB7 - 1 (ready), other polling operations can be
performed. SB7 does not automatically update WSM status atthe
completion of a WSM task. If the WSM status bit shows busy (0),
the user must periodically toggle E or G to determine when the
WSM hes completed an operation (SB7 = 1).
(ESS)
SBS
DATA
These bits should be mesked out when reading the atatus
register.
operation
Device operations are selected by entering standard JEOEC 8-bit command codes with conventional
microprocessor timing IntO an on-chip CSM through I/O terminals OQO-OQ7. When the device is powered up,
internal ~ circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation
requires a command code to be entered into the CSM. Table 2 lists the CSM codes for all modes of operation.
z
The on-chip status register allows the progress of various operations to be monitored. The status register is
interrogated by entering a read-status register command into the CSM (cycle 1) and reading the register data
on I/O terminals OOO-OQ7 (cycle 2). Status-register bits SBO through SB7 correspond to OQO through OQ7.
~1ExAs
INSTRUMENTS
7-120
POST OFFICE BOX 1443 • HOUlTON. TEXAS 77251-1443
TMS28F400BZT, TMS28F400BZB
4194304·BIT BOOT·BLOCK FLASH MEMORY
SMJS400B - JUNE 1994 - REVISED JUNE 1995
operation (continued)
Table 2. Command State Machine Code. for Device Mode Selection
COMMAND
CODE ON
DOG-DQ7t
DEVICE MODE
Invalid/ Reserved
Alternate Program Setup
20h
Block-Erase Setup
40h
Program Setup
SOh
Clear Status Register
70h
Read Status Register
90h
Algorithm Selection
SOh
Erase Suspend
DOh
Erase Resume/BIock-Erase Confirm
Read Array
FFh
t OOG Ie the least significant bit. OQ8-OO15 are any valid 2-state
leval.
DOh
lOh
z
command definition
Once a spec/fic command code has been entered, the WSM executes an internal algorithm generating the
necessary timing signals to program, erase, and verify data. See Table 3 for the CSM command definitions and
data for each of the bus cycles.
Following the read-a1gorithm-selection-code command, two read cycles are required to access the
manufacturer-equivalent code and the device-equivalent code as shown in Table 4 and Table 5.
, Table 3. Command Definitions
FIRST BUS CYCLE
BUS
CYCLES
REQUIRED
OPERATION
Read Array
1
Write
Read Algorithm-Selection Code
3
Write
Read Status Register
2
Write
Clear StatUI Register
1
Write
COMMAND
OPERATION
X
FFh
X
X
SOh
70h
X
SOh
ADDRESS
ADDRESS
DATA
IN/OUT
Read
X
Data Out
Read
AO
MJD
Read
X
SRB
40h or lOh
Write
PA
PO
20h
Write
BEA
DOh
Write
X
DOh
Read Operatlona
Program Mode
Program Setup/Program
(byte lword)
2
Write
PA
Erase Operations
Block·Erase Setup!
Block-Erase Confirm
2
Write
BEA
Erase Suspend!
2
Write
BOh
X
Erase Resume
Legend:
BEA
BIock-erase address. Any address selected within a block selects that block for erase.
M/D Manufacturer-equlvalent/devlce-equlvalent code
PA
Address to be programmed
PO
Data to be programmed at PA
SRB
Status-register data byte that can be found on OQO-OO7
~1ExAs
INSlRUMENTS
POST OFFICE lOX 14<13 • HOUS'ION. TEXAS 77251-14<13
:E
a:
oLL
-ow
Z
SECOND BUS CYCLE
CSM
INPUT
o
~
7-121
z
c~
«
TMS28F400BZT, TMS28F400BZB
4194304-BIT BOOT-BLOCK FLASH ,MEMORY
sMJS400B -JUNE 1994 - REVISED JUNE '1995
byte-wide or word-wide mode .electlon
The memory array is dMded Into two parts: an upper half byte that outputs data through I/0s OQ8-0Q15 and
a lower half byte that outputs data through OQO"':'007. Device operation in either byte-wide or word-wide mode
is user-selectable and is determined by the logic state of BYTE. When BYTE is at a logic high level, the device
is in the word-wide mode and data is written to or read from I/Os OQO-OQ15. When BYTE is at a logic low, the
device is in the byte-wide mode and data is written to or read from I/0s OQO-OQ7.ln the byte-wide mode, I/Os
OQ8-0Q14 are placed in the high-impedance state andbQ15/A_1 becomes the low-order address terminal
and selects either the upper or lower half of the array. Array data from the upper half (OQ8-0Q15) and the lower
half (OQO-OQ7) are multiplexed and appear on OQQ..;..OQ7. Table 4 and Table 5 summarize operations for
word-wide mode and byte-wide mode.
Table 4. Operation Mode. for Word-Wide Mode (BYTE
E
Q
RP
W
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
MOOE
Read
»
c
;;
z
o
m
z
."
o
-
:rJ
:i:
~
-oz
Algorithm-selection mode
Output disable
Standby
VIL
VIL
VIH
VIH
VIL
VIH
VIH
VIH
VIH
VIH
X
X
X
Reset/deep power down
Write (_ Note 1)
VIL
X
X
VIH
VIL
VIHor
VHH
M
AO
vPP
X
X
VID
VIL
X
X
ViH
X
X
X
X
X
X
X
X
X
X
VID
X
VIL
OQO-OQ1&
Data out
Manufacturer-equivalent code 0089h
Device-equivalent code 4470h
(top boot block)
Device-equivalent code 4471 h
(bottom boot block)
High impedance
High impedance
High impedance
VPPLor Data in
VpPH
X
Table 5. Operation Modes for Byte-Wide Mode (BYTE
MOOE
E
Read lower byte
VIL
Read upper byte
VIL
VIL
RP
W
M
AO
Vpp
VIL
VIL
VIH
VIH
VIH
X
X
X
VIH
X
X
VIL
VIH
VIH
VID
VIL
G
Algorithm-selectlon
mode
=VIti>
=Vld
OQ1&/A_1
OQ8-0Q14
Data out
X
VIL
VIH
Hi-Z
Hi-Z
Data out
X
X
Hi-Z
Manufacturer-eql!ivalent
code89h
OQO-OQ7
Device-equivalent code
70h (top boot block)
VIL
VIL
VIH
VIH
VID
VIH
X
X
Hi-Z
Output disable
VIL
VIH
VIH
VIH
X
VIH
X
X
X
X
X
X
X
High impedance
VIH
X
X
Hi-Z
Standby
Hi-Z
High impedance
X
X
VIL
X
X
X
X
X
Hi-Z
High impedance
Reset/deep power
down
Device-equivalent code
71 h (bottom boot block)
VPPL
Hi-Z
or
X
Data in
VPPH
NOTE 1: When writing commands to t!le '28F400BZX, Vpp must be VPPH for block-erase or program commands to be executed and RP must
be held at VHH for the entire boot-block program or erase operation.
Write (see Note 1)
VIL
VIH
VIHor
VHH
VIL
X
X
~TEXAS
INSTRUMENTS'
7-122
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251·,443
TMS28F400BZT, TMS28F400BZB
4194304-BIT BOOT-BLOCK FLASH MEMORY
SMJS400B- JUNE 1994 - REVISED JUNE 1995
command state machine (eSM) operations
The CSM decodes instructions for read array, read algorithm-selection code, read status register, clear status
register, program, erase, erase suspend, and erase resume. The 8-bit command code is input to the device on
DQO-DQ7 (see Table 2 for CSM codes). During a program or erase cycle, the CSM informs the WSM that a
program or erase cycle has been requested. During a program cycle, the WSM controls the program sequences
and the CSM responds only to status reads.
During an erase cycle, the CSM responds to status reads and the erase suspend command. When the WSM
has completed its task, the WSM status bit (S87) is set to a logic high and the CSM responds to the full command.
set. The CSM stays in the current command state until the microprocessor issues another command.
The WSM succeasfully initiates an erase or program operation only when Vpp is within its correct voltage range
(VpPH). For data protection, it is recommended that RP be held at a logic low during a CPU reset.
read operations
There are three read operations available: read array, read algorithm-selection code, and read status register.
readaTray
The array is read by entering the command code FFh on DQO-DQ7. Control terminals E and G must be at a
logic low (VIL> and Wand RP must be at a logic high (VIH) to read data from the array. Data is available on
DQO-DQ15 (word-wide mode) or DQO-DQ7 (byte-wide mode). Any valid address within any of the blocks
selects that block and allows data to be read from the block.
z
o
!i::E
read algornhm..e/ectlon code
Algorithm-selection codes are read by entering command code 90h on DQO-DQ7. Two bus cycles are required
for this operation. The first bus cycle is used to ente.!. the command code and the second bus'£ycle is used to
read the device-equivalent code. Control terminals E and G must be at a logic low (VIL> and W and RP must LL
be at a logic high (VIH). Two identifier bytes are accessed by toggling AO. The manufacturer-equivalent code Z
is obtained on DQO-DQ7 with AO at a logic low (VIL>. The device-equivalent code is obtained when AO is set to a logic high (VIH). Alternately, the manufacturer- and device-equivalent codes can be read by applying VIO
(nominally 12 V) to A9 and selecting the desired code by toggling AO high or low. All other addresses are don't (J
care (see Table 3, Table 4, and Table 5).
Z
a:
o
w
read ststus regls,.r
The status register is read by entering the command code 70h on DQO-DQ7. Control terminals E and G must
be at a logic low (VIL> and W and RP must be ata logic high (VIH). Two bus cycles are required for this operation:
one to enter the command code and a second to read the status register. In a given read cycle, status register
contents are updated on the falling edge of E or G, whichever occurs last within the cycle.
c/.ar status register
The internal circuitry can set only the Vpp status bit (S83), the program status bit (S84) and the erase status
bit (S85) bits of the status register. The clear status register command (50h) allows the external microprocessor
to clear these status bits and synchronize to internal operations. When the status bits are cleared, the device
returns to the read array mode.
boot-block programming/erasing
Should changes to the boot block be required, RP must be set to VHH (12V) and Vpptothe programming voltage
level (VpPH). If an attempt is made to write, erase or erase-suspend the boot block without RP at VHH, an error
signal is generated on SB4 (program-status bit) or S85 (erase-status bit).
A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)
during the second cycle. After writing FFh or FFFFh during the second cycle, the CSM responds only to status
reads. When the WSM status bit (S87) is set to a logic high, signifying the nonprogram operation is terminated,
all commands to the CSM become valid again.
.
~TEXAS
INSTRUMENTS
POST OFFICE BOX , _ • HOUSTON, TEXAS 17251-1_
7-123
c~
--~VPP
Range Error
COMMENTS
Standby
CheckSB3
1 • Detect Vpp low
(S88 Note B)
Standby
CheckSB4
1
Word program
failed
(S88 NoteC)
=
NOTES: A. Full statua-reglster check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program I erase operations.
C. 88418 cleared only by the ciear-status-reg18ter command. but It does not prevent additional program operation attempts.
Rgure 4. Automated Word-Programming Flowchart
~1ExAs
INSTRUMENTS
POITOFFICEBOX 1413· HOUlTON. 'IEXAS 77251-1413
o
z
c~
c
~
RNd
Status register data.
Toggle G or E to update
status register
StIIndby
CheekSB7
1 .. Ready. 0 .. Busy
Repeat for subsequent blocks.
Write FFh after the last block-eraae operation to ra88lthe
device to raad array mode •.
z
n
m
z
-
FULL STATUS-REGISTER CHECK FLOW
cg
:D
r:
BUS
OPERATION
CheckSB3
1 .. Detect Vpp /ow
(aeeNote B)
Command Sequenc.
Standby
Check SB4 and SB5
1 .. Block-erase
command error
Block Era. . Failed
Standby
CheckSB5
1 .. Block erase tallad
(see Note C)
~
Error
Z
COMMENTS
Standby
Vpp Rang. Error
(5
COMMAND
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program I erase operations.
C. SB51s cleared only by the cIear-atatus-reglster command In caSEia where multiple blocks are erased before full status is checked.
Figure 5. Automated Block-Erase Flowchart
~1ExAs
7-128
INSTRUMENTS
POST OFFICE eox 1443 • HOUlTON. 'IEXA8 77251-1443
TMS28F400BZT, TMS28F400BZB
4194304-BIT BOOT-BLOCK FLASH MEMORY
SMJS4008 - JUNE 1894 - REVISED JUNE 1896
BUS
OPERATION
Write
COMMAND
Erase
suspend
COMMENTS
Data =BOh
Read
Status register data.
Toggle G or E to update
status register.
StlIndby
CheckSB7
1 .. Ready
StlIndby
CheckSB6
1 .. Suspended
Z
WrIte
Read
memory
o
-ti
Data =FFh
::E
Read data from block
other than that being
erased.
Read
No
Write
Erase
Data =DOh
a:
oLl-
-Zw
(J
resume
Z
Era.. Continued
~
~
S.. NoteA
NOTE A: Refer to automated block-erase flowchart for complete eresure procedure.
Figure 6. Erase-8uspend/Resume Flowchart
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7·129
TMS28F400BZT, TMS28F400BZB
4194304-BIT BOOT·BLOCK FLASH MEMORY
SMJS400B - JUNE 1884 - REVISED JUNE 1895
absolute maximum ratings over operating tr..-alr temperature range (unle.. otherwise noted)t
Supply voltage range, Vee (see Note 2) .•.••..................•..•......••...•.•.•.• - 0.6 V to 7 V
Supply voltage range, Vpp (see Note 2) .•..• • . . • • . . • . . . . • . . . . . • . . . • . . . • . • . . • • . . . . •. - 0.6 V to 14 V
Input voltage range: All inputs except A9, J:lI5 ...•........•......•......•••••••• - 0.6 V to Vee + 1 V
lw, A9 (see Note) ........................................... - 0.6 V to 13.5 V
Output voltage range (see Note 4) ............................................ - 0.6 V to Vee + 1 V
Operating free-alr temperature range, TA' during read/erase/program: L suffix •••••••.••••• O·C to 70·C
E suffix .......... - 40·C to 85·C
Q SuffIX ........ - 4Q·C to 125·C
Storage temperature range, Tstg ........••.•..•.•...•..•..•.•.•.....•...•••.••.••. - 65·C to 150·C
t S u - beyond those listed under"abaolute maximum ratings" may cause perrnanent damage to Ihe device. Theae are slrees ratings only, and
functional operation of the device at Ih888 or any other conditlona beyond those Indicated under "recommended operating conditions" is not
impDed. Exposure to abaoIute-maximum-rated conditlon8 for extended periods may affect davIce reliability.
NOTES: 2. All voltage values at'e with respect to VSS.
3. The voltage on any input can undershoot to - 2 V for periods less than 20 os.
4. The voltage on any output can overshoot to 7 V for periods lees than 20 os.
l>
c
~
z
o
m
z
~
::a
s:
~
recommended operating conditions
Vee
Supply voltage
Vpp
Supply voltage
High-level de input voltage
VIL
Low-level de Input voltage
NOM
MAX
5
5.25
4.5
5
5.5
8.5
V
12
12.6
V
11.4
TTL
2
UNIT
V
VCC+0.5
V
TTL
Vee- 0,5
-0.5
VCC + 0.5
0.8
V
V
CMOS
VSS-0.2
VSS+0.2
V
CMOS
VLKO Vee Iock-out voltage from wrlte/erase
VHH RP unlock voltage
2
11.5
word/byt..wrlte and block-erase performance, TA = 2S·C, Vpp
PARAMETER
MIN
4.75
0
Ourlng reed only (VPPL)
During write/erase/erase suspend (VPPH)
VIH
(5
Z
During wrlte/readlerase/ereae suspend
'28F400BZx-8
All others
V
12
13
V
= 12 V (see Note 5)
'28F400BZx-8
TYP MAX
'28F400BZx-70
MIN
TYP MAX
'28F400BZx-80
MIN
TYP MAX
'28F4OOBZx·90
MIN
TYP MAX
UNIT
MIN
Main-bIoc~ ereae time
2.2
2.2
2.2
2.2
s
Main-block byte-program
time
3.2
3.2
3.2
3.2
s
Main-block word-program
time
1.6
1.6
1.6
1.6
s
0.32
0.32
0.32
s
Paramater/boot-block
.0.32
erase time
NOTE 5: Excludes syatem-level overhead
~1ExAs
7-130
.
INSlRUMENTS
POST OFFICE BOX 144a • HOUSTON. TEXAS 77261-144a
TMS28F400BZT, TMS28F400BZB
4194304-BIT BOOT-BLOCK FLASH MEMORY
SMJS400B-JUNE 1994-REVlSEDJUNE 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature using test conditions given In Table 6 (unless otherwise noted)
PARAMETER
MIN
TEST CONDmONS
VOH
High-level output voltage
VCC=4.SV,
10H =-2.5 rnA
VOL
Low-level output voltage
VCC- 4.SV,
IOLaS.8mA
VIO
AS selection code voltage
II
110
Input current (leekage), except 10r A9 when A9 "' VIO
AS selection code current
IRP
RP boot-block unlock current
11.S
VCC=S.SV,
MAX
2.4
VI'" OVto S.SV
AS=VIO
UNIT
V
0.4S
V
13
V
:1:1
j.iA
500
j.iA
500
j.iA
:1:10
j.iA
10
j.iA
S
j.iA
200
j.iA
10
Output current (leakage)
IpPS
Vpp standby current (standby)
VPP"VCC
IpPL
Vpp supply current (reset/deep power-down mode)
RP =VSS:l:0.2V
IpP1
Vpp supply current (read)
Vpp>VCC
IpP2
Vpp supply current (active byte write)
VPP"VPPH,
Programming in progress
30
mA
IPP3
Vpp supply current (active word write)
VPP=VpPH,
Programming In progress
40
mA
IpP4
VPP supply current (block erese)
VpP=VpPH,
Block erase in progress
30
mA
IpPS
VPP supply current (erase suspend)
VpP"VpPH,
Block erase suspended
200
j.iA
Ices
Vcc supply current
(standby)
ICCL
Vcc supply current (reset/deep powerdown mode)
ICC1
VCC supply current
(active read)
VCC" S,SV,
VO"OV toVCC
TIL-input level
VCC .. S•SV,
E.RP.VIH
1.S
rnA
CMOS-input level
VCC=S.SV,
E.RP"VIH
100
j.iA
1.2
j.iA
8
j.iA
O·cto 70·C
- 4000 to 85·C
RP .VSS:l:0.2V
- 4O·C to 125·C
TIL-Input level
VCC = S.SV,
f= 10 MHz,
E=VIL.o
10UT=OmA
80
mA
CMOS-Input level
VCC=S.Sv,
f=10MHz,
E - VSS :I: 0.2 V,
'OUT=OmA
55
mA
IC02
VCC supply current (active byte write) (see Notes 10 and 11)
VCC=S.SV,
Programming In progress
60
mA
1CC3
Vce supply current (active word write) (see Notea10 and 11)
VCC·S.5V,
Programming In progress
85
mA
1CC4
Vcc supply current (block erase) (see Notes 10 and 11)
VCC .. 5.5V,
Block erase In progress
30
mA
Ices
VCC supply current (erase suspend) (see Notes 10 and 11)
Vcc =5.5 V,
E=VIH,
Block erase suspended
10
mA
NOTES: 6. Not 100% tested; charactarizatlon dsta available
7. All current velues are RMS unless otherwise noted.
Table 6. AC Test Conditions
SPEED DESIGNATOR
IOL
(mAl
IOH
vzt
(mA)
(V)
VOL
(V)
-8
5.8
-2.5
1.5
1.5
-70, -50, -90
5.8
-2.S
1.5
0.8
t Vz 18 the measured valus used to detect hagh Impedance.
VOH
(V)
VIL
(V)
VIH
(V)
1.5
0
2.0
0.45
CLOAD
If
tr
TEMPERATURE
(PF)
(ne)
(ns)
3.0
30
<10
<10
0·Cto70·C
2.4
100
<10
<10
- 4O·C to 12S·C
-!!11ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
7-131
z
o
fi
:E
a:
~
-wz
o
z
c~
ALT.
SYMBOL
laCBH)
tAVQV
teLQV
0
0
0
n8
ns
n8
n8
occul'lfirst
Acoees time from iWfE
awItohlng high
~1ExAs
7-132 .
0
n8
INSTlWMENTS
PO&T ~ lOX 1441 • HOUSTON, TEXAS 772111-1441
TMS28F400BZT, TMS28F400BZB
4194304-BIT BOOT-BLOCK FLASH MEMORY
SMJS400B - JUNE 1994 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
wrHe/eraae operations - W-controlled write.
ALT.
SYMBOL
'Z8F400BZx·8
MIN
'Z8F400BZx· 70
MAX
MIN
MAX
'Z8F400BZX·80
MIN
MAX
'UF400BZX-90
MIN
MAX
UNIT
tc/Wl
Cycle time, write
lAVAV
80
70
80
90
ns
tc(W)OP
Cycle time, duration of
programming operation
IWHaV1
8
8
8
7
I1B
tc(W)ERB
Cycle time, erase
operation (boot block)
twHav2
0.3
0.3
0.3
0.4
s
tc(W)ERP
Cycle time, erase
operation (parameter
block)
twHav3
0.3
0.3
0.3
0.4
s
tc(W)ERM
Cycle time, erase
operation (main block)
twHav4
0.8
0.8
0.8
0.7
s
1d(RPR)
Delay time, boot-block
relock
tpHBR
If,/Al
Hold time. AO-A17
twHAX
If,lDl
th{E)
Hold time, oa valid
twHox
0
0
Hold time, E
twHEH
10
10
If,(VPP)
Hold time, VPP from valid
status register bit
taWL
0
0
If,(RP)
Hold time. RP at VHH
from valid status register
bit
taVPH
0
0
100
10
100
10
100
100
10
ns
ns
0
0
ns
10
10
ns
0
0
ns
:E
0
0
ns
olL
tau/A}
Setup time, AO-A17
tAVWH
50
50
50
50
ns
tau/Ol
Setup time, DQ
tOVWH
50
50
50
50
ns
tau(E)
Setup time, E before write
operation
teLWL
0
0
0
0
ns
tau(RP)
Setup time, RP at VHH to
Wgolnghigh
tpHHWH
100
100
100
100
ns
tau(VPP)
Setup time, VPP to W
going high
1VPwH
100
100
100
100
ns
lwlWI
Pulse duration, W low
twLWH
50
50
50
50
ns
lw/WHl
Pulse duration. W high
twLWL
10
20
30
30
ns
trac(RPHW)
to W going low
tpHWL
215
215
215
215
ns
R~ry time,
RP high
~1ExAs
INSTRUMENTS
POSTOFFlCEBOX1443· HOUSroN. TEXAS 77251-1443
z
o
~
10
7·133
a:
-o
Z
w
z
c~
~
TMS28F400BZT, TMS28F400BZB
4194304-BIT BOOT..BLOCK FLASH MEMORY
SMJS400B- JUNE 1894 - REVISED JUNE 1885
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (continued)
wrlte/era.e operation. - E-controlled wrHe.
ALT.
SYMBOL
tclW)
Cycle time, write using ~
'28F4OOBZX·8
tAVAV
MIN
80
,'28F400BZX.70
MAX
MIN
MAX
'28F400BZIC·80
70
MIN
80
MAX
'28F4OOBZX·90
MIN
MAX
UNIT
90
ns
Cycle time, duration of
tc(E)OP
programming operation
teHQV1
8
8
8
7
Cycle time, erase opera·
lion using ~ (boot block)
'"
tc(E)ERB
teHQV2
0.3
0.3
0.3
0.4
s
uslng~
Cycle time, erase
tc(E)ERP
operation using ~
(parameter block)
teHQV3
0.3
0.3
0.3
0.4
s
tc(E)ERM
Cycle time, 8r1l8 opera·
tlon using ~ (main block)
teHQV4
0.8
0.8
0.8
0.7
s
!d(RPR)
Delay time, boot·block
ralock
tpHBR
100
100
100
100
ns
ttl{A)
Hold time, AO-A17
tEHAX
10
10
10
10
ns
ttllD)
Hold time, OQ valid
teHDX
0
0
0
0
ns
ttllW)
HoIdtlme,W
teHWH
10
10
10
10
ns
ttl (VPP)
Hold time, Vpp from valid
atatus-reglster bit
fOWL
0
0
0
0
ns
ttl(RP)
Hold time, fiji at VHH from
valid status-raglster bit
fOVPH
0
0
0
0
ns
tauCAl
taulD)
tau(W)
Setup time, AO-A17
tAVEH
50
50
50
50
ns
Setup time, DO valid
Setup time, iii befora E
toVEH
50
twLEL
0
50
0
50
0
50
0
ns
ns
tau(RP)
Setup time, RP at VHH to E
going high
tpHHEH
100
100
100
100
ns
tsu(VPP)
Setup time, Vpp to ~ going
high
tvPEH
100
100
100
100
ns
u8lng~
tELEH
50
50
50
50
ns
Pulse duration, ~ high,
write using E
teHEL.
10
20
30
30
ns
tpHEL.
215
215
215
215
ns
Iw(E)
Iw(EH)
Pulse duration, ~ low, write
Recovery time, RP high to
trac(RPHE) ~golnglow
~1ExAs
7-134
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-\443
TMS28F400BZT, TMS28F400BZB
4194304-BIT BOOT-BLOCK FLASH MEMORY
SMJS4008 -JUNE 1994 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~14------~~------~~1
---JXIP--Acl-d.-... -Va-I-Id--""'X..-----
AO-A17 _ _ _ _ _ _
I+-- ta(A)
~I
E----------------~\
11I.-
,
~ta~~
II
III---~./T.I.-
G------------------~I\
1
1
wJ
I
11'---
___
14
~I ta(G)
I
I I !
I H- I
14 ~II
':00":=:::~ ----- -----«<(({
teI(G)
teI(E)
HI-Z
I
Vee
Jl"lf----I
teI(RP)
-----.!J
"'(0)
14
telI8(E) -+j
I
I
tell8(G)
~I
I
-+l
I
I
i \..
1
i»>}
z
o
HI-Z -
fi
\..
:E
-0:
o
u.
z
-w
Figure 7. Read-Cycle nmlng
o
z
c~
---- HI.z
1
1
I
',
1 "11II--tc(W)OP---"~'
I
V.,.-----,i-:
-----..v
-lo'IIIf----+l~'
Vi J,....~v
v
11
14--~ tau(RP)
RPj
oz
HI.z-
I
I
.
.\
,
I
,
i+--+r-1I1(VPp)
~taU(VPP)
,
1
1
Vpp
Figure 8. Write-Cycle T1mlng (W-Controlled Write)
~ThxAs
7·136
r£ FFh
cr
:!4-+t-II1(RP)
I
~
C. valid SR
--<({ i»)
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lEXAS 77251-1443
,
TMS28F400BZT, TMS28F400BZB
4194304-BIT BOOT-BLOCK FLASH MEMORY
SMJS4OOB- JUNE 11194 - REVISED JUNE 1886
PARAMETER MEASUREMENT INFORMATION
Power Up
Write
Write ¥alld
Automated
and
Standby
Program-SltUp
Command
Add.....
And Data
Byte/Word
Programming
:;~
X",____
I+-- tc(W) ~
14
Write
Raad Statu..
Reg"'" Blta
Raad-Array
Command
I
.,
I ....(A)
, ~lh(A)
III
, i
fiJ
,
I
I
I
,
I
I
I
I
,
I
..I~-II,,~------------~
I
to(E)OP - - - - . .
DQO_
DQ7
Data
(byte
::O-!.wiele)
I
I
i
I
I
I
I
fi
C. ~IIdSR r£ Ffh
:E
a:
~
z
>---- HloZ ----<<<{ .~ HloZ-
HI.z
DQ11
(word
z
o
____
"14-~r-""(RP)
I
I
-
p~:r~_~_~:_~~~,,~_I__~I__________________~~~~lh_(R_P)__________
I
~""(VPP)
I
~
I
I
w
U
Z
~
lh(vpp)
C
ct
vpp
Figure I. Wrtte-Cycle nmlng (I.Controlled Write)
~1EXAS
INSlRUMENTS.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
7·137
. TMS28F400BZT, TMS28F400BZB
4194304-BI1 BOOT-BLOCK FLASH MEMORY
SMJS400B-JUNE 11184 - REVISED JUNE 1l1li5
PARAMETER MEASUREMENT INFORMATION
POWII' Up
and
Stendby
Wrtte
:; ~
Write ErneConfirm
Command
Erue-Setup
Command
X.,.~
I+- to(W) --+I
14
Automated
E.....
Regleter Bite
__. .
-I
Read Statu..
1
1 .u(A)
1 I4*- 1ti(A)
1 I
v
l>
~
~
(')
m
--nz
o:a
a:
~
(5
z
Vpp
Figure 10. Erase-Cycle Timing (W-Controlled Write)
.~1ExAs
INSTRUMENTS
7-138
POST OFFICE BOX 14<13 • HOUSTON. TEXAS 77251-14<13
Write
Read-Array
Command
TMS28F400BZT, TMS28F400BZB
4194304-BIT BOOT-BLOCK FLASH MEMORY
SMJS400B - JUNE 1994 - REVISED JUNE 1885
PARAMETER MEASUREMENT INFORMATION
P_Up
WrIte
lnet
Progl'lm-Setup
WrlteErIMConfIrm
Stlndby
COmmlnd
Commlnd
:;:D<
-..t
teu(w,....k-
I
I
I
I
I
=-=~
-
I
I I4*- th(A)
III
'---+I...I!I
~l.-th(W)
I I
I
I I
I
I
I
I I
I
I
I
I k-14
~I
I I
I
I
I
HI.z
tc(E)ERB
tc(E)ERP --~
tc(E)ERM
>---- HI.z
I
!;
1411
DJ'
..,
II
---«<
teu(RP)
I
I
~ teu(VPP)
YPP
Z
0
DOh
---i~....1 tr.c(RPHE) ~_*-
14-14
I
Writs
RHd-ArI'lY
Commend
1+14--I~*'I-+-1 teu(A)
wJ\,
A
. ~ ---""'I
(word wide)
RHdStltu..
Reglaler Bits
X.,....__....
14-- tc(W)
DQO-DQ7
Automlted
E.....
C. Vllid SR
i)})
r£ FFh
\.:r HI-Z -
Ei
:IE
a:
I
0u-
;s~~
~
~ th(VPP)
0
Z
I
I
~
~~
Flgur. 11. Er....Cycl. Timing (E-Controll.d Write)
~.1ExAs
INSTRUMENTS
POSTOFFlCEBOX1....,· HClUS"roN. TEXA8772S1-1....,
7-139
TMS28F400BZT, TMS28F400BZ8
4194304-BIT BOOT·BLOCKFLASH MEMORY
SMJS400B- JUNE 1894 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
AD-A17
~1I-_ _ _ _ _Ad_d_""'_Va_IIcI_ _ _ _ _ _...I~
I
14-1~------ leeR)
1
-------.!
..I
14-14--~ ta(A) ---~
.. I
I
\ II & - - - - - + -III- - - - - ' .'"II
4 - - ta(E) --~
14-1
..I
I
1
I
!
l>
c
z~
o
m
z
I
I
I
I
I
1
I
4
14-1
."
o:lJ
s::
I
I
I
I
I
I
"II
14
~
14
ta(G)
HI-Z
:
I
14
..I
I
I
I
~
""'''1
I
1
I
I
1
1
tt.(D)
'-u(EB)
Byte DQO-DQ7
Word DQO-DQ7
I
I
I
----t-----(
I
I
>---+-----
HI-Z -
I
I
tella(BL)
--+j
I
I
Word DQ8-DQ14
I
------~~,.,«.,..-;~CIl'"'-A---11-np-ut~>-- HI-Z WordDQ15
Figure 12. BYTE Timing, Changing From Word-Wide to Byte-Wide Mode
~1ExAs
INSTRUMENTS
7-140
tells(G)
-."11-I I
.. I
-+--1--+-1r---cQIl'7'l~.....-;(t~ ~ H~I1 Ii
I
I
1
I
I
I+--
DQ15/A_1 ----
tells(E)
I::
1
I
14-14-"1"1 teI(E)~
I
I
DQ8-DQ14 - - - - HI-Z
I
I
I
I
1 4 . - -...lIl-1 teI(G)
(5
Z
..I
"'--;--+-1---
:
II
I I
1
DQO-DQ7 - - HI-Z
I
!
\
1 \1
-
I
I
I
I
POST OFFICE BOX 1443 • HOUSTON. TEXAS 772111-1443
TMS28F400BZT, TMS28F400BZB
4194304-BIT BOOT·BLOCK FLASH MEMORY
SMJS400B-JUNE 1994-REVlSEDJUNE 1995
PARAMETER MEASUREMENT INFORMATION
AO-A17~
1
14
1
14
~I
1e(A)
1
1
1
1
1
1
\
I
I
I
I
1
1
1
1
1
14
1
1
1
1
iiYi'E
DQO-DQ7
1
1
I1
A
1
1
1
1
1
1
1
1
Ieu(EB)
1
1
14
~I
II1II
1
~I Ie(G)
1
1
1
1
1
14
\
1
1
1
1
~I
1
1
Byt8 DQO-DQ7
I
I
II
Z
-ti
0
tclI8(G)
:&
0
a:
U.
th(D)
Z
1
1
1
1
1
W
(.)
Z
~
HI-Z_
14
I
~I
Q
c(
ld(G)
I
~I
tcI(E)
-~-.~~
HJ.Z
DQ15/A_1~
tclI8(E)
1
1
1
1
1
If
I
I
1
14
~I
HJ.Z
1
1
1
1
14
1
DQI-DQ14
1
1
1
1
14
1
1
1
1
1
1
1
1
~I
If
~I
j+--1e(E)
1
1
1
1
1
1
G
~I
te(R)
\
E
~
1
AcId.... valid
-_.«))}-HI.Z-
»>}-HI.Z-
Figure 13. BYTE TIming, Changing From Byte-Wide to Word-Wide Mode
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
7·141
TMS28F400BZT, TMS28F400BZB
4194304-BI1 BOOT-BLOCK FLASH MEMORY
SMJS4OOB-JUNE 1814- REVISED JUNE 1885
:illExAs . .
7-142
INSTRUMENTS
POSTOFFtCE BOX 1448· HOUlTON. 'T&XA8 77251-1448
TMS27C256 262144-BIT W ERASABLE PROGRAMMABLE
TMS27PC256 262144-BIT PROGRAMMABLE
READ-ONLY MEMORY
- SEPTEMBER 1884 - REVISED JUNE 1886
•
•
•
•
•
•
•
This Data Sheet Is Applicable to All
TMS27C256s and TMS27PC256s Symbolized
With Code "B" as Described on Page 157.
Organization ••• 32K x 8
Single 5N Power Supply
Pin Compatible With existing 256K MOS
ROMs, PROM., and EPROM.
All Inputs IOutputs Fully lTL Compatible
Max Acee../Mln Cycle Time
Vee:t10%
'27C/PC256-10
1OOn.
'27C/PC256-12
120n.
150ns
'27C/PC256-15
170n.
'27C/PC256-17
200ns
'27C/PC256-20
250n.
'27C/PC256-25
Power Saving CMOS Technology
Very Hlgh-Spe.Jf SNAPI Pulse
Programming ,
• 3-State Output Buffers
• 400-mV Minimum DC Nol.. Immunity With
Standard TTL Loads
• Latchup Immunity of 250 mA on All Input
and Output Un..
• Low Power Dissipation (Vee. 5.5 V)
- Active ••• 165 mW Worst Ca..
- Standby ••• 1.4 mW Worst Case
(CMOS Input Levels)
• PEP4 VerSion Available With 168-Hour
Burn-In, and ChOices of Operating
Temparature Ranges
J AND N PACKAGES
(TOP VIEW)
Vee
Vpp
A12
A7
A14
A13
3
AS
AS
AS
AS
4
A4
A3
A11
~
A10
A2
A1
9
E
11
007
006
AO
DQO
DOS
001
002
GND
16
15
004
003
FMPACKAGE
(TOP VIEW)
N
0..:::1 0-.(')
~<~z$>«
o
AS
AS
A11
NC
~
A10
AO
E
11
007
006
NC
DQO
• 256K EPROM Available With MIL-STD-883C
Class B High Reliability Processing
(SMJ27C256)
1415 16 171619 20
..-NO:::l(')-.1/)
agzzgaa
o
~
00
description
The TMS27C256 series are 262144-bit, ultraviolet-light erasable, electrically programmable
read-only memories.
The TMS27PC256 series are 262144-blt, onetime electrically programmable read-only memories.
PIN NOMENCLATURE
AO-A14
000-DQ7
'E
CI
GND
NC
NU
Vee
Vpp
~1ExAs
INSTRUMENI'S
POST OFFICE BOX 1443 • HOUSTON. 'IEXA8 77281-1443
Address Inputs
Inputs (programming) IOutputs
Chip Enabie/Powerdown
Output Enable
Ground
No Intamal Connection
Make No External Connection
5-V Power Supply
13-V Power Supply
Copyright C 1885, Texas Insirumenl8ll1C01p01'111ed
7-143
TMS27C256 2621~BIT UV ERASABLE PROGRAMMABLE
TMS27PC256 2621~BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS25IIG-SEPTEMBER 1884- REVISED JUNE 1995
description (continued)
These devices are fabricated using power-saving CMOS technology for high speed and simple interface With
MOS and bipolar circuitS. All inputs ~nciuding program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTl.. circuit without external
resistors.
The data outPuts are three-state for connecting multiple devices to a common bus. The TMS27C256 and the
TMS27PC256 are pin compatible with 28-pin 256K MOS ROMs, PROMs, and EPROMs.
The TMS27C256 EPROM is offered In a dual-in-line ceramic package (J suffix) designed for insertion in
mounting-hole rows on 15,2-mm (600-mIQ centers. The TMS27PC256 OTP PROM Is offered In a dual-In-line
plastic package (N suffix) designed for Insertion In mounting-hole rows on 15,2-mm (60Q-mil) centers. The
TMS27PC256 OTP PROM Is also supplied in a 32-lead plastic leaded chip-carrier package using 1,25-mm
(50-miQ lead spacing (FM suffix).
The TMS27C256 and TMS27PC256 are offered with two choices of temperature ranges of O°C to 70°C (JL,
Nl, and FML suffixes) and - 40°C to 85°C (JE, NE, and FME suffixes). The TMS27C256 and the TMS27PC256
are also offered with 168-hour burn-in on both temperature ranges (JL4, FML4, JE4, and FME4 suffixes); see
table below.
All package styles conform to JEDEC standards.
EPROM AND
OTPPROM
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WlTHOUTPEP4 BURN..N
SUFFIX FOR PEP4
118oHR. BURN-IN
VI TEMPERATURE RANGES
- we TO 880C
OOCT07O"C
- WC TO 88°C
OOCT070OC
TMS27C256-XXX
JL
JE
JL4
JE4
TMS27PC256-XXX
NL
FML
NE
NL4
FML4
NE4
TMS27P~XXX
FME
FME4
These EPROMs and OTP PROMs operate from a single 5-V supply ~n the read mode), thus are ideal for use
In microprocessor-based systems. One other 13-V supply is needed for programming. All programming signals
are TTL level. These devices are programmable by the SNAPI Pulse programming algorithm. The SNAPI Pulse
programming algorithm uses a Vppof 13 V and a Vee of 6.5 V for a nominal programming time of four seconds.
For programming outside the system, existing EPROM programmers can be used. Locations can be
programmed singly, in blocks, or at random.
~1ExAs .
INSTRUMENTS
7-144
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
TMS27C256 262144·BIT UV ERASABLE PROGRAMMABLE
TMS27PC256 262144·BIT PROGRAMMABLE
READ·ONLY MEMORY
SMLS256G- SEPTEMBER 1984 - REVISED JUNE 1995
operation
The seven modes of operation are listed in the following table. The read mode requires a single 5-V supply. All
inputs are TTL level except for Vpp during programming (13 V for SNAPI Pulse), and 12 V on A9 for the signature
mode.
MODEt
FUNcnON
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
VIL
VIH
VIH·
PROGRAM
INHIBIT
SIGNATURE
MODE
VIH
X
VIL
Vpp
Vee
E
(3
VIL
VIL
VIH
VIL
VIH
X
Vpp
Vee
Vee
Vee
Vpp
VIL
Vpp
Vee
AS
Vee
Vee
Vee
VCC
VCC
x
Vee
X
x
x
x
X
VH'I:
I
NJ
X
X
X
X
X
X
VIL
I
000-DQ7
Data Out
Hi-Z
Hi-Z
Data In
Data Out
Hi-Z
MFG
VIL
Vee
VH*
VIH
CODE
97
I
I
DEVICE
04
tXcan be VIL orVIH.
*VH 12V:t0.5V.
=
read/output disable
When the outputs of two or more TMS27C256s or TMS27PC256s are connected In parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the co!!1peti~ outputs
of the other devices. To read the output of a Single device, a low-level Signal is applied to the E and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins COO through C07.
latchup Immunity
Latchup immunity on the TMS27C256 and TMS27PC256 is a minimum of 250 mA on all inputs and outputs.
This feature provideslatchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
power down
Active ICC supply current can be reduced from 30 mA to 500 IIA (TTL-level inputs) or 250 IIA (CMOS-level
inputs) by applying a high TTL or CMOS signal to the E pin. In this mode all outputs are in the high-impedance
state.
erasure (TMS27C256)
Before programming, the TMS27C256 EPROM is erased by exposing the chip through the transparent lid
to a high intensity ultraviolet light (wavelength 2537 A). EPROM erasure before programming is neCessary to
assure that all. bits are in the logic high state. Logic lows are programmed into the desired locations. A
programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV
intensity x exposure time) is 15-Wos/cm2. A typical 12-mW/cm2 , filterless UV lamp erases the device in 21
minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal
ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C256, the window
should be covered with an opaque label.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443
0
HOUSTON. TEXAS 77251-1443
7-145
TMS27C256 262144-BIT UV ERASABLE PROGRAMMABLE
TMS27PC256 262144-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMI.S258G- SEPTEMBER.1984- REVISED JUNE 1996
Initializing (TMS27PC256)
The one-time programmable TMS27PC256 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAPI Pulse programming
The 256K EPROM and OTP PROM are programmed using 'the TI SNAPI Pulse programming algorithm
Illustrated by the flowchart in Figure 1, which programs in a nominal time of four seconds. Actual programming
time varies as a function of the programmer used.
Data is presented in parallel (eight bits) on pins 000 to 007. Once addresses and data are stable,
e is pulsed.
The SNAPI Pulse programming algorithm uses initial pulses of 100 microseconds (j.tS) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-j.tS
pulses per byte are provided before a failure is recognized.
=
=
=
e=
The programming mode is achieved when Vpp 13 V, Vee 6.5 V, G VIH, and
VIL. More than one device
can be programmed when the devices are connected in parallel. Locations can be programmed in any order.
When the SNAPI Pulse programming routine is complete, all bits are verified with Vee Vpp 5 V.
=
=
program Inhibit
Programming can be inhibited by maintaining a high level input on the
'e pin.
program verify
Programmed bits can be verified with Vpp = 13 V when G = VIL and
e = VIH'
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
actiVated when A9 is forced to 12 V:t 0.5 V. Two identifier bytes are accessed by AO; i.e., AO = VIL accesses
the manufacturer code, which is output on 000-007; AO = VIH accesses the device code, which is output on
OQO-007. All other addresses must be held at VIL. The manufacturer code for these devices is 97, and the
device code is 04.
~1EXAs
7-146
INSTRUMENTS
POST OFFICE BOX 1_ • HOUSTON, TEXAS ~1-1_
TMS27C256 262144-81T UV ERASABLE PROGRAMMABLE
TMS27PC256 262144-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS256G- SEPTEMBER 1984 - REVISED JUNE 1995
Program
Mode
Increment Addre..
Increment
Addre..
Interactive
Mode
No
Final
~
Figure 1. SNAPI Pulse Programming Flowchart
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lEXAS 77251-1443
7-147
TMS27C256 262144-BIT UV·ERASABLE PROGRAMMABLE
TMS27PC256 262144-BIT PROGRAMMABLE
READ·ONLY MEMORY
SM.lS256G- SEPTEMBER 1984 - REVISED JUNE 1996
logic symbol t
AD
A1
A2
A3
A4
AS
AS
A7
AS
At
10
9
8
7
8
T ..
G 22-;::"
A1
A2
II
20
AD
32768x8
4
3
211
24
21
23
2
28
A10
A11
A12
A13
A14 27
E
EPROM
0
0
A 3i7i7
AV
AV
AV
AV
AV
AV
AV
AV
11
12
13
111
111
17
18
19
DQO
A3
A4
AS
D01
AS
DQ2
A7
D03
AI
At
DQ4
D06
DQ8
D07
141
[PWRDWN]
•
JEN
10
OTPPROM
0
32768,,8
9
8
7
8
6
4
3
26
24
21
23
2
28
A 32~87
A10
A11
A12
A13
A14 27
AV
AV
AV
AV
AV
AV
AV
AV
11
12
13
15
18
17
18
19
DQO
DQ1
DQ2
DQ3
DQ4
DQII
DQII
DQ7
14
E
20
G
22-;::" .~
T
[PWRDWN]
I
EN
tThese symbols are In accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for J and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)*
*
Supply voltage range, Vee (see Note 1) .............................................. -0.6 V to 7 V
Supply voltage range, Vpp ......................................................... -0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 ........................... -0.6 V to Vee + 1 V
A9 ............................................... -0.6 Vto 13.5 V
Output voltage range (see Note 1) ..•...•..•.•..•.•••••.•.••••...•..•...•...•• -0.6 V to Vee + 1 V
Operating free-air temperature range ('27C256-__JL and JL4, '27PC256-__NL, NL4, FML,
and FML4) .. .. .. .. .. .. .. .. .. . .. .. .. . .. .. .. .. .... 0° C to 70°C
Operating free-air temperature range C27C256-__JE and JE4, '27PC256-__NE, NE4, FME,
and FME4) ••••.•••••••••••.•.•..•...••.•....•. - 40° C to 85°C
Storage temperature range, Tatg ..••.••.•••..••.•••.•.••.•••.••.••••.•••••••••.••• -65°C to 150°C
Stresses beyond those-listed under "absolute maxlmum ratings" may~se permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" Is not
Implied. Exposure to absolute-maxlmum-rated conditions for extended periods may affect device reliabUity.
NOTE 1: All voltage values are with respect to GND.
~1ExAs
7-148
INSTRUMENTS
POST OFFICE lOX 1443 • HOUSTON. TEXAS 77261-1443
TMS27C256 262144·BIT UV ERASABLE PROGRAMMABLE
TMS27PC256 262144-BIT PROGRAMMABLE
READ·ONLY MEMORY
SMLS258G- SEPTEMBER 1984 - REVISED JUNE 1995
recommended operating conditions
VCC Supply voltage
Read mode (see Note 2)
SNAPI Pulse programming algorithm
MIN
4.5
IU5
Vpp
Read mode
SNAPI Pulse programming algorithm
VCC-0•6
12.75
Supply voltage
NOM
5
6.5
MAX
5.5
6.75
13
VCC+0.6
13.25
UNIT
V
V
2
TTL.
VCc+1
V
CMOS
VCC- 0•2
VCC+1
TTL.
-0.5
0.8
V
Vil Low-level de Input voltage
CMOS
-0.5
0.2
'27C258-__Jl, JL4
'27PC256-__NL, NL4,
·C
OperatIng free-alr temperature
70
0
TA
FML, FML4
'27C258-__JE, JE4
'27PC256-__NE, NE4,
·C
Operating free-alr temperature
-40
85
TA
, . FME,FME4
NOTE 2: Vcc must be applied before or atthe same time as Vpp and ramovad afleror at·the same time as Vpp. The device must not be Inserted
Into or ramovad from the board when Vpp or Vcc is applied.
VIH
High-level de Input voltage
electrical characteristics over recommended ranges of operating conditions
PARAMETER
VOH
High-laval de output voltage
VOL
Low-laval dc output voltage
II
Input current (laakage)
10
Output current Oeakage)
Vpp supply current
TEST CONDmONS
IOH--2.5mA
10H .. - 20 J,IA
IOl-2.1 mA
IpP1
1PP2 Vpp supply current (during program pulse)
TTL.-1nput laval
Vcc supply current
ICC1 (standby)
I CMOS-Input laval
1
IC02 Vee supply current (active)
MIN
3.5
TYpt
MAX
V
VCC- 0.1,
0.4
10l· 20 J,IA
Vl'zOVto 5.5 V
0.1
%1
VO=OVtoVcc
Vpp. VCC. 5.5 V
Vpp .13V
%1
VCC- 5•5V,
E-VIH
VCC- 5•5V,
~-VCC
.VCC- S.5V,
E"Vll,
lcycIa • minimum cycle time,
outputs open
UNIT
1
10
35
250
100
50
500
250
15
30
V
J,IA
J,IA
J,IA
mA
J,IA
mA
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f= 1 MHz*
PARAMETER
TEST CONDmONS
MIN TYPt MAX UNIT
OJ
Input capacitance
Co
Output cepacltance
VI" 0, f== 1 MHz
Vo.O, f.1 MHz
8
10
pF
10
14
pF
t Typical values are at TA • 25·C and norOinai voItagas.
*
CapacItance measurements are made on a sample basls only.
~1ExAs
INSTRUMENTS
POSTOFFICE sox 1443 • HOUSTON, TEXAS 77251-1443
7-149
TMS27C256 262144-BIT UV ERASABLE PROGRAMMABLE
TMS27PC256 262144-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMl.S268?- SEPTEMBER 1984 - REVISED JUNE 1995
switching characteristics over recommended range of operating conditions
TEST CONDITIONS
(SEE NOTES 3 AND 4)
PARAMETER
talE)
tenlG)
Access time from addl'8ll8
Access time from chip enable
Output enable time from ~
tells
Output disable time from GorE, whichever
OCOUI'S flrstt
ty(A)
,Output data valid time lifter change of
!KId_, E, or~, whichever OCOUI'S firstt
taw
(SEE NOTES 3 AND 4)
Access time from address
talA)
talE) • Access time from chip enable
tenlG) Output enable time from G
Output disable time from ~ or E, whichever
OCOUI'S firstt
MIN
MAX
'27C258-12
'27PC256-12
MIN
CL-1OOpF,
1 Sertea 74 TTL Load,
Input tr " 20 ns,
Input If" 20 os
MIN
120
150
ns
120
150
ns
55
55
75
ns
60
ns
0
45
45
'27C256-17
'27PC256-17
MAX
'27C256-20
'27PC256-20
MIN
0
MAX
'27C256-25
'27PC256-26
MIN
UNIT
MAX
170
200
250
ns
170
200
250
75
75
100
ns
ns
60
ns
0
60
0
0
60
Output data valid time after change of
0
0
add_, E, or G, whiChevar OCOUI'S firstt
tVaIue calculated from 0.5 V della to measured level. this panlmeter Is only sampled and not 100% tested.
0
ty(A)
switching characteristics for programming: Vee 6.50 V and Vpp
(see Note 3)
ns
=13 V (SNAPI Pulse). TA =25°C
PARAMETER
telia(G)
ns
0
0
=
UNIT
MAX
100
0
MIN
MAX
'27C256-15
'27PC256-15
100
0
TEST CONDmONS
PARAMETER
tells
CL .. 1oopF,
1 Sertea 74 TTL Load,
Input tr " 20 ns,
Input If " 20 ns
'27C258-10
'27PC258-10
Output dissble time from ~
MIN
MAX
UNIT
0
130
ns
Output enable lime from G
150
ns
ten{Gj
NOTES: 3. For all switching characteristics the Input pulse levels 81'S 0.4 V to 2.4 V. Timing measurements 81'S made at 2 V for logic high and
0.8 V for logic low). (Refel'Snce page 9.)
4. Common test conditions apply for the telia except during programming.
recommende,d timing requirements for programming: Vee
TA = 25°C (S88 Note 3)
= 6.5
V and Vpp
MIN
!h1A)
!hID)
Hold lime, add_
NOM
= 13
MAX
0
':HoId time, data
2
1w(IPGM)
Pulse duratlcn, Initial program
leuW
leulG)
Setup time, add_
95
2
Setuptime,~
2
leulEl
leu(D)
Setup time, E
2
Setup time, data
2
leulVPP)
Setup time, VPP
2
100
105
V.
UNIT
J!S
J!S
J!S
J!S
J!S
J!S
J!S
J!S
J!S
2
Setup time, Vee
leulVCCl
NOTE 3: For aU switChing charsctarlstics the input pulse levels 81'S 0.4 V to 2.4 V. Timing measurements are made at 2 V for logiC high and
0.8 V for logic low). (Reference page 9.)
~1ExAs
7-150
INSTRUMENTS
POST OFFICE &OX 1448· HOU8'lON, TEXAS 77251-1448
TMS27C256 262144-BIT UV ERASABLE PROGRAMMABLE
TMS27PC256 262144-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMl.S268G- SEPTEMBER 1984- REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
2.08 V
.-o.;::--i . . . .
T
~
CL-100pF
(_NoteA)
NOTE A: Cl, Indud. probe and fixture' capacitance.
Figure 2. AC Testing Output Load Circuit
AC testing
Input/output wave forms
2.4
y.----,.V
o.!~X,-___
0.4 y.1oo-_-.l/\ :.:v
AC. testing Inputs are driven at 2.4 V for /ogic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
AO-A14
E
=x,____
.-I!1<,.. . .-_-------------------------- :::
Ad_d_......
__
Va_IId_ _ _ _
,
---+,1----,.\.E-____~df!1
!
'i1
.fr"j- - - - - - - VIH
,
I+-- te(E) --+II
_ _-+-1_ _ _....,.
,
I
\
1II~1----te(A)
--HI..z
14--
rt~ ~
1
I
ten(O)
~
~
---<{«««{
VIL
11
r'- - - - - - -
ty(A) I'llii
Output Valid
"I
VIH
tel.. --tJf
I
}»»»}. HI~
-
:::
Figure 3. Read-Cycle Timing
~1ExAs .
INSTRUMENTS
POST OFFICE lOX 1441- HOUSTON. lexAII772I1-1441
7-151
TMS27C256 262144-BIT UV ERASABLE PROGRAMMABLE
TMS27PC256 262144-BIT PROGRAMMABLE
READ·ONLY MEMORY
SMlS258G- SEPTEMBER 11184- REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Progl'llm - - -....~'I,.I
..~_v.rIfy _ _+l~1
I"
AO-A14
X
_ _.J
~
DQO-DQ7
Add_S~b~
;
1
I+- "u(A)
---<~ ~.-
Vee
XAd:~
1
:IH
IL
r . . . .i. ---(~ _~+W ~)-----:::;:::
I+- tt.~ ~
1
1
1
1 idl-zz
4
• 512K EPROM Available With MIL-8TD-883C
Class B High Reliability Processing
(SMJ27C510)
31 30
o
A7
A6
AS
A9
A2
G
A1
A11
A10
11
E"
DQO
· These devices are fabricated using power saving
CMOS technology for high speed and simple
Interface with MOS and bipolar circuits. All inputs
(including program data Inputs) can be driven by
Series 74 TTL circuits without the use of external
pull-up resistors. Each output can drive one
Series 74 TTL circuit without external resistors.
007
1415 16. 1718 19 20
The TMS27C510 series are 524288-blt, ultraviolet-light erasable, electrically programmable
read-only memories.
The TMS27PC510 series are 524288-bit, onetime electrically programmable read-only
memories.
A14
A13
AS
A4
A3 9
AO
description
29
PIN NOMENCLATURE
AO-A15
Address Inputs
E
Chip Enable
Inputs (programming)/Outputs
Output Enable
Ground
No Internal Connection
5-V Power Supply
12·13 V Power Supply
000-007
G
GND
NC
Vee
Vpp
:Jf.1ExAs
INSTRUMENTS
POST OFFICE eox 1443 • HOU8TON. TEXAS 77251-1443
CopyrIght C 1895. Texas Instruments Incorporated
7·155
TMS27C510 524288-BIT UV ERASABLE PROGRAMMABLE
TMS27PC510 524288-BIT PROGRAMMABLE
READ'()NLYMEMORY
SMLS61OB-AUGUST 1980 - REVISED JUNE 1996
description (continued)
The data outputs are three-state for connecting multiple devices to a common bus. The TMS27C510 and the
TMS27PC510 are pin compatible with 32-pin 1-megabit MOS ROMs, PROMs, andEPROMs.
The TMS27C510 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting-hole rows on 15,2-mm (600-mil) centers. The TMS27C510 Is available with two choices of
temperature ranges of O·C to 70·C (JL suffix) and - 4O·C to 85·C (JE suffix). The TMS27C510 is also offered
with 168-hour bum-in on both temperature ranges (JL4 and JE4 suffixes). (See table below.)
The TMS27PC510 PROM Is offered in a dual-in-line plastic package (N suffix) designed for insertion in
mounting-hole rows on 15,2-mm (600-miQ centers. The TMS27PC510 Is also supplied in a 32-lead plastiC
leaded chlp-carrier package using 1,25-mm (50-miQ lead spacing (FM suffix). The TMS27PC51 0 Is specified
for operation from O·C to 70·C, and - 4O·C to 85·C.
All package styles conform to JEDEC standards.
SUFFIX FOR OPERATING
TEMPERATURE RANGES
EPROM
SUFFIX FOR PEP4
168-HR. BURN-IN
VSTEMPERATURERANGES
~HOUTPEP4BURN4N
O'CTO 70'C
TMS27C510-XXX
- 4O'C TO 85'C
JE
NE,FME
JL
NL, FML
TMS27PC510-XXX
O·CTO 7O'C
- 4O'C TO 85'C
JE4
NE4,FME4
JL4
-
These EPROMs and PROMs operate from a single 5-V supply (in the read mode), thus are Ideal for use in
microprocessor-based systems. One other (13-V) supply is needed for programming. All programming signals
are TTL level. These devices are programmable by a SNAPI Pulse programming algorithm. The SNAPI Pulse
programming algorithm uses a Vpp of 13.0 V and a Vee of 6.5 V for a nominal programming time of seven
seconds. For programming outside the system, existing EPROM programers can be used. Locations can be
programmed singly, in blocks, or at random.
operation
The seven modes of operation are in the following table. Read mode requires a Single 5-V supply. All Inputs are
TTLlevel except for Vpp during programming (13.0 V for SNAPI Pulse). and 12 V on A9 for the signature mode.
MODEt
FUNCTION
READ
OUTPUT
DISABLE
E
VIL
VIL
(J
VIL
Vee
VIH
Vpp
STANDBY
VIH
X
PROGRAMMING
VERIFY
VIL
VIH
VIL
Vpp
PROGRAM
INHIBIT
SIGNATURE
MODE
VIH
X
VIL
Vpp
Vee
Vee
VIH
Vpp
VIL
Vee
Vee
Vee
x
x
x
Vee
X
VH*
Vee
AS
Vee
x
Vee
Vee
X
AD
X
X
X
X
X
X
VIL
OQO-OQ7
Data Out
HI-Z
HI-Z
Data In
Data Out
HI-Z
MFG
Vee
97
tXcan be VILor VIH •.
*VH-12V:tO.5V.
-!lJTEXAS
7-158
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 772t11-1443
I
J
VH*
VIH
CODE
I DEVICE
I
15
TMS27C510 524288-BIT UV ERASABLE PROGRAMMABLE
TMS27PC510 524288·BIT PROGRAMMABLE
READ·ONLY MEMORY
SMLS510B - AUGUST 1990 - REVISED JUNE 1995
read/output disable
When the outputs of two or more TMS27C51 OS or TMS27PC51 OS are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the cOElpeti'!9 outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data Is accessed at pins DQO to DQ7.
latchup Immunity
Latchup immunity on the TMS27C51 0 and TMS27PC510 is a minimum of 250 mA on all inputs and outputs.
This feature provides latch!JP immunity beyond any potential transients at the P.C. board level when the EPROM
is interfaced to industry standard TTL or MOS logic devices. Input/output layout approach controls latchup
without compromising performance or packing density.
powerdown
Active Icc current can be reduced from 30 mA to 500 !AA by applying a high TTL input on E and to 100 !AA by
applying high CMOS Input on E. In this mode all outputs are in the high-impedance state.
erasure (TMS27C510)
Before programming, the TMS27C510 EPROM is erased by exposing the chip through the transparent lid to
high IntenSity uHraviolet light (wavelength 2537 A). The recommended minimum exposure dose (UV intensity
x exposure time) is 15-W s/cm2. A typical 12-mW/ cm2, filterless UV lamp erases the device in 21 minutes. The
lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal ambient light
contains the correct wavelength for erasure. Therefore, when using the TMS27C510, the window should be
covered with an opaque label. After erasure (all bits in logic 1 state), logic Os are programmed into the desired
locations. A programmed zero can be erased only by ultraviolet light.
Initializing (TMS27PC510)
The one-time programmable TMS27PC510 PROM is provided with all bits in logic 1 state, then logic Os are
programmed into the desired locations. Logic Os programmed into- a PROM cannot be erased.
SNAPI Pulse programming
The 512K EPROM and PROM can be programmed using the TI SNAPI Pulse programming algorithm as
illustrated by the flowchart in Figure 1, which can reduce programming time to a nominal 7 seconds. Actual
programming time varies as a function of the programmer used.
The SNAPI Pulse programming algorithm uses initial pulses of 100 microseconds (I!s) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-!!S
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when Vpp = 13.0 V, Vee = 6.5 V, G = VIH, and E = VIL' Data is presented
in parallel (eight bits) on pins DQO to DQ7. Once addresses and data are stable, E is pulsed.
MOre than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAPI Pulse programming routine is complete, aU bits are verified with
Vee =Vpp = 5V.
program Inhibit
Programming can be inhibited by maintaining a high level input on the E pin.
program verify
Programmed bits can be verified with Vpp = 13.0 V when G = VIL and E = VIH'
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lEXAS 7721i1-1443
7-157
TMS27C510 524288-BIT UV ERASABLE PROGRAMMABLE
TMS27PC510 524288-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMl.S51OB-AUGUST 1880 - REVISED JUNE 1995
signature mode
The signature mode provides access to a binaiy code identifying the manufacturer and type. This mode is
activated when AS Is forced to 12 V :t 0.5 V. Two identifier bytes are accessed by AO; i.e., AO VIL accesses
the manufacturer code which is output on 000-007; AO VIH accesses the device code which is output on
OQO-007. All other addresses must be held at VIL. The manufacturer code for these devices is 97, and the
device code is 15.
=
=
~/~
~1ExAs
7-158
.
INSlRUMENTS
PosT OFFICE BOX 1443 •
.
HOUSTON, TEXAS 77251':'1443
TMS27C510 524288-BIT UV ERASABLE PROGRAMMABLE
TMS27PC510 524288-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS51OB- AUGUST 1990 - REVISED JUNE 1195
l
Program
Mode
Increment Add,..e
Increment
AclcIrMe
Interactive
Mode
Device Failed
Fall
Final
J
Figure 1. SNAPI Pula, Programming Flowchart
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77281-1443
7·159
TMS27C510 524288-BIT UV ERASABLE PROGRAMMABLE
TMS27PC510 524288-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS510B- AUGUST 1890 - R!'VISED JUNE 1995
logic symbolst
AD
A1
A2
A3
12
11
10
9
A4 8
A5 7
ASS
5
A7 27
AS 28
AS
A10 23
A11 25
4
A12 28
A13 29
A14 3
A1.,! 2
E
G 24
EPROM 85 536 " 8
AD
A1
A2
A3
0
0
Ai6i3i
AV
AV
AV
AV
AV
AV
AV
AV
DOG
DQ1
DQ2
DQ3
DQ4
DQ5
DQ8
DQ7
A4
A5
AS
A7
AS
AS
A10
A11
A12
A13
A14
A11S
12
·11
10
9
8
7
S
5
27
28
23
25
4
28
29
3
PROM 85 536 " 8
0
0
A 85536
AV
AV
AV
AV
AV
AV
AV
AV
DQO
DQ1
DQ2
DQ3
DQ4
DQ5
D08
DQ7
E
EN
G 24
EN
tThese symbols are in accordance with ANSIIIEEE Std 91-1984 and lEO Publication 617-12.
J and N packages Illustrated.
absolute maximum ratings over operating free-alr temperature range (unless otherwise noted)*
Supply voltage range, Vee (see Note 1) ............................................. - 0.6 V to 7 V
Supply voltage range, Vpp (see Note 1) ............................................ - 0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 .............•.......•.......... - 0.6 V to 6.5 V
A9 ........•.............................•..•...• - 0.6 V to 13.5 V
Output voltage range (see Note 1) .................................... :....... - 0.6 V to Vee + 1 V
Operating free-air temperature range ('27C510- __ JL and JL4;
'27PC510- __ Nl, FML, NE, and FME) ••.••.•.•.•... O°C to 70°C
Operating free-air temperature range ('27C510- __ JE, JE4, NE4, and FME4) •.•.•..•... - 40°C to 85°C
Storage temperature range, Tstg .................................................. - 65°C to 150°C
*functional
stresses
beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These Bra stress ratings only. and
operation of the device at these or any other conditions beyond thoee Indicated under "recommended operating conditions' is not
Implied. Exposure to absolute-maximum-rated conditions for axtended periods may a1fec:t device reliability.
NOTE 1: Under absolute maximum ratings, voltage values are with respect to GND.
~1EXAS
7-160
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
TMS27C510 524288-BIT UV ERASABLE PROGRAMMABLE
TMS27PC510 524288-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS5108-AUGUSTI990 -REVISED JUNE 1995
recomm.nd.d operating conditions
Read mode (see Note 2)
Vee
Supply VOIlage
VPP
Supply voltage
VIH
High-level dc Input voltage
VIL
Low-level dc Input voltage
TA
Op8ratlng free.alr temperature
SNAPI Pulse programming algorithm
Read mode
SNAPI Pulse programming algorithm
TTl
MIN
NOM
MAX
4.5
5
5.5
8.25
8.5
8.75
Vee- 0•8
12.75
13
VCC+0.8
13.25
2
CMOS
VCC+1
VCC-0.2
-0.5
TTL
CMOS
VCC+1
0.8
-0.5
0.2
UNIT
V
V
V
V
·C
(see Table, page 2)
NOTE 2: Vee must be applied before or at Ihe same time ae Vpp and ramoved afteror stlhe same time ae Vpp. The device must not be Inserted
Into or removed from the board when Vpp or Vcc Is applied •
• Iectrlcal charact.rlstlcs ov.r r.comm.nd.d rang.s of supply voltag. and op.ratlng fr....lr
t.mperatur.
PARAMETER
VOH
High-level output voltage
VOL
Low.Jevel output voltage
II
Input current (leakage)
10
Output current Oeekage)
TEST CONDITIONS
10H --2011A
IOL=2.1 mA
VCC- 0•1
MAX
0.4
0.1
:t1
IpP1
Vpp supply current
Vpp supply current (during program pulse)
Vpp .13V
:t1
V
1
10
IIA
IIA
IIA
35
50
mA
IIA
mA
ITTl-input level
VCC = 5.5 V, ..... E=VIH
250
I CMOS-Input level
VCC=5.5V,
e=VCC
100
500
250
VCC=5.5V,
E"VIL,
tcycle = minimum cycle time,
outputs open
15
30
ICC2 VCC supply current (active)
UNIT
V
10L=20 IIA
VI-OVto5.5V
IpP2
Vcc supply current (stendby)
TYPt
3.5
VO-OVtoVCC
Vpp -VCC -5.5V
ICC1
MIN
IOH--2.5mA
t Typical values are st TA = 25·C and nominal voItagee.
capacltanc. ov.r recomm.nded rang.s of supply voltag. and op.ratlng fr••-alr temperature,
f= 1 MHz*
TVPt
MAX
CI
Input capacitance
VI - 0 V, f .. 1 MHz
8
10
pF
Co
Output cepacltance
Vo • 0 V, f. 1 MHz
10
14
pF
PARAMETER
TEST CONDITIONS
MIN
UNIT
*
t Typical valuae are at TA - 25·0 and nominal voItagae.
Capacitance meaeurements are made on sample basis only.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOU8'TON, TEXAS 77251-1443
7-181
TMS27C510 524288-81T UVERASABLE PROGRAMMABLE
TMS27PC510 524288-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS5108-AUGUST 1980 - REVISED JUNE 1995
switching characteristics over recommended ranges of operating conditions
TESTCONDmoNS
(SEE NOTES 3 AND 4)
PARAMETER
taCAl
talE'l
Acce8s time from address
Acce8s time from chip enable
tenCG}
Output enable time from G
Idis
Output disable time from GorE, whichever occurs firstt
tv(A)
Output data valid time after change of address,
E, or G,
'27C510-12
'27PC510-12
MIN
CL-100pF,
1 SerIes 74 TTL Load,
Input tr • 20 ns,
Input tf • 20 ns
0
TEST CONDmONS
(SEE NOTES 3 AND 4)
'27C510-17
'27PCS10-17
MIN
MAX
UNIT
MAX
1&0
ns
120
1&0
ns
55
75
ns
60
ns
45
0
ns
0
'27C510-20
'27PC&10-20
MIN
MIN
120
0
whichever occurs firstt
PARAMETER
MAX
'27CS10-15
'27PCS10-15
MAX
'Z7C510-25
'Z7PC510-25
MIN
UNIT
MAX
ta(A)
Acce8s time from address
170
200
2&0
ns,
talE)
Access time from chip enable
170
200
2&0
ns
ten(G)
Output enable time from G
75
7&
100
ns
Idls
Output disable time from G or E,
whichever occurs firstt
60
ns
tv(A)
Output data valid time after change of
address, E, or G, whichever occurs firstt
1
Sa"" tr •
CL -100 pF,
74 TTL Load,
Input
20 118,
Input tf • 20 ns
0
60
0
0
60
0
0
ns'
0
t Value calculated from 0.& V delta to measured output level. This parameter Is only sampled and not 100% tested.
=
=
switching cl1aracterlstlcs for programming: Vee 6.6 V and Vpp 13.0 V (SNAP I Pulse), TA =25°C
(see Note 3)
PARAMETER
IdlslG}
Output disable time from G
tenCG}
Output enable time from G
MIN
MAX
0
130
UNIT
ns
1&0
ns
recommended timing requirements for, programming. Vee =6.5 V and Vpp = 13.0 V (SNAPI Pulse).
TA = 25°C (see Note 3)
1SNAP! Pulse programming algorithm
MIN
NOM
MAX
UNIT
95
100
10&
I4S
I4S
I4S
I4S
I4S
I4S
I4S
I4S
I4S
twlPGM}
Pulse duration, program
leuCA}
Setup time, address
2
leuCG}
Setup time, G
2
leuCE}
Setup time, E
2
leulO)
leuNPP}
Setup time, data
2
Setup time, Vpp
2
leu (Vee)
Setup time, Vee
Hold time, address
0
theA)
Z
Hold time, data
Z
th(D)
NOTES: 3. For all switching characteristics, the Input pulse levels are 0.4 V to 2.4 V. liming measurements are made at 2 V for logic 1 and
0.8 V for logic O. (Reference page 9.)
4. Common test conditions apply for the Idls except during programming.
~1ExAs
7·162
INSTRUMENTS
POST OFF1CE BOX 1443 • HOUSTON, TEXAS 71261-1443
TMS27C510 524288·BIT UV ERASABLE PROGRAMMABLE
TMS27PC510 524288-BIT PROGRAMMABLE
READ·ONLY MEMORY
SMLS51OB-AUGUSTI990 -REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
2.08 V
_",,=--4.
·L· ... O
T':'
CL-100pF
(_NOleA)
NOTE A: CL Includes probe and fixture capacitance.
Figure 2. AC Testing Output Load Circuit
AC testing Input/output wave forma
:::0<""___
2.4Y--~X 2.0V
0.4 y _ _- J .
_
0.8 V
AC testing Inputs are driven at 2.4 V for logic high and 0.4 V for logiC low. liming measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
AO-A15
x
I
14
ftI(A)
\
E
X
VIH
11
VIH
11I+-
VIH
AddreeaYa11d
I
I
I
I+--ftl(E)~
\
G
DQO-DQ7
Hh'Z
I
I
I
l.- ten(Q) -+I
«««({
VIL
I I
I 1
I I
I
I
VIL
I
1
~
t,,(A)
1
14
OutputYalid
~I
tclia
VIL
--.j
I
))))}
HI~ -
:::
Figure 3. Read-Cycle Timing
~1ExAs
.
INSTRUMENTS
POST OFFICE BOX 1443· HOU81ON. TEXAB 7721i1-1443
7-183
TMS27C510 524288·BITUV ERASABLE PROGRAMMABLE
TMS27PC510 524288-BIT PROGRAMMABLE
READ·ONLY MEMORY
SMLS51 OB..,. AUGUST 1990 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
I~
1
AO-A15
lol
"I .
Program
=x
( 7"---.A
I
}-H1--<
---.A
1
feu(VCC)
E
1
1
1
I
I
"tf
I~
1
1
I
I
I
I
I
1
1
~
I
-..,
I
~w
tw(pGM)
I
I
I
I
I
I
~feu(VPP)
Vcc
,
14
"I
r-
I
"I
VIL
VIH/VOH
VIL/VOL
tclI8(G)t
Vpp*
1
1
Vcc
1
1
1
1
Vcc*
ItJ(D)
~ !~,.
I 14
Vcc
I
1
1
"I
J
fen(G) .
t tctls(G) and tan(G) are characteristics of the device but must be accommodated by the programmer.
* 13.o-V Vpp and a.Sov Vee for SNAPI Pulse programming
Figure 4. Program-Cycle Timing
~TEXAS
7-184
VIH
I
I
'{ l;f
G
1
N+1
I
I
~
Addreaa
loll- "'fAl -+I
1
1
I
~feu(D)
Vpp
:x
1
--7
l+-..t-tau(A)
DQO-DQ7
Verify--+!
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
VIH
VIL
VIH
VIL
TMS27C510 524288-BIT UV ERASABLE PROGRAMMABLE
TMS27PC510 524288-BIT PROGRAMMABLE
READ·ONLY MEMORY
SMLS61OB- AUGUST 1990 - REVISED JUNE 1896
device symbolization
0
TMS
27C51 0
LXPVYWW
-r
Wafer Fab Code
Ole Revlalon Code
Auembly Site Code
'Vear of Manufactu re
Month of Manufactu
-~
-r
-I'"'
""'"
~
TI FML
TMS27PC510
~
LXPYVWW
-
-I'"'
-
-r - - - r
W8far Fab Cod.
Ole Revision Cod.
Auembly Site Cod
Vear of Manufactu re
Month of Manufacture
•
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
7-166
TMS27C510 524288-BIT UV ERASABLE PROGRAMMABLE
TMS27PC510 524288-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS51OB-AUGUST1980 -REVISED JUNE 1995
TYPICAL TMS27C/POC510 CHARACTERISTICS
J
-t
!
STANDBY SUPPLY CURRENT
STANDBY SUPPLY CURRENT
FREE·A1R TEMPERATURE
SUPPLY VOLTAGE
va
f
1.&0
1.&0
Vcc-1.0V
......
.......
1.28
............
1.00
~
~.~
~
TA-28°e
1.28
r--....
"""'" r--
II ~71
.Ii
va
0
28
&0
-- -
n
~
~
1.00
~75
.""
~4.28
./
4.1
TA-Frft-AlrTemperatura-OC
va
1.00
~
r........ ...........
-25
TA-28°e
hMA)(
........
0.75
.lJ ~&O-75
1.&0
V~"'OV
.......
o
25
--
&0
1.25
I--.
75
1.00
100
V
,.
128
/
~&O
4.28
4.5
4.71
FREE·A1R TEMPERATURE
SUPPLY VOLTAGE
V
~
5.71
va
1.&0
,- - '
--
1.5
ACCESS TIME
.,..... v
L..-.....-
TA-28°e
1.25
1.00
.....
r........ ......
~75
0
25
&0
71
100
128
~
4.28
TA-Frae-AJrTemperatura-oC
~1ExAs
7-168
5.25
ACCESS TIME
Vcc-1.0V
~
s.o
,..-
Vec-Supply Voltage-V
"....
0.10
-71
V
TA-Frae-AJr Temperatura-OC
va
1.&0
1.71
SUPPLY VOLTAGE .
FREE·A1R TEMPERATURE
at 11.21
I
4.71 s.o 1.28 s.s
Vee-Supply Voltage-V
va
1.&0
v
ACTIVE SUPPLY CURRENT
ACTIVE SUPPLY CURRENT
J
V
./
,/'
INSTRUMENTS
POST OFFICE BOX 1448 • HOUSTON, TEXAS 77251-1448
4.S
4.71
1.0
5.25
1.1
Vee-Supply Voltage-V
1.75
TMS27C512 524288-BIT UV ERSABLE PROGRAMMABLE
TMS27PC512 524288-BIT PROGRAMMABLE
READ·ONLY MEMORY
SMLS512F-NOVEMBER1985-
•
•
•
•
•
•
•
This Data Sheet is Applicable to All
TMS27C512s and TMS27PC512s Symbolized
with Code -8- as Described on Page 182.
Organization ••• 64K )( 8
Single 5-V Power Supply
Pin Compatible With Existing 512K MOS
ROMs, PROMs, and EPROMs
AlllnputslOutput8 Fully TTL Compatible
Max AccesS/Min Cycle Time
Vee =10%
'27C/PC512-10
100 ns
'27C/PC512-12
120 ns
'27C/PC512-15
150 ns
200 ns
'27C/PC512-20
'27C/PC512-25
250 ns
Power Saving CMOS Technology
Very High-Speed SNAPI Pulse
Programming
J AND N PACKAGES
(TOP VIEW)
VCC
A14
A13
AS
A9
A11
(l/Vpp
A10
E
007
DOS
DQS
D04
D03
FMPACKAGE
(TOP VIEW)
• 3-State Output Buffers
• 400-mV Minimum DC 'Noise Immunity With
Standard TTL Loads
• Latchup Immunity of 250 mA on All Input
and Output Un..
• Low Power Dissipation (Vee = 5.25 V)
- Active ••• 158 mW Worst Case
- Standby ••• 1.4 mW Worst Case
(CMOS Input Levels)
• PEP4 Version Available With 168-Hour
Bum-In, and Choices of Operating
Temperature Ranges
• 512K EPROM Available With MIL-STD-883C
Class B High Reliability Processing
(SMJ27C512)
NIO:::>O.,.(')
!;«<. .___________----!x,.------J
1 "--------
1
...
~I----te(A)
.1
ITro- - - - - - -
~11;.1------+---~I
I } !1
14-- te(E) ~
--------""\\
_
J
i4- ten(G) """"1
DQO-DQ7
HI-Z
VIH
VIL
JAr-------- :::
}»»»>1 1
!
I
VIL
1
I
-----~\
GlVpp
VIH
Add....... Valid
ty(A)
---««««{
1 I+-- leila ---+t
~
.1
I
Output Valid
HI-Z -
:::
Figure 3. Read-Cycle Timing
AO-A15
=x_________
x= :::
Ad_d_re_H_S_ta_ble
__________
tIIII..---I~~I-th(A)
I+-+!-teU(A)
DQO-DQ7
I
))0---
~ta-In Stable
---«
1
1
1
1
~ teu(D) +I
Ci/Vpp
----If
1
I
1
1
1
j)---I
~
IeIla(G) t
I1 Ih(vpp} --loIIII1~f---IJ.\
~
I
1
1 I~----~I~------~I---------
~
teu(vpP) 1
1
I
I
I
I I
1
1
I
I~
~
1
I
I
I
114~--.~I-1
I
teu-(Ve-C)---;II~-""'~
I
Data-out Valid
I
I+- 1h(D}
1
-+I j+" tr~G)G
I
---«
teHD
I I~
I I
E
HI-Z
1
trec(PG)
VPP
VIL
1
I
1
I
~s..1__---'/----
Iw(lPGM)
1
Vee*
Vee
Vee
t tclls(Gl is a characteristic of the device but must be accommodated by the programmer.
*
13-Y G/Vpp and a.s-Y Vee for SNAPt Pulse programming.
Figure 4. Program-Cycle Timing (SNAPI Pulse Programming)
-!!11ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlCN. TEXAS 77251-1443
7-1n
TMS27C512 524288-BITUV ERSABLE PROGRAMMABLE
TMS27PC512 524288-BIT PROGRAMMABLE
READ-ONLY MEMORY
.
SML.S512F - NOVEMBER 1985 - REVISED JUNE 1995
device symbolization
This data sheet is applicable to all TI TMS27C512 CMOS EPROMs and TMS27PC512 CMOS OTP PROMs
with the data sheet revision code -8" as shown below. .
.
L~
0
FML
TMS27PC612
B
Data Sheet RevleIon Code
Wafer Fab Code
DIe Revlelon Cod
Assembly SIta Cod
V..r of Manufaclura
Week of Manufaclura
L
X
P
vv
..If
TMS
27C512
'!!'If.
B
Data Sheet Ravl8lon Code
Wafer Fab Code
DIe RavlaJon Code
Assembly SIte Code
V.ar of Manutactura
Month of Manutaclura
~1ExAs
INSTRUMENTS
7-178
..........
........
n
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
L
X
P
vvYfti
TMS27C010A 1048576-BIT UV ERASABLE PROGRAMMABLE
TMS27PC010A 1048576-BIT PROGRAMMABLE
READ-ONLY MEMORY
• Organization ••• 128K x 8
• Single 5-V Power Supply
• Operationally Compatible With existing
Megabit EPROMs
J AND N PACKAGES
(TOP VIEW)
• Industry Standard 32-Pln Dual-in-llne
Package, 32-Lead Plastic Leaded Chip
Carrier, and 32-Lead Thin Smail-Outline
Package
• Allinputa/Outputa Fully lTL Compatible
• Max Access/Min Cycle TIme
Vee:t:10%
'27C01OA-10
100 ns
'27C/PC010A-12 120 ns
'27C/PC010A-15 150 ns
'27C/PC010A-20 200 ns
Vpp
Vcc
A16
A15
A12
A7
PGM
NC
A14
A13
AS
AS
A4
A3
AS
A9
A11
G'
A10
A2
E
A1
AO
000
001
002
• 8-Blt Output For Use In
Microprocessor-Based Systems
007
006
005
004
003
GND
• Very High-Speed SNAPI Pulse
Programming
FM_PACKAGE
(TOP VIEW)
• Power·Saving CMOS Technology
• 3-State Output Buffers
• 400-mV Minimum DC Noise Immunity With
Standard lTL Loads
• Latchup Immunity of 250 mA on All Input
and Output Pins
(\/It)CDQ.81:::Eo
<< < ~::>
~z
o
• No Pull up Resistors Required
• Low Power Dissipation (Vee 5.5 V)
- Active ••• 165 mW Worst Case
- Standby ••• 0.55 mW Worst Case
(CMOS-Input Levels)
AS
=
• ~EP4 Version Available With 168·Hour
Burn-In and Choices of Operating
Temperature Ranges
A14
A13
A9
A11
G'
A10
E
AO
000
007
1415 16 17 18 19 20
deSCription
The TMS27C010A series are 1048516-bit,
uHraviolet-light erasable, electrically programmable read-only memories.
PIN NOMENCLATURE
AO-A18
The TMS27PC010A series are 1048516-bit,
one-time electrically programmable read-only
memories.
Address Inputs
000-007 Inputs (programming) 100tputs
E
Chip Enable
Output Enable
G
GNO
NC
PGM
Vcc
Vpp
Ground
No Intemal Connection
Program
SoV Power Supply
13-V Power Supplyt
t Only In program mode
-!111EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
Copyright C 1996. Texas Instruments Incorporated
7-179
TMS27C010A 1048576-BIT W ERASABLE PROGRAMMABLE
TMS27PC010A 1048576-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS110B - NoveMBER 1880 - REVISED JUNE 1895
TM$27PC010A ••• DD PACKAGEt
(TOP VIEW)
A11
AS
M
A13
A14
10
2.
3
4
5
32
G
31
A10
30
E
29
~
7
28
U
28
Vee
Vpp
8
25
OQ7
OQ6
OQ5
OQ4
OQ3
8
10
11
12
13
14
15
16
24
VSS
23
NC
A16
A15
A12
A7
AS
A5
A4
8
21
OQ2
OQ1
OQO
20
AO
18
18
17
A1
22
A2
A3
TMS27PC010A ••• DU PACKAGEt
REVERSE PINOUT
(TOP VIEW)
G
\l
A11
A9
A10
E
OQ7
OQ6
OQ5
004
DQ3
AS
4
A2
A3
28
PGM
Vee
Vpp
NC
25
24
10
11
12
13
14
15
16
20
A16
A15
A12
A7
18
AS
23
22
21
t The packages shown are for pinout reference only.
~ThxAs
7·180
A13
A14
5
Vss
DQ2
DQ1
DQO
AO
A1
29
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, 1EXA8 n2s1-1443
18
A5
17
A4
TMS27C010A 1048576-BIT UV ERASABLE PROGRAMMABLE
TMS27PC010A 1048576-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS110B - NOVEMBER 1990 - REVISED JUNE 1995
description (continued)
These devices are fabricated using power-saving CMOS technology for high speed and Simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C010A EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 1S,2-mm (600-mil) centers. The TMS27C010A is also offered with two choices of
temperature ranges, O°C to 70"C (JL suffix) and -40"C to 8S"C (JE suffix). The TMS27C010A is also offered
with 168-hour bum-in on both temparature ranges (JL4 and JE4 suffix). (See table below.)
The TMS27PC01 OA OTP PROM is offered in a dual-in-line plastiC package (N suffix), a 32-pin, plastic leaded
chip carrier package using 1,2S-mm (SO-mil) lead spacing (FM suffix), and a 32-lead TSOP package (DO and
DU suffixes). The TMS27PC010A is offered with two choices of temparature ranges, O"C to 70°C (NL, FML,
DOL, and DUL suffixes) and - 4O"C to 8S"C (NE, FME, DOE, and DUE suffixes). (See table belOW.)
EPROM
AND
OTPPROM
TMS27C010A-xxx
TMS27PC010A-xxx
SUFFIX FOR OPERATING
TEMPERATURE RANGES
wrrHOUT PEP4 BURN-IN
va
SUFFIX FOR PEP4
168 HOUR BURN-IN
TEMPERATURE RANGES
O·Cto 70·C
- 4O·C to 8S·C
O·Cto 70·C
JL
JE
JL4
JE4
NL
NE
NL4
NE4
FML4
FME4
FML
FME
DOL
DOE
DUL
DUE
- 4O·C to 8S·C
These EPROMs and OTP PROMs operate from a single S-V supply (in the read mode), thus are ideal for use
in microprocessor-based systems. One other 13-V supply is needed for programming. All programming signals
are TTL level. These devices are programmable using the SNAPI Pulse programming algorithm. The SNAPI
Pulse programming algorithm uses a Vpp of 13 V and a Vee of 6.S V for a nominal programming time of thirteen
seconds. For programming outside the system, existing EPROM programmers can be used. Locations can be
programmed singly, in blocks, or at random.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON, TEXAS 772151-1443
7-181
TMS27C010A 1048576-BIT UV ERASABLE PROGRAMMABLE
TMS27PC010A 1048576-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS110B- NOVEMBER 1990- REVISED JUNE 1995
operation
The seven'modes of operation are listed In the following table. The read mode requires a single 5-V supply. All
Inputs are TIL level except for Vpp during programming (13 V for SNAPI Pulse), and 12 V on A9 for signature
mode.
MODET
FUNCTION
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE MODE
VIH
VIL
E
VIL
VIL
VIH
VIL
VIL
G
PGM
VIL
VIH
X
VIH
VIL
x·
X
X
X
X
Vee
Vee
Vee
VIH
Vpp
X
Vpp
VIL
Vpp
Vpp
Vee
Vee
AS
Vee
Vee
X
Vee
Vee
Vee
Vee
x
x
x
x
X
VH*
VH*
X
X
X
X
X
x'
I
AO
VIL
I
VIH
VIL
Vee
CODE
DQO-OQ7
oataOut
Hi-Z
Hi-Z
Data In
Data Out
HI-Z
MFG
I
DEVICE
97
I
06
t X can be VIL or VIH.
*VH=12VzO.5V.
read/output disable
When the outputs of two or more TMS27C01 OAs orTMS27PC01 OAs are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from coiPpeti~ outputs of the
other devices. To read the output of a single device, a lOW-level signal Is applied to the "E and G pins. All other
devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.
latchup Immunity
Latchup immunity on the TMS27C01 OA and TMS27PC01 OA is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are Interfaced to Industry standard TIL or MOS logic devices. The Input/output layout approach controls
latchup without compromising performance or packing density.
power down
Active ICC. supply current can be reduced from 30 mA to 500 I!A by applying a high TIL input on E and to
100 I!A by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure (TMS27C010A)
Before programming, the TMS27C01 OA EPROM is erased by exposing the chip through the transparent lid to
a high intensity ultraviolet light (wavelength 2537 A). The recommended minimum exposure dose (UV intenSity
x exposure time) is 15-W·s/cm2• A typical 12-mWIcm 2 , filterless UV lamp erases the device in 21 minutes. The
lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state.
It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using
the TMS27C01 OA, the window should be covered with an opaque label. After erasure (all bits in logic high state),
logic lows are programmed into the desired locations. A programmed low can be erase
AV
AV
AV
AV
AV
AV
AV
AV
24
18
~
,....,
(PWRDOWN]
•I
EN
*Thla symbol Is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12. J package illustrated.
:lllExAs
INSTRUMENTS
POST OFFICE BOX 1+13 • HOUSTON. '1eXA11772II1-1+13
7-166
TMS27C010A 1048576-BIT UV ERASABLE PROGRAMMABLE
TMS27PC010A 1048576-BI1 PROGRAMMABLE
READ-ONLY MEMORY
SMLS110B - NOVEMBER 1990 - REVISED JUNE 1895
absolute maximum ratings over operating free-alr temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ........................•..................... -0.6 V to 7 V
Supply voltage range, Vpp ......................................................... -0.6 Vto 14 V
Input voltage range, All inputs except A9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .• -0.6 V to Vee + 1 V
A9 ................................•....•.•.................. -0.6 V to 13.5 V
Output voltage range, with respect to Vss (see Note 1) .......................... -0.6 V to Vee + 1 V
Operating free-air temperature range ('27C010A-__JL and JL4,
'27PC010A-__NL, FML, DOL, and DUL) ............. O·C to 70·C
Operating free-air temperature range ('27C010A-__JE and JE4,
'27PC01 OA-__NE, FME, DOE, and DUE) ......... - 40·C to 85·C
Storage temperature range, Tstg ............................................ ,..... -65·C to 150·C
t stresses beyond thoee listed under "absolute maxlmum ratings· may cause permanent damage to the device. These ara stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions· Is not
Implied. Exposure to absolute-maxlmum·rated conditions for extended periods may affect device reliability. .
NOTE 1: All voltage values ara with respect to GNO.
recommended operating conditions
'27C01OA-10
'27C010A/PC010A-12
'27C010A/PC010A·15
'27C010A/PC010A-20
Vee
Supply
voltage
.Read mode (see Note 2)
Vpp
Supply
voltage
Read mode (see Note 3)
VIH
Hlgh·1eve1 de input voltage
VIL
Low·level de Input voltage
TA
Operating free-alr temperature
'27COI OA-_JL.,JL4
'27PC010A·__NL, FML., POL., OUL
TA
Operating free-air temperature
'27C010A·_JE,JE4
'27PC010A·__NE, FME, DOE, DUE
SNAPI Pulse programming algorithm
MIN
TYP
4.5
5
5.5
V
6.25
6.5
6.75
V
Vee +0.6
13.25
V
Vee-O•6
12.75
SNAPI Pulse programming algorithm
2
TIL
CMOS
TIL
CMOS
UNIT
Vee
13
MAX
Vee +0.5
Vee-0•2
-0.5
VCC+0.5
0.8
-0.5
GNO+0.2
V
V
V
0
70
·C
-40
85
·C
NOTES: 2. Vee must be applied before oratthe same time as Vppand removed afteroratthesametlmeas Vpp. The device must not be Inserted
Into or removed from the board when VPP or VCC Is applied.
3. During programming, VPP must be maintained at 13 V :t 0.25 V.
7·186
-!llExAs
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUS'T'ON. TEXAS 77251-1443
TMS27C010A 1048576-BIT UV ERASABLE PROGRAMMABLE
TMS27PC010A 1048576-BIT PROGRAMMABLE
READ·ONLY MEMORY
SMLS110B-NOVEMBER 1990-REVISEOJUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TEST CONDITIONS
MIN
10H .. - 20 j.IA
VOH
High-level de output voltage
VOL
Low-level dc output vollege
"
10
IPP1
IpP2
ICC1
Vcc supply current (stendby)
ICC2
Vcc supply current (active) (output open)
MAX
Vee-O•2
3.5
IOH=-2.5mA
UNIT
V
'OL=2.1 mA
0.4
0.1
Input current (Ieekage)
'OL" 20 j.IA
V, ",0 Vto 5.5 V
:01
j.IA
Output current (leakage)
Vo .. OVtoVee
:01
j.IA
Vpp supply current
Vpp
Vpp supply current (during program pulse)
LTTL-input level
Vpp" 13V
VCC .. 5.5V,
I CMOS-lnput level
Vec .. 5.5V,
VCC" 5.5 V,
E .. V,L
=Vee =5.5 V
V
10
j.IA
mA
E.V,H
50
500
E=vee:o O.2V
100
tcycle .. minimum cycle timet; .
30
j.IA
mA
outputs open
t Minimum cycle time = maximum access time.
capacitance over recommended ranges of supply voltage and operating free·alr temperature,
f= 1 MHz*
.
TYP§
MAX
e,
Input cspacHance
V, .. 0 V, ,. 1 MHz
4
8
pF
Co
Output cspacHance
VO"OV,f=1 MHz
6
10
pF
PARAMETER
*
TEST CONDITIONS .
MIN
UNIT
CepecHance meesurements era mede on semple beals only.
§ All typical values era at TA • 25°C and nominal volleges.
switching characteristics over recommended ranges of operating conditions (see Notes 4 and 5)
PARAMETER
TEST
CONDITIONS
'27C010A-10
MIN
MAX
'27C010A-12
'27PC010A-12
MIN
MAX
'27C010A-15
'27PC010A-15
MIN
MAX
'27C010A-20
'27PC010A-20
MIN
UNIT
MAX
talA)
talE)
Access time from addrass
100
120
150
200
ns
Access time from chip enable
100
120
150
200
ns
tan{Gl
Output enable time from G
Output disable time from G or
E, whichever occurs first'
55
55
75
75
ns
60
ns
idls
CL.100pF,
1 SerIes 74
TIL load,
Input tr " 20 ns,
Inputlf" 20 ns
0
50
0
50
0
60
0
Output data valid time after
chenge of addrass, E, or G,
0
0
0
0
ns
whichever occurs first'
Value calculatad from 0.5 V delta to meesurad output laval.
NOTES: 4. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements era made at 2 V for logic high end
0.6 V for logic low (reference AC testing waveform).
5. Common test conditions apply for idis except during programming.
tv(A)
-
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTCN, TEXAS 77251-1443
7-187
TMS27C010A 1048576-BI1 UV ERASABLE PROGRAMMABLE
TMS27PC010A 1048576-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS110B - NOVEMBER 11180- REVISED JUNE 1895
switching characteristics for programming: Vee = 6.5 V and Vpp = 13 V (SNAP I Pulse), TA = 25°C
(S88 Note 4)
tc:Ils(G)
PARAMETER
Olsable time, output disable time from G
teneG)
Enable time, output enilble time from G
UNIT
MIN
MAX
0
130
ns
150
ns
recommended timing requirements for programming: Vee = 6.5 V and Vpp = 13 V (SNAPI Pulse),
TA = 25°C, (see Note 4)
twCPGM)
Pulse duratlon, program
tsuCAl
tsu~a
Setup time, address
Setupttme, E
tsuCGI
tsu(D)
Setupttme,G
Setup time, data
tsuNPP}
Setup ttme, Vpp
tsuNCC)
Setup time, VCC
Hold time, address
ttJeA)
I SNAPI Pulse programming algorithm
MIN
TYP
MAX
95
100
105
2
2
2
2
2
2
0
.
UNIT
....
....
....
....
....
....
....
III
....
Hold time, data
2
ttJeO)
..
NOTE 4: For all switching characteristics the Input pulse levels are 0.4 V to 2.4 V. Timing measuraments are made at 2 V for logic high and
0.8 V for logic low (reference AC testing waveform).
~1ExAs
INSTRUMENTS
7-188
POST OFFICE BOX 1_ • HOUSTON, TexAS 772111-1_
TMS27C010A 1048576-BIT UV ERASABLE PROGRAMMABLE
TMS27PC010A 1048576-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS110B-NOVEMBER 1990-REVISEDJUNE 1995
PARAMETER MEASUREMENT INFORMATION
2.08 V
"""",,"=
----J
T':"
IlL· ... •
CL",1OOpF
(aa.NoteA)
NOTE A: CL Includes probe and fixture capacitance.
Figure 2. AC Test Output Load Circuit
AC testing Input/output wave forms
2.4¥~-","""""X
o.!~X...___
;.:v
¥~_-J
0.4
AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
AO-A1.
x
Add ..... Valid
I
14
ta(A)
\
E
I
\
DQO-DQ7
HJ.Z
I·
I
I
l...-"n(Q)~
«<<<<<<
Vi
VIH
vlL
I I
I I
II
I+--ta(E)~
0'
11
VIH
VIL
I
I
~I
I
I
I
I
X
VIH
1v(A)
vlL
I 14--1c118 ~
14
~
I
OutputYalld
»»»>}
HI-Z -
:::
Figure 3. Read-Cycle Timing
~TEXAS
INS1RUMENTS
POST OFFICE BOX 14-43 • HOUSTON, TEXAS 77251-14-43
7-189
TMS27C010A1 048578-BIT UV ERASABLE PROGRAMMABLE
TMS27PC010A 1048576-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS110B- NOVEMBER 1990- REVISED JUNE 1985
PROGRAMMING INFORMATION
1411111--Verlty ~
l0iii141---- Program --~~
AO-A18
==x
1
1
Aclclraea Stable
:
I
DQO-DQ7
Vpp
II1II- "'CAl ~
~ tau(D)
14---* IcfIa(G)t
1
1
--~~ .;-- )>---+---c(",*1
- - - ' "(
I
1
1
1
---'"1 I1
~tau(VeC)
~
I1
\:
1
tau(E)
ill
I
i4--*- taulA)
~tau(vpP)
Vee
X~_Ad..;N.;.d+;..ra:;...__
,
I
~
-,
vee
1
vee
1
r-
1
II
"'(0)
1411111--I~""""1 tau(G)
r ~
I
-------------------~I
1l1li
1
I
1
1
~ tan(G) tl
~
1
I r---------------
*t
tcIla(G) and ten(G) are characteristics of the device but must be accommodated by the programmer.
13-V VPP end I.SoV Vee for SNAPI Pulse programming.
Figure 4. Program-Cycle Timing (SNAPI Pulse Programming)
~TEXAS
7-190
Vpp
I11
I1
'----/1
I...
1
Iw(pGM)
?>-------
INSTRUMENTS
POST OFFICE BOX 1~ • HOUSTON, TEXAS 77251-1~
Vee*
TMS27C210A 1048576·BIT UV ERASABLE PROGRAMMABLE
TMS27PC210A 1048576·BIT PROGRAMMABLE
READ·ONLY MEMORY
SMLS31OC- NOVEMBER 1990 - REVISED JUNE
JPACKAGE
(TOP VIEW)
• Wlde·Word Organization ••• 64K )( 16
• Single 5-V Power Supply
• Operationally Compatible With Existing
Megabit EPROM.
• 4O-Pln Dual-In-Une Package and 44-Lead
Plastic Leaded Chip Carrier
• All Inputs/Outputs Fully TTL Compatible
• :1:10% Vee Tolerance
• Max Acce88/Min Cycle Time
'27C210A-10
'27C/PC210A-12
'27C/PC210A-15
'27C/PC210A-20
'27C/PC210A-25
100
120
150
200
250
ns
ns
ns
ns
ns
400 VCC
39
3
4
38U NC
37 A15
5
38~ A14
6
0011
0010
009
DaB
GNOt
7
n
35n A13
34~ A12
33D All
6
9
10
11
32
h A10
31
30
nGNOt
12
13
29
DQ4
14
15
27
26
DQ6
005
28
DQ3
16
25
002
17
24
oal
18
23
000 r
~ PGM
2
oa12
oa7
• 16-Blt Output For Use In
Microprocessor-Based Systems
• Very High-Speed SNAPI Pulse
Programming
• Power-Saving CMOS Technology
• 3-State Output Buffers
• 4OD-mV Minimum DC Noise Im",unity With
Standard TTL Loads
• Latchup Immunity of 250 mA on All Input
and Output Pins
• No Pullup Resistors Required
• Low Power Dissipation
- Active ••• 275 mW Worst Case
- Standby ••• 0.55 mW Worst Case
(CMOS-Input Levels)
• PEP4 Version Available With 168-Hour
v
1
VPP
EO
0015
0014
0013
19
22
G[20
21
AS
A8
A7
A8
A5
A4
A3
A2
Al
AO
FNPACKAGE
(TOP VIEW)
0r::E 1/,."
~:!:~
Q.
6
2 1 44 43 42 41 40
gg 8 1w ~~~!r~ < <
0012
0011
0010
009
ooa
5
4 3
0
39
38
9
37
36
11
35
VSS
NC
34
oa7
32
Burn-In and Choices of Operating
oae
Temperature Ranges
005
004
30
33
31
29
A13
A12
All
A10
AS
VSS
NC
A8
A7
AS
AS
description
The TMS27C210A series are 1048576-bit,
ultraviolet-light erasable, electrically programmable read-only memories.
The TMS27PC210A series are 1048576-bit,
one-time electrically programmable read-only
memories.
PIN NOMENCLATURE
AO-A15
Address Inputs
000-0015 Inputs (programmlng)/Outputs
EO
Chip Enable
G
Output Enable
GNO
Ground
NC
No Internal Connection
PGM
Program
VCC
s-V Power Supply
VPP
13·VPowerSupply*
*t
Pins 11 and 30 must ba connected externally to ground.
Only In program mode.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXA877251-1443
Copyright 01995, Texas Instruments Incorporated
7-191
TMS27C210A 1048576-BIT UV ERASABLE PROGRAMMABLE
TMS27PC210A 1048576-BIT PROGRAMMABLE
READ-ONLY MEMORY
/
SMLS31OC- NOVEMBER 1810- REVISED JUNE 1995
description (continued)
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (inciuding program data inputs) can be driven by Series 74 TtL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C210A EPROM Is offered in a dual-In-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mi~ centers. The TMS27C21OA Is also offered with two choices of
temperature ranges, O°C to 70°C (JL suffix) and - 40°C to 85°C (JE SuffIX). The TMS27C21 OA is also offered
with 168-hour bum-in on both temperature ranges (JL4 and JE4 suffixes).
.
The TMS27PC21OA OTP PROM is offered in a 44-pin plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing (FN suffix). The TMS27PC21OA is offered with two choices of temperature ranges,
. O°C to 70°C (FNL suffix) and -40°C to 85°C (FNE suffix). The TMS27PC21OA Is also offered with 168 hour
bum-in on both temperature ranges (FNL4 and FNE4 suffixes). (See table below.)
EPROM
AND
OTPPROM
·TMS27C210A-xx
TMS27PC210A-xx
SUFFIX FOR PEP4
168 HOUR BURN-IN
VS TEMPERATURE RANGES
SUFFIX .FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN-IN
O°Cto 700C
JL
FNL
- 40°C to 85°C
JE
FNE
O°Cto70OC
JL4
FNL4
- 40°C to 850C
JE4
FNE4
These EPROMs and OTP PROMs operate from a single 5-V supply (In the read mode), they are Ideal for use
In microprocessor based systems. One other (13 V) supply is needed for programming. All programming signals
are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation·
The seven modes of operation for the TMS27C21 OA and TMS27PC210A are listed in the following table. The
read mode requires a single 5-V supply. All inputs are TTLievel except for Vpp during programming (13 V), and
12 V on A9 for signature mode.
MODEt
FUNCTION
E
G"
READ
VIL
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
VIL
VIL
VIH
Vpp
PROGRAM
INHIBIT
SIGNATURE MODE
VIL
VIH
X
VIH
X
J5(3M
VIL
X
Vpp
VCC
Vee
Vee
VIL
VIH
VIL
Vpp
Vee
AS
VCC
VCC
Vee
Vee
x
Vee
X
x
x
x
VCC
X
AD
X
X
X
X
X
X
VH*
VIL
DQO-DQ16
Data Out
HI-2
HI-Z
Data In
Data Out
HI-Z
MFG
X
VIH
X
X
VIL
X
VIL
Vpp
Vee
Vee
I
VH*
VIH
I
CODE
97
t X can be VIL or VIH.
* VH • 12V:l:O.6V.
~1ExAs
7-192
INSTRUMENTS
POSTOFFIOE BOX 1443 • HOUSTON. 'I'EXAE! 77251-1443
I
I
DEVICE
AB
TMS27C210A 1048576·BIT UV ERASABLE PROGRAMMABLE
TMS27PC210A 1048576-BIT PROGRAMMABLE
READ·ONLY MEMORY
SMLS31OC- NOVEMBER 1990 - REVISED JUNE 1995
read/output disable
When the outputs of two or more TMS27C21 OAs or TMS27PC21 OAs are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from c0.!!lpeti~ outputs of the
other devices. To read the output of a single device, a low le"el signal is applied to the E and G pins. All other
devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.
latchup Immunity
Latchup immunity on the TMS27C21 OA and TMS27PC21 OA is a minimum of 2S0 rnA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients atthe P.C. board level when the EPROM
is interfaced to industry standard TIL or MOS logic devices. The inputloutput layout approach controls latchup
without compromising performance or packing density.
For more information see application report SMLA001, "Design Considerations; Latchup Immunity of the
HVCMOS EPROM FamilY'. available through TI Sales Offices.
power down
Active lee supply current can be reduced from SO rnA to SOO jJA by applying a high TTL input on E and to
100 jJA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state .
• rasure (TMS27C210A)
Before programming. the TMS27C210A is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 A). The recommended minimum exposure dose (UV intensity x
exposure time) is 1S-W·s/cm2. A typical 12-mWIcm 2 • filterless UV lamp erases the device in 21 minutes. The
lamp should be located about 2.5 cm above the chip during erasure. After erasure. all bits are in the high state.
It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore. when using
the TMS27C21 OA the window should be covered with an opaque label.
Initializing (TMS27PC210A)
The one-time programmable TMS27PC21OA PROM is provided with all bits in the logic high state. then logic
lows are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAPI Pulse programming
The TMS27C210A and TMS27PC210A are programmed using the TI SNAPI Pulse programming algorithm
Illustrated by the flowchart in Figure 1. which can program In a nominal time of seven seconds. Actual
programming time varies as a function of the programmer used.
The SNAPI Pulse programming algorithm uses an initial pulse of 100 microseconds (jAS) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-jAS
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when Vpp = 13 V. Vee = 6.S V. E= VIL. G= VIH. Data is presented in parallel
(16 bits) on pins oao through OQ1S. Once addresses and data are stable. PGM is pulsed low.
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAPI Pulse programming routine is complete, all bits are verified with
Vee = Vpp = 5 V:i: 10%.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 772151-1443
7-193
TMS27C210A 104857~BIT UV ERASABLE PROGRAMMABLE
TMS27PC210A 104857~BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS31OC- NOVEMBER 1990- REVISED JUNE 1995
program Inhibit
Programming can be inhibited by maintaining a high level input on the E or PGM pins.
program verify
Programmed bits can be verified with Vpp
=13 V when G =VIL, E =VIL, and PGM =VIH.
signature mode
The Signature mode provides access to a binary code Identifying the manufacturer and type. This mode is
activated when AS is forced to 12 V. Two Identifier bytes are accessed by toggling AO. OQO-OQ7 contain the
valid codes. All other addresses must be held low. The signature code for these devices Is 97AB. AO low selects
the manufacturer's code 97 (Hex), and AO high selects the device code AB (Hex), as shown by the signature
mode table below.
IDENTIFIERT
PINS
007
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
Dao
MANUFACTURER CODE
VIL
1
0
0
1
0
1
1
1
97
DEVICE CODE
VIH
1
0
1
0
1
0
1
1
AS
tEz G "VIL, AS =VH,A1-AS =VIL.A10-A15=VILo Vpp = Vee. PGM =VIH orVIL.
~TEXAS
7-194
HEX
AO
INSTRUMENTS
POST OFFICE BOX 14<13 • HOUSTON. TEXAS 77251-14<13
TMS27C210A 1048576-BIT UV ERASABLE PROGRAMMABLE
TMS27PC210A 1048576·BIT PROGRAMMABLE
READ·ONLY MEMORY
SMlS31OC- NOVEMBER 1990 - REVISED JUNE 1995
l
Progrem
Mode
Increment Add,...
Increment
Add,...
Interectlve
Mode
No
Ve.
Device Failed
Final
3'
Figure 1. SNAPI Pulse Programming Flowchart
~TEXAS
INSTRUMENTS
POST ot=;FICE BOX 14043 • HOUSTON, 'lE A85~
29
31
32
33
34
36
36
37
15
-
2
I
20
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
19
18
17
16
15
14
13
12
10
9
8
7
6
5
4
3
DQO
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
D09
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
(PWRDWN]
J-....
.....
&:
EN
tThis symbol Is In accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
absolute maximum ratings over operating free..lr temperature range (unless otherwise noted)*
*
Supply voltage range, Vee (see Note 1) .......................•............•....••..• -0.6 V to 7 V
Supply voltage range, Vpp ......................................................... -0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 ........................... -0.6 V to Vee + 1 V
A9 .......................•....................... -0.6 Vto 13.5 V
Output voltage range (see Note 1) ..• • . . . • . • . . . • . . . . • . . . . . • . • . . . . . • . . . . . • . . . .. -0.6 V to Vee + 1 V
Operating free-air temperature range ('27C21 OA-__JL and JL4, '27PC210A-__FNL) .• • . .. O· C to 70·C
Operating free-air temperature range ('27C21 OA-__JE and JE4) ..•.....•.....•....•.. - 40· C to 85·C
Storage temperature range, Tstg ...............••...•.....•..........•.....•.....• -65·C to 150·C
Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliabHIty.
NOTE 1: All voltage values are with respect to GND.
~1ExAs
7-198
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON.1l:XAS 77251-1443
TMS27C210A 1048576-BIT UV ERASABLE PROGRAMMABLE
TMS27PC210A 1048576-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS31OC- NOVEMBER 1990 - REVISED JUNE 1995
recommended operating conditions
TMS27C21OA-10
TMS27C/PC210A-12
TMS27C/PC210A-15
TMS27C/PC210A-20
TMS27C/PC210A-25
UNIT
MIN
NOM
4.5
5
5.5
8.25
6.5
6.75
Read mode (see Note 2)
MAX
Vcc
Supply voltage
VPP
Supply voltage
VIH
High-level de input voltage
VIL
Low-level de Input voltage
TA
Operating free-alr temperature
'27C210A-__JL, JL4
'27PC21OA-__FNL
0
70
·C
TA
Operating free-alr temperature
'270210A-__JE. JE4
-40
85
·C
SNAPI Pulee programming algorithm
Read mode
VCC-0•6
SNAPI Pulse programming algorithm
Vee
12.75
TTl
VCC+0.6
13
2
CMOS
V
13.25
VCC+0.5
Vcc-O.2
V
V
Vee+0•5
TTL
-0.5
0.8
CMOS
-0.5
GNO+0.2
V
NOTE 2: Vee muat be applied before oratthe same time as Vpp and removed after or at the same time as Vpp. The device must not be Inserted
Into or removed from the board when Vpp or VCC Is applied.
electrical characteristics over recommended ranges of operating conditions
PARAMETER
VOH
VOL
TEST CONDITIONS
High-level dc output voltage
t...Ow-leveI de output voltage
Vee- 0•2
IOH=-2mA
2.4
IOL-2.1 mA
0.1
:1:1
10
IlA
IlA
IlA
50
mA
:1:1
Input current Oeakage)
Output current (leakage)
IpP1
Vpp supply current
Vo·OVtoVee
Vpp.Vee -5.5V
IpP2
Vpp supply current (during progrem pulee)
Vpp.13V
Vee supply current (stendby)
IC02 Vee supply current (active)
..
MInimum cycle time
.
V
10L=20\IA
VI-OVto5.5V
II
ICC1
UNIT
0.4
10
ITTl-input level
I CMOS-input level
MAX
MIN
10H --20\IA
V
VCC-5.5V,
E.VIH
500
VCC=5.5V,
E"Vee
100
IlA
VCC-5.5V,
E.VIL••
tcycle .. minimum cycle time.
outputs open t
50
mA
maxImum address access time.
capacitance over recommended
temperature, f 1 MHz*
=
ranges
of
supply voltage
and
operating
free..lr
TVPt
MAX
CI
Input capacitance
VI-OV,
f.1 MHz
8
12
pF
Co
Output capacitance
Vo .. OV.
too 1 MHz
12
15
pF
PARAMETER
*t
TEST CONDITIONS
MIN
UNIT
Capacitance m_urements are made on a sample basis only.
'JYpicaI valuas are at TA .. 25·C and nominal voltages.
~TEXAS
INSTRUMENTS
POST OFFICe BOX 1443 • HOUSTON. TEXAS 772s1-1443
7-197
TMS27C210A 1048576-BIT UV ERASABLE PROGRAMMABLE
TMS27PC210A 1048576-BIT PROGRAMMABLE
READ-ONLY MEMORY·
SMLS310C - NOVEMBER 1990 - REVISED JUNE 1996
switching characteristics over full ranges of recommended operating conditions (see Notes 3
.and 4)
PARAMETER
'27C210A-10
TEST
CONDITIONS
MIN
MAX
'27C210A-12 '27C210A-111 '27C210A-20 '27C210A-25
'27PC210A-12 '27PC210A-1II '27PC210A-20 '27PC210A-25
MIN
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
ta(A)
Access time from
address
100
120
150
200
250
ns
talE)
Access time from
chlpeneble
100
120
150
200
250
ns
55
55
75
75
100
ns
80
ns
Output enable
ten(G) tlmefromG
ldls
Output disable
time from GorE,
whichever occurs
firstt
Cl .. lOOpF,
1 Series 74
TTL load,
Input tr " 20 ns,
Input tf " 20 ns
0
50
0
50
0
60
0
0
60
Output data valid
time after change
of address, E, or
ns
0
0
0
0
0
tv(A)
G, whichever
occurs flrstt
t Value calculated from 0.5 V delta to measured level. This parameter Is only sampled and not 100% tested.
NOTES: 3. For ell switching characteristics the Input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (reference AC testing waveform)
4. Common test conditions apply for ldis except during progremming.
switching characteristics for programming: Vee
(see Note 3)
=6_5 V and Vpp =13 V (SNAPI Pulse). TA =25°C
PARAMETER
ldls(G)
Output disable time from G
tenJGl
Output enable time from G
MIN
MAX
UNIT
0
100
150
n8
ns
recommended timing requirements for programming: Vee = 6.5 V and Vpp = 13 V (SNAPI Pulse).
TA 2SoC. (see Note 3)
=
tw(PGM)
Purse duration, program
tsuJAl
tsulEl
tsu(G)
Setup time, address
tsu(D)
Setup time, data
I SNAPI Pulse programming algorithm
Setup time, E
Setup time, G
Setup time, Vpp
MIN
TVP
MAX
UNIT
95
2
2
2
2
100
105
lIS
lIS
1'8
lIS
lIS
lIS
2
2
lIS
0
lIS
Hold time, data
2
lIS
!hiD)
..
NOTE 3: For ell switching characteriStICS the Input pulse levels are 0.4 V to .2.4 V. Timing measurements are made at 2 V for logre high and
0.8 V for logic low. (reference AC testing waveform)
tsulVPPI
tsuNCC)
theA)
Setup time, VCC
Hold time, address
~1ExAs
7-198
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS27C210A 1.048576-BIT UV ERASABLE PROGRAMMABLE
TMS27PC210A 1048576-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMlS310C - NOVEMBER 1990 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
2.08 V
Output
Under Teat
----t
T":'
RL" 800 Q
CL-100pF
,se.NoteA)
NOTE A: CL includes probe and fixture capacitance.
Figure 2. AC Testing Output Load Circuit
AC testing Input/output wave forms
2.4Y----v
--JA :.:v
0.4 y _ _ _
AC testing Inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
AO-A16
=x--------------OI!I --------~------_ .
X
Add_ valid
vlH
VIL
I
\
V!"",- - - - - ----------'l!1 I
I I
VIL
"'1
14-- "(E) ----+il
- ----+0---""'\
\
14I'0IIIf---- talA)
DQO-DQ15
HI-Z
I ,1-- - - - - - v
I
: . - ten(G)
~
~!yeA)
---<((««<<
VIH
rC
~ I.I'"
Output valid
tells
»»»>}
.1
v::
~
I
HI-Z -
:::
Figure 3. Read-Cycle Timing
-!!11ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
7·199
TMS27C210A 1048576-BIT UV ERASABLE PROGRAMMABLE
TMS27PC210A 1048576-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS31OC- NOVEMBER 1880 - REVISED JUNE 1995
PROGRAMMING INFORMATION
I+-- Verify -----'.~I
I
1IIIIIl'41----prollram ---.~I
AO-A115
-v'
---f\.
AcId ..... Stable
I
:
1+ ..,~
I.--.r .u(A)
DQO-DQ115
---<~
---.A
---.A
1I4---+t;
I
I
I
I
I
I
I
\.
I
I
I
.u(VCC)
.1
I
I' 1
I
I
I
1
I
~ tt.(O)
1
~~~I~-~~-~I
tw(pGM)
-,
~
...1
I
..
I
I
---1----------
11114'--.....*"1-+1 '-u(G) I
I I
I
\[ .I.n(:/
1
*t
tclls(G) and ten(G) are characteristics of the device but must be accommodated by the programmer.
13-V Vpp and B.S-V Vee for SNAPI Pulse prz<
o
AS
A4
A3
A2
A1
AO
000
• No Pullup Resistors Required
• Low Power Dissipation (Vee = 5.5 V)
- Active ••• 165 mW Worst Case
- Standby ••• 0.55 mW Worst Case
(CMOS-Input Levels)
• PEP4 Version Available With 16B-Hour
Burn-In. and Choices of Operating
.
Temperature Ranges
A14
A13
AS
AS
A11
G
A10
E
21
OQ7
description
The TMS27C020 series are 2097152-bit, ultraviolet-light erasable, electrically programmable
read-only memories.
AO-A17
000-007
E
G
The TMS27PC020 series are one-time electrically programmable read-only memories.
These devices are fabricated using power-saving
CMOS technology for high speed and simple
Interface with MOS and bipolar circuits. All inputs
(including program data inputs) can be driven by
Series 74 TTL circuits without the use of external
pull up resistors. Each output can drive one Series
74 TTL circuit without external resistors.
PIIODUCTIOII
DATA
_ _ _10por..........
IIIIiIIIIIIIan dolo.
__
"' _
... _
.. 1'IxUlMtRi..-
-"'!IfIIIIII.-...-.. - .... -....,...................
GNO
PGM
Vee
Vpp
Address Inputs
Inputs (programming)/Outputs
Chip Enable
Output Enable
Ground
Program
S·V Power Supply
13·V Power Supply
*
t The ADVANCE INFORMATION notice applies 10 this package.
*
Only in program mode.
~TEXAs
INSTRUMENTS
POST OFFICE BOX 14013 • HOUSTON. TEXAS 77251-14013
Copyright C , 995. Texas Instruments Incorporated
7-201
TMS27C020 2097152·BIT UV ERASABLE PROGRAMMABLE
TMS27PC020 2097152·BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS020B- NOVEMBER 1880 - REVISED JUNE 1885
description (continued)
The TMS27C020 EPROM is offered In a dual-In-line ceramic package (J suffix) designed for Insertion In
mounting hole rows on 15,2-mm (SOO-mil) centers. The TMS27C020 is also offered with two choices of
temperature ranges of 0° to 70°C (JL suffix) and - 40°C to 85°C (JE suffix). The TMS27C020 Is also offered
with 168-hour bum-in on both temperature ranges (JL4 and JE4 suffixes). (See table belOw.)
The TMS27PC020 is offered in a 32-lead plastic leaded chip carrier using 1,25 mm (50 mil) lead spacing
(FM SuffIX). The TMS27PC020 is offered with a temperature range of O°C to 70°C.
SUFFIX FOR PEP4168 HR. BURN.IN
VS. TEMPERATURE RANGES
SUFFIX FOR OPERATING TEMPERATURE
RANGES wrntOUT PEP4 BURN·IN
EPROM
0'eto70'e
- 4O'e to 85'e
0'eto70'e
- 4O'e to 85'e
TMS27C020-XXX
JL
JE
JL4
JE4
TMS27PC020-XXX
FML
These EPROMs operate from a single 5-V supply (in the read mode), they are ideal for use in
microprocessor·based systems. One other (13 V) supply Is needed for programming. All programming signals
are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The seven modes of operation for the TMS27C020 and TMS27PC020 are listed in the following table. The read
mode requires a single 5-V supply. All inputs are TTL level except for Vpp during programming (13 V), and VH
(12 V) on A9 for the signature mode.
MODEt
FUNCTION
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE MODE
E
(I
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
VIH
VIL
X
x
Vpp
Vee
Vee
Vee
VIL
Vpp
VIH
Vpp
X
X
VIL
PC____________M
__d_~__S~~-*----------~:~1<~-._M~:~:-~1___
~ teu(A)
DQO-DQ7
---<~
of--
I+-
)>----I---«"t fJo-·-.------
~ leuCD)
Vpp
1+--* tclla(G)t
I
I
I
I
I
I
- - ";
I
"'Z-+-I--«
1 tsn(G) 1 1
J+---+t- tsu(D)
*" 1>------1
,
.:
,I I
.1
1ci18(G)
Vpp
Vcc
vppt
Vcc
~~tsU(E)
"
l+--M-atsu(vCC)1
-----~
I
tw(PGM)
I
-l+--+I
i
1
l+-+f-
I
I
I
I
ltt(D)
I
I
I
114111----1.~1-+--
I
I
vcct
Vcc
1
tsu(G)
I
/r----
~JIO--_ _
VIH
t 13-V VPP and 6.5-V Vee for SNAPI Pulse programming
Figure 4. Program-Cycle liming (SNAPI Pulse Programming)
~1ExAs
INSIRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
7-219
TMS27C04O 4194304-BIT UVERASABLE PROGRAMMABLE
TMS27PC04O 4194304-BIT PROGRAMMABLE
READ~NLY MEMORY
SMLS04OE- NOVEMBER 1890 - REVISED JUNE 1995
~1ExAs
7-220
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 7721i1-1443
TMS27C240 4194304-BIT UV ERASABLE PROGRAMMABLE
TMS27PC240 4194304·BIT PROGRAMMABLE
READ·ONLY MEMORY
•
•
•
•
•
Wide-Word Organization ••• 256K )( 16
Single 5-V Power Supply
All Inputs/Outputs Fully TIL Compatible
Static Operations (No Clocks, No Refresh)
Max Access/Min Cycle Time
Vee z 10%
'27C/PC240-10
100 ns
'27C/PC240-12
120 ns
'27C/PC240-15
150 ns
TMS27C240 J PACKAGE
(TOP VIEW)
Vpp
E
DQ15
DQ14
0013
0012
0011
0010
DQ9
• 16-Blt Output For Use In
Microprocessor-Based Systems
• Very High Speed SNAPI Pulse
Programming
oae
GNO*
007
DQ8
005
DQ4
000
002
DQl
000
• Power-Saving CMOS Technology
• 3-State Output Buffers
• 4OO-mV Minimum DC Noise Immunity With
Standard TTL Loads
• Latchup Immunity of 250 mA on All Input
and Output Unes
G
• No Pull up Resistors Required
• Low Power Dissipation (Vee = 5.5 V)
- Active ••• 275 mW Worst Case
- Standby ••• 0.55 mW Worst Case
(CMOS-Input Levels)
• PEP4 Version Available With 168-Hour
Burn-In, .nd Choices of Operating
Temperature Ranges
Vee
A17
A18
A15
A14
A13
A12
A11
A10
1
2
3
4
5
8
7
8
9
10
11
12
13
14
15
18
17
18
19
20
A9
GNO*
AS
A7
AS
AS
25 A4
24 A3
23 A2
22 Al
AO
21
TMS27PC240 FN PACKAGE
(TOP VIEW)
"'
...........
.... ",
g g glw
6 5 4 3
0012
0011
0010
:( :( :(lI).:(
8 ...
~
:e-~>
co
2 1 44 43 42 41 40
0
9
DQ9
oae
description
GNO*
NC
007
The TMS27C240 series are 4194304-bit, ultraviolet-light erasable, electrically programmable
read-only memories.
32
DQ8
31
30
29
005
DQ4
The TMS27PC240 series are 4194304-bit,
one-time electrically programmable read-only
memories.
39
36
37
36
35
34
33
A13
A12
Al1
Al0
A9
GNOt
NC
AS
A7
AS
AS
18 19 20 21 22 23 24 25 26 27 28
ggg§I~ ~ a!:( ~ ~ ~
These devices are fabricated using power-saving
CMOS technology for high speed and simple
interface with MOS and bipolar circuits. All inputs
(including program data inputs) can be driven by
Series 74 TTL circuits without the use of external
pull-up resistors. Each output can drive one
Series 74 TTL circuit without external resistors.
PIN NOMENCLATURE
AO-A17
Address Inputs
000-0015 Inputs (programming)/Outputs
E
Chip Enable
Output Enable
G
GNO
Ground
NC
No Connection
5-VSupply
Vee
13-V Power Supply*
Vpp
$
.*
011. 11 and 30 (J package) and pins 12 and 34 (FN package) must
connected externally to ground•
In program mode
Iv\
)
~1ExAs
INSTRUMENTS
POST PFFICE BOX 1443 • HOU81ON, TEXAS 77261-1443
CopyrIght 0 1985, Texas Instrumlln1B Incorpora1lld
7-221
TMS27C240 4194304-BIT UV ERASABLE PROGRAMMABLE
TMS27PC240 4194304-BIT PROGRAMMABLE
READ-ONLY MEMORY
SML.S24OC - NOVEMBER 1890 - REVISED JUNE 1995
description (continued)
The TMS27C240 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (60o-mll) centers. The TMS27C240 Is also offered with two choices of
temperature ranges of O·C to 70·C (JL suffix) and - 4O·C to 85·C (JE suffix). The TMS27C240 is also offered
with 168-hour burn-In on both temperature ranges (JL4 and JE4 suffb(es). (See table below.)
The TMS27PC240 OTP PROM is offered in a 44-lead plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing (FN suffix). The TMS27PC240 is characterized for a temperature range of O·C to 70·C.
SUFFIX FOR PEP4
168 HR. BURN-IN
VB TEMPERATURE RANGES
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN-IN
o·cTO 7o·e
;" 4O·C TO 85·e
o·eT07o·e
TMS27C240-XXX
JL
JE
JL4
JE4
TMS27pe240-XXX
FNL
FNE
N/A
N/A
- 4O·e TO 85·e
These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), and they are ideal for
use In microprocessor-based systems. One other (13 V) supply is needed for programming. All programming
signals are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The eight modes of operation for the TMS27C240 and TMS27PC240 are listed In the following table. The read
mode requires a Single 5-V supply. All Inputs are TTL level except for Vpp during programming (13 V for SNAPI
Pulse), and 12 V on A9 for the signature mode.
FUNCTIONt
E
G
vPP
vee
AS
AO
1/0
x
x
x
DQO-DQ7
DQ8-DQ15
VIL
VIL
Vee
Vee
Output Disable
VIL
VIH
Vee
Vee
Standby
VIH
X
Vee
Programming
VIL
VIH
Vee
Vpp
x
x
x
Vee
X
X
Data In
Verify
VIH
VIL
Vpp
Vee
X
X
Data Out
VIH
Vpp
Vee
X
X
Hi-Z
Read
Program Inhibit
VIH
Hi-Z
HI-Z
Signature Mode (Mfg)
VIL
VIL
Vee
Vee
VH*
VIL
MfgCode
0097
Signature Mode (Device)
VIL
VIL
Vee
Vee
VH*
VIH
Device Code
0030
t X can be VIL or VIH.
*VH -12VzO.5V.
read/output, disable
When 'the outputs of two or more TMS27C240s or TMS27PC240s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no Interference from the coE1peti~ outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level Signal to one of these
pins.
~1ExAs
7-222
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lEXAS 77261-1443
TMS27C240 4194304-BIT UV ERASABLE PROGRAMMABLE
TMS27PC240 4194304-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS240C- NOVEMBER 1990 - REVISED JUNE 1995
latchup Immunity
Latchup immunity on the TMS27C240 and TMS27PC240 is a minimum of 250 rnA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients atthe P.C. board level when the devices
are Interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latch up
without compromising performance or packing density.
power down
Active ICC supply current can be reduced from 50 mA to 1 rnA by applying a high TTL input on E and to
100 t.IA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure (TMS27C240)
Before programming, the TMS27C240 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 A). The recommended minimum exposure dose (UV intensity x·
exposure time) is 15-W·s/cm2. A 12-mWIcm 2 , filteriess UV lamp erases the device in 21 minutes. The iamp
should be located about 2.5 em above the chip during erasure. After erasure, all bits are in the high state. It
should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using
the TMS27C240, the window should be covered with an opaque label.
Initializing (TMS27PC240)
The one-time programmable TMS27PC240 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased •
. SNAPI Pulse programming
The TMS27C240 and TMS27PC240 are programmed by using the SNAPI Pulse programming algorithm. The
programming sequence is shown in the SNAPI Pulse programming flow chart, see Figure 1.
The initial setup is Vpp = 13 V, Vee = 6.5 V, E = VIH, and G = VIH. Once the initial location is selected, the data
is presented in parallel (eight bits) on pins OQO through OQ15. Once addresses and data are stable, the
programming mode is achieved when E is pulsed low (VII) with a pulse duration oftw(PGM)' Every location is
programmed only once before going to interactive mode.
In the interactive mode, the word is verified atVpp = 13V, Vee = 6.5 V, E =VIH, andG = VIL.lfthe correct data
is not read, the programming is performed by pulling E low with a pulse duration of tw(PGM)' This sequence of
verification and programming is performed up to a maximum of 10 times. When the device is fully programmed,
all bytes are verified with Vee = VPP = 5 V:I: 10%.'
program Inhibit
Programming can be inhibited by maintaining a high level input on the E and G pins.
program verify
Programmed bits can be verified with Vpp = 13 V when G = VIL and E = VIH.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
7-223
TMS27C240 4194304-BIT UV ERASABLE PROGRAMMABLE
TMS27PC240 4194304·BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS240C - NOVEMBER 1990- REVISED JUNE 1995
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode Is
activated when fJ.S (pin 31 for the J package) is forced to 12 V. Two identifier bytes are accessed by toggling
AO. OQO-DQ7 contain the valid codes. All other addresses must be held low. The signature code for these
devices is 9730. AO low selects the manufacturer's code 97 (Hex), and AO high selects the device code 30
(Hex), as shown by the signature mode table below.
PINS
IDENTlFlERt
AO
DQ7'
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQO
HEX
MANUFACTURER CODE
VIL
1
0
0
1
0
1
1
1
'97
DEVICE CODE
VIH
0
0
1
1
0
0
0
0
30
, t E. (3' = VIL, AS. VH, Al-AS = VIL, A10-A17 =Vllo Vpp =Vee, PGM =VIH or VIL.
~1ExAs
INSTRUMENTS
7-224
POST OFFICE BOX 1_ • HOUSTON, 1EXAS 77251-1_
TMS27C240 4194304-BIT UV ERASABLE PROGRAMMABLE
TMS27PC240 4194304-BIT PROGRAMMABLE
READ·ONLY MEMORY
SMLS24OC- NOVEMBER 1990 - REVISED JUNE 1995
Program
Mode
Incrament Addraea
Interactive
Mode
No
Final
~Figure 1. SNAP I Pulll Programming Flowchart
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • H9UST0N. TEXAS 77251-1443
7-225
TMS27C2404194304-BIT UV ERASABLE PROGRAMMABLE
TMS27PC240 4194304·BIT PROGRAMMABLE
READ·ONLY MEMORY
SMLS24OC- NOVEMBER 1980- REVISED JUNE 19\15
logic symbol t
EPROM 256K x 16
AO
A1
A2
A3
A4
AS
AS
A7
AS
AI
A10
A11
A12
A13
A14
A15
A16
A17
21
0'
22
23
24
25
28
27
28
0
>A 262143
29.
31
32
33
34
35
36
37
38
39
19
18
17
18
15
14
13
12
10
9
8
7
,
6
5
4
3
DOG
DQ1
DQ2
003
004
DQ5
006
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
17
2
I
20
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
[PWRDWNJ
r-..
r-..
It
EN
tThese symbols are in .accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers are for the J package.
. absolute maximum ratings over operating tree..lr temperature range (unless otherwise noted)*
*
Supply voltage range, Vee (see Note 1) ....................................•..•.•..•. -0.6 V to 7 V
Supply voltage range, Vpp •.••••..•••••.•..••..•••••.•••...•....•..•..•....••..•••. -0.6 V to 13 V
Input voltage range (see Note 1): All inputs except A9 ....... • . . . • . • . . . . . . . • • . • .• -0.6 V to Vee + 1 V
A9 ............................................... -0.6Vto 1.3.5 V
Output voltage range (see Note 1) ...................•..•.•.....•.......••.•.• -0.6 V to Vee + 1 V
Operating free-air temperature range ('27C24D-__JL and JL4,
'27PC24O-_ ]NL) ......................•.••.•...• 0° C to 70° C
Operating free-air temperature range ('27C240-__JE and JE4) .....................•. - 40° C to 85° C
Storage temperature range, Tstg .........................................•.•.••.•. -65°C to 150° C
StressH beyond thoee listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" Is not
Implied. Expoeura to absolute-maxlmum-rated conditions for extended periods may affect devioe rallability.
NOTE 1: All voltage values are with raepect to GND.
~TEXAS
7-226
INSTRUMENTS
POBTOFFICE BOX 1+13· HOUSTON, TEXAS 77251-1+13
TMS27C240 4194304-BIT UV ERASABLE PROGRAMMABLE
TMS27PC240 4194304-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS2<1OC- NOVEMBER 1990 - REVISED JUNE 1995
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
6.25
6.5
6.75
VCC- o.e
12.75
13
VCC+0.6
13.25
Read mode (see Note 2)
VCC
Supply voltage
VPP
Supply voltage
VIH
High-level de Input voltage
VIL
Low-level de Input voltage
TA
Operating free..aJr temperature
TA
Operating free.aJr temperature
SNAPI Pulse programming algorithm
Read mode
SNAPI Pulse programming algorithm
TTL
2
CMOS
UNIT
V
VCC+0.5
V
V
VCC-0.2
-0.5
VCC+D·5
0.8
CMOS
'27C24O-__JL, JL4
'27PC24OFNL
-0.5
0.2
0
70
·C
'27C24O-__JE, JE4
-40
85
·C
TTL
-
V
NOTE 2: Vcc must be applied before or stthe same lime as VPP and removed after or stthe same time as Vpp. The device must not be Inserted
Into or removed from the board when Vpp or VCC is applied.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
VOH
High-level de output voltage
VOL
Low-level de output voltage
TEST CONDITIONS
*1
i'A
i'A
Vpp =VCC-5.5V
*1
10
Vpp= 13V
50
i'A
mA
Input current (leakage)
Output current Oeakage)
VO=OVtoVCC
IpP1
Vpp supply current
IC02 VCC supply current (active)
capacitance over recommended
temperature, f = 1 MHzt
ranges
V
VCC- 0•1
0.1
II
VCC supply current (standby)
UNIT
0.4
10
IpP2 Vpp supply current (during program pulse)
MAX
2.4
IOL-2.1 mA
10L-20i'A
VI" OVI05.5V
ICC1
MIN
10H - - 400 i'A
10H =-20i'A
V
VCC .. 5.5V,
E:-VIH
1
mA
VCC=5.5V,
E=VCC
100
i'A
VCC .. 5•5V,
E=VII..
Icycle .. minimum cycle time,
outputs open
50
mA
of
supply
voltage
and
operating
free-air
TYP*
MAX
OJ
Input capacitance
VI"OV
4
B
pF
Co
Output capacitance
VO-OV
8
12
pF
PARAMETER
TEST CONDITIONS
MIN
UNIT
*t
Capacitance measurements are made on a eample basis only.
Typical values are at TA .. 25·C and nominal voltages.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
7-227
TMS27C240 4194304-BIT UV ERASABLE PROGRAMMABLE
TMS27PC240 4194304-BI1 PROGRAMMABLE
READ-ONLY MEMORY
,
SMlS24OC- NOVEMBER 1990- REVISED JUNE 1995
switching characteristics over recommended ranges of operating conditions (see Notes 3
and 4)
TEST CONDmONS
PARAMETER
'210240-10
'27P024O-10
MIN
ta(A)
Access lime from address
talE)
Access lime from chip' enable
ten(G)
Output enable lime from G
tells
CL-1oopF,
1 SerIes 74
Output disable time from GorE, whichever
occurs flrstt
'27C24O-12
'27PC24O-12
120
100
120
150
ns
50
60
50
ns
50
ns
MAX
MIN
UNIT
MAX
150
MAX
100
MIN
'27C240-15
'27PC24O-15
ns
TIL load,
Input tr .: 20 lIS,
Input tf .: 20 ns
0
50
0
50
0
Output data valid lime after change of
0
0
0
ns
address, E, or G, whichever occurs flrstt
t Value calculated from 0.5 V delta to measurad level. This psrameter Is only sampled and not 100% tested.
NOTES: 3. For all switching characteristics the Input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (reference AC Testing Wave Form)
4. Common test conditions apply for tel!s except during programming.
ty(A)
switching characteristics for programming: Vee = 6.5 V and Vpp = 13 V (SNAPI Pulse). TA = 25°C
(see Note 3)
MIN
PARAMETER
tells(G)
ten(Gl
Output ,disable time from G
Output _ble lime from G
0
MAX
100
160
UNIT
ns
ns
recommended timing requirements for programming: Vee = 6.5 V and Vpp = 13 V (SNAPI Pulse).
TA = 25°C. (see Note 3)
Pulse duration, 'progrem
twCPGMI
tsuCA)
Satup time, address
tsu(E)
Satuptlme,E
tsuCGI
tsu(D)
Satuptime,G
Satup time, data
tsl!M'Pl
tsy(VCC)
Satup time, Vpp
I SNAPI Pulse programming algorHhm
MIN
TVP
MAX
UNIT
95
100
105
IJ.S
IJ.S
IJ.S
IJ.S
IJ.S
IJ.S
IJ.S
IJ.S
IJ.S
2
2
2
2
2
2
Satup time, Vcc
Hold tlme,'address
0
ihCAI
Hold lime, data
2
thio)
NOTE 3: For all switching charactarlstlcs the Input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (reference AC Testing Wave Form)
~TEXAS
INSTRUMENTS
7-228
POST OFFICE sox 1443 • HOUSTON. TEXAS 77251-1443
TMS27C240 4194304·BIT UV ERASABLE PROGRAMMABLE
TMS27PC240 4194304-BIT PROGRAMMABLE
READ-ONLY MEMORY
SML.S24OC - NOVEMBER 11180 - REVISED-JUNE 1995
PARAMETER MEASUREMENT INFORMATION
2.08 V
Output
UnclerTat - -..
T
CL-100pF
(_NoteA)
NOTE A: CL Includes probe and fixture capacltanca.
Figure 2. AC Testing Output Load Circuit
AC testing Input/output wave forms
2.4V
-----""\X 2V
G.40V - - - - - - ' .
-
2VX
0.8,!
0.8 V
'-_ _ _ _ __
A.C. testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. liming measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
AO:-A17
G
DQO-DQ1S
X1
1
1
1
I
1
1
1
1
1
1
14
X
lA
Add.... V.lld
1
1
\
I
14
\ 114
len(G)
ta(A)
HI-Z
11
11
11
talE) ----+I
1
1
1
.1
·1
«««
.01
1 14 .1 leila
14 .1 1 ty(A)
Output
Valid
»j-HI-Z-
Figure 3. Read-Cycle nmlng
~1ExAs
INSTRUMENTS
POST OFFICE'BOX 1443 • HOUSTON, TEXAS 77251-1443
7-229
TMS27C240 4194304-BI1 UV ERASABLE PROGRAMMABLE
TMS27PC240 4194304-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS2040C- NOVEMBER 1980 - REVISED JUNE 1896
PARAMETER MEASUREMENT INFORMATION
r.4----Verify ---~~I
1
1414--- Program ----+l~1
AO-A17
~
-+~
---<~
. ; - - }- ... -+-!--«
i+--* "u(A)
DQO-DQ1S
I
I
J4----+I- "u(D)
Vpp
I"
---./1
'.
Vee
1
I
~"u(VPP)
J~
I
I
'-u(E)
I
----~-V
I
I
-1+-+1
I
~1t!(D)
~"u(Vee)1
tw(pGM)
"n(G)
1
I
I
14
14
I
~I
fell.(G)
I
I
I
I
I
II
I1
I
I
1"4--I~~1~III
I
~
1+--1t!(A) ---+1
"*"
f~-----I
1
I
"u(G)
'i
I
I
/-.----1
. t 13-V Vpp and S.S-V Vee for SNAPI Pulse programming
Figure 4. Programmlng-Cycle TIming (SNAPI Pulse Programming)
~1ExAs
7-230
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77251-1443
8-1
Contents
CHAPTER 8.
MILITARY PRODUCTS
MiUtary Introduction •.. '•.••.••..•.....•••.••...••..• '•••' ..••.• ~ •••••••.•••.•••••••..• i' ••••••••••••• , 8-3
DYNAMIC RAMS
SMJ44C256
SMJ4C1024
SMJ44100·
SMJ44400
SMJ416100
SMJ416400
SMJ416160
SMJ418160
.
1048576-blt
1048576-blt
4194304-blt
4197304-blt
16777216-blt
16777216-bit
16777216-bIt
16777216-blt
(256K x 4) Enhanced Page Mode • • • • • . • . • • . • • . • . . • . . • • • • • • . • • • • .• 8-5
(1 024K x1) Enhanced Page Mode •.•.•••••••••••••.•••••••••••• 8-25
(4096K x 1) Enhanced Page Mode .••....•.......•..•.•..•..•.•• 8-45
(1 024Kx 4) Enhanced Page Mode .............................. 8-65
(16385Kx 1) Enhanced Page Mode '............................. 8-85
(4096K x 4) Enhanced Page Mode ............................. 8-105
(1 024K x 16) Enhanced Page Mode ............................ 8-123
(1 024K)( 16) Enhanced Page Mode ............................ 8-123
1048578-bit
4194304-blt
4194304-bit
(256K x 4) Multiport Video RAM ................................ 8-145
(256K x 16) Multiport Video RAM ............................... 8-197
(256K x 16) Multiport Video RAM ............................... 8-259
131072-bit
4194304-blt
(16K)( 8) UV Erasable Programmable Read-Only Memory •.••..• " 8-319
.(512K x 8) UV Erasable Programmable Read-Only Memory ••••••.• 8-331
VIDEO RAMS
SMJ44C251B
SMJ55161
SMJ55166
EPROMS
SMJ27C128
SMJ27C040
~TEXAS
8·2
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77261-1443
This section contains Military MOS Memory data sheets.
For additional information on Military devices and availability, please refer to the Military Selection Guide
Qiterature number SCYCOO2), or contact your local TI Field Sales Office.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-3
~1ExAs
8·4
INSTRUMENTS
POST OFFICE BOX 1443'· HOUSTON, 'IEXAS 77251-1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
•
•
•
•
Organization ••• 262144 Words)( 4 Bits
Single 5-V Supply (10% Tolerance)
Processed to MIL-8TD-833, Class B
Performance Ranges:
SMJ44C256-80
SMJ44C256-10
SMJ44C256-12
SMJ44C258-15
• 3-State Unlatched Output
• Low Power Dls.lpatlon
ACCESS ACCESS ACCESS READ
TIME
11ME
TIME
OR
ta(R)
ta(CA) WRITE
talC)
(tAAc)
(tcAc)
(tcw CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
80 ns
20 ns
40 ns 150 ns
100 ns
25 ns
45 ns
190 ns
120 ns
30 ns
55 ns 220 ns
150 ns
40 ns
70 ns
280 ns
• Enhanced Page Mode Operation With
'CAS·Before-RAS (CBR) Refresh
• Long Refresh Period
512·Cycle Refresh I.n 8 ms (Max)
• All Inputs and Clocks are TTL Compatible
JDPACKAGE
(TOP VIEW)
OQ1
OQ2
W
~
TF
AO
A1
A2
A3
VCC
19
18
17
18
15
14
13
12
11
• Packaging Offered:
- 20·Pln 3QO.MII Ceramic DIP (JD Suffix)
- 20·Lead Ceramic Surface·Mount Package
(HJ Suffix)
- 20·Pln Ceramic Flat Pack (HK Suffix)
- 20-Terminal Leadle•• Ceramic
Surface·Mount Package (FQ Suffix)
- 20-Terminal low-Profile Leadle••
Ceramic Surface-Mount Package
(HL Suffix)
- 20-Pln Ceramic Zig zag In-Une Package
(SV Suffix)
• Operating Free-Air Temperature Range
- 55°C to 125°C
HJPACKAGE
(TOP VIEW)
OQ1
OQ2
VSS
OQ4
OQ3
CAS
Vss
OQ4
OQ3
CAS
W
RAS
G
AS
A7
AS
TF
G
AO
A1
AS
A3
AS
VCC
A4
W
RAS
TF
AO
A1
A2
A3
VCC
n
1
2
3
4
5
6
7
8
9
10
RAS
TF
VCC
~S
w
20
19
18
17
18
15
14
13
12
11
W
Vss
OQ4
OQ3
RAS
CAS
TF
G
CAS
AO
A1
AS
G
A2
Vss
OQ4
OQ3
Address Inputs
Column Address Strobe
Data In/Data Out
Data Output Enable
Row Address Strobe
Test Function
S-VS",pply
Ground
Write Enable
FQ/HL PACKAGES
(TOP VIEW)
OQ1
OQ2
HKPACKAGE
(TOP VIEW)
OQ1
OQ2
DQ1-0Q4
G
A7
A6
A2
AS
A4
PIN NOMENCLATURE
AO-AB
CAS
AS
A3
A7
A6
Vee
A7
AS
A5
A4
SVPACKAGE
(TOP VIEW)
G
OQ3
VSS
OQ2
RAS
AO
A2
VCC
A5
A7
1
3
5
2
6
6
10
12
14
16
18
20
CAS
OQ4
OQ1
W
TF
A1
A3
A4
AS
AS
AS
A4
EPIC Is a trademark of Texas Instruments Incorporated.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
Copyright C 1995, Texas Instruments Incorporated
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C '- MAY 1989 - REVISED JUNE 1995
description
TheSMJ44C256 series is a set of high-speed, 1048576-bit dynamic random access memories (DRAMs),
organized as 262 144 words of four bits each. These devices employ EPIC'" (Enhanced Performance
Implanted CMOS) technology for high performance, reliability, and low power.
These devices feature maximum RAS access times of 80 ns, 100 nS,120 ns, and ·150 ns. Maximum power
dissipation Is as low as 305 mW operating and 16.5 mW standby on 150-ns devices.
The EPIC technology permits operation from a single 5-V supply, reducing system power supply and decoupllng
requirements, and easing board layout. IcC peaks are 140 rnA typical, and an Input voltage undershoot of
-1 V can be tolerated, minimizing system noise considerations.
All Inputs and outputs, Including clocks, are compatible with Series 54/174 TTL All addr'esses and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The SMJ44C256 Is offered in 2O-pin ceramic dual-in-line packages (JD suffix) and 20/26-terminal ceramic
leadless carriers (FQ/HL suffixes), 2O/26-pin leaded carrier (HJ suffix), a 20-pin flatpack (HK suffix), .and a
2D-pin ceramic zig-zag in-line package 1SV suffix). They are specified for operation from -55°C t0125°C.
logic symbol t
RAM 258K .. 4
8
AO ~---t 2009/2100
7
A1
8
A2
9
A3
11
o
A4
A 282143
12
A5
13
AS
14
A7
15
AS ....;.,;;..---t 20017/2108
C20[ROW]
G231[REFRESH ROW]
4
RAI - ....--t 24[pWR OWN]
C21J[COLUMN]
G24
17
CAS
ijj
G
23C22
3
18
OQ1
2
0Q2
18
OQ3
19
OQ4
tThls symbol Is In accordance with ANSVIEEE Std 91·1984 and IEC Publication 617·12. Pin numbers shown are for the JO package.
EPIC Is a trademark of Texas Instruments Incorperated,
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SMJ44C256
262144-WORD BY 4-BITDYNAMIC RANDOM-ACCESS MEMORY
SGMS034C- MAY 1989 - REVISED JUNE 1995
functional block diagram
Timing and Control
Row
Address
Buffere
(9)
AO-+-U-W.-WW-......t-----1
M-+~+4-+~~~~
A2-+~+4-+-t-<.---~
A3-+~+4-++---~
I/O
A4-+-+-+4.....----+-I
AS-+--+-+-4~---......
Column Decode
A8-+-t-<.------~
A7-++-------+-I
AS-+-------+-I
Buffers
4ot8
Selection
4
001-004
operation
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum
number of columns that can be accessed is determined by the maximum RAS low time and the eAS page cycle
time used. With minimum CAS page cycle time, all 512 columns specified by column addresses AO through M
can be accessed without intervening RAS cycles.
Unlike conventional page mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The column address
latches to the first eAS falling edge. This feature allows the SMJ44C256 to operate at a wider data bandwidth
than conventional page mode parts, since data retrieval begins as soon as column address is valid rather than
when CAS goes low. This performance improvement is referred to as enhanced page mode. Valid column
address can be presented Immediately after th(RA) (row address hold time) has been satisfied, usually well in
advance of the falling edge of CAS. In this case, data is obtained after ta(C) maximum (access time from CAS
low), if ta(CA) maximum (access time from column address) has been satisfied. In the event that column
addresses for the next page cycle are valid at the time CAS goes high, access time for the next' cycle is
determined by the later occurrence of ta(C) or ta(CP) (access time from rising edge of CAS).
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-7
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C - MAY 1988 - REVISED JUNE 1995
address (AD through AS)
Eighteen address bits are required to decode 1 of 262144 storage cell locations. Nine row-address bits are set
up on pins AO through AS and latched onto the chip by RAS. Nine column-address bits are set up on pins AO
through AS and latched onto the chip by CAS. All addresses must be stable on or before the falling edges of
RAS and CAS. RAS Is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder.
In the SMJ44C256, CAS Is used as a chip select, activating the output buffer as well as latching the address
bits into the column-address buffers.
write enable (W)
The read or write mode is selected through W. A logic high on the W input selects the read mode and a logic
low selects the write mode. The write-enable terminal can be driven from the standard TTL circuits ·without a
pull up resistor. The data input is disabled when the read mode is selected. When Wgoes low prior to CAS
(early-write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
C3 grounded.
.
data In (OQ1-oQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
. of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS is already low, the data is strobed in by W with setup and hold times referenced
to this signal. In a delayed-write or read-modify-write cycle, C3 must be high to bring the output buffers to the
high-impedance state prior to applying data to the I/O lines.
data out (OQ1-1)Q4)
The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS and C3 are brought low. In a read cycle the output becomes valid after the access time Interval ta(C)
that begins with the negative transition of CAS as long as ta(~ Sd ta(CA) are satisfied. The output becomes valid
after the access time has elapsed and remains valid while A and G are low. CAS or C3 going high returns it
to a high-impedance state. This is accomplished by bringing C3high prior to applying data, thus satisfying tcJ(GHD)'
oUtput enable (0)
C3 controls the impedance of the output buffers. When C3 is high, the buffers remain In the high-impedance state.
Bringing C3low during a normal cycle activates the output buffers, putting them in the low-Impedance state. It
is necessary for both G and CAS to be brought low for the output buffers, to go into the low-Impedance state.
Once in the low-impedance state, they remain in the low-impedance state until either Gor CAS is brought high.
refresh
A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by strobing
each of the 512 rows (AO-AS). A normal read or write cycle refreshes all bits In each row that Is selected. A
RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh. Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished
by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a
RAS-only refresh cycle.
CBR refresh
CBR refresh is utilized by bringing CAS low earlier than RAS [see paramete~LRL)R1 and holding it low after
RAS falls [see parameter tcJ(RLCH)R1. For successive CBR refresh cycles, CAS can remain low while cycling
RAS. The external address is ignored and the refresh address is generated internally. The external address is
also ignored during the hidden refresh option.
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lEXAS 77251-1443
SMJ44C256
262144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
SGMS034C- MAY 1989 - REVISED JUNE 1995
power up
To achieve proper device operation, an initial pause of 200 !AS followed by a minimum of eight initialization
(refresh) cycles is required after power-up to the full Vee level.
test function pin
During normal device operation the TF pin must either be disconnected or biased at a voltage less than or equal
to Vee.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .•..•.••......•....•.•....•.••...•..•.• ~ .•.•.........•....... 0 V to 7 V
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Short-circuit output current .•........................•.•.....................•....'•........ 50 mA
Continuous total power dissipation ..•... ,.................................................... 1 W
Operating free-air temperature range, TA .......................................... - 55°C to 125°C
Storage temperature range, Tstg ........... , .............. ,....................... - 65°C to 150°C
t stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
Vee
Supply voltage
VSS
Supply voltage
VIH
High-laval Input voltage
VIL
Low-level Input voltage (see Note 2)
TA
Operating free-alr temperature
MIN
NOM
MAX
4.5
5
0
5.5
2.4
-1
-55
UNIT
V
V
8.5
0.8
V
V
°e
case temperature
125
°e
Te
..
NOTE 2: The algebraIC convention, where the more negative (less positive) limit is designated as minimum, IS used for logic-voltage levels only.
..
~1EXAS
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON, TEXAS 77251-1443
8-9
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C - MAY 1988 - REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unle.. otherwise noted)
TEST CONomONS
PARAMETER
'44C25f1.8O
MIN MAX
'44C268-1 0
MIN MAX
'44C268-12
MIN MAX
'44C268-11
MIN MAX
UNIT
VOH
High-level output
voltage
10H --5mA
VOL
Low-level output
voltage
IOL-4.2mA
'0.4
0.4
0.4
0.4
V
II
Input current
Oeakage)
VCC-SV,
VI "OVto6.5V,
All other pins - 0 V to VCC
:010
:010
:010
:010
IAA
10
Output current
(leakage)
VCC .. 5.5V,
CAS high
:010
:010
:010
:010
IAA
ICC1
Read- or
wrtte-cycle
current
VCC-5.5V,
lc(rdW) - minimum
60
70
60
55
mA
ICC2
Standby current
RAS and CAS high,
3
3
3
3
mA
75
65
55
50
mA
50
45
35
30
mA
2.4
Vo-OtoVcc,
2.4
2.4
2.4
V
After 1 memory cycle,
VIH-2.4V
1CC3
Average refresh
current
(RAS only, or
CBR)
1CC4
Average page
current
VCC-S.Sv,
~rdW) minimum,
CYCling,
CAS hlgl) (RAS only),
RAS low after CAS low (CBR)
=
VCC-S.SV,
RASIow,
~.mlnimum,
A cycling
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
HL/JO/FQ
MIN
HJ
MAX
MIN
HK
MAX
MIN
SV
MAX
MIN
MAX
CI(A)
Input capacitance, addra88 inputs
8
7
8
9
Ci(RC}
Input capacitance, strobe Inputs
7
7
6
8
UNIT
pF
pF
pF
Input cepacitance, write-enable Input
7
7
7
7
CIIW}
pF
Output cepacltance
7
10
8
Co
9
..
NOTE 3: CapacItance Is sampled only at initial design and after any major change. Samples ara tested at 0 V and 25°C with a 1-MHz signal
applied to the pin under test. All other pins are opan.
~ThxAs
8-10
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON.ll:XAS 77251-1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C- MAY 1989 - REVISED JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature (see Figure 1)
ALT.
SYMBOL
PARAMETER
'44C256-80
'44C256-10
'44C256-12 ,
'44C256-15
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
UNIT
taCC)
Access time from CAS low
25
30
40
Access time from column-address
teAC
tM
20
talCAI
40
45
55
70
ns
ns
talRLI
Access time from RAS low
tRAC
80
100
120
150
na
taCG)
Access time from G low
tGAC
20
25
30
40
ns
ta(CP)
Access time from CAS high column
pracharge
tePA
40
50
80
75
na
1dis(CH)
Output dlssble time after CAS high
(see Note 4)
toFF
20
25
30
35
ns
1dis(G)
Output diseble time after G high
(sse Note 4)
tGOFF
20
25
30
35
ns
NOTE 4: 1d1s(CH) and 1d1s(G) are specified when the output ia no longer driven. The outputs are disabled by bringing either G or CAS high.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
ALT.
SYMBOL
PARAMETER
1clrdl
1c(W)
'44C258-80
MIN
MAX
'44C256-1 0
MIN
MAX
'44C256-12
MIN
MAX
'44C256-15
MIN
MAX
UNIT
Cycle time. read (sse Note 8)
tRC
150
190
220
280
Cycle time. write
twc
150
190
220
280
ns
ns
1c(rdW)
Cycle tlme.reed-write/readmOdify-write
tRWC
225
270
305
355
ns
1c(p)
Cycle time. page-mode read
or write (aee Note 7)
tpC
50
55
85
80
na
1c(PM)
Cycle time. page-mode readmodify-write
tpRWC
115
135
150
175
na
1w(CH)
Pulse duretion. CAS high
tep
10
10
15
25
ns
tw(CL)
Pulse duration. CAS low
(see Note 8)
teAS
20
tw(RH)
Pulse duration. RAS high
(precharge)
tAp
80
tw(RL)
Pulse duration.
nonpage mode RAS low
(see Note 9)
1RAS
80
tw(RL)P
Pulse duration.
page mode RAS low
(see Note 9)
tRASP
80 100000
10000
25
10000
100
10000
90
80
10000
30
10000
100 100000
120
40
10000
na
100
10000
120 100000
ns
10000
na
150 100000
ns
150
twIWLI
Pulse duretlon. write low
twp
15
15
20
25
ns
tsu(CA)
Setup time. column address
before CAS low
lAsc
5
5
5
5
na
NOTES: 5. Timing measurements in this table are referenced to VIL max and VIH min.
8. All cycle times assume It 5 ns.
7. To assure 1c(p) min. tsu(CA) ahould be "'tw(CH).
'
8. In a read-modify-write cycle.1d(CLWL) and tsu(WCH) must be Observed. Depending on the user's trensitlon times. this can require
additional CAS low time [tw(CL)I.
9. In a read-modify-write cycle.1d(RLWL) and tsu(WRH) must be observed. Depending on the user's trensitlon times. this can require
additional RAS low time ltw(RL)I.
=
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 772S1-1443
8-11
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C - MAY 1989 - REVISED JUNE 1985
timing req~lrements over recommended ranges of supply voltage and operating temperature
(contrnueCl) (see Note 5)
ALT.
PARAMETER
SYMBOL
'44C256-80
'44C256-10
'44C256-12
MIN
MIN
MIN
MAX
MAX
MAX
'44C258-15
MIN
MAX
UNIT
tsu(RA)
Setup time, row address
before AAS low
lAsR
0
0
0
tsu(D)
Setup time, data before
Vi low (see Note 10)
tDS
0
0
0
0
ns
tsulrdl
Setup time, W high before CAS low
tRCS
0
0
0
0
118
tsu(WCL)
Setup time, W low before CAS low
(see Note 11)
twcs
0
0
0
0
ns
tsulWCH)
Setup time, Vi low before CAS high
25
30
40
118
Setup time, W low before AAS high
tcWL
tRWL
20
tsu(WRH)
20
25
30
40
ne
1h(CA)
Hold time, column address after CAS
low (see Note. 10)
leAH
15
20
20
25
118
1h(RA)
Hold time, row address after RAS
low
IRAH
15
15
15
15
ne
Ih(RLCA)
Hold time, column address after RAS
low (see Note 12)
tAR
60
70
80
100
ne
th(D)
Hold time, data after CAS low
(see Note 10)
toH
15
20
25
30
118
th(RLD)
Hold time, data after RAS low
(see Note 12)
toliR
60
70
85
110
118
th(WLGL)
Hold time, G high after W low
IGH
20
25
30
40
118
Ih(CHrd)
Hold time, W high after CAS high
(see Note 14)
IRCH
0
0
0
0
118
Ih(RHrd)
Hold time, W high after RAS high
(see Note 14)
tRRH
10
10
10
10
ne
Ih(CLW)
Hold time, W low after CAS low
(see Note 11)
twCH
15
20
25
30
118
Ih(RLW)
Hold time, W low after RAS low
(see Note 12)
twCR
65
75
90
105
118
IdCRLCH)
Delay time, RAS low to CAS high
tcSH
80
100
120
150
118
IdCCHRL)
Delay time, CAS high to AAS low
tcRP
0
0
0
0
118
IdCCLRH)
Delay time, CAS low to AAS high
tRSH
20
25
30
40
118
Id(CLWL)
Delay time, CAS low to W low
(see Note 15)
tcwD
80
70
80
90
ne
Id(RLCL)
Delay time, AAS low to CAS low
(see Note 13)
tRCD
30
Id(RLCA)
NOTES: 5.
10.
11.
12.
13.
14.
15.
60
30
30
Delay time, RAS low to column
20
20
40
20
5.5
tRAO
address (see Note 13)
llmlng measurements In thIS table are referenced to VIL max and VIH min.
Referenced to the later of CAS or Vi in write operationa.
Early-write operation only
The minimum value Is measured when Id(RLCL) is set to Id(RLCL) min as a reference.
Maximum value specified only to assure access time.
Either th(RHrd) or Ih(CHrd) must be satisfied for a read cycle.
Read-modify-write operation only
~1ExAs
8-12
75
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
ns
0
90
30
110
ns
65
25
80
na
SMJ44C256
262144·WORD BY 4·B11 DYNAMIC RANDOM·ACCESS MEMORY
SGMS034C- MAY 1989 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating temperature
.
(contrnued) (see Note 5)
ALT.
SYMBOL
PARAMETER
'44C256-80
MIN
'44C256-1 0
MAX
MIN
'44C256-12
MAX
MIN
'44C256-15
MAX
MIN
MAX
UNIT
tc!{CARH)
Delay time, column address to
RAShigh
tRAL
40
45
55
70
ns
tc!{CACH)
Delay time, column address to
CAS high
teAL
40
45
55
70
ns
tc!{RLWL)
Delay time, RAS low to W low
(see Note 15)
tRWD
130
150
170
200
ns
tc!{CAWL)
Delay time, column address to W
low (see Note 15)
tAWD
80
95
105
120
ns
DO
!GOD
20
25
30
40
ns
tc!{GLRH)
Delay time, G low to RAS high
!GSR
20
25
30
40
ns
tc!{RLCH)R
Delay time, AAS low to CAS high
(see Note 16) .
teHR
20
25
25
30
ns
tc!{CLRL)R
Delay time, CAS low to RAS low
(see Note 16)
teSR
10
10
10
15
ns
tc!{RHCL)R
Delay time, RAS high to CAS low
(see Note 16)
tApc
0
0
0
trf
Refresh time interval
tc!{GHD)
tt
NOTES: 5.
15.
16.
17.
Delay time, G high before data at
ns
0
8
6
8
tAEF
Transition time (see Note 17)
tr
Timing measurements In this table are raferenced to VIL max and VIH min.
Read-modify-write operation only
CBR refresh only
System transition times {rise and farn are to be a minimum of 3 ns and a maximum of 50 ns.
8
ms
ns
PARAMETER MEASUREMENT INFORMATION
5V
1.31 V
Output Under Teet - -....- -..
Output Under Teet - - - .
I
_
=
CL=80pF
(S" Note A)
CL 80 pF
(See Note A)
:::=f::
(b) ALTERNATE LOAD CIRCUIT
(8) LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
Figure 1. Load Circuits for Timing Parameters
-!/} 1ExAs
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77251-1443
8-13
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C - MAY 1988 - REVISED JUNE 1986
PARAMETER MEASUREMENT INFORMATION
I
))---I
I
~tcll.(G)
I
I
NOTE A: Output can go from the high-Impedance state to an invalld-data state prior to the specified 8QC8S8 time.
Figure 2. Read-Cycle Timing
~TEXAS
8-14
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C- MAY 1889 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Figure 3. Early-Write-Cycle Timing
~lExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-15
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C- MAY 1989 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Figure 4. Write-Cycle Timing
8·16
:lllExAs
'
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C - MAY 1988 - REVISED JUNE 1985
PARAMETER MEASUREMENT INFORMATION
~
RAS _ _~I
~~
I...
N
-J
~
~'I
tw(RL)
~ It
I'"
1 I+- tcI(RLCL) - . I
1 1
II
teu(RA)
-+I
I
1
I+t 1
I...
~I
iIIII 1
1
I
I
- .. ~ ~)@)
. I'"
1
1
I"
1
I'
Vi
:+1 ,...
1 1 ,
~I
lh(CA)
1 I'"
i
1
1
1
1
tw(CH)
~I
_Er~_,---_
~I
14- teu(WCH) -+t
1
~I :.- teu(WRH) -.j
tcI(RLWL)
I ~I' teu(rd)
,
"
:
»:~o~'r**7!
!I
,,.
I+- tw(Wl) ~
11
~g~1~~~
N
1
tcI(CAWL)
~
, I J,..- tcI(CLWL) ~
,te(C) 1 I,.
~I
1
I I,
I+- te(CA) --.I
I
1
I
,
,
J+t- teu(D) ---+I
,
,
1
OQ1DQ4
~I teu(CA)
tcI(RLCA)
i"---
Vi I
I
Iltt(RLCA) 1
I'"
'""tw-(R-H)--
-+I
I ~I----------~
N
1
~l
l!+tl tcI(CHRL)
1
-t+1 II1II- th(RA)
~
Vi
I~
~I
tw(CL)
1
1 S. . Note A
----------«
1 ltt(D) ---~~,
iIIII
1
1
~------"--~
valid I"
Don't Cere
,...
1
1
1
~I
,...
I
tclI8(0)
1
......--te(O) - - . . ,
1
V'tvVvv~J\ !
)
G ~~Do~v"",~'t"",';~~,,",~,,",~)N"-\,,;;_________
,
~ tcI(OHD) +i
I
1\XXXXXX)(XV~;:~~i'I--.I
\i
F.
3'(!
I I
~
:
j.- Ih(CA)
~ ~
ta(C)
14-- ta(CA)
I
I
tau(CA)
I
tc(p)
II1II
I
~ I
14-1 tw(CL) -.lUi~
1-.. \i
I I
Ici(RLCA)
Vi
~
Se. Note A
«
I
I I
!:
~I
~$E]88
14--1h(C,Hrd) --+t
i
I
I
II1II
..
~
~
Icila(CH)
,
valid Out
})o----
jill
~ 1ci1s(0)
14-- ta(O) ~m~~~~~~
h~;~K*~)i
ag~~g~~m
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the apecified access time.
B. A write-cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and rHd-modify-write timing
specifications are not violated. ,
C. Access time is ta(CP)- or ta(CA)-depandent.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
~1ExAs
INSTRUMENTS
8-18
POST OFFICE SOX 1443 • HOUSTON. TEXAS 77261-1443
SMJ44C256
262144·WORD BY 4-BIT DYNAMIC RANDOM·ACCESS MEMORY
SGMS034C- MAY 1889- REVISED JUNE 19115
PARAMETER MEASUREMENT INFORMATION
1l1li
1
IeU(D) - - ..........1
(aH Note B)
1
I
I,..!--
jIIII-:- "'(0)
---+!...
IeU(D)
1,
(aH Note B)
I
I '''''''(RLD)
1
1
"'(D).I
~
(aee ote B)
I
~ ~ ~
I
1l1li
I
•
I
~
"'(WLQL)
Va"dDete'n~Va"dlnE~~~~~
DQ1-Da4m<
1
-+I I+-
-+I
(aH Note B)
I
IcI(GHD)
1
--.j
.
II1II-
"'(WLGL)
1
1
!+-+
~
IcI(GHD)
1
~
NOTES: A. A read cycle or a read-modify-wrlte cycle can be intermixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
B. Referenced to CAS or iN, whichever occurs last.
Figure 7. Enhanced-Page-Mode Write-Cycle 'riming (see Note A)
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-19
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C- MAY 1989 - REVISED JUNE 1885
PARAMETER MEASUREMENT INFORMATION
NOTES: A. Output can go from the high-impedanca state to an invalid-dala state prior to the specified 8CC888 time.
B. A read or write cycle can be intermixed with read-modify-write cycles 88 long 88 the read and write timing specifications are not
violated.
Figure 8. Enhanced-Page-Mode Read-Modlfy-Wrlte-Cycle TIming (see Note B)
~1ExAs
8-20
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ44C256
262144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
SGMS034C - MAY 1889 - REVISED JUNE 11185
PARAMETER MEASUREMENT INFORMATION
Figure 9. RAS·Only Refresh Timing
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS m51-1443
8-21
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C - MAY 1989 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
,14--
14-- Refretlh Cycle ----.I
,
14
..,
, 14
..' I tw(RL)
'I
YT
II
RASI'l
-
,
' I
, I
I
,I II N'·
I ~
, I.
,I+--
Memory Cycle --+I
'4
tw(RH)
'14
, I
\l
'4
..,
..I 1 tw(RL)
Refretlh Cycle
,
yJ r '\
1
,
,
/S \,
ld(RLCH)R
tw(CL)
I
I
"
,
--.I
tw(RH)
14
..,
..,
! ,,----
',',
~I~~~
I
I I I
1-+11+- lJt(RA) I
r
¥!I
I
I
I
I II i l l
I
j+t teU(C(,-»
I II i4! *- th(CA)
I
I
I
H+I
-"_fr~E~~
"- n
I -+t
"'~IITI·
w~ I I
~~
14- lJt(RHrd)
I
~~~~c~~~
I 1-..1 14-- te(C)
I ~ te(CA)
.... ~
01
~
I
.
~~
~
,
ldle(CH) -f++I
::
I
~
~
,
14- te(O)
I+--ldle(O)
----.r
tt~
"
Figure 10. Hldden-Refresh-Cycle (Enhanced Page Mode) Timing
~1ExAs
INSTRUMENTS
8-22
POST OFFICE BOX 1443 • HOUSTON, lEXAS 77261-1443
· SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C - MAY 1989- REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
144----------tc(rd)
NI+-
I+-Iw(RH) ----.I
AM
----A
tcI(RHCL)R
~ 14--
tcI(CLRL)R
I
14
CAS ----..,,;1 1
-.J
~I
-----------toI-.I
1414------1w(RL) _ _ _ _ _ _~~I
1
Vr.
1
---
It
I
I
I
~~_ _ _~4_-~~_-_-_-_-_tcl_(R_L_CH)_R_ _ _ _ _~j;I
OQ1-OQ4 ---------------HI-Z--------------
Figure 11. Automatic CBR Refresh.cycle Timing
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON;l1:XAS 77261-1443
8-23
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS0340 - MAY 1989 - REVISED JUNE 1996
-!!11ExAs
8·24
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON,.TEXAS 77251-1443
SMJ4C1024
1048576-811 DYNAMIC RANDOM-ACCESS MEMORY
•
•
•
•
HJ PACKAGE
(TOP VIEW)
OrganlzaUon ••• 1048576 x 1
Processed to MIL-8TD-883, Class B
Single S-V Supply (10% Tolerance)
Performance Ranges:
D
(MAX)
80 ns
100 ns
120 ns
150 ns
(MAX)
20 ns
25 ns
30 ns
40 ns
READ
OR
WRITE
CYCLE
(MIN)
(MAX)
40 ns
45 ns
65 ns
70 ns
150 ns
190 ns
220 ns
280 ns
• Enhanced Page Mode Operation for Faster
Memory Access
- Higher Data Bandwidth Than
Conventional Page Mode Parts
- Random Single-Bit Access Within a Row
With a Column Address
• One of TI's CMOS Megabit DRAM Family
Including SMJ44C256 - 256K x 4
'
Enhanced Page Mode
• CAS-Before-RAS (CBR) Refresh
• Long Refresh Period
512-cycle Refresh In S ms (Max)
• 3-State Unlatched Output
• Low-Power Dissipation
• Texas Instruments EPIC'" Process
• All Inputs/Outputs and Clocks Are
TTL-Compatlble
• Packaging Offered:
- 20/26-Lead Ceramic Surface Mount
Package (HJ Suffix)
- 1S-Pln 300-MII Ceramic DIP (JD Suffix)
- 2G-Pln Ceramic Flat Pack (HK Suffix)
- 20/26-Terminal Leadless Ceramic
Surface Mount Package (FQ/HL Suffixes)
- 2G-Pln Ceramic Zig-Zag In"Une Package
(SVSufflx)
• Operating Temperature Range
- 55°C to 125°C
o
Vss
a
iN
ACCESS ACCESS ACCESS
TIME
TIME
TIME
ta(R)
talC)
ta(CA)
(tRAc)
(teAC)
(tAA)
'4Cl024-80
'4Cl 024-1 0
'401024-12
'4C1024-15
JDPACKAGE
(TOP VIEW)
RAS
TF
CAS
NC
NC
Vss
a
iN
m
TF
AS
CAS
AS
3
4
AS
A7
AD
AS
A1
A7
AS
AS
A4
11
AS
A3
AS
Vcc-",;.;..._~_ A4
A2.
HKPACKAGE
(TOP VIEW)
n
D
TF
1
2
3
4
NC
5
AO
8
7
8
9
10
u
iN
RAS
A1
A2.
A3
VCC
Vss
20
FQ/HL PACKAGES
(TOP VIEW)
a
19
18
17
18
15
14
13
12
11
CAS
NC
AS
AS
A7
AS
AS
A4
SVPACKAGE
(TOP VIEW)
Vss
2 CAS
a
4 Vss
CAS
iN
NC
TF
A9
NC
A1
AO
AS
A1
A7
AS
A2.
A3
AS
VCC-,.;.;..._...;;..;.,_ A4
....._..........
A3
A4
AS
AS
PIN NOMENCLATURE
AD-AS
~
o
NC
Q
RAS
TF
VCC
VSS
iii
EPIC is a trademark of Texas Instruments Incorporated.
~1ExAs
INSTRUMENTS
POST OFFICE SOX 1443 • ffOUSTON. TEXAS 77251-1443
Address Inputs
Column Address Strobe
Data In
No Internal Connection
Data Out
Row Address Strobe
Test Function
5-V Supply
Ground
Write Enable
Copyright C 1995. Texas InstrumenIB Incorporellld
8-25
SMJ4C1024
1048576-8IT DYNAMIC RANDOM-ACCESS MEMORY
SGMS023D - DECEMBER 1988- REVISED JUNE 19$5
description
The SMJ4C1 024 is a high-speed, 1 04a576-bit dynamic random-access memory (RAM) organized as 1 048576
words of one bit each. It employs enhanced performance implanted CMOS (EPIC"') technology for high
performance, rel~ability, and low power at a low cost.
This device features maximum RAS access times of 80 ns, 100 ns, 120 ns, and 150 ns. Maximum power
dissipation is as low as 305 mW operating and 16.5 mW standby on 150 ns devices.
The EPIC'" technology permits operation from a single 5-V supply, reducing system power supply and
decoupling requirements, and easing board layout. IDO peaks are 140 rnA typical, and a -1 V input voltage
undershoot can be tolerated, minimizing system noise considerations.
All inputs and outputs, including clocks, are compatible with Series 54 TTL All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The SMJ4C1024 is offered in an 18-pin ceramic dual-In-line package (JD SuffIX), a 20/26-terminaJ ceramic
leadless carrier package (FQ/HL suffixes), a 20/26-pin leaded carrier package (HJ suffix), a 2O-pin flatpack
(HK suffix), and a 2O-pin ceramic zig-zag in-line package (SV suffix). They are characterized for operation from
-55°C to 125°C.
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row address setup and hold and address multiplexing is eliminated.
The maximum number of columns that can be accessed is determined by the maximum RAS low time and the
CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by column
addresses AO through A9 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the f~inj
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of A
latches the column addresses. This feature lets the SMJ4C1024 operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as the column address is valid rather than
when CAS goes low. This performance improvement is referred to as enhanced page mode. A valid column
address can be presented immediately after the row address hold time has been satisfied, usually well in
advance of the falling edge of CAS.. In this case, data is obtained after taCC) maximum (access time from CAS
low), if ta(CA) maximum (access time from column address) has been satiSfied. If the column addresses for the
next page cycle are valid at the same time CAS goes high, access time for the next cycle is determined by the
later occurrence of ta(C) or ta(CP) (access time from riSing edge of CAS).
address (AO-AS)
,
Twenty address bits are required to decOde 1 of 1 048576 storage cell locations. Ten row-address bits are set
up on inputs AO through A9 and latched onto the chip by RAS. The ten column-address bits are set up on pins
AO through A9 and latched onto the chip by CAS. All addresses must be stable on or before the falling edges
of RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row
decoder. CAS is used as a chip select to activate the output buffer as well as latch the address bits into the
column-address buffer.
write enable I(W)
The read or write mode is .selected through W. A logic high on the W input selects the read mode, and a logic
low selects the write mode. The write-enable terminal can be driven from standard TTL circuits without a pullup
resistor. The data input is disabled when the.read mode is selected. When W goes low prior to CAS (early write),
data out remains in the high-impedance state for the entire cycle, permitting common I/O operation.
~1ExAs
8-26
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ4C1024
1048576-8IT DYNAMIC RANDOM·ACCESS MEMORY
SGMS023D- DECEMBER 1988 - REVISED JUNE 11195
data In (0)
Data-in is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip latch. In an early write cycle, W is brought low prior to CAS, and the
data is strobed in by CAS with setup and hold times referenced to this ~nal. In a delayed-write or
read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup and hold times
referenced to this signal.
data out (Q)
The 3-state output buffers provide direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 54 TTL loads. Data out is the sarne polarity as data in. The output is in the high impedance (floating) state
until CAS is brought low. In a read cycle the output becomes valid after the access time ta(C)' taCC) begins with
the negative transition of CAS as long as ta(R) and ta(CA) are satisfied. The output becomes valid after the access
time has elapsed and remains valid while CAS is low; when CAS goes high, the output returns to a
high-impedance state. In a delayed-write or read-modify-write cycle, the output follows the sequence for the
read cycle.
refresh
A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by stsbing
each of the 512 rows (AO-AS). A normal read or write cycle refreshes all bits in each selected row. A RA -only
operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffer remains
in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. Hidden
refresh can be performed while maintaining valid data at the output pin. This is accomplish~holding CAS
at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh
cycle.
CAS-~fore.RAS (CBR) refresh
CBR refresh is used by bringing CAS low earlier than RAS (see parameter tcJ(CLRL)R) and holding it low after
RAS falls (parameter tcJ(RLCH)R>. For successive CBR refresh cycles, CAS can remain low while cycling RAS.
The external address is ignored and the refresh address is generated internally. The external address is also
ignored during the hidden refresh cycles.
power up
To achieve proper device operation, an initial pause of 200 !.IS followed by a minimum of eight initialization cycles
is required after full VCC level is achieved.
test function pin
During normal device operation TF must be disconnected or biased at a voltage less than or equal to VCC.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-27
SMJ4C1024
1048576-8IT DYNAMIC RANDOM-ACCESS MEMORY
SGMS023D - DECEMBER 1988 - REVISED JUNE 1~
logic symbol t
RAM 1024K,,1
AD
A1
A2
A3
A4
5
8
2001 0/21 DO
7
8
10
0
~A1048S7S
11
AS
12
AS
A7
AS
A8
13
14
15
20D19/2108
"
3
~
......
Vi
D
18
~
2
~
1
C20[ROW]
G23 [REFRESH ROW]
24[PWRDWN]
C21 [COL]
024
.
23,21D
> 23C22
24EN
A,22D
AV
tThIs symbol Is In accordance with ANSVlEEE Std. 91-1984 and lEe Publication 817-12.
The pin numbers shown are for Ihe la-pin JO package.
="~
8-28
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS n2s1-1443
17
Q
SMJ4C1024
1048576-811 DYNAMIC RANDOM-ACCESS MEMORY
SGMS023D- DECEMBER 1988 - REVISED JUNE 1995
functional block diagram
Row
Addre..
Buffere
(10)
..
AO-+~~-r+-r+~
~
A1-+~~r+~~~--~
A2-+~~-r+-~--~~
A3-+~~-r~~--~~
D
A4-+-r~r+~------~
A5-+~~~----~~~
Q
A5-+-r~~--------~
A7-+-re-----------~
A8-+~------------~
A8-e--------------~
absolute maximum ratings over operating free-alr temperature range (unless otherwise notecl)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee ..•..•..•...•...•....•....•..•.....•.....•.•.•...•..•.•..••..••• -1 V to 7 V
Short-circuit output current, los •.••..••..•.........••...••..•.••.•.•.•••••••••.••..••••.••• SO mA
Power dissipation ..•..•.............................••........••..•.•.••...•...•.•..••••••. 1 W
Operating temperature range, TA ................................................. - S5°C to 12S·C
Storage temperature range, Tstg ••..•.•.•..••••..•.•••••.•..•..•.•...•.•••••..•.•• - 65·C to 150·C
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the devloe. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
Implied. Exposure to absolute·maxlmum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
Vee
Supply voltage
VIH
High·level Input voltage
VIL
Low·level Input voltage (see Note'2)
TA
Minimum operating free-alr temperature
MIN
NOM
MAX
4.5
2.4
-1
5
5.5
6.5
0.8
-55
UNIT
V
V
V
'e
Maximum operating case temperature
125
Te
'e
NOTE 2: The algebraIC convention, where the more negative (less positive) limit is designated as minimum, Is used for loglc-voltage levels only.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-29
SMJ4C1024
1048576·81T DYNAMIC RANDOM·ACCESS MEMORY
SGMS023D - DECEMBER 1988 - REVISED JUNE 1995
(
electrical characteristics over recommended ranges of supply voltage .and operating free-air
temperature (unless otherwise noted)
TEST
cONDmONS
PARAMETER
VOH
High-level
output voltage
IOH--5mA
VOL
Low-level
output voltage
10L"' 4.2 mA
II
Input current
peakage)
'401024-80
'401024-10
'401024-12
MIN
MIN
MIN
MAX
2.4
MAX
2.4
'401024-15
MAX
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
0.4
V
VCC- 5•5V• VI OVto 6.5 V.
All other pins .. 0 V to Vcc
.,10
.,10
.,10
.,10
JIA
10
Output
current
peakage)
VCC- 5•5V•
(5AShlgh
VO .. OVtoVCC.
.,10
.,10
.,10
.,10
JIA
ICCl
Read-or
write-cycle
current
VCC=5.5V.
Minimum cycle
75
70
60
55
mA
ICC2
Standby
current
After 1 memory cycle.
RAS and (5AS high.
VIH .. 2.4V
3
3
3
3
mA
ICC3
Averege
refresh
current
(RASonlyor
CBR)
Minimum cycle.
VCC .. 5.5V.
RAS cycling.
(5AS high (RAS only).
RAS low after CAS low (CBR)
70
65
55
50
mA
1CC4
Averege page
current
VCC=5.5V.
RASlow.
50
45
35
30
mA
=
=
tpc minimum.
(5AS cycling
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
HL/JD/FQ
PARAMETER
MIN
MAX
HJ
MIN MAX
SV
HK
MIN
MAX
MIN
MAX
UNIT
9
pF
7
pF
7
8
6
8
8
pF
7
7
-;
pF
CI(A)
Input capacitance. address Inputs
6
7
CIIOI
Input cepacitsnce. data input
5
5
CIIRCI
Ci(W}
Input capacitance. strobe Inputs
7
Input capacitance. wrlte-enable Input
7
pF
10
8
Output capacitance
7
9
Co
NOTE 3: capacitance Is sampled onlyatlnltlal design and after any major change. Samples aretested at QV and 25°C with a 1 MHz signal applied
to the pin under teat. All other pins are open.
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature (see Figure 1)
ALT.
SYMBOL
PARAMETER
'401024-80
'4C1 024-1 0
'401024-12
'401024-15
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
UNIT
talCI
t(CA)
teAC
tM
20
25
.30
40
Access time from column address
40
45
55
70
ns
tlRI
Access time from RAS low
tRAC
80
100
120
150
ns
talCPI
Access time from column precharge
tePA
40
40
80
75
ns
ldis(CH)
Output disable time after (5AS high
(see Note 4)
toFF
20
25
30
35
ns
Access time from (5AS low
NOTE 4: ldls(CH) Is specified whan the output Is no longer driven. The output Is disabled by bringing CAS hlQh.
~1ExAs
.
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON, 'TEXA$ 77251-1443
ns
SMJ4C1024
1048576-81T DYNAMIC RANDOM-ACCESS MEMORY
SGMS023D - DECEMBER 1988- REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
PARAMETER
ALT.
SYMBOL
'4C102,wo
'4C1024-1 0
'4C1024-12
'4C1024-15
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
UNrr
tc(rd)
Cycle time, read
(see NoteS)
tRC
150
190
220
2S0
ns
tc(W)
Cycle time, write
twc
150
190
220
260
ns
tc(rdW)
Cycle time,
read-writelread-modify-wrlte
tRwc
175
220
2S5
315
ns
tc
Cycle time, page-mode read
or write (see Note 7)
tpc
50
55
65
60
ns
tc(PM)
Cycle time, page-mode
read-modify-write
tpRWC
75
S5
110
135
ns
tw{CH)
Pulse duration, CAS high
tcp
10
10
15
25
ns
tw(CL)
Pulse duration, CAS low
(see NoteS)
teAs
20
tw(RH)
Pulse duration, RAS high
(precharge)
tRP
SO
twIRL)
Pulse duration, nonpage
mode, RAS low
(see Note 9)
tRAS
SO
tw(RL)P
Pulse duration, page mode,
RAS low (see Note 9)
tRASP
10000
25
10000
SO 100000
100
10000
90
SO
10000
30
10000
100 100000
120
40
10000
ns
100
10000
120 100000
ns
10000
ns
150 100000
ns
150
tw/WL)
Pulse duration, write
twp
15
15
20
25
ns
lsu(CA)
Satup time, column address
before CAS low
tASC
0
3
3
3
ns
lsu(RA)
Setup time, row address
before RAS low
tASR
0
0
0
0
ns
lsu(D)
Setup time, data
(see Note 10)
tDS
0
0
0
0
ns
tsu(rd)
Setup time, raad before CAS
low
tRCS
0
0
0
0
ns
tsu(WCL)
Setup time, W low befora
CAS low (see Note 11)
twcs
0
0
0
0
ns
lsu(WCH)
CAS high
tcwL
20
25
30
40
ns
Isu(WRH)
Setup time, W low before
RAShigh
tRWL
20
25
30
40
ns
lh(CA)
Hold time, column address
after CAS low
leAH
15
20
20
25
ns
th(RA)
Hold time, row address after
RASlow
.
tRAH
12
15
15
20
ns
NOTES: 5.
S.
7.
S.
9.
10.
11.
Setup time, W low before
liming measurements In this table are referenced to VIL max and VIH min.
All cycle times assume tt 5 ns.
To assure tc(P), min, lsu(CA) should be a tw(CH)'
In a read-modlfy-write cycle,Id(CLWL) and lsu(WCH) must be observed.
In a read-modify-write cycle, Id(RLWL) and lsu(WRH) must be observed.
Referenced to the later of CAS or Vii in write operations
Early write operation only
=
~TEXAS
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON. TEXAS 77251-1443
S-31
SMJ4C1024
1048576-8IT DYNAMIC RANDOM-ACCESS MEMORY
SGMS023D- DECEMBER 1988 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5) (continued)
ALT.
SYMBOL
PARAMeTER
tJ,(RClA)
Hold time, column address after
RAS low (see Note 12)
th(D)
Hold time, data (see Note 10)
tDH
th(RLD)
Hold time, data after RAS low
(see Note 12)
tJ,(CHrd)
'4C1024-80
MIN MAX
'4C1 024-1 0
MIN MAX
'4C1024-12
MIN MAX
'4C1024-15
MIN
MAX
UNIT
70
80
100
ns
15
20
25
30
ns
toHR
60
70
85
110
ns
Hold time, reed after CAS high
(see Note 15)
tACH
0
0
0
0
ns
tJ,(RHrd)
Hold time, read after RAS high
(see Note 15)
tRRH
10
10
10
10
ns
th(CLW)
Hold time, write after CAS low
(see Note 11)
twCH
15
20
25
30
ns'
th(RLW)
Hoid time, write after RAS low
(see Note 12)
twCR
60
70
85
100
ns
1d(RLCH)
Delay time, RAS low to CAS high
tcsH
120
150
ns
Delay time, CAS high to RAS low
teRP
80
0
100
1d(CHRL)
0
0
0
ns
1dlCLRHI
Delay time, CAS low to RAS high
tRSH
20
25
30
40
ns
1d(CLWL)
Delay time, CAS low to W low
(see Note 13)
teWD
20
25
40
50
ns
1d(RLCL)
Delay time, RAS low to CAS low
(see Note 14)
tRCD
22
60
28
75
28
90
33
110
ns
1d(RLCA)
Delay time, RAS low to column
ad~ress (see Note 14)
tRAO
17
40
20
55
20
65
25
80
ns
1d(CARH)
Delay time, column address to RAS
high
1RAL
40
45
55
70
ns
1d(CACH)
Delay time, column address to CAS
high
teAL
40
45
55
70
ns
1d(RLWL)
Delay time, RAS low to W low
(see Note 13)
tRWD
80
100
130
160
n8
1d(CAWL)
Delay time, column address to W
low (see Note 13)
tAWD
40
45
65
80
n8
1d(RLCH)R
Delay time, RAS low to CAS high
(see Note 16)
teHR
20
25
25
30
n8
1d(CLRL)R
Delay time, CAS low to RAS low
(see Note 16)
teSR
10
10
10
15
ns
1d(RHCL)R
Delay time, RAS high to CAS low
(see Note 16)
tRPC
0
0
trf
Refresh time interval
tt
NOTES: 5.
10.
11.
12.
13.
14.
15.
16.
17.
Transition time (see Note 17)
tAR
tREF
-
60
-
-
~1ExAs
8-32
8
-
llmlng measurements In thiS table are referenced to VIL max and VIH min.
R,eferenced to the later of CAS or Vi in write operations.
Early-write operation only
The minimum value is measured when 1d(RLCL) is set 1d(RLCL) min as a reference.
Read-modify-write operation only
Maximum value specified only to assure access time.
Either tJ,(RHrd) or th(CHrd) must be satisfied for a read eyele.
CBR refresh only
Transition times (rise and falQ for RAS and CAS are to be minimum of 3 ns and a maximum of 50 ns.
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON. 1lEXAS 77251-1443
ns
0
0
8
8
8
-
ms
nil
SMJ4C1024
1048576-811 DYNAMIC RANDOM-ACCESS MEMORY
SGMS023D- DECEMBER 1988 - REVISED JUNE 1895
PARAMETER MEASUREMENT INFORMATION
v
Outpul Under Teat
ill
--f
T
1.31 V
IOH/IOL
CL-SOpF
,eHNoteA)
~~~---1
RL.Z18D
T
(b) ALTERNATE LOAD CIRCUIT
,e) LOAD CIRCUIT
NOTE A: CL Includes probe and fixture capacitance,
Figure 1. Load Circuits for Timing Parameters
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 772151-1443
8-33
SMJ4C1024
1048576-811 DYNAMIC RANDOM-ACCESS MEMORY
SGMS023D - DECEMBER 1988 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
RAS
~~
--,'14
t{
tw{RL)
11
It ~ 141
14-- tcI(CLRH)
j4- tcI(RLCL) ~
I 14
CAS
tcI{RLC~ ~ !+- .1
I++H- tau(RA)
I
14 I
IXI (I+-- -+iM',~II
, '-------
--+I
----+I
tw(RH)
1
\
~ 1 tau(CA)
1 1 1
14
1 1 tcI(CACH) --.! 1 1
~
1 1 tcI(CARH)
1 .1
1 lti(RLCA)
1
I11III
th(RA)...J.i
,
~
~ tcI(CHRL)
tw(CL)
Ir
1"
}f
11
----+i I+~, 1
tcI(RLCH)
11
~
~
~
tw(CH)
+-t--+!
""'----
'- -.___
- .. ~ ~)0( Cd~~: ~~:""",;,!~~~~»§§0<~.
1
J... '-
1
II
1
Vi
j4-+i-
1
r
1
th(CA)
1
«~:n:E~W1
I
,
,I
,
1
Q
---.!
.
f"" ..u(rd) -...
!
14
HI..z
I1
1
ta(CA)
See Note A
ta(R)
th(CHrd)
~HnHa!-:~
14-- ta(C) ~ 14
,
j4
~ th{RHrd)
J
~
~
tclls(CH)
,
valid
.:
NOTE A: Output can go from the high-impedance stl!te to an invalld-data state prior to the specified access time.
Figure 2. Read-Cycle TIming
~1ExAs
8-34
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON, TEXAS 77251-1443
~
)J-------
SMJ4C1024
1048576·811 DYNAMIC RANDOM·ACCESS MEMORY
SGMS023D - DECEMBER 1888 - REVISED JUNE 1119S
PARAMETER MEASUREMENT INFORMATION
Q
--------------HI-Z--------------Figure 3. Early-Wrlte-Cycle Timing
~1ExAs
INSTRUMENTS.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-35
SMJ4C1024
1048576·BIT DYNAMIC RANDOM·ACCESS MEMORY
SGMS023D - DECEMBER 1988 - REVISED JUNE 1995
Q
(
Not Valid
Figure 4. Write-Cycle TIming
~TEXAS
INSTRUMENTS
8-36
POST OFFlCEBOX 1443 • HOUSTON. TEXAS 77251-1443
i. .--------
SMJ4C1024
1048576-811 DYNAMIC RANDOM-ACCESS MEMORY
SGMS023D- DECEMBER 1988 - REVISED JUNE 1895
PARAMETER MEASUREMENT INFORMATION
NOTE A: Output can go from the high-Impedance state to an Invalid-data state prior to the specified access time.
Figure 5. Read-Wrlte-/Read-Modlfy-Wrlte-Cycle TIming
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS n251-1443
8-37
SMJ4C1024
1048576-8IT DYNAMIC RANDOM·ACCESS MEMORY
SGMS023D- DECEMBER 1988 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
AD-Ai
Q
NOTES: A. Output can go from the high-Impedance state to an invalid-date state prior to the speciflEld access time.
B. Awrite cycle or a reed-modify cycle can be mixed wHh the read cycles as long as the write and read-modify-write timing specifications
are not violated.
C. Access time 18 la(CP) or la(CA) dependent.
Figure 6_ Enhanced-Page-Mode Read-Cycle Timing
-!111ExAs
INSTRUMENTS
8-38
POST OFFICE BOX 1443 • HOUSTON. lEXAS 7721i1-1443
SMJ4C1024
1048576-8IT DYNAMIC RANDOM-ACCESS MEMORY
SGMS023D - DECEMBER 1888 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
i00iii1II1II1-----------
1{
~
~
IcI(RLCH)
I_
I!'II
IcI(RLCL)
tw(RH) ~
tw(ALlP - - - - - - - - - -.~
. 1
tw(CL)
I 1I
.1
~I ~111111--tc(p)
...
...
}l-F
X \L;t-
~ ts'-U-(c....A)~--J1
th(RLC~
I
jIIIII- theRA) ~
1
fill
-+j I+--
tsu(RA)
I
I1
I
1
"'-I
~ IcI(CLRH) ---.j
1
.JoIIII--1cI(CHRL)
~
1
1
---.!
.\, 'X /r-----+-j-L
~
1
I
I
14-
.,
-(CH)
I
r-1cI(CACH)
1II1I
~
IcI(CARH)
th(CA) J
1
1
J
~
AD-A9
Q
--------------------------------HI~------------------------------
NOTES: A. A read cycle or a read-modify-write cycle can be Intermixed with write cycles as long as read and read-modify-wrlte timing
specifications are not violated.
B. Referenced to ~ or W, whichever occurs last.
Figure 7. Enhanced-Page-Mode Write-Cycle Timing
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77251-1443
8-39
SMJ4C1024
1048576-811 DYNAMIC RANDOM-ACCESS MEMORY
SGMS023D - DECEMBER 1988 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORf,tATION
tw(RH) ~
I+I
~~~-----------------tw~~p--------~--------~~ I
YlL
RASN
I I
II
14
I 14
1c(pM)
fcI~LCH)
II taU(CA)-NU
I
I tt.~LCA)
II1II
I~
~I+-tt.~
AO-AS
I
~
I
II1II
I
I
~ th(CA)
.fcI~LCA)1
-.I 14-1- tau~A)
I
I
~ Icolu~n
I I
I
r-- fcI(C~
I
I
I
I
I
!
N
I I I
11II1II
tau(D) -.: 14-
Dm~~~Jf~
I
I
~
I
II1II
ta(R)
I
I
~
I .
I
\l
#t~'~~~~l-;-a¥'ft"~-,
I
I
I
Valid
I
~
SM NoteA~
II
I
II
14- tau(WRH) ~
I
I
Q
~~~
l1li
I
~
I
,~
fll
VAXrl~~n-tct~~
Column
~
valid
~
.t!id-----
I II
III
III
I II
wxr
~tt.(D)
III
fcI(CHR~ ~
\\L
I
I
I
I
tau(WCH)
I
I
j4- ta(C) -.I
ta(CA) ~
I
I
~tw(W~
II1II
"(RLWll---,., I
w~·!
I
I
I
I
I
,
.II
)@(
~II
" I I 14- ta~(rd) ~ -.I j4- fcI(CLW~
II
I
t.......
'~
~
~
I IiII
4):
tw(CH)
I :.---.. fcI~LC~ ~
I I
\. ~tw(C~
I
I
I+- fcI(cLRH) ~
~
ta(CP)
W~,,":'7'r"l;~"""ns~~~~m~
~I
.~
I
SHNotaA ~
14- fclI8(CH) +I
I
~:!:
~
.r-
NOTES: A. Output can go the from high-impedance state to an Invalid-data state prior to the specified access time.
B. A rnd or a write cycle can be Intermixed with read-modify-write cycles as long as the read and write timing speclflcatlons are
not violated.
Figure 8. Enhanced-Page-Mode Read-Modlfy-Wrlte-Cycle llmlng
~TEXAS
INSTRUMENTS
POST OFFICE SOX 1<143 • HOUSTON. TEXAS 77251-1<143
SMJ4C1024
1048576-81T DYNAMIC RANDOM-ACCESS MEMORY
SGM~D-DECEMBER1N8-R~SEDJUNE1~
PARAMETER MEASUREMENT INFORMATION
14
RAS
ifI.-- ~
............... -W'
tc(rd)
N~~(R~
I
~-,
!+-
I
~
~(RH) ---.:
I
"""---
Q-----------------------------HI~----------------------------Figure 9. RAS-Only Refresh-Cycle Timing
,, .
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TeXAS 772151-1443
8-41
SMJ4C1024
1048576-811 DYNAMIC RANDOM-ACCESS MEMORY
SGMS023D - DECEMBER 1988 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Figure 10. Hidden-Refresh-Cycle Timing
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lCXAS n2S1-1443
SMJ4C1024
1048576-8IT DYNAMIC RANDOM·ACCESS MEMORY
SGMS023D - DECEMBER 1988 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
1 4 j 4 f - - - - - - - - - - - t c ( r d ) - - - - - - - - - -.~
.
RAS
J
l+IcI(CHRL)R
14
II1II
~
.
tw(RH)
-+:
IX
.1
IcI(RHCL)R
1 4 1 4 - - - - - - twIRL)
I
ioIII4f-----IcI(RLCH)R
------~~ I
y""----
----~~
yll
--J_
----""'\~~II ____~
I___~__________________
~
___~
I
Q
--------------------HI.z-----------------Figure 11. Automatlc-CBR-Refresh-Cycle TIming
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ4C1024
.
1048576-81T DYNAMIC RANDOM-ACCESS MEMORY
SGMS023D- DECEMBER 1988 - REVISED JUNE 1995
-!!11ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251 ..1443
SMJ44100
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
1991 - REVISED JUNE 1995
HRPACKAGE
crOP VIEW)
• Processed to MIL·STD-883, Class B
• Organization ••• 4194304 x 1
D
• Performance Ranges:
SMJ44100-80
SMJ441OQ-10
SMJ441OQ-12
ACCESS ACCESS ACCESS
READ
TIME
TIME
TIME OR WRITE
(tAA)
CYCLE
(tRAc) . (tcAc)
(MAX)
(MAX)
(MAX)
(MIN)
80 ns
20 ns
40 ns
150 ns
100 ns
25 ns
50 ns
180 ns
120 ns
30 ns
55 ns
210 ns
VSS
a
iN
• Single SOV Power Supply (z10% Tolerance)
RAS
A10
CAS
A9
AO
AS
A1
A2
A7
A6
1.3
Vee
• Enhanced Page Mode Operation for Faster
Memory Access
- Higher Data Bandwidth Than
Conventional Page·Mode Parts
- Random Single-Bit Access Within a Row
With a Column Address
D
VSS
a
w
CAS
RAS
NC
NC
A9
A5
A10
AO
A1
A4
A2
A6
1.3
A5
VCC
A4
AS
A7
VSS
a
• CAS·Before·RAS (CBR) Refresh
CAS
• Long Refresh Period
1024-Cycle Refresh In 16 ms (Max)
A9
NC
• 3-State Unlatched Output
AS
• Low Power Dissipation
A7
A6
• Texas Instruments EPIC" CMOS Process
A5
• All Inputs/Outputs and Clocks are TTL
Compatible
• Packaging Options:
- 1S·Pln, 400 mil Ceramic DIP (JD Suffix)
- 18-Pln, 300 mil Ceramic DIP (JDB Suffix)
- 2D-Pln, Ceramic Flatpack (HR Suffix)
- 2D-Pad, 350 x 675 Ceramic Chip Carrier
(HL Suffix)
- Additional Package Options Planned
• Military Temperature Range
-55°C to 125°C
c::..;.;;.........;..;;;,
AO-A10
CAS
D
. NC
Q
RAS
Vii
VCC
VSS
description
A4
PIN NOMENCLATURE
Address Inputs
Column-Address Strobe
Data In
No Internal Connection
Data Out
Row-Address Strobe
Write Enable
5-VSupply
Ground
The SMJ441 00 is a series of high-speed 4194304-bit dynamic random-access memories (DRAMs), organized
as 4194304 words of one bit each. They employ state-of-the-art enhanced performance implanted CMOS
EPIC'· technology for high performance, reliability, and low power operation.
The SMJ44100 features maximum row access time of 80ns, 100 ns, and 120 ns. Maximum power dissipation
is as low as 385 mWoperating and 22mW standby.
All inputs and outputs, including clocks, are compatible with Series 54 TTL. All addresses and data-in lines are
latched on-Chip to simplify system design. Data-out lines are unlatched to allow greater system flexibility.
EPIC Is a trademark of Texas Instruments Incorporated.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
Copyright C 1995. Texas Instruments Incorporated
8-45
SMJ44100
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040D - JANUARY 1991 - REVISED JUNE 1996
description (continued)
The SMJ44100 is offered in a 300-mil18-pili ceramic dual-in-line package (JOB suffix), an 18-pin ceramic
. dual-in-line package (JD suffix), a 20-pin ceramic flatpack (HR suffix), and a 20-pad 350 x 675 ceramic chip
carrier package (HL suffix). All packages are guaranteed for operation from - 55°C to 125°C.
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by the maximum RAS low time and the ~
page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by column addresses
AO through AS can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS Is high. The falling edge of CAS
latches the column addresses. This feature allows the SMJ44100 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
CAS goes low. This performance improvement is referred to as enhanced page mode. Valid column address
can be presented inimediately after row address hold time has been satisfied, usually well in advance of the
falling edge of CAS. In this case, data is obtained after tCAC maximum (access time from ~ low). if tAA
maximum (access time from column address) has been satisfied. In the event that column addresses for the
neXt cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later
occurrence of tcAC or tePA (access time from rising edge of CAS).
address (AO-A10)
Twenty-two address bits are required to decode 1 of 4194304 storage cell locations. Eleven row-address bits
are set up on inputs AO through A 10 and latched onto the chip by RAS. The eleven column-address bits are
set up on pins AO through A10 and latched onto the chip by CAS. All addresses must be stable on or before
the falling edges of RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as
well as the row decoder. ~ is used as a chip select, activating the output buffer as well as latching the address
bits Into the column-address buffer.
write enable (W)
The read or write mode is selected through W. A logic high on the Winput selects the read mode and a logic
low selects the write mode. The write-enable terminal can be driven from standard TIL circuits without a pull up
resistor. The data input Is disabled when the read mode is selected. When W goes low prior to CAS (early write),
data out remains in the high-impedance state for the entire cycle permitting common I/O operation.
data In (0)
Data is written during a write or read-write cycle. Depending on the mode of operation, the falling edge of CAS
or W strobes data into the on-Chip data latch. In an early-write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-write cycle,
CAS is already low, the data is strobed in by W with setup and hold times referenced to .this signal.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SMJ441 00
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040D - JANUARY 1991 - REVISED JUNE 1995
data out (Q)
The high-impedance state output buffer provides direct TTL compatibility (no pullup resistor required) with a
fanout of two Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance
(floating) state until CAS is brought low. In a read cycle the output becomes valid after the access time interval
tcAC that begins with the negative transition of CAS as long as tRAC and tM are satisfied. The output becomes
valid after the access time has elapsed and remains valid while CAS is low; CAS going high returns it to a
high-impedance state. In a delayed-write or read-write cycle, the output follows the sequence for the read cycle.
refresh
A refresh operation must be performed aUeast once every 16 ms to retain data. This can be achieved by strobing
each of the1 024 rows (AO-A9, A10 is ignored). A normal read or write cycle refreshes all bits in each row that
is selected as well as the corresponding row relative to A10. A RAS-only operation can be used by holding CAS
at the high (inactive) level, conserving power as the output buffer remains in the high-impedance state.
Externally generated addresses must be used for a RAS-only refresh. Hidden refresh can be performed while
maintaining valid data at the output pin. This is accomplished by holding CAS at VIL after a read operation and
cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is
ignored during the hidden refresh cycles.
CAS-before-RAS (CBR) refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter tcsR> and holding it low after RAS
falls (see parameter tcHR>. For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored and the refresh address is generated Internally.
power-up
To achieve proper device operation, an initial pause of 200 !1S followed by a minimum of eight initialization cycles
is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-onlyor CBR) cycle.
t.stmode
An industry standard design for test (OFT) mode is incorporated in the SMJ44100. A CBR cycle with W low
(WCBR) cycle is used to enter test mode. In the test mode, data is written into and read from eight sections of
the array in parallel. Data is compared upon reading and if all bits are equal, the data-out pin goes high. If any
one bit is different, the data-out pin goes low. Any combination read, write, read-write, or page-mode can be
used in test mode. The test mode function reduces test times by enabling the 4M DRAM to be tested as if it were
a 512K DRAM, where row address 10, column address 10, and also column address 0 are not used. A RAS-only
or CBR refresh cycle is used to exit the OFT mode.
~TEXAS
INSTRUMENTS.
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-47
SMJ441 00
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040D-JANUARY 1991 - REVISED JUNE 1995
logic symbol t
RAM 4086K X 1
AD
Ai
A2
A3
9
3OD11/31DO ...
10
11
12
14
A4
15
AS
AS
A7
AS
AS
A10
>A41 a:304
18
17
18
22
5
3OD21/31D10
C30(ROW)
G331(REFRESH ROW)
34[PWRDWN]
r-...
C31[COL]
034
r-.
3
~
CAS
24
t---;::
W
2
1
D
~
r-.
"
3331D
~33C32
MEN
A,32D
A'il
tThis symbol Is In accordance with ANSVIEEE Std 91-1984 .and IEC Publication 817-12.
The pin numbsrs shown are for the HM package.
-!llExAs
INSTRUMENTS
POST OFFICE sox 1443 • HOU8'lON. TEXAS 772&1-1443
25
Q
SMJ441 00
4194304-WORD BY 1-B11
DYNAMIC RANDOM-ACCESS MEMORY
SGMS0400 - JANUARY 1991 - REVISED JUNE 1896
functional block diagram
AD
A1
A10
Column Decod.
•
•
•
Column
AcId....
Bulle...
S.na. Amplltl....
128KArray
128KArray
128KArray
R
0
128KAr...y
D
w
•
•
•
••
Row
•
AcId.....
Bulle...
D
••
•
•c
0
Q
d
•
absolute maximum ratings over operating free-air temperature {unless otherwise noted}t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee •••.••. ; •••••••••••••.•••••••••.•••.•••.••.••.•••••.••..•.••••• -1 V to 7 V
Short-circuit output current •.•••••.•••.••..••.•••.•••.•.•..••...•..•.••••••.•.•••••••••••.• 50 rnA
Power dissipation •••••••.•••••••.••••••..•••••.•••••••••••••.•••.••••••••••••••..••.••.•••• 1 W
Operating free-air temperature range, TA ••..•..••••••.•••••••••.••..••••••••.•••••• - 55°e to 125°e
Storage temperature range, Tstg •.•••••••.•••.•••••.•••.•..•••••••.••••••••••••••• - 65°e to 1500 e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functfonal operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
VCC
Supply voltage
VIH
High-level Input voltage
Low-Ievel Input voltage (see Note 2)
VIL
TA
TC
MIN
NOM
MAX
4.5
2.4
5
5.5
8.5
0.8
-1
-55
Minimum operating temperature
Maximum operating case temperature
..
UNIT
V
V
V
·C
125
"C
NOTE 2: The algebraic convention, where the more negatiVe Oess posltlve) limit is designated as minlmum,ls used for logic-voltage levels only.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ44100
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040D -JANUARY 1991 - REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage, and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDmONS
VOH
High-level output voltage
IOH=-5mA
VOL
Low-level output voltage
IOL-4.2mA
II
Input current (leakage)
10
ICCl
'441CJ0.80
MIN MAX
2.4
'44100-10
MIN
'44100-12
MAX
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
Voo= 5.5V.
VI" 0 V to 8.5 V.
All other pins. 0 V to Voo
:t10
:t10
:t10
IIA
Oulput current (leakage)
VCC-5.5V.
CAS high
VO" 0 Vto VCC.
:tl0
:tl0
:tl0
IIA
Read- or write-cycle current
(see Note 3)
VCC=5.5V.
Minimum cycle
85
80
70
mA
1002
Standby current
After 1 memory cycle.
RAS and CAS high.
VIH 2.4 V (TTL)
4
4
4
mA
1003
Average refresh current
(RAS only. or CBR)
(see Note 3)
Minimum cycle.
VCC=5.5V.
RAS cycling.
eM high (RAS only).
RAS low after CAS low (CBR)
85
75
85
mA
50
40
35
mA
=
tpC .. minimum,
VCC= 5.5V.
RASlow.
CAS cycling
NOTES: 3. Measurad with a maximum of one address change while RAS = VIL
4. Measurad with a maximum of one address change while CAS .. VIH
ICC4
Average page current
(see Note 4)
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
MAX
UNIT
CIIA)
Input capacitance. address Inputs
7
CilD)
Input capacitance. date inputs
7
pF
pF
CIIRC)
Input capacitance. strobe Inputs
10
pF
CI/Wl
Co
Input capacitance. writa-enable Input
10
pF
Output capacitance
10
pF
NOTE 5: VCC = 5 V: 0.5 V and the bias on pins under test is 0 V. Capacitance is sampled only at Initial design and after any major change.
switching characteristics over recommended ranges of supply voltage range and operating
free-alr temperature
PARAMETER
'441CJ0.80
MIN MAX
'44100-10
MIN
MAX
'44100-12
MIN
MAX
UNIT
tAA
Access time from column addrass
40
50
65
ns
teAC
Access time from CAS low
20
25
30
ns
tePA
tRAC
Access time from column precharge
45
50
55
ns
Access time from RAS low
80
100
120
ns
Output disable time after CAS high (see Note 8)
20
25
toFF
NOTE 8: toFF Is specified when the output Is no longer driven. The output IS disabled when CAS Is brought high.
30
ns
:lllExAs
INSTRUMENTS
8-50
POST OFFICE BOX '443 • HOUSTON. TEXAS 7725'-'443
SMJ44100
4194304·WORD BY 1·B11
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040D - JANUARY 1991 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating fru-alr
temperature
tRC
tRWC
tpc
tpRWC
!RAsp
tRAS
Cycle time, random reed or write (see Note 7)
Cycle time, raad-write
Cycle time, page-mode raad or write (see Note 8)
Cycle time, page-mode read-write
Pulse duration, page mode, RAS low (see Note 9)
Pulse duration, nonpage mode, RAS low (see Note 9)
teAS
tep
Pulse duratiOn, ~ low (see Note 10)
Pulse duration, ~ high
lAp
Pulse duration, RAS high (precharge)
twP
tASC
Pulse duration, write
Setup time, column address before ~ low
tASR
Setup time, row address before RAS low
tes
tRCS
Setup time, deta (see Note 11)
'441CJ0.80
MIN
MAX
150
175
50
70
80 100000
80 10000
20 10000
10
80·
15
0
0
0
'44100-10
MIN
MAX
180
210
80
65
100 100000
100 10000
25 10000
10
70
20
0
0
0
0
25
25
'44100-12
MIN
MAX
210
245
65
95
120 100000
120 10000
30 10000
15
80
25
0
0
0
0
30
30
twos
Setup time, reed before ~ low
Setup time, W low before ~ high
Setup time, Wlow before ~ high
Setup time, W low before ~ low
(early-write operatiOn only)
twsR
leAH
tOHR
tOH
Setup time, W high (CBR refresh only)
Hold time, column address after ~ low
Hold time, deta after RAS low
Hold time, deta (see Note 11)
10
15
80
15
75
90
20
25
60
10
75
15
90
0
0
0
0
0
tcwL.
tRWL
0
20
20
0
UNIT
ns
ns
ns
n8
ns
ns
ns
ns
ns
ns
ns
ns
n8
n8
ns
ns
0
ns
10
10
20
20
0
tAR
Hold time, column address after ~ low (see Note 13)
!RAH
tRCH
Hold time, row address after RAS low
Hold time, read after ~ high (see Note 12)
IARH
Hold time, read after RAS high (see Note 12)
twCH
Hold time, write after ~ low (early-write operation only)
15
20
25
twCR
Hold time, write after RAS low (see Note 10)
75
90
twHR
10
10
tAWD
Hold time, W high (CBR refresh only)
Delay time, column address to W low
(read-write operetlon only)
80
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
50
55
ns
leHR
Delay time, RAS low to ~ high (CBR refresh only)
20
20
25
leRP
leSH
Delay time, CAS high to ~ low
0
0
100
0
120
10
10
30
ns
ns
ns
ns
Delay time, RAS low to CAS high
Delay time, ~ low to ~ low (CBR refresh only)
0
80
10
leSR
Delay time, ~ low to W low (read-write operation only)
20
.tcwo
NOTES: 7. All cycle times assume IT .. 5 ns.
8. To assura tpc min,lASC should be :t lep.
9. In a read-write cycle,lRWD and tRWL must be observed.
10. In a read-write cycle, tcw~d IGwL must be observed.
11. Referencad to the later of CAS or W In write operetions
12. Either tRRH or IACH must be setlsfled for a read cycle.
13. The minimum value is measured when tROC is set to tRCO min es a reference.
-!!1ThJMs
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON.lCXAS77251-1443
25
15
ns
8-51
SMJ44100
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040D -JANUARY 1891 - REVISED JUNE 1895
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (continued)
'44100-80
'44100-10
MIN
MAX
MIN
MAX
15
40
40
20
50
'44100-12
MAX
MIN
UNIT
tRAD
tRAL
Delay time, RAS low to column address (see Note 14)
teAL
Delay time, column addr888 to CAS high
40
tRCD
Delay time, RAS low to ~ low (lee Note 14)
20
tRPe
tRSH
tRWO
Delay time, RAS high to CAS low
0
0
nl
Delay time, CAS low to RAS high
0
20
25
30
nl
Delay time, RAS low to W low (read-write operation only)
60
100
120
nl
leLZ
CAS to output in low Z (see Note 15)
0
0
0
tREF
RefreSh time Interval
Delay time, column address to RAS high
20
50
25
60
18
85
55
50
nl
55
75
25
90
nl
nl
18
18
nl
nl
ml
Tranlition time (see Note 18)
IT
NOTES: 14. Maximum value lpeclfied only to assure access time.
15. Valid data is presented at the output after all access times are lltisfied. The output can go from the high-impedance state to an
invalid-data state prior to the specified access times as the output is driven when CAS goes low.
18. Transition times (rill and falQ for RAS and CAS are to be minimum of 3 ns and maximum of 50 nl.
PARAMETER MEASUREMENT INFORMATION
'1
Output Under Tnt
VRL - 21••
~
CL-100pF
(I. . Note A)
,
IV
Output UnderT..t - - . - - - .
CL-100pF
(I.. Note A)
T'
-
(b) ALTERNATE LOAD CIRCUIT
(I) LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
Figure 1. Load Circuits for Timing Parameters
~TEXAS
8-52 .
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, -rexAS 77251-1443
SMJ441 00
4194304-WORD BY 1-B11
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040D - JANUARY 1991 - REVISED JUNE 1895
PARAMETER MEASUREMENT INFORMATION
AO-A10
1
Q
I1
----I"--HI-Z
1
1
14
1
14
j4-tcAc ~ 1111114--toFF--......,~1
IlAA
~I--_----"-""Ir'
1
n:J:V
)
See NoleA ' @ ' \ . v a l l d > - - - - - 1
1
1--------:1
tcLZ j4
~I
1
lRAc
~I
NOTE A: Valid data Is presented at the output after all access times ere satisfied. The output can go from the hlgh-lmpeclance state to an
Invalld-clata atate prior to the speclfled access times as the output Is driven when CAS goes low.
Figure 2. Read-Cycl' Timing
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77261-1443
8-53
SMJ44100
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS0400 - JANUARY 1991 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Q--------------------------H~--------------------------Figure 3. Early-Wrlte-Cycle Timing
~TEXAS
8-54
INSTRUMENTS
'
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SMJ441 00
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040D - JANUARY 1991 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
NOTE A: Valid data Is presented at the output after all access times are satisfied. The output can go from the high-Impedance stata to an
Invalid-data state prior to the specified access times es the output is driven when CAS goes low.
Rgure 4. Write-Cycle Timing
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-55
SMJ441 00
4194304-WORD BY 1·BIT
. DYNAMIC RANDOM·ACCESS MEMORY
SGMS040D-JANUARV 1991 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
NOTe A: valid data Is preaented at the output after an access times are satisfied. The output can go from the high-Impedance state to
an Invallcklata state prior to the specified access times as the output Is driven when CAS goes low.
Figure 5. Read-Wrlte-Cycle nmlng
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
SMJ441 00
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040D - JANUARY 1991 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
IRP
I"
~
IftAsp
N
I I
I j4-- IRCD ---+II
I :.
I
:
ltf!L
14
.:
teAS
:F.
1'!
I I
I
.1 leAH I 14
I j+-1RAH~
I+t- tASR -++I!++- tASc 1
114
1
.1 I
I
I
I
1
~I teRP -+I
!+ tep -+I
-+t 1
1 1
1
I II
.1
tpC
1
teSH
II II
.1
I
. 14-1
N~
II I14
I I
14
I ) + - - IRSH
'11
1
.
teAL
lRAL
(:r
1'--~t"~I--------
I
I
~ 1
I I
I
I
I
.1
II
I
I
I
~~~~"\7f:T
AO-A10
1
I
I4-lRAD~
1
1
1
14
Q
I
I
1
I
1
I
tePA ---II---'.~I
I
I
1
.... 4 - - I
14----1 teAC ----+II
,..- ~~:;oo~~-~~*~:ml"r'ft7"
i+
kW
' ,,!
)@(
I ~I I
I
I
I
I I4--lASH ~
I
I
-++i I+-teWD
I+-t lACS -.I I I
I t+- tAWD ~!.+I
_
I I I
teWL
~ I I
I'f--lAWL ~
I
I I
I
.
tDS
I
I
1
_I
~~--~~~~~
I
I
I,
I
I
I
.¥oi$_- )«e~)( +- ~;?':j:5:m
I
I
14
I
I
14
14
~I
toH
j+- tCAC --.t
~
1
~I
tAA
t
RAC I
teU---+!
See Note A
Q
+;-
. • 1
I
I
I
D
1+
14 I
I I
tep
I
I
I
I
I
tRAD
2X .;.: ~
I
I
w
~I
~I
~I
lH
teAS
-1
;+1ft-I+-
~
I
I
I
teu~
I (... NomA)
14
tePA
I
I
I
I
~
14I
I
I
I
I
~I
j+- toFF - . ,
I
~I
I
I
~, . . . . . - - -....) -
-----------~-----....
VslldOut
NOTES: A. Valid data Is presented at the output after all access times are satisfied. The output can go from the high-Impedance state
to an invalid-data atate prior to the specified access times as the output Is drivan when CAS goes low.
B. A read or write cycle can be Intermixed with read-write cycles as long as the read and write timing specifications are not
violated.
Figure 8. Enhanced-Page-Mode Read-Write-Cycle Timing
~TEXAS
INSTRUMENTS
POST OFFICE sox 1443· HOUSTON. TEXAS n251-1443
8-59
SMJ441 00
4194304-WORD BY 1-B11
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040D - JANUARY 1991 - REVISED JUNE 1985
PARAMETER MEASUREMENT INFORMATION
141
____________
T'~
leRP
.1
1
1
iRc
1 1
t41-iRAS ~1
~I
H
i~
I
I+-
I -+t
tr
1· 11 .... -"1
Vi·· 4 1\'----
f.-iRP
1
-+II
-+I !+-iR
j+ leRP
~
AD-At
Q
---------------HI.z--------------
NOTES: A. Transition limes' (riss and falQ for RAS and CAS are to be minimum of 3 ns and maximum of 50 ns.
B. A10 Is a don't care.
Figure 9. RAS-Only Refresh-Cycle llmlng
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ441 00
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS04OD- JANUARY 1981 - REVISED JUNE 1895
PARAMETER MEASUREMENT INFORMATION
~I~r-------------------~C------------------~~I
~ ~p ----+tI I~1~-----------tRAS -------------,.~II
I
--~/:
I
N
!+- teaR -+t
~PC 41 ~
\l
Y
I
I 141~----tcHR ------~~I
~
~R~~~-~~I
I
Q
r
IliI:-_ _ __
tr
I_-_ _
~
(_NoteA)
~
~I twHR
y
------------------------------HI~------------------------------
NOTES: A. TransIUon Umes (rise and fall) for AA§ and CAS are to be minimum of 3 ns and maximum of 50 ns.
B. AlOis a don't care.
Figure 10. Automatic CBR Refresh-Cycle Timing
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON, TEXAS 77251-1443
8-61
SMJ44100
4194304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS0400 -JANUARY 1991 - REVISED JUNE 19911
PARAMETER MEASUREMENT INFORMATION
t+-- Mamory Cycla
I ,III
=tI
~ I\~AS
}..k
~ RafreahCycle ~
lAp
I·
1l1li
RAIN- Yi N
.:
'
,!
ii: Ti i i:
~~L!
,,
I,
'
'I,
I
r-. ~I
lAp
1111
}JlRAS
y
. I
1
T\.
"
I
~~I
tcHR
' ,.
-i :
tiD
tAR I ,III
I
I
,
I
", r+! i+I
r tcAH
!+rrtASC
I,
I ,
lRAH--t+i/+i I II ,
I ,
-+j IIiIt1tASR I I , I I
.
Refresh Cycla ~
1_
;-
ii
~
I
I~-~--
. 1
II
,
,
,
,
,
I
,
I
"
,
I
I
I
II
,
,
I
,
-'1O_~~m"
I
~
tRRH
-tel
1~I,lACS '~.
1_
~
twHR
-twSR
,__ I ;++t- twHR
I j++t- ty'HR
,.---tw~~tw.SR~
VI" ~ ~~
_
D~~t ltcAc>
(tAN
CYCLE
(MAX)
80 ns
100 ns
120 os
(MAX)
40 ns
45 os
55 ns
150 ns
180 os
210 os
(MAX)
20 ns
25 ns
30 os
JOB OR HR PACKAGES
(TOP VIEW)
DQ1
DQ2
VSS
VSS
W
DQ4
DQ3
DQ4
DQ3
RAS
A9
CAS
DE
CAS
DE
AO
A1
(MIN)
• Enhanced Page Mode Operation for Faster
Memory Access
- Higher Data Bandwidth Than
Conventional Page-Mode Parts
- Random Single-Bit Access Within a Row
With a Column Address
• CAS-Bafore-RAS (CBR) Refresh
• Long Refresh Period
1024-Cycle Refresh In 16 ms (Max)
HLPACKAGE
(TOP VIEW)
AS
A7
AS
A5
A4
M.
A3
Vee
A1
AS
A7
AS
AS
A4
SVPACKAGE
(TOP VIEW)
• 3-State Unlatched Output
• Low Powe, Dissipation
• Texas Instruments Enhanced Performance
Implanted CMOS (EPIC"') Process
• All Inputs/Outputs and Clocks are TTL
Compatible
• Packaging Options:
- 20-Pln, 3OD-MII Ceramic Side-Brazed DIP
(JOB suffix)
- 2D-Pln Ceramic Flatpack (HR Suffix)
- 2D-Pad, 350 )( 675 Ceramic Chip Carrier
(HL suffix)
- 20-Pln Ceramic ZIP (SV suffix)
- Additional Package Options Planned
CAS
• Military Temperature Range
-55 to 125°C
Vee
VSS
PIN NQMENCLATURE
AO-A9
DQ1-DQ4
DE
RAS
Vi
Address Inputs
Column-Address Strobe
Data InJDats Out
Output Enable
Row-Address Strobe
Write Enable
5-V Supply
Ground
description
The SMJ44400 is a series of high-speed 4194304-bit dynamic random-access memories (DRAMs), organized
as 1 048576 words of four bits each. The series employs state-of-the-art EPIC™ technology for high
performance, reliability, and low-power operation.
The SMJ44400 features maximum row access times of 80 ns, 100 riS, and 120 ns. Maximum power dissipation
is as low as 360 mW operating and 22 mW standby.
All inputs and outputs, including clocks, are compatible with Series 54 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
EPIC is e trademark of Texas Instruments Incorporetsd.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443 "
Copyright C 1995. Texaslnslrumentll Incorporated
8-85
SMJ44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041D - JANUARY 1991 - REVISED JUNE 1995
description (continued)
The SMJ44400 Isoftered In a 300-mil. 20-pin ceramic side-brazed duai-in-Iine package (JOB suffix). a 20-pin
ceramic flatpack (HR suffix). a 2O-pad 350 )( 675 ceramic chip carrier (HL suffix). and a 20-pin ceramic zig-zag
in-line package (SV suffix). All packages are characterized for operation from -55°C to 125°C.
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by the maximum RAS low time and the CAS
page cycle time used. With minimum CAS page cycle time. all 1024 columns specified by column addresses
AO through A9 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs. the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The failing edge of CAS
latches the column addresses. This feature ailows the SMJ44400 to operate at a higher data bandwidth than
conventionai page-mode parts. since data retrieval begins as soon as column address is valid rather than when
CAS goes low. This performance improvement is referred to as enhanced page mode. Valid column address
can be presented immediately after row address hold time has been satisfied. usually well in advance of the
falling edge of CAS. In this case. data is obtained after tCAC maximum (access time from CAS low). If tAA
maximum (access time from column address) has been satisfied. In the event that column addresses for the
. next cycle are valid at the time CAS goes high. access time for the next cycle Is determined by the later
occurrence of tCAC or tePA (access time from rising edge of CAS).
address (AD-AS)
Twenty address bits are required to decode 1 of 1 048576 storage cell locations. Ten row-address bits are set
up on inputs AO through A9 and latched onto the chip by RAS. The ten column-address bits are set up on pins
AO through A9 and latched onto the chip by CAS. All addresses must be stable on or before the failing edges
of RAS and CAS. RAS Is similar to a chip enable in that it activates the sense amplifiers as well as the row
decoder. CAS Is used as a chip select. activating the output buffer as well as latching the address bits into the
column-address buffer.
write enable (W)
The read or write mode is selected through W. A logic high on the Winput selects the read mode and a logic
low selects the write mode. The write-enable terminai can be driven from standard TTL circuits without a pullup
resistor. The data input is disabled when the read mode is selected. When W goes low prior to CAS (early write).
data out remains in the high-impedance state for the entire cycle permitting a write operation independent of
the state of OE. This permits early-write operation to be completed with OE grounded.
data In/out (001-004)
The high-impedance output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout
of two Series 54 TTL loads. Data out Is the same polarity as data in. The output is in the high-impedance
(floating) state until CAS and OE are brought low. In a read cycle the output becomes valid after all access times
are satisfied. The output remains valid while CAS and OE are low. CAS or OE going high retums it to the
high-impedance state.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, 1CXAS 77251-1443
SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041D - JANUARY 1891 - REVISED JUNE 1995
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-Impedance
state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-Impedance
state. Once in the low-impedance state, they remain in the low-impedance state until either OE or CAS is
brought high.
refresh
A refresh operation must be performed at least once every 16 ms to retain data. This can be achieved by strobing
each of the1024 rows (A0-A9). A normal read or write cycle refreshes all bits in each row that is selected. A
RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh. Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished
by holding ~ at VIL after a read operation and cycling RAS after a specified precharge period, similar to a
RAS-only refresh cycle. The external address is ignored during the hidden refresh cycles.
CAS-before-RAS (CBR) and hidden refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter tcSIV and holding it low after RAS'
falls (see parameter tCSR)' For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored and the refresh address is generated internally. During CBR refresh,cycles the
outputs remain in the high-impedance state.
Hidden refresh can be performed while maintaining valid data at the output pins. This is accomplished by
holding CAS at VIL after a read operation. RAS is cycled after the specified read cycle parameters are met.
Hidden refresh can also be used in conjunction with an early-write cycle. CAS is maintained at VIL while ~
is cycled, once all the specified early-write parameters are met. Externally generated addresses must be used
to specify the location to be accessed during the initial RAS cycle of a hidden refresh operation. Subsequent
RAS cycles (refresh cycles) use the internally-generated addresses and the external address is ignored.
power up
To achieve proper device operation, an initial pause of 200 jl.8 followed by a minimum of eight initialization cycles
is required after full Vee level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CBR) cycle.
test mode
An Industry standard Design For Test (OFT) mode is incorporated in the SMJ44400. A CBR with W low (WCBR)
cycle is used to enter test mode. In the test mode, data is written into and read from eight sections of the array
In parallel. All data is written into the array through 001. Data is compared upon reading and if all bits are equal,
all DO pins go high. If anyone bit is different, all the DO pins go low. Any combination read, write, read-write,
or page-mode can be used in the test mode. The test mode function reduces t~st times by enabling the
1M x 4-bit DRAM to be tested as if it were a 512K DRAM where column address 0 is not used. A RAS-only or
CBR refresh cycle is used to exit the OFT mode.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77251-1443
SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041D - JANUARY 1981 - REVISED JUNE 1996.
logic aymbol t
AD
A1
A2
A3
A4
AS
AS
A7
AS
AS
RAM 10241( )( 4
•
20010/2100 ..
10
11
12
14
15
0
> A 1 048575
18
17
18
5
4
r-.. 20D19/21Dt '"
~
~
23
3
22
DQ1
DOZ
DQ3
DO.
C21[Column]
G24
~&
1>23C22
24,25EN
r-.. 2321D
-is
1
2
C20[Row]
G231[Refreah Row]
24[power Down]
4-
r
A,22D
V2S
A;Z28
24
25
t This symbol is in accordance with ANSVIEEE Std 91-1984 and lEe Publication 817-12. The pinouts illustrated are for the HL package.
functional block diagram
AD
Column Decode
A1
•
•
AS
•
Column
Addresa
Bune...
Sense Amplille...
12SKAnay
12SKArray
128KAnay
R
0
128KAnay
w
•
•
•
Row
Addresa
Buffa...
•
••
D
e
••
c
•
0
d
e
DQ1-Do.
128KArray
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 1EXAS 77251-1443
SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041D-JANUARY 1991-REVlSEDJUNE 1995
absolute maximum ratings over operating temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) .. .. .. . • . .. . . . .. . .. .. • . .. . • .. . .. .. . • . • • • • . . • . • •• - 1 V to 7 V
Voltage range on Vee •...•..•...............•.....••.•.•.••.•.••.•.•.•••.•••••••.••• - 1 V to 7 V
Short-circuit output current .........•.......................•.•..•.•...•.•.••.•••••••...... 50 rnA
Power dissipation ........•..•.•.•...•.•.....•..••..••••.•.•..•.••.•••••.•.••••.••.•.•••••••• 1 W
Operating temperature range, TA . . . . . • • • . . • . • . . • . • . . . . • . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
Storage temperature range, Tstg ..............•..•................................ - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. ThRe ere stress ratings only, and
functional operation of the device at these or any other condltlons beyond those Indicated under "recommended operating conditions" Is not
Implied. Exposure.to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with rasped to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
VIH
High-level Input voltage
2.4
8.5
V
VIL
Low-level Input voltage (see Note 2)
-1
0.8
V
TA
Minimum operating temperature
UNIT
V
·C
-55
·C
TC
..
..
..
NOTE 2: The algebrBIC convention, where the more negative 0- positive) limit IS designated as minimUm, IS used for Iogic-voltage levels only•
Maximum operating case temperature
125
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
.
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
'44400-80
'~10
MIN
MIN
MAX
2.4
10H --5mA
lOt.: ,,4.2 mA
=
II
Input current Oeakage)
VCC 5.5 V,
VI" 0 Vto 8.5 V,
All other pins = 0 V toVcc
10
Output current (leakage)
VCC=5.6V,
CAS high
VO=OVtoVCC.
ICCI
Read- or wri!e-cycle
current (see Note 3)
VCC .. 5.5V.
Minimum cycle
IC02
Standby current
After 1 memory cycle,
RAS and ~ high,
VIH-2.4V
1003
Average refresh current
(RAS only, or CBR)
(see Note 3)
Minimum cycle.
VCC-5.5V,
RAS cycling.
~ high (RAS only),
RAS low after CAS low (CBR)
ICC4
Average page current
(see Note 4)
VCC=5.5V,
tpc .. minimum.
RASlow,
CAS cycling
. '44400-12
MAX
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
:1:10
:1:10
:1:10
I&A
:1:10
:1:10
:1:10
I&A
85
80
70
mA
4
4
4
mA
85
75
85
rnA
60
40
35
mA
NOTES: 3. Measured with a maximum of one address change while RAS .. VIL
4. Measured with a maximum of one address change while CAS = VIH
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-89
SMJ44400
1 048 576-WORD BY ~BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041D-JANUARY 1991 - REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-alr temperature,
f = 1 MHz (see Note 5)
.
PARAMETER
MIN
MAX
UNIT
pF
7
pF
10
CIIRC) Input capacitance, strobe Inputs
Input capacitance, write-enable Input
10
pF
CI(W)
Output capacitance
pF
10
Co
NOTE 5: Vee. 5 V :t 0.5 V and the bias on pins uncle!' taat Is 0 V. ~ce Is sampled only at Initial design and after any major change.
CIIA)
Input capacitance, address inputs
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'44400-80
MIN
MAX
'44400-10
MIN
MAX
'44400-12
MIN
MAX
UNIT
Access time from column address
Access time from CA§" low
40
45
55
n8
tcAC
20
25
30
ns
tePA
tRAC
Access time from column precharge
Access time from RAS low
45
50
55
80
100
120
ns
ns
toEA
Access time from OE low
Output disable time after CA§" high (see Note 6)
20
25
20
25
30
30
30
lAA
toFF
ns
ns
25
ns
20
toEZ Output disable lime after OE high (see Note 6)
NOTE 6: toFF and toEZ are speclfiad when the output is no longer driven. The outputs are dl88blad by bringing eHher OE or CAS high.
~TEXAS
8-70
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 'TEXAS 77251-1443
SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041D-JANUARY 1891-REVlSEDJUNE 1896
timing requirements over recommended ranges of supply voltag. and op.ratlng fr....lr
t.mperature
'44400-80
MIN
MAX
'44400-10
MIN
MAX
'44400-12
MIN
MAX
UNIT
tRC
Cycle time, random reed or write (see Note 7)
150
180
210
IRwc
tpc
Cycle time, read-write
205
245
285
na
na
118
tpRWC
Cycle time, page-mode read-write
!RASP
Pulse duration, page mode, RAS low (see Note 9)
80
100000
100
100000
120
100000
!RAS
Pulse duration, nonpage mode, RAS low (see Note 9)
80
10000
100
10000
t20
10000
teAS
tep
Pulse duration, CAS low (see Note 10)
20
10000
25
10000
30
10000
Pulse duration, CAS high
10
10
15
na
na
na
na
na
tRP
Pulse duration, RAS high (precharge)
80
70
80
ns
twP
Pulse duration, write
15
20
25
ns
tASC
Setup time, column address before CAS low
0
0
0
tASR
Setup time, row address before RAS low
0
0
0
tos
Setup time, date (see Note 11)
0
0
0
tRCS
Setup time, read before CAS low
0
0
0
tcwL
Setup time, W low before CAS high
20
25
30
tRWL
Setup time, W low before RAS high
20
25
30
na
na
na
na
na
na
twcs
Setup time, W low before CAS low
(early-write oparatlon only)
0
0
0
ns
twSR
Setup time, W high (CBR refresh only)
10
10
teAH
toHR
Hold time, column address after CAS low
15
20
10
20
ns
Cycle time, page-mode read or write (see Note 8)
50
80
85
100
120
135
ns
Hold time, data after RAS low
60
75
90
ns
IoH
tAR
Hold time, date (see Note 11)
15
20
25
Hold time, column address after RAS low (see Note 10)
80
75
90
tRAH
Hold time, row address after RAS low
10
15
15
tRCH
Hold time, reed after CAS high (see Note 12)
0
0
0
tRRH
Hold time, reed after AAS high (see Note 12)
0
0
0
twCH
Hold time, write after CAS low (early-write operation only)
15
20
25
na
na
na
na
na
na
twcR
Hold time, write after RAS low (see Note 10)
80
75
90
ns
twHR
Hold time, W high (CBR refresh only)
10
10
10
ns
toEH
Hold time, OE command
20
25
30
ns
tROH
Hold time, RAS referenced to OE
20
25
30
ns
tAWO
Delay time, column address to W low
(read-write operation only)
70
80
90
ns
teHR
Delay time, RAS low to CAS high (CBR refresh only)
25
ns
Delay time, CAS high to AAS low
20
0
20
teRP
0
0
ns
tcsH
Delay time, AAS low to CAS high
80
100
120
ns
teSR
Delay time, CAS low to AAS low (CBR refresh only)
10
10
10
ns
Delay time, CAS low to W low (read-write operation only)
50
80
70
na
lewD
NOTES: 7. All cycle times assume IT • 5 ns.
8. To assure tpc mln,lAsc should be :a !cp.
9. In a read-write cycle, tRWD and tRWL must be observed.
10. In a read-write cycle, Iew~d ~L must be observed.
11. Referenced to the later of CAS or W in write operations
12. Either tRRH or IRCH must be satisfied for a read cycle.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-71
SMJ44400
1 048 57&oWORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SOMS041D-JANUARY 1891-REVlSEDJUNE 1985
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (continued)
'44400-80
MIN MAX
'44400-10
'44400-12
MIN
MAX
MIN
MAX
20
50
20
85
tRAO
Delay time, ~ low to column address (see Note 13)
15
tRAL
Delay time, column address to AAS high
40
teAL
tRCD
Delay time, column address to CAS high
40
Delay time, AAS low to CAS low (see Note 13)
20
Delay time, AAS high to CAS low
Delay time, CAS low to RAS high
20
25
0
25
110
135
0
0
tRPC
lASH
tRWD
tell
toED
tREF
tr
40
50
50
80
0
Delay time, AAS low to Wlow (read-write operetlon only)
CAS to output In low Z (lee Note 14)
l>E to data delay
65
25
0
30
180
75
18
08
90
nl
nl
nl
08
nl
nl
18
18
08
nl
0
30
25
20
Refresh time Intarval
65
UNIT
me
Tra08ltlon time (see Note 15)
NOTES: 13. Maximum value Ipecified only to assure access time.
14. valid data is presentad at the outputs after all access times are satisfied but can go from the high-impedance state to an Invalid-data
state prior to the specified access times as the outputs are driven when CAS and OE are low.
15. Transition times (rise and faI~ for AAS and CAS are to be a minimum of 3 08 and a maximum of 50 08.
PARAMETER MEASUREMENT INFORMATION
IV
'1VRL
.21.0
"-""'--:-1T
Output Und.rTeat - - . - - - .
CL-l00pF
Note A)
.fVVV
~~.Q,Q,~"'t"-""'"+"~~::tA
I+-teWL-.i
I
L..o
...
I
_
i""WL
i'l _
w~I!1
I
I
Don't Care
_ _- I V V.nAA/'Ou'VV"V
VVVV\A
'- I
I I~
II I.
I
I
~teWD---+I
I
I
I~ tAWD ----.!I
I
14
II IlAWD~ 1l1li
.1 twp
~III
111I
I
"'1
\lI ~
I -+I I ~
I I
14-- tePA --+I
I
I
lAcs
I I
14
.1 toEH
I
14! ~I tAA
I!.- tDH -+i
I
Valid Out
I
I4-lAAC I~·
~ ~t
I
I (SH Note A) I
~teAcl I OS ~I
I
I~
DQ1-
DQ4
I
teLZ -+i 1.4 I
Note A)
~
j4"- toEA -+I I
*-
(SH
()E~
I
Valid
In
_
Valid Out
toEZ I
I+- toEH ~
Valid
)>rl------
.In,1
14
I
~I
I
\.J
I
toED
.k:v::vvvv
~.
I
NOTES: A. Valid data Is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an
invalid-data stete prior to the specified access times as the outputs are driven when CAS and OE are low.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not
violated.
Figure 8. Enhanced-Page-Mode Read-Write-Cycle TIming
~TEXAS
INSTRUMENTS
POST OFFICE BOX 14043 • HOUSTCN. TEXAS 77261-14043
8-79
SMJ44400 '
1 048 576-WORD BY 4-B11
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041D- oWIUARY 1991 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
~c
~
l!+-lRAs-+!
_ _ _ _ _ _ _ _~_~I I
RAt
tcRPrll
I
CAS
~::¥-~*::~
IASR
. AO-A9
Vi
DQ1-DQ4
~ ~ IT
I
I
II
r---+' 4
~mm~"""'"'~!'ft'7*~~KC~~~P'("ft'~~"""'"'~
Row
I
I
I
~~tRP~\'-__
I+-+!- ~pc
I
W
~AH
)@:~Eft'ftn~~'ft7'I~~-»<
Row
0§0m§§0§00§§m§C;~~~;~
~:;K{;;
OE~;~r;::~
Figure 9. RAS-Only Refresh Timing
-!I1TEXAS
8-80
INSTRUMENTS
POSTOFFlCE BOX 1443· HOUSTON, lEXAS 77251-1443
SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041D-JANUARY 11181-REVISEDJUNE 1995
PARAMETER MEASUREMENT INFORMATION
twsR
I
1+1l1li--'.1--1 twHR
AO-AJ~:izr~a~:~
OE~:*~~~*:~
DQ1-DQ4
-------------HI-Z------------Rgure 10. Automatlc-CBR-Refresh-Cycle TIming
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. 'IEXAS 77251-1443
8-81
SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041D':' JANUARY 1891 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
NOTE A: Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an
Invalid-data atate prior to the specified access times as the outputs are driven when CM and OE are low.
Figure 11. Hldden-Refresh-Cycle (Read) Timing
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lEXAS 7721i1-1443
SMJ44400
1 048 576·WORD BY 4-B11
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041D-JANUARV 1891-REVISEDJUNE 1895
PARAMETER MEASUREMENT INFORMATION
Figure 12. Hidden-Refresh-Cycle (Write) nmlng
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-83
SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041D -JANUARY 1991 - REVISED JUNE 1895
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAB 77251-1443
SMJ416100
16m216-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS045C- NOVEMBER 1992 - REVISED JUNE 19116
FNCPACKAOE
(TOP VIEW)
• Organization ••• 16777216 )( 1 Bits
• Single 5-Y Power Supply (10% Tolerance)
• Performance Ranges:
'416100-70
'416100-80
'416100-10
ACCESS
TIME
ACCESS
TIME
tRAC
'cAC
(MAX)
(MAX)
(MAX)
(MIN)
70 ns
80 ns
100 ns
18 ns
20 ns
25 ns
35 ns
40 ns
45 ns
130 ns
150 ns
180 ns
VCC
ACCESS READ
TIME OR WRITE
lAA
CYCLE
• Enhanced Page-Mode Operation for Faster
Memory Access
• CAS-Before-RAS (CBR) Refresh
• Long Refresh Period:
4096 Cycles Refresh In 32 ms
• 3-State Unlatched Output
• Low Power Dissipation
• All Inputs, Outputs and Clocks Are
TTL Compatible
• Operating Free-Air Temperature Range:
- 55°C to 125°C
description
The SMJ416100 series is a set of high-speed
16777216-bit
dynamic
random-access
memories (DRAMs}, organized as 16777216-bit
words by one bit each. They employ enhanced
performance implanted CMOS (EPIC"') technology for high performance, reliability, and low
power. These devices feature maximum RAS
access times of 70 ns, 80 ns, and 10 ns.
All inputs, outputs, and clocks are compatible with
Series 54 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data
out is unlatched to allow greater system flexibility.
VSS
D
Q
NC
W
RAS
Al1
NC
CAS
NC
AS
A10
AS
AD
A7
A1
AS
A2.
AS
A4
A3
E;;;..._ _~
VCC
VSS
HKBPACKAGE
(TOP VIEW)
D
NC
W
RAS
All
NC
NC
Al0
4
,25
5
6
7
24
23
22
8
21
20
19
18
17
16
15
9
10
11
12
AO
Al
A2.
13
14
A3
VCC
The SMJ416100 is offered in a 450-mil
24/28-terminal
surface-mount small-outline
leadless chip carrier (FNC suffix) and a 450-mil
28-lead flatpack (HKB suffix). The packages are
characterized
for
operation
from
- 55°C to 125°C.
3
28
27
28
1
2
VCC
Vss
Q
NC
CAS
NC
AS
NC
NC
A8
A7
A6
AS
A4
Vss
PIN NOMENCLATURE
AO-A11
CAS
D
NC
Q
RAS
IN
Vee
VSS
Address Inputs
Column-Address Strobe
Data In
No Internal Connection
Data Out
Row-Address Strobe
Write Enable
5-VSupply
Ground
EPIC Is a trademark of Texas Instruments Incowrated.
~1ExAs
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON, TEXAS 77251-1443
Copyrlgh1 C 1995, Texas Instruments Incorporated
8-85
SMJ416100
16777216-811
DYNAMICRANDOM·ACCESS MEMORY
SGMS045C - NOVEMBER 1992 - REVISED JUNE 1995
logic symbol t
RAM 16M,,1
AO
A1
A2
A3
A4
AS
AS
A7
AS
A9
A10
A11
10
11
12
13
16
17
18
19
20
23
9
6
30012/2100
0
A 16 777 216
31D~3/21D11
"
5
.~
r.....
25
W
4
D 2
~
~
C30[ROW]
G33 (REFRESH ROW]
34(PWRDWN]
C31 (COL]
G34
"
3331D
A,32D
> 33C32
34 EN
AV
27
Q
tThi8 symbol Is In accordsncewith ANSI/IEEE Std 91-1984 and lEO Publication 817-12.
functional block diagram
AO
A1
A11
Column D.cod.
•
•
•
•
•
•
ColumnAdd .....
Buffe...
S.ns. Ampllfl....
256KArray
256KArray
••
•
RowAddresa
Buffe...
256KArray
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
D
Q
SMJ416100
16m216-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS045C- NOVEMBER 1992 - REVISED JUNE 1896
operation
enhanced page mode
Page-mode operation allows effectively faster memory access by keeping the same row address and strobing
random column addresses onto the chip. The time required to set up and strobe row addresses for the same
page is eliminated. The maximum number of 'columns that can be addressed is determined by tRAS, the
maximum RAS low time.
The column-address buffers in this CMOS device are activated on the falling edge of RAS. They act as a
transparent or flow-through latch while CAS is high. The falling edge of CAS latches the addresses Into these
buffers and also serves as an output-enable. This feature allows the SMJ4161 00 to operate at a higher data
bandwidth than conventional page-mode parts because retrieval begins as soon as the column address is valid
rather than when CAS transitions low. The performance improvement is referred to as enhanced page mode.
A valid column address can be presented Immediately after row-address hold time is satisfied, usually well in
advance of the falling edge of CAS. In this case, data is obtained after tcAC maximum (access time from CAS
low) if tAA maximum (access time from column address) and ~C are satisfied. If the column address for the
next cycle is valid at the time CAS goes high, access time is determined by the later occurrence of tCPA or tcAC'
address (AO-A11)
Twenty-four address bits are required to decode 1 of 167n 216 storage-cell locations. Twelve row-address bits
are set up on Inputs AO through A11 and latched during a normal access and during RAS-only refresh as the
device requires 4096 refresh cycles. Twelve column-address bits are set up on AO through A11 and latched onto
the chip by CAS. All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip enable In that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select,
activating the output buffer as well as latching the address bits into the column buffer.
write enable (W)
The read or write mode Is selected through W. A logic high on W selects the read mode and a logic low selects
the write mode. W can be driven from standard TTL circuits without a puliup resistor. The data input is disabled
when the read mode is selected. When W goes low prior to CAS (early write), data out remains in the
high-Impedance state for the entire cycle, permitting common I/O operation.
d.ta In (0)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling of CAS
or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS and data
Is strobed In by CAS with setup and hold times referenced to this signal. In a delayed-write or read-modify-write
cycle, CAS is already low and data is strobed in by W with setup and hold times referenced to this signal.
data out CQ)
The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 54 TTL loads. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle,
the output becomes valid at the latest occurrence oftRAC, tAA, tcAC, or tePA and remains valid while CAS is low.
CAS going high returns it to the high-impedance state. In a delayed-write or read-modify-write cycle, the output
does not change but retains the state just read.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77251-1443
8-87
SMJ416100
16777216-8IT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS045C - NOVEMBER 1992 - REVISED JUNE 1995
refresh
A refresh operation must be performed at least once every 32 ms to retain data by strobing each of the 4096
rows (AO-A11). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation
can be used by holding CAS at a high (inactive) level, conserving power because the output buffer remains in
the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. Hidden refresh
can be performed by h~ding CAS at VIL after aread operation and cycling RAS after the specified precharge
period, similar to a RA -only refresh cycle except with CAS held low. Valid data Is maintained at the output
throughout the hidden-refresh cycle. The external address Is Ignored and the hidden-refresh address is
generated internally.
CA!-before-RAS (CBR) refresh
CBR refresh Is utilized by bringing CAS low earlier than RAS (see parameter tcSR) and holding it low after
RAS falls (see parameter tcHA>. For successive CBR-refresh cycles, CAS can remain low while cycling
RAS. For this mode of refresh, the external addresses are ignored and the refresh address is generated
intemally.
power up
To achieve proper device operation, an initial pause of 200 J1S followed by a minimum of eight Initialization cycles
is required after full Vee level is achieved. These eight initialization cycles must include at least one refresh
(RAS-only or CBR) cycle.
~1ExAs'
8-88
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lCXAS 77261-1443
SMJ416100
16m216-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS04SC- NOVEMBER 1892 - REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee . . . . . . . . . • . . . . • . • • • . . . • • • • . • . . • • . • . . . . . • . • . . • • • • . . . . . • . • .• -1 V to 7 V
Voltage range on any pin (see Note 1) ..•.••..•.......•.•••.....••••.••••••••••••••.••• - 1 V to 7 V
Short-circuit output current ....•...•......•.......••....•..•.......••..•..•..••••..••••.••• 50 rnA
Power dissipation •••••••................................•...•........•.••.....•••..••••••.. 1 W
Operating free-air temperature range, TA ..•••••...•.••....••..•...•.•........•.... - 55°C to 125°C
Storage temperature range, Tstg ..........•••....••.......•............•.••....•.• - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" Is not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
Vcc
Supply voltage
4.5
5
5.5
UNIT
VIH
High-level Input voltage
2.4
6.5
V
VIL
Low-level Input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
-55
125
·c
V
NOTE 2: The algebraic convention. where the more negative Oess positive) limit Is designated as minimum. is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH=-5mA
VOL
Low-level output voltage
IOL=4.2mA
II
Input current Oeakage)
VCC=5.5V.
VI =OVto 6.5V.
All others = 0 V to VCC
10
Output current (leakage)
ICC1
Read- or write-cycle
current (see Note 3)
1CC2 Standby current
'416100-70
MIN MAX
2.4
'416100-80
MIN MAX
2.4
'416100-10
MIN MAX
2.4
UNIT
V
0.4
0.4
0.4
V
:1:10
:1:10
:1:10
JAA
.. 10
.. 10
:1:10
JAA
80
70
60
mA
After one memory cycle.
RA§ and CAS high.
VIH .2.4 V (lTL)
2
2
2
mA
After one memory cycle.
RA§ and CAS high.
VIH = VCC - 0.2 V (CMOS)
1
1
1
mA
VCC= 5.5V.
Vo = 0 Vto VCC.
CAS high
VCC= 5.5V.
Minimum cycle
Average refresh current
Icca (RAS-only refresh or CBR)
(see Note 3)
Minimum cycle.
VCC=5.5V.
RAS cycling.
CAS high (RAS-only refresh).
RA§ low after CAS low (CBR)
80
70
60
mA
Average page current
ICC4 (see Note4)
VCC- 5•5V•
RASIow.
Minimum cycle.
CAS cycling
65
60
55
mA
5
5
5
mA
Minimum cycle.
VCC-5.5V.
RAS.VIH.
CAS=VIL.
Data out • enabled
. NOTES: 3. Measured with a maximum of one address change while RA§ • VIL
4. Measured with a maximum of one address change while CAS • VIH
5. Measured with indicated conditions following a normal read cycle
Standby current output
ICC7 enable (see Note 5)
-!!1TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-89
SMJ416100
16m21&-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS045C- NOVEMBER 1982 - REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-alr temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, AO-A1.1 t
9
pF
CUO)
Input capacitance, 0 t
8
pF
CURCl
Input capacitance, CAS and RAS t
8
pF
Input capacitance, wt
8
pF
CICWl
Output capacitance t
14
pF
Co
t Input capacitance for ZIP (SV suffix) package Is 12 pF.
NOTE 6: Capacitance Is sampled only at initial design and after any major changes. Samples are 1eated at 0 V and 25°C with a 1-MHz signal
applied to the terminal under test. All other terminals are open.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 7)
PARAMETER
'416100·70
'416100·80
'416100·10
MIN
MiN
MIN
MAX
MAX
40
45
ns
25
ns
45
50
ns
80
100
ns
16
ns
25
ne
Access time from column address
!cPA
Access time from CAS low
Access time from column precharge
40
!RAC
Access time from RAS low
70
toEA
Access time from OE low
18
18
toFF
Output disable time after CAS high (see Note 6)
0
18
0
UNIT
20
tAA
!cAC
35
16
MAX
20
0
Output disable time after OE high (see Note 8)
18
0
20
0
25
·ns
0
toEZ
NOTES: 7. Valid data Is presented at the output after all access times are satisfied. Valid data can go from the hlgh·lmpedance state to an invalid
data state prior to the specified access times as the output is driven when CAS goes low.
6. toFF is specified when the output is no longer driven. The output is disabled by bringing CAS high.
~lExAs
INSTRUMENTS
8-90
POST OFFICE SOX 1443 • HOUSTON. lEXAS 77261-1443
SMJ416100
16m216-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS045C - NOVEMBER 1992 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature
'416100-70
MAX
'416100-60
MAX
UNIT
MIN
MIN
210
n8
56
n8
n8
tRC
Cycle time, random reed or write (see Note 9)
130
tRWC
tpc
Cycle time, read-write (see Note 9)
153
150
175
tpRWC
Cycle time, page mode read or write (see Notes 9 and 10)
Cycle time, page mode reed-write (see Note 9)
45
68
50
75
tRASP
Pulse duration, RAS low, page mode (see Note 11)
lRAs
Pulse duration, RAS low, nonpage mode (see Note 11)
teAS
tep
Pulse duration, ~ low (see Note 12)
tRP
Pulse duration, RAS high (precharge)
twP
Pulse duration, W low
tASC
Setup time, column eddress before ~ low
tASR
Setup time, row address before RAS low
70
70
18
10
50
10
0
0
0
Pulse duration, CAS high
'416100-10
MAX
160
MIN
100000
10000
10000
60
60
20
10
66
100000
100
10000
10000
100
26
10
ns
100000
10000
ns
10000
ns
ns
ns
60
70
ns
10
0
10
0
ns
0
0
0
ns
n8
20
0
26
20
25
ns
n8
tos
Setup time, data (see Note 13)
tRCS
Setup time, W high before ~ low
0
tcwL
Setup time, W low before CAS high
tRWL
Setup time, W low before RAS high
18
18
twcs
Setup time, W low before CAS low (early-write operation only)
0
0
0
ns
twRP
Setup time, W high before RAS low (CBR refresh only)
10
10
10
ns
teAH
tOH
Hold time, column address after CAS low
15
tRAH
Hold time, row eddress after RAS low
tRCH
Hold time, W high after ~ high (see Note 14)
16
10
0
16
15
10
ns
Hold time, data (see Note 13)
15
16
0
ns
tRRH
Hold time, W high after RAS high (see Note 14)
twCH
Hold time, ViI low after CAS low (early-write operation only)
!wAH
tRHCP
0
0
10
0
ns
ns
ns
ns
0
15
10
6
16
10
ns
Hold time, W high after RAS low (CBR refresh only)
0
15
10
Hold time, RAS high from CAS precharge
40
45
ns
tAWO
Delay time, column address to W low (read-write operation only)
36
40
50
45
teHR
Delay time, RAS low to CAS high (CBR refresh only)
10
10
20
ns
teRP
Delay time, CAS high to RASlow
Delay time, RAS low to CAS high
5
70
5
60
6
100
ns
tcsH
teSR
Delay time, CAS low to RAS low (CBR refresh only)
5
10
ns
tcwo
Delay time, CAS low to W low (read-write operation only)
6
18
20
25
ns
NOTES: 9.
10.
11.
12.
,13.
14.
ns
ns
ns
ns
All cycle times assume IT" 5 ns, referenced to VIH(mln) and VIL 23C22
23,20D
...... G25
24,25EN
r
"l
2
3
28
C21[ROW]
G23I[REFRESH ROW]
24[PWRDWN)
C2O[COLUMN]
G24
A,22D
4- 'i728
A,%28
27
tThll symbol 18 In accordance with ANSVIEEE Sid 91-1984 and lEO Publication 617-12.
Pin numberashown are for the FNO and HKB packages.
functional block diagram
AD
Column Decode
Sense Amplifiers
A1
A11
• Column• Add .....
• Buffers*
258KArray
R 258KArray
258KArray 0
••
•
• Row• Add.....
• Buffers
w
258KArray
••
•
D
e
c
0
d
e
258KArray
* Column address 10 and column address 11 are not usad.
~TEXAS
INSTRUMENTS
8-196
POST OFFICE lOX 1443 • HOUSTON. TEXAS 77251-1443
DQ1-DQ4
SMJ416400
4194304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS0420 - MARCH 1992 - REVISED JUNE 1995
operation
enhanced page mode
Page-mode operation allows effectively faster memory access by keeping the same row address and strobing
random column addresses onto the Chip. The time required to set up and strobe row addresses for the same
page is eliminated. The maximum number of columns that can be addressed is determined by tRAS, the
maximum RAS low width.
The column-address buffers in this CMOS device are activated on the falling edge of RAS. They act as a
transparent or flow-through latch while CAS is high. The falling edge of CAS latches the addresses Into these
buffers and also serves as an output enable. This feature allows the SMJ416400 to operate at a higher data
bandwidth than conventional page-mode parts because retrieval begins as soon as the column address Is valid,
rather than when CAS transitions low. The performance improvement is referred to as enhanced page mode.
Valid column address can be presented immediately after row address hold time has been satisfied, usually well
in advance of the falling edge of CAS. In this case, data is obtained after teAC maximum (access time from CAS
low) if tAA maximum (access time from column address) and toEA have been satisfied. When the column
address for the next cycle is valid at the time CAS goes high, access time is determined by the later occurrence
of tCPA or teAC.
address (AD-A11)
Twenty-two address bits are required to decode 1 of 4194304 storage-cell locations. Twelve row-address bits
are set on inputs AO through A11 and latched onto the chip by the row-address strobe, RAS. Ten
column-address bits are set on AO through A9 and latched onto the chip by the column-address strobe, CAS.
Row address A11 is required during a normal access and during RAS-only refresh as the device requires 4096
refresh cycles. All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to
a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select,
activating the output buffer, as well as latching the address bits into the column-address buffer.
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on W selects the read mode
and a logic low selects the write mode. W can be driven from standard TTL circuits without a pull up resistor.
The data input is disabled when the read mode is selected. When W goes low prior to CAS (early write), data
out remains in the high-impedance state for the entire cycle permitting a write operation independent of the state
of OE. This permits early-write operation to be completed with OE grounded.
data-lnJdata-out (DQ1-DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling of CAS
or W strobes data into the on-chip data latch. In the early-write cycle, W is brought low prior to CAS and data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed write or read-modify-write
cycle, CAS is already low; data is strobed in by W with setup and hold times referenced to this signal.
The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
series 54 TTL loads. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle,
the output becomes valid at the latest occurrence of tRAC, tAA, tCAC, or tePA and remains valid while CAS is low.
CAS going high returns it to the high-impedance state. In a delayed-write or read-modify-write cycle, the output
does not change, but retains the state just read.
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance
state. Both RAS and CAS must be brought low for the output buffers to go into the low-impedance state. Once
in the low-impedance state, the output buffers remain in the low-impedance state until either OE or CAS is
brought high.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77251-1443
8-107
SMJ416400
41943~WORDBY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS042D - MARCH 1992- REVISED JUNE 1$95
refresh
A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing
each of the 4096 rows (AO-A11). A normal read or write cycle refreshes all bits in each row that Is selected.
A RA§-only operation can be used by holding CAS at a high (inactive) level, conserving power as the output
buffer remains In the high-impedance state. Externa.!!l..aenerated addresses must be used for a RAS-only
refresh. Hidden refresh can be performed by holding CAS at VIL after a read operation and cycling RAS after
the specified precharge period, similar to a RAS-only refresh cycle except with CAS held low. Valid data Is
maintained at the output throughout the hidden-refresh cycle. An internal-refresh address provides the refresh
address during hidden refresh.
CAS-bafora-RAS (CBR) refresh
CBR refresh Is utilized by bringing CAS low earlier than RAS (see parametertcsR) and holding it low after RAS
falls (see parameter tcHro. For successive CBR refresh cycles, CAS can remain low while cycling RAS. For this
mode of refresh, the external addresses are ignored and the refresh address Is generated Internally.
power up
To achieve proper device operation, an initial pause of 200 j.tS followed by a minimum of eight initialization cycles
is reauired after full Vee level is achieved. These eight initialization cycles need to include at least one refresh
(RA -only or CBR) cycle.
absolute maximum ratings over operating free-alr temperaturet
Supply voltage range, Vee • • • . • . • . . • . . • • • . . • . . . . . . • . • . • . • • • • . • • . . • . • . . . . . • . . . • . . • . •. -1 V to 7 V
Voltage range on any pin (see Note 1) .......•.......•..•......•.•.••••••.••.•••••••••• - 1 V to 7 V
Short-circuit output current .••••.•.••.•.....•........•...•....•••••••••••••.••••••.•••••••• 50 mA
Power dissipation •.••......•..•.•....••.••..•.••••...•...•.•.••..••....•..•.•.•.•.••.•••••• 1 W
Operating free-air temperature range, TA ......•....•..••..•..•..•..•..•..•..•...•. - 55°C to 125°C
Storage temperature range, Tstg •.............•.......••..•..•.••.•••.•..•.•• ;.... - 65°C to 150°C
stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" 18 not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
t
recommended operating conditions
MIN
NOM
MAX
Vcc
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level Input voltage (see Note 2)
-1
0.6
V
UNIT
·c
Operating free-alr temperature
125
-55
TA
..
NOTE 2: The algebraic convention, where the more negative (lass POSitive) limit is deSignated as minimum,. used for logic-voltage levels only•
~TEXAS
INSTRUMENTS
8-108
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SMJ416400
4194304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042D - MARCH 1992 - REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH=-5mA
VOL
Low-level output voltage
10L= 4.2 mA
II
Input current peakage)
VI "OVt06.5V.
All others" 0 V to VCC
10
Output current peakage)
Vo '" 0 V to VCC.
CAS high
ICC1
Read- or write-cycle current
(see Note)
VCC .. 5.5V.
Minimum cycle
1CC2 Standby current
MIN
'416400-80
MAX
2.4
IIIN
'418400-10
MAX
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
%10
%10
%10
!IA
%10
%10
%10
!IA
80
70
60
rnA
VIH = 2.4 V (TTL).
After 1 memory cycle.
RAS and CAS high
2
2
2
mA
VIH = VCC - 0.05 V (CMOS).
After 1 memory cycle.
RAS and CAS high
1
1
1
mA
60
70
60
rnA
65
60
55
rnA
5
5
5
mA
ICC3
Average refresh current
(RAS only or CBR)t
RAScycling.
CAS high (RAS only).
RAS low after CAS low (CBR)
ICC4
Average page current
(see Note 4)t
RASlow.
Standby current
ICC7 output enablet
'416400-70
CAS cycling
CAS=VIL.
RAS=VIH.
Data out .. enabled
t Minimum cycle. Vee .. 5.5 V
NOTES: 3. Measured with a maximum of one address change while RAS .. VIL
4. Measured with a maximum of one address change while CAS = VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
MIN MAX UNIT
PARAMETER
pF
Input capacitance. AO-A11 *
9
CI(A)
pF
8
CI(RC) Input capacitance. RAS and CAS*
pF
8
CUOEl Input capacitance. oe*
pF
8
Input capacitanca. W*
CllWI
Co
*
Output capacitance
14
pF
Input capacitance for ZIP (SV 8uffix) package 18 12 pF.
NOTE 5: capacitance Is sampled only at Initial design and after any major change. Samplas are tested at 0 V and 25°C with a 1-MHz 81gnal '
applied to the pin under test. All other pins are open.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 - HOUSTON. TEXAS 77251-1443
8-109
SMJ416400
4194304-WORD BY 4-B11
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042D - MARCH 1992 - REVISED JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature (see Note 6)
.
'416400-70
PARAMETER
MIN
MAX
'416400-80
MIN
MAX
UNIT
40
45
ns
20
25
ns
45
50
ns
80
100
ns
25
25
ns
ns
tePA
lRAC
Acoess time from column precharge
Access time from RAS low
40
70
IOEA
Acoess time from OE low
Output dlssble I,me after CAS high (see Note 7)
18
18
20
20
0
MAX
18
Acoess lime from column-address
Acoess time from CAS low
toFF
MIN
35
teAC
lAA
'416400-10
0
0
Output dissble time after OE high (see Note 7)
0
18
0
20
0
25
ns
toEZ
NOTES: 8. Valid date Is presented at the outputs after all access times are setisfled but can go from the hlgh-lmpedance atete to an Invalld-date
alate prior to the specified access times as the outputs are driven when CAS goes low.
7. toFF and toEZ are specified when the outputs are no longer driven. The outputs are disabled by bringing either ~ or CAS high.
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature
'416400-70
'416400-80
'416400-10
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tRC
Cycle time, random reed or write (see Note 8)
130
150
180
ns
tRWC
tpc
Cycle time, reed-write (see Note 8)
Cycle time, page mode read or write (see Notes 8 and 9)
181
45
205
50
245
ns
tpRWC
Cycle time, page mode read-write (see Note 8)
98
105
tRASP
tRAS
tCAS
tcp
Pulse duration, RAS low, page mode (see Note 10)
Pulse duration, RAS low, nonpage mode (see Note 10)
Pulse duration, CAS low (see Note 11)
Pulse duration, CAS high
70 100000
70 10000
18 10000
120
100 100000
100 10000
25 10000
tRP
twp
Pulse duration, RAS high (precharge)
Pulse duration, W low
50
10
80
tASC
Setup time, column address before CAS low
tASR
Satup time, row address before RAS low
tos
Satup time, date (see Note 12)
0
80 100000
80
20
10
70
10
ns
ns
0
0
0
ns
0
0
0
ns
0
0
ns
0
25
IIIi
0
0
Setup time, W low before CAS high
18
20
tAWL
Setup time, iN low before RAS high
twcs
Setup time, W low before CAS low (early-write operation only)
Setup time, W high before RAS low (CBR refresh only)
18
0
20
0
ns
25
ns
ns
10
10
0
10
15
15
15
15
15
15
ns
ns
10
10
0
0
0
5
ns
ns
Hold time, row address after RAS low
10
Hold time, W high after CAS high (see Note 13)
0
tRCH
Hold time, iN high after AAS" high (see Note 13)
0
tRRH
NOTES: 8. All cycle times assume IT .. 5 ns, referenced to VIH(mln) and VIL(max)'
9. To assure !PC min, IAsc should be .. tcP.
10. In a read-write cycle, tRWO and tAWL must be observed.
11. In a read-wrlte cycle, tcwll!!!d tcWL must be Observed.
12. Referenced to the later of CAS or WIn write operations
13. Either tRRH or tRCH must be satisfied for a read cycle.
~1ExAs
8-110
ns
10
Satup time, W high before CAS low
teAH
tOH
tRAH
ns
ns
ns
tRCS
Hold time, column address after CAS low
Hold time, data (see Note 12)
10000
10000
ns
ns
10
10
tcwL
twRP
55
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON. 'TeXAS 77251-1443
ns
ns
SMJ416400
4194304-WORD BY 4-B11
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042D - MARCH 1992 - REVISED JUNE 1986
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (continued)
'416400·70
MIN
MAX
'416400·80
MIN
MAX
'416400·10
MIN
MAX
UNIT
twcH
Hold time, W low after CAS low (early-wrlte operation only)
15
15
15
ns
twRH
Hold time, W high after RAS low (CBR refresh only)
10
10
10
ns
toEH
tROH
Hold time, OE command
18
20
ns
Hold time, RAS referenced to l5E
10
10
25
10
lRHCP
tAWD
Hold time, RAS high from CAS precharge
45
70
50
80
ns
Delay time, column address to W low (read-write operation only)
40
63
teHR
tCRP
Delay time, RAS low to CAS high (CBR refresh only)
10
10
20
ns
Delay time, CAS high to RAS low
5
ns
Delay time, RAS low to CAS high
70
100
nl
teSR
Delay time, CAS low to RAS low (CBR refresh only)
5
5
80
5
5
teSH
10
nl
tcwo
Delay time, CAS low to Wlow (read-wrlte operation only)
48
50
60
ns
toED
tRAO
Delay time,l5E to data
18
20
Delay time, RAS low to column address (888 Notl 14)
15
40
25
15
55
lfW.
Delay time, column address to RAS high
35
teAL
tRCD
Delay time, column address to CAS high
35
Delay time, RAS low to CAS low (see Note 14)
60
75
tRPC
Delay time, RAS high to CAS low
20
0
45
45
20
tRSH
tRWD
Delay time, CAS low to RAS high
18
20
Delay time, RAS low to W low (read-write operetion only)
98
110
tepw
Delay time, Wlow after CAS precharge (read-write operatIon only)
63
tREF
Refresh time Interval
tr
Transition time (see Note 15)
35
15
40
52
40
20
0
70
32
ns
ns
ns
ns
ns
0
ns
25
135
ns
nl
80
32
ns
ns
nl
32
ml
NOTES: 14. The mBXImum value il lpeclfied only to assure access time.
15. Transition times (rise and fafQ for RAS and CAS are to be a minimum of 3 ns and a maximum of 30 ns.
~1EXAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251:-1443
8-111
SMJ416400
4194304-WORD BY 4-BIT
DYNAMIC'RANDOM-ACCESS MEMORY
SGM~~MARCH1~2-R~SEDJUNE1~
PARAMETER MEASUREMENT INFORMATION
5V
1.31 V
~
Output Under Teet
~
CL-100pF
C_NoteA)
R1-828D
RL-Z18Q
Output Under Teet - -.....- - .
T
CL-100pF
(_NoteA)
(b) ALTERNATE LOAD CIRCUrr
(8) LOAD CIRCUrr
VIH/VOH min VIL/VOLmax -
-=-==v
-'
--==.T\-._____
X
--J.
'-._ _
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and fixture capacitance.
B. The ac timing parameters ere specified with reference to the minimum valid high-level voltage and the maximum valid
low-level voltage for each signal. This corresponds to 2.4 V and 0.8 V for inputs; 2.4 V and 0.4 V for outputs with the
given load circuit.
Rgure 1. Load Circuits and Voltage Waveforms
~1ExAs
INSTRUMENTS
8-112
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ416400
4194304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042D - MARCH 1992 - REVISED JUNE 1896
PARAMETER MEASUREMENT INFORMATION
NOTE A: Output can go from the high-impedance state to an Invalld-clata state prior to the speclfl8d access time.
Figure 2. Read-Cycle Timing
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-113
SMJ416400
4194304-WORD BY 4-81T
.DYNAMIC RANDOM-ACCESS MEMORY
SGMS042D - MARCH 1992 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
Figure 3. Early-Write-Cycle Timing
~TEXAS
INSTRUMENTS
8-114
POST OFFICE BOX 1443 • HOUSTON. lEXAS 77251-1443
SMJ416400
4194304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042D- MARCH 1992 - REVISED JUNE 1885
PARAMETER MEASUREMENT INFORMATION
4 - - - - - - - - - - t R C - - - - - - - - -.....
~
I
,
~-----t~------~~,
~------------------------~~~---~P--~~~--14',.----~SH - -..
~
I
t e - - - tRCD
-----.;~I
,
~L.--teAS ---+'~ ,
1
1 1111,
~I!
teSH
~~~~~
,--tRAL
i+----!-:,- teAL
'..
I .
--~,
0
.
4
.
,
I,.
1111
,
,
----T,--+I~,
~:
_____
I
~"
teWL
tRWL
w~g~n~g~~_
---r
Jtt~i---teP---~~
~~~:Do~~~~.~~~.~~:~~~
Column
'os
teRP ---..~
14- teAH
---to!
I
I
,
~I
~""'~~~~~~~.~~~.*)~~~~
,:"'--twP-.l
+. .
~
I I,.
DQ'--88888:~~E~
toED -+j I+,
I
~I toH
~~~~~:~~o~"I'7'I'i~'"'·~:~~~~~
141111----toEH---~~
Figure 4. Write-Cycle TIming
-!I1lEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-115
SMJ416400
4194304-WORD BY 4-BIT
DYNAMIC· RANDOM-ACCESS MEMORY
SGMS0420 - MARCH 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
NOTE A: Output can go from the high-Impedance state to an invalld-data &tete prior to the specified access time.
Figure 5. Read-Write-Cycle TIming
~1ExAs
8-t16
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 71251-1443
SMJ416400
4194304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042D - MARCH 1992 - REVISED JUNE 1I11III
PARAMETER MEASUREMENT INFORMATION
Column
AO-11
I
I
I I
II
II
I j"
l4--tAcs ---t+I
II
I
~
1-
I
I
I
I
t
tAA --+--"1
I
r--+ tACH ---.I
I 'W ~tcACt-H
~
I
See NoteA
W~~tRAD~ I
I
I
I
I
I
I
I..
I
I
tcPAt
I
I
I
I
I
~ tcAC ---.II
~~--IAA
~I
I
I
IRAC-----.;~1
~I
I
I
I
I
I
~taFF---+I
I
I
I
DQl-DQ4--------See-N-ote-A-~
~
"c;~:
)-
I
I
1
I
I
I
I
1
ItaEZ
1
I
I
I 1+ taEZ
--.!
~taEA~
I
~~*;~~£~
I+- taEA -+I
~
I
t Access time is tepA, tcAc or tM dependent.
NOTE A: Output can go from the hlgh-lmpedance state to an Invalld-date state prior to the speclfled access time.
I
~
~I
~"""'
..,1
A§m
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-117
SMJ416400
4194304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042D- MARCH 1992- REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
I
~
I
I
1l1li
I
DQ1-DQ4
~
I I I ~tDH4
~ I I
I
~
~H
~
~
I
~S
I
I ~I
~
I
I
I~~~~~
I
~ '1~d ~:~~~g~~~
~I
jIIII
.
I
-+l!toED
I
I~
I
~:*~::*E:r
I
()E
j.- toEH --.I
I
SaaNottA
valldDa~ln
toEH
I
I
I
I
I
'«!:1:*~:§§
NOTES: A. Referenced to ~ or W, whichever occure last.
B. A r8ad cycle or a read-write cycJe can be Intermixed with a write cycle as long as read and read-wrlte timing speclflcatlons are not
Violated.
Figure 7_ Enhanced-Page-Mode Write-Cycle Timing
~TEXAS
8-118
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lCXAS 77251-1443
SMJ416400
4194304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042D - MARCH 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
1\r
tRP;U-,
~P------------------~:v'
, ,
,..
I,..,
teSH
'I~
"'I
, ','"
' ,,"
,.,
--+I
I
tRAD
AO-A11
~"
~IASR I
I
~ ~
II
teWD --.,
,
Itf-IAWD
II ,tRWD
}I,
_
"
,.. I .,
"
,
!.......L
~I
tePw~
~
~I
.1
,
,
teWL -.I
:
I ,
I'
tAA
, ,
~
I I
,
~tePA~
I
I'
1
I
,
,
.,
toEH
,
,
,
! A,!.,{::-"
~ ":' )>1-1-----,YalldOut'
1
, , YalidOut,
!
~
,
I
,
-.::..- toEZ :
r+-toEA-+l'
I"
I
tDH
I--+-tos,
-----~~ :,,!:d
I,
t4--IRWL
t{~ i~
,'
,
,
,".
,
["'I-I
§@§N
teRP~,1,.'
~,-.,.,
--------""::
I
~
+i'~ tRCS
I
.
,
nil'
,
F':
~ ~ )@§§w;,~m
I+r
"
~lRAc~
DQ1-DQ4
, ,"
I
~!!!
,
1-
'
"
I
:
,,
,
.',
"
J
IRSH ---~..,
-tep
-.I
~Ai. ~
I'
.,'
~ I'
teAS
·11,
,..
r-
Vi
IpRWC
IRCD
IRHCP
·1',
I ,..
,
~
,. . .!toEH
I
I..
I
I
I
~
:
toED
I
,
,
,
\..Jr---~~~~
NOTES: A. Output can go from the high-Impedance state to an Invalid-data state prior to the specified access time.
B. A read or write cycle can be Intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 8. Enhanced-Page-Mode Read-Wrlte-Cycle Timing
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-119
SMJ416400
4194304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS0420 - MARCH 1992- REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
CAS
~"-*~r!f:~
I rt'RAM
tASR -1+--+1
I
W
AO-A11 ~=:~ Row )«i'g:1i~]XIo...-_R_OW__
W~*rr~;~
DQ1-DQ4
~i;~~
OE
~*~g£~
Figure 9. RAS-Only Refresh Timing
W~
AO-A11~i*~~~~~
()E~;~*~g£~~~
DQ1-DQ4-------------HJ.Z------------
Figure 10. Automatlc-CBR-Refresh-Cycle Timing
~1ExAs
8-120
INSTRUMENTS
POST OFFICE BOX 1443° HOUSTON, TEXAS 77251-1443
SMJ416400
4194304-WORD BY 4-BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS042D - MARCH 1992 - REVISED JUNE 1985
PARAMETER MEASUREMENT INFORMATION
I+--
l---
M.mory Cycl. ~
I
I
I
I
I
~I
14
I
I
~I
I
I
14
I
I
RASN
I
I fRAs
I
I
¥T
II
iIN:
l---
lAp
I
I
I
I 14
N
I
14
~I
I
I
~: I tRAS I
J!
:!
I I
;+I f4+tcAH
I ~ l...LL
11
tRAH~~ I II
--+l
I
II
I
R.f....h Cycl.
I I
II
II
I I
R.f....h Cycl.
Row
I
I
I I
1 I
I
14
I
I
I
I
I
lAp
I~
1\
.... : !
II
tcHRIL.
~I
II!!I I ~
I
I I
II
II
I I
II
II
I I
1m-lAse
"'~llAsR!11
II
~I
_
AO-A11
--+l
I
I
I
~
eOI~Di~~~£.~
lARH-+j
I ~I tRcs
I I
I
I
f4-
II
I
~ ~twRH
I -+I j.-twRP
I
I
I
I
I
II
II
I I
-}.I .. twRH
I
1~twRP
I
III
I
II h-twRH
I
I
~twRP
~W
I
I
1
I
Figure 11. Hidden-Refresh-Cycle (Read) TIming
-!111ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-121
SMJ416400
4194304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042D - MARCH 1992- REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Figure 12. Hidden-Refresh-Cycle (Write) Timing
~1ExAs
8-122
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ416160, SMJ418160
1048576-WORD BY 16-BIT HIGH-SPEED DRAM
SGMS720A- APRIL 1995 - REVISED JUNE 1995
xxx PACKAGE
• Organization ••• 1048576 x 16
• Single S-V Power Supply (:t10% Tolerance)
• Performance Ranges:
ACCESS ACCESS ACCESS
TIME
TIME
TIME
'41xl6Q.80
'41xl60-70
'41xl8CJ.80
(TOP VIEW)
Vee L
READ OR
OCO
OC1
OC2
OC3
WRITE
'RAC
MAX
tcAC
MAX
tAA
MAX
CYCLE
MIN
60 ns
70 ns
60 n.
16 ns
18 ns
20 ns
30 ns
36 ns
40 n.
110 ns
130 ns
150 n.
VCC
OC4
OC5
OCS
OC7 l
• Enhanced Page-Mode Operation for Faster
Memory Access
• CAS-Before-RAS (CBR) Refresh
• Long Refresh Period
- '416160 - 4096 Cycle Refresh In 32 ms
(Max)
- '418160 -1024 Cycle Refresh In 8 ms
(Max)
• 30State Unlatched Output
• Low Power Dissipation
• Operating Free-Air Temperature Range
-55°C to 125°C
• Texas Instruments Enhanced Performance
Implanted CMOS (EPIC™) Process
• Alllnputs/Outputs Are TTL Compatible
• Packaging
50-Lead, 650-MII-Wlde Ceramic Flatpack
NC
NC
NC
NC
NC
NC
W
RAS
A11t L
A10t
AO
A1
A2
A3
Vee
description
The SMJ41x160 series Is a set of high-speed,
167n216-bit dynamic random-access memories organized as 1 048576 words of 16-bits each.
1°
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
J Vss
49
48
47
48
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
OC15
OC14
OC13
OC12
VSS
J
OC11
OC10
OCg
OCS
NC
NC
NC
NC
NC
J i:CAS
UCAS
DE
J A9
AS
A7
J AS
A5
J A4
Vss
t Al0 and All ale NC for SMJ418160.
PIN NOMENCLATURE
They employ state-of-the-art EPICTM technology
for high performance, reliability, and low power at
low cost.
AO-Al1
These devices feature maximum RAS access
times of 60 ns, 70 ns, and 80 ns. All addresses and
data-in lines are latched on-chip to simplify
system design. Data out is unlatched to allow
greater system flexibility.
NC
OE
000-0015
LCAS
UCAS
RAS
Vec
~S
w
Address Inputs
Data In/Data Out
Lower Column-Address Strobe
Upper Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
5-VSupply
Ground
Write Enable
The SMJ41x160 series Is offered in a 50-lead,
650-mll-wide ceramic flatpack and is characterized for operation from -55°C to 125°C.
EPIC Is a trademark of Texas Instruments InCOrporated.
~/;a
~1ExAs
.
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
Copyright C 1995. Texas Instruments Incorporated
8-123
SMJ416160, SMJ418160
1.048576·WORD BY 16·BIT HIGH·SPEED DRAM
SGMS72OA-APRIL 1995-REVlSEDJUNE 1995
logic symbol t
RAM1Mx16
AD
Al
A2
A3
A4
AS
21
22
23
24
27
28
2OD8/21oo ...
> Al~575
29
AS
30
A7
31
AS
32
AS
20
Al0*
19
All*
2OO15/21D7
20D16
20D17
20D18
20D19
~
I> C20[ROW]
RAS
"1:J
18
LeAS 35
:a
0
c
c:
~
I>
~
G231[REFRESH ROW]
24(PWRDWN]
C21
G24
&
31
UCAS 34
0
-I
~
I> C21
G34
&
31
"1:J
23C22
23C32
r +
Z31
:a
m
<
m
Vi 17
5! 33
-
DOD 2
:e
DOl
DQ2
D03
D04
D05
D06
D07
D08
3
4
5
7
8
9
10
41
42
43
44
46
23,21D
...
..,25
24,25EN27
34,25EN37
.
r
C.
A,22D
V26,27
A,Z26
L....
A,32D
V36,37
A,Z36
D09
DOlO
DOll
D012
47
D013
48
D014
49
D015
tThiSsymbolls In accordance withANSI/lEEE Stet 91-1984 and IEC Publication 617-12.
*A10andA11 are NCforSMJ418160.
~TEXAS
8-124
INSTRUMENTS
POST OFFICE SOX 1443· HOUSTON, l1:XAS 77251-1443
SMJ416160, SMJ418160
1048576-WORD BY 16·B11 HIGH·SPEED DRAM
SGMS72OA- APRIL 1995 - REVISED JUNE 1995
'416160 functional block diagram
~===t1=~--~-C~;;;;;;;;~~::~C~o~lu~m~n~D~R~od~e~:::L~~--~
•
•
•
A7---+-t1H
Column Addrsse
Buffers
Sen.e Amplifiers
•
A8----__
A11
4
256K Array
256K Array :
256K Arrsy
••
•
•
256K Array
w
•
RowAddrsa.
Buffers
~L-
••
D
•
e
c
'iI•••
o
II
d
e
____J
OQO-DQ15
256KArrsy
256KArray
:=w
~
'418160 functional block diagram
a:
a.
t;
::l
C
AO
A1
A9
oa:
Column Decode
•
•
•
•
•
•
a.
ColumnAddrsse
Buffers
256KArrsy R
0
w
••
•
RowAddrsaa
Buffers
256KArray
D
e
•
••
e
0
d
e
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8·125
SMJ416160, SMJ418160
1048576·WORD BY 16·BIT HIGH·SPEED DRAM
SGMS72OA- APRIL 1995 - REVISED JUNE 1995
operation
dualCAS'
Two CAS terminals (LCAS and UCAS) are provided to give independent control of the 16 data-I/O terminals
(OQO-OQ15), with LCAS corresponding to OQO-OQ7 and UCAS corresponding to OQ8-0Q15. For read or
write cycles, the column address is latched on the first xCAS falling edge. Each xCAS going low enables its
corresponding OQx pin with data associated with the column address latched on the first falling xCAS edge.
All address setup and hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS
low to valid data out (see parameter loAd is measured from each individual xCAS, to its corresponding OQx
terminal.
In order to latch in a new column address, both XCAS terminals must be brought high. The column-precharge
time (see parameter lop) is measured from the last )(CAS rising edge to the first xCAS falling edge of the new
cycle. Keeping aSlumn address valid whiletogglingxCAS requires amlnlmum setup time, loLCH. OuringtCLCH,
at least one xCA must be brought low before the other xCAS is taken high.
For early-write ~s, the data is latched on the first XCAS falling edge. Only the OQs that have the
corresponding XCAS low are written into. Each xCAS must m~S minimum in order to ensure writing
into the storage cell. To latch a new address and new data, all xCAS terminals must be high and meet lop.
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum
number of columns that can be accessed is determined by the maximum RAS low time and the XCAS
page-mode ~e time used. With minimum xCAS page-cycle time, all columns can be accessed without
Intervening RAS" cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of R7lS. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the
first XCAS latches the column addresses. This feature allows the device to operate at a higher data bandwidth
than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather
than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after tRAH (row-address hold time) has been satisfied, usually
well in advance ofthe falling edge of xCAS. In this case, data is obtained after loAC maximum (access time from
xCAS low) if tAA maximum (access time from column address) has been satisfied. In the event that column
addresses for the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle
is determined by tCPA (access time from rising edge of the last xCAS).
address: AO-A11 (,416160) and AO-A9 (,418160)
TWenty address bits are required to decode one of the 1048576 storage cell locations. For the SMJ416160,
12 row-address bits are set up on AO through A11 and latched onto the chip by RAS. Eight column-address bits
are set up on AO through A7 and latched onto the chip~he first xCAS. For the SMJ418160, 10 row address
bits are set up on AO-A9 and latched onto the chip by RAS. Ten column address bits are set up on AO-A9 and
latched onto the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and
xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. xCAS
is used as a chip select, activating its corresponding output buffer and latching the address bits into the
column-address buffers.
write enable (W)
The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to xCAS
~Iy write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded.
~TEXAS
8-126
INSTRUMENTS
POST OFFICE BOX 1443.· HOUSTON, 1EXAS 77251-14013
SMJ416160, SMJ418160
1048576·WORD BY 16·BIT HIGH·SPEED DRAM
SGMS720A- APRIL 1995 - REVISED JUNE 1995
data In (DQO-DQ15)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of xCAS or W strobes data Into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data is strobed in by the first xCAS occurrence with setup and hold times referenced to this signal. In
a delayed-write or read-modify-write cycle, xCAS is already low and the data is strobed in by W with setup and
hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the
output buffers to the high-Impedance state prior to impressing data on the I/O lines.
data out (DQO-DQ15)
Data out is the same polarity as data in. The output is in the high-Impedance (floating) state until xCAS and OE
are brought low. In a read cycle, the output becomes valid after the access time interval tCAC (which begins with
the negative transition of xCAS) as long as tRAC and tAA are satisfied.
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-Impedance
state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-Impedance
state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into the
low-impedance state, and they remain in the low-impedance state until either OE or xCAS is brought high.
RAS-only refresh '416160
A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing
each of the 4096 rows (AO-A11). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the
output buffers remain In the high-L,:;t;dance state. Externally generated addresses must be used for a
RAS-only refresh.
RAS-only refresh '418160
A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by strobing
each of the 1024 rows (AO-A9). A normal read or write cycle refreshes all bits in each row that is selected. A
RAS-only operation can be used by holding both xCAS at the high Onactive) level; conserving power as the
output buffers remain in the high-impedance state. Externally generated addresses must be used for a
RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding
xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle. The external address is ignored and the refresh address is generated internally.
xCAS-before-RAS (xCBR) refresh
xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter tcsR> and holding
it low after RAS falls (see parameter tCHR)' For successive xCBR refresh cycles, xCAS can remain low while
cycling RAS. The external address is ignored and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 !.IS followed by a minimum of eight initialization cycles
is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh
(RAS-only or xCBR) cycle.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443
• HOUSTON. TEXAS 77251-1443
8-127
~
~
a:
a.
t;
::l
C
oa:
a.
SMJ416160, SMJ418160
1048576-WORD BY 16-BIT HIGH-SPEED DRAM
SGMS72OA-APRIL 1995-REVlSEDJUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee: .......................................................... - 1 V to 7 V
Voltage range on any pin (see Note 1): ................................................ -1 V to 7 V
Short-circuit output current ..............•...•........•..•.••.....•••..•••••..•...•.••.•••. 50 mA
Power dissipation .•...........•.••..•••••••.............•••....•.••.••••••••.••.•••••••••.• 1 W
Operating free-air temperature range, TA .......................................... - 55°C to 125°C
Storage temperature range, Tstg .................................................. - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions· Is not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to Vss.
recommended operating conditions
-a
~
Vee
VSS
VIH
VIL
TA
MIN
4.5
Supply voltage
Supply voltage
High-level Input voltage
MAX
5.5
UNIT
V
V
-1
6.5
0.8
V
V
-55
125
"C
2.4
Low-level input voltage (see Note 2)
Operating free-air temperature
NOM
5
0
NOTE 2: The aI~ebraiC convention, where the more negative Qess positive) limit Is designated as minimum, Is used for logic-voltage levels only.
C
c:
~
-a
::JJ
-~
~
~TEXAS
8-128
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ416160, SMJ418160
1048576-WORD BY 16-B11 HIGH·SPEED DRAM
SGMS72OA- APRIL 1995 - REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)
SMJ416160
PARAMETER
TEST CONDITIONSt
VOH
High-level output
voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
ICC1*'
Read- or write-cycle current VCC- 5.5V,
ICC2
ICC3§
Standby current
Average refresh current
(RAS only refresh or CBR)
ICC4*' Average page current
MIN
IOL-4.2rnA
VI =OVto6.5V,
VCC=5.5V,
All others = 0 V to VCC
=
Vcc 5.5 V,
xCAShlgh
MAX
2.4
IOH=-5mA
VO" OVtoVCC.
'418160-80
'418160-70
'418160-60
MIN
MAX
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
:1:10
:1:10
:1:10
j.iA
:1:10
:1:10
:1:10
j.iA
90
60
70
rnA
VIH = 2.4 V (TTL).
After one memory cycle,
RAS and xCAS high
Minimum cycle
2
2
2
mA
VIH = VCC - 0.2 V (CMOS),
After one memory cycle.
RAS and xCAS high
1
1
1
mA
90
VCC .. 5.5V,
RASlow,
90
tpC" MIN,
xCAScycling
60
70
mA
~
a:
Standby current, outputs
RAS=VIH,
xCAS=VIL.
5
enabled
Data out - enabled
..
.
.
t For conditions shown es MIN/MAX. use the appropriate value specified In the timing requirements .
* Measured with outputs open
§ Measured with a maximum of one address change while RAS • VIL
11 Measured with a maximum of one address change while xCAS .. VIH
ICC7*'I
~.
W
Minimum cycle,
VCC-5.5V,
RAS cycling.
XCAS high (RAS only).
RAS low after xc;iS low (CBR)
60
70
rnA
5
5
rnA
D.
o
::l
Q
oa:
D.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77261-1443
8-129
SMJ416160, SMJ418160
1048576-WORD BY 16-BIT HIGH-SPEED DRAM
SGMS72OA- APRIL 1995- REVISED ~UNE 1896
electrical characteristics over recommended ranges of supply voltage .and operating free-alr
temperature (unless otherwise noted)
SMJ418160
PARAMETER
VOH
High-level output
voltage
VOL
Low-level output wltege
II
Input current Oeekage)
10
Output current Oeekage)
ICC1:!:§
Read- or wrlte-cycle current VCC= 5.5V.
Minimum cycle
VIH = 2.4 V (TTL.).
After one memory cycle.
RAS and iCAS high
Standby current
VIH .. VCC - 0.2 V (CMOS).
After one memory cycle.
RAS and iCAS high
ICC2
"tJ
:D
oC
ICC3§
C
~
"tJ
:D
-~~
TEST CONDrrlONst
Average refresh current
(RAS only refresh or CBR)
ICC4:!:' Average page current
'418160~60
MIN
'418160-70
MAX
2.4
IOH--5mA
'418160-60
MAX
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
:1:10
:1:10
:1:10
lolA
:1:10
:1:10
.. 10
lolA
190
180
170
mA
2
2
2
mA
1
1
1
mA
Minimum cycle.
Vcc= 5.5V.
RAScycling.
xCAS high (RAS only).
RAS low after xCAS low (CBR)
190
180
170
mA
VCC =5.5 V,
RASlow.
190
180
170
mA
5
5
mA
10L" 4.2 mA
VCC .. 5.5V.
VI-OVto6.5V.
All others = 0 V to VCC
VCC-5.5V.
xCAShlgh
Vo .. OVtoVCC.
tpc = MIN.
xCAScycling
Standby current. outputs
enabled
xCAS =VILo
RAS'=VIH.
5
Data out =enabled
t For conditions shown as MIN/MAX. use the appropriate value specified In the timing requirements.
:I: Measured with outputs open
§ Measured with a maximum of one address change while RAS VIL
11 Measured with a maximum of one address change while iCAS =VIH
ICC7:1:lI
MIN
=
capacitance over recommended ranges of supply voltage and operating free-air temperature,
.
f 1 MHz (see Note 3)
=
PARAMETER
CIIA}
Ci(OE)
CilRC}
CilWl .
MIN
MAX
UNIT
Input capacitance. AO-A 11
Input capacitance. OE
10
10
pF
Input capacitance. xCAS and RAS
10
pF
Input capacitance. W
10
pF
pF
Output capacitance
10
pF
Co
NOTE 3: CapaCitance Is sampled only at Initial design and after any major changes. Samples are tasted at 0 V and 25°C with a 1-MHz signal
applied to the pin under test. All other pins are open.
~TEXAS
INSTRUMENTS
8-130
POST OFFICE BOX 1443. • HOUSTON. TEXAS 772151-1443
SMJ416160, SMJ418160
1048576-WORD BY 16-BIT HIGH-SPEED DRAM
SGMS72OA-APRIL 1995 - REVISED JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
'41x180-70
'41x180-80
PARAMETER
MIN
MAX
MIN
MAX
'41x180-80
MIN
MAX
UNIT
tM
Access time from column address
30
35
40
tCAC
Access time from xCAS low
15
18
20
tCPA
Access time from column precharge
35
40
45
ns
ns
ns
tRAC
Accesa time from RAS low
80
70
80
nl
toEA
Accesa time from OE low
15
18
20
ns
toFF
Output disable time after xCAS high (see Note 5)
20
ns
0
15
0
18
0
15
0
18
0
20
ns
0
toEZ Output disable time after OE high (see Note 5)
NOTES: 4. Valid data il presented at the outputs after all access timas are satisfied but can go from the high-Impedance state to an Invalld-data
atate prior to the specified accass time as the outputs are driven when xCAS and OE are low.
5. toFF and toEZ are specified when the output il no longer driven. The outputs ere disabled by bringing either OE or XCAS high.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'41x180-80
MIN
MAX
'41x160-70
MIN
MAX
110
130
Cycle time, write (see Note 8)
110
Cycle time, read-write (see Note 8)
155
'41x180-80
MIN
MAX
UNIT
tRC
Cycle time, read (see Note 6)
twc
tRWC
tpc
Cycle time, page-mode read or write (see Notes 8 and 7)
40
tpRWC
Cycle time, page-mode read-write (see Note 6)
85
Pulse duretlon, RAS low, page mode (see Note 8)
60 100000
45
96
70 100000
tRAS
Pulse duration, RAS low, nonpage mode (see Nota 8)
60
10000
70
10000
teAS
tAP
Pulse duration, xCAS low (see Note 9)
15
10000
18
10000
Pulse duration, RAS high (precharge)
40
10
50
60
ns
. tRASP
150
nl
130
150
nl
181
205
ns
50
ns
105
ns
80 100000
nl
80
10000
ns
20
10000
ns
twp
Pulse duration, W low
10
10
nl
tASC
Satup time, column addrass before xCAS low
0
0
0
ns
tASR
tos
Satup time, row address before RAS low
0
0
0
nl
Setup time, data (see Note 10)
0
0
0
ns
tRCS
Setup time, W high before xCAS low
0
0
0
nl
lewL
tRWL
Setup time, W low before xCAS high
15
18
20
ns
Setup time, W low before RAS high
15
18
20
ns
twcs
Satup time, W low before xCAS low (early-write operetion only)
0
0
0
ns
tCAH
Hold time, column address after xCAS low
10
15
15
ns
tOH
Hold time, data (see Note 10)
10
15
15
ns
tRAH
Hold time, row address after RAS low
10
10
10
ns
tRCH
Hold time, W high afterxCAS high (see Nota 11)
0
0
0
ns
tRRH
Hold time, W high after RAS high (see Note 11)
0
0
0
15
ns
Hold time, W low after xCAS low (early-write operation only)
10
twCH
NOTES: .6. All cycle timas assume IT 5 ns, referenced to VIH(min) and VIL(max) •
7. To assure tpc min, tASC should be ;0 to teP.
8. In a read-write cycle, tRWO and tRWL must be observed.
9. In a read-write cycle, lewD and teWL must be observed.
10. Referenced to the later of xCAS or iN in write operetions
11. Either tRRH or tRCH must be satisfied for a read cycle.
15
ns
=
~1ExAs
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON. TEXAS n251-1443
8-131
~
W
~a:
D.
t;
~
Q
o
a:
D.
SMJ416160,SMJ418160
1048576-WORD BY 16-BIT HIGH-SPEED DRAM
SGMS720A-APRIL 1995- REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
l:J
C
c:
....n
"m
l:J
S
m
=e
'41xl60-70
'41xl60-60
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
loLCH
Hold time, ieM" low to XCAS high
5
5
5
tRHCP
Hold time, 'RAS high from iCAS precharge
35
40
45
ns
toEH
tROH
lop
Hold time, C5E command
15
10
20
10
ns
Hold time, 'RAS referanced to OE
18
10
Delay time, iCAS high (pracharge)
10
Delay time, column address to W low (read-write operation only)
65
loHR
Delay time, RAS low to xCAS high (CBR refresh only)
10
10
10
70
10
ns
tAWD
10
63
loRP
Delay time, xCAS high to RAS low
5
ns
Delay time, RAS low to xCAS high
80
ns
Delay time, XCAS low to RAS low (CBR refresh only)
Delay time, iCAS low to W low (read-write operation only)
60
5
40
5
70
5
loSH
tCSR
ns
ns
Delay time, OE to data
15
5
50
20
tRAD
Delay time, RAS low to column address (see Note 12)
tRAL
Delay time, column addrass to RAS high
15
30
tcwD
tOED
"o
'41x160-60
tCAL
Delay time, column address to xCAS high
tRCD
Delay time, RAS low to xCAS low (see Note 12)
tRPC
Delay time, RAS high to iCAS low
tRSH
tRWD
Delay time, XCAS low to RAS high
Delay time, 'RAS low to W low (read-write operation only)
15
85
tcPW
Delay time, W low after xCAS precharge (read-write operation only)
80
tREF
Refresh time interval
IT
Transition time (see Note 13)
30
20
0
5
46
18
30
45
1'418180
8
NOTES. 12. The mllXlmum value IS specified only to assure access time.
13. Transition times (rise and fall) should be a minimum of 3 ns and a maximum of 30 ns.
8-132
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
35
20
0
18
52.
98
68
32
~TEXAS
35
35
,'416180
INSTRUMENTS
15
15
40
40
20
ns
ns
ns
ns
ns
40
ns
60
ns
ns
0
20
n8
tiO
ns
n8
75
32
8
ns
ns
32
8
ms
· SMJ418160
SMJ416160,
1048576-WORD BY 16-B11 HIGH-SPEED DRAM
SGMS72OA- APRIL 1885 - REVISED JUNE 1885
PARAMETER MEASUREMENT INFORMATION
IV
1.31 V
Rl_828Q
Output Und.rT.et-....- -..
Output Und.r Tnt
CL-100pF
(n.NoteA)
I
CL-100pF
(8uNot.A)
(8) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
V
A--
VIHIVOHMIN-V
VILIvOLMAX-=A_ _ _ _ _ _ _ _ _ _ _ _
(0) VOLTAGE WAVEFORMS
W
==
NOTES: A. CL includes probe and fixture capacltance.
B. The ac timing parameters are specified with reference to the minimum valid high-level voltage
and the maximum valid low-level voltage for each signal. This corresponds to 2.4 V and 0.8 V
for Inputs; 2.4 V and 0.4 V for outputs with the given load circuit.
~
a:
Figure 1. Load Circuits and Voltage Waveforms
a..
~
:;:)
C
o
a:
a..
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-133
SMJ416160, SMJ418160
1048576-WORD BY 16-BIT HIGH·SPEED DRAM
SGMS72OA- APRIL 1995- REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
RAt
~C
~
iT
-.j
i
I
I I
t
i
II I
"'tJ
:XJ
o
C
c:
I
I
Vi
"'tJ
:XJ
~
~
i
lw(
-- 9X +
~
-
I
. I I
IiIII
teSH
I
I I
I4-tRAD~
I I
!.......I- tRAH I I I
I~ ~i
I I I
I
tASC~ I
I
I
14 I I
t
----""';~
ASR ~!-."
DQO-DQ1S
I It-- tRP --..j
1\~teAS~/
!r-
ft7'V\ :
i;;jtelCH
I
(uaNoteA) ~
I
"{.
.1
1
14
I
I~
I
J~
I I
~SH I I
~ I
I I
II
I I
I I
I I
I
III
I
I I
~ I
teAL
\.
teP--I-I-~~
I
~
+7~~1$:~""'"--__
I
I
~CS ~I ~
~teAH
I
14- teAC -.I
I
(.u Note B)
14------ tAA ~
I
I
I SeeNoteD
~_
---+t------I SeeNoteC
IRRH
I
I
I
~
I 14
I
I.-- tRCH --.:
I
14-
toFF ---:
1
1
~
~~;~g¥o~toEA~
I
I
) ~-----_
I
14 I
~ toEZ
~
Valid Date Out
I
:
.
d&m:~O;!g*:a
To hold the address latched by the first XCAS going low, the parameter tclCH must be met.
tcAC Is measured from xCAS to Its corresponding DQx.
Output can go from the high-Impedance state to an Invalid-date state prior to the specified access time.
xCAS order Is arbitrary.
Figure 2. Read-Cycle Timing
~1ExAs
8-134
I
I
I
(rH~RP
I
I
~ rl4-l4-----+1 tROH
NOTES: A.
B.
C.
D.
I I
II
II
I 1
~
tRAL
i4j4----tRAC
OE
1\"'___
~
tRAS
It=--- tRCD ----.I
I
II
II
I I
I
I
I
I
I
I
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, 1ecAS 77251-1443
SMJ416160, SMJ418160
1048576·WORD BY 16-BIT HIGH·SPEED DRAM
SGMS72OA- APRIL 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
3:
w
Add .....
~
a:
a.
~
iN
::l
C
o
a:
DQO-DQ1S
Valid Data In
.""f\/\,f\/\,'V\J'V\J
Don't Care
a.
'\A/\/\/\/\,/\/'o,/\.
I !4-.r---.L- tDS (see Note B)
1
I
I4-toED~
I
14
toEH ---t!.!
NOTES: A. To hold the address latched by the first XCAS going low, the parameter tcLCH must be met.
B. Referenced to the first xCAS or W, whichever occurs last
C. XCAS order Is arbitrary.
Figure 3. Write-Cycle Timing
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-1.35
SMJ416160, SMJ418160
1048576-WORD BY 16-BIT HIGH-SPEED DRAM
SGMS72OA- APRIL 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
-a
:a
oc
Address
c:
~
-a
:a
~
m
-
DQO-DQ15
:e
NOTES: A To hold the address latched by the first xCAS going low, the parameter tcLCH must be met.
B. XCAS order is arbitrary.
Figure 4. Early-Wrlte-Cycle nmlng
~1EXAS
8-136
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ416160, SMJ418160
1048576·WORD BY 16·B11 HIGH·SPEED DRAM
SGMS72OA- APRIL 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
~
a:
Address
D.
t;
~
C
oa:
008-0015
D.
000-007
NOTES: A. To hold the address latched by the first xCAS going low, the parameter tcLCH must be met.
B. Output can go from the high-Impedance state to an Invalld-data state prior to the specified access time.
C. tcAC Is measurad from xCAS to Its corraspondlng OQx.
O. iCAS order Is arbitrary.
Figure 5. Read-Modlfy-Wrlte-Cycle Timing
~1ExAs
INSTRUMENTS
POST OFFICE SOX 1443 • HOUS'ION, TEXAS 77251-1443
8-137
SMJ416160, SMJ418160
1048576-WORD BY 16-BIT HIGH-SPEED DRAM
SGMS72OA-APRIL 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
IRP~
~~~~-=--:-:-:=========::::::::_IR_A_S_P_-::::::::::::::::':~
I
~IRCD1
I I
II
I I
I ~
I
II
II
-I .
"tJ
oC
I
I
I
(
I
I
iteSH~
I
-,
IteASi4
I
I
~
~I
;
I
I
I
I
j4-tep-tj
I
I
I
I
I~
I4--teAL~
~
--~~
I
I
I
I
I
I
I
I
I
I
I
I
J:_----+I.....----
I
\i
lASR
..~
I
tRSH
tpC
tCAH
~
IRAL'
AddreBB
c:
~
Vi
Don't Care
~~~;tV: I
I
I
I
"tJ
:D
-~
~
I
tCL~H~
(BHNoteA)
~teRpH
tRHCP
i~
I I 'L..J1
llRAH ~ I I
I
I I -H rtt~sc
I
~
:D
Ir'----\414----
~~
II
008-0015
I~
I I
teAC
---1WI
I
I
I
(BeBNotBB)
14 I
tAA
tRRH
~$~~t~
I
I
~
\4-tAA4
~
F
I)
:
------------~ ~~~
I toEA
I
OE
I4--IRCH ~
I
I
XXXXXX)()C
I I
I
I
I
II
~
I
t RCS -*I..-++-~J
~I
I
r I
-I
(BeetePA
Note C)
II
J
I
1ej4--- tRAC ---~"I
I
I
I
I
II:.-.r- toFF
See
__
_NoteD
_ _ _ _ _ _ _ _~
lid
I
I
Out
I --.I
toEZ
See Note 0
DQO-D07
I
~
~~:f?~~a:e:~~toEA~
&
14
I
~
)---------
I
I
~1Ir7\'~:'ft7'~~:'ft"I'*~~'t~~~~~:&m~
NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. !cAe Is measured from iCAS to its corresponding DQx.
Access time Is tePA or tM dependent.
D. Output can go from the high-impedanca state to an invalid-data stste prior to the specified accass time.
E. A write cycle or read-modify-write cycle can be mixed with the read cycles as long es the write- and read-modify-write-tlmlng
specHlcatlons are not violated.
F. xCAS order Is arbitrary.
e.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
~TEXAS
INSTRUMENTS
8-138
POST OFFICE BOX 1443 • HOUSTON, 1CXAS n251-1443
SMJ416160, SMJ418160
1048576·WORD BY 16-BIT HIGH·SPEED DRAM
SGMS720A- APRIL 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~___________________ tRASP ___________________t~R;~
~
I4-jIII- - t R S H
III I
II I
\.
!..
J!
lAsR
I
I
r
I
I
tASC
~--~I
tos~
W
teAS
~ ~I
I
I
I
I
: . - - twp
~
I
§l::e;~~lf
I~
r
~
----r
teAH
tcp
I
I
I
I
I
14
S•• Note B
teSH
~ 141
-.I '-- tRAH I
Addresa
(s•• Not. A)
I
~
14-- teLCH ----.!
I4-lRCD -.(
I
(_.
----I
lRHCP
tpc
twCH
I
I
I
II
-tj
( !
I
j.-- teAL --~~
~------lRAL
I
I
I
.!
~~~~~~~~88~~
f'I
Don't Car.
tCWL
I..
----tlI
~
j.- teRP
\l
I+-
teWL
~
I
Column
~
~ i\'---
I
~
tRWL
I
----..J
Il.
~~~f.:;~
DQ8DQ1S
~ :voUdI'~E=~
DQO-
~
DQ7
~~D
---~~~
~,~--------~~~~~S§;~::~
Valid In
valid In
NOTES: A. To hold the address latched by the first xCAS going low, the parameter tcLCH must be met.
B. Referenced to the first iCASor W, whichever occurs last
C. A read cycle or read-modify-write cycle can be mixed with 'the write cycles as long as the read- and read-modify-write-timing
specifications are not violated.
D. XCAS order Is arbitrary.
Figure 7. Enhanced·Page·Mode Wrlte·Cycle Timing
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSroN. TEXAS 77251-1443
~
~
a::
8-139
t;
:»
Q
oa::
Il.
SMJ416160, SMJ418160
1048576-WORD BY 16·BIT HIGH·SPEED DRAM
SGMS72OA-APRIL 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
r
IRP ~
~I
j+-
~p------------------~~
i't
I 1+ IReD -.I
!!
~
I I
I
I I
I I
I
II
~I
teSH
~I
.
14- IRSH ~
I
/ 1 ~tcAP
tcAsWNc;r=1 i
I
hi
~I
tep
1 '----
,ic----
I
I
II
.~teLeH~ I
d
II X
A"
\L
11*lASe -+I II~
1
II
I
II
~~i~m. _ _ _ _~ ~.
(se. Not. A)
IASR
Add .....
"'U
I
w
.
I -
---..I
j4:-t- IAWD ----.., I
~I
1
1
~
lAA
1
1
~I
I..
I4--lRAe
----+j
11
lAA 1 I"
IDS
I"
1 1
I"
~I IDH
-+1141-
------~.~ ~lld
L..
teWL--1IIINf----~~1I
_
YalldOu
~tOEA~ I
I"
I
--lioI I+- toEZ
OEml
)
~I
1
toEH
IRWL
1
1p:.-..,Q~""~~~~~
~I
~I..--~~I-
I
I
I
I
tePA
(••• Not. B)
Li:
'.lId Out.
~
In )
~I
I..
.1
1 (s•• Not.:)
I.
DQO-DQ15
1I
twp
:IIIRwD----+\ I !~
~ II ~teAeN· ~I
IRes
"'U
-~
J+-
~
-I
:a
~
~I1 i+-IeWD~ I..
...AH ~
:a
oc
c:
o
I"
\}
Yalldln
I
I
~I
toEH
I
»--1-1----I
toED
I
I
~
To hold the address latched by the first xeAS going low, the parameter teLCH must be met.
Access tim. is tePA or tM dependent.
Output can go from the high-Impedance state to an invalid-date state prior to the specified access time.
xCAS order Is arbitrary.
A read or write cycle can be Intermixed with read-modify-write cycles as long as the read- and write-cycle timing specifications are
not violated.
F. tcAc Is measured from XCAS to its corresponding DOx.
NOTES: A.
B.
C.
D.
E.
Figure 8. Enhanced.Page·Mode Read-Modlfy-Wrlte-Cycle Timing
~1ExAs
8-140
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lCXAS 77251-1443
SMJ416160, SMJ418160
1048576-WORD BY 16-BIT HIGH-SPEED DRAM
SGMS72OA- APRIL 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
xCAS
~::~~~~¥'~e:~
tASR
III
II
., ~
See Note A
~
~
tRAH
Address 0@::*gX~e:~ Row )@:?'¥.~:'~:W<,--__
ROW__
Vi
~:?,¥.n;!~~r~:~
~
~
a:
DQO-DQ15 - - - - - - - - - - HI.z - - - - - - - - - - -
a.
~
Figure 9. RAS-Only Refresh-Cycle Timing
::l
Q
oa:
a.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HousmN, TEXAS 77251-1443
8-141
SMJ416160, SMJ418160
1048576-WORD BY 1&;B11 HIGH-SPEED DRAM
SGMS72OA- APRIL 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Figure 10. Hldden-Refresh-Cycle Timing
~1ExAs
8-142
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SMJ416160, SMJ418160
1048576·WORD BY 16·BIT HIGH·SPEED DRAM
SGMS720A- APRIL 1996 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~14--------tRC--------+l·1
I+-- tRP - - - . , ~14-----tRAS -'------+1.1 I
I
I 1
I I~______
N
Jf
---' I
tRPC
I
-.I ~ tcSR......,
\l
~I
t
______________________.JI
!+14- - - t c H R
~~tt
----+t~1
Y
Vi
§@@§@§Q§§§§Q§§@@Q(e~~::¥';:~
Address
~:efi::¥';:~
OE
~:?'fi;:€~~:~
DQO-DQ15
------------HI-2------------
NOTE A: Ally xCAS can be used.
;:
W
~
IX:
a.
Figure 11. Automatlc-xCBR-Refresh-Cycle Timing
~
::l
Q
oIX:
a.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-143
SMJ416160,SMJ418160
1048576-WORD BY 16-BI1 HIGH-SPEED DRAM
SGMS72OA-APRIL 1995 - REVISED JUNE 1995
~TEXAS
8·144
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lEXAS 77261-1443
SMJ44C251B
262144 BY 4-BIT MULTIPORT VIDEO RAM
• Military Operating Temperature Range
- SSOC to 125°C
• Performance Ranges:
ACCESS
TIME
ROW
ADDRESS
(MAX)
la(R)
'440251B-10 100ns
'4402518-12 120 ns
ACCESS ACCESS
TIME
TIME
COLUMN SERIAL
ENABLE DATA
(MAX)
(MAX)
la(C)
25ns
30ns
la(SQ)
30ns
35ns
ACCESS
TIME
SERIAL
ENABLE
(MAX)
la(SE)
20ns
25ns
• Class B High-Reliability Processing
• DRAM: 262144 Words x 4 Bits
SAM: 512 Words x 4 Bits
• Single SOV Power Supply (::1:10% Tolerance)
• Dual Port Accessibility-Simultaneous and
Asynchronous Access From the DRAM and
SAM Ports
• Bldlrectlonal-Data-Transfer Function
Between the DRAM and the Serial-Data
Register
• 4 x 4 Block-Write Feature for Fast Area Fill
Operations; As Many as Four Memory
Address locations Written per Cycle From
an On-Chlp Color Register
• Wrlte-Per-Blt Feature for Selective Write to
Each RAM I/O; Two Wrlte-Per-Blt Modes to
Simplify System Design
• Enhanced Page-Mode Operation for Faster
Access
• CAS-Before-RAS (CBR) and Hidden
Refresh Modes
• All Inputs/Outputs and Clocks Are TTL
Compatible
• Long Refresh Period
Every 8 ms (Max)
• Up to 33-MHz Uninterrupted Serial-Data
Streams
.3-8tate Serlall/OsAliow Easy Multiplexing
of Video-Data Streams
• 512 Selectable Serial-Register Starting
locations
• Texas Instruments EPIC'" Process
• Packaging:
- 28-Pln J-Leaded Ceramic Chip Carrier
Package (HJ Suffix)
- 28-Pln Leadless Ceramic Chip Carrier
Package (HM Suffix)
- 28-Pln Ceramic Sidebrazed DIP
(JD Suffix)
- 28-Pln Zig-Zag In-Une (ZIP), Ceramic
Package (SV Suffix)
• Split Serial-Data Register for Simplified
Real-TIme Register Reload
PIN NOMENCLATURE
AO-AS
CAS
description
DQO-DQ3
Address Inpu1s
Column Enable
DRAM Data In-Out/Wrlte-Mask Bit
Serial Enable
Row Enable
Serial Data Clock
Serial Data In-Out
Transfer Register /Q Output Enable
Write-Mask Select/Write Enable
Special Function Select
Split-Register ActIvity Status
5-VSupply
Ground
Ground (Importsnt: Not connected
to Internal VSs)
SE
The· SMJ44C251 B multiport video RAM is a
RAS
high-speed. dual-ported memory device. It
SC
consists of a dynamic random-access memory
SDQO-SDQ3
(DRAM) organized as 262144 words of 4 bits
fAG
each interfaced to a serial-data register or
W
serial-access memory (SAM) organized as 512
DSF
words of 4 bits each. The SMJ44C251 B supports
QSF
three types of operation: random access to and
vcc
from the DRAM. serial access to and from the
vss
serial register. and bidirectional transfer of data
GND
between any row in the DRAM and the serial
register. Except during transfer operations. the
SMJ44C251 B can be accessed simultaneously
and asynchronously from the DRAM and SAM ports. During a transfer operation. the 512 columns of the DRAM
are connected to the 512 positions in the serial data register. The 512 x 4-bit serial-data register can be loaded
from the memory row (transfer read). or the contents of the 512 x 4-bit serial-data register can be written to the
memory row (transfer write).
EPIC Is a trademark of Texas Instruments Incorporated.
~1ExAs
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Copyright «> 1995, Texas Instruments Incorporated
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SMJ44C251B
262144 BY 4-BIT MULTIPORT VIDEO RAM
SOMS058A- MARCH 1995 - REVISED JUNE 1995
pinouts
HJPACKAGE
(TOP VIEW)
SC
SOQO
SOQ1
TRG
OQO
OQ1
1
2
W
GNO
RAS
9
HMPACKAGE
(TOP VIEW)
Vss
SOQ3
SOQ2
SE
DQ3
OQ2
OSF
CAS
QSF
As
AO
AS
A1
AS
A2
A4
A3
Vee
A7
SC
SOQO
SOQ1
TAG
OQO
OQ1
W
GNO
RAS
SVPACKAGE
(TOP VIEW)
JDPACKAGE
(TOP VIEW)
Vss
SOQ3
SoQ2
SE
OQ3
OQ2
OSF
CAS
QSF
As
AO
AS
A1
AS
A2
A4
A3
Vee
A7
SC
SOQO
SOQ1
TRG
OQO
OQ1
1
SOQ3
SOQ2
~
'Ii.
GNO
RAS
Vss
9
OQ3
OQ2
OSF
CAS
QSF
As
1..0
AS.
A1
AS
A2
A4
A3
Vee
A7
description (continued)
The SMJ44C251 B Is equipped with several features designed to provide higher system-level bandwidth and
to simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates
can be achieved by the device's 4 x 4 block-write mode. The block-write mode allows four bits of data (present
in an on-Chip color-data register) to be written to any combination of four adjacent column-address locations.
As many as 16 bits of data can be written to memory during each CAS cycle time. Also on the DRAM port, a
write mask or a write-per-bitfeature allows masking any combination of the four input/outputs on any write cycle.
The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent write
cycles. The mask register eliminates having to provide mask data on every mask-write cycle.
The SMJ44C251 B offers a split-register transfer read (DRAM to SAM) feature for the serial tester (SAM port).
This feature enables real-time register reload implementation for truly continuous serial data streams without
critical timing requirements. The register is divided into a high half and a low half. While one half is being read
out of the SAM port, the other half can be loaded from the memory array. For applications not requiring real-time
register reload (for example, reloads done during CRT retrace periods), the Single-register mode of operation
is retained to simplify design. The SAM can also be configured in input mode, accepting serial data from an
external device. Once the serial register within the SAM is loaded, its contents can be transferred to the
corresponding column positions in any row in memory In a single memory cycle.
The SAM port is designed for maximum performance. Data can be input to or accessed from the SAM at serial
rates up to 33 MHz. During the split-register mode of operation, internal circuitry detects when the last bit
position is accessed from the active half .of the register and immediately transfers control to the opposite half.
A separate output, QSF, is included to indicate which half of the serial register is active at any given time in the
split-register mode.
All Inputs, outputs, and clock signals on the SMJ44C251 B are compatible with Series 54 TTL devices. All
address lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched
to allow greater system flexibility.
~TEXAS
INSTRUMENTS
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SMJ44C251B
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
description (continued)
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup, row-address hold, and address multiplex is
eliminated, and a memory cycle time reduction of up to 3x can be achieved, compared to minimum RAS cycle
times. The maximum number of columns that can be accessed is determined by the maximum RAS low time
and page-mode cycle time used. The SMJ44C251B allows a ~age (512 cycles) of information to be
accessed in read, write, or read-modify-write mode during a single RAS-Iow period using relatively conservative
page-mode cycle times.
The SMJ44C251 B employs state-of-ths-art Texas Instruments EPIC'" scaled CMOS, double-level
polysilicon/polycide gate technology for very high performance combined with improved reliability. For surface
mount technology, the SMJ44C251 B is offered in a 28-pin J-Ieaded chip carrier package (HJ suffix) or a 28-pln
leadless ceramic chip carrier package (HM suffix). The SMJ44C251 B is offered In a 28-pin 4OO-mil dual-In-line
ceramic sldebrazed package (JO suffix) or a 28-pin ZIP ceramic package (SV suffix) for through-hole Insertion.
The L suffix device is rated for operation from O°C to 70°C. The M suffix device is rated for operation from - 55°C
to 125°C.
The SMJ44C251 B and other multiport video RAMs are supported by a broad line of video/graphic processors
from Texas Instruments, Including the SMJ34010 and the SMJ34020 graphics processors.
functional block diagram
SDQO
SDQ1
SDQ2
SDQ3
~TEXAS
INSTRUMENTS
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8-147
SMJ44C251B
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1996
Function Table
CAS
FALL
RASFALL
FUNCTION
CAS 'i'RG
CBR refresh
Register-to-memory transfer
(transfer write)
L
X
va
DSF
IE
DSF
X
X
X
X
ADDRESS
DQO-DQ3
CASt
TVPEt
CAS
RAS
X
X
X
X
R
Tap
Point
X
X
T
RAS
Vi
H
L
L
X
L
X
Row
Addr
Altemste transfer write
~ndependent of SE)
H
L
L
H
X
X
Row
Addr
Tap
Point
X
X
T
Serial-write-mode enable
(pseudo-transfer write)
H
L
L
L
H
X
Refresh
Addr
Tap
Point
X
X
T
Memory-to-register transfer
(transfer read)
Ii
L
H
L
X
X
Row
Addr
Tap
Point
X
X
T
Split-reglster-transfer read
(must reload tap)
H
L
H
H
X
X
Row
Addr
Tap
Point
X
X
T
L
Row
Addr
Col
Addr
CQ
Mask
valid
Data
R
H
Row
Addr
BlkAddr
DO
Col
A2-AS
Mask
Mask
Col
X
valid
Data
Load and use write mask.
Write data to CRAM
H
Load and use write mask.
Block write to DRAM
H
H
H
L
L
L
L
X
X
Persistent writa-per-bit,
Write data to DRAM
H
H
L
H
X
L
Row
Addr
Persistent writa-per-bit.
Block write to DRAM
H
H
L
H
X
H
Row
Addr
BlkAddr
Normal DRAM read/Write
(nonmasked)
H
H
H
L
X
L
Row
Addr
Col
Addr
BlkAddr
Block write to DRAM
(nonmasked)
H
H
H
L
X
H
Row
Addr
Load write mask
H
H
H
H
X
L
Load color register
H
H
H
H
X
H
X
Refresh
Addr
X
X
Refresh
Addr
X
X
=
t R random access operation; T transfer operation
In persistent write-per-bit function. iii must be high during the refresh cycle.
Coo-D03 are latched on the later of \iii or CAS falling edge.
Col Mask. H: Write to address/column location enabled
CQ Mask =H: Write to
enabled
va
~1ExAs
8-148
X
X
L=Low
*S =
A2-AS
A2-AS
Legend:
H -High
X=Don'tcare
Addr
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POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
Col
Mask
Valid
Data
Col
Mask
DQ
Mask
Color
Data
R
R
R
R
R
R
R
SMJ44C251B
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
operation
Depending on the type of operation chosen, the signals of the SMJ44C251 B perform different functions. Table 1
summarizes the Signal descriptions and the operational modes they control.
Table 1. Detailed Signal Description Versus Operational Mode
PIN
DRAM
TRANSFER
AO-AS
Row. column address
Row. tap address
CAS
Column enable. output enable
Tap-address strobe
001
DRAM data VO, write mask bits
DSF
Block·write enable
Persistent wrlte-per-bit enable
Color-register load enable
RAS
Row enable
Spilt-register enable
Alternate write-transfer enable
Row enable
SE
Serial-In mode enable
SC
Serial enable
Serial clock
Serlal-data VO
SDO
TRG
o output enable
Transfer enable
W
Write enable, write-per-bit select
Transfer-write enable
Split register
ActIve status
OSF
NC/GND
Make no external connection or tie to system VSS.
VCC
5-V supply (typical)
VSS
SAM
Device ground
The SMJ44C251 B has three kinds of operations: random-access operations typical of a DRAM. transfer
operations from memory arrays to the SAM, and serial-access operations through the SAM port. The signals
used to control these operations are described here, followed by discussions of the operations themselves.
address (AO-AB)
For DRAM operation, 18 address bits are required to decode one of the 262144 storage cell locations. Nine
row-address bits are set up on AO-AS and latched onto the chip on the falling edge of RAS. Nine
column-address bits are set up on AO-AS and latched onto the chip on the falling edge of CAS. All addresses
must be stable on or before the falling edges of RAS and CAS.
During the transfer operation, the states of AO-AS are latched on the falling edge of RAS to select one of the
512 rows where the transfer occurs. To select one of 512 tap points (starting positions) for the serial-data input
or output, the appropriate 9-blt column address (AO-A8) must be valid when CAS falls.
row-address strobe (RAS)
RAS is similar to a chip enable because all DRAM cycles and transfer cycles are initiated by the falling edge
of RAS. RAS is a control input that latches the states of row address, W, TRG, SE, CAS, and DSF onto the chip
to invoke DRAM and transfer functions.
column-address strobe (CAS)
CAS is a control input that latches the states of column address and DSF to control DRAM and transfer functions.
When CAS Is brought low during a transfer cycle, it latches the new tap point for the serial-data input or output.
CAS also acts as an output enable for the DRAM outputs 000-003.
~1ExAs
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SMJ44C251B
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SOMS058A- MARCH 1995 - REVISED JUNE 1995
output enable/transfer select (TRG)
'fAG selects either DRAM or transfer operation as RAS falls. For DRAM operation, 'fAG must be held high as
RAS falls. During DRAM operation, TRG functions as an output enable for the DRAM outputs DQO-DQ3. For
transfer operation, TRG must be brought low before RAS falls.
write-mask select, write enable (W)
In DRAM operation, W enables data to be written to the DRAM. W is also used to select the DRAM write-per-bit
mode. Holding W low on the falling edge of RAS invokes the write-per-bit operation. The SMJ44C251 B supports
both the normal write-per-bit mode and the persistent write-per-bit mode.
For transfer operation, W selects either a read-transfer operation (DRAM to SAM) or a write-transfer operation
(SAM to DRAM). During a transfer cycle, if W is high when RAS falls, a read transfer occurs; if W is low, a write
transfer occurs.
special function select (DSF)
DSF is latched on the falling edge of RAS or CAS, similar to an address. DSF determines which of the following
functions are invoked on a particular cycle:
•
•
•
•
•
Persistent write-per-bit
Block write
Split-register transfer read
Mask-register load for the persistent write-per-bit mode
Color-register load for the block-write mode
DRAM data I/O, write-mask data (DQO-DQ3)
DRAM data is written via DQ terminals during a write or read-modify-write cycle. In an early-write cycle, W is
brought low prior to CAS and the data is strobed in bl.CAS with data setup and hold times referenced to this
signal. In a delayed-write or read-modify-write cycle, W is brought low after CAS and the data is strobed in by
W with data setup and hold times referenced to this signal.
The 3-state DQ output buffers provide direct TTL compatibility (no pull up resistors) with a fanout of two Series
54 TTL loads. Data out is the same polarity as data in. The outputs are in the high-impedance (floating) state
as long as CAS and TRG are held high. Data does not appear at the outputs until both CAS and TRG are brought
low. Once the outputs are valid, they remain valid while CAS and TRG are low. CAS or TRG going high retums
the outputs to the high-impedance state. In. a register-transfer operation, the DQ outputs remain in the
high-impedance state for the entire cycle.
The write-per-bit mask Is latched into the device via the random DQ terminals by the falling edge of RAS. This
mask selects which of the four random I/Os are written.
serial data I/O (SDQO-SDQ3)
Serial inputs and serial outputs share common I/O terminals. Serial-input or serial-output mode is determined
by the previous transfer cycle. If the previous transfer cycle was a read transfer, the data register is in
serial-output mode. While in serial-output mode, data in SAM is accessed from the least significant bit to the
most significant bit. The data registers operate modulo 512; so after bit 511 is accessed, the next bits to be
accessed are 00, 01 , 02, etc. If the previous transfer cycle was either a write transfer or a pseudo transfer, the
data register is in serial-input mode and signal data can be input to the register.
serial clock (SC)
Serial data is accessed In or out of the data register on the rising edge of SC. The SMJ44C251 B is designed
to work with a wide range of clock-duty cycles to simplify system design. There is no refresh requirement
because the data registers that comprise the SAM are static. There is also no minimum SC clock operating
frequency.
-!!11ExAs
INSTRUMENTS
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SMJ44C251B
262144 BY 4-BIT MULTIPORT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
serial enable (SE)
During serial-access operations SE is used as an enable/disable for SDa in both the input and output modes.
If SE is held as RAS falls during a write-transfer cycle, a pseudo-transfer write occurs. There is no actual transfer,
but the data register switches from the output mode to the input mode.
no connect/ground (NC/GND)
NC/GND is reserved for the manufacturer's test operation. It is an input and should be tied to system ground
or left floating for proper device operation.
special function output (QSF)
During split-register operation the aSF output indicates which half of the SAM is being accessed. When aSF
is low, the serial-address pOinter is accessing the lower (least significant) 256 bits of SAM. When aSF Is high,
the serial-address pointer is accessing the higher (most significant) 256 bits of SAM. aSF changes state upon
crossing the boundary between the two SAM halves in the split-register mode.
DUring normal transfer operations QSF changes state upon completing a transfer cycle. This state is determined
by the tap point being loaded during the transfer cycle.
power up
To achieve proper device operation, an initial pause of 200 J1S is required after power-up, followed by a minimum
of eight RAS cycles or eight CBR cycles, a memory-to-register transfer cycle, and two SC cycles.
-!/}TEXAS
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8-151
SMJ44C251B
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS058A- MARCH 11l9S- REVISED JUNE 11l9S
random-access operation
The random-access operation functions are summarized in Table 2 and described in the following sections.
Table 2. Random-Access-Operation Functions
CAS
RASFALL
FALL
DQO-DQ3
ADDRESS
FUNcnON
CBR refresh
Load and use write mask,
Write data to DRAM
AD
CAS*
W
CAS
'fRG
wt
DSF
SE
DSF
L
X
X
X
X
X
X
X
X
X
Col
Addr
DQ
Mask
Valid
Data
oa
RAS
CAS
H
H
L
L
X
L
Row
Addr
Load and use write mask,
Block write to DRAM
H
H
L
L
X
H
Row
Addr
BlkAddr
A2-AS
Mask
Col
Mask
Persistent write-par-bit,
Write data to DRAM
H
H
L
H
X
L
Row
Addr
Col
Addr
X
Valid
Data
Persistent write-par-bit,
Block write to DRAM
H
H
L
H
X
H
Row
Addr
BlkAddr
X
Col
Mask
Normal DRAM read/write
(nonmasked)
H
H
H
L
X
L
Row
Addr
Col
Addr
X
Valid
Data
Block write to DRAM
(nonmasked)
H
H
H
L
X
H
Row
Addr
BlkAddr
A2.-AS
X
Col
Mask
Load write mask
H
H
H
H
X
L
Refresh
Addr
X
X
DQ
Mask
Load color register
H
H
H
H
X
H
Refresh
Addr
X
X
Color
Data
A2.-AS
Legend:
H=High
L=Low
X- Don't care
tin parsistent write-par-bit function, Vii must be high during the refresh cycle.
DQO-DQ3 are latched on the later of Vii or CAS failing edge.
Col Mask = H: Write to address/column location enabled
DQ Mask =H: Write to VO enabled
*
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. This mode eliminates the time required for row address setup-and-hold and
address multiplex. The maximum RAS low time and the CAS page cycle time used determine the number of
columns that can be accessed.
Unlike conventional page-mode operation, the enhanced page mode allows the SMJ44C251 B to operate at a
higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CAS
transitions low. A valid column address can be presented immediately after row-address hold time has been
satisfied, usually well in advance of the falling edge of CAS. In this case, data can be obtained after taCC) max
(access time from CAS low), if taCCA) max (access time from column address) has been satisfied.
refresh
There are three types of refresh available on the SMJ44C251 B: RAS-only refresh, CBR refresh, and hidden
refresh.
~TEXAS
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SMJ44C251B
262144 BY 4-BIT MULTIPORT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
RAS-only refresh
A refresh operation must be performed to each row at least once every 8 ms to retain data. Unless CAS is
applied, the output buffers are in the high-impedance state, so the RAS-only refresh sequence avoids any
output during refresh. Externally generated addresses must be supplied during RAS-only refresh. Strobing each
of the 512 row addresses with RAS causes all bits in each row to be refreshed. CAS can remain high Onactive)
for this refresh sequence to conserve power.
CAS-before-RAS (CBR) refresh
CBR refresh is accomplished by bringing CAS low earlier than RAS. The external row address is ignored and
the refresh row address is generated internally when using CBR refresh. Other cycles can be performed In
between CBR cycles without disturbing the internal address generation.
hidden refresh
A hidden refresh is accomplished by holding CAS low in the DRAM-read cycle and cycling RAS. The output data
of the DRAM-read cycle remains valid while the refresh is being carried out. Uke the CBR refresh, the refreshed
row addresses are generated internally during the hidden refresh.
write-pst-bit
The write-per-bit feature allows masking of any combination of the four DQs on any write cycle (see Figure 1).
The write-per-bit operation is invoked only when W is held low on the falling edge of RAS. If W is held high on
the falling edge of RAS, write-per-bit is not enabled and the write operation is performed to all four DQs. The
SMJ44C251 B offers two write-par-bit modes: the nonpersistent write-per-bit mode and the persistent
write-per-bit mode.
,nonpersistent wrlte-per-blt
When DSF is low on the falling edge of RAS, the write mask is reloaded. A 4-bit code (the write-par-bit mask)
is input to the device via the random DQ terminals and latched on the falling edge of RAS. The write-per-bit mask
selects which of the four random I/Os are written and which are not. After RAS has latched the on~chip
write-per-bit mask, input data is driven onto the DQ terminals and is latched on the later falling edge of CAS or
W. When a data low is strobed into a particular I/O on the falling edge of RAS, data is not written to that I/O. When
a data high is strobed into a particular I/O on the falling edge of RAS, data is written to that I/O.
persistent wrlte-per-blt
When DSF is high on the falling edge of RAS, the write-par-bit mask is not reloaded: it retains the value stored
during the last write-per-bit mask reload. This mode of operation is known as persistent write-per-bit because
the write-per-bit mask is persistent over an arbitrary number of write cycles. The write-per-bit mask reload can
be done during the nonpersistent write-per-bit cycle or by the mask-register-Ioad cycle.
~1ExAs
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8·153
SMJ44C251B
262144 BY4·BIT MULTIPORTVIDEO RAM
SGMS058A- MARcH 1895 - REVISED JUNE 1996
I
I
Nonperslatant Wrlta-P8r-B1t
fiASn
I
I
I
CAS I
Perslatent Wrlte-Per-Blt
Write-MaakoReglster Load
I
I
\
\
n
I
I
r1
\
AO-AB
DQO-
DQ3
DaMask
DO Maak
= H:
= L:
Write Data
DaMask
Write Data
Write to I/O enabled
Write to I/O dlaabled
Figure 1. Example of Wrlte-Per-Blt Operations
blockwrlttl
The block-write mode allows data (present in an on-chip color register) to be written into four consecutive
column-address locations. The 4-bit color register is loaded by the color-register-load cycle. Both write-par-bit
modes can be applied in the block-write cycle. The block-write mode also offers the 4 )( 4 column-mask
capability.
load color register
The 10ad-color-registe~le is 'b"Srmed using normal DRAM write-cycle timing except that DSF Is held high
on the falling edges of RAS and A . A 4-bit code is Input to the color register via the random I/O terminals and
latched on the later of the falling edge of CAS or W. After the color register is loaded, it retains data until power
is lost or until another load-color-register cycle is executed.
block write cycle
After the color register is loaded, the block-write cycle can begin as a normal DRAM write cycle with DSF held
high on the falling edge of CAS (see Agures 2, 3, and 4). When the blOCk-write cycle is invoked, each data bit
in the 4-bit color register is written to selected bits of the four adjacent columns of the corresponding random
I/O.
During block-write cycles, only the seven most significant column addresses (A2-Aa) are latched on the falling
edge of CAS. The two least significant addresses (AO-A!l are replaced by four DO bits (DOO-o03), which
are also latched on the later of the falling edge of CAS or W. These four bits are used as a column mask, and
they indicate which of the four column-address locations addressed by A2-Aa are written with the contents of
the color register during the block-write cycle. DOO enables a write to column-address A1 0 (low), AO 0 (low);
D01 enables a write to column-address A1 = 0 (low), AO = 1 (high); D02 enables a write to column-address
A1 =1 (high), AO =0 (low); D03 enables a write to column-address A1 =1 (high), AO =1 (high). A high logic
level enables a write, and a low logic level disables the write. A maximum of 16 bits (4 )( 4) can be written to
memory during each CAS cycle in the block-write mode.
=
~1ExAs
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INSTRUMENTS
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=
SMJ44C251B
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
I
I
Loed-Colo ....R.glst.r Cycl. I
I
I
I
RAS~
I
CASI
Block·Wrlt. C~CI.t
(load and use D mask)
Block·Wrlt. Cycl.t
(no DQ mask)
I
I
\
II
'---.J I
\
I
\
\
I
I
I
Block·Wrlte CyCI.t
(us. Prevlousl~
loaded DQ mas
\
I
\
11
Ii
AO-AS
~
DSF""""P'--W''""""'''''''""-~~
DQO-DQ3
1I$iI" 'U'.
I
I11#III ~
I~~~~~~-.~~~~
t iN must be low during the block-write cycle.
NOTE: OQO-OQ3 are latched on the later of iN or CAS failing edge except In block 6 (see legend).
Legend:
1. Refresh address
2. Row address
3. Block address (A2 -AS)
4. Color-register data
5. Column-mask data
6. DQ-mask data. OQO-OQ3 are latched on the falling edge of RAS.
4'::UnUuc:cccc:c:.=
don't care
Figure 2. Example Block·Write Diagram Operations
N
N +1
N+2
N+3
Block·Wrlte
Enable
L.:=J<4--DQ3
Figure 3. Block-Write Circuit Block Diagram
-!!I1EXAS
INSTRUMENTS
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8-155
SMJ44C251B
262144 BY4-BIT MULTIPORTVIDEO RAM
SGMS058A-MARCH 1995 - REVISED JUNE 1995
COLOR
REGISTER
DATA
COLUMN
DQMASK
MASK
DQO
1
0
001
1
1
DQ2
0
1
1
D03
1
1
1
0
0
Block Write
=>
COLUMN 1
COLUMN 2
COLUMN 3
COLUMN 4
0
0
Masked
0
Masked
1
1
DQO
Masked
D01
Masked
002
Masked
0
0
Masked
003
Masked
1
0
Figure 4. Example of Block Write Operation With DQ Mask and Address Mask
transfer operation
Transfer operations between the memory arr~ (DRAM) and the data registers (SAM) are invoked by bringing
TRG low before RAS falls. The states of W, SE, and DSF, which are also latched on the falling edge of RAS,
determine which transfer operatjon is invoked. Figure 5 shows an overview of data flow between the random
and the serial interfaces.
Col
o
Random-Acc_ Port
Col
Col
Col
255
258
511
r----+---....,
o
Row
4
Memory Array
282144 BIta
Row
511 __
~
__
~
__
~~
258
TRO
AI
DQO-DQ3
Transfer·
DSF
Vi
Con~1
~--------~~
logic
SE
SC
AO-AI
AI--------~--~--------~~~
SDQO-SDQ3 -.""+...
Figure 5. Block Diagram Showing One Random and One Serlal·VO Interface
~TEXAS
INSTRUMENTS
8-156
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ44C251B
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
As shown in Table 3, the SMJ44C251 B supports five basic modes of transfer operation:
•
•
•
•
•
Register~to-memory transfer (normal write transfer, SAM to DRAM)
Alternate-write transfer (independent of the state of SE)
Memory-to-register transfer (pseudo-transfer write). Switches serial port from serial-out mode to serial-in
mode. No actual data transfer takes place between the DRAM and the SAM.
Memory-to-register transfer (normal-read transfer, transfer entire contents of DRAM row to SAM)
Split-register-read transfer (divides the SAM into a low and a high half. Only one half is transferred to the
SAM while the other half is read from the serial I/O port.)
Table 3. Transfer-Operation Functions
CAS
FALL
RASFALL
FUNCTION
CAS
TRG
W
DSF
SE
DSF
ADDRESS
DQO-DQ3
CAS
RAS
CAS
RAS
Row
X
X
W
Register-to-memory transfer
(normel write transfer)
H
L
L
X
L
X
Addr
Tap
Point
Altemata-write transfer
Ondependent of SE)
H
L
L
H
X
X
Row
Addr
Tap
Point
X
X
Serial-write-mode enable
(pseudo-transfer write)
H
L
L
L
H
X
Refresh
Addr
Tap
Point
X
X
Memory-to-register transfer
(normal read transfer)
H
L
H
L
X
X
Row
Addr
Tap
Point
X
X
Split-register-read transfer
(must reload tap)
H
L
H
H
X
X
Row
Addr
Tap
Point
X
X
Legend:
H=Hlgh
L-Low
X.Don'tcare
write transfer
All Vlrite-transfer cycles (except the pseudo write transfer) transfer the entire content of SAM to the selected row
In the DRAM. To invoke a write-transfer cycle, W must be low when AAS falls. There are three possible
write-transfer operations: normal-write transfer, alternate-write transfer, and pseudo-write transfer.
All write-transfer cycles switch the serial port to the serial~in mode.
normal-write transfer (SAM-to-DRAM transfer)
A normal-write transfer cycle loads the contents of the serial-data register to a selected row in the memory array.
TAG, W, and SE are brought low and latched at the falling edge of RAS. Nine row-address bits (AO-AS) are
also latched at the falling edge of RAS to select one of the 512 rows available as the destination of the data
transfer. The nine column-address bits (AO-AS) are latched at the falling edge of CAS to select one of the 512
tap points in SAM that are available for the next serial input.
During a write-transfer operation before RAS falls, the serial-input operation must be suspeSded after a
minimum delay of lcI(SCRL) but can be resumed after a minimum delay of td(RHSC) after RA goes high
(see Figure 6).
~TEXAS
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SMJ44C251B
262144 BY 4-BIT MULTIPORTVIDEO RAM
SGMS068A- MARCH 1995 ~ REVISED JUNE 1995
normal-write transfer (SAM-to-DRAM transfer) (continued)
~
A
I ~---------------------------. I
\~----------/!~i------
!
AO-ASm§0<",,_.,.:"_O_w__>@§X
i
Tap Point
~
w~1
~
SE~I
_
l~
1414--+l~1f--- lcI(SCRL)
I
SC
lcI(RHSC)
~I!'"'------\~~~~~\\,,\~~~@~~'!""'I"""I\\"\~\\,,\r"TT~~'T""{""O~~~~~~
-.I
14-
~
Figure 6. Normal-Wrlte-Transfer-Cycle Timing
alternate-write tranafer (refer to Figure 30)
When DSF is brought high and latched at the falling edge of RAS in the normal-write-transfer cycle, the
aHemate-write transfer occurs.
pseudo-write transfer (write-mode control) (refer to Figure 28)
To invoke the pseudo-write transfer (write-mode control cycle), SE is brought high and latched at the falling edge
of RAS. The pseudo-write transfer does not actually invoke any data transfer but switches the mode of the serial
port from the serial-out (read) mode to the serial-in (write) mode.
Before serial data can be clocked into the serial port via the SDa terminals and the SC input, the SDa terminals
must be switched into input mode. Because the transfer does not occur during the pseudo-transfer write, the
row address (AO-AS) is in the don't care state and the column address (AO-AS), which is latched on the falling
edge of CAS, selects one of the 512 tap points in the SAM that are available for the next serial input.
read fransfer (DRAM-fo-SAM fransfer) (refer fo Figure 7)
During a read-transfer cycle, data from the selected row in DRAM is transferred to SAM. There are two
read-transfer operations: normal-read transfer and split-register-read transfer. .
normal-read transfer (refer to Figure 7')
The normal-read-transfer operation loads data from a selected row in DRAM into SAM. TRG is brought low and
latched at the falling edge of RAS. Nine row-address bits (AO-AS) are also latched at the falling edge of RAS
to select one of the 512 rows available for transfer. The nine column-address bits (AO-AS) are latched at the
. falling edge of CAS to select one of the SAM's 512 available tap points where the serial data is read out.
A normal-read transfer can be performed in three ways: early-load read transfer, real-time or midline-load read
transfer, and late-load read transfer. Each of these offers the flexibility of controlling the TAG trailing edge in
the read-transfer cycle (see Figure 7) .
. ~1ExAs
INSTRUMENTS
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SMJ44C251B
262144 BY 4-BIT MULTIPORT VIDEO RAM
SGMS05BA- MARCH 1995 - REVISED JUNE 1995
normal·read transfer (continued)
,
Early-Load Read Tranafer
RAS~
CAS',
\
'Real·nme-Reload Read Transfer'
Ii\
I',
~
\
I ,'
,---I
Late·Load Read Tranater
~,I
AO-AS
I
TRGi\..J
I
sc I
I
I\
I
I
I
I
I \
I
I
I
I
I
I
I
I
I
Figure 7. Normal·Read·Transfer Timings
spllt·reglster·read transfer
In split·register·read·transfer operation, the serial·data register is split into halves. The low half contains bits
0-255, and the high half contains 256-511. While one half is being read out of the SAM port, the other half can
be loaded from the memory array.
To invoke a split·register read-transfer cycle, DSF is brought high, TRG is brought low, and both are latched at
the falling edge of RAS. Nine row-address bits (AO-AS) are also latched at the falling edge of RAS to select
one of the 512 rows available for the transfer. The nine column-address bits (AO-AS) are latched at the falling
edge of CAS, where address bits AO -A7 select one of the 255 tap points in the specified half of SAM and
address bit AS selects which half Is to be transferred. If AS is a logic low, the low half is transferred. If AS Is a
logic high, the high half is transferred. SAM locations 255 and 511 cannot be used as tap points.
A normal-read transfer must precede the split-register-read transfer to ensure proper operation. After the
normal-read-transfer cycle, the first split-register read transfer can follow immediately without any minimum SC
requirement. However, there is a minimum requirement of a rising edge of SC between split-register
read-transfer cycles.
aSF indicates which half of the SAM is being accessed during serial-access operation. When aSF is low, the
serial-address pointer is accessing the lower (least significant) 256 bits of the SAM. When aSF is high, the
pointer is accessing the higher (most Significant) 256 bits of the SAM. aSF changes state upon completing a
normal-read-transfer cycle. The tap point loaded during the current transfer cycle determines the state of aSF.
In split-register read-transfer mode, aSF changes state when a boundary between the two register halves is
reached (see Figure 12 and Figure 13).
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8·159
SMJ44C251B
262144.BY 4·BIT MULTIPORTVIDEO RAM
SGMSOSSA- MARCH 1995 - REVISED JUNE 1995
spllt-reglster-read transfer (continued)
Read Transfer
With Tap Point N
I
\
Spllt-Regl8t8r
Read Transfer
\
I
' ___I
I
\
'~__-+~A
'~____~I
1
1
~----------
I
OSF
1
__________~---+I------------------------~
I..
SC
~I
e:::
QSF
id(CLQSF)
id(GHQSF)
Point N
-X""------------
Figure 8. Example of a Split-Register Read-Transfer Cycle After a Normal Read-Transfer Cycle
Spllt-Reglster
Read Transfer
WIth Tap Point N
\
RAt
CAS
'fRG
~
OSF
--..r\
,
Split-Register
Read Transfer
"A
1
I
id(RHMS)
I
I
I
I
I
I
I..
~
1
1
1
1
\1
\
I
I
h
~I
I
I
id(MSRL)
SC
14---"'~I- ta(SCQSF)
QSF
-----------------X~~---------
Figure 9. A Split-Register Read-Transfer Cycle After a Split-Register Read-Transfer Cycle
8·160
-!111ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lEXAS n2S1-1443
SMJ44C251B
262144 BY 4-BIT MULTIPORT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
serial-access operation
The serial-read and serial-write operations can be performed through the SAM port simultaneously and
asynchronously with DRAM operations except during transfer operations. The preceding transfer operation
determines the input or output state of the SAM port. If the preceding transfer operation is a read-transfer
operation, the SAM port is in the output mode. If the preceding transfer operation is a write- or
pseudo-write-transfer operation, the SAM port is in the input mode.
Serial data can be read out of or written into SAM by clocking SC starting at the tap point loaded by the preceding
transfer cycle, proceeding sequentially to the most significant bit (bit 511), then wrapping around to the least
significant bit (bit 0) (see Figure 10).
~
0
1 1 1 2 1 ..... 1Tap 1-. ... 1510 1511 I
I
Figure 10. Serial Pointer Direction for Serial Read/Write
For split-register read-transfer operation, serial data can be read out from the active half of SAM by clocking
SC starting at the tap point loaded by the preceding split-register-transfer cycle, then proceeding sequentially
to the most Significant bit ofthe half, bit 255 or bit 511. Ifthere is a split-register-read transfer to the inactive half
during this period, the serial pointer points next to the tap-point location loaded by that split register (see
Figure 15, Case I). If there is no split-register read transfer to the inactive half during this period, the serial pOinter
points next to bit 256 or bit 0, respectively (see Figure 15, Case II).
Figure 11. Serial Pointer for Split-Register Read
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-161
SMJ44C251B
262144 BY 4·BI1 MULTIPORTVIDEORAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
absolute maximum ratings over operating free-alr temperature range (unless otherwise noted)t
Supply voltage rangej Vee (see Note 1) ............................................... -1 V to 7 V
Voltage range on any pin (see Note 1) .•............................................... -1 V to 7 V
Short-circuit output current •....•••.•..••.•..•..•..••..•..•..........•.•..•.....•....•....• 50 mA
Power dissipation ..•.....•.•..•...••.••••.••.•••..•..••••..•.......•................•.••••.. 1 W
Operating free-air temperature range, TA: L suffix ...................................... O°C to 70°C
M suffix ................................. - 55°C to 125°C
Storage temperature range, Tstg ...•..........................•....••••.•..••.•••. - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are atress ratings only, and
functional operstlon of the device at these or any other conditions beyond those Indlceted under "recommended operating conditions" Is not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
4.5
NOM
MAX
5
0
5.5
UNIT
Vee
Supply voltage
VSS
Supply voltage
VIH
High-level inputvoltage
2.9
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.6
V
0
-55
70
·c
TA
Operstlng free-alr temperature
TC
Operating esse temperature
L SuffIX
M suffix
L SuffIX
V
V
125
70
·C
M suffix
125
NOTE 2: The algebraic convention, where the more negative (less positive) limit Is deSignated as minimum, Is used for logic-voltage levels only.
~TEXAS
6-162
INSTRUMENTS
POST OFFICE BOX 1445 • HOUSTON. TEXAS 77251-1445
SMJ44C251B
262144 BY 4·BIT MULTIPORTVIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1996
electrIcal characterIstIcs over recommended ranges of supply voltage and operatIng free-alr
temperature (unless otherwIse noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
10H .. -5mA
VOL
Low-level output voltage (see Note)
IOL=4.2mA
II
10
MIN
MAX
2.4
UNIT
V
0.4
V
Input leakage current
VI" OVt05.8 V.
VCC=5V,
All others open
:1:10
IIA
Output leakage current (see Note 4)
VCC- 5.5V,
:1:10
IIA
PARAMETER (SEE NOTE S)
VO·OVtoVCC
'44C251B-10
'44C251B-12
TEST CONDITIONSt
SAM
PORT
Standby
100
90
Active
110
100
ICCl
Operating current
telrd) and teCWl .. MIN
ICC1A
Operating current
ICC2
Standby current
teISC) =MIN
All clocks. VCC
ICC2A
Standby current
teISC) =MIN
ICC3
RAS-only refresh current
telrt!) and 1c:!Wt = MIN
ICC3A
RAS-only refresh current
ICC4
Page-mode current
teISC) "MIN
te(P) =MIN
Active
ICC4A
Page-mode current
ICes
CAS-before-RAS current'
teISC) =MIN
te(rd) and teCWl = MIN
ICCSA
CAS-before-RAS current
teISC) =MIN
MIN
MAX
MIN
MAX
Standby
15
15
Active
35
Standby
100
Active
110
35
90
100
Standby
65
60
Active
70
65
Standby
90
60
110
100
UNIT
mA
Data-transfer current
Standby
100
90
te(rd) and IcCWl = MIN
Data-transfer current
110
100
Active
ICC6A
teISC) =MIN
t For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
NOTES: 3. The SMJ44C251 B may exhibit simultaneous switching noise as described In the Texas Instruments Advanced CMOS LDg/c
Designer's Handbook. This phenomenon Is exhibited on the DO terminals when the soa terminals are switched and on the SDO
terminals when the DOterminalsareswitched. This may cause VOL and VOH to exceed the date-book limit for a short period of time,
depending upon output loading and temperature. Care should be taken to provide proper termination, decoupllng, and layout of the
devica to minimize simultaneous switching effects.
4. SE is disabled for SDa output leakage tests.
5. ICC (standby) denotes that the SAM port is inactive (standby) and the DRAM port Is active (except for ICCZ>.
ICCA (active) denotes that the SAM port Is active and the DRAM port is active (except for ICCZ>.
ICC is measured with no load on Da or soa.
ICes
~TEXAS
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SGMS058A- MARCH 1995 - REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-alr temperature,
f = 1 MHz (see Note 6)
MIN
PARAMETER
CiCA)
Input capacitance, AO-AB
CURCI
Input capacitance, CAS and AAS
MAX
7
7
UNIT
pF
pF
pF
9
Output capacitance, QSF
pF
9
Co(QSF)
..
NOTE 6: capacitance is sampled only at initial design and after any major change. Samplee are tested at 0 V and 25"0 with a 1-MHz signal
applied to the terminal under test. All other terminals are open.
ColO)
Output capecitance, SDOs and DOs
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 7)
TEST
CONDITIONS t
PARAMETER
ALTo
'44C251B-10
SYMBOL
MIN
MAX
taCC}
Access time from CAS
fd(RLCL) • MAX
ta(CA)
Access time from column address
fdLRLCL} = MAX
teAC
tM
ta(CP)
tarR}
Accass time from CAS high
Accass time from RAS
fd(RLCL) = MAX
fd(RLCL) = MAX
tePA
tRAC
ta(G)
Accass time of DOo-DQ3 from TRG low
toEA
tarSQ}
Accass time of SDQO-SDQ3 from SC high
CL=30pF
tarSE)
Access time of SDQO-SDQ3 from SE low
CL=30pF
tsCA
tSEA
fdis(CH)
Disable time, random output from CAS high
(see Note 6)
CL=100pF
toFF
0
20
fdis(G)
Disable time, random output from 'i'RG high
(aee Note 8)
CL= 100pF
toez
0
fdls(SE)
Disable time, serial output from ~ high
(see Note 8) .
CL=30pF
tsez
0
t For conditions shown ee MINIMAX, use the appropriate value specified In the timing requirements.
NOTES: 7. Switching tlmee assume CL .. 100 pF unlees otherwise noted (see Rgure 12).
8. fdis(CH), fdls(G), and fdls(SE) are apeclfied when the output Is no longer driven.
~TEXAS'
INSTRUMENTS
8-164
POST OFFICE SOX 1443 • HOUSTON, TEXAS 77251-1443
'44C251B-12
MIN
MAX
UNIT
25
30
na
50
60
55
65
ns
ns
100
120
na
25
30
na
30
35
na
20
25
na
0
20
na
20
0
20
ns
20
0
20
ns
SMJ44C251B
262144 BY 4-BIT MULTIPORT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 11195
timing requirements over recommended ranges of supply voltage and operating free-air
temperaturet
ALT.
SYMBOL
'44C251B·10
'44C251B·12
MIN
UNIT
telrdl
te(W)
Cycle time, read (see Nota 9)
lAc
220
na
Cycle time, write (see Note 9)
twc
190
220
ns
telrdWI
teIP)
Cycle time, read-modify-write (see Note 9)
lAMW
250
290
ns
Cycle time, page-mode re811 or write (see Note 9)
60
70
na
tqrdWPl
Cycle time, page-mode read-modify-write (see Note 9)
!PC
tpRMW
105
125
ns
te(TRO)
Cycle time, read transfer (aee Note 9)
tRC
190
220
na
te(TW)
Cycle time, write transfer (see Note 9)
twc
190
220
na
te(SC)
Cycle time, aerial clock (see Notes 9 and 10)
tscc
30
35
ns
tw(CHl
Pulse duration, CAS high
tePN
20
tw(CL)
Pulse duration, CAS low (see Note 11)
Pulse duration, AA§ high
25
80
75000
tw(RH)
teAS
lAp
tw(RLl
Pulse duration, RAS low (see Note 12)
!RAs
100
75000
tw(WL)
Pulse duration, W low
twP
25
tw(TRG)
Pulse duration, fRG low
Pulse duration, SC high
tsc
\w(SCl-)
tw(SELl
Pulse duration, SC low
tscp
10
25
30
12
12
Pulse duration, SE low
tsE
35
40
tw(SEH)
Pulse duration, SE high
40
na
Pulse duration, TRG high
tsEP
trp
35
tw(GHl
30
30
ns
tw(SCHl
MAX
M~
MIN
190
ns
30
30
75000
25
10
120
ns
ns
90
75000
ns
ns
ns
ns
ns
ns
tw(RL)P
Pulse duration, RAS low (page mode)
lsu(CAl
Setup time, column address
lAsc
0
0
ns
lsu(SFC)
Setup time, OSF before CAS low
0
0
ns
lsu(RA)
Setup time, row address
!Fsc
tASR
0
0
ns
lsulWMR}
lsu(OQRl
Setup time, W before RAS low
0
0
ns
Setup time, DO before RAS low
twSR
tMS
0
0
na
lsu(TRG)
Setup time, TRG before RAS low
trHS
0
0
na
lsu(SE)
Setup time, SE before RAS low (see Note 13)
tESR
0
0
ns
lsu(SESCl
Setup time, serial write disable
tsWIS
10
15
ns
lsu(SFRl
Setup time, DSF before RAS low
tFSR
0
0
na
lsI!IDCL)
lsu(OWLl
Setup time, data before CAS low
tosc
0
0
ns
Setup time, data before W low
tosw
0
0
na
100
75000
120
75000
ns
Setup time, read ,command
ns
0
0
lAcs
Setup time, early write command before CAS low
0
0
na
tsu(WCL)
twcs
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 9. All cycle times esaume tt • 5 ns.
10. When the odd tap Is used (tap address can be 0-511, and odd taps are 1,3,5, etc.), the cycle time for SC In the first serial data
out cycle needs to be 70 ns minimum.
11. In a read-modify-write cycllt,Id(CLWL) and lsu(WCH) must be observed. Oepandlng on the user's transition times, this may require
additional CAS low time ttw(CL)I.
12. In a read-modify-write cycle, Id(RLWL) and lsu(WRH) must be observed. Depending on the user's transition times, this may require
additional AA§ low time ttw(RL)l.
13. Reglster-ta-memory (write) transfer cycles only
lsu(rdl
-!111ExAs
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77251-1443
8-165
SMJ44C251B
262144 BY 4-81T MULTIPORT VIDEO RAM
SGMS068A- MARCH 1985 - REVISED JUNE 1985
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (contlnued)t
ALl.
SYMBOL
tsu(WCH)
Setup time, write before 'OAS high
tcwL
tsu(WRH)
Setup time, write before RAS high with TRG .. W .. low
tRWL
tsu{SOS)
Setup time, SOO before SC high
taos
Ih(CLCA)
Hold time, column address after CAS low
'44C251B·1O
MIN
MAX
'44C251B·12
MIN
MAX
UNIT
25
25
30
nl
30
nl
0
nl
leAH
0
20
20
nl
20
15
nl
15
15
15
15
nl
It!LSFCl
Hold time, OSF after 'OAS low
-1h(RA)
Hold time, row address after RAS low
leFH
tRAH
20
15
Ih(TRG)
Ih{SE)
Hold time, TRG after RAS low
ITLH
Hold time, SE after RAS .Iow with TRG • W • low (see Note 13)
tREH
Ih(RWM)
Hold time, write mask, transfer enable after RAS low
Ih{ROO)
th(SFR)
Hold time, DO after RAS low (write-mask operation)
IRWH
tMH
15
15
15
Hold time, OSF after RAS low
tRFH
15
15
15
nl
th(RLCA)
th{CLO)
Hold time, column address after RAS low (see Note 14)
tAR
45
45
nl
Hold time, data after 'OAS low
tOH
20
25
nl
Ih(RLO)
Hold time, data after RAS low (see Note 14)
tOHR
45
50
nl
Ih(WLO)
Hold time, data after W low
tOH
25
nl
It!LCH~
th{RHrd)
Hold time, read after CAS high (see Note 15)
Hold time, read after RAS high (see Note 15)
IRCH
tRRH
20
0
10
th(CLW)
Hold time, write after CAS low
twCH
th{RLWl
Hold time, write after RAS low (see Note 14)
Ih(WLG)
Hold time, TRG after W low (see Note 16)
Ih{SOS)
Hold time, SDO after SC high
Ih(SHSO)
nl
nl
ns
ns
0
nl·
nl
30
10
35
twCR
50
55
nl
toEH
25
5
30
nl
taOH
5
nl
Hold time, SOO after SC high
taOH
5
5
nl
th(RSF)
Hold time, OSF after RAS low
IFHR
45
45
nl
20
ns
120
nl
ns
th(SCSE)
Hold time, serial-write disable
taWIH
20
Id(RLCH)
Delay time, RAS low to CAS high
leSH
100
Id(CHRL)
Delay time, 'OAS high to RAS low
0
nl
Delay time, CAS low to RAS high
leRP
tRSH
0
Id(CLRH)
25
30
nl
Id(CLWL)
Delay time, CAS low to W low (see Notes 17 and )
lewD
55
85
\q(RLCl.)
Delay time, RAS low to CAS low (see Note 19)
IRco
Id{CARHI
Delay time, column address to RAS high
Delay time, RAS low to W low (lee Note 17)
25
50
130
75
IRAL
tRWO
fcI(RLWL)
Delay time, column address to W low (see Note 17)
65
Id{CAWL)
tAWO
t 'TIming measurements are referenced to VIL max and VIH min.
NOTES: 13. Reglster-ta-memory (write) transfer cycles only
14. The minimum value II measured when Id(RLCL) is set to Id(RLCL) min as a reference.
15. Either Ih(RHrd) or t(CHrd) must be satisfied for a read cyele.
18. Output-enable-controlled write. Output remains In the high-Impedance state for the entire cycle.
17. Read-modify-write operation only
18. TRG must disable the output buffers prior to applying data to the DO terminals.
19. The maximum value Is specified only to assure RAS access time.
~1ExAs
.
INSTRUMENTS
8-166
POST OFFICE sox 1443· HOUSTON. TEXAS 77251-1443
25
nl
90
nl
155
nl
nl
100
ns
60
SMJ44C251B
262144 BY 4-81T MULTIPORT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (contlnued}t
ALT.
SYMBOL
'44C251B-10
MIN MAX
'44C251B-12
MIN MAX
UNIT
tellRLCHIRF
Delay time, RAS low to CAS high (see Note 2O)
tcHR
25
25
tellCLRLlRF
tel(RHCL)RF
Delay time, CAS low to RAS low (see Note 2O)
tcsR
tRPC
10
10
na
10
10
lIB
25
Delay time, RAS high to CAS low (see Note 2O)
na
tel(CLGH)
Delay time, CAS low to 'i'RG high for DRAM read cycles
tellGHDl
Delay time, 'i'RG high before data applied at DQ
toED
25
30
30
na
tel(RLTH)
Delay time, RAS low to TAG high (real-time-reload read-trensfer cycle
only)
tRTH
90
95
lIB
lIB
tel(RLSH)
Delay time, RAS low to first SC high after TRG high (see Note 21)
tRSD
130
140
lIB
tellCLSHI
Delay time, CAS low to first SC high after TAG high (see Note 21)
tcsD
4C)
45
lIB
tellSCTRl
tel(THRH)
Delay time, SC high to TFm' high (see Notes 21 and 22)
trSL
15
trRD
-10
20
-10
ns
Delay time, TRG high to RAS high (aee Notes 22 and 23)
tel(SCRL)
Delay time, SC high to RAS low with TRG .. W .. low
(see Notes 13 and 26)
taRS
10
20
na
tellSCSEl
Delay time, SC high to SE high in serial-input mode
20
20
lIB
tel(RHSCI
Delay time, RAS high to SC high (see Note 13)
tSRD
25
30
tel(THRL)
Delay time, TRG high to RAS low (see Note 22)
trRP
tellTHSCI
Delay time, TRG high to SC high (see Notes 22)
trSD
tellSESC)
Delay time, SE low to SC high (see Note 25)
tel(RHMS)
Delay time, RAS high to last (most aigniflC8llt) rising edge of SC before
boundary switch during spilt-register read-transfer cycles
tellCLGH)
Delay time, CAS low to TA~ high In real-time read-transfer cycles
tellCASH)
Delay time, column address to first SC In early-load read-transfer cycles
taws
tw(RH)
35
na
lIB
na
tw(RH)
40
na
10
15
ns
15
20
na
tcrH
tASD
5
5
lIB
45
50
lIB
cycles
tATH
10
10
ns
tel(RLCA)
Delay time, RAS low to column address
tRAO
15
tellDCLI
Delay time, data to CAS low
tozc
0
tellDGU
Delay time, data to TRG low
tDZO
tel(CAGH)
Delay time, column address to TRG high in real-time read-transfer
Delay time, RAS low to serial-Input data
50
15
60
na
0
na
0
0
na
50
50
lIB
tel(RLSDl
taDD
Delay time, TRG low to RAS high
ns
25
30
tel(GLRHl
tROH
t Tlmlng meesurements are referenced to VIL max and VIH min.
NOTES; 13. Regi&tar-to-memory (write) transfer cyclea only
19. The maximum value Is apeclfied only to assure RAS access time.
20. CAS-before-RAS refresh operation only
21. Early-load read-transfer cycle only
22. Real-time-reload read-transfer cycle only
23. Late-Ioad read-transfer cycle only
24. Memory-to-register (read) and reglster-to-memory (write) transfer cycles only
25. serial data-In cycles only
28. In a read-transfer cycle, the atata of SC when RAS falls isa don't care condition. However, to assure proper sequencing of the Internal
clock circuitry, there can be no positive transitions of SC for at least 10 na prior to when RAS goes low.
27. In a memory-to-register (read) transfer cycJe, tel(SCRL) applies only when the SAM was previously In aerial-input mode.
~TEXAS
INSTRUMENTS
POeT OFFICE BOX 1443 • HOUSTON. TEXAS 772111-1443
8-167
SMJ44C251B
262144 BY 4-BIT MULTIPORTVIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)t
ALT.
SYMBOL
'44C251B-10
MIN
MAX
'44C251B-12
MIN MAX
UNIT
tc:I(MSRL)
Delay time, last (most significant) rising edge of SO to RAS low before
bound/lry swHch during splH-reglster reed-trMsfer cycles
tc:I(scaSF)
Delay time, last (255 or 511) rising edge of Seto QSFswitching at the
bound/lry during splH-reglstsr reIld-trMsfer cyclas (sse Note 7)
tsaD
40
40
ns
tc:I(OLQSF)
Delaytima, CAS low to QSF swHchlng In reed-transfer orwrite·trMsfer
cycIa8 (sse Note 7)
teQD
35
35
na
tc:I(GHQSF)
Delaytima, TIm high to QSF swHching In re/ld-tr'llnsferorwrita-tr/lnsfer
cycles (88a Note 7)
tyQD
30
30
ns
tc:I(RLQSF)
Dalay tima, ~ low to QSF switching In reed-trMsfer or write-transfer
cycles (sse Note 7)
tRQD
75
75
na
trf
Refresh tlma Interval. mamory
tREF
ty
8
50
8
ms
50
ns
Transition time
tt
t Timing measurements are referenced to VIL max and VIH min.
NOTE 7: SwHchlng times assume OL 100 pF unlesa otherwise noted (88e Figure 12).
25
3
=
PARAMETER MEASUREMENT INFORMATION
VSS
Figure 12. Load Circuit
~1ExAs
INSTRUMENTS
8-168
F'OST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
ns
25
3
SMJ44C251B
262144 BY 4-BIT MULTIPORTVIDEO RAM
SGMS058A- MARCH 1895 - REVISED JUNE 1896
PARAMETER MEASUREMENT INFORMATION
14
!
tcI(~~
=
N!4-
RAS
I 14- tcI(RLCL)
II
~ ~ th(R~
I
I
I
N
1-
I
I
L
...
--!
(CL)
J
0~tw(RH)~"\'----
14-- tcI(CLRH)I---ti
----Ill...-
~
~I ~
1
it ~
CAS
tc(rd)
I
I
~ tcI(CHRL) ~
11+!-!i i
!I
rl
~'-
tw(CH)
14-- tcI(CLGH)
I4-t- tJ,(RLC~ I
teu~ -.! j4-j teU(C~~ ~
__
I
I II
tJ,(CLC~ I II
~
~
. -.~:+~ :~- ~'---I
I I
teu(rd) --:
tcI(OGL)
DQO-OQ3
~
I.
~
I I
I III
I
I
I
I
I
I
I
I
I
14-- tclI8(CH) ~
14- ta(Gj ~
14- tclI8(G) -..,
~>--+I---+!-+1-------«
1
I
14----:I
I
Valid Output
))------
te(C)
~14-- ta(C~
~14----ta(R)
- - - - . -1t
~
Figure 13. Read·Cycle nmlng
:Jf'
ThxAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-169
SMJ44C251B
262144 BY 4-BIT MULTIPORT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
~~
_ _~I ~
N
RAS
l
I
~I 4j
14
I
Icf(CLRH)
I
U'4-Icf(RLCL) ---tj
~1 +tI
ii+ teu(RA)
N~
~th(RA) I
!4+--- th(RLCA)
1 I
I
~~tw(RH)4'---
Icf{RLCH)
It --.I I ~
~
~
tw(RL)
IT
~
~-IIT.II
tw(CL)
~
.
I
14- It
I ~
Icf(CHRL)
I
----.I
"1\1
J '-
tw(CH)
---tl~
. -.~ :+~ ~'-----'1 I I teU(CA)~
ff
th(SF~)~
teu(SFR) ~
:--
1.11
~
lh(CLCA)
I
I
r'
~
th(SFC)
!.+teu(SFd.
I
I
I
I
I I
I
I
I
-.I
DSF~::'~
teu(TRG) --:
j4j-
_~~_~lh(TRG)
.
I I
I
TRG
~ 14- teu(WMR)
: I 1
I I I
~ I I
l.. I 1
r I I
III
~
te
u(WCH)
tau(WRH)
~
11:4
th(RLW)
h(RWM)
14- ~ ~teu(WCL)
W
~
~I~
t4+
I
14
1
14
I I
I I
I
I teu(DCL) ~
th(RDQ)----.I:-1
DQO-DQ3
:
3
tau(DQR)'"
1
~
~
th(CLW)
1
~
tw(WL)
14-~---th(CLD) ---~~
th(RLD)
1
~-----5-----~~
1
1
Figure 14. Early-Wrlte-Cycle Timing
Table 4. Write-Cycle State Table
STATE
CYCLE
1
2
3
4
5
L
L
H
Don't care
Valid data
Write-mask 10adluSB, write DQs to I/Os
L
L
L
Write mask
Valid data
Use previous write mask, write DOs to II0s
H
H
L
L
Don't care
valid data
L
H
Don't care
Write mask
Write operation
Load write mask on later of W fall and CAS fall
~TEXAS
8-170
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SMJ44C251B
262144 BY 4·BIT MULTIPORTVIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
_ _~I
~~
14
N
RAS
I i4
---.I !.t-
II
--tt
r+
IcI(RLCL)
-+IL.
();':)''"~~'':~'V' ~I 14- Ih(RA)
r
,
CAS
,
I ,
I
IcI(RLCA)
J~
tcI(CLRH)
lw(cL)
I ~ I ~1iI I I
'- !tau(CA)~ 1+-1-
I
IcI(CARH)
I !4+--1h(RLCA)'
I
L
tw(RH) - . :
I ~ If- It
I
~
l.
r
I
yT
l--
~
tcI(RLCH)
tcI(CHRL)
~
~
tw(RL)
.,
I
,
IcI(CHRL)
k I
!f-j'l-1It---Iw(CH) - - - . !
J
I
I
,
I
~ 14-'- I . I : ~ ~
AO-AB~ ~Iumn ~....._ _ _ __
tau(RA)
14
1
tau(SFR) --tt
itI(SFR)
!4t
f-+.i
itI(RSF)
j4- ~
mQQfI,I lJ
II1II
If- I
IL
I
itI(SFC)
1
I
h(RWM),
, ~
I'
14 ,
I IcI(QHD)
!III·
~
-1~MR)
~~
.'
Ih(WLQ)
14
tau(WCH)
Ih(RLW)
I
itI(CLW)
--tt 14-1- tau(DQR)
1
I
tau(DWL)-.i
1
I
~ 14- itI(RDQ)
14
I
I
I
I
1
I
~
~
~
")ooI~~
TRO~II~
I 1
I
141
141
I
I
~
tsu(WCH)
tsu(WRH)
1
~I
!4"t
f+I 14- I 1 j4-- tt.(CLW) --,.---+j
tsU(W~",
->I I ~ II ......W)
~
w
2~11 Iw(W~
~
t.u(WC~ -.I
Iti(RWM)
1
~(RLD)
I
--r
I+- --:......- tsu(D~~
~ 14- I
1 l+-- h(CLD)
tt.(ROQ)
tsu(DQR)
OOO-OQ3 ~
~
1
---I
4
~~~~~'I7'm~~~.~~~
Figure 22. Block-Write-Cycle TIming (Early Write)
Table 9. Block-Wrlte-Cycle State Table
STATE
CYCLE
Write-mask Ioad/Use, block write
L
Use previous write mask, block write
H
2
L
L
Write mask disabled, block write to all VOs
L
H
1
I
va
4
Column mask
Don't care
Column mask
Don't care
Column mask
=
Write mask data 0:
write disable
1: VO write enable
Column mask data DOn ..
0 oolumn write disable
(n .. 0, 1, 2, 3) 1 oolumn write enable
=
DOO - oolumn 0 (addreas A 1 0, AD 0)
DQ1 - oolumn 1 (addreas A1 0, AD .. 1)
DQ2 - oolumn 2 (addre88 A1 1, AD 0)
DQ3-oolumn 3 (addre88 A1 .. 1, AD .. 1)
=
=
~1ExAs
8-178
3
Write mask
INSTRUMENTS
POBTOFF1CE BOX 1443 • HOUSTON,lEXAB n251-1443
=
SMJ44C251B
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS068A- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
TAG
*
I
~II
fcI(GHD)
1 I..
1I
-+I jill:" lsu(WMR)
1-+1.
Vi
I+-
~
1I
I
I"
Ih(RWM)
~
I -I ..u(DQR)
I
I...
I+--
~
I"
Ih(CLW)
Ih(WLG)
1
.1
I
·1
I
1
1
1
.1
11x*-tw(WL)~If:1~~~----
III
-+I IIII-j- lsu(DWL)
14- th(RDQ) I j4- th(WLD) --+I
1.. 1
Ih(RLD)
.1
-+I
DQO-DQ3~·
I
I
I
~~
---+j
th(RLW)
I
i
.lsu(WRH)
teu(WCH)
~
4
Figure 23. Block-Wrlte-Cycle Timing (Delayed-Write)
Table 10. Block-Wrlte-Cycle State Table
STATE
CYCLE
1
2
3
4
Write-mask load/use, block write
L
L
Write mask
Column mask
Use previous write mask, block write
H
L
Don't care
Column mask
Write mask disabled, block write to alii/Os
L
H
Don't care
Column mask
column 0 (address A1 =0, AO =0)
OQ1 - column 1 (address A1 =0, AO =1)
OQ2 - column 2 (address A1 =1, AO =0)
OQ3 - column 3 (address A1 =1. AO .. 1)
oao -
Write mask data 0: VOwrite disable
1: VO write enable
Column mask data OQn =
0 column write disable
(n = 0, 1, 2, 3) 1 column writa enable
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-179
SMJ44C251B
262144 BY 4-BIT MULTIPORTVIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1895
PARAMETER MEASUREMENT INFORMATION
AO-Aa
DSF
Table 11. Enhanced-Page-Mode Block-Write-Cycle Table
STATE
CYCLE
1
2
L
Write-mask load/use, block write
L
Use previous write mask, block write
H
L
Write mask disabled, block write to all VOs
L
H
Don't care
Don't care
=
Write mask data 0: VO write disable
1: I/O write enable
Column mask data Dan ..
0 column write disable
(n =0, 1, 2, 3) 1 column write enable
DOO - column 0 (address A1 0, AO • 0)
D01 -column 1 (addressA1 .. 0, AO .. 1)
D02 - column 2 (address A1 .. 1, AO .. 0)
D03,- column 3 (address A1 1, AO .. 1)
=
~TEXAS
INSTRUMENTS
8-180
3
Write mask
POST OFFICE BOX 1443· HOUSTON, TEXAS 77251-1443
4
Column mask
Column mask
Column mask
SMJ44C251B
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS058A- MARCH 1885 - REVISED JUNE 1885
PARAMETER MEASUREMENT INFORMATION
AO-AB
DSF
tau(TRG)
1
-~.--...
~
~
I
.1
th(TRG)
1
NOTE A: In persistent write-per-bit function, Wmust be high at the falling edge of RAS during the refresh cycle.
Figure 25. RAS·Only Refresh·Cycle llmlng
~ThxAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-181
SMJ44C251B
262144 BY 4-BIT MULTIPORTVIDEO RAM
SGMS05BA- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Mi4--------tc(rd) ---------+l~1
~
__~Jt~
Iw(RH)
I
~
~_~~~~==_Iw_~_~=~~~_~_i'~-----------
~ tct~Hc~RF I
I
~ I tct(CLR~RF
,-II
I ~ tct~LCH)RF 11
""'mWr~-.,..,Ir--~\l.
I
j4-- tct(CHR~
I
AO-AS
I
~
g~~g~~:~
I
DSF
~E-~E~
I
,
~E~E~
I
"~E~E~
DQO-DQ3
-~~~valid
- - - - - - - - - - - - - HI-Z _ _ _ _ _ _ _ _ _ _ _ __ _
OU~)-.
NOTE A; In persistent wrlte-per-bit operation. Vii must be high at the failing edge of RAS during the refresh cycle.
Figure 26. CBR-Refresh-Cycle Timing
~1ExAs
8-182
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ44C251B
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMSOSBA- MARCH 1995 - REVISED JUNE 1986
PARAMETER MEASUREMENT INFORMATION
~ Ref....h Cycle
--+I
I+- RefI'1I8h Cycle ---+I
1
1
te(rd)
~I
1
Iw(RH) '4
.1
I
' 14
te(rd)
.1
I+- Memory Read Cycle -.!
,
1
te(rd)
~14
'4
,
1
'1w(RH) 14
.1
.
..... :. Jj ..... :. .,"
... ~H- I.}~"_~ Y \
-+!
CAl
tcI(CHRL)
I
WI I . !
-t+i 1 ,I 1
I I I-H II+Ii}
,
r~
Iw(CL)
tcI(RLCH)
',',
r
~I
I
tcI(RLCA)
I
lh(CLCA)
I 1-+1 ~ tau(CA)
th(RA)W......i 1
14
1
I
I
I
,II'
. -.-=-~
1-1r"T1,1,
-+I r.+ tau(RA) II I
I I
1
I I I 14
I
~i
.
lh(RHrd)
I
Figure 27. Hldden-Refresh-Cycle Timing
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-183
SMJ44C251B
262144 BY 4·BIT MULTIPORTVIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
OQO-OQ3
Tap Point
BltA7
QSF
i4-~---- tct(RLQSF)
~
NOTE: The wrlte-mode-control cycle is used to change the. SDQs from the output mode to the Input mode. This allows serial data to be written
into the data register. This figure assumes that the device was originally in the serial-read mode.
Figure 28_ Wrlte-Mode-Control Pseudo-Transfer Timing
~1ExAs
8-184
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ44C251B
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS058A - MARCH 1895 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
II1II
14
tc(TW)
i't ~(RLC~ ----1
_ _ _ _...,.1
twIRL)
I
W
tl ~
1
1',---
~(RLCH)
II~
I
II1II-- ~(CARH) ~ !4-i-tw(RH)--.I
I
I
1I 1
1
II
~(CHRL) ~~I---.!~ I
CAS
~
~
I
I I-I
teU(CA)~'\l--tw(C~ --HIt
~(RLCA) -t!
'-----...L
I I
ih(RA)!4
I
I
~".
~
I
~th(CLCA) I
II1II-- ~(CARH)
I
I
th(RLCA)
~
I
j4--tw(CH)
J'-
~
----I
I
_.. d'i( ~ ~- ~ ~i:- m~l8g:=E~
DSF
:¥,!:;!:~~*:~
~f~
teU(TRG)
TRG
~ I
'O"O'~~
II II
1
!III
teu(WMR)
iN
DQO-DQ3
1
1
1I ~~~~~~~~~~~~88<~~5<)
Don't Car.
:x
~ th(RWM)
~ ~(RHSC)
~ iII~~
I ~:e~*::¥'~e:~
I I
I
1+ tw(SCH) it!
11'
~(SCR~~
sc
1
--.-(l
~ ~ teu(SDS)
I
I
I
I
I
HI-Z
::
I
----.....,..1- - - - - I !III
~ tw(SCH)
I I' \, \, \
1
1
1:
\'--_
~I ~
II
\.
tw(SC~ ~
I
I"'{~~I
th(SDS)
SOOO-SDQ3:X .... ,. ~Y7'~~
teu(SE)
14
1
SE~
QSF
~
II1II
1
I
1
1
:
~
~ 1 th(SE) 1
11
1
~
~1
14
~(GHQSF)
~(RLQSF)
I
I
~
~(SESC)
T'jllPolnt
ItA7
~
~
Figure 29. Data-Register-to-Memory Transfer Timing, Serial Input Enabled
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77251-1443
8-185
SMJ44C251B
262144 BY 4·BITMULTIPORT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
III
_ _ _ _-oil
I
tcI(CHR~~I011-~~
I
CAS
W"
"'(RA)
r.u(RA)
tcI(RLC~ ----tl
tcI(RLCH)
I+-- tcI(CARH)
I
~ tcI(RLCA) ~
I r:
r.U(SRF)~
~I
~ow
r
D8F~ II
r
1.
taU(TRG~
TRG~.
i\
I
4
~
I
~
1 .......- -
I
!4--+ 1w(RH) ---.!
I
I
I
r.U(CA)~V--Iw(C~+t!
~ .i4
~
I
tl~
I
I
I
I
I
~
~
Iw(RL)
'It
N:
RAS
AO-AS
fc(TW)
14
I
"'(RLCA)
I 1_
_I
I
~
I
r--l th(CLCA) I
I
~ Iw(CH) 4
~
)@t T~~~t ~'""~ft"7'I'I:~~¥,~i'ft'ftS§fft"7'l'l~:~~~~'
~
"'(SFR) I
I
~:;';E~
!
1
~~~
W~lrI ~:=E:~
--....;r------14-It!
~ Iw(SC~
~ II
::
-.I: 1\ \ \ \ \ .0 , __
~I r+i
I
II
II
14
~II L
I
I
I
I
OQO-OQ3 ----~.----T--_;_- HI.z
Iw(SCI1)
I
I
tcI(SCRL)
I 14
I I
14
I
."
sc
tau(SOS)
SOQO-SOQ3
X
I~
L
Ofta,n
I
-.r
14-
..
Iw(SCL)
I-~!
t
r~
th(SOS)
I
~:¥,~~;!:~~~;:~~taln ~
I
tcI(SCSE)
I
I
r.U(SOS)p
I
I
I
I
~::~~~:;~¥,~:~
~
tcI(SESC)
Tap Point
BHA7
QSF
I
/II
tcI(GHQSF)
tcI(RLQSF)
~
~
Figure 30. Alternate Data-Reglster-to-Memory Transfer-Cycle TImIng
-!111ExAs
INSTRUMENTS
8-186
POST OFFICE BOX 1443· HOUSTON, 1CXAS n251-1443
SMJ44C251B
262144 BY 4-BIT MULTIPORT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
~
tc(TRO)
I 14
----."jl\G
! 1;
tci(CHRL) -ilj41---....1
I
II
~
F
1w(RL)
tci(RLCL) ~
F
~
OSF
:7-
~
__
teu(SFR)
M
ItT tci(CARH) :.I
teU(RA)~ !.--1h~R~A)~
AO-AS
14
"k
¥ /4--1w(RH) ---.i ,,"----
lw(cL)
I
tci(RLCA) ~~'l.
I ~1h(RA) -II
1I
teU(6A) ~ i+T~ th(CLCA)
ztllI·
I
J~
~
tci(RLCH)
.1
~
I
JI
~~
~~~:,~fJ'!:?'~~~:~~~~li~'X~m'I'~*m'I'~~~~
~ Ih(SFR) I
1117'I.~~~~~~~~~~~~~~
- 1 1 -
OQO-OQ3
SC
SOQO-SOQ3
QSF
H
L --------------------------------------------------------NOTES: A. Early-load operation Is defined as t!J(TRG) min < th(TRG) < 1d{RLTH) min.
B. DQ outputs remain In the high-Impedance state forthe entire memory-to-data-reglstertransfer cycle. The memory-to-data-register
transfer cycle Is used to load the data registers In parallel from the memory array. The 512 locations in each data register are written
from the 512 corresponding columns of the selected row. The data that Is transferred into the data registers can be either shifted
out or transferred back into another row.
O. Once data is transferred into the data registers. the SAM Is in the serial-read mode (I.e .• SQ is enabled). allowing data to be shifted
out of the registers. Also. the first bit to be read from the data register after TRG has gone high must ba activated by a positive
transition of SO.
'
Figure 31. Memory-to-Data-Reglster Transfer-Cycle Timing. Early-Load Operation
-!!1 ThxAs
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON, 1CXAS 7"1251-1443
8-187
SMJ44C251B
282144 BY 4-BIT MULTIPORT VIDEO RAM
SGMS068A.,. MARCH 1996 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
14
1 14
~
te(TRD)
~
tw(RL)
I
------~~I~
tcI(CHR
4.
--l4I4I----tl~ ~I
~
1
._
~
ttI(RA)
_I ~ttI(RLCA) II 1
AO-AS
~
~
I
~
~
~
I
§§§§§W
---4
-.
SDQO-SDQ3
Old Data
.~
k- teu(CA)
~ It1(CLCA)
1
tcI(CAG~ ~ I
tcI(RL~
~I ttl (RWM)
AO-AS
II
H
I
I
I
I
~ pl4_~;....-.tcI~(~TH_R_~.:-.....,~~ftftlO~ftftlO~_
~A'
~
of1 ij4-- tw(G~ ----.I
tcI(SCTR)
~ 1..1
~ tcI(THSC)
I
HI..z -+1----11----------I
I
I
14 I
I I
I
;1
I \ '~ :
tw(SCL)
I
~jl I
.
Old Data
\1
14
I
I:
:
/~ta(SQ)~\---tl
I
X.
I
QSF
.
~EE~
!
: .
III
~ tcI(THRL)~
I I
X
I
I
I
1
~ ta(SQ) ~I jill
I
ttI(SHSQ).
l.v
l_:E*t;!::~
II
JI
tw(SC~ -I4-j.--...r~
se
II -
I
I
I
DQO-DQ3
--.j
~ It1(SFR)
1"1
'1!4
~
teu(WMR) ~ I·
VI
tw(R~~'~_ ___
~:'\\T:;~
~::?;:~*::Jxxxxxxxx>
~
Row
teu(SFR) ~
DSF
L
:
1
~I
tcI(RLC~ tw(CL) ~
III rld(RLCA)~··N·
I
teu(RA) ~
1
I
1 ~ld(RLCL) ~
~
te(SC)
I
I
It1(SHSQ) -li+.----i~*1 I
XII;,__
Old Data
N_'_W_D_ata
__
i+-ld(GHQSF) --+I
:
;..
Y"'"--11-a-p-po-lnt-B-lt-A7-tcI(CLQSF)
~
I..
tcI(RLQSF)
~1
L -------------------------~~~-----------------------Late-load operation Is defined as fcjCTHRH) < 0 ns.
NOTES: A.
B. DQ outputs remain In the hlgh-lmpedance state for the entire memory-to-data-reglster transfer cycle. The memory-to-data-reglster
transfer cycle Is used to load the data registers In parallel from the memory array. The 5121ocallons In each data register are written
from the 512 corresponding columns of the selected row. The data that is transferred Into the data registers can be either shifted
out or transferred back Into another row.
C. Once data Is transferred Into the data registers. the SAM Is In the serial read mode Q.e •• sa Is enabled). allowing data to be shifted
out of the registers. Also. the first bit to be read from the data register after 'fAG has gone high must be activated by a positive
transition of SC.
Figure 32. Memory-to-Oata-Reglster Transfer-Cycle nmlng,
Real-nme-Reload Operation/late-load Operation
~ThxAs
INSTRUMENTS
8-188
POST OFFICE 8OX1443 • HOUSTON.1EXA$ mS1-1443
SMJ44C251B
262144 BY 4·BIT MULTIPORTVIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
14
----.
.
.
.
"i'
t
=
~14J---
tc(TRD)
1 14
...1 I
I I
I I
tcI(CHRL)
vvvvA-
Ir
~
-r-----l
L
teu(RA)
_I
I
1
~
AO-AS
tcI(RLCL)
~
~ "'(RA) -.:
I
I
r
I
tw(CL)
I
tw(RH)
I
_..!
IY
4I ~
~
I
"'(CLCA)
---.j ~ teu(CA)
~'---I
I
I
I
I
I
~
I
~;i~:~:e~li~¥'~e:~
ROw
F
~ ~I
14
~
lh(RLCA)
I-
II
.1
-k!~
H tcI(CARH) ~
I "!\~
i
lh(SFR)
DSF
~
tcI(RLCH) :
tcI(RLCA)
~
tt
tw(RL) I
teu(SFR)
teu(TR
~~~
~tcI(CAGH)
~
1:e~*K~e:
tcI(CLGH)
1I·
14
~ I
~ ~
tcI(THRH)
1
I
1
tcI(THRL)
~
~"'(TRG)~.IIII// / / / / f u t w ( G H ) ~~:~i~!:~E~:~
I
~
~(WM~~~
Vi
if
th(RWM)
I
~
DQO-DQ3
SC
SDQO-SDQ3
QSF
H
L --------------------------------------------------------------
NOTES: A Late-load operation is defined as tclCTHRH) < 0 ns.
B. DO outputs remain In the high-Impedance state for the entire memory-to-data-reglster transfer cycle. The memory-to-data-reglstar
transfer cycle is used to load the data reglstars In parallel from the memory arrey. The 51210cetions In each data registar are writtan
from the 512 corresponding columns of the selectad row. The data that Is transferred into the data registars may be either shifted
out or transferred back Into another row.
C. Once data Is transferred Into the data registers, the SAM is In the serial read mode Q.e., SO Is enabled), allowing data to be shifted
out of the registers. Also, the first bit to be read from the data register after TRG has gone high must be activated by a posltlve
transition of SC.
Figure 33. Memory-to-Oata-Reglster Transfer-Cycle Timing, SOQ Ports Previously In Serial-Input Mode
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-189
SMJ44C251B
262144 BY 4-BIT MULTIPORT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Bit 255 or
Bit 511
SDQO-SDQ3
.1 tcI(SCQSF)
1
X
QSF
Bit 255 or
Bit 511
Tap Point M
tcI(SCQSF)
Old
I
1l1li
MSB~~
Tap
PolntN
1l1li "I
la(SQ)
"I
X
NewMSB
H
IE
L _____________________
~------~"I~------------------------II
Figure 34. Split-Register-Mode Read-Transfer-Cycle Timing
~TEXAS
INSTRUMENTS
8-190
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77261-1443
SMJ44C251B
262144 BY 4·BIT MULTIPORTVIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
AO-AS
,
I ,..---1-----"\.\-_ _..",-'1'1
DSF
RowTap1
(hIgh)
-------;i--Jf\
SC
CASElli
SC
QSF
,
,
,,~~T-,,
,
,
,,
,,
255' (hIgh)
------:\~-+_,, ------iSr--?',
,,,
CASE II
QSF
,RowTap2
,(hIgh)
.~~~
1,
Tap
(lOW),
SC
,RowTap2
,(low)
~----+~\......J,....---i',~~T--
CASE I
QSF
,-'J~r----
~~r---
:x::::x:::x~-~~~
~~
RowTap1
(low)
TAG
,\.
,,,
/I
II
'
511
I, \
,
,
,
(low)
255
s~
-------.j.I---~~~~
,
(low)
255, (hIgh)
,
511
(low)
255
___. . .;.....
\ _--+I______----\'~
'/1 I \
"
,~
,
,..,..-r
,
,
,
,
,
,
,
,
,
--------r'--------~~~~~
(low)
255' (hIgh)
,
511
(low).
255
__ _ _,_ _-+-_ _ _ _ _---'1,.
~
,'r-1
Normal Read Tranafer
Split Register to the
High Half of the
Data Register
',S', \
,SpIH Register to the'
,
Low Half of t h e '
,
Data Register,
",..,..-r
Split Register to the
High Ha" of the
Data Register
NOTES: A. In order to achieve proper split-register operation. a normal read transfer should be performed before the first split-register transfer
cycle. This is necessary to Initialize the data register and the starting tap location. First serial access can then begin either after the
normal read-transfer cycle (CASE I). during the first split-register cycle (CASE II). or even after the first split-register transfer cycle
(CASE III). There is no minimum requirement of se clock between the normal read-transfer cycle and the first split-register cycle.
B. Asplitreglatertrsnsferlntotheinactivehalflsnotalioweduntilld(MSRL)lsmet.:!!mASRL)1alheminimum delaylimebetweenthe rising
edge of the serial clock of the last bit (bit 255 or 511) and the falling edge of RAS of the spilt-register transfer cycle Into the Inactive
half.AfterldlMSRL) lame!, thesplit-registertransferintothe inactive halfmustalsosetlsfytheld(RHMSl requirement Id(RHMS) isthe
minimum delay time between the rising edge of RAS of the split-register transfer cycle into the inactive half and the rising edge of
the serial clock of the last bit (bit 255 or 511). There Is a minimum requirement of one rising edge of SC clock between two split-register
transfer cycles.
Figure 35. Spllt-Reglster-Transfer Operating Sequence
~1EXAS
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON. TEXAS 77251-1443
8-191
SMJ44C251B
262144 BY 4-BIT MULTIPORT VIDEO RAM
SGMS058A- MARCH 1996 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
"'(11101 ---:
14
j4-1w(SCH)
SC
~
~I I
I
14 ~I I
tau(SDS)
I4-+t-
valid I"
th(SDS)
I
I
~
I I
~
tau(SDS)
~
valid I"
""TIIO)
•
~I:
I
tc(SC)
---It"'": \[-11
14
I
I
SDQO-SDQ3
~
~
tc(SC)
.
Iw(SCH)
~I
~ Iw(SCH) ~
\r-11 \'---
ih(SDS)
14 ~ I
I
I
~
tau(SDS)
~
valid I"
"'(SDS)
.
~
NOTES: A. The serial data·1n cycle Is used to Input s~rial data Into the data registers. Before data can be written Into the data registers via the
soa terminals, the device must be put Into the write mode by performing a wrlte-mode-control (pseudo-transfer) cycle or any other
wrlte·transfer cycle. A read·transfer cycle Is the only cycle that takes the serial port (SAM) out of the write mode and puts It Into the
read mode, disabling the Input data. Data Is written startlng at the location specified by the Input address loaded on the previous
transfer cycle.
B. While accessing data In the serial·data registers, the state of 'fAG is a don't care as long as TRG Is held high when RAS goes low
to prevent data transfers between memory and data registers.
.
Figure 36. Serlal-Wrlte-Cycle Timing (SE = VIL>
~TEXAS
INSTRUMENTS
8-192
POST OFFICE sox 14<13 • HOUSTON. lEXAS 77251.14<13
SMJ44C251B
262144 BY 4-BIT MULTIPORT VIDEO RAM
SGMS058A- MARCH 1995 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
'
t
t
fRG~
......0) --:
1l1li
1+ Iw(SCH} ~
SC
---A'f:
II1II
~
I
I
8DQO-80Q3
r
\[~ 11
II
I teu(SDS)
1 I
1 jIIII--+I-
te(SC)
.,
~ Iw(SCH} ~
tw(SCH)
\["-' 11I
II1II
1 1
1 1
th(SDS)
~
~
\ ____
teu(SDS)
I
1 1
II(4--+!-
1h(SDS)
~ ~~~ ~ ~I~I' ~
tci(SESC)
~ II1II+
tct(SCSE)
!..
....
SE
.~
te(SC)
""' 1995, Texas Instruments Incorporated
8-197
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS058A- MAY 1895 - REVISED JUNE 1985
GSPACKAGE
(BOTTOM VIEW)
000000000
000000000
0000 0000
000
000
00
00
000
000
0000 0000
000000000
000000000
2
3
4
5
6
7
8
~TEXAS
INSTRUMENTS
8-198
POST OFFICE SOX 1443 • HOUSTON. 'relCAS 77251-1443
9
J
H
G
F
E
D
c
B
A
SMJ55161
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SGMS056A- MAY 1995 - REVISED JUNE 1995
GB Package Pin Assignments - By Location
PIN
NO.
NAME
Jl
Hl
Gl
Fl
El
01
Cl
81
Al
001
oao
sao
'fAG
SC
SE
sa15
oa15
sa14
PIN
NO.
NAME
J2
H2
G2
F2
E2
02
C2
82
A2
S03
002
sal
VSSl
VOOl
VSSl
VSSl
oa14
sa13
NO.
PIN
NAME
J3
H3
G3
F3
003
oa2
V002
VOOl
03
VOOl
V002
0013
sa12
C3
83
A3
NO.
PIN
NAME
J4
H4
G4
004
SQ4
VSS2
C4
B4
A4
VSS2
oa12
sal1
NO.
J5
H5
85
AS
PIN
NAME
005
sa5
oall
salO
NO.
PIN
NAME
NO.
J6
H6
G6
oas
sas
V002
J7
H7
G7
C6
86
A6
V002
oal0
sa9
PIN
NAME
F7
S07
oa7
VSS2
VOOl
07
C7
87
A7
VSSl
VSS2
sa8
oa9
NO.
J8
H8
G8
F8
E6
08
C8
B8
AS
PIN·
NAME
CASL
WE
RAS
VOOl
VSSl
A3
CASU
OSF
oa8
NO.
PIN
NAME
J9
H9
G9
F9
E9
09
C9
89
AS
AS
aSF
A7
AS
AS
A4
A2
Al
AO
GB Package Pin Assignments - By Signal
PIN
PIN
PIN
PIN
PIN
PIN
NAME
NO.
NAME
NO.
NAME
NO.
NAME
NO.
NAME
NO.
NAME
NO.
AO
Al
89
C9
A3
06
E9
F9
G9
H9
J9
J8
C8
Hl
oa12
oa13
oa14
oa15
OSF
aSF
RAS
SC
SE
sao
sal
84
83
82
81
88
sa2
sa3
sa4
sa5
sas
sa7
sa6
sa9
salO
sal1
sa12
H2
J2
H4
H5
H6
J7
87
sa13
sa14
sa15
TAG
VOOl
VOOl
VOOl
VOOl
VOOl
V002
V002
V002
V002
VSSl
VSSl
VSSl
VSSl
VSSl
VSS2
VSS2
VSS2
VSS2
WE
G6
D9
Jl
H3
J3
J4
J5
J6
H7
A2
A2
oal
oa2
oa3
004
005
oa6
oa7
008
0Q9
oalO
oal1
A4
AS
A6
A7
AS
CAS[
CASU
oao
AS
A7
B6
85
AS
G6
El
01
Gl
G2
AS
AS
A4
A3
Al
Cl
Fl
E2
F3
03
F7
F8
G3
C3
C8
F2
D2
C2
07
E8
G4
C4
G7
C7
H8
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-199
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS068A- MAY 1995 - REVISED JUNE 1995
description
The SMJ55161 multiport video RAM is a high-speed, dual-port memory device. It consists of a dynamic
random-access memory (DRAM) organized as 262144 words of 16 bits each interfaced to a serial-data register
(serial-access memory (SAM» organized as 256 words of 16 bits each. The SMJ55161 supports three basic
types of operation: random access to and from the DRAM, serial access from the serial register, and transfer
of data from any row in the DRAM to the serial register. Except during transfer operations, the SMJ55161 can
be accessed simultaneously and asynchronously from the DRAM and SAM ports.
The SMJ55161 is equipped with several features deSigned to provide higher system-level bandwidth and to
simplify deSign integration on ~th the DRAM and SAM ports. On the DRAM port, greater pixel draw rates are
achieved by the device's (4 x 4) x 4 block-write feature. The block-write mode allows 16 bits of data (present
in an on-chip color-data register) to be written to any combination of four adjacent column-address locations.
As many as 64 bits of data can be written to memory during each CAS cycle time. Also on the DRAM port, a
write mask or a write-per-bit feature allows masking of any combination of the 16 inputs/outputs on any write
cycle. The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent
write cycles without reloading. The SMJ55161 also offers byte control. Byte control can be applied In read
cycles, write cycles, block-write cycles, load-write-mask-register cycles, and load-COlor-register cycles. The
SMJ55161 also offers extended-data output mode. The extended-data output mode is effective in both the
page-mode and standard DRAM cycles.
The SMJ55161 offers a split-register-transfer read (DRAM-to-SAM) feature for the serial register (SAM port).
This feature enables real-time register load implementation for continuous serial-data streams without critical
timing requirements. The register is divided into a high half and a low half. While one half is being read out of
the SAM port, the other half can be loaded from the memory array. For applications not requiring real~time
register load (for example, loads done during CRT-retrace periods), the full-register mode of operation is
retained to simplify system deSign.
The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up
to 45 MHz. During the split-register-transfer read operations, internal circuitry detects when the last bit position
is accessed from the active half of the register and immediately transfers control to the opposite half. A separate
output, QSF, Is included to indicate which half of the serial register is active.
.
All inputs, outputs, .and clock Signals on the SMJ55161 are compatible with Series 74 TTL. All address lines and
data-in lines are latched on-Chip to simplify system design. All data-out lines are unlatched to allow greater
system flexibility.
The SMJ55161 employs state-of-the-art Texas Instruments (TI) enhanced performance implanted CMOS
(EPICTM) scaled-CMOS, double-level polysilicon/polycide gate technology combining very high performance
with improved reliability.
The SMJ55161 is offered in a 68-pin ceramic pin-grid-array package (GB suffix) and a 64-pin ceramic flatpack
(HKC suffix).
The SMJ55161 and other TI multiport video RAMs are supported by a broad line of graphic processors and
control devices from TI. Refer to Tables 1 and 2 for additional function and description information.
~TEXAS
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SMJ55161
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SGMS056A- MAY 1995 - REVISED JUNE 1995
functional block diagram
r--------,
I
. . . . . .~I
DSF
"_III
Input
Buffer pi
1 of 4 Sub-Blocks
(8se next page)
~iDIIl
I
I
I
II.. _ _ _ _ _ _ _ _ .JI
r--------,
I
I
gm:i:I
I
DQO-_...
16.....
DQ15
•••column
Buffer
~tI
lIIIlI
8
1 of 4 Sub-Blocks
(8se next page)
AO-AS
DRAM
output~• • • •1!
"~HII.. _ _ _ _ _ _ _ _ .JII
Buffer
1 of 4 Sub-Blocks
(8se next page)
I
II.. _ _ _ _ _ _ _ _ .JI
SQOSQ15
16
SerialOutput
Buffer
r--------,
I
I
!iJBlj~
I
SE
RAI
CASx
TRG
WE
Timing
Generator
I
I
1 of 4 Sub-Blocks
(see next page)
II.. _ _ _ _ _ _ _ _ .JI
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functional block diagram (continued)
sc
1 of 4 Sub-Blocks
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Function Table
CASx
FALL
RASFALL
ADDRESS
DQO-DQ15t
FUNCTION
Reserved (do not use)
CBR refresh (no reset) and stop-point
MNE
CODE
RAS
CASx§
RAS
CASL
CASU
WE
X
X
X
X
X
CBRS
CASx*
TRG
WE
OSF
OSF
L
L
L
L
set'
CBR refresh (option reset)1i
L
X
L
H
X
Stop
Polnt#
X
X
X
L
X
H
L
X
X
X
X
X
CBR
CBR refresh (no reset)*
L
X
H
H
X
X
X
X
X
CBRN
Full-register-transfer read
H
L
H
L
X
Row
Addr
Tap
Point
X
X
RT
Split-register-transfer read
H
L
H
H
X
Row
Addr
Row
Addr
Tap
Point
X
X
SRT
Write
Mask
Valid
Data
RWM
Write
Mask
Col
Mask
BWM
Col
Addr
X
Valid
Data
RWM
Row
Addr
Block
Addr
A2-AS
X
Col
Mask
BWM
L
Row
Addr
Col
Addr
X
Valid
Oste
RW
L
H
Row
Addr
Block
Addr
A2-AS
X
Col
Mask
BW
H
H
L
X
X
Write
Mask
LMR
H
H
H
X
X
Color
Data
LCR
DRAM write
(nonpersistent write-per-blt)
H
H
L
L
L
DRAM block write
(nonpersistent write-par-bit)
H
H
L
L
H
Row
Addr
Col
Addr
Block
Addr
A2-AS
DRAMwrita
(persistent writa-per-bit)
H
H
L
L
L
Row
Addr
DRAM block write
(persistent write-per-bit)
H
H
L
L
H
DRAM write (nonmasked)
H
H
H
L
DRAM block write (nonmasked)
H
H
H
Load write-mask registerCl
H
H
Load color register
H
H
Refresh
Addr
Refresh
Addr
Legend:
Col Mask
H: Writa to addreSs/column enabled
Writa Mask
H: Write to
enabled
X
Oon'tcere
t 000- 0015 are latched on either the first falling edge of CASx or the falling edge of WE. whichever occurs leter.
* logic L Is selected when either or both CAS[ and CASU are low.
SThe column address and block address are latched on the first falling edge of CASx.
, CBRS cycle should be performed immediately after t!'le powerup initialization cycle.
# AO-A3. AS: don't care; M-A7: stop-point code
II CBR refresh (opt/on reset) mode ends persistent write-per-bit mode and stop-point mode.
>\:CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
Cl Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode Is reset only by the CBR (option reset)
cycle.
=
=
=
va
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Table 1. Pin Description Versus Operational Mode
PIN
Row, column address
TRANSFER
Row address, tap point
CASU
Column-address strobe, DO output enable
Tap-address strobe
DO
DRAM data VO, write mask
OSF
Block-write enable
Write-mask-register load enable
Color-registar load enable
CBR (option reset)
Split-register-transferenable
.fiAS
Row-address strobe
Row-address strobe
AO-AS
CAS[
DRAM
SO output enable,
aSF output enable
Serial clock
Serial-data output
~
SC
sa
TRG
WE
oa output enable
Write enable, write-per-bit enable
Transfer enable
aSF
NC/GNO
SAM .
Serial-regiSter status
Either make no extemal connection· or tie to system GNO (VSS)
S-Vsupply
Ground
VCCt
vsst
t For proper device operation, all Vec pins must be connected to a 5-V supply, and all VSS pins must be tiad to ground.
pin definitions
at;ldress (AO-AS)
Eighteen addreSs bits are required to decode one of 262 144 storage cell locations. Nine row-address bits are
set up on pins AD-AS and latched onto the chip on the falling edge of RAS. Nine column-address bits are set
up on pins AD-AS and latched onto the chip on the first falling edge of CASx. All addresses must be stable on
or before the falling edge of RAS and the first falling edge of CASx.
During the full-register-transfer read operation, the states of AD-AS are latched on the falling edge of RAS to
select one of the 512 rows where the transfer occurs. At the first falling edge of CASx, the column-address bits
AO-A8 are latched. The most significant column-address bit (AS) selects which half of the row is transferred
to. the SAM. The appropriate a-bit column address (AD-A7) selects one of 256 tap pOints. (starting positions)
for the serial-data output.
During the split-register-transfer read operation, address bit A7 is ignored atthe falling edge ofCASx. An internal
counter selects which half of the register is used. If the high half of the SAM is currently in use, the low half of
the SAM is loaded with the low half of the DRAM half row and vice versa. Column address (AS) selects the DRAM
half row. The remaining seven address bits (AD-AS) are used to select one of 127 possible starting locations
within the SAM. Locations 127 and 255 are not valid tap points.
row-address strobe (RAS)
RAS is similar to a chip enable so that all DRAM cycles and transfer ~s are initiated by the falling edge of
RAS. RAS is a COntrol input that latches the states of the row address, WE, TRG, CASl, CASU, and DSF onto
the chip to invoke DRAM and transfer-read functions of the SMJ55161.
-!11
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column-address strobe (CASL, CASU)
CASL and CASU are control inputs that latch the states of the column address and DSF to control DRAM and
transfer functions of the SMJ55161. CASx also act as output enables for the DRAM output pins DOO-D015.
In DRAM operation, CASL enables data to be written to or read from the lower byte (DOO-D07), and CASU
enables data to be written to or from the upper byte (D08-D015). In transfer operations, address bits AO-AS
are latched at the first falling edge of CASx as the start position (tap) for the serial-data output (SOO-S015).
output enable/transfer select (TRG) .
TRG selects either DRAM or transfer operation as RAS falls. For DRAM operation, TRG must be held high as
RAS falls. During DRA~ration, TRG functions as an output enable for the DRAM output pins DOO-D015.
For transfer operation, TRG must be brought low before RAS falls.
write-mask select, write enable (WE)
In DRAM operation, WE enables data to be written to the DRAM. WE is also used to select the DRAM
write-par-bit mode. Holding WE low on the falling edge of RAS invokes the write-per-bit operation. The
SMJ55161 supports both the nonpersistent write-per-bit mode and the persistent write-par-bit mode.
special-function select (DSF)
The DSF input is latched on the falling edge of RAS or the first falling edge of CASx, similar to an address. DSF
determines which of the following functions are .invoked on a particular cycle:
•
•
•
•
•
•
•
CBR refresh with reset (CBR)
CBR refresh with no reset (CBRN)
CBR refresh with no reset and stop-point set (CBRS)
Blockwrite
Loading write-mask register for the persistent write-per-bit mode (LMR)
Loading color register for the block-write mode
Split-register-transfer read
DRAM data I/O, write mask data (DQO-DQ15)
DRAM data is written or read through the common I/O DO pins. The 3-state DO-output buffers provide direct
TTL compatibility (no pullup reSistors) with a fanout of one Series 54 TTL load. Data out is the same polarity
as data in. During a normal access cycle, the outputs remain in the high-impedance state until TRG is brought
low. Data appears atthe outputs until TRG returns high, CASx returns high following RAS returning high, or RAS
returns high following CASx returning high. The write mask is latched into the device via the random DO pins
by the falling edge of RAS and is used on all write-per-bit cycles. In a transfer operation, the DO outputs remain
in the high-impedance state for the entire cycle.
serlal-data outputs (SQO -SQ15)
Serial data is read from the SO pins. The SO output buffers provide direct TTL compatibility (no pullup reSistors)
with a fanout of one Series 54 TTL load. The serial outputs are in the high-impedance (floating) state as long
as the serial-enable pin, SE, is high. The serial outputs are enabled when SE is brought low.
serial clock (SC)
Serial data is accessed out of the data register from the rising edge of SC. The SMJ55161 is designed to work
with a wide range of clock duty cycles to simplify system design. There is no refresh requirement because the
data registers that comprise the SAM are static. There is also no minimum SC-clock operating frequency.
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serial enable (§E)
During serial-access operations, SE is used as an enable/disable for the sa outputs. SE low enables the
serial-data output. SE high disables the serial-data output. SE is also used as an enable/disable for output pin
aSF.
IMPORTANT: While SE is held high, the serial clock is not disabled. External SC pulses increment the Internal
serial-address counter regardless of the state of SE. This ungated serial-clock scheme minimizes access time
of serial output from SE low because the serial-clock input buffer and the serial-address counter are not disabled
bySE.
special-function output (QSF)
aSF is an output pin that indicates which half of the SAM is being accessed. When aSF is low, the serial-address
pointer is accessing the lower (least significant) 128 bits of the serial register (SAM). When aSF is high, the
pOinter is accessing the higher (most significant) 128 bits of the SAM.
During full-register-transfer operations, aSF can change state upon completing the· cycle. This state is
determined by the tap point loaded during the transfer cycle. aSF is enabled by SE. If SE is high, the aSF output
is in the high-impedance state.
n~
connect/ ground (NC/GND)
NC/GND should be tied to system ground or left floating for proper device operation.
~I~ TEXAS
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SMJ55161
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functional operation description
random access operation
DRAM Function Table
CASi
RASFALL
FALL
ADDRESS
DOO-DQ1St
FUNCTION
Reserved (do not use)
CASi*
TRG
WE
L
L
L
CBR refresh (no reset) and stop-point
set'
CBR refresh (option reset)lI
L
L
CBR refresh (no raset)*
L
DRAM write
(nonpersistent wrlte-per-bit)
CASL
UNE
CODE
DSF
DSF
RAS
CASi§
RAS
CASU
L
X
X
X
X
X
-
X
X
X
CBRS
X
X
X
CBR
CBRN
WE
L
H
X
H
L
X
Stop
Point'
X
X
H
H
X
X
X
X
X
H
H
L
L
L
Row
Addr
Col
Addr
Write
Mask
VBlld
Data
RWM
DRAM block write
(nonpersistent writa-per-blt)
H
H
L
L
H
Row
Addr
Block
Addr
A2-AS
Writa
Mask
Col
Mask
BWM
DRAM write
(persistent write-per-bit)
H
H
L
L
L
Row
Addr
Col
Addr
X
Valid
RWM
DRAM block write
(persistent write-per-bit)
H
H
L
L
H
Row
Addr
Block
Addr
A2-AS
X
Col
Mask
BWM
DRAM write (nonmasked)
H
H
H
L
L.
Row
Addr
Col
Addr
X
Valid
Data
RW
DRAM block write (nonmasked)
H
H
H
L
H
Row
Addr
Block
Addr
A2-AS
X
Load wrlte-mask raglster e
H
H
H
H
L
Refresh
Addr
X
Load color register
H
H
H
H
H
Refresh
Addr
X
X
X
Data
Col
Mask
BW
X
Write
Mask
LMR
X
Color
Data
LeR
Legend:
Col Mask
.. H: Write to addrass/column enabled
Write Mask .. H: Write to
enabled
X
= Don'tcare
t DQO-DQ15 Bra latched on either the first failing edge ofCASx or the failing edge of WE. whichever occurs later.
Logic L is selected when either or both CASL end CASU Bra low.
SThe column addrass and block addrass ere latched on the first failing edge of CASx.
, CBRS cycle should be performed immediately after the power-up initialization cycle.
, AO-iu. AS: don't cere; A4-A7: stop-point code
II CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
>,t~
ld(SCQSF)
____________________
Figure 20. Example of Successive Split-Register-Transfer Read Operations
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serial-read operation
.The serial-read operation can be performed through the SAM port simultaneously and asynchronously with
DRAM operations except during transfer operations. Serial data can be read from the SAM by clocking SC
starting at the tap point loaded by the preceding transfer cycle, proceeding sequentially to the most significant
bit (bit 255), and then wrapping around to the least significant bit (bit 0), as shown in Figure 21.
r'
011121
•• .. ·1
.
Tap
1-+ ... 125412551
I
.
Figure 21. Serial-Pointer Direction for Serial Read
For split-register-transfer read operation, serial data can be read out from the active half of the SAM by clocking
SC starting at the tap point loaded by the preceding split-register-transfer cycle. The serial pOinter then proceeds
sequentially to the most significant bit of the half, bit 127 or bit 255. If there is a split-register-transfer read to
the inactive half during this period, the serial pointer points next to the tap point location loaded by that
split-register transfer (see Figure 22).
Figure 22. Serial Pointer for Split-Register Read - Case I
If there Is no split-register-transfer read to the Inactive half during this period, the serial pointer points next to
bit 128 or bit 0, respectively (see Figure 23).
Figure 23. Serial Pointer for Split-Register Read - ,Case II
split-register programmable stop pOint
The SMJ55161 offers programmable stop-point mode for split-register-transfer read operation. This mode can
, be used to Improve two-dimensional drawing performance in a nonscanline data format.
In split-register-transfer read operation, the stop point is defined as a register location at which the serial output
stops coming from one half of the SAM and switches to the opposite half of the SAM. While In stop-point mode,
the SAM is divided into partitions whose length is programmed via row addresses M-A7 in a CBR set (CBRS)
cycle. The last serial-address location of each partition is the stop point (see Figure 24).
0
Partition
Length
I
~
,
I
127 128
I· •·1
1. ..
I
1
255
I
1 L..
Figure 24. Example of the SAM With Partitions
-!11 ThxAs
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1
Stop
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SMJ55161
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split-register programmable stop point (continued)
Stop-point mode Is not active until the CBRS cycle is initiated. The CBRS operation is performed by holding
CASx and WE low and DSF high on the falling edge of RAS. The failing edge of RAS also latches row addresses
A4-A7 which are used to define the SAM's partition length. The other row-address inputs are don't cares.
Stop-point mode should be initiated after the initialization cycles are performed (see Table 3).
Table 3. Programming Code for Stop-Point Mode
MAXIMUM
PARTInON
LENGTH
AS
A7
AS
AS
A4
AO-A3
18
X
L
L
L
L
X
18
15.31.47.63.79.95.111.127.143.159.175.
191.207.223.239.255
32
X
L
L
L
H
H
H
8
31.83.95.127.159.191.223.255
X
L
L
X
64
X
4
83.127.191.255
X
L
H
H
H
X
2
127,255
ADDRESS AT RAS IN CBRS CYCLE
128
(default)
NUMBER OF
PARTITIONS
STOP-POINT LOCATIONS
In stop-point mode, the tap point loaded during the split-register-transfer read cycle determines the SAM
partition in which the serial output begins and at which stop point the serial output stops coming from one half
of the SAM and switches to the opposite half of the SAM (see Figure 25).
RAS
~~
Full
~"d XFEy'
r---",""",
Spilt
Split
~.ad XFE'i'
Tap=L1
Tap=H2
Tap_H1
r-
Split ~
..d XFE'j
r---",
~.ad XFE'i'
"
Tap .. L2
H1
191 L1
63 H2
255 L2
SC _ _ _ _ _ _ _ _~~ ••• ~ ••• ~ • • • • • • ~
0
L1
[
SAM Low Half
83
L2
127
128
1 f:
H1
SAM High Half
191
:
4
H2
266
f
1 1
~
4
Figure 25. Example of Split-Register Operation With Programmable Stop Points
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256-/512·blt compatibility of spllt·reglster programmable stop point
The stop-point mode is designed to be compatible with both 256~bit SAM and 512-bit SAM devices. After the
CBRS cycle Is Initiated, the stop-point mode becomes active. In the stop-point mode, and only In the stop-point
mode, the column-address bits AY7 and AY8 are internally swapped to assure compatibility (see Figure 26).
This address-bit swap applies to the column address, and it is effective for all DRAM and transfer cycles. For
example, during the split-register-transfer cycle with stop point, column-address bit AY8 is a don't care and AY7
decodes the DRAM row half for the split-register transfer. During stop-point mode; a CBR (option reset) cycle
is not recommended, because this ends the stop-point mode and restores address bits AY7 and AY8 to their
normal functions. Consistent use of CBR cycles ensures that the SMJ55161 remains In normal mode.
NONSTOP-POINT MODE
AY8.0
AY8=1
AY7.0 AY7.1 AY7.0 AY7.1
o
512 .. 512
512 .. 512
Memory Array
Memory Array
256-Bft
Data Reglltar
256-Bft
Data Regllter
o
256
255
Figure 26. DRAM·to-SAM Mapping, Nonstop·Polnt Versus Stop Point
IMPORTANT: For proper device operation, a stop-point-mode (CBRS) cycle should be initiated immediately
after the power-up initialization cycles are performed.
power up
To achieve roper device operation, an initial pause of 200 IJ.S is required after power up followed by a minimum
of eight RA cycles or eight CBR cycles to initialize the DRAM port. A full-register-transfer read cycle and two
SC cycles are required to initialize the SAM port.
After Initialization, the internal state of the SMJ55161 is as follows:
STATE AFTER INITIALIZATION
QSF
WrIte mode
Wrlte-maak register
Color register
Serial-register tap point
SAM port
Defined by the transfer cycle during Initialization
Nonpersistent mode
Undefined
Undefined
Defined by the transfer cycle during initialization
Output mode
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SGMS056-MAY1995
absolute maximum ratings over operating free-alr temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................... -1 V to 7 V
Voltage range on any pin .... . • . . . . • . . . . . • . . • . • • . . . . • . • . • . • . . • . . • . . . . . . . . . . . . • . • . . . .• -1 V to 7 V
Short-circuit output current ......•.•..•...•.•.•••.•..•.••..••.•••.•..••..•....••..•...•.••. 50 rnA
Power dissipation .•.••..•....•...................................••..•..••.•••••.•••.•.•• 1.1 W
Operating free-air temperature range, TA ..•..••.•......•......•...•........•..•... - 55°C to 125°C
Storage temperature range, Tstg •••.........•.••••......•.•.•.•.••••.•..••..•..•.. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maxlmum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values ara with respect to VSS.
recommended operating conditions
VCC
Supply voltage
VSS
Supply voltage
MIN
NOM
MAX
4.5
5
5.5
0
UNIT
V
V
High-level Input voltage
2.4
6.5
V
VIH
Low-level Input voltage (see Note 2)
-1
0.8
V
VIL
·C
Operating free-air temperature
125
-55
TA
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
*
SAM
PORT
VOH
High-level output voltage
IOH=-1 mA
VOL
Low-level output voltage
IOL=2mA
II
Input current (leakage)
VCC = 5.5 V,
VI 0 V to 5.8 V,
All other pins at 0 V to VCC
10
Output current (leakage) (see Note 3)
VCC. 5.5 V, Vo =OVtoVCC
ICC1
Operating currant §
See Note 4
Standby
ICC1A
Operating current §
!eISC) = MIN
Active
ICC2
Standby currant
All clocks = VCC
Standby
ICC2A
Standby current
ICC3
RAS-only refresh current
!e(SC) =MIN
See Note 4
Active
Standby
ICC3A
RAS-only refresh current
!e(SC)
See Note 4
ICC4
Page-mode current §
!e(P) .. MIN,
Ses Note 5
ICC4A
Page-mode current §
See Note 5
ICC5
CBRcurrent
!eISC) =MIN,
See Note 4
ICC5A
CBRcurrent
See Note 4
Icee
Data-transfer current
!e(SC) = MIN,
See Note 4
MAX
2.4
'55161-80
MIN
MAX
2.4
UNIT
V
0.4
0.4
V
:1:10
:1:10
tIA
:1:10
:1:10
tIA
165
160
mA
210
195
mA
12
12
mA
70
65
mA
165
160
mA
Active
215
195
mA
Standby
100
95
mA
Active
145
130
mA
Standby
165
160
mA
Active
210
195
Standby
180
170
mA
mA
225
200
mA
=
=MIN,
'55161-70
MIN
Active
!e(SC) =MIN
ICC6A Data-transfer current
..
For conditions shown as MINIMAX, use the appropriate value specified In the timing requirements •
§ Measured with outputs open
NOTES: 3. SE Is disabled for sa output leakage tests.
4. Measured with one address change while RAS • VIL; !e(rd),!e(W),!e(TRD) = MIN
5. Measured with one address change while CASx = VIH
*
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
6-227
SMJ55161
262144 BY 16-BIT
MULTIPaRT VIDEO RAM
SGMS0S6-MAY1995
capacitance over recommended ranges of supply voltage and operating free-air temperature,
1 MHz (see Note 6)
f
=
TVP
MAX
CilA)
Input capacitance, address Inputs
5
10
pF
CIIRC)
Input capacitance, address-strobe Inputs
8
10
pF
CIIWl
Input capacitance, write-enable Input
7
10
pF
CIISC)
Input capacitance, serial clock
8
10
pF
CIISE)
Input capacitance, serial enable
7
10
pF
CI(DSF)
Input capacitance, special function
7
10
pF
CifTRGI
Input capacitance, transfer-register Input
7
10
pF
Co/Oj
Output capacHance, SO and DQ
12
15
pF
10
12
pF
PARAMETER
MIN
Co/OSF) Output capacitance, OSF
NOTE 6: Vee = 5 V :t 0.5 V, and the bias on pins under test Is 0 V.
UNIT
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 7)
PARAMETER
TEST
CONDITIONSt
ALT.
SYMBOL
'55161-70
MIN
MAX
'55161-80
MIN
MAX
UNIT
Ia(C)
Access time from CASx
Id(RLCL) .. MAX
teAC
20
20
n8
1a(CA)
Access time from column address
Id(RLCL) .. MAX
tAA
35
40
n8
Ia(CP)
Access time from C5ASx high
tePA
40
45
ns
Ia(R)
Access time from RAS
tRAC
70
80
ns
Ia(G)
Access time of DO from fRG low
toEA
20
20
ns
Id(RLCL) .. MAX
Id(RLCL) = MAX
ta(SO)
Access time of SO from SC high
CL=30pF
IsCA
20
25
ns
Ia(SE)
Access time of SO from SE low
CL=30pF
!sEA
15
20
ns
Idls(CH)
Disable time, random output from CASx high
(see Note a)
CL=50pF
toFF
ldis(RH)
Disable time, random output from RAS high
(see Note a)
CL=50pF
ldis(G)
Disable time, random output from fRG high
(see Note a)
CL=50pF
Idls(WL)
Disable time, random output from WE low
(see Note a)
ldis(SE)
Disable time, serial output from SE high
(see Note a)
0
20
0
20
ns
0
20
0
20
n8
toEZ
0
20
0
20
ns
CL=50pF
twEz
0
20
0
20
ns
CL=30pF
!sEZ
0
15
0
20
ns
t For conditions shown as MINIMAX, use the appropriate value spacified in the timing requirements.
NOTES: 7. Switching tlmas for RAM-port output are measured with a load equivalent to 1 TTL load and 50 pF. Data-out r8ference level:
VOH /VOL" 2
Switching times for SAM-port output are measured with a load equlvalentlo 1 TTL load and 30 pF. Serial-dsta
'
out reference level: VOH I VOL" 2 Vlo.a V.
a. ldis(CH), ldis(RH)' Idls(G), Idls(WL), and ldis(SE) are specified when the outPut is no longer driven.
v/O.a v.
~1ExAs
8-22a
INSTRUMENTS
POST OFFICE sox 1443· HOUSTON. TEXAS 77251-1443
SMJ55161
262144 BY 16·BIT
MULTIPaRT VIDEO RAM
SGMS056- MAYl995
tImIng requIrements over recommended ranges of supply voltage and operatIng free-alr
temperature t
ALT.
'55161-70
SYMBOL
MIN
MAX
'55161-80
MIN
MAX
UNIT
tcCreI)
Cycle time, read
lAc
130
150
n8
tc(W)
Cycle time, write
130
150
tclrdW!
Cycle time, read-modlfy-write
175
200
na
na
tclPI
tclRDWPI
tc[fRDi
Cycle time, page-mode read, write
twc
tRMW
tpc
45
tPRMW
85
lAc
130
50
90
150
n8
Cycle time, page-mode read-modlfy-wrlte
30
10
n8
Cycle time, transfer read
na
na
tc(SCl
Cycle time, serial clock (see Note 9)
tscc
22
lwlCHI
tw(CL)
Pulse duration, CASi high
tePN
10
Pulse duration, CASx low (see Note 10)
twlRHI
twIRL)
Pulse duretion, RAS high
teAS
tRP
Pulse duration, RAS low (see Note 11)
tRAS
20
50
70
tw(WL)
Pulse duration, WE low
twp
tw[fRG)
Pulse duration, 'i'RG low
twlSCHI
tw(SCL)
Pulse duration, SC high
tsc
Pulse duration, SC low
twlGHI
Pulse duration, TRG high
tscp
typ
twIRL)P
Pulse duration, ~ low (page mode)
isu(CA)
Setup time, column address before CASx low
tASC
0
0
ns
isulSFCI
tFSC
0
0
isu/RA)
Setup time, DSF before CASi low
Setup time, row address before RAS low
tASR
0
0
isulWMRI
Setup time, WE before RAS low
0
0
isu(DORI
Setup time, DO before RAS low
twSR
tMS
na
na
na
0
0
n8
isu[fRG)
Setup time, TRG high before RAS low
0
0
na
isu(SFR)
isu(DCL)
Setup time, DSF low b8fore RAS low
ITHs
tFSR
0
0
ns
Setup time, data valid before CASx low
tDSC
0
0
ns
isu(DW!.)
Setup time; data valid before WE low
tDSW
0
0
ns
isulrdl
Setup time, read command, WE high before CASx low
tRCS
0
0
ns
isu(wCLI
Setup time, early-write command, WE low before CASx low
twcs
0
0
ns
isu(WCH)
Setup time, WE low before CASx high, write
15
Setup time, WE low before RAS high, write
20
thlCLCAl
Hold time, column address after CASx low
teAH
10
20
20
15
ns
isu(wRHI
tew!'
tRWL
tRASP
na
10000
20
10000
n8
10000
eo
eo
10000
ns
n8
10
15
na
20
8
8
20
20
ns
10
na
na
70 100000
80
10
ns
20
100000
ns
n8
ns
ns
Hold time, DSF after CASx low
15
15
ih(SFC)
teFH
Hold time, row address after RAS low
ns
10
10
th(RA)
tRAH
t liming measurements are referenced to VIL max and VIH min.
NOTES: 9. Cycle time assumes tt = 3 ns.
10. In a read-modify-write cycle,id(CLWL) and isu(WCH) must be observed. Depending on the user's transition times, this can require
additional CASx low time [tw(CL»).
.
11. In a read-modlfy-write cycle,id(RLW!.) and isu(WRH) must be observed. Depending on the user's transition times, this can require
additional RAS low time !tw(RL))'
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-229
SMJ55161
2621.44 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS058-MAY1995
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (continued) t
ALT.
SYMBOL
th(TRG)
Hold time, TRG after RAS low
th(RWM)
Hold time, write mask after RAS low
thIRDQ)
Hold time., DQ after RAS low (write-mask operation)
tMH
tRFH
tAR
trHH
tRWH
'55161·70
MAX
'55161-80
MIN
MIN
MAX
UNIT
15
15
n.
15
15
15
15
n.
10
30
15
35
n.
~ISFR)
Hold time, DSF after RAS low
th(RLCA)
Hold time, column address valid after RAS low (see Note 12)
thlCLDl
Hold time, data valid after CASx low
tDH
15
ns
th/RLDl
th(WlD)
Hold time, data valid after RAS low (see Note 12)
35
35
n.
Hold time, data valid after WE low
toHR
tDH
15
15
ns
thlCHrdl
thlRHrd)
Hold time, read, WE high after CASx high (see Note 13)
tRCH
0
ns
Hold time, read, WE high after RAS high (see Note 13)
tRRH
th(CLW)
Hold time, write, WE low after CASx low
twCH
0
0
15
0
15
ns
thlRLWl
th(WLG)
Hold time, write, WE low after RAS low (see Note 12)
twCR
Hold time, 'fAG high after WE low (see Note 14)
toEH
35
10
35
10
th(SHSQ)
Hold time, SQ valid after SC high
2
2
ns
thlRSFl
Hold time, DSF after RAS low
tsOH
tFHR
Hold time, output valid after CASx low
35
0
60
15
n.
th/CLQl
35
0
70
10
0
20
0
20
n8
ns
tDHC
I
teSH
td(RLCH)
Delay time, RAS low to CASx high
td(CHRL)
Delay time, CASx high to RAS low
teRP
tdlCLRHl
td(CLWL)
Delay time, CASx low to RAS high
tRSH
Delay time, CASx low to WE low (see Notes 16 and 17)
Delay time, RAS low to CASx low (see Note 18)
teWD
tRCD
tRAL
45
tdlRLCLl
td(CARH)
td(CACH)
Delay time, column address valid to CASx high
tdlRLWU
Delay time, RAS low to WE low (see Note 16)
teAL
tRWO
tdlCAWLl
td(CLRL)
Delay time, column address valid to WE low (see Note 16)
td(RHCL)
td(CLGH)
Delay time, CASx low to TRG high for DRAM read cycles
td(GHD)
Delay time, TRG high before data applied at DQ
I See Note 15
Delay time, column address valid to RAS high
teHR
20
35
ns
ns
ns
ns
n8
ns
50
50
20
60
ns
ns
35
40
n.
95
105
tAWD
60
65
ns
ns
Delay time, CASx low to RAS low (see Note 15)
teSR
0
0
n8
Delay time, RAS high to CASx low (see Note 15)
tRPC
0
0
20
20
ns
ns
15
15
·ns
toED
The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
Either ~(RHrd) or td(CHrd) must be satisfied for a read cycle.
Output-enabllHlontrolied write. Output remains in the high-impedance state for the entire cycle.
CBR refresh operation only
Read-modify-write operation only
TRG must disable the output buffers prior to applying data to the OQ pins.
The maximum value is specified only to assure RAS access time.
~TEXAS
INSTRUMENTS
8-230
n.
n.
40
t llming measurements are referenced to VIL max and VIH min.
NOTES: 12.
13.
14.
15.
16.
17.
18.
10
POST OFFICE SOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056- MAY1985
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (contlnued)t
ALT.
SYMBOL
tcllRLTHI
Delay time, RAS low to TRG high (see Note 19)
tclIRLSH)
Delay time, RAS low to first SC high after TRG high (see Note 20)
tcI(RLCA)
'65161-70
MIN MAX
55
Delay time, RAS low to column address valid
tATH
tRSD
tRAO
tcllGLRHI
Delay time, TRG low to RAS high
tAOH
20
tclCCLSH)
Delay time, CASx low to first SC high after TRG high (see Note 20)
toSD
tcI(SCTR)
Delay time, SC high to 'fAG high (see Notes 19 and 20)
lTSL
fdITHRH)
Delay time, TRG high to RAS high (see 19)
tclrrHRL)
70
15
35
'65161-80
MIN MAX
SO
SO
15
UNIT
ns
ns
40
ns
ns
5
-10
ns
lTRD
20
5
-10
20
25
Delay time, TRG high to RAS low (see Note 21)
lTRP
50
60
ns
tclrrHSC)
Delay time, TRG high to SC high (see Note 19)
lTSD
15
20
ns
tcI(RHMS)
Delay time, RAS high to last (most significant) rising edge of SC before
boundary switch during spilt-register-transfer read cycles
20
20
ns
tcI(CLTH)
Delay time, CASx low to 'fAG high In real-time-transfer read cycles
15
ns
tcI(CASH)
Delay time, column address to first SC In early-load-trensfer read cycles
lOTH
tASD
15
25
30
ns
tcI(CAGH)
Delay time, column address to TRG high in reaI-time-transfer read
cycles
tATH
20
20
ns
tcI(DCL)
Delay time, data to CASx low
tDZC
0
0
ns
tcllDGLI
Delay time, data to TRG low
tDZO
0
0
ns
tcI(MSRL)
Delay time, last (most significant) rising edge of SC to RAS low before
boundary switch during split-register-transfer read cycles
20
20
ns
tcI(SCQSF)
Delay time, last (127 or 255) rising edge of SC to QSF switching at the
boundary during split-reglster-transfer read cycles (see Note 22) .
tsQD
25
30
ns
tcI(CLQSF)
Delay time, CASx low to QSF switching In transfer-read cycles
(see Note 22)
toQD
30
35
ns
tcI(GHQSF)
Delay time, TRG high to QSF switching in transfer-read cycles
(see Note 22)
lTQD
25
30
ns
tcI(RLQSF)
Delay time, RAS low to QSF SWitching in transfer-read cycles
(see Note 22)
tRQD
70
75
ns
ns
ns
8
Refresh time interval, memory
ms
8
irt(MA)
tREF
ns
Transition time
3
50
3
50
tt
IT
t llming measurements are referenced to VIL max and VIH mm.
NOTES: 19. Real-time-load transfer read or late-load-transfer read cycle only
20. Early-load-transfer read cycle only
21. Fuli-register-(read) transfer cycles only
22. Switching times for QSF outPut are measured with a load equivalent to 1 TTL load and 30 pF, and outPut reference level Is
VOH /VOL =2 V/O.8V.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-231
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056-MAY1995
PARAMETER MEASUREMENT INFORMATION
~
I ~
I I...
RAS
~~
---s'N.r
I
CASx
W
I
Y:...+I I
--+I I I
I I I
~(CL) ~
"I
I~
I
I
I
~I
I
I
!4--
tw(RH)
---.I\~---
I'f-IcI(CLRH}
IcI(RLCL)
--+I
I'"
illllt-1cI(CHRL)
III
I I i /f
_~
I i ~
I I Ir~(cH)~ '--~I I 1
II I I
14 I 1 IcI(CARH} ----+i I I I
Ih(RLCA)
I 1 1I
1I I I
I 1
j4 i I
IcI(CACH}
I I ~I I
I I 14
~l Ih(CLCA) I I
I
i l l
I I"
I I
IcI(RLCA) jIIII
th(RA)
~
~
IcI(RLCH}
tt -+t I
-+t
~~
~
j\~"
l+-
I I... I"
I I
leu(RA) -+I IIIiIt
I
II I
I
--+I
L7<::1~~I~",,~~~~~~~~
leu CA)
AO-AS
leu(TRG)
+II
\4tI
I I I
I 1I
~I
I'"
I
II
II
IcI(GLRH}
"
TR.~~~~~~
,i~~
~ I
I th(RHrd) 14
"
~I
lleu(rd)
I
I
I
I
~i
I
IcI(DGL)
I'"
_---,l~
DOG-DQ1S
Oats In)
1 ~I
I
I
I
I
I
I
I
I
I
I I
I ~
I'"
1s(R)
I'"
I~
I
II
W E lI lI
I"
IcII(CH)
a
II II...
I
.,-
~.
I
--.JI+I IcIla(G) -+i
I
jllll-1s(G) ,.,
(
Oats Out
)>------
Is(C)---+l
Is(CA)
~I
~I
Figure 27. Read-Cycle Timing With CASx-Controlied Output
~lExAs
INSTRUMENTS
8-232
POST OFFICE BOX 1443 • HOUSTON, lEXAS n251-1443
SMJ55161
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SGMS058- MAY1995
PARAMETER MEA.SUREMENT INFORMATION
I..
I ~
I I11III
~~
l\l
RAS
I
iii
II I
tau(RA)
~
ii
./...
I+-
I
-+III~I
W.
I r-II-r-----"':II
. y~
I I
~
.l\
I
~~
I I11II I
I
II
Ih(RLCA)
IcI(CARH)
-W-J I
I
1111
II
-+i
(CH)
'----
I I
II
I+H-I IcI(CACH) -+i I
I I
I
~~~
~ iC~lum~ ~
r~III
tau(SFR)
-+t
i:i:
Ih(SFR) I
~I:
I
f!t
;
I
tau(TRG)
+I
I I
I
j.- IcI(CLGH) ++II
II
I
I I I
I'"
I
.1
II
xxxxJ~ ~1IIIII-:::r-~(T1G)11
'i'RG~II~
II
I to
I
"U(rd)~ I
-----'-'oL.a..J
~
W
E lI lI
IcI(DGL)
DQO-DQ15
J\"""---
:+- ~(CL) ~l I I
iIIIIIj IcI(CHRL)
Ih(RA)~
DSF
VI
I r4-~(RH)~
It --.I ~
I+-IcI(CLRH) l----.l I
I4-IcI(RLCL) -+I
I I
IcI(RLCA)
AO-AS
I
I
I
I
I
II
I I
-+!
~
'
.1
~
.1
I
IcI(RLCH)
----s~!
CASx
'c(rcI)
I'"
.1
Data In )
I
I
!!
I
I'"
I~
-+i I ~ Ih(RHrd)
I"'I~~
I
th(CHrd)
li~
I.
I
1+ ta(G) +I
(
ta(CA)
ta(R)
I~
I
I+- ta(C)
I'"
.
IcI(GLRH)
I 1llill-1cI18(G)-+I
~ 1c118(RH) ~
Data Out
)>------
---+l
.:
'-1
Figure 28. Read·Cycle Timing With RAS·Controlled Output
.-!II
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-233
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056 - MAY1995
PARAMETER MEASUREMENT INFORMATION
~
----.i'
~
14
r-t
!.~ IT
tt --'I
I
CASx
~
14
-.I
14-
I
lcI(RLCL)
lcI(CHRL)
y~
I
lcI(CLRH)
~
14III
-.I
l1li1
I
.,
lcI(RLCA) I
r
I
~'I
~
I
I j4-f-lcI(CHRL)
~
¥!.....L-Iw(CH)
I r
-J'--
i
!.+
,
tsu(CA)
J4
Iw(RH)
! )010-+-1- - -......
Iw(CL)
N --.j
,
~ ~ ~ It
lcI(RLCH)
I I
I 14-- th(RLCA)
lh(RA)~
AO-AS
L
~
~
1w(RL)
-I
I I
I
I
~I
L
. . lcI(CACH)
~ th(CLCA)
~~1.~.L.,,~~
~
~~umn_
tsu(SFR) -.I
!
lh(SFR)
j4t
-+I I I tsu(SFC)
14-- lh(RSF) ----.I
t1 rI
I
I
I
I
I I. ~I ~
DSF~II~II~
I I
+-I 14-
I I
th(TRG)
I
I
I
tsU(TmtRG)-.lI4t~1
I .
.
-
I I
I I
I I
TRG
tsu(WMR)
-.I
H
II ~
14
II
I
I
I
I
lh(RWM)+-+-i 14-
~""\
WE
~
'1 II
I
~W
~
~
th(RDQ)~ 14I L
ft1'I1\.
~
tsu(WRH)
~
th(RLW)
i4--lh(CLD)
~
~
th(CLW)
!4i tsu (WCL)
~ I:
1w(WL)
I
~ Mtsu(DCL)
tsU(DQR)-':
DQO-DQ16
I
tsu(WCH)
I
_ _
----.!
I
I
~ Il"mlmom~~I"I7'!7O~~1"I7'!7017'm7
lh(RLD)
3
_
Figure 29. Early-Wrlte-Cycle nmlng
Table 4. Early-Wrlte-Cycle State Table
STATE
CYCLE
1
2
3
Write operation (nonmasked)
H
Don't care
Valid data
Wri1a operation with nonpersistent write-par-bit
L
Write mask
Valid data
Wri1a operation with parsistent write-par-bit
L
Don't care
Valid data
~1ExAs
INSTRUMENTS
8-234
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TRG
~"
.
-+j 14-1- tsuCTRG)
1, ,
i.ft-
-+i
I
,.
n
~
\U(WMR)I
I.:
tsu(WRH)·
tsu(WCH)
lJ1(CLW)
~
~
,
,
.,
"
.~i
I
lJ1rLW)
~'I:
th(WLG)~: ~
,~
~
tw(WL)
, I ~-----.......~~~~~~~~~
tsu(DWL)
tsu(DQR)..,
'I~ i1~
1
11
th(RDQ)
lJ1(WLD)
-+I
I
.1
,
"41
DQO-DQ15
'4
,
1
1
~
'-+j ~
,4
'
'4
"
j+-
1 _I
I
!
1.+,
th(RWM)
WE
fcI(GHD)
I
W7V\~.~J.
~
th(RLD)
~
1
3
,
Figure 30. Late-Wrlte-Cycle TIming (Output-Enable-Controlled Write)
Table 5. Late-Write-Cycle State Table
STATE
CYCLE
1
2
3
Don't care
Vsliddata
Write operation with nonpersistent wrlte-per-blt
H
L
Write mask
Valid data
Write operation with persistent write-per-blt
L
Don't care
Vsliddata
Write operation (nonmasked)
~ThxAs
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PARAMETER MEASUREMENT INFORMATION
14
_ _......1 14
'N.
_J
14
It......., i+
RAS
~
CA§
tc(W)
~
K14-
1
tci(RLCL)
tci(CLRH}
tw(RH}
1
-+l
I+- It
-.1"--1
1
I
_I ~ tci(CHRL) -+I
L
N4
11
II 1_
1h(RA) ~ ~
1
I 1
1 ~1 1
-+I
tci(CHRL)
y~
~I
tci(RLCH}
14
~I
~I
tw(RL)
~.vt
1~
tw(CL)
1
11
.
1
:I
1
.
~
tw(CH}---.l
. -. ~:+-~
. . . *'"
'-(RA)~~~
_I
-.j I4+-
11
11
teu(SFR)
I 1 14
th(RSF)
1
1
1
teu(SFC)
--.I
1
1
1
Ih(S.FR)~"'" i 1:" .~.
1
OSF
~
teu(TRG)
TRG
-+\
i : ~'IoQ~ . .L.I-+I__&:.A&.~~&:.A&.~~~~~&:.A&.~~&:.A&.~
I I
i4" I+-
~
....
1
~l:
l...!.
teu(WMR) - - r""1
14
1
14
1
_I
1
:
1
14
Ih~ I+1
WE
OQO-OQ15
~
11
1
th(TRG)
11
11
11
11
teu(WRH}
I 11
:+i ~
4
I~II
===
1
~I
teu(WCH}
~I
th(RLW)
.
th(CLW)
1
1
~I
.:
1
teu(WCL)
tw(WL)
_
11
1
-+I
1
I
1
~
~ teu(DCL)
10IIII
Ih(CLO) ~
th(RLO)
.:
Write Maak See Note A
~
t Load-wrlte-mask-reglster cycle puts the device Into the persistent write-per-blt mode.
Figure 31. Load-Wrlte-Mask-Reglster-Cycle nmlng(Early-Wrlte Load)
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PARAMETER MEASUREMENT INFORMATION
1II1I
_ _--.;1 1II1I
N
I~
mr ::
1II1I
tcI(RLCL)
I I
th(RA)
.1
~
tcI(RLCH)
~~(CHRL)
, I :+-
.1
I
tc(W)
twIRL)
itH
"----
tw(RH) --.:
tcI(CHRL) ---.:
~ I+- tt
.iy{lr-;-fl-----_~\....
1
tw(CL)
I
/I
~ I+-
1
tcI(CLRH)
-+j
NI~
yi
I ~
I ~ II
.
tw(CH)
·1 .
AO-AS
, j+-
-+I ~
lh{sFR}rr1 ~
teu(SFR)
DSF
th(RSF)
,--+I
-+I I4t teu(SFC)
lllll
,
,
,
~II~'-~
~!!
! 1II1I
~
-+I
1
li
:
1II1I
I
I
,
1II1I
~ tcI(GHD) ~
WIIIII
teurNMR)-+!
,
~
_
teurNRH)!.1
I11III+ teu(TRG)
I I I
rL
!
I
1II1I
teurNCH)
th(CLW)
I
th~RLW)
1II1II
~lh(RWM)~
I
I
DQO-DQ15
,
if
1
teU(DWL)+!
I
I
I
I
II
.
I
I
II
.1
~~
twrNL)
~
!+-- thrNLD) ---+I
I
.1
lh(RLD)
~
.,
.1
I
.1
lhrNLG) II:
Write Maakt
~
t l.oad-wrlte-mask-reglster cycle puts the device into the parsistent write-par-bit mode.
FIgure 32. Load-Write-Mask-Register-Cycle TimIng (late-Write Load)
:II~
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PARAMETER MEASUREMENT INFORMATION
Table 6. Read-Wrlte-/Read-Modlfy-Wrlte-Cycle State Table
STATE
CYCLE
1
2
3
Write operation (nonmasked)
H
Write operation with nonpersistent write-par-bit
L
Don't care
Write mask
V8l1ddata
Valid data
Write operation with perslstant wrlte-per-bit
L
Don't care
Valid data
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PARAMETER MEASUREMENT INFORMATION
_14
;;. !rt
I'
I,
1
,
,
II
I I
'
I1
II
1
I1
lIT1
,
ItI(RHrd)
.1 th(TRG)
tau(TRG) ~I,
'i'RO'tI"
I,
_'
-+1 ~taU(WMR) I I
14'
tau(rd) 1 . 1
WE
XX?"
1,
u ,,
tcI(DGL)
I ,'" F'
,...
141
DQODQ16
------~
Dats In
I,I',
'I
...
1
I
'
1
-+I
~ ta(CA)
~ta(G)
*-
-+I
r-.;
"
(...~. B) ,
, .'
1
,
I
, ".-_....,_ __
I
I!
'
1
i
ta(C)
1
,
,4
,
I+--
,
I
0,
'
I
-+! p!+1-
' -+I,
tcl18(WL)
tclI8(RH)~
I
I.- tcl18(G)
DatsOut
~ tcI{DCL) ---+I
NOTES: A Access time is ta(CPI or ta(CA) dependent.
.
B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
C. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of OSF Is selected on the falling edge of RAS and CASi to select the desired
write mode (normal. block write. etc.).
FIgure 34. Enhanced-Page-Mode Read-Cycle TImIng
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PARAMETER MEASUREMENT INFORMATION
Nrl'llll------------tw(RL)P---------~~~~
, 14
~
tct(RLCH)
, ......1 - - - - tct(RLCL) ---.~,
tc(p)
---..,-.~, tw(RH)~
---+I
'
I11III-- tw(CH) ~I I11III-
I:+-
-.I !IIIII+ t c t ( C H R L ) I......-.-..-- tw(CL)
-ASx-,'VVV
tau(RA)
,
14- tct(RLCA)
+/ I+t
, ,
--+l
tau(CA)
i4-1h(RA) --.t
',
r-"
I
I
'"
tct(RSF) , I
,-,
I
,
ltJ(CLC~
I
tct(CLRH)
!
tct(CHRL)
'\.
-.I
I ,
I
I
,
~ tct(CACH) --+i
,
':;~::._ ~ ~m" ~~ ~~ ~
-+\, ii+tI~
tau(SFR)
, ,
r-ltJ(SFR) -?j
~u
~ ,~,
,
~,
~)i(
,j"', •
.:~ : ~
tau(TRG)
j+- th{TRG) -+!
"
fRGW!
r \
~ ~~U(WMR)
'I'"I "
I .'1 ,
·~(SFC)
'
'I
.'
th(SFC)
I
., .~~Fq
I
_
,-
:::
I11III- tau(WCH)
,
SetNowA
+I
tau(WCH)
:
=+1_
I+:
,
1 : :
liI(RWM) -+\
:...- tw(WL) -+l
~ ta~
Wf~ . . 3;~II~~
~ I11III-+ tau(DQR)
~ taul(D~L) (see Note B)
r
"
,
,
.
tau(DCL)','
,
(see Note B)
,'"
, .,
I+-ltJ(RDQ) ~
,
,'"
,''''
=5~
I'
4)0(
JIIIII
.,
,
.,
th(RLD)
ltJ(CLD) (S88 Note B)
th(WLD) (see Note B)
.,
5
~"..=~
5~
NOTES: A. Referenced to the first falling edge of CASx or the failing edge of WE, whichever occurs later
B. A read cycle or a reed-modify-write cycle can be Intermixed with write cycles, observing reed and reed-modlfy-wrlte timing
epeclficatlons. To assure page-mode cycle time, TRG must remain high throughout the entire page-mode operation If the late write
feature Is used. I1the early wrlte-cycle timing Is used, the state ofTRG is a don't care after the minimum period th(TRG) from the failing
edgeOfRAs.
Figure 35. Enhanced-Page-Mode Write-Cycle Timing
Table 7. Enhanced-Page-Mode Write-Cycle State Table
STATE
CYCLE
1
2
3
4
5
Write operation (nonmasked)
L
L
H
Don't care
Valid date
Write operation with nonpersistent wrlte-per-bit
L
L
L
Write mask
Valid data
Write operation with perslstant write-per-bit
L
L
L
Don't care
Valid data
Load-write mask on eitherthe first falling edge of CASx orthe
Write mask
H
L
H
Don't care
falling edge of WE, whichever occurs later. t
Load-write-mask-regIster cycIe puta the device In the persistent write-per-bit mode. Column eddress at the falUn g edge of CASx is a don't care
during this cycle.
~1ExAs
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PARAMETER MEASUREMENT INFORMATION
-r{
~
~
Iw(RL)P
L'"
~I
---J. ~ 1w(R1
IcI(RLCH)
,4
tc(RDWP) I
IcI(RLCL)
I
'4
Iw(CL).1
~ IcI(CHRL)
i+--1cI(CLRH)
I~I
Iw(CH)
IcI(CHRL) -i'lI--+I
I
,
~J.-~"'~=~:::;;~~r:'
~ 14-1h(RA)
I
~
AO-AS
"
I~ I
I
f4t
~I 1cI(I:I~C~
!"'t tSu(CA)
....
t.u(RA)
I I'll
~ th(R~o~~mn
u 141I
I:
Jm<::
1
IcI(CARH)
I
~,
COI+~
,
~I
I
~
I~ .~
--01 i"I"''''''' I r'
'T~ ~ I II
~ :7Fq~:: :::~~
I
(SFR)
DSF
I ,
I I
.1 Ih(CLCA) I ,~(?ACH)
,~I
I ,
,I ,
I
I I I
I I~ I
lh(TRG)'4 I
-+I :.'1 +_
I t.U(rd)
~
, I'
I'" !
I
II
--.I "
~: I I
-+i
I,
I
Yi
I
I I
I ,
I ,
I I
~.14t
II I
j+-1h(RWM} I
~
.
I
I I,
tau(WCH)
I 1w(WL) 14 ,
~ itau(WMR)
I
I ,
I j+-1cI(CLWL)
,4 I I
IcI(CAWL)
I
I IcI(RLWL)
~I
~: I 14
~I IcI(CLGH)
,
I
"U(TRG)N'~
~I;!W(TRG)
W 'I
I
~~~~~~----~~~~I,
3
I I II j4- t.CC) Cse',NOt' A) , I
,
I~ ,,~I t.CCA) Cse, Not, A) , I
-+I
tau(DQR)
, 1
I th(WLD) I~
I
I
'4-
t++t-1cI(DCL)
-.II+- th(RDQ)
1
I
t.u WLr+! I+-
,
I
-t.I
I I
I ,
j4- taCG) ca"INot'
~
tau(WCH)-+l1+I
i4+-1cI(DCL)
I
I
1-+1
'
I'
IcI(CLGH) : _
'I
I,
,
t.u(WRH) ~
I
i
1
*'
7'-
J
,
I
IF."-j- - - ; - - - - -
Ilj"c--I'l
I
I4-Iw(TRG)
I II
I
;,-~--~----~i~~~~
,
I \.
-+j 14+ t.uCDWL)
I
I
I
,
14
.1
IcI(GHD) 1
taCCP) Ca" N~t, A)
.
1
I~
i-----,
I I
}OOOOO++-<
DQO-DQI5
I
Ih(WLD)
~I ,
II
-J.--.I
I+-
1 IcI(GHD)
II -.t
IcIla(G)
talR) Ca.. Not, A)
-+II+- ta(C) C- Note A)
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are
not violated.
IcI(DGL)
I~
-+I I+-
~I
Figure 36. Enhanced-Page-Mode Read-Modlfy-Wrlte-Cycle Timing
Table 8. Enhanced-Page-Mode Read-Modify-Wrlte-Cycle State Table
STATE
CYCLE
1
2
3
4
5
Write operetlon Cnonmask,d)
L
L
H
Don't care
Valid data
Write operation with nonpersistent write-per-bit
L
L
L
Write mask
Valid data
Write operetion with persistent write-per-bit
L
L
L
Don't care
Valid data
Load write-mask register on either the first falling edge of
Write mask
H
Don't care
L
H
CASx or the falling edge of WE. whichever occurs later.t
Loed write mask register cycle puts the device In the persistent write per bit mode. Column address at the failing edge of CASX is a don't care
during this cycle.
- - -
- -
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tw(RH)~
'4
RAi
.1 I
tw(RL)P
~
~ i L.:
"'(Rl.Cll
__
.... i4F tcI(CHRL)
I
CASx
~ tcI(RLCA) -+I
I I14
taU(RA)
AD-AS
1
111===~~
I
I 14
_
COlu~n
tcI(RLCH) Ttau(CA) 14
.1
-+J j.ll..o
I I ~ 1h(RA) +!
~lth(RL~
I: :'.
~
I
. . Row
_
I
.:
I
1
1
+-It
I
I
I
I
~==r
I;~Iumn-~
~
~
:
4.
I+- tcI(CACH) ~ 1
Itt(CLCA)
rf'-i
~
I
1
,1.1
( 4 - - - - tc(p)
~
I
1
I
1
~~...-~
DSFl~
I tau(TRO)
II
TRG
-+:,4 i4tI
I I
WE
XfT
Y
tcI(DGL)
~:5
I
11
II
I
1 i++III 1
I
th(CLW)
1;-----
1 ~~--~~----~--------_r~~--J
1 I
1
I
I
1
tau(WMRl
tau(rd)
1
I
I
.1
I
:\J:4
I
tw(WL)
I
I
1 ~-----------
~ -.I'+- ta(C) ~---r---~oI-l
I
14- ta(CA)
I
I
.11 tcII8(WL) 1 14
I+- taCO) ~
14
1
.11
14 1
tatA)
( - N"ote B)
{
I
I
1 See Note A
II 114
_ _ _",I
Data In
1
I
.y
--..;!I.
I
.'
;
\
I,
.1
I
Itt(CLD)
I!+-.t- tau(DCL) I
~
t
J
~
Data Out
K
Data In
)-.- - - - - -
I+-"- tcI(DCL) ~
NOTES: A. Output can go from the high-impedance etate to an invalid-data state prior to the specified accesa time.
B. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF Is selected on the falling edge of RAS and CASx to select the desired
write mode (norma', block write, etc.).
Figure 37. Enhanced-Page-Mode Read-/Wrlte-Cycle nmlng
~TEXAS
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PARAMETER MEASUREMENT INFORMATION
~
_ _ _I
~
I~
~I
I~
It --.II j+-
rr
I_!+- tcs(RLCL)
CASx~JJ
1
~
if!
I tI'"
tcl(~
~
.1
twIRL)
~ i+-- tw(RH) ---..!I
tcl(RLCH)
tcl(CLRH)
-.!
N~
tw(CL)
~I
.1 ~ 14- It
I .11
I
~
:+r
tcl(CHRL)
I
I
--+I
iJ,1
I f
~I
I
I
I I ~ lh(RA)
I 1 1
1 I
-+I ~ftlu(RA)
1 I
I
1
1
1
tw(CH)
~
--~~
.._.. ~Jl4~
I I~
lh(RSF) I~
-+I!4+ ftlu(SFC)
1 1
~f6..lh(SFR)11
._~
1
1
~IIWII~
ftlu(SFR)
+'1 I4t
~~5 ~","___Va_I_ld_co_lo_r_lnp_u_t_ _J~
FIgure 38. Load-Color-Reglster-Cycle TImIng (Early-WrIte Load)
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PARAMETER MEASUREMENT INFORMATION
,
,4
tc(W)
, 1l1li
--~N
RAS
, '-..
~ I I~
It ~
~I
IcI(C~
:
r-
i4-1cI(RLCL)
"-
..,...,
IcI(RLCH)
I
IcI(CLRH)
-.I
'N,L,..
tw(CL)
.11
, 14-- th(RSF) 1
1
1 1
1-1
t
lIT
,
L
f i...- tw(RH) ~1
-+t I+- It
~
1
!+t-1cI(CHRL)-.!
' I"
,
I,
1
1
1
1
,
I
i'-tw(CH)
.1
=-~~
AO-AS
iIIIIt
+--1+01 !+-
teu(SFR) ~
ltt(SFR)
~
1 1l1li
IIIIIt
.1
ih(SFC)
teu(SFC)
-liWiiV
i _
-+l
Wl! ! ----+,I.. I..
II1II+
teu(rRG)
,
TAG
"l1li.
-+(
I
WE
~
IIIIIt teu(WMR)
!
I N~
'"
teu(WCH)
·11 .1 ~
.,
ltt(RLW)
,
1
"l1li
,
DQO-DQ15
,
I
1
ih(CLW)teU(WRH)
I..
I4t-t-IcI(GHD)
th(WLG)
.1
1
1
1
1
I
.1
~~
'-twll
~ iIIIIt teu(DWL)
,I
I+--ltt(WLD) --.I
'lltt(RLD)
~
J.
~
..
Valid Color Input
.1
'Vj
I~
:
lsu(WRH)
lh(WLG)
I
.
11
.:
-T--+'
1
1
.1
I
1
1 N~lw(WL)~mo.=-~~~~'1f:?
+i ~ lsu(DQR)
1
..t.I
~ th(RDQ) :
1 141
DQO-DQ15
lsu(WCH)
I~
I~
.11
th(CLW)
th(RLW)
lsu(WMR)
1
th(RWM) 1
~
~
I-+l
r
I
1 1!'------~IoQQ~~~""""~"""".......
I+- lsU(DWL)
11
I+-- th(WLD) -+I
th(RLD)
.1
~~~r
1 ~~~~~~~~~
~3_
Figure 41. Block-Wrlte-Cycle TIming (Late Write)
Table 10. Block-Write-Cycle State Table
STATE
CYCLE
1
H
L
L
Block-write operation (non masked)
Block-write operation with nonpersistent wrlte-per-blt
Block-write operation with persistent write-per-blt
Write-mask date 0: I/O write disable
1: I/O write enable
Column-mask data DOI- DQI + 3 0: column-write disable
0, 4, 8, 12) 1: column-write enable
o..
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POST OFF1CE BOX 1443 • HOUSTON. TEXAS 77251-1443
2
3
Don'tcara
Column mask
Write mask
Column mask
Don't care
Column mask
Example:
DOO - column 0 (address AI .. 0, AD .. 0)
DOl - column 1 (address AI =0, AD" 1)
D02 - column 2 (address AI = I, AD = 0)
D03 - column 3 (address AI .. I, AD " 1)
SMJ55161
262144 BY 16·BIT
MULTIPaRT VIDEO RAM
SGMS056 - MAY 1995
PARAMETER MEASUREMENT INFORMATION
14
AD
---rt
--.!
CASx
'~(RLCH)
I ...
I 14
~I
~II
zg
I..-IcI(RLCA)
I
1 4
I
th(RA)
~ ~ tau(RA)
M-A8
~
_
1
...
I tau(SFR)
1
,
~!
)<)<'W.II
TRG
W
II \
114+
II
lh(RWM)
II
1
I
I
1
I 1
1
1
tau(SFC)
W
,
.::
:
14\1
I I I
:41 :
tau(WMR)
..:
WE~::'
.1
.,
~!:
tau(DQR)
: 1+
th(RDQ)
~
I
=5~
14
1 I
IcI(CAR~)
,
1
I+- ttJ(SFC)I ---+I
I
1
~I
I
1 1
14--+1- tau(SFC)
1
bwJ.
~
I
'I
See Now A
:
tau(WCH)
i+-
-.:
:
tau(WCH)
,
.,
14
tw(WL)
tau(WRH)
"I
I4t- th(WLD) (e. . Note A) -+I
~ tau(DCL) (eee Note A) 1
ttJ(CLD) (eee Note A)
,
--1
!A1 lh(RLD)
~
2
I
~~
Itall(DWL) (e. . Now A)-+I ~ I ,~
-+I I+t
i
1
tau{rRG)
1 :1 1:4
I
.1
j+- IcI(CACH) --.:
ttJ(CLCA)
I
, j+- th(SFC) -+I
!+-lh(TRG)
-+I
T\I'---~/
I
I
1 .1
1.1
j++i-II
I
!.-!.,
H
j+f-t
I
I 14
th(RLCA) I
,-4
I
.~ :BI~_~~reee: ~ -:Bloc~~re~ ~I
1 1
-+i
DSF
--I+-+l
.1,
1 14
ttJ(SFR)
r
'4
N'
-+I
tau(CA)
l+-
......
----.!
IcI(CHRL)
,~
I....
L
...
... (P)
po
tw(RH)-!+-+j
I
tw(CH) -+i j+- IcI(C~H) ~
I
.11 , tw(CL)
1 I IcI(CHRL)
I
.1
hi
"Q
IcI(RLCL)
.1
tw(RL)P
~
3
~3~
NOTES: A. Referenced to the first failing edge of CASx or the falling edge of WE, whichever occurs later
B. To assure page-mode cycle time, 'fAG must remain high throughout the entire page-mode operation if the late-write feature Is used.
Ifthe early-write cycle timing Is used, the state ofTRG is a don' care after the minimum period ih(TRG) from the failing edge of RAS.
Figure 42. Enhanced-Page-Mode Block-Wrlte-Cycle Timing
Table 11. Enhanced-Page-Mode Block-Write-Cycle State Table
STATE
CYCLE
-.
1
2
3
Block-write operation (nonmasked)
H
Oon'care
Column mask
Block-write operation with nonpersistent write-per-bit
L
Wr~emask
Column mask
Block-write operation with persistent write-per-bit
L
Don' care
Column mask
0: VO write disable
1: VO write enable
Column-mask data OOi - DOi + 3
0: column-write disable
0, 4, 8, 12) 1: column-write enable
Write-mask data
o•
Example:
DOO - column 0
D01 - column 1
D02 - column 2
003 - column 3
(address A1 = 0, AO .. 0)
(address A1 = 0, AO = 1)
(address A 1 = 1, AO 0)
(address A1 1, AO 1)
=
=
=
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PARAMETER MEASUREMENT INFORMATION
D Q O - .
D Q 1 5 , .
Figure 43. RAS-Only Refresh-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
I~
tc(rd) -------~.,
1+--1w(RH)
;T .1
---'!~
tcl
"I'7n'r'ft"l'"""r'2!k-(C_LR_L)",,\
CASX _ _
1
~ 1"'~I----Iw(RL) ----I.~I
I"
•
\l
VI
N
I I
tcI(RHCL)
'Ir--------
-.1 I+-
It
I+- tcI(RLCH) ~
V
II
I I
I+- tcI(CHRL) ---+I
I
I I
leu(RA) -+II1..1----1.~1 1!'iIII~I--.....'l-1~~~'r'ft"l'"""~~ I
I I
~
M-M
iYYYYYYYYYYYYYV
~~i__~_~~
-
I I
141
..f -....*'-
leu(SFR) -401~f-~.1
tJ,(RA)
tJ,(SFR)
... ~:,:~
'OOO-OQ15
Figure 44. CBR-Refresh-Cycle Timing
Table 12. CBR-Cycle State Table
STATE
CYCLE
1
2
Don't care
L
3
H
Don't care
H
H
Stop address
H
L
CBR refresh with option reset
CBR refresh with no reset
CBR refresh with stop-point set and no reset
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PARAMETER MEASUREMENT INFORMATION
r+- Memory Reed Cycle
+
I+---- fc(rd)
I
I~
tw(RH)
~I~
Retrash Cycle
~I
I~
~I
~ }f~~N ~V
!_ I~ ~
;#rr
~ I~ ~IIi'~
III ! II !
II
J.~ I ~lh(CLCA)
~ ~
-+I 14I I
I
I I
I I
II I
I
1 1! + r i + teu(CA)
th(RA)
th(RA)
-+j rtC teu(SFR)
I II
I
.1
I
I I
"I
~ lh(RHrd)
I I I
'
-+I
I
th(RA)
I
I I
I
W-teU(RA)
I
~I
I II'"
I I
~I
I
th(RA)
I
'
,
'
~»<~*mm~
-+: Hi
-+j:;t=
I
I I
I
I
I I
:,U(SFR)
I
I
teu(SFR)
~I;._I: ~~I;.
.J -+i !4tr ~h{TRG)
I II
I 11
teu(rd) ~
I I I
~ )4-1- teu(WMR)
'T I\.~
~
~
~
IcI(GLRH~
I
I
II II
I
I
-+:
I I
IcllafCH) ~
~ teu(WMR)
I'
idif l~~~....~\
II
}j
I I
I
-+! ~ teu(WMR)
I
~~
.~ .~~ • fitlIli
---<{
OstaOut
1'1
I
~~
)-
Figure 45. Hldden-Refresh-Cycle Timing
Table 13. Hldden-Refresh-Cycle State Table
STATE
CYCLE
CBR refresh with option reset
CBR refresh with no reset
CBR refresh with stop-point set and no option reset
1
2
3
Don't care
Don't care
L
H
H
H
Stop address
H
L
~1ExAs
8-250
!I ~
l8l§W< :~
AO-Aa
14
taU(SFR)
1
i
1 1
---.I N--J ~
r
tcI(RLCH)
1 1
I- j4- tci(RLCA)
-----tctla(CH)
1
DQO-DQ15
Va_lkI_O_utp_ut_ _ _
--~~If- tctla(G)
1
.
4.
1
\"--___--'1
TRG
Figure 2. DRAM Read Cycle With CA'S-ControUed Output
\~----------------------.....,/
\ _____/1
~
I
\~
____/
I
1
AD-"~ +mn ~ ~mn ~
talC)
1
1
1
I..
I
I..
..:
1...---+1-·
·
..1
ta(CA) --1011..
DQO-DQ15
-----------«
.. I
.. I
ta(CP)
ta(CA)
I..
..II
ta(C)
I..
"I I
1
I.. 1
I
Itt(CLQ)
Valid Output
XI'!'--Va-II-dO-utp-ut-""}-
\~---------------------------~/
Figure 3. DRAM Page-Read Cycle With Extended Output
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byte-write operation
Byte-write operations can be applied In DRAM-write cycles, block-write cycles, load-write-mask-reglster cycles,
and load-color-register cycles. Holding either or both WEL and WEU low selects the write mode. In normal write
cycles, WEL enables data to be written to the lower byte (OQO-OQ7). and WEU enables data to be written to
the upper byte (OQS-OQ15). ~or early-write ~s, one WEx is brought low before CAS falls. The other WEi
can be brought low before CA falls or after CAS falls. The data Is strobed in with data setup and hold times .
for OQO-OQ15 referenced to CAS (see Figure 4).
\~--------------~/
1'
~~i_____________
I I
WELt
\
~.
____________I I
/
I~I------------------J
I I
~.\\\\
lau(DCL) --!:4-4--'---'---~~I
I
141
..----~~I-- lh(CLD)
I
DQO-DQ1B
~
I
I
Yalldlnput
t Either WEi] or WEL can be brought low prior to CAS to Initiate an early-write cycle.
Figure 4. Example of an Early-Write Cycle
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byte-write operation (continued)
For late-write ~d-modify-write cycles, WEL and WEU are both held high before CAS falls. After CAS falls,
either or both WEL and WEU are brought low to select the corresponding byte or bytes to be written. Data is
strobed in by either or both WEL and WEU with data setup and hold times for 000-0015 referenced to
whichever WEx falls earlier (see Figure 5).
\~----------------~I
\~--------------I
f\___ 1
--.J
ieu(DWL)
I I
I I
I I
I
--1144-----~~1 I
I
I
I
I
DQO-DQ15~
\
I
..1--
1414------,~
ValId Input
th(WLD)
~
Figure 5. Example of a late-Write Cycle
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write-par-bit
The write-per-bit feature allows masking any combination of the 16 OQs on any writ~le. The write-per-bit
operation Is invoked when either WEL or WEU are held low on the failing edge of RAS. Assertion of either
IndMduai WEx allows e~ry of the entire 16-bit mask on OQO-OQ15. Byte control of the mask Input Is not
allowed. If both WEL and EU are held high on the falling edge of RAS. the write operation is performed without
any masking. The SMJ55166 offers two write-per-bit modes: nonpersistent write-per-bit and persistent
wrlte-per-bit.
nonpersistent wrlte-per-blt
When either or both WEI: and WEU are low on the failing edge of RAS. the write mask Is reloaded. A 16-blt binary
code (the write-per-bit mask) is input to the device via the random OQ pins and latched on the falling edge ~
RAS. The write-per-bit mask selects which of the 16.random I/Os are to be written and which are not. After RA
has latched the on-Chip write-per-bit mask. input data is driven onto the OQ pins and is latched on either the
first failing edge of WEx or the falling edge of CAS. whichever occurs later. WEL enables the lower byte
(OQO-OQ7) to be written through the mask and WEU enables the upper byte (OQ8-0Q15) to be written
through the mask. If a data low (write mask = 0) Is strobed into a particular I/O pin on the falling edge of RAS.
data Is not written to that I/O. If a data high (write mask = 1) is strobed into a particular I/O pin on the falling edge
of RAS. data is written to that I/O (see Figure 6).
f\_______1
I
I
I
I
I
I
I
I
I
I
I
I
\ _____----'1
7\~___. . .A@@~~~
\ !I I
I I
I I
--_
WED
II I
\
tsU(DQR)
14
I
II
~I
I I
~------..jl
I
N~' ___. . .A@@~~~
II
I
1144--t~o!-lI
II
I I
I I
tsu(DWL) ---!O:4......-+I~1 I
I
114-4-.......
~1th(RDQ)
th(WLD)
DQO~DQ15 ~,.,_W_rlte_M88_k....;lfl~,.,_w_r_lte_l_np_u_t.....-tt~
Figura 6. Example of a Nonpersistent Write-Per-Bit (late-Write) Operation
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persistent wrlte-per-blt
The persistent write-per-bit mode is initiated by performing a load-write-mask-register (LMR) cycle. In the
persistent write-per-bit mode, the write-per-bit mask is not overwritten but remains valid over an arbitrary
number of write cycles until another LMR cycle is performed or power Is removed.
The LMR cycle Is performed using DRAM write-cycle timing with DSF held high on the falling edge of RAS and
held low on the falling edge of CAS. A binary code is Input to the write-mask register via the random 1/0 pins
and latched on either the first WEx falling edge or the failing edge of CAS, whichever occurs later. Byte write
control can be applied to the write mask during the LMR cycle. The persistent write-per-bit mode can then be
used In exactly the same way as the nonpersistent write-per-blt mode except that the input data on the falling
edge of RAS Is Ignored. When the device is set to the persistent write-per-bit mode, It remains In this mode and
Is reset only by a CBR refresh (option reset) cycle (see Figure 7).
L
RASI
Load Wrlte-Maak Regleter
\
Perelstent Write-Per-Sit
/
\
/
I
CAS
CSR Refreeh (option rust)
\
I
I
r l1
I
----I
II
1
I
1
1
I
1
1
/1
\
I
I
\
/
1\
AO-AS
1
Add.....
DSFP'
~
WExP'
~
~~~5~
I
Mask Data
am+
~ ~
A
~.e.
~
Write-Mask' I
Date
~~
Valid
Input
~
I
1 : Write to VO enabled
• 0: Write to VO disabled
Figure 7. Example of a Persistent Write-Per-Blt Operation
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block write
The block-write feature allows up to 64 bits of data to be written simultaneously to one row of the memory array.
This function Is implemented as 4 columns x 4 DOs and repeated In four quadrants. In this manner, each of the
four one-megabit quadrants can have up to four consecutive columns written at a time with up to four DOs per
column (see Figure 8).
DQ1S[[]]
DQ14[[]]
DQ13[[]]
DQ12[[]]
DQ11[[]]
~Q10[[]]
OQ9[[]]
DQS[[]]
One Row of 0-511
OQ7[[]]
OQ6[[]]
DQ5[[]]
DQ4[[]]
DQ3[[]]
DQ2[[]]
OQ1[[]]
~m
4 Consecutive Columns of 0-511
Figure 8. Block·Write Operation
Each one-megabit quadrant has a 4-bit column mask to mask off any or all ofthe four columns from being written
with data. Nonpersistent write-per-blt or persistent write-par-bit functions can be applied to the block-write
operation to provide write-masking options. The DO data is provided by four bits from the on-chip color register.
Bits 0 -3 from the 16-bit write-mask register, bits 0 -3 from the 16-bit column-mask register, and bits 0 -3 from
the 16-blt color-data register configure the block write for the first quadrant, while bits 4-7,8-11, and 12-15
of the corresponding registers control the other quadrants In a similar fashion (see Figure 9).
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block write (continued)
OQ12
I"'T"T"'lO
~~
r--,I
.1._,
12
~: ~~
8[
OQ
ill
9
OQ
4
5
6
7
4[ ]
~
r--
f 1 .J
+++-hl~ L.J
,
I
-, I I
I I I
I
II f r .J
8
10
11
15
_, I I
I I I
I I I
~
.1._,
r .J
-.I~
.J
,
] r-.1._, I
-, I I
I I I
I I .JI
~
-.I~
J
.J
~
ic
~
8
0
2
3+Hr-t4
.Jj
!
I
~
-h
I~~
-4~
.!!l ~
~
I~ ~
~~
\ 0 1 2 3
4 5 6 7
8 9 10 11
12 13 14 15 I
~--------------------~v~--------------------~
Color RegIster
Figure 9. Block Write With Masks
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block write (continued)
Every four columns make a block, which results in 128 blocks along one row. Block 0 comprises columns 0 -3,
block 1 comprises columns 4 -7, block 2 comprises columns 8 -11, etc., as shown in Figure 10.
Block 0
Block 1 •••••.•••••••••.•.•••• Block 127
I "
,,------"'----.v,------"
One Row of 0-511
I
I
\
I
I
\
.I
o
2
3
4
6
7 ••••••••••••••••••••••••••• 511
5
\~----------~vr-----------JI
COIUml18
Figure 10. Block Columns Organization
During block-write cycles, only the seven most significant column addresses (A2 -AS) are latched on the falling
edge of CAS to decode one of the 128 blocks. Address bits AO -A1 are ignored. Each one-megabit quadrant
has the same block selected.
»
c
A block-write cycle Is entered in a manner similar to a ORAM write cycle except OSF is held high on the first
falling edge of CAS. As in a ORAM write operation, WEL and WEU enable the corresponding lower and upper
ORAM DO bytes to be written, respectively. The column-mask data is input via the OOs and is latched on either
the first failing edge of WEx or the falling edge of CAS, whichever occurs later. The 16-bit color-data register
must be loaded prior to performing a block write as described below. Refer to the write-per-bit section for details
on use of the write-mask capability, allowing additional performance options.
~
z
o
m
-z
Example of block write:
block-write column address
= 110000000 (AO -A8 from left to right)
."
o
::tI
s::
~
(5
z
color-data register
write-mask register
column-mask register
bit 0
= 1011
= 1110
= 1111
1st
Ouad
1011
1111
0000
2nd
Ouad
1100
1111
0111
3rd
Ouad
bit 15
0111
1011
1010
4th
Ouad
Column-address bits AO and A1 are Ignored. Block 0 (columns 0 -3) is selected for each one-megabit quadrant.
The first quadrant has1 000-002 written with bits 0-2 from the color-data register (101) to all four columns
of block O. 003 is not written and retains its previous data due to write-mask-register-bit 3 being a O.
The second quadrant (004- 007) has all four columns masked off due to the column-mask bits 4 -7 being 0, .
so that no data is written.
The third quadrant (008-0011 ) has its four ~Os written with bits 8 -11 from the color-data register (1100) to
columns 1-3 of its block O. Column 0 is not written and retains its previous data on all four ~Os due to
column-mask-register-bit 8 being O.
The fourth quadrant (0012-0015) has 0012, 0014, and 0015 written with bits 12, 14, and 15 from the
color-data register to column 0 and column 2 of its block O. 0013 retains its previous data on all columns due
to the write mask. Columns 1 and 3 retain their previous data on all ~Os due to the column mask. If the previous
data for the quadrant was all Os, the fourth quadrant would contain the data pattern shown in Figure 11 after
the block-write operation shown in the previous example.
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block write (continued)
OQ1511 1011 101
OQ1411 101 1101
OQ131 01010101
-.~
Columns 0
1
2
3
Figure 11. Example of Fourth Quadrant After Block-Write Operation
load color register
The load-color-register ~ is performed using normal DRAM write-cycle timing except that DSF is held high
on the falling edges of RAS and CAS. The color register is loaded from pins DaC -Da15, which are latched
on either the first falling edge of WEx or the falling edge of CAS, whichever occurs later. If only one WEx is low,
only the corresponding byte ofthe color register is loaded. When the color register is loaded, it retains data until
power is lost or until another load-color-register cycle is performed (see Figures 12 and 13).
Load-Color-Rsglatsr Cycls
Block-WrIt. Cyels
(no writs mask)
Block-Writs Cyel.
(load and us. writs mask)
OSF~~~~~=
000-OQ15_
Legend:
1.
2.
3.
4.
5.
6.
Refrash address
Row address
Block address (A2-AS) is latched on the failing edge of CAS.
Color-register data
Write-mask data: 000-0015 are latched on the falling edge of RAS.
Column-mask data: DQI-ool + 3 0 0, 4, 8, 12) are latched on either the first failing edge of WEx or the falling edge of CAS, whichever
occurs later.
-don'tcare
=
Figure 12. Example of Block Writes
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load color register (continued)
Load-Maak-Regleter Cycle
Persistent Block-Write Cycle
(UII loaded write mask)
Load-Color-Reglster Cycle
AO-A8~~~~~
WEx~
'fRO
000-0015
DSF
E
~~;;;:~~~~::~~~~~;;::~~;:::~~~~~~~~~~~~::~~
Legend:
1. Refresh address
.
2. Row address
3.
Block address (A2-AS) is latched on the falling edge of CAS.
4. Color-register data
5. Write-mask data: DQO -DQ15 are latched on the failing edge of CAS.
6. Column-mask data: DQI-DQI + 3 (I 0,4,8,12) are latched on either the first WEx falling edge orthefBtling edge of CAS, whichever'
occurs later.
• don'ti:are
=
Figure 13. Example of a Persistent Block Write
DRAM·to-SAM transfer operation
During the DRAM-to-SAM transfer operation, one half of a row (256 columns) in the DRAM array is selected
to be transferred to the 256-bit serial-data register. The transfer operation is invoked by bringing TRG low and
holding WEx high on the falling edge of RAS. The state of DSF, which is latched on the falling edge of RAS,
determines whether the full-register-transfer read operation or the split-register-transfer read operation is
.
performed.
Table 3. SAM Function Table
CAS
FALL
RASFALL
FUNCTION
CAS
TRG
WExt
OSF
ADDRESS
CAS
MNE
CODE
DSF
RAS
CAS
RAS
Tap
Point
X
X
AT
Tap
Point
X
X
SAT
Full-register-transfer read
H
L
H
L
X
Row
Addr
Split-register-transfer read
H
L
H
H
X
Row
Addr
t logic L is selected when either or both WEL and WEU are low.
X
don'tcare
=
~TEXAS
8-280
OOO-DQ15
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 772111-1443
WEx
SMJ55166
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SGMS057A-APRIL 1995-REVISEDJUNE 1995
full-reglster-transf.r read
A full-register-transfer read operation loads data from a selected half of a row in the DRAM into the SAM. TRG
is brought low and latched at the falling edge of RAS. Nine row-address bits (AD -AS) are also latched at the
falling edge of RAS to select one of the 512 rows available for the transfer. The nine column-address bits
(AD -AS) are latched at the falling edge of CAS, where address bit AS selects which half ofthe row is transferred.
Address bits AD -A7 select one of the SAM 256 available tap points from which the serial data is read 'Out (see
Figure 14).
AB=O
o
256256
AB=1
611
612" 612
Memory Array
256-Blt
Data Register
o
255
Figure 14. Full-Reglster.Transfer Read
A full-register-transfer read can be performed In three ways: early load, real-time load (or midline load), or late
load. Each of these offers the flexibility of controlling the TRG trailing edge In the full-register-transfenead cycle
(see Figure 15).
Earty Load
I
RAS
r-"\
I
.
I
CAS
AO-AB
II
1
TRGr\...J
I
I
Tap
Point
I
I
I
I
I
.
I
rr-\.
I
\
.
Row
LeteLoad
I
rr-\.
\
Row
Real-Time Load
I
Tap
Point
1 \
I
I
.
I
I
'--/
I.
I
I
Row
Tap
Point
1\
I
I
I
II
I
fI
I
wEx~~~~
. I
I
~~I~
~~I__- J
Figure 15. Example of Full-Reglster-Transfer Read Operations
~1ExAs
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SMJ55166
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MULTIPORT VIDEO RAM
SGMS057A-APRIL 1995-REVISEDJUNE 1995
spllt-reglster-transfer read
In the split-register-transfer read operation, the serial-data register is split into halves (see Figure 16). The low
half contains bits D-127, and the high half contains bits 128 - 255. While one half is being read out of the SAM
port, the other half can be loaded from the memory array.
o
511
612 Ie 612
Memory Array
256-BIt
Data Reglater
o
255
Figure 16. Split-Register-Transfer Read
To invoke a split-register-transfer read cycle, OSF is brought high, TRG is brought low, and both are latched at
thefaiJing edge of RAS. Nine row-address bits (AD-A8) are also latched at the falling edge of RAS to select
one of the 512 rows available for the transfer. Eight ofthe nine column-address bits (AO -A6 and AS) are latched
at the falling edge of CAS. Column-address bit AS selects which half of the row is to be transferred.
Column-address bits AD-A6 select one of the 127 tap points in the specified half of the SAM. Column-address
bit A7 is ignored, and the split-register-transfer is internally controlled to select the inactive register half
(see Figure 17).
"PlltXFER/
"PlltXFER/
AB.1
AB=o
r"-..
r"-..
0r--~.,...-r--;611
A B
DRAM
SAM
sa
o
A7 .. ot 511
o
m
'1~li~
sa
A7 .. 0t
511
II
'~EII~
sa
t A7 shown Is internally controlled.
, Figure 17. Example of a Spllt-Reglster-Transfer Read Operation
A full-register-transfer read must precede the first split-register-transfer read to ensure proper operation. After
the full-register-transfer read cycle, the first split"register-transfer read can follow immediately without any
minimum SC clock requirement.
~TEXAS
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INSTRUMENTS
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SMJ55166
262144 BY 16-BIT
MULTIPaRT VIDEO RAM
SGMS057A-APRIL 1995-REVISEDJUNE 1995
spllt-reglster-trans'er read (continued)
aSF indicates which half of the register is being accessed during serial-access operation. When aSF is low,
the serial-address painter is accessing the lower (least Significant) 128 bits of the SAM. When aSF is high, the
pointer is accessing the higher (most significant) 128 bits of the SAM. aSF changes state upon completing a
full-register-transfer read cycle. The tap point loaded during the current transfer cycle determines the state of
aSF. aSF also changes state when a boundary between two register halves is reached (see Figure 18 and
Figure 19).
Full-Reglater-Tranafer Read
With Tap Point N
I
\
RAS
1
\
1
1
r\
I
1
1
1
1
SC
r,:;\..
:14
14
I
I
\
1
I
ld(CLOSF)
\
Ii1
I
OSF
I
\
I
\I
CAS
TRG
Spllt·Reglater.
Tranafer Read
x:
PolntN
~
ld(GHOSF)
OSF
Figure 18. Example of a Spllt-Reglster-Transfer Read After a Full-Reglster-Transfer Read
Spllt·ReglsterTransfer Read
With Tap Point N
\
RAS
Spllt.ReglsterTransfer Read
~
If
1
1
1
1
1
~
\
CAS
TRG~
OSF~
1
1
1
1
1
1
ld(RHMS) 14
I
~
I
h
~I
I
\
I
ld(MSRL)
SC
14----,~~I-ld(SCOSF)
OSF
------------------------------~)(~___________________
Figure 19. Example of Successive Split-Register-Transfer Read Operations
~TEXAS
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SMJ55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS057A-APRIL 1995 - REVISED JUNE 1995
...rlal-read operation
The serial-read operation can be performed through the SAM port simultaneously and asynchronously with
DRAM operations except during transfer operations. Serial data can be read from the SAM by clocking SC
starting at the tap point loaded by the preceding transfer cycle, proceeding sequentially to the most significant
bit (bit 255). and then wrapping around to the least significant bit (bit 0). as shown In Figure 20.
r'
01
1121 ..... 1
Tapl-. .. •
125412551
I
Figure 20. Serial-Pointer Direction for Serial Read
For split-register-transfer read operation, serial data can be read out from the active half of the SAM by clocking
SC starting at the tap point loaded by the preceding split-register-transfer cycle. The serial pointer then proceeds
sequentially to the most significant bit of the half, bit 127 or bit 255. If there is a split-register-transfer read to
the inactive half during this period. the serial pointer points next to the tap point location loaded by that
split-register-transfer (see Figure 21).
Figure 21. Serial Pointer for Spllt-Reglster-Transfer Read - Case I
If there is no split-register-transfer read to the inactive half during this period, the serial pointer points next to
bit 128 or bit 0, respectively (see Figure 22).
Figure 22. Serial POinter for Split-Register-Transfer Read - Case II
split-register programmable stop pOint
ThEl SMJ55166 offers programmable stop-point mode for split-register-transfer read operation. This mode can
be used to improve two-dimensional drawing performance in a nonscanline data format.
In split-register-transfer read operation, the stop polntls defined as a reglstElr location at which thEl serial output
stops coming from one half of the SAM and switches to the opposite half of the SAM. While in stop-point mode,
the SAM Is divided into partitions whose lengths are programmed via row addresses A4-A7 in a CBR set
(CBRS) cycle. The last serial-address location of each partition is the stop point (see Figure 23).
127
0
I
Partition
Length
~
I
{
I· · ·1
1. ..
255
128
I
I
I
I J...
Figure 23. Example of the SAM With Partitions
~1ExAS
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I· · ·1
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
I
I
Stop
Points
SMJ55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
. SGMS057A-APRIL 1895- REVISED JUNE 1895
split-register programmable stop point (continued)
Stop-point mode is not active until the CBRS cycle is initiated. The CBRS operation is performed by holding CAS
and WE>< low and DSF high on the falling edge of RAS. The falling edge of RAS also latches row addresses
A4-A7, which are used to define the SAM partition length. The other row-address Inputs are don't cares.
Stop-point mode should be initiated after the initialization cycles are performed (see Table 4).
Table 4. Programming Code for Stop-Point Mode
ADDRESS AT RAi IN CBRS CYCLE
MAXIMUM
PARTITION
LENGTH
AS
A7
AS
AS
A4
AO-A3
16
x
L
L
L
L
X
16
32
X
L
L
L
H
X
6
64
X
L
L
H
H
X
4
15.31.47.63.79.95.111.127.143.159.175.
191.207.223.239.255
31.63.95.127.159.191.223.255
63.127.191.255
X
L
H
H
H
X
2
127.255
126
(default)
NUMBER OF
PARmlONS
STOP·POINT LOCATIONS
In stop·point mode, the tap point loaded during the split·reglster·transfer read cycle determines the SAM
partition in which the serial output begins and at which stop point the serial output stops coming from one half
of the SAM and switches to the opposite half of the SAM (see Figure 24).
Tap_H1
Tap=L1
H1
Tap=H2
191
Tap-L2
63
L1
H2
SC _ _ _ _ _ _ _ _ _~ ••• ~ •• • ~ • • • • • •
SAM Low Half
0
L1
63
t
1
L2
04
t:
127
128
04
H1
SAM HIgh Half
·191
:
04
255
L2
J'\/\....
255
H2
f
1 1
~
04
Figure 24. Example of Split-Register Operation With Programmable Stop Points
~1ExAs
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SMJ55166
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SGMS057A-APRIL 1995-REVISEDJUNE 1995
256-/512-blt compatibility of split-register programmable stop point
The stop-point mode is designed to be compatible with both 256-bit SAM and 512-bit SAM devices. After the
CBRS cycle is Initiated, the stop-point mode becomes active. In the stop-point mode, and only in the stop-point
mode, the column-address bits AY7 and AY8are internally swapped to assure compatibility (see Figure 25).
This address-bit swap applies to the column address, and It is effective for al/ DRAM and transfer cycles. For
example, during the spllt-register-transfer cycle with stop point, column-address bit AY81s a don't care and AY7
decodes the DRAM row half for the spllt,register-transfer. During stop-point mode, a CBR (option reset) cycle
is not recommended because this ends the stop-point mode and restores address bits AY7 and AY8 to their
normal functions. Consistent use of CBR cycles ensures that the SMJ55166 remains in normal mode.
NONSTOP POINT MODE
STOP-POINT MODE
512 x512
Memory Array
512x512
Memory Array
258-Blt
258-Blt
Dste Register
Dete Register
o
Figure 25. DRAM-to-SAM Mapping, Nonstop Point Versus Stop Point
IMPORTANT: For proper device operation, a stop-paint-mode (CBRS) cycle should be initiated immediately
after the power-up initialization cycles are performed.
power up
To achieRfi:Proper device operation, an initial pause of 200 !.IS is required after power up fol/owed by a minimum
of eight
S cycles or eight CBR cycles to initialize the DRAM port. A full-register-transfer read cycle and two
SC cycles are required to initialize the SAM port.
After Initialization, the internal state of the SMJ55166 is as follows:
STATE AFTER INITIAUZATION
aSF
Write mode
Write-mask register
Color register
Serial-register tep point
SAM port
Defined by the transfer cycle during Initialization
Nonpersistent mode
Undefined
Undefined
Defined by the transfer cycle during Initialization
Output mode
~TEXAS
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SMJ55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS057A-APRIL 1995-REVISEDJUNE 1995
absolute maximum ratings over operating free-alr temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................... -1 V to 7 V
Voltage range on any pin .• • . • . • . • . • . • • . . • . . . . . . . . . • . . . . . • . . . • . . • . . • . • . • • • • • • • . . • . • •• -1 V to 7 V
Short-circuit output current .•.•.•••.•.•.•.•••.....•.•..••.•.•.......•.•.•.•••..•.•.•.•••.•. 50 rnA
Power dissipation •..........•.......•....•.•.•.•...........•.•.•....•....•............•.• 1.1 W
Operating free-air temperature range, TA ..............................•.•.•.•.•.•. - 55°C to 125°C
Storage temperature range, Tstg •.•...........................•.......•.•.....•.•. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the devloe at these or any other conditions beyond those Indicated under "recommended operating conditions· Is not
implied. Exposure to absolute-maxlmum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
VSS
Supply voltage
Supply voltage
VIH
High-level input voltage
VCC
MIN
4.5
NOM
5
MAX
5.5
V
0
2.4
UNIT
V
6.5
V
Low-level input voltage (see Note 2)
-1
0.8
V
VIL
·C
Operating free-air temperature
125
-55
TA
.. . .
NOTE 2: The algebraic convention, where the more negative pess posillve) limit is designated as minimum, is used for logic-voltage levels only•
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS*'
VOH
High-level output voltage
IOH =-1 mA
VOL
Low-level output voltage
IOL=2mA
II
SAM
PORT
'55166-70
MIN
MAX
2.4
'55166-80
MIN MAX
2.4
UNIT
V
0.4
0.4
V
Input current (leakage)
Vec=5.5V,
VI =OVto 5.8 V,
All other pins at 0 V to VCC
:1:10
:1:10
tAA
10
Output current (leekage)
(see Note 3)
Vec .. 5.5 V, Vo ,,0 V to Vcc
:1:10
:1:10
tAA
ICC1
Operating current §
See Note 4
Stendby
165
180
mA
ICC1A
Operating current §
210
195
mA
Standby current
teISC) =MIN
All clocks. VCC
Active
ICC2
Standby
12
12
mA
ICC2A
Standby current
ActIve
70
mA
ICC3
RAS-only refresh current
teISCl" MIN
See Note 4
ICC3A
1CC4
RAS-only refresh current
Page-mode current §
te(SC) .. MIN,
ICC4A
Page-mode current §
ICC5
1CC5A
CBR current
Icca
Data-transfer current
CBRcurrent
Stendby
165
65
160
See Note 4
Active
215
195
mA
teIP)" MIN,
See Note 5
Standby
100
95
mA
te(SC) = MIN,
See Note 4
See Note 5
ActIve
145
130
mA
Stendby
165
160
mA
teISC) "' MIN,
See Note 4
See Note 4
ActIve
210
195
mA
Standby
180
170
mA
225
200
rnA
ActIve
ICC6A Data-transfer current
te(SC) =MIN
*' For conditions shown as MIN/MAX, use the appropriate value specified an the timing requirements.
§ Measured with outputs open
NOTES: 3. BE is disabled for sa output leakage tests.
4. Measured with one address change while RAS = VIL.and te{rd), te{W), te{TRD) .. MIN
5. Measured with one address change while CASx = VIH
c
rnA
~.1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-287
SMJ55166
262144 BY 16-BIT
MULTIPaRT VIDEO RAM
SGMS0S7A- APRIL 1995 - REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature.
f = 1 MHz (see Note 6)
TYP
MAX
CI(A)
Input capacitance, AIJ-AS
5
10
pF
CltRC}
CI/W)
Input capacitance, ~.and RAS
S
10
pF
Input capacitance, WEL and WEU
7
10
pF
CI(SC)
Input capacitance, SC
6
10
pF
CUSE!
Input capaclt8nce, §E
7
10
pF
CICDSFl
Ci(TRG)
Input capacitance, QSF
7
10
pF
Input capacitance, TAG
7
10
pF
12
15
pF
10
12
pF
PARAMETER
MIN
Output capacitance, SQ and DQ
CofOI
Co(QSFl Output capacitance, QSF
NOTE S: VCC 5 V :I: 0.5 V, and the bias on pins under test Is 0 V.
UNIT
=
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 7)
PARAMETER
ALT.
TEST
CONDITIONS t
SYMBOL
'&5166-70
'66166-60
MIN
MIN
MAX
MAX
UNIT
ta(C)
Access time from ~
id(RLCL) = MAX
tcAC
20
20
ns
ta(CA)
Access time from column eddress
id(RLCL) = MAX
tM
35
40
ns
ta(CP)
Access time from CAS high
id(RLCL)
tCPA
40
45
ns
ta(R)
Accesa time from RAS
=MAX
id(RLCL) =MAX
!RAc
70
60
ns
ta(G)
Access time of DQ from TRG low
tOEA
20
20
ns
ta(SQ)
Access time of SQ from SC high
CL"30pF
!sCA
20
25
na
ta(SE)
Access time of SQ from SE low
CL=30pF
!sEA
15
20
ns
idls(CH)
Disable time, random output from CAS high
(aee NoteS)
CL=50pF
toFF
idls(RH)
Disable time, random output from RAS high
(see NoteS)
CL=50pF
idls(G)
Disable time, random output from TRG high
(see Note 8)
CL=50pF
idls(WL)
Disable time, -random output from WE low
(see Note 8)
idls(SE)
Disable lime, serial output from SE high (see Note 8)
0
20
0
20
ns
0
20
0
20
na
toEZ
0
20
0
20
ns
CL=50pF
IWEZ
0
20
0
20
na
CL=30pF
!sEZ
0
15
0
20
ns
t For conditions shown as MIN/MAX, use the appropriate value specified in the timing requiraments.
NOTES: 7. Switching times lor RAM-port output are measured with a loed equivalent to 1 TTL load and 50 pF. Data-out reference level:
VOH /VOL .. 2VIO.8 V. Switching times lor SAM-port output are measured with a load equivalent to 1 TIL load and 30 pF. Serlal-data
out reference level: VOH /VOL 2 VlO.8 V.
B. idis(CH), idis(RH), idia(G), idis(WL), and idis(SE) are specified when the output is no longer driven.
=
~TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. 'TECAS 772li1-1443
SMJ55166
262144 BY 16-81T
MULTIPaRT VIDEO RAM
SGMS057A-APRIL 1995-REVlSEOJUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-alr
temperature t
ALT.
SYMBOL
te(rdl
Cycle time, read
IRc
te/Wl
Cycle time, write
telrdWl
te(P)
Cycle time, reed-modify-write
Cycle time, page-mode read, write
Cycle time, page-mode read-modify-write
Cycle time, transfer read
Cycle time, SC (see Note 9)
two
tRMW
tpc
telROWPl
terrRol
telSCl
Iw(CH)
IwICLl
Iw(RH)
'55166-70
MIN
MAX
130
130
175
45
tPRMW
85
IRc
tacc
tePN
130,
teAS
tRP
20
Pulse duration, CAS high
Pulse duration, CAS low (see NOie 10)
22
10
10000
'55166-80
MIN
MAX
150
150
200
UNIT
na
ns
na
50
nl
90
150
30
10
na
na
na
na
na
na
ns
20
10000
twIRL)
Pulse duration, RAS high
Pulse duration, RAS low (see NOie 11)
'RAs
50
70
tw(WLl
Pulse duration, WEx low
twP
10
15
ns
IwrrRGl
Pulse duration, TRG low
Pulse duration, SC high
20
20
na
8
8
10
10
ns
20
20
70 100000
80 100000
IwISCHl
Iw(SCL)
tsc
tscp
trp
Pulse duration, SC low
60
10000
80
10000
na
na
na
IwIGHl
Iw(RUP
Pulse duration, 'fAG high
Pulse duration, RAS low (page mode)
isulCAl
isu(SFCl
Setup time, column address before CAS low
Setup time, OSF before CAS low
Setup time, row address before RAS low
tASC
tFSC
tASR
0
0
0
Satup time, WEx before RAS low
twSR
tMS
0
trHS
tFSR
tosc
0
0
0
0
0
0
0
0
15
0
ns
20
nl
isu1B!< low'
isulrell
Satup time, read command, WE>< high before CAS low
tosw
tRCS
isuIWCLl
Setup time, early write command, WE>< low before CAS low
twcs
Satup time, WE>< low before CAS high, write
Satup time, WE>< low before AAS high, write
0
0
0
0
0
nl
0
0
ns
0
0
na
nl
na
nl
ns
ns
na
ns
isuIWCHl
teWL
20
na
20
tRWL
isulWRHl
Hold time, column address after CAS low
10
15
nl
thlCLCAl
teAH
15
15
Hold time, OSF after CAS low
nl
th(SFC)
teFH
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 9. Cycle time assumes tt =3 nl.
10. In a read-modify-write cycle,ld(CLWL) and isu(WCH) must be observed. Depending on the user's transition times, this can require
additional CAS low time £iw(cL)]'
11. In a read-modify-write cycle, ld(RLWL) and isu(WRH) must be observed. Depending on the user'l transition times, this can require
additional RAS low time [twIRL)].
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-289
SMJ55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS067A-APRII, 1995- REVISED JUNE 1995
tImIng requIrements over recommended ranges of supply voltage and operatIng free-alr
temperature (contlnuecl)t
ALT.
SYMBOL
'65166·70
MIN MAX
'65166·80
MIN
MAX
UNIT .
ih(RA)
Hold time, row address after RAS low
tRAH
10
10
ih(TRG)
Hold time, TRG after RAS low
15
15
ih(RWM1
Hold time, write mask after AAS low
trHH
tRWH
15
.15
ihlRDOI
ih(SFR)
Hold time, DO after RAS low (write-mask operation)
tMH
tRFH
15
15 '
10
10
ns
ns
ns
ns
ns
ih(RLCAI
th(CLD)
Hold time, column address valid after RAS low'(see Note 12)
tAR
30
35
n8
Hold time, data valid after ~ low
tDH
15
15
n8
th(RLDI
Hold time, data valid after RAS low (see Note 12)
tDHR
35
thlWlDI
th(CHrd)
Hold time, data valid after W&.low
toH
15
ns
ns
Hold time, read. W&. high after CAS high (aee Note 13)
tACH
0
35
15
0
th(RHrd)
Hold time. read. W&. high after RAS high (see Note 13)
tRRH
0
0
ns
ih(CLW)
Hold time. write. W&.1ow after CAS low
twCH
15
15
ns
ih(RLWI
Hold time.• write. W&.1ow after RAS low (see Note 12)
twCR
35
35
ihlWlG)
Hold time. TRG high after WEx low (aee Note 14)
10
th(SHSO)
Hold time. SO after SC high
toEH
tSOH
10
2
th(RSFl
Hold time.DSF after RAS low
tFHR
35
th(CLOI
Hold time. Output after CAS low
tDHC
0
na
teSH
tCHR
70
2
35
0
80
15
ns
ns
ns
ns
n8
Hold time, DSF after RAS low
I
n8
ld(RLCH)
Delay time. RAS' low to ~ high
ld(CHRLI
ld(CLRH)
Delay time. CAS high to RAS low
teRP
tRSH
0
0
Delay time. CAS low to RAS high
20
20
na
ld(CLWL)
Delay time. CAS low to W&.1ow (see Notes 16 and 17)
tcwo
45
50
ns
ld(RLCLI
Delay time. RAS loW to CAS low ($ee Note 18)
ld(CARH)
Delay time. column address valid to RAS high
tRCD
tRAL
35
40
na
ld(CACH)
Delay time. column address valid to CAS high
ld(RLWL)
I See Note 15
10
20
50
20
na
60
na
35
40
na
Delay time. RAS low to W&' low (see Note 16)
teAL
tRWD
85
100
na
ld(CAWL)
Delay time. column address valid to W&.low (see Note 16)
tAWD
60
65
n8
ld(CLRL)
Delay time. CAS low to RAS low (see Note 15)
O·
0
na
ld(RHCL)
Delay time. RAS high to ~ low (see Note 15)
teSR
tApc
0
0
n8
ld(CLGH)
Delay time. CAS low to "fAG high for DRAM read cycles
20
20
n8
15
n8
Delay time, "fAG high before data applied at DO
15
ld(GHD)
toED
t liming measurements are referenced to VIL max and VIH min.
NOTES: 12. The minimum value is measured when ld(RLCL) 18 sat to ld(RLCL) min as a reference.
13. Either th(RHrd) or ih(CHrd) must be setisfiad for a read eyele.
14.0utput-enable-:eontrolied write. Output remains In the high-impedance state for the entire cycle.
15. CBR refresh operation only
18. Read-modify-write operation only .
17. "fAG must disable the ouiput buffers prior to applying data to the DO pins.
18. The maximum value is speciflad only to assure RAS access time.
~1ExAs
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timing requirements over recommended ranges of supply voltage and operating free-alr
temperature (contlnued)t
ALT.
SYMBOL
'&5188·70
MAX
'&5188·80
MIN
MIN
80
80
MAX
UNIT
lcIlRLTHl
Delay time, RAS low to fFiCJ high (see Note 19)
lATH
55
lcIIRLSH)
Delay time, RAS low to first SC hIgh after TRG high (see Note 20)
70
lcI(RLCA)
Delay time, RAS low to column address valid
tRSD
tRAO
lcICGLRH)
Delay time, i'RG low to RAS high
tROH
20
lcI(CLSH)
Delay time, CAS low to first SC high after TRG high (see Note 20)
teSD
20
20
25
ns
lcICSCTRI
Delay time, SC high to TRG high (see Notes 19 and 20)
iTsL
Delay time, TRG high to RAS high (see Note 19)
trRD
5
-10
ns
lcIlTHRHI
lcI(THRL)
5
-10
Delay time, TRG high to RAS low (see Note 21)
trRP
50
ns
lcIlTHSC)
Delay time, TRG high to SC high (see Note 19)
trSD
15
80
20
lcI(RHMS)
Delay time, RAS high to last (most signiflC8l1t) rising adge of SC before
boundary switch during spllt-register-transfer read cycles
20
20
ns
15
35
15
ns
ns
40
ns
ns
ns
ns
lcI(CLTH)
Delay time, CAS low to TRG high in real·time-transfer read cycles
lOTH
Delay time, column address to first SC in early-load-transfer read cycles
tASD
15
25
15
30
ns
lcICCASHI
lcI(CAGH)
Delay time, column addreSs to TRG high in real-time-transfer read
cycles
tATH
20
20
ns
lcIrocu
Delay time, data to CAS low
tDZC
0
0
ns
lcI(DGL)
Delay time, data to fFiCJ low
tDZO
0
0
ns
lcI(MSRL)
Delay time, last (most significant) rising adge of SC to RAS low before
boundary switCh during spilt-transfer read cycles
20
20
ns
lcI(sCQSF)
Delay time, last (127 or 255) rising edge of SC to OSF switChing at the
boundary during spllt-register-transfer read cycles (see Note 22)
tsOD
25
30
ns
lcI(CLOSF)
Delay time, CAS low to OSF switching in transfer read cycles
(see Note 22)
teOD
30
35
ns
lcI(GHOSF)
Delay time, i'RG high to OSF switching in transfer read cycles
(see Note 22)
trOD
25
30
ns
lcI(RLOSF)
Delay time, RAS low to OSF switching In transfer read cycles
(see Note 22)
tROD
70
75
ns
it1(MA)
Refresh time Interval, memory
tREF
8
ms
It
Transition time
50
ns
tr
3
8
50
3
ns
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 19.
20.
21.
22.
Real-time-Ioad transfer read or late-load-transfer read cycle only
EarIy-Ioad-transter read cycle only
Full-register-(reed) transfer cycles only
Switching times for OSF output are measured with a load equivalent to 1 TTl. load and 30 pF, and the output reference Iavel is
VOH /VOL =2 VIO.8V.
~TEXAS
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SGMS057A-APRIL 1995-REVlSEDJUNE 1995
wei
IIII
1 1
tcsI8(CH)
1 14
1
~ 11 . 11 11
1
1
1
14 I .1
1
1
!+
+I
I1
I1 I1
{
,
I '+-- --+I
tcs(DGL)
DQO-DQ1S
ta(O)
Data In)
1+ tcsls{G)
Data Out
xxxx:xxxxxxxx:
~'------
ta(C)
1
1
14
14
ta(CA)
ta(R)
~,
.,
Figure 26. Read-Cycle Timing With CAS-Controlled Output
~TEXAS
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MULTIPORT VIDEO RAM
SGMS057A-APRIL 1995-REVISEDJUNE 1995
PARAMETER MEASUREMENT INFORMATION
WEx~11
I~
1111i~
1
teI(DGL)
DQO-DQ1S
14 1
~
Data In)
--
I1
1
1
I
14
.1
1
1
1
1
1
1
1
1
I
1+ ta(G) +I
(
II
I
1 1+ tells(G) -+j
~ tells(RH) ~
Data Out
))------
.
14- ta(C)-+l
14
ta(CA)
ta(R)
.:
.1
Figure 27. Read-Cycle Timing With RAS-Controlled Output
-!!1ThxAs
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-
PARAMETER MEASUREMENT INFORMATION
~
RAS
I ,..
---.iN
twIRL)
tt ~ 14I '"
~
~ ~
I
1+
'"
IcI(RLCL) -.I
M
AD-AS
I
I
~
Iw(CL)
N---+I
II
I j+- th(RLCA)
"'(RA)
14I ..,
IcI(CACH}
~!4T- tau(CA)
I I
IcI(RLCA)"'1
~I I I'll . ~I "'(CLCA)
1+!
~I
IcI(RLCH}
IcI(CLAH}
~
IcI(CHRL)
~
, I
l1'
'L
~I ~ Iw(RH} -+I
I I
t
.
I
~ I+- tt
I
IcI(CHRL) -.I
Vl+i-Iw(CH}~\....
.
I
~I
I
I
I
I
I
I
taU~A)~
III
',,'~'
~'.
IcI(CARH)~
.
Row
Column
.
~~~~~~~~~~~~~~
tau(SFR)
~ I I tau(SFC)
14--- Ih(RSF) --.I
-+! i4t
I I
"'(SFR)tl
r-
·.1
I'''.
I
I
I
I
~: .~
. I
I
I
.
DSF~II~II~
tau(TRG)
fRO
~
-+I i4t
14- Ih(TRG!
I
I
I '
. .
mrll
tau(WMR)
-.I
IrrJ
I.. I I
I.. I I
I I ,"
:
I I
Ih(RLW)
th(CLW)
~ 14- I I ,..
~ .~taU(WCL)
Ih(RWM)
WEi
~::
I I
-+I ~
Ih(RDQ~ -.I 14- ~ I+- tau(DCL)
~ ~~
Ih(RLD)
DQO-DQ15
~
~I
.
1w(WL)
I I
I i4----- "'(CLD)
tau(DQR)
~I
tau(WCH)
tau(WRH)
,
I
~I
~I
I
. - .
---.!
3
I
~
_
Figure 28. Early-Wrlte-Cycle TIming
Table 5. Early-Wrlte-Cycle State Table
STATE
CYCLE
Write operation (nonmasked)
Write operation with nonpersistent write-per-bit
Write operation with persistent write-per-bit
1
2
3
H
Don't care
Valid data
L
Write mask
Don't care
Valid data
L
~TEXAS
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
Valid data
SMJ55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS057A-APRIL 1995 - REVISED JUNE 1995
TAG
~I
I:
I
t4"
!.I I
-+;
I
I
I.
I
~_I.:I tsu(WMR) 1
1
1
~
,
tsu(TRG) :
I4jI tci(GHD)
1.1-.
n
~
WEx
LI
tsu(DQR)-+t
Il
tsu(DWL)
I+-
1 -+;
1 I.'
DQO-DQ1&
Ih(RDQ)
i
I.
I.
I
I
:
I.
I
I.,
tsu(WRH)
tsu(WCH)
th(CLW)
---+I
.1
I
.1
I
th(RLW)
Ih(WLG)
N
~
I
I
I
I
.1
,~~~I~~~~~
~~
tw(WL)
t.I1 I ~1"t-1h(WLD) ---+I
I I
I I
~
I
.1
th(RLD)
3
~
Figure 29. Late-Wrlte-Cycle Timing (Output-Enable-Controlled Write)
Table 6. Late-Wrlte-Cycle State Table
STATE
CYCLE
1
2
3
Write operation (nonmesked)
H
Don't care
Valid data
Write operation with nonpersistent write·per·bit
L
Writemesk
Valid date
Write operation with persistent write-per-blt
L
Don'tcara
valid date
~TEXAS
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PARAMETER MEASUREMENT INFORMATION
~
~
'N
- -.......' ,..
~
1w(RL)
'
Yj..-Iw(RH)
----l I 1I
tt -., t+
I..
I J..- tcs(RLCL) -+I
W
r;i}
-Ao
.,
~'---
.1
I,
,
I .1,
,
1 -+I ~ tt
,
I .I+!-! ~(CHRL) --+I
tcs(RLCH)
tcs(CLRH)
J'-I' ,-'
.
' .
_M~~%:~
Nl,.I
tcs(CHRL)
I I
lti(RA) ~
_I
I
-(CL)
II
-+I
I 1
~Jo.
y,~,
L
,
IIIIIt- teU(SFC)
I
I
I
-... I4t teu(SFR)
"
I I I..
lti(RSF) ---+I
lh(sFR)-f.I.,
DSF
.
Ii
~
____
~~
~a-~'+,
ti j+=
,
Iw{CH)~
,
I
I
I
I' I" .: ~
NQQll I
-II
1
14
~I
I teu(TRO) 1
.......
:4
~teu(WMR'
XX?
U
teI(DOL)
I
th{fRO)
1
1
1 .,---t--1 I
I
I
I
II
WEx
~ I+-lt
I
.1
~
-+I
I :~ ~~1 ~ ! ~}~ collumteln-~~
§X:~:.- ~I>w<; c~+
~
~
I I
I
·1
.1
I
teu(RA)
DSF
~
I+-- tw(CH) ~ I
I
j+- teI(RLCA) -+j
I
!J~
IcI(RLCH)
1
I
teu(CA) I~
~I 14
I
~! I
I+- teI(CLRH)
I
_AS
~I
tw(RL)P
1
1 1
I
1
teu(rd)
I
I
I
I
I
II
I
I
1I
1
I 14
J.41
DQO- ----~
Data In
I
I+-
lti(RHrcI)
I
i+-ta(c)
I
I
I
:.-
~I
I
ta(CA) t
ta(CP) t
Data Out
DQ15
I
1
I
I
th(CLQ) ~
-+I
t----.I
ta(CA)
~I I+- te(O)
ta(R)*
I
--{.r
I
I
I
I
~ ~!4.
i
I
IcIla(WL)
tella(RH)
1"-
-l+-+I
I+- tella(O) -+!
Data Out
I
f+-1cI/DCL)
-+I
*t
Access time is ta(CP) or ta(CA) dependent.
Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS and CAS to select the desired
write mode (normal, block write, etc.).
Rgufe 33. Enhanced-Page-Mode Read-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
t Referenced to the first failing edge of WEx or the falling edge of CAS, whichever occurs later
NOTE A: A reed cycle or a read-modify-write cycle can be intermixed with write cycles,· observing read and read-modify-write timing
specifications. To assure page-mode cycle time, fAG must remain high throughout the entire page-mode operation if the late-write
feature is used. If the early-write-cycle timing is used, the state of TRG is a don't care after the minimum period th(TRG) from the failing
edge of RAs."
Figure 34. Enhanced-Page-Mode Write-Cycle Timing
Table 8. Enhanced-Page-Mode Write-Cycle State Table
STATE
CYCLE
1
Write operation (nonmasked)
L
Write operation with nonpersistent writa-per-blt
2
L
L
L
3
4
5
H
L
Don't care
Valid data
Write mask
Valid data
L
Write operation with persistent write-per-bit
Don't care
valid data
L
L
Load-write-mask register on either the first failing edge of
Don't care
Write mask
H
L
H
wei or the failing edge of~, whichever occurs later.
Load-write-mask-register cycle puta the device In the perslstent write-per-bit mode. Column addreas at the falllng edge of CAS Is a don't care
during this cycle.
*
~TEXAS·
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MULTIPORT VIDEO RAM
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PARAMETER MEASUREMENT INFORMATION
~
~
I 1111
i4t teI(CHRL)
~...
~
teI(RLCA) L.
-.r
AO-AS
I+- ih(RA)
'III'
teI~LCH)
1111
Ic~owp)
·1 teI~LC~
, 1111
tw(CL) ---.I
-= 4,III
I~ teu~
teu(CA)
I
.,
I.,
11111
ih(CLCA) ,
, I+-f tw~H)
I+-- teI(CLRH) ---J
.1
I
teI(CHR~
tw(CH)
,
I ,
I ,
I
1t=:!!..I
.1
I
I I
teI(CARH)
~~~:!~:: ~H-~
~ ~
14- ih(SFR)
!_
1111 I ,
II
~
>t~(SFC)1
~~~(SFC)_W
....,
OSF
~~~p----------------~~
" t e.......
~
.",r+-~~(WCH)-oj;
, ,I
teI(CLW~
I, I'III,,
-.I I
I
1111 ' ,
4 1
.:;.
.1 'I
II
I I
' ,
teu(SFC)
~
_-oj'"I
II
~ r.I- teI(DC~
,'...!I,
I
14- teI(CLGH) ,I
,
I
---.L-!
ih(TRG) 11111'
., I 'III
.' teI(CLGH) I
'I I I teu(WRH) ~
-+I ~te G
I
,
I
1-,
U(TRN)
l1li1
.JA'
!w(TRG)
I I
I
,
I I I
I, II'
, 'I;.:.;.;.;.~,"1"1~-""'fl_~ IF.
"I
I' I
, Ij'-JI
I I'
~ teu(WMR) II I
I
I I
~(TRG)
I I I i+"th~WM) I
I tw(WL) ~
'II
,
,I II r+- te(C)t
I
;'-'I-!-:--il- - - , L~~~~
,III II ~I ta(CA) t
II
I
~ I4+- teu(DW~
teu(DOR)
I I
II
I th(WLD) 1111
.1
- 11____ .... (R~DQ) teI(DC~
II
1111
.1 I teI(GHO) I
~ .....- on
'4-r--,f-I+-Ia(CP) t
II
I
teI(CAWL)
teI(RLWL)
, :
., ,
.
wi
'fl I4t
M
I I
000-0015
,
i---~
I ,
I~
(+-1a(G) t
teI(DG~ -+I I+- I
teI(GHO)
I
I
teI(DG~ -+I
-l+-+I
II
't
,I
I I
-..r
i+-1a(R) t ~
-+II+- Ia(C)t
t Output can go from the high-Impedance state to an Invalld-data state prior to the specified access time.
Valid Out
I+- tella(G)
NOTE A: A read or a write cycle cen be Intermixed with read-modify-write cycles as long as the read and writetlming specifications are not violated.
Figure 35. Enhanced-Page-Mode Read-Modlfy-Wr,te-Cycle Timing
Table 9. Enhanced-Page-Mode Read-Modlfy-Wrlte-Cycle State Table
STATE
CYCLE
Write operation (nonmasked)
1
2
3
4
5
L
L
H
Don't care
Write mask
Valid data
Write operation with nonpersistent write-per-bit
Valid data
L
L
L
Write operation with persistent write-par-bit
Valid data
L
L
L
Don't care
,
Load-write-mask register on either the first failing edge of
Write
mask
H
L
H
Don't care
WEx or the failing edge of l5AS, whichever occurs later.*
* Load-wrlte-mask-reglster cycle sets the device to the persistent write-per-bit mode. Column address at the falling edge of CAS Is a don't care
during this cycle.
~1ExAs
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PARAMETER MEASUREMENT INFORMATION
tw(RH)~
RAS
N
tw(R~P
'l1li.
.!. .
.
1
tcI(RLCL)
-+I ~ tcI(CHR~
,
leu(RA)
~
I j+14
1 'l1li
I+- tcI(CLRH)
tw C~ 'l1li
1
'
~
tcI(RLCA)
,
I
I+I
If\-
.~! 1
-r.
I . --.or
'
I'
ft
1'-'
tcI(RLCH)
teU(CA):IIII.1 'l1li
==:
:
_ -- ---
~ tcI(CACH) --.I
~
:
.1
I,
t~'!
1b(RA) , l 1 l i . ,
~
-...~:WIllI.:- .,~ "7+'
I '.
.1
Ib(CLCA)
,
~
"'(CARH)-.
. . &1r:~-~
th(SFR)
1 'l1li
., Ib(TRG)
, teu(TRG) I
,
1 1
,
1 1
1
-+:1l1li ~teU(WMR\
1
.,
leu(rcI)
wei
W!
1
tcI(DOL) ,1l1li
, 1
_ _ _1l1li'"'11,1
DQODQ15
Data In . )
I
1 1
1
IeU(WC~
"
"
,
1
I
: : ~te(C)
I
..!
,
.!
f\
'
"
~~tw~~y
I+- Ie(CA)t
~
~'I
--
,
:
'I"
.'
I+- ta(G)
tcI(CLGH)
,
1 ,
1 ,l1li
1 ,
1
,
.1 1
.1 ,
'l1li
:
I :
.11
jOIIII
I
I
r- -+II
leu(DCL)
1do(Wll~
Data Out
;----\
1 I
1 ,l1li
•
j+-
I Ib(CLD)
J
I
Data In
)>--------
j4--- tcI(DCL) ~
*t Output
Accesa time is ta(CP) or ta(CA) dependent.
can go from the high-Impedance state to an InvaDd-data state prior to the specified access time.
NOTE A: A write cycle or a read-modlfy-wrlte cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF Is selected on the failing edge of RAS and CAS to select the desired write
mode (normal, block write, etc.).
Figure 36. Enhanced-Page-Mode Read-/Wrlte-Cycle Timing
~1ExAs
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PARAMETER MEASUREMENT INFORMATION
~
~
_ _ _..,.' ,l1li
~,
llllll
It -.I
l+-
,l1li
!+- tcs(RLC4 -+I
!_
tcs(~ ij
&S~-W ~
,,,
, ,
'h(RA)
-+' !.L tau(RA)
AO-AS
~
tw(R4
N',~
.,
.,
tci(RLCH)
,
f ~ tw(RH) ~
-+I I+-It
,~
'""'"
tci(CLRH)
I, ,
'
'L
VT
,
,
~ :+t-........ -----.I
0:
,, :. . I,
"
,
tw(CH)
J\-
.:
,
--~
, ,
"l1li
, JIIII
'h(RSF) ,
taU(SFR)~, IIIIIt
.:
.,
th(SFC)
-+t!llll+ tau(SFC)
"
,
,
,
,
~ ""'h(SFR)"
_
,
'
W"I~',~
fR
G
w
+
i
i
_
:.t
-+t
tau(WMR)
"
,'l1li
'h(RWM)
WEx
+-+!
1+
,l1li "
'l1li' ,
'"
_I
tau(WCH)
tau(WRH)
th(RLW)
I ~!1111
th(CLW)
tau(WCL)
.,'
.'
~
.,
,
~ r+
~ "'VXSOhl
,'
~
I~'I
,
I ~'l1li It...t' t w ( w 4
~
.'
tau(DCL)
,
'l1li
'1l1li
th(CLD) --~.'
,
'h(RLD) ----~.I
~~~~~~~ I~----------------~'
~:5 ~
valid-Color Input
~
Figure 37. Load-Color-Reglster-Cycle Timing (Early-Write Load)
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PARAMETER MEASUREMENT INFORMATION
14
tc(W)
1 14
FiAS
---N
. 1 14
It
~I
w
~
tct(C~
CAS
i
I4t
II
:
AO-AB
I+i4-
.1
tct(RLCH)
14
tct(RLCL)
.
1
1
N.~
1
L
tw(RH)-+I
I 11
. It
!+tJJ 1
~I I
tct(CLRH)
-.I
i+-1h(RSF)
nI:-
.1
.1
tw(RL)
tw(CL)
I I .:
tct(CHRL)
: 14:
I
-+I
tw(CH)
i'.1
~~~
feu(SFR)
-+! i4t
Ih(SFR)
~
1 ,4
.,
th(SFC)
I·
I+- -+I I4t feu(SFC)
1
1
1
D8F~iiW!_
-+I rt- !
I
! .
~
14
14
I .1 ~
'fAG
: :
1 14
~ j4t feu(WMR)
1
1
WEx
th(CLW) feu(WRH)
~ tct(GHD) -:----+1
~ !
1
1
1
14
14
1
I
.1
Ih(RLW)
1
14
1
N~
!
.:
.1
feu(WCH)
th(WLG)
1
1
1
1
1
.1
~~
tw(WL)
1 !_I
~ ~feU(DwL)
1 1 I + - th(WLD) --.I
1
Ilh(RLD)
~:6 ~
Valld-Colorlnput
.:
~
Figure 38. Load-Color-Reglster-Cycle TIming (late-Write Load)
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PARAMETER MEASUREMENT INFORMATION
14--------- tc(W) --------+l~
14------ twIRL) ------I~~I
I
----.i.
",",=======t;,;.;=====;~:0(4~I -.! I+-lt
1+
tw(RH)
tcI(RLCH)
It::!~~_--I~---tc1 (CLRH)
I ~I
I
I r++- tcI(CHRL) -+I
-
~~H-+-':"''''''':'.... 14---tw(CL)
tcI(RLCA)
fcI(RLCA)
~
I I
I ~
I j4- th(RLCA) ---+l
I. I~
~I~ I I
141I~ I I
I
taU(RA)
lh(RA)..w.J I+AO-AS
-.I I j+I j4f
tau(SFR)
th(SFR)..L1J
.
DSF
n
I
I
-!.!
I II
-+II
Block Address
A2-AS
I I~
~I
I II
I
I
I
I
I
I
I
I
.... S C)
I
_
.
II~ I I
tsu(WCH)
I I I~ I I
tsu(WRH)
i4t I -.I J.L tau(WCL)
-+I
/+"
II
Iii I~
~ I!
~I I
1
=
I
1-:-:-L.~~ 1
( + - - th(CLO)
~
I
~I
~I
tw(WL)------I~
IIjoII~f__--+-1~II th(RLD)
-+j /4f taU(DCL)
+-+l14-
~I
:=-------
th(CLW)
Ita(RLW)
~I
~~.
lh(RDQ\
I
I+-lh(TRG) I
II~
I
tau(DQR)
I~I
----.! I I
~II
I I
tau(WMR)
DQO-DQ15
tcI(RSF)
~
th(RWM)
WEx
tcI(CACH)
r-r-y..
~II¥IlII11
tau(TRG) -+(
TRG
.
I+- -+j I4t tau(SFC)
.111 I
J,..o.+----_
I
I I
I
I !+t-lw(CH)--.I
II I
tcI(CARH)
~ ~ tau(CA)
~
~I
th(CLCA)
I
-.1'---1
I
---+J
3
I
_
~~~~~~~~
Figure 39. Block-Write-Cycle Timing (Early Write)
Table 10. Block-Write-Cycle State Table
STATE
CYCLE
1
2
3
Block-write operation (nonmasked)
H
Don't care
Column mask
Block-write operation with nonparslstent write-par-bit
L
Write mask
Column mask
L
Don't care
Column mask
Block-write operstlon with persistent write-par-bit
0: VO write dISable
Write-mask data
1: VO write enable
Column-mask data OOi - OOi + 3
0: column write disable
Q 0, 4, 8, 12)
1: column write enable
=
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Example:
000 - column 0 (address A1 0, AD = 0)
OQ1 - column 1 (address A1 .. 0, AD .. 1)
002 - column 2 (address A1 = 1, AD 0)
OQ3-column 3 (addressA1 1, AD .. 1)
=
=
=
SMJ55166
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MULTIPORT VIDEO RAM
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PARAMETER MEASUREMENT INFORMATION
~
~~
......._...,;,1 14
N,~
it
-.I ¢
I
CAS
14
i4-1cI(RLCL)
IcI(C~ ~
-+I
"'(RWII): :.
~ ..
I
I
I
I
1·1
lh(CLCA)
~((}_
I~
, IcJ(CHRL)
Ij'
~ .1
I
,...-ih(TRG)
I" .
....,
"I
--.I I+-IcJ(CLRH)
~ ~7:;~ ~ ~:;~-: --..r~
1 I. Row
...(SFR) ,
.1 .
tw(RL)P
",_A
-.j
leu(WCH)
I
I
:
:
14-- leu(WCH)
,
. ~
":......, .
"I ...-
_~
I I
-+I 1 1
leu(DWL) t -+l14j- I ~ ih(CLD) t ----+I
i4t Ieu(DQR)
I I4j-- th(WLO) t ----.I
:. 1+ th(ROQ) -.:. ~ leu(DCL) t
OOG-OQ1S
~ I~
2
. . 50(lh(RLO).
3
I
~
~
3
t Referenced to the first falling edge of WEx or the falling edge of CAS, whichever occurs later
NOTE A: To assure page-mode cycle time, TRG must remain high throughout the entire page-mode operation If the late-write feature is used.
If the early Wrlte-cycle timing Is used, the state of TRG is a don't care after ths minimum period ih(TRG) from the failing edge of i!iAS.
Figure 41. Enhanced-Page-Mode Block-Write-Cycle Timing
Table 12. Enhanced-Page-Mode Block-Write-Cycle State Table
STATE
CYCLE
1
2
3
Block-write operation (nonmasked)
H
Don't care
Column mask
Block-write operation with nonpersistent wrlte-per-bit
L
Write mask
Column mask
Block-write operation with persistent write-per-bit
L
Don't care
Column mask
Write-mask data 0: I/O write disable
1: VO write enable
Column-mask data DOi - DQi + 3 0: column write disable
Q 0, 4, 8, 12) 1: column write enable
Example:
DQO - column 0 (address Al 0, AD •
DQl - column 1 (address A1 .0, AD •
002 - column 2 (address A1 • 1, AD •
D03 - column 3 (address A1 • 1, AD •
=
=
~1ExAs
0)
1)
0)
1)
...
INSTRUMENTS
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SGMS057A-APRIL 1895- REVISED JUNE 1895
PARAMETER MEASUREMENT INFORMATION
.1
1oII41------ic(rd)
--------------------~~:r~~---~--~-~----·Jl1
-+I ~ It
fcf(CHR~ -+l1~----·..
:1
CAS~
-.
II
~
I+- ~~H) -+I
..-
II
I 1i441---I.~1-1J1
teu(RA) --il14f--,.~1 I i
(RA)
r~~-
~
~.~~
D
o o - .
D Q 1 5 .
Figure 42. RAS.Only Refresh·Cycle Timing
~1ExAs
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INSTRUMENTS
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PARAMETER MEASUREMENT INFORMATION
~
14--- fw(RH}
ITII~
~~
~I
1
.1
---'
1I~
lcI(cLRL)
eAS~I
~
---+I,'i...~~-=--=--=-~=_fw_(R_L)_
lcI(RHCL)
~ ).1
.-!I'~r
-_-_-_-_-_-_...
11
·11 ~ lcI(RLCH} -+I
\L
:1
1 1
i+--lcI(CHRL) ~
.
i
-+1 I+- It
y
1
1 1
leu(RA) ~11"'f-~.1
1!4
...f--.....ot-l-tt.(RA)
1 1
~
AO-AB~"-_""!"""'I"_ _~
-
11
leu(SFR) ~I"'f-~.I
11oI...I If--.....+I-th(SFR)
DSF~:.:~
DQO-DQ15
Figure 43. CBR-Refresh-Cycle Timing
Table 13. CBR-Cycle State Table
STATE
CYCLE
1
-eBR refresh with option reset
Don't care
CBR refresh with no reset
Don't care
CBR refresh with stop-point set and no reset
Stop address
2
L
3
H
H
H
H
L
-!II TEXAS
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+
PARAMETER MEASUREMENT INFORMATION
~ Memory Read Cycle
Refresh Cycle
~:~ Refresh Cycle -+j
I
I+--tc
~I
I
~ tc(rd)
~I'
(rd)1.-I
I
I~
tw(RH) •
~T
~I
I~
tw(RH)
'-1A~N ~y
"}f
I)
1~.t1
I,
~Ii tcI(CHR~ I
1I
WI I Ii\~!I !i II
II II~~i1U,
I I1I
1 I
I I I ~ 1I+"
I
11-+1
~r.U(CA) I I
~~
-.I :...tI
IIcI(RLCA)
:
~
-.I
I
"'(CLeA)
th(RA)
I
~ ~ r.u(RA) II
AO-AS
I
I I... ~I
I
"'(RA)
IcI(RLCH)
J.r-
'IS:: ~I
I
~I' r.u(RA)
I I
I
I
..u(RA)
I I I
1
I
W-.-
-+I
I
I I
I
+-1-!oI~I--~~1
1I
"'(RA)
I
I -
II II I~ ~II
I
-+l ~ r.u(SFR)
I II I
th(RA)
-+: H;
:IU(SFR)
'-+: :;P:
r.u(SFR)
~';_:~ ~~:r.
-+l r-t
I I
II
rI
I
Y 't.~ ~~
!
I I
l+-*- "'(RHrd)
I I I
-+j
1_
tcll8fCH) --.I
I
r.u(TRG)
~I"'F.°)
I
I
I
I I
II II
tclle(O)
~
II
tcI(GLRH)
II
tt
II II
'\._ _
I h-~--~I~I~I--------~---rI~I------~Jj
I
I
r.U(rd) ~ I
~ t4t- r.u(WMR) I
~ tau(WMR)
-+! ~ tau(WMR)
?
~
I I
~ ,:. . I~I
I
-+I
~ ~3~
~~ ~ 31~ ~~I
"',(RWM)~'
_
_
ta(O)\
I+-
ta(C)
DQ15
~~:,(RWM)
_
'"
3 _
I
~~~
000-
-----c{
Dau
I
out:~
)-
Figure 44. Hldden-Refresh-Cycle nmlng
Table 14. Hldden-Refresh-Cycle State Table
STATE
CYCLE
CBR refresh with option reset
CBR refresh with no reset
CBR refresh with stop-point set and no option reset
1
2
3
Don't care
L
Don't care
H
H
H
H
Stop address
-!llExAs
8-310
'
~:': ~',' ~)(7~~
I I
DSF
I~
II II II. . ~I
r.u(RA)
~I
tc(rd)
I
--+lI !+
It
I
tw(C~ ji:
tcI(CARH)
-+',
_.
~I'
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PARAMETER MEASUREMENT INFORMATION
14
tc(TRD) _ _ _ _ _ _ _ _~.I
-----...,jN
1
14
I4--tcl(RLCL)
tcI(CHRL)
14
~
y~
tcI(RLCH) :
.
14-1- tcI(CARH)
, ,
,,
I
j4- tcI(RLCA) --.I
:
I ~-----__
I.
...-~J 1,4
vwwJ,.
~
tw(RL)
,
0
~
J\
'-----
tw(RH)
I
'
N- --y
:
r1 -":!--F
-l+----tI ~
'I
§§§W( :.(- ~~~~~
fY
tw(SCH)
r
I I
SQ
I..
Old Data
QSF
H
~
=
_~tcI(CASH)
.
HI.z+'---l...1- - - - - - - - - -
I
~ tcI(dLSH)j4
tcI(RLSH)
1
,.
~
~
tw(SCL)
!~\~\\\\~\\\~ ~~tw(sCH) ~',----r:-
j4- ta(SQ)
'h(SHSQ)
I
~"';~"""1~~~,...,..~.,..r$T7'0J"""m"7"lJl!r--tw-(G-H)--.j~~~~~~~
:
tcI(SCTJ:I)
----JJ:
SC
I
" ,
:
DQO-DQ1S
14-
!h(TRG)
t:
I
X
:
.1, I
.
I
ta(SQ)
~ !h(SHSQ)
Old
Da~
=
~SC)
I"
"
1
~ 14- tcI(GHQSF) --.!8
.:
_
,~..- - - - - - tcI(RLQSF)
___
tcI(CLQSF)
~
A
~
New Data
-----Tap Point Bit A7
~
L --------------------------------------------------------------NOTES: A. DQ outputs remain In the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-date-reglster
transfer cycle is used to load the data registers In parallel from the memory array. The 2561ocetions In each data register are wiitten
Into from the 256 corresponding columns of the selected row.
B. Once data is transferred Into the data registers, the SAM is in the serial-read mode (I.e., the SQ Is enabled), allowing data to be
shifted out of the registers. Also, the first bit to read from the data register after TAG has gone high must be activated by a positive
transition of SC.
C. AO-A7: register tap point; AS: Identifies the DRAM row half
D. Early-load operation is defined as th(TAG) min < Ih(TAG) < Id(ALTH) min.
Figure 45. Full-Reglster-Transfer Read Timing, Early-Load Operations
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PARAMETER MEASUREMENT INFORMATION
~
~ lci(RLCL)
- - - -.....
lci(CHRL)
-j4.~--~J
14
~
i
tw(RL)
I
I ~
I
I
I
lci(SCTR)
~.,
--I:~ . ~I1\
fa(SQ)
Old Data
'4
I
ltI(SHSQ) -I414f---~~ I
X
,
I
I
I
I
): \:
'
~ tw(SCL)
Old Data
I
::
.
.:
X.
Vi
\_--I!
~
j4
tc(SC)
14- fa(SQ) ~
ltI(SHSQ)
~~
,4
~"-_ _ _N_'w_D_a_ta_ _
Old Data
V ;'p Point Bit A7
H------------r----------~~====~lci;~~L~QS;F)~===~~.~i------------I...
NOTES: A.
.
14 I
.1 I
I
" 14
.1
lci(THSC)
'HI.z .......I---..jI~---------
I
,
':
QSF
I
I
I
,
I
I
~
1i
~-"":4,---~J!
tw(SCH)
SQ
,
Y
l
DQO-DQ1S
SC
:
~:+- ~~~~~
taU(SFR):4
DSF
~'-_ _
tw(RH)
I..L.!
I : . - lci(RLCA) -+I ~ tw(CL) I
I I4-ltI
-.I
II
I
I
I I (RA) I ......, j4T tau(CA)
tau(RA) -l414-~~ 14-- th(RLCA) ,
,~
I
II
I
~ ~th(C(CA)
AD-AS
,
ytI
lci(RLCH)·
,'
~
~ ..
tc(TRD)
, ~
14-- lci(GHQSF) -.!
lci(RLQSF)
.,
L -------------~-~------------oa
outputs remain in the high-impedance state forthe entire memory-to-data-registertransfer cycle. The memory-to-data-register
transfer cycle Is used to load the data registers in parallel from the memory array. The 256 locations in each data register are written
Into from the 256 corresponding columns of the selected row.
B. Once data Is transferred into the data registers, the SAM is in the serial-read mode ~.e., the sa is enabled), alloWing datil to be
shifted out of the registers. AlsO, the first bit to read from the data register after 'i'RG has gone high must be activated by a positive
transition of SC.
C. AO-A7: register tap point; AS: Identifies the DRAM row half
O. Late load opsretlon Is defined as Id{THRH) < 0 ns.
Figure 46. Full-Reglster-Transfer Read Timing, Real-Time Load Operatlon/Late-Load Operation
8-312
-!!1
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PARAMETER MEASUREMENT INFORMATION
~
----:.iT;- ~(RLCL)
~~~
1 I.
-,
~(CHRL) -l++! I '
1
~(RLCA)
AA,"A'"
1
r-
~(RLCH)
1
I
th(RA) ~
taU(CA)
I+-
lA
.1 ~ tw(RH)
'
l
twIRL)
I.
1
I.
.,
tW(CL)
1
~
-+I
tw(CH)
\
------~
I _ _ _ _ _ _""*'~~~~
Jtl-t-
-+j
'I
1
.1 I
1
t8U(RA)~~11
:
Lo
:~
~jO~TapPolntAO-AS ~
AO-AS
tau(TRG)
-.I
1 1
I ~ 104-~
~III
I
SM Nota A
~II
tau(SFR) ~'
~ ~
~I
I
th(SFR)
"
1
~II
1 -
DSF
taU(wMR)+i,
,
~~~
~_I
W'l.
1
1
DQODQ15
HI-Z--.L.I- - - - - - - - - - -
1
~(MSRL) -l4--~·1 ~(SC)
~(RHMS)
I
+Ii+I '+-- ~(SC) ----+I
1
~-,
SC
Bit 127 or
Blt255 '
SQ
.1
1
~(SCQSF)
X
QSF
TapPolntM
I.
Bit 127 or
BII255
I• •,
1
~(SCQSF)
MSB
Old:~
Tap
PolntN
ta(SQ)
~
X
NewMSB
H
~'
L-----------------~r-------------j
NOTE A: AO-AS: tap point of the given half; A7: don't care; AS: Identifies the DRAM row half
Figure 47. Split-Register-Transfer Read Timing
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PARAMETER MEASUREMENTINFORMATION
~~:-----~---t-------------------------I.,*h(TRG)
...
Jit
1414------Ie(SC)
~
~
14
SC
----iA .
j4
.I
.-.,
~
leeSC)
I
~I
1
sa - - - - _
I
I.
\~'-tSCIl ~rt
~ ih(SHSa)
~~_ _-I.~I-
14j4---1~~I-Iw(SCH)
tweSCH)
la(Sa)
---.,.1
~
\l~
--I
'"
1
It!eSHSa} ---il14t--~~ 1
vm~o~
II
I
I
lw(ScH)
11 \\-__
I_
!'III
la(Sa)
th(SHSa)
I
loll
~
~
1
la(Sa)
---""~ ""~o~
)(Jo----Va-lId,...O-u-t
~ I4-laeSE)
~~I____________________________________~______________
NOTES: A. While reading data through the serial.
SMJ55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS057A- APRIL 1996 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
.
tau(TRG)
14
Iw~CH)
SC
....,1414-----....
~
J.
ft
~
I
_ _--J
-...
~I
SQ
~I
I
~ ~"'1414-:"-----....,-~;=-ih-cr-R-G)---------14~------~~~
~~C)
~I.
~
,'
I~
-"""'X \OJ~ ~ f
I
I
~lcIl.~E)
L
I:'
.,
l
--Va-Ild-O-u-t
--------~)
.J ta~Q)
:4
h~HSQ)
V1,
~
I
~
ta~Q)
,.
~t
I
I4r--~~~I-Iw~CH)
~1f-----I~M--Iw~CH)
I
I
~ ttw(SCL)~ I
~*-tw~CL) ~I!
rr-
~
~I ~
r-- ta~E)
!<
,'-__
~I
POI
t_
.. ~Q)
~ ~ I ih~HSQ)
"'N 0&
)t ....
0&
I
I
I
~_I----------------
NOTES: A. While reading data Ihrough the serial-data register, TRG is a don't care except "i'RG muat be held high when FiAS goes low.
This Is to avoid the initiation of a reglstar-data-transfer operstlon.
B. The serial-data-out cycle Is used to,read data out of the data regiatars. Before data can be read via SQ, the device muat be
put into the read mode by performing a transfer-read cycle.
Figure 49. Serial-Read Timing (SE-Controlled Read)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77261-1443
8-315
SMJ55166
262144 BY 16-81T
MULTIPORT VIDEO RAM
SGMS057A- APRIL.1995 - REVISED JUNE 1995
RAS
PARAMETER MEASUREMENT INFORMATION
,
,.
r,S,'
I ,.-~~,
I.
~~S-
CAS
ADDR
::x::::x::::x==~==~~~
RoWTap1
(low)
TRG
DSF
(hIgh)
'-'
,
---_1--'"
SC
CASE II
SC
,,,
SC
QSF
~F
,,
,
127 (hIgh)
,,
,,
It
~
,
,
,
,
,,255
jj'
.
(lOw)
\
,,
,
,
,
--------~----~,-.--------------~jr-i
127
"
r
j~
-------1-I---~~~~
(low)
127, (high)
It
,
255
jj
I
\
_____\;to...._+I_____""""~
jl""J
,
,
,,
,
,.,
,,,
"
CASElli
(hIgh)
~~~
1,
,
.QSF
,
'j~~S-,
,
Ta p
(lOW),
\
(low)
\~~S--
\.....I
CASE I
QSF
r,~S--
(low)
127
"
r
j~
.
--------------~,-----------~~~~
,
(low)
127' (high)
,
255
(lOw)
127
,
________
\ ___- ;______________~,
,
j
s--?
.
'Split Reglatar to the
Full-Raglater-Tranafer Read ,
High Half of the
,
Data Register
It
j)
,
,
'Split Reglater to the'
,
Low Half of t h e '
,
Data Register,
\
"
r
j~
Spilt Reglatar to tha
High Half of the
Data Reglstar
NOTES: A. In order to achieve proper spilt-register operation. a full-reglster-transfer read should be performed before the first
split-reglster-transfer cycle. This is necessary to Initialize the data register and the starting tap location. First serial access can begin
either after the full-reglster-transfer read cycle (CASE I). during the first spllt-register-transfer cycle (CASE II). or even after the·flrst
split-register-transfer cycle (CASE III). There Is no minimum requirement of se clock between the full-regisler-transfer read cycle
and the first spilt-register cycle.
B. A spilt-register transfer into the Inactive half Is not allowed until fd(MSRL) is met. IdCMSBL) is the minimum delay time between the
rising edge of the serial clock of the last bit (bit 127 or 255) and the falling edge of F!AS of the split-register-transfer cycle Into the
Inactive half. After the Id{MSRL) is met. the spilt-register transfer into the inactive half must aiso satisfy the minimum IdCRHMS)
requirement.Id(RHMS) is the minimum delay time between the rising adge of RAS of the spllt-register-transfer cycle into the Inactive
half and the rising edge of the serial clock of the last bit (bit 127 or 255).
Figure 50. Split-Register Operating Sequence
~1ExAs.
8-316
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS057A-APRIL 1995-REVlSEDJUNE 1995
device symbolization
SMJ55168
F
R
T
-¥-
-¥
~~~
I
I
SpHd (-70. -SO)
Temperature Range
PacugeCode
LotTraceabllltyCode
Date Code
AaeembIySlteCods
DieRsvision Code
WaferFabCode
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77261-1443 ,
8-317
SMJ55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS057A-APRIL 1995-REVISEDJUNE1995
~1ExAs
8-318
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lEXAS 77251-1443
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
•
•
•
•
Organization ••• 16K x 8
Processed to MIL-STD-883, Class B
Single 5-V Power Supply
Pin-Compatible With existing 64K and 128K
EPROMs
• Alllnputs/Outputs Fully TTL-Compatible
• Max AccesslMln Cycle TImes
Vee:to 5%
Vee:to 10%
'27C128-12O
'27C128-15
'27C126·17
'27C128-20
'27C128·25
JPACKAGE
(TOP VIEW)
Vpp
PGM
A7
A6
A13
AS
AS
A9
A11
A4
G
120ns
150ns
170ns
200 ns
250 ns
• HVCMOS Technology
• 30State Output Buffer
• Low Power Dissipation
- Active ••• 138 mW Worst Case
- Standby ••• 1.7 mWWorst Case
(CMOS-Input Levels)
Vcc
1
A12
A10
A1
E
AO
01
17
07
06
05
02
GND
16
04
15
03
00 11
PIN NOMENCLATURE
AO-A13
• 400-mV Minimum DC Noise Immunity With
Standard TTL Loads '
E
• Military Operating Temperature Range
- 55°C to 125°C
PGM
G
GND
00-07
VCC
description
Vpp
Address Inpuls
Chip Enable, Power Down
Output Enable
Ground
Program
Outpuls
5·V Power Supply
12-13-V Power Supply
The SMJ27C128 series is a set of 131 072-bit, ultraviolet-light erasable, electrically programmable read-only
.memories. These devices are fabricated using HVCMOS technology for high speed and simple interfacing with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 54 TTL circuits
without the use of external pullup resistors. The data outputs are tJ1r,ee-state for connecting multiple devices to
a common bus. The SMJ27C128 is pin-compatible with 28-pin 128K ROMs and EPROMs. They are offered In
a 600-mil dual-in-line ceramic package (J suffix) rated for operation from -55°C to 125°C.
Since these EPROMs operate from a single 5-V supply (in the read mode), they are ideal for use in
microprocessor-based systems. One other (12.5 V) supply is needed for programming, but all programming
signals are TTL-level. These devices are programmable by either Fast or SNAPI Pulse programming
algorithms. The Fast programming algorithm uses a VPP of 12.5 V and a Vee of 6 V for a nominal programming
time of two minutes. The SNAPI Pulse programming algorithm uses a Vpp of 13.0 V and a Vee of 6.5 V for a
nominal programming time of two seconds. For programming outside the system, existing EPROM
programmers can be used. Locations can be programmed singly, in blocks, or at random.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON. TEXAS n2SI-I443
Copyrfght C1995, Thxas Instruments Incorporated
8-319
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ"ONLY MEMORY
SOMS006E - AUGUST 1988 - REVISED JUNE 1995
logic symbol t
AD
A1
A2
A3
A4
AS
AS
A7
AS
At
A10
A11
A12
A13
E
G
o'
10
9
8
. EPRONj
16384)('
7
6
6
4
3
25
24
21
23
2
26
20
11
12
13
15
16
17
18
19
AV
AV
AV
AV
AV
AV
AV
AV
> A16~
QO
Q1
Q2
Q3
Q4
Q6
Q6
Q7
13
~WN]
"
22 -;:::-
&
I
EN
tThIs symbol Is In accordance with ANSI/lEEE Sid 91-1984 and lEe Publication 617-12.
operation
The seven modes of op$ration for the SMJ27C128 are listed in the following table. The read mode requires a
Single 5-V supply. All inputs are TIL-level exceptfor Vpp during programming (12.5 V for Fast or 13 V for SNAPI
Pulse) and 12 V on A9 for signature mode.
FUNCTION
(PINS)
MODE
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
(20)
VIL
VIL
VIH
VIL
VIL
VIH
VIL
G
(22)
VIL
VIH
x:I:
VIH
VIL
X
VIL
(27)
VIH
VIH
X
VIL
VIH
X
VIH
Vpp
(1)
Vee
Vee
Vee
Vpp
Vpp
Vpp
Vee
Vee
(28)
vee
Vee
Vee
Vee
Vee
Vee
Vee
x
X
x
x
x
x
VHf
VHf
AO
(10)
X
X
X
X
X
X
VIL
VIH
QO-Q7
(11-13.15-19)
Data Out
HI-Z
Hi-Z
Data In
Data Out
Hi-Z
MFG
DEVICE
97
83
E
PGM
At
(24)
CODE
:I: X can be VIL or VIH.
§VH • 12V:t0.5V.
~1ExAs
8-320
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251,.1443
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMSOO6E -AUGUST 1986 - REVISED JUNE 1996
read/output disable
When the outputs of two or more SMJ27C128s are connected in parallel on the same bus, the output of any
device in the circuit can be read without interference from the outputs of competing devices. To read the output
of the selected SMJ27C128, a low-level signal is applied to the E and G pins. All other devices in the circuit
should have their outputs disabled by the application of a high-level signal to one of these pins. Output data is
accessed at pins 00 through 07.
latchup Immunity
Latchup immunity on the SMJ27C128 is achieved by the application of a minimum of 250 rnA on all inputs and
outputs. This current provides latchup immunity beyond any potential transients at the PC-board level when the
devices are interfaced to industry-standard TTL or MOS logiC devices. Input/output layout approach controls
latchup without compromising performance or packing density.
For more information, see application report SMLA001, Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family, available through TI Field Sales Offices.
powerdown
Active lee supply current can be reduced from 25 mA to 500 j.IA (TTL-level inputs) or 300 j.IA (CMOS-level
inputs) by applying a high input Signal to the E pin. In this mode all outputs are in the high-impedance state.
erasure
Before programming, the SMJ27C128 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 A). EPROM erasure before programming is necessary to assure
that all bits are in the logic 1 (high) state. Logic lows are programmed into the desired locations. A
programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose
(UV intensity x exposure time) is 15 Wos/cm 2. A typical 12 mW/cm2, filterless UV lamp erases the device
in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all
bits are in the high state. It should be noted that normal ambient light contains the correct wavelength for
erasure. Therefore, when using the SMJ27C128, the window should be covered with an opaque label.
SNAPI Pulse programming
The 128K EPROM can be programmed using the TI SNAPI Pulse programming algorithm illustrated by the
flowchart In Figure 1. The TI SNAPI Pulse programming algorithm can reduce programming time to two
seconds. Actual programming time varies as a function of the programming used.
Data is presented in parallel (eight bits) on pins 00 to 07. Once addresses and data are stable, PGM is pulsed.
The SNAPI Pulse programming algorithm uses initial pulses of 100 J.IS followed by a byte verification to
determine when the addressed byte has been successfully programmed. Up to ten 100-J.IS pulses per byte are
provided before a failure is recognized.
The programming mode is aChieved when Vpp = 13 V, Vee = 6.5 V, G = VIH, and E = VIL' More than
one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAPI Pulse programming routine is complete, all bits are verified
with Vee Vpp 5 V.
=
=
Fast programming
The 128K EPROM can be programmed using the Fast programming algorithm illustrated by the flowchart
in Figure 2. During Fast programming, data is presented in parallel (eight bits) on pins aD throGgh a7. Data
is presented in parallel (eight bits) on pins 00 to 07. Once addresses and data are stable, P M is pulsed.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443
0
HOUSTON. TEXASV7261-1443
8-321
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS006c -AUGUST 1988 - REVISED JUNE 1995
Fast programming (continued)
The programming mode Is achieved when Vpp = 12,5 V, Vee = 6 V, G = VIH, PGM = VII.. and E = VIL'
More than one SMJ27C128 can be programmed when the devices are connected in parallel. locations can
be programmed in any order.
Programming uses two types of programming pulses:. prime and final. The length of the prime pulse Is
1 millisecond; this pulse is applied up to 25 times. After each prime pulse, the byte being programmed is
verified. If the correct data is read, the final programming pulse is applied; if correct data is not read, an
additional 1 millisecond pulse is applied up to 25 times. The final programming pulse is 3X long. This
sequence of programming and verification is performed at Vee = 6 V and Vpp = 12.5 V. When the full
Fast programming routine Is complete, all bits are verified with Vee V~p 5 V (see Figure 2).
=
=
program Inhibit
Programming can be inhibited by maintaining a high level input on the E or PGM pin.
program verify
Programmed bits can be verified with Vpp
=12.5 V when G = VIL, E = VIL, and PGM =VIH.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode
is activated when A9 (pin 24) is forced to 12 V :t 0.5 V. Two identifier bytes are accessed by AO (pin 10);
i.e., AO VIL accesses the manufacturer code, which is output on 00-07; AO = VIH accesses the device
code, which is output on 00-07. All other addresses must be held at VIL. Each byte possesses odd parity
on bit 07. The manufacturer code for these devices is 97, and the device code is 83.
=
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, 'IDAS 77251-1443
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMSOO6E - AUGUST1986 - REVISED JUNE 1995
Increment Addre••
Increment
Addres.
Program
Mode
Interactive
Mode
No
Final
I
Figure 1. SNAPI Pulse Programming Flowchart
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
8-323
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMSOOSE-AUGUST 1988 - REVISED JUNE 1996
Ve.
Device
Failed
Increment
Addre..
Figure 2. Fast Programming Flowchart
~1ExAS .
8-324
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
SMJ27C128
131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS008E - AUGUST 1986 - REVISED JUNE 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ........••..••.•.•••••.•.•.•..••••••.•...•..•• -0.6 V to 7 V
Supply voltage range, Vpp (see lIIote 1) ...........••..................•...•......... -0.6 V to 14 V
Input voltage range (see Note 1), All inputs except A9 .•••..••.•...•.•..•...••••••.... -0.6 V to 6.5 V
A9 ............................... -0.6 Vto 13.5 V
Output voltage range (see Note 1) .........•.............•....•.. . . . . . . . . . . . .. -0.6 V to Vee + 1 V
Minimum operating free-air temperature, TA .........•........•........•.•..•.•...•.....•... -55° C
Maximum operating case temperature ........•..•..•.•....•....•...•...•.•••....•.•.••.••. 125° C
Storage temperature range, Tstg .••...................•.•....•...•..•...•••....... -65°C to 150°C
t Stresses beyond those listed under "absolute maxlmum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other cOnditions beyond those indicated under "racommended operating conditions" is not
implied. Exposure to absolute-maxlmum·rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
'27Cl28-15
'27C128-17
'27C128-20
'27C128-25
'27C128-120
VCC
Supply
voltage
MIN
4.75
NOM
5
MAX
5.25
MIN
4.5
NOM
Read mode (see Note 2)
5
MAX
5.5
V
Fast programming algorithm
5.75
6
6.25
5.75
6
6.25
V
SNAPI Pulse programming algOrithm
6.25
6.50
6.75
6.25
6.5
6.75
V
V
12.5
VCC+0.6
13
Read mode (see Noie 3)
VPP
Supply
voltage
VCC-0•6
12
Fast programming algorithm
SNAPI Pulse programming algorithm
VIH
VIL
UNIT
High-level input voltage
Low-level input voltage
TA
Operating free-air temperature
TC
Operating case temperature
TIL
CMOS
TIL
CMOS
12.75
VCC+0.6
12.5
13
13
2
13.25
VCC+1
VCC-0.6
12
12.75
2
13
V
13.25
V
VCC+1
V
VCC-0.2
-0.5
VCC+1
0.6
VCC-0.2
-0.5
VCC+1
0.6
V
-0.5
0.2
-0.5
0.2
V
·C
125
·C
-55
-55
125
V
NOTES: 2. VccmustbeapplledbeforeoratthesametimeasVppandremovedafteroratlhesametimeasVpp. The device must not be inserted
Into or removed from the board when Vpp or VCC is applied.
3. Vpp cen be connected to VCC directly (except in the program mode). VCC supply current in this case is ICC + Ipp.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-325
SMJ27C128
131 072·BIT UVERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS008E - AUGUST 1988 - REVISED JUNE 1995
electrical characteristics over recommended ranges of supply vol_age and operating free-air
temperature
PARAMETER
TEST CONDITIONS
MIN
TVPt.
MAX
UNIT
VOH
High-level output voltage
10H ;, -400 m.A
VOL
Low-ievel output voltage
IOL-2.1 mA
0.4
V
!.IA
!.IA
!.IA
2.4
V
II
Input current (IOkage)
VI-OVto5.5V
:1:1
10
Output current (leakage)
:1:1
IpPl
IpP2
Vpp supply current .
VO=OVtoVcc
Vpp .. Vee .. 5.5 V
Vpp supply current (during program pulse) (see Note 4)
Vpp-13V
ICCl
Vee supply current (standby)
IC02
Vee supply current (active)
I TTL-Input level
I CMOS-Input level
100
35
mA
VCC-5.5V,
E.VIH
50
500
VCC-5.5V,
E-VCC
300
!.IA
!.IA
Vee- 5•5V,
E'-VIL'
25
rnA
tc =minimum cycle time,
10
outputs open
t Typical values are at TA .. 25°C and nominal voltages.
NOTE 4: This parameter has been characterized at 25°C and Is not tested.
capacitance over recommended ranges of supply voltage and operating free-all' temperature,
f = 1 MHz (se. Note 5)
PARAMETER
CI
TVPt
MAX
=1 MHz
8
10
pF
=0 V, f .. 1 MHz
8
14
pF
TEST CONDITIONS
Input capacitance
VI .. 0 V, f
Output capacitance
Co
t Typical values are at TA .. 25°C and nominal voltages.
NOTE 5: Capecltance measuraments are made on sample basis only.
Vo
MIN
UNIT
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Notes 4 and 5)
TEST CONDITIONS
(SEE NOTES 4 AND 5)
PAAAMETER
ta(A)
Access time from address
tatE)
Access time from chip enable
tan(G)
Output enable time from G
Output disable time from G or E,
whichever occurs firstt
ty(A)
.Output data valid time after change of
address, E, or~, whichever occurs flrstt
PARAMETER
ta(A)
Access time from address
tatE)
Access time from chip enable
tan(G)
Output enable time from ~
tells
MIN
MAX
120
'27C128-15
MIN
MAX
MIN
MAX
UNIT
ns
150
170
120
150
170
ns
50
70
70
ns
50
ns
0
50
0
TEST CONDITIONS
(SEE NOTES 4 AND 5)
0
50
0
0
ns
0
'27C128-20
'27C1211-25
MIN
MIN
MAX
200
MAX
UNIT
250
250
ns
200
75
100
ns
80
ns
ns
See Figure 3
Output disable time from Gor E,
whichever occurs flrst*
0
60
Output data valid time after change of address, E, or G,
0
whichever occurs flrst*
* Value calculated from 0.5 V delta to measured level. This parameter Is only sampled and not production-tested.
ty(A)
~1ExAs
8-328
'27C128-17
See Figure 3
tells
)
'27C128-120
INSTRUMENTS
POST OFFICE BOX 1443- HOUSTON. TEXAS.77251-1443
0
0
ns
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMSOO6E-AUGUST1~-R~SEDJUNE1~
recommended timing requirements for programming: Vee = 6 V and Vpp = 12.5 V (Fast) or Vee =
6.5 and Vpp =13 V (SNAPI Pulse). TA = 25°C (see Note 6)
MIN
tells
Disable time, output from G
tanG
tttlA)
Enable time, output from G
Hold time, address
0
tttJPl
Hold time, data
2
MAX
UNIT
130
ns
ns
150
tw(IPGM)
Pulse duration, initial program
Fast programming algorithm
SNAPI Pulse programming algorithm
twlFPGMI
laulA)
Pulse duration, final
Fast programming only
laulGI
!au(D)
NOM
0
0.95
95
2.85
jI8
jI8
1
100
1.05
rna
105
jI8
78.75
me
Setup time, address
Setuptlme,G
2
2
jI8
Setup time, data
2
jI8
jI8
jI8
2
Setup time, VPP
2
jI8
Setup lime, VCC
lau(VCCl
Satuptime, E
jI8
2
IlauCEl
NOTES: 8. For all switching characteristics and timing measurements Input pulselavels are 0.4 V to 2.4 V. Timing measurements are made
at 2.0 V for logic high and 0.8 V for logic low for both Inputs and outputs.
7. Common test conditions apply for Idls except during prcgrammlng.
lau(VPp)
PARAMETER MEASUREMENT INFORMATION
2.08 V
u_"":C--i ........
T'::'
CL-100pF
(sHNoteA)
NOTE A: CL Includes prcbe and fbcIure capacitance.
Figure 3. Output Load Circuit
AC testing Input/output wave forms
2,4
v.1.-._-""'X o.:~
_
0.4 V.
_ _...J
AC testing Inputs are driven at 2.4 V for logic high and 0.4 V for logic low. llmlng measurements are made at
2 V for logic high and O.B V for logiC low for both inputs .and outputs.
~1ExAs
INSTRUMENTS
POST OFFICE sox 1443 • HOUSTON, TEXAS 77251-1443
SMJ27C128
131 072·B11 UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS006E- AUGUST 1986 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
-JX
AO-A13 _ _
X"-_______
Acldre.... Vlllld
1
1
1
1
111
------~II---~
1
1
!
1
14
QO-Q7 - - - HI.z
~--------~------~I
I
1
~ ta(E) -----+j
1
V!r';------.-.,-1 1
~!
I+- tan(G) ...,
~I
«««<
ta(A) .
1y(A)
8-328
I+-- tct..
OutputVIIlki.
Figure 4. Read-Cycle Timing
~1ExAs
1
14
'
INSTRUMENTS
POST OFFICE BOX 1443 • t1ouSlON. TEXAS 77251-1443
--+II
j»»»}
~
H~-
SMJ27C128
131 072·B11 UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMSOO8E- AUGUST 1988 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
AO-A13
00-Q7
Vpp
I'
----./ !I
I
I
I
I
I+---+j tau(VPP):
I
I
I
I
I
I
I
I
Vee
Figure 5. Program-Cycle Timing
~1ExAs
INSTRUMENTS .
POST OFFICE BOX 1443 • HOUSTON,TEXAS 77251-1443
8-329
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS006E - AUGUST 1988 - REVISED JUNE 1995
~1ExAs
8-330
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lEXAS 77251-1443
SMJ27C04O
4194304·81T UV ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
NOVEMBER
JPACKAGE
• Organization ••• S12K x 8
• Single S-V Power Supply
• Industry Standard 32-Pln Dual-in-llne
Package
(TOP VIEW)
• Alllnputs/Outputs Fully TTL Compatible
• Static Operation (No Clocks, No Refresh)
• Max Access/Mln Cycle Time
Vee =*:10"
'27C040-10
'27C040-12
'27C04()..1S
100 ns
120 ns
150 ns
• 8-Blt Output For Use In
Microprocessor-Based Systems
• Power-8avlng CMOS Technology
Vpp
1
Vee
Ale
A1S
A12
A7
Ae
2
5
A18
A17
A14
A13
6
AS
4
AS
A9
A4
All
A3
A2
G
• Latchup Immunity of 250 mA on All Input
and Output Pins
• Military Operating Temperature Range
- 55°C to 125°C
3
Al0
Al 11
AO 12
DCO 13
DCl 14
DC2 15
GND 16
• 3-State Output Buffers
• 400-mV DC Assured Noise Immunity With
Standard TTL Loads
• No Pullup Resistors Required
• Low Power Dissipation (Vee = 5.5 V)
- Active ••• 385 mW Worst Case
- Standby ••• 0.55 mW Worst Case
(CMOS-Input Levels)
-REVISED JUNE 1995
E
DC7
DCe
DCS
DC4
DC3
PIN NOMENCLATURE
AO-A1B
000-007
E
G
GNO
Vee
Vpp
Address Inputs
Inputs (programmlng)/Outputs
ehlpEnable
Output Enable
Ground
5-VSupply
13-V Power Supply t
t Only in program mode
description
The SMJ27C040 is a set of 4194304-bit, ultraviolet-light erasable, electrically programmable read-only
memories (EPROMs).
These devices are fabricated using CMOS technology for high speed and simple interface with MOS and bipolar
circuits. All inputs (including program data inputs) can be driven by Series 54 TTL circuits. Each output can drive
one Series 54. TTL circuit without external resistors. The data outputs are 3-state for connecting multiple
devices to a common bus.
.
The SMJ27C040 is offered in a 32-pin 600-mil dual-in-line ceramic package (J suffix) rated for operation from
- 55°C to 125°C.
Since this EPROM operates from a single 5-V supply (in the read mode), it is ideal for use in
microprocessor-based systems. One other (13-V) supply is needed for programming. All programming signals
are TTL level. For programming outside the system, existing EPROM programmers can be used.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
Copyright C 1995. Texas Instruments Incorporated
8-331
SMJ27C040
.
4194304-BIT UV ERASABLE
PROGRAMMABLE READ-ONLY MEMORY
SGMS048A- NOVEMBER 1992 - REVISED JUNE 1995
logic symbolt
EPROM 524288 X 8
AO
A1
A2
A3
A4
AS
AS
A7
AS
A9
A10
A11
A12
A13
A14
A16
A18
A17
A18
E
12
11
10
8
8
7
8
15
27
28
23
25
4
28
28
3
2
30
31
22
0'"
0
A 524287
T "
24 --;::'
13
14
115
17
18
18
20
21
AV
AV
AV
AV
AV
AV
AV
AV
DQO
DQ1
DQ2
003
DQ4
DQ6
DQ8
DQ7
18
[PWRDWN)
"I
EN
tThls symbol Is In accordance with ANSVIEEE Std 91-1984 and lEe Publication 817-12.
Pin numbers shown are for the J package.
operation
The seven modes of operation are listed in the following table. The read mode requires a single 5-V supply. All
inputs are TTLievel except for Vpp during programming (13 V), and VH (12 V) on A9 for signature mode.
FUNCTION
E
G
Vpp
Vee
Read
VIL
VIL
Vee
Vee
Output Dlseble
VIL
Vee
Vee
Standby
VIH
VIH
X
Vee
Vpp
Vee
A9
AO
x
x
x
Data Out
X
Data In
DQ~Q7
Progrsmming
progrsm Inhibit
VIL
VIH
VIH
VIH
Vpp
Vee
x
x
x
x
x
x
HI-Z
Yeriiy
YIH
YIL
ypp
Vee
x
x
uataOut
Signature Mode
VIL
VIL
Vee
Vee
VIH*
VIL
VIH
Device Code 50
Vee
Hi-Z
HI-Z
MFGCode97
*Xcan be VIL orVIH.
§VH=12V:t0.5V
read/output disable
When the outputs of two or more SMJ27C040s are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from competing outputs of the other devices. To
read the output of a single device, a low level signal is applied to the E and G pins. All other devices in the circuit
should have their outputs disabled by applying a high level Signal to one of these pins. Output data is accessed
at pins 00-07.
-!I1TEXAS
8-332
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS n2S1-1443
SMJ27C040
4194304-BI1 UV ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SGMS046A- NOVEMBER 1992 - REVISED JUNE 1995
latchup Immunity
Latchup immunity on the SMJ27C040 is a minimum of 250 rnA on all inputs and outputs. This feature provides
latchup immunity beyond any potential transients at the P.C. board level when the EPROM is interfaced to
industry standard TTL or MOS logic devices. The input/output layout approach controls latchup without
compromising performance or packing density.
For more information see application report SMLA001, "Design Considerations; Latchup Immunity of the
HVCMOS EPROM FamilY', available through TI Sales Offices.
power down
Active ICC suppllcurrent can be reduced from 70 mA to 1 mA for a high TTL input on E and to 100 tAA for a high
CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure
Before programming, the SMJ27C040 EPROM is erased by exposing the chip through the transparent lid to
a high intensity ultraviolet-light (wavelength 2537 A). The recommended minimum exposure dose
(UV intensity)( exposure time) is 15-W·s/cm2. A typical 12-mW/cm2, filterless UV lamp erases the device in 21
minutes. The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in
the high state. It should be noted that normal ambient light contains the correct wavelength for erasure.
Therefore, when using the SMJ27C040, the window should be covered with an opaque label. After erasure (all
bits in logic high state),logic lows are programmed into the desired locations. A programmed low can be erased
only by ultraviolet light.
SNAPI Pulse programming
The SMJ27C040 and TMS27PC040 are programmed by using the SNAPI Pulse programming algorithm. The
programming sequence is shown in the SNAPI Pulse programming flow chart (Figure 1).
The initial setup is Vpp = 13 V, Vee = 6.5 V, E = VIH, and G = VIH. Once the initial location is selected, the data
is presented in parallel (eight bits) on pins Oa1 through oaa. Once addresses and data are stable, the
programming mode is achieved when E is pulsed low (VII) with a pulse duration of tw(PGM)' Every location is
programmed only once before going to interactive mode.
In the interactive mode, the word is verified atVpp = 13V, Vee =6.5V, E = VIH, andG = VIL.lfthecorrectdata
is not read, the programming is performed by pulling G high, then E low with a pulse duration of tw(PGM)' This
sequence of verification and programming is performed up to a maximum of 10 times. When the device is fully
programmed, all bytes are verified with Vee = Vpp = 5 V ~ 10%.
program Inhibit
Programming can be inhibited by maintaining high level inputs on the E and G pins.
program verify
Programmed bits can be verified with Vpp = 13 V when G = VIL, and E = VIH'
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling AO. All other
addresses must be held low. The Signature code for the SMJ27C040 is 9750. AO low selects the manufacturer's
code 97 (Hex), and AO high selects the device code 50 (Hex), as shown by the signature mode table below.
IDENTlFlERT
PINS
HEX
AO
DQ7
DQ6
DQS
DQ4
DQ3
DQ2
DQ1
DQO
MANUFACTURER CODE
VIL
1
0
0
1
0
1
1
1
97
DEVICE CODE
VIH
0
1
0
1
0
0
0
0
50
t E .. G "VIL, A1-A8 =VIL. A9 =VH. A10-A18 =VIL. Vpp = Vee·
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON.lEXAS 77251-1443
8-333
SMJ27C04O
4194304-BI1 UV ERASABLE·
PR"OGRAMMABLE READ·ONLY MEMORY
SGMS048A- NOVEMBER 1~ - REVISED JUNE 1995
l
Proorem
Mode
Increment Add .....
Increment
Add,...
interactive
Mode
I
FInal
Verification
J
Figure 1. SNAPI Pulse. Programming Flow Chart
~1ExAs
8-334
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lEXAS 77251-1443
SMJ27C040
4194304-BI1 W ERASABLE
PROGRAMMABLE READ-ONLY MEMORY
SGMS048A- NOVEMBER 1882 - REVISED JUNE , .
absolute maximum ratings over operating free..lrtemperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.6 V to 7 V
SUPplYVDltage range, Vpp (see Note 1) ............................................. -0.6Vto 14 V
Input VDltage range (see Note 1), All inputs except A9 ................................ -0.6 V to 6.5 V
AS ..•.•••.••••••.•••.•••••.••••.••• -0.6Vto13V
Output VDlt8ge range, with respect to Vss (see Note 1) •.•••..••..•••.••...•.••.• -0.6 V to Vee + 1 V
Minimum operating free-air temperature ••••••.•••• • • • • • • • • . • • • • • • • • • • • • • • • • • • • • • • • • . • • • • •• - 55°C
Maximum operating case temperature .••.•.•••••••••••••••••.••••••••••• :................... 125°C
Storage temperature range ••••••••••..•••..••.••••••••••••••••••••••••••••••••••• -65°C to 125°C
t Stresses beyond thoaellsted under "absolute maximum ratings" may cause permanent damage to the device. These are 111'8118 ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" II not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device rellabliity.
NOTE 1: All voltage values are with respect to GND.
recommended operaUng conditions
MIN
TYP
MAX
4.5
5.5
V
8.25
8
8.5
8.75
V
Vcc- 0•8
12.75
13
vcc+ 0•8
13.25
V
Read mode (see Nota 2)
Vcc
Supply voltage
Vpp
Supply voltage
VIH
High-level Input voltage
VIL
Low-levellnput voltage
.SNAPI Pulse programming algorithm
Read mode (see Nota 3)
SNAPI Pulse programming algorithm
TA
Operating free-alr temperature
TC
Operating case temperature
TTL
CMOS
TTL
2
VCC- 0•2
-0.5
VCC+0•5
VCC+0•5
0·8
0.2
-0.5
CMOS
UNrr
V
V
V
·C
-55
125
·C
NOTES: 2. Vcc muat be applied before oratlhesametime as Vppand removed aftarorllIthesametime asVpp. Thedevice mull not be Inserted
Into or removed from the board when Vpp or Vcc Is applied.
3. Vpp can be connected to VCC directly (eXcept In the program mode). Vcc supply current in this case would be ICC + Ipp.
During programming, Vpp musfbe maintained at 13 V:I: 0.25 V.
.
electrical characteristics . over recommended ranges of supply voltage and operating free-alr
temperature
PARAMETER
TEST cONDmONS
MIN
MAX
VOH
High-level output voltage
VOL
Low-level output voltage
10H - - 400 \&A
IOL-2.1 mA
II
Input current 088kage)
VI-OVto5.5V
0.4
:1:1
10
IpP1
Output current Oeakage)
VO·OVtoVCC
:1:1
Vpp supply current
Vpp .. VCC. 5.5 V
IpP2
Vpp supply current (during program pulse) (see Note 4)
Vpp -12.75 V,
TA-25·C
I TTL-Input level
VCC=5.5V,
I CMOS-Input level
VCC .. 5•5V,
E"VIH
E .. VCC
ICC1
1CC2
VCC supply current (standby)
2.4
VCC- 5•5V
iE-VII..
!cycle. minimum cycis time,
outpute open (_ Nota 5)
VCC supply current (active)
UNrr
V
10
V
\&A
\&A
\&A
50
1
100
mA
50
mA
mA
\&A
NOTES: 4. This parametar II only sampled and not 100% tested.
5. Minimum cycle time .. maximum access time.
~/~
~1ExAs
.
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-335
SMJ27C040
4194304·BIT UVERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SGMS048A- NOVEMBER 1992 - REVISED JUNE 1995
capacltanc. ov.r recommend.d rang.s of supply voltag. and op.ratlng fr....lr t.mperatur••
f= 1 MHz (Vee Vpp SV:I: O.S V)t
.
=
=
PARAMETER
CI
. TVP*
MAX
VI-OV
4
8
pF
VO-OV
8
12
pF
TEST CONDIi'IONS
Input capacitance
Oulput capacitance
Co
. t Capacitance Is sampled only at Initial design and after any major change .
All typical values are at TA = 25°C and nominal voltages.
..
*
MIN
UNIT
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Notes 7 and 8)
TEST
CONDITIONS
(SEE NOTE
lAND 7)
PARAMETER
talA)
talE)
Access time from address
Access time from chip enable
tan(G)
Output enable time from G
!dIs
Output disable time from G or E, whichever occurs
first (see Note 8)
'27C040-12
'27C040-10
'27C040-15
UNIT
MIN
(see Figure 2)
Input tr s 2d ns
Input If s 20 ns
MAX
MIN
MAX
MIN
MAX
100
100
120
120
150
150
50
50
50
ns
ns
ns
50
ns
0
50
0
50
0
O'!!Put data valid time after change of address,E,
ns
0
0
0
or G, whichever occurs first (see Note 8)
NOTES: 6. For all switching characteristics the Input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (Figure 2)
7. Common test conditions apply for !dis except during programming.
.
8. Value calculated from 0.5-V delta to measured output level. This parameler Is only sampled and not 100% tested.
1y(A}
switching characteristics for programming: Vee = 6,S V and Vpp = 13 V (SNAP I Pulse). TA = 2SoC
PARAMETER
!dI!l(G)
Output disable time frOm G
tan (G)
Output enable time from G
MIN
MAX
0
100
150
UNIT
ns
ns
recommended tIming requirements for programming: Vee = 6•.S V and Vpp = 13 V (SNAPI Pulse).
TA = 2SoC, (see Note 6)
MIN
1h1A)
Hold time, address
0
lh(Dl
Hold time, data
2
IwIPGM}
Pulse duration, program
taulA)
Setup time, address
tau(E)
Setup time, E
2
ta~Gl
taulD}
Setup time, G
2
Setup time, data
2
tau(VPP}
Setup time, VPP
2
I SNAPI Pulse programming algorithm
95
2
TYP
100
MAX
105
UNIT
J.IS
J.IS
J.IS
J.IS
J.IS
J.IS
J.IS
J.IS
J.IS
2
tau(VCC) Setup time, VCC
NOTE 6: For all switching characteristics the Input pulse \evels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logiC logl,c low. (FIgure 2)
~TEXAS
8-336
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON; TEXAS 77251-1443
SMJ27C040
4194304-BIT UV ERASABLE
PROGRAMMABLE READ-ONLY MEMORY
SGMS048A- NOVEMBER 1992 - REVISED JUNE 11186
PARAMETER MEASUREMENT INFORMATION
2.08 V
Output
UnderTHt
----i
RL· 800 g
I
CL=100pF
(eeeNoteA)
NOTE A: CL includes probe and fixture capacitance.
2.4V
----~V
O.4V
------'1\;
:.:v
O.:~XI;.
_____
. Figure 2. Output Load Circuit and Input/Output Wave Forms
AO-A18
~
~
\
I
14--
I
I
I
I
l!
}1
I I
I I
ta{E) ~
I
I
I
\
:.- ten(G)
HI-Z
I
I
I
~
ta(A)
E
DOG-DQ7
X
Addresse. valid
---I
«~~~
I I4--ldla ~
ty(A) ~
Output valid
.
I
i}~}»- HI-Z-
Figure 3. Read-Cycle Timing
~ThxAs' .' .
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
8-337
SMJ27C04O
4194304-BIT UV ERASABLE
PROGRAMMABLE READ-ONLY MEMORY
SGMS048A- NOVEMBER 1812- REVISED JUNE· i885
PARAMETER MEASUREMENT INFORMATION
14-1111----Verlfy ----tl~
I
..
~--- Progmll ---tl~
AO-A18
DQO-DQ7
vppt
=xI.---.t-
'""7-
"u(A)
--~( oa..lnSta~..
I.--../-I -(D)
.-Ji~I
I
I
Z.
"u(E)
J
I
~ "U(VCC) I
_I
I
)- H~-4-!...' ~( D:~b~~ )1-------
"U(VPP)
--./ HL
.
~(G)
I
I
I
I
tw(pGM)
I
~
III
14
I
14
I
II
II
II
II
I
I
"'(0)
-----'--/ I
I
X=
14--"'(A) ~
I
I
I I
fdla(G)
I
I
I
14-l1li_-I~II-+I-
~
!
"U(G)
.
I
I
~~I _ _~/----------
t 13-V VPP and I.SoV vee for SNAPI Pulse programming.
Figure 4. Program-cycle Timing (SNAPI Pulse Programming)
~.1EXAs
.
INSTRUMENTS
POS1' OFFICE BOX 1_ • HOUSTON. TEXAS 77251-1_
9-1
Contents
CHAPTER 13.
MECHANICAL DATA
MOS Memory Commercial
AD (R-PSIM-N30)' SINGLE-IN-L1NE MEMORY MODULE ••••••••••••••••••••. '. • . . • . • . . • • . . . • • . • . . . • • .. 9-5
BK (R-PSIM-N72) SINGLE-IN-UNE MEMORY MODULE •.•.••.•••. : .•. ; • . . . • • . • • • . . • • • • • • • . • • • • • • • • •• 9-6
BK (R-PSIM-N72) SINGLE-/DOUBLE SIDED-IN-UNE MEMORY MODULE •.•.•••••••.••..••..•....•..• 9-7
BK (R-PSIM-N72) DOUBLE-SIDED SINGLE-IN-UNE MEMORY MODULE ••..••..•••.••.•••..•••.•.•••• 9-8
BK (R-PSIM-N72) SINGLE-/DOUBLE-SIDED SINGLE-IN-UNE MEMORY MODULE ••••••••••.•••.•..•.• 9-9
BM (R-PSIM-N72) SINGLE/DOUBLE-SIDED IN-UNE MEMORY MODULE •••.•...•...•..•••••••••••.•. 9-10
DBJ (R-PDSO-G44) PLASTIC SMALL-OUTUNE PACKAGE •.•..•..•••••...............•....•...•...• 9-11
DBR (R-PDSO-G56) PLASTIC DUAL SMALL-OUTLINE PACKAGE •••.••.•••..•....••.....•...••..••. 9-12
DO (R-PDSO-G32) THIN SMALL-OUTUNE PACKAGE .•....•.....•.••.•••.•••.•••.••.••••••••••••.• 9-13
DGA (R-PDSO-G20/26) PLASTIC SMALL-OUTUNE PACKAGE •.•••••••••••••••••••••.•.••...•.•••.. 9-14
DGA (R-PDSO-G24/26) PLASTIC SMALL-OUTLINE PACKAGE ••.•••..•......••..••...•....•..•••..• 9-15
DGC (R-PDSO-G32) PLASTIC SMALL-OUTUNE PACKAGE .•••..••••.•.•••••••••••••••.••••••••.... 9-16
DGE (R-PDSO-G40/44) PLASTIC SMAlL-OUTUNE PACKAGE .•....••..••.••..••..••.•.•••••••••.•• 9-17
'oGE (R-PDSO-G44/50) PLASTIC SMALL-OUTUNE PACKAGE •••.•••••••••.•••.•••..••.••..•••••••• 9-18
DGE (R-PDSO-G44) PLASTIC SMALL-OUTUNE PACKAGE •.•.•..•.•..••.••..••.••••.•.••••••.••••• 9-19
DGH (R-PDSO-G64) PLASTIC SMALL-OUTUNE PACKAGE ......................................... 9-20
OJ (R-PDSO-J20/26) PLASTIC SMALL-OUTUNE J-LEAD PACKAGE •.•...•••.•••••••.••••••••.•••.•• 9-21
OJ (R-PD$O-J24/26) PLASTIC SMALL-OUTUNE J-LEAD PACKAGE •.••••••••••••••••••••••••.•.•••• 9-22
DZ (R-PDSO-J32) PLASTIC SMALL-OUTUNE J-LEAD PACKAGE ••...•.•••.•••••••.••••••••••.•.•••• 9-23
DZ (R-PDSO-J40) PLASTIC SMALL-OUTUNE J-LEAD PACKAGE •••••••••••••••••••••••••••••••••••• 9-24 '
DZ (R-PDSO-J42) PLASTIC SMALL-OUTUNE J-LEAD PACKAGE •••.•••••••••• ,: •••.••••••••••••••••• 9-25
FM (R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER ••••••••••••••••••••••••••••••••••..•••••••• 9-26
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER •••••••.••••••••••••.••.•.••••.••••••••.••••• 9-27
J (R-CDIP-'f'I'*) CERAMIC SIDE-BRAZE DUAL-IN-~INE PACKAGE ..•.••.••••.••••.••.•.•.•••.••.••••• 9-28
N (R-PDIP-'f'I'*) PLASTIC DUAL-IN-UNE PACKAGE ••.••..•....•.•.••..•...••.•••.••••••.•••.•.•..•• 9-29
U (R-PSIM-N30) SINGLE-IN-UNE MEMORY MODULE ••.•.•..••••..•...•..•...•..••.•••.••••••...•. 9-30
~TEXAS
9-2
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 772l!1-1443
MOS Memory Military
FNC (R·CDCC-N24/28) LEAD LESS CERAMIC CHIP CARRIER ...............••...•...••..••...•..•. 9-31
FQ (R·CDCC·N20) LEAD LESS CERAMIC CHIP CARRIER ........................................... 9·32
GB (S·CPGA·P68) CERAMIC PIN GRID A~RAY PACKAGE ......•.••••..•...•...•••..•...••.••••..•. 9-33
HJ (R·CDCC-J20) J·LEADED CERAMIC CHIP CARRIER ••..••................•.................•.•. 9·34
HJ (R·CDCC-J28) J·LEADED CERAMIC CHIP CARRIER .••....•.••.•.......•..••..•.•..•.....•..•.. 9·35
HK (R·CDFP·F20) CERAMIC DUAL FLATPACK ...........•....•...•.............•..•••...•.•••••.• 9·36
HKB (R·CDFP·F28) CERAMIC DUAL FLATPACK ...••..••..•....••...••..•.•..••.•••...•••..••.••.. 9·37
HKC (R·CDFP·F64) CERAMIC DUAL FLATPACK WITH TIE BAR ...•...........•..•...•••...•...••..• 9·38
HKD (R·CDFP·F50) CERAMIC DUAL FLATPACK ..............••..•••......•.•...•..••...••..••.••• 9-39
HL (R·CDCC·N20/26) LEADLESS CERAMIC CHIP CARRIER ..•••.•••••..••••••••••••••.•••••.•••••• 9·40
HM (R·CDCC·N28) LEAD LESS CERAMIC CHIP CARRIER .••.•..••.•.•...•....•...••....•...••..•.. 9·41
HR (R·CDFP·F20) CERAMIC DUAL FLATPACK ..................................•.•..........•..•• 9·42
J (R·CDIP·T**) CERAMIC SIDE·BRAZE DUAL·IN·L1NE PACKAGE .•....•........•............•....... 9·43
JD(R·CDIP·T**) CERAMIC SIDE·BRAZE DUAL·IN·L1NE PACKAGE (400 MIL) •....•...••.......•....••. 9·44
JD (R·CDIP·T**) CERAMIC SIDE·BRAZE DUAL·IN·L1NE PACKAGE (300 MIL) ..••.••...•..••••••••••.• 9-45
JD (R·CDIP·T**) CERAMIC SIDE·BRAZE DUAL·IN·L1NE PACKAGE (600 MIL) ..•.......•.......•.••••• 9·46
JDB (R·CDIP·T"*) CERAMIC SIDE·BRAZE DUAL·IN·L1NE PACKAGE •...•....•...•...........•......• 9-47
SV (R·CZIP·T**) CERAMIC ZIG·ZAG PACKAGE ...........................................•..•.•.•• 9·48
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
Each package drawing contains a JEDEC Std 30 descriptor in the title line. This descriptor uses the following
convention: shape, material, terminal position, package outline, lead form, and terminal count. The codes for
each element in the JEDEC Std30 descriptor are as follows:
SHAPE
O-round.
R - rectangular
MATERIAL
C - ceramic, metal
M-metal
G - ceramic, glass
P-plastlc
TERMINAL POSmON
B-bottom
L-lateral
S-square
X-other
Q_quad
T-trlple
D-dual
P - perpendicular
S-single
Z-zig-zag
PACKAGE OUTLINE
CC - chip carrier
FM - flange mount
GA - grid arrey
SO - small outline
CY - cylinder or can
FP-flatpack
IP-in-line
1M - in-line module
LEAD FORM
F -flat
J-J laad
P-pin/peg
W-wire
G-gullwing
N-no lead
T - through-hole
TERMINAL COUNT
One, two, or three digits as appropriate
-!fTEXAS
INSTRUMENTS
POST OFFICE BOX 1443'· HOUSTON, lEXAS 77251-1443
R -
P DS 0
T
J
-
G XXX
Mechanical Data
'MOS Memory Products - Commercial
AD (R-PSIM-N30)
SINGLE-IN-L1NE MEMORY MODULEt
--------r
3.505(89,03)
3.495 (88,77)
------:------.t
0.125 (3,18) TVP
0.133 (3,38) TVP
l
0.805 (20,45)
0.796 (20,19)
JL
~~
~
0.100(2,54)
I
0.400 (10,16) TVP
~ ~ 0.054 (1,37)
0.047 (1,19)
0.070 (1,78) TVP
4040192/B 10/94
NOTES: B. All linear dimensions are In Inches (millimeters).
C. This drawing Is subject to change without notice.
t Applicable MOS Memory Devlcas:
TM41OOGAD8
TM4100EAD9
~1ExAs
.
INSTRUMENTS
POST OFFICE SOX 1443 • HOUSTON. TEXAS 77251-1443
Mechanical Data
MOS Memory ~roducts - Commercial
\
BK (R-PSIM~N72)
SINGLE-IN-LiNE MEMORY MODULEt
4.255(108,08)
4.245 (107,82)
r
---------~I
,•
0.054(1,37)
0.047 (1,19),
0.125 (3,18) TYP
l'r
,
~~~----------------------------~---~f
1.005 (25,53)
0.895 (25,27)
(£)+--7"
JL-J
~
0.050 (1,27)
-J I.-
0.128 (3,25)
0.120 (3,05)
0.400 (10,18) TYP
0.040 (1,02) TYP
0.208 (5,28) MAX
l
4040226/B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to chenge without notice.
t Applicable MOS Memory Devices:
TM497BBK32
TM497BBK32S
~I1. TEXAS.
NSTRUMENTS
POST OFFICE BOX t443 • HOUSTON, TEXAS 77251-1443
Mechanical Data
MOS Memory Products - Commercial
BK (R-PSIM-N72)
r
SINGLE-/DOUBLE-SIDED IN-LINE MEMORY MODULEt
4.255 (108,08)
4.245 (107,82)
.~r~lr
l
0.125 (3,18) TVP
0.047 (1,19)
f
1.005 (25,53)
0.995 (24,28)
(£)
JL j~_(I~
-J I.-
0.128 (3,25)
0.120 (3,05)
0.400 (10,16) TVP
0.040 (1,02) TVP
0.208 (5,28) MAX
0.360 (9,14) MAX
l
4040197/810184
NOTES: A All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
t Applicable MOS Memory Devices:
TM124BBK32
TM124MBK36B .
TM124MBK36C
TM124BBK32S
TM124MBK36R
TM124MBK36S
TM248CBK32
TM248NBK36B
TM248NBK36C
TM248CBK32S
TM248NBK36R
TM248NBK36S
~1EXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
9-7
Mechanical Data
MOS Memory Products - Commercial
BK (R-PSIM-N72)
DOUBLE-SIDED SINGLE-IN-LiNE MEMORY MODULEt
40401874/A4/iI
NOTES: A. All linear dimensions are In Inches (millimelers).
B. This drawing Is subject to change without notice.
t Appllceble MOS Memory bevices:
'
TM893CBK32
TM893CBK32S
TM497MBK36A
TM497MBK380
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUlTON. TEXAS Tl2S1-1443
Mechanical Data
MOS Memory Products - Commercial
BK (R·PSIM·N72)
r
SINGLE·/DOUBLE·SIDED SINGLE·IN·LINE MEMORY MODULEt
4.255 (108,08)
4.245 (107,82)
~:;g:.:
l
0.125 (3,18) TVP
lr
f
1.005 (25,53)
0.895 (24,28)
~
JL j~.,..~~
I
-J I.-
0.128 (3,25)
0.120 (3,05)
0.400 (10,16) TYP
0.040 (1,02) TYP
0.208 (5,28) MAX
0.360 (9,14) MAX
l
4040197-3/A 4195
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
t Applicable MaS Memory Devices:
TM124BBK32F
TM124BBK32U
TM248CBK32F
TM248CBK32U
TM124MBK36F
TM124MBK36U
TM248NBK36F
TM248NBK36U
-!i11ExAs
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77261-1443
TM124MBK36G
TM124MBK38V
TM248NCK36G
TM248NBK38V
Mechanical Data
MOS Memory Products ~ Commercial
BM (R·PSIM·N72)
SINGLE/DOUBLE-8IDED IN·UNE MEMORY MODULEt
.... 0"..., ---------~I•
.:o...:.ij
4.255 (108,08)
r
0.125 (3,18) TVP
0054 (137)
I
lr
1.305 (33,15)
1.295 (32,89)
(f)+-.- o r
JL-J H
0.050 (1,27)
I
-J I.-
0.128 (3,25)
0.120 (3,05)
0.400 (10,18) TYP
0.040 (1,02) TVP
0.208 (5,28) MAX,
l
0.380 (9,14) MAX -Iot--+I
4088175/A 00/95
NOTES: A All linear dimensions are in inches (millimeters).
B. This drawing Is subject to change without notice.
t Applicable MOS Memory Devices:
TM893NBM36A
TM893NBM36Q
TM497MBM36A
TM497MBM36Q
~1ExA.s
INSTRUMENTS
9-10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
Mechanical Data
MOS Memory Products - Commercial
DBJ (R-PDSO-G44)
PLASTIC SMALL-OUTUNE PACKAGEt
1r-
44
0,451.1
0,35
0,16
®I
I-Z...L.....;:~.=J
23
'T"'TT"T'I"'~jj
ll4'------2 ~J
.."..."...,.,0
28,30 _ _ _ _ _ _ _
28,10
rr,,85
~
MAX
0,50 MI:Y
4073325/A 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
t Applicable MOS Memory Devices:
TMS28F200BZT
TMS28F200BZB
TMS28F400BZT
TMS28F400BZB
-!/} TEXAS
INSTRUMENTS
POST OFFICE BOX 14-13 • HOUSTON, TEXAS 77251-14-13
9-11
Mechanical Data
,MOS Memory Products -- Commercial
DBR (R-PDSo-G56)
PLASTIC DUAL SMALL-OUTUNEPACKAGEt
~--~~--------------------------~=M
o
o
---1
--y
0.553 (14,05)
0.549 (13,95)
---1
t
~
0.020 (0,50)
o
0.010 (0,25)
0.004 (0,10)
I
I-$-I 0.008 (0,21) @I
0
__~~__________________________-J=~
1~4 ~_____
H ..__
I
0.726 (18,44) _ _ _ _-+l~
0.722 (18,35)
1ir
0.014(0,35)
0.012 (0,30)
0.047 (1,20) MAX ]
t--UP<--------~
~'ooooooJhooooooo'-,
-+11• ==========
1
0.006 (0,15)
NOM
.,.
0.791 (20,10) _ _ _ _ _
0.784 (19,90) .
1
0.005 (0,13) MIN
4073302IA 10/94
NOTES: A. All linear dimensions are In Inches(mililmeters).
B. This drawing Is subject to change without notice.
t Applicable MaS Memory Devices:
TMS28F200BZT
TMS28F200BZB
TMS28F400BZT
TMS28F400BZB
~TEXAS .
INSTRUMENTS
9-12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
Mechanical Data
MOS Memory Products - Commercial
THIN SMALL-OUTLINE PACKAGEt
DD (R·PDSO-G32)
,
1
....................................................
~--~~
o
~~
--.!
Y
0.050 (1,27)
I
--.!
t.
....................................................~17
~--~~
18
114l1li---------
0.728 (18,44) _ _ _ _
0.724 (18,38)
~~
e:::"
0.047 (1,20) MAX
1111111
1
t.,.
404OCI87/B 10184
NOTES: A. All linear dlrnens/ona are in Inches (millimeters).
B. This drawing is aubjec:t to change without notice.
t Applicable MOS Memory Devices:
TMS28F512A
TMS28F020
TMS28F010B
TMS27C512
TMS27PC512
TMS28C01OA
TMS27PC01OA
~1ExAs
INSTRUMENTS
POITOFFICE BOX 1443 • HOUSlOH. TEXAS 77251-1443
9-1$
(
Mechanical Data
MOS Mem~ Products - Commercial
DGA (R-PDSO-G20/26)
'1 r- ~:: :i:~ 1.1
PLASTIC SMALL-oUTUNE PACKAGEt
0.008 (0,21)
®1
T
0.371 (9.42)
0.365 (9.02)
0.304 (7.72)
0.296 (7.52)
~~~I'T"""TT".I~
13
0.879 (17,24)
0.671 (17.04)
f bEiU:IUOIu:U:ujjo==SOCWIIu:U:ujju:U:dLJ..:L·
0.047 (1.20) MAX
0.000 (0.00) MIN]
....,.-J 0~=====3l
10.1 0.004 (0.10) ~
4040261S4/C 4/86
NOTES: A, AU linear dimensions are in inches (millimeters).
B. This drawing Ie subject to chenge without notice.
C. Body dimensions do not include mold flash or protrusion.
t Applicable MaS Memory Devices:
TMS44100
TMS46400
TMS44100P
TMS46400P
TMS461 00
TMS46100P
~ThxAs
INSTRUMENTS .
9-14
POST OFFICE BOX 1443 • HOUSTON.ll:i
1""""'1 . ......., ,...,
·
,...,
,...,
,...,
,...,
,...,
o
)
1
13
,...,
c
Lens Protrusion
0.010 (0,25) MAX
~
DIM
A
8
C
24
NARR
28
WIDE
NARR
40
32
WIDE
NARR
WIDE
NARR
WIDE
MAX
0.624(15.85) 0.624(15.85)
0.624(15.85) 0.624(15.85)
0.624(15.85) 0.624(15.85)
0.624(15.85) 0.624(15.85)
MIN
0.590(14.99) 0.590(14.99)
0.590(14.99) 0.590(14.99)
0.590(14.99) 0.590(14.99)
0.590(14.99) 0.590(14.99)
MAX
1.265(32.13) 1.265(32.13)
1.465(37.21) 1.465(37.21)
1.668(42.37) 1.668(42.37)
2.068(52.53) 2.068(52.53)
MIN
1.235(31.37) 1.235(31.37)
1.435(36.45) 1.435(36.45)
1.632(41.45) 1.632(41.45)
2.032(51.61) 2.032(51.61)
MAX
0.541(13.74) 0.598(15.19)
0.541 (13.74) 0.598(15.19)
0.541 (13.74) 0.598(15.19)
0.541(13.74) 0.598(15.19)
MIN
0.514(13.06) 0.571 (14.50)
0.514(13.06) 0.571 (14.50)
0.514(13.06) 0.571 (14.50)
0.514(13.06) 0.571 (14.50)
4040084/810/94
NOTES: A. All linear dimensions are In inches (millimeters).
B. This drawing is subject to change without notice.
- C. This package can be hermetically sealed with a ceramic lid using glass frlt.
D. Index point Is provided on cap for terminal identification only on press ceramic glass frit seal only
t Applicable MOS Memory Devices:
TMS27C256
TMS27C040
TMS27C510
TMS27C240
TMS27C512
TMS27C010A
~TEXAS
9-28
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251~1443
TMS27C210A
TMS27C020
Mechanical Data
MOS Memory Products - Commercial
PLASTIC DUAL-IN-LiNE PACKAGEt
N (R-PDIP-T**)
24 PIN SHOWN
A
0.560 (14,22)
0.520 (13,21)
~~~~
12
0.200 (5,08) MAX
0.020 (0,51) MIN
~---r-IJL
JL
Seating Plane
~0.1OO(2,54)1
0.125(3,18) MIN
0.021(0,53) 1-$-1 0.010 (0,25) @ 1
0.015 (0,38) "'--1.._---'-...;........;'--"'_«...1.
0.010 (0,25) NOM
L...
~
24
28
32
40
48
52
A MAX
1.270
(32,26)
1.450
(36,83)
1.650
(41,91)
2.090
(53,09)
2.450
(62,23)
2.650
(67,31)
A MIN
1.230
(31.24)
1.410
(35,81)
1.610
(40,89)
2.040
(51,82)
2.390
(60,71)
2.590
(65,79)
DIM
4040053/810/94
NOTES: A. All linear dimensions are In Inches (millimeters).
B. This drawing Is subject to change without notice.
C. Falls within JEDEC MS-Oll
D. Falls within JEDEC MS-015 (32 pin only)
t Applicable MOS Memory Devices:
TMS28F512A
TMS27PC010A
TMS28F010B
TMS28F210
TMS27PC256
TMS27PC510
TMS27PC512
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
9-29
Mechanical Data
MOS Memory Products - Commercial
U (R·PSIM.N30)
SINGLE·IN·LlNE MEMORY MODULE*
3A85 (88,77)
3.&015(89,03)
r
~.~
0.125 (3,18) TYP
0.133 (3,38) TVP
'l r=I
0.655 (18,84)
MAX
JL
~~
~
0.100 (2,54)
I
0.400 (10,18) TVP
~ ~ 0.054
(1,37)
0.047 (1,19)
0.070 (1,78) TYP
4040193/B 10/94
NOTES:, A. All linear dimensions are in Inches (millimeters).
B. This drawing is subject to change without notice.
t Applicable MOS Memory DevIces:
,
TM497GU8
TM497EU9
-!11 TEXAS
INSTRUMENTS
POST OFFICE BOX 10143 • HOUSTON. TEXAS 77251-10143
Mechanical Data
MOS Memory Products - Military
LEAOLESS CERAMIC CHIP CARRIERt
FNC (R-COCC-N24128)
j4--
I
0.480 (11,88)
0.440 (11,18)
1
1
0.785 (19,94)
0.785 (19,43)
0.036 (0,89) MIN
12
0.008 (0,20) RAD TVP
0.125 (3,18)
0.105 (2,87)
4040142/B 10/84
NOTES: A. All linear dimensions are In Inches (millimeters).
B. This drawing Is subject to change without notice.
C. This package can be hennetlcelly sealed with a metal lid.
D. The tennlnals are gold plated.
t Applicable MOS Memory Military DevIces:
SMJ418100
SMJ418400
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 772t51-1443
9-31
Mechanical Data
MOS Memory Products - Military
LEADLESS CERA~IC CHIP CARRIERt
FQ (R-CDCC-N20)
n
0.885 (17,40)
0;&65 (18,88)
I
r-
0.357 (9,07)
0.343 (8,71)
I
0.030 (0,78) MIN
~
r
0.008 (0,20) RAD TVP
0.808 (15,44)
G.592 (1S,G4)
L
0.080 (2,28) TVP --I~'"
4040143/B 10/84
NOTES: A All lineal' dimensions are In Inchee (millimeters).
B. This drawing Is subject to change without notice.
C. This package can be hermetically sealed with a meteilid.
D. The ~rmlnals are gold plated.
t Applicable MOS Memory Military DevIces:
SMJ44C258
SMJ4C1024
·~/;a
~.1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lelCAS 77261-1443
Mechanical Data
MOS Memory Products - Military
j
GB (S-CPGA-P68)
CERAMIC PIN GRID ARRAY PACKAGEt
rra~-
0.960 (24,13)
I
D
1F
0
t
0.184 (4,88)
0.166 (4,16)
I
r--
0.536 (13,61)
0.524 (13,31)
lal"~'"
I
f
0.800 (20,32) TYP
1
J
0
0
0
0
0
0
0
0
H
o
@)
0
0
0
0
o
@)
0
G
0
0
o
0
0
0
0
0
0
F
0
0
E
0
0
0
D
0
0
0
c
0
0
0
0
B
o
@)
0
0
A
0
0
0
0
1
234
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o
@)
0
0
0
0
0
0
567
8
8
0.088 (2,23)
0.072 (1,83)
L
0.055 (1,39)
0.045 (1,14)
4040114-14/A 2/95
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Index mark may appear on top or bottom depending on package vendor.
Pins are located within 0.005 (0,13) radius of true position reletive to each other at maximum material condition and within
0.015 (0,38) radius relative to the center of the ceramic.
E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
F. The plns can be gold plated or solder dipped.
G. Falls within MIL-8TD·1835 CMGA1-PN and CMGA13-PN and JEDEC MO-067AA and MO-068AA, respectively
t Applicable MOS Memory Military Devices:
SMJ55161
SMJ55166
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON, TEXAS 77251-1443
9-33
Mechanical Data
MOS Memory Products -- Military
J-LEADED CERAMIC CHIP CARRIERt
HJ (R-CDCc-J20)
(17,40)
14------- 0.685
0.685 (16,89) ------+\
0.608 (15,44)
0.592 (15,04)
------.ti ...~
_
0.048 (1,22)
0.028 (0,71)4 Places
11
20
0.338 (8,59)
~:::;;::;;;:~;:::====:::;;::::;;::;;::;;::::;~LJ1~
10
0.102 (2,59).
0.056 (1,42)
0,.1.044;::::(=1,1=2=)===========0=.080=(2::;:J,,03a .
1t
0.010 (0,25)
.
.~=O='OO6=(O='1=6)='
---'t
===;1,
0.137 (3,48)
0.114 (2,90)
~
0.050 (1,27)
I
0.022 (0,56)
0.012 (0,30)
~~
*
0.035 (0,89) Radius
0.025 (0,64)
4040144-2/810/94
NOTES:. A. All linear dimensions are In Inches (millimeters).
B. This drawing Is subject to change without notlce.
C. This package can be hermetically sealed with a metal lid.
D. The terminals will be gold plated.
t Applicable MOS Memory Military Devices:
SMJ44C256
SMJ4C1 024
~1ExAs
INSTRUMENTS
9-34
POST OFFICE sox 1443 • HOUSTON. TEXAS 77251-1443
Mechanical Data
MOS Memory Products - Military
'.I-LEADED CERAMIC CHIP CARRIERt
HJ (R-CDCC.J28)
0.740 (18,80)
0.720 (18.29)
0.880 (18,78)
0.840 (18,28)
~
+-
·1
0.060 (1,27)
0.030 (0,78) 4 Plac••
=~
28
0.422 (10,72)
0.408 (10,84)
U
a-a
I
1
14
.
0.101 (2,58)
~
~ ~
0.060 (1,27)
I
.
--~~
0.018 (0,41)
.
J
1ta~3-
0.008 (0,15)
I
~
~
0.077(1,96)
0.059 (1,50)
f
0.178 (4,52)
0.138
t,53)
<'-
0.370 (8,40) TVP
-J
0.035 (0,88)
Radlu.
0.025 (0,84)
4040144-3/B 10/94
NOTES: A. All linear dimensions are In inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metallic!.
D. The terminals will be gold plated.
t Applicable MaS Memory Military Devices:
SMJ44C251B
~TEXAS
INSTRUMENTS
POST OFFICE 80X 1443 • HOUSlON. TEXAS 77251-1443
9-35
Mechanical Data
MOS Memory Products - Militarcy
HK (R-CDFP-F20)
CERAMIC DUAL FLATPACKt
r- 0.035 (0,89)
0.025 (0,64)
r
I
0.095 (2,41)
0.010 (0,25)
0.004 (0,10)
•
Tr
""(1,11'1
~
Ud/~
I________~
0.310(7,87)
0.290 (7,37)
-J
J-0.120 (3,O5)
1
l
J
20
[
~
J:
[
I
---y
[
0.880 (17,27)
0.880 (16,78)
0.050 (1,27)
III ::J
III ::J
III
J:
[
r:::::
1.....:1
J:
III ::J
0.021 (0,53)
~ 0.015 (0,3B)
---y
[
10
L~-,lu,.-J
0.370 (9,40)
0.295 (7,50)
4040174/B 10/94
NOTES: A. All linear dimensions are in Inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
t Applicable MOS Memory Military Devices:
·SMJ4C1024
SMJ44C256
~ThxAs
9-36
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77251-1443
Mechanical Data
MOS Memory Products - Military
HKB (R-CDFP-F28)
CERAMIC DUAL FLATPACKt
,... 0.045 (1,14)
0.028 (0,88)
[~
0.009 (0,23)
(0,10)
r.OO4
13
1
A
,-~~~-------+ ~----~
f _",., ..
2Plac..
-0
l
r:-
4PI
0.010 (0,25) MIN
lac..
j
0.480
0.440 (11,88)
(11,18)
0.400 (10,18)
0.350 (8,89)
-I~r41----""~r-
12
0.370
(9,40)
0.250 (8,35)
13
~f~-.!
~:_"~I
0.790 (20,01)
0.780 (19,30)
i:J
:J.
L
0.021 (0,53)
0.01 & (0,38)
28
4040120/810lIl4
NOTES: A. All linear dimensions are In inches (millimeters).
B. This drawing Is subject to change without notice.
C. This package can be hermeticeliy sealed with a metal lid.
D. The terminals are gold plated.
t Applicable MaS Memory Military DevIces:
SMJ416100
SMJ416400
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSlON. TEXAS 77251-1443
11-37
Mechanical Data
MOS Memory Products - Military
CERAMIC DUAL FLATPACK WITH TIE BARt
HKC (R·CDFP·F64)
1620 (4114)
(40:,3)
1:580
sa
rr'-~I~
0.980 (24,89)
0.765 l'9,43)
0.730 (18,54)
0
.
0.026 (0,68) MIN
.
0.150 (3,81)
0.100 (2,54)
?
0
o
0
......
00
....
0
33
64
0.445111,30)
0.420 0 ,67)
-f
1
32
.... -
INPUT/OUTPUT
ib
C (CONTR04 DEPENDENCY
[STORAGE]
&
a
-~IP--I
&
S [Set]
R [Reset]
Z (INTERCONNECTION) DEPENDENCY
OUTPUTS
ActIve high
Actlvelowt
Open-Clrcult (L-type)*
Open-Clrcult (H-type)' U 1--_ _
COMMON CONTROL BLOCK
•
•
t The active-low indicator may be used In combination
*
with the 3-state and open-clrcuit Indicators.
L-types Include N-channel open-draln and P-channel
open-source outputs.
, H-types Include P-channel open-drall) and N-channel
open-source outputs.
b
b
c
d
-Ii
d
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
10-5
.Logic Symbols
Explanation of a Typical Symbol for a Dynamic Memory
The :rMS4C1024 Symbol
...:---t
2OD1t/Z1DI
--=.....--t
G231(REFRESH ROW)
The TMS4C1024 symbol will be explained In detail for each
operating function. The assumption is made that the previous
sections have been read and understood. While this symbol
is complex, so is the device it represents and the symbol
shows how the part will perform depending on the sequence
in which signais are applied .
C2O(ROWJ
Z4[PWR DWNJ
C21[COL)
2
Addressing
The symbol above makes use of an abbreviated form to show the multiplexed, latched addresses. The blocks
representing the address latches are Implied but not shown.
,....
CAS
A1
-
A2
AO
A1
A3
0
A 1 048575
As
A7
AS
A9
RAS
As
A7
CAS
1
2
3
4
5
-
S
,---
•
'---
r-. ~
-
AS
A9
RAS
-
AS
A2
A4
AS
-
A3
A4
20010/2100
C21
21i)
=- 0
AO
7
I.
'-- ~
20019/2109
C20
021
0
A 1048575
F=- 10
11
I--12
I---
13
14
15
16
I - - - 17
r - - - 18
r - - - 11
r-r-r-r--
When RAS goes low, it momentarily enables (through C20, [> indicates a dynamic input) the 0 inputs of the ten
address registers 10 through 19. When CAS goes low, it momentarily enables (through C21) the 0 Inputs of
the ten address registers 0 through 9. The outputs of the address registers are In 20 Internal address lines that
select 1 of 1 048 576 cells.
~TEXAS
10-6
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77261-1443 .
>
Logic Symbols
Refresh
RAS
---1-""0W)
When RAS goes low, row refresh starts. It ends when RAS goes
high. The other input signals required for refreshing are not
indicated by the symbol.
Power Down
CAS is ANDed with RAS (through G24) so when RAS and CAS
are both high, the device is powered down.
24[PWRDWNJ
024
Write
RAS~3
..
Vi
Byvirtue of the AND relationship between CAS and W (explicitly
shown), when either one of these inputs goes low with the other
one and RAS is already low (RAS is ANDed by G23), the D
input is momentarily enabled (through C22). In an "early-write"
cycle it is W that goes low first; this causes the output to remain
off as explained below.
~
D
23C22
A,22D
Read
The ANDed result of RAS and W (produced by G23) Is
clocked into a latch (through C21l.!!.the instant CAS
goes low. This result will be "1" if RAS is low and W is
high. The complement of CAS is shown to be ANDed
with the output of the latch (by G24 and 24). Therefore,
as long as CAS'stays low, the output is enabled. In the
"early-write" cycle referred to above, a "0· was stored in
the latch by W being low when CAS went low, so the
output remained disabled.
IEEE Standards may be purchased from:
Institute of Electrical and Electronics Engineers, Inc.
345 East 47th Street
New York, New York 10017
International Electrotechnical Commission (IEC) publications may be purchased from:
. American National Standards Institute, Inc.
1430 Broadway
New York, New York 10018
-!11
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
10-7
logic Symbols
~\ThxAs
10-8
. INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
11-1
11·2
:lllExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. lEXAS 772111-1443
Quality and Reliability
MOS MEMORY QUALITY AND RELIABILITY STRATEGY
Texas Instruments is committed to providing its customers with reliable, high quality memory products. MOS
Memory management has applied a four-point quality and reliability strategy to:
. • Provide customers with the lowest cost of product ownership through quality, reliability, and service by:
- On-time delivery to minimize customer inventory.
- Quality performance that justifies ship-to-stock certification and eliminates the cost of component testing.
- No system manufacturing fallout.
- No warranty and service costs.
• Develop partnership relationships to service and solve customer problems and anticipate upcoming needs.
• Uve the quality improvement process from product creation and manufacturing through product sales via our total
quality control approach of:
- Quality Function Deployment.
- Design-in and build-in quality and reliability.
-In-control manufacturing.
- Leadership customer service.
• Measure TI's performance by the customer's measurement and perception. The performance standard is continuous customer satisfaction.
Total Quality Control (TQC)
Total Quality Control (TQe) at n is a business management process encompassing all company functions. The
goal of TQe is continuous customer satisfaction. Utilizing a process of improvement through a positive feedback
cycle, TQe is deployed in the MOS Memory Division from the initial design-in Q&R stage, in-control manufacturing,
and customer service (see Figure 1).
PLAN
DO
Uncl....tencl
Cuetomer
CI.....boutl
Product
Specmeatlon
CHECK CUltomer
Survey
ACr
Improve
Delign
Und• ...tencI Need,
DefIne
Requl...mente
EateblIaII
lluliine
Delign rulH/
Package
Clpablllty
DocumentlAudlt!
Control
Through
Stendard.tSPC
Sllvlcl- On-tlm.
Delivery,
Jrr(Juet In llme),
ShIp-1b4tock,
.Joint auallneatlon
Proc_
ANurwnce
Analyala/
Improvement
Me..u .../AN_
Through
Reliability
TeelIng
ProdUCt/Pr_
Improvement
Support - Field
Through Fectory
Verity - FHdbaek
WHh Cuetom.r
Aeauament
Figure 1. Total Quality Control
~1ExAs
'
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON,TEXAS 77251-1443
11-3
Quality and Reliability
Total Quality Control (TQC) (Continued)
Proper application of the concept of NPLAN-DO-CHECK-ACr allows a positive feedback loop that creates continuous Improvement and breakthrough, as opposed to the NFIX-FIX-FIX-FIX" results of a negative loop (see
Figure 2).
.
QualIty FunctIon Deployment
Continuous customer satisfaction can be achieved only by fully understanding customer needs, then introducing
Innovative products that satisfy those needs.· Quality Function Deployment (QFD) accomplishes both purposes at
TI. QFD is a technique that systematically records thevoice of the customer, identifying product and service attributes
most important to the customer. QFD then blends these needs with the talents and innovations of a TI design team
to define a manufacturable, reliable product solution for the customer.
Deslgn-ln Quality and Reliability
Quality and reliability improvements at TI start with the chip and package design. The objective of MOS Mem()ry's
Design-In Quality and Reliability (DIR) thrust Is first-pass qualification ofnew products, internally and at the cU8tomer.
The TI approach to DIR has been to understand customer requirements of a product, and to formalize this knowledge
into a database that incorporates both reliability modeling knowledge, and Nlessons learned" from historical problems
and engineering evaluations. Before any new design is approved, the design is verified against a DIR Nchecklist".
Design verification is planned to evolve to computer v~rificatlon utilizing artificial intelligence.
From Negative Loop
To PoaiUv. Loop
Figure 2. TQC Philosophy
In-Control ManufacturIng
Documentation/Audit System
To assure In-control manufacturing, TI employs a hierarchical specification system. General specifications on all
aspects of quality, reliability, and customer service are written and controlled by the cen~aI Quality and Reliability
group. More detailed specifications control the operating practices of design, manufacturing, marketing, and other
support organizations. These specifications follow guidelines set by the higher-level speCifications, but concentrate
on the type of bUSiness entity.
~TEXAS
11-4
INSTRUMENTS
POST OFFICE BOX 1+13 • HOUSTON. TEXAS 77251-1+13
Quality and Reliability
In-Control Manufacturing (continued)
Regularly scheduled audits are performed within TI to ensure compliance with all specifications. The five types
of audits performed are:
1. Self audit: An internal audit within each functional operation. This type of audit is conducted by persons within the
operation and an additional person from outside the operation.
2. Cross-audit: An audit by persons independent of the operation being audited.
3. Group audit: An audit of an operation conducted by the Semiconductor Group audits and procedures function,
which is a part of the central Quality and Reliability organization.
.
4. Procedures audit: An audit of lower-level Specifications with respect to higher-level specifications.
5. Compliance audit: An audit of operating practices with respect to specifications.
Statistical Process Control (SPC)
Quality improvement is achieved through Statistical Process Control (SPC). SPC is applied throughout the
manufacturing operations of the MOS Memory division. The objectives of SPC are:
- Control processes on a realtime basis.
-Improve process capability (CP).
- Reduce variability to target value (CPl<).
- Eliminate ·out-of-spec" lots.
- Achieve dependable delivery.
- Lower cost-of-quality.
Computer hardware and artificial intelligence software have been coupled to establish interactive control allowing
the computer to generate realtime control charts and prompt adjustments to equipment and processes
(see Figure 3).
'
Identify Problema and
Data Collection
- Pareto of Defecta
9
'----------'
Identify Source of variation
- Multi-variable Chart
- Flah-Bone
Training
- SPC
- Design of experiments
D
Control Charta
- Control to Target
- Reduce Variability
(,.----------'
Capability Studl..
- Proce.. Spread
- Spec Spread
Figure 3. Computer-Aided Statistical Process Control
~TEXAS
INSTRUMENTS
POST OFFICE BOX 14<13 • HOUSTON. TEXAS 77251-14<13
11-5
Quality and Reliability
Die Fabrication Control
In addition to extensive SPC applications in our MOS fabrication centers, TI implements wafer-level quality and
reliability controls.
Wafer-level quality control focuses on reduction of variability around target values (CPK) for key functionality parameters and controls the processes that affect these parameters. For example: Column ~ time (toAd is a key
DRAM parameter. One of the die manufacturing processes that affects toAC is the photo etch. To reduce variability
of the target value of tcAC, polysilicon-width dimension is controlled at the phOto etch process.
Wafer-level reliability controls address process control of known reliability hazards. For example: ExcessIve
phosphorus use in die processing can lead to corrosion defectS in the finished device, Wafer-level reliability controls
require that phospho~slevel control be built into the manufacturing process and that action be prescribed for out-ofcontrol material. Other wafer-level reliability controls are shown in the following table.
Table 1. Wafer Reliability Controls
PARAMETER
CONTROL
Metal
EIactromigratlon Testing, Grain Size, Silicon Nodule Monitor
Step Coveraga/Metal Necking Monitor
Stress-Induced Metal VoId Testing
Protective Overcoat
P.O. Integrity
Stress Testing
Thickness Monitor
Refraction
Corrosion
" Phosphorus In Multilevel OxIde Monitor
Breakdown VoHage
Gate OxIde Integrity
Device Assembly Control
TI has also implemented assembly level reliability controls and SPC at critical assembly points (see Table 2) to
ensure highly reliable device packaging. Each parameter has certain controls performed at appropriate frequencies
to ensure that assembly processing is at qualified levels. Controls may be added or reduced after extensive testing
has been performed. Results are carefully studied and fed back to preclude reliability problem introduction into the
assembly process. Some of the parameters and controls are shown in Table 3.
Table 2. Major Assembly Steps Using SPC/SQct
PLASnc DEVICE ASSEMBLY
Process
.Control Parameter
Mount
Bond
" Coverage of Epoxy
Bond Strength
Mold
Temperature and Molding Paramel8l'S
Trim/Form
Lead Deflection (DIP)
CERAMIC DEVICE ASSEMBLY
Bond
Seal
Bond Strength
Seal Furnace Temperature
tStadstical Process ControVStatistical Quality Control
~1ExAs
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77251-1443
Quality and Reliability
Table 3. MOS Memory Assembly Level Reliability Controls
CONTROL
PARAMETER
P.O. Integrity
Contactless wafer Mount on Tape Ole Mount System
Mold Compound Parameters
Chip/Crack
VISUal Inspection
Temp Cycle
Saw Sleds Conditions
Poker Pin Height
Wet Etch Monitor (EPROM)
Bond Integrity
Bond Strength Monitor
Bond Parametars
Bake/Bond Pull Monitor
Capillary Change
Package Integrity
Visual Inspection
Mold Press Parametars (plastic)
X-Ray Inspection (Plastic)
Trim/Form (Plastic)
Package Seal (Ceramic)
Temp Cycle (Ceramic)
Hermeticity Monitor (Ceramic)
Ole Mount Integrity
Die-Shear Monitor
Centrifuge Monitor
X-Ray Inspect
Leadfreme Polylmlde Pettern Inspect
PIck-Up Arm Force.
Contamination
VISUal Inspection
Product A•••••m.nt!lmprov.m.nt
Reliability Control System
The MOS Memory reliability control system (Figure 4) provides closed-loop-system feedback resulting in corrective actions and ongoing product improvements. Each new product, process, or major change to an existing product
is Internally qualified to industry leadership standards prior to production. This is followed by intensive monitoring
during production ramp-up and reliability monitoring each month, once a product achieves final production release.
Reliability Development Issues
Soft Error: TI does extensive work in all phases of device development to minimize the effects of soft errors. Soft
errors are caused by alpha particles emitted by the decay of small amounts of thorium and uranium located in device
packaging materials. TI maintains an aggressive program of evaluating new mold compounds to ensure low alpha
emmissivity. Certain device design and processing techniques are also applied to ensure a low soft-error rate. The
goal of device deSign and processing is to maximize the cell capacitance by employing an oxide-nitride dielectric,
as opposed to an oxide dielectric. Also, the cell capacitance increases as the dielectric thickness decreases. Testing
has shown that the trench capacitor used in dynamic RAMs has competitive soft-error rates.
Channel Hot Electron: Channel hot electrons are caused by impact ionization In the drain pinch-off region.
Electrons are accelerated toward the drain, collide with positive Ions, and can be trapped in the gate oxide. This
trapped charge can change the characteristics of the transistor by raising the VT (threshold voltage). One method
employed to reduce the effects of hot electrons is to add a lightly doped drain to reduce the electric field at the gate.
Testing for channel hot electrons is performed at a low temperature' (-1 a·C) and a high drain voltage.
Latch-up: A CMOS device can latch-up when the gain of the parasitic PNP+NPN transistors is greater than 1.
These PNP+NPN transistors act as a silicon controlled rectifier (SCR). If enough current flows through the resistors,
the transistors will turn on and the device will latch-up.
To control latch-up, the SCR gain must be controlled to less than or equal to one. Methods for improving latch-up
immunity Include incorporating guard rings between P+ and N+ diffusions, and isolating P+ and N+ diffusions.
Latch-up testing is performed to ensure our CMOS devices meet the minimum holding current for industry
standards.
-!!11EXAS
INSTRUMENTS
POST OFFICE BOX 14043 • HOUSTON. TEXAS 71251-14043
11-7
Quality and Reliability .
Customer $Mvfce
Quality, Reliability, Selvlce, and the Cost of Ownership
The goal of Texas Instruments is to offer the best quality, reliability, and service In the semiconductor Industry.
The foundation for this approach Is to ship consistent quality. Consistent quality allows ship-to-stock programs that
foster the elimination of the customer's incoming inspection. Ship-to-stock quality, coupled with 100% on-time delivery to narrow shipping windows means support of the customer's just-in-time manufacturing program. This combination of quality, reliability, and service can be measured by a single index called "the cost of ownership·. The -cost of
ownership· is defined as being composed of the purchase price, quality adders (for incoming inspection and board
rework), inventory adders (for maintenance of a buffer inventory for suppliers who cannot meetjust-in-time delivery),
in-house reliability adders (for system bum-in and rework), and field reliability adders (for warranty and post-warranty
field repairs).
For more Information about the cost-of-ownership concept, contact your local TI sales office and request the
brochure -rexas Instruments Lowers Semiconductor Cost of Ownership·, SSYB057.
Quality Improvement
Significant improvement in product quality has been achieved through:
- Better definition of customer's requirements.
- Greater emphasis on quality as a design criterion.
-Improved control of incoming materials.
- Intensive training of supervisors and operators.
- Extensive use of statistical process control.
- More automation of operations to minimize op~rator-related defects.
QUALIFICATION
PRODUcnON RAMP LOT ACCEPT
Baseline process
Baseline process
3 - 6 diffusion lOIs
Reliability lot acceptance concurrent wilh
quallficetlons
Worst
case
customer
requirements
TESTS
125·C Op life
EFRt
85/85
Temperature cycle
Pressure raker test
PSP/PVP
Static bias/storage
Soft error
Data ratention bake
Electromigrallon
Package integrity
ESC
qualification
Review of data once sufliclent Iota have been
sampled
Ongoing reliability monitor of 125·C op life,
datil retention bake, temperature cycle,
85/8:5, autoclave, package integrity, and
intemal cavity moisture
TESTS
Control limits for each test based on product
capability
Early Failure Ratat
High temperature reverse bias t
Temperature cycle
Pressure cooker last
Bake
85/85t
t DRAM - 125·C OPL, 80 hours
EPROM & OTP - 200·C bake, 44 hours (OTP in ceramic package)
PSP: Pressure cooker, Solder dip, Pressure cooker
PVP: Pressure cooker, vapor phase, Pressure cooker
§ Non-Volatile only
*
Figure 4. Reliability Control System
~1ExAs
11-8
RNALPRODUcnONRE~E
Control each package/wafer fabrication
site/device combination
INSTRUMENTS
POST OFFICE B01( 1443 • HOUSTON. liXAS 77251-1443
Early 1aIlure rale monitor
Quality and Reliability
A$ is demonstrated in Figure 5, MOS Memory EPROM and DRAM outgoing quality has dramatically improved
during the last few years. This significant improvement has occurred for all TI product lines and has been recognized
publicly by many of our customers, who have given TI more than 70 major quality awards in the last several years.
Included among these awards are Ford's Q-1 and TQE Awards, the U.S. Naval Quality Award, and the Deming Prize,
which is Japan's most prestigious quality award.
Reliability Improvement
Low IC failure rates are achieved through design-in reliability, computer aided design, stringent qualification testing, prior to product release, routine monitoring of released products, and an extensive failure mode tracking and
feedback system for IC failures.
Each generation of MOS Memory products has exhibited a device failure rate improvement trend, and each new
generation shows a step function improvement in quality and reliability over the previous generation (see Figures 5
and 6). Even though the memory device complexity increases in an ongoing manner, TI's failure rate by function has
improved at an even faster pace. TI continues to emphasize reliability improvement as a major factor in reducing the
total cost of ownership for our customers. Reliability improvement is reflected as a reduction in the expected field
failures during system lifetime.
Up-to-date quality and reliability data for MOS Memory products is available. Please contact your local TI sales
office for information.
'
EFR LEARNING CURVE
300
84K
256K
1M
200
4M
•
,._- ...
100 '.
0, _ '. ....... .
..".... ....
.,
~
-..
o~~~--~~~~~--~~~~
o
2
3
4
5
Years
Rgure 5. MOS Memory Quality Improvement
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77261-1443
11-9
Quality and Reliability
AOQ LEARNING CURVE
3,000
14K
256K
1M
2,000
4M
oL-~~--~~~--~~~~~~
o
3
2
4
5
Ve...
~
40
30
20
10
0
1988
1887
1988
1889
1990
1991
1992
Figure 6. MOS Memory Reliability Improvement
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INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77261-1443
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1994
Electrostatic Discharge Guidelines
12·1
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INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, 1EXAS 77251-1443
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies
Scope
This guideline establishes the requirements for methods and materials used to protect electronic parts, devices,
and assemblies Otems) that are susceptible to damage or degradation from electrostatic discharge (ESO). The
electrostatic charges referred to In this specification are generated and stored on surfaces of ordinary plastics, most
common textile garments, ungrounded person's bodies, and many other commonly unnoticed static generators. The
passage of these charges through an electrostatic-sensitive part may result in catastrophic failure or performance
degradation of the part.
The part types for which these requirements are applicable include, but are not limited to the following:
1. All metal-oxide semiconductor (MOS) devices; e.g., CMOS, PMOS, etc.
2. Junction field-effect transistors (JFEl)
3. Bipolar digital and linear circuits
4. Op-amps, monolithic microcircuits with MOS compensating networks, on-board MOS capacitors, or
other MOS elements
5. Hybrid microcircuits and assemblies containing any of the types of devices listed
6. Printed circuit boards and other types of assembly containing static-sensitive devices
7. Thin-film passive devices
Definitions
1. Electrostatic Discharge (ESO): A transfer of electrostatic charges between bodies at different
electrostatic potentials caused by direct contact or electrostatic field induction.
2. Conductive material: Material having a surface resistivity of 10S C/square maximum.
3. Static dissipative material: Material having a surface resistivity between 10S and 109 C/square.
4. Antistatic material: Material having a surface resistivity between 109 and 1014 O/square
5. Surface resistivity: An inverse measure of the conductivity of a material and is the resistance of unit length
and unit width of a surface. Note: Surface resistivity of a material is numerically equal to the surface
resistance between two electrodes forming opposite sides of a square. The size of the square is
immaterial. Surface resistivity applies to both surface and volume conductive materials and has the
dimension of O/square.
6. Volume resistivity: Also referred to as bulk reSistivity, it is normally. determined by measuring the
resistance (R) of a square of material (surface reSistivity) and multiplying this value by the thickness (T).
7. Ionizer: A blower that generates positive and negative ions, either by electrostatic means or from a
radioactive energy source in an airstream and distributes a layer of low velocity ionized air over a work
area to neutralize static charges.
8. Close proximity: For the purpose of this guideline, 6 inches or less.
Device Sensitivity per Test Circuit of Method 3015, MIL·STD-883C
1. Devices are categorized according to their susceptibility to damage resulting from electrostatic
discharges (ESO).
Category
ESD Sensitivity
Class 1
OV-1999V
Class 2
2000 V - 3999 V
Class 3
4000 V and above
2. Devices are to be protected from ESO damage from receipt at incoming inspection through assembly,
test, and shipment of completed equipment.
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POST OFFICE BOX 1443 • HOUSTON. TEXAS 77261-1443
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Guidelines for Handling Electrostatic-Dlscharge-Sensltlve (ESDS)
Devices 'and Assemblies
Appllcabl. Reference Documenta
The following reference documents (of latest issue) can provide additional information on ESD controls.
1. MIL-M-38510 Microcircuits, General Specification
2. MIL-STD-883 Test Methods and Procedures for Microelectronics
3. MIL-STD-19491 Semiconductor Devices, Packaging of
4. MIL-M-55565 Microcircuits, Packaging of
5. DOD-HDBK-26$ Electrostatic Discharge Control Handbook for Protection
6. DOD-STO-1686 Electrostatic Discharge Control Program
7. NAVSEA SE 003-11-TRN-010 Electrostatic Discharge Training Manual
8. JEDEC Standard Publication 108
Facilities for Static-Free Workstation
The minimum acceptable static-free workstation shall consist of a work surface covered with static dissipative
material attached to ground through a 1 MC :t 10% resistor, an attached grounding wrist .strap with integral
1 MC:t 10% resistor for each operator, and air ionizer(s) of sufficient capacity for each operator. The wrist strap shall
be connected to the static dissipative material. Ground shall utilize the standard building earth ground; refer to Figure
1. Conductive floor tile/carpet along with conductive shoes may be used in lieu of the conductive wrist straps for
non-seated personnel. The Site Safety Engineer must review and approve all electrical connections at the static-free
workstation prior to its implementation.
Air ionizers shall be positioned so that the devices at the static-free workstations are within a 4-foot arc measured
by a verticaJline from the face of the ionizer and 45 degrees on each side of this line.
General grounding requirements are to be in accordance with Table 1.
!
R
wHhGround
Chair
(optional)
Personal
Ground
Strap
ESD Protective
Trey., etc.
.
f
g=~atlve
Table
Top
Ionizer
t_.y{!Rl..-_~~§~~~~~~~~~~~~~~~~~~~
WorkBench
All electrical equipment 8ittingon the conductive table top must be harcf grounded but must be isolated from the atatic dissipative work 8urface.
NOTE A: Earth ground is not computer ground or RF ground or any other limited-type ground.
Figure 1. Static-Free Workstation
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INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, lE
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