1996_AMI_.6_Micron_CMOS_Standard_Cell_Data_Book 1996 AMI .6 Micron CMOS Standard Cell Data Book

1996_AMI_.6_Micron_CMOS_Standard_Cell_Data_Book 1996_AMI_.6_Micron_CMOS_Standard_Cell_Data_Book

User Manual: 1996_AMI_.6_Micron_CMOS_Standard_Cell_Data_Book

Open the PDF directly: View PDF PDF.
Page Count: 460

Download1996_AMI_.6_Micron_CMOS_Standard_Cell_Data_Book 1996 AMI .6 Micron CMOS Standard Cell Data Book
Open PDF In BrowserView PDF
0.6 Micron CMOS Standard Cell
Data Book

III'

NtlII.

AMERICAN MlCROSYSTEMS, INC.

Copyright © 1996 American Microsystems, Inc. (AMI). All rights reserved. Trademarks registered.@
Information furnished by AMI in this publication is believed to be accurate. Devices sold by AMI are covered by the
warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express,
statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves
the right to discontinue production and change specifications and prices at any time and without notice.
AMI's products are intended for use in normal commercial applications. Applications requiring extended temperature
range, unusual environmental requirements or high reliability applications such as military, medical life-support or lifesustaining equipment, are specifically not recommended without additional processing by AMI for such application.
Printed in U.S.A.

Table 01

'I-JtMI
I

Conlenls

AMERICAN MICROSYSTEMS,INC.

General Introduction ...............................................................................................................................................ix
Section 1 - Selection Guide ...............................................................................................................................1-1
Section 2 -Introduction to Core & Pad Logic, with Library Characteristics ................................. 2-1
Section 3 - Core Logic .........................................................................................................................................3-1
Section II - Pad Logic ...........................................................................................................................................4-1
Section 5 - Digital son Megacells ..................................................................................................................5-1
Section 6 - Memories ...........................................................................................................................................6-1
Section 7 - Sales Information ...........................................................................................................................7-1

iii

iv

Selection Guide
Section 1

Library Characteristics
Section 2

Core Logic
Section 3

Pad Logic
Section"

Megacells
Section 5

Memories
Section 6

Sales Information
Section 7
v

vi

I
I~

1111

l

II
III
,I,

-

GENERAL INTRODUCTION

viii

D1\MF:RIr.l~1\1

General
Introduction

MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
ilmerican Microsystems, Inc. - Making ASICs
:asier lor More Than a Quarter Century

Markets
• Communications

I

',merican Microsystems, Inc. (AMI) pioneered the
i Ilevelopment of the world's first custom MOS ICs in 1966.
~ith more experience than any other ASIC vendor, you
Ilan be assured that when you bring your ASIC
levelopment project to AMI, you are working with a
lependable team that has the depth of experience to
mvide you with an optimum solution, on time and on
,udget.

• EDP
• Consumer

'he vision shared by all employees at AMI is expressed in
--'ur mission statement:

Sales and Distribution

• Military
• Industrial
• Automotive
• Medical

• Eight full-service sales and technical support offices
located in key markets throughout North America.

Ve will satisfy your customers by producing products that
leet or surpass their quality, reliability, cost and delivery
eeds.

• Eight additional satellite offices in secondary markets.
• Six technical service centers located in San Jose, Los
Angeles, Boston, Portland, Dresden, and Tokyo, which
offer customers a full range of digital ASIC design
resources and services.

,MI strives to realize this vision by offering a range of
roducts and services aimed at improving cycle time,
---3ducing overall design cost, achieving world-class
~Iiability, and designing to customer need. AMI provides
full range of gate array, standard cell, and mixed-signal
,SICs, ASIC design software and services, and modular
)undry services. AMI's Standard Products division offers
'r'lask-programmable ROMs, waveplex wireless products
nd Mask Programmable Systems Devices (MPSDs).
MI's multichip products division specializes in multichip
:Jlutions.

• 44 sales representative offices throughout North
America, with more than 110 outside salespeople.
• AMI's standard product offerings are available through
74 distributor's offices in the United States and Canada.
• In Europe, AMI is represented by distributors or sales
representatives in the United Kingdom, Germany,
France, Italy, Spain, Netherlands, Belgium, Israel,
Sweden, and Denmark. AMI maintains a technical
service center in Dresden, Germany.

MI is a corporation whose headquarters and ASIC
esign and manufacturing operations are located in a
92,000 square foot facility in Pocatello, Idaho; the
tandard Products division is also headquartered in
ocatello. AMI has a software R&D facility in Twain Harte,
,alifornia, and owns a subsidiary, AMI (Phillippines), Inc.,
Icated in a 64,000 square foot facility in Manila,
hilippines, for electrical testing of AMI's products.

• In addition to a sales office in Tokyo, Japan, AMI is
represented by distributor/sales representatives in that
country and in Singapore, Taiwan, Australia, Hong Kong,
and India.

ix

General
Introduction
AMI6S 0.6 micron CMOS Standard Cells
Products

Senices

ASICs

PLDIASIC Conversions

• Mixed-signal, standard cell, and gate array ASICs.
AMI's ASIC products are supported with a library of
more than 500 digital cells and megacells, designed in
the company's 0.6 and 0.8 micron CMOS process
technologies and compatible with all popular
industry-standard CAE environments.

• NETRANS/PALTRANSTM-the first fully automated PLD
to-ASIC conversion service offered by an ASIC vendor.
• NETRANSplus™-the first fully automated ASIC-to
FPGA conversion service offered by an ASIC vendor t(
provide quick-turn prototyping.

ASIC Test

Mask Programmable ROMs
(read-only memories)

• NETSCANTM-AMl's automated ASIC test-patten
generator software for increasing fault coverage.

• AMI's ROMs offer capabilities from 16 megabits to 16
kilobits, response times as fast as 90 nanoseconds, and
require only a 3 to 5 volt power supply. Design flexibility
is afforded by multiple user-definable control pins and a
variety of packaging options.

•

NETIAGTM-AMI's automated JTAG insertion tool fo
boundary scan testing.

ASIC Design
• Design Analyzer, Gate GobblerTM, Five-Corner Logi,
Simulator™, and Accolade™ cell-compiler software-fa
optimizing customers' ASIC design and swiftly tailorinl
logic functions to customers' specific requirements.

ASIC Design Software
• ACCESS Design ToolsTM software-for optimizing ASIC
design at customer sites. AMI's ACCESS product line
includes Design Analyzer™ and Pattern AnalyzerTM
softare, as well as the company's NETRANSTM
FPGA-to-ASIC conversion software for use at customer
sites, and NETRANSplus™ for fast system prototyping
with FPGAs.

FoundrvlMarketing
• Advanced CMOs technology- brings low POWE
consumption, high noise immunity, and high circu
densities to digital and analog/digital ASICs

Multichip Solutions

• Feature sizes as small as 0.6 micron (drawn), and a
large as 5 micron (drawn).

• Manufacturing and testing multichip solutions with one
or more IC's, combined with other electrical
components, in various combinations of substrates,
interconnects, and package form factors.

• Process modularity -enables automated fabricatio
steps to be variously combined in ways tailored to meE
the specific manufacturing requirements of analo~
digitial, and mixed-signal devices .
• "Flexible factory" -provides a diversity of fabricatio
processes and schedule options to meet customE
requirements.
• Long term support of mature processor.

Corporate Headquarters
American Microsystems, Inc.
2300 Buckskin Road
Pocatello, Idaho 83201
Phone: (208) 233-4690
Fax: (208) 234-6796

ACCESS Design Tools, Accolade, ASIS, Design Analyzer, Pattern Analyzer, Five-Corner Logic Simulator, Gate Gobbler, Mixed-Signal Design Soluti(
(MSDS), NETRANS, NETRANSplus, NETSCAN, NETTAG, and PALTRANS are trademarks of American Microsystems, Inc.
PEEL is a trademark of International CMOS Technology, Inc. and/or its successors or assigns.

x

SECTION 1
SELECTION GUIDE

/
I

W'1~.MIERICI~N

Standard Cell
Selection Guide

MICROSYSTEMS, INC.

AM.6S 0.6 micron CMOS Standard Cells
Simple Gates
Page

Name

Description

AA21

2-input AND gate .................................................................. 3-Right

AA22

2-input AND gate .........................................................................3-2

AA31

3-input AND gate ......................................................................... 3-3

AA32

3-input AND gate .........................................................................3-4

AA41

4-input AND gate .........................................................................3-5

AA42

4-input AND gate .........................................................................3-6

EN21

2-input exclusive NOR gate ....................................................... 3-96

E021

2-input exclusive OR gate .......................................................... 3-98

E031

3-input exclusive OR gate ........................................................ 3-100

NA21

2-input NAND gate ................................................................... 3-142

NA22

2-input NAND gate ................................................................... 3-143

NA31

3-input NAND gate ................................................................... 3-144

NA32

3-input NAND gate ................................................................... 3-145

NA41

4-input NAND gate ................................................................... 3-146

NA42

4-input NAND gate ................................................................... 3-147

NA51

5-input NAND gate ................................................................... 3-148

NA52

5-input NAND gate ................................................................... 3-149

NA61

6-input NAND gate ................................................................... 3-150

NA81

8-input NAND gate ................................................................... 3-151

N021

2-input NOR gate ..................................................................... 3-152

N022

2-input NOR gate ..................................................................... 3-153

N031

3-input NOR gate ..................................................................... 3-154

N032

3-input NOR gate ..................................................................... 3-155

N041

4-input NOR gate ..................................................................... 3-156

N042

4-input NOR gate ..................................................................... 3-157

N051

5-input NOR gate ..................................................................... 3-158

N052

5-input NOR gate ..................................................................... 3-159

OR21

2-input OR gate ........................................................................ 3-174

OR22

2-input OR gate ........................................................................ 3-175

OR31

3-input OR gate ........................................................................ 3-176

OR32

3-input OR gate ........................................................................ 3-177

OR41

4-input OR gate ........................................................................ 3-178

OR42

4-input OR gate ........................................................................ 3-179

1-1

Standard Cell
Selection Guide

JtMIIJ

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Complex Gates
Page

Name

Description

AN11

Two 2-input ANDs into 2-input NOR ............................................. 3-7

AN21

2-input AND into 2-input NOR ...................................................... 3-8

AN31

2-input AND into 3-input NOR ...................................................... 3-9

AN41

3-input AND into 2-input NOR .................................................... 3-10

AN51

2-input AND and 3-input AND into 2-input NOR ........................ 3-11

AN61

Two 3-input ANDs into 2-input NOR ........................................... 3-12

AN71

3-input AND into 3-input NOR .................................................... 3-13

AN81

Two 2-input ANDs into 3-input NOR ........................................... 3-14

AN91

2-input AND and 3-input AND into 3-input NOR ........................ 3-15

ANA1

Two 3-input ANDs into 3-input NOR ........................................... 3-16

ANB1

Three 2-input ANDs into 3-input NOR ....................................... 3-17

ANC1

Two 2-input ANDs and 3-input AND into 3-input NOR ............... 3-18

AND1

2-input AND and two 3-input ANDs into 3-input NOR ................ 3-19

ANE1

Three 3-input ANDs into 3-input NOR ....................................... 3-20

AU11

One-Bit full adder ....................................................................... 3-21

ON11

Two 2-input ORs into 2-input NAND ......................................... 3-160

ON21

2-input OR into 2-input NAND .................................................. 3-161

ON31

2-input OR into 3-input NAND .................................................. 3-162

ON41

3-input OR into 2-input NAND .................................................. 3-163

ON51

2-input OR and 3-input OR into 2-input NAND ........................ 3-164

ON61

Two 3-input ORs into 2-input NAND ......................................... 3-165

ON71

3-input OR into 3-input NAND .................................................. 3-166

ON81

Two 2-input ORs into 3-input NAND ......................................... 3-167

ON91

2-input OR and 3-input OR into 3-input NAND ........................ 3-168

ONA1

Two 3-input ORs into 3-input NAND ......................................... 3-169

ONB1

Three 2-input ORs into 3-input NAND ..................................... 3-170

ONC1

Two 2-input ORs and 3-input OR into 3-input NAND ............... 3-171

OND1

2-input OR and two 3-input ORs into 3-input NAND ................ 3-172

ONE1

Three 3-input ORs into 3-input NAND ..................................... 3-173

1-2

~MI=RICJ~N

Standard Cell
Selection Guide

MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Siandard Cells
Inverting Drivers
Name

Description

Page

INV1

Inverter ..................................................................................... 3-106

INV2

Inverter ..................................................................................... 3-107

INV3

Inverter ..................................................................................... 3-108

INV4

Inverter ..................................................................................... 3-109

INV5

Inverter ..................................................................................... 3-110

INV6

Inverter ..................................................................................... 3-111

Inlernal 3-Slale Drivers
ITA1

Internal non-inverting tri-state buffer ........................................ 3-112

ITA2

Internal non-inverting tri-state buffer ........................................ 3-113

ITB1

Internal inverting tri-state buffer ............................................... 3-114

ITB2

Internal inverting tri-state buffer .............................................. , 3-115

ITD1

Internal inverting tri-state buffer ............................................... 3-116

ITD2

Internal inverting tri-state buffer ............................................... 3-117

ITE1

Internal inverting tri-state buffer ............................................... 3-118

ITE2

Internal inverting tri-state buffer ............................................... 3-119

Clock Drivers
1101

Non-inverting clock driver ......................................................... 3-102

1102

Non-inverting clock driver ......................................................... 3-103

1104

Non-inverting clock driver ......................................................... 3-104

1106

Non-inverting clock driver ......................................................... 3-105

IBF1X3

Non-inverting, CMOS input clock-driver pad ............................. .4-82

IBF7X3

Non-inverting, TTL input clock -driver pad ................................. 4-83

IIF1X5

Non-inverting, CMOS clock-driver, second ring ......................... 4-84

Muxes and Decoders
DC24

2:4 Line decoder ........................................................................ 3-29

DC38

3:8 Line decoder ........................................................................ 3-30

MX21

2:1 Digital multiplexer ............................................................... 3-134

MX212

2:1 Digital multiplexer ............................................................... 3-135

MX41

4:1 Digital multiplexer ............................................................... 3-136

MX81

8:1 Digital multiplexer ............................................................... 3-138

MXI21

Inverting 2:1 Digital multiplexer ................................................ 3-140

MXI212

Inverting 2:1 Digital multiplexer ................................................ 3-141

1-3

Standard Cell
Selection Guide

.~IJ
AMERICAN MICROSYSTEMS.INC

AMI6S 0.6 micron CMOS Standard Cells
Sequential Logic
Name

Description

DF001

D-type F/F without set and reset. Output is

DF011

D-type F/F with active low reset. Output is

DF021

D-type F/F with active low set. Output is

Page
0 ............................ 3-32

a ............................. 3-34

DF031

0 ................................ 3-36
D-type F/F with active low set and reset. Output is 0 ................ 3-38

DF041

D-type F/F without set and reset. Output is ON ......................... 3-40

DF051

D-type F/F with active low reset. Output is ON .......................... 3-42

DF061

D-type F/F with active low set. Output is ON .............................. 3-44

DF071

D-type F/F with active low set and reset. Output is ON .............. 3-46

DF101

D-type buffered F/F with active low set.
Output is and ON ................................................................... 3-48

DF111

D-type buffered F/F with active low reset.
Output is and ON ................................................................... 3-50

DF121

D-type buffered F/F with active low set and reset.
Output is and ON ................................................................... 3-52

DF1F1

D-type buffered F/F without set and reset.
Output is and ON ................................................................... 3-54

DF201

D-type mux scan F/F without set and reset
Output is

DF211

D-type mux scan F/F with active low reset
Output is 0 ................................................................................. 3-58

DF221

D-type mux scan F/F with active low set. Output is 0 ................ 3-60

DF231

D-type mux scan F/F with active low set and reset
Output is

DF401

D-type buffered mux scan F/F with active low set
Output is and ON ................................................................... 3-64

DF411

D-type buffered mux scan F/F with active low reset
Output is 0 and ON ................................................................... 3-66

DF421

D-type buffered mux scan F/F with active low set
and reset. Output is 0 and ON ................................................... 3-68

a

a

a
a

a ................................................................................. 3-56

a ................................................................................. 3-62
a

a and ON ................... 3-70
a .......................... 3-72

DF4F1

D-type buffered mux scan F/F. Output is

DL001

D-type latch without set and reset. Output is

DL011

D-type latch with active low reset. Output is 0 ........................... 3-74

DL021

D-type latch with active low set. Output is

DL031

D-type latch with active low set and reset.
Output is

DL041

D-type latch without set or reset. Output is ON ......................... 3-80

DL051

D-type latch with active low reset. Output is ON ....................... 3-82

a .............................. 3-76

a ................................................................................. 3-78

1-4

I'
I

Standard Cell
Selection Guide

ltMII®
AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Name

Description

DL061

D-type latch with active low set. Output is ON ......................... 3-84

Page

DL071

D-type latch with active low set and reset
Output is ON .............................................................................. 3-86

DL631

D-type buffered latch without set and reset
Output is and ON ...................................................................3-88

a

DL641

D-type buffered latch with active low reset
Output is a and ON ................................................................... 3-90

DL651

D-type buffered latch with active low set
Output is and ON ................................................................... 3-92

DL661

D-type buffered latch with active low set and reset
Output is and ON ................................................................... 3-94

JK011

JK-type F/F with active low reset. Output is

JK021

JK-type

JK031

JK-type F/F with active low set and reset
Output is

JK051

JK-type F/F with active low reset. Output is ON ...................... 3-126

a
a

a ........................ 3-120
F/F with active low set. Output is a ............................ 3-122

a ............................................................................... 3-124

JK061

JK-type F/F with active low set. Output is ON ......................... 3-128

JK071

JK-type F/F with active low set and reset.
Output is ON ............................................................................ 3-130

JKBB1

JK-type F/F with active low set and reset.
Output is and ON ................................................................. 3-132

SLFA1

Multiplexed scan latch D-type F/F with active low reset.
Output is

a

a ............................................................................... 3-180

1-5

Standard Cell
Selection Guide

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Power Cells
Name

Page

Description

CVOO

Core cell resistive tie-up to core V DD bus ................................... 3-27

CVSS

Core cell resistive tie-down to core Vss bus .............................. 3-28

Special Core Cells
BL02

Tri-state bus latch ....................................................................... 3-23

BR02

Tri-state bus receiver .................................................................. 3-24

BR04

Tri-state bus receiver .................................................................. 3-25

BR06

Tri-state bus receiver .................................................................. 3-26

T002

Time delay cell, non-inverting .................................................. 3-182

T003

Time delay cell, non-inverting .................................................. 3-183

T008

Time delay cell, non-inverting .................................................. 3-184

1-6

Standard Cell
Selection Guide

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Input Drive Pieces
Name

Description

IOCI3

Inverting CMOS inpuut buffer piece ............................................ .4-1

Page

10CRO

non-buffered, resistive analog interface input piece .................... .4-2

IOCS3

non-inverting, CMOS Schmitt trigger input buffer piece .............. .4-3

IOCX3

non-inverting, CMOS-level input buffer piece .............................. .4-4

IOPX3

non-inverting, PCI-Ievel input buffer piece .................................. .4-5

10QCO

crystal oscillator input receiver piece .......................................... .4-6

IOQC3

crystal oscillator input receiver piece

wi non-inverting, CMOS clock input ............................................ .4-7
IOQS3

crystal oscillator input receiver piece

wi non-inverting, CMOS Schmitt trigger clock input .................... .4-8
IOTS3

non-inverting, CMOS Schmitt trigger input buffer piece .............. .4-9

IOTX3

non-inverting, TTL input buffer piece ......................................... .4-10

Pull Pieces
PL03

active pull-down buffer piece ..................................................... .4-11

PLP3

programmable pull-up/pull-down buffer piece ........................... .4-12

PLU3

active pull-up buffer piece .......................................................... 4-13

Output Drive Pieces
OOCSIP04

CMOS inverting P-channel open drain buffer piece

wi slew rate control output, 1 rnA .............................................. .4-14
OOCSIP08

CMOS inverting P-channel open drain buffer piece

wi slew rate control output, 8 rnA .............................................. .4-15
OOCSIP12

CMOS inverting P-channel open drain buffer piece

wi slew rate control output, 12 rnA ............................................ .4-16
ODCSXE04

CMOS tri-statable non-inverting buffer piece

wi slew rate control output, 4 rnA .............................................. .4-17
ODCSXE08

CMOS tri-statable non-inverting buffer piece

wi slew rate control output, 8 rnA .............................................. .4-18
ODCSXE12

CMOS tri-statable non-inverting buffer piece

wi slew rate control output, 12 rnA ............................................ .4-19
ODCSXE16

CMOS tri-statable non-inverting buffer piece

wi slew rate control output, 16 mA ............................................ .4-20
OOCSXE24

CMOS tri-statable non-inverting buffer piece

wi slew rate control output, 24 mA ............................................ .4-21
ODCSXX04

CMOS non-inverting buffer piece

wi slew rate control output, 4 rnA ............................................... 4-22

1-7

Standard Cell
Selection Guide

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Name
ODCSXX08

Description

Page

CMOS non-inverting buffer piece

wi slew rate control output, 8 rnA ............................................... 4-23
ODCSXX12

CMOS non-inverting buffer piece

wi slew rate control output, 12 rnA ............................................ .4-24
ODCSXX16

CMOS non-inverting buffer piece

wi slew rate control output, 16 rnA ............................................ .4-25
ODCSXX24

CMOS non-inverting buffer piece

wi slew rate control output, 24 rnA ............................................ .4-26
ODCXIP01

CMOS inverting P-channel open drain buffer piece,
1 rnA .......................................................................................... 4-27

ODCXIP02

CMOS inverting P-channel open drain buffer piece,
2 rnA .......................................................................................... 4-28

ODCXIP04

CMOS inverting P-channel open drain buffer piece,
4 rnA .......................................................................................... 4-29

ODCXIP08

CMOS inverting P-channel open drain buffer piece,
8 rnA .......................................................................................... 4-30

ODCXXE01

CMOS tri-statable non-inverting buffer piece, 1 mA .................. .4-31

ODCXXE02

CMOS tri-statable non-inverting buffer piece, 2 mA .................. .4-32

ODCXXE04

CMOS tri-statable non-inverting buffer piece, 4 mA .................. .4-33

ODCXXE08

CMOS tri-statable non-inverting buffer piece, 8 mA .................. .4-34

ODCXXE12

CMOS tri-statable non-inverting buffer piece, 12 mA ................ .4-35

ODCXXE16

CMOS tri-statable non-inverting buffer piece, 16 mA ................ .4-36

ODCXXE24

CMOS tri-statable non-inverting buffer piece, 24 mA ................ .4-37

ODCXXX01

CMOS non-inverting buffer piece, 1 rnA .................................... .4-38

ODCXXX02

CMOS non-inverting buffer piece, 2 rnA .................................... .4-39

ODCXXX04

CMOS non-inverting buffer piece, 4 rnA .................................... .4-40

ODCXXX08

CMOS non-inverting buffer piece, 8 rnA .................................... .4-41

ODCXXX12

CMOS non-inverting buffer piece, 12 mA .................................. .4-42

ODCXXX16

CMOS non-inverting buffer piece, 16 rnA ................................... 4-43

ODCXXX24

CMOS non-inverting buffer piece, 24 rnA ................................... 4-44

ODPSXE24

PCI non-inverting tri-state buffer piece

wi slew rate control output ........................................................ .4-45
ODTSXN04

TTL non-inverting N-channel open drain buffer piece

wi slew rate control output, 4 rnA .............................................. .4-46
ODTSXN08

TTL non-inverting N-channel open drain buffer piece

wi slew rate control output, 8 rnA .............................................. .4-47
ODTSXN12

TTL non-inverting N-channel open drain buffer piece

wi slew rate control output, 12 rnA ............................................ .4-48
1-8

.1
I

Standard Cell
Selection Guide

~.
AMERICAN MICROSYSTEMS, INC.

AM.6S 0.6 micron CMOS Standard Cells
Name
ODTSXN16

Description

Page

TTL non-inverting N-channel open drain buffer piece

wi slew rate control output, 16 mA ............ ,........................... , .... 4-49
ODTSXN24

TTL non-inverting N-channel open drain buffer piece

wi slew rate control output, 24 mA ............................................ .4-50
ODTSXE04

CMOS tri-state output buffer piece

wi slew rate control output, 4 mA .............................................. .4-51
ODTSXE08

CMOS tri-state output buffer piece

wi slew rate control output, 8 mA .............................................. .4-52
ODTSXE12

CMOS tri-state output buffer piece

wi slew rate control output, 12 mA ............................................ .4-53
ODTSXE16

CMOS tri-state output buffer piece

wi slew rate control output, 16 mA ............................................ .4-54
ODTSXE24

CMOS tri-state output buffer piece

wi slew rate control output, 24 mA ............................................ .4-55
ODTSXX04

TTL non-inverting buffer piece

ODTSXX08

TTL non-inverting buffer piece

ODTSXX12

TTL non-inverting buffer piece

wi slew rate control output, 4 mA .............................................. .4-56
wi slew rate control output, 8 mA .............................................. .4-57
wi slew rate control output, 12 mA ............................................ .4-58
ODTSXX16

TTL non-inverting buffer piece
wi slew rate control output, 16 mA ............................................ .4-59

ODTSXX24

TTL non-inverting buffer piece

wi slew rate control output, 24 mA .......................... ,................. .4-60
ODTXXN01

TTL non-inverting N-channel open drain buffer piece,
1 mA ...........................................................................................4-61

ODTXXN02

TTL non-inverting N-channel open drain buffer piece,
1 mA ........................................................................................... 4-62

ODTXXN04

TTL non-inverting N-channel open drain buffer piece,
4 mA ...........................................................................................4-63

ODTXXN08

TTL non-inverting N-channel open drain buffer piece,
8 mA ...........................................................................................4-64

ODTXXN12

TTL non-inverting N-channel open drain buffer piece,
12 mA .........................................................................................4-65

ODTXXN16

TTL non-inverting N-channel open drain buffer piece,
16 mA ......................................................................................... 4-66

ODTXXN24

TTL non-inverting N-channel open drain buffer piece,
24 mA ......................................................................................... 4-67

ODTXXE01

TTL tri-statable non-inverting buffer piece, 1 mA ...................... .4-68
1-9

Standard Cell
Selection Guide

JtMI'~1

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Name

Description

ODTXXE02

TTL tri-statable non-inverting buffer piece, 2 rnA ...................... .4-69

ODTXXE04

TTL tri-statable non-inverting buffer piece, 4 rnA ...................... .4-70

ODTXXE08

TTL tri-statable non-inverting buffer piece, 8 rnA ...................... .4-71

ODTXXE12

TTL tri-statable non-inverting buffer piece, 12 rnA .................... .4-72

ODTXXE16

TTL tri-statable non-inverting buffer piece, 16 rnA ..................... 4-73

ODTXXE24

TTL tri-statable non-inverting buffer piece, 24 rnA .................... .4-74

ODTXXX01

TTL non-inverting output buffer piece, 1 rnA .............................. 4-75

ODTXXX02

TTL non-inverting output buffer piece, 2 rnA .............................. 4-76

ODTXXX04

TTL non-inverting output buffer piece, 4 rnA ............................. .4-77

ODTXXX08

TTL non-inverting output buffer piece, 8 rnA ............................. .4-78

ODTXXX12

TTL non-inverting output buffer piece, 12 rnA ............................ 4-79

ODTXXX16

TTL non-inverting output buffer piece, 16 rnA ........................... .4-80

ODTXXX24

TTL non-inverting output buffer piece, 24 rnA ............................ 4-81

Page

Power Pad Cells
PP6GXBG

vss power pad for core and pad cells ....................................... .4-85

PP6GXBP

V DD power pad for core and pad cells ....................................... .4-86

PP6GXCG

Vss power pad for input
buffers and core cells only ........................................................ .4-87

PP6GXCP

VDD power pad for input
buffers and core cells only ........................................................ .4-88

PP6GXCW

Power pad pin for additional bus ................................................ 4-89

PP6GXPG

Vss power pad for output buffers only ........................................ 4-90

PP6GXPP

VDD power pad for output
buffers and core cells only ........................................................ .4-91

Special Pad Cells
PORA

Power-on-reset ............................................................................ 4-92

ODQFE20M

Crystal oscillator .......................................................................... 4-93

ODQFE99K

Crystal oscillator .......................................................................... 4-94

ODQTE60M

Crystal oscillator .......................................................................... 4-95

1-10

I
:11,
,I

:,1

II

1
II

'I

,I

II

':1
,I

-

-

'"

11II'

II

SECTION 2
INTRODUCTION TO CORE & PAD LOGIC
WITH LIBRARY CHARACTERISTICS

','I

I[
I

ml~MIEHI(~AN

Library
Characteristics

MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
,olescriplion

• Cost driven architecture:
- Offers both 2 and 3 level metal interconnect to provide
the lowest user cost for the number of gates and pads
required.
- Compiled memory blocks on standard cells are
compacted precisely to parameters. No leaf cell
overhead.

rhe "AMI6S" standard cell family continues the AMI
eadership tradition of combining true compact building
llock standard cells and megacells with high speed
nemory and datapath functions. Using a O.6/lm high
lerformance CMOS process, the AMI6S product can
Ilffer a lower cost alternative to gate array for high volume
lpplications.

• Extensive library for quick design:
- Complete primary cell and 1/0 library.
- Asynchronous and synchronous, single and dual-port
RAM compilers with over 2000 compiled RAM sizes
from 32x1 to 2Kx32 bits.
- Synchronous ROM compiler from 64x1 to 16Kx32
bits.
- Megacells include processors, peripherals, and
datapath synthesizers.
- 100% compatible with AMI's proven ASIC Standard
Library.

:eatures
Excellent performance:
- 480 MHz maximum toggle rate on clocked flip-flops
(TJ = 135°C).
- 210 ps delay (FO=2; L=2mm) for a 2-input NAND
gate.
- 130 ps delay (FO=2; L=Omm) for a 2-input NAND
gate.
Operating temperatures range from -55 to 125°C:
Few competing products allow this range.

• 1 to 24 rnA drive per single 1/0 cell:
Slew rate limiting available for 4, 8, 12, 16, and 24 mA
drive. Custom configurations for 1/0 drive up to 96 mA
can be supported.

_ Clock Tree Synthesis:
AMI supports Clock Tree Synthesis for the default
clocking methodology. In this methodology, clock
drivers are placed by the Place and Route tool to
minimize clock skew and latency effects on circuit
performance. Parameterized clock buffers called
CLKBUF and CLKBUFN are provided to model the
clock trees before layout. AMI is able to match the
simulation parameters of the CLKBUF prelayout
models with a physical clock tree during layout.

• Wide range of packaging:
Full QFP and PLCC line, BGAs and PGAs, individual
die. Burn-in capability as required.
• Automatic Test Program Generation:
Includes scan macros (NETSCANTM) for high fault
coverage.

User-designed pad cells:
AMI allows the user to design pad cells by piecing
together predefined components.

• JTAG Boundary Scan macro support
• Full operating voltage range from 2.7V to 5.5V
• ESD protection> 2kV; latchup > 100 rnA
• Power dissipation:
2.5/lW/MHz/gate

.MI6S Standard Cell Family Overview
I

Feature

!

I

Complexity

I

Description
Up to 900,000 gates
Up to 500,000 gates

Comment

1

50% memory, 50% megacell and user defined logic
100% user defined logic

I

Up to 512 pins
Up to 836 pins

Test equipment limit; signal pins only
Die size limit; includes power supply pins

Internal Gate

102 ps (Fanout=1, L=Omm)
215 ps (Fanout=2, L=2mm)

2 input NAND gate, T=25°C, Voo=5V

Input Buffer

675 ps (Fanout=2, L=2mm)

CMOS Input buffer, T =25°C, V oo=5V

I/O Count
I

belay
ITime

Output Buffer 860 ps (C L=15pf)

CMOS Output buffer,T =25°C, Voo=5V

2-1

Library
Characteristics

~II

AMERICAN MICROSYSTEMS,INC

AMI6S 0.6 micron CMOS Standard Cells
FIGURE 2: STANDARD CELL ARCHITECTURE
Compiled memory blocks are
individually compacted to
minimize area [note 5]

•
•
•

I

~~--------------------~~
.............••

MG29C01
Soft Megacell

I •••••••••••••

. .

C===============::t7t"=-=-=-~~~;;:tl::==-IH----.......

.•......••......•.•

U.U.l.I.U.UJ.U••1.1.1.1.•
Power pad placement
as required [note 3]

Megacells and datapath functions
are built from standard library cells [note 4]
Routing channel width varies with
local cell routing requirements [note 2]

Architectural Overview
unused channels are not lost as in gate array c
embedded array products. For 3 level metal, thi
feature can combine with routing over cells to give
very area efficient design.

Some important elements of the AMI6S standard cell
family are:
• 2 or 3 level metal interconnect selectable.

• [Note 1] Each cell function is tightly compacted to a
fixed bus height. Cells are then placed in rows allowing
VDD and Vss supplies to feed through the cells. Since
some functions require more gates than others, their
widths and heights may increase to allow for the added
gates. Transistor sizes and routing are optimized for
their function, giving a much tighter cell design than
with gate arrays or fixed pad ring embedded array
products.

• [Note 3] Power pads are placed as required among I/(
cells and can be placed in corners. Core power can b
either 3V or 5V. Each individual 1/0 can be powered t
3V or 5V. Operating voltage range is 2.7V to 5.5V.

• [Note 2] Rows of cells can be placed adjacently if little
routing is required between them, or largely separated
to allow a large data bus to route through. Tracks of

• [Note 5] Memory blocks are tightly compacted t
customer defined width and depth. See table on page II
for available memory compilers.

• [Note 4] AMI's megacells and compiled datapat
functions are soft cells. They are placed as if part of th
customer defined logic. Full netlists are provide
allowing modification by the customer for his design.

2-2

Library
Characteristics

!':Il.IVIERI!:AN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Product Applications

AMI Design Flow

'~he

AMI will supply an AMI6X design kit which includes a cell
library containing symbols, simulation models and
software for design verification, timing calculations, and
netlist generation. For pre-layout timing simulations,
capacitance and resistance values derived from statistical

AMI6S standard cells are targeted at higher volume
IkJigital ASIC products. The lower cost also fits designs
Ilrequiring significant on-board memory, datapath logic, or
:llegacells.
'FPGA OR PAL CONVERSION: Using NETRANS™ AMI
Ilban convert netlists from most gate array, FPGA, and PAL
Idevices to a more cost and performance effective AMI6X
design for volume production.

FIGURE 3: ASIC DESIGN FLOW

mo

SOURCE
EXISTING
PRODUCTS:
Netlist
capabilities from AM I allow a competitive
:tlternate supply with AMI6X components for current high
folume designs .
~onversion

AMILibrary
ASIC ~
Std.
AMI

.\lEW DESIGN CAPTURE: AMI6X design is supported by
nany popular 3rd party software platforms, as well as
\Ml's Enhanced Design Utilities™ (EDU) environment.

me~ _---::11:--........

0' memo..

)ROCESS UPGRADE: Designs done in AMI's 1.25/lm,
I.O/lm, and O.8/lm ASIC products can easily be upgraded
o the AMI6X family. The AMI ASIC Standard Library
-)rovides a common netlist design base.

\

blO~

Customer
/

AMI supported
Synthesis Tool

~DDING CUSTOM BLOCKS: AMI specializes in adding
:ustom logic to ASIC deSigns. Simple analog functions
Ire also possible.

Netlist transfer
to AMI

Test Vectors
to AMI

,"'SIC Design Tools and Methodology
,MI6X and other AMI ASIC families are supported on
nany front-end design environments:
Cadence™
Mentor Graphics®
Synopsys®
Viewlogic®
Intergraph®
Compass®
Verilog® simulation
IKOS® simulation accelerator
(AMI's sign-off simulator)

Back Annotation
to Customer

\MI has maintained critical proprietary software tools to
,nsure a tight, well coupled design to our silicon process.
"his methodology includes our expert-system design
I.nalysis tools, AMI's Enhanced DeSign Utilities (EDU), a
IIlli0ftware support methodology that covers the complete
let of wafer processing possibilities, and a dedicated,
,xperienced engineering staff that can assist at any level
If the design process.

Prototype Approval

2-3

~:~~~~

Library
Characteristics
AMI6S 0.6 micron CMOS Standard Cells
AMI Design Flow (cont.)
averages of known layouts are used. Once actual layout is
completed by AMI, a post-layout interconnect capacitance
and resistance table will be supplied for final validation of
device timing.
Figure 3 shows a typical design flow for a new design.
Working with an AMI design center, the customer is
responsible for capturing and verifying the design using the
AMI ASIC Standard Library. He is also responsible for
creating the test vectors that will eventually serve as the
logical part of the manufacturing test. Software aids such
as logic synthesis, megacells, automatic test program
generation, netlist rule checkers, etc. can greatly speed up
this process. (A fault coverage check of the test vector set
is optional and can be done as an additional service.)
When the design is received by the factory, the "Design
Start Package" is reviewed by AMI engineers. This start
package, which is completed by the customer, contains the
device specification, netlist, pinlist file, critical timing paths,
and test vectors. The design is pre-screened on the
Enhanced Design Utilities (EDU) and then resimulated on

IKOS, AMI's sign-off simulator. The results are compared,
to the customer's simulation from the third-party CAE
tool.
Once the design has passed the initial screening it is then
ready for placement and routing. The layout proceeds by
first placing memory and megacells, assigning priority to
critical paths, and designing the distribution and buffering
of clocks. Next, the layout is completed with automatic
place-and-route on the balance of the circuit.
After layout has been completed the interconnect data i~
extracted from the physical layout to be fed back to the
sign-off simulator for final circuit verification. This pos'
layout interconnect data can be sent to the customer fOI
final validation on his simulator. When the post-Iayou
simulation has been completed and approved by thE
customer the design is then released for mask and wafel
fabrication.
The test program is developed in parallel using interna
automatic test program generation software. Prototype~
can then be tested before they are shipped.

FIGURE 4: DESIGN ENVIRONMENT WITH THIRD PARTY SOFTWARE
AMI Environment
AMI ASIC *
Std. Library

HDL

Optional
Synthesis Tool

VHDL

AMI ASIC *
Std. Library

Third Party
Environment
*Elements supplied
in AMI Design Kit

Estimated *
Delays

Timing
Simulation

2-4

"'~1V1I::HII. ;AN

Library
Characteristics

MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
,IMemory Compiler Library
I

Memory Compiler

Size

Increment

Comments

min.

max.

SRAM (single-port, synchronous, self-timed)

32 x 1

2K x 32

16 words, 1 bit

preliminary version available

SRAM (dual-port, synchronous)

32 x 1

1K x 32

16 words, 1 bit

preliminary version available

ROM (single-port, synchronous)

64 x 1

16K x 32

64 words, 1 bit

preliminary version available

SRAM (single-port, asynchronous)

32 x 1

2K x 32

16 words, 1 bit

preliminary version available

I

I

Figure 4 outlines a typical software environment when
using third party tools. AMI uses EDIF to speed ports
.between various software products.

Digital Soft Megacells
The AMI6X gate array and standard cell families support
soft megacells that are compatible with many popular
functions. These megacells are functionally and logically
compatible with the stand-alone products.

AMI's Enhanced Design Utilities Tools are intended to be
used interactively at each stage of the design. EDU
software is a set of design analysis tools that check both
the design and test vectors for correctness and
:ompatibility with in-house ASIC testers, and analyze the
::Jesign for inefficiencies and possible flaws that could
-:ause problems in manufacturing the device.

A soft megacell is defined only at the functional schematic
level. Each instance of the megacell will have exactly the
same functional definition; however, the physical mask
layout will be different depending on other functions being
used, the place-and-route tools, and process technology.
The megacell becomes part of the design netlist, requiring
back annotation of interconnect capacitance after placeand-route for final verification.

rhe Design Library
l\MI provides a robust collection of building blocks for the
l\MI6X family. A broad range of primary cells is
":omplemented with memory cell compilers and useful
llegafunctions. With such broad, US-based design
:alent, AMI can quickly design specific cells that
:;ustomers need to add an edge in customization.

The AMI ASIC Standard Library

Because AMI's soft megacells are defined at the gate level,
simulation models are more accurate than that of
behavioral models. Since our soft megacells use AMI's
ASIC Standard Library they have the advantages of design
flexibility, portability, and a path for future cost reduction by
process migration.

rhe AMI ASIC Standard Library contains a rich set of
:;ore and configurable pad cells which allow great
:Iexibility in building competitive devices for customer
:tpplications. The library is portable across all AMI's gate
:trray and standard cell families.

AMI's selection of soft megacells include Core Processors
and Peripherals which duplicate the function of industry
standard parts. In addition AMI offers FIFOs and Datapath
megacells which are developed using synthesizers. These
products are listed in the following tables.

Memory Compilers

Core Processors and Peripherals

rhe AMI6X family includes the line of memory compilers
3hown above. Each of the thousands of possible memory
)Iocks is optimized precisely to the customers'
)arameters rather than built from a presized leaf cell that
:;overs a range of sizes. This yields a better size and
)erformance match for each application.

The Core Processor and Peripheral megacells are
designed to duplicate the function of industry standard,
stand-alone parts. Detailed functional information can be
found in any standard device datasheet.

Jpon supplying the cell specification to AMI, the
:;ustomer can receive an accurate simulation timing
specification overnight by facsimile and a full simulation
,nodel for any AMI supported software environment within
ive working days.

The AMI6X standard libraries provide an innovative new
approach to 10 pad cell design. By chOOSing from a vast
array of input, output, and pullup/pulldown pad piece
cells, the ASIC designer can literally create thousands of
different 10 cell configurations simply by making the
appropriate schematic or HDL connections. In addition,

AMI's Innovative Pad Piece Methodology

2-5

Library
Characteristics
AMI6S 0.6 micron CMOS Standard Cells
AMI conversion libraries can easily migrate netlist
designs from previous technologies that use ASIC STD
pad cells. AMI's Enhanced Design Utilities Tools flatten
pad cells to their functional (fundamental) pad-piece
blocks. Custom configurations are arrived at simply by
"swapping out" the pieces. Pad-piece design benefits
AM I customers by drastically reducing the need to
request and wait for workstation simulation models of 10
pad cells that would not yet exist. For detailed
information of pad piece usage see AM I applications
note Pad Pieces (4401035).

Name

Core Processors
Name
MG29C01

Function

Function

MG82C54

Programmable interval timer

MG82C55A

Programmable peripheral interface

MG82C59A

Programmable interrupt controller

M8490

SCSI controller

M85C30

Serial communications controller

M8868A

UART

M91C36

Digital data separator

M91C360

Digital data separator

MFDC

Floppy disk controller

MGI2CSL

1

MI2C

1

2

C Serial bus slave transceiver

2

C Bus Interface

4-bit microprocessor slice

MG29C10

Microprogram controller/sequencer

FIFOs

MG65C02

8-bit microprocessor

MG80C85

8-bit microprocessor

The AMI6X library supports both latched-based and dualport ram based FIFOs. The latch-based FIFO has a fallthrough architecture and is applicable when the FIFO size
is limited. For large sizes the RAM based FIFO is
appropriate.

MGMC51

Core processor, 8051 compatible

FIFOs

MGMC51I

MGMC51 with ICE port

MGMC51FB

Core processor, 8051 FB compatible

MGFxxyyC1

Fall-through FIFO

MGMC51SD

Reduced function MGMC51

MGFxxxxyyD

Synchronous FIFO

MGFxxxxyyE

Asynchronous FI FO

M8042

8-bit slave microcontroller

M8048

8-bit microcontroller

Name

Peripherals
Function

Name
MG1468C18

Real-time clock

M16C450

UART

M6402

UART

M6845

CRT controller

M765A

Floppy disk controller

M8251A

Communication interface USART

M8253

Programmable interval timer

M82530

Serial communications controller

MG82C37A

Programmable DMA controller

MG82C50A

Asynchronous comm. element

2-6

Function

'!''I-\'''ICnllU'l4I'1

Library
Characteristics

MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
,Datapath

Ordering information

AMI also supports the complex datapath logic functions
listed here. These functions are synthesized from an input
set of design parameters. They can be optimized for either
minimum delay, minimum gate count or can be designed
·to meet a specified delay. Contact AMI for the size range
and parameter set for any desired functions.

With each megacell, AMI supplies schematics and test
vectors on the requested EDA tool. To order a megacell,
use the Digital Soft Megacel/ order form. Contact the
factory for information on the delivery of soft megacells on
various EDA tools or for information on specific speeds
and sizes of particular Datapath megacells.

I

These logic synthesizers produce soft megacell
schematics in the ASIC Standard Library, and a schematic
symbol for incorporation and simulation with the design
netlist.

Datapath
Function

Name
MGAxxyyDv

Adder

MGAxxyyEv

Adder-subtractor

MGBxxyyAv

Barrel/arithmetic shifter

MGBxxBv

Barrel shifter

MGBxxyyCv

Arithmetic shifter

MGCxxAv

2-function binary comparator

MGCxxBv

6-function binary comparator

MGDxxAv

Decrementer

MGlxxAv

Incrementer

MGlxxBv

Incrementer/decrementer

MGMxxyyDv

Signed/unsigned multiplier

MGMxxyyEv

Multiplier-accumulator

MGSxxyyAv

Signed/unsigned subtractor

2-7

Library
Characteristics

AMER~~'J

AMI6S 0.6 micron CMOS Standard Cells
DC Specifications
Operating Specifications
Parameter

Minimum

V 00 Supply Voltage
Ambient Temperature

- Military
- Commercial

2.7

Maximum
5.5

-55

125

o

70

Units
Volts

CMOS Input Specifications (4.5V/
/;/ --- ---:---

-so

-

---- -

- -

/

./

_---------

o ",_-::-...::;:'::'-- - o
1
2

/

-100

- - - - - - - - - - -

- -

3

- 4

...-./

--

/

- - lout
-lout
---- lout
- - - - lout
---lout

(1
(2
(4
(S

mA)
mA)
mA)
mA)

(12,16,24 mA)
-120 ........------'---------'----------''--------'------o
234

5

Vout (volts)

Vout (volts)

N-Channel Pull-Down Device

P-Channel Pull-Up Device

SO

0

70

-10

60

-20

50

~

-30
;;{

40

~

:§

:§ -40 .

30
-50

20

-60

10

2

3

4

-70

5

0

2
Yin (volts)

Yin (volts)

2-10

3

4

IW\~IIC:Dlr~I\~1

Library
Characteristics

MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
,DC Derating Information
I

IThe DC Characteristics on page 2-11 can be derated to obtain values at other operating conditions using the formula:

loc*Kpoc*Kvoc*KTOC
where IDC is a value from the current curves on page 11. KpDC , the DC process derating coefficient; KVDC ' the DC
voltage derating coefficient; and KTDC , the DC temperature derating coefficient, are described below. Due to the ESD
protection structures, the N-channel driver has a different set of coefficients for KpDC and KTDC '

DC Variations with process (KpoC>
DC variations with process are given as fixed constants determined at the limits of acceptable manufacturing of the
::>rocess. These are described below where WCS is the "Worst Case Speed" fabrication, TYP is the "Target" fabrication,
3.nd WCP is the "Worst Case Power" fabrication.

N-Channel Output Driver
(Vol =O.4V)
Process

WCS

KpDC

0.61

I

TYP

I

1.00

N-Channel Pull-Down Device
(Vol =O.4V)

I

WCP

WCS

I

1.47

0.71

I

TYP

I

1.00

All P-Channel
(Voh =2.4V)

I

WCP

WCS

I

1.27

0.68

I

TYP

I

1.00

I
I

WCP
1.45

DC Variations with Voltage (KvoC>

All N-Channel
(Vol =O.4V)
VDD

4.5

KVDC

0.97

5.0

I
I

1.00

All P-Channel
(Voh =2.4V)

I

5.5

4.5

I

1.03

0.79

I

5.0

I

1.00

I

5.5

I

1.21

DC variations with temperature for the N-Channel output driver (KTOC>
1.3 r--~~-~---~-~-~-~-""'-------'
U
"0

g
o
t5
ell
u..

1.2
1.1

"0

.§ 0.9
ca
E
z

o

0.8
0.7

L...-_~ _

-40

_ _ _ _~_~_~_ _ _ _ _ _ _"';;:::::"'"

-20

0

20

40

60

80

Tj = Junction Temperature (deg C)

100

120

DC variations with temperature for all other N-Channel and P-Channel devices
1.3 r--~~-~-----~-~-~-~-""'------'
U
"0

g
o
~
u..

1.2

1.1

"0

.§ 0.9
ca
E

o

Z

0.8
0.7 L . . . - _ ' - - -_ _ _ _ _ _ _......_ _ _........_ _ _ _........-----'
-40
-20
0
20
40
60
80
100 120
Tj = Junction Temperature (deg C)

2-11

Library
Characteristics

AMERI~ltJ

AMI6S 0.6 micron CMOS Standard Cells
Delay Derating Information

I

I

The propagation delays listed in the data sheets are for typical temperature, 25°C; typical supply voltage, 5.0V; anc
typical processing conditions. To calculate the delay at other conditions (including V DD equals 3.0V) the followin~
equation can be used:

Tpdx =Tpdx(typ)*Kp*Kv*KT

where T pdx(tyP) is given in the data sheets. KR the process derating coefficient; KT, the temperature derating coefficient
and Kv, the supply voltage derating coefficient, are described below.

Delay Variations with Temperature (KT )
Delay varies linearly with temperature. The following formulas and common operating points can be used.

Temp

KT

-55 D C
-25°C
O°C
25 D C
70 D C
100°C
125°C

0.84
0.90
0.94
1.00
1.09
1.16
1.22

Temp. Range

KT Formula

-55°C to 25°C

Kr = 1.0 - (25-T/C )*2.12 x 10-3

25°C to 140°C

Kr = 1.0 + (TJoC-25)*2.12 x 10-3

Where T/C is the temperature at the silicon junction.

Delay Variations with Process (Kp)
Delay variations with process are given as fixed constants determined at the limits of acceptable manufacturing of th'
process. These are described below.

Derating Coefficient (Kp)

Process Variation Point

1.36

Delay increase due to "Worst Case Speed" (WCS) fabrication

1.00

Typical delay; Fabrication target

0.71

Delay reduction due to "Worst Case Power" (WCP) fabrication

Delay Variations with Voltage (Kv)
Delay varies nonlinearly with voltage. Some common operating points and a characteristic curve are shown.

Voo

Kv

2.7V
3.0V
3.3V
4.5V
4.75V
5.0V
5.25V
5.5V

1.65
1.47
1.34
1.07
1.03
1.00
0.97
0.95

>~
C
Q)

·u
~0

()

OJ

c

.~
Q)

0

1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9

2.5

2-12

3

3.5
4
4.5
Supply Voltage (volts)

5

5.5

Library
Characteristics

'!l..I\t1EFIiCAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Interpreting the Data Sheet
The figure below shows a typical data sheet and points out the main features of the data sheet. Not shown is a schematic
which accompanies some of the more complex cells.

AA21

Cell Name - - + - - AMERICAN MICROSYSTEMS,INC.

Library Type --+------------------+
Description --+-~

AMI6S 0.6 micron CMOS Standard Cells

Description
AA21 is a 2-input gate which performs the logical AND function.

Logic Symbol

Truth Table

Q
B
A
Logic Symbol --+---+Q
L
Truth Table --+--+-----:;:~=------_+_--_
H
Pin Loading --+---+--"A=T"-o~---+_---""TT""--,..._+__r_---_+_~
Q

H

Equivalent Gates --+---+
Bolt Syntax --+---+
:)ower Characteristics --+-~

H

Equivalent
Load
A

1.0

B

1.0

H

Equivalent Gates: ................... 1.5
Bolt Syntax: ............................ Q .AA21 A B:
Power Characteristics:

See page 2-14 for power equation.

Delay Characteristics --+-~

Delay Characteristics:
Conditions: TJ ; 25°C, VDD

;

5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

Any Input

Q

0.24
0.21

I

5

I

0.47
0.39

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-1

2-13

I

10

I

0.71
0.56

I

14

I

19 (max)

I

0.95
0.73

J

1.20
0.91

Library
Characteristics

MlIIJ

AMERICAN MICROSYSTEMS,INO

AMI6S 0.6 micron CMOS Standard Cells
A description of data sheet features are as follows.
LIBRARY TYPE: Designates the feature size and library type such as standard cell or gate array.

CELL NAME: AMI's cell name.
DESCRIPTION: A brief sentence about the function of the cell.
LOGIC SYMBOL: Shows a picture of the symbol as it may appear in the workstation design kits.
TRUTH TABLE: A boolean table showing the output logic levels as a function of the input logic levels.
Types of logic levels found in the logic tables are as follows:
H
L

i
,!.
X
NC
IL
Z
UN
Q(n)
QN(n)

=

High level steady state,
Low level steady state,
Transition from low level to high level,
Transition from high level to low level,
Any level including transitions,
No change in output level for a given set of input levels,
The output level is unknown for this set of illegal input levels,
High impedance level,
Undriven node or input,
The level of Q before an active transition on the affecting node, and
The level of QN before an active transition on the affecting node.

PIN LOADING: A table of cell input loads in units of equivalent loads (the input load normalized to the input load of ar
NA21, 2-input NAND gate).
EQUIVALENT GATES: Equivalent gates for the cell is defined as the cell area normalized to the area of the NA21.
BOLT SYNTAX: BOLT (Block Oriented Logic Translator) is an AMI proprietary netlist format. This line shows the BOll
syntax for the cell. One example of the use of BOLT is as a design interface from the workstation design kits to AMI.
POWER CHARACTERISTICS: Power for the cell can be described in three parts. The first part is the power dissipate(
due to the leakage current across the channels and through the formed diodes. The second part is due to the switchin!
voltage across loads on the internal nodes of the cell. Finally, the third part is due to the switching voltage across a loa(
that a cell is driving.
The power characteristics table provides the static leakage current for a junction temperature of 85°C, and the dissipativE
load for all the switching nodes in the cell in terms of equivalent 10ads.The load that a cell drives can be calculated b'
adding up input loads and adding to it the estimated load from the Load Estimation table on page 2-15. Below an
equations for calculating the power dissipation.
Core Cells and Input Buffers
POWER = (Static 100 ) Voo + (O.035E-12)EQLpdV002f + (O.035E-12)EQLIVo02f
Output Buffers
POWER = (StatiC 100 ) Voo +( O.035E-12)EQLpdVo02f + CoIVo02t
where:
Static 100
Voo
EQLpd
f
COl
EQLI

= static leakage current of the cell
= operating voltage
= load of the switching nodes in the cell

= frequency of operation
= load in farads on the output buffer
= load of the driven interconnect and driven input pins

The frequency term of the power equation dominates, making the static current term insignificant. However, the term cal
be used to find the standby current.

2-14

Library
Characteristics

P\I\IIERIC-:AN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Generally, three types of buffers (input, output, and bidirectional) may be assembled using pad piece cells. Calculating
Dower characteristics for pad pieces is dependent on the desired buffer type. The power dissipated by a buffer is the
I:umulative power dissipated by its component pad pieces.

• ID pieces use the input buffer equation. (The input and output buffer equations are described on the previous page.)
I

•

Output pieces use the output buffer equation. Note that COL does not include any PAOM pin loading of 10 or PL pad
piece cells that may be connected to the 00 piece.

• PL pieces use the output buffer equation. COL does not include any PAOM pin loading of 10 or 00 pad piece cells
that may be connected to the PL piece.

JELAY CHARACTERISTICS: This table contains delay data for the various input to output paths in the cells. The table
)elow explains each column in the delay characteristics. AMI models the effects of input slew as well as output resistive
--md capacitive loading for a particular cell's path delay. The delay on the data sheets represents a typical load on the
nputs of the cell. More accurate timing can be obtained using one of AMI's workstation kits. Contact your sales
'epresentative or the factory for details.

:xplanation of Columns in the Delay Characteristics Table

Column Name

Explanation

Delay (ns)
From
To

Names the two pins that identify the path for the delay

Parameter

Mnemonic for the propagation delay or timing parameter whose value can be obtained from the values
listed under the number of equivalent loads column.

Number of
Equivalent
Loads

tplH

Input to output propagation delay for a rising edge on the output

tpHl

Input to output propagation delay for a falling edge on the output

tZH

High impedance to high level delay

tZl

High impedance to low level delay

tHZ

High level to high impedance delay

tlZ

Low level to high impedance delay

tsu

Input setup time with respect to clock

th

Input hold time

tw

Input pulse width

The first row of values in this column contains five equivalent loads over the range of allowed loading
for the cell (output buffer loading is in picofarads). The last value in the row on the ri~ht has the word
"max" in parenthesis to indicate that this is the maximum load that the cell can drive. The rest of the
rows contain delay values for each of the parameters corresponding to given loads in the first row. To
find the delay for a cell, add up the loads of all the inputs that the cell is driving, then add the estimated
interconnect load from the Load Estimation table on page 2-16. Finally, look up the value for the
desired timing parameter corresponding to the load on the cell. Interpolation may be used for values in
between load columns. Again, more accurate delays can be achieved by obtaining an AMI workstation
kit.

lotes: 1. Due to differing capabilities of logic Simulators, the delay modeling implementation will vary and in some cases will still use the linear model. Consult the factory
about modeling for some specific workstation kits and simulators. Loads beyond the maximum load are an extrapolation of the model and therefore their
accuracy is not guaranteed.

2-15

Library
Characteristics

ltMlli

AMERICAN MICROSYSTEMS,INO

AMI6S 0.6 micron CMOS Standard Cells
Interconnect Load Estimation Table

Die
Size

Fan Out (Equivalent Loads)

(in mils)

1

3

6

9

12

20

50

80

500

0.7

2.2

4.3

6.2

8.1

12.8

28.8

43.7

450

0.7

2.1

4.1

5.9

7.7

12.2

27.5

41.7

400

0.6

2.0

3.9

5.6

7.3

11.5

26.1

39.6

350

0.6

1.9

3.6

5.3

6.9

10.9

24.6

37.3

300

0.5

1.7

3.4

4.9

6.4

10.1

23.0

34.8

250

0.5

1.6

3.1

4.5

5.9

9.3

21.2

32.1

200

0.4

1.4

2.8

4.1

5.3

8.5

19.2

29.1

150

0.3

1.2

2.4

3.6

4.7

7.4

16.9

25.6

100

0.3

1.0

2.0

3.0

3.9

6.2

14.1

21.4

2-16

Library
Characteristics

MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
I

Packaging
The AMI6X family can be packaged in a variety of popular packages.
New packages are in development which will extend the package offering. Some special packages or packaging
requirements can be supplied if requested. More details on special packages are available from an AMI sales
representative.

IAvaiiable Packages

( ) = Lead time required

Package Type

Pin Count

Plastic Quad Flatpack (PQFP)

44,52,64,80,100,120,128,144,160,184,208,240,256,304

Thin Quad Flatpack (TQFP)

32,44,48,64,80,100,128,144,176

Metal Quad Flatpack (MQUAD®)

128,144,208

Power Quad 2 (PQ2)

128,144,160,208,304

Ceramic Quad Flatpack (CQFP)

40,44,52,64,84,100,132,144,172,196,256,352

Plastic Leaded Chip Carrier (PLCC)

20,28,32,44,52,68,84

Ceramic Leaded Chip Carrier (JLDCC)

28,44,52,68,84

Ceramic Leadless Chip Carrier (CLCC)

20,24,28,32,36,40,44,48,52,68,84

Plastic Pin Grid Array (PPGA)

69,85,101,109,121,132,145,180

Ceramic Pin Grid Array (CPGA)

65,68,69,84,85,101,109,121,132,145,155, 177, 181,208,225,257,
299,476

Ball Grid Array (BGA)

(121), (169), 225, (256),313, (352),388

Jote1: The 304 pin PowerQuad2™ package has an added heat slug to improve power dissipation.

2-17

I

2-18

SECTION 3
CORE LOGIC

rIAI\~ERIICAN

AA21

MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
AA21 is a 2-input gate which performs the logical AND function.
I

Logic Symbol

Pin Loading

Truth Table
B

0

L

L

L

L

H

L

A

1.0

B

1.0

A

~=[)-O
AA21

~~O
AA21

Equivalent
Load

H

L

L

H

H

H

Equivalent Gates: ................... 1.5
Bolt Syntax: ... ,., .. ,................... 0 .AA21 A B;

Power Characteristics:
Value

Units

Static IDD (TJ = 85°C)

Parameter

2.4

nA

EOL pd

3.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To
Q

tpLH
tpHL

1

5

10

14

19 (max)

0.24
0.21

0.47
0.39

0.71
0.56

0.95
0.73

1.20
0.91

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-1

ltNIIJ

AA22

AMERICAN MICROSYSTEMS, INC

AMI6S 0.6 micron CMOS Standard Cells
Description:
AA22 is a 2-input gate which performs the logical AND function.

Logic Symbol

Pin Loading

Truth Table

~=LJ--0
AA22

~~O
AA22

A

B

Q

Equivalent

L

L

L

Load

L

H

L

A

1.0

H

L

L

B

1.0

H

H

H

Equivalent Gates: ................... 1.5
Bolt Syntax: ............................ 0 .AA22 A B;

Power Characteristics:
Parameter
Static IDD (TJ

Units

Value

= 85°C)

EOL pd

3.3

nA

5.2

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

9

18

26

35 (max)

0.25
0.25

0.48
0.43

0.69
0.60

0.91
0.77

1.13
0.94

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-2

AA31
AMI6S 0.6 micron CMOS Standard Cells
Description:
;AA31 is a 3-input gate which performs the logical AND function.

Logic Symbol

Pin Loading

Truth Table

~=cJ-Q
AA31

~=!>-Q
AA31

A

B

C

Q

Equivalent

L

X

X

L

X

L

X

L

X

X

L

L

B

1.0

H

H

H

H

C

1.0

Load
A

1.0

Equivalent Gates: ................... 1.5
Bolt Syntax: ............................ Q .AA31 ABC;

Power Characteristics:
Parameter
Static 100 (TJ

= 85°C)

EQLpd

Value

Units

3.0

nA

5.0

Eq-Ioad

,ee page 2-14 for power equation.

)elay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

5

10

14

19 (max)

Q

0.28
0.25

0.52
0.43

0.75
0.61

0.97
0.78

1.20
0.95

tpLH
tpHL

)elay will vary with input conditions. See page 2-16 for interconnect estimates.

3-3

AA32

ltMlII

AMERICAN MICROSYSTEMS, INC

AMI6S 0.6 micron CMOS Standard Cells
Description:
AA32 is a 3-input gate which performs the logical AND function.

Logic Symbol

Truth Table

Pin Loading

~=L)-Q
AA32

~~Q
AA32

A

B

C

Q

L

X

X

L

X

L

X

L

A

1.0

X

X

L

L

B

1.0

H

H

H

H

C

1.0

Equivalent
Load

Equivalent Gates: ................... 1.9
Bolt Syntax: ............................ Q .AA32 ABC;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EQLpd

Units

3.9

nA

6.3

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

9

18

26

35 (max)

0.31
0.27

0.54
0.47

0.75
0.65

0.96
0.81

1.17
0.98

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-4

~rvIERI(::;AN

AAl61

MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
'Description:
IAA41 is a 4-input gate which performs the logical AND function.

Logic Symbol

Truth Table

Pin Loading

I

~~O
AA41

~~Q

A

B

C

D

0

Equivalent

L

X

X

X

L

Load

X

L

X

X

L

A

1.0

X

X

L

X

L

B

1.0

X

X

X

L

L

C

1.0

H

H

H

H

H

D

1.0

Equivalent Gates: ................... 1.8
Bolt Syntax: ............................ 0 .AA41 ABC D;

Power Characteristics:
Parameter

Value

Units

Static IDD (TJ = 85°C)

3.4

nA

EOL pd

5.7

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions:TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter

!

I

From

To

Any Input

0

tpLH
tpHL

1

5

10

14

19 (max)

0.31
0.25

0.53
0.45

0.76
0.62

0.97
0.79

1.18
0.97

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-5

ltMlJ

AA42

AMERICAN MICROSYSTEMS,INC

AM.6S 0.6 micron CMOS Standard Cells
Description:
AA42 is a 4-input gate which performs the logical AND function.

Logic Symbol

Truth Table

~~Q
AA42

~~Q

Pin Loading

A

B

C

D

Q

L

X

X

X

L

X

L

X

X

L

X

X

L

X

X

X

X

L

H

H

H

H

Equivalent
Load
A

1.0

L

B

1.0

L

C

1.0

H

D

1.0

I

I

I
Equivalent Gates: ................... 2.0
Bolt Syntax: ............................ Q .AA42 ABC D;

Power Characteristics:
Parameter

Value

Units

Static IDD (TJ = 85°C)

4.3

nA

EQLpd

6.8

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

9

18

26

35 (max)

Q

0.34
0.29

0.59
0.50

0.80
0.67

1.01
0.84

1.22
1.00

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-6

ANll

IWAI\i1ERU:::;AN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
,1,AN11 is an AND-NOR circuit consisting of two 2-input AND gates into a 2-input NOR gate.

Logic Symbol

Truth Table

0

Pin Loading
0

A

B

C

D

L

X

L

X

H

Equivalent

L

X

X

L

H

Load

X

L

L

X

H

A

1.0

X

L

X

L

H

B

1.0

H

H

X

X

L

C

1.0

X

X

H

H

L

D

1 .1

Equivalent Gates: ................... 1.8
Bolt Syntax: ............................ 0 .AN11 ABC D;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EOLpd

Value

Units

1.8

nA

5.0

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

0

tpLH
tpHL

1

3

6

8

11 (max)

0.20
0.15

0.47
0.32

0.72
0.47

0.97
0.62

1.25
0.79

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-7

AN21
AMI6S 0.6 micron CMOS Standard Cells
Description:
AN21 is an AND-NOR circuit consisting of one 2-input AND gate into a 2-input NOR gate.

Logic Symbol

Truth Table

Pin Loading
Equivalent

AN21

0

A

B

C

H

H

X

L

A

X

X

H

L

B

1.0

C

1.0

All other combinations

Load

H

1.0

Equivalent Gates: ................... 1.6
Bolt Syntax: ............................ 0 .AN21 ABC;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EQLpd

Units

1.0

nA

4.0

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

6

8

11 (max)

0.18
0.16

0.40
0.32

0.64
0.49

0.89
0.66

1.12
0.83

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-8

AN3l
AMI6S 0.6 micron CMOS Standard Cells
Description:
AN31 is an AND-NOR circuit consisting of a 2-input AND gate and two direct inputs into a 3-input NOR gate.

Logic Symbol

Pin Loading

Truth Table

AN31

A

B

D

L

X

L

L

H

X

L

L

L

H

C

Equivalent

Q

Load
1.1

A

H

H

X

X

L

B

1.0

X

X

H

X

L

C

1.0

X

X

X

H

L

D

1.0

Equivalent Gates: .. ................. 1.8
Bolt Syntax: ............................ Q .AN31 ABC D;
Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

1.0

nA

5.1

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

I

Any Input

To
Q

tpLH
tpHL

1

3

4

6

8 (max)

0.18
0.20

0.42
0.37

0.64
0.52

0.86
0.67

1.09
0.82

i

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-9

AN"1

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
AN41 is an AND-NOR circuit consisting of one 3-input AND gate into a 2-input NOR gate.

Logic Symbol

Pin Loading

Truth Table

Equivalent
Load

A

B

C

D

Q

H

H

H

X

L

A

1.0

X

X

X

H

L

B

1.0

H

C

1.0

D

1.0

All other combinations

Equivalent Gates: ................... 1.7
Bolt Syntax: ............................ Q .AN41 ABC D;

Power Characteristics:
Parameter
Static IDD (TJ

=

85°C)

Value
1.0

Units

5.7

Eq-Ioad

EQLpd

nA

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, VDD

= 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

4

6

8 (max)

0.22
0.26

0.39
0.39

0.56
0.55

0.74
0.70

0.91
0.84

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-10

II-\'VI[cn,,-",",'

~

lN51

MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
iAN51 is an AND-NOR circuit consisting of one 3-input AND gate and one 2-input AND gate into a 2-input NOR gate.

Logic Symbol

I

Pin Loading

Truth Table

Equivalent

I

B

A

D

C

E

Q

Load

H

H

H

X

X

L

A

1.0

X

X

X

H

H

L

B

1.0

H

C

1.0

D

1.1

E

1.0

All other combinations

Equivalent Gates: ................... 2.3
Bolt Syntax: ............................ Q .AN51 ABC D E;

Power Characteristics:
!

Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

1.8

nA

6.7

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

3

4

6

8 (max)

Q

0.24
0.24

0.44
0.42

0.62
0.57

0.80
0.72

0.98
0.87

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-11

~IIJ

AN6l

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
AN61 is an AND-NOR circuit consisting of two 3-input AND gates into a 2-input NOR gate.

Logic Symbol

Pin Loading

Truth Table

Equivalent
A

B

C

D

E

F

Q

H

H

H

X

X

X

L

X

X

H

H

H

X

All other combinations

Load
A

1.0

L

B

1.0

H

C

1.0

D

1.0

E

1.0

F

1.0

Equivalent Gates: ................... 2.4

Bolt Syntax: ............................ Q .AN61 ABC D E F;

Power Characteristics:
Parameter

Value

Units

Static IDD (TJ = 85°C)

2.7

nA

EQLpd

7.3

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter

From

To

Any Input

Q

tpLH
tpHL

1

3

4

6

8 (max)

0.28
0.27

0.42
0.44

0.59
0.59

0.76
0.74

0.92
0.90

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-12

~M(:RICJ~N

AN71

MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
'l\N71 is an AND-NOR circuit consisting of one 3-input AND gate into a 3-input NOR gate.

Logic~~~------------~--~--------------------------~----~----------------~
Symbol
Truth Table
Pin Loading

I_ _ _ _

Equivalent
A

Q

B

C

D

E

Q

Load

H

H

H

X

X

L

A

1.0

X

X

X

H

X

L

B

1.0

X

X

X

H

L

C

1.0

H

D

1.0

E

1.0

X

All other combinations

:quivalent Gates: ................... 2.0
Jolt Syntax: ............................ 0 .AN71 ABC D E;

)ower Characteristics:
Parameter
Static 100 (TJ

= 85°C)

EOL pd

Value

Units

1 .1

nA

6.6

Eq-Ioad

ee page 2-14 for power equation.

)elay Characteristics:
Conditions:TJ = 25°C, V OD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
l\ny Input

To
Q

tpLH
tpHL

1

3

4

6

8 (max)

0.24
0.25

0.45
0.41

0.67
0.56

0.89
0.72

1.10
0.87

elay will vary with input conditions. See page 2-16 for interconnect estimates.

3-13

~IIJ

AN8l

AMERICAN MICROSYSTEMS, INC

AMI6S 0.6 micron CMOS Standard Cells
Description:
AN81 is an AND-NOR circuit consisting of two 2-input AND gates into a 3-input NOR gate.

logic Symbol

Truth Table

Pin loading
Equivalent

A

B

C

D

E

Q

H

H

X

X

X

L

X

X
X

H

H

X

L

B

1.0

X

X

H

L

C

1.0

H

D

1.0

E

1.0

X

All other combinations

Load
A

1.0

Equivalent Gates: ................... 2.1
Bolt Syntax: ............................ Q .AN81 ABC D E;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EQLpd

Units

1.1

nA

7.6

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

4

6

8 (max)

0.23
0.23

0.54
0.35

0.80
0.42

1.07
0.54

1.36
0.66

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-14

~~i'IAI\~ERIICAN

AN9l

MICROSYSTEMS.ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IAN91 is an AND-NOR circuit consisting of one 3-input AND gate and one 2-input AND gate into a 3-input NOR gate.

'I Logic Symbol

Truth Table

Pin Loading
Equivalent

A

B

C

D

E

F

Q

H

H

H

X

X

X

L

X

X

X

H

H

X

X

X

X

X

X

H

H

All other combinations

Load
A

1.0

L

B

1.0

L

C

1.0

D

1.0

E

1.0

F

1.0

Equivalent Gates: ................... 2.5
Bolt Syntax: ............................ Q .AN91 ABC D E F;

Power Characteristics:
Parameter

Value

Units

Static IDD (TJ = 85°C)

1.1

nA

EQLpd

9.0

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

3

4

6

8 (max)

Q

0.28
0.27

0.58
0.44

0.86
0.61

1.15
0.77

1.44
0.93

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-15

ltMlIJ

ANAl

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ANA 1 is an AND-NOR circuit consisting of two 3-input AND gates into a 3-input NOR gate.

Logic Symbol

Truth Table

Pin Loading
Equivalent

A

B

C

D

E

F

G

Q

Load

H

H

H

X

X

X

X

L

A

1.0

X

X

X

H

H

H

X

L

B

1.0

X

X

X

X

X

X

H

L

C

1.0

H

D

1.0

E

1.0

F

1.0

G

1.0

All other combinations

Equivalent Gates: ................... 2.7
Bolt Syntax: ............................ Q .ANA1 ABC D E F G;

Power Characteristics:
Parameter
Static IDD (TJ = 85°C)
EQLpd

Value

Units

1.1

nA

10.0

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter

From
Any Input

To

1

3

4

6

8 (max)

Q

0.32
0.30

0.59
0.45

0.86
0.62

1.12
0.79

1.38
0.95

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-16

ANBl

111'IAI\i1ERIICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ANB1 is an AND-NOR circuit consisting of three 2-input AND gates into a 3-input NOR gate.
II

Logic Symbol

Truth Table

Pin Loading
Equivalent

A

B

C

D

E

F

Q

H

H

X

X

X

X

L

X

X

H

H

X

X

X

X

X

X

H

H

H

D

1.0

E

1.0

F

1.0

All other combinations

Load
A

1.0

L

B

1.0

L

C

1.0

Equivalent Gates: ................... 2.7
Bolt Syntax: ............................ Q .ANB1 ABC DE F;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EQLpd

Units

2.0

nA

9.0

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions:TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

4

6

8 (max)

0.34
0.26

0.61
0.42

0.90
0.57

1.20
0.73

1.48
0.88

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-17

.~IIJ

ANCl

AMERICAN MICROSYSTEMS,ING

AMI6S 0.6 micron CMOS Standard Cells
Description:
ANC1 is an AND-NOR circuit consisting of one 3-input AND gate and two 2-input AND gates into a 3-input NOR gate.

Logic Symbol

Pin Loading

Truth Table

Equivalent
A

B

C

D

E

F

G

Q

Load

H

H

H

X

X

X

X

L

A

1.0

X

X

X

H

H

X

X

L

B

1.0

X

X

X

X

X

H

H

L

C

1.0

H

D

1.0

E

1.0

F

1.0

G

1.0

All other combinations

Equivalent Gates: ................... 2.9
Bolt Syntax: ............................ Q .ANC1 ABC D E F G;

Power Characteristics:
Parameter
Static IDD (TJ

Value

Units

2.0

nA

10.4

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

3

4

6

8 (max)

Q

0.28
0.34

0.49
0.51

0.72
0.71

0.96
0.89

1.18
1.08

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-18

'AI\,~ERII::::AN

ANDl

MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IAND1 is an AND-NOR circuit consisting of two 3-input AND gates and one 2-input AND gate into a 3-input NOR gate.

,Ir---.......- - - - - - - . . . . . , . -.......__....--------------...,..~___- - - - - - _ _ _ ,

I'

logic Symbol

Truth Table

Pin loading

Equivalent
Load
A

B

C

D

E

F

G

H

Q

A

1.0

H

H

H

X

X

X

X

X

L

B

1.0

X

X

X

H

H

H

X

X

L

C

1.0

X

X

X

X

X

X

H

H

L

D

1.0

H

E

1.0

F

1.0

G

1.0

H

1.0

All other combinations

Equivalent Gates: ................... 3.0
Bolt Syntax: ............................ Q .AND1 ABC D E F G H;

Power Characteristics:
Value

Units

Static IDD (TJ = 85°C)

Parameter

2.0

nA

EQLpd

11.3

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions:TJ

= 25°C, VDD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To
Q

tpLH
tpHL

1

3

4

6

8 (max)

0.38
0.40

0.62
0.58

0.92
0.80

1.23
1.02

1.51
1.21

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-19

Mill

ANEl

AMERICAN MICROSYSTEMS,INC

AMI6S 0.6 micron CMOS Standard Cells
Description:
ANE1 is an AND-NOR circuit consisting of three 3-input AND gates into a 3-input NOR gate.

Logic Symbol

Pin loading

Truth Table

Equivalent
Load
A

B

C

D

E

F

G

H

0

A

1.0

H

H

H

X

X

X

X

X

X

L

B

1.0

X

X

X

H

H

H

X

X

X

L

C

1.0

X

X

X

X

X

X

H

H

H

L

D

1.0

H

E

1.0

F

1.0

G

1.0

H

1.0

All other combinations

1.0
Equivalent Gates: ................... 3.2
Bolt Syntax: ............................ 0 .ANE1 ABC D E F G H I;

Power Characteristics:
Parameter

Value

Units

Static 100 (TJ = 85°C)

3.0

nA

EQLpd

11.7

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

4

6

8 (max)

0.34
0.41

0.57
0.60

0.82
0.82

1.06
1.04

1.31
1.24

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-20

LERICA~!

AUll
AMI6S 0.6 micron CMOS Standard Cells

Description:

I

AU11 is a combinational one-bit full adder.

I

,I
I

Truth Table

Logic Symbol

,lco

r-CI
AU11
-A
-

-8

I S r--

Pin Loading

CI

A

L

L

L

L

B

S

CO

L

L

L

Equivalent

H

H

L

Load

L

H

L

H

L

A

4.8

L

H

H

L

H

B

4.8

H

L

L

H

L

CI

3.7

H

L

H

L

H

H

H

L

L

H

H

H

H

H

H

Equivalent Gates: ................... 6.4
Bolt Syntax: ............................ CO S .AU11 A B CI;

Power Characteristics:

i Parameter
. Static 100 (TJ = 85°C)
EQLpd

Value

Units

7.8

nA

20.6

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

5

10

14

19 (max)

1.01
0.84

1.25
1.13

1.48
1.30

1.72
1.48

1.96
1.70

A

S

tpLH
tpHL

B

S

tpLH
tpHL

1.11
0.85

1.38
1.08

1.61
1.29

1.84
1.48

2.09
1.65

CI

S

tpLH
tpHL

0.96
0.82

1.18
1.06

1.43
1.25

1.67
1.43

1.90
1.61

A

CO

tpLH
tpHL

0.51
0.50

0.74
0.75

0.98
0.94

1.21
1.13

1.43
1.33

B

CO

tpLH
tpHL

0.45
0.54

0.74
0.80

0.95
0.99

1.18
1.18

1.44
1.38

Gontinued on next page)

3-21

AUll

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

CI

CO

tpLH
tpHL

1

5

10

14

19 (max)

0.40
0.40

0.64
0.65

0.87
0.85

1.10
1.04

1.33
1.23

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

A--.__--i
B --'-!----1

CI ---.---1-1---1

3-22

I

~~~I
I

BL02

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.

AMI6S 0.6 micron CMOS Standard Cells
Description:
BL02 is a tri-state bus latch that stores the final binary level on the bus when left undriven.
I

1

Logic Symbol

Truth Table

Pin Loading

I~I

Equivalent

N/A

Equivalent Gates: ................... 2.0
Bolt Syntax: ............................ 10 .BL02;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EQLpd

Load

10

Units

1.5

nA

11.1

Eq-Ioad

See page 2-14 for power equation.

3-23

2.5

ltMlIJ

8802

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
BR02 is a non-inverting bus receiver with a single output to be used as the output of tri-state busses.

Logic Symbol

Pin Loading

Truth Table

-m-

A~a
--~

A~a
-·~2

a

Equivalent

L

L

Load

H

H

A

1.0

Equivalent Gates: ................... 1.3
Bolt Syntax: ............................ 0 .BR02 A;

Power Characteristics:
Value

Units

Static IDD (TJ = 85°C)

Parameter

2.7

nA

EQLpd

4.8

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

A

0

tpLH
tpHL

1

9

18

26

35 (max)

0.21
0.21

0.43
0.41

0.65
0.58

0.88
0.73

1.11
0.89

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-24

8H04

'1IIAI"Ii1ERIICAN MlCROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
iBR04 is a non-inverting bus receiver with a single output to be used as the output of tri-state busses.
!

Logic Symbol

Truth Table

Pin Loading

-m-

Equivalent

Q

L
H

L
H

Load

A

2.0

Equivalent Gates: ................... 2.0
30lt Syntax: ............................ Q .BR04 A;

:lower Characteristics:
Parameter

Value

Units

Static 100 (TJ = 85°C)

5.3

nA

EQLpd

8.5

Eq-Ioad

;ee page 2-14 for power equation.

)elay Characteristics:
Conditions: T J = 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

A

Q

tpLH
tpHL

4

19

35

51

67 (max)

0.20
0.23

0.42
0.39

0.61
0.54

0.82
0.69

1.04
0.83

)elay will vary with input conditions. See page 2-16 for interconnect estimates.

3-25

NtlIJ

BR06

AMERICAN MICROSYSTEMS.INC

AMI6S 0.6 micron CMOS Standard Cells
Description:
BR06 is a non-inverting bus receiver with a single output to be used as the output of tri-state busses.

Logic Symbol

Truth Table

Pin Loading

-m0

L

L

H

H

Equivalent
Load

A

2.0

Equivalent Gates: ................... 2.8
Bolt Syntax: ............................ 0 .BR06 A;
Power Characteristics:
Parameter
Static IDO (TJ

Value

= 85°C)

EOL pd

Units

7.1

nA

12.4

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
A

To
Q

tpLH
tpHL

6

28

52

75

99 (max)

0.25
0.27

0.44
0.42

0.63
0.58

0.82
0.73

1.01
0.87

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-26

I~MI:HICI~N

CVDD

MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
'Description:
GVDD is the resistive tie-up to the core V DD bus for all cell inputs.
Equivalent Gates: ................... 1.0
Bolt Syntax: ............................ Q .CVDD;

3-27

evss
AMI6S 0.6 micron CMOS Standard Cells
Description:
CVSS is the resistive tie-down to the core Vss bus for all cell inputs.
Equivalent Gates: .. ................. 1.0
Bolt Syntax: ............................ Q .CVSS;

3-28

DC24
AMI6S 0.6 micron CMOS Standard Cells
Description:
'DC24 is a two-to-four line decoder/demultiplexer with active low enable.
I

Logic Symbol

Truth Table

DC24

E
Q3
Q2

S1
SO

-

Q1
00

B=
B=

Pin Loading

EN

S1

SO

H

X

X

H

H

H

H

L

L

L

L

H

H

H

L

L

H

H

L

H

L

H

L

H

H

L

L

H

H

H

H

H

L

OON 01N 02N 03N

Equivalent
Load
SO

3.2

H

S1

3.1

H

EN

1.0

Equivalent Gates: ................... 6.6
Bolt Syntax: ............................ OON 01 N 02N 03N .DC24 EN SO S1;
Power Characteristics:
Parameter
Static 100 (TJ

= 85°C)

EOL pd

Value

Units

11.0

nA

23.6

Eq-Iaad

3ee page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Sx

ON

tpLH
tpHL

EN

ON

tpLH
tpHL

1

3

4

6

8 (max)

0.28
0.30

0.39
0.41

0.50
0.52

0.60
0.63

0.71
0.73

0.42
0.37

0.54
0.49

0.64
0.60

0.74
0.70

0.85
0.82

)elay will vary with input conditions. See page 2-16 for interconnect estimates.

continued on next page)

3-29

~IJ

DC38

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DC38 is a three-to-eight line decoder/demultiplexer with active low enable,

Logic Symbol

Truth Table

Pin Loading

DC38

Equivalent

E

Load

~
~
CM
Q5 ~
Q6
Q7 ~
QO

-

82
81
80

Truth Table Appears On Next Page

OJ

Q2
Q3

SO

5.6

81

5.5

S2

5.3

EN

1.0

Equivalent Gates: ................... 15.9

Bolt Syntax: ............................ QON 01N Q2N Q3N Q4N Q5N Q6N Q7N .DC38 EN SO 81 S2;

Power Characteristics:
Parameter

Value

Static IDD (TJ

23.6

nA

54.8

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Delay (ns)
From

To

Sx

ON

EN

ON

Parameter

Process
Number of Equivalent Loads
1

2

4

5

7 (max)

tpLH
tpHL

0.42
0.40

0.48
0.50

0.58
0.61

0.69
0.71

0.76
0.82

tpLH
tpHL

0.70
0.53

0.82
0.68

0.92
0.79

1.01
0.88

1.12
0.96

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

(continued on next page)

3-30

De38
(~R~!
1--------------------------------------AMI6S 0.6 micron CMOS Standard Cells

Truth Table
EN

S2

S1

SO

QON

Q1N

Q2N

Q3N

H

X

X

X

H

H

H

L

L

L

L

L

H

H

L

L

L

H

H

L

L

L

H

L

H

H

L

L

H

H

H

H

L

H

L

L

H

H

Q6N

Q7N

H

H

H

H

H

H

Q4N

Q5N

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

L

H

H

H

H

H

H

L

H

H

H

L

H

L

H

H

H

H

H

H

L

H

H

L

H

H

L

H

H

H

H

H

H

L

H

L

H

H

H

H

H

H

H

H

H

H

L

Logic Schematic

3-31

DFOOl

AMIJ

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DF001 is a static, master-slave D flip-flop without SET or RESET. Output is unbuffered and changes state on the rising
edge of the clock.

Logic Symbol

Pin Loading

Truth Table

H

D

C

0

H

i
i

H
L

D

1.0

L

NC

C

2.7

L

COFOO1

!

X

Equivalent
Load

= No Change

NC

Equivalent Gates: ................... 3.9
Bolt Syntax: ............................ 0 .DF001 CD;

Power Characteristics:
Parameter
Static IDD (TJ

Units

Value
5.3

nA

12.7

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, VDD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

3

6

8

11 (max)

C

0

tpLH
tpHL

0.30
0.42

0.42
0.52

0.54
0.63

0.67
0.73

0.80
0.82

Min CWidth

High

tw

0.41

Min CWidth

Low

tw

0.45

Min D Setup

tsu

0.39

Min D Hold

th

0.00

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

(continued on next page)

3-32

DFOOl

i"li.~II®
·1

AMERICAN MICROSYSTEMS, INC.

AMIDS O.D micron CMOS Standard Cells
Logic Schematic
CN

C

}-------.-----<.... Q

C

CN
CN

C

C

CN

3-33

DFOll

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DF011 is a static, master-slave D flip-flop. RESET is asynchronous and active low. Output is unbuffered and changes
state on the rising edge of the clock.

Logic Symbol

Pin Loading

Truth Table

-D
0-C
DF011
-

R

Y

RN

D

C

0

L

X

X

L

H

L

L

H

H

t
t

H

X

L

Equivalent
Load
D

1.0

H

C

3.0

NC

RN

1.0

= No Change

NC

Equivalent Gates: ................... 5.2
Bolt Syntax: ............................ 0 .DF011 CD RN;

Power Characteristics:
Parameter
Static IDD (TJ

Value

Units

6.7

nA

18.6

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

3

6

8

11 (max)

0.44
0.47

0.63
0.59

0.86
0.69

1.09
0.80

1.30
0.90

0.43

0.54

0.64

0.74

C

Q

tpLH
tpHL

RN

Q

tpHL

0.34

Min C Width

High

tw

0.47

Min C Width

Low

tw

0.52

Min RN Width

Low

tw

0.67

Min D Setup

tsu

0.43

Min D Hold

th

0.00

Min RN Setup

tsu

0.36

Min RN Hold

th

0.37

Delay will vary with input conditions. See page 2-16 for interconnect estimates.
(continued on next page)

3-34

~IIJ

DF021

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
OF021 is a static, master-slave 0 flip-flop. SET is asynchronous and active low. Output is unbuffered and changes state
on the rising edge of the clock.

Logic Symbol

Truth Table

.cS
oS Q-

-

-C
OF021

Pin Loading

SN

0

C

Q

Equivalent

L

X

X

H

Load

H

L

L

0

1.0

H

H

i
i

H

C

3.0

H

X

L

NC

SN

2.1

NC

= No Change

Equivalent Gates: .................. .4.8
Bolt Syntax: ............................ Q .OF021 CO SN;

Power Characteristics:
Parameter

Value

Units

Static IDD (TJ = 85°C)

7.1

nA

EQLpd

14.5

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

C

Q

SN

Q

Min C Width

1

3

6

8

11 (max)

tpLH
tpHL

0.36
0.51

0.50
0.61

0.63
0.75

0.77
0.89

0.90
1.00

tpLH

0.18

0.31

0.43

0.57

0.71

High

tw

0.48

Min C Width

Low

tw

0.46

Min SN Width

Low

tw

0.65

Min 0 Setup

tsu

0.38

Min 0 Hold

th

0.00

(continued on next page)

3-36

11'AMIERICJ~N

DF021

MlICROSYSTEMS.ING

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
I.

Parameter

! From

To
tsu

0.14

Min SN Hold

th

0.24

I

3

1

Min SN Setup

6

I

8

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic
SN ~r-------------~----------------------------~

CN

C

C

CN
CN

C

C

CN

C~CN

3-37

I

11 (max)

DF031
AMI6S 0.6 micron CMOS Standard Cells
Description:
OF031 is a static, master-slave 0 flip-flop. SET and RESET are asynchronous and active low. Output is unbuffered and
changes state on the rising edge of the clock.

Logic Symbol

Truth Table

A

Pin Loading

I

RN

0

C

0

L

L

X

X

IL

Equivalent

L

H

X

X

H

Load

SN

oS Or-C
OF031

H

L

X

X

L

0

1.0

H

H

L

L

C

3.0

R

H

H

H

i
i

H

SN

2.1

Y

H

H

X

L

NC

RN

2.2

-

NC

= No Change
= Illegal

IL

Equivalent Gates: ................... 5.8
Bolt Syntax: ............................ 0 .OF031 CORN SN;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EOLpd

Units

8.2

nA

21.2

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

3

6

8

11 (max)

0.38
0.53

0.50
0.65

0.64
0.77

0.78
0.91

0.91
1.04

C

0

tpLH
tpHL

RN

0

tpHL

0.78

0.86

1.00

1.15

1.24

SN

0

tpLH

0.18

0.32

0.44

0.58

0.71

(continued on next page)

3-38

r

DF031

IliRCAN4lM11
'I

I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)

1

Parameter

I

1

I

From

To

Min C Width

High

tw

0.51

Min C Width

Low

tw

0.55

Min RN Width

Low

tw

0.72

Min SN Width

Low

tw

0.73

1

3

I

6

I

8

I

Min D Setup

tsu

0.46

Min D Hold

th

0.00

Min RN Setup

tsu

0.38

Min RN Hold

th

0.38

Min SN Setup

tsu

0.20

Min SN Hold

th

0.25

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

RN G>SN G>-

C

CN

CN

C
CN

C~CN

CN

C

3-39

I

11 (max)

~IIJ

DFO"l

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DF041 is a static, master-slave D flip-flop without SET or RESET. Output is unbuffered and changes state on the rising
edge of the clock.

Pin Loading

Truth Table

Logic Symbol

l~F04h~

D

C

ON

Equivalent

H

L

Load

L

t
t

H

D

1.0

X

L

NC

C

2.7

NC = No Change

Equivalent Gates: ................... 3.9

Bolt Syntax: ............................ ON .DF041 CD;

Power Characteristics:
Parameter
Static IDD (TJ
EOL pd

= 85°C)

Value
5.3

Units

12.7

Eq-Ioad

nA

See page 2-14 for power equation.

Delay Characteristics:
Conditions:TJ = 25°C, VDD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

3

6

8

11 (max)

0.34
0.17

0.55
0.34

0.75
0.49

0.96
0.64

1.17
0.81

C

ON

tpLH
tpHL

Min C Width

High

tw

0.84

Min C Width

Low

tw

0.45

Min D Setup

tsu

0.39

Min D Hold

th

0.00

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

(continued on next page)

3-40

DF041

11'1 AMFRIr.I"l.N MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Logic Schematic
C

CN

CN

,---------------<-7

C
CN

C

C

CN

C~CN

3-41

ON

• JtMlll

DF051

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
OF051 is a static, master-slave 0 flip-flop. RESET is asynchronous and active low. Output is unbuffered and changes
state on the rising edge of the clock.

Logic Symbol

Pin Loading

Truth Table
RN

0

C

ON

-0

L

X

X

H

-cOF051

H

L

H

R

Q p-

Y

H

H

i
i

H

X

L

Equivalent
.-f----

Load

0

1.0

L

C

3.0

NC

RN

1.0

NC = No Change

Equivalent Gates: ................... 5.2
Bolt Syntax: ............................ ON .OF051 CORN;

Power Characteristics:
Value

Units

Static 100 (TJ = 85°C)

Parameter

6.7

nA

EOLpd

18.6

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)

!

Parameter
From

To

1

3

6

8

11 (max)

C

ON

tpLH
tpHL

0.37
0.20

0.59
0.35

0.81
0.50

1.03
0.67

1.24
0.83

RN

ON

tpLH

0.66

0.86

1.09

1.32

1.53

Min CWidth

High

tw

0.96

Min C Width

Low

tw

0.52

Min RNWidth

Low

tw

0.67

Min 0 Setup

tsu

0.43

Min 0 Hold

th

0.00

(continued on next page)

I

\

3-42

DF051
IIJWI
1-----------------------AMI6S 0.6 micron CMOS Standard Cells

Number of Equivalent Loads

Delay (ns)
Parameter
I

To

From

3

1

Min RN Setup

tsu

0.36

Min RN Hold

th

0.37

I

6

I

8

I

11 (max)

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Schematic Logic

CN

C

CN

~-+----------------~~

C
CN

C

C

CN

3-43

ON

_.MIIIJ

DF06l

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DF061 is a static, master-slave D flip-flop. SET is asynchronous and active low. Output is unbuffered and changes state
on the rising edge of the clock.

Logic Symbol

Truth Table
SN

D

C

A

L

X

X

L

S

H

L

H

H

H

i
i

H

X

L

D
C
DF061

-

Pin Loading

Q J-

NC

Equivalent

ON

Load
D

1.0

L

C

3.0

NC

SN

2.1

= No Change

Equivalent Gates: .................. .4.8
Bolt Syntax: ............................ ON .DF061 CD SN;

Power Characteristics::
Parameter
Static 100 (TJ

Value

Units

7.1

nA

14.5

Eq-Ioad

= 85°C)

EOL pd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

3

6

8

11 (max)

C

ON

tpLH
tpHL

0.37
0.20

0.55
0.35

0.76
0.51

0.98
0.66

1.21
0.81

SN

ON

tpHL

0.43

0.56

0.73

0.91

1.12

Min C Width

High

tw

0.77

Min C Width

Low

tw

0.46

Min SN Width

Low

tw

0.48

Min D Setup

tsu

0.38

Min D Hold

th

0.00

(continued on next page)

3-44

I

II ~I'.

DF061

Ar.HlCAN MICROSVSTEMS I\IC

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

3

1

Min SN Setup

tsu

0.14

Min SN Hold

th

0.24

I

6

8

I

I

11 (max)

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic
SN

~.~------------~~----------------------------~

CN

C

,-+-------------~~

C

CN
CN

C

C

CN

'I

3-45

ON

DF07l

AMERICAN MICROSYSTEMS,INC.

AM.6S 0.6 micron CMOS Standard Cells
Description:
DF071 is a static, master-slave 0 flip-flop. SET and RESET are asynchronous and active low. Output is unbuffered and
changes state on the rising edge of the clock.

Logic Symbol

Truth Table
RN

0

C

ON

L

L

X

X

IL

L

H

X

X

L

H

L

X

X

H

A
oS

-

-C
OF071

R

Pin Loading

SN

Q P-

Y

Equivalent
Load

0

1.0

H

H

L

C

3.0

H

H

i
i

H

H

L

SN

2.1

H

X

L

NC

RN

2.2

H

NC = No Change
IL = Illegal
Equivalent Gates: ................... 5.8
Bolt Syntax: ............................ ON .OF071 CORN SN;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EOLpd

Units

8.2

nA

21.2

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

C

ON

RN
SN

(continued on next page)

1

3

6

8

11 (max)

tpLH
tpHL

0.38
0.21

0.60
0.36

0.81
0.52

1.02
0.68

1.24
0.84

ON

tpLH

0.63

0.82

1.05

1.27

1.47

ON

tpHL

0.55

0.67

0.85

1.02

1.16

3-46

DF071

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
To

From

1

Min C Width

High

tw

0.99

Min C Width

Low

tw

0.55

Min RN Width

Low

tw

1.23

Min SN Width

Low

tw

0.57

Min D Setup

tsu

0.46

Min D Hold

th

0.00

Min RN Setup

tsu

0.38

Min RN Hold

th

0.39

Min SN Setup

tsu

0.20

Min SN Hold

th

0.25

3

I

6

8

I

I

11 (max)

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Log ic Schematic
RN G>SN G>-

CN

C

~----------------~~

CN

C
CN

C~CN

CN

C

3-47

ON

DF10l

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DF101 is a static, master-slave D flip-flop. SET is asynchronous and active low. Outputs are buffered and change state
on the rising edge of the clock.

Logic Symbol

A

-

Pin Loading

Truth Table

DSJ Q

D

C

0

ON

Equivalent

L

X

X

H

L

Load

H

L

H

D

1.0

H

i
i

L

H

H

L

C

2.7

L

NC

NC

SN

2.1

-

CDF101

1°

SN

0-

X

H

NC

= No Change

Equivalent Gates: ................... 5.5
Bolt Syntax: ............................ 0 ON .DF1 01 CD SN;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EOLpd

Units

8.4

nA

18.1

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

5

10

14

19 (max)

0.32
0.45

0.57
0.65

0.79
0.84

1.01
1.02

1.21
1.19

C

0

tpLH
tpHL

C

ON

tpLH
tpHL

0.67
0.48

0.86
0.67

1.09
0.84

1.32
1.01

1.53
1.19

SN

0

tpLH

0.78

1.06

1.28

1.49

1.69

SN

ON

tpHL

0.26

0.46

0.62

0.79

0.98

(continued on next page)

3-48

~.AMII

DF10l

I AMERICAN MICROSYSTEMS, INC.

AM.6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min CWidth

High

tw

0.50

Min C Width

Low

tw

0.46

Min SN Width

tw

0.59

Min D Setup

tsu

0.38

Min D Hold

th

0.00

Min SN Setup

tsu

0.14

Min SN Hold

th

0.24

1

5

I

I

10

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Schematic Logic
SN

~r--------------+----------------------------~

CN

C

C

CN
CN

C

c

CN

3-49

14

I

19 (max)

~IIJ

OFlll

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DF111 is a static, master-slave D flip-flop. RESET is asynchronous and active low. Outputs are buffered and change
state on the rising edge of the clock.

Logic Symbol

-

D

-

Pin Loading

Truth Table

J

Q

-

CDF111

RI

Q 0-

Y

RN

D

C

a

ON

Equivalent

L

X

X

L

H

Load

H

L

H

D

1.1

H

i
i

L

H

H

L

C

2.7

H

X

L

NC

NC

RN

1.0

NC

= No Change

Equivalent Gates: ................... 5.5
Bolt Syntax: ............................ 0 ON .DF111 CD RN;

Power Characteristics:
Parameter
Static 100 (TJ

Value

Units

8.0

nA

22.2

Eq-Ioad

= 85°C)

EOLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

C

a

C

1

5

10

14

19 (max)

tpLH
tpHL

0.33
0.48

0.60
0.68

0.84
0.88

1.09
1.06

1.35
1.23

ON

tpLH
tpHL

0.61
0.55

0.88
0.78

1.10
0.95

1.33
1.12

1.60
1.31

RN

a

tpHL

0.92

1.17

1.37

1.56

1.73

RN

ON

tpLH

0.41

0.66

0.90

1.14

1.39

(continued on next page)

3-50

OFlll

r\Arv1ERII:AN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
. From

To

, Min CWidth

High

tw

0.49

Min CWidth

Low

tw

0.52

Min RNWidth

tw

0.66

Min D Setup

tsu

0.44

I

1

Min D Hold

th

0.00

Min RN Setup

tsu

0.38

Min RN Hold

th

0.38

5

I

10

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

CN

C

C

CN
CN

C

C

CN

3-51

I

14

1

19 (max)

Mill

DF121

AMERICAN MICROSYSTEMS,ING.

AMI6S·0.6 micron CMOS Standard Cells
Description:
DF121 is a static, master-slave D flip-flop. SET and RESET are asynchronous and active low. Outputs are buffered and
change state on the rising edge of the clock.

Logic Symbol

6
-

-

Pin Loading

Truth Table

D

S1

Q I----

CDF121

RIO P-

Y

SN

RN

D

C

Q

QN

L

L

X

X

IL

IL

L

H

X

X

H

L

H

L

X

X

L

H

H

H

L

H

H

l'
l'

L

H

H

H

H

X

L

NC

IL

= Illegal

NC

Equivalent
Load
D

1.0

H

C

3.0

L

SN

2.1

NC

RN

2.2

= No Change

Equivalent Gates: ................... 6.7
Bolt Syntax: ............................ 0 ON .DF121 CD RN SN;

Power Characteristics:
Parameter
Static 100 (TJ

= 85°C)

EQLpd

Value

Units

10.0

nA

25.5

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

C

Q

C

1

5

10

14

19 (max)

tpLH
tpHL

0.36
0.49

0.64
0.73

0.90
0.92

1.15
1.10

1.41
1.29

QN

tpLH
tpHL

0.77
0.52

0.98
0.76

1.24
0.91

1.47
1.08

1.68
1.29

SN

0

tpLH

0.73

0.99

1.25

1.49

1.75

SN

QN

tpHL

0.28

0.48

0.66

0.84

1.02

RN

0

tpHL

0.72

0.95

1.15

1.34

1.52

RN

QN

tpLH

1.00

1.19

1.45

1.68

1.89

(continued on next page)

3-52

'i'I:'I·JtMII~

DF121

.. AMERICAN MICROSYSTEM8,INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min C Width

High

tw

0.58

Min C Width

Low

tw

0.54

Min RN Width

Low

tw

0.80

Min SN Width

Low

tw

0.59

Min D Setup

tsu

0.46

Min D Hold

th

0.00

Min RN Setup

tsu

0.39

Min RN Hold

th

0.38

Min SN Setup

tsu

0.20

Min SN Hold

th

0.25

1

5

I

I

10

14

I

19 (max)

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

RN

@-

SN

@-

CN

C

~

CN

C~CN

CN

C

3-53

ON

DF1Fl

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DF1 F1 is a static, master-slave D flip-flop without SET or RESET. Outputs are buffered and change state on the rising
edge of the clock.

Logic Symbol

-D
-C

Truth Table

Pin Loading

0-

D

C

0

ON

X

X

L

H

L

L

H

D

1.0

H

i
i

H

L

C

2.7

X

L

NC

NC

1

DF1 F1

1°

J--

NC

Equivalent
Load

= No Change

Equivalent Gates: .................. .4.8
Bolt Syntax: ............................ 0 ON .DF1 F1 C D;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EOL pd

Units

7.1

nA

17.2

Eq-Ioad

Delay Characteristics:
Conditions: TJ = 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

5

10

14

19 (max)

0.32
0.48

0.58
0.70

0.82
0.90

1.04
1.08

1.25
1.25

0.83
0.67

1.06
0.84

1.29
1.02

1.50
1.20

C

0

tpLH
tpHL

C

ON

tpLH
tpHL

0.65
0.47

Min C Width

High

tw

0.50

Min C Width

Low

tw

0.44

Min D Setup

tsu

0.36

Min D Hold

th

0.00

(continued on next page)

3-54

!
I

ltMII®

DF1Fl

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells

Logic Schematic

CN

C

CN

C

CN

CN

C

C~CN

3-55

DF201

AMERICAN MICROSYSTEMS, INC.

AM.6S 0.6 micron CMOS Standard Cells
Description:
DF201 is a static, master-slave, multiplexed scan D flip-flop without SET or RESET. Output is unbuffered and changes
state on the rising edge of the clock.

Logic Symbol

-0
-

-

Pin Loading

lPuth Table

Q

f----

C OF201
SO
SE

Equivalent

C

D

SO

SE

Q

i
i
i
i

H

X

L

H

L

X

L

L

X

H

H

H

D

1.0

X

L

H

L

SD

1.0

L

X

X

X

NC

SE

2.0

Load
3.1

C

NC = No Change

Equivalent Gates: ................... 5.3
Bolt Syntax: ............................ Q .DF201 CD SD SE;

Power Characteristics:
Value

Units

Static IDD (TJ = 85°C)

8.0

nA

EQLpd

21.2

Eq-Ioad

Parameter

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

C

Q

Min CWidth
Min CWidth

1

3

6

8

11 (max)

tpLH
tpHL

0.35
0.51

0.47
0.58

0.60
0.70

0.71
0.81

0.83
0.92

High

tw

0.51

Low

tw

0.76

Min D Setup

tsu

0.68

Min D Hold

th

0.00

Min SD Setup

tsu

0.68

Min SO Hold

th

0.00

Min SE Setup

tsu

0.77

Min SE Hold

th

0.00

Delay will vary with input conditions. See page 2-16 for interconnect estimates.
(continued on next page)

3-56

DF201

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Logic Schematic

CN

C

o
SEN
SE

CN

C

C

eN

SE~SEN

C~CN

3-57

DF211

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
OF211 is a static, master-slave, multiplexed scan 0 flip-flop.
unbuffered and changes state on the rising edge of the clock.

Logic Symbol

-D
-

Truth Table

Q r---

C DF211
SO
SE R

-

RESET is asynchronous and active low. Output is

Y

Pin Loading

C

0

RN

SO

SE

Q

i
i
i
i

H

H

X

L

H

L

H

X

L

L

X

H

H

H

X

H

L

H

X

X

L

X

L

X

H

X

NC

Equivalent
Load
C

3.0

H

0

1.0

L

RN

1.0

X

L

SO

1.0

X

NC

SE

2.1

= No Change

Equivalent Gates: ................... 5.9
Bolt Syntax: ............................ 0 .DF211 CORN SO SE;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EOLpd

Units

8.4

nA

25.3

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

C

0

tpLH
tpHL

RN

0

tpHL

(continued on next page)

1

3

6

8

11 (max)

0.41
0.49

0.65
0.59

0.87
0.71

1.09
0.81

1.29
0.90

0.32

0.43

0.53

0.63

0.74

3-58

DF211

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

e Width
Min e Width

High

Min RN Width

tw

0.47

Low

tw

0.76

Low

tw

0.67

Min 0 Setup

tsu

0.74

Min 0 Hold

th

0.00

Min SO Setup

tsu

0.74

Min SO Hold

th

0.00

Min SE Setup

tsu

0.83

Min SE Hold

th

0.00

Min RN Setup

tsu

0.38

Min RN Hold

th

0.38

Min

3

1

I

6

I

8

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

RN~R
eN

o
SEN

SE

CN

C

C

CN

SE~SEN

e~CN

3-59

I

11 (max)

DF221

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DF221 is a static, master-slave, multiplexed scan D flip-flop. SET is asynchronous and active low. Output is unbuffered
and changes state on the rising edge of the clock.

Logic Symbol

Truth Table

A
-D
-

-

S

0 r--

C DF221
SD
SE

Pin Loading

C

D

SD

SE

SN

0

Equivalent

i
i
i
i

H

X

L

H

H

Load

L

X

L

H

L

C

3.0

X

H

H

H

H

D

1.0

X

L

H

H

L

SD

1.0

X

X

X

X

L

H

SE

2.0

L

X

X

X

H

NC

SN

2.1

NC

= No Change

Equivalent Gates: ................... 5.5
Bolt Syntax: ............................ 0 .DF221 CD SD SE SN;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EQLpd

Units

8.9

nA

20.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

3

6

8

11 (max)

C

Q

tpLH
tpHL

0.36
0.52

0.52
0.63

0.66
0.76

0.79
0.89

0.93
1.02

SN

Q

tpLH

0.18

0.32

0.45

0.59

0.72

(continued on next page)

3-60

DF221

I'IA"'~ERH~N MICROSYSTEMS,ING

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter

I

From

To

3

1

'I
I: Min C Width

High

tw

0.49

Min CWidth

Low

tw

0.71

Min SNWidth

Low

tw

0.49

Min D Setup

tsu

0.68

Min D Hold

th

0.00

Min SD Setup

tsu

0.68

Min SD Hold

th

0.00

Min SE Setup

tsu

0.78

Min SE Hold

th

0.00

Min SN Setup

tsu

0.14

Min SN Hold

th

0.25

I

6

I

8

)elay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic
SN

[3)-.

CN

o
SEN
SE

SE

s----[>--

SEN

C

s----[>--

CN

CN

C

C

CN

3-61

I

11 (max)

DF231
AMI6S 0.6 micron CMOS Standard Cells
Description:
OF231 is a static, master-slave, multiplexed scan 0 flip-flop. SET and RESET are asynchronous and active low. Output
is unbuffered and changes state on the rising edge of the clock.

Logic Symbol

C

0

RN

SO

SE

SN

Q

t
t
t
t

H

H

X

L

H

H

Equivalent

L

H

X

L

H

L

Load

X

H

H

H

H

H

C

3.0

X

H

L

H

H

L

0

1.0

A
-0
-

Pin Loading

Truth Table

S Q

r--

C OF231
SO
SE R

X

X

L

X

X

H

L

RN

2.2

Y

X

X

H

X

X

L

H

SO

1.1

NC

X

X

L

X

X

L

IL

SE

2.1

L

X

H

X

X

H

NC

SN

2.1

IL

= No Change

= Illegal Condition

Equivalent Gates: ................... 7.5
Bolt Syntax: ............................ Q .OF231 CORN SO SE SN;

Power Characteristics:
Parameter
Static IOD (TJ

Value

= 85°C)

EQLpd

Units

10.0

nA

28.0

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
To

1

3

6

8

11 (max)

C

Q

tpLH
tpHL

0.39
0.51

0.52
0.68

0.67
0.80

0.81
0.93

0.94
1.08

RN

Q

tpHL

0.73

0.89

1.03

1.15

1.27

SN

Q

tpLH

0.20

0.34

0.47

0.62

0.75

From

(continued on next page)

3-62

~'I
i

I

DF231
-----------------------------------------------------AMI6S 0.6 micron CMOS Standard Cells

AMERICAN MICROSYSTEMS.INC.

Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min CWidth

High

tw

0.53

Min C Width

Low

tw

0.76

Min RNWidth

Low

tw

0.75

Min SNWidth

Low

tw

0.57

Min 0 Setup

tsu

0.74

Min 0 Hold

th

0.00

Min SO Setup

tsu

0.74

Min SO Hold

th

0.00

Min SE Setup

tsu

0.84

Min SE Hold

th

0.00

Min RN Setup

tsu

0.39

Min RN Hold

th

0.37

Min SN Setup

tsu

0.19

Min SN Hold

th

0.25

3

1

-,

6

,

,

8

Delay will vary with Input conditions. See page 2-16 for Interconnect estimates.

Logic Schematic
RN G>-SN G>--

C

CN

o
SEN
SE

SO

-7

C

SE~SEN

CN

C~CN
C

3-63

CN

11 (max)

OF"Ol

AMERICAN MlCROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
OF401 is a static, master-slave, multiplexed scan 0 flip-flop. SET is asynchronous and active low. Outputs are buffered
and change state on the rising edge of the clock.

Logic Symbol

Truth Table

cS
-

OSlo r--

-

COF401

-

SO
SE

-

IQ P-

Pin Loading

C

0

SO

SE

SN

a

ON

Equivalent

i
i
i
i

H

X

L

H

H

L

Load

L

X

L

H

L

H

C

2.7

X

H

H

H

H

L

0

1.0

X

L

H

H

L

H

SO

1.0

X

X

X

X

L

H

L

SE

2.0

L

X

X

X

H

NC

NC

SN

2.1

NC

= No Change

Equivalent Gates: ................... 6.8
Bolt Syntax: ............................ O ON .OF401 COSO SE SN;
Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EOLpd

Units

10.2

nA

24.3

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

5

10

14

19 (max)

C

a

tpLH
tpHL

0.36
0.46

0.60
0.68

0.85
0.87

1.10
1.06

1.34
1.24

C

ON

tpLH
tpHL

0.68
0.51

0.89
0.70

1.12
0.88

1.36
1.06

1.58
1.25

SN

a

tpLH

0.83

1.09

1.34

1.59

1.81

SN

ON

tpHL

0.28

0.47

0.66

0.84

1.02

(continued on next page)

3-64

~II®

:ii
!

DF401

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min C Width

High

tw

0.51

Min CWidth

Low

tw

0.68

Min SN Width

Low

tw

0.59

Min D Setup

tsu

0.66

Min D Hold

th

0.00

Min SD Setup

tsu

0.66

Min SD Hold

th

0.00

Min SE Setup

tsu

0.76

Min SE Hold

th

0.00

Min SN Setup

tsu

0.14

Min SN Hold

th

0.24

1

I

5

10

I

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic
SN

§--

CN
D
SEN
SE

SE~SEN

C~CN

CN
C

3-65

14

I

19 (max)

OF"11

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DF411 is a static, master-slave, multiplexed scan D flip-flop,
buffered and change state on the rising edge of the clock.

Logic Symbol

-

-

RESET is asynchronous and active low. Outputs are

Pin Loading

Truth Table

D
IQ C DF411
SD

SE RIO :::r-

Y

C

D

RN

SD

SE

Q

QN

Equivalent

i
i
i
i

H

H

X

L

H

L

Load

X
L

X

L

H

X

L

L

H

C

2.7

X

H

H

H

H

L

D

1.0

X

H

L

H

L

H

RN

1.1

X

L

X

X

L

H

SD

1.0

X

X

NC

NC

SE

2.1

H
NC

= No Change

Equivalent Gates: ................... 8.0
BoltSyntax: ............................ QON .DF411 CD RN SD SE;

Power Characteristics:
Value

Units

Static 100 (TJ = 85°C)

Parameter

9.8

nA

EOL pd

28.7

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

C

0

C
RN
RN

(continued on next page)

1

5

10

14

19 (max)

tpHL

0.35
0.51

0.59
0.70

0.83
0.89

1.07
1.08

1.30
1.28

QN

tpLH
tpHL

0.64
0.59

0.87
0.79

1.09
0.98

1.31
1.16

1.55
1.34

Q

tpHL

0.94

1.20

1.39

1.58

1.79

tpLH

0.44

0.66

0.87

1.10

1.34

ON

tpLI~

3-66

~lt~1

OF"ll

i---------------------------AMI6S 0.6 micron CMOS Standard Cells
I

Number of Equivalent Loads

Delay (ns)
Parameter

I

I

From

To

Min CWidth

High

tw

0.50

Min CWidth

Low

tw

0.75

Min RN Width

Low

tw

0.65

Min D Setup

tsu

0.74

Min D Hold

th

0.00

Min SD Setup

tsu

0.74

Min SD Hold

th

0.00

Min SE Setup

tsu

0.84

Min SE Hold

th

0.00

Min RN Setup

tsu

0.38

Min RN Hold

th

0.38

1

5

I
I

I

10

I

14

I

19 (max)

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

CN

D

~
~

SEN
SD
SE

~

C~CN

CN
C

SE~SEN

3-67

ON

• JtMIIJ

DF421

AlVIEAlCAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DF421 is a static, master-slave, multiplexed scan D flip-flop. SET and RESET are asynchronous and active low. Outputs
are buffered and change state on the rising edge of the clock.

Logic Symbol

Truth Table

A
-D
-

Sio r--C DF421

SD
SE

I

R Q P-

Y

Pin Loading

C

D

RN

SD

SE

SN

a

t
t
t
t

H

H

X

L

H

H

L

L

H

X

L

H

L

H

X

H

H

H

H

H

L

D

1.0

X

H

L

H

H

L

H

RN

2.2

Equivalent

ON

Load
C

3.0

X

X

L

X

X

H

L

H

SD

1.0

X

X

H

X

X

L

H

L

SE

2.1

X

X

L

X

X

L

IL

IL

SN

2.2

X

H

X

H

NC

NC

L
NC

= No Change

X

= Illegal Condition

IL

Equivalent Gates: ................... 8.8
Bolt Syntax: ............................ 0 ON .DF421 CD RN SD SE SN;

Power Characteristics:
Parameter

Value

Units

Static 100 (TJ = 85°C)

11.8

nA

EOLpd

32.4

Eq-Ioad

. See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

5

10

14

19 (max)

0.39
0.52

0.66
0.73

0.90
0.92

1.16
1.10

1.42
1.27

C

a

tpLH
tpHL

C

ON

tpLH
tpHL

0.78
0.57

1.07
0.79

1.29
0.98

1.54
1.14

1.83
1.32

RN

a

tpHL

0.71

0.96

1.13

1.32

1.52

RN

ON

tpLH

0.99

1.27

1.50

1.75

2.03

SN

a

tpLH

0.76

1.04

1.29

1.54

1.81

SN

ON

tpHL

0.34

0.53

0.71

0.88

1.07

(continued on next page)

3-68

I

DF421

AMERICAN MlCROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min C Width

High

tw

0.61

Min CWidth

Low

tw

0.78

Min RNWidth

Low

tw

0.82

Min SNWidth

Low

tw

0.59

Min 0 Setup

tsu

0.78

Min 0 Hold

th

0.00

Min SO Setup

tsu

0.78

Min SO Hold

th

0.00

Min SE Setup

tsu

0.88

Min SE Hold

th

0.00

Min RN Setup

tsu

0.39

Min RN Hold

th

0.39

Min SN Setup

tsu

0.21

Min SN Hold

th

0.25

1

5

1

10

I

I

14

19 (max)

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic
RN 8 SN 8 ->

C

CN

o
SEN
SE

C~CN

CN

RN

SE~SEN

CN

C

3-69

Q

DF~Fl

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
OF4F1 is a static, master-slave, multiplexed scan 0 flip-flop without SET or RESET. Outputs are buffered and change
state on the rising edge of the clock.

Logic Symbol

Truth Table

10

-

D
C DF4F1
SD
0SE

-

1°

-

Pin Loading

C

0

SO

SE

0

ON

Equivalent

i
i
i
i

H

X

L

H

L

Load

L

X

L

L

H

C

2.7

X

H

H

H

L

0

1.0

X

L

H

L

H

SO

1.0

L

X

X

X

NC

NC

SE

2.1

NC

= No Change

Equivalent Gates: ................... 6.1
Bolt Syntax: ............................ 0 ON .OF4F1 C 0 SD SE;

Power Characteristics:
Value

Parameter
Static 100 (TJ

= 85°C)

EOLpd

Units

8.9

nA

23.2

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

5

10

14

19 (max)

C

0

tpLH
tpHL

0.36
0.50

0.59
0.70

0.83
0.89

1.05
1.09

1.26
1.26

C

ON

tpLH
tpHL

0.61
0.47

0.83
0.69

1.05
0.85

1.27
1.03

1.49
1.23

(continued on next page)

3-70

DF4Fl

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

e Width
Min e Width

High

tw

0.48

Low

tw

0.63

Min 0 Setup

tsu

0.63

Min 0 Hold

th

0.00

Min SO Setup

tsu

0.63

Min SO Hold

th

0.00

Min SE Setup

tsu

0.73

Min SE Hold

th

0.00

Min

5

1

1

10

1

14

I

19 (max)

Delay will vary with Input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

e

o

eN

-7

SEN
-7

SO
SE

-7

e~eN

e

eN

SE~SEN

3-71

ON

DLOOl

AMERICAN MICROSYSTEMS,ING

AM.6S 0.6 micron CMOS Standard Cells
Description:
DL001 is a single-phase, unbuffered D latch with active low gate transparency and without SET or RESET.

Logic Symbol

Pin Loading

Truth Table
GN

H
GDL001

Q

D

Equivalent

L

L

L

L

H

H

D

1.0

X

NC

GN

2.1

H
NC

Load

= No Change

Equivalent Gates: ................... 2.6
Bolt Syntax: ............................ 0 .DL001 D GN;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EQLpd

Units

3.5

nA

6.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
To

1

3

6

8

11 (max)

D

0

tpLH
tpHL

0.41
0.36

0.52
0.48

0.64
0.58

0.76
0.68

0.88
0.78

GN

Q

tpLH
tpHL

0.46
0.31

0.59
0.43

0.71
0.53

0.84
0.63

0.96
0.72

Min GNWidth

Low

tw

0.49

Min D Setup

tsu

0.40

Min D Hold

th

0.00

From

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

(continued on next page)

3-72

OLOOl

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Logic Schematic
GN

)----....-----<~

G

G

GN

3-73

Q

OLDll

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DL011 is a single-phase, unbuffered D latch with active low gate transparency. RESET is active low.

Logic Symbol

Truth Table

Pin Loading
RN

Or-

-D
~

D

GN

Q

Equivalent

H

L

L

L

DL011

H

H

L

H

D

1.0

R

H

X

H

NC

GN

1.9

Y

L

X

X

L

RN

1.0

G

NC

Load

= No Change

Equivalent Gates: ................... 2.9
Bolt Syntax: ............................ Q .DL011 D GN RN;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

4.0

nA

8.8

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

3

6

8

11 (max)

D

0

tpLH
tpHL

0.46
0.37

0.66
0.48

0.87
0.60

1.09
0.71

1.31
0.80

GN

Q

tpLH
tpHL

0.46
0.29

0.68
0.42

0.90
0.53

1.12
0.64

1.34
0.74

RN

Q

tpHL

0.27

0.38

0.48

0.58

0.67

Min GN Width

Low

tw

0.47

Min RN Width

Low

tw

0.88

Min D Setup

tsu

0.43

Min D Hold

th

0.00

Min RN Setup

tsu

0.35

Min RN Hold

th

0.14

Delay will vary with input conditions. See page 2-16 for interconnect estimates.
(continued on next page)

3-74

OLDll

AMERICAN MICROSYSTEMS, INC.

AMIBS O.B micron CMOS Standard Cells
Logic Schematic

GN
}--__~---<-7

G

G

GN~G

GN

3-75

Q

.NtI.~

DL021

ArvlERlCAN MICROSYSTEMS, INC.

AMIIS 0.6 micron CMOS Standard Cells
Description:
DL021 is a single-phase, unbuffered D latch with active low gate transparency. SET is active low.

Logic Symbol

Truth Table

A
oS

-

Pin Loading
SN

GN

D

Q

Equivalent

L

X

X

H

Load

H

H

X

NC

D

1.0

H

L

L

L

GN

1.9

L

H

H

SN

1.0

Qf--

-C G

DL021

H
NC

= No Change

Equivalent Gates: ................... 2.3
Bolt Syntax: ............................ Q .DL021 D GN SN;

Power Characteristics:
Parameter
Static IDO (TJ

Value

= 85°C)

EQLpd

Units

3.8

nA

6.1

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

3

6

8

11 (max)

D

Q

tpLH
tpHL

0.38
0.39

0.52
0.52

0.64
0.66

0.78
0.79

0.93
0.92

GN

Q

tpLH
tpHL

0.43
0.31

0.54
0.46

0.67
0.59

0.81
0.72

0.96
0.85

SN

Q

tpLH

0.16

0.30

0.45

0.59

0.74

Min GN Width

Low

tw

0.40

Min SN Width

Low

tw

0.79

Min 0 Setup

tsu

0.39

Min 0 Hold

th

0.00

Min SN Setup

tsu

0.15

Min SN Hold

th

0.24

Oelay will vary with input conditions. See page 2-16 for interconnect estimates.
(continued on next page)

3-76

il.~I'®

DL021

. AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Logic Schematic

SN - 7 > - - - - - - - - - - - - - ,

GN
}---_-----<-7 Q

G

G

GN

GN~G

~I

3-77

~I'JI

OLD31

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DL031 is a single-phase, unbuffered D latch with active low gate transparency. RESET and SET are active low.

Logic Symbol

Truth Table
SN

Pin Loading
RN

D

GN

Q

L

L

X

X

IL

Equivalent

L

H

X

X

H

Load

H

L

X

X

L

D

1 .1

DL031

H

H

X

H

NC

GN

1.9

R

H

H

L

L

L

SN

1.0

I

H

H

H

L

H

RN

1.1

A
-

D S Q r-----

--C

G

NC

= No Change

IL

= Illegal

Equivalent Gates: ................... 3.0
Bolt Syntax: ............................ 0 .DL031 D GN RN SN;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EQLpd

Units

4.7

nA

8.4

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

3

6

8

11 (max)

D

0

tpLH
tpHL

0.50
0.49

0.66
0.60

0.80
0.75

0.94
0.90

1.08
1.02

GN

0

tpLH
tpHL

0.48
0.37

0.68
0.51

0.83
0.66

0.95
0.80

1.07
0.93

SN

0

tpLH

0.16

0.29

0.43

0.57

0.71

RN

0

tpHL

0.40

0.52

0.67

0.82

0.94

(continued on next page)

3-78

DL031

I,III'

~

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

Min GN Width

Low

tw

0.52

Min RNWidth

Low

tw

0.14

Min SN Width

Low

tw

0.94

Min D Setup

tsu

0.50

Min D Hold

th

0.00

Min SN Setup

tsu

0.15

Min SN Hold

th

0.35

Min RN Setup

tsu

0.54

Min RN Hold

th

0.14

3

I

6

I

8

I

11 (max)

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

GN
r-~--------~~

G
G

GN

GN~G
'I

3-79

Q

OLD"1

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DL041 is a single-phase, unbuffered D latch with active low gate transparency and without SET or RESET.

Logic Symbol

Pin Loading

Truth Table

19DL04b~

GN

D

ON

Equivalent

L

L

H

Load

L

H

L

D

1.0

H

X

NC

GN

2.1

NC

= No Change

Equivalent Gates: ................... 2.6
Bolt Syntax: ............................ ON .DL041 D GN;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EOLpd

Units

3.5

nA

6.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
To

1

3

6

8

11 (max)

D

ON

tpLH
tpHL

0.28
0.27

0.49
0.41

0.69
0.57

0.90
0.72

1.11
0.87

GN

ON

tpLH
tpHL

0.22
0.32

0.43
0.47

0.64
0.62

0.85
0.78

1.06
0.94

Min GN Width

Low

tw

0.91

Min D Setup

tsu

0.85

Min D Hold

th

0.00

From

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

(continued on next page)

3-80

OLOlll

AMERICAN MICROSYSTEMS, INC.

AM.6S 0.6 micron CMOS Standard Cells
Logic Schematic
r---------------<~

GN

G

G

GN

3-81

ON

JtMII~

DL051

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DL051 is a single-phase, unbuffered D latch with active low gate transparency. RESET is active low.

Logic Symbol

Pin Loading

Truth Table
RN

D

GN

ON

Equivalent

-D
-C G
DL051
Q 0R

H

L

L

H

H

H

L

L

D

1.0

H

X

H

NC

GN

1.9

Y

L

X

X

H

RN

1.0

NC

Load

= No Change

Equivalent Gates: ................... 3.6
Bolt Syntax: ............................ ON .DL051 D GN RN;

Power Characteristics:
Parameter
Static IDD (TJ = 85°C)
EOLpd

Value

Units

4.9

nA

11.1

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, VDD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

D

ON

GN

1

5

10

14

19 (max)

tpLH
tpHL

0.49
0.55

0.75
0.80

1.02
0.95

1.30
1.13

1.59
1.35

ON

tpLH
tpHL

0.39
0.59

0.70
0.80

0.95
0.99

1.23
1.17

1.54
1.35

RN

ON

tpLH

0.41

0.69

0.96

1.24

1.52

Min GNWidth

Low

tw

0.46

Min RN Width

Low

tw

0.62

Min D Setup

tsu

0.44

Min D Hold

th

0.00

Min RN Setup

tsu

0.33

0.14
Min RN Hold
th
Delay will vary with input conditions. See page 2-16 for interconnect estimates.
(continued on next page)

3-82

OL051

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Logic Schematic

GN

G

GN~G

G

GN

3-83

OL061

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DL061 is a single-phase, unbuffered D latch with active low gate transparency. SET is active low.

Logic Symbol

Truth Table

cS
-

D S

-C

G

DL061

Q p-

Pin Loading
SN

GN

D

ON

Equivalent

L

X

X

L

Load

H

H

X

NC

D

1.0

H

L

L

H

GN

1.9

L

H

H

SN

1.0

H
NC

= No Change

Equivalent Gates: ................... 2.6
Bolt Syntax: ............................ ON .DL061 D GN SN;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EOLpd

Units

4.6

nA

8.3

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

5

10

14

19 (max)

D

ON

tpLH
tpHL

0.49
0.50

0.74
0.66

0.97
0.84

1.19
1.02

1.40
1.19

GN

ON

tpLH
tpHL

0.43
0.50

0.67
0.70

0.90
0.88

1.12
1.05

1.34
1.22

SN

ON

tpHL

0.25

0.43

0.61

0.78

0.95

Min GN Width

Low

tw

0.40

Min SNWidth

Low

tw

0.47

tsu

0.38

Min D Hold

th

0.00

Min SN Setup

tsu

0.13

Min SN Hold

th

0.24

Min D Setup

Delay will vary with input conditions. See page 2-16 for interconnect estimates.
(continued on next page)

3-84

~.~II
I

OL061

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Log ic Schematic

SN

~.r-------------~

GN

G

G

GN

3-85

ltMlIJ

DL071

AMERICAN MICROSYSTEMS,INC.

ANI6S 0.6 micron CMOS Standard Cells
Description:
DL071 is a single-phase, unbuffered D latch with active low gate transparency. RESET and SET are active low.

Logic Symbol

SN

RN

D

GN

ON

L

L

X

X

IL

A
D S

-

Pin Loading

Truth Table

--c G

DL071

FiQ p-

I
NC

Equivalent

L

H

X

X

L

H

L

X

X

H

D

1.1

H

H

X

H

NC

GN

1.9

H

H

L

L

H

SN

1.0

H

H

H

L

L

RN

1.1

= No Change

IL

Load

= Illegal

Equivalent Gates: ................... 3.5
Bolt Syntax: ............................ ON .DL071 D GN RN SN;

Power Characteristics:
Parameter
Static 100 (TJ

= 85°C)

EQLpd

Value

Units

5.5

nA

10.3

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

D

ON

GN

1

5

10

14

19 (max)

tpLH
tpHL

0.57
0.59

0.82
0.80

1.05
0.97

1.29
1.16

1.54
1.35

ON

tpLH
tpHL

0.49
0.58

0.73
0.81

0.97
1.00

1.21
1.17

1.45
1.33

SN

ON

tpHL

0.27

0.46

0.64

0.83

1.00

RN

ON

tpLH

0.48

0.76

0.98

1.22

1.48

(continued on next page)

3-86

DL071

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min GNWidth

Low

tw

0,50

Min RN Width

Low

tw

0.15

Min SN Width

Low

tw

0.62

Min D Setup

tsu

0.49

Min D Hold

th

0.00

Min SN Setup

tsu

0.14

Min SN Hold

th

0.35

Min RN Setup

tsu

0.51

Min RN Hold

th

0.13

1

5

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

GN~G

GN

3-87

I

10

I

14

I

19 (max)

DL631

AMERICAN MICROSYSTEMS.ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DL631 is a single-phase, buffered 0 latch with active low gate transparency and without SET or RESET.

Pin Loading

Truth Table

Logic Symbol

GN

a

ON

L

L

L

H

H

L

H

L

0

1.0

H

NC

NC

GN

1.9

0
-

gI0
1° PI--

--C

DL631

X
NC

Equivalent
Load

= No Change

Equivalent Gates: ................... 3.3
Bolt Syntax: ............................ 0 ON .DL631 D GN;

Power Characteristics:
Parameter
Static IDO (TJ

Value

Units

5.8

nA

12.5

Eq-Ioad

= 85°C)

EOL pd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

D

0

D

ON

GN

1

5

10

14

19 (max)

tpLH
tpHL

0.64
0.66

0.84
0.81

1.09
0.99

1.32
1.19

1.54
1.39

tpLH
tpHL

0.55
0.52

0.77
0.69

1.03
0.88

1.26
1.06

1.49
1.22

a

tpLH
tpHL

0.64
0.54

0.88
0.75

1.11
0.94

1.35
1.12

1.58
1.29

GN

ON

tpLH
tpHL

0.43
0.52

0.72
0.74

0.94
0.92

1.18
1.09

1.45
1.24

MinGNWidth

High

tw

0.00

Min GNWidth

Low

tw

0.43

Min D Setup

tsu

0.40

Min D Hold

th

0.00

Delay will vary With input conditions. See page 2-16 for interconnect estimates.

(continued on next page)

3-88

DL631

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Logic Schematic

GN

GN~G

GN

3-89

DL6111

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DL641 is a single-phase, buffered D latch with active low gate transparency. RESET is active low.

Logic Symbol

-

-C

D

Truth Table

,I

Q

I--

GDL641

Ria pY

Pin Loading

RN

D

GN

Q

ON

Equivalent

H

L

L

L

H

Load

H

H

L

H

L

D

1.0

H

X

H

NC

NC

GN

2.1

X

L

H

RN

1.0

X

L

NC

= No Change

Equivalent Gates: ................... 3.7
BoltSyntax: ............................ O ON .DL641 D GN RN;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EQLpd

Units

6.2

nA

12.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter

From

To

1

5

10

14

19 (max)

D

a

tpLH
tpHL

0.68
0.51

0.94
0.72

1.19
0.92

1.43
1.10

1.66
1.27

D

ON

tpLH
tpHL

0.57
0.71

0.85
0.91

1.11
1.09

1.39
1.26

1.66
1.43

GN

a

tpLH
tpHL

0.69
0.43

0.99
0.66

1.22
0.84

1.46
1.03

1.71
1.21

GN

ON

tpLH
tpHL

0.48
0.74

0.79
0.95

1.04
1.12

1.30
1.29

1.60
1.49

RN

a

tpHL

0.44

0.65

0.84

1.02

1.20

RN

ON

tpLH

0.49

0.77

1.03

1.30

1.59

(continued on next page)

3-90

~il

DL6"1

.• AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min GNWidth

High

tw

0.00

Min GNWidth

Low

tw

0.69

Min RN Width

Low

tw

0.43

Min D Setup

tsu

0.69

Min D Hold

th

0.00

Min RN Setup

tsu

1.21

Min RN Hold

th

0.15

1

5

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

GN

G

GN~G

G

GN

3-91

I

10

I

14

I

19 (max)

OL651

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DL651 is a single-phase, buffered D latch with active low gate transparency. SET is active low.

Logic Symbol

Truth Table

A
DSJ.

-

--C

Q-

GDL651

J Q J-

Pin Loading
GN

L

X

X

H

L

H

H

X

NC

NC

D

1.0

H

L

L

L

H

GN

1.9

H

H

L

SN

1.0

H

D

a

SN

L
NC

QN

Equivalent
Load

= No Change

Equivalent Gates: ................... 3.6
Bolt Syntax: ............................ Q ON .DL651 D GN SN;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EQLpd

Units

6.4

nA

13.0

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

D

Q

D

ON

GN

1

5

10

14

19 (max)

tpLH
tpHL

0.65
0.69

0.90
0.86

1.10
1.04

1.33
1.21

1.60
1.38

tpLH
tpHL

0.60
0.56

0.82
0.76

1.07
0.94

1.31
1.11

1.53
1.29

Q

tpLH
tpHL

0.69
0.61

0.91
0.80

1.14
0.97

1.37
1.14

1.61
1.32

GN

ON

tpLH
tpHL

0.50
0.56

0.76
0.80

1.01
0.98

1.24
1.15

1.46
1.30

SN

Q

tpLH

0.44

0.64

0.87

1.10

1.35

SN

QN

tpHL

0.32

0.51

0.69

0.87

1.05

(continued on next page)

3-92

OL651

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min GNWidth

High

tw

0.00

Min GN Width

Low

tw

0.47

Min SNWidth

Low

tw

0.54

Min D Setup

tsu

0.44

Min D Hold

th

0.00

Min SN Setup

tsu

0.17

th

0.24

Min SN Hold

1

5

I

10

1

14

I

19 (max)

..

Delay Will vary with mput conditions. See page 2-16 for interconnect estimates .

Logic Schematic

SN

~r-----------------~

GN
)------------------<~

G

GN~G

3-93

ON

OL661

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
DL661 is a single-phase, buffered D latch with active low gate transparency. RESET and SET are active low.

Logic Symbol

Truth Table
SN

A
DS

-

-c~

Or---

DL611

Ria 0-

y

Pin Loading
RN

D

GN

Q

QN

L

L

X

X

IL

IL

Equivalent

L

H

X

X

H

L

Load

H

L

X

X

L

H

D

1.1

H

H

X

H

NC

NC

GN

1.9

H

H

L

L

L

H

SN

1.0

H

H

H

L

H

L

RN

1.1

IL

= Illegal

NC

= No Change

Equivalent Gates: .................. .4.5
Bolt Syntax: ............................ Q ON .DL661 D GN RN SN;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EQLpd

Units

7.3

nA

15.4

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

D

Q

D

QN

GN

1

5

10

14

19 (max)

tpLH
tpHL

0.77
0.78

1.00
0.91

1.21
1.07

1.44
1.26

1.69
1.45

tpLH
tpHL

0.68
0.70

0.87
0.84

1.13
1.03

1.39
1.22

1.60
1.37

Q

tpLH
tpHL

0.73
0.65

1.00
0.83

1.23
1.01

1.45
1.17

1.65
1.34

GN

QN

tpLH
tpHL

0.56
0.64

0.80
0.86

1.05
1.04

1.28
1.21

1.51
1.36

SN

Q

tpLH

0.42

0.65

0.87

1.10

1.33

0.51

0.68

0.86

1.03

0.84

1.01

1.18

1.35

SN

QN

tpHL

0.31

RN

Q

tpHL

0.67

(continued on next page)

3-94

OL661

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

5

10

14

19 (max)

RN

ON

tpLH

0.52

0.83

1.04

1.28

1.55

Min GN Width

High

tw

0.00

Min GN Width

Low

tw

0.55

Min RN Width

Low

tw

0.14

Min SN Width

Low

tw

0.67

Min D Setup

tsu

0.55

Min D Hold

th

0.00

Min SN Setup

tsu

0.17

Min SN Hold

th

0.36

Min RN Setup

tsu

0.58

Min RN Hold

th

0.13

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

G
G

GN

GN~G

3-95

EN21

AMERICAN MICROSYSTEMS,ING

AMI6S 0.6 micron CMOS Standard Cells
Description:
EN21 is a 2-input gate which performs the logical exclusive NOR (XNOR) function.

Logic Symbol

Pin Loading

lPuth Table

~=J[»-Q
EN21

A

B

0

Equivalent

L

L

H

Load

L

H

L

A

2.0

H

L

L

B

2.1

H

H

H

Equivalent Gates: ................... 1.9
Bolt Syntax: ............................ 0 .EN21 A B;

Power Characteristics:
Value

Units

Static IDD (TJ = 85°C)

Parameter

3.1

nA

EQLpd

5.8

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

=25°C, V DD =5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

0

tpLH
tpHL

1

3

6

8

11 (max)

0.31
0.32

0.45
0.44

0.69
0.53

0.93
0.67

1.20
0.80

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

(continued on next page)

3-96

EN21

AMERICAN MICROSYSTEM5, INC.

AMI6S 0.6 micron CMOS Standard Cells
Logic Schematic

LOGICAL

A
B

3-97

E021

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
E021 is a 2-input gate which performs the logical exclusive OR (XOR) function.

Logic Symbol

Pin Loading

Truth Table

~~~Q

Q

B

A

Equivalent
Load

L

L

L

L

H

H

A

2.1

H

L

H

B

2.1

H

H

L

Equivalent Gates: ................... 2.0
Bolt Syntax: ............................ Q .E021 A B;

Power Characteristics:
Parameter
Static IDD (TJ

Value

Units

1.8

nA

7.0

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

6

8

11 (max)

0.37
0.34

0.56
0.45

0.79
0.55

1.02
0.64

1.27
0.77

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

(continued on next page)

3-98

E021

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Log ic Schematic

LOGICAL

A
B

3-99

E031

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
E031 is a 3-input gate which performs the logical exclusive OR (XOR) function.

Logic Symbol

Pin Loading

Truth Table

~~[>-Q

A

B

C

Q

L

L

L

L

L

L

H

H

L

H

L

H

L

H

H

H

L

L

H

L

H

L

H

H

L

L

H

H

H

H

Equivalent
Load
A

2.1

L

B

2.1

H

C

2.1

Equivalent Gates: ................... 3.9
Bolt Syntax: ............................ Q .E031 ABC;

Power Characteristics:
Parameter
Static IDD (TJ

Units

Value

= 85°C)

EQLpd

3.6

nA

15.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

3

6

8

11 (max)

Q

0.88
0.75

1.05
0.87

1.36
0.97

1.61
1.14

1.83
1.30

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

(continued on next page)

3-100

E031

:{i

1\1
I

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Log ic Schematic

LOGICAL

A -----I
B -----I

C

3-101

.~II~

1101

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IID1 is a non-inverting clock driver with a single output.

Logic Symbol

Pin Loading

Truth Table

~

A~O
1101
A~O
1101

L

L

H

H

Equivalent
Load

1.1

A

Equivalent Gates: ................... 1.5
Bolt Syntax: ............................ 0.1101 A;

Power Characteristics:
Parameter
Static 100 (TJ

Value

Units

1.8

nA

2.8

Eq-Ioad

= 85°C)

EOLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter

From

To

A

Q

tpLH
tpHL

1

5

10

14

19 (max)

0.17
0.16

0.35
0.33

0.54
0.50

0.74
0.67

0.93
0.84

..

Delay will vary with Input conditions. See page 2-16 for interconnect estimates .

3-102

1102

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IID2 is a non-inverting clock driver with a single output.

Logic Symbol

Pin Loading

Truth Table

A~Q
ID2

~

A~Q
IID2

L

L

H

H

Equivalent
Load
A

1.1

Equivalent Gates: ................... 1.5
Bolt Syntax: ............................ Q .1102 A;

Power Characteristics:
Parameter
Static 100 (TJ

Value

Units

2.7

nA

4.3

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

A

Q

tpLH
tpHL

1

9

18

26

35 (max)

0.18
0.18

0.40
0.35

0.60
0.51

0.82
0.67

1.04
0.83

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-103

11011

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
1104 is a non-inverting clock driver with a single output.

Logic Symbol

Truth Table

A~Q
104

Pin Loading

~

A~Q
104

L

L

H

H

Equivalent
Load
A

2.0

Equivalent Gates: ................... 2.0
Bolt Syntax: ............................ 0.1104 A;

Power Characteristics:
Value

Units

Static 100 (TJ = 85°C)

Parameter

5.3

nA

EOLpd

8.4

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Oelay (ns)
Parameter
From

To

A

Q

tpLH
tpHL

4

19

35

51

67 (max)

0.20
0.22

0.40
0.39

0.59
0.53

0.78
0.68

0.98
0.83

..

Delay Will vary With Input conditions. See page 2-16 for interconnect estimates.

3-104

1106

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
1106 is a non-inverting clock driver with a single output.

Logic Symbol

Pin Loading

Truth Table

A~Q
1106

-m-

A~Q
1106

L

L

H

H

Equivalent
Load
A

2.0

Equivalent Gates: ................... 2.8
Bolt Syntax: ............................ 0.1106 A;

Power Characteristics:
Value

Parameter
Static 100 (TJ

= 85°C)

EOLpd

Units

7.1

nA

12.4

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Oelay (ns)
Parameter
From

To

A

Q

tpLH
tpHL

6

28

52

75

99 (max)

0.25
0.26

0.43
0.42

0.62
0.57

0.81
0.72

1.00
0.87

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-105

INVl

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
INV1 is an inverter which performs the logical NOT function.

Logic Symbol

Truth Table

A~Q
INV1

Pin Loading

~

A~Q
INV1

L

H

H

L

Equivalent
Load

A

1.0

Equivalent Gates: ................... 0.8
Bolt Syntax: ............................ Q .INV1 A;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EQLpd

Units

0.9

nA

1.3

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

A

To

1

5

10

14

19 (max)

Q

0.09
0.09

0.32
0.25

0.54
0.43

0.77
0.60

1.01
0.77

tpLH
tpHL

..

Delay will vary with Input conditions. See page 2-16 for Interconnect estimates.

3-106

INV2

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
INV2 is an inverter which performs the logical NOT function.

Logic Symbol

Pin Loading

Truth Table

A~Q
INV2

1:-

A~Q
INV2

L

H

H

L

Equivalent
Load
A

2.0

Equivalent Gates: ................... 1.3
Bolt Syntax: ............................ Q .INV2 A;

Power Characteristics:
Parameter

Value

Units

Static 100 (TJ = 85°C)

1.8

nA

EQLpd

2.5

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

A

To

1

9

18

26

35 (max)

Q

0.08
0.08

0.28
0.24

0.49
0.41

0.70
0.58

0.92
0.75

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-107

INV3

AMERICAN MICROSYSTEMS,ING.

AM.6S 0.6 micron CMOS Standard Cells
Description:
INV3 is an inverter which performs the logical NOT function.

Truth Table

Logic Symbol

Pin Loading

~

A~Q
INV3
A~Q
INV3

L

H

H

L

Equivalent
Load

2.9

A

Equivalent Gates: ................... 1.3
Bolt Syntax: ............................ Q .INV3 A;

Power Characteristics:
Parameter
Static 100 (TJ

Value

Units

2.7

nA

2.8

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
A

To
Q

tpLH
tpHL

1

13

26

38

51 (max)

0.07
0.06

0.27
0.22

0.47
0.37

0.69
0.53

0.90
0.68

Oelay will vary with input conditions. See page 2-16 for interconnect estimates.

3-108

INV4
AMa6S 0.6 micron CMOS Standard Cells
I

Description:
INV4 is an inverter which performs the logical NOT function.

I

Pin Loading

Truth Table

Logic Symbol

A~O
INV4

1:

A~O
INV4

L

H

H

L

Equivalent
Load
A

3.9

Equivalent Gates: ................... 1.5
Bolt Syntax: ............................ 0 .INV4 A;

. Power Characteristics:
Value

Parameter
Static 100 (TJ

= 85°C)

EQLpd

Units

3.5

nA

3.1

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
!A

To

0

tpLH
tpHL

4

19

35

51

67 (max)

0.09
0.07

0.29
0.25

0.49
0.40

0.69
0.55

0.89
0.72

Oelay will vary with input conditions. See page 2-16 for interconnect estimates.

3-109

.JtMI.I

INV5

AMERICAN MICROSYSTEMS.INC.

ANI6S 0.6 micron CMOS Standard Cells
Description:
INV5 is an inverter which performs the logical NOT function.

Logic Symbol

Truth Table

Pin Loading

A~Q
INV5

-tt:

A~Q
. INV5

L

H

H

L

Equivalent
Load
A

4.8

Equivalent Gates: ................... 1.8

Bolt Syntax: ............................ Q .INVS A;

Power Characteristics:
Parameter

Value

Units

Static IDO (TJ = 8S0C)

4.4

nA

EQLpd

4.3

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 2SoC, V OD = S.OV, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

A

Q

tpLH
tpHL

S

24

44

63

83 (max)

0.09
0.09

0.28
0.23

0.48
0.37

0.67
0.S2

0.87
0.66

Oelay will vary with input conditions. See page 2-16 for interconnect estimates.

3-110

~II®

I

INV6

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
INV6 is an inverter which performs the logical NOT function.

Logic Symbol

Truth Table

Pin Loading

A~O
INV6

-m-

A~O
INV6

L

H

H

L

Equivalent
Load
A

5.7

Equivalent Gates: ................... 2.0
Bolt Syntax: ............................ 0 .INV6 A;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EOLpd

Units

5.3

nA

5.1

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
A

To

6

28

52

75

99 (max)

Q

0.09
0.08

0.27
0.24

0.46
0.39

0.65
0.54

0.84
0.70

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-111

ITAl

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ITA 1 is a non-inverting internal tri-state buffer with active low enable.

Logic Symbol

Pin Loading

Truth Table

:=c1--

a

ITA1

A*

EN

EN

A

0

Equivalent

H

X

Z

Load

L

L

A

L

H

H

EN

1.7

0

1.3

Z = High Impedance

0

1.0

L

Equivalent Gates: ................... 1.9
Bolt Syntax: ............................ 0 .ITA1 A EN;
Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

2.7

nA

6.3

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter

From

To

A

0

Q

EN

1

16

30

45

60 (max)

tpLH
tpHL

0.33
0.28

1.59
1.21

2.95
2.14

4.36
3.08

5.81
4.01

tHZ
tLZ
tZH
tZL

0.05
0.11
0.17
0.16

1.44
1.10

2.80
2.03

4.21
2.97

5.67
3.90

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-112

ITA2

I

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ITA2 is a non-inverting internal tri-state buffer with active low enable.

Pin loading

Truth Table

logic Symbol
EN

A=t.h- O
A*.-O
ITA2

EN

EN

A

Q

Equivalent

H

X

Z

Load

L

L

L

A

1.0

L

H

H

EN

2.9

Q

2.2

Z = High Impedance

ITA2

Equivalent Gates: ................... 2.9
Bolt Syntax: ............................ QN .ITA2 A EN;

Power Characteristics:
Value

Units

Static IDD (TJ = 85°C)

Parameter

4.4

nA

EQLpd

11.5

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

A

Q

Q

EN

1

36

70

105

140 (max)

tplH
tpHl

0.32
0.32

1.43
1.07

2.59
1.81

3.81
2.56

5.09
3.32

tHZ
tlZ
tZH
tZl

0.06
0.17
0.13
0.12

1.22
0.91

2.39
1.65

3.61
2.39

4.88
3.15

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-113

ITBl

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ITB1 is an inverting internal tri-state buffer with active low enable.

Logic Symbol

Truth Table

EN

A*ON
TB1

EN

A

=a,
TB1

Pin Loading
EN

A

H

X

Z

L

L

H

L

H

L

Equivalent

ON

Load

Z = High Impedance

ON

A

1.0

EN

1.7

ON

1.3

Equivalent Gates: ................... 1.5
Bolt Syntax: ............................ ON .ITB1 A EN;

Power Characteristics:
Value

Units

Static 100 (TJ = 85°C)

Parameter

1.8

nA

EQLpd

3.8

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

A

ON

ON

EN

1

16

30

45

60 (max)

tpLH
tpHL

0.23
0.18

1.53
1.11

2.94
2.05

4.40
2.99

5.89
3.92

tHZ
tLZ
tZH
tZL

0.05
0.11
0.17
0.17

1.49
1.10

2.89
2.03

4.35
2.97

5.86
3.91

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-114

I

t_'CA~1
1

IIB2

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _

AMI6S 0.6 micron CMOS Standard Cells
Description:
ITB2 is an inverting internal tri-state buffer with active low enable.

Logic Symbol

I

Truth Table

EN

A~ON
TB2

EN

A

=az
TB2

ON

Z

Pin Loading
EN

A

H

X

Z

L

L

H

L

H

L

ON

Equivalent
Load

= High Impedance

A

3.0

EN

3.0

ON

2.2

Equivalent Gates: ................... 2.3
Bolt Syntax: ............................ ON .ITB2 A EN;

Power Characteristics:
I

Value

Parameter
Static IDD (TJ

= 85°C)

EOLpd

Units

3.5

nA

7.4

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
A

EN

To

1

36

70

105

140 (max)

ON

tpLH
tpHL

0.17
0.12

1.31
0.91

2.51
1.66

3.77
2.42

5.08
3.19

ON

tHZ
tLz
tZH
tZL

0.06
0.17
0.12
0.12

1.26
0.90

2.46
1.66

3.72
2.42

5.03
3.18

Delay will vary with Input conditions. See page 2-16 for interconnect estimates.

3-115

MlIJ

ITD1

AMERICAN MICROSYSTEMS,INC.

ANI6S 0.6 micron CMOS Standard Cells
Description:
IT01 is an inverting internal tri-state buffer with active high enable.

Logic Symbol

Truth Table

E

A~QN
ITD1

E

A~QN

Z

Pin Loading
E

A

ON

Equivalent

L

X

Z

Load

H

L

H

A

1.0

H

H

L

E

1.4

ON

1.3

= High Impedance

ITD1

Equivalent Gates: ................... 1.5
Bolt Syntax: ............................ ON .ITD1 A E;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EQLpd

Units

1.8

nA

4.2

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

A

ON

ON

E

1

16

30

45

60 (max)

tplH
tpHl

0.21
0.18

1.45
1.12

2.76
2.06

4.12
3.00

5.52
3.96

tHZ
tlZ
tZH
tZl

0.15
0.04
0.21
0.14

1.45
1.08

2.76
2.02

4.12
2.96

5.52
3.91

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-116

1102

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IT02 is an inverting internal tri-state buffer with active high enable.

Logic Symbol

Pin Loading

Truth Table

E

A~QN

E

IT02

A~QN

E

A

ON

Equivalent

L

X

Z

Load

H

L

H

A

H

H

L

E

1.9

ON

2.2

Z = High Impedance

2.9

IT02

Equivalent Gates: ................... 2.3
Bolt Syntax: ............................ ON .IT02 A E;

Power Characteristics:
Parameter
Static

IDD

(TJ

Value

Units

3.5

nA

8.2

Eq-Ioad

= 85°C)

EOLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

A

ON

ON

E

1

36

70

105

140 (max)

tplH
tpHl

0.29
0.11

1.24
0.89

2.37
1.64

3.53
2.40

4.75
3.18

tHZ
tlZ
tZH
tZl

0.26
0.05
0.20
0.09

1.24
0.84

2.33
1.60

3.42
2.37

4.54
3.13

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-117

IIEl

AMERICAN MICROSYSTEMS,ING.

AM.6S 0.6 micron CMOS Standard Cells
Description:
ITE1 is a two-phase inverting internal tri-state buffer.

pin Loading

Truth Table

Logic Symbol
EN

EN

A - - - c } : QN
ITE1
E

A~QN

E

A

ON

H

L

X

Z

L

H

L

H

L

H

H

L

L

X

H

X

IL

ITE1

H

EN

Equivalent
Load
A

1.0

L

E

0.4

IL

EN

0.7

ON

1.3

IL = Illegal

Equivalent Gates: ................... 1.2
Bolt Syntax: ............................ QN .ITE1 A E EN;

Power Characteristics:
Value

Units

Static 100 (TJ = 85°C)

0.9

nA

EOLpd

2.3

Eq-Ioad

Parameter

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

A

ON

EN
E

1

16

30

45

60 (max)

tpLH
tpHL

0.33
0.18

1.62
1.11

3.09
2.05

4.64
2.98

6.19
3.92

ON

tHZ
tZH

0.05
0.21

1.59

3.07

4.61

6.17

ON

tLz
tZL

0.04
0.18

1.12

2.05

2.99

3.93

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-118

~I'~

ITE2

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ITE2 is a two-phase inverting internal tri-state buffer.

Logic Symbol

Truth Table
EN

Pin Loading

EN

E

A

ON

Equivalent

H

L

X

Z

Load

L

H

L

H

A

2.1

L

H

H

L

E

0.7

L

L

X

IL

EN

1.3

H

H

X

IL

ON

1.6

~ON
ITE2

EN

A--Bb 0N
ITE2

IL = Illegal

Equivalent Gates: ................... 1.4
Bolt Syntax: ............................ ON .ITE2 A E EN;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EOLpd

Units

1.8

nA

3.5

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD =

5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

26

50

75

100 (max)

0.16
0.14

1.25
0.92

2.38
1.71

3.57
2.49

4.81
3.26

A

ON

tplH
tpHl

EN

ON

tHZ
tZH

0.05
0.16

1.23

2.37

3.55

4.79

E

ON

tlZ
tZl

0.04
0.14

0.93

1.71

2.49

3.28

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-119

JIOll

AMERICAN MICROSYSTEMS, INC.

AMIIS 0.6 micron CMOS Standard Cells
Description:
JK011 is a static, master-slave JK flip-flop. RESET is asynchronous and active low. Output is unbuffered and changes
state on the rising edge of the clock.

Logic Symbol

Truth Table

0-

-J
-

~K011

Pin Loading

RN

J

K

C

L

X

X

X

L

Equivalent

H

L

L

NC

Load

H

L

H

H

H

L

H

H

i
i
i
i

R

Y

H
NC

Q(n+1)

L

J

1.0

H

K

1.0

C

3.0

RN

1.0

Q(n)

= No Change

Equivalent Gates: ................... 7.1
Bolt Syntax: ............................ 0 .JK011 C J K RN;

Power Characteristics:
Parameter
Static IOD (TJ

= 85°C)

EOLpd

Value

Units

9.8

nA

27.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

C

Q

tpLH
tpHL

RN

Q

tpHL

(continued on next page)

1

3

6

8

11 (max)

0.58
0.61

0.79
0.75

1.00
0.86

1.21
0.97

1.42
1.08

0.31

0.75

0.52

0.62

0.70

3-120

JKOll

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min CWidth

High

tw

0.59

Min CWidth

Low

tw

0.74

Min RN Width

Low

tw

0.66

Min J Setup

tsu

0.74

Min J Hold

th

0.00

Min K Setup

tsu

0.62

Min K Hold

th

0.00

Min RN Setup

tsu

0.37

Min RN Hold

th

0.38

1

3

I

6

I

I

8

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

c

3-121

eN

11 (max)

JK021

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
JK021 is a static, master-slave JK flip-flop. SET is asynchronous and active low. Output is unbuffered and changes state
on the rising edge of the clock.

Logic Symbol

Truth Table
J

K

C

0(n+1)

L

X

X

X

H

H

L

L

L

H

H

H

L

H

H

H

i
i
i
i

NC

H

A
-

J S

Pin Loading

SN

0-

-

SK021
-K

NC

Equivalent
Load

L

1.0

J

H

K

1.0

Q(n)

C

3.0

SN

2.1

= No Change

Equivalent Gates: ................... 6.0
Bolt Syntax: ............................ 0 .JK021 C J K SN;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EQLpd

Units

10.2

nA

24.0

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

C

0

SN

0

(continued on next page)

1

3

6

8

11 (max)

tpLH
tpHL

0.53
0.62

0.67
0.81

0.82
0.95

0.97
1.08

1.10
1.19

tpLH

0.17

0.32

0.45

0.59

0.74

3-122

JK021

. AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min C Width

High

tw

Min C Width

Low

tw

0.72

tw

Min J Setup

tsu

0.72

Min J Hold

th

0.00

Min K Setup

tsu

0.59

Min K Hold

th

0.00

Min SN Setup

tsu

0.14

Min SN Hold

th

0.24

Low

J

6

J

1

8

0.65

0.79

Min SNWidth

3

1

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

e~eN

e

3-123

eN

11 (max)

JK031

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
JK031 is a static, master-slave JK flip-flop. SET and RESET are asynchronous and active low. Output is unbuffered and
changes state on the rising edge of the clock.

Logic Symbol

Truth Table

Pin Loading

RN

SN

J

K

C

Q(n+1)

L

L

X

X

X

IL

Equivalent

L

H

X

X

X

L

Load

H

L

X

X

X

H

J

1.0

H

H

L

L

NC

K

1.0

H

H

L

H

H

H

H

L

H

H

H

i
i
i
i

cS
J S Q-C
JK031
-K

R

Y

H

IL

= Illegal

NC

L

C

3.0

H

SN

2.2

Q(n)

RN

2.2

= No Change

Equivalent Gates: ................... 8.5
Bolt Syntax: ............................ 0 .JK031 C J K RN SN;

Power Characteristics:
Parameter

Value

Units

Static 100 (TJ = 85°C)

11.3

nA

EQLpd

30.1

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

C

Q

RN
SN

(continued on next page)

1

3

6

8

11 (max)

tpLH
tpHL

0.49
0.66

0.68
0.81

0.80
0.94

0.93
1.08

1.09
1.21

Q

tpHL

0.91

1.03

1.18

1.30

1.41

0

tpLH

0.18

0.32

0.44

0.57

0.71

3-124

~.JtMI.

JK031

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min C Width

High

tw

0.65

Min C Width

Low

tw

0.76

Min RN Width

Low

tw

0.90

Min SN Width

Low

tw

0.87

tsu

0.76

Min J Hold

th

0.00

Min K Setup

tsu

0.65

Min K Hold

th

0.00

Min RN Setup

tsu

0.37

Min RN Hold

th

0.37

Min SN Setup

tsu

0.20

Min SN Hold

th

0.25

Min J Setup

3

1

I

6

I

8

I

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

C

CN

CN

RN

[D-

SN

[D-

C

C~CN

3-125

CN

11 (max)

~I'J

JK051

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
JK051 is a static, master-slave JK flip-flop. RESET is asynchronous and active low. Output is unbuffered and changes
state on the rising edge of the clock.

Logic Symbol

Truth Table

-J
-

~K051

-K

R Q p-

Y

Pin Loading

RN

J

K

C

QN(n+1)

L

X

X

X

H

H

L

L

L

H

H

H

L

H

H

H

t
t
t
t

NC

H

NC

Equivalent
Load

H

J

1.0

L

K

1.0

QN(n)

C

3.0

RN

1.0

= No Change

Equivalent Gates: ................... 7.1
Bolt Syntax: ............................ ON .JK051 C J K RN;
Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

9.8

nA

27.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

C

ON

RN

ON

(continued on next page)

1

3

6

8

11 (max)

tpLH
tpHL

0.51
0.28

0.70
0.46

0.91
0.61

1.12
0.77

1.32
0.93

tpLH

0.76

0.94

1.16

1.37

1.57

3-126

I.~I'®

JK051

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min C Width

High

tw

1.09

Min C Width

Low

tw

0.74

Min RN Width

Low

tw

0.66

Min J Setup

tsu

0.74

Min J Hold

th

0.00

Min K Setup

tsu

0.62

Min K Hold

th

0.00

Min RN Setup

tsu

0.37

th

0.38

Min RN Hold

1

3

I

6

I

8

I

11 (max)

..

Delay will vary with mput conditions. See page 2-16 for Interconnect estimates .

Logic Schematic

CN

C~CN

C

3-127

~r---------~~

CN

ON

JK061

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
JK061 is a static, master-slave JK flip-flop. SET is asynchronous and active low. Output is unbuffered and changes state
on the rising edge of the clock.

Logic Symbol

A
-

Pin Loading

Truth Table

J S

-

SK061
-K
00-

SN

J

K

C

ON(n+1)

L

X

X

X

L

H

L

L

L

H

H

H

L

H

H

i
i
i
i

NC

H

H
NC

Equivalent
Load

H

J

1.0

L

K

1.0

C

3.0

SN

2.1

ON(n)

= No Change

Equivalent Gates: ................... 6.0
Bolt Syntax: ............................ ON .JK061 C J K SN;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EOLpd

Units

10.2

nA

24.0

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

3

6

8

11 (max)

C

ON

tpLH
tpHL

0.46
0.29

0.73
0.46

0.91
0.61

1.11
0.77

1.36
0.93

SN

ON

tpHL

0.53

0.69

0.85

1.01

1.16

(continued on next page)

3-128

JK061

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min C Width

High

tw

1.10

Min CWidth

Low

tw

0.71

Min SN Width

Low

tw

0.82

Min J Setup

tsu

0.71

Min J Hold

th

0.00

Min K Setup

tsu

0.59

Min K Hold

th

0.00

Min SN Setup

tsu

0.14

Min SN Hold

th

0.24

1

3

1

6

1

I

8

11 (max)

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic
SN ~r-------------------------------~--------------------~
r-+-----------<~

c

c

3-129

eN

ON

JK071

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
JK071 is a static, master-slave JK flip-flop. SET and RESET are asynchronous and active low. Output is unbuffered and
changes state on the rising edge of the clock.

logic Symbol

Truth Table
RN

cS
- J S
-C
JK071
-K

R

OK:>-

Y

Pin loading
SN

J

K

L

L

X

L

H

X

C

ON(n+1)

X

X

IL

Equivalent

X

X

H

Load

H

L

X

X

X

L

J

1.0

H

H

L

L

NC

K

1.0

H

H

L

H

H

C

3.0

H

H

H

L

L

SN

2.2

H

H

H

H

t
t
t
t

ON(n)

RN

2.2

IL

= Illegal

NC

= No Change

Equivalent Gates: ................... 8.5
Bolt Syntax: ............................ ON .JK071 C J K RN SN;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EOLpd

Units

11.3

nA

30.1

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

C

ON

RN
SN

(continued on next page)

1

3

6

8

11 (max)

tpLH
tpHL

0.52
0.32

0.71
0.45

0.92
0.61

1.13
0.78

1.34
0.92

ON

tpLH

0.70

0.96

1.14

1.35

1.59

ON

tpHL

0.62

0.77

0.93

1.11

1.25

3-130

JtMII~

JK071

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min CWidth

High

1
tw

1.11

Min CWidth

Low

tw

0.76

Min RN Width

Low

tw

1.35

Min SN Width

Low

tw

0.93

Min J Setup

tsu

0.76

Min J Hold

th

0.00

Min K Setup

tsu

0.65

Min K Hold

th

0.00

Min RN Setup

tsu

0.37

Min RN Hold

th

0.38

Min SN Setup

tsu

0.20

Min SN Hold

th

0.25

3

I

I

6

8

I

11 (max)

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic

,---------<-. ON
CN

C

CN
RN 8 -

SN 8 -

RN

C

C~CN

3-131

CN

JKBBl

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
JKBB1 is a static, master-slave JK flip-flop. SET and RESET are asynchronous and active low. Outputs are buffered and
change state on the rising edge of the clock.

Logic Symbol

Truth Table
SN

J

K

C

Q(n+1)

QN(n+1)

L

L

X

X

X

IL

IL

L

H

X

X

X

L

H

H

L

X

X

X

H

L

H

H

L

L

NC

K

1.0

H

L

H

L

H

C

3.0

H

H

H

L

H

L

SN

2.2

H

H

H

H

i
i
i
i

NC

H

QN(n)

Q(n)

RN

2.2

cS

~ S IQ

-

-

JKBB1
K Ft Q J-

1-

-

Pin Loading

RN

Y

IL

= Illegal

NC

Equivalent
Load
J

1.0

= No Change

Equivalent Gates: ................... 9.0
Bolt Syntax: ............................ Q QN .JKBB1 C J K RN SN;

Power Characteristics:
Parameter
Static 100 (TJ

Units

Value

= 85°C)

EQLpd

13.1

nA

35.1

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter

From

To

1

5

10

14

19 (max)

0.51
0.62

0.79
0.90

1.05
1.09

1.30
1.29

1.54
1.48

C

Q

tpLH
tpHL

C

QN

tpLH
tpHL

0.90
0.71

1.16
0.88

1.40
1.06

1.64
1.24

1.87
1.41

RN

Q

tpHL

0.84

1.13

1.33

1.52

1.72

RN

QN

tpLH

1.15

1.37

1.62

1.86

2.09

1.19

1.44

1.69

1.93

0.48

0.65

0.83

1.01

SN

Q

tpLH

0.91

SN

QN

tpHL

0.28

(continued on next page)

3-132

~

JKBBl

~I.

. AMERICAN MICROSYSTEMS,ING

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter

---

From

To

Min C Width

High

tw

0.74

Min C Width

Low

tw

0.79

Min RN Width

Low

tw

0.97

Min SN Width

Low

tw

0.63

Min J Setup

tsu

0.79

Min J Hold

th

0.00

Min K Setup

tsu

0.68

Min K Hold

th

0.00

Min RN Setup

tsu

0.43

Min RN Hold

th

0.38

Min SN Setup

tsu

0.20

th

0.25

Min SN Hold

1

5

I

10

14

I

I

..

Delay will vary with Input conditions. See page 2-16 for interconnect estimates.

Logic Schematic
RNB~~--------------------~

QNFB

RN

e~eN

e

3-133

eN

19 (max)

~IIJ

MX21

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
MX21 is a two-to-one digital multiplexer.

logic Symbol

Pin Loading

Truth Table

MX21

E11

S

10

11

Q

Equivalent

L

L

X

L

Load

L

H

X

H

10

1.0

H

X

L

L

11

1.0

H

X

H

H

S

1.6

Equivalent Gates: ................... 2.4
Bolt Syntax: ............................ Q .MX21 1011 S;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EQLpd

Units

3.1

nA

7.8

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Ix Input

Q

tpLH
tpHL

S

Q

tpLH
tpHL

1

5

10

14

19 (max)

0.35
0.33

0.57
0.53

0.78
0.71

0.99
0.89

1.21
1.07

0.54
0.47

0.70
0.69

0.91
0.86

1.12
1.04

1.32
1.22

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-134

MX212

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
MX212 is a two-to-one digital multiplexer.

Logic Symbol

Truth Table

MX212

E11

Pin Loading

S

10

11

Q

Equivalent

L

L

X

L

Load

L

H

X

H

10

1.0

H

X

L

L

11

1.1

H

X

H

H

S

1.6

Equivalent Gates: ................... 2.4
Bolt Syntax: ............................ Q .MX21210 11 S;
Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

4.0

nA

8.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Ix Input

Q

tpLH
tpHL

S

Q

tpLH
tpHL

1

9

18

26

35 (max)

0.40
0.33

0.63
0.57

0.87
0.72

1.09
0.89

1.31
1.07

0.55
0.54

0.78
0.75

1.00
0.93

1.22
1.09

1.44
1.25

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-135

MX41

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
MX41 is a four-to-one digital multiplexer.

Logic Symbol

Pin Loading

Truth Table

MX41
S1
SO
13
12
-11
10
-

Q-

10

11

12

13

S1

SO

Q

Equivalent

L

X

X

X

L

L

L

Load

H

X

X

X

L

L

H

10

1.0

X

L

X

X

L

H

L

11

1.1

X

H

X

X

L

H

H

12

1.0

X

X

L

X

H

L

L

13

1.0

X

X

H

X

H

L

H

SO

3.2

X

X

X

L

H

H

L

S1

3.1

X

X

X

H

H

H

H

Equivalent Gates: ..... .............. 5.1
BoItSyntax: ............................ Q .MX41 1011 1213 SO S1;

Power Characteristics:
Parameter
Static IDD (TJ

Units

Value

= 85°C)

EQLpd

6.2

nA

20.6

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Ix Input

Q

tpLH
tpHL

Any Sx Input

Q

tpLH
tpHL

1

5

10

14

19 (max)

0.85
0.63

1.08
0.89

1.32
1.09

1.54
1.28

1.74
1.47

1.02
0.90

1.22
1.09

1.46
1.30

1.70
1.50

1.89
1.65

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

(continued on next page)

3-136

MIll1

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Logic Schematic

so
10

-7>--------1

SON
SON

11

-7>--------1

SO
SO

SO~SON
12

-7}-------I

SON
SON

S1~S1N
13

-7>--------1

3-137

MIll

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
MX81 is an eight-to-one digital multiplexer.

Truth Table

Logic Symbol

Pin Loading
Equivalent
Load

MX81
S2
S1
SO
17
16
- 15
- 14
13
- 12
-11
10

11

1.0

11

12

1.0

L

12

13

1.1

H

13

14

1.0

14

15

1.0

15

16

1.1

L

16

17

1.0

H

17

SO

5.4

S1

3.3

S2

2.0

L

L

H

H
H

L

L

L

H

H

H

H

H

L
L
L
H
H

Q~

10

L

L

-

1.0

0

S1

-

10

SO

S2

Equivalent Gates: ................... 11.3
Bolt Syntax: ............................ 0 .MX81 10 11 12 13 14 15 16 17 SO S1 S2;

Power Characteristics:
Parameter
Static IDO (TJ

= 85°C)

EQLpd

Value
16.0

Units

45.3

Eq-Ioad

nA

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Ix Input

Q

tpLH
tpHL

Any Sx Input

Q

tpLH
tpHL

1

5

10

14

19 (max)

0.84
0.83

1.09
1.06

1.30
1.24

1.50
1.42

1.72
1.60

1.08
1.04

1.33
1.36

1.54
1.53

1.75
1.68

1.96
1.84

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

(continued on next page)

3-138

~I'®

I:~I

MI8l

'II
, , AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Logic Schematic

10

so

S1

SON
SON

S1N

->

SO~SON
11

->

12
13

->

S1N

S2

SON
SON

S1

S2N

SO
->

SO

S1

S1~S1N
14

SO

->

S2~S2N
15

->

16
17

->

S2N
SO
SO

SON
SON

S1N

S1N

S2

SON
SON
SO

->

SO

3-139

S1

JtMIIJ

MXI21

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
MXI21 is an inverting two-to-one digital multiplexer.

Logic Symbol

Pin Loading

Truth Table
10

S
MXI21

1311

11

ON

Equivalent
Load

L

L

X

H

L

H

X

L

10

1.0

H

X

L

H

11

1.0

H

X

H

L

S

1.6

Equivalent Gates: ................... 2.5
Bolt Syntax: ............................ ON .MX121 1011 S;

Power Characteristics:
Value

Parameter
Static IDD (TJ

= 85°C)

EQLpd

Units

4.0

nA

9.8

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C,

V DD

= 5.0V,

Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

5

10

14

19 (max)

1.20
1.00

1.46
1.17

1.36
1.12

1.62
1.28

Any Ix Input

ON

tpLH
tpHL

0.43
0.45

0.68
0.64

0.94
0.82

S

ON

tpLH
tpHL

0.59
0.58

0.85
0.78

1.11
0.95

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-140

MXI212

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
MXI212 is an inverting two-to-one digital multiplexer.

logic Symbol

Truth Table

Pin loading
10

11

ON

L

L

X

H

L

H

X

L

10

1.1
1.6

S
MXI212

fi11

Equivalent
Load

H

X

L

H

11

H

X

H

L

S

1.0

Equivalent Gates: ................... 3.0
Bolt Syntax: ............................ ON .MX1212 10 11 S;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EOL pd

Units

4.9

nA

11.2

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

9

18

26

35 (max)

Any Ix Input

ON

tpLH
tpHL

0.43
0.48

0.66
0.67

0.87
0.84

1.09
1.01

1.32
1.19

S

ON

tpLH
tpHL

0.61
0.66

0.81
0.81

1.03
0.98

1.25
1.15

1.48
1.30

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-141

NA21

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
NA21 is a 2-input gate which performs the logical NAND function.

Logic Symbol

Pin Loading

Truth Table

~=C>-0
NA21

~=[)-o

0

A

B

L

L

H

Equivalent
Load

L

H

H

A

1.0

H

L

H

B

1.0

H

H

L

NA21

Equivalent Gates: ................... 1.0
Bolt Syntax: ............................ 0 .NA21 A B;

Power Characteristics:
Parameter
Static 100 (TJ

Units

Value

= 85°C)

EQLpd

1.6

nA

1.7

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

3

6

8

11 (max)

0

0.13
0.11

0.25
0.25

0.40
0.37

0.55
0.50

0.69
0.64

tpLH
tpHL

Oelay will vary with input conditions. See page 2-16 for interconnect estimates.

3-142

NA22

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
NA22 is a 2-input gate which performs the logical NAND function.

logic Symbol

Pin loading

Truth Table
A

~=L>-Q
NA22

~=r>-Q
NA22

Q

B

Equivalent
Load

L

L

H

L

H

H

A

2.0

H

L

H

B

1.9

H

H

L

Equivalent Gates: ................... 1.5
Bolt Syntax: ............................ Q .NA22 A B;

Power Characteristics:
Value

Parameter
\I>

Static IDD (TJ = 85°C)
EQLpd

Units

3.1

nA

3.8

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

5

10

14

19 (max)

Q

0.08
0.09

0.21
0.21

0.33
0.32

0.45
0.44

0.57
0.55

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-143

NA31

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
NA31 is a 3-input gate which performs the logical NAND function.

Logic Symbol

Truth Table

g=c>-o
NA31
A
-oDB-o
C-o
NA31

a

Pin Loading

A

B

C

a

Equivalent

L

X

X

H

Load

X

L

X

H

A

1.0

X

X

L

H

B

1.0

H

H

H

L

C

1.0

,

Equivalent Gates: ................... 1.3
Bolt Syntax: ............................ 0 .NA31 ABC;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EOLpd

Units

2.1

nA

2.8

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, VDD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

Q

tpLH
tpHL

1

3

4

6

8 (max)

0.12
0.13

0.23
0.26

0.33
0.36

0.43
0.47

0.54
0.59

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-144

NA32

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
NA32 is a 3-input gate which performs the logical NAND function.

logic Symbol

Pin loading

Truth Table

~=LY-0
NA32

A
-oD- 0
B-o
C-o
NA32

A

B

C

0

L

X

X

H

X

L

X

H

Equivalent
Load
A

2.0

X

X

L

H

B

2.0

H

H

H

L

C

2.0

Equivalent Gates: ................... 2.0
Bolt Syntax: ............................ 0 .NA32 ABC;

Power Characteristics:
Parameter
Static IDD (TJ
EOLpd

= 85°C)

Value

Units

4.2

nA

4.6

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

0

Delay will

tpLH
tpHL

1

4

7

10

14 (max)

0.11
0.11

0.19
0.21

0.28
0.31

0.38
0.40

0.47
0.49

vary with input conditions. See page 2-16 for interconnect estimates.

l

3-145

NA161

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
NA41 is a 4-input gate which performs the logical NAND function.

Logic Symbol

Truth Table

~~o
NA41

~QQ

Pin Loading

A

B

C

D

Q

Equivalent

L

X

X

X

H

Load

X

L

X

X

H

A

1.0

X

X

L

X

H

B

1.0

X

X

X

L

H

C

1.0

H

H

H

H

L

D

1.0

Equivalent Gates: ................... 1.5
Bolt Syntax: ............................ 0 .NA41 ABC D;

Power Characteristics:
Parameter
Static IDD (TJ

Units

Value

= 85°C)

EQLpd

2.5

nA

3.8

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

2

4

5

7 (max)

Q

0.16
0.18

0.26
0.27

0.35
0.38

0.45
0.49

0.55
0.59

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-146

NA"2

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
NA42 is a 4-input gate which performs the logical NAND function.

Logic Symbol

Truth Table

~~Q

Pin Loading

A

B

C

D

Q

Equivalent

L

X

X

X

H

NA42

X

L

X

X

H

A

2.0

A~

X

X

L

X

H

B

2.1

X

X

X

L

H

C

2.0

H

H

H

H

L

D

2.0

8

NA42 Q

Load

Equivalent Gates: ................... 2.8
Bolt Syntax: ............................ Q .NA42 ABC D;

Power Characteristics:
Value

Units

Static IDD (TJ = 85°C)

Parameter

5.0

nA

EQLpd

6.2

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

6

8

11 (max)

0.12
0.14

0.20
0.21

0.27
0.30

0.35
0.39

0.43
0.47

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-147

NA51

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
NA51 is a 5-input gate which performs the logical NAND function.

Logic Symbol

Truth Table

~nQ
~~Q

Pin Loading
D

E

0

X

X

X

H

X

X

X

H

A

B

C

L

X

X

L

Equivalent
Load
A

1.0
1.1

X

X

L

X

X

H

B

X

X

X

L

X

H

C

1.1

X

X

X

X

L

H

D

1.0

H

H

H

H

H

L

E

1.0

Equivalent Gates: ................... 2.2
Bolt Syntax: ............................ 0 .NA51 ABC D E;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EQLpd

Units

2.9

nA

4.3

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, VDD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

Q

tpLH
tpHL

1

2

3

5

6 (max)

0.19
0.17

0.26
0.29

0.36
0.39

0.45
0.49

0.53
0.58

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-148

NA52

AMERICAN MICROSYSTEMS.ING

AMI6S 0.6 micron CMOS Standard Cells
Description:
NA52 is a 5-input gate which performs the logical NAND function.

logic Symbol

Truth Table

AD

8

2

~~
B

2

g

Q

Q

NA52

Pin loading

A

B

C

D

E

Q

Equivalent

L

X

X

X

X

H

Load

X

L

X

X

X

H

A

1.0

X

X

L

X

X

H

B

1.0

X

X

X

L

X

H

C

1.0

X

X

X

X

L

H

D

1.0

H

H

H

H

H

L

E

1.0

Equivalent Gates: ................... 3.3
Bolt Syntax: ............................ Q .NA52 ABC DE;
Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

6.3

nA

12.2

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

5

7

9 (max)

0.38
0.46

0.42
0.54

0.47
0.58

0.52
0.62

0.58
0.67

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-149

.~ll

NA6l

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
NA61 is a 6-input gate which performs the logical NAND function.

Pin Loading

Truth Table

Logic Symbol

B

C

D

E

F

Q

Equivalent

X

X

X

X

X

H

Load

X

L

X

X

X

X

H

A

1.0

X

X

L

X

X

X

H

B

1.0

X

X

X

L

X

X

H

C

1.0

X

X

X

X

L

X

H

D

1.0

X

X

X

X

X

L

H

E

1.0

H

H

H

H

H

H

L

F

1.0

A
L

Ht~{;Q
;~Q

Equivalent Gates: ................... 3.3
Bolt Syntax: ............................ Q .NA61 ABC D E F;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

6.0

nA

12.0

Eq-Ioad

See page 2·14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

5

10

14

19 (max)

0.36
0.49

0.61
0.65

0.85
0.85

1.10
1.03

1.36
1.19

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-150

NA8l

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
NA81 is an 8-input gate which performs the logical NAND function.

Logic Symbol

Truth Table

iRa
iRa

Pin Loading

A

B

C

D

E

F

G

H

Q

L

x

x

X

x

x

x

X

H

X

L

X

X

X

X

X

X

H

Equivalent
Load

A

1.0

X

X

L

X

X

X

X

X

H

B

1.0

X

X

X

L

X

X

X

X

H

C

1.0

X

X

X

X

L

X

X

X

H

D

1.0

X

X

X

X

X

L

X

X

H

E

1.0

X

X

X

X

X

X

L

X

H

F

1.0

X

X

X

X

X

X

X

L

H

G

1.0

H

H

H

H

H

H

H

H

L

H

1.0

Equivalent Gates: .................. .4.1
Bolt Syntax: ............................ 0 .NA81 ABC D E F G H;
Power Characteristics:
Parameter

Value

Units

Static 100 (TJ = 85°C)

6.8

nA

EOL pd

12.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

5

10

14

19 (max)

0

0.40
0.48

0.65
0.70

0.90
0.87

1.16
1.05

1.41
1.23

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-151

N021

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
N021 is a 2-input gate which performs the logical NOR function.

Logic Symbol

Pin Loading

Truth Table
B

Q

L

L

H

L

H

L

A

1.0

H

L

L

B

1.0

H

H

L

A

~=[>-Q
N021

~=L)-Q

Equivalent
Load

N021

Equivalent Gates: ................... 1.1
Bolt Syntax: ............................ Q .N021 A B;

Power Characteristics:
Parameter
Static IDO (TJ

Value

Units

0.9

nA

2.1

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

6

8

11 (max)

0.14
0.10

0.36
0.19

0.55
0.29

0.76
0.39

0.98
0.49

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-152

N022

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
N022 is a 2-input gate which performs the logical NOR function.

Logic Symbol

Truth Table

~=L>-0
N022

~=L)-o
N022

Pin Loading
A

B

0

Equivalent

L

L

H

Load

L

H

L

A

2.0

H

L

L

B

2.0

H

H

L

Equivalent Gates: ................... 1.6
Bolt Syntax: ............................ 0 .N022 A B;

Power Characteristics:
Parameter

Value

Units

Static IDD (TJ = 85°C)

1.8

nA

EQLpd

3.4

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

5

10

14

19 (max)

0.12
0.07

0.30
0.16

0.50
0.24

0.70
0.32

0.90
0.41

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-153

N031

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
N031 is a 3-input gate which performs the logical NOR function.

Logic Symbol

Pin Loading

Truth Table

~=r>-Q
N031

~£)-Q
N031

A

B

C

Q

Equivalent

L

L

L

H

Load

H

X

X

L

A

1.0

X

H

X

L

B

1.0

X

X

H

L

C

1.0

Equivalent Gates: ................... 1.4
Bolt Syntax: ............................ Q .N031 ABC;

Power Characteristics:
Parameter
Static IDD (TJ

Units

Value

= 85°C)

EQLpd

1.2

nA

3.2

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To
Q

tpLH
tpHL

1

3

4

6

8 (max)

0.20
0.11

0.43
0.18

0.65
0.25

0.86
0.33

1.09
0.40

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-154

N032

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
N032 is a 3-input gate which performs the logical NOR function.

Truth Table

Logic Symbol

Pin Loading

A

~=r>-Q
N032

~=rJ-Q
N032

B

C

Q

L

L

L

H

H

X

X

L

X

H

X

X

X

H

Equivalent
Load
A

1.9

L

B

2.0

L

C

2.0

Equivalent Gates: ................... 2.2
Bolt Syntax: ............................ Q .N032 ABC;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

2.4

nA

5.4

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

4

7

10

13 (max)

0.15
0.09

0.33
0.16

0.53
0.23

0.73
0.30

0.93
0.37

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-155

N041

AMERICAN MICROSYSTEMS,1I\lC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
N041 is a 4-input gate which performs the logical NOR function.

logic Symbol

Pin loading

Truth Table

~~Q

§L)---o
N041

A

B

C

0

Q

Equivalent

L

L

L

L

H

Load

H

X

X

X

L

A

1.0

X

H

X

X

L

B

1.0

X

X

H

X

L

C

1.0

X

X

X

H

L

0

1.0

Equivalent Gates: ................... 1.5
BoltSyntax: ............................ Q .N041 ABC 0;

Power Characteristics:
Value

Parameter
Static 100 (TJ

= 85°C)

EQLpd

Units

1.4

nA

4.1

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter

From
Any Input

To

1

2

4

5

7 (max)

a

0.22
0.13

0.46
0.19

0.69
0.25

0.93
0.32

1.17
0.40

tpLH
tpHL

Oelay will vary with input conditions. See page 2-16 for interconnect estimates.

3-156

N042

. AMERICAN MICROSYSTEM8,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
N042 is a 4-input gate which performs the logical NOR function.

Logic Symbol

Truth Table
A

~~Q
~~Q
N042

Pin Loading
B

C

D

0

L

L

L

L

H

H

X

X

X

L

X

H

X

X

X

X

H

X

X

X

X

H

Equivalent
Load
A

1.0

L

B

1.0

L

C

1.0

L

D

1.0

Equivalent Gates: ................... 2.8
Bolt Syntax: ............................ 0 .N042 ABC D;

Power Characteristics:
Parameter
Static 100 (TJ

= 85°C)

EQLpd

Value

Units

4.2

nA

10.4

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

6

8

11 (max)

0.46
0.37

0.57
0.46

0.70
0.57

0.83
0.67

0.97
0.76

Oelay will vary with input conditions. See page 2-16 for interconnect estimates.

3-157

N051

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
N051 is a 5-input gate which performs the logical NOR function.

Logic Symbol

Truth Table
A

A~

Q

~
~nQ
N051

Pin Loading

B

D

C

E

0

L

L

L

L

L

H

H

X

X

X

X

L

X

H

X

X

X

X

X

H

X

X

X

X

X

H

X

X

X

X

Equivalent
Load
A

1.0

L

B

1.0

L

C

1.0

X

L

D

1.0

H

L

E

1.0

Equivalent Gates: ................... 1.8
Bolt Syntax: ............................ 0 .N051 ABC D E;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EQLpd

Units

1.6

nA

5.2

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

2

3

5

6 (max)

Q

0.22
0.14

0.48
0.20

0.70
0.27

0.94
0.33

1.19
0.40

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-158

N052

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
N052 is a 5-input gate which performs the logical NOR function.

Logic Symbol

Pin Loading

Truth Table
A

§

An
N052

§

N052 Q

D

C

E

Q

Equivalent

L

L

L

L

L

H

H

X

X

X

X

L

X

H

X

X

X

L

B

1.0

X

X

H

X

X

L

C

1.0

X

X

X

H

X

L

D

1.0

X

X

X

X

H

L

E

1.0

A

B~Q

B

Load
A

1.0

Equivalent Gates: ................... 3.7
Bolt Syntax: ............................ Q .N052 ABC D E;

Power Characteristics:
Value

Parameter
Static IDD (TJ

= 85°C)

EQLpd

Units

5.1

nA

12.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

3

5

7

9 (max)

Q

0.48
0.39

0.50
0.43

0.54
0.49

0.59
0.54

0.65
0.58

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-159

ONll

AMERICAN MICROSYSTEMS.INC.

AM.6S 0.6 micron CMOS Standard Cells
Description:
ON11 is an OR-NAND circuit consisting of two 2-input OR gates into a 2-input NAND gate.

Logic Symbol

Pin Loading

Truth Table
0

B

C

D

L

L

X

X

H

X

X

L

L

H

A
ON11

A

All other combinations

Equivalent
Load

L

A

1.0

B

1.0

C

1.0

D

1.0

Equivalent Gates: ................... 1.6
Bolt Syntax: ............................ 0 .ON11 ABC D;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

1.8

nA

4.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

0

tpLH
tpHL

1

3

6

8

11 (max)

0.20
0.24

0.42
0.40

0.64
0.56

0.85
0.73

1.07
0.90

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-160

ON21

AMERICAN MICROSYSTEMS, INC.

AM.6S 0.6 micron CMOS Standard Cells
Description:
ON21 is an OR-NAND circuit consisting of one 2-input OR gate into a 2-input NAND gate.

Logic Symbol

Pin Loading

Truth Table
B

C

Q

L

L

X

H

X

X

L

H

A

1.0

L

B

1.0

C

1.0

A

All other combinations

Equivalent
Load

Equivalent Gates: ................... 1.3
Bolt Syntax: ............................ Q .ON21 ABC;

Power Characteristics:
Parameter
Static 100 (TJ

Value

Units

1.5

nA

3.1

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

6

8

11 (max)

0.15
0.16

0.36
0.31

0.57
0.48

0.79
0.64

1.00
0.81

Oelay will vary with input conditions. See page 2-16 for interconnect estimates.

3-161

ON31

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ON31 is an OR-NAND circuit consisting of a 2-input OR gate and two direct inputs into a 3-input NAND gate.

Logic Symbol

Pin Loading

Truth Table
A
ON31

B

C

D

Q

L

L

X

X

H

X

X

L

X

H

X

X

X

L

All other combinations

Equivalent
Load
A

1.0

H

B

1.0

L

C

1.0

D

1.0

Equivalent Gates: ................... 1.7
Bolt Syntax: ............................ Q .ON31 ABC D;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

2.3

nA

4.2

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

4

6

8 (max)

0.23
0.18

0.38
0.33

0.56
0.45

0.73
0.58

0.90
0.73

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-162

'II

ON41

1;'1

I,

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ON41 is an OR-NAND circuit consisting of one 3-input OR gate into a 2-input NAND gate.

Logic Symbol

Pin Loading

Truth Table
B

A

C

D

Q

L

L

L

X

H

X

X

X

L

H

All other combinations

Equivalent
Load

L

A

1.0

B

1.0

C

1.0

D

1.0

Equivalent Gates: ................... 1.6
Bolt Syntax: ............................ Q .ON41 ABC D;

Power Characteristics:
Parameter
Static IDO (TJ

= 85°C)

EQLpd

Value

Units

1.6

nA

4.8

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

4

6

8 (max)

0.22
0.20

0.41
0.31

0.61
0.44

0.81
0.57

1.01
0.69

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-163

ON51

AMERICAN MICROSYSTEMS,ING.

AMI6S 8.6 micron CMOS Standard Cells
Description:
ON51 is an OR-NAND circuit consisting of one 3-input OR gate and one 2-input NAND gate into a 2-input NOR gate.

Pin Loading

Truth Table

Logic Symbol

Equivalent
A
ON51

B

C

D

E

0

Load

L

L

L

X

X

H

A

1.0

X

X

X

L

L

H

B

1.0

L

C

1.0

D

1.0

E

1.0

All other combinations

Equivalent Gates: ................... 1.8
Bolt Syntax: ............................ 0 .ON51 ABC D E;
Power Characteristics:
Parameter
Static IDD (TJ

Value

Units

1.9

nA

5.9

Eq-Ioad

= 85°C)

EOLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, VDD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

0

tpLH
tpHL

1

3

4

6

8 (max)

0.28
0.28

0.46
0.41

0.67
0.55

0.88
0.70

1.08
0.83

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-164

ON6l

AMERICAN MCROSYSTEMS, INC.

AMIIS 0.1 micron CMOS Standard Cells
Description:
ON61 is an OR-NAND circuit consisting of two 3-input OR gates into a 2-input NAND gate.

Logic Symbol

Truth Table

Pin Loading
Equivalent

ON61

A

B

C

D

E

F

Q

L

L

L

X

X

X

H

X

X

L

L

L

X

All other combinations

Load
A

1.0

H

B

1.0

L

C

1.0

D

1.0

E

1.0

F

1.0

Equivalent Gates: ................... 2.3
Bolt Syntax: ............................ Q .ON61 ABC D E F;

Power Characteristics:
Parameter

Value

Units

Static 100 (TJ = 85°C)

2.0

nA

EQLpd

7.0

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

3

4

6

8 (max)

Q

0.23
0.41

0.47
0.54

0.66
0.70

0.86
0.87

1.08
1.05

tpLH
tpHL

..

Delay will vary with Input conditions. See page 2-16 for Interconnect estimates .

3-165

ON71

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ON71 is an OR-NAND circuit consisting of one 3-input OR gate into a 3-input NAND gate.

Logic Symbol

Truth Table

Pin Loading
Equivalent

A

B

C

D

E

0

L

L

L

X

X

H

Load
A

1.0

X

X

X

L

X

H

B

1.0

X

X

X

X

L

H

C

1.0

L

D

1.0

E

1.0

All other combinations

Equivalent Gates: ................... 1.9
Bolt Syntax: ............................ 0 .ON71 ABC D E;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EOLpd

Units

2.3

nA

5.4

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

3

4

6

8 (max)

Q

0.22
0.24

0.41
0.38

0.60
0.54

0.79
0.69

0.98
0.84

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-166

DNIl

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ON81 is an OR-NAND circuit consisting of two 2-input OR gates into a 3-input NAND gate.

logic Symbol

Truth Table

Pin loading
Equivalent

A

8

C

D

E

Q

L

L

X

X

X

H

Load
A

1.0

X

X

L

L

X

H

8

1.0

X

X

X

X

L

H

C

1.0

L

D

1.0

E

1.0

All other combinations

Equivalent Gates: ................... 2.3
Bolt Syntax: ............................ Q .ON81 ABC D E;

Power Characteristics:
Parameter
Static 'DO (TJ

Value

= 85°C)

EQLpd

Units

2.2

nA

5.6

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

3

4

6

8 (max)

Q

0.22
0.28

0.37
0.40

0.54
0.55

0.70
0.71

0.87
0.84

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-167

ON91

AMERICAN MICROSYSTEMS,ING

AMI6S 0.6 micron CMOS Standard Cells
Description:
ON91 is an OR-NAND circuit consisting of one 3-input OR gate and one 2-input OR gate into a 3-input NAND gate.

Logic Symbol

Pin Loading

Truth Table

Equivalent
ON91

A

B

C

D

E

F

Q

L

L

L

X

X

X

H

X

X

X

L

L

X

H

B

1.0

X

X

X

X

X

L

H

C

1.0

L

D

1.0

E

1.0

F

1.0

All other combinations

Load
A

1.0

Equivalent Gates: ................... 2.9
Bolt Syntax: ............................ Q .ON91 ABC D E F;

Power Characteristics:
Parameter
Static IDD (TJ

Units

Value

= 85°C)

EQLpd

2.2

nA

7.0

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To
Q

tpLH
tpHL

1

3

4

6

8 (max)

0.29
0.31

0.48
0.47

0.69
0.62

0.90
0.78

1.10
0.94

Delay will vary with Input conditions. See page 2-16 for Interconnect estimates.

3-168

ONAl

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ONA 1 is an OR-NAND circuit consisting of two 3-input OR gates into a 3-input NAND gate.

Pin loading

Truth Table

logic Symbol

Equivalent
ONA1

A

B

C

D

E

F

G

Q

L

L

L

X

X

X

X

H

X

X

X

L

L

L

X

X

X

X

X

X

X

L

All other combinations

Load

A

1.0

H

B

1.0

H

C

1.0

L

D

1.0

E

1.0

F

1.0

G

1.0

Equivalent Gates: ................... 2.8
Bolt Syntax: ............................ Q .ONA1 ABC D E F G;

Power Characteristics:
Value

Units

Static IDD (TJ = 85°C)

2.6

nA

EQLpd

8.1

Eq-Ioad

Parameter

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

4

6

8 (max)

0.28
0.47

0.49
0.67

0.70
0.86

0.91
1.05

1.11
1.24

Delay will vary with input conditions. See page 2-16 for Interconnect estimates.

3-169

DNBl

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ONB1 is an OR-NAND circuit consisting of three 2-input OR gates into a 3-input NAND gate.

Logic Symbol

Pin Loading

Truth Table

Equivalent
Q

H

A

1.0

A

B

C

D

E

F

L

L

X

X

X

X

H

B

H

C

1.0

L

D

1.0

E

1.0

F

1.0

X

X

L

L

X

X

X

X

X

X

L

L

All other combinations

Load
1.0

Equivalent Gates: ................... 2.5
Bolt Syntax: ............................ O .ONB1 ABC D E F;

Power Characteristics:
Parameter
Static 100 (TJ
EOL pd

= 85°C)

Value

Units

2.7

nA

6.8

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

4

6

8 (max)

0.24
0.43

0.44
0.57

0.59
0.75

0.75
0.92

0.93
1.08

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-170

ONCl

I.!

:i
AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ONC1 is an OR-NAND circuit consisting of one 3-input OR gate and two 2-input OR gates into a 3-input NAND gate.

Logic Symbol

Pin Loading

Truth Table

Equivalent
ONC1

A

B

C

D

E

F

G

0

L

L

L

X

X

X

X

H

X

X

X

L

L

X

X

H

B

1.0

X

X

X

X

X

L

L

H

C

1.0

L

D

1.0

E

1.0

F

1.0

G

1.0

All other combinations

Load
A

1.0

Equivalent Gates: ................... 2.9
Bolt Syntax: ............................ 0 .ONC1 ABC D E F G;

Power Characteristics:
Parameter
Static IDD (TJ

Value

Units

2.8

nA

8.1

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

4

6

8 (max)

0.33
0.46

0.52
0.66

0.74
0.85

0.95
1.03

1.14
1.23

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-171

ONOl

AMERICAN MICROSYSTEMS. INC.

AMIIS 0.6 micron CMOS Standard Cells
Description:
OND1 is an OR-NAND circuit consisting of two 3-input OR gates and one 2-input OR gate into a 3-input NAND gate.

Pin Loading

Truth Table

Logic Symbol

Equivalent
Load
OND1

A

B

C

D

E

F

G

H

Q

A

1.0

L

L

L

X

X

X

X

X

H

B

1.0

X

X

X

L

L

L

X

X

H

C

1.0

X

X

X

X

X

X

L

L

H

0

1.0

L

E

1.0

F

1.0

G

1.0

H

1.0

All other combinations

Equivalent Gates: ................... 2.9
Bolt Syntax: ............................ Q .OND1 ABC D E F G H;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

2.9

nA

8.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

3

4

6

8 (max)

0.34
0.59

0.55
0.81

0.77
1.02

0.98
1.23

1.19
1.43

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-172

I

L~R~I

ONEl
AMI6S 0.6 micron CMOS Standard Cells

Description:
ONE1 is an OR-NAND circuit consisting of three 3-input OR gates into a 3-input NAND gate.

Logic Symbol

Pin Loading

Truth Table

Equivalent
Load
A

ONE1

B

C

D

E

F

G

H

I

Q

A

1.0
1.0

L

L

L

X

X

X

X

X

X

H

B

X

X

X

L

L

L

X

X

X

H

C

1.0

X

X

X

X

X

X

L

L

L

H

D

1.0

All other combinations

L

E

1.0

F

1.0

G

1.0

H

1.0
1.0

Equivalent Gates: ................... 3.1
Bolt Syntax: ............................ Q .ONE1 ABC D E F G H I;

Power Characteristics:
Parameter

Value

Units

Static IDD (TJ = 85°C)

2.9

nA

EQLpd

9.7

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

3

4

6

8 (max)

Q

0.40
0.63

0.62
0.88

0.87
1.09

1.11
1.27

1.33
1.45

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-173

0821

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
OR21 is a 2-input gate which performs the logical OR function.

Logic Symbol

Pin Loading

Truth Table

~=[)-Q
OR21

~~Q
OR21

A

B

Q

L

L

L

Equivalent
Load

L

H

H

A

1.0

H

L

H

B

1.0

H

H

H

Equivalent Gates: ................... 1.5
Bolt Syntax: ............................ Q .OR21 A B;

Power Characteristics:
Parameter
Static IDO (TJ

= 85°C)

EQLpd

Value
1.8

Units

4.4

Eq-Ioad

nA

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, Voo

= 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

5

10

14

19 (max)

Q

0.22
0.29

0.45
0.47

0.69
0.66

0.94
0.83

1.18
1.00

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-174

OR22

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
OR22 is a 2-input gate which performs the logical OR function.

Logic Symbol

Truth Table

Pin Loading
B

A

~=L>-Q
OR22

~=r=>-Q
OR22

Q

Equivalent

L

L

L

L

H

H

A

1.0

B

1.0

H

L

H

H

H

H

Load

Equivalent Gates: ................... 1.5
Bolt Syntax: ............................ Q .OR22 A B;

Power Characteristics:
Value

Parameter
Static 100 (TJ

= 85°C)

EQLpd

Units

2.7

nA

5.7

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To
Q

tpLH
tpHL

1

9

18

26

35 (max)

0.20
0.32

0.44
0.51

0.64
0.69

0.86
0.86

1.09
1.02

Oelay will vary with input conditions. See page 2-16 for interconnect estimates.

3-175

OR31

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
OR31 is a 3-input gate which performs the logical OR function.

Truth Table

Logic Symbol

Pin Loading
A

~=C>-O
OR31

~=rJ-0
OR31

B

0

C

Equivalent
Load

L

L

L

L

H

X

X

H

A

1.0

X

H

X

H

B

1.0

X

X

H

H

C

1.0

Equivalent Gates: ................... 1.7
Bolt Syntax: ............................ 0 .OR31 ABC;

Power Characteristics:
Value

Units

Static IDD (TJ = 85°C)

1.8

nA

EQLpd

5.5

Eq-Ioad

Parameter

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

5

10

14

19 (max)

0.21
0.34

0.43
0.53

0.65
0.73

0.87
0.92

1.09
1.09

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-176

OR32

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
OR32 is a 3-input gate which performs the logical OR function.

Logic Symbol

Truth Table

~=L>-Q
OR32

~=L)-Q
OR32

Pin Loading
A

B

C

Q

Equivalent

L

L

L

L

Load

H

X

X

H

A

X

H

X

H

B

1.1

X

X

H

H

C

1.0

1.0

Equivalent Gates: ................... 2.2
Bolt Syntax: ............................ 0 .OR32 ABC;

Power Characteristics:
Parameter

Value

Units

Static IDD (TJ = 85°C)

2.7

nA

EOL pd

6.7

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To
Q

tpLH
tpHL

1

9

18

26

35 (max)

0.21
0.39

0.44
0.64

0.63
0.82

0.83
0.99

1.05
1.17

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-177

OR41

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
OR41 is a 4-input gate which performs the logical OR function.

Logic Symbol

Pin Loading

Truth Table
A

~~Q
~~Q
OR41

B

D

C

Q

L

L

L

L

L

H

X

X

X

H

X

H

X

X

X

X

H

X

X

X

X

H

Equivalent
Load
A

1.0

H

B

1.0

H

C

1.0

H

D

1.0

Equivalent Gates: ................... 2.0
Bolt Syntax: ............................ Q .OR41 ABC D;

Power Characteristics:
Parameter
Static IDD (TJ

Value

Units

1.9

nA

6.3

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Any Input

Q

tpLH
tpHL

1

5

10

14

19 (max)

0.23
0.36

0.44
0.60

0.66
0.82

0.91
1.07

1.19
1.36

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-178

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
OR42 is a 4-input gate which performs the logical OR function.

logic Symbol

Truth Table

§~Q
~~Q
OR42

Pin loading

A

B

C

D

Q

Equivalent

L

L

L

L

L

Load

H

X

X

X

H

A

1.0

X

H

X

X

H

B

1.0

X

X

H

X

H

C

1.0

X

X

X

H

H

D

1.0

Equivalent Gates: ................... 2.2
Bolt Syntax: ............................ Q .OR42 ABC D;

Power Characteristics:
Parameter

Value

Units

Static IDD (TJ = 85°C)

2.7

nA

EQLpd

7.6

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
Any Input

To

1

9

18

26

35 (max)

Q

0.25
0.45

0.48
0.71

0.70
0.91

0.91
1.10

1.13
1.28

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-179

SLFAl

AMERICAN MICROSYSTEMS.ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
SLFA 1 is a static, master-slave, multiplexed scan latch,O flip-flop. When SCE is low it is a 0 flip-flop with the output
unbuffered and changes state on the rising edge of the clock. When SCE is high it is a 0 latch.

Logic Symbol

-0
-

-

Pin Loading

Truth Table

0

r--

C SLFA1
SO
SE
SCE

C

0

SO

SE

i
i
i
i

H

X

L

X

X

H

X

L

L

X

X

L

H

X

L

L

L

X

L

X

H

X

SCE

Q

L

L

H

L

L

L

H

L

H

L

X

L

L

H

X

L

H

L

H

H

H

H

L

H

H

L

X

X

H

NC

Equivalent
Load
C

4.1

H

0

1.0

L

SO

1.0

NC

SE

2.1

H

SCE

2.1

NC = No Change
Equivalent Gates: ................... 7.6
Bolt Syntax: ............................ 0 .SLFA1 CD SCE SO SE;
Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EQLpd

Units

9.8

nA

30.1

Eq-Ioad

Delay Characteristics:
Conditions: T J = 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

C

0

0
SCE

(continued on next page)

1

5

10

14

19 (max)

tpLH
tpHL

0.91
0.82

1.25
1.07

1.40
1.21

1.51
1.44

1.59
1.68

0

tpLH
tpHL

1.02
1.04

1.20
1.19

1.57
1.45

2.11
1.80

2.80
2.23

Q

tpLH
tpHL

0.89
0.96

1.13
1.11

1.38
1.39

1.62
1.87

1.85
2.53

3-180

SLFAl

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

Min CWidth

High

tw

Min C Width

Low

tw

0.63

Min D Setup

tsu

0.63

Min D Hold

th

0.00

Min SD Setup

tsu

0.63

Min SD Hold

th

0.00

Min SE Setup

tsu

0.72

Min SE Hold

th

0.00

Min SCE Setup

tsu

0.96

Min SCE Hold

th

0.71

1

5

I

10

14

I

I

19 (max)

0.85

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Logic Schematic
C

GN

CN

G

o
SEN
SE

SE~SEN

C~CN

C

SCE
C

GN

LOGICAL

-7

GN

EXCLUSIVE OR
~----

SCE

C

3-181

G

1002

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
TD02 is a non-inverting time delay.

Logic Symbol

---1

Truth Table

TD02
Delay

Pin Loading

~

~

L

L

H

H

Equivalent
Load
A

1.0

Equivalent Gates: ................... 2.8
Bolt Syntax: ............................ Q .TD02 A;

Power Characteristics:
Parameter
Static IDD (TJ

Value

Units

4.4

nA

17.0

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
From

To

A

Q

Parameter
tpLH
tpHL

1

9

18

26

35 (max)

1.79
1.81

2.15
2.01

2.33
2.23

2.56
2.42

2.87
2.57

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-182

TD03

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
TD03 is a non-inverting time delay.

Logic Symbol

-1

Truth Table

TD03
Delay

Pin Loading

-rtt

~

L

L

H

H

Equivalent
Load
A

1.0

Equivalent Gates: ................... 3.0
Bolt Syntax: ............................ Q .TD03 A;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EOLpd

Units

4.4

nA

20.4

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
From
A

To

0

Parameter
tpLH
tpHL

1

9

18

26

35 (max)

2.79
2.77

3.12
3.00

3.35
3.23

3.59
3.45

3.82
3.68

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-183

TD08

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
T008 is a non-inverting time delay.

Logic Symbol

Truth Table

~

A T008 0 r-----

-

Pin Loading

Delay

L

L

H

H

Equivalent
Load

A

1.0

Equivalent Gates: ................... 3.3
Bolt Syntax: ............................ 0 .T008 A;

Power Characteristics:
Parameter
Static IDD (TJ

Value

Units

3.1

nA

10.0

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
From

To

A

Q

Parameter
tpLH
tpHL

1

7

14

20

27 (max)

8.52
7.58

8.81
8.21

9.14
8.50

9.40
8.72

9.56
8.90

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

3-184

SECTION ~
PAD LOGIC

I

I

I,~

IDCI3

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IDCI3 is an inverting, CMOS-level input buffer piece.

Logic Symbol

Truth Table

PA~

P

QC

D

Pin Loading

PADM

OC

Equivalent

L

H

Load

H

L

/

*PADM

217.2

IDCI31

Bolt Syntax: ............................ OC .IDCI3 PADM;

Power Characteristics:
Parameter

Value

nA

175.8

Eq-Ioad

Static IDD (TJ = 85°C)
*EOLpd

Units

4.7

'See page 2-14 for detailed information on the power equation for pad pieces.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
PADM

To
OC

tpLH
tpHL

1

13

26

38

51 (max)

0.84
0.88

0.99
1.02

1.18
1.18

1.36
1.35

1.52
1.54

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

IDCRO

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IDCRD is a non-buffered, resistive analog interface input piece.

Logic Symbol

Pin Loading

Truth Table

P

QC

D

PADM

PA~

/

L

L

H

H

IDCROI

Bolt Syntax: ............................ QC .IDCRO PADM;

Power Characteristics:
Parameter
Static IDD (TJ
*EQLpd

=

85°C)

Value

Units

0.1

nA

2.0

Eq-Ioad

'See page 2-14 for detailed information on the power equation for pad pieces.

4-2

Equivalent

QC

Load
*PADM

187.5

IDCS3

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IDCS3 is a non-inverting, CMOS-level Schmitt trigger input buffer piece with voltage hysteresis.

Logic Symbol

QC

Truth Table

PADM

PA~

P

77

D

Pin Loading

/

QC

L

L

H

H

Equivalent
Load
*PADM

217.2

IDCS31

Bolt Syntax: ............................ QC .IDCS3 PADM;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

*EQLpd

Value

Units

3.8

nA

182.2

Eq-Ioad

*See page 2-14 for detailed information on the power equation for pad pieces.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
PADM

To
QC

tpLH
tpHL

1

13

26

38

51 (max)

2.61
2.45

2.87
2.55

3.07
2.72

3.26
2.92

3.45
3.16

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-3

IDCX3

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IDCX3 is a non-inverting, CMOS-level input buffer piece.

Logic Symbol

lPuth Table

PADM

PA~

P
D

QC

Pin Loading

/

QC

L

L

H

H

Equivalent
Load
*PADM

217.2

IDCX31

Boit Syntax: ............................ QC .IDCX3 PADM;

Power Characteristics:
Parameter
Static

100

Value

nA

172.7

Eq-Ioad

(TJ = 85°C)

*EQLpd

Units

3.8

*See page 2-14 for detailed information on the power equation for pad pieces.

Delay Characteristics:
Conditions: TJ = 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

PADM

To

1

13

26

38

51 (max)

QC

0.89
0.87

1.10
1.06

1.30
1.24

1.48
1.42

1.65
1.60

tpLH
tpHL

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-4

IOPX3

.AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IDPX3 is a non-inverting, PCI-Ievel input buffer piece.

Logic Symbol

Truth Table

PA~

P

QC

Pin Loading

D

PADM

QC

Equivalent

L

L

Load

H

H

/

*PADM

217.2

IDPX31

Bolt Syntax: ............................ QC .IDPX3 PADM;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

*EQLpd

Units

3.3

nA

171.8

Eq-Ioad

'See page 2-14 for detailed information on the power equation for pad pieces.

Delay Characteristics:
Conditions: T J = 25°C, Voo = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter

From
PADM

To

1

13

26

38

51 (max)

QC

0.24
0.83

0.40
1.06

0.62
1.25

0.84
1.42

1.05
1.58

tpLH
tpHL

..
Delay will vary with mput conditions. See page 2-16 for interconnect estimates .

4-5

IDQCO

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IDOCO is a crystal oscillator input receiver piece.

Logic Symbol

Pin Loading

Truth Table

P
0

00

PADM

PA~

/

00

L

L

H

H

'Docal

Bolt Syntax: ............................ 00 .IDOCO PADM;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

*EOLpd

Value

Units

0.1

nA

2.0

Eq-Ioad

'See page 2-14 for detailed information on the power equation for pad pieces.

Design Notes:
The IDOCO cell is for backward compatibility with existing oscillator methodologies.

4-6

Equivalent
Load
*PADM

187.5

IDQC3

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IDOC3 is a crystal oscillator input receiver pad piece with a non-inverting, CMOS-level clock input. 00 is the output to
either the ODOFE20M or the ODOTE60M. PADM is the bond pad from the Xtal-in.

Logic Symbol

Possible Combination Logic Schematics

oc
00

Truth Table

Pin loading
PADM

OC

00

Equivalent

L

L

L

Load

H

H

H

*PADM

217.2

Bolt Syntax: ............................ OC 00 .IDOC3 PADM;

Power Characteristics:
Parameter
Static IDD (TJ

Value

Units

3.8

nA

174.0

Eq-Ioad

= 85°C)

*EOL pd

*See page 2-14 for detailed information on the power equation for pad pieces.

Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter

I

From

To

PADM

OC

PADM

00

1

13

26

38

51 (max)

tpLH
tpHL

0.85
0.79

1.06
1.02

1.27
1.20

1.44
1.37

1.59
1.54

tpLH
tpHL

0.00
0.00

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Design Notes:
The IDQC3 is the input cell of a two cell oscillator circuit. Its function is to connect the QO pin with the QI pin of either the OOQFE20M or the OOQTE60M oscillator output
driver pad pieces. The buffered QC pin is for driving the oscillator into the core. Two package pins are required to create a complete oscillator.

4-7

IDQS3

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IDaS3 is a crystal oscillator input receiver pad piece. ac is a non-inverting, CMOS-level schmitt trigger clock input
buffer. 00 is the output to the ODOFE99K. PADM is the bond pad from the Xtal-in.

Logic Symbol

Logic Schematic
QC

oc
00

Xtal·in

Xtal-out

Truth Table

Pin Loading
PADM

OC

00

L
H

L
H

H

Equivalent
Load

L

*PADM

217.2

Bolt Syntax: ............................ ac ao .IDOS3 PADM;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

*EOLpd

Units

3.8

nA

183.7

Eq-Ioad

·See page 2-14 for detailed information on the power equation for pad pieces.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

1

13

26

38

51 (max)

PADM

ac

tpLH
tpHL

2.59
2.31

2.89
2.61

3.07
2.75

3.26
2.93

3.47
3.15

PADM

ao

tpLH
tpHL

0.00
0.00

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Design Notes:
The IDQS3 is the input cell of a two cell oscillator circuit. Its function is to connect the QO pin with the QI pin of the ODQFE99K oscillator output driver.
I
pad piece. The buffered QC pin is for driving the oscillator into the core. Two package pins are required to create a complete oscillator.

4-8

~II~

IDTS3

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IDTS3 is a non-inverting, TTL-level Schmitt input buffer piece.

Logic Symbol

Pin Loading

Truth Table

Equivalent

PADM QC

QC

PA~

P

77

D

/

L

L

H

H

Load
*PADM

217.2

IDTS31

Bolt Syntax: ............................ QC .IDTS3 PADM;

Power Characteristics:
Value

Parameter
Static IDD (TJ = 85°C)
*EQLpd

Units

3.4

nA

181.8

Eq-Ioad

'See page 2-14 for detailed information on the power equation for pad pieces.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

PADM

QC

tpLH
tpHL

1

13

26

38

51 (max)

1.24
1.49

1.42
1.87

1.60
2.08

1.78
2.24

1.95
2.38

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-9

IOTl3

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IDTX3 is a non-inverting, TTL-level, input buffer piece.

Logic Symbol

Truth Table

Pin Loading
Equivalent

PADM QC

PA~

P
D

oc

L

L

H

H

Load
*PADM

217.2

/

IDTX31

Bolt Syntax: ............................ QC .IDTX3 PADM;

Power Characteristics:
Parameter
Static 100 (TJ

Value

Units

3.3

nA

172.7

Eq-Ioad

= 85°C)

*EQLpd

'See page 2-14 for detailed information on the power equation for pad pieces.

Input Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From
PADM

To
QC

tpLH
tpHL

1

13

26

38

51 (max)

0.21
0.90

0.31
1.17

0.45
1.35

0.62
1.53

0.85
1.72

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-10

PLD3

Ii
I

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
PLD3 is an active pull-down buffer piece.

Logic Symbol

Truth Table

I

I

PLD3

1)

Pin Loading

N/A

Bolt Syntax: ............................ PADM .PLD3 ;

Power Characteristics:
Parameter
Static IDD (TJ

=

85°C)

EQLpd

Value

Units

1.4

nA

207.6

Eq-Ioad

See page 2-14 for power equation.

4-11

N/A

PLP3

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
PLP3 is a programmable pull-up/pull-down buffer piece.

Logic Symbol

Truth Table

I

PLP3

mal
mOl

MA

I,\M
[I;~ 1

Pin Loading

MB

PADM Function

L

L

Pull-down

H

H

Pull-up

H

L

Tri-state

L

H

Tri-state

Bolt Syntax: ............................ PADM .PLP3 MA MB;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

1.4

nA

205.0

Eq-Ioad

See page 2-14 for power equation.

4-12

N/A

PLU3

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
PLU3 is an active pull-up buffer piece.

Logic Symbol

I

Pin Loading

Truth Table

I

PLU3

~M

N/A

Bolt Syntax: ............................ PADM .PLU3 ;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EQLpd

Units

1.4

nA

207.6

Eq-Ioad

See page 2-14 for power equation.

4-13

N/A

ODCSIP04

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCSIP04 is a 4 rnA, inverting, CMOS-level output buffer piece with a P-channel open-drain (pull-up) and controlled
slew rate output.

Truth Table

Logic Symbol

Pin Loading
Equivalent

H

I·

A

Q

Z

PADM

Load

PADM

L

H

A

H

Z

PADM

3.0
217.7

= High Impedance

Bolt Syntax: ............................ PADM .ODCSIP04 A;

Power Characteristics:
Parameter

Value

Static IDD (TJ

33.9

nA

302.6

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZH
tHZ

15

50

100

200

300 (max)

3.52
0.77

8.58

15.93

30.62

45.18

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-14

ODCSIP08

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCSIP08 is an 8 mA, inverting, CMOS-level, output buffer piece with a P-channel open-drain (pull-up) and controlled
slew rate output.

Logic Symbol

Truth Table

Pin Loading
Equivalent

I,

~

Q

PADM

L

H

A

3.0

Z

PADM

218.6

H
Z

PADM

Load

A

= High

Impedance

Bolt Syntax: ............................ PADM .ODCSIP08 A;

Power Characteristics:
Parameter

Value

Static IDD (TJ = 85°C)

33.9

nA

313.0

Eq-Ioad

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZH
tHZ

15

50

100

200

300 (max)

2.24
1.00

4.84

8.52

15.96

23.48

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-15

ODCSIP12

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCSIP12 is a 12 mA, inverting, CMOS-level, output buffer piece with a P-channel open-drain (pull-up) and controlled
slew rate output.

Logic Symbol

Pin Loading

Truth Table

Equivalent

Z

A

PADM

Load

L

H

A

3.0

H

Z

PADM

219.0

= High Impedance

Bolt Syntax: ............................ PADM .ODCSIP12 A;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

33.9

nA

318.1

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J ;:: 25°C, V DD

= 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZH
tHZ

15

50

100

200

300 (max)

1.77
1.00

3.51

5.97

10.89

15.82

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-16

DOCSIED"

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCSXE04 is a 4 mA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable and controlled slew
rate output.

Logic Symbol

Truth Table

Pin Loading
Equivalent
EN

~

f

PADM

A

Load

PADM

L

L

L

A

10.3

L

H

H

EN

7.3

H

X

Z

PADM

217.7

Bolt Syntax: ............................ PADM .ODCSXE04 A EN;

Power Characteristics:
Parameter
Static IDD (TJ

Value

Units

37.6

nA

322.4

Eq-Ioad

= 85°C)

EQLpd

See page 2-14 for power equation. Delay Characteristics:

Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

A
PADM

tpLH
tpHL

3.33
3.36

8.49
8.47

15.80
15.74

30.41
30.25

45.10
44.74

EN
PADM

tHZ
tLZ
tZH
tZL

0.88
0.34
3.57
3.34

8.70
8.41

15.99
15.71

30.64
30.25

45.28
44.69

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-17

DOCSIED8

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCSXE08 is an 8 rnA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable and controlled
slew rate output.

Logic Symbol

Truth Table

Pin Loading
Equivalent

I~

~

PADM

EN

A

PADM

L

L

L

L

H

H

EN

7.3

H

X

Z

PADM

218.7

Load
A

10.3

Bolt Syntax: ............................ PADM .ODCSXE08 A EN;

Power Characteristics:
Parameter

Value

Static IDD (TJ = 85°C)

37.6

nA

EQLpd

338.2

Eq-Ioad

Units

See page 2-14 for power equation. Delay Characteristics:

Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

4.65
4.64

8.41
8.39

15.89
15.85

23.34
23.25

4.94
4.62

8.65
8.37

16.06
15.83

23.60
23.26

A
PADM

tpLH
tpHL

2.02
1.99

EN
PADM

tHZ
tLZ
tZH
tZL

1.14
0.46
2.25
2.00

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-18

ODCSXE12

AMERICAN MICRDSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCSXE12 is a 12 rnA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable and controlled
slew rate output.

Truth Table

Logic Symbol

Pin Loading
Equivalent
EN

~

I:'

PADM

A

Load

PADM

L

L

L

A

10.3

L

H

H

EN

7.3

H

X

Z

PADM

219.1

Bolt Syntax: ............................ PADM .ODCSXE12 A EN;

Power Characteristics:
Parameter
Static IDD (TJ

Units

Value
37.6

nA

348.8

Eq-Ioad

= 85°C)

EQLpd

See page 2-14 for power equation. Delay Characteristics:

Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

A
PADM

tpLH
tpHL

1.63
1.63

3.41
3.43

5.91
6.02

10.86
11.14

15.76
16.17

EN
PADM

tHZ
tLZ
tZH
tZL

1.41
0.59
1.87
1.61

3.68
3.45

6.13
6.01

11.03
11.10

16.02
16.20

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-19

ODCSXE16

AMERICAN MICROSYSTEM8, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCSXE16 is a 16 rnA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable and controlled
slew rate output.

Logic Symbol

Truth Table

Pin Loading
Equivalent

~

I:'

PADM

Load

EN

A

PADM

L

L

L

L

H

H

EN

6.6

H

X

Z

PADM

219.1

A

3.0

Bolt Syntax: ............................ PADM .ODCSXE16 A EN;

Power Characteristics:
Parameter

Value

Static 100 (TJ

41.0

nA

374.2

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation. Delay Characteristics:

Conditions: TJ

= 25°C, Voo = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM
EN
PADM

To

15

50

100

200

300 (max)

tpLH
tpHL

1.79
1.72

2.47
2.94

3.42
4.70

5.34
8.24

7.28
11.78

tHZ
tLZ
tZH
tZL

1.06
1.46
1.40
1.50

2.11
2.74

3.09
4.53

5.01
8.07

6.91
11.59

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-20

ODCSXE216

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCSXE24 is a 24 mA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable and controlled
slew rate output.

Logic Symbol

Truth Table

Pin Loading
Equivalent

~

I~

PADM

EN

A

PADM

L

L

L

Load
A

3.0

L

H

H

EN

4.8

H

X

Z

PADM

219.0

Bolt Syntax: ............................ PADM .ODCSXE24 A EN;

Power Characteristics:
Parameter
Static IDD (TJ

Value

Units

39.2

nA

368.7

Eq-Ioad

= 85°C)

EQLpd

See page 2-14 for power equation. Delay Characteristics:

Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

A
PADM

tpLH
tpHL

1.71
1.49

2.22
2.34

2.94
3.52

4.45
5.89

6.02
8.26

EN
PADM

tHZ
tLZ
tZH
tZL

1.20
1.84
1.28
1.36

1.87
2.21

2.68
3.42

4.22
5.80

5.71
8.16

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-21

ooeSXX04

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCSXX04 is a 4 rnA, non-inverting, CMOS-level, output buffer piece with controlled slew rate output.

Logic Symbol

Pin Loading

Truth Table

A

~

I-

PADM

L

L

H

H

Equivalent
Load
A

9.9

PADM

Bolt Syntax: ............................ PADM . ODCSXX04 A;

Power Characteristics:
Units

Parameter

Value

Static IDD (TJ

34.7

nA

307.5

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, VD D = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

3.24
3.21

8.39
8.28

15.69
15.62

30.32
30.20

45.00
44.58

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-22

ODCSXXOB

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCSXX08 is an 8 mA, non-inverting, CMOS-level, output buffer piece with controlled slew rate output.

Logic Symbol

Truth Table

Pin Loading

A

~

,.

PADM

L

L

H

H

Equivalent
Load
A

9.9

PADM

Bolt Syntax: ............................ PADM . ODCSXX08 A;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EQLpd

Units

34.7

nA

323.4

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

1.83
1.91

4.55
4.53

8.31
8.28

15.76
15.73

23.23
23.14

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-23

ODCSXX12

~I'~

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCSXX12 is a 12 mA, non-inverting, CMOS-level, output buffer piece with controlled slew rate output.

Logic Symbol

Pin Loading

Truth Table

~

I·

A

PADM

Equivalent

L

L

Load

H

H

A

9.9

PADM

Bolt Syntax: ............................ PADM . ODCSXX12 A;

Power Characteristics:
Parameter

Value

Static IDD (TJ = 85°C)

34.7

nA

EQLpd

334.0

Eq-Ioad

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

1.51
1.53

3.23
3.33

5.74
5.88

10.72
10.97

15.59
16.08

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-24

ODCSXX16

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCSXX16 is a 16 rnA, non-inverting, CMOS-level, output buffer piece with controlled slew rate output.

Logic Symbol

Pin Loading

Truth Table

A

~

I,

Equivalent

PADM

L

L

H

H

Load
A

9.9

PADM

Bolt Syntax: ............................ PADM . ODCSXX16 A;

Power Characteristics:
Parameter
Static 100 (TJ

= 85°C)

EQLpd

Value

Units

34.7

nA

337.5

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

1.38
1.27

2.71
2.57

4.59
4.44

8.34
8.15

12.10
11.80

Oelay will vary with input conditions. See page 2-16 for interconnect estimates.

4-25

oDCSXX24

AMERICAN MICROSYSTEMS.ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCSXX24 is a 24 mA, non-inverting, CMOS-level, output buffer piece with controlled slew rate output.

Logic Symbol

Truth Table

Pin Loading

~

I·

PADM

A
L

L

H

H

Equivalent
Load
A

9.3

PADM

Bolt Syntax: ............................ PADM . ODCSXX24 A;

Power Characteristics:
Parameter
Static 'DO (TJ

= 85°C)

EQLpd

Value

Units

35.9

nA

337.8

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

1.35
1.17

2.42
2.03

3.92
3.27

6.91
5.75

9.88
8.24

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-26

ODCXIPOl

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXIP01 is a 1 mA, inverting, CMOS-level, output buffer piece with P-channel, open-drain (pull-up).

Logic Symbol

Truth Table

Pin Loading
Equivalent

~\i2

I·

Z

PADM

A

PADM

Load

L

H

A

3.0

H

Z

PADM

217.4

= High Impedance

Bolt Syntax: ............................ PADM .ODCXIP01 A;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

31.7

nA

275.7

Eq-Ioad

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: TJ = 25°C, V DD

= 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZH
tHZ

15

25

35

50

75 (max)

6.35
0.56

9.25

12.16

16.58

24.02

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-27

.~II~

ODCXIP02

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXIP02 is a 2 rnA, inverting, CMOS-level, output buffer piece with P-channel, open-drain (pull-up).

logic Symbol

Pin loading

Truth Table

Equivalent

~Q

j.

Z

PADM

A

PADM

L

H

A

Load
3.0

H

Z

PADM

217.4

= High Impedance

Bolt Syntax: ............................ PADM .ODCXIP02 A;

Power Characteristics:
Parameter

Value

Static IDD (TJ

31.7

nA

277.6

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZH
tHZ

15

50

75

100

150 (max)

3.49
0.72

8.62

12.27

15.92

23.22

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-28

ODCXIPO"

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXIP04 is a 4 mA, inverting, CMOS-level, output buffer piece with P-channel, open-drain (pull-up).

Logic Symbol

Pin Loading

Truth Table

Equivalent

[>-{(~

I-

Z

PADM

A

PADM

L

H

A

3.0

H

Z

PADM

217.9

= High

Load

Impedance

Bolt Syntax: ............................ PADM .ODCXIP04 A;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

32.2

nA

285.2

Eq-Ioad

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZH
tHZ

15

50

100

200

300 (max)

2.10
0.79

4.75

8.45

15.89

23.42

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-29

ODCXIP08

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXIP08 is an 8 rnA, inverting, CMOS-level, output buffer piece with P-channel, open-drain (pull-up).

Logic Symbol

Truth Table

Pin Loading
Equivalent

~~

I,

Z

PADM

A

PADM

L

H

A

3.0

H

Z

PADM

218.6

= High

Load

Impedance

Bolt Syntax: ............................ PADM .ODCXIP08 A;

Power Characteristics:
Parameter

Value

Static IDD (TJ

32.2

nA

295.2

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: TJ

= 25°C, VDD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

A
PADM

To
tZH
tHZ

15

50

100

200

300 (max)

1.55
1.26

2.93

4.82

8.55

12.30

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-30

ODCXXEOl

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXXE01 is a 1 mA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable.

Logic Symbol

Truth Table

Pin Loading
Equivalent
EN

~

f

PADM

PADM

A

Load

L

L

L

A

4.7

L

H

H

EN

4.5

H

X

Z

PADM

217.4

Bolt Syntax: ............................ PADM .ODCXXE01 A EN;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

32.8

nA

285.3

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C,

V DD

= 5.0V,

Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

25

35

50

75 (max)

A
PADM

tpLH
tpHL

6.26
6.17

9.21
8.86

12.17
11.57

16.61
15.68

23.92
22.72

EN
PADM

tHZ
tLZ
tZH
tZL

0.82
0.39
6.35
6.03

9.30
8.86

12.28
11.68

16.74
15.85

24.01
22.61

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-31

ODCXXE02

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXXE02 is a 2 rnA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable.

Logic Symbol

Truth Table

Pin Loading
Equivalent
EN

~

I:'

PADM

PADM

A

Load
4.7

L

L

L

A

L

H

H

EN

4.5

H

X

Z

PADM

217.4

Bolt Syntax: ............................ PADM .ODCXXE02 A EN;

Power Characteristics:
Parameter

Value

Static IDD (TJ

32.8

nA

288.7

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

75

100

150 (max)

8.53
8.55

12.20
12.18

15.88
15.81

23.24
23.07

8.78
8.63

12.41
12.25

16.03
15.87

23.29
23.11

A
PADM

tpLH
tpHL

3.43
3.47

EN
PADM

tHZ
tLZ
tZH
tZL

1.01
0.49
3.61
3.52

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-32

ODCXXE04

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXXE04 is a 4 mA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable.

Logic Symbol

Truth Table

Pin Loading
Equivalent
EN

~

r

A

Load
7.0

L

L

L

A

L

H

H

EN

5.7

X

Z

PADM

217.9

H

PADM

PADM

Bolt Syntax: ............................ PADM .ODCXXE04 A EN;
Power Characteristics:
Parameter

Value

Static 100 (TJ

34.3

nA

300.1

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

4.67
4.61

8.40
8.34

15.82
15.76

23.33
23.21

4.73
4.64

8.52
8.37

16.02
15.79

23.40
23.24

A
PADM

tplH
tpHl

1.98
1.97

EN
PADM

tHZ
tlZ
tZH
tZl

1.01
0.46
2.09
1.99

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-33

ODCXXE08

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXXE08 is an 8 rnA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable.

Logic Symbol

Pin Loading

Truth Table

Equivalent

~

f

PADM

EN

A

PADM

L

L

L

Load

L

H

H

EN

4.8

H

X

Z

PADM

218.6

A

2.8

Bolt Syntax: ............................ PADM .ODCXXE08 A EN;

Power Characteristics:
Parameter

Value

Units

Static IDD (TJ

37.1

nA

330.3

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

A
PADM

tplH
tpHl

1.91
1.60

3.25
2.93

5.15
4.80

8.91
8.53

12.63
12.26

EN
PADM

tHZ
tlZ
tZH
tZl

1.09
1.03
1.69
1.52

3.08
2.83

5.00
4.70

8.75
8.44

12.43
12.18

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-34

ODCXXE12

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXXE12 is a 12 rnA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable.

Logic Symbol

Pin Loading

Truth Table

Equivalent

I~

~

PADM

Load

EN

A

PADM

L

L

L

L

H

H

EN

4.8

H

X

Z

PADM

218.9

A

2.8

Bolt Syntax: ............................ PADM .ODCXXE12 A EN;

Power Characteristics:
Parameter

Value

Units

Static IDD (TJ

37.1

nA

339.5

Eq-Ioad

=

85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C,

V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

A
PADM

tplH
tpHl

1.95
1.43

2.96
2.31

4.41
3.54

7.39
6.01

10.43
8.53

EN
PADM

tHZ
tlZ
tZH
tZl

1.25
1.20
1.63
1.32

2.73
2.15

4.25
3.42

7.24
5.95

10.21
8.40

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-35

ODCXXE16

AMERICAN MICROSYSTEMS, INC.

AM.6S 0.6 micron CMOS Standard Cells
Description:
ODCXXE16 is a 16 rnA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable,

Logic Symbol

Pin Loading

Truth Table

Equivalent

~

f

PADM

Load

EN

A

PADM

L

L

L

L

H

H

EN

4.8

H

X

Z

PADM

219.0

A

2.8

Bolt Syntax: ............................ PADM .ODCXXE16 A EN;

Power Characteristics:
Parameter

Value

Static IDD (TJ

37.1

nA

344.9

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

2.91
2.00

4.43
2.98

7.43
4.86

10.38
6.67

2.72
1.93

4.23
2.89

7.23
4.76

10.21
6.62

A
PADM

tplH
tpHl

1.84
1.27

EN
PADM

tHZ
tlZ
tZH
tZl

1.25
1.39
1.64
1.24

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-36

ODCXXE24

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXXE24 is a 24 mA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable.

Logic Symbol

Truth Table

Pin Loading
Equivalent
EN

~

I~

PADM

A

PADM

Load

L

L

L

A

2.8

L

H

H

EN

4.8

H

X

Z

PADM

219.0

Bolt Syntax: ............................ PADM .ODCXXE24 A EN;

Power Characteristics:
Parameter
Static IDD (TJ

=

85°C)

EQLpd

Value

Units

37.1

nA

354.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, Voo = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

A
PADM

t pLH
tpHL

1.92
1.31

2.99
1.80

4.49
2.48

7.44
3.76

10.34
4.98

EN
PADM

tHZ
tLZ
tZH
tZL

1.25
1.75
1.71
1.21

2.75
1.72

4.23
2.40

7.20
3.68

10.19
4.89

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-37

ODCXXXOl

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXXX01 is a 1 rnA, non-inverting, CMOS-level output buffer piece.

Logic Symbol

Truth Table

Pin Loading

A

~

I·

PADM

L

L

H

H

Equivalent
Load
A

3.3

PADM

Bolt Syntax: ............................ PADM .ODCXXX01 A;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EQLpd

Units

31.3

nA

274.6

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

25

35

50

75 (max)

6.26
6.05

9.21
8.79

12.15
11.55

16.57
15.70

23.94
22.63

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-38

ODCxn02

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXXX02 is a 2 mA, non-inverting, CMOS-level output buffer piece.

Logic Symbol

Truth Table

Pin Loading

~

I·

A

PADM

L

L

H

H

Equivalent
Load
A

3.3

PADM

Bolt Syntax: ............................ PADM . ODCXXX02 A;

Power Characteristics:
Parameter
Static 100 (TJ

=

85°C)

EQLpd

Value

Units

31.3

nA

277.9

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

75

100

150 (max)

3.47
3.54

8.70
8.61

12.36
12.27

15.99
15.91

23.17
23.07

Oelay will vary with input conditions. See page 2-16 for interconnect estimates.

4-39

oDCXXX04

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXXX04 is a 4 mA, non-inverting, CMOS-level output buffer piece.

Logic Symbol

Truth Table

Pin Loading

A

~

I·

PADM

L

L

H

H

Equivalent
Load
A

4.2

PADM

Bolt Syntax: ............................ PADM . ODCXXX04 A;

Power Characteristics:
Parameter

Value

Static IDD (TJ

31.7

nA

287.1

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

2.06
2.01

4.69
4.64

8.42
8.39

15.89
15.85

23.37
23.25

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-40

ODCXXX08

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXXX08 is an 8 rnA, non-inverting, CMOS-level output buffer piece.

Logic Symbol

Truth Table

Pin Loading

~

I·

A

PADM

Equivalent

L

L

Load

H

H

A

6.3

PADM

Bolt Syntax: ............................ PADM . ODCXXX08 A;

Power Characteristics:
Parameter

Value

Static IDD (TJ

32.6

nA

302.3

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

1.36
1.29

2.70
2.61

4.60
4.50

8.43
8.35

12.28
12.22

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-41

ODCXXX12

~I'~

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXXX12 is a 12 mA, non-inverting, CMOS-level output buffer piece.

Truth Table

Logic Symbol

Pin Loading

~

I,

A

PADM

Equivalent

L

L

Load

H

H

A

7.6

PADM

Bolt Syntax: ............................ PADM. ODCXXX12 A;

Power Characteristics:
Parameter

Value

Static 100 (TJ

33.0

nA

313.3

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

1.25
1.03

2.31
1.92

3.81
3.20

6.80
5.70

9.79
8.15

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-42

ODCXXX16

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXXX16 is a 16 mA, non-inverting, CMOS-level output buffer piece.

Logic Symbol

Truth Table

Pin Loading

A

~

I,

PADM

L

L

H

H

Equivalent
Load
A

8.2

PADM

Bolt Syntax: ............................ PADM . ODCXXX16 A;

Power Characteristics:
Parameter
Static IDD (TJ

=

85°C)

EQLpd

Value

Units

33.4

nA

320.2

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

1.29
0.93

2.34
1.63

3.84
2.60

6.83
4.48

9.80
6.32

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-43

~I'~

ODCXXX24

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODCXXX24 is a 24 rnA, non-inverting, CMOS-level output buffer piece.

Logic Symbol

Truth Table

Pin Loading

A

~

I-

PADM

L

L

H

H

Equivalent
Load
A

8.2

PADM

Bolt Syntax: ............................ PADM . ODCXXX24 A;

Power Characteristics:
Parameter

Value

Units

Static IDD (TJ = 85°C)

33.4

nA

330.3

Eq-Ioad

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

1.46
0.94

2.49
1.42

3.95
2.08

6.89
3.35

9.88
4.59

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-44

ODPSXE24

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODPSXE24 is a PCI, non-inverting, tri-state buffer piece with controlled slew rate output.

Logic Symbol

Truth Table

Pin Loading
Equivalent

t>~

IA

I

EN

PCI

PADM

PADM

A

Load

L

L

L

A

L

H

H

EN

3.8

H

X

Z

PADM

219.1

5.0

Bolt Syntax: ............................ PADM .ODPSXE24 A EN;

Power Characteristics:
Parameter

Value

Static IDD (TJ

43.1

nA

389.6

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

4.48
3.30

6.11
4.22

9.13
5.72

11.98
7.06

4.60
3.30

6.21
4.24

9.21
5.73

12.15
7.11

A
PADM

tpLH
tpHL

3.16
2.35

EN
PADM

tHZ
tLZ
tZH
tZL

1.23
1.00
3.15
2.27

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-45

ODTSXN04

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXN04 is a 4mA, non-inverting, TTL-level, output buffer piece with N-channel open-drain (pull-down) and controlled
slew rate output.

Logic Symbol

Truth Table

Pin Loading
Equivalent
A

~q]

I-

Z

PADM

PADM

Load

L

L

A

5.9

H

Z

PADM

217.3

= High Impedance

Bolt Syntax: ............................ PADM .ODTSXN04 A;

Power Characteristics:
Parameter
Static IDD (TJ

Units

Value
33.4

nA

281.5

Eq-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZL
tLZ

15

50

100

200

300 (max)

4.83
0.28

12.79

23.97

46.20

68.45

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-46

OOISIN08

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXN08 is an 8 mA, non-inverting, TTL-level, output buffer piece with N-channel open-drain (pull-down) and
controlled slew rate output.

Logic Symbol

Truth Table

Pin Loading
Equivalent

~

I·

A

~

Z

PADM

Load

PADM

L

L

A

5.9

H

Z

PADM

217.3

= High Impedance

Bolt Syntax: ............................ PADM .ODTSXN08 A;

Power Characteristics:
Value

Units

33.4

nA

287.0

Eq-Ioad

Parameter
Static 100 (TJ

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZl
tlZ

15

50

100

200

300 (max)

2.65
0.41

6.79

12.67

24.31

35.80

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-47

ODTSXN12

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXN12 is a 12 rnA, non-inverting, TTL-level, output buffer piece with N-channel open-drain (pull-down) and
controlled slew rate output.

Logic Symbol

Pin Loading

Truth Table

Equivalent

H

I·

A

~

Z

PADM

PADM

Load

L

L

A

5.9

H

Z

PADM

217.3

= High Impedance

Bolt Syntax: ............................ PADM .ODTSXN12 A;

Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EQLpd

Units

33.4

nA

292.4

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, Voo = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZL
tLZ

15

50

100

200

300 (max)

1.91
0.54

4.84

8.96

17.03

24.97

Oelay will vary with input conditions. See page 2-16 for interconnect estimates.

4-48

ODTSXN16

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXN16 is a 16 mA, non-inverting, TTL-level, output buffer piece with N-channel open-drain (pull-down) and
controlled slew rate output.

Logic Symbol

Truth Table

Pin Loading
Equivalent

,.

~

~

A

PADM

L

L

A

Load
9.3

H

Z

PADM

217.3

Z = High Impedance

PADM

Bolt Syntax: ............................ PADM .ODTSXN16 A;

Power Characteristics:
Parameter

Value

Static IDD (TJ

35.9

nA

300.3

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZl
tlZ

15

50

100

200

300 (max)

1.55
0.46

3.56

6.43

12.19

17.96

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-49

ODTSXN24

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXN24 is a 24 mA, non-inverting, TTL-level, output buffer piece with N-channel open-drain (pull-down) and
controlled slew rate output.

logic Symbol

Pin loading

Truth Table

Equivalent

~

I·

~

A

PADM

L

L

A

Load
9.3

H

Z

PADM

217.3

Z = High Impedance

PADM

Bolt Syntax: ............................ PADM .ODTSXN24 A;

Power Characteristics:
Value

Parameter
Static

IDD

(TJ

nA

310.4

Eq-Ioad

= 85°C)

EQLpd

Units

35.9

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZL
tLZ

15

50

100

200

300 (max)

1.17
0.64

2.58

4.54

8.42

12.32

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-50

DOISIED"

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXE04 is a 4 mA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable and controlled slew
rate output.

Logic Symbol

Pin Loading

Truth Table

Equivalent

~

I~

PADM

EN

A

PADM

L

L

L

Load

L

H

H

EN

7.3

H

X

Z

PADM

217.7

A

10.3

Bolt Syntax: ............................ PADM .ODTSXE04 A EN;

Power Characteristics:
Units

Parameter

Value

Static 100 (TJ

37.6

nA

322.4

Eql-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

A
PADM

tplH
tpHl

1.96
5.15

4.71
13.21

8.65
24.69

16.56
47.67

24.49
70.68

EN
PADM

tHZ
tlZ
tZH
tZl

0.88
0.34
2.14
5.08

4.91
13.23

8.88
24.72

16.78
47.63

24.67
70.69

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-51

JtMI'~

ODTSXE08

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXE08 is an 8 rnA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable and controlled
slew rate output.

Logic Symbol

Pin Loading

Truth Table

Equivalent

~

I~

PADM

Load

EN

A

PADM

L

L

L

L

H

H

EN

7.3

H

X

Z

PADM

218.7

A

10.3

Bolt Syntax: ............................ PADM .ODTSXE08 A EN;

Power Characteristics:
Parameter

Value

Static 100 (TJ

37.6

nA

338.2

Eql-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, Voo = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

2.70
7.11

4.75
13.04

8.79
24.95

12.77
36.91

2.95
7.08

4.96
13.06

8.98
24.98

13.02
36.82

A
PADM

tpLH
tpHL

1.27
2.99

EN
PADM

tHZ
tLZ
tZH
tZL

1.14
0.46
1.51
2.89

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-52

--~---~--.-.-.----

..

~-----

ODTSXE12

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXE12 is a 12 mA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable and controlled
slew rate output.

Logic Symbol

Truth Table

Pin Loading
Equivalent
EN

~

I:'

PADM

A

Load

PADM

L

L

L

A

10.3

L

H

H

EN

7.3

H

X

Z

PADM

219.1

Bolt Syntax: ............................ PADM .ODTSXE12 A EN;

Power Characteristics:
Parameter
Static IDD (TJ

Value

Units

37.6

nA

348.8

Eql-Ioad

= 85°C)

EQLpd
See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

A
PADM

tpLH
tpHL

1.14
2.28

2.11
5.18

3.46
9.31

6.13
17.52

8.77
25.70

EN
PADM

tHZ
tLZ
tZH
tZL

1.41
0.59
1.43
2.25

2.36
5.14

3.66
9.28

6.32
17.51

9.02
25.69

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-53

ODTSXE16

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXE16 is a 16 mA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable and controlled
slew rate output.

Logic Symbol

Truth Table

Pin Loading
Equivalent

~

I~

PADM

EN

A

PADM

L

L

L

L

H

H

EN

6.6

H

X

Z

PADM

219.1

Load
A

3.0

Bolt Syntax: ............................ PADM .ODTSXE16 A EN;

Power Characteristics:
Parameter

Value

Static IDD (TJ

41.0

nA

374.2

Eql-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM
EN
PADM

To

15

50

100

200

300 (max)

tplH
tpHl

1.80
2.21

2.53
4.28

3.56
7.17

5.59
12.75

7.59
18.12

tHZ
tlZ
tZH
tZl

1.09
1.48
1.54
1.96

2.23
4.05

3.20
6.99

5.22
12.58

7.28
17.90

\

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-54

ODTSXE24

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXE24 is a 24 mA, non-inverting, CMOS-level, tri-state output buffer piece with active low enable and controlled
slew rate output.

logic Symbol

Truth Table

Pin loading
Equivalent

~

I~

PADM

EN

A

PADM

L

L

L

Load

L

H

,H

EN

4.8

H

X

Z

PADM

219.0

A

3.0

Bolt Syntax: ............................ PADM .ODTSXE24 A EN;

Power Characteristics:
Parameter

Value

Static IDD (TJ

39.2

nA

368.7

Eql-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

2.25
3.25

3.04
5.22

4.63
9.03

6.23
12.73

1.92
3.15

2.76
5.12

4.37
8.93

5.95
12.64

A
PADM

tpLH
tpHL

1.67
1.83

EN
PADM

tHZ
tLZ
tZH
tZL

1.23
1.86
1.32
1.71

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-55

ODTSXXO"

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXX04 is a 4 mA, non-inverting, TTL-level, output buffer piece with controlled slew rate output.

Logic Symbol

Truth Table

Pin Loading

A

~

I,

PADM

L

L

H

H

Equivalent
Load
A

9.9

PADM

Bolt Syntax: ............................ PADM .ODTSXX04 A;

Power Characteristics:
Parameter
Static 'DD (TJ

= 85°C)

EQLpd

Value

Units

34.7

nA

307.5

Eq-Ioad

See page.2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

1.82
4.95

4.58
12.93

8.58
24.11

16.50
46.35

24.34
68.64

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-56

ODTsn08

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXX08 is an 8 mA, non-inverting, TTL-level, output buffer piece with controlled slew rate output.

Logic Symbol

Truth Table

Pin Loading

~

I,

A

PADM

L

L

H

H

Equivalent
Load
A

9.9

PADM

Bolt Syntax: ............................ PADM .ODTSXX08 A;

Power Characteristics:
Parameter

Value

Static IDD (TJ

34.7

nA

323.4

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

1.22
2.82

2.59
6.94

4.72
12.83

9.40
24.78

14.44
37.03

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-57

ODTSXX12

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXX12 is a 12 rnA, non-inverting, TTL-level, output buffer piece with controlled slew rate output.

Logic Symbol

Truth Table

Pin Loading

~

I·

PADM

A
L

L

H

H

Equivalent
Load
A

9.9

PADM

Bolt Syntax: ............................ PADM .ODTSXX12 A;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

34.7

nA

334.0

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

=

25°C, V DD

=

5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

1.01
2.15

1.95
5.03

3.31
9.10

5.99
17.16

8.61
25.17

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-58

ODTSXX16

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXX16 is a 16 rnA, non-inverting, TTL-level, output buffer piece with controlled slew rate output.

Logic Symbol

Pin Loading

Truth Table

~

I-

A

PADM

Equivalent

L

L

Load

H

H

A

9.9

PADM

Bolt Syntax: ............................ PADM .ODTSXX16 A;

Power Characteristics:
Parameter

Value

Static IDD (TJ

34.7

nA

337.5

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

1.02
1.76

1.74
3.77

2.74
6.70

4.75
12.54

6.78
18.27

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-59

ODTSXX24

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTSXX24 is a 24 rnA, non-inverting, TTL-level, output buffer piece with controlled slew rate output.

Logic Symbol

Pin Loading

Truth Table

A

OOQ.
~

A

\

Equivalent

PADM

L

L

H

H

Load
A

9,3

PADM

Bolt Syntax: ... ......................... PADM .ODTSXX24 A;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

35.9

nA

337.8

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

0.99
1.42

1.61
2.81

2.46
4.82

4.07
8.73

5.62
12.54

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-60

ODTXXNOl

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXN01 is a 1 mA, non-inverting, TTL-level, output buffer piece with N-channel, open-drain (pull-down).

Logic Symbol

Truth Table

Pin Loading
Equivalent

~q]

I·

A

PADM

L

L

A

3.0

H

Z

PADM

217.2

Load

Z = High Impedance

PADM

Bolt Syntax: ............................ PADM .ODTXXN01 A;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

31.3

nA

269.4

Eq-Ioad

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZl
tlZ

15

25

35

50

75 (max)

8.91
0.27

13.36

17.81

24.39

35.00

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-61

ODTXXN02

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXN02 is a 2 rnA, non-inverting, TTL-level, output buffer piece with N-channel, open-drain (pull-down).

Logic Symbol

Truth Table

Pin Loading
Equivalent
A

~~

I·

Z

PADM

PADM

Load

L

L

A

3.0

H

Z

PADM

217.2

= High Impedance

Bolt Syntax: ............................ PADM .ODTXXN02 A;

Power Characteristics:
Parameter

Value

Static IDD (TJ

31.3

nA

270.8

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZl
tlz

15

50

75

100

150 (max)

4.98
0.37

13.13

18.92

24.68

36.16

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-62

DOIIINO"

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXN04 is a 4 mA, non-inverting, TTL-level, output buffer piece with N-channel, open-drain (pull-down).

logic Symbol

Pin loading

Truth Table

Equivalent

.

A

~qJ

I,

PADM

Load

L

L

A

4.2

H

Z

PADM

217.2

Z = High Impedance

Bolt Syntax: ............................ PADM .ODTXXN04 A;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

31.7

nA

275.1

Eq-Ioad

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZL
tLZ

15

50

100

200

300 (max)

2.61

6.94

12.93

24.81

36.77

DAD

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-63

ODTXXN08

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXN08 is an 8 mA, non-inverting, TIL-level, output buffer piece with N-channel, open-drain (pull-down).

Logic Symbol

Truth Table

Pin Loading
Equivalent
A

~~

I·

PADM

Load

L

L

A

4.2

H

Z

PADM

217.2

Z = High Impedance

PADM

Bolt Syntax: ............................ PADM .ODTXXN08 A;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EQLpd

Units

31.7

nA

280.2

Eq-Ioad

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To

15
tZL
tLZ

50

3.54
0.64

3.69

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-64

100

200

300 (max)

6.81

12.73

18.72

ODTXXN12

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXN12 is a 12 mA, non-inverting, TTL-level, output buffer piece with N-channel, open-drain (pull-down).

Logic Symbol

Pin Loading

Truth Table

Equivalent

~~

I-

A

PADM

L

L

A

Load
6.3

H

Z

PADM

217.2

Z = High Impedance

PADM

Bolt Syntax: ............................ PADM .ODTXXN12 A;

Power Characteristics:
Parameter

Value

Static 100 (TJ

32.6

nA

284.5

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: TJ = 25°C, Voo = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZL
tLZ

15

50

100

200

300 (max)

1.14
0.61

2.57

4.56

8.58

12.49

Oelay will vary with input conditions. See page 2-16 for interconnect estimates.

4-65

ODTXXN16

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXN16 is a 16 mA, non-inverting, TTL-level, output buffer piece with N-channel, open-drain (pull-down).

Logic Symbol

Truth Table

Pin Loading
Equivalent
A

~qJ.

I·

PADM

Load

L

L

A

6.3

H

Z

PADM

217.3

Z = High Impedance

PADM

Bolt Syntax: ............................ PADM .ODTXXN16 A;

Power Characteristics:
Parameter

Value

Units

Static IDD (TJ = 85°C)

32.6

nA

EQLpd

289.9

Eq-Ioad

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZL
tLZ

15

50

100

200

300 (max)

1.06
0.79

2.10

3.60

6.61

9.57

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-66

ODTXXN2l1

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXN24 is a24 mA, non-inverting, TTL-level, output buffer piece with N-channel, open-drain (pull-down).

logic Symbol

Pin loading

Truth Table

Equivalent

Nq]

I·

A

PADM

L

L

A

Load
6.3

H

Z

PADM

217.3

Z = High Impedance

PADM

Bolt Syntax: ............................ PADM .ODTXXN24 A;

Power Characteristics:

Static IDD (TJ

Units

Vlaue

Parameter

= 85°C)

EQLpd

32.6

nA

299.9

Eq-Ioad

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: TJ

=

25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tZL
tLZ

15

50

100

200

300 (max)

0.94
1.15

1.71

2.74

4.75

6.73

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-67

ODTXXEOl

~I'~

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXE01 is a 1mA, non-inverting, TTL-level, tri-state output buffer piece with active low enable.

Logic Symbol

Pin Loading

Truth Table

Equivalent

~

r"

PADM

EN

A

PADM

L

L

L

Load

L

H

H

EN

4.5

H

X

Z

PADM

217.4

A

4.7

Bolt Syntax: ............................ PADM .ODTXXE01 A EN;

Power Characteristics:
Parameter

Value

Static IDD (TJ

32.8

nA

285.3

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

25

35

50

75 (max)

A
PADM

tplH
tpHl

3.60
9.37

5.15
13.67

6.71
17.93

9.09
24.39

13.13
35.44

EN
PADM

tHZ
tlZ
tZH
tZl

0.82
0.39
3.59
9.46

5.23
13.76

6.88
17.98

9.29
24.39

13.12
35.53

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-68

ODTDE02

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXE02 is a 2 mA, non-inverting, TTL-level, tri-state output buffer piece with active low enable.

Logic Symbol

Truth Table

Pin Loading
Equivalent
EN

~

1:"

PADM

A

PADM

Load

L

L

L

A

4.7

L

H

H

EN

4.5

H

X

Z

PADM

217.4

Z = High Impedance

Bolt Syntax: ............................ PADM . ODTXXE02 A EN;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

EQLpd

Units

32.8

nA

288.7

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

75

100

150 (max)

A
PADM

tpLH
tpHL

2.06
5.19

4.80
13.28

6.79
19.08

8.78
24.88

12.76
36.47

EN
PADM

tHZ
tLZ
tZH
tZL

1.01
0.49
2.20
5.20

4.96
13.29

6.93
19.10

8.90
24.92

12.85
36.54

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-69

OOTBED4

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXE04 is a 4 mA, non-inverting, TTL-level, tri-state output buffer piece with active low enable.

Logic Symbol

Truth Table

Pin Loading
Equivalent

~

I:"

PADM

A

EN

PADM

L

L

L

Load
7.0

A

H

L

H

EN

5.7

H

X

Z

PADM

217.9

Z

= High Impedance

Bolt Syntax: ............................ PADM .ODTXXE04 A EN;

Power Characteristics:
Parameter

Value

Static IDD (TJ

34.3

nA

300.1

Eq-Ioad

=

85°C)

EQLpd

Units

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM
EN
PADM

To

15

50

100

200

300 (max)

tpLH
tpHL

1.26
2.92

2.68
7.16

4.70
13.08

8.74
24.95

12.75
36.99

tHZ
tLZ
tZH
tZL

1.01
0.46
1.37
2.95

2.83
7.18

4.87
13.10

8.89
24.98

12.86
37.01

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-70

ODTXXE08

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXEOB is an B rnA, non-inverting, TTL-level, tri-state output buffer piece with active low enable.

Logic Symbol

Pin Loading

Truth Table

Equivalent
EN

~

I:'

PADM

A

Load

PADM

L

L

L

A

2.B

L

H

H

EN

4.B

H

X

Z

PADM

21B.6

Z = High Impedance

Bolt Syntax: ............................ PADM .ODTXXEOB A EN;

Power Characteristics:
Units

Parameter

Value

Static IDD (TJ = B5°C)

37.1

nA

330.3

Eq-Ioad

EQLpd
See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

A
PADM

tpLH
tpHL

1.53
1.99

2.27
4.10

3.30
7.1B

5.32
13.21

7.33
19.0B

EN
PADM

tHZ
tLZ
tZH
tZL

1.09
1.03
1.30
1.96

2.09
4.05

3.15
7.0B

5.17
13.10

7.10
19.02

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-71

ODTXXE12

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXE12 is a 12 rnA, non-inverting, TIL-level, tri-state output buffer piece with active low enable.

Logic Symbol

Truth Table

Pin Loading
Equivalent

~

r

EN

A

PADM

L

L

L

L

H

H

EN

4.8

H

X

Z

PADM

218.9

PADM

Z

Load
A

2.8

= High Impedance

Bolt Syntax: ............................ PADM .ODTXXE12 A EN;

Power Characteristics:
Parameter
Static

IDD

(TJ

= 85°C)

EQLpd

Value

Units

37.1

nA

339.5

Eq-Ioad

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

A
PADM

t plH
tpHl

1.53
1.73

2.16
3.13

2.96
5.12

4.54
9.09

6.19
13.07

EN
PADM

tHZ
tlZ
tZH
tZl

1.25
1.20
1.32
1.64

1.94
3.04

2.77
5.02

4.39
9.00

5.97
12.99

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-72

ODTXXE16

AMERICAN MICROSYSTEMS,INC.

AM.6S 0.6 micron CMOS Standard Cells
Description:
ODTXXE16 is a 16 mA, non-inverting, TTL-level, tri-state output buffer piece with active low enable.

Logic Symbol

Pin Loading

Truth Table

Equivalent

:

A

EN

r ~

PADM

Load

L

L

L

A

2.8

L

H

H

EN

4.8

H

X

Z

PADM

219.0

Z = High Impedance

Bolt Syntax: ............................ PADM .ODTXXE16 A EN;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

37.1

nA

344.9

Eq-Ioad

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

A
PADM

tplH
tpHl

1.56
1.57

2.13
2.65

2.94
4.17

4.56
7.15

6.18
10.10

EN
PADM

tHZ
tlZ
tZH
tZl

1.25
1.39
1.32
1.53

1.94
2.56

2.77
4.05

4.39
7.05

5.97
10.05

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-73

ODTnE24

AMERICAN MICROSYSTEMS, INC.

AM.6S 0.6 micron CMOS Standard Cells
Description:
ODTXXE24 is a 24 mA, non-inverting, TTL-level, tri-state output buffer piece with active low enable.

Logic Symbol

Truth Table

Pin Loading
Equivalent

~

r"

EN

A

PADM

L

L

L

L

H

H

EN

4.8

H

X

Z

PADM

219.0

PADM

Z

Load
A

2.8

= High Impedance

Bolt Syntax: ............................ PADM .ODTXXE24 A EN;

Power Characteristics:
Parameter

Value

Static IDD (TJ

37.1

nA

354.9

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM
EN
PADM

To

15

50

100

200

300 (max)

tplH
tpHl

1.71
1.49

2.22
2.25

2.96
3.31

4.82
5.10

7.12
6.38

tHZ
tlZ
tZH
tZl

1.25
1.75
1.36
1.40

1.96
2.18

2.77
3.22

4.35
5.16

5.90
7.01

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-74

oDTXXXO1

AMERICAN MICROSYSTEMS,INC.

AM.6S 0.6 micron CMOS Standard Cells
Description:
ODTXXX01 is a 1 rnA, non-inverting, TTL-level output buffer piece.

Logic Symbol

Truth Table

Pin Loading

A

~

I-

PADM

L

L

H

H

Equivalent
Load
A

3.3

PADM

Bolt Syntax: ............................ PADM .ODTXXX01 A;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

31.3

nA

274.6

Eq-Ioad

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

25

35

50

75 (max)

3.61
9.29

5.18
13.69

6.73
18.04

9.08
24.52

13.13
35.24

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-75

ODTXXX02

AMERICAN MICROSYSTEMS.INC.

AMI6S 0.6 micron CMOS Standard COlis
Description:
ODTXXX02 is a 2 rnA, non-inverting, TIL-level output buffer piece.

Truth Table

Logic Symbol

Pin Loading

~

I·

PADM

A
L

L

H

H

Equivalent
Load
A

3.3

PADM

Bolt Syntax: ............................ PADM .ODTXXX02 A;

Power Characteristics:
Parameter
Static 100 (TJ

= 85°C)

EQLpd

Value

Units

31.3

nA

277.9

Eq-Ioad

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

75

100

150 (max)

2.07
5.31

4.89
13.39

6.89
19.16

8.87
24.94

12.75
36.51

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-76

ODTXD04

AMERICAN MICROSYSTEMS.ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXX04 is a 4 mA, non-inverting, TTL-level output buffer piece.

Logic Symbol

Truth Table

Pin Loading

A

~

I,

PADM

L

L

H

H

Equivalent
Load
A

4.2

PADM

Bolt Syntax: ............................ PADM .ODTXXX04 A;

Power Characteristics:
Parameter

Value

Static IDD (TJ

31.7

nA

287.1

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

1.34
2.96

2.76
7.16

4.77
13.16

8.80
25.10

12.82
36.98

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-77

ODTXXX08

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXX08 is an 8 mA, non-inverting, TTL-level output buffer piece.

Logic Symbol

Truth Table

Pin Loading

~

I·

A

PADM

Equivalent

L

L

Load

H

H

A

6.3

PADM

Bolt Syntax: ............................ PADM .ODTXXX08 A;

Power Characteristics:
Parameter

Value

Static IDD (TJ

32.6

nA

302.3

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

0.94
1.76

1.70
3.90

2.74
6.90

4.76
12.88

6.74
18.85

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-78

ODTXXX12

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXX12 is a 12 mA, non-inverting, TTL-level output buffer piece.

Logic Symbol

Truth Table

Pin Loading

~

I-

A

PADM

Equivalent

L

L

Load

H

H

A

7.6

PADM

Bolt Syntax: ............................ PADM .ODTXXX12 A;

Power Characteristics:
Parameter

Value

Static 100 (TJ

33.0

nA

313.3

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: TJ = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

0.92
1.39

1.52
2.77

2.34
4.77

3.94
8.77

5.55
12.69

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-79

ODTXXX16

AMERICAN MICROSYSTEMS,INC.

AM.6S 0.6 micron CMOS Standard Cells
Description:
ODTXXX16 is a 16 mA, non-inverting, TIL-level output buffer piece.

Logic Symbol

Truth Table

Pin Loading

~

I·

A

PADM

L

L

H

H

Equivalent
Load
A

8.2

PADM

Bolt Syntax: ............................ PADM .ODTXXX16 A;

Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EQLpd

Value

Units

33.4

nA

320.2

Eq-Ioad

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

0.98
1.07

1.59
2.29

2.38
3.77

3.96
6.75

5.60
9.75

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-80

ODTXD24

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODTXXX24 is a 24 mA, non-inverting, TTL-level output buffer piece.

Logic Symbol

Pin Loading

Truth Table

~

I·

A

PADM

Equivalent

L

L

Load

H

H

A

8.2

PADM

Bolt Syntax: ............................ PADM .ODTXXX24 A;

Power Characteristics:
Parameter

Value

Static IDD (TJ

33.4

nA

330.3

Eq-Ioad

= 85°C)

EQLpd

Units

See page 2-14 for power equation.

Output Delay Characteristics:
Conditions: TJ

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From
A
PADM

To
tpLH
tpHL

15

50

100

200

300 (max)

1.14
1.08

1.68
1.84

2.47
2.89

4.06
4.92

5.67
6.87

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

4-81

IBF1X3

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IBF1 X3 is a non-inverting, CMOS-level input clock-driver pad.
Logic Symbol

Truth Table

Pin Loading

PADM

QC

L

L

H

H

Equivalent
Load
PADM

126.3

CMOS

Bolt Syntax: ............................ QC .IBF1X3 PADM;
Power Characteristics:
Parameter
Static 100 (TJ

Value

= 85°C)

EQLpd

Units

28.5

nA

131.6

Eq-Ioad

See section 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, V OD

= 5.0V, Typical

Process

Delay (ns)

Number of Equivalent Loads

From
PADM

To
QC

Parameter

tpLH
tpHL

1

97

194

291

388 (max)

1.01
1.19

1.43
1.61

1.83
1.92

2.19
2.25

2.51
2.59

See section 2-16 for Interconnect estimates.

4-82

IBF7X3

AMERICAN MICAOSYSTEMS, INC.

AMIIS 0.1 micron CMOS Standard Cells
Description:
IBF7X3 is a non-inverting, TTL-level input clock-driver pad.
Pin Loading

Truth Table

Logic Symbol

PADM

QC

L
H

L
H

Equivalent
Load
PADM

126.3

TTL

Bolt Syntax: ............................ OC .IBF7X3 PADM;
Power Characteristics:
Parameter

Value

Static 100 (TJ = 85°C)

26.9

Units
nA

EOL pd

136.1

Eq-Ioad

See section 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, Voo

= 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
From
PADM

To
OC

Parameter

tpLH
tpHL

1

97

194

291

388 (max)

0.69
1.31

0.85
1.74

1.21
2.06

1.59
2.40

1.94
2.76

See section 2-16 for interconnect estimates.

4-83

~II~

IIF1X5

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
IIF1 X5 is a non-inverting, CMOS-level input clock-driver.

Logic Symbol

Pin Loading

Truth Table

-itt

IIF1X5

A

r-.

Q

CMOS

L

L

H

H

Equivalent
Load
A

5.1

Bolt Syntax: ............................ 0 .IIF1 X5 A;
Power Characteristics:
Parameter
Static IDD (TJ

= 85°C)

EOLpd
See section 2-14 for power equation.

Delay Characteristics:
Conditions: TJ = 25°C, V DD

Value

Units

28.5

nA

222.9

Eq-Ioad

= 5.0V, Typical

Process

Delay (ns)

Number of Equivalent Loads

From
A

To
Q

Parameter

tpLH
tpHL

20

116

212

308

404 (max)

0.73
0.96

0.91
1.10

1.06
1.29

1.22
1.45

1.37
1.58

See section 2-16 for interconnect estimates.

4-84

PP6GXBG

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
PP6GXBG is a V ss power supply pin for output buffers, input buffers, and core cells combined. The PP6GXBG is
intended for circumstances where output and core busses are tied together. It should not be used in conjunction with
PP6GXPG or PP6GXCG. One PP6GXBG must be used for each ground (Vss) pin for core cells and input buffers.

PP6GXBG
PIN

PAD

QC!

4-85

TO CORE

PP6GXBP

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
PP6GXBP is a V DD power supply pin for output buffers, input buffers, and core cells combined. The PP6GXBP is intended
for circumstances where output and core busses are tied together. It should not be used in conjunction with PP6GXPP
or PP6GXCP. One PP6GXBP must be used for each power (V DD ) pin.

PP6GXBP

PIN

PAD

QC

I

4-86

TO CORE

--------_._-----_._------

PP60XGO

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
PP6GXCG is a V ss power supply pin for core celis and input buffers only. One PP6GXCG must be used for each ground
(V ss) pin for the core celis and input buffers.

PP6GXCG

[

:~D

QC [ -

4-87

TOCORE

PP6GXCP

AMERICAN MICROSYSTEMS,INC.

AM.6S 0.6 micron CMOS Standard Cells
Description:
PP6GXCP is a Voo power supply pin for core cells and input buffers only. One PP6GXCP must be used for each power
(Voo) pin for the core cells and input buffers.

PP6GXCP

I :~D

ac I r - TO CORE

4-88

PP6GXCW

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
PP6GXCW is an optional power supply pin for connecting additional buses.

PP6GXCW

I :~D

QC

I r---

4-89

TO CORE

PP6GXPG

AMERICAN MICROSYSTEMS,ING.

AM.6S 0.6 micron CMOS Standard Cells
Description:
PP6GXPG is a Vss power supply pin for output buffers only. One PP6GXPG must be used for each ground (Vss) pin for
output buffers.

PP6GXPG

I ::D

PADM I ~

4-90

TO CORE

PP6GXPP

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
PP6GXPP is a Voo power supply pin for output buffers only. One PP6GXPP must be used for each power (Voo) pin for
the core celis and input buffers.

PP6GXPP
PIN
PAD

PADM

TO CORE

4-91

PORA

AMERICAN MICROSYSTEMS.ING.

AMI6S 0.6 micron CMOS Standard Cells
Description:
paRA is a power-on-reset.
When power is applied, the paR output is asserted low for at least 2 microseconds after the logic circuits become
operational. The active high RESET input also drives the paR signal to its active low state.
For proper operation, user-designed external circuitry must limit the slew rate of Voo power to a maximum of one volt per
microsecond. This ensures that the reset pulse will be properly output when Voo falls to zero and immediately returns to
its valid range.

Logic Symbol

Truth Table

Pin Loading

RESET

paR

L

H

H

L

Equivalent
Load
RESET

3.7

Bolt Syntax: ............................ paR .paRA RESET;

Power Characteristics:
Parameter

Value

Units

Static 100 (TJ = 85°C)

30.7

nA

EQLpd

59.35

Eq-Ioad

See page 2-14 for power equation.

Delay Characteristics:
Conditions: TJ

= 25°C, Voo = 5.0V, Typical

Process
Number of Equivalent Loads

Delay (ns)
Parameter
From

To

RESET

paR

tpLH

7064.00

RESET

paR

tpHL

9.71

1

13

Oelay will vary with input conditions. See page 2-16 for interconnect estimates.

4-92

I

26

I

38

I

51 (max)

ODQFE20M

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODQFE20M is a fundamental mode, enabled crystal oscillator, output buffer pad piece that runs over a frequency range
of 1 MHz - 20 MHz. 01 is the input from IDQC3. E is the oscillator high input enable. PADM is the bond pad to the Xtalout.

logic Symbol

logic Schematic
QC

E

Xtal·in

Xtal-out

Pin loading

Truth Table
PADM

E

01

L

L

H

*PADM

217.4

H

H

L

E

5.4

01

8.7

Equivalent Load

Bolt Syntax: ............................ PADM .ODOFE20M E QI ;

Power Characteristics:
Parameter
Static IDD (TJ

Value

= 85°C)

*EQLpd

Units

32.0

nA

289.5

Eq-Ioad

*See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical

Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

75

100

150 (max)

E

PADM

tpLH
tpHL

3.75
3.32

8.89
8.41

12.55
12.04

16.20
15.67

23.51
22.93

01

PADM

tpLH
tpHL

3.14
3.26

8.21
8.35

11.89
11.98

15.58
15.60

22.95
22.85

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Design Notes:
The ODOFE20M is the output cell of a two cell oscillator circuit. The 01 pin is to be connected the 00 pin of the IDOC3 oscillator input receiver piece.
Two package pins are required to create a complete oscillator.

4-93

ODQFE99K

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODOFE99K is a fundamental mode, enabled crystal oscillator, output driver pad piece that runs over a frequency range
of 32kHz - 1 MHz. 01 is the input from IDQC3. E is the oscillator high input enable. PADM is the bond pad to Xtal-out.

Logic Symbol

Logic Schematic
QC

E

~

PADM

Xtal·in

Xtal·out

Truth Table

Pin Loading
PADM

E

01

L

H

H

H

L

L

Equivalent Load
*PADM

217.4

E

01

4.0

Bolt Syntax: ............................ PADM .ODQFE99K E 01 ;

Power Characteristics:
Parameter
Static IDD (TJ

Units

Value

= 85°C)

*EOLpd

31.7

nA

279.3

Eq-Ioad

*See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J

= 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

E

PADM

tpLH
tpHL

01

PADM

tpLH
tpHL

15

25

35

50

75 (max)

6.57
6.74

9.48
9.49

12.35
12.24

16.70
16.37

24.20
23.30

6.70
6.61

9.59
9.47

12.52
12.28

16.95
16.41

22.92
21.82

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Design Notes:
The ODQFE99K is the output cell of a two cell oscillator circuit. The QI pin is to be connected the QO pin of the IDQS3 oscillator input receiver piece.
Two package pins are required to create a complete oscillator.

4-94

ODQTE60M

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Description:
ODQTE60M is an enabled crystal oscillator, output driver pad piece that runs over a frequency range of 20 - 60 MHz. 01
is the input from the IDQC3. E is the oscillator high input enable. PADM is the bond pad to Xtal-out.

Logic Symbol

Logie Schematic
QC

E

Xtal-in

Xtal-out

Truth Table

Pin Loading
PADM

E

01

L

L

H

*PADM

217.9

H

H

L

E

5.4

QI

8.7

Equivalent Load

Bolt Syntax:_ .. _. __ .___ ._ ............... PADM .ODQTE60M E QI;
Power Characteristics:
Parameter
Static 100 (TJ

Value

Units

32.0

nA

297.5

Eq-Ioad

= 85°C)

*EQLpd
*See page 2-14 for power equation.

Delay Characteristics:
Conditions: T J = 25°C, V DD = 5.0V, Typical Process
Capacitive Load (pF)

Delay (ns)
Parameter
From

To

15

50

100

200

300 (max)

E

PADM

tpLH
tpHL

2.57
1.98

5.26
4.61

8.97
8.33

16.36
15.77

23.91
23.22

01

PADM

tpLH
tpHL

1.84
1.91

4.49
4.53

8.25
8.30

15.72
15.77

23.15
23.14

Delay will vary with input conditions. See page 2-16 for interconnect estimates.

Design Notes:
The ODQTE60M is the output cell of a two cell oscillator circuit. The QI pin is to be connected the QO pin of the IDQC3 oscillator input receiver piece.
Two package pins are required to create a complete oscillator.

4-95

4-96

SECTION 5
MEGACELLS

III
I

~--------------------------~

Megacell
Overview

AMERICAN MICROSYSTEMS, INC.

Digital son Megaeells
Overview

Why Megacells

American Microsystems, Inc. (AMI) provides a wide
selection of Megacells for use in the development of
ASICs; they ease the design of "systems on silicon". Chip
designers today are faced with short time-to-market. at
the same time gate arrays and standard cells are allowing
designs of up to several hundred thousand gates.
Complex elements allow greater functionality without
adversely affecting a design schedule. In fact they can
accelerate time-to-market.
Megacells also provide industry standard functions that
have been proven in silicon. Reducing design time, board
space, system costs, and power requirements while
increasing reliability and performance, AMI Megacells
enable the ASIC designer to develop chips that take on
the characteristics of systems.
The terms megacell, megamacro, megafunction,
macrocell, core and other trademarked terms are
prevalent in the industry today. These ~~rms are. often
interchangeable, and some have specific meaning ~o
various companies. They refer to complex blocks o~ log~c
that implement a digital function. Often the function IS
compatible to a standard product like an 8051. Other
times the function is more generic; a configurable PCI
controller, for example. Sometimes there is associated
physical data, sometimes not. "Core" ofte~ refers to a
complex function that has hand-packed phYSical data and
an associated standard physical interface. It cannot be
modified by the end user.

Using megacells in designing ASICs has several
advantages. Megacells help decrease design time and
cost by providing large building blocks that are the
equivalent of standard products and functions. The pow~r
consumption of a soft megacell can be greatly reduced I~
comparison to the HMOS standard product that It
replaces. Also, because several functions can be p~t on a
single die, printed circuit board space and capacitance
can be saved and the power requirements to get signals
on and off ICs are minimized.
Reliability and system costs improve because of
decreased part and pin counts. Also, because the
megacell is typically implemented in a process
technology smaller than the original standard product,
performance can be several times that of the standard
product.

Core Processors and Peripherals
The Core Processor and Peripheral megacells are
designed to duplicate the function of industry standard
parts. The datasheets for these megacells are intended
to give a short overview, to define cell pinout and to
outline any functional differences between A~I's
megacell and the industry standar~ part. Detailed
functional information can be found In any standard
device datasheet.

Core Processors
MEGACELL

At AMI we refer to all complex functions as Megacells.
These are broken down into Cores (8051 and 6502 code
compatibles etc.), peripherals (UARTs, SCSI controllers,
timers, RTCs etc.), datapath (multipliers, adders, shifters
etc.), and FIFOs.
AM I offers a selection of soft Megacells that duplicate the
function of industry standard parts (core processors and
peripherals), and Megacells developed by using
parameterized logic synthesizers (Datapath and FIFOs).
AMI's strategy is to make all megacells soft. This works
well except for certain FIFOs that require the use of RAM
(a hard cell). Some megacells are defi.ned using ~HDL
while others are netlist based. There IS no associated
physical data with AMI's megac~lIs. The physical. mask
layout will be different for each Instance depending on
other functions being used, the place-and-route tools,
and process technology. Because our Megacells are soft,
they are technology independent and many can be
customized to meet your particular needs.

5-1

FUNCTION

MG29C01

4-Bit microprocessor slice

MG29C10

Microprogram controller/sequencer

M320C25

DSP processor

M320C50

DSP processor

MG65C02

8-Bit microprocessor

M8042

8-Bit slave microcontroller

M8048

8-Bit microcontroller

MG80C85

8-Bit microprocessor

MGMC32

Core processor, 8032 compatible

MGMC321

MGMC32 with ICE port

MGMC32FB

Core processor, 8032FB compatible

MGMC32SD

Reduced function MGMC32

MGMC51

Core processor, 8051 compatible

MGMC51I

MGMC51 with ICE port

Megacell
Overview

~I'~

AMERICAN MICROSYSTEMS,ING.

Digital son Megaeells
MEGACELL

FUNCTION

MGMC51FB

Core processor, 8051 FB compatible

MGMC51SD

Reduced function MGMC51

Datapath
MEGACELL

Peripherals
MEGACELL

FUNCTION

MG1468C18

Real-time clock

M16C450

UART

M6402

UART

M6845

CRT controller

M765A

Floppy disk controller

M8251A

Communication interface USART

M8253

Programmable interval timer

M82530

Serial communications controller

MG82C37A

Programmable DMA controller

FUNCTION

MGAxxyyDv

Adder

MGAxxyyEv

Adder-subtractor

MGBxxyyAv

Barrel/arithmetic shifter

MGBxxBv

Barrel shifter

MGBxxyyCv

Arithmetic shifter

MGCDxxAv

Decrement Counter

MGCUxxAv

Increment Counter

MGCxxAv

2-function comparator

MGCxxBv

6-function comparator

MGDxxAv

Decrementer

MGlxxAv

Incrementer

MGlxxBv

Incrementer/decrementer

MGMxxyyDv

Multiplier

MGMxxyyEv

Multiplier-accumulator

MGSxxyyAv

Subtractor

MG82C50A

Asynchronous comm. element

MG82C54

Programmable interval timer

MG82C55A

Programmable peripheral interface

MG82C59A

Programmable interrupt controller

M8490

SCSI controller

M85C30

Serial communications controller

MGFxxyyC1

Latch-Based FIFO

M8868A

UART

MGFxxxxyyD

Synchronous FIFO

M91C36

Digital data separator

MGFxxxxyyE

Asynchronous FIFO

M91C360

Digital data separator

Soft Megacells

MFDC

Floppy disk controller

MGI2CSL

12C Serial bus slave transceiver

MI2C

12C Bus interface

Soft Megacells provide extreme flexibility with regard to
design changes, testability, fault grading, design
checking, process selection, and whether the design is
implemented as a Gate Array or Standard Cell. Also, to
improve the robustness of the Megacell, AMI's Megacells
are built with fully static logic and no internal tristates.

FIFOs
MEGACELL

Datapath, FIFOs

FUNCTION

Since no physical entity is associated with the Megacell,
its characteristics and functions can be changed or
deleted. For example, to change the initial conditions of
the MGMC51 output ports, it is only necessary to change
the output port flip-flop in each port cell from a set type of
flop to a reset type of flop.

Most of these megacells are produced using
parameterized synthesizers which allow the creation of
various megacell sizes and speeds. They can be
optimized for either minimum delay, minimum gate count
or can be designed to meet a specified delay.
These synthesizers produce soft megacell schematics in
the ASIC Standard Library and are available on various
workstations. The datasheets contain a functional
description, a pin description, and sample equivalent
gate counts with sample delays.

By deleting unused functions, gate count can be
minimized. For example, if a timer or UART is not being
used, it can be deleted resulting in a lower gate count.
Running the simulations, as one would do after any
5-2

Megacell
Overview

AMERICAN MICROSYSTEMS, INC.

Digital son Megacells
design change, validates correct implementation of the
design change.
However, it is in design checking where the strengths of
the soft Megacell approach become obvious. Electronic
design has benefited from the recent introduction of
software programs that check many aspects of the
design, including set up and hold times for flip-flops, the
possibility of asynchronous race conditions, and the fault
coverage of the test vectors. The netlist implementation of
the Megacell can be subjected to these checks along with
the rest of the circuitry. Behavioral models, which are
frequently used with hard Megacells, bypass these
checks.

megacell. When enabled by this test mode, the megacell
pins are connected to the pins of the ASIC. The supplied,
or independent, simulation patterns can then be run to
develop a test or to verify the functionality of the
Megacell.
There are a number of ways to implement a test-mode.
The simplest is to use an otherwise unused pin. Another
approach is to use two or three ASIC pins and determine
an unused condition in normal operation. This condition
can then be used to enable the test-mode. Finally, in a
bus oriented design, it may be possible to write to an
unused register bit to signify test-mode.

Timing

Since the soft megacell uses only components of the
ASIC standard library, process dependencies in the
design are minimized, if not completely removed. As a
result, the design can be ported to new technologies as
they become available. This means not only future cost
savings, but extended voltage and temperature operation
as well.

Bidirectional Pins
Many of AMI's Megacells are functional equivalents of
standard products which have bidirectional pins. A
bidirectional pin can be either an input or an output. To
make our megacells easier to use and to reduce the
possibility of excess current, AMI has split these single
bidirectional pins into three pins: input, output and
control.
If it is necessary to recombine these pins into a single
bidirectional pin, the logic in the following figure can be
used. If the bidirectional pin is to become a pin on the
ASIC, this logic can come from a pad cell. Often the
control pin controls a bank of bidirectional pins.

Electrical Characteristics
AMI's Megacells do not have any direct external
connections to the pins of an ASIC. All necessary
connections should be made with pad buffers external to
the Megacell. The selection of the pad buffer--if one is
used--is up to the system designer, and that selection will
establish the DC electrical characteristics of the final
design.

Split-Pins to Bidirectional-Pin Logic
megaceli

Because AMI's Megacells are technology independent
the electrical and timing characteristics of the design will
depend on the process, layout, and implementation.
When the Megacell is included in a design, delays can be
estimated using the customer-preferred logic simulator
and delay calculator. Post-layout simulations using actual
capacitance numbers will provide even more accurate
timing characteristics.
Datapath Megacells are designed to have delays that
meet the user's timing requirements. These delays may
change slightly when the Megacells are incorporated into
the ASIC.
Our Core Processor and Peripheral Megacells have
simple pin-to-pin relationships with all input changes
expected on the cycle boundary. Some Megacell clocks
expect signals that are in the return-to-one or return-tozero format. Functional timing diagrams are available for
Megacells that have more complex timing relationships.

pad or core logic

control
output

Testing

All inputs to the Megacells are one to four logical loads.
All outputs are buffered so that loading on a given pin will
not affect the internal operation.

Testability of Megacells in ASIC designs is important.
Usually, additional logic is necessary to simplify testing.
Providing either direct or multiplexed input and output
pins for controlling and observing the Megacell can
greatly simplify testing and system debugging. This
dictates that designs are contained in packages having at
least as many pins as the Megacell with the highest pin
count.
If some pins on the ASIC will be multiplexed between
their normal function and a megacell function a test-mode
will be needed to apply the simulation patterns to the

To order a Megacell, complete the "ASIC Megacell Orderform", available from any AMI databook, and submit by
fax (208-234-6659), email (megacells@poci.amis.com),
or from AMI's internet homepage (http://www.amis.com).
Current Megacell information can also be obtained at
AMI's homepage.
Prices for Megacells are charged on a per-use basis. This
charge is encountered each time the cell is used on a
new design. A few Megacells also have an associated
royalty. Contact Marketing for a price quote.

input

Ordering and Availability

5-3

5-4

MG29COl

4-Bil Microprocessor

AMERICAN MICROSYSTEMS,INC.

Digital son Megacells
Features

Description

• A high-performance, low-power CMOS megacell
featuring functional compatibility with the industry
standard 2901

The MG29C01 is a high-performance 4-bit cascadable
microprocessor.
The MG29C01 offers the designer a simple and
methodical
approach
to
designing
bit-slice
microprocessors, high-speed ALUs and boolean
machines.

• Soft megacell technology allows customizing of function
• Uses the ASIC Standard Library for technology
independence

The MG29C01 consists of a fast ALU, a 16-word by 4-bit
two port RAM and the required decoding, multiplexing and
shifting circuits. The microinstruction word consists of nine
bits divided into three groups. Bits 0-2 select the ALU
source operads. Bits 3-5 select the ALU function and bits
6-8 select the destination register.

• 4-Bit cascadable bit-slice
• Eight function ALU including addition, two subtraction
and five logic operations on two operands
• Microprogrammable with three groups of three bits each
for ALU function, destination control and source operand

The ALU allows for several arithmetic functions which
include: unsigned addition and subtraction, two's
complement and one's complement addition and
subtraction, and decrementing. The ALU also produces
the status bits: overflow, carry-out, FO. Boolean functions
offered include: AND, OR, XOR, XNOR, INVERT, PASS,
ZERO, and MASK.

• Two address architecture provides independent access
to two working registers
• Five source ports for data selection
• Four status flags including carry, zero, overflow and sign

LOGIC SYMBOL

The MG29C01 also includes a 16-word by 4-bit register, a
4-bit Q register, and various sources for the ALU.

MG29C01

1(8:0)
001
031
RAMOI
RAM31
CIN

GlK

000
030

Soft Megacells

FO

This soft megacell is in the ASIC Standard Library which is
technology and process independent and is available in
both Standard Cells and Gate Arrays.

F3
GN
PN

A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

GOUT
OVR
RAMOO
RAM30
OEON
OE3N

Contact the factory for more information.

Y(3:0)

5-5

MG29COl

II-Bit Microprocessor

AMERICAN MICROSYSTEMS,INC.

Digital son Megaeells
Pin Description
SIGNAL

TYPE

1(8:0)

Input

SIGNAL DESCRIPTIONS
The nine instruction lines.

GIN

Input

Garry in to the ALU.

GLK

Input

The clock input.

0(3:0)

Input

Data inputs. These data may be selected as one of the ALU sources. 0(0) is the LSB.

A(3:0)

Input

The address inputs to the register stack, used to select which register's contents are
available through the A port. A(O) is the LSB.

8(3:0)

Input

The address inputs to the register stack used to select which registers contents are
available through the B port. B(O) is the LSB.

00O,Q30
QOI, Q31

I/O

Fa

Output

Becomes active when all four ALU outputs are low.

F3

Output

The most significant ALU output bit.

GN, PN

Output

The generate and propagate outputs of the ALU, can be used to for carry look-ahead.

GOUT

Output

Garry out of the ALU.

OVR

Output

Overflow. Indicates the result of an arithmetic two's complement operation has overflowed
into the sign bit.

OEON

Output

A low on this pin indicates 000 and RAMOO are valid.
A low on this pin indicates 030 and RAM30 are valid.

The input and output shift lines for the LSB and MSB of the 0 register, allow for shift up
and shift down operations. Q3 is the MSB. QOO is valid when OEON is low and Q30 is
valid when OE3N is low.

OE3N

Output

RAMOO,
RAM30
RAMOI,
RAM31

I/O

The input and output shift lines for the LSB and MSB of the register stack, allow for shift
up and shift down operations. RAM3 is the MSB. RAMOO is valid when OEON is low and
RAM30 is valid when OE3N is low.

Y(3:0)

Output

Data outputs. These outputs are connected to either ALU or A port of the register stack.

Equivalent Gates
STANDARD CELL

GATE ARRAY

810

1000

5-6

MG29Cl0
12-Bit Microprogram Controller

AMERICAN MICROSYSTEMS,INC.

Digital son Megacells
Features

Description

• A high-performance, low-power CMOS megacell
featuring functional compatibility with the industry
standard 291 0

The MG29C1 0 is a high-performance 12-bit microprogram
controller. It functions as an address sequencer for
controlling the execution of microinstructions in
microprogram memory.

• Soft megacell technology allows customizing of function

It also controls conditional branching to any
microinstruction within its 4096 word range. There are nine
levels of subroutine nesting with return linkage and looping
capability provided by a last-in, first-out stack.

• Uses the ASIC Standard Library for technology
independence
• 12-Bit internal elements can address up to 4069 words of
microcode

The MG29C10 has four sources for providing the 12-bit
address during each microinstruction. These four sources
are as follows:

• 16 sequence control instructions, most are conditional on
state of internal loop counter and/or external conditional
input
• 12-Bit down counter is pre-settable for repeating
instructions or counting loop iterations internally

1.

A direct external input.

2.

• Four microprogram address sources including 9-level
stack, microprogram counter, branch address bus, and
internal holding register

A register/counter (R) which retains data loaded
during an earlier microinstruction.

3.

The last-in, first-out stack/file (F).

4.

The address counter/register which usually
increments the addresses .

• Internal decoder function controls output enables for
three branch address devices

The MG29C10 consists of six functional blocks: an
instruction PLA, a multiplexer, a register/counter, a zero
detector, a 9-word by 12-bit stack, a microprogram counter
register, and an incrementer.

LOGIC SYMBOL
MG29C10

Soft Megacells

CCN
CCENN
CI

RlDN

This soft megacell is in the ASIC Standard Library which is
technology- and process-independent and is available in
both Standard Cells and Gate Arrays.

FUllN 0 - PlN 0 - MAPN 0 - -

A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

VECTN 0 - -

ClK

Y(11:0)

Contact the factory for more information.

5-7

MG29Cl0
12·Bit Microprogram Controller

AMERICAN MICROSYSTEMS,ING.

Digital son Megacells
Pin Description
SIGNAL

TYPE

CCN

Input

CCENN

Input

Enables CCN. Active low.

CI

Input

Carry input to the low order of the microprogram counter.

RLDN

Input

Forces loading of register/counter regardless of instruction or condition. Active low.

ClK

Input

Master input clock.

D(11 :0)

Input

Direct data input to register/counter and multiplexer. D(O) is the lSB.

SIGNAL DESCRIPTIONS
Used as test input criterion. Active low.

1(3:0)

Input

FUllN

Output

Goes low when the internal stack is full. Active low.

PlN

Output

Used to select #1 source (usually a pipeline register) as the direct input source.

MAPN

Output

Used to select #2 source (usually a mapping ROM or PlA) as the direct input source.

Instruction inputs. 1(0) is the lSB.

VECTN

Output

Used to select #3 source (usually an interrupt starting address) as the direct input source.

Y(11 :0)

Output

Address to microprogram memory. Y(O) is the lSB.

Equivalent Gates
STANDARD CEll

GATE ARRAY

1,350

1,950

5-8

M320C25
DSP

AMERICAN MICROSYSTEMS,INC.

Digital son Megaeells
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The M320C25 is a digital signal processor with separate
data and program memory, both of which may be up to 64k
words. It has a 16-bit shifter, a 16 X 16 bit parallel multiplier
and a 32-bit ALU/accumulator. Instructions are pipelined
and it can perform single-cycle multiply/accumulate
instructions. It contains a 16-bit timer, eight auxiliary
registers, an eight-level hardware stack, sixteen input and
sixteen output channels, and a serial port. It is fully
compatible, including instructions execution times, with
industry standard devices.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• 32-bit ALU/accumulator
• 16 X 16 parallel multiplier
• 16-bit shifter
• Up to 64k words of program memory
• Up to 64k words of data memory

The M32C25 contains no RAM or ROM but provides
functional interconnect signals for connecting to memory
blocks. If internal program memory is required, a single
port RAM (or ROM) block of up to 4k X 16 may be
connected to the M320C25 (also the 256 X 16 internal
data RAM block 0 may be configured as program
memory). If internal data memory is required 1,2 or 3
blocks of dual-port RAM may be connected to the
M320C25. Block 0 and 1 can be up to 256 X 16 and block
2 up to 32 X 16.

• 16-bit timer
• Serial port
• Equivalent gates: 17,000

LOGIC SYMBOL
M320C25
D10-15
READY
NHOLD
NINTO
NINT1
NINT2
NBIO
NRS
NX2
NSYNC
MPNMC
CLKR
CLKX
DR
FSR
FSXI
MDO-15
BZDO-15
BODO-15
BTDO-15

AO-15
NDS
NPS
NIS
RNW
NSTRB
NHLZ
ODO-15
NDEN
NBR
NHLDA
NIACK
NMSC
XF
CLLKOUT1
CLKOUT2
DX
NDXE
FSXD
NFSXE
NRDBO
NWRBO
NRDB1
NWRB1
NRDB2
NWRB2
RAO-7
WAO-7
BZWAO-7
BZRAO-7
MAO-11
NMWE
NMOE

5-9

M320C50
DSP

AMERICAN MICROSYSTEMS, INC.

Digital Soft Megaeells
Features

Description

• AMI's implementation of 380ft'S MegaMacro®

The M320C50 is a digital signal processor with separate
data and program memory. The program memory may be
up to 64k words. The data memory may be up to 64k
words, up to 32 words of which may be global access. It
has 64k 16-bit I/O ports, sixteen of which are memory
mapped. The central ALU has a 32-bit arithmetic logic unit,
a 32-bit accumulator and accumulator buffer, a 16-bit
scaling shifter, and a 16 X 16 parallel multiplier. A separate
parallel logic unit can perform bit manipulations on any
data memory location or control/status register. It has eight
auxiliary registers, an eight level hardware stack, and a
four stage instruction pipeline. The M320C50 contains no
ROM or RAM but provides functional interconnect signals
for connecting to memory blocks

• Functionally compatible with the industry standard
• 32-bit ALU/accumulator
• 16 X 16 parallel multiplier
• 16-bit shifter
• 16-bit parallel logic space
• Up to 64k words each of program and data memory
• 64K I/O space
• Interrupt controller
• 8erial port and TDM serial port
• Equivalent gates: 40,000

Peripherals are controlled through 28 memory-mapped
registers and consists of: a timer, a serial port, a timedivision-multiplexed serial port, a programmable wait-state
generator, an interrupt controller, and the I/O ports.

LOGIC SYMBOL
M320C50
A10-14
010-15
REAOY
NHOLO
RNWI
NBIO
NRS
NCLKI
MPNMC
NBRI
NSTRBI
NNMI
NINT1
NINT2
NINT3
NINT4
CLKR
CLKXI
TCLKR
TCLKXI
OR
TOR
FSR
FSK
TFSR
TFSXI
BOOO-15
B100-15
B200-15
POO-15
SOO-15
OROY
PROY

000-15
1000-15
NOEN
NOS
NPS
NIS
RNWO
NSTRBO
NRO
NWR
NBR
NIAQ
NHLOA
NIACK
XP
CLKO
NHOP
IOLE2
TOUT
OX
NOXE

The M320C50 is compatible, including instructions
execution times, with industry standard devices.

TDX

NTOXE
CLKXO
NCLKXE
TCLKXO
NTCLKXE
TAOO
NTAOOE
FSXO
NFSXE
TFSXO
NTFSXE
NBROO-2
NBWRO-2
RAD-8
WAO-8
BORAO-8
ROWAO-8
PRAO-14
PWAO-14
PRNW
NPCE
NPWE
NPOE
SARAO-14
SAWAO-14
SRNWO-15
SPNOO-15
NSCEO-15
NSWE
NSOE

5-10

MG65C02
8-Bit Core Microprocessor

AMERICAN MICROSYSTEMS,INC.

Digital Soft Megaeells
Features

Description

• High-performance, schematic-based megacell

The MG65C02 is an 8-bit microprocessor which is
compatible with the industry standard W65C02S. It has
been designed to be compatible with both the original
NMOS 6502 and the newer CMOS variations from various
vendors.

• Functional compatibility with the industry standard 6502
• Soft megacell technology allows customizing of function
• Uses the ASIC Standard Library for technology
independence

The MG65C02 runs all 6502 opcodes as well as the new
Enhanced Instruction set which include the new bit
manipulation opcodes - RMB, 5MB, BBR, BBS, and WAI
and STP instructions. The latest functions are also
incorporated in the MG65C02 such as Bus Enable, VectorPull, and Memory Lock. It accesses 65 kbytes of
addressable Memory. It is fully static allowing the external
clock to stop in either state. Operation frequency follows a
range of 0 MHz, for low power or standby modes, to more
than 25 MHz for high speed applications.

• 8-Bit Microprocessor
• Fully Static Design
• 0-33 MHz Operation
• 64 kbytes Program Address Space
• Enhanced Instruction Set
• Supports Bit Manipulation
• 72 instructions and 212 opcodes
·15 address modes

Soft Megacells

• Interrupt Capability

The MG65C02 is designed as a soft megacell in the ASIC
standard library, which allows it to be used with other logic
and/or megacells. The soft megacell approach has
advantages of design flexibility and portability, and a path
for future cost reduction by process migration. It can be
used in gate array or standard cell circuits. The core allows
access to pins and functions not available in the industry
standard 6502.

LOGIC SYMBOL
MG65C02
ROYI

ROYO

RESN

RWN
SYNC
VPN

IRON
NMIN
SON
PHI21N

A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

MLN
PHI10UTN
PHI20UT

OBI(7:0)
OBEN

Contact the factory for more information.

5-11

MG65C02
8-Bil Core Microprocessor

AMERICAN MICROSYSTEMS,INC.

Digital son Megaeells
Pin Description
SIGNAL DESCRIPTION

SIGNAL

TYPE

AO-A15

0

Address to memory.

OBOO-OB07

0

Oata bus output. Valid when OBEN is high.

OBI0-OBI7

I

Oata bus Input. Should be valid when OBEN is low.

OBEN

0

Oata Bus Enable.

ROYI

I

Ready Input, active low. Stops the internal clock.

RDYO

0

Ready Output. The WAI instruction uses this pin to bring ROYI low.

RESN

I

Active low Reset.

IRON

I

Active low Interrupt.

NMIN

I

Active low Non-maskable interrupt.

SON

I

Active low sets the overflow bit in the status word.

RWN

0

Read/Write. Active low for write.

SYNC

0

Synchronize. Active during opcode fetch cycle.

VPN

0

Vector Pull, active low. Low during interrupt vector access.
Memory Lock, active low. Low during Read-Modify-Write (RMW) portion of RMW instructions.

MLN

0

PHI21N

I

PHI10UTN

0

Clock. Out of phase with C2IN.

PHI20UT

0

Clock. In phase with PHI2IN. It also goes high with the STP instruction.

Clock.

Equivalent Gates
STANDARD CELL

GATE ARRAY

2,950

3,850

5-12

M8042
8-Bil Slave Microconlroller

AMERICAN MICROSYSTEMS,ING.

Digital Soft Megaeells
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The M8042 is an 8-bit slave microcontroller. This
microcode-free design is software compatible with
industry standard discrete devices. It can address data
RAM of up to 256 bytes and program RAM or ROM of up
to 4K bytes. If program memory is implemented with RAM
a special down-load mode is available to program the
RAM. An 8-bit timer/counter and 18 I/O pins are available.

• Functionally compatible with the industry standard 8042
• Uses AMI's ASIC Standard Library for technology
independence
• Up to 256 bytes of data memory
• Up to 4K bytes of program memory
• Memory down-load mode
• 8-bit timer/counter
• DMA, interrupt or polled operation supported
• Power saving modes
• Equivalent gates (does not include RAM or ROM):
Standard Cell - 2,750; Gate Array - 3,500

LOGIC SYMBOL
M8042
B10-7
IBO-7

NX1
NCS
NWR
NRD
NSS
TO
T1
NRES
EA
SSH
NTST
F10-7
MDO-7
HIM

BOO-7
NBEN
OBO-7
NBO-7
OCO-7
NCBO-7
FAO-7
FOO-7
NFWE
MO-11
DLM
NMOE
SYNC
TOO
NTOE
PROG
NMWE
NFOE
XOFF

Data is transferred between the M8042 and a master CPU
through separate input and output data bus buffers.
Communication can be controlled by two DMA
handshaking lines or by interrupts.
The M8042 has two power saving modes; soft power down
mode and hard power down mode. In soft power down
mode the clock to the ALU is stopped but the timer/counter
and interrupts are still active. In hard power down mode
the clock to the entire M8042 is stopped.
Signals are present that allow the end user to choose the
appropriate memory block for each implementation. This
allows memory size to be configured, and if necessary, the
program memory block may be implemented as "downloadable" RAM.
As no I/O cells are included in the design, all bidirectional
lines (the Data Bus, the Port1 and Port2 buses) are split
into input and output sections, and have associated control
lines for enabling and disabling 3-state buffers where
appropriate. There are individual enable lines for each of
the Port1 and Port2 outputs. This allows implementation of
the 'quasi-bidirectional' pins feature of the original device.
There is only one clock input (NX1), this is again due to the
fact that there are no I/O cells in the design. The output of
a suitable crystal oscillator I/O cell should be connected to
this input. XOFF (which is high true) is used to disable the
oscillator I/O cell in power saving mode.
This megacell requires the use of ROM and RAM which
can be ordered from the AMI Memory group.
A per-use fee is associated with this megacell. Contact the
factory for more information.

5-13

MIDIII
I-Bil Microconlroller

AMERICAN MICROSYSTEMS, INC.

Digital Soft Megaeells
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The M8048 is an 8-bit microcontroller. This microcode-free
design is software compatible (including instruction
execution times) with industry standard discrete devices, It
can address data RAM of up to 256 bytes and program
RAM or ROM of up to 4k bytes. If program memory is
implemented with RAM a special down-load mode is
available to program the RAM. An 8-bit timer/counter and
27 I/O lines are available, and both internal and external
interrupts are supported.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• Up to 256 bytes of data memory
• Up to 4K bytes of RAM or ROM program memory
• Memory down-load mode
• 8-bit timer/counter
• Power saving modes
• Equivalent gates:
Standard Cell - 2,770; Gate Array - 3,470

LOGIC SYMBOL
M8048
B10-7
IBO-7
C10-7
NX1
NDLW
NDLR
NINT
NSS
TO
T1
NRES
EA
SSH
NTST
F10-7
MDO-7
HIM

The M8048 has two power saving modes; soft power down
mode and hard power down mode. In soft power down
mode the clock to the ALU is stopped but the timer/counter
and interrupts are still active. In hard power down mode
the clock to the entire M8048 is stopped.
A per-use fee is associated with this megacell. Contact the
factory for more information.

BOO-7
NBEN
OBO-7
NBO-7
OCO-7
NCBO-7
FAO-7
FOO-7
NFWE
MO-11
PSEN
DLM
NMOE
ALE
TOO
TOEN
PROG
NWR
NRD
NMWE
NFOE
XOFF

5-14

MG80C85
8-Bil Microprocessor

AMERICAN MICROSYSTEMS,INC.

Digital son MegaeeUs
Features

Description

• A high-performance, low-power CMOS megacell
featuring functional compatibility with the industry
standard 8085 and 8085A

The MG80C85 is an 8-bit microprocessor which features
complete functional compatibility with industry standard
8085s and 8085As, and includes support for the special
extended instruction set. Its design incorporates an
onboard system controller, clock generator, serial I/O port
and direct addressing capability to 64K bytes of memory.
The MG80C85 utilizes a multiplexed data bus, with 16-bit
addresses split between an 8-bit address bus and an 8-bit
data bus.

• Soft megacell technology allows customizing of function
• Uses the ASIC Standard Library for technology
independence
• Full support of extended instruction set, and standard
8080 and 8085/8085A instruction sets
• Runs over 10,000 CP/M® programs
• Direct addressing to 64 kbytes
• Four Interrupt inputs (one non-maskable)

The MG80C85 is a macrocell building block for ASIC Logic
design. Thus it can be used in conjunction with existing
standard cell and gate array libraries to incorporate into
original customer IC designs for lower overall system
costs.

LOGIC SYMBOL

Soft Megacells

MG80C85
ClK

ClKB2

HOLD

HlDA

INTR

INTAN

RST5.5
RST6.5

SO
S1

RST7.5

101M

TRAP

WRN

READY

RON

RESETN

ALE
RO

This soft megacell is in the ASIC Standard Library which is
technology- and process-independent and is available in
both Standard Cells and Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.
Contact the factory for more information.

SID
SOD

5-15

MGIOC85
8-Bit Microprocessor

~II~

AMERICAN MICROSYSTEMS,INC.

Digital Soft Megacells
Pin Description
SIGNAL

TYPE

SIGNAL DESCRIPTIONS

A(1S:8)

0

High Address Bus. The most significant 8 bits of the memory address. A(15) is the MSB.

AD(7:0)

1/0

Low Address and Data Bus. The low order memory address bus multiplexed with the data bus.

ALE

0

Address Latch Enable. This signal occurs during the first clock state of a machine cycle.

CLK

0

Clock. The period of CLK is twice the period of the CLKBY2 input.

HLDA

0

HOLD

I

INTAN

0

Interrupt Acknowledge. This active low signal indicates that the interrupt request input (INTR) has
been recognized and acknowledged.

INTR

I

Interrupt Request. When INTR goes HIGH, it will inhibit the Program Counter, generate an INTA)
signal, and sample the data bus for a RESTART or CALL instruction.

101M
RON,
WRN

a
a

READY

I

Ready. This signal is set to HIGH during read or write cycles to indicate that the selected memory
or 1/0 device is ready to send or receive data.

RESETN

I

Reset In. This active low signal sets the Program Counter to zero, and resets the interrupt enable
(INTE) and HLDA flip-flop.

Hold Acknowledge. Indicates that the CPU has received the HOLD request.
Hold Request. Indicates another master is requesting the use of the address and data buses.

Machine Cycle Status. See SO and S1 status bits for further details.
Read and Write Control. These active low signals indicate that selected memory or 1/0 device is to
be read or written to. They are high impedance during HOLD, HALT and RESET modes.

RO

0

RST7.5
RST6.5
RST5.5

I

Restart Interrupts. These inputs provide three maskable interrupts which invoke an automatic
internal restart. RST7.5 is the highest relative priority, followed by RST6.5 and RST5.5. All three
interrupts have a higher priority than INTR.

SO,S1,
IaiM

0

Status Outputs. These signals provide an indication of the machine status during any given cycle.
The status may be latched by the falling edge of the ALE signal.

SID

I

SOD

0

TRAP

I

Trap Interrupt. The highest priority non-maskable restart interrupt.

CLKBY2

I

Clock by Two. This is the input clock source, used to drive the internal clock generator.

Reset Out. Indicates that the CPU is being reset.

Serial Input Data. Data on this pin is loaded into accumulator bit 7 during a RIM instruction.
Serial Output Data. This signal is set or reset by the SIM instruction.

Equivalent Gates
STANDARD CELL

GATE ARRAY

TBD

TBD

5-16

MGMC51 Family
8-Bil Core Microconlrollers

AMERICAN MICROSYSTEMS, INC.

Digital son Megaeells
All controllers are supported by a multiple source, two level
interrupt capability. The core processor supports up to 256
bytes of scratch pad RAM and up to 64K of ROM. The size
of the internal ROM may be adjusted to meet a specific
application.
MGMC511MGMC32

Features
• Functionally compatible with the industry standard 8051
family.
• Several configurations to choose from; including PCA,
emulation-port and reduced-function options.
• Schematic-based, uses the ASIC Standard Library for
technology independence.

The basic MGMC51 contains four 8-bit parallel ports, two
external interrupt sources, three timer/counters, a serial
port, and power management. It is compatible with the
8052 .

• Fully Static Design, 0-40 MHz operation.
• Low Standby Current At Full Supply Voltage.
• 64 kilobytes of Data and Program Address Space.

MGMC51SDIMGMC32SD

• Boolean Processor and serial port.
• Access To Special Function Register Bus.

The MGMC51 SD removes the serial port
MGMC5111MGMC321

The MGMC51I takes an MGMC51 and adds an emulator
port. This port allows the end user to generate special
bond-out parts that can be used to create a professional
in-circuit emulator even though the ASIC pinout does not
match the original 8051 footprint.

LOGIC SYMBOL
MGMC51
Control
PORARST

Ports

ClKIN

P30-P37
P20-P27

ALE
EA

P10-P17
POO-P07

PSEN
MRESET
RESET
8-CLOCK

SFR Interface
SFAO-SFA6
SFDO-SFD7

MGMC51 FBIMGMC32FB

These two configurations add a programmable-counter
array, a watchdog timer, and an emulator port to the
MGMC51. They are compatible with the industry standard
8052FB.

ROM Interface
ROMAO-ROMA12
ROMDO-ROMD7

These configurations duplicate existing microcontrollers
and will meet the requirements of most applications.
However, the MGMC51 is not limited to just these
configurations. The internal SFR bus has been made
available to the designer. This allows the designer to place
their own application into the SFR address space where it
may be directly operated on by the 8051 instruction set.

RAM Interface
RAMDOO-RAMD07
RAMAO-RAMA7

SFRD

RAMDIO-RAMDI7

SFWR

RAWR

Description
AMI's MGMC51 ASIC microcontroller family is a set of 8bit microcontrollers that are functionally compatible with
the industry standard 8052 and 8052FB. All members of
the MGMC51 family are built around the same core
processor and use the same instruction set. They differ
only in the number and types of peripherals and whether
the bidirection pins are left as bidirectional or split into
input, output and control signals. The MGMC51
configurations have bidirectional pins and the MGMC32
configurations have had the bidirectional pins removed.
None of these controllers contain ROM or RAM, the user
should add any desired memory.

Since the MGMC51 microcontrollers are ASIC soft
Megacells in the ASIC Standard Library, they obtain their
AC and DC characteristics from the process that they are
manufactured in. This allows the end user to select both
the strengths of the output buffers and type of input buffer
desired for each pin. And by choosing the appropriate
process, it is possible to obtain low voltage operation at
supplies of 3 volts or less. The process also provides for
the maximum processor speed. A 40 MHz speed is
obtainable. And since the design is fully static, the clock
may be stopped at any time and in either state in order to
minimize power.

5-17

MGMC51 Family
I-Bil Core Microconlrollers

AMERICAN MICROSYSTEMS,INC.

Digital son Megaeells
Pin Description
SIGNAL

TYPE

P30-P37

10

Port 3

P20-P27

10

Port 2

P10-P17

10

Port 1

POO-P07

10

Port 0

SIGNAL DESCRIPTION

RESET

I

Reset. Resets to location 0 only.

PORARST

I

Initializes the Power On Reset.

MRESET

I

Master Reset.

EA

10

External Address. 10 used with some In Circuit Emulators.

ALE

10

Address latch Enable.ls an input for special modes during reset.

PSEN

10

Program Store Enable. Enables external ROM fetch. Is an input for special modes
during reset.

ClKIN

I

B-ClOCK

a
a

ROMAO-ROMA 12

Clock input.
Buffered Clock. Runs at half the XTAl21 frequency. Can clock synchronous
memories.
ROM Address Bus.

ROMDO-ROMD7

I

SFAO-SFA6

0

SFDO-SFD7

10

Special Function Data Bus.

SFRD

Special Function Write Strobe.

RAMDOO-RAMD07

a
a
a
a

RAMDI0-RAMDI7

I

Scratchpad RAM Data In Bus.

RAWR

0

Scratch pad RAM Write.

RARD

0

Scratch pad RAM Read.

SFWR
RAMAO-RAMA7

ROM Data Bus.
Special Function Register Address Bus.

Special Function Read Strobe.
Scratchpad RAM Address Bus.
Scratchpad RAM Data Out Bus.

Equivalent Gates (does not include ROM or RAM)
STANDARD CELL

GATE ARRAY

MGMC51SD

7,370

9,200

MGMC51

8,800

11,000

MGMC51I

9,200

11,700

MGMC51FB

11,720

14,750

5-18

MG1468C18
Real-Time Clock

AMERICAN MICROSYSTEMS,ING.

Digital son Megaeells
Features

Description

• A high-performance, low-power CMOS megacell

The MG1468C18 Real-Time Clock is a peripheral device
which may be used with various processors/computers. It
combines these features: a complete time-of-day clock
with alarm and one hundred year calendar; and a
programmable periodic interrupt and square wave
generator.

• Functionally compatible with the industry standard
146818
• Soft megacell technology allows customizing of function
• Uses the ASIC Standard Library for technology
independence
• 12- or 24-hour clock with a.m and p.m. mode
• Leap year and end-of-month recognition
• Programmable alarm

LOGIC SYMBOL
MG1468C18
AS
CEN
CKFS
ClK
OS
MOT
PS
RESETN
STBYN

ClKOUT
ENTXl
IRON

saw
RAMWE
RAMClK

The Real-Time Clock is designed for use as a battery
powered element, including all the common backed-up
functions such as RAM, time and calendar.
The megacell has been partitioned with battery backup
application in mind. For purposes of electrical isolation the
multiplexed address and data bus is split into input and
output sides. The split avoids any possible conduction
paths which result when the outputs of the tristate buffers
in a portion of the chip, which could be without power, are
connected to active or tristate outputs of powered circuits.
If not using battery backup, it is possible to configure the
megacell to appear to the rest of the ASIC as if the data
bus were bidirectional using ENTXL.
This megacell requires the use of an external 64-byte by 8bit RAM with outputs always enabled. This RAM, in the
correct process, can be ordered from the AM I Memory
group.

Soft Megacells

WRN

00(7:0)
RAMOO(7:0)

This soft megacell is in the ASIC Standard Library which is
technology- and process-independent and is available in
both Standard Cells and Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.
Contact the factory for more information.

5-19

MG1468C18
Real-Time Clock

AMERICAN MICROSYSTI:MS, INC.

Digital son Megaeells
Pin Description
SIGNAL

TYPE

ADI(7:0)

Input

Multiplexed bidirectional address and data bus. May be combined with the 00(7:0) bus
using the ENTXl signal.

SIGNAL DESCRIPTIONS

AS

Input

Address strobe. The falling edge of AS latches the address from the ADI bus.

CEN

Input

Chip enable, active low.

CKFS

Input

Selects the output frequency of ClKOUT. When CKFS=1, the frequency of ClKOUT will
equal ClK. When CKFS=O. the frequency of ClKOUT will equal ClK/4.
Time-base input for the time functions of the Real-Time Clock.

ClK

Input

ClKOUT

Output

Output at the time-base frequency divided by 1 or 4.

00(7:0)

Output

Data output bus. May be combined with the ADI(7:0) bus using the ENTXl signal.

DS

Input

Data Strobe. The OS signal is used with the WRN signal to latch write data from the ADI
bus and output data to the DO bus.

ENTXl

Output

Input/Output bus control. Used to create a multiplexed address/data bus external to the
RTC. When ENTXl = 0, this external bus should be put in output mode, indicating a read
cycle. If ENTXl = 1, the bus should be in a high-impedance state, allowing external drive.

IRON

Output

Interrupt request, active low. Signifies an interrupt condition is present.

MOT

Input

Allows selection between Motorola (MOT=1) and Intel (MOT=0) bus timing.

PS

Input

Power sense. Used to control the Valid RAM and Time bit in register D.

RAMClK

Output

RAMDI(7:0)

Input

RAMDO(7:0)

Output

RAM data coming out of the megacell.

RAMWE

Output

RAM write enable.

RAM clock. An output from the megacell used to clock timed RAMs.
RAM data into the megacell.

RESETN

Input

Megacell reset active low. Does not affect the clock, calendar or RAM functions.

STBYN

Input

Stand by, active low. Prevents access to the RTC.

SQW

Output

WRN

Input

Square wave output from one of the 15 taps provided by the 22 internal-divider stages.
Write enable, active low. Used with the OS pin to read and write data.

Equivalent Gates 1
STANDARD CEll

GATE ARRAY

2,000

2,500

1. Does not include RAM.

5-20

M16ClI50
DART

AMERICAN MICROSYSTEMS,INC.

Digital Soft Megaeells
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The M16C450 is a universal asynchronous receiver/
transmitter (UART) which is fully programmable by an 8-bit
CPU interface. It supports word lengths from five to eight
bits, an optional parity bit and one or two stop bits. If
enabled the parity can be odd, even or forced to a defined
state. A 16-bit programmable baud rate generator and an
8-bit scratch register are included. Eight modem control
lines and a diagnostic loop-back mode are provided.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• Programmable word length, stop bits and parity
• Programmable baud rate generator
• Interrupt generator

An interrupt can be generated from anyone of 10 sources.

• Loop-back mode

Transmission is initiated by writing the data to be sent to
the Transmitter Holding Register. The data will then be
transferred to the Transmit Shift Register together with a
start bit and parity and stop bits as determined by the Line
Control Register. The bits to be transmitted are then
clocked out of the transmit shift register by the transmit
clock (NBAUD) which comes from the baud rate generator.

• Scratch register
• Equivalent gates:
Standard Cell - 1,700; Gate Array - 2,250

LOGIC SYMBOL
M16C450

DlO-7
NCE
A2
A1
AO
NADS
NRD
NWR
ClK
MR
NTST
NDCD
NRI
NDSR
NCTS
RClK
SIN

If enabled, an interrupt will be generated when the
Transmitter Holding Register becomes empty.

DAO-7
NDVl
IRQ
NOUT2
NOUT1
NRTS
NDTR
NBAUD
SOUT

Data is clocked into the receiver by the receive clock
(RCLK). The receive clock should be 16 times the baud
rate of the received data. A filter is used to remove
spurious inputs which last for less than two periods of
RCLK. When the complete word has been clocked into the
receiver the data bits are transferred to the Receiver Buffer
Register to be read by the CPU. The receiver also checks
for a stop bit and for correct parity as determined by the
Line Control Register.
If enabled, an interrupt will be generated when the data
has been transferred to the Receiver Buffer Register.
Interrupts can also be generated for incorrect parity or a
missing stop bit (frame error).
The output modem control lines; NRTS, NDTR, NOUT1
and NOUT2 can be set or cleared by writing to the Modem
Control Register. The current status of the input modem
control line; NDCD, NRI, NDSR and NCTS can be read
from the Modem Status Register. Bit 2 of this register will
be set if the NRI modem status line has changed from low
to high since the register was last read.
If enabled, an interrupt will be generated when NDSR,
NCTS, NRI or NCO are asserted.
A per-use fee is associated with this megacell. Contact the
factory for more information.

5-21

M6"02
DART

AMERICAN MICROSYSTEMS, INC.

Digital son Megacells
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The M6402 is a full-duplex universal asynchronous
receiver/transmitter (UART). It supports word lengths from
five to eight bits, an optional parity bit and one or two stop
bits. It can detect overrun, parity and framing errors in the
received character.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• Programmable word length, stop bits and parity

The M6402 differs from the M8868A in that the master
reset clears the TRE output to "0" and does not initialize
the receive buffer.

• Double-buffered receiver and transmitter
• Overrun, parity and framing error detection

A per-use fee is associated with this megacell. Contact the
factory for more information.

• Equivalent gates:
Standard Cell - 580; Gate Array - 750

LOGIC SYMBOL
M6402

TBR1-8
NTBRL
PI
EPE
SBS
CLS1
CLS2
CRL
TRC
RRC
RRI
NDRR
MR
NTST

RBR1-8
DR
PE
OE
FE
TRE
TBRE
TRO

.

5-22

M61l15
CRT Controller

AMERICAN MICROSYSTEMS,INC.

Digital Soft Megacells
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The M6845 is a highly programmable controller designed
to generate the timing and control signals necessary to
meet a wide range of CRT (Cathode Ray Tube) based
video controllers. It is programmed by an 8-bit CPU
interface. It can address a character memory of up to 16K,
which can represent one or more pages of characters. It
can provide hardware scrolling through pages in multiple
page setups. The position and width of the horizontal and
vertical sync pulses are fully programmable, as is the size
location and blink rate of the cursor.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• Alphanumeric, semi-graphic and full-graphic capability
• Alphanumeric screen formats of up to 16K characters
• Programmable horizontal and vertical sync pulses
• Programmable cursor format and blink rate
• Light pen register
• Interlaced or non-interlaced scan modes
• Equivalent gates:
Standard Cell - 2,100; Gate Array - 2,700

LOGIC SYMBOL
M6845

010-7
NCS
RS
E
RNW
lPSTB
ClK
NRESET
NTST

ORO-7
NVOl
MAO-13
RAO-4
HSYNC
VSYNC
EOISP
ECURS

The horizontal counter is clocked by the ClK input and
counts from 0 up to the value stored in the Horizontal Total
register. The counter output is used by the horizontal sync
block to generate the HSYNC pulse, as defined by the
Horizontal Sync. Position and Sync. Width registers, and
by the display address generator block to produce the
character memory address.
The raster counter is incremented by the horizontal
counter and is used to count scan lines. The output is
available on the row address lines (RAO-4).
The vertical counter is incremented by the raster counter
and is used to count character lines. The output is used by
the vertical sync block to generate the VSYNC pulse, as
defined by the Vertical Sync. Position and Sync. Width
registers, and by the display address generator block to
produce the display memory address.
The frame counter is incremented by the vertical counter
and is used to count display frames. The output is used by
the cursor control block to blink the cursor at a rate
determined by register 10.
By using both the display memory address and the row
address an address space of 512K is available for use in
graphic displays.
Addresses are provided during retrace to provide refresh
for dynamic RAMs.
The light pen register will latch the display memory
address when the lPSTB line goes high.
A per-use fee is associated with this megacell. Contact the
factory for more information.

5-23

M765A
Floppy Disk Controller

AMERICAN MICROSYSTEMS,ING.

Digital son Megacells
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The M765A is a floppy disk controller which also supports
tape drives. This microcode-free design is compatible with
industry standard discrete devices. It supports IBM
System 3740 (FM), IBM System 34 (MFM), Perpendicular
500K BPS and Perpendicular 1M BPS formats. It supports
4 Mb floppy drives and is capable of data rates up to 1.25
Mbps. It provides drive select and motor signals, and
supports drives with tunnel erase heads. It has
programmable write precompensation and a 16 byte data
FIFO. It can directly address 256 tracks and has the ability
to access an unlimited number. The recalibrate command
can step 255 tracks.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• IBM System 3740 format
• IBM System 34 format Perpendicular recording format
Data rates up to 1.25 Mbps
• Directly addresses 256 tracks
• 255 step recalibrate command
• Programmable write precompensation
• 16 byte FIFO
• Equivalent gates:
Standard Cell - 7,100; Gate Array - 9,300

The M765A can be connected to a M91C360, or similar,
data separator to form a complete floppy disk controller.
A per-use fee is associated with this megacell. Contact the
factory for more information.

LOGIC SYMBOL
M765A
OB10-7
NCS
NWR
NRD
AO
NDACK
TC
RDAT
WND
INDEX
FlT
TRKO
WRP
TSD
RDY
DRV1
DRVO
MBDR
WClK
ClK

OBOO-7
NOBO
DRO
IRO
SYNC
DS3
DS2
DS1
DSO
STP
DIR
WE
PS1
PSO
WDAT
SIDE
HDlD
FLTR
TG43
MFM
IDLE

RSET

APD

PRES

MDl

NSlM
NSM
NTEST

FTR

5-24

-----~----------------------------------

M8251 A

Serial Communication Interlace

AMERICAN MICROSYSTEMS, INC

Digital Sofl Megaeells
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The M8251 A is a universal synchronous/asynchronous
receiver/transmitter (USART) communications interface. It
supports asynchronous communications with five to eight
data bits, parity and one, one and a half, or two stop bits. It
can provide automatic break detection. It supports
synchronous communications with one or two SYNC
characters, with internal or external SYNC detection. Both
the transmit and receive data paths are double buffered. It
has four modem control lines.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• Synchronous and asynchronous operation
• Full duplex, double buffered transmitter and receiver
• Internal or external character synchronization
• 1X, 16X and 64X clock modes
• Framing, parity and overrun error detection
• Equivalent gates:
Standard Cell - 1,500; Gate Array - 2,000

LOGIC SYMBOL
M8251 A
100-7

NCS
CND
NRD
NWR
ClK
TXC
RXC
NDSR
NCTS
ISDET
RXD
RES
NTST

DAO-7
DAC

OSDET
DSDET
NRTS
NDTR
TXD
TXE
TXRDY
RXRDY
T64

The M8251A is fully programmable by an 8-bit CPU
interface.
The operating mode of the M8251 A is programmed by
writing to the mode control registers and SYNC registers,
using the 8-bit CPU interface. Transmission can then begin
by writing to the transmit buffer. Data is clocked out of the
transmitter by the transmit clock (TXC), which can be 1, 16
or 64 times the baud rate. The data stream is clocked into
the receiver by the receive clock (RXC), which can be 1, 16
or 64 times the baud rate. In synchronous mode character
reception will not begin until the SYNC character, or
characters, are detected. When each character has been
received it is transferred to the receive buffer to be read by
the CPU interface.
The M8251A has output signals to indicate when the
transmit buffer is empty (TXRDY), when the receive buffer
is full (RXRDY) and when the SYNC characters have been
detected (OSDET, DSDET). Two input (NDSR, NCTS) and
two output (NRTS, NDTR) modem control signals are also
provided. A further input (ISDET) is provided for use with
an external SYNC detector.
A per-use fee is associated with this megacell. Contact the
factory for more information.

5-25

M8253

Programmable Interval Timer

AMERICAN MICROSYSTEMS.INC.

Digital son Megaeells
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The M8253 contains three independent 16-bit timer/
counters that can be programmed over a common 8-bit
CPU interface. It can be used for timing external events,
producing fixed delays or producing repetitive waveforms.
The current value of each of the counters can be latched
and read back over the CPU interface.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• Three independent 16-bit counters
• Binary or BCD counting

A per-use fee is associated with this megacell. Contact the
factory for more information.

• Six counter modes
• Equivalent gates:
Standard Cell - 2,500; Gate Array - 3,250

LOGIC SYMBOL
M8253
IDO-7
AO
A1
NCS
NWR
NRD
CLKO
GATEO
CLK1

DAOO-7
NOD
aUTO
OUT1
OUT2

GATE1
CLK2
GATE2
NTM

5-26

M82530

Serial Communications Controller

AMERICAN MICROSYSTEMS, INC.

Digital son MegaeeUs
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The M82530 serial communications controller has two
independent full-duplex channels which support
asynchronous, bit synchronous (SDLC, HOLC and SOLC
loop mode) and byte synchronous (MONOSYNC,
BISYNC) communication modes. NRZ, NRZI and FM
data encoding/decoding are supported. The M82530
includes a baud rate generator and a digital phase-locked
loop for each channel. Two diagnostic modes: local
loopback and automatic echo are available. The M82530
is fully programmable by an 8-bit system interface, which
includes a six source interrupt controller. The interrupt
controller has external signals that allow it to be daisychained with other interrupt controllers.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• Asynchronous and synchronous modes
• MONOSYNC, BISYNC and SOLC supported
• SOLC loop-mode supported
• NRZ, NRZI and FM encoding/decoding
• Two independent full-duplex channels
• Oigital phase-locked loop for each channel
• Baud rate generator for each channel
• Local loop-back and automatic echo modes
• Equivalent gates:
Standard Cell - 9,400; Gate Array - 12,200

LOGIC SYMBOL
M82530
010-7
ClK
NCS
ONC
ANB
NWR
NRO
NINTA
lEI
NSYAI
TRCAI
RTCA
ROA
NCOA
NCTSA
NSYBI
TRCBI
RTCB
ROB
NCOB
NCTSB
NRST
NTST

OAO-7
NOOE
NROQA
NROQB
NINT
lEO
NSYAO
NSYAE
TRCAO
NTCAE
TDA
NOTRA
NRTSA
NSYBO
NSYBE
TRCBO
NTCBE
TOB
NOTRB
NRTSB

------

Each of the two identical channels in the M82530 contain
a transmitter, a receiver, a baud rate generator, a digital
phase-locked loop and a clock selector. The clock selector
provides the clocks for the transmitter and the receiver
blocks. The clocks can be programmed to come from one
of two external clocks, from the baud rate generator, or
derived from the receiver data stream by the phase-locked
loop. In addition to the two serial communication channels
there is a common 8-bit system interface and a six source
interrupt controller.
The transmitter has a transmit shift register into which data
to be transmitted is loaded. This data is loaded from the
transmit buffer, sync characters and flags are loaded
automatically from the sync registers. In SOLC mode a
zero insertion block will insert zeros into long strings of
ones. A CRC generator produces a CRC check word for
appending to message blocks. The output data stream
then passes to a data encoder block which can produce
NRZ, NRZI or FM encoded formats. The final output
selector allows the output to come from the receiver in
diagnostic or loop modes.
The receiver input selector allows the received data
stream to come from the transmitter in diagnostic modes
or through a 1-bit delay, which is required in SOLC loop
mode. The input stream then passes to a decoder to
convert it into NRZ format. The data stream then goes into
the receive data shift register. The receive data shift
register can be extended to 16-bits for detecting 16-bit
sync characters, and can automatically delete the extra
zeros that were inserted into the data stream in SOLC
mode. A CRC checker can be used in synchronous
modes. The received data characters are transfered to the
receive data FIFO and parity, frame or CRC errors are
transfered to the receive error FIFO.
A per-use fee is associated with this megacell. Contact the
factory for more information.

5-27

MG82C37A
Programmable DMA Controller

AMERICAN MICROSYSTEMS, INC.

Digital Soft Megacells
Features

The MG82C37A is designed to improve system
performance by allowing external devices to transfer data
directly with system memory. High speed and very lowpower consumption make it an ideal component for
aerospace and defense applications. The low-power
consumption also makes it an attractive addition in
portable systems or systems with low-power standby
modes.

• A high-performance, low-power CMOS megacell
featuring functional compatibility with the industry
standard 8237/8237A
• Soft megacell technology allows customizing of function
• Uses the ASIC Standard Library for technology
independence

The MG82C37A DMA controller is a state-driven address
and control signal generator designed to accelerate data
transfer in systems by moving data from an 1/0 device to
memory, or memory to an 1/0 device. Data transfers are
direct, rather than being stored enroute in a temporary
register.

• Compatible with 8080/85, 8086/88, 80286/386 and
68000 j..tP families
• Four independent maskable DMA channels with
autoinitialize capability
• Memory-to-memory transfer
• Fixed or rotating DMA request priority
• Independent polarity control for DREQ and DACK signals
• Address increment or decrement selection
• Cascadable to any number of channels

LOGIC SYMBOL

The organization of the MG82C37A is composed of three
logic blocks, a series of internal registers and a counter
section. The logic blocks include the Timing Control,
Command Control and Priority Encoder circuits.

MG82C37A
EOPIN

EOPON
EOPEN

IORIN
IOWIN

IORON
IOWON
IOEN

CSN
ClK

ADSTB
AE

READY

MEMRN

RESET

MEMWN
HRQ

HlDA
DREQ(3:0)

The MG82C37A also mediates memory-to-memory block
transfers and will move data from a single location to a
memory block. Temporary storage of data is required, but
the transfer rate is significantly faster than CPU processes.
The device provides operating modes to carry out both
single byte and block transfers of data.

The Timing Control block generates internal timing signals
from the clock input and produces external control signals.
Command Control decodes incoming instructions from the
CPU, and the Priority Encoder block regulates DMA
channel priority.
The internal registers hold internal states and instructions
from the CPU. Addresses and word counts are computed
in the counter section.

DACK(3:0)

Soft Megacells
This soft megacell is in the ASIC Standard Library which is
technology- and process-independent and is available in
both Standard Cells and Gate Arrays.

Description
The MG82C37A is a high-performance, programmable
Direct Memory Access (DMA) controller offering functional
compatibility with the industry standard 8237/8237A. It
features
four
channels,
each
independently
programmable, and is cascadable to any number of
channels. Each channel can be programmed to
autoinitialize following DMA termination.

A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.
Contact the factory for more information.

In addition, the MG82C37A supports both memory-tomemory transfer capability and memory block initialization,
as well as a programmable transfer mode.
5-28

MG82C37A
Programmable DMA Controller

AMERICAN MICROSYSTEMS,INC.

Digital Soft Megacells
Pin Description
SIGNAL DESCRIPTIONS

SIGNAL

TYPE

AI(3:0)

I

AO(3:0)

0

low output address bus. During active Cycle, lower 4 bits of the transfer address.
Control line used to determine when AO(3:0) and A(7:4) is valid. Active low.

Input address bus. During Idle Cycle, addresses which control register to be loaded or read.

AEN

0

A(7:4)

0

High Address Bus. During active Cycle, upper 4 bits of the transfer address.

ADSTB

0

Address Strobe. Controls latching of the upper address byte.
Address Enable. Enables the higher order address byte onto the system address bus.

AE

0

ClK

I

Clock Input. May be stopped for standby operation.

CSN

I

Chip Select, active low.

DACK(3:0)

0

DBI(7:0)

I

DBO(7:0)

0

Data Bus output ports.

DEN

0

Control line, active low. Used to determine when DBO(7:0) is valid.

DREQ(3:0)

I

DMA Request. DMA service is requested by activation of the channel from a specific device.

EOPIN

I

End of Process, active low. Force termination of DMA.

EOPON

0

Indicates when DMA is finished.

EOPEN

0

Control line used to determine when EOPON is valid. Active low.

HlDA

I

HRQ

0

Hold Request. Requests control of the system buses. HRQ is issued following a request for
DMA service (DREQ) from a peripheral, and is acknowledged by the HLDA Signal.

10RIN
10RON

I
0

1/0 Read, active low. Idle Cycle: CPU input control signal for reading the Control Registers.
Active Cycle: Output control signal to read data from a peripheral device during a DMA cycle.

10WIN
10WON

I
0

1/0 Write, active low. Idle Cycle: CPU input control signal for loading the control registers.
Active Cycle: Output control signal to load data to a peripheral device during a DMA cycle.

10EN

0

Control line active low. Indicates when 10RON, 10WON, MEMRN and MEMWN are valid.

MEMRN

0

Memory Read, active low. MG82C37A reads data from a selected memory address during a
DMA Read or Memory-to-Memory transfer. Valid when 10EN is low.

MEMWN

0

Memory Write, active low. MG82C37A writes data to a selected memory address during a
DMA Write or Memory-to-Memory transfer. Valid when 10EN is low.

READY

I

Extends the Memory Read and Write pulse widths to accommodate slow I/O peripherals.

RESET

I

Reset. Asynchronous signal clears internal registers and puts the MG82C37A in Idle Cycle.

DMA Acknowledge. Informs a peripheral that the requested DMA transfer has been granted.
Data Bus input ports.

Hold Acknowledge. Indicates the CPU has released control of the system buses.

Equivalent Gates
STANDARD CEll

GATE ARRAY

3,000

3,800

5-29

MG82C50A
Async. Communication Element

AMERICAN MICROSYSTEMS,ING.

Digital son Megacells
Features

Description

• A high-performance, low-power CMOS megacell
featuring functional compatibility with the industry
standard 8250

The MG82C50A Asynchronous Communications Element
(ACE) is a high-performance programmable Universal
Asynchronous ReceiverlTransmitter (UART) and Baud
Rate Generator (BRG) on a single megacell. The device
supports data rate from DC to 625K baud (0-10MHz
clock). It is functionally compatible with the industry
standard 8250.

• Soft megacell technology allows customizing of function
• Uses the ASIC Standard Library for technology
independence
• Single megacell UART/BRG
• On chip baud rate generator 1 to 65535 Divisor
generates the BAUDOUTN (16x) clock
• Prioritized interrupt mode
• Microprocessor bus oriented interface
• Modem interface
• Line break generation and detection
• Loopback mode
• Double buffered transmitter and receiver

LOGIC SYMBOL
MG82C50

csa
CS1
CS2N
ADSN
MR
RDN
WRN
ClKIN
RClK
CTSN
DSRN
DCDN
RIN

The ACE receiver circuitry converts start, data, stop and
parity bits into a parallel data word. The transmitter
circuitry converts a parallel data word into serial form and
appends the start, parity and stop bits. The word length is
programmable to 5, 6, 7 or 8 data bits. Stop bit selection
provides a choice of 1, 1.5 or 2 stop bits .
The Baud Rate Generator divides the clock frequency by a
divisor programmable from 1 to 216_1 to provide standard
RS-232C baud rates. The BAUDOUT programmable clock
output provides a buffered oscillator or a 16x (16 times the
data rate) baud rate clock for general purpose system use.
To meet the system requirements of a CPU interfacing to
an asynchronous channel, the modem control signals
RTSN, CTSN, DSRN, RIN, DCDN are provided.

Soft Megacells
DDIS
CSOUT
BAUDOUTN
RTSN
DTRN
INTRPT

This soft megacell is in the ASIC Standard Library which is
technology- and process-independent and is available in
both Standard Cells and Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.
Contact the factory for more information.

5-30

AMERICAN MICROSYSTEMS, INC.

MG82C50A
Async. Communication Element
Digital Soft Megaeells

Pin Description
SIGNAL

TYPE

SIGNAL DESCRIPTIONS

RON

I

Read, active low. Causes the register selected by A(2:0) to be output to 0(7:0).

WRN

I

Write, active low. Causes data from the data bus 0(7:0) to be input to the MG82C50A.

01(7:0)
00(7:0)

I
0

Data Bus inputs and outputs, 01(0) and 00(0) are the lSBs.

DEN

0

Control line used to determine when 00(7:0) is valid. Active low.

A(2:0)

I

Register Select. Selects the internal registers during CPU bus operations. A(O) is the lSB.

ClKIN

I

Clock in. Clock connection for the internal Baud Rate Generator.

SOUT

0

Serial Data Output. Serial data output from the MG82C50A transmitter circuitry.

CTSN

I

Clear to Send, active low. Indicates that data on SOUT can be transmitted.

DSRN

I

DTRN

0

Data Terminal Ready, active low. Indicates to that the MG82C50A is ready to receive data.

Data Set Ready, active low. Indicates the modem is ready to exchange data.

RTSN

0

Request to Send, active low. Indicates data is ready to transmit. In half duplex operations, RTS is
used to control the direction of the line.

BAUDOUTN

0

Baud out clock. Rate is the ClKIN frequency divided by the specified divisor in the BSR.

OUT1 N,OUT2N

0

Outputs 1and 2, active low. Asserted by setting MCR(2,3) high. Inactive during loop mode.

RIN

I

Ring Indicator, active low. Indicates that a telephone ringing signal has been received by the modem
or data set.

DCDN

I

Data Carrier Detect, active low. Indicates that the data carrier has been detected by the modem or
dataset.

MR

I

Master Reset. Forces the MG82C50A into an idle mode.

INTRPT

0

Interrupt Request. Goes active when an interrupt has occurred if enabled by the IER.

SIN

I

Serial Data Input. Serial data input from the communication line or modem to the MG82C50A
receiver circuits. Disabled when operating in the loop mode.

CSO,CS1,CS2N

I

Chip Selects. Enables WRN and RON. Latched by the ADSN input.

CSOUT

0

Chip Select Out. Indicates the megacell has been selected by active CSO, CS1 and CS2N.

DDIS

0

Driver Disable. Used to disable an external transceiver when the CPU is reading data.

ADSN

I

Address Strobe, active low. Latches A(2:0) and CSO, CS1 and CS2N inputs.

RClK

I

Baud Rate Clock. This input is the 16x Baud Rate Clock for the receiver section of the MG82C50A.
This input may be provided from the BAUDOUT output or an external clock.

Equivalent Gates
STANDARD CELL

GATEARRRAY

2,000

2,500

5-31

MG82C54

Programmable Interval Timer

AMERICAN MICROSYSTEMS, INC.

Digital Solt Megaeells
Major functional blocks include read/write logic, control
word register, and three programmable counters.

Features
• A high-performance, low-power megacell featuring
functional compatibility with the industry standard 8254

The read/write logic block generates internal control
signals for the different functional blocks using address
and control information obtained from the system. The
active LOW signals, CSN, RON and WRN are used to
select the MG82C54 for operation, read a counter, and
write to a counter (or the control word register)
respectively. CSN must be LOW for RON or WRN to be
recognized .

• Soft megacell technology allows customizing of function
• Uses the ASIC Standard Library for technology
independence
• Available in several AMI process technologies
• Three independent 16-Bit counters
• Six programmable counter modes

The inputs AO and A 1are used to select the control word
register, or one of the three counters that is to be written to
or read from. AO and A 1 connect directly to the
corresponding signals of the microprocessor address bus,
while CS is derived from the address bus using either a
linear select method, or an address decoder device.
The MG82C54 has a control word register which is a write
only register. It is selected by the read/write logic block
when AO and A 1=1. When CSN and WRN are LOW, data
are written into the MG82C54 control word register.
Control word data are interpreted as a number of different
commands which are used to program the various device
functions. For example, status information is available with
the Read-Back Command.

• Status read-back command
• Binary or BCD counting

LOGIC SYMBOL
MG82C54
RON
WRN
AO
A1
CSN
CLKO
GATEO

OUTO

CLK1
GATE 1

OUT1

CLK2
GATE2

OUT2

01(7:0)

The MG82C54 contains three identical, independent
counter blocks. Each counter provides the same functions,
but can be programmed to operate in different modes
relative to each other. A typical counter contains the
following functional elements: control logic, counter, output
latches, count registers and status register.
The low-power consumption of the MG82C54 makes it
ideally suited to portable systems or those with low-power
standby modes.

00(7:0)

OEN

Soft Megacells

Description
The MG82C54 is a counter/timer megacell that includes
complete functional compatibility with the industry
standard 8254. Designed for fast operation, it has three
independently programmable 16-bit counters and six
programmable counter modes. Counting can be
performed in both binary and BCD formats. Speed will
depend on what AMI process technology is chosen.
The MG82C54 offers a very flexible, hardware solution to
the generation of accurate time delays in microprocessor
systems. A general purpose, multi-timing element, it can
be used to implement event counters, elapsed time
indicators, waveform generators plus a host of other
functions.

This soft megacell is in the ASIC Standard Library which is
technology- and process-independent and is available in
both Standard Cells and Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.
Contact the factory for more information.

5-32

MG82C54

Programmable Interval Timer

AMERICAN MICROSYSTEMS, INC.

Digital Soft Megaeells
Pin Description
SIGNAL
A1,AO

TYPE

SIGNAL DESCRIPTIONS

I

Address. Used to select the Control Word Register (for read or write operations), or one of
the three Counters. Normally connected to the system address bus.

CLKO

I

Clock input of counter O.

CLK1

I

Clock input of counter 1.

CLK2

I

Clock input of counter 2.

CSN

I

Chip select, active low. Enables the MG82C54 to respond to RON and WRN signals.

01(7:0)

I

00(7:0)

0

Input data bus.
Output data bus.

OEN

0

GATEO

I

Gate input of counter O.

GATE1

I

Gate input of counter 1.

GATE2

I

Gate input of counter 2.

OUTO

0

Output of counter O.

OUT1

0

Output of counter 1.

OUT2

0

Output of counter 2.

RON

I

Read Control, active low. Used to enable the MG82C54 for read operations by the CPU.

WRN

I

Write Control, active low. Used to enable the MG82C54 to be written to by the CPU.

Output enable, active low. Output is low when valid output data is on 00 bus.

Equivalent Gates
STANDARD CELL

GATE ARRAY

2,150

2,800

5-33

MG82C55A

Programmable Peripherallnlerlace

AMERICAN MICROSYSTEMS.INC.

Digital son Megaeells
Features

Description

• A high-performance, low-power CMOS megacell
featuring functional compatibility with the industry
standard 8255A

The MG82C55A Programmable Peripheral Interface is a
high speed, low power CMOS megacell offering functional
compatibility with the industry standard 8255A. It is a
general purpose 1/0 component which interfaces
peripheral equipment to the microcomputer system bus
usually without extra logic.

• Soft megacell technology allows customizing of function
• Uses the ASIC Standard Library for technology
independence
• Supports 8086/8088 and 80186/188 microprocessors
• 24 programmable liD pins
• Direct bit set/reset capability
• Bidirectional bus operation
• Enhanced control word read capability

LOGIC SYMBOL
MG82C55A

AD
A1

The MG82C55A has 24 1/0 lines grouped as three 8-bit
ports (A,B and C), in two control groups (A and B). Group
A consists of port A and port C upper (7:4), while group B
consists of port B and port Clower (3:0). Group A has
three operating modes, (0,1,2) while group B has two
(0,1). The operating modes are:
Mode 0: One 8-bit and one 4-bit uni-directional port,
without handshaking.
Mode 1: One 8-bit uni-directional port with handshaking.
Mode 2: One 8-bit bi-directional port with handshaking.
For any modes other than mode 0, lines from port Care
used as handshaking lines for ports A and B. Port A has
latched inputs and latched outputs while ports Band C
have unlatched inputs and latched outputs.
The system CPU has full access to the MG82C55A's
control register which completely controls the megacell's
configuration. When the control word register is read bit 07
will always be a logic ONE to indicate control word mode
information.

Soft Megacells
This soft megacell is in the ASIC Standard Library which is
technology- and process-independent and is available in
both Standard Cells and Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.
Contact the factory for more information.

5-34

~II~

AMERICAN MICROSYSTEMS.INC.

MG82C55A

Programmable Peripherallnlerlace
Digital son Megacells

Pin Description
SIGNAL

TYPE

SIGNAL DESCRIPTIONS

A1,AO

I

Address. These input signals, in conjunction with RON and WRN, control the selection of
one of the three ports or the control word registers.

CSN

I

Chip Select, active low. Enables the MG82C55A to respond to RON and WRN signals.
RON and WRN are ignored otherwise.

01(7:0)
00(7:0)

I

Oata Bus.

0

OEN

0

PAI(7:0)
PAO(7:0)

0

I

Control line, active low. Used to determine when OBO(7:0) is valid.
Port A. An 8-bit data output latch and an 8-bit data input buffer.

PAEN

0

PBI(7:0)
PBO(7:0)

I

0

PBEN

0

PCI(3:0)
PCO(3:0)

I

0

PCI(7:4)
PCO(7:4)

0

PCEN(7:1)

0

Control line, active low. Used to determine when PCO(7:0) is valid. PCEN(1) controls
PCO(1 :0).

RESET

I

Reset. A high on this input clears the control register and all ports are set to the input
mode.

RON

I

Read Control, active low. This input is low during CPU read operations.

WRN

I

Write Control, active low. This input is low during CPU write operations.

I

Control line, active low. Used to determine when PAO(7:0) is valid.
Port B. An 8-bit data output latch and an 8-bit data input buffer.
Control line, active low. Used to determine when PBO(7:0) is valid.
Port C, Pins (3:0). Lower nibble of an 8-bit data output latch and an 8-bit data input buffer
(no latch for input). This port can be divided into two 4-bit ports under the mode control.
Each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and
status signal inputs in conjunction with ports A and B.
Port C, Pins(7:4). Upper nibble of Port C.

Equivalent Gates
STANDARD CEll

GATE ARRAY

700

900

5-35

MG82C59A

Programmable Interrupt Controller

AMERICAN MICROSYSTEMS, INC.

Digital Soft Megaeells
Features

• Issuing an interrupt to the CPU

• A high-performance, low-power megacell featuring
functional compatibility with the industry standard 82591
8259A

• Then providing the CPU with the interrupt service routine
address of the interrupting peripheral
Each peripheral device usually has a specific interrupt
service routine which is particular to its operational or
functional requirements within the system. The
MG82C59A can be programmed to hold a pointer to the
service routine addresses associated with each of the
peripheral devices under its control. Thus when a
peripheral interrupt is passed through to the CPU, the
MG82C59A can set the CPU Program Counter to the
interrupt service routine required. These pointers (or
vectors) are addresses in a vector table.

• Soft megacell technology allows customizing of function
• Uses the ASIC Standard Library for technology
independence
• Eight level priority controller
• Expandable to 64 levels
• Programmable interrupt modes, with each interrupt
maskable
• Edge- or level-triggered interrupt request inputs
• Polling operation

The MG82C59A is intended to run in one of two major
operational modes, according to the type of CPU being
used in the system. The CALL Mode is used for 8085 type
microprocessor systems, while the VECTOR Mode is
reserved for those systems using more sophisticated
processors such as the 8088/86, 80286/386 or 68000
family.

LOGIC SYMBOL
MG82C59A
SPENI
RDN
WRN

AD

SPENO 0 - SPENEN 0 - -

In either mode, the MG82C59A can manage up to eight
interrupt request levels individually, with a maximum
capability of up to 64 interrupt request levels when
cascaded with other MG82C59As. A selection of priority
modes is also available such that interrupt requests can be
processed in a number of different ways to meet the
requirements of a variety of system configurations.

INT

CSN
INTAN

Priority modes can be changed or reconfigured
dynamically at any time during system operation using the
operation command words (OCWs), allowing the overall
interrupt structure to be defined for a complete system.
Note that the MG82C59A is programmed by the system
software as an 1/0 peripheral.

DE

Description
The MG82C59A is a high-performance, completely
programmable interrupt controller. It can process eight
interrupt request inputs, assigning a priority level to each
one, and is cascadable up to 64 interrupt requests.
Individual interrupting sources are maskable. Its two
modes of operation (Call and Vector) allow it to be used
with virtually all 8000 and 80000 type processors, as well
as with 68000 family microprocessors.
Acting as an overall peripherals manager, its functions
include:
• Accepting interrupt requests from assorted peripheral
devices
• Determining which is the highest priority
• Establishing whether or not the new interrupt is of a
higher priority than any interrupts which might be
currently being serviced, and if so,

The MG82C59A's high-performance and very low-power
consumption makes it useful in portable systems and
systems with low-power standby modes.

Soft Megacells
This soft megacell is in the ASIC Standard Library which is
technology- and process-independent and is available in
both Standard Cells and Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.
Contact the factory for more information.

5-36

MG82C59A

AMERICAN MICROSYSTEMS, INC.

Programmable Interrupt Controller
Digital son Megaeells

Pin Description
SIGNAL

TYPE

SIGNAL DESCRIPTIONS

AO

I

AO Address Line. Acts in conjunction with the CSN, WRN and RON signals. It is used to
decipher various command words written by the CPU, and Status information read by the
CPU. It is typically connected to the CPU - AO address line.

CSN

I

Chip Select, active low. Used to enable RON and WRN communication between the CPU
and the MG82C59A. Note that INTAN functions are independent of CSN.

INTAN

I

Interrupt Acknowledge. Signal used to enable the MG82C59A interrupt vector data onto
the data bus by a sequence of interrupt acknowledge pulses issued by the CPU.

WRN

I

Write, active low. Used to enable the MG82C59A to accept command words from the
CPU, when CSN is LOW.

RON

I

Read, active low. Used to enable the MG82C59A to output status information onto the
data bus for the CPU, when CS is LOW.

IR(7:0)

I

Interrupt Requests. Asynchronous input signals, an interrupt request is executed by
raising an IR input, and holding it HIGH until it is acknowledged (Edge Triggered Mode), or
just by a HIGH level on an IR input (Level Triggered Mode).

CASI(2:0)
CASO(2:0)

I

0

CASEN

0

SPENI
SPENO

I

0

SPENEN

0

Control line used to determine when SPENO is valid. Active low.

01(7:0)
00(7:0)

I
0

Data Bus. 8-Bit data bus for the transfer of control, status and interrupt vector information.

DE

0

Control line used to determine when 00(7:0) is valid. Active high.

INT

0

Interrupt. This signal goes HIGH when a valid interrupt request is asserted.

Cascade Lines. The CAS lines are used as a private bus by a MG82C59A master
to control multiple MG82C59A slaves. The master uses only CASO(2:0).
The slaves use CASI(2:0).
Control line used to determine when CASO(2:0) is valid. Active low.
Slave Program/Enable Buffer. Dual function control signal. When in the
Buffered Mode, SPENO is used to control buffer transceivers.
When not in the Buffered Mode, SPENI is used to designate
a master (SP = 1) or a slave (SP = 0).

Equivalent Gates
STANDARD CEll

GATE ARRAY

1,450

2,000

5-37

M8490
SCSI Controller

AMERICAN MICROSYSTEMS,INC.

Digital Soft Megaeells
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The M8490 is a Small Computer Systems Interface (SCSI)
It
can
control
8-bit
asynchronous
controller.
communication over an ANSI SCSI-II bus. It has an 8-bit
CPU interface through which the local processor can
program it to act as initiator or target on the SCSI bus, and
can control all phases of data transfers by writing to
command registers within the M8490.lt can generate up to
9 separate interrupts to signal to the local processor when
commands have been completed or errors have occurred.
Bus clear, free and settle delays, and optionally arbitration
delays, can be generated automatically from an external
clock. Signals are provided to allow data to be transferred
to, and from, the M8490 by DMA.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• Compatible with ANSI SCSI-II
• Initiator or target mode
• Provides arbitration and bus clear/free/settle delays
• Enhanced arbitration mode
• Generates 9 separate interrupts
• Compatible with 5380 SCSI controller
• Equivalent gates:
Standard Cell - 1,200; Gate Array - 1,500

LOGIC SYMBOL
M8490
IOSO-7
10SP
lACK
IATN
IBSY
ICNO
IINO
IMSG
IREO
IRST
ISEl
IOAO-7
10AP
AOO-2
NCS
NWR
NRO
NOCK
NEOP
NRES
ClK

00SO-7
OOSP
OACK
OATN
OBSY
OCNO
OINO
OMSG
OREO
ORST
OSEl
00AO-7
OOAP
NOAC
NOAP
ORO
ROY
IRO

The M8490 is 5380 compatible, applications currently
using the 5380 controller should be able to use the M8490
with out software changes. The M8490 has additional
features not found in the 5380 making it more attractive for
new designs, these additional features are:- CPU parity,
programmable CPU and SCSI parity, loop back mode,
enhanced arbitration and interrupt support.
The CPU interface block provides an 8-bit interface to the
twelve internal registers that control the M8490. The
registers control the operation of the SCSI bus controller,
the DMA controller and the interrupt controller. The data
transferred over the SCSI bus is also written and read by
the CPU interface.
The DMA controller block provides an alternative means of
writing data to the Output Data register, or reading data
from the Input Data Register. When DMA is enabled the
M8490 requests a DMA cycle by asserting ORO high.
When the request is acknowledged by asserting NOACK
low then reads or writes will be directed to the IDS or ODS
register respectively. A DMA transfer is terminated by
asserting NEap low during the last DMA transfer.
The interrupt controller can generate interrupts to Signal
the completion of a DMA transfer, the completion of
arbitration, the selection of the M8490 or an error
condition. The source of the interrupt can be found by
reading the RPI register.
The SCSI controller block provides access to the SCSI
bus. Internal timers are used to provide bus free, bus clear
and bus settle delays, and to time the arbitration period.
A per-use fee is associated with this megacell. Contact the
factory for more information.

5-38

M85C30

Serial Communications Controller

AMERICAN MICROSYSTEMS.ING.

Digital Soft Megaeells
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The M85C30 serial communications controller has two
channels which
support
independent full-duplex
asynchronous, bit synchronous (SDLC, HOLC and SOLC
loop mode) and byte synchronous (MONOSYNC,
BISYNC) communication modes. NRZ, NRZI and FM data
encoding/decoding are supported.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• Asynchronous and synchronous modes
• MONOSYNC, BISYNC and SOLC supported
• SOLC loop-mode supported
• NRZ, NRZI and FM encoding/decoding
• Two independent full-duplex channels
• Digital phase-locked loop for each channel
• Baud rate generator for each channel
• Local loop-back and automatic echo modes
• SOLC Frame counter and status FIFO
• Equivalent gates:
Standard Cell - 12,700; Gate Array - 16,500

It includes a baud rate generator and a digital phaselocked loop for each channel. Two diagnostic modes: local
loopback and automatic echo are available. A character
counter and a 10 X 19-bit frame status FIFO are available
in SOLC mode.
The M85C30 is fully programmable by an 8-bit system
interface, which includes a six source interrupt controller.
The interrupt controller has external signals that allow it to
be daisy-chained with other interrupt controllers.
A per-use fee is associated with this megacell. Contact the
factory for more information.

LOGIC SYMBOL
M85C30

D10-7
ClK
NCS
DNC
ANB
NWR
NRD
NINTA
lEI
NSYAI
TRCAI
RTCA
RDA
NCDA
NCTSA
NSYBI
TRCBI
RTCB
RDB
NCDB
NCTSB
NRST
NTST

DAO-7
NDOE
NRDQA
NRDQB
NINT
lEO
NSYAO
NSYAE
TRCAO
NTCAE
TDA
NDTRA
NRTSA
NSYBO
NSYBE
TRCBO
NTCBE
TDB
NDTRB
NRTSB

5-39

M8868A
DART

AMERICAN MICROSYSTEMS,INC.

Digital son Megaeells
Features

Description

• AMI's implementation of 3Soft's MegaMacro@

The M8868A is a full-duplex universal asynchronous
receiver/transmitter (UART). It supports word lengths from
five to eight bits, an optional parity bit and one or two stop
bits. It can detect overrun, parity and framing errors in the
received character.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• Programmable word length, stop bits and parity
• Double-buffered receiver and transmitter
• Overrun, parity and framing error detection
• Equivalent gates:
Standard Cell - 600; Gate Array - 760

The M8868A differs from the M6402 in that the master
reset sets the TRE output to "1" and clears the receive
buffer.
A per-use fee is associated with this megacell. Contact the
factory for more information.

LOGIC SYMBOL
M8868A

TBR1-8
NTBRL
PI
EPE
SBS
CLS1
CLS2
CRL
TRC
RRC
RRI
NORR
MR
NTST

RBR1-8
DR
PE
OE
FE
TRE
TBRE
TRO

5-40

M91C36
Digital Data Separator

AMERICAN MICROSYSTEMS, INC.

Digital son MegaeeUs
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The M91 C36 is a digital data separator for use with a
floppy disk controller. It takes the "raw" FM or MFM data
pulses from a disk drive and outputs a clock at the bit rate
and data pulses synchronized to that clock. These signals
can then go to a floppy disk controller, such as the MFDC,
M765A or similar, for decoding. Three control lines, and
the FM/MFM control line, together with a clock (typically 48
or 60 MHz) determine the data rate. This data rate can be
up to 1.25 Mbps.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• Data rates up to 1.25 Mbps
• 75% Jitter tolerance
• ±6.25% Frequency range
• Equivalent gates:
Standard Cell - 800; Gate Array - 1,100

The M91 C36 contains a clock selector block and a second
order digital phase-locked loop which locks to the
frequency and phase of the input data pulses.

LOGIC SYMBOL

The clock selector block produces an internal reference
clock 16 times the cycle rate of the phase-locked loop (32
times the data rate). This internal reference clock
determines the resolution to which the inputs and outputs
are sampled, however the phase and frequency errors are
calculated to a much higher resolution (12 bits and 8 bits
respectively). This allows very high performance without
using a very high clock speed.

M91C36
DIN

ClKA
ClKB
DRSO
DRS1
DRS2
MFM
NTST

RDAT
WND

ClK2
TCO

The WND output is toggled at the end of every cycle of the
phase-locked loop (twice per bit period). If a data pulse
occurred at the DIN input during a cycle an active high
pulse, lasting two periods of the internal reference clock
and synchronized to WND, appears at the RDAT output.

NClR

Unlike an analogue data separator the performance of a
digital data separator, such as the M91 C36, is
independent of the data rate. Its performance at 1.25
Mbps (with an internal clock of 40 MHz) is the same as its
performance at 250 Kbps (with an internal clock of 8 MHz).
A per-use fee is associated with this megacell. Contact the
factory for more information.

5-41

M91C360
Digital Data Separator

AMERICAN MICROSYSTEMS.ING.

Digital Soft Megaeells
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The M91 C360 is a digital data separator for use with a
floppy disk or tape controller. It takes the "raw" FM or MFM
data pulses from a disk or tape drive and outputs a clock at
the bit rate and data pulses synchronized to that clock.
These signals can then go to a floppy disk controller, such
as the MFDC, M765A or similar, for decoding.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• Data rates up to 1.25 Mbps
• Floppy disk or tape
• Power saving mode
• Equivalent gates:
Standard Cell - 950; Gate Array - 1,250

LOGIC SYMBOL
M91C360
DIN

ClKA
ClKS
DRSO
DRS1
DRS2

MFM
NTAPE
POWD

NClR
NTST

RDAT
WND

ClK2
TCO

Three control lines, and the FM/MFM control line, together
with a clock (typically 48 or 60 MHz) determine the data
rate. This data rate can be up to 1.25 Mbps.
The M91 C360 can be configured for use with tape drives.
This will increase the frequency range of the data
separator at the cost of a slight reduction in jitter
performance.
The M91 C360 can be placed in a power-down mode which
will stop the internal clock to reduce power when not in
use.
The M91 C360 contains a clock selector block and a
second order digital phase-locked loop which locks to the
frequency and phase of the input data pulses.
The clock selector block produces an internal reference
clock 16 times the cycle rate of the phase-locked loop (32
times the data rate). This internal reference clock
determines the resolution to which the inputs and outputs
are sampled, however the phase and frequency errors are
calculated to a much higher resolution (12 bits and 8 bits
respectively). This allows very high performance without
using a very high clock speed.
The WND output is toggled at the end of every cycle of the
phase-locked loop (twice per bit period). If a data pulse
occurred at the DIN input during a cycle an active high
pulse, lasting two periods of the internal reference clock
and synchronized to WND, appears at the RDAT output.
Unlike an analogue data separator the performance of a
digital data separator, such as the M91 C360, is
independent of the data rate. Its performance at 1.25 Mbps
(with an internal clock of 40 MHz) is the same as its
performance at 250 Kbps (with an internal clock of 8 MHz).
A per-use fee is associated with this megacell. Contact the
factory for more information.

5-42

MFDC
FlOppy Disk Controller

AMERICAN MICROSYSTEMS,INC.

Digital Soft Megaeells
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The MFDC is a floppy disk controller which uses the
M765A floppy disk controller core and includes the
interface circuitry required in IBM PC compatible systems.
It includes power saving features which are software
compatible with the 82077SL. These include a clock
disable signal, immediate auto-powerdown, low-latency
awakening and a power-saving state for the write
precompensator. The MFDC also contains multiplexers for
swapping the default drive control outputs under software
control.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• IBM System 3740 format
• IBM System 34 format
• Perpendicular recording format
• Data rates up to 1.25 Mbps
• Directly addresses 256 tracks
• 255 step recalibrate command
• Programmable write precompensation
• 16 byte FIFO
• Enhanced power-saving features
• Equivalent gates:
Standard Cell - 8,100; Gate Array - 10,500

LOGIC SYMBOL
MFDC
DB10-7
AO-2
NWR
NRD
ClK
NOACK
TC
RSET
MODEO-2
NSM
DIRD3
SMAPRE
SMAPME
DSKCHG
DRV2
TRKO
WRP
INDEX
RAW
DTYPO-1
MTYPO-1
NlOW
RDAT
WND
NSlM
NTEST
NCS

DBOO-7
NDBDO
NDBD2
NDBD4
NDBD7
IRQ
DRQ
DMADIS
MEO-3
DRO-3
SIDE
STP
DIR
WDAT
WE
DENSEl
FTR
SYNC
MFM
NTAPE
DRSO-2
POWD
IDLE
DOSC

The MFDC can be combined with the M91 C360 digital
data separator (or another data separator) to form a
complete 82077SL compatible PC and PS/2™ floppy disk
subsystem.
All references in this document to the 'core' or 'M765A'
refer to the M765A Floppy Disk Controller that is
incorporated in the MFDC net list.
PS/2™ is a trademark of IBM Corporation.
The MFDC uses the M765A core and provides additional
interfacing logic for a PC compatible system. The
additional blocks added to the M765A core are:

110 BUFFERING. This block provides a PC compatible
CPU interface and access to additional registers outside
the M765Acore. The polarity of control signals can also be
inverted by this block.
CLOCK GENERATOR. This block produces three clocks
for the M765A core from the 24/30 MHz input clock to the
MFDC.The frequency of the clocks to the M765A core are
set by the data rate selected.
DRIVE MAPPING. This block controls the mapping of the
logical drive numbers from the M765A core to the physical
drive numbers coming from the MFDC.
WRITE PRECOMPENSATION. This block applies
precompensation to the data stream coming from the
M765A core. The amount of precompensation is
determined by the delay period and data rate.
POWERDOWN CONTROLLER. This block can provide
either direct or automatic powerdown which will stop
internal clocks to save power.
A per-use fee is associated with this megacell. Contact the
factory for more information.

5-43

!GI2CSL
I CSerial Bus Slave Transceiver

AMERICAN MICROSYSTEMS,INC.

Digital son Megacells
Features

Description

• Phillips licensed FC slave transceiver.

The MGI2CSL megacell implements an 12C serial to 8-bit
parallel bidirectional 110 port. The MGI2CSL is designed to
provide FC bus handshaking and protocol support for a
slave port. The seven bit port address is externally
programmable from the A(6:0) bus. Port addresses are
aSSigned by Phillips.

• Supports normal (100kbitls) and fast (400kbitls) modes
when used with appropriate pads.
• Supports 7-bit addressing.
• Schematic-based, uses the ASIC Standard Library for
technology independence.

LOGIC SYMBOL
MGI2CSL

RE
TST
NACK
8CLD
A(6:0)

DATA
READ
ClK
8T

FUll
RWN

TVAl
B8R(7:0)

80UTN

Received data is not latched. Received data is available on
the BSR bus during the one clock cycle that FULL is HI.
Data must be captured by the external logic during this
time or it will be lost. FULL transitions on the falling edge of
clock.
Because it is a minimal configuration it operates in slave
mode only and does not support any of the following: clock
stretching for slow peripherals, general call addressing, or
ten-bit extended addressing. The MGI2CSL does support
both normal (0 - 100kbit/s) and fast (0 - 400kbitls) modes
when used with appropriate pads. Contact the factory for
pad selection and availability.
Phillips has represented to AMI that purchase of AMI's 12C
components conveys a license under the Phillips FC
Patent Rights to use these components in an FC system.
Provided that the system conforms to the 12C Standard
Specification as defined by Phillips.

Soft Megacells
This soft megacell is in the ASIC Standard Library which is
technology- and process-independent and is available in
both Standard Cells and Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.
Contact the factory for more information.

5-44

AMERICAN MICROSYSTEMS,ING.

12CSerial

MGI2CSL

Bus Slave Transceiver
Digital son Megaeells

Pin Description
SIGNAL

TYPE

SClD

I

Input from bus clock line.

SDAD

I

Input from bus data line.

RE

I

Reset, active high.

TST

I

Test mode, active high.

NACK

I

When high, suppresses transmission of acknowledge signal.

SIGNAL DESCRIPTIONS

A(6:0)

I

Programs 7-bit address that the cell responds to. Address are assigned by Phillips.

DSR(7:0)

I

Parallel data input for serial out.

SOUTN

0

Serial data out to bus driver.

TVAl

0

Transmission valid. Goes high when port has received a valid address.

RWN

0

Status of read/write bit. Indicates whether master is reading or writing to this port. High
indicates a read, a low indicates a write.

FUll

0

High indicates shift register full. BSR bus must be read before the next falling edge of
ClK.

ST

0

High Indicates reception of start signal from bus or reset on RE.

ClK

0

Follows bus clock while transmission is valid.

READ

0

RWN delayed by one clock.

DATA

0

A high level indicates when in DATA mode. A low indicates ADDRESS mode.

BSR(7:0)

0

Parallel data out from serial in.

Equivalent Gates
STANDARD CELL

GATE ARRAY

210

250

5-45

rtI Cl2CBus Interlace

AMERICAN MICROSYSTEMS,INC.

Digital son Megacells
Features

Description

• AMI's implementation of 3Soft's MegaMacro®

The MI2C provides an interface between a microprocessor
and an FC bus. It can operate in master or slave mode and
performs arbitration in master mode to allow it to operate in
multi-master systems. In slave mode it can interrupt the
processor when it recognizes its own 7-bit address or the
general call address. A clock divider is provided to allow
operation from a wide range of input clock frequencies.

• Functionally compatible with the industry standard
• Uses AMI's ASIC Standard Library for technology
independence
• Master or slave operation
• Multi-master systems supported
• Performs arbitration and clock synchronization

A per-use fee is associated with this megacell. Contact the
factory for more information.

• Own address and General Call address detection
• Interrupt on address detection
• Equivalent gates:
Standard Cell - 1,200; Gate Array - 1,450

LOGIC SYMBOL
MI2C

ClK
RST
NTST
100-7
AO
A1
NWR

OAO-7

INTR
OSCl
OSOA

ISCl
ISOA

5-46

MGAxxyyDv
Adder

AMERICAN MICROSYSTEMS.ING

Digital son Megaeells
Features

Description

• High-performance, Schematic-based megacell
synthesizer

The MGAxxyyDv adder synthesizer builds xx-bit by yy-bit
adders. Input operands are A and B with an input carry CI
to produce the output SUM with a carry-out CO.

• Uses the ASIC Standard Library for technology
independence
• Wordlength for inputs A and B are user definable
• Selects multiple architectures for size and speed
efficiency
• Fully buffered inputs and outputs

LOGIC SYMBOL
MGAxxyyDv
CI

co

A((xx-1):O)
8((yy-1):O)

SUM((ww-1):O)

Multiple architectural implementations are synthesized
depending on speed requirements. Possible architectures
include ripple carry, carry look-ahead, and fast carry lookahead.
Inputs A and B and output SUM can be interpreted to be
either in the two's complement or unsigned number
format. The SUM output is the same format as the inputs;
its size is the same as the largest of inputs A or B.
In the name, "xx" represents the A input size and "yy"
represents the B input size. The "V" represents version.
The synthesizer can optimize the design for either
minimum delay, minimum area or a compromise between
the two. Each implementation is given a different version
number. For example, a 24-bit by 20-bit adder optimized
for minimum delay would be named MGA2420D2.

Functional Description
A

B

CI

SUM

CO

A

B

0

A+B

carry-out

A

B

1

A+B+1

carry-out

Contact the factory for information on specific speeds and
sizes or to have an Adder built.

Soft Megacells
This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

5-47

MGAxxyyDv
Adder

AMERICAN MICROSYSTEMS.INC.

Digital Soft Megacells
Pin Description
SIGNAL

TYPE

CI

Input

Carry in, active high.

A((xx-1 ):0)

Input

A Data inputs. A(O) is the LSB.

width> 0

B((yy-1 ):0)

Input

B Data inputs. B(O) is the LSB.

width> 0

CO

Output

Carry out, active high.

SUM((ww-1 ):0)

Output

SUM Data outputs. SUM(O) is the LSB.

SIGNAL DESCRIPTIONS

LEGAL RANGE
1

1
width> 0

Sample Equivalent Gates
STANDARD CELL

CElL NAME

AMISS(O.S micron)

GATE ARRAY

AMI6S(O.6 micron)

AMISG(O.S micron)

AMI6G(O.6 micron)

MGAOSOSD1

62

7S

74

90

MGAOSOSD2

144

143

216

162

MGA1212D1

92

117

110

134

MGA1212D2

217

249

212

263

Sample Delays 1
CElL NAME

STANDARD CELL

GATE ARRAY

AMISS(O.S micron)

AMI6S(O.6 micron)

AMISG(O.S micron)

AMI6G(O.6 micron)

MGAOSOSD1

7.2 ns

5.9 ns

S.1 ns

5.27 ns

MGAOSOSD2

2.5 ns

2.15 ns

2.9 ns

2.17 ns

MGA1212D1

10.3 ns

S.39 ns

11.6 ns

7.54 ns

MGA1212D2

2.9 ns

2.43 ns

3.5 ns

2.37 ns

1. These data are estimated and specified at 5.0V, Tj = 25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-48

MGAxxyyEv

AdderlSublraclor

AMERICAN MICROSYSTEMS, INC.

Digital Soft Megacells
In the name, "xx" represents the A input size and "yy"
represents the B input size. The "v" represents version .
The synthesizer can optimize the design for either
minimum delay, minimum area or a compromise between
the two. Each implementation is given a different version
number. For example, a 24-bit by 20-bit adder/subtractor
optimized for minimum delay would be named
MGS2420A2.

Features
• High-performance, Schematic-based megacell
synthesizer
• Uses the ASIC Standard Library for technology
independence
• Word length for inputs A and B are user definable
• Selects multiple architectures for size and speed
efficiency

Functional Description

• Fully buffered inputs and outputs

LOGIC SYMBOL
MGAxxyyEv

CI

co

A

B

CI

SUM

CO

0

A

B

0

A+B

carry-out

0

A

B

1

A+B+ 1

carry-out

1

A

B

0

A-B

carry-out

1

A

B

1

A - B-1

carry-out

Contact the factory for information on specific speeds and
sizes or to have an Adder/Subtractor built.

A((xx-1):O)
8((yy-1):O)

SUB

SUM((ww-1):O)

Soft Megacells

Description
The MGAxxyyEv adder/subtractor synthesizer builds xxbit by yy-bit adder/subtractors. This megacell either adds
(SUB=O) or subtracts (SUB=1) depending on the value of
SUB. Input operands are A and B with an input carry CI
and a subtract control line SUB. The outputs are SUM and
carry-out CO.
Multiple architectural implementations are synthesized
depending on speed requirements. Possible architectures
include ripple carry, carry look-ahead, and fast carry lookahead.

This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology and process
independent and is available in both Standard Cells and
Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

Inputs A and B and output SUM can be interpreted to be
either in the two's complement or unsigned number
format. The SUM output is the same format as the inputs;
its size is the same as the largest of inputs A or B.

5-49

MGAxxyyEv
Adder/Sublraclor

AMERICAN MICROSYSTEMS,ING.

Digital son Megaeells
Pin Description
SIGNAL

TYPE

SUB

Input

SIGNAL DESCRIPTIONS

LEGAL RANGE

Subtract control. Megacell subtracts when this input is high.

1

CI

Input

Carry in, active high.

A((xx-1):0)

Input

A Data inputs. A(O) is the LSB.

width> 0

1

B((yy-1):0)

Input

B Data inputs. B(O) is the LSB.

width> 0

CO

Output

Carry out, active high.

SUM((ww-1 ):0)

Output

SUM Data outputs. SUM(O) is the LSB.

1
width> 0

Sample Equivalent Gates
CELL NAME

STANDARD CELL

GATE ARRAY

AMIBS(O.B micron)

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

MGA0808E1

82

91

103

121

MGA0808E2

168

186

216

253

MGA1212E1

120

133

151

177

MGA1212E2

288

320

355

415

Sample Delays 1
CELL NAME

GATE ARRAY

STANDARD CELL
AMIBS(O.B micron)

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

MGA0808E1

8.5 ns

7.0 ns

8.8 ns

6.2 ns

MGA0808E2

3.6 ns

3.0 ns

3.5 ns

2.5 ns

MGA1212E1

11.6 ns

9.5 ns

12.4 ns

8.7 ns

MGA1212E2

3.6 ns

3.0 ns

4.2 ns

2.9 ns

1. These data are estimated and specified at 5.0V, Tj =25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-50

MGBxxAv
Barrel/Arithmetic Shilter

AMERICAN MICROSYSTEMS,INC.

Digital Soft Megacells
The type of shift function is controlled by the F inputs and
are as described in the following table.

Features
• Schematic-based megacell synthesizer

Shift Functions

• Uses the ASIC Standard Library for technology
independence

F(2)
0
0
0
1
1

• Wordlength is definable
• High-speed flash shift operations
• Logical and arithmetic shifts available

LOGIC SYMBOL

-

D((xx-1):O)

FUNCTION
Logic shift with zeros fill
Logic shift with ones fill
Arithmetic shift with sign extend
Logical shift with 00 fill
Left of Right circular shift

Logical shift with zeros fill, F(2:0)

-F(2:0)
S(I092(xx)-1 :0)

F(O)
0
1
x
x
x

Sample Truth Tables(MGB04Av):

MGBxxAv

-

F(1)
0
0
1
0
1

8(1:0)
00
01
10
11
Q((xx-1):0)

r----

0(3)

0(2)

0(1)

0(0)

0(3)
0
0
0

0(2)
0(3)
0
0

0(1)
0(2)
0(3)
0

0(0)
0(1 )
0(2)
0(3)

Logical shift with ones fill, F(2:0)

Description
The MGBxxAv barrel/arithmetic shifter synthesizer builds
barrel/arithmetic shifters which provide various shift
functions for a data word size of "xx" bits. The shifts are
performed completely through combinational logic which
allows for very fast operations. Commonly used logical and
arithmetic shift functions are available.
The user has flexibility in specifying the word size. Within
the name shown above, the "xx" represents the size of the
data word. The size of the S bus is equal to log2(xx).
The "v" represents version. The synthesizer can optimize
the design for either minimum delay, minimum area or a
compromise between the two. Each implementation is
given a different version number. For example, an 8-bit
shifter optimized for minimum gatecount would be named
MGB08A1.
The S inputs select the number of bits to be shifted. For a
right circular shift, the S inputs select the number of bits to
be shifted. For a left circular shift, the two's compliment of
the number of bits to be shifted is placed on the S inputs.
In the case of an 8-bit shifter, for example, an input select
value of two (010) operating on the input 00001100 will
generate the output 00000011, a right shift of two bits. If S
has the value of seven (111) the output would become
00011000, which would represent a right shift of seven or
a left shift of one.

5-51

8(1:0)
00
01
10
11

=001

0(3)

0(2)

0(1)

0(0)

0(3)
1
1
1

0(2)
0(3)
1
1

0(1)
0(2)
0(3)
1

0(0)
0(1 )
0(2)
0(3)

Logical shift with 0(0) fill, F(2:0)
8(1:0)
00
01
10
11

=000

=10x

0(3)

0(2)

0(1)

0(0)

0(3)
0(0)
0(0)
0(0)

0(2)
0(3)
0(0)
0(0)

0(1)
0(2)
0(3)
0(0)

0(0)
0(1 )
0(2)
0(3)

Arithmetic shift with sign extend, F(2:0)
8(1:0)
00
01
10
11

0(3)

0(2)

0(1)

0(0)

0(3)
0(3)
0(3)
0(3)

0(2)
0(3)
0(3)
0(3)

0(1)
0(2)
0(3)
0(3)

0(0)
0(1 )
0(2)
0(3)

Left or Right circular shift, F(2:0)
8(1:0)
00
01
10
11

=01 x

=11x

0(3)

0(2)

0(1)

0(0)

0(3)
0(0)
0(1)
0(2)

0(2)
0(3)
0(0)
0(1)

0(1 )
0(2)
0(3)
0(0)

0(0)
0(1)
0(2)
0(3)

MGBxxAv
Barrel/Arithmetic Shilter

AMERICAN MICROSYSTEMS,ING.

Digital Soft Megaeells
Pin Descriptions
SIGNAL

TYPE

LEGAL RANGE

SIGNAL DESCRIPTIONS

F(2:0)

Input

Function inputs. These inputs determine the type of shift to be
performed.

S(I092(xx)-1 :0)

Input

Shift inputs. Specifies the number of position to be shifted.

D((xx-1 ):0)

Input

Data inputs. 0(0) is the LSB.

width> 0

0((xx-1 ):0)

Output

Data outputs. 0(0) is the LSB.

width> 0

3
width

= I092(xx)

Sample Equivalent Gates
CELL NAME

STANDARD CELL

GATE ARRAY

AMIBS(O.B micron)

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

MGB08A1

110

122

124

145

MGB08A2

133

148

156

183

MGB12A1

207

230

247

289

278

304

356

MGB12A2

250

Sample Delays 1
CELL NAME

GATE ARRAY

STANDARD CELL
AMIBS(O.B micron)

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

MGB08A1

4.2 ns

3.4 ns

4.8 ns

3.4 ns

MGB08A2

3.6 ns

3.0 ns

4.0 ns

2.8 ns

MGB12A1

4.2 ns

3.4 ns

4.9 ns

3.4 ns

MGB12A2

3.5 ns

2.9 ns

3.9 ns

2.7 ns

1. These data are estimated and specified at 5.0V, Ti = 25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-52

MGBxxBv
Barrel Shilter

AMERICAN MICROSYSTEMS.ING.

Digital Soft Megaeells
The user has flexibility in specifying the word size. Within
the name shown above, the "xx" represents the size of the
data word. The size of the S bus must be less than or equal
to log2(xx). For example, if xx = 8, the size of the S bus
must be equal to or less than 3. If not all shift combinations
are needed, the size of the S bus can be reduced to save
logic.

Features
• High-performance, Schematic-based megacell
synthesizer
• Uses the ASIC Standard Library for technology
independence
• Wordlength is definable

The "v" represents version. The synthesizer can optimize
the design for either minimum delay, ~inimum are':l or .a
compromise between the two. Each Implementation I~
given a different version number. For example, an 8-blt
shifter optimized for minimum gate count would be named
MGB08B1.

• High-speed flash barrel shift operations
• Fully buffered inputs and outputs

LOGIC SYMBOL
MGBxxBv

Contact the factory for information on specific speeds and
sizes or to have a Shifter built.
-

S(I092(xx)-1 :0)

Sample Truth Table

-

O((xx-1):0)

Q((xx-1):O) -

8(1:0)

0(3)

0(2)

0(1)

0(0)

00

0(3)

0(2)

0(1)

0(0)

01

0(2)

0(1)

0(0)

0(3)

10

0(1)

0(0)

0(3)

0(2)

11

0(0)

0(3)

0(2)

0(1)

Description

Soft Megacells

The MGBxxBv barrel shifter synthesizer builds barrel
shifters which provide various shift functions for a data
word size of "xx" bits. The shifts are performed completely
through combinational logic which allows for very fast
operations. Shifted data wraps around from the MSB to the
LSB.

This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.

The S inputs select the number of bits to be shif~ed ~rom
the D inputs to the Q outputs. In the case of an 8-blt shlf~er,
for example, an input select value of two (010) operating
on the input 00001100 will generate the output 00110000,
a left shift of two bits. If S has the value of seven (111), the
output would become 00000110.

A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used .with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

5-53

MGBxxBv
Barrel Shiller

AMERICAN MICROSYSTEMS,ING.

Digital son Megaeells
Pin Descriptions
SIGNAL

TYPE

S(I092(XX)-1 :0)

Input

Shift inputs. Specifies the number of position to be shifted.

SIGNAL DESCRIPTIONS

D((xx-1 ):0)

Input

Data inputs. D(O) is the LSB.

width> 0

Q((xx-1 ):0)

Output

Data outputs. 0(0) is the LSB.

width> 0

LEGAL RANGE
width ~ I092(XX)

Sample Equivalent Gates
CELL NAME
MGB08B1

STANDARD CELL

GATE ARRAY

AMIBS(O.B micron)

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

77

85

89

104

MGB08B2

80

89

126

147

MGB12B1

155

172

167

195

MGB12B2

200

222

248

290

Sample Delays 1
CELL NAME

STANDARD CELL

GATE ARRAY

AMIBS(O.B micron)

AMI6S(O.6 micron)

MGB08B1

2.3 ns

1.9 ns

2.5 ns

1.8 ns

MGB08B2

2.3 ns

1.9 ns

2.4 ns

1.7 ns

MGB12B1

2.7 ns

2.2 ns

2.6 ns

1.8 ns

MGB12B2

2.8 ns

2.3 ns

3.0 ns

2.1 ns

1. These data are estimated and specified at 5.0V, Tj

AMIBG(O.B micron)

AMI6G(O.6 micron)

=25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-54

MGBxxyyCv
Arithmetic Shilter

AMERICAN MICROSYSTEMS, INC.

Digital Soft Megacells

• Uses the ASIC Standard Library for technology
independence

The "v" represents version. The synthesizer can optimize
the design for either minimum delay, minimum area or a
compromise between the two. Each implementation is
given a different version number. For example an 8-bit
shifter optimized for minimum gate count would be named
MGB0803C1.

• Word length is definable
• High-speed flash arithmetic shift operations

Sample Truth Table (MGB0402Cv):

Features
• High-performance, Schematic-based megacell
synthesizer

• Two's complement or unsigned shift control and data
• Fully buffered inputs and outputs

8(1:0)

8TC

DTC

0(3)

0(2)

0(1)

0(0)

00

0

x

0(3)

0(2)

0(1)

0(0)

LOGIC SYMBOL

01

0

x

0(2)

0(1)

0(0)

0

MGBxxyyCv

10

0

x

0(1)

0(0)

0

0

11

0

x

0(0)

0

0

0

STC
DTC

00

1

x

0(3)

0(2)

0(1)

0(0)

S(I092(XX)-1 :0)

01

1

x

0(2)

0(1)

0(0)

0

10

1

0

0

0

0(3)

0(2)

11

1

0

0

0(3)

0(2)

0(1)

10

1

1

0(3)

0(3)

0(3)

0(2)

11

1

1

0(3)

0(3)

0(2)

0(1 )

D((xx-1):0)

Q((xx-1):0)

Contact the factory for information on specific speeds and
sizes or to have a Shifter built.

Description
The MGBxxyyCv arithmetic shifter synthesizer builds
arithmetic shifters which provide various shift functions for
a data word size of "xx" bits. The shifts are performed
completely through combinational logic which allows for
very fast operations.
The input data 0 is shifted left or right by the number of bits
specified by the control input S. When the control signal
STC is '0', S is interpreted as an unsigned positive number
and the shifter performs only left shift operations.
When STC is '1', S is a two's complement number. If S is
negative, a right shift is performed. If S is positive, a left
shift is performed.
The input data 0 is interpreted as an unsigned number
when OTC is '0' or a two's complement number when OTC
is '1 '. The type of 0 is only significant for right shift
operations where zero padding is done on the MSBs for
unsigned data and sign extension is done for two's
complement data.
The user has flexibility in specifying the word size. Within
the name shown above, the "xx" represents the size of the
data word and "yy" represents the size of the S bus.The
size of the S bus is equal to log2(xx).

Soft Megacells
This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

5-55

MGBxxne,
Arithmetic Shilter

AMERICAN MICROSYSTEMS,INC.

Digital Soft Megaeells
Pin Descriptions
SIGNAL

SIGNAL DESCRIPTIONS

TYPE

LEGAL RANGE

STC

Input

Determines whether S is interpreted as unsigned or two's
complement.

DTC

Input

Determines whether D is interpreted as unsigned or two's
complement.

1

S(log2(XX)-1 :0)

Input

Shift inputs. Specifies the number of position to be shifted.

width < log2(XX)

D((xx-1 ):0)

Input

Data inputs. 0(0) is the LSB.

width> 0

Q((xx-1 ):0)

Output

Data outputs. 0(0) is the LSB.

width> 0

1

Sample Equivalent Gates
CELL NAME

GATE ARRAY

STANDARD CELL
AMIBS(O.B micron)

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

MGB0803C1

130

144

146

171

MGB0803C2

175

194

203

238

MGB1204C1

223

248

245

287

MGB1204C2

320

355

351

411

AMIBS(O.B micron)

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

MGB0803C1

5.0 ns

4.1 ns

5.0 ns

3.5 ns

MGB0803C2

Sample Delays 1
CELL NAME

STANDARD CELL

GATE ARRAY

3.4 ns

2.8 ns

3.6 ns

2.5 ns

MGB1204C1

5.7 ns

4.7 ns

5.7 ns

4.0 ns

MGB1204C2

3.2 ns

2.6 ns

3.4 ns

2.4 ns

1. These data are estimated and specified at 5.0V, Tj

=25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-56

MGCDxxAv
Decrement Counter

AMERICAN MICROSYSTEMS,INC.

Digital son Megaeells
Features

Description

• High-performance, HDL-based megacell synthesizer

The MGCDxxAv synchronous binary counter counts down
on the rising edge of the clock. This counter is available in
all of AMI's supported processes.

• Uses the ASIC Standard Library for technology
independence
• Counter size is definable
• Includes terminal count when count is zero
• Fully buffered inputs and outputs

LOGIC SYMBOL
MGCDxxAv
LOAD

TERM

CE

D((xx-1):O)

CNT((xx-1):O)

The "xx" in the name represents the number of bits in the
counter. For example, an 8-bit counter built for minimum
delay would be named MGCD08A2.
The counter has three input controls LOAD, CE, and
RSTN. Both LOAD and CE must be asserted for the
parallel input to be latched in on the next rising clock edge.
When LOAD is low and CE is high the counter decrements
by one on each rising clock edge. When the count
reaches zero the TERM signal is asserted high. The RSTN
is asynchronous and asserted low. The counter output
(CNT) is the same size as the counter input (D).
Multiple architectural implementations are synthesized
depending on speed requirements. Possible architectures
include ripple carry, carry look-ahead, and fast carry lookahead. These
Megacells
are
produced
using
parameterized synthesizers that allow the creation of
various sizes and speeds. The synthesized Megacell can
be optimized for either minimum delay, minimum gate
count or can be designed to meet a specified delay. Each
implementation is given a different version number. For
example, an 8-bit counter that must run on a 20 ns clock
cycle would be named MGCD08A20.

Soft Megacells
This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

5-57

MGCDxxAv
Decrement Counter

~II~

AMERICAN MICROSYSTEMS,INC.

Digital son MegaeeUs
Pin Description
SIGNAL

TYPE

SIGNAL DESCRIPTIONS

LOAD

Input

Load new count. Data is latched when LOAD and CE are high and the clock transitions
from low to high.

CE

Input

Count enable. Next count or input latched when CE is high and the clock transitions
from low to high.

RSTN

Input

Reset signal. Asynchronously resets counter to 0 when low.

D((xx-1 ):0)

Input

Data inputs. Data appearing on these inputs is latched into the count when LOAD and
CE are high and the clock transitions from low to high.

TERM

Output

Terminal count. Asserted high when the count is all zeros.

CNT((xx-1 ):0)

Output

Data outputs. The output is decremented by one when the clock transitions from low to
high and the CE is asserted.

Sample Equivalent Gates
CELL NAME

STANDARD CEll
AMI6S(O.6 micron)

GATE ARRAY

AMI8S(O.8 micron)

AMI6G(O.6 micron)

AMI8G(O.8 micron)

MGCU08A1

120

130

166

155

MGCU08A2

188

183

205

222

MGCU12A1

179

176

225

238

MGCU12A2

288

277

329

327

AMI6S(O.6 micron)

AMI8S(O.8 micron)

AMI6G(O.6 micron)

AMI8G(O.8 micron)

MGCU08A1

5.4 ns

7.0 ns

4.8 ns

6.4 ns

MGCU08A2

2.9 ns

3.3 ns

3.3 ns

3.6 ns

MGCU12A1

7.3 ns

8.9 ns

6.7 ns

8.3 ns

MGCU12A2

3.2 ns

3.6 ns

3.4 ns

4.0 ns

Sample Clock Cycle Time 1
CELL NAME

STANDARD CEll

GATE ARRAY

1. These data are estimated and specified at 5.0V, Tj =25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-58

MGCDxxAv
Decrement Counter

AMERICAN MICROSYSTEMS,INC.

Digital Soft Megaeells
Count Timing
RSTN

I~

__-----,

---..:

~TRO

ClK

O((xx-1):0)

---..:

:~ Tco

~~_ _ _ _~'~;::

X

-1

-1:X

---.:
LOAD

X

D-1:

X

D-2:

~

;.-TLSU

--------------------------------~r:l~--------------~------~-------.:
;.-TCLSU
~--~I~-------~--~----

CEN

~

D((xx-1 ):0)

D

;'-Tosu

-r7Z--r--Z-r-Z--rZ--r--Z-r-Z-----Z------Z-r-Z---,--Z.,-Z-rZ-------Z-r-/--rZ---'-X,--D~:_ _ _ _ _

- - + - -_ _- + - - -_ _

TTSC

---..:

TERM ________________________________________________________

:.- -.:

~'

Timing Characteristics
SYMBOL
TRO
Tco
TlSU
TClSU
TDSU
TTSC
TTCC

CHARACTERISTIC
reset to output zero
clock to count valid
load set-up
count enable load set-up
data set-up
term set valid
term clear valid

5-59

REFERENCED TO
RSTN falling
elK rising
elK rising
elK rising
elK rising
elK rising
elK rising

,

TTCC

:~

~

MGCUxxAv

Increment Counter

AMERICAN MICROSYSTEMS,INC.

Digital Soft Megaeells
Features

Description

• High-performance, HDL-based megacell synthesizer

The MGCUxxAv synchronous binary counter counts on
the rising edge of the clock. This counter is available in all
of AMI's supported processes.
The "xx" in the name represents the number of bits in the
counter. For example, an 8-bit counter built for minimum
delay would be named MGCU08A2 .

• Uses the ASIC Standard Library for technology
independence
• Counter size is definable
• Includes terminal count when count is all ones
• Fully buffered inputs and outputs

LOGIC SYMBOL
MGCUxxAv
LOAD

TERM

CE

D((xx-1):O)

CNT((xx-1):O)

The counter has three input controls LOAD, CE, and
RSTN. Both LOAD and CE must be asserted for the
parallel input to be latched in on the next rising clock edge.
When LOAD is low and CE is high the counter increments
by one on each rising clock edge. When the count reaches
the maximum count the TERM signal is asserted high. The
RSTN is asynchronous and asserted low. The counter
output (CNT) is the same size as the counter input (D).
Multiple architectural implementations are synthesized
depending on speed requirements. Possible architectures
include ripple carry, carry look-ahead, and fast carry lookahead. These
Megacells
are
produced
using
parameterized synthesizers that allow the creation of
various sizes and speeds. The synthesized Megacell can
be optimized for either minimum delay, minimum gate
count or can be designed to meet a specified delay. Each
implementation is given a different version number. For
example, an 8-bit counter that must run on a 20 ns clock
cycle would be named MGCU08A20.

Soft Megacells
This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

5-60

MGCUxxAv

Increment Counter

AMERICAN MICROSYSTEMS,ING.

Digital son Megacells
Pin Description
TYPE

SIGNAL DESCRIPTIONS

LOAD

Input

Load new count. Data is latched when LOAD and CE are high and the clock transitions
from low to high,

CE

Input

Count enable. Next count or input latched when CE is high and the clock transitions
from low to high.

RSTN

Input

Reset signal. Asynchronously resets counter to 0 when low.

D((xx-1):0)

Input

Data inputs. Data appearing on these inputs is latched into the count when LOAD and
CE are high and the clock transitions from low to high.

TERM

Output

Terminal count. Asserted high when the count is all ones.

CNT((xx-1 ):0)

Output

Data outputs. The output is incremented by one when the clock transitions from low to
high and the CE is asserted.

SIGNAL

Sample Equivalent Gates
CELL NAME

STANDARD CELL

GATE ARRAY

AMI6S(O.6 micron)

AMI8S(O.8 micron)

AMI6G(O.6 micron)

AMI8G(O.8 micron)

MGCU08A1

119

128

152

162

MGCU08A2

155

155

214

207

MGCU12A1

178

172

228

243

MGCU12A2

261

261

355

299

AMI6S(O.6 micron)

AMI8S(O.8 micron)

AMI6G(O.6 micron)

AMI8G(O.8 micron)

MGCU08A1

5.6 ns

6.3 ns

4.9 ns

6.1 ns

MGCU08A2

3.0 ns

3.5 ns

3.1 ns

4.0 ns

MGCU12A1

7.1 ns

7.6 ns

6.6 ns

7.4 ns

MGCU12A2

3.3 ns

4.0 ns

3.3 ns

3.7 ns

Sample Clock Cycle Time 1
CELL NAME

GATE ARRAY

STANDARD CELL

1. These data are estimated and specified at 5.0V, Tj

=25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-61

MGCUxxAv

~II~

Increment Counter

AMERICAN MICROSYSTEMS,ING.

Digital Soft Megaeells
Count Timing
RSTN

11-__----'

ClK
~

O((xx-1):O)

-.-T RO

~

~Tco

~~________~'A

1

x

1
-.:

D+1 : X'--_D+_2---<:.........~

:X'---_D~X
;'-TLSU

lOAD ________________________________~r_:lL------.:

; . -T CLSU

~

:..--TDSU

____________------~-------

CEN

D((xx-1):O)

-r'l--r-Z--r-Z---r--Z-r-Z~Z---r-/-r/~Z--r-Z---,--Z-r-Z-rZ---r-Z
-rZ---"X~D_:_____________- - - - - + - - - - - TTSC

~

',..--

---..: T TCC :.--

TERM ___________________________________________~~I

Timing Characteristics
SYMBOL
T RO

reset to output zero

Teo

clock to count valid

Tlsu
Telsu
T DSU
TTse
TTee

REFERENCED TO

CHARACTERISTIC

RSTN falling
elK rising

elK rising
elK rising
elK rising
elK rising
elK rising

load set-up
count enable load set-up
data set-up
term set valid
term clear valid

5-62

,

'

~

MGCxxAv

~II~

2-Function Comparator

AMERICAN MICROSYSTEMS, INC.

Digital Soft Megaeells
Functional Description

Features
• High-performance, Schematic-based megacell
synthesizer
• Uses the ASIC Standard Library for technology
independence
• Wordlength for inputs A and B are user definable

LEO

Condition

LTLE

GEGT

1

A<= B

1

0

1

A>B

0

1

0

A B

0

1

• Unsigned and two's complement data comparison
• Two comparison functions available

Contact the factory for information on specific speeds and
sizes or to have a Comparator built.

• Fully buffered inputs and outputs

LOGIC SYMBOL

Soft Megacells

MGCxxAv

TC
LEO

This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.

LTLE
GEGT

A((xx-1):O)
8((xx-1):O)

Description
The MGCxxAv comparator synthesizer builds xx-bit 2function comparators. The comparator compares signed
or unsigned numbers (A and B) and produces two output
conditions (LTLE and GEGT).

A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

The input signal LEO determines what these two output
conditions are (see Functional Description). The input TC
determines whether the two inputs are compared as
unsigned (TC = O) or signed (TC = 1).
In the name, "xx" represents the A and B input size and the
represents version. The synthesizer can optimize the
design for either minimum delay, minimum area or a
compromise between the two. Each implementation is
given a different version number. For example, a 24-bit
comparator optimized for minimum delay would be named
MGC24A2.
"V"

5-63

MGCxxAv

2-Function Comparator

AMERICAN MICROSYSTEMS,ING.

Digital Soft Megacells
Pin Description
SIGNAL

TYPE

TC

Input

When 1, signifies A and 8 inputs are two's complement.

SIGNAL DESCRIPTIONS

1

LEO

Input

Determines function of LTLE and GEGT pins.

1

A((xx-1):O)

Input

A Data inputs. A(O) is the LS8.

width> 0

8 Data inputs. 8(0) is the LSB.

width> 0

LEGAL RANGE

8((xx-1 ):0)

Input

LTLE

Output

'Less than' or 'less than or equal' depending on LEO.

1

GEGT

Output,

'Greater than or equal' or 'greater than' depending on LEO.

1

Sample Equivalent Gates
CELL NAME

STANDARD CELL
AMIBS(O.B micron)

GATE ARRAY

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

MGC08A1

39

43

45

53

MGC08A2

92

102

94

110

MGC12A1

53

59

61

71

MGC12A2

100

111

118

138

AMIBS(O.B micron)

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

MGC08A1

3.6 ns

3.0 ns

4.1 ns

2.9 ns

MGC08A2

2.1 ns

1.7 ns

2.4 ns

1.7 ns

MGC12A1

5.1 ns

4.2 ns

5.7 ns

4.0 ns

MGC12A2

2.4 ns

2.0 ns

2.8 ns

2.0 ns

Sample Delays1
CELL NAME

STANDARD CELL

1. These data are estimated and specified at 5.0V, Tj

GATE ARRAY

=25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-64

MGCxxBv

6-Function Comparator

AMERICAN MICROSYSTEMS, INC.

Digital Soft Megaeells
Features

Description

• High-performance, Schematic-based megacell
synthesizer

The MGCxxBv comparator synthesizer builds xx-bit 6function comparators. The comparator compares signed
or unsigned numbers (A and B) and produces six output
conditions (GT, LT, EO, LE, GE, NE).

• Uses the ASIC Standard Library for technology
independence
• Wordlength for inputs A and B are user definable
• Unsigned and two's complement data comparison
• Six comparison functions available
• Fully buffered inputs and outputs

LOGIC SYMBOL
MGCxxBv

The input TC determines whether the two inputs are
compared as unsigned (TC=O) or signed (TC=1).
In the name, "xx" represents the A and B input size and the
"v" represents version. The synthesizer can optimize the
design for either minimum delay, minimum area or a
compromise between the two. Each implementation is
given a different version number. For example, a 24-bit
comparator optimized for minimum delay would be named
MGC24B2.

GT

Te

LT
EQ
LE
GE

Functional Description

NE

A((xx-1):O)

Condition

GT

IT

EQ

lE

A>B

1

a

A 0

B((xx-1 ):0)

Input

B Data inputs. B(O) is the LSB.

width> 0

GT

Output

Asserted when A is greater than B.

1

SIGNAL DESCRIPTIONS

LEGAL RANGE
1

LT

Output

Asserted when A is less than B.

1

EQ

Output

Asserted when A equals B.

1

LE

Output

Asserted when A is less than or equal to B.

1

GE

Output

Asserted when A is greater than or equal to B.

1

NE

Output

Asserted when A does not equal B.

1

Sample Equivalent Gates
CELL NAME

STANDARD CELL
AMIBS(O.B micron)

GATE ARRAY

AMISS(O.S micron)

AMIBG(O.B micron)

AMISG(O.S micron)

MGC08B1

70

78

77

90

MGC08B2

120

133

174

204

MGC12B1

98

109

108

126

MGC12B2

182

202

252

295

Sample Delays 1
CELL NAME

STANDARD CELL

GATE ARRAY

AMIBS(O.B micron)

AMISS(O.S micron)

AMIBG(O.B micron)

AMISG(O.S micron)

MGC08B1

4.7 ns

3.9 ns

4.4 ns

3.0 ns

MGC08B2

2.2 ns

1.8 ns

3.0 ns

2.1 ns

MGC12B1

6.0 ns

4.9 ns

6.3 ns

4.4 ns

MGC12B2

2.6 ns

2.1 ns

2.5 ns

1.8 ns

1. These data are estimated and specified at 5.0V, Tj

=25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-66

MGDxxAv

Decrementer

AMERICAN MICROSYSTEMS, INC.

Digital Soft Megaeells
Features

Description

• High-performance, Schematic-based megacell
synthesizer

The MGDxxAv decrementer synthesizer builds xx-bit
decrementers. The decrementer subtracts 1 from input A
to produce the output SUM.
Multiple architectural implementations are synthesized
depending on speed requirements. Possible architectures
include ripple carry, carry look-ahead, and fast carry lookahead.

• Uses the ASIC Standard Library for technology
independence
• Wordlength for input A is user definable
• Selects multiple architectures for size and speed
efficiency
• Fully buffered inputs and outputs

LOGIC SYMBOL
MGDxxAv

-

A((xx-1):O)

SUM((xx-1 ):0) f - - -

The SUM output is the same size as the input A .
In the name, "xx" represents the A input size and the "v"
represents version. The synthesizer can optimize the
design for either minimum delay, minimum area or a
compromise between the two. Each implementation is
given a different version number. For example, a 24-bit
decrementer optimized for minimum delay would be
named MGD24A2.

Functional Description
A

A

SUM
A- 1

Contact the factory for information on specific speeds and
sizes or to have a Decrementer built.

Soft Megacells
This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

5-67

MGDxxAv

Decremenler

AMERICAN MICROSYSTEMS,INC.

Digital son MegaeeUs
Pin Description
SIGNAL

TYPE

A((xx-1 ):0)

Input

SIGNAL DESCRIPTIONS

SUM((xx-1 ):0)

Output

LEGAL RANGE

A Data inputs. A(O) is the LSB.

width> 0

SUM Data outputs. SUM(O) is the LSB.

width> 0

Sample Equivalent Gates
CELL NAME

STANDARD CELL

GATE ARRAY

AMI8S(O.8 micron)

AMI6S(O.6 micron)

AMI8G(O.8 micron)

AMI6G(O.6 micron)

MGD08A1

31

30

35

45

MGD08A2

53

66

71

91

MGD12A1

48

47

55

69

MGD12A2

88

112

118

154

AMI8S(O.8 micron)

AMI6S(O.6 micron)

AMI8G(O.8 micron)

AMI6G(O.6 micron)

4.6 ns

3.4 ns

4.7 ns

3.24 ns

Sample Delays 1
CELL NAME
MGD08A1

STANDARD CELL

GATE ARRAY

MGD08A2

1.5 ns

1.5 ns

1.7 ns

1.39 ns

MGD12A1

7.2 ns

5.0 ns

7.3 ns

4.88 ns

MGD12A2

1.6 ns

1.6 ns

1.9 ns

1.67 ns

1. These data are estimated and specified at 5.0V, Tj

=

25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-68

MGlxxAv

Incremenler

AMERICAN MICROSYSTEMS,INC.

Digital Soft Megacells
Features

Description

• High-performance, Schematic-based megacell
synthesizer

The MGlxxAv Incrementer synthesizer builds xx-bit
Incrementers. The incrementer adds 1 to input A to
produce the output SUM.
Multiple architectural implementations are synthesized
depending on speed requirements. Possible architectures
include ripple carry, carry look-ahead, and fast carry lookahead.

• Uses the ASIC Standard Library for technology
independence
• Wordlength for input A is user definable
• Selects multiple architectures for size and speed
efficiency
• Fully buffered inputs and outputs

LOGIC SYMBOL
MGlxxAv

-

A((xx-1):O)

SUM((xx-1):O) -

In the name, "xx" represents the A and SUM input sizes,
and the "v" represents version. The synthesizer can
optimize the design for either minimum delay, minimum
area or a compromise between the two. Each
implementation is given a different version number. For
example, a 24-bit incrementer optimized for minimum
delay would be named MG124A2.

Functional Description
A

SUM

A
Contact the factory for information on specific speeds and
sizes or to have an Incrementer built.

Soft Megacells
This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

5-69

MGlxxAv

Incremenler

AMERICAN MICROSYSTEMS.ING.

Digital son Megaeells
Pin Description
LEGAL RANGE

SIGNAL DESCRIPTIONS

SIGNAL

TYPE

A((xx-1 ):0)

Input

SUM((xx-1 ):0)

Output

A Data inputs. A(O) is the LSB.

width> 0

SUM Data outputs. SUM(O) is the LSB.

width> 0

Sample Equivalent Gates
CELL NAME

GATE ARRAY

STANDARD CELL

AMI8G(O.8 micron)

AMI6G(O.6 micron

37

39

46

50

53

62

52

58

62

73

83

92

112

131

AMI8S(O.8 micron)

AMI6S(O.6 micron)

AMI8G(O.8 micron)

AMI6G(O.6 micron

MGI08A1

2.7 ns

2.2 ns

3.0 ns

2.1 ns

MGI08A2

1.4 ns

1.2 ns

1.6 ns

1.1 ns

MGI12A1

3.0 ns

2.5 ns

4.7 ns

3.3 ns

MGI12A2

1.6 ns

1.3 ns

1.8 ns

1.3 ns

AMI8S(O.8 micron)

AMI6S(O.6 micron)

MGI08A1

33

MGI08A2

45

MGI12A1
MGI12A2

Sample Delays 1
CELL NAME

GATE ARRAY

STANDARD CELL

1. These data are estimated and specified at 5.0V, Tj =25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-70

MGlxxBv

IncremenlerlDecremenler

AMERICAN MICROSYSTEMS,ING.

Digital Soft Megacells
Features

Description

• High-performance, Schematic-based megacell
synthesizer

The MGlxxBv Incrementer/Decrementer synthesizer
builds xx-bit Incrementer/Decrementers. When the DEC
input is active (DEC=1) the Incrementer/Decrementer
subtracts 1 from input A. When DEC is not active (DEC=O)
the Incrementer/Decrementer adds 1 to input A.

• Uses the ASIC Standard Library for technology
independence
• Word length for input A is user definable

Multiple architectural implementations are synthesized
depending on speed requirements. Possible architectures
include ripple carry, carry look-ahead, and fast carry lookahead.

• Selects multiple architectures for size and speed
efficiency
• Fully buffered inputs and outputs

In the name, "xx" represents the A and SUM input sizes,
and the "v" represents version. The synthesizer can
optimize the design for either minimum delay, minimum
area or a compromise between the two. Each
implementation is given a different version number. For
example, a 24-bit Incrementer/Decrementer optimized for
minimum delay would be named MG124B2.

LOGIC SYMBOL
MGlxxBv

Functional Description
A((xx-1):O)

SUM((xx-1):O)

A

DEC

A

o

A

SUM
A-1

Contact the factory for information on specific speeds and
sizes or to have an Incrementer/Decrementer built.

Soft Megacells
This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

5-71

MGlxxBv

IncremenlerlDecremenler

AMERICAN MICROSYSTEMS,ING.

Digital Soft Megacells
Pin Description
SIGNAL

TYPE

SIGNAL DESCRIPTIONS

LEGAL RANGE

DEC

Input

Decrement. Megacell decrements when input is high.

A((xx-1):O)

Input

A Data inputs. A(O) is the LSB.

width> 0

SUM((xx-1 ):0)

Output

SUM Data outputs. SUM(O) is the LSB.

width> 0

1

Sample Equivalent Gates
CElL NAME

STANDARD CELL
AMI8S(O.8 micron)

GATE ARRAY

AMI6S(O.6 micron)

AMI8G(O.8 micron)

AMI6G(O.6 micron)

MGI08B1

60

67

78

91

MGI08B2

86

95

117

137

MGI12B1

95

105

128

150

MGI12B2

162

180

204

239

AMI8S(O.8 micron)

AMI6S(O.6 micron)

AMI8G(O.8 micron)

AMI6G(O.6 micron)

7.5 ns

6.2 ns

7.0 ns

4.9 ns

Sample Delays 1
CElL NAME
MGI08B1

STANDARD CELL

GATE ARRAY

MGI08B2

2.2 ns

1.8 ns

2.6 ns

1.8 ns

MGI12B1

12.2 ns

10.0 ns

11.1 ns

8.2 ns

MGI12B2

2.7 ns

2.2 ns

3.1 ns

2.2 ns

1. These data are estimated and specified at 5.0V, Tj

=25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-72

. _ - - - - - - - - - - - - -

----

MGMxxyyDv
Multiplier

AMERICAN MICROSYSTEMS,INC.

Digital Soft Megacells
Features

Description

• High-performance, Schematic-based megacell
synthesizer

The MGMxxyyDv Multiplier synthesizer builds multipliers
of various sizes. The operands A and B are multiplied to
produce the product P. The input and output data are
interpreted as unsigned when TC=O or two's complement
when TC=1.

• Uses the ASIC Standard Library for technology
independence
• Inputs and output sizes are user definable
• Selects multiple architectures for size and speed
efficiency
• Two's complement control allows either unsigned or two's
complement format
• Fully buffered inputs and outputs

LOGIC SYMBOL
MGMxxyyDv
TC

The "v" represents version. The synthesizer can optimize
the design for either minimum delay, minimum area or a
compromise between the two. Each implementation is
given a different version number. For example, a 16-bit by
12-bit multiplier optimized for minimum delay would be
named MGM1612D2.

Soft Megacells
This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.

A((xx-1):0)

P((xx+yy-1 ):0)
8((yy-1):0)

The "xxyy" represents a four character sequence assigned
to each multiplier configuration where "xx" represents the
number of A input bits and "yy" represents the number of B
input bits. The number of products bits are equal to "xx" +
"yy".

A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
fUnctional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.
Contact the factory for information on specific speeds and
sizes or to have a Multiplier built.

5-73

-

- - -

MGMxxnDv
Multiplier

AMERICAN MICROSYSTEMS,ING.

Digital son MegaeeUs
Pin Description
SIGNAL

TYPE

SIGNAL DESCRIPTIONS

LEGAL RANGE

TC

Input

Determines whether the input and output data are interpreted as
unsigned (TC=O) or two's complement (TC=1) numbers.

A((xx-1 ):0)

Input

A input bits. A(O) is the LSB.

width> 0

B((yy-1):O)

Input

B input bits, B(O) is the LSB.

width> 0

P((xx+yy-1):O)

Output

Product bits. P(O) is the LSB.

xx + yy > width > 0

1

Sample Equivalent Gates
CELL NAME

STANDARD CELL

GATE ARRAY

AMIBS(O.B micron)

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

MGM0808D1

490

515

583

602

MGM0808D2

696

668

925

852

MGM1212D1

1,060

1,128

1,252

1,288

MGM1212D2

1,357

1,457

1,756

1,700

AMIBS(O.B micron)

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

17.0 ns

12.5 ns

17.1 ns

11.4 ns

Sample Delays 1
CELL NAME
MGM0808D1

STANDARD CELL

GATE ARRAY

MGM0808D2

10.0 ns

7.9 ns

10.2 ns

6.8 ns

MGM1212D1

25.5 ns

18.4 ns

24.9 ns

15.8 ns

MGM1212D2

12.3 ns

9.2 ns

12.6 ns

8.7 ns

1. These data are estimated and specified at 5.0V, Tj

=25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-74

MGMxxnEv
Multiplier-Accumulator

~II~

AMERICAN MICROSYSTEMS,INC.

Digital son Megaeells
Features

Description

• High-performance, Schematic-based megacell
synthesizer

The MGMxxyyEv multiplier-accumulator synthesizer
builds multiplier-accumulators of various sizes. The
operands A and B are multiplied and the product is added
to C producing the result MAC. The input and output data
are interpreted as unsigned when TC=O or two's
complement when TC=1.

• Uses the ASIC Standard Library for technology
independence
• Widths for inputs A and B are definable
• Selects multiple architectures for size and speed
efficiency
• Two's complement control allows unsigned or two's
complement multiplication-accumulation
• Fully buffered inputs and outputs

LOGIC SYMBOL
MGMxxyyEv

TC

The "xxyy" represents a four character sequence assigned
to each multiplier-accumulator configuration where "xx"
represents the number of A input bits and "yy" represents
the number of B input bits. The number of MAC bits are
equal to "xx" + "yy" .
The "v" represents version. The synthesizer can optimize
the design for either minimum delay, minimum area or a
compromise between the two. Each implementation is
given a different version number. For example, a 16-bit by
12-bit multiplier-accumulator optimized for minimum delay
would be named MGM1612E2.

Soft Megacells
A((xx-1):0)

8((xx-1):0)

C((xx+yy-1 ):0)

MAC((xx+yy-1):0)

This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.
Contact the factory for information on specific speeds and
sizes or to have a Multiplier-Accumulator built.

5-75

MGMxxyyEv
Multiplier-Accumulator

AMERICAN MICROSYSTEMS.INC.

Digital son Megaeells
Pin Description
SIGNAL

TYPE

SIGNAL DESCRIPTION

LEGAL RANGE

TC

Input

Determines whether the input and output data are interpreted as
unsigned (TC=O) or two's complement (TC=1) numbers.

1

A((xx-1 ):0)

Input

A input bits. A(O) is the LSB.

width> 0

B((yy-1):0)

Input

B input bits. B(O) is the LSB.

width> 0

C((xx+yy-1 ):0)

Input

C input bits. C(O) is the LSB.

width = xx + yy

MAC( (xx+yy-1 ) :0)

Output

Result bits. MAC(O) is the LSB.

width = xx + yy

Sample Equivalent Gates
CELL NAME
MGM0808E1

STANDARD CELL

GATE ARRAY

AMIBS(O.B micron)

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

702

779

872

1,020

MGM0808E2

777

862

1,045

1,223

MGM1212E1

1,415

1,570

1,758

2,057

MGM1212E2

1,610

1,787

1,860

2,176

Sample Delays 1
CELL NAME

STANDARD CELL

GATE ARRAY

AMIBS(O.B micron)

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

MGM0808E1

15.0 ns

12.3 ns

16.3 ns

11.4 ns

MGM0808E2

11.8 ns

9.7 ns

12.0 ns

8.4 ns

MGM1212E1

19.5 ns

16.0 ns

21.0 ns

14.7 ns

MGM1212E2

12.7 ns

10.4 ns

13.1 ns

9.2 ns

1. These data are estimated and specified at 5.0V, Tj

=25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-76

MGSxxyyAv

Sublraclor

AMERICAN MICROSYSTEMS,INC.

Digital Soft Megaeells
Features

Description

• High-performance, Schematic-based megacell
synthesizer

The MGSxxyyAv subtractor synthesizer builds xx-bit by yybit subtractors. Input operands are A and B with an input
carry CI to produce the output DIFF with a carry-out CO.
Multiple architectural implementations are synthesized
depending on speed requirements. Possible architectures
include ripple carry, carry look-ahead, and fast carry lookahead.

• Uses the ASIC Standard Library for technology
independence
• Wordlength for inputs A and B are user definable
• Selects multiple architectures for size and speed
efficiency
• Fully buffered inputs and outputs

LOGIC SYMBOL
MGSxxyyAv
CI

co

A((xx-1):O)
8((yy-1):O)

DIFF((ww-1):O)

Inputs A and B and output DIFF can be interpreted to be
either in the two's complement or unsigned number
format. The DIFF output is the same format as the inputs,
and its size is the same as the largest of inputs A or B.
In the name, "xx" represents the A input size and "yy"
represents the B input size. The "v" represents version.
The synthesizer can optimize the design for either
minimum delay, minimum area or a compromise between
the two. Each implementation is given a different version
number. For example, a 24-bit by 20-bit subtractor
optimized for minimum delay would be named
MGS2420A2.

Functional Description
A

B

CI

D1FF

CO

A

B

0

A-B

carry-out

A

B

1

A - B-1

carry-out

Contact the factory for information on specific speeds and
sizes or to have an Subtractor built.

Soft Megacells
This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

5-77

MGSxxnAv

Sublraclor

AMERICAN MICROSYSTEMS, INC.

Digital Soft Megaeells
Pin Description
SIGNAL

TYPE

CO

Output

SIGNAL DESCRIPTION

LEGAL RANGE

Carry out, active high,

1

A((xx-1 ):0)

Input

A Data inputs. A(O) is the LS8.

width> 0

8((yy-1 ):0)

Input

8 Data inputs. 8(0) is the LS8.

width> 0

CI

Input

Carry in, active high.

DIFF((ww-1 ):0)

Output

1
width> 0

DIFF Data outputs. DIFF(O) is the LS8.

Sample Equivalent Gates
CELL NAME

GATE ARRAY

STANDARD CELL
AMIBS(O.B micron)

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

MGS0808A1

70

78

82

96

MGS0808A2

163

181

232

271

MGS1212A1

105

117

122

1,363

MGS1212A2

217

241

285

333

AMIBS(O.B micron)

AMI6S(O.6 micron)

AMIBG(O.B micron)

AMI6G(O.6 micron)

7.4 ns

6.1 ns

8.2 ns

5.7 ns

Sample Delays 1
CELL NAME
MGS0808A1

GATE ARRAY

STANDARD CELL

MGS0808A2

2.7 ns

2.3 ns

3.3 ns

2.3 ns

MGS1212A1

10.5 ns

8.8 ns

11.8 ns

8.3 ns

MGS1212A2

3.3 ns

2.8 ns

3.8 ns

2.7 ns

1. These data are estimated and specified at 5.0V, Tj = 25°C and O.1pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-78

MGFxxyyCl
Latch-based FIFO

AMERICAN MICROSYSTEMS,ING.

Digital son Megaeells
Features

Description

• High-performance, schematic-based megacell
synthesizer

The MGFxxyyC1 FIFO (First In, First Out) memory
synthesizer builds latch based FIFOs of various sizes.
FIFOs built with this synthesizer use the fall-through
algorithm in which data is written to the top of the register
stack and falls through to the bottom of the stack. If the
FIFO is not empty the data stops falling through when valid
data are encountered. Data fallen through to the bottom of
the stack are available at the outputs.

• Uses the ASIC Standard Library for technology
independence
• Uses latch-array, fall-through architecture
• Array sizes are definable
• Fully buffered inputs and outputs

LOGIC SYMBOL
MGFxxyyC1
WRN
RON

IRN

0---

ORN

0---

RSTN

O((yy-1):O)

O((yy-1):O)

These FIFOs have separate asynchronous read and write
clocks. Flags include ORN (output ready not) which
determines if the FIFO is empty and IRN (input ready not)
which determines if the FIFO is full. Indeterminable results
may occur during writes when IRN is active.
The "xxyy" in the name represents a four character
sequence assigned to each FIFO configuration where "xx"
represents the number of words and ''yy'' represents the
number of bits per word. For example, a 32-word by 8-bit
FIFO would be named MGF3208C1.
Contact the factory for information on specific speeds and
sizes or to have a FIFO built.

Soft Megacells
This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

5-79

MGFxxnCl
Latch-based FIFO

AMERICAN MICROSYSTEMS,ING.

Digital Soft Megacells
Pin Description
SIGNAL

TYPE

WRN

Input

Write clock. Data is latched when WRN transitions from low to high.

RON

Input

Read clock. On the low to high transition of RON data on the bottom of the FIFO is
replaced with data from immediately above.

RSTN

Input

Reset signal. Sets FIFO to empty.

D((yy-1 ):0)

Input

Data inputs. Data appearing on these inputs are written into the FIFO on the low to
high transition of WRN. 0(0) is the LSB.

IRN

Output

Input Ready Not. A low on this signal indicates the FIFO is either full or busy. Writing
when IRN is low will cause data to be lost.

ORN

Output

Output Ready Not. A low on this signal indicates that data appearing on the outputs are
valid.

O((yy-1 ):0)

Output

Data outputs. The data stored on the bottom of the stack are constantly available
through these signals and are updated on the rising edge of RON.

SIGNAL DESCRIPTIONS

Sample Equivalent Gates
CELL NAME

STANDARD CELL

GATE ARRAY

AMI6S(O.6 micron)

AMISS(O.S micron)

MGF0232C1

260

253

320

323

MGF0809C1

290

274

368

369

MGF1616C1

843

761

1,030

1,031

MGF1632C1

1,542

1,366

1,846

1,863

AMI6S(O.6 micron)

AMISS(O.S micron)

AMI6G(O.6 micron)

AMISG(O.S micron)

6.1 ns

6.4 ns

5.3 ns

6.2 ns

AMI6G(O.6 micron)

AMISG(O.S micron)

Sample Fall-through Delays 1
CELL NAME
MGF0232C1

STANDARD CELL

GATE ARRAY

MGF0809C1

21.9 ns

23.1ns

18.7 ns

21.4 ns

MGF1616C1

43.1 ns

45.4 ns

36.9 ns

41.9 ns

MGF1632C1

44.5 ns

45.5 ns

39.1 ns

43.2 ns

1. These data are estimated and specified at 5.0V, Tj

=25°C and 0.1 pF output loading. Actual characteristics will vary based on the final gate count, layout, voltage and temperature.

5-80

MGFxxyyCl
Latch-based FIFO

AMERICAN MICROSYSTEMS, INC.

Dlgilal son Megacells
Read / WriteTiming
RSTN

IRN

ORN

Ih__----'

,TWIRl\!

~

---..:

-.-T RIRN

---..:

' . -T RORN'

:"-";TWIR

FIFO FULL

:~T RIR

:~TWOR

T RORN :..--.:

~T ROR

~~_ _'>--'~----'--'-'-~~-~"",--:________
FIFO EMPTY

ZZ)(~---.------,--:----""",--:___--+---'~

WRN

RDN

---..:
D((yy-1):O)

;.-TDSU

-------~x==x---------:--------------

---..:

:.-Tov

O((yy-1):O) - - - - - - - - - - - - - - - - - - - - 7 " " " ' - ,X---V-A-L-ID---X

VALID

Timing Characteristics
SYMBOL
TRIRN

REFERENCED TO

CHARACTERISTIC
reset to input ready set

RSTN

falling
falling

T RORN

reset to output ready clear

RSTN

TWIRN

write to input ready clear

WRN

falling

TWOR

write to output ready set

WRN

rising

TWIR

write to input ready set

WRN

rising

TRIR

read to input ready set

RON

rising

read to output ready clear

RON

falling

T RORN
T ROR

read to output ready set

RON

rising

T DSU

data setup to write

WRN

rising

Tov

read to output valid

RON

5-81

rising

MGFxxxxnD

Synchronous FIFO

AMERICAN MICROSYSTEMS,INC.

Digital son Megacells
Inputs AO and WR are used to write to the registers which
control the AE (almost empty) and AF (almost full) flags.
When AO is low, data on the 01 bus is written into the AE
register on the rising edge of WR. When AO is high data is
written into the AF register. On reset the AE register
defaults to 25% of "xxxx" and AF to 75% of "xxxx".

Features
• Dual-port RAM architecture for zero fall-through time
• Dynamically programmable almost-full and almost-empty
flags.
• Synchronous design

The width of the data input (01) bus is equal to the greater
of, the number of bits per word or log2 (number of words in
FIFO).

• Word width and depth are user definable
• High-performance, Schematic-based megacell
• Uses the ASIC Standard Library for technology
independence

Flags include FE, (FIFO empty) FF, (FIFO full) and the
dynamically programmable AE (almost empty) and AF
(almost full) flags.

LOGIC SYMBOL

The MGFxxxxyyD features a split reset line to allow
implementation of a re-transmit function. XRRST and
XWRST are synchronous active low resets for the read
counter and write counter respectively. Each reset must be
held active for at least one rising edge of its respective
clock to initialize the FIFO.

MGFxxxxyyD

XRRST
XWRST
WCLK
WE
RCLK
RE
AO
WR
DI((nn)-1:0)

FF
FE
AF
AE

To implement a re-transmit function the total number of
writes since the last general reset must be LESS THAN the
number of words in the FIFO. As long as this condition is
met the read counter may be reset and all the words
written since the general reset may be reread. Notice that
if the AE register has been programed to a different value,
the read reset will return it to the default.

DO((yy)-1 :0)

Contact the factory for information on specific speeds and
sizes or to have a FIFO built.

Description
The MGFxxxxyyD FIFO (First In, First Out) builds
synchronous FIFOs of various sizes. These FIFOs use a
Dual-Port Synchronous Static RAM to allow large FIFO
depth without any fall-through time. This FIFO is available
in the SOX (1.0 u Standard Cell) and AMI8S (0.8 u
Standard Cell) technologies.
The "xxx x" in the name represents the number of words in
the FIFO, and must be a power of 2 between five and ten.
(i.e. 32 minimum to 1024 maximum) The "yy" is the number
of bits per word and can be from one to any size needed.
For example, a 128 word by 16 bit FIFO would be named
MGF012816D.
Clock inputs WCLK and RCLK are free-running. Data is
written into the FIFO on the falling edge of WCLK when
WE is high. WE should only transition when WCLK is low.
Data is read on the rising edge of RCLK when RE is high.
The output data must be captured by external logic before
the next rising edge of RCLK.

Soft Megacells
This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logic from the
ASIC Standard Library to build a complete system on a
chip.

5-82

MGFxxxxyyD
Synchronous FIFO

AMERICAN MICROSYSTEMS,ING.

Digital Soft MegaeeUs
Pin Description
SIGNAL

SIGNAL DESCRIPTIONS

TYPE

Synchronous write reset. Resets the write portion of the FIFO. Must be held low
during a rising edge of WCLK.

XWRST

I

WCLK

I

Free-running write clock.

WE

I

Write enable. Data appearing on Din will be written into the FIFO on the falling edge
of WCLK when WE is high. WE should transition only when WCLK is low.

XRRST

I

Synchronous read reset. Resets the read portion of the FIFO. Must be held low
during a rising edge of RCLK.

RCLK

I

Free-running read clock.

RE

I

Read enable. Data is read from the FIFO on the rising edge of RCLK when RE is
high.

AO

I

Address for determining if the AE or AF flag register is to be written. When AO
AF flag register is written.

WR

I

Write control for AE and AF registers. Data appearing on Din is written into either the
AE or AF register on the rising edge of WR.

DI((nn)-1 :0)

I

Data into the FIFO and the AE/AF registers.

DO((yy)-1 :0)

0
0
0
0
0

FF
AF
FE
AE

Data out of the FIFO.
FIFO full flag, active high. Synchronized to WCLK.
FIFO almost full flag, active high. Synchronized to WCLK.
FIFO empty flag, active high. Synchronized to RCLK.
FIFO almost empty flag, active high. Synchronized to RCLK.

Sample Equivalent Gates 1
Cell Name

Standard Cell
AMI8S(O.8 micron)

MGF0032yyD

470

MGF0064yyD

540

MGF0128yyD

640

MGF0256yyD

740

MGF0512yyD

840

MGF1024yyD

940

Note: 1. Does not include RAM.

5-83

= 1 the

MGFxxxxyyD
Synchronous FIFO

AMERICAN MICROSYSTEMS.INC.

Digital Soft Megacells
Read Timing
RCLK

XRRST

.,.

: T RESU : T REH

:.

x

RE

--------------~

:

.:

y
;TPRCOO:

,~'

/ZZZZZZZT~~~~><,--_V_ALl0--L..:...X--,,-,,-Z--L-Z--L--;
,
'

DOx

FE &AE

------------------------------------~><~-------------

Write Timing
WCLK
T WRSUR'

~
XWRST

.TWRSUF,

~,

=><--+---,,*~~y

..
____________________________: __~i--~----~--~~---:TWRHR :

: TWEH

~

WE

:

TWEH

~

:

To1su :
,~,
,
,
Dlx

" ' ; TWESU

,

'

ZZZZZZZX,-----<-----X/T//

/Z

TpWCFO

:~

~

,

: TOIH

,

FF&AF __________________________________~><~

5-84

:

______________

MGFxxxxyyD
Synchronous FIFO

AMERICAN MICROSYSTEMS, INC.

Digital Soft Megaeells
Register Write Timing
WR

~x~~x~

XxRST

: TXRSU : TXRH

:11(

_:11(

:

____ _______________
~

.:

, TAOSU
: II(

AO - - - - - - - - - - - . , ,

:

TAOH

.:11(

'

•'
X:',

--------------------------~>:<~~--~. ~.----------------~--------: TXDSU : TXDH
II(

Dlx

------------------------------------~X

.'11(

'

•

'

X~----

Timing Characteristics
Symbol

,

Characteristic

Referenced to

T RRSU

read reset set-up

RCLK rising

TRRH
T RESU

read reset hold

RCLK rising

read enable set-up

RCLK rising

TREH

read enable hold

RCLK rising

TpRCDO

read clock to data out valid

RCLK rising

TpRCFO

read clock to flag out valid

RCLK rising

TWRSUR

write reset set-up

WCLK rising

TWRHR

write reset hold

WCLK rising

TWRSUF

write reset set-up

WCLK falling

TWRHF
T WESU

write reset hold

WCLK falling

write enable set-up

WCLK rising

write enable hold

WCLK falling

data in set-up

WCLK falling

data in hold

WCLK falling

TWEH
T o1su
TOIH
TpWCFO
T XRSU

write clock to flag out valid

WCLK rising

either reset set-up

WR rising

TXRH
TAOSU
TAOH

either reset hold

WR rising

AD set-up

WR rising

AD hold

WR rising

Txosu

data in set-up

WR rising

TXOH

data in hold

WR rising

5-85

..-

MGFxxxxyyE
Asynchronous FIFO

AMERICAN MICROSYSTEMS,INC.

Digital son Megaeells
Features

Description

• Dual-port RAM architecture for zero fall-through time

The MGFxxxxyyE FIFO (First In, First Out) builds
asynchronous FIFOs of various sizes. These FIFOs use a
Dual-Port Synchronous Static RAM to allow large FIFO
depth without any fall-through time. This FIFO is available
in the SDX (1.0 u Standard Cell) and AMI8S (0.8 u
Standard Cell) technologies.

• Asynchronous design
• Word width and depth are user definable
• High-performance, Schematic-based megacell
• Uses the ASIC Standard Library for technology
independence

LOGIC SYMBOL
MGFxxxxyyE
XRS
XRT
XW

XFE

XR

The "xxxx" in the name represents the number of words in
the FIFO, and must be a power of 2 between five and ten
(Le. 32 minimum to 1024 maximum). The "yy" is the
number of bits per word and can be from one to any size
needed. For example, a 128 word by 16 bit FIFO would be
named MGF012816E.
Data is written into the FIFO on the rising edge of XW, and
read on the falling edge of XR. Flags are updated on the
rising edge of XW and XR. Flags include XFE, (FI FO
empty not) and XFF (FIFO full not).
The MGFxxxxyyE has a general reset, XRS pin, and a retransmit function enabled by the XRT pin. Both pins are
active low.

DI((yy)-1:0)

DO((yy)-1 :0)

To use the re-transmit function the total number of writes
since the last general reset MUST NOT EXCEED the
number of words in the FIFO.
As long as this condition is met, pulling XRT low will reset
the read counter and all the words written since the
general reset may be read.
Contact the factory for information on specific speeds and
sizes or to have a FIFO built.

Soft Megacells
This logic synthesizer produces a soft megacell schematic
in the ASIC Standard Library and a schematic symbol. The
ASIC Standard Library is technology- and processindependent and is available in both Standard Cells and
Gate Arrays.
A soft megacell is defined only at the schematic level.
Each instance of the megacell has exactly the same
functional definition; however, the physical mask layout is
different for each instance depending on other functions
being used, the place-and-route tools, and process
technology. A soft megacell can be used with other
megacells (including ROM and RAM) and logiC from the
ASIC Standard Library to build a complete system on a
chip.

5-86

MGFxxxxyyE
Asynchronous FIFO

AMERICAN MICROSYSTEMS, INC.

Digital Soft Megaeells
Pin Description
SIGNAL DESCRlpnONS

SlIWAL

TYPE

XRS

I

Asynchronous reset. Resets FIFO when pulsed low.

XRT

I

Activates re-transmit function when pulsed low.

XW

I

Active low write signal. Data appearing on Din will be written into the FIFO on the
rising edge of XW.

XR

I

Active low read signal. Data is read from the FIFO on the falling edge of XR.

DI((yy)-1 :0)

I

Data input into the FIFO.

DO((yy)-1 :0)

0
0
0

XFF
XFE

Data output from the FIFO.
FIFO full flag, active low.
FIFO empty flag, active low.

Sample Equivalent Gates 1
Cell Name

Standard Cell
AMl8S(O.8 micron)

MGF0032yyE

300

MGF0064yyE

360

MGF0128yyE

430

MGF0256yyE

495

MGF0512yyE

560

MGF1024yyE

630

NOTE: 1. Doaa not IaI:UIe RAM.

Read Timing
XR

XRS &XRT

: T RRSUR;

T RRSUF :

:~

:~

=x

><

- - - ' - ,T-R-RH~R :

~:

00)(

)(

~---':-T-R-RH-F-I,
0(

.. :

><

,

VALID

X/z/1277

,~--------~~~~~~~~

,

,

~

: T pRFO :
XFE&XFF ____________________________~>:<~----------------------------------

5-87

MGFxxxxyyE

Asynchronous FIFO

AMERICAN MICROSYSTEMS.ING

Digital son Megacells
Write Timing
XW

TWRSU

:

:~
XRS

:~:
TDIH •

XFE& XFF

------------------------------------~~><~-------------TpWFO

:~:

Timing Characteristics

Symbol
TRRSUR
TRRH

Characteristic

Referenced to

read reset set-up

XR rising

read reset hold

XR rising

read reset set-up

XR falling

TRRHF

read reset hold

XR falling

T pRDO

read clock to data out valid

XR falling

T pRFO

read clock to flag out valid

XR rising

T WRSU

write reset set-up

XW rising

TRRSUF

TWRH

write reset hold

XW rising

T DISU

data in set-up

XW rising

data in hold

XW rising

write clock to flag out valid

XW rising

TDIH
T pWFO

5-88

SECTION 6
MEMORIES

RAD5dwvz
Dual-Port Synchronous Sialic RAM

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Features

edge of the related clock and stay valid until the next
falling edge of the related clock. The address lines are
latched on the falling edges of the clocks. The clocks are
used only to precharge the circuitry and operate the
latches; the memory does not need a refresh signal. The
clocks and all of the other inputs can be held stable
indefinitely with no loss of memory as long as power is
supplied to the RAM.

• Two independent ports access the same core array
• Functionally equivalent to AMI's 0.8 micron Dual-Port
Synchronous Static RAM
• Read-Modify-Write cycle possible
• low standby power when the clocks are stopped
• Separate input and output ports with full parallel access

The dual-port RAM consists of two ports, each port having
its own ClK, Address, Data, Output, Output enable, and
Write/Read control lines. This enables the RAM to have
four basic operations: Write A, Read A, Write B, and Read
B. Each of these operations can be performed
independently of the others. There is no internal address
arbitration.

• 3-State outputs interface internal data buses directly
• Precharged design for faster operation with less silicon
area

FIGURE 1: LOGIC SYMBOL

RAD5dwyz

Write A, Write B: If both ports are writing the same
address, then unknown data will be written to that
address.

ACLK
AOE

Read A, Read B: Ports A and B may read data from
different addresses, or both ports may read
simultaneously from the same address.

AW/R
AT8T

BCLK
BOE

Write A, Read B, or Write B, Read A: If each port is
accessing a different address, then uncorrupted data will
be read/written for both operations. If both ports are
accessing the same address, then the data that is read
will be equal to that currently being written if sufficient time
has elapsed for a valid write to propagate to the read port.
The read will reflect the previous contents of the accessed
address if the new data has not yet been written. For
further information, consult the timing diagrams.

BW/R
BT8T

AA((x-1):O)
ADI ((w-1):O)
BA ((x-1):O)
BDI ((w-1):O)

AO ((w-1):O)
BO ((w-1):O)

Within limits specified below, the user has flexibility in
specifying the logical size of the RAM, including both word
size and the number of address locations. The name of
each RAM indicates the logical size and configuration as
explained here. The "RAD" in the name indicates a dualport RAM. The "s" is a version number. The "d" variable
can be an "A" to indicate always active outputs or an "N" to
indicate 3-state outputs with active low enable. The "w"
represents the word length in a mod-36 alpha-numeric
digit using the integers 1-9 and letters A-Z excluding 0, Q,
and V. For example, "N" represents a word length of 23
and "P" represents a word length of 24. The "yz"
represents a hexadecimal value for the number of address
locations divided by 16. For example, "04" represents 64
address locations.

Notes: 1. AAO is the LSB
2. x represents the number of address lines

General Description
This series of 0.6 micron dual-port RAMs operates within
a power supply voltage range of 4.SV to S.SV, and can
operate down to 2.SV with reduced performance. Contact
the factory for low voltage performance specifications.
These dual-port RAMs can be compiled with 3-state or
always active outputs. When either clock is high, the
corresponding port circuitry is precharged. Read and
write operations occur when the corresponding clock is
low. Port outputs become valid a short time after the falling

6-1

RAD5dwyz
Dual-Pori Synchronous Sialic RAM

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
FIGURE 2: DUAL PORT STATIC RAM BLOCK DIAGRAM

•

BCLK
ACLK

Precharge
&

Latch Control
AT8T
AA((x-1):O)

+
A Address
Buffer

I
I

II

ARow
Decode

--

-1
AwlR

~

A Column
Decode

,I

A Write
Control

I
I

BT8T

+
B Address
Buffer

8 Row
Decode

I
I

BA((x-1):O)

-I
I

B Column
Decode

~
I

B Write
Control

~

Core

~

J

ADI:((W-1):O)

BW/R
BDI((W-1):O)

Out~ut

A Ouwut
• Enable uffer

Latc es
and
3-8tate
Drivers

....

-- -AQ((W-1):O)

BQ((W-1):O)

6-2

B Ou~ut
...
Enable uffer

RAD5dwyz
Dual-Pori Synchronous Sialic RAM

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Address and Word Size Ranges

PARAMETER
Address inputs
Word size (data outputs)

MINIMUM

MAXIMUM

5

10

1

1 bit

32 bits

1 bit
16

Address locations (words)

32

1024 (1K)

Total bits in a core (word size times address locations)

32

32,768 (32K)

INCREMENT

Pin Description and Input Capacitance

SIGNAL

TYPE

32X4

1KX 16

AAi,BAi

I

0.07pF

0.07pF

Address inputs

ACLK,BCLK

I

0.10pF

0.15pF

Clock input

SIGNAL DESCRIPTIONS

AOEN, BOEN

I

0.09pF

0.23pF

3-State output control

AQ, BQ (High-Z)

0

0.07pF

0.07pF

Data outputs

AW/RN, BW/RN

I

0.06pF

0.06pF

Write/read not control

ADli, BDIi

I

0.12pF

0.12pF

Data inputs

Area Relative to a 2 Input Nand
32 x 4 DPRAM: 1236
1K x 16 DPRAM: 37180

Bolt Syntax
AQ(w-1) ... AQ1 AQO BQ(w-1) ... B01 BOO .RAD5dwyz AA(x-1) ... AA1 AAO ACLK ADI(w-1) ... ADI1 ADIO AOEN ATST
AWRN BA(x-1) ... BA1 BAO BCLK BDI(w-1) ... BDI1 BDIO BOEN BTST BWRN;
Note: AAO and BAD are the LSBs for their respective ports.

Power Dissipation:

32 x4

1Kx 16

Typical Cpd (Equivalent Power Dissipation Capacitance)

PARAMETER

27.7pF

262pF

Typical Static IDD Tj=85°C

0.23~A

10.8~A

POWER = (STATIC 100 ) (Voo) + Cpd V00

2f

6-3

RAD5dwvz

~II~

Dual-Pori Synchronous Sialic RAM

AMERICAN MICROSYSTEMS.ING.

AMI6S 0.6 micron CMOS Standard Cells
AC Characteristics: t(EQL)=tdx + Ktdx * EQL
The data in the following examples are specified at 5.0V, Tj=25°C, and typical process performance parameters.
Performance at other operating points may be estimated by use of the Voltage, Process, and Temperature derating
curves. Contact the factory to obtain the AC characteristics and input loading for different logical size RAMs.

32 x4
SYMBOL

tdx (ns)

ktdx (nstEQL)

t(5EQL) (ns)

Min elK period read

tclkr

8.22

0.05

8.47

Min elK period write

tclkw

6.81

Min elK width high

twch

3.23

CHARACTERISTIC

Min elK width low during read

twclr

3.84

Max elK low to Q delay

tpcq

4.99

0.05

5.24

Max OEN to Q delay

toenq

0.96

0.05

1.21

Max OEN to High-Z delay

toenz

0.77

Min address setup time 2

tasu

0.93

Min address hold time 2

tah

1.31

twvw

3.18

tdvw

3.00

Min W/RN high to valid

write 1

Min data in (01) stable to valid write 1
Min elK low to valid

write 1

tcvw

3.58

Min data in (01) hold time after rising edge of ClK
when W/RN is high 1

tdh

0.94

Min W/RN hold time after read

twh

0.29

Min Q hold time

tqh

1.08

Min test setup time

ttsu

0.93

Min test hold time

tth

1.31

Notes: 1. If the W/RN line is high at the same time that the ClK line is low. all three timing terms twvw. tdvw. and tcvw must be met or else invalid data may be written
into the RAM. A Read-Modify-Write cycle may be executed by leaving W/RN low until the read is accomplished, then meeting the twvw, tdvw, and tcvw timing
terms to accomplish a valid write. The Q outputs will change to the value that is written. After a write, the Data in (DI) pins must be held stable until after W/
RN falls or ClK rises.
2. If the timing terms tah and tasu are not met, the potential exists that the data in the RAM will be corrupted. This potential exists not only during the write cycle,
but also during the read cycle. If the tah and/or tasu timing is violated, the simulation model will show an invalid read or write, but it will not show corrupted
data.

6-4

AMERICAN MICROSYSTEMS, INC.

RAD5dwvz
Dual-Pori Synchronous Sialic RAM
AMI6S 0.6 micron CMOS Standard Cells

1Kx 16

SYMBOL

tdx (ns)

ktdx (nslEQU

t(5EQU (ns)

Min ClK period read

tclkr

15.38

0.05

15.63

Min ClK period write

tclkw

14.04

CHARACTERISTIC

Min ClK width high

twch

6.20

Min ClK width low during read

twclr

9.17

Max ClK low to Q delay

tpcq

9.17

0.05

9.42

0.05

1.29

Max OEN to Q delay

toenq

1.04

Max OEN to High-Z delay

toenz

0.82

Min address setup time 2

tasu

1.41

Min address hold time2

tah

1.59

Min W/RN high to valid write'

twvw

8.09

Min data in (DI) stable to valid write 1

tdvw

7.55

Min ClK low to valid write 1

tcvw

7.84

Min data in (DI) hold time after rising edge of ClK
when W/RN is high 1

tdh

1.34

Min W/RN hold time after read

twh

0.37

Min Q hold time

tqh

1.15

Min test setup time

ttsu

1.41

Min test hold time

tth

1.59

Notes:

1. Hthe WIIW line is high at tlte same Ume tItat tlte ClJ( line is low, all tItree U_ terms twvw, tdvw, and tcvw must be met or else invalid data may be wrmen into lite RAM.
ARead-ModlIy-Write cycle may be executed by leaving WIRN low unUI the read is accompUshed, tlten meeURg lite twvw, tdvw, and tcvw Umlng terms to accompDsb a valid
write. T1B Q0\JIpUtS wHI change to lite value tltat is written. Alter a write, lite Data In (m) pins must be held stable until &Her WIRN falls or ell( rises.
2. n tlte UIIIing terms tab and tuu are not met, lite potenUai exists tltat the data In tlte RAM will be corrupted. This poteRUai exists not only during lite write cycle, but also
during lite l'8ad cycle. If the tab and/or tuu bing is violated, the slmulaUOO model wiD show an invalid read or write, but h will not show corrupted data.

Testing Notes:
Testability of memory elements in IC designs must be considered when designing and simulating the circuits. Providing
either direct or multiplexed input and output pins for controlling and observing the memory elements may greatly simplify
the testing of the IC and any debugging to the system. For a more detailed description of the testing of memory elements
in ICs, refer to the RAM testing application notes.

Shadow Write Test Mode
The shadow write feature (ATST and BTST) was incorporated in the design to detect short circuits that may exist
between adjacent A and B port BIT lines. As such, the ATST and BTST circuits were only designed to be used in the test
mode.
To test for shorts between adjacent BIT lines, the core cells must be initialized to some known value (0 or 1). The shadow
write mode operates by selecting a common address to be placed on both A and B ports, then either ATST or BTST is
pulled high (1), thus disabling the row select lines associated with that port. A read operation is then performed by the
port whose row select line is not disabled, simultaneous with a write operation that is performed by the other port. A short
is detected if the read produces corrupted data. In order to test for all possible shorts that could occur between adjacent
BIT lines, both a 0 and a 1 must be written to the address under test (keeping the core value constant).

6-5

RAD5dwvz
Dual-Pori Synchronous Sialic RAM

AMERICAN MICROSYSlEMS,INC.

AM.6S 0.6 micron CMOS Standard Cells
Dual-Port RAM
Timing Diagram
Read Cycle (see notes 5 and 6)

tclkr

ACLK
twch

tah

tasu

AQi

VALID

AW/RN

6-6

RAD5dwrz

Dual-Pori Synchronous Sialic RAM

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Dual-Port RAM
Timing Diagram
Write Cycle 1 (see notes 1,2,5, and 6)

tclkw
twch

tcvw

ACLK
tah

tasu

VALID

6-7

RAD5dwvz

Dual-Pori Synchronous Sialic RAM

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Dual-Port RAM
Timing Diagram
Write Cycle 2 (see notes 1,3, 5, and 6)

tclkw

tcvw
twch
ACLK
..

tasu

. .
..

tah

tdvw

twvw

VALID

AQi

6-8

AMERICAN MICROSYSTEMS, INC.

RAD5dwvz
Dual-Pori Synchronous Sialic RAM
AMI6S 0.6 micron CMOS Standard Cells
Dual-Port RAM
Timing Diagram
Read-Modify-Write Cycle (see notes 4,5, and 6)

tpcq
ACLK

•

AQi

AW/RN

tdvw

1+------+.1

6-9

tdh
~

RAD5dwvz
Dual·Pori Synchronous Sialic RAM

• JtMII®
AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
3-State Control Timing
(see notes 5 and 6)

High

AQi

Impedance

toenq
AOEN

Dual-Port RAM
Timing Diagram
Test Mode (see notes 5, 6, and 7)

ACLK
tth

ttsu

6-10

AMERICAN MICROSYSTEMS, INC.

RAD5dwvz
Dual-Pori Synchronous Sialic RAM
AMI6S 0.6 micron CMOS Standard Cells
TIMING DIAGRAM NOTES

1. During a write cycle, the data that is written becomes valid at the outputs as soon as the tcvw, tdvw, and twvw timing
terms are met. The clock does not have to rise, and the AW/RN signal does not have to fall first.
2. The data hold time in write cycle 1 is referenced to the rising edge of ACLK when AW/RN is held high.
3. The data hold time in write cycle 2 is referenced to the falling edge of AW/RN and is equal to zero.
4. The data hold time in the Read-Modify-Write cycle has to be met only when AW/RN is held high.
5. Note that only the "A" port signals are shown on the timing diagrams. The "8" port functions in a similar manner.
6. AT8T and 8T8T are equal to zero unless they are in the test mode.
7. During the test mode the signal timing for read and write operations is identical to that shown on their respective timing
diagrams.

6-11

6-12

RAS8dW¥z,RAS9dW¥z
Sell-Timed Synchronous Sialic RAM

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Features

General Description

• Self-timed design allows flexibility in clock duty cycle
while maintaining fast cycle time

This series of 0.6 micron standard cell compiled RAMs
operates within a power supply voltage range of 4.5V to
5.5V, and can operate with reduced performance at
supply voltages as low as 2.5V. These RAMs can be built
in two aspect ratios with an option of 3-state or always
active outputs. The self-timed feature of these RAMs
allows flexibility in the clock duty cycle while maintaining
fast cycle times. All timing is relative to the rising edge of
the clock input (ClK). When ClK rises, all inputs are
latched and the READ or WRITE operation occurs. The
RAM will stay in the READ mode and not start
precharging until the READ operation is complete, even if
ClK falls.The outputs become valid a short time after the
rising edge of ClK and stay valid until the next rising edge
of ClK. All of the inputs including ClK can be held stable
indefinitely with no loss of memory as long as power is
supplied to the RAM.

• 10.8 nsec typical cycle time for a 1K x 16 RAM
• 3-State or always active outputs
• low standby power when the clock is stopped
• Separate input and output ports with full parallel access
• Two aspect ratios for optimization
• Precharged design for faster operation with lower power
consumption
• Functionally equivalent to AMI's 0.8 micron Self-Timed
Synchronous Static RAM.

FIGURE 1: LOGIC SYMBOL

RAS8Nwyz

Within limits shown below, the user has flexibility in
specifying the logical size of the RAM, including both word
size and number of address locations. The name of each
RAM indicates the logical size and configuration as
explained here. The ''RAS'' in the name indicates a single
port RAM. The "8" or "9" specifies the aspect ratio with
version 8 having 3 column address lines and version 9
having 4 column address lines. All logical sizes may not
be available in both aspect ratios. The "d" variable in the
name can be an "A" to indicate always active outputs or an
"N" to indicate 3-state outputs with active low enable. The
"w" represents the word length in a mod-36 alpha-numeric
digit using the integers 1-9 and the letters A-Z excluding
0, Q, and V. For example, "N" indicates a word length of 23
and "P" indicates a word length of 24. The "yz" represents
a hexadecimal value for the number of address locations
divided by 16. For example, RAS9AGOC is a 192 x 16
single port RAM with 4 column address lines and always
active outputs.

ClK
OEN
WRT

A ((x-1):0)
Q ((w-1 ):0)

01 ((w-1 ):0)
Note 1: AO is the LSB
Note 2: x represents the number of address lines

Performance data is listed in this data sheet for two
example sizes. To obtain performance data or a
workstation symbol and model for a specific size, contact
your sales representative or the factory.

6-13

RAS8dwYz,RAS9d~

Sell-Timed Synchronous Sialic RAM

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
FIGURE 2: RAM BLOCK DIAGRAM

elK

-

--.

Timing,
Precharge
and Latch Control
/'

..

--

V

-

--.

Row
Decode

1
A ((x-1 ):0)
/

/

-

Address
Latches

---- /
/

...
Core

..

....

1
Column
Decode

/
/

....
/'

01 ((w-1 ):0)
/

WRT

OEN

/

..
~

.
..
~

v

I,

Write Control
and
Latches

-...

Output
Enable
Buffer

..
..
~

Senseamps,
Output Latches,
and
3-State Drivers

--/'

v

"

Q ((w-1):0)

6-14

RAS8d~,RASgdwvz

Sell·Timed Synchronous Sialic RAM

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Address and Word Size Ranges

PARAMETER

MAXIMUM

MINIMUM

INCREMENT

Address Inputs

5

11

1

Address locations (Words)

32

2048 (2K)

16

1 bit

32 bits

1 bit

32

65,536 (64K)

Word Size (Data Outputs)
Total bits in a core (Word size times address locations)

Pin Description and Input Capacitance

SIGNAL

TYPE

32 x4

1Kx 16

Ai

Input

0.05pF

0.06pF

Address Inputs

ClK

Input

0.21 pF

0.24pF

Clock Input

SIGNAL DESCRIPTIONS

Di

Input

0.08pF

0.08pF

Data Inputs

OEN

Input

0.17pF

0.31pF

3-State Output Control

WRT

Input

0.06pF

0.06pF

Write Control

a (High-Z)

Output

0.10pF

0.10pF

Data Outputs

Area relative to a 2 Input Nand
32 x 4: 713
1 K x 16: 18337

Bolt Syntax
Q (w-1) ... 01

00 .RAS8dwyz A(x-1) ... A1

AO ClK DI(w-1) ... 011

010 OEN WRT;

Note: AD is the lSB

Power Dissipation

32 x4

1K x 16

Typical C pd (Equivalent Power DisSipation Capacitance)

19.0pF

131pF

Typical Static IDD Tj=85°C

0.211lA

5.51lA

PARAMETER

2

POWER = (STATIC 100 ) (Voo) + Cpd V00 f

Testing Notes
Testability of memory elements in IC designs must be considered when designing and simulating the circuits. Providing
either direct or multiplexed input and output pins for controlling and observing the memory elements may greatly simplify
the testing of the IC and any debugging to the system. The minimum pattern used to test a RAM should write and read
both a zero and a one to every core bit. In addition, a variable pattern should be used to test for address decode faults
and write disturb problems by writing the entire memory then reading it all back. One example of a variable pattern for
these tests is to write the address value to each location. There are many methodologies for testing RAMs that have test
time versus fault coverage trade-off. For more information on testing RAMs, refer to the AMI Application Note titled
"Testing RAM Elements in IC Designs."

6-15

RAS8dw¥z,RAS9d~

~II~

Sell-Timed Synchronous Sialic RAM

AMERICAN MICROSYSTEMS,INC.

AM.6S 0.6 micron CMOS Standard Cells
AC Characteristics: t(EQL)

=tdx + Ktdx * EQL

The data in the following examples are specified at 5.0V, Tj =250 C, and typical process performance parameters.
Performance at other operating points may be estimated by use of the Voltage, Process, and Temperature derating
curves. Contact the factory to obtain the AC characteristics and input capacitance for different logical sizes of RAMs.

32x4

CHARACTERISTIC
Min elK High to ClK High Cyele Time
Min elK Width low

SYMBOL

tdx (ns)

tcyc

6.32

twel

2.65

Min elK Width High During Read

twchr

1.62

Min elK Width High During Write

twchw

1.45

Min Address Setup Before ClK Rises*

tasu

2.62

Min Address Hold After ClK Rises*

tah

0.0

Min WRT Setup Before ClK Rises*

twsu

2.25

Min WRT Hold After ClK Rises*

twh

0.0

Min Data In Setup Before ClK Rises*

tdsu

1.57

Min Data In Hold After ClK Rises*

tdh

0.0

Min Q Hold After ClK Rises

tqh

1.52

Max ClK Rise to Q Valid

tpcq

3.69

Max OEN Rise to Q High Impedance

toenz

0.51

Max OEN Fall to Q Valid

toenq

0.65

Ktdx (ns/EQL)

t(5EQL) (ns)

0.03

3.84

0.03

0.70

*AMI can reduce the Address, WRT, and/or Data In setup times at the expense of longer corresponding hold times.
Contact the factory if you need a RAM with shorter setup times. If the timing terms tah and tasu are not met, the potential
exists that the data in the RAM will be corrupted. This potential exists not only during the write cycle, but also during a
read cycle. If the tah and/or tasu timing is violated, the simulation model will show an invalid read or write, but it will not
show corrupted data.

6-16

AMERICAN MICROSYSTEMS,ING.

RAS8dwvz,RAS9dwyz
Sell-Timed Synchronous Sialic RAM
AM.6S 0.6 micron CMOS Standard Cells

1Kx 16

SYMBOL

tdx (ns)

Min ClK High to ClK High Cycle Time

tcyc

10.8

Min ClK Width low

twcl

4.19

CHARACTBlISTIC

Min ClK Width High During Read

twchr

1.84

Min ClK Width High During Write

twchw

2.43

tasu

2.99

Min Address Setup Before ClK Rises*
Min Address Hold After ClK Rises*

tah

0.02

Min WRT Setup Before ClK Rises*

twsu

2.25

Min WRT Hold After ClK Rises*

twh

0.0

Min Data In Setup Before ClK Rises*

tdsu

1.26

Min Data In Hold After ClK Rises*

tdh

0.0

Min Q Hold After ClK Rises

tqh

2.10

Max ClK Rise to Q Valid

tpcq

6.52

Max OEN Rise to Q High Impedance

toenz

0.69

Max OEN Fall to Q Valid

toenq

0.81

Ktdx (nslEQU

t(5EQU (ns)

0.04

6.72

0.04

1.01

*AMI can reduce the Address, WRT, and/or Data In setup times at the expense of longer corresponding hold times.
Contact the factory if you need a RAM with shorter setup times. If the timing terms tah and tasu are not met, the potential
exists that the data in the RAM will be corrupted. This potential exists not only during the write cycle, but also during a
read cycle. If the tah and/or tasu timing is violated, the simulation model will show an invalid read or write, but it will not
show corrupted data.

3-State Control Timing

Oi

High
Impedance

OEN

6-17

RAS8dwYz,RAS9dwyz
Sell-Timed Synchronous Sialic RAM

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Read Cycle Timing

tcyc
twcl

elK

twchr

tasu

tah

Ai
twsu

WRT

Oi

6-18

twh

AMERICAN MICROSYSTEMS,INC.

RAS8dwyz,RAS9dwyz
Sell-Timed Synchronous Sialic RAM
AMI6S 0.6 micron CMOS Standard Cells
Write Cycle Timing

tcyc
twcl
twchw

elK
tasu

tah

Ai

twsu

twh

WRT

tdsu

tdh

Di

Oi=Di

Oi

6-19

6-20

RASDdwvz,RASEdwvz
Low-Power Asynchronous Sialic RAM

AMERICAN MICROSYSTEMS,ING

AMIIS 0.1 micron CMOS Standard Cells
Features

General Description

• Asynchronous design for ease of use

This series of 0.6 micron asynchronous static RAMs can
be compiled into over 3500 different logical sizes via
AMI'S proprietary automatic cell compiler system,
ACCOLADE. The ACCOLADE system ensures you
receive the most efficient RAM and accurate timing model
for your specific size of memory by: calculating optimum
transistor sizes for your specific size of RAM; compacting
the layout; calculating power consumption; and simulating
to get the AC characteristics for each memory compiled.
These RAMs can be built in two aspect ratios with an
option of 3-state or always active outputs. These RAMs
have fully asynchronous and static operation. All inputs
can be held stable with no loss of memory as long as
power is supplied to the RAM. Operation is characterized
for a power supply voltage range of 4.5V to 5.5V only.

• 11.4 nsec typical cycle time for a 1K x 16 RAM
• 3-State or always active outputs
• Separate input and output ports with full parallel access
• Two aspect ratios for optimization
• Single column per bit aspect ratio (RASDdwyz) for small
memory applications with low power consumption
• Functionally equivalent to AMI's 0.8 micron low-power
asynchronous RAM

FIGURE 1: LOGIC SYMBOL

RASENwyz

Within limits shown below, the user has flexibility in
specifying the logical size of the RAM, including both word
size and number of address locations. The name of each
RAM indicates the logical size and configuration as
explained here. The ''RAS'' in the name indicates a single
port RAM. The "0" or "E" specifies the aspect ratio with
version 0 having no column address lines and version E
having 3 column address lines. All logical sizes may not
be available in both aspect ratios. The "d" variable in the
name can be an "A" to indicate always active outputs or an
"N" to indicate 3-state outputs with active low enable. The
"w" represents the word length in a mod-36 alpha-numeric
digit using the integers 1-9 and the letters A-Z excluding
0, Q, and V. For example, "N" indicates a word length of 23
and "P" indicates a word length of 24. The "yz" represents
a hexadecimal value for the number of address locations
divided by 2 for RASDdwyz RAMs or divided by 16 for
RASEdwyz RAMs. For example, RASEAGOC is a 192 x
16 single port RAM with 3 column address lines and
always active outputs.

WRTN
OEN

A ((x-1):0)
Q ((w-1):0)
01 ((w-1 ):0)

Notes: 1. AD is the LSB.
2. x represents the number of address lines.

Performance data is listed in this data sheet for two
example sizes. To obtain performance data or a
workstation symbol and model for a specific size, contact
your sales representative or the factory.

6-21

RASDdwyz,RASEdwyz
Low-Power Asynchronous Sialic RAM

~II~

AMERICAN MICROSYSTEMS,ING.

AM.6S 0.6 micron CMOS Standard Cells
FIGURE 3: RASEdwyz BLOCK DIAGRAM
Row
Decode

-

/

.....

/

}
A ((x-1):O)

/
/

-

Core

Address
Buffers

'+
Column
Decode
/

/
j~

./

01 ((w-1):O)
WRTN

OEN

/
/

..
...

Write Control

.

Output
Enable
Buffer

-

-

"

..
/
/

...
Senseamps,
and
3-State Drivers

/'

V

1r
Q ((w-1):O)

6-22

RASDdwYz,RASEdW¥z
Low-Power Asynchronous Sialic RAM

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
Address and Word Size Ranges

PARAMETER

MINIMUM

MAXIMUM

Address inputs

1

10

1

Address locations RASDdwyz (words)

2

128

2

Address locations RASEdwyz (words)

32

1024

16

1-bit

32-bits

1-bit

2

32,768 (32K)

Word size (data outputs)
Total bits in a core (word size times address locations)

INCREMENT

Pin Description and Input Capacitance

SIGNAL

TYPE

32 x4

1K x 16

Ai

Input

0.05pF

0.25pF

SIGNAL DESCRIPTIONS
Address inputs

Dli

Input

0.12pF

0.12pF

Data inputs

OEN

Input

0.05pF

0.05pF

3-State output control

WRTN

Input

0.05pF

0.05pF

Write control

o (High-Z)

Output

0.09pF

0.09pF

Data outputs

AO DI(w-1) ... DI1

DIO

Area relative to a 2-lnput Nand
32 x 4: 637
1K x 16: 20730

Bolt Syntax

a (w-1) ... 01

00 .RASDdwyz A(x-1) ... A1

OEN WRTN;

Note: AD is the LSB.

Power Dissipation

PARAMETER

32 x4

Typical Cpd (Equivalent Power Dissipation Capacitance)
Typical Static IDD (TJ

= 85°C)

1K x 16

4.3 pF

51 pF

0.071lA

6. 53 1lA

POWER = (STATIC 100 ) (Voo) + Cpd V00 2 f

Testing Notes
Testability of memory elements in IC designs must be considered when designing and simulating the circuits. Providing
either direct or multiplexed input and output pins for controlling and observing the memory elements may greatly simplify
the testing of the IC and any debugging to the system. The minimum pattern used to test a RAM should write and read
both a zero and a one to every core bit. In addition, a variable pattern should be used to test for address decode faults
and write disturb problems by writing the entire memory then reading it all back. One example of a variable pattern for
these tests is to write the address value to each location. There are many methodologies for testing RAMs that have test
time versus fault coverage trade-off. For more information on testing RAMs, refer to the AMI Application Note titled
"Testing RAM Elements in IC Designs."

6-23

RASDdwyz,RASEd~

Low-Power Asynchronous Slatic RAM

AMERICAN MICROSYSTEMS,INC.

AM.6S 0.6 micron CMOS Standard Cells
AC Characteristics: t(EQL)

=tdx + Ktdx * EQL

The data in the following examples are specified at 5.0V, TJ = 25°C, and typical process performance parameters.
Performance at other operating points may be estimated by use of the voltage, process, and temperature derating
curves. These RAMs are characterized for operation over a power supply range of 4.5V to 5.5V only. Contact the factory
to obtain the AC characteristics and input capacitance for different logical sizes.

32 x4

CHARACTBUsnc
Max address stable to Q valid

SYMBOL

Idx (ns)

KIdx (nslEQU

t(5EQU (ns)

0.046

10.83

0.046

1.92

tacc

10.6

Min write cycle time

tcycw

13.2

Min read cycle time

tcycr

6.61

tqh

7.12

Min Q hold after address change
Max DEN fall to Q valid

toenq

1.69

Max DEN rise to Q high impedance

toenz

2.00

tasu

2.20

Min address setup before WRTN rises
Min address hold after WRTN falls
Min WRTN low pulse width

tah

1.64

twWRTNI

9.31

Min data in stable before WRTN falls

tdsu

0.0

Min data in hold after WRTN falls

tdh

4.04

Max WRTN fall to Q equals data in

twfqv

4.02

0.046

4.25

Max data in stable to Q equals data in

tdvqv

1.54

0.046

1.77

WRTN fall to Q unknown

twfqx

3.40

6-24

RASDd~,RASEdwYz

AMERICAN MICROSYSTEMS,INC.

Low-Power Asynchronous Sialic RAM
AMI6S 0.6 micron CMOS Standard Cells

1Kx 16

CHARACTERISTIC

SYMBOL

tdx (ns)

Ktdx (ns/EQL)

t(5EQL) (ns)

tacc

12.9

0.049

13.15

Min write cycle time

tcycw

11.4

Min read cycle time

tcycr

11.0

tqh

6.37

Max DEN fall to Q valid

toenq

1.38

0.049

1.63

Max DEN rise to Q high impedance

toenz

1.60

Min address setup before WRTN rises

tasu

1.06

tah

2.74

twWRTNI

7.63

Max address stable to Q valid

Min Q hold after address change

Min address hold after WRTN falls
Min WRTN low pulse width
Min data in stable before WRTN falls

tdsu

0.0

Min data in hold after WRTN falls

tdh

3.70

Max WRTN rise to Q equals data in

twfqv

6.17

0.049

6.42

Max data in stable to Q equals data in

tdvqv

2.61

0.049

2.86

WRTN rise to Q unknown

twfqx

4.56

3-STATE CONTROL TIMING

Qi

High
Impedance

OEN

6-25

RASDd~,RASEd~

Low-Power Asynchronous Sialic RAM

AMERICAN MICROSYSTEMS,ING.

AMI6S 0.6 micron CMOS Standard Cells
Read Cycle Timing

%

1,----- ~,,----:---. _
tcyc

Ai

f:

-..-

Oi

tacc

twfqv
WRT

LOWPWR

Write Cycle Timing

Ai

tasu

twhw

tah

WRT

Oli

LOWPWR

Oi

Oi=Oli
twrqx

NOTE: After writing data to an address, the WRTN has to reblrn high before the next write cycle.

6-26

R04cwxYz,R06c~z

Synchronous ROM

AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
represents a word-length of 24. The "xyz" represents a
hexadecimal value for the number of address locations
divided by 16. For example, ''~OC'' represents 192 address
locations. The columns are represented because the
ROM can be built using different aspect ratios, i.e. rows
vs. columns.

Features
• Low standby power when chip select is stopped
• Buffered or 3-state outputs, 3-state outputs are active
low enable
• Precharged design for faster operation with less silicon
area

Performance data is listed below for an example size. To
obtain data and a workstation installation (symbol and
simulation model) for a particular size, contact the factory.

• Functionally equivalent to AMI's 0.8 micron ROM

FIGURE 1: LOGIC SYMBOL
FIGURE 2: ROM BLOCK DIAGRAM
cs
A(i:O)

R06cwx z
Core

OEN'

a~6~~~

and
3-State'
Drivers

General Description
This series of 0.6 micron ROMs operates within a power
supply voltage range of 4.SV to S.SV and can operate
down to 2.SV with lower performance. The R04 series has
always active outputs. The R06 series has 3-state outputs
with active low Output Enable Not (OEN). The circuit is
precharged when the chip select (CS) line is low. The read
operation occurs when CS is high. The outputs become
valid a short time after the rising edge of CS and stay valid
until the next rising edge of CS.

Q((w-1):O)

*For R04 series, OEN input is removed and output driver is never High-Z.
*For R06 series, as shown.

Within the limits specified below, the user has flexibility in
specifying the logical size of the ROM, including both word
size and number of address locations. Within the name as
shown above, the "cwxyz" represents a five character
sequence assigned to each ROM configuration which
uniquely identifies that particular configuration. The "c"
represents the number of column address lines, which is
limited to three, four, or five. The "w" represents the word
length in a mod-36 alpha-numeric digit using the integers
1-9 and the letters A-Z excluding 0, Q, and V. For
example, "N" represents a word-length of 23 and "P"
6-27

R04c~z,R06c~z

~II~

Synchronous ROM

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
Address and Word Size Ranges

PARAMETER

MINIMUM

MAXIMUM

INCREMENT

6

14

1

1-bit

32-bits

1-bit

Address locations

64

16,384 (16K)

64

Total bits in a core (word size times address locations)

64

524,288 (512K)

Address inputs
Word size (data outputs)

Pin Description and Input Capacitance

SIGNAL

TYPE

256 X 16

Ai

SIGNAL DESCRIPTIONS

I

0.05pF

CS

I

0.33pF

Chip select

OEN

I

0.24pF

3-State output control

o (High-Z)

0

0.12pF

Data outputs

Address inputs

AC Characteristics for 256 x 16

CHARACTERISTIC
Max CS to 0 delay
Max OEN to 0 delay
Max OEN to High-Z delay

SYMBOL

tdx (ns)

ktdx (nstEal)

t(5Eal) (ns)

tpcsq

4.77

0.04

4.97

tpoenq

0.68

0.04

0.88

tpoenz

1.08

Min address setup time

tasu

1.59

Min address hold time

tah

0.12

Min CS width low

twcsl

2.91

Min CS width high

twcsh

4.77

tqh

1.02

Min 0 hold time

Power Dissipation:

PARAMETER
Typical C pd (Equivalent Power Dissipation Capacitance)
Typical Static IDD (TJ = 85°C)

256 x 16
39.4pF
0.4561lA

Area Relative to a 2-lnput Nand- 256 x 16 ROM: 1056
Bolt Syntax:
0(w-1) ... 01 00.R04cwxyz Ai. .. A1 AO CS;
0(w-1) ... Q1 00.R06cwxyz Ai ... A1 AO CS OEN;
Notes: 1. AD is the LSB.
2. POWER = (STATIC IDD) (VDD ) + Cpd VDD 2 f
3. AC characteristics: t(EQL) = tdx + Ktdx * EQL
4. Testability of memory elements must be considered when designing and simulating the circuits. Providing either direct or multiplexed input and output pins for
controlling and observing the memory elements may greatly simplify the testing of the IC and any debugging to the system. For a more detailed description of
the testing of memory elements in ICs refer to the ROM testing application notes.
5. The data in the example above is specified at 5.DV, TJ = 25°C, and typical process parameters. Performance at all other operating points may be estimated by
use of the voltage, process, and temperature derating curves. Contact the factory to obtain the AC characteristics and input capacitance for different logical sizes
of ROMs.
6-28

R04c~z,R06c~z

Synchronous ROM

AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
ROM Timing Diagram

+--+1.------t~lh------.1

tasu
I+------twcsl-------+I

cs

1..------- twcsh - - - - . 1

Q((w-1):O)

Valid

DEN

*High-Z = High impedance Q output.
**For R04 series, OEN is not applicable and the Q((w-1):O) is never High-Z.
For R06 series, as shown.

6-29

SECTION 7
SALES INFORMATION

Terms 01 Sale
AMERICAN MICROSYSTEMS,INC.

AMI6S 0.6 micron CMOS Standard Cells
1. ACCEPTANCE:

amount released hereunder, Seller may allocate production deliveries among its
various customers then under contract for similar goods. The allocation will be
made in a commercially fair and reasonable manner. When allocation has been
made, Buyer will be notified of the estimated quota made available.

THE TERMS OF SALE CONTAINED HEREIN APPLY TO ALL QUOTATIONS
MADE AND PURCHASE ORDERS ENTERED INTO BY THE SELLER. SOME OF
THE TERMS SET OUT HERE MAY DIFFER FROM THOSE IN BUYER'S
PURCHASE ORDER AND SOME MAY BE NEW. THIS ACCEPTANCE IS
CONDITIONAL ON BUYER'S ASSENT TO THE TERMS SET OUT HERE IN LIEU
OF THOSE IN BUYER'S PURCHASE ORDER. SELLER'S FAILURE TO OBJECT
TO PROVISIONS CONTAINED IN ANY COMMUNICATION FROM BUYER
SHALL NOT BE DEEMED A WAIVER OF THE PROVISIONS OF THIS
ACCEPTANCE. ANY CHANGES IN THE TERMS CONTAINED HEREIN MUST
SPECIFICALLY BE AGREED TO IN WRITING BY AN OFFICER OF THE SELLER
BEFORE BECOMING BINDING ON EITHER THE SELLER OR THE BUYER. All
orders or contracts must be approved and accepted by the Seller at its home office.
These terms shall be applicable whether or not they are attached to or enclosed
with the products to be sold or sold hereunder. Prices for the items called for hereby
are not subject to audit.

6. PATENTS:
The Buyer shall hold the Seller harmless against any expense or loss resulting from
infringement of patents, trademarks, or unfair competition arising from compliance
with Buyer's designs, specifications, or instructions. The sale of products by the
Seller does not convey any license, by implication, estoppel, or otherwise, under
patent claims covering combinations of said products with other devices or
elements.
Except as otherwise provided in the preceding paragraph, the Seller shall defend
any suit or proceeding brought against the Buyer, so far as based on a claim that
any product, or any part thereof, furnished under this contract constitutes an
infringement of any patent of the United States, if notified promptly in writing and
given authority, information, and assistance (at the Seller's expense) for defense of
same, and the Seller shall pay all damages and costs awarded therein against the
Buyer. In case said product, or any part thereof, is, in such suit, held to constitute
infringement of patent, and the use of said product is enjoined, the Seller shall, at
its own expense, either procure for the Buyer the right to continue using said
product or part, replace same with non-infringing product, modify it so it becomes
non-infringing, or remove said product and refund the purchase price and the
transportation and installation costs thereof. In no event shall Seller's total liability
to the Buyer under or as a result of compliance with the provisions of this paragraph
exceed the aggregate sum paid by the Buyer for the allegedly infringing product.
The foregoing states the entire liability of the Seller for patent infringement by the
said products or any part thereof. THIS PROVISION IS STATED IN LIEU OF ANY
OTHER EXPRESSED, IMPliED, OR STATUTORY WARRANTY AGAINST
INFRINGEMENT AND SHALL BE THE SOLE AND EXCLUSIVE REMEDY FOR
PATENT INFRINGEMENT OF ANY KIND ..

2. PAYMENT:
(a) Unless otherwise agreed, all invoices are due and payable thirty (30) days from
date of invoice. No discounts are authorized. Shipments, deliveries, and
performance of work shall at all times be subject to the approval of the Seller's
credit department and the Seller may at any time decline to make any shipments or
deliveries or perform any work except upon receipt of payment or upon terms and
conditions or security satisfactory to such department.
(b) If, in the judgment of the Seller, the financial condition of the Buyer at any time
does not justify continuation of production or shipment on the terms of payment
originally specified, the Seller may require full or partial payment in advance and, in
the event of the bankruptcy or insolvency of the Buyer or in the event any
proceeding is brought by or against the Buyer under the bankruptcy or insolvency
laws, the Seller shall be entitled to cancel any order then outstanding and shall
receive reimbursement for its cancellation charges.

7. INSPECTION:

(c) Each shipment shall be considered a separate and independent transaction,
and payment therefore shall be made accordingly. If shipments are delayed by the
Buyer, payments shall become due on the date when the Seller is prepared to
make shipment. If the work covered by the purchase order is delayed by the Buyer,
payments shall be made based on the purchase price and the percentage of
completion. Products held for the Buyer shall be at the risk and expense of the
Buyer.

Unless otherwise specified and agreed upon, the material to be furnished under
this order shall be subject to the Seller's standard inspection at the place of
manufacture. If it has been agreed upon and specified in this order that Buyer is to
inspect or provide for inspection at the place of manufacture, such inspection shall
be so conducted as to not interfere unreasonably with Seller's operations, and
consequent approval or rejection shall be made before shipment of the material.
Notwithstanding the foregoing, if, upon receipt of such material by Buyer, the same
shall appear not to conform to the contract, the Buyer shall immediately notify the
Seller of such conditions and afford the Seller a reasonable opportunity to inspect
the material. No material shall be returned without Seller's consent. Seller's Return
Material Authorization form must accompany such returned material.

3. TAXES:
Unless otherwise provided herein, the amount of any present or future sales,
revenue, excise or other taxes, fees, or other charges of any nature, imposed by
any public authority (national, state, local or other) applicable to the products
covered by this order, or the manufacture or sale thereof, shall be added to the
purchase price and shall be paid by the Buyer, or in lieu thereof, the Buyer shall
provide the Seller with a tax exemption certificate acceptable to the taxing
authority.

8. LIMITED WARRANTY:
The Seller warrants that the products to be delivered under this purchase order will
be free from defects in material and workmanship under normal use and service.
Seller's obligations under this Warranty are limited to replacing or repairing or
giving credit for, at its option, at its factory, any of said products which shall, within
one (1) year after shipment, be returned to the Seller's factory of origin,
transportation charges prepaid, and which are, after examination, disclosed to the
Seller's satisfaction to be thus defective. THIS WARRANTY IS EXPRESSED IN
LIEU OF ALL OTHER WARRANTIES, EXPRESS, STATUTORY, OR IMPLIED,
INCLUDING THE IMPliED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE, AND OF ALL OTHER OBLIGATIONS
OR LIABILITIES ON THE SELLER'S PART, AND IT NEITHER ASSUMES NOR
AUTHORIZES ANY OTHER PERSON TO ASSUME FOR THE SELLER ANY
OTHER LIABILITIES IN CONNECTION WITH THE SALE OF THE SAID
ARTICLES. This Warranty shall not apply to any of such products which shall have
been repaired or altered, except by the Seller, or which shall have been subjected
to misuse, negligence, accident, or improper storage. The aforementioned
provisions do not extend the original warranty period of any product which has
either been repaired or replaced by Seller.

4. F.O.B. POINT:
All sales are made F.O.B. point of shipment. Seller's title passes to Buyer, and
Seller's liability as to delivery ceases upon making delivery of material purchased
hereunder to carrier at shipping point, the carrier acting as Buyer's agent. All claims
for damages must be filed with the carrier. Shipments will normally be made by
Parcel Post, United Parcel Service (UPS), Air Express, or Air Freight. Unless
specific instructions from Buyer specify which of the foregoing methods of shipment
is to be used, the Seller will exercise his own discretion.

5. DELIVERY:
Shipping dates are approximate and are based upon prompt receipt from Buyer of
all necessary information. In no event will Seller be liable for any re-procurement
costs, nor for delay or non-delivery, due to causes beyond its reasonable control
including, but not limited to, acts of God, acts of civil or military authority, priorities,
fires, strikes, lockouts, slow-downs, shortages, factory or labor conditions, yield
problems, and inability due to causes beyond the Seller's reasonable control to
obtain necessary labor, materials, or manufacturing facilities. In the event of any
such delay, the date of delivery shall, at the request of the Seller, be deferred for a
period equal to the time lost by reason of the delay. In the event Seller's production
is curtailed for any of the above reasons so that Seller cannot deliver the full

It is understood that if this order calls for the delivery of semiconductor devices
which are not finished and fully encapsulated, then no warranty, statutory, express
or implied, including the implied warranty of merchantability and fitness for a
particular purpose, shall apply. All such devices are sold as is where is.

7-1

Terms 01 Sale
AMERICAN MICROSYSTEMS, INC.

AMI6S 0.6 micron CMOS Standard Cells
9. PRODUCTS NOT WARRANTED BY SELLER:

(i) Seller shall own all copyrights in or relating to each product developed by
Seller whether or not such product is developed under contract with a third party.

The second paragraph of Paragraph 6, Patents, and Paragraph 8, Limited
Warranty, above apply only to integrated circuits of Seller's own manufacture. IN
THE CASE OF PRODUCTS OTHER THAN INTEGRATED CIRCUITS OF
SELLER'S OWN MANUFACTURE, SELLER MAKES NO WARRANTIES,
EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FREEDOM FROM PATENT
INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. Such products
may be warranted by the original manufacturer of such products. For further
information regarding the possible warranty of such products, contact Seller.

G) The design, development or manufacture by Seller of product for a
specific customer shall not be deemed to produce a work made for hire and shall
not give to the customer any copyright interest in the product or any interest in all
or any portion of the mask works relating to the product. In addition, all such rights
shall remain the property of Seller. Seller shall retain all rights in mask work on any
circuit designed using Seller's standard cell library and Seller shall retain all rights
in mask work to the non-personalized portion of any gate array developed for
Buyer.
(k) Engineering work performed by Seller of any kind, including but not
limited to, development of test programs, shall only be on a best efforts basis.

10. PRICE ADJUSTMENTS:
Seller's unit prices are based on certain material costs. These materials include,
among other things, gold, packages and silicon. Adjustments shall be as follows:

14. GOVERNMENT CONTRACT PROVISIONS:
If Buyer's original purchase order indicates by contract number that it is placed
under a government contract, only the following provisions of the current Federal
Acquisition Regulations are applicable, in accordance with the terms thereof, with
an appropriate substitution of parties, as the case may be - i.e., "Contracting
Officer" shall mean "Buyer," "Contractor" shall mean "Seller," and the term
"Contract" shall mean this order:

(a) Gold. The price at the time of shipment shall be adjusted for increases in the
cost of gold in accordance with Seller's current Gold Price Adjustment List. This
adjustment will be shown as a separate line item on each invoice.
(b) Other Materials. In the event of significant increases in the cost of other
materials, Seller reserves the right to renegotiate the unit prices. If the parties
cannot agree on such increase, then neither party shall have any further obligations
with regard to the delivery or purchase of any units not then scheduled for
production.

52.202-1 Definitions; 52.232-11 Extras; 52.212-9 Variation in Quantity;
52.232-23 Assignment of Claims; 52.228-2 Additional Bond Security;
52.224-11 Certain Communist Areas; 52.222-4 Contract Work Hours and
Safety Standards Act-Overtime Compensation; 52.222-20 Walsh-Healey
Public Contracts Act, if this Order exceeds $10,000; 52.222-26 Equal
Opportunity; 52.203-1 Officials Not to Benefit; 52.203-5 Covenant Against
Contingent Fees; 52.249-1 Termination for Convenience of the
Government if this Order does not exceed $500,000 (only to the extent that
Buyer's contract is terminated for the convenience of the government);
52.246-1 Contractor Inspection Requirements; 52.247-1 Commercial Bills
of Lading; 52.222-35 Affirmative Action Viet Nam Veterans if this Order
exceeds $10,000; 52.222-36 Affirmative Action Handicapped Workers, if
this Order exceeds $2,500; 52.222-1 Notice to the Government of Labor
Disputes; 52.215-1 Examination of Records by Comptroller General;
52.220-3 Utilization of Labor Surplus Area Subcontracting Concerns.

11. VARIATION IN QUANTITY:
If this order calls for a product not listed in Seller's current catalog, or for a product
which is specially programmed for Buyer, it is agreed that Seller may ship a
quantity which is five percent (5%) more or less than the ordered quantity and that
such quantity shipped will be accepted and paid for in full satisfaction of each
party's obligation hereunder for the quantity order.

12. CONSEQUENTIAL DAMAGES:
In no event shall Seller be liable for special, incidental or consequential damages.

13. GENERAL:
(a) The validity, performance and construction of these terms and all sales
hereunder shall be governed by the laws of the State of California.
(b) The Seller represents that with respect to the production of articles and/
or performance of the services covered by this order it will fully comply with all
requirements of the Fair Labor Standards Act of 1938, as amended, WilliamsSteiger Occupational Safety and Health Act of 1970, Section 202 of Executive
Order 11246, as amended and where applicable, and other affirmative action
requirements made applicable to this order by federal statute, rule or regulation.
(c) The Buyer may not unilaterally make changes in the drawings, designs
or specifications for the items to be furnished hereunder without Seller's prior
consent.
(d) Except to the extent provided in Paragraph 14, below, this order is not
subject to cancellation or termination for convenience.
(e) If Buyer is in breach of its obligations under this order, Buyer shall
remain .liable for all unpaid charges and sums due to Seller and will reimburse
Seller for all damages suffered or incurred by Seller as a result of Buyer's breach.
The remedies provided herein shall be in addition to all other legal means and
remedies available to Seller.
(f) Buyer acknowledges that all or part of the products purchased
hereunder may be manufactured and/or assembled at any of Seller's facilities
domestic or foreign.
(g) Unless otherwise agreed in a writing signed by both Buyer and Seller,
Seller shall retain title to and possession of all tooling of any kind (including but not
limited to masks and pattern generator tapes) used in the production of products
furnished hereunder.
(h) Buyer, by accepting these products, certifies that he will not export or reexport the products furnished hereunder unless he complies fully with all laws and
regulations of the United States relating to such export or re-export, including but
not limited to the Export Administration Act of 1979 and the Export Administration
Regulations of the U.S. Department of Commerce.

7-2

Domestic
Sales Representatives

AMERICAN MICROSYSTEMS, INC.

Current as of October 14, 1996

Alabama

Colorado

Illinois

Maryland

STG (Southeast Technical
Group, Inc.)
101 Washington Street
Suite 6
Huntsville, AL 35801
(205) 534-2376
(205) 534-2384 (FAX)

Thorn Luke Sales, Inc.
Colorado Division
9000 E. Nichols Ave.
Suite 240
Englewood, CO 80112
(303) 649-9717
(303) 649-9719 (FAX)

Microtex, Inc.
1870 N. Roselle Rd. Suite 107
Schaumburg, IL 60195
(847) 885-8200
(847) 885-8210 (FAX)

S. J. Chesapeake
9525 Hallhurst Rd.
Baltimore, MD 21236
(410) 256-0090
(410) 256-0095 (FAX)

Indiana

MassachuseHs

Arizona

Connecticut

Thorn Luke Sales, Inc.
9700 North 91 st Street
Suite A-200
Scottsdale, AZ 85258
(602) 451-5400
(602) 451-0172 (FAX)

Datcorn Inc.
One Evergreen Avenue
Hamden, CT 06518
(203) 288-7005
(203) 281-4233 (FAX)

Skyline Sales & Associates,
Inc.
103 3rd Southwest Ave.
Suite 203
Carmel, IN 46032
(317) 587-1320
(317) 587-1322 (FAX)

ATS-Advanced Tech Sales
Park Place West
Suite 102
348 Park Street
North Reading, MA 01864
(508) 664-0888
(508) 664-5503 (FAX)

California
Centaur Corporation
17802 Skypark Circle
Suite 100 & 101
Irvine, CA 92714
(714) 261-2123
(714) 261-2905 (FAX)
26635 W. Agoura Rd.
Suite 100 & 101
Calabasas, CA 91302
(818) 878-5800
(818) 878-5818 (FAX)
3914 Murphy Canyon Road
SuiteA125
San Diego, CA 92123
(619) 278-4950
(619) 278-0649 (FAX)
12 Associates
9198 Greenback Ln.
Suite 214
Orangevale, CA 95662
(916) 989-0843
(916) 989-2841 (FAX)
12 Incorporated
3255-1 Scott Blvd.,
Suite 102
Santa Clara, CA 95054
(408) 988-3400
(408) 988-2079 (FAX)

Florida

511 Airport N. Office Park
Fort Wayne, IN 46825
(219) 489-4992
(219) 489-6194 (FAX)

Micro Concepts, Inc.
111 W. Magnolia Ave.
Suite 203
Longwood, FL 32750
(407) 830-8889
(407) 834-0649 (FAX)

Iowa
C. H. Horn & Associates
4403 First Ave., S.E.
Suite 411
Cedar Rapids, IA 52402
(319) 393-8703
(319) 393-7224 (FAX)

2300 Palm Beach Lake Blvd.
Suite 308-E
West Palm Beach, FL 33409
(561) 686-5084
(561) 686-0562 (FAX)

Georgia

Kansas

STG (Southeast Technical
Group, Inc.)
3500 Parkway Lane
Suite 420
Norcross, GA 30092
(404) 416-6336
(404) 416-6433 (FAX)

Midtec Associates, Inc.
11900 West 87th St. Parkway
Suite 220
Lenexa, KS 66215
(913) 541-0505
(913) 541-1179 (FAX)

Kentucky

Idaho

Skyline Sales & Associates,
Inc.
845 Lane Allen Road
Suite 13
Lexington, KY 40504
(606) 276-5061
(606) 276-5142 (FAX)

First Source of Idaho, Inc.
10451 W. Garverdale Court,
#209
Boise, 10 83704
(208) 378-4680
(208) 323-9386 (FAX)

7-3

Michigan
Skyline Sales &
Associates, Inc.
19137 Surrey Lane
Northville, MI 48167
(810) 449-1437
(810) 449-1438 (FAX)

Minnesota
Vector Design Technology
3101 Old Hiway 8, Suite 202
Roseville, MN 55113
(612) 631-1334
(612) 631-1329 (FAX)

Missouri
Midtec Associates, Inc.
55 Westport Plaza, Suite 614
St. Louis, MO 63146
(314) 275-8666
(314) 275-8859 (FAX)

Domestic
Sales Representatives

AMERICAN MICROSYSTEMS,ING.

Current as of October

14, 1996

New Jersey

Ohio

Utah

Washington

S. J. Mid-Atlantic, Inc.
131-0 Gaither Drive
Mount Laurel, NJ 08054
(609) 866-1234
(609) 866-8627 (FAX)

Great Lakes Group, Inc.
7760 Olentangy River Road
Suite 119
Columbus, OH 43235-1374
(614) 885-6700
(614) 885-6701 (FAX)

First Source of Utah
8341 South 700 East
Sandy, UT 84070
(801) 561-1999
(801) 561-4525 (FAX)

Quad Rep, Inc.
375 118th Ave. SE #110
Bellevue, WA 98005
(206) 453-5100
(206) 646-8775 (FAX)

Thorn Luke Sales, Inc.
2081 Pinnacle Terrace Way
#301
Salt Lake City, UT 84121
(801) 947-7631
(801) 947-7632 (FAX)

Wisconsin

New York
L-MAR Associates, Inc.
440 Perington Hills
Office Park
Fairport, NY 14450
(716) 425-9100
(716) 425-9120 (FAX)
S-J Metro
265 Sunrise Highway
Rockville Centre, NY 11570
(516) 536-4242
(516) 536-9638 (FAX)

North Carolina
STG (Southeast Technical
Group, Inc.)
1650 Green Farm Road
Huntersville, NC 28078
(704) 896-3121
(704) 892-3931 (FAX)

33610 Solon Road
Suite 5
Solon, OH 44139
(216) 349-2700
(216) 349-2701 (FAX)

OregOn

Virginia
s. J. Chesapeake

Quad Rep, Inc.
17020 SW Upper
Boones Ferry Rd, #202
Portland, OR 97224
(503) 620-8320
(503) 639-4023 (FAX)

900 S. Washington St.
Suite 307
Falls Church, Virginia 22046
(703) 533-2233
(703) 533-2236 (FAX)

Texas

4032 Providence Road
Hayes, VA 23072
(804) 642-1515
(804) 642-8851 (FAX)

OM Associates, Inc.
9020 I Capital of Texas Hwy.
Suite 335
Austin, TX 78759
(512) 794-9971
(512) 794-9987 (FAX)

725 Royal Anne Lane,
Suite 303
Raleigh, NC 27615
(919) 847-6995
(919) 847-6035 (FAX)

20405 S.H. 249, Suite 170
Houston, TX 77070
(713) 376-6400
(713) 376-6490 (FAX)

700 N. Arendell Ave.
Zebulon, NC 27597
(919) 269-5589
(919) 269-5670 (FAX)

690 West Campbell Road
Suite 150
Richardson, TX 75080
(972) 690-6746
(972) 690-8721 (FAX)

12006 Yucca Drive
Richmond, VA 23236
(804) 378-9170
(804) 378-9171 (FAX)

7-4

Microtex, Inc.
S. 22 W. 22660 Broadway
Suite 4A
Waukesha, WI 53186
(414) 542-5352
(414) 542-7934 (FAX)
(809) 781-2020 (FAX)

International
Sales Representatives

AMERICAN MICROSYSTEMS,INC.

Current as of October 14, 1996

INTERNATIONAL EUROPE
NORTH AMERICA

DENMARK

WESTERN CANADA

T elefonvej 8
DK-2860 Soborg, Denmark
(45) 3957-7110
(45) 3957-7112 (FAX)

J-Squared
Technologies, Inc.
4170 Still Creek Drive., #200
Burnaby, B.C. V5C 6C6
Canada
(604) 473-4666
(604) 473-4699 (FAX)
2723-37th Ave. NE, #206
Calgary, Alberta T1 Y 5R8
Canada
(403) 291-6755
(403) 291-6757 (FAX)

UNITED KINGDOM
Sabre Advanced
Microelectronics Ltd.
Sussex House, Unit 11
The Pines Trading Estate
Broad Street
Guildford, Surrey
GU33BH
United Kingdom
44-1483-35444
44-1483-35888 (FAX)

Berendsen Electronics

FINLAND
Berendsen Electronics
10 Virkatie
P.O. Box 154 Fin
FIN-01511 Vantaa, Finland
(35)808254200
(35) 808275280 (FAX)

FAR EAST
CHINA
Dynatek Electronics Limited
No. 15 Daniwan
Haidian District
Beijing, China
(86-1) 264-5294
(86-1) 264-4527 (FAX)

FRANCE
Unirep

EASTERN CANADA
J-Squared
Technologies, Inc.
300 March Rd. Suite 501
Kanata, Ontario
Canada, K2K 2E2
(613) 592-9540
(613) 592-7051 (FAX)
3395 American Drive
Building 306, Unit 2
Mississauga, Ontario
Canada L4V IT4
(905) 672-2030
(905) 672-2047 (FAX)
100 Alexis Nihon
Suite 960
Ville St-Laurent, QC
Canada H4M-2PS
(514) 747-1211
(514) 747-9824 (FAX)

z. I. de la Bonde
1 bis, rue Marcel Paul Bat. B
91300 Massy, France
33-1-6953-8470
33-1-6920-0061 (FAX)

Room 104, Building 6, Block B,
No. 78, Long Kou West Road
Tien He District
Guangzhou, China
(86-20) 754-9961
(86-20) 754-9661 (FAX)

GERMANY
Hartmut Thiele
Industrievertretungen GmbH
Lubminer Pfad 3
D-13503 Berlin
Germany
49-30-436-2011
49-30-431-5501 (FAX)

Room 703, Golden Lustre
Hotel,
59 Chun Feng Road,
Shenzhen, China
(86-755) 225-2640-703
(86-755) 225-2640-703 (FAX)

Hartmut Senking
Matthias-Claudius- Str. 17
24558 Henstedt - U.,
Germany
(49) 4193-89-2400

HONG KONG
Dynatek Electronics Limited
Unit 701-704, 7/F.,
Hong Leong Industrial Complex
4 Wang Kwong Road,
Kowloon Bay, Hong Kong
(852) 2796-6689
(852) 2796-6109 (FAX)

ITALY
FG Microdesign S.R.L.
Via O. Simoni 5
40011 Anzola Emilia
Bologna, Italy
39-51-732095
39-51-732491 (FAX)

INDIA
Hynetic International
175 Calvert Drive
Suite 5202
Cupertino, CA 95014
(408) 973-0996
(408) 973-8574 (FAX)

NORWAY
Berendsen Electronics
Konowsgt. 8
P.O. Box 9376 Gronland
N-0135, Oslo, Norway
(47) 2208-8500
(47) 2208-8590 (FAX)

7-5

JAPAN
AMI-Japan
20-16 Hikawadai
Nerima-Ku 3-Chome
Tokyo 179, Japan
81 -3-5399-7831
81-3-5399-7834 (FAX)

SINGAPORE
Serial System PTE ltd.
11 , Jalan Mesin
#06-00 Standard Industrial
Building
Singapore 1336
65-2800200
65-2861812 (FAX)

TAIWAN
Serial Semiconductor
Company ltd.
8F, No 11, Lane 3
Tsao Twei, Shen Keng HSiang
Taipei Hsien,
Taiwan R.O.C.
886-2-662-0088
886-2-662-7958 (FAX)

MIDDLE EAST
ISRAEL
Vectronics ltd.
6 Maskit St'
Herzlia Business Park
Bldg B', Herzlia B'
46120 Israel POB 2024
972-9-556-070
972-9-556-508 (FAX)

AMI
Company OfIices

AMERICAN MICROSYSTEMS,ING.

Current as of October 14, 1996

CORPORATE
OFFICES
IDAHO
WORLDWIDE
HEADQUARTERS
2300 Buckskin Rd.
Pocatello, ID 83201
(208) 233-4690
(208) 234-6796 (FAX)

JAPAN
JAPAN ENERGY
CORPORATION
10-1 Toranomon 2-Chome
Minato-ku
Tokyo 105 Japan
81-3-5573-6543
81-3-5573-6777 (FAX)

INTERNATIONAL
OFFICES

UNITED STATES
HEADQUARTERS
STANDARD PRODUCTS
DIVISION
1651 Alvin Rieken Dr.
Pocatello, ID 83201
(208) 233-4690
(208) 234-6760 (FAX)

AMI-JAPAN
20-16 Hikawadai
Nerima-Ku 3-Chome
Tokyo 179, Japan
81-3-5399-7831
81-3-5399-7834 (FAX)

GERMANY - 3

GERMANY - 2

AMI GmbH CORPORATE
HEADQUARTERS
Bertolt-Brecht-Allee 22
D-01309 Dresden,
Germany
49-351-31-99-1500
49-351-31-99-1501 (FAX)

AMI GmbH
Europe Marketing & Sales
Bertolt-Brecht-Allee 22
D-01309 Dresden,
Germany
49-351-31 -99-1506
49-351-31-99-1507 (FAX)

JAPAN -1, 3

NORTH AMERICAN
OFFICES
California, North - 2, 3
2055 Gateway Place
Suite 410
San Jose, CA 95110
(408) 452-8550
(408) 452-7602 (FAX)

California, South - 2, 3
13891 Newport Avenue
Suite 150
Tustin, CA 92680
(714) 573-8199
(714) 573-8190 (FAX)

Georgia - 2
3500 Parkway Lane
Suite 420
Norcross, GA 30092
(770) 729-8860
(770) 729-8868 (FAX)

Indiana - 2
511 Airport North Office Park
Fort Wayne, IN 46825
(219) 489-7372
(219) 489-6194 (FAX)

Minnesota .. 2
5275 Edina Industrial
Boulevard
Suite 218
Edina, MN 55439
(612) 893-1214
(612) 893-0888 (FAX)

New Jersey - 2
210 Summit Avenue, Bldg. A
Montvale, NJ 07645
(201) 930-1350
(201) 930-9820 (FAX)

OregOn - 2, 3
7340 S.W. Hunziker
Suite 210
Portland, OR 97223
(503) 639-1655
(503) 639-3397 (FAX)

Texas - 2
5068 W. Plano Parkway
Suite 199
Plano, TX 75093
(972) 248-7770
(972) 248-2681 (FAX)

MassachuseHs - 2
420 Bedford Street
Suite 120
Lexington Office Park
Lexington, MA 02173
(617) 861-6530
(617) 861-8871 (FAX)

Copyright©1996
American Microsystems, Inc.

1 Sales Personnel
2 Sales & Application Engineering Personnel
3 Technical Services Center
4 Application Engineering Personnel Only
Devices sold by AMI are covered by the warranty and patent indemnification
provisions appearing in its Terms of Sale only. AMI makes no warranty, express,
statutory, implied or by description, regarding the information set forth herein or
regarding the freedom of the described devices from patent infringement. AMI
makes no warranty of merchantability or fitness for any purposes. AMI reserves the
right to discontinue production and change specifications and prices at any time

and without notice. AMI's products are intended for use in commercial applications.
Applications requiring extended temperature range, unusual environmental
requirements, or high reliability applications, such as military, medical life-support or
life-sustaining equipment, are specifically not recommended without additional
processing by AMI for such applications.

American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, 10 83201, (208) 233-4690, FAX (208) 234-6796
7-6
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date                     : 2017:07:13 18:38:01-08:00
Modify Date                     : 2017:07:13 19:09:24-07:00
Metadata Date                   : 2017:07:13 19:09:24-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:eb999ed4-1ff4-7b47-97e6-025218464488
Instance ID                     : uuid:69db8c5d-05da-f744-9d83-9ac27c155354
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 460
EXIF Metadata provided by EXIF.tools

Navigation menu