1996_Analog_Devices_High_Speed_Design_Techniques 1996 Analog Devices High Speed Design Techniques

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HIGH SPEED DESIGN TECHNIQUES
+15V

+

u------'1I1\1\r--

V1N

=

4Vp-p

=

Vo
40Vp-p

VOUT=

40Vp-p

1 :2

TRANSFORMER

1kQ

+5V

INPUT o--"'---;:---;--'VVr::::;;:;;;;;;;;~-

ANALOG
WDEVICES

11IIIIIIII

HIGH SPEED
DESIGN TECHNIQUES
PREFACE
HIGH SPEED OP AMPS
HIGH SPEED OP AMP APPLICATIONS
RF/IF SUBSYSTEMS
HIGH SPEED SAMPLING AND HIGH SPEED ADCs

HIGH SPEED ADC APPLICATIONS
HIGH SPEED DACs AND DDS SYSTEMS
HIGH SPEED HARDWARE DESIGN TECHNIQUES
INDEX

HIGH SPEED DESIGN TECHNIQUES

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HIGH SPEED DESIGN TECHNIQUES

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Analog Devices Sales Offices. Call your local sales office and request
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•

In the U.S.A. and Canada, call800-ANALOGD, (800-262-5643).
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HIGH SPEED
DESIGN TECHNIQUES

ANALOG
DEVICES

HIGH SPEED DESIGN TECHNIQUES

ACKNOWLEDGMENTS
Thanks are due the many technical staff members of Analog Devices in Engineering and
Marketing who provided invaluable inputs during this project. Particular credit is due the
individual authors whose names appear at the beginning of their material.
Special thanks go to Adolfo Garcia, Walter G. Jung, and Ed Grokulsky for thoroughly
reviewing the material for content and accuracy.
Linda Grimes Brandon of Brandon's WordService prepared the new illustrations and typeset
the text. Ernie Lehtonen of the Analog Devices' art department supplied many camera-ready
drawings. Judith Douville compiled the index, and printing was done by R. R. Donnelleyand
Sons, Inc.

Walt Kester
1996

Copyrig ht @ 1996 by Analog Devices, Inc.
Printed in the United States of America
All rights reserved. This book, or parts thereof, must not be reproduced in any form without
permission of the copyright owner.
Information furnished by Analog Devices, Inc., is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices, Inc., for its use.
Analog Devices, Inc., makes no representation that the interconnections of its circuits as
described herein will not infringe on existing or future patent rights, nor do the descriptions
contained herein imply the granting of licenses to make, use, or sell equipment constructed in
accordance therewith.
SpeCifications are subject to change without notice.

ISBN-O-916550-17-6

HIGH SPEED
DESIGN TECHNIQUES
PREFACE
SECTION 1
HIGH SPEED OP AMPS
•

Voltage Feedback Op Amps

•

Current Feedback Op Amps

•

Effects of Feedback Capacitance

•

High-Speed Current-to-Voltage Converters, and
the Effects of Inverting Input Capacitance

•

Noise Comparisons between Voltage Feedback
Op Amps and Current Feedback Op Amps

•

DC Characteristics of High Speed Op Amps

SECTION 2
HIGH SPEED OP AMP APPLICATIONS
•

Optimizing the Feedback Network for Maximum
Bandwidth Flatness in Wideband CFB Op Amps

•

Driving Capacitive Loads

•

Cable Drivers and Receivers

•

A High Performance Video Line Driver

•

Differential Line Drivers/Receivers

HIGH SPEED DESIGN TECHNIQUES

•

High Speed Clamping Amplifiers

•

Single-Supply/Rail-to-Rail Considerations

•

High Speed Video Multiplexing with Op Amps Using
Disable Function

•

Video Programmable Gain Amplifier

•

Video Multiplexers and Crosspoint Switches

•

High Power Line Drivers and ADSL

•

High Speed Photodiode Preamps

SECTION 3
RF/IF SUBSYSTEMS

•
•
•
•
•
•
•

Dynamic Range Compression
LinearVCAs
Log/Limiting Amplifiers
Receiver Overview
Multipliers, Modulators, and Mixers
Modulation / Demodulation
Receiver Subsystems

SECTION 4
HIGH SPEED SAMPLING AND HIGH SPEED ADCs
•

Fundamentals of High Speed Sampling

•

Baseband Antialiasing Filters

•

Undersampling

•

Antialiasing Filters in Undersampling Applications

•

Distortion and Noise in an Ideal N-bit ADC

•

Distortion and Noise in Practical ADCs

•

High Speed ADC Architectures

SECTION 5
HIGH SPEED ADC APPLICATIONS
•

Driving ADC Inputs for Low Distortion and Wide
Dynamic Range

•

Applications of High Speed ADCs in CCD Imaging

•

High Speed ADC Applications in Digital Receivers

SECTION 6
HIGH SPEED DACs AND DDS SYSTEMS
•

Introduction to DDS

•

Aliasing in DDS Systems

•

125MSPS DDS System (AD9850)

HIGH SPEED DESIGN TECHNIQUES

•

DDS Systems as ADC Clock Drivers

•

Amplitude Modulation in a DDS System

•

The AD9831/AD9832 Complete DDS System

•

Spurious Free Dynamic Range Considerations in
DDS Systems

•

High Speed Low Distortion DAC Architectures

•

Improving SF DR Using Sample-and-Hold Deglitchers

•

High Speed Interpolating DACs

•

QPSK Signal Generation Using DDS (AD9853)

SECTION 7
HIGH SPEED HARDWARE DESIGN TECHNIQUES

•
•
•
•
•
•
•

INDEX

•
•

Analog Circuit Simulation
Prototyping Analog Circuits
Evaluation Boards
Grounding in High Speed Systems
Power Supply Noise Reduction and Filtering
Power Supply Regulation/Conditioning
Thermal Management
EMIIRFI Considerations
Shielding Concepts

HIGH SPEED
DESIGN TECHNIQUES
PREFACE
HIGH SPEED OP AMPS
HIGH SPEED OP AMP APPLICATIONS
RFJIF SUBSYSTEMS
HIGH SPEED SAMPLING AND HIGH SPEED ADCs
HIGH SPEED ADC APPLICATIONS
HIGH SPEED DACs AND DDS SYSTEMS
HIGH SPEED HARDWARE DESIGN TECHNIQUES
INDEX

HIGH SPEED DESIGN TECHNIQUES

PREFACE

HIGH SPEED DESIGN TECHNIQUES

PREFACE

PREFACE:
HIGH SPEED DESIGN TECHNIQUES
High speed integrated circuits,
both analog, digital, and mixed-signal
are used in all types of electronic equipment today. This book examines high
speed linear ICs both from the theoretical and practical application point of
view.
Figure P.1 shows some of the
typical applications for high speed
integrated circuits by market segment.
Many applications can be filled using
standard linear IC products, while
others may be better served with
specially designed chipsets (see Figure
P.2).
All of these high speed linear ICs
depend upon a broad base of high speed
core competencies shown in Figure P.3.
Analog Devices has been a leader in
real-world signal processing for over 30
years and has the required expertise in
each critical competency area. Regardless.ofhow complex or highly integrated mixed-signal ICs may become,
there is no escaping the requirement
for these basic building blocks.

An understanding of these building
blocks is required for the customer to
successfully specify, select, and apply
new high speed products at the system
level. While a detailed knowledge of the
internal circuits is not required, an
overall understanding of the operation
of the devices is critical to success.
This book is not intended to be a
system design manual. Instead, it
covers the theory and application of
many high speed analog signal processing building blocks such as amplifiers,
ADCs, DACs, etc. System applications
are presented when they are of broad
general interest or illustrate emerging
market trends.
The proper application of high
speed devices also requires a thorough
knowledge of good hardware design
techniques, such as simulation,
prototyping, layout, decoupling, and
grounding. The last section in the book
focuses on these issues as well as EMI
and RFI design considerations.

P -1

HIGH SPEED DESIGN TECHNIQUES

HIGH SPEED PRODUCTS: TYPICAL APPLICATIONS
VIDEO

IMAGING

COMMUNICATIONS

INSTRUMENTATION

+ Cameras

+ Medical

+ Oscilloscopes

.+ Mixing

+ Scanners

+ Distribution

+ Copiers

+ Video
Conferencing
+ Displays

+ Lasers

+ Cellular:
Broadband
Narrowband
+ Direct Broadcast
Satellite
+ Hybrid Fiber Coax
(HFC)
+ CATV

+CCD

+ADSUHDSL

+ Spectrum
Analyzers
+ Frequency
Synthesizers
+ Automatic Test
Equipment
+Data Acquisition

+ MPEG Systems +RadarlSonar + Data Recovery and
Retiming
Figure P.1

ADI HIGH SPEED INTEGRATED I CHIPSET SOLUTIONS
•

Cellular Communications: GSM, DECT,
AMPS, PCS, etc. (Handsets and Basestations)

•

ADSUHDSL

•

CCD Imaging

•

Video Signal Processing (MPEG, etc.)

•

Fiber Optic and Disk Drive Data Recovery

•

Direct Broadcast Satellite Receivers

•

High Speed Modems

•

Multimedia Sound and Video Processing
Figure P.2

P-2

PREFACE

CORE COMPETENCIES: "DC TO LIGHT"
•

Amplifiers:
Op Amps, VCAs, PGAs, Log Amps,
Sample-and-Hold Amplifiers

•

Switches and Multiplexers

•

Analog-to-Digital Converters (ADCs)

•

Digital-to-Analog Converters (DACs)

•

Analog Signal Processing
Multipliers, RMS-DC Converters, etc.

•

RFIIF Signal Processing

•

DSP

Figure P.3

P-3

HIGH SPEED DESIGN TECHNIQUES

SECTION 1
HIGH SPEED OP AMPS
•

Voltage Feedback Op Amps

•

Current Feedback Op Amps

•

Effects of Feedback Capacitance

•

High-Speed Current-to-Voltage Converters,
and the Effects of Inverting Input Capacitance

•

Noise Comparisons between Voltage Feedback
Op Amps and Current Feedback Op Amps

•

DC Characteristics of High Speed Op Amps

HIGH SPEED DESIGN TECHNIQUES

HIGH SPEED OPERATIONAL AMPLIFIERS

SECTION!
IDGH SPEED OPERATIONAL AMPLIFIERS
Walt Kester
INTRODUCTION
High speed analog signal processing
applications, such as video and communications, require op amps which have
wide bandwidth, fast settling time, low
distortion and noise, high output current, good DC performance, and operate
at low supply voltages. These devices
are widely used as gain blocks, cable
drivers, ADC pre-amps, current-tovoltage converters, etc. Achieving
higher bandwidths for less power is
extremely critical in today's portable
and battery-operated communications
equipment. The rapid progress made
over the last few years in high-speed
linear circuits has hinged not only on
the development of IC processes but
also on innovative circuit topologies.
The evolution of high speed processes by
using amplifier bandwidth as a function
of supply current as a figure of merit is
shown in Figure 1.1. (In the case of
duals, triples, and quads, the current
per amplifier is used). Analog Devices
BiFET process, which produced the

AD712 and OP249 (3MHz bandwidth,
3mA current), yields about 1MHz per
rnA. The CB (Complementary Bipolar)
process (AD817, AD847, AD811, etc.)
yields about lOMHzlmA of supply
current. Ft's of the CB process PNP
transistors are about 700MHz, and the
NPN's about 900MHz.
The latest generation complementary
bipolar process from Analog Devices is
a high speed dielectrically isolated
process called XFCB (eXtra Fast
Complementary Bipolar). This process
(2-4 GHz Ft matching PNP and NPN
transistors), coupled with innovative
circuit topologies allow op amps to
achieve new levels of cost-effective
performance at astonishing low quiescent currents. The approximate figure
of merit for this process is typically
lOOMHzlmA, although the AD8011 op
amp is capable of300MHz bandwidth
on 1mA of supply current due to its
unique two-stage current-feedback
architecture.

1- 1

HIGH SPEED DESIGN TECHNIQUES

AMPLIFIER BANDWIDTH VERSUS SUPPLY CURRENT
FOR ANALOG DEVICES' PROCESSES
1000

-

300

:E

100

AD8011e

N

J:

-

-AD847
AD817

J:

l-

e

::e

30

<
£Xl

10

z

~\\'~

3

~«~~"

\~y..",~~

AD712
OP249
e741

1
0.3

1

3

10

30

SUPPLY CURRENT (PER AMPLIFIER), rnA

Figure 1.1

In order to select intelligently the
correct op amp for a given application,
an understanding of the various op amp
topologies as well as the tradeoffs
between them is required. The two

VOLTAGE FEEDBACK

(VFB) Op AMPs

A voltage feedback (VFB) op amp is
distinguished from a current feedback
(CFB) op amp by circuit topology. The
VFB op amp is certainly the most
popular in low frequency applications,
but the CFB op amp has some advantages at high frequencies. We will
discuss CFB in detail later, but first the
more traditional VFB architecture.
Early IC voltage feedback op amps
were made on "all NPN" processes.

1-2

most widely used topologies are voltage
feedback (VFB) and current feedback
(CFB). The following discussion treats
each in detail and discusses-the similarities and differences.

These processes were optimized for
NPN transistors, and the "lateral" PNP
transistors had relatively poor performance. Lateral PNPs were generally
only used as current sources, level
shifters, or for other non-critical functions. A simplified diagram of a typical
VFB op amp manufactured on such a
process is shown in Figure 1.2.

HIGH SPEED OPERATIONAL AMPLIFIERS

VOLTAGE FEEDBACK (VFB) OP AMP
DESIGNED ON AN "ALL NPN" IC PROCESS
+vs--.---------4-----------------------------~

12T

!

"LATERAL"PNP
i

= v·gm

)

o

+
"gm"

STAGE

~s --~----------------~--------------~

.
•

q
gm=l c · kT

•

i
gm
vQUT=-,- =v·-,-@HF
Jeo Cp
Jeo Cp

Figure 1.2

The input stage is a differential pair
consisting of either a bipolar pair (Q1,
Q2) or a FET pair. This "gm" (transconductance) stage converts the smallsignal differential input voltage, v, into
a current, i, i.e., it's transfer function is
measured in units of conductance, lin,
(or mhos). The small signal emitter
resistance, r e' is approximately equal
to the reciprocal of the small-signal gm'
The formula for the small-signal gm of
a single bipolar transistor is given by
the following equation:

lute temperature. At +25°C, VT =
kT/q= 26mV (often called the Thermal
Voltage, VT)'
As we will see shortly, the amplifier

=~=~(IC)=~(ITJ
or
re kT
kT 2·'

unity gain-bandwidth product, fu' is
equal to gm/21tCp, where the capacitance Cp is used to set the dominant
pole frequency. For this reason, the tail
current, IT,is made proportional to
absolute temperature (PTAT). This
current tracks the variation in r e with
temperature thereby making gm independent of temperature. It is relatively
easy to make Cp reasonably constant
over temperature.

IT is the differential pair tail current,
IC is the collector bias current (IC =
IT"2), q is the electron charge, k is
Boltzmann's constant, and T is abso-

The output of one side of the gm stage
drives the emitter of a lateral PNP
transistor (Q3). It is important to note
that Q3 is not used to amplify the
signal, only to level shift, i.e., the signal
current variation in the collector of Q2
appears at the collector of Q3. The
output collector current of Q3 develops

gm

1-3

HIGH SPEED DESIGN TECHNIQUES

a voltage across high impedance node
A Cp sets the dominant pole of the
frequency response. Emitter follower
Q4 provides a low impedance output.

equal to the small-signal current, i,
multiplied by the impedance of the
parallel combination ofRrr and Cpo
Figure 1.3 shows a simple model for the
single-stage amplifier and the corresponding Bode plot. The Bode plot is
constructed on a log-log scale for convenience.

The effective load at the high impedance node A can be represented by a
resistance, Rrr, in parallel with the
dominant pole capacitance, Cpo The
small-signal output voltage, Vout, is

MODEL AND BODE PLOT FOR A VFB OP AMP

NOISE GAIN = G

=1+~
R1

R2

fO = 21t RTCp

AO

fu= ~
21tCp
fCl

1 +~
R1

=

=~

fu
1 + B.L

G

R1

t------~
I
I

fu
I

I

I

I

= UNITY GAIN FREQUENCY

---------L---I--~f
f Cl = CLOSED LOOP BANDWIDTH

Figure 1.3

The low frequency breakpoint, fo,is
given by:

the above equation for fu, assuming
I Vout I =I v I :

f _
1
o - 27tRTCp.

f

Note that the high frequency response
is determined solely by gm and Cp:

We can use feedback theory to derive
the closed-loop relationship between the
circuit's signal input voltage, vin,and
it's output voltage, Vout:

Vout

gm

=

gm

27tCp.

=V· jroCp .

The unity gain-bandwidth frequency,
fu, occurs where IVout I=Iv I . Solving
1-4

u

Vout
vin

=

1+R2
R1

(
l

1+ jaCP 1+
gm

R2')
R1

HIGH SPEED OPERATIONAL AMPLIFIERS

At the op amp 3dB closed-loop bandwidth frequency, fch the following is
true:
21tfCI CP( R2)
gm
1+ R1 = 1, and hence

I = C dv dv = SR SR = .!.
dt' dt
'
C

fcl=~[ 1
1

2nCp 1+ ~ ,or

f I
c

=

f

SR = IT 12 = 50~ = 25V 1 JlS
Cp
2pF
.
The full-power bandwidth (FPBW) of
the op amp can now be calculated from
the formula:

u

R2
1+-'
Rl

This demonstrates a fundamental
property ofVFB op amps: The closedloop bandwidth multiplied by the
closed-loop gain is a constant, i.e., the
VFB op amp exhibits a constant gainbandwidth product over most of the
usable frequency range.
Some VFB op amps (called de-compensated) are unstable at unity gain and
are designed to be operated at some
minimum amount of closed-loop gain.
For these op amps, the gain-bandwidth
product is still relatively constant over
the region of allowable gain.
Now, consider the following typical
example: IT = 100pA, Cp =2pF. We
find that:
IT/2

50~

gm = VT = 26mV
gm
21tCp

f u =--=

Now, we must consider the large-signal
response of the circuit. The slew-rate,
SR, is simply the total available charging current, IT/2, divided by the dominant pole capacitance, Cpo For the
example under consideration,

1

= 5200

FPBW

= SR

21tA

= 25V 1 JlS = 4MHz
21t·lV
"

where Ais the peak amplitude of the
output signal. If we assume a 2V peakto-peak output sinewave (certainly a
reasonable assumption for high speed
applications), then we obtain a FPBW
of only 4MHz, even though the smallsignal unity gain-bandwidth product is
153MHz! For a 2V p-p output sinewave,
distortion will begin to occur much
lower than the actual FPBW frequency.
We must increase the SR by a factor of
about 40 in order for the FPBW to
equal 153MHz. The only way to do this
is to increase the tail current, IT,of the
input differential pair by the same
factor. This implies a bias current of
4mA in order to achieve a FPBW of
160MHz. We are assuming that Cp is a
fIXed value of 2pF and cannot be lowered by design.

1
=153MHz
21t(520)(2.10-12 )

1-5

HIGH SPEED DESIGN TECHNIQUES

VFB OP AMP BANDWIDTH AND SLEW RATE CALCULATION
•

Assume that IT = 100J,lA, Cp

•

gm

Ic

•
•

fu =

50J.lA

=2pF

1

= VT = 26mV = 5200
~ = 153MHz
2n Cp

Slew Rate

=SR =ITCp12 = 25V I J.l s

BUT FOR 2V PEAK-PEAK OUTPUT (A

•
•

•

=1V)

FPBW = SR = 4MHz
2n A
Must increase IT to 4mA to get FPBW

=160MHzII

Reduce gm by adding emitter degeneration resistors

Figure 1.4

In practice, the FPBW of the op amp
should be approximately 5 to 10 times
the maximum output frequency in
order to achieve acceptable distortion
performance (typically 55-80dBc @ 5 to
20MHz, but actual system requirements vary widely).
Notice, however, that increasing the
tail current causes a proportional
increase in gm and hence fu' In order to
prevent possible instability due to the
large increase in fu, gm can be reduced
by inserting resistors in series with the
emitters of Q1 and Q2 (this technique,
called emitter degeneration, also serves
to linearize the gm transfer function
and lower distortion).

1-6

A major inefficiency of conventional
bipolar voltage feedback op amps is
their inability to achieve high slew
rates without proportional increases in
quiescent current (assuming that Cp is
fIxed, and has a reasonable minimum
value of 2 or 3pF). This of course is not
meant to say that high speed op amps
designed using this architecture are
defIcient, it's just that there are circuit
design techniques available which allow
equivalent performance at lower quiescent currents. This is extremely important in portable battery operated
equipment where every milliwatt of
power dissipation is critical.

HIGH SPEED OPERATIONAL AMPLIFIERS

VFB Op AMPs DESIGNED ON COMPLEMENTARY BIPOLAR PROCESSES

With the advent of complementary
bipolar (CB) processes having high
quality PNP transistors as well as

NPNs, VFB op amp configurations such
as the one shown in the simplified
diagram (Figure 1.5) became popular.

VFB OP AMP USING TWO GAIN STAGES
01

OUTPUT
BUFFER

Figure 1.5

Notice that the input differential pair
(Ql, Q2) is loaded by a current mirror
(Q3 and Dl). We show Dl as a diode for
simplicity, but it is actually a diodeconnected PNP transistor (matched to
Q3) with the base and collector connected to each other. This simplification
will be used in many of the circuit
diagrams to follow in this section. The
common emitter transistor, Q4, provides a second voltage gain stage. Since
the PNP transistors are fabricated on a
complementary bipolar process, they
are high quality and matched to the
NPNs and suitable for voltage gain.
The dominant pole of the amplifier is

set by Cp, and the combination of the
gain stage,Q4, and Cp is often referred
to as a Miller Integrator. The unity-gain
output buffer is usually a complementary emitter follower.
The model for this two-stage VFB op
amp is shown in Figure 1.6. Notice that
the unity gain-bandwidth frequency, fu,
is still determined by the gm of the
input stage and the dominant pole
capacitance, Cpo The second gain stage
increases the DC open-loop gain, but
the maximum slew rate is still limited
by the input stage tail current: SR =
IT/Cp.

1-7

HIGH SPEED DESIGN TECHNIQUES

MODEL FOR TWO STAGE VFB OP AMP

Vin

R1

R2

•

gm
fu=--

•

21tCp

fu
fCL=-"R2
1+R1

IT

•

SR=-Cp

Figure 1.6

The two-stage topology is widely used
throughout the IC industry in VFB op
amps, both precision and high speed.
Another popular VFB op amp architecture is the folded cascode as shown in
Figure 1.7. An industry-standard video
amplifier family (the AD847) is based
on this architecture. This circuit takes
advantage of the fast PNPs available
on a CB process. The differential signal
currents in the collectors of Ql and Q2

1-8

are fed to the emitters of a PNP cascode
transistor pair (hence the term folded
cascode). The collectors of Q3 and Q4
are loaded with the current mirror, Dl
and Q5, and Q4 provides voltage gain.
This single-stage architecture uses the
junction capacitance at the high-impedance node for compensation (and some
variations of the design bring this node
to an external pin so that additional
external capacitance can be added).

HIGH SPEED OPERATIONAL AMPLIFIERS

AD847-FAMILY FOLDED CASCaDE SIMPLIFIED CIRCUIT
.....-----u CCOMP

VB lAS

TCSTRAY
Q5

7

ACGROUNO

01

Figure 1.7

With no emitter degeneration resistors
in Ql and Q2, and no additional external compensating capacitance, this
circuit is only stable for high closed-loop
gains. However, unity-gain compensated versions of this family are available which have the appropriate
amount of emitter degeneration.
The availability of JFETs on a CB
process allows not only low input bias
current but also improvements in the
tradeoff which must be made between
gm and IT found in bipolar input
stages. Figure 1.8 shows a simplified
diagram of the AD845 16MHz op amp.

JFETs have a much lower gm per rnA
of tail current than a bipolar transistor.
This allows the input tail current
(hence the slew rate) to be increased
without having to increase Cp to maintain stability. The unusual thing about
this seemingly poor performance of the
JFET is that it is exactly what is
needed on the input stage. For a typical
JFET, the value ofgm is approximately
Is/IV (Is is the source current), rather
than Id26mV for a bipolar transistor,
i.e., about 40 times lower. This allows
much higher tail currents (and higher
slew rates) for a given gm when JFETs
are used as the input stage.

1-9

HIGH SPEED DESIGN TECHNIQUES

AD845 BiFET 16MHz OP AMP SIMPLIFIED CIRCUIT
01

Q6

Q4

+v--~

Figure 1.8

A New VFB Op Amp Architecture for "Current-on-Demand"
Performance, Lower Power, and Improved Slew Rate
Until now, op amp designers had to
make the above tradeoffs between the
input gm stage quiescent current and
the slew-rate and distortion performance. Analog Devices' has patented a
new circuit core which supplies currenton-demand to charge and discharge the

1 -10

dominant pole capacitor, Cp, while
allowing the quiescent current to be
small. The additional current is proportional to the fast slewing input signal
and adds to the quiescent current. A
simplified diagram of the basic core cell
is shown in Figure 1.9.

HIGH SPEED OPERATIONAL AMPLIFIERS

"QUAD-CORE" VFB gm STAGE FOR CURRENT-ON-DEMAND
+Vs

-Vs

Figure 1.9

The quad-core (gm stage) consists of
transistors Ql, Q2, Q3, and Q4 with
their emitters connected together as
shown. Consider a positive step voltage
on the inverting input. This voltage
produces a proportional current in Ql
which is mirrored into Cpl by Q5. The
current through Ql also flows through
Q4 and Cp2. At the dynamic range
limi t, Q2 and Q3 are correspondingly
turned off. Notice that the charging and
discharging current for Cpl and Cp2 is
not limited by the quad core bias current. In practice, however, small current-limiting resistors are required
forming an "H" resistor network as
shown. Q7 and Q8 form the second gain
stage (driven differentially from the
collectors of Q5 and Q6), and the output
is buffered by a unity-gain complementary emitter follower.

others pending), as well as the circuits
which establish the quiescent bias
currents (not shown in the diagram). A
number of new VFB op amps using this
proprietary configuration have been
released and have unsurpassed high
frequency low distortion performance,
bandwidth, and slew rate at the indicated quiescent current levels (see
Figure 1.10). The AD9631, AD8036,
and AD8047 are optimized for a gain of
+1, while the AD9632, AD8037, and
AD8048 for a gain of +2. The same
quad-core architecture is used as the
second stage of the AD8041 rail-to-rail
output, zero-volt input single-supply op
amp. The input stage is a differential
PNP pair which allows the input common-mode signal to go about 200mV
below the negative supply rail. The
AD8042 and AD8044 are dual and
quad versions of the AD8041.

The quad core configuration is patented
(Roy Gosser, U.S. Patent 5,150,074 and
1 - 11

HIGH SPEED DESIGN TECHNIQUES

"QUAD-CORE" TWO STAGE XFCB VFB OP AMPS
AC CHARACTERISTICS VERSUS SUPPLY CURRENT
PART #

ISY I AMP

BANDWIDTH

SLEW RATE

DISTORTION

AD9631/32

17mA

320M Hz

1300V/J,ls

-72dBc@20MHz

ADB036/37
Clamped

20mA

240MHz

1200V/J,ls

-72dBc@20MHz

ADB047/4B

5.BmA

250MHz

750V/J,ls

-66dBc@5MHz

ADB041 (1)

5.2mA

160MHz

160V/J,ls

-69dBc@10MHz

ADB042 (2)

5.2mA

160MHz

200V/J,ls

-64dBc@10MHz

ADB044 (4)

2.75mA

150MHz

170V/J,ls

-75dBc@5MHz

ADB031 (1)

O.75mA

BOMHz

30V/J,ls

-62dBc@1 MHz

ADB032 (2)

O.75mA

BOMHz

30V/J,ls

-62dBc@1MHz

Number in ( ) indicates single, dual, or quad

Figure 1.10

CURRENT FEEDBACK (CFB)Op AMps
We will now examine the current
feedback (CFB) op amp topology which
has recently become popular in high
speed op amps. The circuit concepts
were introduced many years ago,
however modern high speed complementary bipolar processes are required
to take full advantage of the archi tecture.
It has long been known that in bipolar
transistor circuits, currents can be
switched faster than voltages, other
things being equal. This forms the basis
of non-saturating emitter-coupled logic
(ECL) and devices such as currentoutput DACs. Maintaining low impedances at the current switching nodes
helps to minimize the effects of stray
capacitance, one of the largest detriments to high speed operation. The
1 -12

current mirror is a good example of how
currents can be switched with a minimum amount of delay.
The current feedback op amp topology
is simply an application of these fundamental principles of current steering. A
simplified CFB op amp is shown in
Figure 1.11. The non-inverting input is
high impedance and is buffered directly
to the inverting input through the
complementary emitter follower buffers
Q1 and Q2. Note th-at the inverting
input impedance is very low (typically
10 to lOOn), because of the low emitter
resistance. In the ideal case, it would be
zero. This is a fundamental difference
between a CFB and a VFB op amp, and
also a feature which gives the CFB op
amp some unique advantages.

HIGH SPEED OPERATIONAL AMPLIFIERS

SIMPLIFIED CURRENT FEEDBACK (CFB) OP AMP
r-------4iI---------

+Vs

+

~------~-+------~--~s

R2

R1

Figure 1.11

The collectors of Q1 and Q2 drive
current mirrors which mirror the inverting input current to the high impedance node, modeled by RT and Cpo
The high impedance node is buffered by
a complementary unity gain emitter
follower. Feedback from the output to
the inverting input acts to force the
inverting input current to zero, hence
the term Current Feedback. (In the
ideal case, for zero inverting input
impedance, no small signal voltage can
exist at this node, only small signal
current).

I

Consider a positive step voltage applied
to the non-inverting input of the CFB
op amp. Q1 immediately sources a
proportional current into the external
feedback resistors creating an error
current which is mirrored to the high
impedance node by Q3. The voltage
developed at the high impedance node
is equal to this current multiplied by

the equivalent impedance. This is
where the term transimpedance op amp
originated, since the transfer function is
an impedance, rather than a unitless
voltage ratio as in a traditional VFB op
amp.
Note that the error current is not
limited by the input stage bias current,
i.e., there is no slew-rate limitation in
an ideal CFB op amp. The current
mirrors supply current-on-demand from
the power supplies. The negative feedback loop then forces the output voltage
to a value which reduces the inverting
input error current to zero.
The model for a CFB op amp is shown
in Figure 1.12 along with the corresponding Bode plot. The Bode plot is
plotted on a log-log scale, and the openloop gain is expressed as a
transimpedance, T(s), with units of
ohms.
1 - 13

HIGH SPEED DESIGN TECHNIQUES

CFB OP AMP MODEL AND BODE PLOT

R2

1
27t R2Cp ( 1 + RO + RO )
R1
R2

IT(s)1
(0)

1

FOR
RO« R1
RO« R2

27t R2Cp

fel

I
R2

Figure 1.12

The finite output impedance of the
input buffer is modeled by Ro. The
input error current is i. By applying the
principles of negative feedback, we can
derive the expression for the op amp
transfer function:
Vout _

I+R2
Rl

Vin - 1+ jroCPR2(1+ Ro + ROJ.
R2 R1
At the op amp 3db closed-loop bandwidth frequency, fcl' the following is
true:
Ro ROJ =1
21tfclCpR21+-+(
R2 Rl
.
Solving for fcl:

1 -14

f _

1

cl - 21tCpR2(RO
ROJ .
1 + - + -"
R2 Rl
For the condition Ro « R2 and Rl, the
equation simply reduces to:
f

_
1
cl - 21tCpR2

Examination of this equation quickly
reveals that the closed-loop bandwidth
of a CFB op amp is determined by the
internal dominant pole capacitor, Cp,
and the external feedback resistor R2,
and is independent of the gain-setting
resistor, Rl. This ability to maintain
constant bandwidth independent of
gain makes CFB op amps ideally suited
for wideband programmable gain
am plifiers.

HIGH SPEED OPERATIONAL AMPLIFIERS

Because the closed-loop bandwidth is
inversely proportional to the external
feedback resistor, R2, a CFB op amp is
usually optimized for a specific R2.
Increasing R2 from it's optimum value
lowers the bandwidth, and decreasing it
may lead to oscillation and instability
because of high frequency parasitic
poles.
The frequency response of the AD8011
CFB op amp is shown in Figure 1.13 for
various closed-loop values of gain (+1,
+2, and +10). Note that even at a gain

of + 10, the closed loop bandwidth is still
greater than 100MHz. The peaking
which occurs at a gain of +1 is typical of
wideband CFB op amps when used in
the non-inverting mode and is due
primarily to stray capacitance at the
inverting input. The peaking can be
reduced by sacrificing bandwidth and
using a slightly larger feedback resistor. The AD8011 CFB op amp represents state-of-the-art performance, and
key specifications are shown in Figure
1.14.

AD8011 FREQUENCY RESPONSE
G +1, +2, +10

=

+5

+4

Vs ~ +5V OIR ±5V I
+3 - VOUT= 200mVp-p

fg

+2

I

~

+1

~

0

--~

~

~
z

~~
~

G=+10 L
RF= 5000

~ -1

-2

~

y

.1"\

G=+2
RF= 11<0-

f-

~",.L

~

'\
\

~

\
\
\ \

-3
-4

-s

,

1

G =+1 •
RF=11 f

UNSTABLE

Figure 1.20

In the case of the CFB op amp (Figure
1.20b), the same analysis is used,
except that the open-loop transimpedance gain, T(s), is used to construct the
Bode plot. The definition of noise gain
(for the purposes of stability analysis)
for a CFB op amp, however, must be
redefined in terms of a current noise
source attached to the inverting input
(see Figure 1.21). This current is re-

fleeted to the output by an impedance
which we defme to be the "current noise
gain" ofa CFB op amp:
"CURRENT NOISE GAIN"
.. RO+Z2(1+

~~)

1 - 21

HIGH SPEED DESIGN TECHNIQUES

CURRENT "NOISE GAIN" DEFINITION
FOR CFB OP AMP FOR USE IN STABILITY ANALYSIS

T(s)

Z2

VOUT
CURRENT

Z2

"NOISE GAIN"

=

VOUT
i

Z1

Figure 1.21

Now, return to Figure 1.20b, and
observe the CFB current noise gain plot.
At low frequencies, the CFB current
noise gain is simply R2 (making the
assumption that Ro is much less than
Zl or Z2. The first pole is determined
by R2 and C2. As the frequency continues to increase, C2 becomes a short
circuit, and all the invertng input
current flows through Ro (refer back to
Figure 1.21).
The CFB op amp is normally optimized
for best performance for a fixed feedback resistor, R2. Additional poles in
the transimpedance gain, T(s), occur at
frequencies above the closed loop bandwidth, fcl' (set by R2). Note that the
intersection of the CFB current noise

1 - 22

gain with the open-loop T(s) occurs
where the slope of the T(s) function is
12dB/octave. This indicates instability
and possible oscillation.
It is for this reason that CFB op amps
are not suitable in configurations which
require capacitance in the feedback loop,
such as simple active integrators or
lowpass filters. They can, however, be
used in certain active filters such as the
Sallen-Key configuration shown in
Figure 1.22 which do not require capaci tance in the feedback network.
VFB op amps, on the other hand, make
very flexible active filters. A multiple
feedback 20MHz lowpass filter using
the AD8048 is shown in Figure 1.23.

HIGH SPEED OPERATIONAL AMPLIFIERS

EITHER CFB OR VFB OP AMPS CAN BE USED IN
THE SALLEN-KEY FILTER CONFIGURATION

R2 FIXED FOR CFB OP AMP

Figure 1.22

MULTIPLE FEEDBACK 20MHz LOWPASS FILTER
USING THE AD8048 VFB OP AMP

Figure 1.23
1 - 23

HIGH SPEED DESIGN TECHNIQUES

In general, the amplifier should have a
bandwidth which is at least ten times
the bandwidth of the filter if problems
due to phase shift of the amplifier are
to be avoided. (The AD8048 has a
bandwidth of over 200MHz in this
configuration). The filter is designed as
follows:
Choose:

C2 =

4C1(H+1)
2
= 100pF, for C1 = 50pF
(X,
(X,

R1 = 2Hk = 159.20, use 1540
(X,

R3 = 2k(H + 1) =79.60, use 78.70
R4

=H·R1 = 159.2Q, use 1540

Fo = Cutoff Frequency = 20MHz
= Damping Ratio = l/Q = 2
H = Absolute Value of Circuit Gain
= I-R41R11 = 1
k = 21tFoCl
oc:

HIGH SPEED CURRENT-TO-VOLTAGE CONVERTERS, AND
THE EFFECTS OF INVERTING INPUT CAPACITANCE
Fast op amps are useful as current-tovoltage converters in such applications
as high speed photo diode preamplifiers
and current-output DAC buffers. A

typical application using a VFB op amp
as an IIV converter is shown in Figure
1.24.

COMPENSATING FOR INPUT CAPACITANCE IN A
CURRENT-TO-VOLTAGE CONVERTER USING VFB OP AMP
C2
R2

fp

=

1
21t R2C1

" UNCOMPENSATED

fx

=

21t R2C2

- COMPENSATED

fx

=~

IA(s}1

1
/

I /
-

C1
C2 =

1

21t R2 • fu

FOR 45° PHASE MARGIN

Figure 1.24
1 - 24

HIGH SPEED OPERATIONAL AMPLIFIERS

The net input capacitance, Cl, forms a
pole at a frequency fp in the noise gain
transfer function as shown in the Bode
plot, and is given by:
f

C2=~
V~

_
1
p - 21tR2Cl'

If left uncompensated, the phase shift
at the frequency of intersection, fx' will
cause instability and oscillation. Introducing a zero at fx by adding feedback
capacitor C2 stabilizes the circuit and
yields a phase margin of about 45
degrees. The location of the zero is
given by:
f

These equations can be solved for C2:

_
1
x - 21tR2C2'

Although the addition of C2 actually
decreases the pole frequency slightly,
this effect is negligible ifC2 « Cl. The
frequency fx is the geometric mean of fp
and the unity-gain bandwidth frequency of the op amp, fu'
fx

= ~fp' fu

This value of C2 will yield a phase
margin of about 45 degrees. Increasing
the capacitor by a factor of 2 increases
the phase margin to about 65 degrees
(see References 4 and 5).
In practice, the optimum value ofC2
may be optimized experimentally by
varying it slightly to optimize the
output pulse response.

A similar analysis can be applied to a
CFB op amp as shown in Figure 1.25.
In this case, however, the low inverting
input impedance, Ro, greatly reduces
the sensitivity to input capacitanee. In
fact, an ideal CFB with zero input
impedance would be totally insensitive
to any amount of input capacitance!

.

COMPENSATING FOR INPUT CAPACITANCE IN A
CURRENT-TO-VOLTAGE CONVERTER USING CFB OPAMP

C1

1

- - - - I ' : ; ! -1- 21t RolIR2·C1

IT(s)1
/ UNCOMPENSATED

21t ROC1

1
fx= - - 21t R2C2

/
/

-

- COMPENSATED

C2=~
R2t----¥-

RO •
R2

C1
21t R2·fCL

FOR 45° PHASE MARGIN

Figure 1.25
1 - 25

HIGH SPEED DESIGN TECHNIQUES

The pole caused by Cl occurs at a
frequency fp:

C2=~RR20.

1
1
fp = 27t(Roll R2)Cl :::: 27tRoCl .

This pole frequency will be generally be
much higher than the case for a VFB op
am p, and the pole can be ignored
,completely if it occurs at a frequency
greater than the closed-loop bandwidth
of the op amp.
We next introduce a compensating zero
at the frequency fx by inserting the
capacitor C2:
1
fx = 27tR2C2.
As in the case for VFB, fx is the geometric mean of fp and fcl:

Solving the equations for C2 and rearranging it yields:

Cl
27tR2· fcl .

There is a significant advantage in
using a CFB op amp in this configuration as can be seen by comparing the
similar equation for C2 required for a
VFB op amp. If the unity-gain bandwidth product of the VFB is equal to
the closed-loop bandwidth of the CFB
(at the optimum R2), then the size of
the CFB compensation capacitor, C2, is
reduced by a factor of .JR2/ Ro .
A comparison in an actual application
is shown in Figure 1.26. The full scale
output current of the DAC is 4mA, the
net capacitance at the inverting input
of the op amp is 20pF, and the feedback
resistor is 5000. In the case of the VFB
op amp, the pole due to Cl occurs at
16MHz. A compensating capacitor of
5.6pF is required for 45 degrees of
phase margin, and the signal bandwidth is 57MHz.

LOW INVERTING INPUT IMPEDANCE OF CBF
OP AMP MAKES IT RELATIVELY INSENSITIVE TO INPUT
CAPACITANCE WHEN USED AS A
CURRENT-TO-VOLTAGE CONVERTER
...------1

C2

C2

R2

fCl = 200MHz

RO = son
f -

1

P - 21t R2C1

C2
fx

= 16MHz

f -

= 5.6pF

C2 = 1.8pF

= 57MHz

fx

Figure 1.26
1 -26

1

.P - 21t ROC1

= 176MHz

= 160MHz

HIGH SPEED OPERATIONAL AMPLIFIERS

For the CFB op amp, however, because
of the low inverting input impedance
(Ro = 50Q), the pole occurs at 160MHz,
the required compensation capacitor is
about 1.8pF, and the corresponding
signal bandwidth is 176MHz. In actual
practice, the pole frequency is so close
to the closed-loop bandwidth of the op
amp that it could probably be left
uncompensated.
It should be noted that a CFB op amp's
relative insensitivity to inverting input
capacitance is when it is used in the
inverting mode. In the non-inverting
mode, even a few picofarads of stray
capacitance on the inverting input can
cause significant gain-peaking and
potential instability.
Another advantage of the low inverting
input impedance of the CFB op amp is
when it is used as an IIV converter to

buffer the output of a high speed current output DAC. When a step function
current (or DAC switching glitch) is
applied to the inverting input ofa VFB
op amp, it can produce a large voltage
transient until the signal can propagate
through the op amp to its output and
negative feedback is regained. Back-toback Schottky diodes are often used to
limit this voltage swing as shown in
Figure 1.27. These diodes must be low
capacitance, small geometry devices
because their capacitance adds to the
total input capacitance.
A CFB op amp, on the other hand,
presents a low impedance (Ro) to fast
switching currents even before the
feedback loop is closed, thereby limiting
the voltage excursion without the
requirement of the external diodes.
This greatly improves the settling time
of the IIV converter.

LOW INVERTING INPUT IMPEDANCE OF CFB OP AMP
HELPS REDUCE AMPLITUDE OF FAST CAC TRANSIENTS

CURRENT -OUTPUT
DAC

* SCHOTTKY
CATCH
DIODES

*

NOT REQUIRED FOR CFB OP AMP
BECAUSE OF LOW INVERTING INPUT IMPEDANCE

Figure 1.27
1- 27

HIGH SPEED DESIGN TECHNIQUES

NOISE COMPARISONS BETWEEN VFB AND CFB

Op AMPs

Op amp noise has two components: low
frequency noise whose spectral density
is inversely proportional to the square
root of the frequency and white noise at
medium and high frequencies. The lowfrequency noise is known as 1If noise
(the noise power obeys a 1/flaw - the
noise voltage or noise current is proportional to 1I...Jf). The frequency at which
the 1If noise spectral density equals the
white noise is known as the "1IfCorner
Frequency" and is a figure of merit for
the op amp, with the low values indicating better performance. Values of 1If
corner frequency vary from a few Hz for
the most modern low noise low frequency amplifiers to several hundreds,
or even thousands of Hz for high-speed
op amps.

allows you to calculate the total output
rms noise over the closed-loop bandwidth of the amplifier. This formula
works quite well when the frequency
response of the op amp is relatively flat.
If there is more than a few dB of high
frequency peaking, however, the actual
noise will be greater than the predicted
because the contribution over the last
octave before the 3db cutoff frequency
will dominate. In most applications, the
op amp feedback network is designed so
that the bandwidth is relatively flat,
and the formula provides a good estimate. Note that BW in the equation is
the equivalent noise bandwidth which,
for a single-pole system, is obtained by
multiplying the closed-loop bandwidth
by 1.57.

In most applications of high speed op
amps, it is the total output rms noise
that is generally of interest. Because of
the high bandwidths, the chief contributor to the output rms noise is the
white noise, and that of the l/fnoise is
negligible.

Figure 1.29 shows a table which indicates how the individual noise contributors are referred to the output. After
calculating the individual noise spectral
densities in this table, they can be
squared, added, and then the square
root of the sum of the squares yields the
RSS value of the output noise spectral
densi ty since all the sources are
uncorrelated. This value is multiplied by
the square root of the noise bandwidth
(noise bandwidth = closed-loop bandwidth multiplied by a correction factor of
1.57) to obtain the final value for the
output rms noise.

In order to better understand the
effects of noise in high speed op amps,
we use the classical noise model shown
in Figure 1.28. This diagram identifies
all possible white noise sources, including the external noise in the source and
the feedback resistors. The equation

1 - 28

HIGH SPEED OPERATIONAL AMPLIFIERS

OP AMP NOISE MODEL FOR A
FIRST-ORDER CIRCUIT WITH RESISTIVE FEEDBACK

BW = 1.57f cl
f cl = CLOSED LOOP BANDWIDTH

Figure 1.28

REFERRING ALL NOISE SOURCES TO THE OUTPUT
NOISE SOURCE EXPRESSED AS
A VOLTAGE
Johnson Noise in Rp:
.J4kTRp
Non-Inverting Input Current
Noise Flowing in Rp:
In+RD
Input Voltage Noise:
Vn
Johnson Noise in R1:
.J4kTR1
Johnson Noise in R2:
.J4kTR2
Inverting Input Current Noise
Flowing in R2:
In _R2

MULTIPLY BY THIS FACTOR TO
REFER TO THE OP AMP OUTPUT
N'
olse G'
aln= 1+R2
R1
N'
olse G'
aln= 1+R2
R1
N'
olse G'
aln= 1+R2
R1
-R2/R1 (Gain from input of R1 to
Output)
1
1

Figure 1.29
1 - 29

HIGH SPEED DESIGN TECHNIQUES

Typical high speed op amps with bandwidths greater than 150MHz or so, and
bipolar input stages have input voltage
noises ranging from about 2 to 20nVI
...JHz. To put voltage noise in perspective, let's look at the Johnson noise
spectral density of a resistor:
vn =.J4kTR·BW,
where k is Boltzmann's constant, Tis
the absolute temperature, R is the
resistor value, and BW is the equivalent noise bandwidth of interest. (The
equivalent noise bandwidth of a singlepole system is 1.57 times the 3dB
frequency). Using the formula, a lOOn
resistor has a noise density of 1. 3nVI
...JHz, and a 1000n resistor about 4nVI
...JHz (values are at room temperature:
27°C, or 300K).
The base-emitter in a bipolar transistor
has an equivalent noise voltage source
which is due to the "shot noise" of the
collector current flowing in the
transistor's (noiseless) incremental
emitter resistance, reo The current
noise is proportional to the square root
of the collector current, Ic. The emitter
resistance, on the other hand, is inversely proportional to the collector
current, so the shot-noise voltage is
inversely proportional to the square root
of the collector current. (Reference 5,
Section 9).
Voltage noise in FET-input op amps
tends to be larger than for bipolar ones,
but current noise is extremely low
(generally only a few tens of fAl..JHz)
because of the low input bias currents.
However, FET-inputs are not generally
required for op amp applications requiring bandwidths greater than 100MHz.
Op amps also have input current noise
1 • ___
_____ ..3
on eacn InpU"t;• .r ur nlg.u-l:)p~~U
~input op amps, the gate currents are so
L

,-;, ___

1_!~1

l:;"~m

.['.£J

1 - 30

low that input current noise is almost
always negligible (measured in fAI....JHz).
For a VFB op amp, the inverting and
non-inverting input current noise are
typically equal, and almost always
uncorrelated. Typical values for
wideband VFB op amps range from
O.5pAl....JHz to 5pAl...JHz. The input
current noise of a bipolar input stage is
increased when input bias-current
cancellation generators are added,
because their current noise is not
correlated, and therefore adds (in an
RSS manner) to the intrinsic current
noise of the bipolar stage.
The input voltage noise in CFB op
amps tends to be lower than for VFB op
amps having the same approximate
bandwidth. This is because the input
stage in a CFB op amp is usually
operated at a higher current, thereby
reducing the emitter resistance and
hence the voltage noise. Typical values
for CFB op amps range from about 1 to
5nV/....JHz.
The input current noise ofCFB op amps
tends to be larger than for VFB op
amps because of the generally higher
bias current levels. The inverting and
non-inverting current noise of a CFB is
usually different because of the unique
input architecture, and are specified
separately. In most cases, the inverting
input current noise is the larger of the
two. Typical input current noise for
CFB op amps ranges from 5 to 40pA/
....JHz.
The general principle of noise calculation is that uncorrela ted noise sources
add in a root-sum-squares manner,
which means that if a noise source has
a contribution to the output noise of a
system which is less than 20~ of the
amplitude of the noise from other noise

HIGH SPEED OPERATIONAL AMPLIFIERS

source in the system, then its contribution to the total system noise will be
less than 2% of the total, and that noise
source can almost invariably be ignored
- in many cases, noise sources smaller
than 33% of the largest can be ignored.
This can simplify the calculations using
the formula, assuming the. correct
decisions are made regarding the
sources to be included and those to be
neglected.

is difficult to generalize about their
contribution to the total output noise
without knowing the specific values and
the closed loop gain. The best way to
make the calculations is to write a
simple computer program which performs the calculations automatically
and include all noise sources. In most
high speed applications, the source
impedance noise can be neglected for
source impedances of lOOn or less.

The sources which dominate the output
noise are highly dependent on the
closed-loop gain of the op amp. Notice
that for high values of closed loop gain,
the op amp voltage noise will tend be
the chief contributor to the output
noise. At low gains, the effects of the
input current noise must also be considered, and may dominate, especially in
the case ofa CFB op amp.

Figure 1.30 shows an example calculation of total output noise for the
AD8011 (300MHz, ImA) CFB op amp.
All six possible sources are included in
the calculation. The appropriate multiplying factors which reflect the sources
to the output are also shown on the
diagram. For G=2, the close-loop bandwidth of the AD8011 is 180MHz. The
correction factor of 1.57 in the final
calculation converts this single-pole
bandwidth into the circuits equivalent
noise bandwidth.

Feedforwardlfeedback resistors in high
speed op amp circuits may range from
less than lOOn to more than lkn, so it

AD8011 OUTPUT NOISE ANALYSIS
r- - -- - -- - -- - - - - - - - - - - - - - - - - --- --. (G)- -

-> 1.8nV/..JHz

I

r - - - - - - - - - - - - - - - - - - - - - - - - - - · ( G · Rs)-->0.5nV/..JHz
I
.-- - - - - ....,
I .-- - _1- _ ....
I 2nV,..JHz L _________________ (G) --~ 4nV,..JHz
I I 5pAl..JHz I
L _____ I
L _____ I
I
I
I
I
----l.--..,
G=1 + R2
R1
:_0.9nvNHz
_ _ _ _ _ JI f'J

\

1kn

.---'--- ....

IL __
5pAl..JHz
, __ II

.-----..

4nV,..JHz l1----- (1) .--~ 4nvNHz
lI _____

- - - - - - - - - - - - - - - - - - (R2) .--~ 5nV/"Hz

,--------,

Il _____
4nV/..JHz lL _____________
R1

1kn

(-R2/R1)--~4nV'..JHz

•

OUTPUT NOISE SPECTRAL DENSITY = 8.7nV/..JHz

•

TOTAL NOISE

=8.7/1.57 X 180 X 106 =146~V rms

Figure 1.30
1 - 31

HIGH SPEED DESIGN TECHNIQUES

In communications applications, it is
common to specify the noise figure (NF)
of an amplifier. Figure 1.31 shows the
definition. NF is the ratio of the total
integrated output noise from all sources
to the total output noise which would
result if the op amp were "noiseless"
(this noise would be that of the source
resistance multiplied by the gain of the
op amp using the closed-loop bandwidth
of the op amp to make the calculation).

Noise figure is expressed in dB. The
value of the source resistance must be
specified, and in most RF systems, it is
500. Noise figure is useful in communications receiver design, since it can be
used to measure the decrease in signalto-noise ratio. For instance, an amplifier with a noise figure of 10dB
following a stage with a signal-to-noise
ratio of 50dB reduces the signal-tonoise ratio to 40dB.

NOISE FIGURE OF AN OP AMP

NOISE FIGURE = 2010g

rOUTPUT
TOTAL OUTPUT NOISE ]
L
NOISE DUE TO Rs

, - - - - - - - - - - - - - - - - - - - - - G ---> 1.8nV'''Hz
I
I

___ -L __ -,

I O.gnV'" Hz

______ JI

NOISE FIGURE

TOTAL = 8.7nV'"Hz

=20109[ 8.7J =13.7dB

L1.8J

Figure 1.31

The ratio is commonly expressed in dB
and is useful in signal chain analysis.
In the previous exam pIe, the total
output voltage noise was 8.7nV/...JHz.
Integrated over the closed loop bandwidth of the op amp (180MHz), this
yielded an output noise of 146).1V rms.
The noise of the 500 source resistance
is 0.9nV/...JHz. If the op amp were noiseless (with noiseless feedback resistors),
this noise would appear at the output
multiplied by the noise gain (G=2) of
ihe op amp, or 1.8nVr~Hz. The total
output rms noise just due to the source
1 - 32

resistor integrated over the same
bandwidth is 30.3).1V rms. The noise
figure is calculated as:
NF =2010g10 (146) = 13.7dB.
30.3
The same result can be obtained by
working with spectral densities, since
the bandwidths used for the integration
are the same and cancel each other in
the equation.

NF=20IoglO (

~~)= 13.7dB.

HIGH SPEED OPERATIONAL AMPLIFIERS

HIGH SPEED OP AMP NOISE SUMMARY
•

Voltage Feedback Op Amps:
•
•

•

Voltage Noise: 2 to 20nV'''Hz
Current Noise: 0.5 to 5pAl"Hz

Current Feedback Op Amps:
•
•

Voltage Noise: 1 to 5nV/"Hz
Current Noise: 5 to 40pAl"Hz

•

Noise Contribution from Source Negligible if < 1oon

•

Voltage Noise Usually Dominates at High Gains

•

Reflect Noise Sources to Output and Combine (RSS)

•

Errors Will Result if there is Significant
High Frequency Peaking

Figure 1.32

DC CHARACTERISTICS OF HIGH SPEED
High speed op amps are optimized for
bandwidth and settling time, not for
precision DC characteristics as found in
lower frequency op amps such as the
industry standard OP27. In spite of

Op AMpS

this, however, high speed op amps do
have reasonably good DC performance.
The model shown in Figure 1.33 shows
how to reflect the input offset voltage
. andthe offset currents to the output.

MODEL FOR CALCULATING TOTAL
OP AMP OUTPUT VOLTAGE OFFSET

•

IF Ib+

=Ib- AND R3 =R111R2
Vo = ±VOS[1 +

~J

Figure 1.33
1 - 33

HIGH SPEED DESIGN TECHNIQUES

Input offset voltages of high speed
bipolar input op amps are rarely
trimmed, since offset voltage matching
of the input stage is excellent, typically
ranging from 1 to 3mV, with offset
temperature coefficients of 5 to 15p.VI

°C.
Input bias currents on VFB op amps
(with no input bias current compensation circuits) are approximately equal.
for (+) and (-) inputs, and can range
from 1 to 5p.A. The output offset voltage
due to the input bias currents can be
nulled by making the effective source
resistance, R3, equal to the parallel
combination of R1 and R2.
This scheme will not work, however,
with bias-current compensated VFB op
amps which have additional current
generators on their inputs. In this case,
the net input bias currents are not

necessarily equal or of the same polarity. Op amps designed for rail-to-rail
input operation (parallel PNP and NPN
differential stages as described later in
this section) have bias currents which
are also a function of the common-mode
input voltage. External bias current
cancellation schemes are ineffective
with these op amps also. It should be
noted, however, that it is often desirable to match the source impedance
seen by the (+) and (-) inputs ofVFB op
am ps to minimize distortion.
CFB op amps generally have unequal
and uncorrelated input bias currents
because the (+) and (-) inputs have
completely different architectures. For
this reason, external bias current
cancellation schemes are also ineffective. CFB input bias currents range
from 5 to 15p.A, being generally higher
at the inverting input

OUTPUT OFFSET VOLTAGE SUMMARY
•

•

•

High Speed Bi'polar Op Amp Input Offset Voltage:
•

Ranges from 1 to 3mV for VFB and CFB

•

Offset TC Ranges from· 5 to 15IJVrC

High Speed Bipolar Op Amp Input Bias Current:
•

For VFB Ranges from 1 to 5IJA

•

For CFB Ranges from 5 to 15IJA

Bias Current Cancellation Doesn't Work for:
•

Bias Current Compensated Op Amps

•

Current Feedback Op Amps

Figure 1.34
1 - 34

HIGH SPEED OPERATIONAL AMPLIFIERS

PSRR CHARACTERISTICS OF HIGH SPEED
As with most op amps, the power

Op AMPs

10MHz, it falls to only 20dB, indicating
the need for excellent external LF and
HF decoupling. These numbers are
fairly typical of most high speed VFB or
CFB op amps, although the DC PSRR
may range from 55 to BOdB depending
on the op amp.

supply rejection ratio (PSRR) of high
speed op amps falls off rapidly at higher
frequencies. Figure 1.35 shows the
PSRR for the ADB011 CFB 300MHz
CFB op amp. Notice that at DC, the
PSRR is nearly 60dB, however, at

AD8011 POWER SUPPLY REJECTION RATIO
+10

II

o
-10

= +sv o~
G =+2
RF= 1kQ

Vs'

I-

JsV
10-"'-:::::

-20

~

aJ -30
't:I

ci: -40

ex:

~

-so
-60

::::: ....

",

~

..... 1-"
~~

,

~~

::: .... ~

? ~~

1/1

'7PSRR

~~

-70
-80
-90

100k

1M
10M
FREQUENCY - Hz

100M

SOOM

Figure 1.35

The power pins ofop amps must be
decoupled directly to a large-area
ground plane with capacitors which
have minimal lead length. It is generally recommended that a low-inductance ceramic surface mount capacitor

(O.01pF to O.l].lF) be used for the high
frequency noise. The lower frequency
noise can be decoupled with low-inductance tantalum electrolytic capacitors
(1 to 10].lF).

1 - 35

HIGH SPEED DESIGN TECHNIQUES

REFERENCES
1.

Thomas M. Frederiksen, Intuitive Operational Amplifiers, McGraw-Hill,
1988.

2.

Sergio Franco, Current Feedback Amplifiers, EDN, Jan.5, 1989.

3.

Roy Gosser, U.S Patent 5,150,074.

4.

James L. Melsa and Donald G. Schultz, Linear Control Systems,
McGraw-Hill, 1969, pp. 196-220.

5.

Amplifier Applications Guide, Analog Devices, Inc., 1992~ Section 3.

6.

Walter G. Jung, IC Op amp Cookbook, Third Edition, Howard Sams &
Co., 1986, ISBN: 0-672-22453-4.

7.

Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog
Integrated Circuits, Third Edition, John Wiley, 1993.

8.

J. K. Roberge, Operational Amplifiers-Theory and Practice, John
Wiley, 1975.

9.

Henry W. Ott, Noise Reduction Techniques in Electronic Systems,
Second Edition, John Wiley, Inc., 1988.

10.

Lewis Smith and Dan Sheingold, Noise and Operational Amplifier Circuits,
Analog Dialogue 25th Anniversary Issue, pp. 19-31, 1991.

11.

D. Stout, M. Kaufman, Handbook of Operational Amplifier Circuit
Design, New York, McGraw-Hill, 1976.

12.

Joe Buxton, Careful Design Tames High-Speed Op Amps, Electronic
Design, April 11, 1991.

13.

J. Dostal, Operational Amplifiers, Elsevier Scientific Publishing, New
York, 1981.

14.

Barrie Gilbert, Contemporary Feedback Amplifier Design,

15.

Sergio Franco, Design with Operational Amplifiers and Analog ICs,
McGraw-Hill Book Company, 1988.

16.

Jerald Graeme, Photodiode Amplifiers-Op Amp Solutions, Gain Technology Corporation, 2700 W. Broadway Blvd., Tucson,
AZ 85745, 1996.

1 - 36

SECTION 2
HIGH SPEED OP AMP APPLICATIONS
•

Optimizing the Feedback Network for Maximum
Bandwidth Flatness in Wideband CFB Op Amps

•

Driving Capacitive Loads

•

Cable Drivers and Receivers

•

A High Performance Video Line Driver

•

Differential Line Drivers/Receivers

•

High Speed Clamping Amplifiers

•

Single-Supply/Rail-to-Rail Considerations

•

High Speed Video Multiplexing with Op Amps
Using Disable Function

•

Video Programmable Gain Amplifier

•

Video Multiplexers and Crosspoint Switches

•

High Power Line Drivers and ADSL

•

High Speed Photodiode Preamps

HIGH SPEED DESIGN TECHNIQUES

HIGH SPEED Qp AMp ,ApPLICATIONS

SECTION 2
HIGH SPEED OP AMP APPLICATIONS
Walt Kester, Walt Jung
OPTIMIZING THE FEEDBACK NETWORK FOR
BANDWIDTH FLATNESS IN WIDEBAND CFB
Achieving the highest O.1dB bandwidth
flatness is important in many video
applications. Because of the critical
relationship between the feedback
resistor and the bandwidth of a CFB op
amp, optimum bandwidth flatness is
highly dependent on the feedback
resistor value, the resistor parasitics, as

MAxIMuM
Op AMPs

well as the op amp package and PCB
parasitics. Figure 2.1 shows the fine
scale (O.ldB/division) flatness plotted
versus the feedback resistance for the
AD8001 in a non-inverting gain of2.
These plots were made using the
AD8001 evaluation board with surface
mount resistors.

AD8001 CFB OP AMP BANDWIDTH FLATNESS OPTIMIZED BY
PROPER SELECTION OF FEEDBACK RESISTOR
0.1

G=+2

--t:::::'"r- i'.
'R F =69S0>
I

-0.1

~\

V
\
r\ \ \
\ '
\\
\\
\\
\\
\
~\

-0.2

RF = 7500 ./

G=+2

en

"f

RF =
6490

~

o

-0.3

...~ -0.4
...
5 -0.5

\

-0.6
-0.7
-0.8

\

-0.9
10M
FREQUENCY - Hz

1M

100M

Figure 2.1

It is recommended that once the optimum resistor values have been determined, 1% tolerance values should be
used. In addition, resistors of different
construction have different associated
parasitic capacitance and inductance.

Surface mount resistors are the optimum choice, and it is not recommended
that leaded components be used with
high speed op amps at these frequencies because of their parasitics.
2 -1

HIGH SPEED DESIGN TECHNIQUES

Slightly different resistor values may
be required to achieve optimum performance in the DIP versus the SOIC
packages (see Figure 2.2). The SOIC
package exhibits slightly lower parasitic capacitance and inductance than
the DIP. The data shows the optimum

feedback (RG) and feedforward (RF)
resistors for highest O.ldB bandwidth
for the AD8001 in the DIP and the
SOIC packages. As you might suspect,
the SOIC package can be optimized for·
slightly higher O.ldB bandwidth because of its lower parasitics.

OPTIMUM VALUES OF RF AND RG FOR AD8001
DIP AND SOIC PACKAGES (MAXIMUM O.1dB BANDWIDTH)
Component

AD8001AN (DIP) GAIN
-1
+1
+2

RF

6490

10500

7500

RG

6490

-

7500

0.1dB Flatness

105MHz 70MHz

105MHz

AD8001AR (SOIC) GAIN
Component
-1
+1
+2
RF

6040

9530

6810

RG

6040

-

6810

0.1 dB Flatness

130MHz 100MHz 120MHz

Figure 2.2

As has been discussed, the CFB op amp
is relatively insensitive to capacitance
on the inverting input when it is used
in the inverting mode (as in an IIV
application). This is because the low
inverting input impedance is in parallel
with the external capacitance and tends
to minimize its effect. In the noninverting mode, however, even a few
picofarads of stray inverting input
capacitance may cause peaking and
instability. Figure 2.3 shows the effects
of adding summing junction capacitance to the inverting input of the
2-2

AD8004 (SOIC package) for G = +2.
Note that only IpF of added inverting
input capacitance (CJ) causes a significant increase in bandwidth and an
increase in peaking. For G =-2, however, 5pF of additional inverting input
capacitance causes only a small increase in bandwidth and no significant
increase in peaking.
High speed VFB op amps are sensitive
to stray inverting input capacitance
when used in either the inverting or
non-inverting mode.

Qp AMp APPLICATIONS

HIGH SPEED

.AD8004 CFB OP AMP SENSITIVITY TO
INVERTING INPUT CAPACITANCE FOR G = +2, G = - 2
]

I

r---r-.
+2

d=~2
I
I-

0

cr'

CJ = 1pF

r--" ~
I"-

r:::~

II

-HH-~--'\I\H~~-l
INPUT

SCOPE

10pF

L _______ _

VERTICAL
. SCALE: 100mV/div
HORIZONTAL
SCALE: 10ns/div

................. , ........... ..
··
..
...
.
·
.
·
.
..... .................. ... , .
................... , ..... .
' "
··
.
..
·
' "
_. . . . ··. . . . . .
. . ..
. . .. . . . . . . . . ... ....... ..... . ....... .
.
.
·
.
.
.
·
.
."
..
.
·
.
. . . . ·. . . . . .. . . . . .. . . . . .. . . . . .. . . . . ... . . . . . . . .. . ........ ·. ..
.
.. ..
·
.
.
.
. . .. ..............................
... . ........ ·
.
.
.
.
:
:
:
: ~-.........;/"-----'

SCOPE
OUTPUT

Figure 2.13

Source-end (only) terminations can also
be used as shown in Figure 2.14, where
the op amp is source terminated by the
50n resistor which drives the cable.
The scope is set for 1Mfl input impedance, representing an approximate
open circuit. The initial leading edge of
the pulse at the op amp output sees a
lOOn load (the 50n source resistor in
series with the 50n coax impedance.

When the pulse reaches the load, a
large portion is reflected in phase
because of the high load impedance,
resulting in a full-amplitude pulse at
the load. When the reflection reaches
the source-end of the cable, it sees the
50n source resistance in series with the
op amp closed loop output impedance
(approximately lOOn at the frequency
represented by the 2ns risetime pulse
2 -15

HIGH SPEED DESIGN TECHNIQUES

edge). The reflected portion remains in
phase, and appeRrs at the scope input

as the positive-going "blip" approximately 16ns after the leading edge.

PULSE RESPONSE OF AD8001 DRIVING 5 FEET
OF SOURCE-TERMINATED 50n COAXIAL CABLE

r--------

PULSE
INPUT

I
I
I
I

>-Ht+-_4_---'\ 1\ 1\ r-----..!

SCOPE

10pF

L _______ _

·

~

HORIZONTAL
SCALE: 10ns/div

.

·
.
.
.
..
.
.............................................
·
.
..
· .
·,
.
.
.
.
.
.
.... : .... .: .... .: .... .
: .... : ... : .... : .... : .....

VERTICAL
SCALE: 200mV/div

"'-

··
..
..
..
..
..
..
...
.
.
.... ·: .... .: .... .: ... , .: .... .: ... .: .........
: .........
·
.
.
.
.
·
.
.
.... :· .... .: .... .: .... :. .... :. .......................
~
.
.
.
.
.
·· . .
.
...............................................
..
....
·
.·
.
.
.
.
·
.
.
.
.................................................
··
.
,
.
.
.
.
.
..
·· ... ... ... . .
~

SCOPE
OUTPUT

' "
"
' "

"

' "
"

,---...~

' "

"
"

Figure 2.14

From these experiments, one can easily
see that the preferred method for
minimum reflections (and therefore
maximum bandwidth flatness) is to use
both source and load terminations and
try to minimize any reactance associated with the load. The experiments
represent a worst-case condition, where
the frequencies contained in the fast
edges are greater than 100MHz. (Using
the rule-of-thumb that bandwidth =
O.35/risetime). At video frequencies,
either load-only, or source-only termi-

2 -16

nations may give acceptable results,
but the data sheet should always be
consulted to determine the op amp's
closed-loop output impedance at the
maximum frequency of interest. A
major disadvantage of the source-only
termination is that it.requires a truly
high impedance load (high resistance
and minimal parasitic capacitance) for
minimum absorption of energy. It also
places a burden on this amplifier to
mairttain a low output impedance at
high frequencies.

HIGH SPEED

Now, for a truly worst case, let us
replace the 5 feet of coaxial cable with
an uncontrolled-impedance cable (one
that is largely capacitive with little
inductance). Let us use a capacitance of
150pF to simulate the cable (corresponding to the total capacitance of 5
feet of coaxial cable whose distributed
capacitance is about 30pF/foot). Figure
2.15 shows the output of the AD8001

Op AMP ,ApPLICATIONS

driving a lumped 160pF capacitance
(including the scope input capacitance
of 10pF). Notice the overshoot and
ringing on the pulse waveform due to
the capacitive loading. This example
illustrates the need to use good quality
controlled-impedance coaxial cable in
the transmission of high frequency
signals.

PULSE RESPONSE OF AD8001 DRIVING 160pF

PULSE
INPUT

>-HiH--e----'1,/\ J \,.-_.-i

I
I
+-DIRECT ~ I
CONNECTION
I

II son LOAD
SCOPE

10pF

I
IL _ _ _ _ _ _ _ _ _ _ _

VERTICAL
SCALE: 200mV/div
SCOPE
OUTPUT

HORIZONTAL
SCALE: 10ns/div

Figure 2.15

2 -17

HIGH SPEED DESIGN TECHNIQUES

A

HIGH PERFORMANCE VIDEO

The AD8047 and AD8048 VFB op amps
have been optimized to offer outstanding performance as video line drivers.
They utilized the "quad core" gm stage
as previously described for high slew
rate and low distortion. The AD8048
(optimized for G = +2) has a differential
gain of 0.01% and a differential phase

LINE DRIVER
of 0.020 , making it suitable for HDTV
applications. In the configuration
shown in Figure 2.16, the 0.1dB bandwidth is 50MHz for ±5V supplies, slew
rate is 1000V/ps, and 0.1% settling
time is 13ns. Total quiescent current is
6mA (±5V), and quiescent power dissipation 60mW.

VIDEO LINE DRIVER USING AD8047/AD8048:
ilG = 0.01%, d~ = 0.02°, 50MHz 0.1dB BANDWIDTH, 6mA (±5V)
2000

2000

Figure 2.16

DIFFERENTIAL

LINE

DRIVERS/RECEIVERS

Many applications require gain/phase
matched complementary or differential
signals. Among these are analogdigital-converter (ADC) input buffers,
where differential operation can provide
lower levels of 2nd harmonic distortion
for certain converters. Other uses
include high frequency bridge excitation, and drivers for balanced transmission twisted pair lines such as in ADSL
andHDSL.
2 -18

The transmission of high quality signals across noisy interfaces (either
between individual PC boards or between racks) has always been a challenge to design engineers. Differential
techniques using high common-moderejection-ratio (CMRR) instrumentation
amplifiers largely solves the problem at
low frequencies.

HIGH SPEED Qp

At audio frequencies, transformers, or
products such as the SSM-2142 balanced line driver and SSM-21411SSM2143 line receiver offer outstanding
CMRRs and the ability to transmit lowlevel signals in the presence of large
amounts of noise. At high frequencies,
small toroid transformers using bifilar
windings are effective.
The problem of signal transmission at
video frequencies is complex. Transformers are not effective, because the
baseband video signal has low-frequency components down to a few tens
of Hz. Video signals are generally
single-ended, and therefore don't adapt
easily to balanced transmission line
techniques. In addition, shielded twinconductor coaxial cable with good
bandwidth is usually somewhat bulky
and expensive. Finally, designing high
bandwidth, low distortion differential
video drivers and receivers with high

AMP APPLICATIONS

CMRRs at high frequencies is an extremely difficult task.
Even with the above problems, there
are differential techniques available
now which offer distinct advantages
over single-ended methods. Some of
these techniques make use of discrete
components, while others utilize the
latest in state-of-the-art video differential amplifiers.
Two solutions to the problem of differential transmission and reception are
shown in Figure 2.17. The first represents the ideal case, where a balanced
differential line driver drives a balanced twin-conductor coaxial cable
which in turn drives a differential line
receiver. This circuit, however, is difficult to implement fully at video frequencies for the reasons previously
discussed.

TWO APPROACHES FOR
DIFFERENTIAL LINE DRIVING/RECEIVING

GNDA

VNOISE

GND B

Figure 2.17
2 -19

HIGH SPEED DESIGN TECHNIQUES

The second and most often used approach makes use of a single-ended
driver which drives a source-terminated
coaxial cable. The shield of the coaxial
cable is grounded at the transmitting
end. At the receiving end, the coaxial
cable is terminated in its characteristic
impedance, but the shield is left float-

ing in order to prevent a ground loop
between the two systems. The common
mode ground noise is rejected by the
CMRR of the differential line receiver.
The success of this approach depends
upon the characteristics of the line
receiver.

Inverter-Follower Differential Driver
The circuit of Figure 2.18 is useful as a
high speed differential driver for driving high speed 10-12 bit ADCs, differential video lines, and other balanced
loads at levels of 1-4Vrms. As shown it
operates from ±5V supplies, but it can
also be adapted to supplies in the range

of ±5 to ±15V. When operated directly
from ±5V as here, it minimizes potential for destructive ADC overdrive when
higher supply voltage buffers drive a
±5V powered ADC, in addition to minimizing driver power.

DIFFERENTIAL DRIVER USING INVERTER/FOLLOWER

VOUTA

RIN

83.50 (750)
53.60 (500)

2050

5490

R(;2

RlB

~--~V1VV---+-----'VV\~~~--~r---~

750

NOTE: OECOUPLING
NOT SHOWN

Figure 2=18

2-20

VOUlB

HIGH SPEED

In many of these differential drivers the
performance criteria is high. In addition
to low output distortion, the two signals
should maintain gain/phase flatness. In
this topology, two sections of an AD812
dual current feedback amplifier are
used for the channel A & B buffers,
U1A & U1B. This can provide inherently better open-loop bandwidth
matching than the use of two singles
(where bandwidth varies between
devices from different manufacturing
lots).
The two buffers here operate with
precise gains of ±1, as defined by their
respective feedback and input resistances. Channel B buffer U1B is conventional, and uses a matched pair of
7150 resistors- the value for using the
AD812 on ±5V supplies.
In channel A, non-inverting buffer U1A
has an inherent signal gain of 1, by
virtue of the bootstrapped feedback
network RFB1 and RG1(Reference 5).
It also has a higher noise gain, for
phase matching. Normally a current
feedback amplifier operating as a
simple unity gain follower would use
one (optimum) resistor RFB1, and no
gain resistor at all. Here, with input
resistor RG 1 added, a U1A noise gain
like that of U1B results. Due to the
bootstrap connection ofRFB1-RG1, the
signal gain is maintained at unity.
Given the matched open loop bandwidths of U1A and U1B, similar noise
gains in the A-B channels provide
closely matched output bandwidths
between the driver sides, a distinction
which greatly impacts overall matching
performance.
In setting up a design for the driver,
the effects of resistor gain errors should
be considered for RG2-RFB2. Here a

Op AMp APPLICATIONS

worst case 2% mis-match will result in
less than 0.2dB gain error between
channels A and B. This error can be
improved simply by specifying tighter
resistor ratio matching, avoiding trimming.
If desired, phase matching is trimmed
via RG 1, so that the phase of channel A
closely matches that ofB. This can be
done for new circuit conditions, by
using a pair of closely matched (0.1% or
better) resistors to sum the A and B
channels, as RG1 is adjusted for the
best null conditions at the sum node.
The A-B gain/phase matching is quite
effective in this driver, with test results
of the circuit as shown 0.04dB and 0.10
between the A and B output signals at
10MHz, when operated into dual 1500
loads. The 3dB bandwidth of the driver
is about 60MHz.
Net input impedance of the circuit is set
to a standard line termination value
such as 750 (or 500), by choosing RIN
so that the desired value results with
RIN in parallel with RG2. In this
example, an RIN value of 83.50 provides a standard input impedance of
750 when paralleled with 7150. For
the circuit just as shown, dual voltage
feedback amplifier types with sufficiently high speed and low distortion
can also be used. This allows greater
freedom with regard to resistor values
using such devices as the AD826 and
AD828.
Gain of the circuit can be changed if
desired, but this is not totally straightforward. An easy step to satisfy diverse
gain requirements is to simply use a
triple amplifier such as the AD813,
with the third channel as a variable
gain input buffer.

2 - 21

HIGH SPEED DESIGN TECHNIQUES

Cross-Coupled Differential Driver
Another differential driver approach
uses cross-coupled feedback to get very
high CMR and complementary outputs
at the same time. In Figure 2.19, by
connecting AD8002 dual current feed-

back amplifier sections as cross-coupled
inverters, their outputs are forced equal
and opposite, assuring zero output
common mode voltage.

CROSS-COUPLED DIFFERENTIAL DRIVER
PROVIDES BALANCED OUTPUTS AND 250MHz BANDWIDTH
V1N

R1
5110

5110

U1A
AD8002

VOUTA

I
I
I
I

(see
R3text)

f
I
I
I

AOUT

f

r---5110

Rx

RTA
49.90

VOUT

t

RlS

VOUTB

5110

BOUT
49.90

Rx

NOTE: ALL RESISTORS 1%
DECOUPUNG NOT SHOWN

5110

RX

~----

U1B

AD8002

Figure 2.19

The gain cell which results, U1A and
U1B plus cross-coupling resistances RX,
is fundamentally a differential input
and output topology, but it behaves as a
voltage feedback amplifier with regard
to the feedback port at the U1A (+)
node. The gain of the stage from VIN to
VOUTis:
G= VOUT = 2R2
VIN
Rl

where VOUT is the differential output,
equal to VOUTA - VOUTB.
This relationship may not be obvious,
so it can be derived as follows:
Using the conventional inverting op
amp gain equation, the input voltage
VIN develops an output voltage
VOUTB given by:
VOUTB

2-22

R2

= -VIN R1 .

HIGH SPEED

Also, VOUTA = -VOUTB,
because VOUTA is inverted by U1B.
However, VOUT = VOUTA - VOUTB =
- 2VOUTB·
Therefore,
R2) =2VINR2
VOUT=-2( -VINR1
R1'
and
VOUT 2R2
=-VIN
R1
This circuit has some unique benefits.
First, differential gain is set by a single
resistor ratio, so there is no necessity
for side-side resistor matching with
gain changes, as is the case for conventional differential amplifiers (see line
receivers, below). Second, because the
(overall) circuit emulates a voltage
feedback amplifier, these gain resistances are not as restrictive as in the
case of a conventional current feedback
amplifier. Thus, they are not highly
critical as to value as long as the
equivalent resistance seen by U1A is
reasonably low (~1kn in this case).
Third, the cell bandwidth can be optimized to the desired gain by a single
optional resistor, R3, as follows. Iffor
instance, a net gain of 20 is desired (R21
R1=10), the bandwidth would otherwise
be reduced by roughly this amount,
since without R3, the cell operates with
a constant gain-bandwidth product
(working in the voltage feedback mode).
With R3 present however, advantage
can be taken of the AD8002 current
feedback amplifier characteristics.
Additional internal gain is added by the
connection ofR3, which, given an
appropriate value, effectively raises
gain-bandwidth to a level so as to
restore the bandwidth which would

Op AMp ,ApPLICATIONS

otherwise be lost by the higher closed
loop gain.
In the circuit as shown, no R3 is necessary at the low working gain of 2 times
differential, since the 5110 RX resistors
are already optimized for maximum
bandwidth. Note that these four
matched RX resistances are somewhat
critical, and will change in absolute
value with the use of another current
feedback amplifier. At higher gain
closed loop gains as set by R2IR1, R3
can be chosen to optimize the working
transconductance in the input stages of
U1A and U1B, as follows:

R3~

Rx
(R21 R1)-1

As in any high speed inverting feedback
amplifier, a small high-Q chip type
feedback capacitance, C1, may be
needed to optimize flatness of frequency
response. In this example, a 0.9pF
value was found optimum for minimizing peaking. In general, provision
should be made on the PC layout for an
,NPO chip capacitor in the range of 0.52pF. This capacitor is then value selected at board characterization for
optimum frequency response.
For the dual trace, 1-500MHz swept
frequency response plot of Figure 2.20,
output levels were OdBm into matched
50n loads, through back termination
resistances RTA and RTB, at VOUTA
and V0 UTB. In this plot the vertical
scale is 2dB/div, and it shows the 3dB
bandwidth of the driver measuring
about 250MHz, with peaking about
0.1dB. The four RX resistors along with
RTA and RTB control low frequency
amplitude matching, which was within
0.1dB in the lab tests, using 5110 1%
resistor types. For tightest amplitude
matching, these resistor ratios can be
more closely controlled.
2 - 23

HIGH SPEED DESIGN TECHNIQUES

FREQUENCY RESPONSE OF AD8002 CROSS-COUPLED
DRIVER IS > 250MHz (C1 0.9pF ± 0.1 pF)

=

RELATIVE
RESPONSE
(dB)

0

..............

~.3dB BW=260 MHz

....... "

·2

",

·4
·6

---AOUT

·8

- - - - - - BOUT

"

·10
·12
·14
·16
·18

10

20

40

100

200

400

FREQUENCY (MHz)

Figure 2.20

Due to the high gain-bandwidths involved with the AD8002, the construction of this circuit should follow RF
rules, with the use of a ground plane,

chip bypass capacitors of zero lead
length at the ±5V supply pins, and
surface mount resistors for lowest
inductance.

4 Resistor Differential Line Receiver
Figure 2.21 shows a low cost, medium
performance line receiver using a high
speed op amp rated for video use. It is
actually a standard 4 resistor difference
amplifier optimized for high speed, with
a differential to single-ended gain of

2·24

R21R1. Using low value, DC accurate/
AC trimmed resistances for R1-R4 and
a high speed, high CMR op amp provides the good performance.

HIGH SPEED

Op AMp APPLICATIONS

SIMPLE VIDEO LINE RECEIVER USING THE AD818 OP AMP

Figure 2.21

Practically speaking however, at low
frequencies resistor matching can be
more critical to overall CMR than the
rated CMR of the op amp. For example,
the worst case CMR (in dB) of this
circuit due to resistor mismatch is:

1+ R2]

CMR = 201oglO

[

4~

.

In this expression the term "Kr" is a
single resistor tolerance in fractional
form (1%=0.01, etc.), and it is assumed
the amplifier has significantly higher
CMR (~100dB). Using discrete 1%
metal films for R1IR2 and R31R4 yields
a worst case CMR of 34dB, 0.1% types
54dB, etc. Of course 4 random 1%
resistors will on the average yield a
CMR better than 34dB, but not dra-

matically so. A single substrate dual
matched pair thin film network is
preferred, for reasons of best noise
rejection and simplicity. One type
suitable is the Ohmtek 1005, (Reference 6) which has a ratio match of
0.1 %, which will provide a worst case
low frequency CMR of 66 dB.
This circuit has an interesting and
desirable side property. Because of the
resistors it divides down the input
voltage, and the amplifier is protected
against overvol tage. This allows CM
voltages to exceed ±5V supply rails in
some cases without hazard. For operation with ±15V supplies, inputs should
not exceed the supply rails.
At frequencies above 1MHz, the bridge
balance is dominated by AC effects, and
a C1-C2 capacitive balance trim should
be used for best performance. The C1
2 - 25

HIGH SPEED DESIGN TECHNIQUES

adjustment is intended to allow this,
providing for the cancellation of stray
layout capacitance(s) by electrically
matching the net C1-C2 values. In a
given PC layout with low and stable
parasitic capacitance, C1 is best adjusted once in 0.5pF increments, for
best high frequency CMR. Using designated PC pads, production values then
would use the trimmed value. Good AC
matching is essential to achieving good
CMR at high frequencies. C1-C2 should
be types similar physically, such as
NPO (or other stable) ceramic chip style
capacitors.
While the circuit as shown has unity
gain, it can be gain-scaled in discrete
steps, as long as the noted resistor
ratios are maintained. In practice, this
means using taps on a multi-ratio
network for gain change, so as to raise
both R2 and R4, in identical proportions. There is no other simple way to
change gain in this receiver circuit.
Alternately, a scheme for continuous
gain control without interaction with
CMR is to follow this receiver with a
scaling amplifier/driver with adjustable
gain. The similar AD828 dual amplifier

allows this with the addition of only two
resistors.
Video gain/phase performance of this
stage is dependent upon the device used
for U1 and the operating supply voltages. Suitable voltage feedback amplifiers work best at supplies of±10 - ±15V,
which maximizes op amp bandwidth.
And, while many high speed amplifiers
function in this circuit, those expressly
designed with low distortion video
operation perform best. The circuit as
shown can be used with supplies of ±5
to ±15V, but lowest NTSC video distortion occurs for supplies of ±10V or more,
where differential gain/differential
phase errors are less than 0.01%/0.05°.
Operating at ±5V supplies, the distortion rises somewhat, but the lowest
power drain of70mW occurs.
One drawback to this circuit is that it
does load a 750 video line to some
extent, and so should be used with this
loading taken into account. On the plus
side, it has wide dynamic range for both
signal and CM voltages, plus the inherent overvoltage protection.

Active Feedback Differential Line Receiver
Fully integrating the line receiver
function eliminates the resistor-related
drawbacks of the 4 resistor line receiver, improving CMR performance,
ease of use, and overall circuit flexibil-

2-26

ity. An IC designed for this function is
the AD830 active feedback amplifier
(Reference 7,8). Its use as a differential
line receiver with gain is illustrated in
Figure 2.22.

HIGH SPEED Qp

AMP APPLICATIONS

VIDEO LOOP-THROUGH CONNECTION USING THE AD830

6

NC

---------~--------------ZCM
CA= 5.1pF (±15V)
CA = 12pF (±5V)

Figure 2.22

The AD830 operates as a feedback
amplifier with two sets of fully differential inputs, available at pins 1-2 and 34, respectively. Internally, the outputs
of the two stages are summed and drive
a buffer output stage. Both input stages
have high CMR, and can handle differential signals up to ±2V, and CM voltages can range up to -Vs+3V or
+Vs-2.1V, with a ±lV differential input
applied. While the AD830 does not
normally need protection against CM
voltages, if sustained transient voltage
beyond the rails is encountered, an
optional pair of equal value (~200n)
resistances can be used in series with
pins 1-2.
In this device the overall feedback loop
operates so that the differential voltages VI-2 and V3-4 are forced to be
equal. Feedback is taken from the
output back to one input differential

pair, while the other pair is driven by a
differential input signal. An important
point of this architecture is that high
CM rejection is provided by the two
differential input pairs, so CMR isn't
dependent on resistor bridges and their
associated matching problems. The
inherently wideband balanced circuit
and the quasi-floating operation of the
driven input provide the high CMR,
which is typically 100dB at DC.
The general expression for the Ul
stage's gain "G" is like a non-inverting
op amp, or:
G= VOUT =1+R2
VIN
Rl

For lowest DC offset, balancing resistor
R3 is used (equal to Rll I R2).

2 - 27

HIGH SPEED DESIGN TECHNIQUES

In this example of a video "loopthrough" connection, the input signal
tapped from a coax line and applied to
one input stage at pins 1-2, with the
scaled output signal tied to the second
input stage between pins 3-4. With the
R1-R2 feedback attenuation of 211, the
net result is that the output of U1, is
then equal to 2·VIN, i.e., a gain of2.
Functionally, the input and local
grounds are isolated by the CMR of the
AD830, which is typically 75dB at
frequencies below 1MHz, 60dB at
4.43MHz, and relatively supply independent.
With the addition of an output source
termination resistor RT, this circuit has
an overall loaded gain of unity at the

load termination, RL. It is a ground
isolating video repeater, driving the
terminated 750 output line, delivering
a fmal output equal to the original
input, VIN.
NTSC video performance will be dependent upon supplies. Driving a terminated line as shown, the circuit has
optimum video distortion levels for Vs =
±15V, where differential gain is typically 0.06%, and differential phase
0.089 • Bandwidth can be optimized by
the optional5.1pF (or 12pF) capacitor,
CA, which allows a O.ldB bandwidth of
10MHz with ±15V operation. The
differential gain and phase errors are
about 2x at ±5V.

HIGH SPEED CLAMPING AMPLIFIEllS

There are many situations where it is
desirable to clamp the output of an op
amp to prevent overdriving the circuitry which follows. Specially designed
high speed, fast recovery clamping
amplifiers offer an attractive alternative to designing external clamping!
protection circuits. The AD80361
AD8037 low distortion, wide bandwidth
clamp amplifiers represent a significant
breakthrough in this technology. These
devices allow the designer to specify a
high (VH) and low (VL) clamp voltage.
The output of the device clamps when
the input exceeds either of these two
levels. The AD8036/AD8037 offer
superior clamping performance compared to competing devices that use
output-clamping. Recovery time from
overdrive is less than 5ns.
The key to the AD8036 and AD8037's
fast, accurate clamp and amplifier
performance is their proprietary input
nln"""'" r.lI-rnhH,o,.f,,-ro rp'h;Q
T'lOUT rlOQ;O'T"I
4.& ...... ~
0 .....

"'.I.Q..I. ... .L}' """'",.1.'&'&"'''''''",\.01..&."".

.&.&"' .....

""''''..., ...

reduces clamp errors by more than lOx
2-28

over previous output clamp based
circuits, as well as substantially increasing the bandwidth, precision, and
versatility of the clamp inputs.
Figure 2.23 is an idealized block diagram of the AD8036 connected as a
unity gain voltage follower. The primary signal path comprises Al (a
1200V/ps, 240MHz high voltage gain,
differential to single-ended amplifier)
and A2 (a G=+ 1 high current gain
output buffer). The AD8037 differs from
the AD8036 only in that Al is optimized for closed-loop gains of two or
greater.
The input clamp section is comprised of
comparators CH and CL, which drive
switch Sl through a decoder. The unitygain buffers in series with the +VIN,
VH, and VL inputs isolate the input
pins from the comparators and Sl
without reducing bandwidth or precision.

HIGH SPEED

Op AMp APPLICATIONS

AD8036/AD8037 CLAMP AMPLIFIER EQUIVALENT CIRCUIT
RF
1400

1------------,
I

-V~~~------------------------~
A

VOUT

B

c

S1

ABC
0

1

0

VL:::;V 1N :::;V H 1

0

0

0

0

1

V1N > V H

V 1N < V L

' - _ _ _ _ _ _ _ _ _ _ _ _ ...1

Figure 2.23

The two comparators have about the
same bandwidth as Al (240MHz), so
they can keep up with signals within
the useful bandwidth of the ADB036. To
illustrate the operation of the input
clamp circuit, consider the case where
VH is referenced to +lV, VL is open,
and the AD8036 is set for a gain of +1
by connecting its output back to its
inverting input through the recommended 1400 feedback resistor. Note
that the main signal path always
operates closed loop, since the clamping
circuit only affects AI's noninverting
input.

In practice, the ADB036 comes close to
this ideal behavior. As the +VIN input
voltage ramps from zero to IV, the
output of the high limit comparator CH
starts in the off state, as does the
output ofCL. When +VIN just exceeds
VH (practically, by about lBmV), CH
changes state, switching 81 from "A" to
"B" reference level. Since the + input of
Al is now connected to VH, further
increases in +VIN have no effect on the
ADB036's output voltage. The ADB036
is now operating as a unity-gain buffer
for the VH input, as any variation in
VH, for VH > IV, will be faithfully
produced at VOUT.

If a OV to +2V voltage ramp is applied
to the ADB036's +VIN for the connection just described, VOUT should track
+VIN perfectly up to +lV, then should
limit at exactly +lV as +VIN continues
to +2V.

Operation of the ADB036 for negative
input voltages and negative clamp
levels on VL is similar, with comparator
CL controlling Sl. Since the comparators see the voltage on the +VIN pin as
2 -29

HIGH SPEED DESIGN TECHNIQUES

their common reference level, the
voltage VH and VL are defined as
"High" or "Low" with respect to +VIN.
For example, ifVIN is set to zero volts,
VH is open, and VL is +lV, comparator
CL will switch 81 to "C", so the AD8036
will buffer the voltage on VL and ignore
+VIN·
The performance of the AD8036/
AD8037 closely matches the ideal just
described. The comparator's threshold
extends from 60mV inside the clamp
window defined by the voltages on VL
and VH to 60mV beyond the window's
edge. Switch Sl is implemented with
current steering, so that AI's + input

makes a continuous transition from
say, VIN to VH as the input voltage
traverses the comparator's input
threshold from O.9V to 1.OV for VH =
1.OV.
The practical effect of the non-ideal
operation is to soften the transition
from amplification to clamping modes,
without compromising the absolute
clamp limit set by the input clamping
circuit. Figure 2.24 is a graph of VOUT
versus VIN for the AD8036 and a
typical output clamp amplifier. Both
amplifiers are set for G=+l and VH =
+lV.

COMPARISON BETWEEN INPUT AND OUTPUT CLAMPING
1.6 ,---,---,----r---r---,...----,...----,
1.4 r---t----I---+--+--~--+---I

!5

oJI
~

«
~

1.2

t----+---I----+-CLAMP ERROR - 25mV

ADS036

~~ 1.0 I---~ .! - _.1...."'--r--+---+-+-~-~

....
;:)
o

-.-

".

OUTPUT CLAMP AMP

O.S r--~:...---+_--t---t---~--+----I

0.6 - - - - ' - - - - ' - - - - - I ._ _-'-_ _.l..-_--l.._----I
0.6
O.S
1.0
1.2
1.4
1.6
1.8
2.0
INPUT VOLTAGE - +VIN

Figure 2.24

2-30

HIGH SPEED

The worst case error between VOUT
(ideally clamped) and VOUT (actual) is
typically ISmV times the amplifier
closed-loop gain. This occurs when VIN
equals VH (or VL). As VIN goes above
and/or below this limit, VOUT will stay
within 5mV of the ideal value.

Op AMP ,ApPLICATIONS

low levels of distortion when the input
signals approach the clamping voltages.
Figure 2.25 shows the second and third
harmonic distortion for the amplifiers
as the output approaches the clamp
voltages. The input signal is 20MHz,
the output signal is 2V peak-to-peak,
and the output load is 1000.

In contrast, the output clamp
amplifier's transfer curve typically will
show some compression starting at an
input ofO.SV, and can have an output
voltage as far as 200mV over the clamp
limit. In addition, since the output
clamp causes the amplifier to operate
open-loop in the clamp mode, the
amplifier's output impedance will
increase, potentially causing additional
errors, and the recovery time is significantly longer.

Recovery from step voltage which is two
times over the clamping voltage is
shown in Figure 2.26. The input step
voltage starts at +2V and goes to OV
(left-hand traces on scope photo). The
input clamp voltage (VH) is set at +lV.
The right-hand trace shows the output
waveform. The key specifications for
the ADS0361ADS037 clamped amplifiers are summarized in Figure 2.27.

It is important that a clamped amplifier
such as the ADS0361ADS037 maintain

AD8036/AD8037 DISTORTION NEAR CLAMPING REGION,
OUTPUT:: 2V p-p, LOAD 100Q, F 20MHz

=

=

-80
-75
~ -70

AD80373RD
HARMONIC

"0

I

z
o

-65

I

~ -60

.I AD8037 2ND

ex:
o

HARMONIC

t? -55

I

is

~

'" -50

Z

o
:E -45
ex:

<

J:

f--

-40
-35
-30
0.6

~

"'"

AD80363~D7 ~~
HARMONIC

I

"-

\"

""'"' ~

\ IAD803612ND
HARMONIC

VH
VL
G

AD8036 AD8037
+O,5V
+1V
-0,5V
-1V
+1
+2

0,65
0.7
0,75
0,8
0,85
0.9
0,95
ABSOLUTE VALUE OF OUTPUT VOLTAGE - Volts

~

1,0

Figure 2.25
2 - 31

HIGH SPEED DESIGN TECHNIQUES

AD8036 I AD8037 OVERDRIVE (2x) RECOVERY

INPUT

•

+2V
III

OUTPUT

.......~ ~

III

+1V

~,

,

.. ~
~ ....-

l~

III

-

OV

1ns

n
REF

HORIZONTAL SCALE: 1 ns/div
Figure 2.26

AD8036/AD8037 SUMMARY SPECIFICATIONS
•

Proprietary Input Clamping Circuit with Minimized Nonlinear
Clamping Region

•

Small Signal Bandwidth: 240MHz (AD8036), 270MHz (AD8037)

•

Slew Rate: 1S00V/IJs

•

1.Sns Overdrive Recovery

•

Low Distortion: -72dBc @ 20MHz (SOOn load)

•

Low Noise: 4.5nv/"Hz, 2pAl"Hz

•

20mA Supply Current on ±SV

Figure 2.27
2-32

HIGH SPEED

Op AMP APPLICATIONS

flash converter. The output signal is
clamped at +O.lV and -2.lV. This
multi-function clamping circuit therefore performs several important functions as well as preventing damage to
the flash converter which occurs ifits
input exceeds +O.5V, thereby forward
biasing the substrate diode. The
lN57l2 Schottky diode adds further
protection during power-up.

Figure 2.2S shows the AD9002 S-bit,
l25MSPS flash converter driven by the
ADS037 (240MHz bandwidth) clamping amplifier. The clamp voltages on
the ADS037 are set to +0.55 and
-O.55V, referenced to the ±O.5V input
signal, with the external resistive
dividers. The ADS037 also supplies a
gain of two, and an offset of -lV (using
the AD780 voltage reference), to match
the 0 to -2V input range of the AD9002

AD9002 8-BIT, 125MSPS FLASH CONVERTER
DRIVEN BY AD8037 CLAMP AMPLIFIER
0.1J.1F

+5V

8060

~

BIPOLAR
SIGNAL
±O.5V

IN5712
AD9002
FLASH CONVERTER
(8-BITS, 125MSPS)

RT
750

VIN

+5V

\
\

'-{)t---,

SUBSTRATE
DIODE

7500
+
10J.1F

=-1 ±1V

\

AD780
+2.5V

'L

REF
0.1J.1F

R2
3010

·S.2V

V

O.1~

AD8037 OUTPUT
CLAMPS AT +O.1V, -2.1V

R111R3 = R2
4990

2.5 R1
R1 + R3

= 1 VOLT

Figure 2.28

The feedback resistor, R2 = 30ill, is
selected for optimum bandwidth per the
data sheet recommendation. For a gain
of two, the parallel combination of Rl
and R3 must also equal R2:

In addition, the Thevenin equivalent
output voltage of the AD7S0 +2.5V
reference and the R3t R1 divider must
be +1V to provide the -IV offset at the
output of the AD8037.

Rl· R3 = R2 = 30m
Rl+R3
(nearest 1% standard resistor value).

2.5· R1 = 1volt
Rl+R3

2 -33

HIGH SPEED DESIGN TECHNIQUES

Solving the equations yields Rl = 499!l,
R3 = 750!l (using the nearest 1%
standard resistor values).

Further examples of applications of
these fast clamping op amps are given
in Reference 9.

Other input and output voltages ranges
can be accommodated by appropriate
changes in the external resistors.

SINGLE-SUPPLylRAIL-TO-RAIL CONSIDERATIONS
The market is driving high speed
amplifiers to operate at lower power on
lower supply voltages. High speed
bipolar processes, such as Analog
Devices' CB and XFCB, are basically
12V processes, and circuits designed on
these processes are generally limited to
±5V power supplies (or less). This is
ideal for high speed video, IF, and RF
signals, which rarely exceed 5V peakto-peak.
The emphasis on low power, batteryoperated portable communications and
instrumentation equipment has
brought about the need for ICs which
operate on single +5V, and +3V, and
lower supplies. The term single-supply
has various implications, some of which
are often further confused by marketing
hype.
There are many obvious reasons for
lower power dissipation, such as the
ability to function without fans, reliability issues, etc. There are, therefore,
many applications for single-supply
devices other than in systems which
have only one supply voltage. For
example, the lower power dissipation of
a single-supply ADC may be the reason
for its selection, rather than the fact
that it requires just one supply.
There are also systems which truly
operate on a single power supply. In
such cases, it can often be difficult to
maintain DC coupling from a trans2-34

ducer all the way through to the ADC.
In fact, AC coupling is often used in
single-supply systems, with DC restoration preceding the ADC. This may be
required to prevent the loss of dynamic
range which would otherwise occur
because of the need to provide adequate
headroom to an AC coupled signal of
arbitrary duty cycle. In the AC-coupled
portions of such systems, a "falseground" is often created, usually centered between the rails.
There are other disadvantages associated with lower power supply voltages.
Signal swings are limited, therefore
high-speed single-supply circuits tend
to be more sensitive to corruption by
wideband noise, etc. The single-supply
op amp and ADC usually utilize the
same power bus that supplies the
digital circuits, making proper filtering
and decoupling extremely critical.
In order to maximize the signal swing
in single-supply circuits, it is desirable
that a high speed op amp utilize as
much of the supply range as possible on
both the input and output. Ideally, a
true rail-to-rail input op amp has an
input common-mode range that includes both supply rails, and an output
range which does likewise. This makes
for some interesting tradeoffs and
compromises in the circuit design of the
op amp.

HIGH SPEED

In many cases, an op amp may be fully
specified for both dual ±5V and singlesupply operation but neither its input
nor its output can actually swing closer
than about IV to either supply rail.
Such devices must be used in applications where the input and output
common-mode restrictions are not
violated. This generally involves offsetting the inputs using a false ground
reference scheme.

Op AMP APPLICATIONS

speed designs. In many cases, using
devices specified for operation on +5V,
but without true rail inclusive input/
output operation can give good performance. Amplifiers are also becoming
available that are true single supply
rail-to-rail devices. Understanding
single-supply rail-to-rail input and
output limitations is easy if you understand a few basics about the circuitry
inside the op amp. We shall consider
input and output stages separately.

To summarize, there are many
tradeoffs involved in single-supply high-

HIGH SPEED SINGLE SUPPLY AMPLIFIERS
•

Single Supply Offers:
•
Lower Power
•
Battery Operated Portable Equipment
•
Simplifies Power Supply Requirements (one voltage)

•

Design Tradeoffs:
•
Limited Signal Swings Increase Sensitivity to Noise
•
Usually Share Noisy Digital Power Supply
•
DC Coupling Throughout is Difficult
•
Rail-to-Rail Input and Output Increases Signal Swing,
but not Required in All Applications
•
Many Op Amps Specified for Single Supply, but do not
have Rail-to-Rail Inputs or Outputs

Figure 2.29

There is some demand for high-speed
op amps whose input common-mode
voltage includes both supply rails. Such
a feature is undoubtedly useful in some
applications, but engineers should
recognize that there are relatively few
applications where it is absolutely
essential. These should be carefully
distinguished from the many applica-

tions where common-mode range close
to the supplies or one that includes one
of the supplies is necessary, but input
rail-to-rail operation is not.
In many single-supply applications, it is
required that the input go to only one of
the supply rails (usually ground).
2 - 35

HIGH SPEED DESIGN TECHNIQUES

Amplifiers which will handle zero-volt
inputs are relatively easily designed
using PNP differential pairs (or Nchannel JFET pairs) as shown in Figure 2.30 (circuit used in the AD8041,
AD8042, AD8044). The input commonmode range of such an op amp extends

from about 200mV below the negative
supply to within about IV of the positive supply. If the stage is designed
with N-channel JFETs (AD820/AD8221
AD823/AD824), the input commonmode range would also include the
negative rail.

PNP INPUT STAGE ALLOWS
INPUT TO GO TO THE NEGATIVE RAIL
+VS

I---+- -

- +VBIAS

.VS

Figure 2.30

The input stage could also be designed
with NPN transistors (or P-channel
JFETs), in which case the input common-mode range would include the
positive rail and to within about 1Vof
the negative rail; however, this requirement typically occurs in applications
such as high-side current sensing, a
low-frequency measurement application. The OP28210P482 input stage
uses the P-channel JFET input pair
whose input common-mode range
includes the positive rail.
2-36

True rail-to-rail input stages require
two long-tailed pairs (see Figure 2.31),
one ofNPN bipolar transistors (or
N-channel JFETs), the other ofPNP
transistors (or N-channel JFETs).
These two pairs exliibit different offsets
and bias currents, so when the applied
input common-mode voltage changes,
the amplifier input offset voltage and
input bias current does also. In fact,
when both current sources (II and 12)
remain active throughout the entire
input common-mode range, amplifier

HIGH SPEED

input offset voltage is the average offset
voltage of the NPN pair and the PNP
pair. In those designs where the current
sources are alternatively switched off at
some point along the input commonmode voltage, amplifier input offset

Op AMP APPLICATIONS

voltage is dominated by the PNP pair
offset voltage for signals near the
negative supply, and by the NPN pair
offset voltage for signals near the
positive supply.

RAIL-TO-RAIL INPUT STAGE TOPOLOGY
+Vs

Q1
+IN

lJ-----t----j

Vos
.IN

-+-_ _ _ _ _-+-_ _ _ _ _- j -_ _---J

Q -_ _ _ _

R4

.Vs

Figure 2.31

Amplifier input bias current, a function
of transistor current gain, is also a
function of the applied input commonmode voltage. The result is relatively
poor common-mode rejection (CMR),
and a changing common-mode input
impedance over the common-mode
input voltage range, compared to familiar dual-supply devices. These specifications should be considered carefully
when choosing a rail-rail input op amp,
especially for a non-inverting configuration. Input offset voltage, input bias

current, and even CMR may be quite
good over part of the common-mode
range, but much worse in the region
where operation shifts between the
NPN and PNP devices and vice versa.
True rail-to-rail amplifier input stage
designs must transition from one differential pair to the other differential pair
somewhere along the input commonmode voltage range. Devices like the
AD80311AD8032 (specified for ±5V,
+5V, +3V, and +2.5V) have a common2 - 37

HIGH SPEED DESIGN TECHNIQUES

mode crossover threshold at approximately IV below the positive supply.
The PNP differential input stage is
active from about 200mV below the
negative supply to within about IV of
the positive supply. Over this commonmode range, amplifier input offset
voltage, input bias current, CMR, input
noise voltage/current are primarily
determined by the characteristics of the
PNP differential pair. At the crossover
threshold, however, amplifier input
offset voltage becomes the average
offset voltage of the NPNIPNP pairs
and can change rapidly. Also, amplifier
bias currents, dominated by the PNP
differential pair over most of the input
common-mode range, change polarity
and magnitude at the crossover threshold when the NPN differential pair
becomes active.
Applications which require true rail-rail
inputs should therefore be carefully
evaluated, and the amplifier chosen to
ensure that its input offset voltage,
input bias current, common-mode
rejection, and noise (voltage and current) are suitable.
Figure 2.32 shows two typical highspeed op amp output stages. The emitter-follower stage is widely used, but its

2-38

output voltage range is limited to
within about IV of either supply voltage. This is sufficient for many applications, but the common-emitter stage
(used in the AD80411804218044180311
8032 and others) allows the output to
swing to within the transistor saturation voltage, VCE(SAT), of the rails.
For small amounts of load current (less
than 100pA), the saturation voltage
may be as low as 5 to 20mV, but for
higher load currents, the saturation
voltage can increase to several hundred
millivolts (for example, 500mV at
50mA). This is illustrated in Figure
2.33 for the AD8042 (zero-volts in, railto-rail output). The solid curves show
the output saturation voltage of the
PNP transistor (output sourcing current), and the dotted curves the NPN
transistor (sinking current). The saturation voltage increases with increasing
temperature as would be expected.
An output stage constructed of CMOS
FETs can provide true rail-to-rail
performance, but only under no-load
conditions, and in much lower frequency amplifiers. If the output must
source or sink current, the output swing
is reduced by the voltage dropped
across the FETs internal "on" resistance (typically lOOn).

HIGH SPEED Qp

AMP APPLICATIONS

HIGH SPEED SINGLE SUPPLY OP AMP OUTPUT STAGES
COMMON EMITTER

EMITTER FOLLOWER

e---*--+VS

+Vs

OUTPUT

.......--~.Vs

.Vs

Figure 2.32

AD8042 OUTPUT SATURATION VOLTAGE
VERSUS LOAD CURRENT
0.80 r--__r_-.,.--....,..--r----r--r---r-...,-...,..,--,

> 0.70
I

w
~ 0.60

!:i

~ 0.50 I---+-_+--+_-+--+~~~--L.-+--:~_-j

z
o

~ 0.40

a:

::;)

~

0.30

CIJ

I-

K

0.20

1---+--¥--4:~~--+~~~~-+----l--l

I-

::;)

o

0.1 0 J---7"17...."...::".~~..<::.-+----t--+--~

5

10

15

20

25

30

35

40

45

50

LOAD CURRENT - rnA

Figure 2.33
2 - 39

HIGH SPEED DESIGN TECHNIQUES

SINGLE SUPPLY

Op AMP APPLICATIONS

The following section illustrates a few
applications of op amps in single-supply
circuits. All of the op amps are fully
specified for both ±5V and +5V (and

+3V where the design supports it). Both
rail-to-rail and non-rail-to-rail applications are shown.

A Single-Supply lO-bit 20MSPS ADC Direct-Coupled Driver Using the AD80l1
The circuit in Figure 2.34 shows the
AD8011 op amp driving the AD876 10bit, 20MSPS ADC in a direct-coupled
application. The input and output
common-mode voltage of the AD8011
must lie between approximately +1 and
+4V when operating on a single +5V
supply. The input range of the AD876 is
2V peak-to-peak centered around a
common-mode value of +2.6V, well

within the output voltage range of the
AD8011. The upper and lower range
setting voltages are + 1.6V and +3.6V
and are supplied externally to the
AD876. They are easily derived from a
resistor divider driven by a reference
such as the REF198 (+4.096V). The two
taps on the resistor divider should be
buffered using precision single-supply
op amps such as the AD822 (dual).

DC COUPLED SINGLE SUPPLY DRIVER FOR
AD87610-BIT, 20MSPS ADC

+5V

+1.6V
-FS REF
*COMPLETE CIRCUIT
NOT SHOWN

Figure 2.34
2-40

HIGH SPEED

The source is represented as a 2V video
signal referenced to ground. (The
equivalent of a current generator of 0 to
27mA in parallel with the 750 source
resistor. The termination resistor, IVr,
is selected such that the parallel combination ofRT and Rl is 750. The peakto-peak swing at the termination
resistor is lV, so the AD8011 must
supply a gain of two.
The non-inverting input of the AD8011
is biased to a common-mode voltage of
+1.6V (well within it's allowable common-mode range). R3 is calculated as
follows:
When the source voltage is zero-volts,
there is a current of 3.0mA flowing
through Rl (499Q) and into 40.60 to
ground (the equivalent parallel combination of the 75Q source and the 88.7Q
termination resistor is 40.60). The
output of the AD8011 should be +3.6V
under these conditions. This means
that 2mA must flow through R2. Therefore R3 (connected to the +3.6V source)
must supply 1.OmA into the summing
junction (+ 1.6V), and therefore its value
must be 2000Q.
The input of the AD876 has a series
MOSFET switch that turns on and off
at the sampling frequency. This
MOSFET is connected to a hold capacitor internal to the device. The on im-

Op AMP APPLICATIONS

pedance of the MOSFET is about 500,
while the hold capacitor is about 5pF.
In a worst case condition, the input
voltage to the AD876 will change by a
full-scale value (2V) in one sampling
cycle. When the input MOSFET turns
on, the output of the op amp will be
connected to the charged hold capacitor
through the series resistance of the
MOSFET. Without any other series
resistance, the instantaneous current
that flows would be 40mA. This causes
settling problems for the op amp.
The series 100Q resistor limits the
instantaneous current to about 13mA.
This resistor cannot be made too large,
or the high frequency performance will
be affected. In practice, the optimum
value is often determined experimentally.
The sampling MOSFET of the AD876 is
closed for half of each cycle (25ns when
sampling at 20MSPS). Approximately 7
time constants are required for settling
to 10 bits. The series 1000 resistor
along with the 50Q on resistance and
the 5pF hold capacitor form a time
constant of about 750ps. These values
leave a comfortable margin for settling.
Overall, the AD8011 provides adequate
buffering for the AD876 ADC without
introducing distortion greater than that
of the ADC itself.

2 - 41

HIGH SPEED DESIGN TECHNIQUES

A 10-Bit, 40MSPS ADe Low-Distortion Single-Supply ADC Driver Using the
AD8041 Op Amp
A DC coupled application which requires the rail-to-rail output capability
of the ADB041 is shown in Figure 2.35
as a driver for the AD9050 IO-bit,
40MSPS single-supply ADC. The input
range of the AD9050 is IV p-p centered
around +3.3V. The maximum input
signal is therefore +3.BV. The noninverting input of the ADB041 is driven
with a common-mode voltage of +1.65V
which is derived from the unused
differential input of the AD9050. This
allows the op amp to act as a level
shifter for the ground-referenced bipolar input I V p-p signal, with unity gain

as determined by the lkn resistors, RI
and R2.
Op amps with complementary emitter
follower outputs such as the ADBOII
(operating on +5V) generally will exhibit high frequency distortion for
sinewaves with full-scale amplitudes of
IV p-p centered at +3.3V. Because of its
common emitter output stage, however,
the ADB041 is capable of driving the
AD9050, while maintaining a distortion
floor of greater than 66dB with a
4.9MHz fullscale input (see Figure
2.36).

DC COUPLED SINGLE-SUPPLY DRIVER FOR
AD9050 10-BIT, 40MSPS ADC
+5V

R2
10000

+5V
+3.SV
TO+2.SV
VIN(A)

VCM

= +1.65V

Figure 2.35

2-42

SI -80dB @ 10MHz

•

Low Power (±5V Supplies):
•
•

AD8170 - 65mW
AD8180 - 35mW

•
•

AD8174 - 85mW
AD8182 -70mW

Figure 2.50
2-56

HIGH SPEED Op AMp APPLICATIONS

DUAL SOURCE RGB MULTIPLEXER USING THREE 2:1 MUXES
CHANNEL
SELECT

COMPUTER
R

G

B

~

R

~
~

R

G

V
~
V

B

G

MONITOR

B

THREE AD8170 2:1 MUXES

COMPUTER

Figure 2.51

DIGITIZING RGB SIGNALS WITH ONE ADC AND A 4:1 MUX

R

SCANNER

G
ADC
B

CHANNEL SELECT

Figure 2.52
2 - 57

HIGH SPEED DESIGN TECHNIQUES

EXPANDING TWO 4:1 MUXES INTO AN 8:1 MUX
CHANNEL SELECT
TWO AD8174
4:1 MUXES

VIDEO
OUTPUT

VIDEO
INPUTS

Figure 2.53

The AD8116 extends the concepts
above to yield a 16x16 buffered video
crosspoint switch matrix (Figure 2.54).
The 3dB bandwidth is greater than
200MHz, and the O.ldB gain flatness
extends to greater than 40MHz. Channel switching time is less than 30ns to
0.1%. Crosstalk is 70dB and isolation is
90dB (both measured at 10MHz).
Differential gain and phase is 0.01%
and 0.01 0 for a 150n load. Total power
dissipation is 900mW on ±5V supplies.

2-58

The AD8116 includes output buffers
which can be put into a high impedance
state for paralleling crosspojnt stages
so that the off channels do not load the
output bus. The channel switching is
performed via a serial digital control
which can accommodate "daisy chaining" of several devices. The AD8116 is
packaged in a 128-pin TQFP package.
Key specifications for the device are
summarized in Figure 2.55.

HIGH SPEED

Op AMP ,ApPLICATIONS

AD8116 16x16 BUFFERED VIDEO CROSSPOINT SWITCH
AD8116
SERIAL +-tl
.......
~-----------I SERIAL

~

CLOCK

I

CLOCK

SERIAL I ... ~,
V
DATAIN [""J""" ~SO Bit SHIFT REG.
LATCH

I - - - - - - - - - I LATCH
'I..":>+-l--,r4-:'I
fs O

C ENABLE I"
RESET

I ..

r L. . . . rr-----,-I_ _---,
~ PARALLEL LATCH
,f'SO
DECODE
I
16x6:16 Decodersl

I

C ENABLE

o:-~
0

1~

'I

1;;:~~g
~~I..
0

"OumiT

.1,266

~~

~is::"'

r-1-8>~f-

16 ANALOG'~---I
INPUTS ~---I
~'~---I

SWITCH
MATRIX

~

Iii

BUFFER

r- r;-\3>-ft--

RESET

~

!
~

..

1--Ir-;-.j+l+ll~")..;:....j1--

w 1--........

III-

r-

~V-I-13>~ I-I--

:-v

8(/)
..J

1--........

II-

:-v-I-13>~ I--

Z

1--........

~~ I-- ~

r-r-B>~t- ~

16 ANALOG
OUTPUTS

___

w 1--........

r-~

t-~­
t-~"'" L..L..~

Figure 2.54

AD8116 CROSSPOINT SWITCH KEY SPECIFICATIONS
•

16x16 Buffered Inputs and Outputs

•

Output Buffer Disable Feature Allows Expansion

•

3dB Bandwidth 200M Hz, 0.1 dB Bandwidth 40MHz

•

30ns Switching to 0.10/0

•

Differential Gain 0.01 %, Differential Phase 0.010

•

Power Dissipation: 900mW (±5V Supplies)

•

128-pin TQFP, 0.36 Square Inches Area

Figure 2.55

2-59

HIGH SPEED DESIGN TECHNIQUES

HIGH POWER LINE DRIVERS AND ADSL
ADSL (Asymmetric Digital Subscriber
Line) uses the current subscriber line
connection to the central office to transmit data as high as BMbps, almost 300
times the speed of the fastest traditional modem. ADSL uses the entire
bandwidth (approximately IMHz) of
the connection in addition for the
modulation scheme called Discrete
Multi Tone (DMT).
Although high-speed fiber links already
exist, it is still too difficult and expensive to bring them directly to every
residence. ADSL uses the existing
infrastructure for "the last mile" connecting the home and the local central
office (which already has a high-speed
fiber link to the national network).
Many applications are uneven (asymmetric) in their bandwidth needs sending more information in one direction than the other. Typically, a user
will request a video channel, ask for
information from a central database, or
view complex graphical images on a
web page. All of these applications
require considerable bandwidth. In
contrast, the user may only send commands or files back up to the server.
Realizing this, ADSL was designed to
deliver a bigger downstream capacity to
the home, while having a smaller twoway capacity.
Key to the ADSL system is the requirement for a low-distortion differential
drive amplifier which delivers approxi-

2-60

mately 40V p-p into a 60n differential
load impedance. The AD815 dual high
current driver can deliver 40V p-p
differential into a 50n load (corresponding to 400mA peak current!) using the
application circuit shown in Figure
2.56. Low harmonic distortion is also
required for ADSL applications, since it
affects system bit error rates. The
typical distortion of the device is shown
in Figure 2.57 for 50n and 200n differentialloads.
There are three AD815 models, two are
available in a 15-pin power package,
and the third as a 24-pin thermally
enhanced SOIC. The 15-pin power
package (AD815AY-through hole and
AD815AVR-surface mount) has a low
thermal resistance (9JA = 41°CIW)
which can be reduced considerably (to
eJA = 16 °CIW) by connecting the
package to an area of copper which acts
as a heat sink. The AD815 incorporates
a thermal shutdown circuit to protect
the die from thermal overload.
The AD815 also has applications as a
general purpose high current coil,
transformer, or twisted pair cable
driver, a CRT convergence adjustment
control, or a video signal distribution
amplifier. Each amplifier in the AD815
is capable of driving 6 back-terminated
75n video loads with a differential gain
and phase of 0.05% and 0.45° respec.
tively.

HIGH SPEED

Op AMP APPLICATIONS

ADSL DIFFERENTIAL LINE DRIVER USING THE AD815
+15V

+ D----'V'V\r----I
.---------<) +

VIN

=

Vo=

4Vp-p

RL
120n

II

40Vp-p

V

OUT =
40Vp-p

1:2
TRANSFORMER
-15V

Figure 2.56

THD VS. FREQUENCY FOR AD815 DIFFERENTIAL DRIVER
-40

V~ =1~1~V

I--

~ -50
"C

I--

I

~

~

I--

-

I

I

G =+10
VOUT = 40V p-p

-60

)1

o

/

~ -70

/'

i5
()

Z -80
o
:s:
a:

I--

~~

(DIFFERENTIAL)

/

/

I

I RL =200n
I~

~ -90

--

...J

.:

~-100

-110
100

~/

RL = son

I

1k

L/

(DIFFERENTIAL)

10k
100k
FREQUENCY - Hz

1M

-

-I-

10M

Figure 2.57
2 - 61

HIGH SPEED DESIGN TECHNIQUES

HIGH SPEED PHOTODIODE PREAMPS
Photodiodes generate a small current
which is proportional to the level of
illumination. They have many applications ranging from precision light
meters to high-speed fiber optic receivers.
The equivalent circuit for a photo diode
is shown in Figure 2.58. One of the
standard methods for specifying the
sensitivity of a photodiode is to state its

short circuit photocurrent (Isc) at a
given light level from a well defined
light source. The most commonly used
source is an incandescent tungsten
lamp running at a color temperature of
2850K. At lOOfc (foot-candles) illumination (approximately the light level on
an overcast day), the short circuit
current is usually in the picoamps to
hundreds of microamls range for small
area (less than Imm ) diodes.

PHOTODIODE EQUIVALENT CIRCUIT

RS «
INCIDENT
LIGHT

~

IDEAL
DIODE

RSH

.---~------~-------+----~

t

PHOTO
CURRENT

""100kQ TO
100GQ

Figure 2.58

The short circuit current is very linear
over 6 to 9 decades of light intensity,
and is therefore often used as a measure of absolute light levels. The open
circuit forward voltage drop across the
photodiode varies logarithmically with
light level, but, because of its large
2-62

temperature coefficient, the diode
voltage is seldom used as an accurate
measure of light intensity.
The shunt resistance is usually in the
order of several hundred lu~ to more
than IGQ at room temperature, and

HIGH SPEED

decreases by a factor of two for every
10°C rise in temperature. Diode capacitance is a function of junction area and
the diode bias voltage. A value of 10 to
50pF at zero bias is typical for small
area diodes.
Photodiodes may either be operated
with zero bias (photovoltaic mode) or
reverse bias (photoconductive mode) as
shown in Figure 2.59. The most precise
linear operation is obtained in the
photovoltaic mode, while higher switching speeds are realizable when the
diode is operated in the photoconductive
mode. Under reverse bias conditions, a
small amount of current called dark
current will flow even when there is no
illumination. There is no dark current

Op AMP APPLICATIONS

in the photovoltaic mode. In the photovoltaic mode, the diode noise is basically the thermal noise generated by
the shunt resistance. In the photoconductive mode, shot noise due to conduction is an additional source of noise.
Photodiodes are usually optimized
during the design process for use in
either the photovoltaic mode or the
photoconductive mode, but not both.
Optimizing photodiode preamplifiers is
probably one of the most challenging of
design problems, especially if high
bandwidth and direct coupling is required. Figure 2.60 shows a basic
photo diode preamp designed with an op
amp connected as a current-to-voltage
converter.

PHOTODIODE MODES OF OPERATION

PHOTOCONDUCTIVE

PHOTOVOLTAlC
·
·
•
•

Zero Bias
No Dark Current
Precision Applications
Low Noise (Johnson)

·
·
·
·

Reverse Bias
Dark Current Exists
High Speed Applications
Higher Noise (Johnson + Shot)

Figure 2.59

2 - 63

HIGH SPEED DESIGN TECHNIQUES

HIGH BANDWIDTH PHOTODIODE PREAMP
EQUIVALENT CIRCUIT
10 = IS

+

I DARK

C = CD + C IN
1
R SH

» R2
VN
--7
IS

RSH

I

CD

1N

C

fu = OP AMP GSW PRODUCT
FOR R2

SIGNAL SW

=2nR

=

100j.-tA

V
OUT

=10V

ID

1
C

2 2

=100kQ

Figure 2.60

The sensitivity of the circuit is determined by the amount of photodiode
current multiplied by the feedback
resistor R2. The key parameters of the
diode (see Figure 2.61) are its sensitivity (output current as a function of
illumination level), dark current (the
amount of current which flows due to
the reverse bias voltage when the diode
is not illuminated), risetime, shunt
capacitance, and shunt resistance.

diode applications, the diode is operated
in the reverse-biased or photoconductive
mode. This greatly lowers the diode
junction capacitance, but causes a
small amount of dark current to flow
even when the diode is not illuminated
(we will show a circuit which compensates for the dark current error later in
the section).

The key parameters of the op amp are
its input voltage and current noise, bias
current, unity gain-bandwidth product,
fu, and input capacitance, Cin.

This photodiode is linear with illumination up to approximately 50 to lOOpA. of
output current. The dynamic range is
limited by the total circuit noise and
the diode dark current (assuming no
dark current compensation).

The Motorola 5082-4204 PIN Photodiode will be used as an example for our
discussion. Its characteristics are given
in Figure 2.61. It is typical of many
commercially available PIN photodiodes. As in most high-speed photo-

Using the simple circuit shown in
Figure 2.60, assume that we wish to
have a full scale output of lOV for a
diode current of lOOpA.. This. determines the value of the feedback resistor
R2 to be lOV/lOOpA. = lOOkn.

2-64

HIGH SPEED Qp

AMP APPLICATIONS

MOTOROLA 5082·4204 PHOTODIODE
•

Sensitivity: 350IJA @ 1mW, 900nm

•

Maximum Linear Output Current: 100IJA

•

Area: 0.002cm2 (0.2mm2)

•

Capacitance: 4pF @ 10V reverse bias

•

Shunt Resistance: 10 11 n

•

Risetime: 10ns

•

Dark Current: 600pA @ 10V reverse bias

Figure 2.61

Analysis of Frequency Response and Stability
The photodiode preamp model is the
classical second-order system shown in
Figure 2.62, where the IIV converter
has a total input capacitance Cl (the
sum of the diode capacitance and the op
amp input capacitance). The shunt
resistance of the photodiode is neglected
since it is much greater than R2, the
feedback resistor.

The net input capacitance, Cl, forms a
pole at a frequency fp in the noise gain
transfer function as shown in the Bode
plot.
f

_
1
p - 21tR2Cl·

Note that we are neglecting the effects
of the compensation capacitor C2 and
are assuming that it is small relative to
C 1 and will not significantly affect the
pole frequency fp when it is added to
the circuit. In most cases, this approximation yields results which are close
enough, considering the other variables
in the circuit.
If left uncompensated, the phase shift
at the frequency of intersection, fx, will
cause instability and oscillation. Introducing a zero at fx by adding the feedback capacitor C2 stabilizes the circuit
and yields a phase margin of about 45
degrees.

2- 65

HIGH SPEED DESIGN TECHNIQUES

COMPENSATING FOR INPUT CAPACITANCE IN A
CURRENT-TO-VOLTAGE CONVERTER USING VFB OP AMP
C2
R2

C1

1
21t R2C1

IA(s}1

1
" UNCOMPENSATED

21tR2C2

/

I /
-

- COMPENSATED

fX=~
C2 =

1

C1
21t R2 • fu

FOR 45° PHASE MARGIN

Figure 2.62

f

_
1
x - 21tR2C2

Since fx is the geometric mean of fp and
the unity-gain bandwidth frequency of
the op amp, fu,

This value ofC2 will yield a phase
margin of about 45 degrees. Increasing
the capacitor by a factor of2 increases
the phase margin to about 65 degrees
(see References 4 and 5).
In practice, the optimum value of C2
should be optimized experimentally by
varying it slightly to optimize the
output pulse response.

These equations can be solved for C2:

C2=~

V~·

2-66

HIGH SPEED

Op AMP APPLICATIONS

Selection of the Op Amp
The photodiode preamp should be a
wideband FET-input one in order to
minimize the effects of input bias
current and allow low values of photocurrents to be detected. In addition, if
the equation for the 3dB bandwidth, fx,
is rearranged in terms of fu, R2, and
Cl, then

f-~

x-V~'

where Cl = Cn + Cin
By inspection of this equation, it is
clear that in order to maximize fx, the

FET-input op amp should have both a
high unity gain-bandwidth product, fu,
and a low input capacitance, Cin. In
fact, the ratio of fu to Cin is a good
figure-of-merit when evaluating different op amps for this application. Figure
2.63 compares a number of FET-input
op amps suitable for photodiode
preamps.
By inspection, the AD823 op amp has
the highest ratio of unity gain-bandwidth product to input capacitance, in
addition to relatively low input bias
current. For these reasons, it was
chosen for the wideband photodiode
preamp design.

FET-INPUT OP AMP COMPARISON TABLE
FOR WIDE BANDWIDTH PHOTODIODE PREAMPS
Unity GBW
Product,
fu (MHz)

Input
Capacitance
Cin (pF)

fu/Cin
(MHzlpF)

Input Bias
Current
Ib (pA)

Voltage Noise
@10kHz
(nV/--JHz)

AD823

16

1.8

8.9

3

16

AD843

34

6

5.7

600

19

AD744

13

5.5

2.4

100

16

AD845

16

8

2

500

18

AD745*

20

20

1

250

2.9

AD645

1

1

1

1.5

8

AD820

1.9

2.8

0.7

2

13

AD743

4.5
...

20

0.2

250

2.9

Stable for NOise Gains ~ 5, Usually the Case, Since
High Frequency Noise Gain =1 + C1/C2, and C1 Usually ~ 4C2.

Figure 2.63
2 - 67

HIGH SPEED DESIGN TECHNIQUES

Using the diode capacitance, Cn=4pF,
and the AD823 input capacitance,
Cin=1.8pF, the value of Cl = Cn+Cin =
5.8pF. Solving the above equations
using Cl=5.8pF, R2=lOOkn, and
fu =l6MHz, we find that:

=

=

=

274kHz
O.76pF
2.lMHz.

In the final design (Figure 2.64), note
that the lOOkn resistor is replaced with
three 33.2kn film resistors to minimize
stray capacitance. The feedback capaci-

tor, C2, is a variable l.5pF ceramic and
is adjusted in the final circuit for best
bandwidth/pulse response. The overall
circuit bandwidth is approximately
2MHz.
The full scale output voltage of the
preamp for lOOpA diode current is lOV,
and the error (RTO) due to the photodiode dark current of 600pA is 60mV.
The dark current error can be canceled
using a second photodiode of the same
type in the non-inverting input of the
op amp as shown in Figure 2.64.

2MHz BANDWIDTH PHOTODIODE PREAMP
WITH DARK CURRENT COMPENSATION
~0.8pF

C1
Co

=Co +CIN

·10V

33.21<0 33.21<0

=4pF, CIN =1.8pF
~
01

R2

=1001<0

C1
5.8pF

02
01, 02: HP-5082-4204
·15V
0.1/-L F

LOW LEAKAGE
POLYSTYRENE

1001<0

Figure 2.64

2-68

HIGH SPEED

Op AMP APPLICATIONS

Photo diode Preamp Noise Analysis
As in most noise analyses, only the key

contributors need be identified. Because
the noise sources combine in an RSS
manner, any single noise source that is
at least three or four times as large as
any of the others will dominate.
In the case of the wi deb and photodiode
preamp, the dominant sources of output
noise are the input voltage noise of the
op amp, Vnh and the resistor noise due
to R2, VnR2. The input current noise of
the FET-input op amp is negligible. The
shot noise of the photodiode (caused by
the reverse bias) is negligible because of
the filtering effect of the shunt capacitance C 1. The resistor noise is easily
calculated by knowing that a lkn
resistor generates about 4nV/...JHz,
therefore, a lOOkn resistor generates
40nV/...JHz. The bandwidth for integration is the signal bandwidth, 2.lMHz,
yielding a total output rms noise of:

The factor of 1.57 converts the approximate single-pole bandwidth of 2.lMHz
into the equivalent noise bandwidth.
The output noise due to the input
voltage noise is obtained by multiplying

the noise gain by the voltage noise and
integrating the entire function over
frequency. This would be tedious if done
rigorously, but a few reasonable approximations can be made which
greatly simplify the math. Obviously,
the low frequency lIf noise can be
neglected in the case of the wideband
circuit. The primary source of output
noise is due to the high-frequency noisegain peaking which occurs between fp
and fu. If we simply assume that the
output noise is constant over the entire
range of frequencies and use the maximum value for AC noise gain
[l+(ClIC2)], then

The total rms noise referred to the
output is then the RSS value of the two
components:

The total output dynamic range can be
calculated by dividing the full scale
output signal (lOV) by the total output
rms noise, 260J.lVrms, and converting to
dB, yielding approximately 92dB.

2 - 69

HIGH SPEED DESIGN TECHNIQUES

EQUIVALENT CIRCUIT FOR OUTPUT NOISE ANALYSIS

=

C1 5.8pF
C2 = 0.76pF
R2 = 100kn
Vn (TOTAL)

1+~- - - - - - - - - - - - - C2

NOISE GAIN

1

I

I
fx

fu

274kHz

2.1MHz

16MHz

Vni(out) ~ Vni

•

VnR2 (out) ~~ 4kTR2 .1.57fX

= 731!V rms

•

2
2
Vn(TOTAL) = 250 + 73

~

= 260l! V rms

•

DYNAMIC RANGE

(1+

g~ )~ 1.57fX

fp
•

= 250l! V rms

10V ]

= 20 log [ 260l! V

Figure 2.65

2-70

I

= 92dB

I

HIGH SPEED

Op AMP APPLICATIONS

REFERENCES
1.

Walt Kester, Maintaining Transmission Line Impedances on the PC Board,
within Chapter 11 of System Applications Guide, Analog Devices, 1993.

2.

Joe Buxton, Careful Design Tames High-Speed OpAmps,
Electronic Design, April 11, 1991.

3.

Walt Jung, Op Amps in Line-Driver and Receiver Circuits, Partl
Analog Dialogue, Vol. 26-2, 1992.

4.

William R. Blood, Jr., MECL System Design Handbook (HB205, Rev.l),
Motorola Semiconductor Products, Inc., 1988.

5.

Dave Whitney, Walt Jung,Applying a High-Performance Video Operational
Amplifier, Analog Dialogue, 26-1, 1992.

6.

Ohmtek, Niagara Falls, NY, (716) 283-4025.

7.

Walt Kester, Video Line Receiver Applications Using the AD830 Active
Feedback Amplifier Topology, within Chapter 11 of System
Applications Guide, Analog Devices, 1993.

8.

Walt Jung,Analog-Signal-Processing Concepts Get More Efficient,
Electronic Design Analog Applications Issue, June 24, 1993.

9.

Peter Checkovich, Understanding and Using High-Speed Clamping
Amplifiers, Analog Dialogue, Vol. 29-1, 1995.

10.

Walt Jung, Scott Wurcer, Design Video Circuits Using High-Speed Op-Amp
Systems, Electronic Design Analog Applications Issue,
November 7, 1994.

11.

W. A. Kester, PCM Signal Codecs for Video Applications, SMPTE Journal,
No. 88, November 1979, pp. 770-778.

12.

IEEE Standard for Performance Measurements ofAID and D I A Converters
for PCM Television Circuits, IEEE Standard 746-1984.

13.

Practical Analog Design Techniques, Chapters 1, 2, and 4, 1995, Analog
Devices.

14.

Amplifier Applications Guide, 1992, Analog Devices.

15.

Jerald G. Graeme, Photodiode Amplifiers: Op Amp Solutions, McGraw
Hill, 1995.

2 -71

HIGH SPEED DESIGN TECHNIQUES

SECTION 3
RF/IF SUBSYSTEMS

•
•
•
•
•
•
•

Dynamic Range Compression
LinearVCAs
Log/Limiting Amplifiers
Receiver Overview
Multipliers, Modulators, and Mixers
Modulation I Demodulation
Receiver Subsystems

HIGH SPEED DESIGN TECHNIQUES

RFIIF SUBSYSTEMS

SECTION 3
RFIIF SUBSYSTEMS
Walt Kester, James Bryant, Bob Clarke,
Barrie Gilbert
DYNAMIC RANGE COMPRESSION
In many cases, a wide dynamic range is
an essential aspect of a signal, something to be preserved at all costs. This
is true, for example, in the high-quality
reproduction of music and in communications systems. However, it is often
necessary to com press the signal to a
smaller range without any significant
loss of information. Compression is
often used in magnetic recording, where
the upper end of the dynamic range is
limited by tape saturation, and the
lower end by the granularity of the
medium. In professional noise-reduction
systems, compression is "undone" by
precisely-matched nonlinear expansion
during reproduction. Similar techniques
are often used in conveying speech over
noisy channels, where the performance
is more likely to be measured in terms
of word-intelligibility than audio fidelity. The reciprocal processes of compressing and expanding are
implemented using "compandors", and
many schemes have been devised to
achieve this function.
There is a class of linear dynamic range
compression systems where the gain of
the amplifiers in the signal processing
chain is independent of the instantaneous amplitude of the signal, but is
controlled by a closed loop system in
such a way as to render the output
(that is the peak, or rms value) essentially constant. The harmonic distortion
is relatively low. These systems use
what are often called variable-gain

amplifr,ers. While correct, this lacks
precision, because nonlinear amplifiers
(such as log amps) also exhibit variable
gain, but in direct response to the
signal magnitude. The term voltage
controlled amplifr,er (VCA) is preferred
in this context; it clearly describes the
way in which the gain control is implemented, while allowing latitude in
regard to the actual circuit means used
to achieve the function. The gain may
be controlled by a current within the
circuit, but usually a voltage. Analog
multipliers may be used as VCAs, but
there are other topologies which will be
discussed later in this section.

Logarithmic amps fmd applications
where signals having wide dynamic
ranges (perhaps greater than lOOdB)
must be processed by elements, such as
ADCs, which may have limited dynamic
ranges. Log amps have maximum
incremental gain for small signals; the
gain decreases in inverse proportion to
the magnitude of the input. This permits the amplifier to accept signals
with a wide input dynamic range and
compress them substantially.
Log amps provide nonlinear dynamic
range compression and are used in
applications where low harmonic distortion is not a requirement. All types of
log amps produce a low dynamic range
output without the need to first acquire
some measure of the signal amplitude
for use in controlling gain.
3-1

HIGH SPEED DESIGN TECHNIQUES

We will first examine linear compression techniques using voltage-controlled
amplifiers within automatic-gaincontrol (AGe) loops. Nonlinear signal
compression using log amps is then
discussed.

Both AGe loops using veAs and log
amps make excellent building blocks for
highly integrated RFIIF subsystems for
signal processing in communications
systems as will be demonstrated.

RF IIF SUBSYSTEM BUILDING BLOCKS
•

•

Signal Dynamic Range Compression Techniques
•

Linear: Automatic Gain Control Loop (AGC) using
Voltage Controlled Am plifier (VCA) and Detector

•

Non-Linear: Demodulating I Limiting Logarithmic
Amplifiers

Modulation I Demodulation: In-Phase and Quadrature (I/Q)
and Polar (Amplitude and Phase)
•

Dynamic Range Compression Required

•

IF Subsystems: AGC, Log I Limiting, RSSI, Mixers

Figure 3.1

AUTOMATIC GAIN CONTROL (AGC) AND
VOLTAGE-CONTROLLED AMPLIFIERS (VCAs)
In radio systems, the received energy
exhibits a large dynamic range due to
the variability of the propagation path,
requiring dynamic-range compression
in the receiver. In this case, the wanted
information is in the modulation envelope (whatever the modulation mode),
noi in ihe absolute magnitude of the
carrier. For example, a 1MHz carrier
3-2

modulated at 1kHz to a 30% modulation depth would convey the same
information, whether the received
carrier level is at OdBm or -120dBm.
Some type of automatic gain control
(AGe) in the receiver is generally
utilized to restore the carrier amplitude
io some normalized reference ievei, in
the presence of large input fluctuations.

RFIIF SUBSYSTEMS

AGC circuits are dynamic-range compressors which respond to some metric
of the signal- often its mean amplitude
- acquired over an interval corresponding to many periods of the carrier.
Consequently, they require time to
adjust to variations in received signal
level. The time required to respond to a
sudden increase in signal level can be

reduced by using peak detection methods, but with some loss of robustness,
since transient noise peaks can now
activate the AGC detection circuits.
Nonlinear filtering and the concept of
"delayed AGC" can be useful in optimizing an AGC system. Many tradeoffs are
found in practice; Figure 3.2 shows a
basic system.

A TYPICAL AUTOMATIC GAIN CONTROL (AGC) SYSTEM
VOLTAGE CONTROLLED AMP
VXsinrot
INPUT: UNKNOWN
AMPLITUDE

OUTPUT: FIXED
AMPLITUDE

CONTROL/
VOLTAGE
MEASURES
SIGNAL
LEVEL

• RECTIFIER
DETECTOR
'------r-----'

• RMS/DC CONVERTER
•

PEAK DETECTOR

LPF

Figure 3.2

It is interesting to note that in an AGC
loop actually has two outputs. The
obvious output is the amplitude-stabilized signal. The less obvious output is
the control voltage to the VCA, which is
in reality, a measure of the average

amplitude of the input signal. If the
system is precisely scaled, the control
voltage may be used as a measure of
the input signal, sometimes referred to
as a received signal strength indicator
(RSSI).

3-3

HIGH SPEED DESIGN TECHNIQUES

VOLTAGE CONTROLLED AMPLIFIERS (VCAs)

An analog multiplier can be used as a
variable-gain amplifier as shown in
Figure 3.3. The control voltage is applied to one input, and the signal to the
other. In this configuration, the gain is
directly proportional to the control
voltage.

Most VCAs made with analog multipliers have gain which is linear in volts
with respect to the control voltage, and
they tend to be noisy. There is a demand, however, for a VCA which combines a wide gain range with constant
bandwidth and phase, low noise with
large signal-handling capabilities, and
low distortion with low power consumption, while providing accurate, stable,
linear-in-dB gain. The AD600, AD602,
and AD603 achieve these demanding

and conflicting objectives with a unique
and elegant solution - the X_AMPTM (for
exponential amplifrer). The concept is
simple: a fixed-gain amplifier follows a
passive, broadband attenuator
equipped with special means to alter its
attenuation under the control of a
voltage (see Figure 3.4). The amplifier
is optimized for low input noise, and
negative feedback is used to accurately
define its moderately high gain (about
30 to 40dB) and minimize distortion.
Since this amplifier's gain is fixed, so
also are its ac and transient response
characteristics, including distortion and
group delay; since its gain is high, its
input is never driven beyond a few
millivolts. Therefore, it is always operating within its small signal response
range.

USING A MULTIPLIER AS A
VOLTAGE-CONTROLLED AMPLIFIER (VCA)

CONTROL
V INPUT
C

Vo

VIN.
=K

( 1 +~
R) Vc
R1

Figure 3.3
3-4

RFIIF SUBSYSTEMS

SINGLE CHANNEL OF THE DUAL 30MHz AD600/AD602 X-AMP
GAT1

PRECISION PASSIVE
INPUT ATTENUATOR

C1HI
C1LO

GAIN CONTROL
INTERFACE

~-------

RF2
2.24kU (AD600)
694(2 (AD602)

--------.

RF1
20U
62.511

FIXED GAIN

A1LO o-t__--+--__4....--+--~--t__-_+_-__4--~
R - 2R LADDER NETWORK
(RO 100il :t 2%)

A1CM

AMPLIFIER
41.07dB (AD600)
31.07dB (AD602)

=

Figure 3.4

GAIN OF THE AD600/AD602
AS A FUNCTION OF CONTROL VOLTAGE
45
~

40

/~

35

./

./

30
25
al

"'0
I

;7

20

z 15


~~

1

1/

0

5

~

~

~iII

-1

1.1

-2

V

~iII

-3

VV

-4

JI

-5
100~V

10I-LV

1mV

10mV

100mV

1V

10V

INPUT SIGNAL - V RMS

Figure 3.11

DEVIATION FROM THE IDEAL
LOGARITHMIC OUTPUT
2.5
2.0

1.5
~
I

1.0

~

0.5

a:

ffi

,"

0

:~

I-

~ -0.5

~
o

,.

J~

,

~

"

I~

I'"

1'..-

~

J

-1.0

-1.5
-2.0

IJ

~

-2.5
10I-LV

100~V

1mV

10mV

100mV

INPUT SIGNAL - V RMS

Figure 3.12
3-12

1V

10V

RFIIF SUBSYSTEMS

By suitable choice of the input attenuator, R1 +R2, this could be centered to
cover any range from 25JlV to 250mV
to, say, 1mV to 10V, with appropriate
correction to the value of Vz. (Note that
VS is not affected by the changes in the
range). The gain ripple of ±O.2dB seen
in this curve is the result of the finite
interpolation error of the X-AMP. It
occurs with a periodicity of 12dB twice the separation between the tap
points in each amplifier section.
This ripple can be canceled whenever
the X-AMP stages are cascaded by
introducing a 3dB offset between the

two pairs of control voltages. A simple
means to achieve this is shown in
Figure 3.13: the voltages at C1HI and
C2HI are "split" by ±46.875mV, or
±1.5dB. Alternatively, either one of
these pins can be individually offset by
3dB, and a 1.5dB gain adjustment
made at the input attenuator (Rl+R2).
The error curve shown in Figure 3.14
demonstrates that over the central
portion of the range, the output voltage
can be maintained very close to the
ideal value. The penalty for this modification is higher errors at both ends of
the range.

METHOD FOR CANCELING THE
GAIN-CONTROL RIPPLE

-6V-4-_ _-t
DEC

U1
AD600

U2
AD636

C2
2j.1.F

r--------------I
I
I

: -6V
: DEC---V\l~~-\I'V~~~\I~'~~~V~'v--I

I

..----------- ------..-.. ------.--------~
3dB OFFSET
I

~-----------NC

=NO CONNECT

MODIFICATION

Figure 3.13

3-13

HIGH SPEED DESIGN TECHNIQUES

LOGARITHMIC ERROR USING THE
PREVIOUS CIRCUIT MODIFICATION
2.5

2.0

1.5
III
'C
I

1.0

ffi

0

c:: 0.5
o
c::

_,,;11

( ""'""

I-

~ -0.5

I-

5 -1.0
II

-1.5

r

-2.0
-2.5
10l!V

100l!V

1mV

10mV

100mV

1V

10V

INPUT SIGNAL - V RMS

Figure 3.14

A 40MHz, 80dS, LOW-NOISE
AGC AMPLIFIER USING THE AD603
+10V

THIS CAPACITOR SETS
AGC TIME CONSTANT

AGCLINE
RS
S.49k!l

R7

3.48k!l
5.SV

NOTES:
1 RT PROVIDES A

RS
1.0Sk!l

S.SV

son INPUT IMPEDANCE

2 C3 AND C5 ARE TANTALUM

Figure 3.15
3-14

RFIIF SUBSYSTEMS

Figure 3.15 shows the ease with which
the AD603 (90MHz X-AMP) can be
used as a high speed AGC amplifier.
The circuit uses few parts, has a linearin-dB gain, operates from a single
supply, uses two cascaded amplifiers in
sequential gain mode for maximum SIN
ratio (see the data sheet for the AD600/
AD602, or AD603 for a complete description of the methods for cascading
X-AMPS), and external resistor programs each amplifier's gain. It also
uses a simple temperature-compensated detector.
The circuit operates from a single + 10V
supply. Resistors R1, R2 and R3, R4
bias the common pins of A1 and A2 at
5V. This pin is a low impedance point
and must have a low impedance path to
ground, provided by the 100pF tantalum capacitor and the O.lllF ceramic
capacitors.
The cascaded amplifiers operate in
sequential gain. The offset voltage
between the pins 2 (GNEG) of A1 and
A2 is 1.05V (42.14dB x 25mV/dB),
provided by a voltage divider consisting
of resistors R5, R6, and R7. Using
standard values, the offset is not exact
but is not critical for this application.
The gain of both A1 and A2 is programmed by resistors R13 and R14,
respectively, to be about 42dB; thus the
maximum gain of the circuit is twice
that, or 84dB. The gain-control range
can be shifted up by as much as 20dB
by appropriate choices ofRI3 and R14.
The circuit operates as follows. Al and
A2 are cascaded. Capacitor C1 and the
lOOn of resistance at the input of A1
form a time-constant of lOllS. C2 blocks
the small DC offset voltage at the
output of Al (which might otherwise
saturate A2 at its maximum gain) and

introduces a high-pass corner at about
16kHz, eliminating low frequency
noise.
A half-wave detector is used based on
Q1 and R8. The current into capacitor
CAV is the difference between the
collector current of Q2 (biased to be
300pA at 27°C, 300K) and the collector
current ofQ1, which increases with the
amplitude of the output signal. The
automatic gain control voltage, VAGC,
is the time-integral of this error current. In order for VAGC (and thus the
gain) to remain insensitive to shortterm amplitude fluctuations in the
output signal, the rectified current in
QI must, on average, exactly balance
the current in Q2. If the output of A2 is
too small to do this, VAGC will increase, causing the gain to increase,
until QI conducts sufficiently.
Consider the case where R8 is zero and
the output voltage VOUT is a square
wave at, say 455kHz, that is, well
above the corner frequency of the
control loop.
During the time VOUT is negative with
respect to the base voltage ofQ1, Q1
conducts; when VOUT is positive, it is
cut off. Since the average collector
current ofQ1 is forced to be 300pA, and
the square wave has a duty cycle of 1:1,
QI's collector current when conducting
must be 600pA. With R8 omitted, the
peak amplitude ofVOUTis forced to be
just the VBE ofQ1 at 600pA, typically
about 700mV, or 2VBE peak-to-peak.
This voltage, hence the amplitude at
which the output stabilizes, has a
strong negative temperature coefficient
(TC), typically -1. 7mV/oC. Although
this may not be troublesome in some
applications, the correct value ofR8 will
render the output stable with temperature.
3-15

HIGH SPEED DESIGN TECHNIQUES

To understand this, first note that the
current in Q2 is made to be proportional to absolute temperature (PTAT).
For the moment, continue to assume
that the signal is a square wave.
When Ql is conducting, VOUT is now
the sum ofVBE and a voltage which is
PTAT and which can be chosen to have
an equal but opposite TC to that of
VBE. This is actually nothing more
than an application of the "bandgap
voltage reference" principle. When R8 is
chosen such that the sum of the voltage
across it and the VBE ofQ1 is close to
the bandgap voltage of about 1.2V,
VOUT will be stable over a wide range
of temperatures, provided, of course,
that Q1 and Q2 share the same thermal environment.
Since the average emitter current is
BOOpA during each half-cycle of the
square wave, a resistor of 833il would
add a PTAT voltage of 50 OmV at 300K,
increasing by 1.6BmV/oC. In practice,
the optimum value will depend on the
type of transistor used, and, to a lesser
extent, on the waveform for which the
temperature stability is to be optimized; for the inexpensive 2N3904/
2N390B pair and sine wave signals, the
recommended value is 806il.

3 -16

This resistor also serves to lower the
peak current in Ql when more typical
signals (usually sinusoidal) are involved, and the 1.8kHz lowpass filter it
forms with CAV helps to minimize
distortion due to ripple in VAGC. Note
that the output amplitude under si,ne
wave conditions will be higher than for
a square wave, since the average value
of the current for an ideal rectifier
would be 0.637 times as large, causing
the output amplitude to be 1.2V/
0.B37=1.88V, or l.33V rms. In practice,
the somewhat nonideal rectifier results
in the sine wave output being regulated
to about 1.4Vrms, or 3.BV p-p.
The bandwidth of the circuit exceeds
40MHz. At 10.7MHz, the AGC threshold is 100p.V (-B7dBm) and its maximum gain is 83dB, 20Iog(1.4V/100p.V).
The circuit holds its output at 1.4V rms
for inputs as low as -67dBm to +15dBm
(82dB), where the input signal exceeds
the AD603's maximum input rating.
For a +10dBm input at 10.7MHz, the
second harmonic is 34dB down from the
fundamental, and the third harmonic is
35dB down.

RFIIF SUBSYSTEMS

LOGARITHMIC AMPLIFIERS
The term "Logarithmic Amplifier"
(generally abbreviated to "log amp") is
something ofa misnomer, and "Logarithmic Converter" would be a better
description. The conversion of a signal
to its equivalent logarithmic value
involves a. nonlinear operation, the
consequences of which can be confusing
if not fully understood. It is important
to realize that many of the familiar
concepts of linear circuits are irrelevant
to log amps. For example, the incremental gain of an ideal log amp approaches infinity as the input
approaches zero, and a change of offset
at the output ofa log amp is equivalent
to a change of amplitude at its input not a change of input offset.

that both the input and the output of a
log amp are voltages, although there is
no particular reason why logarithmic
current, transimpedance, or
transconductance amplifiers should not
also be designed.
If we consider the equation y = log(x)
we fmd that every time x is multiplied
by a cons tan t A, y increases by another
constant AI. Thus if 10g(K) = K1, then
log(AK) = K1 + A1, 10g(A2K) = K1 +
2A1, and 10g(KlA) = K1-A1. This gives
a graph as shown in Figure 3.16, where
y is zero when x is unity, y approaches
minus infinity as x approaches zero,
and which has no values for x for which
y is negative.

For the purposes of simplicity in our
initial discussions, we shall assume

GRAPH OF Y

=LOG(X)

y

------------------~---r---------------

X

Figure 3.16
3-17

HIGH SPEED DESIGN TECHNIQUES

range ofa log amp. The constant,
Vy,has the dimensions of voltage,
because the output is a voltage. The
input, Vin, is divided by a voltage, Vx'
because the argument of a logarithm.
must be a simple dimensionless ratio.

On the whole, log amps do not behave
in this way. Apart from the difficulties
of arranging infinite negative output
voltages, such a device would not, in
fact, be very useful. A log amp must
satisfy a transfer function of the form

A graph of the transfer characteristic of
a log amp is shown in Figure 3.17. The
scale of the horizontal axis (the input)
is logarithmic, and the ideal transfer
characteristic is a straight line. When
Yin =Vx , the logarithm is zero (log 1 =
0). Vx is therefore known as the intercept voltage of the log amp because the
graph crosses the horizontal axis at this
value ofVin.

over some range of input values which
may vary from 100:1 (40dB) to over
1,000,000:1 (120dB).
With inPllts very close to zero, log amps
cease to behave logarithmically, and
most then have a linear VinNout law.
This behavior is often lost in device
noise. Noise often limits the dynamic

LOG AMP TRANSFER FUNCTION
/

/
~IDEAL

/

ACTUAL

2V y - - - - - - - - - - - - - - - - - - - - - - - SLOPE = Vy

Yy

_____________ _

+

I

o-r------~~~------~------~----------

I

/
/

I

VIN

=10Vx

/
/~IDEAL

Figure 3.17
3-18

I

I

ACTUAL

V

IN

I

= 100Vx

INPUT ON
LOG SCALE

RFIIF SUBSYSTEMS

of the absolute value of the input and
disregards its sign as shown in Figure
3.19. This type of log amp can be considered to be a full-wave detector with a
logarithmic characteristic, and is often
referred to as a detecting log amp. (3)
They can give an output which is proportional to the log of the absolute
value of the input and has the same
sign as the input as shown in Figure
3.20. This type of log amp can be considered to be a video amp with a logarithmic characteristic, and may be
known as a logarithmic video (log video)
amplifier or, sometimes, a true log amp
(although this type of log amp is rarely
used in video-display-related applications).

The slope of the line is proportional to
Vy. When setting scales, logarithms to
tlie base 10 are most often used because this simplifies the relationship to
decibel values: when Yin = 10Vx ,the
logarithm has the value of 1, so the
output voltage is Vy . When Vin =
100Vx , the output IS 2Vy ,and so forth.
Vy can therefore be viewed either as
tlie "slope voltage" or as the ''volts per
decade factor."
The logarithm function is indeterminate for negative values ofx. Log amps
can respond to negative inputs in three
different ways: (1) They can give a
fullscale negative output as shown in
Figure 3.18. (2) They can give an
output which is proportional to the log

BASIC LOG AMP
(SATURAT~S WITH NEGATIVE INPUT)
+

OUTPUT

+

------------------~----------------~ INPUT

Figure 3.18
3-19

HIGH SPEED DESIGN TECHNIQUES

DETECTING LOG AMP
(OUTPUT POLARITY INDEPENDENT
OF -INPUT POLARITY)
+

OUTPUT

+

-------+-------

INPUT

Figure 3.19

LOG VIDEO OR "TRUE LOG AMP"
(SYM~ETRICAL RESPONSE
TO POSITIVE OR NEGATIVE SIGNALS)
+

OUTPUT

+
-------+--------

Figure 3.20
3-20

INPUT

RFIIF SUBSYSTEMS

There are three basic architectures
which may be used to produce log
amps: the basic diode log amp, the
successive detection log amp, and the
"true log amp" which is based on cascaded semi-limiting amplifiers.
The voltage across a silicon diode is
proportional to the logarithm of the
current through it. If a diode is placed
in the feedback path of an inverting opamp, the output voltage will be proportional to the log of the input current as
shown in Figure 3.21. In practice, the
dynamic range of this configuration is
limited to 40-60dB because of non-ideal
diode characteristic, but if the diode is
replaced with a diode-connected transistor as shown in Figure 3.22, the
dynamic range can be extended to
120dB or more. This type of log amp
has three disadvantages: (1) both the
slope and intercept are temperature
dependent; (2) it will only handle unipolar signals; and (3) its bandwidth is
both limited and dependent on signal
amplitude.
Where several such log amps are used
on a single chip to produce an analog
computer which performs both log and
antilog operations, the temperature
variation in the log operations is unim-

portant, since it is compensated by a
similar variation in the antilogging.
This makes possible the AD538, a
monolithic analog computer which can
multiply, divide, and raise to powers.
Where actual logging is required,
however, the AD538 and similar circuits require temperature compensation
(Reference 7). The major disadvantage
of this type of log amp for high frequency applications, though, is its
limited frequency response - which
cannot be overcome. However carefully
the amplifier is designed, there will
always be a residual feedback capacitance Cc (often known as Miller capacitance), from output to input which
limi ts the high frequency response.
What makes this Miller capacitance
particularly troublesome is that the
impedance of the emitter-base junction
is inversely proportional to the current
flowing in it - so that if the log amp has
a dynamic range of 1,000,000:1, then
its bandwidth will also vary by
1,000,000:1. In practice, the variation is
less because other considerations limit
the large signal bandwidth, but it is
very difficult to make a log amp of this
type with a small-signal bandwidth
greater than a few hundred kHz.

3-21

HIGH SPEED DESIGN TECHNIQUES

THE DIODE lOP-AMP LOG AMP

V=

~T In(,t.)
if 1»10

......... v

...-=~------

Eo

.

= kT
q

In

(.!.tti)
I()

== 0.06109 ~

if liN»

HIN 10

10

Figure 3.21

TRANSISTOR I OP-AMP LOG AMP

EO

EO =

Figure 3.22
3-22

kT

q

In

liN
lES

RFIIF SUBSYSTEMS

For high frequency applications, therefore, detecting and true log architectures are used. Although these differ in
detail, the general principle behind
their design is common to both: instead
of one amplifier having a logarithmic
characteristic, these designs use a
number of similar cascaded linear
stages having well-defined large signal
behavior.

fixed contribution to the output of the
summing amplifier, but the incremental gain to the summing amplifier will
drop to (N-l)A dB. As the input continues to increase, this stage in turn will
limit and make a fixed contribution to
the output, and the incremental gain
will drop to (N-2)A dB, and so forth until the fIrst stage limits; and the
output ceases to change with increasing
signal input.

Consider N cascaded limiting amplifiers, the output of each driving a summing circuit as well as the next stage
(Figure 3.23). If each amplifier has a
gain of A dB, the small signal gain of
the strip is NA dB. If the input signal is .
small enough for the last stage not to
limit, the output of the summing amplifier will be dominated by the output of
the last stage.

The response curve is thus a set of
straight lines as shown in Figure 3.24.
The total of these lines, though, is a
very good approximation to a logarithmic curve, and in practical cases, is an
even better one, because few limiting
amplifiers, especially high frequency
ones, limit quite as abruptly as this
model assumes.

As the input signal increases, the last
stage will limit. It will now make a

BASIC MULTI-STAGE LOG AMP ARCHITECTURE

Figure 3.23
3-23

HIGH SPEED DESIGN TECHNIQUES

BASIC MULTI-STAGE LOG AMP RESPONSE
(UNIPOLAR CASE)

____________ J
OUTPUT

G

G =0
=(N-4)A dB

= (N-3)A dB

) G

}- ~ ~ -(~-~A dB

__ J~ ~ ~N-l)AdB

INPUT

Figure 3.24

The choice of gain, A, will also affect
the log linearity. If the gain is too high,
the log approximation will be poor. Ifit
is too low, too many stages will be
required to achieve the desired dynamic
range. Generally, gains of 10 to 12dB
(3x to 4x) are chosen.

"smeared", and arrives spread over Nt
nanoseconds. A nanosecond equals a
foot at the speed of light, so such an
effect represents a spread in position of
Nt feet in the resolution ofa radar
system-which may be unacceptable in
some systems (for most log amp applications this is not a problem).

This is, of course, an ideal and very
general model- it demonstrates the
principle, but its practical implementation at very high frequencies is difficult.
Assume that there is a delay in each
limiting amplifier of t nanoseconds (this
delay may also change when the amplifier limits but let's consider first order
effects!). The signal which passes
through all N stages will undergo delay
of Nt nanoseconds, while the signal
which only passes one stage will be
delayed only t nanoseconds. This means
that a small signal is delayed by Nt
nanoseconds, while a large one is

A solution is to insert delays in the
signal paths to the summing amplifier,
but this can become complex. Another
solution is to alter the architecture
slightly so that instead of limiting gain
stages, we have stages with small
signal gain of A and large signal (incremental) gain of unity (OdB). We can
model such stages as two parallel
am plifiers, a limiting one with gain,
and a unity gain buffer, which together
feed a summing amplifier as shown in
Figure 3.25.

3-24

RFIIF SUBSYSTEMS

STRUCTURE AND PERFORMANCE OF
"TRUE" LOG AMP ELEMENT AND OF A
LOG AMP FORMED BY SEVERAL SUCH ELEMENTS
LIMITING
AMPLIFIER
GAIN = 3

INPUT
UNITY GAIN
AMPLIFIER
GAIN = 1
UNITY GAIN
(LARGE SIGNAL)

INPUT

Figure 3.25

SUCCESSIVE DETECTION LOGARITHMIC AMPLIFIER
WITH LOG AND LIMITER OUTPUTS
LIMITING AMPLIFIERS
LIMITER
OUTPUT

DETECTORS
LOG
OUTPUT
•

DETECTORS MAY BE FULL OR HALF WAVE

•

SHOULD BE CURRENT OUTPUT DEVICES (NOT
SIMPLE DIODES) SO THAT OUTPUTS MAY BE
SUMMED WITHOUT ADDITIONAL SUMMING
COMPONENTS BEING NECESSARY

Figure 3.26·
3-25

HIGH SPEED DESIGN TECHNIQUES

Figure 3.25 shows that such stages,
cascaded, form a log amp without the
necessity of summing from individual
stages. Both the multi-stage architectures described above are video log
amplifiers, or true log amplifiers, but
the most common type of high frequency log amplifier is the successive
detection log amp architecture shown in
Figure 3.26.
The successive detection log amp consists of cascaded limiting stages as
described above, but instead of summing their outputs directly, these
outputs are applied to detectors, and
the detector outputs are summed as
shown in Figure 3.26. If the detectors
have current outputs, the summing
process may involve no more than
connecting all the detector outputs
together.
Log amps using this architecture have
two outputs: the log output and a
limiting output. In many applications,
the limiting output is not used, but in
some (FM receivers with "S"-meters, for
example), both are necessary. The
limited output is especially useful in
extracting the phase information from
the input signal in polar demodulation
techniques.
The log output of a successive detection
log amplifier generally contains amplitude information, and the phase and
frequency information is lost. This is
not necessarily the case, however, if a
half-wave detector is used, and attention is paid to equalizing the delays
from the successive detectors - but the
design of such log amps is demanding.
The specifications of log amps will
include noise, dynamic range, frequency

3-26

response (some of the amplifiers used as
successive detection log amp stages
have low frequency as well as high
frequency cutoff), the slope of the transfer characteristic (which is expressed as
V/dB or mA/dB depending on whether
we are considering a voltage- or current-output device), the intercept point
(the input level at which the output
voltage or current is zero), and the log
linearity. (See Figures 3.27 and 3.28)

In the past, it has been necessary to
construct high performance, high
frequency successive detection log amps
(called log strips) using a number of
individual monolithic limiting amplifiers such as the Plessey SL-1521-series
(see Reference 16). Recent advances in
IC processes, however, have allowed
the complete log strip function to be
integrated into a single chip, thereby
eliminating the need for costly hybrid
log strips.
The AD641 log amp contains five
limi ting stages (1 OdB per stage) and
five full-wave detectors in a single IC
package, and its logarithmic performance extends from dc to 250MHz.
Furthermore, its amplifier and fullwave detector stages are balanced so
that, with proper layout, instability
from feedback via supply rails is unlikely. A block diagram of the AD641 is
shown in Figure 3.29. Unlike many
previous integrated circuit log amps,
the AD641 is laser trimmed to high
absolute accuracy of both slope and
intercept, and is fully temperature
compensated. Key features of the
AD641 are summarized in Figure 3.30.
The transfer function for the AD641 as
well as the log linearity is shown in
Figure 3.31.

RFIIF SUBSYSTEMS

KEY PARAMETERS OF LOG AMPS
•

NOISE: The Noise Referred to the Input (RTI) of the Log Amp.
It May Be Expressed as a Noise Figure or as a Noise Spectral
Density (Voltage, Current, or Both) or as a Noise Voltage, a Noise
Current, or Both

•

DYNAMIC RANGE: Range of Signal Over Which the Amplifier
Behaves in a Logarithmic Manner (Expressed in dB)

•

FREQUENCY RESPONSE: Range of Frequencies Over Which
the Log Amp Functions Correctly

•

SLOPE: Gradient of Transfer Characteristic in VldB or mAidB

•

INTERCEPT POINT: Value of Input Signal at Which Output is Zero

•

LOG LINEARITY: Deviation of Transfer Characteristic (Plotted on
logllin Axes) from a Straight Line (Expressed in dB)
Figure 3.27

LOG LINEARITY

Eo
(LINEAR)

E j (dBm)

Figure 3.28
3-27

HIGH SPEED DESIGN TECHNIQUES

BLOCK DIAGRAM OF THE AD641 MONOLITHIC LOG AMP

Figure 3.29

AD641 KEY FEATURES
•

44dB Dynamic Range

•

Bandwidth dc to 250M Hz

•

Laser-Trimmed Slope of 1mAldecade - Temperature Stable

•

Laser-Trimmed Intercept of 1mV - Temperature Stable

•

Less than 2dB Log Non-Linearity

•

Limiter Output: ±1.6dB Gain Flatness, ±2° Phase Variation
for -44dBm to OdBm inputs @ 10. 7MHz

•

Balanced Circuitry for Stability

•

Minimal External Component Requirement
Figure 3.30

3-28

RFIIF SUBSYSTEMS

DC LOGARITHMIC TRANSFER FUNCTION
AND ERROR CURVE FOR SINGLE AD641

<

7

~

~

§
o

!5a..
!5
o

2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2

o
-0.2
-0.4
0.1

,
""'~~

.............

/

/

/

/

/

/

,-

2

L~
"......,

L

/

~

1

o

/

r:c

"ex:

i

I

oa:

a:
w

./
1.0

10.0

100.0

1000.0

INPUT VOLTAGE - mV
(EITHER SIGN)

Figure 3.31

THE EFFECT OF WAVEFORM ON INTERCEPT POINT
INPUT

PEAK

INTERCEPT

ERROR (RELATIVE

WAVEFORM

ORRMS

FACTOR

TO A DC INPUT)

Square Wave

Either

1

O.OOdB

Sine Wave

Peak

2

-6.02dB

Sine Wave

RMS

1.414 ("2)

-3.01dB

Triwave

Peak

2.718 (e)

-8.68dB

Triwave

RMS

1.569 (e/"3)

-3.91dB

Gaussian Noise

RMS

1.887

-5.52dB

Figure 3.32
3-29

HIGH SPEED DESIGN TECHNIQUES

Because of its high accuracy, the actual
waveform driving the AD641 must be
considered when calculating responses.
When a waveform passes through a log
function generator, the mean value of
the resultant waveform changes. This
does not affect the slope of the response,
but the apparent intercept is modified
according to Figure 3.32.
The AD641 is calibrated and laser
trimmed to give its defined response to
a DC level or a symmetrical 2kHz
square wave. It is also specified to have
an intercept of 2mV for a sinewave
input (that is to say a 2kHz sinewave of
amplitude 2mV peak [not peak-to-peakl
gives the same mean output signal as a
DC or square wave signal of 1mV).

The waveform also affects the ripple or
nonlinearity of the log response. This
ripple is greatest for DC or square wave
inputs because every value of the input
voltage maps to a single location on the
transfer function, and thus traces out
the full nonlinearities of the log response. By contrast, a general timevarying signal has a continuum of
values within each cycle of its waveform. The averaged output is thereby
"smoothed" because the periodic deviations away from the ideal response, as
the waveform "sweeps over" the transfer function, tend to cancel. As is clear
in Figure 3.33, this smoothing effect is
greatest for a triwave.

THE EFFECT OF WAVEFORM ON AD641 LOG LINEARITY
2

L'"

./"

I'

-

-

........

-

.J~

SINE WAVE
INPUT
-r-

TRI1AVE
INPUT
I

-10
-SO

~

\
1'\

-70
-60
-50
-40
-30
-20
INPUT AMPLITUDE IN dB ABOVE 1V, AT 10kHz

Figure 3.33
3-30

\
\

SQUARE
WAVE INPUT

-10

RFIIF SUBSYSTEMS

Each of the five stages in the AD641
has a gain of 10dB and a full-wave
detected output. The transfer function
for the device was shown in Figure 3.21
along with the error curve. Note the
excellent log linearity over an input
range of 1 to 100mV (40dB). Although
well suited to RF applications, the
AD641 is dc-coupled throughout. This
allows it to be used in LF and VLF
systems, including audio measurements, sonar, and other instrumentation applications requiring operation to
low frequencies or even dc.
The limiter output of the AD641 has
better than 1.6dB gain flatness
(-44dBm to OdBm @ 10.7MHz) and less
than 2 0 phase variation, allowing it to
be used as a polar demodulator
The AD606 is a complete monolithic
50MHz bandwidth log amp using 9
stages of successive detection, and is

shown in Figure 3.34. Key specifications are summarized in Figure 3.35.
Seven of the amplifier/detector stages
handle inputs from -80dBm (3211V rms)
up to about-14dBm (45mV rms). The
noise floor is about -83dBm (1811V
rms). Another two parallel stages
receive the input attenuated by 22.3dB,
and respond to inputs up to +10dBm
(707mV rms). The gain of each stage is
11.15dB and is accurately stabilized
over temperature by a precise biasing
system.
The AD606 provides both logarithmic
and limited outputs. The logarithmic
output is from a three-pole post-demodulation lowpass filter and provides
an output voltage of +O.lV DC to +4V
DC. The logarithmic scaling is such
that the output is +O.5V for a sinusoidal
input of -75dBm, and +3.5V at an
input of +5dBm. Over this range, the
log linearity is typically within ±0.4dB.

AD606 50MHz, SOdB LOG AMP BLOCK DIAGRAM
INHI

COMM

PRUP

VPOS

FIL 1

FIL2

~30PF
30kn

1.Skn

30pF

30kn

LADJ

LMHI

360kn

360kn

~LOW-PASS
OFFSET-NULL
FILTER

HIGH-END
DETECTORS

AD606

7
INLO

ISUM

BFIN

VLOG

OPCM

Figure 3.34
3-31

HIGH SPEED DESIGN TECHNIQUES

AD606 LOG AMP KEY FEATURES
•

Dynamic Range: -75dSm to +5dSm (80dS)

•

Input Noise: < 1.5nV/"'Hz

•

Usable from 200Hz to Greater than 50MHz

•

Slope: 37.5mV/dB Voltage Output

•

On-Chip Lowpass Output Filter

•

Limiter Output: ±1.6dB Gain Flatness, ±2° Phase Variation
for -44dBm to OdBm inputs @ 10.7MHz

•

+5V Single-Supply, 65mW Power Consumption

Figure 3.35

The AD606 can operate above and
below these limits, with reduced linearity, to provide as much as 90dB of
conversion range. A second lowpass
filter automatically nulls the input
offset of the first stage down to the
submicrovolt level.
The AD606's limiter output provides a
hard-limited signal output as a differential current of ±1.2mA from open-

3-32

collector outputs. In a typical application, both of these outputs are loaded
by 2000 resistors to provide a voltage
gain of more than 90dB from the input.
This limiting amplifier has exceptionally low amplitude-to-phase conversion.
The limiter output has ± ldB output
flatness and ±3° phase stability over an
80dB range at 10.7MHz.

RFIIF SUBSYSTEMS

RECEIVER OVERVIEW

Walt Kester, Bob Clarke
We will now consider how the previously discussed building blocks can be
used in designing a receiver. First,
consider the analog superheterodyne
receiver invented in 1917 by Major
Edwin H. Armstrong (see Figure 3.36).
This architecture represented a significant improvement over single-stage
direct conversion (homodyne) receivers
which had previously been constructed

using tuned RF amplifiers, a single
detector, and an audio gain stage. A
significant advantage of the superheterodyne receiver is that it is much
easier and more economical to have the
gain and selectivity of a receiver at
fixed intermediate frequencies (IF) than
to have the gain and frequency-selective circuits "tune" over a band of
frequencies.

DUAL CONVERSION SUPERHET RECEIVER
(EXAMPLE FREQUENCIES)

900MHz
RF

IF STRIP

/

L02

1ST IF
240M Hz

FIXED

2ND IF
10.7MHz

\
DEMODULATOR

Figure 3.36

The receiver shown is a dual conversion
receiver with two intermediate frequency (IF) stages. The frequencies
chosen are typical in digital mobile
radio (DMR), but the principles apply to
other systems as well. The 900MHz RF
signal is mixed down to the first IF
frequency of 240MHz. Tuning is accom-

plished by the first local oscillator
(L01). The LOl frequency is chosen
such that the output of the first mixer
is at the first IF frequency, 240MHz.
Choosing a relatively high first IF
frequency eases the requirement on the
image frequency rejection filter as will
be discussed in the next section on
3-33

HIGH SPEED DESIGN TECHNIQUES

mixers. The first IF is then mixed. down
to the second IF frequency of lO.7MHz,
where it is demodulated (either using
analog or digital techniques).
Because of the wide dynamic range of
the RF signal, such a receiver requires
the use of automatic gain control,
voltage controlled amplifiers, and in
some cases (depending on the type of
demodulation), logarithmic amplifiers.
Receiver design is a complicated art,
and there are many tradeoffs that can
be made between IF frequencies, single-

conversion vs. double-conversion or
triple conversion, filter cost and complexity at each stage in the receiver,
demodulation schemes, etc. There are
many excellent references on the subject, and the purpose of this section is
only to acquaint the design engineer
with some of the building block les
which can make receiver design much
easier.
Before we look at further details of a
receiver, the subject of mixing requires
further discussion.

MULTIPLIERS, MODULATORS, AND MIXERS

Barrie Gilbert, Bob Clarke
An idealized mixer is shown in Figure
3.37. An RF (or IF) mixer (not to be
confused with video and audio mixers)
is an active or passive device that
converts a signal from one frequency to
another. It can either modulate or
demodulate a signal. It has three signal

connections, which are called ports in
the language of radio engineers. These
three ports are the radio frequency (RF)
input, the local oscillator (LO) input,
and the intermediate frequency (IF)
output.

THE MIXING PROCESS
IDEAL MIXER

IF OUTPUT

RF INPUT

fRF + flO
fRF -flO

lOINPUT
Figure 3.37
3-34

RFIIF SUBSYSTEMS

A mixer takes an RF input signal at a
frequency fRF' mixes it with a La
signal at a frequency fLO, and produces
an IF output signal that consists of the
sum and difference frequencies, fRF ±
fLO. The user provides a bandpass
filter that follows the mixer and selects
the sum (fRF + fLO) or difference (fRF
- fLO) frequency.
Some points to note about mixers and
their terminology:
• When the sum frequency is used as
the IF, the mixer called an upconverter;
when the difference is used, the mixer
is called a downconverter. The former is
often used in a transmit channel, the
latter in a receive channel.
• In a receiver, when the La frequency
is below the RF, it is called low-side
injection and the mixer a low-side
downconverter; when the La is above
the RF, it is called high-side injection,
and the mixer a high-side
downconverter.
• Each of the outputs is only half the
amplitude (one-quarter the power) of
the individual inputs; thus, there is a
loss of 6dB in this ideal linear mixer.
(In a practical multiplier, the conversion loss may be greater than 6dB,
depending on the scaling parameters of
the device. Here, we assume a mathematical multiplier, having no dimensional attributes.
A mixer can be implemented in several
ways, using active or passive techniques. A brief review of the various
classes of nonlinear elements that can
be used for frequency translation may
be helpful in setting the context. We
can identify three subclasses of circuits,
sharing certain similarities. All are in
the class of signal multipliers, producing at their output a signal which is, in

one way or another, the product of its
two inputs. They are multipliers, modulators, and mixers.
An analog multiplier generally has two
signal input ports, which can be called
X and Y, and generates an output W
that is the linear product of the voltages applied to these two ports. To
retain dimensional consistency, the
analog linear multiplication function
must invoke the use of a reference
voltage, which we can call U, thus
W=XYIU. In some cases, U is actually a
third input that can be used to implement analog division.
There are three functional categories of
multipliers: In single-quadrant multipliers, X and Y must be unipolar; in
two-quadrant multipliers, one of the
inputs may be bipolar; in four-quadrant
multipliers, both X and Y may be
bipolar. Analog Devices produces a wide
range of "linear" multipliers, including
the AD534, AD538, AD539, AD633,
AD734, AD834 and AD835, providing
the highest available accuracy (±O.02%
for the AD734) to the highest speed
(more than 500MHz for the AD834).
Modulators (sometimes called balancedmodulators, doubly-balanced modulators or even on occasions high level
mixers) can be viewed as sign-changers.
The two inputs, X and Y, generate an
output W, which is simply one of these
inputs (say, Y) multiplied by just the
sign of the other (say, X), that is W =
Ysign(X). Therefore, no reference voltage is required. A good modulator
exhibits very high linearity in its signal
path, with precisely equal gain for
positive and negative values ofY, and
precisely equal gain for positive and
negative values ofX. Ideally, the amplitude of the X input needed to fully
switch the output sign is very small,
that is, the X-input exhibits a compara3-35

HIGH SPEED DESIGN TECHNIQUES

tor-like behavior. In some cases, where
this input may be a logic signal, a
simpler X-channel can be used. A
highly-linear mixer such as the AD83I
is well-suited as a modulator.
A mixer is a modulator optimized for
frequency-translation. Its place in the
signal path is usually close to the
antenna, where both the wanted and
(often large) unwanted signals coexist
at its signal input, usually called ihe
RF port. Thus, the mixer must exhibit
excellent linearity in the sense that its
output (at the IF port) is expected to
increase by the same number of dB as a
test signal applied to the RF port, up to
as high as level as possible. This attribute is defined both by the IdB gaincompression and the 3rd-order intercept
(later explained). The conversion process is driven by an input applied to the
La port.
Noise and matching characteristics are
crucial to achieving acceptable levels of
performance in a receiver's mixer. It is
desirable to keep the La power to a
minimum to minimize cross-talk between the three ports, but this often
conflicts with other requirements. The
gain from the RF port to its IF port at
specified RF and La frequencies is
called the conversion gain and in classi-

cal diode-bridge mixers is less than
-4dB. Active mixers provide higher
conversion gain, and better port-port
isolation, but often at the expense of
noise and linearity. It is not usually
possibly (nor even desirable) to describe
mixer behavior using equations relating
the instantaneous values of inputs and
outputs; instead, we generally seek to
characterize mixers in terms of their
non-ideal cross-product terms at the
output. In this class, Analog Devices
has the AD83I, and mixers are found
embedded in the AD607, AD608 and
other signal-processing ICs.
Thus far, we have seen that multipliers
are linear in their response to the
instantaneous value of both of their
input voltages; modulators are linear in
their response to one input, the other
merely flipping the sign of this signal at .
regular intervals, with virtually zero
transition time, and beyond that having
ideally no other effect on the signal;
mixers are a sort of RF half-breed,
ideally being very linear on the RF
input, and "binary" in their switching
function in response to the La input,
but in reality being nonideal in both
respects; they are optimized for very
low noise and minimal intermodulation
distortion.

Mixing Using an Ideal Analog Multiplier
Figure 3.38 shows a greatly simplified
RF mixer by assuming the use of an
analog multiplier.
Ideally, the multiplier has no noise, no
limit to the maximum signal amplitude,
and no intermodulation between the
various RF signals (that is, no spurious
nonlinearities). Figure 3.39 shows the
result of mixing (= multiplying) an RF
input of sin~Ft with (= by) a La input
3-36

ofsinooLot, where ~F = 21txIIMHz
and ooLO = 21tx 10MHz.
Clearly, to better understand mixer
behavior, we will need to consider not
only the time-domain waveforms, as
shown here, but also the spectrum of
the IF output. Figure 3.40 shows the
output spectrum corresponding to the
above IF waveform.

RFIIF SUBSYSTEMS

"MIXING" USING AN ANALOG MULTIPLIER

RF INPUT

)..------l

IF OUTPUT

Vx

Vx -Vy

LOINPUT l J - - - - - - - - I
Vy

ANALOG MULTIPLIER, e.g., AD834

Figure 3.38

INPUTS AND OUTPUT FOR MULTIPLYING MIXER
FOR fRF = 11 MHz, flo = 10MHz
11

1\

n

1\

1\

n fI

An

RF
v V
I

~ fI i/\ A

V \I

v

u

~ ~ ~

n A IT

Vv

v

A 1\ A II 1\

Horizontal:
200ns/div.

LO
V v II

U v \/

v

v V v v

V

V

IF

Figure 3.39
3-37

HIGH SPEED DESIGN TECHNIQUES

OUTPUT SPECTRUM FOR MULTIPLYING MIXER
FOR fRF 11MHz, flO 10MHz

=

=

=10MHz
fRF =11MHz
flO

0.8

LINEAR
AMPLITUDE

lO AND RF FUllY SUPPRESSED

0.6

0.5

0.5
0.4

SUM AT
21MHz

DIFFERENCE
AT 1MHz

~

~

NO HARMONICS

/\

0.2

o

o

10

30

20

40

50

60

FREQUENCY (MHz)
Figure 3.40

There is no mystery so far. The mathematics are simple. Neglecting scaling
issues (real signals are voltages; thus a

practical multiplier needs an embedded
voltage reference, ignored here) the
relationship is:

The multiplier has thus transformed
the RF input into two, equal-amplitude
cosinusoidal components at its output
(the IF port), one at the sum frequency,
C1l&F + ~o' and the other at the difference frequency, OlaF - COLO'

In practice, an analog multiplier would
be a poor choice for a mixer because the
two linear inputs bring with them a
serious noise penalty.

3-38

RFIIF SUBSYSTEMS

Image Response
A receiver using even this mathematically perfect mixer suffers a basic problem, that of image response. Consider
the use of a low-side downconverter. The
wanted output is found at the frequency
OlrF = ~F - coLO· So we might suppose

that the only component of the RF
spectrum that finds its way through the
mixer "sieve" to the narrow IF passband is the wanted component at ClJw.
But we could have just as easily written
(1) as
Eq.la

because the cosine function is symmetric about t = o. So there is another
spectral component at the RF input
that falls in the IF passband, namely
the one for which COIF = COLO - OlaF' in
this case, the image frequency.

Consider the above example, where fLO
= 1MHz; the wanted
response is at the IF frequency, flF =
1MHz for fRF = 11MHz. However, the
mixer produces the same IF in response
to the image frequency, flMAGE = 9MHz
(see Figure 3.41).
= 10MHz and flF

IMAGE RESPONSE

flF

SIGNAL AT THE
IMAGE FREQUENCY
ALSO PRODUCES A
RESPONSE AT THE
IF FREQUENCY

flMAGE

-------- ------

t
I

I
I

t+- flF ~

flF

~--~-----------5~----~--~----~--~

o

1

9

10

11

FREQUENCY (MHz)

Figure 3.41
3-39

HIGH SPEED DESIGN TECHNIQUES

The most practical solution to this
dilemma is to carefully choose the IF
frequency to minimize the likelihood of
image sensitivity and also include an
image-reject filter at the RF input, just
ahead of the mixer. Another approach
is to use a special type of mixer circuit
that does not respond to the image
frequency. This approach requires

circuitry which is considerably more
complex, and for this reason has generally been unpopular, but it is becoming
more practical in a modern Ie implementation. It has the further disadvantage of higher power consumption, since
two mixer cells operating in quadrature
are required.

The Ideal Mixer
Ideally, to meet the low-noise, highlinearity objectives of a mixer we need
some circuit that implements a polarity-switching function in response to
the LO input. Thus, the mixer can be
reduced to Figure 3.42, which shows
the RF signal being split into in-phase

(0°) and anti-phase (180°) components;
a changeover switch, driven by the local
oscillator (LO) signal, alterna tely
selects the in-phase and antiphase
signals. Thus reduced to essentials, the
ideal mixer can be modeled as a signswitcher.

AN IDEAL SWITCHING MIXER

RF INPUT

I

~OUTPUT

Figure 3.42

3-40

RFIIF SUBSYSTEMS

just a single input at 11MHz with an
LO of 10MHz.

In a perfect embodiment, this mixer
would have no noise (the switch would
have zero resistance), no limit to the
maximum signal amplitude, and would
develop no intermodulation between
the various RF signals. Although
simple in concept, the waveform at the
intermediate frequency (IF) output can
be very complex for even a small number of signals in the input spectrum.
Figure 3.43 shows the result of mixing

The wanted IF at the difference frequency of 1MHz is still visible in this
waveform, and the 21MHz sum is also
apparent. But the spectrum of this
waveform is clearly more complex than
that obtained using the analog multiplier. How are we to analyze this?

INPUTS AND OUTPUT FOR IDEAL SWITCHING MIXER
FOR fRF = 11 MHz, flO = 10MHz
nn

n

n

n

n nnn

~

RF
~

v

v

v

V

v

V

~ U

V

v

I'"'

lO

Horizontal:
200ns/div.
.'-

n
IF

'-

'-

nil

~
UVV

n

~

VV
Figure 3.43

We still have a product, but now it is that of a sinusoid (the RF input) at ~F and a
variable that can only have the values +1 or -1, that is, a unit square wave at ~o.
The latter can be expressed as a Fourier series
8 LO =

4/1C { sin~ot

- 1/3 sin3~ot + 1/5 sin5roLot - .... }

Eq. 2

Thus, the output of the switching mixer is its RF input, which we can simplify as
sin~Ft, multiplied by the above expansion for the square wave, producing

3-41

HIGH SPEED DESIGN TECHNIQUES

= 'Ix {

SIF

SinO>&Ft sinOlr.ot - lIs SinO>&Ft sin30lr.ot
+ 1/5 sin50>&Ft sin500Lo t - .... }

Eq. 3

Now expanding each of the products, we obtain

= 2/x { sin( O>&F + coLO)t + sin( O>&F - Olr.o)t

SIF

- lIs sin(O>&F + 3coLO)t - lIs sin(O>&F - 30lr.o)t
+ 1/5 sin(O>&F + 5coLO)t + 1/5 sin(O>&F - 5 coto)t - ... }

Eq.4

or simply
SIF = 2/x {sin(O>&F + Olr.o)t + sin(O>&F - coto)t + harmonics}
The most important of these harmonic
components are sketched in Figure 3.44
for the particular case used to generate
the waveform shown in Figure 3.43,
that is, fRF = llMHz and fLO = 10MHz.
Because of the 2/x term, a mixer has a
minimum 3.92 dB insertion loss (and
noise figure) in the absence of any gain.

Eq.5

response to coLO - OlaF as the linear
multiplying mixer. The image response
is somewhat subtle, as it does not
immediately show up in the output
spectrum: it is a latent response, awaiting the occurrence of the "wrong" frequency in the input spectrum.

Note that the ideal (switching) mixer
has exactly the same problem of image

OUTPUT SPECTRUM FOR SWITCHING MIXER
FOR fRF 11 MHz AND flO 10MHz

=

=

0.8
LINEAR
AMPLITUDE

0.6

0.637 = -3.9dB
0.212 -13.5dB
0.127 -17.9dB
0.090 -20.9dB

=
=
=

0.637

0.637
WANTED IF
AT 1MHz

0.4

SUM AT
21MHz

~
0.212

0.2

0.212
0.127

o

~----+-----~----~----~----~----~--~
10
20
30
50
60
40

o

FREQUENCY (MHz)

Figure 3.44
3-42

RFIIF SUBSYSTEMS

Diode-Ring Mixer
For many years, the most common
mixer topology for high-performance
applications has been the diode-ring
mixer, one form of which is shown in
Figure 3.45. The diodes, which may be
silicon junction, silicon Schottky-barrier
or gallium-arsenide types, provide the
essential switching action. We do not
need to analyze this circuit in great
detail, but note in passing that the LO
drive needs to be quite high - often a
substantial fraction of one watt - in
order to ensure that the diode conduction is strong enough to achieve low
noise and to allow large signals to be
converted without excessive spurious
nonlinearity.

three ports are poorly controlled, making matching difficult. Furthermore,
there is considerable coupling between
the three ports; this, and the high
power needed at the LO port, make it
very likely that there will be some
component of the (highly-distorted) LO
signal coupled back toward the antenna. Finally, it will be apparent that
a passive mixer such as this· cannot
provide conversion gain; in the idealized scenario, there will be a conversion
loss of 2/1C [as Eq. 4 shows], or 3.92dB.
A practical mixer will have higher
losses, due to the resistances of the
diodes and the losses in the transformers.

Because of the highly nonlinear nature
of the diodes, the impedances at the

DIODE-RING MIXER

Figure 3.45
3-43

HIGH SPEED DESIGN TECHNIQUES

Users of this type of mixer are accustomed to judging the signal handling
capabilities by a "Level" rating. Thus, a
Level-17 mixer needs +17dBm (50mW)
of LO drive and can handle an RF input
as high as +10dBm (±lV). A typical
mixer in this class would be the MiniCircuits LRMS-1H, covering 2-500MHz,
having a nominal insertion loss of
6.25dB (8.5dB max), a worst-case LO-

RF isolation of 20dB and a worst-case
LO-IF isolation of22dB (these figures
for an LO frequency of 250-500MHz).
The price of this component is approximately $10.00 in small quantities. Even
the most expensive diode-ring mixers
have similar drive power requirements,
high losses and high coupling from the
LO port.

FETMixers
A modern alternative to the diode-ring
mixer is one in which the diodes are

replaced by FETs. The idea here is to
reduce the distortion caused by the
inherent nonlinearities of junction
diodes, whose incremental resistance
varies with the instantaneous signal
current. To reduce this effect, the
diodes are often driven to very high
current levels. Indeed, some users of
diode-ring mixers push them to extremes, operating at current levels close
to those which will cause the diodes to
fail by over-dissipation. Thus, in commenting about a certain minor variation to the diode-ring-mixer, we read:
"This helps the mixer to accept higher
LO power without burning out the
diodes!"
(From Wes Hayward, Solid State
Design for the Radio Amateur, ARRL,
1986, Chapter 6, p.120)
To avoid "burning out the diodes", some
mixers use two or four J -FETs in an
analogous way to that shown in Figure
3.45. The idea is that the channel
resistance of a large FET driven into its
triode region of conduction can be as
low as the dynamic resistance of a
diode, thus achieving similar conversion
gain and noise levels. But this lo,\v
resistance arises without any current
3-44

flow in the channel and it is also more
linear than that of the diodes when
signal current does flow, thus resulting
in lower intermodulation, and hence a
larger overall dynamic range. MOSFETs can also be used in a similar way.
This style ofFET-based mixers is very
attractive for many high-performance
applications. However, since the active
devices are still used only as switches,
they do not provide power gain, and
have typical insertion losses of 6 to 8dB.
Furthermore, the balance of these
mixers is still critically dependent on
such things as transistor matching and
transformer winding accuracy, large
LO drives (volts) are needed, and the
overall matching requirements continue
to be difficult to achieve over the full
frequency range. Finally, of course,
they are not directly amenable to
monolithic integration.
Another popular circuit, widely used in
many inexpensive receivers, is the dualgate MOS-FET mixer. In this type of
mixer, the RF signa:l is applied to one
gate of the FET and the LO signal to
the second gate. The multiplication
process is not very well-defined, but in
general terms relies on the fact that
both the first and second gates influence the current in the chaIlnel. The
structure can be modeled as two FETs,

RFIIF SUBSYSTEMS

where the drain of the lower FET
(having the RF input applied to it) is
intimately connected to the source of
the upper FET (having the LO input on
its gate). The lower FET operates in its
triode region, and thus exhibits a gm
that is a function of its drain voltage,

controlled by the LO. Though not
readily modeled to great accuracy, this
mixer, like many others, can be pragmatically optimized to achieve useful
performance, though not without the
support of many associated passive
components for biasing and matching.

Classic Active Mixer
The diode-ring mixer not only has
certain performance limitations, but it
is also not amenable to fabrication
using integrated circuit technologies, at
least in the form shown in Figure 3.45.
In the mid 'sixties it was realized that
the four diodes could be replaced by
four transistors to perform essentially
the same switching function. This
formed the basis of the now-classical
bipolar circuit shown in Figure 3.46,

which is a minimal configuration for
the fully-balanced version. Millions of
such mixers have been made, including
variants in CMOS and GaAs. We will
limit our discussion to the BJT form, an
exam pIe of which is the Motorola
MC1496, which, although quite rudimentary in structure, has been a mainstay in semi-discrete receiver designs
for about 25 years.

CLASSIC ACTIVE MIXER
(

IF OUTPUT

RF
INPUT

Figure 3.46
3-45

HIGH SPEED DESIGN TECHNIQUES

The active mixer is attractive for the
following reasons:

• It provides excellent isolation between
the signal ports.

• It can be monolithically integrated
with other signal processing circuitry.

• Is far less sensitive to load-matching,
requiring neither diplexer nor broadband termination.

• It can provide conversion gain,
whereas a diode-ring mixer always has
an insertion loss. (Note: Active mixers
may have gain. The analog Devices'
AD831 active mixer, for example,
amplifies the result in Eq. 5 by 7tl2 to
provide unity gain from RF to IF.)
• It requires much less power to drive
the LO port.

Using appropriate design techniques it
can provide trade-offs between thirdorder intercept (301 or IP3) and the
ldB gain-compression point (P1dB), on
the one hand, and total power consumption (PD) on the other. (That is, including the LO power, which in a passive
mixer is "hidden" in the drive circuitry.)

Basic Operation of the Active Mixer
Unlike the diode-ring mixer, which
performs the polarity-reversing switching function in the voltage domain, the
active mixer performs the switching
function in the current domain. Thus
the active mixer core (transistors Q3
through Q6 in Figure 3.46) must be
driven by current-mode signals. The
voltage-to-current converter formed by
Ql and Q2 receives the voltage-mode
RF signal at their base terminals and
transforms it into a differential pair of
currents at the their collectors.
A second point of difference between
the active mixer and diode ring mixer,
therefore, is that the active mixer
responds only to magnitude of the input
voltage, not to the input power; that is,
the active mixer is not matched to the
source. (The concept of matching is that
both the current and the voltage at
some port are used by the circuitry
which forms that port). By altering the
bias current, I RR , the transconductance
of the input pair Ql-Q2 can be set over
3-46

a wide range. Using this capability, an
active mixer can provide variable gain.
A third point of difference is that the
output (at the collectors ofQ3-Q6) is in
the form of a current, and can be converted back to a voltage at some other
impedance level to that used at the
input, hence, can provide further gain.
By combining both output currents
(typically, using a transformer) this
voltage gain can be doubled. Finally, it
will be apparent that the isolation
between the various ports, in particular, from the LO port to the RF port, is
inherently much lower than can be
achieved in the diode ring mixer, due to
the reversed-biased junctions that exist
between the ports.
Briefly stated, though, the operation is
as follows. In the absence of any voltage
difference between the bases of Ql and
Q2, the collector currents of these two
transistors are essentially equal. Thus,
a voltage applied to the LO input

RFIIF SUBSYSTEMS

results in no change of output CUlTent.
Should a small DC offset voltage be
present at the RF input (due typically
to mismatch in the emitter areas of Ql
and Q2), this will only result in a small
feedthrough of the LO signal to the IF
output, which will be blocked by the
first IF futer.
Conversely, if an RF signal is applied to
the RF port, but no voltage difference is
applied to the LO input, the output
CUlTents will again be balanced. A
small offset voltage (due now to emitter
mismatches in Q3-Q6) may cause some
RF signal feedthrough to the IF output;
as before, this will be rejected by the IF

filters. It is only when a signal is applied to both the RF and LO ports that
a signal appears at the output; hence,
the term doubly-balanced mixer.
Active mixers can realize their gain in
one other way: the matching networks
used to transform a 50n source to the
(usually) high input impedance of the
mixer provides an impedance transformation and thus voltage gain due to the
impedance step up. Thus, an active
mixer that has loss when the input is
terminated in a broadband 50n termination can have "gain" when an input
matching network is used.

The ADSSt, 500MHz, Low Distortion Active Mixer
The AD831 is a low distortion, wide
dynamic range, monolithic mixer for
use in such applications as RF to IF
down conversion in HF and VHF receivers, the second mixer in digital mobile
radio base stations, direct-to-baseband
conversion, quadrature modulation and
demodulation, and doppler-frequency
shift detection in ultrasound imaging
applications. The mixer includes a local
oscillator driver and a low-noise output
amplifier. The AD831 provides a

+24dBm third-order intercept point for
-10dBm local oscillator power, thus
improving system performance and
reducing system cost, compared to
passive mixers, by eliminating the need
for a high power local oscillator driver
and its associated shielding and isolation problems. A simplified block diagram of the AD831 is shown in Figure
3.47, and key specifications in Figure
3.48.

3-47

HIGH SPEED DESIGN TECHNIQUES

AD831 500MHz LOW DISTORTION ACTIVE MIXER
+5V

IF

OUTPUT

-

LOINPUT
-10 dBm

Figure 3.47

AD831 ACTIVE MIXER KEY SPECIFICATIONS
•

Doubly-Balanced Mixer, 10dB Noise Figure

•

Low Distortion (IF

=10.7MHz, RF to 200MHz):

•

+24dBm Third Order Intercept

•

+10dBm 1dB Compression Point

•

Low LO Drive Required: -10dBm

•

Bandwidth:
•

500MHz RF and LO Input Bandwidths

•

250MHz Differential Current IF Output

•

DC to > 200MHz Single-Ended Voltage IF Output
Figure 3.48

3-48

RFIIF SUBSYSTEMS

Noise Figure
Noise Figure (NF) is a figure of merit
used to determine how a device degrades the signal-to-noise ratio of its
input. Note: in RF systems, the impedance is 50n unless otherwise stated.
Mathematically, noise figure is dermed
as:
SI/NI
NF = 201og10 --==----=-SO/NO'
where SIINI is the input signal-to-noise
ratio, and SofNo is the output signalto-noise ratio.

The NF of the ADB31 is 10dB with a
matched input, which is adequate for
applications in which there is gain in
front of the mixer.
Noise Figure is used in a "cascaded
noise figure calculation", which gives
the overall noise figure of a receiver.
Basically, the noise figure of each stage
is converted into a noise factor (F =
antilog NF/I0) and plugged into a
spreadsheet containing the Friis Equation:

Typical noise figures for passive mixers
with post amplifiers are 12 to 15dB.

FRECEIVER = F1 +

Fo2 -1

G1

where FN and GN are the noise factor
and gain, respectively, of the Nth stage
in the receiver.
For a passive diode-ring mixer, the
noise figure is the same as the insertion
loss. For an active mixer, however,
noise is added to the signal by the
active devices in the signal path. The
difference between the noise figure of a
matched active mixer and an unmatched active mixer can be several dB
due to the "voltage gain" of the imped-

+

FS -1
N
~7" -1
+ ~ ,L"fi.
G1 G2 K-4 K-1
- II GJ
J=l

ance-matching network, which acts as a
"noiseless" preamplifier (Figure 3.49).
In the case of the ADB31, the noise
figure for the matched circuit is 10 dB
(at 70MHz) and the unmatched circuit
with its input terminated with a 50n
resistor is 16dB.
The noise figure is 11.7dB at 220 MHz
using the external matching network
shown in Figure 3.49. The values
shown are for 220 MHz and provide 10
dB of voltage gain.

3-49

HIGH SPEED DESIGN TECHNIQUES

AD831 ACTIVE MIXER WITH 220M Hz
EXTERNAL MATCHING NETWORK

AD831
C1

6

RF
INPUT

RFP

C2

L2

7

RFN

L 1: 100nH, COILCRAFT 1008CS·1 01
L2: 56nH, COILCRAFT 1008CS-S60
C1, C2: 2-10pF CERAMIC VARIABLE

Figure 3.49

Intermodulation Distortion
Even before the "mixing" process in the
core, the entire signal spectrum coexists within the RF input stage. This
part of the mixer is inevitably nonlinear, to a greater or lesser extent, and,
with or without the LO input operative,
generates a very large number of
intermodulation products.
Thus, the key objectives in the design of
a high-performance active mixer are to
achieve a very linear RF input section,
followed by a near-ideal polarity. .
switching stage, followed by a very
linear IF output amplifier (if used) prior
to the first filter.
IdB Compression Point and ThirdOrder Intercept Point
For a single-sinusoid input to a system,
a point will be reached as the input
ampiitude is increased at which the
3-50

apparent gain becomes 1dB lower than
that observed at lower input amplitudes. This is called the 1dB gain
compression level, which we'll abbreviate P1dB, and is usually quoted in
dBm, or decibels above 1mW, that is, it
is expressed as a power measurement.
When using an active mixer with an
input matching network, the gain of the
input matcll.ing network must be taken
into accoun~ when defining the system
in terms of an active mixer's 1dB compression point, since the impedance
transformation of the network increases
the input voltage to mixer.
Another metric used in characterizing
mixers is the third-order intercept,
known as P SOI or IP3. If two tones of
frequency f1 and f2 (representing two
adjacent channels in a communications
system, for example) are applied to a
non-linear system, there will be a large

RFIIF SUBSYSTEMS

number of intermodulation products
generated. The third-order distortion
products which fall at 2f2-f1 and 2f1-f2
are particularly troublesome, because
they are close to the original frequencies (see Figure 3.50). If the two tones
represent true signals, then the thirdorder IMD products can interfere with
signals in the adjacent channels.
Rather than measuring the third-order
distortion products for a variety of
signal amplitudes, the concept of third-

order intercept can be used to extract
the IMD information and is often used
as a figure of merit for mixers and
amplifiers in RF applications.
A plot (Figure 3.51) of the power levels
at the output of the system for the
fundamental of the output frequency
and for its third harmonic, plotted
versus the input power, will-generally
yield a pair of straight lines which
eventually intersect (at the 3rd order
intercept point, IP3).

THIRD-ORDER INTERMODULATION DISTORTION

FREQUENCY

Figure 3.50
3-51

HIGH SPEED DESIGN TECHNIQUES

THIRD-ORDER INTERCEPT USING DATA FOR AD831
+24

3RD ORDER INTERCEPT POINT
; /
-------------------~I~
//1

+10

~ / / -J--I_ _

1 dB COIYIPRESSION POINT

---------------~-

1
1

1 dB 1

·10

IF = 10.7 MHz
RF 100 MHz

=

LINEAR ~
OUTPUT

OUTPUT
POWER
(dBm)

~

3RD ORDER IMD
AT 2f1 • f2 AND 2f2 • f1

·78

----------

INPUT POWER (dBm)

Figure 3.51

The problem with this metric is that it
has meaning only for certain simple
cases. In particular, the 3rd harmonic is
assumed to increase at three times the
rate of the fundamental. The appeal of
P aoI lies in the fact that it is easily
measured, or at least, it is easy to
obtain measurements. (The measurements are not hard to make, but it will
be found that the apparent P aoI is
signal-dependent). Apply a low level
signal, at some known level Po (iIi
dBm, see Figure 3.51), measure the
output power at the fundamental, P l
(in relative terms, dBc) and at the third
harmonic, P a (also in dBc) and from
simple geometry calculate

The non-linearity in some classical
circuits, such as the diode-ring mixer,
approximates a cubic function, and the
3-52

above relationship holds, but in practice, the P aoI can be quite misleading,
for several reasons. First, other circuits
may not, in general, exhibit this type of
non-linearity. This type of behavior
could easily lead to apparent thirdorder intercept values which were
impressively high (theoretically infinite,
if measured using signals of less than
the critical amplitude).
A spur chart is a compilation of the nfl
± mf2 products that result from the
mixing process. The spur chart is useful
because it allows an engineer developing a frequency plan for a radio to
identify possible problems due to spurious signals created in the mixer. However, the spur chart is also tedious to
create; for n = m = 7, a chart requires
112 measurements.

RFIIF

The compilation of results is the spur
chart (also called a "mixer table").

SUBSYSTEMS

Details of making the spur chart measurements and results are given in the
AD831 data sheet (see Reference 17).

Mixer Summary
Mixers are a special kind of analog
multiplier optimized for use in frequency translation, having one linear
input (that associated with the RF
signal) and a second (that associated
with the LO input) which alternates the
phase of the first input by 0/180 0 • In
integrating complete receivers in monolithic form, certain basic circuit forms
have proven useful. So far, we have
considered a classic form, a six-transistor circuit exemplified by the AD831.
Compared to a diode-ring mixer, this
circuit has several advantages, including much better isolation between
ports, the ability to provide conversion
gain (which may also be variable), the
need for much lower LO drive levels,
and the elimination of special matching
networks.
Often cited as a disadvantage of the
active mixer is its poorer dynamic

range: we have just begun to examine
what defines this, beginning with a
consideration of the linearity of the RF
port, traditionally characterized by the
1dB gain-compression input power,
p IdB, and the third-order intercept,
P aOl . The second of these measures was
shown to be meaningful only if the
nonlinearity is essentially cubic in form,
which may not always be true. In
passing, we pointed out that while
inputs and outputs are invariably
characterized in terms of a power level
of so-many-dBm, active mixers respond
to instantaneous signal voltages at
their inputs, which are usually not
matched to their source, which can be
confusing at times.
Now that we have examined each of the
fundamental receiver building blocks,
we are ready to look at receiver subsystems.

3-53

HIGH SPEED DESIGN TECHNIQUES

RECEIVER SUBSYSTEMS

Bob Clarke, Walt Kester
In order to design a communications
receiver, a clear understanding of the
modulation technique is essential.
There are many types of modulation,
ranging from simple amplitude modulation (AM), phase modulation (PM), and
frequency modulation (FM) to multilevel quadrature-am plitude-modulation
(QAM) where both amplitude and
phase are modulated. Most modem
modulation schemes make use of both
signal amplitude and phase information. A complex signal can thus be
represented in two ways as shown in
the diagrams in Figure 3.52. The lefthand diagram represents the signal in
rectangular coordinates as an inphase
(I) and quadrature (Q) signal of the
form:

S(t) = I(t) + jQ(t).
The right hand diagram represents the
same signal expressed in polar coordinates:
S(t) =A(t)el 0 (t).
The conversions between the two
coordinate systems are:
S(t) =A(t)el 0 (t) = I(t) + jQ(t), where
A(t) =

~I(t)2 +Q(t)2 ,

Q(t)]
0(t) = arctan [ I(t)

RECTANGULAR AND POLAR REPRESENTATIONS OF
AMPLITUDE AND PHASE MODULATED SIGNAL
Q(t)

Q(t)

S(t) = A(t)J~(t)

I(t)

RECTANGULAR

POLAR
Figure 3.52

3-54

RFIIF SUBSYSTEMS

Note that the signals are identical, only
their representation is different.
In the case of the I1Q (rectangular)
representation, a linear IF strip is
required. Variable gain is required
because of the wide dynamic range, and
amplitude and phase information must
be preserved. This type of IF strip often
incorporates an I1Q demodulator whose
outputs drive baseband ADCs followed
by a DSP. Linear IF amplifiers are used
in these systems.
For the case of the polar representation,
the signal amplitude is derived from the
RSSI (log) output ofa logllimiting
amplifier and the phase information
from the limited output. This type of IF
strip operates at a high fIXed gain,
retains the phase inform a tion in the
limited output, and often incorporates a
phase demodulator.
In order to handle these two fundamental representations of modulation, ADI
has developed two IF subsystems, the
AD607 and the AD608. These are used
in such applications as PHS, PCN,
DECT, CT2, and GSM where the modula tion mode is some form of phase-shift
keying (PSK).

The standard architecture in GSM and
PHS uses a rectangular representation
of the signal, that is S(t) =I(t) + jQ(t)
and requires a linear IF amplifier stage
such as that in the AD607. In this
architecture, a baseband converter
consisting of two signal inputs; each
with individual low-pass filters, digitizes the I(t) and Q(t) outputs of the IF
IC's quadrature demodulator. Further
demodulation is performed digitally
using a DSP. An equalizer in the DSP
then determines the correct manual
gain control (MGC) voltage (or digital
signal) to change the IF gain to center
the signal in the dynamic range of the
baseband ADCs. The equalizer calculates the RSSI value as part of this
process (see Figure 3.53).
A detailed block diagram of the AD607
Mixer/AGC/RSSI 3V receiver IF subsystem is shown in Figure 3.54. The RF
input frequency can be as high as
500MHz, and the IF frequency from
400kHz to 12MHz. It consists ofa
mixer, linear IF amplifiers, I and Q
demodulators, a phase-locked quadrature oscillator, AGC detector, and a
biasing system with external powerdown. Total power on +3V is 25mW.

The choice of demodulation technique
depends on the receiver architecture.

3-55

HIGH SPEED DESIGN TECHNIQUES

RECEIVER BASED ON AD607 SUBSYSTEM
USING INPHASE/QUADRATURE MODULATION

90dB RANGE

BASEBAND
ADCsAND
DSP

240MHz

AD607

I

LPF

Q

I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ JI

MGC
Figure 3.53

AD607 FUNCTIONAL BLOCK DIAGRAM
LOIP

RFHI

lOUT
FDIN

RFLO
FLTR
QOUT

'----+----------+--.--+-{X:>--+--------_UGAINlRSSI
VPS1LJ~~~1

GREF

VPS2
PRUP

'C=======:::()...-'O"--________________--1
COM1

COM2

Figure 3.54
3-56

RFIIF SUBSYSTEMS

The AD607's low noise, high intercept
mixer is a doubly-balanced Gilbert cell
type. It has a nominal-15dBm inputreferred ldB compression point and aSdBm input-referred third-order
intercept. The mixer section also includes a local oscillator preamplifier,
which lowers the required external LO
drive to -l6dBm.
The variable-gain mixer and the linear
four-stage IF amplifier strip together
provide a voltage controlled gain range
of more than 90dB. The I and Q demodulators, each consisting of a multiplier followed by a 2-pole, 2MHz

low-pass filter, are driven by a phaselocked loop providing inphase and
quadrature clocks. An internal AGe
detector is included, and the temperature stable gain control system provides
an accurate RSSI capability.
The I and Q demodulators provide
inphase and quadrature baseband
outputs to interface with Analog Devices' AD70l3 (1854118136, TETRA,
MSAT) and AD70l5 (GSM) baseband
converters.
Key specifications for the AD607 are
summarized in Figure 3.55.

AD607 MIXER I AGC I RSSI 3V RECEIVER KEY FEATURES
•

Mixer:
•
-15dBm Input 1dB Compression Point
•
-SdBm Input Third Order Intercept Point
•
RF/LO Inputs to 500MHz
•
12dB Noise Figure, Matched Input
•
-16d Bm LO Drive

•

Linear IF Amplifier:
•
45MHz Bandwidth
•
Linear-in-dB Gain Control Over gOdS Gain Range
•
-15dBm Input 1dB Compression Point
•
+1SdBm Output Third Order Intercept Point

•

In-Phase and Quadrature Demodulators:
•
1.5MHz Output Bandwidth
•
Compatible with Baseband Converters (AD7013, AD7015)

•

25mW Total Power @ Single +3V Supply
Figure 3.55

For cases where the signal is represented in polar form, the AD60S is the
proper choice. The AD60S Mixer/LimiterlRSSI 3V Receiver IF Subsystem
consists of a mixer followed by a logarithmic amplifier; the logarithmic
amplifier has both limited output
(phase information) and an RSSI out-

put (amplitude information). This
architecture is useful in polar demodulation applications as shown in Figure
3.56.
A block diagram of the AD60S is shown
in Figure 3.57, and key specifications in
Figure 3.5S.
3-57

HIGH SPEED DESIGN TECHNIQUES

RECEIVER BASED ON AD608 SUBSYSTEM
USING POLAR DEMODULATION
L02

1Q.7MHz

t - - t - - - t RSSI

DETECTORS

DEMOD

80dS RANGE

DSP

LIMITING
AMPLIFIERS
240MHz

AND
>---+--..; PHASE

AD608
L..

Figure 3.56

AD608 FUNCTIONAL BLOCK DIAGRAM
\4--I

24dB MIXER GAIN

--.~t4---

3dB NOMINAL
INSERTION LOSS

--t"~I"'.------

100dB LIMITER GAIN
90dB RSSI
RSSIOUTPUT
20mV/dB
O.2VTO 1.6V

RFINPUT
-95 TO
-15dBm1

+2.7V TO 5.5V
LIMITER
OUTPUT
400mVp-p

AD608
4
+2.7V TO
5.5V

LO INPUT
-16dBm

CMOS LOGIC
INPUT

NOTES:

1 -15dBm

=±56mV MAX FOR LINEAR OPERATION

2 39.7611V RMS TO 397.6mV RMS FOR ±1dB RSSI

ACCURACY

Figure 3.57
3-58

RFIIF SUBSYSTEMS

AD608 MIXER I LIMITER I RSSI 3V RECEIVER KEY FEATURES
•

Mixer:
•
-15dBm Input 1dB Compression Point
•
-5dBm Input Third Order Intercept Point
•
RF/LO Inputs to 500MHz
•
12dB Noise Figure, Matched Input
•
-16dBm LO Drive

•

Logarithmic Amplifier I Limiter:
•
100dB Limiter Gain, 90dB RSSI
•
±1dB Log Linearity
•
±3° Phase Variation, -75dBm to +5dBm IF @ 10.7MHz

•

21 mW Total Power @ Single +3V Supply

Figure 3.58

The log amp both measures the level of
the signal (like the AD641 and AD606)
and limits the signal. The RSSI or
Received Signal Strength Indicator
output is proportional to the log of the
input signal. As a limiting amplifier,
the AD608 removes any amplitude
changes in the signal and keeps only
the phase or frequency changes. These
phase or frequency changes are proportional to the modulating signal and
contain the intelligence in the signal.
The AD608's limiting amplifier is a 5stage log amp with more than 80dB of
dynamic range.
In a typical mobile phone application,
the RF signal (typically 900MHz or
1800MHz) is mixed down to the first IF
(typically 240MHz), is filtered, and
enters the AD608, where it is mixed
down to a second IF at 10.7MHz, where
it is amplified, limited, and measured.
The limited output is demodulated by

an external frequency or phase demodulator. The RSSI output is digitized
by an ADC and used for active power
control in the phone system.
As a practical note, the cutoff frequency

of the log amp's internal low pass filter
depends on what range of frequencies
the log amp was designed for. In analog
cellular systems, where the modulation
mode is narrow-band FM, the IF is
typically 450kHz. The low pass filters
in the IF ICs designed for these standards have a fairly low cutofffrequency, and the filter's voltage output
response provides a "slow" RSSI. In
GSM (Global System for Mobile Communications) and PHS (Personal Handy
System) applications, the IF is typically
10.7MHz or higher, and the filter's
voltage output response provides a
"fast" RSSI. The cutoff frequency of the
low pass filter in the AD608 is 2MHz.
3-59

HIGB SPEED DESIGN TECHNIQUES

REFERENCES
1.

Barrie Gilbert, ISSCC Digest of Technical Papers 1968, pp. 114-115
February 16, 1968.

2.

Barrie Gilbert, Journal of Solid State Circuits, Vol. SC-3, December
1968, pp. 353-372.

3.

C.L. Ruthroff, Some Broadband Transformers, Proc. I.R.E., Vol. 4 7,
August, 1959, pp.1337-1342.

4.

James M. Bryant, Mixers for High Performance Radio, Wescon 1981:
Session 24 (Published by Electronic Conventions, Inc., Sepulveda Blvd.,
EI Segundo, CA)

5.

P.E. Chadwick, High Performance Ie Mixers, IERE Conference on Radio
Receivers and Associated Systems, Leeds, 1981, IERE Conference
Publication No. 50.

6.

P.E. Chadwick, Phase Noise, Intermodulation, and Dynamic Range,
RF Expo, Anaheim, CA, January, 1986.

7.

Daniel H. Sheingold, Editor, Nonlinear Circuits Handbook, Analog
Devices, Inc., 1974.

8.

Richard Smith Hughes, Logarithmic Amplifiers, Artech House, Inc.,
Dedham, MA., 1986.

9.

William L. Barber and Edmund R. Brown, A True Logarithmic Amplifier for
Radar IF Applications, IEEE Journal of Solid State Circuits, Vol. SC15, No.3, June, 1980, pp. 291-295.

10.

Broadband Amplifier Applications, Plessey Co. Publication P.S. 1938,
September, 1984.

11.

M. S. Gay, SL521 Application Note, Plessey Co., 1966.

12.

Amplifier Applications Guide, Analog Devices, Inc., 1992. Section 9.

13.

Charles Kitchen and Lew Counts, RMS-to-DC Conversion Application
Guide, Second Edition, Analog Devices, Inc., 1986.
.

14.

Barrie Gilbert, A Low Noise Wideband Variable-Gain Amplifier Using
an Interpolated Ladder Attenuator, IEEE ISSCC Technical Digest, 1991,
pp. 280, 281, 330.

3-60

RFIIF SUBSYSTEMS

15.

Barne Gilbert, A Monolithic Microsystem for Analog Synthesis of
Trigonometric Functions and their Inverses, IEEE Journal of Solid
State Circuits, Vol. SC-17, No.6, December, 1982, pp. 1179-1191.

16.

Linear Design Seminar, Analog Devices, 1995, Section 3.

17.

AD831 Data Sheet, Rev. B, Analog Devices.

3-61

HIGH SPEED DESIGN TECHNIQUES

SECTION 4
HIGH SPEED SAMPLING AND HIGH SPEED ADCs
•

Fundamentals of High Speed Sampling

•

Baseband Antialiasing Filters

•

Undersampling

•

Antialiasing Filters in Undersampling Applications

•

Distortion and Noise in an Ideal N-bit ADC

•

Distortion and Noise in Practical ADCs

•

High Speed ADC Architectures

HIGH SPEED DESIGN TECHNIQUES

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

SECTION 4
mGH SPEED SAMPLING AND
mGH SPEED ADCs, Walt Kester
INTRODUCTION
High speed ADCs are used in a wide
variety of real-time DSP signal-processing applications; replacing systems that
used analog techniques alone. The
major reason for using digital signal
processing are (1) the cost of DSP
processors has gone down, (2) their
speed and computational power has
increased, and (3) they are
reprogrammable, thereby allowing for
system performance upgrades without
hardware changes. DSP offers solutions
that cannot be achieved in the analog
domain, i.e. V.32 and V.34 modems.
However, in order for digital signal
processing techniques to be effective in
solving an analog signal processing
problem, appropriate cost effective high
speed ADCs must be available. The
ADCs must be tested and specified in
such a way that the design engineer
can relate the ADC performance to
specific system requirements, which
can be more demanding than if they
were used in purely analog signal
processing systems. In most high speed
signal processing applications, AC
performance and wide dynamic range
are much more important than traditional DC performance. This requires
that the ADC manufacturer not only
design the right ADCs but specify them
as completely as possible to cover a
wide variety of applications.
Another important aspect of integrating
ADCs into a high speed system is a
complete understanding of the sampling process and the distortion mecha-

nisms which ultimately limit system
performance. High speed sampling
ADCs first were used in instrumentation and signal processing applications,
where much emphasis was placed on
time-domain performance. While this is
still important, applications of ADCs in
communications also require comprehensive frequency-domain specifications.
Modern IC processes also allow the
integration of more analog functionality
into the ADC, such as on-board references, sample-and-hold amplifiers,
PGAs, etc. This makes them easier to
use in a system by minimizing the
amount of support circuitry required.
Another driving force in high speed
ADC development is the trend toward
lower power and lower supply voltages.
Most high speed sampling ADCs today
operate on either dual or single 5V
supplies, and there is increasing interest in single-supply converters which
will operate on 3V or less for battery
powered applications. Lower supply
voltages tend to increase a circuit's
sensitivity to power supply noise and
ground noise, especially mixed-signal
devices such as ADCs and DACs.
The trend toward lower cost and lower
power has led to the development of a
variety of high speed ADCs fabricated
on standard 0.6 micron CMOS processes. Making a precision ADC on a
digi tal process (no thin film resistors
are available) is a real challenge to the
4-1

II
~

HIGH SPEED DESIGN TECHNIQUES

IC circuit designer. ADCs which require
the maximum in performance still
require a high speed complementary
bipolar process (such as Analog Devices'
XFCB) with thin film resistors.
The purpose of this section is to equip
the engineer with the proper tools

necessary to understand and select
ADCs for high speed systems applications. Making intelligent tradeoffs in
the system design requires a thorough
understanding of the fundamental
capabilities and limitations of state-ofthe-art high speed sampling ADCs.

HIGH SPEED SAMPLING ADCs
•

Wide Acceptance in Signal Processing and Communications

•

Emphasis on Dynamic Performance

•

Trend to Low Power, Low Voltage, Single-Supply

•

More On-Chip Functionality: PGAs, SHA, Digital Filters, etc.

•

Process Technology:
•

Low Cost CMOS: Up to 12-bits @ 10MSPS

•

High Speed Complementary Bipolar: Up to 12-bits @ 70MSPS

•

Statistical Matching Techniques Rather than Thin Film
Laser Trimming

Figure 4.1

FUNDAMENTALS OF HIGH SPEED SAMPLING
The sampling process can be discussed
from either the frequency or time
domain or both. Frequency-domain
analysis is applicable to communications, so that's what we will consider.
First consider the case of a single
frequency sinewave of frequency fa
sampled at a freQuency fo bv an ideal
-

4-2

-

-

Ii;;J

...

impulse sampler (see top diagram in
Figure 4.2). Also assume that fs > 2fa
as shown. The frequency-domain output of the sampler shows aliases or
images of the original signal around
every multiple offs' i.e. at frequencies
equal to
I ± Kfs ± fa I , K = 1, 2, 3, 4, .....

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

ANALOG SIGNAL fa SAMPLED @ fs USING IDEAL SAMPLER
HAS IMAGES (ALIASES) AT I±Kfs ±fal, K = 1,2,3, ...
fa
4

-1

~
O.5fs

I

I

Q



9

I
I
I

I
I
I

I
I

f

I

I

«

I
I
I .~S

!
.1
1.5f
s

s

)

2fs

~ ZONE1+Z0NE2+Z0NE34-<>----ZONE44- - fa

I

?
I
I
I
I

J

4

O. 5fs

I

?

?

I
I
I

I
I

I

I

1.5fs

fs

I
9
I
I
I

I
I
I

2fs

~S

II

Figure 4.2

The Nyquist bandwidth is defined to be
the frequency spectrum from DC to fs/2.
The frequency spectrum is divided into
an infinite number of Nyquist zones,
each having a width equal to 0.5fs as
shown. In practice, the ideal sampler is
replaced by an ADC followed by an FFT
processor. The FFT processor only
provides an output from DC to fs/2, i.e.,
the signals or aliases which appear in
the first Nyquist zone.
Now consider the case of a signal which
is outside the first Nyquist zone (Figure
4.2, bottom diagram) Notice that even
though the signal is outside the first
Nyquist zone, its image (or alias), fs-fa,

falls inside. Returning to Figure 4.2, top
diagram, it is clear that if an unwanted
signal appears at any of the image
frequencies of fa' it will also occur at fa,
thereby producing a spurious frequency
component in the fIrst Nyquist zone.
This is similar to the analog mixing
process and implies that some filtering
ahead of the sampler (or ADC) is required to remove frequency components
which are outside the Nyquist bandwidth, but whose aliased components
fall inside it. The filter performance will
depend on how close the out-of-band
signal is to fs/2 and the amount of
attenuation required.

4-3

HIGH SPEED DESIGN TECHNIQUES

BASEBAND ANTIALIASING FILTERS
Baseband sampling implies that the
signal to be sampled lies in the fIrSt
Nyquist zone. It is important to note
that with no input filtering at the input
of the ideal sampler, any frequency
component (either signal or noise) that
falls outside the Nyquist bandwidth in
any Nyquist zone will be aliased back
into the first Nyquist zone. For this
reason, an antialiasing filter is used in
almost all sampling ADC applications to
remove these unwanted signals.
Properly specifying the antialiasing
filter is important. The first step is to

know the characteristics of the signal
being sampled. Assume that the highest frequency of interest is fa. The
anti aliasing filter passes signals from
DC to fa while attenuating signals
above fa.
Assume that the corner frequency of
the filter is chosen to be equal to fa.
The effect of the finite transition from
minimum to maximum attenuation on
system dynamic range is illustrated in
Figure 4.3.

EFFECTS OF ANTIALIASING FILTER
ON SYSTEM DYNAMIC RANGE
fa

f s • fa

;1--------

/1
/ I
/
I
/
/
I
/
I
I
I
I
I
I
I

DR

fa

fs
2

f s · fa

fs

f

STOPBAND ATTENUATION = DR
FILTER
SPECIFICATIONS

[

TRANSITION BAND: fa TO fs • fa
CORNER FREQUENCY: fa

Figure 4.3

Assume that the input signal has
fullscale components well above the
maximum frequency of interest, fa. The
diagram shows how fullscale frequency
components above fs - fa are aliased
back into the bandwidth DC to fa.
4-4

'rhese aliased components are indistinguishable from actual signals and
therefore limit the dynamic range to
the value on the diagram which is
shown as DR.

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

Some texts recommend specifying the
anti aliasing filter with respect to the
Nyquist frequency, fs/2, but this assumes that the signal bandwidth of
interest extends from DC to fs/2 which
is rarely the case. In the example
shown in Figure 4.3, the aliased components between fa and fs/2 are not of
interest and do not limit the dynamic
range.
The antialiasing filter transition band
is therefore determined by the comer
frequency fa' the stopband frequency fs
- fa' and the stopband attenuation, DR.
The required system dynamic range is
chosen based on our requirement for
signal fidelity.
Filters have to become more complex as
the transition band becomes sharper,
all other things being equal. For instance, a Butterworth filter gives 6dB
attenuation per octave for each filter
pole. Achieving 60dB attenuation in a
transition region between 1MHz and
2MHz (1 octave) requires a minimum of
10 poles, not a trivial filter, and definitely a design challenge.

Therefore, other filter types are generally more suited to high speed applications where the requirement is for a
sharp transition band and in-band
flatness coupled with linear phase
response. Elliptic filters meet these
criteria and are a popular choice.
There are a number of companies which
specialize in supplying custom analog
filters. TTE is an example of such a
company (Reference 1). As an example,
the normalized response of the TTE,
Inc., LEl182 ll-pole elliptic
antialiasing filter is shown in Figure
4.4. Notice that this filter is specified to
achieve at least 80dB attenuation
between fc and 1.2fc. The corresponding
passband ripple, return loss, delay, and
phase response are also shown in
Figure 4.4. This custom filter is available in comer frequencies up to
100MHz and in a choice of PC board,
BNC, or SMA with compatible packages.

CHARACTERISTICS OF TTE, INC., LE1182-SERIES
11-POLE ELLIPTICAL FILTER
Normalized Response

"\

10
20
30

en,:::,.

40

c

3!

ni

50

C(!)

60

 2M

Eq.l

The second eauation
ensures that fn is
placed in the center of a Nyquist zone:
.

4-8

~

.

f - 4fc
s - 2NZ -1 ' Eq. 2

where NZ = 1, 2, 3, 4, .... and NZ corresponds to the Nyquist zone in which the
carrier and its signal fall (see Figure
4.8).
NZ is normally chosen to be as large as
possible while still maintaining fs >
2M. This results in the minimum
required sampling rate. IfNZ is chosen
to be odd, then fc and it's signal will fall
in an odd Nyquist zone, and the image
frequencies in the first Nyquist zone
will not be reversed. Tradeoffs can be
made between the sampling frequency
and the complexity of the antialiasing
filter by choosing smaller values of NZ
(hence a higher sampling frequency).

As an example, consider a 4MHz wide
signal centered around a carrier frequency of 71MHz. The minimum reqwrea sampllng Irequency IS tneretore
. ,

...,..

•

• 'I

ft

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

ANTIALIASING FILTER FOR UNDERSAMPLING
fs - f1

T
DR

1

11-

-

-

-

I I

I
I
I
I
\ I
\ I
I
\1
I

IMAGE

o

11-

~

I\
I
I
I
I
I
I
I
I

\
\

I
I
I
)1
IE
I SIGNALS I
I
I II
OF

-

-

I I

I
I
IMAGE

IMAGE

\ : INTEREST : I
\1
I

O.5fS

-

~

1\
I \
I
I
I \1
I 1\
I
I I \
II

I

1.5fS

fS

~
I I

- -

-'"

I
I
I
I
I
\ I
I

2fS

STOPBAND ATTENUATION = DR
TRANSITION BAND: f2 TO 2fs • f2
f1 TO fs • f1
CORNER FREQUENCIES: f1' f2

BANDPASS FILTER SPECIFICATIONS:

Figure 4.7

CENTERING AN UNDERSAMPLED SIGNAL
WITHIN A NYQUIST ZONE
ZO~E

ZONE NZ • 1

ZONE NZ + 1

NZ

----I
I
\
I
\

I

----I
I
\
I
\
t
\
t
\
I
\
I
\
I
\
I
\
I
\
I
\
I
\

\

I
I
I
I
I
I
I
I

I
\
I
\
\
\
\
\

S~~~~~~~~~~~~S

r--

•

0.5f5

fs > 2~f

--

-~)I~E

fc
O. 5fs

•

-- ---1

-~)I~(
f =
5

0.5f5

4fc
2NZ .1 ,NZ

=1, 2, 3, ...

Figure 4.8
4-9

HIGH SPEED DESIGN TECHNIQUES

8MSPS. Solving Eq. 2 for NZ using fc =
71MHz and fs = 8MSPS yields NZ =
18.25. However, NZ must be an integer,
so we round 18.25 to the next lowest
integer, 18. Solving Eq. 2 again for fs
yields fs = 8.1143MSPS. The final
values are therefore fs = 8.1143MSPS,
fc = 71MHz, and NZ = 18.
Now assume that we desire more
margin for the antialiasing futer, and
we select fs to be 10MSPS. Solving Eq.

2 for NZ, using fc = 71MHz and fs =
10MSPS yields NZ = 14.7. We round
14.7 to the next lowest integer, giving
NZ = 14. Solving Eq. 2 again for fs
yields fs = 10.519MSPS. The fmal
values are therefore fs = 10.519MSPS,
fc = 71MHz, and NZ = 14.
The above iterative process can also be
carried out starting with fs and adjusting the carrier frequency to yield an
integer number for NZ.

DISTORTION AND NOISE IN AN IDEAL N-BIT ADC
Thus far we have looked at the implications of the sampling process without
considering the effects of ADC quantization. We will now treat the ADC as
an ideal sampler, but include the effects
of quantization.
The only errors (DC or AC) associated
with an ideal N-bit ADC are those
related to the sampling and quantization processes. The maxim urn error an
ideal ADC makes digitizing a DC input
signal is ±1/2LSB. Any AC signal
applied to an ideal N-bit ADC will
produce quantization noise whose rms
value (measured over the Nyquist
bandwidth, DC to fs/2) is approximately
equal to the weight of the least significant bit (LSB), q, divided by "'12. (See
Reference 2). This assumes that the
signal is at least a few LSBs in amplitude so that the ADC output always
changes state. The quantization error
signal from a linear ramp input is
approximated as a sawtooth waveform
with a peak-to-peak amplitude equal to
q, and its rms value is therefore q/"'12
(see Figure 4.9).
It can be shown that the ratio of the
rms value of a full scale sinewave to the
rms value of the quantization noise
(expressed in dB) is:
4 -10

SNR = 6.02N + 1.76dB,
where N is the number of bits in the
ideal ADC. This equation is only valid if
the noise is measured over the entire
Nyquist bandwidth from DC to fs /2. If
the signal bandwidth, BW, is less than
fs/2, then the SNR within the signal
bandwidth BW is increased because the
amount of quantization noise within
the signal bandwidth is smaller. The
correct expression for this condition is
given by:

SNR=6.02N+176dB+I010~2'~W ).
The above equation reflects the condition called oversampling, where the
sampling frequency is higher than
twice the signal bandwidth. The correction term is often called processing
gain. Notice that for a given signal
bandwidth, doubling the sampling
frequency increases the SNR by 3dB.
Although the rms value of the noise is
accurately approximated q/"'12, its
frequency domain content may be
highly correlated to the AC input signal. For instance, there is greater
correlation for low amplitude periodic

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

IDEAL N-BIT ADC QUANTIZATION NOISE
DIGITAL
CODE
OUTPUT

/

ANALOG
INPUT

"

/

_t~~ 1LSB

ERROR

/1/1/1/1./1/1/

7vvvvvv

=ql~12

•

RMS ERROR

•

SNR = 6.02N + 1.76dB +

-r--

10109~]
t2 BW FOR FS SINEWAVE
e

Figure 4.9

signals than for large amplitude random signals. Quite often, the assumption is made that the theoretical
quantization noise appears as white
noise, spread uniformly over the
Nyquist bandwidth DC to f s/2. Unfortunately, this is not true. In the case of
strong correlation, the quantization
noise appears concentrated at the
various harmonics of the input signal,
just where you don't want them.
In most applications, the input to the
ADC is a band of frequencies (usually
summed with some noise), so the quantiza tion noise tends to be random. In
spectral analysis applications (or in
performing FFTs on ADCs using spectrally pure sinewaves - see Figure
4.10), however, the correlation between

the quantization noise and the signal
depends upon the ratio of the sampling
frequency to the input signal. This is
demonstrated in Figure 4.11, where an
ideal 12-bit ADCs output is analyzed
using a 4096-point FFT. In the lefthand FFT plot, the ratio of the sampling frequency to the input frequency
was chosen to be exactly 32, and the
worst harmonic is about 76dB below
the fundamental. The right hand diagram shows the effects of slightly
offsetting the ratio, showing a relatively
random noise spectrum, where the
SFDR is now about 92dBc. In both
cases, the rms value of all the noise
components is qI..J12, but in the first
case, the noise is concentrated at harmonics of the fundamental.

4-11

HIGH SPEED DESIGN TECHNIQUES

DYNAMIC PERFORMANCE ANALYSIS
OF AN IDEAL N-BIT ADC

fs

ANALOG
INPUT

IDEAL
N·BIT
ADC

fa

N

-I-

BUFFER
MEMORY
M·WORDS

------")0

~ POIN T
M·POINT
FFT
PROCESSOR SPECT RAL
OUTPUT

Figure 4.10

EFFECT OF RATIO OF SAMPLING CLOCK TO INPUT
FREQUENCY ON SFDR FOR IDEAL 12-BIT ADC
fs I fa

=32

M = 4096

fs I fa

=32.25196850394

o~--~----~----~--~

-1Of-+-----------l
-20f-+--------------l
-30f-+---------~
-40f-+----------~

-50f-+--------------l
-601----+----------------1
-701-+---------------l

1000

SFDR

1500

2000

a

=76dBc

1000

1500

SFDR = 92dBc

Figure 4.11
4 -12

500

2000

HIGH SPEED DESIGN TECHNIQUES

DISTORTION AND NOISE IN PRACTICALADCS
A practical sampling ADC (one that has
an integral sample-and-hold), regardless of architecture, has a number of
noise and distortion sources as shown
in Figure 4.13. The wideband analog
front-end buffer has wideband noise,
non-linearity, and also finite bandwidth. The SHA introduces further nonlinearity, bandlimiting, and aperture
jitter. The actual quantizer portion of
the ADC introduces quantization noise,
and both integral and differential non-

linearity. In this discussion, assume
that sequential outputs of the ADC are
loaded into a buffer memory of length
M and that the FFT processor provides
the spectral output. Also assume that
the FFT arithmetic operations themselves introduce no significant errors
relative to the ADC. However, when
examining the output noise floor, the
FFT processing gain (dependent on M)
must be considered.

ADC MODEL SHOWING NOISE AND DISTORTION SOURCES
~----------~------------~

ANALOG
INPUT

N

SAMPLE
AND
HOLD

ADC

• NOISE
• DISTORTION
• BAND LIMITING

•
•
•
•

ENCODER

NOISE
DISTORTION
BAND LIMITING
APERTURE JITIER

•
•
•

h

~
BUFFER
MEMORY
M

M·POINT
FFT
PROCESSOR

• PROCESSING GAIN

POINT

SPECTRAL
OUTPUT

=10109 (~

)

• ROUNDOFF ERROR (NEGLIGIBLE)

Figure 4.13

4 -14

-

-

-

QUANTIZATION NOISE
DIFFERENTIAL NON·LINEARITY
INTEGRAL NON·L1NEARITY

N

TEST
SYSTEM

TO MEMORY

1---1--- -

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

Equivalent Input Referred Noise (Thermal Noise)

The wideband ADC internal circuits
produce a certain amount of wideband
rms noise due to thermal effects. This
noise is present even for DC input
signals, and accounts for the fact that
the output of most wideband ADCs is a
distribution of codes, centered around
the nominal value of a DC input (see
Figure 4.14). To measure its value, the
input of the ADC is grounded, and a
large number of output samples are

collected and plotted as a histogram
(sometimes referred to as a groundedinput histogram). Since the noise is
approximately Gaussian, the standard
deviation of the histogram is easily
calculated (see Reference 3), corresponding to the effective input rms
noise. It is common practice to express
this rms noise in terms ofLSBs, although it can be expressed as an nIlS
voltage.

HISTOGRAM OF 5000 CONVERSIONS
FOR A DC INPUT SHOWS 5 LSB p-p OR
O.8LSB RMS EQUIVALENT INPUT NOISE
3000 - - - - - - - - - - - - - - - - - - - ,

>~ 2000

1--------

W

::>

o
w
ex:
u.
w
c
o
U

1000

1--------

(X - 2) (X - 1)

(X)

(X + 1) (X + 2) (X + 3)

CODE

Figure 4.14

4-15

HIGH SPEED DESIGN TECHNIQUES

Integral and Differential Non-Linearity
The overall integral non-linearity of an
ADC is due to the integral non-linearity
of the front-end and SHA as well as the
overall integral non-linearity in the
ADC transfer function. However, differential non-linearity is due exclusively to
the encoding process and may vary
considerably dependent on the ADC
encoding architecture. Overall integral

non-linearity produces distortion products whose amplitude varies as a function of the input signal amplitude. For
instance, second-order intermodulation
products increase 2dB for every IdB
increase in signal level, and third-order
products increase 3dB for every IdB
increase in signal level.

QUANTIFYING ADC DYNAMIC PERFORMANCE
•

Harmonic Distortion

•

Worst Harmonic

•

Total Harmonic Distortion (THD)

•

Total Harmonic Distortion Plus Noise (THD + N)

•

$ignal-to-Noise-and-Distortion Ratio (SINAD, or SIN +D)

•

Effective Number of Bits (ENOB)

•

Signal-to-Noise Ratio (SNR)

•

Analog Bandwidth (Full-Power, Small-Signal)

•

Spurious Free Dynamic Range (SFDR)

•

Two-Tone Intermodulation Distortion

•

Noise Power Ratio (NPR)
Figure 4.15

The differential non-linearity in the
ADC transfer function produces distortion products which not only depend on
the amplitude of the signal but the
posi tioning of the differential nonlinearity along the ADC transfer function. Figure 4.16 shows two ADC
transfer functions containing differential non-linearity. The left-hand diagram shows an error which occurs at
midscale. Therefore, for both large and
small signals, the signal crosses
through this point producing a distortion product which is relatively inde4 -16

pendent of the signal amplitude. The
right-hand diagram shows another
ADC transfer function which has differential non-linearity errors at 114 and
3/4 full scale. Signals which are above
1/2 scale peak-to-peak will exercise
these codes, while tliose less and 112
scale peak-to-peak will not.
The design of most high-speed ADCs is
such that differential non-linearity is
spread across the entire ADC range.
Therefore, for signals which are within
a few dB of full scale, the overall inte-

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

ADC DNL ERRORS
CODE
OUT

CODE
OUT

IN

MIDSCALE DNL

1/4FS, 3/4FS DNL

Figure 4.16

gral non-linearity of the transfer function determines the distortion products.
For lower level signals, however, the
harmonic content becomes dominated

by the differential non-linearities and
does not generally decrease proportionally with decreases in signal amplitude.

Harmonic Distortion, Worst Harmonic, Total Harmonic Distortion (THD),
Total Harmonic Distortion Plus Noise (THD + N)
There are a number of ways to quantify
the distortion of an ADe. An FFT
analysis can be used to measure the
amplitude of the various harmonics of a
signal as shown in Figure 4.17. The
harmonics of the input signal can be
distinguished from other distortion
products by their location in the frequency spectrum. The figure shows a
7MHz input signal sampled at 20MSPS
and the location of the first 9 harmonics. Aliased harmonics of fa fall at
frequencies equal to I ±Kfs±nfa I , where
n is the order of the harmonic, and K =
0, 1, 2, 3, .... The second and third

harmonics are generally the only ones
specified on a data sheet because they
tend to be the largest, although some
data sheets may specify the value of the
worst harmonic. Harmonic distortion is
normally specified in dBc (decibels
below carrier), although at audio frequencies it may be specified as a per-'
centage. Harmonic distortion is
specified with an input signal near full
scale (generally 0.5 to 1dB below full
scale to prevent clipping). For signals
much lower than full scale, other distortion products (not direct harmonics)
may limit performance.
4-17

HIGH SPEED DESIGN TECHNIQUES

LOCATION OF HARMONIC DISTORTION PRODUCTS:
INPUT SIGNAL 7MHz, SAMPLING RATE 20MSPS

=

=

RELATIVE
AMPLITUDE
HARMONICS AT: I±Kfs±nfal
n ORDER OF HARMONIC, K

=

=0, 1, 2, 3, ...

3

2
6

I

i i
I

I

3

4

5

9
J

1

2

4
7

6

7

8

II

I

9

10

FREQUENCY (MHz)

Figure 4.17

Total harmonic distortion (THD) is the
ratio of the rms value of the fundamental signal to the mean value of the rootsum-square of its harmonics (generally,
only the first 5 are significant). THD of
an ADC is also generally specified with
the input signal close to full scale.
Total harmonic distortion plus noise
(THD+ N) is the ratio of the rms value

of the fundamental signal to the mean
value of the root-sum-square of its
harmonics plus all noise components
(excluding DC). The bandwidth over
which the noise is measured must be
specified. In the case of an FFT, the
bandwidth is DC to f s/2. (If the bandwidth of the measurement is DC to fgl2,
THD+N is equal to SINAD - see below).

Signal-to-Noise-and-Distortion Ratio (SINAD), Signal-to-Noise Ratio (SNR),
alld Effective Number of Bits (ENOB)

SINAD and SNR deserve careful attention, because there is still some variation between ADC manufacturers as to
their precise meaning. Signal-to-noiseand Distortion (SINAD, or SIN+D) is
the ratio of the rms signal amplitude to
the mean value of the root-sum-square
(RSS) of all other spectral components,
including haimonics, but excluding DC.
SINAD is a good indication of the over4 -18

all dynamic performance of an ADC as
a function of input frequency because it
includes all components which make up
noise (including thermal noise) and
distortion. It is often plotted for various
input amplitudes. SINAD is equal to
THD+ N if the bandwidth for the noise
measurement is the same. A typical
-nll'\.f. 1'1'\'" .f. hL) A. naoo() 1 ,)_'h~+ 1 ()M~P~
ADe is shown in Figure 4.19.
}J.LV" .LV.&.

" ... .1.\;;1 4..L&....I'V6J6.lV

~IW

...., ... " ,

..Lv ... .,. ... .....,... .....,

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

SINAD, ENOB, AND SNR
•

SINAD (Signal-to-NOise-and-Distortion Ratio):
The ratio of the rms signal amplitude to the mean value of
the root-sum-squares (RSS) of all other spectral components,
including harmonics, but excluding DC

•

ENOB (Effective Number of Bits):
ENOB = SINAD -1.76dB
6.02

•

SNR (Signal-to-Noise Ratio, or Signal-to-Noise Ratio
Without Harmonics):
The ratio of the rms signal amplitude to the mean value of
the root-sum-squares (RSS) of all other spectral components,
excluding the first 5 harmonics and DC

Figure 4.18

AD9220 12-BIT, 10MSPS ADC SINAD AND ENOB
VS. INPUT FREQUENCY FOR SAMPLING RATE = 10MSPS:
SINGLE-ENDED DRIVE, Vern +2.5V, INPUT SPAN 2V p-p

=

=

80

13
12.2

75
-0.5dB
I

70

(""""III

-6db
al

65

~

"0

I

11.3

~~

60

c
~
z
U5 55

-20dB

~

~

CJ)

CD

9.7 0

,

~

50
45

40
0.1

10.5

~

8.8

zw

8

7.2
1.0

10.0

6.3

FREQUENCY - MHz

Figure 4.19
4-19

HIGH SPEED DESIGN TECHNIQUES

The SINAD plot shows where the AC
performance of the ADC degrades due
to high-frequency distortion and is
usually plotted for frequencies well
above the Nyquist frequency so that
performance in undersampling applications can be evaluated. SINAD is often
converted to effective-number-of-bits
(ENOB) using the relationship for the
theoretical SNR of an ideal N-bit ADC:
SNR = 6.02N + 1. 76dB. The equation is
solved for N, and the value of SINAD is
substituted for SNR:
ENOB = SINAD-176dB
6.02
.

Signal-to-noise ratio (SNR, or SNRwithout-harmonics) is calculated the.
same as SINAD except that the signal
harmonics are excluded from the calculation, leaving only the noise terms. In
practice, it is only necessary to exclude
the first 5 harmonics since they dominate. The SNR plot will degrade at high
frequencies also, but not as rapidly as
SINAD because of the exclusion of the
harmonic terms.
Many current ADC data sheets somewhat loosely refer to SINAD as SNR, so
the engineer must be careful when
interpreting these specifications.

Analog Bandwidth
The analog bandwidth of an ADC is
that frequency at which the spectral
output of the fundamental swept frequency (as determined by the FFT
analysis) is reduced by 3dB. It may be
specified for either a small signal
(SSBW- small signal bandwidth), or a
full scale signal (FPBW- full power
bandwidth), so there can be a wide
variation in specifications between
manufacturers.
Like an amplifier, the analog bandwidth specification of a converter does

4 -20

not imply that the ADC maintains good
distortion performance up to its bandwidth frequency. In fact, the SINAD (or
ENOB) ofmostADCs will begin to
degrade considerably before the input
frequency approaches the actual3dB
bandwidth frequency. Figure 4.20
shows ENOB and full scale frequency
response of an ADC with a FPBW of
1MHz, however, the ENOB begins to
drop rapidly above 100kHz.

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

ADC GAIN (BANDWIDTH) AND ENOB VERSUS FREQUENCY
SHOWS IMPORTANCE OF ENOB SPECIFICATION
FPSW

I
I
I
I

GAIN (FS INPUT)

=1MHz
GAIN

I

ENOS (FS INPUT)
ENOS
ENOS (-20dS INPUT)

10

100

1k

10k

100k

1M

10M

ADCINPUTFREQUENCY(H~

Figure 4.20

Spurious Free Dynamic Range (SFDR)
Probably the most significant specification for an ADC used in a communications application is its spurious free
dynamic range (SFDR). The SFDR
specification is to ADCs what the third
order intercept specification is to mixers
and LNAs. SFDR of an ADC is defined
as the ratio of the rms signal amplitude
to the rms value of the peak spurious
spectral content (measured over the
entire first Nyquist zone, DC to f s/2).
SFDR is generally plotted as a function
of signal amplitude and may be expressed relative to the signal amplitude
(dBc) or the ADC full scale (dBFS).
For a signal near full scale, the peak
spectral spur is generally determined
by one of the first few harmonics of the
fundamental. However, as the signal

falls several dB below full scale, other
spurs generally occur which are not
direct harmonics of the input signal.
This is because of the differential nonlinearity of the ADC transfer function
as discussed earlier. Therefore, SFDR
considers all sources of distortion,
regardless of their origin.
The AD9042 is a 12-bit, 41MSPS
wideband ADC designed for communications applications where high SFDR
is important. The SFDR for a 19.5MHz
input and a sampling frequency of
41MSPS is shown in Figure 4.21. Note
that a minimum of 80dBc SFDR is
obtained over the entire first Nyquist
zone (DC to 20MHz). The plot also
shows SFDR expressed as dBFS.

4-21

HIGH SPEED DESIGN TECHNIQUES

AD9042 12-BIT, 41MSPS ADe
SFDR VS. INPUT POWER LEVEL
100
~ 90

--..... ....

!Xl

~

z
~

!Xl

80

70

"C

I

en

60 I-

=

50

3l

40

a:
::;)

=

./ .. /

."
d~ ." .....
~

~ 30

U

t;

a:
~

20

/....

-'

w

I........

10

......

~80

-

dBFS

ENCODE 41 MSPS
AIN 19.5MHz

::;)

o

'"

--------

~

, / ......
.. '

-"
.... .. '

...............

/ / ..
.,,**#

....

.'

=

SFDR 80dB
REFERENCE LINE

-

V .. ' ."

. /f.--- I."
'

." .. '

....

-70

..
..'

-60

-50

-40

-30

-20

-10

0

ANALOG~PUTPOWERLEVEL-dBFS

Figure 4.21

SFDR is generally much greater than
the ADCs theoretical N-bit SNR (6.02N
+ 1.76dB). For example, the AD9042 is
a 12-bit ADC with an SFDR of 80dBc
and a typical SNR of 65dBc (theoretical
SNR is 74dB). This is because there is a
fundamental distinction between noise

and distortion measurements. The
process gain of the FFT (33dB for a
4096-point FFT) allows frequency spurs
well below the noise floor to be observed. Adding extra resolution to an
ADC may serve to increase its SNR but
mayor may not increase its SFDR.

Two Tone Intermodulation Distortion
Two tone IMD is measured by applying
two spectrally pure sinew aves to the
ADC at frequencies fl and £2, usually
relatively close together. The amplitude
of each tone is set slightly more than
6dB below full scale so that the ADC
does not clip when the two tones add inphase. The location of the second and
third-order products are shown in
Figure 4.22. Notice that the secondorder products fall at frequencies which
4 - 22

can be removed by digital filters. However, the third-order products 2£2-£1
and 2£1-£2 are close to the original
signals and are more difficult to filter.
Unless otherwise specified, two-tone
IMD refers to these third-order products. The value of the IMD product is
expressed in dBc relative to the value of
either of the two original tones, and not
to their sum.

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

SECOND AND THIRD-ORDER INTERMODULATION
PRODUCTS FOR f1 = 51\11Hz, f2=6r,11Hz

f1

G)
G)

f2

= SECOND ORDER IMD PRODUCTS
= THIRD ORDER IMD PRODUCTS

NOTE: f1=5MH~~=6MHz

4

5

6

7

10

11

12

15

16

17 18

FREQUENCY: MHz

Figure 4.22

Note, however, that if the two tones are
close to fs/4, then the aliased third
harmonic of the fundamental can make
the identification of the actual 2£'2-£1
and 2£1-£2 products difficult. Similarly,
if the two tones are close to fs/3, the
aliased second harmonic may interfere
with the measurement.
The concept of second and third-order
intercept points is not valid for an ADC,
because the distortion products do not
vary in a predictable manner (as a
function of signal amplitude). The ADC
does not gradually begin to com press
signals approaching full scale (there is

no ldB compression point), it acts as a
hard limiter as soon as the signal
exceeds the ADC input range, thereby
suddenly producing extreme amounts of
distortion because of clipping.
On the other hand, for signals much
below full scale, the distortion floor
remains relatively constant and is
independent of signal level. This is
illustrated in Figure 4.23 for the
AD9042, where two-tone SFDR is
plotted as a function of signal level. The
plot indicates that the distortion floor
ranges from 85 to 90dBFS regardless of
the input signal amplitude.

4-23

HIGH SPEED DESIGN TECHNIQUES

AD9042 12-BIT, 41MSPS ADC TWO-TONE SFDR
100

--

~ 90
III

~
z

~

80

en

::J

o

0:

::J

g,

I"-

/

70

III

1J

I

-

dBFS

60

_

ENCODE
F1

50 -

F2

=19.3MHz
=19.51MHz

/

~ 30
20

~

10

a:

##

io'"

*#,,*

(.=##~FDR =80dB

###

REFERENCE LINE

.***

-

V ## ###

~ ##

()

t;

##

V" ###

/

dB;"'"

w

###

. / ~######

=41 MSPS

40

i-o

/

"**"",,
##

• .,**"

~80

-70

-60

-50

-40

INPUT POWER LEVEL (F1

-30

=F2) -

-20

-10

0

dBFS

Figure 4.23

Noise Power Ratio (NPR)
Noise power ratio testing has been used
extensively to measure the transmission characteristics of Frequency Division Multiplexed (FDM)
communications links (see Reference 4).
In a typical FDM system, 4kHz wide
voice channels are "stacked" in frequency bins for transmission over
coaxial, microwave, or satellite equipment. At the receiving end, the FDM
data is demultiplexed and returned to
4kHz individual baseband channels. In
an FDM system having more than
approximately 100 channels, the FDM
signal can be approximated by
Gaussian noise with the appropriate
bandwidth. An individual 4kHz channel
can be measured for "quietness" using a
narrow-band notch (bandstop) filter
and a specially tuned receiver which
measures the noise power inside the
4kHz notch (see Figure 4.24).
4 -24

Noise Power Ratio (NPR) measurements are straightforward. With the
notch filter out, the rms noise power of
the signal inside the notch is measured
by the narrowband receiver. The notch
filter is then switched in, and the
residual noise inside the slot is measured. The ratio of these two readings
expressed in dB is the NPR. Several
slot frequencies across the noise bandwidth (low, midband, and high) are
tested to characterize the system adequately. NPR measurements on ADCs
are made ina similar manner except
the analog receiver is replaced by a
buffer memory and an FFT processor.
NPR is usually plotted on an NPR
curve. The NPR is plotted as a function
of rms noise level referred to the peak
range of the system. For very low noise
loading level, the undesired noise (in

HIGH SPEED SAMPLING AND HIGH SPEED

non-digital systems) is primarily thermal noise and is independent of the
input noise level. Over this region of the
curve, a 1dB increase in noise loading
level causes a 1dB increase in NPR. As
the noise loading level is increased, the
amplifiers in the system begin to overload, creating intermodulation products
which cause the noise floor of the system to increase. As the input noise
increases further, the effects of "overload" noise predominate, and the NPR
is reduced dramatically. FDM systems
are usually operated at a noise loading
level a few dB below the point of maximum NPR.

ADCs

In a digital system containing an ADe,
the noise wi thin the slot is primarily
quantization noise when low levels of
noise input are applied. The NPR curve
is linear in this region. As the noise
level increases" there is a one-for-one
correspondence between the noise level
and the NPR. At some level, however,
"clipping" noise caused by the hardlimiting action of the ADe begins to
dominate. A theoretical curve for 10,
11, and 12-bit ADCs is shown in Figure
4.25 (see Reference 5). Peak NPR and
corresponding loading levels are shown
in Figure 4.26.

NOISE POWER RATIO (NPR) MEASUREMENTS
GAUSSIAN
NOISE
SOURCE

TRANSMISSION
SYSTEM

LPF

GAUSSIAN
NOISE
SOURCE

N

ADC

LPF

NARROWBAND
RECEIVER

BUFFER
MEMORY
AND FFT
PROCESSOR

RMS
NOISE
LEVEL

(dB)

FREQUENCY

0.5f5

Figure 4.24
4-25

HIGH SPEED DESIGN TECHNIQUES

THEORETICAL NPR FOR 10, 11, 12-BIT ADCs
ADe RANGE = ±Vo

NPR
(dB)

----62.7dB

60

k= Vo
(J

(J

=RMS NOISE LEVEL
----57.1d8

55

---51.6dB

50

45 ~-----+~----r------r------~--~
-30
·10
·25
·20
·15
RMS NOISE LOADING LEVEL = ·20Iog(k) dB

Figure 4.25

THEORETICAL NPR SUMMARY
BITS

kOPTIMUM

k(dB)

MAX NPR (dB)

8

3.92

11.87

40.60

9
10
11
12
13
14

4.22

12.50

46.05

4.50
4.76

13.06
13.55

5.01
5.26
5.49
5.72
5.94

14.00
14.41
14.79
15.15

51.56
57.12
62.71
68.35
-74.01
79.70

15.47

85.40

15
16

ADC Range = ±Vo
k Vo I cr
cr = RMS Noise Level

=

Figure 4.26
4 -26

--

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

In multi-channel high frequency communication systems, NPR can also be
used to simulate the distortion caused
by a large number of individual channels, similar to an FDM system. A
notch filter is placed between the noise
source and the ADC, and an FFT
output is used in place of the analog
receiver. The width of the notch filter is
set for several MHz as shown in Figure

4.27 for the AD9042. NPR is the
"depth" of the notch. An ideal ADC will
only generate quantization noise inside
the notch, however a practical one has
additional noise components due to
intermodulation distortion caused by
ADC non-linearity. Notice that the NPR
is about 60dB compared to 62.7dB
theoretical.

AD9042 12-BIT, 41MSPS ADC NPR
MEASURES GOdB (G2.7dB THEORETICAL)
cc

"0

~ -20~-+--~---~-4---~---+-~~-+---4-~

II

...I



~

-80

...I
W

a:
a: -100
w

:r:

oCl.

-120

de

4.1

8.2

12.3

16.4

20.5

FREQUENCY - MHz

Figure 4.27

Aperture Jitter and Aperture Delay
Another reason that the SNR of an
ADC decreases with input frequency
may be deduced from Figure 4.28,
which shows the effects of phase jitter
(or aperture time jitter) on the sampling clock of an ADC (or internal in the
sample-and-hold). The phase jitter
causes a voltage error which is a func-

tion of slew rate and results in an
overall degradation in SNR as shown in
Figure 4.29. This is quite serious,
especially at higher input/output frequencies. Therefore, extreme care must
be taken to minimize phase noise in the
sampling/reconstruction clock of any
sampled data system. This care must
4-27

HIGH SPEED DESIGN TECHNIQUES

extend to all aspects of the clock signal:
the oscillator itself (for example, a 555
timer is absolutely inadequate, but
even a quartz crystal oscillator can give
problems if it uses an active device
which shares a chip with noisy logic);
the transmission path (these clocks are
very vulnerable to interference of all
sorts), and phase noise introduced in
the ADC or DAC. A very common
source of phase noise in converter

circuitry is aperture jitter in the integral sample-and-hold (SHA) circuitry.
A decade or so ago, sampling ADCs
were built up from a separate SHA and
ADC. Interface design was difficult, and
a key parameter was aperture jitter in
the SHA. Today, most sampled data
systems use sampling ADCs which
contain an integral SHA. The aperture
jitter of the SHA may not be specified

EFFECTS OF APERTURE AND SAMPLING CLOCK JITTER
dv
/).v=-_
dt

ANALOG
INPUT
dv

dt =

/).t

~
/). v

SLOPE

RMS

= APERTURE JITIER ERROR

t
/.--r----------

t
-7

I

~

NOMINAL

HELD
OUTPUT

I~ /). t RMS =APERTURE JITIER
HOLD

TRACK

Figure 4.28

as such, but this is not a cause of concern if the SNR or ENOB is clearly
specified, since a guarantee of a specific
SNR is an implicit guarantee of an
adequate aperture jitter specification.
However, the use of an additional highperformance SHA will sometimes
improve the high-frequency ENOB of a
even the best sampling ADC by presenting "DC" to the ADC, and may be
more cost-effective than replacing the
ADC with a more expensive one.
It should be noted that there is also a
fixed component which makes up the
4 -28

ADC aperture time. This component,
usually called effective aperture delay
time, does not produce an error. It
simply results in a time offset between
the time the ADC is asked to sample
and when the actual sample takes place
(see Figure 4.30), and may be positive
or negative. The variation or tolerance
placed on this parameter from part to
part is important in simultaneous
sampling applications or other applications such as I and Q demodulation
where two ADCs are required to track
each other.

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

SNR DUE TO APERTURE AND SAMPLING CLOCK JITTER
16

100

14
80
12
SNR
(dB)

ENOB

10

60

8

t.

40

J .:: 7ns

6

4
20

o
3

10

30

100

FULLSCALE SINEWAVE INPUT FREQUENCY (MHz)

Figure 4.29

EFFECTIVE APERTURE DELAY TIME
, ,+ FS
ANALOG INPUT
SINEWAVE

- - - - - - - - / - - - - - 'ov
\

,
- FS

+te

- te

SAMPLING
CLOCK

Figure 4.30
4-29

HIGH SPEED DESIGN TECHNIQUES

HIGH SPEED ADC ARCIDTECTURES
Successive Approximation ADes
The successive approximation (SAR)
ADC architecture has been used for
decades and is still a popular and cost
effective form of converter for sampling
frequencies of 1MSPS orless. A simplified block diagram of a SAR ADC is
shown in Figure 4.31. On the
START CONVERT command, all the bits
of the successive approximation register
(SAR) are reset to "0" except the MSB
which is set to "1". Bit 1 is then tested in
the following manner: If the DAC output
is greater than the analog input, the

MSB is reset, otherwise it is left set.
The next most significant bit is then
tested by setting it to "1". If the DAC
output is greater than the analog
input, this bit is reset, otherwise it is
left set. The process is repeated with
each bit in turn. When all the bits
have been set, tested, and reset or not
as appropriate, the contents of the
SAR correspond to the digital value of
the analog input, and the conversion
is complete.

SUCCESSIVE APPROXIMATION ADC

AN ALOG
INP UT

EOCOR
DRDY

COMPARATOR

~

SHA

~V
~

DAC

,

SAR*

/

I

START
CONVERT

I

/

*SUCCESSIVE
APPROXIMATION
REGISTER

DIGITAL
OUTPUT

Figure 4.31

An N-bit conversion takes N steps. It
would seem on superficial examination
that a 16-bit converter would have a
conversion time that is twice as long as

an 8=bit one, but this is not the case. In
an 8-bit converter, the DAC must settle
4 - 30

to 8-bit accuracy before the bit decision is made, whereas in a 16-bit
converter, it must settle to 16-bit
accuracy, which takes a lot longer. In
•
0 h·
•
•
practIce,
o-ult succeSSIve apprOilli-nation ADCs can convert in a few hun-

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

dred nanoseconds, while 16-bit ones
will generally take several microseconds.
The classic SAR ADC is only a quantizer: no sampling takes place, and for
an accurate conversion, the input must
remain constant for the entire conversion period. Most modern SAR ADCs
are sampling types and have an internal sample-and-hold so that they can
process AC signals. They are specified
for both AC and DC applications. A
SHA is required in a SAR ADC because
the signal must remain constant during
the entire N-bit conversion cycle.
The accuracy of a SAR ADC depends
primarily on the accuracy (differential
and integral linearity , gain, and offset)
of the internal DAC. Until recently, this
accuracy was achieved using laser
trimmed thin film resistors. Modem
SAR ADCs utilize CMOS switched
capacitor charge redistribution DACs.
This type of DAC depends on the accurate ratio matching and stability of onchip capacitors rather than thin film

resistors. For resolutions greater than
l2-bits, on-chip auto calibration techniques using an additional calibration
DAC and the accompanying logic can
accomplish the same thing as thin film
laser trimmed resistors, at much less
cost. Therefore, the entire ADe can be
made on a standard sub-micron CMOS
process.
The successive approximation ADC has
a very simple structure, is low power,
and has reasonably fast conversion
times «lMSPS). It is probably the
most widely used ADC architecture,
and will continue to be used for medium
speed and medium resolution applications.
Current l2-bit SAR ADCs achieve
sampling rates up to about lMSPS, and
l6-bit ones up to about 300kSPS.
Examples of typical state-of-the-art
•
SAR ADCs are the AD7892 (l2-bits at .
600kSPS), the AD976/977 (16-bits at
lOOkSPS), and the AD7882 (l6-bits at
300kSPS).

Flash Converters
Flash ADCs (sometimes called parallel
ADCs) are the fastest type of ADC and
use large numbers of comparators. An
N-bit flash ADC consists of2 N resistors
and 2N_l comparators arranged as in
Figure 4.32. Each comparator has a
reference voltage which is 1 LSB higher
than that of the one below it in the
chain. For a given input voltage, all the
comparators below a certain point will
have their input voltage larger than
their reference voltage and a "1" logic

output, and all the comparators above
that point will have a reference voltage
larger than the input voltage and a "0"
logic output. The 2N_l comparator
outputs therefore behave in a way
analogous to a mercury thermometer,
and the output code at this point is
sometimes called a thermometer code.
Since 2N_l data outputs are not really
practical, they are processed by a
decoder to an N-bit binary output.

4-31

HIGH SPEED DESIGN TECHNIQUES

FLASH OR PARALLEL ADC
ANALOG
INPUT

1.5R

R

R
PRIORITY
ENCODER
AND LATCH

R

N

DIGITAL

1--+/--'0 OUTPUT

R

R

R

Figure 4.32

The input signal is applied to all the
comparators at once, so the thermometer output is delayed by only one
comparator delay from the input, and
the encoder N-bit output by only a few
gate delays on top of that, so the process is very fast. However, the architecture uses large numbers of resistors
and comparators and it limited to low
resolutions, and if it is to be fast, each
comparator must run at relatively high
power levels. Hence, the problems of
flash ADCs include limited resolution,
high power dissipation because of the
large number of high speed comparators (especially at sampling rates
greater than 50MSPS), and relatively
large (and therefore expensive) chip
sizes. In addition, the resistance of the
reference resistor chain must be kept
low to supply adequate bias current to
the fast comparators, so the voltage
reference has to source quite large
currents (>10 mA).
4 - 32

In practice, flash converters are available up to 10-bits, but more commonly
they have 8-bits of resolution. Their
maximum sampling rate can be as high
as 500 MSPS, and input full-power
bandwidths in excess of300 MHz.
But as mentioned earlier, full-power
bandwidths are not necessarily
full-resolution bandwidths. Ideally, the
comparators in a flash converter are
well matched both for DC and AC
characteristics. Because the strobe is
applied to all the comparators simultaneously, the flash converter is inherently a sampling converter. In practice,
there are delay variations between the
comparators and other AC mismatches
which cause a degradation in ENOB at
high input frequencies. This is because
the inputs are slewing at a rate comparable to the comparator conversion
t;T\'l
a
" ......... .&.v.

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

The input to a flash ADC is applied in
parallel to a large number of comparators. Each has a voltage-variablejunction capacitance, and this
signal-dependent capacitance results in
all flash ADes having reduced ENOB
and higher distortion at high input
frequencies. A model is shown in Figure
4.33, where the input capacitance is
modeled as a fIxed 10pF capacitor in
parallel with a variable capacitor

(modeled as a diode with a zero-bias
junction capacitance of 6pF). As the
input changes from -FS to +FS, the
total input capacitance changes from
about 12.5 to 16pF. The wideband
external drive amplifier is isolated
from the flash converter by a 50n
series resistor. The distortion of this
circuit degrades from about 70dBc at
1MHz to 35dBc at 100MHz.

SIGNAL·DEPENDENT INPUT CAPACITANCE CAUSES·
DISTORTION AT HIGH FREQUENCIES

r---------------I
I
I
CJO 6pF
I
I
I
+FS
IL________________ _

=

THO
(dB)

II

FLASH INPUT MODEL

70

60
50
40
30

1

100

10
INPUT FREQUENCY (MHz)

Figure 4.33

High data rate digital communications
applications such as set-top boxes for
direct broadcast satellites (DBS) require dual 6 or 8-bit high speed ADes
to perform quadrature demodulation. A
dual flash converter ensures good
matching between the two ADes. The
AD9066 (duaI6-bit, 60MSPS) flash
converter is representative of this type

of converter. The AD9066 is fabricated
on a BiCMOS process, operates on a
single +5V supply, and dissipates
400mW. The effective bit performance
of the device is shown in Figure 4.34.
Note that the device maintains greater
than 5 ENOBs up to 60MSPS analog
input.

4-33

HIGH SPEED DESIGN TECHNIQUES

AD9066 DUAL 6-BIT, 60MSPS ADC ENOB
VS.ANALOGINPUTFREQUENCY
5.8
ENboDE =
5.7

"1\

5.6

J!!
ii5
I
CD

\

5.5

o

z
w

Jo MS~S

5.4

\

1\

1\,

5.3

1\

5.2
10

1

100

MHz

Figure 4.34

"INTERPOLATING" FLASH REDUCES THE NUMBER
OF PREAMPLIFIERS BY FACTOR OF TWO
ANALOG
ANALOG

INPUT

INPUT

V2------------ ----

LATCH
2

V2

I

~A------- ---~----DECODE

ViA= Vi + V2
2

V1 - - -

LATCH
iA

B

-A

I
I
I
I
I
I

I

I

I
I
I
I
I
I
I
I

I
I
I
I
I
I

---1---'----A

B

LATCH
1
Vi

A

LATCH
I STROBE

Figure 4.35
4 - 34

B

A

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

Part of the reason for the excellent
performance of the AD9066 is the use of
an interpolation scheme that reduces
the number of differential amplifiers
required by a factor of two (see Reference 6). The architecture enables 64
possible quantization levels to be determined with only 32 preamplifiers which
drive 63 latches. This keeps the input
capacitance to a minimum (lOpF) and
reduces total power dissipation of the
device. The basic interpolation circuit is
shown in Figure 4.35.
The preamplifiers are low-gain gm
stages whose bandwidth is proportional
to the tail currents of the differential
pairs. Consider the case for a positivegoing ramp input which is initially
below the reference to AMP Al, V1. As

the input signal approaches Vl, the
differential 0'l:!!Put of Al approaches
zero (i.e., A = A), and the decision point
is reached. The output of Al drives the
differential input of LATCH 1. As the
input signals continues to go positive, A
continues to go positive, and B begins to
go negative. The interpolated decision
point is determined when A =B. As the
input continues positive, the third
decision point is reached when B = B.
This novel architecture reduces the
ADC input capacitance and thereby
minimizes its change with signal level
and the associated distortion. The input
capacitance of the AD9066 is only about
lOpF. Key specifications for the device
are summarized in Figure 4.36.

II
AD9066 DUAL 6-BIT, 60MSPS FLASH ADC
KEY SPECIFICATIONS

•
•
•
•
•
•
•
•

Input Range: 500mV p-p
Input Impedance: 50kn 111 OpF
ENOS: 5.7bits @ 15.5MHz Input
On-Chip Reference
Power Supply: Single +5V
Power Dissipation: 400mW
Package: 28-pin SOIC
Ideal for Quadrature Demodulation

Figure 4.36
4-35

HIGH SPEED DESIGN TECHNIQUES

Subranging (Pipelined) ADCs
Although it is not practical to make
flash ADCs with high resolution, flash
ADCs are often used as subsystems in
"sub ranging" ADCs (sometimes known
as "half-flash ADCs"), which are capable of much higher resolutions (up to
16-bits).

four significant bits (MSBs) are digitized by the first flash (to better than 8bits accuracy), and the 4-bit binary
output is applied to a 4-bit DAC (again,
better than 8-bit accurate). The DAC
output is subtracted from the held
analog input, and the resulting residue
signal is amplified and applied to the
second 4-bit flash. The outputs of the
two 4-bit flash converters are then
combined into a single 8-bit binary
output word. If the residue signal range
does not exactly fill the range of the
second flash converter, non-linearities
and perhaps missing codes will result.

A block diagram of an 8-bit subranging
ADC based upon two 4-bit flash converters is shown in Figure 4.37. Although 8-bit flash converters are
readily available at high sampling
rates, this example will be used to
illustrate the theory. The conversion
process is done in two steps. The first

8-BIT SUBRANGING ADC

ANALOG
IN ~T

-

GAIN

+

SHA
4-81T
FLASH
.I

~

t

RES IOUE
SIG NAL

/

4-81T
FLASH

4-81T
OAC

1/ 4
./

1/4

OUTPUT REGISTER
)"8
Figure 4.37

Modern subranging ADCs use a technique called digital correction to eliminate problems associated with the
architecture of Figure 4.37. A simplified block diagram of a 12-bit digitally
corrected sub ranging (DCS) ADC is
shown in Figure 4.38. The architecture
4 - 36

is similar to that used in the AD9042
12-bit, 41MSPS ADC. Note that a 6-bit
and an 7-bit ADC have been used to
achieve an overall 12-bit output. These
are not flash ADCs, but utilize a magnitude-amplifier (MagAmp TM) architecture which will be described shortly.

HIGH SPEED SAMPLING AND HIGH SPEED

ADCs

AD904212-BIT, 41MSPS PIPELINED SUBRANGING ADC
WITH DIGITAL ERROR CORRECTION
ANALOG
INPUTu-----t

SHA
1

6·BIT
ADC

SHA
2

SHA
3

6·BIT
DAC

7·BIT
ADC

6

BUFFER
REGISTER

7

6

ERROR CORRECTION LOGIC
12

OUTPUT REGISTERS
12

II

Figure 4.38

If there were no errors in the first-stage
conversion, the 6-bit "residue" signal
applied to the 7-bit ADC by the summing amplifier would never exceed onehalf of the range of the 7-bit ADC. The
extra range in the second ADC is used
in conjunction with the error correction
logic (usually just a full adder) to correct the output data for most of the
errors inherent in the traditional uncorrected subranging converter archi tecture. It is important to note that the
6-bit DAC must be better than 12-bit
accurate, because the digital error
correction does not correct for DAC
errors. In practice, "thermometer" or
"fully-decoded" DACs using one current
switch per level (63 switches in the case
ofa 6-bit DAC) are often used instead
of a "binary" DAC to ensure excellent
differential and integral linearity and
minimum switching transients.

The second SHA delays the held output
of the first SHA while the first-stage
conversion occurs, thereby maximizing
throughput. The third SHA serves to
deglitch the residue output signal,
thereby allowing a full conversion cycle
for the 7-bit ADC to make its decision
(the 6 and 7-bit ADCs in the AD9042
are bit-serial MagAmp ADCs which
require more settling time than a flash
converter).
This multi-stage conversion technique
is sometimes referred to as "pipelining."
Addi tional shift registers in series with
the digital outputs of the first-stage
ADC ensure that its output is ultimately time-aligned with the last 7 bits
from the second ADC when their outputs are combined in the error correction logic. A pipelined ADC therefore

4-37

HIGH SPEED DESIGN TECHNIQUES

has a specified number of clock cycles of
latency, or pipeline delay associated
with the output data. The leading edge
of the sampling clock (for sample N) is
used to clock the output register, but
the data which appears as a result of
that clock edge corresponds to sample N
- L, where L is the number of clock
cycles of latency. In the case of the
AD9042, there are two clock cycles of
latency. Key specifications for the
AD9042 are shown in Figure 4.39.
The error correction scheme described
above is designed to correct for errors
made in the first conversion. Internal
ADC gain, offset, and linearity errors
are corrected as long as the residue
signal fall within the range of the
second-stage ADC. These errors will not
affect the linearity of the overall ADC
transfer characteristic. Errors made in
the fmal conversion, however, do translate directly as errors in the overall
transfer function. Also, linearity errors
or gain errors either in the DAC or the
residue amplifier will not be corrected
and will show up as nonlinearities or

4 - 38

non-monotonic behavior in the overall
ADC transfer function.
So far, we have considered only
two-stage subranging ADCs, as these
are easiest to analyze. There is no
reason to stop at two stages, however.
Three-pass and four-pass sub ranging
pipelined ADCs are quite common, and
can be made in many different ways,
usually with digital error correction.
A simplified block diagram of the
AD9220 12-bit, 10MSPS single-supply,
250mW CMOS ADC is shown in Figure
4.40. The AD9221 (1.25MSPS, 60mW)
and the AD9223 (3MSPS, 100mW)
ADCs use the identical architecture but
operate at lower power and lower
sam pIing rates. This is a four-stage
pipeIined architecture with an additional bit in the second, third, and
fourth stage for error correction. Because of the pipelined architecture,
these ADCs have a 3 clock-cycle latency
(see Figure 4.41). Key specifications for
the AD9220/922119223 are given in
Figure 4.42.

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

AD9042 12-BIT, 41MSPS ADC KEY SPECIFICATIONS

=+2.4V

•

Input Range: 1V peak-to-peak, Vcm

•

Input Impedance: 2500 to V cm

•

Effective Input Noise: 0.33LSBs rms

•

SFDR at 20MHz Input: BOdB minimum

•

SINAD (S/N+D) at 20MHz Input

•

Digital Outputs: TTL Compatible

•

Power Supply: Single +5V

•

Power Dissipation: 595mW

•

Fabricated on High Speed Dielectrically Isolated
Complementary Bipolar Process

=67dB

•

Figure 4.39

AD9220/9221/9223 12-BIT PIPELINED CMOS ADC
ANALOGi------.
INPUT
SHA

SHA
2

1

5·81T 5·81T
ADC DAC
5

SHA

+

+

3

4·BIT 4·BIT
ADC DAC

3-BIT 3·BIT
ADC DAC

4

3

3·81T
ADC
3

BUFFER REGISTERS AND
ERROR CORRECTION LOGIC
12

OUTPUT REGISTERS
12

Figure 4.40
4-39

HIGH SPEED DESIGN TECHNIQUES

LATENCY (PIPELINE DELAY)
OF AD9220/9221/9223 ADC
ANALOG

INPUT

SAMPUNG
CLOCK

OUTPUT
DATA

f

N+1

N+2

f

f
DATA N·2

DATA N-3

N+3

f
DATA N-1

Figure 4.41

AD9220, AD9221, AD9223
CMOS 12-81T ADCs KEY SPECIFICATIONS
•

Family Members:
AD9221 (1.25MSPS), AD9223 (3MSPS), AD9220 (10MSPS)

•

Power Dissipation: 60, 100, 250mW, Respectively

•

FPBW: 25, 40, 60MHz, Respectively

•

Effective Input Noise: 0.1 lSB rms (Span = 5V)

•

SINAD: 71dB

•

SFDR: 88dBc

•

On-Chip Reference

•

Differential Non-Linearity: 0.3lSB

•

Single +5V Supply

•

28-Pin SOIC Package

Figure 4.42
4 -40

DATA N

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

Bit-Per-Stage (Serial, or Ripple) ADes
Various architectures exist for performing AID conversion using one stage per
bit. In fact, a multistage sub ranging
ADC with one bit per stage and no
error correction is one form. Figure 4.43
shows the overall concept. The SHA
holds the input signal constant during

the conversion cycle. There are N
stages, each of which have a bit output
and a residue output. The residue
output of one stage is the input to the
next. The last bit is detected with a
single comparator as shown.

BIT-PER-STAGE, SERIAL, OR RIPPLE ADC

ANALOG
INPUT
SHA

STAGE

R1

STAGE

2

1

BIT1
MSB

R2

STAGE
N-1

BIT N-1

BIT2

BITN
LSB

DECODE LOGIC AND OUTPUT REGISTERS

N

Figure 4.43

The basic stage for performing a single
binary bit conversion is shown in Figure 4.44. It consists of a gain-of-two
amplifier, a comparator, and a 1-bit
DAC. The comparator detects the zerocrossing of the input and is the binary

bit output for that stage. The comparator also switches a 1-bit DAC whose
output is summed with the output of
the gain-of-two amplifier. The resulting
residue output is then applied to the
next stage.

4-41

HIGH SPEED DESIGN TECHNIQUES

SINGLE·STAGE OF BINARY ADC

SWITCH POSITION
SHOWN FOR
NEGATIVE INPUT

BIT OUTPUT
(BINARY CODE)

Figure 4.44

A simplified 3-bit serial-binary ADC is
shown in Figure 4.45, and the residue
outputs are shown in Figure 4.46. Each
residue output signal has
discontinuities which correspond to the
point where the comparator changes
state and causes the DAC to switch.
The fundamental problem with this
architecture is the discontinuity in the
residue output waveforms. Adequate
settling time must be allowed for these
transients to propagate through all the
stages and settle at the final comparator input. The prospects of m~king this
architecture operate at hig1,l speed are
therefore dismal.
A much better bit-per-stage architecture was developed by F.D. Waldhauer

4 -42

(Reference 7) based on absolute value
amplifiers (magnitude amplifiers, or
simply MagAmpsTM). This scheme has
often been referred to as serial-Gray
(since the output coding is in Gray
code), or folding converter (References
8, 9, 10). The basic stage is shown
functionally in Figure 4.47. The comparator detects the polarity of the input
signal and provides the Gray bit output
for the stage. It also determines
whether the overall stage gain is +2 or
-2. The reference voltage VR is
summed with the switch output to
generate the residue signal which is
applied to the next stage. The transfer
function for the folding stage is also
shown in Figure 4.47.

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

3-BIT SERIAL ADC WITH BINARY OUTPUT

ANALOG
INPUT

R1
SHA

R2

STAGE

STAGE

1

2

81T1

81T2

OUTPUT REGISTER

3

Figure 4.45

INPUT AND RESIDUE WAVEFORMS OF
3-BIT BINARY RIPPLE ADC
INPUT

R1

R2

.VR
BINARY
CODE

000

1 001

010

I

011 1 100

101

1110

111

1

Figure 4.46
4-43

HIGH SPEED DESIGN TECHNIQUES

MagAmp STAGE FUNCTIONAL EQUIVALENT CIRCUIT
INPUT

RESIDUE

I

I
I
I

I
: SWITCH POSITION
SHOWN FOR
NEGATIVE INPUT
RESIDUE

BIT OUTPUT
(BINARY CODE)

Figure 4.47

A 3-bit MagAmp folding ADe is shown
in Figure 4.48, and the cOITesponding
residue waveforms in Figure 4.49.

Notice that there is no abrupt transition in any of the folding stage output
waveforms.

3-BIT MagAmp ™ (FOLDING) ADC BLOCK DIAGRAM
ANALOG
INPUT
SHA

I-------i

MAGAMP

1------1

MAGAMP

1

BIT 1

1-------1

2

BIT 2

GRAY CODE REGISTER

3
GRAY-TO-BINARY CONVERTER

3
OUTPUT REGISTER

3

Figure 4.48
4 -44

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

INPUT AND RESIDUE WAVEFORMS
FOR 3-BIT MagAmp ADC
INPUT

R1

R2

.VR

GRAY
CODE

000

I 001

011

010

I

110

111 1101

100

I

Figure 4.49

The key to operating this architecture
at high speeds is the folding stage.
Early designs (see References 7, 8, 9)
used discrete op amps with diodes
inside the feedback loop to generate the
folding transfer function. Modern Ie
circuit designs implement the transfer
function using current-steering openloop gain techniques which can be made
to operate much faster. Fully differential stages (including the SHA) also
provide speed, lower distortion, and
yield 8-bit accurate folding stages with
no requirement for thin film resistor
laser trimming.
An example ofa fully differential gainof-two MagAmp folding stage is shown
in Figure 4.50 (see References 11, 12,
13). The differential input signal is
applied to the degenerated-emitter
differential pair Ql,Q2 and the comparator. The differential input voltage

is converted into a differential current
which flows in the collectors ofQl, Q2.
If +IN is greater than -IN, cascodeconnected transistors Q3, Q6 are on,
and Q4, Q6 are off. The differential
signal currents therefore flow through
the collectors of Q3, Q6 into levelshifting transistors Q7, Q8 and into the
output load resistors, developing the
differential output voltage between
+OUT and -OUT. The overall differential voltage gain of the circuit is two.
If +IN is less than -IN (negative differential input voltage), the comparator
changes stage and turns Q4, Q5 on and
Q3, Q6 off. The differential signal
currents flow from Q5 to Q7 and from
Q4 to Q8, thereby maintaining the
same relative polarity at the differential output as for a positive differential
input voltage. The required offset
voltage is developed by adding a cur4-45

HIGH SPEED DESIGN TECHNIQUES

rent IOFF to the emitter current ofQ7
and subtracting it from the emitter
current of Q8.

shown in Figure 4.51. The first five bits
(Gray code) are derived from five differential MagAmp stages. The differential
residue output of the fifth MagAmp
stage drives a 3-bit flash converter,
rather than a single comparator. The
Gray-code output of the five MagAmps
and the binary-code output of the 3-bit
flash are latched, all converted into
binary, and latched again in the output
data register. Key specifications for the
AD9059 are shown in Figure 4.52.

The differential residue output voltage
of the stage drives the next stage input,
and the comparator output represents
the Gray code output for the stage.
The MagAmp architecture can be
extended to sampling rates previously
dominated by flash converters. The
AD9059 8-bit, 60MSPS dual ADC is

CIRCUIT DETAILS OF MagAmp STAGE
~----------------------------------------~~+5V

+OUT

i+

t

-OUT

GRAY

R

R

Figure 4.50

4 -46

R

HIGH SPEED SAMPLING AND HIGH SPEED ADCs

AD9059 DUAL 8.BIT, 60MSPS ADC FUNCTIONAL DIAGRAM
ANALOG
INPUT

SHA

MAGAMP

MAGAMP

MAGAMP

MAGAMP

MAGAMP

1

2

3

4

5

3-BIT
FLASH
ACC

BIT

1
/ [ GRAY
DIFFERENTIAL
OUTPUTS ON
BITS 1 - 5

REGISTER

8
GRAY-TO-BINARY CONVERTER

8
OUTPUT REGISTER

8

Figure 4.51

AD9059 DUAL 8-BIT, 60MSPS ADC
KEY SPECIFICATIONS
•

Input Range: 1V p-p, Vcrn = +2.5V

•

Input Impedance: 200kQ

•

ENOB: 7.3 @ 10.3MHz Input

•

On-Chip Reference

•

Power Supply: Single +5V Supply (+5 or +3V Digital)

•

Power Dissipation: 375mW (Power Down: 10mW)

•

Package: 28-lead SSOP

•

Ideal for Quadrature Demodulation in DBS
Set-Top Boxes

II 5pF

Figure 4.52
4-47

HIGH SPEED DESIGN TECHNIQUES

REFERENCES
1.

Active and Passive Electrical Wave Filter Catalog, Vol. 34, TTE,
Incorporated, 2251 Barry Avenue, Los Angeles, CA 90064.

2.

W. R. Bennett, "Spectra of Quantized Signals", Bell System Technical
Journal, No. 27, July 1948, pp. 446-472.

3.

Steve Ruscak and Larry Singer, Using Histogram Techniques to Measure AI
D Converter Noise, Analog Dialogue, Vol. 29-2, 1995.

4.

M.J. Tant, The White Noise Book, Marconi Instruments, July 1974.

5.

G.A. Gray and G.W. Zeoli, Quantization and Saturation Noise due to AID
Conversion, IEEE Trans. Aerospace and Electronic
Systems, Jan. 1971, pp. 222-223.

6.

Chuck Lane, A lO-bit 60MSPS FlashADC, Proceedings of the 1989
Bipolar Circuits and Technology Meeting, IEEE Catalog No.
89CH2771-4, September 1989, pp. 44-47.

7.

F.D. Waldhauer, Analog to Digital Converter, U.S. Patent 3-187-325,1965.

8.

J.O. Edson and H.H. Henning, Broadband Codecs for an Experimental
224Mb Is PCM Terminal, Bell System Technical Journal, 44,
November 1965, pp. 1887-1940.

9.

J.S. Mayo, Experimental 224Mb/s PCM Terminals, Bell System
Technical Journal, 44, November 1965, pp. 1813-1941.

10.

Hermann Schmid, Electronic AnaloglDigital Conversions, Van
Nostrand Reinhold Company, New York, 1970.

11.

Carl Moreland, An 8-bit l50MSPS Serial ADC, 1995 ISSCC Digest of
Technical Papers, Vol. 38, p. 272.

12.

Roy Gosser and Frank Murden, A l2-bit 50MSPS Two-Stage AID
Converter, 1995 ISSCC Digest of Technical Papers, p. 278.

13.

Carl Moreland, An Analog-to-Digital Converter Using SerialRipple Architecture, Masters' Thesis, Florida State University
College of Engineering, Department of Electrical Engineering, 1995.

14.

Practical Analog Design Techniques, Analog Devices, 1995, Chapter
4,5, and 8.

15.

Linear Design Seminar, Analog Devices, 1995, Chapter 4, 5.

16.

System Applications Guide, Analog Devices, 1993, Chapter 12, 13,15,16.

4 -48

HIGH SPEED SAMPLING AND HIGH SPEED

ADes

17.

Amplifier Applications Guide, Analog Devices, 1992, Chapter 7.

18.

Walt Kester, Drive Circuitry is Critical to High-Speed Sampling ADCs,
Electronic Design Special Analog Issue, Nov. 7, 1994, pp. 43-50.

19.

Walt Kester, Basic Characteristics Distinguish Sampling AID Converters,
EDN, Sept. 3, 1992, pp. 135-144.

20.

Walt Kester, Peripheral Circuits Can Make or Break Sampling ADC
Systems, EDN, Oct. 1, 1992, pp. 97-105.

21.

Walt Kester, Layout, Grounding, and Filtering Complete Sampling
ADC System, EDN, Oct. 15, 1992, pp. 127-134.

22.

Robert A Witte, Distortion Measurements Using a Spectrum Analyzer,
RF Design, September, 1992, pp. 75-84.

23.

Walt Kester, Confused About Amplifier Distortion Specs?, Analog
Dialogue, 27-1, 1993, pp. 27-29.

24.

System Applications Guide, Analog Devices, 1993, Chapter 16.

25.

Frederick J. Harris, On the Use of Windows for Harmonic Analysis
with the Discrete Fourier Transform, IEEE Proceedings, Vol. 66, No.1,
Jan. 1978, pp. 51-83.

26.

Joey Doernberg, Hae-Seung Lee, David A. Hodges, Full Speed Testing
ofAI D Converters, IEEE Journal of Solid State Circuits, Vol. SC-19,
No.6, Dec. 1984, pp. 820-827.

27.

Brendan Coleman, Pat Meehan, John Reidy and Pat Weeks, Coherent
Sampling Helps When Specifying DSP AID Converters, EDN, October 15,
1987, pp. 145-152.

28.

Robert W. Ramierez, The FFT: Fundamentals and Concepts,
Prentice-Hall, 1985.

29.

R. B. Blackman and J. W. Tukey, The Measurement of Power
Spectra, Dover Publications, New York, 1958.

30.

James J. Colotti, Digital Dynamic Analysis ofA I D Conversion
Systems Through Evaluation Software Based on FFT I DFT Analysis,
RF Expo East 1987 Proceedings, Cardiff Publishing Co., pp. 245-272.

31.

HP Journal, Nov. 1982, Vol. 33, No. 11.

32.

HP Product Note 5180A-2.

33.

HP Journal, April 1988, Vol. 39, No.2.
4-49

HIGH SPEED DESIGN TECHNIQUES

34.

HP Journal, June 1988, Vol. 39, No.3.

35.

Dan Sheingold, Editor, Analog-to-Digital Conversion Handbook,
Third Edition, Prentice-Hall, 1986.

36.

Lawrence Rabiner and Bernard Gold, Theory and Application of
Digital Signal Processing, Prentice-Hall, 1975.

37.

Matthew Mahoney, DSP-Based Testing of Analog and Mixed-Signal
Circuits, IEEE Computer Society Press, Washington, D.C., 1987.

38.

IEEE Trial-Use Standard for Digitizing Waveform Recorders,
Np. 1057-1988.

39.

Richard J. Higgins, Digital Signal Processing in VSLI, Prentice-Hall,
1990.

40.

M. S. Ghausi and K. R. Laker, Modern Filter Design: Active Re and
Switched Capacitors, Prentice Hall, 1981.

41.

Mathcad™ 4.0 software package available from MathSoft, Inc.,
201 Broadway, Cambridge MA, 02139.

42.

Howard E. Hilton, A 10MHz Analog-to-Digital Converter with 110dB
Linearity, H.P. Journal, October 1993, pp. 105-112.

4 - 50

SECTION 5
HIGH SPEED ADC APPLICATIONS
•

Driving ADC Inputs for Low Distortion and Wide
Dynamic Range

•

Applications of High Speed ADCs in CCD Imaging

•

High Speed ADC Applications in Digital Receivers

HIGH SPEED DESIGN TECHNIQUES

HIGH SPEED

ADC APPLICATIONS

SECTION 5
HIGH SPEED ADC APPLICATIONS
Walt Kester, Brad Brannon, Paul Hendricks
DRIVING ADC INPUTS FOR

Low DISTORTION AND

WIDE DYNAMIC RANGE
In order to achieve wide dynamic range
in high speed ADC applications, careful
attention must be given to the analog
interface. Many ADCs are designed so
that analog signals can be interfaced
directly to their inputs without the
necessity of a drive amplifier. This is
especially true in ADCs such as the
AD9220/21123 family and the AD9042,
where even a low distortion drive
amplifier may result in some degradation in AC performance. If a buffer
amplifier is required, it must be carefully.selected so that its distortion and
noise performance is better than that of
theADC.
Single-supply ADCs generally yield
optimum AC performance when the
common-mode input voltage is centered
between the supply rails (although the
optimum common-mode voltage may be
skewed slightly in either direction
about this point depending upon the
particular design). This also eases the
drive requirement on the input buffer
amplifier (if required) since even "railto-rail" output op amps give best distortion performance if their output is
centered about mid-supply, and the
peak signals are kept at least 1V from
either rail.
Typical high speed single-supply ADC
peak-to-peak input voltage ranges may
vary from about O.5V to 5V, but in most

cases, lV to 2V peak-to-peak represents
the optimum tradeoff between noise
and distortion performance.
In single-supply applications requiring
DC coupling, careful attention must be
given to the input and output commonmode range of the driving amplifier.
Level shifting is often required in order
to center a ground-referenced signal
within the allowable common-mode
input range of the ADC.
Small RF transformers are quite useful
in AC coupled applications, especially if
the ADC has differential inputs. Significant improvement in even-order distortion products and common-mode noise
rejection may be realized, depending
upon the characteristics of the ADC.
An understanding of the input structure of the ADC is therefore necessary
in order to properly design the analog
interface circuitry. ADCs designed on
CMOS processes typically connect the
sample-and-hold switches directly to
the analog input, thereby generating
transient current pulses. These transients may significantly degrade performance if the settling time of the op amp
is not sufficiently fast. On the other
hand, ADCs designed on bipolar processes may present a relatively benign
load to the drive amplifier with minimal transient currents.

5-1

HIGH SPEED DESIGN TECHNIQUES

The data sheet for the ADC is the
prime source an engineer should use in
designing the interface circuits. It
should contain recommended interface

circuits and spell out relevant tradeoffs.
However, no data sheet can substitute
for a fundamental understanding of
what's inside the ADe.

HIGH SPEED ADC INPUT CONSIDERATIONS
•

Selection of Drive Amplifier (Only if Needed!)

•

Single Supply Implications

•

Input Range (Span): Typically 1V to 2V peak-to-peak
for best distortion I noise tradeoff

•

Input Common-Mode Range:
Vs I 2 (Nominally) for Single Supply ADCs

•

Differential vs. Single-Ended

•

AC Coupling Using Transformers

•

Input Transient Currents
Figure 5.1

Switched-Capacitor Input ADCs
The AD9220/21123-series of ADCs are
excellent examples of the progress that
has been made in utilizing low-cost
CMOS processes to achieve a high level
of performance. A functional block
diagram is shown in Figure 5.2. This
family of ADCs offers sampling rates of
1.25MSPS (AD9221), 3MSPS
(AD9223), and 10MSPS (AD9220) at

5-2

power dissipations of60, 100, and
250mW respectively. Key specifications
for the family of ADCs are given in
Figure 5.3. The devices contain an onchip reference voltage which allows the
full scale span to be set at 2V or 5V
peak-to-peak (full scale spans between
2V and 5V can be set by adding two
external gain setting resistors).

HIGH SPEED

ADC APPLICATIONS

AD922X-SERIES ADC FUNCTIONAL DIAGRAM
ClK

AVDD

DVDD

VINA
VINB

CAPT
CAPB
12
VREF

OTR

OUTPUT BUFFERS

SENSE

BIT1
(MSB)

1V

AD9221 123/20
REFCOM

AVSS

DVSS

BIT12
(lSB)
CMl

Figure 5.2

AD9220, AD9221, AD9223
CMOS 12-BIT ADCs KEY SPECIFICATIONS
•

Family Members:
AD9221 (1.2SMSPS), AD9223 (3MSPS), AD9220 (10MSPS)

•

Power Dissipation: 60, 100, 2S0mW, Respectively

•

FPBW: 2S, 40, 60MHz, Respectively

•

Effective Input Noise: 0.1 LSB rms (Span = SV)

•

SINAD: 71dB

•

SFDR: 88dBc

•

On-Chip Reference

•

Differential Non-Linearity: 0.3LSB

•

Single +SV Supply

•

28-Pin SOIC Package
Figure S.3
5-3

HIGH SPEED DESIGN TECHNIQUES

The input circuit of the AD9220/21/23series ofCM08 ADCs contains the
differential sample-and-hold as shown
in Figure 5.4. The switches are shown
in the track mode. They open and close
at the sampling frequency. The 16pF
capacitors represent the effective capacitance of switches 81 and 82 plus
the stray input capacitance. The Cs
capacitors (4pF) are the sampling
capacitors, and the eH capacitors are
the hold capacitors. Although the input
circuit is completely differential, the
ADC can be driven either single-ended
or differential. Optimum 8FDR, however, is obtained using a differential
transformer drive.
In the track mode, the differential input
voltage is applied to the Cs capacitors.
When the circuit enters the hold mode,
the voltage across the sampling capaci-

tors is transferred to the CH hold
capacitors and buffered by the amplifier
A (The switches are controlled by the
appropriate phases of the sampling
clock). When the 8IlA returns to the
track mode, the input source must
charge or discharge the voltage stored
on Cs to the new input voltage. This
action of charging and discharging Cs ,
averaged over a period of time and for a
given sampling frequency fs, makes the
input impedance appear to have a
benign resistive component. However, if
this action is analyzed within a sampling period (lIfs )' the input impedance
is dynamic, and hence certain precautions on the input drive source should
be observed.
The resistive component to the input
impedance can be computed by calculating the average charge that is drawn

SIMPLIFIED INPUT CIRCUIT OF AD922X ADC FAMILY

V 1 1 6 PF
Cp

o

I

S1

0--0--1----1
S3!

-

52

t-----..-i

?

O-----I*----..,O--O---.iJ.a----i

"l>-----4J-- -

-

-

-

~-____t - - - -

-

-

--

1 - -___-1

T 16pF
V
Cp

C~
4pF

SWITCHES SHOWN IN TRACK MODE

Figure 5.4
5-4

-

HIGH SPEED

ADC APPLICATIONS

AD922X ADC INPUT VOLTAGE RANGE OPTIONS
SINGLE-ENDED INPUT
Input Signal Range
(Volts)
o to +2
o to +5
+1.5 to +3.5

Common-Mode Voltage
(Volts)
+1
+2.5
+2.5

Peak-to-Peak Signal
(Volts)
2
5
2

DIFFERENTIAL INPUT
Input Signal Range
(Volts)
+2 to +3
+1.25 to +3.75

Peak-to-Peak Signal
Differential (Volts)
2
5

Common-Mode Voltage
(Volts)
+2.5
+2.5

Figure 5.5

AD9220 THO VS. INPUT FREQUENCY: SINGLE-ENDED DRIVE
2V p-p INPUT, Vcm +1V AND Vcm +2.5V, fs 10MSPS

=

=

=

50

THD
(d8c)
60

70

80

90
0.1

0.2

0.5

1

2

5

10

INPUT FREQUENCY (MHz)

Figure 5.6
5-5

HIGH SPEED DESIGN TECHNIQUES

by CH from the input drive source. It
ca~. be shown that if Cs is allowed to
fully charge to the input voltage before
switches 81 and S2 are opened that the
average current into the input is the
same as if there were a resistor equal to
1/( Csfs) connected between the inputs.
Since Cs is only a few picofarads, this
resistive component is typically greater
than several k.Q for an fs = 10M8PS.
If one considers the SHA's input impedance over a sampling period, it appears
as a dynamic load to the input drive
source. When the SHA returns to the
track mode, the input source should
ideally provide the charging current
through the Ron of switches S1 and S2
in an exponential manner. The requirement of exponential charging means
that the source impedance should be
both low and resistive up to and beyond
the sampling frequency.

The output impedance of an op amp can
be modeled as a series inductor and
resistor. When a capacitive load is
switched onto the output of the op amp,
the output will momentarily change
due to its effective high frequency
output impedance. As the output recovers, ringing may occur. To remedy this
situation, a series resistor can be inserted between the op amp and the
SIlA input. The optimum value of this
resistor is dependent on several factors
including the sampling frequency and
the op amp selected, but in most applications, a 30 to 500 resistor is optimum.
The input voltage span of the AD922Xfamily is set by pin-strap options using
the internal voltage reference (see
Figure 5.5). The common-mode voltage
can be set by either pin strap or applying the common-mode voltage to the

SINGLE-ENDED AC-COUPLED
DRIVE CIRCUIT FOR AD922X ADC
+5V

AD922X
INPUT
~.---~------~\ I\t------~

+

r----+----.e-----"

\/\/------0

Figure 5.7
5-6

VINA

VINB

HIGH SPEED

ADC APPLICATIONS

BUFFERED AC-COUPLED INPUT DRIVE
CIRCUIT FOR AD922X ADC
O.1J.lF

+5V

+5V

AD922X
1V p _p

+5V

Figure 5.8

VINB pin. Tradeoffs can be made
between noise and distortion performance. Maximum input range allowable is 5V peak-to-peak, in which case,
the common-mode input voltage must
be one-half the supply voltage, or
+2.5V. The minimum input range is 2V
peak-to-peak, in which case the common-mode input voltage can be set from
+lV to +4V. For best DC linearity and
maximum signal-to-noise ratio, the
ADC should be operated with an input
signal of 5V peak-to-peak. However, for
best high frequency noise and distortion
performance, 2V peak-to-peak with a
common-mode voltage of +2.5Vis
preferred. This is because the CMOS
FET on-resistance is a minimum at this
voltage, and the non-linearity caused
by the signal-dependence of Ron (Ron
modulation effect) is also minimal.

Figure 5.6 shows the THD performance
of the AD9220 for a 2V peak-to-peak
input signal span and common-mode
input voltage of 2.5V and 1V. The data
was taken with a single-ended drive.
Note that the performance is significantly better for Vcm = +2.5V.
A simple single-ended circuit for AC
coupling into the inputs of the AD9220family is shown in Figure 5.7. Note that
the common-mode input voltage is set
for +2.5V by the 4.99kQ resistors. The
input impedance is also balanced for
optimum distortion performance.
If the input to the ADC is coming from
a long coaxial cable run, it may be
desirable to buffer the transient currents at the ADC inputs from the cable
to prevent problems resulting from
5-7

HIGH SPEED DESIGN TECHNIQUES

reflections, especially if the cable is not
source-terminated. The circuit shown in
Figure 5.8 uses the low distortion
ADS011 op amp as a buffer which can
optionally provide signal gain. In all
cases, the feedback resistor should be
fixed at lkn for best op amp performance, since the AD8011 is a currentfeedback type. In this type of
arrangement, care must be taken to
observe the allowable input and output
range of the op amp. The AD8011 input
common-mode range (operating on a
single +5V supply) is from +1.5 to
+3.5V, and its output +1V to +4V. The
ADC should be operated with a 2V
peak-to-peak input range. The 33n
series resistor is required to isolate the
output of the ADS011 from the effective

input capacitance of the ADC. The
value was empirically determined to
yield the best high-frequency SINAD.
Direct coupling of ground-referenced
signals using a single supply requires
the use of an op amp with an acceptable
common-mode input voltage, such as
the AD8041 (input can go to 200mV
below ground). The circuit shown in
Figure 5.9 level shifts the groundreferenced bipolar input signal to a
common-mode voltage of +2.5V at the
ADe input. The common-mode bias
voltage of +2.5Vis developed directly
from an AD780 reference, and the
AD8041 common-mode voltage of
+1.25V is derived with a simple di,vider.

DIRECT·COUPLED LEVEL SHIFTER
FOR DRIVING AD922X ADC INPUT
1kQ
+5V

AD922X

VINA
+2.5V+ 1V
+1.25V
+5V
AD780
2.5V

REF.

Figure 5.9
5-8

HIGH SPEED

Transformer coupling provides the best
CMR and the lowest distortion. Figure
5.10 shows the suggested circuit. The
transformer is a Mini-Circuits RF
transformer, model #T4-6T which has
an impedance ratio of four (turns ratio
of 2). The schematic assumes that the
signal source has a 50n source impedance. The 1:4 impedance ratio requires
the 200n secondary termination for
optimum power transfer and VSWR.
The Mini-Circuits T4-6T has a 1dB
bandwidth from 100kHz to 100MHz.
The center tap of the transformer
provides a convenient means of level
shifting the input signal to the optimum common-mode voltage. The
AD922X CML pin is used to provide the
+2.5 common-mode voltage.
Transformers with other turns ratios
may also be selected to optimize the

ADC ,ApPLICATIONS

performance for a given application.
For example, a given input signal
source or amplifier may realize an
improvement in distortion performance
at reduced output power levels and
signal swings. Hence, selecting a transformer with a higher impedance ratio
(i.e. Mini-Circuits #T16-6T with a 1:16
impedance ratio, turns ratio 1:4) effectively "steps up" the signal level thus
reducing the driving requirements of
the signal source.
Note the 33n series resistors inserted
between the transformer secondary and
the ADC input. These values were
specifically selected to optimize both the
SFDR and the SNR performance of the
ADC. They also provide isolation from
transients at the ADC inputs. Transients currents are approximately equal
on the VINA and VINB inputs, so they

TRANSFORMER COUPLING INTO AD922X ADC

III

RF TRANSFORMER:
MINI·CIRCUITS T4·6T

CML

Figure 5.10
5-9

HIGH SPEED DESIGN TECHNIQUES

are isolated from the primary winding
of the transformer by the transformer's
common-mode rejection.
Transformer coupling using a commonmode voltage of +2.5V provides the
maximum SFDR when driving the
AD922X-series. By driving the ADC
differentially, even-order harmonics are
reduced compared with the singleended circuit. Figure 5.11 shows a plot
of SFDR and SNR for the transformercoupled differential drive circuit using
2V p-p and 5V p-p inputs and a common-mode voltage of +2.5V. Note that
the SFDRis greater than 80dBc for
input signals up to full scale with a
5MHz input signal.

Figure 5.11 also shows differences
between the SFDR and SNR performance for 2V p-p and 5V p-p inputs.
Note that the SNR with a 5V p-p input
is approximately 2dB to 3dB better
than that for a 2V p-p input because of
the additional dynamic range provided
by the larger input range. Also, the
SFDR performance using a 5V p-p
input is 3 to 5dB better for signals
between about -6dBFS and -36dBFS.
This improvement in SNR and SFDR
for the 5V p-p input range may be
advantageous in systems which require
more than 6dB headroom to minimize
clipping of the ADC.

AD9220 SF DR AND SNR FOR 5Vp-p AND 2Vp-p INPUT:
Vern +2.5V, 5MHz INPUT, fs 10MSPS
TRANSFORMER-COUPLED DIFFERENTIAL DRIVE

=

=

90----------~----~-----r----~
80L---~----_+-----+~__~~~~

30L-~~~---4-----+-----r----~

-40

-30

-20

INPUT AMPLITUDE - dBFS

Figure 5.11
5 -10

-10

0

HIGH SPEED

ADC APPLICATIONS

Driving Bipolar Input ADCs

Bipolar technology is typically used for
extremely high performance ADCs with
wide dynamic range and high sampling
rates such as the AD9042. The AD9042
is a state-of-the-art 12-bit, 41MSPS two
stage subranging ADC consisting of a 6bit coarse ADC and a 7-bit residue ADC
with one hit of overlap to correct for any
DNL, INL, gain or offset errors of the
coarse ADC, and offset errors in the
residue path. A block diagram is shown
in Figure 5.12 and key specifications in
Figure 5.13. A proprietary gray-code
architecture is used to implement the
two internal ADCs. The gain alignments of the coarse and residue, likewise the subtraction DAC, rely on the

statistical matching of the devices on
the process. As a result, 12-bit integral
and differential linearity is obtained
without laser trim. The internal DAC
consists of 126 interdigitated current
sources. Also on the DAC reference,
there are an additional 20
interdigitated current sources to set the
coarse gain, residue gain, and" full scale
gain. The interdigitization removes the
requirement for laser trim. The
AD9042 is fabricated on a high speed
dielectrically isolated complementary
bipolar process. The total power dissipation is only 575mW when operating
on a single +5V supply.

AD904212-BIT, 41MSPS ADC BLOCK DIAGRAM
ANALOG
INPUT ().U_- - - - I

•

SHA
1

6·BIT
DAC

6·BIT
ADC
BUFFER
REGISTER

7·BIT
ADC

/

1/7

{6
ERROR CORRECTION LOGIC

OUTPUT REGISTERS

Figure 5.12
5-11

HIGH SPEED DESIGN TECHNIQUES

AD9042 12-BIT, 41MSPS ADC KEY SPECIFICATIONS
•

Input Range: 1V peak-to-peak, Vcm = +2.4V

•

Input Impedance: 2500 to Vcm

•

Effective Input Noise: 0.33LSBs rms

•

SFDR at 20MHz Input: BOdB

•

SINAD at 20MHz Input

•

Digital Outputs: TTL Compatible

•

Power Supply: Single +5V

•

Power Dissipation: 575mW

•

Fabricated on High Speed Dielectrically Isolated
Complementary Bipolar Process

=66dB

Figure 5.13

The outstanding performance of the
AD9042 is partly due to the use of
differential techniques throughout the
device. The low distortion input amplifier converts the single-ended input
signal into a differential one. If maximum SFDR performance is desired, the
signal source should he coupled directly
into the input of the AD9042 without
using a buffer amplifier. Figure 5.14
shows a method using capacitive coupling. Transformer coupling can also he
used if desired.

architecture, and key specifications are
summarized in Figure 5.16.

The AD9050 is a 10-hit, 40MSPS single
supply ADC designed for wide dynamic
range applications such as ultrasound,
instrumentation, digital communications, and professional video. Like the
AD9042, it is fabricated on a high speed
complementary bipolar process. A block
diagram of the AD9050 (Figure 5.15)
illustrates the two-step subranging

The input circuit of the AD9050 is a
relatively benign and constant 5k.Q in
parallel with approximately 5pF. Because of its well-behaved input, the
AD9050 can be driven directly from 50,
75, or lOOn sources without the need
for a low-distortion buffer amplifier. In
nltrasound applications, it is normal to
AC couple the signal (generally be-

5 -12

The analog input circuit of the AD9050
(see Figure 5.17) is differential, but can
be driven either single-endedly or
differentially with equal performance.
The input signal range of the AD9050
is ±0.5V centered around a commonmode voltage of +3.3V, which makes
single supply op amp selection more
difficult since the amplifier has to drive
+3.SV peak signals with low distortion.

HIGH SPEED

ADC APPLICATIONS

INPUT STRUCTURE OF AD9042 ADC IS
DESIGNED TO BE DRIVEN DIRECTLY FROM 50Q
SOURCE FOR BEST SF DR
I
I

I
I

AD9042

I

I
I
I
FROM 50n
SOURCE

INPUT =

1Vp-p

I
I

250n

~:

+

+2.4V

Figure 5.14

•

AD9050 10-BIT, 40MSPS SINGLE SUPPLY ADC
ENCODE

AIN
AIN

VREFOUT

AD9050

Figure 5.15
5-13

HIGH SPEED DESIGN TECHNIQUES

AD9050 10-8IT, 40MSPS ADC KEY SPECIFICATIONS
•

10-Bits, 40MSPS, Single +5V Supply

•

Selectable Digital Supply: +5V, or +3V

•

Low Power: 300mW on BiCMOS Process

•

On-Chip SHA and +2.5V reference

•

56dB S/(N+D), 9 Effective Bits, with 10.3MHz Input Signal

•

No input transients, Input Impedance 5kO, 5pF

•

Input Range +3.3V ±O.5V Single-Ended or Differential

•

28-pin SOIC I SSOP Packages

•

Ideal for Digital Beamforming Ultrasound Systems
Figure 5.16

AD9050 SIMPLIFIED INPUT CIRCUIT
+5V

8kO

8kO
AIN(A)

0 - - - -___- - - - - t - - - - 1

AIN(B) 0 - - - - + - - - - - _ > - - - 1

161<0

INPUT RANGE:
+3.3V ± O.5V
GND

Figure 5.17
5-14

16kO

HIGH SPEED

tween 1MHz and 15MHz) into the
AD9050 differential inputs using a
wideband transformer as shown in
Figure 5.1S. The Mini-Circuits T1-1T
transformer has a 1dB bandwidth from
200kHz to SOMHz. Signal-to-noise plus

ADC APPLICATIONS

distortion (SINAD) values of 57dB (9.2
ENOB) are typical for a 10MHz input
signal. If the input signal comes directly from a 50, 75, or lOOn singleended source, capacitive coupling as
shown in Figure 5.1S can be used.

AC COUPLING INTO THE INPUT OF THE AD9050 ADC
,..--_e_-

+5V

r--e-- +5V

8ka

8ka

•••

•••

•

T1:
MINI-CIRCUITS
T1 -1T

TRANSFORMER
COUPLING

CAPACITIVE
COUPLING

Figure 5.18

If DC coupling is required, the ADS041
(zero-volt in, rail-to-rail output) op amp
can be used as a low distortion driver.
The circuit shown in Figure 5.19 level
shifts a ground-referenced video signal
to fit the +3.3V :!:O.5V input range of
the AD9050. The source is a groundreferenced 0 to +2V signal which is
series-terminated in 750. The terminaV
cm

tion resistor, RT, is chosen such that
the parallel combination of RT and R1
is 750. The ADS041 op amp is configured for a signal gain of -1. Assuming
that the video source is at zero volts,
the corresponding ADC input voltage
should be +3.SV. The common-mode
voltage, Vcm, is determined from the
following equation:

= 3.S( Rs II RT + R1 ) = 3.S(
Rs II RT + R1 + R2

3S.S + 1000
)
3S.S + 1000 + 1000

= 1.94V
5-15

HIGH SPEED DESIGN TECHNIQUES

(26mW), wide bandwidth (160MHz),
and low distortion (-69dBc at 10MHz).
It is fully specified for both ±5V,+5V,
and +3V operation. When operating on
a single +5V supply, the input commonmode range is -O.2V to +4V, and the
output swing is +0.1 V to +4.9V. Distortion performance of the entire circuit
including the ADe is better than
-60dBc for an input frequency of
10MHz and a sampling rate of
40MSPS.

The common-mode voltage, Vcm' is
derived from the common-mode voltage
at the inverting input of the AD9050.
The +3.3V is buffered by the AD820
single-supply FET-input op amp. A
divider network generates the required
+1.94V for the AD8041 , and a potentiometer provides offset adjustment
capability.
The AD8041 voltage feedback op amp
was chosen because of its low power

DC·COUPLED SINGLE·SUPPLY DRIVE CIRCUIT FOR
AD9050 10·BIT, 40MSPS ADC USING AD8041 OP AMP
+5V

R2

AD9050

3.8VT02.8V

16kn
+5V

VCM = +1.94V

:5

~

1000n

OFFSET
ADJUST

Figure 5.19

5-16

AIN(B)

8kn

+3.3V

16kn

HIGH SPEED

APPLICATIONS OF HIGH SPEED ADCs IN
Charge coupled devices (CCDs) contains
a large number of small photocells
called photo sites or pixels which are
arranged either in a single row (linear
arrays) or in a matrix (area arrays).
CCD area arrays are commonly used in
video applications, while linear arrays
are used in facsimile machines, graphics scanners, and pattern recognition
equipment.
The linear CCD array consists of a row
of image sensor elements (photosites, or
pixels) which are illuminated by light
from the object or document. During
one exposure period each photo site
acquires an amount of charge which is

ADC APPLICATIONS

CCD IMAGING

proportional to its illumination. These
photosite charge packets are subsequently switched simultaneously via
transfer gates to an analog shift register. The charge packets on this shift
register are clocked serially to a charge
detector (storage capacitor) and buffer
amplifier (source follower) which convert them into a string of photo-dependent output voltage levels (see Figure
5.20). While the charge packets from
one exposure are being clocked out to
the charge detector, another exposure is
underway. The analog shift register
typically operates at frequencies between 1 and lOMHz.

LINEAR CCO ARRAY
EXPOSURE
CLOCKS

II

PHOTO-SITES (PIXELS)

TRANSFER
CLOCKS
)

SHIFT
CLOCKS

TRANSFER GATE

RESET
LEVEL

1
)

+V

CCO
OUTPUT

ANALOG TRANSPORT
SHIFT REGISTER

SAMPLE VIDEO/
SAMPLE RESET
FETSWITCH

-V

Figure 5.20
5-17

HIGH SPEED DESIGN TECHNIQUES

The charge detector readout cycle
begins with a reset pulse which causes
a FET switch to set the output storage
capacitor to a known voltage. Switching
the FET causes capacitive feedthrough
which results in a reset glitch at the
output as shown in Figure 5.21. The
switch is then opened, isolating the
capacitor, and the charge from the last
pixel is dumped onto the capacitor
causing a voltage change. The difference between the reset voltage and the
final voltage (video level) shown in
Figure 5.21 represents the amount of
charge in the pixel. eCD charges may
be as low as 10 electrons, and a typical
eeD output sensitivity is 0.6p.V/electron. Most CeDs have a saturation
output voltage of about 1V (see Reference 1).
Since eeDs are generally fabricated on
MOS processes, they have limited
capability to perform on-chip signal
conditioning. Therefore, the eCD
output is generally processed by external conditioning circuits.'
eCD output voltages are small and
quite often buried in noise. The largest
source of noise is the thermal noise in
the resistance of the FET reset switch.
This noise may have a typical value of
100 to 300 electrons rms (approximately 60 to 180mV rms). This noise
occurs as a sample-to-sample variation
in the eeD output level and is common

5 -18

to both the reset level and the video
level for a given pixel period. A technique called correlated double sampling
(CDS) is often used to reduce the effect
of this noise. Figure 5.22 shows two
circuit implementations of the CDS
scheme. In the top circuit, the CCD
output drives both SHAs. At the end of
the reset interval, SHA1 holds the reset
voltage level. At the end of the video
interval, SHA2 holds the video level.
The SHA outputs are applied to a
difference amplifier which subtracts one
from the other. In this scheme, there is
only a short interval during which both
SHA outputs are stable, and their
difference represents /lV, so the difference amplifier must settle quickly to
the desired resolution.
Another arrangement is shown in the
bottom half of Figure 5.22, which uses
three SHAs and allows either for faster
operation or more time for the difference amplifier to settle. In this circuit,
SHA1 holds the reset level so that it
occurs simultaneously with the video
level at the input to SHA2 and SHA3.
When the video clock is applied simultaneously to SHA2 and SHA3, the
input to SHA2 is the reset level, and
the input to SHA3 the video level. This
arrangement allows the entire pixel
period (less the acquisition time of
SHA2 and SHA3) for the difference
amplifier to settle.

HIGH SPEED

ADC APPLICATIONS

CCD OUTPUT WAVEFORM
RESET

CCD
OUTPUT

iGLITCH

RESET
LEVEL

VIDEO
LEVEL
VIDEO
LEVEL

I~ PIXEL PERIOD

~

I

I

Figure 5.21

CORRELATED DOUBLE SAMPLING (CDS)
MINIMIZES SWITCHING NOISE AT OUTPUT
METHOD #1

SHA 1
CCD
OUTPUT

RESET CLOCK
VIDEO CLOCK

SHA2

SHA 1
CCD
OUTPUT

0

1
- - - - - .

RESET
CLOCK

SHA2

METHOD #2

-.1'
VIDEO
CLOCK

Figure 5.22
5-19

HIGH SPEED DESIGN TECHNIQUES

The AD9807 is a complete CCD imaging decoder and signal processor on a
single chip (see Figure 5.23). The input
of the AD9807 allows direct AC coupling of the CCD outputs and includes
all the circuitry to perform threechannel correlated double sampling
(CDS) and programmable gain adjustment (lX to 4Xin 16 increments) of the
CCD output. A 12-bit ADC quantizes
the analog signal (maximum sampling
frequency 6MSPS). After digitization,
the on-board DSP allows pixel rate
offset and gain correction. The DSP also
corrects odd/even CCD register imbal-

AD9807

ance errors. A parallel control bus
provides a simple interface to 8-bit
microcontrollers. The device operates on
a single +5V supply and dissipates
500mW. The AD9807 comes in a space
saving 64-pin plastic quad flat pack
(PQFP). By disabling the CDS, the
AD9807 is also suitable for non-CCD
applications that do not require CDS.
The AD9807 is also offered in a pincompatible lO-bit version, the AD9805,
to allow upgrade ability and simplify
design issues across different scanner
models.

ceo IMAGE DECODER AND SIGNAL PROCESSOR
OFFSET GAIN

VINR t > - - - - - - 1

OEB

DOUT<11:0>

VING

CSB

RDB
VINB rr---I------i

WRB

A1

A2

CDSCLK1

CDSCLK2

STRTLN

ADCCLK

Figure 5.23

5 -20

HIGH SPEED

ADC APPLICATIONS

HIGH SPEED ADC APPLICATIONS IN DIGITAL RECEIVERS
Introduction
Consider the analog superheterodyne
receiver invented in 1917 by Major
Edwin H. Armstrong (see Figure 5.24).
This architecture represented a significant improvement over single-stage
direct conversion (homodyne) receivers
which had previously been constructed
using tuned RF amplifiers, a single
detector, and an audio gain stage. A
significant advantage of the
superhetrodyne receiver is that it is
much easier and more economical to
have the gain and selectivity of a receiver at fixed intermediate frequencies
(IF) than to have the gain and frequency-selective circuits "tune" over a
band of frequencies.

The frequencies shown in Figure 5.24
correspond to the AMPS (Advanced
Mobile Phone Service) analog cellular
phone system currently used in the
U.S. The receiver is designed for AMPS
signals at 900MHz RF. The signal
bandwidth for the "A" or "B" carriers
serving a particular geographical area
is 12.5MHz (416 channels, each 30kHz
wide). The receiver shown uses triple
conversion, with a first IF frequency of
70MHz and a second IF of 10.7MHz,
and a third of 455kHz. The image
frequency at the receiver input is
separated from the RF carrier frequency by an amount equal to twice the
first IF frequency (illustrating the point

u.s. ADVANCED MOBILE PHONE SERVICE (AMPS)
SUPERHETRODYNE ANALOG RECEIVER
AMPS: 416 CHANNELS ("A" OR "B" CARRIER)
30kHz WIDE, FM
12.SMHz TOTAL BANDWIDTH
1 CALLER/CHANNEL

BPF

r-\

L01

L02

TUNED

FIXED

70MHz

L03
10.7MHz

FIXED

455kHz

ANALOG
DEMOD, CHANNEL 1
FILTER
30kHz

1STIF

2ND IF

•
•

Y

SAME AS ABOVE

3RDIF

I

•
•
•

CHANNE~n'"

.

30kHz

~--------------------------------------------~

Figure 5.24
5-21

HIGH SPEED DESIGN TECHNIQUES

that using relatively high first IF
frequencies makes the design of the
image rejection filter easier).

They are, however, an important part
of the receiver, and the reader should
be aware that they must be present.

The output of the third IF stage is
demodulated using analog techniques
(discriminators, envelope detectors,
synchronous detectors, etc.). In the case
of AMPS the modulation is FM. An
important point to notice about the
above scheme is that there is one receiver required per channel, and only
the antenna, prefilter, and LNA can be
shared.

Receiver design is a complicated art,
and there are many tradeoffs that can
be made between IF frequencies, singleconversion vs. double-conversion or
triple conversion, fliter cost and complexity at each stage in the receiver,
demodulation schemes, etc. There are
many excellent references on the subj ect, and the purpose of this section is
only to acquaint the design engineer
with some of the emerging architectures, especially in the application of
digital techniques in the design of
advanced communications receivers.

It should be noted that in to make the
receiver diagrams more manageable,
the interstage amplifiers are not shown.

A Receiver Using Digital Processing at Baseband
With the availability of high performance high speed ADCs and DSPs
(such as ADSP-2181 and the ADSP21062), it is now becoming common
practice to use digital techniques in at
least part of the receive and transmit
path, and various chipsets are available
from Analog Devices to perform these
functions for GSM and other cellular
standards. This is illustrated in Figure
5.25 where the output of the last IF
stage is converted into a baseband inphase (I) and quadrature (Q) signal
using a quadrature demodulator. The I
and Q signals are then digitized by two
ADCs. The DSPs then perform the
additional signal processing. The signal
can then be converted into analog
format using a DAC, or it can be processed, mixed with other signals,
upconverted, and retransmitted.
At this point, we should make it clear
that a digital receiver is not the same
thing as digital modulation. In fact, a
digital receiver will do an excellent job
of receiving an analog signal such as
AM or FM. Digital receivers can be
5-22

used to receive any type of modulation
standard including analog (AM, FM) or
digital (QPSK, QAM, FSK, GMSK,
etc.). Furthermore, since the core ofa
digital radio is its digital signal processor (DSP), the same receiver can be
used for both analog and digitally
modulated signals (simultaneously if
necessary), assuming that the RF and
IF hardware in front of the DSP is
properly designed. Since it is software
that determines the characteristics of
the radio, changing the software
changes the radio. For this reason,
digital receivers are often referred to as
software radios.
The fact that a radio is software programmable offers many benefits. A
radio manufacturer can design a generic radio in hardware. As interface
standards change (as from FM to
CDMA or TDMA), the manufacturer is
able to make timely design changes to
the radio by reprogramming the DSP.
From a user or service-providers point
of view, the software radio can be
upgraded by loading the new software

HIGH SPEED

ADC APPLICATIONS

DIGITAL RECEIVER USING
BASEBAND SAMPLING AND DIGITAL PROCESSING
LPF

ACC

455kHz

CHANNEL

CHANNEL 1

1

DSP
3RCIF

•
•
•

LPF

••

Q

•
•
•

•

~~A~~~

ACC

SAME AS ABOVE

__________________________________________

•
•

•

~ICHA~NEL

Figure 5.25

at a small cost, while retaining all of
the initial hardware investment. Additionally, the receiver can be tailored for
custom applications at very low cost,
since only software costs are involved.
A digital receiver performs the same
function as an analog one with one
difference; some of the analog functions
have been replaced with their digital
equivalent. The main difference between Figure 5.24 and Figure 5.25 is
that the FM discriminator in the analog
radio has been replaced with two ADCs
and a nsp. While this is a very simple
example, it shows the fundamental
beginnings of a digital, or software
radio.
An added benefit of using digital techniques is that some of the filtering in
the radio is now performed digitally.
This eliminates the requirement of
tight tolerances and matching for

frequency-sensitive components such as
inductors and capacitors. In addition,
since filtering is performed within the
nsp, the filter characteristics can be
implemented in software instead of
costly and sensitive SAW, ceramic, or
crystal filters. In fact, many filters can
be synthesized digitally that could
never be implemented in a strictly
analog receiver.
This simple example is only the beginning. With current technology, much
more of the receiver can be implemented in digital form. There are
numerous advantages to moving the
digital portion of the radio closer to the
antenna. In fact, placing the ADC at
the output of the RF section and performing direct RF sampling might seem
attractive, but does have some serious
drawbacks, particularly in terms of
selectivity and out-of-band (image)
rejection. However, the concept makes
5-23

HIGH SPEED DESIGN TECHNIQUES

clear one key advantage of software
radios: they are programmable and
require little or no component selection

or adjustments to attain the required
receiver performance.

Narrowband IF-Sampling Digital Receivers
A reasonable compromise in many
digital receivers is to convert the signal
to digital form at the output of the fIrst
or the second IF stage. This allows for
out-of-band signals to be filtered before
reaching the ADC. It also allows for
some automatic gain control (AGC) in
the analog stage ahead of the ADC to
reduce the possibility of in-band signals
overdriving the ADC and allows for
maximum signal gain prior to the AID
conversion. This relieves some of the
dynamic range requirements on the
ADC. Additionally, IF sampling and
digital receiver technology reduce costs
by elimination of further IF stages
(mixers, filters, and amplifiers) and
adds flexibility by the replacement of
fixed analog filter components with
programmable digital ones.

In analyzing an analog receiver design,
much of the signal gain is after the fIrSt
IF stage. This prevents front-end
overdrive due to out-of-band signals or
strong in-band signals. However, in an
IF sampling digital receiver, all of the
gain is in the front end, and great care
must be taken to prevent in-band and
out-of-band signals from saturating the
ADC, which results in excessive distortion. Therefore, a method of attenuation must be provided when large
in-band signals occur. While additional
signal gain can be obtained digitally
after the ADC, there are certain restrictions. Gain provided in the analog
domain improves the SNR of the signal
and only reduces the performance to
the degree that the noise figure (NF)
degrades noise performance.

NARROWBAND IF SAMPLING GSM DIGITAL RECEIVER

200kHz WIDE CHANNELS
16 CALLERS/CHANNEL
70MHz
DIGITAL
DEMODULAll0N

AND

1ST IF

CHANNEL
DSP

1

DECIMAll0N

FILTER

•
•

•

••
•

•
•
•

~~_______________SA__M_E_A_S_A~B~O=V=E~____________~I CH~NEL
Figure 5.26

5-24

HIGH SPEED

ADC APPLICATIONS

track-and-hold, digital RSSI outputs,
references, and control circuitry. The
device accepts two inputs (for use with
diversity antennas) which are multiplexed to the single ADC.

Figure 5.26 shows a detailed IF sampling digital receiver for the GSM
system. The receiver has RF gain,
automatic gain control (AGC), a high
performance ADC, digital demodulator!
filter, and a DSP.

The AD6600 provides greater than
92dB dynamic range from the ADC and
the auto gain-ranging/RSSI circuits.
The gain range is 36dB in 6dB increments (controlled by a 3-bit word from
the RSSI circuit). This sets the smallest
input range at 31mV peak-to-peak, and
the largest at 2V peak-to-peak. SFDR is
70dBc @ 100MHz and 53dBc @
250MHz. Channel isolation is 70dB @
100MHz and 60dB @ 250MHz. The
SNR performance of the AD6600 is
shown in Figure 5.29. The dynamic
range of the AD6600 is greater than
the minimum GSM specification of
91dB.

The heart of the system is the AD6600
dual channel, gain ranging 11-bit,
20MSPS ADC with RSSI (Received
Signal Strength Indicator) and the
AD6620 dual channel decimating
receiver. A detailed block diagram of
the AD6600 is shown in Figure 5.27
and key specifications in Figure 5.28.
The AD6600 is a mixed signal chip that
directly samples narrow band signals at
IF frequencies up to 250MHz. The
device includes an 11-bit, 20MSPS
ADC, input attenuators, automatic gain
ranging circuitry, a 450MHz bandwidth

AD6600 DUAL CHANNEL GAIN RANGING ADC WITH
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)

EXTERNAL
FILTER

IF
A

NBn-----------~

MUX

PEAK
DETECTOR

11·BIT
ADC

IF

8
RSSI
CONTROL
3

Figure 5.27
5-25

HIGH SPEED DESIGN TECHNIQUES

AD6600 KEY SPECIFICATIONS
•

Dual Input, 11-bit, 20MSPS ADC Plus 3-bits RSSI

•

Dynamic Range> 100dB
•

11-bit ADC

~

62dB

•

3-bits RSSI

~

30dB (5 levels, 6dB I level)

•

Process Gain

~

12dB (6.5MSPS Sampling, 30kHz channel)

•

On-Chip Reference and Timing

•

Single +5V Supply, 400mW

•

44-pin TQFP Package

•

Optimum Design for Narrowband Digital Receivers
with IF Frequencies to 250M Hz
Figure 5.28

AD6600 INPUT VS. SNR
,~~

Input voltage range & RSSI
for~6600inputranges

RSSI=1 01, Vin>=.5Vpp

.. "
.. "".10'
. ,- ~ i-""'"
-'III!!.

".

RSSI=100, .25Vpp<=Vin<.5Vpp

.".

RSSI=011, .125Vpp<=Vin<.25Vpp

.;
".

RSSI=010, .0625Vpp<=Vin<.125Vpp

,

".

.".

RSSI=OOO, Vin<.03125Vpp

"

-2

-8
-14

.....

~

RSSI=001, .03125Vpp<=Vin<.0625Vpp

"".

"".""

L

~

+10

-20

l...--' ~""

.. ,. ~I-'

-26

,.~"

............. 1-'

,. "".""
"".

l..--'

,. ~Io'

,..

~

."..

l..--'

"".

Ain

."..

,.."."

i.-"'I'

-83 10'

o

-88
4

8

12

16

20

24

28

32

36

SNR

Figure 5.29
5-26

40

44

48

52

56

60

HIGH SPEED

ADC APPLICATIONS

The analog input to the AD6600 consists of two parallel attenuator stages
followed by an output selection multiplexer. The attenuation levels can be
set either by the on-chip automatic
RSSI circuit (synchronous peak detector) or can be set digitally with external
logic. The ADC TIH input can also be
accessed directly by by-passing the
front-end attenuators.

the previous one. Each comparator has
6dB of built-in hysteresis to eliminate
level uncertainty at the threshold
points. Once one of the comparators is
tripped, it stays in that state until it is
reset by the negative-going edge of the
sampling clock. The 5 comparator
outputs are decoded into a 3-bit word
that is used to select the proper input
attenuation.

An external analog filter is required
between the attenuator output and the
track-and-hold input of the ADC section. This filter may be either a lowpass
or a bandpass depending on the system
architecture. Since the input bandwidth
of the ADC is 450MHz, the filter minimizes the wideband noise entering the
track-and-hold. The bandwidth of the
filter should be set to allow sufficient
settling time (1/2 the sampling period)
during the RSSI peak detection period.

The RSSI follows the IF signal one
clock cycle before the conversion is
made. During this time period, the
RSSI looks for the signal peaks. Prior to
digitization, the RSSI word selects the
correct attenuator factor to prevent the
ADC from over-ranging on the following
conversion cycle. The peak signal is set
6dB below the full scale range of the 11bit ADC. The RSSI word can be read
via the RSSI pins. The II-bit ADC
output functions as the mantissa, while
the RSSI word is the exponent, and the
combination forms a floating point
number.

The ADC is based on the high dynamic
range AD9042 architecture covered
previously. The ADC input is designed
to take advantage of the excellent
small-signal linearity of the track-andhold. Therefore, the full scale input to
the ADC section is only 50mV peak-topeak. The track-and-hold is followed by
a gain block with a 6dB gain-select to
increase the signal level for digitization
by the II-bit ADC. This amplifier only
requires enough bandwidth to accurately settle to the next value during
the sampling period (77ns for fs =
13MSPS). Because of its reduced bandwidth, any high frequency track-andhold feed through is also minimized.
The RSSI peak detector function consists of a bank of 5 high speed comparators with separate reference inputs.
Each reference input is 6dB lower than

The AD6600 is ideal for use in a GSM
narrowband basestation. Figure 5.30
shows a block diagram of the fundamental receiver. Two separate antennas and RF sections are used (this is
often called diversity) to reduce the
signal strength variations due to
multi path effects. The IF output (approximately 70MHz) of each channel is
digitized by the AD6600 at a sampling
rate of6.5MSPS (one-half the master
GSM clock frequency of 13MHz). The
two antennas need only be separated
by a few feet to provide the required
signal strength diversity (the wavelength of a 900MHz signal is about 1
foot). The DSP portion of the receiver
selects the channel which has the
largest signal amplitude.

5-27

HIGH SPEED DESIGN TECHNIQUES

The signal is then passed through a
digital filter (part of the AD6620) which
removes all frequency components
above 200kHz, including the quantization noise which falls in the region
between 200kHz and 3.25MHz (the
Nyquist frequency) as shown in Figure
5.32. The resultant increase in SNR is
12dB (processing gain). There is now no
information contained in the signal
above 200kHz, and the output data
rate can be reduced (decimated) from
6.5MSPS to 406.25kSPS, a data rate
which the nsp can handle. The data
corresponding to the 200kHz channel is
transmitted to the nsp over a simple 3wire serial interface. The nsp performs
such functions as channel equalization,
decoding, and spectral shaping.

The bandwidth of a single GSM channel is 200kHz, and each channel can
handle up to 8 simultaneous callers for
full-rate systems and 16 simultaneous
callers for the newer one-half-rate
systems. A typical basestation may be
required to handle 50 to 60 simultaneous callers, thereby requiring 4
separate signal processing channels
(assuming a one-half-rate system).
The IF frequency is chosen to be
69.875MHz, thus centering the 200kHz
signal in the 22nd Nyquist zone (see
Figure 5.31). The dual channel digital
decimating receiver (AD6620) reverses
the frequency sense of the signal and
shifts it down to baseband.
We now have a 200kHz baseband
signal (generated by undersampling)
which is being oversampled by a factor
of approximately 16 .

NARROWBAND GSM BASESTATION WITH DIVERSITY

69.875MHz

DUAL-CHANNEL DUAL-CHANNEL
ADC,RSSI
DEMODULATION
AND GAIN
AND
RANGING
DECIMATION

IF

r\
1ST IF

B

LO

AD6600

TUNED

=

fs 6.5MSPS
PER CHANNEL

IF

DSP

A

r\

•• ••
••

AD6620

ADSP·2181,
ADSP·21 062
CHANNEL
1

•
•
•

Iyi.---_
U
_----J"
SAME AS ABOVE

Figure 5.30
5-28

CHANNEL

ADO APPLICATIONS

HIGH SPEED

NARROWBAND GSM RECEIVER BANDPASS SAMPLING
OF A 200kHz CHANNEL AT 6.5MSPS

,

,

ZONE'

1

~

,

,

,

, ZONE'
I
22
I
I
11fs
I
I
I
I
~

ZONE' ZONE'
I
I
2
3
I
fs

,

,

I
I
I
I
I
!

I
I
I
I
I
I

~

/

,
.

§

,
I
I

((

I

o

6.50

3.25

,

))

9.75

68.25

12fs
~

/

~
~

~
~
~
I

I

71.50

74.75

78.00

FREQUENCY (MHz)
IF

I

=69.875MHz ± 100kHz

Figure 5.31

DIGITAL FILTERING AND DECIMATION
OF THE 200kHz CHANNEL
~g~~TIZATION
~

_~-L~

U-

f/2

~~##/4W~

o

o

/

325MHz

AFTER FREQUENCY TRANSLATION

fs

=6.5MSPS

i

W~
.

Jd

)

~~~~~~~~~)
3.25MHz
AFTER DIGITAL FILTERING
PROCESSING GAIN 12dB

=

o

I

~~
o

fs

=406.25kSPS

3.25MHz

AFTER DECIMATION (+16)

I

)

325MHz

Figure 5.32
5-29

HIGH SPEED DESIGN TECHNIQUES

The concept of processing gain is common to all communications systems,
analog or digital. In a sampling system,
the quantization noise produced by the
ADC is spread over the entire Nyquist
bandwidth which extends from DC to
f s/2. If the signal bandwidth, BW, is
less than fgl2, digital filtering can
remove the noise components outside
this bandwidth, thereby increasing the
effective SNR. The processing gain in a
sampling system can be calculated from
the formula:

Processing Gain = 10

lO~ 2 .~w ).

The SINAD (noise and distortion measured over fgl2 bandwidth) of the ADC
at the bandwidth of the signal should
be used to compute the actual SINAD
by adding the processing gain determined by the above equation. If the
ADC is an ideal N-bit converter, then
its SNR (measured over the Nyquist
bandwidth) is 6.02N + 1.76dB.
Notice that as shown in the previous
narrowband receiver example, there
can be processing gain even if the
original signal is an undersampled one.
The only requirement is that the signal
bandwidth be less than fs/2, and that
the noise outside the signal bandwidth
be removed with a digital filter.

PROCESSING GAIN
•

Measure ADe SINAD (S.02N + 1.7SdB Theoretical)

•

Sampling Frequency

•

Signal Bandwidth

•

Processing Gain = 10109(

•

SINAD in Signal Bandwidth = SINAD + 10109(

•

SINAD (Theoretical)

•

Processing Gain Increases 3dB each time fs is doubled

=fs

=BW
fs )
2·BW

=S.02N + 1.7SdB + 10109( 2·BW
fs )

Figure 5.33
5 -30

fs )
2·BW

HIGH SPEED

ADC ,ApPLICATIONS

Wideband IF-Sampling Digital Receivers
Thus far, we have avoided a detailed
discussion of narrowband versus
wideband digital receivers. A digital
receiver can be either, but more detailed definitions are important at this
point. By narrowband, we mean that
sufficient pre-filtering has been done
such that all undesired signals have
been eliminated and that only the
signal of interest is presented to the
ADC input. This is the case for the
GSM basestation example previously
discussed.
Wideband simply means that a number
of channels are presented to input of

the ADC and further filtering, tuning,
and processing is performed digitally.
Usually, a wideband receiver is designed to receive an entire band; cellular or other similar wireless services
such as PCS (Personal Communications
Systems). In fact, one wideband digital
receiver can be used to receive all
channels within the band simultaneously, allowing almost all of the
analog hardware (including the ADC) to
be shared among all channels as shown
in Figure 5.34 which compares the
narrowband and the wideband approaches.

NARROWBAND VERSUS WIDEBAND DIGITAL RECEIVER
NARROWBAND
TUNED

DIGITAL
DECIMATION
FILTER

IF

1\
RF
FRONT
END

ADC

IF

1\

ADC

DSP

CHANNEL
1

•••

DIGITAL
DECIMATION
FILTER

DSP

DIGITAL
CHANNELIZER

DSP

CHANNEL
n

BW: 30-200kHZ

WIDEBAND
FIXED
LO

RF
FRONT
END

ADC
DIGITAL
CHANNELIZER

BW: 5-25MHz

1

•
••

IF

r--\

CHANNEL

DSP

CHANNEL
n

Figure 5.34

Note that in the narrowband digital
radio, there is one front-end LO and
mixer required per channel to provide
individual channel tuning. In the

wideband digital radio, however, the
first LO frequency is fixed, and the
"tuning" is done in the digital
channelizer circuits following the ADC.
5-31

HIGH SPEED DESIGN TECHNIQUES

A typical wideband digital receiver may
process a 5 to 25MHz band of signals
simultaneously. This approach is frequently called block conversion. In the
wideband digital receiver, the variable
local oscillator in the narrowband
receiver has been replaced with a fIXed
oscillator, so tuning must be accomplished digitally. Tuning is performed

using a digital down converter (DDC)
and filter chip frequently called a
channelizer. The term channelizer is
used because the purpose of these chips
is to select one channel out of the many
within the broadband spectrum actually present in the ADC output. A
typical channelizer is shown in Figure
5.35.

DIGITAL CHANNELIZER IN WIDEBAND RECEIVER

DECIMATION
FILTER

LOWPASS
FILTER

SERIAL
DATA
TO
DSP

DATA FROM
TUNING
CONTROL

TUNING
NCO
WIDEBAND
ADC

Q

DECIMATION
FILTER

LOWPASS
FILTER

Q

Figure 5.35

It consists of an NCO (Numerically
Controlled Oscillator) with tuning
capability, dual mixer, and matched
digital filters. These are the same
functions that would be required in an
analog receiver, but implemented in
digital form. The digital output from
the channelizer is the demodulated
signal in I and Q format, and all other
signals have been filtered and removed.
Since the channelizer output consists of
one selected RF channel, one
5-32

channelizer is required for each channel. The channelizer also serves to
decimate the output data rate such that
it can be processed by a DSP such as
the ADSP-2181 or the ADSP-21062.
The DSP extracts the signal information from the I and Q data and performs further processing. Another effect
of the filtering provided by the
channelizer is to increase the SNR by
adding processing gain.

HIGH SPEED

In the case of an AMPS signal, there
are 416 channels, each 30kHz wide, for
a total bandwidth of 12.5MHz (each of
the two carriers in a given region are
allocated 12.5MHz of the total 25MHz
cellular band). Each channel carries one
call, so there is a clear advantage in
using the wideband approach versus
the narrowband one in an AMPS
basestation which must handle between 50 and 60 simultaneous calls. On
the other hand, a 200kHz GSM channel
can carry 16 calls simultaneously (for
half-rate systems), so only three or four
channels are required in the typical
GSM basestation, and the narrowband
approach is more cost-effective. Using
to day's technology (1996), the breakeven cost point between narrowband
and wideband ranges from two and
eight channels.

ADC ,ApPLICATIONS

end must be approximately 95 to
100dBFS, allowing for additional
headroom. In addition, the GSM system
has 124 channels, each having a bandwidth of 200kHz for a total signal
bandwidth of 25MHz. The minimum
required sampling rate for an ADC
suitable for wideband GSM is therefore
greater than 50MSPS.
SFDR is a very important specification
when a mobile phone is near the
basestation because it is an indication
of how strong signals interfere with
signals in other channels. Strong signals usually produce the largest spurs
due to front-end distortion, and these
spurs can mask weaker signals from
mobile phones near the cell fringes. The
SFDR for weak signals provides an
indication of the overall noise floor, or
SINAD which can ultimately be related
to the receiver bit error rate (BER).

In an ADC used for narrowband applications, the key specifications are
SINAD, SFDR, and SNR. The
narrowband ADC can take advantage
of automatic gain ranging (as in the
AD6600) to account for signal amplitude variations between individual
channels and thereby achieve extra
dynamic range.

When ,digitizing a wideband signal, full
scale single-tone evaluations are no
longer sufficient. Two-tone and multiple-tone intermodulation testing in
conjunction with SFDR amplitude
sweeps are better indicators of performance.

On the other hand, an ADC used in a
wideband receiver must digitize all
channels simultaneously, thereby
eliminating the possibility of perchannel analog gain ranging. For
example, the GSM (European Digital
Cellular) system specification requires
the receiver to process signals between
-13dBm and -104dBm (with a noise
floor of -114dBm) in the presence of
many other signals. This is a dynamic
range of91dB! This implies that the
SFDR of the ADC and the analog front

The AMPS cellular system basestation
is ideally suited to the wideband digital
receiver design, and a simplified diagram of one is shown in Figure 5.37.
The AD9042 sampling frequency of
30.72MSPS is chosen to be a power-oftwo multiple of the channel bandwidth
(30kHz x 1024). Another popular AMPS
wideband receiver sampling frequency
is 40.96MSPS. The choice of IF frequency is flexible, and a second IF
stage may be required if lower IF
frequencies are chosen.

5-33

HIGH SPEED DESIGN TECHNIQUES

GSM VERSUS AMPS COMPARISONS
GSM

AMPS

Digital Receiver

Narrowband

Wideband

# of Channels

124

416

Channel BW

200kHz

30kHz

Total BW'

25M Hz

12.5MHz

Callers/Channel

16 (one-half rate)

1

ADC

11-bits with RSSI

12-bits

Requirements

6.5 MSPS

30.72 MSPS

92dB Dynamic Range

BOdB SFDR

12dB

27dB

Process Gain

Figure 5.36

AMPS WIDEBAND DIGITAL RECEIVER
416 CHANNELS
30kHz CHANNEL BW
1 CALLER/CHANNEL

=

fs 30.72 MSPS
OR 40.96 MSPS
IF

1\

AD9042
ACC

CHANNELIZER

DSP

•
•
•

•
•
•

CHANNELIZER

DSP

CHANNEL
1

•
•
•

BW: 12.5MHz

NOTE: THERE MAY BE
21F STAGES

n

Figure 5.37
5-34

CHANNEL

HIGH SPEED

With a sampling frequency of
30.72MSPS, the 12.5MHz bandwidth
signal can be positioned in the first
Nyquist zone (DC to 15.36MHz) with
an IF frequency of 7.68MHz, or in the
second Nyquist zone (15.36MHz to
30.72MHz) with an IF frequency of
23.04MHz.
With a sampling frequency of
40.96MSPS, the 12.5 MHz bandwidth
signal can be positioned in the first
Nyquist zone (DC to 20.48MHz) with
an IF frequency of 10.24MHz, or in the
second Nyquist zone (20.48MHz to

ADC ,ApPLICATIONS

40.96MHz) with an IF frequency of
30.72MHz.
The digital channelizers provide the
receiver tuning and demodulate the
signal into the I and Q components.
The output data rate to the DSPs after
decimation is 60kSPS. The processing
gain incurred is calculated as follows:
rrocessing Gain =
1010 J 30.72 )
g\2x 0.03

= 27.1dB.

AMPS WIDEBAND RECEIVER PROCESS GAIN

•

=30.72MSPS (1024· 30kHz)
Channel 8W =30kHz

•

Process Gain =

•

fs

10109(~)
2·BW

= 27.1d8

Figure 5.38

In addition to SFDR, two-tone and
multi-tone intermodulation distortion is
important in an ADC for wideband
receiver applications. Figure 5.39 shows
two strong signals in two adjacent
channels at frequencies fl and £2. If the
ADC has third-order intermodulation
distortion, these products will fall at

2f2-f1 and 2f1-f2 and are indistinguishable from signals which might be
present in these channels. This is one
reason the GSM system is difficult to
implement using the wideband approach, since the c:lynamic range requirement is greater than 91dB.
5-35

HIGH SPEED DESIGN TECHNIQUES

TWO-TONE INTERMODULATION DISTORTION
IN MULTICHANNEL SYSTEM
(GSM REQUIREMt:NT~ SHOWN)
·13dBm

STRONG SIGNALS

I

·104dBm

WEAK SIGNAL
OR 3RD ORDER IMD?

·114dBm ))\---'------1---~---'-------f+

Figure 5.39

The two-tone SFDR of the AD9042 is
greater than BOdB with input tones at
15.3MHz and 19.5MHz as shown in
Figure 5.40. Note than the amplitude of
each tone must be 6dB below full scale
in order to prevent the ADe from being
overdriven. The two-tone SFDR as a
function of input signal amplitude is

5-36

shown in Figure 5.41 for tone frequencies of 19.3MHz and 19.51MHz. The
upper curve is in dBFS, and the lower
in dBc. Note that th~ SFDR is greater
than BOdBFS for all input amplitudes.
Figure 5.42 shows a multitone FFT
output for the AD9042, and the ADC
still maintains B5dBFS of SFDR.

HIGH SPEED

ADC ,ApPLICATIONS

AD9042 TWO-TONE FFT OUTPUT
F1 15.3MHz, F2 19.5MHz, fs 41MSPS

=

=

=

r:D

'C

I

w -20
<
()
...I

en
~

~Or--r--+--+--+-~--~~-+-r--~~

:;:)

u..

()

~ ~Or--r--+--+--+-~--~~-+-r--~~

~

w

>

~

m

-80
~-r~+--+--+-~~~~-+-r~~~

a:

ffi

-100

3:
o
Co

-120

S.2

4.1

de

16.4

12.3

20.5

FREQUENCY - MHz

Figure 5.40

F1

=

AD9042 TWO-TONE SFDR
19.3MHz, F2 19.51MHz, fs 41MSPS

=

100

--

~ 90
r:D

~
z

SO

~

70

'C
I

60

r:D

en

t--

:;:)

o

a:

50

t--

dBFS'
I"'"

/

ENCODE = 41 MSPS
F1 = 19.3MHz
F2 = 19.51 MHz

:;:)

~ 40

w

~ 30

20

~

10

a:

V .. ....

/
fII' ••

..
...
...

~

()

li;

=

./

......*

10-

.......

""""

/ ...
V.
..
dB;'" ••••• SFDR =80dS
i"'" ••••

.......

.""

REFERENCE LINE

-

.....

~SO

-70

~O

-50

~O

INPUT POWER LEVEL (F1

-30

=F2) -

-20

-10

0

dSFS

Figure 5.41
5-37

HIGH SPEED DESIGN TECHNIQUES

AD9042 MULTITONE PERFORMANCE (4 TONES)
fs 41MSPS

=

en

'0

~ -20 J----+---I--t---+--+--Htt+-+---r--t-""""1

...I

~
en
~

~O~--+---I~~~--+-~+-+---r--r-~

;:)

u.

(.)

~ ~0J--~--I--t---+-+-+Mr-r--r~t-""""1

~

w

> ~OJ----+---I--t---+-+-+Mr-r---r--t-""""1

~w

a::
a::
-100
w

oD.
==

-120
de

4.1

8.2
12.3
FREQUENCY - MHz

16.4

20.5

Figure 5.42

Direct IF·to·Digital Considerations
The dynamic performance of the
AD9042 extends well beyond 20MHz
analog input signals (see Figure 5.43).
Therefore it can be used to perform
direct IF-to-digital conversions using a
wide range of IF frequencies. These IF
signals can be undersampled as previously described, and the minimum

5-38

sampling frequency required is determined by the bandwidth of the IF
signal. Figure 5.44 shows a 21.4MHz
signal sampled at lOMSPS using the
AD9042. Note that under these conditions, the SFDR performance is greater
than 80dBFS.

HIGH SPEED

ADC APPLICATIONS

AD9042 SFDR VERSUS INPUT FREQUENCY
90

--- '\

""-

~

80

en

~ 70

\

"C

I

a:

~ 60

~

\

en

t;

a:

~ 50

\

40

30

1

2

4
10
20
40
ANALOG INPUT FREQUENCY - MHz

100

Figure 5.43

AD9042 FFT OUTPUT FOR IF SAMPLED INPUT:
fs = 10MSPS, ANALOG INPUT = 21.4MHz
!Xl
"C

~ -20 1----1--+--1--1---4---1-- AIN = 21.4MHz

...J

c(

o
en
~

~O~~~-++--+-~~~-+--+~

;:)

LL

o
C

c(

e

~Or-~~-++--+-r-~~--+--+~

w

~ ~O~~~-++--+-r-~~-+--+~

~
a:

...J
W

ffi -100

~ -120

dc

1.0

2.0
3.0
FREQUENCY - MHz

4.0

5.0

Figure 5.44
5-39

HIGH SPEED DESIGN TECHNIQUES

The AD6640 represents the next generation in IF sampling ADCs. Key
specifications for the AD6640 are
summarized in Figure 5.45. The architecture is similar to that of the AD9042,
but the device is fabricated on a faster
XFCB process. The input structure is
fully differential and designed for
transformer coupling for minimum
distortion. Maximum sampling frequency is 65MSPS, and the SINAD
performance is 67dB at 60MHz analog
input. SFDR is greater than 80dBFS
for frequencies up to 25MHz. This
device allows direct IF sampling in
wideband communications systems
having bandwidths up to 25MHz (such
as the AMPS system, where each

carrier is allocated 12.5MHz of spectrum). For systems with smaller bandwidths, the higher sampling frequency
provided by the AD6640 will allow
analog antialiasing filter requirements
to be relaxed and provide processing
gain. In undersampling applications,
the device can be used to digitize
70MHz IF signals which lie in the
second or third Nyquist zone. For
instance, a 30MHz wideband signal
bandwidth centered around a carrier
frequency of 48.75MHz can be digitized
at 65MSPS as shown in Figure 5.46. In
narrowband applications, the high
sampling frequency can be used to
achieve additional processing gain.

AD6640 12-BIT, 65MSPS ADC KEY SPECIFICATIONS
•

12-bit, 65MSPS IF-SAMPLING ADC

•

Based on AD9042 architecture, but 1.5X faster CB process

•

Fully differential inputs for optimum distortion performance

•

SFDR Greater than SOdB up to 25MHz Input

•

6SdB SINAD for 60MHz IF input

•

Single +5V Supply, 695mW

•

44·Lead TQFP Package

Figure 5.45

5-40

HIGH SPEED ADC APPLICATIONS

SAMPLING A 25MHz BW SIGNAL USING AD6640:
IF FREQUENCY 48.75MHz, fs 65MSPS

=

=

ZONE 3

ZONE 2

ZONE 1

fs

IF

o

=65MSPS

65

32.5

=

I

97.5
f(MHz)

IF
48.75MHz
SIGNAL BW 25MHz

=

Figure 5.46

Achieving Wide Dynamic Range in High Speed ADCs Using Dither
There are two fundamental limitations
to maximizing SFDR in a high speed
ADC. The first is the distortion produced by the front-end amplifier and
the sample-and-hold circuit. The second
is that produced by non-linearity in the
actual transfer function of the encoder
portion of the ADC. The key to wide
SFDR is to minimize the non-linearity
of each.
There is nothing that can be done
externally to the ADC to significantly
reduce the inherent distortion caused
by the ADC front end. However, the
non-linearity in the ADC encoder
transfer function can be reduced by the
proper use of dither (external noise
which is summed with the analog input
signal to the ADC).

Dithering improves ADC SFDR under
certain conditions. For example, even in
a perfect ADC, there is some correlation
between the quantization noise and the
input signal. This can reduce the SFDR
of the ADC, especially if the input
signal is an exact sub-multiple of the
sampling frequency. Summing broadband noise (about 112 LSB rms in
amplitude) with the input signal tends
to randomize the quantization noise
and minimize this effect (see Figure
5.47). In most systems, however, there
is enough noise riding on top of the
signal so that adding additional dither
noise is not required. Increasing the
wideband rms noise level beyond an
LSB will proportionally reduce the ADC
SNR.
5-41

HIGH SPEED DESIGN TECHNIQUES

USING DITHER TO RANDOMIZE ADC TRANSFER FUNCTION
LARGE
AMPLITUDE

SMALL
AMPLITUDE

ADe

ADe

ADDER

+
~1/2

LSB RMS

NOISE
GENERATOR

RANDOM
NUMBER
GENERATOR

DAe

Figure 5.47

Other schemes have been developed
which use larger amounts of dither
noise to randomize the transfer function of the ADC. Figure 5.47 also shows
a dither noise source comprised of a
pseudo-random number generator
which drives a DAC. This signal is
subtracted from the ADC input signal
and then digitally added to the ADC
output, thereby causing no significant
degradation in SNR. An inherent
disadvantage of this technique is that
the allowable input signal swing is
reduced as the amplitude of the dither
signal is increased. This reduction in
signal amplitude is required to prevent
overdriving the ADC. It should be noted
that this scheme does not significantly
improve distortion created by the frontend of the ADC, only that produced by

5-42

the non-linearity of the ADC
transfer function.

~ncoder

Another method which is easier to
implement, especially in wideband
receivers, is to inject a narrowband
dither signal outside the signal band of
interest as shown in Figure 5.48. Usually, there are no signal components
located in the frequency range near DC,
so this low-frequency region is often
used for such a dither signal. Another
possible location for the dither signal is
slightly below f s/2. Because the dither
signal occupies only a small bandwidth
relative to the signal bandwidth, there
is no significant degradation in SNR, as
would occur if the dither was broadband.

HIGH SPEED

ADC APPLICATIONS

INJECTING OUT-OF-BAND DITHER TO IMPROVE ADC SFDR
f5

INPUT

BPF

ADC

/\
+

NOISE
GENERATOR

OUT-OF-BAND NOISE

OUT·OF·
BAND
FILTER

NEAR DC OR f5/2

Figure 5.48
A subranging ADC such as the AD9042
(see Figure 5.49) has small differential
non-linearity errors that occur at specific regions across the ADC range. For
instance, the AD9042 uses a 6-bit ADC
followed by a 7-bit one. There are 64
decision points associated with the
main-range 6-bit ADC, and they occur
every 15.625mV for a IV full scale
input range. Figure 5.50 shows a
greatly exaggerated representation of
these non-linearities.
The distortion components produced by
the front end of the AD9042 up to about
20MHz analog input are negligible
compared to those produced by the
encoder. That is, the static non-linearity
of the AD9042 transfer function is the
chief limitation to SFDR.

of these small DNL errors are randomized across the ADC input range,
thereby reducing the average DNL
error. The first plot shown in Figure
5.51 shows the undithered DNL over a
small portion of the input signal range.
The horizontal axis has been expanded
to show two of the subranging points
which are spaced 15.625mV (64 LSBs)
apart. The second plot shows the DNL
after adding 5.3mVrms (22 LSBs rms)
of dither. This amount of dither corresponds to -32.5dBm (IV p-p full scale
corresponds to +4dBm). It was determined that further increases in dither
amplitude provided no improvement in
the AD9042 SFDR and would only
serve to cause a loss in headroom and a
decrease in SNR.

The goal is to select the proper amount
of out-of-band dither so that the effect
5-43

•

HIGH SPEED DESIGN TECHNIQUES

AD904212-BIT, 41 MSPS PIPELINED SUBRANGING ADC
WITH DIGITAL ERROR CORRECTION
ANALOG
SHA
SHA
INPUTu--_--l SHA
3

2

1

6·BIT
ADC

7·BIT
ADC

6·BIT
DAC
6

BUFFER
REGISTER

7

6

ERROR CORRECTION LOGIC
12

OUTPUT REGISTERS
12

Figure 5.49

AD9042 SUBRANGING POINT DNL ERRORS
(EXAGGERATED)

OUTPUT
CODE
I
I
I
~ 15.625mV I~
I

64LSBs

I

ANALOG INPUT
Figure 5.50
5-44

HIGH SPEED

ADC APPLICATIONS

AD9042 UNDITHERED AND DITHERED DNL

UNDITHERED

DNL

21.3 LSBs DITHER

1.5.-----r--------...------.

1.5

1.01---1---------11---1

1.0

0.5 1 - - - H - - - r " ' T ' - - . - - - - . - - - - H - - - r l

0.5

(LSBs)

o

--

-0.5 ' - - - - - - - - - - - - - - - - - '

-0.5

-FS

-FS

+ FS

~

~

+ FS

Figure 5.51

The dither signal was generated using
a voltage feedback op amp (AD8048,
3.8nV/-VHz input voltage noise, 200MHz
gain-bandwidth product) as the noise
source (see Figure 5.52). The op amp is
configured for a gain of +26, and the
output noise spectral density is about
100nV/-VHz over an 8MHz bandwidth.
The output of the noise generator is
then amplified by the AD600 dual
wideband VCA which provides a gain
(in dB) which is proportional to the
control voltage. The control voltage can
be fixed, or programmed using a DAC
as shown. The gain of the AD600 can
be set from OdB to 80dB by varying the

control voltage from 0 to +lV. The
bandwidth of the noise is limited to
about 300kHz with a lowpass filter.
The filter .can be either passive or
active, but requires at least 4 poles in
order to attenuate the out-of-band
noise. The output of the lowpass filter is
buffered with the AD797 low-noise op
amp which also provides a gain of +2.
The filtered noise is summed directly
into the input circuit of the AD9042
through a capacitor and a lkO series
resistor. The net input impedance of the
AD9042 is 500 (61.90 in parallel with
the 250Q AD9042 internal impedance).

5-45

HIGH SPEED DESIGN TECHNIQUES

DITHER NOISE GENERATOR
10n

1OOnV/" Hz
BW~8MHz

DAC

A1,A2:
1/2AD600

300kHz

AD9042
Z= 2500

LPF

Figure 5.52

The dramatic improvement in SFDR
obtained with out-of-band dither is
shown in Figure 5.53 using a 4k FFT,
where the AD9042 is sampling a
19.5MHz signal (-29dBFS) at 41MSPS.
Note that the SFDR without dither is

5-46

approximately 80dBFS compared to
94dBFS with dither, representing a
14dB improvement! This improvement
is also shown in the SFDR amplitude
sweeps shown in Figure 5.54. Note the
similar improvement.

HIGH SPEED

ADC ,ApPLICATIONS

AD9042 UNDITHERED AND DITHERED 4k FFT OUTPUT

DITHERED

UNDITHERED

.,
ID

AIN = 19.5MHz @-29dBFS
NO DITHER
1---4---11---4---1---1

I

w -20

~

~ ~0~~~~~~--~~--4-~--4-~

~
(J

~ ~0~~~~~~r-4-~--4-~--1-~

g
w

~a: ~O~~~~~~~~~-+~~-+rl+~
ffi -100

~ -120

4.1

de

8.2
12.3
FREQUENCY - MHz

8.2
12.3
FREQUENCY - MHz

4.1

20.5

16.4

20.5

16.4

Figure 5.53

AD9042 UNDITHERED AND DITHERED SFDR

DITHERED

UNDITHERED
100

100

90

90

.,

~ 80 -

J,

ENCODE = 41 MSPS
AIN = 19.5MHz
NO DITHER

J.//'

70

::l

~

60

5i

50

p'

::l

w
~

(J

40

I~ 30

'\

~ 20

10

/

~o"

~

"

70
60

5i

50

~

40

/

::l

(J

I~ ..' ...."

o

~ 20

10

/V " " "
,..' ..'

./"' " " "

I~ 30

"" SFDR = 80dB
REFERENCE LINE
I
I
I
-70
~O
-50
~O
-30
-20
-10
ANALOG INPUT POWER LEVEL - dBFS

""

J,

r-.

/'f " " "

::l

~

w

~'

/

o

v;J'T

/.,' "
""

ENCODE = 41 MSPS
AIN = 19.5MHz
DITHER = -32.5dBm

.,

~ 80 -

/'

~O

"

"" SFDR = 80dB
REFERENCE LINE
I
I
I
-70
~O
-50
~O
-30
-20
-10
ANALOG INPUT POWER LEVEL - dBFS

"

,;
;;

C' ."" "

Figure 5.54
5-47

HIGH SPEED DESIGN TECHNIQUES

5.55 shows the effects of dither using a
128k FFT and a 2.5MHz input signal.
The SFDR with dither is greater than

At lower frequencies, the FFT size must
be increased from 4k to 128k (reducing
the FFT noise floor by 15dB) in order to
measure the dithered SFDR. Figure

lOOdBFS.

AD9042 UNDITHERED AND DITHERED 128k FFT OUTPUTS

DITHERED

UNDITHERED
In
'C

In
'C
I

~ -20 I---+--I--I--+--+ AIN = 2.5MHz @ -26 dBFS
~

~ -20 1--+--+--+---+--1- DITHI:R = -32.5dBm

NO DITHER

~

C/)

::l

;:)

u.

::l
it

(J

(J

-401----++---+--+--+---+-+--+--+--+---1

~ -6ol----++---+--+--+---+-+--+--+--+---1
~
w
>
j::

:5w

-8ol----++---+--+-:-+---+-+--+--+--+---1

a:
a: -100 1frlI-1H-IHt-+-I-+-

~

-120

de

4.1

8.2
12.3
FREQUENCY - MHz

16.4

20.5

c

c(

-40 h:-+t--t--t--f----+-+--+--I----I---l
-60

~

~ -80 1'IHft-+t--t--t--f----+-+--+--I----I---l
:5
~
ffi -100 t-t-;t;±~:-+-_+---+_:__+--+--I----I---l

~ -120

Figure 5.55

5-48

de

8.2
12.3
FREQUENCY - MHz

16.4

20.5

HIGH SPEED

ADC ,ApPLICATIONS

High Speed ADC Applications in Digital Communications Systems and
Direct Broadcast Satellite (DBS) Set-Top Boxes
In a digital communications system,
digital data (which can be digitized
analog signals) is formatted and transmitted serially over an appropriate
medium. The GSM cellular telephone
system is an example. The ubiquitous
modem (modulator/demodulator), which
PCs and FAX machines use to transmit
and receive data over the standard dialup telephone connection, uses sophisticated modulation techniques to place
huge amounts of data in the 4kHz
bandwidth telephone channel.

used in Direct Broadcast Satellite
systems. The diagram (constellation)
shows the four possible data points,
each representing 2-bits of binary
information. Each point in the constellation is called a symbol and has a
specific I and Q value. In the case of
QPSK, there are two bits of information
per symbol. The symbol rate is often
referred to as the baud rate. For example, in QPSK, if the symbol (or baud)
rate is 30Mbaud (lbaud = Isymbol/sec),
the bit rate is 60Mbits/sec. It is common practice to sample these types of
signals at twice the symbol (or baud)
rate. The I and Q ADC and DSP must
identify the signal as representing one
of two possible levels, and ADCs of 4, 5,
or 6-bits are commonly used in this
application for additional noise margin
and to achieve the overall system biterror-rate (BER) requirement.

Most digital transmission schemes use
some form of in-phase and quadrature
(I and Q) modulation to maximize the
amount of data transmitted over a
given channel bandwidth. Two examples are shown in Figure 5.56 and
Figure 5.57. The first is called Quadrature Phase Shift Keying (QPSK) and is

II

QPSK MODULAliON
01

Q

•

11

•

2-BITS/SYMBOL

10

00

•

•

I OR Q CHANNEL

X X X X
SAMPLING
CLOCK

1

I I I I

1

t

.

Figure 5.56
5-49

HIGH SPEED DESIGN TECHNIQUES

In the QPSK system, the magnitude of
each symbol is equal, and only the
phase is modulated. More 'complex
modulation schemes such as QAM
(Quadrature Amplitude Modulation),
use more symbols on the constellation
and thereby transmit more bits of
information per symbol (at the expense
of more sensitivity to noise and more
complex digital signal processing).
Figure 5.57 shows a 16-QAM constella-

tion which contains 4-bits of information per symbol. Note that the I and Q
channel receiver DSP must now identify the signal as representing one of
the four possible levels. Although the
16-QAM signal carries more bits per
symbol, it is more sensitive to noise,
and the ADC requires more resolution
(typically 8-bits) than for QPSK modulation (typically 4, 5, or 6 bits).

16-QAM MODULATION
Q

4·BITS/SYMBOL

•

•

•

•

•

•

•

•

•

•

•

•

•

0000
I OR Q CHANNEL

1111

•

•

•

t t t t
SAMPLING
CLOCK

I I I I I I

t

~

Figure 5.57
In the digital receiver, the I and Q
components are separated by a quadrature demodulator and digitized by two
ADCs operating in parallel. The ADC
sampling rate is generally twice the
symbol rate. In the case of Direct
Broadcast Satellite (DBS), the symbol
rate is 30Mbaud (lbaud = Isymbo]Jsec),
the bit rate 60rvlliits/sec, and the ADe
sampling rate is 60MSPS. The actual
5-50

signals at the ADC input are called "eye
patterns" because the intersymbol
interference due to noise and limited
bandwidth smears the level transitions
so that the regions where the data is
valid are located in the center of the eye
opening. Figure 5.58 shows a typical II
Q demodulator followed by a dual ADC
such as the AD9066 (6-bits, 60~,1:SPS).

HIGH SPEED

ADC ,ApPLICATIONS

IF SAMPLING USING AD9066 6-BIT, 60MSPS ADC

LPF
70MHz
IF

AD9066
ADC

QVCO

Q

Q

Q

DSP

LPF

FOR DBS, SYMBOL (BAUD) RATE = 30MBAUD, QPSK
SAMPLING RATE 60MSPS

=

Figure 5.58

A recent popular consumer application
of digital communications is in Direct
Broadcast Satellite (DBS) systems. A
simplified block diagram of a DBS
system is shown in Figure 5.59. The
objective is to transmit up to 150 channels of video programming to home
receivers which use a small (18 inch)
dish and an inexpensive (less than
$500) receiver (set-top box). The subscription costs of the services is compatible with cable TV, but picture quality
(because of digital transmission inherent noise immunity) is generally superior over all 150 channels.
MPEG encoding and decoding reduces
the data rates to fit the channel bandwidth. The MPEG (Motion Picture

Experts Group) standard supports
various data rates and minimizes the
bandwidth used. For example, a typical
24-frame-per-second NTSC-quality
movie needs about aMbits/sec after
encoding. A more complex and fastmoving show, such as a soccer game,
requires 5 to 6 Mbits/sec. In a DBS
system, the MPEG encoding rate is
kept at a minimum value compatible
with the anticipated video signal characteristics. Multiple MPEG data
streams are multiplexed and sent
through a single satellite transponder.
In addition, statistical multiplexing
dynamically varies the data rate given
to each source as the program content
changes.

5 -51

•

HIGH SPEED DESIGN TECHNIQUES

DIRECT BROADCAST SATELLITE (DBS)
12.2 -12.7 GHz, 150 CHANNELS

DBS

~
UPLINK

SATELLITE

18" DISH
480MHz

70MHz

1GHz

LNB
DOWN CONVERTER

LO 1
VARIABLE

I

1STIF

L02
FIXED

2ND IF

70MHz
MPEG
COMPRESSION

I
VIDEO
SOURCES

DSP
Q

MPEG

BASEBAND

DECODE

VIDEO

AND
DAC

OR
CH. 3,4 RF

Figure 5.59

The satellite downlink frequency is Kuband (12.2 to 12.7GHz), and the transponder output power is about 120W
(10 to 20 times that of a typical communications satellite which is designed for
much larger receiver antennas). The
LNB (Low Noise Block Converter)
converts the 12.2 to 12.7GHz untuned
band down to 950MHz to 1450MHz,
where the signal is easier to tune, filter,
and bring into the home over standard
coaxial cable. The lower frequency
signal (1GHz) incurs less loss over
standard coaxial cable from the outside
antenna to the inside of the house
(generally 50 feet or more) than the Kuband signal (12GHz).
The set-top box mixes the RF (1GHz)
signal down to the first fixed IF frequency of 480MHz. The La which
drives the mixer is used for channel
tuning. A second fixed-frequency IF
5-52

stage brings the tuned signal down to
70MHz where it is synchronously
demodulated into baseband I and Q
components. The modulation scheme is
QPSK, the symbol rate is 30Mbaud,
and the ADC sampling rate 60MSPS.
Figure 5.60 shows a two-chip solution
to the front-end of the set-top box using
the AD6461 (quadrature demodulator
and baseband filter) and the AD6462
(duaI5-bit ADC and digital receiver).
The input to the AD6461 is the
480MHz DBS IF signal. The chip-set is
designed to support symbol rates up to
42.5Mbaud. The AD6461 utilizes Analog Devices' XFCB process and is packaged in 28-pin sale dissipating about
500mW. The AD6462 utilizes a 0.6
micron CMOS process and is packaged
in an 80-pin PQFP dissipating approximately L2W (operating dynamically).

HIGH SPEED

ADC APPLICATIONS

NEXT-GENERATION DBS 480MI1z IF SIGNAL PROCESSING
AD6461 QUADRATURE DEMOD
AND BASEBAND FILTER
I----e---l

AD6462 DUAL 5-BIT ADC
AND DIGITAL RECEIVER

MATCHED
FILTER

ADC

DEMOD

~...-r---I MATCHED ~--I---I
FILTER

ADC

1----1

Q

...--_....1--_--. DATA

AGC

VCOAND
TUNING
CONTROL

FREQ.
SYNTH.

FORWARD
ERROR
CORRECTION

DAC

SERIAL PORT
AND
CONTROL

OUT

Figure 5.60

5-53

HIGH SPEED DESIGN TECHNIQUES

REFERENCES
1.

An Introduction to the Imaging CCD Array, Technical Note 82W-4022,
Tektronix, Inc., Beaverton, OR., 1987.

2.

Brad Brannon, Using Wide Dynamic Range Converters for Wide Band
Radios, RF Design, May 1995, pp.50-65.

3.

Joe Mitola, The Software Radio Architecture, mEE Communications
Magazine, Vol. 33, No.5, May 1995, pp. 26-38.

4.

Jeffery Wepman, Analog-to-Digital Converters and Their Applications
in Radio Receivers, IEEE Communications Magazine, Vol. 33, No.5, May
1995, pp. 39-45.

5.

Rupert Baines, The DSP Bottleneck, mEE CommunicationsMagazine,
Vol. 33, No.5, May 1995, pp. 46-54.

6.

Brad Brannon, Overcoming Converter Nonlinearities with Dither, Application Note AN-410, Analog Devices, 1995.

7.

Chris Keate and Mark O'Brien, DBS Receiver Chip Simplifies Set-Top Box
Design, RF Design, November 1995, pp. 36-42.

8.

Bill Schweber, Direct Satellite Broadcast, EDN,December 21, 1995, pp. 5358.

5-54

SECTION 6
HIGH SPEED DACs AND DDS SYSTEMS

•
•
•
•
•
•
•
•
•
•
•

Introduction to DDS
Aliasing in DDS Systems
125MSPS DDS System (AD9850)
DDS Systems as ADC Clock Drivers
Amplitude Modulation in a DDS System
The AD9831/AD9832 Complete DDS System
Spurious Free Dynamic Range Considerations in
DDS Systems
High Speed Low Distortion DAC Architectures
Improving SFDR Using Sample-and-Hold
Deglitchers
High Speed Interpolating DACs
QPSK Signal Generation Using DDS (AD9853)

HIGH SPEED DESIGN TECHNIQUES

HIGH

SPEED DACs AND DDS SYSTEMS

SECTION 6
HIGH SPEED DACs AND DDS SYSTEMS
Walt Kester
INTRODUCTION
A frequency synthesizer generates
multiple frequencies from one or more
frequency references. These devices
have been used for decades, especially
in communications systems. Many are
based upon switching and mixing
frequency outputs from a bank of
crystal oscillators. Others have been
based upon well understood techniques
utilizing phase-locked loops (PLLs).
This mature technology is illustrated in
Figure 6.1. A fixed-frequency reference
drives one input of the phase comparator. The other phase comparator input

is driven from a divide-by-N counter
which is in tum driven by a voltagecontrolled-oscillator (VeO). Negative
feedback forces the output of the internalloop filter to a value which makes
the veo output frequency N -times the
reference frequency. The time constant
of the loop is controlled by the loop
filter. There are many tradeoffs in
designing a PLL, such a phase noise,
tuning speed, frequency resolution, etc.,
and there are many good references on
the subject (see References 1,2, and 3).

FREQUENCY SYNTHESIS USING
OSCILLATORS AND PHASE-LOCKED LOOPS
OSCILLATOR BANK

PHASE-LOCKED LOOP

XO

1
fc
PHASE
,...-_ _----, COMPARATOR

FIXED
FREQUENCY
REFERENCE

XO

2

XO
3

VCO

MIXER
fout= N· fc

••

&
Figure 6.1
6 -1

HIGH SPEED DESIGN TECHNIQUES

With the widespread use of digital
techniques in instrumentation and
communications systems, a digitallycontrolled method of generating multiple frequencies from a reference
frequency source has evolved called
Direct Digital Synthesis (DDS). The
basic architecture is shown in Figure
6.2. In this simplified model, a stable
clock drives a programmable-read-onlymemory (PROM) which stores one or
more integral number of cycles of a
sinewave (or other arbitrary waveform,
for that matter). AB the address counter
steps through each memory location,
the corresponding digital amplitude of
the signal at each location drives a
DAC which in turn generates the
analog output signal. The spectral

purity of the fmal analog output signal
is determined primarily by the DAC.
The phase noise is basically that of the
reference clock.
The DDS system differs from the PLL
in several ways. Because a DDS system
is a sampled data system, all the issues
involved in sampling must be considered: quantization noise, aliasing,
filtering, etc. For instance, the higher
order harmonics of the DAC output
frequencies fold back into the Nyquist
bandwidth, making them unfilterable,
whereas, the higher order harmonics of
the output of PLL-based synthesizers
can be filtered. There are other considerations which will be discussed
shortly.

FUNDAMENTAL DIRECT DIGITAL SYNTHESIS SYS.TEM

1
CLOCK

ADDRESS
COUNTER

fc

/

/

SIN
LOOKUP
TABLE

N·BITS

/

/

REGISTER

l'
•

LOOKUP TABLE CONTAINS SIN
DATA FOR INTEGRAL NUMBER
OF CYCLES

N·BITS

DAC

1
fout
LPF

Figure 6.2
6-2

SPEED DACs AND DDS SYSTEMS

HIGH

A FLEXIBLE DDS SYSTEM
PHASE ACCUMULATOR

n = 24-32 BITS

SERIAL
~---. OR BYTE
LOAD
REGISTER

n

n

r-------,

PARALLEL
DELTA
PHASE
REGISTER

PHASE

n

REGISTEDI-+-tI~

M

r----i

SIN ROM
LOOKUP
TABLE

CLOCK

PHASE

FREQUENCY CONTROL

14-16 BITS

N·BITS

AMPLITUDE
TRUNCATION

fc

DAC

LPF

fo

Figure 6.3

A fundamental problem with this
simple DDS system is that the final
output frequency can be changed only
by changing the reference clock frequency or by reprogramming the
PROM, making it rather inflexible. A
practical DDS system implements this
basic function in a much more flexible
and efficient manner using digital
hardware called a Numerically Controlled Oscillator (NCO). A block diagram of such a system is shown in
Figure 6.3.
The heart of the system is the phase
accumulator whose contents is updated
once each clock cycle. Each time the
phase accumulator is updated,the
digital number, M, stored in the delta
phase register is added to the number in
the phase accumulator register. Assume that the number in the delta
phase register is 00 ... 01 and that the

initial contents of the phase accumulator is 00... 00. The phase accumulator is
updated by 00 ... 01 on each clock cycle.
If the accumulator is 32-bits wide, 232
clock cycles (over 4 billion) are required
before the phase accumulator returns to
00... 00, and the cycle repeats.
The truncated output of the phase
accumulator serves as the address to a
sine (or cosine) lookup table. Each
address in the lookup table corresponds
to a phase point on the sinewave from
0° to 360°. The lookup table contains
the corresponding digital amplitude
information for one complete cycle of a
sinewave. (Actually, only data for 90° is
required because the quadrature data
is contained in the two MSBs). The
lookup table therefore maps the phase
information from the phase accumulator into a digital amplitude word, which
in turn drives the DAC.
6-3

HIGH SPEED DESIGN TECHNIQUES

Consider the case for n=32, and M= 1.
The phase accumulator steps through
each of 232 possible outputs before it
overflows. The corresponding output
sinewave frequency is e~ual to the clock
frequency divided by 23 . If M=2, then
the phase accumulator register "rolls
over" twice as fast, and the output
frequency is doubled. This can be
generalized as follows.
For an n-bit phase accumulator (n
generally ranges from 24 to 32 in most
DDS systems), there are 2n possible
phase points. The digital word in the
delta phase register, M, represents the
amount the phase accumulator is
incremented each clock cycle. If fc is the
clock frequency, then the frequency of
the output sinewave is equal to:

This equation is known as the DDS
"tuning equation." Note that the frequency resolution of the system is equal
to fcl2n. For n=32, the resolution is
greater than one part in four billion! In
a practical DDS system, all the bits out
of the phase accumulator are not
passed on to the lookup table, but are
truncated, leaving only the first 13 to
15 MSBs. This reduces the size of the
lookup table and does not affect the
frequency resolution. The phase truncation only adds a small but acceptable
amount of phase noise to the final
output.

6-4

The resolution of the DAC is typically 2
to 4 bits less than the width of the
lookup table. Even a perfect N-bit DAC
will add quantization noise to the
output. Figure 6.4 shows the calculated
output spectrum for a 32-bit phase
accumulator, 15-bit phase truncation,
and a 12-bit DAC. The value of M was
chosen so that the output frequency
was slightly offset from 0.25 times the
clock frequency. Note that the spurs
caused by the phase truncation and the
finite DAC resolution are all at least
90dB below the fullscale output. This
performance far exceeds that of any
commercially available 12-bit DAC and
is adequate for most applications.
The basic DDS system described above
is extremely flexible and has high
resolution. The frequency can be
changed instantaneously with no phase
discontinuity by simply changing the
contents of the M-register. However,
practical DDS systems first require the
execution of a serial, or byte-loading
sequence to get the new frequency word
into an internal buffer register which
precedes the parallel-output M-register.
This is done to minimize package pin
count. After the new word is loaded into
the buffer register, the parallel-output
delta phase register is clocked, thereby
changing all the bits simultaneously.
The number of clock cycles required to
load the delta-phase buffer register
determines the maximum rate at which
the output frequency can be changed.

HIGH SPEED

DACs AND DDS SYSTEMS

CALCULATED OUTPUT SPECTRUM SHOWS
90dB SFDR FOR 15-BIT PHASE TRUNCATION AND
12-BIT OUTPUT DATA TRUNCATION
o r-~---r--~--~~--~-------------20 r--+---~---r--4--~--+-~--~---4-~

~ -4 0 t---+-----+--+--f---f--+-~---+---+----!
"0
I
W

§

-6 0 r----t-----t--+--+---+---+-~-~-4----l

t:

z
<

" -80
:E

-1 0 0

-120

r----t-----t--+---4-~-+-~-~-4-~

J--t-t-+-+t-+-1I+-++-~

1!-..~11111

l1li,

o

0.05

0.1

0.15 0.2

0.25

0.3

0.35

0.4

0.45

0.5

NORMALIZED FREQUENCY - fOUTIfCLK

Figure 6.4

ALIASING IN DDS SYSTEMS
There is one important limitation to the
range of output frequencies that can be
generated from the simple DDS system.
The Nyquist Criteria states that the
clock frequency (sample rate) must be
at least twice the output frequency.
Practical limitations restrict the actual
highest output frequency to about 1/3
the clock frequency. Figure 6.5 shows
the output of a DAC in a DDS system
where the output frequency is 30MHz
and the clock frequency is lOOMHz. An
antialiasing filter must follow the
reconstruction DAC to remove the lower
image frequency (lOO-30=70MHz) as
shown in the figure.
Note that the amplitude response of the
DAC output (before filtering) follows a
sin(x)/x response with zeros at the clock
frequency and multiples thereof. The

exact equation for the normalized
output amplitude, A(fo), is given by:
1tf
o)
fc
1tfo
fc

. (SIn
A(f )=
o

where fo is the output frequency and fc
is the clock frequency.
This rolloff is because the DAC output
is not a series of zero-width impulses
(as in a perfect re-sampler), but a series
of rectangular pulses whose width is
equal to the reciprocal of the update
rate. The amplitude of the sin(x)/x
response is down 3.92dB at the Nyquist
frequency (1/2 the DAC update rate). In
6-5

HIGH SPEED DESIGN TECHNIQUES

ALIASING IN A DDS SYSTEM

LPF

------ --

-

.....

dB
fo

30MHz

2

3

o

10

4

20

30

40

50

60

70

80

90

100

110

120

130

FREQUENCY (MHz)

Figure 6.5

practice, the transfer function of the
antialiasing filter is designed to compensate for the sin(x)/x roll off so that
the overall frequency response is relatively flat up to the maximum output
DAC frequency (generally 113 the
update rate).
Another important consideration is
that, unlike a PLL-based system, the
higher order harmonics of the fundamental output frequency in a DDS
system will fold back into the baseband
because of aliasing. These harmonics
cannot be removed by the antialiasing

6-6

filter. For instance, if the clock frequency is lOOMHz, and the output
frequency is 30MHz, the second harmonic of the 30MHz output signal
appears at 60MHz (out of band), but
also at l00-60=40MHz (the aliased
component. Similarly, the third harmonic (90MHz) appears inband at
lOO-90=lOMHz, and the fourth at
120-100MHz=20MHz. Higher order
harmonics also fall within the Nyquist
bandwidth (DC to fc!2). The location of
the first four harmonics is shown in the
diagram.

HIGH

SPEED DACs AND DDS SYSTEMS

125MSPS DDS SYSTEM (AD9850)
The AD9850 125MSPS DDS system
(Figure 6.6) uses a 32-bit phase accumulator which is truncated to 14-bits
(MSBs) before being passed to the
lookup table. The final digital output is
10-bits to the internal DAC. The
AD9850 allows the output phase to be
modulated using an additional register
and an adder placed between the output of the phase accumulator register
and the input to the lookup table. The
AD9850 uses a 5-bit word to control the
phase which allows shifting the phase

in increments of 180°, 90°, 45°, 22.5°,
11.25°, and any combination thereof.
The device also contains an internal
high speed comparator which can be
configured to accept the (externally)
filtered output of the DAC to generate a
low-jitter output pulse suitable for
driving the sampling clock input of an
ADC. The full scale output current can
be adjusted from 10 to 20mA using a
single external resistor, and the output
voltage compliance is + IV. Key specifications are summarized in Figure 6.7.

AD9850 CMOS 125MSPS "DDS/DAC SYNTHESIZER
BYTE LOAD

5

5
PHASE
CONTROL

8 BITSX5
DATA AND
CONTROL
INPUT
REGISTER
SERIAL LOAD

32

SIN
LOOKUP
TABLE

PHASE
ACCUMULATOR

1 BIT X40

10
10-BIT
DAC

WORD LOAD CLOCK

ANALOG
OUT
RSET

REFERENCE CLOCK IN
HIGH SPEED
COMPARATOR

Figure 6.6

6-7

HIGH SPEED DESIGN TECHNIQUES

AD9850 DDS/DAC SYNTHESIZER KEY SPECIFICATIONS
•

125MSPS Clock Rate

•

On-Chip 10-bit DAC and High Speed Comparator

•

DAC SFDR > 50dBc @ 40MHz Output

•

32-bit Frequency Tuning

•

5-bit Phase Modulation

•

Simplified Control In~erface: Byte-Parallel or Serial Load

•

+5V or +3.3V Supplies

•

380mW Dissipation @ 125MSPS on +5V Supply
(30mW Power-Down Mode)

•

28-Pin Shrink Small Outline Package (SSOP)

Figure 6.7

The frequency tuning (delta-phase
register input word) and phase modulation words are loaded into the AD9850
via a parallel or serial loading format.
The parallel load format consists of five
consecutive loads of an 8-bit control
word (byte). The first 8-bit byte controls
phase modulation (5-bits), power-down
enable (1-bit), and loading format (2bits). Bytes 2-5 comprise the 32-bit
frequency tuning word. The maximum
control register update frequency is

6-8

23MHz. Serial loading of the AD9850 is
accomplished via a 40-bit serial data
stream on a single pin. Maximum
update rate of the control register in
the serial-load mode is 3MHz.
The AD9850 consumes only 380mW of
power on a single +5V supply at a
maximum 125MSPS clock rate. The
device is available in a 28-pin surface
mount SSOP (Shrink Small Outline
Package).

HIGH

SPEED DACs AND DDS SYSTEMS

DDS SYSTEMS AS ADC CLOCK DRIVERS
DDS systems such as the AD9850
provide an excellent method of generating the sampling clock to the ADC,
especially when the ADC sampling
frequency must be under software
control and locked to the system clock
(see Figure 6.8). The true DAC output
current lout, drives a 200.0, 42MHz
lowpass filter which is source and load
terminated, thereby making the
equivalent load lOOn. The filter removes spurious frequency components
above 42MHz. The filtered output
drives one input of the AD9850 internal
comparator. The complementary DAC
output current drives a loon load. The
output of the 100kQ resistor divider
placed between the two outputs is

decoupled and generates the reference
voltage for the internal comparator.
The comparator output has a 2ns rise
and fall time and generates a TTU
CMOS-compatible square wave. The
jitter of the comparator output edges is
less than 20ps rms. True and complementary outputs are available if required.
In the circuit shown (Figure 6.8), the
total output rms jitter for a 40MSPS
ADC clock is 50ps rms, and the resulting degradation in SNR must be considered in wide dynamic range
applications.

USING DDS SYSTEMS AS ADC CLOCK DRIVERS
DACOUTPUT
42MHz
125 MHz

2000

AD9850

100kn

DDS/DAC

LPF

SYNTHESIZER
100kn
FREQ.
CONTROL

Ar--~-----------

]

CMOSADC
CLOCK DRIVERS

Figure 6.8
6-9

HIGH SPEED DESIGN TECHNIQUES

AMPLITUDE MODULATION IN A

DDS SYSTEM

Amplitude modulation in a DDS system
can be accomplished by placing a digital
multiplier between the lookup table and
the DAC input as shown in Figure 6.9.
Another method to modulate the DAC
output amplitude is to vary the reference voltage to the DAC. In the case of

the AD9850, the bandwidth of the
internal reference control amplifier is
approximately IMHz. This method is
useful for relatively small output amplitude changes as long as the output
signal does not exceed the +lV compliance specification.

AMPLITUDE MODULATION IN A DDS SYSTEM
fc

SIN
LOOKUP
TABLE

PHASE
ACCUMULATOR

AM

CAC

REGISTER

OUTPUT

MULTIPLIER

Figure 6.9

THE AD9830/9831

COMPLETE

The AD9830/9831 CMOS DDS systems
(see Figure 6.10) contain two frequency
registers and four phase registers
thereby allowing both frequency and
phase modulation. The registers are
loaded through a parallel microprocessor port. The DDS chips contain a 32bit phase accumuiator register, 12-bit
6-10

DDS SYSTEMS
sin ROM lookup table, and a 10-bit
DAC. The AD9830 operates at 50MSPS
and dissipates 250mW on the +5V
supply. The AD9831 operates at
25MSPS and dissipates 150mW on a
+5V supply and 35mW on +3V. Key
specifications for the devices are summarized in Figure 6.11.

HIGH

SPEED DACs AND DDS SYSTEMS

AD9830/9831 , 50/25MSPS COMPLETE DDS SYSTEMS
AVDD AGND REFOUT

DVDD DGND

FS ADJUST

REFIN

MCLK
COMP
FSELECT

lOUT

PHASE
ACCUMULATOR
(32-BIT)

AD9830

DO

015

WR

AO

A1

A2

PSELO

PSEL1

Figure 6.10

AD9830/9831 DDS SYSTEMS KEY SPECIFICATIONS
•

50MSPS (AD9830), 25MSPS (AD9831) Update Rate

•

Single +5V (AD9830), +5V/+3V (AD9831) Supply

•

32-bit Phase Accumulator, 12-bit Address Sine ROM

•

On Chip 10-bit DAC (70dB SFDR)

•

Two On-Chip Frequency Modulation Registers

•

Four On-Chip Phase Modulation Registers

•

On-Chip Reference

•

Power Dissipation: 250mW (AD9830),
150mW (AD9831 @ +5V), 35mW (AD9831 @ +3V)

•

48-pin TQFP
Figure 6.11
6 -11

HIGH SPEED DESIGN TECHNIQUES

SPURIOUS FREE DYNAMIC RANGE CONSIDERATIONS
IN

DDS

SYSTEMS

In many DDS applications, the spectral
purity of the DAC output is of primary
concern. Unfortunately, the measurement, prediction, and analysis of this
performance is complicated by a number of interacting factors.
Even an ideal N-bit DAC will produce
harmonics in a DDS system. The amplitude of these harmonics is highly dependent upon the ratio of the output
frequency to the clock frequency. This is
because the spectral content of the DAC
quantization noise varies as this ratio
varies, even though its theoretical rms
value remains equal to q/~12 (where q
is the weight of the LSB). The assumption that the quantization noise appears as white noise and is spread
uniformly over the Nyquist bandwidth
is simply not true in a DDS system (it is
more apt to be a true assumption in an
ADC-based system, because the ADC
adds a certain amount of noise to the
signal which tends to "dither" or randomize the quantization error. However, a certain amount of correlation
still exists). For instance, if the DAC
output frequency is set to an exact
submultiple of the clock frequency, then
the quantization noise will be concentrated at multiples of the output frequency, i.e., it is highly signal
dependent. If the output frequency is
slightly offset, however, the quantization noise will become more random,
thereby giving an improvement in the
effective SFDR.
This is illustrated in Figure 6.12, where
a 4096 point FFT is calculated based on

6 -12

digitally generated data from an ideal
12-bit DAC. In the left-hand diagram,
the ratio between the clock frequency
and the output frequency was chosen to
be exactly 32 (128 cycles of the
sinewave in the FFT record length),
yielding an SFDR of about 78dBc. In
the right-hand diagram, the ratio was
changed to 32.25196850394 (127 cycles
of the sinewave within the FFT record
length), and the effective SFDR is now
increased to 92dBc. In this ideal case,
we observed a change in SFDR of 14dB
just by slightly changing the frequency
ratio.
Best SFDR can therefore be obtained
by the careful selection of the clock and
output frequencies. However, in some
applications, this may not be possible.
In ADC-based systems, adding a small
amount of random noise to the input
tends to randomize the quantization
errors and reduce this effect. The same
thing can be done in a DDS system as
shown in Figure 6.13 (Reference 5). The
pseudo-random digital noise generator
output is added to the DDS sine amplitude word before being loaded into the
DAC. The amplitude of the digital noise
. is set to about 112 LSB. This accomplishes the randomization process at
the expense of a slight increase in the
overall output noise floor. In most DDS
applications, however, there is enough
flexibility in selecting the various
frequency ratios so that dithering is not
required.

HIGH

SPEED DACs AND DDS SYSTEMS

EFFECT OF RATIO OF CLOCK TO OUTPUT FREQUENCY
ON THEORETICAL 12-81T DAC SFDR USING 4096-POINT FFT

fc I fo = 32

fc I fo

=32.25196850394

O~--------~--------~
-1Of--+--------------~

-201---i-------------l
-30f--+----------~

-40f--+-----------~

-501---i------------l
-6 0I - - - i - - - - - - - - - - - - l
-70f.--+-----------~

-100 1---i--+--I--+-4--4.-...t-....f.....-.f.--I-+--t---I--I--+~

-110
-120 I

o

500

1000

1500

2000

0

500

1000

1500

2000

Figure 6.12

INJECTION OF DIGITAL DITHER IN A DDS SYSTEM TO
RANDOMIZE QUANTIZATION NOISE AND INCREASE SFDR

M

~

SINE
PHASE
DELTA
PHASE -;--:;. ACCUMU- ~ LOOKUP
TABLE
LATOR
REGISTER

~

ADDER

~

'i'

~

-

f--o

~

~

... fc

DAC

~

PSEUDORANDOM
NUMBER
GENERATOR

VN =

~

rms

Figure 6.13
6 -13

HIGH SPEED DESIGN TECHNIQUES

A non-ideal DAC will introduce several
other mechanisms of distortion. First,
the overall integral non-linearity of the
DAC transfer function will introduce
harmonic distortion. This distortion
behaves much like that produced by the
non-linearity of an amplifier. The
distortion due to the differential nonlinearity of the DAC is highly dependent upon the nature of the differential
non-linearity and is difficult to predict
mathematically. The third source of
DAC distortion are code-dependent
output glitches. In a DAC there is a
transient (or glitch) produced whenever
the DAC input code changes. This
glitch is usually worst at midscale,
where the DAC makes the transition
between the codes 1000 ... 000 and
0111 ... 111, and all the DAC bits must
switch. These glitches occur because of
the unequal turn-onlturn-off times of
the DAC current switches. They also
occur at 114 scale, 1/8 scale, etc., with
decreasing amplitude. Because the

glitches are code-dependent (hence
signal-dependent) they produce harmonics of the fundamental output DAC
frequency. For instance, each time the
sinewave crosses through mid-scale, a
glitch occurs, thereby producing a
second harmonic - since the sinewave
passes through midscale twice each
cycle. The harmonics produced by these
code-dependent glitches fold back into
the Nyquist bandwidth due to aliasing
and thereby affect the SFDR.
Low distortion high-speed DACs generally have a specification for the area of
the worst glitch (called glitch impulse
area). In general, the smaller the glitch
area, the better the distortion-but it is
difficult to mathematically relate the
distortion performance to the glitch
area. The glitch impulse area for low
distortion DACs is usually less than
30pV-sec. A typical midscale glitch
impulse is shown for the AD9721 DAC
in Figure 6.15.

CONTRIBUTORS TO DDS DAC DISTORTION
•

Resolution

•

Integral Non-Linearity

•

Differential Non-Linearity

•

Code-Dependent Glitches

•

Ratio of Clock Frequency to Output Frequency
(Even in an Ideal DAC)

•

Mathematical Analysis is Difficult!

Figure 6.14

6 -14

HIGH

SPEED DACs AND DDS

SYSTEMS

AD9720/AD9721 DAC MIDSCALE GLITCH SHOWS 1.34pV-s
NET IMPULSE AREA AND SETTLING TIME OF 4.5ns
SETTLING TIME ~ 4.5ns
NET GLITCH 1.34pV-s
PEAK GLITCH = 1.36pV-s

=

z

o
en
:>
a _.
:>
E

AD9720

N

lOUT

100 MHz
LPF

TeST CIRCUIT

5 ns/DIVISION

Figure 6.15

The best way to measure DAC performance is with a spectrum analyzer,
with a DDS system used to drive the
DAC (Figure 6.16). Because there are
nearly an infinite combination of possible clock and output frequencies,
SFDR is generally specified for only a
few selected combinations. One method
is to plot the SFDR as a function of
clock frequency for the output frequency slightly offset from 1/3 or 1/4
the clock frequency. The small frequency offset randomizes the quantization noise and also allows the distortion
products to be easily observed.

Note that for the output slightly offset
from fd3, the even harmonics will be
aliased very close to the output signal
as shown in Figure 6.17 . Similarly, for
the output slightly offset from fcf4, the
odd harmonics will fall close to the
output frequency (Figure 6.18).The
SFDR at fd3 is usually considered a
worse case condition and is often plotted as a function of clock frequency as
shown in Figure 6.19 for the AD9721
lO-bit, lOOMSPS TTL-compatible DAC.

6 -15

HIGH SPEED DESIGN TECHNIQUES

TEST SETUP FOR MEASURING DAC SFDR

l\

PARALLEL OR
SERIAL PORT

PC

DDS

/

/

N
/

N
LATCH

/

DAC

/

fo

STABLE
FREQUENCY
REFERENCE

fc

SPECTRUM
ANALYZER

Figure 6.16

LOCATION OF EVEN HARMONICS FOR
f o =fc /3-Llf
fo

ilf

I~

I

10

4

2

Figure 6.17
6-16

8

HIGH

SPEED DACs AND DDS SYSTEMS

LOCATION OF ODD HARMONICS FOR
fo=fc/4-~f
fo

~f

9

I~

I

7

3

5

Figure 6.18

SFDR OF AD972110-BIT DAC FOR
fo - fc 13 (BANDWIDTH: DC TO fc 12)

80

III

SF DR
(dBc)
70

60

50

40

~--~--~-----r--~----+---~

o

20

40

60

80

100

CLOCK FREQUENCY (MHz)

Figure 6.19

6 -17

HIGH SPEED DESIGN TECHNIQUES

HIGH SPEED

Low DISTORTION DAC ARCmTECTURES

Because of the emphasis in communications systems for DDS DACs with high
SFDR, much effort has been placed on
determining optimum DAC architectures. Practically all low distortion high
speed DACs make use of some form of
non-saturating current-mode switching.
A straight binary DAC with one current
switch per bit produces code-dependent
glitches as discussed above and is
certainly not the most optimum architecture (Figure 6.20). A DAC with one
current source per code level can be
shown not to have code-dependent
glitches, but it is not practical to implement for high resolutions. However,
this performance can be approached by
decoding the first few MSBs into a
"thermometer" code and have one
current switch per level. For example, a
5-bit thermometer DAC would have an
architecture similar to that shown in
Figure 6.21.
The input binary word is latched and
then decoded into 31 outputs which
drive a second latch. The output of the
second latch drives 31 equally weighted
current switches whose outputs are
summed together. This scheme effectively removes nearly all the codedependence of the output glitch. The
residual glitch that does occur at the
output is equal regardless of the output

6-18

code change and can be filtered. The
distortion mechanisms associated with
the full-decoded architecture are primarily asymmetrical output slewing, finite
switch turn-on and turn-off times, and
integral nonlinearity.
The obvious disadvantage of this type
of thermometer DAC is the large number of latches and switches required to
make a 12, 10, or even 8-bit DAC.
However, if this technique is used on
the 5 MSBs of an 8, 10, or 12-bit DAC,
a significant reduction in the codedependent glitch is possible. This
process is called segmentation and is
quite common in low distortion DACs.
Figure 6.22 shows a scheme whereby
the first 5 bits of a 10-bit DAC are
decoded as described above and drive
31 equally weighted switches. The last
5 bits are derived from binarily
weighted current sources. Equally
weighted current sources driving an R/
2R resistor ladder could be used to
derive the LSBs, however, this approach requires thin film resistors
which are not generally available on a
low-cost CMOS process. Also, the use of
R/2R networks lowers the DAC output
impedance, thereby requiring more
drive current to develop the same
voltage across a fixed load resistance.

HIGH

SPEED DACs AND DDS SYSTEMS

5-BIT BINARY DAC ARCHITECTURES

MSB

R (CAN BE EXTERNAL)

Figure 6.20

5-BIT "THERMOMETER" OR "FULLY-DECODED" DAC

MSB

0
()

"LSB

5-BIT
LATCH roo--

5-TO-31
DECODE
LOGIC

•
••
31
LINES

31-BIT
LATCH

III

••
•

31
CUR RENT
EQUAL
31
OUT PUT
LINES CURRENT
SWITCHES

r-----o

-

•

•

••

••

i

CLOCK
Figure 6.21

6 -19

HIGH SPEED DESIGN TECHNIQUES

10-BIT SE'GMENTED DAC
5
/

/

10

MSB
DECODE

31

31

/

/

/

/

10-BIT
LATCH

/

/

36-BIT
LATCH

FULLY
DECODED
MSB
DAC

f--

CUR RENT
OUT PUT
~

/
C LOCK

5

5

/

/

I

BINARY
LSB
DAC -

i

1
Figure 6.22

AD9850 10-81T CMOS CURRENT SWITCH DAC CORE
5

rT10

I

/

10-BIT
LATCH

BITS 1-5
DECODE

I

31

31

/

/

I

f-

BITS 6-9
DECODE

/

15
/

l-

SWITCHES

5-TO-31

4

31
CURRENT

320~A

47-BIT
LATCH
/

15
/

CURR ENT
OUTP UT

15
CURRENT
SWITCHES

()

FS
20~A

4-TO-15

LSB
CLOCK

1

1

10~A

1

i
Figure 6.23

6-20

1
CURRENT
SWITCH

=

10.23rnA

-

HIGH

The AD9850 internal 10-bit DAC uses
two major stages of segmentation as
shown in Figure 6.23. The first 5 bits
(MSBs) are fully decoded and drive 31
equally weighted current switches
(320pA each). The next 4 bits are
decoded into 15 lines which drive 15
current switches, each supplying 20pA
(1/16 the current supplied by each MSB
switch). The LSB is latched and drives
a single current switch which supplies
10pA (1/32 the current supplied by each
MSB switch). A total of 47 current
switches and latches are required to
implement this architecture.
The basic current switching cell is made
up of a differential PMOS transistor
pair as shown in Figure 6.24. The
differential pairs are driven with lowlevel logic to minimize switching tran-

SPEED DACs AND DDS SYSTEMS

sients and time skew. The DAC outputs
are symmetrical differential currents
which help to minimize even-order
distortion products (especially which
driving a differential output such as a
transformer or an op amp differential II
V converter).
The overall architecture of the AD9850
is an excellent tradeoff between power/
performance and allows the entire DDS
function to be implemented on a standard CMOS process with no thin film
resistors. Single-supply operation on
+3.3V or +5V makes the device extremely attractive for portable and low
power applications. The SFDR performance is typically 60, 55, and 45dBc for
output frequencies of 1, 20, and 40MHz,
respectively (clock frequency =
125MSPS).

PMOS TRANSISTOR CURRENT SWITCHES

•
Figure 6.24
6 -21

HIGH SPEED DESIGN TECHNIQUES

The AD9760 (lO-hit), AD9762 (l2-hit)
and AD9764 (l4-hit) lOOMSPS DACs
utilize the same basic switching core as
the AD9850. This family of DACs is
pin-compatible, and offers exceptional
AC and DC performance. They operate
on single +5V or +3V supplies and

contain on-chip latches, reference, and
are ideal for the transmit channel in
wireless hasestations, ADSUHFC
modems, and DDS applications. Key
specifications for the family are summarized in Figure 6.25.

AD9760/9762/9764 FAMILY OF 100MSPS DACs
•

•
•
•
•
•
•

Pin-Compatible 10-bit (AD9760), 12-bit (AD9762),
and 14-bit (AD9764)
SFDR for 15MHz Output: -60dSc
Low Glitch Impulse: 5pVsec
On-Chip Reference
Single +5V or +3V Supplies
Power Dissipation: 175mW @ 5V
Power-Down Mode: 30mW

Figure 6.25

6-22

HIGH

SPEED DACs AND DDS SYSTEMS

IMPROVING SFDR USING SAMPLE-AND-HOLD DEGLITCHERS
High-speed sample-and-hold amplifiers
(such as the AD9100 and AD9101) can
be used to de glitch DAC outputs as
shown in Figure 6.26. Just prior to
latching new data into the DAC, the
SHA is put into the hold mode so that
the DAC switching glitches are isolated
from the output. The switching transients produced by the SHA are codeindependent and occur at the clock
frequency and hence are easily filtered.

However, great care must be taken so
that the relative timing between the
SHA clock and the DAC update clock is
optimum. In addition, the distortion
performance of the SHA must be at
least 6 to lOdB better than· the DAC, or
no improvement in SFDR will be realized. Achieving good results using an
external SHA deglitcher becomes
increasingly more difficult as clock
frequencies approach lOOMSPS.

SAMPLE-AND-HOLD (SHA) USED AS DAC DEGLITCHER

The AD6742 is a 12-hit, 65MSPS low
distortion DAC with on-chip SHA
deglitcher designed for communications
applications. This DAC is fabricated on

the XFCB process and provides 75dB
SFDR for a 20MHz output. A functional
diagram is shown in Figure 6.27, and
key specifications in Figure 6.28.

6-23

HIGH SPEED DESIGN TECHNIQUES

AD6742 12-BIT, 65MSPS DEGLITCHED DAC
VREF

REFIN BYPASS

OACREF

VCC

GNO

VEE

VOUT

DREF

CURRENT

SOURCES/SWITCHES

DIGITAL INPUT STAGES AND LATCHES

011

01 0

09

08

07

06

05

04

03

02

01

DOC L 0 C K CL 0 CK

Figure 6.27

AD6742 12-BIT, 65MSPS DAC KEY SPECIFICATIONS
•

12-bit, 65MSPS Communications DAC

•

High SFDR: 75dB (min) @ 65MSPS and 20MHz Output

•

Fabricated on XFCB process

•

On-Chip Reference

•

Dual 5V Supplies, 800mW power dissipation

Figure 6.28
6-24

HIGH SPEED DACs AND DDS SYSTEMS

HIGH SPEED INTERPOLATING

DACs

Consider a DDS system which operates
at a clock frequency of 100MSPS and
outputs a 30MHz sinewave (see Figure
6.29). The first aliased (or image)
frequency occurs at 100-30 = 70MHz.
Assume we wish the anti aliasing filter
to attenuate this image frequency
component by 60dB. The filter must go
from a passband of 30MHz to 60dB
stopband attenuation over the transi-

tion band lying between 30 and 70MHz
(approximately one octave). A
Butterworth filter design gives 6dB
attenuation per octave for each pole.
Therefore, a minimum of 10 poles is
required to provide the desired attenuation. Filters become even more complex
as the transition band becomes narrower.

LPF REQUIRED TO REJECT IMAGE FREQUENCY
LPF

O~--------~

~

TRANSITION
BAND

~I
I

dB
fo
30MHz

~o

II

--------- ----------o

10

20

30

40

50

60

70

80

90

100

110

120

130

FREQUENCY (MHz)

Figure 6.29

In ADC-based systems, oversampling
can ease the requirements on the
antialiasing filter, and a sigma-delta
ADC has this inherent advantage. In a
DAC-based system (such as DDS), the
concept of interpolation can be used in a
similar manner. This concept is common in digital audio CD players, where
the basic update rate of the data from

the CD is about 44kSPS. "Zeros" are
inserted into the parallel data, thereby
increasing the effective update rate to
4-times, 8-times, or 16-times the fundamental throughput rate. The 4x, 8x, or
16x data stream is passed through a
digital interpolation filter which generates the extra data points. The high
oversampling rate moves the image
6-25

HIGH SPEED DESIGN TECHNIQUES

frequencies higher, thereby allowing a
less complex filter with a wider transition band.

additional data points. The response of
the digital filter relative to the 2-times
oversampling frequency is shown in
Figure 6.30. The analog antialiasing
filter transition zone is now 10 to
50MHz (the first image occurs at
2fc-fo=60-10=50MHz).

The same concept can be applied to a
high speed DDS DAC. Assume a traditional DAC is driven at an input word
rate of 30MSPS (see Figure 6.30). The
maximum realizable DAC output
frequency is about 10MHz. The image
frequency component at 30-10 =
20MHz must be attenuated by the
analog antialiasing filter, and the
transition band of the filter is 10 to
20MHz.

The AD977x is a 4-times oversampling
interpolating 10-bit DAC, and a simplified block diagram is shown in Figure
6.31. The device is designed to handle
10-bit input word rates up to about
30MSPS. The internal digital filter
consists of a 15-tap filter operating at
2fc followed by a 7-tap filter operating
at 4fc. The output word rate is
120MSPS, putting the image frequency
at 4fc-fo=120-10=110MHz. SFDR of
the DAC for a 10MHz output is approximately 60dBc.

Assume that we increase the update
rate to 60MSPS by inserting a "zero"
between each original data sample. The
parallel data stream is now 60MSPS
and is passed through the digital interpolation filter which computes the

ANALOG FILTER REQUIREMENTS FOR fo
fc 30MSPS AND fc 60MSPS

=

=

=10MHz:

fCLOCK = 30MSPS

dB

10

dB

20

----r

-- --

fo

-- --- -'

ANALOG

fCLOCK
......

........

= 60MSPS

1

LPF~

---//f
.....

"-

/ / IMAGE

IMAGE"""",
10

20

30

40

Figure 6.30
6-26

50

/

60

70

HIGH

SPEED DACs AND DDS SYSTEMS

INCREASING THE DAC THROUGHPUT RATE BY "K"
USING A PLL AND A DIGITAL INTERPOLATION FILTER
(INTERPOLATING DAC)

~

LATCH

10/

/

fc
PLL

DIGITAL
10/
INTERPOLATION
/
FILTER

LATCH

K·fc

rt-

DAC

LPF

=

TYPICAL APPLICATION. fc - 33MSPS
fo 10MHz
K=40R8

ll>

Figure 6.31

6-27

HIGH SPEED DESIGN TECHNIQUES

QPSK SIGNAL GENERATION USING DDS (AD9853)
tor. The quadrature modulators are
driven by the sine and cosine outputs
from the DDS section. The modulator
outputs are then recombined digitally
and then converted into analog by an
internal lO-bit DAC. The resulting
QPSK constellation is shown in Figure
6.33. This scheme of modulation is
quite common, and results in relatively
high noise immunity. Key specifications
for the AD9853 are given in Figure
6.34.

The AD9853 is a digital Quadrature
Phase Shift Keying (QPSK) modulator
useful in the 5 to 40MHz return path
transmitter in a hybrid fiber coax
(HFC) CATV cable modem application
(see Figure 6.32). This allows asynchronous data transfer over the HFC cable
plant. The device takes the serial QPSK
data input, splits it into an in-phase (I)
and quadrature (Q) signal. The I and Q
channel data is then filtered and passed
through a digital quadrature modula-

AD9853 DIGITAL QPSK MODULATOR
FIR
FILTER

INTERPOLATING
FILTER

SERIAL

MUX
QPSK
INPUT

10·BIT
DAC

FIR
FILTER

Q

____

I

r- -

-

INTERPOLATING
FILTER

..I

-

-

-

-

-

SIN

-

11------------CLOCKS

140MSPS DDS AND CONTROL FUNCTIONS

X4PLL
REF CLOCK INPUT

BURST
MODE
CONTROL

MASTER
RESET

FREQ.
UPDATE

Figure 6.32

6-28

WORD
LOAD
CLOCK

32·BIT FREQ.
TUNING AND
CONTROL WORD

SPEED DACs AND DDS SYSTEMS

HIGH

QPSK CONSTELLATION
Q

01

., ,

,,

/. 11
/

,,
/
/

/
/

,

/
/
/

,,

/
/

,,

/
/

00

•

,,

• 10

Figure 6.33

AD9853 DIGITAL QPSK MODULATOR KEY SPECIFICATIONS
•

Performs Transmit Function for QPSK 5-40MHz
Hybrid Fiber Coax (HFC) Return Path

•

Includes Raised Cosine Pulse-Shaping Filter
(Alpha 0.5) and Interpolation Filters

•

140MSPS Clock Frequency

•

46dBc SFDR @ 40MHz Output

•

+5V or +3.3V Operation

•

300mW Dissipation @ 125MSPS Clock Frequency
(30mW Power-Down Mode)

•

28-Pin SSOP Surface-Mount Package

=

Figure 6.34

6-29

HIGH SPEED DESIGN TECHNIQUES

REFERENCES
1.

R.E. Best, Phase-Locked Loops, McGraw-Hill, New York, 1984.

2.

F.M. Gardner, Phaselock Techniques, 2nd Edition, John Wiley,
New York, 1979.

3.

Phase-Locked Loop Design Fundamentals, Applications Note AN-535,
Motorola, Inc.

4.

The ARRL Handbook for Radio Amateurs, American Radio
Relay League, Newington, CT, 1992.

5.

Richard J. Kerr and Lindsay A. Weaver, Pseudorandom Dither for
Frequency Synthesis Noise, United States Patent Number 4,901,265,
February 13, 1990.

6.

Henry T. Nicholas, III and Henry Samueli, An Analysis of the Output
Spectrum of Direct Digital Frequency Synthesizers in the Presence of
Phase-Accumulator Truncation, IEEE 41st Annual Frequency Control
Symposium Digest of Papers, 1987, pp. 495-502, IEEE Publication No.
CH2427 -3/8 7/0000-495.

7.

Henry T. Nicholas, III and Henry Samueli, The Optimization of Direct
Digital Frequency Synthesizer Performance in the Presence of Finite Word
Length Effects, IEEE 42nd Annual Frequency Control Symposium
Digest of Papers, 1988, pp. 357-363, IEEE Publication No. CH25882/88/0000-357.
.

6-30

SECTION 7
HIGH SPEED HARDWARE DESIGN TECHNIQUES

•
•
•
•
•
•
•
•
•

Analog Circuit Simulation
Prototyping Analog Circuits
Evaluation Boards
Grounding in High Speed Systems
Power Supply Noise Reduction and Filtering
Power Supply Regulation/Conditioning
Thermal Management
EMI/RFI Considerations
Shielding Concepts

HIGH SPEED DESIGN TECHNIQUES

HIGH SPEED lIARDWARE DESIGN TECHNIQUES

SECTION 7
HIGH SPEED HARDWARE
DESIGN TECHNIQUES
Walt Kester, James Bryant, Walt Jung,
Adolfo Garcia, John McDonald, Joe Buxton
ANALOG CIRCUIT SIMULATION

Walt Kester, Joe Buxton
In recent years there has been much
pressure placed on system designers to
verify their designs with computer
simulations before committing to actual
printed circuit board layouts and hardware. Simulating complex digital
designs is extremely beneficial, and
very often, the prototype phase can be
eliminated entirely. However, bypassing the prototype phase in high-speed!
high-performance analog or mixedsignal circuit designs can be risky for a
number of reasons.
For the purposes of this discussion, an
analog circuit is any circuit which uses
ICs such as op amps, instrumentation
amps, programmable gain amps
(PGAs), voltage controlled amps
(VCAs), log amps, mixers, analog
multipliers, etc. A mixed-signal circuit
is an AID converter (ADC), DIA converter (DAC), or combinations of these
in conjunction with some amount of
digital signal processing which mayor
may not be on the same IC as the
converters.
Consider a typical IC operational
amplifier. It may contain some 20-40
transistors, almost as many resistors,
and a few capacitors. A complete SPICE
(Sim ulation Program with Integrated

Circuit Emphasis, see Reference 1)
model will contain all these components, and probably a few of the more
important parasitic capacitances and
spurious diodes formed by the various
junctions in the op-amp chip. For highspeed ICs, the package and wirebond
parasitics may also be included. This is
the type of model that the Ie designer
uses to optimize the device during the
design phase and is typically run on a
CAD workstation. Because it is a detailed model, it will be referred to as a
micromodel. In simulations, such a
model will behave very much like the
actual op-amp, but not exactly.
The IC designer uses transistor and
other device models based on the actual
process upon which the component is
fabricated. Semiconductor manufacturers invest considerable time and money
developing and refining these device
models so that the IC designers can
have a high degree of confidence that
the first silicon will work and that
mask changes (costing additional time
and money) required for the final
manufactured product are minimized.
However, these device models are not
published, neither are the IC
micromodels, as they contain propri7 -1

HIGH SPEED DESIGN TECHNIQUES

etary information which would be of
use to other semiconductor companies
who might wish to copy or improve on
the design. It would also take far too
long for a simulation ofa system containing several ICs (each represented
by its own micromodel) to reach a
useful result. SPICE micromodels of
analog ICs often fail to converge (especially under transient conditions), and
multiple IC circuits make this a greater
possibility.
For these reasons, the SPICE models of
analog circuits published by manufacturers or software companies are
macromodels (as opposed to
micromodels), which simulate the major
features of the component, but lack fine
detail. Most manufacturers of linear
ICs (including Analog Devices) provide
these macromodels for components such
as operational amplifiers, analog multipliers, references, etc. (Reference 2 and
3). These models represent approximations to the actual circuit, and parasitic

effects such as package capacitance and
inductance and PC board layout are
rarely included. The models are designed to work with various versions of
SPICE simulation programs such as
PSpice® (Reference 4) and run on
workstations or personal computers.
The models are simple enough so that
circuits using multiple ICs can be
simulated in a reasonable amount of
computation time and with good certain ty of convergence. Consequently,
SPICE modeling does not always reproduce the exact performance of a circuit
and should always be verified experimentally using- a carefully built prototype.
Finally, there are mixed-signal ICs
such as AID and DIA converters which
have no SPICE models, or if they exist,
the models do not simulate dynamic
performance (Signal-to-noise, effective
bits, etc.), and prototypes of circuits
using them should always be built.

SPICE SIMULATIONS:
MACROMODEL OR MICROMODEL?
METHODOLOGY ADVANTAGES

DISADVANTAGES

MACROMODEL

Ideal Elements
Fast
May Not Model All
Model the Device
Simulation
Characteristics
Behavior
Time, Easy to
Modify
MICROMODEL
Fully
Most Com plete Slow Simulation,
Characterized
Model
Difficulty in
Transistor Level
Convergence
Not Available to
Customers

Figure i.1
7-2

HIGH SPEED HARDWARE DESIGN TECHNIQUES

The ADSpice Model
The ADSpice model was developed to
advance the state-of-the-art in op amp
macromodelling and provide a tool for
designers to simulate accurately their
circuits. Previously, the dominant
model architecture was the Boyle model
(Reference 3). However, this model was
developed over 20 years ago and does
not accurately model many of today's
higher speed amplifiers. The primary
reason for this is that the Boyle model
has only two frequency shaping poles
and no zeroes. In contrast, the ADSpice
model has an open architecture that
allows for unlimited poles and zeroes,
leading to much more accurate AC and
transient responses.

The ADSpice model is comprised of
three main portions: the input and gain
stage, the pole/zero stages, and the
output stage. The input stage shown in
Figure 7.2 uses the only two transistors
in the entire model. These are needed
to model properly an op amp's differential input stage characteristics. Although the example here uses NPN
transistors, the input stage can easily
be modified to include PNP, JFET, or
CMOS devices. The rest of the input
stage uses simple SPICE elements such
as resistors, capacitors, and controlled
sources.

ADSpice INPUT AND GAIN STAGE MODEL
v+
OPEN LOOP GAIN = gm1 • R7

IN· 1
R7

IN+

C3

2

Figure 7.2
7-3

HIGH SPEED DESIGN TECHNIQUES

An example of a controlled source is
gm 1 in the gain stage, which is a voltage controlled current source.·lt senses
the differential collector voltage from
the input stage and converts that to a
current. When the current flows
through R7, a single-ended voltage is
produced. By making the product of
gm 1 and R7 equal to the open loop
gain, the entire open-loop gain is produced in the gain stage, which means
that all other stages are set to unity
gain. This leads to significant flexibility
in adding and deleting stages.

Following the gain stage are an unlimited number of pole / zero stages and
their combinations. The typical topol-

ogy of these stages is shown in Figure
7.3, which is similar to the gain stage.
The main difference is that now the
product of gm2 times R8 is equal to
unity. The pole or zero frequency is set
by the parallel combination of the
resistor and capacitor, R8-C4 for the
pole and Rg-C5 for the zero. Because
these stages are unity gain, any number of them can be added or deleted
without affecting the low frequency
response of the model. Instead, the high
frequency gain and phase response can
be tailored to match accurately the
actual amplifier's response. The benefits are especially apparent in closed
loop pulse response and stability analysis.

POLE AND ZERO STAGE
C5

Rg

gm2
R8

C4

-+ E1

R10

gm2 R8 = 1

E1 [
EREF

EREF

POLE

ZERO

Figure i.3
7-4

a=1

R10
Rg+R10

HIGH SPEED IlARnWARE DESIGN TECHNIQUES

cant improvement over the Boyle model
because now the power consumption of
the circuit under load can be analyzed
accurately. Furthermore, circuits that
use the supply currents for feedback
can also be sim ula ted.

The output stage in Figure 7.4 not only
models the open loop output impedance
at DC but with the inclusion of an
inductor also models the rise in im pedance at high frequencies. Additionally,
the output current is correctly reflected
in the supply currents. This is a signifi-

OUTPUT STAGE
v+

R11
R13

07

08

R14
010

09

R12

vOUTPUT IMPEDANCE = R11 + R12 + sLO

2

Figure 7.4

As an illustration of using the ADSpice

model to predict circuit performance,
the AD847 op amp (50MHz unity gainbandwidth product) output was loaded
in a 65pF capacitor and the response
measured (both in ADSpice and in the
circuit). The results shown in Figure 7.5

illustrate good correlation between the
simulated and the actual response. As
an additional example, extra parasitic
capacitances were added as shown in
Figure 7.6, and the simulated and
actual responses com pared. Again, note
the excellent general agreement.

7-5

HIGH SPEED DESIGN TECHNIQUES

AD847 PULSE RESPONSE
'oo.. r················································

'"~f T .~------,--'
.,~"

-200mV+ M"" - ....... -- .... -t-- ........... _ ..... + ........... -- .... ---+- ........................ + .... ..
Ons
lOOns
200ns
300ns
400n.
Q

v(3)

Time

(A)

(8)

(C)

Properly laid out PC board and simulation agree closely

Figure 7.5

PC BOARD PARASITICS WILL ALTER THE RESULTS
m ..

r···················································...

.

,~,t

omvt .

.

'\

-200mV+-" •• " ..... 0_"" +- ........ ____ ...... + 0- __ .. _0 .... " ..... +_ 0_." .0 ........... +_ ..
Ons
lOOns
200ns
300ns
400ns
o v(3)

Time

(A)

(8)

• Parasitic capacitances worsen the circuit's response
• Properly modelling the parasitics in SPICE yields good results

Figure 7.6
7-6

(C)

HIGH SPEED llARDWARE DESIGN TECHNIQUES

Other Features of ADSpice Models
fiers, analog multipliers, voltage references, analog switches, multiplexers,
matched transistors, and buffers. A
complete set of ADSpice models is
available from Analog Devices upon
request.

In addition to offering models of op
amps (both voltage and current feedback), which allow simulation of AC
and DC performance, Analog Devices
has included noise in many of its amplifier models. The capability to model a
circuit's noise performance in SPICE
can be appreciated by anyone who has
tried to analyze noise by hand. A complete analysis is a very involved and
tedious task which requires calculating
all the individual noise contributors and
reflecting them to the input or output.
The procedure is further complicated by
the fact that noise gain is generally a
function of frequency and can significantly affect results ifnot carefully
considered.

ADSpice will give good approximations
to actual performance, if used correctly.
However, the user must include the
external com ponen ts and parasi tics
which may affect the device performance in the circuit. This becomes a
difficult task at frequencies much above
100MHz, and caution must be used in
interpreting the simulation results.
There is no substitute for prototyping
at these frequencies.

To greatly simplify this task, the
ADSpice model was enhanced to include noise generators which accurately
predict the broadband and Ilf noise of
the actual amplifier. Noise is currently
modeled in a number of ADI op amps,
variable gain amplifiers, and voltage
references. For further discussion on
the noise model details, see Reference

While pulse and frequency response can
be successfully simulated using the
ADSpice models, distortion performance
cannot be predicted since non-linear
effects are not included in the models.
As mentioned previously, models for
ADCs and DACs are not available due
to the difficulty in modeling their AC
performance.

2.
In addition to amplifiers, ADSpice
models exist for instrumentation ampli-

7-7

HIGH SPEED DESIGN TECHNIQUES

SUMMARY: AOSpice FEATURES
•

Transistor-Level Input Stage Model

•

Unlimited Poles and Zeros

•

Noise is Included in Some Models

•

Distortion is not Modeled

•

Over 500 Models Exist for:
•
•
•
•
•
•

•

Am plifiers
Instrumentation Amplifiers
Analog Multipliers
Voltage References
VCAs
Multiplexers and Switches

But There is no Substitute for a Good Prototype!!

Figure 7.7

PROTOTYPING TECHNIQUES

James Bryant, Walt Kester
The basic principle of a breadboard or
prototype is that it is a temporary
structure, designed to test the performance of a circuit or system, and must
therefore be easy to modify.
There are many commercial
prototyping systems, but almost all of
them are designed to facilitate the
prototyping of digital systems, where
noise immunities are hundreds of
millivolts or more. Non copper-clad
Matrix board, Vectorboard, wire-wrap,
and plug-in breadboard systems are,
without exception, unsuitable for high
performance or high frequency analog
prototyping because their resistance,
inductance, and capacitanCe are too
high. Even the use of standard IC
7-8

sockets is inadvisable in many
prototyping applications.
An important consideration in selecting
a prototyping method is the requirement for a large-area ground plane.
This is required for high frequency
circuits as well as low speed precision
circuits, especially when prototyping
circuits involving ADCs or DACs. The
differentiation betweep. high-speed and
high-precision mixed-signal circuits is
difficult to make. For example, 16+ bit
ADCs (and DACs) may operate on high
speed clocks (> 10MHz) with rise and
fall times of less than a few nanoseconds, while the effective throughput
...

1

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l>1:J

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VJ. l>llv ,",VIJ. V v.1 \.Iv.1" .1.u.Q.J

IVv .LvOO

,,~~u.~.L

lOOkSPS. Successful prototyping of

HIGH SPEED IIAru>WARE DESIGN TECHNIQUES

these circuits requires that equal
attention be given to good high-speed
and high-precision circuit techniques.
The simplest technique for analog
prototyping uses a solid copper-clad
board as a ground plane (Reference 5
and 6). The ground pins of the ICs are
soldered directly to the plane, and the
other components are wired together
above it. This allows HF decoupling
paths to be very short indeed. All lead
lengths should be as short as possible,
and signal routing should separate
high-level and low-level signals. Connection wires should be located close to
the surface of the board to minimize the
possibility of stray inductive coupling.
In most cases, 18-gauge or larger
insulated wire should be used. Parallel
runs should not be "bundled" because of
possible coupling. Ideally the layout (at
least the relative placement of the
components on the board) should be
similar to the layout to be used on the
final PCB. This approach is often
referred to as deadb ug prototyping
because the lCs are often mounted
upside down with their leads up in the
air (with the exception of the ground

pins, which are bent over and soldered
directly to the ground plane). The
upside-down lCs look like deceased
insects, hence the name.
Figure 7.8 shows a hand-wired breadboard using two high speed op amps
which gives excellent performance in
spite of its lack of esthetic appeal. The
IC op amps are mounted upside down
on the copper board with the leads bent
over. The signals are connected with
short point-to-point wiring. The characteristic impedance of a wire over a
ground plane is about 120.0, although
this may vary as much as ±40% depending on the distance from the plane.
The decoupling capacitors are connected directly from the op amp power
pins to the copper-clad ground plane.
When working at frequencies of several
hundred MHz, it is a good idea to use
only one side of the board for ground.
Many people drill holes in the board
and connect both sides together with
short pieces of wire soldered to both
sides of the board. If care is not taken,
however, this may result in unexpected
ground loops between the two sides of
the board, especially at RF frequencies.

7-9

HIGH SPEED DESIGN TECHNIQUES

"DEADBUG" PROTOTYPE

Figure 7.8

Pieces of copper-clad board may be
soldered at right angles to the main
ground plane to provide screening, or
circuitry may be constructed on both
sides of the board (with connections
through holes) with the board itself
providing screening. In this case, the
board will need standoffs at the corners
to protect the components on the underside from being crushed.
When the components of a breadboard
of this type are wired point-to-point in
the air (a type of construction strongly
advocated by Robert A. Pease of National Semiconductor (Reference 6) and
sometimes known as "bird's nest"
construction) there is always the risk of
the circuitry being crushed and resulting shori-circuits. Also, if the circuitry
rises high above the ground plane, the
7 -10

screening effect of the ground plane is
diminished, and interaction between
different parts of the circuit is more
likely. Nevertheless, the technique is
very practical and widely used because
the circuit may easily be modified
(assuming the person doing the modifications is adept at using a soldering
iron, solder-wick, and a solder-sucker).
Another prototype breadboard is shown
in Figure 7.9. The single-sided copperclad board has pre-drilled holes on 0.1"
centers (Reference 7). Power busses are
at the top and bottom of the board. The
decoupling capacitors are used on the
power pins of each Ie. Because of the
loss of copper area due to the pre-drilled
holes, this technique does not provide
as lo\v a ground impedance as a completely covered copper-clad board.

HIGH SPEED IIARnWARE DESIGN TECHNIQUES

"DEADBUG" PROTOTYPE USING PRE-DRILLED
SINGLE-SIDED COPPER-CLAD BOARD

Figure 7.9

In a variation of this technique, the les
and other components are mounted on
the non-copper-clad side of the board.
The holes are used as vias, and the
point-to-point wiring is done on the
copper-clad side of the board. The
copper surrounding each hole used for a
via must be drilled out to prevent
shorting. This approach requires that
all Ie pins be on 0.1" centers. Low
profile sockets can be used for low
frequency circuits, and the socket pins
allow easy point-to-point wiring.
There is a commercial breadboarding
system which has most of the advantages of the above techniques (robust
ground, screening, ease of circuit alteration, low capacitance and low inductance) and several additional

advantages: it is rigid, components are
close to the ground plane, and where
necessary, node capacitances and line
impedances can be calculated easily.
This system is made by Wainwright
Instruments and is available in Europe
as "Mini-Mount" and in the USA (where
the trademark "Mini-Mount" is the
property of another company) as
"Solder-Mount" (Reference 8).
Solder-Mount consists of small pieces of
PCB with etched patterns on one side
and contact adhesive on the other.
These pieces are stuck to the ground
plane, and components are soldered to
them. They are available in a wide
variety of patterns, including
ready-made pads for IC packages of all
sizes from 8-pin SOICs to 64-pin DILs,
7-11

HIGH SPEED DESIGN TECHNIQUES

strips with solder pads at intervals
(which intervals range from 0.040" to
0.25", the range includes strips with
0.1" pad spacing which may be used to
mount DIL devices), strips with conductors of the correct width to form
microstrip transmission lines (50n,
60n, 75n or lOOn) when mounted on
the ground plane, and a variety of pads
for mounting various other components.

Self-adhesive tinned copper strips and
rectangles (LO-PADS) are also available as tie-points for connections. They
have a relatively high capacitance to
ground and therefore serve as lowinductance decoupling capacitors. They
come in sheet form and may be cut with
a knife or scissors. A few of the many
types of Solder-Mount building-block
components are shown in Figure 7.10.

SAMPLES OF "SOLDER-MOUNT" COMPONENTS

Figure 7.10

7 -12

HIGH SPEED IlARDWARE DESIGN TECHNIQUES

The main advantage of Solder-Mount
construction over "bird's nest" or
"deadbug" is that the resulting circuit is
far more rigid, and, if desired, may be
made far smaller (the latest SolderMounts are for surface-mount devices
and allow the construction of breadboards scarcely larger than the final PC
board, although it is generally more
convenient if the prototype is somewhat
larger). Solder-Mount is sufficiently
durable that it may be used for small
quan ti ty production as well as
prototyping.

Figure 7.11 shows an example of a
2.5GHz phase-Iocked-Ioop prototype
built with Solder-Mount. This is a high
speed circuit, but the technique is
equally suitable for the construction of
high resolution low frequency analog
circuitry. A particularly convenient
feature of Solder-Mount at VHF is the
ease with which it is possible to make a
transmission line.

"SOLDER-MOUNT" PROTOTYPE

Figure 7.11

7-13

HIGH SPEED DESIGN TECHNIQUES

If a conductor runs over a ground plane,
it forms a microstrip transmission line.
The Solder-Mount components include
strips which form microstrip lines when
moun ted on a ground plane (they are
available with impedances of 50n, 60n,
75n, and lOOn). These strips may be
used as transmission lines, for impedance matching, or simply as power
buses. (Glass fiber/epoxy PCB is somewhat lossy at VHF and UHF, but the
losses will probably be tolerable if
microstrip runs are short.)
Both the "deadbug" and the "SolderMoun t" prototyping techniques become
somewhat tedious for complex analog or
mixed-signal circuits. Larger circuits
are often better prototyped using more
formal layout techniques.
An approach to prototyping more
complex analog circuits is to actually
layout a double-sided board using CAD
techniques. PC-based software layout
packages offer ease of layou t as well as
schematic capture to verify connections
(Reference 9). Although most layout
software has some amount of autorouting capability, this feature is best
left to digital designs. After the components are placed in their desired positions, the interconnections should be
routed manually following good analog
layou t guidelines. After the layout is
complete, the software verifies the
connections per the schema tic diagram
net list.

7 -14

Many design engineers find that they
can use CAD techniques to layout
simple boards themselves, or work
closely with a layout person who has
experience in analog circuit boards. The
result is a pattern-generation tape (or
Gerber file) which would normally be
sent to a PCB manufacturing facility
where the final board is made. Rather
than use a PC board manufacturer,
however, automatic drilling and milling
machines are available which accept
the PG tape directly (Reference 10).
These systems produce single and
double-sided circuit boards directly by
drilling all holes and using a milling
technique to remove copper and create
insulation paths and finally, the finished board. The result is a board very
similar to the final manufactured
double-sided PC board, the chief exception being that there is no "platedthrough" hole capability, and any "vias"
between the two layers of the board
must be wired and soldered on both
sides. Minimum trace widths of 25 mils
(1 mil = 0.001") and 12 mil spacing
between traces are standard, although
smaller trace widths can be achieved
with care. The minimum spacing between lines is dictated by the size of the
milling bit, typically 10 to 12 mils. An
exam pIe of such a prototype board is
shown in Figure 7 .12 (top view) and
Figure 7.13 (bottom view).

HIGH SPEED HARDWARE DESIGN TECHNIQUES

"MILLED" PROTOTYPE - TOP VIEW

Figure 7.12

"MILLED" PROTOTYPE - BOTTOM VIEW

Figure 7.13
7-15

HIGH SPEED DESIGN TECHNIQUES

Ie sockets can degrade the performance
of high speed or high precision analog
les. Although they make prototyping
easier, even low-profile sockets often
introduce enough parasitic capacitance
and inductance to degrade the performance of the circuit. If sockets must be
used in high speed circuits, an Ie socket
made of individual pin sockets (sometimes called cage jacks) mounted in the
ground plane board may be acceptable
(clear the copper, on both sides of the
board, for about 0.5mm around each
ungrounded pin socket and solder the
grounded ones to ground on both sides
of the board). Both capped and uncapped versions of these pin sockets are
available (AMP part numbers 5330808-3, and 5-330808-6, respec-

tively). The pin sockets protrude
through the board far enough to allow
point-to-point wiring interconnections
between them (see Figure 7.14).
The spring-loaded gold-plated contacts
within the pin socket makes good
electrical and mechanical connection to
the Ie pins. Multiple insertions, however, may degrade the performance of
the pin socket. The uncapped versions
allow the Ie pins to extend out the
bottom of the socket. After the prototype is functional and no further
changes are to be made, the Ie pins can
be soldered directly to the bottom of the
socket, thereby making a permanent
and rugged connection.

PIN SOCKETS (CAGE JACKS) HAVE MINIMUM PARASITIC
RESISTANCE, INDUCTANCE, AND CAPACITANCE

PCB DIELECTRIC

PCB DIELECTRIC

"'-CAPPED OR UNCAPPED
VERSIONS AVAILABLE

Figure 7.14
7 -16

HIGH SPEED lIARDWARE DESIGN TECHNIQUES

The prototyping techniques discussed
so far have been limited to single or
double-sided PC boards. Multilayer PC
boards do not easily lend themselves to
standard prototyping techniques. If
multilayer board prototyping is required, one side of a double-sided board
can be used for ground and the other
side for power and signals.Point-topoint wiring can be used for additional
runs which would normally be placed
on the additional layers provided by a
multi-layer board. However, it is difficult to control the impedance of the
point-to-point wiring runs, and the high
frequency performance of a circuit
proto typed in this manner may differ

significantly from the final multilayer
board.
Other difficulties in prototyping may
occur with op amps or other linear
devices having bandwidths greater
than a few hundred megahertz. Small
variations in parasitic capacitance
(< 1pF) between the prototype and the
final board may cause subtle differences in bandwidth and settling time.
Oftentimes prototyping is done with
DIP packages, when the final production package is an SOIC. This can
account for differences between prototype and final PC board performance.

EVALUATION BOARDS

Walt Kester
Most manufacturers of analog ICs
provide evaluation boards (usually at a
nominal cost) which allow customers to
evaluate products without constructing
their own prototypes. Regardless of the
product, the manufacturer has taken
proper precautions regarding grounding, layout, and decoupling to ensure
optim um device performance. The
artwork or CAD file is usually made
available free of charge, should the
customer wish to copy the layout directly or make modifications to suit the
application.

7.17, respectively, show the top and
bottom side of the PCB. The amplifier is
connected in the non-inverting mode.
The top side (Figure 7.16) shows the top
side of the SOIC package along with
input and output SMA connectors.
Notice that the ground plane is cut
away around the SOIC in order to
minimize parasitic capacitance. The
bottom side of the board (Figure 7.17)
shows the surface mount resistors and
capacitors which comprise the op amp
gain-setting and power supply
decoupling circuits, respectively.

Figure 7.15 shows the schematic for the
AD8001 (SOIC package) 800MHz op
amp evaluation board. Figures 7.16 and

7-17

HIGH SPEED DESIGN TECHNIQUES

AD8001AR (SOIC) 800M Hz OP AMP: NON-INVERTING
MODE EVALUATION BOARD SCHEMATIC

O.01J,l F
1000pF

OUT

IN

~OOPF
O.01J,l F

+

10J,lF

Figure 7.15

AD8001AR (SOIC) EVALUATION BOARD - TOP VIEW

•

•

•

•

•

•

•

•

•

Figure 7.16
7 -18

•

•

HIGH SPEED IlARDWARE DESIGN TECHNIQUES

AD8001AR (SOle) EVALUATION BOARD - BOTTOM VIEW

Figure 7.17

In high speedlhigh precision Ies, special attention must be given to power
supply decoupling. For example, fast
slewing signals into relatively low
impedance loads produce high speed
transient currents at the power supply
pins of an op amp. The transient currents, in turn, produce corresponding
voltages across any parasitic impedance
which may exist in the power supply
traces. These voltages, in turn, may
couple to the amplifier output because
of the op amp's finite power supply
rejection at high frequencies.
A three-capacitor decoupling scheme
was chosen for the AD8001 evaluation
board to ensure a low impedance path
to ground at all transient frequencies.
The highest frequency transients are

shunted to ground by the lOOOpF and
the O.OlllF ceramic capacitors. These
are located as close to the power supply
pins as possible to minimize any series
inductance and resistance. Because the
devices are surface mount, there is
minimum stray inductance and resistance in the path to the ground plane.
The lower frequency transient currents
are shunted to ground by the lOllF
tantalum capacitors.
The input and output signal traces are
of the AD8001 evaluation board are
50Q microstrip transmission lines.
Notice that there is considerable continuous ground plane area on both sides
of the PCB. Plated-through holes connect the top and bottom side ground
planes at several points in order to
7-19

HIGH SPEED DESIGN TECHNIQUES

maintain low impedance ground continuity at high frequencies.
Evaluation boards can range from
relatively simple ones (op amps) for
example) to rather complex ones for
mixed-signal lCs such as AID converters. ADC evaluation boards often have
on-board memory and DSPs for analyzing the ADC performance. Software is
often provided with these more complex
evaluation boards so that they can
interface with a personal computer to
perform complex signal analysis such
as histogram and FFT testing.
Complete evaluations of ADCs requires
the use of FFTs to fully characterize the
devices AC performance. A typical test

setup is shown in Figure 7.18. The
manufacturer's evaluation board is
used as a means for interfacing to the
ADC. The evaluation board is designed
to allow easy access to the ADC inputs
and outputs while also providing a good
layout (including all necessary references) buffer amplifiers) and
decoupling). The evaluation board
allows the ADC output data to be
captured on a parallel output connector.
Most ADC evaluation boards contain an
on-board DAC which can be used to
check the functionality of the ADC, but
is somewhat limited in performing
meaningful AC testing. A block diagram of the AD9042 (12-bits, 41MSPS)
evaluation board is shown in Figure
7.19, and a photo in Figure 7.20.

TEST SETUP REQUIRED TO EVALUATE HIGH SPEED ADCs
POWER
SUPPLIES

{
LOW PHASE
JITTER
SINEWAVE
SOURCE

~

BANDPASS
FILTER

ADCON

~ EVALUATION

BOARD

MEMORY
OR LOGIC
ANALYZER

/

/
~

CLOCK
LOW PHASE
JITTER
SAMPLING
CLOCK
SOURCE

fs

I

V

PC

I
MONITOR

Figure 7.18
7-20

PARALLEL OR
SERIAL PORT

HIGH SPEED IIARDWARE DESIGN TECHNIQUES

AD904212-BIT, 41MSPS ADC EVALUATION BOARD
FUNCTIONAL DIAGRAM
74ASOO

74ASOO

XTAL
OSC
40.96MHz

CK
AD9042

100n

ENCODE
ENCODE

T1 ·1T
MINICIRCUITS

•
•
•

74AC574
REGISTERS
(2)

499n

Figure 7.19

AD9042 EVALUATION BOARD - TOP VIEW

•
Figure 7.20
7-21

HIGH SPEED DESIGN TECHNIQUES

The most complex part of the problem
is usually designing the buffer memory
module. A high speed logic analyzer is
one method of capturing the ADC
output data, and interfaces easily to the
ADC evaluation board. Data from the
logic analyzer can be loaded into a PC
through either parallel or serial ports.
Once the ADC data is inside the PC,
software packages such as Mathcad can
be used to perform the actual FFT.
Another alternative is to use a commercially-available data acquisition module
that plugs directly into a card slot of
the PC. These modules come complete
with FFT and other ADC test software,
but are not easily portable from one PC
to another and are generally difficult to
interface with laptop computers.
Although fast and relatively low power
memories (FIFOs) are available commercially, designing a buffer memory,
the interfaces to the ADC and the PC,
and the necessary software can be a
time-consuming proj ect. Analog Devices
has designed a simple 16-bit by 16k
deep 100MHz memory board (3 x 4
inches) and the necessary software to

7-22

allow high speed ADC evaluation
boards to interface directly with the
parallel printer port of most PCs. The
core of the memory design is the
IDT72265 16k by 18-bit wide FIFO or
alternately, the IDT72255 is an 8k pin
compatible device which may be substituted if the deeper memory is not
required.
This FIFO chip features fully independent 110 ports that allow data to be
loaded at up to 100MSPS and downloaded at the rate of a parallel printer
port. Since the ports are independent,
both can operate simultaneously, i.e.,
data may be read out while new data is
being written. The chip takes care of all
addressing, overhead and much of the
hand-shaking for these operations.
Included is circuitry that prevents
unread data from being overwritten,
eliminating the need for extensive write
control circuitry.
A photograph of the Fifo Memory board
is shown in Figure 7.21, and Figure
7.22 shows it connected to the AD9042
evaluation board.

HIGH SPEED HARDWARE DESIGN TECHNIQUES

BUFFER MEMORY FIFO BOARD - TOP VIEW

Figure 7.21

MEMORY BOARD I AD9042 EVALUATION BOARD

Figure 7.22
7-23

HIGH SPEED DESIGN TECHNIQUES

Using this hardware and Windowsbased software to capture the ADC
data, many testing possibilities exist.
Figure 7.23 shown a time-domain plot
of data captured using the fifo memory.
Once the data is captured, FFT analysis (Figure 7.24) or DNL histograms
(Figure 7.25) are easily generated.
In summary, good analog designers
utilize as many tools as possible to
ensure that the final system design
performs correctly. The first step is the
intelligent use oflC macromodels,
where available, to simulate the circuit.
The second step is the construction of a
prototype board to further verify the

design and the simulation. The final
PCB layout should be then be based on
the prototype layout as much as possible.
Finally, evaluation boards can be
extremely useful in evaluating new
analog les, and allow designers to
verify the IC performance with a minimum amount of effort. The layout of
the components on the evaluation board
can serve as a guide to both the prototype and the final PC board layout.
Gerber files are generally available for
all evaluation board layouts and may
be obtained at no charge.

DATA CAPTURE PC OUTPUT DISPLAY

Figure 7.23

7-24

HIGH SPEED HARDWARE DESIGN TECHNIQUES

FFTOUTPUT

Figure 7.24

DNL HISTOGRAM

Figure 7.25
7-25

HIGH SPEED DESIGN TECHNIQUES

REFERENCES: SIMULATION, PROTOTYPING, AND
EVALUATION BOARDS
1.

Paolo Antognetti and Guiseppe Massobrio, Ed, Semiconductor Device
Modeling with SPICE, McGraw Hill, 1988.

2.

Amplifier Applications Guide, Section 13, Analog Devices, Inc., Norwood,
MA,1992.

3.

Boyle, et aI, Macromodelling of In tegra ted Circuit Operational Amplifiers,
IEEE Journal of Solid State Circuits,Vol. SC-9, no.6, December 1974.

4.

PSpice@ Simulation software. MicroSim Corporation, 20 Fairbanks, Irvine,
CA 92718, 714-770-3022

5.

Jim Williams, High Speed Amplifier Techniques, Linear Technology
Application Note 47, August, 1991.

6.

Robert A. Pease, Troubleshooting Analog Circuits, ButterworthHeinemann, 1991.

7.

Vector Electronic Company, 12460 Gladstone Ave., Sylmar, CA 91342,
Tel. 818-365-9661, Fax. 818-365-5718.

8.

Wainwright Instruments Inc., 69 Madison Ave., Telford, PA, 18969-1829,
Tel. 215-723-4333, Fax. 215-723-4620.
Wainwright Instruments GmbH, Widdersberger Strasse 14,
DW-8138 Andechs-Frieding, Germany. Tel: +49-8152-3162,
Fax: +49-8152-40525.

9.

Schematic Capture and Layout Software:
PADS Software, INC, 165 Forest St., Marlboro, MA, 01752 and
ACCELTechnologies, Inc., 6825 Flanders Dr., San Diego, CA, 92121

10.

Prototype Board Cutters:
LPKF CAD/CAM Systems, Inc., 1800 NW 169th Place,
Beaverton, OR, 97006 and
T-Tech, Inc., 5591-B New Peachtree Road, Atlanta, GA, 34341

11.

Howard W. Johnson and Martin Graham, High-Speed Digital Design,
PTR Prentice Hall, 1993.

12.

Practical Analog Design Techniques, Analog Devices, 1995.

7-26

HIGH SPEED lIARDWARE DESIGN TECHNIQUES

GROUNDING IN HIGH SPEED SYSTEMS

Walt Kester, James Bryant
The importance of-maintaining a low
impedance large area ground plane is
critical to practically all analog circuits
today, especially at high speeds. The
ground plane not only acts as a low
impedance return path for high frequency currents but also minimizes
EMIIRFI emissions. Because of the
shielding action of the ground plane,
the circuits susceptibility to external
EMIIRFI is also reduced.
All I C ground pins should be soldered
directly to the ground plane to minimize series inductance. Power supply
pins should be decoupled to the ground
plane using low inductance ceramic
surface mount capacitors. If throughhole mounted ceramic capacitors must
be used, their leads should be less than
Imm. Ferrite beads may be also required.
The ground plane allows the impedance
of PCB traces to be controlled, and high
frequency signals can be terminated in
the characteristic impedance of the
trace to minimize reflections when
necessary.
Each PCB in the system should have at
least one complete layer dedicated to
the ground plane. Ideally, a doublesided board should have one side dedicated to ground and the other side for
interconnections. In practice, this is not
possible, since some of the ground plane
will certainly have to be removed to
allow for signal and power crossovers
and vias. Nevertheless, as much area
as possible should be preserved, and at
least 75% should remain. After completing an initial layout, the ground layer
should be checked carefully to make
sure there are no isolated ground

"islands." IC ground pins located in a
ground "island" have no current return
path to the ground plane.
The best way of minimizing ground
impedance in a multicard system is to
use another PCB as a backplane for
interconnections between cards, thus
providing a continuous ground plane to
the mother card. The PCB connector
should have at least 30-40% of its pins
devoted to ground, and these pins
should be connected to the ground
plane on the backplane mother card. To
complete the overall system grounding
scheme there are two possibilities: (1)
The backplane ground plane can be
connected to chassis ground at numerous points, thereby diffusing the various ground current return paths. (2)
The ground plane can be connected to a
single system "star ground" point
(generally at the power supply).
The first approach is often used at very
high frequencies and where the return
currents are relatively constant. The
low ground impedance is maintained all
the way through the PC boards, the
backplane, and ultimately the chassis.
It is critical that good electrical contact
be made where the grounds are connected to the sheet metal chassis. This
requires self-tapping sheet metal
screws or "biting" washers. Special care
must be taken where anodized aluminum is used for the chassis material,
since its surface acts as an insulator.
In other systems, especially high speed
ones with large amounts of digital
circuitry, it is highly desirable to physically separate sensitive analog components from noisy digital components. It
is usually desirable to use separate
7-27

HIGH SPEED DESIGN TECHNIQUES

ground planes for the analog and the
digital circuitry. On PCBs which have
both analog and digital circuits, there
are two separate ground planes. These
planes should not overlap in order to
minimize capacitive coupling between
the two. The separate analog and
digital ground planes are continued on
the backplane using either
motherboard ground planes or "ground
screens" which are made up of a series
of wired interconnections between the
connector ground pins. The arrangement shown in Figure 7.26 illustrates

that the two planes are kept separate
all the way back to a common system
"star" ground, generally located at the
power supplies. The connections between the ground planes, the power
supplies, and the "star" should be made
up of multiple bus bars or wide copper
brads for minimum resistance and
inductance. The back-to-back Schottky
diodes on each PCB are inserted to
prevent accidental DC voltage from
developing between the two ground
systems when cards are plugged and
unplugged.

SEPARATING ANALOG AND DIGITAL GROUNDS
VD

PCB

VD

ANALOG
GROUND

DIGITAL
GROUND
PLANE

DIGITAL
GROUND
PLANE

•••

PCB

POWER
SUPPLIES

SYSTEM STAR
GROUND

Figure 7.26

Sensitive analog components such as
amplifiers and voltage references are
referenced and decoupled to the analog
ground plane. The ADCs and DACs
(and even some mixed-signal ICs)
should be treated as analog components
and also grounded and decoupled to the
analog ground plane. At first glance;

7-28

this may seem somewhat contradictory,
since a converter has an analog and
digital interface and usually pins designated as analog ground (AGND) and
digital ground (DGND). The diagram
shown in Figure 7.27 will help to explain this seeming dilemma.

HIGH SPEED HARDWARE DESIGN TECHNIQUES

PROPER GROUNDING OF ADCs, DACs,
AND OTHER MIXED-SIGNAL ICs
VA

VD

ADC,
OR
DAC

ANALOG
IN/OUT

ANALOG
CIRCUITS

A

"QUIET"
DIGITAL

DIGITAL
CIRCUITS

~--~I---'"

BUFFER
LATCH

NOISY
DATA BUS

B

A

av

.¢rA

)

D

I = DIGITAL
"'\7 0 GROUND PLANE

= ANALOG
GROUND PLANE

Figure 7.27

Inside an IC that has both analog and
digital circuits, such as an ADC or a
DAC, the grounds are usually kept
separate to avoid coupling digital
signals into the analog circuits. Figure
7.27 shows a simple model ofa converter. There is nothing the IC designer
can do about the wirebond inductance
and resistance associated with connecting the pads on the chip to the package
pins except to realize it's there. The
rapidly changing digital currents produce a voltage at point B which will
inevitably couple into point A of the
analog circuits through the stray capacitance, CSTRAY. In addition, there
is approximately O.2pF unavoidable
stray capacitance between every pin of
the IC package! It's the IC designer's
job to make the chip work in spite of
this. However, in order to prevent
further coupling, the AG ND and DG ND
pins should be joined together exter-

nally to the analog ground plane with
minimum lead lengths. Any extra
impedance in the DGND connection will
cause more digital noise to be developed
at point B; it will, in tum, couple more
digital noise into the analog circuit
through the stray capacitance.

The name "DGND" on an Ie tells us
that this pin connects to the digital
ground of the IC. This does not imply
that this pin must be connected to the
digital ground of the system.
It is true that this arrangement will
inject a small amount of digital noise on
the analog ground plane. These currents should be quite small, and can be
minimized by ensuring that the converter input/or output does not drive a
large fanout (they normally can't by
design). Minimizing the fanout on the
converter's digital port will also keep
7-29

HIGH SPEED DESIGN TECHNIQUES

the converter logic transitions relatively
free from ringing, and thereby minimize any potential coupling into the
analog port of the converter. The logic
supply pin (Vn) can be further isolated
from the analog supply by the insertion
of a small lossy ferrite bead as shown in
Figure 7.27. The internal digital currents of the converter will return to
ground through the Vn pin decoupling
capacitor (mounted as close to the
converter as possible) and will not
appear in the external ground circuit. It
is always a good idea (as shown in
Figure 7.27) to place a buffer latch
adjacent to the converter to isolate the
converter's digital lines from any noise

which may be on the data bus. Even
though a few high speed converters
have three-state outputs/inputs, this
isolation latch represents good design
practice.
The buffer latch and other digital
circuits should be grounded and
decoupled to the digital ground plane of
the PC board. Notice that any noise
between the analog and digital ground
plane reduces the noise margin at the
converter digital interface. Since digital
noise immunity is of the orders of
hundreds or thousands of millivolts,
this is unlikely to matter.

POWER SUPPLY, GROUNDING, AND OECOUPLING POINTS
VA

7-30

VA

Vo

HIGH SPEED lIARnWARE DESIGN TECHNIQUES

Separate power supplies for analog and
digital circuits are also highly desirable.
The analog supply should be used to
power the converter. If the converter
has a pin designated as a digital supply
pin (Vn), it should'either be powered
from a separate analog supply, or
filtered as shown in the diagram. All
converter power pins should be
decoupled to the analog ground plane,
and all logic circuit power pins should
be decoupled to the digital ground
plane. If the digital power supply is
relatively quiet, it may be possible to
use it to supply analog circuits as well,
but be very cautious.
The sampling clock generation circuitry
should also be grounded and heavilydecoupled to the analog ground plane.
As previously discussed, phase noise on
the sampling clock produces degradation in system SNR.
A low phase-noise crystal oscillator
should be used to generate the ADC
sampling clock, because sampling clock
jitter modulates the input signal and
raises the noise and distortion floor.
The sampling clock generator should be
isolated from noisy digital circuits and
grounded and decoupled to the analog
ground plane, as is true for the op amp
and theADC.
Ideally, the sampling clock generator
should be referenced to the analog
ground plane in a split-ground system.
However, this is not always possible
because of system constraints. In many
cases, the sampling clock must be
derived from a higher frequency multipurpose system clock which is generated on the digital ground plane. If it is
passed between its origin on the digital

ground plane to the ADC on the analog
ground plane, the ground noise between
the two planes adds directly to the clock
and will produce excess jitter. The jitter
can cause degradation in the signal-tonoise ratio and also produce unwanted
harmonics. This can be remedied somewhat by transmitting the sampling
clock signal as a differential one using
either a small RF transformer or a high
speed differential driver and receiver as
shown in Figure 7.29. The driver and
receiver should be ECL to minimize
phase jitter. In either case, the original
master system clock should be generated from a low phase noise crystal
oscillator.
It is evident that noise can be minimized by paying attention to the system layout and preventing different
signals from interfering with each
other. High level analog signals should
be separated from low level analog
signals, and both should be kept away
from digital signals. We have seen
elsewhere that in waveform sampling
and reconstruction systems the sampling clock (which is a digital signal) is
as vulnerable to noise as any analog
signal, but is as liable to cause noise as
any digital signal, and so must be kept
isolated from both analog and digital
systems.
If a ground plane is used, as it should in
be most cases, it can act as a shield
where sensitive signals cross. Figure
7.30 shows a good layout for a data
acquisi tion board where all sensitive
areas are isolated from each other and
signal paths are kept as short as possible. While real life is rarely as tidy as
this, the principle remains a valid one.

7-31

HIGH SPEED DESIGN TECHNIQUES

SAMPLING CLOCK DISTRIBUTION FROM
DIGITAL TO ANALOG GROUND PLANES
+VO

+VD

DIGITAL
GROUND PLANE

(D)
LOW PHASE
NOISE
MASTER CLOCK

ANALOG
I GROUND PLANE

I

(A)
SAMPLING
CLOCK

SYSTEM CLOCK
GENERATORS

METHOO 1

D

D

A

SAMPLING
CLOCK

DSP
METHOD 2

D

Figure 7.29

A PC BOARD LAYOUT SHOWING GOOD SIGNAL ROUTING

SAMPLING CLOCK
GENERATOR

TIMING
CIRCUITS

ADC

BUFFER
LATCH

CONTROL
LOGIC

1----7~

DEMULTIPLEXER

FILTER
BUFFER
MEMORY

DSP
AMPLIFIER

POWER

ADDRESS
BUS
ANALOG
INPUT

DATA
BUS

Figure 7.30
7-32

MULTIPLE
GROUNDS

HIGH SPEED IlARDWARE DESIGN TECHNIQUES

There are a number of important points
to be considered when making signal
and power connections. First of all a
connector is one of the few places in the
system where all signal conductors
must run parallel - it is therefore a good
idea to separate them with ground pins
(creating a faraday shield) to reduce
coupling between them.
Multiple ground pins are important for
another reason: they keep down the
ground impedance at the junction
between the board and the backplane.
The contact resistance of a single pin of

a PCB connector is quite low (of the
order of 10 mOhms) when the board is
new - as the board gets older the contact resistance is likely to rise, and the
board's performance may be compromised. It is therefore well worthwhile to
afford extra PCB connector pins so that
there are many ground connections
(perhaps 30-40% of all the pins on the
PCB connector should be ground pins).
For similar reasons there should be
several pins for each power connection,
although there is no need to have as
many as there are ground pins.

7-33

HIGH SPEED DESIGN TECHNIQUES

POWER SUPPLY NOISE REDUCTION AND FILTERING

Walt Jung and John McDonald
Precision analog circuitry has traditionally been powered from well regula ted,
low noise linear power supplies. During
the last decade however, switching power
supplies have become much more common in electronic systems. As a consequence, they also are being used for
analog supplies. Good reasons for the
general popularity include their high
efficiency, low temperature rise, small
size, and light weight.
In spite of these benefits, switchers do
have drawbacks, most notably high
output noise. This noise generally extends over a broad band of frequencies,
resulting in both conducted and radiated
noise, as well as unwanted electric and
magnetic fields. Voltage output noise of
switching supplies are short-duration
voltage transients, or spikes. Although
the fundamental switching frequency can
range from 20kHz to IMHz, the spikes
can contain frequency components extending to 100l\fHz or more. While
specifying switching supplies in terms of
RMS noise is common vendor practice, as
a user you should also specify the peak (or
p-p) amplitudes of the switching spikes,
with the output loading of your system.
The following section discusses filter
techniques for rendering a noisy switcher
output analog ready, that is sufficiently
quiet to power precision analog circuitry
with relatively small loss of DC terminal
voltage. The filter solutions presented are
generally applicable to all power supply
types incorporating switching element(s)
in their energy path. This includes various DC-DC converters as well as popular
5V (PC type) supplies.
An understanding of the EM! process is
necessary to understand the effects of
7-34

supply noise on analog circuits and
systems. Every interference problem has
a source, a path, and a receptor [Reference
1]. In general, there are three methods
for dealing with interference. First,
source emissions can be minimized by
proper layout, pulse-edge rise time
control/reduction, filtering, and proper
grounding. Second, radiation and conduction paths should be reduced through
shielding and physical separation. Third,
receptor immunity to interference can be
improved, via supply and signal line
filtering, impedance level control, impedance balancing, and utilizing differential
techniques to reject undesired commonmode signals. This section focuses on
reducing switching power supply noise
with external post filters.
Tools useful for combating high frequency
switcher noise are shown by Figure 7.3!.
They differ in electrical characteristics as
well as practicality towards noise reduction, and are listed roughly in ari order of
priorities. Of these tools, Land C are the
most powerful filter elements, and are
the most cost-effective, as well as small
sized.

Capacitors are probably the single most
important filter component for switchers.
There are many different types of capacitors, and an understanding of their
individual characteristics is absolutely
mandatory to the design of effective
practical supply filters. There are generally three classes of capacitors useful in
10kHz-100MHz filters, broadly distinguished as the generic dielectric types;
electrolytic, film, and ceramic. These can
in turn can be further sub-divided. A
thumbnail sketch of capacitor characteristics is shown in the chart of Figure 7.32.

HIGH SPEED IlARDWARE DESIGN TECHNIQUES

NOISE REDUCTION TOOLS
•

Capacitors

•

Inductors

•

Ferrites

•

Resistors

•

Linear Post Regulation

•

PHYSICAL SEPARATION FROM SENSITIVE
ANALOG CIRCUITS II

Figure 7.31

CAPACITOR SELECTION
Aluminum
Electrolytic
(General
Purpose)

Aluminum
Tantalum
Electrolytic Electrolytic
(Switching
Type)

Polyester
(Stacked
Film)

Ceramic
(Multilayer)

Size

100 J,lF (1)

120J,lF(1)

100 J,lF (1)

1 J,lF

0.1 J,lF

Rated Voltage

25V

25V

20V

400 V

50V

ESR

0.6Q@
100 kHz

0.18 Q @
100 kHz

0.12 Q@
100 kHz

0.11 Q@
1 MHz

0.12 Q@
1 MHz

Operating
Frequency (2)

== 100 kHz

== 500 kHz

== 1 MHz

== 10 MHz

== 1 GHz

(1) Types shown in Figure 9.26 data
(2) Upper frequency limit is strongly size and package dependent

Figure 7.32
7-35

HIGH SPEED DESIGN TECHNIQUES

With any dielectric, a major potential
filter loss element is ESR (equivalent
series resistance), the net parasitic
resistance of the capacitor. ESR provides an ultimate limit to filter performance, and requires more than casual
consideration, because it can vary both
with frequency and temperature in
some types. Another capacitor loss
element is ESL (equivalent series
inductance). ESL determines the frequency where the net impedance characteristic switches from capacitive to
inductive. This varies from as low as
10kHz in some electrolytics to as high
as 100MHz or more in chip ceramic
types. Both ESR and ESL are minimized when a leadless package is used.
All capacitor types mentioned are
available in surface mount packages,
preferable for high speed uses.
The electrolytic family provides an
excellent, cost-effective low-frequency
filter component, because of the wide
range of values, a high capacitance-tovolume ratio, and a broad range of
working voltages. It includes general
purpose aluminum electrolytic types,
available in working voltages from
below 10V up to about 500V, and in
size from 1 to several thousand flF
(with proportional case sizes). All
electrolytic capacitors are polarized,
and thus cannot withstand more than a
volt or so of reverse bias without damage. They also have relatively high
leakage currents (up to tens of flA, and
strongly dependent upon design specifics).
A subset of the general electrolytic
family includes tantalum types, generally limited to voltages of 100V or less,
with capacitance of 500flF or
less[Reference 3]. In a given size,
tantalums exhibit a higher capacitanceto-volume ratios than do general pur7-36

pose electrolytics, and have both a
higher frequency range and lower ESR.
They are generally more expensive
than standard electrolytics, and must
be carefully applied with respect to
surge and ripple currents.
A subset of aluminum electrolytic
capacitors is the switching type, designed for handling high pulse currents
at frequencies up to several hundred
kHz with low losses [Reference 4]. This
capacitor type competes directly with
tantalums in high frequency filtering
applications, with the advantage of a
broader range of val ues.
A more specialized high performance
aluminum electrolytic capacitor type
uses an organic semiconductor electrolyte [Reference 5]. The OS-CON capacitors feature appreciably lower ESR and·
higher frequency range than do other
electrolytic types, with an additional
feature of low low-temperature ESR
degradation.
Film capacitors are available in very
broad value ranges and an array of
dielectrics, including polyester, polycarbonate, polypropylene, and polystyrene.
Because of the low dielectric constant of
these films, their volumetric efficiency
is quite low, and a 10flF/50V polyester
capacitor (for example) is actually a
handful. Metalized (as opposed to foil)
electrodes does help to reduce size, but
even the highest dielectric constant
units among film types (polyester,
polycarbonate) are still larger than any
electrolytic, even using the thinnest
films with the lowest voltage ratings
(50V). Where film types excel is in their
low dielectric losses, a factor which may
not necessarily be a practical advantage for filtering switchers. For example, ESR in film capacitors can be as
low as 10mQ or less, and the behavior

HIGH SPEED IlARDWARE DESIGN TECHNIQUES

of films generally is very high in terms
of Q. In fact, this can cause problems of
spurious resonance in filters, requiring
damping components.
Typically using a wound layer-type
construction, film capacitors can be
inductive, which can limit their effectiveness for high frequency filtering.
Obviously, only non-inductively made
film caps are useful for switching
regulator filters. One specific style
which is non-inductive is the stackedfilm type, where the capacitor plates
are cut as small overlapping linear
sheet sections from a much larger
wound drum of dielectric/plate material. This technique offers the low
inductance attractiveness of a plate
sheet style capacitor with conventional
leads [see References 4, 5, 6]. Obviously, minimal lead length should be
used for best high frequency effectiveness. Very high current polycarbonate
film types are also available, specifically designed for switching power
supplies, with a variety of low inductance terminations to minimize ESL
[Reference 7].
Dependent upon their electrical and
physical size, film capacitors can be
useful at frequencies to well above
10MHz. At the highest frequencies,
only stacked film types should be
considered. Some manufacturers are
now supplying film types in leadless
surface mount packages, which eliminates the lead length inductance.
Ceramic is often the capacitor material
of choice above a few MHz, due to its
compact size, low loss, and availability
up to several J..lF in the high-K dielectric
formulations (X7R and Z5U), at voltage
ratings up to 200V [see ceramic families
of Reference 3]. NPO (also called COG)
types use a lower dielectric constant
formulation, and have nominally zero

TC, plus a low voltage coefficient (unlike the less stable high-K types). NPO
types are limited to values of O.lJ..lF or
less, with O.OlJ..lF representing a more
practical upper limit.
Multilayer ceramic "chip caps" are very
popular for bypassing/ filtering at
10MHz or more, simply because their
very low inductance design allows near
optim um RF bypassing. For smaller
values, ceramic chip caps have an
operating frequency range to 1GHz. For
high frequency applications, a useful
selection can be ensured by selecting a
value which has a self-resonant frequency above the highest frequency of
interest.
All capacitors have some finite ESR. In
some cases, the ESR may actually be
helpful in reducing resonance peaks in
filters, by supplying "free" damping.
For example, in most electrolytic types,
a nominally flat broad series resonance
region can be noted in an impedance vs.
frequency plot. This occurs where I Z I
falls to a minimum level, nominally
equal to the capacitor's ESR at that
frequency. This low Q resonance can
generally be noted to cover a relatively
wide frequency range of several octaves. Contrasted to the very high Q
sharp resonances of film and ceramic
caps, the low Q behavior of electrolytics
can be useful in controlling resonant
peaks.
In most electrolytic capacitors, ESR
degrades noticeably at low temperature, by as much as a factor of 4-6
times at -55°C vs. the room temperature value. For circuits where ESR is
critical to performance, this can lead to
problems. Some specific electrolytic
types do address this problem, for
example within the HFQ switching
types, the -10cC ESR at 100kHz is no
7-37

HIGH SPEE:P DESIGN TECHNIQUES

more than 2x that at room temperature. The OSCON electrolytics have a
ESR vs. temperature characteristic
which is relatively flat.
Figure 7.33 illustrates the high frequency impedance characteristics of a
number of electrolytic capacitor types,
using nominaI100~F/20V samples. In
these plots, the impedance, I Z I, vs.
frequency over the 20Hz-200kHz range
is displayed using a high resolution 4terminal setup [Reference 8]. Shown in
this display are performance samples

for a 100~F/25V general purpose aluminum unit (top curve @ right), a 120~F/
25V HFQ unit (next curve down @
right), a 100~F/20V tantalum bead
type (next curve down @ right), and a
100~F/20V OS-CON unit (lowest curve
@ right). While the HFQ and tantalum
samples are close in 100kHz impedance, the general purpose unit is about
4 times worse. The OS-CON unit is
nearly an order of magnitude lower in
100kHz impedance than the tantalum
and switching electrolytic types.

IMPEDANCE Z (0) VS. FREQUENCY (Hz) FOR 100IJF
ELECTROLYTIC CAPACITORS (AC CURRENT SOmA RMS)

=

100

Ap
1'li

~,

10

,
~

\Z\ (0)

~

~
GEN. PURPOSE AL

100IJF,25V

i""o. "
~

".

0.1

...... t::::.. :.,-1-

---

"HF.Q" 120IJF, 25V
TANTALUM BEAD

100IJF,20V

- 100IJF,20V

OS-CONAL

10m

1m

20

100

1k
10k
FREQUENCY (Hz)

100k 200k

Figure 7.33

As noted, all real capacitors have
parasitic elements which limit their
performance. The equivalent electrical
network representing a real capacitor
models both ESR and ESL as well as
the basic capacitance, plus some shunt
__ ,...:,..+ ..... ~~" T~ n"n~ n "'n. .... n"~;"nl nn-non;
~'t:;;:)~;:)"(1J.J."'t:;. ~J.J. O"""'J.J. Cl }lJ.Cl"'''''''''Cl'''
=

"''''1:'",,,,...

tor, at low frequencies the net imped7-38

ance is almost purely capacitive (noted
in Figure 7.33 by the 100Hz impedance). At intermediate frequencies, the
net impedance is determined by ESR,
for example about 0.120 to 0.40 at
125kHz, for several types. Above about
lMHz these capacitor types become
inductive, with impedance dominated

HIGH SPEED IIARnWARE DESIGN TECHNIQUES

by the effect of ESL (not shown). All
electrolytics will display impedance
curves similar in general shape. The
minimum impedance will vary with the
ESR, and the inductive region will vary
with ESL (which in turn is strongly
effected by package style).
Regarding inductors, Ferrites (nonconductive ceramics manufactured from
the oxides of nickel, zinc, manganese, or
other compounds) are extremely useful

in power supply filters [Reference 9]. At
low frequencies «100kHz), ferrites are
inductive; thus they are useful in lowpass LC filters. Above 100kHz, ferrites
become resistive, an important characteristic in high-frequency filter designs.
Ferrite impedance is a function of
material, operating frequency range,
DC bias current, number of turns, size,
shape, and temperature. Figure 7.34
summarize a number ferrite characteristics.

CHARACTERISTICS OF FERRITES
•

Good for frequencies above 25kHz

•

Many sizes and shapes available including
leaded "resistor style"

•

Ferrite impedance at high frequencies is
primarily resistive -- Ideal for HF filtering

•

Low DC loss: Resistance of wire passing through
ferrite is very low

•

High saturation current

•

Low cost

Figure 7.34

Several ferrite manufacturers offer a
wide selection offerrite materials from
which to choose, as well as a variety of
packaging styles for the finished network (see References 10 and 11). A
simple form is the bead of ferrite material, a cylinder of the ferrite which is

simply slipped over the power supply
lead to the decoupled stage. Alternately, the leaded ferrite bead is the
same bead, pre-mounted on a length of
wire and used as a component (see
Reference 11). More complex beads
offer multiple holes through the cylin7-39

HIGH SPEED DESIGN TECHNIQUES

der for increased decoupling, plus other
variations. Surface mount beads are
also available.
PSpice ferrite models for Fair-Rite
materials are available, and allow
ferrite impedance to be estimated [see
Reference 12]. These models have been
designed to match measured impedances rather than theoretical impedances.
A ferrite's impedance is dependent upon
a number of inter-dependent variables,
and is difficult to quantify analytically,
thus selecting the proper ferrite is not
straightforward. However, knowing the

following system characteristics will
make selection easier. First, determine
the frequency range of the noise to be
filtered. Second, the expected temperature range of the filter should be
known, as ferrite impedance varies
with temperature. Third, the DC current flowing through the ferrite must be
known, to ensure that the ferrite does
not saturate. Although models and
other analytical tools may prove useful,
the general guidelines given above,
coupled with some experimentation
with the actual filter connected to the
supply output under system load conditions, should lead to a proper ferrite
selection.

CHOOSING THE RIGHT FERRITE DEPENDS ON
•

Source of Interference

•

Interference Frequency Range

•

Impedance Required at Interference Frequency

•

Environmental Conditions:
Temperature, AC and DC Field Strength,
Size I Space Available

•

Don't fail to Test the Design ------EXPERIMENT! EXPERIMENT!

Figure 7.35

7-40

HIGH SPEED IIARnWARE DESIGN TECHNIQUES

Using proper component selection, low
and high frequency band filters can be
designed to smooth a noisy switcher's
DC output so as to produce an analog
ready 5V supply. It is most practical to
do this over two (and sometimes more)
stages, each stage optimized for a range
of frequencies. A basic stage can be
used to carry all of the DC load current,
and filter noise by 60dB or more up to a
1-10MHz range. This larger filter is
used as a card entry filter providing
broadband filtering for all power entering a PC card. Smaller, more simple
local filter stages are also used to
provide higher frequency decoupling

right at the power pins of individual
stages.
Figure 7.36 illustrates a card entry
filter suitable for use with switching
supplies. With a low rolloff point of
105kHz and m V level DC errors, it is
effective for a wide variety of filter
applications just as shown. This filter is
a single stage LC low-pass filter covering the 1kHz to 1MHz range, using
carefully chosen parts. Because of
component losses, it begins to lose
effectiveness above a few MHz, but is
still able to achieve an attenuatioll:
approaching 60dE at 1MHz.

"CARD-ENTRY" SWITCHING SUPPLY FILTER
L1

+

+

100/-tH
5V INPUT
FROM NOISY
SWITCHING
SUPPLY OR DC
TO DC
CONVERTER

C1
1OO/-tF,20V
TANTALUM

C2
1/-t F
CERAMIC

+

OUTPUT TO
300mA LOAD
ANALOG
STAGE

R1

.

o------------------1~1n-----------------o.
Figure 7.36
7-41

HIGH SPEED DESIGN TECHNIQUES

The key to low DC losses is the use of
input choke, L1, a ferrite-core unit
selected for a low DC resistance (DCR)
of <0.250 at the 100J..lH inductance
(either an axial lead type.5250 or a
radial style 6000·101K choke should
give comparable results) [Reference 13].
These chokes have low inductance shift
with a 300mA load current, and the low
DCR allows the 300mA to be passed
with no more than 75mV of DC error.
Alternately, resistive filtering might be
used in place ofL1, but a basic tradeoff

here is that load current capacity will
be compromised for comparable DC
errors. C1, a 100J..lF/20V tantalum type,
provides the bulk of the capacitive
filtering, shunted by a 1J..lF multilayer
ceramic.
Figure 7.37 shows the frequency response of this filter in terms of SPICE
simulation and lab measurements, with
good agreement between the simulation
and the measurements below 1MHz.

OUTPUT RESPONSE OF "CARD-ENTRY" FILTER
LAB VS. SIMULATION
OJ

-

°i

2

OUTPUT
:
(RELATIVE dB)

I

-

= SPICE SIMULATION
x

= LAB RESULTS

-<0-

- 60

1

-eo-

-100 + --- - --10

------r------------..,-------------,
-------------r--------.----or
---------- 10M'..,------------100'
1. OK
10K
lOOK
1. OM
100M
FREQUENCY (Hz)

Figure i.3i
7-42

HIGH SPEED lIARDWARE DESIGN TECHNIQUES

This type of filter does have some
potential pitfalls, and one of them is the
control of resonances. If the LCR circuit
formed does not have sufficiently high
resistance at the resonant frequency,
amplitude peaking will result. This
peaking can be minimized with resistance at two locations: in series with
L1, or in series with C1+C2. Obviously,
limi ted resistance is usable in series
with L1, as this increases the DC
errors.

attenuation below 1MHz. Note that for
wide temperature range applications,
all temperature sensitive filter components will need consideration.
A local high frequency filter useful with
the card entry filter is shown in Figure
7.38. This simple filter can be considered an option, one which is exercised
dependent upon the high fre"quency
characteristics of the associated IC and
the relative attenuation desired. It uses
Zl, a leaded ferrite bead such as the
Panasonic EXCELSA39, providing a
resistance of more than 800 at 10MHz,
increasing to over 1000 at 100MHz.
The ferrite bead is best used with a
local high frequency decoupling cap
right at the IC power pins, such as a
O.lJ..lF ceramic up.it shown.

In the filter, R1 is a damping resistor,
used to control resonant peaks, and it
should not be eliminated. A 10 value
provides a slightly underdamped response, with peaking on the order of
1dB. Alternately, 1.50 can be used for
less peaking, with a tradeoff of less

HIGH FREQUENCY LOCALIZED DECOUPLING

+5V

TO ADDITIONAL
STAGES

FROM
CARD-ENTRY
FILTER

Z1
LEADED FERRITE BEAD
PANASONIC EXCELSA39
(OPTIONAL)

ANALOG
IC

O.1J.1.F
CERAMIC

Figure 7.38
7-43

HIGH SPEED DESIGN TECHNIQUES

Both the card entry filter and the local
high frequency decoupling filters are
designed to fl1.ter differential-mode
noise only, and use common, off the
shelf components [Reference 14].
The following list summarizes the
switching power supply filter layoutJ
construction guidelines which will help
ensure that the filter does the best
possible job:

(1) Pick the highest electrical value and
voltage rating for filter capacitors which
is consistent with budget and space
limits. This minimizes ESR, and maximizes filter performance. Pick chokes for
low ilL at the rated DC current, as well
as low DCR.
(2) Use short and wide PCB tracks to
decrease voltage drops and minimize
inductance. Make track widths at least
200 mils for every inch of track length
for lowest DCR, and use 1 oz or 2 oz
copper PCB traces to further reduce IR
drops and inductance.
(3) Use short leads or better yet, leadless
components, to minimize lead inductance. This minimizes the tendency to
add excessive ESL and/or ESR. Surface
mount packages are preferred.
(4) Use a large-area ground plane for
minimum impedance.
(5) Know what your components do over
frequency, current and temperature
variations! Make use of vendor component models for the simulation of prototype designs, and make sure that lab
measurements correspond reasonably
with the simulation. While simulation is
not absolutely necessary, it does instill

7-44

confidence in a design when correlation
is achieved(see Reference 15).
The discussion above assumes that the
incoming AC power is relatively clean,
an assumption not always valid. The
AC power line can also be an EM!
entry/exit path! To remove this noise
path and reduce emissions caused by
the switching power supply or other
circuits, a power line filter is required.

It is important to remember that AC line
power can potentially be lethal! Do not
experiment without proper equipment
and training! All components used in
power line filters should be UL approved, and the best way to provide this
is to specify a packaged UL approved
filter. It should be installed in such a
manner that it is the first thing the AC
line sees upon entering the equipment
(see Figure 7.39). Standard three wire
IEC style line cords are designed to
mate with three terminal male connectors integral to many line filters. This
is the best way to achieve this function,
as it automatically grounds the third
wire to the shell of the filter and equipment chassis via a low inductance path.
Commercial power line filters can be
quite effective in reducing AC powerline noise. This noise generally has both
common-mode and differential-mode
components. Common-mode noise is
noise that is found on any two of the
three power connections (black, white,
or green) with the same amplitude and
polarity. In contrast, differential-mode
noise is noise found only between two
lines. By design, most commercially
available filters address both noise
modes (see Reference 1(3).

HIGH SPEED lIARDWARE DESIGN TECHNIQUES

POWER LINE FILTERING IS ALSO IMPORTANT

POWER
LINE

POWER
LINE
FILTER

SWITCHING
POWER
SUPPLY

I

SWITCHING
POWER
SUPPLY
FILTER

Power Line Filter Blocks EMI from
Entering or Exiting Box Via Power Lines

Figure 7.39

7-45

HIGH SPEED DESIGN TECHNIQUES

REFERENCES: NOISE REDUCTION AND FILTERING
1.

EMC Design Workshop Notes, Kimmel-Gerke Associates, Ltd., St. Paul,
MN. 55108, (612) 330-3728.

2.

Walt Jung, Dick Marsh, Picking Capacitors, Parts 1 & 2, Audio, February,
March, 1980.

3.

Tantalum Electrolytic and Ceramic Capacitor Families, Kemet Electronics,
Box 5928, Greenville, SC, 29606, (803) 963-6300.

4.

Type HFQ Aluminum Electrolytic Capacitor and type V Stacked Polyester
Film Capacitor, Panasonic, 2 Panasonic Way, Secaucus, NJ, 07094,
(201) 348-7000.

5.

OS-CON Aluminum Electrolytic Capacitor 93/94 Technical Book, Sanyo,
3333 Sanyo Road, Forrest City, AK, 72335, (501) 633-6634.

6.

Ian Clelland, Metalized Polyester Film Capacitor Fills High Frequency
Switcher Needs, PCIM, June 1992.

7.

Type 5MC Metallized Polycarbonate Capacitor, Electronic Concepts, Inc.,
Box 1278, Eatontown, NJ, 07724, (908) 542-7880.

8.

Walt Jung, Regulators for High-Performance Audio, Parts 1 and 2, The
Audio Amateur, issues 1 and 2, 1995.

9.

Henry Ott, Noise Reduction Techniques in Electronic Systems, 2d
Ed., 1988, Wiley.

10.

Fair-Rite Linear Ferrites Catalog, Fair-Rite Products, Box J, Wallkill,
NY, 12886, (914) 895-2055.

11.

Type EXCEL leaded ferrite bead EMI filter, and type EXC L leadless
ferrite bead, Panasonic, 2 Panasonic Way, Secaucus, NJ, 07094,
(201) 348-7000.

12.

Steve Hageman, Use Ferrite Bead Models to Analyze EM! Suppression,
The Design Center Source, MicroSitn Newsletter, January, 1995.

13.

Type 5250 and 6000-101K chokes, J. W. Miller, 306 E. Alondra Blvd.,
Gardena, CA, 90247, (310) 515-1720.

14.

DIGI-KEY, PO Box 677, Thief River Falls, MN, 56701-0677, (800) 344-4539.

15.

Tantalum Electrolytic Capacitor SPICE Models, Kemet Electronics,
Box 5928, Greenville, SC, 29606, (803) 963-6300.

16.

EichhoffElectronics, Inc., 205 Hallene Road, Warwick, RI., 02886,
(401) 738-1440.

7~--4"'!'""6--

HIGH SPEED IIARDWARE DESIGN TECHNIQUES

POWER SUPPLY REGULATION/CONDITIONING

Walt Jung
Many analog circuits require stable
regulated voltages relatively close in
potential to an unregulated source. An
example would be a linear post regulator for a switching power supply, where
voltage loss (dropout) is critical. This
low dropout type of regulator is readily
implemented with a rail-rail output op
amp. The wide output swing and low
saturation voltage enables outputs to
come within a fraction of a volt of the

source for medium current «30mA)
loads, such as reference applications.
For higher output currents, the rail-rail
voltage swing feature allows direct
drive to low saturation voltage pass
devices, such as power PNPs or Pchannel MOSFETs. Op amps working
from 3V up with the rail-rail features
are most sui table here, providing power
economy and maximum flexibility.

Low DROPOUT REFERENCES
Basic references
Among the many problems in making
stable DC voltage references work from
5V and lower supplies are quiescent
power consumption, overall efficiency,
the ability to operate down to 3V, low
input/output (dropout) capability, and
minimum noise output. Because low
voltage supplies can't support zeners of
::6V, low voltage references must
necessarily be bandgap based- a basic
::l.2V potential. With low voltage
systems, power conservation can be a
critical issue with references, as can
output DC precision.
For many applications, simple onepackage flXed (or variable) voltage
references with minimal external
circuitry and high accuracy are attractive. Two unique features of the three
terminal REFl9X bandgap reference
family are low power, and shutdown
capability. The series allows flXed
outputs from 2.048-5V to be controlled
between ON and OFF, via a TTU
CMOS power control input. It provides
precision reference quality for those
popular voltages shown in Figure 7.40.

The REFl9X family can be used as a
simple three terminal flXed reference as
per the table by tying pins 2 and 3
together, or as an ON/OFF controlled
device, by programming pin 3 as noted.
In addition to the shutdown capacity,
the distinguishing functional features
are a low dropout of 0.5V at lOmA, and
a low current drain for both quiescent
and shutdown states, 45 and l5~
(max.), respectively. For example,
working from inputs in the range of 6.3
to l5V, a REFl95 used as shown drives
5V loads at up to 30mA, with grade
dependent tolerances of±2 to ±5mV,
and max TCs of 5 to 25ppm/°C. Other
devices in the series provide comparable accuracy specifications, and all
have low dropout features.
To maximize DC accuracy in this
circuit, the output ofUl should be
connected directly to the load with
short heavy traces, to minimize IR
drops. The common terminal (pin 4) is
less critical due to lower current in this
leg.

7-47

HIGH SPEED DESIGN TECHNIQUES

30 mA REFERENCE FAMILY WITH OPTIONAL SHUTDOWN
VS{ }--_---,
Vs > VOUT + 0.5V
TO +15V

.----------, 6

U1
REF19X

Vc

+

3
POWER r---r--L--.--~
CONTROL
+
4
C2

TTUCMOS
LEVELS

C1
1~F

~---~~

t

(TANTALUM)
_ _ _ _ _ _ _~

10~F

HIGH (OR OPEN) =
ON
LOW = OFF

U1

VOUT (V)

REF191
REF192
REF193
REF196
REF198
REF194
REF195

2.048
2.5
3.0
3.3
4.096
4.5
5.0

Figure 7.40

RAIL·TO·RAIL OUTPUT OP AMPS ALLOW GREATEST
FLEXIBILITY IN LOW DROPOUT FREQUENCIES
+3VORMORE

VOUT=VREF

> - - - e - - - - - u OR
VOUT = VREFx (1 + R2/R3)

I
I
I
I
I
I
I

I

01
AD589
+1.235V
AD1580
+1.225V

I
I
I

l
l ____

:~

~ R3

U1: SEETEXT

R2

I

\l

-------------------------0 VREF
(UNBUFFERED)

Figure 7.41
7-48

HIGH SPEED HARDWARE DESIGN TECHNIQUES

Scaled References
Another approach, one with the advantage of voltage flexibility, is to buffer/
scale a low voltage reference diode.
With this approach, one difficulty is
getting an amplifier to work well at 3V.
A workhorse solution is the low power
reference and scaling buffer shown in
Figure 7.41. Here a low current 1.2V,
two-terminal reference diode is used for
Dl, either the 1.235V AD589 or the
1.225V AD1580. Resistor Rl sets the
diode current, chosen for 50pA at a
minimum supply of2.7V. Obviously,
loading on the unbuffered diode must
be minimized at the VREF node.

ence, allowing much higher source/sink
currents. A higher op amp quiescent
current is expended in doing this, but
this is a basic tradeoff of the approach.
Quiescent current is amplifier dependent, ranging from 45pA1channei with
the OP196/296/496 series to 10002000].lNchannei with the OP284 and
OP279. The former series is most useful
for very light loads «2mA), while the
latter series provide device dependent
outputs up to 50mA. Various devices
can be used in the circuit as shown, and
their key specs are summarized in
Figure 7.42.

Amplifier Ul both buffers and optionally scales up the nominal1.2V refer-

OP AMPS USEFUL IN LOW VOLTAGE RAIL-RAIL
REFERENCES AND REGULATORS
Device*

Iq/channel

Vsat(+),

Vsat(-), V

Isc,mA

mA

V(min @mA)

(max@mA)

(min)

OP193/293/493

0.017

4.20 @ 1

0.280 @ 1 (typ) ±8

OP196/296/496

0.045

4.30 @ 1

0.430 @ 1

±4

OP295/495

0.150 (max) 4.50 @ 1

0.110 @ 1

± 11

OP191/291/491

0.300

4.80@2.5

0.075 @ 2.5

±8.75

AD820/822/824

0.620

4.89@2

0.055 @ 2

±15

OP184/284/484

1.250 (max) 4.85@2.5

0.125 @ 2.5

± 7.5

OP279

2.000

0.075 @ 10

±45

4.80 @ 10

*Typical device specifications @ Vs

=+5V, T =25°C, unless otherwise noted.
A

Figure 7.42
7-49

HIGH SPEED DESIGN TECHNIQUES

In Figure 7.41, without gain scaling
resistors R2-R3, VOUT is simply equal
to VREF. With the scaling resistors,
VOUT can be set anywhere between
VREF and the positive rail, due to the op
amp's rail-rail output swing. Also, this
buffered reference is inherently low
dropout, allowing a +4.5V reference
output on a +5V supply, for example.
The general expression for VOUT is
shown in the figure, where VREF is the
reference voltage.

Amplifier standby current can be
further reduced below 20pA, if an
amplifier from the OP193/293/493
series is used. This will be at the expense of current drive and positive rail
saturation, but does provide the lowest
possible quiescent current if necessary.
All devices in Figure 7.42 operate from
voltages down to 3V (except the OP279,
which operates at 5V).

Low Dropout Regulators
By adding a boost transistor to the
basic rail-rail output low dropout reference of Figure 7.41, output currents of
100mA or more are possible, still
retaining features of low standby

current and low dropout voltage. Figure
7.43 shows a low dropout regulator
with 800pA standby current, suitable
for a variety of outputs at current levels
oflOOmA.

100mA LOW NOISE, LOW DROPOUT REGULATOR
Q1

MJE170

+V IN

o-__........-------~

VOUT

,...----+----__- -__-0 3-6V (TABLE)
OUTPUT TABLE

R4
39.2kQ

C1
100llF/25V
(LOW ESR)

R1
(TABLE)

+

C4

O.01IlF

01
A0589
1.235V

R1

6V

383kO

6.2V

5V

301k~

5.2V

4V

226kO

4.2V

3.3V

169kO

3.5V

3.0V

143kO

3.2V

+ C2

R5
100kQ

100llF/25V
(LOW ESR)
C3
11lF FILM

R2
100kQ

--~'-------'-------~----------------~~--~'-~COMMON

Figure 7.43
7-50

(min)

Vour

VIN

HIGH SPEED lIARDWARE DESIGN TECHNIQUES

The 100mA output is achieved with a
controlled gain bipolar power transistor
for pass device Q1, an MJE170. Maximum output current control is provided
by limiting base drive to Ql via series
resistor R3. This limits the base c;urrent
to about 2mA, so the max HFE of Ql
then allows no more than 500mA. This
limits Ql's short circuit power dissipation to safe levels.
Overall, the circuit operates as a follower with gain, as was true in the case
of Figure 7.41, so VOUT has a similar
output expression. The circuit is
adapted for different voltages simply by
programming Rl via the table. Dropout
with a lOOmA load is about 200mV,
thus a 5V output is maintained for
inputs above 5.2V (see table), and
VOUT levels down to 3V are possible.
Step load response of this circuit is
quite good, and transient error is only a

few mVp-p for a 30-100mA load change.
This is achieved with low ESR switching type capacitors at Cl-C2, but the
circuit also works with conventional
electrolytics (with higher transient
errors).
If desired, lowest output noise with the
AD820 is reached by including the
optional reference noise filter, R5-C3.
Lower current op amps can also be used
for lower standby current, but with
larger transient errors due to reduced
bandwidth.
While the 30mA rated output current of
the REF19X series is higher than most
reference ICs, it can be boosted to much
higher levels if desired, with the addition of a PNP transistor, as shown in
Figure 7.44. This circuit uses full time
current limiting for protection of pass
transistor shorts.

150mA BOOSTED OUTPUT REGULATOR/REFERENCE
WITH CURRENT LIMITING
R4
+Vs

Q1
TIP32A

= 6 TO 9V o-_e_--a__-'V\2n/\r-_e_--(--.SEE TEX,...T_)_ _--,
(SEE TEXT)

C2
100llF/25V

+
C3
0.111 F

01
Vc 0--

~1N4148
(SEE TEXT
ON SLEEP)

F

OUTPUT TABLE
U1

VOUT (V)

REF192
REF193
REF196
REF194
REF195

2.5
3.0
3.3
4.5
5.0

S

)..i~--'-'-''''-IIQ +VOUT
3.3V
C1
@ 150mA
10l1F/25V
(TANTALUM)
R3
1.82k
S

V OUT
Vs
O-~----------~---------~~--OCOMMON
COMMON
F

Figure 7.44
7-51

HIGH SPEED DESIGN TECHNIQUES

In this circuit the supply current of
reference U1 flows inR1-R2, developing
a base drive for pass device Q1, whose
collector provides the bulk of the output
current. With a typical gain of 100 in
Q1 for 100-200mA loads, U1 is never
required to furnish more than a few
rnA, and this factor minimizes temperature related drift. Short circuit protection is provided by Q2, which clamps
drive to Q1 at about 300mA of load
current. With separation of controll
power functions, DC stability is optimum, allowing best advantage of
premium grade REF19X devices for U1.
Of course, load management should
still be exercised. A short, heavy, low
resistance conductor should be used
from Ul-6 to the VOUT sense point "S",
where the collector of Q1 connects to
the load.
Because of the current limiting, dropout
voltage is raised about 1.1V over that of
the REF19X devices. However, overall
dropout typically is still low enough to
allow operation of a 5 to 3.3V regulator/
reference using the 3.3V REF-196 for
U1, with a Vs of 4.5V and a load current of 150mA.
The heat sink requirements ofQ1
depend upon the maximum power.
With Vs = 5V and a 300mA current
limit, the worst case dissipation ofQ1 is
1.5W, less than the TO-220 package
2\V limit. IfTO-39 or TO-5 packaged
devices such as the 2N4033 are used,
the current limit should be reduced to
keep maximum dissipation below the
package rating, by raising R4. A tantalum output capacitor is used at C1 for
its low ESR, and the higher value is

7 -52

required for stability. Capacitor C2
provides input bypassing, and can be
an ordinary electrolytic.
Shutdown control of the booster stage is
shown as an option, and when used,
some cautions are in order. To enable
shutdown control, the connection to U12 and Ul-3 is broken at "X", and diode
D1 allows a CMOS control source to
drive Ul-3 for ON/OFF control. Startup
from shutdown is not as clean under
heavy load as it is with the basic
REF19X series stand-alone, and can
require several milliseconds under load.
Nevertheless, it is still effective, and
can fully control 150mA loads. When
shutdown control is used, heavy capacitive loads should be minimized.
Dedicated low dropout linear IC regulators offer all the virtues of the discrete
approaches, but in a easier-to-use
compact format. The ADP3367 is such
a device, providing either a fixed output
of 5V ±2%, or adjustable outputs over a
range of 1.3 to 16.5V, with current
outputs up to 300mA. Using a CMOS
architecture with a PNP pass transistor, it has a quiescent current of 25~
(max., unloaded), and a dropout voltage
of 175mV (max.) with a 100mA output.
Figure 7.45 shows the basic hookup for
the ADP3367, which uses the "thermal
coastline" 8 pin sOle package, which is
designed for power dissipation up to
960mW. For fixed 5V outputs, Rl and
R2 aren't used, and the SET pin is
grounded as shown. With the SHDN
pin also grounded, this simple hookup
provides a constant 5V at VOUT, with
the low dropout features mentioned.

HIGH SPEED IIARDWARE DESIGN TECHNIQUES

30mA LOW DROPOUT FIXEDNARIABLE
REGULATOR WITH OPTIONAL SHUTDOWN
VIN
+5.15V
TO
+16.5V

VOUT

OUT

IN

R2 ~
162kn

ADP3367
C1
O.1~F

SHDN

SET
GND

-

-.

*

+5V

+

I
I

C2
10~F

~

0- - -

R1
100kn

VSHDN

I

* WITH R1, R2:
VOUT= VREF (1 +

:~)

WHERE VREF = +1.255V,
VOUT = +3.3V (VALUES SHOWN)

Figure 7.45

The ADP3367's useful output current
capacity will be dependent upon the
VIN-VOUTdifferential, such that the
resulting power it dissipates is contained to 960 mW or less. For example,
at low iriput-output differences of2.5V,
up to 300mA is available. For higher
input-output differences, the allowable
current is reduced according to the
curves shown in Figure 7.46. The upper
shaded curve corresponds to the output
current which is consistent with the
ADP3367's package limitations. Note
that the allowable output current is
appreciably higher than that of a
standard SO package, shown in the
lower shaded curve.

mented, shutdown is accomplished by
applying a control voltage of more than
1.5V to VSHDN. OtherWise, this pin
should be tied to ground as shown. The
SET pin has a dual function, and can be
used either to select an internal divider
(which provides the fIxed 5V output), or
it can be used with an external divider,
RI-R2. When the SET pin is grounded,
the internal divider is active, and the 5
V output results. When the SET pin is
used with the external divider, VOUT is
programmed as:

The ADP3367 can be placed in a shutdown mode, which reduces the output
voltage to zero and drops the standby
current to less than l~. When imple-

where VREF is 1.255V, the internal
reference voltage of the ADP3367. The
divider's absolute resistance values are
not critical, since the input current at
7-53

HIGH SPEED DESIGN TECHNIQUES

ADP3367 LOAD CURRENT VS. INPUT - OUTPUT VOLTAGE
400r---------~----------~--------~

300

<

E

I
J-

Z

~ 200
a:

;:,

o
c
o<

-' 100

10

5

15

Figure 7.46

the SET pin is low, typically lOpA. This
allows resistances of lOOk - lmeg,
consistent with the overall low standby
power objectives. The example 1%
values shown provide a 3.3V output.
They can be further increased, if it is
desired to lower standby current consumption below the ::l2JlA resulting
with the values shown.
C2, the output capacitor, is a lOJlF
type, and is required for regulator
stability. Larger sizes are permissible,
and will help improve transient re-

7-54

sponse. An input bypass is also
recommended, Cl.
To achieve the full power capability
inherent to the design, the ADP3367
should be mounted on a PCB in such as
way that internally-generated heat can
flow outward easily from the die to the
PCB. Large area PCB copper traces
should be used beneath and around the
IC, and mounting should be such that
the part is exposed to unrestricted air
flow [see Reference 5].

HIGH SPEED IlARDWARE DESIGN TECHNIQUES

REFERENCES: POWER SUPPLY REGULATION/CONDITIONING
1.

Walt Jung, Build an Ultra-Law-Noise Voltage Reference,
Electronic Design Analog Applications Issue, June 24, 1993.

2.

Walt Jung, Getting the Most from
Dialogue 28·1, 1994.

3.

Walt Jung, The Ins and Outs of 'Green' RegulatorslReferen.ces ,
Electronic Design Analog Applications Issue, June 27, 1994.

4.

Walt Jung, Very-Low-Noise 5- V Regulator, Electronic Design,
July 25, 1994.

5.

"Power Dissipation" Discussions, ADP3367 Data Sheet, Analog Devices.

Ie Voltage References,

Analog

7-55

HIGB SPEED DESIGN TECHNIQUES

THERMAL MANAGEMENT

Walt Jung
For reliability reasons, modern semiconductor based systems are increasingly called upon to observe some form
of thermal management. All semiconductors have some specified safe upper
limit to junction temperature (TJ),
usually on the order of 150°C (but
sometimes 175°). Like maximum
power supply potentials, maximum
junction temperature is a worst case
limitation which shouldn't be ex-

ceeded. In conservative designs, it
won't be approached by less than
an ample safety margin. This is a
critical point, since the lifetime of all
semiconductors is inversely related
to their operating junction temperature. The cooler semiconductors can
be kept during operation, the more
closely they will approach maximum
useful life.

Thermal basics
The general symbol e is used for
thermal resistance, that is:

In general, a device with a thermal
resistance e equal to 100°CIW will
exhibit a temperature differential of
100°C for a power dissipation of 1W,
as measured between two reference
points. Note that this is a linear
relation, so a 500mW dissipation in
the same part will produce a 50°C
differential, and so forth. For any
power P (in watts), calculate the
effective temperature differential (~T)
in °c as:

A real example illustrating this relationship is shown by Figure 7.48. These
curves indicate the maximum power
dissipation vs. temperature characteris~
tic for a device using 8 pin DIP and
SOIC packaging. For a TJ(max) of
150°C, the upper curve shows the
allowable power in a DIP package.
This corresponds to a e which can
be calculated by dividing the ~T by
P at any point. For example, 1W of
power is allowed at a TA of 60°C, so
the L\T is 150°C - 60°C = 90°C.
Dividing by 1W gives this DIP
package's e of 90°CIW. Similarly,
the SOIC package yields 160°CIW.
These figures are in fact the eJA for
the AD823 op amp, but they also
happen to be quite similar to other 8
pin devices. Given such data as
these curves, the eJA for a given
device can be readily determined, as
above.

~T=pxe

As the relationship signifies, to main-

where e is the total applicable thermal resistance. Figure 7.47 summarizes these thermal relationships.

tain a low TJ, either e or the power
dissipated (or both) must be kept
low. A low ~T is the key to extending semiconductor lifetimes, as it

e = thermal resistance, in units of
°C/watt (or, °CIW).
eJA and eJC are two more specific
terms used in dealing with semiconductor thermal issues, which are
further explained below.

7 -56

HIGH SPEED HARDWARE DESIGN TECHNIQUES

THERMAL BASICS
•

S = Thermal Resistance (OC/W)

•

L\T=PxS

•

SJA = Junction - to - Ambient Thermal Resistance

•

SJC = Junction - to - Case Thermal Resistance

•

SCA = Case - to - Ambient Thermal Resistance

•

SJA = SJC + SCA

•

TJ = TA + (P x SJA), P = Total Device Power Dissipation

•

TJ(Max)

=150°C

(Sometimes 175°C)

Figure 7.47

MAXIMUM POWER DISSIPATION VS. TEMPERATURE
FOR 8-PIN MINI-DIP AND 8-PIN SOIC PACKAGES
2.0
.....

til

i

~

~~PINIMINI-DIPlpAdKAJE

k,

==I
~ 1.5

~
a.

........

.... r-........

(j)

(J)

5

a: 1.0

~a.

:e
:::l
:e 0.5

"- ~

r-........ .........

""r-.......
.

r-........iJr'r-........
8-PIN SOIC PACKAGE

1T = +150°C
I
1

"- "r--.... i'.....

J

...........

..........

~

"

....

-...... ..

:e

o

-50 -40 -30 -20 -10 0 10 20 30 40 50 60
AMBIENT TEMPERATURE - °C

70

80 90

Figure 7.48
7-57

HIGH SPEED DESIGN TECHNIQUES

leads to low maximum junction
tem pera tures.
In semiconductors, one temperature
reference point is al ways the device
junction, taken to mean the hottest spot
inside the chip operating within a given
package. The other relevant reference
point will be either the case of the
device, or the ambient temperature, TA,
that of the surrounding air. This then
leads in turn to the above mentioned
individual thermal resistances, 8JA and
8JC·
Taking the more simple case first, 8JA
is the thermal resistance of a given
device measured between its junction and the ambient air. This thermal
resistance is most often used with
small, relatively low power ICs
which do not dissipate serious
. amounts of power, that is 1W or
less. 8JA figures typical of op amps
and other small devices are on the
order of 90-100°CIW for a plastic 8
pin DIP package. It must be understood that thermal resistances are
highly package dependent, as different materials have differing degrees
of thermal conductivity. As a general
rule of thumb, thermal resistance for
the conductors within packaging
materials is closely analogous to
electrical resistances, that is copper
is the best, followed by aluminum,
steel, and so on. Thus copper lead
frame packages offer the highest
performance (lowest 8).
A summary of the thermal resistances
of various IC packages is shown in
Figures 7.49 and 7.50. In general,
most of these packages do not lend
themselves to easy heat sink attachment (with notable exceptions, such
as the older round metal can types).
Devices which are amenable to heat
7-58

sink attachment will often be noted
by a 8JC dramatically lower than
the 8JA. See for example the 15
pin SIP package (used by the
AD815).
9JC is the thermal resistance of a given
device as measured between its junction and the device case. This form is
most often used with larger power
semiconductors which do dissipate
significant amounts of power, that is
typically more than 1W. The reason for
this is that a heat sink generally must
be used with such devices, to maintain
a sufficiently low internal junction
temperature. A heat sink is simply an
additional low thermal resistance
device attached externally to a semiconductor part to aid in heat removal. It will have some additional
thermal resistance of its own, also
rated in °CIW.
Rather than just a single number, 8 in
this case will be com posed of more than
one component, i.e., 81, 82, etc. Like
series resistors, thermal i;mpedances
add, making a net calculation relatively
simple. For example, to compute a net
9JA given a relevant 8JC, the thermal
resistance of the heat sink, 8CA, or
case to ambient is added to the 8JC
as:
9JA = 8JC + 8CA
and the result is the 8JA for that specific circumstance.
A second form of the general overall
rela tionship between TJ, TA, P and 8
is:
TJ = TA + (P x 8)
To take a real world example, the
AD815AVR power-tab packaged op

HIGH SPEED IlARDWARE DESIGN TECHNIQUES

STANDARD PACKAGE THERMAL RESISTANCES-1
Package

ADI designation

8JA (OCIW)

9JC (OC/W)

N-8
D-8
R-8
R-8
H-08A (TO-99)

90
110
160
90
150

22
60
60
45

10 pin metal can

H-10A (TO-100)

150

25

AD582

12 pin metal can

H-12A (TO-8)

100

30

AD841

14 pin plastic DIP
14 pin ceramic DIP
14 pin sOle

N-14
0-14
R-14

150
110
120

30

AD713
AD585
AD813

15 pin SIP

Y-15

41

2

AD815 Through-Hole

16 pin plastic DIP
16 pin ceramic DIP
16 pin SOIC

N-16
D-16
R-16

120
95
85

40
22

8
8
8
8
8

pin
pin
pin
pin
pin

plastic DIP
ceramic DIP
SOIC
SOIC
metal can

Comment
AD823
AD712
ADP3367 Thermal Coastline
OP07

AD524
AD811

Figure 7.49

STANDARD PACKAGE THERMAL RESISTANCES - 2
Package

ADI designation

9JA (OCIW)

9JC (OCIW)

Comment

18 pin ceramic DIP D-18

120

35

AD7575

20 pin plastic DIP
N-20
20 pin ceramic DIP 0-20
20 pin SOIC
R-20

102
70
74

31
10
24

24 pin plastic DIP
N-24
24 pin ceramic DIP 0-24

105
120

35
35

28 pin plastic DIP
N-28
28 pin ceramic DIP 0-28
28 pin SOIC
R-28

74
51
71

24
8
23

AD7547

Figure 7.50
7-59

HIGH SPEED DESIGN TECHNIQUES

!JITnn
'-4 ......

'hOCl

1' ....'-4 ....

0
""'

t:\ T

A

"tlfi

V.L

-:E".L

'-'I"

nAt
AT
A
----UA.'&'

-~

nt' A 10f""ItXT ...... y.;+1..

VY~~.1~

~~v

additional heat sinking (the device
simply operating in still air). Using it
just as this would allow a power of:
P

=(TJ -

TN/ 9JA

or, (150°C - 70°C)/41°C IW, which
results in an allowable power of about
2W.
However, such a mode of operation falls
short of the device's full power handling
capacity. The AD815AVR's 9JC is quite
low at about 2°CIW, and if a heat sink
of significantly less than 38°CIW is used
with it, then it can dissipate much more
power for a given junction temperature.
A 20°CIW heat sink will allow almost
twice the power to be dissipated by the
same device, simply because of the
lower net 8JA only 22°CIW. This can be
accomplished by a double-sided PCB
copper plane area of 1k mm 2 [see
Reference 1].
To illustrate, the general relationship
of the AD815AVR and PCB heat sink

1~ -~hnW'n
- - - " .. -

--

hv
l?i0"11'ro
7 h:1 Tn
-J
- -b ...... • ......... .., ...

4 ......

the first example cited above, full
advantage of PCB heat sink area
was not taken, and as the graph
shows, the net 8JA can be reduced
to as low as =17°CIW by increasing
the heat sink area further. The
tradeoff is simply one of board area,
and with a 2k mm2 heat sink area,
nearly 5W of power can be handled
by the same device, assuming the
same AT and max TJ. Of course, for
the AD815 (and other devices) even
more conservative operation is
optionally possible by holding to a
lower maximum TJ.
Note that for the data of Figure 7.51,
these data assume that the AD815AVR
is soldered directly to one of the dual
copper PCB planes.
The power tab style package used
with the AD815AVR can also be
used with conventional PC mounted
heat sinks, with 8JC of 20°CIW and
less. See Reference 2.

AD815AVR AND PCB HEAT SINK 9JA VS.
PCB HEAT SINK AREA
35

30

~

~ 25

'" "

()

°I

~

c:(

~..,

20

15

10

AD815AVR, A Y (9JC = 2°CIW)

o

~

-

0.5k
1k
1.5k
2k
COPPER HEAT SINK AREA (TOP AND BOTTOM) - mm 2

Figure 7.51
7-60

10.....

2.5k

HIGH SPEED HARDWARE DESIGN TECHNIQUES

Calculating Power In Various Devices
In all instances of thermal calculations, a basic assumption is that the
power is the total for a given package. With many modern devices
now using more than one supply,
the net total power dissipated will be
the sum of all individual supply
quiescent powers, plus any load
dependent power. For many low
output current op amps for example,
total power will then be essentially
the same as the quiescent. As long
as this is safely less than the package can support, there is little worry.
However, with some devices operable over a wide range of supply
voltages, there are instances where
high supply voltages and a medium
to high quiescent current plus load
current can be a problem.
.
The AD811 is such an example,
being capable of operation from ±5V
to ±15V, with a quiescent current of
about 16mA. If operated at ±15V,
the quiescent dissipation is nearly
500mW, which with a 90°CIW eJA,
will push TJ to about 115°C in a
70°C ambient, high enough for
concern. If the signal voltage output
for such an amplifier doesn't require
the ±15V supplies, then reducing the

supplies will lower the quiescent
power, and TJ.
To illustrate a general relationship of
the power dissipated in an op amp
and the power in a load for family of
supply voltages, Figure 7.52 was
prepared. This is a test simulation of
a standard gain-of-2 non inverting
amplifier driving a 1500 load, with
1kO gain and feedback resistors.
Assuming an input voltage of 1V DC,
the 2V output across the net resistor
load of 150n I 12kO=140n will produce a power P r of about 29mW.
The AD817 amplifier operates over a
supply range of ±5V to ±15V, which
is the Vs sweep range for the test
circuit. The op amp quiescent power
P q increases to 210mW at ±15V,
while the signal power P s dissipated
by the op amp increases to 187mW
at ±15V. The total power in the op
amp is their sum, 397mW at ±15V.
Clearly, operating relatively high
current and low voltage loads from
an op amp does waste considerable
power, and lower voltage supplies
will be much more efficient, where
allowable.

7-61

HIGH SPEED DESIGN TECHNIQUES

AD817 OP AMP POWER DISSIPATION VS. SUPPLY VOLTAGE
Ps + Pq =TOTAL
OPAMPPOWER

400

POWER
(mW)

+2V
300

Pq = QUIESCENT POWER

200

Ps = SIGNAL POWER

100

Pr = LOAD POWeR

0
0

5

10

15

±VS, VOLTS

Figure 7.52

Where appropriate, a clip on DIP
compatible heat sink such as the
AAVID 580100 can be used [Reference 3]. This series has sinks compatible with ICs of 8 through 40 pin
sizes, using a staggered fin design.
Performance of these (and all) heat
sinks is enhanced by air movement,
either through forced convection, or
as a minimum, by arranging PCB
cards vertically to enhance natural
convection.
AID converters can consume considerable power, although the trend
is towards lower voltage and lower
power dissi pa tion. Like op amps,
they are generally analyzed by adding up the total power in the package, which can then be used with
the package's 9JA to compute junction temperature. In adding various

7-62

power totals, some care should be
made to ascertain if any power is
clock dependent. In some CMOS
based designs, there can be appreciable differences in power as a
function highllow clock speed as
shown in Figure 7.53 for the
AD9220 12-bit, 10MSPS ADC.
For example, the AD9042 12 bit
AID consumes about 600mW total on
two 5V supplies, and its 28 pin DIP
package has a 9JA of 34°CIW. What
will be the max TJ for this part in a
TA of 7DOC? You should get a TJ of
90.4°C (LlT = 0.6W x 34°CIW =
20.4°C, so TJ for TA of 70°C, = 70°C+
20.4°C). This particular part is therefore in good shape for this TA, assuming that there are no adjacent "hot
spot" sources to increase the device's
effective T A.

HIGH SPEED HARDWARE DESIGN TECHNIQUES

AD9220 12-BIT, 10MSPS CMOS ADC POWER DISSIPATION
VS. SAMPLING CLOCK FREQUENCY
300r---~--~----~--~--~----~--~~

280r---~---+----~--~---+--~~~4-~

~ 260~--4----+----~~4----+~~~--~~
I

a::
w
3=

2

240~~9----+--~~--4----+----~--4-~

220~--4----+----~--4----+--~~--~~

200~--~--~----~--~--~--~~--~~

o

2

4

6

8

10

12

14

CLOCK FREQUENCY - MHz

Figure 7.53

Airflow Control
For large power dissipations and/or
to maintain low TJ's, forced air
movement can be used to increase air
flow and aid in heat removal. In its
most simple form this can consist of
a continuously or thermostatically
operated fan, directed across high
temperature, high wattage dissipation devices such as CPUs, DSP
chips, etc.
Quite often however, more sophisticated temperature control is necessary.
Recent temperature monitoring and
control ICs such as the TMP12, an
airflow temperature sensor IC, lend
themselves to such applications.
The TMP12 includes on chip two comparators, a voltage reference, a temperature sensor and a heater. The
heater is used to force a predictable

internal temperature rise, to match a
power Ie such as a microprocessor. The
temperature sensing and control portions of the IC can then be programmed to respond to the
temperature changes and control an
external fan, so as to maintain some
range of temperature. Compared to
a simple thermostat, this allows
infinite resolution of user control for
control points and ON/OFF hysteresis.
The device is placed in an airstream
near the power IC, such that both
see the same stream of air, and will
thus have like temperature profiles,
assuming proper con trol of the
stream. This is shown in basic form
by the layout diagram of Figure
7.54.
7-63

HIGH SPEED DESIGN TECHNIQUES

SYSTEM USE OF TMP12 AIRFLOW SENSOR

PGA
PACKAGE

AIR FLOW

1 I~C.
\ I; ;I,l.ri-

PGA
SOCKET

POWER

PC BOARD

TMP12

Figure 7.54

With the TMP12's internal 250mW
heater ON and no airflow, the TMP12
thermal profile will look like the
curve "A;' of Figure 7.55, and will
show a 20°C rise above TA. When
airflow is provided, this same dissipation results in a lower temperature, "D". In programming the device
for airspeed control, the designer
can set up to two switch points,
shown here symbolically by "B" and
"C", which are HIGH and LOW
setpoints, respectively. The basic
idea is that when the IC substrate

7-64

reaches point B in temperature, the
external fan will be turned on to
crea te the airstream, and lower the
temperature. If the overall system
setup is reasonable in terms of
thermal profiling, this small Ie can
thus be used to indirectly control
another larger and independent
power source with regard to its
temperature. Note that the dual
mode control need not necessarily
be used, in all applications. An
unused comparator is simply wired
high or low.

HIGH SPEED IlARDWARE DESIGN TECHNIQUES

TMP12 TEMPERATURE RELATIONSHIPS
65

a---.-_"_
60

0;

a:
:;)

~

ffi

55
c

50

/

Q.

:iE
w

~ 45

C

a. TMP12 DIE TEMP NO AIR FLOW
b. HIGH SET POINT
c. LOW SET POINT
d. TMP12 DIE TEMP MAX AIR FLOW
e. SYSTEM AMBIENT TEMPERATURE

40

e

35
0

50

100

150

200

250

TMP12 Po (mW)

Figure 7.55

Figure 7.56 shows a circuit diagram
using the TMP 12 as a general purpose controller. The device is connected to a 5V supply, which is also
used to power a control relay and
the TMP12's internal heater at pin 5.
Setpoint programming of the TMP12
is accomplished by the resistor
string at pins 4 through 1, R1 - R3.
These resistors establish a current
drain from the internal reference
source at pin 4, which sets up a
reference current, IREF, which is set
as:

In this expression, THYs is the hysteresis temperature swing desired
about the setpoint, in °C, and the
7JlA is recommended minimum
loading of the reference. For a 2°C

hysteresis for example, IREF is
17JlA; for 5°C, it would be 32pA.
Given a desired setpoint temperature
in °C, the setpoint can be converted
to a corresponding voltage. Although
not available externally, the internal
temperature dependent voltage of
the TMP12 is scaled at 5mVfOC, and
is equal to 1.49V at 25°C.
To convert a setpoint temperature to a
voltage VSETPOINT,
VSETPOINT = 1.49V + [5mV/oC x
(TSETPOINT - T25) ]
where TSETPO INT is the desired
setpoint temperature, and T25 is 25°C.
For a 50°C high setpoint, this works out
to be VSETPOINT(HI) = 1.615V. For a
lower setpoint of 35°C, the voltage
VSETPOINT(LO) would be 1. 59V.
7-65

HIGH SPEED DESIGN TECHNIQUES

The divider resistors are then chosen
to draw the required current IREF
while setting the two tap voltages
corresponding to VSETPOINT(HI)
and VSETPOINT(LO).

RTOTAL = VREF /IREF
= 2.5V / IREF
Rl = [VREF - VSETPOINT(HI) ]/ IREF
= [ 2.5V - VSETPOINT(HI) ]/ IREF
R2= [VSETPOINT(HI)
- VSETPOINT(LO)] /IREF
R3 = VSETPOINT(LO) /IREF

In the example of the figure, the
resulting standard values for R1 - R3
correspond to the temperature/
voltage setpoint examples noted
above. Ideal 1% values shown give
resistor related errors of only 0.1°C
from ideal. Note that this is error is
independent of the TMP12 temperature errors, which are ±2°C.
As noted above, both comparators of
the device need not always be used, and
in this case the lower comparator
output is not used. For a single point
50°C controller, the 35°C setpoint is
superfluous. One resistor can be eliminated by making R2 + R3 a single value

7-66

of 95.3kn and connecting pin 3 to
GND. Pin 6 should· be left as a noconnect. If a greater hysteresis is
desired, the resistor values will be
proportionally lowered.
It is also important to minimize potential parasitic temperature errors associated with the TMP12. Although the
open-collector outputs can sink up to
20mA, it is advised that currents be
kept low at this node, to limit any
additional temperature rise. The Ql Q2 transistor buffer shown in the
figure raises the current drive to
100mA, allowing a 50nJ5V coil to
be driven. The relay type shown is
general purpose, and many other
power interfaces are possible with
the TMP12. If used as shown, the
relay contacts would be used to turn
on a fan for airflow when the active
low output at pin 7 changes, indicating the upper setpoint threshold.
A basic assumption of the TMP12's
operation is that it will "mimic" another device in temperature rise.
Therefore, a practical working system must be arranged and tested for
proper airflow channeling, minimal
disturbances from adj acent devices,
etc. Some experimentation should
be expected before a final setup will
result.

HIGH SPEED IIARDWARE DESIGN TECHNIQUES

TMP12 50° SETPOINT CONTROLLER
+5V

TMP12

R1

TO FAN OR
COOUNG DEVICE

LO

)

~

TEMPERATURE
SENSOR AND
VOLTAGE
REFERENCE

SPDTRELAY
5V COIL, 50n MIN
OMRON G2R·14·DC5
Q1, Q2 2N2222

=

R2

=

R3
HYSTERESIS
GENERATOR

=

FOR THYS 2°C, IREF 17~A
SETPOINT (HI) 50°C
SETPOINT (LO) 35°C (IF USED)
R1 = 52.31<0
R2 = 4.421<0 OR 95.31<0
R3 = 90.91<0

=
=

J

VREF
I
----REF - R1 + R2 + R3

Figure 7.56

7-67

HIGH SPEED DESIGN TECHNIQUES

REFERENCES: THERMAL MANAGEMENT
1.

Power Consideration Discussions, AD815 Dat~ Sheet, Analog Devices.

2.

Heat Sinks for Multiwatt® Packages, AAYID Engineering, Inc., One Kool
Path, Laconia, NH, 03246, (603) 528-3400.

3.

General Catalog, AAYID Engineering, Inc., One Kool Path, Laconia, NH,
03246, (603) 528-3400.

7-68

HIGH SPEED IlARDWARE DESIGN TECHNIQUES

EMIIRFI CONSIDERATIONS
Adolfo A. Garcia
Electromagnetic interference (EM!) has
become a hot topic in the last few years
among circuit designers and systems
engineers. Although the subject matter
and prior art have been in existence for
over the last 50 years or so, the advent
of portable and high-frequency industrial and consumer electronics has
provided a comfortable standard of

living for many EMI testing engineers,
consultants, and publishers. With the
help ofEDN Magazine and Kimmel
Gerke Associates, this section will
highlight general issues of EMC (~lec­
tromagnetic ~ompatibility) to familiarize the system/circuit designer with this
subject and to illustrate proven techniques for protection against EM!.

A PRIMER ON EMI REGULATIONS
The intent of this section is to summarize the different types of electromagnetic compatibility (EMC) regulations
imposed on equipment manufacturers,
both voluntary and mandatory. Published EMC regulations apply at this
time only to equipment and systems,

and not to components. Thus, EMI
hardened equipment does not necessarily imply that each of the components
used (integrated circuits, especially) in
the equipment must also be EMI hardened.

Commercial Equipment
The two driving forces behind commercial EMI regulations are the FCC
(Federal Communications Commission)
in the U. S. and the VDE (Verb and
Deutscher Electrotechniker) in Germany. VDE regulations are more
restrictive than the FCC's with regard
to emissions and radiation, but the
European Community will be adding
immunity to RF, electrostatic discharge, and power-line disturbances to
the VDE regulations, and now requires
mandatory compliance. In Japan,
commercial EMC regulations are covered under the VCCI (Voluntary Control Council for Interference) standards
and, implied by the name, are much
looser than their FCC and VDE counterparts.

All commercial EMI regulations primarily focus on radiated emissions, specifically to protect nearby radio and
television receivers, although both FCC
and VDE standards are less stringent
with respect to conducted interference
(by a factor of 10 over radiated levels).
The FCC Part 15 and VDE 0871 regulations group commercial equipment
into two classes: Class A, for all products intended for business environments; and Class B, for all products
used in residential applications. For
example, Table 7.1 illustrates the
electric-field emission limits of commercial computer equipment for both FCC
Part 15 and VDE 0871 compliance.

7-69

HIGH SPEED DESIGN TECHNIQUES

Radiated Emission Limits for Commercial Computer Equipment
Frequency (MHz)

Class A
(at 3 m)
300 p.V/m
500 p.V/m
700 p.V/m

30 - 88
88 - 216
216 - 1000

Class B
(at 3 m)
100 p.V/m
150 p.V/m
200 p.V/m

Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING

COMPANY 1995, A Division of Reed Publishing USA.
Table 7.1

In addition to the already stringent
VDE emission limits, the European
Community EMC standards (IEC and
IEEE) now requires mandatory compliance to these additional EMI threats:
Immunity to RF fields, electrostatic
discharge, and power-line disturbances.
All equipment/systems marketed in
Europe must exhibit an immunity to

RF field strengths of 1-10V/m (lEC
standard 801-3), electrostatic discharge
(generated by human contact or
through material movement) in the
range of 10-15kV (IEC standard 801-2),
and power-line disturbances of 4kV
EFTs (extremely fast transients, IEC
standard 801 .. 4) and 6kV lightning
surges (IEEE standard C62.41).

Military Equipment
The defining EMC specification for
military equipment is MIL-STD-461
which applies to radiated equipment
emissions and equipment susceptibility
to interference. Radiated emission
limits are very typically 10 to 100 times

more stringent than the levels shown in
Table 7.1. Required limits on immunity
to RF fields are typically 200 times
more stringent (RF field strengths of 550mV/m) than the limits for commercial
equipment.

Medical Equipment
Although not yet mandatory, EMC
regulations for medical equipment are
presently being defined by the FDA
(Food and Drug Administration) in the
USA and the European Community.
The primary focus of these EMC regulations will be on immunity to RF fields,

7-70

electrostatic discharge, and power-line
disturbances, and may very well be
more stringent than the limits spelled
out in MIL-STD-461. The primary
objective of the medical EMC regula ..
tions is to guarantee safety to humans.

HIGH SPEED IlARDWARE DESIGN TECHNIQUES

Industrial- and Process-Control Equipment
Presently, equipment designed and
marketed for industrial- and processcontrol applications are not required to
meet pre-existing mandatory EMC
regulations. In fact, manufacturers are
exempt from complying to any standard

in the USA However, since industrial
environments are very much electrically hostile, all equipment manufacturers will be required to comply with all
European Community EMC regulations
in 1996.

Automotive Equipment
Perhaps the most difficult and hostile
environment in which electrical circuits
and systems must operate is that found
in the automobile. All of the key EMI
threats to electrical systems exist here.
In addition, operating temperature
extremes, moisture, dirt, and toxic
chemicals further exacerbate the problem. To complicate matters further,
standard techniques (ferrite beads,
feed-through capacitors, inductors,
resistors, shielded cables, wires, and
connectors) used in other systems are
not generally used in automotive applications because of the cost of the additional components.
Presently, automotive EMC regulations, defined by the very comprehensive SAE Standards J551 and J1113,
are not yet mandatory. They are,

however, very rigorous. SAE standard
J551 applies to vehicle-level EMC
specifications, and standard J1113
(functionally similar to MIL-STD-461)
applies to all automotive electronic
modules. For example, the J1113
specification requires that electronic
modules cannot radiate electric fields
greater than 300nV/m at a distance of3
meters. This is roughly 1000 times
more stringent than the FCC Part 15
Class A specification. In many applications, automotive manufacturers are
imposing J1113 RF field immunity
limits on each of the active components
used in these modules. Thus, in the
very near future, automotive manufacturers will require that IC products
comply with existing EMC standards
and regulations.

EMC Regulations' Impact on Design
In all these applications and many
more, complying with mandatory EMC
regulations will require careful design
of individual circuits, modules, and
systems using established techniques
for cable shielding, signal and powerline filtering against both small- and

large-scale disturbances, and sound
multi-layer PCB layouts. The key to
success is to incorporate sound EMC
principles early in the design phase to
avoid time-consuming and expensive
redesign efforts.

7-71

HIGH SPEED DESIGN TECHNIQUES

A DIAGNOSTIC FRAMEWORK FOR EMIlRFI PROBLEM SOLVING
With any problem, a strategy should be
developed before any effort is expended
trying to solve it. This approach is
similar to the scientific method: initial
circuit misbehavior is noted, theories
are postulated, experiments designed to
test the theories are conducted, and
results are again noted. This process
continues un til all theories have been
tested and expected results achieved
and recorded. With respect to EMI, a
problem solving framework has been
developed. As shown in Figure 7.57, the

model suggested by Kimmel-Gerke in
[Reference 1] illustrates that all three
elements (a source, a receptor or victim,
and a path between the two) must exist
in order to be considered an EMI problem. The sources of electromagnetic
interference can take on many forms,
and the ever-increasing number of
portable instrumentation and personal
communications/computation equipment only adds the number of possible
sources and receptors.

A DIAGNOSTIC FRAMEWORK FOR EMI
Reprinted from EON Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

ANY INTERFERENCE PROBLEM CAN BE BROKEN DOWN INTO:

•
•
•

The SOURCE of interference
The RECEPTOR of interference
The PATH coupling the source to the receptor
SOURCES
Microcontroller
+ Analog
+ Digital
ESD
Communications
Transmitters
Power
Disturbances
Lightning

PATHS

Radiated
Microcontroller
+ EM Fields
+ Analog
+ Crosstalk
+ Digital
Capacitive
Inductive Communications
+ Receivers
Conducted
+ Signal
Other Electronic
+ Power
Systems
+ Ground

Figure 7.57

7-72

RECEPTORS

HIGH SPEED IIAImWARE DESIGN TECHNIQUES

Interfering signals reach the receptor
by conduction (the circuit or system
interconnections) or radiation (parasitic
mutual inductance and/or parasitic
capacitance). In general, if the frequencies of the interference are less than
30MHz, the primary means by which
interference is coupled is through the
interconnects. Between 30MHz and
300MHz, the primary coupling mechanism is cable radiation and connector
leakage. At frequencies greater than
300MHz, the primary mechanism is
slot and board radiation. There are
many cases where the interference is
broadband, and the coupling mechanisms are combinations of the above.

When all three elements exist together,
a framework for solving any EMI
problem can be drawn from Figure
7.58. There are three types of interference with which the circuit or system
designer must contend. The first type of
interference is that generated by and
emitted from an instrument; this is
known as circuit/system emission and
can be either conducted or radiated. An
exam pIe of this would be the personal
computer. Portable and desktop computers must pass the stringent FCC
Part 15 specifications prior to general
use.

THREE TYPES OF INTERFERENCE
EMISSIONS - IMMUNITY - INTERNAL
Reprinted from EON Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

HANDHELD
TRANSMITTER
RADIO

TRANSMITTER~

LIGHTNING---.....;>~I

\

RADIATED
EMISSIONS

INTERNAL
ELECTRONICS
CONDUCTED
EMISSIONS

POWER
DISTURBANCE

Figure 7.58
7-73

HIGH SPEED DESIGN TECHNIQUES

The second type of interference is
circuit or system immunity. This describes the behavior of an instrument
when it is exposed to large electromagnetic fields, primarily electric fields
with an intensity in the range of 1 to
10V/m at a distance of 3 meters. Another term for immunity is susceptibility, and it describes circuit/system
behavior against radiated or conducted
interference.
The third type of interference is internal. Although not directly shown on the
figure, internal interference can be
high-speed digital circuitry within the
equipment which affects sensitive
analog (or other digital circuitry), or
noisy power supplies which can contaminate both analog and digital circuits. Internal interference often occurs
between digital and analog circuits, or
between motors or relays and digital
circuits. In mixed signal environments,
the digital portion of the system often
interferes with analog circuitry. In
some systems, the internal interference
reaches such high levels that even very
high-speed digital circuitry can affect
other low-speed digital circuitry as well
as analog circuits.
In addition to the source-path-receptor
model for analyzing EMI-related problems, Kimmel Gerke Associates have
also introduced the FAT-ID concept
[Reference 1]. FAT-ID is an acronym
that describes the five key elements
inherent in any EM! problem. These
five key parameters are: frequency,
amplitude, time, impedance, and distance.
The frequency of the offending signal
suggests its path. For example, the
path of low-frequency interference is
often the circuit conductors. As the
interference frequency increases, it will
take the path of least impedance,
usually stray capacitance. In this case,
7-74

the coupling mechanism is radiation.
Time and frequency in EM! problems
are interchangeable. In fact, the physics of EM! have shows that the time
response of signals contains all the
necessary information to construct the
spectral response of the interference. In
digi tal systems, both the signal rise
time and pulse repetition rate produce
spectral components according to the
following relationship:
1
fEMI=--1t. trise

Eq.7.1

For example, a pulse having a Ins rise
time is equivalent to an EMI frequency
of over 300MHz. This time-frequency
relationship can also be applied to highspeed analog circuits, where slew rates
in excess of 1000V/ps and gain-bandwidth products greater than 500MHz
are not uncommon.
When this concept is applied to instruments and systems, EMI emissions are
again functions of signal rise time and
pulse repetition rates. Spectrum analyzers and high speed oscilloscopes used
with voltage and current probes are
very useful tools in quantifying the
effects of EMI on circuits and systems.
Another important parameter in the
analysis of EMI problems is the physical dimensions of cables, wires, and
enclosures. Cables can behave as either
passive antennas (receptors) or very
efficient transmitters (sources) of interference. Their physical length and their
shield must be carefully examined
where EMI is a concern. As previously
mentioned, the behavior of simple
conductors is a function of length, crosssectional area, and frequency. Openings
in equipment enclosures can behave as
slot antennas, thereby allowing EMI
energy to affect the internal electronics.

HIGH SPEED IlAImWARE DESIGN TECHNIQUES

PASSIVE COMPONENTS: YOUR ARSENAL AGAINST
Minimizing the effects of EMI requires
that the circuit/system designer be
completely aware of the primary arsenal in the battle against interference:
passive components. To use successfully
these components, the designer must
understand their non-ideal behavior.
For example, Figure 7.59 illustrates the
real behavior of the passive components used in circuit design. At very
high frequencies, wires become transmission lines, capacitors become inductors, inductors become capacitors, and
resistors behave as resonant circuits.
A specific case in point is the frequency
response of a simple wire compared to
that ofa ground plane. In many circuits, wires are used as either power or
signal returns, and there is no ground

EMI

plane. A wire will behave as a very low
resistance (less than O.02n1ft for 22gauge wire) at low frequencies, but
because of its parasitic inductance of
approximately 20nWinch, it becomes
inductive at frequencies above 13kHz.
Furthermore, depending on size and
routing of the wire and the frequencies
involved, it ultimately becomes a transmission line with an uncontrolled
impedance. From our knowledge of RF,
unterminated transmission lines become antennas with gain. On the other
hand, large area ground planes are
much more well-behaved, and maintain
a low impedance over a wide range of
frequencies. With a good understanding
of the behavior of real components, a
strategy can now be developed to find
solutions to most EMI problems.

ALL PASSIVE COMPONENTS EXHIBIT
"NON IDEAL" BEHAVIOR
Reprinted from EDN Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

COMPONENT

LF BEHAVIOR

HF BEHAVIOR

RESPONSE

z
11

II

0----l\fV'v---0

~

/

/

1\

II

\.,/ \ j

/

I

WIRE

f

j<

0---1~

o-fffi--1~

Z

t------'\ //'
\/

CAPACITOR

-B)))) )))))-

o-----IOR-o

INDUCTOR

-()

}-

RESISTOR

o--l\M--o

• f

z

Lrfur I------jf>( .
~zl

'\

/

\
\ I
\{

/

f

/

/

• f

Figure 7.59
7-75

HIGH SPEED DESIGN TECHNIQUES

RADIO FREQUENCY INTERFERENCE
The world is rich in radio transmitters:
radio and TV stations, mobile radios,
computers, electric motors, garage door
openers, electric jackhammers, and
countless others. All this electrical
activity can affect circuit/system performance and, in extreme cases, may
render it inoperable. Regardless of the
location and magnitude of the interference, circuits/systems must have a
minimum level of immunity to radio
frequency interference (RFI). The next
section will cover two general means by
which RFI can disrupt normal instrument operation: the direct effects of
RFI sensitive analog circuits, and the
effects of RFI on shielded cables.
Two terms are typically used in describing the sensitivity of an electronic
system to RF fields. In communications,
radio engineers define immunity to be
an instrument's susceptibility to the
applied RFI power density at the unit.
In more general EMI analysis, the
electric-field intensity is used to describe
RFI stimulus. For comparative purposes, Equation 7.2 can be used to
convert electric-field intensity to power
density and vice-versa:

E (:) =61.4 ~Pr(:~)

Eq.7.2

where E = Electric Field Strength, in
volts per meter, and
PT = Transmitted power, in
milliwatts per cm 2.
From the standpoint of the source-pathreceptor model, the strength of the
electric field, E, surrounding the receptor is a function of transmitted power,
antenna gain, and distance from the
7-76

source of the disturbance. An approximation for the electric-field intensity
(for both near- and far-field sources) in
these terms is given by Equation 7.3:

(V)= 5.5(~Prrd.GA)

E m

Eq.7.3

where E =Electric field intensity, in V/
m;

PT = Transmitted power, in
mW/cm 2 ;
=Antenna gain (numerical);
and
d = distance from source, in
meters

GA

For example, a 1W hand-held radio at a
distance of 1 meter can generate an
electric-field of 5.5V/m, whereas a
10kW radio transmission station located lkm away generates a field
smaller than 0.6V/m.
Analog circuits are generally more
sensitive to RF fields than digital
circuits because analog circuits, operating at high gains, must be able to
resolve signals in the microvolt/millivolt
region. Digital circuits, on the other
hand, are more immune to RF fields
beca use of their larger signal swings
and noise margins. As shown in Figure
7.60, RF fields can use inductive and/or
capacitive coupling paths to generate
noise currents and voltages which are
amplified by high-impedance analog
instrumentation. In ma~ cases, out-ofband noise signals are detected and
rectified by these circuits. The result of
the RFI rectification is usually unexplained offset voltage shifts in the
circuit or in the system.

HIGH SPEED IlAImWARE DESIGN TECHNIQUES

RFI CAN CAUSE RECTIFICATION IN
SENSITIVE ANALOG CIRCUITS
Reprinted from EON Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

•

INPUTS PICK UP HIGH FREQUENCY ENERGY ON
SIGNAL LINE, WHICH IS DETECTED BY THE AMPLIFIER

VCC

•

•

OUTPUT DRIVERS CAN BE JAMMED, TOO: ENERGY
COUPLES BACK TO INPUT VIA VCC OR SIGNAL LINE
AND THEN IS DETECTED OR AMPLIFIED

Figure 7.60

KEEPING RFI AWAY FROM ANALOG CIRCUITS
Reprinted from EON Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

REMOTE

LOCAL

•

Decouple all voltage supplies to analog chip with high-frequency capacitors

•

Use high-frequency filters on all lines that leave the board

•

Use high-frequency filters on the voltage reference if it is not grounded
Figure 7.61
7-77

HIGH SPEED DESIGN TECHNIQUES

There are techniques that can be used
to protect analog circuits against in terference from RF fields (see Figure 7.61).
The three general points of RFI coupling are signal inputs, signal outputs,
and power supplies. At a minimum, all
power supply pin connections on analog
and digital ICs should be decoupled
with O.lpF ceramic capacitors. As was
shown in Reference 3, low-pass filters,
whose cutoff frequencies are set no
higher than 10 to 100 times the signal
bandwidth, can be used at the inputs
and the outputs of signal conditioning
circuitry to filter noise.

the highest RF interference frequency
expected. As illustrated in Figure 7.62,
real low-pass filters may exhibit leakage at high frequencies. Their inductors
can lose their effectiveness due to
parasitic capacitance, and capacitors
can lose their effectiveness due to
parasitic inductance. A rule of thumb is
that a conventional low-pass filter
(made up ofa single capacitor and
inductor) can begin to leak when the
applied signal frequency is 100 to 1000
higher than the filter's cutoff frequency.
For example, a 10kHz LPF would not
be considered very efficient at filtering
frequencies above 1MHz.

Care must be taken to ensure that the
low pass filters (LPFs) are effective at

A SINGLE LOW PASS FILTER LOSES EFFECTIVENESS
AT 100 -1000 f3dB
Reprinted from EON Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

TYPICALLY 100 • 1000 f3d8

FILTER
ATTENUATION

,f3dB
FREQUENCY

Figure 7.62
7-78

HIGH SPEED IIARDWARE DESIGN TECHNIQUES

Rather than use one LPF stage, it is
recommended that the interference
frequency bands be separated into lowband, mid-band, and high-band, and
then use individual filters for each
band. Kimmel Gerke Associates use the
stereo speaker analogy of woofermidrange-tweeter for RFI low-pass filter
design illustrated in Figure 7.63. In
this approach, low frequencies are
grouped from 10kHz to 1MHz, midband frequencies are grouped from
1MHz to 100MHz, and high frequencies
grouped from 100MHz to IGHz. In the
case of a shielded cable input/output,
the high frequency section should be
located close to the shield to prevent
high-frequency leakage at the shield
boundary. This is commonly referred to
as feed-through protection. For applications where shields are not required at

the inputs/outputs, then the preferred
method is to locate the high frequency
filter section as close the analog circuit
as possible. This is to prevent the
possibility of pickup from other parts of
the circuit.
Another cause of filter failure is illustrated in Figure 7.64. If there is any
impedance in the ground connection (for
example, a long wire or narrow trace
connected to the ground plane), then
the high-frequency noise uses this
impedance path to bypass the filter
completely. Filter grounds must be
broadband and tied to low-impedance
points or planes for optimum performance. High frequency capacitor leads
should be kept as short as possible, and
low-inductance surface-mounted ceramic chip capacitors are preferable.

MULTISTAGE FILTERS ARE MORE EFFECTIVE
Reprinted from EDN Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

FEEDTHROUGH

CAPACITOR

TWEETER

FERRITE

/

BEAD

IRON

/CORE

MIDRANGE

WOOFER

STEREO SPEAKER ANALOGY

Figure 7.63
7-79

HIGH SPEED DESIGN TECHNIQUES

NON-ZERO (INDUCTIVE ANDIOR RESISTIVE) FILTER
GROUND REDUCES EFFECTIVENESS
Reprinted from EON Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

FILTER

r-------------------------I.

I

EN~~Gyl ~t UVrI
:

. >

)

)

)

>
II

HF
ENERGY

/

L_____________ ___________

I

~

BOND IMPEDANCE

Figure 7.64

SOLUTIONS FOR POWER-LINE DISTURBANCES
The goal of this next section is not to
describe in detail all the circuit/system
failure mechanisms which can result
from power-line disturbances or faults.
Nor is it the intent of this section to
describe methods by which power-line
disturbances can be prevented. Instead,
this section will describe techniques
that allow circuits and systems to
accommodate transient power-line
disturbances.
Figure 7.65 is an example of a hybrid
power transient protection network
commonly used in many applications
where lightning transients or other
power-line disturbances are prevalent.
These networks can be designed to
provide protection against transients as
high as IOkVand as fast as IOns. Gas
discharge tubes (crowbars) and large
geometry zener diodes (clamps) are
used to provide both differential and
common-mode protection. Metal-oxide
7-80

varistors (MOVs) can be substituted for
the zener diodes in less critical, or in
more compact designs. Chokes are used
to limit the surge current until the gas
discharge tubes fire.
Commercial EMI filters, as illustrated
in Figure 7.66, can be used to filter less
catastrophic transients or high-frequency interference. These EMI filters
provide both common-mode and differential mode filtering as in Figure 7.66.
An optional choke in the safety ground
can provide additional protection
against common-mode noise. The value
of this choke cannot be too large, however, because its resistance may affect
power-line fault clearing. These filters
work in both directions: they are not
only protect the equipment from surges
on the power line but also prevent
transients from the internal switching
power supplies from corrupting the
power line.

HIGH SPEED lIARDWARE DESIGN TECHNIQUES

POWER LINE DISTURBANCES CAN GENERATE EMI
Reprinted from EDN Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

GAS DISCHARGE
TUBES
"CROWBARS"
_ _ _A _ __

r --.------1
V ____
LINE

N

TRANSIENT
SUPPRESSORS
BIG ZENERS
OR MOVs
~

-.__---1

- - 7 - -___

LOAD

G-___----~------------~~----~u
•

COMMON-MODE AND DIFFERENTIAL MODE PROTECTION

Figure 7.65

SCHEMATIC FOR A COMMERCIAL POWER LINE FILTER
Reprinted from EDN Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

GND
OPTIONAL

\

NOTE: OPTIONAL CHOKE ADDED FOR COMMON-MODE PROTECTION

Figure 7.66
7-81

HIGH SPEED DESIGN TECHNIQUES

Transformers provide the best commonmode power line isolation. They provide
good protection at low frequencies
«lMHz), or for transients with rise and
fall times greater than 300ns. Most
motor noise and lightning transients
are in this range, so isolation transformers work well for these types of
disturbances. Although the isolation
between input and output is galvanic,
isolation transformers do not provide
sufficient protection against extremely

fast transients «10ns) or those caused
by high-amplitude electrostatic discharge (1 to 3ns). As illustrated in
Figure 7.67, isolation transformers can
be designed for various levels of differential- or common-mode protection. For
differential-mode noise rejection, the
Faraday shield is connected to the
neutral, and for common-mode noise
rejection, the shield is connected to the
safety ground.

FARADAY SHIELDS IN ISOLATION TRANSFORMERS
PROVIDE INCREASING LEVELS OF PROTECTION
Reprinted from EDN Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

•

•
•
•

STANDARD TRANSFORMER - NO SHIELD
•

SINGLE FARADAY SHIELD
• CONNECT TO SAFETY GROUND FOR
COMMON-MODE PROTECTION

SINGLE FARADAY SHIELD
•

CONNECT TO NOISY-5IDE NEUTRAL
WIRE FOR DIFFERENTIAL-MODE
PROTECTION

~
~
)JC
7h=

TRIPLE FARADAY SHIELD
•
•

7-82

NOTE CONNECTION FROM SECONDARY
TO SAFETY GROUND TO ELIMINATE
GROUND-TO-NEUTRAL VOLTAGE

CONNECT TO SAFETY GROUND FOR
COMMON MODE
CONNECT TO NEUTRALS FOR
DIFFERENTIAL MODE

~

HIGH SPEED IlARDWARE DESIGN TECHNIQUES

PRINTED CIRCUIT BOARD DESIGN FOR
This section will summarize general
points regarding the most critical
portion of the design phase: the printed
circuit board layout. It is at this stage
where the performance of the system is
most often com promised. This is not
only true for signal-path performance,
but also for the system's susceptibility
to electromagnetic interference and the
amount of electromagnetic energy
radiated by the system. Failure to
implement sound PCB layout techniques will very likely lead to system!
instrument EMC failures.

EMI PROTECTION

Figure 7.68 is a real-world printed
circuit board layout which shows all the
paths through which high-frequency
noise can couple/radiate int%ut of the
circuit. Although the diagram shows
digital circuitry, the same points are
applicable to precision analog, highspeed analog, or mixed analog/digital
circuits. Identifying critical circuits and
paths helps in designing the PCB
layou t for both low emissions and
susceptibility to radiated and conducted
external and internal noise sources.

METHODS BY WHICH HIGH FREQUENCY ENERGY
COUPLED AND RADIATE INTO CIRCUITRY VIA PLACEMENT
Reprinted from EON Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

COUPLING TO 1/0 VIA
CROSSTALK OR RADIATION

COUPLING VIA COMMON
POWER IMPEDANCE

~c~\----- ---'---~-----+--~~-----t~
v

~c\
V

RADIATION FROM
POWER WIRING

COUPLING VIA COMMON
GROUND IMPEDANCE

RADIATION
FROM I/O
WIRING

Figure 7.68
7-83

HIGH SPEED DESIGN TECHNIQUES

A key point in minimizing noise problems in a design is to choose devices no
faster than actually required by the
application. Many designers assume
that faster is better: fast logic is better
than slow, high bandwidth amplifiers
are clearly better than low bandwidth
ones, and fast DACs and ADCs are
better, even if the speed is not required
by the system. Unfortunately, faster is
not better, but worse where EMI is
concerned.
Many fast DACs and ADCs have digital
inputs and outputs with rise and fall
times in the nanosecond region. Because of their wide bandwidth, the
sampling clock and the digital inputs
and can respond to any form of high
frequency noise, even glitches as narrow as 1 to 3ns. These high speed data
converters and amplifiers are easy prey

for the high frequency noise of microprocessors, digital signal processors,
motors, switching regulators, hand-held
radios, electric jackhammers, etc. With
some of these high-speed devices, a
small amount of input/output filtering
may be required to desensitize the
circuit from its EMIIRFI environment.
Adding a small ferrite bead just before
the decoupling capacitor as shown in
Figure 7.69 is very effective in filtering
high frequency noise on the supply
lines. For those circuits that require
bipolar supplies, this technique should
be applied to both positive and negative
supply lines.
To help reduce the emissions generated
by extremely fast moving digital signals
at DAC inputs or ADC outputs, a small
resistor or ferrite bead may be required
at each digital input/output.

POWER SUPPLY FILTERING AND SIGNAL LINE
SNUBBING GREATLY REDUCES EMI EMISSIONS
Reprinted from EDN Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

FERRITE
BEAD '---...

~

FERRITE BEAD OR
10 - 33n RESISTOR

__

vcc----------+-~--~--.-----~

~

GND--------------------~----~

MICROPROCESSOR
OR OTHER HIGH-SPEED
CLOCKED CIRCUIT

Figure 7.69
7 -84

HIGH SPEED IlARDWARE DESIGN TECHNIQUES

Once the system's critical paths and
circuits have been identified, the next
step in implementing sound PCB layout
is to partition the printed circuit board
according to circuit function. This
involves the appropriate use of power,
ground, and signal planes. Good PCB
layouts also isolate critical analog paths
from sources of high interference (110.
lines and connectors, for example). High
frequency circuits (analog and digital)
should be separated from low frequency
ones. Furthermore, automatic signal
routing CAD layout software should be
used with extreme caution, and critical
paths routed by hand.
Properly designed multilayer printed
circuit boards can reduce EMI emissions and increase immunity to RF
fields by a factor of 10 or more compared to double-sided boards. A multilayer board allows a complete layer to
be used for the ground plane, whereas
the ground plane side of a double-sided
board is often disrupted with signal
crossovers, etc. If the system has sepa-

rate analog and digital ground and
power planes, the analog ground plane
should be underneath the analog power
plane, and similarly, the digital ground
plane should be underneath the digital
power plane. There should be no
overlap between analog and digital
ground planes nor analog and digital
power planes.
The preferred multi-layer board arrangement is to embed the signal traces
between the power and ground planes,
as shown in Figure 7.70. These lowimpedance planes form very highfrequency stripline transmission lines
with the signal traces. The return
current path for a high frequency signal
on a trace is located directly above and
below the trace on the ground/power
planes. The high frequency signal is
thus contained inside the PCB, thereby
minimizing emissions. The embedded
signal trace approach has an obvious
disadvantage: debugging circuit traces
tha t are hidden from plain view is
difficult.

"TO EMBED OR NOT TO EMBED"
THAT IS THE QUESTION
Reprinted from EDN Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

BEFORE

AFTER

Route

Power

Power

:::::::::::::::::::::::::::::::::::::::::::::::::::::.:::::::::::::::::::::::::::::"::::"::::::::::::::::

Route

Ground

::::::~:::::;:::::=:::::;:::::::::::=;::::::::::::::::::::::::::;:=:::::::::::::::":~:;:;:::::::;::::.;:::

Route

Route

Ground
•

•

::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::"::::::::::::::::::::::::::::::::::::::

::::::::::::::::::=:::=:=:=:::::::::::::::=:::::::::::::::::=:::::::::=:::::=:=:::::=:::::::=:=:=:=:::=:::

Advantages of Embedding
•

Lower impedances, therefore lower emissions and crosstalk

•

Reduction in emissions and crosstalk is significant above 50MHz

•

Traces are protected

Disadvantages of Embedding
•

Lower Interboard capacitance, harder to decouple

•

Impedances may be too low for matching

•

Hard to prototype and troubleshoot buried traces

Figure 7.70
7-85

HIGH SPEED DESIGN TECHNIQUES

Much has been written about terminating printed circuit board traces in their
characteristic impedance to avoid
reflections. A good rule-of-thumb to
determine when this is necessary is as
follows: Terminate the line in its characteristic impedance when the one-way
propagation delay of the PCB track is
equal to or greater than one-half the
applied signal rise / fall time (whichever
edge is faster). A conservative approach
is to use a 2 inch (PCB track length)/
nanosecond (rise-, fall-time) criterion.
For example, PCB tracks for high-speed
logic with rise/fall time of 5ns should be
terminated in their characteristic
impedance and if the track length is
equal to or greater than 10 inches
(including any meanders). The 2 inch/
nanosecond track length criterion is
summarized in Figure 7.71 for a number of logic families.
This same 2 inch/nanosecond rule
of thumb should be used with analog circuits in determining the need
for transmission line techniques. For
instance, if an amplifier must output a
maximum frequency offmax, then the
equivalent risetime, t r , can be calculated using the equation tr = 0.35/fmax'
The maximum PCB track length is
then calculated by multiplying the
risetime by 2 inch/nanosecond. For
example, a maximum output frequency
of 100MHz corresponds to a risetime of
3.5ns, and a track carrying this signal
greater than 7 inches should be treated
as a transmission line.
Equation 7.4 can be used to determine
the characteristic impedance of a PCB

7 -86

track separated from a power/ground plane
by the board's dielectric (micros trip transmission line):

z (n) o

87
I [ 5.98d ]
- ~er + 1.41 n 0.89w + t Eq.7.4

where er = dielectric constant of printed
circuit board material;
d = thickness of the board between
metal layers, in mils;
w = width of metal trace, in mils;
and
t = thickness of metal trace, in mils.
The one-way transit time for a single metal
trace over a power/ground plane can be
determined from Eq. 7.5:
tpd (ns/ ft) = 1.017~0.475er + 0.67 Eq.7.5
For example, a standard 4-layer PCB
board might use 8-mil wide, 1 ounce (1.4
mils) copper traces separated by 0.021"
FR-4 (er=4.7) dielectric material. The
characteristic impedance and one-way
transit time of such a signal trace would be
88n and 1. 7ns/ft (7"/ns), respectively.
Transmission lines can be effectively
termina ted in several ways depending on
the application, as described in Section 2 of
this book.

HIGH SPEED lIARDWARE DESIGN TECHNIQUES

LINE TERMINATION SHOULD BE USED WHEN
LENGTH OF PCB TRACK EXCEEDS 2 inches I ns
Reprinted from EDN Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

DIGITAllC
FAMilY
GaAs
ECl
Schottky
FAST
AS
AC
ALS
LS
TTL
HC

tr, tf
(ns)
0.1
0.75
3
3
3
4
6
8
10
18

PCB TRACK lENGTH
(inches)
0.2
1.5
6
6
6
8
12
16
20
36

PCB TRACK lENGTH
(cm)
0.5
3.8
15
15
15
20
30
40
50
90

=

tr rise time of signal in ns
tf = fall time of signal in ns
•

For analog signals @ f max, calculate tr

=tf =0.35 I fmax

Figure 7.71

•
7-87

HIGH SPEED DESIGN TECHNIQUES

REFERENCES ON EMIIRFI
1.

EDN's Designer's Guide to Electromagnetic Compatibility, EDN, January,
20, 1994, material reprinted by permission ofCahners Publishing Company,
1995.

2.

Designing for EMC (Workshop Notes), Kimmel Gerke Associates, Ltd., 1994.

3.

Systems Application Guide, Chapter 1, pg. 21-55, Analog Devices, Incorporated, Norwood, MA, 1994.

4.

Henry Ott, Noise Reduction Techniques In Electronic Systems, Second Edition, New York, John Wiley & Sons, 1988.

5.

Ralph Morrison, Grounding And Shielding Techniques In Instrumentation, Third Edition, New York, John Wiley & Sons, 1986.

6.

Amplifier Applications Guide, Chapter XI, pg. 61, Analog Devices, Incorporated, Norwood, MA, 1992.

7.

B.Slattery and J.Wynne, Design and Layout ofa Video Graphics
System for Reduced EMI, Analog Devices Application Note AN-SSS.

8.

Paul Brokaw, An IC Amplifier User Guide To Deco up ling, Grounding,
And Making Things Go Right For A Change, Analog Devices
Application Note, Order Number E1393-5-590.

9.

A. Rich, Understanding Interference-Type Noise, Analog Dialogue, 16-3,
1982, pp. 16-19.

10.

A. Rich, Shielding and Guarding, Analog Dialogue, 17-1, 1983, pp. 8-13.

11.

EMC Test & Design, Cardiff Publishing Company, Englewood, CO.
An excellent, general purpose trade journal on issues of EMI and EMC.

7-88

HIGH SPEED HARDWARE DESIGN TECHNIQUES

SmELDING CONCEPTS

Adolfo Garcia, John McDonald
The concepts of shielding effectiveness
presented next are background material.
Interested readers should consult References 1,2, and 6 cited at the end of the
section for more detailed information.
Applying the concepts of shielding requires an understanding of the source of
the interference, the environment surrounding the source, and the distance
between the source and point of observation (the receptor or victim). If the circuit
is operating close to the source (in the
near-, or induction-field), then the field
characteristics are determined by the
source. If the circuit is remotely located
(in the far-, or radiation-field), then the
field characteristics are determined by
the transmission medium.
A circuit operates in a near-field if its
distance from the source of the interference is less than the wavelength (A) of the
interference divided by 2n, or 1J2n. If the
distance between the circuit and the
source of the interference is larger than
this quantity, then the circuit operates in
the far field. For instance, the interference caused by a 1ns pulse edge has an
upper bandwidth of approximately
350MHz. The wavelength of a 350MHz
signal is approximately 32 inches (the
speed of light is approximately 12"/ns).
Dividing the wavelength by 2n yields a
distance of approximately 5 inches, the
boundary between near- and far-field. If a
circuit is within 5 inches of a 350MHz
interference source, then the circuit
operates in the near-field of the interference. If the distance is greater than 5
inches, the circuit operates in the far-field
of the interference.
Regardless of the type of interference,
there is a characteristic impedance

associated with it. The characteristic, or
wave impedance ofa field is determined
by the ratio of its electric (or E-) field to
its magnetic (or H-) field. In the far field,
the ratio of the electric field to the magnetic field is the characteristic (wave
impedance) of free space, given by Zo =
3770.. In the near field, the wave-impedance is determined by the nature of the
interference and its distance from the
source. If the interference source is highcurrent and low-voltage (for example, a
loop antenna or a power-line transformer), the field is predominately magnetic and exhibits a wave impedance
which is less than 3770.. If the source is
low-current and high-voltage (for example, a rod antenna or a high-speed
digital switching circuit), then the field is
predominately electric and exhibits a
wave impedance which is greater than
3770..
Conductive enclosures can be used to
shield sensitive circuits from the effects of
these external fields. These materials
present an impedance mismatch to the
incident interference because the impedance of the shield is lower than the wave
impedance of the incident field. The
effectiveness of the conductive shield
depends on two things: First is the loss
due to the reflection of the incident wave
off the shielding material. Second is the
loss due to the absorption of the transmitted wave within the shielding material.
Both concepts are illustrated in Figure
7.72. The amount of reflection loss depends upon the type of interference and
its wave impedance. The amount of
absorption loss, however, is independent
of the type of interference. It is the same
for near- and far-field radiation, as well
as for electric or magnetic fields.

7-89

HIGH SPEED DESIGN TECHNIQUES

REFLECTION AND ABSORPTION ARE THE TWO
PRINCIPAL SHIELDING MECHANISMS
Reprinted from EON Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

INCIDENT RAY

-- --

.... -.. ............

4--- --

REFLECTED RAY

SHIELD
MATERIAL

TRANSMITTED
RAY

ABSORPTIVE
REGION

Figure 7.72

Reflection loss at the interface between two media depends on the difference in the
characteristic impedances of the two media. For electric fields, reflection loss depends on the frequency of the interference and the shielding material. This loss can
be expressed in dB, and is given by:

Re(dB) = 322 + lOIOglO[

cr~ 2] Eq.7.6

Jlrf r

where crr = relative conductivity of the shielding material, in Siemens per meter;
Ilr = relative permeability of the shielding material, in Henries per meter;
f = frequency of the interference, and
r = distance from source of the interference, in meters
For magnetic fields, the loss depends also on the shielding material and the frequency of the interference. Reflection loss for magnetic fields is given by:

and, for plane waves ( r > IJ2n), the reflection loss is given by:
7-90

HIGH SPEED HARDWARE DESIGN TECHNIQUES

Rpw(dB) = 168 + 1010glO [ a r ]
Ilrf

Eq.7.8

Absorption is the second loss mechanism in shielding materials. Wave attenuation
due to absorption is given by:
Eq.7.9
where t =thickness of the shield material, in inches. This expression is valid
for plane waves, electric and magnetic
fields. Since the intensity of a transmitted field decreases exponentially relative to the thickness of the shielding
material, the absorption loss in a shield
one skin-depth (8) thick is 9dB. Since
absorption loss is proportional to thickness and inversely proportional to skin
depth, increasing the thickness of the
shielding material improves shielding
effectiveness at high frequencies.

frequencies, both reflection and absorption loss to magnetic fields is low; thus,
it is very difficult to shield circuits from
low-frequency magnetic fields. In these
applications, high-permeability materials that exhibit low-reluctance provide
the best protection. These low-reluctance materials provide a magnetic
shunt path that diverts the magnetic
field away from the protected circuit.
Some characteristics of metallic materials commonly used for shielded enclosures are shown in Figure 7.73.

Reflection loss for plane waves in the
far field decreases with increasing
frequency because the shield impedance, Zs' increases with frequency.
Absorption loss, on the other hand,
increases with frequency because skin
depth decreases. For electric fields and
plane waves, the primary shielding
mechanism is reflection loss, and at
high frequencies, the mechanism is
absorption loss. For these types of
interference, high conductivity materials, such as copper or aluminum, provide adequate shielding. At low

A properly shielded enclosure is very
effective at preventing external interference from disrupting its contents as
well as confining any internally-generated interference. However, in the real
world, openings in the shield are often
required to accommodate adjustment
knobs, switches, connectors, or to
provide ventilation (see Figure 7.74).
Unfortunately, these openings may
com promise shielding effectiveness by
providing paths for high-frequency
interference to enter the instrument.

7-91

HIGH SPEED DESIGN 'TECHNIQUES

IMPEDANCE AND SKIN DEPTHS
FOR VARIOUS SHIELDING MATERIALS
Material

Cu

Conductivity

Permeability

Shield Impedance

Skin Depth

Or

Jlr

IZsl

o(inch)

1

1

3.68E-7· .Jf

2.6
.Jf

AI

1

0.61

4.71E-7· .Jf

3.3
.Jf

Steel

0.1

1,000

3.68E- 5·.Jf

0.26

-If
.fl Metal

0.03

20,000

3E-4·.Jf

0.11
.Jf

where

=5.82 x 107 Slm
1-10 =41t x 10-7 HIm
eo =8.85 x 10-12 F/m

0'0

Figure 7.73

ANY OPENING IN AN ENCLOSURE CAN ACT AS
AN EMI WAVEGUIDE BY COMPROMISING
SHIELDING EFFECTIVENESS
Reprinted from EDN Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

,

SEAMS/

<:::f)<:::f)<:::f)

\

SWITCHES

D
\

DISPLAY
PANEL

Figure 7.74
7-92

VENTILATORS

DATA
CABLES

HIGH SPEED lIARDWARE DESIGN TECHNIQUES

The longest dimension (not the total
area) of an opening is used to evaluate
the ability of external fields to enter the
enclosure, because the openings behave
as slot antennas. Equation 7.10 can be

used to calculate the shielding effectiveness, or the susceptibility to EMI leakage or penetration, of an opening in an
enclosure:

Shielding Effectiveness (dB) = 20 loglO

(2\ )

Eq.7.10

where A= wavelength of the interference and
L = maximum dimension of the opening
Maximum radiation of EMI through an
opening occurs when the longest dimension of the opening is equal to one halfwavelength of the interference
frequency (OdB shielding effectiveness).
A rule-of-thumb is to keep the longest
dimension less than 1/20 wavelength of
the interference signal, as this provides
20dB shielding effectiveness. Furthermore, a few small openings on each side
of an enclosure is preferred over many
openings on one side. This is because
the openings on different sides radiate
energy in different directions, and as a
result, shielding effectiveness is not

compromised. If openings and seams
cannot be avoided, then conductive
gaskets, screens, and paints alone or in
combination should be used judiciously
to limit the longest dimension of any
opening to less than 1120 wavelength.
Any cables, wires, connectors, indicators, or control shafts penetrating the
enclosure should have circumferential
metallic shields physically bonded to
the enclosure at the point of entry. In
those applications where unshielded
cables/wires are used, then filters are
recommended at the point of shield
entry.

Sensors and Cable Shielding
The improper use of cables and their
shields is a significant contributor to
both radiated and conducted interference. As illustrated in Figure 7.75,
effective cable and enclosure shielding
confines sensitive circuitry and signals
within the entire shield without compromising shielding effectiveness.
Depending on the type of interference
(pickup/radiated, lowlhigh frequency),
proper cable shielding is implemented
differently and is very dependent on the
length of the cable. The first step is to
determine whether the length of the
cable is electrically short or electrically
long at the frequency of concern. A
cable is considered electrically short if

the length of the cable is less than 1/20
wavelength of the highest frequency of
the interference, otherwise it is electrically long. For example, at 50/60Hz, an
electrically short cable is any cable
length less than 150 miles, where the
primary coupling mechanism for these
low frequency electric fields is capacitive. As such, for any cable length less
than 150 miles, the amplitude of the
interference will be the same over the
entire length of the cable. To protect
circuits against low-frequency electricfield pickup, only one end of the shield
should be returned to a low-impedance
point. A generalized example of this
mechanism is illustrated in Figure
7.76.
7-93

HIGH SPEED DESIGN TECHNIQUES

LENGTH OF SHIELDED CABLES DETERMINES AN
"ELECTRICALLY LONG" OR "ELECTRICALLY SHORT"
APPLICATION
Reprinted from EDN Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

SHIELDED ENCLOSURE B

SHIELDED ENCLOSURE A
LENGTH
(

[>

A

"'\

:

[>

SHIELDED
CABLE
FULLY SHIELDED ENCLOSURES CONNECTED BY FULLY
SHIELDED CABLE KEEP ALL INTERNAL CIRCUITS AND
SIGNAL LINES INSIDE THE SHIELD .
• TRANSITION REGION: 1/20 WAVELENGTH

Figure 7.75

CONNECT THE SHIELD AT ONE POINT AT THE LOAD
TO PROTECT AGAINST LOW FREQUENCY (50/60Hz).THREATS
Reprinted from EDN Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

CAPACITIVE COUPLING
TO CABLE

CABLE SHIELD
GROUNDED AT LOAD

EQUIVALENT
CIRCUITS

Figure 7.76
7-94

HIGH SPEED IIARnWARE DESIGN TECHNIQUES

In this example, the shield is grounded
at the receiver. An exception to this
approach (which will be highlighted
again later) is the case where line-level
(>lVrms) audio signals are transmitted
over long distances using twisted pair,
shielded cables. In these applications,
the shield again offers protection
against low-frequency interference, and
an accepted approach is to ground the
shield at the driver end (LF and HF
ground) and ground it at the receiver
with a capacitor (HF ground only).
In those applications where the length
of the cable is electrically long, or protection against high-frequency interference is required, then the preferred
method is to connect the cable shield to
low-impedance points at both ends
(direct connection at the driving end,
and capacitive connection at the receiver). Otherwise, unterminated
transmission lines effects can cause

reflections and standing waves along
the cable. At frequencies of 10MHz and
above, circumferential (360°) shield
bonds and metal connectors are required to main low-impedance connections to ground.
In summary, for protection against lowfrequency «lMHz), electric-field interference, grounding the shield at one end
is acceptable. For high-frequency interference (> lMHz), the preferred method
is grounding the shield at both ends,
using 3600 circumferential bonds between the shield and the connector, and
maintaining metal-to-metal continuity
between the connectors and the enclosure. Low-frequency ground loops can
be eliminated by replacing one of the
DC shield connections to ground with a
low inductance O.OlpF capacitor. This
capacitor prevents low frequency
ground loops and shunts high frequency
interference to ground.

Shielded Twisted Pair Cable Grounding Examples
The environments in which analog
systems operate are often rich in
sources of EM!. Common EMI noise
sources include power lines, logic signals, switching power supplies, radio
stations, electric lighting, and motors.
Noise from these sources can easily
couple into long analog signal paths,
such as cables, which act as efficient
antennas. Shielded cables protect
signal conductors from electric field (Efield) interference by providing low
impedance paths to ground at the
offending frequencies. Aluminum foil,
copper, and braided stainless steel are
materials very commonly used for cable
shields due to their low impedance
properties.
Simply increasing the separation between the noise source and the cable

will yield significant additional attenuation due to reduced coupling, but
shielding is still required in most applications involving remote sensors.
There are two paths from an EMI
source to a susceptible cable: capacitive
(or E-field) and magnetic (or H-field)
coupling. Capacitive coupling occurs
when parasitic capacitance exists
between a noise source and the cable.
The amount of parasitic capacitance is
determined by the separation, shape,
orientation, and the medium between
the source and the cable.
Magnetic coupling occurs through
parasitic mutual inductance when a
magnetic field is coupled from one
conductor to another. Parasitic mutual
inductance depends on the shape and
7-95

HIGH SPEED DESIGN TECHNIQUES

relative orientation of the circuits in
question, the magnetic properties of the
medium, and is directly proportional to
conductor loop area. Minimizing conductor loop area reduces magnetic
coupling proportionally.
Shielded twisted pair cables offer further noise immuni ty to magnetic fields.
Twisting the conductors together reduces the net loop area, which has the
effect of canceling any magnetic field
pickup, because the sum of positive and
negative incremen tal loop areas is
ideally equal to zero.
To study the shielding problem, a
precision RTD (Resistance Temperature
Detector) amplifier circuit was used as

the basis for a series of experiments. A
remote lOOn RTD was connected to the
bridge, bridge driver, and the bridge
amplifier circuit (Figure 7.77) using 10
feet of a shielded twisted pair cable.
The RTD is one element ofa 4-element
bridge (the three other resistor elements are located in the bridge and
bridge driver circuit). The gain of the
instrumentation amplifier was adjusted
so that the sensitivity at the output
was 10mV/oC, with a 5V full scale.
Measurements were made at the output of the instrumentation amplifier
with the shield grounded in various
ways. The experiments were conducted
in lab standard environment where a
considerable amount of electronic
equipment was in operation.

UNGROUNDED SHIELDED CABLES ACT AS ANTENNAS

10 FEET
SHIELDED
TWISTED
PAIR

RTD
1000

BRIDGE
AND
BRIDGE
DRIVER

IN-AMP
OUTPUT

VERTICAL SCALE: 2mV/div
HORIZONTAL SCfALE: 10ms/div

Figure 7.77
7-96

HIGH SPEED IlARnWARE DESIGN TECHNIQUES

The first experiment was conducted
with the shield ungrounded. As shown
in Figure 7.77, shields left floating are
not useful and offer no attenuation to
EMI-induced noise, in fact, they act as
antennas. Capacitive coupling is unaffected, because the floating shield
provides a coupling path to the signal
conductors. Most cables exhibit parasitic capacitances between 10-30pF/ft.
Likewise, HF magnetically coupled
noise is not attenuated because the
floating cable shield does not alter
either the geometry or the magnetic
properties of the cable conductors. LF
magnetic noise is not attenuated significantly, because most shield materials absorb very little magnetic energy.
To implement effective EMIIRFI shielding, the shield must be grounded. A
grounded shield reduces the value of
the impedance of the shield to ground
to small values. Implementing this
change will reduce the amplitude of the
E-Field noise substantially.
Designers often ground both ends of a
shield in an attempt to reduce shield
impedance and gain further E-Field
attenuation. Unfortunately, this approach can create a new set of potential
problems. The AC and DC ground
potentials are generally different at
each end of the shield. Low-frequency
ground loop current is created when
both ends of a shield are grounded. This
low frequency current flows through the
large loop area of the shield and couples
into the center conductors through the
parasitic mutual inductance. If the
twisted pairs are precisely balanced,
the induced voltage will appear as a
common-mode rather than a differential voltage. Unfortunately, the conductors may not be perfectly balanced, the
sensor and excitation circuit may not be
fully balanced, and the common mode
rejection at the receiver may not be

sufficient. There will therefore be some
differential noise voltage developed
between the conductors at the output
end, which is amplified and appears at
the final output of the instrumentation
amplifier. With the shields of the experimental circuit grounded at both
ends, the results are shown in Figure
7.78.
Figure 7.79 illustrates a properly
grounded system with good electric field
shielding. Notice that the ground loop
has been eliminated. The shield has a
single point ground, located at the
signal conditioning circuitry, and noise
coupled into the shield is effectively
shunted into the receiver ground and
does not appear at the output of the
instrumentation amplifier.
Figure 7.80 shows an example ofa
remotely located, ungrounded, passive
sensor (ECG electrodes) which is connected to a high-gain, low power AD620
instrumentation amplifier through a
shielded twisted pair cable. Note that
the shield is properly grounded at the
signal conditioning circuitry. The
AD620 gain is 1000x , and the amplifier is operated on ±3V supplies. Notice
the absence of 60Hz interference in the
amplifier output.
Most high impedance sensors generate
low-level current or voltage outputs,
such as a photodiode responding to
incident light. These low-level signals
are especially susceptible to EMI, and
often are of the same order ofmagnitude as the parasitic parameters of the
cable and input amplifier.
Even properly shielded cables can
degrade the signals by introducing
parasitic capacitance that limits bandwidth, and leakage currents that limit
sensitivity. An example is shown in
Figure 7.81, where a high-impedance
7-97

HIGH SPEED DESIGN TECHNIQUES

GROUNDING BOTH ENDS OF A SHIELD PRODUCES
LOW FREQUENCY GROUND LOOPS

RTD

100n

10 FEET

BRIDGE

SHIELDED
TWISTED
PAIR

BRIDGE
DRIVER

AND

G2
IN-AMP
VERTICAL SCALE: 2mVldiv
HORIZONTAL SCALE: 10ms/dlv

OUTPUT

Figure 7.78

GROUNDING SHIELD AT RECEIVER END SHUNTS LOW AND
HIGH-FREQUENCY NOISE INTO RECEIVER GROUND
~
RTD

100n

~
10 FEET

BRIDGE

SHIELDED
TWISTED
PAIR

BRIDGE
DRIVER

IN-AMP

AND

VERTICAL SCALE: 2mV/div
HORIZONTAL SCALE: 10ms/div

OUTPUT

Figure 7.79
7-98

RG

HIGH SPEED lIARDWARE DESIGN TECHNIQUES

FOR UNGROUNDED PASSIVE SENSORS,
GROUND SHIELD AT THE RECEIVING END

G

SHIELDED
TWISTED
PAIR

=1000
OUTPUT

ELECTRODES

dm

G1

G2

VERTICAL SCALE: 10mV/div
HORIZONTAL SCALE: O.2sec/div

IN-AMP
OUTPUT

Figure 7.80

SHIELDS ARE NOT EFFECTIVE WITH
HIGH IMPEDANCE REMOTE SENSORS
CCOMP

PHOTODIODE
DETECTOR

~

SHIELDED
TWISTED
PAIR

HIGH
IMPEDANCE
>100MO

~

20pF/ft

• CABLE CAPACITANCE LIMITS BANDWIDTH
• CABLE LEAKAGE CURRENT LIMITS SENSITIVITY

Figure 7.81
7-99

HIGH SPEED DESIGN TECHNIQUES

photodiode is connected to a preamp
through a long shielded twisted pair
cable. Not only will the cable capacitance limit bandwidth, but cable leakage current limits sensitivity. A
pre-amplifier, located close to the highimpedance sensor, is recommended to
amplify the signal and to minimize the
effect of cable parasitics.
Figure 7.82 is an example of a highimpedance photodiode detector and preamplifier, driving a shielded twisted

pair cable. Both the amplifier and the
shield are grounded at a remote location. The shield is connected to the
cable driver common, G1, ensuring that
the signal and the shield at the driving
end are both referenced to the same
point. The capacitor on the receiving
side of the cable shunts high frequency
noise on the shield into ground G2
without introducing a low-frequency
ground loop. This popular grounding
scheme is known as hybrid grounding.

REMOTELY LOCATED HIGH IMPEDANCE
SENSOR WITH PREAMP
PHOTODIODE
PREAMP

SHIELDED
TWISTED
PAIR

LFAND HF
GROUND
G1

G2

Figure 7.82

7 -100

HIGH SPEED IlARDWARE DESIGN TECHNIQUES

Figure 7.83 illustrates a balanced
active line driver with a hybrid shield
ground implementation. When a
system's operation calls for a wide
frequency range, the hybrid grounding
technique often provides the best choice
(Reference 8). The capacitor at the
receiving end shunts high-frequency
noise on the shield into G2 without
introducing a low-frequency ground

loop. At the receiver, a common-mode
choke can be used to help prevent RF
pickup entering the receiver, and
subsequent RFI rectification (see References 9 and 10). Care should be taken
that the shields are grounded to the
chassis entry points to prevent contamination of the signal ground (Reference
11).

HYBRID (LF AND HF) GROUNDING WITH ACTIVE DRIVER
BALANCED
LINE
DRIVER

BALANCED
LINE
RECEIVER

SHIELDED
TWISTED
PAIR

G1

\

/

LFAND HF
GROUND

G2

HF GROUND

Figure 7.83

To summarize this discussion, shield
grounding techniques must take into
account the type and the configuration
of the sensor as well as the nature of
the interference. When a low-impedance passive sensor is used, grounding
the shield to the receiving end is the
best choice. Active sensor shields should

generally be grounded at the source
(direct connection to source ground) and
at the receiver (connect to receiver
ground using a capacitor). This hybrid
approach minimizes high-frequency
interference and prevents low-frequency ground loops. Shielded twisted
cond uctors offer additional protection
7-101

HIGH SPEED DESIGN TECHNIQUES

As shown in Figure 7.84, pigtail termi-

against shield noise because the
coupled noise occurs as a commonmode, and not a differential signal.
The best shield can be compromised by
poor connection techniques. Shields
often use "pig-tail" connections to make
the connection to ground. A "pig-tail"
connection is a single wire connection
from shield to either chassis or circuit
ground. This type of connection is
inexpensive, but at high frequency, it
does not provide low impedance. Quality shields do not leave large gaps in
the cable/instrument shielding system.
Shield gaps provide paths for high
frequency EM! to enter the system. The
cable shielding system should include
the cable end connectors. Ideally, cable
shield connectors should make 3600
contact with the chassis ground.

nations on cables very often cause
systems to fail radiated emissions tests
because high-frequency noise has
coupled into the cable shield, generally
through stray capacitance. If the length
of the cable is considered electrically
long at the interference frequency, then
it can behave as a very efficient quarter-wave antenna. The cable pigtail
forms a matching network, as shown in
the figure, to radiate the noise which
coupled into the shield. In general,
pigtails are only recommended for
applications below 10kHz, such as 501
60Hz interference protection. For
applications where the interference is
greater than 10kHz, shielded connectors, electrically and physically connected to the chassis, should be used.

"SHIELDED" CABLE CAN CARRY HIGH FREQUENCY
CURRENT AND BEHAVES AS AN ANTENNA
Reprinted from EON Magazine (January 20,1994), © CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA

SHIELD

EQUIVALENT
CIRCUIT

)

ICM

=COMMON-MODE CURRENT
Figure 7.84

7-102

HIGH SPEED IlARDWARE DESIGN TECHNIQUES

REFERENCES: CABLE SHIELDING
1.

H.W. Ott, Noise Reduction Techniques in Electronic Systems,
Second Edition, John Wiley & Sons, Inc., New York, 1988.

2.

Ralph Morrison, Grounding and Shielding Techniques in
Instrumentation, Third Edition, John Wiley & Sons, Inc.,
New York, 1988.

3.

Systems Application Guide, Section 1, Analog Devices, Inc., Norwood,
MA,1993.

4.

AD620 Instrumentation Amplifier, Data Sheet, Analog Devices, Inc.

5.

A. Rich, Understanding Interference-Type Noise, Analog Dialogue, 16-3,
1982, pp. 16-19.

6.

A. Rich, Shielding and Guarding, Analog Dialogue, 17-1, 1983, pp. 8-13.

7.

EDN's Designer's Guide to Electromagnetic Compatibility, EDN, January,
20, 1994, material reprinted by permission ofCahners Publishing Company, 1995.

8.

Designing for EMC (Workshop Notes), Kimmel Gerke Associates, Ltd., 1994.

9.

James Bryant and Herman Gelbach, High Frequency Signal Contamination,
Analog Dialogue, Vol. 27-2, 1993.

10.

Walt Jung, System RF Interference Prevention, Analog Dialogue, Vol. 28-2,
1994.

11.

Neil Muncy, Noise Susceptibility in Analog and Digital Signal Processing
Systems, presented at 97th Audio Engineering Society Convention,
Nov. 1994.

7-103

HIGH SPEED DESIGN TECHNIQUES

GENERALREFERENCES:HARDWARE DESIGNTECHNIQUES
1.

Linear Design Seminar, Section 11, Analog Devices, Inc., 1995.

2.

E.S.D. Prevention Manual
Available free from Analog Devices, Inc.

3.

B.I. & B. Bleaney, Electricity & Magnetism, OUP 1957, pp 23,24, & 52.

4.

Paul Brokaw, An I.C. Amplifier User's Guide to Decoupling, Grounding
and Making Things Go Right for a Change, Analog Devices Application
Note, Available free of charge from Analog Devices, Inc.

5.

Jeff Barrow, Avoiding Ground Problems in High Speed Circuits,
R.F. Design, July 1989.
AND

Paul Brokaw & Jeff Barrow, Grounding for Low- and High-Frequency
Circuits, Analog Dialogue, 23-3 1989.
Free from Analog Devices.

6.

International EMI Emission Regulations
Canada
CSA C108.8-M1983
FDR VDE 0871NDE 0875
Japan
CISPR (VCCI)IPUB 22
USA FCC-15 Part J

7.

Bill Slattery & John Wynne, Design & Layout ofa Video Graphics System
for Reduced EMI, Analog Devices Application Note (E1309-15-10/89)
Free from Analog Devices.

8.

William R. Blood, Jr., MECL System Design Handbook (HB205, Rev. 1),
Motorola Semiconductor Products, Inc., 1988.

9.

Wainwright Instruments Inc., 69 Madison Ave., Telford, PA, 18969-1829,
Tel. 215-723-4333, Fax. 215-723-4620.
Wainwright Instruments GmbH, Widdersberger Strasse 14,
DW-8138 Andechs-Frieding, Germany. Tel: +49-8152-3162,
Fax: +49-8152-40525.

10.

Ralph Morrison, Grounding and Shielding Techniques in
Instrumentation, Third Edition, John Wiley, Inc., 1986.

11.

Henry W. Ott, Noise Reduction Techniques in Electronic Systems,
Second Edition, John Wiley, Inc., 1988.

12.

Robert A. Pease, Troubleshooting Analog Circuits, ButterworthHeinemann, 1991.

7 -104

HIGH SPEED lIARDWARE DESIGN TECHNIQUES

13.

Jim Williams, Editor, Analog Circuit Design: Art, Science, and
Personalities, Butterworth-Heinemann, 1991.

14.

Doug Grant and Scott Wurcer, Avoiding Passive Component Pitfalls,
The Best of Analog Dialogue, pp. 143-148, Analog Devices, Inc., 1991.

15.

Walt Jung and Richard Marsh, Picking Capacitors, Part I., Audio,
February, 1980.

16.

Walt Jung and Richard Marsh, Picking Capacitors, Part II., Audio,
March, 1980.

17.

Daryl Gerke and Bill Kimmel, The Designer's Guide to Electromagnetic
Compatibility, EDN Supplement, January 20,1994.

18.

Walt Kester, Basic Characteristics Distinguish Sampling AID Converters,
EDN, September 3, 1992, pp.135-144.

19.

Walt Kester, Peripheral Circuits Can Make or Break Sampling ADC
System, EDN, October 1, 1992, pp. 97-105.

20.

Walt Kester, Layout, Grounding, and Filtering Complete Sampling
ADC System, EDN, October 15,1992, pp. 127-134.

21.

Howard W. Johnson and Martin Graham, High-Speed Digital Design,
PTR Prentice Hall, 1993.

7-105

HIGH SPEED DESIGN TECHNIQUES

INDEX
•

SUBJECT INDEX

•

ANALOG DEVICES PARTS INDEX

HIGH SPEED DESIGN TECHNIQUES

INDEX

SUBJECT INDEX
A
AAVID Engineering, Inc., 7.68
Absolute value amplifier, 4.42
AC-coupled single-ended-to-differential
driver, single-supply, 2.50-51
AC-coupled single-supply circuit, headroom considerations, 2.48-50
Active and Passive Electrical Wave Filter
Catalog, 4.48
AD538:
Miller capacitance, 3.21
monolithic analog computer, 3.21
AD600:
op amp:
voltage controlled:
amplifier gain, 3.7, 5.45-46
gain vs. differential control voltage,
3.5-6
X-AMP, key specifications, 3.8
AD602:
gain vs. differential control voltage, 3.5-6
signal-to-noise ratio, 3.7
X-AMP, key specifications, 3.8
AD603:
automatic gain control amplifier, 3.14-16
circuit bandwidth, 3.16
key specifications, 3.8
low noise automatic gain control amplifier, 3.4
X-AMP single version, 3.7
AD606:
block diagram, 3.31
key specifications, 3.31-32
limiter output, 3.32
logarithmic and limited outputs, 3.31
monolithic log amp, 3.31
AD607:
block diagram, 3.55-56
IF subsystem, 3.55-57
automatic gain control loop, 3.3.57
inphase and quadrature demodulator,
3.57
linear amplifier, 3.57
low noiselhigh intercept mixer, 3.57
receiver, 3.57
key specifications, 3.57
AD608:
block diagram, 3.58
IF subsystem, 3.57-59
limiter, 3.59
logarithmic amplifier/limiter, 3.59
mixer, 3.59
receiver, 3.59
key specifications, 3.59

low pass futer, cutoff frequency, 3.59
AD636, RMSIDC converter, 3.9
AD641:
block diagram, 3.28
DC-coupling, 3.31
error curve, 3.29
gain, 3.31
key features, 3.28
log linearity, 3.27
transfer function, 3.18, 3.29
AD645, photodiode preamplifier, 2.67
AD743, photodiode preamplifier, 2.67
AD744, photodiode preamplifier, 2.67
AD745, photodiode preamplifier, 2.67
AD780, Thevenin equivalent output
voltage, 2.33
AD797, op amp, low noise, 5.45-46
AD813, programmable gain video amplifier, 2.54-55
AD815:
applications, 2.60-61
in asymmetric digital subscriber line
system, 2.60-61
THD vs. frequency, 2.61
AD817:
capacitive loads, internal compensation
scheme, 2.10-11
high impedance compensation, 2.10
power dissipation vs. supply voltage, 7.62
AD820, photodiode preamplifier, 2.67
AD823:
photodiode preamplifier, 2.67-68
dark current compensation, 2.68
AD831:
block diagram, 3.47
with external matching network, 3.50
key specifications, 3.48
low distortion active mixer, 3.36, 3.47-50,
3.52-53
noise figure, 3.49-50
AD831 Data Sheet, 3.61
AD834, as analog multiplier, 3.37
AD843, photodiode preamplifier, 2.67
AD845:
BiFET op-amp, circuit, 1.10
photodiode preamplifier, 2.67
AD847, op amp, ADSpice modeling, 7.5-6
AD847-family, folded cascode voltage
feedback op-amp, circuit, 1.9
AD876:
buffering by AD8011, 2.41
DC-coupled single-supply driver, 2.40
input, MOSFET switch, 2.41
Index-1

HIGH SPEED DESIGN TECHNIQUES

sampling MOSFET, 2.41
AD976/977, 16-bit SAR ADC, 4.31
AD977X, 10-bit DAC, oversampling interpolating, block diagram, 6.27
AD6461, quadrature demodulator/
baseband filter, 5.52-53
AD6600:
11-bitADC:
gain ranging:
analog input and filter, 5.27
block diagram, 5.25
diversity, 5.27
key specifications, 5.26
with RSSI, 5.25
SNR,5.26
AD6620, dual channel decimating receiver,
5.2S
AD6640:
architecture, 5.40
key specifications, 5.40
sampling, 5.41
AD6742:
12-bitDAC:
SHA deglitched:
functional diagram, 6.24
key specifications, 6.24
AD7SS2, 16-bit SAR ADC, 4.31
AD7S92, 12-bit SAR ADC, 4.31
ADS001:
cable driver, pulse response, 2.14-17
input/output signal traces, 7.19-20
resistors:
DIP package, 2.2
SOIC package, 2.2, 7.17-19
three-capacitor decoupling, 7.19
ADS002, cross-coupled, frequency response, 2.24
ADS004, sensitivity to inverting input
capacitance, 2.3
ADS011:
frequency response, 1.15
higher overall bandwidth, 1.17
key specifications, 1.16
output noise analysis, 1.31
power supply rejection ratio, 1.35
single-supply ADC direct-coupled driver,
2.40-41
two-stage gain configuration, 1.16-17
advantages, 1.17
ADS013:
differential voltage protected, 2.52
triple current-feedback op amp, 2.51-53
ADS031, single-supply gain-of-two line
driver, 2.46-47
A

T\OI\O~.

fi.LlOVuU~

distortion near clamping region, 2.31
Index-2

input vs. output clamping, 2.30
key specifications, 2.32
overdrive recovery, 2.32
performance, 2.30
unity gain voltage follower, equivalent
circuit, 2.29
ADS037:
distortion near clamping region, 2.31
key specifications, 2.32
overdrive recovery, 2.32
performance, 2.30
unity gain voltage follower, equivalent
circuit, 2.29
ADS041:
op amp:
buffer for RGB signals, 2.43-44
single-supply ADC driver, 2.42-43,5.15
AC-coupled composite video line
driver, 2.49-50
advantages, 2.50
sync stripper, 2.44-45
ADS042:
buffer for RGB signals, 2.43-44
output saturation voltage vs. load current, 2.39
single-supply AC-coupled differential
driver, 2.50-51
ADS044, buffer for RGB signals, 2.43-44
ADS047, in video line driver, 2.1S
ADS04S:
op amp:
voltage feedback, in multiple feedback
lowpass filter, 1.22-24
.
voltage feedback in video line driver,
2.1S
ADS116:
buffered video crosspoint switch:
circuit, 2.59
key specifications, 2.59
ADS170:
bipolar video multiplexer:
block diagram, 2.56
key specifications, 2.56
ADS174:
bipolar video multiplexer:
block diagram, 2.56
key specifications, 2.56
ADS1S0:
bipolar video multiplexer:
block diagram, 2.56
key specifications, 2.56
ADS1S2:
bipolar video multiplexer:
block diagram, 2.56
1.~ •• ~_~~.:.c:~

Avy

... +.:~.........

0 t::.a

i:)lIv\,;~.u\,;awv.ui:), ~.vv

AD9002, flash converter, 2.33

INDEX

AD9042:
12-bit subranging ADC:
in AMPS cellular system, 5.33-34
block diagram, 5.11
digital error correction, 5.43-44
scheme, 4.37
dithering effects, 5.45-48
evaluation board:
block diagram, 7.21
FIFO memory, 7.23
fabrication, 5.11
FIT outputs, 5.36-38,5.47-48
key specifications, 4.39, 5.12
MagAmp architecture, 4.37
noise power ratio, 4.27
performance, 5.12
process gain, 4.22
SFDR, 4.21-22, 4.24, 5.12, 5.36-39, 5.43,
5.47
limitations, 5.43
subranging point DNL errors, 5.44
AD9050:
10-bit single-supply ADC:
AC input coupling, 5.15
block diagram, 5.13
fabrication, 5.12
FIT output, 2.43
input circuit, 5.12-14
key specifications, 5.14
op amp single-supply driver, 2.42-43
SINAD, 5.15
AD9059:
8-bit dual ADC:
functional diagram, 4.46
key specifications, 4.47
AD9066:
6-bit ADC, 4.33, 5.50-51
flash converter:
basic interpolation circuit, 4.34
BiCMOS process, 4.33
ENOB vs. analog input frequency,
4.34
key specifications, 4.35
IF sampling, 5.50-51
AD9220:
12-bit pipelined CMOS ADC:
block diagram, 4.39, 5.3
input circuit with SHA, 5.4
key specifications, 4.40, 5.3
latency delay, 4.39
SFDR and SNR, 5.10
THD vs. input frequency, 5.5,5.7
AD9221:
12-bit pipelined CMOS ADC:
block diagram, 5.3
input circuit with SHA, 5.4

key specifications, 4.40, 5.3
latency delay, 4.40
AD9223:
12-bit pipelined CMOS ADC:
block diagram, 5.3
input circuit with SHA, 5.4
key specifications, 4.40, 5.3
latency delay, 4.40
AD9721:
10-bitDAC:
midscale glitch impulse, 6.14-15
SFDR plot, 6.17
AD9760:
100MSPS DAC:
applications, 6.22
key specifications, 6.22
AD9762:
100MSPS DAC:
applications, 6.22
key specifications, 6.22
AD9764:
100MSPS DAC:
applications, 6.22
key specifications, 6.22
AD9805, 10-bit ADC, 5.20
AD9807, 12-bit ADC, CCD imaging decoder/signal processor, schematic, 5.20
AD9830/9831 CMOS DDS system, key
specifications, 6.11
AD9850:
10-bit CMOS:
current switch DAC core, 6.20-21
SFDR,6.21
125MSPS DDSIDAC synthesizer, 6.7-8
frequency tuning, 6.8
key specifications, 6.8
serial loading, 6.8
AD9853:
digital QPSK modulator:
in CATV setup, 6.28
key specifications, 6.29
AD620 Instrumentation Amplifier, 7.103
AD815 Data Sheet, 7.68
ADC,5.1-54
3-bit MagAmp folding, 4.44
block diagram, 4.44
equivalent circuit, 4.44
input, 4.45
residue waveforms, 4.45
3-bit serial binary:
residue outputs, 4.42-43
simplified scheme, 4.42
8-bit, subranging, block diagram, 4.36
8-bit MagAmp folding, 4.45
10-bit, distortion and noise, noise power
ratio, theoretical curve,
Index-3

HIGH SPEED DESIGN TECHNIQUES

4.26
II-hit, distortion and noise, noise power
ratio, theoretical curve,
4.26
12-hit:
distortion and noise:
noise power ratio, theoretical curve,
4.26
SINAD andENOB, 4.19
SAR, sampling rates, 4.31
subranging, digitally corrected, block
diagram, 4.37
wideband, high SFDR, 4.21-22
16-bit, SAR, sampling rates, 4.31
applications, 5.1-54
CCD imaging, 5.17-20
digital receivers, 5.21-53
low distortion/wide dynamic range
inputs, 5.1-16
architectures, 4.30-47
bipolar input, uses, 5.11
bit-per-stage, 4.41-47
folding converter, 4.42
MagAmp architecture, 4.42
scheme, 4.41
serial-Gray architecture, 4.42
single binary bit conversion stage, 4.4142
see also ADC, serial; ADC, ripple
CCD imaging, 5.17-20
charge detector readout, 5.18
correlated double sampling, 5.18-19
linear CCD array scheme, 5.17
output waveform, 5.19
pixel charge, 5.18
SHA, 5.18-19
digital receivers, 5.21-53
direct-coupled driver, single-supply, 2.4041
distortion mechanisms, 4.1
distortion and noise, 4.14-29
analog bandwidth, 4.20-21
definition, 4.20
aperture jitter and delay, 4.27-29
effects, 4.27-28
SNR,4.29
differential non-linearity:
distortion products, 4.16-17
encoding process, 4.16
effective aperture delay time, 4.28, 4.29
ENOB, 4.18-21
gain vs. frequency, 4.21
equivalent number of bits, 4.19
harmonic distortion, 4.17
integral and differential non~linea...""ity,
4.16-17
Index-4

noise power ratio, 4.24-27
measurements, 4.25
summary, 4.26
theoretical curves, 4.26
sampling clock jitter, 4.28
SNR,4.29
SFDR, 4.21-22
SHA, aperture jitter, 4.28
SINAD ratio, 4.18-19
SNR,4.18-19
phase jitter, 4.27
sources:
equivalent input referred noise, 4.15
grounded-input histogram, 4.15
model, 4.14
thermal noise, 4.15
THD+N, 4.17
THD,4.17
two tone !MD, 4.22-24
measurement, 4.22
second- and third-order
intermodulation products, 4.23
worst harmonic, 4.17
dither, and SFDR, 5.41
DNL errors, correction by dither, 5.43
dynamic performance quantification, 4.16
evaluation board:
buffer memory design, 7.22
DAC, 7.20-21
FIT, 7.20-21
FIFO memory, 7.22-23
fabrication:
CMOS, 4.1-2
XFCB process, 4.2
FIT processing gain, 4.14
flash converter, 4.31-35
gain-of-two MagAmp folding stage, 4.46
grounding, 7.28
half-flash, 4.36
high speed, 4.1-47
evaluation board, 7.20-21
maximizing SFDR, limitations, 5.41
ideal 12-bit:
FIT testing, noise floor, 4.13
input frequency vs. sampling clock
ratio, SFDR, 4.12
ideal N-bit:
distortion and noise, 4.10-13
over Nyquist bandwidth, 4.10
dynamic performance analysis, 4.12
input, 4.11
oversampling, 4.10
FIT processing gain, 4.10,4.13
quantization noise, 4.11
sampling, dither signal, 4.13
sampling and quantization errors, 4.10

INDEX

testing, FFT, 4.13
with integral sample-and-hold, 4.14
low distortion/wide dynamic range
inputs, 5.1-16
bipolar input, 5.11-16
AC coupling, 5.15
DC coupling, 5.15-16
drive circuit, 5.16
input /output common-mode range, 5.1
switched-capacitor input, 5.2-10
buffered AC-coupled input drive
circuit, 5.7-8
direct-coupled level shifter, 5.8
input voltage range options, 5.4
output impedance, 5.6
output voltage span, 5.6
SFDR,5.4
single-ended AC coupling circuit, 5.67
THD vs. input frequency, 5.5,5.7
track-and-hold, 5.4
transformer coupling, 5.9-10
lower power and voltage, 4.1
parallel, 4.31-35
diagram, 4.32
see also ADC, flash converter
pipelined, 4.36-40
real-time DSP signal processing, 4.1
advantages, 4.1
ripple, 4.41-47
sampling, 4.1
characteristics, 4.2
integral SHA, jitter elimination, 4.28
Nyquist zones, 4.8
SAR,4.30-31
accuracy, 4.31
block diagram, 4.30
with calibration DAC, 4.31
as quantizer, 4.31
serial, 4.41-47
SHA,4.14
single-supply low-distortion ADC driver,
2.42-43
subranging, 4.36-40
block diagram, 4.36
digital correction, 4.36
see also ADC, pipelined
ADP3367:
load current vs. input/output voltage,
7.54
low dropout fIXed/variable regulator, 7.53
shutdown mode, 7.53
ADP3367 Data Sheet, 7.55
ADSL; See: Asymmetric digital subscriber
line
ADSpice model:

feature summary, 7.7-8
input and gain stage model, 7.3-4
open architecture, 7.3
other features, 7.7-8
output stage, 7.5
pole and zero stage, 7.4
Advanced mobile phone service; See:
AMPS
AGC; See: Automatic gain control loop
Aliases, 4.2-3
Amplifier, voltage controlled, 3.1
Amplifier Applications Guide (1992), 1.36,
2.71,3.60,4.49, 7.26,7.88
Amplifier input bias current, and commonmode voltage, 2.37
AMPS:
analog cellular phone system, 5.21,5.33
process gain, 5.35
vs. GSM, 5.34
Analog bandwidth, fundamental swept
frequency, 4.20
Analog circuit:
ADSpice model, 7.3-6
input and gain stage model, 7.3-4
open architecture, 7.3
other features, 7.7-8
output stage, 7.5
pole and zero stage, 7.4
Boyle model, 7.3
definition, 7.1
evaluation boards, 7.17-26
mixed-signal, high-speed vs. highprecision, 7.8
prototyping, 7.8-17
sensitivity to RFI, 7.76
simulation, 7.1-7
Spice micromodel, 7.1
Spice simulations, comparison, 7.2
Analog ground, separated from digital
ground, 7.28-29
Analog ground plane, for decoupling, 7.29
Analog multiplier, as voltage-controlled
amplifier, 3.4
Analog superheterodyne, receiver, 3.33,
5.21
Antialiasing filter, in undersampling, 4.810
Antognetti, Paolo, 7.26
Aperture jitter, 4.28
Armstrong, Major Edwin H., 3.33, 5.21
The ARRL Handbook for Radio Amateurs,
6.30
Asymmetric digital subscriber line:
and high power line drivers, 2.60-61
low-distortion differential drive amplifier, 2.60
Index-5

HIGH SPEED DESIGN TECHNIQUES

Automatic gain control, 3.2-9
nonlinear filtering, 3.3
received signal strength indicator, 3.3
system schematic, 3.3

B
Baines, Rupert, 5.54
Bandpass sampling, 4.4-10
Barber, William L., 3.60
Barrow, Jeff, 7.104
Bennett, W.R., 4.48
Best, R.E., 6.30
BiFET process, 1.1-2
Blackman, R.B., 4.49
Bleaney, B., 7.104
Bleaney, B.L, 7.104
Blood, William R. Jr., 2.71, 7.104
Bode plot, 1.4, 1.14, 1.20, 1.21, 1.25
Boltzmann's constant, 1.30
Boyle, -, 7.26
Brannon, Brad, 5.1, 5.54
Broadband Amplifier Applications, 3.60
Brokaw, Paul, 7.88, 7.104
Brown, Edmund R., 3.60
Bryant, James M., 3.1, 3.60, 7.1, 7.8, 7.27,
7.103
Buffer:
single-supply:
gain-of-two, 2.43-44
diagram, 2.44
output, 2.45
Buffer latch:
decoupling, 7.30
grounding, 7.30
Butterworth fIlter, 4.5, 6.25
Buxton, Joe, 1.36, 2.71, 7.1

C
Cable drivers, 2.12-17
characteristics, 2.13
coaxial cable:
bandwidth flatness loss, 2.14
pulse response, 2.15
skin effect, 2.13
Cable radiation and connector leakage,
EMIIRFI coupling, 7.73
Cable receivers, 2.12-17
Cage jacks, 7.16
Capacitive loading:
compensation:
active, limitations, 2.9
drawbacks, 2.12
forced-high loop noise gain, 2.4
in-the-loop, 2.8-9
overcompensation, 2.4
Index-6

passive, 2.6
driving, amplifier stability, 2.4
high speed op amp:
effects, 2.3, 2.5
open-loop series resistance, 2.6
Capacitor:
.
ceramic, 7.34-35
multilayer ceramic "chip caps", 7.37
NPO types, 7.37
characteristics, 7.34-35
classes, 7.34-35
electrolytic, 7.34-35
aluminum, 7.36
OS-CON, 7.36
ESR, 7.38
switching, 7.36
ESR degradation, 7.37
high frequency impedance, 7.38
tantalum, 7.36
ESL, 7.35
fIlm, 7.34-35
inductive, 7.37
low dielectric loss, 7.36-37
noninductive, 7.37
stacked-fIlm, noninductive, 7.37
finite ESR, 7.37
real,parasitics,7.38
CB bipolar process, 1.1-2, 2.34
CB process, 1.1-2
CCD systems, using programmable gain
video amplifier, 2.54
Chadwick, P.E., 3.60
Channelizer, with numerically controlled
oscillator (NCO), 5.31
Checkovich, Peter, 2.71
Clamping amplifiers, 2.28-34
input and output compared, 2.30
Clarke, Bob, 3.1, 3.33-34, 3.54
Clelland, Ian, 7.46
CMOS switch:
disadvantages, 2.55
"on" resistance, 2.55
CMR; see: Common-mode rejection
CMRR; see: Common-mode rejection-ratio
Coaxial cable:
skin effect, 2.13
wire resistance, 2.13
Coleman, Brendan, 4.49
Colotti, James J., 4.49
Common-mode rejection-ratio instrumentation amplifiers, 2.18-19
Communications, high speed integrated
circuits, chipset solutions, P.2
Compandor, 3.1
Complementary bipolar process, 1.1
Compression:

INDEX

linear dynamic range, 3.1
variable-gain amplifiers, 3.1
magnetic recording, 3.1
Counts, Lew, 3.60
Coupling, EMIIRFI, 7.73
Current feedback (CFB) process, 1.2
Current noise gain, op amp, defmition,
1.21-22
Current-output DACs, 1.12
Current-to-voltage converter, input capacitance compensation, 1.24

D
DAC:
5-bit binary, architectures, 6.19
5-bit thermometer:
architecture, 6.19
disadvantage, 6.18
10-bit, CMOS current switch core,
scheme, 6.20
10-bit segmented:
PMOS transistor current switches, 6.21
scheme, 6.20
12-bit:
SFDR, clock vs. output frequency, 6.13
SHA deglitched, XFCB fabricated, 6.2324
and DDS systems, 6.1-30
deglitching, 6.23-24
using SHA, 6.23
fully decoded, architecture, 6.19
glitch impulse area, 6.14
grounding, 7.28
interpolating, 6.25-27
low distortion, architecture, 6.18-22
performance:
measurement, spectrum analyzer, 6.15
SFDR measurement, 6.16
SFDR, improvement, using SHA
deglitchers, 6.23-24
triple video, 2.43, 2.46
TTL-compatible, 6.15, 6.17
Data transmission:
asymmetric digital subscriber line, 2.6061
discrete multi tone modulation, 2.60
DDS:
125MSPS system, 6.7-8
frequency tuning, 6.8
phase modulation, 6.8
serial loading, 6.8
AD9830/9831 CMOS system, 6.10-11
key specifications, 6.11
structure, 6.10-11
as ADC clock drivers, 6.9

comparator, 6.9
complementary DAC, 6.9
filter, 6.9
scheme, 6.9
aliasing, 6.5-6
DAC output, 6.5-6
graph, 6.6
higher-order harmonics, 6.6
Nyquist bandwidth, 6.6
Nyquist criteria, 6.5
Nyquist frequency, 6.5
amplitude modulation:
by digital multiplier, 6.10
scheme, 6.10
basic architecture:
differing from PLL, 6.2
flexible system, scheme, 6.3
numerically controlled oscillator, 6.3
block diagram, 6.3
flexibility, 6.4
output spectrum, 6.4-5
PROM-driven clock, 6.2
scheme, 6.2
digital audio CD player, interpolation,
6.25
filter:
analog, requirements, 6.26
antialiasing, 6.25
Butterworth, 6.25
low pass, 6.25
interpolation, 6.25
QPSK signal generation, 6.28-29
constellation, 6.29
modulator, 6.28
scheme, 6.28
SFDR considerations, 6.12-17
clock selection, 6.12
DAC glitch impulse area, 6.14
DAC output spectral purity, 6.12
digital dither, and quantization noise,
6.13
harmonic distortion, 6.14
harmonics, 6.12
even, location, 6.16
odd, location, 6.17
non-ideal DAC, distortion, 6.14
Nyquist bandwidth, 6.12
output glitches, 6.14
specifications, 6.15
tuning equation, 6.4
Deadbug prototyping, 7.9-10
Designing for EMC (Workshop Notes),
7.88,7.103
Differential line drivers and receivers,
2.18-28
active feedback receiver, 2.26-28
Index-7

HIGH SPEED DESIGN TECHNIQUES

video, 2.26-27
approaches, 2.19-20
cross-coupled driver, 2.22-24
cell bandwidth, 2.23
circuit benefits, 2.23
gain calculations, 2.22-23
high common-mode rejection, 2.22
four-resistor receiver, 2.24-26
video:
diagram, 2.25
drawback, 2.26
gain/phase performance, 2.26
high common-mode rejection-ratio
instrumentation amps, 2.18-19
inverter-follower driver, 2.20-21
diagram, 2.20
input impedance, 2.21
open-loop bandwidth matching, 2.21
resistor gain error effects, 2.21
single-ended driver, source-terminated
coaxial cable, 2.20
Digital communication systems, 16-QAM
modulation, 5.50
Digital communications system, QPSK
modulation, 5.49
Digital ground, separated from analog
ground, 7.28-29
Digital mobile radio, IF stages, schematic,
3.33
Digital receivers:
AMPS analog cellular phone system,
5.21,5.33
image frequency at receiver, 5.21
one receiver per channel, 5.22
digital communication systems, 5.49-53
16-QAM modulation system, 5.50
modulation systems, 5.49-50
QPSK modulation system, 5.49-50
digital processing at baseband, 5.22-24
schematic, 5.23
software radios, 5.22-23
direct broadcast satellite set-top boxes,
5.49-53
direct IF-to-digital, 5.38-41
FFr output, 5.39
SFDR, 5.38-39
narrowband IF-sampling, 5.24-30
advantages, 5.24
comparison with wideband, 5.31
DSP functions, 5.28
GSM system, 5.24, 5.27-28
Bandpass sampling, 5.29
digital filtering and decimation, 5.29
diversity, 5.27-28
f"'C'l\JI" 9..... A l\JI"UC' J::: OA
v o • ..
u, V.U"'l:
Nyquist frequency, 5.28
U-U.Ll~

Index-8

.c~ LY~~

Nyquist zones, 5.28
oversampling, 5.28
processing gain, 5.30
RSSI peak detector function, 5.27
SINAD, 5.30
SNR, Nyquist bandwidth, 5.30
wide dynamic range using dither, 5.41-48
ADC transfer function randomizing,
5.42
dither noise generator, scheme, 5.46
effect on SFDR, 5.41-43
wideband IF-sampling, 5.31-38
AMPS cellular system, 5.33-34
process gain, 5.35
AMPS vs. GSM, 5.34
comparison with narrowband, 5.31
digital radio Channelizer, 5.31-32
scheme, 5.32
GSM:
disadvantages, 5.35-36
two-tone intermodulation distortion,
5.36
Nyquist zones, 5.35
SFDR, 5.33
Direct broadcast satellite set-top boxes:
IF signal processing, 5.52-53
modulation, 5.52-53
Direct broadcast satellite system:
ADC sampling rate, 5.50
bandwidth smears, 5.50
baud rate, 5.49
bit-error-rate, 5.49
block diagram, 5.52
constellation, 5.49
downlink frequency, Kuband, 5.52
eye patterns, 5.50
low noise block converter (LNBC), 5.52
MPEG encoding/decoding, 5.51
symbols, 5.49
Direct digital synthesis; See: DDS
Direct IF to digital conversion, 4.4-10
Discrete multi tone, modulation scheme,
2.60
Dostal, J., 1.36
Dual conversion superhet receiver, 3.33

E
EDN (Jan. 20,1994), 7.88, 7.103
Edson, J.O., 4.48
Electric field, strength, definition, 7.76
Electric-field intensity, in RFI, 7.76
Electromagnetic compatibility; See: EMC
Electromagnetic interference; See: EMI
Ellintic filter. 4.5
EMC Design'Workshop Notes, 7.46

INDEX

EMC Test & Design, 7.88
EMI:
cable:
capacitive coupling, 7.95
magnetic coupling, 7.95-96
twisted pair, for noise immunity, 7.96
unshielded as antenna, 7.96
paths, 7.34, 7.72
printed circuit board design, 7.83-87
device speed, 7.84
embedding, 7.85
multi-layer arrangement, striplines,
7.85
noise filter, 7.84
planes, 7.85
power supply filter, 7.84
signal line snubbing, 7.84
trace termination, 7.86
transmission lines, 7.86-87
protection, printed circuit board design,
7.83-87
receptors, 7.34, 7.72
regulations, 7.69-71
automotive equipment, SAE standards,
7.71
commercial equipment:
conducted interference, 7.69
emission limits, 7.70
FCC and VDE, 7.69-70
radiated emissions, 7.69
impact on design, 7.71
industrial- and process-control equipment, 7.71
medical equipment, 7.70
military equipment, MIL-STD-461, 7.70
sources, 7.34, 7.72
power-line transients, 7.80-81
see also entries under EMIJRFI and RFI
EMIJRFI, 7.69-87
coupling:
cable radiation and connector leakage,
7.73
slot and board radiation, 7.73
via interconnects, 7.73
diagnostics, source, path, and receptor,
7.72-74
emission:
conduction, 7.73
radiation, 7.73
immunity, 7.74
internal, 7.74
passive components, 7.75
path:
conduction, 7.73
radiation, 7.73
shielding, 7.89-102

ground loops, 7.97-98
grounded, 7.97
signal amplitude, 7.74
signal distance, 7.74
signal frequency, 7.74
signal impedance, 7.74
signal time, 7.74
source-path-receptor model, 7.72-74
susceptibility, 7.74
see also separate entries under EMI, RFI
Emitter degeneration:
voltage feedback op-amp, 1.6
effects on equipment, 1.6
ENOB, 4.18-21
Equivalent number of bits; See: ENOB
Equivalent series inductance; See: ESL
E.S.D. Prevention Manual, 7.104
European digital cellular system; See:
GSMsystem
Evaluation board, 7.17-26
buffer memory design, 7.22
DAC, 7.20-21
FFT,7.20-21
FIFO memory, 7.22-23
IC performance verification, 7.24
for op amp, 7.17-19
power supply decoupling, 7.19
transient currents, 7.19
Windows software:
DNL histogram, 7.25
FFT output, 7.25
time-domain data, 7.24
Exponential amplifier, 3.4
Extra fast complementary bipolar (XFCB)
process, 1.1

F
Faraday shields, 7.82
Federal Communications Commission;
See: FCC
Ferrite:
bead, 7.39
characteristics, 7.39
choice, 7.40
impedance, 7.39-40
leaded bead, 7.39
low-pass filter, 7.39
nonconductive ceramics, 7.39
PSpice models, 7.40
Filter:
antialiasing:
effects on system dynamic range, 4.4
and Nyquist frequency, 4.5
requirements:
and increasing sampling frequency,
Index-9

HIGH SPEED DESIGN TECHNIQUES

4.6
relaxed, 4.6
specifications, 4.4
transition band:
determination, 4.5
sharpness vs. ADC sampling frequency, 4.6
undersampling, 4.8-10
Bandpass specifications, 4.9
centering signal in Nyquist zones, 4.9
equations, 4.8-10
band, 7.40
baseband antialiasing, 4.4-6
Butterworth, 4.5
elliptic, 4.5
low pass:
ferrite, 7.39
and RFI effects, 7.78-79
multiple feedback lowpass, design calculations, 1.24
multistage, for RFI effects, 7.79
RFI effects:
band filters, 7.79
feed-through protection, 7.79
Fixed-gain amplifier, in X-AMP, 3.4
Flash converter:
3 clock cycle latency, 4.38-39
basic interpolation circuit, 4.34
clamp amplifier driven, 2.33
diagram, 4.32
input, 4.33
input capacitance, high freque;ncy distortion, 4.33
latency cycles, 4.38
multi-pass subranging pipelined, 4.38
multi-stage conversion technique
(pipelining),4.37
pipeline delay, 4.38
pipelining, 4.37
preamplifiers, 4.35
sampling device, 4.32
thermometer code output, 4.31
Folded cascode:
voltage feedback op-amp architecture,
1.8-9
single-stage, 1.8-9
FPBW; See: Full-power bandwidth
Franco, Sergio, 1.36
Fredericksen, Thomas M., 1.36
Frequency division multiplexed communications, noise power ratio testing,
4.24
Frequency synthesis, using oscillators and
PLLs, 6.1
u- _________
___ L1.. __ ! ___
...
~

L'.l~y'U~U\';y i)yUW.l~i).lL.o~.l, u.~

Full power bandwidth (FPBW), 4.20
Index-10

G
Garcia, Adolfo A., 7.1, 7.69, 7.89
Gardner, F.M., 6.30
Gay, M.S., 3.60
Gelbach, Herman, 7.103
Gerke, Daryl, 7.105
Ghausi, M.S., 4.50
Gilbert cell, mixer, 3.57
Gilbert, Barrie, 1.36, 3.1,3.34,3.60-61
Glitch impulse area, 6.14
Gold, Bernard, 4.50
Gosser, Roy, 1.36,4.48
Graeme, Jerald G., 1.36,2.71
Graham, Martin, 7.26, 7.105
Grant, Doug, 7.105
Gray code, 4.42, 4.46
Gray, G.A., 4.48
Gray, Paul R., 1.36
Ground impedance, multicard system, 7.27
Ground loops, 7.97-98
Ground plane, EMIIRFI emissions, minimizing, 7.27
Grounding:
buffer latch, 7.30
and decoupling, 7.28-30
EMIIRFI emissions, minimizing, 7.27-33
high speed systems, 7.27-33
multiple ground pins, 7.33
power supply, 7.30
sampling clock, 7.31
star ground, 7.27-28
GSM system, 5.24, 5.27-29, 5.33

H
Hageman, Steve, 7.46
Harmonic distortion, 4.17
definition, 4.17
location of distortion products, graph,
4.18
Harmonic sampling, 4.4-10
Harris, Frederick J., 4.49
Hendricks, Paul, 5.1
Henning, H.H., 4.48
Higgins, Richard J., 4.50
High speed hardware, design techniques,
7.1-105
High speed systems:
analog components, separation, 7.27-28
ground plane, low impedance, 7.27
grounding, 7.27-33
Hilton, Howard E., 4.50
Hodges,
David A., 4.49
LT ___ ..l ___ ___1..!L_-L____ __ ..l _..l ____ L _ _ _ _ £'
~V.luvuyu~ GU\,;U.l~\';"U.l~,

GU.lU

i::lUVGU.l"Glb~

superheterodyne, 3.33,5.21

V.l

INDEX

HP Journal (Apr. 1988), 4.49
HP Journal (June 1988), 4.50
HP Journal (Nov. 1982), 4.49
HP Product Note 5180A-2, 4.49
Hughes, Richard Smith, 3.60
I
IEEE Standard 746-1984, 2.71
IEEE Trial-Use Standard for Digitizing
Waveform Recorders, 4.50
IF sampling, 4.4-10
Imaging, high speed integrated circuits,
chipset solutions, P.2
Immunity, 7.76
Instrumentation, high speed integrated
circuits, chipset solutions, P.2
Integrated circuits:
chipset solutions, P.2
core competencies, P.3
markets, P.2
Interconnects, EMIJRFI coupling, 7.73
Intermodulation distortion; See: IMD
International EMI Emission Regulations,
7.104
An Introduction to the Imaging CCD
Array, 5.54

J
Johnson noise, 1.29
Johnson, Howard W., 7.26, 7.105
Jung, Walter G., 1.36, 2.1,2.71, 7.1, 7.34,
7.46-47, 7.55-56, 7.103,
7.105

K
Kaufman, M., 1.36
Keate, Chris, 5.54
Kerr, Richard J., 6.30
Kester, Walter A., 1.1,2.1,2.71,3.1,3.3334,3.54,4.1,4.49,5.1,
6.1, 7.1, 7.8, 7.17, 7.27, 7.105
Kimmel, Bill, 7.105
Kitchen, Charles, 3.60
Koernberg, Joey, 4.49

L
Laker, KR., 4.50
Lane, Chuck, 4.48
LE118211-pole elliptic antialiasing filter,
characteristics, 4.5
Lee, Hae-Seung, 4.49
Line driver, high speed op amp, singlesupply, 2.47
Linear Design Seminar (1995), 3.61, 4.48,
7.104

Log amp; See: Logarithmic amplifier
Log video, 3.19-20
Logarithmic amplifier, 3.17-32
basic architectures:
basic diode log amp, 3.21
successive detection log amp, 3.21
true log amp, 3.21
basic graph, 3.19
as converter, 3.17
detecting, 3.19-20, 3.23
diodelop-amp log amp, 3.21-22
disadvantages, 3.21
filter, internal low pass, cutoff frequency,
3.59
graph, 3.17
high frequency applications, preferred
architectures, 3.23
intercept voltage, 3.18
key parameters, 3.27
monolithic, successive detection stages,
3.31-32
multi-stage architecture, 3.23
multi-stage response, unipolar, 3.24
noise in dynamic range, 3.18
nonlinear dynamic range compression,
3.1
slope voltage, 3.19
specifications, 3.26-27
dynamic range, 3.26-27
frequency response, 3.26-27
intercept point, 3.26-27
waveform effect, 3.29-30
log linearity, 3.26-27
graph, 3.27
waveform effect, 3.30
noise, 3.26-27
slope of transfer characteristic, 3.26-27
successive detection:
cascaded limiting stages, 3.26
log and limiter outputs, 3.25-26
summing, 3.25
transfer characteristic, 3.18
transistorlop-amp log amp, 3.22
true, 3.19-20, 3.23
in summing amplifier, 3.25
in video display, 3.19
volts per decade factor, 3.19
Logarithmic video amplifier, 3.19

M
McDonald, John, 7.1, 7.34, 7.89
MagAmp , 4.42
3-bit folding ADC, 4.44
block diagram, 4.44
equivalent circuit, 4.44
input, 4.45
Index-11

HIGH SPEED DESIGN TECHNIQUES

residue waveforms, 4.45
6- and 7-bit ADCs, 4.37
8-bit folding ADC, 4.45
architecture, 4.36
gain-of-two folding stage, 4.46
Magnitude amplifier, 4.42
architecture, 4.36
Mahoney, Matthew, 4.50
Marsh, Richard, 7.46,7.105
Massobrio, Guiseppi, 7.26
Mathcad 4.0 Software Package, 4.50
Mayo, J.S., 4.48
Meehan, Pat, 4.49
Melsa, James L., 1.36
Meyer, Robert G., 1.36
Mil-STD-461, 7.70
Miller capacitance, in logarithmic amplifier, 3.21
Miller integrator, voltage feedback op-amp,
CB process, 1.7
Mini-Circuits LRMS-1H mixer, 3.44
Mitola, Joe, 5.54
Mixed-signal circuit, detmition, 7.1
Mixed-signal IC, grounding, 7.28
Mixer:
active, 3.36
1dB gain compression level, 3.50-53
basic operation, 3.46-47
BJT form, 3.45-46
classic, 3.45-46
design objectives, 3.50
different from diode-ring, 3.46
gam, 3.47
IMD, 3.50
spur chart, 3.52-53
third-order, plot, 3.51
third-order intercept, 3.50-53
noise figure, 3.49
poor dynamic range, 3.53
scheme, 3.45
various uses, 3.47
as analog multiplier, optimized for
frequency translation, 3.53
conversion gain, 3.36
detmition, 3.36
diode-ring, 3.43-44
circuit non-linearity, 3.52
diagram, 3.43
gallium-arsenide diodes, 3.43
passive, noise figure, 3.49
silicon junction diodes, 3.43
silicon Schottky-barrier diodes, 3.43
diodes, nonlinearity, impedances, 3.43
downconverter, 3.35
FET, 3.44-45
diode burnout prevention, 3.44
Index-12

dual-gate MOS-FET, 3.44-45
insertion losses, 3.44
high level, 3.35
high-side downconverter, 3.35
ideal, 3.40-42
idealized, scheme, 3.34
low-side downconverter, 3.35
modulator optimized for frequency
translation, 3.36
multiplying:
inputs and outputs, 3.37
mathematics, 3.38
output spectrum, 3.38
noise and matching, 3.36
port:
intermediate frequency output, 3.34
local oscillator input, 3.34
RF input, 3.34
RF, scheme, 3.37
summary, 3.53
switching:
harmonic components, 3.42
image response, 3.42
inputs and outputs, 3.41
mathematics, 3.41-42
output spectrum, 3.42
scheme, 3.40
up converter, 3.35
Mobile phone, RF signal, mixing, demodulation, 3.59
Modulator:
balanced, 3.35
doubly-balanced, 3.35
high level mixer, 3.35
response, 3.36
as sign-changer, 3.35
Moreland, Carl, 4.48
Morrison, Ralph, 7.88, 7.103, 7.104
Motion Picture Experts Group; See: MPEG
Motorola 5082-4204 PIN Photodiode, 2.64
characteristics, 2.64-65
Motorola MC1496 mixer, 3.45
Multiplexer:
expanding two 4:1 into 8:1, 2.58
video circuit, op amps using disable
function, 2.51-53
Multiplier:
analog, 3.35
for mixing, 3.36-38
four-quadrant, 3.35
linear, devices, 3.35
mathematical, 3.35
response, 3.36
single-quadrant, 3.35
two-quadrant, 3.35
Muncy, Neil, 7.103

INDEX

Murden, Frank, 4.48
Mux; See: Video multiplexer

N
N-channel JFET pair input stage, negative
rail, 2.36
Nash, Eamon, 2.46
Nicholas, Henry T., III, 6.30
Noise:
Boltzmann's constant, 1.30
calculation, principles, 1.30-31
equivalent noise bandwidth, calculation,
1.28
Johnson, 1.29
minimizing, by signal separation, 7.31
photodiode preamplifier, analysis, 2.69-70
power supply, reduction and filtering,
7.34-46
reduction tools, 7.35
shot-noise voltage, 1.30
sources, output, 1.29
voltage, 1.30
Noise analysis, photodiode preamplifier,
2.69-70
Noise figure:
calculation, 3.49
definition, 3.49
opamp, 1.32
calculation, 1.32
Noise gain:
circuit, 1.22
definition, 1.21-22
high, 2.4-5
follower stability, 2.5
inverter stability, 2.5
source, 1.21-22
Noise power ratio, 4.24-27
peak,4.26
Non-saturating emitter-coupled logic, 1.12
Numerically controlled oscillator:
32-bit phase accumulator, output spectrum,6.4-5
delta phase register, 6.3
n-bit phase accumulator, 6.4
part of DDS system, 6.4
phase accumulator, 6.3
Nyquist bandwidth, 4.3, 4.10, 5.30, 6.2, 6.6,
6.12
Nyquist criteria, 4.7-8, 6.5
Nyquist frequency, 5.28, 6.5
Nyquist zones, 4.3, 4.8, 5.28, 5.35, 5.40

o
O'Brien, Mark, 5.54
Ohmtek (firm), 2.71

Opamp:
amplifier bandwidth vs. supply current,
1.1
diagram, 1.2
applications, 2.1-71
gain/phase matched signals, 2.18
bias currents, 1.34
cable driver:
pulse response, 2.14-17
source-end termination, 2.15-16
cable drivers and receivers, 2.12-17
capacitive load compensation:
active, 2.8-9
damping resistor, 2.7-8
and frequency response, 2.7
in-the-Ioop, 2.8-9
internal, 2.9-10
CFB; See: Op amp, current feedback
clamping, 2.28-34
classical noise model, 1.28-29
closed-loop output impedance, 2.16
current feedback, 1.12-18
active fIlter, 1.22-23
bandwidth, 1.17, 1.18
Bode plot, 1.14
closed-loop bandwidth, 1.14-15
determination, 1.17
current-to-voltage converter:
advantages, 1.26-27
input capacitance compensation, 1.25
low inverting input impedance, 1.27
distortion, 1.18
family characteristics, 1.18
feature summary, 1.18
feedback capacitance effects, noise gain,
1.20-21
full-power bandwidth, 1.17
input bias currents, 1.34
input capacitance compensation,
current-to-voltage converter, 1.25
input current noise, 1.30
input voltage noise, 1.30
inverting impedance level, 1.12-13
inverting input impedance, 1.17, 1.27
inverting mode, advantages, 1.27
key features, 1.17
low impedance, 1.27
model, 1.14
simplified diagram, 1.13
slew rate, 1.13, 1.18
suitability, configurations, 1.22
triple, 2.51-53
in video programmable gain amplifier, 2.54-55
wideband:
capacitive loads, 2.3-12
Index-13

HIGH SPEED DESIGN TECHNIQUES

forced-high loop noise gain, 2.4
overcompensation, 2.4
stability, 2.4
linear drivers, design, 2.3
optimum bandwidth flatness, 2.1-12
feedback resistors, 2.1-2
zero slew-rate limitation, 1.13
current feedback vs. voltage feedback,
noise comparisons, 1.28-33
current-to-voltage converter, 1.24-27
compensation calculations, 1.25
inverting input capacitance effects,
1.24-27
DC characteristics, 1.33-35
output offset voltage, summary, 1.34
differential line drivers and receivers,
2.18-28
evaluation board, schematic, 7.17-18
feedback capacitance effects, 1.19-24
Bode plot, 1.20-21
closed loop bandwidth, 1.20
noise gain, 1.19-20
signal bandwidth, 1.20
signal gain, 1.19-20
feedforwardlfeedback resistors, 1.31
input bias current, and common-mode
voltage, 2.37
Johnson noise, 1.29-30
N -channel JFET pairs, 2.36
noise, summary, 1.33
noise comparisons, 1.28-33
model, 1.28-29
noise figure, 1.32
calculation, 1.32
noise sources, 1.29,1.31
closed-loop gain, 1.31
output stage:
common emitter, 2.39
emitter follower, 2.39
output voltage offset, model, 1.33
PNP input, negative rail, 2.36
power pins, decoupling, 1.35
power supply rejection ratio, characteristics, 1.35
rail-to-rail input, 2.34
rail-to-rail output, in low dropout references, 17.48
review, 1.1-36
single-supply, 2.34
AC-coupled, headroom considerations,
2.48-50
AC-coupled single-ended-to-differential
driver, 2.50-51
ADC direct-coupled driver, 2.40-41
ADC low-distortion ADC driver, 2.42-43
applications, 2.40-51
Index-14

AC-coupled, headroom considerations, 2.48-50
AC-coupled single-ended-to-differential driver, 2.50-51
ADC low-distortionADC driver, 2.4243
direct-coupled driver, 2.40-41
RGB buffer, 2.43-44
sync stripper, 2.44-46
video line driver with zero-volt
output, 2.46-47
characteristics, 2.35 .
design tradeoffs, 2.35
rail-to-rail input, 2.35
RGB buffer, 2.43-44
sync stripper, 2.44-46
video line driver with zero-volt output,
2.46-47
terminated cable, resistive load, 2.12
total output RMS noise, 1.28
VFB; See: Op amp, voltage feedback
video, 2.51
video line driver, 2.17
video line receiver, 2.25
voltage feedback, 1.2-12
active fIlter, 1.22-23
amplifier unity gain-bandwidth product,1.3
bandwidth calculation, 1.6
bipolar:
inefficiency, 1.6
slew rates, 1.6
Bode plot, 1.4
.
capacitive load compensation, in-theloop, 2.9
capacitor in feedback loop, 1.20
noise gain, 1.20-21
circuit topology, 1.2
closed-loop bandwidth vs. closed-loop
gain, 1.5
complementary bipolar process, 1.1,
1.7-10
BiFET, circuit, 1.10
components, 1.7
input differential pair, 1.7
JFETs,1.9
tail currents, 1.9
Miller integrator, 1.7
model, 1.8
two gain stages, diagram, 1.7
current-on-demand architecture, 1.1012
quad-core structure, diagram, 1.11
current-to-voltage converter:
input capacitance compensation, 1.24
in photodiode, 2.65-66

INDEX

de-compensated, 1.5
emitter degeneration, 1.6
feedback capacitance effects, noise gain
stability, 1.20-21
folded casco de architecture, 1.8-9
circuit, 1.9
stability, 1.9
unity-gain compensated, 1.9
full-power bandwidth, 1.6
calculation, 1.5
fundamental property, 1.5
gain-bandwidth product, 1.5
in high-speed ADC applications, 5.16
model, 1.4
NPN process, 1.2-3
diagram, 1.3
quad-core structure, diagram, 1.11
rail-to-voltage, single-supply, performance, 2.46
slew rate calculation, 1.6
structure, 1.3-4
equations, 1.4-5
input stage, 1.3
tail current, 1.3
transconductance stage, 1.3
voltage feedback vs. current feedback,
noise comparisons, 1.28-33
OS-CON capacitor, 7.36
Ott, Henry W., 1.36, 7.46, 7.88, 7.103, 7.104
Overcompensation, op amp bandwidth
reduction, 2.4
Oversampling; See: Sampling,
oversampling

p
PCRR; See: Power supply rejection ratio
Pease, Robert A., 7.10, 7.26, 7.104
Personal communications systems, 5.31
PGA; See: Programmable gain video
amplifier
Phase jitter, 4.27
Phase-Locked Loop Design Fundamentals,
6.30
Phase-locked loops, 6.1
Photoconductive photodiode mode, 2.63
Photodiode:
circuit sensitivity, 2.64
dark current, 2.63
equivalent circuit, 2.62
frequency response and stability analysis, 2.65-66
high bandwidth preamplifier, equivalent
circuit, 2.64
Motorola 5082-4204 PIN:
characteristics, 2.64-65

Photoconductive mode, 2.64-65
operating bias, 2.63
operating modes, 2.63
preamplifier:
comparisons, 2.67
dark current compensation, 2.68
equivalent noise bandwidth, 2.69
key parameters, 2.64
noise analysis, 2.69-70
optimizing, 2.63-64
output noise analysis, 2.69-70
eqUivalent circuit, 2.70
selection, 2.67-68
preamps, 2.62-70
second-order current-to-voltage converter:
input capacitance compensation, 2.66
using voltage-feedback op-amp, 2.65-66
shunt resistance, 2.62-63
Photovoltaic photodiode mode, 2.63
Pin sockets, 7.16
PMOS transistor current switches, 6.21
PNP input stage, negative rail, 2.36
Power:
dissipation:
AID converters, 7.62
calculation, 7.61-62
clock dependent, 7.62
Power supply:
analog ready filters, 7.34
decoupling, 7.30
filter, ferrites, 7.39
grounding, 7.30
noise reduction and filtering, 7.34-46
power line filter, 7.44-45
regulation/conditioning, 7.47-54
basic references, 7.47-48
low dropout references, 7.47-54
linear IC regulators, 7.52-53
rail-to-rail output op amp, 7.48
low dropout regulators, 7.50-54
boosted output with current limiting,
7.51
controlled gain bipolar power transistor, 7.50
scaled references, 7.49-50
low voltage rail-rail, 7.49
separate for analog/digital circuits, 7.31
switcher:
band filter, 7.40
"card-entry" filter, 7.41
disadvantages, 7.43
output response testing, 7.42
SPICE simulation, 7.42
filter layout/construction, guidelines,
7.44
Index-15

HIGH SPEED DESIGN TECHNIQUES

high frequency localized decoupling,
7.43
output noise, 7.34
capacitor as filter, 7.34
Practical Analog Design Techniques
(1995),2.71,4.48, 7.26
Printed circuit board design, EMI protection, 7.83-87
Programmable gain video amplifier, using
triple current-feedback op amp,
2.54-55
Prototyping, 7.8-17
CAD techniques:
Gerber file, 7.14
pattern-generation tape, 7.14
commercial breadboarding, 7.11
"Deadbug",7.9-10
"Deadbug" with predrilled copper-clad
board, 7.10-11
gold-plated contacts, 7.16
IC sockets:
cage jacks, 7.16
cautions, 7.16
pin sockets, 7.16
large-area ground-plane, 7.8
"milled" technique, 7.14-15
multilayer PC boards, disadvantages,
7.16
point-to-point wiring, "hird's nest", 7.10
Solder-Mount, 7.11-14
advantages, 7.11-13
components, 7.12
PSpice Simulation Software, 7.26

Q
QPSK modulation, in digital communication systems, 5.49-50
Quadrature phase shift keying; See: QPSK
Quantization noise, 4.11

R
Rabiner, Lawrence, 4.50
Radio frequency interference; See: RFI
Rail-to-rail:
high speed op amp:
application considerations, 2.38
characteristics, 2.34
input stage:
topology, 2.37
two long-tailed pairs, 2.36
output stage, 2.38-39
implications, 2.34-39
Ramierez, Robert W., 4.49
Received signal strength indicator; See:
RSSI
Index-16

Receiver:
demodulation:
architecture, 3.57
linear, 3.55
inphase/quadrature, 3.56
polar, 3.57-58
design overview, 3.33-34
high-side injection, 3.35
image frequency, 3.39
image response, 3.39-40
filter, 3.40
scheme, 3.39
low-side injection, 3.35
modulation, 3.54-57
amplitude, 3.54
rectangular and polar representations, 3.54
phase, 3.54
rectangular and polar representations, 3.54
subsystem, 3.54-59
Rectification, analog circuits, 7.77
Reidy, John, 4.49
RFIIF subsystems, 3.1-61
automatic gain control, 3.2-9
dynamic range compression, 3.1-2
logarithmic amplifiers, 3.17-32
modulation/demodulation, 3.2
multipliers, modulators, and mixers,
3.34-53
receivers, 3.54-59
overview, 3.33-34
RMS-linear-dB measurement system,
3.9-16
RMSIDC converters, 3.9-16
signal dynamic range compression
techniques, 3.2
voltage-controlled amplifiers, 3.4-9
RFI, 7.76-80
analog circuits:
coupling:
power supplies, 7.78
signal inputs, 7.78
signal outputs, 7.78
filter failure, 7.79-80
low pass filters, leakage, 7.78
multistage filters, 7.79
protection, 7.77-80
rectification, 7.77
disruption:
shielded cables, 7.76
to analog circuits, 7.76
electric-field intensity, 7.76
immunity, definition, 7.76
power-line disturbances, 7.80-82
Faraday shields, 7.82

INDEX

filters, 7.81
transformers, 7.82
transient protection, 7.80-81
rectification, analog circuits, 7.77
see also entries under EMIIRFI and EMI
RGB buffer, single-supply, 2.43-44
RGB multiplexer, dual source, with three
2:1 multiplexers, 2.57
RGB signal, digitizer, with ADC and 4:1
multiplexer, 2.57
Rich, A., 7.88, 7.103
RMS-linear-dB measurement system:
deviation from ideal logarithmic output,
3.12
logarithmic output vs. input signal level,
3.12
signal output vs. input level, 3.11
RMSIDC converter, as detector element in
automatic gain control loop, 3.9
Roberge, J.K, 1.36
Ruscak, Steve, 4.48
Ruthroff, C.L., 3.60

s
SIN+D; See: Signal to noise and distortion
Sallen-Key filter, 1.22-23
Sampling, 4.1-47
and analog demodulation, 4.8
bandpass, 4.7-10
baseband, Nyquist zones, 4.4
direct IF to digital conversion, 4.4-10
filters, 4.3
baseband anti ali asing, 4.4-6
frequency vs. anti aliasing filter requirements' 4.6
fundamentals, 4.2-3
aliases, 4.2-3
Nyquist bandwidth, 4.3-4
Nyquist zones, 4.3-4, 4.7-8
signal images, 4.2
harmonic, 4.7-10
IF, 4.7-10
oversampling, 4.10
undersampling,4.7-10
antialiasing filters, 4.8-10
Nyquist criteria, 4.7-8
Nyquist zones, 4.7-8
scheme, 4.7
Sampling clock:
distribution, digital to ground plane, 7.32
generator, grounded to analog ground
plane, 7.31
grounding, 7.31
jitter, 4.28
SNR degradation, 7.31
Samueli, Henry, 6.30

Schmid, Hermann, 4.48
Schottky diode, 1.27,2.33, 7.28
Schultz, Donald G., 1.36
Schweber, Bill, 5.54
Semiconductor:
ambient temperature, 7.58
device junction, 7.58
junction temperature upper limit, 7.56
standard package thermal resistance,
7.59
thermal management, 7.56-68
SFDR, 4.21-22
SHA, deglitcher for DAC, 6.23-24
Sheingold, Daniel H., 1.36, 3.60, 4.50
Shielding:
cable, 7.93-95
electrically shortllong application, 7.9395
low frequency interference, 7.95
pigtail terminations, 7.102
twisted-pair, grounding, 7.95-102
circuit:
characteristics, 7.89
conductive enclosures, 7.89
absorption, 7.89-91
effectiveness, 7.89-90
reflection, 7.89-90
materials, impedance and skin depths,
7.92
openings as EMI waveguides, 7.92-93
effectiveness, equation, 7.93
EMIIRFI emissions, 7.89-102
ground loops, 7.97-98
grounding, 7.97-98
proper techniques, 7.97-98
interference:
distance, 7.89
impedance, 7.89
source, 7.89
surrounding environment, 7.89
line driver, hybrid grounding, 7.101
sensor, 7.93-95, 7.97-100
hybrid grounding, 7.100
type and configuration, 7.101-102
Shot-noise voltage, 1.30
Signal routing, in PC board layout,
scheme, 7.32
Signal-to-noise and distortion ratio; See:
SINAD
Signal-to-noise ratio; See: SNR
SINAD, 4.18-19
Singer, Larry, 4.48
Single-supply:
high speed op amp:
applications, 2.40-51
characteristics, 2.35
Index-17

HIGH SPEED DESIGN TECHNIQUES

rail-to-rail input, 2.35
implications, 2.34-39
signal swing maximization, 2.34
Single-supply AC-coupled circuits, headroom considerations, 2.48-50
Single-supply AC-coupled single-ended-todifferential driver, 2.50-51
Single-supply ADC direct-coupled driver,
2.40-41
Single-supply ADC low-distortion ADC
driver, 2.42-43
Single-supply RGB buffer, 2.43-44
Single-supply sync stripper, 2.44-46
output, 2.46
Single-supply video line driver with zerovolt output, 2.46-47
Slattery, B., 7.88
Slattery, Bill, 7.104
Slot and board radiation, EMIIRFI, 7.73
Small signal bandwidth (SSBW), 4.20
Smith, Lewis, 1.36
SNR, 4.18-19
Source-path-receptor model, EMIIRFI,
7.72-74
Spurious free dynamic range; See: SFDR
Stout, D., 1.36
Successive approximation; See: SAR
Superheterodyne, receiver, 3.33, 5.21
Sync stripper, single-supply, 2.44-46
Systems Application Guide (1993), 4.48,
4.49,7.103
Systems Application Guide (1994), 7.88

T
Tail current, voltage feedback, 1.3
Tant, M.J., 4.48
THD+N, 4.17
THD,4.17
Thermal management:
airflow control, 7.63-68
on-chip temperature control, 7.63
calculating power in various devices,
7.61-63
power dissipation, 7.61-62
semiconductors, 7.56-68
thermal basics, 7.56-60
thermal resistance, 7.56-57
power dissipation vs. temperature, 7.57
TMP12:
airflow sensor, 7.64
parasitic temperature errors, minimization, 7.66
setpoint controller, scheme, 7.67
temperature relatior~hips, 7.65
Total harmonic distortion; See: THD
Index-18

Total harmonic distortion plus noise; See:
THD+N
Transconductance, voltage feedback, smallsignal, formula, 1.3
Transmission line:
driving, preferred method, 2.15
parasitics, 2.3
True log amplifier, 3.19-20,3.26
Tukey, J.W., 4.49

U
mtrasound systems, using programmable
gain video amplifier, 2.54
Undersampling:
Nyquist criteria, 4.7-8
Nyquist zones, 4.7-8
scheme, 4.7

V
VCA; See: Voltage controlled amplifier
Vector Electronic Company, 7.26
Verband Deutscher Electrotechniker; See:

VDE

VFB; See: Voltage feedback
Video:
composite, single-supply AC-coupled line
driver, 2.49-50
high speed integrated circuits, chipset
solutions, P.2
Video amplifier, programmable gain, 2.5455
Video crosspoint switch, buffered, 2.59
Video line driver, 2.18
.
single-su pply:
AC-coupled, 2.49
zero-volt output, 2.46-47
Video line receiver, 2.25
gain-scaling, 2.26
loop-through connection, 2.27-28
NTSC performance, 2.28
overvoltage protection, 2.25-26
Video log amplifier, 3.26
Video multiplexer:
2:1:
diagram, 2.53
off-channel isolation, 2.53
3:1, diagram, 2.52
bipolar, diagrams, 2.56
crosspoint switches, 2.55-59
disable function, 2.51-53
Video op amps, 2.51
Video programmable gain amplifier, with
triple current-feedback op amp,
n ~A ~~
.&..U
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