1996_Cypress_Programmable_Logic_Data_Book 1996 Cypress Programmable Logic Data Book

User Manual: 1996_Cypress_Programmable_Logic_Data_Book

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Tools

1996

Cathy Russell
Account Manager

Marshall Industries
Bay Area
336 Los Coches Street
Milpitas, CA 95035
(408) 942-4600
(408) 262-1224 Fax
(408) 942-6039 Voice Mail
(408) 994-0839 Pager
Email: crussell@001 .marshall.com
Internet Web site : www.marshall.com

marshall

CYPRESS
Programmable Logic
Data Book
1996

Cypress Semiconductor is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor, 3901 North First St., San Jose, CA 95134 (408) 943-2600
Telex: 821032 CYPRESS SNJ UD, TWX: 910 997 0753, FAX: (408) 943-2741
FAX-On-Demand: 1-800-213-5120 or 1-408-943-2798, Web Address: http:/www.cypress.com

How To Use This Book
Overall Organization

Key to Waveform Diagrams

This book has been organized by product type, beginning with Product Information. The products are
next, starting with Small PLDs, CPLDs, FPGAs, and
Development Systems. A section containing Quality
is next, followed by a Package Diagrams section.
Within each section, data sheets are arranged in
order of part number.

Rising edge of signal will
occur during this time.

=

Falling edge of signal will
occur during this time.

Recommended Search Paths

To search by:

Use:

Product line

Table of Contents or flip
through the book using the
tabs on the right-hand pages.

Size

The Product Selector Guide
in section 1.

Numeric part number Numeric Device Index following the Thble of Contents. The book is also arranged in order of part
number.

Signal may transition
during this time (don't
care condition).
Signal changes from highimpedance state to valid
logic level during this time.
Signal changes from valid
logic level to high-impedance
state during this time.

Other manufacturer's The Cross Reference Guide
part number
in section 1.
Military part number

The Military Selector Guide
in section 1.

Published November 1995

© Cypress Semiconductor Corporation, 1995. The infonnation contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use many circuitry other than circuitry embodied In a Cypress Semiconductor Corporation product. Nor does it conveyor imply any license under patent or other rights. Cypress Semiconductor does not authoriZe its products for use as critical components in /ife..support systems where a malfunction or failure of the product may reasonably be expected to result in significant
injury to the user. The inclusion of Cypress Semiconductor products in life-support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies
Cypress Semiconductor against all damages.

Table of Contents
Page Number

Table of Contents
General Information

Cypress Semiconductor Background ......................................................................... 1-1
Ordering Information ..................................................................................... 1-4
Cypress Semiconductor Bulletin Board System (BBS) Announcement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-5
Application Notes ........................................................................................ 1-6
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
Product Line Cross Reference ............................................................................. 1-10
Military Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-14
Military Product Selector Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-15
Military Ordering Information .................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-17

Small PLDs (Programmable Logic Devices)
Introduction to Cypress PLDs

2-1

Device

Description

PALC20 Series
PALCE16V8
PALCE20V8
PLDC20GlOB
PLDC20GlO
PLDC20RAlO
PALCE22VlO
PALC22VlO
PALC22VI0B
PAL22VI0C
PAL22VPI0C
PALC22VlOD
CY7C330
CY7C331
CY7C332
CY7C335

Reprogrammable CMOS PALC 16L8, 16R8, 16R6, 16R4 . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-6
Flash Erasable, Reprogrammable CMOS PAL Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-7
Flash Erasable, Reprogrammable CMOS PAL Device .............................. 2-17
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. 2-27
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. 2-27
Reprogrammable Asynchronous CMOS Logic Device ............................. 2-35
Flash Erasable, Reprogrammable CMOS PAL Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-46
Reprogrammable CMOS PAL Device ........................................... 2-56
Reprogrammable CMOS PAL Device ........................................... 2-57
Universal PAL Device ........................................................ 2-58
Universal PAL Device ........................................................ 2-58
Flash Erasable, Reprogrammable CMOS PAL Device .............................. 2-59
CMOS Programmable Synchronous State Machine ................................ 2-68
Asynchronous Registered EPLD ............................................... 2-69
Registered Combinatorial EPLD ............................................... 2-83
Universal Synchronous EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-84

CPLDs (Complex PLDs)
Device

Description

Ultra39000
Ultra39192
Ultra39256
Ultra39320
Ultra39384
Ultra39448
Ultra39512
FLASH370 CPLD Family
CY7C371
CY7C372
CY7C373
CY7C374
CY7C375
FLAsH370i ISR CPLD Family
CY7C371i
CY7C372i
CY7C373i

UltraLogic High-Density CPLD Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
UltraLogic 192-Macrocell CPLD ................................................ 3-2
UltraLogic 256-Macrocell CPLD ................................................ 3-3
UltraLogic 320-Macrocell CPLD ................................................ 3-4
UltraLogic 384-Macrocell CPLD ................................................ 3-5
UltraLogic 448-Macrocell CPLD ................................................ 3-6
UltraLogic 512-Macrocell CPLD ................................................ 3-7
UltraLogic High-Density Flash CPLDs ........................................... 3-8
UltraLogic 32-Macrocell Flash CPLD ........................................... 3 -15
UltraLogic 64-Macrocell Flash CPLD ........................................... 3-24
UltraLogic 64-Macrocell Flash CPLD ........................................... 3-33
UltraLogic 128-Macrocell Flash CPLD .......................................... 3-43
UltraLogic 128-Macrocell Flash CPLD .......................................... 3-54
UltraLogic High-Density Flash CPLDs .......................................... 3-66
UltraLogic 32-Macrocell Flash CPLD ........................................... 3-73
U1traLogic 64-Macrocell Flash CPLD ........................................... 3-82
UltraLogic 64-Macrocell Flash CPLD ........................................... 3-91
iii

~

¥-,~

Table of Contents

==', CYPRESS
CPLDs (Complex PLDs) (continued)
Device

Description

CY7C374i
CY7C375i
CY7C340 EPLD Family
CY7C341B
CY7C341
CY7C342B
CY7C342
CY7C343
CY7C343B
CY7C344
CY7C344B
CY7C346
CY7C346B

UltraLogic 128·Macrocell Flash CPW .......................... . . . . . . . . . . . . . ..
UltraLogic 128·Macrocell Flash CPW .........................................
Multiple Array Matrix High·Density EPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
192·Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
192·MacrocellMAXEPLD ...................................................
128·Macrocell MAX EPWs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
128·Macrocell MAX EPLDs .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64·Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64·Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
32·MacrocellMAXEPW ....................................................
32·MacrocellMAXEPLD ....................................................
128·Macrocell MAX EPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
128·Macrocell MAX EPWs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-100
3-110
3-122
3-128
3-140
3-141
3-158
3-159
3-159
3-175
3-175
3-189
3-189

FPGAs (Field Programmable Gate Arrays)
Device

Description

Ultra38000 Family
Ultra38003
Ultra338003
Ultra38005
Ultra338005
Ultra38007
Ultra338007
Ultra38009
Ultra338009
Ultra38012
Ultra338012
Ultra38016
Ultra338016
Ultra38020
Ultra338020
pASIC380 Family
CY7C381P
CY7C382P
CY7C3381A
CY7C3382A
CY7C383A
CY7C384A
CY7C3383A
CY7C3384A
CY7C385P
CY7C386P
CY7C3385A
CY7C3386A
CY7C387P
CY7C388P
CY7C3387P
CY7C3388P

UltraLogic Very High Speed CMOS FPGAs . .. .. . . . . .. . .. . .. .. . . . . . . .. . . .. . . . .. . .. 4-1
UltraLogic Very High Speed 3K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
UltraLogic Very High Speed 3K Gate 3.3V CMOS FPGA ........................... 4-6
UltraLogic Very High Speed 5K Gate CMOS FPGA . . .. .. . . .. . . . . . . . .. . . . . . . . .. . . .. 4-7
UltraLogic Very High Speed 5K Gate 3.3V CMOS FPGA .......... . . . . . . . . . . . . . . . .. 4-8
UltraLogic Very High Speed 7K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-9
UltraLogic Very High Speed 3.3V 7K Gate CMOS FPGA .......... . . . . . . . . . . . . . . .. 4-19
UltraLogic Very High Speed 9K Gate CMOS FPGA ............................... 4-20
UltraLogic Very High Speed 9K Gate 3.3V CMOS FPGA .......................... 4-21
UltraLogic Very High Speed 12K Gate CMOS FPGA .............................. 4-22
UltraLogic Very High Speed 12K (36K) Gate 3.3V CMOS FPGA . . . . . . . . . . . . . . . . . . .. 4- 23
UltraLogic Very High Speed 16K Gate CMOS FPGA .............................. 4-24
UltraLogic Very High Speed 16K Gate 3.3V CMOS FPGA ......................... 4-25
UltraLogic Very High Speed 20K Gate CMOS FPGA .............................. 4-26
UltraLogic Very High Speed 20K Gate 3.3V CMOS FPGA ......................... 4-27
UltraLogic Very High Speed CMOS FPGAs ...................................... 4-28
UltraLogic Very High Speed 1K Gate CMOS FPGA ............................... 4-35
UltraLogic Very High Speed 1K Gate CMOS FPGA ............................... 4-35
UltraLogic 3.3V Very High Speed 1K Gate CMOS FPGA .......... . . . . . . . . . . . . . . .. 4-44
UltraLogic 3.3V Very High Speed 1K Gate CMOS FPGA .......................... 4-44
UltraLogic Very High Speed 2K Gate CMOS FPGA ............................... 4-52
UltraLogic Very High Speed 2K Gate CMOS FPGA ............................... 4-52
UltraLogic 3.3V High Speed 2K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-61
UltraLogic 3.3V High Speed 2K Gate CMOS FPGA ............................... 4-61
UltraLogic Very High Speed 4K Gate CMOS FPGA ........... _. . . . . . . . . . . . . . . . . .. 4-69
UltraLogic Very High Speed 4K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-69
UltraLogic 3.3V High Speed 4K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-81
UltraLogic 3.3V High Speed 4K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-81
UltraLogic Very High Speed 8K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-90
UltraLogic Very High Speed 8K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-90
UltraLogic Very High Speed 8K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-100
UltraLogic Very High Speed 8K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-100

iv

~

~YPRESS

Table of Contents

Development Systems
PLD, CPLD, and FPGA Development Tools Overview .......................................................... 5-1

Device
Description
CY3120/CY3125
Wmp2+ VHDL Compiler for PLDs, CPLDs, and FPGAs ............................ 5-2
CY3121/CY3126
Wa1p2 VHDL Compiler for PLDs and CPLDs ..................................... 5-6
CY3130/CY3135
Wa1p3 VHDL Development System for PLDs, CPLDs, and FPGAs .................. 5-10
CY3140
ABEUSynario Design Software Kit for FLASH370 ................................. 5-15
CY3141
Wa1p3 PROSeries Bolt-In ..................................................... 5 -16
CY3146
Synopsys Design Software Kit for pASIC380 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -18
CY3500
Impulse3 Device Programmer and Adapters ...................................... 5 -19
Third-Party Tool Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 - 22

Quality
Quality, Reliability, and Process Flows ....................................................................... 6-1
pASIC380 Family ............... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-16
CY7C380 Family Quick Power Calculator .................................................................... 6-29
Moisture-Sensitive Devices Handling Information ............................................................. 6-34
Thermal Management and Component Reliability ............................................................ 6-36

Packages
Thpe and Reel Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-1
Package Diagrams ........................................................................................ 7-5

Sales Representatives and Distributors
Direct Sales Offices
North American Sales Representatives
International Sales Representatives
Distributors

v

~

_X
Numeric Device Index
=--/CYPRESS = = = = = = = = = = = = = = =
2JI

Page Number

Device Number

Description

CY3120/CY3125
CY31211CY3126
CY3130/CY3135
CY3140
CY3141
CY3146
CY3500
CY7C330
CY7C331
CY7C332
CY7C335
CY7C3381A
CY7C3382A
CY7C3383A
CY7C3384A
CY7C3385A
CY7C3386A
CY7C3387P
CY7C3388P
CY7C340 EPLD Family
CY7C341
CY7C341B
CY7C342
CY7C342B
CY7C343
CY7C343B
CY7C344
CY7C344B
CY7C346
CY7C346B
CY7C371
CY7C371i
CY7C372
CY7C372i
CY7C373
CY7C373i
CY7C374
CY7C374
CY7C375
CY7C375i
CY7C381P
CY7C382P
CY7C383A
CY7C384A
CY7C385P
CY7C386P
CY7C387P
CY7C388P
FLASH370 CPLD Family
FLASH370i
PAL22VlOC
PAL22VPlOC
PALC20 Series
PALC22VlO
PALC22VlOB
PALC22VlOD
PALCE16V8

Wmp2+ VHDL Compiler for PLDs, CPLDs, and FPGAs ............................ 5-2
Walp2 VHDL Compiler for PLDs and CPLDs ..................................... 5-6
Walp3 VHDL Development System for PLDs, CPLDs, and FPGAs .................. 5-10
ABEUSynario Design Software Kit for FLASH370 ................................. 5 -15
Walp3 PROSeries Bolt-In ..................................................... 5-16
Synopsys Design Software Kit for pASIC380 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -18
Impulse3 Device Programmer and Adapters ...................................... 5 -19
CMOS Programmable Synchronous State Machine .................... . . . . . . . . . . .. 2-68
Asynchronous Registered EPLD ............................................... 2-69
Registered Combinatorial EPLD ............................................... 2-83
Universal Synchronous EPLD .................................................. 2-84
UltraLogic 3.3V High Speed 1K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-44
UltraLogic 3.3V High Speed 1K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-44
U1traLogic 3.3V High Speed 2K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-61
UltraLogic 3.3V High Speed 2K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-61
UltraLogic 3.3V High Speed 4K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-81
UltraLogic 3.3V High Speed 4K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-81
UltraLogic Very High Speed 8K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-100
U1traLogic Very High Speed 8K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-100
Multiple Array Matrix High-Density EPLDs ..................................... 3-122
192-MacroceIlMAXEPLD ................................................... 3-140
192-MacroceIlMAXEPLD ................................................... 3-128
128-Macrocell MAX EPLDs .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-158
128-Macrocell MAX EPLDs .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-141
64-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-159
64-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-159
32-Macrocell MAX EPLD .................................................... 3-175
32-MacroceIlMAXEPLD .................................................... 3-175
128-Macrocell MAX EPLDs .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 -189
128-Macroce1lMAXEPLDs .................................................. 3-189
U1traLogic 32-Macrocell Flash CPLD ........................................... 3-15
U1traLogic 32-Macrocell Flash CPLD ........................................... 3-73
UltraLogic 64-Macrocell Flash CPLD ........................................... 3-24
UltraLogic 64-Macrocell Flash CPLD ............................................ 3-82
UltraLogic 64-Macrocell Flash CPLD ........................................... 3-33
UltraLogic 64-Macrocell Flash CPLD ........................................... 3-91
UltraLogic 128-Macrocell Flash CPLD .......................................... 3-43
UltraLogic 128-Macrocell Flash CPLD ......................................... 3 -100
UltraLogic 128-Macrocell Flash CPLD ................................ ".......... 3-54
U1traLogic 128-Macrocell Flash CPLD ......................................... 3-110
UltraLogic Very High Speed 1K Gate CMOS FPGA ............................... 4-35
U1traLogic Very High Speed 1K Gate CMOS FPGA ............................... 4-35
U1traLogic Very High Speed 2K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-52
UltraLogic Very High Speed 2K Gate CMOS FPGA ............................... 4-52
U1traLogic Very High Speed 4K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-69
U1traLogic Very High Speed 4K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-69
U1traLogic Very High Speed 8K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-90
UltraLogic Very High Speed 8K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-90
UltraLogic High-Density Flash CPLDs ........................................... 3-8
ISR CPLD Family U1traLogic High-Density Flash CPLDs .......................... 3-66
Universal PAL Device ........................................................ 2-58
Universal PAL Device ........................................................ 2-58
Reprogrammable CMOS PALC 16L8, 16R8, 16R6, 16R4 . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-6
Reprogrammable CMOS PAL Device ........................................... 2-56
Reprogrammable CMOS PAL Device ........................................... 2-57
Flash Erasable, Reprogrammable CMOS PAL Device .............................. 2-59
Flash Erasable, Reprogrammable CMOS PAL Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-7

vi

-

-.,~

Numeric Device Index
rcYPRESS ================

PALCE20V8
PALCE22VlO
pASIC380 Family
PLDC20GlO
PLDC20Gl0B
PLDC20RAlO
Ultra338003
Ultra338005
Ultra338007
Ultra338009
Ultra338012
Ultra338016
Ultra338020
Ultra38000 Family
Ultra38003
Ultra38005
Ultra38007
Ultra38009
Ultra38012
Ultra38016
Ultra38020
Ultra39000
Ultra39192
Ultra39256
Ultra39320
Ultra39384
Ultra39448
Ultra39512

Flash Erasable, Reprogrammable CMOS PAL Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-17
Flash Erasable, Reprogrammable CMOS PAL Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-46
UltraLogic Very High Speed CMOS FPGAs ...................................... 4-28
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. 2-27
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. 2-27
Reprogrammable Asynchronous CMOS Logic Device ............................. 2-35
UltraLogic Very High Speed 3K Gate 3.3V CMOS FPGA ........................... 4-6
UltraLogic Very High Speed 5K Gate 3.3V CMOS FPGA ........................... 4-8
UltraLogic Very High Speed 3.3V 7K Gate CMOS FPGA .......................... 4-19
UltraLogic Very High Speed 9K Gate 3.3V CMOS FPGA .......................... 4-21
UltraLogic Very High Speed 12K (36K) Gate 3.3V CMOS FPGA .................... 4-23
UltraLogic Very High Speed 16K Gate 3.3V CMOS FPGA ......................... 4-25
UltraLogic Very High Speed 20K Gate 3.3V CMOS FPGA ......................... 4-27
UltraLogic Very High Speed CMOS FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
UltraLogic Very High Speed 3K Gate CMOS FPGA ................................ 4-5
UltraLogic Very High Speed 5K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-7
UltraLogic Very High Speed 7K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-9
UltraLogic Very High Speed 9K Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4- 20
UltraLogic Very High Speed 12K Gate CMOS FPGA .............................. 4-22
UltraLogic Very High Speed 16K Gate CMOS FPGA .............................. 4-24
UltraLogic Very High Speed 20K Gate CMOS FPGA .............................. 4-26
UltraLogic High-Density CPLD Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
UltraLogic 192-Macrocell CPLD ................................................ 3-2
UltraLogic 256-Macrocell CPLD ................................................ 3-3
UltraLogic 320-Macrocell CPLD ................................................ 3-4
UltraLogic 384-Macrocell CPLD ................................................ 3-5
UltraLogic 448-Macrocell CPLD ................................................ 3-6
UltraLogic 512-Macrocell CPLD ................................................ 3-7

vii

GENERAL INFORMATION

II

SMALLPLDs

II
II

CPLDs

FPGAs
DEVELOPMENT SYSTEMS
QUALITY

PACKAGES

II
II
II
II

~

;;;::s

--..,...

_.,~

==;CYPRESS
Table of Contents

Table of Contents
Page Number

General Information
Cypress Semiconductor Background ......................................................................... 1-1
Ordering Information ..................................................................................... 1-4
Cypress Semiconductor Bulletin Board System (BBS) Announcement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-5
Application Notes ........................................................................................ 1-6
Product Selector Guide ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
Product line Cross Reference ............................................................................. 1-10
Military Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-14
Military Product Selector Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-15
Military Ordering Information ............................................................................. 1-17

#-.~

-.:::=r' CYPRESS
to ensure competitive advantage. Used extensively in a wide
range of applications, PLDs constitute a large and growing market. Cypress's UltraLogic product line addresses the high-density programmable logic market. UltraLogic includes the
Ultra3800 and pASIC380 families of field-programmable
gate arrays (FPGAs), the industry's fastest. It also includes high
performance complex PLDs, the FLAsH370~ family. Both of
these product families are supported by Cypress's VHDL (Very
high-speed integrated circuit Hardware Description Language)
based Wap3 N, the industry's most advanced software design
tool. Cypress pioneered the use of VHDL for PLD programming, and Wap software is a key factor in the company's overall
success in the PLD market.
Cypress is a leading provider of the industry-standard 22VlO
PLD with a wide range of products. Cypress is committed to
competing in all ranges of the PLD market, with small devices,
including the industry standard 16V8, the MAX340 EPLD line,
and the U1traLogic products. To support these products, Cypress offers one ofthe industry's broadest range of programming
tools and software for the programming of its PLDs.
Cypress provides one of the industry'S broadest ranges of CMOS
EPROMs and PROMs. Cypress owns a large share of the highspeed CMOS PROM market, and with its new cost structure, is
effectively penetrating the mainstream EPROM market with a
popular 256 Kbit EPROM, and the introduction of the world's
fastest 512K and 1 Megabit EPROMs at 25 ns.
FCT Logic products are used in bus interface and data buffering
applications in almost all digital systems. With the addition of
the FCT logic product line, Cypress now offers over 46 standard
logic and bus interface functions. The products are offered in
the second generation FCT-T format, which is pin-compatible
with the older FCT devices, but adds TTL (transistor-to-transistor logic) outputs for significantly lower ground bounce and improved system noise immunity. Cypress also offers the most
popular devices with on-chip 25-ohm termination resistors
(FCT2-T) to further lower ground bounce with no speed loss.
Included in the new product family is the CYBUS3384, a bus
switch that enables bidirectional data transfer between multiple
bus systems or between 5 volt and 3.3 volt devices. Cypress also
offers 16-bit versions of popular FCT products. This broad
product offering is produced on Cypress's high-volume, CMOS
manufacturing lines.

Cypress Semiconductor Background
Cypress Semiconductor was founded in April 1983 with the
stated goal of serving the high-performance semiconductor market. This market is served by producing the highest-performance
integrated circuits using state-of-the-art processes and circuit design. Cypress is a complete semiconductor manufacturer, performing its own process development, circuit design, wafer fabrication, assembly, and test. The company went public in May
1986 and has been listed on the New York Stock Exchange since
October 1988.
The initial semiconductor process, a CMOS process employing
1.2-micron geometries, was introduced in March 1984. This process is used in the manufacturing of Static RAMs and Logic circuits. In the third quarter of 1984, a 1.2-micron CMOS EPROM
process was introduced for the production of programmable
products. At the time of introduction, these processes were the
most advanced production processes in the industry. Following
the 1.2-micron processes, a O.8-micron CMOS SRAM process
was implemented in the first quarter of 1986, and a O.8-micron
EPROM process in the third quarter of 1987.
In keeping with the strategy of serving the high-performance
markets with state-of-the-art integrated circuits, Cypress introduced two new processes in 1989. These were a bipolar submicron process, targeted for ECL circuits, and a BiCMOS process
to be used for most types of TTL and ECL circuits.
The circuit design technology used by Cypress is also state of the
art. This design technology, along with advanced process technology, allows Cypress to introduce the fastest, highest-performance circuits in the industry. Cypress's offers products in four
divisions: the Static Memory Division, the Programmable Products Division, the Computation Products Division, and the Data
Communications Division.

N

N

Static Memories Division
Cypress is a market-leading supplier of SRAMs, providing a
wide range of SRAM memories for leading companies worldwide. SRAMs are used in high-performance personal computers, workstations, telecommunications systems, industrial systems, instrumentation devices, and networking products.
Cypress's lower production cost structure allows the company to
compete effectively in the high-volume personal computer and
workstation market for SRAMs, including providing cache
RAMs to support today's high-performance microprocessors,
This business, combined
such as Pentium ~ , and PowerPC
with upcoming low-voltage products for the cellular communications, portable instrument, and laptop/notebook PC markets,
positions Cypress for future success in this key product area.
Multichip modules is a fast-growing market segment that consists of multiple semiconductor chips mounted in packages that
can be inserted in a computer circuit board. Cache modules for
personal computers are the mainstay of this product line, and
Cypress has announced major design wins for these products in
IBM's PSNaluePoint line of PCs, and in Apple Computer's
highest performing Power Macintosh products.
N

N

Data Communications Division
This is an especially significant area for Cypress since it represents a more market-driven orientation for the company in a
fast-growing market segment. As part of the new company strategy, Cypress has dedicated this product line to serve the highspeed data communications market with a range of products
from the physical connection layer to system-level solutions.
HOTLink ~, high-speed, point-to-point serial communications
chips have been well received. HOTLink, along with the recently announced SONET./SDS Serial1tansceiver (SST ~), address
the fast-growing market segments of Asynchronous 1tansfer
Mode (ATM) and Fibre Channel communications. The company has also entered the Ethernet market with the 100BaseT-4
CY7C971 Fast Ethernet Transceiver and the CY7B8392 Coax
Ethernet 1tansceiver. The data communications division encompasses related products including RoboClock, a programmable skew clock buffer that adjusts complex timing control signals for a broad range of systems. The division also offers a
broad range of First-In, First-Out (FIFO) memories, used to
communicate data between systems operating at different fre-

•

N

N

Programmable Products Division
With increasing pressure on system designers to bring products
to market more quickly, programmable logic devices (PLDs) are
becoming extremely popular. PLDs are logic control devices
that can be easily programmed by engineers in the field, and later erased and reprogrammed. This allows the designers to make
key changes to their systems very late in the development cycle

1-1

II

=:"rcYPRESS
quencies, and Dual-Port Memories, used to distribute data to
two different systems simultaneously.
Computation Products Division
This division focuses on the high-volume, high-growth market
surrounding the desktop computer. It is the second of Cypress's
market-oriented divisions. The division includes timing technolo~ products o~ered through Cypress's IC Designs Subsidiary in
Kirkland, Washmgton. IC Designs products are used widely in
personal computers and disk drives, and the product line provides Cypress with major inroads into these markets, helping
move the company towards a more market-driven orientation.
IC Designs clock oscillators control the intricate timing of all aspects of a computer system, including signals for the computer's
central processing unit (CPU), keyboard, disk drives, system bus
serial port, and real-time clock. They replace all of the metal ca~
oscillators used in the system. IC Designs recently announced a
new product, QuiXTAL m , which is a programmable metal can
oscillator, and replaces individual oscillators used to control timing. signals in virtually every type of electronics equipment.
QUiXTAL can be programmed to any frequency, providing users
t~e ability to make I.ast-minute frequency adjustments, speeding
time to market. QuiXTAL takes frequency synthesis beyond the
PC market, and addresses the broad market segments of electronic instrumentation, telecommunications equipment and
medical systems.
'

Th improve global competitiveness, Cypress chose to move most
bac~-end assembly, test, and mark operations to a facility in
ThaIland. Be assured that Cypress's total quality commitment
extends to the new site--Cypress Bangkok.
The move to Bangkok consummated an intense search by Cypress for a world-class, environmentally sophisticated facility
that we could bring on line quickly. The Cypress search team
scrutinized fIfteen manufacturing facilities in five countries and
chose a site managed by Alphatec Electronics Co., Ltd., a privately owned, entrepreneurial company promoted by the Thailand Board of Investment. Cypress Bangkok occupies almost
25,000 square feet-a significant portion of the manufacturing
floor space available within the facility. The full facility at Bangkok occupies more than 85,000 square feet on a site that encompasses 25 acres-sufficient room for expansion to a number of
buildings in a campus-like setting. In order to meet growiug demand for its products, Cypress has broken ground on a new assembly and test facility in the Philippines, which is scheduled for
completion in 1996.
Cypress San Jose maintains complete management control of all
~sembly, test, mark, and ship operations worldwide, thus assurmg complete continuity of back-end operations and quality.

Also offered by this division are chipsets for personal computers.
~ress entered this market with the 1994 acquisition of Contaq
Mlcrosystems, and recently announced the hyperCache m Chipset for Pentium m -class PCS. The hyperCache Chipset is the industry's most highly integrated. In addition to integrating keyboard and mouse control, real-time clock, and local-bus IDE
control, it is the only chipset which offers integrated second-level
cache.

Cypress ~as added Thpe Automated Bonding (TAB) to its packa~e offenng. TAB, a surface-mount packaging technology, proVIdes the densest lead and package footprint available for fully
tested die.
From Cypress's facility in Minnesota, a VME Bus Interface
Products group has been in operation since the acquisition of
VTC's fab in 1990. Cypress manufactures VIC and VAC VME
devices on the 0.8 micron CMOS process.
The Cypress motto has always been "only the best-the best facilities, the best equipment, the best employees ... all striving to
make the best CMOS and BiCMOS products."

Cypress Facilities

Cypress Process Technology

Cypress operates wafer fabrication facilities in California's Silicon Valley (San Jose), Round Rock (Austin), Texas, and Bloomington, Minnesota. The company's fourth wafer fab, located adjacent to the Bloomington, Minnesota facility, went on-line in
July 1995. There are additional Cypress Design Centers in
Starkville, Mississippi, Colorado Springs, Colorado and the
United Kingdom, and a PLD software design group i~ Beaverton, C?regon. The facilities are designed to the most demanding
techmcal and environmental specifications in the industry. At the
Texas and Minnesota facilities, the entire wafer fabrication area
is specified to be a Gass 1 environment. This means that the ambient air has less than 1 particle of greater than 0.2 microns in
diameter per cubic foot of air. Other environmental considerations are carefully insured: temperature is controlled to a ±0.1
degree Fahrenheit tolerance; filtered air is completely exchanged
more than 10 times each minute throughout the fab; and critical
equipment is situated on isolated slabs to minimize vibration.
The company has also received IS09000 registration, a standard
model of quality assurance that is awarded to companies with exa.cting standards of quality management, production, and inspectIOnS.
Attention to assembly is equally critical. Cypress manufactures
100 percent of its wafers in the United States, at the front-end
fabrication sites in California (San Jose), Minnesota (Bloomington), and Thxas (Round Rock). Cypress Thxas, the company's
largest fab, and Cypress Minnesota's fabs, are all Class 1 facilities.

In the last decade, there has been a tremendous need for highperformance semiconductor products manufactured with a ba1ance of SPEED, RELIABILITY, and POWER. Cypress Semiconductor overcame the classically held perceptions that CMOS
was a moderate-performance technology.
Cypress initially introduced a 1.2-micron "N" well technology
with double-layer poly and a single-layer metal. The process
employed lightly doped extensions of the heavily doped source
and drain regions for both "N" and "P" channel transistors for
significant improvement in gate delays. Further improvements in
performance, through the use of substrate bias techniques, have
added the benefit of eliminating the input and output latch-up
characteristics associated with older CMOS technologies.
Cypress pushed process development to new limits in the areas
of PROMs (Programmable Read Only Memory) and EPLDs
(Erasable Programmable Logic Devices). Both PROMs and
EPLDs have existed since the early 1970s in a bipolar process
that employed various fuse technologies and was the only viable
high-speed nonvolatile process available. Cypress PROMs and
EPLDs use EPROM technology, which has been in use in MOS
(Metal Oxide Silicon) since the early 1970s. EPROM technology
has traditionally emphasized density while forsaking perform~ce. Through Improved technology, Cypress produced the first
high-performance CMOS PROMs and EPLDs, replacing their
bipolar counterparts.
To m~tain our leadersh!p position in CMOS technology, Cypress mtroduced a sub-mIcron technology in 1987. This 0.8 mi-

1-2

cron breakthrough made Cypress's CMOS one of the most advanced production processes in the world. The drive to maintain
leadership in process technology has not stopped with the
0.8-micron devices. Cypress introduced a 0.65-micron process in
1991. A 0.5-micron process is currently in production.
Although not a requirement in the high-performance arena,
CMOS technology substantially reduces the power consumption
for any device. This improves reliability by allowing the device to
operate at a lower die temperature. Now higher levels of integration are possible without trading performance for power. For instance, devices may now be delivered in plastic packages without
any impact on reliability.
While addressing the performance issues of CMOS technology,
Cypress has not ignored the quality and reliability aspects of
technology development. Rather, the traditional failure mechanisms of electrostatic discharge (ESD) and latch-up have been
addressed and solved through process and design technology innovation.
ESD-induced failure has been a generic problem for many highperformance MOS and bipolar products. Although in its earliest
years, MOS technology experienced oxide reliability failures, this
problem has largely been eliminated through improved oxide

growth techniques and a better understanding of the ESD problem. The effort to adequately protect against ESD failures is perturbed by circuit delays associated with ESD protection circuits.
Focusing on these constraints, Cypress has developed ESD protection circuitry specific to 1.2-, 0.8-, 0.65-, and O.5-micron
CMOS process technology. Cypress products are designed to
withstand voltage and energy levels in excess of 2001 volts and
0.4 miIIi-joules.
Latch-Up, a traditional problem with CMOS technologies, has
been eliminated through the use of substrate bias generation
techniques, the elimination of the "P" MOS pull-ups in the output drivers, the use of guardring structures anrl care in the physical layout of the products.
Cypress has also developed additional process innovations and
enhancements: multilayer metal interconnections, advanced
metal deposition techniques, silicides, exclusive use of plasma for
etching, and 100-percent stepper technology with the world's
most advanced equipment.
Cypress technologies have been carefully designed, creating
products that are "only the best" in high-speed, excellent reliability, and low power.

UltraLogic, Ultra3800, FLAsH370, Wwp3, HOTLink, SST, and hyperCache are trademarks of Cypress Semiconductor Corporation.
pASIC is a trademark of QuickLogic.
Pentium is a trademark of Intel Corporation.
Power PC and PSNalue Point are trademarks of International Business Machines Corporation.
Power Macintosh is a trademark of Apple.
MAX is a trademark of Altera.

1-3

II

#fL~YPRESS~==================o=r=d=er=i=ng~In=fI=o=nn==a=ti=o~n
In general, the ordering codes for products follow the format below; e.g., CY7C128-45DMB, PALC16R8L-35PC
PAL & PLD
PREFIX DEVICE
IpALC I I 16R8 I
PALC
16R8
PALC
22VI0
PALCE
16V8
PLDC
20GlO
CY
7C330

SUFFIX
-25LMB I

L:~~gl
-25P C
-25WC
-33P C

[

FAMILY
PAL 20
LOW POWER PAL 20
PAL 24 VARIABLE PRODUcr TERMS
FLASH-ERASABLE PAL20
GENERIC PLD 24
PLD SYNCHRONOUS STATE MACHINE
PROCESSING
B = MIL-STD-883C FOR MILITARY PRODUcr
= LEVEL 2 PROCESSING FOR COMMERCIAL PRODUcr
T = SURFACE-MOUNTED DEVICES TO BE TAPE AND REELED
R = LEVEL 2 PROCESSING ON TAPE AND REELED DEVICES
TEMPERATURE RANGE
C = COMMERCIAL (O°C TO +70°C)
I = INDUSTRIAL (-40°C TO +85°C)
M = MILITARY (-55°C TO + 125°C)
PACKAGE
B
D
E
F

G
H
J
K
L
N
P
Q
R
S
T
U
V
W=
X =

Y
Z

=
=

HD=
HV=
PF =
PS =
PZ=
BG=

PLASTIC PIN GRID ARRAY (PPGA)
CERAMIC DUAL IN-UNE PACKAGE (CERDIP)/BRAZED DIP
TAPE AUTOMATED BONDING (TAB)
FLATPACK (SOLDER-SEALED FiAT PACKAGE)
PIN GRID ARRAY (PGA)
WINDOWED LEADED CHIP CARRmR
PLASTIC LEADED CHIP CARRIER (PLCC)
CERPACK (GLASS-SEALED FLAT PACKAGE)
LEADLESS CHIP CARRmR (LCC)
PLASTIC QUAD FLATPACK (PQFP)
PLASTIC DUAL IN-LINE (PDIP)
WINDOWED LEADLESS CHIP CARRmR (LCC)
WINDOWED PIN GRID ARRAY (PGA)
SOIC (GULL WING)
WINDOWED CERPACK
CERAMIC QUAD FLATPACK (CQFP)
SOIC (J LEAD)
WINDOWED CERAMIC DUAL IN-UNE PACKAGE (CERDIP)
DICE (WAFFLE PACK)
CERAMIC LEADED CHIP CARRmR
TSTOP
HERMETIC DIP (MODULE)
HERMETIC VERtICAL DIP
PLASTIC FLAT SIP
PLASTIC SIP
PLASTIC ZIP
BALL GRID ARRAY

SPEED (ns or MHz)
L = LOW-POWER OPTION
A, B, C, D, G, CF = REVISION LEVEL

Cypress FSCM #65786

1-4

.-=.

-

-.,~

,CYPRESS================================
Cypress Semiconductor Bulletin Board System (BBS) Announcement

Cypress Semiconductor supports a 24-hour electronic Bulletin Board System (BBS) that allows Cypress
Applications to better serve our customers by allowing them to transfer files to and from the BBS.
The BBS is set up to serve in multiple ways. One of its purposes is to allow customers to receive the most
recent versions of Cypress programming software. Another is to allow the customers to send PLD programming files that they are having trouble with to the BBS. Cypress Applications can then find the errors in the
files, correct them, and place them back on the BBS for the customer to download. The customer may also
ask questions in our open forum message area. The sysop (system operator) will forward these questions to
the appropriate applications engineer for an answer. The answers then get posted back into the forum.
Communications Set-Up
The BBS uses US Robotics HST Dual Standard modems capable of 14.4-Kbaud rates without compression
and rates upwards of 19.2-Kbaud with compression. It is compatible with CCITT V.32 bis, V.32, V.22
(2400-baud), Bell 212A (1200-baud), CCITT V.42, and CCITT V.42 bis. It also handles MNP levels 2, 3, 4,
and 5.

To call the BBS, set your communication package parameters as follows:
Baud Rate:

1200 baud to 19.2 Kbaud. Max. is determined by your modem.
Data Bits: 8
Parity: None (N)
Stop Bits: 1

In the U.S. the phone number for the BBS is (408) 943-2954. In Japan the BBS number is
81-423-69-8220. In Europe the BBS number is 49-810-62-2675. These numbers are for transmitting
data only.
If the line is busy, please retry at a later time. When you access the BBS, an initial screen with the following

statement will appear:
Rybbs Bulletin Board

After you choose the graphics format you want to use, the system will ask for your first and last name. If you
are a first-time user, you will be asked a few questions for the purposes of registration. Otherwise you will be
asked for your password, and then you will be logged onto the BBS, which is completely menu driven.
Downloading Application Notes and Datasheets
A complete listing of files that may be downloaded is included on the BBS. Application notes are available
for downloading in two formats, PCL and Postscript ™. An "hp" in front of the file name indicates it is a PCL
file and can be downloaded to Hewlett-Packard LaserJets™ and compatible printers. Files without the hp
preceding them are in Postscript and can be downloaded to any Postscript printer.
If you have any problems or questions regarding the BBS, please contact Cypress Applications at (408)

943-2821 (voice).
Postscript is a trademark of Adobe Corporation.
LaserJet is a trademark of Hewlett Packard Corporation.

1-5

II

#~

Application Notes

~;CYPRESS
Contact a Cypress representative to get copies of the application notes listed here.

ABEL 4.0/4.1 and the CY7C330, CY7C331, and CY7C332
Abel- HDL vs. IEEE-1076 VHDL
Architectures and Thchnologies for FPGAs
Are Your PLDs Metastable?
Bus-Oriented Maskable Interrupt Controller
CMOS PAL Basics
CPLD Arithmetic
CY7C331 Asynchronous Self-Timed VMEbus Requestor
CY7C344 as a Second-Level Cache Controller for the 80486
CY7C380 Family Quick Power Calculator
Describing State Machines with Warp2 VHDL
Design Considerations For On-Board Programming of the 7C374 and7C375
Design Tips for Advanced Max Users
Designing a Multiprocessor Interrupt Distribution Unit with MAX
Designing with the CY7C335 and Warp2 VHDL Compiler
Designing with FPGAs
DMA Control Using the CY7C342 MAX EPill
The FLAsH370 Family of CPills and Designing with Warp2
FPGA Design Entry Using Warp3
Implementing a Reframe Controller for the CY7B933 HOTLink Receiver in a CY7C371 CPill
Implementing a 128Kx8 Dual-Port Using FLAsH370
FIFO RAM Controller with Programmable Flags
Getting Started Converting .ABL Files to VHDL
Interfacing PROMs and RAMs to DSP Using Cypress MAX Products
Mentor Simulation with Cypress PLDs
PAL Design Example: A GCR EncoderlDecoder
pASIC380 Power vs. Operating Frequency
PCI Bus Applications on FPGAs
PLD-Based Data Path for SCSI-2
State Machine Design Considerations and Methodologies
1'2 Framing Circuitry
Thp·Down Design Methodology with VHDL
Using ABEL to Program the Cypress 22VlO
Using CUPL with Cypress PLDs
Using Hierarchical VHDL Design
Using LoglIC to Program the CY7C330
Using Scan Mode on pASIC380 for In-Circuit Testing
Using Synopsys/Exemplar
Using the CY7C331 as a Waveform Generator
VHDL Techniques for Optimal Design Fitting
Describing State Machines with Warp2
Glossary - '93
Glossary - '94

1-6

Product Selector Guide

=:'?cYPRESS
PLDs
tpD(ns)

f(MHz)

IcC(mA)

Pins

PALCI6L8
PALCI6L8L

20
25

70
45

20
20

D,L,P'Q,V,W
D,L,P,Q,V,W
D,L,P,Q,V,W

Part Number

Packages

PALC16R4

20

28.5
28.5
28,5

70

20

PALC16R4L

25

28.5

45

20

D,L,P'Q, YoW

PALC16R6

20

28.5

70

20

D,L,P,Q, YoW

PALC16R6L

25

28.5

45

20

D,L,P'Q, YoW

PALC16R8

20

28.5

70

20

D,L,P'Q,V,W

PALC16R8L

25

28.5

45

20

D,L,P,Q, YoW

PALCE16V8

5

142.8

115

20

D,J,L,P

PALCE16V8

10

69

90

20

D,J,L,P

PALCEI6V8L

15

45.5

55

20

D,J,L,P'QSOP

PLDC20GI0

25

33.3

55

24/28

D,J,L,p,W

PLDC20GI0B

15

45.5

70

24/28

D,J,L,p,W

PLD20RAI0

15

45.5

75

24/28

D,H,J,L,p,W

PALCE20V8

5

142.8

115

24/28

D,J,L,P

PALCE20V8

10

58.8

90

24/28

D,J,L,P

PALCE20V8L

15

45.5

55

24/28

D,J,L,P,QSOP

PALC22VlO*

20

41.7

90

24/28

D,J,L,P,Q,W

PALC22VlOL*

25

33.3

55

24/28

D,J,L,P,Q,W

PALC22VlOB*

15

50

90

24/28

D,H,J,L,P,Q, W

PALC22VIOD

7.5

100

130

24/28

D,J,L,P

PALC22VlOD

10

76.9

90

24/28

D,J,L,P

PALCE22VI0

5

142.8

115

24/28

D,J,L,P

PALCE22VlO

IS

50

90

24

D,J,L,P

CY7C331
CY7C335

20
15

35
50

130
140

28
28

D,J,H,P,Q,W
D,J,H,p,W

* Not recommended for new designs.

CPLDs
Flash370'"
Organization

Pins

Part Number

32-Macrocell Flash CPLD
32-MacrocellFlash CPLD Low Power

44
44

CY7C371
CY7C371L

64-MacroceIlFlash CPLD

44,84,100

64-MacrocellFlash CPLD Low Power

44,84,100

128-Macrocell Flash CPLD

Speed (ns)

Icc

(rnA)

Packages

fMAXIts/teo = 143 MHz/5 ns/6 ns
fMAXIts/teo=83 MHz/6.5 ns/6.5 ns

175
90

A,J,Y
A,J

CY7C372/3

fMAX/tS/teo= 100 MHz/6.5 ns/6.5 ns

250

A,G,J,Y

CY7C372L/3L

fMAXltsiteo = 100 MHz/6.5 ns/6.5 ns

125

A,G,J,Y

84,100,160

CY7C374/5

fMAX/tsiteo = 100 MHz/7 nsn ns

300

A,G,J,V,Y

128-Macrocell Flash CPLD Low Power

84,100,160

CY7C374L/5L

fMAX/tsiteo = 100 MHz/7 nsn ns

ISO

A,G,J,V,Y

32-Macrocell ISR Flash CPLD

44

CY7C371i

fMAXltsiteo = 143 MHzJ5 ns/6 ns

175

A,J,Y
A,J

32-Macrocell ISRFlash CPLD Low Power

44

CY7C37i1L

fMAXltsiteo = 83 MHz/6.5 ns/6.5 ns

90

64-Macrocell ISR Flash CPLD

44,84,100

CY7C372i/3i

fMAXltsiteo = 100 MHz/6.5 ns/6.5 ns

250

A,G,J,Y

64-Macrocell ISRFlash CPLD Low Power

44,84,100

CY7C372iL/3iL

fMAXltsiteo = 100 MHz/6.5 ns/6.5 ns

125

A,G,J,Y

128-Macrocell ISRFlash CPLD
128-Macrocell ISRFlash CPLD Low Power

84,100,160
84,100,160

CY7C374i/5i
CY7C374iL/5iL

fMAXltsitco = 100 MHz/7 nsn ns
fMAXlts/teo = lOOMHznnsnns

300
ISO

A,G,J,V,Y
A,G,J,V,Y

1-7

III

Product Selector Guide
CPLDs (continued)
Ultra39000'"
Icc

Organization

Pins

CY7C39192
CY7C39256

208,240

240
240,304
304

CY7C39448
CY7C39512

192-MacroccllF1ashISRCPLD
256-Macroccll F1ash ISR CPLD

84,160
160,208

320-Macrocell F1ash ISR CPLD
384-Macroccll F1ash 1SR CPLD
448-Macroccll F1ash 1SR CPLD
512-MacroccllF1ash ISR CPLD

(rnA)

Speed (ns)

Part Nomber

Packages

fMAX/tpD/ts/tCO= 125 MHz/10ns/5 ns/5.5 ns
fMAX/tpD/tS/tco= 125 MHz/lO ns/5 ns/5.5 ns

TBD
TBD

A,J
A,N

CY7C39320

fMAX/tpD/ts/tCO= 125 MHz/10ns/5 ns/5.5 ns

TBD

N

CY7C39384

fMAX/tPD/ts/tco=lOOMHz/12ns/6ns/6.5ns

TBD

N

fMAX/tpD/ts/tCO= 100 MHz/12 ns/6 ns/6.5 ris
fMAX/tpo/ts/tco= 100 MHz/12 ns/6 ns/6.5 ns

TBD
TBD

N
N

MAX340'"
Organization

Pins

32MacrocellCPLD
64 Macrocell CPLD

28S
44

128 Macrocell CPLD
128 Macroccll CPLD
192 Macrocell CPLD

Part Number

Speed (ns)

IccfJSB
(rnA)

Packages

CY7C344/B
CY7C343/B

tPDIS/CO = 15/lO/lO, lO/6/5
tPDIS/CO = 20/12/12, 12/8/6

200/150
135/125

H,J,p,W
H,J,R

68

CY7C342/B

!PDIS/CO = 25/15/14, 12/8/6

250/225

H,J,R

84,100
84

CY7C346/B
CY7C341/B

tPD/S/CO = 25/15/14, 15/10/7
tPDIS/CO = 25/15/14, 15/10/7

250/225
380/360

H,J,N,R
H,J,R

FPGAs
pASIC380'"
ICcfJSB
Organization

Pins

Part Number

Speed Grade

(rnA)

Packages

CY7C381N2A

-X,-O,-1,-2

1SB= 10

A,G,J

44,68,100

CY7C3381A!2A

-X,-0,-1

ISB=0.65

A,J

68,84,100

CY7C383N4A

-X,-0,-1,-2

ISB= 10

A,G,J

3.3V CMOS 2K Gates FPGA

68,84,100

CY7C3383N4A

-X,-0,-1

ISB = 0.65

A,J

CMOS 4KGates FPGA

84,100,144,160

CY7C385N6A

-X,-0,-1, -2

ISB= 10

A,G,J,U

3.3V CMOS 4K Gates FPGA

84,100,144

CY7C3385N6A

-X,-O,-l

ISB=0.65

A,J

CMOS 8KGates FPGA

144,160,208,223

CY7C387N8A

-X,-0,-1,-2

ISB= 10

A,G,N,U

3.3V CMOS 8KGates FPGA

144,208

CY7C3387N8A

-X,-O,-1

ISB = 0.65

A,N

CMOS1KGatesFPGA

44,68,100

3.3VCMOS1KGatesFPGA
CMOS2KGatesFPGA

Ultra3800'"
Organization

Pins

Part Nnmber

Speed Grade

ICcfJSB
(rnA)

Packages

CMOS3KGatesFPGA

84,144

CY7C3803

-X,-O, -1,-2

ISB= 10

A,J

3.3V CMOS 3K Gates FPGA

84,144

CY7C33803

-X,-0,-1,-2

ISB = 0.65

A,J

CMOS5KGatesFPGA

84,144,208

CY7C3805

-X,-0,-1,-2

ISB= lO

A,J,N

3.3V CMOS 5K Gates FPGA

84,144,208

CY7C33805

-X,-0,-I,-2

18B=0.65

A,J,N

CMOS7KGatesFPGA

144,208,256

CY7C3807

-X, -0,-1,-2

ISB= 10

A, N,BGA

3.3VCMOS7KGatesFPGA

144,208,256

CY7C33807

-X,-0,-1,-2

ISB=0.65

A, N, BGA

CMOS9KGatesFPGA

144,208,256

CY7C3809

-X,-0,-1,-2

ISB= 10

A, N, BGA

3.3V CMOS 9K Gates FPGA

144,208,256

CY7C33809

-X,-0,-1,-2

18B=0.65

A,N,BGA

CMOS 12KGatesFPGA

208,352

CY7C3812

-X,-0,-1,-2

ISB= 10

N,BGA

3.3V CMOS 12K Gates FPGA

208,352

CY7C33812

-X,-0,-1,-2

ISB=0.65

N,BGA

CMOS 16K Gates FPGA

208,352

CY7C3816

-X,-0,-1,-2

ISB= 10

N,BGA

3.3VCMOS 16K Gates FPGA

208,352

CY7C33816

-X,-0,-1,-2

18B=0.65

N,BGA

CMOS20KGatesFPGA

208,352

CY7C3820

-X,-0,-1, -2

ISB= 10

N,BGA

3.3V CMOS 20K Gates FPGA

208,352

CY7C33820

-X,-0,-1,-2

18B=0.65

N,BGA

1-8

Product Selector Guide

#it ?cYPRESS
Design and Programming Tools
1YJIe

Description

Part Number

Wa1p2 + ~ forPC
Wa1p2~ forPC

VHDLDesignThol

CY3120

VHDLDesignThol

CY3121

Wa1p2 + for Sun

VHDLDesignThoI

CY3125

Wa1p2 for Sun

VHDL Design Tool

CY3126

Wa1p3~

VHDL/CAE Design Tool

CY3130

Wa1p3 for Sun

VHDL/CAE Design Tool

CY3135

Abel '" Kit for PC

FLASH370 Design Kit

CY3140

forPC

PROseries N for PC

Viewlogic N Design Kit

CY3141

Abel KitforSUN

FLASH370 Design Kit

CY3145

Synopsys ~ for Sun

pASIC380 Design Kit
Programmer

CY3146

Impulse3~

II

CY3500

Notes:
The above specifications are for the commercial temperature range of 0 0 C to 70 0 C. Military temperature range ( - 55 0 C to +125 0 C) product processed
to MIL-STD-883 Revision C is also available for most products. Speed and power selections may vary from those above. Contact your local sales office

for more information.
Commercial grade product is available in plastic, CERDIp, or LCe. Military grade product is available in CERDlp, LCC, or PGA.
Power supplies for most product lines are Vee = 5V ± 10%.
22S, 24S, 28S stands for 300 mil. 22-pin, 24-pin, 28-pin, respectively. 28.4 stands for 28-pin 400 mil, 24.4 stands for 24-pin 400 mil.
PLCC, SOJ, and SOIC packages are available on some products.
F, K, and T packages are special order only.
Please contact a Cypress representative for product availability.
MAX and MAX + PLUS are registered trademarks of Altera Corporation. Pentium is a trademark of Intel Corporation.

Package Code:
B = Plastic Pin Grid Array
D = CerDIP
E = Thpe Automated Bond (TAB)
F = Flatpack
G = Pin Grid Array (PGA)
H = Windowed Hermetic LeC
J = PLCC
K = Cerpack
L = Leadless Chip Carrier (LCC)
N = Plastic Quad Flatpack
P = Plastic

Q
Q
R
S
T
U
V
W
X
Y
Z

= Windowed LeC
QSOP

=

= Windowed PGA
= SOIC
= Windowed Cerpack
= Ceramic Quad Flatpack
= SOJ
= Windowed Cerdip
= DICE
= Ceramic LCC
= TSOP

HD
HG
PA
PD
PM
PN
PS
PV
PZ
SO

= Hermetic DIP (Module)
= CeramicPGA(Module)
= TSSOP
= Plastic DIP (Module)
= Plastic SIMM
= Plastic Angled SIMM
= Plastic SIP
= SSOP
= Plastic ZIP
= SOIC

Wa1p2, Wa1p2+, Wa1p3, Ultra3800, Ultra39000, and Impulse3 are trademarks of Cypress Semiconductor Corporation.
Abel is a trademark of Data I/O.
Proseries and ViewLogic are trademarks of ViewLogic.
Synopsys is a trademark of Synopsis.

1-9

Product Line Cross Reference
CYPRESS
PALCI6L8-25C
PALCI6L8-30M
PALCI6L8-35C
PALCI6L8-40M
PALCI6L8L-35C
PALC16R4-25C
PALC16R4-30M
PALC16R4-35C
PALC16R4-40M
PALCI6R4L-35C
PALC16R6-25C
PALC16R6-30M
PALCI6R6-35C
PALC16R6-40M
PALC16R6L-35C
PALCI6R8-25C
PALCI6R8-30M
PALC16R8-35C
PALC16R8-40M
PALC16R8L-35C
PALC22VlO- 35C
PALC22VlO-40M
PALC22VlOL- 25C
PALC22VlOL-35C
PLDC20GlO-35C
PLOC20GlO-40M

CYPRESS
PALCI6L8L-25C
PALCI6L8-20M
PALCI6L8-25C
PALCI6L8-30M
PALCI6L8L-25C
PALCI6R4L-25C
PALCI6R4-20M
PALCI6R4-25C
PALC16R4-30M
PALCI6R4L-25C
PALC16R6L-25C
PALC16R6-20M
PALCI6R6-25C
PALC16R6-30M
PALC16R6L-25C
PALCI6R8L-25C
PALCI6R8-20M
PALC16R8-25C
PALC16R8-30M
PALC16R8L-25C
PALC22VlO-25C
PALC22VlO-30M
PALC22VlO- 25C
PALC22VlOL-25C
PLDC20GlO-25C
PLDC20GlO-30M

ALTERA
PREFIX:EPM
50320C
50320C-2
50320C-15
50320C-17
50320C-20
50320C-25
50320M
50320M-25
50321C
50321C-2
50321C-15
50321C-17
50321C-20
50321C-25
503211-20
50321M
50321M-25
5032LC
5032LC-2
5032LC-15
5032LC-17
5032LC-20
5032LC-25
5032PC
5032PC-2
5032PC-15
5032PC-17
5032PC-20
5032PC-25
5064JC
5064JC-l
5064JC-2
5064JI

CYPRESS
PREFIX:CY
7C344-25WC
7C344-20WC
7C344-15WC
Call Factory
7C344-20WC
7C344-25WC
7C344-25WMB
7C344-25WMB
7C344-25HC
7C344-20HC
7C344-15HC
Call Factory
7C344-20HC
7C344-25HC
7C344-20HI
7C344-25HMB
7C344-25HMB
7C344-25JC
7C344-20JC
7C344-15JC
Call Factory
7C344-2OJC
7C344-25JC
7C344-25PC
7C344-20PC
7C344-15PC
Call Factory
7C344-20PC
7C344-25PC
7C343-35HC
7C343-25HC
7C343-30HC
7C343-35HI

ALTERA
5064JM
5064LC
5064LC-l
5064LC-2
5128AGC-1
5128AGC-2
5128AGC-3
5128AJC-l
5128AJC-2
5128AJC-3
5128ALC-1
5128ALC-2
5128ALC-3
5128GC
5128GC-l
5128GC-2
5128GM
5128JC
5128JC-l
5128JC-2
5128JI
5128JI-2
5128JM
5128LC
5128LC-1
5128LC-2

5128U
5128U-2
5130GC
5130GC-l
5130GC-2
5130GM
5130JC
513OJC-1
5130JC-2
5130JM
5130LC
5130LC-l
5130LC-2
5130U
5130U-2
5130QC
5130QC-1
5130QC-2
5130QI
5192AGC-1
5192AGC-2
5192AJC-l
5192AJC-2
5192ALC-l
5192ALC-2
5192GC
5192GC-l
5192GC-2
51921C
51921C-1
51921C-2
519211
5192LC
5192LC-l
5192LC-2

CYPRESS
7C343-35HMB
7C343-35JC
7C343-25JC
7C343-3OJC
7C342B-12RC
7C342B-15RC
7C342B-20RC
7C342B-12HC
7C342B-15HC
7C342B-20HC
7C342B-121C
7C342B-15JC
7C342B-20JC
7C342-35RC
7C342-25RC
7C342-30RC
7C342-35RMB
7C342-35HC
7C342-25HC
7C342-30HC
7C342-35HI
7C342-30HI
7C342-35HMB
7C342-35JC
7C342-25JC
7C342-30JC
7C342-35JI
7C342-30HI
7C346-35RC
7C346-25RC
7C346-30RC
7C346-35RM
7C346-35HC
7C346-25HC
7C346-30HC
7C346-35HM
7C346-35JC
7C346-25JC
7C346-30JC
7C346-35JI
7C346-30JI
7C346-35NC
7C346-25NC
7C346-30NC
7C346-35NI
7C34IB-15RC
7C34IB-20RC
7C34IB-15HC
7C341B-20HC
7C341B-15JC
7C43IB-20JC
7C341-35RC
7C341-25RC
7C341-30RC
7C341-35HC
7C341-25HC
7C341-30HC
7C341-35HI
7C341-35JC
7C341-25JC
7C341-30JC

AMD
SMDPN
5962-851550lRX
5962-85155012X
5962-85155 02RX
5962-85155022X
5962-8515503RX
5962-85155032X
5962-8515504RX
5962-85155042X
5962-8515505RX
5962-85155052X
5962-8515506RX
5962-85155062X
5962-8515507RX
5962-85155072X
5962-8515508RX
5962-85155082X
5962-8605301LA
5962-86053013A
5962-86053 01KA
5962-8605302LA
5962-86053 023A
5962-8605302KA
5962-8605304LA
5962-86053043A
5962-8605304KA
5962-86053 053A
5962-8605305KA
5962-8605305LA
5962-885150lRX
5962-88515012X
5962-8851502RX
5962-88515022X
5962-8851503RX
5962-88515032X
5962-8851504RX
5962-88515042X
PREFIX:Am
PREFIX:SN
SUFFIX:B
SUFFIX:O
SUFFIX:F
SUFFIX:L
SUFFIX:P
MACHllO-121C
MACHllO-15JC
MACHllO-20JC
MACHllO-20/BXA
MACH130-15JC
MACHI30-20JC
MACHI30-20/BXA
MACH2lO-12JC
MACH2lO-15JC
MACH210-20JC
MACH210-2O/BXA
MACH210A -lOJC
MACH210A-121C
MACH230-15JC
MACH230-20JC
MACH435 -15JC
MACH435-2OJC
PALI6L8A-4C

Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
* = meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
t
SOIConly
:j: = 32-pin LCC crosses to the 7C198M

1-10

CYPRESS
SMDPN
5962-8871309RX
5962-88713 09XX
5962-88713 lORX
5962-88713 lOXX
5962-88713 llRX
5962-88713 llXX
5962-88713 12RX
5962-88713 12XX
5962-8871309RX
5962-8871309XX
5962-88713 lORX
5962-88713 lOXX
5962-8871311RX
5962-88713 llXX
5962-8871312RX
5962-88713 12XX
5962-89841 OlLX
5962-89841013X
5962-89841 OlKX
5962-898410lLX
5962-898410l3X
5962-898410lKX
5962-8984102LX
5962-89841023X
5962-89841 02KX
5962-89841063X
5962-8984106KX
5962-89841 06LX
5962-8871309RX
5962-8871309XX
5962-8871310RX
5962-8871310XX
5962-8871311RX
5962-88713 llXX
5962-88713 12RX
5962-88713 12XX
PREFIX:CY
PREFIX:CY
SUFFIX:B
SUFFIX:DORW
SUFFIX:F
SUFFIX:L
SUFFIX:P
7C371-83JC
7C371-66JC
7C371-66JC
7C371-66YMB
7C373-83JC
7C373-66]C
7C373-66YMB
7C372-10OJC
7C372-83JC
7C372-66JC
7C372-66YMB
7C372-125JC
7C372-lOOJC
7C374-83JC
7C374-66]C
7C374-83JC
7C374-66JC
PALCI6L8L- 35C

~

-.,~

Product Line Cross Reference

?CYPRESS
AMD
PAL16L8A-4M
PAL16L8AC
PAL16L8ALC
PAL16L8ALM
PAL16L8AM
PAL16L8BM
PAL16L8C
PAL16L8LC
PAL16L8LM
PAL16L8M
PAL16L8QC
PAL16L8QM
PAL16R4A-4C
PAL16R4A-4M
PAL16R4ALC
PAL16R4ALM
PAL16R4AM
PAL16R4BM
PAL16R4C
PAL16R4LC
PAL16R4LM
PAL16R4M
PAL16R4QC
PAL16R4QM
PAL16R6A-4C
PAL16R6A-4M
PAL16R6AC
PAL16R6ALC
PAL16R6ALM
PAL16R6AM
PAL16R6BM
PAL16R6C
PAL16R6LC
PAL16R6LM
PAL16R6M
PAL16R6QC
PAL16R6QM
PALI6R8A-4C
PAL16R8A-4M
PAL16R8AC
PAL16R8ALC
PAL16R8ALM
PAL16R8AM
PAL16R8BM
PAL16R8C
PAL16R8LC
PAL16R8LM
PAL16R8M
PAL16R8QC
PAL16R8QM
PAL22Vl0-7JC
PAL22VlO-7PC
PAL22V1O-IOJC
PAL22VlO-lOPC
PAL22VIO-12/B3A
PAL22VlO-12/BLA
PAL22V1O-15DC
PAL22VlO-15JC
PAL22VlO-15PC
PAL22V1O-20/B3A
PAL22VlO-20/BLA
PAL22VlOIB3A

CYPRESS
PALC16L8-40M
PALC16L8-25C
PALCI6L8-25C
PALC16L8-30M
PALC16L8-30M
PALC16L8-20M
PALC16L8-35C
PALC16L8-35C
PALC16L8-40M
PALC16L8-40M
PALCI6L8L-35C
PALC16L8-40M
PALC16R4L- 35C
PALC16R4-40M
PALC16R4-25C
PALC16R4-30M
PALCI6R4-30M
PALC16R4-Z0M
PALC16R4-3SC
PALCI6R4-35C
PALCI6R4-40M
PALCI6R4-40M
PALCI6R4L-35C
PALCI6R4-40M
PALCI6R6L- 35C
PALCI6R6-40M
PALCI6R6-ZSC
PALCI6R6-2SC
PALC16R6-30M
PALC16R6-30M
PALCI6R6-20M
PALC16R6-3SC
PALC16R6-3SC
PALC16R6-40M
PALC16R6-40M
PALC16R6L-3SC
PALC16R6-40M
PALC16R8L-35
PALC16R8-40M
PALCI6R8-25C
PALCI6R8-2SC
PALCI6R8-30M
PALC16R8-30M
PALC16R8-20M
PALC16R8-35C
PALCI6R8-35C
PALC16R8-40M
PALC16R8-40M
PALC16R8L-35
PALC16R8-40M
PALCE22V1O-7JC
PALCE22VlO-7PC
PALCE22V1O-I0JC
PALCE22VlO-1OPC
PALCE22VlO-lOLMB
PALCE22VlO-lODMB
PALC22V1OB-15DC
PALC22VlOB-15JC
PALC22V1OB-15PC
PALC22V1OB-20LMB
PALC22VlOB-20DMB
PALC22VlO-35LMB

AMD
PAL22V1OIBLA
PAL22VlONB3A
PAL22V1ONBLA
PAL22V1OAJC
PAL22VlOAPC
PAL22VlOJC
PAL22V1OPC
PALCE16V8H-5JQ4
PALCE16V8H-7JQ4
PALCEI6V8H-7PQ4
PALCE16V8H-lOJC/4
PALCE16V8H-lOPC/4
PALCE16V8H-15JC/4
PALCE16V8H-15PQ4
PALCE16V8H-25JC/4
PALCEI6V8H-25PC/4
PALCEI6V8Q-15JQ4
PALCE16V8Q-15PC/4
PALCE16V8Q-25JQ4
PALCEI6V8Q-25PQ4
PALCE20V8H-5JQ4
PALCE20V8H-7JQ4
PALCE20V8H-7PC/4
PALCE20V8H-lOJQ4
PALCE20V8H-lOPC/4
PALCElOV8H-15JQ4
PALCE20V8H-lSPQ4
PALCEZOV8H-25JQ4
PALCElOV8H-25PC/4
PALCE20V8Q-15JQ4
PALCElOV8Q-lSPQ4
PALCE20V8Q-25JQ4
PALCElOV8Q-25PQ4
PALCE22VlOH -7JC
PALCE22VlOH-lOPC
PALCE22VlOH-lOJC
PALCE22VlOH-lOPC
PALCE22VlOH
-lS/B3A
PALCE22VlOH
-ISIBLA
PALCE22VlOH-15JC
PALCE22VlOH-15PC
PALCE22V1OH
-20/B3A
PALCE22V1OH
-20/BLA
PALCE22VlOH
-25IB3A
PALCE22VlOH
-25/BLA
PALCE22VlOH-25JC
PALCE22VlOH-25PC
PALCE22V1OH
-30/B3A
PALCE22VlOH
-30/BLA

CYPRESS
PALC22V1O-35DMB
PALC22VlO-25LMB
PALC22VlO-25DMB
PALC22VlO-25JC
PALC22VlO-25PC
PALC22V1O-35JC
PALC22V1O-35PC
PALCE16V8-5JC
PALCE16V8-7JC
PALCEI6V8-7PC
PALCE16V8-IOJC
PALCE16V8-lOPC
PALCE16V8-15JC
PALCE16V8-15PC
PALCE16V8-25JC
PALCE16V8-25PC
PALCE16V8L-15JC
PALCE16V8L-15PC
PALCEI6V8L-25JC
PALCEI6V8L-2SPC
PALCE20V8-5JC
PALCE20V8-7JC
PALCE20V8-7PC
PALCE20V8-lOJC
PALCE20V8-lOPC
PALCE20V8-1SJC
PALCE20V8-1SPC
PALCEZOV8- 2SJC
PALCE20V8-25PC
PALCElOV8L-1SJC
PALCElOV8L-15PC
PALCElOV8L-25JC
PALCElOV8L-25PC
PALCE22VlO-7JC
PALCE22VlO-IOPC
PALCE22VlO-lOJC
PALCE22VlO-lOPC
PALCE22VlO
-ISLMB
PALCE22VlO
-15DMB
PALCE22VlO-15JC
PALCE22V1O-15PC
PALCE22VlO
-15LMB
PALCE22VIO
-15DMB
PALCE22V1O
-25LMB
PALCE22VlO
-25DMB
PALCE22VlO-25JC
PALCE22V1O-25PC
PALCE22V1O
-25LMB
PALCE22V1O
-25DMB

ATMEL
22VlO
22V1O-15

CYPRESS
PALC22VlO
PALC22VlOB
CYPRESS
PREFIX:CY

HARRIS
PREFIX:AT

1-11

PREFIX:HM
PREFIX:HPL
SUFFIX:8
PREFIX: 1
PREFIX:9
PREFIX:4
PREFIX:3
16LC8-5
16LC8-8
16LC8-9
16RC4-5
16RC4-8
16RC4-9
16RC6-5
16RC6-8
16RC6-9
16RC8-5
16RC8-8
16RC8-9

PREFIX:CY
PREFIX:CY
SUFFIX:B
SUFFIX:D
SUFFIX:F
SUFFIX:L
SUFFIX:P
PALC16L8L-35C
PALC16L8-40M
PALC16L8-40M
PALC16R4L- 35C
PALC16R4-40M
PALC16R4-40M
PALC16R6L-35C
PALC16R6-40M
PALC16R6-40M
PALC16R8L-35C
PALC16R8-40M
PALCI6R8-40M

INTEL
PREFIX:8SC
PREFIX:85C
PREFIX:D
PREFIX:L
PREFIX:P
SUFFIX:/B
22VI0-lOC
22VIO-lOC
22VIO-IOC
22V1O-lOC
22VlO-lSC
22VlO-15C

CYPRESS
PREFIX:CY
PREFIX:PLD
SUFFIX:D
SUFFIX:L
SUFFIX:P
SUFFIX:B
PALC22VlOD-7C
PALC22VlOD-IOC
PAL22VIOC-7C+
PAL22VlOC-IOC+
PALC22VlOB-15C
PALC22VIOD-15C

LATTICE
PREFIX:EE
PREFIX:GAL
PREFIX:ST
SUFFIX:B
SUFFIX:D
SUFFIX:L
SUFFIX:P
GAL16V8A-lOLJ
GAL16V8A-lOLP
GAL16V8A-1SLJ
GAL16V8A-1SLP
GAL16V8A-15QJ
GAL16V8A -15QP
GAL16V8A - L5LJ
GAL16V8A - 25LP
GAL16V8A-25QJ
GAL16V8A - 25QP
GAL16V8B-7LJ
GAL16V8B-7LP
GAL16V8B-lOLJ
GAL16V8B-I0LJI
GAL16V8B-lOLP
GAL16V8B-lOLPI
GAL16V8B-15LJI
GAL16V8B-15LPI
GAL16V8B- 25LJI
GAL16V8B- 25LPI
GAL16V8A
GAL16V8B

CYPRESS
PREFIX:CY
PREFIX:PALCE
PREFIX:CY
SUFFIX:B
SUFFIX:D
SUFFIX:L
SUFFIX:P
PALCE16V8-10JC
PALCE16V8-10PC
PALCE16V8-15JC
PALCE16V8-15PC
PALCE16V8L-15JC
PALCE16V8L-15PC
PALCEI6V8-25JC
PALCEI6V8-25PC
PALCE16V8L-25JC
PALCE16V8L-25PC
PALCE16V8-7JC
PALCE16V8-7PC
PALCE16V8-1OJC
PALCE16V8-lOJI
PALCE16V8-lOPC
PALCE16V8-lOPI
PALCE16V8-15JI
PALCE16V8-15PI
PALCE16V8-25JI
PALCE16V8-25PI
PALCE16V8
PALCE16V8

II

Product Line Cross Reference
LATTICE
GAl20VSA -lOU
GAL20V8A -lOLP
GAL20V8A -15U
GAL20V8A -15LP
GALZOV8A -15QJ
GAL20V8A -15QP
GALZOV8A-LSU
GAL20V8A -25LP
GAL20V8A - 25QJ
GALZOV8A -25QP
GALZOV8B-7U
GAl2OV8B-7LP
GALZOV8B-10U
GALZOV8B-1OUI
GALZOV8B-1OLP
GALZOV8B-lOLPI
GALZOV8B-15UI
GALZOV8B-15LPI
GALZOV8B-25UI
GAL20V8B-25LPI
GAL20V8A
GAL20V8B
GALZ2VIOB-7U
GAL22VlOB-7LP
GAL22VlOB-lOU
GAL22VlOB-lOLP
GAL22VlOB·15LD

GALZ2V1OB-1SU
GAL22VIOB-1SUI
GALZ2V1OB-15LP
GALZ2V1OB-lSLPI
GALZ2VIOB-15LR
/883
GALZ2VlOB-20UI
GAL22VlOB-20LD
/883
GAL22VlOB-20LPI
GAL22VlOB-20LR
/883
GAL22VlOB-25LD
/883
GALZ2VlOB- 25U
GAL22V1OB-25UI
GAL22V1OB-2SLP
GAL22V1OB-2SLPI
GALZ2VlOB-25LR
/883
GAL22VlOB-30LD
/883
GAL22VlOB-30LR
/883
GALZ2VlOC-5U
GAL22V1OC-7U
GAL22VlOC-7PC

CYPRESS
PALCE20V8-lOJC
PALCE20V8-lOPC
PALCE20V8-15JC
PALCE20V8-15PC
PALCE20VSL-15JC
PALCE20V8L-15PC
PALCE20V8-25JC
PALCE20V8-25PC
PALCE20V8L-25JC
PALCE20V8L-25PC
PALCE20V8-7JC
PALCE20V8-7PC
PALCE20V8-lOJC
PALCE20V8-10JI
PALCE20V8-10PC
PALCE20V8-lOPI
PALCE20V8-1SJI
PALCE20V8-15PI
PALCE20V8-25JI
PALCE20V8-25PI
PALCE20V8
PALCE20V8
PALCE22V1O-7JC
PALCE22VIO-7PC
PALCE22VlO·lOJC
PALCE22VIO-lOPC
PALCE22VlO15DMB
PALCE22VlO·15JC
PALCE22V10-lSJI
PALCE22V1O·15PC
PALCE22V1O·lSPI
PALCE22VlO15LMB
PALCE22VlO·1SJI
PALCE22VlO15DMB
PALCE22VlO·15PI
PALCE22VlOlSLMB
PALCE22V1O25DMB
PALCE22V10·2SJC
PALCE22V1O·25JI
PALCE22V10·2SPC
PALCE22V1O·25PI
PALCE22V1O25LMB
PALCE22VlO25DMB
PALCE22VlO25LMB
PALCE22VlO-5JC
PALCE22VlO-7JC
PALCE22VIO-7PC

MMIJAMD
SUFFlX:883B
SUFFlX:F
SUFFIX:J
SUFFIX:L
SUFFIX:N
PALl6R8D-4C

CYPRESS
SUFFIX:B
SUFFIX:F
SUFFIX:D
SUFFIX:L
SUFFIX:P
PALC1648L-25C

/883

MMI/AMD
SUFFIX:SHRP
PAL12LlOC
PAL12LlOM
PAL14LSC
PAL14LSM
PAL16L6C
PAL16L6M
PAL16LSA-2C
PAL16L8A-2M
PAL16LSA-4C
PAL16LSA-4M
PAL16LSAC
PAL16LSAM
PAL16LSB-2C
PAL16LSB-2M
PAL16LSB-4C
PAL16LSB-4M
PAL16LSBM
PAL16LSC
PAL16LSD-4C
PAL16LSD-4M
PAL16LSM
PAL16R4A-2C
PAL16R4A-2M
PAL16R4A-4C
PAL16R4A-4M
PALl6R4AC
PAL16R4AM
PAL16R4B-2C
PAL16R4B-2M
PALl6R4B-4C
PAL16R4B-4M
PAL16R4BM
PAL16R4C
PAL16R4D-4C
PAL16R4M
PAL16R6A-2C
PAL16R6A-2M
PAL16R6A-4C
PAL16R6A-4M
PALl6R6AC
PAL16R6AM
PAL16R6B-2C
PAL16R6B-2M
PAL16R6B-4C
PAL16R6B-4M
PAL16R6BM
PAL16R6C
PAL16R6D-4C
PAL16R6M
PAL16R8A-2C
PAL16R8A-2M
PAL16R8A-4C
PAL16R8A-4M
PAL16R8AC
PAL16R8AM
PAL16R8B-2C
PAL16R8B-2M
PAL16R8B-4C
PAL16R8B-4M
PAL16R8BM
PAL16R8C

CYPRESS
SUFFIX:B
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-35C
PLDC20GlO-40M
PALC16LS-35C
PALC16LS-40M
PALC16LSL-3SC
PALC16LS-40M
PALC16LS-25C
PALC16LS-30M
PALC16LS-35C
PALC16LS-30M
PALC16LSL-35C
PALC16LS-40M
PALC16LS-20M
PALC16LS-3SC
PALC16LSL-25C
PALC16LS-30M
PALC16LS-40M
PALC16R4-35C
PALC16R4-40M
PALC16R4L-3SC
PALC16R4-40M
PALC16R4-25C
PALC16R4-30M
PALC16R4-25C
PALC16R4-30M
PALC16R4L-35C
PALC16R4-40M
PALC16R4-20M
PALC16R4-35C
PALC16R4L-25C
PALC16R4-40M
PALC16R6-35C
PALC16R6-40M
PALC16R6L-35C
PALC16R6-40M
PALC16R6-25C
PALC16R6-30M
PALC16R6-25C
PALC16R6-30M
PALC16R6L-35C
PALC16R6-40M
PALC16R6-20M
PALC16R6-35C
PALC16R6L-25C
PALC16R6-40M
PALC16R8- 35C
PALC16R8-40M
PALC16R8L- 35C
PALC16R8-40M
PALC16R8-25C
PALC16R8-30M
PALC16R8-25C
PALC16R8-30M
PALC16R8L-35C
PALC16R8-40M
PALC16R8-20M
PALC16R8-35C

MMIJAMD
PAL16R8M
PAL18UC
PAL18UM
PALZOLlOAC
PAL20LlOAM
PALZOLlOC
PAL20LlOM
PALZOLZC
PAL20L2M
PAL20LSA-2C
PALZOLSA-2M
PALZOLSAC
PALZOLSAM
PAL20LSC
PALZOLSM
PAL20R4A-2C
PAL20R4A-2M
PALZOR4AC
PAL20R4AM
PALZOR4C
PALZOR4M
PAL20R6A-2C
PALZOR6A-2M
PALZOR6AC
PALZOR6AM
PALZOR6C
PALZOR6M
PALZOR8A-2C
PAl2OR8A-ZM
PALZOR8AC
PALZOR8AM
PALZOR8C
PALZOR8M
PALC22V10/A

CYPRESS
PALC16R8-40M
PLDCZOGlO-35C
PLDCZOGIO-40M
PLDCZOGlO-35C
PLDC20GlO-30M
PLDCZOGlO-35C
PLDC20GlO-40M
PLDCZOGlO- 35C
PLDC20GlO-40M
PLDC2OG1O-3SC
PLDC20GlO-40M
PLDC20GlO- 2SC
PLDCZOGlO-30M
PLDC20GlO-35C
PLDCZOG 1O-40M
PLDC20G1O-35C
PLDCZOGlO-40M
PLDC20GlO- 25C
PLDCZOGlO-30M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-35C
PLDC20GIO-40M
PLDC20GIO-25C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-35C
PLDC20GlO-40M
PLDCZOGlO-25C
PLDC20GlO-30M
PLDCZOGlO-3SC
PLDC20GlO-40M
PALC22VlO-35C

NATIONAL
PREFIX:DM
PREFIX:GAL
PREIFX:IDM
PREFIX:NM
PREFIX:NMC
SUFFIX:J
SUFFIX:N
18UC
18UM
20LZM
GAL22VlO-1SC
GALZ2VlO-2OI
GALZ2VlO-20M
GALZ2VlO-25C
GALZ2VlO-3OI
GALZ2VlO-30M
PAL164A2M
PALl6LSA2C
PAL16LSA2M
PAL16LSAC
PAL16LSAM
PAL16LSB2C
PAL16LSB2M
PAL16LSB4C
PALl6LSB4M
PAL16LSBM

CYPRESS
PREFIX:CY
PREFIX:None
PREFIX:CY
PREFIX:CY
PREFIX:CY
SUFFIX:D
SUFFIX:P
PLDC2OGlO-3SC
PLDCZOG lO-40M
PLDC20GIO-40M
PALCE22VlO-15C
PALCE22VlO-15I
PALCE22VlO-15M
PALCE22VlO-25C
PALCE22V1O-251
PALCE22VlO-25M
PALC16R4-40M
PALC16L8-35C
PALC16LS-40M
PALC16L8-25C
PALC16LS-30M
PALC16LS-25C
PALC16LS- 30M
PALC16LSL-35C
PALC16LS-40M
PALC16L8-20M

Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on ICC and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
• = meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
t
SOIConly
:j: = 32·pin LCC crosses to the 7C198M

1-12

=-~

Product Line Cross Reference

~'CYPRESS

NATIONAL
PALl6LBC
PAL16LBM
PALl6R4A2C
PALl6R4AC
PALl6R4AM
PALl6R4B2C
PALl6R4B2M
PAL16R4B4C
PAL16R4B4M
PALIGR4BM
PAL16R4C
PAL16R4M
PAL16RGA2C
PAL1GR6A2M
PAL16R6AC
PAL16R6AM
PAL16R6B2C
PALl6R6B2M
PALl6R6B4C
PALl6R6B4M
PALl6R6BM
PAL16R6C
PAL16R6M
PALI6R8A2C
PAL16R8A2M
PAL16R8AC
PAL16R8AM
PAL16R8B2C
PAL16R8B2M
PAL16R8B4C
PAL16R8B4M
PAL16R8BM
PAL16R8C
PAL16R8M
PAL20L2C
PAL20LBAC
PAL20LBAM
PAL20LBBC
PAL20LBBM
PAL20LBC
PAL20LBM
PAL20LlOB2C
PAL20LlOB2M
PAL20LlOC
PAL20LlOM
PAL20R4AC
PAL20R4AM
PAL20R4BC
PAL20R4BM
PAL20R4C
PAL20R4M
PAL20RGAC
PAL20R6AM
PAL20R6BC
PAL20R6BM
PAL20R6C
PAL20RGM
PAL20R8AC
PAL20R8AM
PAL20R8BC
PAL20R8BM

CYPRESS
PALC16LB-35C
PALC16LB-40M
PALC16R4-35C
PALC16R4-25C
PALC16R4-30M
PALCI6R4-25C
PALCI6R4-30M
PALCI6R4L-35C
PALCI6R4-40M
PALCIGR4-20M
PALC1GR4-35C
PALC1GR4-40M
PALC1GRG-35C
PALC1GRG-40M
PALC1GRG-25C
PALC1GRG-30M
PALC16R6-25C
PALC16R6-30M
PALCIGR6L-35C
PALC1GRG-40M
PALCI6R6-20M
PALC1GRG-35C
PALC1GRG-40M
PALC1GR8-35C
PALCI6R8-40M
PALC16R8-25C
PALC16R8-30M
PALC16R8-25C
PALC16R8-30M
PALCI6R8L-35C
PALC16R8-40M
PALC16R8-20M
PALC16R8-35C
PALC16R8-40M
PLDC20GI0-35C
PLDC20G10-25C
PLDC20GlO-30M
PLDC20G10-25C
PLDC20GlO-30M
PLDC20GI0-35C
PLDC20G10-40M
PLDC20GI0-25C
PLDC20GI0-30M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO- 25C
PLDC20GI0-30M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-25C
PLDC20GlO-30M

NATIONAL
PAL20R8C
PAL20R8M

CYPRESS
PLDC20GlO- 35C
PLDC20GlO-40M

QIDCKLOGIC
PREFIX:QL
8XI2B-*CG68C
8XI2B-*CGG81
8XI2B-*CG68M
8X12B- *PFIOOC
8X12B-*PF10OI
8X12B-*PL44C
8X12B- *PL441
8X12B-*PL68C
8X12B- 'PL68I
12X16B-*CG84C
12XI6B-*CG84I
12X16B-*CG84M
12XIGB- *PF100C
12X16B- *PF1OOI
12X16B- *PL68C
12X16B- *PL68I
12X16B- *PL84C
12XIGB- *PLB4I
16X24B-*GCI44C
16X24B-*GCI44I
16X24B-*GCI44M
16X24B-*PFIOOC
16X24B-*PFlOOI
16X24B-*PFI44C
16X24B-*PF1441
16X24B- *PLB4C
16X24B-*PLB4I
24X32B-*GC44C
24X32B-*GC144I
24X32B-*GC144MB
24X32B-*GC208C
24X32B-*GC208I
24X32B- *GC208M
24X32B- *PF144C
24X32B- *PF144I
24X32B- *PF208C
24X32B-'PF208I

CYPRESS
PREFIX:CY
7C382A-*GC
7C382A-*GJ
7C382A-*GMB
7C382A-*AC
7C382A-*AI
7C381A-*JC
7C381A-*JI
7C382A-*JC
7C382A-*JI
7C384A-*GC
7C384A-*GJ
7C384A-*GMB
7C384A-*AC
7C384A-*AI
7C383A-*JC
7C383A-*JI
7C384A-*JC
7C384A-*JI
7C386A-*GC
7C386A-*GJ
7C386A-*GMB
7C385A-*AC
7C385A-*AI
7C386A-*AC
7C386A-*AI
7C385A-*JC
7C385A-*JI
7C387A-*GC
7C387A-*GJ
7C387A-*GMB
7C388A-*GC
7C388A-*GJ
7C388A-*GMB
7C387A-*AC
7C387A-*AI
7C388A-*AC
7C388A-*AI

TI
PREFIX:JBP
PREFIX:PAL
PREFIX:SM
PREFIX:SMJ
PREFIX:SN
PREFIX:TBP
PREFIX:TIB
PREFIX:TMS
SUFFIX:F
SUFFIX:J
SUFFIX:N
22VI0AC
22VlOAM
PALI6LB-20M
PALI6LB-25C
PALI6LB-30M
PALI6LBA-2C
PALI6LBA-2M
PALl6LBAC

CYPRESS
PREFIX:CY
SUFFIX:P
PREFIX:CY
PREFIX:CY
PREFIX:CY
PREFIX:CY
PREFIX:CY
PREFIX:CY
SUFFIX:F
SUFFIX:L
SUFFIX:D
PALC22VI0-25C
PALC22VI0-30M
PALCIGLB-20M
PALCI6LB-25C
PALCI6LB-30M
PALCI6LB-35C
PALC16LB-40M
PALCI6LB-25C

1-13

TI
PAL16LBAM
PAL16R4-20M
PAL16R4-25C
PAL16R4-30M
PALl6R4A-2C
PALl6R4A-2M
PALl6R4AC
PALlGR4AM
PALl6R6-20M
PALl6R6-25C
PALl6R6-30M
PALl6R6A-2C
PALl6R6A-2M
PALl6R6AC
PALl6R6AM
PALl6R8-25C
PALl6R8-30M
PALl6R8A-2C
PALlGR8A-2M
PALl6R8AC
PALlGR8AM
PAL20LBA-2C
PAL20LBA-2M
PAL20LBAC
PAL20LBAM
PAL20LlOA-2C
PAL20LlOA-2M
PAL20LlOAC
PAL20LlOAM
PAL20R4A-2C
PAL20R4A-2M
PAL20R4AC
PAL20R4AM
PAL20R6A-2C
PAL20R6A-2M
PAL20R6AC
PAL20R6AM
PAL20R8A - 2C
PAL20R8A-2M
PAL20R8AC
PAL20R8AM
PAL22VlO-7C
PAL22VlO-15C
PAL22VlO-20M
PAL22VlOAC
PAL22VI0AC
PAL22V10AM
PAL22V10AM
PAL22VlOC
PAL22V10C

CYPRESS
PALC16LB-30M
PALC16R4-20M
PALCI6R4-25C
PALCI6R4-30M
PALCI6R4-25C
PALCI6R4-40M
PALCI6R4-25C
PALCI6R4-30M
PALCIGR6-20M
PALC1GR6-25C
PALC16R6-30M
PALC16R6-25C
PALC16R6-40M
PALC16R6-25C
PALC16R6-30M
PALC16R8-25C
PALCI6R8-30M
PALC1GR8-25C
PALCIGR8-40M
PALC1GR8-25C
PALCI6R8-30M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20G10-35C
PLDC20GlO-30M
PLDC20G10-25C
PLDC20GlO-30M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC2OGlO-25C
PLDC2OGlO-30M
PALCE22VlO-7C
PALC22VlOB-15C
PALC22VlOB-20M
PALC22VlO-25C
PALC22VlOL-25C
PALC22VlO-25MB
PALC22VlO-30MB
PALC22VlO-35C
PALC22VlOL- 35C

•

Military Overview
Every final data sheet also contains detailed Group A subgroup
testing information. All of the specified parameters that are tested
at Group A are listed in a table at the end of each final data sheet,
with a notation as to which specific Group A test subgroups apply.

Features
Success in any endeavor requires a high level of dedication to the
task. Cypress Semiconductor has demonstrated its dedication
through its corporate commitment to support the military marketplace. This commitment starts with product design. All products
are designed using our state-of-the-art CMOS and BiCMOS processes, and they must meet the full - 55 to + 125 degrees Celsius
operational criteria for military use. The commitment shows in
our dedication to meet and exceed the stringent quality and reliability requirements of MIL-STD-883 and MIL-PRF-38535. It
shows in Cypress's participation in each of the military processing
programs: MIL-STD-883 compliant, SMD (Standardized Military Drawing), and QML. Finally, our commitment shows in our
leadership position in special packages for military use.

Assembly Traceability Code@>
Cypress Semiconductor places an assembly traceability code on
every military package that is large enough to contain the code.
The ATC automatically provides traceability for that product to
the individual wafer lot. This unique code provides Cypress with
the abilitytodeterminewhiclj.operators andequipmentwere used
in the manufacture of that product from start to finish.

Quality and Reliability
MIL-STD-883 and MIL-PRF-38535 spell out the toughest of
quality and reliability standards for military products. Cypress
products meet all of these requirements and more. Our in-house
quality and reliability programs are being updated regularly with
tighter and tighter objectives. Please refer to the chapter on Quali- '
ty, Reliability, and Process Flows for further details.

Product Design
Every Cypress product is designed to meet or exceed the full temperature and functional requirements of military product. This
means that Cypress builds military product as a matter of course,
rather than as an accidental benefit offavorable test yield. Designs
are being carried out in our industry-leading 0.65-micron CMOS
and BiCMOS processes. Cypress is able to offer a family of products that are industry leaders in density, low operating and standby
current, and high speed. In addition, our technology results in
products with very small manufacturable die sizes that will fit into
the LCCs and flatpacks so often used in military programs.

Military Product Offerings
Cypress offers three levels of processing for military product.
First, all Cypress products are available with processing in full
compliance with MIL-STD-883.

DESC-Certified Facility
On May 8,1986, the Cypress facility at 3901 North First Street in
San Jose, California was certified by DESC for the production of
JAN Class B CMOS Microcircuits. And, most recently, on February 16, 1994, Cypress received QML (Qualified Manufacturers
List) transitional certification from Defense Electronic Supply
Center to the requirements of MIL-PRF-38535. This certification allows Cypress to continue to produce JAN products as well as
manufacture devices listed on the QML. QML certification attests to Cypress' commitmentto quality and reliability through the
use of statistical process control and total quality management.
Our wafer fabrication facilities are Class 10 (San Jose) and Class
1 (Round Rock, TX and Bloomington, MN) manufacturing environments and our assembly facility is also a clean room.

Datasheet Documentation
Every Cypress final data sheet is a corporate document with a revision history. The document number and revision appears on each
final data sheet. Cypress maintains a listing of all data sheet documentation and a copy is available to customers upon request. This
gives a customer the ability to verify the current status of any data
sheet and it also gives that customer the ability to obtain updated
specifications as required.

Second, selected products are available to the SMD (Standardized
Military Drawing) program administered by DESC. These products are not only fully MIL-STD-883D compliant, but are also
screened to the electrical requirements of the applicable military
drawing.
Third, selected products are available as QMUJAN devices.
These products are processed in full accordance with MILPRF-38535B and they are screened to the electrical requirements
of the applicable slash sheet.

Product Packaging
All packages for military product are hermetic. A look at the package appendix in the back of this data book will give the reader an
appreciation of the variety of packages offered. Included are cerDIPs, windowed CerDIPs, leadless chip carriers (LCCs), windowed leadless chip carriers, cerpaks, windowed cerpaks, quad
cerpaks, windowed quad cerpaks, bottom-brazed flatpacks, and
pin grid arrays.

Summary
Cypress Semiconductor is committed to the support of the militarymarketplace. Our commitment is demonstrated by our product designs, our DESC-certified facility, our documentation and
traceability, our quality and reliability programs, our support of all
levels of military processing, and by our leadership in special
packaging.

Assembly 1taceability Code is a trademark of Cypress Semiconductor Corporation.

1-14

=

rcYPRESS ======M=i=li=ta=ry~P=r=o=d=u=ct=S=e=l=ec=t=or=G=u=id=e=

PLDs
Organization
PAl20
PALC20
PALC20
PALCE20
PLD24
PLD24
PLDC24
PLD24
PLDC24
PLD24
PLDC24
PLDC24
PLDC24
PLDC24
PLDC24
PLDC24
PLDC28
PLDC28
PLDC28
PLDC28
PLDC28
PLD28

16L8, 16R8, 16R6, 16R4
16L8, 16R8, 16R6, 16R4
16L8, 16R8, 16R6, 16R4
16V8-Macrocell
22Vl0C-Macrocell
22VlOC-Macrocell
22V10-Macrocell
22V10-Macrocell
22Vl0-Macrocell
22V10-Macrocell
22V10-Macrocell
22V10-Macrocell
22V10D-Macrocell
20G 100Generic
20RA10-Asynchronous
20RA10-Asynchronous
7C330-State Machine
7C330-State Machine
7C331-Asynchronous
7C331-Asynchronous
7C332-Combinatorial
7C335-Synchronous

Pins
20
20
20
20S
24S
24S
24S
24S
24S
24S
24S
24S
24S
24S
24S
24S
28S
28S
28S
28S
28S
28S

Part Number

JAN/SMD
Number[ll"

PAL16XX
PALC16XX
PALC16XX
PALCE16V8
PAL22VlOC
PAL22VP1OC
PALC22VlO
PALC22VlOB
PALC22VlO
PALC22VlOB
PALC22VlOB
PALC22V1OB
PALC22V1OD
PLDC20GlO
PLD20RAlO
PLD20RA1O
CY7C330
CY7C330
CY7C331
CY7C331
CY7C332
CY7C335

5962-92338(0)
5962-88678(W)
5962-88713(0)
5962-89839
5962-91760(0)
5962-91760(0)
5962-87539(W)
5962-87539(W)
5962-88670(0)
5962-88670(0)
M38510/507(W)
M3851O/508(0)
5962-89841 (0)
5962-88637(0)
5962-90555(0)
5962-90989(W)
5962-89546(W)
5926-90802(0)
5962-90754(W)
5962-89855(0)
5962-91584(W)
5862-9451O(W)

Part Number

JAN/SMD
Number[1\*

Icc

Speed (ns/MHz)

(mA@ns/MHz)

883
Avai\ability

tpD= 7,10
tpD = 20,30,40
tpD = 20,30, 40
tPD/S/CO = 10/10n
tPD/S/CO = 1O/3.6n.s
tPD/S/CO = 1O/3.6n.s
tPD/S/CO = 25/18/15
tpD/S/CO = 20/17/15
tPD/S/CO = 25/18/15
tPD/S/CO = 15/12/10
tPD/S/CO = 15/12/10
tPD/S/CO = 15/12/10
tPD/S/co=IO/6n
tPD/S/CO = 20/17/15
tPD/SU/CO = 20/10/20
tPD/SU/co=20/1O/20
50,40,28 MHz
50,40,28 MHz
tpD = 25, 30, 40
tpD = 25,30,40
tpD = 20,25,30
fMAX5 = 66.6,50,83

180@7
70@20
70@20
130@10
190@1O
190@1O
100@25
100@20
100@25
120@15
120@15
120@15
130@1O
80@30
100@25
100@25
180@40MHz
180@40MHz
200@20MHz
200@20MHz
200@24MHz
160@66.6MHz

Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now

Speed (ns/MHz)

(mA@ns/MHz)

883
Availability

tpD = 12,20,25,35
tpD = 15,20,25,30,35
tpD = 15,20,25,30,35
tpD = 20,25,30,35,40
tpD = 20,25,30,35
100,83,66 MHz
fMAX/tS/teO= 83MHz/
10/10
fMAXitslteo=83MHz/8/8

220@25
225@25
320@30
480@30
320@35
150@100MHz
260@83

Now
Now
Now
Now
Now
Now
Now

300@83

fMAX!tsltco=83MHz/8/8
fMAXitsftco=B3MHz/B/8
fMAXitsltco=83MHz/B/B

300@B3
370@B3
370@B3

CPLDs
Organization

MAX28
MAX40
MAX68
MAX84
MAX100
PLDC28
37X-44

7C344-32 Macrocell
7C343-64 Macrocell
7C342-128 Macrocell
7C341-192 Macrocell
7C346-128 Macrocell
7C361-StateMachine
7C371-32 Macrocell

37X-44
37X-84

7C372-64 Macrocell
7C373-64 Macrocell
7C374-128 Macrocell
7C375-12B Macrocell
7C376-192 Macrocell

37X-B4

37X-16O
FLAsH.370160
FLAsH.370-

Pins

CY7C344/B
CY7C343/B
CY7C342/B
CY7C341/B
CY7C346/B
CY7C361
CY7C371

5962-90611(W)
5962-92158(W)
5962-89468(W)
5962-92062(W)
5962-91344(W)

84
84
160
160

CY7C372
CY7C373
CY7C374
CY7C375
CY7C376

5962-94688(0)
5962-94689(0)
5962-94713(0)

7C377-192 Macrocell

240

CY7C377

7C378-256 Macrocell

160

CY7C378

7C379-256 Macrocell

240

CY7C379

28S
40/44
68
84
84/100
28S

44
44

5962-94684(0)

fMAX/tS/tco=83MHz/
12/12
fMAX/tS/teO = 83MHz/
12/12
fMAX/tS/tco=83MHz/
12/12
fMAX/tsltco=83MHz/
12/12

240
FLAsH.370160
FLAsH.370-

240

Icc

300ffBD

Now
Now
Now
Now
4Q95

300(TBD

4Q95

300(TBD

2Q95

300(TBD

2Q95

FPGAs
Organization
1KFPGA
2KFPGA
4KFPGA

CMOSBx12

CMOS 12x16
CMOS 16x24

Pins

68
84
145

Part Number

JAN/SMD
Number[1\*

Speed (ns/MHz)
-0,-1
-0,-1
-0,-1

CY7C382A
CY7C384A
CY7C385A

1-15

Icc

(mA@ns/MHz)

883
Availability

20
20
20

Now
Now
Now

III

!jrcYPRESS ======M=i=li=ta=ry~P=r=o=d=u=ct=S=e=l=ec=t=or=G=u=id=e=
FPGAs (continued)
Organization

Pins

JAN/SMD
Nnmber[ll·

PartNnmber

4K1-

r0-

D

Q

I--

t>,

0--0

~~
v
INTRO-5

Figure 3. Registered Outputs with Feedback
state sequencer. The summation of the product terms is stored in
the D-type output ffip-flop on the rising edge of the system clock.
The Q output ofthe ffip-flop can then be gated to the output pin by
enabling the three-state output buffer. The output of the ffip-flop
can also be fed back into the array as an input term. The output
feedback feature allows the PLD to remember and then alter its
function based upon that state. This circuit can be used to execute
such functions as counting, skip, shift, and branch.

of any I/O pins as inputs. The CY7C335 also contains four dedicated hidden macrocells with no external output that are used as
additional state registers for creating high-performance state machines (Figure 7).

Asynchronous Register Control

The programmable macrocell, illustrated in Figure 4, provides the
capability of defining the architecture of each output individually.
Each of the potential outputs may be specified to be "registered"
or "combinatorial." Polarity of each output may also be individually selected allowing complete flexibility of output configuration.
Further configurability is provided through "array" configurable
"output enable" for each potential output. This feature allows the
outputs to be reconfigured as inputs on an individual basis or alternately used as a bidirectional I/O controlled by the programmable
array (see Figure 5).

Cypress also offers PLDs that may be used in asynchronous systems in which register clock, set, and reset are controlled by the
outputs of the product term array. The clock sigual is created by the
processing of external inputs and/or internal feedback by the logic
of the product term array, which is then routed to the register clock.
The register set and reset are similarly controlled by product term
outputs and can be triggered at any time independent of the register clock in response to external and/or feedback inputs processed
by the logic array. The proprietaryCY7C331 Asynchronous Registered PLD, for which the I/O macrocell is illustrated in Figure 8, is
an example of such a device. The register clock, set, and reset functions of the CY7C331 are all controlled byproduct terms and are
dependent only on input signal timing and combinatorial delay
through the device logic array to enable their respective functions.

Buried Register Feedback

Input Register Cell

The CY7C331 and CY7C335 PLDs provide registers that may be
"buried" or "hidden" by electing feedback of the register output.
These buried registers, which are useful in state machines, may be
implemented without sacrificing the use of the associated device
pin as an input. In previous PLDs, when the feedback path was activated, the input pin-path to the logic array was blocked. The proprietary CY7C335 reprogrammable synchronous state machine
macrocell illustrates the shared input multiplexer, which provides
an alternative input path for the I/O pin associated with a buried
macrocell register (Figure 6). Each pair of macrocells shares an input multiplexer, and as long as alternate macrocells are buried, up
to six of the twelve output registers can be buried without the loss

Other Cypress PLDs provide input register cells to capture short
duration inputs that would not otherwise be present at the inputs
long enough to allow the device to respond. The proprietary
CY7C335 Reprogrammable Synchronous State Machine provides
these input register cells (Figure 9). The clock for the input register
may be provided from one of two external clock input pins selectable by a configuration bit, C4, dedicated for this purpose for each
input register. This choice of input register clock allows signals to
be captured and processed from two independent system sources,
each controlled by its own independent clock. These input register
cells are provided within I/O macrocells, as well as for dedicated input pins.

Programmable Macrocell

Document #: 38-00165 - B

2-2

.=::;r-

----.....

-'i~

Introduction to Cypress PLDs

'CYPRESS

CLOCK AR
OE
0

..L.L
)-

~

11

MACRO·
CELL

>

SP

~

INTRO-6

Figure 4. Programmable Macrocell

fI

9
0

OUTPUT REG
BYPASS MUX

1
PIN14:0E- OUTPUT
ENABLE
0 MUX

OUTPUT ENABLE PRODUCT TERM

SET PRODUCT TERM

II

\"" 1

EX OR PRODUCT TERM

S

SClJ(',~

SClK2

ClK
MUX

1

?

TO ARRAY~

J--

--[)

0

I/O
PIN

Q
R

-

I

C5
RESET PRODUCT TER~

~I

Q-

D

,L/

II

1

0
FEED
BACK
MUX

INPUT
REG
BYPASS
MUX

1
C2

C1

0

IClK1

INPUT
CLOCK
1 MUX

IClK2

1
INPUT REGISTER

~

Q

D~

ci3
n

i'>

'---

TO ARRAY

~

<

0
SHARED""::'INPUT
MUX
1

I

I

CX(11 -16)

INTRO-7

FROM ADJACENT MACROCEll

Figure 5. CY7C335 I/O Macrocell

2-3

110

Introduction to Cypress PLDs

FROM
LOGIC
ARRAY
FEEDBACK
TO LOGIC
ARRAY
INPUT TO
LOGIC
ARRAY
FEEDBACK
TO LOGIC
ARRAY
FROM
LOGIC
ARRAY
INTRO-8

Figure 6. CY7C33S I/O Macrocell Pair Shared Input MUX

SET PRODUCT TERM

S

}----1 D

Q

!
SCLK1
SCLK2
C5

RESET PRODUCT TERM

INTRO-9

Figure 7. CY7C33S Hidden Macrocell

2-4

Introduction to Cypress PLDs
PIN14

----I
OE
MUX

SET PRODUCT TERM

S

D

01-_-------"

OUTPUT
REGISTER

CLOCK PRODUCT TERM

R

RESET PRODUCT TERM

___..:::..,.1-------- FEEDBACK
MUX

S

o

D

INPUT
REGISTER

R
INTRO-l0

TO SHARED
INPUTMUX

Figure 8. CY7C331 Registered Asynchronous Macrocell

1
INPUT REGISTER

r---

INPUT
PIN

0

D

0

INPUT
REG
BYPASS
MUX

I.....-

ICLK1

ICLK2

1

I>
INTRO-ll

C6

Figure 9. CY7C335 Input Macrocell

2-5

TO ARRAY

.>

d7

0""'-INPUT
CLOCK lMUX

....

This is an abbreviated datasheet. Contact a Cypress
representative for complete specifications. For new
designs, please refer to the PALCEI6V8.

PAL®C20 Series

Reprogrammable CMOS
PALC 16L8, 16R8, 16R6, 16R4
• High reliability
- Proven EPROM technology
- > 1500V input protection from
electrostatic discharge
-100% AC and DC tested
-10% power supply tolerances
- High noise immunity
- Security feature prevents pattern
duplication
-100% programming and functional
testing

Features
• CMOS EPROM technology for reprogrammability
• High performance at quarter power
-tPD = 25ns
-ts = 20ns
-teo = 15ns
-Icc = 45mA
• High performance at military
temperature

Functional Description

=20ns

-tpD

Cypress PALC20 Series devices are highspeed electrically programmable and UVerasable logic devices produced in a proprietary N-well CMOS EPROM process.
These devices utilize a sum-of-products
(AND-OR) structure providing users with
the ability to program custom logic functions serving unique requirements.

-ts = 20ns
-tco

=15ns

-Icc = 70mA
• Commercial and military temperature
range

PALs are offered in 20-pin plastic and ceramic DIP, plastic SOJ, and ceramic LCC
packages. The ceramic package can be
equipped with an erasure window; when
exposed to UV light, the PAL is erased
and can then be reprogrammed.
Before programming, AND gates or produet terms are connected via EPROM cells
to both true and complement inputs. Programming an EPROM cell disconnects an
input term from a product term. Selective
programming of these cells allows a specific logic function to be implemented in a
PALC device. PALC devices are supplied
in four functional configurations designated 16R8, 16R6, 16R4, and 16L8.
These 8 devices have potentially 16 inputs
and 8 outputs configurable by the user.
Output configurations of 8 registers, 8
combinatorial, 6 registers and 2 combinatorial as well as 4 registers and 4 combinatorial are provided by the 4 functional
variations of the product family.

Logic Symbols and DIP and SOJ Pinouts
16R8

16R6

16R4

16L8

Vee

Vee

Vee

0
0
0
0
0
0
0

I/O
0
0
0
0
0
0

I/O
I/O

0

I/O

I/O
I/O
I/O
I/O
I/O
I/O

0
0
0
0

I/O
I/O

0

LCCPinouts

8

4
5
6
7

3 2 L1J 201~8

17
16
15
8
1.
910111213

___ ~o

80

0.
__ o:>0

0.
_ _ 0:::>::::.

o

o
o

o
o

4
5
6
7

8

3 2l1J

201ra o
17 o
16 o
15 o
14 o

4
5
6
7
8

910111213

e20·5

3 2l1J201~8
17
16
15
14
910111213

110

o
o
o

o

4
5
6
7

3 2 L1J201~8

17
16
15
8
14
910111213

-en-co

C20-6

;f'

PAL is a registered trademark of Advanced Micro Devices.

2-6

::::.

110
110
110
110
110
C20·8

PALCEl6V8

Flash Erasable,
Reprogrammable CMOS PAL ® Device
Features
• Active pull-up on data input pins
• Low power version (16V8L)
- 55 mA max. commercial (10, 15, 25
ns)
- 65 mA max. industrial (10, 15, 2S ns)
- 65 mA military (15 and 25 ns)
• Standard version has low power
- 90 mA max. commercial (10, 15, 25
ns)
-115 mA max. commercial (7 ns)
-130 mA max. military/industrial
(10, 15, 25 ns)
• CMOS Flash technology for electrical
erasability and reprogrammability
• PCI compliant

• User-programmable macrocell
- Output polarity control
- Individually selectable for registered or combinatorial operation
• Up to 16 input terms and 8 outputs
• QSOP packaging available
-7.5 ns com'l version
5 ns teo
5 ns t8
7.5 ns tpD
125-MHz state machine
-10 ns military/industrial versions
7 ns teo
10 ns ts
10 ns tPD
62-MHz state machine
• High reliability
- Proven Flash technology
-100% programming and functional
testing

Functional Description
The Cypress PALCE16V8 is a CMOS
Flash Electrical Erasable second-generation programmable array logic device. It
is implemented with the familiar sum-ofproduct (AND-OR) logic structure and
the programmable macrocell.
The PALCE16V8 is executed in a 20-pin
300-mil molded DIP, a 300-mil cerdip, a
20-lead square ceramic leadless chip carrier, a 20-lead square plastic leaded chip carrier and a 20-lead, quarter-size outline.
The device provides up to 16 inputs and 8
outputs. The PALCE16V8 can be electrically erased and reprogrammed. The programmable macrocell enables the device
to function as a superset to the familiar
20-pin PLDs such as 16L8, 16R8, 16R6,
and 16R4.

Logic Block Diagram (PDIP/CDIP)

1100

1/0,

Pin Configuration

1103

1/02

110.

DIP/QSOP
Top View

CLK/lo
11
12
13
14
15
Is

17
18

GND

110,

1/0.

PLCe/Lee
Top1;iew

~"

1/07

3 21 2019

I/Os

1/05
1/04
1/03
1/0 2
1/01
1/0 0
"ClE/ls

....

~-=d ~~

vee

1/06
1/05
1/04
1/0 3
1/0 2
lSV8-3

13
14
15
16
17
16V8-2

_a:JC~OO

a~:::,:::,

PAL is a registered trademark of Advanced Micro Devices.

2-7

1/0,

Vee

lSV8-1

•

PALCEl6V8
Selection Guide
tpDns
Com'l/Ind
Mil

Generic Part Number

PAt,CE1W$f5

",',

"")5,"

PALCEI6V8-7

7.5

PALCEI6V8-10
PALCE16V8-15

10
15
25

PALCE16V8-25
PALCEI6V8L-15
PALCEI6V8L- 25

(,,>,/',

tsns
Com'l/Ind
Mil

">~">

,i', ,

7
10

t!5

15

10
12
15
12

25

25

15

15

25

10
12
20
12
20

tcons
IccmA
Com'l/Ind
Mil
Com'l
Mil/lnd
'>4 <,
"(;\";'/ ",J~5;, '","
5
115
7
10
90
130

"'';''',!:,,'

10
12
10
12

10
12
12

90
90

130
130

55

20

55

65
65

Shaded area contams prehmmary mfonnation.

Functional Description (continued)
ThePALCE16V8 features 8 product terms per output and 32 input
terms into the AND array. The first product term in a macrocell
can be used either as an internal output enable control or as a data
product term.
There are a total of 18 architecture bits in the PALCE16V8 macrocell; two are global bits that apply to all macrocells and 16 that apply locally, two bits permacrocell. The architecture bits determine
whether the macrocell functions as a register or combinatorial with
inverting or noninverting output. The output enable control can
come from an external pin or internally from a product term. The
output can also be permanently enabled, functioning as a dedicated output or permanently disabled, functioning as a dedicated
input. Feedback paths are selectable from either the input/output
pin associated with the macrocell, the input/output pin associated
with an adjacent pin, or from the macrocell register itself.

Electronic Signature

An electronic signature word is provided in the PALCE16V8 that
consists of 64 bits of programmable memory that can contain userdefined data.
Security Bit
A security bit is provided that defeats the readback of the internal
programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE16V8 provides low-power operation through
the use of CMOS technology, and increased testability with Flash
reprogrammability.

Power-Up Reset

Product Term Disable

All registers in the PALCE16V8 power-up to a logic LOW for predictable system initialization. For each register, the associated output pin will be HIGH due to active-LOW outputs.

Product Term Disable (PID) fuses are included for each product
term. The PID fuses allow each product term to be individually
disabled.

Configuration Table
Cell Configuration

Devices Emulated

CGo

CGl

CLOx

0

1

0

Registered Output

Registered Med PALs

0
1

1
0

1
0

CombinatorialI/O
Combinatorial Output

1
1

0
1

1
1

Input
Combinatorial I/O

Registered Med PALs
Small PALs
Small PALs
16L8 only

2-8

$$ -.~

PALCEl6V8

~,CYPRESS

Macrocell
To

rr==~-----------------------------J1
OE

...----1-11 1

1

o
o

oX

Adjacent
Macrocell

1

Ol---~

0
1

1 0

ClOx

Ell

r-------.-~ 1 1

oX

>----..4t--1

D

Q

1-----1

1 0

Ot------~

ClK

o

CLl x

CG1 for pin 13 to 18
CGo for pin 12 and 19

ClOx

From
Adjacent
Pin
l6ve...

2-9

PALCEl6V8
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
>200 rnA

Latch-Up Current

Storage Temperature .................. -65°C to +150°C
Ambient Temperature with
Power Applied ....................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ....................... -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.5V to +7.0V
DC Input Voltage ....................... -O.5V to + 7.0V
Output Current into Outputs (WW) .............. 24 rnA
DC Programming Voltage ......................... 12.SV

Operating Range
Range
Commercial
Military[l]

Ambient
Temperature
O°C to +7SoC

5V±5%

-S5°C to +125°C

SV ±10%

Industrial

-40°C to +8SoC

5V ±1O%

Vee

Electrical Characteristics Over the Operating Rangd2]
Description

Parameter
VOH

VOL

Output mGH Voltage

Output LOW Voltage

Test Conditions

Min.

Vee = Min.,
VIN = Vrn or VIL

IOH= -3.2 rnA

Com'l

IOH = -2 rnA

MiVInd

Vee = Min.,
VIN = VIH or VIL

IOL = 24 rnA

Com'l

IOL= 12 rnA

MiVInd

Vrn
VIL[4]

Input HIGH Level

Guaranteed Input Logical mGHVoltage for Ail Inputs[3]

2.0

Input LOW Level

Guaranteed Input Logical LOW Voltage for AIl Inputs[3]

-0.5

IIH

Input or I/O HIGH Leakage 3.SV S VIN S Vee
Current

IIL[5]

Input or I/O LOW Leakage OV S VIN S VIN (Max.)
Current

Ise

Output Short Circuit Current Vee = Max., VOUT = 0.5V[6, 7]

Icc

Operating Power Supply
Current

,

5,7 ns
Vee = Max.,
VIL = Ov, VIH = 3V,
10,15,25 ns
Output Open,
f= 15 MHz
15L,
25Lns
(counter)
10,15,25 ns

Max.

-30
Com'l

Unit
V

2.4

0.5

V

0.8

V

10

!lA

-100

!lA

-150

rnA

115

rnA

90

rnA

55

rnA

V

MiVInd

130

rnA

15L,25Lns

Mil.

65

rnA

ISL,2SLns

Ind.

65

rnA

Capacitance[7]
Parameter
CIN
COUT

Description
Input Capacitance
Output Capacitance

Test Conditions
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V@f= 1 MHz

'JYp.

5
5

Unit
pF
pF

Endurance Characteristics[7]
Test Conditions
Normal Programming Conditions
Notes:
1. TA is the "instant on" case temperature.
2. See the last page ofthis specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. VldMin.) is equal to -3.0V for pulse durations less than 20 ns.

5.
6.
7.

2-10

The leakage current is due to the internal pull·up resistor on all pins.
Not more than one output should be tested at a time. Duration of the short
circuit should not be more than one second. VOUT = 0.5V has been cho·
sen to avoid test problems caused by tester ground degradatiOIL
Tested initially and after any design or process changes that may affect
these parameters.

PALCEl6V8
AC Test Loads and Waveforms
ALL INPUT PULSES

3.0V---90%
GND

16VB·5

fI
R1
OUTPUT o--+---_~!) TEST POINT
R2
16VB·6

Commercial
Specification

Sl

CL
SOpF

tpzx, tEA

Closed
Z,H: Open
Z,L: Closed

tpxz, tER

H,Z:Open
L, Z: Closed

SpF

tPD, teo

Rl
200Q

R2
390Q

Military
Rl
390Q

R2
7S0Q

Measured Output Value
l.SV
l.SV
H, Z: VOH - O.SV
L • Z: VOL + O.5V

2-11

PALCEl6V8
Commercial and Industrial Switching Characteristics[2]
16V8-7

16V8-S
Parameter
tpD

Description
Input to Output

16V8-10

16V8-1S

16V8-25

Min,

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

1

5

3

7.5

3

10

3

15

3

25

ns

Propa~ation

Delay ,9]

6

6

10

15

20

ns

1

5

6

10

15

20

ns

Input to Outp'ut
Enable Delay[7]

1

6

9

10

15

25

ns

tER

Input to Output
Disable Delay[7, 10]

1

5

9

10

15

25

ns

tco

Clock to
Delay[8,9]

1

4

12

ns

ts

Input or Feedbaok
Set-UpTime

3

tH

Input Hold Time

0

0

0

0

0

ns

tp

External Clock
Period (teo + ts)

7

10

14.5

22

27

ns

tWH

Clock Width
HIGH[7]

3

4

6

8

12

ns

tpzx

OE to Output
Enable

1

tpxz

OEtoOutput
Disable

tEA

Output

,

2

5

5

2

7

2

10

12

7.5

2
15

ns

,,',

,

, 3

tWL

Clock Width LOW[7]

4

6

8

12

ns

fMAX1

External Maximum
Frequency
(l/(tco + ts»[7, 11]

143

100

69

45.5

37

MHz

fMAX2

Data Path Maximum
Frequenw. ~l/(tWH
+ tWL»[ ,1 ]

166

125

83

62.5

41.6

MHz

fMAX3

Internal Feedback
Maximum
Frel!?uency (l/(tCF +
ts»[ , 13]

166

125

74

50

40

MHz

tCF

Register Clock to
Feedback Inputf7, 14]

tpR

Power-Up Reset
Timd7]

3
1

3
1

6
1

Shaded area contains preHmin ary intormatloD.
Notes:
8. Min. times are tested initially and after any design or process changes
that may affect these parameters.
9. This specification is guaranteed for all device outputs changing state in
a given access cycle.

10. This parameter is measured as the time after OE pin or internal disable
input disables or enables the output pin. This delay is measured to the
point at which a previous HIGH level has fallen to 0.5 volts below VOH
min. or a previous LOW level has risen to 0.5 volts above VOL max.
11. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can
operate.

8
1

10
1

ns
fts

12. This specification indicates the guaranteed maximum frequency at
which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate.
14. This parameter is calculated from the clock period at fMAX internal
(l/fMAX3) as measured (see Note 7 above) minus ts.

2-12

PALCEl6V8
Military Switching Characteristics[2]
16V8-10
Parameter

Description

tpD

Input to Output
Propagation Delay[B, 9]

tpzx

OE to Output Enable
OE to Output Disable
Input to Output Enable Delayl?]
Input to Output Disable DelayL', IUJ
Clock to Output Delayl~,~]

tpxz
tEA
tER
tco
ts
tH
tp

Input or Feedback Set-Up Time
Input Hold Time
External Clock Period (tco
Clock Width HIGHl'J
Clock Width LOWL?J

+ ts)

16V8-15

16V8-25

Min.

Max.

Min.

Max.

Min.

Max.

Unit

3

10

3

15

3

25

ns

10

15

20

ns

10
10

15

20
25

ns

15
15

10
2
10

7

2

10

2

12

15

0

0

0

17

22
8

27
12

25
12

ns
ns
ns
ns
ns

8

12

ns
ns
ns

fMAXI

External Maximum Frequency
(l/(tco + tS)!?,11]

58

45.5

37

MHz

fMAX2

Data Path Maximum Frequency
(l/(tWH + twL)[?' 12]

83

62.5

41.6

MHz

fMAX3

Internal Feedback Maximum
Frequency (1/(tCF + ts»[?' 13]

62.5

50

40

MHz

tCF

Register Clock to
Feedback Input[7, 14]

tpR

Power-Up Reset TimeL!J

tWH
tWL

6
6

8

6
1

1

10
1

ns
Ils

Switching Waveform
INPUTS, I/O, ---~....
REGISTERED
FEEDBACK _ _ _....l,.;V

CP

REGISTERED
OUTPUTS _ _ _ _ _ _....L.~

COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _ _

~~

16V8-7

Power-Up Reset Waveform
POWER
SUPPLY VOLTAGE

10%

-2~9~0~%~--------------------------VCC

------.....::Ir-

~------------- tpR------------~~

REGISTERED -------t-t-------~~__,.~~"'7"~~~~,..._--------­
ACTIVE LOW
OUTPUTS -------+-+------~~~'-~~~~~
CLOCK
16V8-8

2-13

PALCEl6V8

..........
ZrcYPRESS
Functional Logic Diagram for PALCEl6V8
. - - PIN NUMBERS

.r -

1

.~

0

3 4

7 8

11 12

15 16

19 20

PIN NUMBERS - - - - - .•

INPUTUNE
NUMBERS

PRODUCT LINE FIRST CELL NUMBERS

Vee

I~

I
23 24

2728

31..--J

00
32
64
96
128
192 160

~

I-

~

MC7
Cl1-2048
CLO 2120
PTD-2128
2135
MC6
CL1 2049
CLO 2121
PTD 2136
2143

256 288
320
384 352
448 416
480

3

.1-

:!:

544

640 608
704 672
736

A

4

.1-

~

:: soo
896 864
960 928
992

1-

5

~

1024

'088 '056
1152

1120
1184

12~6'248

.....

6

j-

~

I-r-

r-

Ctl-...Fal
....
-

I--

MC5 rCl1 2050
CLO 2122 fPTD 2144
2151

Wrl!Zl

rr-

.... I
~

I--

MC4
CL1 2051
CLO 2123
PTD 2152
2159

I--

MC3 fCl1 2052
CLO 2124 fPTD 2160
2167

I--

~

+~
..+ ~
=+
.. ~

r-

::,3,2
1408 1376

1472 '440
1504

.....

7

.1-

~

::~1568
'684 '632
1728
... 1760

.....

8

~

MC2
Cl1 2053
CLO-2125 fPTD 2168
2175

1+

MC1
CL1 2054
CLO 2126
PTD 2176
-2183
MCO
Cl1 2055
CLO 2127
PTD 2184
2191

::,824
'920 '888
'984 '952
2016

9

~

~~

:1-0

3 4

7 8

11 12

1516

19 20

23 24

2728

r-

-

~

31

I

11

USER ELECTRONIC SIGNATURE ROW
GLOBAL ARCH BITS

CGo=2192
CG,=2193
MSB LSB

MSB

2-14

LSB

16V8-9

PALCEl6V8
Ordering Infonnation
ICC
(rnA)

tpD
(ns)

ts
(ns)

tco
(ns)

Ordering Code

Package
Name

Package 'JYpe

Operating
Range

115

5

3

4

PALCE16V8-5JC

J61

20-Lead Plastic Leaded Chip Carrier

Commercial

115

7.5

5

5

PALCEI6V8-7JC

J61

20-Lead Plastic Leaded Chip Carrier

Commercial

PALCE16V8 -7PC

P5

20-Lead (300-Mil) Molded DIP

90

10

7.5

7

PALCEI6V8-lOQC

Q5

20-Lead Quarter-Size Outline

90

10

7.5

7

PALCEI6V8-10JC

J61

20-Lead Plastic Leaded Chip Carrier

PALCEI6V8-lOPC

P5

20-Lead (300-Mil) Molded DIP

PALCEI6V8-lOJI

J61

20-Lead Plastic Leaded Chip Carrier

PALCEI6V8-lOPI

P5

20-Lead (300-Mil) Molded DIP

130
130
90
130
130
90
130
130

10
10
15
15
15
25
25
25

7.5
10
12
12
12
15
15
15

7
7
10
10
10
12
12
12

PALCEI6V8-lODMB

D6

20-Lead (300-Mil) CerDIP

PALCEI6V8-lOLMB

L61

20-Pin Square Leadless Chip Carrier

PALCEI6V8-15JC

J61

20-Lead Plastic Leaded Chip Carrier

PALCEI6V8-15PC

P5

20-Lead (300-Mil) Molded DIP

PALCEI6V8-15JI

J61

20-Lead Plastic Leaded Chip Carrier

PALCEI6V8-15PI

P5

20-Lead (300-Mil) Molded DIP

PALCEI6V8-15DMB

D6

20-Lead (300-Mil) CerDIP

PALCEI6V8-15LMB

L61

20-Pin Square Leadless Chip Carrier

PALCEI6V8-25JC

J61

20-Lead Plastic Leaded Chip Carrier

PALCEI6V8-25PC

P5

20-Lead (3OO-Mil) Molded DIP

PALCEI6V8-25JI

J61

20-Lead Plastic Leaded Chip Carrier

PALCEI6V8-25PI

P5

20-Lead (3OO-Mil) Molded DIP

PALCEI6V8- 25DMB

D6

20-Lead (300-Mil) CerDIP

PALCEI6V8- 25LMB

L61

20-Pin Square Leadless Chip Carrier

Shaded area eontams prelImmary mformatlOn.

2-15

Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military

fI

#-.~

PALCEl6V8

..",...., CYPRESS

Ordering Information (continued)

55

15

12

10

PALCEI6V8L-15JC
PALCEI6V8L-15PC

J61
P5
Q5
J61

20-Lead Plastic Leaded Chip Carrier
20-Lead (300-Mil) Molded DIP
20-Lead Quarter-Size Outline
20-Lead Plastic Leaded Chip Carrier

P5
Q5
D6
L61
J61
P5
Q5

2O-Lead (300-Mil) Molded DIP
20-Lead Quarter-Size Outline
20-Lead (300-Mil) CerDIP
20-Pin Square Leadless Chip Carrier
20-Lead Plastic Leaded Chip earrier
20-Lead (300-Mil) Molded DIP
20-Lead Quarter-Size Outline

J61
P5
Q5

20-Lead Plastic Leaded Chip Carrier
20-Lead (300-Mil) Molded DIP
20-Lead Quarter-Size Outline

Industrial

D6
L61

20-Lead (300-Mil) CerDIP
20-Pin Square Leadless Chip Carrier

Military

~~~~~~~--~~--~~~~~~~~-=~--~

Parameter
VOH
VOL
VIH
VIL
IIX
Ioz
Icc

Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

Switching Characteristics
Parameter

Subgroups

tpD

9,10,11
9,10,11
9,10,11
9,10,11

teo
ts
tH

Document #: 38-00364-C

2-16

Commercial

Industrial

Military
Commercial

PALCE20V8

Flash Erasable,
Reprogrammable CMOS PAL ® Device
Features
• Active pull-up ou data input pins
• Low power version (20V8L)
- 55 rnA max. commercial (15,25 ns)
- 65 rnA max. military/industrial
(15,25 ns)
• Standard version has low power
- 90 rnA max. commercial
(15,25 ns)

• User-programmable macrocell
- Output polarity control
- Individually selectable for registered or combinatorial operation
• QSOP package available
-10, 15, and 25 ns com'l version
-15, and 25 ns military/industrial
versions
• High reliability
- Proven Flash technology
-100% programming and functional
testing

-115 rnA max. commercial (10 ns)
-130 rnA max. military/industrial
(15,25 ns)

Functional Description

• CMOS Flash technology for electrical
erasahility and reprogrammability

The Cypress PALCE20V8 is a CMOS
Flash Erasable second-generation pro-

grammable array logic device. It is implemented with the familiar sum-of-product
(AND-OR) logic structure and the programmable macrocell.
The PALCE20V8 is executed in a 24-pin
300-mil molded DIP, a 300-mil cerdip, a
28-lead square ceramic leadless chip carrier, a 28-lead square plasticleaded chip carrier, and a 24-lead quarter size outline.
The device provides up to 20 inputs and 8
outputs. The PALCE20V8 can be electrically erased and reprogrammed. The programmable macrocell enables the device
to function as a superset to the familiar
24-pin PLDs such as 20LS, 20R8, 20R6,
20R4.

Logic Block Diagram (PDIP/CDIP/QSOP)

Pin Configuration
PLCC/LCC
'ThpView

DIP/QSOP
Top View
ClK/lo

1,
12
13
I,
I.
I.
I,
I.
I.
110

GND

o

_"'.r~ !;l ~ ~g

Vee
113
I/~

I/O.
110.

I,

110,
I/O,

I.
NC

1/02
110,
1100

I,
I,
18

I,

110,
110.
I/O.
NC
I/O,
110 2

110 ,

112

00111

2QVB·3

2QVB·2

PAL is a registered trademark of Advanced Micro Devices, Inc.

2-17

~ -'i~

PALCE20V8

w,ICYPRESS
Selection Guide
tpDns
Mil
Com'I/lnd
5

Generic Part Number
PALCE20V8-5
PALCE20V8-7
PALCE20V8-1O
PALCE20V8 -15
PALCE20V8-25
PALCE20V8L- 15
PALCE20V8L- 25

7.5
10
15
25
15
25

10
15
25
15
25

ts ns
Mil
Com'I/lnd

3
7
10
12
15
12
15

10
12
20
12
20

teo ns
Com'l/lnd
4
5
7
10
12
10
12

Mil

lee mA
Com'l
MiI/lnd

115
10
12
20
12
20

115
115
90
90
55
55

130
130
130
65
65

Shaded area contams prehmmary mformatlOn.

Functional Description (continued)
The PALCE20V8 features 8 product terms per output and 40 input
terms into the AND array. The first product term in a macrocell
can be used either as an internal output enable control or as a data
product term.
There are a total of 18 architecture bits in the PALCE20V8 macrocell; two are global bits that apply to all macrocells and 16 that apply locally, two bits per macrocell. The architecture bits determine
whether the macrocell functions as a register or combinatorial with
inverting or noninverting output. The output enable control can
come from an external pin or internally from a product term. The
output can also be permanently enabled, functioning as a dedicated output or permanently disabled, functioning as a dedicated
input. Feedback paths are selectable from either the input/output
pin associated with the macrocell, the input/output pin associated
with an adjacent pin, or from the macrocell register itself.
Power-Up Reset
All registers in the PALCE20V8 power-up to a logic LOW for predictable system initialization. Foreach register, the associated output pin will be HIGH due to active-LOW outputs.
Electronic Signature
An electronic signature word is provided in the PALCE20V8 that
consists of 64 bits of programmable memory that can contain userdefined data.

Security Bit
A security bit is provided that defeats the readback of the internal
programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE20V8 provides low-power operation through
the use of CMOS technology, and increased testability with Flash
reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each product
term. The PTD fuses allow each product term to be individually
disabled.
Input and I/O Pin Pull-Ups
The PALCE20V8 input and I/O pins have built-in active pull-ups
that will float unused inputs and I/Os to an active HIGH state (IogicaI1). All unused inputs and three-stated I/O pins should be connected to another active input, Vee, or Ground to improve noise
immunity and reduce Icc.

Configuration Table
CGo

CGl

CLOx

0
0
1
1
1

1
1
0
0
1

0

1
0
1
1

Cell Configuration
Registered Output
CombinatorialI/O
Combinatorial Output
Input
CombinatorialI/O

2-18

Devices Emulated
Registered Med PALs
Registered Med PALs
Small PALs
Small PALs
20LSonly

==-- -,,~

PALCE20V8

_'CYPRESS
Macrocell
OE

1 1

Vee

oX

11
101---...,
o0

To
Adjacent
Macrocell

o1

1 0

CLOx
~----_--l1

1

OX 1-----1

III

01-----110

01-------.

I-----From
Adjacent
Pin

CGl for pin 16 to 21 (DIP)
CGo for pin 15 and 22 (DIP)

20V8-4

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Thmperature .................. -65°C to + 150°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Volt~ge to Ground Potential
(Pm 24 to Pm 12) ....................... -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.5V to + 7.0V
DC Input Voltage ....................... -O.5V to + 7.0V
Output Current into Outputs (LOW) .............. 24 rnA
DC Programming Voltage ......................... 12.5V

>200mA

Latch-Up Current

Operating Range
Range
Commercial
Industrial
Military[lj

Note:
1. TA is the "instant on" case temperature.

2-19

Ambient
Temperature
O°C to +75°C

Vee
5V±5%

-40°C to +85°C

5V ±1O%

-55°C to +125°C

5V ±1O%

-.,~

PALCE20V8

~;CYPRESS
Electrical Characteristics Over the Operating Rangel2]
Parameter
VOH

Description
Output HIGH Voltage

Test Conditions

Min.

Vee = Min.,
VIN = Vm or VIL

IOH = -3.2 rnA

Com'l

IOH = -2 rnA

Mil/Ind

IOL = 24 rnA

Com'l

IOL = 12 rnA

Mil/Ind

VOL

Output LOW Voltage

Vee = Min.,
VIN = Vm or VIL

Vm

Input HIGH Level

Guaranteed Input Logical HIGH Voltage for All Inputs[3]

2.0

VIL[4]

Input LOW Level

Guaranteed Input Logical LOW Voltage for All Inputs[3]

-0.5

1m

Input or I/O mGH Leakage 3.5V ~ VIN ~ Vee
Current

IIL[S]

Input or I/O LOW Leakage OV ~ VIN ~ VIN (Max.)
Current

Ise

Output Short Circuit Current Vee = Max., VOUT = 0.5V[6, 7]

Icc

Operating Power Supply
Current

Vee = Max.,
5,7,10 ns
VIL = Ov, Vm = 3V,
15,25 ns
Output Open,
f=15MHz
15L,25Lns
(counter)
10,15,25 ns
15L,25Lns

Max.

2.4

Unit
V

0.5

V

0.8

V

10

ItA

-100

ItA

-150

rnA

115

rnA

90

rnA

55

rnA

Mil/Ind

130

rnA

Mil/Ind

65

rnA

-30
Com'l

V

Capacitance[7]
Parameter
CIN
COUT

Description
Input Capacitance
Output Capacitance

Test Conditions
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz

1YP.
5
5

Unit
pF
pF

Endurance Characteristics[7]
Description
Minimum Reprogramming Cycles

Test Conditions
Normal Programming Conditions

Notes:
2.

See the last page ofthis specification for Group A subgroup testing in-

6.

formation.
3.
4.
5.

These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
VIL (Min.) is equal to -3.0V for pulse durations less than 20 ns.
The leakage current is due to the internal pull-up resistor on all pins.

7.

2-20

Not more than one output should be tested at a time. Duration of the short
circuit should not be more than one second. Your = 0.5V has been chosen to avoid test problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect
these parameters.

=:..

PALCE20V8

?cYPRESS

AC Test Loads and Waveforms
ALL INPUT PULSES

3.0V--90%
GND

20V8-5

fI
R1
OUTPUT

o--t---t----;i!)

TEST POINT

R2
20V8-6

Commercial
Specification

SI

tpD, teo

Closed

tpzx, tEA

Z. H: Open
Z. L: Closed

tpxz, tER

H.Z: Open
L. Z: Closed

Military

CL

Rl

R2

Rl

R2

Measured Output Value

SOpF

200Q

390Q

390Q

750Q

l.SV
l.SV

H. Z: VOH - O.SV
L • Z: VOL + O.5V

5pF

2-21

PALCE20V8
Commercial and Industrial Switching Characteristics[2]
I. 2OV8'c~;.· .• • JOVll;.;7
Parameter
tpD

Description
Input to Output
Propagation Delay[8]

Mm~

>1~

...
.... ...

l\fai(; Mbi.

5

.. ~'

5

.
.

:

.

20V8-10
Max.

Min.

Max.

Min.

Max.

Unit

7.5

1

10

1

15

1

25

ns

6

10

15

20

ns

6
9.

10

15

20

ns

10

15

25

ns

9· •

10

15

25

ns

12

ns

OE to Output Enable

tpxz

OE to Output Disable

tEA

Input to Outp'ut
Enable Delay[7]

tER

Input to Output
Disable Delay[7.9]

tco

Clock to Output Delay[8]

1

ts

Input or Feedback
Set-Up Time

3

tH

Input Hold Time

0

0

0

tp

External Clock Period
(teo + ts)

7

12

17

tWH

Clock Width HIGH[7]

3

5

8

tWL

Clock Width LOW[7]

3

5 ....

8

fMAX!

External Maximum
Frequency (l!(tco + tS»[7. 10]

fMAX2

Data Path Maximum
Frequency
(l!(tWH + tWL»)P, 11]

166.6

fMAX3

Internal Feedback Maximum
Frequency (l!(tcF + tS»)p·12]

166;6

tCF

Register Clock to
Feedback Inputl7• 13]

Power-Up Reset Timel7J
tpR
SnaOeO area contams prel1mmary mtormatlOn.

••

.. :

.. 6

6
4

...

5

1

1

7

143

...

1

10

1
15

ns

0

0

ns

22

27

ns

8

12

ns

8

12

ns

58

45.5

37

MHz

62.5

62.5

41.6

MHz

62.5

50

40

MHz

12

.

•

100

7

10

83

20V8-25

Min.

tpzx

5·.

20V8-15

Max.

I
•

.
100
3

1

3

6
..

1

1

8
1

10
1

ns
ItS

Notes:

8.

Min. times are tested initially and after any design or process changes
that may affect these parameters.
9. This parameter is measured as the time after OE pin or internal disable
input disables or enables the output pin. This delay is measured to the
point at which a previous HIGH level has fallen to 0.5 volts below VOH
min. or a previous LOW level has risen to 0.5 volts above VOL max.
10. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can
operate.

11. This specification indicates the guaranteed maximum frequency at
which the device can operate in data path mode.
12. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate.
13. This parameter is calculated from the clock period at fMAX internal
(1/fMAX3) as measured (see Note 7 above) minus ts.

2-22

PALCE20V8
Military Switching Characteristics[2]
20V8-10
Parameter

Description

20V8-25

20V8-15

Min.

Max.

Min.

Max.

Min.

Max.

Unit

1

10

1

15

1

25

ns

tpD

Input to Output
Propagation Delay[8]

tpzx

OE to Output Enable

10

15

20

ns

tpxz

10

15

20

ns

tEA

OE to Output Disable
Input to Output Enable DelayLI]

10

15

25

ns

tER

Input to Output Disable Delayl/, Y]

10

15

25

ns

tco

Clock to Output Delayl8J

1

20

ns

ts

Input or Feedback Set-Up Time

10

12

20

ns

tH
tp

Input Hold Time

0

0

0

ns

20

24

40

ns

8
8

10
10

15

ns

15

ns

50

41.7

25

MHz

10

1

12

1

tWH

External Clock Period (teo + ts)
Clock Width HlGHL7]

tWL

Clock Width LOWI7]

fMAXI

External Maximum Frequency
(lI(tco + tS)[7, 10]

fMAX2

Data Path Maximum Frequency
(lI(tWH + twL)[7, 11]

62.5

50

33.3

MHz

fMAX3

Internal Feedback Maximum
Frequency (l/(tCF + tS»[7, 12]

62.5

50

33.3

MHz

tCF

Register Clock to
Feedback Input[7, 13]

Power-Up Reset Timel7]
tpR
snaaea area contams pre Immary mlormatlon.

1

1

10

8

6

1

ns
I's

Switching Waveform
INPUTS, I/O. ---~
REGISTERED
FEEDBACK _ _ _....L.:.V

CP
tEA. tpZX[10]

REGISTERED
OUTPUTS _ _ _ _ _ _.......U(.v

COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _ _

~~

20V8-7

Power-Up Reset Waveform
POWER
SUPPLY VOLTAGE

10%t

Vee

90%
tpR

REGISTERED
ACTIVE LOW
OUTPUTS

XXXXXX

....!.L.

~

CLOCK
tpR MAX = 1 /lS

2-23

I'
_ t WL -

20VB·B

fI

~YPRESS

PALCE20V8

Functional Logic Diagram for PALCE20V8
. - PIN NUMBERS DIP (PLCC) PACKAGE

1 (2

"

PIN NUMBERS DIP (PLCC) PACKAGE

0

)D---Cl=

4

12

8

16

20

24

28

32

32

2 (3

0

~

MC6
CL1 2561
CLO 2633

~

MC5
CL1 2562
CLO 2634

~

MC4
CL1 2563
CLO 2635

~

MC3
CL1 2564
CLO 2636

~

MC2
CL1 2565
CLO 2637

~

MC1
CL1 =2566
CLO=2638

~

MCO
CL1 =2567
CLO = 2639

r-----Jv

3 (4)
320

600

4 (5)
640

920

5 (6)
960

1240

6(7)
1280

15~0

7 (9
1600

1880

)0 ..

1920

2200

9 (1 1)
2240

23 (27)

MC7
CL1 2560
CLO 2632

280

8 (10

------,t

~
~CGo

PTD

I

25~O

10 (12)

I--

b:J.

11 (13)

0

2568
BYTE 7

t t

2569 ..

I

BYTE 6 .

... 2630
. .. BYTE 1

21 (25)

20 (24)

19 (23)

18 (21)

17 (20)

16 (19)

15 (18)

14 (17)

CGO~
'"

ELECTRONIC SIGNATURE ROW

22 (26)

13 (16)

2631
BYTE 0

I

CGO=2704

CG 1 =2705

20V8-9

MSB LSB

2-24

PALCE20V8
Ordering Information for PALCE20V8
Package
Name

Operating
Range

tpD
(ns)

ts
(ns)

teo
(ns)

115

5

3

4

PALCE20V8-5JC

J64

28-Lead Plastic Leaded Chip Carrier

Commercial

115

7.5

7

5

PALCE20V8-7JC

J64

28-Lead Plastic Leaded Chip Carrier

Commercial

PALCE20V8-7PC

P13

24-Lead (300-Mil) Molded DIP

ICC

(mA)

115
130
130

10
10
10

10
10
10

7
10
10

90

15

12

10

130

15

12

12

130
90
130
130

15
25
25
25

12
15
20
20

12
12
20
20

Ordering Code

Package 'JYpe

PALCE20V8-10JC

J64

28-Lead Plastic Leaded Chip Carrier

PALCE20V8-lOPC

P13

24-Lead (300-Mil) Molded DIP

PALCE20V8-lOJI

J64

28-Lead Plastic Leaded Chip Carrier

PALCE20V8-lOPI

P13

24-Lead (300-Mil) Molded DIP

PALCE20V8-lODMB

D14

24-Lead (300-Mil) CerDIP

PALCE20V8-lOLMB

L64

28-Pin Square Leadless Chip Carrier

PALCE20V8-15JC

J64

28-Lead Plastic Leaded Chip Carrier

PALCE20V8-15PC

P13

24-Lead (300-Mil) Molded DIP

PALCE20V8-15JI

J64

28-Lead Plastic Leaded Chip Carrier

PALCE20V8-15PI

P13

24-Lead (300-Mil) Molded DIP

PALCE20V8-15DMB

D14

24-Lead (300-Mil) CerDIP

PALCE20V8-15LMB

L64

28-Pin Square Leadless Chip Carrier

PALCE20V8-25JC

J64

28-Lead Plastic Leaded Chip Carrier

PALCE20V8-25PC

P13

24-Lead (300-Mil) Molded DIP

PALCE20V8-25JI

J64

28-Lead Plastic Leaded Chip Carrier

PALCE20V8-25PI

P13

24-Lead (300-Mil) Molded DIP

PALCE20V8-25DMB

D14

24-Lead (300-Mil) CerDIP

PALCE20V8-25LMB

L64

28-Pin Square Leadless Chip Carrier

Shaded area contains preliminary information.

2-25

Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military

fI

--=.
::::aw

PALCE20V8

rcYPRESS

Ordering Information for PALCE20V8L

teo

(mA)

ICC

tpD
(ns)

ts
(ns)

(ns)

55

15

12

10

15

65

65

15

55

25

65

25

25

65

12

12
15

20

20

12

12
12

20

20

Ordering Code

Package
Name

PALCE20Y8L-15JC

J64

28-Lead Plastic Leaded Chip Carrier

PALCE20Y8L-15PC

24-Lead (300-Mil) Molded DIP

PALCE20Y8L-15QC

P13
Q13

PALCE20Y8L-15JI

J64

28-Lead Plastic Leaded Chip Carrier

PALCE20Y8L-15PI

24-Lead (300-Mil) Molded DIP

PALCE20Y8L-15QI

P13
Q13

PALCE20Y8L-15DMB

D14

24-Lead (300-Mil) CerDIP

PALCE20Y8L-15LMB

L64

28-Pin Square Leadless Chip Carrier

J64

28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP

PALCE20Y8L-25QC

P13
Q13

PALCE20Y8L- 25JI

J64

28-Lead Plastic Leaded Chip Carrier

PALCE20Y8L- 25PI

24-Lead (300-Mil) Molded DIP

PALCE20Y8L- 25QI

P13
Q13

PALCE20Y8L-25DMB

D14

24-Lead (300-Mil) CerDIP

PALCE20Y8L-25LMB

L64

28-Pin Square Leadless Chip Carrier

Parameter

Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

Switching Characteristics
Parameter

Subgroups

tpD

9,10,11
9,10,11
9,10,11
9,10,11

Document #: 38-00367-C

2-26

Commercial

Industrial

24-Lead Quarter-Size Outline

PALCE20Y8L-25PC

YOH
VOL
YIH
YIL
Irx
loz
Icc

Operating
Range

24-Lead Quarter-Size Outline

PALCE20Y8L- 25JC

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics

teo
ts
tH

Package 'JYpe

Military
Commercial

24-Lead Quarter-Size Outline
Industrial

24-Lead Quarter-Size Outline
Military

PLDC20G lOB/PLDC20GIO

CMOS Generic 24-Pin
Reprogrammable Logic Device
Features
• Fast
- Commercial: tpD = 15 ns, teo = 10
ns, ts = 12 ns
- Military: tpD = 20 ns, teo = 15 ns,
ts=ISns
• Lowpower
- Icc max.: 70 mA, commercial
-Icc max.: 100 mA, military
• Commercial and military temperature
range
• User-programmable output cells
- Selectable for registered or combinatorial operation
- Output polarity control
- Output enable source selectable
from pin 13 or product term

• Generic architecture to replace standard logic functions including: 20LlO,
20L8, 20R8, 20R6, 20R4, 12LlO, 14L8,
16L6, 18L4, 20L2, and 20V8
• Eight product terms and one OE
product term per output
• CMOS EPROM technology for
reprogrammability
• Highly reliable
- Uses proven EPROM technology
- Fully AC and DC tested
- Security feature prevents logic pattern duplication

- ± 10% power supply voltage and
higher noise immunity

Functional Description
Cypress PLD devices are high-speed electricallyprogrammable logic devices. These
devices utilize the sum-of-products (ANDOR) structure providing users the ability to
program custom logicfunctions for unique
requirements.
In an unprogrammed state the AND gates
are connected via EPROM cells to both
the true and complement of every input.
By selectively programming the EPROM
cells, AND gates may be connected to either the true or complement or disconnected from both true and complement inputs.
Cypress PLDC20GIO uses an advanced
O.S-micron CMOS technology and a proven EPROM cell as the programmable element. This technology and the inherent

Logic Block Diagram

I/O,

liD,

110.

IJOE

liD.

I/O,

I/o.

110 3

1102

1/0,

Vee

1/0 0

20010·1

Pin Configurations
LCC
Thp View
_ _ 0:> :::-::::-

ii: 880

---~~g'g

4 3 2~1!282726

4 3 2 1 282726

()
Z

25
24

I
NC

9
10
11

JEDEC PLCC[1]
Top View

STDPLCC
ThpView

PLDC20G10
PLDC20G10B

23
22
21
20
19

NC

110 2
1103
I/O.
I/O,
I/0.
11O,

12131415161718

--$~~~~

NC
I
I
NC
I
I
NC

--~~~g'g
4 3 2 1 282726

110 2
1/°3
110.
11O,
110.
11O,

PLDC20G10
PLDC20G10B

I
NC

CG7C323-A
CG7C323B-A

---$~~~

Note:
1. The CG7C323 is the PLDC20GlO packaged in the JEDEC-eompatible 28-pin PLCC pinout. Pin function and pin order is identical for

2-27

NC

11O,
110.
I/O,

NC

20G10·2

1/°2
1103
110.

20G10-4

- - ~ ~~ ~ g

20G1Q-3

both PLCC pinouts. The difference is in the location of the "no connect" or NC pins.

II

PLDC20GIOBIPLDC20GIO
Selection Guide
Icc (mA)

Generic
Part Number
2001OB-15
20GlOB-20
2001OB-25
20GlO-25
20010-30
20010-35
20010-40

tpD (ns)

ts (ns)

Com/Ind
70

Mil

Com/lnd
15

Mil

Com/Ind
12

Mil

70

100
100

20

20

12

15

55

30

80

Functional Description (continued)

20GIO Functional Description
The PLDC20GI0 is a generic 24-pin device that can be programmed to logic functions that include but are not limited to:
20LlO, 20LS, 20R8, 20R6, 20R4, 12LlO, 14LS, 16L6, 18L4, 20L2,
and 20V8. Thus, the PWC20GlO provides significant design, inventoryandprogrammingflexibilityoverdedicated24-pindevices.
It is executed in a 24-pin 300-mil molded DIP and a 300-mil windowed cerDIP. It provides up to 22 inputs and 10 outputs. When
the windowed cerDIP is exposed to UV light, the 20G10 is erased
and then can be reprogrammed.
The programmable output cell provides the capability of defining
the architecture of each output individually. Each of the 10 output
cells may be configured with registered or combinatorial outputs,
active HIGH or active LOW outputs, and product term or Pin 13
generated output enables. Three architecture bits determine the
configurations as shown in the Configuration Thble and in Figures
1 through 8. A total of eight different confignrations are possible,

35

25

with the two most common shown inFigure 3 and Figure 5. The default or unprogrammed state is registered/active/LOW/Pin 11 OE.
The entire programmable output cell is shown in the next section.
The architecture bit 'Cl' controls the registered/combinatorial option. In either combinatorial or registered configuration, the output can serve as an I/O pin, or if the output is disabled, as an input
only. Any unused inputs should be tied to ground. In either registered or combinatorial configuration, the output of the register is
fed back to the array. This allows the creation of control-state machines by providing the next state. The register is clocked by the signal from Pin 1. The register is initialized on power up to Q output
LOW and Q output HIGH.
In both the combinatorial and registered configurations, the
source of the output enable signal can be individually chosen with
architecture bit 'C2'. The OE signal may be generated within the
array, or from the external OE (Pin 13). The Pin 13 allows direct
control of the outputs, hence having faster enable/disable times.
Each output cell can be configured for output polarity. The output
can be either active HIGH or active LOW. This option is controlled
by architecture bit 'CO'.
Along with this increase in functional density, the Cypress
PWC20GI0 provides lower-power operation through the use of
CMOS technology and increased testabilitywith aregisterpreload
feature.

Programmable Output Cell
r-------------------~

-i ~~~~J

r--!-_..:O.::.E.:..;PRc:;O:;:D:;:U.::.CT:..T:.:E::,:RM:::..-_ _ _ _ _ _ _ _

MUX

OUTPUT

I----..:OO=--t s~~r

I-I---t--H

1-t---..:0:..;1-1 c, Co

INPUT!
FEED·
BACK
~X

c,

20
25

40

advantage of being able to program and erase each cell enhances
the reliability and testability of the circuit. This reduces the burden
on the customer to test and to handle rejects.
A preload function allows the registered outputs to be preset to any
pattern during testing. Preload is important for testing the functionality of the Cypress PLD device.

15
15

20
30

35

Mil

15

15

80

12

18

25
25

55

teo (ns)
Com/lnd
10

---+--~---------~I-+--il-~

~ ::::::+=::::::::::::::::::::::~~

PIN 13

2-28

I
I

_ _ _ .1

2OG1O·5

PLDC20G10B/PLDC20G10
Configuration Table
Figure

Cz

Cl

Co

1

0

0

0

Product Thrm OE/Registered/Active LOW

Configuration

2

0

0

1

Product Thrm OE/Registered/Active HIGH

5

0

1

0

Product Term OE/Combinatorial/Active LOW

6

0

1

1

Product Term OE/CombinatoriaVActive HIGH

3

1

0

0

Pin 13 OE/Registered/Active LOW

4

1

0

1

Pin 13 OE/Registered/Active HIGH

7

1

1

0

Pin 13 OE/CombinatoriaVActive LOW

8

1

1

1

Pin 13 OE/CombinatoriaVActive HIGH

fI

Registered Output Configurations
C2 = 0
Cl =0
Co = 1

C2 = 0
Cl = 0

Co = 0

>-----10

Q

20010-6

20G10-7

Figure 1. Product Term OE/Active LOW

Figure 2. Product Term OE/Active HIGH

o

C2 = 1
Cl = 0
Co = 0

Q

>-----10

20010-8

C2 = 1
Cl = 0
Co = 1

Q

20G10-9

Figure 3. Pin 13 OE{Active LOW

Figure 4. Pin 13 OE/Active HIGH

Combinatorial Output Configurations[2]

=0
=1
Co = 0

C2 = 0
Cl = 1
Co = 1

C2
Cl

20010-10

20G10-11

Figure 5. Product Term OE/Active LOW

Figure 6. Product Term OE/Active HIGH

=1
=1
Co = 0

C2 = 1
Cl = 1
Co = 1

C2
Cl

20G10-12

20G10·13

PIN 13

PIN 13

Figure 7. Pin 13 OE/Active LOW

Figure 8. Pin 13 OE/Active mGH

Note:
2. BidirectionalI/O configurations are possible only when the combinatorial output option is selected

2-29

PLDC20GIOB/PLDC20GIO
Maximum Ratings
(Above which the usefullife maybe impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to + 150°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential ........ -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.SV to +7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Output Current into Outputs (LOW) .............. 16 rnA
DC Programming Voltage
PLDC20GlOB and CG7C323B-A ................ 13.0V
PLDC20GlO and CG7C323-A ................... 14.0V

Latch-Up Current ........................... >200 rnA
Static Discharge Voltage ......................... >500V
(per MIL-STD-SS3, Method SOlS)

Operating Range
Ambient
Temperature

Range
Commercial

O°C to +75°C

Vee
5V ±1O%

MilitaryL3J

-55°C to + 125°C

5V ±1O%

Industrial

-40°C to +S5°C

5V ±1O%

Electrical Characteristics Over the Operating Range (Unless Otherwise Noted)[4]
Parameter
VOR

Description
Output HIGH Voltage
Output LOW Voltage

VOL

Min.

Test Conditions
Vee = Min.,
VIN = VIH or VIL

lOR = -3.2 rnA

Com'l/Ind

lOR = -2 rnA

Military

Vee = Min.,
VIN = VIH or VIL

IOL = 24 rnA

Com'l/Ind

IOL= 12 rnA

Military

Input HIGH Level

Guaranteed Input Logical HIGH Voltage for All InputsL~J

VIL

Input LOW Level

Guaranteed Input Logical LOW Voltage for All InputsPJ

IIX

Input Leakage Current

V

2.0

V
V

+10
- 90

!lA
rnA

Com'l/Ind-15, -20

70

rnA

Com'l/Ind-25, -35

55

rnA

Military-20, -25

100

rnA

Military-30, -40

SO

rnA

100

!lA

Ise
lee

Power Supply Current

Output Leakage Current

V

O.S

VSSSVINSVCC
Output Short Circuit Current Vee = Max., VOUT = 0.5VLb,IJ

loz

Unit

0.5

VIH

OsVINSVee
Vee = Max.,
lOUT = ornA
Unprogrammed Device

Max.

2.4

-10

-100

Vee - Max., VSSS VOUTS Vee

Capacitance[7]
CIN

Parameter

Description
Input Capacitance

COUT

Output Capacitance

Notes:
3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.

Test Conditions
TA = 2SoC, f = 1 MHz

Max.
10

Unit
pF

VIN - 2.0V; Vee - 5.0V

10

pF

6.

7.

2-30

Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. V OUT = O.5V has
been chosen to avoid test problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect
these parameters.

-

-~

PLDC20G10BIPLDC20G10

~7CYPRESS

AC Test Loads and Waveforms (Commercial)
R1238Q

R1238Q

5v~(319QMIL)

5V:F1(319QMIL)

OUTPUT

OUTPUT

INCLUDING
JIG AND
SCOPE

I

50 pF

R2170Q
(236Q MIL)
INCLUDING
JIG AND
SCOPE

(a)

Equivalent to: THEvENIN EQUIVALENT (Commercial)
99Q
OUTPUT o---------wv--- 2.08V = Vthc

I

R2170Q
(236Q MIL)

5 pF

-=

-=

20GI().14

(b)

Equivalent to: THEvENIN EQUIVALENT (Milnary/lndustrial)
136Q
OUTPUT C>-----'IMr---O 2.13V = Vthm

20GIO·15

2OGIO·16

Switching Characteristics Over Operating Rangel3•8. 9]
Commercial

B-15
Parameter

Description

B-20

-25

-35

Min. Max. Min. Max. Min. Max. Min. Max.

Unit

tpD

Input or Feedback to Non-Registered Output

15

20

25

35

ns

tEA

Input to Output Enable

15

20

25

35

ns

tER

Input to Output Disable

15

20

25

35

ns

tpzx

Pin 11 to Output Enable

12

15

20

25

ns

tpxz

Pin 11 to Output Disable

12

15

20

25

ns

teo

Clock to Output

10

12

15

25

ns

ts

Input or Feedback Set-Up Time

12

12

15

30

ns

tH

Hold Time

0

0

0

0

ns

tp[lO]

Clock Period

22

24

30

55

ns

tWH

Clock High Time

8

10

12

17

ns

tWL

Clock Low Time

8

10

12

17

ns

fMAX[ll]

Maximum Frequency

45.4

41.6

33.3

18.1

MHz

Notes:
8. Part (a) of ACTest Loads and Waveforms used for all parameters except tER, tpzx, and tpxz. Part (b) of AC Test Loads and Waveforms
used for tER, tpzx, and tpxz.
9. The parameters tER and tpxz are measured as the delay from the input
disable logic threshold transition to VOH - O.5V for an enabled HIGH
output or VOL + O.SV for an enabled LOW input.
10. til minimum guaranteed clock period is that guaranteed for state machine operation and is calculated from tp = ts + teo. The minimum

guaranteed period for registered data path operation (no feedback)
can be calculated as the greater of (tWH + twLl or (ts + tH)'
11. fMAX, minimum guaranteed operating frequency, is that guaranteed
for state machine operation and is calculated from fMAX = 1/(ts +
teo). The minimum guaranteed fMAX for registered data path operation (no feedback) can be calculated as the lower of 1/(twH + twLl or
1/(18 + tH).

2-31

II

PLDC20GIOB/PLDC20GIO
Switching Characteristics Over Operating Rangd3, 8, 9] (continued)
Military/lndustrial

B-20
Parameter

Description

B-25

-40

-30

Min. Max. Min. Max. Min. Max. Min. Max.

Unit

tpD

Input or Feedback to Non-Registered Output

20

25

30

40

ns

tEA

Input to Output Enable

20

25

30

40

ns

tER

Input to Output Disable

20

25

30

40

ns

tpzx

Pin 11 to Output Enable
Pin 11 to Output

17

20

25

25

ns

17

20

25

25

ns

25

ns

tpxz

Disable

15

15

teo

Clock to Output

ts

Input or Feedback
Set-UpTime

tH
tp[lO]

Hold Time

0

0

Clock Period

30

33

tWH

Clock Higb Time

12

14

tWL

Clock Low Time

12

fMAX[ll]

Maximum Frequency

33.3

15

18

20
20

35

ns

0

0

ns

40

60

ns

16

22

ns

14

16

22

ns

30.3

25.0

16.6

MHz

Switching Waveform
INPUTS 1/0, 1r"7~~"'"
REGISTERED
FEEDBACK ...........~"

CP

tpzx

REGISTERED
OUTPUTS _ _ _ _ _--'~~

tEA
COMBINATORIAL
OUTPUTS ______________~~~VI'---------------------~~
20Gl0-17

2-32

&--::z
==--r;::.

PLDC20GIOB/PLDC20GIO

;,. CYPRESS

Functional Logic Diagram
-[>0

4

8

12

18

20

24

2B

32

38

40

DE
0

·

:B::::::t..-/

..... 7

DE
0

··

:'1---

~
~

7

2

=~
~
CELL

~

'-I

OUTPU
CELL

:4--

DE
0

·

3

g::::r- :4--

~7

DE
0

··

~~

7

4
DE
0

5

UTPU
CELL

~

·

l:E:f-....

OUTPU
CELL

~

~7
DE
0

·

6

UTPU
CELL

~

--l':::7

DE
0

··

~

~
0-'

7

7

UTPU
CELL

:4--

DE
0

·

8

I:i3-J

~7

DE
0

··

9

OUTPU
CELL

~

~

0-'

--l':::7

OUTPU
CELL

~

DE
0

·

~
~
~
~
~
~

±r
7;
UTPUT
CELL

..... 7

~

10 --I

11

~

OUTPU
CELL

---b

20G1(}-18

2-33

23

22

II
21

20

19

18

17

16

15

14

13

~rcYPRESS

PLDC20GIOB/PLDC20GIO

Ordering Information
tpD
ts
teo Icc
(ns)

(ns)

(ns)

(rnA)

15

12

10

70

Ordering Code
PLDC20GlOB 15JC/JI
PWC20G lOB -15PC/PI

20

12

12

70

20

15

15

100

25

15

15

55

25

18

15

100

30

20

20

80

35

30

25

55

40

35

25

80

PLDC20GlOB-15WC
CG7C323B - A15JC/JIL 1 J
PLDC20GlOB-20JC/JI
PLDC20G lOB- 20PCIPI
PLDC20GlOB-20WC
CG7C323B-A20JC/JIlIJ
PLDC20GlOB-20DMB
PLDC20GlOB 20LMB
PLDC20GlOB-20WMB
PLDC20GlO- 25JC/JI
PLDC20G10- 25PCIPI
PLDC20GlO-25WC
CG7C323-A25JC/JILIJ
PLDC20GlOB-25DMB
PWC20GlOB 25LMB
PWC20GlOB-25WMB
PLDC20GlO-30DMB
PWC20G10-30LMB
PWC20GlO- 30WMB
PLDC20GlO 35JC/JI
PLDC20GlO- 35PCIPI
PLDC20GlO-35WC
CG7C323 A35JC/JIlIJ
PLDC20GlO-40DMB
PLDC20GlO-40LMB
PLDC20GlO-40WMB

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIH
VIL
Ilx
Ioz
ICC

Package
Name
J64
P13
W14
J64
J64
P13
W14
J64
D14
L64
W14
J64
P13
W14
J64
D14
L64
W14
D14
L64
W14
J64
P13
W14
J64
D14
L64
W14

28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP

Switching Characteristics

Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

Package 'Jype

Parameter

Subgroups

9,10,11
tPD
9,10,11
tpzx
9,10,11
teo
9,10,11
ts
9,10,11
tH
Document #: 38-00019-G

2-34

Operating
Range
Commercial!
Industrial

Commercial!
Industrial

Military

Commercial!
Industrial

Military

Military

Commercial!
Industrial

Military

PLDC20RAIO

Reprogrammable
Asynchronous CMOS
Logic Device
Features
• Advanced-user programmable macrocell
• CMOS EPROM technology for reprogrammability
• Up to 20 input terms
• 10 programmable 110 macrocells
• Output macrocell programmable as
combinatorial or asynchronous Dtype registered output
• Product-term control of register
clock, reset and set and output enable
• Register preload and power-up reset
• Four data product terms per output
macrocell

- Military/lndustrial
tpD = 20 ns
teo = 20 ns
tsu = 10 ns
• Lowpower
- Icc max - 80 rnA (Commercial)
- Icc max = 85 rnA (Military)
• High reliability
- Proven EPROM technology
- >2001V input protection
-100% programming and functional
testing
• Windowed DIP, windowed LCC, DIP,
LCC, PLCC available

Functional Description
The Cypress PLDC20RAlO is a high-performance, second-generation program-

• Fast
- Commercial
tpD = 15 ns
teo = 15 ns
tsu=7ns

mabIe logic device employingaflexible macrocell structure that allows any individual
output to be configured independently as a
combinatorial output or as afully asynchronous D-type registered output.
The Cypress PLDC20RAlO provides lower-power operation with superior speed
performance than functionally equivalent
bipolar devices through the useofhigh -performance 0.8-micron CMOS manufacturing technology.
The PLDC20RA10 is packaged in a 24 pin
300-mil molded DIP, a 300-mil windowed
cerDIp, and a 28-lead square leadless chip
carrier, providing up to 20 inputs and 10
outputs. When the windowed device is exposed to UV light, the 20RAlO is erased
and can then be reprogrammed.

Logic Block Diagram

I/O,

I/O.

1/0 7

liD.

I/O,

1/0 3

1/02

Vee

1100
RA1()'1

Selection Guide
Generic Part
Number
20RAlO-15

Com'l
15

20RAlO-20

20

tpD ns
Mil/lnd
20

Com'l
7
10

tsu ns
MiI/lnd
10

Com'l
15
20

teo ns
MiI/lnd
20

Com'l
80
80

lee ns
MiIJInd
85

20RAlO-25

25

15

25

85

20RAlO-35

35

20

35

85

2-35

fI

~

~ ?cYPRESS

PLDC20RAIO

Pin Configurations
LCC
Top View

STD PLCC/HLCC
Top View

~ :21~~gg
'2
'3
'4
'5
'6
'7
NC

5
6

10
11

~:.?I~

2~1!

282726
25
24
23
PLDC20RA 10 22
21
20
19
12131415161718
4 3

gg'g

-=- .?I~ l! ~ g'g

4 3 21282726

NC

1/02
1/03
1/04
1/05
1/0 6
1/0 7

JEDEC PLCC/HLCC [1]
Top View

NC

5

'3

I,
NC

PLDC20RA10

15
'6

4 3 21282726
1/02
1/0 3
1/0 4
1/0 5
1/0 6
1/0 7
NC

NC

''32

14
NC

15
'6
'7

PLDC20RA10
CG7C324

_ 2001 V
(per MIL-SID-SS3, Method 3015)

Latch-Up Current ............................ >200 rnA
DC Program Voltage .............................. 13.0V

Operating Range
Ambient
Temperature
O°C to +75°C

Vee
5V:!: 10%

Industrial

-40°C to +S5°C

5V:!: 10%

Military[2]

-55°C to + 125°C

5V:!: 10%

Range
Commercial

fI

Electrical Characteristics Over the Operating Rangel3]
Parameter
VOH

Description

Min.

Test Conditions

Output HIGH Voltage

Vee = Min.,
VIN = VIH or VIL

IOH = -3.2 rnA

Com'l

IOH = -2 rnA

MiI/lnd

IOL = SrnA

VOL

Output LOW Voltage

Vee = Min.,
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed Input Logical HIGH Voltage for All Inputs[4]

VIL

Input LOW Level

Guaranteed Input Logical LOW Voltage for All Inputs[4]

IIX

Input Leakage Current

Vss:<:::: VIN :<:::: Vee, Vee = Max

Ioz

Output Leakage Current

Ise
IcC!

Iee2

Max.

Unit
V

2.4

0.5

V

O.S

V

-10

+10

Vee = Max., Vss:<:::: VOUT:<:::: Vee

-40

+40

fAA
fAA

Output Short Circuit Current[5]

Vee = Max., VOUT = 0.5V[6]

-30

-90

rnA

Standby Power Supply Current

Vee= Max., VIN = GND Outputs Open

Com'l

75

rnA

MiIJInd

SO

rnA

Com'l

SO

rnA

MiIJInd

S5

rnA

Power SUPB?, Current at
Frequency

Vee = Max., Outputs Disabled (In High Z
State) Device Operating af fMAX

2.0

V

Capacitance[5]
Max.

Unit

CIN

Input Capacitance

VIN = 2.0 V @ f = 1 MHz

10

pF

COUT

Output Capacitance

VOUT = 2.0 V @ f = 1 MHz

10

pF

Parameter

Description

Test Conditions

Notes:
2. TA is the "instant on" case temperature.
3. See the last page ofthis specification for Group A subgroup testing information.
4. These are absolute values with respect to devicee ground and all overshoots due to system or tester noise are included.

5.
6.

2-39

Tested initially and after any design or process changes that may affect
these parameters.
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = 0.5 V has
been chosen to avoid test problems caused by tester ground degradation.

-

-~

I

PLDC20RAIO

CYPRESS

AC Test Loads and Waveforms (Commercial)
Rl 457Q
(470Q MIL)

Rl 457Q
(470Q MIL)

ALL INPUT PULSES
3.0V---

5 v ; n R2
5 V 5 f 1 R2
OUTPUT
OUTPUT
GND
270Q
270Q
50 pF
(319Q Mil)
5 pF
(319Q Mil)

I

I

~78~~~NG -=-

-=-

SCOPE

~78~~~NG -=SCOPE

(a)
Equivalent to:
OUTPUT

-=RA1()'15

RA10-14

(b)

THEvENIN EQUIVALENT (Commercial)

~

Equivalent to:

190Q

1.86V=Vt hc

OUTPUT~

RA1().16

Parameter
tpxZ(-)

tpXZ(+)

THEvENIN EQUIVALENT (Military/Industrial)
2.02V=Vlhc

Output Waveform-Measurement Level

Vth
1.5V

2.6V

VOH O.5V

O.5V

VOL

O.SV

tpZX(+)

Vthc

Vx

tpZX(-)

Vthc

Vx

tER(-)

1.5V

VOH O.5V

tER(+)

2.6V

VOL

tEA(+)

Vthc

Vx

tEA(-)

Vthc

Vx

l

O.5V

l

2-40

RA10·18

Vx
RA1().19

VOH
RA10·20

, I:

RA10·21

Vx

RA10·22

~
~
~

Vx

O.5V

(c)

~
~
~

VX

VOL

O.5V

O.5V

l
l

~

l
l

,

RA1()'23

VOH
RA1().24

VOL

RA10·25

RA1()'17

- -.:::4:
=--,

PLDC20RAIO

CYPRESS

Switching Characteristics Over the Operating Rangel 3, 7, 8]
Commercial
-20
-15
Parameter

Description

Min.

Max.

Min.

Military/lndustrial
-25

-20

Max.

Min.

Max.

Min.

Max.

-35

Min.

Max.

Unit

tpD

Input or Feedback to
Non-Registered Output

15

20

20

25

35

ns

tEA

Input to Output Enable

15

20

20

30

35

ns

tER

Input to Output
Disable

15

20

20

30

35

ns

tpzx

Pin 13 to Output
Enable

12

15

15

20

25

ns

tpxz

Pin 13 to Output
Disable

12

15

15

20

25

ns

teo

Clock to Output

35

ns

tsu

Input or Feedback
Set-UpTime

15

7

20
10

25

20
15

10

20

ns

tH

Hold Time

3

5

3

5

5

ns

tp

Clock Period
(tsu + tCO)

22

30

30

40

55

ns

tWH

Clock Width HIGH[5]

10

13

12

18

25

ns

tWL

Clock Width LOW[5]

10

13

12

18

25

ns

fMAX

Maximum Frequency
(1/tp )[5]

45.5

33.3

33.3

25.0

18.1

MHz

ts

Input of Asynchronous
Set to Registered
Output

15

20

20

25

40

ns

tR

Input of Asynchronous
Reset to Registered
Output

15

20

20

25

40

ns

tARW

Asynchronous Reset
Width[5]

15

20

20

25

25

ns

tASW

Asynchronous Set
Width[5]

15

20

20

25

25

ns

tAR

Asynchronous Set!
Reset Recovery Time

10

12

12

15

20

ns

twp

Preload Pulse Width

15

15

15

15

15

ns

tsup

Preload Set-Up Time

15

15

15

15

15

ns

tHP

Preload Hold Time

15

15

15

15

15

ns

Notes:
7. Part (a) of AC Thst Loads was used for all parameters except tEA> tER,
tpzx and tpxz, which use part (b).
8. The parameters tER and tpxz are measured as the delay from the input disable logic threshold transition to VOH - 0.5 V for an enabled

2-41

HIGH output or VOL +O.5V for an enabled LOW output. Please see
part (c) of AC Test Loads and Waveforms for waveforms and measurement reference levels.

fI

~

£¥

~

PLDC20RAIO

-==-; CYPRESS
Switching Waveform
INPUTS, REGISTERED
FEEDBACK

CP
ASYNCHRONOUS
RESET
ASYNCHRONOUS
SET
OUTPUTS
(HIGH ASSERTED)

tEA
OUTPUT ENABLE
INPUT PIN

RA10-26

Preload Switching Waveform
PIN 13
OUTPUT
ENABLE
REGISTER
OUTPUTS
PIN 1
PRELOAD
CLOCK

RA10-27

Asynchronous Reset
ASYNCHRONOUS
RESET
OUTPUT

RA10-28

Asynchronous Set
ASYNCHRONOUS
SET

OUTPUT

:=~rl'----­

-3

_~-------,ts

RA10-29

2-42

?cYPRESS ================~~~
PLDC20RAIO
Functional Logic Diagram

......

1

:§If§·····~~~~~~Dr.;,~::~~r

~Il[j~r
~1l[A~r
~1D~r
~[A~r

.s
3 ...

..
,.

5"

"
6 "

7 ...

8

9 ...

~D~"
:'--·~D~r
:
~D~r

10-f'

11 ...

..

II

••--

~~[j~r

72~."":R::~-v~

.~
o

J

.c

7

•

~1D~r

11

12

'$

~13
16"

20 2l ,. 27 211 31

2-43

32 35 ;'1 3'

RA10-30

~

=

I

~

PLDC20RAIO

CYPRESS

Ordering Information

teo

IcCl

tpD
(ns)

tsu
(ns)

(ns)

80

15

7

15

80

85

85

85

20

20

25

35

10

10

15

20

20

20

25

35

Package
Name

Package 'JYpe

Operating
Range

PLDC20RAlO-15HC

H64

28-Pin Windowed Leaded Chip Carrier

Commercial

PLDC20RAlO-15JC

J64

28-Lead Plastic Leaded Chip Carrier

Ordering Code

PLDC20RAlO-15PC

P13

24-Lead (300-Mil) Molded DIP

PLDC20RAlO-15WC

W14

24-Lead (300-Mil) Windowed CerDIP

CG7C324-A15HC

H64

28-Pin Windowed Leaded Chip Carrier

CG7C324-A15JC

J64

28-Lead Plastic Leaded Chip Carrier

PLDC20RAlO-20HC

H64

28-Pin Windowed Leaded Chip Carrier

PLDC20RAlO-20JC

J64

28-Lead Plastic Leaded Chip Carrier

PLDC20RAlO- 20PC

P13

24-Lead (300-Mil) Molded DIP

PLDC20RAlO-20WC

W14

24-Lead (300-Mil) Windowed CerDIP
28-Pin Windowed Leaded Chip Carrier

CG7C324-A20HC

H64

CG7C324-A20JC

J64

28-Lead Plastic Leaded Chip Carrier

PLDC20RAlO- 20DI

Dl4

24-Lead (300-Mil) CerDIP

PLDC20RAIO-20JI

J64

28-Lead Plastic Leaded Chip Carrier

PLDC20RAlO- 20PI

P13

24-Lead (300-Mil) Molded DIP

PLDC20RAlO- 20WI

W14

24-Lead (300-Mil) Windowed CerDIP

PLDC20RAlO-20DMB

Dl4

24-Lead (300-Mil) CerDIP

PLDC20RAlO-20HMB

H64

28-Pin Windowed Leaded Chip Carrier

PLDC20RAlO-20LMB

L64
Q64

28-Square Leadless Chip Carrier

PLDC20RAlO-2QMB
PLDC20RAlO-20WMB

W14

24-Lead (300-Mil) Windowed CerDIP

PLDC20RAlO- 25DI

D14

24-Lead (300-Mil) CerDIP

PLDC20RAlO- 25JI

J64

28-Lead Plastic Leaded Chip Carrier

Industrial

Military

28-Pin Windowed Leadless Chip Carrier

PLDC20RAlO- 25PI

P13

24-Lead (300-Mil) Molded DIP

PLDC20RAlO-25WI

W14

24-Lead (300-Mil) Windowed CerDlP

PLDC20RAlO-25DMB

Dl4

24-Lead (300-Mil) CerDIP

PLDC20RAlO-25HMB

H64

28-Pin Windowed Leaded Chip Carrier

PLDC20RAlO-25LMB

L64

28-Square Leadless Chip Carrier

PLDC20RAlO-25QMB

Q64

28-Pin Windowed Leadless Chip Carrier

PLDC20RAlO-25WMB

W14

24-Lead (300-Mil) Windowed CerDIP

PLDC20RAlO- 35DI

D14

24-Lead (300-Mil) CerDIP

PLDC20RAIO- 3JI

J64

28-Lead Plastic Leaded Chip Carrier

PLDC20RAlO- 35PI

P13

24-Lead (300-Mil) Molded DIP

PLDC20RAlO-35WI

W14

24-Lead (300-Mil) Windowed CerDIP

PLDC20RAlO-35DMB

Dl4

24-Lead (300-Mil) CerDIP

PLDC20RAlO-35HMB

H64

28-Pin Windowed Leaded Chip Carrier

PLDC20RAlO-35LMB

L64

28-Square Leadless Chip Carrier

PLDC20RAlO-35QMB

Q64

28-Pin Wi.ndowed Leadless Chip Carrier

PLDC20RAI0-35WMB

W14

24-Lead (300-Mil) Windowed CerDlP

2-44

Commercial

Industrial

Military

Industrial

Military

=~

PLDC20RAIO

'CYPRESS

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VIL

1,2,3

IIX

1,2,3

Ioz

1,2,3

Icc

1,2,3

EI

Switching Characteristics
Parameter

Subgroups

tpD
tpzx
teo
tsu
tH

9,10,11
9,10,11
9,10,11
9,10,11
9,10,11

Document #: 38-00073-E

2-45

PALCE22VIO

Flash Erasable,
Reprogrammable CMOS PAL® Device
Features
• Lowpower
-90 mA max. commercial (10 ns)
-130 mA max. commercial (5 ns)
• CMOS Flash EPROM technology for
electrical erasability and reprogram·
mability
• Variable product terms
-2 x (8 through 16) product terms
• User-programmable macrocell
- Output polarity control
- Individually selectable for registered or combinatorial operation
• Up to 22 input terms and 10 outputs
• DIP, LCC, and PLCC available
- 5 ns commercial version
4 ns tco

Functional Description

3 ns ts
5 ns tpD
181-MHz state machine
-10 ns military and industrial versions
7 ns teo
6ns ts
10 ns tpD
nO-MHz state machine
-IS-ns commercial, industrial, and
military versions
-25-ns commercial, industrial, and
military versions
• High reliability
- Proven Flash EPROM technology
-100% programming and functional
testing

The Cypress PALCE22VlO is a CMOS
Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-products (AND-OR) logic structure and the
programmable macrocell.
The PALCE22V10 is executed in a 24-pin
300-mil molded DIP, a 300-mil cerDIp, a
28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides up to 22 inputs and 10
outputs. The PALCE22V10 can be electrically erased and reprogrammed. The programmable macrocell provides the capability of defining the architecture of each
output individually. Each of the 10 potential outputs may be specified as "registered" or "combinatorial." Polarity of

Logic Block Diagram (PDIP/CDIP)

I/Og

1/0 7

1/08

Pin Configuration

1/06

liD,

1/05

__ 0

4 3 2 1 282726

4 3 2 ~1~ 282726

25
24
23

22
21
20
19
12131415161718

--$~-gg

1/0 2
1/0 3
1/0 4

I
I
I
NC
I
I
I

N/C
1/0 5

liDs
1/0 7
CE22Vl0-2

1/0 2

1/0 3
1/0 4

N/C

1/0 5
1/0 6
1/0 7
- - ( 1 ) 0 - ma:a

-!I' z

PAL is a registered trademark of Advanced Micro Devices.

2-46

gg

1100

Vec
CE22Vl 0-1

a:088o
z::;;;::,.::::,

--~~~gg

7
8
9
10
11

1/01

1/02

PLCC
ThpView

LCC
ThpView

I
I
I
NC
I
I
I

1/03

CE22Vl0-3

PALCE22VIO
Selection Guide
tpD ns
Generic Part Number

Com'l

ts ns

MillInd

Com'l

MillInd

3

tcons
Com'l
Mil/Ind

IccmA
Com'l

Mil/lnd

PALCE22V10-5

5

PALCE22VlO-7

7.5

PALCE22VlO-1O

10

10

6

6

7

7

90

PALCE22VlO-15

15

15

10

10

8

8

90

120

PALCE22VlO-25

25

25

15

15

15

15

90

120

4

5

Functional Description (continued)
each output may also be individually selected, allowing complete
flexibility of output configuration. Further configurability is provided through "array" configurable "output enable" for each potential output. This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a
combination I/O controlled by the programmable array.
PALCE22VlO features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms per
output. By providing this variable structure, the PALCE 22VlO is
optimized to the configurations found in a majority of applications
without creating devices that burden the product term structures
with unusable product terms and lower performance.
Additional features of the Cypress PALCE22VlO include a synchronous preset and an asynchronous reset product term. These
product terms are common to all macrocells, eliminating the need
to dedicate standard product terms for initialization functions. The
device automatically resets upon power-up.

130
130

5

150

put. Each of these outputs is achieved through an individual programmable macrocell. These macrocellsare programmable to provide a combinatorial or registered inverting or non-inverting
output. In a registered mode of operation, the output of the register is fed back into the array, providing current status information
to the array. This information is available for establishing the next
result in applications such as control state machines. In a combinatorial configuration, the combinatorial output or, if the output is
disabled, the signal present on the I/O pin is made available to the
array. The flexibility provided by both programmable product term
control of the outputs and variable product terms allows a significant gain in functional density through the use of programmable
logic.
Along with this increase in functional density, the Cypress
PALCE22VlO provides lower-power operation through the use of
CMOS technology, and increased testability with Flash reprogrammability.

Configuration Thble

The PALCE22VlO, featuring programmable macrocells and variable product terms, provides a device with the flexibility to implement logic functions in the 500- to 800-gate-array complexity.
Since each of the 10 output pins may be individually configured as
inputs on a temporary or permanent basis, functions requiring up
to 21 inputs and only a single output and down to 12 inputs and 10
outputs are possible. The 10 potential outputs are enabled using
product terms. Any output pin may be permanently selected as an
output or arbitrarily enabled as an output and an input through the
selective use of individual product terms associated with each out-

2-47

Registered/Combinatorial
Configuration

Cl

Co

0

0

Registered/Active LOW

0

1

Registered/Active HIGH

1

0

Combinatorial/Active LOW

1

1

Combinatorial/Active HIGH

PALCE22VIO
Macrocell

r----------------------,I
AR
OUTPUT
SELECT
a i - - - - - I MUX

) - - - J . . - - - -......-ID

I
I
I

01-.-----1

CP

SP
INPUT/
FEEDBACK
MUX

C1 --------~--~----------------------------~
Co --------~------------------~M~A~C~R~O~C~E~LL~------~

~----------------------

CE22V1Q-4

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................. -65°C to +150°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Volt~ge to Ground Potential
(Pm 24 to Pm 12) ....................... -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.5V to + 7.0V
DC Input Voltage ....................... -O.5V to + 7.0V
Output Current into Outputs (LOW) .............. 16 rnA
DC Programming Voltage ......................... 12.5V
Latch-Up Current ........................... >200 rnA

Static Discharge Voltage
(per MIL-STD-883, Method 3015) .............. >2001V

Operating Range
Range
Commercial
Industrial
Military!l]

Note:
1. TA is the "instant on" case temperature.

2-48

Ambient
Temperature
O°C to +75°C

Vee
5V±5%

-40°C to +85°C

5V ±1O%

-55°C to + 125°C

5V±1O%

PALCE22V10
Electrical Characteristics Over the Operating Range[2]
Parameter
VOH

Description
Output HIGH Voltage

'lest Conditions

Min.

Vee = Min.,
VIN = VIH or VIL

IOH = -3.2 rnA

Com'l

IOH = -2 rnA

Mil/Ind

IOL = 16 rnA

Com'l

IOL = 12 rnA

Mil/Ind

Max.

Unit

2.4

V

VOL

Output LOW Voltage

Vee = Min.,
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed Input Logical HIGH Voltage for All Inputs[3]

2.0

VIL[4]

Input LOW Level

Guaranteed Input Logical LOW Voltage for All Inputs[3j

-0.5

0.8

V

IIX

Input Leakage Current

Vss~

-10

10

Ioz

Output Leakage Current

Vee = Max., Vss~ VOUT~ Vee

-40

40

flA
flA

Ise

Output Short Circuit Current Vee = Max., VOUT = 0.5v[5, 6]

-30

-130

rnA

IcC!

Standby Power Supply
Current

90

rnA

Iee2[6]

Operating Power Supply
Current

VIN ~ Vee, Vee = Max.

Vee - Max.,
10,15,25 ns
V IN = GND,
Outputs Open in 5,7.5 ns
Unprogrammed
15,25 ns
Device
10 ns

Com'l

Vee = Max., V IL =
3V,
Output Open, Device Programmed as
a lO-Bit Counter,
f=25MHz

Com'l

Ov, VIH =

10,15,25 ns

0.5

Mil/Ind

5,7.5 ns
15,25 ns

Mil/Ind

10 ns

V

V

130

rnA

120

rnA

120

rnA

110

rnA

140

rnA

130

rnA

130

rnA

Capacitance[6]
Parameter

Description

CjN

Input Capacitance

COUT

Output Capacitance

Max.

Unit

VIN = 2.0V @ f = 1 MHz

Test Conditions

Min.

10

pF

VOUT = 2.0V @ f = 1 MHz

10

pF

Endurance Characteristics[6]
Description
Minimum Reprogramming Cycles

Test Conditions
Normal Programming Conditions

Notes:
2. See the last page of this specification for Group A subgroup testing in·
formation.
3. These are absolute values with respect to device ground. AU over·
shoots due to system or tester noise are included.
4. VIL (Min.) is equal to -3.0V for pulse durations less than 20 ns.

5.
6.

2-49

Not more than one output should be tested at a time. Duration of the short
circuit should not be more than one second. VOUT = O.5V has been cho·
sen to avoid test problems caused by tester ground degradation.
Thsted initially and after any design or process changes that may affect
these parameters.

fI

PALCE22VIO
AC Test Loads and Waveforms
R123BQ

R123BQ

OUTP:~:r.1(319Q
MIL)

5V :=F1(319QMIL)
OUTPUT

INCLUDING
JIG AND
SCOPE

I

R2170Q
(236Q MIL)

CL

-=

INCLUDING
JIG AND
SCOPE

-=

I

R2170Q
(236Q MIL)

5 pF

-=

OUTPUT

O~-1~--1750Q

I

(1.2KQ

MIL)

-=
(b)

(a)

CL

(c)

ALL INPUT PULSES
3.0V--90%
GND
CE22V1 0·5

(d)

Equivalent to: THEvENIN EQUIVALENT (Military)

Equivalent to: THEvENIN EQUIVALENT (Commercial)

136Q

99Q

OUTPUT 0-----'WIr----0 2.0BV = Vthc

Load Speed
5,7.5, 10, 15,25 ns

CL
50pF

OUTPUT 0-----'WIr----0 2.13V = Vthm

CE22Vl0-6

Package

Parameter

Vx

PDIp,CDIp,
PLCC,LCC

tER(-)

1.5V

tER(+)

2.6V

tEA(+)

OV

tEA(-)

Vthc

Output Waveform-Measurement Level
VOH O.5V

~

t
t
t

VOL

O.5V

Vx

1.5V

Vx

0.5V

~
~
~
~

(e) Test Waveforms

2-50

CE22V1D-7

Vx
Vx
VOH

VOL

~

---."..

-,,~

PALCE22VIO

; CYPRESS
Commercial Switching Characteristics PALCE22VIO[2, 7]
22VIO-S
Parameter

Description

22VIO-7

22VIO-IO

22VIO-lS

22VIO-2S

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

3

5

3

7.5

3

10

3

15

3

25

ns

tpD

Input to Output
Propagation Delay[8]

tEA

Input to Outp'ut
Enable Delay[9]

6

8

10

15

25

ns

tER

Input to Output
Disable Delay[10]

6

8

10

15

25

ns

tco

Clock to Output Delay[8]

2

15

ns

tSI

Input or Feedback Set-Up Time

3

5

6

10

15

ns

tS2

Synchronous Preset Set-Up Time

4

6

7

10

15

ns

tH

Input Hold Time

0

0

0

0

0

os

tp

External Clock Period (tco + tS)

7

10

12

20

30

ns

tWH

Clock Width HIGH[6]

2.5

3

3

6

13

ns

tWL

Clock Width LOW[6]

2.5

3

3

6

13

ns

fMAXI

External Maximum
Frequency (l/(tco + ts»[U]

143

100

76.9

55.5

33.3

MHz

fMAX2

Data Path Maximum Frequency
(l/(tWH' + twd)[6,12]

200

166

142

83.3

35.7

MHz

fMAX3

Internal Feedback Maximum
Frequency (l/(tCF + tS»[6,13]

181

133

111

68.9

38.5

MHz

tCF

Register Clock to
Feedback Inpud6, 14]

2

4

2.5

5

2

2.5

7

2

3

8

2

13

4.5

os

tAW

Asynchronous Reset Width

8

8

10

15

25

ns

tAR

Asynchronous Reset
Recovery Time

4

5

6

10

25

ns

tAP

Asynchronous Reset to
Registered Output Delay

tSPR

Synchronous Preset
Recovery Time

4

6

8

10

15

ns

tpR

Power-Up Reset Timd6, 15]

1

1

1

1

1

Ils

7.5

12

Noles:
7. Part (a) of AC Thst Loads and Waveforms is used for all parameters except tER and tEA( + ). Part (b) of AC Thst Loads and Waveforms is used
fortER. Part (c) ofAC Thst Loads and Waveforms is used fortEA(+)'
8. Min. times are tested initially and after any design orproccss changes.
that may affect these parameters.
9. The test load of part (a) of AC Thst Loads and Waveforms is used for
measuring tEA(-). The test load of part (c) of AC Test Loads and
Waveforms isusedformeasuringtEA(+)only. Please see part (e) ofAC
Thst Loads and Waveforms for enable and disable test waveforms and

measurement reference levels.
10. This parameter is measured as the time after output disable input that
the previous output data state remains stable on the outpu t. This delay
is measured to the point at which a previous HIGH level has fallen to
0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts
above VOL max. Please see part (e) of AC Thst Loads and Waveforms
for enable and disable test waveforms and measurement reference
levels.

20

13

25

ns

11. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can
operate.
12. This specification indicates the guaranteed maximum frequency at
which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate.
14. This parameter is calculated from the clock period at fMAX internal
(l/fMAX3) as measured (see Note 11 above) minns ts.
15. The registers in the PALCE22VlO have been designed with the capability to reset during system power-up. Following power-up, all registerswill be reset to a logic LOW state. The output state will depend on
the polarity of the output buffer. This feature is useful in establishing
state machine initialization. Th insure proper operation, the rise in Vee
must be monotonic and the timing constraints depicted in Power-Up
Reset Waveform must be satisfied.

2-51

II

=- .. ~

PALCE22VIO

=;CYPRESS
Military and Industrial Switching Characteristics PALCE22VIO[2, 7]
22V1O-1O

Parameter

Description

22V1O-1S

22V1O-2S

Min.

Max.

Min.

Max.

Min.

Max.

Unit

3

10

3

15

3

25

ns

15

25

ns

15

25

ns

15

ns

tpD

Input to Output
Propagation Delay[8]

tEA

Input to Output Enable Delay[9]

10

tER

Input to Output Disable Delay[lO]

10

tco

Clock to Output Delay[8]

2

t51

Input or Feedback Set-Up Time

6

10

18

ns

7

2

8

2

t52

Synchronous Preset Set-Up Time

7

10

18

ns

tH

Input Hold Time

0

0

0

ns

tp

External Clock Period (tco

12

20

33

ns

tWH

Clock Width HIGH[6]

3

6

14

ns

tWL

Clock Width LOW[6]

3

6

14

ns

fMAX1

External Maximum Frequency
(lI(tco + t5))[11]

76,9

50.0

30.3

MHz

fMAX2

Data Path Maximum Frequency
(1/(tWH + tWL))[6, 12]

142

83.3

35.7

MHz

fMAX3

Internal Feedback Maximum
Frequency (l/(tCF + t5))[6,13]

111

68.9

32.2

MHz

tCF

Register Clock to
Feedback Inputl6, 14]

+ t5)

13

4.5

3

ns

tAW

Asynchronous Reset Width

10

15

25

ns

tAR

Asynchronous Reset
Recovery Time

6

12

25

ns

tAP

Asynchronous Reset to
Registered Output Delay

t5PR

Synchronous Preset
Recovery Time

8

20

25

ns

tpR

Power-Up Reset Timel6, 15]

1

1

1

fls

12

2-52

20

25

ns

='

PALCE22VIO

?cYPRESS

Switching Waveforms
INPUTS I/O, _____......
REGISTERED
FEEDBACK
SYNCHRONOUS _ _ _~V'
PRESET
CP

ASYNCHRONOUS
RESET _ _ _ _ _ _ _ _~~------~~
REGISTERED -----------~........
OUTPUTS _ _ _ _ _ _ _~UL~

COMBINATORIAL -----------------.....:,...;.:
OUTPUTS

------------------------~~
CE22Vl0-B

Power-Up Reset Waveform[15]
POWER
10'" ~'E9;oO%%:------------------------ Vcc
SUPPLY VOLTAGE _ _ _ _ _ _ _:."0f-

~----------- tpR------~

REGISTERED
ACTIVE LOW
OUTPUTS

--------t-t------~~~~~~~~~~kr--------­
------~r_-----~~~~~~~~

CLOCK

CE22Vl0-9

2-53

PALCE22VIO

1ircYPRESS
Functional Logic Diagram for PALCE22VIO

1-ri>

•

AR
DE
0

'-1"

1

1

4

3

I> :::8b

··

DE
0

1....--

··

~
13-

11

··
"

cell

~

DE
0

4

~bh
Macro-

~

13

T

9

;:bh,
~~

8

1h
,;-~'

7

cell

~

D~=

o===:

F

Bt----

.~

11

15

D~=

o===:
===:
:~
:===:

7

Macro-

......

~

13
DE
0

··

l=t---.
~r--'

9

D~=

O===:
.===:
:~
9===:

d--

D~~
0;;;::::::;:.;;:

:~
:===:::

:B:::l """

7~

I=C'J

~

~

SP

~,
coli

'~

11

8

I--

::~r
TT~

~
~
15 ;;;;;;;;;::;;;;

:~
6

20

COII

~

:~
:~

"

21

1

I::::

DE
0

5

22

cell

DE
0

-i'

23

1><1- ::tb
::bh
13....<1-

·

2-1"9

3

cell

::1--

7

II

~tb"
'-rr

~~
Moe.,.

coil

13
CE22V10·10

2-54

14

I......-r-

..-1.

1

6

PALCE22VIO
Ordering Information
ICC

(mA)

tpD

(ns)

ts
(ns)

tco
(ns)

Ordering Code

Package
Name

Package 'IYpe

Operating
Range

130

5

3

4

PALCE22V1O-5JC

J64

28-Lead Plastic Leaded Chip Carrier

Commercial

130

7.5

5

5

PALCE22V1O-7JC

J64

28-Lead Plastic Leaded Chip Carrier

Commercial

PALCE22V1O-7PC

P13

24-Lead (300-Mil) Molded DIP

PALCE22VI0-I0JC

J64

28-Lead Plastic Leaded Chip Carrier

PALCE22V1O-1OPC

P13

24-Lead (300-Mil) Molded DIP

90

10

150
150

90

10
10

15

120
120

15
15

25

90
120
120

25
25

6
6
6

7.5
7.5
7.5

15
15
15

7

PALCE22V1O-1OJI

J64

28-Lead Plastic Leaded Chip Carrier

PALCE22V1O-10PI

P13

24-Lead (300-Mil) Molded DIP

PALCE22V10-10DMB

D14

24-Lead (300-Mil) CerDIP

PALCE22V1O-10KMB

K73

24-Lead Rectangular Cerpack

PALCE22V1O-1OLMB

L64

28-Square Leadless Chip Carrier

PALCE22V1O-15JC

J64

28-Lead Plastic Leaded Chip Carrier

PALCE22V1O-15PC

P13

24-Lead (300-Mil) Molded DIP

PALCE22V1O-15JI

J64

28-Lead Plastic Leaded Chip Carrier

PALCE22V1O-15PI

P13

24-Lead (300-Mil) Molded DIP

7
7

10
10

PALCE22VI0-15DMB

D14

24-Lead (300-Mil) CerDIP

PALCE22V1O-15KMB

K73

24-Lead Rectangular Cerpack

PALCE22VI0-15LMB

L64

28-Square Leadless Chip Carrier

PALCE22VI0- 25JC

J64

28-Lead Plastic Leaded Chip Carrier

PALCE22VI0-25PC

P13

24-Lead (300-Mil) Molded DIP

10

15

PALCE22V1O- 25JI

J64

28-Lead Plastic Leaded Chip Carrier

PALCE22V1O-25PI

P13

24-Lead (300-Mil) Molded DIP

PALCE22V1O-25DMB

D14

24-Lead (300-Mil) CerDIP

PALCE22V10-25KMB

K73

24-Lead Rectangular Cerpack

PALCE22V1O-25LMB

L64

28-Square Leadless Chip Carrier

15
15

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics

Switching Characteristics

Parameter

Subgroups

Parameter

Subgroups

VOH
VOL
VIH
VIL
IIX
Ioz
Icc

1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

tpD

9,10,11
9,10,11
9,10,11
9,10,11

tco
ts
tH

Document #: 38-00447-B

2-55

Commercial
Industrial
Military

Commercial
Industrial
Military

Commercial
Industrial
Military

Ell

This is an abbreviated datasheet. Contact a
Cypress representative for complete specifications.
For new designs, please refer to the PALCE22VIO.

PALC22VIO
Reprogrammable CMOS
PAL® Device
Features
• Advanced second-generation PAL
architecture
• Lowpower
- SS mA max. "C'
- 90 mA max. standard
-120 mA max. military
• CMOS EPROM technology for
reprogrammabiJity
• Variable product terms
- 2 x (8 tbrough 16) product terms
• User-programmable macrocell
- Output polarity control
- Individually selectable for registered or combinatorial operation
• 20, 2S, 3S ns commercial and
industrial

• 2S, 30, 40 ns military
• Up to 22 input terms and 10 outputs
• Iligh reliability
- Proven EPROM technology
-100% programming and functional
testing
• Windowed DIP, windowed LCC, DIP,
LCC, and PLCC available

Functional Description·
The Cypress PALC22VlO is a CMOS second-generation programmable logic
array device. It is implemented with the familiar sum-of-products (AND-OR) logic
structure and a new concept, the "programmable macrocell."
The PALC22V10 is available in 24-pin
300-mil molded DIPs, 300-mil windowed
cerDIPs, 28-lead square ceramic leadless

chip carriers, 28-lead square plastic1eaded
chip carriers, and provides up to 22 inputs
and 10 outputs. When the windowed cerDIP is exposed to UV light, the 22V10 is
erased and can then be reprogrammed.
The programmablemacrocell provides the
capability of defining the architecture of
each output individually. Each of the 10
potential outputs may be specified as registered or combinatorial. Polarity of each
output may also be individually selected,
allowing complete flexibility of output
configuration. Further configurability is
provided through array-configurable output enable for each potential output. This
feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or
alternately used as a combination I/O controlled by the programmable array.

Logic Block Diagram (PDIP/CDIP)
vss

CP/I

I/O,

1105

110a

1/0:1

1/01

1/00

Vec
Vl0-l

Pin Configuration

LCC/PLCC
Top View

--~~ygg
4 3

I
I
NC
I
I
I

2~1!

282726
25
2_
23
7
8
22
9
21
10
20
11
19
12131415161718

1/0 2
1/0 3
I/O_
NC
1/0 5
1/0 6
1/0 7

--(1')0- Oleo

ftJz

PAL is a registered trademark of Advanced Micro Devices.

Document #: 38-00020-H

2-56

gg

Vlo-2

This is an abbreviated datasheet. Contact a Cypress
representative for complete specifications. For new
designs, please refer to the PALCE22V10.

PALC22VIOB
Reprogrammable CMOS PAL® Device
• Advanced second generation PAL architecture
• Lowpower
- 90 rnA max. standard
-100 rnA max. military
• CMOS EPROM technology for reprogrammability

The Cypress PALC22V10B is a CMOS
second-generation programmable logic
array device. It is implemented with the
familiarsum-of-products(AND-OR)logic
structure and a new concept, the
"Programmable Macrocell."
The PALC22VlOB is executed in a 24-pin
300-mil molded DIP, a 300-mil windowed
cerDIP, a 28-lead square ceramic leadless
chip carrier, a 28-lead square plasticleaded
chip carrier, and provides up to 22 inputs
and 10 outputs. When the windowed cerDIP is exposed to UV light, the 22VlOB is
erased and can then be reprogrammed.
The programmable macrocell provides the
capability of defining the architecture of
each output individually. Each of the 10
potential outputs may be specified as "registered" or "combinatorial." Polarity of
each output may also be individually

• Up to 22 input terms and 10 outputs
• Enhanced test features
- Phantom array
-Top test

• Variable product terms
- 2 x (8 through 16) product terms
• User-programmable macrocell
- Output polarity control
- Individually selectable for registered or combinatorial operation
- "IS" commercial and industrial
10 ns tco
10 ns ts
15 ns tpD
50 MHz

Functional Description

- "IS" and "20" military
10/15 ns teo
10/17 ns ts
15/20 ns tpD
50/31 MHz

Features

-Bottom test
-Preload
• High reliability
- Proven EPROM technology
-100% programming and functional
testing
• Windowed DIP, windowed LCC, DIP,
LCC, PLCC available

Logic Block Diagram (PDIP/CDIP)
Vss

CP/I

Pin Configurations

V10B-1

LCC

PLCC

ThpView

ThpView

__ t~~g'g

__ t~~g'g
4 3 2'1' 282726
••
25
24

I
I
I

N/C
I
I
I

7

8
9
10
11

23

22
21
20
19
12131415161718

4321282726
1/02
1/03
1/04

1/0 2

110 3
1/0 4
N/C
1/0 5

I

I
N/C
I
I

N/C
1/05
1/06

1107

1/0 6

I

110 7
-

V10B-2

PAL is a registered trademark of Advanced Micro Devices

Document #: 38-00195-B

2-57

-

(1)(.)-

:!!'z

Ol

co

gg

Vl0B-3

Ell

PAL22VIOC
PAL22VPIOC
Universal PAL® Device
Features
• Ultra high speed supports today's and
tomorrow's fastest microprocessors
-tpD=6ns
-tsu = 3ns

-'MAx

=117 MHz

• Reduced ground bounce and undershoot
• PLCC and LCC packages with additional Vee and Vss pins for lowest
ground bounce
• Up to 22 inputs and 10 outputs for
more logic power

• 10 user-programmable output
macrocells
- Output polarity control
- Registered or combinatorial
operation
- 2 new feedback paths
(PAL22VPI0C)
• Synchronous PRESET, asynchronous
RESET, and PREWAD capability for
flexible design and testability
• High reliability
- Proven Ti-W fuse technology
-AC and DC tested at the factory
• Security Fuse

• Variable product terms
- 8 to 16 per output

grammable array logic devi
BiCMOS process and Ti-W
PAL22VlOC and PAL22
familiarsum-of-products(
structure and a new co
mabIe macrocell.
Both the PAL22V
22VPlOC
provide 12 dedi
and 10 I/O
pins (see Logic
ram). By selecting each I
permanent or
tempor
22 inputs can be
requiring
up to 21
achieve
utput, down to 12 ininpu
pu
s can be realized. The
roduct term available on
this selection.

Functional Description
The
Cypress
PAl22Vl0C
PAl22VPlOC are second-generatio

Logic Block Diagram and PDIP (P)/CDIP (D) Pin Contigu

v10o-1

PLCC (J)/CLCC (y)
1bpView

--~yyg'g

--~yyg'g
4 3 2 ~1: 282726
25
24
7
23
8 PAL22V10C 22
9 PAL22VP10C 21
10
20
11
19

4321282726

1/0 2
1/°3
1/0 4

Vss

1/0 5

I

vss
I

II0s
1/°7

12131415161718
-

-

rJJOO-

:!t':!t'

0)

co

gg

v1Oc-2

v10c-3

PAL is a registered trademark of Advanced Micro Devices.

Document #: 38-A-00020-E

2-58

For new designs, please refer to the PALCE22VIO.

PALC22VIOD
Flash Erasable,
Reprogrammable CMOS PAL ® Device
• DIP, LCC, and PLCC available

Features
• Advanced second-generation PAL architecture
• Lowpower
- 90 rnA max. commercial (10 ns)
-130 rnA max. commercial (7.5 ns)
• CMOS Flash EPROM technology for
electrical erasability and reprogrammability
• Variable product terms
- 2 x (8 through 16) product terms
• User-programmable macrocell
- Output polarity control
- Individually selectable for registered or combinatorial operation
• Up to 22 input terms and 10 outputs

• High reliability
-Proven Flash EPROM technology
-100% programming and functional
testing

- 7.5 ns commercial version
5 ns tco
5 ns ts
7.5 ns tPD
133-MHz state machine

Functional Description
The Cypress PALC22VlOD is a CMOS
Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-products (AND-OR) logic structure and the
programmable macrocell.
The PALC22VlOD is executed in a 24-pin
300-mil molded DIP, a 300-mil cerDIp, a
28-lead square ceramic leadless chip carrier, a 28-lead square plasticleaded chip carrier, and provides up to 22 inputs and 10
outputs. The 22VlOD can be electrically

-10 ns military and industrial versions
6 ns tco
6 ns ts
10 ns tpD
nO-MHz state machine
-15-ns commercial and military
versions
- 25-ns commercial and military
versions

Logic Block Diagram (PDIP/CDIP)
\Iss

CPII

IIOg

1/08

1/0 7

1/05

IIOS

1/°4

1/0 3

1/°2

1/°1

1/°0

Vec
Vl0D·l

Pin Configuration
PLCC

LCC

ThpView

Top View

__ ~~>Sgg

__ 5~9gg

4 3 2 1 28 27 26

4 3 2 ~1~ 282726

I
I
I
NC
I

25
24
7
23
8
22
9
21
10
20
11
19
12131415161718
- - 00(.)-

:!J'Z

(J)(Q

1/°2
1/°3
1/°4
N/C
1/0 5
1/°6
1/0 7

I
I
I
NC
I

21

1/°2
1/0 3
1/0 4
N/C
1/0 5
I/Os
1/0 7

Vl00-2

gg

-

PAL is a registered trademark of Advanced Micro Devices.

2-59

-

(I) (.) -

:!J' Z

C)

co

gg

Vl0D-3

Ell

PALC22VIOD
Functional Description (continued)
erasedandreprogrammed. Theprogrammablemacrocellprovides
the capability of defining the architecture of each output individually. Each of the 10 potential outputs may be specified as "registered" or "combinatorial." Polarity of each output may also be individually selected, allowing complete flexibility of output
configuration. Further configurability is provided through "array"
configuraple "output enable" for each potential output. This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination I/O controlled by
the programmable array.
PALC22VlOD features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms per
output. By providing this variable structure, the PAL C 22VlOD is
optimized to the configurations found in a majority of applications
without creating devices that burden the product term structures
with unusable product terms and lower performance.
Additional features of the Cypress PALC22V10D include a synchronous preset and an asynchronous reset product term. These
product terms are common to all macrocells, eliminating the need
to dedicate standard product terms for initialization functions. The
device automatically resets upon power-up.
The PALC22VlOD, featuring programmable macrocells and variable product terms, provides a device with the flexibility to implement logic functions in the 500- to 800-gate-array complexity.
Since each of the 10 output pins may be individually configured as
inputs on a temporary or permanent basis, functions requiring up
to 21 inputs and only a single output and down to 12 inputs and 10
outputs are possible. The 10 potential outputs are enabled using

product terms. Any output pin may be permanently selected as an
output or arbitrarily enabled as an output and an input through the
selective use ofindividual product terms associated with each output. Each of these outputs is achieved through an individual programmablemacrocell. Thesemacrocells are programmable to provide a combinatorial or registered inverting or non-inverting
output. In a registered mode of operation, the output of the register is fed back into the array, providing current status information
to the array. This information is available for establishing the next
result in applications such as control state machines. In a combinatorial configuration, the combinatorial output or, if the output is
disabled, the signal present on the I/O pin is made available to the
array. Theflexibilityprovided byboth programmable producUerm
control of the outputs and variable product terms allows a siguificant gain in functional density through the use of programmable
logic.
Along with this increase in functional density, the Cypress
PALC22VlOD provides lower-power operation through the use of
CMOS technology, and increased testability with Flash reprogrammability.

Configuration Table
Registered/Combinatorial
Cl

Co

0

0

0
1
1

1
0
1

Configuration
Registered/Active LOW
Registered/Active HIGH
Combinatorial/Active LOW
Combinatorial/Active HIGH

Macrocell

r----------------------,
AR

>--+------;0

QI-----I

OUTPUT
SELECT
MUX

CP
SP
INPUT!
FEEDBACK
MUX

MACROCELL

~----------------------

2-60

Vl0D·4

=r--.,.....
==

-'I~

PALC22VIOD

'CYPRESS

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................. -65°C to +150°C
Ambient Temperature with
Power Applied ....................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ....................... -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -0.5V to +7.0V
DC Input Voltage ....................... -O.5V to +7.0V
Output Current into Outputs (LOW) .............. 16 rnA
DC Programming Voltage ......................... 12.5V
Latch-Up Current ........................... >200 rnA

Static Discharge Voltage
(per MIL-STD-883, Method 3015) .............. >2001V
Operating Range
Ambient
Temperature

Range
Commercial
Military!!]

O°C to +75°C

Vee
5V±5%

-55°C to +125°C

5V ±10%

Industrial

-40°C to +85°C

5V ±1O%

fII

Electrical Characteristics Over the Operating Range!2]
Parameter
VOH

VOL

Description
Output HIGH Voltage

Output LOW Voltage

Test Conditions

Min.

Vee = Min.,
VIN = VIH or VIL

IOH = -3.2 rnA

Com'l

IOH = -2 rnA

Mil/lnd

Vee = Min.,
VIN = VIH or VIL

IOL= 16 rnA

Com'l

IOL= 12 rnA

Mil/lnd

Max.

Unit

2.4

V

V

0.5

VIH

Input HIGH Level

Guaranteed Input Logical HIGH Voltage for All Inputs!3]

2.0

VIL!4]

Input WW Level

Guaranteed Input Logical LOW Voltage for All Inputs!3]

-0.5

0.8

V

Ilx

Input Leakage Current

Vsss VIN S Vee, Vee = Max.

-10

10

loz

Output Leakage Current

Vee = Max., Vsss VOUT.!S. Vee

Ise

Output Short Circuit Current Vee = Max., VOUT = 0.5V!5, 6]

lee!

lee2!6]

Standby Power Supply
Current

Operating Power Supply
Current

Vee = Max.,
10,15,25 ns
VIN= GND,
Outputs Open in 7.5 ns
Unprogrammed
15,25 ns
Device
10 ns

Com'l

10,15,25 ns

Com'l

Vee = Max., VIL =
OY, VIH = 3Y,
Output Open, Device Programmed as
a IO-Bit Counter,
f=25MHz

-40

40

t-tA
t-tA

-30

-90

rnA

Mil/lnd

7.5 ns
15,25 ns

V

Mil/lnd

10 ns

90

rnA

130

rnA

120

rnA

120

rnA

110

rnA

140

rnA

130

rnA

130

rnA

Capacitance!6]
Parameter
qN
COUT

Description
Input Capacitance
Output Capacitance

Test Conditions

Min.

VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz

Max.
10
10

Unit
pF
pF

Endurance Characteristics!6]
Test Conditions
Normal Programming Conditions
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. VJdMin.) is equal to -3.0V for pulse durations less than 20 ns.

5.
6.

2-61

Not more than one output should be tested at a time. Duration of the short
circuit should not be more than one second. VOUT = OSV bas heen chosen to avoid test problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect
these parameters.

PALC22VIOD
AC Test Loads and Waveforms
R1238Q

R1238Q

OUTP:~:Fl(319QMI~

5V:F1(319QMIL)
OUTPUT

INCLUDING
JIG AND
SCOPE

I

R2170Q
(236Q MIL)

CL

-=

INCLUDING
JIG AND
SCOPE

-=

I

R2170Q
(236Q MIL)

5 pF

O~-I--l 750Q

I

-=

-=

(a)

OUTPUT

(b)

(1.2KQ
MIL)

CL

(c)

ALL INPUT PULSES
3.0V---90%
GND

VIOD·5

(d)
Equivalent to: THEVENIN EQUIVALENT (Commercial)

Equivalent to: THEvENIN EQUIVALENT (Military)

99Q
OUTPUT Q----vvI,----O 2.08V = V1hc

136Q
OUTPUT Q----vvI,----O

2.13V = Vlhm

VIOD-6

Load Speed

7.5, 10, 15, 25 ns

CL
50pF

Package

PDlp,CDlp,
PLCC,LCC

VIOD-7

Parameter

Vx

tER(-)

1.5V

tER(+)

2.6V

tEA(+)

OV

tEA(-)

Vthc

Output Waveform-Measurement Level

VOH O.5V
VOL
Vx
Vx

t ~
t t::

O.5V

1.5V

O.5V

t

t

t::
~

(e) Test Waveforms

2-62

VX

VIOD-8

Vx
VIOD-9

VOH
VIOD-IO

VOL

VIOD-II

=-~

PALC22VIOD

-=-; CYPRESS

Commercial Switching Characteristics PALC22VIOD[2,7]
22V10D-7
Parameter

Description

22V10D-10

22V10D-15

22V10D-25

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

3

7.5

3

10

3

15

3

25

ns

tpD

Input to Output
Propagation Delay[S,9]

tEA

Input to Output Enable Delay[lO]

8

10

15

25

ns

tER

Input to Output Disable Delay[ll]

8

10

15

25

ns

tco

Clock to Output Delay[S, 9]

2

15

ns

tSI

Input or Feedback Set-Up Time

5

6

10

15

ns

tS2

Synchronous Preset Set-Up Time

6

7

10

15

ns

tH

Input Hold Time

0

0

0

0

ns

tp

External Clock Period (tco

10

12

20

30

ns

tWH

Clock Width HIGH[6]

3

3

6

13

ns

tWL

Clock Width LOW[6]

3

3

6

13

ns

fMAXI

External Maximum Frequency
(lI(tco + tS»[12]

100

76.9

55.5

33.3

MHz

fMAX2

Data Path Maximum Frequency
(lI(tWH + twd)[6, 13]

166

142

83.3

35.7

MHz

fMAX3

Internal Feedback Maximum
Frequency (1/(tCF + tS»[6, 14]

133

111

68.9

38.5

MHz

tCF

Register Clock to
Feedback Inputl 6, 15]

tAW

Asynchronous Reset Width

8

tAR

AsynchronousResetRecoveryTime

5

tAP

Asynchronous Reset to
Registered Output Delay

tSPR

Synchronous Preset Recovery Time

6

8

10

15

ns

tpR

Power-Up Reset Timel6, 16]

1

1

1

1

Its

+ ts)

5

2

2.5

7

3

6

Wavefonnsisusedformeasuringt~+)only.Pleaseseepart(e)ofAC

Thst Loads and Waveforms for enable and disable test wavefonns and
measurement reference levels.
I!. This parameter is measured as the time after output disable input that
the previous output data state remains stable on the output. This delay
is measured to tbe point at which a previous HIGH level has fallen to
0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts
above VOL max. Please see part (e) of AC Thst Loads and Wavefonns
for enable and disable test waveforms and measurement reference
levels.

2

13

4.5
25

20

ns
ns

25

10

13

12

8

15

10

Notes:
7. Part (a) of ACTest Loads and Wavefonns is used for all parameters ex·
cept tER and tEA( +). Part (b) of AC Thst Loads and Wavefonns is used
for tER. Part (c) of AC Test Loads and Wavefonns is used for tEA( +).
8. Min. times are tested initially and after any design or process changes
that may affect these parameters.
9. This specification is guaranteed for all device outputs changing state in
a given access cycle.
10. The test load of part (a) of AC Test Loads and Waveforms is used for
measuring tEA( _). The test load of part (c) of AC Test Loads and

2

ns
25

ns

12. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can
operate.
13. This specification indicates the guaranteed maximum frequency at
which the device can operate in data path mode.
14. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate.
15. This parameter is calculated from the clock period at fMAX internal
(l/fMAX3) as measured (see Note 11 above) minus ts.
16. The registers in the PALC22VI0D have been desigued with the capa·
bility to reset during system power·up. Following power-up, all regis·
ters will be resetto a logic LOW state. The output state will depend on
the polarity of the output buffer. This feature is useful in establishing
state machine initialization. To insure proper operation, the rise in V cc
must be monotonic and the timing constraints depicted in Power-Up
Reset Wavefonn must be satisfied.

2-63

til

.....:::=-..

...zp~

PALC22VIOD

; CYPRESS
Military and Industrial Switching Characteristics PALC22VIOD[2,7]
22VIOD-IO
Parameter

Description

22VIOD-15

22VIOD-25

Min.

Max.

Min.

Max.

Min.

Max.

Unit

3

10

3

15

3

25

ns

tpD

Input to Output
Propagation Delay[8, 9]

tEA

Input to Output Enable Delay[10]

10

15

25

ns

tER

Input to Output Disable Delay[ll]

10

15

25

ns

teo

Clock to Output Delay[8, 9]

15

ns

2

7

2

tS1

Input or Feedback Set-Up Time

6

10

8

2
18

ns

tS2

Synchronous Preset Set-Up Time

7

10

18

ns

tH

Input Hold Time

0

0

0

ns

tp

External Clock Period (teo

12

20

33

ns

tWH

Clock Width HIGH[6]

3

6

14

ns

tWL

Clock Width LOW[6]

3

6

14

ns

fMAX1

External Maximum Frequency
(1!(teo + tS»[12]

76.9

50.0

30.3

MHz

fMAX2

Data Path Maximum Frequency
(1!(tWH + tWL»[6, 13]

142

83.3

35.7

MHz

fMAX3

Internal Feedback Maximum
Frequency (1!(tcF + tS»[6,14]

111

68.9

32.2

MHz

tCF

Register Clock to
Feedback Inpud6, 15]

+ ts)

3

13

4.5

ns

tAW

Asynchronous Reset Width

10

15

25

ns

tAR

Asynchronous Reset
Recovery Time

6

12

25

ns

tAP

Asynchronous Reset to
Registered Output Delay

tSPR

Synchronous Preset
Recovery Time

8

20

25

ns

tpR

Power-Up Reset Timd6, 16]

1

1

1

[ts

12

2-64

20

25

ns

g

~YPRESS

PALC22VIOD

Switching Waveform
INPUTS I/O, _ _ _ __
REGISTERED
FEEDBACK
SYNCHRONOUS ---~ ' - _ - 1
PRESET
CP

ASYNCHRONOUS
RESET

------+:----4-...J1

II

REGISTERED ------...;..:,....,:
OUTPUTS _ _ _ _ _ _..Lloal '-_-4_-L:.lLl;'
COMBINATORIAL - - - - - - - - - - - . . . . . . ; : . . : ; . '
OUTPUTS

--------------~~

Vl00-12

Power-Up Reset Waveform[16]
POWER

10% JfS9~~%~-------------------------VCC

SUPPLY VOLTAGE ------~
REGISTERED
ACTIVE LOW
OUTPUTS

tpR------....-I

-------t-t-------.;~~~"7~~.;;:::;;!."7_-------­
------H~-----~~~~~~~~

CLOCK----------------t~------------------------~~
Vl00-13

2-65

=-- ,,~
~;CYPRESS

PALC22VIOD

Functional Logic Diagram for PALC22VIOD

1-r-C

AR

•

1

1

4

3

6

0

OE

··
0

~~

~7

OE

0

2

··
9

:1--

0

··

-+-'

0

··

21

20

cell

~k..

·

cell

~-

15
OE

0

··
15
0

·

I=k..

cell

~

13
OE

0

~

··

~tb
TT
Macro-

~~

9

~-

cell

OE

7

22

~ T

13
0

6

cell

T

-'

OE

5

23

cell

[~

11
OE

4

cell

::tb
::tb
=tb,
T
~~ =tb'
TT

OE

3

::1r
::tb

8

17

=±r

6

cell

~ TT

8-011
OE

0

E::\

9

=~

··

~

9
OE

7

~

cell

4

'-13
V10D-14

2-66

5

T-r-

-1--.....,

SP

1

~ cell

~~,

0

··

::th,

..-=...

-

-"'~

PALC22VIOD

; CYPRESS

Ordering Information
(mA)

Icc

tpD
(ns)

ts
(ns)

teo
(ns)

130

7.5

5

5

90

10

150
150

10
10

6
6
6

7
7
7

90

15

7.5

10

120

15

7.5

10

120

90

15

25

120
120

25
25

7.5

15
15
15

10

Ordering Code

Package
Name

PALC22V10D-7JC

J64

28-Lead Plastic Leaded Chip Carrier

PALC22VlOD-7PC

P13

24-Lead (300-Mil) Molded DIP

PALC22VlOD-1OJC

J64

28-Lead Plastic Leaded Chip Carrier

PALC22VlOD-10PC

P13

24-Lead (300-Mil) Molded DIP

PALC22VlOD-lOJI

J64

28-Lead Plastic Leaded Chip Carrier

PALC22VlOD-10PI

P13

24-Lead (300-Mil) Molded DIP

PALC22VlOD-lODMB

D14

24-Lead (300-Mil) CerDlP

PALC22VlOD-lOKMB

K73

24-Lead Rectangular Cerpack

PALC22VlOD-lOLMB

L64
J64

28-Square Leadless Chip Carrier

PALC22VlOD-15JC
PALC22VlOD -15PC

P13

24-Lead (300-Mil) Molded DIP

PALC22VlOD-15JI

J64

28-Lead Plastic Leaded Chip Carrier

PALC22VlOD-15PI

P13

24-Lead (300-Mil) Molded DIP

PALC22VlOD-15DMB

D14

24-Lead (300-Mil) CerDlP

PALC22VlOD-15KMB

K73

24-Lead Rectangular Cerpack

15
15
15

28-Lead Plastic Leaded Chip Carrier

PALC22VlOD-15LMB

L64

28-Square Leadless Chip Carrier

PALC22VlOD-25JC

J64

28-Lead Plastic Leaded Chip Carrier

PALC22VlOD - 25PC

P13

24-Lead (300-Mil) Molded DIP

PALC22VlOD-25JI

J64

28-Lead Plastic Leaded Chip Carrier

PALC22VlOD-25PI

P13

24-Lead (300-Mil) Molded DIP

PALC22VlOD-25DMB

D14

24-Lead (300-Mil) CerDlP

PALC22V10D-25KMB

K73

24-Lead Rectangular Cerpack

PALC22VlOD-25LMB

L64

28-Square Leadless Chip Carrier

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter

Subgroups

VOH
VOL
VIR
VIL
IJX
Ioz
Icc

1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

Switching Characteristics
Parameter

Subgroups

tpD

9,10,11
9,10,11
9,10,11
9,10,11

teo
ts
tH

Package 'l)'pe

Document#: 38-00185-H

2-67

Operating
Range
Commercial
Commercial
Industrial
Military

II
Commercial
Industrial
Military

Commercial
Industrial
Military

CY7C330

CMOS Programmable
Synchronous State Machine
Features
• lWelve I/O macrocells each having:
- registered, three-state I/O pins
- input register clock select multiplexer
- feed back multiplexer
- output enable (OE) multiplexer
• All twelve macrocell state registers
can be hidden
• User-configurable state registersJK, RS, T, or D
• One input multiplexer per pair of I/O
macrocells allows I/O pin associated
with a hidden macrocell state register
to be saved for use as an input
• Four dedicated hidden registers
• Eleven dedicated, registered inputs

• Three separate clocks-two inputs,
one output
• Common (pin 14-controlled) or
product term-controlled output enable for each I/O pin
• 256 product terms-32 per pair of
macrocells, variable distribution
• Global, synchronous, product termcontrolled, state register set and reset-inputs to product term are
clocked by input clock
• 66-MHz operation
- 3-ns input set-up and I2-ns clock to
output
-15-ns input register clock to state
register clock
• Lowpower
-130mAlcc

Logic Block Diagram

0330-1

Commercial
Military
Commercial

7C330-66
66_6

140

Military

2-68

7C330-50
50_0

7C330-40

50_0

40_0

130
160

7C330-33
33.3

7C330-28
28.5

130
150

150

CY7C331

Asynchronous Registered EPLD
Features
• 'IWelve 110 macrocells each having:
- One state flip-flop with an XOR
sum-of-products input
- One feedback flip-flop with input
coming from the I/O pin
- Independent (product term) set,
reset, and clock inputs on all
registers
-Asynchronous bypass capability on
all registers under product term
control (r s 1)
- Global or local output enable on
three-state 110
- Feedback from either register to
the array
• 192 product terms with variable distribution to macrocells

= =

• 13 inputs, 12 feedback I/O pins, plus 6
shared I/O macrocell feedbacks for a
total of31 tme and complementary
inputs
• High speed: 20 ns maximum tpD
• Security bit
• Space-saving 28-pin slim-line DIP
package; also available in 28-pin
PLCC
• Lowpower
- 90 mA typical Icc quiescent
-180 mA Icc maximum
- UV-erasable and reprogrammable
- Programming and operation 100%
testable

Functional Description
The CY7C331 is the most versatile PLD
available for asynchronous designs. Central resources include twelve full D-type
flip-flops with separate set, reset, and clock
capability. For increased utility, XOR
gates are provided at the D-inputs and the
product term allocation per flip-flop is
variably distributed.

I/O Resources
Pins 1 through 7 and 9 through 14 serve as
array inputs; pin 14 may also be used as a
global output enable for the 110 macrocell
three-state outputs. Pins 15 through 20 and
23 through 28 are connected to 110 macrocells and may be managed as inputs or outputs depending on the configuration and
the macrocell OE terms.

Logic Block Diagram

liD.

liD.

I/O,

1/0.

GND

I.

GND

Vee

10

liD,

liD.

1/0,

1100

C331·1

Selection Guide
Generic Part
Number
CY7C331-20
CY7C331-25
CY7C331-30
CY7C331-40

IcC! (mA)
Com'l
130
120

ts (ns)

tPD (ns)
Mil
160
150
150

Com'l
20
25

Mil
25
30
40

2-69

Com'l
12
12

Mil
15
15
20

tco (ns)
Com'l
Mil
20
25
25
30
40

CY7C331
PLCC

Pin Configuration

The D-type flip-flop that is fed from the array (i.e., the state flipflop) has a logical XORfunction on its input that combines a single
product term with a sum(OR) of a number of product terms. The
single product term is used to set the polarity of the output or to
implement toggling (by including the current output in the product
term).
The Rand S inputs to the flip-flops override the current setting of
the 'Q' output. The S input sets 'Q' true and the R input resets 'Q'
(sets it false). If both Rand S are asserted (true) at once, then the
output will follow the input ('Q' = 'D') (see Table 1).

lbpView

.2>~:'p~gg
l_
Is
I.
GND
17
I.
19

1/0 3
110_

liDs
Vee
GND

liD.
1/0 7

:: ;:: 8
gg ;";,,
--l8
~

~

~

~

Thble 1. RS Truth Thble
C331-2

I/O Resources (continued)
It should be noted that there are two ground connections (pins 8
and 21) which, together with Vee (pin 22) are located centrally on
the package. The reason for this placement and dual-ground structure is to minimize the ground-loop noise when the outputs are
driving simultaneously into a heavy capacitive load.
The CY7C331 has twelve I/O macroceIls (see Figure 1). Each macrocell has two D-type flip-flops. One is fed from the array, and one from
the I/O pin. For each flip-flop there are three dedicated product terms
driving the R, S, and clock inputs, respectively. Each macrocell has
one input to the array and for. each pair of macroceIls there is one
shared input to the array. The macrocell input to the array may be
configured to come from the 'Q' output of either flip-flop.

R

S

Q

1

o

o

1

1
D

o
1

Shared Input Multiplexer
The input associated with each pair of macrocells may be configured by the shared input multiplexer to come from either macrocell; the 'Q' output of the flip-flop coming from the I/O pin is used
as the input signal source (see Figure 2).

Product Term Distribution
The product terms are distributed to the macrocells such that 32
product terms are distributed between two adjacent macrocells.

TO PIN 14 (INVERTED)
OEPTERM

OUT SET PTERM

TO I/O PIN
OUT CLK PTERM

OUT RESET PTERM
IN CLKPTERM
IN SETPTERM
IN RESET PTERM
XORPTERM
ORPTERMS
TO INPUT BUFFER

INPUT FLIP-FLOP

TO SHARED
INPUTMUX

C331·3

TO PIN 14 (INVERTED)

Figure 1. I/O MacroceU

2-70

CY7C331
Product Term Distribution (continued)
The pairing of macrocells is the same as it is for the shared inputs.
Eight ofthe product terms are used in each macrocell for set, reset,
clock, output enable, and the upper part of the XOR gate. This
leaves 16 product terms per pair of macrocells to be divided between the sum-of-products inputs to the two state registers. The
following table shows the I/O pin pairing for shared inputs, and the
product term (PT) allocation to macrocells associated with the I/O
pins (see Table 2).
Thble 2. Product Thrm Distributiou
Macrocell
0
1
2
3
4
5
6
7
8
9
10

11

OIJTPUT FROM
LOGIC ARRAY

Pin Number
28
27
26
25
24
23
20
19
18
17
16
15

Product Terms
4
12
6
10
8
8
8
8
10
6
12
4

MACROCELLA

FEEDBACK TO -----,~
LOGIC ARRAY --~N

INPUT TO
LOGIC ARRAY

-----,71

Q-OUTPUT FROM
INPUT REGISTER OF
110 MACROCELL A

---N
Q-OUTPUT FAOM
INPUT REGISTER OF
I/O MACROCELL B

.---"-'-----'----.
OIJTPUT FROM
LOGIC ARRAY

The CY7C331 is configured by three arrays of configuration bits
(CO, C1, C2). For each macrocell, there is one CO bit and one C1
bit. For each pair of macrocells there is one C2 bit.
There are twelve CO bits, one for each macrocell. If CO is programmed for a macrocell, then the three-state enable (OE) will be
controlled by pin 14 (the global OE). If CO is not programmed,
then the OE product term for that macrocell will be used.
There are twelve C1 bits, one for eachmacrocell. The C1 bit selects
inputs for the product term (PT) array from either the state register
(if the bit is unprogrammed) or the input register (if the bit is programmed).
There are six C2 bits, providing one C2 bit for each pair of macrocells. The C2 bit controls the shared input multiplexer; if the C2 bit
is not programmed, then the input to the product term array comes
from the upper macrocell (A). If the C2 bit is programmed, then
the input comes from the lower macrocell (B).
The timing diagrams for the CY7C331 cover state register, input
register, and various combinational delays. Since internal clocks
are the outputs of product terms, all timing is from the transition of
the inputs causing the clock transition.

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -65°C to + 150°C
Ambient Temperature with
Power Applied ........................ -55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 8 or 21) .................... -O.5V to +7.0V
DC Input Voltage ........................ -3.0V to +7.0V
Output Current into Outputs (LOW) ............... 12 rnA
Static Discharge Voltage ........................ > 1500V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
DC Programming Voltage . . . . . . . . . . . . . . . . . . . . . . . .. 13.0 V

.Operating Range
Range
Commercial

MACROCELLB

FEEDBACK TO -----,~
LOGIC ARRAY

---O-.J

Military[1]

Figure 2. Shared Input Multiplexer

2-71

Ambient
Thmperature
DoC to +70°C

Vee
5V± 10%

-55°C to + 125°C

5V± 10%

Ell

CY7C331
Electrical Characteristics Over the Operating Range[2]
Parameter

Description

Test Conditions

Min. Max.

Unit

VOR

Output HIGH Voltage

Vee = Min., VIN = VIHor VIL
lOR = - 3.2 rnA (Com'l), lOR = - 2 rnA (Mil)

VOL

Output LOW Voltage

Vee = Min., VIN = VIR or VIL
IOL = 12 rnA (Com'l), IOL = 8 rnA (Mil)

Vrn

Input HIGH Voltage

Guaranteed HIGH Input, all Inputs[3]

VIL
IIX

Input LOW Voltage

Guaranteed LOW Input, all Inputs[3]

Input Leakage Current

Vss < VIN < Vee, Vee = Max.

-10

Vss < VOUT < Vee, Vee = Max.
Vee = Max., VOUT = 0.5V[5]

-40
-30
Com'I-20

130

rnA

Com'I-25

120

Mil-25

160

loz

Output Leakage Current

Ise

Output Short Circuit
Currentl4]

leel

Standby Power Supply
Current

Vee = Max., YIN
Outputs Open

= GND,

0.5
2.2

Mil-3~,

Iee2

Power Sup~ly Current at
Frequency 4, 6]

Vee = Max., Outputs Disabled
(in High Z State)
Device Operating at fMAX External (fMAXl)

V

2.4

-40

V
V

0.8

V

+10
+40

!LA
!LA

-90

rnA

rnA

150

Com'l

180

Mil

200

rnA

Capacitance[4]
Parameter

Description

Max.

Unit

CIN

Input Capacitance

VIN = 2.OVatf = 1 MHz

Test Conditions

10

pF

CoUT

Output Capacitance

VOUT = 2.OV at f = 1 MHz

10

pF

Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
4. Thsted initially and after any design or process changes that may affect
these parameters.

5.

6.

2-72

Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground degradation.
Because these input signals are controlled byproduct terms, active input polarity may be of either polarity. Internal active input polarity has
been shown for clarity.

CY7C331
AC Test Loads and Waveforms
R1 3130

R1313Q

OUTP~~ ~(470Q
Mil)
50 pF

~~8~~~NG

I

R2 208Q
(3190 Mil)

-=

ALL INPUT PULSES

OUTP~~ s : n ( 4 7 0Mil)Q

90%

R2 208Q
(3190 Mil) GND

5 pF

~~8~~~NG

-=

SCOPE

I

3.0V

-=

-=

(b)

C331-5

.s. 5 ns

SCOPE

(a)
Equivalent to:

THEVENIN EQUIVALENT (Commercial)

OUTPUT

~

C331·6

Equivalent to:

2.00V = V1hc

THEVENIN EQUIVALENT (Military)

OUTPUT

~

2.02V = V1hm
C331·8

C331·7

Parameter
tpXZ(-)

tpXZ(+)

Vx
1.5V

Output Waveform-Measurement Level
VOH

O.5V~

O.5V~

2.6V
VOL

tpZX(+)

0.5V~

Vthc
Vx

tpZX(-)

tER(-)

tER(+)

Vthc

1.5V

Vx

VOH

0.5V~
O.5V~
O.5V~

2.6V
VOL

tEA(+)

O.5V~

Vthc
Vx

tEA(-)

Vthc

Vx

O.5V~

~~

Vx

~~

C331·9

Vx
0331-10

7~

VOH
0331-11

~~

VOL

0331-12

~~

Vx

C331·13

~~

Vx
0331·14

~~

VOH
C331-15

~~

VOL

C331-16

(c) Test Waveforms and Measurement Levels

Switching Characteristics Over the Operating Rangd2]
Commercial

-20
Parameter
tpD

Description

Min.

Input to Output Propagation Delay(7]
Input Register Clock to Output Delay[8]

-25

Max.

Min.

20
35

tleo
tIOH

Output Data Stable Time from Input C1ock[8]

5

tIS
tJH

Input or Feedback Set-Up Time to Input Register Clock[8]
Input Register Hold Time from Input Clock[8]

2
11

2-73

Max.

Unit

25
40

ns
ns

5
2

ns
ns

13

ns

II

CY7C331
Switching Characteristics .Over the Operating Rangd 2] (continued)
Commercial

-20
Parameter
tIAR
tlRW
tlRR
tIAS
tlSW
tlSR
tWH

Description

Min.

Input to Input Register Asynchronous Reset Delay[8]
Input Register Reset Width[4, 8]
Input Register Reset Recovery Timd4, 8]

-25

Max.

Min.

35
35

Max.

Unit

40

ns
ns

40

35

40

ns
ns

Input to Input Register Asynchronous Set Delay[8]
Input Register Set Width[4, 8]
Input Register Set Recovery Timel4, 8]

35
35

40
40

ns
ns

35

40

Input and Output Clock Width HIGH[8, 9, 10]

12

15

ns

tWL
fMAX!

Input and Output Clock Width LOW[8, 9, 10]

12
27.0

15
23.8

ns
MHz

fMAX2

Maximum Frequency Data Path in Input Registered Mode (Lowest
of 1/tlCO, 1/(tWH + tWL), or 1/(tls + tIH)[8]

28.5

25.0

MHz

tIOH-tIH33X

Output Data Stable from Input Clock Minus Input Register Input
Hold Time for 7C330 and 7C332[12, 13]

0

0

ns

tco

Output Register Clock to Output Delay[9]
Output Data Stable Time from Output Clock[9]

3

3

ns
ns
ns

tOH
ts

Maximum fre~uency with Feedback in Input Registered Mode
(1/(tICO + tiS)) 11]

20

25

Output Register Input Set-Up Time to Output Clock[9]

12

12

tH

Output Register Input Hold Time from Output Clock[9]

8

8

tOAR
tORW

Input to Output Register Asynchronous Reset Delay[9]
Output Register Reset Width[9]
Output Register Reset Recovery Timd9]

tORR
tOAS
tosw
tOSR
tEA
tER
tpzx

Input to Output Register Asynchronous Set Delay[9]
Output Register Set Width[9]
Output Register Set Recovery Timd9]

20
20

25
25
25

20
20

Input to Output Enable Delay[14, 15]
Input to Output Disable Delay[14, 15]
Pin 14 to Output Enable Delay[14, 15]

ns
25

25

20
20

ns
ns
ns

25

ns
ns

25

25

ns
ns

25
20
20

25

ns

20
20

ns
ns

tpxz

Pin 14 to Output Disable Delay[14, 15]

fMAX3

Maximum Fre~uen~ with Feedback in Output Registered Mode
(1/(tco + ts))[ 6,17]

31.2

27.0

MHz

fMAX4

Maximum Fre~uency Data Path in Output Registered Mode (Lowest of 1/ieo, 1/ tWH + tWL), or 1/(ts + tH))[9]

41.6

33.3

MHz

tOH-tIH33X

Output Data Stable from Output Clock Minus Intjut
Register Input Hold Time for 7C330 and 7C332[ ,18]
Maximum Frequency Pipelined Modd lO, 17]

0

0

ns

35.0

30.0

MHz

fMAXS

Noles:
7. Refer to Figure 3, configuration 1.
8. Refer to Figure 3, configuration 2.
9. Refer to Figure 3, configuration 3.
10. Refer to Figure 3, configuration 6.
11. Referto Figure 3, configuration 7.
12. Refer to Figure 3, configuration 9.
13. This specification is intended to guarantee interface compatibility of
the other members of the CY7C330 family with the CY7C331. This
specification is met for the devices noted operating at the same ambient temperature and at the same power supply voltage. These parameters are tested periodically by sampling of production product.

14. Part (a) ofAC Thst Loads and Waveforms used for all parameters except tpzXIo tpXZI, tpzx, and tpxz, which use part (b). Part (c) shows
the test waveforms and measurement levels.
15. Refer to Figure 3, configuration 4.
16. Refer to Figure 3, configuration 8.
17. This specification is intended to guarantee that a state machine configuration created with internal or external feedback can be operated
with output register and input register clocks controlled by the same
source. These parameters are tested by periodic sampling of production product.
18. Refer to Figure 3, configuration 10.

2-74

-

-.,~

CY7C331

-.::=J!" CYPRESS

Switching Characteristics Over the Operating Rangd2] (continued)
Military
-25
Parameter
tpD
tlCO

Description

Min.

Input to Output Propagation Delay[7]
Input Register Clock to Output Delay[4, 8]

tlOH
tiS
tIH

Output Data Stable Time from Input Clock[4. 8]

tlAR

Input to Input Register Asynchronous Reset Delay[4, 8]

tlRW

Input Register Reset Width[8]

45

tlRR
tlAS

Input Register Reset Recovery Timel S]

45

Input or Feedback Set-Up Time to Input Register Clock[8]
Input Register Hold Time from Input Clock[4, 8]

-40

-30

Max.

Unit

25

30

40

ns

45

50

65

ns

Max.

5
5

Min.

Max.

5
5

5
5

45

ns
ns

20

15

13

Min.

50
50

ns
65

65

50

65

ns
ns
ns

Input to Input Register Asynchronous Set Delay[8]
Input Register Set Width[8]
Input Register Set Recovery Timel 8]

45

50

65

ns
ns

45

50

65

ns

tWH
tWL

Input and Output Clock Width High[8, 9, 10]

15

20

25

ns

Input and Output Clock Width Low[8, 9, 10]

fMAX1

Maximum frequency with Feedback in Input Registered
Mode (1I(tlco + tIS»[l1]

15
20.0

20
18.1

25
14.2

MHz

fMAX2

Maximum frequency Data Path in Input Registered Mode
(Lowest of 1ItlCO, l/(tWH + twL), or 1I(tlS + tIH)[8]

22.2

20.0

15.3

MHz

tIOH-tIH33X

Output Data Stable from Input Clock Minus Input Register
Input Hold Time for 7C330 and 7C332[12, 13]

0

0

0

ns

tco

Output Register Clock to Output Delay[9]

tOH
ts

Output Data Stable Time from Output Clock[9]

3

3

3

ns

Output Register Input Set- Up Time to Output Clock[9]
Output Register Input Hold Time from Output Clock[9]

15
10

15

tH

10

20
12

ns
ns

tOAR
tORW

Output Register Reset Width[9]

25

30

40

Output Register Reset Recovery Timd9]

25

30

40

tlSW
tlSR

tORR
tOAS
tosw

45

25

Input to Output Register Asynchronous Reset Delay[9]

Input to Output Register Asynchronous Set Delay[9]
Output Register Set Width[9]
Output Register Set Recovery Timel 9]

tOSR
tEA

Input to Output Enable Delay[14, 15]

tER
tpzx

50

65

30

25

40

30

25

ns

40

25

30

40

25

30

40

ns
ns

40

30

ns

ns
ns
ns
ns

Input to Output Disable Delay[14, 15]
Pin 14 to Output Enable Delay[14, 15]

25
25
20

30
30
25

40
40

tpxz

Pin 14 to Output Disable Delay[14, 15]

20

25

35

fMAX3

Maximum Frequen~ with Feedback in Output Registered
Mode )1I(tco + ts)[ 6,17]

25.0

22.2

16.6

ns
MHz

fMAX4

Maximum Frequency Data Patb in Output Registered Mode
(Lowest of l/tco, 11(tWH + tWL), or 1/(ts + tH)[9]

33.3

25.0

20.0

MHz

tOH-tIH33X

Output Data Stable from Output Clock Minus Input Register Input Hold Time for 7C330 and 7C332[13, 18]
Maximum Frequency Pipelined Model 10, 17]

0

0

0

ns

28.0

23.5

18.5

MHz

fMAX5

2-75

35

ns
ns
ns

« ~YPRESS

CY7C331

Switching Waveforms
INPUT OR
I/O PIN

I/O INPUT
REGISTER
CLOCK[6]
OUTPUT
REGISTER
CLOCKI6]

OUTPUT

SET AND
RESET
INPUTsl6J

1_-----1--

tpO[21] ------~

C331-17

*=.,~

OEPRODUCT~

TERM INPUT[6,15]
PIN 14 AS lJE[24]

.,~
tpxz

I---

OUTPUT

""

OUTPUT
REGISTER
RESET INPUT[6, 9]

~tER-

OUTPUT
REGISTER
CLOCK[6,9]
OUTPUT
REGISTER
SET INPUT[6, 9]

//.

b

tpzx

//.
'\"

,/

"-

-tOAR-

')E
-

toRW---I t:=tORR

71{

t

I/O INPUT
REGISTER RESET
INPUT[6,B] _ _ _ _ _ _ _ _ _ _ _ _ _....
I/O INPUT
REGISTER
CLOCK[6, B]

tOAS

tlAR -

tlRW

toSR

I

-tosw

~

~

tlRR

I

~I_ - - -

tIAS~~ • i i~
"

I/O INPUT
REGISTER
SET INPUT[6, B] - - - - - - - - - - - - - - - - - - - - . . . .

tlSR

tlSW

C331-1B
Notes:
19, Output register is set in '!tansparent mode. Output register set and reset inputs are in a HIGH state.
ZO, Dedicated input or input register set in '!tansparent mode. Input register set and reset inputs are in a HIGH state,
21. Combinatorial Mode. Reset and set inputs of tbe input and output registers should remain in a HIGH state at least until the output responds
at tpD. When returning set and reset inputs to a LOW state, one of
these signals should go LOW a minimum of toSR (set input) or toRR
(reset input) prior to tbe other. This guarantees predictable register
states upon exit from Combinatorial mode,

22. When entering tbe Combinatorial mode, input and output register set
and reset inputs must be stable in a HIGH state a minimum of tISR or
tIRR and tOSR or toRR respectively prior to application of logic input
signals.
23, When returning to the input and/or output Registered mode, register
set and reset inputs must be stable in a WW state a minimum oftIsR
or tIRR and tOSR or tORR respectively prior to the application of tbe
register clock input.
24. Refer to Figure 3, configuration 5.

2-76

CY7C331

CONFIGURATION 1

PIN

l---------C~==j

INPUT OR 1/0 PIN

PIN

CONFIGURATION 2

1___~C~LO~C~K/~S/!!:R~-C~==j

r

UNREGISTERED
INPUT OR 1/0 PIN

INPUT
PRODUCT
TERM
ARRAY

INPUT REGISTER

II
OUTPUT REGISTER
PIN

CONFIGURATION 3

PRODUCT
TERM
ARRAY

UNREGISTERED
INPUT OR 1/0 PIN
CLOCK/SIR

PIN

INPUT
UNREGISTERED
INPUT OR I/O PIN

PIN

CONFIGURATION 4

l---------c~==j

PRODUCT

1-------,

TERM
ARRAY

INPUT OR 1/0 PIN
PIN

1/0 PIN

INPUT OR I/O PIN

PIN
14

CONFIGURATION 5

INPUT OR 1/0 PIN
PIN
INPUT OR 1/0 PIN

INPUT REGISTER

CONFIGURATION 6

UNREGISTERED
INPUT OR 1/0 PIN

OUTPUT REGISTER

PRODUCT
TERM
ARRAY

CLOCK

PIN
0331-19

CLOCK INPUT

Figure 3. Timing Configurations

2-77

CY7C331

'rcYPRESS

CONFIGURATION 7

PIN

DATA INPUT
PRODUCT
TERM
ARRAY

CONFIGURATION 8

PIN

CLOCK INPUT

0331-20

CONFIGURATION 9

CONFIGURATION 10

C331-21

CLOCK

Figure 3. Timing Configurations (continued)

2-78

~

CY7C331

'Jill

~,CYPRESS
CY7C331 Logic Diagram (Upper Half)

o

•

UI

24

5'

.

,;:~~':~lIl1l1l1l1l1l1l1l1l1l1l1l1l1l1l1l1l1l1l1!1~~~!![~;J
__
0 }-;:-.:(O)
JIIIIIIII~rrl;~~(CO"I)
LI984
. ".
4~llllllll~~q~(CO"I)
D LI19I
I

--

~4(CO

I)

4-o-j!=

-0 1

1-<

3

....

r-

I~rr= ~

nod. 33

~

I L1~g.

Ir~

.

(CO.

(C2)

1.21152

~

I)

1~1=
5

6

7

~L4911111118-D--~~~~~Hili(a>--)
60
L3918

....-

~

-0

node 32

LUgl' (C2)

rIll III

..

I
TO LOWER SECTION

2-79

C331·22

fI

CY7C331
CY7C331 Logic Diagram (Lower Half)

TO UPPER SECTION

I
,....L.
L5952

Hm

(CO •. l)

20

.~

0

LS9"

r-'
node 31
L11921 ( C2)

10

l7930

IL1~4(CO.. I)

10

rr=r

-t..r"

r"1.!!J
r-'
node 30
L11926 (C2)

11

-

LI052

12
LII20
~(CO.. l)

-.l!J
12-rJrF

r
nod. 29
L11931 (e2)

LIII60
~(CO •• l)

iLlll

T

C331-23

2-80

CY7C331
Ordering Information

teo

(mA)

tpD
(ns)

ts
(ns)

(ns)

130

20

12

20

ICCl

160

120

150

150

25

25

30

40

15

12

15

20

25

25

30

40

Ordering Code

Package
Name

Package 1)'pe

CY7C331-20HC

H64

28-Pin Windowed Leaded Chip Carrier

CY7C331-2OJC

J64

28-Lead Plastic Leaded Chip Carrier

CY7C331-20PC

P21

28-Lead (300-Mil) Molded DIP

CY7C331-20WC

W22

28-Lead (300-Mil) Windowed CerDlP

CY7C331-25DMB

D22

28-Lead (300-Mil) CerDIP

CY7C331-25HMB

H64

28-Pin Windowed Leaded Chip Carrier

CY7C331-25LMB

L64

28-Square Leadless Chip Carrier

CY7C331-25QMB

Q64

28-Pin Windowed Leadless Chip Carrier

CY7C331-25TMB

T74

28-Lead Windowed Cerpack

CY7C331-25WMB

W22

28-Lead (300-Mil) Windowed CerDIP

CY7C331-25HC

H64

28-Pin Windowed Leaded Chip Carrier

CY7C331-25JC

J64

28-Lead Plastic Leaded Chip Carrier

CY7C331-25PC

P21

28-Lead (300-Mil) Molded DIP

CY7C331-25WC

W22

28-Lead (300-Mil) Windowed CerDIP

CY7C331-30DMB

D22

28-Lead (300-Mil) CerDIP

CY7C331-30HMB

H64

28-Pin Windowed Leaded Chip Carrier

CY7C331-30LMB

L64

28-Square Leadless Chip Carrier

CY7C331-30QMB

Q64

28-Pin Windowed Leadless Chip Carrier

CY7C331- 30TMB

T74

28-Lead Windowed Cerpack

CY7C331-30WMB

W22

28-Lead (300-Mil) Windowed CerDIP

CY7C331-40DMB

D22

28-Lead (300-Mil) CerDIP

CY7C331-40HMB

H64

28-Pin Windowed Leaded Chip Carrier

CY7C331-40LMB

L64

28-Square Leadless Chip Carrier

CY7C331-40QMB

Q64

28-Pin Windowed Leadless Chip Carrier

CY7C331-40TMB

T74

28-Lead Windowed Cerpack

CY7C331-40WMB

W22

28-Lead (300-Mil) Windowed CerDIP

2-81

Operating
Range
Commercial

Military

II
Commercial

Military

Military

~

CY7C331

:'rcYPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter

Subgroups

VOH

1,2,3

VOL

1,2,3

VIR

1,2,3

VIL

1,2,3

IIX

1,2,3

Ioz

1,2,3

Icc!

1,2,3

Switching Characteristics
Parameter

Subgroups

tIS
tIR
tWH
tWL
tco
tPD
tIAR
tIAS
tpxz
tpzx
tER
tEA
ts
tH

9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9, 10, 11
9,10,11
9,10,11

Document #: 38-00066-D

2-82

CY7C332

Registered Combinatorial
EPLD
Features
• 12 I/O macrocells each having:
- Registered, latched, or transparent
array input
- A choice of two clock sources
- Global or local output enable (OE)
- Up to 19 product terms (PTs) per
output
- Product term (PT) output polarity
control
• 192 product terms with variable
distribution to macrocells
- An average of 14 PTs per macrocell
sum node
• 'I\vo clock inputs with configurahle
polarity control

Functional Description

• 13 input macrocells, each having:
- Complementary input
- Register, latch, or transparent
access
- 'I\vo clock sources
• 15 ns tpD max.
• Lowpower
-120 mA typical Icc quiescent
-180mAmax.
- Power-saving "Miser Bit" feature
• Security fuse
• 28-pin slim-line package; also available in 28-pin PLCC
• UV-erasable and reprogrammable
• Programming and operation 100%
testable

The CY7C332 is a versatile co
PLD with I/O registers
are 25 array inputs; each
that may be configured as
or simple buffer. 0
three-state contro
location of prod
is varied so t

•

Logic Block Diagram

C332-1

Iecl (mA)
Commercial

trs (ns)

treo/tpD (ns)

Military

Commercial

130

Military

Commercial
3

Military

18/15

120

160

20

23(20

3

4

120

150

25

25

3

4

150

30

2-83

4

CY7C335

Universal Synchronous EPLD
Features
• 100-MHz output registered
operation
• Twelve I/O macrocells, each having:
- Registered, three-state I/O pins
-Input and output register clock select multiplexer
- Feed back multiplexer
- Output enable (OE) multiplexer
• Bypass on input and output registers
• All twelve macrocell state registers
can be hidden
• User configurable I/O macrocells to
implement JK or RS flip-flops and T
or D registers
• Input multiplexer per pair of I/O macrocells allows I/O pin associated with
a hidden macrocell state register to be
saved for use as an input
• Four dedicated hidden registers
• Twelve dedicated registered inputs
with individually programmable bypass option

• Three separate clocks-two input
clocks, two output clocks
• Common (pin l4-controlled) or
product term-controlled output enable for each I/O pin
• 256 product terms-32 per pair of
macrocells, variable distribution
• Global, synchronous, product termcontrolled, state register set and reset-inputs to product term are
clocked by input clock
-2-ns input set-up and 9-ns output
register clock to output
-lOons input register clock to state
register clock
• 2S-pin, 300-mil DIP, LeC, PLCC
• Erasable and reprogrammable
• Programmable security bit

Functional Description
The CY7C335 is a high-performance, erasable, programmable logic device (EPLD)
whose architecture has been optimized to
enable the user to easily and efficiently

construct very high performance state machines.
The architecture of the CY7C335, consisting ofthe user-configurable output macrocell, bidirectionalI/O capability, input registers, and three separate clocks, enables
the user to design high-performance state
machines that can communicate either
with each other or with microprocessors
over bidirectional parallel buses of userdefinable widths.
The four clocks permit independent, synchronous state machines to be synchronized to each other.
The user-configurable macrocells enable
the designer to designate JK-, RS-, T-, or
D-type devices so that the number of product terms required to implement the logic
is minimized.
The CY7C335 is available in a wide variety
of packages including 28-pin, 300-mil plastic and ceramic DIPs, PLCCs, and LCCs.

Logic Block Diagram

1/0.

1/0 7

16

Vss

I,

I/O.

Vss

Vee

2-84

I/O,

I/O,

1,/CLK3

loIClK2

1/02

I/O,

ClK1

1/00

C335-1

CY7C335
Pin Configurations
LCC

PLCC

'fupView

I,
I.
15
VSS

16
17
Is

'fupView

4 3 2'1' 282726
...
25
24
7
23
8
22
9
21
10
20
19
11
12131415161718

1/03
I/O.

I,
I.
I.

liD,
liD.
liD.

VSS

Vee

10
I,

Vss
1/0 6

I,

1/07

1/05

Vee
VSS
1/06

liD,

C335-2

fI

C335-3

Selection Guide
Maximum Operating
Frequency (MHz)
ICCl (rnA)

CY7C335-100
100

Commercial
Military
Commercial
Military

CY7C335-83
83.3
83.3
140

140

CY7C335-66
66.6
66.6
140
160

160

CY7C335-50
50
50
140

CY7C335-40

160

160

40.0

Architecture Configuration Bits
The architecture configuration bits are used to program the multiplexers. The function of the architecture bits is outlined in Table 1.
Table 1. Architecture Configuration Bits
Architecture
Configuration Bit

Number of Bits

Value

Function

CO

Output Enable
SelectMUX

12 Bits, 1 Per
I/O Macrocell

0---Virgin State

I-Programmed

Output Enable Controlled by Pin 14

Cl

State Register
Feed Back MUX

12 Bits, 1 Per
I/O Macrocell

0---Virgin State

State Register Output is Fed Back to Input Array

1-Programmed

I/O Macrocell is Configured as an Input and
Output of Input Path is Fed to Array

I/O Macrocell
Input Register
Clock Select
MUX

12 Bits, 1 Per
I/O Macrocell

0---Virgin State

ICLK1 Controls the Input Register I/O Macrocell
Input Register Clock Input

1-Programmed

ICLK2 Controls the Input Register I/O Macrocell
Input Register Clock Input

C3

Input Register
Bypass MUXI/O Macrocell

12 Bits, 1 Per
I/O Macrocell

0---Virgin State

Selects Input to Feedback MUX from Input
Register

I-Programmed

Selects Input to Feedback MUX from I/O pin

C4

Output Register
Bypass MUX

12 Bits, 1 Per
I/O Macrocell

0---Virgin State

Selects Output from the State Register

1-Programmed

Selects Output from the Array, Bypassing the State
Register

C5

State Clock MUX

16 Bits, 1 Per I/O
Macrocell and 1 Per
Hidden Macrocell

0---Virgin State

State Clock 1 Controls the State Register

1-Programmed

State Clock 2 Controls the State Register

C6

Dedicated Input
Register Clock
SelectMUX

12 Bits, 1 Per
Dedicated Input
Cell

0---Virgin State

ICLKI Controls the Input Register I/O Macrocell
Dedicated Input Register Clock Input

1-Programmed

ICLK2 Controls the Input Register I/O Macrocell
Dedicated Input Register Clock Input

C2

2-85

Output Enable Controlled by Product Term

CY7C335
Table 1. Architecture Configuration Bits (continued)
Architecture
Configuration Bit

Number of Bits

Value

Function

C7

Input Register
Bypass MUXInput Cell

12 Bits, 1 Per
Dedicated Input
Cell

O-Virgin State

Selects Input to Array from Input Register

1-Programmed

Selects Input to Array from Input Pin

C8

ICLK2 Select
MUX

1 Bit

O-Virgin State

Input Clock 2 Controlled by Pin 2

1-Programmed

Input Clock 2 Controlled by Pin 3

ICLKl Select
MUX

1 Bit

SCLK2 Select
MUX

1 Bit

I/O Macrocell
Pair Input
SelectMUX

6 Bits, 1 Per
I/O Macrocell
Pair

C9
ClO
CX
(11-16)

O-Virgin State

Input Clock 1 Controlled by Pin 2

1-Programmed

Input Clock 1 Controlled by Pin 1

O-Virgin State

State Clock 2 Grounded

l-Programmed

State Clock 2 Controlled by Pin 3

O-Virgin State

Selects Data from I/O Macrocell Input Path of
Macrocell A of Macrocell Pair

1-Programmed

Selects Data from I/O Macrocell Input Path of
Macrocell B of Macrocell Pair

1
INPUT REGISTER

~

INPUT
PIN

D

Q

ICLK2

O~

INPUT
CLOCK
1
MUX

....

...

TO ARRAY

":?

d7

'---

ICLK1

0

INPUT
REG
BYPASS
MUX

- >

C6

C335-4

Figure 1. CY7C335 Input Macrocell

2-86

CY7C335

co
PIN 14: OE

o

OUTPUT ENABLE PRODUCT TERM

OUTPUT REG
BYPASS MUX
OUTPUT
ENABLE 1-_ _
MUX

+,

SET PRODUCT TERM

EX OR PRODUCT TERM

!
SCLK1
SCLK2
RESET PRODUCT TERM
TO ARRAY

o
FEED
BACK
MUX

C1
ICLK1

INPUT REGISTER

o

C2

o
INPUT
CLOCK
MUX

Q

D

C3

ICLK2

0335-5

TO ARRAY

CX(11 -16)

FROM ADJACENT MACROCELL

Figure 2. CY7C335 Input/Output Macrocell

2-87

§it

CY7C33S

jEYPRESS
SET PRODUCT TERM

S

D

Q

!
SCLKl
SCLK2

RESET PRODUCT TERM

C335-6

Figure 3. CY7C33S Hidden Macrocell

SCLK2 TO OUTPUT MACROCELLS AND HIDDEN MACROCELLS
PIN 1
ICLKl

ICLK2

SCLKl TO OUTPUT MACROCELLS AND HIDDEN
MACROCELLS

PIN 2

C8

PIN3

C335-7

Figure 4. CY7C33S Input Clocking Scheme

2-88

CY7C335
Maximum Ratings
(Above which the useful life maybe impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to + 150°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Volt~ge to Ground Potential
(Pm 22 to Pins 8 and 21) ................. -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -0.5V to +7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Output Current into Outputs (Low) ............... 12 mA

Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
DC Programming Voltage ......................... 13.0V
Operating Range
Ambient
Temperature
DoC to +75°C

5V ± 10%

-40°C to +85°C

5V ± 10%

-55°Cto +125°C

5V ± 10%

Range
Commercial
Industrial
Military[l]

Vee

Electrical Characteristics Over the Operating Rangd2]
Parameter
VOH
VOL

Description
Output HIGH Voltage
Output LOW Voltage

V/H

Input HIGH Level

VIL

Input LOW Level

Ilx

Input Leakage Current

Ioz

Output Leakage Current

Ise

Output Short Circuit Current

IcC!

Standby Power
Supply Current

Iee2

Power Supply Current
at Frequency[5]

Test Conditions

Min.

Vee = Min.,
VIN = V/H or VIL

IOH - -3.2mA

Com'l

IOH - -2mA

MillInd

Vee = Min.,
VIN = V/H or VIL

IOL

= 12mA

Com'l

Mil/Ind
IOL = 8mA
Guaranteed Input Logical HIGH Voltage for All InputsL3j
Guaranteed Input Logical LOW Voltage for All Inputs L3 j

VIN ~ Vee, Vee = Max.
= Max., Vss~ VOUT~ Vee
= Max., VOUT = 0.5VL4,'j
Vee = Max., VIN = GND

Max.

Unit

2.4

V
0.5

V

0.8

V

2.2

V

Vss~

-10

10

Vee
Vee

-40

40

f!A
f!A

-30

Outputs Open

Vee = Max.,
Outputs Disabled (in High Z State),
Device Operating at fMAX External (fMAXS)

-90

mA

Com'l

140

mA

Mil/Ind

160

rnA

Com'l

180

mA

MillInd

200

mA

Capacitance[5]
Parameter
CIN
COUT

Description
Input Capacitance
Output Capacitance

Test Conditions
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz

Min.

Max.
10
10

Unit
pF
pF

Notes:
1.

2.
3.

tA is the "instant on~' case temperature.
See the last page ofthis specification for Group A subgroup testing information.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

4.
S.

2-89

Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by ground degradation.
Thsted initially and after any design or process changes that may affect
these parameters.

~~YPRESS

CY7C335

AC Test Loads and Waveforms (Commercial)
R1313Q
(470Q MILIIND)

OUTP:~:=Fl
INCLUDING
JIG AND
SCOPE

I

so pF

-=-

ALL INPUT PULSES
3.0V---GND

-=-

.5.3 ns
C335-8

(a)

I

90%

R2208Q
(319Q MiI/lnd)

1

R = 12SQ (190Q MIL)

OUTPUTO
C

= so pF

T
OV

~

I
OV

VTH = 2.00V
(2.02V MIL)

1.5V

tpxz(+)

2.6V

tpzx (+)

Vth

OV

tCER (-)

1.5V

tCER (+)

2.6V

tCliA(+)

Vth

VOH

Vx
VOH

Vx

~
~

O.5V
O.5V

O.5V

~~

~
~

~

0.5V
O.5V

·O.5V

~
~

~
~

O.5V

VOL

Vth

~

O.5V

Vx
tCEA(-)

1

Vx

OV

C335-10

Output Waveform-Measurement Level

VOL

Vth

1

(d) Three-state Delay Load (Load 2)

Vx
tpzx (-)

'Wo

c=sPFT

C335-9

Vx

tpxz(-)

I

R = 12SQ (190Q MIL)

OUTPUTO

(c) Thevenin Equivalent (Load 1)

Parameter

C335-11

(b)

~

:

~~

Figure S. Test Waveforms

2-90

.~
~

Vx

C335-12

Vx
C335-13

VOH
C335-14

VOL

C335 15

Vx

C335-16

Vx
C335-17

VOH
C335-18

VOL

C335-19

.....;:=,..

-:~;J~YPRESS

CY7C335

Commercial AC Characteristics
7C33S·tOO
Parameter

Description

Min.

Max.

7C33S·S3

7C33S·66

Min. Max. Min. Max.

7C33S·S0
Min.

Max.

Unit
ns

Combinatorial Mode Parameters
tpD

Input to Output Propagation Delay

15

15

20

25

tEA

Input to Output Enable

15

15

20

25

ns

Input to Output Disable
tER
Input Registered Mode Parameters

15

15

20

25

ns

tWH

Input and Output Clock Width HIGHt' J

4

5

6

8

ns

tWL

Input and Output Clock Width LOWl'J

4

5

6

8

ns

tiS

Input or Feedback Set-Up Time to Input Clock

2

2

2

3

ns

tIH

Input Register Hold Trrne from Input Oock

2

2

2

3

ns

tlCO

Input Register Clock to Output Delay

tIOH

Output Data Stable Trrne from Input Oock

18

tIOH - tIH Output Data Stable from Input Clock Minus I~ut Register Hold Time for 7C330, 7C332, and 7C335[
33x

18

20

25

ns

3

3

3

3

ns

0

0

0

0

ns

tpzx

Pin 14 Enable to Output Enabled

12

12

15

20

tpxz

Pin 14 Disable to Output Disabled

12

12

15

20

ns

fMAX!

Maximum Frequency of (2) CY7C335s in Input Registered
Mode (Lowest of l/(tlCO+tIS) & l/(tWL +tWH)[5]

50

50

45.4

35.7

MHz

fMAX2

Maximum Frequency Data Path in Input Registered Mode
(Lowest of (l/(tlCO), l/(tWH+tWL), 1/(tls+trn»[5]

55.5

55.5

50

40

MHz

tlCEA

Input Clock to Output Enabled

17

17

20

25

ns

Input Clock to Output Disabled
tlCER
Output Registered Mode Parameters

15

15

20

25

ns

ns

tCBA

Output Clock to Output Enabledt' J

17

17

20

25

ns

tCER

Output Clock to Output Disab1edl'J

15

15

20

25

ns

ts

Output Register Input Set-Up Time from Output Clock

8

9

12

15

tH

Output Register Input Hold Time from Output Clock

0

0

0

0

tco

Output Register Clock to Output Delay

9

10

12

15

ns

tC02

Input Output Register Clock or Latch Enable to
Combinatorial Output Delay (Through Logic Array)[5]

17

18

23

30

ns

ns
ns

tOH

Output Data Stable Time from Output Clock

2

2

2

2

ns

tOHZ

Output Data Stable Time From Output Clock (Through
Memory Array)[5]

3

3

3

3

ns

tOHZ-tIH

Output Data Clock Stable Time From Output Clock Minus Input Register Hold Timel5]

0

0

0

0

ns

fMAX3

Maximum Frequency with Internal Feedback in Output
Registered Model5]

100

83.3

66.6

50

MHz

fMAX4

Maximum Frequency of (2) CY7C335s in Output Refstered
Mode (Lowest of l/(tco + ts) & l/(tWL + tWH)[5

58.8

50

41.6

33.3

MHz

fMAXS

Maximum Frequency Data Path in Output Registered
Mode (Lowest of l/(tCO), l/(tWL + tWH), 1/(ts + tH»[5]

111

100

83.3

62.5

MHz

tOH - tIH
33x

Output Data Stable from Output Clock Minus Inyut Register Hold Time for 7C330, 7C332, and 7C335[6

0

0

0

0

ns

2-91

II

CY7C335
Commercial AC Characteristics (continued)
Parameter
Pipelined Mode Parameters

17C33S-100 I 7C33S-83
7C33S-66 I 7C33S-S0
Min. Max. Min. Max. Min. Max. I Min. I Max.

Description

I
I Unit

tcos

Input Clock to Output Clock

10

12

15

20

ns

fMAX6

Maximum Frequency Pipelined Mode (Lowest of
1/(tcos), 1/(tco), 1/(tWL + tWH», 1/(tIS + tIH)[5]

100

83.3

66.6

50

MHz

fMAX7

Maximum Frequency of (2) CY7C335s in Pipelined Mode
(Low~st of 1/(tco + tIS) or Vtcos)

90.9

83.3

66.6

50

MHz

Power-Up Reset Parameters
Power-Up Reset Time15, 7J

1

tpOR

1

1

1

!-IS

Military/lndustrial AC Characteristics
7C335-83
7C335-66
7C33S-50
7C33S-40
Min. Max. Min. Max. Min. Max. Min. Max.

Parameter
Description
Combinatorial Mode Parameters
Input to Output Propagation Delay
tPD
Input to Output Enable
tEA
Input to Output Disable
tER
Input Registered Mode Parameters
Input and Output Clock Width HIGH[5]
tWH
Input and Output Clock Width LOW[5]
tWL

20
20
20

5
5
3
3

Input or Feedback Set-Up Tllfle to Input Oock
tIS
Input Register Hold Time from Input Oock
tIH
Input Register Clock to Output Delay
tICO
Output Data Stable Time from Input Oock
tIOH
tIOH - tIH Output Data Stable from Input Oock Minus Influt
33x
RegIster Hold Time for 7C330, 7C332, and 7C33 [6]

Notes:
6. This specification is intended to guarantee interface compatibility of
!be other members of the CY7C330 family with the CY7C335. This
specification is met for !be devices operating at !be same ambient tem·
perature and at the same power supply voltage.

25
3
0

15
15

30
3
0

20
20

30
30

ns
ns
ns
ns
ns
ns
ns

38.4

38.4

35,7

29.4

43.4

43.4

40

33.3

MHz

20
20

20
20

25

25

30
30

ns
ns

20
20

20
20

25
25

30
30

ns
ns
ns
ns
ns
ns

12
0

11
22

2-92

10
10
4
4

ns
ns
ns

ns
ns
MHz

10
0

7.

30
30
30

25
8
8
3
3

3
0
15
15

Output Register Input Set-Up Time to Output Clock
Output Register Input Hold Time from Output Clock
Output Register Clock to Output Delay
OutputRegisterOockor Latch Enable to Combinatorial
Output Delay (Through Logic Array) [5]

25
25

23

23

Pin 14 Enable to Output Enabled
Pin 14 Disable to Output Disabled
Maximum Frequency of (2) CY7C335s in Input
fMAX!
Registered Mode (Lowest of V(trco + trs) &
1/(tWL + tWH»[5]
Maximum Frequency Data Path in Input Registered
fMAX2
Mode (Lowest of (V(trco), 1/(tWH + tWL),
1/(trs + tIH»[5]
Input Oock to Output Enabled
trcBA
Input Clock to Output Disabled
tICER
Output Registered Mode Parameters
Output Clock to Output Enabled [5]
tCEA
Output Clock to Output Disabled [5]
tCER

tco
tC02

6
6
3
3

3
0

tpzx
tpxz

ts
tH

20
20
20

Unit

15
0
12
23

20
0
15
30

20
35

This part has been designed with !be capability to reset during system
power-up. Following power-up, !be input and output registers will be
reset to a logic LOW state. The output state will depend on how the
array is programmed.

CY7C335
Military/Industrial AC Characteristics (continued)
Parameter
tOH2

Output Data Stable Time from Output Clock
Output Data Stable Time From Output Clock
(Through Memory Array)[S)

tOH2-tIH

tOH

7C335-66
7C335-83
7C335-50
Min. Max. Min. Max. Min. Max.
2
2
2

Description

7C335-40
Min. Max.
2

Unit
ns

3

3

3

3

ns

Output Data Clock Stable Time From Output Clock
Minus Input Register Hold TimelS)

0

0

0

0

ns

fMAX3

Maximum Frequency with Internal Feedback in Output Registered ModelS)

83.3

66.6

50

40

MHz

fMAX4

Maximum Frequency of (2) CY7C335s in Output Registered Mode (Lower of l/(tco + ts) & l/(tWL + tWH»[S)

47.6

41.6

33.3

25

MHz

fMAXS

Maximum Frequency Data Path in Output Registered
Mode (Lowest of 1/(tco), lI(tWL + tWH), l/(ts + tH»[S)

90.9

83.3

62.5

50

MHz

0

0

0

0

ns

12
83.3

15

20

25

ns

66.6

50

40

MHz

71.4

66.6

50

40

MHz

tOH - tIH Output Data Stable from Output Clock Minus InRut
Register Hold Time for 7C330, 7C332, and 7C335[6)
33x
Pipelined Mode Parameters
tcos

Input Clock to Output Clock

fMAX6

Maximum Frequency Pipe lined Mode
(Lowest of 1/(tcos), l/(tIS), or 1/(tCO», 1/(tIS + tIH)[S)

Maximum Frequency of (2) CY7C335s in Pipelined
Mode (Lowest of l/(tco + tIS) or 1/tCOS)
Power-Up Reset Parameters
I Power-Up Reset TimelS, 7)
tpOR

fMAX7

I

2-93

I

1

I

1

1

1

Its

II

Silt

~

-.r; CYPRESS

CY7C335

Switching Waveform
INPUT OR
I/O PIN

INPUT REG.
CLOCK

~-------------- ~os -------+~----~-OUTPUT
REG. CLOCK

OUTPUT

t------ tpD - - - - I

114-----

1------------ tER
PIN 14
ASO'E

tlCER

-------~

-----------~

c

_ _ _ _f - -pxz- - . t

tpzx
C335-20

Power-Up Reset Waveform[7]
VCC

OUTPUT

CLOCK

C335-21

2-94

-

-,~

CY7C335

~'CYPRESS

Block Diagram (Page 1 of 2)

node=34

node=33

TO LOWER SECTION

C335-22

2-95

-.

-~

==============~CY~7~C~33~5

, CYPRESS

Block Diagram (Page 2 of 2)

TO UPPER SECTION

I

II

II

II

H

J-r
1+

§-I~ ~

D

=

11~

_-r

node=37

node=32

rr
node=31

1--"''''

(C4,5)

I:If

~

L

..;;

node=36

=
~ r--t=I

@]-[}

t---"''''

(C4,5)

i"D

1= ~

~ ~

(C~rC

II1II
II II lIlT

o

"""0",

1m:' 24'11111111 321111 40'IIIITTTIIII4s 1111'56'n~
I

, 1'6

TH,

6'4 ' SET

node=30'" ()F

C335-23

2-96

~

.r~YPRESS

CY7C335

Ordering Information
fMAX
(MHz)

ICCI
(mA)

100

140

83.3

83.3

66.6

66.6

50

160

140

160

140

140

Package
Name

Package 1Ype

CY7C335-100HC

H64

28-Pin Windowed Leaded Chip Carrier

CY7C335 -lOOJC

J64

28-Lead Plastic Leaded Chip Carrier

Ordering Code

CY7C335 -IOOPC

P21

28-Lead (300-Mil) Molded DIP

CY7C335 -lOOWC

W22

28-Lead (300-Mil) Windowed CerDIP

CY7C335-83DI

D22

28-Lead (300-Mil) CerDIP

CY7C335-83HI

H64

28-Pin Windowed Leaded Chip Carrier

CY7C335 - 83PI

P21

28-Lead (300-Mil) Molded DIP

CY7C335-83WI

W22

28-Lead (300-Mil) Windowed CerDIP

CY7C335-83DMB

D22

28-Lead (300-Mil) CerDIP

CY7C335-83HMB

H64

28-Pin Windowed Leaded Chip Carrier

CY7C335 - 83LMB

28-Square Leadless Chip Carrier

CY7C335-83QMB

L64
Q64

CY7C335 -83WMB

W22

28-Lead (300-Mil) Windowed CerDIP

CY7C335 - 83HC

H64

28-Pin Windowed Leaded Chip Carrier

CY7C335-83JC

J64

28-Lead Plastic Leaded Chip Carrier

Commercial

Industrial

Military

28-Pin Windowed Leadless Chip Carrier

CY7C335-83PC

P21

28-Lead (300-MiI) Molded DIP

CY7C335 - 83WC

W22

28-Lead (300-MiI) Windowed CerDIP

CY7C335-66DI

D22

28-Lead (300-MiI) CerDIP

CY7C335-66HI

H64

28-Pin Windowed Leaded Chip Carrier

CY7C335-66PI

P21

28-Lead (300-MiI) Molded DIP

CY7C335-66WI

W22

28-Lead (300-MiI) Windowed CerDIP

CY7C335-66DMB

D22

28-Lead (300-MiI) CerDIP

CY7C335 - 66HMB

H64

28-Pin Windowed Leaded Chip Carrier

CY7C335 -66LMB
CY7C335-66QMB

L64
Q64

28-Pin Windowed Leadless Chip Carrier

CY7C335-66WMB

W22

28-Lead (300-MiI) Windowed CerDIP

CY7C335-66HC

H64

28-Pin Windowed Leaded Chip Carrier

CY7C335-66JC

J64

28-Lead Plastic Leaded Chip Carrier

CY7C335-66PC
CY7C335-66WC

P21
W22

28-Lead (300-MiI) Windowed CerDIP

CY7C335-50HC

H64

28-Pin Windowed Leaded Chip Carrier

CY7C335-50JC

J64

28-Lead Plastic Leaded Chip Carrier

CY7C335 - 50PC

P21

28-Lead (300-MiI) Molded DIP

CY7C335-50WC

W22

28-Lead (300-MiI) Windowed CerDIP

2-97

Operating
Range

Commercial

Industrial

Military

28-Square Leadless Chip Carrier

Commercial

28-Lead (300-MiI) Molded DIP
Commercial

•

CY7C335

:"rcYPRESS
Ordering Infonnation (continued)

fMAx

ICCI

(MHz)

(rnA)

50

160

40

160

Ordering Code

Package
Name

CY7C33S - SODI

D22

28-Lead (300-Mil) CerDIP

CY7C33S-S0HI

H64

28-Pin Windowed Leaded Chip Carrier

CY7C33S - SOPI

P21

28-Lead (300-MiI) Molded DIP

CY7C33S-S0WI

W22

28-Lead (3OO-Mil) Wmdowed CerDIP

CY7C33S-S0DMB

D22

28-Lead (300-MiI) CerDIP

CY7C33S-50HMB

H64

28-Pin Windowed Leaded Chip Carrier

CY7C335 - 50LMB

L64

28-Square Leadless Chip Carrier

CY7C335-50QMB

Q64

28-Pin Windowed Leadless Chip Carrier

CY7C335-50WMB

W22

28-Lead (3OO-Mil) Wmdowed CerDIP

CY7C33S-40DI

D22

28-Lead (300-Mil) CerDIP

CY7C335-40HI

H64

28-Pin Windowed Leaded Chip Carrier

CY7C335-40PI

P21

28-Lead (300-Mil) Molded DIP

CY7C335-40WI

W22

28-Lead (3OO-Mil) Windowed CerDIP

CY7C335-40DMB

D22

28-Lead (300-Mil) CerDIP

CY7C335-40HMB

H64

28-Pin Windowed Leaded Chip Carrier

CY7C335 -40LMB
CY7C335-40QMB

L64
Q64

28-Pin Windowed Leadless Chip Carrier

CY7C335-40WMB

W22

28-Lead (3OO-Mil) Windowed CerDIP

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIH
VIL
IIX
Ioz
lee

Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

Switching Characteristics
Parameter

Subgroups

tpD

9,10,11

tIeo
tIS
teo

9,10,11
9,10,11
9,10,11

ts
tH

9,10,11
9,10,11
9,10,11

teas

Package 'JYpe

Document #: 38-00186-C

2-98

28-Square Leadless Chip Carrier

Operating
Range
Industrial

Military

Industrial

Military

GENERAL INFORMATION

II

SMALLPLDs

BI

CPLDs

II
II
II

FPGAs
DEVELOPMENT SYSTEMS
QUALITY

III

PACKAGES

II

SarcYPRESS
Table of Contents

Table of Contents
Page Number

CPLDs (Complex PLDs)
Device
Uitra39000
Ultra39192
Ultra39256
Uitra39320
Ultra39384
Uitra39448
Ultra39512
FLAsH370 CPLD Family
CY7C371
CY7C372
CY7C373
CY7C374
CY7C375
FLAsH370i ISR CPLD Family
CY7C371i
CY7C372i
CY7C373i
CY7C374i
CY7C375i
CY7C340 EPLD Family
CY7C341B
CY7C341
CY7C342B
CY7C342
CY7C343
CY7C343B
CY7C344
CY7C344B
CY7C346
CY7C346B

Description
UltraLogic High-Density CPLD Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
UitraLogic 192-Macrocell CPLD ................................................ 3-2
UltraLogic 256-Macrocell CPLD ................................................ 3-3
UitraLogic 320-Macrocell CPLD ................................................ 3-4
UitraLogic 384-Macrocell CPLD ................................................ 3-5
UitraLogic 448-Macrocell CPLD ................................................ 3-6
UitraLogic 512-Macrocell CPLD ................................................ 3-7
UitraLogic High-Density Flash CPLDs ........................................... 3-8
UitraLogic 32-Macrocell Flash CPLD ........................................... 3-15
UitraLogic 64-Macrocell Flash CPLD ........................................... 3-24
UltraLogic 64-Macrocell Flash CPLD ........................................... 3-33
UitraLogic 128-Macrocell Flash CPLD .......................................... 3-43
UltraLogic 128-Macrocell Flash CPLD .......................................... 3-54
UitraLogic High-Density Flash CPLDs .......................................... 3-66
UltraLogic 32-Macrocell Flash CPLD ........................................... 3-73
UitraLogic 64-Macrocell Flash CPLD ........................................... 3-82
UitraLogic 64-Macrocell Flash CPLD ........................................... 3-91
UltraLogic 128-Macrocell Flash CPLD ......................................... 3-100
UitraLogic 128-Macrocell Flash CPLD ......................................... 3-110
Multiple Array Matrix High-Density EPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-122
192-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-128
192-MacrocellMAXEPLD ................................................... 3-140
128-Macrocell MAX EPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-141
128-Macrocell MAX EPLDs .................................................. 3-158
64-MacrocellMAXEPLD .................................................... 3-159
64-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-159
32-MacrocellMAXEPLD .................................................... 3-175
32-MacrocellMAXEPLD .................................................... 3-175
128-Macrocell MAX EPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-189
128-Macrocell MAX EPLDs . . .. . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-189

ADVANCED INFORMATION

Ultra39000 ™

UltraLogic ™ High-Density
CPLD Family
Features

Functional Description

• High density
-192-512 macrocells
-64-224 I/O pins
- Multiple input/clock pins
• High performance
-125 -100 MHz performance
-10-12nstpD
-5-6nsts
-5.5-6.5 ns teo
• In·System Reprogrammable (ISR ,. )
• Fast CMOS technology
• Fully PCI compliant
• Full JTAG compatibility
• 3.3V or 5V operation
• Programmable speed/power options
• Simple timing model
• No hidden delays
• Packages
- 84 to 304 pins
- PLCC, TQFP, and PQFP
• Programmable security bit
• Warp3 ~ CAE developmeut system
-VHDLinput
- ViewLogic ~ graphical user interface
- Schematic capture (ViewDraw ~ )
-Available on Sun, HP, and Windows m platforms
• Warp2 m /Warp2+ m VHDL Compiler
-VHDLinput
- Functional simulator
- Available on Sun, HP, and Windows
platforms

The Ultra39000 ,. family of high-density,
high-performance Complex Programmable Logic Devices (CPLDs) provide an
in-system reprogrammable solution complete with full Joint Test Action Group
(JTAG IEEE1149.1) compatability. Each
member of the Ultra39000 Family of fast,
reconfigurable CPLDs has been designed
to bring the high performance and the ease
of use of 22V10s to ultra high-density
PLDs. And since they are designed and
fabricated with Cypress's state-of-the-art
electrically-alterable Flash technology,
users can program the devices in-circuit,
which simplifies both the development and
manufacturing processes. This, in turn,
speeds time to market and reduces product
inventory costs. The entire family will operate at 3.3V or 5V and is fully compliant
with the PCI Local Bus Specification. It
will operate with speeds of up to 125 MHz.
All of the macrocells in each of the
Ultra39000 Family members are distributed among a number of distinct logic
blocks. For example the Ultra39192 has 12
logic blocks, while the Ultra39512 has 32.
Each logic block contains 16 macrocells
along with a product term array and a fast,
intelligent product term matrix. Each logic
block in the Ultra39000 architecture is
connected through a Programmable Interconnect that produces extremely fast and
predictable paths through the device
All members ofthe Ultra39000 Familyfeature an abundant number ofI/O resources
with 64 to 2241/0 pins as well as four dedicated inputs/clocks and provide both fast
synchronous and asynchronous clocking

capabilities. Each member is also both upwardly and downwardly pin-compatible
with the other family members, providing a
built-in upgrade path.
Additionally, the Ultra39000 Family features a programmable speed/power option
that allows users to optimize designs for
either ultra-fast performance or ultra-low
power. The family also provides slew rate
control for each of the outputs that reduces
switching noise. And finally, the
Ultra39000 Family features a very simple
timing model that results in parameters
that are not dependent on the device resources utilized or the type of application
being implemented.
Development support for the entire family
of Cypress Programmable Logic Devices
including Ultra39000 is provided through
all of Cypress's state-of-the-art VHDLbased tools as well as a vast array of third
party solutions. Wap3 is a sophisticated
design tool based on ViewLogic's CAE design environment, which integrates Cypress's IEEE1164-compliant VHDL synthesis engine, full schematic capture capability (ViewDraw'·), a VHDL waveform
simulator, VHDL debugger, and a fullfunction timing simulator. This integrated
tool features mixed-mode entry allowing
designs to be entered textually, schematically, or in a combination of both. It is supported on PCs running Windows, and on
Sun and Hewlett Packard workstations. In
addition, both Warp2 and Wa1p2 + are lowcost VHDLcompilers offering VHDL synthesis capability and a functional simulator. See the separate software and third
party data sheets for further information.

Ultra39000 Selection Guide
Device

Macrocells

Pin Count

Max. I/O Pins

fMAX(MHz)

tpD (ns)

ts (ns)

teo (ns)

39192

192

84/160

64/128

125

10

5

5.5

39256

256

160/208

128/160

125

10

5

5.5

39320

320

208/240

160/192

125

10

5

5.5

39384

384

240

192

100

12

6

6.5

39448

448

240/304

192/224

100

12

6

6.5

39512

512

304

224

100

12

6

6.5

Warp2, Wmp2+, Warp3, ISR, Ultra39000, and UltraLogic are trademarks of Cypress Semiconductor Corporation.
ViewLogic and ViewDraw are trademarks of ViewLogic Corporation.
Windows is a trademark of Microsoft Corporation.

Document #: 38-00475

3-1

Ell

ADVANCED INFORMATION

Ultra39192

UltraLogic ™ 192-Macrocell CPLD
Features

Functional Description

•
•
•
•
•
•
•
•
•
•

The Ultra39192 is a high-density, highperformance Complex Programmable
Logic Device (CPLD) providing in-system
reprogrammability (ISR) and full Joint
Test Action Group (JTAG IEEE1l49.1)
compatibility. It is part of the
Ultra39000 m family of fast, reconfigurable CPLDs, which has been designed to
bring the high performance and the ease of
use of 22V10s to ultra high-density PLDs.
The entire family is also fully compliant
with the PCI Local Bus Specification and
will operate at either 3.3V or SY.
The 192 macrocells in the Ultra39192 are
divided between 12 logic blocks. Each logic block contains 16 macrocells along with
a product term array and a fast, intelligent
product term matrix. Each logic block in
the Ultra39000 architecture is connected
through a Programmable Interconnect

192 macrocells in 12 logic blocks
In-System Reprogrammable (ISR m )
Fully PCI compliant
Full JTAG compatability
3.3V or 5V operation
Programmable speed/power options
64 and 128 I/O pins
4 dedicated inputs/clocks
No hidden delays
Highspeed
-fMAX = 125 MHz
-tpD IOns
-ts=5ns
-teo 5.5 ns
• Available in 84-pin PLCC and 160-pin
TQFP packages
• Pin compatible with the Ultra39256

=

=

Logic Block Diagram

I/O

that produces extremely fast and predictable paths through the device.
All members of the Ultra39000 family feature an abundant number ofI/O resources.
The Ultra39192 contains either 64 or 128
I/O pins, as well as four dedicated inputs/
clocks, and provides both fast synchronous
and asynchronous clocking capabilities.
Additionally, the Ultra39192 features a
prograrnmablespeedlpoweroptionthatallows users to optimize designs for eitherultra-fast performance or ultra-low power.
The family also provides slew rate control
for each of the outputs, which reduces
switching noise. And finally, the
Ultra39192 features a very simple timing
model that results in parameters that are
not dependent on the device resources utilized or the type of application being implemented.

I/O

I/O~>--I
INPUTS/
CLOCKS

INPUTS/
CLOCKS

Ultra39192-1

UltraLogic, ISR, and Ultra39000 are trademarks of Cypress Semiconductor Corporation.
Document #: 38-00473

3-2

ADVANCED INFORMATION

Ultra39256

UltraLogic ™ 256-Macrocell CPLD
Features

Functional Description

•
•
•
•
•
•
•
•
•
•

The Ultra39256 is a high·density, highperformance Complex Programmable
Logic Device (CPLD) providing in-system
reprogrammability (ISR) and full Joint
Test Action Group (JTAG IEEE1149.1)
compatibility. It is part of the
Ultra39000 m Family of fast, reconfigurable CPLDs, which has been designed to
bring high performance and the ease of
use of 22VlOs to ultra high-density PLDs.
The entire family is also fully compliant
with the PCI Local Bus Specification and
will operate at either 3.3V or 5V.
The 256 macrocells in the UItra39256 are
divided between 16 logic blocks. Each logic block contains 16 macrocells along with
a product term array and a fast, intelligent
product term matrix. Each logic block in
the Ultra39000 architecture is connected
through a Programmable Interconnect

256 macrocells in 16 logic blocks
In.System Reprogrammable (ISR m )
Fully PCI compliant
Full JTAG compatibility
3.3V or 5V operation
Programmable speed/power options
12S or 160 I/O pins
4 dedicated inputs/clocks
No hidden delays
Higb speed
- fMAX = 125 MHz
-tPD = IOns
-ts = 5ns
-teo = 5.5 ns
• Available in 160·pin TQFP and
20S·pin PQFP packages
• Pin compatible with the U1tra39192
and the UItra39320

that produces extremely fast and predictable paths through the device.
All members of the Ultra39000 family fea·
ture an abundant numberofl/O resources.
The Ultra39256 contains either 128 or 160
I/O pins, as well as four dedicated inputs/
clocks, and provides both fast synchronous
and asynchronous clocking capabilities.
Additionally, the Ultra39256 features a
programmable speed/power option that allows users to optimize designs for eitherul·
tra-fast performance or ultra·low power.
The family also provides slew rate control
for each of the outputs which reduces
switching noise. And finally, the
Ultra39256 features a very simple timing
model that results in parameters that are
not dependent on the device resources utilized or the type of application being implemented.

Logic Block Diagram

I/O

Programmable

H

LOGIC
BLOCK

~

INPUTS/
CLOCKS

INPUTS/
CLOCKS

~

LOGIC
BLOCK

~
Interconnect

I/O

I/O

I/O

I/O

UltraLogic, ISR, and Ultra 39000 are trademarks of Cypress Semiconductor Corporation
Document #: 38-00474

3-3

I/O

EI

ADVANCED INFORMATION

UltraLogic

1M

Features

Functional Description

•
•
•
•
•
•
•
•
•
•

The Ultra39320 is a high-density, highperformance Complex Programmable
Logic Device (CPLD) providing in-system
reprogrammability (ISR) and full Joint
lest Action Group (JTAG IEEE1149.1)
compatibility. It is part of the
Ultra39000 ~ family of fast, reconfigurable CPLDs, which have been designed to
bring the high performance and the ease of
use of 22VI0s to ultra high-density Pills.
The entire family is also fully compliant
with the PCI Local Bus Specification and
will operate at either 3.3V or Sv.
The 320 macrocells in the U1tra39320 are
divided between 20 logic blocks. Each logic block contains 16 macrocells along with
a product term array and a fast, intelligent
product term matrix. Each logic block in
the Ultra39000 architecture is connected
through a Programmable Interconnect

320 macrocells in 20 logic blocks
In-System Reprogrammable (ISR ,. )
Fully PCI compliant
Full JTAG compatibility
3.3V or 5V operation
Programmable speed/power options
160 or 192 I/O pins
4 dedicated inputs/clocks
No hidden delays
High speed
- fMAX = 125 MHz
-tpD
IOns
-ts = 5ns
-teo = 5.5 ns
• Available in 20S-pin and 240-pin
PQFP package
• Pin compatible with the U1tra39256

=

Ultra39320

320-Macrocell CPLD
that produces extremely fast and predictable paths through the device.
All members of the U1tra39000 family feature an abundant number ofI/O resources.
The U1tra39320 contains 160 or 192 I/O
pins as well as four dedicated inputs/clocks
and provides both fast synchronous and
asynchronous clocking capabilities.
Additionally, the U1tra39320 features a
programmablespeedlpoweroptionthatallows users to optimize designs for either ultra-fast performance or ultra-low power.
The family also provides slew rate control
for each of the outputs, which reduces
switching noise. And finally, the
Ultra39320 features a very simple timing
model that results in parameters that are
not dependent on the device resources utilized or the type of application being implemented.

Logic Block Diagram
I/O

110

.--.......

I/O

I/O

/1/0

I/O

INPUTS/
CLOCKS

INPUTSI
CLOCKS

I/O

I/O

I/O

U~ra39320·1

U1traLogic, ISR, and Ultra39000 are trademarks of Cypress Semiconductor Corporation
Document #: 38-00471

3-4

ADVANCED INFORMATION

Ultra39384

UltraLogic ™ 384-Macrocell CPLD
Features

Functional Description

•
•
•
•
•
•
•
•
•
•

The U!tra39384 is a high-density, highperformance Complex Programmable
Logic Device (CPLD) providing in-system
reprogrammability (ISR) and full Joint
Test Action Group (JTAG IEEE1149.1)
compatibility. It is part of the
Ultra39000 m family of fast, reconfigurable CPLDs, which have been designed to
bring the high performance and the ease of
use of 22VlOs to ultra high-density PLDs.
The entire family is also fully compliant
with the PCI Local Bus Specification and
will operate at either 3.3V or 5Y.

384 macrocells in 24 logic blocks
In-System Reprogrammable (ISR ,. )
Fully PCI compliant
Full JTAG compatibility
3_3V or 5V operation
Programmable speed/power options
192 I/O pins
4 dedicated inputs/clocks
No hidden delays
High speed
- fMAX = 100 MHz
-tpD 12ns
-ts = 6ns
-teo 6.5 ns
• Available in 240-pin PQFP package
• Pin compatible with the U1tra39448

=

=

The 384 macrocells in the Ultra39384 are
divided between 24 logic blocks. Each logic block contains 16 macrocells along with
a product term array and a fast, intelligent
product term matrix. Each logic block in
the Ultra39000 architecture is connected
through a Programmable Interconnect

that produces extremely fast and predictable paths through the device.
All members of the Ultra39000 family feature an abundant number ofI/O resources.
The Ultra39384 contains 192 I/O pins as
well as four dedicated inputs/clocks and
provides both fast synchronous and asynchronous clocking capabilities.
Additionally, the UJtra39384 features a
programmable speed/power option that allows users to optimize designs for either
ultra-fast performance or ultra-low power.
The family also provides slew rate control
for each of the outputs, which reduces
switching noise. And finally, the
Ultra39384 features a very simple timing
model that results in parameters that are
not dependent on the device resources utilized or the type of application being implemented.

Logic Block Diagram
I/O

I/O

I/O

I/O

I/O

I/O

I/O

INPUTS/
CLOCKS
I/O

16 1~oo

I/O

BLOCK

I/O

I/O

I/O

I/O

~

I/O

UItra39384-1

UltraLogic, ISR, and Ultra39000 are trademarks of Cypress Semiconductor Corporation
Document #: 38-00472

3-5

II

ADVANCED INFORMATION

UltraLogic

TM

Features

Functional Description

•
•
•
•
•
•
•
•
•
•

The U1tra39448 is a high-density, highperformance Complex Programmable
Logic Device (CPLD) providing in-system
reprogrammability (ISR) and full Joint
lest Action Group (JTAG IEEE1149.1)
compatibility. It is part of the
Ultra39000~ family of fast, reconfigurable CPLDs, which have been designed to
bring the high performance and the ease of
use of 22VI0s to ultra high-density PLDs.
The entire family is also fully compliant
with the PCI Local Bus Specification and
will operate at either 3.3V or Sv.
The 448 macrocells in the Ultra39448 are
divided between 28 logic blocks. Each logic block contains 16 macrocells along with
a product term array and a fast, intelligent
product term matrix. Each logic block in
the U1tra39000 architecture is connected
through a Programmable Interconnect

448 macrocells in 28 logic blocks
In-System Reprogrammable (lSR ~ )
Fully PCI compliant
Full JTAG compatibility
3.3Vor SV operation
Programmable speed/power options
192 or 224 I/O pins
4 dedicated inputs/clocks
No hidden delays
Higb speed
-fMAX 100 MHz
-tpD = 12n8
-ts = 6ns
-lco= 6.Sns
• Available in 240-pin and 304-pin
PQFP packages
• Pin compatible witb tbe U1tra39384
and U1tra39S12

=

Ultra39448

448-Macrocell CPLD
that produces extremely fast and predictable paths tbrough the device.
All members of the U1tra39000 family feature an abundantnumberofl/O resources.
The U1tra39448 contains eitber 192 or 224
I/O pins as well as four dedicated inputs/
clocks and provides both fast synchronous
and asynchronous clocking capabilities.
Additionally, the U1tra39448 features a
programmable speed/power option that ailows users to optimize designs for eitberultra-fast performance or ultra-low power.
The family also provides slew rate control
for each of tbe outputs, which reduces
switching noise. And finally, the
U1tra39448 features a very simple timing
model that results in parameters that are
not dependent on tbe device resources utilized or the type of application being implemented.

Logic Block Diagram

INPUTS!

INPUTS!

CLOCKS

CLOCKS

UHra3944B·1

UltraLogic, ISR, and U1tra39000 are trademarks of Cypress Semiconductor Corporation
Document #: 38-00469

3-6

ADVANCED INFORMATION

UltraLogic

TM

Features

Functional Description

•
•
•
•
•
•
•
•
•
•

The Ultra39512 is a high-density, highperformance Complex Programmable
Logic Device (CPLD) providing in-system
reprogrammability (ISR) and full Joint
Thst Action Group (JTAG IEEE1149.1)
compatibility. It is part of the
Ultra39000 ~ family of fast, reconfigurable CPLDs, which have been designed to
bring the high performance and the ease of
use of 22VlOs to ultra high-density PLDs.
The entire family is also fully compliant
with the PCI Local Bus Specification and
will operate at either 3.3V or 5Y.
The 512 macrocells in the Ultra39512 are
divided between 32 logic blocks. Each logic block contains 16 macrocells along with
a product term array and a fast, intelligent
product term matrix. Each logic block in
the Ultra39000 architecture is connected
through a Programmable Interconnect

512 macrocells in 32 logic blocks
In-System Reprogrammable (ISR
Fully PCl compliant
Full JTAG compatibility
3.3V or 5V operation
Programmable speed/power options
2241/0 pins
4 dedicated inputs/clocks
No hidden delays
Highspeed
-fMAX 100 MHz
-tpD = 12ns
-ts 6ns
-teo = 6.5 ns
• Available in 304-pin PQFP package
• Pin compatible with the U1tra39448
N

=

=

)

UItra39512

512-Macrocell CPLD
that produces extremely fast and predictable paths through the device.
All members of the Ultra39000 family feature an abundant numberofl/O resources.
The Ultra39512 contains 224 I/O pins as
well as four dedicated inputs/clocks and
provides both fast synchronous and asynchronous clocking capabilities. essing and
decoding capabilities.
Additionally, the Ultra39512 features a
programmable speed/power option that allows users to optimize designs for eitherultra-fast performance or ultra-low power.
The family also provides slew rate control
for each of the outputs, which reduces
switching noise. And finally, the
Ultra39512 features a very simple timing
model that results in parameters that are
not dependent on the device resources utilized or the type of application being implemented.

Logic Block Diagram
I/O

I/O

I/O

I/O

I/O

I/O

I/O

INPUTS/
CLOCKS

INPUTS/
CLOCKS

B6
~
K

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Ultra39512M 1

UltraLogic, ISR, and Ultra39000 are trademarks of Cypress Semiconductor Corporation.
Document #: 38-00470

3-7

II

FLASH370™
CPLD Family

CYPRESS

UltraLogic ™ High-Density Flash CPLDs

Features
• Flash erasable CMOS CPLDs
• High density
- 32-128 macroceUs
-32-128 I/O pins
- Multiple clock pins
• High speed
-tpD 8.5-12ns
-ts = 5-7ns
-teo 6-7ns
• Fast Programmable Interconnect Matris (PIM)
-Uniform predictable delay, indepeudent of routing
• Intelligent product term allocator
- 0-16 product terms to any macrocell
- Provides product term steering on
an individual basis
- Provides product term sharing
among local macrocells
- Prevents stealing of neighboring
product terms
• Simple timing model
- No fanout delays
- No expander delays
- No dedicated vs. I/O pin delays
- No additional delay through PIM
- No penalty for using.full16 product terms
- No delay for steering or sharing
product terms
• Flexible clocking
- 2-4 clock pins per device
- Clock polarity control
• Security bit and user ID supported

=

=

• Packages
-44-160 pins
- PLCC, CLCC, PGA, and TQFP
packages

• Wtup2N/Wa1p2+ m
- Low-cost, text-based design tool,
PLD compiler
-IEEE 1164-compliant VHDL
- Available on PC and Sun platforms
• Wa1p3 N CAE development system
-VHDLinput
- ViewLogic graphical user interface
- Schematic capture (ViewDraw m)
- VHDL simulation (ViewSim N )
-Available on PC, HP, and Sun platforms

General Description
The FLASH370 m family of CMOS CPWs
provides a range of high-density programmable logic solutions with unparalleled
performance. Each member of the family
is designed with Cypress's state-of-the-art
0.65-micron Flash technology. All of the
devices are electrically erasable and reprogrammable, simplifying product inventory
and reducing costs.
The FLASH370 family is designed to bring
the flexibility, ease of use and performance
of the 22VlO to high-density CPWs. The
architecture is based on a number of logic
blocks that are connected by a Programmable Interconnect Matrix (PIM). Each
logic block features its own product term
array, product term allocator array, and 16
macrocells. The PIM distributes signals
from one logic block to another as well as
all inputs from pins.
The family features a wide variety of densities and pin counts to choose from. At each
density there are two packaging options to
choose from-one that is I/O intensive and
another that is register intensive. For example, the CY7C374 and CY7C375 both
feature 128 macrocells. On the CY7C374
half of the macrocells are buried and the
device is available in 84-pin packages. On

the CY7C375 all of the macrocells are fed
to I/O pins and the device is available in
160-pin packages. Figure 1 shows a block
diagram of the CY7C374/5.

Functional Description
Programmable Interconnect Matrix
The Programmable Interconnect Matrix
(PIM) consists of a completely global routing matrix for signals from I/O pins and
feedbacks from the logic blocks. The PIM
is an extremely robust interconnect that
avoids fitting and density limitations.
Routing is automatically accomplished by
software and the propagation delay
through the PIM is transparent to the user.
Signals from any pin or any logic block can
be routed to any or all logic blocks.
The inputs to the PIM consist of all I/O
and dedicated input pins and all macrocell
feedbacks from within the logic blocks.
The number of PIM inputs increases with
pincount and the number of logic blocks.
The outputs from the PIM are signals
routed to the appropriate logic block(s).
Each logic block receives 36 inputs from
the PIM and their complements, allowing
for 32-bit operations to be implemented
in a single pass through the device. The
wide number of inputs to the logic block
also improves the routing capacity of the
FLASH370 family.
An important feature of the PIM involves
timing. The propagation delay through the
PIM is accounted for in the timing specifications for each device. There is no additional delay for traveling through the PIM.
In fact, all inputs travel through the PIM.
Likewise, there are no route-dependent
timing parameters on the FLAsH370 devices. The worst-case PIM delays are incorporated in all appropriate FLAsH370
specifications.

FLAsH370 Selection Guide
Device
371
372
373
374
375

Pins
44
44
84
84
160

Macrocells
32
64
64
128
128

Dedicated Inputs
6
6
6
6
6

I/O Pins
32
32
64
64
128

3-8

Flip-Flops
44
76
76
140
140

Speed (tpD)
8.5
10
10
12
12

Speed (fMAX>
143
125
125
100
100

=

-~

FLAsH370

&r;CYPRESS
CLOCK
INPUTS

4
INPUT/CLOCK
MACROCELLS

INPUT
MACROCELLS

4

36

36

16

16

36

36
16

PIM

16

36

36

16

16

36

36

16

16

EI

flash370-1

Figure 1. CY7C374/5 Block Diagram

Functional Description (continued)

Product Term Array

-Routing signals through the PIM is completely invisible to the user.
All routing is accomplished 100% by software-no hand routing is
necessary. Wap and third-party development packages automatically route designs for the F'LAsH370 family in a matter of minutes.
Finally, the rich routing resources of the FLASH370 family accommodate last minute logic changes while maintaining fixed pin assignments.
Logic Block

Each logic block features a 72 x 86 programmable product term
array. This array is fed with 36 inputs from the PIM, which originate from macrocell feedbacks and device pins. Active LOW and
active HIGH versions of each of these inputs are generated to
create the full 72-inputfield. The 86 product terms in the array can
be created from any of the 72 inputs.

The logic block is the basic building block of the FLASH370 architecture. It consists of a product term array, an intelligent productterm allocator, 16 macrocells, and a number ofl/O cells. The number of I/O cells varies depending on the device used.
There are two types of logic blocks in the FLASH370 family. The
first type features an equal number (16) of I/O cells and macrocells
and is shown in Figure 2. This architecture is best for I/O-intensive
applications. The second type oflogic block features a buried macrocell along with each I/O macrocell. In other words, in each logic
block, there are eight macrocells that are connected to I/O cells
and eight macrocells that are internally fed back to the PIM only.
This organization is designed for register-intensive applications
and is displayed in Figure 3. Note that at each FLAsH370 density
(except the smallest), an I/O intensive and a register-intensive device is available.

Of the 86 product terms, 80 are for general-purpose use for the 16
macrocells in the logic block. Four of the remaining six product
terms in the logic block are output enable (OE) product terms.
Each ofthe OE product terms controls up to eight of the 16 macrocells and is selectable on an individual macrocell basis. In other
words, each I/O cell can select between one of two OE product
terms to control the output buffer. The first two of these four OE
product terms are available to the upper half of the I/O macrocells
in a logic block. The other two OE product terms are available to
the lower half of the I/O macrocells in a logic block. The final two
product terms in each logic block are dedicated asynchronous set
and asynchronous reset product terms.
Product Term Allocator
Through the product term allocator, software automatically distributes product terms among the 16 macrocells in the logic block
as needed. A total of 80 product terms are available from the local
product term array. The product term allocator provides two important capabilities without affecting performance: product term
steering and product term sharing.

3-9

FLAsH370
r ... - - - - - .... - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .. - - - - - - - - - - - - - - - - - - ..

,

2

6

0-16
PRODUCT
TERMS

72x86
FROM'--............,3....
6_~
PRODUCT TERM
PIM
ARRAY

80

PRODUCT
TERM
ALLOCATOR

16

TO
PIM

,..... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _16_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

J

ftash37Q-2

Figure 2. Logic Block for CY7C371, CY7C373, and CY7C375 (I/O Intensive)

j---------------------------------------------------------------.,

,
,
,
,
,
,
,
,
,
,
,
,
,
,

f2

J MACRO-I
0-16

---.,..<

,
,
,
,
,
,
,

TO
PIM

,

J

MACRO-rCELL

0-16
PRODUCT
TERMS

72x86

PRODUCT
TERM
ALLOCATOR

80

PRODUCT TERM
ARRAY

I

0-16
PRODUCT
TERMS

··
··

1/0

~

tJcens
3,5,7

···

C~LL

I

0-16
PRODUCT4

"RMS

-~

2

J MACRO-I
I

,
,
,
,
,
,
,
,

,
,

C~LL

PRODUCT
TERMS ~

6

,
FROM ,'
, 36
PIM

I

I"'''1-]
CELL
16

16

·

1/0

~
toLs

11,13,15

2

,
,
,
'...--..
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,

,

··
··

'...--..

,
,
,
,
,
,
,
,
,
,
,
,

-

8

,----------------------------------------------------- ----------~
ftash37D-3

Figure 3. Logic Block for CY7C372 and CY7C374 (Register Intensive)

3-10

FLASH370
Product Term Steering

Each ofthese product terms features programmable polarity. This
allows the registers to be set or reset based on an AND expression
or an OR expression.

Product term steering is the process of assigning product terms to
macrocells as needed. For example, if one macrocell requires ten
product terms while another needs just three, the product term allocator will "steer" ten productterms to one macrocell and three to
the other. On FLAsH370 devices, product terms are steered on an
individual basis. Any number between 0 and 16 product terms can
be steered to any macrocell. Note that 0 product terms is useful in
cases where a particular macrocell is unused or used as an input
register.

Clocking of the register is very flexible. Depending on the device,
either two or four global synchronous clocks are available to clock
the register. Furthermore, each clock features programmable polarity so that registers can be triggered on falling as well as rising
edges (see the Dedicated/Clock Inputs section). Clock polarity is
chosen at the logic block level.
At the output of the macrocell, a polarity control mux is available
to select active LOW or active HIGH signals. This has the added
advantage of allowing significant logic reduction to occur in many
applications.
The FLAsH370 macrocell features a feedback path to the PIM separate from the I/O pin input path. This means that if the macrocell
is buried (fed back internally only), the associated I/O pin can still
be used as an input.

Product Term Sharing
Product term sharing is the process of using the same product term
among multiple macrocells. For example, if more than one output
has one or more product terms in its equation that are common to
other outputs, those product terms are only programmed once.
The FLAsH370 product term allocator allows sharing across groups
offouroutput macrocells in a variable fashion. The software automatically takes advantage of this capability-the user does not
have to intervene. Note that greater usable density can often be
achieved if the user "floats" the pin assignment. This allows the
compiler to group macrocells that have common product terms adjacently.

Buried Macrocell
Some ofthe devices in the FLASH370 family feature additional macrocells that do not feed individual I/O pins. Figure 5 displays the
architecture of the I/O and buried macrocells for these devices.
The I/O macrocell is identical to the one on devices without buried
macrocells.
The buried macrocell is very similar to the I/O macrocell. Again, it
includes a register that can be configured as combinatorial, a D
flip-flop, a T flip-flop, or a latch. The clock for this register has the
same options as described for the I/O macrocell. The primary difference between the I/O macrocell and the buried macrocell is that
the buried macrOcell does not have the ability to output data directly to an I/O pin.

Note that neither product term sharing nor product term steering
have any effect on the speed ofthe product. All worst-case steering
and sharing configurations have been incorporated in the timing
specifications for the FLAsH370 devices.
FLAsH370 Macrocell
I/O Macrocell
Within each logic block there are 8 or 16 I/O macrocells depending
on the device used. Figure 4 illustrates the architecture ofthe I/O
macrocell. The macrocellfeatures a register that can be configured
as combinatorial, a D flip-flop, a T flip-flop, or a level-triggered
latch.
The register can be asynchronously set or asynchronously reset at
the logic block level with the separate set and reset product terms.

One additional difference on the buried macrocell is the addition
of input register capability. The buried macrocell can be configured to aetas an input register (D-type or latch) whose input comes
from the I/O pin associated with the neighboring macrocell. The
output of all buried macrocells is sent directly to the PIM regardless of its configuration.

I/O MACROCELL
r - -

I/O CELL

r------------------ ..
0-16 PRODUCT
TERMS

"0'
I

U1""T"r-t"

I

C5 C6
______________

C2

C3

______________________________________ J

FEEDBACK TO PIM
ASYNCHRONOUS
BLOCK RESET
ASYNCHRONOUS
BLOCK PRESET

FEEDBACK TO PIM
flash37G-4

2 BANK OE TERMS

Figure 4. I/O Macrocell
Note:
1. C1 is not used on the CY7C371 and CY7C372 since the mux size is 2:1

3-11

J

II

*:~YPRESS

FLAsH370
permanently off (input only), or dynamically controlled by one of
two OE product terms.

FLAsH370 I/O Cell

The I/O cell on the FLAsH370 devices is illustrated along with the
I/O macrocell in Figures 4 and 5. The user can program the I/O cell
to change the way the three-state output buffer is enabled and/or
disabled. Each output can be set permanently on (output only),

Dedicated/Clock Inputs

Six pins on each member of the FLASH370 family are designated as
input-only. There are two types of dedicated inputs on FLAsH370
devices: input pins and input/clock pins. Figure 6 illustrates the ar-

I/O MACROCELL
r - -

FROM PTM
I/O CELL

r------------------ ..

,

0-'6 PRODUCT
TERMS

I
I

,

"O~

"1" -.-.-......_ _....

,...... -

C5 C6

--------------.1

_________ J

BURIED MACROCELL

r - -

FROM PTM

0-'6 PRODUCT
TERMS

FEEDBACK TO PIM
FEEDBACK TO PIM
FEEDBACK TO PIM
ASYNCHRONOUS
BLDCKRESET
ASYNCHRONOUS
BLOCK PRESET

flash370·5

2 BANK OE TERMS

Figure 5. I/O and Buried Macrocells
INPUT PIN

TOPIM
FROM CLOCK
POLARITY MUXES

Figure 6. Input Pins
Note:
2. C9 is not used on the CY7C371 and CY7C372 since the mux size is 2:1

3-12

FLAsH370
TO CLOCK MUX ON
ALL INPUT MACROCElLS

r---------------,I

INPUT/CLOCK PIN

I
I

TO CLOCK MUX

~~~LOCK

I
I

L__ ~!::~~~,~~~ _____ J

TOPIM
FROM CLOCK
POLARITY INPUT
CLOCK PINS

CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT

flash370-7

Figure 7. Input/Clock Pins
Notes:
3. C8 and C9 are not included on the CY7C371 and CY7C372 since each input/clock pin has the other input/clock pin as its clock.
4. CI5 and CI6 are not used on the CY7C371 and CY7C372 since there are two clocks.

chitecture for input pins. Four input options are available for the
user: combinatorial, registered, double-registered, or latched. If a
registered or latched option is selected, anyone of the input clocks
can be selected for control.

Figure 7 illustrates the architecture of input/clock pins. There are
either two or four input/clock pins available, depending on the device selected. (The CY7C371 and CY7C372 have two input/clock
pins while the other devices have four input/clock pins.) Like the
input pins, input/clock pins can be combinatorial, registered,
double registered, or latched. In addition, these pins feed the
clocking structures throughout the device. The clock path at the
input is user-configurable in polarity. The polarity ofthe clock signal can also be controlled by the user. Note thatthis polarity is separately controlled for input registers and output registers.
Timing Model
One of the most important features of the FLASH370 family is the
simplicity of its timing. All delays are worst case and system performance is unaffected by the features used or not used on the parts.
Figure 8 illustrates the true timing model for the 8.5-ns devices. For
combinatorial paths, any input to any output incurs an 8.S-ns
worst-case delay regardless of the amount of logic used. For synchronous systems, the input set-up time to the output macrocells
for any input is 5.0 ns and the clock to output time is also 6.0 ns.

COMBINATORIAL SIGNAL
0
O~-----------------tpD = 8.5 ns

REGISTERED SIGNAL

,At--------ID
o---P

O'-----___
CLOCK

ts = 5.0 ns

flash370-8

tco = 6.0 ns

Figure 8. Timing Model for CY7C371

Again, these measurements are for any output and clock, regardless of the logic used.
Stated another way, the FLASH370 features:
• no fanout delays
• no expander delays
• no dedicated vs. 1/0 pin delays
• no additional delay through PIM
• no penalty for using 0-16 product terms
• no added delay for steering product terms
• no added delay for sharing product terms
• no routing delays
• no output bypass delays
The simple timing model of the FLASH370 family eliminates unexpected performance penalties,

Development Software Support
Wa1p2/Wa1p2 +

Warp2/Walp2 + are state-of-the-art VHDLcompilersfordesigning
with Cypress PLDs and PROMs. Warp2/Warp2+ utilize a proper
subset of IEEE 1164 VHDL as the Hardware Description Language (HDL) for design entry. VHDL provides a number of significant benefits for the design entry. VHDL provides a number of
significant benefits for the design engineer. Warp2/Warp2+ accepts VHDL input, synthesizes and optimizes the entered design,
and outputs a JEDEC map for the desired device. For simulation,
Warp2/Warp2+ provides the graphical waveform simulator called
Nova.
VHDL (VHSIC Hardware Description Language) is an open,
powerful, non-proprietary language that is a standard for behavioral design entry and simulation. It is already mandated for use by
the Department of Defense and supported by every major vendor
of CAE tools. VHDL allows designers to learn a single language
that is useful for all facets of the design process. See separate data
sheet for further information.
Wa1p3

Warp3 is a sophisticated design tool that is based on the latest version of ViewLogic's CAE design environment. Warp3 features

3-13

II

~

FLASH370

:"rcYPRESS
schematic capture (ViewDraw ~), VHDL waveform simulation
(ViewSim ~ ), a VHDL debugger, and VHDL synthesis, all integrated in a graphical design environment. Wap3 is available on
PCS using Windows 3.1 or subsequent versions, and on HP and Sun
workstations. See separate data sheet for further information.
Third-Party Software

Programming

Cypress maintains a very strong commitment to third-party design
software vendors. All major third-party software vendors (includingABEL ~ , LOG/iC ~ , CUPL and Minc) will provide support
for the ~H370 family of devices. To expedite this support, Cypress supplies vendors with all pertinent architectural information
as well as design fitters for our products.
Document #: 38-0021S-C

As with development software, Cypress strongly supports thirdparty programmers. Allmajorthird-partyprogrammers(including
Data I/O, Logical Devices, Minato, SMS, and Stag) will support
the FLAsH370 family.

N

,

The Impulse3 ~ device programmer from Cypress will program all
Cypress PLDs, CPLDs, and PROMs. This unit is a programmer
that connects to any IBM-compatible PC via the printer port.
Third-Party Programmers

W:ap2,. Wap2+,. Wap3, FLAsH370, UltraLogic and Impulse3 are trademarks of Cypress Semiconductor Corporation.
VlewSlm and VlewDraw are trademarks of ViewLogic.
ABEL is a trademark of Data I/O Corporation.
LOG/iC is a trademark of Isdata Corporation.
CUPL is a trademark of Logical Devices, Inc.

3-14

CY7C371

UltraLogic ™ 32-Macrocell Flash CPLD
Features

Functional Description

• 32 macrocells in two logic blocks
• 32 I/O pins
• 6 dedicated inputs including 2 clock
pins
• No hidden delays
• High speed
-fMAX = 143 MHz
-tpD= 8.S ns
-ts = Sns
-teo 6ns
• Electrically alterable FLASH
technology
• Available in 44-pin PLCC, CLCC, and
TQFP packages
• Pin compatible with the CY7C372

The CY7C371 is a Flash erasable Complex
Programmable Logic Device (CPLD) and
is part of the FLASH37o. family of high-density, high-speed CPLDs. Like all members
of the FLASH37o. family, the CY7C371 is
designed to bring the ease of use and high
performance of the 22VIo. to high-density
CPLDs.
The 32 macrocells in the CY7C371 are divided between two logic blocks. Each logic
block includes 16 macrocells, a 72 x 86
product term array, and an intelligent
product term allocator.
The logic blocks in the FLASH37o. architecture are connected with an extremely fast
and predictable routing resource-the
Programmable Interconnect Matrix

=

(PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the
interconnect.
Like all members ofthe FLASH37o. family,
the CY7C371 is rich in 110 resources.
Each macrocell in the device features an
associated 110 pin, resulting in 32110 pins
on the CY7C371. In addition, there are
four dedicated inputs and two input/clock
pins.
Finally, the CY7C371 features a very simple timing model. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used
or the type of application, the timing parameters on the CY7C371 remain the
same.

Logic Block Diagram
CLOCK
INPUTS
2
INPUT/CLOCK
MACROCELLS

INPUT
MACROCELLS

2

2

PIM

161/05

LOGIC
BLOCK
A

1/00-1/0 15

36

36

16

16

LOGIC
BLOCK
B

161/05
1/0 16- 1/0 31

16

16

7c371-1

Selection Guide
Maximum Propagation Delay, tpD (ns)
Minimum Set-Up, ts (ns)
Maximum Clock to Output, teo (ns)

I Commercial

Maximum Supply
Current, Icc (rnA)
.

7C371~143

7C371-110

7C371-83

7C371L-83

8.5

10

12

12

15

15

5

6

10

10

12

12

7C371-66

7C371L-66

6

6.5

10.

10

12

12

220.

175

175

90.

175

90.

220.

110.

220.

110.

I. Military/lnd.

Shaded area contams prelImmary mformatlOn .

3-15

II

..............

~YPRESS

==

Pin Configurations

CY7C371
TQFP

PLCC/CLCC
Top View

Top View
<:t (f) C'II.,.... o~ U c;; g &i re:
ggggg",~gggg

<=I' C'l C\l ..... o~ 0
;;; g &i g)
ggggg,,~gggg

110.
1/07

1,
GNO
CLKO~2

1/0.
1/0.

110 ,.
110 "

11
12
13

33

32

31
30
29
,7,8,9202, 2223 2. 25 262728

"

15
16

1/027
1/0 29
1/0 25

I.

1/0 24

1/0.

1/0..
CLK1/1.

I.

1/0 7

110.

1/027
1/0 29
1/0 25

1/0.

1,

CLK1/1.

GND

GND
14

GND

I,
I.

CLKO~2

1/0.
1/0.
1/0 10
1/0"

I.
1/0 23
1/0 22
1/0 21

1/0 23

1/0 22
1/021

70371-2

70371-3

Logic Block
The number of logic blocks distinguishes the members of the
FLAsH370 family. The CY7C371 includes two logic blocks. Each
logic block is constructed of a product term array, a product term
allocator, and 16 macrocells.

Product Term Array
The product term array in the FLAsH370 logic block includes 36 inputs from the PIM and outputs 86 product terms t~ the p.roduct
term allocator. The 36 inputs from the PIM are available m both
positive and negative polarity, making the overall array size 72x 86.
This large array in each logic block allows for very complex functions to be implemented in a single pass through the device.

Product Term Allocator
The product term allocator is a dynamic, configu.rable resource
that shifts product terms to macrocells that reqUire them. Any
number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product
term steering). Furthermore, product terms can be shared among
multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to
increase the effective density of the FLASH370 CPLDs. Note that

product term allocation is handled by software and is invisible to
the user.

I/O Macrocell
Each of the macrocells on the CY7C371 has a separate associated
I/O pin. The input to the macrocell is the sum of between 0 and 16
product terms from the product term allocator. The macrocell includes a register that can be optionally bypassed. It also has polarity control, and two global clocks to trigger the register. The macrocell also features a separate feedback path to the PIM so that
the register can be buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the two
logic blocks on the CY7C371 to the inputs and to each other: All
inputs (including feedbacks) travel through the PIM. There IS no
speed penalty incurred by signals traversing the PIM.
Design '!boIs
Development software for the CY7C371 is available from Cypress's Wmp2, Wmp2+, and Wmp3 software packages. Allofthese
products are based on the IEEE-standard VHDL language. Cypress also actively supports third-party design tools such as
ABEL m ,CUPL N ,MINC, and LOG/iC N • Please contactyourlocal Cypress representative for further information.

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -65°C to + 150°C
Ambient Temperature with
Power Applied ........................ -55°C to +125°C
Supply Voltage to Ground Potential ......... -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.5V to + 7.0V
DC Input Voltage ........................ -O.5V to + 7.0V
DC Program Voltage .............................. 12.5V
Output Current into Outputs (LOW) ............... 16 rnA

Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA

Operating Range

Note:

1.

TA is the "instant on" case temperature.

3-16

Ambient
Temperature
O°C to +70°C

Vee
5V±5%

Military!l]

-55°C to + 125°C

5V± 10%

Industrial

-40°C to +85°C

5V± 10%

Range
Commercial

CY7C371
Electrical Characteristics Over the Operating Rangd21
Parameter

Description

Min.

Test Conditions

Output HIGH Voltage

VOH

Vee =
Min.

IOH = -3.2 rnA (Com'IJInd)

IOL = 16 rnA (Corn'I/Ind)

Max.

Unit

2.4

V
V

IOH = -2.0 rnA (Mil)

VOL

Output LOW Voltage

Vee =
Min.

VIH

Input HIGH Voltage

Guaranteed Input Logical HIGH Voltage for all inputs[3]

2.0

7.0

VlL

Input LOW Voltage

Guaranteed Input Logical LOW Voltage for all inputs[3]

-0.5

0.8

V

IlX

Input Load Current

GND:;::;VI:;::; Vee

-10

+10

fLA

Ioz

Output Leakage Current

GND s Vo s Vee, Output Disabled

-50

+50

fLA

los

Output Short
Circuit Currentl4, 51

Vee = Max., VOUT = O.5V

-30

-90

rnA

Icc

Power Supply Current

Vee = Max., lOUT = 0 rnA,
f = 1 mHz, VIN = GND, Vecf6]

175

rnA

0.5

V
V

IOL = 12 rnA (Mil)

Com'l
Com'l"~'

V

90

-66, -83
Com'I-143,
Mil/lnd

220

Ind "e -66, -83

110

Shaded area can tams prelImmary mformallon.

Capacitance[5]
Description

Parameter

Test Conditions

Max.

Unit

CIN

Input Capacitance

VIN = 5.0V at f=1 MHz

10

pF

COUT

Output Capacitance

VOUT = 5.0V at f = 1 MHz

12

pF

Endurance Characteristics[5]
Description
Minimum Reprogramming Cycles

Test Conditions
Normal Programming Conditions

Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. Not more than one output should be tested at a time. Duration ofthe
short circuit should not exceed I second. VOUT = O.5V has been chosen to avoid test problems caused by tester ground degradation.

5.
6.

3-17

Tested initially and after any design or process changes that may affect
these parameters.
Measured with 16-bit counter programmed into each logic block.

II

~
,CYPRESS

CY7C371

AC Test Loads and Wavefonns
5V 0---"'INv--,

OUTPUT 0 - -......- -....
INCLUDING
JIG AND
SCOPE

OUTP:

1700 (COM'L)
2360 (MIL)

I

35 PF

-=

5ri

2380 (COM'L)
3190 (MIL)

2380 (COM'L)
3190 (MIL)

5 PF
INCLUDING
JIG AND
SCOPE

7c371·4

(a)

I

-=

(b)

1700 (COM'L)
2360 (MIL)

-=

7c371-5

ALL INPUT PULSES
3.0V--90%

Equivalent to:

THEVENIN EQUIVALENT
990 (COM'L)
1360 (MIL)
2.08V (COM'L)
OUTPUT 0-----'IMI---0 2.13V (MIL)

GND

(c)

Parameter

Vx

tER( )

1.5V

tER(+)

2.6V

tEA(+)

1.5V

tEA(-)

Vthc

7c371-6

Output Waveform-Measurement Level
VOH O.5V

0.5V:

VOL

O.5V:

Vx
Vx

: r

0.5V

:

~
~

/:

Vx

70371-7

Vx
70371·8

VOH
70371·9

VOL

7c371·10

(d) Test Waveforms

Switching Characteristics Over the Operating Range[7]

7C37t~1~
Parameter

Description

~.

,~.

7C371-110

7C371-83
7C371L-83

7C371-66
7C371L-66

Min. Max.

Min.

Min.

Max.

Max.

Unit

Combinatorial Mode Parameters
tpD
tpDL

Input to Combinatorial Output
Input to Output Through 'Itansparent Input or
Output Latch

.. ,8.5, :'
" .,'
t,'~P:
I:',' .:," ,

.

12
18

15
22

ns
ns

15

20

24

ns

14
14

19
19

24
24

ns
ns

"

Input to Output Through Transparent Input and I' ,' .••.. 13,5
Output Latches
I·· .. ', 1",,Input to Output Enable
tEA
," . < 13
Input to Output Disable
tER
!'.1~
Input Registered/Latched Mode Parameters
Clock or Latch Enable Input LOW TimeL~ I
tWL
.,.z.?" ' ......
Clock or Latch Enable Input HIGH TimePI
tWH
2.5' " -".
,'i
Input Register or Latch Set-Up Time
tiS
Input Register or Latch Hold Time
tm
, l:~:' "
Input Register Clock or Latch Enable to Combina- .-.,':,~., ,~,
tlCO
torial Output
Input Register Clock or Latch Enable to Output
tlCOL
.... ,."".
Through'Itansparent Output Latch
tpDLL

.' ·x

2;

,::[2.:,'

.,i, . . ,:': :.~~"

Shaded area contams prehrmnary mformalton.
Note:
7. AIL AC parameters are measured with 16 outputs switching.

10
13

8.

3-18

4
4
3
3
14

19

24

ns
ns
ns
ns
ns

16

21

26

ns

3
3
2
2

5
5
4
4

This specification is intended to guarantee interface compatibility of
the other members of the CY7C370 family with the CY7C371. This
specification is met for the devices operating at the same ambient temperature and at the same power supply voltage.

CY7C371
Switching Characteristics Over the Operating Range[7] (continued)

Parameter

Description

7C371-143

7C371-110

Min.

Min.

Output Registered/Latched Mode Parameters
Clock or Latch Enable to Output
teo
Set-Up Time from Input to Clock or Latch
ts
Enable
Register or Latch Data Hold Time
tH
Output Clock or Latch Enable to Output Delay
teo2
(Through Memory Array)
tses
tses2
tSL
tHL
fMAXl
fMAX2

fMAX3
tOH-tlH
37x

Max.

0

Maximum Frequency Data Path in Output Re~isteredlLatched Mode &Lesser of 1/(tWL + tWH ,
1I(ts + tH), or 1/tco) ]
Maximum Frequency with external feedback
(Lesser of 1/(tco + ts) and 1/(tWL + tWH»[S]
Output Data Stable from Output clock Minus
Input Register Hold Time for 7C37x[5, 8]

Pipelined Mode Parameters
Input Register Clock to Output Register Clock
tiCS
Maximum Frequency in Pipelined Mode (Least of
fMAX4
1/(teo + tiS), l/tles, l/(tWL + tWH), 1I(tls + tlH)'
or 1ItSCS)
Reset/Preset Parameters
Asynchronous Reset Widthl']
tRW
Asynchronous Reset Recovery Time l5 ]
tRR
Asynchronous
Reset to Output
tRO
Asynchronous Preset WidthP]
tpw
Asynchronous Preset Recovery Timel']
tpR
Asynchronous Preset to Output
tpo
Power-On ResetlS]
tpOR

12
12

0
14

12

Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch Enable
Hold Time for Input Through 1tansparent Latch
from Output Register Clock or Latch Enable
Maximum Frequency with Internal Feedback
(Least of 1/tses, 1/(ts + tH), or 1/teo)[S]

10
10

6

0

Output Clock or Latch Enable to Output Clock or
Latch Enable (Through Memory Array)
Output Clock Through Array to Output Clock
(2-Pass Delay)[S]

Max. Min. Max. Min. Max.
6.5

6
5

7C371-83
7C371-66
7C371L-83 7C371L-66

0
19

24

Unit
ns
ns
ns
ns

7

9

12

15

ns

13

16.5

21

27

ns

9

10

12

15

ns

0

0

0

0

ns

143

111

83.3

66.6

MHz

166.7

153.8

100

83.3

MHz

91

80

50

41.6

MHz

0

0

0

0

ns

7
125

9

111

12
76.9

15
62.5

ns
MHz

8
10

10
12

15
17

20
22

ns
ns
ns
ns
ns
ns

16

14
10
12

8
10

..

14

1

21
15
17

16
1

26
20
22

21
1

26
1

!-Is

Shaded area contaInS prelimInary InformatIOn.

Switching Waveforms
Combinatorial Output
INPUT

COMBINATORIAL
OUTPUT

______t~~x~x~xx~x*----3-19

7c371-11

II

CY7C371
Switching Waveforms (continued)
Registered Output

E. t_J_"----

INPUT

CLOCK

REGISTERED
OUTPUT

1-~-1

---------x--x~----

---------

r~~----~H------1r~-----~L-----1~

CLOCK

_ _%-i.-------------"X-

Latched Output
INPUT

LATCH ENABLE

LATCHED
OUTPUT

)(

-----/) (

-----~::~ts~::~::::~tH~I----:::: ~--------------------

",'----------

----4----~~

_t
________

P:

_t:=1 _

1

~x~g~)K----------------x~

Registered Input
REGISTERED
INPUT

)~

X
tiS

tlH

/

INPUT REGISTER
CLOCK

xxt.....----

~tICO
COMBINATORIAL
OUTPUT

CLOCK

3-20

=- -~
~;CYPRESS

CY7C371

Switching Waveforms (continued)
Clock to Clock

x

REGISTERED
INPUT

C,~

INPUT REGISTER
CLOCK

OUTPUT
REGISTER CLOCK

J==c}

7c371-15

Latched Input

--tiS

, tlH-

LATCH ENABLE

-~1
XX

COMBINATORIAL
OUTPUT

;

LATCH ENABLE

Ell

'K

'K

LATCHED INPUT

tWH

t

)...

tWL

H:1=
XX
}

7c371-16

Latched Input and Output
LATCHED INPUT

LATCHED
OUTPUT

INPUT LATCH
ENABLE

OUTPUT LATCH
ENABLE

LATCH ENABLE

__;I-----twH=~t-l--_-_tW_L-______----.l}__
7c371-17

3-21

-.. ~

CY7C371

~,CYPRESS
Switching Waveforms (continued)
Asynchronous Reset
~---tRW

INPUT

-------

..

REGISTERED
OUTPUT

CLOCK
70371-18

Asynchronous Preset
tpw

)K

'I

INPUT

..

I\.
_tPQ_

REGISTERED
OUTPUT

XXXX)K
I--tpR

CLOCK

Power-Up Reset Waveform
POWER
SUPPLY VOLTAGE

10%t/

Vee

90%
tpOR

REGISTERED
ACTIVE LOW
OUTPUTS

xxx XXX

CLOCK
tpOR MAX = 1 JlS

~"

V
ts

i--=-

!---tWL-

V
70371·20

Output Enable/Dlsable
INPUT

OUTPUTS
70371-21

3-22

-=

:~

CY7C371

'CYPRESS

Ordering Information
Speed
(MHz)
143
110
83

66

Package
Name

Package 'JYpe

Operating
Range

CY7C371-143AC

A44

44-Lead Thin Plastic Quad Flat Pack

Commercial

CY7C371-143JC

J67

44-Lead Plastic Leaded Chip Carrier

CY7C371-110AC

A44

44-Lead Thin Plastic Quad Flat Pack

CY7C371-11OJC

J67

44-Lead Plastic Leaded Chip Carrier

CY7C371-83AC

A44

44-Lead Thin Plastic Quad Flat Pack

CY7C371L-83AC

A44

44-Lead Thin Plastic Quad Flat Pack

CY7C371-83JC

J67

44-Lead Plastic Leaded Chip Carrier

CY7C371L-83JC

J67

44-Lead Plastic Leaded Chip Carrier

CY7C371-83AI

A44

44-Lead Thin Plastic Quad Flat Pack

CY7C371L-83AI

A44

44-Lead Thin Plastic Quad Flat Pack

CY7C371-83JI

J67

44-Lead Plastic Leaded Chip Carrier

CY7C371L-83JI

J67

44-Lead Plastic Leaded Chip Carrier

CY7C371- 83YMB

Y67

44-Lead Ceramic Leaded Chip Carrier

Military

CY7C371-66AC

A44

44-Lead Thin Plastic Quad Flat Pack

Commercial

CY7C371L-66AC

A44

44-Lead Thin Plastic Quad Flat Pack

CY7C371-66JC

J67

44-Lead Plastic Leaded Chip Carrier

CY7C371L-66JC

J67

44-Lead Plastic Leaded Chip Carrier

CY7C371-66A1

A44

44-Lead Thin Plastic Quad Flat Pack

CY7C371L-66A1

A44

44-Lead Thin Plastic Quad Flat Pack

CY7C371-66JI

J67

44-Lead Plastic Leaded Chip Carrier

CY7C371L-66JI

J67

44-Lead Plastic Leaded Chip Carrier

CY7C371-66YMB

Y67

44-Lead Ceramic Leaded Chip Carrier

Ordering Code

Commercial
Commercial

Industrial

II

Industrial

Military

Shaded areas contaJII prellmmary mformatlOn.

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics

Switching Characteristics

Parameter

Subgroups

Parameter

Subgroups

VOH

1,2,3

tpD

9,10,11

VOL

1,2,3

tco

9,10,11

VIH

1,2,3

tICO

9,10,11

VIL

1,2,3

ts

9,10,11

IIX

1,2,3

tH

9,10,11

loz

1,2,3

tIS

9, 10, 11

IcC!

1,2,3

tIH

9,10,11

tICS

9,10,11

Document #: 38-00212-E
ABEL is a trademark of Data I/O Corporation.
LOG/iC is a trademark of Isdata Corporation.
CUPL is a trademark of Logical Devices Incorporated.

3-23

CY7C372

UltraLogic

1M

64-Macrocell Flash CPLD

Features

Functional Description

• 64 macrocells in four logic blocks

The CY7C372is a Flash erasable Complex
Programmable Logic Device (CPLD) and
is part of the FLAsH370~ family of highdensity, high-speed CPLDs. Like all members ofthe FLAsH370 family, the CY7C372
is designed to bring the ease of use and
high performance of the 22VlO to highdensity CPLDs.
The 64 macrocells in the CY7C372 are divided between four logic blocks. Each logic
block includes 16 macrocells, a 72 x 86
product term array, and an intelligent
product term allocator.
The logic blocks in the FLASH370 architecture are connected with an extremely fast
and predictable routing resource-the
Programmable Interconnect Matrix

• 321/0 pins
• 6 dedicated inputs including 2 clock
pins
• No hidden delays
• High speed
- fMAX = 125 MHz
-tpD = IOns
-ts = 5.5ns
-teo = 6.5 ns
• Electrically alterable Flash
technology
• Available in 44·pin PLCC and CLCC
packages
• Pin compatible with the CY7C371

(PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the
interconnect.
Like all members of the FLAsH370 family,
the CY7C372 is rich in I/O resources. Every two macrocells in the device feature an
associated I/O pin, resulting in 32 1/0 pins
on the CY7C372. In addition, there are
four dedicated inputs and two input/clock
pins.
Finally, the CY7C372 features a very simple timing model. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used.
or the type of application, the timing parameters on the CY7C372 remain the
same.

Logic Block Diagram

INPUT
MACROCELLS

2

81/0s

81/0s
36

1/00 -1/0 7

1/0 24-1/0 31

16

81/0s

81/0s
36

1/08-1/0 15

1/0 16 -1/0 23

16

16

16
7c372-1

Selection Guide
7C372...,125 7C372-100

7C372-83

7C372-66

7C372L-66

Maximum Propagation Delay, tpD (ns)

10

12

15'

20

20

Minimum Set-up, ts (ns)

5.5

6.0

8

10

10

Maximum Clock to Output, teo (ns)

6.5

6.5

8

10

10

280

250

250

250

125

300

300

I Commercial

Maximum SU~PIY
Current, Icc rnA)

. .

I Military/Industrial

..

Shaded area contams prelimmary mformatlon .

3-24

==-

.,~

CY7C372

~'CYPRESS
Pin Configuration

term steering). Furthermore, product terms can be shared among
multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to
increase the effective density of the FLAsH370 PLDs. Note that
product term allocation is handled by software and is invisible to
the user.

65432:1:4443424140

I/O,
I/O,
I/O,

- -

8
9

10

10

11

11

GND

I/O.
I/O,

12
13
14
15

110 10
1/0 11

16
17

ClKO/12

39

1/027

38

1/026

I/O Macrocell

37
36
35

I/O"
1/0 2.

Half of the macrocells on the CY7C372 have separate I/O pins
associated with them. In other words, each I/O pin is shared by two
macrocells. The input to the macrocell is the sum of between 0 and
16 product terms from the product term allocator. The macrocell
includes a register that can be optionally bypassed. It also has polarity control, and two global clocks to trigger the register. The I/O
macrocell also features a separate feedback path to the PIM so that
the register can be buried if the I/O pin is used as an input.

34
33
32
31
30

29

CLK1/IS
GND
I,
I.
1/0 23

1/022
1/021

18 1920 21 22232425 26 27 28

Buried Macrocell

Functional Description (continued)
Logic Block
The number of logic blocks distinguishes the members of the
FLAsH370 family. The CY7C372 includes four logic blocks. Each
logic block is constructed of a product term array, a product term
allocator, and 16 macrocells.

Product Term Array
The product term array in the FLAsH370 logic block includes 36 inputs from the PIM and outputs 86 product terms to the product
term allocator. The 36 inputs from the PIM are available in both
positive and negative polarity, making the overall array size 72 x 86.
This large array in each logic block allows for very complex functions to be implemented in a single pass through the device.

Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product

The buried macrocell is very similar to the I/O macrocell. Again, it
includes a register that can be configured as combinatorial, as a D
flip-flop, a T flip-flop, or a latch. The clock for this register has the
same options as described for the I/O macrocell. One difference on
the buried macrocell is the addition of input register capability.
The user can program the buried macrocell to act as an input register (D-type or latch) whose input comes from the I/O pin
associated with the neighboringmacrocell. The output of all buried
macrocells is sent directly to the PIM regardless of its configuration.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the four
logic blocks on the CY7C372 to the inputs and to each other. All
inputs (including feedbacks) travel through the PIM. There is no
speed penalty incurred by signals traversing the PIM.
Development Tools
Development software for the CY7C372 is available from Cypress's Wa/p2 m and Wa/p3 m software packages. Both of these
products are based on the IEEE standard VHDL language. Cypress also supports third-party vendors such as ABEL m , CUPL ,. ,
and LOG/icm. Please contact your local Cypress representative
for further information.

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -65°C to + 150°C
Ambient Temperature with
Power Applied ........................ -55°C to + 125°C
Supply Voltage to Ground Potential ......... -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.5V to + 7.0V
DC Input Voltage ........................ -O.5V to +7.0V
DC Program Voltage .............................. 12.5V
Output Current into Outputs ...................... 16 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)

Latch-Up Current ............................ >200 rnA

Operating Range
Range

Ambient
Temperature
O°Cto +700C

Vee
5V±5%

Industrial

-40°C to +85°C

5V ± 10%

Military[lj

-55°C to + 125°C

5V ± 10%

Commercial

Note:
1. TA is the "instant on" case temperature.

3-25

•

==--~

CY7C372

~CYPRESS

Electrical Characteristics Over the Operating Rangd2]
Parameter

Description

Test Conditions

Output HIGH Voltage

VOH

Vee = Min.

Min.

Max.

Unit

2.4

IOH = -3.2 rnA (Com'l/Ind)

V
V

IOH = - 2.0 rnA (Mil)
0.5

VOL

Output LOW Voltage

Vee = Min.

VIH

Input HIGH Voltage

Guaranteed Inpnt Logical HIGH Voltage for all Inputs[3]

2.0

7.0

V

VIL

Input LOW Voltage

Guaranteed Input Logical WW Voltage for all Inputs[3]

-0.5

0.8

V

IIX

Input Load Current

GNDsVIsVee

-10

+10

loz

Output Leakage Current

GND S Vo s Vee, Output Disabled

-50

+50

!lA
!lA

los

Output Short
Circuit Currend4, 5]

Vee = Max., VOUT = O.SV

-30

-90

mA

lee

Power Supply Current [6]

Vee = Max., lOUT = 0 rnA,
f = 1 mHz, VIN = GND, Vee

IOL = 16 rnA (Com'l/Ind)

V
V

IOL = 12 rnA (Mil)

Com'l

250

rnA

125

rnA

Com'l
-125

280

rnA

Mil
Ilndustrial

300

rnA

>eom'l"C'
-'66 ..

.

Shaded area contams prelImmary mformatlOn.

Capacitance[5]
Max.

Unit

CIN

Parameter

Input Capacitance

Description

VIN = S.OV at f=1 MHz

Test Conditions

10

pF

CoUT

Output Capacitance

VOUT = S.OV at f = 1 MHz

12

pF

Endurance Characteristics[5]
Description

Test Conditions

Minimum Reprogramming Cycles
Parameter

Vx

tER( )

l.SV

tER(+)

2.6V

tEA(+)

l.SV

tEA( )

Vthc

Normal Programming Conditions

Output Waveform-Measurement Level
VOH O.SV
VOL
Vx
Vx

:

o.SV:
O.5V

O.5V

l

l

~
~
~
~

Vx
Vx
VOH

VOL

(a) Test Waveforms
Notes:
2. See the last page ofthis specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. Not more than one output should be tested at a time. Duration of the
short circuit should not exceed 1 second. VOUT = O.5V has been chosen to avoid test problems caused by tester ground degradation.

5.
6.

3-26

Tested initially and after any design or process changes that may affect
these parameters.
Meaured with 16-bit counter programmed into each logic block.

-=-.

CY7C372

-===rcYPRESS
AC Test Loads and Waveforms

our; ~
I~',
,~~.~~F1
H""

INCLUDING
JIG AND
SCOPE

5V
OUTPUT

1236Q (mil)
-

-

5n

23SQ (com'l)

23SQ (com'l)

(a)

319Q

5 pF

~~8~~~NG
SCOPE

(mil)

I
-=

170Q (com'l)
236Q (mil)

-=

7c372-3

(b)
ALL INPUT PULSES

3.0V---

Equivalent to:

THEVENIN EQUIVALENT
99Q (com'l)
136Q (mil)
2.0SV (com 'I)
OUTPUT Q------'IIIIIr- 2.13V (mil)

90%
10%

GND

5.2 ns
7c372-4

II

Switching Characteristics Over the Operating Range[7]
7C372-66
Parameter

Description

7C372-125

7C372-100

7C372-83

Min.

Min.

Min. Max. Min. Max.

Max.

Max.

7C372L-66
Unit

Combinatorial Mode Parameters
tpD

Input to Combinatorial Output

10

12

15

20

ns

tpDL

Input to Output Through Transparent Input or
Output Latch

13

15

18

22

ns

tpDLL

Input to Output Through Transparent Input and
Output Latches

15

16

19

24

ns

tEA

Input to Output Enable

14

16

19

24

ns

14

16

19

24

ns

Input to Output Disable
tER
Input Registered/Latched Mode Parameters
Clock or Latch Enable Input LOW TimerS]
tWL

3

3

4

5

ns

tWH

Clock or Latch Enable Input HIGH TimerS]

3

3

4

5

ns

tIS

Input Register or Latch Set-Up Time

2

2

3

4

ns

tm

Input Register or Latch Hold Time

2

2

3

4

tICO

Input Register Clock or Latch Enable to
Combinatorial Output

14

16

19

24

ns

tICOL

Input Register Clock or Latch Enable to Output
Through Transparent Output Latch

16

18

21

26

ns

10

ns

ns

Output Registered/Latched Mode Parameters

6.5

tco

Clock or Latch Enable to Output

ts

Set-Up Time from Input to Clock or Latch Enable

6.5

8

tH

Register or Latch Data Hold Time

tC02

Output Clock or Latch Enable to Output Delay
(Through Memory Array)

tscs

Output Clock or Latch Enable to Output Clock or
Latch Enable (Through Memory Array)

8

10

12

15

ns

tSL

Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch Enable

10

12

15

20

ns

tHL

Hold Time for Input Through nansparent Latch
from Output Register Clock or Latch Enable

0

0

0

0

ns

5.5

6

8

10

0

0

0

0

14

Shaded area contams prelImmary mformatlOn.

3-27

ns

24

19

16

ns
ns

CY7C372
Switching Characteristics Over the Operating Rangd?] (continued)
'"

,

7~'i~~US' 7C372-100

7C372-83

7C372-66
1jj~1~I.~6j5: .

Mh1; Mn,

Min.

Min. Max.

Min. Max.

125

100

83

66

MHz

153.8

125

100

MHz

80

62.5

50

MHz

0

0

0

ns

"

Parameter
fMAXI

Description
Maximum Frequency with Internal Feedback in
Output Registered Mode (Least of l/tscs,
1/(ts + tH), or 1/tCO)[5]

I';;,
1518

""".'

Unit

.,'.' ..

fMAX2

Maximum Frequency Data Path in Output RegisteredlLatched Mode &Lesser of 1/(tWL + tWR),
!.' .,
1/(ts + tH), or 1/tco) ]
,.

fMAX3

Maximum Frequency with External Feedback
(Lesser of l/(tco + ts) and 1/(tWL + tWH»[5]

83)3

.,'

...... '

tOR-tIH
37x

Output Data Stable from Output clock Minus
Input Register Hold Time for 7C37x[5, 8]

1·,,',0.'"

.. ' ..

'"

Max.

" ··i;.
.

'

:..

,.".

Pipelined Mode Parameters
tiCS

8

Input Register Clock to Output Register Clock

Maximum Frequency in Pipelined Mode (Least of
l/(tco + t!1)' l/tICS, 1/(tWL + tWH), l/(tls + tIH),
or l/tscs)[
Reset/Preset Parameters
Asynchronous Reset WidthPJ
tRW
Asynchronous Reset Recovery Timel5j
tRR

fMAX4

tRo
tpw
tPR
tpo
tpOR

IJZS;

12

15

ns

,

83.3

66.6

MHz

'J'

12

15
17

20

ns

22

ns

"

"

)0
,L2,;:,

k "

Asynchronous Reset to Output
Asynchronous Preset WidthPj
Asynchronous Preset Recovery Timel5j

10
100

.".

·'·C
16.

,iQ:'; ::"

.~2

Asynchronous Preset to Output
Power-On Resetpj

......
"

' .. '
16,
,/1'"

14
18
12
14

21

26
20

15
17

22

ns
ns

18

21

26

ns
ns

1

1

1

J.ls

Shaded area contams prelImmary mformatlOn.

Switching Waveforms
Combinatorial Output

INPUT

COMBINATORIAL
OUTPUT

________~l~x~x~x~x~xi------

Note:
7. All AC parameters are measured with 16 outputs switching.
8. This specification is intended to guarantee interface compatibility of
the other members of the CY7C370 family with the CY7C372. This
specification is met for the devices operating at the same ambient temperature and at the same power supply voltage.

3-28

70372·5

CY7C372
Switching Waveforms (continued)
Registered Output

E. t_J_____,,--

INPUT

CLOCK

REGISTERED
OUTPUT

~:-1

------------------~x--~~~._-_-_-_-_-_-_-

;14---~tW-H-tl+--:WL---.I}~
CLOCK

Latched Output
INPUT

7c372-6

______

JjK~

______________ __________________
~;K

~ts
LATCH ENABLE

LATCHED
OUTPUT

tH-

______~------~)V

_____ ~':-1

~x~Z~)K,.

""I\.

'----------

~:-1

-----------~x~~

70372-7

Registered Input
REGISTERED
INPUT

__________-J""K~_________J)K~__________
v

INPUT REGISTER
CLOCK

~~_1

COMBINATORIAL
OUTPUT

__________________x~Z~)K========
_;'---~tw-H--tol----_tw_L~}~

CLOCK

7c372·8

3-29

II

.4f-:::Z

CY7C372

"CYPRESS
Switching Waveforms (continued)
Clock to Clock
REGISTERED
INPUT

INPUT REGISTER
CLOCK

OUTPUT
REGISTER CLOCK

----~><~--------------------------

_ _c_~t

070372-9

Latched Input

)

)K

LATCHED INPUT

tlH--

I--tlS

V

LATCH ENABLE

"r\.

xrl--~x~x1=

I-- tpDL

COMBINATORIAL
OUTPUT

LATCH ENABLE

I--tlCO

_____J---~H==~t=~~_L-_~}----

70372-10

Latched Input and Outpnt
LATCHED INPUT

tpDLL

LATCHED
OUTPUT
IsL
tHL

INPUT LATCH
ENABLE
tiCS

OUTPUT LATCH
ENABLE

LATCH ENABLE

J

tWH

t
3-30

tWL

}

7c372-11

~

J

CY7C372

?cYPRESS

Switching Waveforms (continued)
Asyncbronous Reset

14---- tRW -----1.~1

INPUT

REGISTERED
OUTPUT

CLOCK
7c372-12

Asyncbronous Preset
tpw

)r-,.

INPUT

II

•
I\.

!--tpo-

XXXX K:

REGISTERED
OUTPUT

_ _ _ _J.....I---

CLOCK

tpR

7c372-13

Power-Up Reset Wavefonn
~~9~0~%--------------------------VCC

POWER
10%
SUPPLY VOLTAGE ------~

....- - - - - - tpOR -------~

REGISTERED -------t-+------""'~""'7'~~~:__:l~~.j...".--------­
ACTIVE
LOW _ _ _ _ _ _
OUTPUTS
....t.~"_.::~~~~~:::./

++-_____

CLOCK
tpOR MAX = 1 !tS

Output Enable/Disable
INPUT

OUTPUTS
70372-15

3-31

CY7C372
Ordering Information
Speed
Ordering Code

(MHz)

";':'~,~;"

l,a;/~

'?","~

100

CY7C372-100JC

83

66

Package
Name

Package 'JYpe

Operating
Range

;:~J~7:i;1;1 r(~~~4'~~ilC',~~~,~JlJ~,;' '}\, ::';~~C1il1i'l
J67

44-Lead Plastic Leaded Chip Carrier

Commercial

CY7C372-83JC

J67

44-Lead Plastic Leaded Chip Carrier

Commercial

CY7C372-83JI

J67

44-Lead Plastic Leaded Chip Carrier

Industrial

CY7C372-83YMB

Y67

44-Lead Ceramic Leaded Chip Carrier

Military

CY7C372-66JC

J67

44-Lead Plastic Leaded Chip Carrier

Commercial

CY7C372-66YMB

Y67

44-Lead Ceramic Leaded Chip Carrier

Military

CY7C372-66JI

J67

44-Lead Ceramic Leaded Chip Carrier

Industrial

CY7C372L-66JC

J67

44-Lead Ceramic Leaded Chip Carrier

Commercial

Shaded areas contain preliminary information,

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics

Switching Characteristics

Parameter

Subgroups

Parameter

Subgroups

VOH

1,2,3

tpD

9,10,11

VOL

1,2,3

tco

9,10,11

VIH

1,2,3

tlCO

9,10,11

VIL

1,2,3

ts

9,10,11

IJX

1,2,3

tH

9,10,11

Ioz

1,2,3

tiS

9,10,11

Icc

1,2,3

tIH

9,10,11

tiCS

9,10,11

Document #: 38-00213-C

Wa/p2, Wap2+, Wap3 , UltraLogic, and FLAsH370 are trademarks of Cypress Semiconductor Corporation,
ABEL is a trademark of Data I/O Corporation.
LOG/iC is a trademark of Isdata Corporation.
CUPL is a trademark of Logical Devices Incorporated.

3-32

CY7C373

UltraLogic ™ 64-Macrocell Flash CPLD
Features

Functional Description

• 64 macrocells in four logic blocks

The CY7C373 is a Flash erasable Complex
Programmable Logic Device (CPLD) and
is part of the FLAsH370 m family of highdensity, high-speed CPLDs. Like all members ofthe FLASH370 family, the CY7C373
is designed to bring the ease of use and
high performance of the 22VlO to highdensity CPLDs.

• 641/0 pins
• 6 dedicated inputs including 4 clock
pins
• No hidden delays
• High speed
- fMAX 125 MHz
-tPD = 10 ns
-ts = 5.5 ns
-teo = 6.5 ns
• Electrically alterable Flash
technology
• Available in 84-pin PLCC and
100-pin TQFP packages
• Pin compatible with the CY7C374

=

The 64 macrocells in the CY7C373 are divided between four logic blocks. Each logic
block includes 16 macrocells, a 72 x 86
product term array, and an intelligent
product term allocator.

(PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the
interconnect.
Like all members ofthe FLASH370 family,
the CY7C373 is rich in I/O resources. Every macrocell in the device features an
associated I/O pin, resulting in 641/0 pins
on the CY7C373. In addition, there are
two dedicated inputs and four input/clock
pins.

Finally, the CY7C373 features a very simple timing model. Unlikeotherhigh-density CPLD architectures, there are no hidden speed delays such as fanout effects, in. terconnect delays, or expander delays. ReThe logic blocks in the FLASH370 architec- gardless of the number of resources used
ture are connected with an extremely fast or the type of application, the timing paand predictable routing resource-the rameters on the CY7C373 remain the
Programmable
Interconnect
Matrix same.

Logic Block Diagram

INPUT
MACROCELLS

36

1/00 -1/0 15

1/0 48 -1/063

16

36

1/016-1/0 31

1/032-1/0 47

16

32

32

7C373-1

Selection Guide
7C373-125

7C373-100

7C373-83

7C373-66

7C373L-66

Maximum Propagation Delay (ns)

10

12

15

20

20

Minimum Set-up, ts (ns)

5.5

6

8

10

10

Maximum Clock to Output, tco (ns)

6.5

6.5

8

10

10

280

250

250

250

125

300

300

I Commercial

Maximum Supply
Current, Icc (rnA)

..

I Industrial

Shaded area contams prehmmary mformatlon

3-33

II

.?cYPRESS

/

CY7C373

Pin Configurations
PLCC

Top View

GND
110 ..
110..
110..
1/052
110.,
110..
110..
110..
CLK3/14
GND

110.
1/00
1/0 10

I/O"

1/0 12

I/O,.
1/0 14

11O,.
CLKO/lo

Vee

GND
CLKM,

7C373

Vee
CLK2/I.

1/016

1/047
110..
110..
I/0..
I/0..

1/0 17
I/O,.
I/O,.
1/°20

1/021

1/042

1/022

1/041

1/°23

11O..

GND

TQFP

Top View

10099 98 97 96 95 94 93 92 91 9089 88 87 86 85 84 83 82 81 80 79 78

n

76
75
74

NC
GND

73

I/O.
110,

72
71
70
69
68
67
66
65
64
63
62
61
80
59

1/010

110"

1/0,2
I/O,.
1/0 14

I/O,.
ClKoIlo

Vee
N/C
GND
CLK,/I,
110,.
1/017
110,.
110,.

13
14
15
16
17
18

58

57
56
55
54
63
62
51

1/0 20
1/02'
1/022
1/0 23

Vee
NC

25

NC

Vee
I/0••
I/0..
110••
1/052
1/05 1

1/0.0
1/°49
1/048
ClKoII4
GND
NC

Vee
CLK,II.
11047
110..
I/O..
I/0..
1/043
1/0 42
I/O.,
liD ..
GND
NC

26 2726 29 30 31 32 3334 36 36 3738394041 424344 45 4647 48 49 50
7C373-2

3-34

CY7C373
Functional Description (continued)

Programmable Interconnect Matrix

Logic Block

The Programmable Interconnect Matrix (PIM) connects the four
logic blocks on the CY7C373 to the inputs and to each other. All
inputs (including feedbacks) travel through the PIM. There is no
speed penalty incurred by signals traversing the PIM.
Development Tools

The number of logic blocks distinguishes the members of the
FLASH370 family. The CY7C373 includes four logic blocks. Each
logic block is constructed of a product term array, a product term
allocator, and 16 macrocells.

Product Term AlTay
The product term array in the FLASH370 logic blockincludes36 inputs from the PIM and outputs 86 product terms to the product
term allocator. The 36 inputs from the PIM are available in both
positive and negative polarity, making the overall array size 72x86.
This large array in each logic block allows for very complex functions to be implemented in single passes through the device.

Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product term resources to macrocells that require them.
Any number of product terms between 0 and 16 inclusive can be
assigned to any ofthe logic block macrocells (this is called product
term steering). Furthermore, product terms can be shared among
multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to
increase the effective density of the FLASH370 CPLDs. Note that
the product term allocator is handled by software and is invisible to
the user.

I/O Macrocell
Each of the macrocells on the CY7C373 has a separate I/O pin
associated with it. In other words, each I/O pin is shared by two macrocells. The input to the macrocell is the sum of between 0 and 16
product terms from the product term allocator. The macrocell includes a register that can be optionally bypassed, polarity control
over the input sum-term, and two global clocks to trigger the register. The macrocell also features a separate feedback path to the
PIM so that the register can be buried if the I/O pin is used as an
input.

Development software for the CY7C373 is available from Cypress's Warp2 m , Warp2+ m , and Warp3 m software packages. Both
of these products are based on the IEEE standard VHDL language.
Cypress also supports third-party vendors such as ABEL m , CUPL m ,
and LOG/iC '.. Please contact your local Cypress representative for
further information.

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................... -65°C to + 150°C
Ambient Thmperature with
Power Applied ........................ -55°C to + 125°C
Supply Voltage to Ground Potential ......... -O.SV to +7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.5V to +7.0V
DC Input Voltage ........................ -O.SV to +7.0V
DC Program Voltage .............................. 12.5V
Output Current into Outputs ...................... 16 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA

Operating Range

3-35

Range
. Commercial
Industrial

Ambient
Temperature
O°C to +70°C

5V±S%

-400C to +8S o C

SV ± 10%

Vee

II

CY7C373
Electrical Characteristics Over the Operating Range
Parameter

Description

Test Conditions

Min.

I IOH = -3.2 rnA (Com'l/Ind)
I IOL = 16 rnA (Com'l/Ind)

Max.

Unit

2.4

VOH

Output HIGH Voltage

Vee = Min.

VOL

Output LOW Voltage

Vee = Min.

V

VIH

Input mGH Voltage

Guaranteed Input Logical HIGH Voltage for all Inputs[l]

VII.

Input LOW Voltage

Ilx

Input Load Current

Ioz

Output Leakage Current

GND ~ Vo ~ Vee, Output Disabled

-SO

los

Output Short
Circuit Current[2,3]

Vee = Max., VOUT = O.SV

-30

ICC

Power Supply Currentl4]

Vee = Max., lOUT = 0 rnA,
f = 1 mHz, VIN = GND, Vee

Com'l

2S0

rnA

. Com')

125

0.5

V

2.0

7.0

V

Guaranteed Input Logical LOW Voltage for all Inputs[l]

-0.5

0.8

V

GND~VI~Vee

-10

+10
+SO

!AA
!AA

-90

rnA

••••

"t',:':"66

..

rnA
.

Com'l
-125

280

rnA

Industrial

300

rnA

Shaded area contams prehnunary mformation
Capacitance[3]
Max.

Unit

CIN

Parameter

Input Capacitance

Description

VIN = S.OV at f=l MHz

Test Conditions

10

pF

CoUT

Output Capacitance

VOUT = S.OV at f = 1 MHz

12

pF

Endurance Characteristics[3]
Description

Thst Conditions

Minimum Reprogramming Cycles
Parameter

Vx

tER( )

l.SV

tER(+)

2.6V

tEA(+)

l.SV

tEA( )

Vthe

Normal Programming Conditions

Output Waveform-Measurement Level
VOH O.SV
VOL
Vx
Vx

t I:

O.SV
O.SV

O.5V

t
t

Vx

~
~

Vx
VOH

t I:

VOL

(a) Thst Waveforms
Notes:
1. These are absolute values with respect to device ground. All over-

shoots due to system or tester noise are included.
2. Not more than one output should be tested at a time. Duration of the
short circuit should not exceed 1 second. VOUT = O.5V has been chosen to avoid test problems caused by tester ground degradation.

3. Tested initially and after any design or process changes that may affect
these parameters.
4. Measured with 16-bit counter programmed into each logic block.

3-36

L~

CY7C373

~'CYPRESS

AC Test Loads and Waveforms
238Q (COM'L)

238Q (COM'L)

5V~
OUTPUT
35 pF

I

-=

INCLUDING
JIG AND
SCOPE

-=

ALL INPUT PULSES
3.0V---

5V5[l319Q(MIL)
OUTPUT
170Q (COM'L)
5 pF
236Q (MIL)
INCLUDING
JIG AND
SCOPE

(a)

GND

I

-=
(b)

-= 170n•• (COM'L)
7C373·4

7C373-5

THEVENIN EQUIVALENT
99Q (COM'L)
2.08V (COM'L)

Equivalent to:

OUTPUT

o---wv---o

Switching Characteristics Over the Operating Rangel5]

Parameter

Description

7C373-125

7C373-100

7C373-83

7C373-66
7C373L-66

Min.

Min.

Min. Max.

Min. Max.

Combinatorial Mode Parameters
Input to Combinatorial Output
tpo
Input to Output Through 'fiansparent Input or
tpOL
Output Latch
tpOLL

Input to Output Through Transparent Input and
Output Latches

Input to Output Enable
tEA
Input to Output Disable
tER
Input Registered/Latched Mode Parameters
Clock or Latch Enable Input LOW Time[3J
tWL
Clock or Latch Enable Input HIGH TimeL3J
tWH
tIS
tIH
tICO
tIcaL

Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to
Combinatorial Output

Max.

12

15

20

ns

15

18

22

ns

15

16

19

24

ns

14
14

16
16

19
19

24
24

ns
ns

3

3

3
2
2

2
2

Output Registered/Latched Mode Parameters
Clock or Latch Enable to Output
tco
Set-Up Time from Input to Clock or Latch Enable
ts
Register or Latch Data Hold Time
tH

II
Unit

10
13

3

Input Register Clock or Latch Enable to Output
Through Transparent Output Latch

Max.

4
4

5

ns
ns

5
4
4

3
3

ns
ns

14

16

19

24

ns

16

18

21

26

ns

10

ns
ns

6.5
0

8

6.5

0

Output Clock or Latch Enable to Output Delay
(Through Memory Array)

tscs

Output Clock or Latch Enable to Output Clock or
Latch Enable (Through Memory Array)

8

10

12

15

ns

tSL

Set-Up Time from Input Through 'fiansparent
Latch to Output Register Clock or Latch Enable

10

12

15

20

ns

tHL

Hold Time for Input Through Transparent Latch
from Output Register Clock or Latch Enable

0

0

0

0

ns

fMAXI

Maximum Frequency with Internal Feedback
(Least of 1/tscs, 1/(ts + tH), or 1/tCO)[3]

125

100

83

66

MHz

153.8

153.8

125

100

MHz

Maximum Frequency Data Path in Output
Registered/Latched Mode ~Lesser of 1/(tWL +
tWH), 1/(ts + tH), or 1/tco) 3]
snaaea area contams prellmmary mrormallon

3-37

16

ns

24

19

tC02

fMAX2

14

10

8
0

6
0

5.5

ns

L~

CY7C373

~'CYPRESS

Switching Characteristics Over the Operating Range[S] (continued)
,

.

,.

7C373-66

1q73~US
Parameter

Mm.

Description

fMAX3

Maximum Frequency of (2) CY7C373s with
External Feedback (Lesser of l/(tco + ts) and
l/(tWL + twW)[3]

83.3

tOR-tIH
37x

Output Data Stable from Output clock Minus
Input Register Hold Time for 7C37x[3, 6]

.0

...

7C373-100

7C373-83

7Q7;3L~

.MaX. Min. Max. Min. Max. Min. Max. Unit
'

80

62.5

50

MHz

0

0

0

ns

.

,.

.... I

Pipelined Mode Parameters
tICS
fMAX4

8

10

12

15

ns

125

83.3

66.6

50.0

MHz

ns

Input Register Clock to Output Register Clock

Maximum Frequency in Pipelined Mode (Least of
l/(tco + t~), l/tICS, l/(tWL + tWR), l/(tIS + tIH),
or I/tscs)[
Reset/Preset Parameters
Asynchronous Reset WidthLjJ
tRW
Asynchronous Reset Recovery Time L3J
tRR

10

12

15

20

12

14

17

22

16

tRO
tpw

Asynchronous Reset to Output
Asynchronous Preset WidthL3J

10

tpR
tpo

Asynchronous Preset Recovery Timel3J

12

tpOR

.
...

Asynchronous Preset to Output
Power-On ResetL3J

.'

Shaded area contams prelImmary mformatlOn.
Note:
5. ALI AC parameters are measured with 16 outputs switching.
6. This specification is intended to guarantee interface compatibility of
the other members of the CY7C370 family with the CY7C373. This
specification is met for the devices operating at the same ambient temperature and at the same power supply voltage.

3-38

18
12

15

14

16
1

21

ns
26

17

ns
ns

20
22

ns

18

21

26

ns

1

1

1

fIB

==-- -'i~

-=-_,

CY7C373

CYPRESS

Switching Waveforms
Combinatorial Output
INPUT

COMBINATORIAL
OUTPUT

t
__________

%

1

~z~x~x~x~x~x~========

7C373-6

Registered Output
INPUT

CLOCK

f=.

REGISTERED
OUTPUT

t'--I-,f---,,--1-<~--------------------------

INPUT REGISTER
CLOCK

OUTPUT
REGISTER CLOCK
7C373-10

Latched Input
LATCHED INPUT

lATCH ENABLE

)(

I+--tlS
tpDL

tlH~V

'I\.

tlCO

COMBINATORIAL
OUTPUT

xx1-----.x~x1=

LATCH ENABLE

______J~_twH~~t~~-__ L-_-}~--

I--

I--

tw__

7C373-11

3-40

CY7C373
Switching Waveforms (continued)
Latched Input and Output
LATCHED INPUT

LATCHED
OUTPUT

14---tSL

INPUT LATCH
ENABLE

OUTPUT LATCH
ENABLE

LATCH ENABLE

__J-~-_tWH=="""*"t==_tWL=~}....--_

II
7C373-12

Asynchronous Reset

INPUT

REGISTERED
OUTPUT

CLOCK
7C373-13

Asynchronous Preset
j4----tpw

•

INPUT

REGISTERED
OUTPUT

CLOCK
7C373-14

3-41

CY7C373
Switching Waveforms (continued)
Power-Up Reset Waveform
POWER
SUPPLY VOLTAGE

JE~90~%~------------------------VCC

-------r10%

~------------tpOR------------~~

REGISTERED -------+-+------~"7'I:....,.~~...,..:__::~"7'I:t_7--------­
ACTIVELDW
OUTPUTS -------+-+------~~~~~~~~~
CLOCK

tpOR MAX = 1 Ils

7C373·15

Output EnabJe/DisabJe
INPUT

OUTPUTS
7C373-16

Ordering Information
Speed
(MHz)

1$'/,

,r, '"'.":,,
100

83

66

Ordering Code

CX?~73,,-,:,l~A.P ,', "
.' CX7C$~';'125JC",' ,"""

Package
1YPe
,AIOQ','

Package
1YPe

1OQ-fi4 !fhin,QulldF1a~c~

Operating
Range
"

' <::oin1nerciiil

;Jill "', ,!l4,~a9l>ll!sti9Le

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