1996_Fujitsu_Wireless_Communications_Products_Data_Book 1996 Fujitsu Wireless Communications Products Data Book

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FUJITSU

Wireless Communications Products
Including Power Management
Dala Book
1996 Rev. 1.0

Introduction and Quick Selection Guide

II

Prescalers

IEaII

CMOS Phase-Locked Loops (PLLs)

III

Super PLLs (Single Chip PLLs/Prescalers)

II

Super Analog RF Devices
BiCMOS LSI RF Integrated Circuits
Piezoelectric Devices/SAW Filters
Power Management Switches

III
l1li
III
•

Quality and Reliability

D
III

Ordering Information

HI

Sales Information

If)

Glossary

III

Application Notes and Articles

00

FUJITSU

Wireless Communications Products
Including Power Management

1996
Data Book
Rev. 1.0

Fujitsu Limited
Tokyo, Japan
Fujitsu Microelectronics, Inc.
San Jose, California, U.S.A.

©1995 Fujitsu Microelectronics, Inc., San Jose, Califomia
All Rights Reserved
The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu Microelectronics, Inc. assumes no responsibility for inaccuracies.
The information conveyed in this document does not convey any license under the copyrights, patent rights or trademarks claimed and
owned by Fujitsu Limited, its subsidiaries, or Fujitsu Microelectronics, Inc.
Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice.
No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without the prior
written consent of Fujitsu Microelectronics, Inc.
This document is published by the Product Communications Department. Fujitsu Microelectronics, Inc., 3545 North First Street, San
Jose, Califomia, U.S.A 95134-1804
Printed in the U.S.A.

PREFACE

This data book contains the latest product information which is part of the vast line of
Fujitsu's Telecommunications Products that supports the rapidly growing markets
for Wireless Communications products and services. This edition includes Prescalers, CMOS PLLs, Super PLLs, Super Analog RF Devices, high performance Piezoelectric Bandpass SAW Filters, and Power Management Switches. All of these products are manufactured to meet the high standard of quality and reliability that is found
in all of Fujitsu's products.
Fujitsu Microelectronics, Inc. (FMI), is further committing to higher levels of product support and information responsiveness to its valued customers through the establishment of a Customer Response Center (CRC) and a site on the Internet World
Wide Web (WWW). The CRC, planned to be operational in Oct, 1995, will give you
the convenience of calling one number (1-800-866-8608) for support of your product questions and information needs. In addition, the Internet WWW site for FMI
(www.fmi.fujitsu.com) is in the process of being registered and will be brought online to give you quick and easy access to the vast array of information covering the
large number of product lines supported by FMI. Our goal is to provide all of our
customers the best possible support and attention they deserve.

iii

iv

Contents and Alphanumeric Product List
SECTION 1 - Introduction and Quick Selection Guide . . . . . . . . . . . . . . . . ..
SECTION 2 - Prescalers MB501 L
MB501LV
MB501SL
MB504
MB504L
MB504LV
MB505-16
MB506
MB507
MB508
MB509
MB510
MB511
MB551

1-1

At a Glance .............................. 2-1
1.1 GHz Two Modulus Prescaler ...................................... 2-3
1.1 GHz Low Voltage/Low Power Two Modulus Prescaler ............... " 2-15
1.1 GHz Super Low Power Two Modulus Prescale ... . . . . . . . . . . . . . . . . . . .. 2-25
520 MHz Two Modulus Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
520 MHz Two Modulus Prescaler ..................................... 2-3
520 MHz Low Voltage/Low Power Two Modulus Prescaler ................. 2-15
1.6 GHz Two Modulus Prescaler ....................................... 2-35
2.4 GHz Two Modulus Prescaler ....................................... 2-39
1.6 GHz Two Modulus Prescaler ....................................... 2-43
2.3 GHz Two Modulus Prescaler ....................................... 2-51
1.1 GHz Two Modulus Prescaler ............. ; ......................... 2-59
2.7 GHz Two Modulus Prescaler ....................................... 2-67
1.0 GHz Two Modulus Prescaler ....................................... 2-73
1.0 GHz Two Modulus Prescaler ....................................... 2-81

SECTION 3 - CMOS Phase-Locked Loops (PLLs) MB87001A
MB87006A
MB87014A
MB87076
MB87086A
MB87087
MB87091
MB87093A
MB87094
MB87095A
MB87096A

At a Glance ....... 3-1
13 MHz Serial Input PLL Frequency Synthesizer ........................ 3-3
17 MHz Serial Input PLL Frequency Synthesizer ......................... 3-15
180 MHz Serial Input PLL Frequency Synthesizer ........................ 3-27
10 MHz Serial Input PLL Frequency Synthesizer with Power Down ......... 3-37
95 MHz Serial Input PLL Frequency Synthesizer ......................... 3-49
17 MHz Serial Input PLL Frequency Synthesizer .......................... 3-59
300 MHz Serial Input PLL Frequency Synthesizer ....................... 3-71
145 MHz Serial Input PLL Frequency Synthesizer ....................... 3-89
15 MHz @ 1.1 V Serial Input PLL Frequency Synthesizer ................. 3-99
110 MHz Serial Input PLL Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . . .. 3-89
90 MHz Serial Input PLL Frequency Synthesizer .......................... 3-89

SECTION 4 - Super PLLs (Single Chip PLLs/Prescalers) MB 15A01
MB15B01
MB1501
MB1501 H
MB 1501 L
MB15A02
MB 1502
MB 1502H
MB15B03
MB15F03
MB 1503
MB1504
MB1504H
MB1504L

At a Glance .. 4-1
1.1 GHz Prescaler/Seriallnput PLL Frequency Synthesizer ................. 4-5
1.1 GHz Dual PrescalerlSeriallnput PLL Frequency Synthesizer ........... 4-19
1.1 GHz Prescaler/Seriallnput PLL Frequency Synthesizer ............... 4-33
1.1 GHz Prescaler/Seriallnput PLL Frequency Synthesizer ............... 4-33
1.1 GHz PrescalerlSeriallnput PLL Frequency Synthesizer ............... 4-33
1.1 GHz PrescalerlSeriallnput PLL Frequency Synthesizer ............... 4-51
1.1 GHz Prescaler/Seriallnput PLL Frequency Synthesizer ............... 4-67
1.1 GHz Prescaler/Seriallnput PLL Frequency Synthesizer ............... 4-67
1.1 GHz. 0.3 GHz Dual PrescalerlSeriallnput PLL Frequency Synthesizer .. 4-81
2.0 GHz. 0.5 GHz Dual Prescaler/Seriallnput PLL Frequency Synthesizer .. 4-95
1.1 GHz PrescalerlSerial Input PLL Frequency Synthesizer ............... 4-109
520 MHz PrescalerlSeriallnput PLL Frequency Synthesizer ............. 4-125
520 MHz PrescalerlSeriallnput PLL Frequency Synthesizer ............. 4-125
520 MHz Prescaler/Seriallnput PLL Frequency Synthesizer ............. 4-125

v

SECTION 4 - Super PLLs (Single Chip PLLs/Prescalers)
MB15E05
MB1505
MB15E06
MB1506
MB1507
MB1508
MB1509
MB15U10
MB1510
MB15B11
MB1511
MB1512
MB15B13
MB1513
MB1514
MB1515
MB15A16
MB1516A
MB1517A
MB1518
MB15A19
MB1519
MB15Sxx Series
MB15S02

2.0 GHz Low Power PrescalerlSeriallnput PLL Frequency Synthesizer ..... 4-143
600 MHz PrescalerlSeriallnput PLL Frequency Synthesizer .............. 4-157
2.5 GHz Low Power PrescalerlSerial Input PLL Frequency Synthesizer ..... 4-143
2.0 GHz PrescalerlSerial Input PLL Frequency Synthesizer ............... 4-169
2.0 GHz PrescalerlSeriallnput PLL Frequency Synthesizer ............... 4-185
2.5 GHz PrescalerlSeriallnput PLL Frequency Synthesizer ............... 4-197
400 MHz Dual PrescalerlSeriallnput PLL Frequency Synthesizer .......... 4-207
1.1 GHz Dual PrescalerlSeriallnput PLL Frequency Synthesizer ........... 4-221
1.1 GHz Dual PrescalerlSeriallnput PLL Frequency Synthesizer ........... 4-231
1.1 GHz 400 MHz Dual PrescalerlSerial Input PLL Frequency Synthesizer .. 4-243
1.1 GHz PrescalerlSerial Input PLL Frequency Synthesizer ............... 4-257
1.1 GHz PrescalerlSeriallnput PLL Frequency Synthesizer ............... 4-269
1.1 GHz Dual PrescalerlSeriallnput PLL Frequency Synthesizer ........... 4-281
1.1 GHz PrescalerlSerial Input PLL Frequency Synthesizer ............... 4-295
400 MHz Dual PrescalerlSeriallnput PLL Frequency Synthesizer .......... 4-309
2.5 GHz PrescalerlSeriallnput PLL Frequency Synthesizer ............... 4-323
1.2 GHz PrescalerlSerial Input PLL Frequency Synthesizer ............... 4-337
1.1 GHz PrescalerlSerial Input PLL Frequency Synthesizer ............... 4-349
2.0 GHz PrescalerlSeriallnput PLL Frequency Synthesizer ............... 4-365
2.5 GHz PrescalerlSerial Input PLL Frequency Synthesizer ............... 4-391
600 MHz Dual PrescalerlSeriallnput PLL Frequency Synthesizer .......... 4-401
600 MHz Dual PrescalerlSeriallnput PLL Frequency Synthesizer .......... 4-415
300 MHz Mask Programmable IF Prescaler/PLL ......................... 4-429
284 MHz.116 MHz Fixed Divide IF Prescaler/PLL for GSM ................ 4-437

SECTION 5 - Super Analog RF Devices MB531
MB539
MB54501
MB54502
MB54503
MB54609
MB54619

At a Glance .................. 5-1
1.1 GHz Tx Mixer ..................................................... 5-3
1.6 GHz Low Noise Amplifier .......................................... 5-11
1.1 GHz Low Noise Amplifier and Mixer ................................. 5-19
1.1 GHz Dual Low Noise Amplifiers ..................................... 5-25
1.1 GHz Medium Power PA Driver Amplifier ............................. 5-31
1.0 GHz I/O Ouadrature Modulator (Preliminary) ......................... 5-37
2.0 GHz I/O Ouadrature Modulator (Preliminary) .......................... 5-59

SECTION 6 - BiCMOS LSI RF Integrated Circuits MB1520
MB1530
MB1540
MB1550
MB54500
MB54600
MB1560

vi

At a Glance ......... 6-1
Series I Semi-Custom LSI RF IC ........................................ 6-3
Series I Semi-Custom LSI RF IC ........................................ 6-3
Series I Semi-Custom LSI RF IC ....................................... 6-3
Series I Semi-Custom LSI RF IC ........................................ 6-3
Series II Semi-Custom LSI RF IC ...................................... 6-31
Series III Semi-Custom LSI RF IC ...................................... 6-45
Series IV Semi-Custom LSI RF IC ...................................... 6-59

SECTION 7 - Piezoelectric Devices/SAW Filters FAR-FSCC-86MSO-L2AA
FAR-FSCC-836MSO-L2AZ
FAR-FSCC-881 MSO-L2AB
FAR-FSCC-881 MSO-L2AY
FAR-FSCC-933MSO-L2BA
FAR-FSCC-878MSO-L2BB
FAR-FSCC-888MSO-L2CA
FAR-FSCC-933MSO-L2CB
FAR-FSCC-911 MSO-L20A
FAR-FSCC-8S6 MSO-L2 OB
FAR-FSCC-902 MSO-L2 EZ
FAR-FSCC-947MSO-L2EB
FAR-FSCC-947MSO-L2EY
FAR-FSCC-947MSO-L2EX
FAR-FSCC-897MSO-L2KA
FAR-FSCC-942 MSO-L2 KB
FAR-FSCC-942 MSO-L2 KY
FAR-FSCC-950MOO-L2FA
FAR-FSCC-820MOO-L2FB
FAR-FSCC-91SMOO-L2JA
FAR-FSCC-915MOO-L2JZ
FAR-FSCC-93SMOO-L2LA
FAR-FSCB-836MSO-L2AA
FAR-FSCB-881 MSO-G201
FAR-FSCB-881 MSO-G211
FAR-FSCB-888MSO-G201
FAR-FSCB-933MSO-G202
FAR-FSCB-933MSO-G212
FAR-FSCB-902MSO-G201
FAR-FSCB-947MSO-G201
FAR-FSCB-947MSO-G211
FAR-FSCB-911 MSO-G201
FAR-FSCB-933MSO-G201
FAR-FSCB-878MSO-G201
FAR-F6CC-1 G441 O-L2ZA
FAR-F6CC-1 G4890-L2ZB
FAR-F6CC-1 G6190-L2ZN
FAR-F6CE-1G747S-L2YA
FAR-F6CE-1 G842S-L2YB
FAR-F6CE-1 G8800-L2XA
FAR-F6CE-1 G960O-L2XB
FAR-F6CE-2G4S0O-L2WA
M2 Series (0100)
M2 Series (0300)
M3 Series (0001)
M3 Series (0101)

SECTION 8 - Power Management Switches MB3802
MB3807A

At a Glance ...........

7-1

AMPS/IS-S4/IS-9S SAW Filter ....................................... 7-7
AMPS/IS-S4/IS-9S SAW Filter ....................................... 7-7
AMPS/IS-S4/IS-9S SAW Filter ....................................... 7-7
AMPS/IS-S4/IS-9S SAW Filter ....................................... 7-7
NTT SAW Filter .................................................... 7-7
NTT SAW Filter .................................................... 7-7
ETACS SAW Filter .................................................. 7-7
ETACS SAW Filter .................................................. 7-7
NTACS SAW Filter ................................................. 7-7
NTACS SAW Filter .................................................. 7-7
NMT/GSM SAW Filter ............................................. 7-7
NMT/GSM SAW Filter ............................................. 7-7
NMT/GSM SAW Filter ............................................. 7-7
NMT/GSM SAW Filter .............................................. 7-7
E-GSM SAW Filter ................................................. 7-7
E-GSM SAW Filter ................................................ 7-7
E-GSM SAW Filter ................................................ 7-7
POC SAW Filter ................................................... 7-7
POC SAW Filter .................................................. 7-7
900 MHz ISM SAW Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-7
900 MHz ISM SAW Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-7
2-Way Pager SAW Filter ........................................... 7-7
AMPS/lS-136/1S-9S SAW Filter ..................................... 7-37
AMPS/lS-136/1S-9S SAW Filter ..................................... 7-37
AMPS/lS-136/1S-95 SAW Filter .................................... 7-37
ETACS SAW Filter ............................................... 7-37
ETACS SAW Filter ............................................... 7-37
ETACS SAW Filter ............................................... 7-37
NMT/GSM SAW Filter ............................................ 7-37
NMT/GSM SAW Filter ............................................. 7-37
NMT/GSM SAW Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-37
NTACS SAW Filter ............................................... 7-37
NTT SAW Filter .................................................. 7-37
NTT SAW Filter .................................................. 7-37
POC 1.S GHz SAW Filter .......................................... 7-65
POC 1.5 GHz SAW Filter .......................................... 7-65
POC 1.S GHz SAW Filter .......................................... 7-65
OCS 1800 SAW Filter ............................................. 7-65
OCS 1800 SAW Filter ............................................ 7-65
PCS (US) SAW Filter ............................................. 7-65
PCS (US) SAW Filter ............................................. 7-65
WLAN (US) SAW Filter ........................................... 7-65
Piezoelectric Oevice (Voltage Controlled Oscillator) ................... 7-87
Piezoelectric Oevice (Voltage Controlled Oscillator) ................... 7-95
Piezoelectric Oevice (Voltage Controlled Oscillator) ...................7-105
Piezoelectric Modulator ............................................7-109

At a Glance ..............

8-1

Oual .12 Ohm, 1.2 Amp Switches with Zero "Off State" Currrent ........ 8-3
Oual .3 Ohm (12V port), 6.0 Ohm (5V port) Switches for Flash . . . . . . . . .. 8-17
Memory Cards and Other PCMCIA A.pplications ...................... 8-17

vii

SECTION 9 - Application Notes and Articles -

At a Glance ...........

9-1

Fujitsu Prescalers and Phase-Locked L60ps forNHF and UHF Frequency Synthesis ............... 9-3
Resonator-Type Low-Loss Filters ........................................................... 9-35
Land S Band Low-Loss Filters using SAW Resonators ......................................... 9-43

SECTION 10 - Quality and Reliability ................................. 10-1
SECTION 11 - Ordering Information .................................. 11-1
SECTION 12 - Sales Information ..................................... 12-1
SECTION 13 - Glossary . ................' ............................. 13-1

viii

SECTION 1
Introduction and Quick Selection Guide

1-1

1-2

RFIWIRELESS PRODUCTS
Telecommunication Devices
Fujitsu's Telecom IC product offering includes a wide range of leading
.edge RFlWireless parts for use in diverse applications such as cellular
telephones, cordless telephones, PCS/PCN systems, wireless PBX
systems, wireless LANIWAN systems, pagers, cable television converter boxes and a variety of portable wireless communication devices. The
core product families for RFlWireless applications include Prescalers,
Phase-Locked Loops (PLLs), SingleChip PLUPrescalers (Super
PLLs), RF Analog Devices (Super Analog), and Piezoelectric Devices
(SAW Filters and VCOs/Modulators). These products are manufactured to meet the high standard of quality and reliability that is found in all
Fujitsu products.
Prescalers
Fujitsu offers a wide range of prescaler devices capable of satisfying the technical requirements of today's applications. Features include devices covering the 200 MHz to 2.7 GHz range, low power
consumption, and a multitude of divide ratios.
PLLs
The Fujitsu family of PLLs offers a wide range of operation frequencies with low supply current and voltages to meet many diverse design requirements. A serial input programming capability is a feature of all Fujitsu's PLLs.
Super PLLs
Fujitsu is one of only a few semiconductor manufacturers to offer
single-chip PLUPrescaler devices and was the creator of the industry standard MB1501. These devices are manufactured using
an advanced BiCMOS process that combines high speed and low
power consumption in a single chip. With the increased emphasis
on board space reduction to improve cost, reliability, and overall
end product size for portable applications, these single-chip devices are an ideal solution for wireless systems designers.
Super Analog
Included are a series of highly integrated Analog RF devices such
as Low Noise Amplifiers (LNA), Modulators, Demodulators and
Mixers that are typically used in the front ends of mobile and portable wireless communication systems. These include single and
multi-function devices based on Fujitsu's advanced RF
SiCMOS and Bipolar processes which are second to none.
Piezoelectric Devices
Fujitsu's lithium tantalate piezoelectric bandpass SAW Filters provide sharp roll-off characteristics and excellant stability over temperature in very small 3.8 mm x 3.8 mm or 5 mm x 5 mm surface
mount packages. Standard transmit and receive frequencies are
available for AMPS, NTACS, ETACS, NMT/GSM, NTT, PDC and
ISM/USA. This family of devices also includes a series of Voltage
Controlled Oscillators (VCOs) and Modulators

1-3

RFIWIRELESS PRODUCTS
Quick Selection Guide - Prescaler, Super Analog
: Application
Frequency

Bipolar Prescalers

I
I
I
I
I
I
I
I
I

MB510

2.5GHz MB506

2.0GHz -

1.5GHz -

MB50S-16
MB507

1.0 GHz -

MB511

0.5GHz -

I
I
I
I
I

MB504

MB508

MB501L

MB504L

I

I
Single
Modulus

I
I
I
I
I
I
I
I

Dual
Modulus

I
I
I
I

MB501LV

MB504LV

MB501SL

I

I
Dual
Modulus
& Low
Current

I
I
I
I

Dual
Modulus
& Low
Voltage

I
I
I
I

MB509

I

I
Dual
Modulus
& Super
Low
Power

MB551

Dual
Modulus
& Power
Saving

I
I
I
I
I
I
I
I
I
I

Prescaler
&VCO

Device
Type

Super Analog Devices
Application
Frequency

I
I
I
I

I
I
I
I
I
I  I 
I
I
I
I
I
I

I
I
I
I
I
I
I
I
I

I

I

I

2.5GHz

2.0 GHz


1.5GHz

1.0GHz

0.5GHz

Mixer

1-4

Low Noise
Amp

I
Low Noise
Amp & Mixer

Dual Low
Noise Amp



I
I
I
I



I



II
I
I

I
Med. Power
Amp

I
Quadrature
Modulators

I

RFIWIRELESS PRODUCTS
Quick Selection Guide - CMOS PLLs, Super PLLs
Application
Frequency

Fujitsu CMOS PLLs

250 MHz

200 MHz

150 MHz

100 MHz

50 MHz

MB87001A
MB87006A
MB87076A
MB87087

I
I
I
I
I
I
I
I
I

Wide Voltage
Range &
Swallow Cntr.

MB87086A

I

I
I
I
I
I
I
I
I
I

-

2.0GHz

-

MB87095A

1

1

I

I

I
I
I
I
I
I
I

MB87096A

I
PLL w/o
Swallow Cntr.

MB87014A

I
I
I
I
I

1

1

I

1

I

I

I

1

PLL w/o
Swallow Cntr.,
Fixed Divide
Ratios in (SSOP)

Application
Frequency

2.5GHz

MB87093A

I
I
I
I
I

MB87094

I
I
I
I
I
1
1

I
I

I

Very Low
Voltage

PLL&
Prescaler

MB87091

I
I

Low Voltage
High Freq.

OeviceType

Super PLLs

I
I
MB1506**
MB1507

MB1508
MB151S"
MB1518

MB15E06**

1

MB15F03"

MB15E05"

MB1517A .. 1

I
I

1
1.5 GHz -

{
1.0 GHz -

0.5GHz -

MBIS01'

MB1501L *
MB1501H *

MB1504 *
MB1S04L *
MB1504H*

I
I
I'{MBI~ I
I
I
I
1
I
I
MB1502H
MB1503
MB1S11
MB1512
MB1505

I
Wide Operating
Voltage & Low
Current
Note:

MB1SB03"1·
MB 15B

=

MB1SA02"
MB1513

MB15A16

MB1510

MB1SSxx"
(MASK PROG)
MB15S02"

I
Super Low
Current &
Analog Switch

"li!BISI5A.J
"I
I' {MBISB01"'{MBI5AOI
13"
I
I
I
I
,I
1
1
I
1
I
I
I

Dual Modulus,
Fixed Ref. Ct.
Divide Ratios

L suffix Low speed lock up; H suffix
• Not for New Designs
•• New Products

MB15A19"
MB1519
MB1514
MB1509

I

I
Dual PLL &
Prescaler

=High speed lock up

I

I
I

Super Low
Current & Small
Package
(SSOP)

Digital
Systems
Device Type

1-5

RFIWIRELESS PRODUCTS
Bipolar Prescalers - 200 MHz to 2.7 GHz
Device
Part No.

Frequency
(Maximum)

Divide
Ratio

Icc (Typ.)

Vcc

10mA

5V

8-pin DIP, SOP

64/65, 128/129

12mA

3V

8-pin DIP, SOP

64/65, 128/129

5mA

5V

8-pin DIP, SOP

32133, 64/65

10mA

5V

8-pin DIP, SOP

32133, 64/65

5mA

5V

8-pin DIP, SOP

32133, 64/65

6mA

3V

8-pin DIP, SOP

128,256

9mA

5V

8-pin DIP, SOP

2.4 GHz

64,128,256

18mA

5V

8-pin DIP, SOP

1.6 GHz

128/129, 256/257

18mA

5V

8-pin DIP, SOP

2.3 GHz

128/129, 256/257,
5121514

24mA

5V

8-pin DIP, SOP

MB501L

1.1 GHz

64/65, 128/129

MB501LV

1.1 GHz

MB501SL

1.1 GHz

MB504

520 MHz

MB504L

520 MHz

MB504LV

520 MHz

MB505-16

1.6 GHz

MB506
MB507
MB508

Package

MB509

1.1 GHz

64/65, 128/129

12mA

5V

8-pin DIP, SOP

MB510

2.7 GHz

128/144, 256/272

10mA

5V

8-pin DIP, SOP

MB511

1.0 GHz

1,2,8

23mA

5V

8-pin DIP, SOP

PrescalerNCO
Device
Part No.
MB551

Frequency
(Maximum)
1.0 GHz

Divide
Ratio

Icc (Typ.)

Vcc

16mA

5V

Icc (Typ.)

Vcc

Tx Mixer

12.7 mA

5V

8-pin SSOP

128/129

Package
8-pin SOP

Super Analog Devices
Device
Part No.

1-6

Frequency
(Maximum)

Features

Package

MB531

1.1 GHz

MB539

1.6 GHz

Low Noise Amp

8mA

5V

8-pin SSOP

MB54501

1.1 GHz

LNAIMixer

6mA

3V

16-pin SSOP

MB54502

1.1 GHz

Dual LNAs

4mA

3V

16-pin SSOP

MB54503

1.1 GHz

PA Driver Amp

26mA

3.6V

16-pih SSOP

MB54609

1.0 GHz

1/0 Modulator

20mA

3V

20-pin SSOP

MB54619

2.0 GHz

1/0 Modulator

25mA

3V

20-pin SSOP

RFIWIRELESS PRODUCTS
Low Power CMOS Phase Locked Loops (PLLs)
Divide Ratio
Device
Part No.

fiN MHz
3V/5V
(max)

@

A

N
Prog.
Ct.

Swallow

R
Refer.
Ct.

loomA
3V/5V

@

Voo

Package

MB87001A

10/13

5-1023

0-127

8-2048

2.0/3.0

2.7-5.5 V

1S-pin DIP, SOP

MB8700SA

10/17

5-1023

0-127

Binary
5-1S383

2.5/3.5

3.0-S.0V

1S-pin DIP, SOP

MB87014A

-/180

5-1023

0-63

Binary
5-65535

-/8.0

4.5-5.5 V

16-pin DIP, SOP

MB87076

10/10

5-2047

0-127

Binary
5-16383

2.5/3.0

2.7-5.5 V

16-pin DIP, SOP

MB87086A

-/95

5-1023

-

Binary
5-65535

-/8.0

4.5-5.5 V

16-pin DIP, SOP

MB87087

10/17

5-1023

0-127

Binary
5-16383

2.5/3.5

3.0-6.0V

16-pin DIP, SOP

MB87091

300/-

5-4095

0-63

Binary
5-16383

8.0/-

2.7-3.3 V

16-pin DIP, SOP,
SSOP

MB87093A

-/145

725

-

64

-/10

4.5-5.5 V

16-pin SSOP

1.1-1.7 V

16-pin SSOP

MB87094

15

@

1.1 V

5-2047

0-127

-

MB87095A

-/110

550

MB87096A

-/90

750

Binary
5-4095

1

@

1.1 V

64

-/10

4.5-5.5 V

16-pin SSOP

128

-/10

4.5-5.5 V

16-pin SSOP

1-7

RFIWIRELESS PRODUCTS
BiCMOS Single-Chip PLUPrescalers (Super PLLs)
Prescaler

PLL

A
Device
Part No.

fiN
(max)

N
Prog. Ct.

Swallow
Ct.

Binary
16-2047

Binary
0-127

Binary
6-16383

6.5mA

3V

16-pin SSOP
20-pin SSOP

R
Refer. Ct.

lee (typ)

Vee

Package

MB15AOl

1.1 GHz

64/65
128/129

MB15B01**

1.1 GHz

64/65
128/129

Binary
16-2047

Binary
0-127

Binary
8-16383

13mA

3V

MB1501*

1.1 GHz

64/65
128/129

Binary
16-2047

Binary
0-127

Binary
8-16383

15mA

3-5 V

16-pin DIP, SOP

MB1501H*

1.1 GHz

64/65
128/129

Binary
16-2047

Binary
0-127

Binary
8-16383

15mA

3-5 V

16-pin SOP

MB1501L*

1.1 GHz

64/65
128/129

Binary
16-2047

Binary
0-127

Binary
8-16383

15 mA

3-5 V

16-pin SOP

MB15A02

1.1 GHz

64/65
128/129

Binary
16-2047

Binary
0-127

Binary
6-16383

7mA

5V

16-pin SSOP

MB1502

1.1 GHz

64/65
128/129

Binary
16-2047

Binary
0-127

Binary
8-16383

8mA

5V

16-pin SOP

MB1502H

1.1 GHz

64/65
128/129

Binary
16-2047

Binary
0-127

Binary
8-16383

8mA

5V

16-pin SOP

MB15B03**

1.1 GHz

64/65,
128/129
16/17,
32133

Binary
5-2047

Binary
0-127

Binary
6-16383

10mA

3V

16-pin SSOP

0.3 GHz

MB15F03**

2.0 GHz
0.5 GHz

64/65,
128/129
16/17,
32133

Binary
5-2047

Binary
0-127

Binary
6-16383

9mA

3V

16-pin SSOP

MB1503

1.1 GHz

128/129

Binary
16-2047

Binary
0-127

Binary
8-16383

8mA

5V

16-pin SOP

MB1504*

520 MHz

32/33
64/65

Binary
16-2047

Binary
0-127

Binary
8-16383

10mA

3-5 V

16-pin SOP

MB1504H*

520 MHz

32133
64/65

Binary
16-2047

Binary
0-127

Binary
8-16383

10mA

3-5 V

16-pin SOP

MB1504L*

520 MHz

32133
64/65

Binary
16-2047

Binary
0-127

Binary
8-16383

10mA

3-5 V

16-pin SOP

MB15E05

2.0 MHz

64/65
128/129

Binary
5-2047

Binary
0-255

Binary
8-16383

6mA

3V

16-pin SSOP

MB1505

600 MHz

32/33
64/65

Binary
16-2047

Binary
0-63

Binary
8-16383

6mA

5V

16-pin SOP

MB15E06

2.5 GHz

64/65
128/129

Binary
5-2047

Binary
0-255

Binary
8-16383

7mA

3V

16-pin SSOP

MB1506

2.0 GHz

128/129
256/257

Binary
5-2047

Binary
0-255

Binary
8-16383

18mA

5V

20-pin SSOP

• Not for New Designs
•• Dual PLUprescaler set

1-8

Divide
Ratio

RFIWIRELESS PRODUCTS
BiCMOS Single-Chip PLUPrescalers (Super PLLs) continued
MB1507

2.0 GHz

128/129
256/257

Binary
16-2047

Binary
0-255

Binary
8-16383

18mA

5V

16-pin SOP

MB1508

2.5 GHz

256/272
5121528

Binary
32-4095

Binary
0-31

256/512
1024/2048

16mA

5V

20-pin SOP

MB1509**

400 MHz

32133
64/65

Binary
16-2047

Binary
0-127

512, 1024

8mA

3V

20-pin SOP

MB15U10**

1.1 GHz

NA

Binary
1024131071

NA

Binary
6-4095

7mA

3V

2Q-pin SSOP

MB1510**

1.1 GHz

64/65
128/129

Binary
16-2047

Binary
0-127

512, 1024

15mA

3-5 V

2Q-pin SOP

MB15B11**

1.1 GHz
0.4 GHz

64/65,
128/129
32133,
64/65

Binary
16-2047

Binary
0-127

Binary
8-16383

9.5mA

3V

20-pin SSOP

MB1511

1.1 GHz

64/65
128/129

Binary
16-2047

Binary
0-127

Binary
8-16383

7mA

3-5 V

20-pin SSOP

MB1512

1.1 GHz

64/65
128/129

Binary
16-2047

Binary
0-127

Binary
8-16383

7mA

3-5 V

20-pin SSOP

MB15B13**

1.1 GHz

64/65
128/129

Binary
16-2047

Binary
0-127

Binary
8-16383

13mA

3V

20-pin SSOP

MB1513

1.1 GHz

128/129

Binary
16-2047

Binary
0-127

Binary
8-16383

7mA

3-5 V

20-pin SSOP

MB1514**

400 MHz

64/65

Binary
16-2047

Binary
0-127

1700

8mA

3V

20-pin SOP

MB1515

2.5 GHz

256/272
5121528

Binary
32-4095

Binary
0-31

256,512
1024,2048

6.5mA

5V

20-pin SSOP

MB15A16

1.1 GHz

NA

Binary
5-2047

Binary
0-127

Binary
6-16383

6.5mA

3V

16-pin SSOP

MB1516A

1.1 GHz

64/65
128/129

Binary
5-2047

Binary
0-127

Binary
6-16383

6.5mA

3V

16-pin SSOP

MB1517A

2.0 GHz

64/65
128/129

Binary
16-2047

Binary
1)-255

Binary
6-16383

14mA

3V

16-pin SSOP

MB1518

2.5 GHz

5121528

Binary
32-511

Binary
0-31

512

16mA

5V

16-pin SOP

600 MHz

64/65

Binary
16-2047

Binary
0-127

256,2048

11 mA

3V

20-pin SOP

MB1519**

600 MHz

64/65

Binary
16-2047

Binary
0-127

512, 1024

11 mA

3V

20-pin SOP

MB15Sxx
Series

300 MHz

16/17

Binary
5-4095

Binary
0-31

Binary
5-4095

3.5mA

3V

8-pin SSOP

MB15S02

284 MHz
116 MHz

16/17

Fixed 17
Fixed 7

Fixed12
Fixed 4

Fixed13
Fixed 13

3.5mA

3V

8-pin SSOP

MB15A19**

* Not for New Designs
** Dual PLUprescaler set

1-9

RFIWIRELESS PRODUCTS

1·10

PIEZOELECTRIC DEVICES
FSCB Series SAW Filters for Mobile Communications
The FSCB series are wide bandpass Surface Acoustic Wave
(SAW) filters for use in the 700 MHz to 1 GHz range. The FSCB
series uses a single lithium tantalate piezoelectric crystal (UTa03) which has a high electromechanical coupling coefficient.
The LiTa03 also provides wide bandwidths and exceptional stability. Fujitsu's exclusive mounting technology makes the FSCB
series very compact and surface mountable. The FSCB is suitable for use in handheld cellular phones.

•

Considerably smaller and lighter than a ceramic filter

•

Surface mount package (SMT)

•

High stopband attenuation types available

•

Wide variety of bandwidths for world-wide systems

•

Low insertion loss

•

High power rating: 0.2 W guaranteed

•

External impedance matching

•

Package: 8-pad ceramic LCC (5.0 mm x S.O mm x 1.S mm)

Product Line-up
Part Number

System

Use

Center Frequency (MHz)

Bandwidth
(MHz)

FAR-FSCB-836M50-G201

AMPS/ADC

Tx

836.5

2S

FAR-F5CB-881 M50-G201

AMPS/ADC

Ax

881.5

25

FAR-FSCB-881 MSO-G211

AMPS/ADC

Rx

881.5

2S

FAR-FSCB-888MSO-G201

ETACS

Tx

888.5

33

FAR-FSCB-933M50-G202

ETACS

Rx

933.5

33

FAR-F5CB-933MSO-G212

ETACS

Rx

933.5

33

FAR-F5CB-902M50-G201

NMT/GSM

Tx

902.5

25

FAR-F5CB-947M50-G201

NMT/GSM

Rx

947.5

2S

FAR-F5CB-947M50-G211

NMT/GSM

Rx

947.5

25

FAA-F5CB-911 MSO-G201

NTACS

Tx

911.5

27

FAR-F5CB-933M50-G201

NTT

Tx

933.5

17

FAR-F5CB-878M50-G201

NTT

Rx

878.5

17

Comment

High stopband
attenuation

High stopband
attenuation

High stopband
attenuation

Package
8 Pad Ceramic LCC
5mm

(BOTTOM VIEW)

(TOP VIEW)

o

0 0

11

1 .5 mm (SIDE VIEW)

1-11

PIEZOELECTRIC DEVICES
FSCC (L2) Series SAW Filters -

son Matched for Mobile Communication

The F5CC series are wide bandpass Surface Acoustic Wave

•

(SAW) filters for use in the 700 MHz to 1 GHz range. The F5CC

•

No external matching circuitry necessary

series uses a single lithium tantalate piezoelectric crystal (U-

•

Lower insertion loss

Ta03) which has a high electromechanical coupling coefficient.
The LiTa03 also provides wide bandwidths and exceptional sta-

•

SMT Package

•

Wide variety of standard products for all the world's major
telecommunications systems

•

High power rating: 0.2 W

•

Package: 6-pad ceramic LCC (3.8 mm x 3.8 mm x 1.5 mm)

bility. The F5CC( L2) series is ultra compact and surface mountable which makes it suitable for use in hand held cellular phones

Ultra compact, light weight

Product Line-up - Standard Version
Part Number

System

Part Symbol

Center Frequency (MHz)

Bandwidth (MHz)

FAA-F5CC-836M50-L2AA

AMPS/ADC (Tx)

AA

836.5

25

FAA-F5CC-881 M50-L2AB

AMPS/ADC (Ax)

AB

881.5

25

17

FAA-F5CC-933M50-L2BA

NIT (Tx)

BA

933.5

FAA-F5CC-878M50-l2BB

NIT (Ax)

BB

878.5

17

FAA-F5CC-888M50-l2CA

ETACS (TX)

CA

888.5

33

CB

933.5

33

FAA-F5CC-933M50-L2CB

ETACS (AX)

FAA-F5CC-911 M50-L2DA

NTACS (Tx)

DA

911.5

27

FAA-F5CC-856M50-L2DB

NTACS (Ax)

DB

856.5

27
25

FAA-F5CC-902M50-L2EA

NMT/GSM (Tx)

EA

902.5

FAA-F5CC-947M50-L2EB

NMT/GSM (Ax)

EB

947.5

25

FAA-F5CC-897M50-L2KA

E-GSM (Tx)

KA

897.5

35

FAA-F5CC-942M50-L2KB

E-GSM (Ax)

KB

942.5

35

FAA-F5CC-950M00-L2FA

PDC (Tx)

FA

950.0

20

FAA-F5CC-820MOO-l2FB

PDC (Ax)

FB

820.0

20

FAA-F5CC-915M00-L2JA

ISMIUSA

JA

915.0

26

FAA-F5CC-935M00-L2LA

2-Way Pager

LA

935.0

12

System

Part Symbol

Center Frequency (MHz)

Bandwidth (MHz)

FAA-F5CC-836M50-L2AZ

AMPS/ADC (Tx)

AZ

836.5

25

FAA-F5CC-881M50-L2AY

AMPS/ADC (Ax)

AY

881.5

25

FAA-F5CC-902M50-L2EZ

NMT/GSM (Tx)

EZ

902.5

25

FAA-F5CC-947M50-l2EY

NMT/GSM (Ax)

EY

947.5

25

Product Line-up - High Attenuation Version
Part Number

1·12

FAA-F5CC-947M50-L2EX

NMT/GSM (Ax)

EX

947.5

25

FAA-F5CC-942M50-l2KY

E-GSM (Ax)

KY

942.5

35

FAA-F5CC-915MOO-l2JZ

ISMIUSA

JZ

915.0

26

PIEZOELECTRIC DEVICES
Packa e
6 Pad Ceramic LCC

(BOTTOM VIEW)

[:J

DI3.amm

(TOP VIEW)

111.smm

(SIDE VIEW)

I '0

0 0

I

1-13

PIEZOELECTRIC DEVICES
F6Cx (L2) Series SAW Filters - SOQ Matched for Mobile Communication
The F6Cx series are wide bandpass Surface Acoustic Wave
(SAW) filters for use in the 1 GHz to 2.5 GHz range. The F6Cx
series uses a single lithium tantalate piezoelectric crystal (LiTa03) which has a high electromechanical coupling coefficient.
The LiTa03 also provides wide bandwidths and exceptional stability. The F6Cx(l2) series is ultra compact and surface mountable which makes it suitable for use in hand held cellular and PCS
phones. Several new standard devices for PCS/PCN Systems
have recently been added to the F6Cx Series SAW Filters.

•

Ultra compact, light weight

•

No external matching circuitry necessary

•

Lower insertion loss

•

SMT Package

•

Wide variety of standard products for all the world's major
telecommunications systems

•

High power rating: 0.2 W

•

Packages:
F6CC (L2): 6-pad ceramic LCC (3.8 mm x 3.8 mm x 1.5 mm)
F6CE (L2): 6-pad ceramic LCC (3.0 mm x 3.0 mm x 1.2 mm)

Product Line-up - Standard Version
Part Number

System

Part Symbol

Center Frequency (MHz)

FAR-F6CC-1 G441 O-l2ZA

PDC (Tx)

ZA

1441.0

Bandwidth (MHz)

24

FAR-F6CC-1 G4890-l2ZB

PDC (Rx)

ZB

1489.0

24

FAR-F6CC-1 G6190-L2ZN

PDC (Lo)

ZN

1619.0

24

FAR-F6CE-1G7475-L2YA

DCS (Tx)

YA

1747.5

75

FAR-F6CE-1 G8425-L2YB

DCS (Rx)

YB

1842.5

75
60

FAR-F6CE-1 G8800-L2XA

PCS (Tx)

XA

1880.0

FAR-F6CE-1 G9600-L2XB

PCS (Rx)

XB

1960.0

60

FAR-F6CE-2G4500-L2WA

ISMIWLAN

WA

2450.0

100

Packa e
6 Pad Ceramic LCC for F6CC (L2) Series

(TOP VIEW)

(BOnOM VIEW)

o

1-14

0 0

II1.5mm

(SIDE VIEW)

PIEZOELECTRIC DEVICES
M2 Series (0100) General Purpose Voltage Controlled Oscillators
The M2 series (0100) voltage controlled oscillators (VCO) operate in the frequency range of 4 to 30 MHz. The M2 series uses a
single lithium tantalate piezoelectric crystal (UTaOa) which has a
high electromechanical coupling coefficient. The UTaOs also
provides a wide variable frequency range and exceptional stability.

± 0.2%

•

Wide variable frequency width:

•

High precision oscillation frequency, ready for use without adjustment

•

High reliability due to hermetically sealed package

•

Custom frequencies also available

•

Package: 4 pin metal case compatible with 14 pin DIP IC
package

Standard Frequencies (MHz)
8.192

13.500

16.934

21.053

9.408

14.318

17.734

21.477

28.224

11.290

16.000

18.432

22.579

28.322

11.580

16.257

18.816

24.576

26.636

12.288

16.384

20.480

25.175

33.868

27.338

Package

Metal Case DIP 14
(Top)

(Bottom)

20.8mm max.

13.1 mm
max.

7.6mm

(Side)

I-

18.3 mm

~I

~~mm
__

~~

mm --

~~6.3mm

1-15

PIEZOELECTRIC DEVICES
M2 Series (0300) Voltage Controlled Oscillators for Digital Audio
The M2 series (0300) voltage controlled oscillators (VCO) operate in the frequency range of 4 to 30 MHz. They use a single lithium tantalate piezoelectric crystal (LiTa03) which has a high electromechanical coupling coefficient. The LiTa03 also provides a
wide variable frequency range and exceptional stability. The
0300 module contains 3 VCOs for the three sampling frequencies used in digital audio equipment (32, 44.1, and 48 kHz). The
frequencies are selected by external signals.
•

Clock replay in response to 3 sampling frequencies (32, 44.1
and 48 kHz)

•

Wider variable frequency width than in quartz crystals:
±0.1 % or more

•

Excellent stability for signal noise reproduced by high quality
of the lithium tantalate

•

100 times more stable than VCOs of LC and TTL IC configuration

•

3 sampling frequencies controlled at CMOS logic level

•

Compatible with the Electronic Industry Association of Japan
(EIAJ) digital 1/0 standard type II (consumer digital audio
eqUipment), Level I (high resolution mode and Level II (standard resolution mode)

•

Package: 16 pin Single in Line Package for high density
mounting

Standard Combinations of Frequencies
Type A

TypeB

TypeC

f01 (L)

8.192 MHz

32 kHz x 256

f02 (M)

11.290 MHz

44.1 kHz x 256

f03 (H)

12.288 MHz

48 kHz x 256

f01 (L)

12.288 MHz

32 kHz x 384

f02 (M)

16.934 MHz

44.1 kHz x 384

f03 (H)

18.432 MHz

48 kHz x 384

f01 (L)

16.384 MHz

32 kHz x512

f02 (M)

22.579 MHz

44.1 kHz x 512

f03 (H)

24.576 MHz

48 kHz x512

Package

16 Pin SIP Module
8.0 mm max

43.0mm max

O.4mm
2.54mm

1-16

0.3mm

PIEZOELECTRIC DEVICES
M3 Series (0001) General Purpose SAW Voltage Controlled Oscillators
The M3 series (0001) voltage controlled oscillators (VCO) operate in the frequency range of 50 to 300 MHz. They use a single
lithium tantalate (LiTa03) SAW resonator. The M3 series VCOs
oscillate directly in the VHF band up to 300 MHz and have a wide
variable frequency range and high temperature stability.
•

Direct oscillation at high frequencies: 50 to 300 MHz

•

Wider variable frequency range: 800 ppmN or more (0.5 to
4.5 V)

•

Superb temperature characteristics: ±200 ppm (0 to 60°C) or
less

•

High-precision oscillation frequency, ready for use without
adjustment

•

High reliability due to hermetically sealed package

•

High carrier noise ratio: -90 dB or less (12.5 kHz detuning,
8 kHz band)

•

Frequency offset by built-in offset terminal

•

Package: 5 pin metal case compatible with 16 pin DIP IC
package

III

Standard Frequencies
Frequency

Application

Part Number

74.25 MHz

Professional HDTV

M3DA-74M25D-DOOl

97.20 MHz

Transmission Standard HDTV

M3DA-97M20D-DOOl

115.52 MHz

Broad-band ISDN

M3DA-155M52-DOOl

Package
Metal Case DIP 16

(Top)

(Bottom)
17.78 ± 0.5 (0.700 ± 0.020)

25.6 MAX (1.008)

--"1---+...=2..=..54 ± 0.5 (0.100 ± 0.020)

13.08 MAX
(0.515)

7.62± 0.5
(0.300 ± 0.020)

0000000

(Side)
5.9±0.5

c:::;==~==~;;:;;:~

-.l.------t-

(0.232 ± 0.020)

~

0.4±0.1
5.0±0.5
_(,-0._0_16_±_0_.0_0_4}'--L... (0.197 ± 0.020)
Units: mm (inches)

1-17

PIEZOELECTRIC DEVICES
M3 Series (0101) SAW Modulators
The M3 series (0101) SAW modulators contain direct oscillators
(50 MHz to 300 MHz). They use a single lithium tantalate (LiTa03)
SAW resonator. The M3 series modulators can be used in direct
modulation applications requiring high modulation sensitivity and
a high signal to noise ratio in the VHF band (up to 300 MHz)
•

High frequency direct modulation: 50 to 300 MHz

•

High modulation sensitivity: 800 ppmN min. (0.5 to 4.5 V)

•

Excellent modulation distortion ratio: 40 dB max. (1 kHz to
1.75 kHz dev.)

•

Excellent signal to noise ratio: -50 dB max.

•

Excellent temperature characteristic: + 200 ppm max. (-20 to
700 C)

•

Highly reliable hermetically sealed package

•

Package: 5 pin metal case compatible with 14 pin DIP IC
package

Standard Frequency
Standard Frequency

Application

Part Number

145.0 MHz

Mobile Phone

M3DA-145MOD-D101

Package

Metal Case DIP 14
(Top)

(Bottom)

20.8 mm max.

15.2 mm

13.1 mm
max.

(Side)

I-

18.3 mm

·1

~~m

~~5

1-18

mm-

~~6.3mm

7.6mm

POWER MANAGEMENT DEVICES
MB3802 - Power Management Switch
Enhance PC Notebook Battery Life With This Power-saving
Switch
The notebook PC typifies the recent trend in electronic devices towards
compact, lightweight, battery-driven products that can be used anywhere, anytime. Use of this IC facilitates the contribution to the "green
computer."
A major problem with such battery-driven devices is brief or insufficient
battery life. This has focused attention on the issues of reducing power
consumption and simultaneously extending battery life. Notebook PCs
and other small computers switch off power to peripheral devices (hard
or floppy disk drives, PCMCIA Cards, etc.) that are not operating. The
circuits that control the switches, however, are either 3V or 5V circuits
and operate constantly, consuming energy.
To control power lines to peripheral devices, FUJITSU has developed
the MB3d0210w-voltage :nput switch (VIN > 2.2V typ.), which consumes
no current when the switches are turned off.

MB3807A - Flash Memory Power
Management Switch
Fujitsu has specifically developed the MB3807A to efficiently control
Flash Memory devices, however it is also ideally suited for power control
of other battery powered portable applications. The W,B3807A consists
of two SPOT switches, with each switch conSisting of one pole suited for
higher current requirements (.5 Amps) at typically 12 Volts and the other
pole suited for lower cur:-ent req'Jire,ments (.1 Amps) typically from 3/5
Voft sources.

1·19

POWER MANAGEMENT DEVICES
MB3802 - Power Management Switch
•

Small Supply Current : ON State 100 !AA
OFF State 0 I4A

Operates on low input voltage, ideal for use in 3V systems

•

Low Control Voltage : 2.5V - 6V

Low On Resistance : 120mO x 2 channels
(Power NMOS FET Included)

•

Rush Current Protection

•

Small Package: Narrow SOP16

•

Controls power lines to peripheral devices

•

Greatly extends use of battery-driven notebook PCs

•
•

Low Leak Current : < 1 !AA (Both Directions)

•

Product Line-up - Power Management Switches
Part Number

Numberof.
Channels

ON
Resistance

Handling
OCCurrent

Handling
Voltage

Switch
Mode

Applications

MB3802

2

0.120

1.2A

<7V

SPST

Notebooks
Laptops
Handhelds
Portables
PCMCIA Cards

MB3807A

2

0.30
60

0.5A
0.1A

<15V

SPOT

Flash Memory
PCMCIA Cards

MB3802 Block Diagram and External Connections
Co
External
Capacitor

1-20

POWER MANAGEMENT DEVICES
MB3807A -

Power Management Switch for Flash Memory

•

Power Management Switch for Flash Memory

•

Compatibility for a PCMCIA Digital Interface

•

Controls Two PCMCIA Card Slots

•

Low On Resistance: 12V Port 0.30
5V Port 60

•

5V Port Supports 3.3V and 5V Operation

•

Small Package : Narrow SOP16

Product Line-up - Power Management Switches
Part Number

Number of
Channels

ON
Resistance

Handling
DC Current

Handling
Voltage

Switch
Mode

MB3802

2

0.120

1.2A

<7V

SPST

Notebooks
Laptops
Handhelds
Portables
PCMCIA Cards

MB3807A

2

0.30
60

0.5A
0.1A

< 15V

SPOT

Flash Memory
PCMCIA Cards

Applications

MB3807A Block Diagram and External Connections
DLY

EN1
Switch-ON
circuit
Charge Pump

(SW1)

Switch-ON
circuit
Charge Pump

1-21

POWER MANAGEMENT DEVICES

1-22

SECTION 2
Prescalers - At a Glance
Fujitsu offers a wide range of prescaler devices capable of satisfying the technical requirements of today's
applications. Features include devices covering the 200 MHz to 2.7 GHz range, low power consumption,
and a multitude of divide ratios.

Page
Number
2-3

Device
Part
Number

fiN (max)

Divide Ratio

lee (typ)

Vee

Package

MB501L

1.1 GHz

64165, 128/129

10mA

5V

2-15

MB501LV

1.1 GHz

64/65, 128/129

12mA

3V

8-pin, DIP, SOP
8-pin, DIP, SOP

2-25

MB501SL

1.1 GHz

64/65, 128/129

SmA

5V

8-pin, DIP, SOP

2-3

MB504

520 MHz

32/33, 64/65

10mA

5V

8-pin, DIP, SOP

2-3

MB504L

520 MHz

32/33, 64/65

SmA

5V

8-pin, DIP, SOP

2-15

MB504LV

520 MHz

32133, 64/65

6mA

3V

8-pin, DIP, SOP

2-35

MBS05-16

1.6GHz

128,256

9mA

SV

8-pin, DIP, SOP

2-39

MB506

2.4 GHz

64,128,256

18mA

5V

8-pin, DIP, SOP

lBmA

SV

8-pin, DIP, SOP

2-43

MBS07

1.6 GHz

128/129,
256/257

2-51

MB508

2.3 GHz

128/129,
256/257

24mA

5V

8-pin, DIP, SOP

2-59

MB509

1.1 GHz

64/65, 128/129

12mA

5V

8-pin, DIP, SOP

2-67

MB510

2.7 GHz

128/144,
256/272

10mA

5V

8-pin, DIP, SOP

2-73

MB511

1.0 GHz

1,2, B

23 rnA

5V

8-pin, DIP, SOP

2-81

MBSS1

1.0 GHz

128/129

16mA

5V

8-pin, SOP

2-1

2-2

00
FUJITISU
~~§n~®§§§§§§~~~~~
11
August 1995

~

DATA SHEET

MBS01 US041S04L
TWO MODULUS PRESCALERS

Ell

TWO MODULUS PRESCALERS
The Fujitsu MB501 U504/504L are two modulus prescalers, which are use with
a frequency synthesizer to make a PLL (Phase Locked Loop). They will divide
the input frequency by the modulus of 64/65 or 128/129 for the MB501 L, and
32133 or 64/65 for the MB504/MB504L. The MB501 Land MB504L are
low-power versions. The output of 1.6V peak to peak on ECL level applies to all.
• High Operating Frequency, Low Power Operation:
1.1 GHz at 50mW typo (MB501 L)
520MHz at 50mW typo (MB504)

PLASTIC PACKAGE
DIP-08P-M01

520MHz at 25mW typo (MB504L)
• Pulse Swallow Function

=-40°C to +85°C

• Wide Operation Temperature

TA

• Stable Output Amplitude:

VOUT = 1.6Vp-p

• Complete PLL synthesizer circuit with the Fujitsu MB87001 A, PLL
synthesizer IC
• Plastic 8-pin Standard Dual-In-Line Package or space saving Flat Package

PLASTIC PACKAGE
FPT-08P-M01

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Symbol

Value

Unit

Supply Voltage

Vce

-0.5 to +7.0

V

Input Voltage

VIN

-0.5toVce

V

Output Current

Vo

10

mA

Ambient Temperature

TA

-40 to +85

°C

Storage Temperature

TSTG

- 55 to +125

°C

Rating

PIN ASSIGNMENT

IN

Vee
SW

OUT

Note:

Permanent device damage mayoccurifthe above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in
the operational soctio~s of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Thisdevicecontainscircu~rytoprotecttheinputsagainstdamage

due to high static voltages or electric fields. However, ~ is advised
that normal precautions be taken to avoid application of any
voltage higher than maximum rated voHages to this high
impedance circu~.

Copyright © 1990 by FUJITSU LIMITED

2-3

MB501L
MB504
MB504L

a) MB501L

MB5011
MB501L
OUT

Note:

SW

Me

H

H

1/64

H

L

1/65

L

H

1/128

L

L

1/129

Divide Ratio

SW: H = Vee. L = OPEN
Me: H 2.0V to Vee.
L GND to O.8V

=

=

b) MB504IMB504L

MB504I
MB504L
OUT

Note:

2-4

Me

Divide Ratio

H

H

1/32

H

L

1/33

L

H

1/64

L

L

1/65

=

=

SW: H Vee. L OPEN
Me: H =2.0V to Vee.
L GND to O.8V

=

Figure 1. Block Diagrams

SW

MB501L
MB504
MB504L

PIN DESCRIPTION
Pin Number

Symbol

Function

1

IN

2

Vee

DC Supply Voltage

3

SW

Divide Ratio Contro/lnput (See Divide Ratio Table)

4

OUT

Output

5

GND

Ground

6

MC

Modulus Control Input (See Divide Ratio Table)

7

NC

Non Connection

8

m

Complementary Input

Ell

Input

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Unit

Symbol

Supply Voltage

Vee

Output Current

10

Ambient Temperature

TA

Load Capacitance

CL

Min.

Typ.

Max.

4.5

5.0

5.5

1.2
-40

V

mA

+85

°C

12

pF

2-5

MB501L
MB504
MB504L

ELECTRICAL CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Value
Parameter

Symbol

Conditions

Unit
Min.

MB501L
Power Supply Current

MB504

1/0 pins are open

Icc

MB504L
Output Amplitude

1.0

Vo

Input Signal Amplitude for IN

mA

5

7"

mA
Vp_p

1.6

520

MHz

MB504L

10

520

MHz

MB501L

-4

5.5

dBm

-12

10

dBm

-12

10

dBm

MB504

fiN

PIN

Low Level Input Voltage for MC

VILM

..

VIHS

Low Level Input Voltage for SW

VILS

High Level Input Current for MC

IIHM

VIH=2.0V

Low Level Input Current for MC

IILM

VIL =0.8V

MB504
MB504L

tSET

V

2.0

High Level Input Voltage for SW

MB501L

2-6

mA

14"

10

MB504

VIHM

* Vcc = 5V. TA = 25°C
•• Design Guarantee

14"

10

MHz

High Level Input Voltage for MC

Note:

10

1100

With input coupling
capacitor 1000pF

MB504L

Modulus Set-uo lime
MCtoOUT

Max.

10

MB501L
Input Frequency

Typ.

Vcc-o· 1

Vcc

0.8

V

Vcc+ 0 . 1

V

OPEN

V
0.4

mA
mA

-0.2
16

26

ns

20

30

ns

18

28

ns

MB501L
MB504
MB504L

MB501 L TIMING CHART (2 MODULUS)

II

Example: Divide Ratio of 64/65

~

IN

______

64
-JA~

______

65
~

r -______-JA~________~

J1fl-JU1Jl--M-----M--J1JUlJl--M
j

32

32_~_~r- - -- - -- --1""'-_3_2_---1

L

33

J - -_ _

,

OUT

Me

Note:

"-----'

~

I

I

tSET

I

tSET

I

When divide ratio of 65 is selected, positive pulse is applied by one to 33.
The typical set up time is 16ns (MB501L) from the Me signal input to the timing of
change of prescaler divide ratio.

2-7

MB501L
MB504
MB504L

MB504IMB504L TIMING CHART (2 MODULUS)

Example: Divide Ratio of 32133

r -______

j

16

32
-JA~

______

~\

r -______

33
-JA~

______

16_~~~r- - - -- -- - -1,",,"__1_6_ - I

~

L

17

..Io--_ _

,,

OUT

Me
"---+'
I

Note:

2-8

tSET

I

'+---'
I

tSET

I

When divide ratio of 33 is selected, positive pulse is applied by one to 17.
The typical set up time is 20ns (MB504), 18ns (MB504L) from the Me signal input to the timing of
change of prescaler divide ratio.

MB501L
MB504
MB504L

Vee

I

J;

Sampling scope input point
for input wavefonn
Vee

C1
IN

P.G.

son

=+s.ov ± 10%

C3

Ell

Sampling scope prober paint
for output waveform

SW
OUT

TN
C2

CL
MC

GND

RL

MC Input

C1: 1000pF
C2: 1000pF

Ca: 0.1~F

CL: 12pF (including scope and jig capacitance)
RL: 2kn

Figure 2. Test Circuit

2-9

MB501L
MB504
MB504L

TYPICAL CHARACTERISTICS CURVES

~

1000

~

I-

I.

J

500

1000

Vee = S.OV
TA = 2SoC

MBJ01L

w

c

800

:::i

a..

~
c(

..J

600

c(

Z

CJ

en

400

I~

a..

~
~

200

~

~

z

:E

"-

0

10

20

SO

100

200

2000

INPUT FREQUENCY (MHz)

Figure 3. Input Signal Amplitude vs. Input Frequency

:>
g
w

c

~

1000

I MBSO~

Vee =IS.OV
TA=2SoC

800

I-

:::i

a..

~
c(
..J
c(

Z

CJ

en

600

400

I~

a..
~

200

~
~

~

Z

:E

0

i'-- I---10

20

SO

100

200

INPUT FREQUENCY (MHz)

-----""

SOO

1000

Figure 4. Input Signal Amplitude vs. Input Frequency

2-10

MB501L
MB504
MB504L

TYPICAL CHARACTERISTICS CURVES (Continued)

Ell
~

1000

w
c 800
=>
~

Vee ~ S.OV
TA=2S o C

I MBsolL

:::::i

Cl.

::e

<
<
Z

600

en

400

...J

(!)
~

=>
Cl.
~

200

Z

0

::e
=>
::e
:E

-

10

20

50

100

200

500

1000

INPUT FREQUENCY (MHz)

Figure 5. Input Signsl Amplitude VB. Input Frequency

2-11

MB501L
MB504
MB504L

OUTPUT

Clock
Data

LE

47Kn 47Kn 47Kn

S/W
Control ( } - - - - - - - - - - - - + - + - - '

:12.8MHz x'tal
: +2.75V to +4.5V
: 8VMax.
: depends on crystal oscillator

Lock
Det.
lOKQ

An example of application of MB501 U504/504L with PLL Synthesizer IC MB87001 A

Figure 6. Typical Application Example

2-12

MBS01L
MBS04
MBS04L

PACKAGE DIMENSIONS
8-LEAD

PLASTIC DUAL IN-LINE PACKAGE
01)
(CASE No.: DlP-08P-M

+ .016
.370 -.012

'I

~~===nl
244 ± .010

U::~;:::=::;:::;==rrr':r O~I
+ .012

.039

:.~)..

( 0.99 -0.00

I

I I
· '(:i~)
+ .012

.172 (4.36) MAX .

.118 (3.00) MIN .

. 100(2.54)
TYP.

.018 ±.003
(0.46 ±a.08)

Dimensions in inches (millimeters) .
©1988 FUJITSU LIMITED D08006S·2C

2-13

MB501L
MB504
MB504L

PACKAGE DIMENSIONS (Continued)
8-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-08P-M01)

.089(2.25) MAX.
(SEATED HEIGHT)
.002(0.05) MIN.
(STANDOFF)

cf

lNDEX

l

·307±.016
(7.8O±O.40)
1

.209±.012
(5.30±O.30)

~==n==;t::~

.0~~~7)

J I.(~:~~)
.150(3.81)

.020±.008

JL

1$1 0.005(0.13l@1

(0.5O±O.20)

+ .002
+ 0.05
.006 -.001 (0.15_ 0.02 )

r-------,

REF.
"A"

I
I
I
I
I
I
I
I

Details of "A" part

.008(0.20)

.020(0.50)
.007(0.18)
MAX.
.027(0.68)

L ___

I
I
I
I
I
I
I
I

~~·_.J

Dimensions in inches (millimeters).
©1988 FUJITSU LIMITED F08002S-3C

2-14

cO
FUJI"SU
=~~n4.~~~~~~~~ .1,
Sept. 1995

=

DATA SHEET

MBS01 LV/S04LV
LOW VOLTAGE/LOW POWER TWO MODULUS PRESCALERS

Ell

LOW VOLTAGE/LOW POWER TWO MODULUS PRESCALERS
The Fujitsu MB501 LV/504LV are low power and low voltage versions of
MB501/504, two modulus prescalers used with a frequency synthesizer to make
a Phase Locked Loop (PLL). They will divide the input frequency by the modulus
of 64/65 or 128/129 for the MB501 LV, and 32133 or 64/65 for the MB504LV. The
output level is 1.1 V peak to peak on ECL level.

• Wide Low Voltage Operation

3.0V typ., +2.7 to 4.5V

• High Frequency Operation, Low Power Operation (VIN

=-12dBm min.)

PLASTIC PACKAGE
DIP-08P-M01

1.1 GHz at 36mW typo (MB501 LV)
520MHz at 18mW typo (MB504LV)
• Pulse Swallow Function

=-40°C to +85°C

• Wide Operation Temperature

TA

• Stable Output Amplitude

Your = 1.1Vp-p typo

• Built-in a termination resistor
Stable output amplitude is obtained up to output load capacitance of 8pE

PLASTIC PACKAGE
FPT-08P-M01

• Complete PLL synthesizer circuit with the Fujitsu MB87001 A, PLL
synthesizer IC
• Plastic 8-pin Standard Dual-In-Line Package or space saving Flat Package

IN

ABSOLUTE MAXIMUM RATINGS (see NOTE)

vee
Symbol

Value

Unit

Supply Voltag3

Rating

Vee

-0.5 to +7.0

V

Input Voltage

VIN

-0.5 to + Vee

V

10

10

mA

TSTG

-55to +125

·C

sw

Output Current
Storage Temperature

Note:

OUT

Permai1entdevicedamage mayoccurifthe above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in
the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Thisdevicecontainscircunrytoproteclthe inputsagainsl damage
due to high slatic vohages oreleclric fields. However, n is advised
that normal precautions be taken to avoid application of any
vohage higher than maximum rated vohages to this high
impedance circun.

Copyright © 1992 by FUJITSU LIMITED

2-15

MB501LV
MB504LV

Fig. 1 - BLOCK DIAGRAMS

a) MBI01LV

OUT

Oil/ide Ratio

SIN

Me

H

H

1/64

H

L

1/85

L

H

11128

L

L

11129

Note: SW: H - Vee. L - open
Me: H - VIHM to Vee.
L - GND to O.8V
1
VIHM - 2"Vee +O.3V

b) MeI04LV

l'f,j

IN

sw

Me

Oil/ide Ratio

H

H

1/32

H

L

1133

L

H

1/64

L

L

1/85

OUT

Note: SW: H - Vee. L - open
Me: H - VIHM to Vee.
L - GND to O.8V
1
vlHM -'2Vee + O.3V

2-16

MB501LV
MB504LV

II

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Symbol

Supply Voltage

Vee

Output Current

10

Ambient Temperature

TA

Load Capacitance

CL

Unit
Min

Typ

Max

2.7

3.0

4.5

1.2
-40

V
mA

+85

°c

8

pF

PIN DESCRIPTION
Pin Number

Function

Symbol

1

IN

Input

2

Vee

DC Supply Voltage

3

SW

Divide Ratio Control Input (See Divide Ratio Table)

4

OUT

Output

5

GND

Ground

6

MC

Modulus Control Input (See Divide Ratio Table)

7

NC

Non Connection

8

TN

Complementary Input

2-17

MB501LV
MB504LV

ELECTRICAL CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Value
Parameter

Symbol

Conditions

Unit
Min.

MB501LV
Power Supply Current

Icc

0.8

Vo
MB501LV

Input Frequency

fiN

PIN

High Level Input Voltage for MC Input

VIHM

Low Level Input Voltage for MC Input

VILM

High Level Input Voltage for SW Input

VIHS

Low Level Input Voltage for SW Input

VILS

High Level Input Current for MC Input

IIHM

VIH =2.0V

Low Level Input Current for MC Input

IILM

VIL= 0.8V

MB501LV
Modulus Set-up Time
MCtoOUT

2-18

mA

6

rnA

1.1

Vp_p

10

1100

MHz

10

520

MHz

-12

5.5

dBm

VIHM = 1/2 Vee +0.3

V

VIHM

Vcc-o· 1

Vec

0.8

V

Vec+ 0.1

V

OPEN

V
0.4

-0.2

rnA
rnA

16

26

ns

18

28

ns

tSET
MB504LV

Note: • DeSign Guarantee

12

With input coupling capacitor
1000pF

MB504LV
Input Signal Amplitude

Max.

Vcc=3.0V

MB504LV
Output Amplitude

'TYP·

MBS01LV
MBS04LV

MB501LV TIMING CHART (2 MODULUS)
Example: Divide ratio = 64/65

65

64

IN

rul····IlM· ··TW·· ... Ilfl" fUlfUl"fU1
J

32

1.-_ _
3_2_--.Jf

.... . .. .

·l.,..',~_ _3_2_---,J

L

33

OUT

MC---------------~

:---~

, !sET '

---

: !sET

:

Note: When divide ratio of 65 is selected, positive pulse is applied by one to 33.
The typical set up time is 16 ns from the MC signal input to the timing of change of prescaler divide ratio.

2-19

MB501LV
MB504LV

MB504LV TIMING CHART (2 MODULUS)
Example: Divide ratio = 32/33

33

32

INM····J1M·····M· ·l1Jl .nJlJUll1J1

J

16

..,.Jr -----

L..-_ _
16
__

H

••

_.

·l.,..\_ _16_ _-,

17

L

OUT

MC------------------------------~

IsET :

: IsET

Note: When divide of 33 is selected. positive pulse is applied by one to17.
The typical set up time is 18 ns from the MC signal input to the timing of change of prescaler divide ratio.

2-20

MB501LV
MB504LV

Fig. 2 - TEST CIRCUIT

+2.7Vto+4.5V
Sampling scope input point
for input waveform
Sampling scope prober point
for output waveform

Vee

P.G.

OUT~-~----------~

IN

L -_ _ _...lJ

son
MC GND

MC input

C, : 1000pF
C2: 1000pF
C3: O.lJ.1F
C L : 8pF (including scope and jig capacitance)

TYPICAL CHARACTERISTICS CURVES
Fig. 3 - INPUT SIGNAL AMPLITUDE
vs. INPUT FREQUENCY

""i
Ii.

>

.sw 1000
0
:::l
t-

:J
Q.
:2

«
«
Z

..J

t:l

en

Vee = 3.0V
TA = 25°C

MB501lV

800

~

«
..J
«
z

600

~

MB504lV

Vee = 3.0V
TA = 25°C

800

600

t:l

iii 400

400

t:::l

Q.

~

200

200

:2

:::l

~

o
~
:J
Q.

:2
Z

.sw 1000
:2

t:::l
Q.

Fig. 4 - INPUT SIGNAL AMPLITUDE
vs. INPUT FREQUENCY

""i
Ii.

>

0

:::l

1---....
10

20

1.0

50

100

200

500

INPUT FREQUENCY (MHz)

1000 2000

~
Z

~

o

~

10

20

50

100

200

INPUT FREQUENCY (MHz)

500

1000

2-21

MB501LV
MB504LV

Fig, 5 - TYPICAL APPLICATION EXAMPLE

Vsx (Max. 8 V)
Vee
10Kn
12Kn

OUTPUT
12Kf2

10Kn
Clock O } - - - - - _ - - - - '
Data 0 - - - _ . - - + - - - - -

LE

MB 501 LVI504LV

Vee
Vsx

12.8 MHz X'tal
+2.7V to +4.5V
8V Max.

C" C2

depends on crystal oscillator

XI

L;::O~---it~-10-K-n----------------------~

2-22

M8501LV
M8504LV

Ell

PACKAGE DIMENSIONS
8-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-08P-M01)
370'

gi~

(940 +-0 40)
- 030

r---

INDEX
244 t01 0
(620 t025)

300(762)

TYP

~:::::r=r:=::::;::::;:=:¢J~
039~J>12
(099~g30)

I

1060~J>12
(152~g30)

035~g1~
(089 ~gjg)
172(436) MAX

.118(3.00) MIN

100(254)

TYP
~

1988 FUJITSU LIMITED D08006-2C

018±.003
(046tO.08)
Dimensions in
inches (millimeters)

2-23

MB501LV
MB504LV

PACKAGE DIMENSIONS (Continued)
8-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-08P·M01)

089(2.25) MAX
(SEATED HEIGHT)

1-1

~======~-.,

I
.

[.307±.016

p.80±040)

'

IN[)J:X

0

.26B ~ :g6~(6.80 ~ 8:~gl

.209±.012
(s.30±0.30)

~::::;t::=n==~--. j
.0SO( 1.27)

I

TYP

,

_

J'

R

__ i

JL

01 8 00
1.
:0. 104J$I¢.00s(0. 13)@1
,(0.4 5 _. ~

i .150(3.81)

t-- - - REF

_

-I

"A"

1. 020 ±.008
(O.SO± 0.20)

'+·002(0 lS+0.0S)
.006 - .001 . -0.02

r - - - - - -- - - - - - - - ,
I

:,

Details of "A" part

I

~00B(0'20);

,
I
I

.

:
,

:
I

II
~

I

I
I
I
I

.020(0.50):
.007(0.18) :

: MAX
i.027(0.6B)
MAX

:
I

IL _______________ JI

Dimensions in
Inches (millimeters)

C 1988 FUJITSU LIMITED F08OO2S·3C

All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical
semiconductor applications. Complete Information sufficient for construction purposes
is not necessarily given.
The Information contained in this document has been carefully checked and is believed
to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
The Information contained in this document does not convey any license under '~he
copyrights, patent rights or trademarks claimed and owned by Fujitsu.
\
Fujitsu reserves the right to change products or specifications without notice.

\

No part of this publication may be copied or reproduced in any form or by any means, or
transferred to any third party without prior written consent of Fujitsu.

2-24

0)

FUJI~SU

Sept. 1995

=~§na~~~~~~~~
=
DATA SHEET

I,

MB501SL
SUPER LOW POWER TWO MODULUS PRESCALER

lEI

SUPER LOW POWER TWO MODULUS PRESCALER
The Fujitsu MB501 SL is a super low power version of the MB501 two modulus
prescaler used with a frequency synthesizer to make a Phase Locked Loop
(PLL). It divides the input frequency by the modulus of 64/65 or 128/129,
respectively. The MB501 SL achieves extremely small stray capacitance by the
use of Fujitsu's Advanced Process Technology. High speed operation is
achieved with low power supply current of 5mA which is about half of the current
value of the MB501L.

• High Frequency Operation:

fmax =1.1 GHz max. (PIN =-14bBm)

• Pulse Swallow Function:

64/65, 128/129

• Low Power Supply Current:

5.OmAtyp.

• Stable Output Amplitude:

Vo = 1.6Vp-p typo

PLASTIC PACKAGE
DIP"()SP·M01

PLASTIC PACKAGE
FPT-OSP-M01

•

• Complete PLL synthesizer circuit with the Fujitsu MB87001 A, PLL
synthesizer IC
• Plastic 8-pin Dual-In-Line Package
• Plastic 8-pin Mini Flat Package

PLASTIC PACKAGE
FPT"()SP-M02

• Built-in Termination Resistor
• Stable output amplitude is obtained up to output load capacitance of 8pF.

IN

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating

Symbol

Value

Unit

Vee

-0.5 to +7.0

V

Vee
SW

Power Supply Voltage

OUT

Input Voltage
Output Voltage
Storage Temperature

Note:

VIN

-0.5 to + Vee

V

10

10

mA

TSTG

-55to+125

°c

Pennanent device damage may occur ifthe above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in
the operational sections I)f this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ThisdevicecontainscircuRrytoprotecttheinputsagainstdamage
due to hlghstaticvoltagesorelectrlcflelds. However,lt Is advised
that npnnal precautions be taken to avoid epplicalion of any
voltage higher than rnaxi'IIum rated voltages to this high
Impedance circuit.

Copyright C> 1995 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS

2-25

MB501SL
Fig. 1 - MB501 SL BLOCK DIAGRAM

iNo--~
IN D----'IIr.-,

IJo-+--o OUT

MB501SL

SW

MC

H

H

Divide Ratio
1/64

H

L

1165

L

H

1/128

L

L

1/129

Note: SW: H = VCG • l =open
MC: H =2.0V to VCG •
L =GND to O.8V

PIN DESCRIPTION

2-26

Pin Number

Symbol

1

IN

2

VCG

Power Supply. +5V

3

SW

Divide Ratio Control Input (See Divide Ratio Table)

4

OUT

Output

5

GND

Ground

6

MC

Modulus Control Input (See Divide Ratio Table)

7

NC

Non Connection

8

iN

Complementary Input

Description

Input

MB501SL

RECOMMENDED OPERATING CONDITIONS
Values
Parameter

Symbol

II

Unit
Min.

Typ.

Max.

Power Supply Voltage

Vee

4.5

5.0

5.5

V

Operating Temperature

TA

-40

-

+S5

DC

Load Capacitance

CL

-

-

S

pF

ELECTRICAL CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Values
Parameter

Symbol

Condition

Unit
Min.

Typ.

Max.

-

5.0

7.0

mA

-

Vp_p

Power Supply Current

Icc

-

Output Amplitude

Vo

Built-in a termination resistor.
Load capacitance = SpF

1.0

1.6

Input Frequency

fin

With input coupling capacitor
1000pF

10

-

1100

MNz

Input Signal Amplitude

PIN

-

-14

-

0

dBm

High Level Input Voltage for MC

VIHM

-

2.0

-

-

V

Low Level Input Voltage for MC

V:LM

-

-

-

O.S

V

High Level Input Voltage for SW

V:HS

-

Vee-O· 1

Vee +0.1

V

Low Level Input Voltage for SW

I'ILS

-

High Level Input Current for MC

IIHM

VIH=2.0V

-

-

0.4

mA

Low Level Input Current for MC

IILM

VIL=0.8V

-0.2

-

-

rnA

Modulus Set-up lime MC to Output

tSET

-

-

16

26

ns

Vee

V

OPEN

Note: • Design Guarantee

2-27

MB501SL
Fig. 2 -TEST CIRCUIT

Vee = +5.0V ±10%
Sampling scope input point
for input waveform

/

Vee

Sampling scope prober point
for output waveform

SW

C,

IN

P.G.

OUT

iN
Cl

Cz
MC

GND

MC input

C, : 1000pF
C 2 : 1000pF

C3 : O.lI1F
Cl : 8pF(inciuding scope and jig capacitance)

TWO MODULUS OPERATING TIMING CHART
Example. Divide Ratio of 64/65

IN

64

65

r~----------~~'----------~~

r~-----------~~----------~

JlJl--JlM.--1lfl----Il1l--~--.M
I

8
I

j

32

i

I

32

~

'
,

•

J-------1

•

I

32

33

OUT

MC

1

,

:--I

tSET

Notes:
When divide ratio of 129 is selected, positive pulse is added by one to 65.
The typical set up time(tsn) is 16 ns from MC signal input to the timing of change of prescaler divide ratio.

2-28

L

MB501SL

TYPICAL CHARACTERISTICS CURVES

III

Fig. 3 - INPUT SIGNAL AMPLITUDE vs. INPUT FREQUENCY

E

10

CD
~

z

;>
W

o

::>

Vee = 4.5V
Vee = 5.0V
Vee = 5.5V

0

f-

:J

a..

::E

DATASHEET SPEC

«


~ -20

::E
::>
::E

Z

~

-30

0.8

1.0

1.2

1.4

INPUT FREQUENCY t'N(GHz)

Fig. 4 - INPUT SIGNAL AMPLITUDE vs. INPUT FREQUENCY
Vee

E

= 5.0V

10

CD

~
z

TA = -40°C
TA = 25°C
TA = 85°C

::>

w

0

0

::>
f-

:J

a..

::E

«
«
z

....J

DATASHEET SPEC
-10

C!)

C75
f-

::>

a..
~

-20

::E
::>
::E

Z

~

-30

0.8

1.0

1.2

1.4

INPUT FREQUENCY f'N(GHz)

2-29

MB501SL
Fig. 5 - POWER SUPPLY CURRENT VS. POWER SUPPLY VOLTAGE

«E
:]

6.0t------t--------+--------t----l

t-

z
w
a:
a:

:::>

u
~

5 . 0 1 - - - - - - t - - - - - - - - + - - - - : : : : .......:;;..--+---~

CL
CL

:::>
(f)

ffi

~

4.0..-----i--------+--------t---.....j

4.5

5.0
POWER SUPPLY VOLTAGE Vee (V)

5.5

Fig. 6 - POWER SUPPLY CURRENT vs. TEMPERATURE

«E

:]

6.0

t-

Z

W

a:
a:
:::>
u

>oJ

5.0

CL
CL

:::>

. .V

(f)

a:
w

~

4.0

~

~

-------

0

CL

-20

-40

o
20
40
TEMPERATURE TA(°C)

60

80

Fig. 7 -INPUT SIGNAL VS. INPUT FREQUENCY

E

co

10
Vee = 5.0V
TA = 25°C

::£.
z

:>
w

0

:::>
t::J

0

CL
~

DATASHEET SPEC

0(

oJ
0(

-10

)

z

"
Ci)

t:::>
CL

~

-20

~

:::>

~

Z

~

-30

......

r--------......~

10

2-30

100
INPUT FREQUENCY (MHz)

.-.-/

V

1000

MB501SL
Fig. 8 -TYPICAL APPLICATION EXAMPLE

OUTPUT

C~ck~-------'----~

-+----'

Data 0 - - - -....

LE~~~T-_+--------~

471<0471<0471<0

XI
Vee
Va.
~

~

.

k

~

L

C,. C:r
____+-______________________________

12.SMHz x'taI
SV± 10%
SV Max.
depends on crystal osillalor

Det.

10kn

2-31

MB501SL

PACKAGE DIMENSIONS
8-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-OSP-M01)

.370~:g~~

.244±.010
(6.20 ± 0.25)

.300(7.62)

TYP

~=;:::::;:::=:::;:::;:=;:y~
.039~J>12

II

(0.99~g30)

.1060~J>12
(152~ g30)

.035~:g~~
(0.89~g~5)
172(436) MAX

020(0 51)
MIN
100(254) .1-

TYP
11:11988 FUJITSU LIMITED 008006S.2C

2-32

118(3 00) MIN

018; 003
(046; 008)
Dimensions in
inches (niRirneters)

MB501SL

PACKAGE DIMENSIONS (Continued)

lEI

8-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-08P-M01)

089(225) MAX
I(SEATED HEIGHT)
, .002(0.05) MIN
(STAND OFF)

11

.268 ~g~~(6.80 ~g~g)

R

L

I

050(~

~ (045 ± 0

TYP

150(381)
REF

...,

lOJ$/ ¢005(O 13)'M/

1.020 ,.00.
(0.50±0.20)

006 +002(0 15 +0.05)
.
-.001'
-0.02

r--------------.,
: Details of "A" part :

:,

~008(0.20);

J

,

-

J

I

J

I

J

020(0.50);

:

i

,

: II .007(0.18)

J

I

:

.

1

J

,
MAX
J
,027(068) :

J
MAX
L
_______________
JJ

Cl988 FUJITSU LIMITED F08002S-3C

Dimensions in
inches (miUimelersJ

2-33

MB501SL

PACKAGE DIMENSIONS (Continued)
8-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT·08P·M02)

2361.016
(600,0.401
154 + 012
(390 + 0 30)

!

1971.012
(500~,030)

!

.'
f

--+i

!

016(040)

'I

!!

-: ;. 01 7 + 004 ; 4;
(0 42 + 0 10) , ~ , cf> 005(0 13) (~,

1-

"A"

.020:i .OOS
(050±020)

---t!-

OOS:! .002
(020:1 005)

Details of "A'· part

016(040)

~i

lW·:-i

, (OOS(O 20)
007(0 lSI

'0

004(0101

, MAX"
026(065)

, MAX'

Dimensions in
11'1988 FUJITSU LIMITED F08OO4S-2C

2-34

inches (rTillimeters)

00
FUJI"SU
~~~n4.0~a~~~~~~~
II
Sept. 1995

~

DATA SHEET

MBS05-16
ULTRA HIGH FREQUENCY PRESCALER

III

ULTRA HIGH FREQUENCY PRESCALER
The Fujitsu MB505 is a high frequency, up to 1.6GHz, prescaler used with a
frequency synthesizer to form a Phase locked loop (Pll). It will divide the input
frequency by the modulus of 128 or 256 and the cutput level is 1.6V peak to peak
on ECl level.
Operation in the 1.6GHz range meets the specification for applications in Direct
Broadcasting Satellite Systems (DBS), CATV systems, and UHF Transceivers.

PLASTIC PACKAGE
DIP-08P-M01

FEATURES
• High Frequency Operation

1.6GHz max.

• low Power Dissipation

45mWtyp.

• Wide Operation Temperature

PLASTIC PACKAGE
FPT-08P-M01

• Stable Output Amplitude

• Complete Pll synthesizer circuit with the Fujitsu MB87006A, Pll
synthesizer IC

PIN ASSIGNMENT
• Plastic 8-pin Standard Dual-In-Line Package or Flat Package

ABSOLUTE MAXIMUM RATINGS (See Note)

IN

Symbol

Value

Unit

Supply Voltage

Vee

-0.5 to +7.0

V

Input Voltage

VIN

-0.5 to Vee

V

10

10

mA

TSTG

-55 to +125

°C

Rating

Vee

sw

Output Current
Storage Temperature
Note:

Permanent device daMage mayoccurifthe above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in
the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

OUT

NC
NC
GND

This device contains circuHry to protect the inputs against
damage due to high static voltages or electric fields. However,
H is advised that normal precautions be taken to avoid
application of any voltage hig,erthanmaximum rated voltages
to this high impedance circun.

2-35

MBSOS-16

Fig. 1 - MB 505 BLOCK DIAGRAM

SW

Divide Ratio

H

1/128

L

1/256

Note: SW: H

= Vee.

L = ope!'

PIN DESCRIPTION

2-36

Pin Number

Symbol

1

IN

2

Vee

Power Supply Voltage

3

SW

Divide Ratio Control Input Selecting divide ratio (See Divide Ratio Table)

4

OUT

Output

5

GND

Ground

6

NC

No Connection

7

NC

No Connection

8

iN

Complementary Input

Function
Input

MBSOS-16

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Symbol

Supply Voltage

Vee

Output Current

10

Ambient Temperature

TA

Load Capacitance

Unit
Min.

Typ.

Max.

4.5

5.0

5.5

1.2
-40

CL

V
mA

+85

°C

12

pF

ELECTRICAL CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted.)
Value
Parameter

Symbol

Conditions

Unit
Min.

Supply Curent

Icc

Output Amplitude

Vo

Input Frequency

fiN

Input Signal Amplitude

Typ.

1.0
with input coupling
capacitor 1000pF

Max.

9

mA

1.6

Vp-p

100

1600

MHz

PIN

-12

5.5

dBm

High Level Input Voltage for SW

VIHS*

Vee-O· 1

Vee +0.1

V

Low Level Input Voltage for SW

VILS

Note:

Vee
Open

V

*Design Guarantee

1
~

I
Vee S.OV
TA 25°C

1000

=
=

w

0

::)

I-

800

:::::i

a..

::!:
c(
....I
c(

600

Z

(!)

(j)
I-

400

::)

a..
~

200

::!:

::)

::!:

Z
~

-

~

V

0
100

SOO 1000 2000
200
INPUT FREQUENCY (MHz)

Figure 2. Input Signal Amplitude VB. Input Frequency

2-37

MB505-16

PACKAGE DIMENSIONS
(Suffix: ·P) (Suffix: ·PF)

I-LEAD PLASTIC DUAL.....UNE PACKAGE
(CASE No.: DlP-IIP-II01)

I140ElICJ

f

2".0.10.

"lO:G.ZSI

__._ t
I

1

L. no.:.::; __ -:
(Uo.~~

.

.LEAD PLASTIC FLAT PACJAGE
(CASE No.: FPT-08P-II01)

i IS'MAX
II
I,

~

.-f

---I
I

i

I

307 •.0."
1.7.8,,0...,
.2011.012

a I~DEX

.5.30;o..ZS.!

J ,

.--l

.-J.-----,~!:;:.ro,

_ " 271!
.
-Ty-'-·----

0."'112

~!.-';;2j

mo orl=r0l51··5IMAX
"~~

...

-

-

.0.3.5 •.001
'0..1.0..21

.'117 FWITSU LIMITED FOIOCI2S·2C

2-38

00
FUJI"SU
=~~n3.0~a~~~~~~~
Sept. 1995

=

11

DATA SHEET

MB506
ULTRA HIGH FREQUENCY PRESCALER
ULTRA HIGH FREQUENCY PRESCALER
The Fujitsu MB506 is a high frequency, up to 2.4GHz, prescaler used with a
frequency synthesizer to form a Phase locked loop (Pll). It will divide the input
frequency by the modulus of 128 or 256 and the output level is 1.6V peak to peak
on ECl level.Operation in the 1.6GHz range meets the specification for
applications in Direct Broadcasting Satellite Systems (DBS), CATV systems, and
UHF Transceivers.

PLASTIC PACKAGE
DIP-08P-M01
FEATURES
• High Frequency Operation

2.4GHzmax.

• Power Dissipation

9OmWtyp.

• Wide Operation Temperature

-40°C to +85°C

• Stable Output Amplitude

VOUT = 1.6Vp-p

PLASTIC PACKAGE
FPT-08P-M01

• Complete Pll synthesizer circuit with the FujitslJ MB87006A, Pll
synthesizer IC

PIN ASSIGNMENT

• Plastic 8-pin Standard Dual-In-Line Package or Flat Package
IN

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

VCC

Value

Unit

Supply Voltage

Vee

-0.5 !0+7.0

V

Input Voltage

VIN

-0.5 to Vee

V

10

10

mA

TSTG

-55 to +125

°C

Output Current
Storage Temperature

Note: Pennanentdevicedamage mayoccurifthe above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in

TN
NC

SW

SW2

OUT

GND

This device contains clrcuHry to protect the inputs against
damage due to high static voltages or electric fields. However,
it is advised that nannal precautions be taken to avoid
application ofanyvo!tagehigherthanmaximum rated voltages
to this high impedance circuit.

Copyright Cl 1995 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS

2-39

MB506

Fig. 1 - MB 506 BLOCK DIAGRAM

Divide Ratio

SW1

SW2

H

H

1/64

L

H

1/128

H

L

1/128

L

L

1/256

Note: H = Vee. L = open

PIN DESCRIPTION
Pin Number

2-40

Symbol

Function

1

IN

Input

2

Vee

Power Supply Voltage

3

SWl

Divide Ratio Control Input Selecting divide ratio (See Divide Ratio Table)

4

OUT

Output

5

GND

Ground

6

SW2

Divide Ratio Control Input Selecting Divide Ratio (See Divide Ratio Table)

7

NC

No Connection

8

IN

Complementary Input

MB506

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Unit

Symbol

Supply Voltage

Vee

Output Current

10

Ambient Temperature

TA

Load Capacitance

CL

Min.

Typ.

Max.

4.5

5.0

5.5

III

rnA

1.2
-40

V

+85

°C

12

pF

ELECTRICAL CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Value
Parameter

Symbol

Supply Curent

Min.

Typ.
18

rnA

1.0

1.S

VH

Icc

Output Amplitude

Vo

Input Frequency

PIN

High Level Input Voltage for SW

100

2200

TA=-40°C
to SO°C

100

2400

tiN = 1OOMHz to 1.3GHz

-16

5.5

tiN = 1.3MHz to 2.4GHz

-4

5.5

MHz

dBm
Vcc-o· 1

VIHS*

Low Level Input Voltage for SW

Max.

TA = -40°C
to 85°C

with input
coupling
capacitor
1000pF

fiN

Input Signal Amplitude

Note:

Unit

Conditions

Vec
Open

VILS

Vee +0.1

V
V

"Design Guarantee

f>

~

w
c
:::>
.....
:::i

1000

Vee'=s.ov
TA= 25°C

800

!l.

600

«
...J
«

400

:::ii:

z

(!)

en

..... 200
:::>
!l.

~

:::ii:
:::>
:::ii:

Z

~

--'

0
100

200
SOO 1000 2000
INPUT FREQUENCY (MHz)

Figure 2. Input Signal Amplitude

liS.

5000

Input Frequency

2-41

MBS06

PACKAGE DIMENSIONS
8-LEAD PLASTIC DUAL·IN·UNE PACKAGE
(CASE No.: DIP-OSP·M01)

8-LEAD PLASTIC FLAT PACJAGE
(CASE No.: FPT-GSP·M01)

t

15 MAX

II

- ~":~:~'"
[J m
00110051

1

301' 016

a

INDEX

I 178'001

2091012

1530(251 1;

__ I

050112])
-TY-P---

C 1987 FUJITSU LIMITED 008006S-2C

2-42

Dimensions in
inches (ITiRllT18Iers)

---t

018-.004
~

C 1987 FUJITSU LIMITED F08OO2S-2C

16 80:g jg)
!

I

020' 008
105'021

~'A"
\.

\ .008,10.21

orfJ

.0201051

00710,181
--'~x-

02710.68)
-~

Dimensions in
inches (1TiIliIT18lers)

00
FUJI"SU
~~~n4.0~a~~~~~~~
I,
Sept. 1995

~

DATA SHEET

MBS07
1.6GHz TWO MODULUS PRESCALER

DI

1.6GHz TWO MODULUS PRESCALER
The Fujitsu MB507 is a 1.6GHz two modulus prescaler used with a frequency
synthesizer to form a Phase locked loop (PlL). It will divide the input frequency
by the modulus of 128/129 or 256/257 and has an output level of 1.6V peak to
peak on ECl level.

FEATURES
• High Frequency Operation

1.6GHz max.

• Power Dissipation

90mWtyp.

PLASTIC PACKAGE
DIP-08P-M01

• Pulse Swallow Function

• Wide Operation Temperature

-40°C to +85°C

• Stable Output Amplitude

VOUT = 1.6Vp-p

PLASTIC PACKAGE
FPT-08P-M01

• Complete Pll synthesizer circuit with the Fujitsu MB87001 A, PLl
synthesizer IC
• Package
Standard 8-pin Dual-In-Line Package (Suffix: -P)
Standard 8-pin Flat Package
(Suffix: -PF)

PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

IN

Value

Unit

Supply Voltage

Vce

-0.5 to +7.0

V

Input Voltage

VIN

-0.5 to Vee

V

10

10

mA

TSTG

-55 to +125

°C

Output Current
Storage Temperature
Note:

Pennanentdevicedamage mayoccurifthe above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in
the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

IN'

VCC

NC

sw

MC

OUT

GND

This device contains circuHry to protect the inputs against
damage due to high static VOllages or electric fields. However,
k is advised that normal precautions be taken to avoid
application ofanyvottage hi~erthanmaximum ratedvottages
to this high impedance circuft.

Copyright © 1995 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS

2-43

MB507

Fig. 1 - MB507 BLOCK DIAGRAM

MB 507

SW

MC

H

H

Divide Ratio
1/128

H

L

1/129

L

H

1/256

L

L

1/257

Note: SW; H '" Vee, L '" open
MC; H '" 2.0 V to Vee, L = GND to 0.8 V

PIN DESCRIPTION
Pin Number

Function

IN

Input

2

Vee

DC Supply Voltage

3

SW

Divide Ratio Control Input Selecting Divide Ratio (See Divide Ratio Table)

4

OUT

Output

5

GND

Ground

6

MC

Modulus Control Input (See Divide Ratio Table)

7

NC

Non Connection

8

iN

Complementary Input

1

2-44

Symbol

MB507

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Unit

Symbol

Supply Voltage

Vee

Output Current

10

Ambient Temperature

TA

Load Capacitance

Cl

Min.

Typ.

Max.

4.5

5.0

5.5

III

mA

1.2
-40

V

+85

°C

12

pF

ELECTRICAL CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted.)
Value
Parameter

Symbol

Unit

Conditions
Min.

Supply Curent

lee

Output Amplitude

Vo

Input Frequency

fiN

Input Signal Amplitude

1.0
with input coupling
capacitor 1000pF

Max.

18

mA

1.6

Vp-p

100

1600

MHz

10

dBm

P,N

-4

High Level Input Voltage for MC
Input

V,HM

2.0

Low Level Input Voltage for MC
Input

V,lM

High Level Input Voltage for SW
Input

V'HS*

Low Level Input Voltage for SW
Input

V,lS

High Level Input Current for MC
Input

I'HM

V,H =2.0V

Low Level Input Current for MC
Input

l'lM

V'l=0.8V

Modulus Set-up Time MC to OUT

tSET

1.6GHz Operation

Note:

Typ.

V
V

Vee -0.1

Vee

Vee +0.1

V
V

Open
0.4

mA
mA

-0.2
18

28

ns

*Design Guarantee

2-45

MB507

Fig. 2 - TEST CIRCUIT

,...--__<>-------__- - - - - - - 0

vee = + 5.0 V ± 10%

Sampling scope input point
for input waveform

I
P.G.

Sampling scope prober point
for output waveform

Vee

OUT~-~~--.----~

IN

L-_ _---l'-'

MC GND

MC input
C, : 1000pF
C2 : 1000pF
C3: 0.1J.lF
C L : 12pF (including scope and jig capacitance)
R L : 2K!1

TIMING CHART (2 MODULUS)
Example: Divide ratio = 128/129
129

128

IN

I1Jl . ·Jl]Ul----nn

J

64

'--__6_4_---..,...,.Jf - -- - -- -

l\-·._64_...-J

65

L

OUT

MC------------------------------~

.----

: IsET :

Note: When divide of 129 is selected, positive pulse is applied by one to 65.
The typical set up time is 18 ns from the MC signal input to the timing of change of prescaler divide ratio.

2-46~------------------------------------------------------------~

MB507

Fig. 3 - INPUT SIGNAL AMPLITUDE vs. INPUT FREQUENCY
Q.

tl.

>

Vee = 5.0V
700 I-TA '" 25°C

.s
w

600

0

::J

I~

500

Q.

~

«
...J
«
z

400

(!l

ii.i 300
I-

::J

Q.

~
~

::J

200

100

~

i

-

~ "'--

z

10

20

~

50

100

200

500 1000 2000

INPUT FREQUENCY. (MHz)

Fig. 4 - TYPICAL APPLICATION EXAMPLE
VSX (Max. 8 VI
10Kn
12Kn

OUTPUT
MB 87001A
0. D47.uF

~

12Kn

Vee
10Kn

Da~~----~~----~

Clock.o----.--+-----l
LEO-~-+-~--------~

LOCkt=-_-

XI
: 12.8MHzX'tal
Vee : 5 V! 10%
Vsx : 8 V Max.
C" C2: depends on crystal oscillator

Det.

10Kn

2-47

MB507

PACKAGE DIMENSIONS
(Suffix: P)
8-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-08P-M01)

INDEX
.244±010
(6.20±0.25)

300(7.62)

TYP

1l;:::::;:::;:=;::::;:=::;:::;::::;:Y~
039~0012

II

012

I1 060+-0

(099~g30)

.035~:g~~
(0.89 ~ g:~g)
.172(4.36) MAX

118(3.00) MIN

.100(2.54)

TYP
C 1988 FUJITSU LIMITED 008006S.2C

2-48

.018±.003
(046±008)
Dimensions in
inches (milimeten;)

MB507

PACKAGE DIMENSIONS (Continued)

III

(Suffix: PF)
8-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-08P-M01)

(635

.089(2.25) MAX
/(SEATED HEIGHT)
.002(005) MIN
(STAND OFF)

~g~g)-l

-,

+-----,
i

'

~~~~-1

.050(1.27)

268

R

iI

J-.

,.018 + .004
- (0.45 + 0.1

oJ$1 16.005(0 13»",,1

TYP

_150(3. 81
REF

l..

~g6~(6.80 ~

gjg)

I
~ (0.50±0.20)
020±.008

.006 + .002(0_ 15 + 0.05)
-.001
-0.02

r--------------,
: Details of "A" part :

"A"

:

,/-'.;

~
,

;

Cl .. QQ4(0.1.0)

~008(0.20):

,
I

I
I

,

I

:

I
.020(0.50);
11007(0.18) :

I

\.

41 11188 FUJITSU LIMITED F08OO2S-3C

I
I

!307±016
1(780 ± 0.40)
.209±.01·2
(530±030)

INDEX

:

I

MAX

:.027(068)

I

,

I

MAX

L _______________ J

Dimensions in
inches (mHiimelers)

2-49

2-50

cO
FUJI"SU
=~~n3.~~~~~~~~
II
Sept. 1995

=

DATA SHEET

MB50B
2.3GHz TWO MODULUS PRESCALER
2.3GHz TWO MODULUS PRESCALER
The Fujitsu M8508 is a 2.3GHz two modulus prescaler used with a frequency
synthesizer to form a Phase locked loop (Pll) and divides the input frequency
by a modulus of 128/130, 256/258 or 512/514. The output level is 1.6V peak to
peak ECl level. The ultra high frequency operation provides wide application,
such as Direct Broadcasting Satellite System, CATV system, UHF Transceiver,
etc.

FEATURES
• High Frequency Operation:

f =2.3GHz max. (PIN =-4dBm min.)

• Input Signal Amplitude:

VIN

• Pulse Swallow Function:

128/130,256/258,5121514

• Power Dissipation:

120r..Wtyp.

• Wide Operation Temperature:

-40°C to +85°C

• Stable Output Amplitude:

VOUT =1.6Vp-p typo

PLASTIC PACKAGE
DIP-08P-M01

=100mVp-p (fiN =100MHz to 1.8GHz)

PLASTIC PACKAGE
FPT-08P-M01

• Complete Pll synthesizer circuit with the Fujitsu MB87001 A, Pll
synthesizer system block IC

PIN ASSIGNMENT

• Standard Plastic B-pin Dual-In-Line Package or Flat Package
IN

ABSOLUTE MAXIMUM RATINGS (See Note)
Symbol

Value

Unit

Power Supply Voltage

Rating

Vee

-0.5 to +7.0

V

Input Voltage

VIN

-0.5 to Vce

V

Output Current

10

10

mA

Operating Temperature

TA

-40 to +85

°C

TSTG

-55 to +125

°C

VCC

SW1

Storage Temperature

Note: Pennanentdevicedamage mayoccuriftheaboveAbsolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in
the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

OUT

This device contains circuHry to protect the inputs against
damage due to high static vohages or electric fields. However,
H is advised that normal precautions be taken to avoid
application of anyvoltagehigherthanmaximumratedvoltages
to this high impedance circuH.

Copyright e> 1995 by FUJITSU LIMITED and PJJITSU MICROELECTRONICS

2-51

MBS08

Fig. 1 - MB508 BLOCK DIAGRAM

V:::=;~}-----l
iNc

IN

C Q

p..-t---o OUT

MC
SW1

SW2

MC

Divide Ratio

H

H

H

1/128

H

H

l

1/130

H

l

H

1/256

l

H

H

1/256

H

l

l

1/258

l

H

l

1/258

l

L

H

1/512

l

l

l

1/514

Note: SW: H=Vee, l=Open
MC: H=2.0V to Vee, l=GND to O.SV

PIN DESCRIPTION
Pin Number

2-52

Symbol

1

IN

2

Vee

Descriptions
Input
Power Supply. +5V

3

SWl

Divide Ratio Control Input (See Divide Ratio Table)

4

OUT

Output

5

GND

Ground

6

MC

7

SW2

8

iN

Modulus Control Input (See Divide Ratio Table)
Divide Ratio Control Input (See Divide Ratio Table)
Complementary Input

MBSOS

RECOMMENDED OPERATING CONDITIONS
Values
Parameter

Symbol

Power Supply Voltage

Vee

Output Current

10

Operating Temperature

TA

Load CapaCitance

CL

Unit
Min.

Typ.

Max.

4.5

5.0

5.5

1.2
-40

V
rnA

+85

°C

12

pF

ELECTRICAL CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted.)
Values
Parameter

Symbol

Condition

Unit
Min.

Power Supply Current

lee

Output Amplitude

Vo

Input Frequency

1.0

Typ.

Max.

24

rnA

1.6

Vp-p

fiN

with input coupling
capacitor 1000pF

100

2300

PINA

fiN = 1800MHz to
2300MHz

-4

5.5

PINS

fiN = 1OOMHz to
1800MHz

-16

10

Input Signal Amplitude

dBm

High Level Input Voltage for MC

VIHM

Low Level Input Voltage for MC

VILM

High Level Input Voltage for SW

VIHS *

Low Level Input Voltage for SW

VILS

High Level Input Current for MC

2.0

V
0.8

Vec-O· 1

Vee

Vce +0.1

Open

IIHM

VIH =2.0V

Low Level Input Current for MC

IILM

VIL=0.8V

High Level Input Current for SW

IIHS

VIH = Vee

Modulus Set-up Time MC to
Output at 2.3GHz Operation

!sET

Note:

MHz

V
V
V

0.4
-0.2

rnA
rnA

18

250

J.IA

28

ns

*Design Guarantee

2-53

MBSOS

Fig. 2 - TEST CIRCUIT

P.G.

5

I

Ul

Vee

~C3

Sampling scope input point
for input waveform
C1

Vee

I

IN

50n

Sampling scope prober point
for output waveform

SW1 SW2

OUT

iN
C2

= +S.OV±10%

RL
MC

GND

MC input

C1 : 1000pF
C2: 1000pF
C3: 0.1~F

CL : 12pF (Including scope and jig capacitance)
CR: 2kS1

TIMING CHART (2 MODULUS)
Example: Divide ratio = 128/130
130

128

IN

flIl---JlflJl---M
J

64

1--

'---__6_4____

-M--JUlI1nM
-l\-',

_64_-,,1

66

_L

OUT

MC--------------------------------~

.-"--

tsET :

Note: When divide ratio of 130 is selected. positive pulse is applied by two to 66,
The typical set up time is 18 ns from the MC signal input to the timing of change of prescaler divide ratio,

2-54

MBSOS

Fig. 3 - INPUT SIGNAL AMPLITUDE vs. INPUT FREQUENCY
I

~

700

.s>

600

Ii.

= S.OV
= 25°C

Vee

TA

I

OJ

I

'0

.~

Ci.
E

500

co

400

i

<{

§,

en

:;

300

Q.

.:

E
~
E

200

~

100

'c

~ I'--.
10

20

_./
50

100 200

500 1000 2300 5000

Input Frequency (MHz).

Fig. 4 - TYPICAL APPLICATION EXAMPLE
Vsx (Max. 8 V)
10Kn
12Kn

OUTPUT
MB 87001 A

12Kn

10KH

Clock O - - - - - - - - < p - - - - - '

Data

LE
!

MBSOS

LOCk
Det.

t

,--,---

~:c ;~8,~~~ X",
Vsx

BV Max.

I

I
i

C,. C2: depends on crystal oscillaj

10K!}

2-55

MB508

PACKAGE DIMENSIONS
(Suffix: ·P)
a·LEAD PLASTIC DUAL IN·LlNE PACKAGE
(CASE No.: DIP·08p·M01)
370+ .016
-.012

INDEX
.244± .010
(6.20 ± 0.25)

.300(7.62)

TYP

~:::::;::::::::;:;:::;::::;:y~
.039::6'12

II

(0.99::8'30)

I

1·060~6'12
(0.25 ± 0.05)

(1.52::g· 30)

.035:::g~~
172(4.36) MAX

.118(3.00) MIN

.100(2.54)

TYP
C 1988 FUJITSU LIMITED D08OO6-2C

2·56

.018±.003
(046±008)
Dimensions in
inches (mUlimet8r&)

MBSOS

PACKAGE DIMENSIONS (Continued)
(Suffix: -PF)
8-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-08P-M01)
089(2.25) MAX
,(SEATED HEIGHT)

002(005) MIN
(STAND OFF)

l

i .307±.016

j(7.80±OAO)
.209±.Q1'2
/5.30±0.30)

INDEX

cf

.268 ~g6~(6.80 ~ g~g)

1o!::::;t;::::;:i;:=n=~ __ .L
..
_.1

I!

050(1.27)

1 i.

R I.

020 ±.OO8
(0.50±0.20)

l.oo~ ~

0 18 ± .004 r-:-1--::-:=-=-"-=-,,,,",

--I (0~45 ±0.lot$I¢·005/0.13)iMlI

TYP

, .150/3.81)
~-·-REF-~

"A"
,-

... ,

~gg~)

: Details of "A" part :

:,

~008(0.20);

I
I

I
' I

I

I

:
:
:
I
I
L

CD 1988 FUJITSU LIMITED F08OO2S-3C

:ggfrO.15

r--------------.,
I

II .020(0.50):
: ~i007(0.18):
:
i
MAX
:
.
[.027(0.68) I
MAX
_______________
JI

Dimensions in
inches (millimeters)

2-57

2-58

OJ

Sept. 1995

FUJITSU

Edition 3.0a
DATA SHEET

MB509
TWO MODULUS PRESCALER WITH STAND-BY MODE
TWO MODULUS PRESCALER WITH STAND-BY MODE
The Fujitsu MBS09 is a low power, two modulus prescaler equipped with the
standby mode. The MBS09 is used in conjunction with a frequency synthesizer
to form a Phase Locked Loop (PLL) and will divide the input frequency by the
modulus of 65/65 or 128/129.
Power consumption is typically 11.5mA at S.OV. under normal operation, with the
current reduced t0180~ in standby mode. By using MBS09 with the MB87076,
intermittent operating mode can be achieved.

PLASTIC PACKAGE
DIP-08P-M01

FEATURES
• High Frequency Operation:

fmax ::.: '1.1 GHz max. (PIN = -4dBm min.)

• Pulse Swallow Function:

64/65, 128/129

• Power Supply Consumption:

58mWtyp.

• Stand-by Current:

180J.L~

• Stable Output Amplitude:

Vo = 1.6Vp-p typo

typo

PLASTIC PACKAGE
FPT-08P-M01

• Complete PLL synthesizer circuit with the Fujitsu MB87076, PLL frequency
synthesizer IC
• Plastic 8-pin Dual-tn-Une Package (Suffix: -P)
Plastic 8-pin Mini Flat Package (Suffix: -PF)

PIN ASSIGNMENT

• Built-in a Termination Resistor
Stable output amplitude is obtained up to output load capacitance of 8pF

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating
Power Supply Voltage
Input Voltage
Output Current
Storage Temp,}rature
Note:

IN

Symbol

Value

Unit

Vee

-{).5 to +7.0

V

VIN

V

-0.5 to Vee

10

10

TSTG

-55 to +125

I

Vec

PS

SW

Me

OUT

GND

rnA

°C

Permanentdevicedarnage mayoccurifthe above Absolute Maxlm:Jm Ratings are
exceeded. Functional operation shou:d be restricted to the conditions as detailed in
the operational seL,1lons c.1 this data 6heet. Exposure to absolute maximum rating
conditions tor e>.1ended periods may affect device reliability.

I________________________

~

This device contains circuHry to protect the inputs against
• damage dUel to high static voltages or electric fields. However.
it is advised that normal precautions be taken to avoid
application of anyvoRage higherthanmaxlmum rated voltages
to this high impedance circuit.

Copyright © 1990 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS. INC.

2-59

MB509
Fig. 1 - MB509 BLOCK DIAGRAM

PS

OUT

PS

SW

Me

Divide Ratio

H

H

H

1/64

H

H

L

1/65

H

L

H

11128

H

L

L

L

Note:

SW: H=Vee • Laopen
MC: Ho:3.0V to Vee.
L-GND to O.SV
PS: HR2.0V to Vee.
L..GND to O.4V

1/129
Stand-by mode

PIN DESCRIPTION

2-60

Pin Number

Symbol

Description

1

IN

2

Vee

Power Supply, +5V

3

SW

Divide Ratio Control Input (See Divide Ratio Table)

4

OUT

Output

5

GND

Ground

6

MC

Modulus Control Input (See Divide Ratio Table)

7

PS

Stand-by Control Input (See Divide Ratio Table)

S

TN

Complementary Input

Input

MB509

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Symbol

Power Supply Voltage

Unit
Min.

Typ.

Max.

Vee

4.5

5.0

5.5

Operating Temperature

TA

-40

-

+85

°C

Load Capacitance

CL

-

-

8

pF

V

ELECTRICAL CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Value
Parameter

Symbol

Unit

Condition
Min.

Power Supply Curent

Icc

Typ.

Max.

-

11.6

-

rnA

-

~

-

Vp-p

Ips

Stand-by mode

-

180

Output Amplitude

Vo

Built-in a Termination
Resistor.
Load Capacitance=8pF

1.0

1.6

Input Frequency

fiN

With input coupling
capacitor 1000pF

10

-

1100

MHz

Input Signal Amplitude

PIN

-

-4

-

5.5

dBm

3.0

-

-

V

0.8

V

Vee +0.1

V

High Level Input Voltage for MC

VIH

Low Level Input Voltage for MC

VIL

High Level Input Voltage for SW

VIHS*

Low Level Input Voltage for SW

VILS

High Level Input Voltage for PS
Low Level Input Voltage for PS

Vee-O· 1

Open

VIH

2.0

-

-

VIL

-

-

0.4

V

0.4

rnA

-

rnA

16

26

ns

IIH

V1H =3.0V

-

Low Level Input Current for MC

IlL

VIL= 0.8V

-0.2

Note:

V

-

High Level Input Current for MC

Modulus Set-up lime MC to Output

Vee

tSET

-

-

V

*Design Guarantee

2-61

MB509

Fig. 2 - TEST CIRCUIT

....--.....-------.a-------o

Vcc=+5.0V±10%

Sampling scope input point
for input waveform

/

Vee

C,

P.G·£-_ _ _w

IN

Sampling scope prober point
for output waveform

SW

OUT~-------~----~

MC

GND

C,: 1000pF
C2 : 1000pF
C3 : O.1j.1F
CL : 8pF (including scope and jig capacitance)

PS pin is open.

TWO MODULUS OPERATING TIMING CHART (64/65 DIVIDE RATIO)

64

IN

r

65

~--------~,--------

r --------~---------"'"

"'"

M--:flJill--rul------M--nJlM--rul
I

,

I

f

I

I

I

I

J

I

32

I

,

,,

,,~---3-2--~,~r---------1~,----3-2----,~,
,

OUT

,

,

L

33

,,

MC

Notes: When divide ratio of 65 is selected. positive pulse is added by one
to 33.
The typical set up time is 16ns from the MC signal input to the
timing of change of prescaler divide ratio.

2-62

~
tSET

I

MBS09

TYPICAL CHARACTERISTICS CURVES
Fig. 3 - INPUT SIGNAL AMPLITUDE VS. INPUT FREQUENCY

III

Vcc=5.0V

10

E

CD
~

~

Oatasheet spec.

0

w

Q

::::>
~

:::;
Cl.

::::E

<:
....J
<:

z

Q
C/)
~

::::>

Cl.

~
::::E
::::>
::::E

Z
~

-30
1.2

1.0

1.6

1.4

INPUT FREQUENCY fIN (GHz)

Fig. 4 - WAVEFORM OF STAND BY MODE
« Power Off ~

«PowerOn~

PS pin Input
Signal

,;

OUT pin
Output signal
(Prescaler
output)

C5

III 11 If\~

:> r \, \I~
,

1\

~ I , I~ I~ I~ I, I , I

.

.

\ \l \1 1\1. \I. 1\1. \I. \1
~

50ns/Oiv.
Note:

About 50 ns of set up time is required both power on/off.

2-63

MB509

Fig. 5 - TYPICAL APPLICATION EXAMPLE

Microcomputer
PS Signal
LE Data Clock

16

15

14

13

12

11

10

9

MB87076

2

3

4

Voo

._------------------ ..
I

Prescaler
MB509
OUTPUT

2-64

MB509

PACKAGE DIMENSIONS

•

8-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DIP-8P-MOI)

INDEX
244± .010
(6.20±0.25)

300(7.62)
TYP

1J;:::r:::r:=;:::;:=~~
.039~J>12

II

(099~g30)

1060~J>12
(1.52 ~g.30)

035~:gl~
.172(4.36) MAX

.118(3.00) MIN

100(2.54)
TYP

© 1988 FUJITSU LIMITED D08006S-2C

.018±.003
(0.46 ± 0.08)
Dimensions in
inches (millimeters)

2-65

MB509

PACKAGE DIMENSIONS continued)
a-LEAD PLASTIC FLAT PACKAGE
(Case No. : FPT-8P-MOI)
089(2.251 MAX
(SEATED HEIGHTI
002(0.051 MIN

~~==;;tl
·307±.016
INDEX
(7.80 ± 0.401
1
'209±012
(5.30±0.301

cj

\C::;tr:::rtr=:;::;:~_J.

!

268 ~g6g(680 ~8:~gl

H

1.

050(127)
TYP

i .150(3.81)
1--.----- ~
REF

1 020 ,.008

(050±0.201

.006 + .002(0.15 +0.05 1
-.001
-0.02

r--- -- ------- --,
: Details of "A" part :

"A"

I

.020(0.501:
.007(0.18) :
I
!
MAX
:
I
I
,.027(0.681 I
IL ______________
MAX
.JI

©1988 FUJITSU LIMITED F08002S-3C

2-66

Dimensions in
inches (millimetersl

OJ
FUJI"SU
=~~a®~~~~~~~
.,
Sept. 1995

=

DATA SHEET

MB510
2.7GHz TWO MODULUS PRESCALER
--------------------------------------------------------------------2.7GHz TWO MODULUS PRESCALER

III

The Fujitsu MB510 is an ultra high speed, two modulus prescaler that forms a
Phase Locked Loop (PLL) when combined with a frequency synthesizer such as
the Fujitsu MB87001A. It divides the inputfrequencybythe modulus of 128/144
or 256/272, and operates at a low power supply current of 10mA at 5.0V.
Through the use of Fujitsu's Advanced Process Technology, the MB51 0 achieves
extremely small stray capacitance from its internal elements.

FEATURES
• High Frequency Operation:

2.7GHz max.

• Power Dissipation:

50mW typo

• Pulse Swallow Function:

128/144, 256/272

• Wide Operation Temperature:

-40°C to +85°C

• Stable Output Amplitude:

VOUT =1.6Vp-p typo

PLASTIC PACKAGE
FPT·08P·M01

• Built-in Termination Resistor
• Complete PLL synthesizer circuit with the Fujitsu MB87001 A PLL
synthesizer IC
• Pac:

t

800

w

600

0

I

~I

Vee=5.0V _
TA = 25°C

::>

I-

:J

a. 500
~

«
«
z

..J

400

(!)

Ci3 300

I-

::>

a. 200
~

~

::>
~

Z

~

I

100

~ 1'--.
10

20

-"

V

50 100 200
500 1000 2000
INPUT FREQUENCY (MHz)

Figure 3. Input Signal Amplitude vs. Input Frequency

2-70

MB510
TIMING CHART (2 MODULUS)
Example: Divide ratio

=1281144

128
IN

III

144

M- --JUUl- --M ----M- --MM- -Jill

J

64

~_64_.."......r

--------l\--_64_~

80

L

OUT

MC--------------------------------~

~

,

~

tSET'

,

tSET'

Note: When divide of 144 is selected, positive pulse is applied by 16 to 80.
The typical set up time is 16 ns from the MC signal input to the timing of change of prescaler divide ratio.

Vsx (Max. 8V)

101<0
121<0

16 15 1413 12 11 10 9
MB87001A

OUTPUT
121<0

101<0

Clock u-------- (CL S 5pF)

• Wide temperature range:

PIN ASSIGNMENT

• Plastic 8-pin Dual-In-Une package (Suffix: -P)
Plastic 8-pin Flat package (Suffix: -PF)
IN

1

Vce

2

0

8

TN

7

81

ABSOLUTE MAXIMUM RATINGS (See Note)
Symbol

Value

Unit

Power Supply Voltage

Vee

-0.5 to +7.0

V

Input Voltage

VIN

-0.5 to Vee +0.5

V

10

10

mA

TSTG

-55 to +125

°C

Rating

Output Current
Storage Temperature
Note:

Permanent device damage mayoccurifthe above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in
the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

TOP VIEW
NC

3

6

82

OUT

4

5

GND

This device contains circuHry to protect the inpu1s against
damage due to high static voltages or electric fields. However,
H is advised that normal precautions be taken to avoid
application of anyvoHage higherthan maximum ratedvollages
to this high impedance circuft.

Copyright © 1995 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS, INC.

2-73

MB511

OUT

S1

Divide
Ratio
Controller
S2

Figure 1. MB511 Block Diagram

FUNCTION TABLE
Operating Frequency

S1

S2

Divide Ratio

L

L

Not used

-

L

H

1

250M Hz

H

L

2

500MHz

H

8

1000MHz

H

H=Vee
L=OPEN

PIN DESCRIPTIONS

2-74

Pin Number

Symbol

110

1

IN

I

Input. The connection with VCO should be an AC connection.

Descriptions

2

Vee
NC

-

Power supply voltage input.

3
4

OUT

0

Output. Termination resistor is necessary due to emitter follower output.

No connection.

5

GND

-

Ground.

6

52

I

Divide ratio control input.

7

51

I

Divide ratio control input.

8

rn

I

Complementary Input.

MB511

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Symbol

Note

Unit
Min.

Typ.

Max.

5.0

5.5

Power Supply Voltage

Vee

4.5

Operating Temperature

TA

-40

Load Capacitance

CL

V

+85

°C

5

pF

III

Termination resistor 500n

ELECTRICAL CHARACTERISTICS
Value
Parameter

Symbol

Unit
Min.

Typ.

Max.

Note

Power Supply Current

lee

15

23

32

rnA

Except termination
output current.

Output Amplitude

Vo

0.4

0.8

1.2

Vp-p

500n termination,
CL= 5pF max.

1/1

'1

50

250

MHz

1/2

'2

50

500

MHz

1/8

f3

50

1000

MHz

PIN

-20

+10

dBm

VIH

Vee~·7

Vee +0.5

V

Input Frequency

Input Signal Amplitude
High Level Input Voltage

Vee

Min. value is measured
with coupling capacitor of
1000pF.
50n

S1, S2
Low Level Input Voltage
Low Level Input Current

S1,S2

IIH

V

OPEN

VIL
40

160

~A

Vee=5V

2-75

MB511

Vee

Sampling scope prober point
for output waveform

Vee

p.G.~~F

IN

500

1

J

MB511

5pF

(including scope and jig capacitance)

.-----IlN
GND

l'OOOpF

Figure 2. Test Circuit

2-76

=+5.0V ± 10%

MB511

TYPICAL CHARACTERISTICS CURVES

-I

-I

~E
(!Jill

~E°H--r----II-+­

OH--r----II-+-

(!Jill

Ci)~

Ci)~

~ ~ -10 t-+--t----1H-

~ cE-10 t-+--t----1H-

a..w

~~

~o

~

E_?rlH---"'I~-+--1f­

E

~ _?rlH---",,"-+--1f~~
z::!:

::!:~
z::!:

~ 

~;c
26.0
:...JE

~~ -10
a.. w
~O
::!:=>
=>I::: -20
::!:-I
_a..
Z::!:
~0
enII:

w

24.0

~

~-

3:

a..

I

22.0
4.5
INPUT FREQUENCY fin (MHz)

Figure 5. Input Sensitivity Curve (111 Divide Ratio)
Power Supply Voltage Dependency

V

<= Typ (23.0mA)

0

-30

~

5.0

5.5

POWER SUPPLY VOLTAGE Vee (V)

Figure 6. Power Supply Current
vs. Power Supply Voltage

2-77

MB511

TYPICAL CHARACTERISTICS CURVES (Continued)

INPUT FREQU::NCY fin (MHz)

INPUT FREQUENCY fin (MHz)

Figure 7. Input Sensitivity Curve (1/8 Divide Ratio)
Temperature Dependency

vcc =5.0V tl!1~!i:~'!!

-Hff-+1f-tt+--+--HH

iii:!H
i

Operaling
Area
5010
1000MHz
-2010
+SdBm

Figure 6. Input Sensitivity Curve (1/2 Divide Ratio)
Temperature Dependency

!zw

28.0

a:
a:

:::>

~;( 26.0

--- ~~

its
~8

CI)-

a:

~

10

1000
INPUT FREQUENCY fin (MHz)

Figure 9. Input Sensitivity Curve (1/1 Divide Ratio)
Temperature Dependency

2-78

24.0

Vcc=5.bv
I

---.........

'"

,

<= Typ (23.0mA)

'1

22.0
-40

0
40
TEMPERATURE TA (OC)

Figure 10. Power Supply Current
vs. Temperatule

80

MB511

III

PACKAGE DIMENSIONS
8-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DIP-8P-MOI)

INDEX

.244±010
(620±025)

300(762)

TYP

1J;::::;::::;::::::::;::::;:=:::r:;::::?I~
039~J>12 I I
(0.99~g30)

I·060~0012
(0.25±0.05)

(1.52~g30)

035~g1~

.172(436) MAX

.118(300) MIN

.100(2.54)

.018±.003

TYP

(0 46±0.08)

© 1988 FUJITSU LIMITED D08006S-2C

Dimensions in
inches (millimeters)

2-79

MB511

PACKAGE DIMENSIONS (continued)
8- LEAD PLASTIC FLAT PACKAGE
(Case No. : FPT -8P-MO I)
089(2.25) MAX
(6.35 +0.25)
-0.20

I

(SEATED HEIGHT)

Iff

~

-,

.002(0.05) MIN

I

: 307t.016
!(780t040)
.209:+:.012
(5.30±0.30)

INDEX

cf

268 ~

0,"

86~(680 ~

r==i1.

8:i8)'

020UO

,

(0.50±020)

050(127)1

JL006 +002(015 +0.05)
-001
-0.02

TYP

_15~~F81L
"A"

6:ncl2o~

,-

--- -- --- - -- -

- -,

Details of ''A'' part :

,

~008(020);

d

:

,

Ii .020(050):
: li007(0 18) :
,
MAX
'

,

i

0~~x68):

!... _____ __________ J

© 1988 FUJITSU LIMITED F08002S-3C

2-80

Dimensions In
Inches (millimeters)

~

DS04-21600-3E

~~~~~~~~~~~£T~~F~IBU
MB551 ASSP for DTS BIPOLAR
Prescaler with VCO (Dual-Modulus, 1.0 GHz)

fJI

• DESCRIPTION
The MBSS1 is a dual-modulus prescaler incoporating a voltage controlled oscillator (VeO) and is used with
SOO-MHz band frequency synthesizers. The MBSS1 consists of: a Colpitts oscillator with grounded base capacitor, a buffer amplifier with open collector output, a prescaler interface circuit, and a dual-modulus prescaler
operating at frequencies divided by 128/12S. The oscillator block accommodates external components such
as a capacitor, a dielectric oscillator (resonator), and a variable capacitor. These components combined with
the circuitry on the MBSS1 chip makes up the veo.
The veo and the prescaler are connected by an internal circuit. This minimizes the effects of prescaler input
load variation on critical veo characteristics, such as c/N ratio.
The MBSS1 typically operates at

5V

and draws

16

mA of current.

• FEATURES
• Oscillator frequency: 1 GHz (Max)
• Low power consumption: Icc = 16 mA (Typical)
• Oscillator output power: 0 dBm (Typical)
• C/N ratio: 70 dB (Typical) Measurement conditions: L\f = 50 kHz, BW = 15 kHz
65 dB (Typical) Measurement conditions: 6f = 25 kHz, BW = 15 kHz
• SIN ratio: 45 dB (Typical) Measurement conditions: BW = 0.3 to 3 kHz, 3 kHz.Dev, 1 kHz Tone
• Stable oscillator output
Supply voltage dependence: ±200 kHzIV (Typical)
Frequency stability: 35 ppm/°C (Typical)
(Continued)

• PACKAGE
8 pin Plastic SOP

(FPT-8P-M01 )

Copyright@ 1995 by FUJITSU LIMITED

2-81

MB551
(Continued)
• Pulse swallow method: Division-by-128/129 prescaler
• Prescaler output with termination circuit: V I = 1.6 VP·p

• PIN ASSIGNMENT

(Top view)
8

fveo

7

2

Vee

3

M

6

5

4

OUT

GND
E

C
B

(FPT·8P·M01)

Pin No.

Symbol

Function

1

fveo

veo signal pin

2

Vee

I Power supply pin

3

M

I Module setting pin

4

OUT

r

Prescaler output pin

5

B

Oscillator transistor base pin

6

e

Oscillator transistor collector pin

7

E

Oscillator transistor emitter pin

8

I

GND

! Ground pin

• TIMING DIAGRAM (Example of Dual-modulus, division-by-128/129 type)
129 cycles

128 cycles

IN

Jill····JlJlll····JlJl········ I1J1-···JlJ1J1J1-····I1J1
j

64 cycles

64 cycles

r"."' ... "" 1

64 cycles

65 cycles

L

OUT

M

'.----ISET

:

:

ISET

I

L_ ...___._. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

2-82

• M pin = High: Division by 128
M pin = Low: Division by 129
(VIH = 2.0 V min, VIL = 0.8 V max.)
• Division plus one makes the high-to-Iow transition longer by one cycle of the frequency-divided signal.
• Setup time (tSET) from input of the M signal to change in the divide ratio of the prescaler is 16 ns (typical).

MB551
• BLOCK DIAGRAM
VCObiock

--.-------------1>---

Vee

C

1

Bias circuit

250P

Prescaler block

ref
I

-33p

I

~
XQ

F4

C Q

~

_______________________________________________________________ 2-83

MB551
• MAXIMUM RATINGS
Parameter

Symbol

Supply voltage

Vee
I
I

Oscillator transistor basel
emitter applied voltage

Ve, VE

M/OUT (Pin 3/4) applied
voltage

VP1

Rating

Unit

-0.5 to +7.0

V

-

-

-0.5 to Vee + 0.5

V

Vee $ VP2 < +7.0

V

±10

mA

-55 to +125

°C

I

Remarks
Do not apply external
DC voltage to the base
or emitter pin.

i

I
i
I

fveo/C (Pin 1/6) applied

VP2

voltage

!

Ip

Applied current
Storage temperature

i

!

Tstg

• RECOMMENDED OPERATING CONDITIONS
Parameter
Supply voltage
External variable capacitor
control voltage
Operating temperature
Prescaler output load

2-84

I

i

Symbol

Value

Unit

i

Min.

Typ.

Max.

I Vee

4.5

5.0

5.5

V

VT

1.5

-

4.5

V

I Ta

-40

-

+85

°C

8

pF

I
!

CL

-

I

Remarks

MB551

----------------------------

• ELECTRICAL CHARACTERISTICS
1.

veo Block
I

Parameter

i

Oscillator frequency
Oscillator output

I

i
fosc

i

Pout

I

i

C/N ratio

Value

I

Symbol
,

Min.

I

-

i

-

i

I

I
!

Max.
1000

MHz

-

dBm

I

70

-

C/N

i

0
[

i
i

-

I

dB

i

-

65

SIN

I

I

-

-

45

Fundamentall1 st harmonic
ratio
Frequency stability

I
I

-

SP-1

i

6ft

Supply voltage variation

6fr

Mod Sense

6fosc

i

I

iI

-

I

I

-10

:

15 kHz

dB

Of = 25 kHz, BW =
15 kHz

dB

I
i BW =0.3 to 3 kHz,
13kHz, Oev, Tone
i 1 kHz
I

-

dB
I

!

-

35

I

-

I

10C ; -40 to 85°C, 25°C
! (Typical)
ppm

I

I

-

±200

I

kHz/V
MHzlV

-

4

i

!

! Of = 50 kHz, BW =
i

I
I

I

i

II
I

I

SIN ratio

Remarks

Unit

Typ.

I

1

5V ±100/0

I
I

Control range: 1.0 to
4.0V

Note: Electrical characteristics depend on external components and mounting conditions. These values are
reference values assuming the test circuit examples on pages 6 and 7.

2. Prescaler Block
Parameter
Supply current

Value
Symbol
Icc

Unit

Min.

Typ.

Max.

-

16.0

-

Output amplitude

VOUT

1.0

Response frequency

fin

-

Allowable input power

Pin

-4

High-level input voltage
(MC)

VIH

2.0

VIL

High-level input current
(MC)

IIH

-

IiL

-0.2

Module setup time

tSET

-

1.6

mA

-

-

Vp-p
-

--c------

Remarks

-------+-

Load capacitance
when internal
termination pin is used:
8 pF or less

-

1000

MHz

-

+10

dBm

-

-

V

0.8

V

-

0.4

mA

-

mA

16

26

ns

------

2-85

MB551
• TEST CIRCUIT EXAMPLE 1

2pF

82 nH

1~MH'IT1 pF

2pF

GND
8

2-86

B

C

6

1

20PF

5

MB551

2

Chip capacitor:
Chip coil:
Dielectric oscillator:
Varicap:

3pF

E
7

3900

20pF
OUTPUTcH
(500)

VT

fvco

3

Vee

IM

4

l_OM_UT_H_ig-oh impedance prober
(Sampling scope)

~

56nH

l l

lO.01 11F

UMK316C, UMK212C, UCN103C Series (Taiyo Yuden)
LQN2A Series (Murata Works)
DRR060UE (Murata Works)
ISV164 (NEC)

MB551
• TEST CIRCUIT EXAMPLE 2

I

?
I

1500 MHz

T

1.5 pF

II
4pF

2 pF

i

iE

,e

7

6

390n

=

I

~ I

MA333 51 pF T

*

OVT

0.01 J!.F

T.1~PF

!

8

82 nH

3pF

I---T---1
GND

i

3 pF

5

MB551

3

2

4

VCC~I
M
fouT

High impedance prober
- - - 0 (Sampling scope)
M

l l lO.01!iF

Chip capacitor:
Chip coil:
Dielectric oscillator:
Varicap:

UMK316C Series (Taiyo Yuden)
LQN2A Series (Murata Works)
DRR060UE (Murata Works)
MA333 (Mitsubishi Electric)

2-87

MB551
• RECOMMENDED PC BOARD PATTERN

Dielectric oscillator

[Mounted component list}
Cl:
C2:
C3:
C4:
C5:
C6:
C7:
C8:
C9:
Cl0:
Cll:
C12:
C13:
C14:

1 pF (Taiyo Yuden UMK212C)
2 pF (Taiyo Yuden UCN103C)
3 pF (Taiyo Yuden UMK212C)
4 pF (Taiyo Yuden UMK212C)
2 pF (Taiyo Yuden UMK212C)
20 pF (Taiyo Yuden UMK316C)
51 pF (Taiyo Yuden UMK212C)
20 pF (Taiyo Yuden UMK316C)
20 pF (Taiyo Yuden UMK316C)
51 pF (Taiyo Yuden UMK212C)
20 pF (Taiyo Yuden UMK316C)
51 pF (Taiyo Yuden UMK212C)
20 pF (Taiyo Yuden UMK316C)
51 pF (Taiyo Yuden UMK212C)

C15: 0.01 IlF (Film capacitor)
C16: 0.01 IlF (Film capacitor)
C17: 0.01 IlF (Film capacitor)

Rl:

390

L 1:
L2:
L3:

22 nH (Murata Works LQN2A)
56 nH (Murata Works LQN2A)
82 nH (Murata Works LQN2A)

Q

(Rohm MCR25)

VD: lSV164 (NEC)

Dielectric oscillator: (Murata Works DRR060 Series, 1.5 GHz)

2-88~

_________________________________________________________________

~

MB551
----

- - _... _ - - -

• MEASUREMENT RESULTS
(1) Supply Current

20.01---+--------t-----+---1
Icc
(mA)

Typ= 16 mA

15.01--+-----1-----+---1
4.5

5.0

5.5
Vee (V)

(2) Oscillation Waveform (50-kHz span)

o I---+--+

E

[Xl

-3D~--~~-+---++-~-++--+-r--r--l

:9Qj

~
S

g.
~

o

Frequency

2-89

MB551
• MEASUREMENT RESULTS (TEST CIRCUIT 1 ON RECOMMENDED PC BOARD)
(1) Conversion Gain

!

865

I

I

I

I
I

lose
(MHz)

V

/

/ 

0

<;>,~:',

~

,,

",'

;~::.:p~!aSheet ~pec

In

.~ (dBm)
.+::
-10
·iii

\

I
I

,

I!

I

,,:,.

-20

a.
.E
-30

-0.6

~

Vi
'

,
\

V-

. . . . . . . . . . 1. .

.......

!

I
1.0

-

Ta=-40°C

-

Ta= +25°C

- - - Ta = +85°C

I

I
1.4

Input frequency fin (GHz)

2-92

V

h

c::
Q)

!II

....::J

\~

1.8

MB551
• MEASUREMENT RESULTS (TEST CIRCUIT 2)
(1) Conversion Gain

I

860

/

i
fosc
(MHz)
845
/

%

6f~ =7.5 MHz/V

I!

/

830

/

I~

I

2.0

1.0

I

I
!

i

I

3.0

4.0

5.0

Vee = 5.0 V
Ta +25°C

=

VT (V)

(2) CIN, SIN
• Control voltage dependence

80~+1----+----r--~----~50
C/N

70

(dB)

~---+-S/N_+_---f---_+__i

··t······· ................ t··

-+~

60

SIN
(dB)

I
C/N (625 kHi)

----+-------t---t 40

I

50

i

I--~--__+----+_---+--__t_; Vee = 5.0 V

'--_'_ _ _'""'""'"-_ _ _ _ _ _'--__~ Ta = +2SoC

1.0

2.0

3.0

4.0

5.0
VT (V)

2-93

MB551
• SAMPLE APPLICATION CIRCUIT

~!':r
I
i~

?'500MH'

-L

-...----.--

4 F

T

'Ttr

i

P

Vee (5 V)

3900

22nH
1 pF

2 pF

3 pF 20 pF

B

8

6

7

1r

5

MB87001A
MB551

234
Vee Clock Data LE

5

678
fin

M

LD

l.!,D~o_ _ _ _ __

3

2

Vee (5 V)

I Vee
CKO----...
8Io---+---,
STB o---+-+--~
47
kQ

47
kO

47
kQ

Vee

33kQ

1000 pF

I

'0""

56 nH

~.
20 pF j;0.01 I1F

2-94

I i'Y

i

Lock Oe1.

l

4
M

120 pF

OUT

I

~ 51 pF

MB551
• ORDERING INFORMATION
Part number
MB551 PF

Package

Remarks

8 pin Plastic SOP
(FPT-8P-MOl )

2-95

MB551
• PACKAGE DIMENSIONS
8 pin Plastic SOP
(FPT-8P-M01 )

I~~;(;~ 1,
~
1.27(.050)·1

TVP

5.30±0.30

2.25J.08~MAX

(Mounting height)
0.05(.002)MIN
(STANDOFF)

•

I

6.80:::::

7.80±0.40

'T'" "T

16

(.268:g:)

'

j

II. 0.15~:

(.006-001 )

I

~

©

2-96

1994 FUJITSU UMITED F080025-4C-4

I
! O.50±O.20
(.020±.008)

_______________ J

Dimensions in mm (inches)

SECTION 3
CMOS Phase-Locked Loops (PLLs) - At a Glance
The Fujitsu family of CMOS PLLs offers a wide range of operating frequencies with low supply current and
voltages to meet many diverse design requirements. A serial input programming capability is a feature of all
Fujitsu's PLLs.

Page
Number

Device Part
Number

fiN (max)

MHz
@3v/5v

N
Program
Counter

A
Swallow
Counter

R
Reference
Counter

loomA
@3vl5v

Voo

Package

3-3

MB87001A

10/13

Binary
5-1023

Binary
0-127

Binary
8-2048

2.0/3.0

2.7-5.5V

16-pin
DIP, SOP

3-15

MB87006A

10/17

Binary
5-1023

Binary
0-127

Binary
5-16383

2.5/3.5

3.0-6.0V

16-pin
DIP, SOP

3-27

MB87014A

-/180

Binary
5-1023

Binary

0-63

Binary
5-65535

-/8.0

4.5-5.5V

16-pin
DIP, SOP

3-37

MB87076

10/10

Binary
5-2047

Binary
0-127

Binary
5-16383

2.5/3.0

2.7-5.5V

16-pin
DIP, SOP

3-49

MB87086A

-/95

Binary
5-1023

none

Binary
5-65535

-/8.0

4.5-5.5V

16-pin
DIP, SOP

3-59

MB87087

10/17

Binary
5-1023

Binary
0-127

Binary
5-16383

2.5/3.5

3.0-6.0V

16-pin
DIP, SOP

3-71

MB87091

300/-

Binary
5-4095

Binary

0-63

Binary
5-16383

8.0/-

2.7-3.3V

16-pin
DIP, SOP,
SSOP

3-89

MB87093A

-1145

725

none

64

-/10

4.5-5.5V

16-pin
SSOP

3-99

MB87094

Binary
5-2047

Binary
0-127

Binary
5-4095

1@1.1V

1.1-1.7V

16-pin
SSOP

3-89

MB87095A

-/110

550

none

64

-110

4.5-5.5V

16-pin
SSOP

3-89

MB87096A

-190

750

none

128

-/10

4.5-5.5V

16-pin
SSOP

15@1.1V

3-1

3-2

00

Sept. 1995

FUJITSU

Edition B.Oa

DATA SHEET

MB87001A
CMOSPLLFREQUENCYSYNTHES~ER

III

CMOS SERIAL INPUT PHASE-LOCKED-LOOP (PLL)
FREQUENCY SYNTHESIZER
The FujHsu MB87001A, fabricated in CMOS technology, is a serial input PLL frequency
synthesizer.
The MB87001 A contains an inverter for connection to an extemal oscillator, a programmable
reference divider, a divide factor of programmable reference divider control circuit, a phase
detector, a charge pump, a 17-bit shift register, a 17-bit latch, a programmable divider (a binary
7-bit swallow counter, a binary 10-bit programmable counter), and a control generator for an
extemal dual modulus prescaler.

PLASTIC PACKAGE
DIP-16P-M04

When supplemented with a loop filter and VCO, the MB87001 A contains the necessary circuitry
to make up a Phase Locked Loop (PLL). Typically, a dual modulus prescaler such as the
MB501L can be added, allowing input frequency operation up to 1.1 GHz.
S2 and S3 input (1/8,1/16,1/64,
1/128, 1/256, 1/512, 1/1024, 1/2048)

•

Single power supply voltage:
Veo = 2.7V to 5.5V

•

Wide temperature range:
TA =-40 to 85°C

•

13MHz typical input capability
@5V (fin input)

•

On-Chip inverter for oscillator

•

8 divide factors for programmable
reference divider is selected by S1 ,

•

Programmable 17-bit divider with
input amplifier consisting of:
Binary 7-bit swallow counter
Binary 10-bit programmable counter

•

2 type of phase detector output
On-chip charge pump output
Output for extemal charge pump

•

Easy interface to Fujitsu dual
modulus prescaler

ABSOLUTE MAXIMUM RATINGS (see NOTE)

(Vss

=OV)

Rating

Symbol

Value

Unit

Power Supply Voltage

Voo

Vss -0.5 to Vss +7.0

V

Input Voltage

VIN

Vss -0.5 to Voo +0.5

V

Output Voltage

VOUT

Vss -0.5 to Voo +0.5

V

Output Current

lOUT

±10

mA

Open-drain Output

Voop

Vss-O.5 to Voo +3.0

V

TA

-40 to +85

°C

TSTG

-65 to +150

°C

300

mW

Operating Temperature
Storage Temperature
Power Dissipation

NOTE:

Po

Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Copyright ©1995 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS, INC.

PLASTIC PACKAGE
FPT-16P-M06

PIN ASSIGNMENT

Voo

16

Vss

Clock

15

OSCIN

Data

14

OSCOUT

LE

13

S3

fin

12

S2

M

11

S1

LD

10

tPP

Do

9

tPR

This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However,
it is advised that normal precautions be taken to avoid
application of anyvoHage higher than maximum rated voltages
to this high impedance circuit.

3-3

MB87001A

Fig. 1 - MB87001A BLOCK DIAGRAM

Voo
Clock

Data

0---

~
2

17-bitShiftRegister

I

0

I
I

l1O-bit Shift Register

7 -bit Shift Register

•

I-

I

I
I
I
I
I
I

:==[OJ]]]===IIII[[[[[[=:
I

LE

~

7-bnLaoch

l~~t ~~

I

Ii
I

I

Programmable Divider

3-4

DO

8

Crystal
Oscillator

I

L _____ J

Divide Factor of
Programmable
Reference Divider
Control Circuit

Binary 10-bit
Programmable Counter

I
I
I
I
I
I

I
I
I
I
I
_ _ _ _ _ _ _ _ _ _ _ .JI

7

I
II
I

:==[[OJJI==UI[[[[[[C:
Binary 7-bit
Swallow Counter

LD

OSC'N

I
1_,I\I1lfl.....---.J

I

17-bit Latch

81---.. . . ·...1
AMP

-@Vss

r----------------------,

Charge Pump

11-bit
Programmable
Reference Divider

fp

fr

MB87001A

PIN DESCRIPTION
Pin No.

Pin Name

I/O

1

VOO

-

Power supply voltage input

Description

2

Clock

I

Clock signal input for 17-bit shift register
Each rising edge of the clock shifts one bit of the data into the shift register

3

Data

I

Serial data input for 17-bit shift register
The data is used for setting the divide factor of the programmable divider

4

LE

I

Load enable input
When this pin is high level (high active). the data stored in the 17-bit shift register is transferred to
the 17-bitlatch.

5

fiN

I

Input for programmable divider from VCO or prescaler output
This input involves the bias circuit and amplifier. The connection with the external dual modulus
prescaler should be an AC connection.

6

M

0

Control output for external dual modulus prescaler
The connection to the prescaler should be a DC connection. This output level is synchronized
with the falling edge of the fiN input signal (pin #5).
Pulse Swallow Function:
MB501 L M = High: Preset modulus factor 64 or 128
M = Low: Preset modulus factor 65 or 129

7

LD

0

Output of phase detector
It is high level when fr and fp are equal. and then the loop is locked. Otherwise it outputs a
negative pulse signal.

8

Do

0

Three-state charge pump output of the phase detector
The mode of Do is changed by the combination of the programmable reference divider output
frequency (fr) and the programmable divider output frequency (fp) as listed below:
Drive mode (Do = High level)
fr >fp:
High-impedance mode
fr=fp:
frfp:
Low
fr=fp:
Low
High-Impedance
High-Impedance
fr < fp:
High
* .pP is a N-channel open drain output

11
12
13

Sl
S2
S3

I
I
I

Control input for programmable reference divider
The combination of these inputs provides 8 kinds of divide factor for the programmable reference
divider.

~

actor

Sn

1
8

1
16

1
-64

-1
128

1
256

-1
512

1
-1024

•

-12048

Sl

0

1

0

1

0

1

0

1

S2

0

0

1

1

0

0

1

1

S3

0

0

0

0

1

1

1

1

14

OSCOUT

0

15

OSCIN

I

Input pin for crystal oscillator.
Input to the inverting amplifier that forms part of the oscillator
This pin receives the oscillator signal as AC coupled when an external oscillator is used.
For large amplitude Signals (standard CMOS levels) DC coupling may also be used.

16

Vss

-

Ground

Output pin for crystal oscillator
Output of the inverting amplifier
This pin should be open when an external oscillator is used.

3-5

MB87001A

FUNCTIONAL DESCRIPTION
DIVIDE FACTOR OF PROGRAMMABLE DIVIDER
Serial data of binary code is inputto the Data pin. These data are loaded into the 17-bit shift registerfrom the MSB. When the load enable signal (LE) is
high, the data stored in the 17-bit shift register is transferred to the 17-bit latch.

0

The data G) to
set a divide factor of the binary 7-bit swallow counter and data G) to @ set a divide factor of the binary 10-bit programmable
counter. In other words, serial data is equivalent to the divide factor of programmable divider.

Fig. 2 - BLOCK DIAGRAM OF PROGRAMMABLE DIVIDER

r-----~----------------------------------------------- -------------

..

MSB

LSB

17-BIT
SHIFT
REGISTER

Data
Clock

,

---------,
17-BIT
LATCH

LE

---------r,
Binary 7-bit Swallow Counter

PROGRAM-'
MABLE
'
DIVIDER

Binary 10-bit Programmable Counter

,
I.

3-6

_____________________________________

-

_

-

_

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

..

MB87001A
Binary 7-bit Swallow Counter Data Input

CD ®
0

0

®

0

®

0

CD

Divide
Factor A

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

1

0

2

0

0

0

0

0

1

1

3

0

0

0

0

1

0

0

4

1

1

1

1

1

1

1

127

1.11

Note: Divide factor A: 0 to 127
Depending upon the divide factor set input (SW) of extemal prescaler, the input data should be as follows:
Example MB501 L
SW = H (64/65): Bit 7 of shift register (7) should be zero

Binary 10-bit Programmable Counter Data Input

@

@

@

@

@)

@

@

@

®

®

Divide
Factor N

0

0

0

0

0

0

0

1

0

1

5

0

0

0

0

0

0

0

1

1

0

6

0

0

0

0

0

0

0

1

1

1

7

1

1

1

1

1

1

1

1

1

1

1023

Note: Divide factor less than 5 is prohibited
Divide factor N: 5 to 1023

PULSE SWALLOW FUNCTION
fveo =[(N x M) + A] x fr
fveo: Output frequency of extemal voltage controlled oscillator (VeO)
N

Preset divide factor of binary 10-bit programmable counter (5 to 1023)

M

Preset modulus factor of extemal dual modulus prescaler (e.g. 64 in 64/65 mode, 128 in 128/129 mode of an MB501L prescaler)

A

Preset divide factor of binary 7-bit swallow counter (0 to 127)

fr

Output frequency of the programmable reference divider

3-7

MB87001A
TIMING CHART
• tl - t5

~ 1fls,

---~

Data

S1=LSB

Clock

LE

Clock: Clock signal input for the 17-bit shift register
Each rising edge of the clock shifts one bit of data into the shift register.
Data : Serial data input for the 17-bit shift register
LE

Load enable input
When LE is high (high active), the data stored in the 17-bit shift register is transferred to the 17-bit latch.
The 17-bit data is used for setting a divide factor of the programmable divider.

RECOMMENDED OPERATING CONDITIONS

(Vss =OV)

Value
Parameter

Unit

Symbol
Min

Typ

Max

Power Supply Voltage

Voo

2.7

-

5.5

V

Input Voltage

VIN

Vss

-

Voo

V

Operating Temperature

TA

-40

-

+85

°C

HANDLING PRECAUTIONS
• This device should be transported and stored in anti-static containers.
o

This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats.

o

Always turn the power supply off before inserting or removing the device from its socket.

• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

3-8

MB87001A

ELECTRICAL CHARACTERISTICS
(Vee

=3.0V, Vss =OV, TA =-40 to +85°C)
Value

Parameter

Symbol

Condition

Unit
Min

High-level Input Voltage

-

2.1

-

-

VIL

-

-

-

0.9

fiN

0.8

-

-

VflN

Input Sensitivity
OCS IN
High-level Input Current

Vose

Amplitude in AC
coupling, sine wave

fiN

High-level Output Voltage

Low-level Output Voltage

P and OSCOUT
Low-level Output Voltage
Low-level Output Voltage

$P

High-level Output Voltage

High-level Output Current

Typ

3.5

-

-

N-channel Open Drain
Cut Off Current

4>P

V

1.0
-1.0

-

-

±50

-

-

±50

-

1.5

-

4.95

-

-

Vp_p

~

~

V
0.05

IOH

VOH=2.0V

-1.0

IOl

VOL = O.SV

1.0

Vo = Voo +3.0V

-

1.0

-

Il A

IOl=O.SmA

VOHX

IOH=OI!A

VOlX

IOl=O~

4.50

-

IOFF

1.0

-

V

0.50

-

rnA

100

-

-

2.0

-

rnA

Max. Operating Frequency of
Programmable Reference Divider

fMAXd

-

15

25

-

MHz

Max. Operating Frequency of Programmable Divider

fMAXp

-

13

25

-

MHz

Power Supply Current* 1

Note: *1: fiN = 5.0MHz, 12.8MHz crystal is connected between OSCIN and OSCOUT.
Inputs are connected to ground except for fiN and OSCIN. Outputs are open.

3·10

1.5

-

1.0

Except 4>P and OSCOUT
Low-level Output Current

Max

-

VOlP

OSCOUT
Low-level Output Voltage

Unit
Min

MB87001A
Fig. 3 -TYPICAL APPLICATION EXAMPLE

OUTPUT

III

tJ-----........

Clock
----J
Data Q._ _ _- - I - - - - - - - l
LEo--.--+--+---------~

47k!l 47k!l 47k!l

12.BMHz x'tal

5V± 10%
BV Max.
depends on crystal osillator

LOCko-___-._______________________

~

Det.

10k!l

TYPICAL CHARACTERISTICS CURVES
Inupt Sensitivity vs. Input Frequency
(fin Section)
Voo

Power Supply Current vs. Input Frequency

=5V. TA =+25'C

Voo

500

1

=5V

TA

=+25'C

1

OSCIN = 12.8MHz

I- fr=O.lMHz

I

200

II

100

Power
Supply
Current 3

I

Input
Sensitivity 50
VflN (mVp.p)

II

20

[7

100 (mA)

to-

V

t...-..- ~

j
10

~r-

/

10
10

20

50

100

20

50

100

Input Frequency fiN (MHz)

Input Frequency fiN (MHz)

3-11

MB87001A

PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M04)

1S 0 MAX

-t

INDEX-1

INDEX-2

.1

.300(7.62)

(6.2o±O.25)

TYP

r:
I

G---:::

(O.99~·30)

©1991 FUJITSU LIMITED D16033S-2C

3-12

I~r

.244±.010

/<:.,-N-,---,---r-----,---,--~---,-,-----r~~ ~

\

Dimensions in
inches (millimeters)

MB87001A

PACKAGE DIMENSIONS (Continued)
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M06)
.089(2.2S)MAX
(MOUNTING HEIGHT)
.002(0.OS)MIN
(STAND OFF HEIGHT)

-+---.,---

.307±.016
(7.8o±0.40)

INDEX

o

/
"B"

.268 ~:g6~

.209±.012
(S.3o±O.30)

~---..----r-r--'---'-'-~ ~
I

.OSO(1. 27L
TVP

.1 ! .018±.00~ 'Ir-~,-I
of

r-10=-.0"""0-S("'-0.-13-:-)-=®-',
(0.4S±0.10)L..:-..l...-----=---.J
-- --- -- --- --- --- -- l

"A"

(6.80~:~g)

==tI

II
-H--

J

Details of "A" part

.016(0.40): :

(0. so±o.2
  • :··.unlt .

Power Supply Voltage

Voo

Vss -0.5 to Vss +7.0

V

Do

Input Voltage

VIN

Vss -0.5 to Voo +0.5

V

VSS

11

LE

VOUT

Vss -0.5 to Voo +0.5

V

LD

10

Data

lOUT

±10

mA

fin

9

Clock

Ta

-40 to +85

°C

TSTG

-55 to +125

°C

Po

300

mW

Output Voltage
Output Current
Operating Temperature
Storage Temperature
Power Dissipation
NOTE:

Permanent device damage may occur if the above Abaolute Maximum Ratlnga are exceeded. Functional
operation should be restricted to the conditions as detailed in the oparalionar sections of this data sheet
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Copyright©

1995 FUJITSU

This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However,
it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voHages
to this high impedance circun.

LIMITED and FUJITSU MICROELECTRONICS, INC.

3-15

MB87006A
Fig. 1 - MB87006A BLOCK DIAGRAM

r-----------,I

I

14-bit Shift Register

I
I

~------~

~~~or-r-""""I"'f""I'......:J1

r------,
I
Crystal
I
I
I

OSCOUT

Oscillator

I
I

I
I

I
I

I
I

Programmable
Reference Divider
Binary 14-bit
Reference Counter

I

L _ _ _ _ _ _ _ _ _ _ ..J

L.I ............... L.I ..... , ' - _ _ _ _ _ ,

I
I
I

r------,

I

Control Register

I
I

I

I

I

I

I

L_________ ____________ II

I

3·16

..J

MB87006A

PIN DESCRIPTION
~'nN~;

. .•••.• .·.• I·.····......

i·.

...

...

.

<.

DescrlpUon

...

.<

.::................<................<..........c:{••••<. . . .

..»

Input pin for crystal oscillator.
Input to the inverting amplifier that forms part of the oscillator.
This pin receives the oscillator signal as AC coupled when an external oscillator is used. For large
amplitude signals (standard CMOS levels) DC coupling may also be used.

1

OSCIH

2

OSCOUT

0

Output pin for crystal oscillator.
Output of the inverting amplifier. This pin should be open when an external oscillator is used.

3

fv

0

Monitor output of the phase detector.
This pin is tied to the programmable divider output.

4

Voo

-

Power supply voltage input.

0

Three-state charge pump output of phase detector.
The mode of Do is changed by the combination of programmable reference divider output frequency
fr, and programmable divider output frequency fv as listed below:
fr> fv:
Drive mode (Do = High level)
High impedance
fr= Iv:
Ir < fv:
Sink mode (Do = Low level)

5

Do

J

6

Vss

-

Ground.

7

lD

0

Output of phase detector.
It is high level when fr and fv are equal, and when the loop is locked.
Otherwise it outputs negative pulse signal.

8

fin

I

Clock input for programmable divider.
This input contains internal bias circuit and amplifier. The connection with an external dual-modulus
prescaler should be an AC connection.

9

Clock

I

Clock signal input for 17-bit shift register and 14-bit shift register.
Each rising edge of the clock shifts one bit of the data into the shift registers.

10

Data

I

Serial data input for programmable divider and programmable reference divider.
The last bit of the data is the control bit. Control bit determines which latch is activated. The data
stored in the shift register is transferred to the 14-bit latch when the bit is high, and to 17-bit latch when
low.

11

LE

I

Load enable input with internal pull up resistor.
When this pin is high (active high), the data stored in shift register is transferred to 14-bit latch or 17-bit
latch depending on the control bit data.

12

M

0

Control output for an external dual modulus prescaler.
The connection to the prescaler should be DC connection. This output level is synchronized with failing edge of fin input signal (pin #8).
Pulse swallow function:
e.g. MB501L: M = High: Preset modulus factor 64 or 128
M = Low Preset modulus factor 65 to 129

3-17

MB87006A

PIN DESCRIPTION (Continued)
13

fr

o

Monitors output of phase detector input.
This pin is tied to the programmable reference divider output.

14

REFoUT

o

Monitor output pin of the reference frequency.
This output can be used as system clock for microprocessor, or reference oscillator for another PLL
frequency synthesizer.

o
o

Output for external charge pump.
The mode of $R and $V are changed by the combination of programmable reference divider output
frequency fr and programmable divider output frequency fv as listed below.

15
16

fr> fv:
fr= tv:
fr < fv:

~R

~V

Low-level
High-level
High-level

HIgh-level
High-level
Low-level

FUNCTIONAL DESCRIPTION
SERIAL DATA INPUT TIMING

Data

Clock

~~~~

Control bit

(S2)

(Control bit)

.•..

LE

.1.1.

(S1)

latts

• Data for programmable reference divider.

Nol•• :

Data: Serial data input is used for setting divide factor of programmable reference divider and progranmable divider.
Data is input from MSB, and last bit data is a control bit.
Control bit is set high when divide factor of programmable reference divider is set. Control bit is set low level when divide factor 01
programmable divider is set.
Clock: Data is input to internal shift registers by rising edge of the clock.
LE: Load enable input:
When LE is high, the data stored in shift register is transferred to 14-bit latch, or 17-bit latch depending on the control bit setting.

3-18

MB87006A
PULSE SWALLOW FUNCTION
fyco = [ (N x M) + A I x fose ... R (N > A)
fvco

Output frequency of extemal voltage controlled oscillator (VCO)

N

Preset divide factor of binary 10-bit programmable counter (5 to 1023)

M

Preset modulus factor of external dual modulus prescaler
(e.g. 64 in 64/65 mode, 128 in 128/129 mode of an MB501L prescaler)

A

Preset divide factor of binary 7-bit programmable counter (0 to 127, A < N)

fose

Output frequency of extemal oscillator

R

Preset divide factor of binary 14-bit programmable reference counter (5 to 16383)

DIVIDE FACTOR OF PROGRAMMABLE REFERENCE DIVIDER
Serial data consists of 14-bit data, which is used for setting divide factor of programmable reference counter, and l-bit control data. In this case,
control bit is set high level.
The data format is shown below.

Control
Register

LSB

MSB

Data

14-bit
Shift Register

Clock

----------- ...
I

------------'
I

I

Programmable
Reference
Divider

Binary 14-bit Reference Counter

,

BINARY 14-BIT REFERENCE COUNTER DATA INPUT

@

@

0

0

® ® 0

0

® ®

CD

Divide
Factor

@

@

@

0

0

0

0

0

0

0

0

0

0

1

0

1

5

0

0

0

0

0

0

0

0

0

0

1

1

0

6

0

0

0

0

0

0

0

0

0

0

0

1

1

1

7

1

1

1

1

1

1

1

1

1

1

1

1

1

1

16383

® ®

Note: Divide factor less than 5 is prohibited.
Divide factor : 5 to 16383

3-19

MB87006A
DIVIDE FACTOR OF PROGRAMMABLE DIVIDER
Serial data consists of 17-bit c1ata, which is used for setting divide factor of programmable divider, and l-bit control c1ata. In this case, control bit is
set low level. The data (D toQ) set a divide factor of 7-bit swallow counter and c1ata@to@setdivide factor of lQ-bit programmable counter.
The data format is shown below.

lSB

MSB

Data

17-bit
Shift Register

Clock

Binary 10-bit Programmable Counter

Binary 7-bit Swallow Counter

BINARY 7·BIT SWALLOW COUNTER DATA INPUT

0

® ®

@

®

® CD

Divide
Factor

A

0
0
0
0
0

0
0
0
0
0

0
0
0
0

0
0

0
1

1

1

0

2

0
0

0
0
0
0
0

1

1

3

1

0

0

4

1

1

1

1

1

1

1

127

0
0
0

0

Note: Divide factor A: 0 to 127
Depending upon the divide factor set input (SW) of external prescaler, the input data should be as follows.
e.g. MB501L (+65/65)prescaler
SW = H (64165): Bit 7 to shift registerQ) should be zero.

BINARY 10·BIT PROGRAMMABLE COUNTER DATA INPUT

@

@

0
0

0
0

0

0

1

1

@

@

@

@

0

0

5

1

0

6

0

0
0
0

1
1

0

0
0
0

1

0
0

0
0

0

0

1

1

1

7

1

1

1

1

1

1

1

1

1023

Note: Divide factor less than 5 is prohibited
Divide factor N : 5 to 1023

3·20

Divide
Factor
N

@

@

® ®

Programmable:
Divider

MB87006A
PHASE DETECTOR OUTPUT WAVEFORM

Iv

DO~

n

~RU

U

~V

LOU

U

¢

U

High Impedance

U
U

RECOMMENDED OPERATING CONDITIONS

3.0

6.0

v

Input Voltage

Vss

Voo

v

Operating Temperature

-40

+85

Power Supply Voltage

Voo

3-21

MB87006A

ELECTRICAL CHARACTERISTICS
(VDD

. . . . . . . . <.
. « > .............
.••:•••.•••••••.....•...•.•••••.......

)<

........... \.>

ii.··.;········ .i..:
.• / .•.•.• . . . :«

<

=3.0V, Vss =OV, TA =-40 to 85°C)

........... ••.•...... <..···.2 .< •. . /< « .......
.......
s,,~~ '@ :.:' .... ..
>< "7
?
.
'
:
•
>.•... .. :....
'i:
.>. '.::::. tU.·r
>< i\

)

:

.....

High-level Input Voltage

V1H

i

VooxO,7

Except fin
Low-level Input Voltage

and OSCIN

V
VooxO,3

VIL

fin

Vfpp

OSCIN

Vsin

Input Sensitivity

High-level Input Current

...

Amplitude in AC
coupling, sine wave

0,5
Vp_p
0,5

IIH

VIN '" Voo

1,0

k

VIN '" Vss

-1,0

fin

lIin

VIN == Vss to Voo

±30

~

OSCIN

lose

VIN '" Vss to Voo

±30

~

LE

ILE

VIN: Vss

-40

~

Except

VOH

IOH= 0j.1A

VOL

IOL= OJ.1A

IOH

VOH = 2.6V

-0,5

IOL

VOL: O,4V

0,5

IOHM

VoH== 2,6V

-0,7

Low-level Output Current

IOLM

Vo L==O,4V

1,5

Power Supply Current-'

100

Except fin

~

and OSCIN
Low-level Input Current

Input Current

High·level Output Voltage
Low-level Output Voltage

High·level Output Current
Except M
and OSCOUT
Low-level Output Current
High-level Output Current

2,95
V

OSCOUT

0,05

mA

M

2,5

mA

Maximum Operating Frequency of
Programmable Reference Divider

fmaxd

10

20

MHz

Maximum Operating Frequency of
Programmable Divider

fmaxp

10

20

MHz

Notes:

3-22

mA

-1: fin = 8.0MHz 11,5MHz Crystal is connected between OSCIN and OSCOUT
Inputs are grounded except for fin and OSCIN. Output are open.

MB87006A

ELECTRICAL CHARACTERISTICS (continued)
. . :. .:.. . . . .
>.....::..... ·i c : . : :. . . . : . . . . . ..
:...:........::.:. :.: ••. :.:.: . . :.;.........:.<

.?<
:. . . :.•.: . .

(Voo

= 5.0V, Vss = OV, TA = -40 to 85°C)

··::«:~i

High-level Input Voltage
Low-level Input Voltage

Symbol

:

.. ..
:

VIH

:.. :. . . . .

.·.:·· .•:... Min

Value

Except lin

\

.. .•.... :......... :..... .

VooxO.7

V
VooxO.3

Vlpp

Amplitude in AC

0.5
Vp.p

coupling. sine wave
OSCIN

.

:Unit

Vil

fin

..••••••••..•.•..

Typ

Except lin
andOSCIN

Input Sensitivity

High-level Input Current

....

Condltlorl

Vsin
IIH

0.5

VIN '" Voo

1.0

VIN '" Vss

-1.0

andOSCIN
Low-level Input Current

Input Current

lin

Ifin

VIN '" Vss to Voo

±50

OSCIN

lose

VIN = Vss to Voo

±50

VIN = Vss

-60

lE
High-level Output Voltage

Except

VOH

IOH =01lA

4.95

V

OSCOUT
Low-level Output Voltage
High-level Output Current

0.05

10H

VOH: 4.6V

-1.0

10l

VOL =O.4V

1.0

IOHM

VOH'" 4.6V

-1.5

Low-level Output Current

10lM

Vov'= O.4V

3.0

Power Supply Current.'

100

Except M
and OSCOUT

Low-level Output Current
High-level Output Current

mA

M

mA

3.5

mA

Maximum Operating Frequency 01
Programmable Relerence Divider

Imaxd

10

25

MHz

Maximum Operating Frequency of
Programmable Divider

Imaxp

17

25

MHz

Note:

.1. lin = 8.0MHz. 11.5MHz Crystal is connected between OSCIN and OSCOUT
Inputs are ground except for lin and OSCIN. Outputs are open.

3·23

MB87006A

TYPICAL CHARACTERISTICS CURVE

INPUT SEVSITIVITY CHARACTERISTICS (fin Section)

500

200

100

50
Input Sensitivity

Vlin (mVp.p)

20

""'~

,I

./

10
5

2
2

5

10

20

Input Frequency lin (MHz)

3-24

50

100

MB87006A

PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M04)

__

---t1 S' MAX
-,

~-~r;;;;:::~_::::;-_-=:=-=::I

300(762)

TYP

,..-----------,-- --I

_. _~. 4'

72(436, MAX

I

1.118(300) MIN

L.1
~59il~71 _ _ -

MAX

C 1988 FUJITSU LIMITED D16033S·2C

TYP

020(0.51) MIN

Dimensions in
inches (millimeters)

3-25

MB87006A

PACKAGE DIMENSIONS (Continued)
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M06)
089(225) MAX

I (SEATED

~
•

t----.

r#:=:::!:!::=:!::!::::!:!:~===!::::::!:==:!ri

1307 •. 01 6
(780" 040)
209- 012

1/;F::;;;:=n==rr=;;:===Ti"f..:;;..r=,=rt>J.
05 0(127)
TYP

I

I

"3~ .

HEIGHT)-

:~~5~~:N
.268' .016 (680 - 040)
006 . - 0.20

or

----+ 020 =006
0 .05 )
~ .006"... 002(0.15001
-0.02
.---t (0 500 020)

004~-:-;:;:;:;;=-;..-:c;;-;-::-1
10)~1 <1>005(0 13)~

018'
--4;045' o.

·-De~a~l; -;'1- ~A'- ;a;t--:

ij§

'6(040):

·

H;

· I
I

350\869\ REF
~

3-26

1990 FUJITSU LIMITED F16015S·2C

008'020':

! 007(018) ,
I
MAX
:
1027(068)
I
MAX
:

Dimensions in
inches (millilT18lars)

c»

DS04-21305-3aE

~~~~~~~~~~~ET~~ruJrrsu
MB87014A ASSP
CMOS PLL Frequency Synthesizer
CMOS SERIAL INPUT PHASE-LOCKED-LOOP (PLL)
FREQUENCY SYNTHESIZER
The Fujitsu MB87014A, fabricated in advanced CMOS technology, is a serial input phase locked
loop (PLL) frequency synthesizer with an on chip 180MHz dual modulus prescaler.
The MB87014A contains a dual modulus prescaler, inverter for an extemal oscillator,
programmable reference divider, control circuit, phase detectors, charge pump, programmable
divider (binary 6-bit swallow counter and binary 10-bit programmable counter).
The MB87014A can make up PLL frequency synthesizer operating up to 180MHz.
• Single Power Supply Voltage: Voo =4.5V to 5.5V
• Wide Temperature Aange: Ta =-30 to 60°C
• 180MHz input capability @5V (fin input)
• On-chip Inverter for oscillator
• Programmable divider with input amplifier consisting of;
Binary 6-bit swallow counter
Binary 10-bit programmable counter
• Programmable reference divider with input amplifier consisting of;
Binary 16-bit programmable reference counter
• Divide factor of programmable divider and programmable reference divider are set by
serial data input. (The last data bit is a control bit.)
• 3-type of phase detector outputs
On-chip charge pump output for active LPF
On-chip charge pump output for passive LPF
Output for extemal charge pump
• 16-pin Standard Dual-in-line Package (Suffix: -P)
16-pin Standard Flat Package (Suffix: -PF)
• Pulse Swallow Function
fvco [(N x M) +A] x (fosc + A) (N > A)
fvco : Output frequency of extemal voltage controlled oscillator (VCO)
N
: Preset divide factor of binary 10-bit programmable counter (5 to 1023)
M
Preset modulus factor of intemal dual modulus prescaler (64/65)
A
Preset divide factor of binary 6-bit swallow counter (0 to 63)
fosc
Output frequency of the extemal oscillator
A
Preset divide factor of binary 16-bit programmable reference counter
(5 to 65535)

PLASTIC PACKAGE
DIP-16P-M04

PLASTIC PACKAGE
FPT-16P-M06

PIN ASSIGNMENT

=

16

ellA

OSCOUT

15

eIIV

fv

14

NC

13

fr

OSCIN

10

Voo
TOP VIEW

Operating Ambient
Temperature

~;~~~i~~n!~~I~b~a::t~i~t':J~oof~r!'~~i:~V:S

NOTE:

Copyright

i~~!~~:::a~i~~:rs~~fo:c:~e:'Ia~~~~~t

e
AJ::II:d
Exposure to absolute maximum rating condHions for extended periods may affect device reliabilHy.

©

Dop

12

DOA

Vss

11

LE

LD

10

Data

fin

9

Clock

This device contains circuitry to protect the inputs against
damage due to high staticvo!tages or electric fields. However,
H is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages
to this high impedance circuit.

1994 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS, INC.

3-27

MB87014A
MB87014A BLOCK DIAGRAM

CRYSTAL
OSCILLATOR

I

PROGRAMMABLE REFERENCE DIVIDER

I

I

I

BINARY l6-BIT
PROGRAMMABLE REFERENCE
COUNTER(RI

BINARY6-BIT
(AI
SWALLOW
COUNTER
CONTROL

3-28

BINARY lD-BIT
IN)
PROGRAMMABLE
COUNTER

I

MB87014A

PIN DESCRIPTION
pin No.

..«
•. :. ><:.• :• •.: .•.•.:.:. :.

symbol .·lfA<

.) ..

:::::

.:::..::<::::::::::

:>.

Description

...

.........................
.

>

. . · : : i : · :.::

••••••••••••••••••

1

OSC'N

I

2

OSCOUT

0

Output pin for crystal oscillator.
Output of the inverting amplifier. This pin should be left open when an external oscillator is used.

3

fv

0

Monitor pin for the phase detector input.
This pin is tied to the programmable divider output.

4

Vee

-

Power supply voltage input.

0

Output pin for low pass filter (Passive type).
The mode of OOP is changed by the combination of programmable reference divider output frequency
fr, and programmable divider output frequency fv as listed below:
fr > fv:
Drive mode (Oop =High level)
High-impedance
fr =fv:
f,fv:
Sink mode (OOA = Low level)
High-impedance
fr =fv:
Drive mode (OOA =High level)
fr  fv:
fr = Iv:
fr < fv:

oV

~R

High level
High level
Low level

Low level
High level
High level

3-29

MB87014A

FUNCTIONAL DESCRIPTIONS
DIVIDE FACTOR OF DIVIDER
Serial data of binary code is input to Data pin. On rising edge of clock shifts one bit of data into the shift registers. Input data consists of 16-bit data
and 1-bit of control data. The control data determines which latch is activated. When control bit is high, 16-bit latch is selected. When low, 6-bit
latch and 10-bit latch is selected.

Last Data Input

Control Bit

First Data Input

LSB
Divide factor of divider setting bits ----------~

The serial data is input to 16-bit shift registers and 1-bit control register. When load enable is high, the data from the shift register is latched into the
programmable reference divider (binary 16-bit programmable reference counter) or programmable divider (binary 6-bit swallow counter and
binary 10-bit programmable counter) depending upon a control bit setting.

MSB

LSB

16bit
Shift
..._ ..................,..............~....' -.......""'".............,..................,........,................................... Register

16bit
Latch

LE

Binary 16-bit Programmable Reference Counter (C ="W)
or
Binary 6-bit Swallow Counter or Binary 10-bit Programmable Counter (e

3-30

="L")

MB87014A

FUNCTIONAL DESCRIPTIONS (Continued)
BINARY 6-BIT SWALLOW COUNTER
DATA INPUT
Divide
Factor

CD CD ® 0 ®

@

BINARY 1D-BIT PROGRAMMABLE COUNTER DATA INPUT
Divide
Factor

® ® ®

@ (1) @ @ @

@ @

0

0

0

0

0

0

0

5

1

0

1

0

0

0

0

0

0

0

1

1

0

0

0

0

0

6

0

1

1

0

0

0

0

0

0

0

2

0

1

0

0

0

0

7

1

1

1

0

0

0

0

0

0

0

63

1

1

1

1

1

1

1023

1

1

1

1

1

1

1

1

1

1

..

• DIvIde factor A: 0 to 63

III

• Divide factor N: 5 to 1023
• Divide factor less than 5 is prohibited.

BINARY 16-BIT PROGRAMMABLE COUNTER DATA INPUT
Divide
Factor

CD CD CD CD ® ® ®

@ ® @ @ @ @ @ @ @)

5

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

6

0

1

1

0

0

0

0

0

0

0

0

0

0

0

1

0

7

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

65535

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

• Divide factor R: 5 to 65535
• Divide factor less than 5 is prohibited.

STAND-BY MODE
When all zero of 16-bit serial data is input, the MB87014A goes to stand-by mode. During stand-by mode, internal circuit stops operation and fin and
OSCIN are forced to high level. Thus, low supply current is achieved. Stand-by down mode is release, when the data except all zero data is input.

SERIAL DATA INPUT TIMING

Data

Clock

_ .@-XI::::
.
~
I
I

I

•••

@

>.<0

:::~_c

JLl1L....
I

I

___

- - - -rL
' ,

II

LE

'---..
:

12

:

b~"

'........"

"

t4

I

,

ts~

"
Notes:

Data: Serial data input is used for setting divide factor of programmable reference divider or progranmable divider.
Data is input from MSB and last bit data is control bit.
Control bit is high level when divide factor of programmable reference divider is set. Control bit is set low level when divide factor
of programmable divider is set.
Clock: Clock input for 16-bit shift registers and control register. Data is input into internal shift registers by rising edge of the clock.
LE: Load enable input:
When LE is high, the data from shift register is latched into programmable reference divider or programmable divider depending
upon the control bit setting.

3-31

MB87014A
PHASE DETECTOR OUTPUT WAVEFORM

ILJl

Iv

Dop

,
,
,
,

----l

,
,

GR

,

n
,

, ,,
,,

,

u.

,,

----1,

U

l

U

n

U
, ,

,
,
,

3-32

l

¢:I HIGH IMPEDANCE

,
,

GV

LD

n

,

,

DOA

,

,

I

U U

¢:I HIGH IMPEDANCE

MB87014A

RECOMMENDED OPERATING CONDITIONS
Value

Typ
5.5

V

Vss

Voo

V

-30

+60

DC

Power Supply Voltage

Voo

4.5

Input Voltage

VIN

Operating Temperature

T..

5.0

ELECTRICAL CHARACTERISTICS
I} ........> . . . . . . . .·.·.....i '/.<) .}<. ./
1«' . . ...»<. ~.. cc«'i.
..' . .......
Ii
····«/·
. .·.,i .·........<> . · . « >
i '...........
I.· ...... .•.
.............................. ........... .....................
'<.:
High-level Input Voltage
Low-level Input Voltage

Except fin
andOSCIN

I~.,"~I

(Vss

III

=OV, Voo =SV, T.. =-30 to 60°C)

·.:H .........< ,j> . /.<) ·.·. •.

3.5

VIH

V
VIL

fin

Vtpp

OSCIN

V"n

Input Sensitivity

1.5

1.0
Amplitude in AC coupling,
Sine wave

Vp.p

1.0

"H

VIH = Voo

1.0

IlL

VIL = Vss

-1.0

lfin

VIN = Vss to VOO

±50

lose

VIN = Vss to VOO

±50

VOH

IOH= O~

VOL

IOL=O~

IOH

VOH = 4.6V

-1.0

Low-level Output Current

IoL

VOL = 0.4V

1.0

Power Dissipation.'

loop

8.0

rnA

Stand-by Current. 2

loos

100

~

High-level Input Current
Low-level Input Current

Except fin
andOSCIN
fin

~

~

Input Current
OSCIN
High-level Output Voltage

Except
OSCOUT

Low-level Output Voltage
High-level Output Current

Maximum Operating. 3
Frequency

Notes:

Except
OSCOUT

4.95
V

0.05

rnA

REF Section

fm•• d

40

60

MHz

PD Section

fm ..p

180

250

MHz

.1: fon = 180MHz, 22MHz cystal is connected between OSCIN and OSCOUT pins.
Inputs are grounded except fin and OSCIN. Outputs are open .
• 2 All serial data is set to zero. Input are grounded except fin and OSC,,,. Output are open .
• 3 REF Section :Maximum operating frequency of programmable reference divider.
PD Section :Maximum operating frequency of programmable divider.

3-33

MB87014A

TYPICAL CHARACTERISTICS CURVES
Input Sensitivity vs. Input Frequency (fin Section)

=5V, Ta =25°C

Voo
500

200

~

~V

~\.

100

,~

Input Sensitivity 50
Vfin (mVp-p)

V

V

/

'- ~"

20

10

5

5

2

10

20

100

50

200

Input Frequency fin (MHz)

Power Supply Current vs. Input Frequency
Voo

=5V, Ta =25°C

12

10

8
Power Supply Current

100 (mA)

6

---

4

V"

V

"

v

2

o

2

5

10

20

50 100

Input Frequency fin (MHz)

3-34

200

500

MB87014A

PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M04)

III
300(762)

TYP

.050(1.27)

MAX

@1988 FUJITSU LIMITED D16033S-2C

.020(0.51) MIN

Dimensions in
inches (millimeters)

3-35

MB87014A

PACKAGE DIMENSIONS (Continued)
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M06)

089(2.25) MAX
(SEATED HEIGHT)
'-, .400+.010(10.15-0.256
-.008
-0.20
i

i

-INDEX
,../'/

U

"B"

"

.050(1.27)

TYP

L07±016

1(7·80± 0.40)
209±.012
(530± 030)

_~=IJ

JL·~$14>005(013).M I
(0.45 ± 0.10)

268 :gb~ (6.80 ~ g~g)

--+

.020± .008

li----t (0.50::020)
--Il- .0064--001
.002 (0. 15 + 005)
-0.02

"A"

@1990 FUJITSU LIMITED F16015S-2C

3-36

Dimensions in
inches (millimeters)

00

DS04-21203-4E

FUJITSU

DATA SHEET

MB87076
CMOSPLLFREQUENCYSYNTHES~ER

•

CMOS SERIAL INPUT PHASE-LOCKED-LOOP (PLL)
FREQUENCY SYNTHESIZER WITH POWER DOWN MODE
The Fujitsu MB87076, fabricated in CMOS technology, is a serial input PLL frequency
synthesizer that features a power down mode.
The MB87076 contains an inverter for the oscillator, 14-bit shift register, 18-bit shift register,
1-bit control register, 14-bit latch, 18-bit latch, programmable divider (binary 11-bit
programmable counter and binary 7-bit swallow counter), programmable reference divider
(binary 14-bit programmable reference counter), phase detector, charge pump, control
generator for two modulus prescaler, and power down circuit.
The MB87076 selects either operation mode or power down mode, depending on the PS input
signal level. When the device begins operation, phase fr and fv are synchronized.
• Single power supply voltage: Voo = 2.7 to 5.5V
• Wide temperature range: TA = -40 to +85°C
• Low power supply current: 3mA typ, (100IJA in power down mode)
• On-chip inverter for oscillator
• Programmable reference divider with input amplifier
Programmable divider with input amplifier
• 2 Types of phase detector output
On-chip charge pump output
Output for external charge pump
• On-chip power down circuit
• 16-pin standard dual-in-line package (Suffix: -PI
16-pin standard flat package (Suffix: -PF)
• Pulse swallow function
fveo
((N x M) +A) x fose + R
fveo : VCO (Voltage Controlled Oscillator) output frequency
N
Preset divide factor of binary 11-bit programmable counter
(16 to 2047)
M
Preset modulus factor of external two modulus prescaler
(64 in 64/65 mode, 128 in 128/129 mode)
A
Preset divide factor of binary 7-bit swallow counter (0 to 127)
fose
Output frequency of an external oscillator
R
Preset divide factor of binary 14-bit programmable reference counter
(8 to 16383)

=

ABSOLUTE MAXIMUM RATINGS see NOTE)
Rating
Power Supply Voltage

Symbol

Value

Unit

Voo

Vss -0.5 to Vss +7.0

V
V

VIN

Output Voltage
Output Current

VOUT

Vss -0.5 to Voo +0.5

V

lOUT

±10

rnA

Open Drain Output

VoP

Vss -0.5 to Voo +3.0

V

Ta

-40 to +85

°C

TSTG

-55 to +125

°C

Po

300

mW

Operating Temperature
Storage Temperature
Power Dissipation
NOTE:

Copyright

Permanent device damage may occur If the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sactions of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

© 1994 by FUJITSU LIMITED

PLASTIC PACKAGE
FPT-16P-M06
PIN ASSIGNMENT
OSCIN

CPR

OSCOUT

CPP

LC

PS

vOO

Vss -0.5 to Voo +0.5

Input Voltage

PLASTIC PACKAGE
DIP-16P-M04

Do

vss

M
LE

LD

Data

fiN

Clock

This device contains circuitry to protect tna inputs against
damage due to high static voltages or electric fields. However.
it is advised that normal precautions be taken to avoid
application of any voltage highelthan maximum rated voltages
to this high impedance circuit.

3-37

MB87076

BLOCK DIAGRAM

r:---------:1
I
I

LE

L:~'"T""I"'",....,...,...,....,....,,..,...,...~~

,--------{13

Power
Down
Circuit

PS

LC

r------,
I Control Register I

I
I
I '---.......,........." T ' T ' " - - - - - - ' I
I
I
I
I
I
I
I
L_____
_ ______ ..JI
M

Clock

3-38

~-----------------------------__t12

MB87076

PIN DESCRIPTION
Pin No.

Pin Name

VO

Description

1

OSCIN

I

Pin for crystal oscillator
The input to the inverting amplifier that forms part of the oscillator. This pin receives the oscillator
signal as an AC coupling when an external oscillator is used. For large amplitude signals
(standard CMOS levels) DC coupling may also be used.

2

OSCOUT

0

Pin for crystal oscillator
The output of the inverting amplifier. This pin should be connected to ground when an external
oscillator is used.

3

LC

0

Output pin for loop control signal
This pin is at high level when the operation mode is selected. It is at low level when the power
down mode is selected.

4

Voo

-

Power supply voltage

5

Do

0

Three-state charge pump output
The mode of Do is changed by the combination of the programmable reference divider output
frequency (fr) and the programmable divider output frequency (fp) as listed below:
Do = H level
fr >fp:
Do = High-impedance level
fr=fp:
f, fp:
fr = fp:
Low
High
fr  fv:
High-impedance
fr= fv:
Sink mode (Dop = Low level)
fr  Iv:
High-impedance
fr= fv:
fr  fv:
Ir= fv:
fr < fv:

~V

~R

High level
High level
Low level

Low level
High level
High level

III

3·51

MB87086A

FUNCTIONAL DESCRIPTIONS
DIVIDE FACTOR OF PROGRAMMABLE REFERENCE DIVIDER
Serial data of binary code is input to Data pin. Each rising edge of clock makes one bit of the data shift into the shift registers and control register.
Input data consists of l6-bit or 10-bit data and 1-bit of control bit data. The l6-bit data is used for setting the divide factor of programmable
reference divider. The 10-bit data is used for setting the divide factor of programmable divider.
The last bit of the data stored in control register is a control bit. Control data determines which latch is activates. When this bit is at high level, l6-bit
latch is selected. when this is at low level. 10-bit latch is selected.
The data format is shown below.

Last Input Bit
Programmable
Reference Divider

Programmable
Divider

1+------- Divide Factor of Programmble Reference
Divider Setting Bits

When LE is high level and control bit is high level. the data stored in l6-bit shift register is transferred~ l6-bit latch. When LE is high level and
control bit is at low level. the data stored in 10-bit shift register is transferred to 10-bit latch.

~~~-r~~~~~~~~~~~~~~~~~~~

l6-bit
Latch

.......,.......,..~r--'-r....l...,....&....,.......~......T"'"......r--oI....,...a...,....a...... l6-bit

,....'-,~...,....a...,....&...,..

Shift

....._ ......_ ......_ ......_ ......_ ......_ ......_ ......_ ......_ ......_ ......_ ......_ ......_ ......- ......- ........... Register

LE

3-52

MB87086A
BINARY la-BIT PROGRAMMABLE DIVIDER DATA INPUT
(10)

(9)

(8)

(7)

(6)

(5)

(4)

(3)

(2)

(1)

Divide
Factor

0

0

0

0

0

0

0

t

0

1

5

0

0

0

0

0

0

0

1

1

0

6

1

1

1

1

1

1

1

1

1

1

1023

III

Note: Divide factor less than 5 is prohibited.
Divide factor N: 5 to 1023

BINARY l6-BIT PROGRAMMABLE REFERENCE DIVIDER DATA INPUT

@ @) @ @ @ @ @> @ ®

CD ® ® 0 ® ® 0

Divide
Factor

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

5

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

6

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

65535

Note: Divide factor less than 5 is prohibited.
Divide factor R: 5to 65535

SERIAL DATA INPUT TIMING
tt

-t5~

11ls

@(10)

Data

~)~ ~ ~
I

Clock

LE

0

~ ~ ~~_C_ _ _ __

---lli-fl ... JUfL. -,
'-I tt I

Notes:

=x=

n. . --

...., __- - - r -.....

"--tz
I

13~

Data input for programmable reference divider.

()

Data input for programmable divider.

Data

Serial data input is used for selling divide factor of programmable reference divider or progranmable divider.
Data is input from MSB and last bit data is control bil.
Control bit is set high level when divide factor of programmable reference divider is sel. Control bit is set low level when divide
factor of programmable divider is sel.

Clock Clock input for 1O-bit shift register, 16-bit shift register and control register. Data is input into internal shift registers by rising edge of
the clock.
LE Load enable input:
When LE is high level. the data stored in shift registers is transferred to 16-bitlatch, or 10-bit latch depending on the control bit
setting.

3·53

MB87086A
PHASE DETECTOR OUTPUT WAVEFORM

fr

lUl~n,--

Iv

I

I
I

I

Dop

--.J
I

I

t--~...n'--~--fLJt-:~----I------~ HIGH IMPEDANCE

I
I

I

I

I

I

I

I
I
I

D~ ~_'~~~~~~~~~~~~~~~~~~~~~ ~GHIMPEDANCE
I

u
U
I
I

uu
3-54

MB87086A

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Unit

Symbol
Min

Typ

Max

5.0

5.5

V

Power Supply Voltage

Voo

4.5

Input Voltage

VIN

Vss

Voo

V

Operating Temperature

T...

-30

+60

°C

ELECTRICAL CHARACTERISTICS

(Vss

=OV, VDD =SV, T" =-30 to 60°C)
Value

Symbol

Parameter

Unit

Condition
Min

low-level Input Voltage

Except fin
andOSCIN

V
VIL

fin

Vtpp

OSCIN

Vsin

Input Sensitivity

1.5
1.0
Amplitude in AC coupling,
Sine wave

Vp.p
1.0

IIH

VIH = Voo

1.0

IlL

VIL = Vss

-1.0

fin

Ifin

VIN = Vss to Voo

±SO

OSCIN

lose

VIN = Vss to Voo

±SO

VOH

IOH= O~

VOL

IOL=O~

IOH

VOH = 4.6V

-1.0

low-level Output Current

IOL

VOL = 0.4V

1.0

Power Dissipation.!

100

High-level Input Current
low-level Input Current

Except fin
andOSCIN

Max

3.5

\lIH

High-level Input Voltage

Typ

~

~

Input Current

High-level Output Voltage

Except
OSCOUT

low-level Output Voltage
High-level Output Current

Maximum Operating. 2
Frequency

Notes:

Except
OSCOUT

4.95
V
0.05

mA

8.0

mA

REF Section

fmaxd

40

60

MHz

PO Section

fmaxp

95

130

MHz

.1: fin 100MHz, 22MHz cystal is connected between OSC IN and OSCOUT pins.
Inputs are grounded except fin and OSCIN. Outputs are open .
• 2 REF Section: Maximum operating frequency of programmable reference divider.
PO Section: Maximum operating frequency or programmable divider.

3-55

MB87086A

PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M04)

300(762)
TYP
I

I

~'-::- ~- -=:J--,

I

m
.
~nnm··

010:!. .002
(Q.25±005)

i

----I

~~0(1_:27}-:

_

~~~~_5~!

MAX

Ie 1988 FUJITSU LIMITED DI6033S-2C

3-56

II

~

i

17
1

1

2(4361 MAX

11813001 MIN

~

.018±00J-1
T Y P ' (046 ± 0.08)020(0.51) MIN

Dimensions in
inches (rntllimat9r&)

MB87086A

PACKAGE DIMENSIONS (Continued)
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M06)

•

089(225) MAX
i---r(SEATED -HEIGHT) i

002 (0051 MIN

~

,
307' 016
)(780' 040)
209, 012
(530' 030)

I
050(127)

!

rip

®~DOF~

g6~ (6

268

I

_---+ .020 - 008

I; .018
-~O~
-1L
-·~r::0"1-:4>-;:0""0-;:-5-;-;:(0;-:.1;-;:3;-;-):EJ-:-M;-'
(045-010) _.

--l.006 - .002 10 15 • 0.05 1
001
·0.02

-------------1
Details of "A" part

:~

I

:

MAX
027(068)

I

,

M_A_X_____ ,

L ____ • __

C 1990 FUJITSU LIMITED F16015S-2C

: Details of "B" part :

:

" .. :
i 004 (0.1 QL.J '

1-350(889) REF --i

1--------------,
: ¥.006(015 1 :

rennnmq
:
C>.

gigl

,---t (050 - 020)

"A"

i

80 -

I

I

;

,008(0201:
I

:

007(018)

I

MAX
027(068)

L________~~~ __ .!

Dimensions in
inches (miI~met8rs)

3-57

3-58

cO

January 1991

FUJITSU

Edition 3.0
DATA SHEET

MB87087
CMOS PLL FREQUENCY SYNTHESIZER
CMOS SERIAL INPUT PHASE-LOCKED-LOOP (PLL)

III

FREQUENCVSVNTHES~ER
The Fujitsu MB87087, fabricated in CMOS technology, is a serial input phase locked loop
(PLL) frequency synthesizer.
The MB87087 contains an inverter for oscillator, programmable reference divider (binary
14-bit programmable reference counter), 14-bit shift register, 14-bit latch, phase detector,
charge pump, 17-bit shift register, 17-bit latch, programmable divider (binary 7-bit swallow
counter, binary 10-bit programmable counter) and control generator for dual modulus
prescaler.
When supplemented with a loop filter and VCO, the MB87087 contains the necessary circuit
to make up PLL frequency synthesizer. Typically, a dual modulus prescaler such as the
MB501 L can be added, allowing input frequency operation up to 1.1 GHz.
•

Wide range power supply voltage:
Vee = 3.0 to 6.0V

•

Wide temperature range:
T,,= -40 to 85°C

•

17MHz typical input capability
@5V (fin input)

•

On-chip inverter for oscillator

• Binary 14-bit programmable reference counter
•

•
•

•

Programmable divider with input amplifier consisting of:
• Binary 7-bit swallow counter
• Binary 10-bit programmable counter
Programmable reference divider with
input amplifier consisting of:

PLASTIC PACKAGE
DIP·16p·M04

Divide factor of programmable divider
and programmable reference divider
are set by serial data input (The last
data bit is a control bit)

PLASTIC PACKAGE
FPT·16p·M06

2-types of phase detector output
• On-chip charge pump output
• Output for external charge pump

•

Easy interface with Fujitsu prescalers

•

16-pin standard dual-in-line package
(MB87087P)
16-pin standard nat package
(MB87087PF)

ABSOLUTE MAXIMUM RATINGS (see NOTE)

PIN ASSIGNMENT

OSCIN

16

~R

OSCOUT

15

~V

fv

14

NC

Raling

Symbol

Value

Unit

Power Supply Voltage

Voo

Vss -C.5 to Vss +7.0

V

Voo

13

fr

VIN

Vss -C.5 to Voo +0.5

V

Do

12

M

VOUT

Vss -C.5 to Voo +0.5

V

Vss

11

LE
Data
Clock

Input Voltage
Output Voltage
Output Current

loUT

±10

mA

LD

10

Operating Temperature

T"

-40 to +85

°C

fin

9

TSTG

-55 to +125

°C

Po

300

mW

Storage Temperature
Power Dissipation

NOTE:

Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

This device rontains cllcurtry to proted the inputs against
damage due to high statlcvo~ag8S or el8C111C fields. However.
rt is adVised that normal precautions be taken to avoid
application of any vohage higher than ma.irrum rated
voltages to this high impedance circuit.

Copyright ©'991 by FUJITSU LIMITED

3-59

MB87087
MB87087 BLOCK DIAGRAM

r-----------,I

I

14-bit Shift Register

I
I
:JI

~------~

""''''''''~I'''T'''I'''T'''I'''',.,..,....

Programmable
Reference Divider
Binary 14-bit
Reference Counter

IIr---------~~--~----------~~~--~

r------,
I
I

3-60

Control Register

I
I

I "'--_.......r"""!_......_

I
I
I
I
IL _ _ _ _ _ _ _ _

.......,...._ _ _ _ _. . - .

I

I
I
I
I
_ _ _ _ _ _ _ _ _ _ _ _ .JI

MB87087

PIN DESCRIPTION
Description

PinHO.

Symbol

flO

1

OSCIN

I

2

OSCOUT

0

Output pin for crystal oscillator.
Output of the inverting amplifier. This pin should be open when an external oscillator is used.

3

fv

0

Monitor output of the phase detector.
This pin is tied to the programmable divider output.

4

Voo

-

Power supply voltage input.

0

Three-state charge pump output of phase detector.
The mode of Do is changed by the combination of programmable reference divider output frequency
fr. and programmable divider output frequency fv as listed below:
fr> fv:
Drive mode (Do = High level)
High impedance
fr= fv:
Sink mode (00= Low level)
fr < fv:

5

Do

Input pin for crystal oscillator.
Input to the inverting amplifier that forms part of the oscillator.
This pin receives the oscillator signal as AC coupled when an external oscillator is used. For large
amplitude signals (standard CMOS levels) DC coupling may also be used.

6

Vss

-

Ground.

7

LD

0

Output of phase detector.
It is high level when fr and fv are equal. and when the loop is locked.
Otherwise it outputs negative pulse signal.

8

fin

I

Clock input for programmable divider.
This input contains internal bias circuit and amplifier. The connection with an external dual-modulus
prescaler should be an AC connection.

9

Clock

I

Clock signal input for 17-bit shift register and 14-bit shift register.
Each rising edge of the clock shifts one bit of the data into the shift registers.

10

Data

I

Serial data input for programmable divider and programmable reference divider.
The last bit of the data is the control bit. Control bit determines which latch is activated. The data
stored in the shift register is transferred to the 14-bit latch when the bit is high. and to 17-bit latch when
low.

11

LE

I

Load enable input with internal pull up resistor.
When this pin is high (active high). the data stored in shift register is transferred to 14-bit latch or 17-bit
latch depending on the control bit data.

12

M

0

Control output for an external dual modulus prescaler.
The connection to the prescaler should be DC connection. This output level is synchronized with failing edge of input signal fin (pin #8).
Pulse swallow function:
ego MB501L: M = High: Preset modulus factor 64 or 128
M = Low: Preset modulus factor 65 to 129

3-61

MB87087

PIN DESCRIPTION

(Continued)

.

PinHo.

Symbol

13

fr

0

Monitor output of phase detector input.
This pin is tied to the programmable divider output.

14

NC

-

No connection.

15
16

~V

oA

0
0

Output for external charge pump.
The mode of ellA and ~V are changed by the combination of programmable reference divider output
frequency fr and programmable divider output frequency Iv as listed below.

..

........

110

DescriptJon

..

fr> fv:
fr= fv:
fr < fv:

ellA

eIlV

Low-level
High-level
High-level

High-level
High-level
Low-level

...

FUNCTIONAL DESCRIPTION
SERIAL DATA INPUT TIMING
tt -

ts~ 1~s

Data

~ ~ ~~

Control bit

(S2)

(Control bit)

----

Clock

LE

tt

.1.1.

(S1)

lftb

• Data for programmable reference divider.

Notes:

Data: Serial data input is used for setting divide factor of programmable reference divider and progranmable divider. Data is input from
MSB. and last bit data is a control bit.
Control bit is set high when divide factor of programmable reference divider is set. Control bit is set low level when divide factor of
programmable divider is set.
Clock: Data is input to internal shift registers by rising edge of the clock.
LE: Load enable input:
When LE is high. the data stored In shift register is transferred to 14-bit latch. or 17-bit latch depending on the control bit setting.

3·62

MB87087
PULSE SWALLOW FUNCTION
fveo ,. [ (N x M)
fveo

-to

A I x fose

+

A (N > A)

Output frequency of external voltage controlled oscillator (VCO)

N

Preset divide factor of binary 10-bit programmable counter (5 to 1023)

M

Preset modulus factor of external dual modulus prescaler
(e.g. 64 in 64165 mode, 128 in 128/129 mode of an MB50 1L prescaler)

A

Preset divide factor of binary 7-bit programmable counter (0 to 127, A < N)

fose

Output frequency of external oscillator

A

Preset divide factor of binary 14-bit programmable reference counter (5 to 16383)

III

DIVIDE FACTOR OF PROGRAMMABLE REFERENCE DIVIDER
Serial data consists of 14-bit data, which is used for setting divide factor of programmable reference counter, and 1-bit control data. In this case,
control bit is set high level.
The data format is shown below.

LSB

MSB

Data

14-bit
Shift Register

Clock

,
-----------1

14-bit Latch

,

-.-_._ .... _.',
Programmable
Reference
Divider

Binary 14-bit Reference Counter

,

BINARY 14·BIT REFERENCE COUNTER DATA INPUT

@

@

@

@

@

® ® 0

® ® 0

® CD

CD

Divide
Factor

0

0

0

0

0

0

0

0

0

0

0

1

0

1

5

0

0

0

0

0

0

0

0

0

0

0

1

1

0

6

0

0

0

0

0

0

0

0

0

0

0

1

1

1

7

1

1

1

1

1

1

1

1

1

1

1

1

1

1

16383

Note: Divide factor less than 5 is prohibited.
Divide factor: 5 to 16383

3·63

MB87087
DIVIDE FACTOR OF PROGRAMMABLE DIVIDER
Serial data consists of l7-bit data, which is used for setting divide factor of programmable divider, and l-bit control data. In this case, control bit is
set low level. The data

CD to<2) set a divide factor of 7-bit swallow counter and data ® to@set divide factor of 1a-bit programmable counter.

The data format is shown below.

LSB

MSB

Data

l7-bit
Shift Register

Clock

I

I

Binary 7 -bit Swallow Counter

Binary la-bit Programmable Counter

BINARY 7-BIT SWALLOW COUNTER DATA INPUT
<2)

® ®

a
a

0
a

a
a

0

0

0

0

0

0

0

0

a

1

1

1

CD ® ® CD
a
a

Divide
Factor
A

a
a

a
a

a
1

a
1

0

0

1

0

2

a

a

1

1

3

a

1

0

0

4

1

1

1

1

127

Note: Divide factor A: 0 to 127
Depending upon the divide factor set input (SW) of external prescaler, the input data should be as follows.
e.g. MB501L (+65/65)prescaler
SW = H (64/65): Bit 7 to shift registerQ) should be zero.

BINARY 10-BIT PROGRAMMABLE COUNTER DATA INPUT
Divide
Factor
N

@

@

®

@

@

@

@

0
0

0
0

0
0

0
0

a
a

a
a

a
a

1
1

a
1

1
0

5
6

0

0

0

a

0

a

0

1

1

1

7

1

1

1

1

1

1

1

1

1

1

1023

Note: Divide factor less than 5 IS prohibited
Divide factor N .5 to 1023

3-64

® ®

@

Programmable
Divider

I
I

MB87087
PHASE DETECTOR OUTPUT WAVEFORM

III
tv

DO~
eIlR

U

n

High Impedance

U

U

eIlV

LOU

¢

U

U

U

RECOMMENDED OPERATING CONDITIONS
(Vss

= OV)

Unit

Symbol

Power Supply Voltage

Vee

3.0

6.0

V

Input Voltage

V,N

Vss

Vee

V

Operating Temperature

TA

-40

+85

°C

3-65

MB87087

ELECTRICAL CHARACTERISTICS
(Voo = 3.0V, Vss = OV, TA = -40 to 85°C)
Value ......

Ii·
I·. :·

Parameler
.

Symbol

...

..

Low-level Input Voltage

......

..

High-level Input Voltage

V1H
Except fin
and OSCIN

Min

Typ

Max

. . ..<
V

lin

Vlin

OSCIN

Vosc

VooxO.3

Amplitude in AC
coupling, sine wave

0.5
VP. p
0.5

IIH

VIN = Voo

1.0

ill

VIN = Vss

-1.0

fin

lIin

VIN = Vss to Voo

±30

~

OSCIN

lose

V1N = Vss to Voo

±30

~

LE

iLe

VIN = Vss

-40

IlA

VOH

IOH= O~

VOL

IOl=O~

IOH

VOH = 2.6V

IOl

VOL = 0.4V

0.5

IOHM

VOH = 2.6V

~.7

Low-level Output Current

IOLM

VOL = 0.4V

1.5

Power Supply Current

100

Except lin
and OSCIN

Low-level Input Current

Input Current

High-level Output Voltage

Except

IlA

Low-level Output Voltage
High-level Output Current
Except M
and OSCOUT
Low-level Output Current
High-level Output Current

2.95
V

OSCOUT

0.05

~.5

mA

M

.1

mA

2.5

mA

Maximum Operating Frequency of
Programmable Reference Divider

fmaxd

10

20

MHz

Maximum Operating Frequency of
Programmable Divider

fmaxp

10

20

MHz

Notes:

3-66

...:...

.

VooxO.7

V1l

Input Sensitivity

High-level Input Current

..

Condition

.1: fin = 8.0MHz 11.5MHz Crystal is connected between OSC 1N and OSCOUT.
Inputs are grounded except fin and OSCIN. Output are open.

<

MB87087

ELECTRICAL CHARACTERISTICS (Continued)

(Voo = s.ov, Vss = ov, TA = -40 to 85°C)
Value

Parameter

Symbol

Condition

High-level Input Voltage

Unit
Min

..

Typ

Max

VooxO.7

V'H
Except fin

Low-level Input Voltage

andOSC'H

fin

V

Vlin

Input Sensitivity

Amplitude in AC

Vose

VP.p
0.5

ItH

Y,N = Voo

1.0

I.L

Y,N = Vss

-1.0

fin

Ifin

V'N = Vss to Voo

±50

~

OSC 'N

lose

Y,N = Vss to Voo

±50

~

LE

ILE

V,H = Vss

-60

~

VOH

IoH = O~

VOL

IOl= O~

10M

VOH = 4.6V

-1.0

IOl

VOL = 0.4V

1.0

IOHM

VOH '" 4.6V

-1.5

Low-level Output Current

IOlM

VOL = 0.4V

3.0

Power Supply Current .'

100

Except fin

~

andOSC'H
Low-level Input Current

Input Current

High-level Output Voltage

Except

High-level Output Current

4.95
V

OSCOUT
Low-level Output Voltage

Except M

0.05

mA

and OSCOUT
Low-level Output Current

High-level Output Current
M

Maximum Operating Frequency of
Programmable Reference Divider

Maximum Operating Frequency of
Programmable Divider

Note:

III

0.5

coupling. sine wave
OSC'N

High-level Input Current

VooxO.3

V'L

mA

3.5

mA

fmaxd

10

25

MHz

fmaxp

17

25

MHz

.1. fin = 8.0MHz. 11.5MHz Crystal is connected between OSC'N and OSCOUT
Inputs are grounded except fin and OSC,N. Outputs are open.

3-67

MB87087

TYPICAL CHARACTERISTICS CURVE

Input Sevsltlvlty vs. Input Frequency (fin Section)
Voo

=5V, TA =25°C

500

200

100

50
Input Sensitivity
Vlin (mVp.p)

20

10

"'"

I

/

".

5

2

5

10

20

Input Frequency lin (MHz)

3-68

50

100

MB87087

PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M04)

II
.----

INDEX-1

;

I

300(762)

TYP
INDEX-2

~~~
(025±005)

r------------""'\ -

-~----T

~

• 172(4.36) MAX

-- t i
i

1.

118(300) MIN

~--!

050(127)
MAX

020(0.51) MIN

Dimensions in
tC 1988 FUJITSU LIMITED 016033S·2(:

inches (millimelers)

3-69

MB87087

PACKAGE DIMENSIONS (Continued)
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT·16P·M06)

-400'

g~g110

15'

089(225) MAX
HEIGHT)

! (SEATED

g~g)i
i

~

.~~5~F~:N

307'016
11780' 0401
209' 012
1530·030)

.

05011 27)

I

TYP

J.-

'.'

. 268' 016(680'040)
008
020

---+ 020' 008

_ !_I

,----t 10 50 . a 20)

-l

018 .. 004r;;:;-r...,..-;;:."....-:"",.,.....,.,....,

(04~$14>00510131 Mi

006' 002 (0 15 • 0 as)
001'
002

:V

,---------- ---~ ...
: Details of ·'B" part:

~nnoorb~
f
'.. '
i

i

....

II)

1990 FUJITSU LIMITED Fl6015S·2C

©FUJITSU LIMITED 1991

3-70

L;a.1 004(0 lQO
3501889) REF-

16(040):

~

006(0151:
'~
,

~: :

,

!

, Ii

008(020) :

0081020)

:

!

I!

007(018) :
:
MAX
,
:0271068)
, I
MAX'
I
:L
I

-1

i I

007(018)'
MAX - :
027(0.68) :
MAX
______________
I
I

Dimensions in
inches (millimelers)

Printed in Japan PV0130-911A3

00

Sept. 1995

FUJITSU

Edition 4.0a
DATA SHEET

MB87091
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
CMOS SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH POWER SAVING FUNCTION
The Fujitsu MB87091 is a CMOS serial Input Phase Locked Loop (PLL) frequency
synthesizer ideal for use in cordless telephone sets and other radio equipment. It
incorporates an inverter for an oscillation circuit, a programmable reference divider
(14-bit binary programmable reference counter), a shift register control register,
latches, a programmable divider (&-bit binary swallow counter with 12-bit binary
programmable counter and dual modulus prescaler: 64/65), a phase comparator, an
intermittent mode control circuit, and a constanH:urrent charge pump. The power
save control input pin (PS) for the intermittent mode control circuit is used to switch
between the stand by and active modes. This is used for phase synchronization at the
beginning of operation. The MB87091 permits construction of PLL frequency
synthesizers with operating frequencies of up to 300 MHz.

FEATURES
•
•
•
•
•
•
•
•

Single power supply voltage: VDD =2.7 to 3.3V
Built-in inverter for an oscillator
Adjustable output CL:rrent of t:le charge pump with an extemal resistor
Intermittent mode control circuit
Two phase comparator outputs (for external and internal charge pumps)
Wide operating temperature range (TA) -40°C to 60°C
Plastic DIP ackage(Suffix: -P), Plastic SOP package(Suffix: -PF),
Plastic SSOP package (Suffix: -PFV)
Setting the divide ratio
Use the below formula to define the parameters for setting the divide ratio
fun= eN x M +.A) x (tcsa + B)
(N)A)
(fvco) Output frequency of the extemal VCO
(N) Preset divide ratio of 12-bit binary programmable counter (5 to 4,095)
(M ) Preset modulus of the dual modulus prescaler (64)
(A) Preset divide ratio of 6-bit binary swallow counter (0 to 63)
(fose) Output frequency of the external reference frequency oscillator
(R) Preset divide ratio of 14-bit binary programmable reference counte
(5 to 16,383)

ABSOLUTE MAXIMUM RATINGS (See NOTE)

NOTE:

II

•

(FPT.16P·M06)

•

(FPT·20P·M03)

(Vss=OV)

Permanent device damage may occur ifthe above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in
the operational sections of tnis data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

This device contains circuitry to protect the Inputs against
damage due to high static voltages or electric fields. However, HIs advised thet normal precautions be taken to avoid application of any voltage higher than maximum rated voltagea
10 this high Impadance circuli.

CopyrIght© 1994 by FWITSU LIMITED and FUJITSU MICROELECTRONICS, INC.

3·71

MB87091

BLOCK DIAGRAM OF MB87091
(This block diagram is for DIP/SOP packages.)

Ir.-----------,
Programmable Reference Divider I
I
14-bit Binary
I
I
Programmable
I
Reference Counter

D

3-72

Control Register

MB87091

PIN ASSIGNMENT

(TOP VIEW)

(TOP VIEW)
Vss

Voo

Clock

2

OSCIN

Data

3

OSCOUT

Voo

Vss

Clock

2

NC

3

OSCIN
18

NC

LE

4

Data

4

fiN

5

12

FC

LE

5

16

TEST

PS

6

11

P

fiN

6

15

FC

LD

7

10

R

PS

7

14

P

RC

NC

8

13

NC

LD

9

12

R

Do

10

11

RC

Do

8

TEST

9

(DIP-16P-M04)

III

OSCOUT

(FPT-16P-M06)
(FPT-20P-M03)

3·73

MB87091

PIN DESCRIPTIONS
Pin No.
DIPI
SOP

Pin Name

VO

SSOP

Description

1

1

Voo

-

Power supply pin

2

2

Clock

I

Clock input to the shift register
Each rising edge of the clock shifts one bit of the data into the shift register. The
input portion contains a Schmitt trigger circuit.

-

3

NC

-

No connection

3

4

Data

I

Serial data input for programmable divider and programmable reference divider

4

5

LE

I

The input portion contains a Schmitt trigger circuit.
Load Enable signal input pin
A high on this pin transfers the contents of the shift register into the latch. The
latched data provides the divide ratios of the dividers. The input portion contains a
Schmitt trigger circuit.

5

6

fiN

I

Input to the programmable divider
The input portion contains a bias circuit and an amplifier. This pin is connected to
an external voltage controlled oscillator (VCO) with an AC coupling.

6

7

PS

I

Power save control input pin
A high on this pin places the MB87091 into the active mode and a low into the stand
by mode. The PS pin has to be set low at power-on time (see Section 1.1,
"Intermittent Operation," in "Functional Descriptions").

-

8

NC

-

7

9

LD

0

No connection
Phase comparator output pin
The LD pin outputs high when the PLL is locked and low when the PLL is unlocked.

8

10

Do

0

Phase comparator output pin
The output current of this charge pump is adjustable with external resistor RRC.
The Do output may be inverted by the FC input. The relationships between the
programmable reference divider output (fr) and the programmable divider output
(fp) are shown below:
fr> fp: "W level (FC = "L"), "L" level (FC = "W)
fr= fp: High impedance
fr < fp: "L" level (FC = "L"), "W level (FC = "H")

9

11

RC

-

Connect pin with an external resistor RRC

10

12

R

0

Phase comparator output pin (for external charge pump)

(see Section 1.4, "Phase Comparator" in "Functional Descriptions")

The relationships between the programmable reference divider output (fr) and the
programmable divider output (fp) are shown below:
When FC "L"
fr> fp: R = "L" level
fr = fp: R = "L" level
fr < fp: R = "W level
When FC ="W
fr > fp: R = "H" leve
fr = fp: R = "L" level
fr < fp: R = "L" level

=

-

3-74

13

NC

-

No connection

MB87091

PIN DESCRIPTIONS (Continued)
Pin No.
DIPI
SOP

SSOP

11

14

Pin Name

1/0

P

0

Description
Phase comparator output pin (for external charge pump)
Ij>P is an N-channel, open-drain output. The relationships between the
programmable reference divider output (tr) and the programmable divider output
(fp) are shown below:
When FC ="L"
fr> fp: q,P ="L" level
fr =fp: lj>P = High impedance
fr < fp: lj>P =High impedance
When FC ="H"
fr> fp: cpP =High impedance
fr =fp: cpP =High impedance
fr < fp: cpP = "L" level

12

15

I

FC

III

Phase comparator input selector pin
(see Section 1.4, "Phase Comparator" in "Functional Descriptions")

13

16

TEST

I

This is used to enable test mode
A high on this pin places the MB87091 into the test mode. As this pin is provided
with a pull-down resistor, it should be left open as a rule. The pin is used for
shipping tests and not used for normal operation.

14

17

OSCOUT

0

-

18

NC

-

No connection

OSC'N

I

Crystal oscillator connect pin

15

19

Crystal oscillator connect pin

A crystal oscillator is connected between the OSCIN and OSCOUT pins. It can clock
input to OSCIN from the external. In this case, the OSCIN pin must be AC coupled
and the OSCOUT pin must be left open.
16

20

Vss

-

Ground pin

3-75

MB87091

FUNCTIONAL DESCRIPTIONS
1.

Circuit Description

1.1

Intermittent Operation

The intermittent operation of the M887091 refers to the process of activating and deactivating its internal circuit as necessary thus
saving power dissipation otherwise consumed by the circuit. If the circuit is simply restarted from the stand by state, however, the
phase relationship between the reference frequency (fr) and the programmable frequency (fp), which are the input to the phase
comparator, is not stable even when they are of the same value. This may cause the phase comparator to generate an excessively
large error signal, resulting in an out-of-synch lock frequency.
To preclude the occurrence of this problem, the M887091 has an intermittent mode control circuit which forces the frequencies into
phase synchronization with each other when the M887091 is reactivated, thus minimizing the error signal and resultant lock
frequency fluctuations. The intermittent mode control circuit is controlled by the PS pin. Setting the PS pin high provides the normal
operation mode and setting the pin low provides the standby mode and places the M887091 into the standby state. The M887091
behavior in the active and standby modes is summarized below:

=

•

Active mode (PS "H")
All M887091 circuits are active and provide the normal PLL operation.

•

Standby mode (PS ="L")
The circuits that consume power heavily, and cause little inconvenience when deactivated, run down and the M887091 enters the
low power dissipation state. The Do, A, P, and LD pins take the same state as when the PLL is locked. The Do pin becomes
high-impedance state and the input voltage to the voltage controlled oscillator (VCO) is maintained at the same level as in the
active mode (lock state) according to a time constant of a low pass filter (LPF). Consequently, the output frequency from the VCO
(fvco) is maintained at approximately the lock frequency.
The M887091 continues the intermittent mode operation by alternating the active and standby modes. When it switches from
standby to active mode, it forces the phase of fr and fp to correspond to minimize the error signal. In this way, the M887091 can
keep the power dissipation of its entire circuitry at the minimum.
The M887091 must be placed into the standby mode (PS

="L") when it is powered on.

1.2 Programmable Divider
The fvco input through the fiN pin is divided by the programmable divider and then output to the phase comparator as fp. It consists of a
dual modulus prescaler, a 6-bit binary swallow counter, a 12-bit binary programmable counter, and a controller which controls the
divide ratio of the prescaler.
Divide ratio range:
•
•

=

=

Prescaler: M 64, M+ 1 65
Swallow counter: A =0 to 63
Programmable counter: N =5 to 4095

The M887091 uses the pulse swallow method; consequently, the divide ratios of the swallow and programmable counters must
satisfy the relationship N > A.
The total divide ratio of the programmable divider is calculated as follows:
Total divide ratio =(M+ 1)xA+Mx(N-A) = MxN+A =64xN+A
When N is set within 5 ::; N ::; 63, the possible divide ratio A of the swallow counter can take values 0 ::; A ::; N-1 because N must be

=

greater than A. For example, 0::; A::; 19 is allowed when N 20, but 20::; A::; 63 is not allowed in that case. Consequently, N 2:: 64 must
be satisfied for the total divisor to be set within 0 ::; A ::; 63.
The fp and fiN pins have the following relationship:
fp = fiN + (64 x N + A)

3-76

MB87091
1.3 Programmable Reference Divider
The programmable reference divider divides the reference oscillation frequency (fosc) from the crystal oscillator connected between
the OSCIN and OSCOUT pins or from the external oscillator input taken in directly through the OSCIN pin. It then sends the resultant frto
the phase comparator. It consists of a 14-bit binary programmable reference counter. When the output from the external oscillator is
to be input directly to OSCIN, the pin connection must be AC coupled and the OSCOUT pin is left open. Also, to prevent OSCOUT from
malfunctioning, its traces on the printed circuit board must be kept minimal or eliminated entirely; whenever possible, it must be free of
any form of load.
The following divisor is used:
•

Programmable reference counter: N ::: 5 to 16383

The fr and fose have the following relationship:
•

III

fr::: fose + R

1.4

Phase Comparator

The phase comparator detects the phase difference between the outputs fr and fp from the dividers and generates an error signal that
is proportional to the phase difference. The outputs from the phase comparator include 1) Do which takes on one of the three states,
"L" (low), "H" (high), or "Z" (high impedance), and is sent to the LPF, 2) cj>R, 3) cj>P, and 4) LD which indicates the Pll lock or unlock
state.

1.4.1

Phase Comparator

The phase comparator detects the phase difference between fr and fp and generates an error signal that is proportional to the phase
difference. The roles of the fr and fp supplied to the phase comparator may be reversed by switching the logical input level on the FC
pin; this inverts the logical level on the Do output. The logical level on the Do output may be selected according to the characteristics of
the external LPF and the VCO. (Refer to Table 1.)
Table 1. Phase Comparator Inputs/Output Relationships

~

FC="L"

FC="H"

Relationship

Do

cj>R

cj>P

Do

q,R

q,P

fr > fp

H

L

L

fr =fp
fr < fp

Z

L
L
H

Z
Z

Z

H
L
L

Z
Z

L

H

L

1.4.2 Charge Pump
The charge pump is available in two forms: internal and external.
• Internal constant-current charge pump output (Do)
• External charge pump outputs (cj>R, cj>P)
The output current at the Do pin from the internal constant-current charge pump is controlled by varying the external resistance (RRC)
connected between RC and GND, as shown in Figure 1.

, . . . . - - - - - . To fiN

LD
, . -_ _-, ~

10L

t----LJDo
L -_ _....

¢:::I

10H

External Resistor
RRC

3·77

MB87091
1.4.3 Phase Comparator Input/Output Waveforms
The phase comparator outputs the logic levels summarized in Table 1, according to the phase difference between the fr and fp phase
differences. Note that q,P is an N-channel open drain output. The pulse width of the phase comparator outputs are identical and equal
to the phase difference between fr and fp, as shown in Figure 2.

Figure 2.

fr

-fl

fp

When FC="L"
Do

I
I
I
I
I
I
I
I
I

q,R

q,P

n

n
n in n
I I
I I

I
I
I

I I
I I
I I

I
I
I
I
I
I

I
I
I
I
I
I
I
I
I

i

I
I

~
I
I
I
I
I

I
I
I

-w

When FC="H"
Do

I
I
I
I
I
I
I
I

--n

q,R

q,P

Phase Comparator Input/Output Waveforms (Charge Pump)

J-i

HI
I
I
I
I
I
I
I
I

W
I

I
I
I
I
I

I
I
I
I

W
I I

H

I
I
I
I

I
I
I
I
I
I
I
I
I

I

I
I
I
I
I
I
I
I

I

I
I
I
I
I
I

I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I

fL
I

hI
I
I
I

LJ
I I
I

I

II

I

I

I

n
U

High Z

I

I

HighZ

I
I
I
I

I

High Z

I
I

I
I
I

I

HighZ

High Z :High impedance state
q,P
:N-channel open drain output

3-78

MB87091
1.4.4 Lock Detector

The lock detector detects the lock and unlock states of the PLL. The lock detector outputs "H" when the PLL enters the lock state and
outputs "L" when the PLL enters the unlock state, as shown in Figure 3. When PS ="L", the lock detector outputs "H" compulsorily.

Figure 3.

Phase Comparator Input/Output Waveform (Lock Detector)

Jl. JLJL
Jl. JLJL

fr

fp

III

..J

LD

2.

Setting the Divide Ratio

2.1

Serial Data Format

The format of the serial data is shown in Figure 4. The serial data is composed of a control bit and divide ratio setting data. The control
bit selects the programmable divider or programmable reference divider.
In case of the programmable divider, serial data consists of 18 bits (6 bits for the swallow counter and 12 bits for the programmable
counter) and 1 control bit, as shown in Figure 4.1. In case of the programmable reference divider, the serial data consists of 14 divisor
bits and 1 control bit, as shown in Figure 4.2.
The control bit is set to 0 to identify the serial data for the programmable divider and to 1 to select the serial data for the programmable
reference divider.

Figure 4.

Serial Data Format

MSB

LSB

~

Ie

A
0

'fr j.---

Direction of data input
A
1

A
2

A
3

A
4

(}

~

A

N

N

N

N

N

N

5

0

1

2

3

4

5

1

NIN
6

7

N

N

N

N

8

9

10

11

Programmable counter

Swallow counter

Control bit
Figure 4.1

-I

Divide ratio for the programmable divider

MSB

LSB

R
3

R
4

R
5

R
6

R
7

R
8

Programmable reference counter
Figure 4.2

-I

Divide ratio for the programmable reference divider

3-79

MB87091
2.2

The Flow of Serial Data

Serial data is received via the data pin in synchronization with the Clock input and loaded into the shift register which contains the
divide ratio setting data and into the control register which contains the control bit. The logical product (through the AND gate in Figure
5) of LE and the control register output (Le., control bit) is fed to the Enable input of the latches. Accordingly, when LE is set high, the
latch for the divider identified by the control bit is enabled and the divide ratio data from the shift register is loaded into the selected
counter(s).

Figure 5.

The Flow of Serial Data

r---------------------------------,I

I
I
I
I

Programmable I
Reference
I
Divider
I
14----------------~

14·bit Binary Programmable Reference Counter

~--------------

14·bit Latch
14
Data D---t--t
la·bit Shift Register
ClockO--~

18

18·bit Latch

LE

• 12 - - - - - - - - - - - ,

I
I .

I
I
I
L
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
I
I

I

Prescaler

Programmable
Divider

~

* : Control Register

2.3

Setting the Divide Ratio for the Programmable Divider

Columns AO to AS of Table 2.1 represent the divide ratio of the swallow counter and columns NO to N11 of Table 2.2 represent the
divide ratio of the programmable counter. The control bit is set to O.

Table 2.

Divide Ratio for the Divider
Table 2.2 Programmable Counter Divisor N

Table 2.1 Swallow Counter Divisor A
Divide
Ratio

3-80

A

A
1

3

A
4

A

0

A
2

A

A
0

0

0

0

0

0

0

1

1

0

0

0

0

0

•
•

•
•

.• .• .• .• .•

63

1

1

1

1

1

5

1

Divide
Ratio

N
0

N
1

N
2

N

N

3

4

N
5

N
6

N
7

N
8

N
9

N
10

N
11

5

1

0

1

0

0

0

0

0

0

0

0

0

6

0

1

1

0

0

0

0

0

0

0

.•

•
•

•
•

.• .•

0

4095

1

1

1

N

1

•
•

..

0

•
•

.•

•
•

•
•

•
•

•
•

1

1

1

1

1

1

1

1

MB87091
2.4

Setting the Divide Ratio for the Programmable Reference Divider

Columns AD-A 13 of Table 3 represent the divide ratio of the programmable reference counter. The control bit is set to 1 .

Table 3.

2.5

Divide Ratio for the Reference Divider

Divide
Ratio
R

R
0

R
1

R
2

R
3

R
4

R

R
6

R
7

R

R

5

8

9

R
10

R
11

R
12

R
13

5

1

0

1

0

0

0

0

0

0

0

0

0

0

0

6

.•

0

1

1

0

0

0

0

0

0

0

0

0

0

0

•
•

•
•

•
•

•
•

•
•

•
•

•
•

•
•

•
•

•
•

•
•

•
•

•
•

•
•

16383

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Serial Data Input Timing

The MB87091 uses 19 bits of serial data for the programmable divider and 15 bits for the programmable reference divider. When
more bits of serial data than are defined for the target divider are received, only the last valid serial data bits are effective.
To set the divide ratio for the MB87091 dividers, it is necessary to supply the Data, Clock, and LE signals at the timing shown in
Figure 6.
t1 (~1 Ils) : Data setup time
t2 (~1 /lS): Data hold time
t3 (~1 /lS): Clock pulse width
t4 (~1 /lS) : LE setup time to the fall edge of last clock
t5 (~1 /lS): LE pulse width

Figure 6.

Serial Data Input Timing

Data

LE

t5

3·81

MB87091
Since the divide ratios are unpredictable when the MB87091 is turned on, it is necessary to initialize the divide ratio for both dividers at
power-on time. As shown in Figure 7, after setting the divide ratio for one divider (e.g., programmable reference divider), set LE to the
"H"level before setting the divide ratio for the other divider (e.g., programmable divider). To change the divide ratio of one divider after
initialization, input the serial data only for that divider (the divide ratio for the other divider is preserved).

Figure 7.

Serial Data for Programmable
Reference Divider

Data

Clock

LE

Inputting Serial Data (Setting Divisors)

Serial Data for Programmable Divider

15 Clocks

O·

19 Clocks

______

~n~

______

~

* : Control Bit

RECOMMENDED OPERATING CONDITIONS
(Vss=OV)

Symbol

Value

Unit

Supply Voltage

Voo

2.7 to 3.3

V

Input Voltage

YIN

Vss to Yoo

V

Ambient Temperature

TA

-40 to +60

°C

Rating

HANDLING PRECAUTIONS
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly
grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

3-82

MB87091

ELECTRICAL CHARACTERISTICS
(Vee

=3.0V, Vss =OV, TA =-40 to +60°C)
Value

Parameter

Symbol

Conditions

Unit
Min

Input Voltage

Except fiN and
OSCIN

VIH

-

2.1

-

-

L Level

VIL

-

-

-

0.9

-

fiN
OCSIN

Input Current

Vfpp

AC coupling amplitude

1.0

-

VSIN

AC coupling amplitude

1.0

-

H Level

IIH

V IN = Voo

-

1.0

L Level

IlL

V IN = Vss

-

-1.0

IfIN

VIN = Vss to Voo

-

±30

OCSIN

losc

VIN = Vss to Voo

±30

TEST

ITEST

V IN = Voo

2.95

fiN

Except
OSCOUT

0.05

-

-

0.50

VO H = 2.5V

-0.5

-

IOL

VOL = 0.5V

0.5

-

H Level

IOH

VOH = 2.5V

"1

L Level

IOL

VOL = O.SV

"1

VOH

IOH = O~A

L Level

VOL

IOL= OIlA

H Level

VOH

IOH= O~A

L Level

VOL

IOL= O~A

H Level

IOH

L Level

OSCOUT

2.50

Output Current

~A

V

-1.0

-

1.0

-

1.0

mA

mA

cpPOnly

IOFF1

VOUT = Vss to Voo

Do Only

IOFF2

VOUT=VO O

Active Mode

looop

"2

-

8

16

mA

loos

"3

-

10

-

/-LA

40

-

-

300

-

-

Cutoff Current

Supply Current
Standby Mode
REF Section

fMAXd

Programmable Reference
Divider

PO Section

fMAXP

Programmable Divider

Maximum Operating Frequency

*3:

I1A

V

2.0

-2.0

Vp_p
Sine

-

-

Do Only

*1:
*2:

50

V

-

H Level

Output Voltage

Except
OSCOUT, Do
&cpP

Max

H Level

Input Sensitivity

Except fiN,
OSCIN & TEST

Typ

~A

MHz

RRC = 5 k.Q
fiN 300 MHz, 12.8 MHz crystal is connected between OSCIN and OSCOUT pins, RRC 5 kn
Inputs are connected to GND, except tiN, OSCIN, and TEST. Outputs are open.
Current consumption at PS ="L". Inputs are connected to GND, except fiN, OSCIN, and TEST pins.
Outputs and the RC pin are open.

=

=

3-83

MB87091

TYPICAL APPLICATION EXAMPLE
Voo

MB87091
Mieroeontroller
Cloekl----------......;;.~

Data 1--_ _ _ _ _ _ _ _ _--1

LE

12.8MHZ

15pF

15pF

;J;

PS

;J;

1000pF

r------------,
LPF
R2
C1
I

I
I
I
I

R1

I
I
I

~RRe

,,15kD.
1---.------ fveo

Package: DIP, SOP

3-84

'PAGE INiENiIONALL'l
lEfT Bl~N\(

3-85

MB87091

PACKAGE DIMENSIONS (CONTINUED)
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M06)
.089(2.25)MAX
(MOUNTING HEIGHT)

I

,002(0.05)MIN
(STAND OFF HEIGHT)

-+---'-j

I
.307±.016
(7.80±0.40)

INDEX

o

/
"6"

.268 ~:gJ~ (6.80 ~:~g)

.209±.012
(5.30±0.30)

~;;::::;::;:::::;:;::::;:;:::::r:;:~:;:?1 ~
'i

.050(1.27~ I
TYP

,~.'

'-$-'

.018±.004
.,II!. (0.45±0.10)

I

"A"

0.005(0.13)@)

===tI

II
--4i--

,

01.004(0.,011'

r--

.350(8.89) REF - -

.006~:gg~ (O.15~:g~)

y= T'5

r - o;t;I~f7."N-p;rt- , , - o;t;I~f7B:-P;rt-,
.016(0.40)11

G

.02O±.OOB
(0.5o±ut pin, and has a bias circuit and an alJ1)lifier. Connection with an extemal
osciUator should be AC coupling.

8

LD

0

Lock signal output pin. This pin is high when a loop is locked. This pin is low when the loop is alA
of lock.

9

PS

I

Power save control pin. When PS is high, an active mode is selected. When PS is low, a standby
mode is selected.'

10

ASW2

Cornmon pin of the analog switches.

11

COMM

-

12

ASW1

-

Analog switch 1.

13

Do

0

T~slate output pin of the charge pump. The charge PUIJ1) outpuIlevel is changed according to
combination of the R-divider output frequency" and the N-divider output frequency tv.

14

NC

-

No conneclion

15

STBY

0

This pin ~s low when the standby mode is selected. When a signal is input to Rin pin after the
active mode is selected, this pin outputs high.

Voo

-

Power s~y pin.

16

Note:

Pin Description

III

Analog switch 2.

, Refer to an Intermittent operation In functional description in page 4.

3-91

MB87093A
MB87095A
MB87096A

FUNCTIONAL DESCRIPTIONS
1

Intermittent Operation

The intermittent operation of every MB87093A1MB87095A1MB87096A refers to the process of activating and deactivating its
internal circuit for saving power disSipation. If the circuit is simply restarted from the standby state. however. an excessively large
error signal might be generated. resulting in an out-of-synch lock frequency. Because the phase relationship between the reference
frequency (fr) and the frequency (tv) is not stable even when they are of the same value.
To preclude this problem. every MB87093A1MB87095A1MB87096A has an intermittent mode control circuit which forces the
frequencies fr and fv into the same phase other than when the MB87093A1MB87095A1MB87096A are reactivated. this minimizing
the error signal and resultant lock frequency fluctuations. The intermittent mode control circuit is controlled by the PS pin. Setting the
PS pin high provides the active mode. and setting the PS pin low provides the standby mode and places the MB87093A1MB87095A1
MB87096A into the standby state.
The MB87093A1MB87095A1MB87096A must be placed in the standby mode (PS .. -L1 when power is impressed.

2

Input sensor

The STBY pin outputs in the standby mode. and outputs high after receiving a signal via Rin pin when the mode switches from the
standby mode into the active mode.
For example. it is possible to control a VCO by this function.

3

N-dlvlder

The tvco of an extemal VCO output Signal input through fin is divided by the N-divider and then output to the phase comparator as
tv. It consists of a binary 10-bit N-counter. The divide ratio N of the N-divider for each MB87093A1MB87095A1MB87096A is shown
in Table 1.
Table 1. N-dlvlder's Dlvtde Ratio N

4

Part Number

Divide Ratio N

MB87093A

725

MB87095A

550

M887096A

750

R-dlvlder

The R-divider divides the reference oscillation frequency (fosc) from an external reference oscillator (TCXO). and output fr to the
phase comparator. It consists of a binary 6-bit R-counter. Table 2 shows the R-divider'S divide ratio.
Table 2. R-dlvlder's Dlvtde Ratio R

5

Part Number

Divide Ratio R

MB87093A

64

MB87095A

64

MB87096A

128

Phase Comparator

The phase comparator detects the phase difference between the outputs fr and fv and generates an error signal that is proportional
to the phase difference. The outputs from the phase comparator include 1) Do which takes one of the three states; namely. -L" (Low).
-W (high). and ·Z· (high-impedance). 2) LD which indicates the PLL lock or unlock state.

3-92

MB87093A
MB87095A
MB87096A
5.1

Phase Comparator

The phase comparator detects the phase difference between fr and tv and generates an error signal that is proportional to the phase
difference. Table 3 shows logical levels of Do and LD according to the phase relationship between fr and tv.
Table 3. Phase Comparator Inputs/Output Relationships
Output

5.2

III

LD

Phase Relationship

Do

fr>fv
fr=fv
fr'

DS04-21213-1aE

~~~~~~~~~~~ET~~ruJIBU
MB87094 ASSP
Serial Input PLL Frequency Synthesizer

II

CMOS SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH POWER SAVING FUNCTION
The Fujitsu MB87094 is a CMOS serial input Phase Locked Loop (PLL) frequency
synthesizer. It incorporates an Input amplifier, a programmable divider (binary
11-bit programmable counter and binary 7-bit swallow counter), a phase
comparator, a charge pump, an oscillator circuit, a programmable reference
divider (binary 12-bit programmable reference counter), a shift register/control
register, a data latch, an intermittent mode control circuit. A power save control
input pin (PS) forthe intermittent mode control circuit is used to switch between the
stand-by and active modes. This is used for phase synchronization at the
beginning of operation from a stand-by mode. The MB87094 permits construction
of PLL frequency synthesizers with operating frequencies of up to 15 MHz.

FEATURES
•

Low power supply voltage: VDD =1.1 to 1.7V
VooH =2.6 to 3.3V

•

Intermittent mode control circuit

•

Ambient temperature range: TA = -10°C to 50°C

•

Plastic 16-pin SSOP package (Suffix: -PFV)

•

Setting the divide ratio
Use the below formula to define the parameters for setting the divide ratio

fYCQ.= (N x M+ A) x (fQSC + B)

•
(FPT-16P-M05)

(N)A)

(fY.CQ..) Output frequency of the extemal veo
(N) Preset divide ratio of binary11-bit programmable counter (5 to 2047)
(M) Preset modulus of external dual modulus prescaler (M/M+ 1)
(A) Preset divide ratio of binary 7-bit swallow counter value (0 to 127)
(fQS.Q) Roference oscillator frequency
(B) Preset divide ratio of binary 12-bit programmable reference counter
(5 to 4035)

This device contalna circuitry to protect th.lnputs agalnal dam
age due to high static voltages or electric fielda. However, It Ia
advised that normal praceutiona be taken to avoid application of
any voltage higher than maximum rated voltages to this high impedance circuit.

Copyright©l994 by FUJITSU UMIEO and FUJITSUMICROElECTRONICS, INC.

3-99

MB87094

PIN ASSIGNMENT
(TOP VIEW)

16

VDD

GND

fIN

2

15

RIN

Clock

3

14

fv

Data

4

13

fr

LE

5

12

Test

VooH

6

11

M

Do

7

10

FC

PS

8

9

LD

0

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating_
Supply Voltage
Input Voltage
Output Voltage

Output Current

Value

Voo

-0.5 to +5.0

VooH

-0.5 to +5.0

V

VIN

-0.5 to Voo+0.5

V

VINH

-0.5 to VooH+0.5

V

VOUT

-0.5 to Voo+0.5

V

VouTH

-0.5 to VooH+0.5

V

lOUT

±10

mA

Unit
V

Ambient Temperature

TA

-10 to +50

°C

Storage Temperature

Tstg

-40 to +125

°C

Po

300

mW

Power Dissipation
NOTE:

3-100

(GND=OV)

Symbol

Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

MB87094

PIN DESCRIPTIONS
1

Pin
Name
Voo

-

1V

Power supply pin

2

fiN

I

1V

Programmable divider input pin
This pin has a bias circuit and an amplifier. Connection with an external voltage controlled oscillator (VCO) should be AC coupling.

3

Clock

I

3V

Clock input pin for the shift register
Data are loaded at the rising edge of the clock. A Schmitt trigger circuit is used.

4

Data

I

3V

Serial data input pin for setting divide ratio of dividers
A Schmitt trigger is used.

5

LE

I

3V

Load enable signal input pin
When LE is set to high, the data in the shift register is sent to the latch. A Schmitt
trigger is used.

Pin No

*1

Description

I/O Interface

6

VooH

-

3V

Power supply pin

7

Do

0

3V

Tri-state charge pump output pin
A constant-current feed charge pump is used and its output current can be controlled
by the external resistor RRC. The Do output level is inverted by FC. The charge pump
output level is changed according to the combination of the programmable reference
divider output frequency (fr) and the programmable divider output frequency (fv).

8

PS

I

3V

Power save control pin
When PS is set to "H", an active mode is selected. When PS is set to "L", a standby
mode is selected. *2

9

LD

0

3V

Phase comparator output pin
When a PLL is locked, this pin outputs "H". When the PLL is unlocked, it outputs "L".

10
11

FC
M

I

0

3V
3V

Phase comparator input switch pin *3
Control output for external dual modulus prescaler
This output level is synchronized with the falling edge of the fiN input signal
Pulse swallow function:
M "H" : Preset modulus factor M of an external prescaler
M "L" : Preset modulus factor M+ 1 of an external prescaler

II

=
=

12

Test

I

1V

Test mode pin
The test mode is selected by setting this pin to "H". Leave this pin open for ordinary
operation, because a pull-down resistor is used.

13

fr

0

1V

Monitoring pin for the programmable reference divider output

14

fv

0

1V

Monitoring pin for the programmable divider output

15

RIN

I

1V

Connect pin with extemal reference oscillator (TCXO, etc.).
A bias circuit and an amplifier are used. Connection with TCXO should be an AC
coupling.

16

GND

-

-

Ground pin

Note:
*1 : In consideration of the interface with external circuits like a microcontroller, each pin is set to either 3V interface or
1V interface.
*2: When power is impressed, the PS pin has to be set to "Ln. Refer to an intermittent operation in the functional
description.
*3 : Refer to the phase comparator in the functional description.

3-101

MB87094

BLOCK DIAGRAM
MB87094 BLOCK DIAGRAM

Voo

fiN

1)

'r-~ -- -I
.----

Clock

Data

LE

3T<)--

r- L-

Schmitt
Circuit

5)-

ry

1
Programmable
Reterence Divider
112

3-102

8

I rl

~~
Output
Control

RIN

1~

tv

-(B

fr

~~

Test

~L
Control Rregister (1 bit)
+ Shift Register (18 bits)

-

118

-f

r
IL

Output
Control

Latch (18 bits)

1

18

VooH 6)

PS

Phase
Comparator

fv

{12

Programmable
Divider

7

~~

Latch (12 bits)

'"--

Do

~~ GND

Intermittent
Operation
Control
Circuit

I
I

I

Charge Pump

r--

11

M

J

I

1~ FC

I

L/

Lock Detector

9

LD

MB87094

FUNCTIONAL DESCRIPTIONS
1.

Circuit Description

1.1 Intermittent Operation
The intermittent operation of the MB87094 refers to the process of activating and deactivating its internal circuit as necessary thus saving
electric energy otherwise consumed by the circuit. If the circuit is simply restarted from the standby state, however, the phase relationship
between the reference frequency (fr) and the programmable frequency (fv), which are the input to the phase comparator, is not stable
even when they are of the same value. This may cause the phase comparator to generate an excessively large error signal, resulting in an
out-of-synch lock frequency.
To preclude the occurrence of this problem, the MB87094 has an intermittent mode control circuit which forces the frequencies into phase
with each other when the MB87094 is reactivated, thus minimizing the error signal and resultant lock frequency fluctuations. The
intermittent mode control circuit is controlled by the PS pin. Setting the PS pin high provides the normal operation mode and setting the pin
low provides the standby mode and places the MB87094 into the standby state. The MB87094 behavior in the active and standby modes
is summarized below.
•

Active mode (PS = "H")
All MB87094 circuits are active and provide the normal PLL operation.

•

Standby mode (PS = "L")
The MB87094 stops every circuit that consumes power heavily and that causes little inconvenience when deactivated and enters the
low-power dissipation state. The Do and LD pins take the same state as when the PLL is locked. The Do pin becomes a
high-impedance state and the input voltage to the voltage control oscillator (VCO) is maintained at the same level as in the active
mode (that is, lock state) according to a time constant of a low pass filter (LPF). Consequently, the output frequency from the VCO
(fvco) is maintained at approximately the lock frequency.
The MB87094 continues the intermittent mode operation by alternating the active and standby modes. When it switches from standby
to active modes, it forces the phase of fr and fp to correspond and minimize the error signal. In this way, the MB87094 can keep the
power consumption of its entire circuitry at the minimum.
The MB87094 must be placed in the standby mode (PS = "L") when power is impressed.

1.2 Programmable Divider
The fvco of an external VCO output signal or the fpsc of a prescaler output signal, input through fiN, are divided by the programmable
divider and then output to the phase comparator as fv. It consists of a binary 7-bit swallow counter, binary 11-bit programmable counter,
and a controller which controls the divide ratio of the prescaler.
The following are their divide ratios:
• Swallow counter: A = 0 to 127
• Programmable counter: N = 5 to 2047
The MB87094 uses the pulse swallow method; consequently, the divide ratios of the swallow and programmable counters must satisfy the
relationship N > A.
On the supposition that the divide ratio of a prescaler is M/M+ 1 (M=128), the total divide ratio of the programmable divider is calculated as
follows:
Total divide ratio = (M+ 1)xA+Mx(N-A) =MxN+A = 128xN+A
When N is set within 5::; N::; 127, the divide ratio Aofthe swallow counter can take values O::;A::; N-1 because N must be greater than A.
For example, 0::; A::; 19 is allowed when N =20 but 20::; A $127 is not allowed in that case. Consequently, N;:: 128 must be satisfied for
the total divide ratio to be set within 0 $ A ::; 127.

3-103

3

MB87094
1.3 Programmable Reference divider
The programmable reference divider divides the reference oscillation frequency (fosc) from an external reference oscillator (TCXO)
connected with AC coupling, and outputs fr to the phase comparator. It consists of a 12-bit binary programmable reference counter.
The following divide ratio is used:
• Programmable reference counter: R :: 5 to 4095
The fr and fosc have the following relationship:
• fr= fosc + R

1.4 Phase Comparator
The phase comparator detects the phase difference between the outputs fr and fv and generates an error signal that is proportional to the
phase difference. The outputs from the phase comparator include 1) DO which takes on one of the three states, "L" (low), "H" (high), or 0Z'
(high impedance), and 2) LD which indicates the PLL lock or unlock state.

1.4.1 Phase Comparator
The phase comparator detects the phase difference between tr and tv and generates an error signal that is proportional to the phase
difference. The roles of the fr and fp supplied to the phase comparator may be reversed by switching the logical input level of the FC pin.
This inverts the logical level of the DO output. The logical level of DO may be selected according to the characteristics of the external LPF
and the VCO. (Refer to Table 1.)

Table 1. Phase Comparator InputS/Output Relationships

~

Relationship

tr> tv
tr =tv
tr < tv

FC="L"

FC="H"

DO

DO

L

H
High-Impedance

L

H

1.4.2 Phase Comparator Input/Output Waveforms
The phase comparator outputs logic levels summarized in Table 1, according to the phase difference between fr and tv phase
differences. The pulse width of the phase comparator outputs are identical and equal to the phase difference between fr and fv as
shown in Figure 1.

fr

-D
I
I
I
I
I

fv

n
n in
I I

I

W:FC="L~
When FC="H"
Do

I
I
I
I

I
I
I
I

--u

I I
I I

H
I
I
I
I I

U

n
n
I

I
I
I
I
I
I
I

flI

rL

~
I

n

HighZ

I
HighZ

High Z : High impedance state

Figure 1. Phase Comparator Input/Output Waveforms (Charge Pump)

3-104

MB87094
1.4.3 lock Detector
The lock detector detects the lock and unlock states of the PLL. The lock detector outputs "H" when the PLL enters the lock state and
outputs "L" when the PLL enters the unlock state as shown in Figure 2. When the pulse width of the error signal is kept zero for four (4)
clocks, the lock detector outputs "H" as a lock signal. When it detects a phase difference after the PLL is locked, "L" is output at once.

JL
JL

fr

fv

II

LD

Figure 2. Phase Comparator Input/Output Waveform (Lock Detector)

2.

Setting the Divide Ratio

2.1 Serial Data Format
The format of the serial data is shown in Figure 3. The serial data is composed of a control bit and divide ratio setting data. The control bit
selects the programmable divider or the programmable reference divider.
In the case of the programmable reference divider, serial data consists of 12 bits forthe programmable reference counter and 1 control bit,
as shown in Figure 3.1. In the case of the programmable divider, the serial data consists of 18 bits (7 bits for the swallow counter and 11
bits for the programmable counter) and 1 control bit, as shown in Figure 3.2.
The control bit is set to 0 to select the serial data for the programmable divider and to 1 to select the serial data for the programmable
reference divider.
MSB

LSB

Figure 3.1 Divide Ratio for the Programmable Reference Divider
LSB

MSB

Swallow Counter

"I-

Programmable Counter

..

I

Figure 3.2 Divide Ratio for the Programmable Divider

Figure 3. Serial Data Format

3-105

MB87094
2.2 The Flow of Serial Data
Serial data is received via the data pin in synchronization with the Clock input and is loaded into the shift register which contains the divide
ratio setting data and into the control register which contains the control bit. The logical product (through the AND gate in Figure 4) of LE
and the control register output (Le., control bit) is fed to the Enable input of the latches. Accordingly, when LE is set high, the latch for the
divider identified by the control bit is enabled and the divide ratio data from the shift register is loaded into the selected counter.

r---------------------------------,I

I
I
I
I

Programmable
Reference

12-bit Binary Programmable Reference Counter

L ______________

~~M

I
I
I

12----------------~

12-bit Latch
12
Data 0---+--1
18-bit Shift Register
Clock 0--1-1
18
18-bit Latch

LE

11 - - - - - - - - - - - ,

I

I
I
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ I
Programmable
Divider

~

~ :Control Register

Figure 4. The Flow of Serial Data
2.3 Setting the Divide Ratio for the Programmable Divider
Columns AO to A6 of Table 2.1 represent the divide ratio of the swallow counter and columns NO to N 10 of Table 2.2 represent the divide
ratio of the programmable counter. The control bit is set to O.

Table 2. Divide Ratio for the Programmable Divider
Table 2.2 Programmable Counter Divide ratio N

Table 2.1 Swallow Counter Divide ratio A

Divide
Ratio

A

A

A

3

4

A
5

A

1

A
2

A

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

•
•

.•

•
•

.. .•

0

1

1

1

1

A

.• .•
127

3-106

1

1

6

Divide
Ratio

N
0

N

N

N
4

N
5

N
8

N

6

N
7

N

2

N
3

N

1

9

10

5

1

0

1

0

0

0

0

0

0

0

0

6

1

1

0

a

a

a

0

a

a

a

•
•

•
•

1

1

N

•
•

..

0

•
•

.• .•

•
•

•
•

.•

•
•

.. ..

1

2047

1

1

1

1

1

1

1

1

1

MB87094
2.4 Setting the Divide Ratio for the Programmable Reference Divider
Columns RO-R 11 of Table 3 represent the divide ratio of the programmable reference counter. The control bit is set to 1.

Table 3. Divide Ratio for the Programmable Reference Divider
Divide
Ratio
R

R
0

R
1

R
2

R
3

R
4

R
5

R
6

R
7

R
8

R
9

R
10

R
11

5

1

0

1

0

0

0

0

0

0

0

0

0

6

0

1

1

0

0

0

0

0

0

. ..
•

4095

1

•
•

. ..

0

•
•

.. .• ..

0

•
•

..

0

•
•

..

1

1

1

1

1

1

1

1

1

1

•

1

III

2.5 Monitor Mode
Setting both the PS pin and TEST pin high, the monitor mode is available. The fr and tv pins typically output low. In the monitor mode, the fr
pin outputs signals from the programmable reference divider, and the fv pin outputs signals from the programmable divider.

2.6 Serial Data Input Timing
The MB87094 uses 19 bits of serial data for the programmable divider and 13 bits for the programmable reference divider. When more
bits of serial data than are defined for the target divider are received, only the last valid serial data bits are effective.
To set the divide ratio for the MB87094 dividers, it is necessary to supply the Data, Clock, and LE signals at the timing shown in Figure 5.
t1 (~1 JlS)
t4 (~1 JlS)

:Data setup time
t2 (~1 Ils): Data hold time
:LE setup time to the falling edge of the last clock

(~1 Ils): Clock pulse width
t5 (~1 Ils): LE pulse width

t3

Data

Clock

LE

t5

Figure 5. Serial Data Input Timing

3-107

MB87094
Since the divide ratios are unpredictable when the MB87094 is turned on, it is necessary to initialize the divide ratio for both dividers. As
shown in Figure 6, after setting the divide ratio for one divider (e.g., programmable reference divider), set LE to the "H" level before setting
the divide ratio for the other divider (e.g., programmable divider). To change the divide ratio of one divider after initialization, input the
serial data only for that divider (the divide ratio for the other divider is preserved).

Serial Data for Programmable
Reference Divider

Data

Clock

LE

Serial Data for Programmable Divider

13 clocks

______

O·

19 clocks

~n~

______

~

* :Control bit
Figure 6. Serial Data Setting Procedure

RECOMMENDED OPERATING CONDITIONS
GND= OV
Parameter
Power Supply Voltage

Symbol

UNIT
V

VooH

2.6 to 3.3

V

VIN

GND to Voo

V

VINH

GNDto VooH

V

TA

-10to +50

°C

Voo

Input Voltage
Ambient Temperature

Value
1.1 to 1.7

HANDLING PRECAUTIONS
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti·ESD precautions. Ensure that personnel and equipment are properly grounded. Cover work·
benches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

3-108

MB87094

ELECTRICAL CHARACTERISTICS
(VooH = 3.0V, Voo = 1.1 V, GND = OV, TA = -10 to +50°C)

Value
Parameter

Symbol

Conditions
Min

TEST

CLK, Data,
LE,PS,FC

H Level

VIH

-

0.77

-

-

L Level

VIL

-

-

-

0.33

H Level

VIH

-

2.10

-

-

L Level

VIL

-

-

-

0.90

V

fiN

Vfpp

AC Coupling Amplitude

0.5

-

-

RIN

VSIN

AC Coupling Amplitude

0.5

-

-

IIH

VIH = VOOH

-

1.0

-

ilL

VIL= GND

-

-1.0

-

fiN

IfIN

VI = GND to Voo

-

±30.0

-

~

RIN

lose

VI = GND to Voo

-

±30.0

-

~

TEST (pull down pin)

/rEST

VIH = Voo

-

SO.O

-

~

H Level

VOH

IOH=O~

1.0S

-

-

L Level

VOL

10L = OJlA

-

-

0.05

H Level

VOH

10H=0~

2.95

L Level

VOL

IOL = OJlA

-

0.05

H Level

10H

VOH = 0.6V

-0.2

-

L Level

IOl

Val = O.SV

0.2

-

-

H Level

IOH

VOH = 2.SV

-0.4

-

VOL = O.SV

0.4

-

-

mA

L Level

IOL
IOFFH

VOH = VOOH

-

100

nA

IOFFL

VOL

-

-

100

nA

-

-

1.0

mA

-

-

20.0

~

Input
Sensitivity

H Level

CLK, Data,
LE,PS,FC
Input
Current

fr, fv

Do, LD, M

fr, fv
Output
Current

Max
V

Input
Voltage

Output
Voltage

Unit

Typ.

Do, LD, M

Cutoff Current

L Level

Do
Active Mode

lop

=GND

*1

Supply Current
Stand-by Mode
Maximum Operating
Frequency

REF Section
PO Section

IS6
fMAXd
fMAXp

*2
Programmable
Reference Divider
Programmable Divider

II

Vtr-P
Sine

~

V

-

-

lS

-

-

15

-

-

V

mA

MHz

Note;
*1: fiN = RIN = lSMHz(O.SVpp), lop = 100 (l.4V) + looH (3V) x 3.3
*2: Conditions for measuring the standby current (Iss) are the same as the case of the active mode (lop).

3-109

MB87094

TYPICAL APPLICATION EXAMPLE

Voo

Micro
controller

TCXO

Clock
Data

LE

VooH

PS

3-110

MB87094

.
·
.
n

16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M05)

.049+.008

OO~ (MOUNTING HEIGHT)

h

I

(1.25~:~g)

[7 : .004(0.10)

I

I

1

I

I

III

.2S2±.008
I

(6.4D±0.20)

*.173±.004

.213(5.40) NOM

I

(4.4D±O.10)

1.·.i< ···' • •. ~e~~~i\i,
Sym})oJ 1/
)i
'.,' .• ,

..

fOUT

,', ..'

Vee

NC

Vee

-0.5 to +5.0

V

Do

FC

Vp

Vee to 8.0

V

GND

-0.5 to Vee +0.5

V

LD

Data

-0.5 to 6.0

V

fiN

Clock

±10

mA

-55 to +125

°C

Output voltage

Vo

Open drain voltage

Voop

Output current

10

Storage temperature

Tstg

NOTE:

. ". .

Vp

P

0

Phase comparator output for an extemal charge pump
Phase of the output is reversed depending on FC input.
P pin is a N-ch open drain output.

16

R

0

Phase comparator output for an extemal charge pump
Phase of the output is reversed depending on FC input.
R pin is a C-MOS output.

III

4-7

MB15A01

FUNCTION DESCRIPTIONS
Pulse swallow function
The divide ratio can be calculated using the following equation:
fveo =[(P x N) + A] x fose + R (A < N)
fveo : Output frequency of external voltage controlled oscillator (VCO)
N
: Preset divide ratio of binary H·bit programmable counter (5 to 2,047)
A
: Preset divide ratio of binary 7·bit swallow counter (0 S A S 127)
fose : Output frequency of the reference frequency oscillator
R
Preset divide ratio of binary 14·bit programmable reference counter (6 to 16,383)
P
: Preset divide ratio of modules prescaler (64 or 128)

Serial data input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the 15·bit programmable reference divider and 18·bit
programmable divider separately.
Binary serial data is entered via the Data pin.
One bit of data is shifted into the internal shift register on the rising edge of clock. When the load enable pin is high or open, stored data
is latched depending on the control data as follows:
Control data

(a)

Destination of serial data

H

15 bit latch

L

18 bit latch

Programmable reference divider
The programmable reference divider consists of a 16·bit shift register, a 15·bit latch and a 14·bit reference counter. The serial
16·bit data format is shown below:

--_.~

Direction of data shift

Divide ratio setting bit for programmable reference counter

4-8

MB15A01
•

14-bit programmable reference counter divide ratio

Divide ratio
R

S

S

S

S

S

S

S

S

S

S

12

11

10

9

8

7

6

4

3

S
2

S

13

S
5

S

14

6

0

0

0

0

0

0

0

0

0

0

0

1

1

0

7

.

0

0

0

0

0

0

0

0

0

0

0

1

1

•

•

•

. . . . . . . .

1

•

•

.

16383

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

III

(Divide ratio = 6 to 16,383)

Notes: 1. Divide ratios less than 6 are prohibited.
2. SW: This bit selects the divide ratio of the prescaler.
Low: 128 or 129
High: 64 or 65
3. Sl to S14: These bits select the divide ratio of the programmable reference counter (6 to 16,383).
4. C: Control bit: Set high.
5. Start data input with MSB first.

(b)

Programmable divider divide
The programmable divider consists of a 19-bit shift register, a l8-bit latch, a 7-bit swallow counter, and a 11-bit programmable
counter. The serial 19-bit data format is shown below:

-----t..

Direction of data shift

Divide ratio setting bit for
swallow counter

Divide ratio setting bit for programmable counter

4-9

MB15A01
•

7-bit swallow counter divide ratio
Divide
ratio

S

A

S
7

0

1

127

S

S

S

S

S

S

S

S

S

S

18

17

16

15

14

13

12

11

10

9

8

0

0

5

0

0

0

0

0

0

0

0

1

0

1

0

1

6

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

6

0

0

0

0

1

S

1

S

4

S
2

S

•

.....

1

1

1

1

ll-bit programmable counter divide ratio
Divide
ratio
N

S
3

S
5

. .

•

. ......
2047

1

1

1

1

1

1

1

1

•

.

1

1

1

1

1

(Divide ratio =5 to 2,047)

(Divide ratio = 0 to 127)
Notes: 1.
2.
3.
4.
5.

•

..

1

Divide ratios less than 5 are prohibited for 11-bit programmable counter.
51 to 57: These bits select the divide ratio of swallow counter (0 to 127).
58 to 518: These bits select the divide ratio of programmable counter (5 to 2,047).
C: Control bit: (5et low)
5tart data input with M5B first.

Serial data input timing
•

t1
t4

(~100ns):

(~100ns):

Data setup time
t2 (~10oons): Data hold time
LE setup time to the riSing edge of last clock

Data

~
.
--

18=

I

M5B

517

--~10
59
I

,

I

(5W)(*1)
Clock

I

(514)

I

(58)

(57)

(~3OOns):

(~800ns):

Clock pulse width
LE pulse width

--JID<1=
C: Control bit
- - L5B
(51)

(C: Control bit)

JlJL--J1lIL--JUL
rL
"

I,

I

LE

I

t3
ts

I

I
I II

I

I

------t
I

I

t1~

I

•

I

I

ts

I

• 4
I

-I---i-

*1: Bits enclosed in parentheses are used when the divide ratio of the programmable reference divider is selected.
Note:

4-10

One bit of data is shifted into the shift register on the rising edge of the clock.

MB15A01
Relation between the

Fe input and phase characteristics

The Fe pin changes the phase characteristics of the phase comparator. Both the internal charge pump output level (Do) and the
phase comparator output (R, P) are reversed depending on the Fe pin input level. Also, the monitor pin (fOUT) output is controlled
by the Fe pin. The relationship between the Fe input level and each of Do, R, and P is shown below:

FC = High or open
Do

R

P

fOUT

Do

R

fr> fp

H

L

L

(fr)

L

fr< fp

L

H

Z(*1)

(fr)

Z(*1)

L

Z (*1)

(fr)

fr

*1:

FC=Low

=fp

P

fOUT

H

Z(*1)

(fp)

H

L

L

(fp)

Z(*1)

L

Z(*1)

(fp)

High impedance

III

When designing a synthesizer, the Fe pin setting depends on the veo and LPF characteristics.

*: When the LPF and veo characteristics are
similar toeD, set Fe high or open.

*:

When the veo characteristics are similar to
® , set Fe low.

veo
output
frequency

LPF input voltage _

4-11

MB15A01
Phase comparator output waveforms
fr> fp,

fr> fp

--.fl'--__ n

fr

-J

fr =fp

fr< fp

fr< fp

n n n

-H
L

-H
fp
L

H
LD
-

L

----r"',--,..-,-_ :

[FC = "H"]

LJUr----~,

cl»P

1

cl»R

1_,,--I----'n'-------'nL...----:

_ - - 1 - -- . 1 . . . .

---n- -ll-------'r---ll----U--------:

Do

[FC = "L"]

cl»P

cl»R

Do

Note:

4-12

I'

U

U"-----= :
-H

~'----....L-I_____I_~I_

L

---Lt- -li- -----'r---ll-----n-------- :
Phase difference detection range: -21t to +21t

MB15A01

RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol

Value

Unit

Min

Typ

Max

Vee

2.7

3.0

3.5

V

Vp

Vcc

6.0

V

Input voltage

VI

GND

Vee

V

Operating temperature

Ta

-40

-

+85

°C

Supply voltage

Remark

Notes: To protect against damage by electrostatic discharge, note the following handling precautions:
-

Store and transport devices in conductive containers.

-

Use properly grounded workstations, tools, and equipment.

-

Tum off power before inserting or removing this device into or from a socket.

-

Protect leads with conductive sheet, when transporting a board mounted device.

4-13

MB15A01

ELECTRICAL CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)

ii ·. . . . . .

.. . . )·.i.>< ..i



.· . i. . . .. . . . . .

. . . •. :: ...............

Supply current

........
~.

......

......

........................

. . . . . . m..~.............

. .....

lee

-

6.5

...•..........
•. >•

-

r> •.••••......«>
..
..'", A< •
.....................

> •...•....•......••••••••

..>......).>.\

fiN = 1.1 GHz, OSCIN = 12
MHz, Vee = 3.0 V. In locked
state.
AC coupling. The minimum
operating frequency is measured with a 1000pF capacitor connected.

fiN

fiN

"10

-

1100

MHz

OSCIN

fose

-

12

23

MHz

fiN

PflN

-10

-

6

dBm

OSCIN

Vose

0.5

-

-

VIM>

50n

High-level input voltage

Clock, Data,

VIH

Vee xO .7

-

-

V

Low-level input voltage

LE

VIL

-

Vee xO.3

V

\IH

-

1.0

IlA

IlL

-

-

-1.0

IlA

OSCIN

lose

-

±50

IlA

FC,LE

ILE

-

-60

High-level output voltage R,LD

VOH

2.1

-

-

V

Vee = 3 V, IOH = -1.0mA

Low-level output voltage RlP, LD

VOL

-

-

0.4

V

Vcc = 3V, IOL = 1.0mA

High-jmjJedance
Cut off current

Do,,P

IOFF

-

-

1.1

IlA

R,LD

IOH

-1.0

-

mA

Vcc= 3V

RlP, LD

IOL

-

-

1.0

mA

Vcc= 3V

High-level input current
Low-level input current

Data, Clock

input current

Output current

4-14

·i •.•• ••

rnA

Operating frequency

Input sensitivity

.'<.

IlA

Vp = Vee to 6.0V
GND to 6.0 V

V~~p =

MB15A01

TEST CIRCUIT
(FOR MEASURING INPUT SENSITIVITY fin/OSCin)
Vc

0.1
1000p

p·G

~
son %

~

Vp

r r

0.1

~

1000p

r---"'---'---'--'""'"'----,

~ p·G

8 7 6 5 4 3 2 1

%50n

II

9 10 11 12 13 14 15 16

Vcc 2kn
'-----+--- ¢
' - - - - - - -........- - - - - - < ; . ; : : : J

Oscilloscope

Select fout monitor output

4-15

MB15A01

APPLICATION EXAMPLE

Vpx (6V)
10 k
12 k
12 k

] From

a controller

fp

H

L

fr= fp

Z

Z

fr100ns)
t4 (>100ns)

o

Data

Data set up time
12 (>1000ns) : Data hold time
LE set up time to the rising edge of the last clock

Nl1=MSBE~~~ I~~~3
,

o

Clock

CN'.LSB

-----------------

,

---1W1...fW1...
_________....1'. . . .'___

OLE

t3 (>300ns): Clock pulse width
t5 (>800ns): LE pulse width

~
---.
't1'

"

,

rL

; : '

t'

,.. 2....

t~'
3 ""T , ~

t.

-.!'

"'-;

, ,

t5 ...............
, ,

On rising edge of the clock, one bit of the data is transferred into the shift register.

4-25

MB15B01

PHASE DETECTOR OUTPUT WAVEFORM

fr

fp
I

~
I
I
twu

(FC bit =High)

-~- - - Z - -

(FC bit =Low)

00- -

Note:

I

I

twl

'----_ _ _ _---"'1

LD

Do- -

..-",..

-~- - - Z - -

-q------~- ----J-: ------~- ------f ------ r_.
H

J

-d------~- -----9--------~- ------f ------Jr-.
J

• Phase error detection range =-2lt to +2lt
• LD output becomes low when phase error is twu or more.
• LD output becomes high when phase error is twL or less and continues to be so for three cysles or more.
• twL and twL depend on OSCin input frequency.

~25ns. foscin =12.8 MHz)
(e. g. twL ~1250ns. foscin 12.8 MHz)

twu ~8Jtosc (e. g. twu
twL~16lfosc

4-26

J

=

MB15B01

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Symbol
Min

Typ

Unit

Note
Vcc1 =Vcc2

Max

Power Supply Voltage

Vee

2.7

3.0

3.5

V

Input Voltage

VIN

GNO

-

Vee

V

Operating Temperature

Ta

-30

-

+80

°C

HANDLING PRECAUTIONS

II

• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESO precautions. Ensure that personnel and equipment are property grounded. Cover workbenches with grounded conductive mats.
• Always tum the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

4-27

MB15B01

ELECTRICAL CHARACTERISTICS
1< ...«
I

<

iiij···
•.•:....>. .............••...., ...

: .................................

-

"11

.• ·.···.·:>..... i .....

*1

-

7.0(0.1)

.:1

-

100

-

1100

-

12.8

20.0

-10

-

0

dBm

Vosc

0.5

-

-

Vp-p

Data,
Clock
LE,BSC

VIH

VccxO.7+0.4

-

-

IIH

Low-level Input Current

Data,
Clock
LE,BSC

Input Current

OSCIN

-

6.0(0.1)

-

fin

OSCIN

fosc

fin

Pfin

OSCIN

Icc1

PLL 1 section

Icc2

PLL2 & common sections

Power Supply Current

fin

mA

MHz

Operating Frequency

50n

Input Sensitivity

High-level Input Voltage
Low-level Input Voltage
High-level Input Current

High-level Output Voltage

.-

VIL

High-impedance Cutoff
Current

Do,BS

1.0

-

-

ilL

-

-1.0

losc

-

±50

0.4

VOH

Vcc= 3.0V

2.2

VOL

Vcc= 3.0V

-

-

IOFF

-

-

1.1

IOH

-1.0

-

-

IOL

-

-

1.0

-

-2.5

-

LO
Low-level Output Voltage

V
VccxO.3-0.4

LO

~

V

~

mA

Output Current
IOH

Vcc=3.0V

001,2

Analog Switch ON Resistance

mA
RON

*1 : The value in ( ) is power supply current in power saving mode.

4-28

-

50

-

n

MB15B01

TEST CIRCUIT (PRESCALER INPUT SENSITIVITY TEST)

1000pF

Vee 1

PG~

5001
P.G

fr

, . . . - . - + - - - - - - - -........- 0 Oscilloscope

~P,..F_ _ _ _ _-<
son

GND

I

II

MB15B01

P'G1-

10kn

1000pF

son

fp
L....---+-----+--+--+---~u

I

Oscilloscope

O,1~F
'---_~

Controller

4-29

MB15B01

APPLICATION EXAMPLE
Lock Detector
Output

3V

MB15B01

fr

GND

rO.

LD1

BS1

1IlF
Lock Detector

1000pF

Output

Note: C1, C2
Clock, Data, LE

4-30

: depends on a crystal oscillator.
: involves a schmitt circuit.
When input pins are open, please insert the pull down/up resistor individually to prevent oscillation.

MB15B01

PACKAGE DIMENSION
20-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-20P-M03)

.049~:gg:

--I*--~----

(1.25~:~g)

*.256±.004

~6t~~'0~~
INDEX

1

I

I

.252±.008
(6.40±0.20)

cI
~~~~~
(0.65±0.12)

.11.

.OO9~:gg~
(0.22~:Jg)

.213(5.40) NOM

"A"

~'

j

-' ,
'

, r:
;- - - - •• - - • -Details'of

"A; part -. ---. ---,

004
±.004
(0.1 o±o.1 0)

O"1o~

REF

©1991 FUJITSU LIMITED F20012S-2C

(STANDOFF
HEIGHT)

CJJI~.~~~

.230(5.85)

*:This dimension does not include resin protruction.

III

f

I

*.173±.OO4
(4.40±0.10)

.0256±.0047

(MOUNTING HEIGHT)

~

-- -

-- --- --

(O.so±o.201

- -

------------- --

-'

Dimensions in
inches (millimeters)

4-31

4-32

00

September 1995

FUJITSU

Edition 6.0a
DATA SHEET

MB 150 11MB 1501 HIMB1501 L
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 1.1 GHz PRESCALER
The Fujitsu MB1501/MB1501H/MB1501L, utilizing BI-CMOS technology, is a
single chip serial input PLL frequency synthesizer with pUlse-swallow function.
The MB1501 series contain a 1.1 GHz two modulus prescaler that can select either
64/65 or 128/129 divide ratio; control signal generator; 16-bit shift register, 15-bit
latch; programmable reference divider (binary 14-bit programmable reference
counter); 1-bit switch counter; phase comparator with phase inverse function;
charge pump; crystal oscillator; 19-bit shift register; 18-bit latch; programmable
divider (binary 7-bit swallow counter and binary 11-bit programmable counter).

III
PLASTIC PACKAGE
Dlp·16p·M04

The MB1501 operates on a low supply voltage (3V typ) and consumes low power
(45mWat 1.1 GHz).

MB1501 Product Line
Vp
Voltage

Voop
Voltage

Lock up
time

/;>0

i

Output
Width
MB1501
8Vmax
8.5V max Middle speed Middle
Low
MB1501H 10V max 10.0Vmax High speed
High
MB1501L 8Vmax
8.5V max Low speed

High-level LOW-level
Output
Output
Current
Current
Middle
Middle
High
Low
Low
High

High operating frequency: fiN MAX=1.1 GHz (PIN MIN=O.20Vp_p)
On-chip prescaler
Low power supply voltage: 2.7V to 5.5V (3.0V typ)
Low power supply consumption: 45mW (3.0V, 1.1 GHz operation)
Serial input 18-bit programmable divider consisting of:
o Binary 7-bit swallow counter (Divide ratio: 0 to 127)
o Binary ll-bit programmable counter (Divide ratio: 16 to 2047)
• Serial input 15-bit programmable reference divider conSisting of:
o Binary 14-bit programmable reference counter (Divide ratio: 8 to 16383)
o l-bit switch counter (SW) Sets divide ratio of prescaler
• 2types of phase detector output
C On-Chip charge pump (Bipolar type)
o Output for external charge pump
• Wide operating temperature: TA=-40°C to +85°C

PLASTIC PACKAGE
FPT·16p·M06

•
•
•
•
•

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating
Power Supply Voltage
Output Voltage
Open-drain Output

Symbol
Vee
VPH
Vp,VPL
VOUT
VnnPH
voOP,VOOPL

Output Current
Storage Temperature
NOTE:

InllT
TSTG

Condition
MB1501H
MB1501/1501L
MB1501H
MB1501/1501 L

Value

Unit

~.5to+7.0

V

Vee to 12.0
Vee to 10.0
~.5 to Vee +0.5
~.5 to 11.0
~.5to 9.0
±10
-55 to +125

PIN ASSIGNMENT

OSCIN

0R

OSCOUT

0P

Vp

fp

Vee

fr

Do

FC

GND

LE

LD

Data

fin

Clock

V
V
V
mA
°C

This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However, His advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance circuit.

Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Copyri9ht@I994by FUJITSU LIMITED and FUJITSU MICROELECTRONICS,INC.

4·33

MB1501
MB1501H
MB1501L

MB1501/MB1501H1MB1501L BLOCK DIAGRAM

vcc

0-

GND0--

r-----------,
16·8it Shift Register

I
I

~]IillillillilI[~
15·8it Latch

I
LE

I
I
I

16·8it Shift Register

I
I
I

15·8it Latch

11r------------,rr--~~__~~~~--J

13

fr

12

FC

LJlilIillillilIC
r
I
I

I

Programmable
Reference Divider

LD

'

0R

8inary 14·8it
1·bit
Reference Counter SW

0P

r---------------,
19·8it Shift Register
I

I

t-t---;I~

19·8it Shift Register

I

~J]ImI[O]ImI[[~
I
I
II

I

Vp
Charge
Pump

Do

18·8it Latch

11·8it Latch

:]]IillIUlllillIIC__

'---_,--.----..w 14

I

Programmable Divider

I
I
I

--~~~--.. ~~-~~---..I

Clock

4-34

fp

MB1501
MB1501H
MB1501L

PIN DESCRIPTIONS
Pin No.
1
2

Pin Name
OSCIN
OSCOUT

1/0
I

Descriptions

0

Oscillator input.
Oscillator output.
A crystal is placed between OSCIN and OSCOUT.

3

Vp

-

Power supply input for charge pump.

4

Vee

-

Power supply voltage input.

S

Do

0

Charge pump output.
Phase characteristic can be inversed depending upon FC input.

6

GND

-

Ground.

7

LD

0

Phase comparator output.
This pin outputs high when the phase is locked. While the phase difference of fr and fp exists,
the output level goes low.

S

fin

I

Prescaler input.
The connection with an external VCO should be an AC connection.

9

Clock

I

Clock input for 19-bit shift register and 16-bit shift register.
Each rising edge of the clock shifts one bit of data into the shift registers.

10

Data

I

Serial data of binary code input.
The last bit of the data is a control bit. The last data bit specifies which latch is activated.
When the last bit is high level and LE is high-level, data is transferred to 15-bit latch.
When the last bit is low level and LE is high level, data is transferred to 1S-bit latch.

11

LE

I

Load enable input (with internal pull up resistor).
When LE is high level (or open), data stored in the shift register is transferred to latch depending on the control data.

12

FC

0

Phase selecting input of phase comparator (with internal pull up resistor). When FC is low
level, charge pump and phase detector characteristics can be inversed.

13

fr

0

Monitor pin of phase comparator input.
It is the same as programmable reference divider output.

14

fp

0

Monitor pin of phase comparator input.
It is the same as programmable divider output.

15
16

0P
0R

0
0

Outputs for external charge pump.
Phase characteristics can be inversed depending on FC input.
0P pin is an N-channel open-drain output.

4-35

MB1501
MB1501H
MB1501L

FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is input using Data pin, Clock pin and LE pin, The 1S-bit programmable reference divider and 18-bit programmable
divider are controlled respectively.
On rising edge of the clock shifts one bit of the data into the internal shift registers.
When load enable (LE) is high level (or open), data stored in shift resisters is transferred to 15-bit latch or 18-bit latch depending upon
the control bit level.
Control data "H" ; Data is transferred into 1S-bit latch.
Control data "L" ; Data is transferred into 18-bit latch.

PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is
shown below.

- - - - - - -__ Data input
Last data input

First data input

@

S

S

S

S

5

6

7

8

14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO

Divide
ratio
R

S

S

S

S

S

S

S

S

S

S

S

S

S

S

14

13

12

11

10

9

8

7

6

5

4

3

2

1

8

0

0

0

0

0

0

0

0

0

0

1

0

0

0

9

.

0

0

0

0

0

0

0

0

0

1

0

1

•

•

•

•

•

•

•

•

..

0

•

.

0

16383

1

1

1

1

1

1

1

1

1

1

1

Divide ratio less than 8 is prohibited.
Divide ratio R: 8 to 16383
SW: Divide ratio of prescaler setting bit.
SW="H": 64
SW="L" : 128
Sl to S14: Divide ratio of programmable reference counter setting bits (8 to 16383)
C: Control bit (Control bit is set to high.)

4-36

1

•

.

1

1

MB1501
MB1501H
MB1501L

FUNCTIONAL DESCRIPTIONS
PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown below.

.. Data input

Last data input

!

!
C

S

S

1

2

I-

@

First data input

Control bit
.LSB

MSB.!

~ I: I: I: I

S

S

7

8

9

10

S

S

S

S

12

13

14

15

sis Is

16

17

18

Divide ratio of programmable counter
setting bits

Divide ratio of swallow counter
setting bits

7-BIT SWALLOW COUNTER DIVIDE RATIO

sis I~

@

11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO

Divide
ratio
A

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

6

5

4

3

2

1

Divide
ratio
N

S

7

18

17

16

15

14

13

12

11

10

9

8

0

0

0

0

0

0

0

0

16

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

0

1

17

0

0

0

0

0

1

0

0

0

1

•

•

•

•

•

•

•

•

.

0

•

•

•

•

•

•

•

•

•

•

•

127

1

1

1

1

1

1

1

2047

1

1

1

1

1

1

1

1

1

1

1

Divide ratio A : 0 to 127

Divide ratio less than 16 is prohibited.
Divide ratio N : 16 to 2047

S8 to S18 :Divide ratio of programmable counter setting bits (16 to 2047)
Sl to S7: Divide ratio of swallow counter setting bits (0 to 127)
C: Control bit (Control bit is set to low.)
Dara is input from MSB data.

4-37

MB1501
MB1501H
MB1501L

SERIAL DATA INPUT TIMING

S9

S 1=LSB
(S1)

----

X

C: Control bit

(C: Control bit)

....

On the rising ed!ile of the clock shifts one bit of the data into the shift registers.
Parenthsis data IS used for setting the divide ratio of the programmable reference divider.

PHASE CHARACTERISTICS
VCO CHARACTERISTICS
FC pin (pin 12) is provided to inverse the phase comparator
characteristics. The characteristics of internal charge pump output
(Do), phase detector outputs (0R,0P) can be inversed depending
upon FC input data. Outputs are shown below.

o>z

FC=H (or open)
Do

0R

0P

W
:::::I

FC=L
Do

0R

oW

0P

fr>fp

H

L

L

L

H

Z

fr

VCO INPUT VOLTAGE _

MB1501
MB1501H
MB1501L

RECOMMENDED OPERATING CONDITIONS
Parameter

Value

Symbol

Vee
Power Supply Voltage

Min

Typ

2.7

3.0

Max
5.5

VPH

MB1501H

Vee

10.0

Vp, VPL

MB1501
MB1501L

Vee

8.5

VOOPH

MB1501H

Vee

10.0

V~~p, VOOPL

MB1501
MB1501L

Vee

8.5

Open-drain Output

Unit

V
V

V

Input Voltage

V1N

GND

Vee

V

Operating temperature

TA

-40

+85

°C

4-39

MB1501
MB1501H
MB1501L

ELECTRICAL CHARACTERISTICS
(Vee=2.7 to 5.5V, TA=-40 to +85°C)
Parameter
Power Supply Current

Pin Name

Symbol

Condition

Vee

Icc

*1

fin

fiN

*2

Operating Frequency
OSCIN

fose

Value
Min

Typ

-

15

10

-

-

12

High-level Input Voltage
Low-level Input Voltage
High-level Input Current
Low-level Input Current

Low-level Output Voltage
N-channel Open-drain
Cutoff Current
High-level Output Current
Low-level Output Current

MHz

20

MHz

-10

-

6

dBrn

Pfin2

Vee=4.0 to 5.5V

-4

-

6

dBrn

-

Vp_p

-

V

VIN

0.5

-

Except
fin and
OSCIN

VIH

0. 7xVec

-

VIL

-

-

Data,
Clock

IIH

-

1.0

-

JlA

IlL

-

-1.0

-

JlA

OSCIN

liN

-

±50

-

JlA

LE,FC

ILE

-

-60

-

JlA

Except
Do and
OSCOUT

VOH

2.4

-

-

V

-

-

0.4

V

0P

10FF

-

-

1.1

JlA

Except
Do and
OSCOUT

10H

-1.0

-

-

rnA

1.0

-

-

rnA

Vec=3.0V
VOL

Low-level Output Current

Do,0P

Vee~Vp~8V

10L

0. 3xVec

V

~DOHH

Vee=3V
MB1501H
Vp=12V,TA=25°C

-2.2

-4.5

-

rnA

'DOH

MB1501

-0.5

-2.0

-

rnA

IOOHL

MB1501L

-0.5

-1.1

IOOLH

Vee=3V
MB1501H Vp=12V, TA=25°C

2.2

6.0

-

rnA

IDOL

MB1501

1.5

6.0

-

rnA

'OOLL

MB1501L

4.5

12.0

-

rnA

'1.0

JlA

Do

looz

Vee=3V
Vp=6V, TA=25°C

Vee=3V
Vp=6V,TA=25°C

MB1501H Vee=3V, Vp=12V
TA==25°C
MB1501
Vee=3V, Vp=9V
MB1501L TA=25°C

Note: *1 Vce=3.0V, fIN=1.1GHz, fose=12MHz crystal.
Inputs are grounded except fiN, and outputs are open.
*2 Input coupling capaCitor 1000pF is connected.

4·40

1100

OSCIN

High-level Output Current

Leakage Current

mA

Vee=2.7 to 4.0V

Input Current

High-level Output Voltage

-

Unit

Pfin1
fin
Input Sensitivity

Max

-

-2.2

rnA

MB1501
MB1501H
MB1501L

TYPICAL CHARACTERISTICS CURVES
CHARGE PUMP CHARACTERISTICS
•

MB1501/MB1501H

•

MB1501L

Vp

Vp

Do

Do

GND

GND

LOCK UP TIME MEASUREMENT

(

1V1div

t

J

~

10ns/div

Low unlock condition ---. Lock (533MHz)

High unlock condition - - . Lock (518MHz)
~

1\

1/
I--

/

MB1501H

,J
I"

t

1/, r

if'/'

J..ooo-

Ir

~

'\

J.ooo-

~~~

~L\

.~~
~

V
MB1501L

.

~

V

~

-......

A ~~

~

I'

DO PIN OUTPUT CURRENT CURVES (TYPICAL)
VOH vs. 10H

~

8.0

::t:
0

"-

>

Q)

0>

VOL vs. 10L

,
,,

~ 2.0
..J

0

>

\

.i!!

g

M81501L

:;
.9- 7.0
::J

MB~501

_ MB1501H _

0>

M81501L _

.i!!

g
I--

I

0

MB1501
MB1501H

Q)

-

~ 1.0
:;
0

Q)

>

Q)

1.:
0>
I

~

>

~

:?:

0

...J

0.0

6.0
0

-3
-1
-2
-4
High-level Output Current 10H (rnA)

-5

0

---

.i

10
Low-level Output Current 10L (rnA)

20

4-41

MB1501
MB1501H
MB1501L
Do PIN OUTPUT WAVEFORM AT LOCK CONDITION
Output Waveform

1V/div
(

IL-_ _....

J

100ns/div

MB1501

J

I

~

Ir"

MB1501H

--

-

--

--1--

--1--

--

----

r

MB1501L

---- -- --1/- --I- - • - J

---- --

4-42

----

'I

--

-

--

MB1501
MB1501H
MB1501L
PHASE CHARACTERISTICS (M vs. Do OUTPUT ENERGY)
150

~

100

0" V"

L/"/

50

~r

:>
I

C!:!:!.

100

>-

c:
w

~

O

e>
Q)

80

40

60

1-

MB1501H
- - MB1501
- - - MB1501L

l
J

/

-150

,,'

W

°r~O

20

-50

-100

~: '/

20

I

,,"

80

,,------ .-------

/"

/~

60

.JII'

,--

TIme.1f (ns)
Vp

Te

o

°k

0'1
SCI loscope

10k

VCC=VP=3.0V ~
flNSfosc=12MHz
[ f,.=fp=46.9kHz

(-) Energy

4-43

MB1501
MB1501H
MB1501L
INPUT SENSITIVITY
Input Sensitivity vs. Input Frequency (Supply Voltage Dependence)
E
m
:!:!.

+10

z

0

.2;:~

-10

ti:
-i5

cQ)

(J)

S

a.
.E

-20

....
- rt-

I

Vee=S.5V

~--

Operating Area
Vcc=4.0 to S.SV

II

Vcc=2.7 to 4.0V

1;;"'---

-30
I ...........

-40

~

-----

-

-~

~

"
-~
\

.......!!!!

~~

1\

VIC 2.7V

Vee=4.5V

-50
1.0

1.1

1.2

1.3
1.4
1.5
1.6
Inp.ut Frequency fin (GHz)

1.7

1.8

1.9

....---_-0 Vee

;J; O.1J.lF

a-p

000PF

P.G

Oscilloscope
(Counter)

14

8

50n

6

Input Sensitivity vs. Input Frequency (Temperature Dependence)
E
m

~

0

ti:

-10

z

~
~
cQ)

.ii)

-20

(J)

-30

Sa.

.E

-f==:::::

+10
~

G
••,". . .
Operating
Area
~c_c=..4.~ ~ :.S:'
Vcc=2.7 to 4.0V

~

I

0

- TA=-4.0 C

1\,

,

\

~~

-

-~ ~
11

~

TA +25°C

TA +85°C

::=::; -",,-

-40
-50
1.0

1.1

1.2

1.3
1.4
1.5
1.6
Input Frequency fin (GHz)

<> Vee=3.0V

a-p
P.G

OOOPF

50n

4-44

1.7

1.8

1.9

....---..._-0 Vee

;J; 0.1J.lF

8

14
6

'---.,.....--'

Oscilloscope
(Counter)

MB1501
MB1501H
MB1501L
INPUT IMPEDANCE

lOMHz
lOOMHz

~,~~,....

200MHz

500MHz
.q;;~~~~Pl-W--l()OO MHz

TEST CIRCUIT
Do Pin Output Current (lo H • lad Measurement

Vee

Vp

MB1501

4-45

MB1501
MB1501H
MB1501L
Lock up Time Measurement

Oscilloscope (10MQ, 10pF)

LPFCircuit
1kil

4kil

~Tw.,
1k'o

10llF

Vcc=3~Vp=8V

fvco=Low unlock condition
( fvco=High unlock condition

)

- + Step to Lock condition (533MHz)
- + Step to Lock condition (518MHz)

Phase Characteristics Measurement

10kil

OSCin

-----10k'o

fin
fp

Vcc=3V, Vp=3V
.1f=fr-fp
( Energy (En)=V 2t

4-46

-----------

Oscilloscope
(10MQ, 10pF)

1

MB1501
MB1501H
MB1501L

TYPICAL APPLICATION EXAMPLE
Vpx(6V)

_--_OUTPUT

Charge Pump Selection
(Internal or external)

FROM
CONTROLLER

~}
16

FC

0P

0R

15

13

14

12

III

47kQ

LE
11

10

6

7

MB1501

2
OSCou

5

4

3
Vp

Vee

Do

GND

8
LD

1000pF
6V

Vec(3V)

3V

LOCK DET.

Cl, C2: Depends on crystal oscillator
LE,FC: With internal pull up resistor
0P
Open drain output

4-47

MB1501
MB1501H
MB1501L

PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No.: DIP-16P-M04)

1S 0 MAX

-t

INDEX-1

"
INDEX-2

.244±.010
: (6.2o±O.25)

~:::;::=;=::::;::=::;:=::;==;:=:;:=;:::::;:::::;::=;=;::::::;==:;,J: ~
.1

I.. 039~012
(0.99~·30)

©1991 FUJITSU LIMITED D16033S-2C

4-48

i
.300(7.62)

TYP

rff~t
I

I'

_1
~-':::::::::::-l_

.1 l.o.o~12

(1.S2~·30)

.01o±.002
(O.2S±o.OS)

Dimensions in
inches (millimeters)

MB1501
MB1501H
MB1501L

PACKAGE DIMENSIONS
1S-LEAD PLASTIC FLAT PACKAGE
(Case No.: FPT-1SP-MOS)

4~ ~gri~ (10 15~~g) ~+_ _ _ _

.089(2.25)MAX
MOUNTING HEIGHT)

-y-

I

~~~===~~--r

I
INDEX

0

.307±.016
(7.80±0.40)

1

/

TI
IT--rw

I

~I

.268

I

.209±.012
(5.30±0.30)

"8"

'J..-+---t.----'[--lr-lr--H'~:lr------l.J· ~
I

.050(1. 27

TYP

11

I, ..

•

J

II

.018±.004 'I'--~""'-'-I-----'I
II, .. (0.45±0.10)L:c.......L-~-·0-0-5(-0.-13-)
=C9~

"A"

--

i

.002(0.05)MIN
(STAND OFF HEIGHT)

t
I

~:g6~ ~:~g)
(6.80

d

.02o±.008
(0.50±o.20)

•

+. 002 (015+ 0 .05 )
. -0.02

~. 006 -.001

Det;;I~~A-;;-p;rt -, ~

H

-

Dei~il~~8-;;-p;rt - ~

.016(0.40):1 1

fn5

006(0 15)

i

:1)8)1,

, .008(0.20) I i i

.

.008(0.20) 1

I'

II I
.007(0.18)
II .! ... 007(0.18) I
MAX
I
I
•
MAX
.027(0.68)
::
027(0.68)
_ _ _ _ _ ~~ _ _ J L _ _ _ _ ~~ _ _ J

-i-- •.

©1991 FUJITSU LIMITED F16015S-2C

Dimensions in
inches (millimeters)

4-49

I

j
j
j
j
j
j
j
j
j
j
j
j

4-50

00

==D~SO~4-2~13~21~-1a~E~1~~~~~~~=========---_FUJITSU

==

DATA SHEET

MB15A02 ASSP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER

LOW POWER SERIAL INPUT PLL
SYNTHESIZER WITH 1.1 GHZ PRESCALER
The Fujitsu MB15A02, utilizing Bi-CMOS technology, is a single chip serial input
PLL synthesizer with pUlse-swallow function.
The MB 15A02 contains a 1.1 GHz two modulus prescaler that can select either a
64/65 or 128/129 divide ratio, control signal generator, 16-bit shift register, 15-bit
latch, programmable reference divider (binary 14-bit programmable reference
counter), 1-bit switch counter, phase comparator with phase reverse function,
charge pump, crystal oscillator, 19-bit shift register, 1S-bit latch, and programmable
divider (binary 7-bit swallow counter and binary 11-bit programmable counter).
It operates supply voltage of 5V typo and achieves very low supply current of 7mA
typo realized through the use of ~ujitsu Advanced Process Technology.
• High operating frequency: fiN MAX=1.1GHz (PIN MIN=-10dBm)
• Pulse swallow function: 64/65 or 128/129
• Low supply current: lce=7mA typo
• Serial input 18-bit programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 16 to 2,047
• Serial input 15-bit programmable reference divider consisting of:
- Binary 14-bit programmable reference counter: 6 to 16,383
- 1-bit switch counter (SW) sets divide ratio of prescaler
• Two types of phase detector output
- On-chip charge pump (Bipolar type)
- Output for external charge pump
• Wide operating temperature: -40°C to +85°C
• 16-pin Plastic SOP Package
16-pin and 2O-pin Plastic SSOP Packages

II
PLASTIC PACKAGE
FPT-16P-M05

PLASTIC PACKAGE
FPT-16P-M06

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating

Symbol

Rating

Unit

Power Supply Voltage

Vee
Vp

-0.5 to +7.0
VcctoS.O

V

Output Voltage

VOUT

-0.5 to Vcc +0.5

V

Open-drain Voltage

Voop

-0.5 to 6.0

V

Output Current

lOUT

±10

rnA

Storage Temperature

TSTG

-55 to +125

°C

Remark

V
0Ppin

NOTE: Permanent device damage may occur if the above Absolute Maximum
Ratln~s are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

PLASTIC PACKAGE
FPT-20P-M03
This device contains circuitry to protect the inputs against
damage due to high static voHagas or electric fields. However, it is advised that normal precautions be taken to avoid
applicetion of any voltage higher than maximum rated
voltages to this high impedance circuit

Copyright © FUJITSU LIMITED and FUJITSUMICROELECTRONICS, INC.

4-51

MB15A02

PIN ASSIGNMENT

OSCIN

0R

0R

NC

NC

OSCOUT

0P

OSCOUT

0P

Vp

fOUT

Vp

fOUT

NC

Vee

NC

FC

Do

FC

LE

GND

LE

Top View
GND

Data
fin

LD

Data

NC

NC

Clock
fin
(FPT-16P-M06)
(FPT-16P-M05)

4-52

Clock

(FPT-20P-M03)

MB15A02

BLOCK DIAGRAM

r

MONITOR
FREQUENCY
CHANGING
CIRCUIT

PROORAMMABLEREFERENCef'l

Il DIVIDER
I BINARY 14-BIT

I
I

I-+----+l~

14 fOUT

II

fr

REFERENCE COUNTER

vcc8

rJ1U1U1Ull __,
.J

1

15-BIT LATCH

- -_ 15-BIT
__
___ 1
1
LATCH

L ___________

LE 11 } - - - - - - H

rJ1U1U1Ull __ ,
I
1

19-BIT SHIFT REGISTER

1

19-BIT SHIFT REGISTER

1

_-_
.
'-----C---'
r

-

-

....

-

-

-

-

-

-

-

12 FC

..

~VP

0

00

LrnrOrOTOTnT.J

r-----------,
1
1S-BIT LATCH
1
1

7-BIT LATCH 111-BIT LATCH

II

LrnrnrnTnT+1T.J

Note: Pin numbers are based on SOP/SSOP 16-pin packages.

4-53

MB15A02

PIN DESCRIPTION
Pin No.
Pin Name
SOP-16P
SSOP-16P SSOP-20P

4-54

110

Description

I
0

Oscillator input.
Oscillator output.
A crystal is placed between OSCIN and OSCOUT.
Power supply pin for charge pump. When the internal charge pump is not
used, Vp pin needs to be connected to Vee.

Vcc

-

Do

0

Charge pump output.

7

GND

-

Ground.

7

8

LD

0

8

10

fiN

I

9

11

Clock

I

10

13

Data

I

Binary serial data input.
The last bit of data is a control bit. When this bit is high level, the data stored
in shift register is transferred to 15-bit latch. When this bit is low level and LE
is high level, the data is transferred to 18-bit latch.

11

14

LE

I

Load enable input (with internal pull up resistor).
When LE is high, the data stored in shift register is transferred into latch according to the control bit.

12

15

FC

I

Phse select input of phase comparator (with internal pull up resistor).
When FC is low level, the characteristics of phase comparator is reversed.
FC input signal is also used to select fout pin (test pin) output, fr or fp.

13

2,9,12,16,19

NC

-

No connection

OSCIN
OSCOUT

1
2

1
3

3

4

Vp

4

5

5

6

6

Power supply pin.

Phase comparator output.
Normally this pin outputs high level. When there is a phase error between fr
and fp, LD becomes low for the period corresponding to the error.
Prescaler input.
The connection with an external VCO should be AC connection.
Clock input for 19-bit shift register and 16-bit shift register.
On rising edge of the clock shifts one bit of data into shift register.

14

17

fOUT

0

Minitor pin of phase comparator input.
fout pin outputs either programmable reference divider output (fr) or programmable divider output (fp) according to FC pin input level.
FC=H: It is the same as fr output level.
FC=L: It is the same as fp output level.

15

18

!ZIP

0

Outputs for external charge pump.
The characteristics are reversed according to FC input.
0P pin is N-channel open drain output.

16

20

0R

0

Outputs for external charge pump.
0R pin is CMOS output.

MB15A02

FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable
reference divider and 18-bit programmable divider, respectively.
Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the internal shift register and when load enable pin is high level or open, stored
data is transferred into latch according to the control bit.
Control data "H" data is transferred into 15-bit latch.
Control data "L" data is transferred into 18-bit latch.

PROGRAMMABLE REFERENCE DIVIDER

II

Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit programmable reference counter. Serial 16-bit
data format is shown below.

l r
C

Direction of data shiftDivide ratio 0 presca er setting b'It
MSB.

Control bit

LSB

l

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

1

2

3

4

5

6

7

8

9

10

11

12

13

14

W

j.---

Divide ratio of programmable reference counter setting bit

-----f

14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide
Ratio
R

S

S

S

S

S

S

S

S

S

S

S

S

S

S

14

13

12

11

10

9

8

7

6

5

4

3

2

1

6

0

0

0

0

0

0

0

0

0

0

0

1

1

0

7

0

0

0

0

0

0

0

0

0

0

0

1

1

1

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

16383

1

1

1

1

1

1

1

1

1

1

1

1

1

1

NOTES: Divide ratio less than 6 is prohibited.
Divide ratio: 6 to 16.383
SW: This bit selects divide ratio of prescaler.
SW=H :64/65
SW=L : 1281129
S1 to S14: These bits select divide ratio of programmable reference divider.
C: Control bit (sets at high level).
Start data input with MSB first.

PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown following page.

4-55

MB15A02
Direction of data shift -----

S

S

S

S

S

S

10

11

12

13

14

15

Divide ratio of swallow
counter
setting bit

Divide ratio of programmable
counter
setting bit

7·BIT SWALLOW COUNTER DIVIDE RATIO
Divide
Ratio
A

S

S

S

S

S

S

S

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

1

•

•

•

•

•

•

•

•

127

1

1

1

1

1

1

1

NOTE:

Divide ratio: 0 to 127

11·BIT PROGRAMMABLE COUNTER DIVIDE RATIO
Divide
Ratio
N

S

S

S

S

S

S

S

S

S

S

S

18

17

16

15

14

13

12

11

10

9

8

16

0

0

0

0

0

0

1

0

0

0

0

17

0

0

0

0

0

0

1

0

0

0

1

•

•

•

•

•

•

•

•

•

•

•

•

2047

1

1

1

1

1

1

1

1

1

1

1

NOTES: Divide ratio less than 16 is prohibited.
Divide ratio: 16 to 2,047
S1 to S7: Swallow counter divide ratio setting bit. (0 to 127)
S8 to S 18: Programmable counter divide ratio setting bit.
C: Control bit (sets at low level).
Data input with MSB first.

PULSE SWALLOW FUNCTION
fvco= [(PxN)+A) xfosc+R
fvco:Output frequency of external voltage controlled oscillator (VCO)
N: Preset divide ratio of binary 11·bit programmable counter (16 to 2,047)
A: Preset divide ratio of binary 7·bit swallow counter (OSA=S;127, Afp

H

L

L

(fr)

L

H

Z

(fp)

fr Oscilloscope
L...-_ _ _ _- l I L . . . -_ _ _-<;::I

Note: Pin numbers are based on SOP/SSOP 16-pin packages.

4-60

Select fout monitor output

MB15A02

TYPICAL APPLICATION EXAMPLE
,.....--...... OUTPUT

Charge Pump
Selection
(Internal or
external)
FROM
CONTROLLER

0R
16

0P
15

FC

14

13

12

LE
11

Data

47k

II

47k

10

MB15A02 (SOP/SSOP 16-pin)

2
OSC'N

3
OSCou V p

4

5
Vee

Do

8

7

6
GND

LD

1000p

LOCK DET.

Vpx
Vp

6V max.
When internal charge pump is not used, Vp pin needs to be connected to Vee.
C1,C2 Depends on crystal oscillator
LE,FC With internal pull up resistor
0P
Open drain output
CMOS output
0R

4-61

MB15A02

ORDERING INFORMATION
Part Number

4-62

Package

MB15A02PF

Plastic SOP, 16-pin
FTP-16P-M06

MB15A02PFVi

Plastic SSOP, 16-pin
FTP-16P-M05

MB15A02PFV2

Plastic SSOP, 2O-pin
FTP-20P-M03

MB15A02

PACKAGE DIMENSIONS
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT~16P·M05)

.049~:gg~

----.+--14----- (MOUNTING HEIGHT)

I~ ~~l~i)~ ~
INDEX

J
U

(1.2S~:~g)

1

I

,

(0.65±0.12)

(6.40±0.20)

III

i
.213(S.40) NOM

*.173±.004
(4.40±0.10)

L4;:;1;=;:;::::;:;:::;;:::~ ~
.0256±.OO47

t

.252±.00B

"A"

~'

-

-,
"

j

.II . (0.22~:6~)
Details of •A" part

~
~

, ' I'
[JJI~·'.:.:
.0_004

00lO~

(STANDOFF
HEIGHn

(0.5o±fp

Note:

Z

T

T

=(High impedance)

~
z

CD

vce CHARACTERISTICS
Depending upon vce characteristics,

::::l

FC pin should be set accordingly:

a:

-

W

@
IL.

~

When vce characteristics are like 1,
FC should be set High or open circuit;

::::l

a..

-

5o

8

> ~------------------~

veo INPUT VOLTAGE -

4-72

When

vce characteristics are like 2,

Fe should be set Low.

MB1502
MB1502H

fr

fp

U

LD

Do

---

I

~)
: ------ --- Z

U
U LJ
----V-------U------Lr
I

I

I

I

I

I

III

NOTES: Phase difference detection range: -21t to +21t
Spike appearance depends on charge pump characteristics. Also, the spike is output in order to diminish dead band.
When fr > fp or fr < fp, spike might not appear depending upon charge pump characteristics.

ANALOG SWITCH
ON/OFF of analog switch is controlled by LE input signal. When the analog switch is ON, internal charge pump output (Do) to be
connected to BISW pin. When the analog switch is OFF, BISW pin is set to high-impedance state.
LE=H (Changing the divide ratio of internal prescaler) : Analog switch=ON
LE=L (Normal operating mode): Analog switch=OFF
LPF time constant is decreased in order to insert a analog switch between LPF1 and LPF2 when channel of PLL is changing.
Thus, lock up time is decreased, that is, fast lock up time is achieved.

CHARGE PUMP .....-ofii----I
IL

_ _ _ _ _ _ _ _ _ _ _ _ _ .,

: BISW
(CONTROL SIGNAL) _ _~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ OJI

RECOMMENDED OPERATING CONDITIONS
Parameter

Value
Unit

Min

Typ

Vee

4.5

5.0

5.5

V

Vp

Vee

Vp

8.0

V

Input Voltage

VI

GND

Vee

V

Operating Temperature

TA

-40

85

°C

Power Supply Voltage

i

Symbol

Max

MB1502
MB1502H

ELECTRICAL CHARACTERISTICS
(Vcc=4.5 to 5.5V, TA=-40 to +850 C, unless otherwise noted.)
Parameter

Symbol

Power Supply Current
Operating Frequency

Input Sensitivity
High·levellnput Voltage
Low·levellnput Voltage
High·level Input Current
Low-level Input Current
Input Current
High-level Output Voltage
Low-level Output Voltage
N-channel Open Drain Cutoff
Current
Output Current

Icc

Note 1

fin

Note2

OSCIN

fosc

fin

P,in

OSCIN

Vosc

0.5

VIH

VccxO .7

Except fin
andOSCIN

4-74

Typ
8.0

10
12
-10

Max

Unit

12.0

mA

1100

MHz

20

MHz

6

dBm
Vpp
V

VccxO .3

VIL

Data
Clock

IIH

1.0

IlL

-1.0

OSCIN

V

losc

±50

itA
itA
itA

LE,FC

ILE

-60

"A

Except Do
and
OSCOUT

VOH

Vcc=5V

4.4

V

VOL
Vp =Vccto 8V
Voop= GND to 8V

0.4

V

1.1

!tA

Do,0P

10FF

Except Do
and
OSCOUT

10H

-1.0

10L

1.0

IOOH

-0.8

-1.5

mA

11

22

mA

-1.4

-2.4

mA

4.5

10

mA

25

C

Do
Do

IDOL

High-level Output Current

IOOLH

Low-level Output Current

IOOLH

Analog Switch On Resistor

RON

NOTE:

Min

fin

High-level Output Current
Low-level Output Current

Value

Condition

MB1502

MB1502H

Vcc=5V,
Vp=8V,
TA.,2S·C

1: fin = 1. 'IGHz, OSCIN=12MHz, Vrx;=SV. Inputs are grounded and outputs are open.
2: AC coupling. Minimum operating frequency is measured when a capacitor 1000pF is connected.

mA
mA

MB1502
MB1502H

TYPICAL CHARACTERISTICS CURVES
INPUT SENSITIVITY CHARACTERISTICS

tin Input Sensitivity vs. Input Frequency

OSC1N Input Sensitivity vs. Input Frequency

Vcc=5.0V

Vcc-S.OV, TA-25"C

+5

10
Input
Sensitivity
Posc{dBm)

Input
Sensitivity
PIN (dBm)

-15

0

-10 t---+--++-t+H+++--+-+-.....,

t-+~r-+--+--+-I--+-~~~H

0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.31.4 1.5
Input Frequency fin (GHz)

5

10

50 100

Input Frequency OSC1N (MHz)

I-a= P.G

P.G
8

7

6

5

4

3

2

1

9 10 11 12 13 14 15 16

9 10 11 12 13 14 15 16
Oscilloscope

Oscilloscope

4-75

MB1502
MB1502H

DO PIN OUTPUT CURRENTCURVES (TYPICAL)
VOH VS. IOH

~
~

8.0

...

r:::!~~6~~~CI=C:r=r::J

Q)

Cl

!!!

g
5

5'
o

7.0

-

I

MB1 502++----4-.... MB1 502H-+--_+_---I

Q)

>
Q)

"j'

.r:.

Cl

J:

6.0 '--___"--....aI._~--'_-""-_~---"-_........__'

o

-3
-1
-2
High-level Output Current

-4
IOH

-5

(rnA)

VOL VS. IOL

....--+-+ MB1 502H -++---+-+--+-ooo!---l

30

40

Low-level Output Current

IOL

(rnA)

rl

cecW..

50

TT 100
MB1502

VOcJJV.
~v.

Ta-aoC

_1Oi.

~ r ~ M~2H 1t-----:-IoM-.~--.7.(
.. ~

4-76

MB1502
MB1502H

INPUT IMPEDANCE CHARACTERISTICS

~Mm--20MHZ

--

~~~-lOOMHz

~!-f--

-i-i-~~~~~-t----

200MHz

500MHz

4-77

MB1502
MB1502H

TYPICAL APPLICATION EXAMPLE
Vpx(6V)
...-------. OUTPUT

Charge Pump Selection
(Intemal or extemal)
FROM
CONTROLLER

....------+---- }

0P

0R
16

FC

14

15

12

13

Data

LE
11

10

6

7

47kQ

MB1502

2
OSCo

OSCIN

4

3
Vp

5
Vee

Do

GND

8
LD

0
X'tal

6V

I

C1

I

0P

4-78

5V

2
C

33kn
O.1J.LF

Vp, Vpx
ClI C2
LE,FC

Vee (5V)

1000pF

I

8Vmax
Depends on crystal oscillator
With intemal pull up resistor
Open drain output

O.01J.LF

LOCKDET

I

10kn

MB1502
MB1502H

PACKAGE DIMENSIONS
16-Lead Plastic Dual In-Line Package
(Case No.: DIP-16P-M04)

INDEX-1

~

r¢:=======~~==~===~l
.244±.010
(6.20±0.25)

INDEX-2

.300(7.62)
TYP

~;::=::;=;:::::;::::;::::;::::;:::::;:::;::::;::::::;::::;::::;::::;y~

©1991 FUJITSU LIMITED D16033S-2C

Dimensions in
inches (millimeters)

4-79

MB1502
MB1502H

16-Lead Plastic Flat Package
(Case No.: FPT-16P-M06)
.089(2.25)MAX
(MOUNTING HEIGHT)

.400:,::8Jg(10.lscg~g) ~

.002(0.05)MIN
(STAND OFF HEIGHT)
Pi

I

INDEX

/

1

.307±.01B
(7.80±0.40)

268 +.016 (680+0 .40 )
.
-.008' ~.20

.209±.012
(5.30±0.30)

"S"
0
~;::::n=::y:;::=r;:~~~

.050(1.27~ I
TYP

I.

II

I

I

I

I

==tI

-l-

.018±.004 ' r - : - r - r - - - - -

~. (0.45±o.10~.10.005(0.13)@) I
"A"

--+----'-1

.0000ooa
(0.50±0.20)

006 +.002 (0 15+0.05 )
.
-.001 . ~.02

Ir--~-77--'r-------Details of A part
I I Details of "S" part "1
I
.016(0.40)1 I
.006(0.15) ,

I

II
'I
II
II

I
,

I
,

I

~I,
I
,

.0070.18)
MAX

I'I _

.007(0.18)
MAX

.027(0.68)
MAX

•

.027(0.68)
MAX

I','

I
I

II

~--------~~--------~
©1991 FUJITSU LIMITED F16015S-2C

4-80

Dimensions in
inches (millimeters)

cO

June 1995
Edition 0.1

FUJITSU

MB 15B03~~~pf,~Od~uc~tf:Pf,~Of/~'le~S~he~et~~=====--_
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER

~~~

On-chip 1.1GHz & 300MHz PRESCAlER
The Fujitsu MB15B03 is a serial input Phase Locked Loop (PLL) frequency
synthesizer with a 1.1 GHz and a 300MHz prescalers. A 64/65 or a 128/129 for
the 1.1 GHz prescaler, and a 16/17 or a 32133 for 300MHz prescaler can be selected
that enables pulse swallow operation.
Furthermore, a super charger circuit is included to provide a fast tuning as well as low
noise performance. As a result of this, MB 15B03 is ideally suitable for digital mobile
communications, such as GSM.

PACKAGE

FEATURES
•
•
•
•
•
•

High frequency operation RF synthesizer : 1.1 GHz max.
IF synthesizer : 300MHz max.
Low power supply voltage: Vee'" 2.7 to 3.6V
Very Low power supply current: Icc = 10 mA typo (Vcc '" 3V)
Power saving function: Ips. '" Ips2 = 100 ~A typo (Vcc =3V)
Serial input 14-bit programmable reference counter: R = 6 to 16.383
Serial input l8-bit programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary l1-bit programmable counter: 5 to 2.047

FPT-16P-MOS

• On-chip high performance charge pump circuit and phase
comparator, achieving high-speed lock.up and low phase noise
• Wide operating temperature: TA = -40 to 85°C
• Plastic 16-pin SSOP package (FPT-16P-M05)

PIN ASSIGNMENT

GNDRF

ABSOLUTE MAXIMUM RATINGS (see NOTE)

,•...........::.:.:::.:: ..

'::.:;:,::::::::.;.

Remark

Value

Unit

Power Supply Voltage

Vee

-0.5 to 5.0

V

Output Voltage

Vo

-0.5 to Vee +0.5

V

Output Current
Storage Temperature
NOTE:

10

±10

mA

TSTG

-55 to +125

°C

Clock

aSCin

2

15

Data

GNDIF

3

14

LE

finlF

4

13

finRF

VCCIF

5

12

VCCRF

LDlfout

6

11

XfinRF

PSIF

7

10

PSRF

DOIF

8

9

DORF

:':::.

. Symbol

16

TOP
VIEW

Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections 01 this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

4-81

MB15B03

BLOCK DIAGRAM
VCCIF GND'F

i.-;~.:.:: --~ --:.~;,:,~- --~- -~.~;~,:- --I -;,~~ ~~ ---~ -------------j
7>~

PSt

-entmode

T

:~~

'H
:

Prescaler

fin. ,,)

:

(IF-PU)
3213

16117,

f

:

Binary 7-bit

T

I

Binary l'-bit

~r

.I

Phase

Chargel Super

:

LD~ SW'F! FC'F swall~:p~~unterl ~!g~~~~!~~ ~I ~.~~i I ~F~:::'~) \charg : 8) D~F
1
I.
••
:
~~

2·bitlatch

~

!

T1

... --------

1

I

I
14·bit latch

I

Lock

:

Det.:
(IF,PLL)

:

Binary 14·bit pro- I,,,
grammable ref. ~------t
counter(IF·PLL)

Ii T2

...

AN~
./ l

ill
LD

IrlF

Tl

:= ~

fin...~)-

Xlin...

1

Prescaler
f...,
(R'.PLL)

~ f...,

64/65,
Intermitt

PSRf\!)-~' -e:~~e
(RF.PLL)
LE

,~~

!

2·bitlatch

L...::I'::"'----~~-~t----.-I IrRF
fplF
...+---+-----I-~ I
Ullt

~L-_'_4._b_it_la_tc_h_...,j

I

r

I'

,

LDd SWRF I FCRF

1I i

r~

3·bit latch

t

Lock
Det.
(R'·PLL)

~(6

fPRF

J

....''--'''-....,

Binary 7·bit I Binary 11·bi!
swallow counter / programmablE
(R"PLL)
/ counter(R'.PLL

~L_7_.b_it_la_t_ch_--LT_'_'·_b_it_la_tc_h-"

L,.:I
~
....

Phase
compo
(RF.PLL)

charg:1
pump S uper
(RF,PLl) charger

Latch selectorl

r--~_lIL-~i____~_~

Da.-Ij~ S~m!tt f-..,
IlCI\;

Btnary 14·bit pro·
grammable ref.
countercR.·PLL)

I
r
~lt=t==:t--l--====~-l----J~--+4"":~

128/129
,_1:

T T2

~

~
S~m.ltt ~
k
CIOC\~~

·*--

1 1"
e I e I 23.bi! shift
N/N/
.
1I

2,

I

register

1'---------------------~
Vee..

4-82

GNDRF

LD/fout

MB15B03

PIN DESCRIPTIONS
.

:....

. ..... :

:.: .

.:. DescrIptions

::::
.:/.

1

GNDRf

-

Ground for RF-PLL section.

2

eSCin

I

The programmable reference divider input. TCXO should be connected with a coupling
capacitor.

3

GNO"

-

Ground for the IF section.

4

fin ..

I

Prescaler input pin for the IF-PLL.
The connection with VCO should be AC coupling.

5

Vee..

-

Power supply voltage input pin for the IF-PLL section.
When power is OFF, latched data of the IF-PLL is cancelled.

6

LDlfout

0

Lock detect signal output (LO) / phase comparator monitoring output (fout)
The output signal is selected by a LOS bit in a serial data.
LOS bit = "W ; outputs fout signal
LOS bit. "L" ; outputs LD signal

7

PSII'

....
::.:.....•..

Power saving mode control for the IF-PLL section. This pin must be set at "L" at
Power-ON. (Open is prohibited.)
PS'F = "H" ; Normal mode
PSIF = "L" ; Power saving mode

8

00,1'

o

Charge pump output for the IF-PLL section.
Phase characteristics of the phase comparator can be reversed by the FC-bit.

9

DOAF

o

Charge pump output for the RF-PLL section.
Phase characteristics of the phase comparator can be reversed by the FC-bit.
Power saving mode control for the RF-PLL section. This pin must be set at "L" at
Power-ON. (Open is prohibited.)

10

PSRF
PSRF
11

XfinRF

12

="H" ; Normal mode
="L" ; Power saving mode

Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
Power supply voltage input pin for the RF-PLL section, the shift register and the oscillator
input buffer. When power is OFF, latched data of RF-PLL is cancelled.

13

finRF

Prescaler input pin for the RF-PLL.
The connection with VCO should be AC coupling.

14

LE

Load enable signal input (with the schmitt trigger circuit.)
When LE is "H", data in the shift register is transferred to the corresponding latch
according to the control bit in a serial data.

15

Data

Serial data input (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (IF-ref counter, IF-Prog. counter, RF-ref.
counter, RF-prog. counter) according to the control bit in a serial data.

16

Clock

Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a riging edge of the clock.

4-83

MB15B03

FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:

fvco • {(P x N) + A} x fosc + R

(A < N)

fvco: Output frequency of external voltage controlled ociflator (VCO)
P:

Preset divide ratio of dual modulus prescaler (16 or 32 for IF·PLL, 64 or 128 for RF·PLL)

N:

Preset divide ratio of binary 11·bit programmable counter (5 to 2047)

A:

Preset divide ratio of binary 7 -bit swallow counter (O!> A !> 127)

lose: Reference oscillation frequency
R:

Preset divide ratio of binary 14·bit programmable reference counter (6 to 16,383)

SERIAL OAT A INPUT
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL sections,
programmable reference dividers of IFIAF PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of clock, one bit of serial data is transferred into the shift register. When load enable signal is high, the data
stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.

Table1. CONTROL BIT
<":

qOhtroI~lts
.:CN1· . · · · )(CN2 . . ·

Oestinatl0 fl of :5er1~IUi:llUI

... ....< . . . :. .«

.:

.:..........

. . . •. . . . ..« .fp

H

L

fr - fp

Z

Z

fr < fp

L

H

VCO Polar~y

.l,D/fQutoutput signal
H

fout (fr'FIRF. fpIFIRF) signals

L

LD signal

SERIAL DATA INPUT TIMING

<::?

N11(MSB)X

Data

N10

~~~~3

<::?

CN1(LSB)

----------------

,

--,

Clock

'"

<::?

.

lE

,

I

,

,I

I

,

I

,,

rL

--~:------I-------I I ,
t5~
:-- t3---: : :

'

'
,, '
'
t1
t2 :

t6~

~t~

,

~t4

'

: - - t8--':

On rising edge of the clock. one bit of the data is transferred into the shift register.

:P~l'arneter" <.

Min.

Typ.

Max.

Unit

'

..

Parameter . . .

.M'an.'.;

Typ.

Max~;

I··' Unit . •.
.

".,,'

t1

30

ns

t5

100

ns

t2

30

ns

t6

100

ns

t3

30

ns

17

200

ns

t4

30

ns

18

200

ns

4-87

MB15B03

PHASE DETECTOR OUTPUT WAVEFORM

I

I

~
I
I

_____________1
tWL

LD
(FC bit .. High)

0",_ ---~ ---Z---q------',- ---,j--L------Jr------J,_ -----J,_ H

(FC bit
DO,FIRf- -

=Low)

-~-

- -

Z--

-d------J1-----q-------r------.1,_ -----J( -J

LD OUTPUT LOGIC TABLE

···IF~r.U.sec*)n

::::.
...

. . :1·:·:RF·P,tP~~ii6n ..:>< ........•. >:.:::
.::.,.

:::::.::

LQoutput

Locking state / Power saving state

Locking state / Power saving state

H

Locking state / Power saving state

Unlocking state

L

Unlocking state

Locking state I Power saving state

L

Unlocking state

Unlocking state

L

Note: • Phase error detection range

..

=-21t to +21t

• Pulses on DOlFIIV' signals are output to prevent dead zone.
• LD output becomes low when phase error is twu or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• twu and tWL depend on OSCin input frequency as follows.
twu ~ 8110sc: i.e. twu ~ 625ns when foscin = 12.8 MHz
tWL S 16lfosc: i.e. tWL S 1250ns when foscin = 12.8 MHz

4-88

MB15B03

POWER SAVING MODE (INTERMITTENT MODE CONTROL CIRCUIT)
Setting a PS'F(AF) pin to Low, IF·PLL(RF·PLL) enters into power saving mode resultatly current sonsumption can be limited to
100~ (typ.). Setting PS pin to High, power saving mode is released so that the device works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode. In general,
the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. Such
case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an unde·
fined phase relation between reference frequency (f.) and comparison frequency (fp) and may in the worst case take longer
time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during
power up, thus keeping the loop locked.
PS pin must be set 1.. at Power-ON.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving function
stops working, then current consumption is reduced to 100llA per one PLL section.
At that time, the Do and lD become the same state as when a loop is locking. That is, the Do becomes high impedance.
A veo control voltage is naturally kept at the locking voltage which defined by a LPF"s time constant. As a result of this,
veo's frequency is kept at the locking frequency.

l

l

OFF

OFF

OFF

H

l

ON

OFF

ON

L

H

OFF

ON

ON

H

H

ON

ON

ON

III

4-89

:..

MB15B03

RECOMMENDED OPERATING CONDITIONS
. Unit
3.6

V

GND

Vec

V

-40

+85

Vce

2.7

Input Voltage

Vi

Operating Temperature

Ta

Power Supply Voltage

3.0

Note

HANDLING PRECAUTIONS
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

ELECTRICAL CHARACTERISTICS
1
/ •. .:.
1><;:::

<

.....

... :

...

.....

:..

.... . ; : ( :

... Symbol

w.w, ........

.

.•..•.......

..'.'< ..•.•

.:........ •:...::::i; .... •.. '.

. .......

.. '

..

.....;...

.

<> .

<;./.:::

Value

Min

Typ

Max

.':

leoF

fin'F = 300M Hz,
fose = 12MHz

-

3.5

-

lecRF

finRF = 11 OOMHz,
fosc= 12MHz

-

6.5

-

Ips'F

Vcc'Fcurrent at PS .. ="L"

-

100

-

IpsRF

VecRFcurrent at PS'FfRF ="L'

-

100

-

fin'F

fin'F

IF-PLL

50

-

300

finRF

finRF

RF-PLL

100

-

1100

OSCin

fose

min. 500mVp-p

-

12.8

23

fin'F

PfinlF

-10

-

+2

dBm

finRF

PfinRF

-10

-

+2

dBm

aSCin

Vase

500

-

-

mVp-p

Power Supply Current "1

mA

Power Saving Current "2

Operating Frequency

Input Sensitivity

lJ.A

IF-PLL, son termination
(Refer to the test circuit.)
RF-PLL, son termination
(Refer to the test circuit.)

·1: Conditions; VfX,Ftfl.F 3V, Ta = 25°C, in locking state.
·2: Conditions; VCOFtfl.F= 3V, Ta = 25°C, in power saving state.
0&

4·90

UnIt

MHz

MB15B03

ELECTRICAL CHARACTERISTICS
_~..; .•• :';i'SYmbq
''':':!'

<}) I::"':"

),:::::::

Input Voltage

Inp.ut Current

cutoff current

1,.·/"'.·····::,:::::.
'.. '.: .:.:.: . x:',:':::

,":::::.::'

VI"

VccxO.7+0A

VI~

-

Data. Clock
LE.PS

II"

-

IlL

-1.0

LD

Do

OSCin

-100

Vo"

Vcc '" 3.0V. IOH _ -1.0mA

VOl..

Vcc

=3.0V. b. -

1.0mA

10FF

10H

Vee.3.0V

LD
10L

Output Current
100H

Do
100L

Vee

= 3.0V

Vee ,3.0V, VOOH =2.0V.
Ta = 25°C
Vee . 3.0V, VOOL = 1.0V
Ta",-_25°Q

.

..

Data. Clock
LE.PS

OSCin

Output Voltage

. ·•••.. Z... ;;y;;i;:: I.)

2.2

Typ

:·Max.

-

-

-

-

....
'.

'

<~
Vn····
V

-

VfV'Vn

~..n

+1.0

-

~

+100

-

-

-

0.4

-

0.3

-1.0

-

-

-

-

1.0

-12

-

-3.5

6

-

18

III

V

~

mA

mA

4-91

MB15B03

TEST CIRCUIT (PRESCAlER INPUT / PROGRAMMA·
BlE REFERENCE DIVIDER INPUT SENSITIVITY TEST)
fout

r-----------OUOseilloseope
Vee"
1000pF

I 5011!

P.G~OOPF

GND

50nl
MB1SB03

P.Gi'

1000pF

son

.
1000pF

4-92

I

()

P.G

MB15B03

APPLICATION EXAMPLE

Output

3V

Clock

II

Data

MB15B03

rO. 1IlF
Lock Detector

1000pF

Output

Nole:

Clock. Data. LE

: involves a schmitt circuit
(When inputs are open. pull up/down resistor is necessary to prevent self-oscillation.)

4-93

MB15B03

PACKAGE DIMENSION
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M05)

.049~:~:
_4--+------ (MOUNTING HEIGHT)
(1.25~:~g)

~ ~ ~~ITi)~ ~
J
U

11I

INDEX

I

.252±.OO8
(6.4Oi:o.20)

.213(5.40) NOM

*.173±.004
(4.4Oi:o.10)

1¢:;1;=;:;::::n::;;::~ -.-l
.0256±.0047

I

+.004
.009 -.002

(0.65±o.12)

·A·~ •

-.~

.-L
.- ...............................

.006~:ggf(0.15~:g~)
- ....................................... ,

Details of •A· part

~
~

.004±.OO4
(0.10±0.10)

(STAND OFF
HEIGHT)

*:This dimension does not include resin protruction.

~1991 FUJITSU LIMITED F16013S·2C

4-94

Dimensions in
inches (millimeters)

00

June 1995
Edition 0.1a

FUJITSU

MB 15F03~~~PIi~Od~uc~t~PIi~Of/~"Je~S~he~et~~=====--_
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
~~~

On-chip 2.0GHz & 500MHz PRESCALER
The Fujitsu MB15F03 is a serial input Phase Locked Loop (PLL) frequency
synthesizer with a 2.0GHz and a 500MHz prescalers. A 64/65 or a 128/129 for
the 2.0GHz prescaler, and a 16/17 or a 32133 for 500MHz prescaler can be selected
that enables pulse swallow operation.
The latest BiCMOS process technology is used, resulting in a low supply current
of 9.0mA typo at a supply voltage of 3.0V.
Furthermore, a super charger circuit is included to provide a fast tuning as well as low
noise performance. As a result of this, MB15F03 is ideally suitable for digital mobile
communications, such as PHS (Personal Handy System), PCN (Personal Communication Network) and PCS (Personal Communication Service).

~~ ~"

~~~~\}

~-------~

PACKAGE

\S

•

FEATURES
• High frequency operation RF synthesizer : 2.0GHz max.
IF synthesizer : 500MHz max.
• Low power supply voltage: Vcc::: 2.7 to 3.6V
• Very Low power supply current: Icc =9.0 mA typo (Vcc = 3V)
• Power saving function: IpS1 = IpS2 = 10!lA max. (Vcc = 3V)
• Serial input 14-bit programmable reference divider: R = 5 to 16,383
• Serial input 18-bit programmable divider conSisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 5 to 2,047

FPT-16P-M05

• On-chip high performance charge pump circuit and phase
comparator, achieving high-speed lock-up and low phase noise
• Wide operating temperature: TA =-40 to 85°C
• Plastic 16-pin SSOP package (FPT-16P-M05)

PIN ASSIGNMENT

16

Clock

OSCin

2

15

Data

GNDIF

3

14

LE

finlF

4

GNDRF

ABSOLUTE MAXIMUM RATINGS (see NOTE)
.

ReIl18I'k···.···.·.·
:... :

......

Value

Unit

Vee

-0.5 to 4.0

V

Input Voltage

VI

-0.5 to Vee +0.5

V

Output Voltage

Vo

-0.5 to Vee +0.5

V

TSTG

-55 to +125

°C

Rating

...

.

Power Supply Voltage

Storage Temperature
NOTE:

Symbol

...

..

:

VCCIF

TOP 13
VIEW
12
5

finRF
VCCRF

LD/fout

6

11

XfinRF

PSIF

7

10

PSRF

DOIF

8

9

DORF

Pennanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

4-95

MB15F03

BLOCK DIAGRAM

-1

~';:..1

r------------------------------------------

il
I

t'

7) :
I

:

finF

~

3-bit latch

~!

~---------------r_-----------_,
7-bit latch

I

-ent mode
Binary 7-bit I
control
SW,F I FC'F
swallow counter I
JlF•P
L
L
':L
i.i
(IF·PLL) '
1

LD~

H

4):

~

Intermitt

J

I.

11-bit latch
Binary 11-bit
programmabl'
·
'
counter(IF·PLL)

3

- - - - - - - - - - - - - - ':

~

I--

~

•

16/~Ft~31 ai*=~~~===t:=tl===1J--lr;1
Prescaler

...J

:

';::

~1_-2--b-it....la-tch-_I~1--14---b-it_Ia_tch_--t

:

!

II

T1

:._-------I

pump h
(IF.PLL) c arge

(IF·PLL)

:

LDI'

:
I

L....-______

~~

I

Binary 14-bit programmable ref.
counter(RF·PLL)

T2

2-bit latch

~L....-_1_4-_b_it_la_tc_h_

Prescaler 14-++--t-------,
(RF.PLL)

I

64/65,
128/129

I

LEEIk--~
~

Da.-r,'r-- S fp

H

L

fr<~ lII.

,,-'

i

i'.i·'

/

Vcc

2.7

3.0

3.6

V

Input Voltage

Vi

GND

-

Vee

V

Operating Temperature

Ta

-40

-

+85

DC

Power Supply Voltage

"""'" in dual inline package (Suffix: -P)
Plastic 16;>in small outline package (Suffix: -PF)

High operating frequency
Pulse-swallow function

PLASTIC PACKAGE
(FPT-16P-M06)

ABSOLUTE MAXIMUM RATINGS (See NOTE)
...

Ratings

Supply Voltage

··············>i£~U.ci····

\

SwntJPI I....... ·... ..... .
Vee

.. . .

. ·\
.• • . .•. • .•. • . . .•. · . . ·.··.\IOIOIDI~

I

OSCou~-------~

Do

----------------------------<~

r16=biiShlft ReQi;t;-1

osc,l\------.l

r Prescaler

II Output

(a,.,1----el1 Prescaler
MC

1P"S1

I

111.bit Latchl

~I[]Io:rraIOI~

i

Programmable Divider

I

11

I ~Binary 7-bit
I Swallow
I Counter

I~10
~.,

L-_ _

-I~- '9
~

Data

Clock

I

1 1 I
L
I

Binary 11'bit'i
Programmable
Counter

L--ff-1-f--

L---------tf

1-bit
Control
Latch

Control Circuit

I

J

I

4-111

MB1503

PIN DESCRIPTION
Pin No. Pin Name

4-112

Description

110
I

Programmable reference divider input
Oscillator input
An external crystal is connected to this pin.

OSCOUT

0

Oscillator output
An external crystal is connected to this pin.

3

Vp
Vee

-

Power supply input for charge pump and analog switch

4
5

Do

0

Charge pump output
The phase of the charge pump is reversed depending on the FC input.

6

GND

-

Ground

7

LD

0

Phase comparator output
The output level is high when LD is locked. The output level is low when LD is unlocked.

8

fiN

I

Prescaler input
Connection with an external VCO should be done by AC coupling.

9

Clock

I

Clock input for 19-bit and 16-bit shift registers
Data is shifted into the shift register on the rising edge of the clock.The Schmitt trigger is
contained.

10

Data

I

Serial data input using binary code
The last bit of the data is a control bit.
When the control bit is high, data is transmitted to the 15-bit latch.
When it is low, data is transmitted to the 18-bit latch.The Schmitt trigger input is involved.

11

LE

I

Load enable signal input
When LE is high, the data of the shift register are transferred to a latch, depending on the
control bit in the serial data. At the same time, an internal analog switch turns on and the output
of the internal charge pump is connected to the BiSW pin.The Schmitt trigger input is involved.

12

FC

I

Phase select input of phase comparator (with internal pull-up resistor)
When FC is low, the characteristics of the charge pump and phase comparator are reversed.
The FC input signal is also used to control the fOUT pin (test pin) of fR or fp.

13

BiSW

0

Analog switch output
BiSW is usually in the high-impedance state. When the switch is turned on (LE is high), the
state of the internal charge pump is output.

14

fp

0

Monitor pin of programr:t:@ble counter output

15

fR

0

Monitor pin of reference counter output

16

PS

I

Power save signal input
Set PS low while the system is powered (never use pin 16 as it is opened)
PS = High : Operation mode
PS = Low : Stand-by mode

1

OSCIN

2

Power supply

MB1503

FUNCTIONAL DESCRIPTIONS
Pulse swallow function
The divide ratio can be calculated using the following equation:
fvco

=[(M x N) + A] x fose + R

(A < N)
fveo : Output frequency of external voltage controlled oscillator (VCO)
N
Preset divide ratio of binary 11-bit programmable counter (16 to 2,047)
A
Preset divide ratio of binary 7-bit swallow counter (0 ~ A ~ 127)
fosc : Output frequency of the reference frequency oscillator
R
Preset divide ratio of binary 14-bit programmable reference counter (8 to 16,383)
M
Preset divide ratio of modules prescaler (128)

III

Serial data input
Serial data is input using the Data, Clock, and LE pins. Serial data controls the 1S-bit programmable reference divider and 18-bit
programmable divider separately.
Binary serial data is input to the Data pin.
One bit of data is shifted into the internal shift registers on the rising edge of the clock. When the load enable pin is high or open, stored
data is latched depending on the control data as follows:
Control data

(a)

Destination of serial data

H

15-bit latch

L

18-bit latch

Programmable reference divider ratio
The programmable reference divider consists of a 15~bit latch and a 14-bit reference counter. The serial 16-bit data format is
shown below:

- - -......~ Direction of data shift

Divide ratio setting bit for programmable reference counter

4-113

MB1503
14-bit programmable reference counter divide ratio

Divide ratio

S

S

S

S

S

13

12

11

10

S
8

S
7

6

S
5

S

14

S
9

S

R

4

S
3

S
2

S
1

8

0

0

0

0

0

0

0

0

0

0

1

0

0

0

9

0

0

0

0

0

0

0

0

0

0

1

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

.
16383

. . . . . . . . . . . . . .
(Divide ratio

Notes:

(b)

1. Divide ratios less than 8 are prohibited
2. SW: This bit selects the divide ratio of the prescaler
SW Low: 128 or 129 (SW must be always be low)
3. S1 to S14: These bits select the divide ratio of the programmable reference counter (8 to 16,383)
4. C: Control bit: Set high
5. Input MSB data first

Programmable divider divide ratio
The programmable divider consists of a 19-bit shift register, 18-bit latch, 7-bit swallow counter, and 11-bit programmable
counter. The serial 19-bit data format is shown below:

- - - . . Direction of data shift

Divide ratio setting bit for
swallow counter

4-114

=8 to 16,383)

Divide ratio setting bit for programmable counter

MB1503
•

7 ·bit swallow counter divide ratio

11·bit programmable counter divide ratio

S
5

S
2

S
1

Divide
ratio
N

S
18

S
17

S
16

S
15

S
14

S

4

S
3

S

A

S
6

S

7

13

12

S
11

10

S
9

S
8

0

0

0

0

0

0

0

0

16

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

0

1

17

0

0

0

0

0

0

1

0

0

0

1

127

1

1

1

1

1

1

1

2047

1

1

1

1

1

1

1

1

1

1

1

Divide
ratio

S

. . . . . . . .

. . . . . . . . . . . .

(Divide ratio = 0 to 127)

Notes:

S

(Divide ratio

=16 to 2,047)

1. Divide ratios less than 16 are prohibited for the 11-bit programmable counter
2. S 1 to S7: These bits select the divide ratio of the swallow counter (0 to 127)
3. S8 to S18: These bits select the divide ratio of the programmable counter (16 to 2,047)
4. C: Control bit: (Set low)
5. Input MSB data first

II

Serial data input timing
•

t1 (~ 1flS): Data setup time
t2 (~ 1flS): Data hold time
t4 (~ 1flS): LE setup time to the rising edge of last clock

Data

~--~--=rux

~ __ ~._

(SW) (*1)
Clock

t3 (~ 1J-ls): Clock pulse width
t5 (~ 1J-ls): LE pulse width

I

(S14)

(S8)

I

(S7)

LSB

(S1)

C: Control bit

(C: Control bit)

JlJJL.. J1lJL.. lLfLI

fL

I

II

LE

,
t1~

---------.j
I

I

t3 ~ ~.",--,."", t4
t5

-:--f-

* 1: Bits enclosed in parentheses are used when the divide ratio of the programmable reference divider is selected.

Note:

One bit of data is shifted into the shift register on the rising edge of the clock.

4-115

MB1503
Intermittent operation
Intermittent operation limits power consumption by shutting down or starting the internal circuits according to their necessity. It device
operation resumes uncontrolled, the error signal output from the phase comparator may exceed the limit due to an undefined phase
relationship between the reference frequency (fR) and the comparison frequency (fp) and frequency lock is lost.
To prevent this, an intermittent operation control circuit is provided to decrease the variation in the locking frequency by forcibly
correcting the phase of both frequencies to limit the error signal output. This is done by the PS control circuit. If PS is set high, the
circuit enters the operating mode. If PS is set low, operation stops and the device enters the stand-by mode. Each mode is explained
below:
Operating mode (PS =High Level)
All circuits are operating, and PLL operation is normal.
Stand-by mode (PS = Low level)
Circuits that do not affect operation are powered down to limit current consumption.
The current in the power save state is typically 1001lA.
At this time, the levels of Do and LD are the same as when the PLL is locked.
Since Do is placed in the high-impedance state and the input voltage of the voltage controlled oscillator (VCO) is set to the voltage
in the operating mode (when locked) by the time constant of the low-pass filter, the frequency output from the VCO (fveo) is kept at
the locking frequency.
The operating and stand-by modes alternate repeatedly. This intermittent operation limits the error signal by forcibly correcting the
phase of the reference and comparison frequencies to limit power consumption.
The device must be set in the stand-by mode (PS = low) when it is powered up.

Relationship between the

Fe input and phase characteristics

The FC pin changes the phase characteristics of the phase comparator. The internal charge pump output level (Do) is reversed,
depending on the FC pin input level. The relationship between the FC input level and Do is shown below:

*1:

FC = High or open

FC= Low

fR > fp

H

L

fR < fp

L

H

fR =fp

Z (*1)

Z (*1)

High impedance

When designing a synthesizer, the FC pin setting depends on the VCO characteristics.

,
*: When the VCO characteristics are similar to

(0, set FC high or open.
*: When the VCO characteristics are similar to

,

VCO
output
frequency

0, set FC low.

/

/

",
,
/

/

/

/

/
/

>( ,

/

//

,,

,,

VCO input voltage _

4-116

/(0

'0

MB1503
Phase comparator output waveform (Fe

=High)

fp

LD

H

Do - - -

JL
:

1

- - - - - - -

II

--u------u---L

r-- Lh---I

Z - -

I

I

Notes: 1. Phase difference detection range: -21t to +2n
2. Spike appearance depends on the charge pump characteristics. Also, the spike is output to diminish
dead band.
3. When fA > fp or fA < fp, a spike might not appear depending on the charge pump characteristics.
4. LD is low when the phase difference is tw or more. LD is high when the phase difference is tw or less for
three or more cycles (when fOSCIN =12.8MHz, tw =625 to 1,250ns).

Analog switch
The LE signal turns the analog switch on or off. When the analog switch is turned on, the charge pump output (Do) is output through
the BiSW pin. When it is turned off, the BiSW pin is in the high-impedance state.
When LE
When LE

=high (when the divide ratio of the internal divider is changed):

=low (normal operating mode):

Analog switch

=on

Analog switch = off

The LPF time constant can be decreased by inserting an analog switch between LPF1 and LPF2. This decreases the lock-up time
when the PLL channel is changed.

(Control signal LE)

------------------

I
..JI

4-117

MB1503

RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol
Vee

Value
Min

Typ

Max

4.5

5.0

5.5

Unit
V

Supply Voltage
Vp

Vee"; Vp"; 8.0

Input Voltage

VI

GND

-

Vee

V

Operating Temperature

TA

-40

-

+85

°C

Notes: To protect against damage by electrostatic discharge, note the following handling precautions:

4-118

V

-

Store and transport devices in conductive containers.

-

Use properly grounded workstations, tools, and equipment.

-

Turn off power before inserting or removing this device a socket.

-

Protect leads with conductive sheet, as treatment (transport) a board mounted the device.

MB1503

ELECTRICAL CHARACTERISTICS
Parameter

SYlTlbol

ccc,

Min

.:.'

Value

JVpi ." .

,

.

,',,"",.

Max.:.:.

Unit I.'

Condition

"..

:>' :.:. "

=

Supply Current

lee

-

B.O

12.0

Stand-by Current

IPS

-

100

-

~

With fIN 1.1 GHz, OSCIN
12MHz, Vee
5.0V. The
PS pin is grounded, remaining inputs are at Vee, and
outputs are open.

AC coupling. The minimum
operating frequency is
measured with a 1OOpF capacitor connected.

=

Low-level Input Voltage
High-level Input Current

=

fIN

fIN

10

-

1100

MHz

OSCIN

fose

-

12

20

MHz

-

fIN

PflN

-10

-

6

dBm

-

OSCIN

Vose

0.5

-

-

Vp--p

-

VIH

Vee xO .7

-

-

V

-

VIL

-

-

Vee xO.3

V

-

IIH

-

1.0

~

-

IlL

-

-1.0

-

~

-

FC

IFe

-

-60

-

~

-

OSCIN

lose

-

±50

-

~

-

VOH

4.4

-

-

V

Vee

VOL

-

-

0.4

V

-

10FF

-

1.1

~

10H

-1.0

-

mA

-

10L

1.0

-

mA

-

RON

-

25

-

Q

-

Operating Frequency

High-level Input Voltage

Except fIN and
OSCIN

Data, Clock,
LE

=

mA

=

Input Sensitivity

. ...

With fIN 1.1 GHz, OSCIN
12MHz, Vee 5.0V. Inputs
are Vee and outputs are
open.

=

II

Low-level Input Current

Input Current
Hit-level Output
Votage
Low-level Output Voltage

Except Do and
OSCOUT

High-impedance
Cut off Current

Do

Output Current

Except Do and
OSCOUT

Analog Switch ON Resistance

=5V

=

VOO GND to BV
Vee SVp S BV

4-119

MB1503

TEST CIRCUIT
(FOR MEASURING PRESCALER INPUT SENSITIVITY)

Vp=6V

O.1J.l
1000p

PG

I

7fT

7fT

~ ,.....-....--"-~~---.
50nl

87654321
Vee

9 10 11 12 13 14 15 16

Oscilloscope

4-120

=5V

MB1503

APPLICATION EXAMPLE

I
I

r vco I
I
I

1

LPF

I

Output

-

-...

IfR

PS
16

15

Fmm
controller

-

Ifp
14

1

II

LE

Biswi FC
13

12

Data

Clock

11

10

9

6

7

8

~

7.'r

47K ; ~ 47K

7."r

MB1513

1
OSCIN

2

Hm-

X'tal
-'- C 1 -I.- C2

;J;.

Vp, Vpx:
C 1 , C2 :

4

3
oscou Vp

;J;.

5
Vcc

LI
O.1~ l
6V

LJ

5V

Do

lGND ILD

fiN
II

Ir
1000p

Maximum 8V
Depends on the crystal parameters

4-121

MB1503

PACKAGE DIMENSIONS
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M06)
.089(2.25)MAX
(MOUNTiN(fHEIGHTi

Q

r

..-dJ

.307±.016
(7.8o±0.40)

INDEX

0

/

.268~:gJ~ (6.80~:~g)

.209±.012
(5.3o±O.30)

"S"

~~=rr~~~~~~~
.050(1.27~ I
TYP

I:
I i

• i

==t
-lI

I

.018±.004 ',":;--r-----=--,
« (0.45±0.1 0)1-$-1 0.005(0.13) @ 1

I

i
1

I
I
II _

Details of "A" part

4. .122

r--------~

I I

i

Details of "S" part

:

~O~)i ~OT·'5)
~~
.008(0.20)1 1

.027(0.68)

I
I
II

L _ _ _ _ ~~ _ _ J

©1991 FUJITSU LIMITED F16015S-2C

.0_008
(0.5o±O.20)

006 +.002 (0 15+0.05 )
.
-.001 . -0.02

r--------,

"A"

.002(0.05)MIN

(STr D OFF HEIGHT)

I
I
II

.008(0.201

.0070.18)
MAX
« .027(0.68)

L _ _ _ _ ~~ _ _ _

Dimensions in
inches (millimeters)

MB1503

16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M04)

15°MAX

I~

-t

INDEX-1

.244±.010
(6.2o±O.25)

INDEX-2

Ir,t
.300(7.62)
TYP

~;:::=;=:;:::::::;::=::;::=;:==;:::::=;:=:;:::=:;:::=;::~~

•

.01o±.002
(0.25±0.05)

-~JLffl~:tf:~:::::::
I
.050(1.27)
I • MAX
I

"I

©1991 FUJITSU LIMITED D16033S-2C

TYP

II

~

.020(0.51)MIN

(0.46±0.OB)

Dimensions in
inches (millimeters)

4-123

4-124

~D~s~o~~2~130~1~~E~~~~~~~==~
__
==
DATA SHEET

cO

FUJITSU

nqS 1504/nqS 1504H/nqS 1504L
ASSP SERIAL INPUT PLL FREQUENCY SYNTHESIZER
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 520MHz PRESCALER
The Fujitsu MB1504/MB1504H/MB1504L. utilizing BI-CMOS technology. is a single chip
serial input PLL frequency synthesizer with pulse-swallow function.
The MB 1504 series contains a 520MHz two modulus prescaler that can select either 32133 or
64/65 divide ratio; control signal generator; 16-bit shift register; 15-bit latch; programmable
reference divider (binary 14-bit programmable reference counter); 1-bit switch counter; phase
comparator with phase inverse function; charge pump; crystal oscillator; 19-bit shift register;
18-bit latch; and a programmable divider (binary 7-bit swallow counter and binary 11-bit
programmable counter).

II

The MB 1504 operates from a low supply voltage (3V typ) and consumes low power (30mW at
520MHz).

MB1504 Product Line
vp Voltage

Voop Voltage

Lock up TIme

~?d?t.utPut

High-level
Output Current

Low-level
Output Current

MB1504

SVmax

S.5V max

Middle speed

Middle

Middle

Middle

MB1504H

10V max

10.0V max

High speed

Low

High

Low

MB1504L

SVmax

S.5V max

Low speed

High

Low

High

PLASTIC PACKAGE
DIP-16P-M04

FEATURES
•

High operating frequency: fiN MAX=520MHz (VIN MIN=0.20Vp_p)

•
•

On-chip prescaler
Low power supply voltage: 2.7V to 5.5V (3.0V typ)

•

Low power supply consumption: 30mW (3.0V. 520MHz operation)

•

Serial input 18-bit programmable divider consisting of:
-Binary 7 -bit swallow counter (Divide ratio: 0 to 127)
-Binary 11-bit programmable counter (Divide ratio: 16 to 2047)
Serial input 15-bit programmable reference divider consisting of:
-Binary 14-bit programmable reference counter (Divide ratio: 8 to 16383)
-1-bit switch counter (SW) Sets divide ratio of prescaler

•

•

•

PLASTIC PACKAGE
FPT-16P-M06

2 types of phase detector output
-On-chip charge pump (Bipolar type)
-Output for external charge pump
Wide operating temperature: TA=-40°C to +85°C
This device contains Circuitry to protect the inputs against
damage due to high static voltages or electric fields. However. It is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high Impedance circuit.

4-125
Copyright@1994 by FUJITSU LlMIED

MB1504
MB1504H
MB1504L

PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating

Symbol
Vee

Power Supply Voltage
Output Voltage
Open-drain Output

VPH
Vp,VPL
VOUT
VOO PH
VoOP,VOOPL

Condition

MB1504H
MB1504/1504L

MB1504H
MB1504/1504L

Value

Unit

-0.5 to +7.0

V

Vee to 12.0
Vee to 10.0

V

-0.5 to Vee +0.5
-0.5 to 11.0
-0.5 to 9.0

V

Output Current

lOUT

-

+10

Storage Temperature

TSTG

-

-55 to +125

NOTE:

4-126

V

rnA
DC

Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

MB1504
MB1504H
MB1504L
MB1504/MB1504H/MB1504L BLOCK DIAGRAM

vee@-GND~

r-----------,

I
I

I
I
I

16-Bit Shift Register

~]IillillillilI[~
I

LE

16-Bit Shift Register

1S-Bit Latch

I
I
I

1S-Bit Latch

11

13

fr

12

FC

]IilIilIillilIC

r

I
OSC'N

Programmable
Reference Divider

'

Binary 14-Bit
Reference Counter

1

LD

I
I

•

r---------------,I

I

.....+----rl....

19-Bit Shift Register
19-Bit Shift Register

vp

:

Charge
Pump

~]]IOJI[O]IOJI[[~
I
I
I:

I

Do

18-Bit Latch

11-Bit Latch

:]JlillJlillJlllIfI~
___ .,I
I

14

fp

Programmable Divider

I
I
I
I

Programmable Counter
_ _ _ _ _ _ _ .J

4-127

MB1504
MB1504H
MB1504L

PIN DESCRIPTIONS
Pin No.
1
2

4-128

Pin Name
OSCIN
OSCOUT

I/O
I

0

Descriptions
Oscillator input
Oscillator output
A crystal is placed between OSCIN and OSCOUT.

3

Vp

-

Power supply input for charge pump

4

Vee

-

Power supply voltage input

5

Do

0

Charge pump output
The phase characteristics can be inversed depending upon the FC input.

6

GND

-

Ground

7

LD

0

Phase comparator output
This pin outputs high when the phase is locked. While the phase difference of fr and fp exists, the output
level goes low.

a

fiN

I

Prescaler input
The connection with an external VCO should be an AC connection.

9

Clock

I

Clock input for 19-bit shift register and 16-bit shift register
Each rising edge of the clock shifts one bit of data into the shift registers.

10

Data

I

Serial data of binary code input
The last bit of the data is a control bit. The last data bit specifies which latch is activated.
When the last bit is high level and LE is high-level, data is transferred to the 15-bit latch.
When the last bit is low level and LE is high level, data is transferred to the 18-bit latch.

11

LE

I

Load enable input (with internal pull up resistor)
When LE is high level (or open), data stored in the shift register is transferred to the latch depending on the
control data.

12

FC

0

Phase selecting input of phase comparator (with internal pull up resistor)
When FC is low level, the charge pump and phase detector characteristics can be inversed.

13

fr

0

Monitor pin of phase comparator input
It is the same as the programmable reference divider output.

14

fp

0

Monitor pin of phase comparator input
It is the same as the programmable divider output.

15
16

0P

0
0

0R

Outputs for external charge pump
The phase characteristics can be inversed depending on the FC input.
The 0P pin is an N-channel open-drain output.

MB1504
MB1504H
MB1504L

FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is input using the Data pin, Clock pin and LE pin. The lS-bit programmable reference divider and 18-bit programmable divider are
controlled, respectively.
On rising edge of the clock, one bit of the data shifts into the internal shift registers.
When load enable (LE) is high level (or open), data stored in the shift registers is transferred to the lS-bit latch or l8-bit latch depending upon the control bit
level.
Control data "H" : Data is transferred into the l5-bit latch.
Control data "L": Data is transferred into the 18-bit latch.

III

PROGRAMMABLE REFERENCE DIVIDER
The programmable reference divider consists of a 16-bit shift register, lS-bit latch and 14-bit reference counter. Serial 16-bit data format is shown below.

---------4.•

Data input

Control bit
LSB

Last data input

S

C

First data input

S

S

S

2

3

4

....- - - Divide ratio of programmable reference counter setting bits - - - - . t

@ 14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide
ratio
R

S

S

S

S

S

S

S

S

S

S

S

S

S

S

14

13

12

11

10

9

8

7

6

5

4

3

2

1

8

0

0

0

0

0

0

0

0

0

0

1

0

0

0

9

0

0

0

0

0

0

0

0

0

0

1

0

0

1

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

16383

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Divide ratio less than 8 is prohibited
Divide ratio R: 8 to 16383
SW: Divide ratio of prescaler setting bit
SW="H": 32
SW","L": 64
S1 to S14: Divide ratio of programmable reference counter setting bits (8 to 16383)
C: Control bit (control bit is set to high)

4-129

MB1504
MB1504H
MB1504L

FUNCTIONAL DESCRIPTIONS
PROGRAMMABLE DIVIDER
The programmable divider consists of a 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
5erial 19-bit data format is shown below.

-----------t.~ Data input

@

@ 11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO

7-BIT 5WALLOW COUNTER DIVIDE RATIO

5

5

5

5

5

5

5

5

5

5

5

1

Divide
ratio
N

18

17

16

15

14

13

12

11

10

9

8

0

0

16

0

0

0

0

0

0

1

0

0

0

0

0

0

1

0

0

0

0

0

1

0

0

0

1

•

•

•

•

.

0

•

.

17

•

•

•

•

•

.

1

1

1

1

1

1

1

1

1

1

1

1

1

Divide
ratio
A

5

5

5

5

5

5

5

7

6

5

4

3

2

0

0

0

0

0

0

1

0

. .

0

0

0

•

•

63

1

1

0

Divide ratio A : 0 to 63

•
2047

..
1

Divide ratio of programmable counter setting bits (16 to 2047)
58 to 518:
51 to 57:
Divide ratio of swallow counter setting bits (0 to 127)
C: Control bit (control bit is set to low)
Data is input from the M5B.

4-130

1

Divide ratio less than 16 is prohibited
Divide ratio N : 16 to 2047

MB1504
MB1504H
MB1504L
SERIAL DATA INPUT TIMING

Data

S18=MSB

S17

S10

S9

S 1=LSB

*(SW)

(S14)

(S8)

(S7)

(S1)

Clock

X

C: Control bit

(C: Control bit)

....

~* '" lsi-

LE
t1 -of--4-

III

·1

On the rising edge of the clock. one bit of the data shifts into the shift registers.
Data in ( ) is used for setting the divide ratio of the programmable reference divider.

PHASE CHARACTERISTICS
VCO CHARACTERISTICS
The FC pin (pin 12) is provided to inverse the phase comparator characteristics.
The characteristics of the internal charge pump output (Do). and phase detector
outputs (0R. 0P) can be inversed depending upon the FC input data. Outputs
are shown below.

>-

()

z

W

Do

aw

FC=L

FC=H (or open)
0R

::J

0P

Do

0R

0P
Z

a::

LL

I-

::J

fr>fp

H

L

L

L

H

fr
Note:

VCO INPUT VOLTAGE _

Z=(High impedance)

Depending upon VCO characteristics. FC pin should be set accordingly:
When VCO characteristics are like
FC should be set high or open circuit;
When VCO characteristics are like
FC should be set Low.



>

.r.

~

.3

I

Cl

I
6.0

4-134

MB1504
MB1504H

(J)

I

"S

2.0

~

1\

I

(J)

Cl

~

o

-2
-3
-4
High-level Output Current 10H (rnA)

-1

-5

~

0.0

U

o

~~

10
Low-level Output Current 10L (rnA)

20

MB1504
MB1504H
MB1504L
Do PIN OUTPUT WAVEFORM AT LOCK CONDITION

Output Waveform

(

1V/div

i. . ___.. J
100nsldiv

MB1504

J

I
I

r

MB1504H

1

MB1504L

---- --

r

--/-

-

-- -----

J

/

4-135

MB1504
MB1504H
MB1504L
PHASE CHARACTERISTICS (M vs. DO OUTPUT ENERGY)

150

/
~~
lj/
~

100

I

50

§
I

'2
~

~

0

>.
~

100

80

40

60

~

1// V
~'

V~40

20

CD

c:

"

60

w

-50

-100

r--

1--

MB1504HI
- - MB1504
- - - MB1504L

I

/

-150

/
/"

~/

limedf (ns)

E
VP10k

D

10k

[

.

Oscilloscope

Vcc=Vp=3.0V ]
~Nsfosc=12MH

fr=fp=46.9kHz

4-136

,,"
",

.,,-- 10---

80

MB1504
MB1504H
MB1504L
INPUT SENSITIVITY

Input Sensitivity vs. Input Frequency (Supply Voltage Dependence)
10

E
!Xl

~

rr

0

'>

-10

z

Guaranteed
Operating Area
Vcc=4.0 to S.SV

~

:0=

III

'ii)

c:

Q)

C/)

-20
:5
Q.
£:
-30

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

Vee

1.2

Vp

Input Frequency fiN (GHz)

9 10 11 12 13 14 15 16

Oscilloscope

Input Sensitivity vs. Input Frequency (Temperature Dependence)

10

~
~
z

rr
~

:0=

·wC.

0
-10

I
I
Guaranteed
Operating Area
Vcc=4.0 to S.SV

Vcc~2.7V t~ 4.0V
~A=-40°C

\

Q)

C/)

'5

-20

Q.

.E

-30

~

:::. ;;;; ~

,)

~"

!

I
~ TA=+2S C

i I

, --~ ~ '-.. TA=+8SoC

~

I

-

Vcc=3.0V

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

Vp

1.2

Input Frequency fiN (GHz)
87654321
9 10 11 12 13 14 15 16

Oscilloscope

4-137

MB1504
MB1504H
MB1504L
INPUT IMPEDANCE

lOMHz
lOOMHz
200MHz
500MHZ

I

.ii.Ui"=:'
I
!I

..... au.,~ ...~It'

.
• ,
...
"'"
. ·-~""'~'·fll.
J

,f,T10';;.':;.-....

~,,\. •
~'i'

,.

'.!

•

:

~!

I

,
:I

:

~ ~

I
!

~

L,. ;"

,j".!

I : ;

:;.

•

•

:

,

.,

:

".

,'"

'-I
i';~'~;

!-...!..--.!Ji;
~ ~ ~;.

;::;

TEST CIRCUIT
Do Pin Output Current (IOH, lod Measurement

Vee

Vp

Do""'-- 10L
MB1504

4-138

MB1504
MB1504H
MB1504L
Lock u Time Measurement

Oscilloscope (10MO, 10pF)

III

LPF Circuit

(

Vcc=3V, Vp=8V
]
fvco=Low unlock condition ~ Step to Lock condition (533MHz)
fvco=High unlock condition ~ Step to Lock condition (518MHz)

Phase Characteristics Measurement

vee

Vp
....,...----~-

10kO

10kQ
Oscilloscope
(10MQ, 10pF)

1---- - - - - - -

fp

(

V cc=3V. Vp=3V
Llf=fr-fp
Energy (En)=V 2 t

4-139

MB1504
MB1504H
MB1504L

TYPICAL APPLICATION EXAMPLE
..-_ _ _-. OUTPUT

FROM
CONTROLLER

~}
0R

16

FC

0P
15

14

12

13

Data

LE
10

11

MB1504

2
OSC'N

3
OSCOUT

4
Vp

5
Vee

678
Do

GND

LD

1000pF

6V

Vec(3V)

3V

LOCK DET.

V p• Vpx 8V max.
C1. C2 Depends on crystal oscillator
LE.FC
With internal pull up resistor
0P
Open drain output

4-140

MB1504
MB1504H
MB1504L

PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No.: DIP-16P-M04)

r--

Inn

.770+·008(19.SS+0.20) _ _- . J
-.012
-0.30
i

~ rOO 0 0 0 0 c:'J I

INDEX-'i - - INDEX·2 /'

V. LJ
.1
,I .

.

039

(0.99~·30)

©1991 FUJITSU LIMITED D16033S·2C

1-

r-:::::~:-T!

-------r~~~)3Wp~2)~

LJ LJ Q ~ ~ ~ ~ CJ

~012

1S°(v1AX

.11 . .060~012

(1.52 ~.30)

i

-'.010±.002
(0.25±0.05)

Dimensions in
inches (millimeters)

4-141

MB1504
MB1504H
MB1504L

PACKAGE DIMENSIONS
16-LEAD PLASTIC FLAT PACKAGE
(Case No.: FPT-16P-M06)
~ 400+.010(1015+0.25 )--..
. -.008 . -0.20
•

I

I

(MOUNTING HEIGHT)
.002(0.05)MIN

r

:

m N O OFF HEIGHT)

1 I

.307±.016
(7.80±0.40)
.209±.012
(5.3o±O.30)

I

k!:;t:::::;1;=::;:;::=;::;:=;:::;::=r:;=::;:;~ -.-l

.050(1.27~ \
TYP

I

\..

(0.45±0.10)1'-'.:.......J-.- - - - - - - ' - - ' .

II
-4l-.006+.002(01.-+0.05)
-.001 . °-0.02

I oetallsOf ~"Part \
I
I

.016(0.40~

1

I
©1991 FUJITSU LIMITED F16015S-2C

4-142

L

,------Details of "S" part
1

:~:(0.15)'

I
I I ~:::::=:::::::t !,
I I
1
.008(0.20) :

I
I
I
I

~:g~~ (6.80 ~:jg)
.02o±.008
(0.5o±O.20)

J

I! ..018±.004 r-I~"'--'-I,...0.=00=5={O-,-.13=)-=@,.-,1

I

268

===t.

.008(0.20)1
.007(0.18) I

I

I

1

MAX
.0270.68
___

I

~~_.J

.007(0.18) :

MAX

I

.027 0.68) :

1 _ _ _ _MAX
L
_ _ _I

Dimensions in
inches (millimeters)

00

June
Edition O.2a

FUJITSU

1995

MB15E05/EOli=~~p,~'rod~UC~tPfi~'Om~eS~'hee~t~=====--_
On-chip 2.0GHzl2.SGHz PRESCALER
The Fujitsu MB15E05lE06 are serial input Phase Locked Loop (PLL) frequency
synthesizers with a 2.0GHz (MB15E05) and a 2.5GHz (MB15E06) prescalers. A
64/65 or a 128/129 can be selected for the prescaler that enables pulse swallow
operation.
The latest BiCMOS process technology is used, resulting in a supply current of
6mA typo (MB15E05) and 7mA typo (MB15E06). They operate with
a supply voltage of 3.0V (typ.).
Furthermore, a super charger circuit is included to get a fast tuning as well as low
noise performance. As a result of this, MB 15E05lE06 are ideally suitable for digital
mobile communications, such as PCN(Personal Communication Network},
PCS(Personal Communication Service}, Wireless LAN etc.

FEATURES
• High frequency operation MB15E05: 2.0GHz max.
MB15E06: 2.5GHz max.
• Low power supply voltage: Vee =2.7 to 3.6V
• Very Low power supply current: MB 15E05 : lee = 6.0 mA typo (Vee = 3V)
MB15E06: Icc =7.0 mA typo (Vee =3V)
• Power saving function: Ips = 10 ~ max. (Vee = 3V)
• Pulse swallow function: 64/65 or 128/129
• Serial input 1~-bit programmable reference divider: R = 5 to 16383
• Serial input 18-bit programmable divider consisting of:
- Binary 7-bit sw&lIow counter: 0 to 127
- Binary 11-bit ,rogra.mmable counter: 5 to 2047
• Wide operating temperature: TA = -40 to 85°C
• Plastic 16-pin SSOP package (FPT-16P-M05)

ABSOLUTE MAXIMUM RATINGS (SEE NOTE)

FPT-16P-MOS

PIN ASSIGNMENT

OSCin

Permanent device damage may occur if the above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in
the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

R

OSCout

2

15

P

Vp

3

14

LDlfout

Vcc

4

Do

NOTE:

16

TOP 13
VIEW
12
5

ZC
PS

GND

6

11

LE

Xfin

7

10

Data

fin

8

9

Clock

This device contains circuitry to protect the inputs against
damage due to high staticvoltaQ8S or electric fields. However,
~ is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high impedance circu~.

4-143

MB15E05
MB15E06

BLOCK DIAGRAM

Ir

~

____ ____
~

19-bit shift register
+-~~c

)}-------t--~--'-I ~ I

19-bit shift register

LE

r-----------,

sw

I

Programmable divider

I
I

Prescaler

I
I

64/65,
128/129

Ip

MD

4-144

MB15E05
MB15E06

PIN DESCRIPTION

III
8

fin

Prescaler input.
Connection with an external VCO should be done with AC coupling.

9

Clock

Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.)

10

Data

Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
Control bit = "H" ; Data is transmitted to the programmable reference counter.
Control bit = "L" ; Data is transmitted to the programmable counter.

11

LE

Load enable signal input (Open is prohibited.)
When LE is high, the data in the shift register is transferred to a latch, according to the
control bit in the serial data.

12

PS

Power saving control input. This pin should be set at "L" at Power-ON. (Open is prohibited.)
PS = "H" ; Normal mode
PS = "L" ; Power saving mode

13

ZC

Forced high-impedance control for the charge pump (with internal pull up resistor.)
ZC = "H" ; Normal Do output.
ZC = "L" ; Do becomes high impedance.

14

LDlfoUT

o

Lock detector output(LD)/Monitor pin of the phase comparator(fout).
A LOS bit in a serial data switchs LDlfout pin's output.
LDS = "H" ; outputs fout (frlfp monitoring output)
LDS = "L" ; outputs LD ("H" at locking, "L" at unlocking.)

4-145

MB15E05
MB15E06

FUNCTION DESCRIPTIONS
PULSE SWALLOW FUNCTION
The divide ratio can be calculated using the following equation:
fveo • [(M
fveo
N
A
fose
R
M

x N) + A] x fose + R (A < N)
: Output frequency of external voltage controlled oscillator (VCO)
: Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
: Preset divide ratio of binary 7-bit swallow counter (0 S A S 127)
: Output frequency of the reference frequency oscillator
: Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
: Preset divide ratio of modules prescaler (64 or 128)

SERIAL DATA INPUT
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the
programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high, stored data is latched
according to the control bit data as follows:

Table.1 CONTROL BIT

H

17 bit latch (for the programmable reference divider)

L

18 bit latch (for the programmable divider)

SHIFT REGISTER CONFIGURATION
Programmable Reference Counter

,

MSB

LSB
Data Flow - - - - - -

I
1

2

3

4

5

6

7

8

9

10

C

R

R

R

R

R

R

R

R

R

R

R

R

R

R

N

1

2

3

4

5

6

7

8

9

10

11

12

13

14

11

12

13

14

15

16

17

18

SW FC LOS

T
CNT
: Control bit
R1 to R14: Divide ratio setting bit for the programmable reference counter (5 to 16,383)
SW
: Divide ratio setting bit for the prescaler (64/65 or 128/129)
FC
: Phase control bit for the phase comparator
LOS
: LDlfout signal select bit
Note: Start data input with MSB first.

4-146

[Table.
[Table.
[Table.
[Table.
[Table.

1]
2]
5]
7]
6]

MB15E05
MB15E06

Programmable Counter
LSB

MSB

Data Flow-

t

t

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

C
N

A
1

A
2

A
3

A
4

A
5

A
6

A
7

N
1

N
2

N
3

N
4

N

N

5

6

N
7

N
8

N
9

N
10

N
11

T

eNT
: Control bit
N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047)
A 1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)

[Table. 1]
[Table. 3]
[Table. 4]

III

Note: Start data input with MSB first.

Table2. BINARY 14-BIT PROGRAMMABLE REFERENCE COUNTER DATA SETTING

Note: • Divide ratio less than 5 is prohibited.

Table.3 BINARY 11-BIT PROGRAMMABLE COUNTER DATA SETTING

5
6

o
o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o
o

2047
Note:. Divide ratio less than 5 is prohibited .
• Divide ratio (N) range = 5 to 2,047

4-147

MB15E05
MB15E06
Table.4 BINARY 7·BIT SWALLOW COUNTER DATA SETTING

Note:- Divide ratio (A) range", 0 to 127

Table. 5 PRESCALER DATA SETTING

H

64/65

L

128/129

Table. 6 LD/fout OUTPUT SELECT DATA SETTING

H

fout signal

L

LD signal

Relation between the FC Input and phase characteristics
The Fe bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level (Do) and the
phase comparator output (R. P) are reversed according to the Fe bit. Also. the monitor pin (fouT) output is controlled by the Fe bit.
The relationship between the Fe bit and each of Do. R. and P is shown below.

Table. 7 FC BIT DATA SETTING (LOS

="H")

L

(fr)

L

H

Z*

(fp)

(fr)

H

L

L

(fp)

(fr)

*: High impedance

4-148

L

MB15E05
MB15E06
When designing a synthesizer, the Fe pin setting depends on the veo and LPF characteristics.

CD
.: When the LPF and veo characteristics are
similar to CD, set Fe bit high.
.: When the veo characteristics are similar to
(2), set Fe bit low.

veo
output
frequency

,

" ,,
,

'®

II

LPF input voltage -

POWER SAVING MODE {INTERMITTENT MODE CONTROL CIRCUIT}
Setting a PS pin to Low, the Ie enters into power saving mode resultatly current sonsumption can be limited to 1O~A (max.).
Setting PS pin to High, power saving mode is released so that the Ie works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from the power saving mode. In
general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to
an undefined phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take
longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during
power up, thus keeping the loop locked.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving function
stops working, then current consumption is reduced to 1O~ per one PLL section.
At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high impedance.
A veo control voltage is naturally kept at the locking voltage which defined by a LPF"s time constant. As a result of this,
veo's frequency is kept at the locking frequency.
Note;. While the power saving mode is executed, ZC pin should be set at "W or open. If ZC is set at "L" during power
saving mode, approximately 1OJ.tA current flows .
• PS pin must be set "L" at Power-ON.

Table.8 PS PIN SETIING

H

Normal mode

L

Power saving mode

Table.9 ZC PIN SETTING

H

Normal output

L

High impedance

4-149

MB1SEOS
MB1SE06

SERIAL DATA INPUT TIMING

<:?

Data

MSB

L~
~~
,
,

X

__
: nL __fU1--Il
,

~ ~ ~=X

lS_B_ _ _ __

,

ClockJWl: 1n~
t

I

<:?

LE

__

•

:

---_.....,-,-,

....
't1:

I .

I,

':

rL

' , ' ,

"

,.. t~

I

ts-r--:--

...... t3--" '
'
t6~

~t7-:

~t4

On rising edge of the clock, one bit of the data is transferred into the shift register.

4-150

t1

20

ns

tS

30

ns

t2

20

ns

t6

100

ns

t3

30

ns

t7

100

ns

t4

20

ns

MB15E05
MB15E06
PHASE COMPARATOR OUTPUT WAVEFORM

fr
II
II

,, ,,
,

fp

-.: 1..____________
~Itwu

LD

-.:

,

'..-

, tWL

~I----------'1

II

[FC = "H" ]

4>P

4>R

u

I

--'--~__'______Jn'------'---_"_____'__

[FC = "L" ]

u
4>R

Notes:

~~n~~~I~'_____~~

1. Phase error detection range: -21t to +21t
2. Pulses on Do output signal during locked state are output to prevent dead zone.
3. LD output becomes low when phase is twu or more. LD output becomes high when phase error is tWL
or less and continues to be so for three cys/es or more.
4. twu and tWL depend on OSCin input frequency.
twu ~ 8/lose (e. g. twu 2! 625ns, f05ein = 12.8 MHz)
twLs16/lose (e. g. tWL oS 1250n5, fosein = 12.8 MHz)

5. LD becomes high during the power saving mode (PS = "L".)

4·151

MB15E05
MB15E06

RECOMMENDED OPERATING CONDITIONS
II.
li.><

.........•..••.•..•......•.......••.....•.••..

>

/..•......... I·······• •••••••

.>i<)·.·.· ..........i. Ii

.....

........~

.........................

.

'

~?

Vee

2.7

3.0

3.6

V

Vp

Vcc

-

6.0

V

Input voltage

VI

GND

Vee

V

Operating temperature

TA

-40

-

+85

°C

Supply voltage

Notes: To protect against damage by electrostatic discharge, note the following handling precautions:
-

Store and transport devices in conductive containers.

-

Use properly grounded workstations, tools, and equipment.

-

Tum off power before inserting or removing this device into or from a socket.

-

Protect leads with conductive sheet, when transporting a board mounted device.

ELECTRICAL CHARACTERISTICS
•••••••••••••.•.......•.....••.•••.•••....•....•..•...........................

··.···.·.·.i ......\]!

.......

~

.....'

;

Power Supply Current *1

.............. .

MB15E05

lee

finlF = 2000MHz,
fosc = 12MHz

6.0

MB15E06

lee

finRF = 2500MHz,
fosc= 12MHz

7.0

Power Saving Current *2

Ips

10

IlA

MB15E05

fin

100

2000

MB15E06

fin

100

2500

3

40

-10

+2

dBm

500

Vee

mVp-p

Crystal Oscillator Operating Frequency
fin

fose
Pfin

Input Sensitivity
OSCin

=

min. 500mVp-p
50n termination (Refer
to the test circuit.)

Vose

*1: Conditions; Vee 3.0V, Ta 25°C, in locking state.
*2: Conditions; Vee = 3.0V, Ta = 25°C, in power saving state.

4-152

rnA

Vee current at PS ="L
and ZC = "H""

Operating Frequency

=

•••••••••••••
........

MHz

-

MB15E05
MB15E06

ELECTRICAL CHARACTERISTICS

Input Voltage

/

.....•.... .c .•
........... .. ..
:

,

...

...

;;; ... - ,~/:.
. .:....:.. ,.. : .: ..,...,.,::...:

..:..........:••.. :.:.: .....:.:c ••:...

.

...

.... :

•.• Mln

I ..

VOL

-

-

0.4

VOOH

Vcc-O.4

-

-

VOOL

-

-

0.4

Do

10FF

-

-

1.1

~

<1>P

10L

1.0

-

-

rnA

10H

-

-

-1.0

10L

1.0

-

-

-10.0*1

-

-

10.0*1

-

VIL

-

IIH

-1.0

IlL

-1.0

IIH

-1.0
Pull up input

-100

IIH

0

IlL

-100

R.
LDlfout

VOL

Open drain output

-

Do

Output Current

Typ}

VOH

VccxO.7

IlL

P

High Impedance
Cutoff Current

I

Vcc-O.4

ZC

VIH

OSCin

Output Voltage

. ,,<10_
-

Data. Clock
LE.PS.ZC

Data. Clock.
LE.PS

Input Current

Sy~bOI

<1>R.
LDlfout

Do

V
VccxO.3
+1.0
~

+1.0
+1.0
0
+100

~

III

~

0
0.4

-

V

V

V

100H
looL

Open drain output

Vec 3.0V. Vp = 5V.
VOOH = 4.0V
Vec 3.0V. Vp = 5V.
VOOL = 1.0V

rnA

rnA

*1: Condition; Ta = 25°C

4-153

MB15E05
MB15E06

TEST CIRCUIT
(FOR MEASURING INPUT SENSITIVITY fin/OSCin)
Vee

P'G

Vp

~ooo:OOOP
50 n

10~00P

~---L----'-_...L..-..J..----L--.

8

765

432

P'G

50 n

1

9 10 11 12 13 14 15 16
L - -_ _ _ _~

4·154

Oscilloscope

MB15E05
MB15E06

APPLICATION EXAMPLE

Vpx (6V)

12k

To a lock detect.

III

12k

] From

a controller

fp

Note:

tz

w
::>

Z

T

~------------------~
veo INPUT VOLTAGE -

4-162

Do

Do

VCO CHARACTERISTICS
Depending upon VCO characteristics,
FC pin should be set accordingly:
- When VCO characteristics are like 1,
FC should be set High or open circuit;
- When VCO characteristics are like 2,
Fe should be set Low.

MB1505

fr

fp

LD

Do

U
U U
L
---~
: - - - - - - - - - z - - - -lJL -------u ----LJ ---L
~

U

I

fr > fp

fr = fp

I

I

I

I

I

I

fr < fp

fr < fp

fr < fp

NOTES: Phase difference detection range: -21t to +21t
Spike appearance depends on charge pump characteristics. Also, the spike is output in order to diminish dead band.
When fr > fp or fr < fp, spike might not appear depending upon charge pump characteristics.

ANALOG SWITCH
ON/OFF of analog switch is controlled by LE input signal. When the analog switch is ON, internal charge pump output (Do) to be
connected to BISW pin. When the analog switch is OFF, BISW pin is set to high-impedance state.
LE=H (Changing the divide ratio of internal prescaler) : Analog switch=ON
LE=L (Normal operating mode): Analog switch=OFF
LPF time constant is decreased in order to insert a analog switch between LPF1 and LPF2 when channel of PLL is changing.
Thus, lock up time is decreased, that is, fast lock up time is achieved.

CHARGEPUMP~--~--~
I

L _ _ _ _ _ _ _ _ _ _ _ _ _ ""

: BISW
(CONTROL SIGNAL) _ _---'

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .JI

RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol

Value
Max

Unit

Min

Typ

Vcc

4.5

5.0

5.5

V

Vp

Vee

Vp

8.0

V

Input Voltage

VI

GND

Vee

V

Operating Temperature

TA

-40

85

°C

Power Supply Voltage

4-163

MB1505

ELECTRICAL CHARACTERISTICS
Value
Symbol

Parameter

Condition
Min

Power Supply Current

Icc

Note 1

fin

fin

Note2

OSCIN

fosc

Typ

Unit
Max

6.0
10

mA
600

MHz

20

MHz

6

dBm

Operating Frequency
12

-4

fin

Ptln

OSCIN

Vase

0.5

Except fin
andOSC'N

VIN

Vee xO .7

Data
Clock

IIH

1.0

!LA

IlL

-1.0

!LA

OSCIN

losc

±50

!LA

LE,FC

ILE

-60

!LA

Input Sensitivity
High-level Input Voltage
Low-level Input Voltage
High-level Input Current
Low-level Input Current

Vpp
V
VccxO .3

V,L

Input Current

High-level Output Current
Low-level Output Current
N-channel Open Drain Cutoff
Current

Output Current

Analog Switch On Resistor

NOTE:

4-164

Vcc=5 V

V

V

4.4

Except Do
andOSCOUT

VOH

Do.0P

IOFF

Except Do
and OSCOUT

IOH

-1.0

mA

IOL

1.0

mA

VOL
Vp=Vcc t08V
VOOP= GND to 8V

RON

1: fin = 600MHz, OSCIN=12MHz, Vcc=5V.lnputs are grounded and outputs are open.
2: AC coupling. Minimum operating frequency is measured when a capacitor 1000pF is connected.

25

0.4

V

1.1

JLA

Q

MB1505

TEST CIRCUIT
Vp=6V

P.G~~rP_F~~~ ~~L-1-_
__

50n%

5 4 3 2
MB1505

Oscilloscope

4-165

MB1505

TYPICAL APPLICATION EXAMPLE
, - - - - - . . OUTPUT

Charge Pump
Selection
(Internal or
external)
FROM
CONTROLLER

r----e-----o }

0P

0R
16

15

FC

13

14

12

LE

Data

11

10

6

7

MB1505

2
OSCIN

4

3
OSCou

Vp

5
Vee

Do

GND

8
LD

0
5V

6V

1 1
C1

2

C
0.1f.1F

Vp, Vpx

c1, C2

LE, FC

0P

4-166

Vee (5V)

1000pF

X'tal

1

8Vmax
Depends on crystal oscillator
With internal pull up resistor
Open drain output

LOCK DET
0.01f.1 F

I

10kn

MB1505

PACKAGE DIMENSIONS
16-Lead Plastic Dual In-Line Package
(Case No.: DIP-16P-M04)

INDEX-1

~======~=======~--t
.244±.010
(6.20±0.25)

INDEX-2

.300(7.62)
TYP

~;::::;::;:::::;:::::;::::;~:;::::;=::;:::::;::::;::::::;~

©1991 FUJITSU LIMITED D16033S-2C

Dimensions in
inches (millimeters)

4·167

MB1505

PACKAGE DIMENSIONS
16-Lead Plastic Flat Package
(Case No.: FPT-16P-M02)
.089(2.2S)MAX
(MOUNTING HEIGHT)
.002(0.05)MIN
(STAND OFF HEIGHT)

---t----;-j
.268 :::g6~

(6.80::g:~g)

1000000S

.OSO(1.27~ 1
TYP

I.

11===t

II .o18±.o04
• • (O.4S±0.10)1-$-,0.00S(0.13)@ ,
"A"

(O.5O±O.20)

-H-- .006 :::gg~ (0.15 ~:g~)
r-

Oet;;l~;:-A:P;rt-,

I
I
I
I
I
.020(0.SO) I
II
.0070.18)
MAX
I
.027(0.68)
I

1 - - - - - ( .08(0.20)

_ _ _ _ ~~_ _ .J
©1988 FUJITSU LIMITED F1600SS-4C

4-168

Dimensions in
inches (millimeters)

00

~D~so~~~213~1~~1~E~~~~~~~~==~_ _ FUJITSU

~

DATA SHEET

MB1506 ASSP for DTS Bi-CMOS (For 2.0 GHz band)
PLL Frequency Synthesizer with Built-in Prescaler
• DESCRIPTION
The Fujitsu MB1506 is a PLL (phase-locked loop) frequency synthesizer, ideally suited for DBS tuner, MeA radio
and similar wireless communications devices.
The MB1506 features a 2.0 GHz, two-modulus prescaler to enable pulse-swallow type processing, as well as
analog switches for faster lock up time.

III

Fujitsu's Bi-CMOS process is used for low power consumption of Icc = 18 mA (typ.) .

• FEATURES
•
•
•
•
•

High speed operation: fin = 2.0 GHz
Low power consumption: Icc = 18 mA (typ.)
Wide operating temperature range: Ta = -40°C to +85°C
Two types of phase comparator output (built-in charge pump, external charge pump)
Built-in functions:
16-bit shift register
15-bit latch
Reference frequency divider
Binary 14-bit programmable reference counter (divide ratio: 8 to 16383)
1-bit switch counter
19-bit shift register
19-bit latch
(Continued)

• PACKAGE
Plastic SSOP, 20-pin

(FPT-20P-M03)

Copyright@ 1995 by FUJITSU LIMITED

4-169

MB1506
(Continued)
Comparison dividers
Binary 8-bit swallow counter (divide ratio: 0 to 255)
Binary 11-bit programmable counter (divide ratio: 16 to 2047)
Phase comparator with phase conversion function
2.0 GHz band two-modulus prescaler (divide ratios: 128/129,256/257)
Control signal generator circuit
Crystal oscillator circuit
Monitor frequency switching circuit
Charge pump
1-bit control latch
Analog switch

• PIN ASSIGNMENT

(Top view)

~R

OSCIN
N.C.

N.C.

,p

OSCOUT

Vp

fout

Vee

BiSW

Do

FC

GND

LE

Data

LD
N.C.

N.C.

fin

Clock

(FPT-20P-M03)

4-170

MB1506

• PIN DESCRIPTION
Pin No.
1

Pin name

Descriptions

110

OSCIN

I

Crystal oscillator connection pin for reference divider (OSCIN
circuit input pin, and OSCOUT = oscillator circuit output pin)

= oscillator

3

OSCOUT

0

4

Vp

-

5

Vcc

-

Power supply pin

6

Do

0

On-chip charge pump output pin
Phase characteristics may be inverted according to the setting of the FC pin.

7

GND

-

GND pin

8

LD

0

Phase comparator output pin
Normal setting isLD = "H" with an output signal LD
duration of the phase error between fr and fp.

Power supply pin for charge pump output and analog switch output

= "L" equivalent to the

10

fin

I

Prescaler input pin
Use in an AC coupled state.

11

Clock

I

Clock signal input pin for 19-bit shift register and 16-bit shift register
Data is read on the rising edge of the clock pulse.

13

Data

I

Serial data input pin for binary coded data
The final data bit is the control bit.
Control data

.-

Serial data transfer destination

H

15-bit latch

L

19-bit latch

14

LE

I

Load enable signal input pin (with pull-up resistor)
When LE = "H" or LE = "OPEN", the contents of the shift register is
transferred to one of the latches according to the combination of serial data
control bit settings. Also, when the internal analog switch is "on" at this time,
the signal output from the internal charge pump is sent to the BiSW pin.

15

FC

I

Phase comparator phase switching pin (with pull-up resistor)
Enables inversion of the polarity of the phase comparator output, according
to the polarity of externally connected LPF or VCO. When FC = "L" the
charge pump and phase comparator characteristics are inverted.
Also switches the output of the fout pin, either fr or fp.

16

BiSW

0

Analog switch output pin
Normally in high-impedance state, outputs the status of the internal charge
pump only when the switch is turned on (LE = "H").

17

fout

0

Phase comparator input monitor pin
According to the FC pin input level, this pin outputs either the output signal
from the reference divider (fr) or the comparison divider (fp).
Fe

III

Output signal

H

fr output equivalent

L

fp output equivalent
(Continued)

4-171

MB1506

(Continued)

18

cliP

110
! 0

20

cIIA

i 0

Pin No.

2,9,12,
19

4-172

Pin name

N.C.

-

Descriptions

Phase comparator output signal pin for external charge pump
Phase characteristics may be inverted according to the FC pin setting.
The cliP pin is N channel open-drain output.
No connection.

MB1506

• BLOCK DIAGRAM

:---------------1
16-bit shift register
16-bit shift register
fout

FC
LE

III

LD

cpR
OSC'N

4tP

Analog switch

1-----------------------I

1

19-bit shift register
19-bit shift
register

:-_-_-_-_-_-_-_-_-_-_-_-.:I:,-_-_-_-_-_-_-_-_-_-_:
fin
1
1

1

~- ---- ~ -------- ~ ~ -- ~j.~ ---- ~ ~ ~ -------- ~
Comparison divider

.. : Data signal

~_________-_ _:_c_o_n_tr_ol_S_ig_n_a_I________________________________________________________________~4-173

MB1506

• FUNCTIONAL DESCRIPTION
1. Divide Ratio Settings
Setting values should be determined according to the following formula:
fveo

= [(M x N) + A] x fose + R

(A < N)

fvco: Externally connected VCO output frequency
M: Prescaler frequency division ratio (128 or 256)
N: Binary 11-bit programmable counter setting (16 to 2047)
A: Binary 8-bit swallow counter setting (0 :5 A :5 255)
fose: Reference oscillator frequency
A: Binary 14-bit programmable reference counter setting (8 to 16383)

2. Serial Data Input Methods
Serial data input uses three pins. the Data pin. Clock pin and LE pin. and is used to separately control the 15-bit
reference divider and 19-bit comparison divider.
Serial data should be input in binary form at the Data pin.
Serial data is read sequentially by the shift register at the rise edge of the clock signal. and is transferred to a latch
together with the appropriate control data when the load enable signal goes to "H"level (or open).
Control data ! Serial data transfer destination
H
L

4·174

I
I

15-bit latch
19-bit latch

MB1506

(1) Divide Ratios in the Reference Divider
The reference divider is configured with a 16-bit shift register, 15-bit latch and 14-bit reference counter. The serial
data configuration has 16 bits, as shown below.

III
Programmable reference counter divide
ratio setting bits
• 14-bit programmable reference counter divide ratios
Divide
ralio R
8

I

S S S S
14 13 12 11

S
10

S
9

S
8

S

S
6

S

7

5

S
4

S
3

S
2

S
1

0

0

0

0

0

0

0

1

0

0

0

0

0

1

1

1

1

0

0

0

9

0

0

0

0

0

0

0

0

0

0

1

16383

1

1

1

1

1

1

1

1

1

1

1

Note: Divide ratio of less than 8 are prohibited.
(Setting value range: 8 to 16383)

I

L - -_ _ _ _ _ _

Data should be input with the M8B first.
8W: Prescaler divide ratio setting bit.

sw

!I

H

I

128/129

L

I

256/257

Prescaler divide ratio setting bit

81 to 814: Divide ratio setting bit (8 to 16383)
C: Control bit (set to "H")

4·175

MB1506

(2) Divide Ratios in the Comparison Divider
The comparison divider is configured with a 19-bit shift register, 19-bit latch, 8-bit swallow counter and 11-bit
programmable counter. The serial data configuration has 19 bits, as shown below.

----------------------------------------------

Swallow counter divide
ratio setting bits
• 7-bit swallow counter divide ratios

Programmable counter divide
ratio setting bits
• 11-bit prgrammable counter divide ratios
S ! 5
5
5
S 5
5 I 5 5
19 18 17 16 15114 13 12 11

5
7

5
6

5
5

5
4

S
3

5
2

5
1

0

0 1 0
I

0

0

0

0

0

0

16

0

0

0

0

0

0

1

0

1

0

0

0

0

0

0

0

1

17

0

0

0

0

0

0

1

0

1

1

1

1

1

1

1

1

2047

1

1

1

1

1

1

1

Divide
ratio A

S
8

255

(5etting value range: 0 to 255)

Divide
ratiO N

5
10

5
9

0

0

0

0

0

1

1 I 1

1

1

I

Note: Frequency divide ratios of less than 16 are
prohibited. (setting value range: 16 to 2047)

Data should be input with the MSB first.
S1 to S8: Swallow counter divide ratio setting bits (0 to 255)
S9to S18: Programmable counter divide ratio setting bits (16 to 2047)
C: Control bit (set to ilL")

3. Serial Data Input Timing

MS • XStS

Data S19

(5W)

:

(S14)

:.:~:
(56)

(57)

(S1)

(c: control bit)

CIOC"11m. .. JLJ1 .. JUL

•

LE

t,~

t,

10

t2 ...· - - -

rL

tJ -:---:- t ....- - - - - : -....
ts~

ts ;: 1 ~s

Items 10 parentheses ( ) apply when setting divide ratios for the reference divider.
Data is read at the rising of the clock signal.
L ____________________________
_

4-176:

MB1506
4. FC Pin Input and Phase Characteristics
The Fe pin is used for switching of phase relation in the phase comparator. This pin controls the inversion of phase
characteristics in the internal charge pump output (Do) and phase comparator output (cpR, cpP).
In addition, the output from the phase comparator input monitor pin (fout) can be controlled from the Fe pin. The
following table shows the relation between Fe pin settings and the Do, cpR, cpP, and fout settings.

~

FC: "H" or open
Do

cpR

cpP

FC: "L"

i

i

fout

I

I.

Do

I

cpR

i

cpP

fr> fp

H

L

L

(fr)

L

H

Z

fr = fp

Z

L

Z

(fr)

Z

L

Z

fr< fp

L

H

Z

(fr)

H

L

I

i
I

L

Z: High impedance
In phase locked loop design, the

I
I

fout

I
I

(fp)

(fp)

(fp)

•

Fe pin should be controlled by veo polarity.

(1)

When veo polarity is represented by
line (1), Fe value is "W or open.
When veo polarity is represented by
line (2), Fe value is "L".

..............
••••••••••••. (2)

veo input voltage

4-177

MB1506

The following diagram illustrates the phase comparator output waveform (Fe

="H").

fr~

L

fp

u

LOU
00

u

L

--~-Jr---z------~--LJ--LJ-L
fr > fp

fr '"' fp

fr < fp

fr < fp

fr < fp

• The phase error detection range is -2 7t to +2 7t.
• Differences in charge pump characteristics may cause slight variation in spikes. The spike is output in order
to eliminate dead zones.
• Depending on charge pump characteristics, the spike may not be output when fr > fp, or when fr < fp.

5. Analog Switch
The analog switch is turned on/off by the LE signal. When the switch is on, the output signal from the internal
charge pump (Do) is output to the BiSW pin (when off, the pin remains in high impedance state).

I

Analog switch

H (when internal dividers' setting is changed.)

j

On

L

I

Off

LE

As illustrated below, the analog switch can be inserted between the LPF (LPF1 + LPF2) so as to reduce the LPF
time constant during PLL channel switching, thereby resulting in faster lock up time.

!SiSW

(Control signal LE)

----------

4-178

MB1506

• ABSOLUTE MAXIMUM RATINGS
Parameter

I

Symbol Ii
Vee

Power supply voltage

Value
Min.

I

-0.5

i

Unit

Max.

i

7.0

!

V

i

V

Vp

Vee

10.0

Output voltage

VOUT

-0.5

Vee + 0.5

Open drain voltage

Voop

-0.5

8.0

Output current

lOUT

-10

10

Storage temperature

Tstg

-55

+125

V

II

V
\

mA
°C

• RECOMMENDED OPERATING CONDITIONS
Parameter

I

Vee

Power supply voltage
Input voltage
Operating temperature

Symbol

I

Value

I

Min.

I

4.5

i

i T -

VP

Vee

VIN

GND

Ta

-40

i

r

Typ.

Max.

5.0

5.5

Unit
V

8.0

V

Vee

V

+85

I

°C

Note: Protection against damage from static electricity has been provided by the addition of anti-static elements
and precautionary measures in circuit design, however the following precautions are advised when
handling:
• Always place the MB 1506 in a conductive case for storage and transporting.
• Before handling, ensure that al\ operators, fixtures and tools are protected from electrification (grounded),
and provide a grounded conductive sheet on the operating floor.
• Always ensure that power is switched off before inserting the device into or removing the device from any
socket.
• When handling (or transporting) any circuit board containing an MB1506 device, all leads should be
protected with electro-conductive sheeting.

4-179

MB1506

• ELECTRICAL CHARACTERISTICS

(Vee

Symbol

Parameter
Power supply current *,
Operating frequency

!
: 1in*2
!

OSCIN
fin*3

Input sensitivity

: OSCIN

H level input voltage

Except fin,
OSCIN

L level input voltage
H level input current

Data, Clock

I

Value
Min.

Icc

-

fin

10

fose

-

Pfin

Vose
VIH
V,l
IIH

= 4.5 V to 5.5, Ta = -40°C to +85°C)

I

Typ.

I

18.0

I

-4

!

20

MHz

-

6

dBm

-

Vp-p

Vee x 0.7l
- I 1.0
±50

!

-60

I
I

-

!

0.4

LE,FC

IlE

4.4

L level output voltage

Except 00*4,
OSCOUT

VOH
VOL

High impedance cutoff current

00*5, q,P

IOFF

-

I Except Do,

10H

-1.0

-

OSCOUT

10l

1.0

-

RON

-

25

Output current
Analog switch on resistance

I

I

I

I
I

I

-1.0

-

MHz

V

Vee x 0.3

-

-

H level output voltage

I

I

lose

Input current

mA

I
I

OSCI

i

i

12

0.5

;

2000

-

i

I
1

Unit

Max.

i
i

III

L level input current

i

I

1.1

-

V
~
~
~
~

l

V
V

I

I

~

mA
I

!

mA
Q

"1: Power supply current measurement conditions: Connection to a crystal with Vee =5 V, fiN = 2.0 GHz, fose = 12
MHz.
*2: AC coupled. Minimum operating frequency is measured with a coupling of 1000 pF.
*3: 50 n system
*4: AtVee=5V
"5: Vp = Vee to 8 V, Voop =GND to 8 V

4-180

MB1506

• MEASUREMENT CIRCUIT (Prescaler Input Sensitivity Measurement)

Vee. 5 V

X'tal

Vp.6V

1000pF

p·G

~

II
Oscilloscope

4-181

MB1506

• APPLICATION EXAMPLE

VPJ. (6 V)

OUTPUT

.-----------QFrom
controJer

47 kQ

47 kQ

MB1507

O.01I1 F

I

VPX, Vp: 8 V (maximum)
C1, C2: determined by crystal oscillator
LE, FC: with pull-up resistor
cj>P: open-drain output

• ORDERING INFORMATION
Part number

MB1506PFV

4-182

Package

20-pin Plastic SSOP
(FPT-20P-M03)

Remarks

MB1506

• PACKAGE DIMENSION
Plastic SSOP, 20 pin
(FPT-20P-M03)

~

l

·4.40:1:0.10 6.40:1:0.20

•

l

5.40(.213)

~u~QJ~)/J
0.15~::
.000::~l

5.85!.2301REF

~ De~~ ~f -::A-:

;rt- -------- I

I
I

I
I
I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

J

Note: Items with asterisk (") do not include resin residue.
@

1994 FUJITSU UMITEO F200125-2C-4

Dimentions in mm (inches)

4-183

4-184

00

September 1995
Edition 4.0a

FUJITSU

DATA SHEET

MB1507
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 2.0GHz PRESCALER
The Fujitsu MB1507 is a single chip serial input PLL frequency synthesizer designed for
Broadcast Satelite tuner and cellular telephone applications.
It contains a 2.0 GHz dual modulus prescaler which enables pulse swallow function, and an
analog' switch to speed up lock up time.
It operates supply voltage of 5.0Vtyp. and dissipates 1BmA typo of current realized through the
use of Fujitsu's unique U-ESBIC Bi-CMOS technology.
•

High operating frequency: fiN MAX=2.0GHz (PIN MIN=-4dBm)

•

Pulse swallow function: 128/129 or 2561257

•

Low supply current: Icc=18mA typo

•

Serial input 19-bit programmable divider consisting of:
o Binary 8-bit swallow counter: 0 to 255
o Binary 11-bit programmable counter: 16 to 2047

•

Serial input 15-bit programmable reference divider consisting of:
o Binary 14-bit programmable reference counter: 8 to 16383
o 1-bit switch counter (SW) Sets divide ratio of prescaler

•

On-chip analog switch achieves fast lock up time

•

2types of phase detector output
o On-chip charge pump (Bipolar type)
o Output for external charge pump

III
PLASTIC PACKAGE
FPT-16P-M06

PIN ASSIGNMENT

0

•

Wide operating temperature: -40 C to +85°C

•

16-pin Plastic Flat Package (Suffix: -PF)

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating
Power Supply Voltage

Symbol

Value

Unit

Vcc

-0.5 to +7.0

V

Vp

Vccto 10.0

V
V

Output Voltage

VOUT

-0.5 to Vee +0.5

Open-drain Voltage

Voop

-0.5 to 8.0

V

Output Current

lOUT

+10

rnA

Storage Temperature

TSTG

-55 to +125

°c

NOTE:

Permanent device damage may occur If the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

This device contains circuitry to protectlhe inputs against
damage due to high static voltages or electric fields. However, nis advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance circuit.

Copyrlght© 1995 FUJITSU LIMITED and FUJITJU MICROELECTRONICS, INC.

4·185

MB1507

MB1507 BLOCK DIAGRAM

r-----------,
16-BIT SHIFT REGISTER
I

I

I

16-BIT SHIFT REGISTER

~I{]I{]IDID:::~

I

15-BIT LATCH

~-

LATCH
_15-BIT
__
_ _..

I
I

LIGIDIGID:::.J

rPROGRAMMABLE REFERENCEl
1DIVIDER
1

1

BINARY 14-BIT
REFERENCE COUNTER

......- - t....

1-------..... .J
L.. _ _ _ _ _ _ _ _ _ _ _

DO

5~----_+r_----------_+~-+_------~

.--------------+---------~---~11 LE

4-186

MB1507

PIN DESCRIPTION
Pin No.

Pin Name

110

1
2

OSCIN
OSCoUT

I
0

Oscillator input.
Oscillator output.
A crystal is placed between OSCIN and OSCoUT.

3

Vp

-

Power s~y iJl)ut for charge pump and analog switch.

4

Vee

-

Powers~yvOHageiJl)ut.

5

Do

0

Charge pUfT1) output.
The characteristics of charge pump is reversed depending upon FC input.

6

GND

-

Ground.

7

LD

0

Phase comparator output.
NormaUy the output level is high level. While the phase difference of f, and fp exists, the output becomes low level.

8

fiN

I

Prescaler input.
The connedion with VCO should be AC connection.

9

Clock

I

Clock input for 2O-bit shift register and 16-bit shift register.
On rising edge of the clock shifts one bit of data into the shift registers.
Binary serial data input.
The last bit of the data is a control bit which specified destination of shift registers. When this bit is
high level and LE is high level, the data stored in shift register is transferred to 15-bit latch. When
this bit is low level and LE is high level, the data is transferred to 19-bit latch.

DMc:rIptlon

10

Data

I

11

LE

I

12

FC

I

13

BISW

0

Analog switch output.
Usually BISW pin is set high-impedance state. When internal analog switch is ON (lE pin is high
IeveO, this pin outputs intemal charge pump output.
Monitor pin of phase comparator input.
fout pin outputs programmable reference divider output (fr) or programmable divider output (fp) depending upon FC pin iJl)ut level.
FC=H: It is the same as fr oulput level.
FC=L: It is the same as fp output level.

14

fOUT

0

15
16

0P
0R

0
0

II

Load enable iJl)ut (with puH up resistor).
When LE is high or open, the data stored in shift register is transferred into latch depending upon thE
control bit. At the time, internal charge pump output to be connected to BISW pin because intemal
analog switch becomes ON state.
Phase select input of phase corJl)arator (with pull up resistor).
When FC is low level, the characteristics of charge pump, phase comparator is reversed.
FC pin iJl)ut signal controls fout pin (test pin) output level, fr or fp.

Outputs for external charge pump.
The characteristics are reversed according to FC iJl)ut.
¢p pin is N-channel open drain output.

4-187

MB1507

FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable reference divider
and 19-bit programmable divider, respectively.
Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored data is
transferred into latch depending upon the control bit.
Control data oW data is transferred into 15-bit latch.
Control data "L" data is transferred into 19-bit latch.

THE DIVIDE RATIO SETTING
fveo..(MxN}+AJxfosc+R
fvco: Output frequency of external voltage controlled oscillator (VCO)
M:
Preset modulus of external dual modulus prescaler (128 or 256)
N:
Preset divide ratio of binary 11-bit programmable counter (16 to 2047)
A:
Preset divide ratio of binary 8-bit swaHow counter (O~55, A output level of phase comparator is controlled by FC pin input level.

>-

~

w

::J

o
w

FC=L

FC=H or open

ex:

LL

Do

0R

0P

fout

Do

0R

0P

fout

f,>fp

H

L

L

(fr)

l

H

Z

(fp)

f,=fp

Z

L

Z

(fr)

Z

L

Z

(fP)

t,..:fp

L

H

Z

(fr)

H

L

l

(fP)

~

Il.

Not.:

Z=(High impedance)

Depending upon VCO polarity. FC pin should be set accordingly:
FC should be set High or open circuit;
When VCO polarity are like
FC should be set low.
When VCO polarity are like

1p

U

frcfp

fr1p or fr

Sept. 1995
Edition 2.0a

FUJITSU

DATA SHEET

MB150B
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
SERIAL INPUT PLL
FREQUENCY SYNTHESIZER
ON CHIP 2.5 GHz PRESCALER
DESCRIPTION
The Fujitsu MB1508 with an on chip 2.5 GHz dual modulus prescaler is a serial input
PLL (Phase Locked Loop) frequency synthesizer with pulse swallow function. It is
well suited for BS tuner, CATV system, and TV tuner applications.
It operates with a supply voltage of 5.0V typo and dissipates 16mA typo of current
realized through the use of Fujitsu's unique U-ESBIC Bi-CMOS technology.

Plastic Package

FEATURES
• Power supply voltage: Vcc =4.5 to 5.5V

FPT-20P-M01

• High operating frequency: fiN = 2.5 GHz (PIN =--4dBm)
• 2.5 GHz dual modulus prescaler: P =256/272,512/528
• low supply current: Icc =16mA typo
• Programmable reference divider consisting of:
Binary 2-bit programmable reference counter (R =256, 512, 1024, 2048)

Pin Assignment

• Programmable divider consisting of:
Binary 5-bit swallow counter (A =0 to 31)
Binary 12-bit programmable counter (N =32 to 4095)
• Wide operating temperature: --40°C to +85°C
• Plastic 20-pin Flat Package (Suffix: -PF)
(TOP VIEW)

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating
Power Supply Voltage

Symbol

Value

Unit
V

FC

LD

LE

fOUT

Data

Vcc

-0.5 to +7.0

Output Voltage

Vo

-0.5 to Vce +0.5

V

Output Current

10

±10

mA

OSCIN

TSTG

-55 to +125

°C

OSCou

Storage Temperature
NOTE:

Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded.Functlonal operation should be restricted to the conditions as detailed in the operational
sections ofthis data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Clock
VCC1

VeC2
fiN
GND2

liN
BC1

GND

BC2

D01

BC3

D02

BC4

This device contains circuHry to protect the inputs against
damage due to hi~ static voHages or electric fields. However,
H is advised that nonnal precautions be taken to avoid
application ofanyvoHage higherthan maximum ratedvoHages
to this hi~ impedance circuH.

Copyright @ 1991 by FUJITSU LIMITED

4-197

MB1508

MB1508 BLOCK DIAGRAM

LD

Ion

lOUT

17

~

BC2

BC1

GND2

BC3

BC4

15

lOUT

r----------,

FC

L--.......- - r - - - - - . I

L...-H----I

Monitor Frequency
Selector

Reference Counter
(R.256,512,1024,2048)

Charge Pump

Crystal
Oscillator

1

FC

4-198

0

LE

0

Data

0

Clock

~

VCC1

OSC.,

OSC OU l

r
GND1

9

10

DOl

D02

MB1508

PIN DESCRIPTIONS
Pin No. Pin Name

110

Descriptions

1

FC

I

Phase select input pin 01 the phase detector. This pin involves an internal pull up resistor.
When this pin is low. characteristics of the charge pump and phase detector can be reversed. This
input also selects fouT pin output level. either Ir or Ip. Please see on page 6.

2

LE

I

Load enable input pin. This pin involves a schmit! trigger circuit.
When this pin is high. the data stored in the shift register is transferred into the latch.

3

Data

I

Serial data of binary code input pin. This pin involves a schmit! trigger circuit.

4

Clock

I

Clock input pin 01 the 24-bit shift register. This pin involves a schmitt trigger circuit.
On rising edge of the clock shifts one bit ot the data into the shift register.

5

VCCI

-

PLL power supply voltage input pin

6
7

OSC",
OSCOUT

I
0

Oscillator input pin.
Oscillator output pin.
A crystal is connected between OSC'N pin and OSCOUT pin.

8

GND1

-

PLL ground pin.

9
10

001
002

0
0

Charge pump output pins.
Phase characteristics can be reversed depending upon FC pin input level.

11
12
13
14

BC4
BC3
BC2
BCl

0
0
0

Band switching output pins. (Open--{;ollector output)
Output is controlled by a band bit data. individually.
SCX-bit=H : SCX output transistor is ON.
SCX-bit=L BCX output transistor is OFF.
(X=l to 4)

15

to

I

Complementary input pin of !"'. Please connect to GND through a capacitor.

16

GND2

-

Prescaler ground pin.

17

fin

I

Prescaler input pin.
This signal is AC coupled.

18

VCC2

-

Prescaler power supply voltage input pin.

19

fouT

0

Monitor pin of the phase detector input.
lOUT pin outputs either 01 the programmable reference divider output frequency fr or programmable
divider output frequency fp depending upon the FC pin input level.
FC pin

20

LD

0

fout output signal

H

fr

L

fp

Phase detector output pin
Normally thiS pin outputs high While the phase difference between Ir and fp exists. this pin outputs
low.

4-199

MB1508

FUNCTIONAL DESCRIPTIONS
DIVIDE RATIO SEITING
Divide ratio can be set using the following equation:

An x fosc + R

fvco = {(P x N) + (16 x

fvco: Output frequency of an external voltage controlled oscillator (VeO)
P:
Preset divide ratio of an internal dual modulus prescaler (256 or 512)
N:

Preset divide ratio of binary 12-bit programmable counter (32 to 4095)

A:

Preset divide ratio of binary 5-bit swallow counter (0 to 31)

fosc: Reference oscillator frequency
R:

Preset divide ratio of reference counter (256.512.1024.2048)

SERIAL DATA INPUT
On rising edge of the clock shifts one bit of the data into the shift register.
When the load enable is high, the data stored in the shift register is transferred to the latch.
24 bit of serial data formit is shown below.

r

I-

- - - . . Data Input Flow
LSB

A

A

1

2

MSB.

A
3

A

A

4

5

Divide ratio of swallow
counter selting bit

N
1

N
2

N

N
4

3

'I'

N
5

N

N

N

N

6

7

8

9

N
10

N
11

N
12

S
W

-I

Divide ratio of programmable
counter selting bit

R
2

R
1

B
C
4

B
C
3

B
C
2

L

I

I

Band switch
setting bit

Divide ratio of prescaler setting bit
Divide ratio of reference counter seltin g bit
5-bit swallow counter divide ratio (A 1 to AS)
Divide ratio

A

A

A

A

A

A

5

4

3

2

1

0

0

0

0

0

0

1

0

0

0

0

1

2

0

0

0

1

0

31

1

1

1

1

1

12-bit programmable counter divide ratio (N1 to N12)
Divide ratio

32

4-200

N

B
C
1

N
11

N

N

N

N

N

N

N

N

N

12

10

9

8

7

6

5

4

3

2

N
1

0

0

0

0

0

0

1

0

0

0

0

0

33

0

0

0

0

0

0

1

0

0

0

0

1

34

0

0

0

0

0

0

1

0

0

0

1

0

4095

1

1

1

1

1

1

1

1

1

1

1

1

I

MB1508

FUNCTIONAL DESCRIPTIONS
Reference counter divide ratio (R 1 to R2)

R

Divide ratio

R

R

2

1

256

0

0

512

0

1

1024

1

0

2048

1

1

•

Prescaler divide ratio (SW)
When divide ratio of prescaler setting bit is high, divide ratio of 256/272 is selected.
When divide ratio of prescaler setting bit is low, divide ratio of 5121528 is selected.
Band Switch Setting (BC1 to BC4)
When band switch setting bit is high, output is ON.
When band switch setting bit is low, output is OFF.

SERIAL DATA INPUT TIMING

Data

BC1
(MSB)

~----;;VAl

--A,
. --

---------

--1\(LSB)

I

I

Clock

~_JUL~
•

I

•

I

I,

I

J

I

I

LE

~
t,

I

rL

---.;---r--,

I

_

t.-':
I

I

I

t5~

Note: On rising edge of the clock shifts one bit of the data into the shift register.
When LE is high, the data stored the shift register is transferred into the latch.

4-201

MB1508
PHASE DETECTOR CHARACTERISTICS
Fe pin selects the phase of the phase detector. Phase characteristics (chage pump output) can be reversed depending upon the Fe pin
input level. Monitor pin (fout) output level is selected by the FC pin input level as well.
FC = H (or open)
001,002
fr> fp

H

fr= fp

Z

fr< fp

L

FC = L
001,002

fout

fout

L

Outputs programmable
reference divider output
frequency Ir.

Outputs programmable
divider output
frequency fp.

Z
H

Note:

Z:

VCO POLARITY

High-impedance

Depending upon the VCO polarity, FC pin should be set accordingly.
When VCO polarity is like 1,
Fe should be set high or open.
When veo polarity is like 2,
FC should be set low.

VCOOutput
Frequency

veo Input Voltage -....

PHASE DETECTOR WAVEFORM

Ir~

J

L

J

fp

u u u
(Fe =H)
0 01,002

L

Jf--------lr·--- -J7 --. --LJ-_. -L..S--L-tJ------.-_Ir.--. J}- --.--Jf--.-Jt---L H

' "

Z- -

I

I

(FC = L)
001,002

Z- -

,

Ir> fp

Note:

Ir = Ip

Phase difference detection range: -21t to +21t
Spike shape depends on the charge pump characteristics.
The spike is output to diminish the dead band.

4-202

fr< fp

,

'

fr < Ip

fr fp

H

L

fr=fp

Z

Z

fr< fp
VCO Polarity

L

0)

H

®

Note: Z = High-impedance
Depending upon the VCO polarity. the FC bit should be set.

VCO Output
Frequency

VCO Input Voltage _

4-213

MB1509

PHASE DETECTOR OUTPUT WAVEFORM

fr

fp
,

~
, ,

tw

tw

~

LD

(Fe bit:: High)

Do - - -

(Fe bit

=Low)

Do - - -

Note:

~- - - Z - -

~- - - z - -

I

~
I
I

_ _ _ _---III

-9-------~ -----JH

L- - - - - - -

~ - - - - - - - Jf ------Jr-.

-d------~-----9--------~ -------f ------Jr-.
J

• Phase difference detection range =-21t to +21t
• LD output becomes low when the phase difference is tw or more.
LD output becomes high when the phase difference less than tw is repeated 3 times or more
(e. g. tw 625 to 1250 ns, foscin 12.8 MHz).

=

=

• Spike appearance depends on the charge pump characteristics. The spike is output to diminish the dead band.
• When fr > fp or fr < fp, a spike might not generate depending upon the veo characteristics.

4-214

MB1509
ANALOG SWITCH
ON/OFF of the analog switch is controlled by the combination of the control data and LE signal. When the analog switch is ON. the 8S 1 and 8S2
pins output the charge pump output (001 • 002). When the analog switch is OFF. the 8S pin is set to high impedance.
Control Data = H
Divide ratio of transmit section is set

Control Data = L
Divide ratio of reception section is set

LE= H

LE = L

LE=H

LE = L

Analog switch of transmit section

ON

OFF

OFF

OFF

Analog switch of reception section

OFF

OFF

ON

OFF

When an analog switch is inserted between LP1 and LP2. faster lock up time is achieved to reduce the LPF time constant during PLL channel switching.

II

- - - - - - - - - - - - - - - - -, Do
CHARGE PUMP

,

L. _ _ _ _ _ _ _ _ _ _ _ _ _ -.

, BISW

(CONTROL SIGNAL)

-----_ ... -------------------- ... ----,

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Unit

Symbol
Min

Typ

Max

Vee

2.7

3.0

5.5

V

Vp

Vec

8.0

V

Input Voltage

Y,N

GND

Vee

V

Operating Temperature

TA

-40

-

+85

°C

Power Supply Voltage

Note

Vee1

=VCC2

-

HANDLING PRECAUTIONS
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

4-215

MB1509

ELECTRICAL CHARACTERISTICS
'::':"':::

ICC1

Reception section is active.

.11
-

4.0

-

ICC2

Transmit/reception section
are active.

-

8.0

12.0

fin1

P= 64/6S

10

400

fin2

P = 32133

10

-

200

-

12.8

20

Vee = 2.7 to 4.0V, son

-10

0

Vee = 4.0 to S.SV, son

-4

-

/.,::,"::::.':: .. :

.·i',' .":.<>:'::<:"'<."/.

I,:>

I/,?

.,i<

}}

::.

ii iC

Power Supply Current*

OSCIN

fose

fin

Pfin

Input Sensitivity
OSCIN
High-level Input Voltage

Except fin
andOSCIN

"'··:':.

RON

*: fin =400MHz, OSCIN =12.8MHz, Vee1 = Vee2 =3.0V. The remaining input pins are grounded and output pins are open.
**: AC coupling. Minimum operating frequency is measured with capacitor 1000pF.

j.iA

V

MB1509

TEST CIRCUIT (PRESCALER INPUT SENSITIVITY TEST)

PG ===n--r~Pr-F__-( >-_ _-<
son

II

GND

I

MB1S09

P.G1"

1000pF

son

fp

L---+---------u

r

Oscilloscope

0.1JlF

4-217

MB1509

APPLICATION EXAMPLE

Output

Lock Detector

3V

6V

MB1509

1000pF

Output

Note:

VP1,VP2
C1,C2
Clock, Data, LE
X'tal

4·218

:8V max
: depends on the crystal oscillator
: involve the Schmitt circuit
When input pins are open, please insert the pull down/up resistor individually to prevent the oscillation.
: 12.8MHz

MB1509

PACKAGE DIMENSIONS
20-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-20P-M02)

INDEX-1

.970

I'

~:g~~ (24.64 ~:~g)

-------.1'1
o

k::::;=;=::;::::::;:=;:=:;=::::;=;::=:;:=;=:::;::=;::::;:::::::;:::=;:::~~
f

.11 ~034 ~012

1SOMAl<

III

.244±.010
(6.20±0.25) .300(7.62)

!

-

TYP

-~_

~

- - - ==-

~

.01o±.002
(0.25±0.05)

(0.as::g· 30 )

MAX

©1991 FUJITSU LIMITED D20003S-3C

Dimensions in
inches (millimeters)

4-219

MB1509

PACKAGE DIMENSIONS (Continued)
20-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-20P-M01)

.089(2.25) MAX
(MOUNTING HEIGHT)
.002(0.05) MIN
(STAND OFF HEIGHT)

.307±.016
(7.80±0.40)

d

1012

INDEX

(5.3o±O.30)

1L-rJ.r-.....,.+,..:--r-r--,..,------r-,---,--r------,.,--..,..,.-rr--r-~ --.l
U

LJ

®!

I[

TYP

_I •. 018±.004

\-$-\0.005(0.13)
(0.45±0.10) ' - - ' - - ' - - - - - - - '

,-------,

"A"

I
I
I
I
I
I
I
I
I

I

~---

.450(11.43) REF

©1991 FUJITSU LIMITED F20003S·5C

4-220

-----+\-1

Details of "A" part

I

.008(0.20) I

I
I
I
I
.020(0.50) I
.007(0.18)
MAX
.027(0.68)

-- ---MAX

L _______

\

I

I

.J

Dimensions in
inches (millimeters)

cO

June 1995
Edition 0.4

FUJITSU

:: MB 15U1 0 ================-----1.1GHz DUAL PLL FREQUENCY SYNTHESIZER

INTRODUCTION
The Fujitsu MB15U10 is a dual serial input phase-locked loop (PLL) frequency
synthesizer and is ideally suitable for mobile communications such as cellular phones.
The MB15U10 has two PLL frequency synthesizer circuits on a single chip: one for
transmission and the other for reception (PLL 1 and PLL2).
It can operate from a +2.6V to 5.5V supply. Fujitsu's advanced technology achieves an
Icc of 7 mA (typical) as well as 10 ~ (max.) at power saving mode.

III

FEATURES
Two PLLs' for transmission/reception
Low current consumption

Icc .. 7 mA typo at 3 V

Power saving funtion

Ips .. 10 IlA max.

PIN ASSIGNMENT

Divide ratio setting with serial data input:
Binary 12-bit reference counter
: 6 to 4095
Binary 17-bit main counter
: 1024 to 131,071
·Main counters can be programmed individually each other.

P1/fp1

On-chip constant current source charge pumps

P2Ifp2

(TOP VIEW)

Adjustable charge pump output current with an external resistor

Plastic 2D-pin SSOP (shrink small outline) package

VOO ,.2

-0.3 to +4.0

V

Vp

Voo to 6.0

V

Output voltage

Vo

-0.3 to Voo +0.3

V

Output current

10

±10

mA

Storage temperature

Tstg

-55 to +125

°C

NOTE:

PO/lO

Do,

Vp

VOO,

Lock detection function
Phase matching circuit helps fast intermittent operation

Supply voltage

ISET

Permanent device damage may occur if the above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

002

PS

AGNO

fin,

fin2

OGNO

V0D2

OSCin

lE

P3Ifr2

Data

OSCout

Clock

(FPT-20P-M03)

This device contains circuItry to proted the inputs
against damage due to high static IIOnages Of eledriC
fields. However. it IS advised that normal precautions
be taken to avoid application of any IIOltage higher than
maximum rated VOltages to this htgh ilTll6darce circuit.

4-221

MB15U10

BLOCK DIAGRAM
VOOI

CRI

LDI

selector

Cl,A.B

--.l

~2

selector

9

P3Ifr2

I

P1/fpl

2

P2Jfp

!pI
Ip2

f~

15~-------+----~~+---~1

- - - - - - - - PLL2
CR2

V002

4-222

DGND

AGND

MB15U10

PIN DESCRIPTION

Data output I fp2 monitoring output (Open drain output)

2

P2Ifp2

3

001

Charge pump output (PLL 1)

4

VOO1

Power supply for digital blocks (PLL 1)

5

PS

Power saving mode control (input "L": power saving mode)

6

fin1

RF input (PLL 1)

8

OSCin

Crystal oscillator or TCXO input

9

P311r2

Data output I fr2 monitoring output (Open drain output)

10

OSCout

11

Clock

Clock input

12

Data

Data input

13

LE

14

VOO2

Power supply for digital blocks (PLL2)

15

fim

RF input (PLL2)

16

AGND

17

002

Charge pump output (PLL2)

18

Vp

Power supply for charge pump

19

POILD

20

ISET

III

Crystal oscillator output

Load enable of serial input data (input "W : Data is shifted into a latch.)

Ground for the charge pumps

Data output flock detector output (Open drain output)
Output is selected by "aLA" and "OLS" bits in a serial data
Charge pump output current adjustment (A resistor is connected.)

4-223

MB15U10

FUNCTION DESCRIPTIONS
Serial data Input
Serial data is processed using the Data. Clock. and LE pins. Serial data controls the programmable reference divider.
programmable divider (PLL 1) and programmable divider (PLL2) separately by means of address setting.
Binary serial data is entered via the Data pin.
One bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable pin is high. stored data is
latched.

a)Serlal data Input format
- - - - - - - - Direction of data input

r(MSB)

(LSB).

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

X

X

X

P
0

0

0

C

X

X

P
S

P
3

P
2

P
1

X

0

0

0

1

1

2

P
S
1

X

L
B

R

C

L
A

M
A
11

M
A
10

M
A
9

M
A
8

M
A

M
A

M
A
4

M
A
3

M
A
2

M
A
1

M
A

0

1

0

0

7

M
A
6

0

1

0

1

0

1

1

0

0

0

0

0

M
A
16

0

M
B
16

R

2

15

M
A
14

M
A
13

M
A
12

0

0

T
S

S

R

R

R

R

R

R

R

R

R

R

11

10

9

8

7

6

R
5

R

R

4

3

2

1

0

M
B
13

M
B
12

M
B
11

M
B
10

M
B
9

M
B
8

M

M
B
6

M
B
5

M
B
4

M

M
B
2

M
B
1

M
B
0

M
A

M
B
15

M
B
14

B
7

5

B
3

0

Auxiliary bit for test (no need at ordinary use)

Data setting
MAO to 16
MBO to 16
RO to 11
SR
POt03
OLA.B
CR1.2
PS1.2
TS

X

o

4·224

----------..1-

Divide ratio setting bits of the main counter (PLL 1)
Divide ratio setting bits of the main counter (PLL2)
Divide ratio setting bits of the reference counter
Divide ratio select bit of reference frequency (PLL 1 and PLL2)
Setting bits of PO to P3 output pins
Select bits of PO/LD pin output
Select bits of charge pump output current
Power saving mode control bits
Test bits (Set ·0· at ordinary use.)
Dummy bits (Set ·0· or ., •. )
Set ·0·

Address

[See Table
[See Table
[See Table
[See Table
[See Table
[See Table
[See Table
[See Table
[See Table

1]
2]
3]
4]
5]
6]
7]
8]
9]

-I

MB15U10
b)Data setting description
• Table 1 : MAO to MA 16 : Divide ratio of the binary 17-bit main counter (PLL 1)

1024

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1025

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

•
Notes:

•

0

•

Divide ratios less than 1024 are prohibited.

(Divide ratio = 1024 to 131,071)

• Table 2 : MBO to MB16 : Divide ratio of the binary 17-bit main counter (PLL2)

1024

o

0

000

0

o

0

000

0

0

000

1025

o

0

0

0

o

0

000

0

0

0

0

0

III

0

•
Notes: Divide ratios less than 1024 are prohibited.

(Divide ratio

= 1024 to 131,071)

• Table 3: R1 to R11 : Divide ratio of the binary 12-bit reference counter

Notes:

6

o

0

0

0

0

0

0

0

7

000

0

0

0

0

0

0

0

Divide ratios less than 6 are prohibited.

(Divide ratio

o

=6 to 4095)

• Table 4 : Divide ratio select bit of reference frequency (PLL 1 and PLL2)

o

Notes: R

R

R

R

2R

= Programmed value with

RO to R11 bits

4-225

MB15U10
• Table 5: PO to P3 ; PO to P3 outputs control

o

ON("lj
OFF ("Z")

Notes: X '" 0 to 3
• Table 6 : OLA, OlB ; 19-pin output selection

o

o

PO signal

o

Lock detect signal (PLL2)

o

lock detect signal (PLl1)
lock detect signal (Pll1 and PlL2)

• Table 7 : CR1, CR2 ; Charge pump output current selection

o

100
2100

Notes: Pll1 and Pl2 can be controlled individually.
• Table 8: PS ; Power saving control

o

Power saving mode
Operation

Notes: PLL 1 and PL2 can be controlled individually.
• Table 9: TS ; Test bit (Set to "0" at ordinary use.)

o

Output P1 signal

Outputs P2 signal

outputs P3 signal

outputs fp1

outputs fp2

outputs fr2

Notes: Reference frequency and comparison frequency can be monitored via P1 to P3 pins.

4-226

MB15U10
Serial data Input timing
•

t,

(~

~ (~20ns).

20ns).

h

(~50ns).

t.

ts (~20ns).

(~50ns).

16

(~

1000ns)

Data

Clock

JllJL--JllJL--1L1LlLI

I

I

I

I

I
1 I
'

LE

, ,
, ,

,.

t,~

Note:

-+-":".-_':",-,

•

I

t. 1

-:

I

·.,ts

h~.,
,.

II

• ~t.

One bit of data is shifted into the shift register on the rising edge of the clock.

RECOMMENDED OPERATING CONDITIONS

2.6

5.5

V

Voo

6.0

V

Input voltage

GND

Voo

V

Operating temperature

-30

+85

Supply Voltage

Notes: To protect against damage by electrostatic discharge. note the following handling precautions:
-

Store and transport devices in conductive containers.

-

Use properly grounded workstations. tools, and equipment.

-

Turn off power before inserting or removing this device into or from a socket.

-

Protect leads with conductive sheet, when transporting a board mounted device.

4-227

MB15U10

ELECTRICAL CHARACTERISTICS
<
I .• •••.

.

":i.i.··· .•· •• ...•.•...•...•

>

~J111
.

100

..

..••..•.•..•• .:;;>"'~.

.........

.. . . . . . •. . .

-

7.0

9.0

mA

*1

-

11.0

-

mA

*2

V001,2

Ips

-

-

10

~

flN1,2

fiN

90

-

1100

MHz

OSCIN

fose

3

12.8

35

MHz

flN1,2

PfiN

-13

+1

dBm

50Q, Vcc=2.6 to 3.5V

flN1,2

PflN

-7

+1

dBm

50Q, Vcc=3.5 to 5.5V

OSCIN

Vose

0.5

-

Vp--p

-

V

Operating frequency

VIH

Voo xO.7

-

Vil

-

-

Voo xO.3

V

IIH

-

-

1.0

~

III

-1.0

-

~

lose

-100

-

100

~

Low-level output voltage PO to P3

VOL

-

-

0.4

V

Open drain output

Set output voltage

ISET

VSET

-

1.2

-

V

RSET = 5kQ to 60kQ

High-impedance
Cut off current

Do" PO to P3

10FF

-

-

1.1

~

IOOH1

1.4

1.9

2.4

mA

100L1

1.4

1.9

2.4

mA

IDOHO

0.7

0.96

1.2

mA

IDOLO

0.7

0,96

1.2

mA

RSET =7kQ connected.
CR1, 2 bits ="0"
Voo =3.0V, Vp =5.0V

10l

1.0

-

-

mA

Open drain

Input sensitivity

High-level input voltage
Low-level input voltage

Data, Clock,
LE,PS

High-level input current
Low-level input current
Input current

Data, Clock,
LE,PS
OSCIN

001,2
Output current
001,2
PO to P3

Note: *1 ; fiN = 1.1 GHz, OSCIN = 12.8 MHz, Voo =3.0 V. In locked state.
*2 ; fiN = 1.1 GHz, OSCIN =12.8 MHz, Voo =5.0 V. In locked state.

4-228

. ...

. . • < ..•. >•..•...•.•..••.....•...........•...........................•... . ·.·. . .•.·.i

RSET = 7kQ connected.
CR1, 2 bits ="1"
Voo = 3.0V, Vp =5.0V

MB15U1U

PACKAGE AND DIMENSIONS
20-LEAD PLASTIC FLAT PACKAGE
(Case No.: FPT-20P-M03)

: ~2::~~,~ 41
[f~R~~H~a~
INDEX

o~

/

_.-:-_-;-._.049~:gg:
_""':":';;:";""_ (MOUNTING

(1.25j:~g)

HEIGHT)

i ClI·OO4(0.1 0) i

. I

1.
I

III

252±.008
(6.40±0.20)
.2l3{5.40) NOM

-.173±.004
(4.40±0.10)

~;::;::;:;:::::;::;::::::;;~ ~

WA" ................ '

••••

.0256±.0047
(0.65±0.12)

I

I

~

006+.002 (015+0.05)
•
-.001 . -0.02

Details of " A" part
." • .004±.004
(O.l 0±0.1 0)

I

(STAND OFF
HEIGHT)

.230(5.85)
REF

-:This dimension does not include resin protruction.

~1992

FUJITSU LIMITED F20012S-2C

Dimensions in
inches (millimeters)

4-229

4-230

OJ

Sept. 1995
Edition 1. 1a

FUJITSU

DATA SHEET

MB1510
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 1.1 GHz PRESCALER
DESCRIPTION
The Fujitsu MB1510 is a 1.1 GHz dual serial input PLL (Phase Locked Loop)
frequency synthesizer designed for cellular telephone and cordless telephone
applications.
The MB 1510 has two PLL circuits on a single chip: PLL 1 and PLL2. An analog switch
is provided for each PLL circuit decrease lock up time. Separate power supply pins
are provided for each PLL circuit as well.
1.1 GHz dual modulus prescalers are on chip and enables a pulse swallow function.
It operates from a supply voltage of 3.0V typo and dissipates 15 rnA typo of current
realized through the use of Fujitsu's unique U-ESBIC Bi-CMOS technology.

Plastic Package
FPT-20P-M01
FEATURES
• High operating frequency: fin = 1.1 GHz (Pin = -10 dBm, Vcc = 3V)
• Pulse swallow function: 64/65 or 128/129
• Low power supply current: Icc =15 rnA typ, @3V.

Pin Assignment

• Serial input reference divider: R = 512 or 1024
• Serial input 18-bit programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 16 to 2047
- Tx and Rx programmable counters may be controlled separately.

(TOP VIEW)

• Low power supply voltage: Vcc = 2.7 to 5.5V

GND

Clock

• On-Chip analog switches achieve fast lockup time

OSCIN

• Fast lock up by bipolar charge pumps

OSCou

LE

flN1

flN2

• Wide operating temperature: TA =-40 to 85°C

VCC1

• Plastic 20-pin fiat package (Suffix: -PF)

fr
LD1

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating
Power Supply Vohage

BSC1

LD2
BSC2

Value

Unit

D01

D02

V

BS1

BS2

Vee

Output Voltage

VOUT

-0.5 to Vec+O.5

V

Output Current

lOUT

±10

mA

TSTG

-55 to +125

°C

NOTE:

VCC2

fp

Symbol

-0.5 to 7.0

Storage Temperature

Data

Permanent device damage may occur If the above Absolute Maximum Ratings are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections
of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

Pin Assignment might be changed to
Improve the characteristics without notice.

This device contains circuitry to protect the inputs against
damage due to high stalic voltages or electric fields. However,
it is advised that nonnal precautions be taken to avoid
application ofanyvottage higherthan maximum rated voltages
to this high impedance circuit.

Copyright 1995 by FUJITSU LIMITED and FUJITSU MICROELECfRONICS, INC.

4-231

MB1510
MB1510 Block Diagram
LOt Dol eSl

fr

fp

eSC1

LD2Do2 BS2

r

BSC2

r

I
I
I
I
I
I
I
I
I
I

I

I
I
I
I

I

I
I

I
I

r-----.J

r-----.J

I

I
I
I
I
I
I

I
I
I

PLL 1

~shl\

r.gister

Vee 1

L-________~4~----------~~2>

OSCIH

4-232

~~3~--------~~------------~~~----~~~---q~~
Data Clock
LE
OSCouT
fin2

MB1510

PIN DESCRIPTIONS
Pin No.

Pin Name

1/0

1

GNO

I

Descriptions
Ground
Oscillator input pin
Oscillator output pin
A crystal is connected between OSC'N pin and OSOUT pin.

2
3

OSC'N
OSCOUT

0

4

fiM

I

5

VCC1

-

Power supply voltage input pin of PLL 1 section.
When power is OFF, latched data of PLL 1 section is cancelled.

6

f,

0

Monitor pin for programmable reference divider output

7

L01

0

Lock detect signal output pin of PLL 1 section.

Prescaler input pin of PLL 1 section.
The connection with VCO should be AC connection.

Condition

8

8SC1

I

III

LD pin output level

Lock

H

Unlock

L

Analog switch control pin of PLL 1 section.
BSC1

8S 1 pin output

L

High-impedance

H

Charge pump output

9

001

0

Charge pump output pin of PLL 1 section.
Phase characteristics of the phase detector can be reversed depending upon FC-bit setting.

10

8S1

0

Analog switch output pin of PLL 1 section, and controlled by 8SC1.

11

8S2

0

Analog switch output pin of PLL2 section, and controlled by 8SC2.

12

002

0

Charge pump output pin of PLL2 section.
Phase characteristics of the phase detector can be reversed depending upon FC-bit setting.

13

8SC2

I

Analog switch control pin of PLL2 section.
8SC2

14

L02

0

High-impedance

H

Charge pump output

Lock detect signal output pin of PLL2 section.
Condition

15

fp

0

8S2 pin output

L

LO pin output level

Lock

H

Unlock

L

Monitor pin for programmable divider output.
This pin output divided frequency of PLL 1 section or PLL2 section depending upon FP bit setting.
Condition·

LO pin output level

Lock

H

Unlock

L

4-233

MB1510

PIN DESCRIPTIONS

(Continued)

Pin No.

Pin Name

16

VCC2

17

fin2

I

Prescaler input pin of PLL2 section.
The connection with VCO should be AC connection.

18

LE

I

Load enable input pin. This pin involves a schmitt trigger circuit.
When this pin is high, the data stored in the shift register is transferred into the latch depending
on a control data.
At this moment, charge pump output signal is output from BS pin since internal analog switch
becomes ON.

19

Data

I

Serial data input pin of 23-bit shift register. This pin involves a schmitt trigger circuit.
The stored data in the shift register is transferred to either PLL 1 section or PLL2 section depending upon a control data.

I/O

-

Descriptions
Power supply voltage input pin for PLL2 section, programmable reference divider, shift register,
and crystal oscillator.
When power is OFF, latched data of PLL2 section and reference counter is cancelled.

Control bit data

20

Clock

I

The destination of data

H

Latch of PLL 1 section

L

Latch of PLL2 section

Clock input pin of 23-bit shift register. This pin involves a schmitt trigger circuit.
On rising edge of the clock shifts one bit of data into the shift register.

FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
fyeo
fyeo:

4-234

={(M x N) + A} x fose + R

(A < N)

Output frequency of external voltage controlled oscillator (VCO)

M:

Preset divide ratio of dual modulus prescaler (64 or 128)

N:

Preset divide ratio of binary 11-bit programmable counter (16 to 2047)

A:

Preset divide ratio of binary 7-bit swallow counter (0 ~ A ~ 127)

fose:

Reference oscillation frequency

R:

Preset divide ratio of reference counter (512 or 1024)

MB1510

FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data is input using three pins, Data pin, Clock pin, and LE pin. Programmable divider of Pll1 section and programmable
divider of PLl2 section are controlled individually.
Serial data of binary data is input into Data pin.
On rising edge of clock shifts one bit of serial data into the shift register. When load enable signal is high. the data stored in the shift
register is transferred to either the latch of PLL 1 section or the latch of PLl2 section depending upon the control bit data setting.

Control data

Destination of serial data

H

latch of PlL 1 section

L

Latch of PLl2 section

SHIFT REGISTER CONFIGURATION
DataFlow~

MSB

t
1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

C

R

F

P

F

A

A

A

A

A

A

A

N

N

N

N

N

N

H

N

N

N

N

N

E

P

R

C

1

2

3

4

5

6

7

1

2

3

4

5

6

7

8

9

10

11

T

F

E

: Divide ratio of the programmable counter setting bit (16 to 2047)
: Divide ratio of the swallow counter setting bit (0 to 127)
: Phase control bit of the phase detector
: Divide ratio of the prescaler setting bit (64/65,128/129)
: Output of the programmable divider control bit (fp1 or fp2)
: Divide ratio of the reference counter setting bit (512 to 1024)
: Control bit

N1 to N11
A1 to A7
FC

PRE
FP
REF

CHT

SERIAL DATA INPUT TIMING
• t1 , 12, 13, t4, t5 ~ 11J.S

Da..

CWok

~ -R;3
----MS"~
...~--.
:
--Nl1.

- - -

-

~--J1lIL-ll-flJL
•
I

"

•

I

LE

C, Co","" bit

_____

I"

'"

,

,

~--

~

'u'

~

t2-:

'

, I
,'
, ' ,

13~

-

t4 ---:

:

,

I

t5~

, ,

On rising edge of the dock shifts one bit of the data into the shift register.

4-235

MB1510
BINARY 11-BIT PROGRAMMABLE COUNTER DATA SETTING
Divide
Ratio
(N)

N
11

N
10

N
9

N

N
7

N
6

N

N
3

N

5

N
4

N

8

2

1

16

0

0

0

0

0

0

1

0

0

0

0

17

.

0

0

0

0

0

0

1

0

0

0

1

•

. . . . .

•

. . . .

2047

1

1

1

1

1

11

1

1

1

1

1

Note:

Divide ratio loss than 16 is prohibited.
Divide ratio (H) range:: 16 to 2047

BINARY 7-BIT SWALLOW COUNTER DATA SETTING
Divide
Ratio
(A)

A
7

A
6

0

0

0

1

.
127
Note:

A
4

A

3

A
2

A
1

0

0

0

0

0

0

0

0

. . .

0

0

0

1

•

•

. .

1

1

1

1

1

1

1

A
5

Divide ratio (A) range:: 0 to 127

PRE:

DIVIDE RATIO (P) OF THE PRESCALER SETIING BIT

H =64/65
L=128/129
REF:

DIVIDE RATIO (R) OF THE REFERENCE COUNTER SETIING BIT
H=S12 (fr=25.0 kHz)
L= 1024 (fr= 12.5 kHz)

FP:

OUTPUT OF THE PROGRAMMABLE DIVIDER SETIING BIT
H = fp pin (15 pin) outputs programmable~ divider output frequency (fp1) of PLL 1 section.
L = fp pin (15 pin) outputs programmable divider output frequency (fp2) of PLl2 section5

FC :

PHASE CONTROL BIT OF THE PHASE DETECTOR
Output of charge pump is selected by FC pin.

FC= H

FC= L

fr> fp

H

L

fr = fp

Z

Z

fr < fp

L

H

CD

®

VCO Polarity
Note:

4-236

Z:: High-impedance
Depending upon the VCO polarity.
FC should be bit set.

VCOOuput
Frequency

VCO Input Voltage ~

MB1510

PHASE DETECTOR OUTPUT WAVEFORM

fr

fp

...,t.....!.
, ,

, ,

tw

tw

~____---------r-

LD

(Fe bit

=High)

00--- ---Z-- - H------ ~ ---- ~-------~-------Jr------Jr-'
- L
".

~

(Fe bit ,. Low)

l z -00---1---

-q

l-I ------- Jr------ r-·
-d-------1---l
-9-------.
-

J

Note:
• Phase difference detection range = -27t to +27t

•

LD output becomes low when phase difference is tW or more.
LD output becomes high when phase difference less than tW is repeated 3 times or more.
(e. g. tW = 625 to 1250ns. foscin = 12.8 MHz)

•

Spike appearance depends on the charge pump characteristics. The spike is output to diminish the dead band.

•

When fr > fp or fr < fp. spike might not generate depending on the charge pump characteristics.

4-237

MB1510
ANALOG SWITCH
ON/OFF of the analog switch is controlled by BSC input signal. BSC1 controls the analog switch of the PLL 1 circuit. BSC2 controls
the analog switch of PLL2. When the analog switch is ON. BS pin output the charge pump output (001. 002). When analog switch is
OFF. BS pin is set to high-impedance.
BCS1 (2)

H

L

ON

OFF

Charge pump output 001 (2)

High-impedance

Analog switch of PLLl1 (2) section
BS1 (2) output

When an analog switch is inserted between LPF-1 and LPF-2. faster lock up time is achieved to reduce LPF time constant during
PLL channel switch in .

--------.-------~ ~
CHARGE PUMP

,
~-------------.,

sse

RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Power Supply Voltage

Unit

Symbol

Vee

Input Voltage

VIN

Operating Temperature

TA

Min

Typ

Max

2.7

3.0

5.5

V

GHO

-

Vee

V

-40

-

+85

°C

Note
Vee1

= Vee2

HANDLING PRECAUTIONS
•

This device should be transported and stored in anti-static containers.

•

This is a static sensitive device; take proper anti-ESO precautions. Ensure that personnel and equipment are properly grounded.

•

Cover workbenches with grounded conductive mats.

•

Always turn the power supply off before inserting or removing the device from its socket

•

Protects leads with a conductive sheet when handling or transporting PC boards with devices.

4·238

MB1510

ELECTRICAL CHARACTERISTICS
Parameter

Value

Condition

Symbol
ICCl

PLL2 current

ICC2

(PLL 1 + PLL2) current

-

finl

*1

10

fin2

*2

Power Supply Current

Unit

8.0

-

15.0

-

-

mA

1100

fin
Operating Frequency
OSCIN

fose

fin

Pfin

High-level Input Current

-10

-

0

-4

-

2

VOSC

0.5

-

-

Except fin
andOSCIN

VIH

VcCX 0.7+0.4

-

-

VIL

-

vcc xO.3-0.4

Data. Clock
LE

IIH

FC

IFC

-

dBm

IlL

Low-level Input Current
Input Current

OSCIN

losc

High-level Output Voltage

VOH

Low-level Output Voltage

Except Do
andOSCOUT

High-Impedance Cutoff
Current

Do.
fp

H

L

fr= fp

Z

Z

fr< fp

L

H

VCO Polarity

?

1

?

III

VCOOutput
Frequency

Note: • Z = High-impedance
• Depending upon the VCO polarity, FC bit should be set.
• Phase characteristic for each PLL 1 and PLL2 is set by the
serial data at that time of divide ratio setting for each
programmable divider.

VCO Input Voltage _

SERIAL DATA INPUT TIMING

t1 (>100ns)
t4 (>100ns)

¢

Data

Data set up time
t2 (>1000ns) : Data hold time
LE set up time to the rising edge of the last clock

N11 • MSB

V;;; ---_--;;:sr;;-----;;v_________
_••...::.:.J\
~_.

,

~

Clock

¢LE

t3 (>300ns): Clock pulse width
t5 (>800ns): LE pulse width

eN1· LSB

~

,

,

~--JUJ1-~
_____~'-.'-. "
::' rL
, ,
,

-...:
't1'

;.. t2-:

t3

-r--:-- :.4 ---'
,
:

'
:

t5~

, ,

On rising edge of the clock, one bit of the data is transferred into the shift register.

4-249

MB15B11

PHASE DETECTOR OUTPUT WAVEFORM

fr

fp

,

----,

~
, ,

,

tw

(FC bit =High)
Do - - -

~- - - Z - -

(FC bit =Low)
Do - - -

Note:

~- - - z --

I

tw

~

LD

I

_ _ _ _----,I

-9-------~ ------JH

L- - - - - - -

~ - - - - - - - Jr------Jr-.

-d------~ -----9--------~ -------r------Jr-.
J

• Phase difference detection range =-21t to +21t
• LD output becomes low when phase difference is tw or more .
• LD output becomes high when phase difference is tw or less and continues to be so for three cysles or more.
• tw depends on OSCin input frequency.

(e.g. tW635ns to 1250ns when foscin

4-250

=12.8 MHz)

MB15B11

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Unit

Symbol
Min

Typ

Max

2.7

3.0

3.5

V

Vee

Vcc

-

6.0

V

Input Voltage

VIN

GND

-

Vee

V

Operating Temperature

TA

-30

-

+80

°C

Vee

Note

Vee1

=Vee2

Power Supply Voltage

HANDLING PRECAUTIONS

III

• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats.
• Always tum the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

4-251

MB15B11

ELECTRICAL CHARACTERISTICS

Ii /iii

. . ....>/ i

...· i i i .....

>• .•. · i ••.. . •.

• •. ?:..... . . . . . . . . . . . . . . . . · · · · · . .················.·.i:i·.··
l
i i i i \ ·.
. . . . . . . . . ·...i ......»

....

? •••••

··.·.i.
...........

lee1

PLL 1 section

Icc2

PLL2 section

.•......

._.
..
-

3.5(0.1)

-

-

6.0(0.1)

-

..

Power Supply Current

fin1

fin1

100

-

400

fin2

fin2

100

-

1100

OSCIN

fose

-

12.8

20.0

fin1

Pfin1

PLL 1, 500 system

-10

-

4

dBm

fin2

Pfin2

PLL2, 500 system

-10

-

4

dBm

OSCIN

Vose

0.5

-

-

Vp-p

VIH

VccxO.7+0.4

-

-

Vil

-

-

IIH

-

1.0

Low-level Input Current

Data,
Clock
LE

III

-1.0

Input Current

OSCIN

lose

-

±50

-

2.2

-

-

-

-

0.4

-

-

1.1

-1

6

-

50

-

MHz

Operating Frequency

Input Sensitivity

High-level Input Voltage

Except fin
andOSCin

Low-level Input Voltage
High-level Input Current

High-level Output Voltage
Low-level Output Voltage
High--irnpedance Cutoff
Current

Except Do
and OSCout

Output Current

VOH

Vee=3.0V

Do,cI>P

IOFF

to 8.0V,
Voop = GND to 8.0V

IOH

-1.0

IOl

1.0

IOH

Vp=6.0V

IOL

Vcc= 3.0V

IOH

Vp=6.0V

IOl

Vcc=3.0V

001

002

Analog Switch ON Resistance
Notes:

V
VcexO.3-0.4

I1A

V
VOL

Except Do
andOSCout

4-252

mA

RON

*1: The value in ( ) is power supply current in power saving mode.

-

12

-3

-

I1A
rnA

mA

rnA

a

MB15B11

TEST CIRCUIT (PRESCALER INPUT SENSITIVITY TEST)

Vp1

PG

~~r-F

Vcc1

_ _ _-< 1 - - - {

II

GND

5001
M815811

POGi'

1000pF

fp

50n

L...---t---------u

Oscilloscope

Vp2

4-253

MB15B11

APPLICATION EXAMPLE
Lock Detector
Output

3V

6V

From {

Controller

Clock

Data

fin2

Vcc2

LD2

002

MB15B11

GND

fin 1

fr

LD1

1000pF

Output

Note:

X'tal
C1,C2
Clock, Data, LE
Vp1, Vp2

4-254

; 12.8MHz
: depends on a crystal oscillator.
: involves a schmitt circuit.
(When inputs are open, pull up/down resistor is necessary to prevent self-oscillation.)
:6Vmax.

BS1

MB15B11

PACKAGE INFORMATION

•
FPT-20P-M03
2D-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT·20P.M03)
--<~-+----- (MOUNTING HEIGHT)
·.256~.004

-1

1..100.
I

(6.40:1:0.20)

.213(5.40) NOM

·.173:1:.004 I
(4.4~0.10)

14rl;::;:;::;:;:::;:r:;:;::::;:;::::;;:::;:;:::;?J ~

.0256::.0047
(0.65::0.12)

.//.

"A" _ _ ' .

- 'j

+·004
.009 -.002

(0.22~:6~)
Details of "A"

~
~

part

~(STANDOFF

~I :'~")__

[lJ1

HEIG"D

4
o.to~
~."'O,201
,020<008

• "'. :This dimension does not include resin protruction.

©1991 FUJITSU LIMITED F20012S·2C

Dimensions in
inches (millimeters)

4-255

4-256

April 1995

~~~n2.0~~~~~~~_
DATA SHEET
~

MB1511

FuoOJI"SU
I,

ASSP

SERIAL INPUT PLL FREQUENCY SYNTHESIZER
DESCRIPTION
The Fujitsu MB 1511 is a single chip serial input PLL frequency synthesizer designed
for VHF tuner and cellular telephone applications.
It contains a 1.1 GHz dual modulus prescaler which enables pulse swallow function,
and an analog switch to speed up lock up time.
It operates supply voltage of 3.0 V typo and dissipates 7 rnA typo of current realized
through the use of Fujitsu's unique U-ESBIC Bi-CMOS technology.

•

FEATURES
• Low power supply voltage: Vee =2.7 to 5.5 V
• High operating frequency: fiN MAX =1.1 GHz (PIN MIN =-10dBm)
• Pulse swallow function: 64/65 or 128/129
• Low supply current: Icc =7 rnA typo
• Serial input 18-bit programmable divider consisting of:
Binary 7-bit swallow counter: 0 to 127
Binary 11-bit programmable counter: 16 to 2047

Plastic Package
(FPT.20P·M03)

• Serial input 15-bit programmable reference divider consisting of:
Binary 14-bit programmable reference counter: 8 to 16383
1-bit switch counter (SW) sets divide ratio of prescaler
• On-chip analog switch achieves fast lock up time
• 2 types of phase detector output
On-chip charge pump (Bipolar type)
Output for external charge pump
• Wide operating temperature: -40°C to +85°C
• 20-pin Plastic Shrink Small Outline Package (Suffix: -PFV)
ABSOLUTE MAXIMUM RATINGS
Parameter

Symbol

Value

Units

Power Supply voltage

Vcc
Vp

-0.5 to +7.0

V

Vccto 10.0

V

VOUT

-0.5 to Vcc+0.5

V

V~~p

-0.5 to 8.0

V

lOUT
Tstg

±10

mA

-55 to +125

°C

Output voltage
Open-drain voltage
Output current
Storage temperature
NOTE:

Permanent device damage may occur if the above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in
the operational sections of theis data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However, n
Is advised that normal precautions be takan to avoid application
of any voltage higher than maximum rated voltages to this high
impedance circuit.

4-257

MB1511

MB1511 BLOCK DIAGRAM

r------------,

I
I

I

I
I
I
I

lS-BIT SHIFT REGISTER

16-BIT SHIFT REGISTER

~Iilllil}£OI===~

I

I

15-BIT LATCH

+-.....- - - - - - - _ I
I

I

15-BIT LATCH

~~-----------~I

rIL.1ill1il}£OI===.JII
PROGRAMMABLE REFERENCE
DIVIDER

L....._-++tI.. BINARY 14-BIT

I

1-9---+.....

REFERENCE COUNTER

I~------------~

L. _ _ _ _ _ _ _ _ _ _ _ _ .J

Do

S ~--------~+-----------------------~~~~----------~

.---------------------------~----------------~----~14

4-258

LE

MB1511

PIN DESCRIPTION
Pin No.

Pin Name

I/O

1

OSCIN
OSCOUT

I
0

3

Description
Oscillator input.
Oscillator output.
A crystal is placed between OSCIN and OSCOUT .

4

Vp

5

Vee

-

6

Do

0

Charge pump output.
The characteristics of charge pump is reversed depending upon FC input.

7

GND

-

Ground.

S

lD

0

Phase comparator output.
Normally this pin outputs high level. While the phase difference of f, and fp exists, this
pin outputs low level.

Power supply input for charge pump and analog switch.
Power supply voltage input.

10

fiN

I

Prescaler input.
The connection with an external VCO should be AC connection.

11

Clock

I

Clock input for 19-bit shift register and 16-bit shift register.
On rising edge of the clock shifts one bit of data into the shift registers.

13

Data

I

Binary serial data input.
The last bit of the data is a control bit which specified destination of shift registers.
When this bit is high level and LE is high level, the data stored in shift register is transferred to 15-bit latch. When this bit is low level and LE is high level, the data is transferred to 18-bit latch.

14

LE

I

Load enable input (with internal pull up resistor).
When LE is high or open, the data stored in shift register is transferred into latch depending upon the control bit. At the time, internal charge pump output is connected to
BISW pin because internal analog switch becomes ON state.

15

FC

I

Phase select input of phase comparator (with internal pull up resistor).
When FC is low level, the characteristics of charge pump, phase comparator is reversed.
FC input signal controls foul pin (test pin) output level, f, or fp.

16

BISW

0

Analog switch output.
Usually BISW pin is set high-impedance state. When internal analog switch is ON (LE
pin is high level), this pin outputs internal charge pump output.
Minitor pin of phase comparator input.
fout pin outputs either programmable reference divider output (f,) or programmable divider output (fp) depending upon FC pin input level.
FC=H: It is the same as f, output level.
FC=L: It is the same as fp output level.

17

foUT

0

18
20

0P
0R

0
0

Outputs for external charge pump.
The characteristics are reversed according to FC input.
0P pin is N-channel open drain output.

2,9
12,19

NC

-

No connection.

•

4-259

MB1511

FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
5erial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. 5erial data input controls 15-bit programmable
reference divider and 18-bit programmable divider, respectively.
Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open,
stored data is transferred into latch depending upon the control bit.
Control data "H" data is transferred into 15-bit latch.
Control data "L" data is transferred into 18-bit latch.

PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. 5erial16-bit data format is
shown below.
Divide ratio of prescaler setting bit
M5B

I---

5

5

5

5

5

5

5

5

5

7

8

9

10

11

12

13

14

W

Divide ratio of programmable reference counter setting bit

-----I

14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide
Ratio
R

5

5

5

5

5

S

5

5

5

5

5

5

5

5

14

13

12

11

10

9

8

7

6

5

4

3

2

1

8

0

0

0

0

0

0

0

0

0

0

1

0

0

0

9

0

0

0

0

0

0

0

0

0

1

0

1

•

•

•

•

•

.

0

1

1

1

1

1

1

. ...
16383

1

1

1

•

.

0

•

.

•

1

1

1

1

1

NOTES: Divide ratio less than 8 is prohibited.
Divide ratio: 8 to 16383
5W: This bit selects divide ratio of prescaler.
SW.. H :64/65
SW.L : 128/129
51 to 514: These bits select divide ratio of programmable reference divider.
C: Control bit (sets as high level).
Data is input from MSB side.

PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
5erial19-bit data format is shown following page.

4-260

MB1511

Divide ratio of programmable
counter
setting bit

Divide ratio of swallow
counter
setting bit

7·BIT SWALLOW COUNTER DIVIDE RATIO
Divide
Ratio
A

S

S

S

S

S

S

S

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

1

.

0

0

0

0

0

1

•

•

•

.

0

•

•

.

127

1

1

1

1

1

1

1

NOTE: Divide ratio: 0 to 127
11·BIT PROGRAMMABLE COUNTER DIVIDE RATIO
Divide
Ratio

S

S

S

S

S

S

S

S

S

S

S

N

18

17

16

15

14

13

12

11

10

9

8

16

0

0

0

0

0

0

1

0

0

0

1

17

0

0

0

0

0

0

1

0

0

0

1

. ..

2047

1

1

•

.

•

..

•

.

•

.

1

1

1

1

1

1

1

1

1

NOTES: Divide ratio less than 16 is prohibited.
Divide ratio: 16 to 2047
S 1 to S7: Swallow counter divide ratio setting bit. (0 to 127)
S8 to S 18: Programmable counter divide ratio setting bit. (16 to 2047)
C: Control bit (sets as low level).
Data is input from MSB side.

PULSE SWALLOW FUNCTION
The divide ratio is set using the following equation.
fvco " [MxN)+A] xfosc+R
fveo: Output frequency of external voltage controlled oscillator (VCO)
M: Preset modulus of external dual modulus prescaler (64 or 128)
N: Preset divide ratio of binary 11-bit programmable counter (16 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter (~A~127. Az

w
::>

@

outputs (Do. 0R.0P) and FC input level are shown below.

cr.
u..

~

::>

FC=H or open

Note:

a..

FC=L

~

::>

Do

0R

0P

f....1

Do

0R

0P

foul

f,>1p

H

L

L

(1,)

L

H

Z

(fp)

f,d p

L

H

Z

(1,)

H

L

L

(fp)

1,..fp

Z

L

Z

(f,)

Z

L

Z

(fp)

o

~

Zz(High impedance)

Depending upon veo characteristics. FC pin should be set accordingly:
When VCO characteristics are like
FC should be set High or open circuit;
When veo characteristics are like~. FC should be set Low.

tp

t,=tp

I

f,fp or f,dp, spike might not appear depending upon charge pump characteristics.

ANALOG SWITCH
ON/OFF of analog switch is controlled by LE input signal. When the analog switch is ON, internal charge pump output
connected to BISW pin. When the analog switch is OFF, BISW pin is set to high-impedance state.

LE

(Do) is

Analog Switch

H (Changing the divide ratio of intermal prescaler)

ON

L (Normal operating mode)

OFF

When an analog switch is inserted between LP 1 and LP2, faster lock up times is achieved to reduce LPF time constant during PLL channal switching.

------------------~Oo
CHARGE PUMP

I

I

____ lC9_N!!:l9~_Sl~t_!~L_L_E2 _____________ ~

4-263

MB1511

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Unit

Symbol
Min

Typ

Max

V~

2.7

3.0

5.5

V

Vp

V~

-

8.0

V

Input Voltage

VI

GND

-

V~

V

Operating Temperature

TA

-40

-

85

°C

Power Supply Voltage

HANDLING PRECAUTIONS
• This device should be transported and stored in anti-static containers.
• This is static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly
grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off befer inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handing or transporting PC boards with devices.

4-264

MB1511

ELECTRICAL CHARACTERISTICS

(vee =2.7 V to 5.5 v, Ta =-40oe to +85°C)
Value

Parameter

Min

Typ

Max

Icc

-

7.0

-

mA

fin· 2

fiN

10

-

1100

MHz

OSCIN

fose

-

12

fin-l·3

Pfln1

-4

-

Symbol

Power supply current"1
Operating frequency

Input sensitivity

High-level input voltage
Low-level input voltage

fin-2·4

Pfin2

-10

OSCIN

Vose

0.5

Except fin and
OSCIN

V IH

OSC IN

lose

LE,FC

ILE

-

Except DO and
OSCOUT

VOH·S

2.2

VOL

-

-

DO,0p'6

IOFF

-

-

IOH

-1.0

IOL

1.0

-

RoN

-

50

High-level input current

Data clock
Low-level input current
Input current
High-level output current
Low-level output current
N-channel open drain
cutoff current
Output current

Analog switch on resistance

VCCxO.7

V IL
IIH
IlL

Except DO and
OSCOUT

1.0
-1.0

+50
-60

Unit

20

MHz

6

dBm

6

dBm

VCCxO.3

Vp-p
V

-

~

0.4

V

1.1

~

-

itA
itA

-

III

V

~
~
~
V

Q

Notes:
1. fin =1.1 GHz, OSCIN=12 MHz, VCC=3V. Inputs are grounded and outputs are open.
2.
AC coupling. Minimum operating frequency is measured when a capacitor l000pF.
3.
VCC=4.0 to 5.5V, 50n
4.
VCC=2.7to4.0V,50n
5.
VCC=3V
6.
VP=VCC to 8V, VOOP=GND to 8V

4-265

MB1511

TEST CIRCUIT

10 9 8

7

6

5

4

321

' - - - - - - - - - 0 Oscilloscope

4-266

MB1511

TYPICAL APPLICATION EXAMPLE
_--_OUTPUT

Charge Pump
Selection
(Internal or
external)
FROM
CONTROLLER

0R
20

19

LE

0P
18

16

17

15

Data

14

13

12

7

8

9 10

47k

III

47k

MB1511

2
OSC'N

3

6

5

4

Do

OSCOUT VP

6V

GND

LD

3V

LOCK DET

Vp , Vpx : 8V max.
C t , C 2 : Depends on crystal oscillator
LE,FC : With internal pull up resistor
0P
: Open drain output

4-267

MB1511

PACKAGE DIMENSIONS
20-LEAD PLASTIC FLAT PACKAGE
(Case No. : FPT-20P-M03)
049· gg~
------IMOUNTING HEIGHTI
11 25· ~gj

g

-

·256· .004
(650·010\--

0041010'
.---"~

252· 008
1640·0201

213(5401 NOM

• 173· 004
(440·0101

0256 ·0047
1065·0121

009·

- - (022 .

gg~

gb~)
Oetaols of

_

]

~

o to

10

part

(STANO OFF

.1010.010\

. !

230(5851
REF

·A

004· 004

r

HEIGHTI

020· 008
1050·0201

DimenSions In

C 1991 FUJITSU LIMITED F20012S-2C

4-268

*

This dimension does not Include resin protrusion

.,.,cnes Imllhmetersl

00

Sept. 1995
Edition 1.0a

FUJITSU

DATA SHEET

MB1512
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
LOW POWER SERIAL INPUT PLL SYNTHESIZER
WITH 1.1 GHz PRESCALER
The Fujitsu MB1512, utilizing BI-CMOS technology, is a single chip serial input PLL
synthesizer with pUlse-swallow function.
The MB1512 contains a 1.1 GHz two modulus prescalerthat can select of either
64/65 or 128/129 divide ratio, control signal generator, 16-bit shift register, 15-bit
latch, programmable reference divider (binary 14-bit programmable reference
counter), 1-bit switch counter, phase comparator with phase conversion function,
charge pump, crystal oscillator, 19-bit shift register, 18-bit latch, programmable
divider (binary 7 -bit swallow counter and binary 11-bit programmable counter) and
analog switch to speed up lock up time.
It operates with a supply voltage of 5V typo and achieves very low supply current of
8mA typo realized through the use of Fujitsu Advanced Process Technology.
•
•
•
•
•

•

•
•

•
•

High operating frequency: fiN MAX=1.1GHz (PIN MIN=-10dBm)
Pulse swallow function: 64/65 or 128/129
Power supply voltage: Vee=4.5 to 5.5V
Low supply current: lee=8mA typo
Serial input 18-bit programmable divider consisting of:
Binary 7-bit swallow counter: 0 to 127
Binary 11-bit programmable counter: 16 to 2047
Serial input 15-bit programmable reference divider consisting of:
Binary 14-bit programmable reference counter: 8 to 16383
1-bit switch counter (SW) sets divide ratio of prescaler
On-Chip analog switch achieves fast lock up time
2types of phase detector output
On-chip charge pump (Bipolar type)
Output for external charge pump
Wide operating temperature: -40°C to +85°C
20-pin Plastic Shrink Small Outline Package

III
PLASTIC PACKAGE
FPT-20P-M03

PIN ASSIGNMENT

OSCIN
NC

NC

OSC-

0P
fOUT
BISW
FC

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating
Power Supply Voltage

LE

Symbol

Value

Unit

Vee

-0.5 to +7.0

V

NC

Vp

Vee to 10.0

V

Clock

Output Voltage

VOUT

-0.5 to Vee +0.5

V

Open-drain Voltage

Voop

-0.5 to 0.8

V

Output Current

lOUT

±10

mA

Storage Temperature

TSTG

-55 to +125

°c

NOTE:

0R

Permanent device damage may occur if the above Absolute Maximum
Ratin~s are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Data

NC

This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid
application of any vottage higher than maximum rated
voltages to this high impedance circuit.

Copyright@ 1994 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS, INC.

4-269

MB1512

MB1512 BLOCK DIAGRAM

r-----------,
16-BIT SHIFT REGISTER
I

I
I

I

16-BIT SHIFT REGISTER

~I[JI[JI[JIO===~

I

I
I
~---_ _ _ _ _--,I
1S-BIT LATCH

1S-BIT LATCH

vcc0

L.1[JlfJlfJIO===.J
rpROGRAMMABLE REFERENCE'1
I DIVIDER

1
'----+.........~
1

BINARY 14-BIT
REFERENCE COUNTER

1
1-+----+-'

1 _ _ _ _- - . . . . 1....

L.. _ _ _ _ _ _ _ _ _ _ _ .J

DO

6 ~--------_i+_----------------------+-~-4------------~

t----------------------------+-----------------+--~14

4-270

LE

MB1512

PIN DESCRIPTION
Pin No.
1

3

Pin Name

va

OSCIN
OSCOUT

I

Description

0

Oscillator input.
Oscillator output.
A crystal is placed between OSCIN and OSCOUT.
Power supply input for charge pump and analog switch.

4

Vp

-

5

Vee

-

Power supply voltage input.

6

Do

0

Charge pump output.
The characteristics of charge pump is reversed depending upon FC input.

7

GND

-

Ground.

8

LD

0

Phase comparator output.
Normally this pin outputs high level. While the phase difference of fr and fp exists, this
pin outputs low level.

9

NC

-

No connection.

10

fiN

I

11

Clock

I

Prescaler input.
The connection with an external VCO should be AC connection.
Clock input for 19-bit shift register and 16-bit shift register.
On rising edge of the clock shifts one bit of data into the shift registers.

12

NC

-

No connection.

13

Data

I

Binary serial data input.
The last bit of the data is a control bit which specified destination of shift registers.
When this bit is high level and LE is high level, the data stored in shift register is transferred to 15-bit latch. When this bit is low level and LE is high level, the data is transferred to 18-bit latch.

14

LE

I

Load enable input (with intemal pull up resistor).
When LE is high or open, the data stored in shift register is transferred into latch depending upon the control bit. At the time, internal charge pump output to be connected
to BISW pin because internal analog switch becomes ON state.

15

FC

I

Phse select input of phase comparator (with intemal pull up resistor).
When FC is low level, the characteristics of charge pump, phase comparator is reversed.
FC input signal is also used to control fout pin (test pin) output level, fr or fp.

16

BISW

0

Analog switch output.
Usually BISW pin is set high-impedance state. When intemal analog switch is ON (LE
pin is high level), this pin outputs internal charge pump state.

17

fOUT

0

Minitor pin of phase comparator input.
fout pin outputs either programmable reference divider output (fr) or programmable
divider output (fp) depending upon FC pin input level.
FC=H: It is the same as fr output level.
FC=L: It is the same as fp output level.

18
20

(()P

0R

0
0

Outputs for external charge pump.
The characteristics are reversed according to FC input.
0P pin is N-channel open drain output.

NC

-

No connection.

2
19

•

4-271

MB1512

FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable
reference divider and 18-bit programmable divider, respectively.
Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the intemal shift registers and when load enable pin is high level or open, stored
data is transferred into latch depending upon the control bit.
Control data "H" data is transferred into 15-bit latch.
Control data "L" data is transferred into 18-bit latch.

PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is
shown below.

j.--

Divide ratio of programmable reference counter setting bit

------i

14·BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide
Ratio
R

S

S

S

S

S

S

S

S

S

S

S

S

S

S

14

13

12

11

10

9

8

7

6

5

4

3

2

1

8

0

0

0

0

0

0

0

0

0

0

1

0

0

0

9

0

0

0

0

0

0

0

0

0

0

1

0

0

1

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

1

1

1

1

1

16383

1

1

1

1

1

1

1

1

1

NOTES: Divide ratio less than 8 is prohibited.
Divide ratio: 8 to 16383
SW: This bit selects divide ratio of prescaler.
SW=H :64165
SW=L : 128/129
S1 to S14: These bits select divide ratio of programmable reference divider.
C: Control bit (sets as high level).
Data is input from MSB side.

PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown following page.

4-272

MB1512
Control bit
LSB

l

r

C

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

MSB_---:i

Divide ratio of programmable
counter
setting bit

Divide ratio of swallow
counter
setting bit

-I

7-BIT SWALLOW COUNTER DIVIDE RATIO
Divide
Ratio
A

S

S

S

S

S

S

S

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

1

•

•

•

•

•

•

• •

127

1

1

1

1

1

1

III

1

NOTE: Divide ratio: 0 to 127

11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO
Divide
Ratio
N

S

S

S

S

S

S

S

S

S

S

S

18

17

16

15

14

13

12

11

10

9

8

16

0

0

0

0

0

0

1

0

0

0

17

0

0

0

0

0

0

1

0

0

0

"

•

•

•

•

•

•

•

•

•

•

•

•

2047

1

1

1

1

1

1

1

1

1

1

1

1

NOTES: Divide ratio less than 16 is prohibited.
Divide ratio: 16 to 2047
S1 to S7: Swallow counter divide ratio setting bit. (0 to 127)
S8 to S18: Programmable counter divide ratio setting bit. (16 to 2047)
C: Control bit (sets as low level).
Data is input from MSB side.

PULSE SWALLOW FUNCTION
fveo= [(PxN)+A] xfosc+R
fveo:Output frequency of external voltage controlled oscillator (VCO)
N: Preset divide ratio of binary 11·bit programmable counter (16 to 2047)
A: Preset divide ratio of binary 7·bit swallow counter (0::;A:5127, A

@
II:

u..

FC=L

FC=H or open

I-

::>
n.

Do

0R

0P

fout

00

0R

0P

fout

fr>fp

H

L

L

(fr)

L

H

Z

(fp)

frfp

1 --. z • - - U ·
-1frfp

u

L

-----L-t· ---l..-..j· ---L-

frfp or fr;.

...::.. .... :> ·.:··Z. . . .
... ..........:.............. ii""" ,~·.'c:."7.>

..............: :

. ·. . ·.···"7·.'·77>

.....

..

.

Power Supply Voltage

Vcc

-0.5 to 5.0

V

Output Voltage

VOUT

-0.5 to Vce +0.5

V

Open Drain Voltage

VOOP

-o.5to+ 5.0

V

Output Current

lOUT

±10

rnA

Storage Temperature

TSTG

-55 to +125

°C

NOTE:

fr, fp

Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

GND

LE
fin2
Vcc2
fp
LD2
BS2B

001

002

BS1

BS2A

This device conlains circuitry 10 protect the inputs against
damage due to high sialic vokages or electric fields. However,
" is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages
to this high impedance circuit.

4-281

MB15813

BLOCK DIAGRAM
VCCl

- - - - - - - psi - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ..

BSl

002

BS2B

VCC2

4-282

GNO

GNO

MB15B13

PIN DESCRIPTIONS
Pin No. Pin Name

I/O

Descriptions

1

GND

-

Ground.

2
3

OSCIN
OSCOUT

I

0

Oscillator input pin.
Oscillator output pin.
A crystal is connected between OSCIN pin and OSCoUT pin.

4

fin1

I

Prescaler input pin of PLL 1 section.
The connection with VCO should be AC.

5

Vee 1

-

Power supply voltage input pin of PLL 1 section.
When power is OFF, latched data of PLL 1 section is cancelled.

6

fr

0

Monitor pin for programmable reference divider output. (Open drain output)

7

LDl

0

Lock detect signal output pin of PLL 1 section.
Condition

LD pin output level

Lock

H

Unlock

L

8

GND

-

Ground

9

001

0

Charge pump output pin of PLL 1 section.

10

BSl

0

Analog switch output pin of PLL 1 section, and controlled by BSC bit.

11

BS2A

I/O

Analog switch I/O pin of PLL2 section

12

002

0

Charge pump output pin of PLL2 section.

13

BS2B

I/O

Analog switch 1/0 pin of PLL2 section

14

LD2

0

Lock detection signal output pin of PLL2 section.
Condition

15

fp

0

III

lD pin output level

Lock

H

Unlock

L

Monitor pin for programmable divider output. (Open drain output)
This pin outputs divided frequency of PLl1 section or PlL2 section depending upon FP bit setting.
FPbit

Output

H

PLL 1 section (fp 1)

L

PLL2 section (fp2)

4-283

MB15813

PIN DESCRIPTIONS (Continued)
PIn No. PlnName

DescriptIons

110

16

Vcc2

-

Power supply voltage input pin for PLL2 section, programmable reference divider, shift register, and
crystal oscillator.
When power is OFF, latched data of PLL2 section and reference counter is cancelled.

17

fin2

I

Prescaler input pin of PLL2 section.
The connection with VCO should be AC.

18

LE

I

Load enable input pin. This pin is followed by a schmitt trigger circuit.
When this pin is high, the data stored in the shift register is transferred into the latch depending on a
control data.

19

Data

I

Serial data input pin of 23·bit shift register. This pin is followed by a schmitt trigger circuit.
The stored data in the shift register is transferred to one of PLL 1 section, PLL2 section and program·
mabie counter depending upon control data settings.

20

Clock

I

Clock input pin of 23·bit shift register. This pin is followed by a schmitt trigger circuit.
On rising edge of the clock, one bit of data is transferred into the shift register.

FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the folloWing equation:

fvco

={(P x N) + A} x fosc + R

(A < N)

fvco: Output frequency of external voltage controlled ocillator (VeO)
P:

Preset divide ratio of dual modulus prescaler (64 or 128)

N:

Preset divide ratio of binary 11-bit programmable counter (16 to 2047)

A:

Preset divide ratio of binary 7·bit swallow counter (O~ A ~ 127)

fosc: Reference oscillation frequency
R:

4-284

Preset divide ratio of binary 14-bit programmable reference counter (8 to 16383)

MB15B13

FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable divider of PLL 1 section, programmable divider of PLL2
section and programmable reference divider are controlled individually.
Serial data of binary data is entered into Data pin.
On rising edge of clock, one bit of serial data is transferred into the shift register. When load enable signal is high, the data stored In the shift register
is transferred to one of latch of them depending upon the control bit data setting.

Control bits
CNT1

Destination of serial data

CNT2

L

L

Reference counter

L

H

Programmable counter of PLL 1

H

H

Programmable counter of PLL2

II

SHIFT REGISTER CONFIGURATION
Programmable Reference Counter

LSB

MSB

DataFlow_

~

~
3

4

5

6

7

8

9

10

11

12

C

F

R

R

R

R

R

R

R

R

R

R

R

R

P

R
1

R

N

2

3

4

5

6

7

8

9

10

11

12

13

14

1

2

C
N
T
1

13

14

15

16

17

T
2

R1 to R14 : Divide ratio setting bit for the programmable counter (8 to 16383)
FP
: Test purpose bit (monitor output fp1lfp2 selection)
CNT1, 2
: Control bit

Programmable Counter

LSB

MSB

DataAow_

~

•
1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

C
N
T
1

C
N
T
2

P
S

P
R

B

A
1

A
2

A
3

A
4

A

A
6

A
7

N
1

N
2

N
3

N
4

N
5

N
6

N
7

N
8

N

S

N
10

N
11

E

C

Ntto Ntt
A1 to A7

SSC
PRE
PS
CNTt,2

5

9

: Divide ratio setting bit for the programmable counter (16 to 2047)
: Divide ratio setting bit for the swallow counter (0 to 127)
: Analog switch control bit
: Divide ratio setting bit for the prescaler (64/65, 128/129)
: Power saving control bit
: Control bit

4-285

MB15B13
BINARY 14-BIT PROGRAMMABLE REFERENCE COUNTER DATA SETTING
Divide
Ratio
(R)

R
14

R
13

8

0

9

0

16383

1

R
12

R
11

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

R
10

R
9

R

R

R

R

8

7

6

5

0

0

0

0

1

R
4

R

R

R

3

2

1

0

1

0

0

0

0

1

0

0

1

1

1

1

1

1

Note: • Divide ratio less than 16 is prohibited.
• Divide ratio (N) range =16 to 2047

Note: • Divide ratio less than 8 is prohibited .
• Divide ratio (R) range =8 to 16383

BINARY 11-BIT PROGRAMMABLE COUNTER DATA SETTING
Divide
Ratio
(N)

N
11

N

N

N

9

N
8

N

10

7

6

N
5

N
4

N
3

N
2

N
1
0

16

0

0

0

0

0

0

1

0

0

0

17

0

0

0

0

0

0

1

0

0

0

1

V

V

V

V

V

V

V

V

V

V

V

V

2047

1

1

1

1

1

1

1

1

1

1

1

BINARY 7-BIT SWALLOW COUNTER DATA SETTING
Divide
Ratio

A

A

A

7

6

5

A
4

0

0

0

0

0

1

0

0

0

0

V

V

V

V

V

127

1

1

1

1

A

A

A

3

2

1

0

0

0

0

0

1

V

V

V

1

1

1

Note:. Divide ratio (A) range =0 to 127

(A)

PRESCALER DATA SETTING
Divide Ratio

PRE

64/65

1

1281129

0

Note: • Divide ratio for each PLL 1 and PLL2 is set by the serial data
at that time of divide ratio setting for each programmable
divider.

ANALOG SWITCH CONTROL DATA SETTING

ssc

Analog SW (PLL 1)

Analog SW (PLL2)

L

High impedance

High impedance

H

Charge pump output

BS2A and BS2B connected

Note:. Selection of PLL 1 or PLL2 is done by the control bits of CNT1 and CNT2.
And each analog switch can be controlled individually.

4-286

MB15813
POWER SAVING FUNCTION CONTROL (INTERMITTENT OPERATION)
PS
H

L

PLL 1'5 section

ON

OFF

PLL2's section and
common section

ON

OFF

Note:. Power saving mode for each PLL 1 and PLL2

IS selected by the serial data at that time of divide ratio setting
for each programmable divider.
• Common section ; Crystal oscilator circuit, reference counter

Intermittent operation limits power consumption by shutting down or start the intemal circuits case by case. If device
operation resumes uncontrolled, the error signal output from the phase comparator may exceed the limit due to an undefined
phase relationship between the reference frequency (fA) and the comparison frequency (fp) and frequency lock is lost.
To prevent this, an intermittent operation control circuit is provided to decrease the variation in the locking frequency by
forcibly correcting phase of both frequencies to limit the error signal output. This is done by the PS control circuit. If PS is set
high, the circuit enter the operating mode. It PS is set low, operation stops and the device enters the stand-by mode.

III

The operating and stand-by modes alternate repeatedly. This intermittent operation limits the error signal by forcibly
correcting the phase of the reference and comparison frequencies to limit power consumption.

SERIAL DATA INPUT TIMING

t1 (>100ns)
t4 (>100ns)

<:?

Data

NI1

Data set up time
t2 (>1000ns) : Data hold time
LE set up time to the rising edge of the last clock

=MSB

t3 (>300ns): Clock pulse width
t5 (>800ns): LE pulse width

V;; •••
--- -::sr:;--•• •--;;;;;:v
.;::::J\_________
~

CNn - LSB

~

,

<:?

Clock

<:?

LE

-lliJl-_JUJl_~
_____~'_'__ .. ::' rL
~

, t1 '

: . t2-:

t
3

~

:-

"

4--": :
,' ,
, ,
I

t5~

On rising edge of the clock, one bit of the data is transferred into the shift register.

4-287

MB15B13

PHASE COMPARATOR OUTPUT WAVEFORM

fr

fp
I

I

I

I

...-....

~
I
I
twu

-....-_----',

LD

Do - - -

~- - - Z - -

twL

-9-------~ -----JH

L- - - - - - -

~ - - - - - - - Jr------Jr-.

Relation between phase comparator and charge pump output
Do output
fr > fp

H

fr=fp

Z

fr < fp

L

Note: • Phase difference detection range =-27t to +27t
• LD output becomes low when phase difference is twu or more.
• LD output becomes high when phase difference is twL or less and continues to be so for three cysles or mere.
• twL and twL depend on OSCin input frequency.
twu ~8lfosc (e. g. twu ~25ns, foscin = 12.8 MHz)
twL~16/fosc (e. g. twL ~1250ns, fescin =12.8 MHz)

4-288

MB15B13

RECOMMENDED OPERATING CONDITIONS
Parameter

V.'u.

Symbol

Min

Typ

Max

Unit

Note

Vee1 = Vee2

Power Supply Voltage

Vee

2.7

3.0

3.5

V

Input Voltage

Y,N

GNO

Vee

V

Operating Temperature

TA

-30

Analog Switch BS2 Current

las

-6

-

+80

°C

+6

mA

Vcc=3.0V

HANDUNGPRECAUTIONS

III

• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESO precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats.
• Always tum the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

4-289

MB15B13

ELECTRICAL CHARACTERISTICS

"1

Icc1

PLL 1 section

S.0{0.1)

Icc2

PLL2 & common sections

7.0{O.1)

Power Supply Current

rnA

1

fin

fin

100

1100
MHz

Operating Frequency
OSCIN

fosc

fin

Pfin

OSCIN

Vosc

O.S

Data,
Clock
LE

VIH

VccxO.7+0.4

IIH

1.0

Low-level Input Current

Data,
Clock
LE

III

-1.0

Input Current

OSCIN

losc

±SO

20.0

12.8

son

o

-10

dBm

Input Sensitivity

High-level Input Voltage
Low-level Input Voltage
High-level Input Current

High-level Output Voltage

Vp-p

V
VccxO.3-0.4

Vil

VOH

Vcc=3.0V

VOl

Vcc=3.0V

2.2

V

LD
Low-level Output Voltage
High--impedance Cutoff
Current

DO,BS

0.4

IOFF

1.1
-1.0

IOH

rnA

LD
1.0

IOl

Output Current
IOH

Vcc=3.0V

-0.6

IOl

Vcc=3.0V

6.0

"2

D01,2

Analog Switch ON Resistance
Notes:

4-290

RON

*1: The value in ( ) is power supply current in power saving mode.
*2: L type charge pump which is similar to MB1SA31's is used.

50

rnA
"2

M815813

TEST CIRCUIT (PRESCALER INPUT SENSITIVITY)

1000pF

Vcc1

PG~

5001
PG

fp

r---+---------...-.-u

~OOOP..F_ _ _--<

Oscilloscope

GND

III

5001
M815813

P'Gi'

1000pF

50n

fp
' - - - - t - - - - + - - - t - - i - - 4 - - U Oscilloscope

L..----f

Controller

4-291

MB15B13

APPLICATION EXAMPLE
Lock Detector
Output

Vcc

Fom
Controller

t

Txdriver

Clock

Data

LE

fin2

002

Vcc2

BS2A

t

Rx

~

Tx

MB15B13

fr

GND

LD1

GND

BS1

1000pF

Output

Note:

4-292

C1. C2
Clock. Data. LE

: depends on a crystal oscillator.
: involves a schmitt circuit.
When input pins are open, please insert the pull down/up resistor individually to prevent oscillation.

M815813

PACKAGE INFORMATION

III
FPT-20P-M03
20-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-20P-M03)

.049~:gg:

--<-+---t----- (MOUNTING HEIGHT)

(1.25~:~g)

*.256±.004
(6.50:0.10)

.252:.008
(6.40:0.20)

1

.213(5.40) NOM

*.173:.004
(4.40:0.10)

~:;::::;::;:=;:;::;;::;:;::;:~~
.0256:.0047

+. 004
.009 -.002

(0.65±0.12)

(O.22~:6g)

j

"A" __..'-

Details of "A" part

L(ST~DO~

WI ~".::~

.230{5.85)

OOlo;:J1

REF

- ~• :This dimension does not include resin protruction.

©1991 FUJITSU LIMITED F20012S-2C

-

- - - - .. -

....

HEIG~

(0.50.0.20)

- .... - - .. - ......

- .. - - - ........
Dimensions in
inches (millimeters)

4-293

4-294

cO

OS04-21316-1 E

FUJITSU

DATA SHEET

MB1513
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
SERIAL INPUT PLL FREQUENCY SYNTHESIZER WITH POWER
SAVING FUNCTIONS (1.1GHz)
The Fujitsu MB 1513 is a serial input phase-locked loop (PLL) frequency synthesizer with a
pulse-swallow function. A stand-by mode is provided to limit power consumption during
intermittent operation.
The MB1513 is configured of a 1.1 GHz dual-modulus prescalerwith selectable 128/129
divide ratio, control signal generator, 16-bit shift register, 15-bit latch, programmable
reference divider (binary 14-bit programmable reference counter), 1-bit switch counter,
phase comparator with phase conversion function, charge pump, crystal oscillator, 19-bit
shift register, 18-bit latch, programmable divider (binary 7-bit swallow counter and binary
11-bit programmable counter), analog switches, and an intermittent operation control
circuit that selects the stand-by or operating mode depending on the power-save control
input state (PS).
The MB 1513 operates from a single +5 V supply. Fujitsu's advanced process technology
achieves an Icc of 8mA, typical. The stand-by mode current consumption is just 100JlA.

FEATURES
fiN = 1.1GHz (P IN = -10 dBm)
High-speed dual-modulus prescaler with selectable
128/129 divider ratio
Icc = 8 mA typo at 5V
Low supply current
Power-saving stand-by mode
100j.lA typo
Serial input, 18-bit programmable divider consisting of:
: 0 to 127
- Binary 7-bit swallow counter
- Binary 11-bit programmable counter: 16 to 2,047
Serial input 15-bit programmable reference divider consisting of:
- Binary 14-bit programmable reference counter: 8 to 16,383
- 1-bit switch counter sets prescaler divide ratio
On-chip analog switch for fast lockup
On-chip charge pump minimizes system component count
Wide operating temperature range: -40 to +85°C
Plastic 2o-pin shrink small outline package (Suffix: PFV)
High operating frequency
Pulse-swallow function

PLASTIC PACKAGE
(FPT-20P-M03)

This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
fields. However. it is advised that normal precautions be
taken to avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit.

Copyright©1994 by FUJITSU LlMIED

4-295

MB1513

PIN ASSIGNMENT

(TOP VIEW)
OSCIN

PS

NC

NC

OSCOUT

fA

Vp

fp
BiSW

VCC

FC

Do
GND

LE

LD

Data

NC

NC
Clock

fiN

ABSOSUTE MAXIMUM RATINGS(See NOTE)
Ratings

Symbol

Value

Unit

Vce

-0.5 to +7.0

V

Supply Voltage
Output Voltage

Vp

Vee ~ Vp ~ 10.0

V

Vo

-0.5 to Vee +0.5

V

±10

mA

-55 to +125

°C

Output Current

10

Storage Temperature

Tstg

NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

4-296

MB1513

BLOCK DIAGRAM

OSCI

1

r-------,
16-bit Shift Register I

'\--~-=--=--=--=--=-"'..L.,l

.

I

Oscillator

I

~S1

I 16-bit Shift Registe~ I
Ly
,J

I-

OSCou 2~--------4

Vp

~IOIOIOI~
I
1S-bit latch
I

f---+{

~IOIOIOI~

3

1

I
Ir

Vee

II

1S-bit Latch

~

4

1

Programmable
Reference Divider

~

Binary 14-bit

Reference
Counter

:

I

s~R==

W

...I

PS1
Intermittent 1-+-__
Operation
.--~_ _--I Control Cir- I--I----+-....J
cuit

-+--+_+-+_.1

L.._-+-+-__.....

Do

GND

LD

From
Charge
Pump

5~-~---~~+4--------~r_--+_--+--r_-------~

6

7

L-_ _ _ _ _ _ _ _-I-_ _ _ _ _ _+-______-41 Schmitt 101 _ _...(11

From
Phase
Comparator

Trigger

Ir----------,
19-bit Shift Register
,
L+-I--....
r..t 19-bit Shift Register I

Lock Detec~
tion Circuit!

>IOIIIIrarOI~

I

PS1

fiN

~~:ier

rOutput

1

L
f"'Ps1

81-----01 Prescaler
L..----,.---........I.

1

MC

111.bit Latchl,

lE

1-bit~Data

Control~
Latch
L -_ _--I1 Schmitt

I

Trigger

rL..t9

Clock

~IOIIIIrarOI~

I

SW

I

18-bit Latch

f---+{ 7-bit Latch I

r

Programmable Divider

-,- 11

I I

I
I

;1' .1-1.,--........1
I
I
I
L--ft-i-t---.J
I,

Binary 7-bit
Swallow
,
Counter

1..--------1:

Binary 11-bIt 1
Programmabie Counter

Control Circuit

I

4-297

MB1513

PIN DESCRIPTION
Pin No. Pin Name

Description

OSCIN

2

NC

-

No connection

OSCOUT

0

Oscillator output
An external crystal is connected to this pin.

4

Vp

5

Vee

-

6

Do

0

Charge pump output
The phase of the charge pump is reversed depending on the FC input.

3

4·298

110

1

I

Programmable reference divider input
Oscillator input
An external crystal is connected to this pin.

Power supply input for charge pump and analog switch
Power supply

7

GND

-

Ground

8

LD

0

Phase comparator output
The output level is high when LD is locked. The output level is low when LD is unlocked.

9

NC

-

No connection

10

fiN

I

Prescaler input
An external VCO is AC-coupled to this pin.

11

Clock

I

Clock input for 19-bit and 16-bit shift registers
One bit of data is shifted into the registers on the rising edge of the clock.
A Schmitt trigger circuit is involved.

12

NC

-

No connection

13

Data

I

Binary serial data input
The last bit of the data is a control bit.
When the control bit is high, data is transmitted to the 15-bit latch.
When the control bit is low, data is transmitted to the 18-bit latch.
A Schmitt trigger circuit is involved.

14

LE

I

Load enable signal input
When LE is high, the contents of the shift register are transferred to a latch, depending on the
control bit in the serial data. At the same time, an internal analog switch turns on and the
output of the internal charge pump is connected to the BiSW pin.
A Schmitt trigger circuit is involved.

15

FC

I

Phase select input of phase comparator (with internal pull-up resistor)
When FC is low, the characteristics of the charge pump and the phase comparator are reversed.
The FC input signal is also used to control the fOUT pin (test pin) of fR or fp.

16

BiSW

0

Analog switch output
Usually, BiSW is in the high-impedance state. When the switch is on (LE is high), the charge
pump is connected to the BiSW pin.

17

fp
fR

0
0

Programmable counter output monitor pins

18
19

NC

-

No connection

20

PS

I

Power save signal input
Set low when the system is operating (never use pin 20 as it is opened)
Operation mode
PS = High
PS =Low : Stand-by mode

Reference counter output monitor pin

MB1513

FUNCTIONAL DESCRIPTIONS
Pulse swallow function
The divide ratio can be calculated using the following equation:
fveo

=[(M x N) + A] x fose + A

(A < N)
fveo : Output frequency of external voltage controlled oscillator (VeO)
N
Preset divide ratio of binary ll-bit programmable counter (16 to 2,047)
A
Preset divide ratio of binary 7-bit swallow counter (0 ~ A ~ 127)
fosc : Output frequency of the reference frequency oscillator
R
Preset divide ratio of binary 14-bit programmable reference counter (8 to 16,383)
M
Preset divide ratio of prescaler (128)

III

Serial data input
Serial data is input using the Data, Clock, and LE pins. Serial data controls the 15-bit programmable reference divider and 18-bit
programmable divider separately.
Binary serial data is input to the Data pin.
One bit of data is shifted into the internal shift registers on the riSing edge of the clock. When the load enable pin is high or open,
stored data is latched, depending on the control as follows:
Control Data

(a)

Destination of Serial Data

H

15-bit latch

L

18-bit latch

Programmable reference divider ratio
The programmable reference divider consists of a 15-bit latch and a 14-bit reference counter. The 16-bit serial data format is
shown below:

----t.~

Direction of data shift

Divide ratio setting bit for programmable reference counter

4-299

MB1513
•

14-bit programmable reference counter divide ratio
Divide Ratio

S

S

S

S

S

S

S

S

S

S

13

12

11

10

9

7

6

S
5

S

14

S
8

S

R

4

3

2

1

8

0

0

0

0

0

0

0

0

0

0

1

0

0

0

9

0

0

0

0

0

0

0

0

0

0

1

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

.
16383

. . . . . . . . . . . . . .
(Divide ratio

Notes:

(b)

1. Divide ratios less than 8 are prohibited
2. SW: This bit selects the divide ratio of the prescaler
SW Low: 128 or 129
(SW must be always be low.)
3. S1 to S14: These bits select the divide ratio of the programmable reference counter (8 to 16,383)
4. C: Control bit: Set high
5. Data is input from the MSB.

Programmable divider divide ratio
The programmable divider consists of a 19-bit shift register, 18-bit latch, 7-bit swallow counter, and an 11-bit programmable
counter. The 19-bit serial data format is shown below:

- - - . . . . Direction of data shift

Divide ratio setting bit for
swallow counter

4-300

=8 to 16,383)

Divide ratio setting bit for programmable counter

MB1513
•

7-bit swallow counter divide ratio

Divide
ratio

11-bit programmable counter divide ratio

S

S

6

S
5

S

A

S
7

4

3

S
2

S
1

Divide
ratio
N

S
18

S
17

S
16

S
15

S
14

S
13

S
12

S
11

S
10

S
9

S
8

0

0

0

0

0

0

0

0

16

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

0

1

17

0

0

0

0

0

0

1

0

0

0

1

127

1

1

1

1

1

1

1

2047

1

1

1

1

1

1

1

1

1

1

1

. . . . . . ..

. . . . . . . . . . . .

(Divide ratio = 0 to 127)

Notes:

(Divide ratio:: 16 to 2,047)

1. Divide ratios less than 16 are prohibited for 11-bit programmable counters
2. Sl to S7: These bits select the divide ratio of swallow counter (0 to 127)
3. S8 to S18: These bits select the divide ratio of programmable counter (16 to 2,047)
4. C: Control bit: (Set low)
5. Data is input from the MSB.

Serial data input timing
•

t3 (;::: 1IJ.s): Clock pulse width
ts (;::: 1I1S): LE pulse width

t1 (;::: 1I1S): Data setup time
t2 (;::: 1IJ.s): Data hold time
t4 (;::: 1IJ.s): LE setup time to the rising edge of last clock

Data

~--~--~

~

(SW) (*1)'
Clock

LE

(S14)

__ ~ __
(S8)

,

(S7)

C: Control bit

LSB

(Sl)

(C: Control bit)

JlJJL--JlJJL--JLJL
,
t1-:--:-

'.

"

' ,
--------....t3 ~ - ......ts

* 1:

rL
, ,

...
, ......., t4

-i--i-

Bits enclosed in parentheses are used when the divide ratio of the programmable reference divider is selected.

Note:

One bit of data is shifted into the shift register on the rising edge of the clock.

4-301

MB1513
Intermittent operation
Intermittent operation limits power consumption by shutting down or starting the internal circuits according to their necessity. If
device operation resumes uncontrolled, the error signal output from the phase comparator may exceed the limit due to an
undefined phase relationship between the reference frequency (fA) and the comparison frequency (fp) and frequency lock is lost.
To prevent this, an intermittent operation control circuit is provided to decrease the variation in the locking frequency by forcibly
correcting the phase of both frequencies to limit the error signal output. This is done by the PS control circuit. If PS is set high, the
circuit enters the operating mode. If PS is set low, operation stops and the device enters the stand-by mode. Each mode is
explained below:
•

Operating mode (PS = High)
All circuits are operating, and PLL operation is normal.

•

Stand-by mode (PS = Low)
Circuits that do not affect operation are powered-down to save power.
The current in the power save state is typically 1001lA.
At this time, the levels of Do and LD are the same as when the PLL is locked.
Since Do is placed in the high-impedance state and the input voltage of the voltage-controlled oscillator (VCO) is set to the
voltage in the operating mode (when locked) by the time constant of the low-pass filter, the frequency output from the VCO
(fveo) is kept at the locking frequency.

The operating and stand-by modes alternate repeatedly. This intermittent operation limits the error signal by forcibly correcting the
phase of the reference and comparison frequencies to limit power consumption.
The device must be set in the stand-by mode (PS = low) when it is powered up.

Relationship between

Fe input and phase characteristics

The FC pin controls the phase characteristics of the phase comparator. The internal charge pump output level (Do) is reversed
depending on the FC pin input level. The relationship between the FC input level and Do is shown below:
FC = High or open

FC = Low

fA> fp

H

L

fA <, ,

/

/

,,

VCO Input Voltage _

4-302

/

,

/0

'0

MB1513
Phase comparator output waveform (Fe

=High)

fp

LD

Do -- - -

Notes:

-~ - - Z

'-----_ _ _ _--...11
-~-- --Jr---~---- --'[------- J --- -- --\--r

III

1. Phase difference detection range: -21t to +21t
2. Spike appearance depends on the charge pump characteristics. The spike is output to diminish dead
band.
3. When fR > fp or fR < fp, a spike might not appear, depending on the charge pump characteristics.
4. LD is low when the phase difference is tw or more. LD is high when the phase difference is tw or less for
three or more continuous cycles (when fOSCIN = 12.8 MHz, tw =625 to 1,250 ns).

Analog switch
The LE signal turns the analog switch on or off. When the analog switch is turned on, the charge pump output (Do) is output
through the BiSW pin. When it is turned off, the BiSW pin is in the high-impedance state.
When LE = high (when the divide ratio of the internal divider is changed): Analog switch = on
When LE =low (normal operating mode): Analog switch off

=

The LPF time constant can be decreased by inserting an analog switch between LPF1 and LPF2. This decreases the lock-up time
when the PLL channel is changed.

----------,

I
I

L ______ -,
I

(Control Signal LE)

------------------

BiSW

I
.JI

4-303

MB1513

RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol
Vee

Min

4.5

I

Value
Typ

Max

5.0

5.5

Unit
V

Supply Voltage
Vp

Vee::; Vp::; B.O

Input Voltage

VI

GND

Operating Temperature

TA

-40

-

V
Vee

V

+85

°C

HANDUNGPRECAUTIONS
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly
grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

4-304

MB1513

ELECTRICAL CHARACTERISTICS
Parameter

Symbol

Min

Value
Typ

Max

Unit

Conditions

With fiN =1.1 GHz, OSC'N :;:
12MHz, Vee =S.OV

Supply Current

Icc

-

B.O

-

mA

Stand-by Current

IPS

-

100

-

IlA

-

fiN

fiN

10

-

1100

MHz

AC coupling.The minimum
operating frequency is
measured with a 1000pF
capacitor connected

OSC'N

fose

-

12

20

MHz

-

fiN

PflN

-10

-

6

dBm

-

OSC'N

Vose

0.5

-

Vp-p

-

V,H

Vee x 0.7+0.4

-

-

V

-

V'L

-

-

Vee x 0.3-0.4

V

-

I'H

-

1.0

IlA

-

I,L

-

-1.0

-

IlA

-

FC

IFe

-

-60

-

IlA

-

OSC'N

lose

-

±50

-

IlA

-

VOH

4.4

-

-

V

Vee

VOL

-

-

0.4

V

-

Operating Frequency

Input Sensitivity

High-level Input Voltage
Low-level Input Voltage

Except fiN and
OSC'N

High-level Input Current
Data Clock LE

III

Low-level Input Current

Input Current
High-level Output VoltagE
Low-level Output Voltage

Except Do and
OSCOUT

VOO =GND to BV
Vee $; Vp $; 8V

High-impedance
Cut off Current

Do

10FF

-

-

1.1

IlA

Except Do and
OSCOUT

10H

-1.0

-

-

mA

-

Output Current

IOL

1.0

-

-

mA

-

RON

-

25

-

Q

-

Analog Switch ON Resistance

=5V

4-305

MB1513

TEST CIRCUIT
(FOR MEASURING· PRESCALER INPUT SENSITIVITY)

Vp==6V

1000pF

P G

~
1
50n

~

r--'--"""'-----'-....a..................--,

10 8 7 6 5 4 3 1
Vee == 5V

11 13 14 15 17 18 19 20

4-306

~

MB1513

APPLICATION EXAMPLE

I
I

LPF

I

I

I

I

VCO

1

Output

I

II

_ ] From

Controller

IfR Ifp

PS
20

19

17

18

LE

BiSwl FC
16

15

I

Data

Clock

14

13

12

11

7

8

9

10

"'"
:~ 47K ; ~ 47K

4

7i T

7.7-

MB1513

1

2

4

3

OSC1N

Hop-

Vp, Vpx:
C 1 , C2 :

t

!

Vcc

C

2

Do !ND ILD

5V

6V

X'tal
lC

6

5

oscou Vp

LI LJ
O.1~

~:

1000p

Vee (5V)

-'-

J;

Maximum 8V
Depend on the crystal parameters

4-307

MB1513

PACKAGE DIMENSIONS
20-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-20P-M03)

.049~:gg~
(1.25~:~g)

*.256±.004

(MOUNTING HEIGHT)

(6.5o±O.10)

I
INDEX

o

_ /

I

.252±.008
(6.4o±O.20)
.213(5.40) NOM

*.173±.004
(4.4o±O.10)

l4;=;j;::::;~:::;:;:::;:;:::~~

"A"

~

.

.

.0256±.0047
(0.65±o.12)

(0.22~:J~)
Details of "A" part
004±.004
(STAND OFF
(0.1 o±o.1 0)
HEIGHT)

.230(5.85)
REF

r::

[JJ
I~
OOto~

.02fr±OOB

(O.50±0.201

*:This dimension does not include resin protruction.

©1991 FUJITSU LIMITED F20012S-2C

4-308

Dimensions in
inches (millimeters)

00

Sept. 1995
Edition 1.0a

FUJITSU

DATA SHEET

MB1514
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 400MHz PRESCALER
The Fujitsu MB1514 is a dual serial input PLL (phase locked loop) frequency synthesizer designed for cordless telephone applications.
The MB1514 has two PLL circuits on a single chip; one for transmission (PLL-1)
and the other for reception (PLL-2). Separate power supply pins are provided for
each PLL circuit. Transmission PLL contains a low sensitivity charge pump for
modulation, and reception PLL contains a high sensitivity charge pump for fast
lock-up time. 400MHz dual modulus prescalers are provided and enables a pulse
swallow function.
MB1514 operates at 3.0 V typo power supply voltage and dissipates SmA typo of
current realized through the use of Bi-CMOS technology.

PLASTIC PACKAGE
DIP-20P-M02

FEATURES
• Low voltage operation: Vee =2.2V to 4.2V
• High operating frequency: fin

=400MHz (Pin =-1 OdBm, Vee =3.0V)

• Low current consumption: Icc =SmA typo (Vcc =3V)
• Power saving function
• Two charge pumps
Low sensitivity charge pump for transmission (PLL-1)
High sensitivity charge pump for reception (PLL-2)

PLASTIC PACKAGE
FPT-20P-M01

• Plastic 20-pin DIP package (Suffix: -P)
Plastic 20-pin SOP package (Suffix: -PF)

PIN ASSIGNMENT
GND

Clock

OSCIN

ABSOLUTE MAXIMUM RATINGS
......... ··>,,",i.,; . . . >. •. •.•.•. .•. .•. i\> •..••••••.•••••.••

.... ;............

... ..:

.......

...................
.......

Supply Voltage
Output
Voltage

OSCOUT, Do, BS
LO, LFo

Output Current
Storage Temperature
NOTE:

.

Vee
VOt
V02

......

..... .··.i»<·

Data

OSCOUT

LE

fint

fin2

VCCt

-0.5 to +6.0
-0.5 to Vcc+0.5
-0.5 to +6.0

VCC2

V

LD

V

LFot

LF02

LFll

LFI2

PS

V

Dol

002

eSt

eS2

10

±10

mA

TSTG

-55 to +125

°c

Pennanent device damage may occur ifthe above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

DIP-20P-M021
FPT-20P-M01
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields.
However, it Is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated
voltages to this high impedance circuH.

Copyri9ht© 1992 by FUJITSU LIMITED

4-309

MB1514

BLOCK DIAGRAM
LFll

VCCl

LFol

------- -- ------- --- ------- ------ --- ----- --.
20-bit latch (PLL1)

LD1/LD2
LE2

PS

NOTE;
PLL 1 : Transmission section
PLL2: Reception sedion

4-310

VCC2

GND

LFI2

LFo2

MB1514

BLOCK DESCRIPTIONS
TRANSMISSION/RECEPTION BLOCK
• 20-bit latch
• Programmable divider;
Binary 7-bit swallow counter (Divide ratio: 0 to 127)
Binary 11-bit program mabie counter (Divide ratio: 16 to 2047)
The programmable dividers for transmission and reception are able to be controlled independently.
• Phase detectors with phase polarity change function
• 400MHz dual modulus prescalers (Divide ratio: 64165)
• Charge pumps
• Transistors for LPFs

III

• Analog swithes

COMMON BLOCK
• 23-bit shift register
• Reference divider;
Reference counter (Divide ratio: 1700)
(Divide frequency = 12.5 kHz (Crystal oscillator frequency = 12.8 kHz))
• Crystal oscillation circuit
• Latch selector
• Shmitt circuits
• LD/frlfp output selector

4-311

MB1514

PIN DESCRIPTIONS
PinHo. SYmbol

Pin Descriptions

tlO

:

1

GND

-

Ground.

2

OSCIN

I

Input and output of a reference divider and a crystal is externally connected between these

3

OSCOUT

0

pins.

4

finl

I

..

Input of a prescaler of PLL-1 (Transmission section).
Connection with a VCO should be AC (capacitor) coupling.

5

VCCl

-

Power supply for PLL-1 block.
When power is cut off, PLL-1 block's latched data is cancelled.

6

LD

0

Output of lock detectors, a reference divider, and programmable dividers.

7

LFol

0

Output of the transistor, used for transmission LPF.

Output data is selected by data setting of LD bits in the serial data. This is open-drain output.

8

LFI1

I

Input of the transistor, used for transmission LPF.

9

DOl

0

Output of the charge pump(PLL-1).

10

851

0

Output of the analog switch(PLL-1).

Phase polarity is inverted by FC bit setting in the serial data.
Usually this pin is high-impedance state. When LE is set to high, the state of the internal
charge pump is output.
11

852

0

Output of the analog switch(PLL-2: reception section).
Usually this pin is high-impedance state. When LE is set to high, the state of the internal
charge pump is output.

12

D02

0

Output of the charge pump{PLL-2).
Phase polarity is inverted by FC bit setting in the serial data.

13

LFI2

I

Input of the transistor which is used for reception LPF.

14

LF02

0

Output of the transistor which is used for reception LPF.

15

PS

I

Power saving control for PLL-2 circuits.

PS

4-312

,

State

...

, .. ': .. '.

,

H

Active state

L

Power saving state
(Crystal oscillation circuit and PLL2 circuits are
inactive)

."\

MB1514

PIN DESCRIPTIONS
Pin No.
16

Symbol
VCC2

Pin Descriptions

1/0

-

.........

Power supply for Pll-2 circuits, a reference counter, a shift register, and a crystal oscillation
circuit. When power is cut off, Pll-2 block's and reference counter's latched data are
cancelled.

17

tim

I

Input of a prescaler of Pll-2.
Connection with a VCO should be AC (capacitor) coupling.

18

lE

I

load enable signal input. This pin involves a schmitt trigger circuit.
When this pin is high (lE="H'j, the data stored in a shift register is transferred into the latch
according to the control bit in the serial data.

II

And at the moment, internal analog switch is closed(ON), then each charge pump output
signal is output through the
19

Data

I

as pin.

Serial data input. This pin involves a schmitt trigger circuit.
The stored data in the shift register is transferred to either transmission or reception sections
depending upon the control bit as follows.
Control bit dab

20

Clock

I

.', . . The destination of data ....

H

latch of Pll-1 (transmission)

l

latch of Pll-2 (reception)

Clock input pin of 23-bit shift register. This pili involves a schmitt trigger circuit.
Each riSing edge of the clock shifts one bit of data into the shift register.

FUNCTIONAL DESCRIPTIONS
Divide ratio can be set using the following equation:
tvco = { (M x N) + A} x fosc ~ R (A < N)
fvco: Output frequency of an external voltage controlled oscillator (VCO)
M: Preset divide ratio of an internal dual modulus prescaler (64)
N:

Preset divide ratio of binary 12-bit programmable counter (16 to 2047)

A:

Preset divide ratio of binary 5-bit swallow counter (0 ~ A ~ 127)

fosc: Output frequency of the external reference frequency oscillator
R:

Preset divide ratio of reference counter (1700)

4-313

MB1514

FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data is input using three pins; Data, Clock, and LE pins. Programmable dividers of PLL-1 and PLL-2 are controlled individually.
Serial data of binary data is input to the Data pin.
On rising edge of the clock shifts one bit of the data into the shift register.
When the load enable (LE) is high, the data stored in the shift register is transferred to either the latch of the transmission or the reception sections, depending upon the control bit setting.

Controlbft data

The destination of data

H

Latch of PLL-1 (transmission)

L

Latch of PLL-2 (reception)

SHIFT REGISTER COSTITUTION

• oata Input FIow

Th I t b·it (Contro lb·It)
e LSB
as

r~

r

1

2

3

4

5

C
N

L
0
1

L
0
2

0

F
C

T

The first bit (MSB~
..

N1 to N11
A1 to A7
FC
DMY
LD2
LD1
CNT

M

6
A
1

7

8

9

10

11

12 13 14

15 16

A
2

A

A
4

A

A
6

A
7

N

3

5

N
1

N
2

3

N
4

17 18 19

20 21

N

N
8

5

N
6

N
7

22 23
N N
10 11

N

9

Y

: Divide ratio of the programmable counter setting bit (16 to 2047)
: Divide ratio of the swallow counter setting bit (0 to 127)
: Phase control bit of the phase detector
: Dummy bit (set to "L" as a rule)
: Select bit of LD output (LD, fr, fp1, fp2)
: Select bit of LD output (LD, fr, fp1, fp2)
: Control bit

BINARY "-BIT PROGRAMMABLE COUNTER DATA SETTING
11-bit programmable counter divide ratio (N1 to N11)
I,'
N
Divide ratio
N
N.: ·.' . . N
····'··8
11
10
..
9

N
7

N
·,·:".6

N
5

0

1

N
··,'·4
> ..

N

N

3

2

0

0

0

,N
1

16
17
:

0

0

0

0

0

0

0

0

0

0

0

1

0

:

:

:

:

0
:

0

:

:

:

2047

1

1

1

1

1

1

1

1

1

:
1

1

NOTE: Divide ratio less than 16 is prohibited.

4-314

i

0
1

"

•...

M81514
BINARY 7-BIT SWALLOW COUNTER DATA SETTING
7-bit swallow counter divide ratio (A1 to A7)

A
7

DIvide ratio

A
0

0

1

0

2
127

A

6

A
5

A

A
3

A
2

A

4

0

0

0

0

0

1

0

0

0

0

1

0
:

0
0
0
:

0
:

0
:

0

1

0

1

1

1

1

1

1

1

III

LD1, LD2 : LD OUTPUT SELECT
LD1

L02

1

1

Reference frequency (fr)

LOOutput

1

0

PLL-1 programmable frequency (fp1)

0

1

PLL-2 programmable frequency (fp2)

0

0

Lock detector output

DMY: DUMMY BIT
Set to "L" as a rule

SERIAL DATA INPUT TIMING
tl
t4

(~
(~

1 JlS) : Data setup time
t2 (~ 1 JlS) : Data hold time
1 JlS) : LE setup time to the rising edge of the last clock

N11:
--Data _ _ _
(M_S_B.,,), N10 ___

,,

b (~ 1 JlS) : Clock pulse width
ts (~ 1 JlS) : LE pulse width

--;V;;----~

.::.A..... _..~_N_T

_ _ _ _ __

ClockJUfL.JLJL ..fW1LE

----_-i--- -· -~,....­
pi

I
..
t2__

I

,

,

,' ''

rL
I

~'~.---I-----:
b~
~t4-"':'

, ,

'

I

•

ts.~
,

I

NOTE: On rising edge of the clock shifts one bit of the data into the shift register.

When LE is high, the data stored in the shift register is transferred into the latch.

4-315

MB1514
PHASE DETECTOR CHARACTERISTICS
Fe bit selects the phase of the phase detector. Phase characteristics (chage pump output) can be reversed depending upon
the Fe bit of the serial data. The phases of the charge pump outputs through LO pin are reversed depending upon the Fe bit
as well.

i~

FC="H"
001, D02, LD(fp1. & fp2) output

FC="L"
.<.,

001, 002, LD(fp1 & fp2} output

fr> fp

H

L

=fp

Z·

Z·

fr < fp

L

H

fr

·Z: High-impedance

VCO POLARITY

\;2.:':.•

"'> .' .
:~;:"'" '.'"
.-:"'.
"'.

,

'

.

....

,','. ".,:>

Power Supply Current

.:,,,":

:

',:.':':.

:'.: . . ,:',:?\

1-'(. I) '. « :

.

(VCCl =VCC2 =2 2V to 4.2V, Ta =_10°C to + 70°C)
I':
'."
:<\ If:>,. . : : . . . <.·:/i.,. :J,a~~,~' : .." "· •. i"i?i i i ' .::..••• :.: •••• Ii
lill~~~>,.',.:'

i)\. '.•'.•. • • . <' 1....iI r~I~:' ." ". t\t[":':

:MM>: lii·".:i<:.::·:

I}i

Icel

PLL-2 Current

-

4.0

-

rnA

lec2

PLL-1 + PLL-2 Current

-

8.0

-

rnA

-

400

fin

finl

10

OSCIN

fose

-

fin

Pfin

OSCIN

Vose

Operating Frequency
50n system

21.25

-

MHz

-10

-

0

dBm

0.5

-

-

Vp-p

-

-

Input Sensitivity
High-\evellnput Voltage
Low-level Input Voltage
High-level Input Current
Low-level Input Current

Except fin
and OSCIN

VIH

VccxO.7+0.4

-

VIL

Data,
Clock,
LE,PS

IIH

OSCIN

losc

ilL

-

V
VcexO.3-0.4

1.0

-

-1.0

J,lA

±50

Input Current
LFi
High-level Output Voltage
LOW-level Output Voltage
High-impedance Cutoff
Current

Output Current

4-318

Except Do,
OSCOUT

ILF

1.1
2.2

-

-

-

-

0.4

-

-

1.1

-

-

10.0

10H

-1.0

-

-

10L

1.0

-

-

Vose

Vec= 3.0V

V
VOH

Do,LFo
10FF
LD
Except Do,
OSCOUT

J1A
mA

MB1514

ELECTRICAL CHARACTERISTICS
(Vee,

Parameter

Symbol

IOL
10H

002
10L

Unit

Min

Typ

Max

-

-0.5

mA

=3.0V
Vee =3.0V
Vee =3.0V
Vee =3.0V

Output Current

Analog Switch ON Resistance

Value

Condition

-

12

-

-1.5

-

-

6

-

mA

-

50

-

n

Vee

10H

Do,

=Vee2 =2 2V to 4 2V Ta =-10°C to + 70°C)

Ron

mA
mA

III

TEST CIRCUIT (FOR PRESCALER INPUT SENSITIVITY)
Vee'

Crystal

D
1000pF
P.G

P.G

1
1

Oscilloscope
GND

10

9

8

7

6

5

4

3

2

17

18

19

MB1514
11

12

13

14

15

16

20

1000pF

r

O.1Il F

HANDLING PRECAUTION
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly
grounded. Cover work-benches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC bords with devices.

4-319

MB1514

APPLICATION EXAMPLE

I

OUTP UT

I

VCO

I

LPF

I

III
3V

.,.

1000pF
From {
controller

....

rl·1f..1.F

::

1

~

Clod<
20

Data
19

LE
18

POW ERSAVING
CONT ROLSIGNAL

VCC2

fin2
17

r-

16

LF02

PS

14

15

LFI2

BS2

D02

13

12

11

8

9

10

MB1514

1
GND
11'

OSCIN PsCou

~
f ~
stal
C1

OUTPUT

4

3

2

I
I

5
fin1

6

VCC1

LD

J

C2 :

LF01

LFI1

D01

BS,

3V

3V

0.1f..1.

,

7

't

LOCK DETECTOR

4kO

:

~OOOpF

II
VCO

LPF

I

I

NOTE;
C1, C2 : depends on the aystal oscillator.
Clock, Data, LE : Using shmitt trigger circuits (When inputs are left open, pull-down or puH-l4> resistors are necessary
to prevent 06ciUation.)
Crystal: 21.25MHz
LD
: Open drain

4-320

MB1514

PACKAGE DIMENSIONS
2O-LEAD PLASTIC DUAL IN· LINE PACKAGE
(CASE No.: DIP·20P·M02)

1

~, f - - - - - -

INDEX-1

.970

~:~~ (24.64 ~g:~)

-------.1'1

r;:::::::=================~

o

!

III

.244±.010
(6.20±0.25) .300(7.62)

/I.C:;::;:=;:::;::::;::::;:::;:::::;::::;:::::;::::::;:::;:::::;:::::;::::;:=;:::::;;:::::;::::~

~

TYP

_+L--- ----=~

.11 ~034 ~0012
(0.~·30)

.172(4.36)MAX

.11S(3.00)MIN
.100(2.54)
.050(1.27)

TYP

. / / . .01S±.003
(0.4e±o.OS)

.020(0.51)MfN

MAX

©1991 FWITSU LIMITED D20003S-3C

Dimensions in
inches (millimeters)

4-321

MB1514

PACKAGE DIMENSIONS (Continued)
20-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-20P-M01)

.089(2.25) MAX
(MOUNTING HEIGHT)
.002(0.05) MIN
(STAND OFF HEIGHT)
~:-+----.-

+. 016 (680+0.40)
.268-.008· -0.20

INDEX

cf

O~~27)

.11 ..

O'45±QB±.004
(0.
.10)

'.1

1I==tI

.0000.OO'
(O.5O±o.20)

.u- .OO6~:gg~(0.15~:g~)

¢.OO5(0.13xgl

-.,...~----....

,--------,
I Details of "A" part I
"A"

,

-..

I
I
I
1

I

1

I
1

. . . - - - - .450(11.43) REF - - - - . !

4·322

.008(0.20) I

I
I
1

1

.020(0.50)1
.007(0.18) I

MAX
.027(0.68)

I

L _ _ _ _ MAX
_ _ _ .J
1

FUJOJI"SU
=~~nzo~a~~~~~~~
I,
Sept. 1995

=

DATA SHEET

MB1515

ASSP
BiCMOS 2.5GHz PLL FREQUENCY SYNTHESIZER
WITH BUILT-IN PRESCALER

DESCRIPTION
The MB1515 is a serial input PLL (Phase-Locked Loop) frequency synthesizer with
a built-in prescaler allowing for a pulse swallow system in the two modulus 2.5 GHz
band. It is suitable for BS and TV tuners and CATV systems.
The synthesizer is powered by 5 V (typical). Using the latest proprietary process,
current consumption has been reduced to Icc = 16 mA (typical).

2O-pin Plastic
SSOP

FEATURES
• Supply voltage: Vee

=5 V

• High-speed operation capability: fin
• Low current consumption: Icc

=2.5 GHz (Pin = - 4 dBm)

=16 mA (typical)

• Broad operating temperature range: Ta

= - 40°C to +85°C

• Integrated Functions
24-bit shift register
24-bit latch
Reference divider
Binary 2-bit programmable reference counter (Divide ratios: 256, 512,
1024, and 2048)
Comparison Divider
Binary 5-bit swallow counter (Divide ratios: 0 to 31)
Binary 12-bit bit programmable counter (Divide ratios: 32 to 4095)
Phase comparator with phase conversion feature
Two modulus prescaler for 2.5 GHz band (Divide ratios: 256/272 and 512/528)
4-bit band switching signals
Control signal generator
Crystal oscillator
Charge pump

(FPT-20P-M03)

MAXIMUM RATINGS
Symbol

Value

Units

Supply voltage

Vee

-0.5 to +7.0

V

Output voltage

Vo

-0.5 to Vee+0.5

V

Output current

10

±10

mA

Tstg

-55 to +125

°C

Parameter

Storage temperature

RECOMMENDED OPERATING CONDITIONS
Value
Symbol

Min.

Typ.

Max

Vee

4.5

5.0

5.5

V

Input voltage

VI

GND

Vee

V

Operating temperature

Ta

-40

-

+85

°C

Parameter
Supply voltage

Unit

NOTES:
1. To prevent damage caused by static electricity, an antistatic element is added and
antistatic enhancement is also built into the circuit. However, the following handling
cautions must be observed:
o
Contain the device in a conductive case when storing or transporting it.
o
Before handling, verify that the person handling the device, fixtures, and tools are not
charged (grounded). Use a grounded conductive sheet as the wor\( surface.
o Tum off power before connecting or disconnecting the device to or from the socket.
o
Protect the lead with a conductive sheet when handling (such as transporting) a
board on which this device is mounted.

This device contains circuitry to protect the inputs against damage
due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid application of any
voltage higher than maximum rated vottages to this high
impedance circu~.

4-323

MB1515
PIN ASSIGNMENT
(Top view)

FC

20

LD

LE

2

19

fout

Data

3

18

VCC2

Clock

4

17

fin

VCCI

5

16

GND2

OSCin

6

15

fin

OSCout

7

14

BCl

GNDl

8

13

BC2

Dol

9

12

BC3

Co2

10

11

BC4

(FPT-2OP-M03)

4-324

MB1515
PIN DESCRIPTION
VO

Descrlprlon

1

FC

I

Phase switch input pin to the phase comparator (with pull up resistor). This pin allows for inverting the polarity
of phase comparator output, according to the polarity of the externally connected LPF and VCO. When FC is
at "L" level, charge pump and phase comparator characteristics are reversed. This pin also toggles the output
of the fout pin (test pin) between fr and fp.

2

LE

I

Load enable signal input pin (with Schmitt trigger circuit). The pin sends shift register contents to the latch
when LE is at "H" (or open).

Pin No.

Pin name

3

Data

I

Serial data input pin using binary codes (with Schmitt trigger circuit).

4

Clock

I

24·bit shift register clock input pin (with Schmitt trigger circuit). Data is read at the rising edge of the clock
pulse.

S

VCC1

-

6

OSCin

I

Power supply pin (for PLL).
Cystal oscillator connect pin and reference divider input pin. (OSCin: Oscillator input pin, OSCout: Oscillator
output pin)

7

OSCout

0

8

GND1

-

Grounding pin (for PLL)

9

001

0

Charge pump output pin. Phase characteristics invert with FC pin settings.

10

002

0

11

BC4

0

12

BC3

0

13

BC2

0

14

BC1

0

15

fin

I

-

Band switch output pin (open collector output). Output is controlled by the serial data band bit setting.
When BCX bit is "H", the BCX output transistor turns ON.
When BCX bit is "H", the BCX output transistor turns OFF. (X: 1 to 4)

fin's complementary input pin. Connect to ground via a capacitor.

16

GND2

17

lin

18

VCC2

-

Power supply pin (for prescaler).

19

fout

0

Phase comparator input monitor pin.Produces either the reference divider
output (fr)or the comparison divider output (fp) signal depending on the
FC pin's input level.

20

LD

I

0

III

Ground pin (for prescaler).
Prescaler input pin. Input using ac coupling.

FC

Output Signal

"H"

fr

"L"

fp

Phase comparator output pin. LD is usually "H", and is set to "L" for the duration equivalent to the phase error
between fr and fp.

4-325

m

~

r-

W
N

o
o

m

~

c

~~ lGjl Lin I

);
C)

:D
~

==

5-bit swallow
counter

(A

=Ot031)

s::

12-bit programmable
counter
(N 32 to 4095)

OJ
.....

fp

=

(J1

.....

fr

,

I

(J1

Reference counter

>I (A = 256, 512, 1024,2048)
Charge pump
Crystal oscillator

~

~

MB1515
ELECTRICAL CHARACTERISTICS
Value
Parameter

Symbol

Condition

Min.

Icc

When input at fin=2.5GHz
and OSCin= 4MHz,
Vcc=5V. Other input pins
are GND and output pins
are open.

-

fin

fin

Must be AC-coupled. The
minimum operating frequency when coupled at
1000 pF.

100

OSCin

fose

-

Pfin1

2300 to 2500 MHz

Power supply current

Operating frequency

-

OSCin
High level input voltage
Other the fin
andOSCin

High level input current

Data, Clock,
LE

4

-

2500

Units

rnA

MHz

10

MHz

-

6

dBm

Pfin2

1900 to 2300 MHz

-7

-

6

dBrn

Pfin3

1000 to 1900 MHz

-10

6

dBrn

Pfin4

100 to 1000 MHz

-20

-

6

dBm

-

Vp•p

Vose

-

-

-

-

-1.0

-

-60

-

±50

IIH

-

-

FC

IILFC

Input current

OSCin

Ilosc

High level output voltage

VOH

Low level output voltage

Excluding
Do and BC

High impedance cutoff
current

Do 1,2 BC
1 t04

V

-

IlL

Low level input current

0.5
Vcc xO .7
+0.4

V IH
V IL

Low level input voltage

16.0

Max.

-4

fin
Permissible input voltage

Typ.

When Vcc =5 V

1.0

Vcc xO .3
-0.4

-

-

V
!LA
!LA
!LA
!LA

4.4

-

-

V
V

VOL

-

-

-

0.4

IOFF

-

-

-

1.1

!LA

-

-

-

rnA

Output current

Excluding
Do and BC

IOH

Output voltage breakdown

BC1 t04

VB

IOL

-1.0
1.0

-

12

rnA
V

4-327

MB1515
FUNCTIONAL DESCRIPTIONS

1. Formula for calculation of divide ratio
Set divider's divide ratio according to the following formula:
fveo
where
fveo
P
N
A
fose
R

=[(P x N) + (16 x A)] x fose + R
Externally connected veo output frequency
Prescaler divide ratio (256 or 512)
Binary 12-bit programmable counter setting (32 to 4095)
Binary 5-bit swallow counter setting (0 to 31)
Reference oscillation frequency
Reference counter setting (256, 512, 1024,2048)

2. Serial data input procedure
Serial data is input from three inputs, Data pin, Clock pin and LE pin, allowing for control of the 4-bit band switch setting, the 3-bit reference
divider and the 17-bit comparison divider respectively. The data is sequentially fetched into the internal shift register at the rising edge
of the clock and transferred to the latch when load enable is at the "H" level.
The 24-bit shift register is configured as follows:

r-

.A
1

A
2

Leading bit ~

Lastbit

MSB

LSB

A
3

A
4

A
5

I~Swallow counter divide~I·

N
1

N
2

N
3

N
4

N

5

N
6

N

7

N
8

N
9

N
10

N
11

Programmable counter divide ratio setting bits

N
12

S

R

R

W

1

2

B
C
4

-I

ratio setting bits

----.
B
C

2

Band switch
setting bits

Prescaler divide ratio setting bit Reference counter divide ratio setting bits

Band switch setting (BC1 to BC4)
When data set in the band bits is at "H," output is turned ON. When data is at "L,n output is turned OFF.
Prescaler divide ratio (SW)
Divided by 256/272 when data set in the SW bit is at "H." Divided by 5121528 when data is at "L."

4-328

B
C
3

B
C
1

MB1515
Divide ratios for 5-blt swallow counter (Alto AS)
Divide ratio A

AS

A4

A3

A2

A1

0

0

0

0

0

0

1

0

0

0

0

1

2

..

0

..

0

..

0

..

1

..

0

..

31

1

1

1

1

1

III

Reference counter divide ratios (Rl and R2)
Divide ratio R

R2

R1
0

256

0

512

0

1

1024

1

0

2048

1

1

Divide ratios for 12-blt programmable counter (Nl to N12)
Divide ratios

N12

N11

N10

N9

N8

N7

N6

NS

N4

N3

N2

N1

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

1

0

0

0

0

0

0

1

0

2

..

0

..

0

0

0

0

0

1

0

0

0

1

0

.. .. .. .. .. .. .. .. .. .. ..

4095

1

1

1

1

1

1

1

1

1

1

1

1

4-329

MB1515
3. Serial data input timings
When designing the synthesizer, control the Fe pin according to the veo polarity.

Data

BC2

Clock·

lE*

_

.~·.~~~~~~X.~·.~~·.~~·.=:X ~_l~_B_)

__

JlJJL
........ILln
. . . . JLJL
: :
::
::
i
fl
1

i

I
I

I

t1

I

~:--,

i

I
I

I

I

-:,

iii.

1

I

b

I

~

I

t

I

I
I

I

b----t:---

I

--;,'

I

I
I

t

t. :.-:

I

:

:

1~

15

tl, 12, b, tA, 15 :2 1 J!S
*: Fetches data at the rising edge of the clock.
*: Fetches data when lE is at "H" level.

4.

Fe pin input in relation to phase characteristics

The Fe pin switches the phase of the phase comparator. Phase characteristics (charge pump output) are inverted by contrOlling this
pin. Output from the phase comparator input monitor pin (fout) is also controlled by this Fe pin. The relation of Fe pin input with Do and
fout is as follows:
FC: "H" (or open)

fout

001,002

fout

fr>fp

H

l

fr=fp

Z

Outputs reference
divider output (fr)

Outputs comparison
divider output fp

fr< fp

fr dp

Notes:
1. The phase error is detected in a range of - 2 It to +2 It.
2. Output of a "glitch" varies slightly with charge pump characteristics. This "glitch" is output to eliminate an dead band.

4-331

MB1515
EXAMPLE MEASUREMENT CIRCUIT (PRESCALER INPUT SENSmVITY)

pat

1000p

;;;

1000p

SOC

4-332

20

0.11L

19

18

17

16

15

14

13

12

11

2

3

4

5

6

7

8

9

10

MB1515
EQUIVALENT CIRCUIT DIAGRAM

• FC

• fin, fin

III
• LE, Data, clock

• LE, Data, clock

• OSCin, OSCout

• LE, Data, clock

• BC1, BC2, BC3, BC4

4·333

MB1515
EXAMPLE APPLICATION

VT

Tuner

BC1

La

BC2

BC3

BC4
12V

5V

T
~100Op

t:>, r: r: 0~47K
~Op
;~

0.1J.li

~

ILD Ifout
20

19

Vccz
18

GND2 fiji

fin
11

16

15

BC1

~

~

~

BC3

BC4

BC2

14

13

12

11

7

8

9

10

MB1515

1
FC

4

3

2
LE

Data

5
Clock

from

Controller

""

C 1, C2: Determined by the crystal oscillator
FC: with pull up resistor

4-334

VCCI

OSCin

U

.l'llr
,..
...,
,..
...,

6

j.

0.1 J1

1 Dol
OSC,tND
out

HOJX'taJ

,tCI ,;;Cz

33V

Doz

-r~

II
II

Hi

"

II
I

......

MB1515
ORDERING INFORMATION
Parts Number

Package

M81515PFV

Plastic SSOP, 20 pins
(FPT-20P-M03)

Notes

EXTERNAL DIMENSIONS
20-pin plastic SSOP
(FPT-20P-M03)

o

/

(MOUNTING
HEIGH!)

III

I

INDEX

~

.049~:=
(1.25~:~)

Ll

.213(5.40) NOM

•. 173±.004
(4.40±0.10)

~::;:::::;::;::;:::;::;:::::;:;~~

'A' ----..:

'".::t- .006~:~(O.15~:~)

.0256±.OO47
(0.65±0.12)
r

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

.................... - - ......................

i

Details of •A· part
.004±.004
(0.1 O±O. 1 0)

(STAND OFF
HEI GHT)

.230(5.85)
REF

.:This dimension does not include resin protruction.

~1992

FUJITSU UMITED F20012S-2C

1- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . _ .. I

Dimensions in
inches (millimeters)

4-335

4-336

0')

FUJITSU

June 1995

Edition 0.1

MB15A16
1.2GHz HIGH-SPEED TUNING PLL FREQUENCY
SYNTHESIZER
The Fujitsu MB15A16 is a serial input phase-locked loop (PLL) frequency synthesizer
with a pulse-swallow function, and is very suitable for the digital radio applications
such as GSM. MB15A16 achieves the low noise performance as well as the high-speed
lock-up which is required for digital cellular phones.

1]1

The MB15A16 can operate from a single +3 V supply and has an Iccof7.0 mA (typical).

FEATURES

=

Pulse-swallow function

: fiN
1.2 GHz (PIN = -10 dBm)
: High-speed dual-modules prescaler with selectable
64/65 and 128/129 divide ratios

•

Low supply current
Power saving funtion

: Icc 7.0 rnA typo at 3 V
: Ips = 100 J,LA typo (Controlled with PS pin)

•

Serial input, 18-bit programmable divider consisting of:
Binary 7-bit swallow counter
: 0 to 127
Binary 11-bit programmable counter: 5 to 2,047

•

Serial input 17-bit programmable reference divider consisting of:
Binary 14-bit programmable reference counter: 6 to 16,383
1-bit for setting a prescaler divide ratio (SW bit)
1-bit for switching a phase polarity (FC bit)
1-bit for selecting LOlfout (LOS bit)

High operating frequency

=

PIN ASSIGNMENT
(TOP VIEW)
OSCIN

•

On-chip high performance charge pump circuit and phase comparator, achieving
high-speed lock-up and low phase noise

•

Two types of phase comparator outputs selectable
On-chip charge pump output
Output for an external charge pump

•

Wide operating temperature range: -40 to +85°C
Plastic 16-pin SSOP (shrink small outline) package (Suffix: -PFV)

OSCou

Vp

LD/fout

Vcc

NC

Do

PS

GND

LE

XflN
fIN

Data
Clock

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Ratings
Supply voltage
Output voltage

Symbol

Unit

Vce

-0.5 to +5.0

V

Vp

Vee to 5.5

V

Vo

-0.5 to Vec +0.5

V

Open drain voltage

VOOP

Output current

10

Storage temperature

Tstg

NOTE:

Value

-0.5 to 6.0

V

±10

mA

-55 to +125

°C

Remark

P

Permanent device damage may occur if the above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

This Clevice contains circurtry to protect the inputs
against damage due to high static vohagas 01 electrIc
fields. However. rt is advised that normal precautiOns be
taken to avoid applicatiOn of any vohaga higher than
maximum rated vohagas to this higll impedance CIrcuit.

4·337

MB15A16

BLOCK DIAGRAM

r-------,
,
Programmable
I
,

reference divider
Binary 14-blt
reference counter

,
Ir

Phase
comparator

Ip

1

P

LO

~--~~----~~~~I

LDlfrlfp
selector

I

LE

lIalalilIL_~

I

1--f---4-......
II
DATA

19-bit shift register

I

19-bit shift register

1'1

,

I

nmmmmrr

Do

,..----------,

LE

s
Prescaler

64/65.
1281129

I

,

18-bit latch

,

,

'".--------,

I
111 .bitlatchl,

,

lTnTn1fllTOTr
r----------,
I

Programmable divider

I
I
I
I
Ip

4-338

1-+-----_(11 LDlfo

'------I

MB15A16

PIN DESCRIPTION
Pin No. Pin name

Description

VO

1

OSCIN

I

Programmable reference divider input.
Oscillator input.
Connection for external a crystal or a TCXO.

2

OSCOUT

0

Oscillator output.
Connection for an external crystal.

3

Vp

4

Vee

-

5

Do

0

Charge pump output.
Phase of the charge PUITIP can be reversed according FC input.

6

GNO

-

Ground.

Power supply input for the charge pump.
Power supply input.

7

Xfin

I

Prescaler complementary input, and should be grounded via a capacitor.

S

fin

I

Prescaler input.
Connection with an external VCO should be done AC coupled.

9

Clock

I

Clock input for 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.)

10

Data

I

Serial data input using binary code.
The last bit of the data is a control bit. (Open is prOhibited.)
Control bit ="W; Data is transmitted to the 17-bit latch.
Control bit ="L" ; Data is transmitted to the 1S-bit latch.

11

LE

I

Load enable signal input (Open is prohibited.)
When LE is high, the data of the shift register are transferred to a latch, according to the
control bit in the serial data.

12

PS

I

Power saving control input. This pin must be set at "L" at Power-ON. (Open is prohibited.)
PS ="H" ; Normal mode
PS ="L" ; Power saving mode

13

NC

-

No connection.

14

LO/fOUT

0

Lock detector output(LD)lMonitor pin of the phase comparator(fout).
A LOS bit in a serial data switchs LD/fout pin's output.
LOS ="H" ; outputs fout
LOS ="L" ; outputs LD

15

4>P

0

Phase comparator output for an external charge pump.
Phase of the output is reversed according to FC input.
cl>P pin is a N-ch open drain output.

16

cl>R

0

Phase comparator output for an external charge pump.
Phase of the output is reversed according to FC input.
cl>R pin is a C-MOS output.

II

4-339

MB15A16

FUNCTION DESCRIPTIONS
Pulse swallow function
The divide ratio can be calculated using the following equation:
fveo =[(M x N) + AJ x fose + R (A < N)
fveo : Output frequency of external voltage controlled oscillator (VCO)
N
: Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0 SA S 127)
fose : Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14-bit programmable reference counter (6 to 16,383)
M : Preset divide ratio of modules prescaler (64 or 128)

Serial data input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the 16-bit programmable reference divider and 18-bit
programmable divider separately.
Binary serial data is entered via the Data pin.
One bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable pin is high or open, stored
data is latched depending on the control data as follows:
Control data

(a)

Destination of serial data

H

17 bit latch

L

18 bit latch

Programmable reference divider ratio
The programmable reference divider consists of a 17-bit latch and a 14-bit reference counter. The serial 18·bit data format is
shown below:

- -___•• Direction of data shift

Divide ratio setting bit for programmable reference counter
Phase switching bit
LDlfout selecting bit

4-340

MB15A16
•

14·bit programmable reference counter divide ratio

Divide ratio

S

S

S

S

S

S

S

S

12

11

10

8

7

6

4

3

S
2

S

13

S
5

S

14

S
9

S

R
6

0

0

0

0

0

0

0

0

0

0

0

1

1

0

7

0

0

0

0

0

0

0

0

0

1

1

1

•
16383

. .
1

1

1

•

.

0

•

. .

0

•

•

•

. .

•

.

1

1

1

1

1

1

1

1

1

1

1

1

II

=

(Divide ratio 6 to 16,383)
Not.s: 1. Divide ratios less than 6 are prohibited.
2. SW: This bit selects the divide ratio of the prescaler.
Low: 128 or 129
High: 64 or 65
3. LOS: This bit selects LDlfout pin output
High: outputs phase comparator monitoring signal(fout).
Low: outputs lock detect signal(LD)
4. FC: This bit selects phase characteristics.
5. S1 to S14: These bits select the divide ratio of the programmable reference counter (6 to 16,383).
6. C: Control bit: Set high.
7. Start data input with MSB first.

(b)

Programmable divider divide ratio
The programmable divider consists of a.19·bit shift register, a 18·bit latch, a 7·bit swallow counter, and a 11·bit programmable
counter. The serial 19·bit data format is shown below:

--_.~

Direction of data shift

Divide ratio setting bit for
swallow counter

Divide ratio setting bit for programmable counter

4-341

MB15A16
•

7·bit swallow counter divide ratio

Divide
ratio

•

ll-bit programmable counter divide ratio

S

S
4

Divide

3

S
2

S

6

S
5

S

A

S
7

1

0

0

0

0

0

0

0

1

0

0

0

0

0

0

•

•

•

•

•

•

•

127

1

1

1

1

,

(Divide ratio

S
17

S
16

S
15

S
14

S
13

S
12

S
11

S
10

S

N

S
18

9

S
8

0

5

0

0

0

0

0

0

0

0

1

0

1

1

6

0

0

0

0

0

0

1

•

•

•

•

•

.

0

•

.

1

•

.

0

•

.

0

2047

1

1

1

1

1

1

1

1

1

1

1

ratio

,

1

=0 to 127)

(Divide ratio = 5 to 2,047)

Notes: 1. Divide ratios less than 5 are prohibited for ll-bit programmable counter.
2. Sl to S7: These bits select the divide ratio of swallow counter (0 to 127).
3. S8 to S18: These bits select the divide ratio of programmable counter (5 to 2,047).
4. C: Control bit: (Set low)
5. Start data input with MSB first.

Serial data input timing
•

t1 (~l00ns): Data setup time
t2 (~ 1000ns): Data hold time
... (~l00ns): LE setup time to the rising edge of last clock

Data

~
., -18=

MSB

'

(LOS) (.1)'
Clock

S17

(FC)

t3 (~300ns): Clock pulse width
ts (~790ns): LE pulse width

--~10'
S9 . --~

,
(S8)

'(S7)

--

C: Control bit

LSB

(Sl)

(C: Control bit)

JlJJL.. Jl..ln-.. JLJL
,,

rL

, ,

--' ,

LE

,
t1~

I.

,

t3~,','

•

,

ts

'.: ...

"

-r-7-

.1: Bits enclosed in parentheses are used when the divide ratio of the programmable reference divider is selected.
Note:

4-342

•

One bit of data is shifted into the shift register on the rising edge of the clock.

MB15A16
Power saving mode (Intermittent operation control circuit)
Setting PS pin to Low. MB15A16 enters into power saving mode resultatly current sonsumption can be limited to 100llA (typ.).
Setting PS pin to High. power saving mode is released so that the device works normally.
In addition. the intermittent operation control circuit is included which helps smooth start up from stand by mode. The power
consumption can be reduced by the intermittent operation that powering down or waking up parts of the PLL circuitry. If a PLL is
powered up uncontrolled. the resulting phase comparator output signal is unpredictable due to an undefined phase relation between referePtce frequency (f,) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop.
To prevent this. the intermittent operation control circuit enforces a limited error signal output of the phase detector during power
uP. thus keeping the loop locked.
PS pin must be set ·C at Power-ON.

Relation between the Fe input and phase characteristics
The Fe bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level (Do) and the
phase comparator output (R. P) are reversed according to the Fe bit. Also. the monitor pin (fOUT) output is controlled by the Fe bit.
The relationship between the Fe bit and each of Do. R. and P is shown below:

FC -High

II

FC= Low
P

fout

H

Z(*1)

(fp)

H

L

L

(fp)

Z(*1)

L

Z(*1)

(fp)

Do

R

P

fout

Do

R

fr > fp

H

L

L

(fr)

L

fr < fp

L

H

Z(*1)

(fr)

fr=fp

Z(*1)

L

Z(*1)

(fr)

*1: High impedance
When designing a synthesizer. the Fe pin setting depends on the veo and LPF characteristics.

"
*: When the LPF and veo characteristics are
similar to ? set Fe bit high.
*: When the veo characteristics are similar to
1. set Fe low.

veo
output
frequency

""

./?

""
./

./

./

./

./

./

" >(

./

./

./

./

"""

./

""

"

LPF input voltage _

4·343

MB15A16
Phase comparator output waveforms

fr

fp
I

-::~

--~~I

LD

[FC

-::t;.

__________~I

="H" 1
4>P

4>R

u
I
~____~__~~n~__~____~__~_
-.Jr---.--if· .... lr . z

Do

.-J...... ~...... -Jr" ... -.~ _...

[FC = "L"]

I

4>P

n

4>R

Do

-.J .....

r

·li

L.... lr . z

U
I

.JF-..... ~....... Jr·······~· _..

Notes: 1. Phase difference detection range: -21t to +21t
2. LD output becomes low when phase is twu or more. LD output becomes high when phase error is twL or
less and continues to be so for three cysles or more.
3. twu and twL depend on OSCin input frequency.
twu s Slfosc (e. g. twu ~ 625ns, foscin = 12.8 MHz)
twt.~ 16lfosc (e. g. twL ~ 1250ns, foscin = 12.8 MHz)

4-344

MB15A16

RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol

Min

Value
Typ

Max

Unit

Vee

2.7

3.0

3.6

V

Vp

Vee

-

5.0

V

VI

GND

Vee

V

TA

-40

-

+85

°C

Remark

Supply voltage

nputvoltage
Operating temperature

Notes: To protect against damage by electrostatic discharge, note the following handling precautions:

-

Store and transport devices in conductive containers.

-

Use properly grounded workstations, tools, and equipment.

-

Tum off power before inserting or removing this device into or from a socket.

-

Protect leads with conductive sheet, when transporting a board mounted device.

III

4-345

MB15A16

ELECTRICAL CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

Supply current
(Power saving current)

Ite
( PS)

Min

Value
Typ

Max

Unit

-

7
(0.1)

-

mA

300

-

1200

MHz

With fiN =1.2 GHz, OSCIN =
12 MHz, Vee = 3.0 V. In
locked state.

AC coupling with a 1000pF
capacitor connected.

fiN

fiN

OSCIN

fose

-

12

23

MHz

fiN

VI IN

-10

6

dBm

OSCIN

Vose

0.5

-

Vp-p

Vee x 0.3

V

1.0

~

-

~

100

~

-

V

0.4

V

Vee = 3V, IOL = 1.0mA

Operating frequency

son (refer to the test circuit.)

Low-level output voltage

R,P. LD

VOL

-

-

High-impedance
Cut off current

Do,,P

IOFF

-

-

0.3

~

Vp = Vce to 3.6V
VOOP = GND to 6V

R,LD

IOH

-1.0

-

mA

Vee = 3V

R,P, LD

IOL

-

-

1.0

mA

Vec = 3V

-5

mA

Vee=3V,

Vp=5.0V,

10

mA

Vcc = 3V,

Vp=5.0V,

Input sensitivity

High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input current

Data, Clock,
LE,PS
Data, Clock,
LE,PS
OSCIN

High-level output voltage R, LD

VIH

Vee x 0.7

VIL
IIH

-

IlL

-1.0

lose

-100

VOH

2.1

Output current
VOOH=4.0V
VOOL=1.0V

4-346

Condition

Do

IOOH

-15

IDOL

6

V

Vec

=3 V, IOH = -1.0mA

MB15A16

TEST CIRCUIT
(FOR MEASURING INPUT SENSITIVITY fin/OSCin)
Vee Vp

P.G~~OOOP
500

l 0 0 r : = 0 P p.G

,........--.L.___
876

5

4

Jo.-----.l......,

3

2

50 0

1

III

9 10 11 12 13 14 15 16

' - - - - - - - ¢ Frequency counter

4-347

MB15A16

APPLICATION EXAMPLE

Vpx (6V)

10k
12k
To a lock detect.

12k

,-----------0 ] =~":.troll.r
PS

cl>R
16

12

15

LE

Clock

11

10

9

6

7

8

MB15A16

2
OSCIN OSCoUT

Vpx
C1, C2
cl>P
cl>R

4-348

4

3
Vp

5

Vee

Maximum 6 V
Depend on the crystal parameters
N-ch open drain output
C-MOS output

Do

00

DS04-21323-2aE

~~~~~~DATA~SHE~ET====--FUJITSU
MB1516A ASSP
1.1GHz High-Speed Tuning PLL Frequency Synthesizer

DESCRIPTION
The Fujitsu MB1516A is a serial input phase-locked loop (PLL) frequency synthesizer with
a pulse-swallow function. MB1516A achieves the low noise performance as well as the
high-speed lock-up which is required for digital mobile communications.
The MB1516A can operate from a single +3 V supply. Fujitsu's advanced technology
achieves an Icc of 6.5 mA (typical).

III

FUNCTION
• High operating frequency
• Pulse-swallow function
•
•
•
•

•
•
•
•

: fiN =1.1 GHz (PIN =-10 dBm)
: High-speed dual-modulus prescaler with selectable
64/65 and 128/129 divide ratios
Low supply current
: Icc =6.5 mA typo at 3 V
Power saving funtion
: Ips =100 ~ typo
Serial input, 18-bit programmable divider consisting of:
Binary 7-bit swallow counter
: 0 to 127
Binary 11-bit programmable counter: 5 to 2,047
Serial input 16-bit programmable reference divider consisting of:
Binary 14-bit programmable reference counter: 6 to 16,383
1-bit switch counter sets prescaler divide ratio
1-bit power saving function control
On-chip high performance charge pump circuit and phase comparator, achieving
high-speed lock-up and low phase noise
Two types of phase comparator outputs selectable
On-chip charge pump output
Output for an external charge pump
Wide operating temperature range: -40 to +85°C
Plastic 16-pin SSOP (shrink small outline) package (Suffix: -PFV)

...

I

Parameter

.:

.::

.:.

SymbOl

><» ..>... ::
:····.··.:·.···.i'~~···~L>L>

•.. .•.••• . •.. ..;,;{;>/}

L

crr:z

Vcc

-0.5 to +5.0

V

Vp

Vcc to 5.5

V

Output voltage

Vo

-0.5 to Vcc +0.5

V

Open drain voltage

VOOP

-0.5 to 6.0

V

Output current

10

±10

mA

Supply voltage

(TOP VIEW)
OSCIN
OSCOUT
Vp

••••••••• i
~,.

••:...

:":s

cI>R
cI>P
fOUT

Vce

NC

Do

FC

GND

ABSOLUTE MAXIMUM RATINGS (See NOTE)

I·:

PIN ASSIGNMENT

LE

LD

Data

fIN

Clock

cI>P, fout

Storage temperature
Tstg
-55 to +125
°C
NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

4·349

MB1516A

BLOCK DIAGRAM

r-------,

I
I

Programmable
reference divider
Binary 14-bit
reference counter

I
I
fp

LE
fp

lIUrOIOIL_.
I
I
I

1-+----+-1-'
DATA

19-bit shift register
19-bit shift register

I
I
I
I

nmmmrmrl

r----------,
LE

I

111 -bit latch I

I
sw

Prescaler

64/65,

I

.. _--------j

18-bit latch

7-bit latch

I

I

ITnTn1ftlTnTl

r----------,
I
I

I
I
I
.-_.L-._-, I

Programmable divider

r--'---..,

128/129
fp

4-350

MB1516A

PIN DESCRIPTION
Pin No. Pin name

110
I

Description
Programmable reference divider input
Oscillator input
Connection for external crystal or TCXO.

1

OSC 'N

2

OSCOUT

0

Oscillator output
Connection for external crystal.

3

Vp
Vee

-

Power supply input for charge pump

4
5

Do

0

Charge pump output
Phase of charge pump can be reversed based on FC input.

6

GND

-

Ground

7

LD

0

Lock detector output
The output level is usually high. Only when there is a phase error between fr and fp,
LD becomes low for the period corresponding to the error.

S

f,N

I

Prescaler input
Connection with an external VCO should be done AC coupled.

9

Clock

I

Clock input for 19-bit shift register
Data is shifted into the shift register on the rising edge of the clock.

10

Data

I

Serial data input using binary code
The last bit of the data is a control bit.
When the control bit is high, data is transmitted to the 16-bit latch.
When it is low, data is transmitted to the 18-bit latch.

11

LE

I

Load enable signal input (with internal pull up resistor)
When LE is high. the data of the shift register are transferred to a latch. depending on the
control bit in the serial data.

12

FC

I

Phase switch input for phase comparator (with internal pull-up resistor)
When FC is low, the characteristics of the charge pump and phase comparator are reversed
The FC input signal is also used to control the fOUT pin (test pin) output (fA or fp).

13

NC

-

No connection

14

fOUT

0

Monitor pin of phase comparator
When FC is high. fOUToutputs programmable reference divider output(fr). When FC is low, tOUT
outputs programmable divider output(fp).

15

cl>P

0

Phase comparator output for an external charge pump
Phase of the output is reversed depending on FC input.
ct>P pin is a N-ch open drain output.

16

cl>R

0

Phase comparator output for an external charge pump
Phase of the output is reversed depending on FC input.
ct>R pin is a C-MOS output.

Power supply

4·351

MB1516A

FUNCTION DESCRIPTIONS
Pulse swallow function
The divide ratio can be calculated using the following equation:

fveo

z

[(M x N) + A] x fosc + R (A < N)

fveo
N
A
fosc
R
M

:
:
:
:
:
:

Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
Preset divide ratio of binary 7-bit swallow counter (0::; A::; 127)
Output frequency of the reference frequency oscillator
Preset divide ratio of binary 14-bit programmable reference counter (6 to 16,383)
Preset divide ratio of modules prescaler (64 or 128)

Serial data Input
Serial data is processed using the Data, Clock, and lE pins. Serial data controls the 16-bit programmable reference divider and 18-bit
programmable divider separately.
Binary serial data is entered via the Data pin.
One bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable pin is high or open, stored
data is latched depending on the control data as follows:
Control data

(a)

Destination of serial data

H

16 bit latch

l

18 bit latch

Programmable reference divider ratio
The programmable reference divider consists of a 16-bit latch and a 14-bit reference counter. The serial 17·bit data format is
shown below:

--~.~ Direction of data shift

Divide ratio setting bit for programmable reference counter
Power saving control bit

4-352

MB1516A
14-bit programmable reference counter divide ratio

Divide ratio

5

5

5

5

5

5

11

10

9

6

4

5
3

5

12

5
5

5

13

5
7

5

14

5
8

5

R

2

1

6

0

0

0

0

0

0

0

0

0

0

0

1

1

0

7

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

.
16383

. . . . . . . . . . . . . .
(Divide ratio'"' 6 to 16,383)

Notes:

1. Divide ratios less than 6 are prohibited.
2. SW :This bit selects the divide ratio of the prescaler.

3.
4.
5.

6.
(b)

Low: 128 or 129
High: 64 or 65
Sl to S14: These bits select the divide ratio of the programmable reference counter (6 to 16,383).
C: Control bit: Set high.
PS: This bit controls stand by mode.
High: Nomal mode
Low: Stand by mode
Start data input with MSB first.

Programmable divider divide ratio
The programmable divider consists of a 19-bit shift register, a 18-bit latch, a 7 -bit swallow counter, and a ll-bit programmable
counter. The serial 19-bit data format is shown below:

-----..~ Direction of data shift

Divide ratio setting bit for
swallow counter

Divide ratio setting bit for programmable counter

4-353

MB1516A
•

7-bi! swallow counter divide ratio

Divide
ratio

11-bit programmable counter divide ratio

5
6

5
3

5
2

5
18

5
17

5
16

5
15

14

5
13

5
12

5
11

5

1

Divide
ratio
N

5

5

5
4

5

A

5
7

10

9

5
8

0

0

0

0

0

0

0

0

5

0

0

0

0

0

0

0

0

1

0

1

1

0

0

0

0

0

0

1

6

0

0

0

0

0

0

0

0

1

1

0

1

1

. .
127

1

5

•

.....

1

1

1

1

1

5

. ........

1

2047

1

1

1

1

1

1

(Divide ratio .. 0 to 127)

1

1

(Divide ratio

..

•
1
so

5 to 2,047)

Notes: 1. Divide ratios less than 5 are prohibited for 11-bit programmable counter.
2. 51 to 57: These bits select the divide ratio of swallow counter (0 to 127).
3. 58 to 518: These bits select Ihe divide ratio of programmable counter (5 to 2,047).
4. C: Control bit: (5et low)
5. 5tart dala input with M5B first.

Serial data input timing

Data

X= ~ ~=X__

~_ _ _ _ _ _

(L_S_B_)_ _ _ _ __

Clock

, ,

LE

"
n
_,J..:_:__-,-_I l -

, ,,

tl~

,

,
,

Is .. ,

,

.. :

15 ~
-I"~::---'''.''''
13
I
I
,
I

,

:,..

,.

12

Notes: One bil of data is shifled into the shift registor on the rising edge of the clock.

4-354

I

,•

--r--;...,

t6

-1...: ; - . - - - - , . . . . . . . .

14

MB1516A
Power saving mode (Intermittent operation control circuit)
Setting PS bit to Low. MB1516A enters into power saving mode resultatly current sonsumption can be limited to 100~A (typ.).
Setting PS bit to High. power saving mode is released so that the device works normally.
In addition. the intermittent operation control circuit is included which helps smooth start up from stand by mode. The power
consumption can be reduced by the intermittent operation that powering down or waking up parts of the PLL circuitry. " a PLL is
powered up uncontrolled. the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (fR) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop.
To prevent this. the intermittent operation conttol circuit enforces a limited error signal output of the phase detector during power
uP. thus keeping the loop locked.

Relation between the Fe input and phase characteristics
The Fe pin changes the phase characteristics of the phase comparator. Both the internal charge pump output level (Do) and the
phase comparator output (R. P) are reversed depending on the Fe pin input level. Also. the monitor pin (fOUT ) output is controlled
by the Fe pin. The relationship between the Fe input level and each of Do. R, and P is shown below:
FC = High or open
Do

R

P

fR> tp

H

L

fR R

P

fOUT

L

(tr)

L

H

Z(*1)

(fp)

H

2(*')

(fr)

H

L

L

(fp)

L

2(*')

(fr)

2(*')

L

Z(*1)

(fp)

*1: High impedance
When designing a synthesizer, the Fe pin setting depends on the vee and LPF characteristics.

*: When the LPF and vee characteristics are
similar toC). set Fe high or open.

*: When the vee characteristics are similar to

vee
output
frequency

0, set Fe low.

LPF input voltage

_

4-355

MB1516A
Phase comparator output waveforms

fr

fp

-..-

-..-

u

I

,

I

•

twu

LD

I

tWL

--~I~----------~I

[FC = "H"]
Ci)P

-'---~-----L-----,nL-----J..----L-----'-_
--J -----_l}H-----11'-

Do

r

z

.--J-L------~- ------Jr-------~ ----

[FC = "L"]
Ci)P

Ci)R

Do

Notes:

4-356

n
--Jr-------J-L ----1r- z

U
I

.-Jr -----~-

J -------~ ----

r

1. Phase difference detection range: -27t to +27t
2. LD output becomes low when phase is twu or more. LD output becomes high when phase error is tWL or
less and continues to be so for three cysles or more.
3. twu and tWL depend on aSCin input frequency.
twu ~ 8/fosc (e. g. twu ~ 625ns, foscin = 12.8 MHz)
IWLS 16/fosc (e. g. twL$ 1250ns, foscin = 12.8 MHz)

MB1516A

RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol

Value

Unit

Min

Typ

Max

Vee

2.7

3.0

3.6

V

Vp

Vcc

-

5.0

V

Input voltage

VI

GND

-

Vee

V

Operating temperature

Ta

-40

-

+85

·C

Supply voltage

Remark

Notes: To protect against damage by electrostatic discharge, note the following handling precautions:
-

Store and transport devices in conductive containers.

-

Use properly grounded workstations, tools, and equipment.

-

Turn off power before inserting or removing this device into or from a socket.

-

Protect leads with conductive sheet, when transporting a board mounted device.

4-357

MB1516A

ELECTRICAL CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)

. ,.,<"
.,.'.,:.:,."

,.,..., . . '. '.'. ". . . ·~i""" '·',/\\ii\

,.,.

",,'. ".,'•....,". ',.'. . ',', ".'.'»'. '.,'.'•.• •". . .'. .,. •,.',..•"•.'.) 1\'<

'.',,'>/\.
:,'::',

.,

""".,.,.",.",.

" ..".,.. ·'·'/i<·"'.::
i<
"." "..'. ,.", . ,<'".,.,,'
,,<.
,<
""

1",. / , .

'.,'.",:.:...':.1.".,.,

'·'.'IYI1<,·,.

Icc

-

6.5

-

rnA

With fiN = 1.1 GHz, OSCIN
= 12 MHz, Vee = 3.0 V.
In locked state.

fiN

300

-

1100

MHz

AC coupling. The minimum
operating frequency is measured with a 1OOOpF capacitor connected.

OSCIN

fosc

-

12

23

MHz

fiN

PflN

-10

-

6

dBm

Vose

0.5

-

Vp-p

VIH

Vee xO .7

-

-

V

VIL

-

-

Vee xO.3

V

IIH

-

-

1.0

~

-1.0

~

±50

-

~

-60

-

~

Supply current

fiN
Operating frequency

Input sensitivity
OSCIN
High-level input voltage
Low-level input voltage

Except fiN and
OSCIN

High-level input current
Data, Clock

OSCIN

lose

FC, LE

ILE

-

VOH

2.1

-

-

V

Vce=3V,loH=-1.0mA

VOL

-

-

0.4

V

Vcc = 3V, 10L = 1.0mA

10FF

-

-

1.1

~

Vec=3.6V
Vp=5V

10H

-1.0

-

rnA

Vcc=3V

10L

-

-

1.0

mA

Vcc=3V

Low-level input current

IlL

Input current

High-level output voltage

4-358

50n

Low-level output voltage

Except Do and
OSCOUT

High-impedance
Cut off current

Do, fout, Cl>P

Output current

Except Do and
OSCOUT

MB1516A

TEST CIRCUIT
(FOR MEASURING INPUT SENSITIVITY fin/OSCin)
Vee

0.1

p. G

J.L

= Vp .. 3V
0.1

J.L

~oo,...p...J.-_-,--r----ll..-...l_r_..L-...,'0~
50n~

8 7 6 5 4 3 2 1

p. G

~ 50n

9 10 11 12 13 14 15 16

2kn
~---+--¢:J

L..-_ _ _ _--IL._ _ _---<;;=I

Frequency counter

Select fout monitor output

4-359

MB1516A

TYPICAL CHARACTERISTIC CURVES

Charge pump current vs. Do voltage

Charge pump current vs. Do voltage

Vee =3.0V

Vee =3.0V

5

5

1\

4

~
J:

o
>

4

\

vp =5V

~

\

3

\

~

\

1\

2

Vp =3V

o

-5

,I

2

1\

\
\
\

3

1\

-10

1

-15

-20

o

-25

I--

-

5

f--'
10

15

20

25

IOL(mA)

IOH(mA)

Fin Input sensitivity vs. Input frequency
[dBm]
+10r----,----~-----r----,---~~~~r---~----~----,

+5
+0
-5

E
co

:s.z
cL

-10
-15
-20
-25
-30
-35
400
Vee = 2.7 3 3.6
MARK=x 0 0

4-360

600

800

1000

1200

Fin [MHz]

1400

1600

1800

2000

MB1516A

TYPICAL CHARACTERISTIC CURVES (Continued)
Prescaler Input
Impedance Characteristics

S11

4:

10.102

n

-37.453

n

3.8631

pF

1100 MHz
14.539 n
-125.61 n
500 MHz
2: 9.6484 n
-69.262 n
800 MHz
3: 9.9023 n
-46.156 n
1 GHz
1:

MB1516A fiN [MHz]

START

Crystal Input
Impedance Characteristics

S11

-1.8371

n

3.4653

pF

25 MHz
1:

1.425
-3.5698
10
2: 1.0444
-2.637
15
3: 800.75
-2.2129
20

MB1516A OSCIN [MHz]

START

kn
kO
MHz

kn
kn
MHz

kO
kO
MHz

STOP 100 MHz

4·361

MB1516A

APPLICATION EXAMPLE

Vpx (6V)

12 k
12 k
] From
controller

P

R
15

16

LE

FC
14

12

13

Data

Clock

11

10

9

6

7

8

47k

MB1516A

2
OSCIN

D

OSCOUT

4

3

5

Vp

Vce

3V

3V

Do

LD
1000 P

L . . - - - - - o Lock det.

Maximum 6 V
Depend on the crystal parameters
With internal pull-up resistor
N-ch open drain output
C-MOS output

4·362

47 k

MB1516A

REFERENCE INFORMATION
Typical plots measured
with the test circuit shown
on the right of this description are shown below.
Each plot shows lock up
time, phase noise with
various span.

Test Circuit
•
•
•
•
•

OSCin

Do
fin

'vco= 825 MHz
K v= 10 MHzlv
, r= 300 KHz
, osc= 19.2 MHz
LPF:

>B+>I
15k

1.5k

Spectrum

I

Analyzer

330 P

III

PLL Phase Noise

PLL Lock Up Time
520.02811

4700p

IO.0471l

~

10dBI

I :

REF

100dBm

An10dB

10.00150
MHz

RBW
100Hz

500
Hzldiv

VBW
10Hz

.• IM

.Jj

.1 ,,.,
~I\

1.11." •.

~~

, I'!"W ~

9.999000
MHz
10.1699~

1.9904199 ms

10dBI

REF

100 dBm

CENTER 825 MHz

SPAN 20 kHz

PLL Reference Leakage

PLL Phase Noise
An 10 dB
10dBI

REF

100 dBm

An 10 dB

11\

I\
J 1
/ \

RBW
30 Hz
VBW
10Hz

P

I.~LJ
'V\. WI r'I

",

SPAN 2.0 kHz

RBW
10kHz

llt\'1'..

I

IWJ'
,

IA J

~

." VA

CENTER 825 MHz

\
I \
I \

VBW
30Hz

~
SPAN 1.0 MHz

~
CENTER 825 MHz

4-363

MB1516A

PACKAGE AND DIMENSION
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P·M05)

\~ ~~1~;)~ ~
J
U

INDEX

I

.049~:gg~
---1--+---+----- (MOUNTING HEIGHT)
(1.25~:~)

1

I

I

-l

.213(S.40) NOM

*.173±.OO4
(4.4o±O.10)

~~~~
47--r-fool._
_._02_S6-,±,-.0_0_
(O.S5±O.12)

)

.252±.Ooa
(6.4o±O.20)

"A"

--~

-

----.'

.009~:gg~

(0.22~:6~)
Details of "A" part

.004±.OO4

~

(STAND OFF

:O'IO±O"0)

.179(4.55)
REF

.

00tol00

*:This dimension does not include resin prolruction.

©1991 FUJITSU LIMITED F16013S-2C

4-364

.

=t

HEIGHT)

.02o±.OO8
(0.So±O.20)

Dimensions in
inches (millimeters)

~

DS04-21325-1aE

~~~~~~~~~SHE~£T~~ruJITSU
MB1517A ASSP
2.0 GHz High-Speed Tuning PLL Frequency Synthesizer

The Fujitsu MB 1517A is a serial input phase-locked loop (Pll) frequency synthesizer with
a pulse-swallow function. MB1517A achieves the low noise performance as well as the
high-speed lock-up which is required for digital mobile communications.
The MB1517A can operate from a Single +3 V supply. Fujitsu's advanced technology
achieves an Icc of 12 mA (typical) as well as 100 J.IA (typical) at power down mode.

Plastic SSOP, 16 pin

FEATURES
• High operating frequency
• Pulse-swallow function

: fiN =2.0 GHz (P,N =-10 dBm)
: High-speed two-modulus prescaler with selectable
64/65 and 128/129 divide ratios
low supply current
: lee = 12 mA typo at 3 V
Power saving funtion
: Ips =100 J.IA typo
Serial input, 18-bit programmable divider consisting of:
Binary 7-bit swallow counter
: 0 to 127
Binary 11-bit programmable counter: 5 to 2,047
Serial input 17-bit programmable reference divider consisting of:
(FPT-16P-M05)
Binary 14-bit programmable reference counter: 6 to 16,383
1-bit switch counter sets prescaler divide ratio
1-bit power saving function control
1-bit lO/font switch
On-chip high performance charge pump circuit and phase comparator, achieving , . . . . . . - - - - - - - - - - - - - ,
high-speed lock-up and low phase noise
Two types of phase comparator outputs selectable
PIN ASSIGNMENT
On-chip charge pump output
Output for an extemal charge pump
Wide operating temperature range: -40 to +85°C
(TOP VIEW)
Plastic 16-pin SSOP (shrink small outline) package

•
•
•
•

•
•
•
•

ABSOLUTE MAXIMUM RATINGS (See NOTE)
..........

Ii

Parameters

..

......

Syrn~ol

I·.··.··
.....•

.....

..?~'I~~

...

.....

.......... :...

i<.···

OSC'N

cIIR

OSCOUT

cliP

Vp

LDlfoUT

vee

NC

Vee

-0.5 to +5.0

V

Do

FC

Vp

Vee to 5.5

V

GND

Output voltage

Vo

-0.5 to Vee +0.5

V

Xf,N

Open drain voltage

VOOP

.'

. ................

"

Supply voltage

Output current

10

Storage temperature

Tstg

NOTE:

-0.5 to 6.0

V

±10

mA

-55 to +125

°C

cliP, lO/fout

LE
Data
Clock

fiN
(FPT-16P-M05)

Pennanent device damage may occur if the above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

4-365

MB1517A

BLOCK DIAGRAM

OSC'N , } - - - - - . . ,

r-------,
Programmable
I

I
OSCOUT

,

2 ) e - - - - -....

reference divider

,

Binary 14·bit

fR

reference counter I~--t-';;';"'---------f

,

(!)R

,

(!)P

6-----l'

FC

Phase

fp

LO

fR

LE

I
I

, LD

lIGrUlillL"'-:

!fOUT

---+----.-....1

,

'I

1-+----+--.....

I

DATA

Clock

19-bit shift register
19-bit shift register

,

I',

,

lTmmmrmr

111)-----'

DO

r----------,

LE

I
I

,

18-bit latch
7·bit latch

I,

I

... _-------,

I11-bit latch I ,,

ITnTD1fllTOT(
r----------,
I

Prescaler

64165,

Programmable divider

,....-lL...--..,

,...---&----.

,,
I
,

128/129
fp

4·366

MB1517A

PIN DESCRIPTION
PinHO. Plnnarne

I/O

1

OSCIN

I

2

OSCOUT

0

Description

.

..

\

Programmable reference divider input
Oscillator input
Connection for external crystal or TCXO.
Oscillator output
Connection for external crystal.

3

Vp

4

Vee

-

5

Do

0

Charge pump output
Phase characteristics of the charge pump can be reversed by FC input.

6

GND

-

Ground

7

Xfin

I

Complementary input of the prescaler
Xfin pin should be grounded via a capacitor.

8

fiN

I

Prescaler input
Connection with an external VCO should be done AC coupled.

9

Clock

I

Clock input for 19·bit shift register
Data is shifted into the shift register on the rising edge ot the clock.

10

Data

I

Serial data input using binary code
The last bit of the data is a control bit.
When the control bit is high, data is transmitted to the 17-bit latch.
When it is low, data is transmitted to the 18-bit latch.

11

LE

I

Load enable signal input
When LE is high, the data of the shift register are transferred to a latch, according to the
control bit in the serial data.

12

FC

I

Phase switch input for phase comparator
When FC is low, the characteristics of the charge pump and phase comparator are reversed
The FC input signal is also used to control the tOUT pin (test pin) output (tA or fp).

Power supply input for the internal charge pump
Power supply

13

NC

-

No connection

14

LDJfoUT

0

Lock detector output I Phase comparator monitoring output
This is a N·ch open drain output.
Either of the outputs is selected by LOS bit of the serial data.
a)Lock detector output: at lock state .... LD ="H"
at unlock stae.. LD ="L"
b)Monitoring output: Phase comparator input signals (fp, fA) can be monitored.

15

P

0

Phase comparator output for an external charge pump
Phase of the output is reversed according to FC input.
P pin is a N·ch open drain output.

16

R

0

Phase comparator output for an external charge pump
Phase of the output is reversed depending on FC input.

III

4-367

MB1517A

FUNCTION DESCRIPTIONS
Pulse swallow function
The divide ratio can be calculated using the following equation:
fveo

=[(P x N) + A] x fo se '" R
fveo
N
A
fose
A
P

:
:
:
:
:
:

(A < N)
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
Preset divide ratio of binary 7-bit swallow counter (0 ~ A ~ 127)
Output frequency of the reference frequency oscillator
Preset divide ratio of binary 14-bit programmable reference counter (6 to 16.383)
Preset divide ratio of modules prescaler (64 or 128)

SerIal data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the 17-bit programmable reference divider and 18-bit
programmable divider separately.
Binary serial data is entered via the Data pin.
One bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable pin is high. stored data is
latched according to the control data as follows:

(a)

H

17 bit latch

L

18 bit latch

Programmable reference divider ratio
The programmable reference divider consists of a 18-bit shift register. a 17-bit latch and a 14-bit reference counter. The serial
18-bit data format is shown below:

----4.~

Direction of data shift

,..-___ Control bit(LSB)

Divide ratio setting bit for _ _ _....
the prescaler

Divide ratio setting bit for the programmable reference counter
Power saving control bit

4-368

MB1517A
•

14·bit programmable reference counter divide ratio
.

OMderatlo
.R

R
14

R
13

R
12····

R • .•. 1<"
11
10

R
9 ....

R
8

R
7

R
6

R

R
4

R
3

R
2

R

5

6

0

0

0

0

0

0

0

0

0

0

0

1

1

0

7

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

•
16383

1

. . . . . . . . . . . . . .

III

(Divide ratio =6 to 16,383)
Notes: 1. Divide ratios less than 6 are prohibited.
2. SW :This bit selects the divide ratio of the prescaler.
Low: 128 or 129
High: 64 or 65
3. R1 to R14: These bits select the divide ratio of the programmable reference counter (6 to 16,383).
4. C: Control bit: Set high.
5. PS: This bit controls power saving mode.
High : Nomal operation
Low: Power saving mode
6. LOS: This bit controls LDlfout output signal
High: fout signal (fR or fp) is selected and output via LDlfout pin.
Low: Lock detect signal is selected and output via LDlfout pin.
7. Start data input with MSB first .
(b)

Programmable divider divide ratio
The programmable divider consists of a 19·bit shift register, a 18·bit latch, a 7·bit swallow counter, and a 11·bit programmable
counter. The serial 19·bit data format is shown below:
----t.~

Direction of data shift

Divide ratio setting bit for
swallow counter

Divide ratio setting bit for programmable counter

4-369

.

MB1517A
7·bit swallow counter divide ratio

(f?

:

••
"'!':>, 4

3'

S
2

0

0

0

0

0

0

0

0

0

0

0

0

DlYide .1 5
ratio

•

A

17

0

!~>

.~

5

?~

'··Olvfde

:/.

ratIO
N

0

.

N
8

N

N

N

10

N
9

7,

6

5

N ··'N >'N:· '··N'·'
4
3 "·"2 f

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

N
11

5
6

>

N

(Divide ratio
1.
2.
3.
4.
5.

=0 to 127)

0

(Divide ratio = 5 to 2,047)

Divide ratios less than 5 are prohibited for the 11-bit programmable counter.
Sl to S7: These bits select the divide ratio of the swallow counter (0 to 127).
N1 to N11: These bits select the divide ratio of the programmable counter (5 to 2,047).
C: Control bit: (Set low)
Start data input with MSB first.

SerIal data Input timing

Data

X= ~ ~

~________

Clock

-I

t1~
I

fa .:
Note:

=><_L_S_B_ __

·• ·. rL
·
..
- ··'--•

LE

4-370

0

2047

127

~es:

11·bit programmable counter divide ratio

I

,.
I.
I

.......-~

....

ts~

·
,

I

.:

t7

...;.-.:.-

-I'~:----~:-""

One bit of data is shifted into the shift register on the rising edge of the clock.

,

,- , t3

,

a,

•

ts

MB1517A
Power saving mode (Intermittent operation control circuit)
Setting PS bit to Low, MS1 51 7A enters into power saving mode resultatly current sonsumption can be limited to 1OO~A (typ.).
Setting PS bit to High, power saving mode is released so that the device works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from power saving mode. The power
consumption can be reduced by the intermittent operation that powering down or waking up parts of the PLL circuitry. If a PLL is
powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (fR) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power
up, thus keeping the loop locked.

Relation between the Fe Input and phase characteristics
The Fe pin changes the phase characteristics of the phase comparator. Both the internal charge pump output level (Do) and the
phase comparator output (R, P) are reversed depending on the Fe pin input level. Also, the monitor pin (four) output is controlled
by the Fe pin. The relationship between the Fe input level and each of Do, R, and P is shown below:

I>

',::::'::: ,:::,

,,::

"::,':>;

::::, c:::

!!tU;

<,.c:c •••:.:,::, ':::':,cc ;::,:::::.;::.::::>

cc::,:/

/::c'

:;:;::

:'<-

11+

'>
c': c'

':,

o.?

:::::

',:,'.Cc',:"::

:::,:"

:':::,:::::::::
:'::::::

fA> fp

H

L

L

(fR)

L

H

Z(*1)

(fp)

fA < fp

L

H

Z{*1)

(fR)

H

L

L

(fp)

Z(*1)

L

Z (*1)

(fR)

Z{*1)

L

Z{*1)

(fp)

fA

=fp

III

*1: High impedance
When designing a synthesizer, the Fe pin setting depends on the vee and LPF characteristics.

*: When the LPF and vee characteristics are
similar toG). set Fe high.

*: When the vee characteristics are similar to

vee
output
frequency

®. set Fe low.

LPF input voltage

~

4-371

~

MB1517A
Phase comparator output waveforms

fr

fp

I

I

-..'
,

LD
[FC

~-twu

I

--~~I

-.''

~-twL

__________~I
I

= "H"]

u

R

[FC

I
__--'--___----'n___~________'__

= "L"]
P

R

I

U

~~n~~~I~~~~

Notes: 1. Phase difference detection range: -2n to +2n
2. LD output becomes low when phase error is twu or more. LD output becomes high when phase error is
twL or less and continues to be so for three cysles or more.
3. twu and twL depend on OSCin input frequency.
twu ~ 81fosc (e. g. twu ~ 625ns, foscin =12.8 MHz)
tWL s; 16/fosc (e. g. tWL S; 1250ns, foscin

4-372

=12.8 MHz)

MB1517A

RECOMMENDED OPERATING CONDITIONS
Parameter

...

.

..

•..•. .••..•.
.... / ...>.... ......... <......\
Vee

2.7

Vp

3.0

3.6

V

Vee

5.0

V

GND

Vee

V

Supply voltage
Input voltage
Operating temperature

Ta

+85

Notes: To protect against damage by electrostatic discharge, note the following handling precautions:
-

II

Store and transport devices in conductive containers.

-

Use properly grounded workstations, tools, and equipment.

-

Tum off power before inserting or removing this device into or from a socket.

-

Protect leads with conductive sheet, when transporting a board mounted device.

4-373

MB1517A

ELECTRICAL CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)

............ ,.•.........

.

I

.......

Supply current

Stand by current

~I~}..

II
-

12

-

rnA

With fiN = 2.0 GHz, OSCIN =
12 MHz, Vee = 3.0 V. In
locked state.

Ips

-

100

-

~

PS bit = "L"
AC coupling. The minimum
operating frequency is measured with a 1oo0pF capacitor connected.

1000

-

2000

MHz

fose

-

12

23

MHz

fiN

PflN

-10

-

6

dBm

OSCIN

Vose

0.5

-

-

Vp-p

VIH

Vee xO .7

-

-

V

VIL

-

-

Vee xO .3

V

fiN

fiN

OSCIN

Input sensitivity

Low-level input voltage

Except fiN and
OSCIN

IIH

-

-

1.0

~

Low-level input current

Data, Clock,
LE,FC

IlL

-1.0

-

-

~

Input current

OSCIN

lose

-100

+100

~

VOH

2.1

VOL

High-level input current

High-level output voltage
Low-level output voltage

Except Do ::Inri
OSCOUT

High-impedance
Cut off current

Do, LD/fout,
cl>P

Output current

Except Do ::Inn
OSCOUT

4-374

ii
..> •.•. ••.•

......\ .......... \

lee

Operating frequency

High-level input voltage

<...

50nSystem

-

V

Vee=3V,loH=-1.0mA

-

-

0.4

V

Vcc = 3V, 10L = 1.0mA

10FF

-

-

1.1

~

Vee = 3.6V, Vp = 5 .OV
Voop = GND to 6 .OV

10H

-1.0

-

-

rnA

Vcc=3V

IOL

-

-

1.0

rnA

Vcc=3V

MB1517A

TEST CIRCUIT
(for Measuring Input Sensitivity fin/OSCin)
Vee =Vp = 3V

r
r
P'G~~~P'G
0.1 "

0.1 "

1000p

500~

1000p

8 7 6 5 4 3 2 1
9 10 11 12 13 14 15 16

~ soo

III

Vee
2kO

'-----......--<:;;::1 Frequency counter
'-------'------<;;;=1

Select fout monitor output

4-375

MB1517A

TYPICAL CHARACTERISTIC CURVES

Charge pump current vs. Do voltage

Charge pump current vs. Do voltage
Vcc =3.0V

Vec =3.0V

5

5

-....

1\

4

\

3

=3v

Vp

i\
\
\

-5

-10

,I

2

:\
\

\

o

4

=5v

\
\
\

~

2

Vp

-15

-20

"-- I-5

o

-25

~

10

15

IOL(mA)

IOH(mA)

Input sensitivity vs. Input frequency
[dBm]
+10
+5

~ i'.....
~J

W.#"/d//'y/,#"~

+0
-5
-10

E
ell

~

/

aCATALOG-SPEq:

j~

~.h ~// V/~ ~h 'l"//

~

.df

-15

z
cL -20

- rm.... . .

~

-25
-30

/y
/,V

~~
"Y'

~

-35
-40
1000

1200

1400 1600 1800 2000 2200

2400 2600 2800 3000 3200

fin(MHz)

4-376

Vee = 2.7

3 3.6

MHz=

0

x

0

3400 3600

20

25

MB1517A

TYPICAL CHARACTERISTIC CURVES (Continued)

Prescaler Input Impedance
11.115 n
-45.209 n
1 GHz
2: 8.3428 n
-12.503 n
1.5 GHz
3: 9.2764 n
-7.1001 n
1.6 GHz
4: 17.173 n
5.8379 n
2 GHz
1:

fiN

[MHz) t---~-+------r------"";;~~-t

II

Crystal Input Impedance
2.1155 n
-4.4665 n
10 MHz
2: 426.63 n
-2.201 kn
25 MHz
1:

4-377

MB1517A

TYPICAL APPLICATION EXAMPLE

Vee
2kO

r----------4---o

Lock det.

From
,...----+--t--00 ] controller

r---+--f-....o

c1Jp

c1JR

15

16

LE

13

14

12

11

Data
10
47k47k 47k

MB1517A

2

OSCIN osCour

;J;

C1

3

4

Vp

Vee

3V

3V

~.1 JL

;Jfl.1 JL

X'tal

;J;. C2

Vpx
: Maximum 6 V
C1, C2 : Depend on the crystal oscillatar
c1JP, LDJfout : N-ch open drain output
c1JR
: C-MOS output

4-378

5

6

Do

7

8

MB1517A

REFERENCE INFORMATION
Typical plots measured
with the test drcuit are
shown below.
Each plot shows lock up
time, phase noise, and
reference leakage.

Test Circuit
• fvoo= 1651.2 MHz
• K v= 10 MHzIv
• f r= 300 KHz
• f osc= 19.2 MHz
• LPF:

aSCin
Do
fin

>~>
=l=
1'
I ~~_.t47OOp70Op I

Spectrum
Analyzer

a1330P

0.04711

PLL Lock Up lime

III

PLL Phase Noise

PLL lock UP Time = 584.99597 J.LS

REF 100 dBm
10dBl

ATT 10 dB

30.00150
MHz

........

RBW

•

500
Hzldiv

100Hz
VBW II
30Hz 1'" .,

..

~

29.99900
MHz
SPAN 20kHz

PLL Phase Noise
REF 10.0dBm
10dBl

CENTER 1651.20000 MHz

PLL Reference Leakage

ATT 10dB

REF 10.0 dBm
10 dBI

ATT 10 dB

1\
J 1\
RBW

I\
.I \
J IV' 'V "-, .
~r

30Hz

VBW
10Hz

I.I

L.L

RBW
10kHz

~III

.. I.

I·

SPAN 2.0 kHz

,\

VBW
.11

J

30 Hz

CENTER 1651.20 MHz

lJ

V

SPAN 1.0 MHz

\
\
~ "--.4

CENTER 1651.20 MHz

4·379

MB1517A

ORDERING INFORMATION

MB1517APFV1

4-380

Plastic· SSOP. 16-pin
(FPT-16P-M05)

MB1517A

PACKAGE DIMENSION
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M05)

r

I

· .1m...,.

~ ~ r;r·~O)~ ~
J
U

INDEX

f

I I

I

.252±.008
(6.4Oi:O.20)

(0.65±o.12)

.11.

.009~:~:
(0.22~:~)

r:
[Jpl

;- - - - - - - - -

~
~

III

'J~)~

*.173±.OO4
(4.4Oi:O.10)

~;::;;::;:;::;;r:::n:::riJ~
.0256±.0047

.049+.008

004
_+----i-_---.- (MOUNTING HEIGHT)
(1.25~:~)

I

-D~ia~s-oi

'"A= Part ------ . - -,

0
04±.OO4

(STAND OFF

~.,:: HE~

0'to.;:J! (0.501:0.20)

*:This dimension does not include resin protrudion.
©1991 FWITSU LIMITED F16013S-2C

Dimensions in
inches (millimeters)

4-381

MB1517A Test Data
February 1995

ANALOG LSI DESIGN DEPARTMENT

FU}rrsU

Digital Cordless Telephone

Block Diagram of DECT RF part
ANT

Demod

RSSI

Tx

Tx:Ch.9 1881.792MHz
Ch.5 1881.792MHz
Ch.O 1897.344MHz

Tx-amp

Data
Clock

LE

Dr-amp

Mod

4-382

February 1995

Analog LSI Dept.

FU)'ITsU

MB1517A Test Data

.PLL Serial Data Setting (fr=1.728MHz)
Frequency
Ch.9

1771.200MHz

,
+

-

15.552MHz

Rx
Ch.O

l

Prescaler(M)

1786.752MHz

PLL Divide Ratio
N-Counter(N) A-Counter(A)

64

16

1

64

16

10

64

17

64

17

126.144MHz
Ch.9

1881.792MHz

,
+

15.552MHz

Tx
Ch.O

1897.344MHz

pulse Swallow Function . fvco

= {( M x N ) + A } x fr

10

A 1897.344MHz,within
Rx9->TxO

144 J.l S
It

±

euu

50KHz

1897.344MHz -> 1771.200MHz,within ± 50KHz
TxO ->Rx9

A euta IVA

58.88

58.98
kHZ/dl U

I--il-+-+-TxO

144,us

1771.200MHz -> 1897.344MHz,within ± 50KHz

TxO->Rx9

160,u s

1897.344MHz -> 1771.200MHz,within ± 50KHz

72dBc

± 1.728MHz offset at 1771.200MHz

Hopping Time
Spurious Level
Phase Noise

• Loop filter scamatics

.VCO; Kv=87MHzIV
( muRata MQE030 - 1835 )

4-384

February 1995

within Loop Bandwidth at 1771.200MHz

78dBc/Hz

Do

~
280Q
560Q

I

VT(toVCO)

o.01uF
13000 pF
:&0.1 t1 F

Analog LSI Dept.

FUJITSU

MB1517A Test Data

APPLICATION EXAMPLE

16

14

15

13

12

LE

11
47kQ 47kQ 47kQ

MB1517A

2

5

4

6

8

7

OSCout

;J;.l.u F;J;.l.u F

v

r J; r

0

February 1995

Analog LSI Dept.

FUJITsU

MB1517A Test Data

• veo Operating Range
2200
2100
'N2000

:I:

~1900
0

0
~ 1800

'111111~WllllllilllliI1897'344MHZ
~
1771.200MHz

1700
1600
0

1

2

3

Control Voltage(volts)
February 1995

Analog LSI Dept.

4·385

MB1517A Test Data
(peN Application)
April 1995

ANALOG LSI DESIGN DEPARTMENT

MB1517A Test Data (peN)

APPLICATION EXAMPLE

LE

16

15

14

13

12

11
47kQ 47kQ 47kQ

MB1517A

2

3

4

7

6

5

8

OSCout

:J;'l.L1F :J;'l.L1F

4-386

April 1995

'--'--J\lI~""'-.I.""\II~HI/I,o..---~

I

J;

I

V0

Output

Analog LSI Dept.

rP

FUJITSU

MB1517A Test Data (PCN)

• PLL Hopping Time
1797.600MHZ -> 1872.400MHZ,within ±

500 I.J. s

Lch ->Hch
(1

1KHz

1872.400MHz -> 1797600MHz,within ± 1KHz
o.l'tkrl<: 599.9176.1 'JS

1j:-74.8888 "Hz

1j:-74.9819"Hl

" .•,sao i=F~iiim~"""'====~

t~~~~~~~~~;;~

J9.98589[=

!1Hz

kHZldlU

'ft'

2.888

IV'

--,

500 I.J. S

Hch ->Lch

rtt.r lC: S88.816ft us

k.Hz/dIU

--,

II
1--<

29.99599
t9.1359u.
d lIIk,r x: S8B.81'"

19.1Z&'us

us

1.9983766 u

a ,.It.r )(: 588.8'7'61 us

y:-?4.8888 "Hz

'1:-74.8918I'1Hz

F

F~

S8.88888

I

~

58.99888)

i
~1:7~Or---~~----------~I·

~,,,·t

"Hz/thu

!
19.1359 liS

1.9983859 ..

la.1266 us

April 1995

Analog LSI Dept.

MB1517A Test Data (PCN)

•

Spurious Level

ATTEN 10dB
RL -10 0dB..

VAVG 16
10d B/

AMKR -61 sedB
200kHz

•

Phase Noise I Loop Band Width

ATTEN 10dB
RL
10 0dB m

-

bl.'5 :l9c..

~~

w.til""'

I \
A
)1..

f

\

CENTER 1. 83500BGHz
RBW 10kHz
VBW 10kHz

April 1995

J

% ·'1o.b ~~l\a

I

CENTER 1 63S00000GHz
RBW 3013Hz
VBW 300Hz

SPAN 50. 1313kHz
SWP 2 Bs"c

Analog LSI Dept.

4-387

MB1517A Test Data (peN)

.veo Operating Range(muRata MQE030-1835)
2200
2100
'N2000

J:
!.1900
0

~~~~~___+~--~........-t-o:--~---+_r1872.400MHz

~ 1800

-+------------~~-----""'""+-------""f---L1797.600MHz

CJ

1700
1600
1

0

2

3

Control Voltage(volts)
Analog LSI Dept.

April 1995

FUJITSU

MB1517A Test Data (PCN)

•

PLL Serial Data Setting (fr=200kHz)
Frequency

Prescaler(M)

Lo ch 1797.600MHz

t

37.4MHz

RxlTx

•t

Mi ch 1835.000MHz

37.4MHz

•

Hi ch 1872.400MHz

pulse Swallow Functjon . Nco

4-388

April 1995

l
J

74.8MHz

= {( M x N ) + A } x fr

PLL Divide Ratio
N-Counter(N) A-Counter(A)

64

140

28

64

143

23

64

146

18

AHch

500p S

1797.600MHz·> 1872.400MHz,within

±

1KHz

Hch ·>Lch

500p s

1872.400MHz·> 1797.600MHz,within

±

1KHz

Hopping Time
Spurious Level
Phase Noise

• Loop filter scamatics

.veo; Kv=87MHzIV

±200kHz offset at 1835.000MHz

61dBc
70dBc/Hz

Do

within Loop Bandwidth at 1835.000MHz

r

~
910Q
15kQ

T

3000pF
J;0.03 P F

~

VT(toVCO)

400pF

( muRata MQE030 - 1835 )

April 1995

Analog LSI Dept.

4-389

4-390

~

DS04-21311-2aE

~~~~~~~~~s~~ET~~F~ITSU
MB1518
Serial Input PLL Frequency Synthesizer With
On-Chip 2.SGHz Prescaler
The Fujitsu MB 1518 with an on chip 2.5 GHz dual modulus prescaler is a serial input PLL (Phase
Locked Loop) frequency synthesizer with pulse swallow function. It is well suited for BS tuner,
CATV system applications.
It operates supply voltage of 5.0V typo and dissipates 16mA typo of current realized through the
use of Fujitsu's unique U-ESBIC Bi-CMOS technology.

•

Power supply voltage: VCC = 4.5 to 5.5V

•

High operating frequency: fin =2.5GHz (Pin =-4dBm)

•

2.5GHz dual modulus prescaler: P =5121528

•

Low power supply current: Icc =16mA typo

•

Programmable reference divider: R =512

•

Programmable divider conSisting of:
Binary 5-bit swallow counter (A = 0 to 31)
Binary 9-bit programmable counter (N =32 to 511)

•

Wide operating temperature: Ta =-40 to +85°C

•

Plastic 16-pin flat package (Suffix: -PF)

PLASTIC PACKAGE
FPT-16P-M06

PIN ASSIGNMENT
LE

ABSOLUTE MAXIMUM RATINGS (see NOTE)

Data

fOUT

Clock

VCC2

VCCl

fiN

OSCIN
Power Supply Voltage

Vcc

--0.5 to 7.0

V

Output Voltage

Vo

0.5 to Vee +0.5

V

Output Current

10

±10

mA

TSTG

-55 to +125

°C

Storage Temperature
NOTE:

Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

LD

GND2

OSCOUT

liN

GND1

FC

001

002

This device contains circuitry to protect the inputs against
damage due to high static voltagas or electric fields.
However, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum
rated voltages to this high impedance circuit.

Copyright© 1994 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS, INC.

4-391

MB1518

BLOCK DIAGRAM
LD

GND2

~

fiN

FC

D02

11

10

9

fOUT.--------~

'-----f

Monitor Frequency
Selector

Reference Counter
(R=512)

Crystal
Oscillator

(0
LE

4-392

0

Data

0

Clock

~

VCCI

OSCIN

OSCOUT

r
GND1

8
001

MB1518

PIN DESCRIPTIONS
Pin No.

Pin Name

1/0

Descriptions

1

LE

I

Load enable input pin
This pin involves a Schmitt trigger circuit. When this pin is high. the data stored in the shift register is
transferred into the latch.

2

Data

I

Serial data of binary code input pin
This pin involves a Schmitt trigger circuit.

3

Clock

I

Clock input pin of the 14-bit shift register
This pin involves a schmitt trigger circuit. On the rising edge of the clock. one bit ot the data shifts into
the shift register.

4

VCCl

-

PLL power supply voltage input pin

5

OSCIN
OSCOUT

I

6

0

Oscillator input pin
Oscillator output pin
A crystal is connected between the OSCIN pin and the OSCOUT pin.

7

GND1

8
9

DOl
D02

0
0

Charge pump output pins
The phase characteristics can be reversed depending upon the FC pin input level.

10

FC

I

Phase select input pin of the phase detector
This pin involves an internal pull up resistor. When this pin is low. characteristics of the charge pump
and phase detector can be reversed. This input also selects tOUT pin outputlevel. either fr or fp. Please
see page 6.

11

fiN

I

Complementary input pin of fiN
Please connect to GND through a capacitor.

12

GND2

-

Prescaler ground pin

13

fiN

I

Prescaler input pin
This signal is input with an AC connection.

14

VCC2

-

Prescaler power supply voltage input pin

15

fOUT

0

Monitor pin of the phase detector input
The fOUT pin outputs either the programmable reference divider output frequency fr or programmable
divider output frequency fp. depending upon the FC pin input level.

PLL ground pin

FC Pin

16

LD

0

fOUT Output Signal

H

fr

L

fp

Phase detector output pin
Normally this pin outputs high. While the phase difference between fr and fp exists. this pin outputs low.

4·393

MB1518

FUNCTIONAL DESCRIPTIONS
DIVIDE RATIO SETTING
Divide ratio can be set using the following equation:
fveo

={(P x N) + (16 x A)} x fose

-i-

R

fveo: Output frequency of an external voltage controlled oscillator (VeO)
P:
Preset divide ratio of an internal dual modulus prescaler (512)
N:

Preset divide ratio of binary 9-bit programmable counter (32 to 511)

A:

Preset divide ratio of binary 5-bit swallow counter (0 to 31)

fosc: Reference oscillator frequency
R:

Preset divide ratio of reference counter (512)

SERIAL DATA INPUT
On the rising edge of the clock, one bit of the data shifts into the shift register.
When the load enable is high. the data stored in the shift register is transferred to the latch.
14-bit serial data format is shown below.

------I..

IT~LSi ~
/-

~ ~

1 : 1 : 1N1

1

Divide ratio of swallow
counter setting bit

Data Input Flow

~ I ~ I ~ f?B

I: 1

Divide ratio of programmable
counter setting bit

5-bit swallow counter divide ratio (A 1 to AS)
Divide Ratio

A

A

A

5

4

3

A
2

A

A
0

0

0

0

0

0

1

0

0

0

0

1

2

0

0

0

1

0

1

:

:

:

:

:

:

31

1

1

1

1

1

9-bit programmable counter divide ratio (N1 to N9)
Divide Ratio

N

N

N

N

N

N

N

N

N

9

8

7

6

5

4

3

2

1

32

0

0

0

1

0

0

0

0

0

33

0

0

0

1

0

0

0

0

1

34

0

0

0

1

0

0

0

1

0

:

:

:

:

:

:

:

1

1

1

1

1

1

1

1

1

:
511

4-394

N

MB1518
SERIAL DATA INPUT TIMING

Data

~ --:;V(L~~)

N9

- -

--A-...
---"---------,
~_JUJl_JUL_
(MSB)

,

Clock

LE

I

I

I

I

I . ,

-----"""',-.,--.. . :--.
. .'-- ::
:--;
t1'

; . t2-;

t3~

_

rL

t4-':

,
,

t5~
"

Note: On the rising edge of the clock. one bit of the data shifts into the shift register.

When LE is high. the data stored the shift register is transferred into the latch.

4-395

MB1518
PHASE DETECTOR CHARACTERISTICS
The FC pin selects the phase of the phase detector. The phase characteristics (charge pump output) can be reversed depending upon the
FC pin input level. The monitor pin (fOUT) output level is selected by the FC pin input level as well.
FC = H (or open)

fr> fp

H

fr= fp

Z

frdp

L

FC=L

fOUT

001,002

Outputs programmable
reference divider output
frequency (fr)

Z

001,002

fOUT

L
Outputs programmable
divider output
frequency (fp)

H

Note:

Z:

VCO POLARITY

High-impedance

Depending upon the VCO polarity, the FC pin should be set
accordingly.
When VCO polarity is like (1),
FC should be set high or open.
When VCO polarity is like
FC should be set low.

®,

VCOOutput
Frequency

VCO Input Voltage _

PHASE DETECTOR WAVEFORM

fr~

J

J

J

J

L

fp

u u u
(FC=H)
0 01 ,002

(FC=L)
0 01 ,002

H

4--------r---- tk -----U----~-- t 0

J

0

Z- -

_I

z- -

o

fr= fp

Phase difference detection range : -27t to +27t
Spike shape depends on the charge pump characteristics.
The spike is output to diminish the dead band.

4-396

0

-J-------- r---- + ----~-- -~- -t fr>fp

Note:

L

frdp

0

frdp

0

frdp

MB1518
TEST CIRCUIT (FOR PRESCALER INPUT SENSITIVITY)

0.1J.l

I

1000p
P.G

i

1000p
Frequency
counter

16

15

14

13

12

11

10

9

6

7

8

MB1518
2

3

4

5

[]

rr
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Power Supply Voltage

Unit

Symbol
Min

Typ

Max

Vee

4.5

5.0

5.5

V

Input Voltage

VI

GND

-

Vee

V

Operating Temperature

Ta

-40

-

+85

°C

HANDLING PRECAUTIONS
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats.
• Always

turn the power supply off before inserting or removing the device from its socket.

• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

4-397

MB1518

ELECTRICAL CHARACTERISTICS
•.. (> .•.

,\i>.·

«

·i.

Power Supply Current
fin

I\~Ii

fin

OSCIN

Low-level Input Voltage
High-level Input Current

&i""·.'.> <

Note 1

-

16.0

-

fin

Note2

10

-

2500

-

-

4

10

2300 to 2500MHz

-4

-

6

1900 to 2300MHz

-7

-

6

10 to 1900MHz

-10

-

6

0.5

-

VCCxO.7+O.4

-

-

Except fin
andOSCIN

-

-

Data.
Clock.
LE

-

1.0

-

fOSC

Pfin

IIH

-

IlL

-

-

-1.0

-

-

-

-60

-

-

±50

-

4.4

-

-

Vosc
VIH
VIL

Low-level Input Current

Input Current

"".,,

......... ,

FC

IILFC

OSCIN

Ilosc

High-level Output Voltage

VOH

001. 0 02

High-level Output Current

Vcc= 5.0V

-

-

-

0.4

10FF

-

-

-

1.1

10H

-

-1.0

-

-

10L

-

1.0

-

-

Note1: fin=2.5GHz. OSCIN=4.0MHz. Vrx;=5.0V. Input pins are grounded and output pins are open.
Note2: AC coupling. Minimum operating frequency is measured with a capacitor 1000pF.

4-398

dBm

Vpp

V

j.lA

V
VOL

Except Do
Low-level Output Current

mA

VccxO.3-0.4

Except Do
Low-level Output Voltage
High-impedance Cutoff
Current

.r0W
MHz

OSCIN

High-level Input Voltage

.-':,:i>

Icc

Operating Frequency

Input Sensitivity

I~

I~~j

j.lA

mA

MB1518

MB1518 APPLICATION CIRCUIT

VT

VCO

III

VCOOUT

5V
...

::1000p

o"f

Lock Det.

LD
16

IfOUT
15

1000p

Jr

::
fiN

VCC2
14

13

fIN

GND2
12

11

FC
10

D02

9

33v

MB1518

1

2
LE

Data

5

4

3
Clock

VCCl

5V

J

From
Controller

--

0.1 11

.~

7

6

OSCin OSCout GND1

HOIX'tal

XXX
C1

8
DOl

..
...

:~
.........
......

,."

C

2

C 1 , C 2 : depends on the crystal oscillator
FC
: with internal pull up resistor

4-399

MB1518

PACKAGE DIMENSIONS
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M06)

,

l

~~==~=.4=00~~=:g=6~g=(1=0'~15=~=0:=~~~)~~~

.089(2.25)MAX
(MOUNTING HEIGHT)
.002(O.05)MIN
(STAND OFF HEIGHT)

-+----.

1

.307±.016
(7.8o±0.40)

INDEX

d
II

.. I-

I
11==t
+-

I

I

TYP

.209±.012
(5.3o±O.30)

"S"

.018±.004 -~I'~I------'t
±o} -$- 121.005(0.13) ®
(0.45_ .10 L.:.-...l.-_~~-=---C

.02o±.008
(0.50±0.20)

.006~:gg~ (0.15~:g~)

¥

1--------'1--------,
"A"

I

Details of "A" part

I I

.0~16(0.40):
--

: :
I
II II

.008(0.20} I
.350(8.89) REF

II

.00~~X18}

:

II

Details of "S" part

I

I

!

.00~(0.15) :
-L
I

~:
.008(0.20)

.00~~~8)

I
II

I
I .027(0.68)
!I
I
.027(0.68)
I
IL _ _ _ _ _MAX
I I ____
- _MAX
_ _ _ JL
_ _ _ JI
©1991 FUJITSU LIMITED F16015S-2C

4-400

Dimensions in
inches (millimeters)

cO

September 1993
Edition 1.0

FUJITSU

DATA SHEET

MB15A19
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 600MHz PRESCALER
The FufdsU MB15A19 is a 600MHz dual serial input PLL (Phase Locked) frequency synthesizer
designed for cellular telephone and cordless telephone applications.

III

The MBl5A19 has two PLL circuits on a single chip: one for transmit and the other for reception.
Separate power supply pins are provided for the transmit and reception PLL circuits. Transmit

PLL contains a low sensitivity charge pump for ease of modulation and reception PLL contains a
high sensitivity charge pump for faster lock up time.
600 MHz dual modulus prescalers are on chip and enables a pulse swallow function.
It operates supply voltage of 3.0V typo and dissipates 11 mA typo of current realized through the
use of Fujitsu's unique U-ESBIC Bi-CMOS technology.
•

H"Jgh operating frequency: fin - 600MHz

•

Low power supply voltage: Vec - 2.7 to 5.5V

•

Low power supply current:

PLASTIC PACKAGE
FPT·20P-M01

Icc • 11 rnA typo @3V.

• Wide operating temperature: TA • -40 to 85°C
•

•

PIN ASSIGNMENT

Two charge pumps
Low sensitivity charge pump for transmit
H"lQh sensitivity charge pump for reception
Plastic 2O-pin flat package (Suffix: -PF)

ABSOLUTE MAXIMUM RATINGS (see NOTE)

OSCIN

2

OSCOUT

3

fin 1

4

Veel
Vet;

-0.5 to 7.0

Power Supply Voltage

V
Vp

Vet; to 10.0

VOUT

-0.5 to Vet; +0.5

Output Current

lOUT

±10

mA

Storage Temperature

TSTG

-55 to +125

°c

Output Voltage

NOTE:

V

Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional oporation should be restricted to the conditions as
detailed in the operational sections of this data sheet Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Copyright @,iS13byFWITSU LIMITED

Clock

GNO

5

Data
18

LE
fin2

TOP
VIEW

16

VCC2
fp

fr

6

15

LO ,

7

14

L0 2

VPl

8

13

VP2

001

9

12

002

BS,

10

11

BS2

This d...nc. contains circuitry 10 praled Ihe Inpuls against
damage due 10 high Italic volag. or elednc lields. However,

I Is advised thai normal precautions be taken 10 avoid
~icalion ol anyVOllage highat than maximum rMeeI wIIag_
to this high l~atlCe circuit.

4-401

M815A19
MB15A19 BLOCK DIAGRAM

22-b11lhll

regtaler

4-402

MB15A19

BLOCK DESCRIPTIONS
TRANSMIT/RECEPTION BLOCK
• 20-bit latch
• Programmable divider consisting of:
Binary 7-bit swallow counter (Divide ratio: 0 to 12n
Binary 11-bit programmable counter (Divide ratio: 16 to 2047)
• Phase detector with phase polarity change function
• 600MHz dual modulus prescaler (Divide ratio: 64/65)
• Charge pump

II

COMMON BLOCK
• 22-bit shift register
• Programmable divider consisting of:
Reference counter (Divide ratio: 256, 2048)
(Divide frequency. 50kHz, 6.25kHz (Crystal oscillator frequency. 12.8MHz)
• Crystal oscillator
• fp monitor output selector
• Latch selector
• Schmitt circuits
• Analog switches

4·403

MB15A19

PIN DESCRIPTIONS
"';';':";"

1

GND

-

Ground.

2
3

OSCIN
OSC-

I
0

Oscmator input pin.
Oscillator output pin.
A crystal is connected between OSCIN pin and OSCOUT pin.
Prescaler input pin of transmit section.
The connection with VCO should be AC connection.

OUT

4

fin,

I

5

VCC1

-

6

fr

0

Monitor pin for programmable reference divider output

7

LD1

0

Lock detect signal output pin of transmit section.

Power supply voltage input pin of transmit section.
When power is OFF, latched data of transmit section is cancelled.

Condition

H

Unlock

L

8

VPl

-

Power supply voltage input for charge pump and analog switch of transmit section.

9

001

0

Charge pump output pin of transmit section.
Phase characteristics of the phase detector can be reversed depending upon FC-bit setting.

10

851

0

Analog switch output pin of transmit section.
Usually this pin is high-impedance state. During SW is ON (LE • high), charse pump output is connected to this pin.

~11

852

0

Analog switch output pin of reception section.
Usually this pin is high-impedance state. During SW is ON (LE • high), charge pump output is connected to this pin.

12

002

0

Charge pump output pin of reception section.
Phase characteristics of the phase detector can be reversed depending upon FC-bit setting.

13

VP2

-

Power supply voltage input for charge pump and analog switch of reception section.

14

LD2

0

Lock detect signal output pin of reception section.
Condition

15

fp

o

LD pin output level

Lock

H

Unlock

L

Monitor pin for programmable divider output
This pin outputs divided frequency of transmit section or reception section depending upon FP bit setting.
FP bit

4-404

LD pin output level

Lock

Output

H

Transmit section (fp1)

L

Reception section (fp2)

MB15A19

PIN DESCRIPTIONS (Continued)
:::::::~t~::ij~~: Pln:N~~.
:.;.:.;.:.:"::.:"
.

":'::::;'::;>:::::::::{.::;;;;;;'.
.. :.:

..

'.;:;:;.. ::::":-:::;:'<:::;::'.:::. ...;.;.::;...;:::... :::.:;..:.; ..•;:.;';'"

:"

_.

·C.:"

:.:;:;::;;:-

. ::::.;.;;;... :.. ::.;;., .·::;·::::;:;i

";'::;":'::':'

:·::::::;:::;::'::.;:::·::r

16

Vccz

-

17

tina

I

Prescaler input pin of reception section.
The coMection with VCO should be AC conneeiton.

18

LE

I

Load enable input pin. This pin involves a schmitt trigger circuit
When this pin is high, Ihe data stored In the shift register is transferred into the latch depending on a
control data.
At this moment, charge pump output signal is output from as pin since internal anafog swith becomes
ON.

19

Data

I

Serial data input pin of 22-bit shift register. This pin involves a schmitt trigger circuit
The stored data in the shift register is transferred to either transmit section or reception section depen~
Ing upon a control data.

20

Clock

I

Power supply voltage input pin for reception section, programmable reference divider, shift register,
and crystal oSCIllater.
When power is OFF, latched data of reception section and reference counter is canceUed.

Control bit data

The destination of data

H

Latch of transmit section

L

Latch of reception section

•

Clock input pin of 22·bit shift register. This pin involves a schmitt trigger circuit
On rising edge of the clock shifts one bit of data into the shift register.

FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:

fveo - {(M x N) + A} x fose + R

(A < N)

fvco: Output frequency of external voltage controlled ocillator (VeO)
M:

Preset divide ratio of dual modulus presealer (64)

N:

Preset divide ratio of binary 11·bit programmable counter (16 to 2047)

A:

Preset divide ratio of binary 7·bit swallow counter (OS A S 127)

fose: Reference oscillator frequency
R:

Preset divide ratio of reference counter (256 or 2048)

4-405

MB15A19

FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data Is Input using three pins. Data pin. Clock pin. and LE pin. Programmable cfrvider of transmit section and programmable cflViderof recap1ion section are controUed IndividuaDy.
Serial data of binary data is input Into Data pin.
On rising edge of clock shifts one bit of serial data into the shift register. When load enable signal is high. the data stored in the shift register is
transferred to either the latch of transmit section or the latch of reception section depending upon the control bit data setting.
Control data

Destination of serial clata

H

Latch of transmit section

L

Latch of reception section

SHIFT REGISTER CONFIGURATION
Control bit

! L;B
1

2

IB

Data Flow --..
3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

22

C

R

F

F

A

A

A

A

A

A

A

N

N

N

N

N

N

N

N

N

N

N

N

E

P

C

1

2

3

4

5

6

7

1

2

3

4

5

6

7

8

9

10

11

T

F

N1 to N11
A1 toA7

FC
FP
REF
CNT

: Divide ratio of the programmable counter setting bit (16 to 2047)
: Divide ratio of the swallow counter setting bit (0 to 127)
: Phase control bit of the phase cletector
: Output of the programmable cfrvider control bit (fp 1 or fp2)
: Divide ratio of the reference counter setting bit (256 to 2048)
: Conlrol bit

SERIAL DATA INPUT TIMING

• tl • tz. ~
Dara

t.. ts ~ 1J.1.S

Nl1 - MS8

v;;;--· · ~ · -,,;;:;;V
~--- ~---~
I
I

aock

LE

C: Con'" Nt

I
I

--lliJl.JUJl.~
:'

-----~...I - ~
Itll

"
I

i;

I

,.ta-.

I

I

I

I

13~

,

I

rL
I

I

:-t.-+::
I

I

ts~
I

On rising edge of the clock shifts one bit of the data into the shift register.

4-406

21

I

MB15A19
BINARY 11-BIT PROGRAMMABLE COUNTER DATA SETIING
Divide
Ratio
(N)

N
11

N
9

N
10

N
8

N

7

N
6

N
5

N
4

N
3

N
2

N
1

16

0

0

0

0

0

0

1

0

0

0

0

17

0

0

0

0

0

0

1

0

0

0

1

2047

1

1

1

1

1

1

1

1

1

1

1

Note: Divide ratio less than 16 is prohibited.
Divide ratio (N) range. 16 to 2047

II

BINARY 7-BIT SWALLOW COUNTER DATA SETIING
A

A

A

A

7

6

5

4

0

0

0

0

1

0

0

0

127

1

1

1

1

Divide
Ratio

A
3

A

A

2

1

0

0

0

0

0

0

0

1

1

1

1

(A)

Note: Divide ratio (A) range. 0 to 127
REF : DIVIDE RATIO (R) OF THE REFERENCE COUNTER SETIING BIT
H • 256 (fr • so.o kHz)
L • 2048 (fr • 6.25 kHz)
FP

FC

: OUTPUT OF THE PROGRAMMABLE DIVIDER SETIING BIT
H • fp pin (15 pin) outputs programmable divider output frequency (fp1) of transmit section.
• L. fp pin (15 pin) outputs programmable cftvider output frequency (fp2) of reception section.
: PHASE CONTROL BIT OF THE PHASE DETECTOR
Output of charge pump is selected by FC pin.

FC.H

FC.L

fr > fp

H

L

fr.fp

Z

Z

fr fp or fr < fp, spike might not generate depending up the veo characteristics.

4-408

MB15A19

ANALOG SWITCH
ONIOF F of the analog switch is controned by the combination of the control data and lE signal. When the analog switch is ON, BS " BS2 pin output
the chatge pump output (DOl. 0Q2). When analog switch is OFF, BS pin is set to high impedance.
Control data - H
Divide ratio of transmit section is set

Control data - L
Divide ratio of reception section is set

lE.H

lE.l

LE-H

LE al

Analog switch of transmit section

ON

OFF

OFF

OFF

Analog switch of reception section

OFF

OFF

ON

OFF

III

When a analog switch is inserted between LP1 and LP2. faster lock up time is achieved to reduce lPF time constant during PLL channel switching.

----------------~ Do
CHARGE PUMP

I

SISW

(CONTROL SIGNALE) - - - - - - '

-------------------------------~

RECOMMENDED OPERATING CONDITIONS

Power Supply Voltage

HANDLING PRECAUTIONS
• This device should be transported and stored in anti-st"'!ic containers.
• This is a static-sensitive device; take proper anti-ESO precautions. Ensure that personnel and equipment are properly grounded. Cover workbencf1es with grounded conductive mars.
• Always tum the power supply off betore inserting or removing the device trom its socket
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

4-409

MB15A19

ELECTRICAL CHARACTERISTICS

a;:.ll~J!I"
.~

Power Supply Current.

IccI

Reception section Is active.

1cc2

Transmit/reception sec:tlon
are active.

-

20

Vee - 2.7 to 4.0V, soO

-8

-

0

fin

PflN
Vee • 4.0 to S.SV, soO

-4

-

2

Except fin
andOSCIN

Do
Except Do
andOSCOUT

Vpp

-

-

VL

-

-

VccXO.3-0.4

1.0

-1.0

-

±50

-

2.2

-

-

-

-

0.4

-

-

1.1

lose
VOH

Vcc· 3 •OV

VOL

IOFF

Vp • Vcc to S.OV

IOH

-1.0

lOt.

1.0

-

-

-

-1

-

Vcc· 3V

-

12

-

IOH

Vp.6V

-

-3

-

lOt.

Vee .3V

-

6

-

-

2S

-

001

Doz

RoN

.: fin. 600MHz, OSCIN • 12.8MHz, Veet • VCC2. 3.0V. The remaining input pins are grounded and output pins are open .
•• : AC coupling. Minimum operating frequency is measured when a capacitor 1OOOpF is connected.

V

J.lA

V

J.1A

-

Vp.6V

IOH

4-410

dBm

VccXO•7+O. 4

Input Current

mA

MHz

VIH

OSCIN
Except Do
andOSCour

;::~~:a·!

Vase

IlL

Notes:

11.0

12.8

LE

Analog Switch ON Resistance

-

-

Low-level Input Current

Output Current

5.5

'osc

IIH

H(gh-impedance Cutoff
Current

-

'.':'::

:':::":::.:':,

OSCIN

Data.
Cloc:k

Low-level Output Voltage

..• ,.,.',::.:

: :.:::,::

600

High-level Input Current

High-level Output Voltage

'.:'

":.:':'::':.

-

OSCIN

Low-Ievellnput Voltage

>.'

10

Input Sensitivity

High-level Input Voltage

I~

fin

fin
Operating Frequency••

\

.~·:L:

mA

0

MB15A19

TEST CIRCUIT (PRESCALER INPUT SENSITIVITY TEST)

P.G

~~,..F

1

_ _-<

>-_ _-<

III

GND

500

POGi'

MB15A19

1000pF

soO

fp

'----+---------0

Oscilloscope

IOo1~

4-411

MB15A19

APPLICATION EXAMPLE

Output

Lock Deteetor
3V

6V

MB15A19

fr

GND

Lock Detector
1000pF

Output

Note: VP1, Vpz
C1,C2
Clock, Dala, LE

x·taI

4-412

:8 V max.
:depends on the ctYstai oscn/ator.
:invo/ve the schmitt circuit
When input pins are open, please insert the pull downlup resistor individually to prevent the oscillation.
: 12.8MHz

MB15A19

PACKAGE DIMENSIONS
2D-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-20P-M01)

.089(2.25) MAX

~ .500~:::(1"1O:g:~) ~

(MOUNTING HEIGHT)

'()02(0.05) MIN
~J-,-(S_T._AND OFF HEIGHT)

l

INDEX

III

.307±.016
(7.eo±o.40)
+. 016 (6 80..0·40)
•268-.008· -0.20

.209±.012
(5.3O±O.30)

cf

I
==*
JL

~~~~~~~~~-1
.050(1.27)
TYP

•

II

.006::~~(0.15~:g~)

.018±.OO4
I

(O.45±o.10)

.0_008
(O.5O±O.20)

L-\.:......I-\0_.00_5....:...(0_.13....:...)@;;..J\

r--------,
I

Details of "A" part

I

II
.008(0.20) II
I
I
I
I
I
I
I
.020(0.50) I
I
.007(0.18) I
I
I
I
.027(0.68) I
I1.. _ _ _ _ _ _ _ _ .1I
1 + - - - - .450(11.43) REF - - -

C1991 FUJITSU LIMITED F2OO035-SC

Dimensions in
inches (millimeters)

4-413

4·414

00

DS04-21314-1E

~~~~~~~~~s~~ET~~F~ITSU
MB1519 ASSP
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER

III

DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 600MHz PRESCALER
The Fujitsu MB 1519 is a 600MHz dual serial input PLL (Phase Locked) frequency synthesizer
designed for cellular telephone and cordless telephone applications.
The MB 1519 has two PLL circuits on a single chip: one for transmit and the other for reception.
Separate power supply pins are provided for the transmit and reception PLL circuits. Transmit
PLL contains a low sensitivity charge pump for ease of modulation and reception PLL contains a
high sensitivity charge pump for faster lock up time.

PLASTIC PACKAGE
DIP-20P-M02

600 MHz dual modulus prescalers are on chip and enables a pulse swallow function.
It operates supply voltage of 3.0V typo and dissipates 11 mA typo of current realized through the
use of Fujitsu'S unique U-ESBIC Bi-CMOS technology.
•
•
•
•
•

•

High operating frequency: fin =600MHz
Low power supply voltage: Vee =2.7 to 5.5V
Low power supply current: Icc = 11 mA typ, @3V.
Wide operating temperature: TA =-40 to 85°C
Two charge pumps
Low sensitivity charge pump for transmit
High sensitivity charge pump for reception
Plastic 20-pin dual in line package (Suffix: -P)
Plastic 20-pin flat package (Suffix: -PF)

PLASTIC PACKAGE
FPT-20P-M01

PIN ASSIGNMENT
GND

ABSOLUTE MAXIMUM RATINGS see NOTE)
Rating

05CIN

Symbol

Value

Unit

Vee

-0.5 to 7.0

V

Vp

Vee to 10.0

Output Voltage

VOUT

-0.5 to Vee +0.5

V

Output Current

lOUT

±10

rnA

NOTE:

TSTG

-55 to +125

fr

°C

Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Copyright@I994byFUJITSU LlMIED

fin,
VeCl

Power Supply Voltage

Storage Temperature

OSeOUT

LD,

Data
Data

LE
fin2
VCC2
fp

L02

VPl

VP2

001

002

BS ,

B52

This device contains circu~ry to protect the inputs against
damage due to high static vo~ages or electric fields. However,
~ is advised that nonnal precautions be taken to avoid
application of any vo~age higher than maximum rated vo~ages
to this high impedance circurt.

4-415

MB1519
MB1519 BLOCK DIAGRAM

RECEP·
TION
SECTION

23-bk shill
register

4-416

MB1519

BLOCK DESCRIPTIONS
TRANSMlT/RECEPnON BLOCK
• 20-bit latch

• Programmable divider consisting of:
Binary 7-bit swallow counter (Divide ratio: 0 to 127)
Binary 11-bit programmable counter (Divide ratio: 16 to 2047)
• Phase detector with phase polarity change function
• 600MHz dual modulus prescaler (Divide ratio: 64165)

• Charge pump

COMMON BLOCK
• 23-bit shift register

• Programmable divider consisting of:
Reference counter (Divide ratio: 512.1024)
{Divide frequency. 25kHz. 12.5kHz (Crystal oscillator frequency. 12.8MHz)
• Crystal oscillator
• fp monitor output selector
• Latch selector

• Schmitt circuits
• Analog switches

4-417

MB1519

PIN DESCRIPTIONS
PIn No,;

""'·.NamI

1

GNO

2
3

ose-

OSCtN

.... (

..... ...

)10

-

..

:Dllerlpuona . ;

':"<:~;:)::.:'::.:;>:-:'"

...............

.• \ ..........................................<•.. . .

Ground.

I

Oscilator Wlput pin.
Oscilator 0UIp\J pin.
A a)'Sta1 is connected between OSC!N pin and 0SC0ur pin.

0

OUT

"

in1

I

PrescaIer if1)U pin of transmit section.
The connection with veo should be AC connection.

S

VCC1

-

Power ~y voltage if1)ut pin of transmit section.
When power is OFF, latched data of transmit section is canceled.

8

t

0

MonitOf' pin for programmable reterence divider output.

7

lO1

0

Lock detect signal output pin of transmit section.
Condition

LO pin ou\pU\ level

Lock

H

Unlock

L

8

VP1

-

Power ~y voltage if1)ut

9

001

0

Charge PUf11) output pin of transmit section.
Phase characteristics of the phase detectOf' can be reversed depending upon Fe-bit setting.

10

881

0

Analog switch output pin of transmit section.
Usually this pin is high-impedance state. During SW is ON (lE • high), charge pump output is c0nnected to this pin.

11

882

0

Analog switch output pin of reception section.
Usually this pin is high-impedance state. During SW is ON (lE • high), charge pump output is c0nnected to this pin.

12

002

0

Charge PUf11) output pin of reception section.
Phase characteristics of the phase detector can be reversed depending upon Fe-bit setting.

13

VP2

-

Power ~y voltage if1)U

14

lO2

0

Lad< detect signal 0lAput pin of reception section.
Condition

15

4-418

..

\)

0

tor charge pump and analog switch of transmit section.

tor charge pump and analog switch of reception section.

LD pin ouIput level

Lock

H

Unlock

L

Monitor pin for programmable divider OUIput.
This pin outputs divided Irequency of transmit section or reception section depending upon FP bi setting.
FPbit

Output

H

Transmit section (fp1)

L

Reception section (fp2)

MB1519

PIN DESCRIPTIONS (Continued)

.,...No. PlitNll.

......•.ltQ ..:...

............../.. .............../<

....;. . • <:.>>::<~

}<.<:>
.:..,:/
.. )

.:/

........;. . .• •.•:. • . :. <...•••..::::.;:•. :.:
..........................;.......:...........

:

16

VCC2

-

17

IiI"2

I

Prescaler i~ pin of reception section.
The connection with veo should be AC conneciton.

18

LE

I

Load enable i'lJlA pin. This pin involves a schmitt trigger ci"cuil.
When this pin is high, the data stored in the shift register is transferred into the latch depending on a
control data.
At this moment, charge pump 0IApUt signal is outpIA ..om as pin since internal analog swilh becomes
ON.

19

Data

I

Serial data i'lJut pin oI23-bit shift register. This pin involves a sctvnitt trigger circuit.
The stored data in the shift register is transferred to either transmit section or reception section
depending upon a control data

Power SUfJPIy voltage i~ pin for reception section, pro(T8mmable reference divider, shift register,
and crystal oscillator.
When power is OFF, latched data of reception section and reference counter is cancelled.

Control bit data

20

Clock

I

The destination of data

H

Latch of transmit section

L

Latch of reception section

Clock input pin of 23-bit shift register. This pin involves a schmitt trigger ci"cuit.
On rising edge 01 the clock shifts one bit of data into the shift register.

FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
fveo • {(M x N) + AI x fose ~ R (A < N)
fveo: Output frequency of external voltage controlled ocillator (VeO)
M:

Preset divide ratio of dual modulus prescaler (64)

N:

Preset divide ratio of binary 11 -bit programmable counter (16 to 2047)

A:

Preset divide ratio of binary 7-bit awallow counter (~ A s 127)

fosc:Reference oscillator frequency
R:

Preset divide ratio of reference counter (51 2 or 1024)

4-419

MB1519

FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serialdata is if1>ut USing ltYee pins. Data pin. Clock pin. and LE pin. Prcqammable divider of transmit section and programmable divider of reception section are conlroled individually.
Serial data of binary data is input into Data pin.
On rising edge of clod< shifts one bit of serial data into the shift reQister. When kMd enable signal is high. the data stored in the shift register is
nnsferred to either the latch of transmit section or the latch of reception section depending upon the control bit data setting.

Control data

Destination of serial data

H

Latch of transmit section

L

Latch of reception section

SHIFT REGISTER CONFIGURATION

!,

,

Conrolbit

Dataflow ......

LSB

1

2

3

4

5

6

7

8

9

10

11

MSB

12

13

14

15

16

17

18

19

20

21

23

C

R

F

0

F

A

A

A

A

A

A

A

N

N

N

N

N

N

N

N

N

N

N

N

E

P

M

C

1

2

3

4

5

6

7

1

2

3

4

5

6

7

8

9

10

11

T

F

N1 to N11
A1 to A7

Y
: Divide ratio of the programmable counter setting bit (16 to 2047)
: Divide ratio of the swaHow counler setting bit (0 to 127)

FP
REF

: Phase control bit of the phase detector
: Dummy bit fp

H

L

fr-fp

Z

Z

fr

,.,

,

>"',,...... , .,/,

"'''''','''::>::>'

:",,'

..... ..

·:·'··::·:::·.:,·::.,:,: • ·::.:::,7:·::··:·• ·.·(.

,:::::7 -:'":':77:i,:/:}: I ' : : :

Vee

2.7

5.5

V

Vp

Vcc

8.0

v

Input Voltage

GND

Vee

V

Operating Temperatu-e

-40

Power SLPPIy Voftage

3.0

VCC1· VCC2

HANDLING PRECAUTIONS
• This device should be transported and stored in anl~static containers.
• This is a static-sensitive device; take proper ant~ESD precautions. Ensure that personnel and equipment are prcper1y grounded. Cover workbenches with grounded coR:iuctive mats .
• Always tu-n the paNer supply off before inserting or removing the device from its socket.
• Protect leads with a coR:iuctive sheet when handling or transporting PC boards with devices.

4-423

MB1519

ELECTRICAL CHARACTERISTICS

Icc 1
Power Supply Current·

Reception section is active.

.eactive.
fin

8.0

11.0

16.0

mA

Transmitlreception section

fin

5.S

10

600

MHz

Operating Frequency••

12.8
Vee - 2.7 to 4.0V, SOO

-8

o

Vee - 4.0 to 5.SV, son

-4

..

fin

Input SenslMly
OSCIN
High-level ,~ Voltage

Low-level ....,.. Voltage

20

Vosc

dBm

Vpp

0.5
VccxO·7+O.4

Except fin
andOSCIN

V
VccxO·3-0.4

1.0

Data,
Clock
Low-level ,~ Cooent

LE

-1.0

Input CUTant
High-level 0uIpd Volage

Low-level 0uIpuI Voltage

High-impedance Cutoff

Current

Vec- 3.OV

Except Do
andOSCour

DO

2.2
V
0.4

IoFF

Vp • Vee to 8.0V
Voop - GND to B.OV

1.1

-1.0

Except Do
andOSCour

1.0
Vp.6V

-1

Vcc -3V

12

Vp.6V

-3

Vee -3V

6

rnA

0uIput Cooent

002
Analog Switch ON Resistance
Hotel:

4-424

25

.: fin. 6OOMHz, OSCtN • 12.BMHz, VCC1 • VCC2 - 3.0V. The remaining iflllt pins are grounded and output pins.e open .
•• : AC COl4>Iing. Minimum operating frequency is measLl"ed when a capacitor 1000pF is connected.

MB1519

TEST CIRCUIT (PRESCALER INPUT SENSITIVITY TEST)

P.G

::::nT~.......---( ~

GND

_!

MB1519

P'G~

1000pF

SOO

~

""---+-------0()

Oscilloscope

4-425

MBiSi9

APPLICATION EXAMPLE

Output

Lock Detedor

~

Controller

3V

6V

VCC2

VP2

{
Clock

Data

002

~

MB1519

GND

OSC'N

0SC0ur

fr

Output

Nolt: VPlo VP2
C1, C2
Clock, Data, LE
X'taJ

4-426

: 8 V max.

: depends on the aystal oscillator.
: involve the schmitt circuit.
When if1)ut pins are open, please insert the puU downllop resistor individually to prevent the oscillation.
: 12.BMHz

MB1519

PACKAGE DIMENSIONS
2G-LEAD PLASnC DUAL IN·LlNE PACKAGE
(CASE No.: DIP·20P·M02)

I. .----INDEX-1

.970~:g~(24.64~~g) -----~·I

rr=====~=~====::!::::::!::::=!:::::::!===7i

r

III

o

.172(4.36)MAX

.118(3.oo)MIN

.100(2.54)
.050(1.27)
MAX

TYP

. II.

.018t.OO3
(0.46±o.08)

.020(0.51 )MIN

Dimensions in
@1991 FWrrSU UMITED D200035-3C

inches (millimeters)

4·427

MB1519

PACKAGE DIMENSIONS (Continued)
2O-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-20P-M01)

.089(2.25) MAX
(MOUNTING HEIGHT)
.002(0.05) MIN
(STAND OFF HEIGHT)

INDEX

cf

. . - - - - .450{11.43) REF - - - e o !

Dimensions in
C1991 FWrTSU LIMITED F20003S-SC

4-428

inches (millimeters)

cP

Sept. 1995
Edition O. 1a

FUJITSU

MB15S series -

Product Profile Sheet - -

IF BAND PLL FREQUENCY SYNTHESIZER
Small package and IF band MASK ROM PLL
(SIMPLL Series)
The Fujitsu MB 15S series is an exclusive Intermediate Frequency (IF) band Phase Locked Loop (PLL) frequency synthesizer with
pulse swallow operation. It can operate at a maximum of 300MHz.
The reference divider and comparison divider have fixed divide ratios, so that it is not required to set the divide ratios by a jlcontroller
externally. Since the dividers are designed by means 0'1 a MASK ROM method, a customer can choose them optionally. SOP and
SSOP 8-pin plastic packages are available.

III

It operates with a supply voltage of 3.0V typo and dissipates 3.5 mA typo of current realized through the use of Fujitsu's Bi-CMOS
technology.

FEATURES
• Operating frequency: 300MHz max.
• Low power supply current: Icc (total) =3.5 mA typo (Vee =3V)
• Pulse swallow function;
300MHz Prescaler: 16/17 or 32/33
• MASK ROM optional the comparison and reference dividers:
- Main counter; 5 to 4095
- Swallow counter; 0 to 31
- Reference counter; 5 to 4095
• Charge pump options:
- Analog cellular phones; Low sensitivity charge pump for direct modulation.
- Digital cellular phones; Super charger circuit for High speed tuning.
• Low power supply voltage: Vee =2.7 to 3.5V
• Wide operating temperature: TA =-40 to 85°C
• Plastic 8-pin SOP and 8-pin SSOP packages

SOP-8P-M01

ABSOLUTE MAXIMUM RATINGS (see NOTE)

I

/> . . '~~im~«F

\'

."'"

.".'

.':':,>:.'.:( ",.,,,~.,~~,:.,::

>:

Vee

-0.5 to 5.0

V

Input voltage

V,

-0.5 to Vee + 0.5

V

Output Voltage

VOUT

-0.5 to Vee +0.5

V

Output Current

lOUT

Ot05

mA

Storage Temperature

TSTG

-55 to +125

°C

Power Supply Voltage

NOTE:

SOP-8P-M03

Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

4-429

MB15S series

PIN ASSIGNMENT

o

Vce

Do

LO

GND

fin

OSCin

fout

4

Div

PIN DESCRIPTIONS

4-430

Vce

Power supply voltage input.

2

Do

Charge pump output

3

GND

4

fin

Prescaler input. Connection should be with AC coupling.

5

Div

Divide ratio switching input. Two kinds of divide ratios are selectable by Div input "W or "L".

6

fout

Test purpose output. This pin is an open drain output so that should be left open usually.

7

LD

Lock detector output.

8

OSCin

Ground

Reference counter input. Connection should be with AC coupling.

MB15S series

BLOCK DIAGRAM

I

III

Reference divider
Reference counter
(5 to 4095)

Data
setting
circuit

Comparison divider
Swallow counter
(0 to 31)

r'laUI
Control circuit

4-431

MB15S series

FUNCTIONAL DESCRIPTIONS
Divide ratios of the internal counters can be set optionally according to customer requirements. Two different frequencies
can be selected by Div input -W or "L-.
The divide ratio can be calculated using the following equation:
fvco - {(P x N) + A} x fose + R

(A < N)

fvco: Output frequency of external voltage controlled ocil/ator (Veo: up to 300MHz)
P:

Preset divide ratio of dual modulus prescaler (16/17 or 32133)

N:

Divide ratio of the main counter (5 to 4095)

A:

Divide ratio of the swallow counter (0 to 31)

fosc: Reference oscillation frequency ( up to 23MHz)
R:

Divide ratio of the reference counter (5 to 4095)

PHASE DETECTOR TIME CHART

fr

fp
I

~

I

_ _ _ _ _ _1

lD

Do - - -

Note:

I

tw

tw

~- - - Z • -

-q------'1- ----JH

• Phase difference detection range

- - - - - -

L

Jr------JI------JJ - -

=-2lt to +2lt

• Spikes on Do pulse during locking state are output to prevent dead zone.
• LD output becomes low when phase difference is tw or more .
• LD output becomes high when phase difference is tw or less and continues to be so for three cysles or more.
• twdepends on aSCin input frequency.
(e.g. tW635ns to 1250ns when foscin = 12.8 MHz)

4·432

MB15S series

RECOMMENDED OPERATING CONDITIONS

3.5

v

GND

Vee

v

-40

+85

Power Supply Voltage

Vee

2.7

Input Voltage

VIN

Operating Temperature

TA

3.0

HANDLING PRECAUTIONS

• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly
grounded. Cover workbenches with grounded conductive mats.
• Always tum the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

III

ELECTRICAL CHARACTERISTICS
Recommended operating conditions unless otherwise noted.

-Icc

PLL is locked. Vcc =
3.0V, Ta = 25°C

-

3.5

5.0

mA

fin

AC coupling by 1OO0pF
capacitor

10

-

300

MHz

Oscillator input frequency

fosc

AC coupling by 1OO0pF
capacitor

-

12

23

MHz

Input sensitivity

Pin

AC coupling by 1oo0pF
capaCitor

-10

-

+2

dBm

VOSCin

AC coupling by 1oo0pF
capacitor

0.5

-

-

Vpp

VIH

Vcc x 0.7

-

-

V

VIL

-

-

VccxO.3

V

IiH

-

-

1.0

J.l.A

IiL

-1.0

-

-

J.l.A

losc

-100

100

J.l.A

Power supply current
Operating frequency

Oscillator input sensivity

Input voltage (Div)

Input current (Div)

Input current (OSCin)

VOH

Vcc= 3.0V

2.6

-

-

V

VOl

Vcc=3.0V

-

-

0.4

V

VDo~3.3V

-

-

1.1

J.l.A

Output voltage

High impedance cut off current (Do)

IOFF

4-433

MB15S series

CUSTOMER REQUESTING SPECIFICATIONS

VCO output frequency

fvco

Reference oscillation frequency

fosc

Comparison
divider
Reference
divider

P

- 23MHz
fosc. R x fr

N

Main counter divide ratio

A

Swallow counte divide ratio

R

Reference counter divide ratio

fr

Reference frequency

Option

Prescaler divide ratio

16/17 or 32133

Charge pump type

5 to 4095

o to 31
5 to 4095

Low sensitivity type or
super charger

Package

SSOP 8-pin or SOP S-pin

ES request date/qty.

Typically 6 weeks from spec.
fix to the first ES.

CS request date/qty.
MP request date/qty.
Target price
Customer comments

4-434

- 300MHz
fvco - {(P x N) + A} x fr

MB15S series

PACKAGE DIMENTIONS
8-lEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-8P-M01)

6.35~:~~

I
'
;';:::::=====~-rl
i

II

i

; 7.80tO.40

"-30~t.0161

S.30tO.30
(.209:.012)
.
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1.271.0S01
TVP

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r--Re;:--

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"A"

~
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r-··-------.. ---,

: Oet.iI. of uA" part :

:: ~'201.008~.'
!....-1:
,

,

:

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,I

II

:

0.So'I.020r,
: I, 0.18(.0071:

•

I

!0.6~~~71:

.. _. --- - --~~!'-- .. ;

t:' 1992 fUJITSU LIMITED fD8002S-4C-3

OirrenalOn. In rrilimet8tl (Inches)

': This dimensIOn does nee Include resin PIOIrusion.

8-lEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-8P-M03)

.• 3.50:0.10

:gg!1

i

(.049:

I

.0' 0.10(.0041 .

(MOUNTING HEIGHt)

!~'~ ,~l~o" '
•

:

6 20:020

.I_.~ (.244~.0081

..A·· ........ -_~

080(.03151

I

TYP

- -

(oos::ggtl

O~'ds

o'-::;::'p,,"-(~M~;M~,

;

hMrW
I 2.401.09 4 1 REF

I
:0-10'

:

(STANO OFF :
I
HEIGHn;

,--i-

:~I

I

0.50:0.20

I

:.. . _____ LO!O..:: EO-.!).J

t'1992 FUJITSU LIMITED F08005HC-1

Dimensions In rriUimel8tS (inchesl

4·435

4-436

OJ

FUJITSU

March 1995
Edition 0.1

MB 15S02~~~p"~'Od~uc~tP~rO~fil!!.e~Sh~ee~t~~====-__
IF BAND PLL FREQUENCY SYNTHESIZER
Small package and IF band MASK ROM f.L.L
(SIMPLL Series)
The Fujitsu MB15S02 is an exclusive Intermediate Frequency (IF) band Phase Locked Loop (PLL) frequency synthesizer with
pulse swallow operation. The reference divider and comparison divider have fixed divide ratios, so that it is not required to
set the divide ratios by a microcontroller externally.
It operates with a supply voltage of 3.0V typo and dissipates 3.5 mA typo of current realized through the use of Fujitsu's
Bi-CMOS technology.
The RF synthesizer block of a digital cellular phone can be easily realized with an MB15S02 and MB1516A (1.1 GHz PLL, SSOP-16),
both designed with GSM systems in mind.

II

FEATURES
• Prescaler operating frequency: 300MHz

max.

• Low power supply current: Icc (total) • 3.5 mA typo (Vec • 3V)
• Pulse swallow function; Prescaler: 16/17
• Setting frequency (Selectable by Div input.)
- fose - 13.0MHz, flF • 284.0MHz (Div - -Hj
- fose - 13.0MHz, flF • 116.0MHz (Div - -L j
• Rapid synchronization at powering up
8
Fujitsu's original charge pump -super charger circuit is included, that enables
rapid synchronization at powering up.
• Lock detector
• Low power supply voltage: Vee. 2.7 to 3.5V
• Wide operating temperature: TA • -40 to 85°C
• Plastic 8-pin SSOP packages

SOP-8P-M03

Vee

-0.5 to 5.0

V

Input Voltage

VI

-0.5 to Vee + 0.5

V

Output Voltage

VOOT

-0.5 to Vee +0.5

V

Output Current

louT

Oto 5

mA

Storage Temperature

TSTG

-55 to +125

°C

Power Supply Voltage

NOTE:

Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections 01 this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

4-437

MB15S02

PIN ASSIGNMENT

o

Vee

8

OSCin

Do

7

LD

GND

6

fout

5

Div

fin

4

PIN DESCRIPTIONS

4-438

Vcc

Power supply voltage input (2.7V to 3.5V).

2

Do

Charge pump output

3

GND

4

fin.

Prescaler input. Connection should be with AC coupling.

S

Div

Divide ratio switching input. Two kinds of divide ratios are selectable by Div input "W or "l".

6

fout

Test purpose output. This pin is an open drain output so that should be left open usually.

7

lD

lock detector output.

8

OSCin

Ground

Reference counter input. Connection should be with AC coupling.

MB15S02

BLOCK DIAGRAM

III

Reference counter

.

. _---------------- ..

Data
setting
circuit

Prescaler

;-----------------------.
Comparison divider

t-----~~-~-_+-....J

16/17

t

r"OUI

Control circuit

4-439

MB15S02

FUNCTIONAL DESCRIPTIONS
Two different frequencies can be selected by Div input -W or -L-.
The divide ratios are calculated using the following equation:

fvco • {(P x N) + A} x fose + R (A < N)

PHASE DETECTOR TIME CHART

fr

fp
I

I

I

,

~

......-.

lW

lW

I

I

LO

Note: • Phase difference detection range =-2lt to +2lt
• Spikes on 00 pulse during locking state are output to prevent dead zone.

• LO output becomes low when phase difference is tw or more.
• LO output becomes high when phase difference is tw or less and continues to be so for three cysles or more.
• lWdepends on OSCin input frequency.
(e.g. tW635ns to 1250ns when !oscin z 12.8 MHz)

4-440

MB15S02

RECOMMENDED OPERATING CONDITIONS

Power Supply Voltage

2.7

Vee

Input Voltage
Operating Temperature

3.0

GND

3.5
Vee

TA

v
v

+85

HANDLING PRECAUTIONS
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly
grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

•

ELECTRICAL CHARACTERISTICS
Recommended operating conditions unless otherwise noted.

Power supply current

Icc

PLL is locked. Vcc 3.0V. Ta '" 25°C

Operating frequency

fin

AC coupling by 1000pF
capacitor

Oscillator input frequency

fosc

AC coupling by 1000pF
capacitor

Input sensitivity

Pin

AC coupling by 1000pF
capacitor

-10

VOSCin

AC coupling by 1000pF
capacitor

500

mVpp

Vee x 0.7

V

Oscillator input sensitivity

Input voltage (Div)

VIH

3.5
80
12

5.0

mA

300

MHz

23

MHz

+2

dBm

VIL

Vee x 0.3

V

IIH

1.0

~

Input current (Div)

Input current (OSCin)

ilL

-1.0

losc

-100

~

100

~

V

2.6

VOH

Vce", 3.0V

VOl

Vee

3.0V

0.4

V

10FF

VDo~3.6V

1.1

~

Output voltage

High impedance cut off current (Do)

e

4-441

MB15S02

APPLICATION EXAMPLES
GSM system

Ax: 947MHz

116MHz

4-442

MB15S02

PACKAGE DIMENSION

&-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-8P-M03)
, 25- 0 .20

~------·-:~%6~.I~i ~O~GHe~
•

. • 3.50:0.10

~
d

TYI'

I

.0, 0.10(.0041 .

I~=

INOIX

0.'0(.03151

(.041_:00~

!.I

j
5.20 i.2051

N?M

(.1'5:.0041

:

----,

.

'.20:0.20
(.246 ~.: .0011

.~

..A .. ,.;' •• '!-.- - - -.....
'

,1
035:0.10
,.014:.0041

0.10\.0041 ~

0.1 5 :g:g~

\.oos::88i,

I

- - oH".;; '01 -::;::. 'Di';i -(~~;~~I

6Jiiijj
I 2.40 (.0941 liEF

.
;0-10'

• (STANO OFF

I

I

.--+

•

HEICiHTI;

:~I

Ii.. _ _ _ _ _ _
0.50:0.20
i
____ _

.

'.020: .0011

I

e 1992 fUJITSU LIMITED FD8005S-lC-l

4-443

4-444

SECTION 5
Super Analog RF Devices - At a Glance
Introduced are a series of highly integrated Analog RF devices such as Low Noise Amplifiers (LNA), Modulators, Demodulators and Mixers that are typically used in the front ends of mobile and portable wireless
communication systems. These include single and multi-function devices based on Fujitsu's advanced RF
BiCMOS and Bipolar processes which are second to none.

Page
Number

Device Part
Number

Frequency
(max)

Features

lee (typ)

Vee

12.7 rnA

5V

8-pin
SSOP

Package

5-3

MB531

1.1 GHz

TX Mixer

5-11

MB539

1.6 GHz

LNA

SmA

5V

8-pin
SSOP

5-19

MB54501

1.1 GHz

LNAlMixer

6mA

3V

16-pin
SSOP

5-25

MB54502

1.1 GHz

Dual LNAs

4mA

3V

16-pin
SSOP

5-31

MB54503

1.1 GHz

PA Driver
Amp

26 rnA

3.6V

16-pin
SSOP

5-37

MB54609

1.0 GHz

Quadrature
Modulator

20 rnA

3V

2O--pin
SSOP

5-59

MB54619

2.0GHz

Quadrature
Modulator

25 rnA

3V

2O--pin
SSOP

•

5-1

5-2

c»

DS04-23504-1E

~~~~~~~rn~~~ET~~ruJITSU
MB531

ASSP BIPOLAR

Up Conversion Mixer (1.1 GHz)
• DESCRIPTION
The MB531 is a Up Conversion Mixer ideally suited for car telephones operating on AMPS, TACS and similar
frequency bands.
Features include local buffer amp, double balanced mixer and emitter-follower circuit for high conversion gain and
high isolation between Lo and RF inputs.
The latest silicon process technology is used to achieve a low power supply current of 13 rnA.

• FEATURES
• Wide input frequency range: up to 1.1 GHz (max)
• High conversion gain: 3.5 dB (typ) Lo: 110 MHz, -5 dBm
RF: 800 MHz, IF output: 910 MHz
• High isolation: RF-lo: -28 dB (typ): RF-IF: -13 dB (typ)
La-RF: -37 dB (typ): la-IF: -23 dB (typ)

• PACKAGE
a-pin Plastic SOP

(FPT-8P-M01 )

Copyrighl© 1995 by FUJITSU LIMITED

5-3

MB531

• PIN ASSIGNMENT

(Top view)

Vmix

RF

IF

Vbias

GND

GND

Lo

GND
(FPT-8P-M01 )

Pin No.
1

2
3
4

5
6

7

a

5-4

r

I
I
I

!
I

Symbol

I

Vmix

I

IF
GND

Pin description
Power supply (for mixer circuit)
IF output
Ground

i

Lo

I

GND

Ground

GND

Ground

i

Vbias

Power supply (for bias circuit)

I

RF

I

I

Lo signal input

RF signal input

MBS31

• BLOCK DIAGRAM

-.

Buffer amplifier

'----------(3 5 6)---------'
GND

• ABSOLUTE MAXIMUM RATINGS
Symbol

Parameter
Power supply voltage
Input voltage

Vee

I

Output current

Value

,

V,N

Vcc-3.5 to Vcc-2.5

10

I
I
!

Unit
V
V

I

mA

-55 to +125

i

I

DC

i

Value

!

Unit

I

+4.5 to +5.0

I

V

I

DC

lOUT

Storage temperature

-0.5 to +7.0

I
I

Tstg

• RECOMMENDED OPERATING CONDITIONS
Parameter

I
I

Symbol

I

Vee

Power supply voltage
Operating temperature

i

Ta

I
;

I

I

-40 to +85

5-5

MBS31

• ELECTRICAL CHARACTERISTICS
(Vee

=S.OV. Ta =+25°C)

Value
Parameter

Symbol

Condition
Min.

Power supply current

Vmi. + Vbias

Icc

fRF
Response frequency
Lo

flo
Output frequency

flF

Conversion gain

Ge

Maximum output power

=-10 to 0 dBm

-

I

NF

Third order intercept point

IP3

1 dB compression point

1dBCP

I
I

.
DSB measurement value·
Input level *
Output level *

XRF.....LO
XLO.....RF
*

XRF .... IF
XLo....lF
VRF
Open end voltage

VLO

I

At Vee =5V.
Pin function verification test
(not a condition for operation)

VIF
*: Measurement conditions: RF == BOO MHz.Lo = 110 MHz. -5 dBm, IF

5-6

9.0

-

POUT

Noise figure

Crosstalk attenuation

I

I
I
\

I

i

Max.

13.0

i

18.5

mA

1100

MHz

1100

MHz

1100

MHz

800
110

I

! 910
3.5
-7.0
I

-

i

-4

-

I

-12

i

I

13.5 !

I
I

Unit

Typ.

-28
-37

-

-13

-

-23

1.5

2.0

1.5
2.7

!

-

dB
dBm

-

j I I I

dB
dBm

I

dBm

I

: dB

I

dB

,i dB
. I

i

dB

2.5

!

V

2.0

2.5

i

V

3.2

3.7

I

V

=910 MHz. Vee =SV. Ta = +2SoC

MB531

• MEASUREMENT CIRCUIT

Vcc-5.0V
SG1
1 Vmix

100~

RF 8

2 IF

Vbias 7

3 GND

GND 6
GND 5

----i'"'__5_0;.;:;Q;............~

: 50 Q micro strip line

5-7

MBS31

• ORDERING INFORMATION
Part Number
MB531PF

5-8

I
i

Package
8-pin Plastic SOP
(FPT-8P-M01)

Remarks

MBS31

• PACKAGE DIMENSIONS
8-pin Plastic SOP
(FPT-8P-M01 )

.251992 FUJITSU LIMITED F080028-4C

I

002
0 .05 )
.006+.
-.001 (0 . 15+
-0.02

:
.008(0.20) 1

I
1

I

~

~

i

" r:

I~

I

,

I
I
I
1

I

.020(0.50) I
,
.007(0.18) I
:
MAX
I
I
,
,.027(0.68) :
,l ___________
-.
,MAX
_I
I

.I

.020±.008
(0.50±0.20)

~Details
of "A" part

I
I
I

"A"

'

III

r------------,

.150(3.81)
REF
-I

I

-t-;.-

!

I

I-

l--r
II
'
!

.018~.004 I rt-. 1
to'
(0.45±0.1 0) 1 -q:T 0.005(0.13) \(!Pi

)

I

I

[j ~
.050(1.27) ,
TYP -

.002(0.05) MIN

I(STAND OFF HEIGHT)

111

i

~~-.i
~ INDEX

.089(2.25) MAX
(MOUNTING HEIGHT)

Dimensions in inches (mm)

5-9

5-10

c»

DS04-23904-3E

~~~~~DA7j~"ASH~EET=======--FUJITSU
MB539 ASSP BIPOLAR
Low-Noise AMP for High-Frequency Bands (to 1.6 GHz)
• DESCRIPTION
The MB539 is a low-noise amplifier IC (integrated circuit) for high-frequency bands. designed for use in mobile
communications systems including portable phones.
The low-noise. high-gain features of the MB539 provide exceptional stability. The IC is capable of operating at
frequencies as high as 1.6 GHz.
The latest FUJITSU process technology is used to achieve low power consumption of 9.0 mA (typ) .

III

• FEATURES
: 5 V (typ.)
: 9.0 mA (typ.)
: 1.6 GHz (max.)
: 11 dB
: 4dB
: -2 dBm
: -17 dBm (input)
: -7 dBm (output)
• Third order intercept paint: -5 dBm (input)
: 6 dBm (output)
•
•
•
•
•
•
•

Operating voltage
Current consumption
Operating frequency
Gain
Noise figure
Maximum output power
1 dB compression point

at fRF = 1.6 GHz

• PACKAGE
8-pin Plastic SSOP

(FPT-8P-M03)
----------------_ _ - - - - - - - - ••

Copyrighl© 1995 by FWITSU LIMITED

5-11

MB539
• PIN ASSIGNMENT

(Top view)

GND

AFoUT

GND

Vee

GND

Vee

AFIN

Vee

(FPT-BP-M03)

Pin

No.

Pin description

I

I
I

GND

1

GND

2

Vee

3

GND

I GND

4

AFIN

I

AF AMP input

5

Vee

I

Power supply

I

Power supply

6

Vee

7

GND

I

AFoUT

I

B

5-12

Symbol

I

I

Power supply

GND
AF AMP output

MB539

• EQUIVALENT CIRCUIT DIAGRAM

Vee

0--...._-------_---_

AFIN

Bias
circuit

AFouT

I I

I
(Total 9.0 rnA)

5-13

MBS39

• ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Output voltage
Input voltage
Output current
Storage temperature

!
i
i

I

Symbol

!

Unit

Remarks

-0.5 to +7.0

V

I

-0.5 to Vee+0.5

V

!

-0.5 to Vee+0.5

V

10

oto 10

mA

;

Tstg

-55 to +125

°C

I

Vee

I

Vo

I

VI

!
!
I

Value
I
I

I

I

!

I

• RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Power supply voltage
Input voltage
Operating Temperature

t

Symbol
Vee
I

I

Unit

i
ii

Min.

Typ.

Max.

I

4.5

5.0

5.5

I
iI

V

I

°C

VI

GND

-

Vee

Ta

-40

-

+85

V

Remarks

I

I
I

I

Note: The user should take full precautions to prevent accidental damage from static electricity .
• For storage or transport, place in a conductive case .
• Before handling, verify that all operators, fixtures and tools are free from electrification (grounded), and
use an operating platform of grounded conductive sheeting.
• Always switch off the power before this device is inserted into or removed from sockets.
• When handling or transporting circuit boards in which this device is mounted, leads must be protected by
conductive sheeting.

5-14

MB539

• ELECTRICAL CHARACTERISTICS

I
I

Parameter

I

Value

I

Symbol

Unit

Max.

J

5.0

5.5

I

V
mA

Min.

Typ.

I

Power supply voltage

Vee

4.5

Power supply current

Ice

-

I

9.0

12.0

i

Operating frequency

fmax

-

II

1100

1600

I MHz

1.

fRF

Remarks

Vcc

= 1100 MHz

=5.0V

=5.0V. Ta =+25°C)

(Vcc
Value
Unit

Symbol

Parameter

Min.
Gain

Gain

-

16.0

Noise figure

NF

-

2.5

Maximum output power

POUT

-

0.0

1dBCP

-

-19.0

1 dB compression point

I

Intercept point

fRF

II

Iso

Remarks

Max.
I

I

-

dB

I
I

dB

I

-

dBm I
dBm

Input

dBm

Output

-

-3.0

-

-8.0

-

-

8.0

-

dBm

-

-25.0

-

dB

!
I

IP3

In-Out isolation

2.

Typ.

I dBm

Input
I

i

= 1600 MHz

(Vec

Symbol

Min.

-

Gain

Gain

I

-

Maximum output power

I

i

POUT

I

-

-2.0

I

-

-17.0

I

-7.0

i

-5.0

;
i

I

I
I

!

Intercept point

!

-

IP3

-

I

!

4.0

I

I

;

i

I

I

-

I

dB

II

-

i

dB

I

dBm

I

dBm

I Input

11.0

NF

i1dBCP!

Unit

Max.

I
i

I

Typ.

Noise figure

I

6.0

=5.0V. Ta =+25°C)

!

Value

!
Parameter

1 dB compression point

Output

I

I
I

I

!

I

I

I

I

Output

dBm

I

Input

dBm

I

Output

dB

I

I dBm

-

Remarks

i
!

In-Out isolation
Note:

I

Iso

-

-20.0

-

• Electrical characteristics may vary depending on the use of external elements or mounting conditions .
• The above characteristics represent data obtained with the". MEASUREMENT CIRCUIT."

5-15

MB539

• MEASUREMENT CIRCUIT

GND

AFooT

Vee

GND

GND

Vee

AFIN

Vee

1----+

To spectrum
analyzer, etc.

Vee=5.0V

Vee=5.0V

r

• ORDERING INFORMATION
Part Number
MB539PFV

5-16

Package
B-pin Plastic SSOP
(FPT-BP-M03)

Remarks

MB539

• PACKAGE DIMENSION
- - - - -... - . - - - - - . ----- .. ----.-.-.-.-----.--.

8-pin Plastic SSOP
(FPT-8P-M03)

l

*: This dimension does not include resin protruction.

!

• 3.5~0.10

~

I

I

4.2~0.10

1d:;:c5;;:::;:;;::'N::;D;::EX;:::;:~~~1
TYP

I I.

ijli1ijj
li.

40!.0941REF,I

III

",

"A"

0.80(,0315),

I

t,

"""'-"'[1

0.15:::

, "(.006=:')

r-----------------

I Details of "A" pan

:

I
I
I

I
I

I

I

I
I
I
I

I

I

I
I

I

:_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ JI

@)

1994 FWITSU LIMITED F08OO5S-1C-2

Dimensions in mm (inches)

5-17

5·18

00

Sept. 1995
Edition 1.0a

FUJITSU

Data Sheet

MB54501
FRONT-END UP/DOWN CONVERTER

INTRODUCTION
The Fujitsu MB54501 includes a low-noise amplifier and a mixer, which are used
for front end of mobile telecommunication systems.
Using Fujitsu's advanced technology, MB54501 achieves an Icc of 6.0mA (typ.).

•

ELECTRICAL CHARACTERISTICS
Amplifier

Mixer

•

Supply voltage

3V (typ.)

3V (typ.)

•

Current consumption

3mA (typ.)

3mA (typ.)

•

Input frequency

1.1GHz(max.)

1.1 GHz(max.)

•

Gain

14dB (typ.) *1

15dB (typ.) *2

•

Noise figure

2.2dB (typ.) *1

5dB (SSB, typ.) *2

•

1dB compression point

-1dBm (typ.) *1

•

Input return loss

8dB (typ.) *1

•

10dB (typ.) *1
Output return loss
*1 : Measured by the circuit of "measurement circuit example".
(fin = 878M Hz)

PLASTIC PACKAGE
. FP-16P-M05

*2 : Measured by the circuit of "measurement circuit example".
(IF = 90MHz)

PIN ASSIGNMENT

PACKAGE
•

16-pin Plastic Shrink Small Outline Package (Suffix: -PFV)

ABSOLUTE MAXIMUM RATINGS
I'·:· .,:,.

Parameters

'."

.'< I,· ".',.:
:.:/::<
.;:>~;I;J~I,i< / \ » i · .: . . . ,.,.,..//

~;,~~:[i
{i

Vee

-0.5 to 7.0

V

Output Voltage

Va

-0.5 to Vcc+0.5

V

Storage Temperature
NOTE:

Lext

GND

RFin

GND

Rext

,",i ,O:'\i·,·,,:,

Supply Voltage

Output Current

RFout

10

Oto 10

mA

TSTG

-55 to +125

°c

Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

VCC

NC

NC

RE

GND

RE

GND
MIXin

GND
MIXout

This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields.
However, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated
voltages to this high impedance circuit.

Copyright@ 1994 by FUJITSU LIMITED and FUJITSUMICROELECTRONICS, INC.

5-19

MB54501

EQUIVALENT CIRCUIT

Main
Bias
Circuit

•

Main
Bias
Circuit

Amplifier ----I.~

.,

Mixer

•

PIN DESCRIPTIONS
Pin No.

5-20

Description

Pin Name

Description

Pin No.

Pin Name

9

MIXout

Mixer output

GND

Ground

RE

Emitter of a transistor for mixer

1

RFout

Amplifier output

2

GND

Ground

10

3

GND

Ground

11

4

Vee

Power supply

12

5

NC

No connection

13

NC

No connection

6

GND

Ground

14

Rext

Emitter of a transistor for amplifier

7

GND

Ground

15

RFin

Amplifier input

8

MIXin

Mixer input

16

Lext

Amplifier load connection

MB54501

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Symbol
Min.

TYP.

Max.

Un"

Supply Voltage

Vcc

2.7

3.0

5.5

V

Input Voltage

VI

GND

-

Vee

V

Operating Temperature

Ta

-40

-

+85

°c

Note.: To protect against damage by electrostatic discharge, note the following handling precautions:
-

Store and transport devices in conductive containers.

-

Use proper1y grounded workstations, tools, and equipment.

-

Tum off power before inserting or removing this device into or from a socket.

-

Protect leads with conductive sheet, when transporting a board mounted device.

III

5-21

MB54501

ELECTRICAL CHARACTERISTICS
AMPLIFIER

(Vcc = +3.0V, Ta = 25°C)

• • • •.• . . . i)

·.·.·1 .• · • •· • .•·.•..··.·./.·.····

Supply Voltage

Vee

Supply Current

lee

... .

2.7

3.0

5.5

3.0

Operating Frequency

mA

878

Gain

V

MHz

1100

Gain

14

dB

Noise Figure

NF

2.2

dB

1dB Compression Point

PldB

-1

dBm

Input Retum Loss

RLIN

8

dB

RLoUT

10

dB

Output Return Loss

Output

Remark: Electrical characterisics depend on extemal circuits (elements) or status of mounting.
The above characteristics are measured by the test circuit in the next page.

MIXER
. . ·i i.··· > ).
::.

i

)<.

(Vcc = +3.0V, Ta = 25°C)

...

.

...........
ii
.i

.......

:.

~.....

\ ......, . ...
}

Supply Voltage

Vee

2.7

3.0

5.5

V

Current Consumption

Icc

-

3.0

-

mA

Operating Frequency

MIXIN

-

878

1100

MHz

9

-

dB

-

15

-

dB

-

5

-

dB

Gain

S21

Amplifier characteristics

Conversion Gain

Gc

Noise Figure

NF

Mixer
characteristics
IF= 90MHz

SSB

Remark: Electrical characterisics depend on extemal circuits (elements) or status of mounting.
The above characteristics are measured by the test circuit in the next page.

5-22

i

••••••

MB54501

MEASUREMENT CIRCUIT (EXAMPLE)

2nH

100p

50n

measuring ~ t--......--f 1 AFout

apparaw.

3,on

!

;J; 1000p
Vcc=3V-.--....--.....~

Vee

NC 13

NC

RF=878MHz

3pTaop
r,6o
LO=788MHz

.---~t---+-4--

VcC=3V

J;20P J;30P

5-23

MB54501

PACKAGE DIMENSIONS
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M05)

.049~:gg:

--I-+--~----

(1.25~:~g)

~ ~ ~~~~i)~ ~I
.252±.OO8
(6.40±0.20)

INDEX

cf

*.173±.004
(4.4o±o.10)

~;::;:;:::::;:;:~~
.0256±.0047
(0.65±O.12)

.11 .

.OO9~:~

(MOUNTING HEIGHT)

1
..~

.213(5.40) NOM

,,-L

.006

~:gg~ (0.15~:g~)

(O.22~:Jg)

t:j
REF

*:This dimension does not include resin protrusion.
©1991 FUJITSU LIMITED F16013S-2C

5-24

Dimensions in
inches (millimeters)

00

Sept. 1995
Edition 1.0a

FUJITSU

Data Sheet

MB54502
LOW NOISE AMPLIFIER (2 CIRCUITS)
LOW NOISE AND CURRENT AMPLIFIER
INTRODUCTION

The Fujitsu MB54502 includes two independent amplifiers which are used for mobile
telecommunication applications such as handy phones and car phones. Both of the
amplifiers achieve low current consumption as well as the low noise performance.
Using Fujitsu's advanced technology, MB54502 achieves an Icc of 2mA typo respectively (total4mA typ.).
ELECTRICAL CHARACTERISTICS

• Supply voltage
• Current consumption
• Input frequency

3V (typ.)

• Gain
• Noise figure
• 1dB compression point

14dB (typ.) *1
2.2dB (typ.) *1
-6dBm (typ.) *1

• Amplitude tolerance
• Input return loss

2.5dB (typ.) *1
8dB (typ.) *1

2mA (typ.)
1.1 GHz(max.)

• •

PLASTIC PACKAGE
FP-16P-M05

8dB (typ.) *1
• Output return loss
*1 : Measured by the circuit of "measurement circuit example".
(fin =820M Hz)

PIN ASSIGNMENT

PACKAGE

• 16-pin Plastic Shrink Small Outline Package (Suffix: -PFV)
Rext1 C

ABSOLUTE MAXIMUM RATINGS

\i,ii,·

.. /.::.:

:::;::.:.. :.::.' :'.::

Supply Voltage

-{l.5 to 7.0

V

Output Voltage

Vo

-{l.5 to Vee+0.5

V

Output Current

10

Oto 10

rnA

TSTG

-55 to +125

°c

Storage Temperature
NOTE:

1St:J GND

RFout1L 3

14tJ Vcc1

GNDC 4

Vee

Pennanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

1St:J RFin1

1

Lext1C 2

NCC S

TOP

VIEW

13t:J NC
12t:J Vcc2

RFout2C S

11t:J GND

Lext2C 7

10pGND

Rext2C 8

et:J RFin2

This davice contains circuitry to protect the inputs against
damage due to high static voltages or electric fields.
However, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated
voltages to this high impedance circun.

Copyright@ 1994 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS, INC.

5-25

MB54502

EQUIVALENT CIRCUIT

Main
Bias
Circuit

Amplifier1 ----I.~

Amplifier2 ---~

•

PIN DESCRIPTIONS
Pin No.

5-26

Description

Pin Name

Description

Pin No.

Pin Name

9

RFin2

Input (amplifier 2)

1

Rext1

Emitter (amplifier 1)

2

Lext1

Load connection (amplifier 1)

10

GND

Ground

3

RFout1

Output (amplifier 1)

11

GND

Ground

4

GND

Ground

12

Vcc2

Power supply (amplifier 2)

5

NC

No connection

13

NC

No connection

6

RFout2

Output (amplifier 2)

14

Vcc1

Power supply (amplifier 1)

7

Lext2

Load connection (amplifier 2)

15

GND

Ground

8

Rext2

Emitter (amplifier 2)

16

RFin1

Input (amplifier 1)

MB54502

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Symbol

Unit

Min.

Typ.

Max.

3.0

5.5

V

Supply Voltage

Vcc

2.7

Input Voltage

VI

GND

-

Vee

V

Operating Temperature

Ta

-40

-

+85

°c

Notes: To protect against damage by electrostatic discharge, note the following handling precautions:
-

Store and transport devices in conductive containers.

-

Use property grounded workstations, tools, and equipment.

-

Tum off power before inserting or removing this device into or from a socket.

-

Protect leads with conductive sheet, when transporting a board mounted device.

III

5-27

MB54502

ELECTRICAL CHARACTERISTICS
(Vcc1 = +3.0V. Vcc2=0.OV. Ta = 25°C
or Vcc1 = O.OV, Vcc2=+3.0V. Ta = 25°C)
Target Value
Parameter

Symbol

Supply Voltage

Vcc

Supply Current

Icc

Operating Frequency

fin

Gain

Conditions

1 amplifier active

2.7

3.0

5.5

V

-

2.0

-

mA

-

820

1100

MHz

14

dB
dB

2.2

Output

-

-6

-

dBm

820±50 MHz

-

2.5

-

dB

RLIN

-

8

-

dB

RLoUT

-

8

-

dB

NF

1dB Compression Point

PldB

Output Return Loss

Max.

-

Noise Figure

Input Return Loss

~.

-

Gain

Amplitude Tolerance

-

Remark: Electrical characterisics depend on external circuits (elements) or status of mounting.
The above characteristics are measured by the test circuit in the next page.

5-28

Unit

Min.

MB54502

MEASUREMENT CIRCUIT (EXAMPLE)

1 Rextl

son
measuring
apparatus

-:r
-:rSP
S.2n

~SUring
apparatus

S.2n

III
Vcc1=3V

Sp

Vcc2=3V

3.

5-29

MB54502

PACKAGE DIMENSIONS
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M05)

049+. 008

--tI~-f04--'_-_.0_0_4_ (MOUNTING HEIGHn

I~ ~:'ff;)~ ~
J
U

INDEX

(1.25:g:~g)

1

I

I

.252:1:.008
(6.40±0.20)

1
..~

.213(5.40) NOM

*.173±.004
(4.40±0.10)

~;::::::;;:::;:;~~
.0256±.0047

.009~:&~

(0.65±o.12)

(0.22~:Jg)

r=!

.[JplL

.- - - - - - - - - -Oetaiis-of

ftA; part ---------,
(STANDOFF

~".:: HEIG~

O"'~

REF

t.

(O.so±o.20)

_______________________

...

____ ,

*:This dimension dOes not include resin protrusion.
©1991 FUJITSU LIMITED F16013S-2C

5-30

Dimensions in
inches (millimeters)

00

Sept. 1995
Edition 1.0a

FUJITSU

Data Sheet

MB54503
HIGH-POWER AMPLIFIER

INTRODUCTION
The Fujitsu MB54503 is a high-power amplifier which is used for mobile telecommunication systems such as handy phones and car phones. This device is ideally
suitable for power amplifier driver.
Using Fujitsu's advanced technology, MB54503 achieves an Icc of 2B.OmA (typ.) .

•

ELECTRICAL CHARACTERISTICS
• Supply voltage

3.BV (typ.)

• Current consumption

2BmA (typ.)

• Input frequency

1.1 GHz(max.)

• Gain
• Output lavel (@Pin=-8dBm)

25dB (typ.) *1

• Input return loss

14dB (typ.) *1

III

PLASTIC PACKAGE
FP-16P-M05

+13dBm (typ.) *1

• Output return loss
BdB (typ.) *1
*1 : Measured by the circuit of "measurement circuit example".
(fin =933MHz)

PACKAGE
• 16-pin Plastic Shrink Small Ooutline Package (Suffix: -PFV)

PIN ASSIGNMENT

RFin1

ABSOLUTE MAXIMUM RATINGS

GND
Rext1

GND
Supply Voltage

Vee

-0.5 to 7.0

V

Output Voltage

Vo

-0.5 to Vee+0.5

V

Output Current
Storage Temperature
NOTE:

10

Oto 10

TSTG

-55 to +125

mA

Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periodS may affect device reliability.

NC

GND
Lext
RFout1

NC
RFin2

Vee

Rext2

GND

GND

RFout2

GND

This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields.
However. it is advised that normal precautions be taken to
avoid application 01 any voltage higher than maximum rated
voltages to this high impedance circu~.

Copyright@ 1994 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS. INC.

5-31

MB54503

EQUIVALENT CIRCUIT

Main
Bias
Circuit

Main
Bias
Circuit

_______ The first amplifier - - +

4--

The second amplifier ----.

PIN DESCRIPTIONS
Pin No.

5-32

Description

Pin Name

Description

Pin No.

Pin Name

9

GND

Ground

1

RFin1

The first amplier input

2

GND

Ground

10

GND

Ground

3

Rext1

Emitter for the first amplifier

11

Rext2

Emitter for the second amplifier

4

GND

Ground

12

RFin2

The second amplier input

5

NC

No connection

13

NC

No connection

6

Vcc

Power supply

14

RFout1

The first amplifier output

7

GND

Ground

15

Lext

Load connecting for the first amplifier

8

RFout2

The second amplifier output

16

GND

Ground

MB54503

RECOMMENDED OPERATING CONDITIONS
Value
Parameter

Unit

Symbol
Min.

Typ.

Max.

Supply Voltage

Vee

2.7

3.6

5.0

V

Input Voltage

VI

GND

Vee

V

Operating Temperature

Ta

-40

-

+85

°c

Notes: To protect against damage by electrostatic discharge, note the following handling precautions:

-

Store and transport devices in conductive containers.

-

Use properly grounded workstations, tools, and equipment.

-

Tum off power before inserting or removing this device into or from a socket.

-

Protect leads with conductive sheet, when transporting a board mounted device.

•

5-33

MB54503

ELECTRICAL CHARACTERISTICS
(Vcc = +3.6V, Ta = 25°C)
Target Value
Parameter

Symbol

Conditions
Min.

Typ.

Max.

Supply Voltage

Vcc

2.7

3.6

5.0

V

Supply Current

Icc

-

26

-

mA

Operating Frequency

fin

-

933

Gain

Gain

-

25

-

dB

Output Power

Pout

-

+13

-

dBm

Input Return Loss

RLIN

-

14

-

dB

RLoUT

-

6

-

dB

Output Retum Loss

Pin =-8dBm

Remark: Electrical characterisics depend on extemal circuits (elements) or status of mounting.
The above characteristics are measured by the test circuit in the next page.

5-34

Unit

1100

MHz

MB54503

MEASUREMENT CIRCUIT (EXAMPLE)

933MHz

~00p

VCC=3.6Vr- . - -......1000P

10n
~--I1

RFin1

........- - - - I

J;

50Q
measuringapparatus

VCC=3.6V

-.__--+----.----'
1OOOp

J;

J; 100p

5-35

MB54503

PACKAGE DIMENSIONS
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M05)

.049~:gg:

--Jot--"I4-----

~ ~ ~:.~;)~ ~
J
U

INDEX

(1.25~:~g)

1

I

I

.252±.008
(S.40±0.20)

1

.213(5.40) NOM

*.173±.004
(4.40±0.10)

l4=;t=;;r=n=n=~ ~
.0256±.0047
(0.65±o.12)

(MOUNTING HEIGHT)

"A"

~

..

~'

'-~r' .006 +.002 (0.15+0.05)
I

.11.

,

, 'r
,-

E:f
REF

-

-

-

-

-

-

-

-

-

-

-

-.001

-

-

-

-

-

-

-

-

-

-0.02

_.

-

-

-

-

-

1

Details of "A" part

.oott.OO4

(STANDOFF

[JJ1~'::0. HEIG~

ooto.;::t±

(O.5O±O.20)

*:This dimension does not include resin protrusion.
©1991 FUJITSU LIMITED F1S013S-2C

5-36

Dimensions in
inches (millimeters)

cP

OS04-23509-1 E

~~~~~~~~~~~ET~~ruJrrsu
M 854609 ASSP for Telephone
Quadrature Modulator Ie (With 1.0 GHz Up-Converter)
• DESCRIPTION
The MB54609 is an intermediate-frequency (IF) quadrature modulator IC
optimized for use in digital mobile telecommunication systems such as GS
The MB54609 incorporates a quadrature modulator for IF modulation,
type phase shifter as well, capable of handing IFs in a broad band.

:uD-lc:onven mixer, and a F/F
power supply current of 18 mA
device.

In addition, the MB54609 operates at a low power supply
(both as typical values), contributing to saving the power

-,III

• FEATURES
• Incorporating a high-performance tranlsmiissi~
used for POC services (Maximum output
Maximum output frequency: 1.1 GHz,
• Externally connecting the quad
to be inserted in between
The quadrature modulator

the entire frequency band of up to 800 MHz
GHz)
dBm (typical)
the transmission mixer, allowing a bandpass filter (BPF)

(Continued)

• PACKAGE
20-pin Plastic SSOP

(FPT-20P-M03)

Copyright© 1995 by FUJITSU LIMITED

5-37

MB54609

(Continued)

• Flip-flop phase shifter capable of handling intermediate frequencies in the broad band (100 to BOO MHz)
• Operation at low voltage: 2.7 to 3.0 to 3.3 V
• Low current consumption
During operating: 1B.0 rnA (typical)
In power save mode: 0.6 rnA (typical)
• Operating temperature range: Ta =-20 to +B5°C

• PIN ASSIGNMENT

MB54609

• PIN DESCRIPTION
Pin no.

Pin name

Function

1

RFout

Up-converter output pin

2

GND

GNOpin

3

L02

LO input pin for mixer

4

GND

GNOpin

5

XIF

IF input complementary pin for mixer

6

IF

IF input pin for mixer

7

L01

LO input pin for quadrature modulator

8

XL01

LO input complementary pin for quadrature modulator

9

GND

GNDpin

10

Vee

Power supply pin

11

Vee

Power supply pin

12

GND

GNDpin

13

I

Baseband input (I) pin

I Power supply voltage must be applied to both pins.

14

XI

Baseband input (I) complementary pin

15

QMOD

Quadrature modulator IF output pin

16

XQMOD

Quadrature modulator IF output complementary pin

17

XQ

Baseband input (Q) complementary pin

18

Q

Baseband input (Q) pin

19

GND

GNDpin

20

PS

Power save mode control pin

5-39

MB54609
• BLOCK DIAGRAM

Vee

GND

IF

QMOD

XI

RFout
Q

XQ

PS

L01

XL01

XQMOD

L02

XIF

• ABSOLUTE MAXIMUM RATINGS

I

Symbol

Rating

Power supply voltage

Vee

-0.5 to 5.0

Output voltage

Vo

-0.5 to Vee + 0.5

V

Input voltage

VI

-0.5 to Vee + 0.5

V

Open collector applied voltage

Voc

Vee± 0.3
(-0.5 to 5.0)

V

Output current

10

±10

rnA

Storage temperature

Tstg

Parameter

-55 to +125

Unit

Remarks

V

i

RFout pin
Do not leave this pin
open.

°C

Note: Although the MB54609 contains an antistatic element to prevent electrostatic breakdown and the circuitry
has been improved in electrostatic protection, observe the following precautions when handling the device:
• When storing or carrying the device, put it in a conductive case.
• Before handling the device, check that the jigs and tools to be used have been uncharged (grounded) as
well as yourself. Use a conductive sheet on the working bench.
• Before fitting the device into or removing it from the socket, turn the power supply off.
• When handling (such as transporting) the MB54609 mounted board, protect the leads with a conductive
sheet.

5-40

Precaution: Exceeding any of the above absolute maximum ratings may cause permanent damage to the LSI. For
normal operation, the device should be used under the recommended operating conditions.
Exceeding any of the recommended conditions may adversely affect LSI reliability.

MB54609

• RECOMMENDED OPERATING CONDITIONS
Parameter

Value

Symbol

Unit

Min.

Typ.

Max.

2.7

3.0

3.3

V

GND

-

Vee

V

-

Vee + 0.2

V

+85

°C

Power supply voltage

Vee

Input voltage

VI

Open collector applied voltage

Voc

Vee-O.2

Operating temperature

Ta

-20

Remarks

AFout pin. Do not leave this
pin open.

• ELECTRICAL CHARACTERISTICS
Parameter

Symbol

(Vee
Value

Min.

Typ.

Max.

Unit

=3.0 V

I

Ta =+25°C)

Remarks

Power supply current

Icc

-

1B.0

23.5

mA

DC current (Input with no
AC signal)

Power supply current in power
save mode

leePS

-

0.6

0.9

mA

DC current (Input with no
AC signal)

Shifter input
L01

Baseband
input

Operating band

fL01

100

400

BOO

MHz

Input level

PL01

-15

-5

dBm

Operating band

fee

DC

10

MHz

Input amplitude

Vaa

-

-

1.2

Vpp

Offset voltage

Vos

1.5

1.6

1.7

V

3.0

-

750

1100

MHz

PL02

-

-

0

dBm

fRF

-

950

1100

MHz

-

dBm
%

RMS value

Offset current

los

Mixer input
L02

Operating 6and

fi.02

Input level

Mixer output
RFout

Operating band

Modulation
precision

External offset voltage value
Input Imp. converted value
5331<0

~

fRF

=

= fL02 ± fL01/2

Output level

PRF

-

-9

Ampmude deviation

AERR

1.3
0.B2

-

deg.

RMSvalue

OMJOlMix direct COIlnm

1.9

-

%

RMSvalue

V88= 1Vpp

-40

-30

dBc

Phase deviation

PERR

Vector error

VERR

-

CS

-

Carrier suppression

I

-

flOl = 400 MHz (-15 dBm)
fL02

= 750 MHz (-5 dBm)

fRF = 950 MHz output

With external offset
unadjusted

5-41

MB54609

• EVALUATION BOARD (Reference Example)
• Material: BT resin BT-HL870 (Dielectric constant [1 MHz] = 3.4 to 3.6)
• Thickness: 4 layers, 1.6 mm (Copper thickness: External layer = 18 J.I1T1, Internal layer = 70 J.l.m)
• Plating: electroless gold plating
• Layer 1
(front surface)

o

/
o

o

o

.®.
.
. · 0

.~.

o

o

o

.~.
•

nll/lotIGl/lotll]!'!! •

z=aICaggg~a;otnl!.~

0

o

o

v .o
..

o

o

~
• Layer2

. .. ~td.[gjld. . ~l·

.~

o

/

.

• @) •

• @ •

0 · 0

. ...~ ~

o

0 0: °:

o.

•

o " .

. .
0

."...

·:":"0·0··

.. .

•••

• D

••

••

0

. .

.

•

. @

.0

@)

.

o

o

0

0

5-42iL--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
(Continued)

MB54609
(Continued)
• Layer3

v

o

o

o

~

.r:'\

~.

o ..

.~

.
•

oE!j

o

o·

.

. · .. 0

0

.. . .

o
. 0
0: . . :: 0

0:

0

o

0

· ..EL.a o. .
..
~

o 00

0

o

0

o

0

0.

o.

.
0
0

00 •
•

0

o

0

• Layer4
(rear surface)

0

o

o

o

o

00
0

0

.~o

0

.¥
o
/

o

o@o

o

•

•

0

....
•

o

0

[!l!J

o

0

o

0

o

o

o
5-43

MB54609

• MEASUREMENT DATA (Reference Values)
* Application-common characteristiCs

• DC characteristics (test circuit 1)
@ Input with no AC signal

40

1

30

J!
c
~

::l
U

>.

¢o

20

-e:
1/1

~

0

__----

------

_ _ Vcc-3.3V
.
Vee - 3.0 V

_--- Vee - 2.7 V

--------- --------------

::l

a..

----

Icc

__ •

10

1.0

~
~
i
::l

1/1-

'-c(

o

-20

o

20

40
Temperature Ta (OC)

5·44

60

80

0.8

i~

0.6

~]
~

0.4

!
1/1

1

MB54609

• Input Impedance (Only Ie: test circuit 4)
@ Impedance from Ie pin end

.

.

L01
1 UFS

CH1 S11

1: 195.750

-766.130

2.0774pF

28.0390
-255.40
300 MHz
16.0550
-145.70
SOOMHz
12.6680
-77.5590
800 MHz

C2

log MAG

CH2 5 11

10 dBIREF 0 dB

1.:

:i
.3.:

C2
4

2

A:

I

-.2709 dB

L02

CH15 11

1 UFS

1: 16.3540

3.2268 pF

C2
3:

CH2 5 11

log MAG

.1:

10 dBlREF 0 dB

14.8770
-50.0180
900 MHz
13.7250
-39.764 0
1 GHz
14.7460
4.84030
1.6GHz
-2.2095 dB

800.200 000 MHz
J559dB
300 MHz

~~~fo
-1~~~~

2:

1:

C2

"

I

!:

[j.

3

4

-2.5448 dB
900 MHz
-2.8953 dB
1 GHz
-5.2236 dB

fo

1.6GHz

I
I

1
I
START 100.000 000 MHz

~1.6390

I

STOP 2100.000 000 MHz

START 100.000 000 MHz

STOP 2100.000 000 MHz

• Output Impedance (Only Ie: test circuit 4)
@ Impedance from Ie pin end
• RFout
CH1 5 22

1 UF5

1:9.86330

-124.640

1.5961 pF

9.8984 0
-106.210
900 MHz
11.0550
-92.5080
lGHz
12.1370

C2

4:ftftfz

CH2 S22

log MAG

1:

10 dBlREF 0 dB

-.4733 dB

_8QIl.000 000 MHz

C2

l.:

-.6207 dB
900 MHz

.3.:

-.8619 dB
lGHz

V
A

1
2

I
I
START 100.000 000 MHz

3

Cl
4

.!: -2.0524 dB

I
J
I

lt

GHZ

I
I

STOP 2100.000 000 MHz

5·45

MB54609

• SOG-MHz POC APPLICATION MEASUREMENT DATA (Reference Values)
Parameter
Baseband input signal
Shifter input signal L01

Mixer input signal L02
Mixer output signal RFout

Return loss

Measurement Unit
result

Symbol

Condition

fee

42

kbps

7tl40QPSK, Root-Nyquist filter (a =0.5)

Vee

1.0

Vpp

Single-end input

-

-

flOl

400

MHz

PlOl

-15

dBm

-

-

fl02

750

MHz

-

PlO2

-5

dBm

-

-

-

fRF

950

MHz

fRF = fl02 + flOl/2

PRF

-8.4

dBm

SSBvalue

1

RLlOl

-17

dB

=400 MHz
fl02 =750 MHz
fRF =950 MHz

3

RLl02

-2

dB

RLRF

-12

dB

AERR
Modulation precision

PERR

I

VERR

I

Carrier suppression

CS

flOl

RMS Magnitude Error

1.3

%

0.82

deg.

RMS Phase Error

1.9

%

RMS Vector Error

-34.5

dBc

i

-

• External circuit constants (with the IC mounted on the evaluation board)

GND

XQMOD
M854609

QMOD
XI

GND
Vee

5-46

Test
circuit

2
2

MB54609

• Modulation precision and output spectrum (test circuit 2)
@ Baseband signal: rtl4 OQPSK, 42 kbps, 1.0 Vpp, PN 15, Root-Nyquist filter a
Input signals: L01 400 MHz, -15 dBm; L02 750 MHz, -5 dBm
Output signal: RFout 950 MHz

=

=

=

• Modulation precision

=0.5

• Output spectrum

_V_

lao

RMSVecIar

Enor.
Enor • •1.112~
.2!M~

RMS~Enor.

,'-

_~

3.*~

RMS _
_
_

Enor •
Enor •
Enor.

CMW F..cj
CMWPIIaH

OIIMI.
OIIMI.
•

L :'\

0.821 Goga
-2.2~Goga

II

a.sel..o:l Hz
15Usedlgl
-32.421c11

O'-~
(~.e35. 10.3!MI~

BlaV_

.( 2.306.

GmIIy ~

•

,

\

r

Ila,

VG: 5.000.01 VlOIN
IIaMbIInd Filler: RlNyq (o,sooo) Rectangle Len •

~

III

I'

I

\
.MAIolo..

..IJ

CENTER. 950 MHz
SPAN. 200 kHz
RBW • 3 kHz VBW. 100 Hz SWP = 3 s
An.10dB
REF. 0 dBm 10 dB/div.

OSR ••. 7el905

• Spectrum (test circuit 2)
@ Baseband signal: rtl4 OQPSK, 42 kbps, 1.0 Vpp, 0000, Root-Nyquist filter a
Input signals: L01 = 400 MHz, -15 dBm; L02 = 750 MHz, -5 dBm
Output Signal: RFout 950 MHz

=0.5

=

=700 MHz
;--r-¥

• Span = 240 kHz

• Span

~r-~
~f-~

-

I

N

~e

l:

::Ee
°m
Je'C

r-~~
--- ..... '0

&~

)(.-

~I

;-~
g~

f - _lOCO

.5~

~r-~

:5rg-;-e!.ci- -

N

~

J \

I \

I

...- U

I

1 •J

VW

V

II

J

\ I

~l

I

t

l

I

I

I

1

III

W1a.&A.u. III

CENTER =950 MHz
SPAN = 26.2 kHz
RBW =300 Hz VBW = 300 Hz SWP = 1.3 s
An .. 10dB
REF = 0 dBm 10 dB/div.

CENTER = 750 MHz
SPAN = 700 MHz
RBW .. 1 MHz VBW .. 3 kHz SWP = 1.1 s
An= 10dB
REF .. 10 dBm 10 dB/div.

~----------------------------------------------------

~

5-47

MB54609

• RF output level dependent on baseband amplitude (PRF: test circuit 1, Modulation precision: test circuit 2)
@ Baseband Signal of test circuit 2: rrJ4 DQPSK, 42 kbps, 1.0 Vpp, PN 15, Root-Nyquist filter a. = 0.5
Input signals of test circuits 1 and 2: L01 =400 MHz, -15 dBm; L02 = 750 MHz, -5 dBm
Output signals of test circuits 1 and 2: RFout 950 MHz

=

0

E -10

III

l

l

>

:E.

ffi

Q.

~
6 w

1 -20

i

i

>

0

u.
a: -30

- 4

:e
a:
,sa1/1c:

c> VERR

~

-40

en

- 2

lg
i

'5

o ~

0,1

10
Baseband amplitude Vf18 (Vpp)

• RF output level dependent on L01 and L021nput levels (PJu:: test circuit 1, Modulation precision: test circuit 2)
@ Baseband Signal of test circuit 2: nl4 DQPSK, 42 kbps, 1.0 Vpp, PN 15, Root-Nyquist filter a. = 0.5
Input signals of test circuits 1 and 2: L01 400 MHz, -15 dBm; L02 750 MHz, -5 dBm
Output signals of test circuits 1 and 2: RFout = 950 MHz

=

=

• RF output level dependent on L02 Input level
(@Pl01 = -15 dBm)

• RF output level dependent on L01 Input level
(@Pl02 = -5 dBm)

l

0,...

ffi
>

E

o
~

III

:E. -10- 6

1
j/

40

c> VERR

a:

!

.2

-2~

~

-40r' - - - - - " ' - - 1 - - - ' - 1 - -.....
1----'1---' 0

-20

-15

-10

-5

Shifter output level

5-48

PLOt

0
(dBm)

5

0-

ffi

>

:E. -10 - - . . ; . . : . . ; - - - - - - - - - ~

- 6

'S

s5 -30-

u.
a:

-40 -

~
::E

i

>
en
- 4 :e
a:

-20-

c:

-

6

'8

g
w

¢PRF

S cfQj

i_30r-~-4~
::.

E
III

c> VERR

'en
'u

0

-.;::

~

1

-20

0

- 2

1

-15

-10

Mixer input level

1

-5
PL02

1

o
(dBm)

5

c.
c:
0

ClI

'5

'8

::E

MB54609

• RF output level dependent on temperature (PRF: test circuit 1, Modulation precision: test circuit 2)
@ Baseband signal of test circuit 2: 1tI4 OQPSK, 42 kbps, 1.0 Vpp, PN 15, Root-Nyquist filter a = 0.5
Input signals of test circuits 1 and 2: L01 400 MHz, -15 dBm; L02 750 MHz, ~ dBm
Output signals of test circuits 1 and 2: RFout 950 MHz

=

=

=

o
¢> PRF

eco

--.~.--.
•
'.
Vee'"=3.0
3.3 V
V
_____________
:.. ___• __ Vee

-10

~

_----

Vee-2.7V ~

-

:s

!.

-20

i

-30

1
o

~~

ffi

LL

a:

i

J3

.......... ~.

4)

.... - ~."'--._.
.~~..:1:.3 V 2
;;;
- - - - - - - - - - - - - Vee = 3.0 V ::!:
r::> VERR
Vee. 2.7 V
a:

5

·iii

-40

"[
6

i

~~----~----~----~----~~----~--~o

-20

0

20

40

60

~
::!:

80

Temperature Ta (OC)

• Carrier suppression dependent on temperature (test circuit 2)
@ Baseband signal: 1tI4 OQPSK, 42 kbps, 1.0 Vpp, 0000, Root-Nyquist filter a
Input signals: L01 = 400 MHz, -15 dBm; L02 = 750 MHz, ~ dBm
Output Signal: RFout 950 MHz

=0.5

=

-20

S

-30

:s
CI)

o
c

.~

--'--- ---

_ . _ Vee=3.3V

_ _. - .

-40

!
:J

Vee = 3.0 V

_.-.

-----

_ - - - - Vce=2.7V

VI

iii -50

.~

o
-40

-20

o

20

40

60

80

Temperature Ta (0C)

5-49

MB54609

• Input Impedance (with components mounted: test circuit 3)
@ Impedance including external components and evaluation board
• L02

• L01
CH15 11

1 UF5

~:48.9920

-2.78910

570.64 pF

g:
Cor

41.7870
-4.89650
300 MHz

35i~H

CH15 11

1 UF5

~:6.77640

699.98 pH

3.29860

Cor

!:

SOOMHz

i=

~~H
BOO MHz

CH2 5 11

log MAG

10 dBlREF 0 dB

1:

-30.473 dB

CH2 5 11

log MAG

1:

10 dBIREF 0 dB

100.000 000 MHz

Cor

1

I

21

-21713 dB
BOO MHz

~:

-3~~~

~

-15.42 dB
SOOMHz

2

-10.449 dB
BfOMHZ

I
I
I

L

I

5TART 100.000 000 MHz

I

5TOP 1 100.000 000 MHz

START 100.000 000

MHz

• Output impedance (with components mounted: test circuit 3)
@ Impedance Including external components and evaluation board

. RFout
CHI 5 11

1 UF5

.2;78.9530

-16.7620

9.9949pF

40.6090
41.3570
900 MHz
28.7760
-28.809 0
1 GHz
12.9790
-4.8784 0
1.IGHz

Cor

CH2 5 11

log MAG

10 dBIREF 0 dB

g:

-11.792 dB

9!j0.OOO OQO MHz

-J.~
Cor

~:

~

-7.JI63dB
900 MHz
-7.4

(j

dB
1 GHz

1.---

1-:~

~:

J
5TART 100.000 000 MHz

5-50

~

~

l

I

I

-2.3584 dB

750.00 000 MHz

3·

~:

~
1

27.3070
58.090
1.1 GHz

i~ -19~859dB
300 MHz
I

~-

7.61330
9.42090
BOO MHz
10.4510
22.7350
900 MHz

-4.5661 dB
1.1 GHz

I

STOP 1 100.000 000 MHz

~

~:

J

I

-3.Jog8dB
GHz

rI

5TOP 1 100.000 000 MHz

MB54609
• 1.5-GHz POC APPLICATION MEASUREMENT DATA (Reference Values)
• Measurement results
Parameter
Baseband input signal
Shifter input signal101
Mixer input signal lO2
Mixer output signal RFout

Return loss

Modulation precision
Carrier suppression

Test
circuit

Measurement
result

Unit

Condition

f88

42

kbps

rrl4 OQPSK, Root-Nyquist filter (a =0.5)

-

Vss

1.0

Vpp

Single-end input

-

flo 1

356

MHz

PLOl

-5

dBm

fl02

1619

MHz

PL02

-5

dBm

fRF

1441

MHz

fRF

PRF

-13.4

dBm

SSBvalue

1

3

Symbol

=fL02 + flO1/2

RlRF

-14

dB

=356 MHz
= 1619 MHz
fRF = 1441 MHz

AERR

1.6

%

RMS magnitude error

PERR

0.90

d~g.

RMS phase error

VERR

2.2

%

RMS vector error

-39.0

dBc

RUOl

-18

dB

Rll02

-6

dB

CS

-

-

III

flOl

fl02

-

2

2

• External circuit constants (with the IC mounted on the evaluation board)

GND

XQ
XQMOD
MB54609

QMOD
XI

GND

5-51

MB54609

• Modulation precision and output spectrum (test circuit 2)
@ Baseband signal: 7tl4 OQPSK, 42 kbps, 1.0 Vpp, PN 15, Root-Nyquist filter a.
Input signals: L01 = 356 MHz, ~ dBm; L02 = 1619 MHz, ~ dBm
Output signal: RFout 1441 MHz

=0.5

=

• Output spectrum

• Modulation precision

RMSVec:IOr
Eno, •
PelkV_
Error.
RMSIoIegnitude Error •
PeIk~Error.

RMSPhUe
......
_

Error.
Error.

c.
__
CantllrF,.q

0IIMt.
0IIMt.
•

llluV_
a-tIy Center

.(

2.243..

",. ~

4.li~

1.5eN
3.7_

I

O.lI02dog1
-1.977 dogI
-US...03Hz
7.417dog1

\
\

I

\

-33.001 cIS

1.83t.1.275~

{

• (-1.2115.0.133)"

J

\

:--. .,.""J

..........""-

CENTER", 1441 MHz
SPAN .. 200 kHz
RBW .. 3 kHz VBW .. 3 kHz SWP .. 100 ms AVG .. 128
An .. l0dB
REF .. -l0dBm 10dB/div.

VG: 7.00CJe.02VION

_lid Fifer: RtNyq (0.500) RecIar1gte Len. 54 OSR. 4.7811105

• Spectrum (test circuit 2)
@ Baseband signal: 7tl4 OQPSK, 42 kbps, 1.0 Vpp, 0000, Root-Nyquist filter a.
Input signals: L01 356 MHz, ~ dBm; L02 1619 MHz, -5 dBm
Output signal: RFout 1441 MHz

=

• Span

\

=

=

=26.2 kHz

• Span

=0.5

=500 MHz¥
::.E

Ole
.... co
~"'O

r-:Z::

::.Ee

f-- ....
"'0
~

"'0

<7

~

8~
....II

"'""'0

:!co

s-uco

~ cir--

-~

~"'"

co

r-;~
1-1

C:O-o
)

I \
I \

V

\

\ f

JU

~ ~ WI w

5-52

"'

\

~~. J.
W

CENTER = 1441 MHz
SPAN = 26.2 kHz
RBW = 300 Hz VBW = 100 Hz SWP = 4 s
An= 10dB
REF = -10 dBm 10 dB/div.

....al

I

!I

1

II

I

1

II II

I

.1.
CENTER = 1619 MHz
SPAN = 500 MHz
RBW = 1 MHz VBW = 1 kHz SWP
An = 10dB
REF -10 dBm 10 dB/div.
%

=3 s

MB54609

• RF output level dependent on baseband amplitude (PRF: test circuit 1, Modulation precision: test circuit 2)
@ Baseband signal of test circuit 2: 7tl4 OQPSK, 42 kbps, 1.0 Vpp, PN 15, Root-Nyquist filter (l 0.5
Input signals of test circuits 1 and 2: L01 356 MHz, -5 dBm; L02 1619 MHz, -5 dBm
Output signals of test circuits 1 and 2: RFout 1441 MHz

=

=

=

=

0

E
a:l

-10

~

~

a:

ffi

lI:

>

Cl.

1j!

g

-20

-

6

u.
a: -30

-

rn
4 ::!

w

~

i

>

0

a:

c:

·en0

~VERR

-40

-

2

.~

.

c.
c:
0

~

::J

0

0.1

10

"8

::!

Base band amplitude Vf18 (Vpp)

• RF output level dependent on L01 and L02 input levels (PRF: test circuit 1, Modulation precision: test circuit 2)
@ Baseband signal of test circuit 2: 7tl4 OQPSK, 42 kbps, 1.0 Vpp, PN 15, Root-Nyquist filter (l
Input signals of test circuits 1 and 2: L01 356 MHz, -5 dBm; L02 1619 MHz, -5 dBm
Output signals of test circuits 1 and 2: RFout = 1441 MHz

=

=

• RF output level dependent on L01 Input level
(@PL02 = -5 dBm)

~

>

~

a:

-101-

:>
g

¢:> PRF

6 w

~

-20

Q)

- 4 >

"S

.9::J
0

=

It

&
Qj

• RF output level dependent on L02 Input level
(@PL01 -5 dBm)

~
e...

01-

E
a:l

-30

u.

a:

rn

~
c>

VERR -

~
Cl.
Qj

>

~

-20 I-

"S

%
-30
0

-401-

·u

-20

0 c.
5 c:

----

g

¢:> PRF

a:

·en

~

:>

:2. -101-

c:
0

~

01-

E
a:l

::!

a:
2

6 ~

~
Q)

---

u.

c>

-40

VERR

- 4 >

rn

::!

a:

- 2

-10

-5

Shifter output level

PLOl

0
(dBm)

0

:;
"5
""0
0

::!

-20

c:

·en0

·u

~

~

-15

=0.5

-15

-10

Mixer input level

-5
PL02

0
(dBm)

5

0 c.
c:
.2
iii
"5
""0
0

::!

5-53

MB54609

• Input impedance (with components mounted: test circuit 3)
@ Impedance including external components and evaluation board

• L01
CHI S 11

• L02
1 UFS

-2.78910

.1:48.9920

570.64pF

Cor

CHI S 11

1 UFS

Cor

g;

15.6620
38.4450
1 GHz
60.7070

~

..!fW.~3

sr:.rdH~

1.4GHz

CH2 S 11

log MAG

10 dBlREF 0 dB

.!;

-30.473 dB

CH2 S 11

log MAG

-4:

10c&REFOdB

100.000 090 MHz

~~ -19~85'd8

.!~ -3.~8c11
lGHz

300 MHz

Cor

~:

I
.!:

1

~

I
I

~

I

i

I

I

I

START 100.000 000 MHz

-15.42 dB
SOOMHz

Cor

-.l
-10.449d8

1

BjlOMHZ
I
I

STOP 1 100.000 000 MHz

START 100.000 000 MHz

• Output impedance (with components mounted: test circuit 3)
@ Impedance including external components and evaluation board

.

RFout

CHI S'1

1 UFS

1.: 74.9180

21.884 pF

-5.04690

22.760

5f:flrH~

Cor

~

CH2 5

'1

log MAG

1:

10 dBIREF 0 dB

58.350
5.02930
1.48GHz
58.8440
42.4380
1.6GHz
-13.853 dB

1 441.000 000 MHz

.1~
Cor

-3.~5

dB
1.2GHz

1:

-20.927 dB
1.48GHz

\.V9.!:

-8.6101 dB
\6GHZ

7r" r""'-..6

~

I

I

I
START 100.000 000 MHz

5-54

I
I

STOP 2 100.000 000 MHz

-6.5383 dB

1 60(1.000 OQO MHz

2

3

" 1:

-4.~~

-:

-3.~~~

I
I

I
I

I

I

STOP 2 100.000 000 MHz

MB54609

• TEST CIRCUITS (Reference Examples)
• Test circuit 1
(for SSB measurement)

.. /f

8
D.U.T

Synchronized

1

:.

'tf

Spectrum analyzer (50 0)

8
VBB.1.0 Vpp
f .. 600kHz

• Test circuit 2
(for modulation precision
measurement)

Baseband
signal
generator

~

Modulation precision
analyzer (50 0)

____________________________________________________________

~~55

(Continued)

MB54609

(Continued)

• Test circuit 3 (for impedance measurement with components mounted)
Network analyzer (50 Q)

l

Vee .. 3.0 V

N.C.

Network analyzer (50 !l)
N.C.

• Test circuit 4 (for measurement of Impedance of only Ie)
Network analyzer
PORT-1

POry.!~~

Vee. 3.0 V (applied to PORT-2 internal bias tee)

Jr

Operation
RFout

GND
l02
1k
1k

XIF
IF
lO1

XQMOD
MB54609

QMOD
XI
1k

Xl01
GND
Vee

1k

J;.

Vos

= 1.6 V

GND
Vee

5-56 ____________________________________________________________
0.1 II ;+;.

~

MB54609
• ORDERING INFORMATION
Part number
MB54609PFV

I

Package

I

2o-pin Plastic SSOP
(FPT-20P-M03)

Remarks

5-57

MB54609

• PACKAGE DIMENSION
2o-pin Plastic SSOP
(FPT-20P-M03)

*: These dimensions do not include resin protrusion.

-r---;o..,...,.,=::;;.- (Mounting height)

0.15:::
.006':::)

5.85(.230IREF

@

5-58

1994 FUJITSU UMITED F20012S-2C-4

~ Oelaih~f;;;rt-

- - - - - - - -,

I

I

I
I

I
I

I

I

I
I

I
I

I
I

I
I

I

I

I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ JI

Dimensions in mm (inches)

Edition

o. 1 (94/Sept.l21)

== MB54619================--

OJ

FUJITSU

QUA ORA TURE MODULA TOR
(2.0GHz BAND UP CONVERTER BUlL TIN)
INTRODUCTION
MB54619 is a quadrature modulator Ie for IF modulation. The power consumption is as low as 25mA typo because of Fujitsu's
advanced technology. There is a 2.0GHz band up converter on chip that makes the MB54619 ideally suitable for high frequency mobile communications such as DEeT, peN, GSM and so on. The phase shifter is F/F type and allows a wide IF bandwidth
to be achieved.

FEATURES

II

• High performance transmit mixer
Output frequency : 2.0 GHz max.
Output level
: -14 dBm typo
• Quadrature modulator and transmit mixer have external pinouts
and allows for a BPF to be inserted between them.
Quadrature modulator output can drive a 50 n load.
• F/F type phase shifter allows wide IF band operation
Operating IF band : 100 MHz to 800 MHz
• Low power supply voltage

: Vcc

=2.7 V to 3.3 V

• Low supply current
Operating
: 25.0 rnA typo
Power down mode : 0.6 mA typo
• Operating temperature
• Package

: Ta

=-20°C to +75 °C

: Plastic SSOP 20-pin (FPT-20P-M03)

BLOCK DIAGRAM
Vcc

XI

GND

OMOD

IF

U-----1,,/

AFout

o
XO O-----1,J
PS

LO,

XL01

XOMD

XIF

L02

5-59

Edition 0.1 (941SepU21)

PIN ASSIGNMENT


AFoul
GND

20
2

PS

19

GND

L02

3

18

Q

GND

4

17

XO

XIF

5

16

XOMOD

IF

6

15

OMOD
XI

XL01

7

14

L01

8

13

GND

9

12

GND

10

11

Vee

Vee

PIN DESCRIPTION

.:.<

>J<

Ph; ~()~ ,..••':;..~. ~ •. ~~<~.>.

<\:>. . . . .... .
.> : ' : ) < •.. •.<.
:.::,;:;.. .....• . - . •...
.... ;...> :; :.' :. <};::::;}}

.>•..•.••••;;;....
I

::;::.::.~ ~~~:;;~ ~::::, ~;
..

••

..

- -

1

RFout

Up converter output

11

Vee

2

GND

Ground

12

GND

3

L02

Mixer LO input

13

I

4

GND

Ground

14

XI

5

XIF

Mixer IF complementary input

15

OMOD

6

IF

Mixer IF input

16

XOMOD

7

XL01

O-modulator LO complementary input

17

xa

Baseband complementary input (a)

8

L01

O-modulator LO input

18

a

Baseband input (0)

9

GND

Ground

19

GND

10

Vee

Power supply

20

PS

5-60

Power supply

Ground

Baseband input (I)
Baseband complementary input (I)
a-modulator IF output
a-modulator IF complementary output

Ground
Power down control

ELECTRICAL CHARACTERISTICS
..•...•..

-

Vcc

Power supply current

Icc

25.0

mA

DC current

Power down current

IccPS

0.6

mA

DC current

Shifter input
LO,

3.0

3.3

Operating band

flo!

100

800

MHz

Input level

PlOl

-15

o

dBm

DC

Baseband
input
L02

Operating band

fee

Input amplitude

Vee

1.2

Vpp

Mixer input
l02

Operating band

fl02

1900

MHz

Input level

Pl02

-5

dBm

Mixer output
RFout

Operating band

fRF

2000

Output level

Modulation
precision

PRF

MHz

MHz

fRF

=fl01/2 + fl02

dBm

-14

Amplitude error

AERR

Phase error

PERR

Vector error

VERR

3

CS

-30

Carrier suppression

=25·C

v

Power supply voltage

2.7

Ta

2

Q-MOD
& Mixer
direct
connection.
BB = 1Vpp

%

RMS value

deg.

RMS value

%

RMS value

dBc

External offset.
no offset adjustment

Note; flOl = 500MHz (-10dBm). fl02 = 1650MHz (-10dBm). fRF = 1900MHz output

5-61

Edition O. 1 (941SepU21)

PERIPHERAL CONNECTION EXAMPLE

RFout

GND

1650MHZ~

PS

GND

L02

o

GND

XO

XIF

XOMOD

t-- Baseband signal (0)
~-"""'V'v---~,,---JV'v-

1.6V offset

__- 1.6V offset

r---,,---, Connecllo

IF/XIF
directly or

IF
XL01

500MHZ~

OMOD
XI

via BPF

t--_--JIIV-__-

L01

GND

GND

Vee

Vce

Vee

5-62

1.6V offset

II

FPT-20P-M03
20-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-20P-M03)

.049~:~

---i~-""'-'-----

~ ~ ~~~~~~ i i ~
INDEX

(1.25~:~g)

1

"II

cI
L4i=i1i:::::;;::::~:::;:::;:;:::::;:;:::;~ ~

.252:.008
(6.40±0.20)

1

.213(5.40) NOM

*.173:.004

(4.40±0.10)

.0256:.0047
(0.65:0.12)

.11 .

(MOUNTING HEIGHT)

j

·A·~,-

.009~:~

(0.22~:6~)
Details of "A" part

.004:.004

.230(5.85)
REF

[JJI~·':~

OOto~

(STANDOFF
HEIGHT)

(0. 5O±0. 20j

*:This dimension does not include resin protruction.
©1991 FUJITSU LIMITED F2oo12S-2C

Dimensions in
inches (millimeters)

5-63

5-64

SECTION 6
Semi-Custom BiCMOS LSI RF Integrated Circuits - At a Glance
Fujitsu has an answer for those customers who wish to pursue a semi-custom solution tailored to their design needs for high volume, cost and size critical applications. Fujitsu's advanced Semi-Custom BiCMOS
LSI RF IC technology is an array-based methodology used to develop both custom devices and standard
devices. This means that many of the standard parts in the SuperPLL and Super Analog product lines have
equivalent macros already developed for implementation in a semi-<:ustom solution. This provides a low
risk integration path from discrete solutions using standard devices for prototyping or first generation designs to complete, highly integrated solutions. Please contact your nearest Fujitsu representative for further
details and engagement requirements.

Page
Number

Part
Number

6-3

MB1520

I

FRAME I

6-3

MB1530

I

FRAME II

6-3

MB1540

I

FRAME III

6-3

MB1550

I

FRAME IV

Series
Number

Frame Number

6-31

MB54500

II

FRAME I

6-45

MB54600

III

FRAME III

6-59

MB1560

IV

FRAME I

6-1

6-2

cP

Sept. 1995
Edition 3.0b
DATA SHEET

FUJITSU

MB1520lMB1530lMB1540lMB1550 SERIES
Bi-CMOS LSI RF IC SPECIFICATION
ADVANCED SEMICUSTOM TECHNOLOGY OF
SUPER PLL WITH RF SYSTEM ON LSI
The Fujitsu MB1520/1530/1540/1550 series are semicustom LSIIC's based on a
master slice method. Super PLL (PLL and Prescaler) macros and high frequency
analog macros, such as VCO's. IF amplifiers, RF amplifiers and mixers can be
realized on a single chip in accordance with customer requests. This is achieved by
means of predefined blocks (Super PLL's and analog macros) laid out on the
respective frames in a number of different combinations. The performance of each
block is custom specified.
The MB1520/1530/1540/1550 series makes it possible to compose single chip silicon
front ends for mobile communication systems. Due to the design process used,
development cycles and cost are greatly reduced over standard full custom LSI
designs, resulting in lower system cost solutions and reduced time-to-market.

Features
• Super PLL's as well as high frequency analog circuits, such as VCO's, mixers,
RF and IF amplifiers.

FPT-20P-M03

FPT-34P-M01

[PRINTING]
• Four available frame sizes, offering various combinations of Super PLL's and
analog macros.
• Choice of a wide variety of existing Super PLL's and analog functions, as well as
custom specifications of the same.

FPT-34P-M03

• Choice of power supply voltages between 2.7V and 5.5V. (Minimum 2.0V with
some restrictions available.)
• Available high speed lock up circuit for digital mobile communications such as
DECT, GSM, PDC, and so on.
• A number of standard features, such as power saving modes, phase shifter
circuit, analog switches, charge pumps, depending on the frame size.

FPT-48P-M04

• Development cycle is typically 14 weeks.

Application Examples
• MB 1520 series:

BS tuner, car navigation systems

• MB 1530 series:

MCA wireless for business use, analog cordless phones

• MB 1540 series:

Analog cellular phones, trunked radios

• MB1550 series:

Digital cellular and digital cordless phones

FPT-48P-M05

FPT-64P-M03
This devica contains circuitry to protect the inputs against damage
due to high static voHages or electric fields. However. ~ is advised
that normal precautions be taken to avoid application of any voHage
higher than maximum rated voltages to this high impedance circu~.

©1994 by FUJITSU LIMITED and Fuji1su Microelectronics. Inc.

6-3

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series

Bi-CMOS LSI RF IC SERIES
Master-slice methodology is that wafers of a particular frame are prefabricated as much as having finished diffusion processes, forming
the basic elements, such as transistors, resistors and capacitors. The remaining contact and wiring process steps then determine and
configure the function and value of each element according to cases.
This series is based on a master-slice method for which predefined blocks are laid out. Four series, MB 1520/153011540/1550 are available in accordance with combinations of the predefined blocks. (Please refer to "Chip Layout".) Table 1 shows representative blocks ani
features of each series.

Table 1. SERIES
Analog
Macro

Operating
Frequency
(max.)

SSOP

QFP

SQFP

1 circuit

2 circuits

2.4GHz

20-pin

2 circuits

2 circuits

4 circuits

1.9GHz

34-pin

-

-

MB1540

2 circuits

2 circuits

6 circuits

2.4GHz

48-pin

3 circuits·

3 circuits

8 circuits

2.4GHz

-

48-pin

MB1550

48-pin

64-pin

Series
Name

Prescaler

MB1520

1 circuit

MB1530

* 1 Prescaler or 90° phase shifter

6-4

PLL

Package

MB 1520 Series
MB1530 Series
MB1540 Series
MB1550 Series

CHIP LAYOUT
1 Prescaler
1 PLL
2 Analog Macros

[Q] I Analog
Charge Pump
[Q]
Switch

[Q][Q]

MB1520 Series

!

~B

[Q]

[Q]

Macro

[Q]

~B

o
[Q]
[Q]
[Q]
[Q]

[Q]

PLL

[Q]

Analog
Macro

I

Praacaler
Analog
Interface

[gJ

I

[Q]
_

~B

2 Pres caler
2PLL
4 Analog Macros

[g]
[Q]
[g]

[QJ
[Q]

[Q] [Q] [g]

[Q]
MB1530 Series

III

[Q]

EJ
Analog
Macro

[g] [g] [Q] [g] [g] [g] [Q] [Q] [g]

I

II

Analog
Macro

[g]

-

~ 1=1 ~.

AnalopPrescaler
Interface
Prescaler
2

[g]

U
~
[g]

I

Analog
Macro

[Q]
f[jl

~

[Q]
.----

[Q]

Charge
Pump
Analog
Switch

AnalogPrescaier
In,erface

[Q]
[Q]

g
g

I
[g]
[g]

[g]

PLL2

1--------------------/
PLl1

[g]

[g] [QJ [g] [Q] [g] [Q]

[g]
6-5

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series

CHIP LAYOUT (Continued)
MB1540 Series
2 Prescaler
2PLL
6 Analog Macros

[Q] [QJ [Q]

[Q] [Q] [Q]

[QJ [QJ [Q]

~I ~~Iog~

[Q]
[Q]
[Q]
[Q]
[Q]
[Q]
[Q]
[Q]
[Q]
[Q]

Switch

[QJ [QJ

[Q]

rQ]

I

p~=r IIl

II

Prescaler
1
I

" II

Clilerc$\u·

Interface

[Q]

P~: II c::~
~~~
Interface

[Q]

[Q]

~~'o:

Analog

Macro

1---1

2 Prescaler
3PLL
8 Analog Macros
1 Prescaler or
90° phase shifter

[Q]
PlL2

Analog

Plll

Macro

Analog

[Q]

Macro

[Q]
[Q]

[Q]

Analog

Analog

Macro

Macro

[Q] [Q][Q]

[Q]

[Q] [Q]

[Q]

101010101 [Q] 1010110101

[Q]~ GEJ~[Q]
~ [Q]
[Q]
[Q] I c::~~ I , - - - - - , , - - - - - - , I C:~~ I[Q]
[Q]
[Q] ~
[Q]

Prescaler

Prescaler

2

1

[Q]

~

[Q]

Analog-

Pll1
EJalog

Macro

PlL2

[Q]

1:11
[J
El
[Q]

[Q]

~[J1og
[Q]

~======~

Macro

[Q]

II = IE]
~

[Q]

Prescaler

[Q]

IF Prescaler or
FIR phase shifter

Pll3

alog

Macro

Analog

Macro

Macro

[Q]

[Q]

[QJ
[Q]

[Q]

Analog

Macro

Analog

lololo\olc\o\olo\o\olol
6-6

[Q]
[Q]

I---I[Q]

[Q]

MB1550 Series

~

[Q]
[Q]

=10=10=10=\C='1=0=10=10=10:11

[QJ
[QJ
[QJ
[QJ

--------------------------------------------------------------~

MB1520
MB1530
MB1540
MB1550

Series
Series
Series
Series

CHIP LAYOUT (Continued)
Analog Cell
Re.istor Array Area

~

Capacitor Arrey Area

Translator Array Area

~t
I
BIeaArea
Rellator
Arrey
Area

Ground Capacitor
Group
(l20pFmax)

Capacftor Array Area

Resistor Array Area

Transistor Array Area

I-Realator Array Area

6-7

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series

ABSOLUTE MAXIMUM RATINGS
Parameter

(Reference voltage is GND.)
Value

Unit

Power Supply Voltage

Vee

Symbol

-O.Sto +7.0

V

Input Voltage

VIN

-0.5 to Vee +0.5

V

Output Voltage

lOUT

±10

mA

Ambient Temperature

TSTG

-50 to +125

°C

NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should
be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS
Parameter

Power Supply Voltage
Ambient Temperature

Symbol
Vee

Value

Min.

Unit
Max.

5.5

V

+85

°C

V

0
-40

* The minimum operating voltage is at 2.0V, but some restriction may be required.

6-8

Typ.

2.7*

GND
TA

(Reference voltage is GND.)

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series

MACRO CELLS DESCRIPTIONS
1. Super PLL (PLL and Prescaler)

I
I
I

2
Oscillator
Circuit

5

~------~

L_-

T

- __,

I
~____
I __~
Shift Register
& Latch

I
I

L_

~3~__~__~

Phase

Detector

1.1 Functional Descriptions

1.

2.

3.

4.

In designing "super PLL block", some functions may be restricted depending on kind of series (MB1520/1530/1540/1550).
Availability of main functions is summarized in Table 2.
Phase comparator
Phase difference detection range is -23t (pi) to +2n: (pi). In order to minimize the dead zone area, the phase comparator is
deSigned to deliver a minimum signal to the charge pump even when the phase difference is zero. Also, it is possible to choose
the characteristics of the phase comparator to meet polarity of veo.
Counter (Reference Counter and Programmable Counter)
Two types of counters are available for PLL 1 and PLL2 of aI/ series
: programmable and fixed
: Fixed
Regarding Pll3, one type of counter is available
Charge pump
All charge pumps are based on bipolar technology. Their voltage levels at "H" depend on the power supply voltage chosen. It is
possible to optimize charge pump characteristics individually according to customer needs.
High speed lock up circuit
This circuit is an option to further increase the lock up time ofthe Pll, and is available for PLL 1 and PLl2 (except PlL3). It
will mainly be required in the new emerging digital communication standards.
Prescaler
Divide ratio can be chosen freely, so can two modulus type and fixed type. However, regarding PlL3, only fixed type is available
and the divide ratio can be chosen from 1/2, 1/4, and 1/8.

6-9

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series
Table 2. SUPER PLL FUNCTION TABLE

MB1520
MB1530
MBl540

MB1550

Prescaler

Programmable
Counter

Reference
Counter

High Speed
Lock Up
Function

Power
Save

PLLl

T

P/F

P/F

X

X

PLL1

T

P/F

X

X

P/F*

Mode

-

-

X

X

P/F

-

X

P/F

X

X

P/F

P/F

X

X

F

F

-

X

PLL2

T

P/F

PLLl

T

P/F

P/F

PLL2

T

P/F

PLL1

T

P/F

PLL2

T

PLL3

S

NOTE: T: Two Modulus S: Single Modulus (1/2, 114, or 1/8) P/F: Programmable or Fixed F: Fixed X: Available
*: Common for PLL1 and 2

5. Analog switch
This switch is controlled by the LE signal. When LE is at MW, the analog switch is closed (ON). In this mode, the charge pump
output (Do) is fed in parallel to the pin BS. This decreases the time constant of the loop filter and reduces the charge pump load.
The result is an increased lock up speed.
Analog Switch

I ________,
L

,

(Control Signal LE)

I
I

---------------------~

6-10

BS

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series
6.

Intermittent operation control circuit
The intermittent operation reduces the power consumption by powering down or waking up parts of the PLL circuitry. All the
transmission, the reception and IF block PLL may be controlled by this circuit.
If a PLL is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase
relation between the reference frequency (fn) and the comparison frequency (fp) and may in the worst case take longer time for
lock up of the loop.
To prevent this, the intermittent operation control circuit forces a limited error signal output of the phase detector during power up,
thus keeping the loop locked.
The circuit can be controlled externally or internally, depending on customer requirements. If controlled externally, the circuit is
activated by an external signal to the PS pin. If controlled internally, the intermittent control circuit follows the power state set by
the analog cells. When the power supply for the analog cells is shut down, the stand by state is automatically selected. When the
analog cells are supplied with power, the active state is selected.
The charge pump output is in a high impedance state during stand by, so that the veo control voltage is being clamped at the
active state level.
Ouring the stand by state, the latches store the data which they hold at the time of power down. The shift register data, on the
contrary, may be renewed during stand by.
NOTE: Powering up for the digital blocks (VCCRD, VCCTD), (after they are disconnected) has to be done in stand by rnode.

Table 3. STANDARD STAND BY STATE OF PLL BLOCK
Circuit State

Rx

Tx

IF

Active Mode

Stand By Mode

Reception circuits

X

PO

Oscillator circuit

X

X*

Reference counter

X

-

Transmission circuits

X

PO

Oscillator circuit

X

X

Reference counter

X

-

IF circuits

X

PO

Oscillator circuit

X

X

Reference counter

X

-

NOTE: X: Active state PO: Power down mode -: Stop working
*: Oscillator circuit can be stopped in accordance with PK's PO signal.

6-11

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series
7.

Lock detector circuit
LD output is selected by setting the "r bit. (See 1.2 Serial data format.)
When the phase difference is equal or higher than tw (see diagram below), LD goes into "L". When the phase 'ifference is tw or
less and continues to be so for three cycles or more, the LD goes into "H". For example, in case of a 12.8MHz oscillator frequency
tw, is 625ns to 1250ns. The relation between LD and PLL circuit is shown in Table 4.
Lock Detection

fp

..

: ,...
I

LD

I

tw

.

""
""

:.-

...:;.-

I

~

tw

-------

""
""

I

tw

-------

twl

Table 4. RELATIONSHIP BETWEEN LD SIGNAL AND THE CIRCUIT STATE
Operation Mode

PLL circuit

LD Output

Stand-by

L

Stand-by
Active

Unlock

L

Lock

H

1.2 Serial Data Format
The PLL operation is controlled by serial data inputs. The parameters of the serial data are shown below. The data input starts
with the MSB bit. The data length may vary between 22 and 37 bits. The actual data format is being worked out with the customer.

Table 5. SERIAL DATA FORMAT
Function

Typical Bit Number

Control Bit (CNT bit)

Selects direction of data transfer (Rx or Tx)

1 to 2

LD Select Bit (T bit)

Selects the LD output

1 to 2

Fe Bit (F bit)

Switches phase of the comparator

1

Programmable Counter Bit (N bit)

Sets programmable counter's divide ratio

11

Swallow Counter Bit (A bit)

Sets swallow counter's divide ratio

7

Name

Reference Counter Bit (R bit)

6-12

I

Fixed

I Programmable

Sets reference counter's divide ratio

1 to 2

Sets reference counter's divide ratio

14

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series
1.3 Serial Data Input Timing
Binary data is entered using the Data, Clock, and LE pins. The serial data separately controls the programmable reference
divider as well as the programmable divider.
Each data bit is shifted into the internal shift register at the rising edge of each clock pulse. When the LE pin is "H", stored data is
transferred from the shift register into the latch, chosen by the control bit. A schmitt trigger at each input improves noise immunity.
NOTE: 1. One clock pulse always shifts one data bit into the shift register, even during stand by state.
2. Input voltages (Data, Clock, and LE pins) should always be lower than Vcc.

Serial Data Input Timing
-------------~ ~
T~ V
CNT

Data

Clock

T1 I\.
(LSB)
-------------~ ~

JLJLUL-----------JLfL
,
,I.,. . IL
'

LE

---"--,-- - - - - - - - - - - - -

,

004...

,
...
,

Data set up time (~ 1 Ilsec)
Data hold time (~ 1 Ilsec)
Clock pulse width (~ 1 J.1Sec)
LE set up time to the rising edge of the last clock
LE pulse width (~ 1 Ilsec)

,

4

.

~t5
,

t1 --"-'"
t1:
t2:
t3:
t4:
t5:

---'--'--~-----i

'---11:-":
, ,

: ..:---.,..... t2

(~

1 Ilsec)

Notes: 1. One bit of data is shifted into the shift register on the rising edge of the clock (edge trigger).
2. Data in the shift register is transferred to the latch when LE becomes H.

6-13

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series
2. Mixer, IF Amplifier
Some basic examples for achievable circuits are shown below. However, conceming circuitry and performance, it is possible to configu
each analog macro cell to customer requirements.

2.1 Basic Construction
Mixer circuit can either be of DBM (Doubled Balanced Mixer) or SBM (Single Balanced Mixer) type. LO and RF inputs can be
connected with the intemal bias circuit, if necessary. The mixer output is connected with its own power supply (VMIX) via a load
resistor, then connected with the following IF amplifier.
The IF amplifier consists of a differential amplifier and NPN transistor, which forms the emitter follower output.
Basic Equivalent Circuit (1)
~

loiN

Mixer

IF Amplifier - - .

<>-......- - [
Mix Out

loiN o--t----~--~

RFIN <>------1'
RFIN

0------+-------+----'
GND

Basic Equivalent Circuit (2)

loiN

Mix Out
to BIAS ....-

----+---.. . .

......

GND

6-14

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series
3. RF Amplifier
3.1 Basic Construction
The output signal from the common emitter circuit will be supplied though an emitter follower.
Basic Equivalent Circuit

RFoUT

GND

4. VCO
4.1 Basic Construction
The veo circuit consists of an output buffer transistor and an oscillation transistor, which construct a base grounded colpitts
circuit. Resonator and varicap can't be integrated in the chip, so they need to be connected extemally.
Basic Equivalent Circuit

VCCA

e
B

veOOUT

E

GND

6-15

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series

EXAMPLES OF AN ANALOG CIRCUIT'S BASIC CHARACTERISTICS

veo
Value

Parameter
Min.
Supply Voltage

Typ.

4.5

Unit
5.5

6

Current Consumption
Operating Frequency

V
mA

400

MHz

CIN

70

dB

SIN

50

dB

Output Power

-5

dBm

3

MHzIV

Mod Sense

Conditions

Max.

Offset frequency = 25kHz, BW = 15kHz

Mixer
Value

Parameter
Min.
Supply Voltage

Typ.

4.5

Unit
5.5

6

Current Consumption

Conditions

Max.
V
mA

Gain

13

dB

Maximum Output Power

-5

dBm

1 dB Compresssion Point

-10

dBm

Output level

Intercept Point

-16

dBm

Input level

Noise Figure

10

dB

RF-Lo Isolation

20

dB

DSB measurement

Amplifier
Value
Parameter
Min.
Supply Voltage

Typ.

4.5

Unit

Conditions

Max.
5.5

V

Current Consumption

6

mA
MHz

Operating Frequency

400

Gain

20

dB

Maximum Output Power

-3

dBm

f=400MHz

1 dB Compresssion Point

-10

dBm

f = 400MHz, Output level

Intercept Point

-19

dBm

3

dB

Noise Figure

6-16

f = 400MHz (small signal input)

f = 400MHz, 400.1 MHz, Input level
f=400MHz

MB1520
MB1530
MB1540
MB1550

Series
Series
Series
Series

MB1540 APPLICATION CIRCUIT EXAMPLE
To Transmission Mixer 800M Hz

To Reception
Mixer, 800MHz

Reception
Block

Data ...
Clock ...

LE

Transmission
Block

...

ToLD

To Transmission
Output, 700MHz

6-17

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series

DEVELOPMENT PROCEDURE
1. Study about product development
(1) The customer submits technical and commercial requests to Fujitsu. Fujitsu reviews the customer requirements, if necessary
simulation is done.
[Technical request]
Function:
Functional descriptional material, 1/0 signal descriptional material, Block diagram, etc.
Specifications:
Prescaler, PLL, VCO, Mixer, Amplifier, etc.
[Commercial request]
Delivery and price: Development schedule, development aSSignment plan, demand, NRE, target price, etc.
(2) Fujitsu submits a counter proposal. And the final target specification evolves from the discussions about proposaVcounter
proposals between the customer and Fujitsu.
(3) Detailed circuit and test specifications are studied. Then all of the specifications are decided. After that development schedule,
NRE, quotation are estimated formally.
(4) After the customer and Fujitsu agree to develop the device, the final specification (data sheet) is submitted to the customer to
confirm the specification.

CUSTOMER

FUJITSU

Submit technical and commerical
requests

Study the customer requests

(3)

All specifications decided

NRE and price decided

The final target data sheet

6-18

MB1520
MB1530
MB1540
MB1550

Series
Series
Series
Series

2. Development of Ie
(1) Design and layout of the chip starts. First engineering samples become available approximately 14 weeks after the final target
data sheet is issued.
(2) ES is evaluated by the customer and Fujitsu.
(3) The final specification sheet of finished product is submitted to the customer from Fujitsu when the customer is satisfied with
evaluation result. Then, preparation for mass production is started. Typically 3 months are necessary for the first shipment from
when the final specification sheet (for finished products) is issued.

CUSTOMER

FUJITSU

The final target data sheet

(1)

Design and layout

ES
About 14 weeks

ES evalution

III

(2)

(3)

About 3 months

1

Development finish, start
preparation for MP

6-19

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series

TARGET SPECIFICATION BLANK
MB1520 Series
Parameter

Power Supply Current

Typ.

Max.

Unit

Note

ICCD

mA

Digital section
Analog section

ICCA

mA
V

Digital section (PLL, Prescaler)

VCCA

V

Analog section (VeO)

Operating Frequency
Range

fveo

MHz

Output Power

POUT

dBm

CIN Ratio

CIN

dB

Detuning l:!.. f :_ _ _kHz
Bandwidth: _ _ _kHz

SIN Ratio

SIN

dB

Reference deviation:_ _ _kHz/dev
Bandwidth: _ _ _ kHz to _ _ _kHz

Mod Sense

6·20

Request Value
Min.

Vcco

Power Supply Voltage

veo

Symbol

l:!.. fveo

MHzIV Control voltage V-r. _ _ _ to_ _ _V

Operating Frequency
Range

fAMP

MHz

Gain

Gain

dB

RF-Amp Noise Figure
Intercept Point

NF

dB

IP3

dBm

Input level

1 dB Compression Point

CP

dBm

Output level

In-out Isolation

Iso

dB

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series
MB1520 Series (Continued)
Parameter

Operating Frequency
Gain
Mixer

PLL

Noise Figure

Symbol

Request Value
Min.

Typ. Max.

Note

Unit

fRF

MHz

flO

MHz

flF

MHz

GAIN

dB

NF

dB

Output frequency

Measurement method; SSB or DSB
measurement value

Intercept Point

IP3

dBm

Input level

1 dB Compression Point

CP

dBm

Output level

LO-RF Isolation

Iso

dB

fosc

MHz

Oscillation Frequency
Lock-up Time

TlR

ms

Comparison frequency: fr =___kHz
Step frequency: .1.f =___kHz

Memo:

* If you have any questions, please fill in the above "Memo· column.

Customer name:
Application:
ES request day:
CS request day:
Planning quantity:

6-21

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series

TARGET SPECIFICATION BLANK
MB1530IMB1540 Series
Parameter

Request Value
Min.

Typ.

Max.

Unit

Note

ICCR

rnA

Reception section

ICCT

rnA

Transmission section

VCCD

V

Digital section (PLL, Prescaler)

VCCA

V

Analog section (VCO)

Operating Frequency
Range

fvco

MHz

Output Power

POUT

dBm

TX·VCO C/N Ratio

C/N

dB

Detuning a f :_ _ _kHz
Bandwidth: _ _ _kHz

SIN Ratio

SIN

dB

Reference deviation: _ _ _kHzldev
Bandwidth: _ _ _kHz to _ _ _kHz

Power Supply Current

Power Supply Voltage

Mod Sense

afvco

MHzIV Control voltage Vl'-_ _ _ to_ _ _V

Operating Frequency
Range

fvco

MHz

Output Power

POUT

dBm

RX-VCO C/N Ratio

C/N

dB

Detuning a f :_ _ _kHz
Bandwidth: _ _ _kHz

SIN Ratio

SIN

dB

Reference deviation: _ _ _kHzldev
Bandwidth: _ _ _kHz to _ _ _kHz

Mod Sense

RF-Amp

6-22

Symbol

afvco

MHzIV Control voltage Vl'-_ _ _ to_ _ _V

Operating Frequency
Range

fAMP

MHz

Gain

Gain

dB

Noise Figure

NF

dB

Intercept Point

IP3

dBm

Input level

1 dB Compression
Point

CP

dBm

Output level

In-out Isolation

Iso

dB

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series
MB1530/MB1540 Series (Continued)
Request Value
Parameter

Symbol
Min.
fRF

MHz
MHz

flF

MHz

GAIN

dB

Noise Figure

NF

dB

Intercept Point

IP3

dBm

Input level

1 dB Compression
Point

CP

dBm

Output level

Gain

LO-RF Isolation
Oscillation Frequency
PLL

Note

Unit

flO

Operating Frequency

Mixer

Typ. Max.

Lock-up Time

Output frequency

Measurement method; SSB or DSB
measurement value

Iso

dB

fosc

MHz

TlR

ms

Reception

TlT

ms

Transmission

Memo:

Comparison frequency: fr = ___kHz

ILaf=
Step frequency;
_ _kHz

II

• If you have any questions, please fill in the above "Memo" column.
Customer name:

Application:
ES request day:
CS request day:

Planning quantity:

6-23

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series

PACKAGE DIMENSIONS
MB1520 Series
2D-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-20P-M03)
(MOUNTING
HEIGHT)

.0256±.0047
(0.65tO.12)

.11 ~

+·004

.009 -.002

(O.22~:Jg)

~
REF

*:This dimension does not include
resin protrusion.
©1991 FUJITSU LIMITED F20012S-2C

6-24

(STANDOFF
HEIGHT)

MB1520
MB1530
MB1540
MB1550

Series
Series
Series
Series

PACKAGE DIMENSIONS (Continued)
MB1530 Series
34-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-34P-M01)

.402±.016
(10.2O±O.4O)

.3621:.012

(9.20±0.3O)

==+-~
11-:"""

• .. (0. 15±O.05)

r

·A"

II
I
I
I
I
I
I

-O;-aU;-o~;p;.n

.006(0.20)

-,

II

I
I
.024(0.60) I
.007(0.18) I
MAX
I
.025(0.63)
I

L _ _ _ ~~_...J

©1991 FUJITSU LIMITED F34001S-3C

Dimensions in
inches (millimeters)

6-25

MB1520 Series
MB1530 Series
MB1540 Series
MB1550 Series

PACKAGE DIMENSIONS (Continued)
MB1530 Series
34-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-34P-M03)
34 pin Plastic SSOP
(FPT-34P-M03)
·".OIhO.10!.433t.00f!

* : This dimension does not include resin protraction.
....,.._...,.-;-1;.::.2=S!"".::
••~ (MOUNTING HEIGHn

!!.Of!it::)

L.....-iOIO.l0(.O5<:>:.<::·

:·:>. .• <,

.:< . :.:. •.

Min~:TYp,::

. .•. •. : .:.

.. }i .

> ......:•.. . } :
.

:..::

...

:::.

:

Supply Voltage

.linn.

<. . . : . .: :. :":.;;,, ...: :. .:::'::::'..' '::.>::'......:. <.:::::.::
•.•.
<::.:::,:,::>.::::.<:.:
.~

..

.>:,::}.::
·:::)y'P~ .. :./:

I><:~

I··

4.5

::<:.::.::

<:Max.
5.5

/

.: ...•.:::

::.:.'::.:':..:.::::':
1:<::li;i·~

•. :.

':.:i:.:::::>::.:.::: :>/:.

":.'

:",. ,,;:;", • , .. ':.-: ,:::

.::>\.......

..'.

,> ....::::

::>::-:.:::

I',•• :::

·;:::::{·.<.·or:·.

):: 1:::7 Ir .:::·i~*~:)

.";'

Supply Voltage

5.5

4.5

I:.IJ~~/:::·
I::>:::::,

""':;:';:

'..,;,;:

'i>::::

':.':

:?

'::::·::::••. !.·:i::···i·j:·....iil....·::iii.i·:•

··:::·.:Ts;;jj

-"j

:;-::./::r;:

:<::
::"::.'.:: :'.';:::::){

:..

V

Current Consumption

6

mA

Operating Frequency

400

MHz

Gain

20

dB

Maximum Output Power

-3

dBm

f- 400MHz

1dB Compression Point

-10

dBm

f - 400MHz, Output level

Intercept Point

-19

dBm

f - 400MHz, 400.1 MHz, Input level

Noise Figure

3

dB

f - 400MHz (-3OdBm in)

f .. 400MHz (-3OdBm in)

6-35

MB54500 SERIES

BASIC EQUIVALENT CIRCUIT OF ANALOG CIRCUITS
1.Mlxer and IF amplifier
The mixer is a DBM (Double-Balanced Mixer) of active type. LO and RF inputs can be connected with internal
bias circuit. The mixer output is connected with its own power supply (VMIX) via a load resistor, then connected
with next IF amplifier.
The IF amplifier consists of a differential amplifier and NPN transistors, and the differential amplifier's ouput is
output through an emitter follower.

.-

Mixer

IF Amplifier ----.
VMIX

LOIN

Mix Out

LOIN
RFIN
RFIN

GND

2.RF Amplifier
Output signal from common emitter circuit is output through emitter follower. It is possible to connect RF input with
internal bias circuit.

VAMP

RFIN

RFoUT

GND

6-36

MB54500 SERIES

3.

veo

The VCO consists of an output buffer's transistor and an oscillation's transistor which constructs a base
grounded colpitts circuit. Resonator, varicap and so on are connected externally.

Vvco
C

B

VCOour

E

----~--------------~-4--GND

6-37

MB54500 SERIES

DEVELOPMENT PROCEDURE
1.Examination about product development
(1 )Examination about specifications, and development conditions.
A customer submit target specifications of his idea to Fujitsu. Fujitsu reviews the specifications to judge technological feasibility. by means of simulation if necessay. and cost estimation.
[Products Information]
Functional Information
Specificational information

: Functional descriptional material, 1/0 signal descriptional material. Block diagram. etc.
: Prescaler. PLL. VCO. Mixer. Amplifier, etc.

[Development Information]
Delivery related Information
: Development schedule. development assignment plan. etc.
Ouotation related information : Demand. NRE. target price. etc.

(2)Examination about product development
Fujitsu and the customer examine go/no-go of the product develpment in together. based on result of the review.

(3) Examination about product development
Circuits' functions and charateristics are examined in detail so that detailed specifications and test specifications
are examined. After the specification is finalized. development schedule. NRE. formal quotation are done.

(4)Confirmation of the final specification (data sheet)
After the customer and Fujitsu agree to develop the device. the final specification (data sheet) is submitted to
the customer to confirm the specifications.
CUSTOMER

FUJITSU

(1 )
Information about quotation & specifications.
Schedule. target specs. demand. target price. etc.

r--_ _ _ _ _ _ _ _ _ _--,(3)

(4)

6-38

Studies the request of quotation
Studies the feasibility of the
specification

MB54500 SERIES

2.Development of

Ie

(1)/C designing and manufacturing by way of trial
Fujitsu designs the device and manufacture it by way of trial based on the final specifications. It takes about 12
weeks (typ.) from when the final specification sheet is issued to when the first ES (Engineering Sample) are
manufactured.

(2)Evaluation of ES
ES is evaluated by both the customer and Fujitsu based on the final specifications.

(3)The final confirmation
A specification sheet of finished product is submitted to the customer from Fujitsu when the customer
satisfied with evaluation result. so that preparation for mass production is started by Fujitsu. Typically 3 months are
necessary for the first shipment from when the specification sheet (for finished products) is issued.

CUSTOMER

FUJITSU

The final specifications (data sheet)

(1 )

IC designing

About 12 weeks

Price quotation. development schedule

No good

(2)

(3)

1
About 3 months

Development finish. start preparation for MP

6-39

MB54500 SERIES

APPLICATION CIRCUIT EXAMPLE

Pll frequency synthesizer
MB1sXX series.

LPF
Do

veo

~

fin

~----------------

Vee

.

..

I~---r-+---

RFin

RF

J----r-+----IF
GND

~----------------------'

6-40

Local

MB54500 SERIES

PACKAGE DIMENSIONS
8-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-8P-M01)

+.010
.250-.008

.089(2.25) MAX
(MOUNTING HEIGHT)
.002(0.05) MIN
(STAND OFF HEIGHT)
~I,-+--.-

INDEX

cf
.050( 1.27) ,
TYP

r--------,

I
"A·

I

.008(0.20) II

I
I
I
I
I
I

I
I
I
.020(0.50) I

I

IL
©1991 FUJITSU LIMITED F08002S-4C

Details ot "A· part

II

.007(0.18)
MAX
.027(0.68)

MAX
_____
___

I
I
I
JI
Dimensions in
inches (millimeters)

6-41

MB54500 SERIES

PACKAGE DIMENSIONS (Continued)
8-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-8P-M03)

I~
~ 13'~~'~ ~ I

I

.205(5.20)

NOM
. 165±.004
(4.2O±O.10)

INDEX

~
.0315(0.80l

I I II

TYp.

014+004

••

(~.3~.10)1.10.004(0.10)81

J

.244±.008

.A........ __ ".

l 'G'T20)

II.

2
~~ .. _ .006_+• 00
00 1

(015+0.05)
. -:'·'·>:·

.;..~ r~,.?: ?<::·I<:::~~~-·:>'::;:<:

2.7

Supply Voltage

3.0

3.3

...

v

15

mA

RF

800

MHz

Lo

110

MHz

IF

910

MHz

7

dB

Maximum Output Power

-9

dBm

1dB Compression Point

-12

dBm

Output level

Intercept Point

-9

dBm

Input level

Noise Figure

11

dB

DSB output

RF-lo Isolation

20

dB

Current Consumption

Operating
Frequency

Gain

•

fRF + flo = flF

6-49

MB54600 SERIES

3.Amplifier

Supply Voltage

2.7

3.0

3.3

V

Current Consumption

7.5

mA

Operating Frequency

900

MHz

Gain

13

dB

Maximum Output Power

f • 900MHz (-3OdBm in)

dBm

f- 900MHz

f - 900MHz, 900.1 MHz, Input level

1dBCom

6-50

Intercept Point

-9

dBm

Noise Figure

2.5

dB

f.900MHz

MB54600 SERIES

BASIC EQUIVALENT CIRCUIT OF ANALOG CIRCUITS
1.Mlxer and IF amplifier
The mixer is a DBM (Double-Balanced Mixer) of active type. LO and RF inputs can be connected with internal
bias circuit. The mixer output is connected with its own power supply (VIotIX) via a load resistor, then connected
with next IF amplifier.
The IF amplifier consists of a differential amplifier and NPN transistors, and the differential amplifier's ouput is
output through an emitter follower.
~

Mixer

IF Amplifier ~

2.RF Amplifier
Output signal from common emitter circuit is output through emitter follower. It is possible to connect RF input with
internal bias circuit.

VAMP

RFIN

RFOUT

GND

6-51

MB54600 SERIES

3.

veo

The VCO consists of an output buffer's transistor and an oscillation's transistor which constructs a base
grounded colpitts circuit. Resonator, varicap and so on are connected externally.

Vvco

C
B

VCOoUT

E

----~--------------~~--GND

6-52

MB54600 SERIES

DEVELOPMENT PROCEDURE
1.Examination about product development
(1)Examination about specifications, and development conditions.
A customer submit target specifications of his idea to Fujitsu. Fujitsu reviews the specifications to judge technological feasibility, by means of simulation if necessay, and cost estimation.
[Products Information]
Functional Information
Specificational information

: Functional descriptional material, 110 signal descriptiona[ material, Block diagram, etc.
: Prescaler, PLL, VCO, Mixer, Amplifier, etc.

[Development Information]
Delivery related Information
: Development schedule, development assignment plan, etc.
Quotation related information : Demand, NRE, target price, etc.

(2)Examination about product development
Fujitsu and the customer examine go/no-go of the product develpment in together, based on resuft of the review.

(3) Examination about product development
Circuits' functions and charateristics are examined in detail so that detailed specifications and test specifications
are examined. After the specification is finalized, development schedule, NRE, formal quotation are done.

(4}Confirmation of the final specification (data sheet)
After the customer and Fujitsu agree to develop the device, the final specification (data sheet) is submitted to
the customer to confirm the specifications.
FUJITSU

CUSTOMER

(1 )
Information about quotation & specifications.
Schedule, target specs, demand, target price, etc.

Studies the request of quotation
Studies the feasibility of the
specification

--.(3)

,....-_ _ _-.L-_ _ _ _

(4)

6-53

MB54600 SERIES

2.Development of Ie
(1 )Ie designing and manufacturing by way of trial
Fujitsu designs the device and manufacture it by way of trial based on the final specifications. It takes about 12
weeks (typ.) from when the final specification sheet is issued to when the first ES (Engineering Sample) are
manufactured.

(2) Evaluation of ES
ES is evaluated by both the customer and Fujitsu based on the final specifications.

(3)The final confirmation
A specification sheet of finished product is submitted to the customer from Fujitsu when the customer
satisfied with evaluation result. so that preparation for mass production is started by Fujitsu. Typically 3 months are
necessary for the first shipment from when the specification sheet (for finished products) is iSSUed.

CUSTOMER

FUJITSU

The final specifications (data sheet)

(1 )

IC designing

About 12 weeks

Price quotation. development schedule

No good

(2)

(3)

1
About 3 months

Development finish. start preparation for MP

6-54

MB54600 SERIES

APPLICATION CIRCUIT EXAMPLE

I'

I'

Vcc1

GND1

_______ l ________________ l ________ .
I

I

,

,

Lo1

Phase Shifter

1

I
Q
Q

____________ . . . . _ . - - - - - - J

Buffer AMP

+
RFout _-+--....I..----l

AMP

t
MIX

14-~-+-- Lo2

. - - - - - -, - - - - -- - - - -- - - - - - - - - -1- - - - - - -

6-55

MB54600 SERIES

PACKAGE DIMENSIONS
2D-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-20P-M03)

.049~:~:

--+--~---- (MOUNTING HEIGHT)

~ ~ ~~~~~ i ~ ~
INDEX

(1.25:g:~)

1I.

I

I

25 2±.OO8
(S.4O±O.20)

cI
14;::;1;=;:;::;:;:::;:;:::;:;::::;:;:::~ ~

.213(5.40) NOM

*.173±.OO4
(4.40±0.10)

j

·A·-......,, . -'. .

'- L

.0256±.OO47

, ·r

(0.65±o.12)

,- - - - - - - - - -D"alaiis-of

.OO6::~~(0.15:~gg~)
·A= Part ---------,

.004±.004

.230(5.85)

[JJI~·'.:.:

(STAND OFF

HE1GHn

REF

O'".d1 (O.so±o.20)
*:This dimension does not include resin protruction.

©1991 FUJITSU LIMITED F20012S-2C

6-56

Dimensions in
inches (millimeters)

MB54600 SERIES

PACKAGE DIMENSIONS
34-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-34P-M03)

* : This dimension does not include resin protraction.

34 pin Plastic SSOP
(FPT-34P-M03)
• , 1.00%O.101.433t.0041

I

6.1OtO.10

~a-;=;:;: ;:;:I:;:;:NO: ;: ;EX: :;:;: ; : ;: : n: : ;:r:;:;: ;:r: ; : ;: ;:;: ;:;: :;: ;~ l~1
.1 I O.65!.0256ITYP

I.

@)

I
I

""r . J

I' (.009
0.22:=! 1$10.10(.004181
.... )
10.40<.409IREF

1994 FWITSU UMITED F34003S-IC-2

j

8.10t0.20

7.10(.2801

.A.· .......[[·

...

rr. 0.15 ...
(.006:=)

r1ii.1
Dimensions in mm (inches)

6-57

6-58

00

=D~so~6-~701~o4~-1~E~~~~~~~~==~_ _ FUJITSU
=
DATA SHEET

MB 1560 Semicustom (For PLL Frequency Synthesizers)
Bi-CMOS LSI RF IC Specification
• DESCRIPTION
This FUJITSU Series is a master-slice type semi-custom LSI ideal for use in high-frequency front-end circuits
in VCO, amplifier, mixer and orthogonal modulator devices.
The MB1560 series features an analog circuit unit that is a more highly integrated version of the MB1520 MB1550 series featuring two analog cell circuits, plus a digital circuit unit with a power-saving prescaler circuit
and a PLL 1 circuit with pulse-swallow capability.
The PLL, prescaler and high-frequency analog circuits can be designed to users' specifications using FUJITSU's
standard macro cell technology.
This LSI series uses FUJITSU's latest wafer process technology for power-saving operation and master-slice
semi-custom design to reduce lead times and lower costs. In addition, the ultra-compact flat package helps
maintain circuit confidentiality, and contributes to lighter, more compact design by reducing the number of components.
The MB1560 series is ideal for high-frequency applications, particularly mobile communication devices operating on digital specifications such as PCN, DECT, PHS and so on .

• FEATURES
•
•
•
•
•
•
•

PLL circuits can be customized for operating frequency, logical circuits, etc.
High frequency analog circuits with adjustable resistance levels
High speed operating capacity to 3.0 GHz
On-chip low-current consumption and power-saving circuits
On-chip high-speed lockup function
Supply voltage: 2.7 V to 3.3 V (minimum operating voltage to 2.0 V min.)
Development time (standard): approx. 10 weeks

• LINEUP
Series
MB1560

Prescaler
1 circuit

Copyrighl© 1995 by FUJITSU LIMITED

PLL
1 circuit

Analog
circuits
2 circuits

i Operating
!;

frequency

:

Package
QFP . SQFP .

i ssap!

3.0 GHz ! 20
34

Remarks
For single PLL
frequency synthesizers

6-59

MB1560

• PACKAGE
20 pin Plastic SSOP

34 pin Plastic SSOP

(FPT-20P-M03)

(FPT-34P-M03)

• CHIP LAYOUT
• MB1560 Series

DDDDI '90ID
I . 0
Cha
pump

Phase shifter
macro

D
0
D

0
Analog
macro

0

0

0

PLL

0

0

0

Analog
macro

0

0

0

I

0

Analogprescaler
interface

Prescaler

0

I

00 0000
6-60--

0

0

MB1560

• Analog Cell

Capacitor
array

Capacitor array

Capacitor
array

(3 pF x 3)

(15pFx5)

(3pFx3)

§3

>-

>-

~

Transistor
array

~

g
1/1

unit

>-

!!!

~

I~oal

Resistor array

uM

~

as

Transistor
array

g
1/1

0

'lii

"in

"in

"in

"in

a:

a:

a:

a:

Q)

Ql

1

1

Q)

Q)

1(2 pF x 4)1

III

>-

~

!!!

Capacitor
array

1

1

I

6·61

MB1560

• MACRO CELL DESCRIPTIONS
1. Prescaler
Divides the reference frequency by any given value and outputs the resulting frequency. Choice of two-modulus or
fixed output mode.

2. PLL
• Phase comparator
The phase comparator has a phase detection range of -2 1t to +2 1t, and is designed to eliminate blind spots in
phase comparison by output of a margin-ot-error signal to the charge pump even when the phase difference is
zero. Phase comparator characteristics can also be tuned to the polarity of VCO.
• Counters
The divide ratios of the comparator-side counter and reference-side counter can be either programmable or fixed.
• Charge pump
The "H" level output voltage from the charge pump is determined by power supply voltage. Charge pump
characteristics for the sending and receiving systems can be optimized for each specific application.
For example, when FM modulation is applied directly to the VCO signal, charge pump characteristics can be
adjusted for lower speeds in order to reduce the sensitivity of the synthesizer loop so that output does not track the
modulation.
• Analog switch
When switching frequencies, the analog switch can be used to switch the capacitance ot the low pass filter, to
reduce the time constant in the filter and the load on the charge pump. This enables higher lock-up speed.
Switch control is synchronous with the LE signal, to that the analog switch is on when the LE signal is "high".
• High speed lock-up circuit
This circuit is specially designed for faster lock-up speeds.
• Intermittent operation control circuit
This on-chip power-saving function reduces circuit current flow in standby status, enabling devices to operate with
less power demand. A special circuit is built in to prevent excessive error signal from increasing lock-up delay
during the transition from power-saving mode to operating mode.
• List of standard macro cells

Type

PLL1

I

Vee I Icc
!

i

I

I

----

PLL2 i

3V

14mA

I Operating
I frequency
1.1 GHz

r------,-------!

6mA I 2.0 GHz

(M)

(N)

6-62

~

16 to 2047

64/65

Crystal oscillator input frequency: Up to 32 MHz
Standby mode current demand: 100

Comparator
counter
divide ratio

Prescaler
divide ratio

I

I counter
Swallow

Reference
counter
divide ratio

divide ratio

I (A)
!

I

(R)

o to 127

I
I

8 to 16383

MB1560
3. High Frequency Analog Cells
• Mixer
Active type double-balanced mixer
• IF amplifier
The IF amplifier is configured from a differential amplifier plus an NPN transistor using emitter-follower output from
the differential amplifier.

• RF amplifier
Provides emitter-follower output of the output signal from the emitter-ground circuit. The RF input side can be
connected to an internal bias circuit.
• VCO
Configured from an oscillator transistor in a base-ground Colpitts type oscillator circuit, plus a transistor acting as
output buffer. Can be connected to external devices such as varicap or resonator.
• Orthogonal modulator
An orthogonal modulator is used for IF frequency modulation. In addition, a flip-flop type 90° phase shift circuit can
be included in the configuration.

Note: Circuit format and other detailS can be adjusted to meet customer requirements .

• CIRCUIT OPERATING DESCRIPTIONS
1. Intermittent Operation Control Circuit
The intermittent operation control circuit operates the LSI circuits during communication operations and at all other
times places the chip in standby status to reduce power demand.
(1) Circuit operation in operating mode
All circuits are in operating status, and the chip performs normal PLL operations.
(2) Circuit operation in standby mode
All circuits that can be stopped without interfering with operation are shut down, and the chip goes into low-power
operating mode.

Latch data:
Shift register:
Charge pump output:
VCO input voltage:

Saves immediately preceding data
Data input enabled
High impedance
Saves voltage level stored in low-pass filter during the last operating mode

 The digital system power supply must still be applied in standby mode.

6-63

MB1560

2. Phase Lock Detection Circuit
To detect phase lock condition from the LD signal pin output, the T-bit should be selected. When the phase
difference is greater than tw, the LD pin will output an L level signal, and when the difference is less than tw for 3 or
more cycles, the output will change to H level. The length of the tw time interval can be set in the range of 625 ns to
1250 ns by connection to the crystal oscillator.
• LD Signal operating status
i

Operating status
Standby mode
Operating mode

PLL circuit

LD output

Standby

H

Un-lock

L

Lock

H

3. High Speed Tuning Circuit
The following high speed tuning circuits are available for use according to specific applications.
• High speed tuning circuits for ASTRO MASTER IV
Function
Analog switch

6-64

I

Operation

i Circuit temporarily reduces LPF time
constant at lock-up.

I For broad-band steps, circuit forcibly

Turbo circuits

I switches charge pump on/off

Supercharger circuit

I capacity

Hypercharger circuit

I capacity of the supercharger circuit

i
!

Circuit increases charge pump drive
Circuit further enhances the drive

Optimum applications
Analog portable phone
devices (receiving system)
PHS devices
PHS devices
POC, GSM etc.

MB1560

• SERIAL DATA
1. Data Bit Configuration
PLL operating settings are made through serial data input. The standard serial data format is shown in the table
below. Serial data is entered MSB-first, and the data length is in the range of 22 to 37 bits.
• Standard format for serial data
Bit name (abbreviation)

Functional description

Control bit (CNT bit)

Selects transfer destination (sending or
receiving system)

LD select bit (T-bit)

Selects LD output

FC bit (F-bit)

Switches the phase of phase comparator

Programmable counter bit (N-bit)

Sets the programmable counter's divide
ratio

Swallow counter bit (A-bit)

Sets the swallow counter's divide ratio

Reference counter bit
(R-bit)

I

Standard bit count

I

!

1 to 2
1 to 2
1
11
7
1 to 2

Fixed

I Programmable

Sets the reference counter's divide ratio
14

III

2. Serial Data Input Timing
After the serial data is stored in the shift register, it can be transferred to the latch circuit by means of the LE signal.

<:= Serial data"'

<:= Clock signal

<:= LE

(MSB)~··············~~)

------ i

i

,,

,,

..............

-----

. . . . . . . 1L-11-.. . ..
- - -.. . . . . . .--fl-m---

*1: Serial data is input, MSS-first.
*2: 100 ns $ h, t4
300 ns $ t3

800 ns $ ts

1000 ns $ 12

Notes: • Data input utilizes the serial data, clock and LE signals at supply voltage or lower levels
• Shift register data is updated sequentially each time the clock signal is input. Data is synchronized
with the rising edge of the clock signal, and is read sequentially into the shift register, MSS-first.
• After LSB input, the LE signal is changed from L level to H level.
• Shift register data is transferred to the latch circuit while the LE signal is at H level.
• Each input signal pin has a Schmitt trigger circuit to protect against abnormal operation due to
noise.

6·65

MB1560

• ABSOLUTE MAXIMUM RATINGS

I

Parameter

Rating
Symbol
I

1

Min.

Max.

Supply voltage·

Vee

-0.5

+4.0

Unit

I
V

Input voltage"

VIN

-0.5

Vee + 0.5

V

Output current

lOUT

-10

10

mA

Storage temperature

Tstg

-55

+125

°C

.: Voltage values are based on GND

=0 V.

Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability .

• RECOMMENDED OPERATING CONDITIONS
Value

Parameter

Symbol

Vee

Supply voltage·1
Operating temperature

GND
I

I

Ta

Min.

i

Typ.

Max.

2.7*2

I

-

3.3

!
i

0

I

-

-40

·1: Voltage values are based on GND = 0 V
"2: Operation is assured to the minimum operating voltage level of 2.0 V min.

6-66

i

+85

Unit

V
I

V
°C

MB1560

• ANALOG CIRCUIT CHARACTERISTICS
Circuit

Parameter

I Supply voltage

Conditions

Value (typ.)

Unit

-

3.0

V

I

-

11

rnA

-

900

MHz

Offset frequency = 25 kHz, Band
Width = 16 kHz

77

dB

BW = 0.3 to 3 kHz, 3 kHZ/Dev

44

dB

Current demand

l Operating frequency
, CIN ratio

VCO

SIN ratio

I

Supply voltage

-

Current demand

Output power

l

Mod Sense

IF

I Operating
, frequency
Mixer

LO

i RF

6

dBm
MHzIV

3.0

V

-

12

rnA

-

800

I

MHz

PLO = -10 dBm

110

MHz

fRF = flo + flF

910

MHz

-

Conversion gain
Maximum output power

Amplifier

I

-2

I

6

dB

-11

dBm

1 dB compression pOint

Output level

-15

dBm

Intercept point

Input level

-8

dBm

I

NF

DSB measurement

12

dB

I

Supply voltage

-

3.0

V

Current demand

I

Operating frequency

-

i

j

6

rnA

900

MHz

I

Gain

f:: 900 MHz (-30 dBm in)

14

dB

!

Maximum output power

f:: 900 MHz

-3

dBm
dBm

I

1 dB compression pOint

f :: 900 MHz, output level

-8

I

Intercept point

f :: 900 MHz, 900.1 MHz, input level

-12

!

NF

f:: 900 MHz

I

2.2

i
I

III

dBm
dB
(Continued)

6-67

MB1560

(Continued)

Circuit

Conditions

Parameter

Current demand

i Operating
frequency

Orthogonal
modulator

I

precision

I
i

6-68

L01

I
i

Unit

V

25

mA

500

MHz

=-5 dBm
= fL02 + fL01/2

L02

PL02

1650

MHz

RF

fAF

1900

MHz

i

-14

dBm

i

1.9

Amplitude
deviation
Phase
deviation

RMS Magnitude Error

I

:

%

RMS Phase Error

0.9

deg.

RMS Vector Error

2.4

%

-31

dBc

L

Vector error
Carrier leak

3.0

= -5 dBm

PLOl

I Output level
I Modulator

; Value (typ.)

-

Supply voltage

I

I

-

MB1560

• ANALOG SYSTEM: BASIC EQUIVALENT CIRCUITS
1. Mixer, IF Amplifier
The MB1560 series features an active-type double-balanced mixer. The LO and RF output can t ~ connected to an
internal bias circuit. The mixer output ;s connected through on-Chip load resistor to the ch.~~ s power supply, and
then to the next-stage IF amplifier. The IF amplifier is configured from a differential amplifier and NPN transistor,
and provides emitter-follower differential amplifier output.

Mixer

I-

IF amplifier

·1

VMIX

III
LOIN
Mixer output

LOINX
RFIN

RFINX

GND

6-69

MB1560

2. RF Amplifier
The emitter-ground circuit output signal is output as an emitter-follower signal. The RF input can be grounded to an
internal bias circuit.

VAMP o---~----~-

RFIN o--?---{
RF output

GNDO----4---~--~-

3.

veo Amplifier

The VCO amplifier is configured from an oscillator transistor in a base-ground Colpitts type oscillator circuit, plus a
transistor acting as output buffer. The veo amplifier can be connected to external devices such as varicap or
resonator.

Vvco

0---------....------

C 0-----.

vco output
B o--,---{

E o-------1--lI---<----i

GND

6-70

O-----4------~--~-

MB1560

• DEVELOPMENT PROCESSES
Each product in the MB1560 Series is developed through the following processes, based on requirement and
specifications supplied by the customer.

1. Feasibility Study
(1) Product specifications and development process study
FUJITSU conducts simulations based on documentation provided by the customer, in order to evaluate the
technical and economic feasibility of each proposed design.
Product Documentation
Technical documentation: Functional descriptions, 110 signal descriptions, block diagrams.
Characteristics documentation: For prescalers, PLL, VCO, mixers, amplifiers, etc.
Development Documentation
Delivery schedule documentation: Development schedule, division of responsibilities, etc.
Cost estimates: Volume requirements, development costs, target prices

(2) Product feasibility evaluation
Based on the foregoing studies, FUJITSU and the customer meet to evaluate feasibility.

(3) Development of planned specifications
Circuit functions and characteristics are studied in detail, and circuit specifications and testing specifications are
developed. After specifications have been determined, final estimates of the development schedule, timing and
cost, and the product price can be produced.

(4) Approval of provisional delivery specifications
After FUJITSU and the customer have determined the feasibility of product development, a provisional delivery
schedule is agreed upon.

6-71

MB1560

Customer

FUJITSU

Product specifications, conditions
for estimation

(1)
Functional study. cost estimation

No good

(3)

Preparation of documentation
for development study

Detailed product documentation

Development schedule, timing.
and price estimate

No good

Provisional delivery
schedule

6-72

MB1560

2. LSI Development
(1) LSI design, prototype development
Based on the provisional delivery specifications agreed by the customer and FUJITSU, chip design and prototype
work begins. The standard time required for an ES prototype is approximately 10 weeks from the approval of
provisional delivery specifications.

(2) ES (engineering sample) evaluation
Both the customer and FUJITSU evaluate the ES prototype based on the provisional delivery specifications.

(3) Final approval
If there are no problems with the evaluation, FUJITSU and the customer agree on final delivery specifications and
end development, moving to the mass production stage. The standard lead time for delivery of mass production
products is approximately three months.

Customer

FUJITSU

.---------------------------------------------------------- ... ------------------------- ... _----------------------------Provisional delivery
specifications

LSI design

ES prototype preparation

ES evaluation

(2)

No good

Delivery specifications
Good

I

I
-------~--

..

- -! 6-73

MB1560

• ORDERING INFORMATION
Part number

6-74

Remarks

Package

MB156XPFV

20 pin Plastic SSOP
(FPT-20P-M03)

MB156XPFV

34 pin Plastic SSOP
(FPT-34P-M03)

I

MB1560

• PACKAGE DIMENSIONS
20 pin Plastic SSOP
(FPT-20P-M03)

* :This dimension does not include resin protraction.

'I

~~=
L049=::)

,,'00."'" '''0'"

010.10(.004) I

l
J

5.40(.213)

NOM

.1

1

0.65:0.12
(.0256:!:.0047)

i1tiritirititit
I
.1
5.85(.230)REF

@

1994 FUJITSU UMITED F20012S-2C-4

0.15~::
.006:~)

I
I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ J

Dimensions in mm (inches)

(Continued)

6-75

MB1560

(Continued)

1-----I

* : This dimension does not include resin protraction~

,

34 pin Plastic SSOP
(FPT-34P-M03)

.0...,

• ".OO+O.'O(.433±.004)

I

~5~. '0

'I

(.049~·=)

(MOUNTING HEIGHT)

0\ 0.10(.004)\

l

7.10(.280)

8.10±O.20

J

,,

.A······_--t(
....
• • 0.15=

l.o.65(0256)TYP

(.006-.00,)

,---------------, Details 01 "A" part

I.

10.40(.409)REF

© 1994 FWITSU LIMITED F34003S-1C-2

6-76

I

I
I
I

DimenSions in mm (inches)

SECTION 7
Piezoelectric Devices/SAW Filters - At a Glance

7-1

7-2

SECTION 7
F5CC (L2) Series SAW Filters - At a Glance
The F5CC (L2) product family is based upon Fujitsu's advanced LiTa03 technology which provides very
sharp roll-off characteristics and excellent temperature stability, with the addition of a 50 Q impedance
matching network integrated into the filter. This is a very popular and cost effective feature, as it reduces the
number of external components. In addition to its superior performance compared to other technologies,
the F5CC series comes in a smaller 3.8 x 3.8 mm surface mount package for those size and weight sensitive
applications.
SeePage~.

(* New devices - Data not included in this edition.)

Part Number

Standard

Use

Center
Frequency
(MHz)

Passband

Width

Comment

(MHz)

FAR-FSCC-836MSO-L2AA

AMPS/
IS-136/15-9S

Tx

836.S

2S

FAR-FSCC-836MSO-L2AZ

AMPS/
IS-136/1S-95

Tx

836.S

2S

FAR-FSCC-881 MSO-L2AB

AMPS/
IS-136/15-9S

Rx

881.5

25

FAR-FSCC-881 MSO-L2AY

AMP51
15-136/15-95

Rx

881.S

2S

FAR-FSCC-933MSO-L2BA

NTT

Tx

933.S

17

High stopband
attenuation

I

FAR-FSCC-878MSO-L2BB

NTT

Rx

878.S

17

FAR-FSCC-888MSO-L2CA

ETACS

Tx

888.S

33

FAR-FSCC-933MS0-L2CB

ETACS

Rx

933.5

33

FAR-FSCC-911 MSO-L20A

NTACS

Tx

911.5

27

FAR-F5CC-856MSO-L20B

NTACS

Rx

8S6.S

27

FAR-F5CC-902MS0-L2EA

NMT/GSM

Tx

902.5

2S

FAR-FSCC-902MSO-L2EZ

NMT/GSM

Tx

902.S

2S

FAR-FSCC-947MSO-L2EB

NMT/GSM

Rx

947.5

25

FAR-FSCC-947MSO-L2EY
FAR-FSCC-947MSO-L2EX*

NMT/GSM

Rx

947.S

2S

FAR-FSCC-897MSO-L2KA*

E-GSM

Tx

897.S

35

FAR-FSCC-942MSO-L2KB*

E-GSM

Rx

942.S

3S

FAR-FSCC-942MSO-L2KY*

E-GSM

Rx

942.S

3S

FAR-FSCC-9S0MOO-L2FA

POC

Tx

9S0.0

20

FAR-FSCC-820MOO-L2FB

POC

Rx

820.0

20

FAR-FSCC-91SMOO-L2JA*

900 MHz ISM

TxlRx

91S.0

26

FAR-FSCC-91SMOO-L2JZ*

900 MHz ISM

TxlRx

91S.0

26

FAR-FSCC-93SMOO-L2LA*

2-WayPager

TxlRx

915.0

12

High stopband
attenuation

High stopband
attenuation

High stopband
attenuation

High stopband
attenuation

High stopband
attenuation

7-3

SECTION 7
F5CB Series SAW Filters - At a Glance
The F5CB series of LiTa03 SAW Filters were Fujitsu's initial entry into the high performance SAW Filter
market covering many of the major cellular standards under 1 GHz. The F5CB series requires external 50 Q
impedance matching and are supplied in 5 x 5 mm surface mount packages.
See Page 7-37 .

Part Number

7·4

Standard

Use

Center
Frequency
(MHz)

Passband
Width
(MHz)

FAA-F5CB-836M5o-G201

AMPS/
IS-136/15-9S

Tx

836.S

2S

FAA-FSCB-881 MSo-G201

AMPS/
IS-136/15-95

Ax

881.S

25

FAA-F5CB-881 M5o-G211

AMPSI
IS-136/15-95

Ax

881.5

2S

FAA-F5CB-888M5o-G201

ETACS

Tx

888.5

33

FAA-FSCB-933MSo-G202

ETACS

Ax

933.S

33

FAA-F5CB-933MSo-G212

ETACS

Ax

933.S

33

FAA-FSCB-902M5o-G201

NMT/GSM

Tx

902.S

25

FAA-F5CB-947M5o-G201

NMT/GSM

Ax

947.5

25

FAA-FSCB-947M5o-G211

NMT/GSM

Ax

947.S

25

FAA-FSCB-911 MSO-G201

NTACS

Tx

911.5

27

FAA-F5CB-933M5O-G201

NTT

Tx

933.5

17

FAA-F5CB-878M5O-G201

NTT

Ax

878.5

17

Comment

High stopband
attenuation

High stopband
attenuation

High stopband
attenuation

SECTION 7
F6Cx (L2) Series SAW Filters - At a Glance
The F6Cx series is similar to the F5CC series in that both have the 50 Q impedance matching integrated
onto the filter. The F6Cx series of SAW Filters is targeted for applications between 1 GHz and 2.5 GHz.
Presently available products support Japan's Personal Digital Cellular (PDC) standard (the F6CC series)
and Fujitsu has recently added several new standard devices (the F6CE series) to this product line to meet
the needs of the emerging PCS standards in the 1.8 GHz to 2 GHz range and of Wireless LAN applications in
the 2.4 GHz ISM Band in the US. The F6CC products are available in 3.8 x 3.8 mm surface mount packages
and the F6CE products are housed in very small 3 x 3 mm surface mount packages to meet the demands of
future communication handsets for small size and light weight.

SeePage~.

Part Number

Standard

Use

Center
Frequency
(MHz)

Passband
Width
(MHz)

Comment

FAR-F6CC-1G441O-L2ZA

POC 1.5GHz

Tx

1441.0

24

FAR-F6CC-1G4890-l2ZB

POC 1.5GHz

Rx

1489.0

24

3.8 X 3.8mm

FAR-F6CC-1G6190-l2ZN

POC 1.5 GHz

Lo

1619.0

24

3.8 x 3.Smm

3.8 X 3.8mm

FAR-F6CE-1G7475-L2YA

OCS 1800

Tx

1747.5

75

3 x 3mm

FAR-F6CE-1G8425-L2YB

OCS 1800

Rx

1842.5

75

3 X 3mm
3 x3mm

FAR-F6CE-1G8800-L2XA

PCS(US)

Tx

1880.0

60

FAR-F6CE-1G9600-L2XB

PCS (US)

Rx

1960.0

60

3 X 3mm

FAR-F6CE-2G4500-L2WA

WLAN(US)

2450.0

100

3 X 3mm

1-5

SECTION 7
M2, M3 Series (Resonators, Modulators, VCOs) - At a Glance
The M2 and M3 Series of devices are exclusively distributed and supported by
PAL-TECH Electronics, Inc. Please contact PAL-TECH with any inquiries regarding these products at:

PAL-TECH Electronics, Inc.
510 N. First Street, Suite 208
San Jose, CA 95112
Phone: (408)293-2290
Fax: (408) 293-2291

7-6

Page
Number

Part
Number

7-87

M2 Series (0100)

7-95

M2 Series (0300)

7-105

M3 Series (0001)

7-109

M3 Series (0101)

OJ

~D~so~~~231~~~~~E~~~~~~~==~~_FUJITSU
~

DATA SHEET

F5 SERIES (L2 Type) ASSP
PIEZOELECTRIC SAW BPF

SAW BANDPASS FILTER (700 to 1000 MHz)
DESCRIPTION

F5 series are wide band bandpass filters for use in the 700MHz to 1000MHz of frequency range.
F5 series uses a single lithium tantalate piezoelectric crystal (LiTa03) that has large electromechanical coupling
coefficient. This provides wide bandwidths and exceptional stability.
Our exclusive mounting technology makes F5 series very compact and surface mountable.

IJI

The F5 series is most suitable for use in handheld phones of both analog and digital systems.

FEATURES

PACKAGE

• Ultra compact and light (0.02 cc, 0.1 g)
• Outside matching circuit is unnecessary.
• Surface mount package (SMT)
• Wide variety of bandwidths for worldwide system
(AMPS, ADC, ETACS, NMT, GSM, NTT, NTACS, PDC)
• Low insertion loss
• High power rating: 0.2 W garanteed

Copyright@1994by FUJITSU LIMITED

7-7

F5 SERIES (L2 Type)
PIN ASSIGNMENT

(Bottom view)
Pin No.

Pin name

Description

1

GND

Ground Pin

2

IN

Input Pin

3

GND

Ground Pin

4

GND

Ground Pin

5

OUT

Output Pin

6

GND

Ground Pin

MAXIMUM RATINGS
Item
Operating temperature

Symbol

Unit
*1

Ta

-30 to +70

Storage temperature

Tstg

--40 to +100

Maximum input level

Pin

+200

mW

-

700 to 1000

MHz

Frequency range

*1 This is also the Recommended Operating Conditions.

7-8

Rating

°C

F5 SERIES (L2 Type)
STANDARD FREQUENCIES
STANDARD VERSION
Center frequency
(MHz)

Bandwidths
(MHz)

System

Part Symbol

Part number

836.5

25

AMPS/ADC (Tx)

AA

FAA-F5CC-836M5O-L2AA

881.5

25

AMPS/ADC (Ax)

AB

FAA-F5CC-881M5O-L2AB

933.5

17

NTT (Tx)

BA

FAA-F5CC-933M5O-L2BA

878.5

17

NTT (Ax)

BB

FAA-F5CC-878M5O-L2BB

888.5

33

ETACS (Tx)

CA

FAA-F5CC-888M5O-L2CA

933.5

33

ETACS (Ax)

CB

FAA-F5CC-933M5O-L2CB

911.5

27

NTACS (Tx)

DA

FAA-F5CC-911 M5CH.2DA

856.5

27

NTACS (Ax)

DB

FAA-F5CC-856M5o-l2DB

902.5

25

NMT/GSM (Tx)

EA

FAA-F5CC-902M5O-L2EA

947.5

25

NMTIGSM (Ax)

EB

FAA-F5CC-947M5O-L2EB

950.0

20

PDC (Tx)

FA

FAA-F5CC-950M0CH.2FA

820.0

20

PDC (Ax)

FB

FAA-F5CC-820MOo-L2FB

III

HIGH ATTENUATION VERSION
Center frequency
(MHz)

Bandwidths
(MHz)

836.5

25

881.5

25

902.5
947.5

Part Symbol

Part number

AMPS/ADC (Tx)

AZ

FAA-F5CC-836M5O-L2AZ

AMPSIADC (Ax)

AY

FAA-F5CC-881M5CH.2AY

25

NMTIGSM (Tx)

EZ

FAA-F5CC-902M5O-L2EZ

25

NMT/GSM (Ax)

EY

FAA-F5CC-947M5O-L2EY

System

'·9

F5 SERIES (L2 Type)
ELECTRICAL CHARACTERISTICS (STANDARD VERSION)
1. AMPS I ACC system (Tx)

Part number: FAR-FSCc-836MSo-L2AA
(Ta =-30·to 70°C)
Rating

Item

Symbol

Conditions

Unit
Min.

Typ.

Max.

-

2.0

3.5

dB

Insertion loss

IL

824 to 849 MHz

In-band ripple

-

824 to 849 MHz

-

0.6

2.0

dB

-

-

-

dB

869 to 894 MHz

20

27

dB

-

-

-

-

1.8

2.0

-

Absolute
stopband
attenuation
In-band VSWR

2. AMPS I ACC system (Rx)

824 to 849 MHz

Remarks

dB

Part number: FAR-FSCc-8S1 MSo-L2AB
(Ta =-30 to 70°C)
Rating

Item

Conditions

Unit
Min.

Typ.

Max.

Insertion loss

IL

869 to 894 MHz

3.5

dB

-

869 to 894 MHz

-

2.5

In-band ripple

0.6

2.0

dB

DC to 824 MHz

20

23

dB

824 to 849 MHz

20

28

914 to 939 MHz

20

27

dB

-

Absolute
stopband
attenuation

In-band VSWR

7-10

Symbol

939 to 1049 MHz

25

28

1049 to 2000 MHz

20

21

-

869 to 894 MHz

-

1.8

2.0

dB

dB
dB

Remarks

F5 SERIES (L2 Type)
ELECTRICAL CHARACTERISTICS (STANDARD VERSION)
3. ETACS system (Tx)

Part number: FAR-F5Cc-888M50-L2CA
(Ta = -30 to 70°C)

Rating
Item

Symbol

Conditions

Insertion loss

IL

872 to 905 MHz

In-band ripple

-

872 to 905 MHz

Absolute
stopband
attenuation
In-band VSWR

-

Unit
Min.

Typ.

Max.

-

3.0

5.0

dB

1.5

917 to 950 MHz

10

15

-

-

-

-

dB

-

-

872 to 905 MHz

-

2.1

2.5

-

Remarks

dB
dB
dB

-

Part number: FAR-F5CC-933M50-L2CB

4. ETACS system (Rx)

(Ta

=-30 to 70°C)

Rating
Item

Symbol

Conditions

Unit
Min.

Typ.

Max.

3.5

5.5

dB

2.0

dB

Insertion loss

IL

917 to 950 MHz

In-band ripple

-

917 to 950 MHz

-

OCto 872 MHz

20

32

872 to 900 MHz

25

32

Absolute
stopband
attenuation

In-band VSWR

900 to 905 MHz

10

15

1007 to 1040 MHz

30

38

1040 to 2000 MHz

20

26

-

917 to 950 MHz

-

2.0

2.5

Remarks

II

dB
dB
dB
dB
dB

-

7-11

F5 SERIES (L2 Type)
ELECTRICAL CHARACTERISTICS (STANDARD VERSION)
5. NTACS system (Tx)

Part number: FAR-F5CC-911 M5O-L2DA
(Ta = -30 to 70°C)
Rating

Item

Symbol

Conditions
Typ.

Max.

2.5

3.5

dB

0.6

2.0

dB

-

-

-

843 to 870 MHz

25

29

dB

-

-

-

-

1.8

2.0

Insertion loss

IL

898 to 925 MHz

In-band ripple

-

898 to 925 MHz

Absolute
stopband
attenuation
In-band VSWR

-

6. NTACS system (Rx)

Unit
Min.

898 to 925 MHz

Remarks

-

-

Part number: FAR-F5CC-856MSo-L2DB
(Ta =-30 to 70°C)
Rating

Item

Conditions

Unit
Min.

Typ.

Max.

2.5

3.5

dB

Insertion loss

IL

843 to 870 MHz

In-band ripple

-

843 to 870 MHz

-

0.6

2.0

dB

DC to 733 MHz

23

25

dB

733 to 760 MHz

35

40

760 to 815 MHz

25

29

-

898 to 953 MHz

25

35

-

953 to 980 MHz

35

40

-

980 to 1100 MHz

25

30

-

1100 to 2000 MHz

20

21

-

843 to 870 MHz

-

1.9

2.5

Absolute
stopband
attenuation

In-band VSWR

7·12

Symbol

dB
dB
dB
dB
dB
dB

-

Remarks

F5 SERIES (L2 Type)
ELECTRICAL CHARACTERISTICS (STANDARD VERSION)
7. NMT I GSM system (Tx)

Part number: FAR-FSCC-902MSo-L2EA
(Ta = -30 to 70°C
Rating

Item

Symbol

Conditions

Unit
Min.

Typ.
2.0

3.5

dB

0.6

2.0

dB

-

Insertion loss

IL

890 to 915 MHz

In-band ripple

-

890 to 915 MHz

-

-

-

835 to 960 MHz

20

27

-

dB

-

-

-

dB

-

890 to 915 MHz

-

1.8

2.0

-

Absolute
stopband
attenuation
In-band VSWR

8. NMT I GSM system (Rx)

Remarks

Max.

dB

Part number: FAR-FSCC-947MSo-L2EB
(Ta

=-30 to 70°C)

Rating
Item

Symbol

Unit

Conditions
Min.

Typ.

Max.

2.5

3.5

dB

0.6

2.0

dB

25

-

dB

Insertion loss

IL

935 to 960 MHz

In-band ripple

-

935 to 960 MHz

-

DC to BOO MHz

20

Absolute
stopband
attenuation

In-band VSWR

890 to 915 MHz

20

980 to 1025 MHz

15

28
28

1025 to 1070 MHz

35

40

-

Remarks

III

dB

dB
dB

1070 to 1105 MHz

30

35

-

dB

1105 to 1600 MHz

20

25

dB

1600 to 2000 MHz

15

20

-

935 to 960 MHz

-

1.9

2.5

-

dB

7·13

F5 SERIES (L2 Type)
ELECTRICAL CHARACTERISTICS (STANDARD VERSION)
9. POC system (Tx)

Part number: FAR-FSCC-9S0MOo-L2FA
(Ta "" -30 to 70°C)

Rating
Item

Symbol

Conditions
Typ.

Max.

2.0

3.0

dB

0.6

1.5

dB

-

-

-

20

25

-

-

-

-

dB

810 to 830 MHz

dB

1.8

2.0

-

Insertion loss

IL

940 to 960 MHz

In-band ripple

-

940 to 960 MHz

Absolute
stopband
attenuation
In-band VSWR

10. POC system (Rx)

Unit
Min.

940 to 960 MHz

Remarks

dB

Part number: FAR-FSCC-820MOo-L2FB
(Ta = -30 to 70°C)

Rating
Item'

Conditions

Unit
Min.

Typ.

Max.

3.0

4.0

dB

810 to 830 MHz

-

0.5

1.5

dB

OCto 740 MHz

20

25

dB

dB

810 to 830 MHz

Insertion loss

IL

In-band ripple

-

940 to 960 MHz

25

28

1040 to 1060 MHz

25

30

-

-

1060 to 2000 MHz

20

26

-

dB

-

810 to 830 MHz

-

1.8

2.0

-

Absolute
stopband
attenuation
In-band VSWR

7-14

Symbol

dB

Remarks

F5 SERIES (L2 Type)
ELECTRICAL CHARACTERISTICS (HIGH ATTENUATION VERSION)
11. AMPS I ADC system (Tx)

Part number: FAR-F5CC-836M50-L2AZ
(Ta = -30 to 70°C)

Rating
Item

Symbol

Insertion loss

Il

In-band ripple

-

Absolute
stopband
attenuation
In-band VSWR

12. AMPS I ADC system (Rx)

Conditions

Unit
Min.

Typ.

Max.

-

3.0

4.0

dB

824 to 849 MHz

-

1.0

2.0

dB

D.C. to 800MHz

25

28

dB

dB

-

824 to 849 MHz

869 to 894 MHz

30

40

894 to 1049 MHz

30

35

1049 to 2000 MHz

20

26

-

824 to 849 MHz

-

2.0

2.5

Remarks

dB
dB

Part number: FAR-F5CC-881 M50-l2AY
(Ta

=-30 to 70°C)

Rating
Item

Symbol

Conditions

Unit
Min.

Typ.

Max.

2.8

4.0

dB

Insertion loss

Il

869 to 894 MHz

In-band ripple

-

869 to 894 MHz

-

1.0

2.0

dB

OCto 779 MHz

25

31

dB

779 to 804 MHz

35

40

Absolute
stopband
attenuation

In-band VSWR

914 to 939 MHz

20

30

939 to 1049 MHz

35

40

1049 to 2000 MHz

20

26

-

869 to 894 MHz

-

2.0

2.5

804 to 824 MHz

25

31

824 to 849 MHz

20

31

Remarks

II

dB
dB
dB
dB
dB
dB

-

7-15

F5 SERIES (L2 Type)
ELECTRICAL CHARACTERISTICS (STANDARD VERSION)
1. AMPS I ACC system (Tx)

Part number: FAR-F5Cc-836M5O-L2AA
(Ta = -30 to 70°C)
Rating

Item

Symbol

Conditions
Typ.

Max.

2.0

3.5

dB

0.6

2.0

dB

-

-

-

dB

869 to 894 MHz

20

27

-

-

-

-

1.8

2.0

-

Insertion loss

IL

824 to 849 MHz

In-band ripple

-

824 to 849 MHz

Absolute
stopband
attenuation
In-band VSWR

2. AMPS I ACC system (Rx)

Unit
Min.

824 to 849 MHz

Remarks

dB
dB

Part number: FAR-F5Cc-8S1 M5O-L2AB
(Ta =-30 to 70°C)
Rating

Item

Conditions

Unit
Min.

Typ.

Max.

Insertion loss

IL

869 to 894 MHz

3.5

dB

-

869 to 894 MHz

-

2.5

In-band ripple

0.6

2.0

dB

OCto 824 MHz

20

23

dB

824 to 849 MHz

20

28

-

Absolute
stopband
attenuation

In-band VSWR

7-16

Symbol

914 to 939 MHz

20

27

939 to 1049 MHz

25

28

1049 to 2000 MHz

20

21

-

869 to 894 MHz

-

1.8

2.0

dB
dB
dB
dB

Remarks

F5 SERIES (L2 Type)
CHARACTERISTIC DATA EXAMPLES (STANDARD VERSION)
1. AMPS I ACC system (Tx)

CHI St1
AM~

log MAG
TX

5 dB /

REF

Part number: FAR-FSCc-836MSQ-L2AA

1 : - 30.282 dB

0 dB

8OO.r_~ MHz

~ J\

2: -1.329

1

CHl SII/M 1 U FS
AMPSTX

1 : 1.92030

dB

824 MHz
2: -1.4237 dB
849 MHz
4: -31.154 dB

\

869 MHz

H1d

i"'--~

l

~

\

I~

ry

I

~,

~

H1d

I

4

V'"

I
\
lJ

CENTER 835.000 000 MHz

" 1M

CHl S

lAMP!'

SWR

:x

000 MHz

SPAN 200.000

1 : 26068

1/REF 1

V

8OO.?F? MH2

,

I

CENTER 835.000 000 MHz

CH2 Szl/M 1 U FS

1: 1.55470

SPAN 200.000

246.521110

000 MHz

III

49.044pH

800.000 000 MHz

I I I
21: 1.38~2
824 MHz
Ai

/,

H1d

...

........ r.....
~

CH2 Szl/M SWR

I

BOO.~MH

L

I •

H1d
735.000 000 MHz

2

AI
I
/ 4

... -

~ -.J

START

4: 3.5304
869 MHz

1 : 32.152

l/REF 1

u

3: 1.2051
849 MHz

I

2 : 1.4163
824 MHz
3 : 1.2066
849 MHz
4 : 3.5619
869 MHz

t--I

3 STOP 935.000

H1d

I
000 MHz

START

735.000 000 MHz

STOP 935.000

000 MHz

7-17

F5 SERIES (L2 Type)
CHARACTERISTIC DATA EXAMPLES (STANDARD VERSION)
2. AMPS I ADC system (Rx)

CHt 52t
log MAG
AMPS AX

5 dBI REF

~

2-

Part number: FAR-FSCC-881 MSo-L2AB

1 : - 32.004 dB

0 dB

Cl

849.,

i

MHz

CHt Stt/M 1 U FS
AMPS AX

1 : 3.33790

9.28860
1.7413 nH
849.000 000 MHz

2 : -1.9124 dB
869 MHz
3: -1.8311 dB
894 MHz
4 : -30.38 dB
914 MHz

\

HId

HId

\

,

~1

"

41

/ 1

~

1I

1

v

1M SWR
AMPS AX

S, I

/ IV'"

\I

V

SPAN 200.000 000 MHz

CENTER 880.000 000 MHz

CH,

f

1 : 15499

l/REF 1

'0'

oor

I S:9.~
MHz
I
2:1.5452
4¥- V
869 MHz
3 : 1.1496
894 MHz
I
4 : 8.3418
914 MHz

•

HId

...

I

CH2 S22/M 1 U FS

1 : 3.19530

SPAN 200.000 000 MHz

8.6680
1.6249 nH
849.000 000 MHz

Cor

•

HId

3

1 . 16119

l/REF 1

'0'

CENTER 880.000 000 MHz

S:9.~ ~ MH.

I

I 2 : 1.5454
869 MHz

. . " I'
V

J

I
I

H1d
~

CENTER 880.000 000 MHz 2

7-18

-

3: 1.1753

894 MHz
4 : 7.8064
914 MHz

I
,Q

3 SPAN 200.000 000 MHz

CENTER 880.000 000 MHz

SPAN 200.000 000 MHz

F5 SERIES (L2 Type)
CHARACTERISTIC DATA EXAMPLES (STANDARD VERSION)
3. ETACS system (Tx)

CHI S2!

Jog

MAG

5 dB /

Part number: FAR-F5Cc-888MSo-L2CA

R:F

0 dB

1 : - 2.2698 dB

/r ~

ETACS TX

872.,

2

I

'i

CHI Su/M 1 U FS

2 : -3.328 dB
905 MHz
3: -20.436 dB
917 MHz

1 : 29.1640

516.36 pH

2.82910

872.000 000 MHz

ETACSTX

MHz

c..

4: -36.854 dB
950 MHz

HId
3

"'\......

,r

HId

r

IA

) 'V'

I
I

CENTER 890.000 000 MHz

-

I

SPAN 200.000

000 MHz

1 . 17226

l/REF 1

CENTER 890.000 000 MHz

CH2 s-o./M 1 U FS

SPAN 200.000

2.7363 0

1 : 30.8370

-,-f

ErACSTX

1:172.00

,
'\
\

H1d

1

II

""""'"
CH2 S:m 1M SWA

'"

1D
~

OJ

1/REF 1

499.43 pH

872.000 000 MHz

au

,

MN:

2: 57.932

"'~~----",("
\

2':

\

000 MHz

1.3046
905 MHz
3 : 1.6986
917 MHz

... ../
I

4 : 20.4
950 MHz

'

.... '3:

'(" .. ~ i --....

'....

.....

"

\

\

....,'"

n

-16'=~HZ
67.141 (1

-38.867 (1

917 MHz
~.4: 5.7598 (1
-35.102 (1

"'" ..........~~ ::'; . . .

950 MHz

1 . 16292
.Q.U

I

71

L

672.000 000 MH,
I

Co,

2 : 1.4061
905 MHz

3 : 2.0496
917 MHz

1

H1d

~/,

CENTER

690.000 000 MHz

-

HId

LI 3f--4: l~tHZ

,,'CJ

2 SPAN 200.000 000 MHz

START 790.000 000 MHz

SPAN 990.000

000 MHz

7-19

F5 SERIES (L2 Type)
CHARACTERISTIC DATA EXAMPLES (STANDARD VERSION)
4. ETACS system (Rx)

CH, S21

log

5 dB I

MAG

Part number: FAR-FSCC-933MSo-L2CB

FEF

1 : - 19.279 dB

0 dB

905'11

.k- rx

ETACS RX

3

/2

Cor

11

~

1

Hld

1 : 15.6840

259.5 pH

1.4756 0

905.000 000 MHz

ETACSAX

2 : - 3.3257 dB
917 MHz
3: -3.2486 dB
950 MHz
4: -40.573 dB
1.007 GHz

1\

I

CH, S,,/M 1 U FS

MHz

2: 31.354

a

-2.en9 a

Cor

Hld

~

--

~

~

i / ~'

SPAN 200.000 000 MHz

CENTER 935.000 000 MHz

1 . 3191

l/FEF 1

CH, S" /M SWR
ETACS AX

-v

1

SPAN 200.000

CENTER 935.000 000 MHz

CHz Szz/M 1 U FS

1 : 10.9160

~r=

I
I

1\
\

I
I
I

\
\ 1
V

H1d

2
CHz ~/M SWR

I

I
I

1

I

I

7-20

935.000 000 MHz

..

.Q

,

I
If

I

2:~

1.5879

917 MHz

..

I

1.00~ GHz

-,... :::: ....

...... _ " " "

1.007 GHz

1 . 58894

I

CENTER

,'r-----_:
I

1/FEF 1

L..... ["'0.. .....

a
a
\
, ' . 3: 58.68 a
, .. " - , - - .. -7.7188 a
,<
950 MHz
.... . / ' ,
\ _ 4: 3.9082 a
I...... '"....
-27.96 a

.. '

"
II

H1d

2 : 1.6033
917 MHz
3 : 1.2087
4 : 22.195

_J

Ilr-'" f""oo,.,

4.6147 nH

905.000 000 MHz

I

950 MHz

I

~

26.24 0

I

I ",,5.000 000 MHl

000 MHz

!t5.doo U

MH2

, 2 : 1.2232
917 MHz
3 : 1.2386
950 MHz

4 : 16.813
1.007 GHz

3 SPAN 200.000 000 MHz

H1d
START 835.000 000 MHz

STOP 1 035.000

000 MHz

F5 SERIES (L2 Type)
CHARACTERISTIC DATA EXAMPLES (STANDARD VERSION)
Part number: FAR-F5CC-911 M5O-L2DA

5. NTACS system (Tx)

5 dB I F£F

CHl S21
log MAG
NTACS TX

0 dB

~ -~
4

Cor

1 : - 33.303 dB
843'11 MHz

: 1.3589 Cl

-8.~ Cl

23.515 pF
843.000 000 MHz

2 : -29.485 dB

\

870 MHz

1

3: -2.1124 dB
896. MHz
4: -2.2046 dB
925 MHz

\
H1d

HId

I--

-, V 2\
"f

"\,

~

,/

•

/

CHl S /M 't'7
1 SWR
NTACSlX

"

\. )

I
~

V

SPAN 200.000 000 MHz

CENTER 910.000 000 MHz

1 . 37703

l/REF 1

,

.,

CENTER 910.000 000 MHz

CH2 S22/M 1 U FS

843.000 000 MH

-f·

1 : 1.6357 Cl

SPAN 200.000 000 MH2

D

-6.4114 Cl
29.447 pF
843.000 000 MHz

• I

Cor

l,S)SS
1\

H1d

-

CH2 S:!2 /M

v1

SWR

-

IV
I

870 MHz
3 : 1.5002
896 MHz
4 : 1.2004
925 MHz

~

1/REF 1

1

31063

843.'f~ MH2

1

I I

Cor

H1d

CHl Sll 1M 1 U FS
NTACS TX

2': 17.lsa
870 MHz

-

START 810.000 000 MHz 3

,n"

-,
,Q

4

I

3 : 1.4916
896 MHz
4 : 1.1858

Cor

HId

925 MHz

STOP 1 010.000 000 MHz

START 810.000 000 MHz

STOP 1 010.000 000 MHz

7-21

F5 SERIES (L2 Type)
CHARACTERISTIC DATA EXAMPLES (STANDARD VERSION)
6. NTACS system (Ax)

CHI S21

log

Part number: FAA-FSCc-8S6MSO-L2DB

5 dB I F£F

MAG

0 dB

1 . - 29708 dB

Ie ~,

NTACSAX

814'1

I

j

MHz

2: - 2.4842 dB
843 MHz
3: -2.4896 dB
670 MHz
4: -36.679 dB
698 MHz

I

H1d

CHI Su/M 1 U FS
NTACS AX

1 : 2.72180

2.81410
550.22 pH
814.000 000 MHz

Co.

H1d

1
V

/'
~

\

\

/

,...
"1~ II

~

r

CENTER 860.000 000 MHz

CHI S'1

1M

SWR

SPAN 200.000 000 MHz

l/REF 1

V

1

: 18427

~,...,....

NTACS AX

CENTER 860.000 000 MHz

CH2 S22/M 1 U FS

/1-e1!b .. ~.M
I
I

,
H1d

IV

"'2\0.""~
J::J.
2
3
CH2 Sz2 /M SWR

1

•

I

,
2
~

CENTER

7-22

860.000 000 MHz

'....
J
3

I

I

,/'t r-e14.~
, 060 MHz
H1d

I

,'.,.-----,,:
,
\

I '
I'

2: 31.601 Q
3.7949 Q
843 MHz
3: 45.979 Q

\ , , - , - , .. -5.59n Q
,('
870 MHz
./ "
\
4: 6.8281 Q
,.... "
, ..... - -37.289 Q
' " ' .... "
,,
-, ... :::: .... 898 MHz

1 . 25113

l/REF 1

V

1 : 1.99890
3.2189 0
629.36 pH
._--_
614.000 000 MHz

2: 1.6116
643 MHz
3 : 1.067
670 MHz
4 : 10.112
898 MHz

I

SPAN 200.000 000 MHz

"

2 : 1.5943
643 MHz
3 : 1.1545
870 MHz
4 : 11.442
89~ MHz

Cor

H1d

I

SPAN 200.000 000 MHz

CENTER 860.000 000 MHz

SPAN 200.000 000 MHz

F5 SERIES (L2 Type)
CHARACTERISTIC DATA EXAMPLES (STANDARD VERSION)
7. NMT I GSM system (Tx)

CHI S2!

log

MAG

5 dB /

FEF

Part number: FAR-FSCC-902MSO-L2EA

,

0 dB

1 : - 32.965 dB

~ -~ 1\

NMT TX

870·r

J

CHI S11/M 1 U FS

2: -1.6.nSdB
BOO MHz
3: -1.5427 dB

1 : 4.062Q

10.098 Q

1.8473 nH

870.000 000 MHz

NMT TX

MHz

Co.

915 MHz
4: -26.332 dB
93i MHz

H1d

H1d

"\

(
I{

,"

..... 1

4

~

"

/1

\/

SPAN 200.000 000 MHz

CENTER 900.000 000 MHz

CHI S 1M SWA

;1 V-

1 IREF 1

v

1 : 12.812
I

NMT TX

I

1

CENTER 900.000 000 MHz

CH2 S22/M 1 U FS

1 : 4.0527Q

87 tl.ooo1bM

SPAN 200.000 000 MHz

11.328 Q

2.0723 nH

870.000 000 MHz

II
II

Cor

4 r 2 : 1.31'95
890 MHz
3 : 1.0546
915 MHz
I
4 : 5.1917
935 MHz
H

HId

.....

"::'

....0.

.....

3

CH2 SZI 1M SWA

1 IREF 1

V

...

1 : 12.969
lft

I 87b.ooo ooo MH
II
II

Cor

1

HId

~
CENTER

900.000 000 MHz

r--- 2 : 1.3659

890 MHz
3 : 1.092
915 MHz
4 : 5.3149
935 MHz
~
.Q
3 SPAN 200.000 000 MHz
H
I
I

HId

.,..,

CFNTER 900.000 000 MHz

SPAN 200.000 000 MHz

7·23

F5 SERIES (L2 Type)
CHARACTERISTIC DATA EXAMPLES (STANDARD VERSION)
8. NMT I GSM system (Rx)

CHI S21

log

MAG

5 dB /

Part number: FAR-FSCC-947MSo-L2EB

F£F

1 . - 39.671 dB

0 dB

Ir ~

NMT RX

915'11 MHz

'-

2 : -1.9195 dB
935 MHz
3: -1.9695 dB
960 MHz
4: -29.093 dB
900 MHz

H1d

CH, S,,/M 1 U FS
NMT RX

1 : 6.2412 Q

20.725 Q
3.6048 nH
915.000 000 MHz

2: 39.6390
Cor

H1d

\

i.--'\

lL

V

41

\~ .
'\. ~ r

~
1

II

SPAN 200.000 000 MHz

CENTER 950.000 000 MHz

CH, Sl1 /M SWR
NMT AX

1 . 94053

1/REF 1

.

IQ.

141
II II

H1d

. . . r-----..'"
\

2 :38.695 g
2.9473 g
935 MHz
3: 47.217 g
-3.7051 0

I ...
I"

\

, ......... , - ..

,

,<'
"

..

960 MHz

4: 17.193 g

\

....

,'If"'"

........... '..

-50.631 0

980 MHz

1 : 12946

1 /REF 1

~

~

...

--,.... ::~ "

~15.000~ MH
4-

Al

IU
I
II
I

H1d
"

7-24

915.000 000 MHz

I

'-1-0
.u ""''''~
3

3.65 nH

20.984 Q

1 : 4.54690

2 : 1.3007
935 MHz
3 : 1.079
960 MHz
4 : 6.1523
960 MHz

1/

CENTER

CH2 822/M 1 U FS

SPAN 200.000 000 MHz

915.~ ~ MH

I - - ~1

CH2 Sz! /M SWR

CENTER 950.000 000 MHz

_L _ _

950.000 000 MHz

r

~2:

1.3031
935. MHz
3 : 1.1
960 MHz
4 : 6.0688
~ MHz

"'3 SPAN 200.000 000 MHz

HId

I

~

CFNTER 950.000 000 MHz

SPNl 200.000 000 MHz

FS SERIES (L2 Type)
CHARACTERISTIC DATA EXAMPLES (STANDARD VERSION)
9. JDC system (Tx)

CH, S21

log

MAG

Part number: FAR-FSCC-9S0MOO-L2FA

5 dB I

Il:F

1 . - 'Zl.D73 dB

0 dB

820., i

,

Ilf ~

PDC TX

~

CH, S"/M 1 U FS

poe

MHz

TX

: 1.sno

__- - _ .

-38.291 a
5.0088 pF
820.000 000 MHz

2 : - 29.433 dB
840 MHz
3: -1.5171 dB
940 MHz
4: -1.7669 dB
900 MHz

H1d

H1d

r-t.."""

~

\j

N

1f'J

v
J

'tV

CENTER 950.000 000 MHz

SPAN 300.000 000 MHz

S11'~

SWR
PDCTX~

1/REF 1

I

'\..
~

3

1: 1.13530

__- - _ _

-14.348 a
13.528 pF
820.000 000 MHz

I

.... ~
""
4

1/REF 1

~

1 : 47.62
I 820.000 000 MHz

-I

t!

I',
I I
I

H1d

CH2 S22/M 1 U FS

III

2 : 39.546
840 MHz
3 : 1.1994
940 MHz
4 : 1.0882
960 MHz

I

H1d

~&SWR

1 : 42.262

' F'C:XX: 000 MHz

SPAN 300.000 000 MHz

CENTER 950.000 000 MHz

I

I

2 : 46.617
840 MHz
3 : 1.1849
940 MHz
4 : 1.086
960 MHz

1

Cor

H1d

i
CENTER 950.000 000 MHz

SPAN :m.000 000 MHz

7·25

F5 SERIES (L2 Type)
CHARACTERISTIC DATA EXAMPLES (STANDARD VERSION)
10. JOC system (Rx)

CHI S21

Part number: FAR-F5Cc-820MOO-L2FB

MAG 5 dB/ FEF

log

,

0 dB

1 : - 34.728 dB

rf ~

PDC AX

740.,

i

2: -l.ml dB
810 MHz
3: -2.196 dB
83) MHz
4: -30.165 dB
940 MHz

Hld

CHI Sl1/M 1 U FS

1 : 2.51950

-37.322 0

5.7626 pF

740.000 000 MHz

POC AX

MHz

2: 35.936 0

Ccr

Hld
1'-0..

-....... ~

,

,

1"l

\ I

I

I
IAI

SPAN 300.000 000 MHz

CENTER 820.000 000 MHz

CH, S /M SWR _'\1
1
poe AX

"

l/REF 1

J

,r
"\ .... 1

CH2 S22 /M SWR v1

f4'MHz

CH2 S'¥}./M 1 U FS

1 : 978.75mO

-7.58960

2B.338pF

740.000 000 MHz

006

2 : 1.3921
810 MHz
3 : 1.0576
830 MHz
4 : 13.747
94~ MHz

I

L1

SPAN 300.000 000 MHz

1 . 3>91
74O.doo

Hld

CENTER 820.000 000 MHz

I

.Q

l/REF 1
II
II

1

52216

L
740.000

_~_

000

MHz

Co,

2 : 1.3229
A

II
I

HId
START

7-26

670.000 000 MHz

lI... ~
~
.u

2

3

810 MHz
3:1.08n
830 MHz
4 : 16.415
~ MHz
I

STOP 970.000 000 MHz

Hld
START 670.000 000 MHz

STOP 970.000 000 MHz

F5 SERIES (L2 Type)
CHARACTERISTIC DATA EXAMPLES (HIGH ATTENUATION VERSION)
11. AMPS I ACC system (Tx)

CH, 521

log
AMPS TX

MAG

Part number: FAR-F5CC-836M50-L2AZ

5 dB / REF 0 dB

~
I

t

33.an

1: -

dB

CH, S,,/M 1 U FS

~--_

15.005 pF

800.000 000 MHz

2 : -2.1369 dB
624 MHz

~

I

-12.50&1

1 : 4.9673[2

AMPSTX

800'11 MHz

3: -2.6534 dB

\

849 MHz

4 : -74.754 dB

E!69 MHz

H1d

Hld

~

,,'If *\
i\.j

CENTER 835.000 000 MHz

SPAt 200.000

l/REF 1

,

~

AMPS TX

\

r

000 MHz

1 . 10701

CENTER 835.000 000 MHz

CH2 622/M 1 U FS

1 : 2.4343[2

aoo.~.~ MHz

SPAN 200.000

1.4425[2

000 MHz

285.98

III

I*i

800.000 000 MHz

2 : 1.3824
624 MHz
3 : 1.3886
849 MHz
4 : 10.009
B69 MHz

,,
,

\

H1d

I
~

2

CH2 ~/M SWR

-

j

If

~

"'3'

""

l/REF 1

v

J

I
I
1

I

20552

aoo.'f

I
\
III

'-'

I

H1d
~

CENTER 835.000 000 MHz2

" .....
Q

I

~ MH.I

2 : 1.2514
624 MHz
3 : 1.3961
849 MHz
4: 6.698
B69 MHz

I

3 SPAN 200.000

Co.

H1d

I
I
000 MHz

START

735.000 000 MHz

STOP 935.000 000 MHz

7-27

F5 SERIES (L2 Type)
CHARACTERISTIC DATA EXAMPLES (HIGH ATTENUATION VERSION)
12. AMPS I ACC system (Rx)

CHI S21
log MAG
AMPS AX

5 dB /

Ff:F

Part number: FAR-FSCC-881 MSO-L2AY

1 : - 35.329 dB

0 dB

1Jtf-tJ'

,

\

H1d

849·r I

CHI S,l/M 1 U FS
AMPSRX

1 : 6.5200Q

-7.0962Q

26.417pF

849.000 000 MHz

MHz

2: - 2.6388 dB
869 MHz
3: -1.6836 dB
894 MHz
4: -27.479 dB
914 MHz

Co,

H1d

~

,/

.... V

\
0

CENTER 680.000 000 MHz

CHl S"

1M

4: 35.982Q

SPAN 200.000 000 MHz

-63.016 Q

2.7633 pF

914.000 000 MHz

1: 2.6596

a

3 : 1.3853
E!94 MHz
4 : 3.0538
914 MHz

\
\

I

~
I~

CH2 Szz/M SWA

'-

J

4 . 40706

1/REF 1

Il914.? ~ MH

~

\
I

PI
I~

H1d

.-

7-28

CH2 S'r2/M 1 U FS

I
2 : 1.5416
869 MHz

\

CENTER

CENTER 680.000 000 MHz

I

\
\

Cor

~

000 MHz

649.000 000 MH

I
I.
~

H1d

J

1 . 78235

l/REF 1

SWA

AMPS AX

SPAN 200.000

660.000 000 MHz 2

1
'-~
Q

1 : 17.729
849 MHz
2 : 1.2759
869 MHz
3 : 1.3422
E!94 MHz

I
I

Cor

H1d

J

I

3 SPAN 200.000 000 MHz

CENTER 880.000 000 MHz

SPAN 200.000 000 MHz

F5 SERIES (L2 Type)

CHARACTERISTIC DATA EXAMPLES (HIGH ATTENUATION VERSION)
13. NMT I GSM system (Tx) Part number: FAR-F5CC-902M50-L2EZ

CHl

S21

log

5 dB I F£F

MAG

NMT TX

0 dB

1 : - 38.637 dB

CHl Sll 1M 1 U FS

~
, I)

1 : 8.4302 0

___- - _ _

NMTTX

870'11 MHz

-3.5049 0
52. 195 pF
870.000 000 MHz

2 : -2.7226 dB
BOO MHz
3: -2.433 dB
915 MHz
4: -42.811 dB
935 MHz

\

H1d

H1d

i--

~

, / V'

r ---v.I--

if

SPAN 200.000 000 MHz

CENTER 900.000 000 MHz

CHl S" 1M SWR

1 . 59007

l/REF 1

NMT TX

870.c:r

~

"\,

b

\

i

\
\

If
I

HId

...

'-.

I.......",.

CENTER 900.000 000 MHz

CH2 S22/M 1 U FS

1 : 4.43550

oor MH

SPAN 200.000 000 MHz

•

15.084 C
2.7593 nH
870.000 000 MHz

2 : 1.5042
890 MHz
3 : 1.2429
915 MHz
4 : 5.6325
935 MHz

I

I

J

I

I

3

CH2 &:z 1M SWR

1 : 123

l/REF 1

'"

B70.? ~ MH

A
It

'''I
J

HId
~

CENTER

900.000 000 MHz2

,,,

.0
~ SPAN

2 : 1.4281
890 MHz
3 : 1.1tr22
915 MHz
4 : 4.5522
935 MHz

I

i

CCt

H1d
CENTER 900.000 000 MHz

SPAN 200.000 000 MHz

200.000 000 MHz

7-29

F5 SERIES (L2 Type)

CHARACTERISTIC DATA EXAMPLES (HIGH ATTENUATION VERSION)
14. NMT I GSM system (Rx) Part number: FAR-FSCC-947MSo-L2EY

CHI S21
log
NMT AX

MAG

5 dB / F£F

I

1 : - 35.416 dB

0 dB

rr-: ~

915.,

i

MHz

2: - 2.8437 dB
935 MHz
3: -2.3557 dB

1\

CHI SII/M 1 U FS
NMT AX

1 : 10.1190

248.94 pF

SPAN 200.000

000 MHz

915.000 000 MHz

c..

900 MHz
4: -31.542 dB
98) MHz

HId

HId

~

....--

~I(

~

r

,
\
,

NMT AX

-""

SPAN 200.000 000 MHz

CENTER 950.000 000 MHz

1 . 49424

I/REF 1

I

CENTER 950.000 000 MHz

CH2 S22/M 1 U FS

1 : 5.50080

915.'f ~ MHl

Ib

I

\

¢
C

\

HId

'\.
~
~

CH2 ~/M SWR

J

"

960 MHz
4: 4.012
980 MHz

J

1

':I

1 . 10204

I/REF 1

915.'f ~ MH

I

2 : 1.5546
II

935 MHz

~I

3 : 1.2467
960 MHz

r
,,
HId

\
CENTER

17.567 a
3.0557 nH
915.000 000 MHz

2: 32.002 (1
1.4531 (1
935MHz
40.707 (1
3.6172 (1

2 : 1.7349

935 MHz
3 : 1.3024

7-30

-698.73 rna

___- - _ _

4 : 5.9192
980 MHz

c..

H1d

I
~

950.000 000 MHi

"-A

3 SPAN 200.000 000 MHz

CENTER 950.000 000 MHz

SPAN 200.000

000 MHz

F5 SERIES (L2 Type)
MEASURING CIRCUIT

®

®

00

~

7JT

PART NUMBER DESIGNATION
[Designation example]
FAR-FSCC-

OODOOO

..

Cor
Del

Hid

1: -3.7465 dB

5dBl REFOdB

log MAG

NTACSRX'

8.84380
870 MHz

Hid

/\

~~

M hJI
~ v_Y

,t"..
I

\1
Y

CENTER 860.000 000 MHz

SPAN 200.000 000 MHz

CENTER 860.000 OOOMHz

SPAN 200.000 OOOMHz

III
1: 1.5956

11 REF 1

SWR

CH1 S"

NTA~RXI I~

I

Cor
Del

CH1

2: 56.0920

7.1348 0 1.3052 nH
870.000 000 MHz

843.000 000 MHz

,1

2: 1.1936
870 MHz

1: 51.852 0
-23.9410

Cor
Del

843 MHz

...a. I

Hid

~

.,.

/

I

,..,.
r-

Hid

/

1\

~ \/

, J2
1

CENTER 860.000 000 MHz

J

•

SPAN 200.000 000 MHz

CENTER 860.000 000 MHz

SPAN 200.000 000 MHz

7-57

12. NTT type (Tx)
Part number: FSCB-933MSO-G201

log MAG

CH1 Sa1

5dBl REF OdB

Cor

2: ~.72711 dB
942 MHz

1

~

I

Hid

V

__ 1.4

,III

II ""

CENTER 935.000 000 MHz

SWR

.,

,

Ii

Cor
Del

1 U FS

1:44.33 0

10.285 0 1.7697 nH
925.000 000 MHz

NTITX

2: 32.7270
-7.10350
942 MHz

Cor

Del

{\

d 11
IY

SPAN 200.000 000 MHz

11 REF 1

1: 1.3923

CENTER 935.000 OOOMHz

CH1

S"

1 U FS

SPAN 200.000 OOOMHz

1: 36.0160

NTITX

I

NTTITl(

S22

Hid

\

J

,1

CH1

1125.~ooo,MHZ

~,

I

Del

CH1 SII

1:-3.307 dB

lY- .....

NTT'Tl(

1.877 0 322.95 pH
925.000 000 MHz

1125.000 OOOJMHz

2:1.1n
942 MHz

2:45.8790

Cor

~.64450

942 MHz

Del

I

Hid

"'\

..J
fn r

/

1

I

I

/

Hid

V

I'V
1

J

Ut. 612
CENTER 935.000 000 MHz

7·58

SPAN 200.000 000 MHz

CENTER 935.000 000 MHz

SPAN 200.000 000 MHz

13. NTT type (Rx)
Part number: FSCB-878MSO-G201

'J' ~

NIT'AX

Cor

Del

Hid

.,It

f

I
I~

~r

I

1: 26.7390

CH1

15.083 0 2.7592 nH
870.000 000 MHz

870.000 000 MHz

2:-3.594d8

2'

I

~

1: -3.6685 dB

5 dB! REF 0 dB

log MAG

CH1 &'11

/
L
I

B87MHz

2: 45.1620
4.68360
887 MHz

Cor
Del

1\

1\,

Hid

\

~

1

~

\
I \I
{

II
II'

r

SPAN 200.000 000 MHz

CENTER 880.000 000 MHz

CENTER 880.000 OOOMHz

SPAN 200.000 OOOMHz

III
CH1 S,'

J

NIT'AX

Cor

Del

til \
Hid

lrf
,

11 REF 1

SWR
W

1: 1.5187

I

870.000 000 MHz
_L
2: 1.3401
B87 MHz

/
AJ

"

/

/'

CH1

Sl1
1 U FS
NTIRX

1: 38.816 0

-14.7910 12.368 pF
870.000 000 MHz
2: 66.1680
-4.9180
887 MHz

Cor
Del

Hid

r ~v I
I
IIV
1

I

I~ ~2
CENTER 880.000 000 MHz

SPAN 200.000 000 MHz

CENTER 880.000 000 MHz

SPAN 200.000 000 MHz

7-59

TEST CIRCUIT

®

(D.®.@,
it

t----i

t--"""'T""'---(

(ID.(!).®

Each value is changed according to specification

PART NUMBER DESIGNATION
Designation example
FSCB- 000000 -GOOD - D

 Packaging (Reeled tape)

:
Designation

7-60

®

Contents

T

1Kpcs/reel

R

3Kpcs/reel

DIMENSIONS
RO.2
(0.008)

t

1

5.0(0.197)

~ ~~____
4.4~(0_.1_7~3)__~~

~

'IT
4.8(0.189)

RO.4

I

/)~.

_ _ _ _----JI( [0,197)

(0.016)

ODD I ~




.DESCRIPTION

Pin name

Description

1

GND

Ground Pin

2

IN

Input Pin

3

GND

Ground Pin

4

GND

Pin No.

5

OUT

6

GND

Ground Pin
"

Output Pin
Ground Pin

7-67

F

6

SERIES

(L

2)

"MAXIMUM RATINGS
I t em

Symbol

Rating

Operating temperature

T.

-30-85

°C

Storage temperature

T atll

-40-100

°C

1000-2500

MHz

FreQuecy range
Maximum input level

Refer to electrical characteristics

PIN

Unit

I

mW

"Recommended Operating Conditions

Item
Operating temperature

Symbol

Rating

Unit

T.

-30--85*

°C

*Standard Rating for Wireless LAN is 0 -- 60°C
"STANDARD

System

BW
(MHz)

1441.0

24

P DeL 5 G (Tx)

ZA

FAR-F6CC-IG4410-L2ZA

C

1 4 8 9.0

24

P DeL 5 G (Rx)

ZB

FAR-F6CC-IG4890-L2ZB

C

1 6 1 9. 0

2 4 P DeL 5 G (Lo)

ZN

FAR-F6CC-IG6190-L2ZN

e

1 7 4 7.5

7 5 Des 1800 (Tx)

A

FAR-F6CE-1G7475-L2YA

E

1842.5

7 5 Des 1800 (Rx)

B

FAR-F6CE-1G8425-L2YB

E

1 8 8 0.0

6 0 pes (Tx)

e

FAR-F6CE-IG8800-L2XA

E

1 9 6 o. 0

6 0 pes (Rx)

D

FAR-F6CE-IG9600-L2XB

E

E

FAR-F6CE-2G4500-L2WA

E

100 Wireless LAN .'

Part
Symbol

Part number

Package
Size

Center
freQ. (MHz)

2 4 5 0, 0

7-68

FREQUENCIES

F6

CL2

SERIES

Type)

IIIELECTRICAL CHARACTERISTICS (STANDARD VERSION)
1.

P 0 C 1. 5 G sys tem
Part number

CT x)

F AR-F 6 CC- 1 G 4 4 1 0 -L 2 ZA
Rating

Item

Symbol

Condi tion

Unit

Min.

Typ.

Max.

1429 .......,1453 MHz

-

2.5

3.5

dB

In-band ripple

1429 .......,1453 MHz

-

1.0

1.8

dB

Absolute
stopband

DC

.......,1200 MHz

20

26

-

dB

att~nuation

1200 -1260 MHz

25

30

-

dB

1260 -1287 MHz

30

34

-

dB

1287 -1380 MHz

25

29

-

dB

1477 -1513 MHz

10

14

-

dB

1513 -1607 MHz

33

39

-

dB

-" 1607 """"1631 MHz

35

39

-

dB

1631 -1900 MHz

30

38

-

dB

1900 -2906 MHz

18

20

-

dB

1429 .......,1453 MHz

-

1.3

2.0

-

1429 ---1453 MHz

-

-

200

mW

Insertion loss

IL

In-band VSWR
Max. input power

PIN

Remarks

III

7-69

F6

SERIES

(L2

Type)

IIIELECTRICAL CHARACTERISTICS (STANDARD VERSION)
2.

poe 1. 5 G system
Part number

(R x)
FAR - F 6 C C - 1 G 4 8 9 0 - L 2 Z B

Rating
Item

Symbol

Min ..

Unit

Typ.

Max.

1477 --1501 MHz

-

2.9

3.2

dB

1477 --1501 MHz

-

1.2

1.7

dB

Absolute
stopband

DC -- 130 MHz

30

38

-

dB

att~nuation

130 -- 958 MHz

20

26

-

dB

958 --1216 MHz

25

27

-

dB

1216 --1241 MHz

30

32

-

dB

1241 --1429 MHz

26

28

-

dB

1429 --1453 MHz

10

17

-

dB

1542 --1566 MHz

20

40

-

dB

1566 --1607 MHz

30

40

-

dB

1607 --1631 MHz

35

40

-

dB

1631 --1737 MHz

30

40

-

dB

1737 --1761 MHz

35

40

-

dB

1761 --1900 MHz

30

37

-

dB

1900 --3000 MHz

. 15

20

-

dB

1477 --1501 MHz

-

1.4

2.0

-

1477 ---1501 MHz

-

-

200

mW

Insertion loss

IL

In-band ripple

-

In-band VSWR
Max. input power

7-70

Condi tion

PIN

Remarks

F6

(L2

SERIES

Type)

_

ElECTR I CAL CHARACTER I ST I CS (STANDARD VERS ION)

3.

P DeL 5 G system (L 0)

Part number

FAR - F 6 C C - 1 G 6 1 9 0 - L 2 Z N

Rating
Item

Symbol

Condition
Min.

Insertion loss

IL

In-band deviation

-

3.0

4.0

dB

1607 --1631 MHz

-

1.5

2.0

dB

-- 130 MHz

30

38

-

dB

130 --1501 MHz

25

28

-

dB

1737 --1809 MHz

30

35

-

dB

1809 --2500 MHz

20

29

-

dB

MHz

15

25

-

dB

1607 --1631 MHz

-

1.6

2.0

-

--1631 MHz

-

-

200

mW

3214

In-band VSWR
Max. input power

PIN

Max.

1607 --1631 MHz

DC

Absolute
stopband
attenuation

Unit

Typ.

-~1607

Remarks

1.11

7-71

F6

SERIES

(L2

Type)

IIIELECTRICAL CHARACTERISTICS (STANDARD VERSION)
4. DCS1800 system, CTx)
Preliminary
Part number
FAR - F 6 C E - 1 G 7 4 7 5 - L 2 Y A

T.=-30-E5t

Rating
Item
Insertion loss

Symbol
IL

In-band ripple

Absolute
s'topband
attrnuation

Condi tion

Max. input power

PIN

Unit
Typ.

Max.

1710

~1785

MHz

-

3.5

4.5

dB

1710

~1785

MHz

-

2.0

3.0

dB

DC

~1500

MHz

15

17

-

dB

1500

~1670

MHz

20

22

-

dB

1805 ....... 1880 MHz

5

10

-

dB

MHz

22

24

-

dB

3420 ....... 3570 MHz

25

27

-

dB

5130 ....... 5355 MHz

10

20

-

dB

1710 --1785 MHz

-

2.0

3.0

-

1710 --1785 MHz

-

-

100

mW

1880

In-band VSWR

Min ..

~2200

5. DC S 1 8 0 0 system CR x)
Preliminary
Part number
FAR - F 6 C E - 1 G 8 4 2 5 - L 2 Y B

Rema:-ks

T ... = - 3 - - '

Rating
Item

Symbol

Unit

Condi tion
Min.

Insertion loss

IL

In-band ripple

Absolute
stopband
at tenua tion

In-band VSWR
Max. input power
7-72

PIN

Typ.

Max.

1805 --1880 MHz

-

3.9

4.8

dB

1805 --1880 MHz

-

2.0

2.5

dB

DC --1500 MHz

21

23

-

dB

1600 --1710.MHz

26

28

-

dB

1710 --1785 MHz

8

24

-

dB

1920 --2400 MHz

22

24

-

dB

3610 --3760 MHz

22

25

-

dB

1805 --1880 MHz

-

2.0

3.0

-

1805 ----1880 MHz

-

-

100

mW

Remar!:s

F6

SERIES

(L2

Type)

IIIELECTRICAL CHARACTERISTICS (STANDARD VERSION)
6.

pes

system
Part number

Preliminary

(Tx)

F AR-F 6 e E- 1 G 8 8 0 0 -L 2 XA
Rating

Item

Symbol

Condition
Min.

Insertion loss

IL

In-band deviation
Absolute
stopband
attenuation

In-band VSWR
Max. input power
7.

PIN

--

Unit
Typ.

Max.

1850 --1910 MHz

-

3.5

4.5

dB

1850 --1910 MHz

-

1.5

2.5

dB

DC -1500 MHz

22

24

-

dB

1500 -1800 MHz

25

28

-

dB

1930 -1990 MHz

5

8

-

dB

3700 -3820 MHz

20

24

-

dB

5550 -5730 MHz

4

5

-

dB

1850 --1910 MHz

-

1.8

2.5

-

1850 -1910 MHz

-

-

100

mW

pes

system (R x)
Prel iminary
Part number
FAR - F 6 e E - 1 G 9 6

a a-

Remarks

1.11

L 2 XB
Rating

Item

Symbol

Condition

Unit
Min.

Insertion loss

IL

In-band deviation
Absolute
stopband
attenuation

In-band VSWR
Max. input power

PIN

Typ.

Max.

1930 --1990 MHz

-

4.0

4.8

dB

1930 --1990 MHz

-

2.0

2.8

dB

DC --1500 MHz

22

24

-

dB

1500 --1850 MHz

25

28

-

dB

1850 --1910.MHz

10

25

-

dB

3920 --4040 MHz

20

23

-

dB

1930 --1990 MHz

-

1.8

2.5

-

1930 --1990 MHz

-

-

100

mW

Remarks

7-73

F6

SERIES

(L2

Type)

IIIELECTRICAL CHARACTERISTICS (STANDARD VERSION)
8. W ire 1 e s s - LAN system

Part number

Prel iminary

FAR - F 6 C E - 2 G 4 5 0 0 - L 2 WA

Rating
Item

Symbol

Unit

Condi tion
Min.

Insertion loss

IL

In-band ripple

Absolute
stopband
attef1uation

In-band VSWR
Max. input power

7-74

PIN

TyP.

Max.

2400 --2500 MHz

-

4.5

5.5

dB

2400 --2500 MHz

-

2.3

3.5

dB

DC --1700 MHz

20

25

-

dB

1800 -2200 MHz

25

28

-

dB

2700 --3100 MHz

30

34

-

dB

4800 -5000 MHz

15

18

-

dB

2400 -2500 MHz

-

2.0

3.0

-

2400 -2500 MHz

-

-

mW

Remarks

F6

CL 2

SERIES

T y p e)

T Y PIC ALe H A RAe T E R 1ST I C S ,(STANDARD VERSION)

_

1.

P DeL 5 G system

(T x)
FAR - F 6 C C - 1 G 4 4 1 0 - L 2 Z A

Part number

CHI S21

1:1 ClB/

1011 MAli

PDC-T~

REF 0

1: -2.3101 CIS
00 0 o MHz

ClB

I;-~

\

CO"

!

i: -2."

~ 8A~

:!I: -HI

t3 de

I • .c

CO ..

-1~6 ~ GA~

"

~

2.71:1711 ..

PDC-TX

liHz

1.";

\

Hld

CHI 811/14 1 U FS

1 .c2ll.

Hld

/'\.

~

-- /

/
-':'

1M'\.

..

CEHTER S ..:sO. 000 000 HHz:

1

CHI 811/14 SNR
PDC-T~

/

\ N

SPAN

1:

REF S

I

"00.000 000 HHz

2

•

\I.,

CH2 822/14 1 U FS

8PAN

.coo. 000

3.1511111..

000 14Hz:

391. 1:11:1 pH \

1 "28. 00 0 o HHZ

::

CO"

1.181111

CENTER 1 "110.000 000 14Hz:

•

3111
36Hz:

1~.4

....
3

F 1.1:1
22

,

~7l"

...,z:

733
16Hz:

Hld

Cor

I~
CENTER 1 ":SO. 000 000 HHz:

W

it

"

8PAN

"00.000 000 14Hz:

Hld
5T ART 1 2110,000 000 14Hz

STOP 1 111:10,000 000 14Hz

~------------------------------------------------------------------~

7-75

SERIES

F6

_TYPICAL

2.

CHi

C H A R ACT E R 1ST I C S (STANDARD VERSION)

P 0 C 1. 5 G system (R x )
Part number
FAR - F 6 C C - 1 G 4 8 9 0 - L 2 Z 8

Szt

loa MAG

II 138/

1: -28 8:U 138

REI" 0 138

PDC-f'K

/!
co,.

Ty p e)

(L 2

I

!

~t

_\

I

\

.211. 00 0

o

it -til.
1..

ill.A:

... _ , '7 •

•• 1311

1 ....

IDiZ

~

-2 ••
1 II

•• 128.

CHt 5tl/H 1 U FS

Q

-14. !578 ".

POC-AX

MHZ

Co,.

ti.A~
HId

HId

~
~
...........

, /
--

I

CENTER 1 41S0. 000 000 HHz

CHI S •• /H SWA

V\

~

1

4

1\ £

8P"'"

REI" 1

1:

PDC-f'

CENTER 1 41S0. 000 000 MHz

.00.000 000 HHz

1 /C2B.

•

co,.

13.1415

00 0

.

IS.
1..

o

CH2 522/1<

1 U FS

1:

3.7"151

SPAN

Q

400'.000 000 HHz

8.3115 ..

Q

HHz

SIl~HZ

· 1.4: 17I",...CiHZ

\

•

1. 153
1.11 1 GHZ

HId

Cor

I

CENTER 1 .ISO. 000 000 MHz

7-76

rJ
~ SIt...,.
3

"

HId
.00.000 000 MHZ

5T ART 1 2150.000 000 MHz

STOP

1 81S0. 000 000 HHz

F6

_TYPICAL
3.

y p e)

C HA R AC T E R 1ST I C S (STANDARD VERSION)

poe 1. 5 G system (L 0
Part number

CHi 1021

T

(L 2

SERIES

)

FAR - F 6 C C - 1 G 6 1 9 0 - L 2 Z N

log MAG

1I ClII/

II

Cor

1,; -32 11112 ClB

REF 0 ClII

PDC-I.P

~

00 OC

o

-3.0
1.11

~BG~~

1 1101.

tl"\

z

5

..

-

Q,

." df

1.": 1 UtiZ
;I -~15~

1\

V

,.- ~ f'\

.

SWR
CH' 10 ..
PDC-lP

/

IY

~.IIOlll

n

Cor
Del

&I

INt----

SPAN

~Oo.

REF ,

~

000 000 14Hz

1 1501i, 00 OC

I
I
I
I
I

\
\

36.3.2

1,;

I
I

I

Cor
Del

1.311117 n

~

CENTER 1 1520.000 000 MHz

,

1,;

Hld

\r

\}

' U FS

PDC-LO

'3G~~

1\

HId

CHI lOll

14Hz

.

!

o

CENTER 1 1520.000 000 MHz

CH2 522

1 U FS

1,;

2.71139 n

SP,t.N

400.000 000 MHz

II.O~2l1

n

IISII.II

pH

14Hz

~II' l~a2H2

1

1.'"

IllO.
, lltiz

. 1'9! l,oaHl'

II
Hld

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7-77

F 6

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T Y PIC ALe H A RAe T E R 1ST I C S (STANDARD VERSION)

_

4. 0 C S 1 8 0 0 system (T x)
Prel iminary
Part number
F A~ - F 6 C E- 1 G 7 4 7 5 - L 2 YA

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SERIES

F6

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T Y PIC ALe H A RAe T E R 1ST I C S .(STANDARD VERSION)

_

5. 0 C S 1 800 system (R x)
Preliminary
FAR - F 6 C E - 1 G 8 4 2 5 - L 2 Y B
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______________________________________________________________~7-79

F 6

SERIES

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Ty p e)

A L C H A R ACT E R 1ST I C S

(STANDARD VERSION)

6. P C S system (T x)
Prel iminary
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F6

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(STANDARD VERSION)

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7-81

F 6

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SERIES

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T Y PIC ALe H A RAe T E R 1ST I C S (STANDARD VERSION)

_

8. W ire I e s s - LAN system
Prel iminary
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F

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"MEASURING CIRCUIT

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CD@

TIT

"PART NUMBER

III

DESIGNATION

[Designation example]
FAR - F 6 CO-O i I 0 ] - L 2 ITJ-O

@ @
Q)Package designation:

c

C: 3. 8mm x 1.6 mm
E : 3. 0 mm c x 1. 2 mm

Refer to

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(IDFrequency
designation:
[Ex amp IeJ

Specify the nominal frequency in six alphanumeric
characters. Enter G(for GHz) at the decimal point.
Refer to standard friquencies.
1. 4 4 lOG H z

<>

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Specify a number from WA to ZZ.
Refer to standard friqueneies.

@Paeking:
(Reeled tape)

T : 1 K pes/ ree I
R : 3 K pes/ ree I
7·83

F6

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_DIMENSIONS

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Part

Symbol

F AJ
B Ii

DATE CODE

--------~ I'-

\

LOT No.

I

7·85

F

6

SERIES

(L

"PACKING:Reel

2)

type

(1)Reel dimension

12. 4±~: ~

IE 18. 4J2..{T

Type

A

Volume

-T

250

1 Kpcs

-R

330

3 Kpcs

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Pulling side

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Package

R

W

K

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4.2 ± O. 1

1.8

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3.4 ± o. 1

3.4 ±

o.

1

1.5

Unit:mm

cO

October 1990
Edition 1.0

FUJITSU

DATA SHEET

M2 Series (D100)
PIEZOELECTRIC DEVICE
VOLTAGE CONTROLLED OSCILLATOR
DESCRIPTION
The M2 series (0100) voltage controlled oscillators (VCO) operate in the frequency range of 4 to 30 MHz.
The M2 series VCOs use a single UTa03 (lithium tantalate) piezoelectric crystal
with a high electromechanical coupling coefficient for stable and wide variable frequency width.

FEATURES
•

Wider variable frequency width than quartz crystals: ± 0.2% or more

•

High stability (100 times more stable than LC configuration)

•

Excellent carrier noise ratio

•

Hermetically sealed in a metal case for high reliability in severe environmental
conditions

•

Compatible with 14-pin DIP IC packages

Metal Case
DIP-14

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Symbol

Ratings

Unit

Power Supply Voltage

Vee

-0.5 to 7.0

V

Input Control Voltage

Parameter

V1N

-0.5 to 10

V

Output Voltage

VOUT

-0.5 to Vee +0.5

V

Output Current

lOUT

±25

mA

Ta

-30 to +85

°C

TSTG

-40 to +100

°C

4t030

MHz

Operating Temperature
Storage Temperature

RECOMMENDED OPERATING CONDITIONS
Symbol

Ratings

Unit

Power Supply Voltage

Vee

4.75 to 5.25

V

Input Control Voltage

V1N

0.5 to 5.0

V

Operating Temperature

Ta

"-

0

t4

8

Bottom

Oscillation Frequency Range

Parameter

70

Ot

-30 to +85

NOTE: Permanent device damage may occur if absolute maximum ratings are exceeded.
Functional operation should be restricted to the conditions as detailed in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

0 ..1

View

Terminal
No.

Terminal
Name

1

V1N1

Control Voltage
Input Terminal

7

GND

Grounding
Terminal

8

VOUT

Oscillation
Output Terminal

14

Vee

Power Supply
Terminal

°C

III

Description

This device contain, cifcuilry to protect !he inputs against
dama941 due to high static voltages or alectric: fields. Howewr. ft
is acfvisecj that normal precautions be taken 10 aYOld application
of any VOltage hi!!her than maximum rated VOltages 10 this high
impedance circuft.

C 1990 by FUJITSU LIMITED

7·87

M2 Series (0100)

STANDARD FREQUENCIES
8.192 MHz

14.318 MHz

17.734 MHz

21.053 MHz

25.175MHz

9.408 MHz

16.000 MHz

18.432 MHz

21.4n MHz

27.338 MHz

11.290 MHz

16.257 MHz

18.816 MHz

22.579 MHz

28.224 MHz

11.580 MHz

16.384 MHz

20.480 MHz

24.576 MHz

28.636 MHz

12.288 MHz

16.934 MHz

ELECTRICAL CHARACTERISTICS
DC Characteristics
Ratings

Item
Output Level
Power Supply Current

Symbol
VOUT
Icc

Condition

Unit
Minimum

Maximum

See the measuring circuit diagram

0.5

-

Vp_p

Load open

-

15

rnA

Measuring Circuit Diagram

Output

I

c,..22pF ±3pF

(CL Is the value Including the measurement probe and the jig capacitance.)

AC Characteristics
Ratings
Item

Symbol

Unit

Condition

Remarks

Minimum Maximum

Oscillation Frequency

Frequency Voltage Stabil-

ity
Frequency Temperature
Stability

7-88

fosc

V1N =2.5V

-0.05

+0.05

%

fH

V1N =4.5V

+0.15

-

%

fL

V1N =0.5 V

-

-0.15

%

Af,Vce

Vec =4.75 V
Vec = 5.25 V

-200

200

ppm

5 V reference, V 1N = 2.5 V

Af, Ta

V1N =0.5 V
V1N =4.5 V

-500

500

ppm

25°C reference -10° to 70°C,
TA = 25°C

Nominal Frequency reference
Vee=5V, T a =25OC

M2 Series (0100)

STANDARD CHARACTERISTICS:
Part Number: M20A-8M192G-0100
Control Voltage and Oscillation Frequency
5,000
...,-')

I

4,000

/<7

3,000

& 2,000

iii

1,000

;;

0

~
~

~

Y

/

,~
~

-1,000

)...--'

..J~

~ -2,000

a -3,000 (~

t

y

-4,000

o -5,000 0

0.5

1.0

1.5

2.0

2.5

3.0

4.0

3.5

4.5

5.0

Control Voltage (V)

Temperature Characteristics
800
700

e-

600

!

500

i

400
300 "-

GI

;;
~
!!I

Ig
....III

1S

0

200

,

100

,../

~

0
-100

---

.../

~

/

_c V

-

~)...

III

-200
-300

-400

-500
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (OC)
Power Supply Voltage Characteristics
VIN - 2.5 V

2,000

'[

.s

&

i
;;
~
GI

Ig
....

1,500
1,000
500
0
-500
-1,000

.!II

-1,500

0

-2,000

'0

4.50

4.75

5.00

5.25

5.50

Power Supply Voltage (V)

7-89

M2 Series (0100)

STANDARD CHARACTERISTICS:
Part Number: M2DA-28M636-D100
Control VoHage and Oscillation Frequency
5,000

I

4,000

3,000

& 2,000

Iii
-6

i'
!

1,000

0
-1,000

~,r

g

-2,000 0-3,000

i

-4,000

~

-5,000 0

0.5

1.0

1.5

----

v--2.0

2.5

,..-

3.0

---' ~

~

4.0

3.5

4.5

5.0

Control Vohage (V)

Temperature Characteristics

I

800

700
600

V

500

./

400

//

300

200
100

/'T

----

o
-100

-200

../

"

.......

/"

l.--""
~

-300
-400
-500
-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (OC)

Power Supply Voltage Characteristics
VIN - 2.5 V

2,000

I.9:
&

fi
-6

g-

GJ

1,500
1,000
500

o

&

-500

g

-1,000

.:

:i
~

-1,500
-2,000
4.50

4.75

5.00

Power Supply Voltage (V)

7-90

5.25

5.50

M2 Series (0100)

STANDARD CHARACTERISTICS:
Part Number: M2DA-12M288-D100
Control Voltage and Oscillation Frequency

i&
i

5,000
4,000
3,000

-6

0

!
S
i

-1,000

f

5

~

2,000
1,000

~
~

-2,000

.-4

y--

~)

~

y-

~~

-3,000
-4,000
-5,000 0

1.0

0.5

1.5

2.0

3.0

2.5

3.5

4.5

4.0

5.0

Control Voltage (V)

Temperature Characteristics

VIN -2.5V

800
700

E

600

!

500

gt

400

'6

300

~

200

GI

III

!
S
III
11III
.",,"

0

..d'

100
0

""U-

-100

-

--.., ) -

- :----

~

V

L

~

III

-200
-300
-400
-500
-40

-30

-20

-10

0

10

20

30

Temperature (OC)

40

50

60

70

so

90

Power Supply Voltage Characteristics
VIN - 2.5 V

2,000

ioS
&
i

'6

~GI

I8

1,500
1,000
500

0
-500
-1,000

.",,"

.!!

'"B

5

-1,500
-2,000
4.50

4.75

5.00

5.25

5.50

Power Supply Voltage (V)

7-91

M2 Series (0100)
Oscillation Spectrum
CARRIER NOISE RATIO OF VCO
REF 10.0dBm
ATT 10dB

MKR

12.288000 MHz

o dBm

ladS

1

SPAN

{\
I\
I \

5.0 kHz

PBW

I \

100Hz

I

UBW
100Hz

J

..J.~

L....l.
SWP 35

\
1\

\.t..

....

c.L

CENTER 12.288000 MHz

SPAN 5.0 kHz

O\l1pUllignal purity (e/N ratio)

APPLICATION CIRCUIT EXAMPLES
Example 1. Connection to CMOS
Vee

Vee
R
OUT

C~'

II

C

~~

~~----~~

@ M2Series ®

o

r--<0:r---;UT
~~----~~

IC

(Reference value)
C = 2010 100pF
R. 1 MO
Ie. 74HC04
74CU04elc.

(0100)

CD

@

M2Series

®

o

(0100)

CD

lR2c.

Example 2. Connection to LS TTL (or CMOS)

-

-0
R

OUT
~

@ M2 Series ®
(0100)

-

-0.4
-0.5 0

..-J~--1.0

-' ~-

2.0

--

~

:)

..-- >--

V

3.0

8.192 MHz

4.0

5.0

Control Vo~age (V)
Oscillation Frequency' M

0.5
0.4

~
CD
g»
j!
()

g!

!c

0.3
0.2
0.1

..___ly

o
-0.1

~

-0.2

0

.~

1"11

'0

"

-0.3
-0.4
-0.5

)-

.---I

:r-

o

,-

.---c. 1---- ~---11.290 MHz

~~

.-1.'----

1.0

2.0

3.0

4.0

5.0

Control Vo~age (V)
Oscillation Frequency' H

0.5
0.4
0.3
0.2

~

0.1

~;r

o

-0.4
-0.5 0

..---<.,-

V

ly---'P'"

1.0

2.0

3.0

Control Vo~age (V)

7-98

..... >

112.288 MHz

y.--<
..-(

-0.3

,...........

..-.J.V

4.0

5.0

M2 Series (0300)
STANDARD CHARACTERISTICS
1B. Control Voltage and Oscillation Frequency Changes
Part Number: M2SC-18M432-D300
Oscillation Frequency: L

0.5
0.4

~
Q)

0.3

~

0.2

IG

fi

0.1

8
5l

>.

0

Q)

c
0

.~

~
·6
--16.384 MHz

;>--

2.0

1.0

4.0

3.0

5.0

Control Voltage (V)
Oscillation Frequency' M

0.5
0.4
~
QI

0.3

~

0.2

.fi
g

0.1

!

~.1

~

~.3 r-~--~~~_--~--~----~----r---~----+---~----~----I

15

o

o

t-----t-----+----+-----+------,I-~------,c-,~,;;.-=--..-<=-+'-..;;.-----+----+-----l 22.579 MHz

~.2

~)o-'

~.4 ~o-=--;----1-----r----r----+----+----1---~~--~--~

~.5 0

1.0

2.0

3.0

4.0

5.0

Control Voltage (V)

Oscillation Frequency' H

0.5
0.4

~
&
c
as
15
C5'

i

1
c

oj

I

-------y

0.3
0.2
0.1
0
~.1
~.2
~.3

~.4
~.5

I~-o

1r---'
1.0

-" ~----

.-----.-J

2.0

y

-"

~

3.0

Control Voltage (V)

7-100

.--!-

....;~---24.576 MHz

4.0

5.0

M2 Series (0300)
2. Oscillation Spectrum
Part Number: M2SC-18M432-D300
Example of f03 ,. 18.432 MHz

REF -1 O~.O_d_a,...m_,......A_TT'T"'""10_d..,.B_...---,.M_K_R~_18..,.4_3_34-,-M_H..,z
10dBI

REF -1 0.0 dBm
10dBI

-10.0dBm

SPAN

ATT10dB

MKR

18.43214 MHz

SPAN
20kHzr--+__+--+__~~~~__~-+__~~

200kHzr-~__T--+__+-++~~~__~-1__~

RBW

RBW

3kHz

300Hz

vaw

VBW

3OOHzr--+--+--+--~-1--~--~-+--~~

3kHz

=

RBW 3 kHz
SPAN 200 kHz

RBW = 300Hz
SPAN 20kHz

=

=

3. Frequency Switch Oscillation Startup CharacteristiCS
The characteristics in the circuit below were measured with Vcc. 5.0 V and VFC

Fo

PG

T

•

5.0 V.

Condition: Vee = 5.0 V
VIN =5.0 V

M2SC-18M432-D300

Fl

~

Oscilloscope

7-101

M2 Series (D300)
4. Frequency and Switching Oscillation Startup Characteristics
A. Condition: Stop ~ 12.288 MHz

Stop ~ 12.288 MHz

2 Vldiv
2J.1S/div
10J.1S

B. Condition: Stop ~ 16.934 MHz

Stop ~ 16.934 MHz

2 Vldiv
2J.1S/div
11J.1S

C. Condition: Stop ~ 18.432 MHz

W
Stop

1,0 -

If> 11
- - - - - - I F-·k
··:l<

~

j~
rl>~
2 Vldiv
2J.1S/div

10J.1S

7-102

18.432 MHz

M2 Series (0300)
PART NUMBERING SYSTEM
[Part Number Example]

M2SC-DDDDDD

 -100

I-

~

-150

f-

J:

-200 ~

g
a-

-250 -

I

-10

I

I

I

I

I

I

I

o

+10

+20

+30

+40

+50

+60

+70

Ambient Temperature (0C)

III

Example 3. Oscillation Spectrum

REF 10.0dBm
IOdS

ATT 10dB

MKR

155.51955 MHz
dBm

MARKER
155.51955MHz
6.4dBm

RBW
300Hz

VSW
1 kHz t--;--t--+--t--f+-lf-+--+---l--+-~

SWP3a

SPAN

so kHz

CENTER 155.5200 MHz

7-107

M3 Series (0001)
PART NUMBERING SYSTEM
(Part Number Example)

M3DA-DDDDDD

o

®

-0

DOD

CD

®

Frequency designation: Designates the nominal frequency in six alphanumeric characters. M indicates the decimal
point in MHz.
Frequency

Designation

74.25 MHz

74M250

97.2 MHz

97M200

115.52 MHz

115M52

Serial Number (of the series):
Standard: 001
Non-standard products: 001 to 099

PACKAGE DIMENSIONS
(Top)

I'

(Bottom)

25.6 Mamimum
(1.008)

Y

'L

17.78 ± 0.5 (0.700 ± 0.020)

..

•

2.54 ± 0.5 (0.100 ± 0.020)

-1

E

I

::I

·xE1\1

0

0

ooOO~o

::::E ......

~~
• It)

'-

@o o 0 0

~e

~

~

')
410.5 (0.020)

""1

@_

7.62±0.5
(0.300 ± 0.020)

(Rear)

0

(

--

0

~

'-

(Side)

'"'

0

"-

---

~

t

~

o

+1
01

ItS

~11
+.

_CD _ _

0

e.

0
+1
N
C')

"!

e.

~

q
~

0
+1

o ,...
+101
o --:

1tSe.

0

..,.+1
0
Units: mm (in.)

7-108

cfJ
===EditiO~n
1.0~~~~~~====-~FUJITSU
===
DATA SHEET
October 1990

M3 Series (D101)
Piezoelectric Device
Modulator, 50 MHz to 300 MHz

DESCRIPTION
These piezoelectric modulators feature direct oscillators (50 MHz to 300 MHz). The
piezoelectric modulator uses a lithium tantalate piezoelectric single crystal (LiTa03)
with a high electromechanical coupling coefficient. The piezoelectric modulator
employs an exclusive SAW resonator. The piezoelectric modulator can be used in
direct modulation applications needing high modulation sensitivity and a high signal
noise ratio in the VHF band (up to 300 MHz).

FEATURES
•

High frequency direct modulation:

50 to 300 MHz

•

High modulation sensitivity:

800 ppmIV min. (0.5 to 4.5 V)

•

Excellent modulation distortion ratio: 40 dB max. (1 KHz to 1.75 KHz dev.)

•

Excellent signal noise ratio:

•

Excellent temperature characteristic: ±200 ppm max. (-20 to 70°)

-50 dB max.

•

Highly reliable hermetically sealed package

•

Compatible with 14·pin DIP Ie packages

Power Supply Voltage

Symbol
Vcc

Unit

-0.5 to 7.0

VML

-0.5 to 10

V

VMM

-0.5 to 7.0

V

III

70

80

ML
4

Negative
Ta

-20 to +85

°e

TSTG

-40 to +100

°e

RECOMMENDED OPERATING CONDITIONS
Parameter

14

ermlnal No. Terminal Name

Positive

Operating Temperature
Storage Temperature

o

V

MM Pin Input Voltage

MM Pin Modulation Polarity

40

1

(See Note)

Ratings

ML Pin Input Voltage

ML Pin Modulation Polarity

OIP·14

~================~
(Bottom View)

o

ABSOLUTE MAXIMUM RATINGS
Parameter

Metal Case

Symbol

Ratings

Unit

Power Supply Voltage

Vcc

4.75 to 5.25

V

ML Pin Input Voltage

VML

2.5

V

Operating Temperature

Ta

-20 to 70

°e

MM

Description
Control Voltage
Input Terminal
Modulation Input

GND

Grounding Terminal

8

VOUT

Oscillation Output
Terminal

14

Vee

Power Supply
Terminal

This device contains circuitry to protect the inputs
against damage clue to high static voltages or electric
fields. However, it is advised that normal precautions
be taken to avoid application of any voltage higher
than maximum rated voltages to this high impedance
circuit.

Note: Permanent device damage may occur if absolute maximum ratings are
exceeded. Functional operation should be restricted to the conditions
as detailed in the operation sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

Copyright

©

1990 by

FUJITSU LIMITED

7-109

M3 Series (0101)
STANOAROFREQUENCY
Standard Frequency

Application

Part Number

145.0 MHz

Mobile Phone

M3DA-145MOO-D 101

ELECTRICAL CHARACTERISTICS
(Vee =5.0 V)

Ratings
Symbol

Hem

Condition

Min.

Typ.

-

Max.

Unit

+300

ppm

Remarks
fo reference

Afo

VUL - 2.5 V

-300

(tH-td

800

to

VUL " 0.5 V
VUL - 4.5 V

-

Af(Ta)

VUL - 2.5 V

-200

-

+200

ppm

25°C reference,
Ta'" -20 to 70°C

POUT

VULc 2.5 V

-5

-3

-1

dBm

50.Q termination

Output Level Stability

AP (VF)

VUL " 0.5 V
VML .. 4.5 V

-2

-

+2

dB

VML =2.5 V
reference

Output Level Temperature
Stability

AP (Ta)

VML-2.5 V

-2

-

+2

dB

25°C reference,
Ta" -20 to 70°C

-

-

10

mA

-SO

-

+50

ppm

1.75 KHz DEV

-

-

-40

dB

3.5 KHz DEV

-

-

-40

dB

5.0 KHz DEV

-

-

-40

dB

1.75 KHz DEV

-

-

-50

dB

Oscillation Frequency Deviation
Variable Width of Oscillation
Frequency
Temperature Stability of
Oscillation Frequency
Output Level

Current Consumption

lee

Oscillation Frequency Power
Supply Voltage Fluctuation

Af(Vcc)

Modulation
Distortion
(1 KHz tone)
Modulation
Characteristic

Signal to Noise
Ratio
Modulator Input
Impedance

VUL " 2.5 V

10

-

ppmN

±5%at Vee'" 5
V
reference

15 KHz LPF

300 to 3 KHz

KQ

PART NUMBERING SYSTEM
Designation Example
M3DA-DDDDDD - DODD

0·

7-110

®

®

Frequency Designation:

The standard frequency is designated in six alphanumeric characters. M is used to
designate the decimal point in MHz. Refer to STANDARD FREQUENCY.
Example: 145.0 MHz device is designated as 145MOO.

Serial Number:

The serial number is assigned from 101 to 199 (with 101 as the standard).

M3 Series (D1 01)
PACKAGE MARKING
(Bottom View)
Fujitsu Logo

Part Number

\

I

SV-145M
0101

0

t
Lot number

Index

PACKAGE DIMENSIONS
Units: mm (in.)
15.2 (0.598)

f

•

7.6
(0.299)

t

13.1 max.
(0.516)

•

J

20.8 max. (0.819)
18.3 (0.720)

I:--+----

1
----,

-~n===:::;tr===:;;::~

'I

6.3
(0.248)

5.0

(0.197)

7-111

M3 Series (0101)
SAW MODULATOR CHARACTERISTICS
M30A-145MOO-0101
Characteristics

Rating

Item
Output Frequency

145.0 MHz

144.997 MHz

Current Consumption

10 mA or less (with buffer)

7.3mA

Output Level

-3dBm ±2 dB

-2.00 dBm

Spurious Response Ratio

Higher harmonic < 4 dB at 2 fo (290 MHz)

-7.3 dB

Power Supply
Fluctuation

Within ±50 ppm for 5 V ±0.25 V

+6.00 ppm
-5.80 ppm

AFC-F-F
Characteristic

±550 ppm or more for 2.5 V ±1 V

-789 ppm
+1016 ppm

Temperature
Characteristic

Within ±300 ppm for -35 to +85

+66 ppm
+41 ppm

Frequency
Stability

AFC Voltage Versus Output
Frequency Characteristics
Modulation
Input Level

At 25 ±5°C, the AFC voltage for the output frequency
of 145 MHz is V~ .. 2.5 V +0.3 V
At -20 +85°C, the AFC voltage for the output
frequency of 145 MHz is Vc .. 2.5 V ±0.3 V

Signal Noise
Characteristic

Vc

= 2.5 V

-28 dBm ±3 dB (600 W)
1 KHz ±3.5 KHz DEV·

-20°C
+85°C

-26.1 dB

15 KHz LPF

-46 dB
-49 dB
-48 dB

15 KHz LPF

< ±1 dB120 Hz to 5 KHz ±5 KHz DEV·

-55 dB

< -50 dB ±1. 75 KHz DEV·

Test Circuit

Vee

Modulation
Analyzer
HP8901B

14

8
OUT

4

7-112

= 2.5 V

2.476 V
2.459 V

*Adjust the control voltage for an oscillation frequency of 145 MHz for the modulation characteristic.

Vc

Vc

2.501 V

-35 dB or less 1 KHz (±1.75 KHz DEV)·
Modulation
Distortion Ratio -30 dB or less 1 KHz (±3.5 KHz DEV)·
-20 dB or less 1 KHz (±5.0 KHz DEV)*
Modulation
Modulation
Characteristic Characteristic

Remarks

7

Audio Analyzer
HP8903B

300 to 3 KHz

M3 Series (D1 01)
M30A-14SMOO-D101 MODULATION FREQUENCY CHARACTERISTICS
/

/

N

r--.:I:
~
r--. Ii)

/

/

I

1
I

co
C")

0
z

T
J

[

V~
....

III
0

0
,...

....

0

CD
~

.

c
"n;
....
0
(!)-+-

..

..

-i-"t

7-113

M3 Series (0101)

SAW MODULATOR CHARACTERISTIC DATA
M30A·145MQO-0101
No. ES-38 0

.- -

0
-1

-2
-3
-4 Output Level
(dBm)

-5
-6

-7

0.6~--------------------------------------------------~

-8

0.5

0.4

Oscillation
Frequency
Variation

(0/0)

0.1

o t-------~'i:J'---------------------__t
-0.1
-0.2
-0.3
-o.4~~--~~---~---~-------~---~--~~--~---------~~
o
3
4
7
8
2
5
6
Control Voltage, Vc (V)
V-F Characteristic

7·114

145.00 MHz

M3 Series (0101)

SAW MODULATOR CHARACTERISTIC DATA (Continued)
M3DA-145MOO-D101
No. ES-3S0

2
Output Level
Fluctuation
(dB)

o

A

_~'
I

-1

I

--+--+--+--

-2
500
400
300
200
Oscillation
Frequency
Variation
(ppm)

III

100
0
-100
-200
-300
-400
-500
-40 -30

Frequency
Variation
(ppm)

+20

100
SO
60
40
20
0
-20
- + ...... ... + ...
-40
I
I
-60 - - - +I - -80
-100 4 .7
4.S

o

-10

10

20

30

40

50

60

70

80

90

Temperature (OC)
Temperature Characteristic
.... -

... ... + ... -

- + ... ... -+ ... ...

I

... + ... -

-- + -

I

...

I

- + ......
I

.... I

... - .......... + ...... - + ... ... - ....... - .................... + ... ...
I

•

I

I

I

I

I

... -+ ......
I

4.9

5.0

5.1

5.2

5.3

Supply Voltage (V)
Supply Voltage Fluctuation

7-115

7-116

SECTION 8
Power Management Switches - At a Glance
The typical cellular handset typifies the recent trend towards compact, lightweight, battery dependent products that can be used anywhere, anytime. Fujitsu's innovative power management switches can effect a
reduction of power consumption in the "OFP state, thereby extending battery life.

Page
Number

8-3

8-17

Part
Number
MB3802

'ON'
Resistance

Maximum
Handling Current
1.2 A

(dual switches)

0.120

per channel

MB3807A

0.30 (12 V port)
6.0 0 (5 V port)

0.5 A (12V port)

(dual switches)

0.1 A (5V port)

Comment
Well suited for most
portable radio applications
Designed for PCMCIA
card controllers; will
have niche application
to wireless products

•

8-1

8-2

00

February 1995
Edition 1.0a

DATA SHEET

FUJITSU

MB3802
POWER MANAGEMENT SWITCH
DESCRIPTION
The MB3802 is a dual power management switch incorporating two
identical switch circuits which have extremely low ON resistance and
consume zero input current when the switches are turned OFF. These
features effectively reduce power consumption and extend the battery
life of portable, battery-driven products. The MB3802 can be used to
efficiently control various power supply systems for Notebook Computers and typical peripheral devices such as Disk Drives and PCMCIA
Cards.

16-pin plastic SOP
(FPT-16P-M04)

The MB3802 switch blocks turn on at a very low input voltage (typical VIN
> 2.2 V) and a stable ON resistance is obtained irrespective of the
switching voltage since the internal DC/DC converter applies the
optimum voltage for the N-ch MOS gate at Switch-ON.
No external diode is required because the switch block is configured with
an N-ch MOS structure to prevent the flow of reverse current at
Switch-OFF.

•

Additionally, a load-side capacitor can be discharged at Switch-OFF by
an intemal discharge switch which is operated by an extemal control pin.

FEATURES
• Extremely low ON resistance:
- RON = 0.12 n (typical)
- RON = 0.06 (typical for parallel connection)

n

• Reverse current protection at load side at Switch-OFF
• Operation start at low input voltage: VIN > 2.2 V (typical)
• Low power consumption
- At Switch-OFF: liN = 0 ~, VIN = 0 V
- At Switch-ON: liN

=230 ~, VIN =5 V

• Load discharge function
• External control of ON/OFF time
• Break-before-make operation
• 16 Pin Plastic Flat Package (Suffix: -PF)

Copyright 4:>1995 FUJITSU UMlTEO. Fujnsu Microelectronics. Inc.

ThiS device contains circunry to protect the inputs against
damage due to high static vohages or electric fields.
However. it is acJvised that normal precautions be taken to
avoid application of any vohage hi~.r than maximum rated
vohagaa to this high impedance circun.

8-3

MB3802

BLOCK DIAGRAM AND EXTERNAL CONNECTIONS
Co
External capacitor

7},-

Note: The MB3802 incorporates two switch blocks as shown above. However, GND is common to both blocks.

PIN ASSIGNMENT
(TOP VIEW)

0

GNDA

16

VINA

DCGA

2

15

DlYA

SWINA

3

14

SWOI,ITA

SWINA

4

13

SWOUTA

MB3802
SWINS

5

12

SWOUTB

SWINS

6

11

SWOUTB

DCGs

7

10

DlYs

GNDs

8

9

VINS

(FPT-16P-M04)

8-4

MB3802

BLOCK DESCRIPTION
When V,N exceeds 2.2 V, the Comparator starts driving the DC/DC converter which boosts the V,N voltage in order to
switch the N-ch MOS, applying the optimum voltage to the switch gate.
When V,N is below 2.1 V, the Comparator stops the DC/DC converter, starts the Switch-OFF circuit, and discharges the
voltage from the switch gate to GND. The Switch-OFF circuit is powered from the SW,N and consumes 0.4 JlA at 5 V.
Since the N-ch MOS back gate is connected to GND, Switch-OFF reverse current is prevented irrespective of the High
level state between SW,N and SWOUT.
The load discharge circuit installed between SWOUT and GND is powered by the DCG pin, and discharges the load-side
capacitor at Switch-QFF. When it is not necessary to discharge the load, connect the DCG pin to GND.
The DlY pins are for connection to an extemal capacitor to delay the Switch-ON/OFF time. The surge current at the
load side is reduced during power-on by controlling the Switch-ON time. The Switch-ON time is also dependent on the
boot time of the DC/DC converter.

PIN DESCRIPTION
1. Power Management Switch
Pin No.

Pin Symbol

Description

16

VINA

9

VINe

Switch Control Pins: These input control pins drive the Switch-ON with a High input level and
Switch-OFF with a Low input level. They also serve as power-supply pins for the DC/DC converter to
generate the switch gate voltage.

3,4
5,6
13, 14

SWINe
SWOUTA

11,12

SWOUTB

2

DCGA

7

DCGe

15

DLYA

10

DLYe

SWINA

1

GNDA

8

GNDe

Switch Input pins: Two common pins are assigned to SWINA and SWINe. They serve as input
power supply pins for the Load Switches and the Switch-OFF circuit.
Switch output pins: Two common pins are assigned to SWOUTA and SWOUTB. They are typically
connected to the high side of the controlled load. When DCGA or DCGB are al a High level, the
respective load-dlscharge circuits implement the discharge function via these pins.

III

SWOUTNSWOUTB discharge control pins: These pins are used to control the discharge of the load
at Switch-OFF. Connect them to GND when the discharge function is not required.
Switch-ONiOFF time control pins: The ON/OFF time can be delayed by connecting an external
capacitor. Both times are delayed about three fold by installing a SOO-pF capacitor between these pins
and GND. Leave these pins open when they are not used. 10 V may be generated when these pins
are open. To keep these pins at high impedance, take care 10 mount the device so that there is mini·
mal current leakage (less than 0.1 JlA).
Ground pins for Input threshold reference voltage and load discharge: When two switching
circuits are used, ground both GND pins.

8-5

MB3802

ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter

Symbol

Input voltage

-

V,N

Switching voltage
Switching current
Total Power Dissipation
Storage temperature

Condition

Ratings

Unit

-0.3 to 7.0

V

At Switcll-OFF

-0.3 to 7.0

At Swltcll-ON

-0.3 to 7.0

V

Vsw
Isw

At Switch-ON peak

3.6

A

Po

Ta S+75 °c

290

mW

-55 to +125

°c

-

Tstg

2. Recommended Operating Conditions
Ratings
Parameter
Input voltage
Switching level

Conditions

-

V,N
VSWIN

Unit
Min.

typical

Max.

0

-

6.0

V

At Switch-ON

0

-

6.0

At Switcll-OFF

0

-

6.0

At Switcll-ON (for single switch)

-

-

1.2

A

V

SWitching current

Isw

DLY-pin connection capacitance

CD

-

-

-

10

nF

IDLY

-

-0.1

J.lA

2.5

-

0.1
6.0

V

-40

-

+75

°c

DLY-pin mounting leak current
Input voltage to load discharge circuit
Operating temperature

8-6

Symbol

VOCG
Top

V,N=3V,5V

-

MB3802

3. DC Characteristics
Parameter

Symbol

Min.
Input Current

Switching Resistance

Switch-OFF leak current

Unit

Ratings

Conditions

Typical

Max.

IIN1

VIN=OV

-

0

-

IIN2

VIN=3V

-

100

200
460

VIN=5 V

-

230

RON1

VIN = 3 V, Isw = 0.5 A, VSWIN = 3 V

120

160

RON2

VIN = 5 V,lsw= 0.5 A, VSWIN =3 V

-

130

175

=0 V, VSWIN =6 V

JlA
JlA
JlA
mO
mO

0.5

2.0

VTH1

At Switch-ON

2.0

2.2

2.4

V

VTH2

At Switch-OFF

1.9

2.1

2.3

V

Input hysteresis

VHVS

-

50

100

mV

RON

=3 V, 5 V, Isw = 0.5 A
Ta =-40° to +75°C

-

-

-

Switch resistance

ROCG1

VSWOUT = 3 V, VOCG = 3 V

1500

VSWOUT

-

750

ROCG2

500

1000

n
n

0

2

JlA

Input threshold voltage

Switch charge resistance

Input current to Switch discharge
circuit

IL

IOCG

VIN

VIN

=5 V, VOCG = 5 V

VOCG=5V

210

JlA

mO

r--;;;o

4. AC Characteristics
Parameter

Symbol

Conditions

Switch-ON time

Switch-OFF time

Switch-ON/OFF time lag

Unit

Ratings
Min.

Typical

Max.

lON1

VIN =OV->3V, VSWIN=3 V

100

300

900

J.I.S

toN2

VIN = 0 V -> 5 V, VSWIN = 5 V

50

150

450

J.I.S

toFF1

VIN = 3 V -> 0 V, VSWIN =3 V

20

60

180

J.I.S

toFF2

VIN =5 V->OV, VSWIN =5 V

10

30

150

J.I.S

ltiVS1

VIN=3v/OV, VSWIN=3V

80

240

720

J.I.S

ltivS2

VIN = 5 V/O V, VSWIN = 5 V

40

120

300

J.I.S

8·7

MB3802

AC CHARACTERISTIC TEST DIAGRAMS
1. Test Condition
Open

SW,N

MB3802

rI

SWOUT

Vs= 3 VIS V

R

Load "'...., . 1A

R=3!l1S!l

2. Switch-ON/OFF Timing Chart
t,.
,-.-...
I

I

I

•

I

.,-

I

tt

I

~

______________

•

,

~.,

90%

I

OV
90%
SWOUT

OV

toN

SWOUT

10%

Note: The riselfalltimes (1 0%/90%) OfV,N are both less than 1~.

8-8

0V

MB3802

APPLICATIONS
1. Separate Use of Two Switching Circuits

SWINA __+-------------,
SW~AI------------~

MB3802

GND

Notes:
1. The two power supplies VSA and VSB can be used separately by controlling the voltages VINA and VINB.
2. Connect the DCG pin to GND when it is not used.

2. Switching Two Power Supplies

VINA

SWINA
SW~A

MB3802
SWINB

VINB
GND

SW~B

DlVA

I

VSB

VSA

Imsv

Note: When using different power supplies tor a single load, control them by connecting an extemal capacitor so that both
switches are not ON at the same time.

8-9

MB3802

3. Switching Two Loads

SWOUTA I-----------l~--__.

MB3802

GND

Vs

Note: Make this connection to control two different loads separately using a single power supply.

4. Connecting Serial Switches

GND

Vs

Note: Make this connection to supply power from Vs to load B via load A.

8-10

MB3802

5. Connecting Parallel Switches

SWINA 1-+--------4---------.
SWOUTA 1-"'--,

MB3802
SWINB 1-+--+----....
GND

SWOUTB

Vs

Note: Connect the circuits A and B in parallel to produce a low ON resistance (RoN =0.060). In this case, connect
the DlYA and DlYB pins in common to give synchronous ON/OFF between both switches.

6. 25% ON Resistance

DlYA

SWINA .....-+---~I---------,
SWOUTA

MB3802
SWINB I-+--t--.
SWOUTB ........-

...-t---...,

Vs

DCGe

DCGA
DlYA

load

SWINA 1-+--1--'
SWOUTA I--+--'

MB3802
SWINe 1-+--1---'
SWOUTB
DCGe
Notes:
1. Make this connection to produce an ON resistance that is much lower than the single device parallel switch
connection (as shown In 5.) Also, connect the DlY pins in common.
2. Consider the differences between the ON resistances and the Switch-ON/OFF times between the two devices
(MB3802) and insure that load control is not offset at one device.

8-11

MB3802

7. Low-side Switch

r -_ _ _
V_IN_A_.....

SWINA t - - - - f
SWOUTA

MB3802
SWINS t - - t - - - f
GND

SWOUTB
DLYs
Rs

VIN=3 v, Vs=3 V
Switch·ON time
Switch·OFF time

SOilS
5.0mS

VIN=5V, Vs=5V
451lS
3.5mS

Notes:
1. Make this connection to control the Switch-ONfOFF at the lower load side.
2. To assist the Switch·OFF circuit operation driven by the SWIN power supply, connect high resistances (RA and Rs
= 5 to 10 MQ) to the DLY pins without overloading the DCfDC converter.
3. With this connection, the Switch·OFF time is longer than the Switch·ON time.

8-12

MB3802

TYPICAL CHARACTERISTICS CURVES
300

ON Resistance (Input-voltage dependence)

150

ON Resistance (Load current dependence)

Isw=1 A
250 ~~I---'-_.__.ON resistance
-----(mO.)
200 ~--ir--"""'"
-

VSWIN = SV
VSWIN=5V
VSWIN = 4V
VSWIN=3V
VSWIN = 2V
VSWIN = 1V
VSWIN=OV

-+---r--~

ON resistance
(mO)
100~----~~~~--+---~--__~--~

150~~r---r---r---r--r---r-~

50~--~----~--~----~--~~--~

o

ON Resistance
(Temperature dependence: SWIN = 3 V)

0.2

0.4

0.6

0.8

1.0

ON Resistance
(Temperature dependence: SW,N

150~~~--------r---------'---------~---------'

1.2

Load current (A)

=5 V)

150~~~--------r---------'---------~---------'

VswIN=3V
Isw= 1 A

VSWIN = 5 V
Isw=1 A

ON resistance
ON resistance
(mO.)
100 ~-+---=-...-r:.~---+-----+------f
(mO)
100 b.o'~-7""'I~-++--+-----+-----f

VIN=3V
VIN=5 V
50

500

-25

0

25
Ta(Co)

VIN=3V
VIN=5V

50

50

75

Swltch-ON TIme
(Input voltage characteristic: SWIN = 3 V)

500

-25

0

25
Ta (CO)

50

75

Swltch-ON TIme
(Input voltage characteristic: SWIN = 5 V)

VSWIN=3V
Isw= 1 A

VSWIN=5V
Isw= 1 A
400

300

300

Switch-ON
time OJ,S)

Switch-ON
time (J.1S)
200

200

100

100
Ta=+75°C

0
3.0

3.5

4.0
4.5
5.0
Input voltage (V)

5.5

6.0

0
3.0

3.5

4.0
4.5
5.0
Input voltage (V)

5.5

S.O

8-13

MB3802
Swltch-OFF Time
(Input voltage characteristic: SWIM

Switch-oFF Time
(Input voltage characteristic: SWIM

=3 V)

so

100
VSWIN=3V
Isw=1 A

VSWIN = S V
Isw=1 A

I

90

40

I

\

Ta=-2SoC

80
Switch-OFF
time (J,LS)

60

--- --

_.1.

r--- -

-- --

~

SO
3.0

3.S

4.0

---t---

S.O

Input voltage M

-lS.S

Swltch-ON Time
(DLY-pln connection capacitance: SWIM

--- --- ~. 1--- --

~ 1\~

10

Ta=-2SoC
Ta = +2SoC •
Ta=+7SoC

I

o

6.0

~--

I~

20

,Ta= +7SoC

4.S

i---i---- -

Swltch-oFF
tlme(J.1S)

Ta=+2SoC

r..---

,

30

I
70

=SV)

3.0

3.S

4.0

4.S

5.0

Input voltage M

5.S

Swltch-oN Time
(DLY-pln connection capacitance: SWIM

=3 V)

100r--------------r--------------,
VSWIN=3V
Isw=1 A

6.0

=5 V)

100r-------------~------------~

VSWIN=5V
Isw= 1 A

10~----------------~---------~7'~

ON-time
(mS)

ON-time
(mS)

0·1 01oo0~"""'--'--L"""'.L..&..U10"'"0-0--"'"--'-.........L..L...I..Lo.LJ
1 ooo

0., 0'-0---'---I--'-'-.L.I...l.J1i.&00-0---..I...................I....IU-I1..L.10000
Capacitance (pF)

Capacitance (PF)
Switch-OFF Time
(DLY-pln connection capacitance: SWIM

=3 V)

10000 r------------..,--------------,
VSWIN=3V
Isw=1 A

Switch-OFF Time
(DLY-pln connection capacitance: SWIN

=

5 V)
10000 ..._------------------,..------------------,
VSWIN = 5 V
Isw= 1 A

1000r--------------r------~r'--~

OFF-time
(mS)

OFF-time
(mS)
100~--~~~-----r--~------------;

1000
Capacitance (pF)

8-14

10000

100~-----~~~~~-----------i

..............~~~--~--~~~~
1000
10000

10~--~

100

Capacitance (pF)

MB3802
Discharge Resistance
(DCG voltage dependence: SWOUT = 3 V)

Discharge Resistance
.
(DCG voltage dependence: SWOUT = 5 V)

10
VSWOlJT=3 V

VSWOUT= 5 V

Discharge
resistance

Discharge
resistance

(1tCl)

(1tCl)

0.1'-----"---------'------'
345
2
6

0.1 ' - - - - - " - - - - - - - - - ' - - - - - - '
3
4
5
2
6
DCG voltage (V)

DCG voltage M

Output Leak Current (at Swltch-OFF)

Input Current (Input voltage dependence)

1000 ~--__r---_r_--___,r-----,

2oo~--+_--+_---+_--+_~~~

Leak current

(nA)

loo ......-~~----+---+_--_I

Input current

(IJA)
100~----+_----+_~~~~--+_--~

VIN=OV

102~---~3-----~4------5~-----J6

O~----~~~~--~~--~----~

o

1.0

2.0

3.0

5.0

Input voltage (V)

SWIN voltage (V)

Swltch.()n resistance
(relationship between VIN and Vs)

Surge Current and Output Voltage Boot
(DLY-pln connection capacitance dependence)

•

140

~

J
IN

N~

/"
if': ,~ :::--..... 510 pF Output voltage

I IY~ r
OutputGND
InputGND
(Surge current)

i~

Ij

~~

............ "'Open

... 10rO p,

/

I

I I I

....... Open
, / 510 pF Surge current ~ ./ loo0pF

.......

5~~~~~~-+--~~~~~~

4 ~-+-+-~--...,,~Switch voltage
(V)
3~-V~r-~~~~--r-~~

~

2~-+....,o&+--

~

"-

O~~--~~L-~

3.0
Time
VIN=0->5V
SW1N =5V
Load capacitance =47 J.l.F

__~__L-~__~

4.0

4.5

5.0

5.5

6.0

VIN voltage (V)

V: 200 mA/div. (surge current)
V: 1.0 V/div. (output voltage)
H: 200 J.l.S/div. (time axis)

8-15

MB3802
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M04)

400+.010
. -.008

.083(2.10) MAX
(MOUNTING HEIGHT)

(10.15~:~g)

I'

'1
INDEX

cf

~.j-I-+oI.f-

_.O--=5TY0::i-:.(lp=-.27
.....

I

0(0) MIN
(STAND OFF HEIGHT)

f

.252±.016
(6.40±0.40)
.154±.012
(3.90±0.30)

~

.11..(0.O'45±Q8±.O.10)
O4 I-$-I
0.005(0. 13)t9I
'--'-""'-------'
r----------,

_oi"~O.'O~
~
.350(8.89)
REF

©1993 FUJITSU LIMITED F16012S-4C

8-16

I
I
I
I
I
:

I
I
IL

Details of MAM part
.008(0.20)

I
I
I
I
I

.020(0.50):
.00::;8)
.027(0.68)

I
II

_ _ _ _MAX
_____ J

Dimensions in
inches (millimeters)

00

=D~S04-§276~02~-1E§§§§§~~~===-_FUJITSU
=
DATA SHEET

MB3807A ASSP Power Supply BIPOLAR

PowerManagementSwftchmglC

(with flash memory power switching function)
• DESCRIPTION
When data is written to or read from flash memory, it requires that the voltage at its power supply (Vpp) be switched
(to 12 V for writing and to 3.3 or 5.0 V for reading).
The MB3807A is a power management switching IC, designed to be compatible with the PCMCIA digital controller,
to switch the Vpp voltage of flash memory.
When the switch is turned on, optimum voltage is applied to the gate of the internal charge pump N-ch MOS switch,
providing a constant amount of ON resistance. The ON resistance is also kept to be low to reduce voltage drop at
the Vpp pin that is caused by large current flowing when data is written.
In addition, the OFF time is much shorter than the ON time to prevent short-circuiting between the reading and
writing power supplies when the device switches the Vpp voltage for reading or writing data (break-befora-make
operation).

• FEATURES
• Switching at low ON resistance
For writing data: SWIN1 = 12 V, Ron = 0.3 (2
For reading data: SWIN2 =5 V, Ron = 6.0 (2
SWIN2 =3.3 V, Ron = 8.5 (2
• Wide range of supply voltages: Vee =2.7 to 5.5 V
• Prevention of reverse current from the load at switch-off time
• ON time controllable with external pin
• Break-before-make operation

III

• PACKAGE
16 pin Plastic SOP

(FPT-16P-M04)

Copyright©

1995 by FUJITSU LIMITED

8-17

MB3807A

• PIN ASSIGNMENT

(TOP VIEW)
ENh

16

Vee

ENOA

2

15

DLYA

SWIN2A

3

14

SWOUTA

SWINh

4

13

SWOUTA

SWIN1e

5

12

SWOUTe

SWIN2e

6

11

SWOUTe

ENOe

7

10

DLYe

GND

8

9

EN1e

(FPT-16P-M04)

• LOGICAL OPERATION TABLE

8-18

EN1

ENO

SW1

SW2

0

0

OFF

OFF

0

1

OFF

ON

1

0

ON

OFF

1

1

OFF

OFF

.-r-"

MB3807A

• PIN DESCRIPTION
Pin name

i

1

EN1A

I These pins turn the corresponding switches on and off depending on the PCMCIA

9

EN1s

2

ENOA

I

Pin No.

7

ENOB

4

SWIN1A

5

I

SWIN1B

Function
compatible signals, as shown in "LOGICAL OPERATION TABLE."

These pins connect the 12-V power supply for writing data to flash memory. When
the SW1 is turned on, the voltage at the SWIN1 pin is output to the SWOUT pin.
These pins also serve as power supply pins for the charge pump on the SW1 side.
For switching, the pins require a voltage higher than Vec.

I

SWIN2A

3
6

I

SWOUTA

13, 14
11, 12

SWIN2s

These pins connect the 3.3/5.O-V power supply for reading data from flash memory.
When the SW2 is on, the voltage at the SWIN2 pin is output to the SWOUT pin.
These pins also serve as power supply pins for the charge pump on the SW2 side.
For switching, the pins require a voltage higher than Vcc.

I
:

These pins are output pins of the switch. A pair of two pins are used commonly as
: either SWOUTA or SWOUTB pins.
SWOUTB . These pins are connected to the Vpp pin of the flash memory.

15

DLYA

10

DLYB
Vee

16

I

8

I GND

These pins control the switch ON time.
The ON time is controllable using an external capacitor.
: Leave these pins open when not in use. Note that a voltage of about 25 V is
: generated when the pins are open. Since high impedance is required, be careful
I when mounting the device not to generate current leakage.

III

I Power supply pin

I Ground pin

8-19.

MB3807A

• BLOCK DIAGRAM
DLY

EN1

ENO

Note:

The MB3807 A contains a pair of above circuit blocks .

• BLOCK DESCRIPTION
The SWINl and SWIN2 pins are connected to the 12-V and 3.S/S.D-V power supplies, respectively. The SWOUT
pin is connected to the Vpp power supply pin of the flash memory.
When conditions, ENl = "H" and ENO = "L" are established in an attempt to write data to flash memory, the switchon circuit (charge pump) on the SWl side is activated.
The charge pump applies optimum voltage to the SWl gate to turn the switch on, causing the SWOUT pin to supply
12-V power from the SWINl pin to the Vpp pin of the flash memory. On the SW2 side, the switch-off circuit
discharges the SW2 gate voltage to the GND to turn the switch off.
Reading data from flash memory assume the conditions ENl = "L" and END = "H." When the conditions are
established, the switch-on circuit (charge pump) on the SW2 side and the switch-off circuit on the SW1 side are
activated to cause the SWOUT pin to supply 3.3/S.0-V power from the SWIN2 pin to the Vpp pin of the flash
memory.
Since the switch-on circuits are powered from the SWINl and SWIN2 pins, 80 to 3S0 J,LA current flows from the
SWINl and SWIN2 pins to the GND when the switch is turned on.
The back gate of the N-channel MaS is connected to the GND. This prevents reverse current from flowing at
switch-off time, regardless of the high potential of SWINl or SWIN2 pin and the SWOUT pin.
The pLY pin is an external capacitance connector to delay turning the switch on. Controlling the switch ON time
minimizes surge current flowing to the capacitor connected to the load when the switch is turned on.

8-20

MB3807A

• ABSOLUTE MAXIMUM RATINGS
I

I Symbol II

Parameter

Input voltage

i

VSWINl
Switching voltage

I VSWIN2
ISWINl

Switching current
Permissible loss

Po
Tstg

I

Max.

I

18

Unit

I

-

-0.3

18

i

V

-

1.5

I

A

0.3

I

A

290

!

mW

+125

i

°C

7

-0.3

Ta s + 75°C

I

i

-0.3

Switch-on peak

!

Min.

I

IswIN2

Storage temperature

I

i

V,N

I
i

Ratings

Conditions

-

i

i

I

-55

I

I
I

V
V

Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability .

• RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol

I

Supply voltage

Vee

High-level input voltage

V,H

!

low-level input voltage

V,L

I

VSWINl

I

-

I

VSWIN2
ISWINl

Switching current

IswIN2

DlYpin capacitance for connection ! COLY
DlY pin leakage current i IDLY

I

i

Top

I

Min.

2.7

5.5
Vee

0

-

0

15.0

0

-

I

-

-

I

-

-

I

-0.1

-

!

!

i

-40

i

I

Unit
I

V
i

6.0

I

V
V

6.0

100
-----

10

III

V

!

V
rnA

I

mA

500

I
-----r-I

V
V

Vee x 0.2
15.0

I

I Switch ON state
I Switch ON state

i

Vee

Vee

! Switch OFF state

1

Min.

Vee x 0.8

, Switch OFF state

Switching voltage

Operating temperature

[

Values

Conditions

I

nF
~

0.1

------~----

I
!

+75

t

!

°C

8-21

MB3807A

• ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Values

i

Symbol i

Parameter

Conditions

Typical·'

Min.

,

Unit

Max.

Switch resistance
I. RONl ,. VSWINl = 12 V, ISWINl = 500 mA
300
450
mQ
(SW1)
Vce= 3 V, 5 V, Ta = +25°C
I - - - - - - - - - + - - - - - . - - - - - - - - - - - - + - - - - - I r - - - - - - ------ - - - - - - 1 - - - - - - 1
Switch resistance
VSWIN2 = 3 to 5 V ISWIN2 = 100 mA
10
6
RON2
(SW2)
i Vee= 3 V2, 5 V, Ta = +25°C
I

Switch resistance

i

RONTl ! VSWINl = 12 V, ISWINl = 500 mA
Vec= 3 V, 5 V
RONT2

High-level input current : hH
Low-level input current

ilL

610

I VSWIN2= 3 to 5 V, ISWIN2= 100 mA

14

I Vcc=3V,5V

I Vee= 5.5 V, VIH= 5.5 V
i Vce= 5.5 V, VIL= a V
i ENO = 0 V, EN1 = a V

a
a

10

o

10

a

10

175

350

700

30

80

200

24

35

100

300

-10

: or ENO = 3 V, EN1 = 3 V
i VSWINl = 15 V, Vcc= 3V

Switch-off leakage
current

1L2

mQ

~

I

i ENO = 0 V. EN1 = 0 V
i or END =3 V. EN1 = 3 V

~

, VSWIN2= 6 V, Vcc= 3 V
ISWONl
Charge pump driving
currenf2
I

IswON2 I ENO = 5 V, EN1 = a V
! Vcc= 5 V, VSWIN2= 5 V

DLY output v()ltage

VOLY

i

Supply current

Icc

i ENO = 5 V, EN1 = 0 V
i or ENO = 5 V, EN1 = a V
: Vcc= 5 V

*1:
*2:

8-22

ENO = a V, EN1 = 5 V
! Vce = 5 V, VSWINl = 12 V

Vcc=5V,VSWIN2=12V

I
!

50

!

I

Typical values assume Vce = TYP, Ta = +25°C.
The charge pump driving current flows from SWIN to GND when the switch is turned on.

I
V

MB3807A

2. AC Characteristics
Parameter

I

I

I Symbol I

Conditions

I

Values
Min.

I

= 12 V, R =24 0 , Vee = 5 V I 30
.!
VSWINl = 12 V, R =24 0, Vee = 3 V I 30
VSWIN2 = 5 V, R =50 0, Vee =5 V
40
VSWIN2 = 3 V, R = 30 0 , Vee =3 V
200
VSWINt = 12 V, R =24 0, Vee =5 V
10
VSWINt = 12 V R =24 0, Vee =3 V
10
VSWIN2 =5 V, R =500, Vee =5 V
1
VSWIN2 =3 V, R =30 0 , Vee:: 3 V
1
29

tONt

VSWINt

tON2
ON time

tON3
tON4
tOFFt

OFF time

tOFF2
!

I

tOFF3
tOFF4
tHYSt

ON/OFFtime
difference

tHYS2

I

ii

tHYS3

j

I

tHYS4

I

Note: ON/OFF time difference: tHYSt =tONt tHYS2 = tON2 tHYS3 = tON3 tHYS4 = tON4 -

-

Typical

i

I

Unit

I

J.1S

Max.

60

140

60

140

90

200

400

1200

30

60

IlS

40

70

J.1S

7

20

J.1S

7

20

J.1S

J.1S
J.1S
1

J.1S

53

130

J.1S

29

53

130

J.1S

30

60

190

190

360

12000

I

I

IlS

J.1S

tOFF3
tOFF4
tOFFt
tOFF2

8-23

MB3807A

• AC SPECIFICATION TEST DIAGRAM
• Measurement Conditions

o

DLY
(OPEN)

Vee

SWIN1
ENO
SWIN2
SWOUT

GND

A: Load resistance

• TIMING DIAGRAM
• ON-time and OFF-time Waveforms

~
..••..•:••.•..•..•...............•....•......•••...•....•..............

:~~-~~.~

Vee

EN1
: 10%

;~~-----------------OV

. .

~:;,..,..,....,..,.....--.......,~~~~ ~·t·

w

..............

Vee

ENO
10%

' - - - - - - - OV

SWOUT(SW1)

SWOUT{SW2)

ov
Note: The ENO/EN1 rise and fall times (10 %, 90 %) are each 1 ms or less.
____________________________________________________________

8-24~

~

(Continued)

MB3807A

(Continued)

:~9~0~o/c~o-------------------------------

Vee

EN1
~-----'

.............................................................................. ov
.

tr

.

:+--+:
:

------~----------------+---~90~% ~

:r-:9~0-=-%~-- Vee

ENO

OV

SWOUT(SW1)

___-----, ......................................................................... =: VSWIN2

III

SWOUT(SW2)
---------------- 0 V

Note:

The ENO/ENl rise and fall times

(10 %.90 %) are each 1 ms or less

8-25

MB3807A

• APPLICATION

r

3.3V
5.0V

~

H

~

..,

--"

-

v

MB3802

I

PCMCIA
card slotA
~

A:VPpJ

12.0V

E

Icontroller
PCMCIA I

~

~

MB3807A
PCMCIA
card slot B

t'-.. ~

v

'-MB3802

8-26

MB3807A

• TYPICAL CHARACTERISTIC CURVES
ON resistance (SW1)

ON resistance (SW2)
10

400

a

.5.

Vee: 3.0 V
Vee= 5.0 V Isw= 500 rnA

~

Vee = 5.0 V

-------------------~-----------.-----

9

u
c:

~

Vec= 3.0 V

;

Isw: 100 rnA

--- ---. -- j' ------ .. -~- -- ------t-- -------1- --- -- --- -:-- ---- ---

350

I\)

'iii

,

8

.
.,

.,,,
,

---- -- ----- - ~- ------ ---- ---- --- - -~- ---- ------------ ---

,
,

300

- ........ --- .. ~ - .............. - .:., - ................ ~, .................. ~-, ................. :., ................ ..

250

.... __ .... ___ ~_ . ___ ._ . _.... __ .... ___ . t._ .......... _..... _..... _____ ~ ........ ___ A.

7

z

0
.c
1:l

'j

en

6

200

4

10

9

11

12

14

13

15

3

Switching voitage (SWIN2) (V)

ON resistance (temperature dependence characteristic: SWIN1)
450
Vee = 3.0 V -Vee = 5.0 V 400

:

!

~~~~~ _
~ ~ ~ ~ ~ ~ ~ ~I~ ~ ~ ~ ~ ~~~~ ~ ~ ~ ~! ~ ~ ~ ~ ~: ~ _~_~~:~I!_____
_~~_ ~ _ _ ___

350

Ta = +75°cj___

'

,

6

4

Switching voitage (SWIN1) (V)

ON resistance (temperature dependence characteristic: SWIN2)
7.5,
,
;

g

3.0 V

--VSWINZ;- 12 V
Vee =

7.0

----.---------L-------------~------- Vee = 5.0 V

6.5

---------------~--------------:-------------.~---------------

!!
,

:

:

III

_

,

-_._----.------., ---_ ................., -----_ .... -.---_ ...., _---_.--------

300

.;------~

250

·--ta;.-:.:250~~---------!--------------i---------------

200

---------------'.--------------.-------------

__ J?,::=:W~~I-~---------!--------------~---------------

5.0

,

,

Ta=-40°d,/
150

4.0
110

200

400

300

500

40

20

Isw(rnA)

;

,....
~

Vee =

io V - - •

---------------;---------------i-------Vee= 5.0 V ,

,

.g
~

.c
£

.~

en

Vee =
V---------,----------:----------;---------,----.-----:----------

30

----- --. -~--- -------. ----- ----: --- -- -- --~--- -------~ ---------

10.5

~

~
(5

28

S
a.
S

26

c:::

24

Q)

>

9.5

z

0

5.0

32

10.0

III

'iii

34

--

I\)

u
c:

100

80

Charge pump output voltage

ON resistance (temperature dependence characteristic: SWIN2 )
11.5
11.0

60
Isw(rnA)

o

9.0

a.

>....J
o

8.5
8.0

7.5

: - •... -_ . •. • _.: . 1···-·-··1
18

20

40

60

Isw(rnA)

80

100

9

10

12
11
13
14
Switching voltage (SWIN1)(V)

15

8-27
(Continued)

MB3807A

(Continued)
Charge pump driving current

Charge pump driving current
150

600

Vee =3.0 V -.:.
Vee = 5.0 V Isw= 100m A

<
a
c:
~

500
.
----Ta-~-~ooC'~

U

OJ

t:
.s;
~

Ta=-25°C

: -----

0.

E

-".--' .. - - :

~ __ ~ Ta=+25°C

---.~--------:------- .. --~-;-----------.-----.--

50

Q)

~

--;::,.~--:-----

.. --:;:;~.f.;;-?~~'---

400

::J
0.

ca

.

.. -- .. -.. --------: .... ~~~;;:_. -_

100

::J

:

ia = +75°C

4

5

300

.c:

U

o

200
9

10

11

12

13

14

15

3

Switching voltage (SWIN1) (V)

Switch OFF time (SW1)

Switch ON time (SW1)
80

SWIN1 =12V
: Isw= 0.5 A

'iii'
Q)

60

50
40

40

_ .. -

60

0

--------------------~-------------------~------.-------------

50

- -- - _ ............ - - - - -- _ .. -!",. -_ .. -- - _ .... -- _ ...... - - - ~- -- -- --- -- -_ ...... - -_ ..

70

~

u.
u.

z

o

.,

.,,

80

a

a

:
: SWIN1 .. 12 V
---- -,- -------- -- -.':- ---- ---- --- --------;--lsw;'; U~5- P\' ----

90

--------------------~-------------------~--------------------

'in

~

100

i

70

6

Switching voltage (SWIN2) (V)

-_ .. ---- -- --- -- - -.:.. -- ... _ ..... .. -- .. _ ... _. ~- -. --.. -_ .. _ .... --- -- --,

,

.

.

.. _ - - _ .. - - - - - - - - - - - - - - , - - - - - - - - _ . - • • _ .. _ - - - - , - - - - - _ . _ .. _ - - _ _ _ _ a _ A .

,

30

--------------------'--------_.-.

20

--_ .. -- ---- ----------:-- .. - - -- - _.- .. ---- ... -- .. -- -- --- - .. ------ -_..
-~

_

10

3

4

5

6

4

3

Supply voltage (Vcc) (V)

5

6

Supply voltage (Vcc) (V)

Switch ON time (SW2)

Switch OFF time (SW2)

600

20
:

Isw= 100 rnA

Isw= 100m A

.
--.-----------------,... _-----------------,.-------.. ---------

500

15

--------------------~---------.---------;-

.. ----.-----------.

Ii)

a
~
z
o

SWIN2 = 3.0 V
.. - . - . - . ----- . - . -- -.:.. . - -- _.. - -_. - ----- . -- ~ --- -- -. ---- . - . - . -. - -

300

Q)

~

10

u.
u.

0

. - . --- A:. -- -.. ---.. -. ---.... ~ -. ----- --. -

200

SWIN2 =5.0 V

'

......

_-

...

'"

-.. -------------- ....-:-"::-... --~..:;,_------"--- ... --- ..

5

---'--

100

'-- ---

SWIN2

o
3

8-28

= 5.0 V

o
4

5

Supply voltage (Vcc) (V)

6

3

4

5

6

Supply voltage (Vcc) (V)

~----------------------------------------~--------------------------------~

MB3807A

• ORDERING INFORMATION
Part number
M83807APF

Package

Remarks

16 pin Plastic SOP
(FPT-16P-M04)

II

8-29

MB3807A

• PACKAGE DIMENSION
16 pin Plastic SOP
(FPT-16P-M04)

~= = = INDE= X~~Fl
Lb:;=O;:+:;:=/=:;::;:=;::::;:==:;::;:::::::;=:;::::;::;;:::::::;::;

l,l.271.050)TVP

.'ijOO~

.' ',O.45iO.10 1$100 13( 005)
(.018±.004)· . . .'

~
I

.:

YOI0.10(.004)1

g
,

5.40:g~

,6;r

(.213::::)

~I

"0.15:g::

(.006::')

0.50±0.20
(.020±.008)

---------------I

: Details of "A" part

J

........ .

I

I

---------------

@

8-30

1994 FUJITSU UMITED Fl60125-4C-4

Dimensions in mm (inches)

SECTION 9
Application Notes and Articles - At a Glance

Application Notes
Page Number
9-3

Title
Fujitsu Prescalers and Phase-Locked Loops for VHF and UHF Frequency
Synthesis

Technical Articles
Page Number

Title

9-35

Resonator-Type Low-Loss Filters

9-43

Land S Band Low-Loss Filters using SAW Resonators

II

9-1

9-2

OJ

March 1991
Edition 2.0

APPLICATION NOTE

FUJITSU

Prescalers and PLLs

I

Fujitsu Prescalers and Phase-Locked Loops
for VHF and UHF Frequency Synthesis
A Tutorial with Selection Guides

Fujitsu Microelectronics, Inc.
Field Applications Engineering
Copyright© 1991 by Fujitsu Microelectronics, Inc.

Abstract
This Application Note includes a broad introduction to the relevant high frequency synthesis theory and its
application areas, a description of prescaler and phase-locked loop (PLL) components, and guidelines for
selecting and designing with Fujitsu's extensive selection of prescaler and PLL Ie products.

D

9-3

Copyrighl© 1991 Fujitsu Microelectronics, Inc., San Jose, California

All Rights Reserved.
Circuit diagrams using Fujitsu products are included to illustrate typical semiconductor applications. Information sufficient for
construction purposes may not be shown.
The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu
Microelectronics, Inc. assumes no responsibility for inaccuracies.
The information conveyed in this document does not convey any license under the copyrights, patent rights or trademarks
claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu Microelectronics, Inc.
Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice.
No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior
written consent of Fujitsu Microelectronics, Inc.
This document is published by the Publications Department, Fujitsu Microelectronics, Inc.,
3545 North First Street, San Jose. California. U.S.A. 95134-1804; U.S.A.
Printedjo the U.S.A.
Edition 1.1

9-4

Contents

Introduction ........................................................................... .
PLL Tuning Systems .................................................................... .
What is a PLL? .......................................................................... 3
Frequency Synthesis With PLLs and Prescalcrs .............................................. 4
The Pulse Swallow Method ............................................................... 6
A description of the pulse swallow method is as follows: .............................. 6
Stand-alone PLLs and Integrated PLLs ..................................................... 7
Selecting the Right PLL IC ................................................................ 9
Selecting A PLL ........................................................................ 10
Width of the counters ............................................................ 10
Selecting the N and A counters ......................................... . . . . . . . . . .. 10
PLL Counter Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11
A Practical Example: Selecting the PLL IC for an FM Receiver ................................ 11
Example ........................................................................ 11
Programming of the counters ..................................................... 12
Set-up and switching times of the counters and modulus control logic ....... . . . . . . . . . .. 12
Positive or negative edge triggering of counters ..................................... 12
Phase detector .................................................................. 13
Charge pump ............... , ... " ............ " ................................ 14
Charge pump waveforms and fr and fv ....................................... " .... 15
4-bit Microcontrollers with PLLs .................................................... " .... 15
What is a Prescaler? ............................................ . . . . . . . . . . . . . . . . . . . . . . . .. 16
Dual modulus prescalers ......................................................... 17
Single modulus prescalers ........................................................ 17
Microwave Prescalers ............................................................ 18
Stand-alone Prescaler Application ......................................................... 18
Selecting the Right Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 19
Toggling speed .................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 19
Termination resistor internal/external .............................................. 20
Stability of Vout ................................................................. 21
Flexibility of the input voltage ..................................................... 21
EeL level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 21
Flexibili ty of Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 21

9·5

Contents (Continued)

Modulus set-up time ............................................................ 21
Input impedance and reactance .............................................. . . . .. 21
Smith chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 21
Packaging .................................................................... "

22

Signal propagation delay through the prescaler ..................................... 24
Balanced inputs ...................................................... , .......... 24
Output duty cycles .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 24
Power dissipation ............................................................... 24
Conclusion ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25
References ............................................................................ 27
Books ......................................................'................... 27
Articles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 27

9-6

Illustrations

Figures

Page

1.

A Typical Heterodyne FM Receiver Tuned to the 88.1 MHz Signal . . . . . . . . . . . . . . . . . . . . . .. 2

2.

A Typical Heterodyne (Audio) Sender. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3

3.

A Basic PLL Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3

4.

Frequency SynthesiS with a Programmable Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5

5.

Prcscalcr Accommodating for a Slow Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5

6.

Pulse Swallow ................................................................... 6

7.

System Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7

8.

Fujitsu's Integrated PLL ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7

9.

Varactor Diode in a VCO or a VCXO ................................................ 8

10.

A Varactor Diode Acting as a Voltage-controlled Variable Capacitance ................... 9

11.

PLL Program Counter Triggered by OppoSite Edge .................................. 13

12.

PLL Program Counter Triggered by Same Edge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13

13.

Active Low Pass Filter ............................................................ 14

14.

External Charge Pump Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15

15.

Frequency Division .............................................................. 16

16.

Selection Guide to the Fujitsu Bipolar Prcscaler Family ............................... 18

17.

A Stand-alone Application of a Prescaler: Clock Rate Reduction ....................... 18

18.

Input Signal Amplitude Versus Input Frequency for MB509 Dual Modulus Prescaler ..... 20

19.

Smith Chart Constant Resistance .................................................. 22

20.

Smith Chart Constant Reactance ................................................... 22

21.

Input Impedance of Fujitsu's MB501 L Dual Modulus Prescalcr as a Function of
Frequency Shown on a Smith Chart ................................................ 23

Tables

Page

1.

Fujitsu's Low Power CMOS PLLs ................................................... 9

2.

Fujitsu's Super PLLs ............................................................. 10

3.

Fujitsu Prescalers ................................................................ 25

9-7

Introduction
Phase-locked loops (PLLs) and prescalers are used for synthesizing and controlling frequencies in a multitude of high frequency systems. These systems range from radio and television broadcasting, cellular
phones, computer local area networks (LANs), and measurement instrumentation to satellite and microwave systems.
Dedicated PLL integrated circuits (ICs) are manufactured in CMOS technology and typically operate in
the 20-30 MHz range (maximum). Prescalers manufactured in bipolar ECL or GaAs technologies are considered interface les that allow the relatively slower PLLs to accurately control and select frequencies well
into the microwave range (> 1 GHz).
Fujitsu manufactures a broad range of high frequency telecommunication ICs that includes prescalers,
PLLs, integrated PLLs, as well as microcontrollers with onboard PLL and prescaler circuits.

PLL Tuning Systems
Tuning of telecommunication senders and receivers is, by far, the largest application area for today's PLLs
and prescalers. High frequency PLLs have largely replaced older methods such as direct tuning an RC or
LC oscillator to the desired local oscillator frequency.
At the expense of a quantized (instead of a continuous frequency) resolution, PLLs and the so-called digital tuning circuits into which they are incorporated provide a cheaper, faster, more compact and reliable
solution to tuning circuitry. The fact that PLLs only allow selection of frequencies in discrete steps, rather
than over a continuous range, is not a concern because the available frequencies (for airwaves, long distance telephone cables, satellites, microwave links, ISDN etc.) are heavily regulated and limited to preassigned channel frequencies.
The frequency position and spacing between channels depends on the physical carrier medium and the
program material involved. For example, U.S. airwaves regulations of the Federal Communications Commission (FCC) specify that:

9-8

March 1991
Fujitsu Microelectronics, Inc.

Prescalers and PLLs
Tutorial and Selection Guide

AM radio must be broadcast at 530, 540, 550 to 1610, or 1620 kHz
FM radio must be broadcast at 87.9, 88.1 to 107.7, 107.9 MHz
TV (channels 2~9) must be broadcast at 55.25, 61.25, 67.25, 77.25, 83.25 to 795.25, 801.25 MHz.
These frequencies represent the center frequencies of each channel. The spacing of 10KHz between assigned AM channels, 200 kHz between assigned FM channels, and 6 MHz between assigned TV channels
reflects the progressively higher bandwidths necessary for FM and lV.
Other regulated frequencies worth mentioning within the VHF (30 - 300 MHz) and UHF (300 MHz - 3
GHz) bands include: 46/49 MHz for cordless telephones, 800-900 MHz for cellular phones (also known as
land mobile radio services), 0.1-1.5 GHz for cable lV and >2 GHz for emerging DigitallV standards and
Integrated Services Digital Network (ISDN). Fujitsu prescalers and PLL les are appropriate for most of
these applications.
Figure 1 shows a superheterodyne FM broadcast receiver and some of the involved spectra and frequencies. For an example, let us examine the steps involved in tuning to the FM station at 88.1 MHz.

MM ~ ... ,J,.,
87.9

88.1

88.3

107.7

/

AL~D
107.9 MHz

AlA ,J.., •..~ rt!'r
10.5

10.7

10.9

"MHz

,/

"

floc
Local Oscillator

•.

98.8 MHz

fe= 10.7 MHz
~

~

150 kHz

Figure 1. A Typical Heterodyne FM Receiver Tuned to the 88.1 MHz Signal

The antenna is exposed to a multitude of transmission frequencies. In order to retrieve the desired signal,
s~veral stages of amplification and progressive selective filtration must be applied. In FM broadcasting
each radio station is allowed to use up to 150 kHz around the assigned center frequency. Since the spacing

9-9

Prescalers and PLLs
Tutorial and Selection Guide

March 1991
Fujitsu Microelectronics, Inc.

between the assigned channels is 200 kHz, this leaves a 50-kHz wide isolation gap betweei't the stations to
avoid a spectral overlap. Thus, a lSO-kHz wide filter can be used in the final stage to isolate the desired
station from all the others. Accurate tuning of such a narrow filter over the 20-MHz wide FM frequency
range is not an easy task. To achieve accurate tuning, the filter is kept at a constant frequency, the so-called
Intennediate Frequency (IF), and the desired radio signal is shifted in frequency to fall exactly within the
filter passband. 10.7 MHz is the broadly used value for IF in commercial FM tuners.
The antenna signal is converted to a lower frequency by mixing (or heterodyning) with an appropriately
chosen local oscillator frequency floc. A PLL is employed for synthesizing floc. In order to place the desired radio station (originally located at fin) exactly at the center of the IF bandpass filter, the PLL frequency f,oc must be set so that IF = f,oc - fjn. In other words, to tune to the 88.1 MHz signal, a floc of 88.1+ 10.7
MHz =98.8 MHz is necessary. Tuning to another signal is accomplished by selecting a different floc.
An appropriate FM demodulator working at the IF provides the final restoration of the original signal.

On the sender side (see Figure 2) the sequence is reversed: a modulated IF signal is mixed with the local
frequency oscillator up to the appropriate channel-frequency and broadcast.

Modulator
(FM, AM, TV etc.)

Local Oscillator

Figure 2. A Typical Heterodyne (AudiO) Sender

Near-ideal PSK, PM, or FM demodulators can be implemented with PLLs as well as local oscillators.

What is a PLL?
A PLL is a control loop consisting of a phase detector (PO), low pass filter (LPF), voltage controlled oscillator (VeO), program counter(s), and, as necessary, single- or dual-modulus prescalers. (Sec Figure 3.)

Figure 3. A Basic PLL Configuration

The output of the PO is a voltage indicating the phase difference between its two inputs.

9·10

Pre scalers and PLLs
Tutorial and Selection Guide

March 1991
Fujitsu Microelectronics. Inc.

The LPF smooths the PO output and determines the dynamic performance of the loop. The dynamic performance includes general servo loop issues, such as the capture and lock ranges, the noise suppression
bandwidth and the transient response.
When the loop is out of lock, the PO voltage changes the frequency of the veo in a direction that reduces
the phase difference between the input signal and the local oscillator signal. When the loop is locked, the
signals at both inputs are in phase and have the same frequency.
Generally speaking, the output of the veo is considered the desired PLL output. It should be mentioned,
however, that in some instances  fo = N • fret

A reprogramming of liN" by +1 or -1 will result in selection of a new output frequency with channel separation of fret.
The scheme of Figure 4, although attractive in its simplicity, is only applicable to output frequencies below
40 MHz, since higher VCO frequencies will exceed the program counter's toggling rate.
Figure 5 shows a widely used remedy to the high frequency problem: a 11M prescaler is inserted in the
feedback loop as a buffer between the VCO and the program counter. This lowers the program counter's
input frequency to foutlM instead of fout.

f=iretlR

ire!

Prescaler

+M

f out = tL.!.M.x f ref
R

Figure 5. Prescaler Accommodating for a Slow Program Counter
Figure 5 also shows a reference frequency divider, l/R, inserted in the reference frequency path to allow
more flexibility in output frequency programming. Without the reference frequency divider, the presence
of the prescaler would result in broadening the channel separation to M • fret- A resolution of fref is maintained by setting R equal to M.
In many cases, the scheme of Figure 5 is a satisfactory solution, with one drawback. Compared to Figure 4,
the operational frequency of the phase detector is lowered by the prescaling factor M. A lowered PO frequency necessitates use of a narrower low-pass filter to suppress spurious output signals from the phase
detector at the comparison frequency and its harmonics. Especially in very high frequency synthesizers,
where the divide ratio of the prescaler becomes substantial, the loop's lock-in and switching speed characteristics will be severely degraded as a result of narrowing the lowpass filter.

9-12

March 1991
Fujitsu Microelectronics. Inc.

Prescalers and PLLs
Tutorial and Selection Guide

The Pulse Swallow Method
The widely used "multi-modulus division", also known as pulse swallowing (see Figure 6), offers a solution to previously mentioned problems. This method employs two programmable counters and a dual
modulus prescaler inside the loop. (For simplicity the reference frequency divider is not shown.)

fret

PD

Program
counter
1/N

Dual Modulus
Prescaler
11M & 1/(M+1)

f olA =(N x M + A) X fta(

Modulus
Control Logic

FIgure 6. Pulse Swallow
A description of the pulse swallow method is as follows:
N must be larger than A (N)A). The dual modulus prescaler is initially set to divide by M+l. After "A"
pulses out of the prescaler, the swallow counter is full and changes the prescaler modulus to M. After additional (N-A) pulses out of the prescaler, the program counter changes the prescaler modulus back to
M;.l, restarts the swallow counter and the cycle repeats.
In this way each cycle of the liN counter is a result of:
A • (M+1) + (N-A) • M

=N • M+A

cycles of the f pit·
In other words:
f ",,/

= (N.

M + A) • fret

Since M is multiplied by N, but not A, the frequency will change by fret when A is changed by 1. In this
way both the channel separation and the PD frequencies are maintained at fre! to provide for an uncompromised loop performance.

9-13

Prescalers and PLLs
Tutorial and Selection Guide

March 1991
Fujitsu Microelectronics, Inc.

As previously mentioned, more complex variations of the multi-modulus theme include: NfN+Z prescalers (as in MBS08 with 128/130,256/258 and 512/514) and quad-modulus schemes involving multiple·
swallow counters and special prescalers.

Stand-alone PLLs and Integrated PLLs
Figure 7 shows a general purpose high frequency synthesizer and the functional blocks. These blocks are:
the PO, the reference counter, the A and the N counters and modulus control logic. The MB87014, manufactured entirely in CMOS, includes an onboard 180 MHz prescaler.

Ir.
foul

Dual Modulus
Prescaler

l/M& lI(M+l)

Figure 7. System Blocks

Advances in recent years in CMOS and BiCMOS (combined ECL and CMOS on one chip) have allowed
integration of gigahertz prescalers on the same chip as the PLL. The architecture of these integrated PLL
BiCMOS devices is illustrated in Figure 8.

foul

Dual Modulus

Bipolar

Prescaler

prescaler
integrated
on chip

l/M& 1/(M+l)

,-.--~---------------------------------.

Figure 8. Fujitsu's Integrated PLL ICs

9-14

March 1991
Fujitsu Microelectronics. Inc.

Prescalers and PLLs
Tutorial and Selection Guide

Before discussing the blocks on the PLL chip, let us briefly mention the circuits not found on it. As stated
earlier, the low~pass filter must yield a good compromise between accommodating the desired noise and
switching characteristics on one side and removing spurious components from the phase detector output
on the other side. A charge pump output (see Figure 14) from the PLL is provided in most cases, allowing
direct connection of an external passive RC
filter. The charge pump output is simply a very high impedance output (Zout ~ 400k Q) well suited to
drive high-Q resonant circuits found in the VCO. Optionally, an unbuffered PO output is often also made
available for connection of custom external active filter configurations. Typical filter bandwidths for frequency syntheSis are 1-10 kHz.
The prescaler and the VCO are the only two devices actually operating at the high output frequency

foul.

The VCO is frequently custom made for a specific application. Some popular oscillator types, in order of
decreasing phase and frequency-stability, but increasing frequency coverage and linearity, are as follows:
• PLL IC with an on-chip inverter Ibuffer for an external reference frequency oscillator
• Voltage controlled crystal oscillator with varactor diode (also known as VCXO)
• LC oscillator with a varactor diode
• RC muItivibrator
A list of crystal oscillator and VCXO manufacturers can be found in reference 11.

Charge
Pump

III

VCOorVCXO

LPF

+

Vdc

,
Co

High impedance
current source

f

=

~/L[CO+C(Vdc))

LC luning circuit or Crystal

Figure 9. Varactor Diode In a veo or a vexo

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Prescalers and PLLs
Tutorial and Selection Guide

March 1991
FUjitsu Microelectronics, Inc.

Capacitance

Varactor Diode
Characteristics

(DC) Voltage

Figure 10. A Varactor Diode Acting as a Voltage-controlled Variable Capacitance

Selecting the Right PLL

Ie

Table 1 lists Fujitsu's family of CMOS PLL ICs and Table 2 lists the BiCMOS integrated PLL ICs.

Table 1. Fujitsu's Low Power CMOS PLLs

Please refer to the CMOS PLL's section.

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Presca/ers and PLLs
Tutorial and Selection Guide

Table 2. Fujitsu's Super PLLs

Please refer to the Super PLL's section.

Selecting A PLL

The specifications to consider when selecting a PLL are as follows:

Width of the counters
The most significant feature of the various PLL devices (since operating speed is practically the same for
all), is the width of their counters. In general, the width (in bits) of the reference counter detennines the
frequency resolution (llfchannel =freflR) obtainable from the system. The width of the programmable
counter, (lIN> (see Figure 7) and the swallow counter (1/A) detennine the number of channels that can be
covered. Fujitsu devices are available with up to IS-bit wide combined program and swallow counters,
and I6-bit wide reference counters.

Selecting the N and A counters
It is easily observed from the dual-modulus equation [fOUl =(N • M+A) • llfchannel] that A need not assume values higher than the prescaler modulus M, since setting A equal to M+X is equivalent to setting A
equal to X and increasing N by 1. Hence, all possible channels can be covered in a dual modulus configuration if the programmable swallow counter number (A) is allowed to assume all values from 0 to M-l,
where M is the modulus of the M/M+ 1 prcscaler:

• O~A~M-1

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Fujitsu Microelectronics, Inc.

Under all circumstances the condition N~A must be satisfied:
• Nmin = Amar

=M-l.

To select the right PLL counters for your application, supply the information that is requested in the following guide.

PLL Counter Selection Guide
1.

Identify maximum and minimum output frequency desired, fout, mllX and fout, min.

2.

Select a M/M+l prescaler, so thatfout,max/M can be accommodated by the PLL «20 MHz typically).

3.

Identify desired channel spacing(s), 6.fchannel.

4.

Let A = 0, then Nmin = fout, min/6.fchilnn£1 and Nmax = fout,max/6.fc}umnel.

5.

Verify that Nmin~M-l; if not, select a bigger prescaling modulus and go back to

6.

Select an N program counter with enough bit-width to accommodate the value of Nmax •

7.

~<;!p

3.

Select an A swallow counter with enough bit-width to accommodate the value M-l; set all higher
bits to O.

8.

Select the reference frequency divider (R) and a crystal reference frequency so that freflR = d!channel.

A Practical Example: Selecting the PLL Ie for an FM Receiver
We are going to select the appropriate PLL IC and prescaler for the local oscillator of the superheterodyne
FM receiver shown earlier in Figure 1. In order to receive an FM station at fin, the local oscillator must be

set to f,oc = fin + 10.7 MHz. For receiving all FM stations, floc has to be selectable between 98.6 MHz and
118.6 MHz in 0.2 MHz steps; that is 101 positions in total.
To select a PLL for our example FM Receiver, we used the PLL Selection Guide, supplied the required information (see Example), and selected the appropriate PLL.

Example

=118.6 MHz

=98.6 MHz

1.

fout, max

2.

Choose the MB503 prescaler (M=16)

fout

fout, max/M =7.4 MHz < 20 MHz

3.
4.

6.fchannel = 0.2 MHz
Nmin = fout,min/6.fchilnnel = 493
Nmax

9-18

=fout,max/6.fchannel = 593

5.

Nmax > 16, OK

6.

Nmax of 593 requires a 10-bit wide N-countcr

March 1991
Fujitsu Microelectronics, Inc.

Prescalers and PLLs
Tutorial and Selection Guide

7.

Amax of 15 requires the following:
•

A 4-bil wide (swallow) counler

• Eilher an MB8700 1A or an MB87006A
•

8.

ChooseMB87001A

Choose an fre/of 3.2 MHz and set the R-counter to 16 to yield flfchanneI

=0.2 MHz

Programming of the counters
In order to preserve board spacc, all Fujitsu PLLs have scrially programmable counters. The divisor values are fed through a serial pin to a shift register and latched-in with a control pulse. This allows 16-pin
packaging to be used for all devices.

Set-up and switching times of the counters and modulus control logic
These delays are important and can become a limiting factor, especially when operating in pulse swallow
mode. When the circuit has counted down so that the N program counter is full, the whole counter system
is reset. The reset function must be completed within the next cycle of the M/M+1 prescaler or,

treset < M/!out,max
Where treset equals the sum of propagation delays through the A and N counters, frxo, low when fret < foco and high-impedance state when
fret =jrx:o. This output can be connected directly to an active or passive external filter. The MB87014 provides an inverted charge pump output as well.

The charge pump output is derived from two flip-flops out of the phase detector, 4>r and 4>v. In the case of
MB87006A, MB87014 and the MB870861 when the loop is unlocked, the appropriate output terminal, 4>r or
4>v, pulls low to indicate which of the two inputs fret or fvco is at a higher frequency.
The signals 4>r and 4>v would normally be considered an intermediate result; however, they are also made
accessible on two output terminals allowing construction of an external charge pump.
A charge pump combines the two digital outputs (4)r and 4>v) into one output. (See Figure 13.) The external
configuration shown here also directly implements the lowpass filter. Note that due to different polarity
assignments, this configuration is not appropriate for MB87001A, 87073,87076, and the integrated PLLs.
Also n()te that often a large resistor is inserted following the op-amp output to increase the output impedance.

PO
loVCO

Figure 13. Active Low Pass Filter
A fast external charge pump implementation appropriate for the MB87001A, 87073,87076 PLLs, les, and
an integrated PLL is shown in Figure 14. The 4>r and 4>v outputs on these devices are of the open-drain
type. (The rest of the PLL family provides push-pull outputs for 4>r and 4>v.)
1Note thai the remaining Fujitsu PLL ICs (MB8700IA, 87073, and 87076), as well as the single-chip PLL/prescalerfami-

Jy (MB 15(0), have a different phase detector design and a different truth table for 4>r and 4>v:
4>r
4>v
fr> fv
Low
Low
fr = fv
Low
High-Impedance
fr < fv
High
High-Impedance
The cp-outputs of these devices are open drain.
An external charge pump allows use of faster transistors or op-amps (higher slew rates) and may offer
improvement in lock-in performance.

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Prescalers and PLLs
Tutorial and Selection Guide

Vp (5-BV)

"'--J'V'v\..r---'~ To lPF

Ground

Figure 14. External Charge Pump Example

Charge pump waveforms and ~r and ~v
As previously mentioned, in the case of MB87006A, 87014 and 87086 (see footnote 1 on the preceeding
page), when the loop is unlocked, the appropriate output terminal, cpr or cpv, pulls low to indicate which of
the two inputs fret or foco is at a higher frequency. This active terminal, ~r or ~v, will not stay at a steady
low but will occasionally toggle to a high state. Basically, its output provides a pulse-width modulated
representation of the frequency difference between the inputs.
When the loop is in lock, ~r and ~v will both be in the "high" state. However, synchronously with the
phase comparison frequency, a short spurious negative pulse will occur at both outputs.
The same pulse anomalies will also appear on the output from the internal charge pump. One of the tasks
of the loop lowpass filter is to remove all spurious signals (pulses) from the PO output. The loop filter
bandwidth must, therefore, always be below the phase comparison frequency. Conversely the phase comparison frequency should be kept as high as possible.

4-bit Microcontrollers with PLLs
Fujitsu also offers a family of 4-bit microcontrollers, the MB88560 family with an on-chip PLL.The
MB88560 family consists of two 4-bit CMOS microcomputers: the MB88561 with a liquid crystal display
(LCD) controller I driver and the MB88562 with a vacuum fluorescent display (VFD) driver. Both devices
contain 21 I/O lines, an 8-bit timer I counter, an AID converter with 6-bit resolution, display drivers, and a
PLL with prescalers suitable for all broadcast and shortwave frequencies. Each device has independent
AM (up to 32 MHz) and FM (up to 120 MHz) inputs. Up to 4 K by 8-bit ROM space and 256 K by 4-bit
static RAM space is available on-chip.
Both chips allow extremely compact designs of car radjos, personal stereos, personal communication
equipment, etc.

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Presca/ers and PLLs
Tutorial and Selection Guide

A two-part MB88560 design guide and a demo board are both available from Fujitsu.

What is a Prescaler?
A prescaler is an integrated circuit that divides the frequency of an incoming signal by an integer M (see
Figure15). The divisor, M, is called the Modulus.
Internally, a prescaler is a specialized ripple counter, which counts incoming pulses and performs one output cycle for every M received input cycle. If M is an even number the output is toggled following every
M/2 input pulse. For M odd, one of the toggles is delayed an extra input cycle (e.g., 6 input pulses for output high and 5 input pulses for output low for M =11).

In:

14

Tin

~I

••••

Out:

I~

~I

Figure15. Frequency Division

There are distinct differences between prescalers and general purpose divide-by-N counters. We will refer
to the latter as program counters and substitute the letter N when referring to them for the remainder of
this text.
Prescalers are comparatively simple devices. They contain a minimal amount of logic (less than approximately 100 gates) and offer a few, well chosen modulus numbers. This streamlined architecture allows
implementation in the fastest bipolar and GaAs technologies without excessive power consumption or
expense. For example, the MB510 dual modulus prescaler from Fujitsu offers a choice of four divide ratios

III

(128, 144,256 and 272). Manufactured in 0.8 Jlm bipolar technology, this B-pin device is ECL compatible,
accepts input frequencies up to 2.7 GHz, and dissipates only 0.05 watts of power.
Program counters, on the other hand, contain a fair amount of programming and decoding logic in order
to allow a wide selection of N (any value of N between 0 and 2q_l is made selectable using a q-bit wide
program input). The relatively high internal gate count generally limits program counters to TTL or
CMOS technology with toggling speeds of less than 40 MHz.
The important point to be made is that there is no need to make program counters faster, or prescalers
more programmable. The distinction between the two types of devices is intentional. Once the frequency
is brought down sufficiently by a prescaler, so')histicated frequency manipulation is performed with
CMOS program counters and a PLL. Prescalers are generally classified as either single or dual modulus.

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Prescalers and PLLs
Tutorial and Selection Guide

Dual modulus prescalers
Dual modulus prescalers allow a very rapid transition from a divide-by-M mode to a divide-by-M+l
mode (e.g., from 64 to 65); hence, they are often also called M/M+ 1 prescalers (64{65). [n conjunction with
PLLs and the pulse swallow method (discussed on page 14), dual modulus prescalers allow finer frequency resolution than single modulus prescalers.

Single modulus prescalers
Single modulus prescalers are fixed, or semi-fixed dividers that only divide by a fixed number M. A semifixed single modulus prescaler allows a choice of more than one modulus (e.g., 32,64 and 128), but is not
necessarily optimized for fast switching between moduluses, and the modulus choices are not spaced one
apart.
Less common varieties of prescalers include:

• M/M+Z (where Z:# 1) dual modulus prescalcrs
• Four modulus prescalers
• Decimal single modulus prescalcrs
Figure 16 shows Fujitsu's bipolar prescaler Ies.

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Fujitsu Microelectronics. Inc.

Prescalers and PLLs
Tutorial and Selection Guide

Please refer to the Quick Section Guide
In the front of this data book.

Figure 16. Selection Guide to the Fujitsu Bipolar Prescaler Family

Microwave Prescalers
Microwave prescalers manufactured in GaAs technology are available from specialized vendors, including Fujitsu. The microwave prescalers have frequencies above 3 GHz (microwave range) and toggle
speeds of up to 10 GHz. The cost of GaAs parts, however, is considered high when compared to Eel bipolar parts.

Stand-alone Prescaler Application
Prescalers can be used as stand-alone components without a PlL.
A stand-alone application does not involve feedback of signals around the prcscaler. The most common
stand-alone application for a prescaler is in digital clock distribution networks, where a prescaler simply
reduces an incoming clock rate and distributes it to slower analog or digital circuitry. (See Figure17.)

frel

foul

=frel 1M

Figure 17. A Stand-alone Application of a Prescaler: Clock Rate Reduction

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Prescalers and PLLs
Tutorial and Selection Guide

Prescalers offer several advantages as stand-alone clements. For example, consider an appiiCation that
requires a high quality I-MHz reference signal. For this application, a straightforward, high quality
I-MHz crystal oscillator might seem the most obvious choice; however, the highest quality will be
achieved with a higher frequency reference signal (10 MHz) followed by a prcscaler (1 /10). This application is preferred because of the following reasons:
• Crystal resonators with higher oscillation frequency tend to have smaller dimensions, shorter oscillation stabilization times and narrower characteristic variations.

• A prescaler will clean up the incoming high frequency signal in two ways:
- It will totally remove variations in the amplitude noise (amplitude envelope of the incoming sig-

nal), since its output amplitude is independent of the input.
- It will reduce the phase noise (jitter of zero-crossings) of the incoming signal by approximately a
factor of M since its output only switches synchronously with one out of every M/2 input pulses.
The above reasons apply up to a certain point, or as long as the prescaling factor is moderate. The frequency of the crystal should not be increased to the point where RF shielding or board layout has to be
changed. Increasingly small dimensions or the price of the crystal can also become a problem.
Numerous digitalISI ICs take advantage of the beneficial properties of prescaling; e.g., they have onboard prescalers that allow a direct connection of high frequency crystal docks to slower internal logic.
For example, Fujitsu's line of 4-bit microprocessors offers a built-in, divide-by-2 prescaler as a recommended option. This option allows the user to drive the 2-MHz internal logic with a 4-MHz crystal rather
than a 2-MHz crystal. With this option, the 4-MHz crystal clock will tum on and be fully operational (as
well as recover from any external disturbances) in half the time required for a 2-MHz crystal.

Selecting the Right Prescaler
To select the appropriate prescaler, first determine the necessary modulus choices and input toggling
speeds.

Toggling speed
One should be aware that a I-GHz (fin,max typically) prescaler does not abruptly stop functioning when
fed frequencies above 1 GHz. The I-GHz prescalcr will typically require higher input levels to trigger, and
it may deliver a smaller output swing, but typically it will function up to a 20-50 percent higher frequency. See Figure 18.
These characteristics are important, since frequency switching in a PLL is normally accompanied by a fair
amount of overshoot. A VCO intended to stabilize at 1 GHz may reach, for example, 1.4 GHz before settling down. It is important that the loop (including the prescaler) remains functional during that period.
Charts like Figure 18 can be helpful in verifying such cases.

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Prescalers and PLLs
Tutorial and Selection Guide

Vee

E
!Xl

= 5.0V

10

E

Z

TA

>
w
0

= 85°C

0

:::>

f-

::i
n.

:?;
~

...I
~

-10

Z
(!)

in
f-

:::>
n.
~

-20

:?;

:::>
~

z

~
-30
1.0

1.2

1.4

1.6

INPUT FREQUENCY fiN (GHz)

Figure 18. Input Signal Amplitude Versus Input Frequency for MBS09 Dual Modulus Prescaler

Prescalers with higher frequency ratings will typically be associated with higher power dissipation and
higher switching noise. For example, measurements of gallium arsenide dividers suggest noise performances 20 to 30 dB worse than for Eel dividers (reference 10).
Also note that the input coupling capacitance of a prescaler will limit the lowest useful frequency.

Termination resistor internal/external
All Fujitsu prescalers, except MB501lV, MB504lV, MB501Sl, MB509, and MB510 have an open emitter
output. Typically a 2.2k n resistor to ground for a load capacitance of 12 pF is recommended. By choosing
a smaller or a larger external resistor, the prescaler's output can be tailored to drive higher or lower loads,
respectively.
The prescalers with on-chip termination can drive output load capacitances of up to 8 pF undistorted. A
shunt resistance can be added for driving larger loads.
In some situations it is desirable to "overdesign" the termination resistor. The limited current driving ability will tend to smooth the output signal, thus reducing its harmonic content and switching noise induced
into supply lines.

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Prescalers and PLLs
Tutorial and Selection Guide

Stability of Vout
One of the purposes of prescaling is to eliminate amplitude modulation from the output of the veo.
Therefore, it is absolutely mandatory that the output high and low are stable and guaranteed over a wide
range of Vin, VCCI and tempera ture.

Flexibility of the input voltage
A prescaler should be able to toggle properly with relatively widely varying input voltage levels (anywhere between 0.15 to 2 Vp-p for the Fujitsu MB 504), while maintaining a constant output level.
EeL level

For most Fujitsu prescalers the maximum allowable input voltage swing is 2 Vp-p. This means that a typical ITl voltage swing of 3 V will overload the prescaler, whereas Eel voltage levels can be accommodated without problems. The outputs of the prescaler are Eel compatible, too.
The statement "The outputs are 1.6 V peak on Eel level" found on the data sheet for MB501, 503, 504 etc.
means that Fujitsu prescalers do not require negative supply voltages. In this sense they are not "true"
Eel devices.

Flexibility of Vee
A wide operational range of Vee is essential (2.7 V to 4.5 V, 3.0 V typical for MB501 LV), if a prescaler is to
be used in a battery-powered system. Most Fujitsu prescalers, except the low voltage (lV-suffix) types
which operate from a 3 V supply, operate from a single 5 V supply. The integrated PLls, MB1501 and
MB1504, however, operate from a 3 V supply (a higher supply voltage between Vee and 8 V is required
for the charge pump circuit).

Modulus set-up time
The time from application of appropriate voltage to the modulus select pin to appearance of the correctly
prescaled waveform at the output is 10-50 ns. As previously discussed in the Pll section, fast modulus
set-up times are necessary for correct implementation of the pulse swallow method.

Input impedance and reactance
Excessive reactance may affect performance of the veo and require buffer circuitry between it and the
prescaler. For very high frequencies (> 500 MHz), the input impedance should be given on a Smith chart.
The nominal input impedance of Fujitsu's high frequency prescalers is son.

Smith chart
Signals on a printed circuit board travel at approximately 2/3 the speed of light. This means that at frequencies above 500 MHz, the signal wavelengths become less than 0.4 m and comparable in size to the
board itself. At this point, circuit board traces start acting as transmission lines; i.e., the RMS voltage level
will vary along the trace unless impedances of the termination and the trace are matched.
A Smith chart is a graphical impedance representation widely used in transmission theory. It is a tool allowing an easy assessment of impedance mismatch.

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March 1991
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Presca/ers and PLLs
Tutorial and Selection Guide

The chart consists of two sets of circles: the constant resistance circles (see Figure 19) and the constant reactance circles (see Figure 20). The values of these circles are normalized to the characteristic impedance of
the system by dividing the actual value of resistance or reactance by the characteristic impedance, for example, in a 50 n system, a resistance of lOOW is normalized to a value of 2.0.
A further series of circles may be plotted on the chart; these are the circles of constant voltage standing
wave ratio (VSWR) and represent the degree of mismatch in the system. The VSWR is the ratio of the device impedance to the characteristic impedance. It is always expressed as a ratio greater than 1 (a 25 n
device in a 50 n system gives rise to a 2:1 VSWR). See Figure 21.

Packaging
All Fujitsu prescalers are available in 8-pin DIP or surface mountable 8-pin plastic flat packages. Space
saving and better stray capacitance performance are obtained with surface mounting.
CMOS PLLs and BiCMOS integrated PLLs are available in 16-pin DIP and Flatpacks.

o

Figure 19. Smith Chart Constant
Resistance

Figure 20. Smith Chart Constant
Reactance

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Presca/ers and PLLs
Tutorial and Selection Guide

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Fujitsu Microelectronics, Inc.

IMPEDANCt. OR ADMITTANC.£ COORDINATES

500 MHz
RAOIALL.Y SCALED ""'UM(T[RS

30

•
I

Note:

;

••

... ..
,

The nominal lin is 50 Q.

Figure 21. Input Impedance of Fujitsu's MBSOl L Dual Modulus Prescaler as a Function of
Frequency Shown on a Smith Chart

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Signal propagation delay through the prescaler
Although a signal delay through the prescaler will affect the lock-in times of the loop, the prescaler is, in
this respect, of little importance relative to the loop lowpass filter. Extensive phase shifts between the input and the output of the prescaler may, however, affect the PLL stability.
High capacitive loading will typically be the main cause for delays. This situation can be remedied by decreasing the output termination resistor value, thereby improving drive performance.
Self-oscillation problems can be caused by poor grounding, lack of decoupling, or cross-talk due to board
layout. Fujitsu prescalers are guaranteed to be non-oscillatory under most conditions.

Balanced inputs
The ability to drive balanced inputs can be beneficial at high frequencies. All Fujitsu prescalers offer complementary inputs. The prescaler outputs, however, are single ended as they are intended to drive singleended PLL inputs.

Output duty cycles
The output duty cycle should be 50 percent when the modulus is an even number (such as three input
clock periods high and three input clock periods low for division with modulus 6). Division by an odd
number should cause minimal deviation from 50 percent duty cycle (such as four input clocks high and
three input clocks low for division with modulus 7). Rise and fall times are, of course, load dependent and
deviations from idealized waveforms will occur. Also, clearly specify which of the output half-cycles (output low or output high) is the one that is extended in the M+l mode of a dual modulus prescaler.

Power dissipation
Thanks to a proprietary, "third generation," 0.8 J.l.m emitter self-align and polysilicon electrode and resistor (ESPER) manufacturing technology, Fujitsu can offer bipolar prescalers with the most beneficial frequency rating/power dissipation ratio available. See Table 3.

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Prescalers and PLLs
Tutorial and Selection Guide

Table 3. Fujitsu Prescalers

Please refer to the Prescalers section
in the front of this databook.

Conclusion
For further technical assistance and product information, including updates, please contact your nearest
Fujitsu Microelectronics Sales Office. You will find a listing of the offices at the back of this paper.

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Fujitsu Microelectronics, Inc.

References
Books
1.

Berlin, Howard M. Design of Phase-Locked Loop Circuits, with Experiments. Indianapolis: Howard
W. Sams & Co. 1978.

2.

Blanchard, Alain. Phase-Locked Loops: Application to Coherent Receiver Design. New York:
Wiley-Inter science, 1976.

3.

Egan, William F. Frequency Synthesis by Phase Lock. New York: Wiley-Interscience, 1981.

4.

Gardner, Floyd M. Phaselock Techniques. New York: John Wiley and Sons, 1979.

5.

Kinley, Harold. The PLL Synthesizer Cookbook. Blue Ridge Summit: TAB Books, 1980.

6.

Kroupa, V.F. Frequency Synthesis. New York: Wiley, 1973.

7

Lindsay, W. C. and M. K. Simon, eds. Phase-Locked Loops and Their Application. New York: IEEE
Press, 1978.

8.

Manassewitch, Vadim. Frequency Synthesizers. Theory and Design. New York: Wiley, 1976.

9.

Plessey Semiconductors. Radio Telecoms IC Handbook. Irvine: Plessy Semiconductors, 1987.

10. Rohde, Ulrich L. Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs: PrenticeHall, 1983.

Articles
11. Hillstrom, Tim L. "Design method yields low-noise, wide-range crystal oscillators." EDN (March
1988).
12. Onnond, Tom. "Crystal Oscillators." EDN (October 17, 1985).

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9-34

Proc. Int. Syrnp. SAW Devices for Mobile Cornrn., 179-185, 1992

RESONATOR-TYPE LOW-LOSS FILTERS

Y. Satoh, O. Ikata, T. Matsuda, T. Nishihara, and T. Miyashita
Fujitsu Laboratories Ltd.
10-1 Morinosato-Wakamiya, Atsugi 243-01, Japan
1. Introduction
The application of 800-900 MHz SAW filters as RF filters has contributed to the
recent miniaturization trend in portable telephone terminals(1)·(2). SAW filters merit
attention for their small size and sharp transition-band characteristics, and will
find increased application for further reductions in size and power consumption
and the higher sensitivity of portable telephone terminals. For example, an
antenna duplexer implemented with SAW filters would greatly contribute the size
reduction of telephone terminals. The conventional SAW filter's potential to
implement these improvements will require work to decrease its insertion loss,
obviate an external matching circuit, and increase its power handling ability.
These problems are difficult to solve with conventional transversal filters having
the interdigitated interdigital transducer (IIDT) structure. From 800 to 900 MHz,
the experimental insertion loss limit for IIOT filters is 3 to 4dB with an external
matching circuit (1).(2). The input or output impedance of /lOT filters is usually
capacitive because of the large number of finger pairs and the high relativepermittivity of substrates such as LiTa03 . Hence, conventional !JOT filters need
inductive external matching elements. To overcome these limitations, we
investigated the resonator-type SAW filter having a ladder structure similar to the
ceramic or crystal filter. This filter can have a low insertion loss and does not
require an external matching circiut, but the connection of many resonators
increases tuning difficulty and size. Fortunately, these problems are resolvable
with high-frequency SAW resonators because their frequency of resonance is
controllable in the photolithographic fabrication process, and filter size remains
small due to the short period of the lOT at high frequencies.
2. Principles
In the basic section of a ladder resonator filter (Figure 1), the impedance of the
series-arm resonator (Zs) and the admittance of the parallel-arm resonator (Yp)
are given in the following equations, assuming that they include no resistance:

Zs
Yp

=
=

jXs
jBp

(1)

(2)
The variations of Xs and Bp as a function of frequency are graphed in Figure 2.
Here, the anti resonance angular frequency of the parallel-arm resonator (map)
nearly equals the resonance angular frequency of the series-arm resonator (wrs).

9-35

The image transfer constant (y) of the
basic filter section (Figure 1) is
expressed with Xs and Bp in the
following equation:
tan h (y) = ~ Bp.Xs / (Bp.Xs - 1) (3)
According to the theory of imageparameter filters, the basic section in
Figure
1 shows a passband
characteristic when equation 3 has an
imaginary number. It does, however,
show a stopband characteristic when it
has a real number. Therefore, condition
o < Bp.Xs < 1 gives the passband, and
condition Bp.Xs > 1 or Bp.Xs <0 gives the
stopband (Figure 2). The vicinity of
center frequency roo ( = OOrs = roap ) results
in a passband and both sides out of a
passband result in stopbands. Since Xs
and Bp nearly equal to zero in the vicinity
of the center frequency, the insertion
loss is supposed theoretically to be zero
and the input/output impedance equal to
the line impedance.
3. Simulation
We developed a simulation tool for the
resonator-type filter based on the
Smith's equivalent circuit model(3). We
modified its 3 x 3 admittance-matrix
expression to a 4 x 4 chain-matrix
expression
as
previously
demonstrated(4). The equivalent circuit
used in our simulation (Figure 3)
includes the electrode resistance R(5).
We assumed an electrode line and
space ratio of 1:1. In this simulation, we
added the following electrode effects to
the previous si mulation(2) :
(1) Aperture length of lOT: W
(2) Thickness of lOT: h
The aperture length of lOT W affects
static capacitance Co and resistance R of
one finger as given from the following
equations:
Co =Weo ~/2
(4)
R = 4 W pol (peh)
(5)
Here,
po = 9 ~ .cm (AI-2% Cu, at 1 GHz)
£11 E33: Oielectric tensor components
of the substrate
p: lOT period
9-36

Fig.1 Basic section of a ladder filter
Q)

o
c:
ro

E

E +
.-

'0

~ 0 I-----Ir----::~~l_--­

a.
~

ro c:
'6>
ro
E BpXs

_-'1

1.04

•

,

,-

.....

,

~

-,~

.'

,

1.02

1.00

0

4

2

6

8

10

(x 10.2 )

h/A

Fig.4 Dependence of tv on hi).
,

,

I

~Dtr±r:fD8D~
CJID
CJI
1

1

II Ii

o

1

i

I

I

0

Fig.S Filter structure consisting of three
sections
(a)

en

821

0

~ -10

.§

ca

-20

::J -30

'\

r:::

~

«

-40
-50

850

900

950

1000

Frequency (MHz)
(b)

811

(c)

822

Fig.6 Comparison of the simulation
(solid lines) and experiment
(broken lines)
9-37

the actual center-frequency shift. We then measured the resonant frequency of
one port resonator for various thicknesses and derived 'tv under lOT from it.
Results are plotted by the solid line in Figure 4. The relationship of 'tv to the
thickness under the lOT is obtained experimentally as
'tv = 1 + A + B(h/A) + C(h/A)2
(9)
Here, A=0.022, B=0.413, and C= 7.66. We used this relationship for the
simulations.
In the circuit comparing experimental and simulation results (Figure 5), each
basic section is connected alternately to match image-impedances. Bonding wire
inductance is about 1.5 nH. The structure had 150 finger pairs, 60 J.1m aperture,
and 4.12-J.1m periods in the series-arm resonators, and 40 finger pairs, 160-J.1m
aperture, and 4.30-J.1m periods in the parallel-arm resonators. Each SAW
resonator had short-terminated reflectors. Results of comparison are shown in
Figure 6 when hlA. is 0.073, am is 0.1 X(hlA.) neper/finger, and k2 is 7.5%. We fitted
k2 to the band width in passband and am to the insertion loss in the actual device.
As shown, we obtained good agreement for three S-parameter sets.
4. Filter design
We used a simulation tool developed to investigate design rules for the
resonator-type filter. The following parameters were important for controlling filter
characteristics:
(1) Static capacitance ratio (Cop/Cos) of the parallel-arm resonator(Cop) to the
series-arm resonator(Cos)
o
(2) Static capacitance value for each
individual resonator(Cop,Cos)
Cop/Cos-10
In designing filters, the static
~
0.6capacitance is determined by the
c -20
product of finger pair number and
o
aperture length W.
.~ -30
:::>
First, the static capacitance ratio
c
(Cop/Cos) controls the insertion loss and
~ -40
stop band rejection --a tradeoff (Figure
-<
7). This tendency is the same in a
ceramic filter. If filter specifications call
for a low insertion loss, we should select
the lower value of Cop/Cos; for a high
Fig.7
stop-band rejection, we would choose
the higher Cop/Cos.
We next found that the filter's
(b)
11
(a) S21
input/output impedance can be
_
0""'-"--"'--"'-'---"""-'
controlled by changing the values of Cop
CD
~·10
and Cos, while keeping the value of
.§ -20
Cop/Cos constant. Figures 8 to 10 show
the variation of S parameters (S21 and
~ -30
S11) when Cop and Cos are increased
2 -40
and Cop/Cos=0.75. Small dotted circles in
~ -50 850 900 950 1000
the Sl1 charts indicate the borderline of
Frequency (MHz)
r=O.33 (SWR=2.0). When the Sl1 values
of the passband are within these circles,
Fig.8 S-parameter characteristics
th.e filter is in the matching condition.
under Cop=1.6 pF and Cos=2.1 pF
Figures 8 and 10 show the unmatched

m·

S

9-38

condition, while Figure 9 shows the
matched condition. Therefore, Cop and
C os can be combined to optimize
impedance matching (the shaded area
in Figure 11). Figure11 (a) is for a 933MHz filter and (b) is a 1.S-GHz filter.
Optimum values of Cop and Cos exist for
al most all practical Cop/Cos values to the
matching condition.
We considered the matching condition
mechanism using a simple model. Since
the resonator-type filter is simply
expressed by the LC equivalent circuit
(see Figure 1), each resonators
impedance, Zs and Zp, is given by the
following equations, using the symbols
from Figure 1,
Z5=( ro 2-rors2) / jroCos( ro 2-roas 2 ) (10)

(b)

(a) 821
_

en

S 11

0'--'--"""""'''''''''''-'''''''-

::.!2..·10

.§ -20
~

·30

2
« -50 850
-40

900

950

100e

Frequency (MHz)

Fig.9 S-parameter characteristics
under Cop=2.7 pF and Cos=3.6 pF

(a)
_
en

821

(b)

S 11

o,.....,...-~........--~

:2. -10

.§ -20
~

-30

Zp=(ro2-rorp2) / jroCop(ro2-roap2) (11)
2 -40
where
« -50 850 900 950 1000
CDrs =1/ ~ L1s C1S:
Frequency (MHz)
Resonant angular frequency
Fig. 10 S-parameter characteristics
of the series-arm resonator
under Cop=3.7 pF and Cos=S.O pF
CDas = ro rs(1 +C1s/2CosF
Antiresonant angular frequency
(a) to =933 MHz
of the series-arm resonator
rorp=1/ ~ L1p C1p:
Resonant angular frequency
of the parallel-arm resonator
Wap=Olrp(1 +C 1p/2Cop)=
Antiresonant angular frequency
of the parallel-arm resonator
For the matching condition of the
constant K-type filter, the following
relationship must be satisfied:
Zs xZp= R2
(12)
Cos (pF)
As shown in Figure 2, the following
(b) to = 1.5 GHz
relationships is assumed,
COap=rors= roo, roO-rorp=roas-roO
2(00» .1ro, .1ro=(COas-COrp ) /2
(13)
where 000 is the center frequency of the
filter. From equations 12 and 13, the
relationship becomes:
R2= 11 (COo 2 Cos Cop)
(14)
The relationship of equation 14 is plotted
by the solid fine in Figures 11 a, and b.
Cos (pF)
Note that the matching areas shaded
Fig.11
Optimum
relations
between Cop
agree well with the equation 14, except
and
Cos
for
impedance
matching
for high Cop/Cos values.
9-39

5. Low-loss RF filter development
We designed and fabricated RF filters for portable telephone terminals using the
rule we obtained on static capacitance. We used an AI-Cu sputtered film for the
electrodes and a 36°y-x LiTa03 crystal for the piezoelectric substrate. As an
example, Figures 12 and 13 show the 521 and 5WR characteristic of a 900-MHz
filter designed under capacitance conditions of Cop=3.0 pF, Cos=3.2 pF, and
Cop/Cos=O.94. For comparison, the same characteristics of a conventional \lOT
filter are also shown. Note that the insertion loss of the resonator-type filter is
improved by 2 dB and that its SWR is less than 1.9, indicating no need for an
external matching circuit. Figures 14 and 15 show the 521 and SWR characteristic
of a 1.5-GHz band filter fabricated using an i-line stepper. The capacitance
values are Cop=2.26 pF, Cos=1.6 pF, and Cop/Cos=1.4, giving us low-loss
characteristics (IL<2.5 dB) and the matched condition (5WR<1.5). These filters
are mounted in a 3.8 x 3.8 x 1.5 mm ceramic SMT package (Figure 16).
6. Conclusion
We investigated a bandpass filter using 5AW resonators with a ladder structure.
To calculate optimum design conditions, we developed a detailed simulation tool
__

O~N----~~~~~~

3.0 ..

en

~ -1 0 I----'-----'-~+_~---r--+---I

1 .OL--...l-'--'----'--'--'-'---'---'--J--.I

932

1032

Frequency

Fig.12 521 characteristics of 900-MHz
filters for portable telephones

o

832

932

Frequency

(MHz)

Fig.13 5WR characteristics of 900-MHz
filters fqr portable telephones

vt'\

10

\
\

a:

c

.,8 -25
ct:l
:J
C

r--....

Q)

~

~

y.J

-50
1. 26

""

C1)5

/
II,..

/
v

\

1. 66
1. 46
Frequency (GHz)

Fig.14 521 characteristics of 1.5-GHz
filters for portable telephones
9-40

1
1.26

\. I~
1.46
1.66
Frequency (GHz)

Fig.15 5WR characteristics of 1.5-GHz
filters for portable telephones

which considered the aperture and electrode thickness. We fabricated 900-MHz
and 1.5-GHz bandpass filters as examples, and confirmed that the insertion loss
decreased compared to that for conventional IIOT filter, and that the input or
output impedance was nearly 50 O. These features will be useful in the
development of advanced portable telephone terminals.

Fig.16 3.8 x 3.8 x 1.5 mm SMO package
Acknowledgements
The authors would like to thdnk K. Komenou for his encouragement, N.
Wakatsuki for his helpful suggestions, Y. Fujiwara and H. Omori for their supply of
SMD packages and many technical supports.
References
(1) M. Hikita, H. Kojima, T. Tabuchi, and Y. Kinoshita, "800-MHz high-performance
SAW filter using new resonant configuration", IEEE Trans. on MIT, vol. MIT33,No.6,p.510, 1985.
(2) O. Ikata, Y. Satoh, T. Miyashita, T. Matsuda, and Y. Fujiwara, "Development of
a~O-MHz band SAW filters using weighting for the number of finger pairs",
1990 Ultrasonics Symposium, Proceedings, p. 83, 1990.
(3) W. R. Smith, H. M. Gerard, and W. R. Jones, "Analysis and design of dispersive
interdigital surface-wave transducers," IEEE Trans. on MIT, vol. MIT-20, No.
7, p. 458, 1972.
(4) H. Sato, K. Yamanouchi, and K. Shibayama, "Studies on the triple transit echo
of acoustic surface wave filter", Paper of Technical Group, JIEICE, US-7325, pp. 1-14, 1973(in Japanese).
(5) N. Nakayama, N. Wakatsuki, and M. Nakamura, "Effects of stray capacitance
and electrode resistance on the acoustic surface wave transducers", Paper of
Technical Group, JIEICE, US-73-48, pp. 1-10, 1973(in Japanese).
(6) T. Kojima and H. Hoshi, "Investigation of SAW resonators utilizing energy
storage effect", Paper of Technical Group, JIEICE, US-86-21, pp. 61-68,
1986(in Japanese).

9-41

9-42

Land S Band Low-Loss Filters
using SAW Resonators
T. Matsuda, H. Uchishiba, O. Ikata, T. Nishihara and Y. Satoh
FUJITSU LABORATORIES LTD.
Akashi, Japan
communication network (peN) in Europe around

Abstract
This paper describes Land S band low-loss filters

1.8 GHz. and wireless LAN system around 2.4 GHz.

using one-port SAW resonators in a ladder circuit

The filters used in these systems are required to

structure.

Four kinds of filters were developed.

have low-loss. wide band and sharp band edge

Three types have a wide frequency band. with

characteristics with small package size. The ladder
type SAW filters reported previously').2) are suitable

fractional bandwidth of about 4%. A 36° y-x LiTa03
substrate was used for these. The last type of filter

tor these requirement.

has a narrow frequency band. with 0.03% of

frequency versus its fractional bandwidth. and

fractional bandwidth. and used an ST-cut quartz
substrate. To design these ladder type SAW filters,
several important factors were considered. the

Figure 1 shows the tilter

areas which have been realized by using ladder
type SAW filters. The 800 MHz filters for use in
advanced mobile phone systems (AMPS) were

static capacitance of lOT. the period of lOT and film

reported in the previous paper').

thickness.

For fabrication. i·line stepper and

these same techniques are applied to Land S

reactive ion etching was used to delineate fine lOT

band filters with a wide range of fractional

patterns with line and gap width of 0.4 to 0.7

~m.

In this paper.

bandwidths.

Minimum insertion losses of 2 dB were obtained for
the three wide band fifters. The insertion loss ot the
narrow band tilter was 6 dB. The input and output
impedance of these filters were 50 n. The filters
were mounted in 3 mm x 3 mm x 1 mm or 3.B mm x
3.8 mm x 1.5 mm SMT packages.

;?

5

~

.c

-E

3

C

as

J:l

1. Introduction
The

spread

of

the

mobile

communication systems has increased the demand
of SAW filters and this market will extend in the
future.

In order to accept a large number of

subscribers. the

2

(ij

worldwide

C

.E
U
....as

00

LL

~

LiTa03

4

i
-0

/

~

800 MHz
(AMPS)

1.5 -2.4 GHz

tf
c

Quartz
2

3

Frequency (GHz)

frequency band ot mobile

communication systems has become higher. The
recent increase in data communications has given

Figure

further impetus to this market.

bandwidth. The shaded areas closed by solid line
are described in the present paper.

For example. the

personal digital cellular (PDq in Japan uses the
frequency range around 1.5 GHz. personal

1

Filter frequency versus its fractional

9-43

2. Filter specifications
Japanese POC, European PCN and wireless LAN
were selected as targets for the wide band filter
application. These three filters used LiTa03 as a
substrate. For the narrow band pass filter
application, the timing filter of HOTV was developed
by using a quartz substrate. Table 1 shows these
tilter specifications. As shown in Table 1, each
specification of four systems has a different deSign
difficulty. PCN in Europe requires the widest
fractional bandwidth of 4.3%. Wireless LAN in
Europe requires high stopband rejection with wide
bandwidth. HOTV requires the narrowest fractional
bandwidth of 0.03%..

3. The design of wide band-pass filters
Figure 2 shows the outline of a one-port SAW,
resonator and the these basic ladder circuit
structure used. As suggested in the equivalent
circuit of Figure 2, the one-port SAW resonator has
dual resonance frequencies. In the ladder type
filter design, the anti-resonance frequency of the
parallel arm resonator nearly coincides with the
resonance frequency of the series arm resonator. A
number of basic ladder circuits are connected so as
to minimize the impedance mismatching as shown
in Figure 3. The character L in Figure 3 indicates
the inductance of the bonding wire used in the
connection to the SMT ceramic package. The
resonance frequency of each resonator is designed
by the period of lOT. In the design of the ladder
type filter, the important factors that effect the filter'S
characteristics are described in the following
example of the PCN filter design.

(1) Resonators' capacitance product (CsCp)
When the series arm resonators' static
capacitance and the parallel am resonators' SIalic
capacitance are symbolized as Cs and Cp
respectively, the product of Cp and Cs can control
the input and output impedance of the ladder type
filters )·2) as the equation.
'
CpCs", 1/(~R2)
(1)
Here, Wo is the center angular frequency of the filter
and A is the line impedance which is usually 50 O.
This relationship is plotted in Figure 4 for the center
frequency (fo) of 1.5 GHz, 1.8 GHz, 2.4 GHz. The
higher fo, the smaller the value of CpCs becomes.
The static capacitance value is determined by the
product of aperture length and finger pair number of
lOT. Therefore, the small static capacitance results
in the small size of lOT, that is, the small chip size.
The ladder type SAW filter is suitable for high
frequency filter in view of the package size.
Resonator

a) A SAW resonator
and its equivalent circuit.

(b) A basic ladder
circuit structure.

Figure 2 The outline of a one-port SAW resonator
and a basic ladder circuit structure used.

Table 1 SAW filter specifications

PDCin~

PeN in E.".

Cenw

T.:, 44' GHz
Rx.uallGHz

T.:l.7475GHz
RI:' 8425 GHz

2.4SGHz

1.4850Hz

7SMHl

lOOUHz

400kHz

~

8andwIdII

Inset1IOn lou
al baI'dwodIh
SIOpband
anenualion

9-44

WniessLAN Tinmgfiller
IotHOTV
inEIoI"Op8

Item

24 MHz
3dB

4dB

Sd8

7dB

30 dB

20 dB

40 dB

32 dB

Figure 3 A filter structure connecting three basic
sections. The character L indicates the inductance
of bonding wire.

(2) Resonators' capacitance ratio (Cp/Cs) and the
number of basic ladder circuits

5

The filters' insertion loss and stopband attenuation

4

CL
oS

are affected by the ratio Cp/Cs.

3

2

C.

Figure 5 shows

dependencies of the bandwidth, the stopband

0

°0

3

2

4

Cs (pF)
Figure 4 Optimum relations between Cp and Cs
for impedance ")atching.

attenuation and the minimum insertion loss on
Cp/Cs in the frequency range around 1.8 GHz. As
shown in Figure 5, if Cp/Cs becomes larger,
bandwidth is narrower. The minimum insertion loss
didn't change, but the nominal insertion loss
averaged over the passband increased. It is
necessary for the PCN specification that the
stopband attenuation is larger than 20 dB and the
bandwidth is wider than 82 MHz over a temperature
range of -30 to 70 ac. It is noticed in Figure 5 that
both the stopband attenuation and bandwidth

100

N

80

~

60

:::J:

.t::.

i5

i'C
e::

CD

40

Bandwidth

Slop-band

~

20

m
0

0.4

0.8

1.0

specifications can't be satisfied together.

.com
~

development to solve this problem is described in
the later section.

JOe::
.2

same characteristics as Cp/Cs. By increasing the

20~
e::
CD
10 :=

Minimum
insertion loss S 0.6

50

et

1.2

A new

The number of basic ladder circuits show the
number, the stopband attenuation is improved, the
insertion loss is increased and the bandwidth
becomes narrower.

0

(3) The difference of period, 6."A.

CplCs

The anti-resonance frequency of the parallel arm
Figure 5 Dependence of bandwidth, the stopband
attenuation and minimum insertion loss on Cp/Cs in
the frequency range around 1.8 GHz.

resonator and the resonance frequency of the
series arm resonator are controlled by 6."A. which is
the difference between lOT periods of the parallel
arm resonator and the series arm resonator. The
anti-resonance frequency of the parallel arm
resonator doesn't need to be equal to the

N

%:

!.

eo

.c

60

i'C

40

i5
e::

CD

m

20
0
0.06

resonance frequency of the series arm resonator.
The passband can be extended by increasing 6."A..

5

100

a.ndwIdth (MHz)

~

/7
0.07

0.08

~A

0.09

4

3::a:
U)

2

1
0.10

(J,Lm)

Figure 6 Dependence of band width and SWR on
6."A. in the frequency range around 1.8 GHz.

The standing wave ratio (SWR), however, becomes
larger by increasing 6."A..
Figure 6 shows
dependence of SWR and bandwidth on 6.). in the
frequency range around 1.8 GHz. When the limit of
SWR is less than 2.0, the bandwidth is limited to 70
MHz which is insufficient for the PCN specification.
(4) Film thickness. h
The number of basic ladder circuits . .1). and Cp/Cs
are related to each other as described above and
the wide band filter for PCN can't be realized by

9-45

adjusting
these
factors.
However,
electromechanical coupling factor (k 2) of the

4. The design of a narrow band-pass filter
This filter used an ST-cul qu~rtz as substrate and
SH-type SAW3). The dielectric constant of quartz is

piezoelectric substrate was noticed to relate the
fractional bandwidth. If k2 is larger, the bandwidth is

much smaller than that of LiTa03. Therefore, the

wider.

size of lOT needs more space compared with

The electromechanical coupling factor is

given in the following equation.

LiTa03 substrate in order 10 design the impedance
matching. The value of ~ is very small, about 0.01
~m.

(2)

Some attention is therefore needed to control

LU. To precisely control .1A., the reticle is made with

Here,
Vo: free surface velocity
Vm : metal surface velocity

very high accuracy.

As apparent in this equation, if Vm become slower,
k 2 become larger. The thicker film thickness of lOT
is available to make Vm slower, but the nominal
insertion loss may be increased by making the
electrodes thicker.
Figure 7 shows the
experimental dependence of bandwidth, insertion,

5. Fabrication and evaluation of filters
The electrode film consisted of AI-Cu alloy
deposited by the DC sputter on piezoelectric
substrates. The lOT photoresist patterns were
exposed on an i-line stepper. Figure 8 shows lOT

loss and SWR on the film thickness. The values of
CplCs and .1A. were constant in Figure 7, but the

photoresist patterns for 2.4 GHz. The line and gap
width of lOT patterns were 0.4 ~m. The reactive ion
etching was used to avoid surface damage of a

passband was extended and SWR became less
than 2.0 by increasing the film thickness. Contrary

substrate. Figure 9 shows the S21 and SWR
characteristics of 1.5 GHz filter for PDC. This filter

to the anticipated result, the insertion loss didn't
deteriorate for these film thicknesses. The reason
for this characteristic may be that the insertion loss
is recovered by increasing k2 through making the

had 2 dB minimum insertion loss, 38 MHz
bandwidth at 3 dB and about 30 dB stopband
attenuation. The SWR was less than 2.0 in the
passband.
Figure 10 shows the same

electrodes thicker. For further increasing the film

characteristics of 1.8 GHz filter for European PCN.

thickness, the insertion loss will deteriorate due to

The maximum fractional bandwidth in this study

bulk wave radiation. For PCN specification, a
sufficient bandwidth (85 MHz) and an SWR «2.0)

was obtained. Filter characteristics were 85 MHz
bandwidth at 4 dB and about 20 dB stopband

are obtained at 0.2

~m

120
Insertion loss

'N

::c 100
~

=80

"C

i
'g60

0

40

.:s;;::+

~
Bandwidth

~~

as
m

0.10

0.15

attenuation. The SWR was less than 2.0. Figure 11
shows the wireless LAN filter. The bandwidth was

film thickness.

0.20

"Cm

30
21::

~

=,g=

1
0.5

5
4
3
2
1
0.25

a:

;:
en

Film thickness (J,lm)

110 MHz at 5 dB and the stopband attenuation was
about 45 dB which was a very high value. The
SWR was less than 2.5. Figure 12 shows a timing
filter for HDTV. The bandwidth of 400 kHz at 6.S
dB, which was the minimum fractional bandwidth of
0.03% in this study, about 30 dB the stopband
attenuation and the SWR of less than 2.0 were
obtained. The HoTV filter and POC filter were
mounted in a 3.8 mm x 3.8 mm x 1.5 mm ceramic
SMT packages. The other filters were mounted in 3
mm x 3 mm x 1 mm ceramic SMT packages.

Figure 7 Dependence of bandwidth, insertion loss
and SWR on the film thickness in the frequency
range around 1.8 GHz.

9-46

i::[;Q ~:'EE
1.40

1.45

1.50

Frequency (GHz)

(a) S21

1.40

1.45

1.50

Frequency (GHz)

(b)5WR

Figure 12 521 and SWR characteristics of 1.5 GHz
filter for HOTV.

L-J

1 J..lm

Figure 8 lOT photoresist patterns for 2.4 GHz.

6. Conclusion

1.':Q] ~"D1J
!

Ci -50

1.26

1.46

1.66

1
1.26

Frequency (GHz)

1.46

1.66

Frequency (GHz)

(b)SWR

(a) S21

Figure 9 521 and SWR characteristics of 1.5 GHz
filter for Japanese POC.

i·,:Eillr ~"[IT]
~

-50
1.4

1.8

2.2

1
1.4

1.8

2.2

Land S band low-loss filters were developed
using the ladder type filter made of one port SAW
resonators. The filters for POC in Japan, PCN in
Europe and wireless LAN in Europe were
successfully developed as wideband applications,
and HOTV filter was developed as a narrow band
application.
These filters' characteristic
impedances were all 50 O. The properties of these
filters will be useful in the future development of the
wireless communications systems discussed.
Acknowledgement
The author would like to thank Y. Fujiwara for his
supply of 5MT package and H. Omori for his helpful
suggestions.
Reference

Frequency (GHz)

Frequency (GHz)

(1) O. lkata, T. Miyashita, T. Matsuda, T. Nishihara

(a)~l

(b)SWR

and Y. Satoh, "Development of Low-loss Band-

Figure 10 S21 and SWR characteristics of 1.8 GHz

Pass Filters Using 5AW Resonators for Portable

filter for European PCN.

Telephones": IEEE, Ultrasonic symposium, pp. 111115, (1992)

f.,:[[] ~"1\n

·~

2.0

2.5
Frequency (GHz)

(a) S21

3.0

,~
2.0

2.5

(2)Y. Satoh, O. Ikata, T. Matsuda, "A Band-Pass
Filter Using One-Port SAW Resonators", FUJITSU
Scientific & Technical Journal, Vol. 29, No.4,
pp.367-376 (December, 1993)

3.0

Frequency (GHz)

(b)SWR

(3)T. Nishikawa, A. Tani, C. Takeuchi, ·SH-Type

Figure 11 S21 and SWR characteristics of 2.4 GHz

Surface Acoustic Waves on Rotated V-cut Quartz",
FUJITSU Scientific & Technical Journal, Vol. 17 No.

filter for wireless LAN.

4, pp.99-113 (December, 1981)

9-47

9-48

- - - - - - - - - - - - SECTION 10
Quality and Reliability

10·1

10-2

Fujitsu Quality Program
To ensure the best quality in our semiconductor products, Fujitsu conducts a complete program of inspections at every phase of
processing.
The wide range of inspections in our manufacturing programs ensures that every product has the quality and reliability for which
it was designed Statistical analysis evaluates these results objectively.

Incoming Inspections
Whenever a Fujitsu plant purchases materials or components from another manufacturer, the Quality Control Group conducts an
incoming inspection. The group visits the supplier's factories to convey the importance Fujitsu places on the quality of everything
we buy. Moreover Fujitsu will work together with the suppliers to maintain and improve the quality of their products.
Every year, we award the best manufacturers to encourage all our suppliers to maintain and improve the quality of their products

Control Flow for the Purchase of Materials and Components
Requesting for Ordering Materials and Components
According to Production Plan (to Procurement Group)

Production Control Group

~--'L.';;;;;;;;;.,J

Ordering/Purchasing (to Material Supplier)

Procurement Group

Delivery of Materials and Components
(From Supplier to Production Control Group)

Production Control Group

Incoming Inspections of Materials and Components

Quality Control Group

Production Control Group

Manufacturing Control Group

10-3

Quality Control Flow Chart
Check Item

Inspection of Incoming Material

Waler Surface Inspection, Monitor Test 01 Film Thickness

Test 01 Electrical Charaderislica, Stress Test (100% inspection)

Passivation (Insulation Layer Formation)

Sample Surface Inspection AQL 0,65% Levell

Bond ·welling and SurfacelnspectionlSample Wire Bond Strenglh TesllMonHor Test 01 Sample Run lor Machine Calibration,

In-Process Manufacturing Group Inspections
Fujitsu's Manufacturing Groups implement these inspections to set control items and standards for each manufacturing process.
Prompt feedback maintains and improves the quality consciousness throughout the groups.
Inspections occur regularly for each lot and/or each production line.

In-Process QC Group Inspections
The Quality Control Groups inspect at the end of each major manufacturing.
Using the sampling standards. the groups confirm the level of quality before the products proceed to the next phase.

10-4

Statistical Process Control (SPC)

16M DRAM Oxide Thick

Fujitsu's SPC program uses statistical analysis. Engineering Groups set the major quality parameters and
their spec value for the manufacturing processes to assure the proper quality. The Manufacturing Groups determine the control values for the equipment and conditions for the production process.
Once mass production begins, the Manufacturing
Groups implement control plans to check and improve
the product capability to each process.
Some important parameters are film thickness, monitor
characteristics, bonding strength, electrical characteristics and yield (see figure at right). Computer software
checks each parameter automatically.

UL
UCL
~

Q)

~ p.---r--~~~------~~~------~--------~~
.c

I-

~

LCL
LL

~~

~~~~
Lot No.

o•

Pre-Cap Visual Inspection
Internal Mechanical Inspection

Leak Test (Hermetic Package only)

Production Process
Testllnspection·

[I)

Production Process and
Testllnspection

+

oc Gate (Sampting)

Lead Cutting and Forming

External Visual Inspection

External Sampling Vosuallnspection AOL 1.0% Levell

Shipping Test
Electrical Characteristics Test: AOL 0.25% Levell
External Visual Inspections: AOL 1.0% Levell
Ex1emal Visuallnspactions: AQL 1.0"4 Levell (Ceramic PKG)

Reliability Test
(Lot tests!
Periodic
Test)

Endurance and Environment Tests/Ali Sampling Tesls

Warehousing

10-5

10-6

- - - - - - - - - - - - SECTION 11
Ordering Information

III

11-1

11-2

ORDERING INFORMATION FOR STANDARD PRODUCTS

Part Number

Description

Package Type

Options

PRESCALERS
MB501L

M850lLV
MB501SL

MB504

MB504L

MB504LV
MB505-16
MB506

MB507

1.1 GHz Prescaler DIP-GSP-MOl
FPT-OSP-MOl
FPT-GSP-MOl
1.1 GHz Prescaler DIP-OSP-MOl
FPT-GSP-MO 1
1.1 GHz Prescaler DIP-GSP-MOl
FPT-GSP-MOl
--1-FPT-GSP-MOl
520 MHz Prescaler DIP-GSP-MOl
FPT-GSP-MO 1
FPT-GSP-MO 1
520 MHz Prescale DIP-GSP-MOl
FPT-GSP-MO 1
FPT-GSP-MOl
520 MHz Prescaler DIP-GSP-MOl
FPT-GSP-MOl
1.6 GHz Prescaler DIP-OSP-MOI
FPT-OSP-MOl
2.4 GHz Prescaler DIP-OSP-MOl
FPT-OSP-MOl
FPT-GSP-MO 1
1.6 GHz Prescaler DIP-OSP-MOl
FPT-GSP-MOI
---"----"--------- ---FPT-GSP-M01
2.3 GHz Prescaler DIP-GSP-MOl
FPT-GSP-MO 1
FPT-GSP-M01
1.1 GHz Prescaler DIP-OSP-MOl
FPT-OSP-MOl
2.7 GHz Prescaler DIP-OSP-MOl
FPT-OSP-MOl
FPT-GSP-MO 1
2.7 GHz Prescaler DIP-OSP-MOl
FPT-GSP-MOl
1.0 GHz Prescaler FPT-OSP-MOl
&VCO

T&R

T&R

T&R

T&R

T&R

~-

MB50S

MB509
MBS10

MBSll
MB551

T&R

T&R

T&R

Order Number

MBS01LP
MBS01LPF
MBSOl LPF-ER
MBS01LVP
MBS01LVPF
MBS01SLP
MB501SLPF
MBSO 1SLPF-ER-----MB504P
MB504PF
MB504PF-ER
MB504LP
MB504LPF
MB504LPF-ER
MBS04LVP
MB504LVPF
MB505-16P
MB505-16PF
MB506P
MB506PF
MB506PF-ER
MBS07P
MBS07PF
MBS07PF-ER
MB50SP
MBSOSPF
MB50SPF-ER
MBS09P
MB509PF
MBS10P
MBS10PF
MB507PF-ER
MBSllP
MBS11PF
MBS51PF

--- ---. __._-

III

11-3

ORDERING INFORMATION FOR STANDARD PRODUCTS

•
Part Number

Description

Package Type

CMOS PUs
MB87oo1A

13 MHz PLL

MB87006A

17 MHz PLL

MB87014A

180 MHz PLL

MB87076
MB87086A

10 MHz PLL
95 MHz PLL

MB87087
MB87091

17 MHz PLL
300 MHz PLL

MB87093A
MB87094
MB87095A
MB87096A

145 MHz PLL
15 MHz PLL
110 MHz PLL
90 MHz PLL

DIP-16P-M04
FPT-16P-M06
DIP-16P-M04
FPT-16P-M06
DIP-16P-M04
FPT-16P-M06
FPT-16P-M06
FPT-16P-M06
DIP-16P-M04
FPT-16P-M06
FPT-16P-M06
FPT-16P-M06
FPT-20P-M03
FPT-16P-MOS
FPT-16P-MOS
FPT-16P-MOS
FPT-16P-MOS

SUPER PLLs
MB15AOl
MB15B01
MB1S01

MB1S01H
MB1S01 L
MB1SA02

MB1S02
MB1S02H
MB15803
MB15F03
MBl503

11-4

FPT-16P-MOS
FPT-20P-M03
DIP-16P-M04
FPT-16P-M06
FPT-16P-M06
FPT-16P-M06
1.1 GHz SPLL
FPT-16P-M06
FPT-16P-M06
1.1 GHz SPLL
FPT-16P-M06
FPT-16P-M06
1.1 GHz SPLL
FPT-16P-MOS
FPT-20P-M03
FPT-16P-M06
1.1 GHz SPLL
FPT-16P-M06
FPT-16P-M06
1.1 GHz SPLL
1.1/.3 GHz D-SPLL FPT-16P-MOS
2.0/.5 GHz D-SPLL FPT-16P-MOS
FPT-16P-M06
1.1 GHz SPLL

Options

MB87001AP
MB87001APF
MB87006AP
MB87006APF
MB87014AP
MB87014APF
MB87014APF-ER
MB87076PF
MB87086AP
MB87086APF ------_.__.._--MB87087PF
MB87091PF
MB87091PFV
MB87093APFV
MB87094PFV
MB8709SAPFV
MB87096APFV

T&R

~-

1.1 GHzSPLL
1.1 GHz D-SPLL
1.1 GHz SPLL

T&R
T&R

__ ._-----

_. __.. _._._---- . __.

T&R

T&R

Order Number

MB15A01PFV1
MB15BOlPFV
MB1S01P
MB1S01PF
MB1S01 PF-ER
MB1S01HPF
MB1S01
HPF-ER
-----_.__._---_._._..•.__ .. _--MB1S01LPF
MB1SOl LPF-ER
MB15A02PF
MB1SA02PFV1
MB1SA02PFV2
MBl502PF
MB 1S02PF-ER
MBl502HPF
MB1SB03PFV1
MB1SF03PFV1
MB1503PF

------_.._-

ORDERING INFORMATION FOR STANDARD PRODUCTS
Part Number

Description

MBl504

520 MHzSPLL

MBl504H
MBl504L
MB15E05
MBl505
MB15E06
MBl506
MBl507
MBl508
MBl509
MB15U10
MB1510
MB15B11
MB1511
MB1512
MB15B13
MB1513
MB1514
MB1515
MB15A16
MB1516A
MB1517A
MB1518
MB15A19
MB1519
MB15S02

Package Type

DIP-16P-M04
FPT-16P-M06
FPT-16P-M06
520 MHzSPLL
FPT-16P-M06
FPT-16P-M06
520 MHzSPLL
2.0 GHz SPLL
FPT-16P-MOS
600 MHzSPLL
FPT-16P-M02
2.5 GHz SPLL
FPT-16P-MOS
2.0 GHz SPLL
FPT-20P-M03
2.0 GHz SPLL
FPT-16P-M06
FPT-20P-MOl
2.5 GHz SPLL
400 MHz D-SPLL FPT-20P-MOl
1.1 GHz D-SPLL
FPT-20P-M03
1.1 GHz D-SPLL
FPT-20P-M01
FPT-20P-MOl
1.1/.4 GHz D-SPLL FPT-20P-M03
FPT-20P-M03
1.1 GHzSPLL
FPT-20P-M03
1.1 GHzSPLL
FPT-20P-M03
FPT-20P-M03
1.1 GHz D-SPLL
FPT-20P-M03
1.1 GHz SPLL
FPT-20P-M03
FPT-20P-M03
400 MHz D-SPLL FPT-20P-MOl
2.5 GHz SPLL
FPT-20P-M03
FPT-16P-MOS
1.1 GHzSPLL
FPT-16P-MOS
FPT-16P-MOS
1.1 GHzSPLL
FPT-16P-MOS
1.1 GHz SPLL
FPT-16P-M05
FPT-16P-M05
2.5 GHz SPLL
FPT-16P-M06
FPT-16P-M06
600 MHz D-SPLL FPT-20P-M01
600 MHz D-SPLL FPT-20P-MOl
300 MHz MASKED SOP-8P-M03

Options

Order Number

MBl504P
MBl504PF
T&R
MB 1504PF-ER
MBl504HPF
MBl504LPF
MB15EOSPFV1
MBl505PF
MB 15E06PFV1
MBl506PFV -----_. ---_.._MBl507PF
MBl508PF
MBl509PF
MB15U10PFV
MB1510PF
T&R
MB 151 OPF-ER
MB15B11PFV
MB1511PFV
T&R
MB1511PFV-ER
MB1512PFV
T&R
MB 1512PFV-ER
MB15B13PFV
MB1513PFV
MB1513PFV-ER
T&R
MB1514PF
MB1515PFV
- - - - - - - -r--- ----MB15A 16PFV1
T&R
MB15A 16PFV1-ER
MB1516APFVl
T&R
MB1516APFV1-ER
MB1517APFV1
T&R
MB1517APFV1-ER
MB1518PF
T&R
MB 1518PF-ER
MB15A19PF
MB1519PF
MB15S02PFV

01

11·5

ORDERING INFORMATION FOR STANDARD PRODUCTS

11-6

Part Number

DescrlpHon

Package Type

SUPER ANALOG
MB531
MB539
MB54501
MB54502
MB54503
MB54609
MB54619

1.1 GHz MIXER
1.6GHzLNA
1.1 GHz LNA/MIX
1.1 GHz D-LNA
1.1 GHzAMP
1.0 GHz I/Q MOD
2.0 GHz I/Q MOD

FPT-8P-MOl
FPT-8P-M03
FP-16P-MOS
FP-16P-MOS
FP-16P-MOS
FPT-20P-M03
FPT-20P-M03

SAW FILTERS
FAR-FSCB-836MSO-G201

AMPS SAW

SXSMM

FAR-FSCB-881 MSO-G201

AMPS SAW

SXSMM

FAR-FSCB-881 MSO-G211
FAR-FSCB-888MSO-G201
FAR-FSCB-933MSO-G202
FAR-FSCB-911 MSO-G201

AMPS SAW
ETACSSAW
ETACSSAW
NTACSSAW

SXSMM
SXSMM
SXSMM
SXSMM

FAR-FSCB-902MSO-G201
FAR-FSCB-947MSO-G201
FAR-FSCB-947MSO-G211
FAR-FSCC-836M50-L2AA
FAR-FSCC-836M50-L2AZ
FAR-FSCC-881 M50-L2AB
FAR-FSCC-881 M50-L2AY
FAR-FSCC-933M50-L2BA
FAR-FSCC-878M50-L2BB
FAR-FSCC-888M50-L2CA
FAR-FSCC-933M50-L2CB
FAR-FSCC-911 M50-L2DA
FAR-FSCC-856M50-L2DB
FAR-FSCC-902MSO-L2EA
FAR-FSCC-902M50-L2EZ
FAR-FSCC-902M50-L2EX
FAR-FSCC-947M50-L2EY
FAR-FSCC-897M50-L2KA
FAR-FSCC-942M50-L2KB
FAR-FSCC-942M50-L2KY

NMTSAW
NMTSAW
NMTSAW
AMPS SAW
AMPS SAW
AMPS SAW
AMPS SAW
NTISAW
NTISAW
ETACSSAW
ETACSSAW
NTACSSAW
NTACSSAW
NMTSAW
NMTSAW
NMTSAW
NMTSAW
EGSMSAW
EGSMSAW
EGSMSAW

SXSMM
SXSMM
SXSMM
3.8X3.8 MM
3.8X3.8 MM
3.8X3.8 MM
3.8X3.8 MM
3.8X3.8 MM
3.8X3.8 MM
3.8X3.8 MM
3.8X3.8 MM
3.8X3.8 MM
3.8X3.8 MM
3.8X3.8 MM
3.8X3.8 MM
3.8X3.8MM
3.8X3.8 MM
3.8X3.8 MM
3.8X3.8 MM
3.8X3.8 MM

Options

Order Number

MB531PF
MB539PFV
MB54501PFV
MB54502PFV
MB54503PFV
MB54609PFV
MB54619PFV ------3KT&R
lKT&R
3KT&R
lKT&R
3KT&R
lKT&R
lKT&R
3KT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
lKT&R

FSCB-836MSOG201 R
FSCB-836MSOG20 1T
FSCB-881 MSOG20 1R
FSCB-881 MSOG20 IT
FSCB-881 MSOG211 R
FSCB-888MSOG20 1T
FSC B-933 MSOG202T
FSCB-911 MSOG201 R
FSCB-911 MSOG20lT
FSC B-902 MSOG20 1T
FSCB-947MSOG20 1T
FSCB-947MSOG20 1T
FSCC-836M50L2AAT
FSCC-836MSO-L2AZT
FSCC-881 M50L2ABT
FSCC-881 M50-L2AYT
FSCC-933MSO-L2BAT
FSCC-878M50-L2BBT
FSCC-888MSO-L2CAT
FSCC-933M50-L2CBT
FSCC-911 M50-L2DAT
FSCC-856M50-L2DBT
FSCC-902M50-L2EAT
FSCC-902M50L2EZT
FSCC-902M50-L2EXT
FSCC-947M50-L2EYT
FSCC-897M50L2KAT
FSCC-942M50-L2KBT
FSCC-942MSO-L2KYT

ORDERING INFORMATION FOR STANDARD PRODUCTS
Part Number

Description

Package Type

Options

Order Number

FAR-F5CC-950MOO-L2FA
FAR-F5CC-820MOO-L2FB
FAR-F5CC-915MOO-L2JA
FAR-F5CC-915MOO-L2JZ
FAR-F5CC-935MOO-L2LA
FAR-F6CC-1 G441 O-L2ZA
FAR-F6CC-1 G4890-L2ZB
FAR-F6CC-1 G6190-L2ZN
FAR-F6CE-1 G7475-L2VA
FAR-F6CE-1 G8425-L2VB
FAR-F6CE-1 G8800-L2XA
FAR-F6CE-1 G9600-L2XB
FAR-F6CE-2G4500-L2WA

PDCSAW
PDCSAW
ISM SAW (US)
ISM SAW (US)
2-WAV PAGER
PDC 1.5GHz
PDC 1.5 GHz
PDC 1.5GHz
DCS 1800
DCS 1800
PCS SAW (US)
PCSSAW(US)
LAN2.4GHz

3.8X3.8 MM
3.8X3.8 MM
3.8X3.8MM
3.8X3.8 MM
3.8X3.8 MM
3.8X3.8MM
3.8X3.8MM
3.8X3.8MM
3X3MM
3X3MM
3X3MM
3X3MM
3X3MM

lKT&R
lKT&R
lKT&R
lKT&R
lKT&R
1KT&R
1KT&R
1KT&R
1KT&R
1KT&R
1KT&R
lKT&R
1KT&R

F5CC-950MOOL2FAT
F5CC-820MOOL2FBT
F5CC-915MOO-L2JAT
F5CC-915MOO-L2JZT
F5CC-935MOOL2LAT
F6CC-1 G441 O-L2ZAT
F6CC-1 G4890-L2ZBT
F6CC-1 G6190-L2ZBT
F6CE-1 G7475-L2VAT
F6CE-l G8425-L2VBT
F6CE-l G8800-L2XAT
F6CE-l G9600-L2XBT
F6CE-2G4500-L2WAT

PWRMGMTSW
PWRMGMTSW

FPT-16P-M04
FPT-16P-M04

POWER MANAGEMENT
MB3802
MB3807A

MB3802PF
MB3807APF

III

11-7

11-8

- - - - - - - - - - - - SECTION 12
Sales Information

If)

12-1

12-2

Introduction to Fujitsu
Fujitsu Limited (Japan)
Fujitsu Limited was founded as a telecommunications equipment manufacturer in
1935, and today is not only one of Japan's leading telecommunications companies,
but also one of the world's largest computer manufacturers.
This leadership has resulted, at least in part, form the superb quality of the company's
semiconductors and electronic components. Manufactured by the company's
Electronics Devices Operations Group, these vital electronic devices also contribute
to the high reliability and performance of products made by many other manufacturers
around the world.
Today, Fujitsu is one of the world's top manufacturers of semiconductors and
electronic components. In Japan, Fujitsu's R&D laboratories for semiconductor and
electronic components are situated in Kawasaki and Mie, and manufacturing works
are located in Iwate, Aizu, Wakamatsu and Suzaka. Fujitsu also has six affiliated
manufacturing works in the country. Overseas facilities in the U.S., Europe, and Asia
also help to meed the growing global demand for Fujitsu semiconductors and
electronic components.
Fujitsu enforces strict quality control at all stages of production, from materials
selection through manufacturing to final testing. As a result, Fujitsu's electronic
devices are known for their extremely high reliability and excellent
cost-fo-performance ratio.
Fujitsu manufactures a full line of semiconductors and electronic components to meet
the diverse applications of am wide variety of customers. Backed by Fujitsu's
extensive R&D commitment equal to over 10 percent of annual sales, Fujitsu's
electronic devices stay on the cutting edge of electronics technology.

12-3

Sales Information

Fujitsu Limited
Japan
FUJITSU LIMITED
Application & Sales
Engineering Dept.
1015, Kamikodanake
Nakahara-ku,
Kawasaki211,Japan
Tel: (044)754-3283
FAX: (044)754-3343

North and South America
FUJITSU
MICROELECTRONICS, INC.
3545 North First Street
San Jose, CA 95134-1804,
USA.
Tel: 1-800-642-7616

Europe
FUJITSU
MIKROELEKTRONIK GmbH
Am Siebenstein 6-10,
63303 Dreieich-Buchschlag,
Germany
Tel: (06103) 690-0
Telex: 411963
FAX: (06103) 690-122

Asia
FUJITSU
MICROELECTRONICS ASIA
PTE LIMITED
#06-04 to #05-07
Plaza By The Park
No. 51 Bras Basah Road
Singapore 0718
Tel: 336-1600
Telex: 55573
FAX: 336-1609

12-4

Wireless Data Book

Sales Information

Wireless Data Book

Fujitsu Microelectronics, Inc. (FMI) Sales Offices
CALIFORNIA

GEORGIA

NEW YORK

Irvine

Atlanta

NewVork

Century Centre
2603 Main Street, Ste. 510
Irvine, CA 92714
Tel: 7141724-8777
FAX: 7141724-8778

3500 Parkway Lane, Ste. 210
Norcross, GA 30092
Tel: 770/449-8539
FAX: 770/441-2016

Hauppauge Office Park
Building 2, Ste. 310
898 Veterans Memorial Hwy
Hauppauge, NY 11788
Tel: 516/582-8700
FAX: 516/582-3855

San Jose
3545 North First Street
San Jose, CA 95134-1804
Tel: 408/922-9000
FAX: 408/432-90441
408/432-9045
HERZING: 408/943-1204

ILLINOIS
Chicago
One Pierce Place, Ste.1245 W.
Itasca, IL 60143-2681
Tel: 708/250-8580
FAX: 708/250-8591

Santa Clara
2880 Lakeside Drive, Ste. 250
Santa Clara, CA 95054
Tel: 408/982-1800
FAX: 408/982-1825

COLORADO

MASSACHUSETTS
Boston
1000 Winter Street, Ste. 2500
Waltham, MA 02154
Tel: 6171487-0029
FAX: 617/890-9002

Denver
12000 North Washington Street,
Ste.370
Thornton, CO 80241
Tel: 3031254-9901
FAX: 303/254-9921

MINNESOTA
Minneapolis
3800 W. 80th Street, 8te. 430
Bloomington, MN 55431-4419
Tel: 6121893-5570
FAX: 6121893-5580

OREGON
Portland
15220 NW Greenbrier Pkwy
Ste.360
Beaverton, OR 97006
Tel: 503/690-1909
FAX: 503/690-8074

TEXAS
Dallas
14785 Preston Road, Ste. 274
Dallas, TX 75240
Tel: 214/233-9394
FAX: 2141386-7917

Houston
Two Chasewood Park, 8te. 250
20405 SH 249
Houston, TX 77070
Tel: 713/379-3030
FAX: 713/379-1059

If)

12-5

Sales Information

Wireless Data Book

FMI Sales Representatives - USA
WESTERN AREA
ARIZONA
Aztech Component Sales. Inc.
15230 N. 75th Street, Ste. 1031
Scottsdale, AZ 85260
6021991-6300
FAX: 6021991-0563

CALIFORNIA
Innflnity Sales Inc.
20 Corporate Park, Ste. 100
Irvine, CA 92714
714/833-0300
FAX: 714/833-0303

6540 Lusk Blvd., Ste. C256
San Diego, CA 92121
619/535-9300
FAX: 619/550-3707
26560 W. Agoura Road,
Suite 103A
Calabasas, CA 91302
818/880-6480

FAX: 818/880-1922

12-6

NORCOMP
1267 Oakmead Parkway
Sunnyvale, CA 94086
408/733-7707
408/774-1947
8880 Wagon Way
Granite Bay, CA 95746
916/791-7776
FAX: 9161791-2223

COLORADO
Spectrum Marketing
2211 West 27th Avenue,
Ste.316
Denver, CO 80211
3031480-9991
FAX: 303/455/5303

2924 Robidoux Road
Sandy, Utah 84093
801/972-8552
FAX: 801/943-9522

IDAHO
Intermountain Technical
Marketing
1310 E. First Street
Meridian,lD 83642
208/888-6071
FAX: 208/888-6074

OREGON
L-Squared Limited
15234 NW Greenbrier Parkway
Beaverton, OR 97006
503/629-8555
FAX: 5031645-6196

10502 Riviera PI. N.E.
Seattle, WA 98125-6937
206/525-8555
FAX: 206/527-0882

Wireless Data Book

Sales Information

FMI Sales Representatives -

USA (continued)

CENTRAL AREA
ILLINOIS

MINNESOTA

TEXAS

Beta Technology
1009 Hawthome Drive
Itasca, IL 60143
708/250-9586
FAX: 708/250-9592

Beta Technology
15612 Highway 7, Suite 320
Minnetonka, MN 55345
6121938-1 006
FAX: 6121938-2209

Technica' Marketing, Inc.
(T.M.I)
3320 Wiley Post Road
Carrollton, TX 75006
2141387-3601
FAX: 2141387·3605
TWX: 910/860-5158

INDIANA
Valentine Associates
1030 Summit Drive
Carmel, IN 46032-2580
317/846-0008
FAX: 317/846-0255

OHIO
Stegman Blaine Marketing
8228 Winton Road, Ste. 3000
Cincinnati, OH 45231
5131729-1969
FAX: 5131729-1984

KENTUCKY

147 W. National Road
Vandalia, OH 45377

Valentine Associates
3215 Brentwood Drive
Henderson, KY 42420

513/890-7975

5021826-9444
FAX: 5021826-9108

MICHIGAN
R.C. Merchant Be Co., Inc.
23735 Research Drive
Farmington Hills, MI 48335
810/476-4600
FAX: 810/476-3162

2901 Wilcrest Drive, Ste. 139
Houston, TX 77042
713/783-4497
FAX: 7131783·5307
TLX: 510/100-9699
3701 Executive Center Drive
Suite 205
Austin, TX 78731

FAX: 5131890-5191

5121343·6976
FAX: 5121343-7986

10539 Shale Brook Way
Cleveland, OH 44136

WISCONSIN

216/572-0003
FAX: 2161238-3229
4347 Stow Road
Stow, OH 44224
216/688-9603
FAX: 216/688-6421

Beta Technology
9401 W. Beloit Street, Ste. 409
Milwaukee, WI 53227

414/543-6609
FAX: 4141543·9288

815 Main Street
St. Joseph, MI 49085

616/983·7378
FAX: 616/983·3506

12-7

Sales Information

Wireless Data Book

FMI Sales Representatives -

USA (continued)

EASTERN AREA
ALABAMA

MARYLAND

NEW YORK

Com Rep, Inc.
190 Lime Quarry Road, Ste. 212
Madison, AL 35758
2051772-9982
FAX: 2051772-8693

Arbotek Asso., Inc.
2408 Peppermill Drive, Ste. I
Glen Burnie, MD 21061
4101768-5335
FAX: 4101768-8118

Quality Components
116 Fayette Street
Manlius, NY 13104
315/682-8885
FAX: 315/682-2277
TWX: 910/997-1313

CONNECTICUT

MASSACHUSETTS

Connecticut Applied
Technology
555 Highland Avenue, Ste. 2
Cheshire, CT 06410
203/272-6564
FAX: 203/271-3670

3D Sales
5 Burlington Woods Drive
Burlington, MA 01803
617/229-2999
FAX: 617/229-2033

716/655·0556
FAX: 716-655-0601
500 Helendale Road, Ste. 125
Rochester, NY 14609
716/288-3420
FAX: 716/288-3484

NEW JERSEY

NORTH CAROLINA

BGR Associates
Evesham Commons
525 Route 73, Ste. 100
Marlton, NJ 08053
609/983-1020
FAX: 609/983-1879
TWX; 710/940-1358

ComRep, Inc.
3125 Poplarwood Court,
Ste.123
Raleigh, NC 27604
919/873-1003
FAX: 919/873-0307

FLORIDA
Semtronic Associates
657 Maitland Avenue
Altamonte Springs, FL 32701
407/831-8233
FAX: 407/831-2844
TLX: 810/854-0321
1467 S. Missouri Avenue
Clearwater, FL 34616
813/461-4675
FAX: 813/442-2234
3471 NW 55th Street
Ft. Lauderdale, FL 33309
305/731-2484
FAX: 3051731-1019

GEORGIA
ComRep, Inc.
6855 Jimmy Carter Blvd.,
Ste.2128
Norcross, GA 30071
770/449-9905
FAX: 770/449-1909

12-8

Technical Applications &
Marketing (T.A.M)
91 Clinton Road, Ste. 1D
Fairfield, NJ 07006
201/575-4130
FAX: 201/575-4563

8206 Providence Road,
Ste.1200-374
Charlotte, NC 28277
704/544-9122
FAX: 704/543-9646

PUERTO RICO
Semtronic Associates
Crown Hills
#125 Carite St.lEsq. Ave.
Parana
Rio Piedras, PR 00926
8091766-0700
FAX: 8091763-8071

Sales Information

Wireless Data Book

FMI Sales Representatives -

Canada

Pipe-Thompson, Ltd.
5468 Dundas Street, W. 206
Islington, Ontario M9B 6E3
4161236·2355
FAX: 416/236·3387
17 Brandy Creek Crescent
Kanata, Ontario K2M 288
613/591·1821
FAX: 613/591·0461

IfJ
12·9

Sales Information

FMI Distributors ALABAMA
Innsight Electronics
4835 University Square, Ste. 19
Huntsville, AL 35816
205-830-1222
FAX: 205-830-1225
Marshall Industries
3313 Memorial Parkway South,
Ste.150
Huntsville, AL 35801
205-881-9235
FAX: 205-881-1490
Milgray Electronics
5021 Bradford Dr., Ste. 202
Huntsville, AL 35805
205-722-8551
FAX: 205-722-0161

ARIZONA
Innsight Electronics
1515 West University Drive,
Ste.103
Tempe, AZ 85281
602-829-1800
FAX: 602-967-2658
Marshall Industries
9831 S. 51st St., Ste. C107-109
Phoenix, AZ 85044
602-496-0290
FAX: 602-893-9029

CALIFORNIA
Bell Mlcroproducts
30 Fairbanks, Ste. 114
Irvine, CA 92718
714-470-2900
FAX: 714-470-2929
1941 Ringwood Avenue
San Jose, CA 95131-1721
408-451-9400
FAX: 408-451-1600
860-H Hampshire
Westlake Village, CA 91362
805-496-2606
FAX: 805-496-6119

12-10

Wireless Data Book

USA
Insight Electronics
2 Venture Plaza, Ste. 340
Irvine, CA 92718
714-727-3291
FAX: 714-727-1804

Milgray Electronics
25 Mauchly, Ste. 329
Irvine, CA 92718
714-753-1282
FAX: 714-753-1682

9980 Huennekens Street
San Diego, CA 92121
619-587-1100
FAX: 619-587-1380

6835 Flanders Drive, Ste. 300
San Diego, CA 92121
619-457-7545
FAX: 619-457-9750

1295 Oakmead Parkway
Sunnyvale, CA 94086
408-720-9222
FAX: 408-720-8390

2860 Zanker Road, Ste. 209
San Jose, CA 95134
408-456-0900
FAX: 408-456-0300

4333 Pari< Terrace Drive,
Ste.101
Westlake Village, CA 91361
818-707-2101
FAX: 818-707-0321

275 E. Hillcrest Drive, Ste. 145
Thousand Oaks, CA 91360
805-371-9399
FAX: 805-371-9317

Marshall Industries
26637 W. Agoura Road
Calabasas, CA 91302-1959
818-878-7000
FAX: 818-880-6846
9320 Telstar Avenue
EI Monte, CA 91731
818-307-6000
FAX: 818-307-6297
One Morgan Drive
Irvine, CA 92718
714-458-5365
FAX: 714-581-5255
336 Los Caches Street
Milpitas, CA 95035
408-942-4600
FAX: 408-942-4722
3039 Kilgore Avenue, Ste. 140
Rancho Cordova, CA 95670
916-635-9700
FAX: 916-635-6044
5961 Kearny Villa Road
San Diego, CA 92123
619-627-4140
FAX: 619-627-4163

5650 0 T C Parkway, Ste. 202
Englewood, CA 80111
303-721-7702
FAX: 303-721-7803

COLORADO
Insight Electronics
384 Inverness Drive South,
Ste.105
Englewood, CO 80112
303-649-1800
303-649-1818
Marshall Industries
12351 North Grant Street, Ste. A
Thornton, CO 80111
303-451-8383
FAX: 303-457-2899

CONNECTICUT
Milgray Electronics
326 West Main Street
Milford, CT 06460-0418
203-878-5538
FAX: 203-878-6970
Marshall Industries
Barnes Industrial Park North,
20 Sterling Dr.
Wallingford, CT 06492
203-265-3822
FAX: 203-284-9285

Wireless Data Book

FMI Distributors -

Sales Information

USA (continued)

FLORIDA

GEORGIA

KANSAS

BelWantage
1110 Douglas Avenue, Ste. 2050
Altamonte Springs, FL 32714
407-542-3083
FAX: 407-682-1286

Insight Electronics
3005 Breckinridge Blvd.,
Ste.210-A
Duluth, GA 30136
404-717-8566
404-717-8588

Marshall Industries
10413 W. 84th Terrace
Lenexa, KS 66214
913-492-3121
FAX: 913-492-6205

1761 West Hillsboro Blvd.,
Ste.208
Deerfield Beach, FL 33441
305-429-1001
FAX: 305-481-3586
Insight Electronics
600 North Lake Road, Ste. 250
Altamonte Springs, FL 32701
407-834-6310
FAX: 407-834-6461

Marshall Industries
5300 Oakbrook Parkway,
Ste.14O
Norcross, GA 30093
404-923-5750
FAX: 404-923-2743

ILLINOIS

6400 Congress Avenue,
Ste.1600
Boca Raton, FL 33487
407-997-2540
FAX: 407-997-2542

Insight Electronics
1365 Wiley Road, Ste. 142
Schaumburg, IL 60173
708-885-9700
FAX: 708-885-9701

17757 U.S. Hwy 19 North,
Ste.520
Clearwater, FL 34624
813-524-8850
FAX: 813-532-4245

Marshall Industries
50 East Commerce Drive, Unit A
Schaumburg, IL 60173
708-490-0155
FAX: 708-490-0569

Marshall Industries
380 South Northlake Blvd.,
Ste.1024
Altamonte Springs, FL 32701
407-767-8585
FAX: 407-767-8676

Milgray Electronics
1530 East Dundee Road,
Ste.250
Palatine, IL 60067-8319
708-202-1900
FAX: 708-202-1985

2700 W. Cypress Creek Road,
Ste.D114
Ft. Lauderdale, FL 33309
305-977-4880
FAX: 305-977-4887
2840 Scherer Drive, Ste. 410
St. Petersberg, FL 33716
813-573-1399
813-573-0069
Milgray Electronics
755 Rinehart Road, Ste. 100
Lake Mary, FL 32746
407-321-2555
FAX: 407-322-4225

INDIANA
Marshal/Industries
14027 Sedona Court
Indianapolis, IN 46032
317-388-9069
FAX: 317-297-2787

Milgray Electronics
6400 Glenwood, Ste. 313
Overland Park, KS 66202-4021
913-236-8800
FAX: 913-384-6825

MASSACHUSETTS
BelWantage
17A Sterling Road
Billerica, MA 01862
508-667-2400
FAX: 508-663-7474
Insight Electronics
55 Cambridge Street, Ste. 301
Burlington, MA 01803
617-270-9400
FAX: 617-270-3279
Interface Electronics·
228 South Street
Hopkinton, MA 01748
508-435-0100
FAX: 508-435-6516
Marshal/Industries
33 Upton Drive
Wilmington, MA 01887
508-657-9024
FAX: 508-658-7608
Milgray Electronics
187 Ballardvale Street
Wilmington, MA 01887-1046
508-657-5900
FAX: 508-658-7989

Mligray Electronics
5226 Elmwood Ave
Indianapolis. IN 46023
317-781-9997
FAX: 317-781-6970

12-11

Sales Information

FMI Distributors -

USA (continued)

MARYLAND

NORTH CAROLINA

NEW YORK

BellNantage
6925 R Oakland Mills Road
Columbia, MD 21045
410-720-5100
FAX: 410-381-2172

Marshall Industries
5224 Greens Dairy Road
Raleigh, NC 27604
919-878-9882
FAX: 919-872-2431

BellNantage
1056 West Jericho Turnpike
Smithtown, NY 11787
516-543-2000
FAX: 516-543-2030

Insight Electronics
6925 Oakland Mills Road, Ste. D
Columbia, MD 21045
410-381-3131
FAX: 410-381-3141

Milgray Electronics
2925 Huntleigh Drive, Ste. 101
Raleigh, NC 27604-3374
919-790-8094
FAX: 919-872-8851

Marshall Industries
100 Marshall Drive
Endicott, NY 13760
607-785-2345
FAX: 607-785-5546

Marshall Industries
9130B Guilford Road
Columbia, MD 21046
410-880-3030
FAX: 410-880-3202
Milgray Electronics
6460 Dobbin Road, Ste. D
Columbia, MD 21045-5813
410-730-6119
FAX: 410-730-8940

MICHIGAN
Marshall Industries
31067 Schoolcraft Road
Livonia, MI48150
313-525-5850
FAX: 313-525-5855

MINNESOTA
Marshall Industries
14800 28th Avenue North,
Ste.175
Plymouth, MN 55447
612-559-2211
FAX: 612-559-8321
rnsight Electronics
5353 Gamble Drive, Ste. 330
St. Louis Park, MN 55416
612-525-9999
FAX: 612-525-9998

MISSOURI
Marshall Industries
514 Earth City Expressway,
Ste.131
Earth City, MO 63045
314-770-1749
FAX: 314-770-1486

12-12

Wireless Data Book

NEW JERSEY
BellNantage*
23 Sebago Street
Clifton, NJ 07013
201-777-4100
FAX: 201-777-6194
Insight Electronics
2 Eves Drive, Ste. 208
Marlton, NJ 08053
609 985-5556
FAX: 609-985-5895
Interface Electronics
1 Greentree Center, Ste. 201
Marlton, NJ 08053
609-988-5448
FAX: 609-988-5566
Marshall Industries
101 Fairfield Road
Fairfield, NJ 07004
201-882-0320
FAX: 201-882-0095
158 Gaither Drive #100
Mt. Laurel, NJ 08054
609-234-9100
FAX: 609-778-1819
Milgray Electronics
3001 Greentree Executive
Campus, Ste. C
Marlton, NJ 08053-1551
609-983-5010
FAX: 609-985-1607
3799 Route 46 East, Ste. 303
Parsippany, NJ 07054-1273
201-335-1766
FAX: 201-335-2110

1250 Scottsville Road
Rochester, NY 14624
716-235-7620
FAX: 716-235-0052
Milgray Electronics
77 Schmitt Boulevard
Farmingdale, NY 11735-1410
516-420-9800
FAX: 516-420-9884
1170 Pittsford-Victor Road,
Ste.200
Pittsford, NY 14534-3807
716-381-9700
FAX: 716-381-9495

OHIO
Insight Electronics
9700 Rockside Road, Ste. 105
Valley View, OH 44125
216-520-4333
FAX: 216-520-4322
Marshall Industries
3520 Park Center Drive
Dayton. OH 45414
513-898-4480
FAX: 513-898-9835
30700 Bainbridge Road, Unit A
Solon, OH 44139
216-248-1788
FAX: 216-248-2312
Milgray Electronics
6155 Rockside Road, Ste. 206
Cleveland, OH 44131-2289
216-447-1520
FAX: 216-447-1761

Wireless Data Book

FMI Distributors OREGON
Insight Electronics
8705 S.W. Nimbus Avenue,
Ste.200
Beaverton, OR 97005
503-626-3031
FAX: 503-641-4530

Marshall Industries
9705 S.W. Gemini Drive
Beaverton, OR 97005
503-644-5050
FAX: 503-646-8256

Milgray Electronics
8705 S.W. Nimbus, Ste. 260
Beaverton, OR 97008
503-626-4040
FAX: 503-641-0650

TEXAS
Bell Microproducts
12701B Research Blvd.,
Ste.301
Austin, TX 78759
512-258-0725
FAX: 512-258-6512
1202 Executive Drive West
Richardson, TX 75081
214-783-4191
FAX: 214-783-4192

Insight Electronics
11500 Metric Blvd., Ste. 215
Austin, TX 78758
512-719-3090
FAX: 512-719-3091
10777 Westheimer, Ste. 1100
Houston, TX 77042
713-260-9614
FAX: 713-260-9602
1778 N. Plano Road, Ste. 320
Richardson, TX 75081
214-783-0800
FAX: 214-680-2402

Sales Information

USA (continued)
Marshall Industries
8504 Cross Park Drive
Austin, TX 78754
512-837-1991
FAX: 512-832-9810
10681 Haddington Drive,
Ste.160
Houston, TX 77043
713-467-1666
FAX: 713-467-9805
1551 N. Glenville Drive
Richardson, TX 75081
214-705-0600
FAX: 214-705-0675

Milgray Electronics
11824 Jollyville Road, Ste. 103
Austin, TX 78759
512-331-9961
FAX: 512-331-1070
16610 N. Dallas Parkway,
Ste.1300
Dallas, TX 75248-2617
214-248-1603
FAX: 214-248-0218
12919 SW Freeway, Ste. 130
Stafford, TX 77477-4113
713-240-5360
FAX: 713-240-5404

WASHINGTON
Marshal/Industries
11715 North Creek Pkwy. South,
Ste.112
Bothell, WA 98011
206-486-5747
FAX: 206-486-6964

Insight Electronics
12002 115th Avenue, N.E.
Kirkland, WA 98034
206-820-8100
FAX: 206-821-2976

WISCONSIN
Marshal/Industries
20900 Swenson Drive, Ste. 150
Waukesha, WI 53186
414-797-8400
FAX: 414-797-8270

Insight Electronics
10855 W. Potter Road
Wauwatosa, WI 53222
414-258-5338
FAX: 414-258-5360

UTAH
Milgray Electronics
310 East 4500 South, Ste. 110
Murray, UT 84107
801-261-2999
FAX: 801-261-0880

Marshal/Industries
2355 South 1070 West, Ste. D
Salt Lake City, UTY 84119
801-973-2288
FAX: 801-973-2296

12-13

Sales Information

FMI Distributors -

Canada

ALBERTA

ONTARIO

QUEBEC

Active Components
3833-29th Street NE
Calgary, Alberta, Canada
T1Y 6B5
403-250-5550
FAX: 403-291-7054

Active Components
5935 Airport Road, Ste. 200
Mississauga, Ontario, Canada
L4V 1W5
905-612-9200
FAX: 905-612-9185

Active Components
237 Hymus Boulevard
Pointe Claire, Quebec, Canada
H9R 5C7
514-694-7710
FAX: 514-695-3707

4606 97th Street
Edmonton, Alberta, Canada
T6E 5N9
403-438-2858
FAX: 604-434-0812

Baxter Center, 1050 Baxter Rd.
Ottawa, Ontario, Canada
K2C3P2
613-820-8313
FAX: 613-820-3271

1000 Ave. St.Jean Baptiste,
Ste.l00
Quebec,Quebec,Canada
G2E5G5
418-877-6666
FAX: 418-877-6671

BRITISH COLUMBIA
Active Components
1695 Boundary Road
Vancouver, B.C., Canada
V5K4X7
604-294-1166
FAX: 604-294-1206

MANITOBA
Active Components
106 King Edward St. East
Winnipeg, Manitoba, Canada
R3H ON8
204-944-1446
FAX: 204-783-8133

12-14

Wireless Data Book

Marshall Industries
6285 Northam Drive, Ste. 112
Mississauga, Ontario, Canada
L4V 1X5
905-612-1771
FAX: 905-612-1988

Milgray Electronics
2783 Thamesgate Drive
Mississagua, Ontario, Canada
L4T lG5
905-678-0958
FAX: 905-678-1213

Marshall Industries
148 Brunswick Boulevard
Pointe Claire, Quebec, Canada
H9R 59P
514-694-8142
FAX: 514-694-6989

Mligray Electronics
6600 Trans Canada Hwy,
Ste.209
Pointe Claire, Quebec, Canada
H9R 4S2
514-426-5900
FAX: 514-426-5836

- - - - - - - - - - - SECTION 13
Glossary

13-1

13-2

Wireless Communications Glossary

This section contains definitions for terms and phrases which are commonly used in discussions of wireless communications.
On the next page, we include a list of acronyms which are associated with wireless communications, as welf as acronyms which are
specific to Fujitsu's corporate structure or wireless product line. Following the list of acronyms is the definitions portion of the glossary.

13-3

AGC

Automatic Gain Control

FM

Frequency Modulation

AM

Amplitude Modulation

FMG

Fujitsu Microelectronics, GmbH

AMPS

Advanced Mobile Phone System

FMI

Fujitsu Microelectronics, Inc.

ANSI

American National Standards Institute

FML

Fujitsu Microelectronics, Ltd.

ASIC

Application-Specific Integrated Circuit

FNI

Fujitsu Networks Industry, Inc.

ASK

Amplitude Shift Keying

FNSA

Fujitsu Network Switching of America, Inc.

BiCMOS

Bipolar/Complementary Metal Oxide
Semiconductor

FNTS

Fujitsu Network Transmission Systems, Inc.

B-PCS

Frequency Shift Keying

GFSK

Gaussian Frequency Shift Keying

CAGR

Compound Annual Growth Rate

GHz

Gigahertz

COMA

Code Division Multiple Access

GMSK

Gaussian Minimum Shift Keying

CMOS

Complementary Metal Oxide
Semiconductor

GPS

Global Positioning Satellite System

GSM

Global System for Mobile Communications
(also known as Groupe Speciale Mobile)
Intermediate Frequency

CODEC

Coder/Decoder

CT1

Cordless Telephone - First Generation

IF

Cordless Telephone - Second Generation

IS-54

Interim Standard Number 54

CTIA

Cellular Telephone Industry Association

15-95

Interim Standard Number 95

DBS

Direct Broadcast Satellite

15-136

Interim Standard Number 136

DCS1800

Digital Communication Service at
1800 MHz

ISM

Industrial, Scientific, and Medical

JDC

Japanese Digital Cellular

Digital European Cordless Telephone

CT2

13-4

Broadband Personal Communications
Systems

FSK

DECT
DQPSK

kHz

Kilohertz

Differential Quadrature Phase Shift Keying

LAN

Local Area Network

DSP

Digital Signal Processing

LiTa03

Lithium Tantalate

DSSS

Direct Sequence Spread Spectrum

LNA

Low Noise Amplifier

ESPER

Emitter-Base Self-Aligned Polysilicon
Electrode and Resistor

LO

Local Oscillator

ETACS

Enhanced Total Access Communications
System

MCM

Multi-Chip Module

MHz

Megahertz

NF

Noise Figure

NMT

Nordic Mobile Telephone

N-PCS

Narrowband Personal Communications
Systems

ETSI

European Telecommunication Standards
Inst.

FAI

Fujitsu America, Inc.

FBCS

Fujitsu Business Communication Sys., Inc.

FCC

Federal Communications Commission

PA

Power Amplifier

FCPA

Fujitsu Computer Products of America, Inc.

PBX

Private Business Exchange

FCPT

Fujitsu Computer Packaging Tech., Inc.

PC

Personal Computer

FCSI

Fujitsu Compound Semiconductor, Inc.

PCB

Printed Circuit Board

FDD

Frequency Division Duplexing

PCMCIA

PC Memory Card Interface Association

FDMA

Frequency Division Multiple Access

PCN

Personal Communications Network

FHSS

Frequency Hopping Spread Spectrum

PCS

Personal Communications System

FJ

Fujitsu Japan

PHS

Personal Handiphone System

PLL

Phase Lock Loop

SAW
SMR
TACS
TOO
TOMA
U-PCS

PM

Phase Modulation

PQFP

Plastic Quad Flat Pack

PSK

Phase Shift Keying

QAM

Quadrature Amplitude Modulation

QFP

Quad Flat Pack

QPSK

Quadrature Phase Shift Keying

veo

Voltage Controlled Oscillator

R&D

Research and Development
Radio Frequency

WAN
WLAN

Wide Area Network

RF

Surface Acoustic Wave
Specialized Mobile Radio
Total Access Communications System
Time Division Duplexing
Time Division Multiple Access
Unlicensed Personal Communications
Systems

Wireless Local Area Network

III
13·5

13-6

Terms and Phrases Associated with Wireless
Advanced Mobile Phone Service (AMPS)
The standard for analog cellular telephone service in the United States.

Amplitude Modulation (AM)
A method of analog modulation where the input data signal is used to vary the amplitude of the carrier.

Amplitude Shift Keying (ASK)
A method of digital modulation where the digital input data signal is used to vary the amplitude of the carrier. Very popular with
remote car alarm applications.

Antenna
A device which converts electromagnetic radiation in the form of radio waves into an electrical signal, and vice versa.

Baseband controller
A CMOS or BiCMOS circuit which controls the operation of the analog sections of the radio. The baseband controller acts as
the interface between the analog portion of the radio and the digital data and control functions. It is often an ASIC
implementation.

Broadband Personal Communication Service (B-PCS)
A standard under development in the United States to provide digital wireless service in a manner similar to cellular telephony,
in that the service will be available from infrastructure developed and operated by third-party companies. The system will
provide wireless voice, data, and eventually video communication capability.

Cellular telephony
A wireless telephone service which allows a user to make and receive calls while driving, walking, or remaining stationary. This
is accomplished via an infrastructure which has a number of base station antenna sites arrayed in such a way to create a
number of individual 'cells' which cover a specified geographic area. The infrastructure allows users to move from cell to cell
during a call by transferring the radio connection to the user's cellular telephone from one base station to another. This
infrastructure is established by a third party, and a user must subscribe to the service and pay both monthly and air time
charges to access the infrastructure.

Charge pump
A component of a phase lock loop system which produces pulses of electrical current. The polarity of the current and the time
duration of the pulse are controlled by the phase detector. The output of charge pump serves as the input to the loop filter of
a PLL system.

a

Code Divided Multiple Access (COMA)
A type of multiplexing for wireless systems ~eveloped by Qualcomm which uses spread spectrum techniques to allow many
users to share the same frequency bands simultaneously.

Compression point (P1 dB)
The maximum input signal strength that an amplifier can amplify in a linear manner.

Conversion gain
A measure of the gain of a mixer, measured from the signal input port to the output port.

Cordless Telephone - Second Generation (CT2)
A digital cordless telephone standard developed in France and Britain for residential and office use. Also very popular in Hong
Kong and other Far East countries.

Cordless telephony
A cordless telephone is a device which serves the same basic function as an ordinary telephone, but without the restriction of a
cord. They have a limited range of service, and are intended for use in and around the home. Cordless telephones do not
require third party infrastructure or subscriber tees.

Differential Quadrature Phase Shift Keying (DQPSK)
A modified form of quadrature phase shift keying which offers a slight improvement in performance.

III

Digital Communications Service at 1800 MHz (DCS-1800)
A modification of the GSM protocol to allow operation at 1800 MHz for European PCS applications.

13-7

Terms and Phrases Associated with Wireless (Continued)
Digital Communications Service at 1900 MHz (DCS-1900)
A modification of the GSM protocol to allow operation at 1900 MHz. This is one of several proposed standards for broadband
PCS and unlicensed PCS in the United States.
Digital European Cordless Telephone (DECT)
A standard for digital cordless telephones which is adopted throughout Europe. Originally designed for office applications, it has
voice and data capability inherent to the standard. It is now becoming more common for residential use as well.
Direct Conversion Receiver
A radio receiver architecture where the local oscillator frequency is set equal to the carrier frequency of the signal of interest.
This produces an output Signal which is centered at 0 Hz, which means that the signal is directly converted to its baseband
representation. This architecture is used most commonly in pagers. Also known as a homodyne receiver.
Dual Conversion Receiver
A radio receiver architecture which uses two frequency conversions (via two separate mixer/Jocal oscillator combinations). Dual
conversion receivers generally give superior performance, but at the expense of extra component count and cost. Also known
as a dual superheterodyne receiver.
. Dual modulus prescaler
A prescaler which has two distinct divide ratios. The choice of divide ratio is determined by a control input to the prescaler
which is generated by the swallow counter of a PLL IC.
Duplexer
A device which is used in systems which utilize frequency division duplexing. It consists of two filters, one for the frequencies
used for the received radio signals, and one for the frequencies used for the transmitted radio signals. The duplexer provides
the receiver with isolation from interference from the transmitter for radio systems which use the same antenna for both transmit
and receive.
Duplexing
The rules which determine how two radios transmit and receive signals to each other.
Dynamic Range
The range of input Signal strength that a radio receiver can detect properly. It is bounded on the low end by the noise of the
receiver, and on the high end by the distortion and nonlinearity of the receiver.
Frequency Division Duplexing (FDD)
A method of duplexing where a radio transmits on one carrier frequency, and receives on another frequency, so that the
transmission and reception do not interfere with each other.
Frequency Division Multiple Access (FDMA)
A type of multiplexing for wireless systems where each radio conversation is assigned a unique carrier frequency exclusively
for their use.
Frequency Modulation (FM)
A method of analog modulation where the input data signal is used to vary the frequency of the carrier.
Frequency Shift Keying (FSK)
A method of digital modulation where the frequency of the carrier alternates between two or more discrete frequencies based
on the state of the digital input data signal. It is relatively easy and inexpensive to implement, but it has poor spectral efficiency.
Gain
The ratio of the signal strength at the output of a device to the signal strength at its input.
Gaussian Minimum Shift Keying (GMSK)
This is a special, tightly controlled version of frequency shift keying modulation designed for better spectral efficiency. It is the
modulation method used for GSM and its derivatives.
Global System for Mobile Communications (GSM)
A standard for digital cellular telephone service which was originally developed for use in Europe. GSM is now being adopted
as the digital cellular standard in many areas of the world, with the exception of Japan and the United States.

13·8

Terms and Phrases Associated with Wireless (Continued)
Low noise amplifier (LNA)
An amplifier used at the input of radio receivers which amplifies the radio frequency signals. LNAs are designed so that they
add the smallest possible amount of noise to the received radio signal.
Messaging
A service which is functionally equivalent to wireless electronic mail. Moderate length text messages can be sent and re~eived
from a portable device, such as a personal digital assistant.
Mixer
A device which multiplies two input signals together. It is used in conjunction with a local oscillator to perfonn frequency
translations on radio signals.
Multiplexing
The means by which wireless communication systems accommodate many users simultaneously.
Narrowband Advanced Mobile Phone Service (N-AMPS)
A modification to the AMPS cellular telephone standard in the United States which reduces the bandwidth of a frequency
channel by a factor of three, thus increasing the capacity of a cellular system threefold.
Narrowband Personal Communication Service (N-PCS)
A standard which is being deployed in the United States which provides advanced digital messaging services, such as 2-way
paging.
Noise
Random electrical signals which are generated in all electrical circuits. Excessive levels of noise prevent radios from detecting
input signals with low signal strengths.
Noise Figure (NF)
A measure of the amount of noise that an amplifier or mixer adds to the input signal.
Nordic Mobile Telephone (NMT)
One of the first analog cellular systems developed, now in use in Norway, Sweden, Finland, and a number of other countries.
Paging
A basic form of wireless communication which allows a user to be notified, via a beeping sound from a small radio receiver
known as a pager, that someone is trying to contact them. More sophisticated paging products have an alphanumeric display
which allows small text messages to be sent to the user. Conventional pagers are receive-only devices, and do not contain a
transmitter of any kind.
Passband
The input signal frequencies which a filter allows to pass through to its output.
Personal Communications Network (PCN)
see Personal Communications System
Personal Communications System (PCS)
A generic cfassification of digital wireless communications services which are under development in both the United States,
Europe, and Japan. PCS is envisioned as a means to provide a ubiquitous ~nytime, anywhere~ communication service for
voice, data, messaging! paging, and eventually compressed video.
Phase detector
A component of a phase lock loop system which compares the relative placement in time of the positive edges of its two input
signals. The results of this comparison are used to control the charge pump of a PLL system.
Phase lock loop (PLL)
A circuit which generates an output signal whose phase and frequency characteristics are controlled by an input reference
signal. A basic PLL system consists of a reference signal, a phase detector, a charge pump, a loop filter, and a voltage
controlled oscillator (VCO). Almost all PLL systems also include programmable counters and prescalers which allow the output
frequency of the PLL to be set to a non-integer multiple of the reference signal.

•

In integrated circuit terms, a PLL refers to the integration of the phase detector, charge pump, programmable counters, and in
some cases the prescaler, onto one IC. This is also known as a synthesizer.

13·9

Terms and Phrases Associated with Wireless (Continued)
Harmonics
Signals at frequencies which are integer muHiples of the frequency of a sinusoidal signal. Harmonics are caused by
nonlinearities in amplifiers and mixers which distort the fundamental signals.
Homodyne Receiver
see Direct Conversion Receiver
IF filter
A filter which is used on radio signals which have been converted down to an intermediate frequency. The IF filter has a
passband width equal to the bandwidth of an individual frequency channel for the application. The IF filter selects which
frequency channel will be demodulated by the radio.
Image filter.
A filter used at the input of radio receivers which allows only the relevant frequencies for that application to pass through. and
rejects all other frequencies.
Industrial, Sci~ntlflc, and Medical (ISM)
Radio frequency bands available in the United States and some parts of Europe for unlicensed radio operation. The ISM bands
are commonly used for digital cordless telephones and wireless local area networks (WLANs). Most applications using the ISM
bands utilize spread spectrum techniques. The three ISM bands available in the US are 902-928 MHz, 2.4-2.483 GHz, and
5.725-5.85 GHz.
Insertion loss
A measure of how much signal strength is lost on signals within the passband of a filter.
Interim Standard 54 (15-54)
see Interim Standard 136.
Interim Standard 95 (IS-95)
One of two competing standards for digital cellular telephone service in the United States. This standard specifies the use of
code division multiple access (COMA) as the method of multiplexing. This standard was Originally developed by Qualcomm.
Interim Standard 136 (IS-136)
One of two competing standards for digital cellular telephone service in the United States. This standard. formerly known as
IS-54, specifies the use of time division multiple access (TOMA) as the method of multiplexing. This standard was originally
developed by a consortium of cellular service providers and equipment manufacturers led by Motorola.
Intermediate frequency (IF)
The frequency that the high frequency radio signal is translated to by the mixer and local oscillator.
Interstage filter
An interstage filter is used to filter signals between stages of a power amplifier. They are used to filter out any harmonics which
may be generated by distortions in the power amplifier.
Japanese Digital Cellular (JDC)
The standard for digital cellular telephones in Japan. Also known as RCR-27.
Local oscillator (LO)
A pure sinusoidal signal which is used in conjunction with a mixer to perform precise frequency translations on radio signals.
The local oscillator signal is often generated by using a voltage controlled oscillator (VCO) which is controlled by a phase lock
loop (PLL). The tuning of a radio to a specific frequency channel is accomplished by setting the frequency of the LO to an
appropriate value.
Lock time
The time that a phase lock loop takes to change its output frequency and have it become locked to the reference Signal.
Loop bandwidth
A measure of how quickly a phase lock loop responds to keep its output signal locked to the reference signal.
Loop filter
A component of a phase lock loop system which converts the pulses of electrical current from the output of the charge pump
into a voltage which is used as the input to a voltage controlled oscillator.

13·10

Terms and Phrases Associated with Wireless (Continued)
Phase noise
A measure of how much a fixed frequency oscillator signal varies in frequency due to the effects of random noise in the
oscillator circuit.

Power amplifier (PA)
This device takes a modulated transmit signal at the RF frequency and amplifies it to a level which is appropriate to drive the
antenna. It is often implemented as a series of amplifier stages.

Prescaler
A device which takes the high frequency output signal from a VCO and divides the frequency down to a value which can be
used as an input to the program counter divider portion of a PLL.

Program counter (N-counter)
A component of a phase lock loop system which divides the output frequency of the voltage controlled oscillator, usually after it
has already been divided by a prescaler, before presenting it as an input to the phase detector. The amount of frequency
division performed by the program counter can be altered by programming the counter with a different value, which will result in
a course change in the output frequency of the PLL system.

Quadrature Amplitude Modulation (QAM)
A complex method of digital modulation where the input data signal controls both the amplitude and phase of the carrier. It is
difficult and expensive to implement, but is one of the most spectrally efficient form of modulation.

Quadrature modulator
A device which is used in radios which utilize complex digital modulation techniques such as QPSK and QAM. It takes a local
oscillator signal and splits it into two components, identical in frequency but separated in phase by 90 degrees. These two
signals are then modulated by two separate input signals (the I and Q data signals), and the resulting modulated signals are
then combined into one signal and fed into a mixer to be upconverted in frequency to the proper RF frequency.

Quadrature Phase Shift Keying (QPSK)
A method of digital modulation where the phase of the carrier takes on one of four possible values, corresponding to the state
of two digital input data bits which control the modulation. It is a popular form of modulation because it represents a good
compromise of ease of implementation and spectral efficiency.

Reference counter (R-counter)
A component of a phase lock loop system which divides the frequency of the reference signal before presenting it as an input
to the phase detector. Changing the value that is stored in the reference counter results in a change in the size of the frequency
steps that the PLL output frequency can make.

Reference Signal
The external signal used by a phase lock loop system as the reference from which the output signal of the PLL is derived.

Spec::ialized Mobile Radio
Private, licensed mobile radio networks commonly used for dispatching services for taxis, delivery companies, etc.

Spectral Efficiency
A measure of the data rate which can be sent per 1 Hz of bandwidth. Units are in bits per second per Hz (bps/Hz). The greater
the spectral efficiency, the greater the channel capacity.

Spread spec::trum
A technique developed for military communications which essentially "spreads· a narrow bandwidth radio signal over a wide
frequency band in order to make the signal less susceptible to interference. It is also used to improve the security of a wireless
data transmission, as it is difficult to intercept.

Spurious Signals, spuril
Unwanted signals at frequencfes other than the desired frequency. Spurii result from the operation of a phase lock loop (due to
the inherent operation of the phase detector), and from unwanted mixer output signals.

Stopband
The input signal frequencies which a filter prevents from passing through to its output.

13-11

Terms and Phrases Associated with Wireless (Continued)
Swallow counter (A-counter)

•

A component of a phase lock loop system which works in conjunction with the program counter to control the divide ratio of a
dual modulus prescaler. Changing the value programmed in the swallow counter will result in a fine change in the output
frequency of the PLL system.

Synthesizer
A common term for an phase lock loop integrated circuit.

Time Division Duplexing (TDD)
A method of duplexing where a radio transmits and receives on the same carrier frequency. but at different times. so that the
transmission and reception do not interfere with each other.

Time Division Multiple Access (TDMA)
A type of multiplexing for wireless systems where multiple radios use the same carrier frequency. but only in certain specified
timeslots. so that no two radios use the same carrier frequency at the same time.

Time Division Duplexing (TDD)
A method of duplexing where a radio transmits and receives on the same carrier frequency. but at different times. so that the
transmission and reception do not interfere with each other.

Unlicensed Personal Communication Service (U-PCS)
A standard under development in the United States to provide digital wireless service in a manner similar to cordless telephony.
in that the service will not require access to third-party infrastructure.

Voltage controlled oscillator (VCO)
A device which produces a sinusoidal output signal. The frequency of the output signal is controlled by a voltage at the input to
the device.

Wireless Local Area Network (WLAN)
A computer network which allows the transfer of data and the ability to share resources without the need to physically connect
each node with wires. Popular with users of portable computers. and in environments where it is impractical to install a wired

LAN.

13-12

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Introduction and Quick Selection Guide
Prescalers
CMOS Phase-Locked Loops (PLLs)
Super PLLs (Single Chip PLLs/Prescalers)
Super Analog RF Devices
BiCMOS LSI RF Integrated Circuits
Piezoelectric Devices/SAW Filters
Power Management Switches
Application Notes and Articles
Quality and Reliability
Ordering Information
Sales Information
Glossary

FUJITSU MICROELECTRONICS, INC.
3545 North First Street
San Jose, California 95134-1804
1-800-642-7616
See the list of sales offices inside this data book.

cp-TC-DB-10007-10/95
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